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-rw-r--r--arch/arm/Kconfig20
-rw-r--r--arch/arm/Makefile2
-rw-r--r--arch/arm/configs/exynos4_defconfig70
-rw-r--r--arch/arm/configs/kirkwood_defconfig1
-rw-r--r--arch/arm/configs/mx51_defconfig2
-rw-r--r--arch/arm/configs/s5p64x0_defconfig2
-rw-r--r--arch/arm/configs/s5pv210_defconfig2
-rw-r--r--arch/arm/include/asm/kexec.h3
-rw-r--r--arch/arm/include/asm/pmu.h14
-rw-r--r--arch/arm/kernel/machine_kexec.c7
-rw-r--r--arch/arm/kernel/perf_event.c17
-rw-r--r--arch/arm/mach-davinci/board-da830-evm.c67
-rw-r--r--arch/arm/mach-davinci/board-da850-evm.c96
-rw-r--r--arch/arm/mach-davinci/board-dm644x-evm.c8
-rw-r--r--arch/arm/mach-davinci/board-mityomapl138.c167
-rw-r--r--arch/arm/mach-davinci/board-omapl138-hawk.c284
-rw-r--r--arch/arm/mach-davinci/board-tnetv107x-evm.c57
-rw-r--r--arch/arm/mach-davinci/da830.c6
-rw-r--r--arch/arm/mach-davinci/da850.c99
-rw-r--r--arch/arm/mach-davinci/devices-da8xx.c125
-rw-r--r--arch/arm/mach-davinci/devices-tnetv107x.c25
-rw-r--r--arch/arm/mach-davinci/dm355.c5
-rw-r--r--arch/arm/mach-davinci/dm365.c5
-rw-r--r--arch/arm/mach-davinci/include/mach/da8xx.h11
-rw-r--r--arch/arm/mach-davinci/include/mach/edma.h36
-rw-r--r--arch/arm/mach-davinci/include/mach/mux.h4
-rw-r--r--arch/arm/mach-davinci/include/mach/psc.h2
-rw-r--r--arch/arm/mach-davinci/include/mach/spi.h15
-rw-r--r--arch/arm/mach-davinci/include/mach/tnetv107x.h2
-rw-r--r--arch/arm/mach-davinci/tnetv107x.c2
-rw-r--r--arch/arm/mach-dove/cm-a510.c1
-rw-r--r--arch/arm/mach-dove/common.c8
-rw-r--r--arch/arm/mach-dove/common.h1
-rw-r--r--arch/arm/mach-dove/dove-db-setup.c1
-rw-r--r--arch/arm/mach-dove/include/mach/bridge-regs.h4
-rw-r--r--arch/arm/mach-dove/include/mach/dove.h3
-rw-r--r--arch/arm/mach-dove/include/mach/gpio.h42
-rw-r--r--arch/arm/mach-dove/include/mach/irqs.h7
-rw-r--r--arch/arm/mach-dove/irq.c30
-rw-r--r--arch/arm/mach-exynos4/Kconfig195
-rw-r--r--arch/arm/mach-exynos4/Makefile56
-rw-r--r--arch/arm/mach-exynos4/Makefile.boot (renamed from arch/arm/mach-s5pv310/Makefile.boot)0
-rw-r--r--arch/arm/mach-exynos4/clock.c (renamed from arch/arm/mach-s5pv310/clock.c)286
-rw-r--r--arch/arm/mach-exynos4/cpu.c (renamed from arch/arm/mach-s5pv310/cpu.c)99
-rw-r--r--arch/arm/mach-exynos4/cpufreq.c (renamed from arch/arm/mach-s5pv310/cpufreq.c)110
-rw-r--r--arch/arm/mach-exynos4/dev-ahci.c263
-rw-r--r--arch/arm/mach-exynos4/dev-audio.c (renamed from arch/arm/mach-s5pv310/dev-audio.c)143
-rw-r--r--arch/arm/mach-exynos4/dev-pd.c (renamed from arch/arm/mach-s5pv310/dev-pd.c)40
-rw-r--r--arch/arm/mach-exynos4/dev-sysmmu.c (renamed from arch/arm/mach-s5pv310/dev-sysmmu.c)121
-rw-r--r--arch/arm/mach-exynos4/dma.c (renamed from arch/arm/mach-s5pv310/dma.c)50
-rw-r--r--arch/arm/mach-exynos4/gpiolib.c365
-rw-r--r--arch/arm/mach-exynos4/headsmp.S (renamed from arch/arm/mach-s5pv310/headsmp.S)6
-rw-r--r--arch/arm/mach-exynos4/hotplug.c (renamed from arch/arm/mach-s5pv310/hotplug.c)10
-rw-r--r--arch/arm/mach-exynos4/include/mach/debug-macro.S (renamed from arch/arm/mach-s5pv310/include/mach/debug-macro.S)6
-rw-r--r--arch/arm/mach-exynos4/include/mach/dma.h (renamed from arch/arm/mach-s5pv310/include/mach/dma.h)0
-rw-r--r--arch/arm/mach-exynos4/include/mach/entry-macro.S (renamed from arch/arm/mach-s5pv310/include/mach/entry-macro.S)4
-rw-r--r--arch/arm/mach-exynos4/include/mach/gpio.h156
-rw-r--r--arch/arm/mach-exynos4/include/mach/hardware.h (renamed from arch/arm/mach-s5pv310/include/mach/hardware.h)8
-rw-r--r--arch/arm/mach-exynos4/include/mach/io.h (renamed from arch/arm/mach-s5pv310/include/mach/io.h)8
-rw-r--r--arch/arm/mach-exynos4/include/mach/irqs.h (renamed from arch/arm/mach-s5pv310/include/mach/irqs.h)26
-rw-r--r--arch/arm/mach-exynos4/include/mach/map.h162
-rw-r--r--arch/arm/mach-exynos4/include/mach/memory.h (renamed from arch/arm/mach-s5pv310/include/mach/memory.h)8
-rw-r--r--arch/arm/mach-exynos4/include/mach/pm-core.h49
-rw-r--r--arch/arm/mach-exynos4/include/mach/pwm-clock.h (renamed from arch/arm/mach-s5pv310/include/mach/pwm-clock.h)8
-rw-r--r--arch/arm/mach-exynos4/include/mach/regs-clock.h (renamed from arch/arm/mach-s5pv310/include/mach/regs-clock.h)41
-rw-r--r--arch/arm/mach-exynos4/include/mach/regs-gpio.h42
-rw-r--r--arch/arm/mach-exynos4/include/mach/regs-irq.h (renamed from arch/arm/mach-s5pv310/include/mach/regs-irq.h)8
-rw-r--r--arch/arm/mach-exynos4/include/mach/regs-mct.h52
-rw-r--r--arch/arm/mach-exynos4/include/mach/regs-mem.h (renamed from arch/arm/mach-s5pv310/include/mach/regs-mem.h)6
-rw-r--r--arch/arm/mach-exynos4/include/mach/regs-pmu.h162
-rw-r--r--arch/arm/mach-exynos4/include/mach/regs-sysmmu.h (renamed from arch/arm/mach-s5pv310/include/mach/regs-sysmmu.h)10
-rw-r--r--arch/arm/mach-exynos4/include/mach/smp.h (renamed from arch/arm/mach-s5pv310/include/mach/smp.h)2
-rw-r--r--arch/arm/mach-exynos4/include/mach/sysmmu.h46
-rw-r--r--arch/arm/mach-exynos4/include/mach/system.h (renamed from arch/arm/mach-s5pv310/include/mach/system.h)8
-rw-r--r--arch/arm/mach-exynos4/include/mach/timex.h (renamed from arch/arm/mach-s5pv310/include/mach/timex.h)8
-rw-r--r--arch/arm/mach-exynos4/include/mach/uncompress.h (renamed from arch/arm/mach-s5pv310/include/mach/uncompress.h)8
-rw-r--r--arch/arm/mach-exynos4/include/mach/vmalloc.h (renamed from arch/arm/mach-s5pv310/include/mach/vmalloc.h)8
-rw-r--r--arch/arm/mach-exynos4/init.c (renamed from arch/arm/mach-s5pv310/init.c)10
-rw-r--r--arch/arm/mach-exynos4/irq-combiner.c (renamed from arch/arm/mach-s5pv310/irq-combiner.c)4
-rw-r--r--arch/arm/mach-exynos4/irq-eint.c (renamed from arch/arm/mach-s5pv310/irq-eint.c)62
-rw-r--r--arch/arm/mach-exynos4/localtimer.c (renamed from arch/arm/mach-s5pv310/localtimer.c)2
-rw-r--r--arch/arm/mach-exynos4/mach-armlex4210.c215
-rw-r--r--arch/arm/mach-exynos4/mach-nuri.c305
-rw-r--r--arch/arm/mach-exynos4/mach-smdkc210.c (renamed from arch/arm/mach-s5pv310/mach-smdkc210.c)48
-rw-r--r--arch/arm/mach-exynos4/mach-smdkv310.c (renamed from arch/arm/mach-s5pv310/mach-smdkv310.c)72
-rw-r--r--arch/arm/mach-exynos4/mach-universal_c210.c650
-rw-r--r--arch/arm/mach-exynos4/mct.c421
-rw-r--r--arch/arm/mach-exynos4/platsmp.c (renamed from arch/arm/mach-s5pv310/platsmp.c)12
-rw-r--r--arch/arm/mach-exynos4/pm.c420
-rw-r--r--arch/arm/mach-exynos4/setup-fimc.c44
-rw-r--r--arch/arm/mach-exynos4/setup-i2c0.c (renamed from arch/arm/mach-s5pv310/setup-i2c0.c)4
-rw-r--r--arch/arm/mach-exynos4/setup-i2c1.c (renamed from arch/arm/mach-s5pv310/setup-i2c1.c)4
-rw-r--r--arch/arm/mach-exynos4/setup-i2c2.c (renamed from arch/arm/mach-s5pv310/setup-i2c2.c)4
-rw-r--r--arch/arm/mach-exynos4/setup-i2c3.c (renamed from arch/arm/mach-s5pv310/setup-i2c3.c)4
-rw-r--r--arch/arm/mach-exynos4/setup-i2c4.c (renamed from arch/arm/mach-s5pv310/setup-i2c4.c)4
-rw-r--r--arch/arm/mach-exynos4/setup-i2c5.c (renamed from arch/arm/mach-s5pv310/setup-i2c5.c)4
-rw-r--r--arch/arm/mach-exynos4/setup-i2c6.c (renamed from arch/arm/mach-s5pv310/setup-i2c6.c)4
-rw-r--r--arch/arm/mach-exynos4/setup-i2c7.c (renamed from arch/arm/mach-s5pv310/setup-i2c7.c)4
-rw-r--r--arch/arm/mach-exynos4/setup-keypad.c35
-rw-r--r--arch/arm/mach-exynos4/setup-sdhci-gpio.c (renamed from arch/arm/mach-s5pv310/setup-sdhci-gpio.c)52
-rw-r--r--arch/arm/mach-exynos4/setup-sdhci.c (renamed from arch/arm/mach-s5pv310/setup-sdhci.c)12
-rw-r--r--arch/arm/mach-exynos4/sleep.S76
-rw-r--r--arch/arm/mach-exynos4/time.c (renamed from arch/arm/mach-s5pv310/time.c)80
-rw-r--r--arch/arm/mach-imx/Kconfig12
-rw-r--r--arch/arm/mach-imx/Makefile5
-rw-r--r--arch/arm/mach-imx/clock-imx1.c1
-rw-r--r--arch/arm/mach-imx/clock-imx25.c3
-rw-r--r--arch/arm/mach-imx/devices-imx1.h11
-rw-r--r--arch/arm/mach-imx/devices-imx25.h6
-rw-r--r--arch/arm/mach-imx/dma-v1.c2
-rw-r--r--arch/arm/mach-imx/ehci-imx25.c80
-rw-r--r--arch/arm/mach-imx/ehci-imx27.c82
-rw-r--r--arch/arm/mach-imx/eukrea_mbimx27-baseboard.c7
-rw-r--r--arch/arm/mach-imx/mach-cpuimx27.c49
-rw-r--r--arch/arm/mach-imx/mach-eukrea_cpuimx25.c27
-rw-r--r--arch/arm/mach-imx/mach-imx27_visstrim_m10.c32
-rw-r--r--arch/arm/mach-imx/mach-imx27ipcam.c78
-rw-r--r--arch/arm/mach-imx/mach-imx27lite.c11
-rw-r--r--arch/arm/mach-imx/mach-mx1ads.c22
-rw-r--r--arch/arm/mach-imx/mach-mx21ads.c11
-rw-r--r--arch/arm/mach-imx/mach-mx25_3ds.c32
-rw-r--r--arch/arm/mach-imx/mach-mx27_3ds.c43
-rw-r--r--arch/arm/mach-imx/mach-mx27ads.c11
-rw-r--r--arch/arm/mach-imx/mach-mxt_td60.c12
-rw-r--r--arch/arm/mach-imx/mach-pca100.c49
-rw-r--r--arch/arm/mach-imx/mach-pcm038.c27
-rw-r--r--arch/arm/mach-imx/mach-scb9328.c13
-rw-r--r--arch/arm/mach-imx/mm-imx1.c21
-rw-r--r--arch/arm/mach-imx/mm-imx21.c23
-rw-r--r--arch/arm/mach-imx/mm-imx25.c18
-rw-r--r--arch/arm/mach-imx/mm-imx27.c23
-rw-r--r--arch/arm/mach-kirkwood/common.c16
-rw-r--r--arch/arm/mach-kirkwood/common.h2
-rw-r--r--arch/arm/mach-kirkwood/d2net_v2-setup.c1
-rw-r--r--arch/arm/mach-kirkwood/db88f6281-bp-setup.c1
-rw-r--r--arch/arm/mach-kirkwood/dockstar-setup.c1
-rw-r--r--arch/arm/mach-kirkwood/guruplug-setup.c1
-rw-r--r--arch/arm/mach-kirkwood/include/mach/bridge-regs.h3
-rw-r--r--arch/arm/mach-kirkwood/include/mach/gpio.h29
-rw-r--r--arch/arm/mach-kirkwood/include/mach/kirkwood.h2
-rw-r--r--arch/arm/mach-kirkwood/irq.c22
-rw-r--r--arch/arm/mach-kirkwood/mpp.c3
-rw-r--r--arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c1
-rw-r--r--arch/arm/mach-kirkwood/netspace_v2-setup.c3
-rw-r--r--arch/arm/mach-kirkwood/netxbig_v2-setup.c2
-rw-r--r--arch/arm/mach-kirkwood/openrd-setup.c3
-rw-r--r--arch/arm/mach-kirkwood/pcie.c8
-rw-r--r--arch/arm/mach-kirkwood/rd88f6192-nas-setup.c1
-rw-r--r--arch/arm/mach-kirkwood/rd88f6281-setup.c1
-rw-r--r--arch/arm/mach-kirkwood/sheevaplug-setup.c2
-rw-r--r--arch/arm/mach-kirkwood/t5325-setup.c18
-rw-r--r--arch/arm/mach-kirkwood/ts219-setup.c1
-rw-r--r--arch/arm/mach-kirkwood/ts41x-setup.c9
-rw-r--r--arch/arm/mach-loki/common.c9
-rw-r--r--arch/arm/mach-loki/common.h1
-rw-r--r--arch/arm/mach-loki/include/mach/bridge-regs.h5
-rw-r--r--arch/arm/mach-loki/lb88rc8480-setup.c1
-rw-r--r--arch/arm/mach-mv78xx0/buffalo-wxl-setup.c1
-rw-r--r--arch/arm/mach-mv78xx0/common.c8
-rw-r--r--arch/arm/mach-mv78xx0/common.h1
-rw-r--r--arch/arm/mach-mv78xx0/db78x00-bp-setup.c1
-rw-r--r--arch/arm/mach-mv78xx0/include/mach/bridge-regs.h4
-rw-r--r--arch/arm/mach-mv78xx0/include/mach/gpio.h31
-rw-r--r--arch/arm/mach-mv78xx0/include/mach/mv78xx0.h1
-rw-r--r--arch/arm/mach-mv78xx0/irq.c22
-rw-r--r--arch/arm/mach-mv78xx0/mpp.c3
-rw-r--r--arch/arm/mach-mv78xx0/rd78x00-masa-setup.c1
-rw-r--r--arch/arm/mach-mx3/Kconfig25
-rw-r--r--arch/arm/mach-mx3/Makefile6
-rw-r--r--arch/arm/mach-mx3/devices-imx35.h2
-rw-r--r--arch/arm/mach-mx3/ehci-imx31.c83
-rw-r--r--arch/arm/mach-mx3/ehci-imx35.c80
-rw-r--r--arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c4
-rw-r--r--arch/arm/mach-mx3/iomux-imx31.c12
-rw-r--r--arch/arm/mach-mx3/mach-armadillo5x0.c41
-rw-r--r--arch/arm/mach-mx3/mach-bug.c66
-rw-r--r--arch/arm/mach-mx3/mach-cpuimx35.c31
-rw-r--r--arch/arm/mach-mx3/mach-kzm_arm11_01.c17
-rw-r--r--arch/arm/mach-mx3/mach-mx31_3ds.c462
-rw-r--r--arch/arm/mach-mx3/mach-mx31ads.c57
-rw-r--r--arch/arm/mach-mx3/mach-mx31lilly.c95
-rw-r--r--arch/arm/mach-mx3/mach-mx31lite.c37
-rw-r--r--arch/arm/mach-mx3/mach-mx31moboard.c39
-rw-r--r--arch/arm/mach-mx3/mach-mx35_3ds.c42
-rw-r--r--arch/arm/mach-mx3/mach-pcm037.c46
-rw-r--r--arch/arm/mach-mx3/mach-pcm037_eet.c2
-rw-r--r--arch/arm/mach-mx3/mach-pcm043.c54
-rw-r--r--arch/arm/mach-mx3/mach-qong.c22
-rw-r--r--arch/arm/mach-mx3/mach-vpr200.c328
-rw-r--r--arch/arm/mach-mx3/mm.c43
-rw-r--r--arch/arm/mach-mx3/mx31moboard-devboard.c7
-rw-r--r--arch/arm/mach-mx3/mx31moboard-marxbot.c6
-rw-r--r--arch/arm/mach-mx3/mx31moboard-smartbot.c13
-rw-r--r--arch/arm/mach-mx5/Kconfig27
-rw-r--r--arch/arm/mach-mx5/Makefile4
-rw-r--r--arch/arm/mach-mx5/board-cpuimx51.c20
-rw-r--r--arch/arm/mach-mx5/board-cpuimx51sd.c31
-rw-r--r--arch/arm/mach-mx5/board-mx50_rdp.c34
-rw-r--r--arch/arm/mach-mx5/board-mx51_3ds.c43
-rw-r--r--arch/arm/mach-mx5/board-mx51_babbage.c43
-rw-r--r--arch/arm/mach-mx5/board-mx51_efikamx.c211
-rw-r--r--arch/arm/mach-mx5/board-mx51_efikasb.c283
-rw-r--r--arch/arm/mach-mx5/board-mx53_evk.c40
-rw-r--r--arch/arm/mach-mx5/board-mx53_loco.c178
-rw-r--r--arch/arm/mach-mx5/board-mx53_smd.c40
-rw-r--r--arch/arm/mach-mx5/clock-mx51-mx53.c148
-rw-r--r--arch/arm/mach-mx5/cpu.c11
-rw-r--r--arch/arm/mach-mx5/crm_regs.h7
-rw-r--r--arch/arm/mach-mx5/devices-imx50.h (renamed from arch/arm/mach-mx5/devices-mx50.h)8
-rw-r--r--arch/arm/mach-mx5/devices-imx53.h4
-rw-r--r--arch/arm/mach-mx5/efika.h10
-rw-r--r--arch/arm/mach-mx5/ehci.c156
-rw-r--r--arch/arm/mach-mx5/mm-mx50.c19
-rw-r--r--arch/arm/mach-mx5/mm.c14
-rw-r--r--arch/arm/mach-mx5/mx51_efika.c636
-rw-r--r--arch/arm/mach-mxc91231/iomux.c14
-rw-r--r--arch/arm/mach-mxc91231/magx-zn5.c11
-rw-r--r--arch/arm/mach-mxc91231/mm.c7
-rw-r--r--arch/arm/mach-mxs/Kconfig24
-rw-r--r--arch/arm/mach-mxs/Makefile5
-rw-r--r--arch/arm/mach-mxs/clock-mx23.c11
-rw-r--r--arch/arm/mach-mxs/clock-mx28.c25
-rw-r--r--arch/arm/mach-mxs/devices-mx23.h11
-rw-r--r--arch/arm/mach-mxs/devices-mx28.h23
-rw-r--r--arch/arm/mach-mxs/devices.c2
-rw-r--r--arch/arm/mach-mxs/devices/Kconfig16
-rw-r--r--arch/arm/mach-mxs/devices/Makefile6
-rw-r--r--arch/arm/mach-mxs/devices/platform-auart.c64
-rw-r--r--arch/arm/mach-mxs/devices/platform-dma.c49
-rw-r--r--arch/arm/mach-mxs/devices/platform-fec.c5
-rw-r--r--arch/arm/mach-mxs/devices/platform-flexcan.c51
-rw-r--r--arch/arm/mach-mxs/devices/platform-mxs-i2c.c51
-rw-r--r--arch/arm/mach-mxs/devices/platform-mxs-pwm.c22
-rw-r--r--arch/arm/mach-mxs/devices/platform-mxsfb.c46
-rw-r--r--arch/arm/mach-mxs/gpio.c46
-rw-r--r--arch/arm/mach-mxs/include/mach/common.h1
-rw-r--r--arch/arm/mach-mxs/include/mach/devices-common.h35
-rw-r--r--arch/arm/mach-mxs/include/mach/iomux-mx23.h190
-rw-r--r--arch/arm/mach-mxs/include/mach/iomux.h3
-rw-r--r--arch/arm/mach-mxs/include/mach/mx23.h38
-rw-r--r--arch/arm/mach-mxs/include/mach/mx28.h45
-rw-r--r--arch/arm/mach-mxs/include/mach/mxs.h9
-rw-r--r--arch/arm/mach-mxs/include/mach/mxsfb.h49
-rw-r--r--arch/arm/mach-mxs/include/mach/uncompress.h1
-rw-r--r--arch/arm/mach-mxs/mach-mx23evk.c90
-rw-r--r--arch/arm/mach-mxs/mach-mx28evk.c237
-rw-r--r--arch/arm/mach-mxs/mach-tx28.c183
-rw-r--r--arch/arm/mach-mxs/module-tx28.c131
-rw-r--r--arch/arm/mach-mxs/module-tx28.h9
-rw-r--r--arch/arm/mach-mxs/ocotp.c90
-rw-r--r--arch/arm/mach-mxs/pm.c43
-rw-r--r--arch/arm/mach-mxs/regs-clkctrl-mx23.h124
-rw-r--r--arch/arm/mach-mxs/regs-clkctrl-mx28.h177
-rw-r--r--arch/arm/mach-mxs/system.c2
-rw-r--r--arch/arm/mach-orion5x/common.c10
-rw-r--r--arch/arm/mach-orion5x/common.h1
-rw-r--r--arch/arm/mach-orion5x/d2net-setup.c2
-rw-r--r--arch/arm/mach-orion5x/db88f5281-setup.c1
-rw-r--r--arch/arm/mach-orion5x/dns323-setup.c1
-rw-r--r--arch/arm/mach-orion5x/edmini_v2-setup.c1
-rw-r--r--arch/arm/mach-orion5x/include/mach/bridge-regs.h6
-rw-r--r--arch/arm/mach-orion5x/include/mach/gpio.h28
-rw-r--r--arch/arm/mach-orion5x/include/mach/orion5x.h1
-rw-r--r--arch/arm/mach-orion5x/irq.c19
-rw-r--r--arch/arm/mach-orion5x/kurobox_pro-setup.c2
-rw-r--r--arch/arm/mach-orion5x/ls-chl-setup.c1
-rw-r--r--arch/arm/mach-orion5x/ls_hgl-setup.c1
-rw-r--r--arch/arm/mach-orion5x/lsmini-setup.c1
-rw-r--r--arch/arm/mach-orion5x/mpp.c3
-rw-r--r--arch/arm/mach-orion5x/mss2-setup.c1
-rw-r--r--arch/arm/mach-orion5x/mv2120-setup.c1
-rw-r--r--arch/arm/mach-orion5x/net2big-setup.c1
-rw-r--r--arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c1
-rw-r--r--arch/arm/mach-orion5x/rd88f5181l-ge-setup.c1
-rw-r--r--arch/arm/mach-orion5x/rd88f5182-setup.c1
-rw-r--r--arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c1
-rw-r--r--arch/arm/mach-orion5x/terastation_pro2-setup.c1
-rw-r--r--arch/arm/mach-orion5x/ts209-setup.c1
-rw-r--r--arch/arm/mach-orion5x/ts409-setup.c1
-rw-r--r--arch/arm/mach-orion5x/ts78xx-fpga.h15
-rw-r--r--arch/arm/mach-orion5x/ts78xx-setup.c78
-rw-r--r--arch/arm/mach-orion5x/wnr854t-setup.c1
-rw-r--r--arch/arm/mach-orion5x/wrt350n-v2-setup.c1
-rw-r--r--arch/arm/mach-s3c2440/mach-gta02.c71
-rw-r--r--arch/arm/mach-s3c64xx/Kconfig5
-rw-r--r--arch/arm/mach-s3c64xx/cpufreq.c2
-rw-r--r--arch/arm/mach-s3c64xx/mach-smdk6410.c46
-rw-r--r--arch/arm/mach-s5p64x0/Kconfig4
-rw-r--r--arch/arm/mach-s5p64x0/mach-smdk6440.c47
-rw-r--r--arch/arm/mach-s5p64x0/mach-smdk6450.c47
-rw-r--r--arch/arm/mach-s5pc100/Kconfig1
-rw-r--r--arch/arm/mach-s5pc100/gpiolib.c1
-rw-r--r--arch/arm/mach-s5pc100/mach-smdkc100.c48
-rw-r--r--arch/arm/mach-s5pv210/Kconfig7
-rw-r--r--arch/arm/mach-s5pv210/Makefile1
-rw-r--r--arch/arm/mach-s5pv210/gpiolib.c1
-rw-r--r--arch/arm/mach-s5pv210/include/mach/regs-clock.h5
-rw-r--r--arch/arm/mach-s5pv210/mach-aquila.c56
-rw-r--r--arch/arm/mach-s5pv210/mach-goni.c107
-rw-r--r--arch/arm/mach-s5pv210/mach-smdkc110.c4
-rw-r--r--arch/arm/mach-s5pv210/mach-smdkv210.c47
-rw-r--r--arch/arm/mach-s5pv210/mach-torbreck.c4
-rw-r--r--arch/arm/mach-s5pv210/setup-fimc.c43
-rw-r--r--arch/arm/mach-s5pv310/Kconfig151
-rw-r--r--arch/arm/mach-s5pv310/Makefile43
-rw-r--r--arch/arm/mach-s5pv310/gpiolib.c304
-rw-r--r--arch/arm/mach-s5pv310/include/mach/gpio.h135
-rw-r--r--arch/arm/mach-s5pv310/include/mach/map.h144
-rw-r--r--arch/arm/mach-s5pv310/include/mach/regs-gpio.h42
-rw-r--r--arch/arm/mach-s5pv310/include/mach/regs-pmu.h30
-rw-r--r--arch/arm/mach-s5pv310/include/mach/sysmmu.h122
-rw-r--r--arch/arm/mach-s5pv310/mach-universal_c210.c237
-rw-r--r--arch/arm/mach-tcc8k/board-tcc8000-sdk.c19
-rw-r--r--arch/arm/mach-tcc8k/clock.c38
-rw-r--r--arch/arm/mach-u300/core.c179
-rw-r--r--arch/arm/mach-u300/include/mach/coh901318.h7
-rw-r--r--arch/arm/mach-u300/mmc.c160
-rw-r--r--arch/arm/mach-u300/spi.c21
-rw-r--r--arch/arm/mach-ux500/Makefile8
-rw-r--r--arch/arm/mach-ux500/board-mop500-keypads.c229
-rw-r--r--arch/arm/mach-ux500/board-mop500-pins.c241
-rw-r--r--arch/arm/mach-ux500/board-mop500-regulators.c62
-rw-r--r--arch/arm/mach-ux500/board-mop500-sdi.c184
-rw-r--r--arch/arm/mach-ux500/board-mop500-stuib.c205
-rw-r--r--arch/arm/mach-ux500/board-mop500-u8500uib.c111
-rw-r--r--arch/arm/mach-ux500/board-mop500-uib.c135
-rw-r--r--arch/arm/mach-ux500/board-mop500.c328
-rw-r--r--arch/arm/mach-ux500/board-mop500.h25
-rw-r--r--arch/arm/mach-ux500/board-u5500-sdi.c25
-rw-r--r--arch/arm/mach-ux500/board-u5500.c6
-rw-r--r--arch/arm/mach-ux500/clock.c6
-rw-r--r--arch/arm/mach-ux500/cpu-db5500.c53
-rw-r--r--arch/arm/mach-ux500/cpu-db8500.c76
-rw-r--r--arch/arm/mach-ux500/devices-common.c1
-rw-r--r--arch/arm/mach-ux500/devices-common.h7
-rw-r--r--arch/arm/mach-ux500/devices-db5500.h19
-rw-r--r--arch/arm/mach-ux500/devices-db8500.c67
-rw-r--r--arch/arm/mach-ux500/devices-db8500.h15
-rw-r--r--arch/arm/mach-ux500/dma-db5500.c16
-rw-r--r--arch/arm/mach-ux500/include/mach/uncompress.h6
-rw-r--r--arch/arm/mach-ux500/include/mach/usb.h25
-rw-r--r--arch/arm/mach-ux500/usb.c160
-rw-r--r--arch/arm/mm/Kconfig4
-rw-r--r--arch/arm/plat-mxc/Kconfig1
-rw-r--r--arch/arm/plat-mxc/Makefile1
-rw-r--r--arch/arm/plat-mxc/devices.c2
-rw-r--r--arch/arm/plat-mxc/devices/platform-fec.c9
-rw-r--r--arch/arm/plat-mxc/devices/platform-imx-dma.c6
-rw-r--r--arch/arm/plat-mxc/devices/platform-imx-fb.c5
-rw-r--r--arch/arm/plat-mxc/devices/platform-imx-i2c.c10
-rw-r--r--arch/arm/plat-mxc/devices/platform-imx2-wdt.c9
-rw-r--r--arch/arm/plat-mxc/devices/platform-spi_imx.c9
-rw-r--r--arch/arm/plat-mxc/ehci.c369
-rw-r--r--arch/arm/plat-mxc/gpio.c111
-rw-r--r--arch/arm/plat-mxc/include/mach/common.h10
-rw-r--r--arch/arm/plat-mxc/include/mach/gpio.h15
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx3.h8
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx35.h14
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx50.h44
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx51.h44
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx53.h2639
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mxc91231.h8
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-v1.h2
-rw-r--r--arch/arm/plat-mxc/include/mach/irqs.h6
-rw-r--r--arch/arm/plat-mxc/include/mach/mx1.h9
-rw-r--r--arch/arm/plat-mxc/include/mach/mx53.h2
-rw-r--r--arch/arm/plat-mxc/include/mach/mxc.h10
-rw-r--r--arch/arm/plat-mxc/include/mach/mxc_ehci.h7
-rw-r--r--arch/arm/plat-mxc/include/mach/ulpi.h9
-rw-r--r--arch/arm/plat-mxc/include/mach/uncompress.h7
-rw-r--r--arch/arm/plat-mxc/iomux-v1.c24
-rw-r--r--arch/arm/plat-mxc/ulpi.c5
-rw-r--r--arch/arm/plat-nomadik/gpio.c487
-rw-r--r--arch/arm/plat-nomadik/include/plat/gpio.h6
-rw-r--r--arch/arm/plat-orion/gpio.c456
-rw-r--r--arch/arm/plat-orion/include/plat/gpio.h5
-rw-r--r--arch/arm/plat-orion/include/plat/time.h5
-rw-r--r--arch/arm/plat-orion/time.c119
-rw-r--r--arch/arm/plat-s3c24xx/Kconfig7
-rw-r--r--arch/arm/plat-s5p/Kconfig23
-rw-r--r--arch/arm/plat-s5p/Makefile3
-rw-r--r--arch/arm/plat-s5p/cpu.c25
-rw-r--r--arch/arm/plat-s5p/dev-csis0.c2
-rw-r--r--arch/arm/plat-s5p/dev-csis1.c2
-rw-r--r--arch/arm/plat-s5p/dev-fimc3.c43
-rw-r--r--arch/arm/plat-s5p/include/plat/camport.h28
-rw-r--r--arch/arm/plat-s5p/include/plat/csis.h28
-rw-r--r--arch/arm/plat-s5p/include/plat/exynos4.h34
-rw-r--r--arch/arm/plat-s5p/include/plat/mipi_csis.h43
-rw-r--r--arch/arm/plat-s5p/include/plat/s5p-time.h40
-rw-r--r--arch/arm/plat-s5p/include/plat/s5pv310.h34
-rw-r--r--arch/arm/plat-s5p/include/plat/sysmmu.h95
-rw-r--r--arch/arm/plat-s5p/irq-gpioint.c170
-rw-r--r--arch/arm/plat-s5p/s5p-time.c448
-rw-r--r--arch/arm/plat-s5p/setup-mipiphy.c63
-rw-r--r--arch/arm/plat-s5p/sysmmu.c370
-rw-r--r--arch/arm/plat-samsung/Kconfig13
-rw-r--r--arch/arm/plat-samsung/Makefile1
-rw-r--r--arch/arm/plat-samsung/dev-pwm.c53
-rw-r--r--arch/arm/plat-samsung/include/plat/cpu.h1
-rw-r--r--arch/arm/plat-samsung/include/plat/devs.h25
-rw-r--r--arch/arm/plat-samsung/include/plat/fimc-core.h5
-rw-r--r--arch/arm/plat-samsung/include/plat/gpio-cfg.h16
-rw-r--r--arch/arm/plat-samsung/include/plat/pd.h4
-rw-r--r--arch/arm/plat-samsung/include/plat/sdhci.h63
-rw-r--r--arch/arm/plat-samsung/pwm.c33
406 files changed, 17615 insertions, 5754 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e34bf0272da4..b70fe202c00b 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -722,7 +722,8 @@ config ARCH_S5P64X0
722 select GENERIC_GPIO 722 select GENERIC_GPIO
723 select HAVE_CLK 723 select HAVE_CLK
724 select HAVE_S3C2410_WATCHDOG if WATCHDOG 724 select HAVE_S3C2410_WATCHDOG if WATCHDOG
725 select ARCH_USES_GETTIMEOFFSET 725 select GENERIC_CLOCKEVENTS
726 select HAVE_SCHED_CLOCK
726 select HAVE_S3C2410_I2C if I2C 727 select HAVE_S3C2410_I2C if I2C
727 select HAVE_S3C_RTC if RTC_CLASS 728 select HAVE_S3C_RTC if RTC_CLASS
728 help 729 help
@@ -760,15 +761,16 @@ config ARCH_S5PV210
760 select HAVE_CLK 761 select HAVE_CLK
761 select ARM_L1_CACHE_SHIFT_6 762 select ARM_L1_CACHE_SHIFT_6
762 select ARCH_HAS_CPUFREQ 763 select ARCH_HAS_CPUFREQ
763 select ARCH_USES_GETTIMEOFFSET 764 select GENERIC_CLOCKEVENTS
765 select HAVE_SCHED_CLOCK
764 select HAVE_S3C2410_I2C if I2C 766 select HAVE_S3C2410_I2C if I2C
765 select HAVE_S3C_RTC if RTC_CLASS 767 select HAVE_S3C_RTC if RTC_CLASS
766 select HAVE_S3C2410_WATCHDOG if WATCHDOG 768 select HAVE_S3C2410_WATCHDOG if WATCHDOG
767 help 769 help
768 Samsung S5PV210/S5PC110 series based systems 770 Samsung S5PV210/S5PC110 series based systems
769 771
770config ARCH_S5PV310 772config ARCH_EXYNOS4
771 bool "Samsung S5PV310/S5PC210" 773 bool "Samsung EXYNOS4"
772 select CPU_V7 774 select CPU_V7
773 select ARCH_SPARSEMEM_ENABLE 775 select ARCH_SPARSEMEM_ENABLE
774 select GENERIC_GPIO 776 select GENERIC_GPIO
@@ -779,7 +781,7 @@ config ARCH_S5PV310
779 select HAVE_S3C2410_I2C if I2C 781 select HAVE_S3C2410_I2C if I2C
780 select HAVE_S3C2410_WATCHDOG if WATCHDOG 782 select HAVE_S3C2410_WATCHDOG if WATCHDOG
781 help 783 help
782 Samsung S5PV310 series based systems 784 Samsung EXYNOS4 series based systems
783 785
784config ARCH_SHARK 786config ARCH_SHARK
785 bool "Shark" 787 bool "Shark"
@@ -993,7 +995,7 @@ source "arch/arm/mach-s5pc100/Kconfig"
993 995
994source "arch/arm/mach-s5pv210/Kconfig" 996source "arch/arm/mach-s5pv210/Kconfig"
995 997
996source "arch/arm/mach-s5pv310/Kconfig" 998source "arch/arm/mach-exynos4/Kconfig"
997 999
998source "arch/arm/mach-shmobile/Kconfig" 1000source "arch/arm/mach-shmobile/Kconfig"
999 1001
@@ -1315,7 +1317,7 @@ config SMP
1315 depends on GENERIC_CLOCKEVENTS 1317 depends on GENERIC_CLOCKEVENTS
1316 depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \ 1318 depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
1317 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \ 1319 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
1318 ARCH_S5PV310 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \ 1320 ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
1319 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE 1321 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE
1320 select USE_GENERIC_SMP_HELPERS 1322 select USE_GENERIC_SMP_HELPERS
1321 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP 1323 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
@@ -1403,7 +1405,7 @@ config LOCAL_TIMERS
1403 bool "Use local timer interrupts" 1405 bool "Use local timer interrupts"
1404 depends on SMP 1406 depends on SMP
1405 default y 1407 default y
1406 select HAVE_ARM_TWD if !ARCH_MSM_SCORPIONMP 1408 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1407 help 1409 help
1408 Enable support for local timers on SMP platforms, rather then the 1410 Enable support for local timers on SMP platforms, rather then the
1409 legacy IPI broadcast method. Local timers allows the system 1411 legacy IPI broadcast method. Local timers allows the system
@@ -1415,7 +1417,7 @@ source kernel/Kconfig.preempt
1415config HZ 1417config HZ
1416 int 1418 int
1417 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \ 1419 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
1418 ARCH_S5P6442 || ARCH_S5PV210 || ARCH_S5PV310 1420 ARCH_S5P6442 || ARCH_S5PV210 || ARCH_EXYNOS4
1419 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER 1421 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1420 default AT91_TIMER_HZ if ARCH_AT91 1422 default AT91_TIMER_HZ if ARCH_AT91
1421 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE 1423 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 5c7114bb8a25..c7d321a3d95d 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -181,7 +181,7 @@ machine-$(CONFIG_ARCH_S5P64X0) := s5p64x0
181machine-$(CONFIG_ARCH_S5P6442) := s5p6442 181machine-$(CONFIG_ARCH_S5P6442) := s5p6442
182machine-$(CONFIG_ARCH_S5PC100) := s5pc100 182machine-$(CONFIG_ARCH_S5PC100) := s5pc100
183machine-$(CONFIG_ARCH_S5PV210) := s5pv210 183machine-$(CONFIG_ARCH_S5PV210) := s5pv210
184machine-$(CONFIG_ARCH_S5PV310) := s5pv310 184machine-$(CONFIG_ARCH_EXYNOS4) := exynos4
185machine-$(CONFIG_ARCH_SA1100) := sa1100 185machine-$(CONFIG_ARCH_SA1100) := sa1100
186machine-$(CONFIG_ARCH_SHARK) := shark 186machine-$(CONFIG_ARCH_SHARK) := shark
187machine-$(CONFIG_ARCH_SHMOBILE) := shmobile 187machine-$(CONFIG_ARCH_SHMOBILE) := shmobile
diff --git a/arch/arm/configs/exynos4_defconfig b/arch/arm/configs/exynos4_defconfig
new file mode 100644
index 000000000000..2ffba24d2e2a
--- /dev/null
+++ b/arch/arm/configs/exynos4_defconfig
@@ -0,0 +1,70 @@
1CONFIG_EXPERIMENTAL=y
2CONFIG_BLK_DEV_INITRD=y
3CONFIG_KALLSYMS_ALL=y
4CONFIG_MODULES=y
5CONFIG_MODULE_UNLOAD=y
6# CONFIG_BLK_DEV_BSG is not set
7CONFIG_ARCH_EXYNOS4=y
8CONFIG_S3C_LOWLEVEL_UART_PORT=1
9CONFIG_MACH_SMDKC210=y
10CONFIG_MACH_SMDKV310=y
11CONFIG_MACH_UNIVERSAL_C210=y
12CONFIG_NO_HZ=y
13CONFIG_HIGH_RES_TIMERS=y
14CONFIG_SMP=y
15CONFIG_NR_CPUS=2
16CONFIG_HOTPLUG_CPU=y
17CONFIG_PREEMPT=y
18CONFIG_AEABI=y
19CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc mem=256M"
20CONFIG_VFP=y
21CONFIG_NEON=y
22CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
23CONFIG_BLK_DEV_LOOP=y
24CONFIG_BLK_DEV_RAM=y
25CONFIG_BLK_DEV_RAM_SIZE=8192
26CONFIG_SCSI=y
27CONFIG_BLK_DEV_SD=y
28CONFIG_CHR_DEV_SG=y
29CONFIG_INPUT_EVDEV=y
30# CONFIG_INPUT_KEYBOARD is not set
31# CONFIG_INPUT_MOUSE is not set
32CONFIG_INPUT_TOUCHSCREEN=y
33CONFIG_SERIAL_8250=y
34CONFIG_SERIAL_SAMSUNG=y
35CONFIG_SERIAL_SAMSUNG_CONSOLE=y
36CONFIG_HW_RANDOM=y
37CONFIG_I2C=y
38# CONFIG_HWMON is not set
39# CONFIG_MFD_SUPPORT is not set
40# CONFIG_HID_SUPPORT is not set
41# CONFIG_USB_SUPPORT is not set
42CONFIG_EXT2_FS=y
43CONFIG_MSDOS_FS=y
44CONFIG_VFAT_FS=y
45CONFIG_TMPFS=y
46CONFIG_TMPFS_POSIX_ACL=y
47CONFIG_CRAMFS=y
48CONFIG_ROMFS_FS=y
49CONFIG_PARTITION_ADVANCED=y
50CONFIG_BSD_DISKLABEL=y
51CONFIG_SOLARIS_X86_PARTITION=y
52CONFIG_NLS_CODEPAGE_437=y
53CONFIG_NLS_ASCII=y
54CONFIG_NLS_ISO8859_1=y
55CONFIG_MAGIC_SYSRQ=y
56CONFIG_DEBUG_KERNEL=y
57CONFIG_DETECT_HUNG_TASK=y
58CONFIG_DEBUG_RT_MUTEXES=y
59CONFIG_DEBUG_SPINLOCK=y
60CONFIG_DEBUG_MUTEXES=y
61CONFIG_DEBUG_SPINLOCK_SLEEP=y
62CONFIG_DEBUG_INFO=y
63# CONFIG_RCU_CPU_STALL_DETECTOR is not set
64CONFIG_SYSCTL_SYSCALL_CHECK=y
65CONFIG_DEBUG_USER=y
66CONFIG_DEBUG_ERRORS=y
67CONFIG_DEBUG_LL=y
68CONFIG_EARLY_PRINTK=y
69CONFIG_DEBUG_S3C_UART=1
70CONFIG_CRC_CCITT=y
diff --git a/arch/arm/configs/kirkwood_defconfig b/arch/arm/configs/kirkwood_defconfig
index 2f7042813765..aeb3af541fed 100644
--- a/arch/arm/configs/kirkwood_defconfig
+++ b/arch/arm/configs/kirkwood_defconfig
@@ -24,6 +24,7 @@ CONFIG_MACH_OPENRD_ULTIMATE=y
24CONFIG_MACH_NETSPACE_V2=y 24CONFIG_MACH_NETSPACE_V2=y
25CONFIG_MACH_INETSPACE_V2=y 25CONFIG_MACH_INETSPACE_V2=y
26CONFIG_MACH_NETSPACE_MAX_V2=y 26CONFIG_MACH_NETSPACE_MAX_V2=y
27CONFIG_MACH_D2NET_V2=y
27CONFIG_MACH_NET2BIG_V2=y 28CONFIG_MACH_NET2BIG_V2=y
28CONFIG_MACH_NET5BIG_V2=y 29CONFIG_MACH_NET5BIG_V2=y
29CONFIG_MACH_T5325=y 30CONFIG_MACH_T5325=y
diff --git a/arch/arm/configs/mx51_defconfig b/arch/arm/configs/mx51_defconfig
index 9cba68cfa51a..e3c903281f70 100644
--- a/arch/arm/configs/mx51_defconfig
+++ b/arch/arm/configs/mx51_defconfig
@@ -110,7 +110,7 @@ CONFIG_MMC=y
110CONFIG_MMC_BLOCK=m 110CONFIG_MMC_BLOCK=m
111CONFIG_MMC_SDHCI=m 111CONFIG_MMC_SDHCI=m
112CONFIG_NEW_LEDS=y 112CONFIG_NEW_LEDS=y
113CONFIG_LEDS_CLASS=m 113CONFIG_LEDS_CLASS=y
114CONFIG_RTC_CLASS=y 114CONFIG_RTC_CLASS=y
115CONFIG_RTC_INTF_DEV_UIE_EMUL=y 115CONFIG_RTC_INTF_DEV_UIE_EMUL=y
116CONFIG_EXT2_FS=y 116CONFIG_EXT2_FS=y
diff --git a/arch/arm/configs/s5p64x0_defconfig b/arch/arm/configs/s5p64x0_defconfig
index 2993ecd35145..ad6b61b0bd11 100644
--- a/arch/arm/configs/s5p64x0_defconfig
+++ b/arch/arm/configs/s5p64x0_defconfig
@@ -10,6 +10,8 @@ CONFIG_S3C_BOOT_ERROR_RESET=y
10CONFIG_S3C_LOWLEVEL_UART_PORT=1 10CONFIG_S3C_LOWLEVEL_UART_PORT=1
11CONFIG_MACH_SMDK6440=y 11CONFIG_MACH_SMDK6440=y
12CONFIG_MACH_SMDK6450=y 12CONFIG_MACH_SMDK6450=y
13CONFIG_NO_HZ=y
14CONFIG_HIGH_RES_TIMERS=y
13CONFIG_CPU_32v6K=y 15CONFIG_CPU_32v6K=y
14CONFIG_AEABI=y 16CONFIG_AEABI=y
15CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x20800000,8M console=ttySAC1,115200 init=/linuxrc" 17CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x20800000,8M console=ttySAC1,115200 init=/linuxrc"
diff --git a/arch/arm/configs/s5pv210_defconfig b/arch/arm/configs/s5pv210_defconfig
index 0488a1eb4d7d..fa989902236d 100644
--- a/arch/arm/configs/s5pv210_defconfig
+++ b/arch/arm/configs/s5pv210_defconfig
@@ -13,6 +13,8 @@ CONFIG_MACH_AQUILA=y
13CONFIG_MACH_GONI=y 13CONFIG_MACH_GONI=y
14CONFIG_MACH_SMDKC110=y 14CONFIG_MACH_SMDKC110=y
15CONFIG_MACH_SMDKV210=y 15CONFIG_MACH_SMDKV210=y
16CONFIG_NO_HZ=y
17CONFIG_HIGH_RES_TIMERS=y
16CONFIG_VMSPLIT_2G=y 18CONFIG_VMSPLIT_2G=y
17CONFIG_PREEMPT=y 19CONFIG_PREEMPT=y
18CONFIG_AEABI=y 20CONFIG_AEABI=y
diff --git a/arch/arm/include/asm/kexec.h b/arch/arm/include/asm/kexec.h
index c0094d8edae4..c2b9b4bdec00 100644
--- a/arch/arm/include/asm/kexec.h
+++ b/arch/arm/include/asm/kexec.h
@@ -50,6 +50,9 @@ static inline void crash_setup_regs(struct pt_regs *newregs,
50 } 50 }
51} 51}
52 52
53/* Function pointer to optional machine-specific reinitialization */
54extern void (*kexec_reinit)(void);
55
53#endif /* __ASSEMBLY__ */ 56#endif /* __ASSEMBLY__ */
54 57
55#endif /* CONFIG_KEXEC */ 58#endif /* CONFIG_KEXEC */
diff --git a/arch/arm/include/asm/pmu.h b/arch/arm/include/asm/pmu.h
index 8ccea012722c..7544ce6b481a 100644
--- a/arch/arm/include/asm/pmu.h
+++ b/arch/arm/include/asm/pmu.h
@@ -12,11 +12,25 @@
12#ifndef __ARM_PMU_H__ 12#ifndef __ARM_PMU_H__
13#define __ARM_PMU_H__ 13#define __ARM_PMU_H__
14 14
15#include <linux/interrupt.h>
16
15enum arm_pmu_type { 17enum arm_pmu_type {
16 ARM_PMU_DEVICE_CPU = 0, 18 ARM_PMU_DEVICE_CPU = 0,
17 ARM_NUM_PMU_DEVICES, 19 ARM_NUM_PMU_DEVICES,
18}; 20};
19 21
22/*
23 * struct arm_pmu_platdata - ARM PMU platform data
24 *
25 * @handle_irq: an optional handler which will be called from the interrupt and
26 * passed the address of the low level handler, and can be used to implement
27 * any platform specific handling before or after calling it.
28 */
29struct arm_pmu_platdata {
30 irqreturn_t (*handle_irq)(int irq, void *dev,
31 irq_handler_t pmu_handler);
32};
33
20#ifdef CONFIG_CPU_HAS_PMU 34#ifdef CONFIG_CPU_HAS_PMU
21 35
22/** 36/**
diff --git a/arch/arm/kernel/machine_kexec.c b/arch/arm/kernel/machine_kexec.c
index 30ead135ff5f..e59bbd496c39 100644
--- a/arch/arm/kernel/machine_kexec.c
+++ b/arch/arm/kernel/machine_kexec.c
@@ -75,6 +75,11 @@ void machine_crash_shutdown(struct pt_regs *regs)
75 printk(KERN_INFO "Loading crashdump kernel...\n"); 75 printk(KERN_INFO "Loading crashdump kernel...\n");
76} 76}
77 77
78/*
79 * Function pointer to optional machine-specific reinitialization
80 */
81void (*kexec_reinit)(void);
82
78void machine_kexec(struct kimage *image) 83void machine_kexec(struct kimage *image)
79{ 84{
80 unsigned long page_list; 85 unsigned long page_list;
@@ -104,6 +109,8 @@ void machine_kexec(struct kimage *image)
104 (unsigned long) reboot_code_buffer + KEXEC_CONTROL_PAGE_SIZE); 109 (unsigned long) reboot_code_buffer + KEXEC_CONTROL_PAGE_SIZE);
105 printk(KERN_INFO "Bye!\n"); 110 printk(KERN_INFO "Bye!\n");
106 111
112 if (kexec_reinit)
113 kexec_reinit();
107 local_irq_disable(); 114 local_irq_disable();
108 local_fiq_disable(); 115 local_fiq_disable();
109 setup_mm_for_reboot(0); /* mode is not used, so just pass 0*/ 116 setup_mm_for_reboot(0); /* mode is not used, so just pass 0*/
diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
index d150ad1ccb5d..22e194eb8536 100644
--- a/arch/arm/kernel/perf_event.c
+++ b/arch/arm/kernel/perf_event.c
@@ -377,9 +377,18 @@ validate_group(struct perf_event *event)
377 return 0; 377 return 0;
378} 378}
379 379
380static irqreturn_t armpmu_platform_irq(int irq, void *dev)
381{
382 struct arm_pmu_platdata *plat = dev_get_platdata(&pmu_device->dev);
383
384 return plat->handle_irq(irq, dev, armpmu->handle_irq);
385}
386
380static int 387static int
381armpmu_reserve_hardware(void) 388armpmu_reserve_hardware(void)
382{ 389{
390 struct arm_pmu_platdata *plat;
391 irq_handler_t handle_irq;
383 int i, err = -ENODEV, irq; 392 int i, err = -ENODEV, irq;
384 393
385 pmu_device = reserve_pmu(ARM_PMU_DEVICE_CPU); 394 pmu_device = reserve_pmu(ARM_PMU_DEVICE_CPU);
@@ -390,6 +399,12 @@ armpmu_reserve_hardware(void)
390 399
391 init_pmu(ARM_PMU_DEVICE_CPU); 400 init_pmu(ARM_PMU_DEVICE_CPU);
392 401
402 plat = dev_get_platdata(&pmu_device->dev);
403 if (plat && plat->handle_irq)
404 handle_irq = armpmu_platform_irq;
405 else
406 handle_irq = armpmu->handle_irq;
407
393 if (pmu_device->num_resources < 1) { 408 if (pmu_device->num_resources < 1) {
394 pr_err("no irqs for PMUs defined\n"); 409 pr_err("no irqs for PMUs defined\n");
395 return -ENODEV; 410 return -ENODEV;
@@ -400,7 +415,7 @@ armpmu_reserve_hardware(void)
400 if (irq < 0) 415 if (irq < 0)
401 continue; 416 continue;
402 417
403 err = request_irq(irq, armpmu->handle_irq, 418 err = request_irq(irq, handle_irq,
404 IRQF_DISABLED | IRQF_NOBALANCING, 419 IRQF_DISABLED | IRQF_NOBALANCING,
405 "armpmu", NULL); 420 "armpmu", NULL);
406 if (err) { 421 if (err) {
diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c
index b52a3a1abd94..8bc3701aa05c 100644
--- a/arch/arm/mach-davinci/board-da830-evm.c
+++ b/arch/arm/mach-davinci/board-da830-evm.c
@@ -20,6 +20,8 @@
20#include <linux/i2c/at24.h> 20#include <linux/i2c/at24.h>
21#include <linux/mtd/mtd.h> 21#include <linux/mtd/mtd.h>
22#include <linux/mtd/partitions.h> 22#include <linux/mtd/partitions.h>
23#include <linux/spi/spi.h>
24#include <linux/spi/flash.h>
23 25
24#include <asm/mach-types.h> 26#include <asm/mach-types.h>
25#include <asm/mach/arch.h> 27#include <asm/mach/arch.h>
@@ -30,6 +32,7 @@
30#include <mach/da8xx.h> 32#include <mach/da8xx.h>
31#include <mach/usb.h> 33#include <mach/usb.h>
32#include <mach/aemif.h> 34#include <mach/aemif.h>
35#include <mach/spi.h>
33 36
34#define DA830_EVM_PHY_ID "" 37#define DA830_EVM_PHY_ID ""
35/* 38/*
@@ -534,6 +537,64 @@ static struct edma_rsv_info da830_edma_rsv[] = {
534 }, 537 },
535}; 538};
536 539
540static struct mtd_partition da830evm_spiflash_part[] = {
541 [0] = {
542 .name = "DSP-UBL",
543 .offset = 0,
544 .size = SZ_8K,
545 .mask_flags = MTD_WRITEABLE,
546 },
547 [1] = {
548 .name = "ARM-UBL",
549 .offset = MTDPART_OFS_APPEND,
550 .size = SZ_16K + SZ_8K,
551 .mask_flags = MTD_WRITEABLE,
552 },
553 [2] = {
554 .name = "U-Boot",
555 .offset = MTDPART_OFS_APPEND,
556 .size = SZ_256K - SZ_32K,
557 .mask_flags = MTD_WRITEABLE,
558 },
559 [3] = {
560 .name = "U-Boot-Environment",
561 .offset = MTDPART_OFS_APPEND,
562 .size = SZ_16K,
563 .mask_flags = 0,
564 },
565 [4] = {
566 .name = "Kernel",
567 .offset = MTDPART_OFS_APPEND,
568 .size = MTDPART_SIZ_FULL,
569 .mask_flags = 0,
570 },
571};
572
573static struct flash_platform_data da830evm_spiflash_data = {
574 .name = "m25p80",
575 .parts = da830evm_spiflash_part,
576 .nr_parts = ARRAY_SIZE(da830evm_spiflash_part),
577 .type = "w25x32",
578};
579
580static struct davinci_spi_config da830evm_spiflash_cfg = {
581 .io_type = SPI_IO_TYPE_DMA,
582 .c2tdelay = 8,
583 .t2cdelay = 8,
584};
585
586static struct spi_board_info da830evm_spi_info[] = {
587 {
588 .modalias = "m25p80",
589 .platform_data = &da830evm_spiflash_data,
590 .controller_data = &da830evm_spiflash_cfg,
591 .mode = SPI_MODE_0,
592 .max_speed_hz = 30000000,
593 .bus_num = 0,
594 .chip_select = 0,
595 },
596};
597
537static __init void da830_evm_init(void) 598static __init void da830_evm_init(void)
538{ 599{
539 struct davinci_soc_info *soc_info = &davinci_soc_info; 600 struct davinci_soc_info *soc_info = &davinci_soc_info;
@@ -590,6 +651,12 @@ static __init void da830_evm_init(void)
590 ret = da8xx_register_rtc(); 651 ret = da8xx_register_rtc();
591 if (ret) 652 if (ret)
592 pr_warning("da830_evm_init: rtc setup failed: %d\n", ret); 653 pr_warning("da830_evm_init: rtc setup failed: %d\n", ret);
654
655 ret = da8xx_register_spi(0, da830evm_spi_info,
656 ARRAY_SIZE(da830evm_spi_info));
657 if (ret)
658 pr_warning("da830_evm_init: spi 0 registration failed: %d\n",
659 ret);
593} 660}
594 661
595#ifdef CONFIG_SERIAL_8250_CONSOLE 662#ifdef CONFIG_SERIAL_8250_CONSOLE
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index b01fb2ab944a..a7b41bf505f1 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -29,6 +29,8 @@
29#include <linux/regulator/machine.h> 29#include <linux/regulator/machine.h>
30#include <linux/regulator/tps6507x.h> 30#include <linux/regulator/tps6507x.h>
31#include <linux/input/tps6507x-ts.h> 31#include <linux/input/tps6507x-ts.h>
32#include <linux/spi/spi.h>
33#include <linux/spi/flash.h>
32 34
33#include <asm/mach-types.h> 35#include <asm/mach-types.h>
34#include <asm/mach/arch.h> 36#include <asm/mach/arch.h>
@@ -38,6 +40,7 @@
38#include <mach/nand.h> 40#include <mach/nand.h>
39#include <mach/mux.h> 41#include <mach/mux.h>
40#include <mach/aemif.h> 42#include <mach/aemif.h>
43#include <mach/spi.h>
41 44
42#define DA850_EVM_PHY_ID "0:00" 45#define DA850_EVM_PHY_ID "0:00"
43#define DA850_LCD_PWR_PIN GPIO_TO_PIN(2, 8) 46#define DA850_LCD_PWR_PIN GPIO_TO_PIN(2, 8)
@@ -48,6 +51,70 @@
48 51
49#define DA850_MII_MDIO_CLKEN_PIN GPIO_TO_PIN(2, 6) 52#define DA850_MII_MDIO_CLKEN_PIN GPIO_TO_PIN(2, 6)
50 53
54static struct mtd_partition da850evm_spiflash_part[] = {
55 [0] = {
56 .name = "UBL",
57 .offset = 0,
58 .size = SZ_64K,
59 .mask_flags = MTD_WRITEABLE,
60 },
61 [1] = {
62 .name = "U-Boot",
63 .offset = MTDPART_OFS_APPEND,
64 .size = SZ_512K,
65 .mask_flags = MTD_WRITEABLE,
66 },
67 [2] = {
68 .name = "U-Boot-Env",
69 .offset = MTDPART_OFS_APPEND,
70 .size = SZ_64K,
71 .mask_flags = MTD_WRITEABLE,
72 },
73 [3] = {
74 .name = "Kernel",
75 .offset = MTDPART_OFS_APPEND,
76 .size = SZ_2M + SZ_512K,
77 .mask_flags = 0,
78 },
79 [4] = {
80 .name = "Filesystem",
81 .offset = MTDPART_OFS_APPEND,
82 .size = SZ_4M,
83 .mask_flags = 0,
84 },
85 [5] = {
86 .name = "MAC-Address",
87 .offset = SZ_8M - SZ_64K,
88 .size = SZ_64K,
89 .mask_flags = MTD_WRITEABLE,
90 },
91};
92
93static struct flash_platform_data da850evm_spiflash_data = {
94 .name = "m25p80",
95 .parts = da850evm_spiflash_part,
96 .nr_parts = ARRAY_SIZE(da850evm_spiflash_part),
97 .type = "m25p64",
98};
99
100static struct davinci_spi_config da850evm_spiflash_cfg = {
101 .io_type = SPI_IO_TYPE_DMA,
102 .c2tdelay = 8,
103 .t2cdelay = 8,
104};
105
106static struct spi_board_info da850evm_spi_info[] = {
107 {
108 .modalias = "m25p80",
109 .platform_data = &da850evm_spiflash_data,
110 .controller_data = &da850evm_spiflash_cfg,
111 .mode = SPI_MODE_0,
112 .max_speed_hz = 30000000,
113 .bus_num = 1,
114 .chip_select = 0,
115 },
116};
117
51static struct mtd_partition da850_evm_norflash_partition[] = { 118static struct mtd_partition da850_evm_norflash_partition[] = {
52 { 119 {
53 .name = "bootloaders + env", 120 .name = "bootloaders + env",
@@ -231,8 +298,6 @@ static const short da850_evm_nor_pins[] = {
231 -1 298 -1
232}; 299};
233 300
234static u32 ui_card_detected;
235
236#if defined(CONFIG_MMC_DAVINCI) || \ 301#if defined(CONFIG_MMC_DAVINCI) || \
237 defined(CONFIG_MMC_DAVINCI_MODULE) 302 defined(CONFIG_MMC_DAVINCI_MODULE)
238#define HAS_MMC 1 303#define HAS_MMC 1
@@ -244,7 +309,7 @@ static inline void da850_evm_setup_nor_nand(void)
244{ 309{
245 int ret = 0; 310 int ret = 0;
246 311
247 if (ui_card_detected & !HAS_MMC) { 312 if (!HAS_MMC) {
248 ret = davinci_cfg_reg_list(da850_evm_nand_pins); 313 ret = davinci_cfg_reg_list(da850_evm_nand_pins);
249 if (ret) 314 if (ret)
250 pr_warning("da850_evm_init: nand mux setup failed: " 315 pr_warning("da850_evm_init: nand mux setup failed: "
@@ -394,7 +459,6 @@ static int da850_evm_ui_expander_setup(struct i2c_client *client, unsigned gpio,
394 goto exp_setup_keys_fail; 459 goto exp_setup_keys_fail;
395 } 460 }
396 461
397 ui_card_detected = 1;
398 pr_info("DA850/OMAP-L138 EVM UI card detected\n"); 462 pr_info("DA850/OMAP-L138 EVM UI card detected\n");
399 463
400 da850_evm_setup_nor_nand(); 464 da850_evm_setup_nor_nand();
@@ -664,6 +728,13 @@ static struct snd_platform_data da850_evm_snd_data = {
664 .rxnumevt = 1, 728 .rxnumevt = 1,
665}; 729};
666 730
731static const short da850_evm_mcasp_pins[] __initconst = {
732 DA850_AHCLKX, DA850_ACLKX, DA850_AFSX,
733 DA850_AHCLKR, DA850_ACLKR, DA850_AFSR, DA850_AMUTE,
734 DA850_AXR_11, DA850_AXR_12,
735 -1
736};
737
667static int da850_evm_mmc_get_ro(int index) 738static int da850_evm_mmc_get_ro(int index)
668{ 739{
669 return gpio_get_value(DA850_MMCSD_WP_PIN); 740 return gpio_get_value(DA850_MMCSD_WP_PIN);
@@ -683,6 +754,13 @@ static struct davinci_mmc_config da850_mmc_config = {
683 .version = MMC_CTLR_VERSION_2, 754 .version = MMC_CTLR_VERSION_2,
684}; 755};
685 756
757static const short da850_evm_mmcsd0_pins[] __initconst = {
758 DA850_MMCSD0_DAT_0, DA850_MMCSD0_DAT_1, DA850_MMCSD0_DAT_2,
759 DA850_MMCSD0_DAT_3, DA850_MMCSD0_CLK, DA850_MMCSD0_CMD,
760 DA850_GPIO4_0, DA850_GPIO4_1,
761 -1
762};
763
686static void da850_panel_power_ctrl(int val) 764static void da850_panel_power_ctrl(int val)
687{ 765{
688 /* lcd backlight */ 766 /* lcd backlight */
@@ -1070,7 +1148,7 @@ static __init void da850_evm_init(void)
1070 ret); 1148 ret);
1071 1149
1072 if (HAS_MMC) { 1150 if (HAS_MMC) {
1073 ret = davinci_cfg_reg_list(da850_mmcsd0_pins); 1151 ret = davinci_cfg_reg_list(da850_evm_mmcsd0_pins);
1074 if (ret) 1152 if (ret)
1075 pr_warning("da850_evm_init: mmcsd0 mux setup failed:" 1153 pr_warning("da850_evm_init: mmcsd0 mux setup failed:"
1076 " %d\n", ret); 1154 " %d\n", ret);
@@ -1106,7 +1184,7 @@ static __init void da850_evm_init(void)
1106 __raw_writel(0, IO_ADDRESS(DA8XX_UART1_BASE) + 0x30); 1184 __raw_writel(0, IO_ADDRESS(DA8XX_UART1_BASE) + 0x30);
1107 __raw_writel(0, IO_ADDRESS(DA8XX_UART0_BASE) + 0x30); 1185 __raw_writel(0, IO_ADDRESS(DA8XX_UART0_BASE) + 0x30);
1108 1186
1109 ret = davinci_cfg_reg_list(da850_mcasp_pins); 1187 ret = davinci_cfg_reg_list(da850_evm_mcasp_pins);
1110 if (ret) 1188 if (ret)
1111 pr_warning("da850_evm_init: mcasp mux setup failed: %d\n", 1189 pr_warning("da850_evm_init: mcasp mux setup failed: %d\n",
1112 ret); 1190 ret);
@@ -1153,6 +1231,12 @@ static __init void da850_evm_init(void)
1153 if (ret) 1231 if (ret)
1154 pr_warning("da850_evm_init: suspend registration failed: %d\n", 1232 pr_warning("da850_evm_init: suspend registration failed: %d\n",
1155 ret); 1233 ret);
1234
1235 ret = da8xx_register_spi(1, da850evm_spi_info,
1236 ARRAY_SIZE(da850evm_spi_info));
1237 if (ret)
1238 pr_warning("da850_evm_init: spi 1 registration failed: %d\n",
1239 ret);
1156} 1240}
1157 1241
1158#ifdef CONFIG_SERIAL_8250_CONSOLE 1242#ifdef CONFIG_SERIAL_8250_CONSOLE
diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c
index 0ca90b834586..556bbd468db3 100644
--- a/arch/arm/mach-davinci/board-dm644x-evm.c
+++ b/arch/arm/mach-davinci/board-dm644x-evm.c
@@ -440,11 +440,6 @@ evm_u35_setup(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
440 gpio_request(gpio + 7, "nCF_SEL"); 440 gpio_request(gpio + 7, "nCF_SEL");
441 gpio_direction_output(gpio + 7, 1); 441 gpio_direction_output(gpio + 7, 1);
442 442
443 /* irlml6401 switches over 1A, in under 8 msec;
444 * now it can be managed by nDRV_VBUS ...
445 */
446 davinci_setup_usb(1000, 8);
447
448 return 0; 443 return 0;
449} 444}
450 445
@@ -705,6 +700,9 @@ static __init void davinci_evm_init(void)
705 davinci_serial_init(&uart_config); 700 davinci_serial_init(&uart_config);
706 dm644x_init_asp(&dm644x_evm_snd_data); 701 dm644x_init_asp(&dm644x_evm_snd_data);
707 702
703 /* irlml6401 switches over 1A, in under 8 msec */
704 davinci_setup_usb(1000, 8);
705
708 soc_info->emac_pdata->phy_id = DM644X_EVM_PHY_ID; 706 soc_info->emac_pdata->phy_id = DM644X_EVM_PHY_ID;
709 /* Register the fixup for PHY on DaVinci */ 707 /* Register the fixup for PHY on DaVinci */
710 phy_register_fixup_for_uid(LXT971_PHY_ID, LXT971_PHY_MASK, 708 phy_register_fixup_for_uid(LXT971_PHY_ID, LXT971_PHY_MASK,
diff --git a/arch/arm/mach-davinci/board-mityomapl138.c b/arch/arm/mach-davinci/board-mityomapl138.c
index 0bb5f0ce4fdc..2aa79c54f98e 100644
--- a/arch/arm/mach-davinci/board-mityomapl138.c
+++ b/arch/arm/mach-davinci/board-mityomapl138.c
@@ -17,6 +17,8 @@
17#include <linux/i2c.h> 17#include <linux/i2c.h>
18#include <linux/i2c/at24.h> 18#include <linux/i2c/at24.h>
19#include <linux/etherdevice.h> 19#include <linux/etherdevice.h>
20#include <linux/spi/spi.h>
21#include <linux/spi/flash.h>
20 22
21#include <asm/mach-types.h> 23#include <asm/mach-types.h>
22#include <asm/mach/arch.h> 24#include <asm/mach/arch.h>
@@ -25,6 +27,7 @@
25#include <mach/da8xx.h> 27#include <mach/da8xx.h>
26#include <mach/nand.h> 28#include <mach/nand.h>
27#include <mach/mux.h> 29#include <mach/mux.h>
30#include <mach/spi.h>
28 31
29#define MITYOMAPL138_PHY_ID "0:03" 32#define MITYOMAPL138_PHY_ID "0:03"
30 33
@@ -44,38 +47,109 @@ struct factory_config {
44 47
45static struct factory_config factory_config; 48static struct factory_config factory_config;
46 49
50struct part_no_info {
51 const char *part_no; /* part number string of interest */
52 int max_freq; /* khz */
53};
54
55static struct part_no_info mityomapl138_pn_info[] = {
56 {
57 .part_no = "L138-C",
58 .max_freq = 300000,
59 },
60 {
61 .part_no = "L138-D",
62 .max_freq = 375000,
63 },
64 {
65 .part_no = "L138-F",
66 .max_freq = 456000,
67 },
68 {
69 .part_no = "1808-C",
70 .max_freq = 300000,
71 },
72 {
73 .part_no = "1808-D",
74 .max_freq = 375000,
75 },
76 {
77 .part_no = "1808-F",
78 .max_freq = 456000,
79 },
80 {
81 .part_no = "1810-D",
82 .max_freq = 375000,
83 },
84};
85
86#ifdef CONFIG_CPU_FREQ
87static void mityomapl138_cpufreq_init(const char *partnum)
88{
89 int i, ret;
90
91 for (i = 0; partnum && i < ARRAY_SIZE(mityomapl138_pn_info); i++) {
92 /*
93 * the part number has additional characters beyond what is
94 * stored in the table. This information is not needed for
95 * determining the speed grade, and would require several
96 * more table entries. Only check the first N characters
97 * for a match.
98 */
99 if (!strncmp(partnum, mityomapl138_pn_info[i].part_no,
100 strlen(mityomapl138_pn_info[i].part_no))) {
101 da850_max_speed = mityomapl138_pn_info[i].max_freq;
102 break;
103 }
104 }
105
106 ret = da850_register_cpufreq("pll0_sysclk3");
107 if (ret)
108 pr_warning("cpufreq registration failed: %d\n", ret);
109}
110#else
111static void mityomapl138_cpufreq_init(const char *partnum) { }
112#endif
113
47static void read_factory_config(struct memory_accessor *a, void *context) 114static void read_factory_config(struct memory_accessor *a, void *context)
48{ 115{
49 int ret; 116 int ret;
117 const char *partnum = NULL;
50 struct davinci_soc_info *soc_info = &davinci_soc_info; 118 struct davinci_soc_info *soc_info = &davinci_soc_info;
51 119
52 ret = a->read(a, (char *)&factory_config, 0, sizeof(factory_config)); 120 ret = a->read(a, (char *)&factory_config, 0, sizeof(factory_config));
53 if (ret != sizeof(struct factory_config)) { 121 if (ret != sizeof(struct factory_config)) {
54 pr_warning("MityOMAPL138: Read Factory Config Failed: %d\n", 122 pr_warning("MityOMAPL138: Read Factory Config Failed: %d\n",
55 ret); 123 ret);
56 return; 124 goto bad_config;
57 } 125 }
58 126
59 if (factory_config.magic != FACTORY_CONFIG_MAGIC) { 127 if (factory_config.magic != FACTORY_CONFIG_MAGIC) {
60 pr_warning("MityOMAPL138: Factory Config Magic Wrong (%X)\n", 128 pr_warning("MityOMAPL138: Factory Config Magic Wrong (%X)\n",
61 factory_config.magic); 129 factory_config.magic);
62 return; 130 goto bad_config;
63 } 131 }
64 132
65 if (factory_config.version != FACTORY_CONFIG_VERSION) { 133 if (factory_config.version != FACTORY_CONFIG_VERSION) {
66 pr_warning("MityOMAPL138: Factory Config Version Wrong (%X)\n", 134 pr_warning("MityOMAPL138: Factory Config Version Wrong (%X)\n",
67 factory_config.version); 135 factory_config.version);
68 return; 136 goto bad_config;
69 } 137 }
70 138
71 pr_info("MityOMAPL138: Found MAC = %pM\n", factory_config.mac); 139 pr_info("MityOMAPL138: Found MAC = %pM\n", factory_config.mac);
72 pr_info("MityOMAPL138: Part Number = %s\n", factory_config.partnum);
73 if (is_valid_ether_addr(factory_config.mac)) 140 if (is_valid_ether_addr(factory_config.mac))
74 memcpy(soc_info->emac_pdata->mac_addr, 141 memcpy(soc_info->emac_pdata->mac_addr,
75 factory_config.mac, ETH_ALEN); 142 factory_config.mac, ETH_ALEN);
76 else 143 else
77 pr_warning("MityOMAPL138: Invalid MAC found " 144 pr_warning("MityOMAPL138: Invalid MAC found "
78 "in factory config block\n"); 145 "in factory config block\n");
146
147 partnum = factory_config.partnum;
148 pr_info("MityOMAPL138: Part Number = %s\n", partnum);
149
150bad_config:
151 /* default maximum speed is valid for all platforms */
152 mityomapl138_cpufreq_init(partnum);
79} 153}
80 154
81static struct at24_platform_data mityomapl138_fd_chip = { 155static struct at24_platform_data mityomapl138_fd_chip = {
@@ -223,6 +297,82 @@ static int __init pmic_tps65023_init(void)
223} 297}
224 298
225/* 299/*
300 * SPI Devices:
301 * SPI1_CS0: 8M Flash ST-M25P64-VME6G
302 */
303static struct mtd_partition spi_flash_partitions[] = {
304 [0] = {
305 .name = "ubl",
306 .offset = 0,
307 .size = SZ_64K,
308 .mask_flags = MTD_WRITEABLE,
309 },
310 [1] = {
311 .name = "u-boot",
312 .offset = MTDPART_OFS_APPEND,
313 .size = SZ_512K,
314 .mask_flags = MTD_WRITEABLE,
315 },
316 [2] = {
317 .name = "u-boot-env",
318 .offset = MTDPART_OFS_APPEND,
319 .size = SZ_64K,
320 .mask_flags = MTD_WRITEABLE,
321 },
322 [3] = {
323 .name = "periph-config",
324 .offset = MTDPART_OFS_APPEND,
325 .size = SZ_64K,
326 .mask_flags = MTD_WRITEABLE,
327 },
328 [4] = {
329 .name = "reserved",
330 .offset = MTDPART_OFS_APPEND,
331 .size = SZ_256K + SZ_64K,
332 },
333 [5] = {
334 .name = "kernel",
335 .offset = MTDPART_OFS_APPEND,
336 .size = SZ_2M + SZ_1M,
337 },
338 [6] = {
339 .name = "fpga",
340 .offset = MTDPART_OFS_APPEND,
341 .size = SZ_2M,
342 },
343 [7] = {
344 .name = "spare",
345 .offset = MTDPART_OFS_APPEND,
346 .size = MTDPART_SIZ_FULL,
347 },
348};
349
350static struct flash_platform_data mityomapl138_spi_flash_data = {
351 .name = "m25p80",
352 .parts = spi_flash_partitions,
353 .nr_parts = ARRAY_SIZE(spi_flash_partitions),
354 .type = "m24p64",
355};
356
357static struct davinci_spi_config spi_eprom_config = {
358 .io_type = SPI_IO_TYPE_DMA,
359 .c2tdelay = 8,
360 .t2cdelay = 8,
361};
362
363static struct spi_board_info mityomapl138_spi_flash_info[] = {
364 {
365 .modalias = "m25p80",
366 .platform_data = &mityomapl138_spi_flash_data,
367 .controller_data = &spi_eprom_config,
368 .mode = SPI_MODE_0,
369 .max_speed_hz = 30000000,
370 .bus_num = 1,
371 .chip_select = 0,
372 },
373};
374
375/*
226 * MityDSP-L138 includes a 256 MByte large-page NAND flash 376 * MityDSP-L138 includes a 256 MByte large-page NAND flash
227 * (128K blocks). 377 * (128K blocks).
228 */ 378 */
@@ -377,16 +527,17 @@ static void __init mityomapl138_init(void)
377 527
378 mityomapl138_setup_nand(); 528 mityomapl138_setup_nand();
379 529
530 ret = da8xx_register_spi(1, mityomapl138_spi_flash_info,
531 ARRAY_SIZE(mityomapl138_spi_flash_info));
532 if (ret)
533 pr_warning("spi 1 registration failed: %d\n", ret);
534
380 mityomapl138_config_emac(); 535 mityomapl138_config_emac();
381 536
382 ret = da8xx_register_rtc(); 537 ret = da8xx_register_rtc();
383 if (ret) 538 if (ret)
384 pr_warning("rtc setup failed: %d\n", ret); 539 pr_warning("rtc setup failed: %d\n", ret);
385 540
386 ret = da850_register_cpufreq("pll0_sysclk3");
387 if (ret)
388 pr_warning("cpufreq registration failed: %d\n", ret);
389
390 ret = da8xx_register_cpuidle(); 541 ret = da8xx_register_cpuidle();
391 if (ret) 542 if (ret)
392 pr_warning("cpuidle registration failed: %d\n", ret); 543 pr_warning("cpuidle registration failed: %d\n", ret);
diff --git a/arch/arm/mach-davinci/board-omapl138-hawk.c b/arch/arm/mach-davinci/board-omapl138-hawk.c
index 0b8dbdb79fe0..67c38d0ecd10 100644
--- a/arch/arm/mach-davinci/board-omapl138-hawk.c
+++ b/arch/arm/mach-davinci/board-omapl138-hawk.c
@@ -19,6 +19,279 @@
19 19
20#include <mach/cp_intc.h> 20#include <mach/cp_intc.h>
21#include <mach/da8xx.h> 21#include <mach/da8xx.h>
22#include <mach/mux.h>
23
24#define HAWKBOARD_PHY_ID "0:07"
25#define DA850_HAWK_MMCSD_CD_PIN GPIO_TO_PIN(3, 12)
26#define DA850_HAWK_MMCSD_WP_PIN GPIO_TO_PIN(3, 13)
27
28#define DA850_USB1_VBUS_PIN GPIO_TO_PIN(2, 4)
29#define DA850_USB1_OC_PIN GPIO_TO_PIN(6, 13)
30
31static short omapl138_hawk_mii_pins[] __initdata = {
32 DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3,
33 DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER,
34 DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3,
35 DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK,
36 DA850_MDIO_D,
37 -1
38};
39
40static __init void omapl138_hawk_config_emac(void)
41{
42 void __iomem *cfgchip3 = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG);
43 int ret;
44 u32 val;
45 struct davinci_soc_info *soc_info = &davinci_soc_info;
46
47 val = __raw_readl(cfgchip3);
48 val &= ~BIT(8);
49 ret = davinci_cfg_reg_list(omapl138_hawk_mii_pins);
50 if (ret) {
51 pr_warning("%s: cpgmac/mii mux setup failed: %d\n",
52 __func__, ret);
53 return;
54 }
55
56 /* configure the CFGCHIP3 register for MII */
57 __raw_writel(val, cfgchip3);
58 pr_info("EMAC: MII PHY configured\n");
59
60 soc_info->emac_pdata->phy_id = HAWKBOARD_PHY_ID;
61
62 ret = da8xx_register_emac();
63 if (ret)
64 pr_warning("%s: emac registration failed: %d\n",
65 __func__, ret);
66}
67
68/*
69 * The following EDMA channels/slots are not being used by drivers (for
70 * example: Timer, GPIO, UART events etc) on da850/omap-l138 EVM/Hawkboard,
71 * hence they are being reserved for codecs on the DSP side.
72 */
73static const s16 da850_dma0_rsv_chans[][2] = {
74 /* (offset, number) */
75 { 8, 6},
76 {24, 4},
77 {30, 2},
78 {-1, -1}
79};
80
81static const s16 da850_dma0_rsv_slots[][2] = {
82 /* (offset, number) */
83 { 8, 6},
84 {24, 4},
85 {30, 50},
86 {-1, -1}
87};
88
89static const s16 da850_dma1_rsv_chans[][2] = {
90 /* (offset, number) */
91 { 0, 28},
92 {30, 2},
93 {-1, -1}
94};
95
96static const s16 da850_dma1_rsv_slots[][2] = {
97 /* (offset, number) */
98 { 0, 28},
99 {30, 90},
100 {-1, -1}
101};
102
103static struct edma_rsv_info da850_edma_cc0_rsv = {
104 .rsv_chans = da850_dma0_rsv_chans,
105 .rsv_slots = da850_dma0_rsv_slots,
106};
107
108static struct edma_rsv_info da850_edma_cc1_rsv = {
109 .rsv_chans = da850_dma1_rsv_chans,
110 .rsv_slots = da850_dma1_rsv_slots,
111};
112
113static struct edma_rsv_info *da850_edma_rsv[2] = {
114 &da850_edma_cc0_rsv,
115 &da850_edma_cc1_rsv,
116};
117
118static const short hawk_mmcsd0_pins[] = {
119 DA850_MMCSD0_DAT_0, DA850_MMCSD0_DAT_1, DA850_MMCSD0_DAT_2,
120 DA850_MMCSD0_DAT_3, DA850_MMCSD0_CLK, DA850_MMCSD0_CMD,
121 DA850_GPIO3_12, DA850_GPIO3_13,
122 -1
123};
124
125static int da850_hawk_mmc_get_ro(int index)
126{
127 return gpio_get_value(DA850_HAWK_MMCSD_WP_PIN);
128}
129
130static int da850_hawk_mmc_get_cd(int index)
131{
132 return !gpio_get_value(DA850_HAWK_MMCSD_CD_PIN);
133}
134
135static struct davinci_mmc_config da850_mmc_config = {
136 .get_ro = da850_hawk_mmc_get_ro,
137 .get_cd = da850_hawk_mmc_get_cd,
138 .wires = 4,
139 .max_freq = 50000000,
140 .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
141 .version = MMC_CTLR_VERSION_2,
142};
143
144static __init void omapl138_hawk_mmc_init(void)
145{
146 int ret;
147
148 ret = davinci_cfg_reg_list(hawk_mmcsd0_pins);
149 if (ret) {
150 pr_warning("%s: MMC/SD0 mux setup failed: %d\n",
151 __func__, ret);
152 return;
153 }
154
155 ret = gpio_request_one(DA850_HAWK_MMCSD_CD_PIN,
156 GPIOF_DIR_IN, "MMC CD");
157 if (ret < 0) {
158 pr_warning("%s: can not open GPIO %d\n",
159 __func__, DA850_HAWK_MMCSD_CD_PIN);
160 return;
161 }
162
163 ret = gpio_request_one(DA850_HAWK_MMCSD_WP_PIN,
164 GPIOF_DIR_IN, "MMC WP");
165 if (ret < 0) {
166 pr_warning("%s: can not open GPIO %d\n",
167 __func__, DA850_HAWK_MMCSD_WP_PIN);
168 goto mmc_setup_wp_fail;
169 }
170
171 ret = da8xx_register_mmcsd0(&da850_mmc_config);
172 if (ret) {
173 pr_warning("%s: MMC/SD0 registration failed: %d\n",
174 __func__, ret);
175 goto mmc_setup_mmcsd_fail;
176 }
177
178 return;
179
180mmc_setup_mmcsd_fail:
181 gpio_free(DA850_HAWK_MMCSD_WP_PIN);
182mmc_setup_wp_fail:
183 gpio_free(DA850_HAWK_MMCSD_CD_PIN);
184}
185
186static irqreturn_t omapl138_hawk_usb_ocic_irq(int irq, void *dev_id);
187static da8xx_ocic_handler_t hawk_usb_ocic_handler;
188
189static const short da850_hawk_usb11_pins[] = {
190 DA850_GPIO2_4, DA850_GPIO6_13,
191 -1
192};
193
194static int hawk_usb_set_power(unsigned port, int on)
195{
196 gpio_set_value(DA850_USB1_VBUS_PIN, on);
197 return 0;
198}
199
200static int hawk_usb_get_power(unsigned port)
201{
202 return gpio_get_value(DA850_USB1_VBUS_PIN);
203}
204
205static int hawk_usb_get_oci(unsigned port)
206{
207 return !gpio_get_value(DA850_USB1_OC_PIN);
208}
209
210static int hawk_usb_ocic_notify(da8xx_ocic_handler_t handler)
211{
212 int irq = gpio_to_irq(DA850_USB1_OC_PIN);
213 int error = 0;
214
215 if (handler != NULL) {
216 hawk_usb_ocic_handler = handler;
217
218 error = request_irq(irq, omapl138_hawk_usb_ocic_irq,
219 IRQF_DISABLED | IRQF_TRIGGER_RISING |
220 IRQF_TRIGGER_FALLING,
221 "OHCI over-current indicator", NULL);
222 if (error)
223 pr_err("%s: could not request IRQ to watch "
224 "over-current indicator changes\n", __func__);
225 } else {
226 free_irq(irq, NULL);
227 }
228 return error;
229}
230
231static struct da8xx_ohci_root_hub omapl138_hawk_usb11_pdata = {
232 .set_power = hawk_usb_set_power,
233 .get_power = hawk_usb_get_power,
234 .get_oci = hawk_usb_get_oci,
235 .ocic_notify = hawk_usb_ocic_notify,
236 /* TPS2087 switch @ 5V */
237 .potpgt = (3 + 1) / 2, /* 3 ms max */
238};
239
240static irqreturn_t omapl138_hawk_usb_ocic_irq(int irq, void *dev_id)
241{
242 hawk_usb_ocic_handler(&omapl138_hawk_usb11_pdata, 1);
243 return IRQ_HANDLED;
244}
245
246static __init void omapl138_hawk_usb_init(void)
247{
248 int ret;
249 u32 cfgchip2;
250
251 ret = davinci_cfg_reg_list(da850_hawk_usb11_pins);
252 if (ret) {
253 pr_warning("%s: USB 1.1 PinMux setup failed: %d\n",
254 __func__, ret);
255 return;
256 }
257
258 /* Setup the Ref. clock frequency for the HAWK at 24 MHz. */
259
260 cfgchip2 = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
261 cfgchip2 &= ~CFGCHIP2_REFFREQ;
262 cfgchip2 |= CFGCHIP2_REFFREQ_24MHZ;
263 __raw_writel(cfgchip2, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
264
265 ret = gpio_request_one(DA850_USB1_VBUS_PIN,
266 GPIOF_DIR_OUT, "USB1 VBUS");
267 if (ret < 0) {
268 pr_err("%s: failed to request GPIO for USB 1.1 port "
269 "power control: %d\n", __func__, ret);
270 return;
271 }
272
273 ret = gpio_request_one(DA850_USB1_OC_PIN,
274 GPIOF_DIR_IN, "USB1 OC");
275 if (ret < 0) {
276 pr_err("%s: failed to request GPIO for USB 1.1 port "
277 "over-current indicator: %d\n", __func__, ret);
278 goto usb11_setup_oc_fail;
279 }
280
281 ret = da8xx_register_usb11(&omapl138_hawk_usb11_pdata);
282 if (ret) {
283 pr_warning("%s: USB 1.1 registration failed: %d\n",
284 __func__, ret);
285 goto usb11_setup_fail;
286 }
287
288 return;
289
290usb11_setup_fail:
291 gpio_free(DA850_USB1_OC_PIN);
292usb11_setup_oc_fail:
293 gpio_free(DA850_USB1_VBUS_PIN);
294}
22 295
23static struct davinci_uart_config omapl138_hawk_uart_config __initdata = { 296static struct davinci_uart_config omapl138_hawk_uart_config __initdata = {
24 .enabled_uarts = 0x7, 297 .enabled_uarts = 0x7,
@@ -30,6 +303,17 @@ static __init void omapl138_hawk_init(void)
30 303
31 davinci_serial_init(&omapl138_hawk_uart_config); 304 davinci_serial_init(&omapl138_hawk_uart_config);
32 305
306 omapl138_hawk_config_emac();
307
308 ret = da850_register_edma(da850_edma_rsv);
309 if (ret)
310 pr_warning("%s: EDMA registration failed: %d\n",
311 __func__, ret);
312
313 omapl138_hawk_mmc_init();
314
315 omapl138_hawk_usb_init();
316
33 ret = da8xx_register_watchdog(); 317 ret = da8xx_register_watchdog();
34 if (ret) 318 if (ret)
35 pr_warning("omapl138_hawk_init: " 319 pr_warning("omapl138_hawk_init: "
diff --git a/arch/arm/mach-davinci/board-tnetv107x-evm.c b/arch/arm/mach-davinci/board-tnetv107x-evm.c
index a6db85460227..1a656e882262 100644
--- a/arch/arm/mach-davinci/board-tnetv107x-evm.c
+++ b/arch/arm/mach-davinci/board-tnetv107x-evm.c
@@ -25,6 +25,7 @@
25#include <linux/mtd/partitions.h> 25#include <linux/mtd/partitions.h>
26#include <linux/input.h> 26#include <linux/input.h>
27#include <linux/input/matrix_keypad.h> 27#include <linux/input/matrix_keypad.h>
28#include <linux/spi/spi.h>
28 29
29#include <asm/mach/arch.h> 30#include <asm/mach/arch.h>
30#include <asm/mach-types.h> 31#include <asm/mach-types.h>
@@ -37,6 +38,7 @@
37 38
38#define EVM_MMC_WP_GPIO 21 39#define EVM_MMC_WP_GPIO 21
39#define EVM_MMC_CD_GPIO 24 40#define EVM_MMC_CD_GPIO 24
41#define EVM_SPI_CS_GPIO 54
40 42
41static int initialize_gpio(int gpio, char *desc) 43static int initialize_gpio(int gpio, char *desc)
42{ 44{
@@ -99,6 +101,12 @@ static const short uart1_pins[] __initdata = {
99 -1 101 -1
100}; 102};
101 103
104static const short ssp_pins[] __initdata = {
105 TNETV107X_SSP0_0, TNETV107X_SSP0_1, TNETV107X_SSP0_2,
106 TNETV107X_SSP1_0, TNETV107X_SSP1_1, TNETV107X_SSP1_2,
107 TNETV107X_SSP1_3, -1
108};
109
102static struct mtd_partition nand_partitions[] = { 110static struct mtd_partition nand_partitions[] = {
103 /* bootloader (U-Boot, etc) in first 12 sectors */ 111 /* bootloader (U-Boot, etc) in first 12 sectors */
104 { 112 {
@@ -196,19 +204,68 @@ static struct matrix_keypad_platform_data keypad_config = {
196 .no_autorepeat = 0, 204 .no_autorepeat = 0,
197}; 205};
198 206
207static void spi_select_device(int cs)
208{
209 static int gpio;
210
211 if (!gpio) {
212 int ret;
213 ret = gpio_request(EVM_SPI_CS_GPIO, "spi chipsel");
214 if (ret < 0) {
215 pr_err("cannot open spi chipsel gpio\n");
216 gpio = -ENOSYS;
217 return;
218 } else {
219 gpio = EVM_SPI_CS_GPIO;
220 gpio_direction_output(gpio, 0);
221 }
222 }
223
224 if (gpio < 0)
225 return;
226
227 return gpio_set_value(gpio, cs ? 1 : 0);
228}
229
230static struct ti_ssp_spi_data spi_master_data = {
231 .num_cs = 2,
232 .select = spi_select_device,
233 .iosel = SSP_PIN_SEL(0, SSP_CLOCK) | SSP_PIN_SEL(1, SSP_DATA) |
234 SSP_PIN_SEL(2, SSP_CHIPSEL) | SSP_PIN_SEL(3, SSP_IN) |
235 SSP_INPUT_SEL(3),
236};
237
238static struct ti_ssp_data ssp_config = {
239 .out_clock = 250 * 1000,
240 .dev_data = {
241 [1] = {
242 .dev_name = "ti-ssp-spi",
243 .pdata = &spi_master_data,
244 .pdata_size = sizeof(spi_master_data),
245 },
246 },
247};
248
199static struct tnetv107x_device_info evm_device_info __initconst = { 249static struct tnetv107x_device_info evm_device_info __initconst = {
200 .serial_config = &serial_config, 250 .serial_config = &serial_config,
201 .mmc_config[1] = &mmc_config, /* controller 1 */ 251 .mmc_config[1] = &mmc_config, /* controller 1 */
202 .nand_config[0] = &nand_config, /* chip select 0 */ 252 .nand_config[0] = &nand_config, /* chip select 0 */
203 .keypad_config = &keypad_config, 253 .keypad_config = &keypad_config,
254 .ssp_config = &ssp_config,
255};
256
257static struct spi_board_info spi_info[] __initconst = {
204}; 258};
205 259
206static __init void tnetv107x_evm_board_init(void) 260static __init void tnetv107x_evm_board_init(void)
207{ 261{
208 davinci_cfg_reg_list(sdio1_pins); 262 davinci_cfg_reg_list(sdio1_pins);
209 davinci_cfg_reg_list(uart1_pins); 263 davinci_cfg_reg_list(uart1_pins);
264 davinci_cfg_reg_list(ssp_pins);
210 265
211 tnetv107x_devices_init(&evm_device_info); 266 tnetv107x_devices_init(&evm_device_info);
267
268 spi_register_board_info(spi_info, ARRAY_SIZE(spi_info));
212} 269}
213 270
214#ifdef CONFIG_SERIAL_8250_CONSOLE 271#ifdef CONFIG_SERIAL_8250_CONSOLE
diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c
index ec23ab473620..2ed2f822fc40 100644
--- a/arch/arm/mach-davinci/da830.c
+++ b/arch/arm/mach-davinci/da830.c
@@ -148,7 +148,7 @@ static struct clk scr2_ss_clk = {
148static struct clk dmax_clk = { 148static struct clk dmax_clk = {
149 .name = "dmax", 149 .name = "dmax",
150 .parent = &pll0_sysclk2, 150 .parent = &pll0_sysclk2,
151 .lpsc = DA8XX_LPSC0_DMAX, 151 .lpsc = DA8XX_LPSC0_PRUSS,
152 .flags = ALWAYS_ENABLED, 152 .flags = ALWAYS_ENABLED,
153}; 153};
154 154
@@ -397,8 +397,8 @@ static struct clk_lookup da830_clks[] = {
397 CLK(NULL, "uart0", &uart0_clk), 397 CLK(NULL, "uart0", &uart0_clk),
398 CLK(NULL, "uart1", &uart1_clk), 398 CLK(NULL, "uart1", &uart1_clk),
399 CLK(NULL, "uart2", &uart2_clk), 399 CLK(NULL, "uart2", &uart2_clk),
400 CLK("dm_spi.0", NULL, &spi0_clk), 400 CLK("spi_davinci.0", NULL, &spi0_clk),
401 CLK("dm_spi.1", NULL, &spi1_clk), 401 CLK("spi_davinci.1", NULL, &spi1_clk),
402 CLK(NULL, "ecap0", &ecap0_clk), 402 CLK(NULL, "ecap0", &ecap0_clk),
403 CLK(NULL, "ecap1", &ecap1_clk), 403 CLK(NULL, "ecap1", &ecap1_clk),
404 CLK(NULL, "ecap2", &ecap2_clk), 404 CLK(NULL, "ecap2", &ecap2_clk),
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index 78b5ae29ae40..68fe4c289d77 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -345,6 +345,34 @@ static struct clk aemif_clk = {
345 .flags = ALWAYS_ENABLED, 345 .flags = ALWAYS_ENABLED,
346}; 346};
347 347
348static struct clk usb11_clk = {
349 .name = "usb11",
350 .parent = &pll0_sysclk4,
351 .lpsc = DA8XX_LPSC1_USB11,
352 .gpsc = 1,
353};
354
355static struct clk usb20_clk = {
356 .name = "usb20",
357 .parent = &pll0_sysclk2,
358 .lpsc = DA8XX_LPSC1_USB20,
359 .gpsc = 1,
360};
361
362static struct clk spi0_clk = {
363 .name = "spi0",
364 .parent = &pll0_sysclk2,
365 .lpsc = DA8XX_LPSC0_SPI0,
366};
367
368static struct clk spi1_clk = {
369 .name = "spi1",
370 .parent = &pll0_sysclk2,
371 .lpsc = DA8XX_LPSC1_SPI1,
372 .gpsc = 1,
373 .flags = DA850_CLK_ASYNC3,
374};
375
348static struct clk_lookup da850_clks[] = { 376static struct clk_lookup da850_clks[] = {
349 CLK(NULL, "ref", &ref_clk), 377 CLK(NULL, "ref", &ref_clk),
350 CLK(NULL, "pll0", &pll0_clk), 378 CLK(NULL, "pll0", &pll0_clk),
@@ -387,6 +415,10 @@ static struct clk_lookup da850_clks[] = {
387 CLK("davinci_mmc.0", NULL, &mmcsd0_clk), 415 CLK("davinci_mmc.0", NULL, &mmcsd0_clk),
388 CLK("davinci_mmc.1", NULL, &mmcsd1_clk), 416 CLK("davinci_mmc.1", NULL, &mmcsd1_clk),
389 CLK(NULL, "aemif", &aemif_clk), 417 CLK(NULL, "aemif", &aemif_clk),
418 CLK(NULL, "usb11", &usb11_clk),
419 CLK(NULL, "usb20", &usb20_clk),
420 CLK("spi_davinci.0", NULL, &spi0_clk),
421 CLK("spi_davinci.1", NULL, &spi1_clk),
390 CLK(NULL, NULL, NULL), 422 CLK(NULL, NULL, NULL),
391}; 423};
392 424
@@ -543,30 +575,19 @@ static const struct mux_config da850_pins[] = {
543 MUX_CFG(DA850, EMA_WAIT_1, 6, 24, 15, 1, false) 575 MUX_CFG(DA850, EMA_WAIT_1, 6, 24, 15, 1, false)
544 MUX_CFG(DA850, NEMA_CS_2, 7, 0, 15, 1, false) 576 MUX_CFG(DA850, NEMA_CS_2, 7, 0, 15, 1, false)
545 /* GPIO function */ 577 /* GPIO function */
578 MUX_CFG(DA850, GPIO2_4, 6, 12, 15, 8, false)
546 MUX_CFG(DA850, GPIO2_6, 6, 4, 15, 8, false) 579 MUX_CFG(DA850, GPIO2_6, 6, 4, 15, 8, false)
547 MUX_CFG(DA850, GPIO2_8, 5, 28, 15, 8, false) 580 MUX_CFG(DA850, GPIO2_8, 5, 28, 15, 8, false)
548 MUX_CFG(DA850, GPIO2_15, 5, 0, 15, 8, false) 581 MUX_CFG(DA850, GPIO2_15, 5, 0, 15, 8, false)
582 MUX_CFG(DA850, GPIO3_12, 7, 12, 15, 8, false)
583 MUX_CFG(DA850, GPIO3_13, 7, 8, 15, 8, false)
549 MUX_CFG(DA850, GPIO4_0, 10, 28, 15, 8, false) 584 MUX_CFG(DA850, GPIO4_0, 10, 28, 15, 8, false)
550 MUX_CFG(DA850, GPIO4_1, 10, 24, 15, 8, false) 585 MUX_CFG(DA850, GPIO4_1, 10, 24, 15, 8, false)
586 MUX_CFG(DA850, GPIO6_13, 13, 8, 15, 8, false)
551 MUX_CFG(DA850, RTC_ALARM, 0, 28, 15, 2, false) 587 MUX_CFG(DA850, RTC_ALARM, 0, 28, 15, 2, false)
552#endif 588#endif
553}; 589};
554 590
555const short da850_uart0_pins[] __initdata = {
556 DA850_NUART0_CTS, DA850_NUART0_RTS, DA850_UART0_RXD, DA850_UART0_TXD,
557 -1
558};
559
560const short da850_uart1_pins[] __initdata = {
561 DA850_UART1_RXD, DA850_UART1_TXD,
562 -1
563};
564
565const short da850_uart2_pins[] __initdata = {
566 DA850_UART2_RXD, DA850_UART2_TXD,
567 -1
568};
569
570const short da850_i2c0_pins[] __initdata = { 591const short da850_i2c0_pins[] __initdata = {
571 DA850_I2C0_SDA, DA850_I2C0_SCL, 592 DA850_I2C0_SDA, DA850_I2C0_SCL,
572 -1 593 -1
@@ -577,24 +598,6 @@ const short da850_i2c1_pins[] __initdata = {
577 -1 598 -1
578}; 599};
579 600
580const short da850_cpgmac_pins[] __initdata = {
581 DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3,
582 DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER,
583 DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3,
584 DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK,
585 DA850_MDIO_D, DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN,
586 DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1, DA850_RMII_RXER,
587 DA850_RMII_MHZ_50_CLK,
588 -1
589};
590
591const short da850_mcasp_pins[] __initdata = {
592 DA850_AHCLKX, DA850_ACLKX, DA850_AFSX,
593 DA850_AHCLKR, DA850_ACLKR, DA850_AFSR, DA850_AMUTE,
594 DA850_AXR_11, DA850_AXR_12,
595 -1
596};
597
598const short da850_lcdcntl_pins[] __initdata = { 601const short da850_lcdcntl_pins[] __initdata = {
599 DA850_LCD_D_0, DA850_LCD_D_1, DA850_LCD_D_2, DA850_LCD_D_3, 602 DA850_LCD_D_0, DA850_LCD_D_1, DA850_LCD_D_2, DA850_LCD_D_3,
600 DA850_LCD_D_4, DA850_LCD_D_5, DA850_LCD_D_6, DA850_LCD_D_7, 603 DA850_LCD_D_4, DA850_LCD_D_5, DA850_LCD_D_6, DA850_LCD_D_7,
@@ -604,29 +607,6 @@ const short da850_lcdcntl_pins[] __initdata = {
604 -1 607 -1
605}; 608};
606 609
607const short da850_mmcsd0_pins[] __initdata = {
608 DA850_MMCSD0_DAT_0, DA850_MMCSD0_DAT_1, DA850_MMCSD0_DAT_2,
609 DA850_MMCSD0_DAT_3, DA850_MMCSD0_CLK, DA850_MMCSD0_CMD,
610 DA850_GPIO4_0, DA850_GPIO4_1,
611 -1
612};
613
614const short da850_emif25_pins[] __initdata = {
615 DA850_EMA_BA_1, DA850_EMA_CLK, DA850_EMA_WAIT_1, DA850_NEMA_CS_2,
616 DA850_NEMA_CS_3, DA850_NEMA_CS_4, DA850_NEMA_WE, DA850_NEMA_OE,
617 DA850_EMA_D_0, DA850_EMA_D_1, DA850_EMA_D_2, DA850_EMA_D_3,
618 DA850_EMA_D_4, DA850_EMA_D_5, DA850_EMA_D_6, DA850_EMA_D_7,
619 DA850_EMA_D_8, DA850_EMA_D_9, DA850_EMA_D_10, DA850_EMA_D_11,
620 DA850_EMA_D_12, DA850_EMA_D_13, DA850_EMA_D_14, DA850_EMA_D_15,
621 DA850_EMA_A_0, DA850_EMA_A_1, DA850_EMA_A_2, DA850_EMA_A_3,
622 DA850_EMA_A_4, DA850_EMA_A_5, DA850_EMA_A_6, DA850_EMA_A_7,
623 DA850_EMA_A_8, DA850_EMA_A_9, DA850_EMA_A_10, DA850_EMA_A_11,
624 DA850_EMA_A_12, DA850_EMA_A_13, DA850_EMA_A_14, DA850_EMA_A_15,
625 DA850_EMA_A_16, DA850_EMA_A_17, DA850_EMA_A_18, DA850_EMA_A_19,
626 DA850_EMA_A_20, DA850_EMA_A_21, DA850_EMA_A_22, DA850_EMA_A_23,
627 -1
628};
629
630/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */ 610/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
631static u8 da850_default_priorities[DA850_N_CP_INTC_IRQ] = { 611static u8 da850_default_priorities[DA850_N_CP_INTC_IRQ] = {
632 [IRQ_DA8XX_COMMTX] = 7, 612 [IRQ_DA8XX_COMMTX] = 7,
@@ -764,6 +744,13 @@ static struct davinci_id da850_ids[] = {
764 .cpu_id = DAVINCI_CPU_ID_DA850, 744 .cpu_id = DAVINCI_CPU_ID_DA850,
765 .name = "da850/omap-l138", 745 .name = "da850/omap-l138",
766 }, 746 },
747 {
748 .variant = 0x1,
749 .part_no = 0xb7d1,
750 .manufacturer = 0x017, /* 0x02f >> 1 */
751 .cpu_id = DAVINCI_CPU_ID_DA850,
752 .name = "da850/omap-l138/am18x",
753 },
767}; 754};
768 755
769static struct davinci_timer_instance da850_timer_instance[4] = { 756static struct davinci_timer_instance da850_timer_instance[4] = {
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index beda8a4133a0..625d4b66718b 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -38,12 +38,23 @@
38#define DA8XX_EMAC_MDIO_BASE 0x01e24000 38#define DA8XX_EMAC_MDIO_BASE 0x01e24000
39#define DA8XX_GPIO_BASE 0x01e26000 39#define DA8XX_GPIO_BASE 0x01e26000
40#define DA8XX_I2C1_BASE 0x01e28000 40#define DA8XX_I2C1_BASE 0x01e28000
41#define DA8XX_SPI0_BASE 0x01c41000
42#define DA8XX_SPI1_BASE 0x01f0e000
41 43
42#define DA8XX_EMAC_CTRL_REG_OFFSET 0x3000 44#define DA8XX_EMAC_CTRL_REG_OFFSET 0x3000
43#define DA8XX_EMAC_MOD_REG_OFFSET 0x2000 45#define DA8XX_EMAC_MOD_REG_OFFSET 0x2000
44#define DA8XX_EMAC_RAM_OFFSET 0x0000 46#define DA8XX_EMAC_RAM_OFFSET 0x0000
45#define DA8XX_EMAC_CTRL_RAM_SIZE SZ_8K 47#define DA8XX_EMAC_CTRL_RAM_SIZE SZ_8K
46 48
49#define DA8XX_DMA_SPI0_RX EDMA_CTLR_CHAN(0, 14)
50#define DA8XX_DMA_SPI0_TX EDMA_CTLR_CHAN(0, 15)
51#define DA8XX_DMA_MMCSD0_RX EDMA_CTLR_CHAN(0, 16)
52#define DA8XX_DMA_MMCSD0_TX EDMA_CTLR_CHAN(0, 17)
53#define DA8XX_DMA_SPI1_RX EDMA_CTLR_CHAN(0, 18)
54#define DA8XX_DMA_SPI1_TX EDMA_CTLR_CHAN(0, 19)
55#define DA850_DMA_MMCSD1_RX EDMA_CTLR_CHAN(1, 28)
56#define DA850_DMA_MMCSD1_TX EDMA_CTLR_CHAN(1, 29)
57
47void __iomem *da8xx_syscfg0_base; 58void __iomem *da8xx_syscfg0_base;
48void __iomem *da8xx_syscfg1_base; 59void __iomem *da8xx_syscfg1_base;
49 60
@@ -573,13 +584,13 @@ static struct resource da8xx_mmcsd0_resources[] = {
573 .flags = IORESOURCE_IRQ, 584 .flags = IORESOURCE_IRQ,
574 }, 585 },
575 { /* DMA RX */ 586 { /* DMA RX */
576 .start = EDMA_CTLR_CHAN(0, 16), 587 .start = DA8XX_DMA_MMCSD0_RX,
577 .end = EDMA_CTLR_CHAN(0, 16), 588 .end = DA8XX_DMA_MMCSD0_RX,
578 .flags = IORESOURCE_DMA, 589 .flags = IORESOURCE_DMA,
579 }, 590 },
580 { /* DMA TX */ 591 { /* DMA TX */
581 .start = EDMA_CTLR_CHAN(0, 17), 592 .start = DA8XX_DMA_MMCSD0_TX,
582 .end = EDMA_CTLR_CHAN(0, 17), 593 .end = DA8XX_DMA_MMCSD0_TX,
583 .flags = IORESOURCE_DMA, 594 .flags = IORESOURCE_DMA,
584 }, 595 },
585}; 596};
@@ -610,13 +621,13 @@ static struct resource da850_mmcsd1_resources[] = {
610 .flags = IORESOURCE_IRQ, 621 .flags = IORESOURCE_IRQ,
611 }, 622 },
612 { /* DMA RX */ 623 { /* DMA RX */
613 .start = EDMA_CTLR_CHAN(1, 28), 624 .start = DA850_DMA_MMCSD1_RX,
614 .end = EDMA_CTLR_CHAN(1, 28), 625 .end = DA850_DMA_MMCSD1_RX,
615 .flags = IORESOURCE_DMA, 626 .flags = IORESOURCE_DMA,
616 }, 627 },
617 { /* DMA TX */ 628 { /* DMA TX */
618 .start = EDMA_CTLR_CHAN(1, 29), 629 .start = DA850_DMA_MMCSD1_TX,
619 .end = EDMA_CTLR_CHAN(1, 29), 630 .end = DA850_DMA_MMCSD1_TX,
620 .flags = IORESOURCE_DMA, 631 .flags = IORESOURCE_DMA,
621 }, 632 },
622}; 633};
@@ -725,3 +736,101 @@ int __init da8xx_register_cpuidle(void)
725 736
726 return platform_device_register(&da8xx_cpuidle_device); 737 return platform_device_register(&da8xx_cpuidle_device);
727} 738}
739
740static struct resource da8xx_spi0_resources[] = {
741 [0] = {
742 .start = DA8XX_SPI0_BASE,
743 .end = DA8XX_SPI0_BASE + SZ_4K - 1,
744 .flags = IORESOURCE_MEM,
745 },
746 [1] = {
747 .start = IRQ_DA8XX_SPINT0,
748 .end = IRQ_DA8XX_SPINT0,
749 .flags = IORESOURCE_IRQ,
750 },
751 [2] = {
752 .start = DA8XX_DMA_SPI0_RX,
753 .end = DA8XX_DMA_SPI0_RX,
754 .flags = IORESOURCE_DMA,
755 },
756 [3] = {
757 .start = DA8XX_DMA_SPI0_TX,
758 .end = DA8XX_DMA_SPI0_TX,
759 .flags = IORESOURCE_DMA,
760 },
761};
762
763static struct resource da8xx_spi1_resources[] = {
764 [0] = {
765 .start = DA8XX_SPI1_BASE,
766 .end = DA8XX_SPI1_BASE + SZ_4K - 1,
767 .flags = IORESOURCE_MEM,
768 },
769 [1] = {
770 .start = IRQ_DA8XX_SPINT1,
771 .end = IRQ_DA8XX_SPINT1,
772 .flags = IORESOURCE_IRQ,
773 },
774 [2] = {
775 .start = DA8XX_DMA_SPI1_RX,
776 .end = DA8XX_DMA_SPI1_RX,
777 .flags = IORESOURCE_DMA,
778 },
779 [3] = {
780 .start = DA8XX_DMA_SPI1_TX,
781 .end = DA8XX_DMA_SPI1_TX,
782 .flags = IORESOURCE_DMA,
783 },
784};
785
786struct davinci_spi_platform_data da8xx_spi_pdata[] = {
787 [0] = {
788 .version = SPI_VERSION_2,
789 .intr_line = 1,
790 .dma_event_q = EVENTQ_0,
791 },
792 [1] = {
793 .version = SPI_VERSION_2,
794 .intr_line = 1,
795 .dma_event_q = EVENTQ_0,
796 },
797};
798
799static struct platform_device da8xx_spi_device[] = {
800 [0] = {
801 .name = "spi_davinci",
802 .id = 0,
803 .num_resources = ARRAY_SIZE(da8xx_spi0_resources),
804 .resource = da8xx_spi0_resources,
805 .dev = {
806 .platform_data = &da8xx_spi_pdata[0],
807 },
808 },
809 [1] = {
810 .name = "spi_davinci",
811 .id = 1,
812 .num_resources = ARRAY_SIZE(da8xx_spi1_resources),
813 .resource = da8xx_spi1_resources,
814 .dev = {
815 .platform_data = &da8xx_spi_pdata[1],
816 },
817 },
818};
819
820int __init da8xx_register_spi(int instance, struct spi_board_info *info,
821 unsigned len)
822{
823 int ret;
824
825 if (instance < 0 || instance > 1)
826 return -EINVAL;
827
828 ret = spi_register_board_info(info, len);
829 if (ret)
830 pr_warning("%s: failed to register board info for spi %d :"
831 " %d\n", __func__, instance, ret);
832
833 da8xx_spi_pdata[instance].num_chipselect = len;
834
835 return platform_device_register(&da8xx_spi_device[instance]);
836}
diff --git a/arch/arm/mach-davinci/devices-tnetv107x.c b/arch/arm/mach-davinci/devices-tnetv107x.c
index 85503debda51..6162cae7f868 100644
--- a/arch/arm/mach-davinci/devices-tnetv107x.c
+++ b/arch/arm/mach-davinci/devices-tnetv107x.c
@@ -35,6 +35,7 @@
35#define TNETV107X_SDIO0_BASE 0x08088700 35#define TNETV107X_SDIO0_BASE 0x08088700
36#define TNETV107X_SDIO1_BASE 0x08088800 36#define TNETV107X_SDIO1_BASE 0x08088800
37#define TNETV107X_KEYPAD_BASE 0x08088a00 37#define TNETV107X_KEYPAD_BASE 0x08088a00
38#define TNETV107X_SSP_BASE 0x08088c00
38#define TNETV107X_ASYNC_EMIF_CNTRL_BASE 0x08200000 39#define TNETV107X_ASYNC_EMIF_CNTRL_BASE 0x08200000
39#define TNETV107X_ASYNC_EMIF_DATA_CE0_BASE 0x30000000 40#define TNETV107X_ASYNC_EMIF_DATA_CE0_BASE 0x30000000
40#define TNETV107X_ASYNC_EMIF_DATA_CE1_BASE 0x40000000 41#define TNETV107X_ASYNC_EMIF_DATA_CE1_BASE 0x40000000
@@ -342,6 +343,25 @@ static struct platform_device tsc_device = {
342 .resource = tsc_resources, 343 .resource = tsc_resources,
343}; 344};
344 345
346static struct resource ssp_resources[] = {
347 {
348 .start = TNETV107X_SSP_BASE,
349 .end = TNETV107X_SSP_BASE + 0x1ff,
350 .flags = IORESOURCE_MEM,
351 },
352 {
353 .start = IRQ_TNETV107X_SSP,
354 .flags = IORESOURCE_IRQ,
355 },
356};
357
358static struct platform_device ssp_device = {
359 .name = "ti-ssp",
360 .id = -1,
361 .num_resources = ARRAY_SIZE(ssp_resources),
362 .resource = ssp_resources,
363};
364
345void __init tnetv107x_devices_init(struct tnetv107x_device_info *info) 365void __init tnetv107x_devices_init(struct tnetv107x_device_info *info)
346{ 366{
347 int i, error; 367 int i, error;
@@ -380,4 +400,9 @@ void __init tnetv107x_devices_init(struct tnetv107x_device_info *info)
380 keypad_device.dev.platform_data = info->keypad_config; 400 keypad_device.dev.platform_data = info->keypad_config;
381 platform_device_register(&keypad_device); 401 platform_device_register(&keypad_device);
382 } 402 }
403
404 if (info->ssp_config) {
405 ssp_device.dev.platform_data = info->ssp_config;
406 platform_device_register(&ssp_device);
407 }
383} 408}
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index a5f8a80c1f28..76364d1345df 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -403,16 +403,13 @@ static struct resource dm355_spi0_resources[] = {
403 .start = 16, 403 .start = 16,
404 .flags = IORESOURCE_DMA, 404 .flags = IORESOURCE_DMA,
405 }, 405 },
406 {
407 .start = EVENTQ_1,
408 .flags = IORESOURCE_DMA,
409 },
410}; 406};
411 407
412static struct davinci_spi_platform_data dm355_spi0_pdata = { 408static struct davinci_spi_platform_data dm355_spi0_pdata = {
413 .version = SPI_VERSION_1, 409 .version = SPI_VERSION_1,
414 .num_chipselect = 2, 410 .num_chipselect = 2,
415 .cshold_bug = true, 411 .cshold_bug = true,
412 .dma_event_q = EVENTQ_1,
416}; 413};
417static struct platform_device dm355_spi0_device = { 414static struct platform_device dm355_spi0_device = {
418 .name = "spi_davinci", 415 .name = "spi_davinci",
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index 02d2cc380df7..4604e72d7d99 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -625,6 +625,7 @@ static u64 dm365_spi0_dma_mask = DMA_BIT_MASK(32);
625static struct davinci_spi_platform_data dm365_spi0_pdata = { 625static struct davinci_spi_platform_data dm365_spi0_pdata = {
626 .version = SPI_VERSION_1, 626 .version = SPI_VERSION_1,
627 .num_chipselect = 2, 627 .num_chipselect = 2,
628 .dma_event_q = EVENTQ_3,
628}; 629};
629 630
630static struct resource dm365_spi0_resources[] = { 631static struct resource dm365_spi0_resources[] = {
@@ -645,10 +646,6 @@ static struct resource dm365_spi0_resources[] = {
645 .start = 16, 646 .start = 16,
646 .flags = IORESOURCE_DMA, 647 .flags = IORESOURCE_DMA,
647 }, 648 },
648 {
649 .start = EVENTQ_3,
650 .flags = IORESOURCE_DMA,
651 },
652}; 649};
653 650
654static struct platform_device dm365_spi0_device = { 651static struct platform_device dm365_spi0_device = {
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
index e7f952066527..e4fc1af8500e 100644
--- a/arch/arm/mach-davinci/include/mach/da8xx.h
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -15,6 +15,7 @@
15 15
16#include <linux/platform_device.h> 16#include <linux/platform_device.h>
17#include <linux/davinci_emac.h> 17#include <linux/davinci_emac.h>
18#include <linux/spi/spi.h>
18 19
19#include <mach/serial.h> 20#include <mach/serial.h>
20#include <mach/edma.h> 21#include <mach/edma.h>
@@ -23,6 +24,7 @@
23#include <mach/mmc.h> 24#include <mach/mmc.h>
24#include <mach/usb.h> 25#include <mach/usb.h>
25#include <mach/pm.h> 26#include <mach/pm.h>
27#include <mach/spi.h>
26 28
27extern void __iomem *da8xx_syscfg0_base; 29extern void __iomem *da8xx_syscfg0_base;
28extern void __iomem *da8xx_syscfg1_base; 30extern void __iomem *da8xx_syscfg1_base;
@@ -77,6 +79,7 @@ void __init da850_init(void);
77int da830_register_edma(struct edma_rsv_info *rsv); 79int da830_register_edma(struct edma_rsv_info *rsv);
78int da850_register_edma(struct edma_rsv_info *rsv[2]); 80int da850_register_edma(struct edma_rsv_info *rsv[2]);
79int da8xx_register_i2c(int instance, struct davinci_i2c_platform_data *pdata); 81int da8xx_register_i2c(int instance, struct davinci_i2c_platform_data *pdata);
82int da8xx_register_spi(int instance, struct spi_board_info *info, unsigned len);
80int da8xx_register_watchdog(void); 83int da8xx_register_watchdog(void);
81int da8xx_register_usb20(unsigned mA, unsigned potpgt); 84int da8xx_register_usb20(unsigned mA, unsigned potpgt);
82int da8xx_register_usb11(struct da8xx_ohci_root_hub *pdata); 85int da8xx_register_usb11(struct da8xx_ohci_root_hub *pdata);
@@ -95,6 +98,7 @@ extern struct platform_device da8xx_serial_device;
95extern struct emac_platform_data da8xx_emac_pdata; 98extern struct emac_platform_data da8xx_emac_pdata;
96extern struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata; 99extern struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata;
97extern struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata; 100extern struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata;
101extern struct davinci_spi_platform_data da8xx_spi_pdata[];
98 102
99extern struct platform_device da8xx_wdt_device; 103extern struct platform_device da8xx_wdt_device;
100 104
@@ -123,15 +127,8 @@ extern const short da830_ecap2_pins[];
123extern const short da830_eqep0_pins[]; 127extern const short da830_eqep0_pins[];
124extern const short da830_eqep1_pins[]; 128extern const short da830_eqep1_pins[];
125 129
126extern const short da850_uart0_pins[];
127extern const short da850_uart1_pins[];
128extern const short da850_uart2_pins[];
129extern const short da850_i2c0_pins[]; 130extern const short da850_i2c0_pins[];
130extern const short da850_i2c1_pins[]; 131extern const short da850_i2c1_pins[];
131extern const short da850_cpgmac_pins[];
132extern const short da850_mcasp_pins[];
133extern const short da850_lcdcntl_pins[]; 132extern const short da850_lcdcntl_pins[];
134extern const short da850_mmcsd0_pins[];
135extern const short da850_emif25_pins[];
136 133
137#endif /* __ASM_ARCH_DAVINCI_DA8XX_H */ 134#endif /* __ASM_ARCH_DAVINCI_DA8XX_H */
diff --git a/arch/arm/mach-davinci/include/mach/edma.h b/arch/arm/mach-davinci/include/mach/edma.h
index dc10ef6cf572..20c77f29bf0f 100644
--- a/arch/arm/mach-davinci/include/mach/edma.h
+++ b/arch/arm/mach-davinci/include/mach/edma.h
@@ -151,42 +151,6 @@ struct edmacc_param {
151#define DA830_DMACH2EVENT_MAP1 0x00000000u 151#define DA830_DMACH2EVENT_MAP1 0x00000000u
152#define DA830_EDMA_ARM_OWN 0x30FFCCFFu 152#define DA830_EDMA_ARM_OWN 0x30FFCCFFu
153 153
154/* DA830 specific EDMA3 Events Information */
155enum DA830_edma_ch {
156 DA830_DMACH_MCASP0_RX,
157 DA830_DMACH_MCASP0_TX,
158 DA830_DMACH_MCASP1_RX,
159 DA830_DMACH_MCASP1_TX,
160 DA830_DMACH_MCASP2_RX,
161 DA830_DMACH_MCASP2_TX,
162 DA830_DMACH_GPIO_BNK0INT,
163 DA830_DMACH_GPIO_BNK1INT,
164 DA830_DMACH_UART0_RX,
165 DA830_DMACH_UART0_TX,
166 DA830_DMACH_TMR64P0_EVTOUT12,
167 DA830_DMACH_TMR64P0_EVTOUT34,
168 DA830_DMACH_UART1_RX,
169 DA830_DMACH_UART1_TX,
170 DA830_DMACH_SPI0_RX,
171 DA830_DMACH_SPI0_TX,
172 DA830_DMACH_MMCSD_RX,
173 DA830_DMACH_MMCSD_TX,
174 DA830_DMACH_SPI1_RX,
175 DA830_DMACH_SPI1_TX,
176 DA830_DMACH_DMAX_EVTOUT6,
177 DA830_DMACH_DMAX_EVTOUT7,
178 DA830_DMACH_GPIO_BNK2INT,
179 DA830_DMACH_GPIO_BNK3INT,
180 DA830_DMACH_I2C0_RX,
181 DA830_DMACH_I2C0_TX,
182 DA830_DMACH_I2C1_RX,
183 DA830_DMACH_I2C1_TX,
184 DA830_DMACH_GPIO_BNK4INT,
185 DA830_DMACH_GPIO_BNK5INT,
186 DA830_DMACH_UART2_RX,
187 DA830_DMACH_UART2_TX
188};
189
190/*ch_status paramater of callback function possible values*/ 154/*ch_status paramater of callback function possible values*/
191#define DMA_COMPLETE 1 155#define DMA_COMPLETE 1
192#define DMA_CC_ERROR 2 156#define DMA_CC_ERROR 2
diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h
index de11aac76a80..5d4e0fed828a 100644
--- a/arch/arm/mach-davinci/include/mach/mux.h
+++ b/arch/arm/mach-davinci/include/mach/mux.h
@@ -908,11 +908,15 @@ enum davinci_da850_index {
908 DA850_NEMA_CS_2, 908 DA850_NEMA_CS_2,
909 909
910 /* GPIO function */ 910 /* GPIO function */
911 DA850_GPIO2_4,
911 DA850_GPIO2_6, 912 DA850_GPIO2_6,
912 DA850_GPIO2_8, 913 DA850_GPIO2_8,
913 DA850_GPIO2_15, 914 DA850_GPIO2_15,
915 DA850_GPIO3_12,
916 DA850_GPIO3_13,
914 DA850_GPIO4_0, 917 DA850_GPIO4_0,
915 DA850_GPIO4_1, 918 DA850_GPIO4_1,
919 DA850_GPIO6_13,
916 DA850_RTC_ALARM, 920 DA850_RTC_ALARM,
917}; 921};
918 922
diff --git a/arch/arm/mach-davinci/include/mach/psc.h b/arch/arm/mach-davinci/include/mach/psc.h
index 62b0858f68ca..a47e6f29206e 100644
--- a/arch/arm/mach-davinci/include/mach/psc.h
+++ b/arch/arm/mach-davinci/include/mach/psc.h
@@ -150,7 +150,7 @@
150#define DA8XX_LPSC0_SCR0_SS 10 150#define DA8XX_LPSC0_SCR0_SS 10
151#define DA8XX_LPSC0_SCR1_SS 11 151#define DA8XX_LPSC0_SCR1_SS 11
152#define DA8XX_LPSC0_SCR2_SS 12 152#define DA8XX_LPSC0_SCR2_SS 12
153#define DA8XX_LPSC0_DMAX 13 153#define DA8XX_LPSC0_PRUSS 13
154#define DA8XX_LPSC0_ARM 14 154#define DA8XX_LPSC0_ARM 14
155#define DA8XX_LPSC0_GEM 15 155#define DA8XX_LPSC0_GEM 15
156 156
diff --git a/arch/arm/mach-davinci/include/mach/spi.h b/arch/arm/mach-davinci/include/mach/spi.h
index 38f4da5ca135..7af305b37868 100644
--- a/arch/arm/mach-davinci/include/mach/spi.h
+++ b/arch/arm/mach-davinci/include/mach/spi.h
@@ -19,6 +19,8 @@
19#ifndef __ARCH_ARM_DAVINCI_SPI_H 19#ifndef __ARCH_ARM_DAVINCI_SPI_H
20#define __ARCH_ARM_DAVINCI_SPI_H 20#define __ARCH_ARM_DAVINCI_SPI_H
21 21
22#include <mach/edma.h>
23
22#define SPI_INTERN_CS 0xFF 24#define SPI_INTERN_CS 0xFF
23 25
24enum { 26enum {
@@ -39,13 +41,16 @@ enum {
39 * to populate if all chip-selects are internal. 41 * to populate if all chip-selects are internal.
40 * @cshold_bug: set this to true if the SPI controller on your chip requires 42 * @cshold_bug: set this to true if the SPI controller on your chip requires
41 * a write to CSHOLD bit in between transfers (like in DM355). 43 * a write to CSHOLD bit in between transfers (like in DM355).
44 * @dma_event_q: DMA event queue to use if SPI_IO_TYPE_DMA is used for any
45 * device on the bus.
42 */ 46 */
43struct davinci_spi_platform_data { 47struct davinci_spi_platform_data {
44 u8 version; 48 u8 version;
45 u8 num_chipselect; 49 u8 num_chipselect;
46 u8 intr_line; 50 u8 intr_line;
47 u8 *chip_sel; 51 u8 *chip_sel;
48 bool cshold_bug; 52 bool cshold_bug;
53 enum dma_event_q dma_event_q;
49}; 54};
50 55
51/** 56/**
diff --git a/arch/arm/mach-davinci/include/mach/tnetv107x.h b/arch/arm/mach-davinci/include/mach/tnetv107x.h
index 5a681d880dcb..89c1fdc63c0b 100644
--- a/arch/arm/mach-davinci/include/mach/tnetv107x.h
+++ b/arch/arm/mach-davinci/include/mach/tnetv107x.h
@@ -34,6 +34,7 @@
34 34
35#include <linux/serial_8250.h> 35#include <linux/serial_8250.h>
36#include <linux/input/matrix_keypad.h> 36#include <linux/input/matrix_keypad.h>
37#include <linux/mfd/ti_ssp.h>
37 38
38#include <mach/mmc.h> 39#include <mach/mmc.h>
39#include <mach/nand.h> 40#include <mach/nand.h>
@@ -44,6 +45,7 @@ struct tnetv107x_device_info {
44 struct davinci_mmc_config *mmc_config[2]; /* 2 controllers */ 45 struct davinci_mmc_config *mmc_config[2]; /* 2 controllers */
45 struct davinci_nand_pdata *nand_config[4]; /* 4 chipsels */ 46 struct davinci_nand_pdata *nand_config[4]; /* 4 chipsels */
46 struct matrix_keypad_platform_data *keypad_config; 47 struct matrix_keypad_platform_data *keypad_config;
48 struct ti_ssp_data *ssp_config;
47}; 49};
48 50
49extern struct platform_device tnetv107x_wdt_device; 51extern struct platform_device tnetv107x_wdt_device;
diff --git a/arch/arm/mach-davinci/tnetv107x.c b/arch/arm/mach-davinci/tnetv107x.c
index 6fcdecec8d8c..1b28fdd892a6 100644
--- a/arch/arm/mach-davinci/tnetv107x.c
+++ b/arch/arm/mach-davinci/tnetv107x.c
@@ -278,7 +278,7 @@ static struct clk_lookup clks[] = {
278 CLK(NULL, "timer1", &clk_timer1), 278 CLK(NULL, "timer1", &clk_timer1),
279 CLK("tnetv107x_wdt.0", NULL, &clk_wdt_arm), 279 CLK("tnetv107x_wdt.0", NULL, &clk_wdt_arm),
280 CLK(NULL, "clk_wdt_dsp", &clk_wdt_dsp), 280 CLK(NULL, "clk_wdt_dsp", &clk_wdt_dsp),
281 CLK("ti-ssp.0", NULL, &clk_ssp), 281 CLK("ti-ssp", NULL, &clk_ssp),
282 CLK(NULL, "clk_tdm0", &clk_tdm0), 282 CLK(NULL, "clk_tdm0", &clk_tdm0),
283 CLK(NULL, "clk_vlynq", &clk_vlynq), 283 CLK(NULL, "clk_vlynq", &clk_vlynq),
284 CLK(NULL, "clk_mcdma", &clk_mcdma), 284 CLK(NULL, "clk_mcdma", &clk_mcdma),
diff --git a/arch/arm/mach-dove/cm-a510.c b/arch/arm/mach-dove/cm-a510.c
index 96e0e94e5fa9..03e11f9dca97 100644
--- a/arch/arm/mach-dove/cm-a510.c
+++ b/arch/arm/mach-dove/cm-a510.c
@@ -90,6 +90,7 @@ MACHINE_START(CM_A510, "Compulab CM-A510 Board")
90 .boot_params = 0x00000100, 90 .boot_params = 0x00000100,
91 .init_machine = cm_a510_init, 91 .init_machine = cm_a510_init,
92 .map_io = dove_map_io, 92 .map_io = dove_map_io,
93 .init_early = dove_init_early,
93 .init_irq = dove_init_irq, 94 .init_irq = dove_init_irq,
94 .timer = &dove_timer, 95 .timer = &dove_timer,
95MACHINE_END 96MACHINE_END
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index fe627aba6da7..e06a88f1f81d 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -532,6 +532,11 @@ void __init dove_i2c_init(void)
532/***************************************************************************** 532/*****************************************************************************
533 * Time handling 533 * Time handling
534 ****************************************************************************/ 534 ****************************************************************************/
535void __init dove_init_early(void)
536{
537 orion_time_set_base(TIMER_VIRT_BASE);
538}
539
535static int get_tclk(void) 540static int get_tclk(void)
536{ 541{
537 /* use DOVE_RESET_SAMPLE_HI/LO to detect tclk */ 542 /* use DOVE_RESET_SAMPLE_HI/LO to detect tclk */
@@ -540,7 +545,8 @@ static int get_tclk(void)
540 545
541static void dove_timer_init(void) 546static void dove_timer_init(void)
542{ 547{
543 orion_time_init(IRQ_DOVE_BRIDGE, get_tclk()); 548 orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
549 IRQ_DOVE_BRIDGE, get_tclk());
544} 550}
545 551
546struct sys_timer dove_timer = { 552struct sys_timer dove_timer = {
diff --git a/arch/arm/mach-dove/common.h b/arch/arm/mach-dove/common.h
index a51517c3fe76..6a2046e44706 100644
--- a/arch/arm/mach-dove/common.h
+++ b/arch/arm/mach-dove/common.h
@@ -22,6 +22,7 @@ extern struct mbus_dram_target_info dove_mbus_dram_info;
22 */ 22 */
23void dove_map_io(void); 23void dove_map_io(void);
24void dove_init(void); 24void dove_init(void);
25void dove_init_early(void);
25void dove_init_irq(void); 26void dove_init_irq(void);
26void dove_setup_cpu_mbus(void); 27void dove_setup_cpu_mbus(void);
27void dove_ge00_init(struct mv643xx_eth_platform_data *eth_data); 28void dove_ge00_init(struct mv643xx_eth_platform_data *eth_data);
diff --git a/arch/arm/mach-dove/dove-db-setup.c b/arch/arm/mach-dove/dove-db-setup.c
index 95925aa76dd9..2ac34ecfa745 100644
--- a/arch/arm/mach-dove/dove-db-setup.c
+++ b/arch/arm/mach-dove/dove-db-setup.c
@@ -97,6 +97,7 @@ MACHINE_START(DOVE_DB, "Marvell DB-MV88AP510-BP Development Board")
97 .boot_params = 0x00000100, 97 .boot_params = 0x00000100,
98 .init_machine = dove_db_init, 98 .init_machine = dove_db_init,
99 .map_io = dove_map_io, 99 .map_io = dove_map_io,
100 .init_early = dove_init_early,
100 .init_irq = dove_init_irq, 101 .init_irq = dove_init_irq,
101 .timer = &dove_timer, 102 .timer = &dove_timer,
102MACHINE_END 103MACHINE_END
diff --git a/arch/arm/mach-dove/include/mach/bridge-regs.h b/arch/arm/mach-dove/include/mach/bridge-regs.h
index 214a4c31f069..226949dc4ac0 100644
--- a/arch/arm/mach-dove/include/mach/bridge-regs.h
+++ b/arch/arm/mach-dove/include/mach/bridge-regs.h
@@ -26,10 +26,6 @@
26#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c) 26#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c)
27#define SOFT_RESET 0x00000001 27#define SOFT_RESET 0x00000001
28 28
29#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110)
30#define BRIDGE_MASK (BRIDGE_VIRT_BASE | 0x0114)
31#define BRIDGE_INT_TIMER0 0x0002
32#define BRIDGE_INT_TIMER1 0x0004
33#define BRIDGE_INT_TIMER1_CLR (~0x0004) 29#define BRIDGE_INT_TIMER1_CLR (~0x0004)
34 30
35#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200) 31#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200)
diff --git a/arch/arm/mach-dove/include/mach/dove.h b/arch/arm/mach-dove/include/mach/dove.h
index 27b414578f2e..e5fcdd3f5bf5 100644
--- a/arch/arm/mach-dove/include/mach/dove.h
+++ b/arch/arm/mach-dove/include/mach/dove.h
@@ -130,7 +130,8 @@
130#define DOVE_PMU_MPP_GENERAL_CTRL (DOVE_MPP_VIRT_BASE + 0x10) 130#define DOVE_PMU_MPP_GENERAL_CTRL (DOVE_MPP_VIRT_BASE + 0x10)
131#define DOVE_RESET_SAMPLE_LO (DOVE_MPP_VIRT_BASE | 0x014) 131#define DOVE_RESET_SAMPLE_LO (DOVE_MPP_VIRT_BASE | 0x014)
132#define DOVE_RESET_SAMPLE_HI (DOVE_MPP_VIRT_BASE | 0x018) 132#define DOVE_RESET_SAMPLE_HI (DOVE_MPP_VIRT_BASE | 0x018)
133#define DOVE_GPIO_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0400) 133#define DOVE_GPIO_LO_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0400)
134#define DOVE_GPIO_HI_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0420)
134#define DOVE_GPIO2_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe8400) 135#define DOVE_GPIO2_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe8400)
135#define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe803c) 136#define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe803c)
136#define DOVE_AU1_SPDIFO_GPIO_EN (1 << 1) 137#define DOVE_AU1_SPDIFO_GPIO_EN (1 << 1)
diff --git a/arch/arm/mach-dove/include/mach/gpio.h b/arch/arm/mach-dove/include/mach/gpio.h
index 340bb7af529d..e7e5101e35a5 100644
--- a/arch/arm/mach-dove/include/mach/gpio.h
+++ b/arch/arm/mach-dove/include/mach/gpio.h
@@ -6,46 +6,4 @@
6 * warranty of any kind, whether express or implied. 6 * warranty of any kind, whether express or implied.
7 */ 7 */
8 8
9#ifndef __ASM_ARCH_GPIO_H
10#define __ASM_ARCH_GPIO_H
11
12#include <asm/errno.h>
13#include <mach/irqs.h>
14#include <plat/gpio.h> 9#include <plat/gpio.h>
15#include <asm-generic/gpio.h> /* cansleep wrappers */
16
17#define GPIO_MAX 72
18
19#define GPIO_BASE_LO (DOVE_GPIO_VIRT_BASE + 0x00)
20#define GPIO_BASE_HI (DOVE_GPIO_VIRT_BASE + 0x20)
21
22#define GPIO_BASE(pin) ((pin < 32) ? GPIO_BASE_LO : \
23 ((pin < 64) ? GPIO_BASE_HI : \
24 DOVE_GPIO2_VIRT_BASE))
25
26#define GPIO_OUT(pin) (GPIO_BASE(pin) + 0x00)
27#define GPIO_IO_CONF(pin) (GPIO_BASE(pin) + 0x04)
28#define GPIO_BLINK_EN(pin) (GPIO_BASE(pin) + 0x08)
29#define GPIO_IN_POL(pin) (GPIO_BASE(pin) + 0x0c)
30#define GPIO_DATA_IN(pin) (GPIO_BASE(pin) + 0x10)
31#define GPIO_EDGE_CAUSE(pin) (GPIO_BASE(pin) + 0x14)
32#define GPIO_EDGE_MASK(pin) (GPIO_BASE(pin) + 0x18)
33#define GPIO_LEVEL_MASK(pin) (GPIO_BASE(pin) + 0x1c)
34
35static inline int gpio_to_irq(int pin)
36{
37 if (pin < NR_GPIO_IRQS)
38 return pin + IRQ_DOVE_GPIO_START;
39
40 return -EINVAL;
41}
42
43static inline int irq_to_gpio(int irq)
44{
45 if (IRQ_DOVE_GPIO_START < irq && irq < NR_IRQS)
46 return irq - IRQ_DOVE_GPIO_START;
47
48 return -EINVAL;
49}
50
51#endif
diff --git a/arch/arm/mach-dove/include/mach/irqs.h b/arch/arm/mach-dove/include/mach/irqs.h
index 46681466f92b..03d401d20453 100644
--- a/arch/arm/mach-dove/include/mach/irqs.h
+++ b/arch/arm/mach-dove/include/mach/irqs.h
@@ -92,10 +92,5 @@
92 92
93#define NR_IRQS (IRQ_DOVE_PMU_START + NR_PMU_IRQS) 93#define NR_IRQS (IRQ_DOVE_PMU_START + NR_PMU_IRQS)
94 94
95/* Required for compatability with PXA AC97 driver. */ 95
96#define IRQ_AC97 IRQ_DOVE_AC97
97/* Required for compatability with PXA DMA driver. */
98#define IRQ_DMA IRQ_DOVE_PDMA
99/* Required for compatability with PXA NAND driver */
100#define IRQ_NAND IRQ_DOVE_NAND
101#endif 96#endif
diff --git a/arch/arm/mach-dove/irq.c b/arch/arm/mach-dove/irq.c
index 9317f0558b57..101707fa2e2c 100644
--- a/arch/arm/mach-dove/irq.c
+++ b/arch/arm/mach-dove/irq.c
@@ -99,11 +99,21 @@ void __init dove_init_irq(void)
99 orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF)); 99 orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF));
100 100
101 /* 101 /*
102 * Mask and clear GPIO IRQ interrupts. 102 * Initialize gpiolib for GPIOs 0-71.
103 */ 103 */
104 writel(0, GPIO_LEVEL_MASK(0)); 104 orion_gpio_init(0, 32, DOVE_GPIO_LO_VIRT_BASE, 0,
105 writel(0, GPIO_EDGE_MASK(0)); 105 IRQ_DOVE_GPIO_START);
106 writel(0, GPIO_EDGE_CAUSE(0)); 106 set_irq_chained_handler(IRQ_DOVE_GPIO_0_7, gpio_irq_handler);
107 set_irq_chained_handler(IRQ_DOVE_GPIO_8_15, gpio_irq_handler);
108 set_irq_chained_handler(IRQ_DOVE_GPIO_16_23, gpio_irq_handler);
109 set_irq_chained_handler(IRQ_DOVE_GPIO_24_31, gpio_irq_handler);
110
111 orion_gpio_init(32, 32, DOVE_GPIO_HI_VIRT_BASE, 0,
112 IRQ_DOVE_GPIO_START + 32);
113 set_irq_chained_handler(IRQ_DOVE_HIGH_GPIO, gpio_irq_handler);
114
115 orion_gpio_init(64, 8, DOVE_GPIO2_VIRT_BASE, 0,
116 IRQ_DOVE_GPIO_START + 64);
107 117
108 /* 118 /*
109 * Mask and clear PMU interrupts 119 * Mask and clear PMU interrupts
@@ -111,18 +121,6 @@ void __init dove_init_irq(void)
111 writel(0, PMU_INTERRUPT_MASK); 121 writel(0, PMU_INTERRUPT_MASK);
112 writel(0, PMU_INTERRUPT_CAUSE); 122 writel(0, PMU_INTERRUPT_CAUSE);
113 123
114 for (i = IRQ_DOVE_GPIO_START; i < IRQ_DOVE_PMU_START; i++) {
115 set_irq_chip(i, &orion_gpio_irq_chip);
116 set_irq_handler(i, handle_level_irq);
117 irq_desc[i].status |= IRQ_LEVEL;
118 set_irq_flags(i, IRQF_VALID);
119 }
120 set_irq_chained_handler(IRQ_DOVE_GPIO_0_7, gpio_irq_handler);
121 set_irq_chained_handler(IRQ_DOVE_GPIO_8_15, gpio_irq_handler);
122 set_irq_chained_handler(IRQ_DOVE_GPIO_16_23, gpio_irq_handler);
123 set_irq_chained_handler(IRQ_DOVE_GPIO_24_31, gpio_irq_handler);
124 set_irq_chained_handler(IRQ_DOVE_HIGH_GPIO, gpio_irq_handler);
125
126 for (i = IRQ_DOVE_PMU_START; i < NR_IRQS; i++) { 124 for (i = IRQ_DOVE_PMU_START; i < NR_IRQS; i++) {
127 set_irq_chip(i, &pmu_irq_chip); 125 set_irq_chip(i, &pmu_irq_chip);
128 set_irq_handler(i, handle_level_irq); 126 set_irq_handler(i, handle_level_irq);
diff --git a/arch/arm/mach-exynos4/Kconfig b/arch/arm/mach-exynos4/Kconfig
new file mode 100644
index 000000000000..a021b5240bba
--- /dev/null
+++ b/arch/arm/mach-exynos4/Kconfig
@@ -0,0 +1,195 @@
1# arch/arm/mach-exynos4/Kconfig
2#
3# Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4# http://www.samsung.com/
5#
6# Licensed under GPLv2
7
8# Configuration options for the EXYNOS4
9
10if ARCH_EXYNOS4
11
12config CPU_EXYNOS4210
13 bool
14 select S3C_PL330_DMA
15 help
16 Enable EXYNOS4210 CPU support
17
18config EXYNOS4_MCT
19 bool "Kernel timer support by MCT"
20 help
21 Use MCT (Multi Core Timer) as kernel timers
22
23config EXYNOS4_DEV_PD
24 bool
25 help
26 Compile in platform device definitions for Power Domain
27
28config EXYNOS4_DEV_SYSMMU
29 bool
30 help
31 Common setup code for SYSTEM MMU in EXYNOS4
32
33config EXYNOS4_SETUP_I2C1
34 bool
35 help
36 Common setup code for i2c bus 1.
37
38config EXYNOS4_SETUP_I2C2
39 bool
40 help
41 Common setup code for i2c bus 2.
42
43config EXYNOS4_SETUP_I2C3
44 bool
45 help
46 Common setup code for i2c bus 3.
47
48config EXYNOS4_SETUP_I2C4
49 bool
50 help
51 Common setup code for i2c bus 4.
52
53config EXYNOS4_SETUP_I2C5
54 bool
55 help
56 Common setup code for i2c bus 5.
57
58config EXYNOS4_SETUP_I2C6
59 bool
60 help
61 Common setup code for i2c bus 6.
62
63config EXYNOS4_SETUP_I2C7
64 bool
65 help
66 Common setup code for i2c bus 7.
67
68config EXYNOS4_SETUP_KEYPAD
69 bool
70 help
71 Common setup code for keypad.
72
73config EXYNOS4_SETUP_SDHCI
74 bool
75 select EXYNOS4_SETUP_SDHCI_GPIO
76 help
77 Internal helper functions for EXYNOS4 based SDHCI systems.
78
79config EXYNOS4_SETUP_SDHCI_GPIO
80 bool
81 help
82 Common setup code for SDHCI gpio.
83
84config EXYNOS4_SETUP_FIMC
85 bool
86 help
87 Common setup code for the camera interfaces.
88
89# machine support
90
91menu "EXYNOS4 Machines"
92
93config MACH_SMDKC210
94 bool "SMDKC210"
95 select CPU_EXYNOS4210
96 select S3C_DEV_RTC
97 select S3C_DEV_WDT
98 select S3C_DEV_I2C1
99 select S3C_DEV_HSMMC
100 select S3C_DEV_HSMMC1
101 select S3C_DEV_HSMMC2
102 select S3C_DEV_HSMMC3
103 select EXYNOS4_DEV_PD
104 select EXYNOS4_DEV_SYSMMU
105 select EXYNOS4_SETUP_I2C1
106 select EXYNOS4_SETUP_SDHCI
107 help
108 Machine support for Samsung SMDKC210
109
110config MACH_SMDKV310
111 bool "SMDKV310"
112 select CPU_EXYNOS4210
113 select S3C_DEV_RTC
114 select S3C_DEV_WDT
115 select S3C_DEV_I2C1
116 select S3C_DEV_HSMMC
117 select S3C_DEV_HSMMC1
118 select S3C_DEV_HSMMC2
119 select S3C_DEV_HSMMC3
120 select SAMSUNG_DEV_KEYPAD
121 select EXYNOS4_DEV_PD
122 select EXYNOS4_DEV_SYSMMU
123 select EXYNOS4_SETUP_I2C1
124 select EXYNOS4_SETUP_KEYPAD
125 select EXYNOS4_SETUP_SDHCI
126 help
127 Machine support for Samsung SMDKV310
128
129config MACH_ARMLEX4210
130 bool "ARMLEX4210"
131 select CPU_EXYNOS4210
132 select S3C_DEV_RTC
133 select S3C_DEV_WDT
134 select S3C_DEV_HSMMC
135 select S3C_DEV_HSMMC2
136 select S3C_DEV_HSMMC3
137 select EXYNOS4_DEV_SYSMMU
138 select EXYNOS4_SETUP_SDHCI
139 select SATA_AHCI_PLATFORM
140 help
141 Machine support for Samsung ARMLEX4210 based on EXYNOS4210
142
143config MACH_UNIVERSAL_C210
144 bool "Mobile UNIVERSAL_C210 Board"
145 select CPU_EXYNOS4210
146 select S3C_DEV_HSMMC
147 select S3C_DEV_HSMMC2
148 select S3C_DEV_HSMMC3
149 select S3C_DEV_I2C1
150 select S3C_DEV_I2C5
151 select S5P_DEV_ONENAND
152 select EXYNOS4_SETUP_I2C1
153 select EXYNOS4_SETUP_I2C5
154 select EXYNOS4_SETUP_SDHCI
155 help
156 Machine support for Samsung Mobile Universal S5PC210 Reference
157 Board.
158
159config MACH_NURI
160 bool "Mobile NURI Board"
161 select CPU_EXYNOS4210
162 select S3C_DEV_WDT
163 select S3C_DEV_HSMMC
164 select S3C_DEV_HSMMC2
165 select S3C_DEV_HSMMC3
166 select S3C_DEV_I2C1
167 select S3C_DEV_I2C5
168 select EXYNOS4_SETUP_I2C1
169 select EXYNOS4_SETUP_I2C5
170 select EXYNOS4_SETUP_SDHCI
171 select SAMSUNG_DEV_PWM
172 help
173 Machine support for Samsung Mobile NURI Board.
174
175endmenu
176
177comment "Configuration for HSMMC bus width"
178
179menu "Use 8-bit bus width"
180
181config EXYNOS4_SDHCI_CH0_8BIT
182 bool "Channel 0 with 8-bit bus"
183 help
184 Support HSMMC Channel 0 8-bit bus.
185 If selected, Channel 1 is disabled.
186
187config EXYNOS4_SDHCI_CH2_8BIT
188 bool "Channel 2 with 8-bit bus"
189 help
190 Support HSMMC Channel 2 8-bit bus.
191 If selected, Channel 3 is disabled.
192
193endmenu
194
195endif
diff --git a/arch/arm/mach-exynos4/Makefile b/arch/arm/mach-exynos4/Makefile
new file mode 100644
index 000000000000..b8f0e7d82d7e
--- /dev/null
+++ b/arch/arm/mach-exynos4/Makefile
@@ -0,0 +1,56 @@
1# arch/arm/mach-exynos4/Makefile
2#
3# Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4# http://www.samsung.com/
5#
6# Licensed under GPLv2
7
8obj-y :=
9obj-m :=
10obj-n :=
11obj- :=
12
13# Core support for EXYNOS4 system
14
15obj-$(CONFIG_CPU_EXYNOS4210) += cpu.o init.o clock.o irq-combiner.o
16obj-$(CONFIG_CPU_EXYNOS4210) += setup-i2c0.o gpiolib.o irq-eint.o dma.o
17obj-$(CONFIG_PM) += pm.o sleep.o
18obj-$(CONFIG_CPU_FREQ) += cpufreq.o
19
20obj-$(CONFIG_SMP) += platsmp.o headsmp.o
21
22ifeq ($(CONFIG_EXYNOS4_MCT),y)
23obj-y += mct.o
24else
25obj-y += time.o
26obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
27endif
28
29obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
30
31# machine support
32
33obj-$(CONFIG_MACH_SMDKC210) += mach-smdkc210.o
34obj-$(CONFIG_MACH_SMDKV310) += mach-smdkv310.o
35obj-$(CONFIG_MACH_ARMLEX4210) += mach-armlex4210.o
36obj-$(CONFIG_MACH_UNIVERSAL_C210) += mach-universal_c210.o
37obj-$(CONFIG_MACH_NURI) += mach-nuri.o
38
39# device support
40
41obj-y += dev-audio.o
42obj-$(CONFIG_EXYNOS4_DEV_PD) += dev-pd.o
43obj-$(CONFIG_EXYNOS4_DEV_SYSMMU) += dev-sysmmu.o
44
45obj-$(CONFIG_EXYNOS4_SETUP_FIMC) += setup-fimc.o
46obj-$(CONFIG_EXYNOS4_SETUP_I2C1) += setup-i2c1.o
47obj-$(CONFIG_EXYNOS4_SETUP_I2C2) += setup-i2c2.o
48obj-$(CONFIG_EXYNOS4_SETUP_I2C3) += setup-i2c3.o
49obj-$(CONFIG_EXYNOS4_SETUP_I2C4) += setup-i2c4.o
50obj-$(CONFIG_EXYNOS4_SETUP_I2C5) += setup-i2c5.o
51obj-$(CONFIG_EXYNOS4_SETUP_I2C6) += setup-i2c6.o
52obj-$(CONFIG_EXYNOS4_SETUP_I2C7) += setup-i2c7.o
53obj-$(CONFIG_EXYNOS4_SETUP_KEYPAD) += setup-keypad.o
54obj-$(CONFIG_EXYNOS4_SETUP_SDHCI) += setup-sdhci.o
55obj-$(CONFIG_EXYNOS4_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
56obj-$(CONFIG_SATA_AHCI_PLATFORM) += dev-ahci.o
diff --git a/arch/arm/mach-s5pv310/Makefile.boot b/arch/arm/mach-exynos4/Makefile.boot
index d65956ffb43d..d65956ffb43d 100644
--- a/arch/arm/mach-s5pv310/Makefile.boot
+++ b/arch/arm/mach-exynos4/Makefile.boot
diff --git a/arch/arm/mach-s5pv310/clock.c b/arch/arm/mach-exynos4/clock.c
index fc7c2f8d165e..871f9d508fde 100644
--- a/arch/arm/mach-s5pv310/clock.c
+++ b/arch/arm/mach-exynos4/clock.c
@@ -1,9 +1,9 @@
1/* linux/arch/arm/mach-s5pv310/clock.c 1/* linux/arch/arm/mach-exynos4/clock.c
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * S5PV310 - Clock support 6 * EXYNOS4 - Clock support
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
@@ -23,6 +23,7 @@
23 23
24#include <mach/map.h> 24#include <mach/map.h>
25#include <mach/regs-clock.h> 25#include <mach/regs-clock.h>
26#include <mach/sysmmu.h>
26 27
27static struct clk clk_sclk_hdmi27m = { 28static struct clk clk_sclk_hdmi27m = {
28 .name = "sclk_hdmi27m", 29 .name = "sclk_hdmi27m",
@@ -46,72 +47,82 @@ static struct clk clk_sclk_usbphy1 = {
46 .id = -1, 47 .id = -1,
47}; 48};
48 49
49static int s5pv310_clksrc_mask_top_ctrl(struct clk *clk, int enable) 50static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
50{ 51{
51 return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable); 52 return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable);
52} 53}
53 54
54static int s5pv310_clksrc_mask_cam_ctrl(struct clk *clk, int enable) 55static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
55{ 56{
56 return s5p_gatectrl(S5P_CLKSRC_MASK_CAM, clk, enable); 57 return s5p_gatectrl(S5P_CLKSRC_MASK_CAM, clk, enable);
57} 58}
58 59
59static int s5pv310_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable) 60static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
60{ 61{
61 return s5p_gatectrl(S5P_CLKSRC_MASK_LCD0, clk, enable); 62 return s5p_gatectrl(S5P_CLKSRC_MASK_LCD0, clk, enable);
62} 63}
63 64
64static int s5pv310_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable) 65static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
65{ 66{
66 return s5p_gatectrl(S5P_CLKSRC_MASK_LCD1, clk, enable); 67 return s5p_gatectrl(S5P_CLKSRC_MASK_LCD1, clk, enable);
67} 68}
68 69
69static int s5pv310_clksrc_mask_fsys_ctrl(struct clk *clk, int enable) 70static int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
70{ 71{
71 return s5p_gatectrl(S5P_CLKSRC_MASK_FSYS, clk, enable); 72 return s5p_gatectrl(S5P_CLKSRC_MASK_FSYS, clk, enable);
72} 73}
73 74
74static int s5pv310_clksrc_mask_peril0_ctrl(struct clk *clk, int enable) 75static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
75{ 76{
76 return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable); 77 return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable);
77} 78}
78 79
79static int s5pv310_clksrc_mask_peril1_ctrl(struct clk *clk, int enable) 80static int exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
80{ 81{
81 return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL1, clk, enable); 82 return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL1, clk, enable);
82} 83}
83 84
84static int s5pv310_clk_ip_cam_ctrl(struct clk *clk, int enable) 85static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable)
86{
87 return s5p_gatectrl(S5P_CLKGATE_IP_MFC, clk, enable);
88}
89
90static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable)
85{ 91{
86 return s5p_gatectrl(S5P_CLKGATE_IP_CAM, clk, enable); 92 return s5p_gatectrl(S5P_CLKGATE_IP_CAM, clk, enable);
87} 93}
88 94
89static int s5pv310_clk_ip_image_ctrl(struct clk *clk, int enable) 95static int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable)
96{
97 return s5p_gatectrl(S5P_CLKGATE_IP_TV, clk, enable);
98}
99
100static int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
90{ 101{
91 return s5p_gatectrl(S5P_CLKGATE_IP_IMAGE, clk, enable); 102 return s5p_gatectrl(S5P_CLKGATE_IP_IMAGE, clk, enable);
92} 103}
93 104
94static int s5pv310_clk_ip_lcd0_ctrl(struct clk *clk, int enable) 105static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
95{ 106{
96 return s5p_gatectrl(S5P_CLKGATE_IP_LCD0, clk, enable); 107 return s5p_gatectrl(S5P_CLKGATE_IP_LCD0, clk, enable);
97} 108}
98 109
99static int s5pv310_clk_ip_lcd1_ctrl(struct clk *clk, int enable) 110static int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
100{ 111{
101 return s5p_gatectrl(S5P_CLKGATE_IP_LCD1, clk, enable); 112 return s5p_gatectrl(S5P_CLKGATE_IP_LCD1, clk, enable);
102} 113}
103 114
104static int s5pv310_clk_ip_fsys_ctrl(struct clk *clk, int enable) 115static int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
105{ 116{
106 return s5p_gatectrl(S5P_CLKGATE_IP_FSYS, clk, enable); 117 return s5p_gatectrl(S5P_CLKGATE_IP_FSYS, clk, enable);
107} 118}
108 119
109static int s5pv310_clk_ip_peril_ctrl(struct clk *clk, int enable) 120static int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable)
110{ 121{
111 return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable); 122 return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable);
112} 123}
113 124
114static int s5pv310_clk_ip_perir_ctrl(struct clk *clk, int enable) 125static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
115{ 126{
116 return s5p_gatectrl(S5P_CLKGATE_IP_PERIR, clk, enable); 127 return s5p_gatectrl(S5P_CLKGATE_IP_PERIR, clk, enable);
117} 128}
@@ -358,7 +369,7 @@ static struct clksrc_clk clk_vpllsrc = {
358 .clk = { 369 .clk = {
359 .name = "vpll_src", 370 .name = "vpll_src",
360 .id = -1, 371 .id = -1,
361 .enable = s5pv310_clksrc_mask_top_ctrl, 372 .enable = exynos4_clksrc_mask_top_ctrl,
362 .ctrlbit = (1 << 0), 373 .ctrlbit = (1 << 0),
363 }, 374 },
364 .sources = &clkset_vpllsrc, 375 .sources = &clkset_vpllsrc,
@@ -389,239 +400,322 @@ static struct clk init_clocks_off[] = {
389 .name = "timers", 400 .name = "timers",
390 .id = -1, 401 .id = -1,
391 .parent = &clk_aclk_100.clk, 402 .parent = &clk_aclk_100.clk,
392 .enable = s5pv310_clk_ip_peril_ctrl, 403 .enable = exynos4_clk_ip_peril_ctrl,
393 .ctrlbit = (1<<24), 404 .ctrlbit = (1<<24),
394 }, { 405 }, {
395 .name = "csis", 406 .name = "csis",
396 .id = 0, 407 .id = 0,
397 .enable = s5pv310_clk_ip_cam_ctrl, 408 .enable = exynos4_clk_ip_cam_ctrl,
398 .ctrlbit = (1 << 4), 409 .ctrlbit = (1 << 4),
399 }, { 410 }, {
400 .name = "csis", 411 .name = "csis",
401 .id = 1, 412 .id = 1,
402 .enable = s5pv310_clk_ip_cam_ctrl, 413 .enable = exynos4_clk_ip_cam_ctrl,
403 .ctrlbit = (1 << 5), 414 .ctrlbit = (1 << 5),
404 }, { 415 }, {
405 .name = "fimc", 416 .name = "fimc",
406 .id = 0, 417 .id = 0,
407 .enable = s5pv310_clk_ip_cam_ctrl, 418 .enable = exynos4_clk_ip_cam_ctrl,
408 .ctrlbit = (1 << 0), 419 .ctrlbit = (1 << 0),
409 }, { 420 }, {
410 .name = "fimc", 421 .name = "fimc",
411 .id = 1, 422 .id = 1,
412 .enable = s5pv310_clk_ip_cam_ctrl, 423 .enable = exynos4_clk_ip_cam_ctrl,
413 .ctrlbit = (1 << 1), 424 .ctrlbit = (1 << 1),
414 }, { 425 }, {
415 .name = "fimc", 426 .name = "fimc",
416 .id = 2, 427 .id = 2,
417 .enable = s5pv310_clk_ip_cam_ctrl, 428 .enable = exynos4_clk_ip_cam_ctrl,
418 .ctrlbit = (1 << 2), 429 .ctrlbit = (1 << 2),
419 }, { 430 }, {
420 .name = "fimc", 431 .name = "fimc",
421 .id = 3, 432 .id = 3,
422 .enable = s5pv310_clk_ip_cam_ctrl, 433 .enable = exynos4_clk_ip_cam_ctrl,
423 .ctrlbit = (1 << 3), 434 .ctrlbit = (1 << 3),
424 }, { 435 }, {
425 .name = "fimd", 436 .name = "fimd",
426 .id = 0, 437 .id = 0,
427 .enable = s5pv310_clk_ip_lcd0_ctrl, 438 .enable = exynos4_clk_ip_lcd0_ctrl,
428 .ctrlbit = (1 << 0), 439 .ctrlbit = (1 << 0),
429 }, { 440 }, {
430 .name = "fimd", 441 .name = "fimd",
431 .id = 1, 442 .id = 1,
432 .enable = s5pv310_clk_ip_lcd1_ctrl, 443 .enable = exynos4_clk_ip_lcd1_ctrl,
433 .ctrlbit = (1 << 0), 444 .ctrlbit = (1 << 0),
434 }, { 445 }, {
446 .name = "sataphy",
447 .id = -1,
448 .parent = &clk_aclk_133.clk,
449 .enable = exynos4_clk_ip_fsys_ctrl,
450 .ctrlbit = (1 << 3),
451 }, {
435 .name = "hsmmc", 452 .name = "hsmmc",
436 .id = 0, 453 .id = 0,
437 .parent = &clk_aclk_133.clk, 454 .parent = &clk_aclk_133.clk,
438 .enable = s5pv310_clk_ip_fsys_ctrl, 455 .enable = exynos4_clk_ip_fsys_ctrl,
439 .ctrlbit = (1 << 5), 456 .ctrlbit = (1 << 5),
440 }, { 457 }, {
441 .name = "hsmmc", 458 .name = "hsmmc",
442 .id = 1, 459 .id = 1,
443 .parent = &clk_aclk_133.clk, 460 .parent = &clk_aclk_133.clk,
444 .enable = s5pv310_clk_ip_fsys_ctrl, 461 .enable = exynos4_clk_ip_fsys_ctrl,
445 .ctrlbit = (1 << 6), 462 .ctrlbit = (1 << 6),
446 }, { 463 }, {
447 .name = "hsmmc", 464 .name = "hsmmc",
448 .id = 2, 465 .id = 2,
449 .parent = &clk_aclk_133.clk, 466 .parent = &clk_aclk_133.clk,
450 .enable = s5pv310_clk_ip_fsys_ctrl, 467 .enable = exynos4_clk_ip_fsys_ctrl,
451 .ctrlbit = (1 << 7), 468 .ctrlbit = (1 << 7),
452 }, { 469 }, {
453 .name = "hsmmc", 470 .name = "hsmmc",
454 .id = 3, 471 .id = 3,
455 .parent = &clk_aclk_133.clk, 472 .parent = &clk_aclk_133.clk,
456 .enable = s5pv310_clk_ip_fsys_ctrl, 473 .enable = exynos4_clk_ip_fsys_ctrl,
457 .ctrlbit = (1 << 8), 474 .ctrlbit = (1 << 8),
458 }, { 475 }, {
459 .name = "hsmmc", 476 .name = "hsmmc",
460 .id = 4, 477 .id = 4,
461 .parent = &clk_aclk_133.clk, 478 .parent = &clk_aclk_133.clk,
462 .enable = s5pv310_clk_ip_fsys_ctrl, 479 .enable = exynos4_clk_ip_fsys_ctrl,
463 .ctrlbit = (1 << 9), 480 .ctrlbit = (1 << 9),
464 }, { 481 }, {
465 .name = "sata", 482 .name = "sata",
466 .id = -1, 483 .id = -1,
467 .enable = s5pv310_clk_ip_fsys_ctrl, 484 .parent = &clk_aclk_133.clk,
485 .enable = exynos4_clk_ip_fsys_ctrl,
468 .ctrlbit = (1 << 10), 486 .ctrlbit = (1 << 10),
469 }, { 487 }, {
470 .name = "pdma", 488 .name = "pdma",
471 .id = 0, 489 .id = 0,
472 .enable = s5pv310_clk_ip_fsys_ctrl, 490 .enable = exynos4_clk_ip_fsys_ctrl,
473 .ctrlbit = (1 << 0), 491 .ctrlbit = (1 << 0),
474 }, { 492 }, {
475 .name = "pdma", 493 .name = "pdma",
476 .id = 1, 494 .id = 1,
477 .enable = s5pv310_clk_ip_fsys_ctrl, 495 .enable = exynos4_clk_ip_fsys_ctrl,
478 .ctrlbit = (1 << 1), 496 .ctrlbit = (1 << 1),
479 }, { 497 }, {
480 .name = "adc", 498 .name = "adc",
481 .id = -1, 499 .id = -1,
482 .enable = s5pv310_clk_ip_peril_ctrl, 500 .enable = exynos4_clk_ip_peril_ctrl,
483 .ctrlbit = (1 << 15), 501 .ctrlbit = (1 << 15),
484 }, { 502 }, {
503 .name = "keypad",
504 .id = -1,
505 .enable = exynos4_clk_ip_perir_ctrl,
506 .ctrlbit = (1 << 16),
507 }, {
485 .name = "rtc", 508 .name = "rtc",
486 .id = -1, 509 .id = -1,
487 .enable = s5pv310_clk_ip_perir_ctrl, 510 .enable = exynos4_clk_ip_perir_ctrl,
488 .ctrlbit = (1 << 15), 511 .ctrlbit = (1 << 15),
489 }, { 512 }, {
490 .name = "watchdog", 513 .name = "watchdog",
491 .id = -1, 514 .id = -1,
492 .enable = s5pv310_clk_ip_perir_ctrl, 515 .parent = &clk_aclk_100.clk,
516 .enable = exynos4_clk_ip_perir_ctrl,
493 .ctrlbit = (1 << 14), 517 .ctrlbit = (1 << 14),
494 }, { 518 }, {
495 .name = "usbhost", 519 .name = "usbhost",
496 .id = -1, 520 .id = -1,
497 .enable = s5pv310_clk_ip_fsys_ctrl , 521 .enable = exynos4_clk_ip_fsys_ctrl ,
498 .ctrlbit = (1 << 12), 522 .ctrlbit = (1 << 12),
499 }, { 523 }, {
500 .name = "otg", 524 .name = "otg",
501 .id = -1, 525 .id = -1,
502 .enable = s5pv310_clk_ip_fsys_ctrl, 526 .enable = exynos4_clk_ip_fsys_ctrl,
503 .ctrlbit = (1 << 13), 527 .ctrlbit = (1 << 13),
504 }, { 528 }, {
505 .name = "spi", 529 .name = "spi",
506 .id = 0, 530 .id = 0,
507 .enable = s5pv310_clk_ip_peril_ctrl, 531 .enable = exynos4_clk_ip_peril_ctrl,
508 .ctrlbit = (1 << 16), 532 .ctrlbit = (1 << 16),
509 }, { 533 }, {
510 .name = "spi", 534 .name = "spi",
511 .id = 1, 535 .id = 1,
512 .enable = s5pv310_clk_ip_peril_ctrl, 536 .enable = exynos4_clk_ip_peril_ctrl,
513 .ctrlbit = (1 << 17), 537 .ctrlbit = (1 << 17),
514 }, { 538 }, {
515 .name = "spi", 539 .name = "spi",
516 .id = 2, 540 .id = 2,
517 .enable = s5pv310_clk_ip_peril_ctrl, 541 .enable = exynos4_clk_ip_peril_ctrl,
518 .ctrlbit = (1 << 18), 542 .ctrlbit = (1 << 18),
519 }, { 543 }, {
520 .name = "iis", 544 .name = "iis",
521 .id = 0, 545 .id = 0,
522 .enable = s5pv310_clk_ip_peril_ctrl, 546 .enable = exynos4_clk_ip_peril_ctrl,
523 .ctrlbit = (1 << 19), 547 .ctrlbit = (1 << 19),
524 }, { 548 }, {
525 .name = "iis", 549 .name = "iis",
526 .id = 1, 550 .id = 1,
527 .enable = s5pv310_clk_ip_peril_ctrl, 551 .enable = exynos4_clk_ip_peril_ctrl,
528 .ctrlbit = (1 << 20), 552 .ctrlbit = (1 << 20),
529 }, { 553 }, {
530 .name = "iis", 554 .name = "iis",
531 .id = 2, 555 .id = 2,
532 .enable = s5pv310_clk_ip_peril_ctrl, 556 .enable = exynos4_clk_ip_peril_ctrl,
533 .ctrlbit = (1 << 21), 557 .ctrlbit = (1 << 21),
534 }, { 558 }, {
535 .name = "ac97", 559 .name = "ac97",
536 .id = -1, 560 .id = -1,
537 .enable = s5pv310_clk_ip_peril_ctrl, 561 .enable = exynos4_clk_ip_peril_ctrl,
538 .ctrlbit = (1 << 27), 562 .ctrlbit = (1 << 27),
539 }, { 563 }, {
540 .name = "fimg2d", 564 .name = "fimg2d",
541 .id = -1, 565 .id = -1,
542 .enable = s5pv310_clk_ip_image_ctrl, 566 .enable = exynos4_clk_ip_image_ctrl,
543 .ctrlbit = (1 << 0), 567 .ctrlbit = (1 << 0),
544 }, { 568 }, {
545 .name = "i2c", 569 .name = "i2c",
546 .id = 0, 570 .id = 0,
547 .parent = &clk_aclk_100.clk, 571 .parent = &clk_aclk_100.clk,
548 .enable = s5pv310_clk_ip_peril_ctrl, 572 .enable = exynos4_clk_ip_peril_ctrl,
549 .ctrlbit = (1 << 6), 573 .ctrlbit = (1 << 6),
550 }, { 574 }, {
551 .name = "i2c", 575 .name = "i2c",
552 .id = 1, 576 .id = 1,
553 .parent = &clk_aclk_100.clk, 577 .parent = &clk_aclk_100.clk,
554 .enable = s5pv310_clk_ip_peril_ctrl, 578 .enable = exynos4_clk_ip_peril_ctrl,
555 .ctrlbit = (1 << 7), 579 .ctrlbit = (1 << 7),
556 }, { 580 }, {
557 .name = "i2c", 581 .name = "i2c",
558 .id = 2, 582 .id = 2,
559 .parent = &clk_aclk_100.clk, 583 .parent = &clk_aclk_100.clk,
560 .enable = s5pv310_clk_ip_peril_ctrl, 584 .enable = exynos4_clk_ip_peril_ctrl,
561 .ctrlbit = (1 << 8), 585 .ctrlbit = (1 << 8),
562 }, { 586 }, {
563 .name = "i2c", 587 .name = "i2c",
564 .id = 3, 588 .id = 3,
565 .parent = &clk_aclk_100.clk, 589 .parent = &clk_aclk_100.clk,
566 .enable = s5pv310_clk_ip_peril_ctrl, 590 .enable = exynos4_clk_ip_peril_ctrl,
567 .ctrlbit = (1 << 9), 591 .ctrlbit = (1 << 9),
568 }, { 592 }, {
569 .name = "i2c", 593 .name = "i2c",
570 .id = 4, 594 .id = 4,
571 .parent = &clk_aclk_100.clk, 595 .parent = &clk_aclk_100.clk,
572 .enable = s5pv310_clk_ip_peril_ctrl, 596 .enable = exynos4_clk_ip_peril_ctrl,
573 .ctrlbit = (1 << 10), 597 .ctrlbit = (1 << 10),
574 }, { 598 }, {
575 .name = "i2c", 599 .name = "i2c",
576 .id = 5, 600 .id = 5,
577 .parent = &clk_aclk_100.clk, 601 .parent = &clk_aclk_100.clk,
578 .enable = s5pv310_clk_ip_peril_ctrl, 602 .enable = exynos4_clk_ip_peril_ctrl,
579 .ctrlbit = (1 << 11), 603 .ctrlbit = (1 << 11),
580 }, { 604 }, {
581 .name = "i2c", 605 .name = "i2c",
582 .id = 6, 606 .id = 6,
583 .parent = &clk_aclk_100.clk, 607 .parent = &clk_aclk_100.clk,
584 .enable = s5pv310_clk_ip_peril_ctrl, 608 .enable = exynos4_clk_ip_peril_ctrl,
585 .ctrlbit = (1 << 12), 609 .ctrlbit = (1 << 12),
586 }, { 610 }, {
587 .name = "i2c", 611 .name = "i2c",
588 .id = 7, 612 .id = 7,
589 .parent = &clk_aclk_100.clk, 613 .parent = &clk_aclk_100.clk,
590 .enable = s5pv310_clk_ip_peril_ctrl, 614 .enable = exynos4_clk_ip_peril_ctrl,
591 .ctrlbit = (1 << 13), 615 .ctrlbit = (1 << 13),
592 }, 616 }, {
617 .name = "SYSMMU_MDMA",
618 .id = -1,
619 .enable = exynos4_clk_ip_image_ctrl,
620 .ctrlbit = (1 << 5),
621 }, {
622 .name = "SYSMMU_FIMC0",
623 .id = -1,
624 .enable = exynos4_clk_ip_cam_ctrl,
625 .ctrlbit = (1 << 7),
626 }, {
627 .name = "SYSMMU_FIMC1",
628 .id = -1,
629 .enable = exynos4_clk_ip_cam_ctrl,
630 .ctrlbit = (1 << 8),
631 }, {
632 .name = "SYSMMU_FIMC2",
633 .id = -1,
634 .enable = exynos4_clk_ip_cam_ctrl,
635 .ctrlbit = (1 << 9),
636 }, {
637 .name = "SYSMMU_FIMC3",
638 .id = -1,
639 .enable = exynos4_clk_ip_cam_ctrl,
640 .ctrlbit = (1 << 10),
641 }, {
642 .name = "SYSMMU_JPEG",
643 .id = -1,
644 .enable = exynos4_clk_ip_cam_ctrl,
645 .ctrlbit = (1 << 11),
646 }, {
647 .name = "SYSMMU_FIMD0",
648 .id = -1,
649 .enable = exynos4_clk_ip_lcd0_ctrl,
650 .ctrlbit = (1 << 4),
651 }, {
652 .name = "SYSMMU_FIMD1",
653 .id = -1,
654 .enable = exynos4_clk_ip_lcd1_ctrl,
655 .ctrlbit = (1 << 4),
656 }, {
657 .name = "SYSMMU_PCIe",
658 .id = -1,
659 .enable = exynos4_clk_ip_fsys_ctrl,
660 .ctrlbit = (1 << 18),
661 }, {
662 .name = "SYSMMU_G2D",
663 .id = -1,
664 .enable = exynos4_clk_ip_image_ctrl,
665 .ctrlbit = (1 << 3),
666 }, {
667 .name = "SYSMMU_ROTATOR",
668 .id = -1,
669 .enable = exynos4_clk_ip_image_ctrl,
670 .ctrlbit = (1 << 4),
671 }, {
672 .name = "SYSMMU_TV",
673 .id = -1,
674 .enable = exynos4_clk_ip_tv_ctrl,
675 .ctrlbit = (1 << 4),
676 }, {
677 .name = "SYSMMU_MFC_L",
678 .id = -1,
679 .enable = exynos4_clk_ip_mfc_ctrl,
680 .ctrlbit = (1 << 1),
681 }, {
682 .name = "SYSMMU_MFC_R",
683 .id = -1,
684 .enable = exynos4_clk_ip_mfc_ctrl,
685 .ctrlbit = (1 << 2),
686 }
593}; 687};
594 688
595static struct clk init_clocks[] = { 689static struct clk init_clocks[] = {
596 { 690 {
597 .name = "uart", 691 .name = "uart",
598 .id = 0, 692 .id = 0,
599 .enable = s5pv310_clk_ip_peril_ctrl, 693 .enable = exynos4_clk_ip_peril_ctrl,
600 .ctrlbit = (1 << 0), 694 .ctrlbit = (1 << 0),
601 }, { 695 }, {
602 .name = "uart", 696 .name = "uart",
603 .id = 1, 697 .id = 1,
604 .enable = s5pv310_clk_ip_peril_ctrl, 698 .enable = exynos4_clk_ip_peril_ctrl,
605 .ctrlbit = (1 << 1), 699 .ctrlbit = (1 << 1),
606 }, { 700 }, {
607 .name = "uart", 701 .name = "uart",
608 .id = 2, 702 .id = 2,
609 .enable = s5pv310_clk_ip_peril_ctrl, 703 .enable = exynos4_clk_ip_peril_ctrl,
610 .ctrlbit = (1 << 2), 704 .ctrlbit = (1 << 2),
611 }, { 705 }, {
612 .name = "uart", 706 .name = "uart",
613 .id = 3, 707 .id = 3,
614 .enable = s5pv310_clk_ip_peril_ctrl, 708 .enable = exynos4_clk_ip_peril_ctrl,
615 .ctrlbit = (1 << 3), 709 .ctrlbit = (1 << 3),
616 }, { 710 }, {
617 .name = "uart", 711 .name = "uart",
618 .id = 4, 712 .id = 4,
619 .enable = s5pv310_clk_ip_peril_ctrl, 713 .enable = exynos4_clk_ip_peril_ctrl,
620 .ctrlbit = (1 << 4), 714 .ctrlbit = (1 << 4),
621 }, { 715 }, {
622 .name = "uart", 716 .name = "uart",
623 .id = 5, 717 .id = 5,
624 .enable = s5pv310_clk_ip_peril_ctrl, 718 .enable = exynos4_clk_ip_peril_ctrl,
625 .ctrlbit = (1 << 5), 719 .ctrlbit = (1 << 5),
626 } 720 }
627}; 721};
@@ -746,7 +840,7 @@ static struct clksrc_clk clksrcs[] = {
746 .clk = { 840 .clk = {
747 .name = "uclk1", 841 .name = "uclk1",
748 .id = 0, 842 .id = 0,
749 .enable = s5pv310_clksrc_mask_peril0_ctrl, 843 .enable = exynos4_clksrc_mask_peril0_ctrl,
750 .ctrlbit = (1 << 0), 844 .ctrlbit = (1 << 0),
751 }, 845 },
752 .sources = &clkset_group, 846 .sources = &clkset_group,
@@ -756,7 +850,7 @@ static struct clksrc_clk clksrcs[] = {
756 .clk = { 850 .clk = {
757 .name = "uclk1", 851 .name = "uclk1",
758 .id = 1, 852 .id = 1,
759 .enable = s5pv310_clksrc_mask_peril0_ctrl, 853 .enable = exynos4_clksrc_mask_peril0_ctrl,
760 .ctrlbit = (1 << 4), 854 .ctrlbit = (1 << 4),
761 }, 855 },
762 .sources = &clkset_group, 856 .sources = &clkset_group,
@@ -766,7 +860,7 @@ static struct clksrc_clk clksrcs[] = {
766 .clk = { 860 .clk = {
767 .name = "uclk1", 861 .name = "uclk1",
768 .id = 2, 862 .id = 2,
769 .enable = s5pv310_clksrc_mask_peril0_ctrl, 863 .enable = exynos4_clksrc_mask_peril0_ctrl,
770 .ctrlbit = (1 << 8), 864 .ctrlbit = (1 << 8),
771 }, 865 },
772 .sources = &clkset_group, 866 .sources = &clkset_group,
@@ -776,7 +870,7 @@ static struct clksrc_clk clksrcs[] = {
776 .clk = { 870 .clk = {
777 .name = "uclk1", 871 .name = "uclk1",
778 .id = 3, 872 .id = 3,
779 .enable = s5pv310_clksrc_mask_peril0_ctrl, 873 .enable = exynos4_clksrc_mask_peril0_ctrl,
780 .ctrlbit = (1 << 12), 874 .ctrlbit = (1 << 12),
781 }, 875 },
782 .sources = &clkset_group, 876 .sources = &clkset_group,
@@ -786,7 +880,7 @@ static struct clksrc_clk clksrcs[] = {
786 .clk = { 880 .clk = {
787 .name = "sclk_pwm", 881 .name = "sclk_pwm",
788 .id = -1, 882 .id = -1,
789 .enable = s5pv310_clksrc_mask_peril0_ctrl, 883 .enable = exynos4_clksrc_mask_peril0_ctrl,
790 .ctrlbit = (1 << 24), 884 .ctrlbit = (1 << 24),
791 }, 885 },
792 .sources = &clkset_group, 886 .sources = &clkset_group,
@@ -796,7 +890,7 @@ static struct clksrc_clk clksrcs[] = {
796 .clk = { 890 .clk = {
797 .name = "sclk_csis", 891 .name = "sclk_csis",
798 .id = 0, 892 .id = 0,
799 .enable = s5pv310_clksrc_mask_cam_ctrl, 893 .enable = exynos4_clksrc_mask_cam_ctrl,
800 .ctrlbit = (1 << 24), 894 .ctrlbit = (1 << 24),
801 }, 895 },
802 .sources = &clkset_group, 896 .sources = &clkset_group,
@@ -806,7 +900,7 @@ static struct clksrc_clk clksrcs[] = {
806 .clk = { 900 .clk = {
807 .name = "sclk_csis", 901 .name = "sclk_csis",
808 .id = 1, 902 .id = 1,
809 .enable = s5pv310_clksrc_mask_cam_ctrl, 903 .enable = exynos4_clksrc_mask_cam_ctrl,
810 .ctrlbit = (1 << 28), 904 .ctrlbit = (1 << 28),
811 }, 905 },
812 .sources = &clkset_group, 906 .sources = &clkset_group,
@@ -816,7 +910,7 @@ static struct clksrc_clk clksrcs[] = {
816 .clk = { 910 .clk = {
817 .name = "sclk_cam", 911 .name = "sclk_cam",
818 .id = 0, 912 .id = 0,
819 .enable = s5pv310_clksrc_mask_cam_ctrl, 913 .enable = exynos4_clksrc_mask_cam_ctrl,
820 .ctrlbit = (1 << 16), 914 .ctrlbit = (1 << 16),
821 }, 915 },
822 .sources = &clkset_group, 916 .sources = &clkset_group,
@@ -826,7 +920,7 @@ static struct clksrc_clk clksrcs[] = {
826 .clk = { 920 .clk = {
827 .name = "sclk_cam", 921 .name = "sclk_cam",
828 .id = 1, 922 .id = 1,
829 .enable = s5pv310_clksrc_mask_cam_ctrl, 923 .enable = exynos4_clksrc_mask_cam_ctrl,
830 .ctrlbit = (1 << 20), 924 .ctrlbit = (1 << 20),
831 }, 925 },
832 .sources = &clkset_group, 926 .sources = &clkset_group,
@@ -836,7 +930,7 @@ static struct clksrc_clk clksrcs[] = {
836 .clk = { 930 .clk = {
837 .name = "sclk_fimc", 931 .name = "sclk_fimc",
838 .id = 0, 932 .id = 0,
839 .enable = s5pv310_clksrc_mask_cam_ctrl, 933 .enable = exynos4_clksrc_mask_cam_ctrl,
840 .ctrlbit = (1 << 0), 934 .ctrlbit = (1 << 0),
841 }, 935 },
842 .sources = &clkset_group, 936 .sources = &clkset_group,
@@ -846,7 +940,7 @@ static struct clksrc_clk clksrcs[] = {
846 .clk = { 940 .clk = {
847 .name = "sclk_fimc", 941 .name = "sclk_fimc",
848 .id = 1, 942 .id = 1,
849 .enable = s5pv310_clksrc_mask_cam_ctrl, 943 .enable = exynos4_clksrc_mask_cam_ctrl,
850 .ctrlbit = (1 << 4), 944 .ctrlbit = (1 << 4),
851 }, 945 },
852 .sources = &clkset_group, 946 .sources = &clkset_group,
@@ -856,7 +950,7 @@ static struct clksrc_clk clksrcs[] = {
856 .clk = { 950 .clk = {
857 .name = "sclk_fimc", 951 .name = "sclk_fimc",
858 .id = 2, 952 .id = 2,
859 .enable = s5pv310_clksrc_mask_cam_ctrl, 953 .enable = exynos4_clksrc_mask_cam_ctrl,
860 .ctrlbit = (1 << 8), 954 .ctrlbit = (1 << 8),
861 }, 955 },
862 .sources = &clkset_group, 956 .sources = &clkset_group,
@@ -866,7 +960,7 @@ static struct clksrc_clk clksrcs[] = {
866 .clk = { 960 .clk = {
867 .name = "sclk_fimc", 961 .name = "sclk_fimc",
868 .id = 3, 962 .id = 3,
869 .enable = s5pv310_clksrc_mask_cam_ctrl, 963 .enable = exynos4_clksrc_mask_cam_ctrl,
870 .ctrlbit = (1 << 12), 964 .ctrlbit = (1 << 12),
871 }, 965 },
872 .sources = &clkset_group, 966 .sources = &clkset_group,
@@ -876,7 +970,7 @@ static struct clksrc_clk clksrcs[] = {
876 .clk = { 970 .clk = {
877 .name = "sclk_fimd", 971 .name = "sclk_fimd",
878 .id = 0, 972 .id = 0,
879 .enable = s5pv310_clksrc_mask_lcd0_ctrl, 973 .enable = exynos4_clksrc_mask_lcd0_ctrl,
880 .ctrlbit = (1 << 0), 974 .ctrlbit = (1 << 0),
881 }, 975 },
882 .sources = &clkset_group, 976 .sources = &clkset_group,
@@ -886,7 +980,7 @@ static struct clksrc_clk clksrcs[] = {
886 .clk = { 980 .clk = {
887 .name = "sclk_fimd", 981 .name = "sclk_fimd",
888 .id = 1, 982 .id = 1,
889 .enable = s5pv310_clksrc_mask_lcd1_ctrl, 983 .enable = exynos4_clksrc_mask_lcd1_ctrl,
890 .ctrlbit = (1 << 0), 984 .ctrlbit = (1 << 0),
891 }, 985 },
892 .sources = &clkset_group, 986 .sources = &clkset_group,
@@ -896,7 +990,7 @@ static struct clksrc_clk clksrcs[] = {
896 .clk = { 990 .clk = {
897 .name = "sclk_sata", 991 .name = "sclk_sata",
898 .id = -1, 992 .id = -1,
899 .enable = s5pv310_clksrc_mask_fsys_ctrl, 993 .enable = exynos4_clksrc_mask_fsys_ctrl,
900 .ctrlbit = (1 << 24), 994 .ctrlbit = (1 << 24),
901 }, 995 },
902 .sources = &clkset_mout_corebus, 996 .sources = &clkset_mout_corebus,
@@ -906,7 +1000,7 @@ static struct clksrc_clk clksrcs[] = {
906 .clk = { 1000 .clk = {
907 .name = "sclk_spi", 1001 .name = "sclk_spi",
908 .id = 0, 1002 .id = 0,
909 .enable = s5pv310_clksrc_mask_peril1_ctrl, 1003 .enable = exynos4_clksrc_mask_peril1_ctrl,
910 .ctrlbit = (1 << 16), 1004 .ctrlbit = (1 << 16),
911 }, 1005 },
912 .sources = &clkset_group, 1006 .sources = &clkset_group,
@@ -916,7 +1010,7 @@ static struct clksrc_clk clksrcs[] = {
916 .clk = { 1010 .clk = {
917 .name = "sclk_spi", 1011 .name = "sclk_spi",
918 .id = 1, 1012 .id = 1,
919 .enable = s5pv310_clksrc_mask_peril1_ctrl, 1013 .enable = exynos4_clksrc_mask_peril1_ctrl,
920 .ctrlbit = (1 << 20), 1014 .ctrlbit = (1 << 20),
921 }, 1015 },
922 .sources = &clkset_group, 1016 .sources = &clkset_group,
@@ -926,7 +1020,7 @@ static struct clksrc_clk clksrcs[] = {
926 .clk = { 1020 .clk = {
927 .name = "sclk_spi", 1021 .name = "sclk_spi",
928 .id = 2, 1022 .id = 2,
929 .enable = s5pv310_clksrc_mask_peril1_ctrl, 1023 .enable = exynos4_clksrc_mask_peril1_ctrl,
930 .ctrlbit = (1 << 24), 1024 .ctrlbit = (1 << 24),
931 }, 1025 },
932 .sources = &clkset_group, 1026 .sources = &clkset_group,
@@ -945,7 +1039,7 @@ static struct clksrc_clk clksrcs[] = {
945 .name = "sclk_mmc", 1039 .name = "sclk_mmc",
946 .id = 0, 1040 .id = 0,
947 .parent = &clk_dout_mmc0.clk, 1041 .parent = &clk_dout_mmc0.clk,
948 .enable = s5pv310_clksrc_mask_fsys_ctrl, 1042 .enable = exynos4_clksrc_mask_fsys_ctrl,
949 .ctrlbit = (1 << 0), 1043 .ctrlbit = (1 << 0),
950 }, 1044 },
951 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 }, 1045 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 },
@@ -954,7 +1048,7 @@ static struct clksrc_clk clksrcs[] = {
954 .name = "sclk_mmc", 1048 .name = "sclk_mmc",
955 .id = 1, 1049 .id = 1,
956 .parent = &clk_dout_mmc1.clk, 1050 .parent = &clk_dout_mmc1.clk,
957 .enable = s5pv310_clksrc_mask_fsys_ctrl, 1051 .enable = exynos4_clksrc_mask_fsys_ctrl,
958 .ctrlbit = (1 << 4), 1052 .ctrlbit = (1 << 4),
959 }, 1053 },
960 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 }, 1054 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 },
@@ -963,7 +1057,7 @@ static struct clksrc_clk clksrcs[] = {
963 .name = "sclk_mmc", 1057 .name = "sclk_mmc",
964 .id = 2, 1058 .id = 2,
965 .parent = &clk_dout_mmc2.clk, 1059 .parent = &clk_dout_mmc2.clk,
966 .enable = s5pv310_clksrc_mask_fsys_ctrl, 1060 .enable = exynos4_clksrc_mask_fsys_ctrl,
967 .ctrlbit = (1 << 8), 1061 .ctrlbit = (1 << 8),
968 }, 1062 },
969 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 }, 1063 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 },
@@ -972,7 +1066,7 @@ static struct clksrc_clk clksrcs[] = {
972 .name = "sclk_mmc", 1066 .name = "sclk_mmc",
973 .id = 3, 1067 .id = 3,
974 .parent = &clk_dout_mmc3.clk, 1068 .parent = &clk_dout_mmc3.clk,
975 .enable = s5pv310_clksrc_mask_fsys_ctrl, 1069 .enable = exynos4_clksrc_mask_fsys_ctrl,
976 .ctrlbit = (1 << 12), 1070 .ctrlbit = (1 << 12),
977 }, 1071 },
978 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 }, 1072 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
@@ -981,7 +1075,7 @@ static struct clksrc_clk clksrcs[] = {
981 .name = "sclk_mmc", 1075 .name = "sclk_mmc",
982 .id = 4, 1076 .id = 4,
983 .parent = &clk_dout_mmc4.clk, 1077 .parent = &clk_dout_mmc4.clk,
984 .enable = s5pv310_clksrc_mask_fsys_ctrl, 1078 .enable = exynos4_clksrc_mask_fsys_ctrl,
985 .ctrlbit = (1 << 16), 1079 .ctrlbit = (1 << 16),
986 }, 1080 },
987 .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 8, .size = 8 }, 1081 .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 8, .size = 8 },
@@ -1022,16 +1116,16 @@ static struct clksrc_clk *sysclks[] = {
1022 1116
1023static int xtal_rate; 1117static int xtal_rate;
1024 1118
1025static unsigned long s5pv310_fout_apll_get_rate(struct clk *clk) 1119static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
1026{ 1120{
1027 return s5p_get_pll45xx(xtal_rate, __raw_readl(S5P_APLL_CON0), pll_4508); 1121 return s5p_get_pll45xx(xtal_rate, __raw_readl(S5P_APLL_CON0), pll_4508);
1028} 1122}
1029 1123
1030static struct clk_ops s5pv310_fout_apll_ops = { 1124static struct clk_ops exynos4_fout_apll_ops = {
1031 .get_rate = s5pv310_fout_apll_get_rate, 1125 .get_rate = exynos4_fout_apll_get_rate,
1032}; 1126};
1033 1127
1034void __init_or_cpufreq s5pv310_setup_clocks(void) 1128void __init_or_cpufreq exynos4_setup_clocks(void)
1035{ 1129{
1036 struct clk *xtal_clk; 1130 struct clk *xtal_clk;
1037 unsigned long apll; 1131 unsigned long apll;
@@ -1070,12 +1164,12 @@ void __init_or_cpufreq s5pv310_setup_clocks(void)
1070 vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0), 1164 vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
1071 __raw_readl(S5P_VPLL_CON1), pll_4650); 1165 __raw_readl(S5P_VPLL_CON1), pll_4650);
1072 1166
1073 clk_fout_apll.ops = &s5pv310_fout_apll_ops; 1167 clk_fout_apll.ops = &exynos4_fout_apll_ops;
1074 clk_fout_mpll.rate = mpll; 1168 clk_fout_mpll.rate = mpll;
1075 clk_fout_epll.rate = epll; 1169 clk_fout_epll.rate = epll;
1076 clk_fout_vpll.rate = vpll; 1170 clk_fout_vpll.rate = vpll;
1077 1171
1078 printk(KERN_INFO "S5PV310: PLL settings, A=%ld, M=%ld, E=%ld V=%ld", 1172 printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
1079 apll, mpll, epll, vpll); 1173 apll, mpll, epll, vpll);
1080 1174
1081 armclk = clk_get_rate(&clk_armclk.clk); 1175 armclk = clk_get_rate(&clk_armclk.clk);
@@ -1086,7 +1180,7 @@ void __init_or_cpufreq s5pv310_setup_clocks(void)
1086 aclk_160 = clk_get_rate(&clk_aclk_160.clk); 1180 aclk_160 = clk_get_rate(&clk_aclk_160.clk);
1087 aclk_133 = clk_get_rate(&clk_aclk_133.clk); 1181 aclk_133 = clk_get_rate(&clk_aclk_133.clk);
1088 1182
1089 printk(KERN_INFO "S5PV310: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n" 1183 printk(KERN_INFO "EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
1090 "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n", 1184 "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
1091 armclk, sclk_dmc, aclk_200, 1185 armclk, sclk_dmc, aclk_200,
1092 aclk_100, aclk_160, aclk_133); 1186 aclk_100, aclk_160, aclk_133);
@@ -1103,7 +1197,7 @@ static struct clk *clks[] __initdata = {
1103 /* Nothing here yet */ 1197 /* Nothing here yet */
1104}; 1198};
1105 1199
1106void __init s5pv310_register_clocks(void) 1200void __init exynos4_register_clocks(void)
1107{ 1201{
1108 int ptr; 1202 int ptr;
1109 1203
diff --git a/arch/arm/mach-s5pv310/cpu.c b/arch/arm/mach-exynos4/cpu.c
index 0db0fb65bd70..793011391943 100644
--- a/arch/arm/mach-s5pv310/cpu.c
+++ b/arch/arm/mach-exynos4/cpu.c
@@ -1,7 +1,7 @@
1/* linux/arch/arm/mach-s5pv310/cpu.c 1/* linux/arch/arm/mach-exynos4/cpu.c
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as 7 * it under the terms of the GNU General Public License version 2 as
@@ -19,8 +19,10 @@
19 19
20#include <plat/cpu.h> 20#include <plat/cpu.h>
21#include <plat/clock.h> 21#include <plat/clock.h>
22#include <plat/s5pv310.h> 22#include <plat/exynos4.h>
23#include <plat/sdhci.h> 23#include <plat/sdhci.h>
24#include <plat/devs.h>
25#include <plat/fimc-core.h>
24 26
25#include <mach/regs-irq.h> 27#include <mach/regs-irq.h>
26 28
@@ -29,55 +31,60 @@ extern int combiner_init(unsigned int combiner_nr, void __iomem *base,
29extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq); 31extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq);
30 32
31/* Initial IO mappings */ 33/* Initial IO mappings */
32static struct map_desc s5pv310_iodesc[] __initdata = { 34static struct map_desc exynos4_iodesc[] __initdata = {
33 { 35 {
36 .virtual = (unsigned long)S5P_VA_SYSTIMER,
37 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
38 .length = SZ_4K,
39 .type = MT_DEVICE,
40 }, {
34 .virtual = (unsigned long)S5P_VA_SYSRAM, 41 .virtual = (unsigned long)S5P_VA_SYSRAM,
35 .pfn = __phys_to_pfn(S5PV310_PA_SYSRAM), 42 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM),
36 .length = SZ_4K, 43 .length = SZ_4K,
37 .type = MT_DEVICE, 44 .type = MT_DEVICE,
38 }, { 45 }, {
39 .virtual = (unsigned long)S5P_VA_CMU, 46 .virtual = (unsigned long)S5P_VA_CMU,
40 .pfn = __phys_to_pfn(S5PV310_PA_CMU), 47 .pfn = __phys_to_pfn(EXYNOS4_PA_CMU),
41 .length = SZ_128K, 48 .length = SZ_128K,
42 .type = MT_DEVICE, 49 .type = MT_DEVICE,
43 }, { 50 }, {
44 .virtual = (unsigned long)S5P_VA_PMU, 51 .virtual = (unsigned long)S5P_VA_PMU,
45 .pfn = __phys_to_pfn(S5PV310_PA_PMU), 52 .pfn = __phys_to_pfn(EXYNOS4_PA_PMU),
46 .length = SZ_64K, 53 .length = SZ_64K,
47 .type = MT_DEVICE, 54 .type = MT_DEVICE,
48 }, { 55 }, {
49 .virtual = (unsigned long)S5P_VA_COMBINER_BASE, 56 .virtual = (unsigned long)S5P_VA_COMBINER_BASE,
50 .pfn = __phys_to_pfn(S5PV310_PA_COMBINER), 57 .pfn = __phys_to_pfn(EXYNOS4_PA_COMBINER),
51 .length = SZ_4K, 58 .length = SZ_4K,
52 .type = MT_DEVICE, 59 .type = MT_DEVICE,
53 }, { 60 }, {
54 .virtual = (unsigned long)S5P_VA_COREPERI_BASE, 61 .virtual = (unsigned long)S5P_VA_COREPERI_BASE,
55 .pfn = __phys_to_pfn(S5PV310_PA_COREPERI), 62 .pfn = __phys_to_pfn(EXYNOS4_PA_COREPERI),
56 .length = SZ_8K, 63 .length = SZ_8K,
57 .type = MT_DEVICE, 64 .type = MT_DEVICE,
58 }, { 65 }, {
59 .virtual = (unsigned long)S5P_VA_L2CC, 66 .virtual = (unsigned long)S5P_VA_L2CC,
60 .pfn = __phys_to_pfn(S5PV310_PA_L2CC), 67 .pfn = __phys_to_pfn(EXYNOS4_PA_L2CC),
61 .length = SZ_4K, 68 .length = SZ_4K,
62 .type = MT_DEVICE, 69 .type = MT_DEVICE,
63 }, { 70 }, {
64 .virtual = (unsigned long)S5P_VA_GPIO1, 71 .virtual = (unsigned long)S5P_VA_GPIO1,
65 .pfn = __phys_to_pfn(S5PV310_PA_GPIO1), 72 .pfn = __phys_to_pfn(EXYNOS4_PA_GPIO1),
66 .length = SZ_4K, 73 .length = SZ_4K,
67 .type = MT_DEVICE, 74 .type = MT_DEVICE,
68 }, { 75 }, {
69 .virtual = (unsigned long)S5P_VA_GPIO2, 76 .virtual = (unsigned long)S5P_VA_GPIO2,
70 .pfn = __phys_to_pfn(S5PV310_PA_GPIO2), 77 .pfn = __phys_to_pfn(EXYNOS4_PA_GPIO2),
71 .length = SZ_4K, 78 .length = SZ_4K,
72 .type = MT_DEVICE, 79 .type = MT_DEVICE,
73 }, { 80 }, {
74 .virtual = (unsigned long)S5P_VA_GPIO3, 81 .virtual = (unsigned long)S5P_VA_GPIO3,
75 .pfn = __phys_to_pfn(S5PV310_PA_GPIO3), 82 .pfn = __phys_to_pfn(EXYNOS4_PA_GPIO3),
76 .length = SZ_256, 83 .length = SZ_256,
77 .type = MT_DEVICE, 84 .type = MT_DEVICE,
78 }, { 85 }, {
79 .virtual = (unsigned long)S5P_VA_DMC0, 86 .virtual = (unsigned long)S5P_VA_DMC0,
80 .pfn = __phys_to_pfn(S5PV310_PA_DMC0), 87 .pfn = __phys_to_pfn(EXYNOS4_PA_DMC0),
81 .length = SZ_4K, 88 .length = SZ_4K,
82 .type = MT_DEVICE, 89 .type = MT_DEVICE,
83 }, { 90 }, {
@@ -87,13 +94,13 @@ static struct map_desc s5pv310_iodesc[] __initdata = {
87 .type = MT_DEVICE, 94 .type = MT_DEVICE,
88 }, { 95 }, {
89 .virtual = (unsigned long)S5P_VA_SROMC, 96 .virtual = (unsigned long)S5P_VA_SROMC,
90 .pfn = __phys_to_pfn(S5PV310_PA_SROMC), 97 .pfn = __phys_to_pfn(EXYNOS4_PA_SROMC),
91 .length = SZ_4K, 98 .length = SZ_4K,
92 .type = MT_DEVICE, 99 .type = MT_DEVICE,
93 }, 100 },
94}; 101};
95 102
96static void s5pv310_idle(void) 103static void exynos4_idle(void)
97{ 104{
98 if (!need_resched()) 105 if (!need_resched())
99 cpu_do_idle(); 106 cpu_do_idle();
@@ -101,32 +108,38 @@ static void s5pv310_idle(void)
101 local_irq_enable(); 108 local_irq_enable();
102} 109}
103 110
104/* s5pv310_map_io 111/*
112 * exynos4_map_io
105 * 113 *
106 * register the standard cpu IO areas 114 * register the standard cpu IO areas
107*/ 115 */
108void __init s5pv310_map_io(void) 116void __init exynos4_map_io(void)
109{ 117{
110 iotable_init(s5pv310_iodesc, ARRAY_SIZE(s5pv310_iodesc)); 118 iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
111 119
112 /* initialize device information early */ 120 /* initialize device information early */
113 s5pv310_default_sdhci0(); 121 exynos4_default_sdhci0();
114 s5pv310_default_sdhci1(); 122 exynos4_default_sdhci1();
115 s5pv310_default_sdhci2(); 123 exynos4_default_sdhci2();
116 s5pv310_default_sdhci3(); 124 exynos4_default_sdhci3();
125
126 s3c_fimc_setname(0, "exynos4-fimc");
127 s3c_fimc_setname(1, "exynos4-fimc");
128 s3c_fimc_setname(2, "exynos4-fimc");
129 s3c_fimc_setname(3, "exynos4-fimc");
117} 130}
118 131
119void __init s5pv310_init_clocks(int xtal) 132void __init exynos4_init_clocks(int xtal)
120{ 133{
121 printk(KERN_DEBUG "%s: initializing clocks\n", __func__); 134 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
122 135
123 s3c24xx_register_baseclocks(xtal); 136 s3c24xx_register_baseclocks(xtal);
124 s5p_register_clocks(xtal); 137 s5p_register_clocks(xtal);
125 s5pv310_register_clocks(); 138 exynos4_register_clocks();
126 s5pv310_setup_clocks(); 139 exynos4_setup_clocks();
127} 140}
128 141
129void __init s5pv310_init_irq(void) 142void __init exynos4_init_irq(void)
130{ 143{
131 int irq; 144 int irq;
132 145
@@ -148,29 +161,29 @@ void __init s5pv310_init_irq(void)
148 } 161 }
149 162
150 /* The parameters of s5p_init_irq() are for VIC init. 163 /* The parameters of s5p_init_irq() are for VIC init.
151 * Theses parameters should be NULL and 0 because S5PV310 164 * Theses parameters should be NULL and 0 because EXYNOS4
152 * uses GIC instead of VIC. 165 * uses GIC instead of VIC.
153 */ 166 */
154 s5p_init_irq(NULL, 0); 167 s5p_init_irq(NULL, 0);
155} 168}
156 169
157struct sysdev_class s5pv310_sysclass = { 170struct sysdev_class exynos4_sysclass = {
158 .name = "s5pv310-core", 171 .name = "exynos4-core",
159}; 172};
160 173
161static struct sys_device s5pv310_sysdev = { 174static struct sys_device exynos4_sysdev = {
162 .cls = &s5pv310_sysclass, 175 .cls = &exynos4_sysclass,
163}; 176};
164 177
165static int __init s5pv310_core_init(void) 178static int __init exynos4_core_init(void)
166{ 179{
167 return sysdev_class_register(&s5pv310_sysclass); 180 return sysdev_class_register(&exynos4_sysclass);
168} 181}
169 182
170core_initcall(s5pv310_core_init); 183core_initcall(exynos4_core_init);
171 184
172#ifdef CONFIG_CACHE_L2X0 185#ifdef CONFIG_CACHE_L2X0
173static int __init s5pv310_l2x0_cache_init(void) 186static int __init exynos4_l2x0_cache_init(void)
174{ 187{
175 /* TAG, Data Latency Control: 2cycle */ 188 /* TAG, Data Latency Control: 2cycle */
176 __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL); 189 __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
@@ -188,15 +201,15 @@ static int __init s5pv310_l2x0_cache_init(void)
188 return 0; 201 return 0;
189} 202}
190 203
191early_initcall(s5pv310_l2x0_cache_init); 204early_initcall(exynos4_l2x0_cache_init);
192#endif 205#endif
193 206
194int __init s5pv310_init(void) 207int __init exynos4_init(void)
195{ 208{
196 printk(KERN_INFO "S5PV310: Initializing architecture\n"); 209 printk(KERN_INFO "EXYNOS4: Initializing architecture\n");
197 210
198 /* set idle function */ 211 /* set idle function */
199 pm_idle = s5pv310_idle; 212 pm_idle = exynos4_idle;
200 213
201 return sysdev_register(&s5pv310_sysdev); 214 return sysdev_register(&exynos4_sysdev);
202} 215}
diff --git a/arch/arm/mach-s5pv310/cpufreq.c b/arch/arm/mach-exynos4/cpufreq.c
index 7c08ad7d8887..a1bd258f0c4d 100644
--- a/arch/arm/mach-s5pv310/cpufreq.c
+++ b/arch/arm/mach-exynos4/cpufreq.c
@@ -1,9 +1,9 @@
1/* linux/arch/arm/mach-s5pv310/cpufreq.c 1/* linux/arch/arm/mach-exynos4/cpufreq.c
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com 4 * http://www.samsung.com
5 * 5 *
6 * S5PV310 - CPU frequency scaling support 6 * EXYNOS4 - CPU frequency scaling support
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
@@ -31,15 +31,13 @@ static struct clk *moutcore;
31static struct clk *mout_mpll; 31static struct clk *mout_mpll;
32static struct clk *mout_apll; 32static struct clk *mout_apll;
33 33
34#ifdef CONFIG_REGULATOR
35static struct regulator *arm_regulator; 34static struct regulator *arm_regulator;
36static struct regulator *int_regulator; 35static struct regulator *int_regulator;
37#endif
38 36
39static struct cpufreq_freqs freqs; 37static struct cpufreq_freqs freqs;
40static unsigned int memtype; 38static unsigned int memtype;
41 39
42enum s5pv310_memory_type { 40enum exynos4_memory_type {
43 DDR2 = 4, 41 DDR2 = 4,
44 LPDDR2, 42 LPDDR2,
45 DDR3, 43 DDR3,
@@ -49,7 +47,7 @@ enum cpufreq_level_index {
49 L0, L1, L2, L3, CPUFREQ_LEVEL_END, 47 L0, L1, L2, L3, CPUFREQ_LEVEL_END,
50}; 48};
51 49
52static struct cpufreq_frequency_table s5pv310_freq_table[] = { 50static struct cpufreq_frequency_table exynos4_freq_table[] = {
53 {L0, 1000*1000}, 51 {L0, 1000*1000},
54 {L1, 800*1000}, 52 {L1, 800*1000},
55 {L2, 400*1000}, 53 {L2, 400*1000},
@@ -160,7 +158,7 @@ struct cpufreq_voltage_table {
160 unsigned int int_volt; 158 unsigned int int_volt;
161}; 159};
162 160
163static struct cpufreq_voltage_table s5pv310_volt_table[CPUFREQ_LEVEL_END] = { 161static struct cpufreq_voltage_table exynos4_volt_table[CPUFREQ_LEVEL_END] = {
164 { 162 {
165 .index = L0, 163 .index = L0,
166 .arm_volt = 1200000, 164 .arm_volt = 1200000,
@@ -180,7 +178,7 @@ static struct cpufreq_voltage_table s5pv310_volt_table[CPUFREQ_LEVEL_END] = {
180 }, 178 },
181}; 179};
182 180
183static unsigned int s5pv310_apll_pms_table[CPUFREQ_LEVEL_END] = { 181static unsigned int exynos4_apll_pms_table[CPUFREQ_LEVEL_END] = {
184 /* APLL FOUT L0: 1000MHz */ 182 /* APLL FOUT L0: 1000MHz */
185 ((250 << 16) | (6 << 8) | 1), 183 ((250 << 16) | (6 << 8) | 1),
186 184
@@ -194,17 +192,17 @@ static unsigned int s5pv310_apll_pms_table[CPUFREQ_LEVEL_END] = {
194 ((200 << 16) | (6 << 8) | 4), 192 ((200 << 16) | (6 << 8) | 4),
195}; 193};
196 194
197int s5pv310_verify_speed(struct cpufreq_policy *policy) 195int exynos4_verify_speed(struct cpufreq_policy *policy)
198{ 196{
199 return cpufreq_frequency_table_verify(policy, s5pv310_freq_table); 197 return cpufreq_frequency_table_verify(policy, exynos4_freq_table);
200} 198}
201 199
202unsigned int s5pv310_getspeed(unsigned int cpu) 200unsigned int exynos4_getspeed(unsigned int cpu)
203{ 201{
204 return clk_get_rate(cpu_clk) / 1000; 202 return clk_get_rate(cpu_clk) / 1000;
205} 203}
206 204
207void s5pv310_set_clkdiv(unsigned int div_index) 205void exynos4_set_clkdiv(unsigned int div_index)
208{ 206{
209 unsigned int tmp; 207 unsigned int tmp;
210 208
@@ -321,7 +319,7 @@ void s5pv310_set_clkdiv(unsigned int div_index)
321 } while (tmp & 0x11); 319 } while (tmp & 0x11);
322} 320}
323 321
324static void s5pv310_set_apll(unsigned int index) 322static void exynos4_set_apll(unsigned int index)
325{ 323{
326 unsigned int tmp; 324 unsigned int tmp;
327 325
@@ -340,7 +338,7 @@ static void s5pv310_set_apll(unsigned int index)
340 /* 3. Change PLL PMS values */ 338 /* 3. Change PLL PMS values */
341 tmp = __raw_readl(S5P_APLL_CON0); 339 tmp = __raw_readl(S5P_APLL_CON0);
342 tmp &= ~((0x3ff << 16) | (0x3f << 8) | (0x7 << 0)); 340 tmp &= ~((0x3ff << 16) | (0x3f << 8) | (0x7 << 0));
343 tmp |= s5pv310_apll_pms_table[index]; 341 tmp |= exynos4_apll_pms_table[index];
344 __raw_writel(tmp, S5P_APLL_CON0); 342 __raw_writel(tmp, S5P_APLL_CON0);
345 343
346 /* 4. wait_lock_time */ 344 /* 4. wait_lock_time */
@@ -357,99 +355,95 @@ static void s5pv310_set_apll(unsigned int index)
357 } while (tmp != (0x1 << S5P_CLKSRC_CPU_MUXCORE_SHIFT)); 355 } while (tmp != (0x1 << S5P_CLKSRC_CPU_MUXCORE_SHIFT));
358} 356}
359 357
360static void s5pv310_set_frequency(unsigned int old_index, unsigned int new_index) 358static void exynos4_set_frequency(unsigned int old_index, unsigned int new_index)
361{ 359{
362 unsigned int tmp; 360 unsigned int tmp;
363 361
364 if (old_index > new_index) { 362 if (old_index > new_index) {
365 /* The frequency changing to L0 needs to change apll */ 363 /* The frequency changing to L0 needs to change apll */
366 if (freqs.new == s5pv310_freq_table[L0].frequency) { 364 if (freqs.new == exynos4_freq_table[L0].frequency) {
367 /* 1. Change the system clock divider values */ 365 /* 1. Change the system clock divider values */
368 s5pv310_set_clkdiv(new_index); 366 exynos4_set_clkdiv(new_index);
369 367
370 /* 2. Change the apll m,p,s value */ 368 /* 2. Change the apll m,p,s value */
371 s5pv310_set_apll(new_index); 369 exynos4_set_apll(new_index);
372 } else { 370 } else {
373 /* 1. Change the system clock divider values */ 371 /* 1. Change the system clock divider values */
374 s5pv310_set_clkdiv(new_index); 372 exynos4_set_clkdiv(new_index);
375 373
376 /* 2. Change just s value in apll m,p,s value */ 374 /* 2. Change just s value in apll m,p,s value */
377 tmp = __raw_readl(S5P_APLL_CON0); 375 tmp = __raw_readl(S5P_APLL_CON0);
378 tmp &= ~(0x7 << 0); 376 tmp &= ~(0x7 << 0);
379 tmp |= (s5pv310_apll_pms_table[new_index] & 0x7); 377 tmp |= (exynos4_apll_pms_table[new_index] & 0x7);
380 __raw_writel(tmp, S5P_APLL_CON0); 378 __raw_writel(tmp, S5P_APLL_CON0);
381 } 379 }
382 } 380 }
383 381
384 else if (old_index < new_index) { 382 else if (old_index < new_index) {
385 /* The frequency changing from L0 needs to change apll */ 383 /* The frequency changing from L0 needs to change apll */
386 if (freqs.old == s5pv310_freq_table[L0].frequency) { 384 if (freqs.old == exynos4_freq_table[L0].frequency) {
387 /* 1. Change the apll m,p,s value */ 385 /* 1. Change the apll m,p,s value */
388 s5pv310_set_apll(new_index); 386 exynos4_set_apll(new_index);
389 387
390 /* 2. Change the system clock divider values */ 388 /* 2. Change the system clock divider values */
391 s5pv310_set_clkdiv(new_index); 389 exynos4_set_clkdiv(new_index);
392 } else { 390 } else {
393 /* 1. Change just s value in apll m,p,s value */ 391 /* 1. Change just s value in apll m,p,s value */
394 tmp = __raw_readl(S5P_APLL_CON0); 392 tmp = __raw_readl(S5P_APLL_CON0);
395 tmp &= ~(0x7 << 0); 393 tmp &= ~(0x7 << 0);
396 tmp |= (s5pv310_apll_pms_table[new_index] & 0x7); 394 tmp |= (exynos4_apll_pms_table[new_index] & 0x7);
397 __raw_writel(tmp, S5P_APLL_CON0); 395 __raw_writel(tmp, S5P_APLL_CON0);
398 396
399 /* 2. Change the system clock divider values */ 397 /* 2. Change the system clock divider values */
400 s5pv310_set_clkdiv(new_index); 398 exynos4_set_clkdiv(new_index);
401 } 399 }
402 } 400 }
403} 401}
404 402
405static int s5pv310_target(struct cpufreq_policy *policy, 403static int exynos4_target(struct cpufreq_policy *policy,
406 unsigned int target_freq, 404 unsigned int target_freq,
407 unsigned int relation) 405 unsigned int relation)
408{ 406{
409 unsigned int index, old_index; 407 unsigned int index, old_index;
410 unsigned int arm_volt, int_volt; 408 unsigned int arm_volt, int_volt;
411 409
412 freqs.old = s5pv310_getspeed(policy->cpu); 410 freqs.old = exynos4_getspeed(policy->cpu);
413 411
414 if (cpufreq_frequency_table_target(policy, s5pv310_freq_table, 412 if (cpufreq_frequency_table_target(policy, exynos4_freq_table,
415 freqs.old, relation, &old_index)) 413 freqs.old, relation, &old_index))
416 return -EINVAL; 414 return -EINVAL;
417 415
418 if (cpufreq_frequency_table_target(policy, s5pv310_freq_table, 416 if (cpufreq_frequency_table_target(policy, exynos4_freq_table,
419 target_freq, relation, &index)) 417 target_freq, relation, &index))
420 return -EINVAL; 418 return -EINVAL;
421 419
422 freqs.new = s5pv310_freq_table[index].frequency; 420 freqs.new = exynos4_freq_table[index].frequency;
423 freqs.cpu = policy->cpu; 421 freqs.cpu = policy->cpu;
424 422
425 if (freqs.new == freqs.old) 423 if (freqs.new == freqs.old)
426 return 0; 424 return 0;
427 425
428 /* get the voltage value */ 426 /* get the voltage value */
429 arm_volt = s5pv310_volt_table[index].arm_volt; 427 arm_volt = exynos4_volt_table[index].arm_volt;
430 int_volt = s5pv310_volt_table[index].int_volt; 428 int_volt = exynos4_volt_table[index].int_volt;
431 429
432 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); 430 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
433 431
434 /* control regulator */ 432 /* control regulator */
435 if (freqs.new > freqs.old) { 433 if (freqs.new > freqs.old) {
436 /* Voltage up */ 434 /* Voltage up */
437#ifdef CONFIG_REGULATOR
438 regulator_set_voltage(arm_regulator, arm_volt, arm_volt); 435 regulator_set_voltage(arm_regulator, arm_volt, arm_volt);
439 regulator_set_voltage(int_regulator, int_volt, int_volt); 436 regulator_set_voltage(int_regulator, int_volt, int_volt);
440#endif
441 } 437 }
442 438
443 /* Clock Configuration Procedure */ 439 /* Clock Configuration Procedure */
444 s5pv310_set_frequency(old_index, index); 440 exynos4_set_frequency(old_index, index);
445 441
446 /* control regulator */ 442 /* control regulator */
447 if (freqs.new < freqs.old) { 443 if (freqs.new < freqs.old) {
448 /* Voltage down */ 444 /* Voltage down */
449#ifdef CONFIG_REGULATOR
450 regulator_set_voltage(arm_regulator, arm_volt, arm_volt); 445 regulator_set_voltage(arm_regulator, arm_volt, arm_volt);
451 regulator_set_voltage(int_regulator, int_volt, int_volt); 446 regulator_set_voltage(int_regulator, int_volt, int_volt);
452#endif
453 } 447 }
454 448
455 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); 449 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
@@ -458,51 +452,51 @@ static int s5pv310_target(struct cpufreq_policy *policy,
458} 452}
459 453
460#ifdef CONFIG_PM 454#ifdef CONFIG_PM
461static int s5pv310_cpufreq_suspend(struct cpufreq_policy *policy) 455static int exynos4_cpufreq_suspend(struct cpufreq_policy *policy)
462{ 456{
463 return 0; 457 return 0;
464} 458}
465 459
466static int s5pv310_cpufreq_resume(struct cpufreq_policy *policy) 460static int exynos4_cpufreq_resume(struct cpufreq_policy *policy)
467{ 461{
468 return 0; 462 return 0;
469} 463}
470#endif 464#endif
471 465
472static int s5pv310_cpufreq_cpu_init(struct cpufreq_policy *policy) 466static int exynos4_cpufreq_cpu_init(struct cpufreq_policy *policy)
473{ 467{
474 policy->cur = policy->min = policy->max = s5pv310_getspeed(policy->cpu); 468 policy->cur = policy->min = policy->max = exynos4_getspeed(policy->cpu);
475 469
476 cpufreq_frequency_table_get_attr(s5pv310_freq_table, policy->cpu); 470 cpufreq_frequency_table_get_attr(exynos4_freq_table, policy->cpu);
477 471
478 /* set the transition latency value */ 472 /* set the transition latency value */
479 policy->cpuinfo.transition_latency = 100000; 473 policy->cpuinfo.transition_latency = 100000;
480 474
481 /* 475 /*
482 * S5PV310 multi-core processors has 2 cores 476 * EXYNOS4 multi-core processors has 2 cores
483 * that the frequency cannot be set independently. 477 * that the frequency cannot be set independently.
484 * Each cpu is bound to the same speed. 478 * Each cpu is bound to the same speed.
485 * So the affected cpu is all of the cpus. 479 * So the affected cpu is all of the cpus.
486 */ 480 */
487 cpumask_setall(policy->cpus); 481 cpumask_setall(policy->cpus);
488 482
489 return cpufreq_frequency_table_cpuinfo(policy, s5pv310_freq_table); 483 return cpufreq_frequency_table_cpuinfo(policy, exynos4_freq_table);
490} 484}
491 485
492static struct cpufreq_driver s5pv310_driver = { 486static struct cpufreq_driver exynos4_driver = {
493 .flags = CPUFREQ_STICKY, 487 .flags = CPUFREQ_STICKY,
494 .verify = s5pv310_verify_speed, 488 .verify = exynos4_verify_speed,
495 .target = s5pv310_target, 489 .target = exynos4_target,
496 .get = s5pv310_getspeed, 490 .get = exynos4_getspeed,
497 .init = s5pv310_cpufreq_cpu_init, 491 .init = exynos4_cpufreq_cpu_init,
498 .name = "s5pv310_cpufreq", 492 .name = "exynos4_cpufreq",
499#ifdef CONFIG_PM 493#ifdef CONFIG_PM
500 .suspend = s5pv310_cpufreq_suspend, 494 .suspend = exynos4_cpufreq_suspend,
501 .resume = s5pv310_cpufreq_resume, 495 .resume = exynos4_cpufreq_resume,
502#endif 496#endif
503}; 497};
504 498
505static int __init s5pv310_cpufreq_init(void) 499static int __init exynos4_cpufreq_init(void)
506{ 500{
507 cpu_clk = clk_get(NULL, "armclk"); 501 cpu_clk = clk_get(NULL, "armclk");
508 if (IS_ERR(cpu_clk)) 502 if (IS_ERR(cpu_clk))
@@ -520,7 +514,6 @@ static int __init s5pv310_cpufreq_init(void)
520 if (IS_ERR(mout_apll)) 514 if (IS_ERR(mout_apll))
521 goto out; 515 goto out;
522 516
523#ifdef CONFIG_REGULATOR
524 arm_regulator = regulator_get(NULL, "vdd_arm"); 517 arm_regulator = regulator_get(NULL, "vdd_arm");
525 if (IS_ERR(arm_regulator)) { 518 if (IS_ERR(arm_regulator)) {
526 printk(KERN_ERR "failed to get resource %s\n", "vdd_arm"); 519 printk(KERN_ERR "failed to get resource %s\n", "vdd_arm");
@@ -532,7 +525,6 @@ static int __init s5pv310_cpufreq_init(void)
532 printk(KERN_ERR "failed to get resource %s\n", "vdd_int"); 525 printk(KERN_ERR "failed to get resource %s\n", "vdd_int");
533 goto out; 526 goto out;
534 } 527 }
535#endif
536 528
537 /* 529 /*
538 * Check DRAM type. 530 * Check DRAM type.
@@ -549,7 +541,7 @@ static int __init s5pv310_cpufreq_init(void)
549 printk(KERN_DEBUG "%s: memtype= 0x%x\n", __func__, memtype); 541 printk(KERN_DEBUG "%s: memtype= 0x%x\n", __func__, memtype);
550 } 542 }
551 543
552 return cpufreq_register_driver(&s5pv310_driver); 544 return cpufreq_register_driver(&exynos4_driver);
553 545
554out: 546out:
555 if (!IS_ERR(cpu_clk)) 547 if (!IS_ERR(cpu_clk))
@@ -564,16 +556,14 @@ out:
564 if (!IS_ERR(mout_apll)) 556 if (!IS_ERR(mout_apll))
565 clk_put(mout_apll); 557 clk_put(mout_apll);
566 558
567#ifdef CONFIG_REGULATOR
568 if (!IS_ERR(arm_regulator)) 559 if (!IS_ERR(arm_regulator))
569 regulator_put(arm_regulator); 560 regulator_put(arm_regulator);
570 561
571 if (!IS_ERR(int_regulator)) 562 if (!IS_ERR(int_regulator))
572 regulator_put(int_regulator); 563 regulator_put(int_regulator);
573#endif
574 564
575 printk(KERN_ERR "%s: failed initialization\n", __func__); 565 printk(KERN_ERR "%s: failed initialization\n", __func__);
576 566
577 return -EINVAL; 567 return -EINVAL;
578} 568}
579late_initcall(s5pv310_cpufreq_init); 569late_initcall(exynos4_cpufreq_init);
diff --git a/arch/arm/mach-exynos4/dev-ahci.c b/arch/arm/mach-exynos4/dev-ahci.c
new file mode 100644
index 000000000000..f57a3de8e1d2
--- /dev/null
+++ b/arch/arm/mach-exynos4/dev-ahci.c
@@ -0,0 +1,263 @@
1/* linux/arch/arm/mach-exynos4/dev-ahci.c
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS4 - AHCI support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/clk.h>
14#include <linux/delay.h>
15#include <linux/dma-mapping.h>
16#include <linux/platform_device.h>
17#include <linux/ahci_platform.h>
18
19#include <plat/cpu.h>
20
21#include <mach/irqs.h>
22#include <mach/map.h>
23#include <mach/regs-pmu.h>
24
25/* PHY Control Register */
26#define SATA_CTRL0 0x0
27/* PHY Link Control Register */
28#define SATA_CTRL1 0x4
29/* PHY Status Register */
30#define SATA_PHY_STATUS 0x8
31
32#define SATA_CTRL0_RX_DATA_VALID(x) (x << 27)
33#define SATA_CTRL0_SPEED_MODE (1 << 26)
34#define SATA_CTRL0_M_PHY_CAL (1 << 19)
35#define SATA_CTRL0_PHY_CMU_RST_N (1 << 10)
36#define SATA_CTRL0_M_PHY_LN_RST_N (1 << 9)
37#define SATA_CTRL0_PHY_POR_N (1 << 8)
38
39#define SATA_CTRL1_RST_PMALIVE_N (1 << 8)
40#define SATA_CTRL1_RST_RXOOB_N (1 << 7)
41#define SATA_CTRL1_RST_RX_N (1 << 6)
42#define SATA_CTRL1_RST_TX_N (1 << 5)
43
44#define SATA_PHY_STATUS_CMU_OK (1 << 18)
45#define SATA_PHY_STATUS_LANE_OK (1 << 16)
46
47#define LANE0 0x200
48#define COM_LANE 0xA00
49
50#define HOST_PORTS_IMPL 0xC
51#define SCLK_SATA_FREQ (67 * MHZ)
52
53static void __iomem *phy_base, *phy_ctrl;
54
55struct phy_reg {
56 u8 reg;
57 u8 val;
58};
59
60/* SATA PHY setup */
61static const struct phy_reg exynos4_sataphy_cmu[] = {
62 { 0x00, 0x06 }, { 0x02, 0x80 }, { 0x22, 0xa0 }, { 0x23, 0x42 },
63 { 0x2e, 0x04 }, { 0x2f, 0x50 }, { 0x30, 0x70 }, { 0x31, 0x02 },
64 { 0x32, 0x25 }, { 0x33, 0x40 }, { 0x34, 0x01 }, { 0x35, 0x40 },
65 { 0x61, 0x2e }, { 0x63, 0x5e }, { 0x65, 0x42 }, { 0x66, 0xd1 },
66 { 0x67, 0x20 }, { 0x68, 0x28 }, { 0x69, 0x78 }, { 0x6a, 0x04 },
67 { 0x6b, 0xc8 }, { 0x6c, 0x06 },
68};
69
70static const struct phy_reg exynos4_sataphy_lane[] = {
71 { 0x00, 0x02 }, { 0x05, 0x10 }, { 0x06, 0x84 }, { 0x07, 0x04 },
72 { 0x08, 0xe0 }, { 0x10, 0x23 }, { 0x13, 0x05 }, { 0x14, 0x30 },
73 { 0x15, 0x00 }, { 0x17, 0x70 }, { 0x18, 0xf2 }, { 0x19, 0x1e },
74 { 0x1a, 0x18 }, { 0x1b, 0x0d }, { 0x1c, 0x08 }, { 0x50, 0x60 },
75 { 0x51, 0x0f },
76};
77
78static const struct phy_reg exynos4_sataphy_comlane[] = {
79 { 0x01, 0x20 }, { 0x03, 0x40 }, { 0x04, 0x3c }, { 0x05, 0x7d },
80 { 0x06, 0x1d }, { 0x07, 0xcf }, { 0x08, 0x05 }, { 0x09, 0x63 },
81 { 0x0a, 0x29 }, { 0x0b, 0xc4 }, { 0x0c, 0x01 }, { 0x0d, 0x03 },
82 { 0x0e, 0x28 }, { 0x0f, 0x98 }, { 0x10, 0x19 }, { 0x13, 0x80 },
83 { 0x14, 0xf0 }, { 0x15, 0xd0 }, { 0x39, 0xa0 }, { 0x3a, 0xa0 },
84 { 0x3b, 0xa0 }, { 0x3c, 0xa0 }, { 0x3d, 0xa0 }, { 0x3e, 0xa0 },
85 { 0x3f, 0xa0 }, { 0x40, 0x42 }, { 0x42, 0x80 }, { 0x43, 0x58 },
86 { 0x45, 0x44 }, { 0x46, 0x5c }, { 0x47, 0x86 }, { 0x48, 0x8d },
87 { 0x49, 0xd0 }, { 0x4a, 0x09 }, { 0x4b, 0x90 }, { 0x4c, 0x07 },
88 { 0x4d, 0x40 }, { 0x51, 0x20 }, { 0x52, 0x32 }, { 0x7f, 0xd8 },
89 { 0x80, 0x1a }, { 0x81, 0xff }, { 0x82, 0x11 }, { 0x83, 0x00 },
90 { 0x87, 0xf0 }, { 0x87, 0xff }, { 0x87, 0xff }, { 0x87, 0xff },
91 { 0x87, 0xff }, { 0x8c, 0x1c }, { 0x8d, 0xc2 }, { 0x8e, 0xc3 },
92 { 0x8f, 0x3f }, { 0x90, 0x0a }, { 0x96, 0xf8 },
93};
94
95static int wait_for_phy_ready(void __iomem *reg, unsigned long bit)
96{
97 unsigned long timeout;
98
99 /* wait for maximum of 3 sec */
100 timeout = jiffies + msecs_to_jiffies(3000);
101 while (!(__raw_readl(reg) & bit)) {
102 if (time_after(jiffies, timeout))
103 return -1;
104 cpu_relax();
105 }
106 return 0;
107}
108
109static int ahci_phy_init(void __iomem *mmio)
110{
111 int i, ctrl0;
112
113 for (i = 0; i < ARRAY_SIZE(exynos4_sataphy_cmu); i++)
114 __raw_writeb(exynos4_sataphy_cmu[i].val,
115 phy_base + (exynos4_sataphy_cmu[i].reg * 4));
116
117 for (i = 0; i < ARRAY_SIZE(exynos4_sataphy_lane); i++)
118 __raw_writeb(exynos4_sataphy_lane[i].val,
119 phy_base + (LANE0 + exynos4_sataphy_lane[i].reg) * 4);
120
121 for (i = 0; i < ARRAY_SIZE(exynos4_sataphy_comlane); i++)
122 __raw_writeb(exynos4_sataphy_comlane[i].val,
123 phy_base + (COM_LANE + exynos4_sataphy_comlane[i].reg) * 4);
124
125 __raw_writeb(0x07, phy_base);
126
127 ctrl0 = __raw_readl(phy_ctrl + SATA_CTRL0);
128 ctrl0 |= SATA_CTRL0_PHY_CMU_RST_N;
129 __raw_writel(ctrl0, phy_ctrl + SATA_CTRL0);
130
131 if (wait_for_phy_ready(phy_ctrl + SATA_PHY_STATUS,
132 SATA_PHY_STATUS_CMU_OK) < 0) {
133 printk(KERN_ERR "PHY CMU not ready\n");
134 return -EBUSY;
135 }
136
137 __raw_writeb(0x03, phy_base + (COM_LANE * 4));
138
139 ctrl0 = __raw_readl(phy_ctrl + SATA_CTRL0);
140 ctrl0 |= SATA_CTRL0_M_PHY_LN_RST_N;
141 __raw_writel(ctrl0, phy_ctrl + SATA_CTRL0);
142
143 if (wait_for_phy_ready(phy_ctrl + SATA_PHY_STATUS,
144 SATA_PHY_STATUS_LANE_OK) < 0) {
145 printk(KERN_ERR "PHY LANE not ready\n");
146 return -EBUSY;
147 }
148
149 ctrl0 = __raw_readl(phy_ctrl + SATA_CTRL0);
150 ctrl0 |= SATA_CTRL0_M_PHY_CAL;
151 __raw_writel(ctrl0, phy_ctrl + SATA_CTRL0);
152
153 return 0;
154}
155
156static int exynos4_ahci_init(struct device *dev, void __iomem *mmio)
157{
158 struct clk *clk_sata, *clk_sataphy, *clk_sclk_sata;
159 int val, ret;
160
161 phy_base = ioremap(EXYNOS4_PA_SATAPHY, SZ_64K);
162 if (!phy_base) {
163 dev_err(dev, "failed to allocate memory for SATA PHY\n");
164 return -ENOMEM;
165 }
166
167 phy_ctrl = ioremap(EXYNOS4_PA_SATAPHY_CTRL, SZ_16);
168 if (!phy_ctrl) {
169 dev_err(dev, "failed to allocate memory for SATA PHY CTRL\n");
170 ret = -ENOMEM;
171 goto err1;
172 }
173
174 clk_sata = clk_get(dev, "sata");
175 if (IS_ERR(clk_sata)) {
176 dev_err(dev, "failed to get sata clock\n");
177 ret = PTR_ERR(clk_sata);
178 clk_sata = NULL;
179 goto err2;
180
181 }
182 clk_enable(clk_sata);
183
184 clk_sataphy = clk_get(dev, "sataphy");
185 if (IS_ERR(clk_sataphy)) {
186 dev_err(dev, "failed to get sataphy clock\n");
187 ret = PTR_ERR(clk_sataphy);
188 clk_sataphy = NULL;
189 goto err3;
190 }
191 clk_enable(clk_sataphy);
192
193 clk_sclk_sata = clk_get(dev, "sclk_sata");
194 if (IS_ERR(clk_sclk_sata)) {
195 dev_err(dev, "failed to get sclk_sata\n");
196 ret = PTR_ERR(clk_sclk_sata);
197 clk_sclk_sata = NULL;
198 goto err4;
199 }
200 clk_enable(clk_sclk_sata);
201 clk_set_rate(clk_sclk_sata, SCLK_SATA_FREQ);
202
203 __raw_writel(S5P_PMU_SATA_PHY_CONTROL_EN, S5P_PMU_SATA_PHY_CONTROL);
204
205 /* Enable PHY link control */
206 val = SATA_CTRL1_RST_PMALIVE_N | SATA_CTRL1_RST_RXOOB_N |
207 SATA_CTRL1_RST_RX_N | SATA_CTRL1_RST_TX_N;
208 __raw_writel(val, phy_ctrl + SATA_CTRL1);
209
210 /* Set communication speed as 3Gbps and enable PHY power */
211 val = SATA_CTRL0_RX_DATA_VALID(3) | SATA_CTRL0_SPEED_MODE |
212 SATA_CTRL0_PHY_POR_N;
213 __raw_writel(val, phy_ctrl + SATA_CTRL0);
214
215 /* Port0 is available */
216 __raw_writel(0x1, mmio + HOST_PORTS_IMPL);
217
218 return ahci_phy_init(mmio);
219
220err4:
221 clk_disable(clk_sataphy);
222 clk_put(clk_sataphy);
223err3:
224 clk_disable(clk_sata);
225 clk_put(clk_sata);
226err2:
227 iounmap(phy_ctrl);
228err1:
229 iounmap(phy_base);
230
231 return ret;
232}
233
234static struct ahci_platform_data exynos4_ahci_pdata = {
235 .init = exynos4_ahci_init,
236};
237
238static struct resource exynos4_ahci_resource[] = {
239 [0] = {
240 .start = EXYNOS4_PA_SATA,
241 .end = EXYNOS4_PA_SATA + SZ_64K - 1,
242 .flags = IORESOURCE_MEM,
243 },
244 [1] = {
245 .start = IRQ_SATA,
246 .end = IRQ_SATA,
247 .flags = IORESOURCE_IRQ,
248 },
249};
250
251static u64 exynos4_ahci_dmamask = DMA_BIT_MASK(32);
252
253struct platform_device exynos4_device_ahci = {
254 .name = "ahci",
255 .id = -1,
256 .resource = exynos4_ahci_resource,
257 .num_resources = ARRAY_SIZE(exynos4_ahci_resource),
258 .dev = {
259 .platform_data = &exynos4_ahci_pdata,
260 .dma_mask = &exynos4_ahci_dmamask,
261 .coherent_dma_mask = DMA_BIT_MASK(32),
262 },
263};
diff --git a/arch/arm/mach-s5pv310/dev-audio.c b/arch/arm/mach-exynos4/dev-audio.c
index a1964242f0fa..1eed5f9f7bd3 100644
--- a/arch/arm/mach-s5pv310/dev-audio.c
+++ b/arch/arm/mach-exynos4/dev-audio.c
@@ -1,4 +1,7 @@
1/* linux/arch/arm/mach-s5pv310/dev-audio.c 1/* linux/arch/arm/mach-exynos4/dev-audio.c
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
2 * 5 *
3 * Copyright (c) 2010 Samsung Electronics Co. Ltd 6 * Copyright (c) 2010 Samsung Electronics Co. Ltd
4 * Jaswinder Singh <jassi.brar@samsung.com> 7 * Jaswinder Singh <jassi.brar@samsung.com>
@@ -24,18 +27,18 @@ static const char *rclksrc[] = {
24 [1] = "i2sclk", 27 [1] = "i2sclk",
25}; 28};
26 29
27static int s5pv310_cfg_i2s(struct platform_device *pdev) 30static int exynos4_cfg_i2s(struct platform_device *pdev)
28{ 31{
29 /* configure GPIO for i2s port */ 32 /* configure GPIO for i2s port */
30 switch (pdev->id) { 33 switch (pdev->id) {
31 case 0: 34 case 0:
32 s3c_gpio_cfgpin_range(S5PV310_GPZ(0), 7, S3C_GPIO_SFN(2)); 35 s3c_gpio_cfgpin_range(EXYNOS4_GPZ(0), 7, S3C_GPIO_SFN(2));
33 break; 36 break;
34 case 1: 37 case 1:
35 s3c_gpio_cfgpin_range(S5PV310_GPC0(0), 5, S3C_GPIO_SFN(2)); 38 s3c_gpio_cfgpin_range(EXYNOS4_GPC0(0), 5, S3C_GPIO_SFN(2));
36 break; 39 break;
37 case 2: 40 case 2:
38 s3c_gpio_cfgpin_range(S5PV310_GPC1(0), 5, S3C_GPIO_SFN(4)); 41 s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 5, S3C_GPIO_SFN(4));
39 break; 42 break;
40 default: 43 default:
41 printk(KERN_ERR "Invalid Device %d\n", pdev->id); 44 printk(KERN_ERR "Invalid Device %d\n", pdev->id);
@@ -46,7 +49,7 @@ static int s5pv310_cfg_i2s(struct platform_device *pdev)
46} 49}
47 50
48static struct s3c_audio_pdata i2sv5_pdata = { 51static struct s3c_audio_pdata i2sv5_pdata = {
49 .cfg_gpio = s5pv310_cfg_i2s, 52 .cfg_gpio = exynos4_cfg_i2s,
50 .type = { 53 .type = {
51 .i2s = { 54 .i2s = {
52 .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI 55 .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI
@@ -56,10 +59,10 @@ static struct s3c_audio_pdata i2sv5_pdata = {
56 }, 59 },
57}; 60};
58 61
59static struct resource s5pv310_i2s0_resource[] = { 62static struct resource exynos4_i2s0_resource[] = {
60 [0] = { 63 [0] = {
61 .start = S5PV310_PA_I2S0, 64 .start = EXYNOS4_PA_I2S0,
62 .end = S5PV310_PA_I2S0 + 0x100 - 1, 65 .end = EXYNOS4_PA_I2S0 + 0x100 - 1,
63 .flags = IORESOURCE_MEM, 66 .flags = IORESOURCE_MEM,
64 }, 67 },
65 [1] = { 68 [1] = {
@@ -79,11 +82,11 @@ static struct resource s5pv310_i2s0_resource[] = {
79 }, 82 },
80}; 83};
81 84
82struct platform_device s5pv310_device_i2s0 = { 85struct platform_device exynos4_device_i2s0 = {
83 .name = "samsung-i2s", 86 .name = "samsung-i2s",
84 .id = 0, 87 .id = 0,
85 .num_resources = ARRAY_SIZE(s5pv310_i2s0_resource), 88 .num_resources = ARRAY_SIZE(exynos4_i2s0_resource),
86 .resource = s5pv310_i2s0_resource, 89 .resource = exynos4_i2s0_resource,
87 .dev = { 90 .dev = {
88 .platform_data = &i2sv5_pdata, 91 .platform_data = &i2sv5_pdata,
89 }, 92 },
@@ -95,7 +98,7 @@ static const char *rclksrc_v3[] = {
95}; 98};
96 99
97static struct s3c_audio_pdata i2sv3_pdata = { 100static struct s3c_audio_pdata i2sv3_pdata = {
98 .cfg_gpio = s5pv310_cfg_i2s, 101 .cfg_gpio = exynos4_cfg_i2s,
99 .type = { 102 .type = {
100 .i2s = { 103 .i2s = {
101 .quirks = QUIRK_NO_MUXPSR, 104 .quirks = QUIRK_NO_MUXPSR,
@@ -104,10 +107,10 @@ static struct s3c_audio_pdata i2sv3_pdata = {
104 }, 107 },
105}; 108};
106 109
107static struct resource s5pv310_i2s1_resource[] = { 110static struct resource exynos4_i2s1_resource[] = {
108 [0] = { 111 [0] = {
109 .start = S5PV310_PA_I2S1, 112 .start = EXYNOS4_PA_I2S1,
110 .end = S5PV310_PA_I2S1 + 0x100 - 1, 113 .end = EXYNOS4_PA_I2S1 + 0x100 - 1,
111 .flags = IORESOURCE_MEM, 114 .flags = IORESOURCE_MEM,
112 }, 115 },
113 [1] = { 116 [1] = {
@@ -122,20 +125,20 @@ static struct resource s5pv310_i2s1_resource[] = {
122 }, 125 },
123}; 126};
124 127
125struct platform_device s5pv310_device_i2s1 = { 128struct platform_device exynos4_device_i2s1 = {
126 .name = "samsung-i2s", 129 .name = "samsung-i2s",
127 .id = 1, 130 .id = 1,
128 .num_resources = ARRAY_SIZE(s5pv310_i2s1_resource), 131 .num_resources = ARRAY_SIZE(exynos4_i2s1_resource),
129 .resource = s5pv310_i2s1_resource, 132 .resource = exynos4_i2s1_resource,
130 .dev = { 133 .dev = {
131 .platform_data = &i2sv3_pdata, 134 .platform_data = &i2sv3_pdata,
132 }, 135 },
133}; 136};
134 137
135static struct resource s5pv310_i2s2_resource[] = { 138static struct resource exynos4_i2s2_resource[] = {
136 [0] = { 139 [0] = {
137 .start = S5PV310_PA_I2S2, 140 .start = EXYNOS4_PA_I2S2,
138 .end = S5PV310_PA_I2S2 + 0x100 - 1, 141 .end = EXYNOS4_PA_I2S2 + 0x100 - 1,
139 .flags = IORESOURCE_MEM, 142 .flags = IORESOURCE_MEM,
140 }, 143 },
141 [1] = { 144 [1] = {
@@ -150,11 +153,11 @@ static struct resource s5pv310_i2s2_resource[] = {
150 }, 153 },
151}; 154};
152 155
153struct platform_device s5pv310_device_i2s2 = { 156struct platform_device exynos4_device_i2s2 = {
154 .name = "samsung-i2s", 157 .name = "samsung-i2s",
155 .id = 2, 158 .id = 2,
156 .num_resources = ARRAY_SIZE(s5pv310_i2s2_resource), 159 .num_resources = ARRAY_SIZE(exynos4_i2s2_resource),
157 .resource = s5pv310_i2s2_resource, 160 .resource = exynos4_i2s2_resource,
158 .dev = { 161 .dev = {
159 .platform_data = &i2sv3_pdata, 162 .platform_data = &i2sv3_pdata,
160 }, 163 },
@@ -162,17 +165,17 @@ struct platform_device s5pv310_device_i2s2 = {
162 165
163/* PCM Controller platform_devices */ 166/* PCM Controller platform_devices */
164 167
165static int s5pv310_pcm_cfg_gpio(struct platform_device *pdev) 168static int exynos4_pcm_cfg_gpio(struct platform_device *pdev)
166{ 169{
167 switch (pdev->id) { 170 switch (pdev->id) {
168 case 0: 171 case 0:
169 s3c_gpio_cfgpin_range(S5PV310_GPZ(0), 5, S3C_GPIO_SFN(3)); 172 s3c_gpio_cfgpin_range(EXYNOS4_GPZ(0), 5, S3C_GPIO_SFN(3));
170 break; 173 break;
171 case 1: 174 case 1:
172 s3c_gpio_cfgpin_range(S5PV310_GPC0(0), 5, S3C_GPIO_SFN(3)); 175 s3c_gpio_cfgpin_range(EXYNOS4_GPC0(0), 5, S3C_GPIO_SFN(3));
173 break; 176 break;
174 case 2: 177 case 2:
175 s3c_gpio_cfgpin_range(S5PV310_GPC1(0), 5, S3C_GPIO_SFN(3)); 178 s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 5, S3C_GPIO_SFN(3));
176 break; 179 break;
177 default: 180 default:
178 printk(KERN_DEBUG "Invalid PCM Controller number!"); 181 printk(KERN_DEBUG "Invalid PCM Controller number!");
@@ -183,13 +186,13 @@ static int s5pv310_pcm_cfg_gpio(struct platform_device *pdev)
183} 186}
184 187
185static struct s3c_audio_pdata s3c_pcm_pdata = { 188static struct s3c_audio_pdata s3c_pcm_pdata = {
186 .cfg_gpio = s5pv310_pcm_cfg_gpio, 189 .cfg_gpio = exynos4_pcm_cfg_gpio,
187}; 190};
188 191
189static struct resource s5pv310_pcm0_resource[] = { 192static struct resource exynos4_pcm0_resource[] = {
190 [0] = { 193 [0] = {
191 .start = S5PV310_PA_PCM0, 194 .start = EXYNOS4_PA_PCM0,
192 .end = S5PV310_PA_PCM0 + 0x100 - 1, 195 .end = EXYNOS4_PA_PCM0 + 0x100 - 1,
193 .flags = IORESOURCE_MEM, 196 .flags = IORESOURCE_MEM,
194 }, 197 },
195 [1] = { 198 [1] = {
@@ -204,20 +207,20 @@ static struct resource s5pv310_pcm0_resource[] = {
204 }, 207 },
205}; 208};
206 209
207struct platform_device s5pv310_device_pcm0 = { 210struct platform_device exynos4_device_pcm0 = {
208 .name = "samsung-pcm", 211 .name = "samsung-pcm",
209 .id = 0, 212 .id = 0,
210 .num_resources = ARRAY_SIZE(s5pv310_pcm0_resource), 213 .num_resources = ARRAY_SIZE(exynos4_pcm0_resource),
211 .resource = s5pv310_pcm0_resource, 214 .resource = exynos4_pcm0_resource,
212 .dev = { 215 .dev = {
213 .platform_data = &s3c_pcm_pdata, 216 .platform_data = &s3c_pcm_pdata,
214 }, 217 },
215}; 218};
216 219
217static struct resource s5pv310_pcm1_resource[] = { 220static struct resource exynos4_pcm1_resource[] = {
218 [0] = { 221 [0] = {
219 .start = S5PV310_PA_PCM1, 222 .start = EXYNOS4_PA_PCM1,
220 .end = S5PV310_PA_PCM1 + 0x100 - 1, 223 .end = EXYNOS4_PA_PCM1 + 0x100 - 1,
221 .flags = IORESOURCE_MEM, 224 .flags = IORESOURCE_MEM,
222 }, 225 },
223 [1] = { 226 [1] = {
@@ -232,20 +235,20 @@ static struct resource s5pv310_pcm1_resource[] = {
232 }, 235 },
233}; 236};
234 237
235struct platform_device s5pv310_device_pcm1 = { 238struct platform_device exynos4_device_pcm1 = {
236 .name = "samsung-pcm", 239 .name = "samsung-pcm",
237 .id = 1, 240 .id = 1,
238 .num_resources = ARRAY_SIZE(s5pv310_pcm1_resource), 241 .num_resources = ARRAY_SIZE(exynos4_pcm1_resource),
239 .resource = s5pv310_pcm1_resource, 242 .resource = exynos4_pcm1_resource,
240 .dev = { 243 .dev = {
241 .platform_data = &s3c_pcm_pdata, 244 .platform_data = &s3c_pcm_pdata,
242 }, 245 },
243}; 246};
244 247
245static struct resource s5pv310_pcm2_resource[] = { 248static struct resource exynos4_pcm2_resource[] = {
246 [0] = { 249 [0] = {
247 .start = S5PV310_PA_PCM2, 250 .start = EXYNOS4_PA_PCM2,
248 .end = S5PV310_PA_PCM2 + 0x100 - 1, 251 .end = EXYNOS4_PA_PCM2 + 0x100 - 1,
249 .flags = IORESOURCE_MEM, 252 .flags = IORESOURCE_MEM,
250 }, 253 },
251 [1] = { 254 [1] = {
@@ -260,11 +263,11 @@ static struct resource s5pv310_pcm2_resource[] = {
260 }, 263 },
261}; 264};
262 265
263struct platform_device s5pv310_device_pcm2 = { 266struct platform_device exynos4_device_pcm2 = {
264 .name = "samsung-pcm", 267 .name = "samsung-pcm",
265 .id = 2, 268 .id = 2,
266 .num_resources = ARRAY_SIZE(s5pv310_pcm2_resource), 269 .num_resources = ARRAY_SIZE(exynos4_pcm2_resource),
267 .resource = s5pv310_pcm2_resource, 270 .resource = exynos4_pcm2_resource,
268 .dev = { 271 .dev = {
269 .platform_data = &s3c_pcm_pdata, 272 .platform_data = &s3c_pcm_pdata,
270 }, 273 },
@@ -272,15 +275,15 @@ struct platform_device s5pv310_device_pcm2 = {
272 275
273/* AC97 Controller platform devices */ 276/* AC97 Controller platform devices */
274 277
275static int s5pv310_ac97_cfg_gpio(struct platform_device *pdev) 278static int exynos4_ac97_cfg_gpio(struct platform_device *pdev)
276{ 279{
277 return s3c_gpio_cfgpin_range(S5PV310_GPC0(0), 5, S3C_GPIO_SFN(4)); 280 return s3c_gpio_cfgpin_range(EXYNOS4_GPC0(0), 5, S3C_GPIO_SFN(4));
278} 281}
279 282
280static struct resource s5pv310_ac97_resource[] = { 283static struct resource exynos4_ac97_resource[] = {
281 [0] = { 284 [0] = {
282 .start = S5PV310_PA_AC97, 285 .start = EXYNOS4_PA_AC97,
283 .end = S5PV310_PA_AC97 + 0x100 - 1, 286 .end = EXYNOS4_PA_AC97 + 0x100 - 1,
284 .flags = IORESOURCE_MEM, 287 .flags = IORESOURCE_MEM,
285 }, 288 },
286 [1] = { 289 [1] = {
@@ -306,36 +309,36 @@ static struct resource s5pv310_ac97_resource[] = {
306}; 309};
307 310
308static struct s3c_audio_pdata s3c_ac97_pdata = { 311static struct s3c_audio_pdata s3c_ac97_pdata = {
309 .cfg_gpio = s5pv310_ac97_cfg_gpio, 312 .cfg_gpio = exynos4_ac97_cfg_gpio,
310}; 313};
311 314
312static u64 s5pv310_ac97_dmamask = DMA_BIT_MASK(32); 315static u64 exynos4_ac97_dmamask = DMA_BIT_MASK(32);
313 316
314struct platform_device s5pv310_device_ac97 = { 317struct platform_device exynos4_device_ac97 = {
315 .name = "samsung-ac97", 318 .name = "samsung-ac97",
316 .id = -1, 319 .id = -1,
317 .num_resources = ARRAY_SIZE(s5pv310_ac97_resource), 320 .num_resources = ARRAY_SIZE(exynos4_ac97_resource),
318 .resource = s5pv310_ac97_resource, 321 .resource = exynos4_ac97_resource,
319 .dev = { 322 .dev = {
320 .platform_data = &s3c_ac97_pdata, 323 .platform_data = &s3c_ac97_pdata,
321 .dma_mask = &s5pv310_ac97_dmamask, 324 .dma_mask = &exynos4_ac97_dmamask,
322 .coherent_dma_mask = DMA_BIT_MASK(32), 325 .coherent_dma_mask = DMA_BIT_MASK(32),
323 }, 326 },
324}; 327};
325 328
326/* S/PDIF Controller platform_device */ 329/* S/PDIF Controller platform_device */
327 330
328static int s5pv310_spdif_cfg_gpio(struct platform_device *pdev) 331static int exynos4_spdif_cfg_gpio(struct platform_device *pdev)
329{ 332{
330 s3c_gpio_cfgpin_range(S5PV310_GPC1(0), 2, S3C_GPIO_SFN(3)); 333 s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 2, S3C_GPIO_SFN(3));
331 334
332 return 0; 335 return 0;
333} 336}
334 337
335static struct resource s5pv310_spdif_resource[] = { 338static struct resource exynos4_spdif_resource[] = {
336 [0] = { 339 [0] = {
337 .start = S5PV310_PA_SPDIF, 340 .start = EXYNOS4_PA_SPDIF,
338 .end = S5PV310_PA_SPDIF + 0x100 - 1, 341 .end = EXYNOS4_PA_SPDIF + 0x100 - 1,
339 .flags = IORESOURCE_MEM, 342 .flags = IORESOURCE_MEM,
340 }, 343 },
341 [1] = { 344 [1] = {
@@ -346,19 +349,19 @@ static struct resource s5pv310_spdif_resource[] = {
346}; 349};
347 350
348static struct s3c_audio_pdata samsung_spdif_pdata = { 351static struct s3c_audio_pdata samsung_spdif_pdata = {
349 .cfg_gpio = s5pv310_spdif_cfg_gpio, 352 .cfg_gpio = exynos4_spdif_cfg_gpio,
350}; 353};
351 354
352static u64 s5pv310_spdif_dmamask = DMA_BIT_MASK(32); 355static u64 exynos4_spdif_dmamask = DMA_BIT_MASK(32);
353 356
354struct platform_device s5pv310_device_spdif = { 357struct platform_device exynos4_device_spdif = {
355 .name = "samsung-spdif", 358 .name = "samsung-spdif",
356 .id = -1, 359 .id = -1,
357 .num_resources = ARRAY_SIZE(s5pv310_spdif_resource), 360 .num_resources = ARRAY_SIZE(exynos4_spdif_resource),
358 .resource = s5pv310_spdif_resource, 361 .resource = exynos4_spdif_resource,
359 .dev = { 362 .dev = {
360 .platform_data = &samsung_spdif_pdata, 363 .platform_data = &samsung_spdif_pdata,
361 .dma_mask = &s5pv310_spdif_dmamask, 364 .dma_mask = &exynos4_spdif_dmamask,
362 .coherent_dma_mask = DMA_BIT_MASK(32), 365 .coherent_dma_mask = DMA_BIT_MASK(32),
363 }, 366 },
364}; 367};
diff --git a/arch/arm/mach-s5pv310/dev-pd.c b/arch/arm/mach-exynos4/dev-pd.c
index 58a50c2d0b67..3273f25d6a75 100644
--- a/arch/arm/mach-s5pv310/dev-pd.c
+++ b/arch/arm/mach-exynos4/dev-pd.c
@@ -1,9 +1,9 @@
1/* linux/arch/arm/mach-s5pv310/dev-pd.c 1/* linux/arch/arm/mach-exynos4/dev-pd.c
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com 4 * http://www.samsung.com
5 * 5 *
6 * S5PV310 - Power Domain support 6 * EXYNOS4 - Power Domain support
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
@@ -19,7 +19,7 @@
19 19
20#include <plat/pd.h> 20#include <plat/pd.h>
21 21
22static int s5pv310_pd_enable(struct device *dev) 22static int exynos4_pd_enable(struct device *dev)
23{ 23{
24 struct samsung_pd_info *pdata = dev->platform_data; 24 struct samsung_pd_info *pdata = dev->platform_data;
25 u32 timeout; 25 u32 timeout;
@@ -42,7 +42,7 @@ static int s5pv310_pd_enable(struct device *dev)
42 return 0; 42 return 0;
43} 43}
44 44
45static int s5pv310_pd_disable(struct device *dev) 45static int exynos4_pd_disable(struct device *dev)
46{ 46{
47 struct samsung_pd_info *pdata = dev->platform_data; 47 struct samsung_pd_info *pdata = dev->platform_data;
48 u32 timeout; 48 u32 timeout;
@@ -64,14 +64,14 @@ static int s5pv310_pd_disable(struct device *dev)
64 return 0; 64 return 0;
65} 65}
66 66
67struct platform_device s5pv310_device_pd[] = { 67struct platform_device exynos4_device_pd[] = {
68 { 68 {
69 .name = "samsung-pd", 69 .name = "samsung-pd",
70 .id = 0, 70 .id = 0,
71 .dev = { 71 .dev = {
72 .platform_data = &(struct samsung_pd_info) { 72 .platform_data = &(struct samsung_pd_info) {
73 .enable = s5pv310_pd_enable, 73 .enable = exynos4_pd_enable,
74 .disable = s5pv310_pd_disable, 74 .disable = exynos4_pd_disable,
75 .base = S5P_PMU_MFC_CONF, 75 .base = S5P_PMU_MFC_CONF,
76 }, 76 },
77 }, 77 },
@@ -80,8 +80,8 @@ struct platform_device s5pv310_device_pd[] = {
80 .id = 1, 80 .id = 1,
81 .dev = { 81 .dev = {
82 .platform_data = &(struct samsung_pd_info) { 82 .platform_data = &(struct samsung_pd_info) {
83 .enable = s5pv310_pd_enable, 83 .enable = exynos4_pd_enable,
84 .disable = s5pv310_pd_disable, 84 .disable = exynos4_pd_disable,
85 .base = S5P_PMU_G3D_CONF, 85 .base = S5P_PMU_G3D_CONF,
86 }, 86 },
87 }, 87 },
@@ -90,8 +90,8 @@ struct platform_device s5pv310_device_pd[] = {
90 .id = 2, 90 .id = 2,
91 .dev = { 91 .dev = {
92 .platform_data = &(struct samsung_pd_info) { 92 .platform_data = &(struct samsung_pd_info) {
93 .enable = s5pv310_pd_enable, 93 .enable = exynos4_pd_enable,
94 .disable = s5pv310_pd_disable, 94 .disable = exynos4_pd_disable,
95 .base = S5P_PMU_LCD0_CONF, 95 .base = S5P_PMU_LCD0_CONF,
96 }, 96 },
97 }, 97 },
@@ -100,8 +100,8 @@ struct platform_device s5pv310_device_pd[] = {
100 .id = 3, 100 .id = 3,
101 .dev = { 101 .dev = {
102 .platform_data = &(struct samsung_pd_info) { 102 .platform_data = &(struct samsung_pd_info) {
103 .enable = s5pv310_pd_enable, 103 .enable = exynos4_pd_enable,
104 .disable = s5pv310_pd_disable, 104 .disable = exynos4_pd_disable,
105 .base = S5P_PMU_LCD1_CONF, 105 .base = S5P_PMU_LCD1_CONF,
106 }, 106 },
107 }, 107 },
@@ -110,8 +110,8 @@ struct platform_device s5pv310_device_pd[] = {
110 .id = 4, 110 .id = 4,
111 .dev = { 111 .dev = {
112 .platform_data = &(struct samsung_pd_info) { 112 .platform_data = &(struct samsung_pd_info) {
113 .enable = s5pv310_pd_enable, 113 .enable = exynos4_pd_enable,
114 .disable = s5pv310_pd_disable, 114 .disable = exynos4_pd_disable,
115 .base = S5P_PMU_TV_CONF, 115 .base = S5P_PMU_TV_CONF,
116 }, 116 },
117 }, 117 },
@@ -120,8 +120,8 @@ struct platform_device s5pv310_device_pd[] = {
120 .id = 5, 120 .id = 5,
121 .dev = { 121 .dev = {
122 .platform_data = &(struct samsung_pd_info) { 122 .platform_data = &(struct samsung_pd_info) {
123 .enable = s5pv310_pd_enable, 123 .enable = exynos4_pd_enable,
124 .disable = s5pv310_pd_disable, 124 .disable = exynos4_pd_disable,
125 .base = S5P_PMU_CAM_CONF, 125 .base = S5P_PMU_CAM_CONF,
126 }, 126 },
127 }, 127 },
@@ -130,8 +130,8 @@ struct platform_device s5pv310_device_pd[] = {
130 .id = 6, 130 .id = 6,
131 .dev = { 131 .dev = {
132 .platform_data = &(struct samsung_pd_info) { 132 .platform_data = &(struct samsung_pd_info) {
133 .enable = s5pv310_pd_enable, 133 .enable = exynos4_pd_enable,
134 .disable = s5pv310_pd_disable, 134 .disable = exynos4_pd_disable,
135 .base = S5P_PMU_GPS_CONF, 135 .base = S5P_PMU_GPS_CONF,
136 }, 136 },
137 }, 137 },
diff --git a/arch/arm/mach-s5pv310/dev-sysmmu.c b/arch/arm/mach-exynos4/dev-sysmmu.c
index e1bb200ac0f0..3b7cae0fe23e 100644
--- a/arch/arm/mach-s5pv310/dev-sysmmu.c
+++ b/arch/arm/mach-exynos4/dev-sysmmu.c
@@ -1,8 +1,10 @@
1/* linux/arch/arm/mach-s5pv310/dev-sysmmu.c 1/* linux/arch/arm/mach-exynos4/dev-sysmmu.c
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com 4 * http://www.samsung.com
5 * 5 *
6 * EXYNOS4 - System MMU support
7 *
6 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation. 10 * published by the Free Software Foundation.
@@ -13,11 +15,33 @@
13 15
14#include <mach/map.h> 16#include <mach/map.h>
15#include <mach/irqs.h> 17#include <mach/irqs.h>
18#include <mach/sysmmu.h>
19#include <plat/s5p-clock.h>
20
21/* These names must be equal to the clock names in mach-exynos4/clock.c */
22const char *sysmmu_ips_name[EXYNOS4_SYSMMU_TOTAL_IPNUM] = {
23 "SYSMMU_MDMA" ,
24 "SYSMMU_SSS" ,
25 "SYSMMU_FIMC0" ,
26 "SYSMMU_FIMC1" ,
27 "SYSMMU_FIMC2" ,
28 "SYSMMU_FIMC3" ,
29 "SYSMMU_JPEG" ,
30 "SYSMMU_FIMD0" ,
31 "SYSMMU_FIMD1" ,
32 "SYSMMU_PCIe" ,
33 "SYSMMU_G2D" ,
34 "SYSMMU_ROTATOR",
35 "SYSMMU_MDMA2" ,
36 "SYSMMU_TV" ,
37 "SYSMMU_MFC_L" ,
38 "SYSMMU_MFC_R" ,
39};
16 40
17static struct resource s5pv310_sysmmu_resource[] = { 41static struct resource exynos4_sysmmu_resource[] = {
18 [0] = { 42 [0] = {
19 .start = S5PV310_PA_SYSMMU_MDMA, 43 .start = EXYNOS4_PA_SYSMMU_MDMA,
20 .end = S5PV310_PA_SYSMMU_MDMA + SZ_64K - 1, 44 .end = EXYNOS4_PA_SYSMMU_MDMA + SZ_64K - 1,
21 .flags = IORESOURCE_MEM, 45 .flags = IORESOURCE_MEM,
22 }, 46 },
23 [1] = { 47 [1] = {
@@ -26,8 +50,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
26 .flags = IORESOURCE_IRQ, 50 .flags = IORESOURCE_IRQ,
27 }, 51 },
28 [2] = { 52 [2] = {
29 .start = S5PV310_PA_SYSMMU_SSS, 53 .start = EXYNOS4_PA_SYSMMU_SSS,
30 .end = S5PV310_PA_SYSMMU_SSS + SZ_64K - 1, 54 .end = EXYNOS4_PA_SYSMMU_SSS + SZ_64K - 1,
31 .flags = IORESOURCE_MEM, 55 .flags = IORESOURCE_MEM,
32 }, 56 },
33 [3] = { 57 [3] = {
@@ -36,8 +60,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
36 .flags = IORESOURCE_IRQ, 60 .flags = IORESOURCE_IRQ,
37 }, 61 },
38 [4] = { 62 [4] = {
39 .start = S5PV310_PA_SYSMMU_FIMC0, 63 .start = EXYNOS4_PA_SYSMMU_FIMC0,
40 .end = S5PV310_PA_SYSMMU_FIMC0 + SZ_64K - 1, 64 .end = EXYNOS4_PA_SYSMMU_FIMC0 + SZ_64K - 1,
41 .flags = IORESOURCE_MEM, 65 .flags = IORESOURCE_MEM,
42 }, 66 },
43 [5] = { 67 [5] = {
@@ -46,8 +70,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
46 .flags = IORESOURCE_IRQ, 70 .flags = IORESOURCE_IRQ,
47 }, 71 },
48 [6] = { 72 [6] = {
49 .start = S5PV310_PA_SYSMMU_FIMC1, 73 .start = EXYNOS4_PA_SYSMMU_FIMC1,
50 .end = S5PV310_PA_SYSMMU_FIMC1 + SZ_64K - 1, 74 .end = EXYNOS4_PA_SYSMMU_FIMC1 + SZ_64K - 1,
51 .flags = IORESOURCE_MEM, 75 .flags = IORESOURCE_MEM,
52 }, 76 },
53 [7] = { 77 [7] = {
@@ -56,8 +80,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
56 .flags = IORESOURCE_IRQ, 80 .flags = IORESOURCE_IRQ,
57 }, 81 },
58 [8] = { 82 [8] = {
59 .start = S5PV310_PA_SYSMMU_FIMC2, 83 .start = EXYNOS4_PA_SYSMMU_FIMC2,
60 .end = S5PV310_PA_SYSMMU_FIMC2 + SZ_64K - 1, 84 .end = EXYNOS4_PA_SYSMMU_FIMC2 + SZ_64K - 1,
61 .flags = IORESOURCE_MEM, 85 .flags = IORESOURCE_MEM,
62 }, 86 },
63 [9] = { 87 [9] = {
@@ -66,8 +90,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
66 .flags = IORESOURCE_IRQ, 90 .flags = IORESOURCE_IRQ,
67 }, 91 },
68 [10] = { 92 [10] = {
69 .start = S5PV310_PA_SYSMMU_FIMC3, 93 .start = EXYNOS4_PA_SYSMMU_FIMC3,
70 .end = S5PV310_PA_SYSMMU_FIMC3 + SZ_64K - 1, 94 .end = EXYNOS4_PA_SYSMMU_FIMC3 + SZ_64K - 1,
71 .flags = IORESOURCE_MEM, 95 .flags = IORESOURCE_MEM,
72 }, 96 },
73 [11] = { 97 [11] = {
@@ -76,8 +100,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
76 .flags = IORESOURCE_IRQ, 100 .flags = IORESOURCE_IRQ,
77 }, 101 },
78 [12] = { 102 [12] = {
79 .start = S5PV310_PA_SYSMMU_JPEG, 103 .start = EXYNOS4_PA_SYSMMU_JPEG,
80 .end = S5PV310_PA_SYSMMU_JPEG + SZ_64K - 1, 104 .end = EXYNOS4_PA_SYSMMU_JPEG + SZ_64K - 1,
81 .flags = IORESOURCE_MEM, 105 .flags = IORESOURCE_MEM,
82 }, 106 },
83 [13] = { 107 [13] = {
@@ -86,8 +110,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
86 .flags = IORESOURCE_IRQ, 110 .flags = IORESOURCE_IRQ,
87 }, 111 },
88 [14] = { 112 [14] = {
89 .start = S5PV310_PA_SYSMMU_FIMD0, 113 .start = EXYNOS4_PA_SYSMMU_FIMD0,
90 .end = S5PV310_PA_SYSMMU_FIMD0 + SZ_64K - 1, 114 .end = EXYNOS4_PA_SYSMMU_FIMD0 + SZ_64K - 1,
91 .flags = IORESOURCE_MEM, 115 .flags = IORESOURCE_MEM,
92 }, 116 },
93 [15] = { 117 [15] = {
@@ -96,8 +120,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
96 .flags = IORESOURCE_IRQ, 120 .flags = IORESOURCE_IRQ,
97 }, 121 },
98 [16] = { 122 [16] = {
99 .start = S5PV310_PA_SYSMMU_FIMD1, 123 .start = EXYNOS4_PA_SYSMMU_FIMD1,
100 .end = S5PV310_PA_SYSMMU_FIMD1 + SZ_64K - 1, 124 .end = EXYNOS4_PA_SYSMMU_FIMD1 + SZ_64K - 1,
101 .flags = IORESOURCE_MEM, 125 .flags = IORESOURCE_MEM,
102 }, 126 },
103 [17] = { 127 [17] = {
@@ -106,8 +130,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
106 .flags = IORESOURCE_IRQ, 130 .flags = IORESOURCE_IRQ,
107 }, 131 },
108 [18] = { 132 [18] = {
109 .start = S5PV310_PA_SYSMMU_PCIe, 133 .start = EXYNOS4_PA_SYSMMU_PCIe,
110 .end = S5PV310_PA_SYSMMU_PCIe + SZ_64K - 1, 134 .end = EXYNOS4_PA_SYSMMU_PCIe + SZ_64K - 1,
111 .flags = IORESOURCE_MEM, 135 .flags = IORESOURCE_MEM,
112 }, 136 },
113 [19] = { 137 [19] = {
@@ -116,8 +140,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
116 .flags = IORESOURCE_IRQ, 140 .flags = IORESOURCE_IRQ,
117 }, 141 },
118 [20] = { 142 [20] = {
119 .start = S5PV310_PA_SYSMMU_G2D, 143 .start = EXYNOS4_PA_SYSMMU_G2D,
120 .end = S5PV310_PA_SYSMMU_G2D + SZ_64K - 1, 144 .end = EXYNOS4_PA_SYSMMU_G2D + SZ_64K - 1,
121 .flags = IORESOURCE_MEM, 145 .flags = IORESOURCE_MEM,
122 }, 146 },
123 [21] = { 147 [21] = {
@@ -126,8 +150,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
126 .flags = IORESOURCE_IRQ, 150 .flags = IORESOURCE_IRQ,
127 }, 151 },
128 [22] = { 152 [22] = {
129 .start = S5PV310_PA_SYSMMU_ROTATOR, 153 .start = EXYNOS4_PA_SYSMMU_ROTATOR,
130 .end = S5PV310_PA_SYSMMU_ROTATOR + SZ_64K - 1, 154 .end = EXYNOS4_PA_SYSMMU_ROTATOR + SZ_64K - 1,
131 .flags = IORESOURCE_MEM, 155 .flags = IORESOURCE_MEM,
132 }, 156 },
133 [23] = { 157 [23] = {
@@ -136,8 +160,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
136 .flags = IORESOURCE_IRQ, 160 .flags = IORESOURCE_IRQ,
137 }, 161 },
138 [24] = { 162 [24] = {
139 .start = S5PV310_PA_SYSMMU_MDMA2, 163 .start = EXYNOS4_PA_SYSMMU_MDMA2,
140 .end = S5PV310_PA_SYSMMU_MDMA2 + SZ_64K - 1, 164 .end = EXYNOS4_PA_SYSMMU_MDMA2 + SZ_64K - 1,
141 .flags = IORESOURCE_MEM, 165 .flags = IORESOURCE_MEM,
142 }, 166 },
143 [25] = { 167 [25] = {
@@ -146,8 +170,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
146 .flags = IORESOURCE_IRQ, 170 .flags = IORESOURCE_IRQ,
147 }, 171 },
148 [26] = { 172 [26] = {
149 .start = S5PV310_PA_SYSMMU_TV, 173 .start = EXYNOS4_PA_SYSMMU_TV,
150 .end = S5PV310_PA_SYSMMU_TV + SZ_64K - 1, 174 .end = EXYNOS4_PA_SYSMMU_TV + SZ_64K - 1,
151 .flags = IORESOURCE_MEM, 175 .flags = IORESOURCE_MEM,
152 }, 176 },
153 [27] = { 177 [27] = {
@@ -156,8 +180,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
156 .flags = IORESOURCE_IRQ, 180 .flags = IORESOURCE_IRQ,
157 }, 181 },
158 [28] = { 182 [28] = {
159 .start = S5PV310_PA_SYSMMU_MFC_L, 183 .start = EXYNOS4_PA_SYSMMU_MFC_L,
160 .end = S5PV310_PA_SYSMMU_MFC_L + SZ_64K - 1, 184 .end = EXYNOS4_PA_SYSMMU_MFC_L + SZ_64K - 1,
161 .flags = IORESOURCE_MEM, 185 .flags = IORESOURCE_MEM,
162 }, 186 },
163 [29] = { 187 [29] = {
@@ -166,8 +190,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
166 .flags = IORESOURCE_IRQ, 190 .flags = IORESOURCE_IRQ,
167 }, 191 },
168 [30] = { 192 [30] = {
169 .start = S5PV310_PA_SYSMMU_MFC_R, 193 .start = EXYNOS4_PA_SYSMMU_MFC_R,
170 .end = S5PV310_PA_SYSMMU_MFC_R + SZ_64K - 1, 194 .end = EXYNOS4_PA_SYSMMU_MFC_R + SZ_64K - 1,
171 .flags = IORESOURCE_MEM, 195 .flags = IORESOURCE_MEM,
172 }, 196 },
173 [31] = { 197 [31] = {
@@ -177,11 +201,32 @@ static struct resource s5pv310_sysmmu_resource[] = {
177 }, 201 },
178}; 202};
179 203
180struct platform_device s5pv310_device_sysmmu = { 204struct platform_device exynos4_device_sysmmu = {
181 .name = "s5p-sysmmu", 205 .name = "s5p-sysmmu",
182 .id = 32, 206 .id = 32,
183 .num_resources = ARRAY_SIZE(s5pv310_sysmmu_resource), 207 .num_resources = ARRAY_SIZE(exynos4_sysmmu_resource),
184 .resource = s5pv310_sysmmu_resource, 208 .resource = exynos4_sysmmu_resource,
185}; 209};
210EXPORT_SYMBOL(exynos4_device_sysmmu);
211
212static struct clk *sysmmu_clk[S5P_SYSMMU_TOTAL_IPNUM];
213void sysmmu_clk_init(struct device *dev, sysmmu_ips ips)
214{
215 sysmmu_clk[ips] = clk_get(dev, sysmmu_ips_name[ips]);
216 if (IS_ERR(sysmmu_clk[ips]))
217 sysmmu_clk[ips] = NULL;
218 else
219 clk_put(sysmmu_clk[ips]);
220}
221
222void sysmmu_clk_enable(sysmmu_ips ips)
223{
224 if (sysmmu_clk[ips])
225 clk_enable(sysmmu_clk[ips]);
226}
186 227
187EXPORT_SYMBOL(s5pv310_device_sysmmu); 228void sysmmu_clk_disable(sysmmu_ips ips)
229{
230 if (sysmmu_clk[ips])
231 clk_disable(sysmmu_clk[ips]);
232}
diff --git a/arch/arm/mach-s5pv310/dma.c b/arch/arm/mach-exynos4/dma.c
index 20066c7c9e56..564bb530f332 100644
--- a/arch/arm/mach-s5pv310/dma.c
+++ b/arch/arm/mach-exynos4/dma.c
@@ -1,4 +1,8 @@
1/* 1/* linux/arch/arm/mach-exynos4/dma.c
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
2 * Copyright (C) 2010 Samsung Electronics Co. Ltd. 6 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
3 * Jaswinder Singh <jassi.brar@samsung.com> 7 * Jaswinder Singh <jassi.brar@samsung.com>
4 * 8 *
@@ -30,10 +34,10 @@
30 34
31static u64 dma_dmamask = DMA_BIT_MASK(32); 35static u64 dma_dmamask = DMA_BIT_MASK(32);
32 36
33static struct resource s5pv310_pdma0_resource[] = { 37static struct resource exynos4_pdma0_resource[] = {
34 [0] = { 38 [0] = {
35 .start = S5PV310_PA_PDMA0, 39 .start = EXYNOS4_PA_PDMA0,
36 .end = S5PV310_PA_PDMA0 + SZ_4K, 40 .end = EXYNOS4_PA_PDMA0 + SZ_4K,
37 .flags = IORESOURCE_MEM, 41 .flags = IORESOURCE_MEM,
38 }, 42 },
39 [1] = { 43 [1] = {
@@ -43,7 +47,7 @@ static struct resource s5pv310_pdma0_resource[] = {
43 }, 47 },
44}; 48};
45 49
46static struct s3c_pl330_platdata s5pv310_pdma0_pdata = { 50static struct s3c_pl330_platdata exynos4_pdma0_pdata = {
47 .peri = { 51 .peri = {
48 [0] = DMACH_PCM0_RX, 52 [0] = DMACH_PCM0_RX,
49 [1] = DMACH_PCM0_TX, 53 [1] = DMACH_PCM0_TX,
@@ -80,22 +84,22 @@ static struct s3c_pl330_platdata s5pv310_pdma0_pdata = {
80 }, 84 },
81}; 85};
82 86
83static struct platform_device s5pv310_device_pdma0 = { 87static struct platform_device exynos4_device_pdma0 = {
84 .name = "s3c-pl330", 88 .name = "s3c-pl330",
85 .id = 0, 89 .id = 0,
86 .num_resources = ARRAY_SIZE(s5pv310_pdma0_resource), 90 .num_resources = ARRAY_SIZE(exynos4_pdma0_resource),
87 .resource = s5pv310_pdma0_resource, 91 .resource = exynos4_pdma0_resource,
88 .dev = { 92 .dev = {
89 .dma_mask = &dma_dmamask, 93 .dma_mask = &dma_dmamask,
90 .coherent_dma_mask = DMA_BIT_MASK(32), 94 .coherent_dma_mask = DMA_BIT_MASK(32),
91 .platform_data = &s5pv310_pdma0_pdata, 95 .platform_data = &exynos4_pdma0_pdata,
92 }, 96 },
93}; 97};
94 98
95static struct resource s5pv310_pdma1_resource[] = { 99static struct resource exynos4_pdma1_resource[] = {
96 [0] = { 100 [0] = {
97 .start = S5PV310_PA_PDMA1, 101 .start = EXYNOS4_PA_PDMA1,
98 .end = S5PV310_PA_PDMA1 + SZ_4K, 102 .end = EXYNOS4_PA_PDMA1 + SZ_4K,
99 .flags = IORESOURCE_MEM, 103 .flags = IORESOURCE_MEM,
100 }, 104 },
101 [1] = { 105 [1] = {
@@ -105,7 +109,7 @@ static struct resource s5pv310_pdma1_resource[] = {
105 }, 109 },
106}; 110};
107 111
108static struct s3c_pl330_platdata s5pv310_pdma1_pdata = { 112static struct s3c_pl330_platdata exynos4_pdma1_pdata = {
109 .peri = { 113 .peri = {
110 [0] = DMACH_PCM0_RX, 114 [0] = DMACH_PCM0_RX,
111 [1] = DMACH_PCM0_TX, 115 [1] = DMACH_PCM0_TX,
@@ -142,27 +146,27 @@ static struct s3c_pl330_platdata s5pv310_pdma1_pdata = {
142 }, 146 },
143}; 147};
144 148
145static struct platform_device s5pv310_device_pdma1 = { 149static struct platform_device exynos4_device_pdma1 = {
146 .name = "s3c-pl330", 150 .name = "s3c-pl330",
147 .id = 1, 151 .id = 1,
148 .num_resources = ARRAY_SIZE(s5pv310_pdma1_resource), 152 .num_resources = ARRAY_SIZE(exynos4_pdma1_resource),
149 .resource = s5pv310_pdma1_resource, 153 .resource = exynos4_pdma1_resource,
150 .dev = { 154 .dev = {
151 .dma_mask = &dma_dmamask, 155 .dma_mask = &dma_dmamask,
152 .coherent_dma_mask = DMA_BIT_MASK(32), 156 .coherent_dma_mask = DMA_BIT_MASK(32),
153 .platform_data = &s5pv310_pdma1_pdata, 157 .platform_data = &exynos4_pdma1_pdata,
154 }, 158 },
155}; 159};
156 160
157static struct platform_device *s5pv310_dmacs[] __initdata = { 161static struct platform_device *exynos4_dmacs[] __initdata = {
158 &s5pv310_device_pdma0, 162 &exynos4_device_pdma0,
159 &s5pv310_device_pdma1, 163 &exynos4_device_pdma1,
160}; 164};
161 165
162static int __init s5pv310_dma_init(void) 166static int __init exynos4_dma_init(void)
163{ 167{
164 platform_add_devices(s5pv310_dmacs, ARRAY_SIZE(s5pv310_dmacs)); 168 platform_add_devices(exynos4_dmacs, ARRAY_SIZE(exynos4_dmacs));
165 169
166 return 0; 170 return 0;
167} 171}
168arch_initcall(s5pv310_dma_init); 172arch_initcall(exynos4_dma_init);
diff --git a/arch/arm/mach-exynos4/gpiolib.c b/arch/arm/mach-exynos4/gpiolib.c
new file mode 100644
index 000000000000..d54ca6adb660
--- /dev/null
+++ b/arch/arm/mach-exynos4/gpiolib.c
@@ -0,0 +1,365 @@
1/* linux/arch/arm/mach-exynos4/gpiolib.c
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS4 - GPIOlib support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/irq.h>
15#include <linux/io.h>
16#include <linux/gpio.h>
17
18#include <mach/map.h>
19
20#include <plat/gpio-core.h>
21#include <plat/gpio-cfg.h>
22#include <plat/gpio-cfg-helpers.h>
23
24static struct s3c_gpio_cfg gpio_cfg = {
25 .set_config = s3c_gpio_setcfg_s3c64xx_4bit,
26 .set_pull = s3c_gpio_setpull_updown,
27 .get_pull = s3c_gpio_getpull_updown,
28};
29
30static struct s3c_gpio_cfg gpio_cfg_noint = {
31 .set_config = s3c_gpio_setcfg_s3c64xx_4bit,
32 .set_pull = s3c_gpio_setpull_updown,
33 .get_pull = s3c_gpio_getpull_updown,
34};
35
36/*
37 * Following are the gpio banks in v310.
38 *
39 * The 'config' member when left to NULL, is initialized to the default
40 * structure gpio_cfg in the init function below.
41 *
42 * The 'base' member is also initialized in the init function below.
43 * Note: The initialization of 'base' member of s3c_gpio_chip structure
44 * uses the above macro and depends on the banks being listed in order here.
45 */
46static struct s3c_gpio_chip exynos4_gpio_part1_4bit[] = {
47 {
48 .chip = {
49 .base = EXYNOS4_GPA0(0),
50 .ngpio = EXYNOS4_GPIO_A0_NR,
51 .label = "GPA0",
52 },
53 }, {
54 .chip = {
55 .base = EXYNOS4_GPA1(0),
56 .ngpio = EXYNOS4_GPIO_A1_NR,
57 .label = "GPA1",
58 },
59 }, {
60 .chip = {
61 .base = EXYNOS4_GPB(0),
62 .ngpio = EXYNOS4_GPIO_B_NR,
63 .label = "GPB",
64 },
65 }, {
66 .chip = {
67 .base = EXYNOS4_GPC0(0),
68 .ngpio = EXYNOS4_GPIO_C0_NR,
69 .label = "GPC0",
70 },
71 }, {
72 .chip = {
73 .base = EXYNOS4_GPC1(0),
74 .ngpio = EXYNOS4_GPIO_C1_NR,
75 .label = "GPC1",
76 },
77 }, {
78 .chip = {
79 .base = EXYNOS4_GPD0(0),
80 .ngpio = EXYNOS4_GPIO_D0_NR,
81 .label = "GPD0",
82 },
83 }, {
84 .chip = {
85 .base = EXYNOS4_GPD1(0),
86 .ngpio = EXYNOS4_GPIO_D1_NR,
87 .label = "GPD1",
88 },
89 }, {
90 .chip = {
91 .base = EXYNOS4_GPE0(0),
92 .ngpio = EXYNOS4_GPIO_E0_NR,
93 .label = "GPE0",
94 },
95 }, {
96 .chip = {
97 .base = EXYNOS4_GPE1(0),
98 .ngpio = EXYNOS4_GPIO_E1_NR,
99 .label = "GPE1",
100 },
101 }, {
102 .chip = {
103 .base = EXYNOS4_GPE2(0),
104 .ngpio = EXYNOS4_GPIO_E2_NR,
105 .label = "GPE2",
106 },
107 }, {
108 .chip = {
109 .base = EXYNOS4_GPE3(0),
110 .ngpio = EXYNOS4_GPIO_E3_NR,
111 .label = "GPE3",
112 },
113 }, {
114 .chip = {
115 .base = EXYNOS4_GPE4(0),
116 .ngpio = EXYNOS4_GPIO_E4_NR,
117 .label = "GPE4",
118 },
119 }, {
120 .chip = {
121 .base = EXYNOS4_GPF0(0),
122 .ngpio = EXYNOS4_GPIO_F0_NR,
123 .label = "GPF0",
124 },
125 }, {
126 .chip = {
127 .base = EXYNOS4_GPF1(0),
128 .ngpio = EXYNOS4_GPIO_F1_NR,
129 .label = "GPF1",
130 },
131 }, {
132 .chip = {
133 .base = EXYNOS4_GPF2(0),
134 .ngpio = EXYNOS4_GPIO_F2_NR,
135 .label = "GPF2",
136 },
137 }, {
138 .chip = {
139 .base = EXYNOS4_GPF3(0),
140 .ngpio = EXYNOS4_GPIO_F3_NR,
141 .label = "GPF3",
142 },
143 },
144};
145
146static struct s3c_gpio_chip exynos4_gpio_part2_4bit[] = {
147 {
148 .chip = {
149 .base = EXYNOS4_GPJ0(0),
150 .ngpio = EXYNOS4_GPIO_J0_NR,
151 .label = "GPJ0",
152 },
153 }, {
154 .chip = {
155 .base = EXYNOS4_GPJ1(0),
156 .ngpio = EXYNOS4_GPIO_J1_NR,
157 .label = "GPJ1",
158 },
159 }, {
160 .chip = {
161 .base = EXYNOS4_GPK0(0),
162 .ngpio = EXYNOS4_GPIO_K0_NR,
163 .label = "GPK0",
164 },
165 }, {
166 .chip = {
167 .base = EXYNOS4_GPK1(0),
168 .ngpio = EXYNOS4_GPIO_K1_NR,
169 .label = "GPK1",
170 },
171 }, {
172 .chip = {
173 .base = EXYNOS4_GPK2(0),
174 .ngpio = EXYNOS4_GPIO_K2_NR,
175 .label = "GPK2",
176 },
177 }, {
178 .chip = {
179 .base = EXYNOS4_GPK3(0),
180 .ngpio = EXYNOS4_GPIO_K3_NR,
181 .label = "GPK3",
182 },
183 }, {
184 .chip = {
185 .base = EXYNOS4_GPL0(0),
186 .ngpio = EXYNOS4_GPIO_L0_NR,
187 .label = "GPL0",
188 },
189 }, {
190 .chip = {
191 .base = EXYNOS4_GPL1(0),
192 .ngpio = EXYNOS4_GPIO_L1_NR,
193 .label = "GPL1",
194 },
195 }, {
196 .chip = {
197 .base = EXYNOS4_GPL2(0),
198 .ngpio = EXYNOS4_GPIO_L2_NR,
199 .label = "GPL2",
200 },
201 }, {
202 .config = &gpio_cfg_noint,
203 .chip = {
204 .base = EXYNOS4_GPY0(0),
205 .ngpio = EXYNOS4_GPIO_Y0_NR,
206 .label = "GPY0",
207 },
208 }, {
209 .config = &gpio_cfg_noint,
210 .chip = {
211 .base = EXYNOS4_GPY1(0),
212 .ngpio = EXYNOS4_GPIO_Y1_NR,
213 .label = "GPY1",
214 },
215 }, {
216 .config = &gpio_cfg_noint,
217 .chip = {
218 .base = EXYNOS4_GPY2(0),
219 .ngpio = EXYNOS4_GPIO_Y2_NR,
220 .label = "GPY2",
221 },
222 }, {
223 .config = &gpio_cfg_noint,
224 .chip = {
225 .base = EXYNOS4_GPY3(0),
226 .ngpio = EXYNOS4_GPIO_Y3_NR,
227 .label = "GPY3",
228 },
229 }, {
230 .config = &gpio_cfg_noint,
231 .chip = {
232 .base = EXYNOS4_GPY4(0),
233 .ngpio = EXYNOS4_GPIO_Y4_NR,
234 .label = "GPY4",
235 },
236 }, {
237 .config = &gpio_cfg_noint,
238 .chip = {
239 .base = EXYNOS4_GPY5(0),
240 .ngpio = EXYNOS4_GPIO_Y5_NR,
241 .label = "GPY5",
242 },
243 }, {
244 .config = &gpio_cfg_noint,
245 .chip = {
246 .base = EXYNOS4_GPY6(0),
247 .ngpio = EXYNOS4_GPIO_Y6_NR,
248 .label = "GPY6",
249 },
250 }, {
251 .base = (S5P_VA_GPIO2 + 0xC00),
252 .config = &gpio_cfg_noint,
253 .irq_base = IRQ_EINT(0),
254 .chip = {
255 .base = EXYNOS4_GPX0(0),
256 .ngpio = EXYNOS4_GPIO_X0_NR,
257 .label = "GPX0",
258 .to_irq = samsung_gpiolib_to_irq,
259 },
260 }, {
261 .base = (S5P_VA_GPIO2 + 0xC20),
262 .config = &gpio_cfg_noint,
263 .irq_base = IRQ_EINT(8),
264 .chip = {
265 .base = EXYNOS4_GPX1(0),
266 .ngpio = EXYNOS4_GPIO_X1_NR,
267 .label = "GPX1",
268 .to_irq = samsung_gpiolib_to_irq,
269 },
270 }, {
271 .base = (S5P_VA_GPIO2 + 0xC40),
272 .config = &gpio_cfg_noint,
273 .irq_base = IRQ_EINT(16),
274 .chip = {
275 .base = EXYNOS4_GPX2(0),
276 .ngpio = EXYNOS4_GPIO_X2_NR,
277 .label = "GPX2",
278 .to_irq = samsung_gpiolib_to_irq,
279 },
280 }, {
281 .base = (S5P_VA_GPIO2 + 0xC60),
282 .config = &gpio_cfg_noint,
283 .irq_base = IRQ_EINT(24),
284 .chip = {
285 .base = EXYNOS4_GPX3(0),
286 .ngpio = EXYNOS4_GPIO_X3_NR,
287 .label = "GPX3",
288 .to_irq = samsung_gpiolib_to_irq,
289 },
290 },
291};
292
293static struct s3c_gpio_chip exynos4_gpio_part3_4bit[] = {
294 {
295 .chip = {
296 .base = EXYNOS4_GPZ(0),
297 .ngpio = EXYNOS4_GPIO_Z_NR,
298 .label = "GPZ",
299 },
300 },
301};
302
303static __init int exynos4_gpiolib_init(void)
304{
305 struct s3c_gpio_chip *chip;
306 int i;
307 int group = 0;
308 int nr_chips;
309
310 /* GPIO part 1 */
311
312 chip = exynos4_gpio_part1_4bit;
313 nr_chips = ARRAY_SIZE(exynos4_gpio_part1_4bit);
314
315 for (i = 0; i < nr_chips; i++, chip++) {
316 if (chip->config == NULL) {
317 chip->config = &gpio_cfg;
318 /* Assign the GPIO interrupt group */
319 chip->group = group++;
320 }
321 if (chip->base == NULL)
322 chip->base = S5P_VA_GPIO1 + (i) * 0x20;
323 }
324
325 samsung_gpiolib_add_4bit_chips(exynos4_gpio_part1_4bit, nr_chips);
326
327 /* GPIO part 2 */
328
329 chip = exynos4_gpio_part2_4bit;
330 nr_chips = ARRAY_SIZE(exynos4_gpio_part2_4bit);
331
332 for (i = 0; i < nr_chips; i++, chip++) {
333 if (chip->config == NULL) {
334 chip->config = &gpio_cfg;
335 /* Assign the GPIO interrupt group */
336 chip->group = group++;
337 }
338 if (chip->base == NULL)
339 chip->base = S5P_VA_GPIO2 + (i) * 0x20;
340 }
341
342 samsung_gpiolib_add_4bit_chips(exynos4_gpio_part2_4bit, nr_chips);
343
344 /* GPIO part 3 */
345
346 chip = exynos4_gpio_part3_4bit;
347 nr_chips = ARRAY_SIZE(exynos4_gpio_part3_4bit);
348
349 for (i = 0; i < nr_chips; i++, chip++) {
350 if (chip->config == NULL) {
351 chip->config = &gpio_cfg;
352 /* Assign the GPIO interrupt group */
353 chip->group = group++;
354 }
355 if (chip->base == NULL)
356 chip->base = S5P_VA_GPIO3 + (i) * 0x20;
357 }
358
359 samsung_gpiolib_add_4bit_chips(exynos4_gpio_part3_4bit, nr_chips);
360 s5p_register_gpioint_bank(IRQ_GPIO_XA, 0, IRQ_GPIO1_NR_GROUPS);
361 s5p_register_gpioint_bank(IRQ_GPIO_XB, IRQ_GPIO1_NR_GROUPS, IRQ_GPIO2_NR_GROUPS);
362
363 return 0;
364}
365core_initcall(exynos4_gpiolib_init);
diff --git a/arch/arm/mach-s5pv310/headsmp.S b/arch/arm/mach-exynos4/headsmp.S
index 164b7b045713..6c6cfc50c46b 100644
--- a/arch/arm/mach-s5pv310/headsmp.S
+++ b/arch/arm/mach-exynos4/headsmp.S
@@ -1,5 +1,5 @@
1/* 1/*
2 * linux/arch/arm/mach-s5pv310/headsmp.S 2 * linux/arch/arm/mach-exynos4/headsmp.S
3 * 3 *
4 * Cloned from linux/arch/arm/mach-realview/headsmp.S 4 * Cloned from linux/arch/arm/mach-realview/headsmp.S
5 * 5 *
@@ -16,11 +16,11 @@
16 __INIT 16 __INIT
17 17
18/* 18/*
19 * s5pv310 specific entry point for secondary CPUs. This provides 19 * exynos4 specific entry point for secondary CPUs. This provides
20 * a "holding pen" into which all secondary cores are held until we're 20 * a "holding pen" into which all secondary cores are held until we're
21 * ready for them to initialise. 21 * ready for them to initialise.
22 */ 22 */
23ENTRY(s5pv310_secondary_startup) 23ENTRY(exynos4_secondary_startup)
24 mrc p15, 0, r0, c0, c0, 5 24 mrc p15, 0, r0, c0, c0, 5
25 and r0, r0, #15 25 and r0, r0, #15
26 adr r4, 1f 26 adr r4, 1f
diff --git a/arch/arm/mach-s5pv310/hotplug.c b/arch/arm/mach-exynos4/hotplug.c
index c24235c89eed..2b5909e2ccd3 100644
--- a/arch/arm/mach-s5pv310/hotplug.c
+++ b/arch/arm/mach-exynos4/hotplug.c
@@ -1,4 +1,4 @@
1/* linux arch/arm/mach-s5pv310/hotplug.c 1/* linux arch/arm/mach-exynos4/hotplug.c
2 * 2 *
3 * Cloned from linux/arch/arm/mach-realview/hotplug.c 3 * Cloned from linux/arch/arm/mach-realview/hotplug.c
4 * 4 *
@@ -30,13 +30,13 @@ static inline void cpu_enter_lowpower(void)
30 * Turn off coherency 30 * Turn off coherency
31 */ 31 */
32 " mrc p15, 0, %0, c1, c0, 1\n" 32 " mrc p15, 0, %0, c1, c0, 1\n"
33 " bic %0, %0, #0x20\n" 33 " bic %0, %0, %3\n"
34 " mcr p15, 0, %0, c1, c0, 1\n" 34 " mcr p15, 0, %0, c1, c0, 1\n"
35 " mrc p15, 0, %0, c1, c0, 0\n" 35 " mrc p15, 0, %0, c1, c0, 0\n"
36 " bic %0, %0, %2\n" 36 " bic %0, %0, %2\n"
37 " mcr p15, 0, %0, c1, c0, 0\n" 37 " mcr p15, 0, %0, c1, c0, 0\n"
38 : "=&r" (v) 38 : "=&r" (v)
39 : "r" (0), "Ir" (CR_C) 39 : "r" (0), "Ir" (CR_C), "Ir" (0x40)
40 : "cc"); 40 : "cc");
41} 41}
42 42
@@ -49,10 +49,10 @@ static inline void cpu_leave_lowpower(void)
49 " orr %0, %0, %1\n" 49 " orr %0, %0, %1\n"
50 " mcr p15, 0, %0, c1, c0, 0\n" 50 " mcr p15, 0, %0, c1, c0, 0\n"
51 " mrc p15, 0, %0, c1, c0, 1\n" 51 " mrc p15, 0, %0, c1, c0, 1\n"
52 " orr %0, %0, #0x20\n" 52 " orr %0, %0, %2\n"
53 " mcr p15, 0, %0, c1, c0, 1\n" 53 " mcr p15, 0, %0, c1, c0, 1\n"
54 : "=&r" (v) 54 : "=&r" (v)
55 : "Ir" (CR_C) 55 : "Ir" (CR_C), "Ir" (0x40)
56 : "cc"); 56 : "cc");
57} 57}
58 58
diff --git a/arch/arm/mach-s5pv310/include/mach/debug-macro.S b/arch/arm/mach-exynos4/include/mach/debug-macro.S
index b0d920c474d3..58bbd049a6c4 100644
--- a/arch/arm/mach-s5pv310/include/mach/debug-macro.S
+++ b/arch/arm/mach-exynos4/include/mach/debug-macro.S
@@ -1,7 +1,7 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/debug-macro.S 1/* linux/arch/arm/mach-exynos4/include/mach/debug-macro.S
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * Based on arch/arm/mach-s3c6400/include/mach/debug-macro.S 6 * Based on arch/arm/mach-s3c6400/include/mach/debug-macro.S
7 * 7 *
diff --git a/arch/arm/mach-s5pv310/include/mach/dma.h b/arch/arm/mach-exynos4/include/mach/dma.h
index 81209eb1409b..81209eb1409b 100644
--- a/arch/arm/mach-s5pv310/include/mach/dma.h
+++ b/arch/arm/mach-exynos4/include/mach/dma.h
diff --git a/arch/arm/mach-s5pv310/include/mach/entry-macro.S b/arch/arm/mach-exynos4/include/mach/entry-macro.S
index e600e1d522df..d8f38c2e5654 100644
--- a/arch/arm/mach-s5pv310/include/mach/entry-macro.S
+++ b/arch/arm/mach-exynos4/include/mach/entry-macro.S
@@ -1,8 +1,8 @@
1/* arch/arm/mach-s5pv310/include/mach/entry-macro.S 1/* arch/arm/mach-exynos4/include/mach/entry-macro.S
2 * 2 *
3 * Cloned from arch/arm/mach-realview/include/mach/entry-macro.S 3 * Cloned from arch/arm/mach-realview/include/mach/entry-macro.S
4 * 4 *
5 * Low-level IRQ helper macros for S5PV310 platforms 5 * Low-level IRQ helper macros for EXYNOS4 platforms
6 * 6 *
7 * This file is licensed under the terms of the GNU General Public 7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any 8 * License version 2. This program is licensed "as is" without any
diff --git a/arch/arm/mach-exynos4/include/mach/gpio.h b/arch/arm/mach-exynos4/include/mach/gpio.h
new file mode 100644
index 000000000000..939728b38d48
--- /dev/null
+++ b/arch/arm/mach-exynos4/include/mach/gpio.h
@@ -0,0 +1,156 @@
1/* linux/arch/arm/mach-exynos4/include/mach/gpio.h
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS4 - GPIO lib support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_GPIO_H
14#define __ASM_ARCH_GPIO_H __FILE__
15
16#define gpio_get_value __gpio_get_value
17#define gpio_set_value __gpio_set_value
18#define gpio_cansleep __gpio_cansleep
19#define gpio_to_irq __gpio_to_irq
20
21/* Practically, GPIO banks upto GPZ are the configurable gpio banks */
22
23/* GPIO bank sizes */
24#define EXYNOS4_GPIO_A0_NR (8)
25#define EXYNOS4_GPIO_A1_NR (6)
26#define EXYNOS4_GPIO_B_NR (8)
27#define EXYNOS4_GPIO_C0_NR (5)
28#define EXYNOS4_GPIO_C1_NR (5)
29#define EXYNOS4_GPIO_D0_NR (4)
30#define EXYNOS4_GPIO_D1_NR (4)
31#define EXYNOS4_GPIO_E0_NR (5)
32#define EXYNOS4_GPIO_E1_NR (8)
33#define EXYNOS4_GPIO_E2_NR (6)
34#define EXYNOS4_GPIO_E3_NR (8)
35#define EXYNOS4_GPIO_E4_NR (8)
36#define EXYNOS4_GPIO_F0_NR (8)
37#define EXYNOS4_GPIO_F1_NR (8)
38#define EXYNOS4_GPIO_F2_NR (8)
39#define EXYNOS4_GPIO_F3_NR (6)
40#define EXYNOS4_GPIO_J0_NR (8)
41#define EXYNOS4_GPIO_J1_NR (5)
42#define EXYNOS4_GPIO_K0_NR (7)
43#define EXYNOS4_GPIO_K1_NR (7)
44#define EXYNOS4_GPIO_K2_NR (7)
45#define EXYNOS4_GPIO_K3_NR (7)
46#define EXYNOS4_GPIO_L0_NR (8)
47#define EXYNOS4_GPIO_L1_NR (3)
48#define EXYNOS4_GPIO_L2_NR (8)
49#define EXYNOS4_GPIO_X0_NR (8)
50#define EXYNOS4_GPIO_X1_NR (8)
51#define EXYNOS4_GPIO_X2_NR (8)
52#define EXYNOS4_GPIO_X3_NR (8)
53#define EXYNOS4_GPIO_Y0_NR (6)
54#define EXYNOS4_GPIO_Y1_NR (4)
55#define EXYNOS4_GPIO_Y2_NR (6)
56#define EXYNOS4_GPIO_Y3_NR (8)
57#define EXYNOS4_GPIO_Y4_NR (8)
58#define EXYNOS4_GPIO_Y5_NR (8)
59#define EXYNOS4_GPIO_Y6_NR (8)
60#define EXYNOS4_GPIO_Z_NR (7)
61
62/* GPIO bank numbers */
63
64#define EXYNOS4_GPIO_NEXT(__gpio) \
65 ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
66
67enum s5p_gpio_number {
68 EXYNOS4_GPIO_A0_START = 0,
69 EXYNOS4_GPIO_A1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_A0),
70 EXYNOS4_GPIO_B_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_A1),
71 EXYNOS4_GPIO_C0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_B),
72 EXYNOS4_GPIO_C1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_C0),
73 EXYNOS4_GPIO_D0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_C1),
74 EXYNOS4_GPIO_D1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_D0),
75 EXYNOS4_GPIO_E0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_D1),
76 EXYNOS4_GPIO_E1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E0),
77 EXYNOS4_GPIO_E2_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E1),
78 EXYNOS4_GPIO_E3_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E2),
79 EXYNOS4_GPIO_E4_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E3),
80 EXYNOS4_GPIO_F0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E4),
81 EXYNOS4_GPIO_F1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_F0),
82 EXYNOS4_GPIO_F2_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_F1),
83 EXYNOS4_GPIO_F3_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_F2),
84 EXYNOS4_GPIO_J0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_F3),
85 EXYNOS4_GPIO_J1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_J0),
86 EXYNOS4_GPIO_K0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_J1),
87 EXYNOS4_GPIO_K1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_K0),
88 EXYNOS4_GPIO_K2_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_K1),
89 EXYNOS4_GPIO_K3_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_K2),
90 EXYNOS4_GPIO_L0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_K3),
91 EXYNOS4_GPIO_L1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_L0),
92 EXYNOS4_GPIO_L2_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_L1),
93 EXYNOS4_GPIO_X0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_L2),
94 EXYNOS4_GPIO_X1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_X0),
95 EXYNOS4_GPIO_X2_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_X1),
96 EXYNOS4_GPIO_X3_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_X2),
97 EXYNOS4_GPIO_Y0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_X3),
98 EXYNOS4_GPIO_Y1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y0),
99 EXYNOS4_GPIO_Y2_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y1),
100 EXYNOS4_GPIO_Y3_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y2),
101 EXYNOS4_GPIO_Y4_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y3),
102 EXYNOS4_GPIO_Y5_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y4),
103 EXYNOS4_GPIO_Y6_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y5),
104 EXYNOS4_GPIO_Z_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y6),
105};
106
107/* EXYNOS4 GPIO number definitions */
108#define EXYNOS4_GPA0(_nr) (EXYNOS4_GPIO_A0_START + (_nr))
109#define EXYNOS4_GPA1(_nr) (EXYNOS4_GPIO_A1_START + (_nr))
110#define EXYNOS4_GPB(_nr) (EXYNOS4_GPIO_B_START + (_nr))
111#define EXYNOS4_GPC0(_nr) (EXYNOS4_GPIO_C0_START + (_nr))
112#define EXYNOS4_GPC1(_nr) (EXYNOS4_GPIO_C1_START + (_nr))
113#define EXYNOS4_GPD0(_nr) (EXYNOS4_GPIO_D0_START + (_nr))
114#define EXYNOS4_GPD1(_nr) (EXYNOS4_GPIO_D1_START + (_nr))
115#define EXYNOS4_GPE0(_nr) (EXYNOS4_GPIO_E0_START + (_nr))
116#define EXYNOS4_GPE1(_nr) (EXYNOS4_GPIO_E1_START + (_nr))
117#define EXYNOS4_GPE2(_nr) (EXYNOS4_GPIO_E2_START + (_nr))
118#define EXYNOS4_GPE3(_nr) (EXYNOS4_GPIO_E3_START + (_nr))
119#define EXYNOS4_GPE4(_nr) (EXYNOS4_GPIO_E4_START + (_nr))
120#define EXYNOS4_GPF0(_nr) (EXYNOS4_GPIO_F0_START + (_nr))
121#define EXYNOS4_GPF1(_nr) (EXYNOS4_GPIO_F1_START + (_nr))
122#define EXYNOS4_GPF2(_nr) (EXYNOS4_GPIO_F2_START + (_nr))
123#define EXYNOS4_GPF3(_nr) (EXYNOS4_GPIO_F3_START + (_nr))
124#define EXYNOS4_GPJ0(_nr) (EXYNOS4_GPIO_J0_START + (_nr))
125#define EXYNOS4_GPJ1(_nr) (EXYNOS4_GPIO_J1_START + (_nr))
126#define EXYNOS4_GPK0(_nr) (EXYNOS4_GPIO_K0_START + (_nr))
127#define EXYNOS4_GPK1(_nr) (EXYNOS4_GPIO_K1_START + (_nr))
128#define EXYNOS4_GPK2(_nr) (EXYNOS4_GPIO_K2_START + (_nr))
129#define EXYNOS4_GPK3(_nr) (EXYNOS4_GPIO_K3_START + (_nr))
130#define EXYNOS4_GPL0(_nr) (EXYNOS4_GPIO_L0_START + (_nr))
131#define EXYNOS4_GPL1(_nr) (EXYNOS4_GPIO_L1_START + (_nr))
132#define EXYNOS4_GPL2(_nr) (EXYNOS4_GPIO_L2_START + (_nr))
133#define EXYNOS4_GPX0(_nr) (EXYNOS4_GPIO_X0_START + (_nr))
134#define EXYNOS4_GPX1(_nr) (EXYNOS4_GPIO_X1_START + (_nr))
135#define EXYNOS4_GPX2(_nr) (EXYNOS4_GPIO_X2_START + (_nr))
136#define EXYNOS4_GPX3(_nr) (EXYNOS4_GPIO_X3_START + (_nr))
137#define EXYNOS4_GPY0(_nr) (EXYNOS4_GPIO_Y0_START + (_nr))
138#define EXYNOS4_GPY1(_nr) (EXYNOS4_GPIO_Y1_START + (_nr))
139#define EXYNOS4_GPY2(_nr) (EXYNOS4_GPIO_Y2_START + (_nr))
140#define EXYNOS4_GPY3(_nr) (EXYNOS4_GPIO_Y3_START + (_nr))
141#define EXYNOS4_GPY4(_nr) (EXYNOS4_GPIO_Y4_START + (_nr))
142#define EXYNOS4_GPY5(_nr) (EXYNOS4_GPIO_Y5_START + (_nr))
143#define EXYNOS4_GPY6(_nr) (EXYNOS4_GPIO_Y6_START + (_nr))
144#define EXYNOS4_GPZ(_nr) (EXYNOS4_GPIO_Z_START + (_nr))
145
146/* the end of the EXYNOS4 specific gpios */
147#define EXYNOS4_GPIO_END (EXYNOS4_GPZ(EXYNOS4_GPIO_Z_NR) + 1)
148#define S3C_GPIO_END EXYNOS4_GPIO_END
149
150/* define the number of gpios we need to the one after the GPZ() range */
151#define ARCH_NR_GPIOS (EXYNOS4_GPZ(EXYNOS4_GPIO_Z_NR) + \
152 CONFIG_SAMSUNG_GPIO_EXTRA + 1)
153
154#include <asm-generic/gpio.h>
155
156#endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/hardware.h b/arch/arm/mach-exynos4/include/mach/hardware.h
index 28ff9881f1a6..5109eb232f23 100644
--- a/arch/arm/mach-s5pv310/include/mach/hardware.h
+++ b/arch/arm/mach-exynos4/include/mach/hardware.h
@@ -1,9 +1,9 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/hardware.h 1/* linux/arch/arm/mach-exynos4/include/mach/hardware.h
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * S5PV310 - Hardware support 6 * EXYNOS4 - Hardware support
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/mach-s5pv310/include/mach/io.h b/arch/arm/mach-exynos4/include/mach/io.h
index 8a7f9128391f..d5478d247535 100644
--- a/arch/arm/mach-s5pv310/include/mach/io.h
+++ b/arch/arm/mach-exynos4/include/mach/io.h
@@ -1,13 +1,13 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/io.h 1/* linux/arch/arm/mach-exynos4/include/mach/io.h
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * Copyright 2008-2010 Ben Dooks <ben-linux@fluff.org> 6 * Copyright 2008-2010 Ben Dooks <ben-linux@fluff.org>
7 * 7 *
8 * Based on arch/arm/mach-s5p6442/include/mach/io.h 8 * Based on arch/arm/mach-s5p6442/include/mach/io.h
9 * 9 *
10 * Default IO routines for S5PV310 10 * Default IO routines for EXYNOS4
11 * 11 *
12 * This program is free software; you can redistribute it and/or modify 12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as 13 * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/mach-s5pv310/include/mach/irqs.h b/arch/arm/mach-exynos4/include/mach/irqs.h
index 536b0b59fc83..5d037301d21a 100644
--- a/arch/arm/mach-s5pv310/include/mach/irqs.h
+++ b/arch/arm/mach-exynos4/include/mach/irqs.h
@@ -1,9 +1,9 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/irqs.h 1/* linux/arch/arm/mach-exynos4/include/mach/irqs.h
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * S5PV310 - IRQ definitions 6 * EXYNOS4 - IRQ definitions
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
@@ -85,6 +85,9 @@
85#define IRQ_RTC_ALARM COMBINER_IRQ(23, 0) 85#define IRQ_RTC_ALARM COMBINER_IRQ(23, 0)
86#define IRQ_RTC_TIC COMBINER_IRQ(23, 1) 86#define IRQ_RTC_TIC COMBINER_IRQ(23, 1)
87 87
88#define IRQ_GPIO_XB COMBINER_IRQ(24, 0)
89#define IRQ_GPIO_XA COMBINER_IRQ(24, 1)
90
88#define IRQ_UART0 COMBINER_IRQ(26, 0) 91#define IRQ_UART0 COMBINER_IRQ(26, 0)
89#define IRQ_UART1 COMBINER_IRQ(26, 1) 92#define IRQ_UART1 COMBINER_IRQ(26, 1)
90#define IRQ_UART2 COMBINER_IRQ(26, 2) 93#define IRQ_UART2 COMBINER_IRQ(26, 2)
@@ -108,6 +111,11 @@
108#define IRQ_MIPI_CSIS0 COMBINER_IRQ(30, 0) 111#define IRQ_MIPI_CSIS0 COMBINER_IRQ(30, 0)
109#define IRQ_MIPI_CSIS1 COMBINER_IRQ(30, 1) 112#define IRQ_MIPI_CSIS1 COMBINER_IRQ(30, 1)
110 113
114#define IRQ_FIMC0 COMBINER_IRQ(32, 0)
115#define IRQ_FIMC1 COMBINER_IRQ(32, 1)
116#define IRQ_FIMC2 COMBINER_IRQ(33, 0)
117#define IRQ_FIMC3 COMBINER_IRQ(33, 1)
118
111#define IRQ_ONENAND_AUDI COMBINER_IRQ(34, 0) 119#define IRQ_ONENAND_AUDI COMBINER_IRQ(34, 0)
112 120
113#define IRQ_MCT_L1 COMBINER_IRQ(35, 3) 121#define IRQ_MCT_L1 COMBINER_IRQ(35, 3)
@@ -131,6 +139,7 @@
131#define IRQ_MCT_L0 COMBINER_IRQ(51, 0) 139#define IRQ_MCT_L0 COMBINER_IRQ(51, 0)
132 140
133#define IRQ_WDT COMBINER_IRQ(53, 0) 141#define IRQ_WDT COMBINER_IRQ(53, 0)
142#define IRQ_MCT_G0 COMBINER_IRQ(53, 4)
134 143
135#define MAX_COMBINER_NR 54 144#define MAX_COMBINER_NR 54
136 145
@@ -139,8 +148,13 @@
139#define S5P_EINT_BASE1 (S5P_IRQ_EINT_BASE + 0) 148#define S5P_EINT_BASE1 (S5P_IRQ_EINT_BASE + 0)
140#define S5P_EINT_BASE2 (S5P_IRQ_EINT_BASE + 16) 149#define S5P_EINT_BASE2 (S5P_IRQ_EINT_BASE + 16)
141 150
142/* Set the default NR_IRQS */ 151/* optional GPIO interrupts */
152#define S5P_GPIOINT_BASE (S5P_IRQ_EINT_BASE + 32)
153#define IRQ_GPIO1_NR_GROUPS 16
154#define IRQ_GPIO2_NR_GROUPS 9
155#define IRQ_GPIO_END (S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT)
143 156
144#define NR_IRQS (S5P_IRQ_EINT_BASE + 32) 157/* Set the default NR_IRQS */
158#define NR_IRQS (IRQ_GPIO_END)
145 159
146#endif /* __ASM_ARCH_IRQS_H */ 160#endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-exynos4/include/mach/map.h b/arch/arm/mach-exynos4/include/mach/map.h
new file mode 100644
index 000000000000..6330b73b9ea7
--- /dev/null
+++ b/arch/arm/mach-exynos4/include/mach/map.h
@@ -0,0 +1,162 @@
1/* linux/arch/arm/mach-exynos4/include/mach/map.h
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * EXYNOS4 - Memory map definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_MAP_H
14#define __ASM_ARCH_MAP_H __FILE__
15
16#include <plat/map-base.h>
17
18/*
19 * EXYNOS4 UART offset is 0x10000 but the older S5P SoCs are 0x400.
20 * So need to define it, and here is to avoid redefinition warning.
21 */
22#define S3C_UART_OFFSET (0x10000)
23
24#include <plat/map-s5p.h>
25
26#define EXYNOS4_PA_SYSRAM 0x02020000
27
28#define EXYNOS4_PA_FIMC0 0x11800000
29#define EXYNOS4_PA_FIMC1 0x11810000
30#define EXYNOS4_PA_FIMC2 0x11820000
31#define EXYNOS4_PA_FIMC3 0x11830000
32
33#define EXYNOS4_PA_I2S0 0x03830000
34#define EXYNOS4_PA_I2S1 0xE3100000
35#define EXYNOS4_PA_I2S2 0xE2A00000
36
37#define EXYNOS4_PA_PCM0 0x03840000
38#define EXYNOS4_PA_PCM1 0x13980000
39#define EXYNOS4_PA_PCM2 0x13990000
40
41#define EXYNOS4_PA_SROM_BANK(x) (0x04000000 + ((x) * 0x01000000))
42
43#define EXYNOS4_PA_ONENAND 0x0C000000
44#define EXYNOS4_PA_ONENAND_DMA 0x0C600000
45
46#define EXYNOS4_PA_CHIPID 0x10000000
47
48#define EXYNOS4_PA_SYSCON 0x10010000
49#define EXYNOS4_PA_PMU 0x10020000
50#define EXYNOS4_PA_CMU 0x10030000
51
52#define EXYNOS4_PA_SYSTIMER 0x10050000
53#define EXYNOS4_PA_WATCHDOG 0x10060000
54#define EXYNOS4_PA_RTC 0x10070000
55
56#define EXYNOS4_PA_KEYPAD 0x100A0000
57
58#define EXYNOS4_PA_DMC0 0x10400000
59
60#define EXYNOS4_PA_COMBINER 0x10448000
61
62#define EXYNOS4_PA_COREPERI 0x10500000
63#define EXYNOS4_PA_GIC_CPU 0x10500100
64#define EXYNOS4_PA_TWD 0x10500600
65#define EXYNOS4_PA_GIC_DIST 0x10501000
66#define EXYNOS4_PA_L2CC 0x10502000
67
68#define EXYNOS4_PA_MDMA 0x10810000
69#define EXYNOS4_PA_PDMA0 0x12680000
70#define EXYNOS4_PA_PDMA1 0x12690000
71
72#define EXYNOS4_PA_SYSMMU_MDMA 0x10A40000
73#define EXYNOS4_PA_SYSMMU_SSS 0x10A50000
74#define EXYNOS4_PA_SYSMMU_FIMC0 0x11A20000
75#define EXYNOS4_PA_SYSMMU_FIMC1 0x11A30000
76#define EXYNOS4_PA_SYSMMU_FIMC2 0x11A40000
77#define EXYNOS4_PA_SYSMMU_FIMC3 0x11A50000
78#define EXYNOS4_PA_SYSMMU_JPEG 0x11A60000
79#define EXYNOS4_PA_SYSMMU_FIMD0 0x11E20000
80#define EXYNOS4_PA_SYSMMU_FIMD1 0x12220000
81#define EXYNOS4_PA_SYSMMU_PCIe 0x12620000
82#define EXYNOS4_PA_SYSMMU_G2D 0x12A20000
83#define EXYNOS4_PA_SYSMMU_ROTATOR 0x12A30000
84#define EXYNOS4_PA_SYSMMU_MDMA2 0x12A40000
85#define EXYNOS4_PA_SYSMMU_TV 0x12E20000
86#define EXYNOS4_PA_SYSMMU_MFC_L 0x13620000
87#define EXYNOS4_PA_SYSMMU_MFC_R 0x13630000
88
89#define EXYNOS4_PA_GPIO1 0x11400000
90#define EXYNOS4_PA_GPIO2 0x11000000
91#define EXYNOS4_PA_GPIO3 0x03860000
92
93#define EXYNOS4_PA_MIPI_CSIS0 0x11880000
94#define EXYNOS4_PA_MIPI_CSIS1 0x11890000
95
96#define EXYNOS4_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000))
97
98#define EXYNOS4_PA_SATA 0x12560000
99#define EXYNOS4_PA_SATAPHY 0x125D0000
100#define EXYNOS4_PA_SATAPHY_CTRL 0x126B0000
101
102#define EXYNOS4_PA_SROMC 0x12570000
103
104#define EXYNOS4_PA_UART 0x13800000
105
106#define EXYNOS4_PA_IIC(x) (0x13860000 + ((x) * 0x10000))
107
108#define EXYNOS4_PA_AC97 0x139A0000
109
110#define EXYNOS4_PA_SPDIF 0x139B0000
111
112#define EXYNOS4_PA_TIMER 0x139D0000
113
114#define EXYNOS4_PA_SDRAM 0x40000000
115
116/* Compatibiltiy Defines */
117
118#define S3C_PA_HSMMC0 EXYNOS4_PA_HSMMC(0)
119#define S3C_PA_HSMMC1 EXYNOS4_PA_HSMMC(1)
120#define S3C_PA_HSMMC2 EXYNOS4_PA_HSMMC(2)
121#define S3C_PA_HSMMC3 EXYNOS4_PA_HSMMC(3)
122#define S3C_PA_IIC EXYNOS4_PA_IIC(0)
123#define S3C_PA_IIC1 EXYNOS4_PA_IIC(1)
124#define S3C_PA_IIC2 EXYNOS4_PA_IIC(2)
125#define S3C_PA_IIC3 EXYNOS4_PA_IIC(3)
126#define S3C_PA_IIC4 EXYNOS4_PA_IIC(4)
127#define S3C_PA_IIC5 EXYNOS4_PA_IIC(5)
128#define S3C_PA_IIC6 EXYNOS4_PA_IIC(6)
129#define S3C_PA_IIC7 EXYNOS4_PA_IIC(7)
130#define S3C_PA_RTC EXYNOS4_PA_RTC
131#define S3C_PA_WDT EXYNOS4_PA_WATCHDOG
132
133#define S5P_PA_CHIPID EXYNOS4_PA_CHIPID
134#define S5P_PA_FIMC0 EXYNOS4_PA_FIMC0
135#define S5P_PA_FIMC1 EXYNOS4_PA_FIMC1
136#define S5P_PA_FIMC2 EXYNOS4_PA_FIMC2
137#define S5P_PA_FIMC3 EXYNOS4_PA_FIMC3
138#define S5P_PA_MIPI_CSIS0 EXYNOS4_PA_MIPI_CSIS0
139#define S5P_PA_MIPI_CSIS1 EXYNOS4_PA_MIPI_CSIS1
140#define S5P_PA_ONENAND EXYNOS4_PA_ONENAND
141#define S5P_PA_ONENAND_DMA EXYNOS4_PA_ONENAND_DMA
142#define S5P_PA_SDRAM EXYNOS4_PA_SDRAM
143#define S5P_PA_SROMC EXYNOS4_PA_SROMC
144#define S5P_PA_SYSCON EXYNOS4_PA_SYSCON
145#define S5P_PA_TIMER EXYNOS4_PA_TIMER
146
147#define SAMSUNG_PA_KEYPAD EXYNOS4_PA_KEYPAD
148
149/* UART */
150
151#define S3C_PA_UART EXYNOS4_PA_UART
152
153#define S5P_PA_UART(x) (S3C_PA_UART + ((x) * S3C_UART_OFFSET))
154#define S5P_PA_UART0 S5P_PA_UART(0)
155#define S5P_PA_UART1 S5P_PA_UART(1)
156#define S5P_PA_UART2 S5P_PA_UART(2)
157#define S5P_PA_UART3 S5P_PA_UART(3)
158#define S5P_PA_UART4 S5P_PA_UART(4)
159
160#define S5P_SZ_UART SZ_256
161
162#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/memory.h b/arch/arm/mach-exynos4/include/mach/memory.h
index 470b01bf8614..374ef2cf7152 100644
--- a/arch/arm/mach-s5pv310/include/mach/memory.h
+++ b/arch/arm/mach-exynos4/include/mach/memory.h
@@ -1,9 +1,9 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/memory.h 1/* linux/arch/arm/mach-exynos4/include/mach/memory.h
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * S5PV310 - Memory definitions 6 * EXYNOS4 - Memory definitions
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/mach-exynos4/include/mach/pm-core.h b/arch/arm/mach-exynos4/include/mach/pm-core.h
new file mode 100644
index 000000000000..f26e46bc06ca
--- /dev/null
+++ b/arch/arm/mach-exynos4/include/mach/pm-core.h
@@ -0,0 +1,49 @@
1/* linux/arch/arm/mach-exynos4/include/mach/pm-core.h
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Based on arch/arm/mach-s3c2410/include/mach/pm-core.h,
7 * Copyright 2008 Simtec Electronics
8 * Ben Dooks <ben@simtec.co.uk>
9 * http://armlinux.simtec.co.uk/
10 *
11 * EXYNOS4210 - PM core support for arch/arm/plat-s5p/pm.c
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16*/
17#include <mach/regs-pmu.h>
18
19static inline void s3c_pm_debug_init_uart(void)
20{
21 /* nothing here yet */
22}
23
24static inline void s3c_pm_arch_prepare_irqs(void)
25{
26 unsigned int tmp;
27 tmp = __raw_readl(S5P_WAKEUP_MASK);
28 tmp &= ~(1 << 31);
29 __raw_writel(tmp, S5P_WAKEUP_MASK);
30
31 __raw_writel(s3c_irqwake_intmask, S5P_WAKEUP_MASK);
32 __raw_writel(s3c_irqwake_eintmask, S5P_EINT_WAKEUP_MASK);
33}
34
35static inline void s3c_pm_arch_stop_clocks(void)
36{
37 /* nothing here yet */
38}
39
40static inline void s3c_pm_arch_show_resume_irqs(void)
41{
42 /* nothing here yet */
43}
44
45static inline void s3c_pm_arch_update_uart(void __iomem *regs,
46 struct pm_uart_save *save)
47{
48 /* nothing here yet */
49}
diff --git a/arch/arm/mach-s5pv310/include/mach/pwm-clock.h b/arch/arm/mach-exynos4/include/mach/pwm-clock.h
index 7e6da2701088..8e12090287bb 100644
--- a/arch/arm/mach-s5pv310/include/mach/pwm-clock.h
+++ b/arch/arm/mach-exynos4/include/mach/pwm-clock.h
@@ -1,7 +1,7 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/pwm-clock.h 1/* linux/arch/arm/mach-exynos4/include/mach/pwm-clock.h
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * Copyright 2008 Openmoko, Inc. 6 * Copyright 2008 Openmoko, Inc.
7 * Copyright 2008 Simtec Electronics 7 * Copyright 2008 Simtec Electronics
@@ -10,7 +10,7 @@
10 * 10 *
11 * Based on arch/arm/mach-s3c64xx/include/mach/pwm-clock.h 11 * Based on arch/arm/mach-s3c64xx/include/mach/pwm-clock.h
12 * 12 *
13 * S5PV310 - pwm clock and timer support 13 * EXYNOS4 - pwm clock and timer support
14 * 14 *
15 * This program is free software; you can redistribute it and/or modify 15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as 16 * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/mach-s5pv310/include/mach/regs-clock.h b/arch/arm/mach-exynos4/include/mach/regs-clock.h
index b5c4ada1cff5..6e311c1157f5 100644
--- a/arch/arm/mach-s5pv310/include/mach/regs-clock.h
+++ b/arch/arm/mach-exynos4/include/mach/regs-clock.h
@@ -1,9 +1,9 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/regs-clock.h 1/* linux/arch/arm/mach-exynos4/include/mach/regs-clock.h
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * S5PV310 - Clock register definitions 6 * EXYNOS4 - Clock register definitions
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
@@ -17,13 +17,13 @@
17 17
18#define S5P_CLKREG(x) (S5P_VA_CMU + (x)) 18#define S5P_CLKREG(x) (S5P_VA_CMU + (x))
19 19
20#define S5P_INFORM0 S5P_CLKREG(0x800)
21
22#define S5P_CLKDIV_LEFTBUS S5P_CLKREG(0x04500) 20#define S5P_CLKDIV_LEFTBUS S5P_CLKREG(0x04500)
23#define S5P_CLKDIV_STAT_LEFTBUS S5P_CLKREG(0x04600) 21#define S5P_CLKDIV_STAT_LEFTBUS S5P_CLKREG(0x04600)
22#define S5P_CLKGATE_IP_LEFTBUS S5P_CLKREG(0x04800)
24 23
25#define S5P_CLKDIV_RIGHTBUS S5P_CLKREG(0x08500) 24#define S5P_CLKDIV_RIGHTBUS S5P_CLKREG(0x08500)
26#define S5P_CLKDIV_STAT_RIGHTBUS S5P_CLKREG(0x08600) 25#define S5P_CLKDIV_STAT_RIGHTBUS S5P_CLKREG(0x08600)
26#define S5P_CLKGATE_IP_RIGHTBUS S5P_CLKREG(0x08800)
27 27
28#define S5P_EPLL_CON0 S5P_CLKREG(0x0C110) 28#define S5P_EPLL_CON0 S5P_CLKREG(0x0C110)
29#define S5P_EPLL_CON1 S5P_CLKREG(0x0C114) 29#define S5P_EPLL_CON1 S5P_CLKREG(0x0C114)
@@ -33,18 +33,24 @@
33#define S5P_CLKSRC_TOP0 S5P_CLKREG(0x0C210) 33#define S5P_CLKSRC_TOP0 S5P_CLKREG(0x0C210)
34#define S5P_CLKSRC_TOP1 S5P_CLKREG(0x0C214) 34#define S5P_CLKSRC_TOP1 S5P_CLKREG(0x0C214)
35#define S5P_CLKSRC_CAM S5P_CLKREG(0x0C220) 35#define S5P_CLKSRC_CAM S5P_CLKREG(0x0C220)
36#define S5P_CLKSRC_MFC S5P_CLKREG(0x0C228)
36#define S5P_CLKSRC_IMAGE S5P_CLKREG(0x0C230) 37#define S5P_CLKSRC_IMAGE S5P_CLKREG(0x0C230)
37#define S5P_CLKSRC_LCD0 S5P_CLKREG(0x0C234) 38#define S5P_CLKSRC_LCD0 S5P_CLKREG(0x0C234)
38#define S5P_CLKSRC_LCD1 S5P_CLKREG(0x0C238) 39#define S5P_CLKSRC_LCD1 S5P_CLKREG(0x0C238)
40#define S5P_CLKSRC_MAUDIO S5P_CLKREG(0x0C23C)
39#define S5P_CLKSRC_FSYS S5P_CLKREG(0x0C240) 41#define S5P_CLKSRC_FSYS S5P_CLKREG(0x0C240)
40#define S5P_CLKSRC_PERIL0 S5P_CLKREG(0x0C250) 42#define S5P_CLKSRC_PERIL0 S5P_CLKREG(0x0C250)
41#define S5P_CLKSRC_PERIL1 S5P_CLKREG(0x0C254) 43#define S5P_CLKSRC_PERIL1 S5P_CLKREG(0x0C254)
42 44
43#define S5P_CLKDIV_TOP S5P_CLKREG(0x0C510) 45#define S5P_CLKDIV_TOP S5P_CLKREG(0x0C510)
44#define S5P_CLKDIV_CAM S5P_CLKREG(0x0C520) 46#define S5P_CLKDIV_CAM S5P_CLKREG(0x0C520)
47#define S5P_CLKDIV_TV S5P_CLKREG(0x0C524)
48#define S5P_CLKDIV_MFC S5P_CLKREG(0x0C528)
49#define S5P_CLKDIV_G3D S5P_CLKREG(0x0C52C)
45#define S5P_CLKDIV_IMAGE S5P_CLKREG(0x0C530) 50#define S5P_CLKDIV_IMAGE S5P_CLKREG(0x0C530)
46#define S5P_CLKDIV_LCD0 S5P_CLKREG(0x0C534) 51#define S5P_CLKDIV_LCD0 S5P_CLKREG(0x0C534)
47#define S5P_CLKDIV_LCD1 S5P_CLKREG(0x0C538) 52#define S5P_CLKDIV_LCD1 S5P_CLKREG(0x0C538)
53#define S5P_CLKDIV_MAUDIO S5P_CLKREG(0x0C53C)
48#define S5P_CLKDIV_FSYS0 S5P_CLKREG(0x0C540) 54#define S5P_CLKDIV_FSYS0 S5P_CLKREG(0x0C540)
49#define S5P_CLKDIV_FSYS1 S5P_CLKREG(0x0C544) 55#define S5P_CLKDIV_FSYS1 S5P_CLKREG(0x0C544)
50#define S5P_CLKDIV_FSYS2 S5P_CLKREG(0x0C548) 56#define S5P_CLKDIV_FSYS2 S5P_CLKREG(0x0C548)
@@ -58,25 +64,36 @@
58 64
59#define S5P_CLKSRC_MASK_TOP S5P_CLKREG(0x0C310) 65#define S5P_CLKSRC_MASK_TOP S5P_CLKREG(0x0C310)
60#define S5P_CLKSRC_MASK_CAM S5P_CLKREG(0x0C320) 66#define S5P_CLKSRC_MASK_CAM S5P_CLKREG(0x0C320)
67#define S5P_CLKSRC_MASK_TV S5P_CLKREG(0x0C324)
61#define S5P_CLKSRC_MASK_LCD0 S5P_CLKREG(0x0C334) 68#define S5P_CLKSRC_MASK_LCD0 S5P_CLKREG(0x0C334)
62#define S5P_CLKSRC_MASK_LCD1 S5P_CLKREG(0x0C338) 69#define S5P_CLKSRC_MASK_LCD1 S5P_CLKREG(0x0C338)
70#define S5P_CLKSRC_MASK_MAUDIO S5P_CLKREG(0x0C33C)
63#define S5P_CLKSRC_MASK_FSYS S5P_CLKREG(0x0C340) 71#define S5P_CLKSRC_MASK_FSYS S5P_CLKREG(0x0C340)
64#define S5P_CLKSRC_MASK_PERIL0 S5P_CLKREG(0x0C350) 72#define S5P_CLKSRC_MASK_PERIL0 S5P_CLKREG(0x0C350)
65#define S5P_CLKSRC_MASK_PERIL1 S5P_CLKREG(0x0C354) 73#define S5P_CLKSRC_MASK_PERIL1 S5P_CLKREG(0x0C354)
66 74
67#define S5P_CLKDIV_STAT_TOP S5P_CLKREG(0x0C610) 75#define S5P_CLKDIV_STAT_TOP S5P_CLKREG(0x0C610)
68 76
77#define S5P_CLKGATE_SCLKCAM S5P_CLKREG(0x0C820)
69#define S5P_CLKGATE_IP_CAM S5P_CLKREG(0x0C920) 78#define S5P_CLKGATE_IP_CAM S5P_CLKREG(0x0C920)
79#define S5P_CLKGATE_IP_TV S5P_CLKREG(0x0C924)
80#define S5P_CLKGATE_IP_MFC S5P_CLKREG(0x0C928)
81#define S5P_CLKGATE_IP_G3D S5P_CLKREG(0x0C92C)
70#define S5P_CLKGATE_IP_IMAGE S5P_CLKREG(0x0C930) 82#define S5P_CLKGATE_IP_IMAGE S5P_CLKREG(0x0C930)
71#define S5P_CLKGATE_IP_LCD0 S5P_CLKREG(0x0C934) 83#define S5P_CLKGATE_IP_LCD0 S5P_CLKREG(0x0C934)
72#define S5P_CLKGATE_IP_LCD1 S5P_CLKREG(0x0C938) 84#define S5P_CLKGATE_IP_LCD1 S5P_CLKREG(0x0C938)
73#define S5P_CLKGATE_IP_FSYS S5P_CLKREG(0x0C940) 85#define S5P_CLKGATE_IP_FSYS S5P_CLKREG(0x0C940)
86#define S5P_CLKGATE_IP_GPS S5P_CLKREG(0x0C94C)
74#define S5P_CLKGATE_IP_PERIL S5P_CLKREG(0x0C950) 87#define S5P_CLKGATE_IP_PERIL S5P_CLKREG(0x0C950)
75#define S5P_CLKGATE_IP_PERIR S5P_CLKREG(0x0C960) 88#define S5P_CLKGATE_IP_PERIR S5P_CLKREG(0x0C960)
89#define S5P_CLKGATE_BLOCK S5P_CLKREG(0x0C970)
76 90
91#define S5P_CLKSRC_MASK_DMC S5P_CLKREG(0x10300)
77#define S5P_CLKSRC_DMC S5P_CLKREG(0x10200) 92#define S5P_CLKSRC_DMC S5P_CLKREG(0x10200)
78#define S5P_CLKDIV_DMC0 S5P_CLKREG(0x10500) 93#define S5P_CLKDIV_DMC0 S5P_CLKREG(0x10500)
94#define S5P_CLKDIV_DMC1 S5P_CLKREG(0x10504)
79#define S5P_CLKDIV_STAT_DMC0 S5P_CLKREG(0x10600) 95#define S5P_CLKDIV_STAT_DMC0 S5P_CLKREG(0x10600)
96#define S5P_CLKGATE_IP_DMC S5P_CLKREG(0x10900)
80 97
81#define S5P_APLL_LOCK S5P_CLKREG(0x14000) 98#define S5P_APLL_LOCK S5P_CLKREG(0x14000)
82#define S5P_MPLL_LOCK S5P_CLKREG(0x14004) 99#define S5P_MPLL_LOCK S5P_CLKREG(0x14004)
@@ -94,21 +111,18 @@
94#define S5P_CLKDIV_STATCPU1 S5P_CLKREG(0x14604) 111#define S5P_CLKDIV_STATCPU1 S5P_CLKREG(0x14604)
95 112
96#define S5P_CLKGATE_SCLKCPU S5P_CLKREG(0x14800) 113#define S5P_CLKGATE_SCLKCPU S5P_CLKREG(0x14800)
114#define S5P_CLKGATE_IP_CPU S5P_CLKREG(0x14900)
97 115
98/* APLL_LOCK */
99#define S5P_APLL_LOCKTIME (0x1C20) /* 300us */ 116#define S5P_APLL_LOCKTIME (0x1C20) /* 300us */
100 117
101/* APLL_CON0 */
102#define S5P_APLLCON0_ENABLE_SHIFT (31) 118#define S5P_APLLCON0_ENABLE_SHIFT (31)
103#define S5P_APLLCON0_LOCKED_SHIFT (29) 119#define S5P_APLLCON0_LOCKED_SHIFT (29)
104#define S5P_APLL_VAL_1000 ((250 << 16) | (6 << 8) | 1) 120#define S5P_APLL_VAL_1000 ((250 << 16) | (6 << 8) | 1)
105#define S5P_APLL_VAL_800 ((200 << 16) | (6 << 8) | 1) 121#define S5P_APLL_VAL_800 ((200 << 16) | (6 << 8) | 1)
106 122
107/* CLK_SRC_CPU */
108#define S5P_CLKSRC_CPU_MUXCORE_SHIFT (16) 123#define S5P_CLKSRC_CPU_MUXCORE_SHIFT (16)
109#define S5P_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << S5P_CLKSRC_CPU_MUXCORE_SHIFT) 124#define S5P_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << S5P_CLKSRC_CPU_MUXCORE_SHIFT)
110 125
111/* CLKDIV_CPU0 */
112#define S5P_CLKDIV_CPU0_CORE_SHIFT (0) 126#define S5P_CLKDIV_CPU0_CORE_SHIFT (0)
113#define S5P_CLKDIV_CPU0_CORE_MASK (0x7 << S5P_CLKDIV_CPU0_CORE_SHIFT) 127#define S5P_CLKDIV_CPU0_CORE_MASK (0x7 << S5P_CLKDIV_CPU0_CORE_SHIFT)
114#define S5P_CLKDIV_CPU0_COREM0_SHIFT (4) 128#define S5P_CLKDIV_CPU0_COREM0_SHIFT (4)
@@ -124,7 +138,6 @@
124#define S5P_CLKDIV_CPU0_APLL_SHIFT (24) 138#define S5P_CLKDIV_CPU0_APLL_SHIFT (24)
125#define S5P_CLKDIV_CPU0_APLL_MASK (0x7 << S5P_CLKDIV_CPU0_APLL_SHIFT) 139#define S5P_CLKDIV_CPU0_APLL_MASK (0x7 << S5P_CLKDIV_CPU0_APLL_SHIFT)
126 140
127/* CLKDIV_DMC0 */
128#define S5P_CLKDIV_DMC0_ACP_SHIFT (0) 141#define S5P_CLKDIV_DMC0_ACP_SHIFT (0)
129#define S5P_CLKDIV_DMC0_ACP_MASK (0x7 << S5P_CLKDIV_DMC0_ACP_SHIFT) 142#define S5P_CLKDIV_DMC0_ACP_MASK (0x7 << S5P_CLKDIV_DMC0_ACP_SHIFT)
130#define S5P_CLKDIV_DMC0_ACPPCLK_SHIFT (4) 143#define S5P_CLKDIV_DMC0_ACPPCLK_SHIFT (4)
@@ -142,7 +155,6 @@
142#define S5P_CLKDIV_DMC0_CORETI_SHIFT (28) 155#define S5P_CLKDIV_DMC0_CORETI_SHIFT (28)
143#define S5P_CLKDIV_DMC0_CORETI_MASK (0x7 << S5P_CLKDIV_DMC0_CORETI_SHIFT) 156#define S5P_CLKDIV_DMC0_CORETI_MASK (0x7 << S5P_CLKDIV_DMC0_CORETI_SHIFT)
144 157
145/* CLKDIV_TOP */
146#define S5P_CLKDIV_TOP_ACLK200_SHIFT (0) 158#define S5P_CLKDIV_TOP_ACLK200_SHIFT (0)
147#define S5P_CLKDIV_TOP_ACLK200_MASK (0x7 << S5P_CLKDIV_TOP_ACLK200_SHIFT) 159#define S5P_CLKDIV_TOP_ACLK200_MASK (0x7 << S5P_CLKDIV_TOP_ACLK200_SHIFT)
148#define S5P_CLKDIV_TOP_ACLK100_SHIFT (4) 160#define S5P_CLKDIV_TOP_ACLK100_SHIFT (4)
@@ -154,13 +166,14 @@
154#define S5P_CLKDIV_TOP_ONENAND_SHIFT (16) 166#define S5P_CLKDIV_TOP_ONENAND_SHIFT (16)
155#define S5P_CLKDIV_TOP_ONENAND_MASK (0x7 << S5P_CLKDIV_TOP_ONENAND_SHIFT) 167#define S5P_CLKDIV_TOP_ONENAND_MASK (0x7 << S5P_CLKDIV_TOP_ONENAND_SHIFT)
156 168
157/* CLKDIV_LEFTBUS / CLKDIV_RIGHTBUS*/
158#define S5P_CLKDIV_BUS_GDLR_SHIFT (0) 169#define S5P_CLKDIV_BUS_GDLR_SHIFT (0)
159#define S5P_CLKDIV_BUS_GDLR_MASK (0x7 << S5P_CLKDIV_BUS_GDLR_SHIFT) 170#define S5P_CLKDIV_BUS_GDLR_MASK (0x7 << S5P_CLKDIV_BUS_GDLR_SHIFT)
160#define S5P_CLKDIV_BUS_GPLR_SHIFT (4) 171#define S5P_CLKDIV_BUS_GPLR_SHIFT (4)
161#define S5P_CLKDIV_BUS_GPLR_MASK (0x7 << S5P_CLKDIV_BUS_GPLR_SHIFT) 172#define S5P_CLKDIV_BUS_GPLR_MASK (0x7 << S5P_CLKDIV_BUS_GPLR_SHIFT)
162 173
163/* Compatibility defines */ 174/* Compatibility defines and inclusion */
175
176#include <mach/regs-pmu.h>
164 177
165#define S5P_EPLL_CON S5P_EPLL_CON0 178#define S5P_EPLL_CON S5P_EPLL_CON0
166 179
diff --git a/arch/arm/mach-exynos4/include/mach/regs-gpio.h b/arch/arm/mach-exynos4/include/mach/regs-gpio.h
new file mode 100644
index 000000000000..1401b21663a5
--- /dev/null
+++ b/arch/arm/mach-exynos4/include/mach/regs-gpio.h
@@ -0,0 +1,42 @@
1/* linux/arch/arm/mach-exynos4/include/mach/regs-gpio.h
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS4 - GPIO (including EINT) register definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_REGS_GPIO_H
14#define __ASM_ARCH_REGS_GPIO_H __FILE__
15
16#include <mach/map.h>
17#include <mach/irqs.h>
18
19#define EXYNOS4_EINT40CON (S5P_VA_GPIO2 + 0xE00)
20#define S5P_EINT_CON(x) (EXYNOS4_EINT40CON + ((x) * 0x4))
21
22#define EXYNOS4_EINT40FLTCON0 (S5P_VA_GPIO2 + 0xE80)
23#define S5P_EINT_FLTCON(x) (EXYNOS4_EINT40FLTCON0 + ((x) * 0x4))
24
25#define EXYNOS4_EINT40MASK (S5P_VA_GPIO2 + 0xF00)
26#define S5P_EINT_MASK(x) (EXYNOS4_EINT40MASK + ((x) * 0x4))
27
28#define EXYNOS4_EINT40PEND (S5P_VA_GPIO2 + 0xF40)
29#define S5P_EINT_PEND(x) (EXYNOS4_EINT40PEND + ((x) * 0x4))
30
31#define EINT_REG_NR(x) (EINT_OFFSET(x) >> 3)
32
33#define eint_irq_to_bit(irq) (1 << (EINT_OFFSET(irq) & 0x7))
34
35#define EINT_MODE S3C_GPIO_SFN(0xf)
36
37#define EINT_GPIO_0(x) EXYNOS4_GPX0(x)
38#define EINT_GPIO_1(x) EXYNOS4_GPX1(x)
39#define EINT_GPIO_2(x) EXYNOS4_GPX2(x)
40#define EINT_GPIO_3(x) EXYNOS4_GPX3(x)
41
42#endif /* __ASM_ARCH_REGS_GPIO_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/regs-irq.h b/arch/arm/mach-exynos4/include/mach/regs-irq.h
index c6e09c7f9161..9c7b4bfd546f 100644
--- a/arch/arm/mach-s5pv310/include/mach/regs-irq.h
+++ b/arch/arm/mach-exynos4/include/mach/regs-irq.h
@@ -1,9 +1,9 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/regs-irq.h 1/* linux/arch/arm/mach-exynos4/include/mach/regs-irq.h
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * S5PV310 - IRQ register definitions 6 * EXYNOS4 - IRQ register definitions
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/mach-exynos4/include/mach/regs-mct.h b/arch/arm/mach-exynos4/include/mach/regs-mct.h
new file mode 100644
index 000000000000..ca9c8434b023
--- /dev/null
+++ b/arch/arm/mach-exynos4/include/mach/regs-mct.h
@@ -0,0 +1,52 @@
1/* arch/arm/mach-exynos4/include/mach/regs-mct.h
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS4 MCT configutation
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_REGS_MCT_H
14#define __ASM_ARCH_REGS_MCT_H __FILE__
15
16#include <mach/map.h>
17
18#define EXYNOS4_MCTREG(x) (S5P_VA_SYSTIMER + (x))
19
20#define EXYNOS4_MCT_G_CNT_L EXYNOS4_MCTREG(0x100)
21#define EXYNOS4_MCT_G_CNT_U EXYNOS4_MCTREG(0x104)
22#define EXYNOS4_MCT_G_CNT_WSTAT EXYNOS4_MCTREG(0x110)
23
24#define EXYNOS4_MCT_G_COMP0_L EXYNOS4_MCTREG(0x200)
25#define EXYNOS4_MCT_G_COMP0_U EXYNOS4_MCTREG(0x204)
26#define EXYNOS4_MCT_G_COMP0_ADD_INCR EXYNOS4_MCTREG(0x208)
27
28#define EXYNOS4_MCT_G_TCON EXYNOS4_MCTREG(0x240)
29
30#define EXYNOS4_MCT_G_INT_CSTAT EXYNOS4_MCTREG(0x244)
31#define EXYNOS4_MCT_G_INT_ENB EXYNOS4_MCTREG(0x248)
32#define EXYNOS4_MCT_G_WSTAT EXYNOS4_MCTREG(0x24C)
33
34#define EXYNOS4_MCT_L0_BASE EXYNOS4_MCTREG(0x300)
35#define EXYNOS4_MCT_L1_BASE EXYNOS4_MCTREG(0x400)
36
37#define MCT_L_TCNTB_OFFSET (0x00)
38#define MCT_L_ICNTB_OFFSET (0x08)
39#define MCT_L_TCON_OFFSET (0x20)
40#define MCT_L_INT_CSTAT_OFFSET (0x30)
41#define MCT_L_INT_ENB_OFFSET (0x34)
42#define MCT_L_WSTAT_OFFSET (0x40)
43
44#define MCT_G_TCON_START (1 << 8)
45#define MCT_G_TCON_COMP0_AUTO_INC (1 << 1)
46#define MCT_G_TCON_COMP0_ENABLE (1 << 0)
47
48#define MCT_L_TCON_INTERVAL_MODE (1 << 2)
49#define MCT_L_TCON_INT_START (1 << 1)
50#define MCT_L_TCON_TIMER_START (1 << 0)
51
52#endif /* __ASM_ARCH_REGS_MCT_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/regs-mem.h b/arch/arm/mach-exynos4/include/mach/regs-mem.h
index 834227140eaa..0368b5a27252 100644
--- a/arch/arm/mach-s5pv310/include/mach/regs-mem.h
+++ b/arch/arm/mach-exynos4/include/mach/regs-mem.h
@@ -1,9 +1,9 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/regs-mem.h 1/* linux/arch/arm/mach-exynos4/include/mach/regs-mem.h
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com 4 * http://www.samsung.com
5 * 5 *
6 * S5PV310 - SROMC and DMC register definitions 6 * EXYNOS4 - SROMC and DMC register definitions
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/mach-exynos4/include/mach/regs-pmu.h b/arch/arm/mach-exynos4/include/mach/regs-pmu.h
new file mode 100644
index 000000000000..62b0014d05e0
--- /dev/null
+++ b/arch/arm/mach-exynos4/include/mach/regs-pmu.h
@@ -0,0 +1,162 @@
1/* linux/arch/arm/mach-exynos4/include/mach/regs-pmu.h
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS4 - Power management unit definition
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_REGS_PMU_H
14#define __ASM_ARCH_REGS_PMU_H __FILE__
15
16#include <mach/map.h>
17
18#define S5P_PMUREG(x) (S5P_VA_PMU + (x))
19
20#define S5P_CENTRAL_SEQ_CONFIGURATION S5P_PMUREG(0x0200)
21
22#define S5P_CENTRAL_LOWPWR_CFG (1 << 16)
23
24#define S5P_CENTRAL_SEQ_OPTION S5P_PMUREG(0x0208)
25
26#define S5P_USE_STANDBY_WFI0 (1 << 16)
27#define S5P_USE_STANDBY_WFI1 (1 << 17)
28#define S5P_USE_STANDBY_WFE0 (1 << 24)
29#define S5P_USE_STANDBY_WFE1 (1 << 25)
30#define S5P_USE_MASK ((0x3 << 16) | (0x3 << 24))
31
32#define S5P_WAKEUP_STAT S5P_PMUREG(0x0600)
33#define S5P_EINT_WAKEUP_MASK S5P_PMUREG(0x0604)
34#define S5P_WAKEUP_MASK S5P_PMUREG(0x0608)
35
36#define S5P_MIPI_DPHY_CONTROL(n) S5P_PMUREG(0x0710 + (n) * 4)
37#define S5P_MIPI_DPHY_ENABLE (1 << 0)
38#define S5P_MIPI_DPHY_SRESETN (1 << 1)
39#define S5P_MIPI_DPHY_MRESETN (1 << 2)
40
41#define S5P_PMU_SATA_PHY_CONTROL S5P_PMUREG(0x0720)
42#define S5P_INFORM0 S5P_PMUREG(0x0800)
43#define S5P_INFORM1 S5P_PMUREG(0x0804)
44#define S5P_INFORM2 S5P_PMUREG(0x0808)
45#define S5P_INFORM3 S5P_PMUREG(0x080C)
46#define S5P_INFORM4 S5P_PMUREG(0x0810)
47#define S5P_INFORM5 S5P_PMUREG(0x0814)
48#define S5P_INFORM6 S5P_PMUREG(0x0818)
49#define S5P_INFORM7 S5P_PMUREG(0x081C)
50
51#define S5P_ARM_CORE0_LOWPWR S5P_PMUREG(0x1000)
52#define S5P_DIS_IRQ_CORE0 S5P_PMUREG(0x1004)
53#define S5P_DIS_IRQ_CENTRAL0 S5P_PMUREG(0x1008)
54#define S5P_ARM_CORE1_LOWPWR S5P_PMUREG(0x1010)
55#define S5P_DIS_IRQ_CORE1 S5P_PMUREG(0x1014)
56#define S5P_DIS_IRQ_CENTRAL1 S5P_PMUREG(0x1018)
57#define S5P_ARM_COMMON_LOWPWR S5P_PMUREG(0x1080)
58#define S5P_L2_0_LOWPWR S5P_PMUREG(0x10C0)
59#define S5P_L2_1_LOWPWR S5P_PMUREG(0x10C4)
60#define S5P_CMU_ACLKSTOP_LOWPWR S5P_PMUREG(0x1100)
61#define S5P_CMU_SCLKSTOP_LOWPWR S5P_PMUREG(0x1104)
62#define S5P_CMU_RESET_LOWPWR S5P_PMUREG(0x110C)
63#define S5P_APLL_SYSCLK_LOWPWR S5P_PMUREG(0x1120)
64#define S5P_MPLL_SYSCLK_LOWPWR S5P_PMUREG(0x1124)
65#define S5P_VPLL_SYSCLK_LOWPWR S5P_PMUREG(0x1128)
66#define S5P_EPLL_SYSCLK_LOWPWR S5P_PMUREG(0x112C)
67#define S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR S5P_PMUREG(0x1138)
68#define S5P_CMU_RESET_GPSALIVE_LOWPWR S5P_PMUREG(0x113C)
69#define S5P_CMU_CLKSTOP_CAM_LOWPWR S5P_PMUREG(0x1140)
70#define S5P_CMU_CLKSTOP_TV_LOWPWR S5P_PMUREG(0x1144)
71#define S5P_CMU_CLKSTOP_MFC_LOWPWR S5P_PMUREG(0x1148)
72#define S5P_CMU_CLKSTOP_G3D_LOWPWR S5P_PMUREG(0x114C)
73#define S5P_CMU_CLKSTOP_LCD0_LOWPWR S5P_PMUREG(0x1150)
74#define S5P_CMU_CLKSTOP_LCD1_LOWPWR S5P_PMUREG(0x1154)
75#define S5P_CMU_CLKSTOP_MAUDIO_LOWPWR S5P_PMUREG(0x1158)
76#define S5P_CMU_CLKSTOP_GPS_LOWPWR S5P_PMUREG(0x115C)
77#define S5P_CMU_RESET_CAM_LOWPWR S5P_PMUREG(0x1160)
78#define S5P_CMU_RESET_TV_LOWPWR S5P_PMUREG(0x1164)
79#define S5P_CMU_RESET_MFC_LOWPWR S5P_PMUREG(0x1168)
80#define S5P_CMU_RESET_G3D_LOWPWR S5P_PMUREG(0x116C)
81#define S5P_CMU_RESET_LCD0_LOWPWR S5P_PMUREG(0x1170)
82#define S5P_CMU_RESET_LCD1_LOWPWR S5P_PMUREG(0x1174)
83#define S5P_CMU_RESET_MAUDIO_LOWPWR S5P_PMUREG(0x1178)
84#define S5P_CMU_RESET_GPS_LOWPWR S5P_PMUREG(0x117C)
85#define S5P_TOP_BUS_LOWPWR S5P_PMUREG(0x1180)
86#define S5P_TOP_RETENTION_LOWPWR S5P_PMUREG(0x1184)
87#define S5P_TOP_PWR_LOWPWR S5P_PMUREG(0x1188)
88#define S5P_LOGIC_RESET_LOWPWR S5P_PMUREG(0x11A0)
89#define S5P_ONENAND_MEM_LOWPWR S5P_PMUREG(0x11C0)
90#define S5P_MODIMIF_MEM_LOWPWR S5P_PMUREG(0x11C4)
91#define S5P_G2D_ACP_MEM_LOWPWR S5P_PMUREG(0x11C8)
92#define S5P_USBOTG_MEM_LOWPWR S5P_PMUREG(0x11CC)
93#define S5P_HSMMC_MEM_LOWPWR S5P_PMUREG(0x11D0)
94#define S5P_CSSYS_MEM_LOWPWR S5P_PMUREG(0x11D4)
95#define S5P_SECSS_MEM_LOWPWR S5P_PMUREG(0x11D8)
96#define S5P_PCIE_MEM_LOWPWR S5P_PMUREG(0x11E0)
97#define S5P_SATA_MEM_LOWPWR S5P_PMUREG(0x11E4)
98#define S5P_PAD_RETENTION_DRAM_LOWPWR S5P_PMUREG(0x1200)
99#define S5P_PAD_RETENTION_MAUDIO_LOWPWR S5P_PMUREG(0x1204)
100#define S5P_PAD_RETENTION_GPIO_LOWPWR S5P_PMUREG(0x1220)
101#define S5P_PAD_RETENTION_UART_LOWPWR S5P_PMUREG(0x1224)
102#define S5P_PAD_RETENTION_MMCA_LOWPWR S5P_PMUREG(0x1228)
103#define S5P_PAD_RETENTION_MMCB_LOWPWR S5P_PMUREG(0x122C)
104#define S5P_PAD_RETENTION_EBIA_LOWPWR S5P_PMUREG(0x1230)
105#define S5P_PAD_RETENTION_EBIB_LOWPWR S5P_PMUREG(0x1234)
106#define S5P_PAD_RETENTION_ISOLATION_LOWPWR S5P_PMUREG(0x1240)
107#define S5P_PAD_RETENTION_ALV_SEL_LOWPWR S5P_PMUREG(0x1260)
108#define S5P_XUSBXTI_LOWPWR S5P_PMUREG(0x1280)
109#define S5P_XXTI_LOWPWR S5P_PMUREG(0x1284)
110#define S5P_EXT_REGULATOR_LOWPWR S5P_PMUREG(0x12C0)
111#define S5P_GPIO_MODE_LOWPWR S5P_PMUREG(0x1300)
112#define S5P_GPIO_MODE_MAUDIO_LOWPWR S5P_PMUREG(0x1340)
113#define S5P_CAM_LOWPWR S5P_PMUREG(0x1380)
114#define S5P_TV_LOWPWR S5P_PMUREG(0x1384)
115#define S5P_MFC_LOWPWR S5P_PMUREG(0x1388)
116#define S5P_G3D_LOWPWR S5P_PMUREG(0x138C)
117#define S5P_LCD0_LOWPWR S5P_PMUREG(0x1390)
118#define S5P_LCD1_LOWPWR S5P_PMUREG(0x1394)
119#define S5P_MAUDIO_LOWPWR S5P_PMUREG(0x1398)
120#define S5P_GPS_LOWPWR S5P_PMUREG(0x139C)
121#define S5P_GPS_ALIVE_LOWPWR S5P_PMUREG(0x13A0)
122
123#define S5P_ARM_CORE0_CONFIGURATION S5P_PMUREG(0x2000)
124#define S5P_ARM_CORE0_OPTION S5P_PMUREG(0x2008)
125#define S5P_ARM_CORE1_CONFIGURATION S5P_PMUREG(0x2080)
126#define S5P_ARM_CORE1_STATUS S5P_PMUREG(0x2084)
127#define S5P_ARM_CORE1_OPTION S5P_PMUREG(0x2088)
128
129#define S5P_ARM_COMMON_OPTION S5P_PMUREG(0x2408)
130#define S5P_TOP_PWR_OPTION S5P_PMUREG(0x2C48)
131#define S5P_CAM_OPTION S5P_PMUREG(0x3C08)
132#define S5P_TV_OPTION S5P_PMUREG(0x3C28)
133#define S5P_MFC_OPTION S5P_PMUREG(0x3C48)
134#define S5P_G3D_OPTION S5P_PMUREG(0x3C68)
135#define S5P_LCD0_OPTION S5P_PMUREG(0x3C88)
136#define S5P_LCD1_OPTION S5P_PMUREG(0x3CA8)
137#define S5P_MAUDIO_OPTION S5P_PMUREG(0x3CC8)
138#define S5P_GPS_OPTION S5P_PMUREG(0x3CE8)
139#define S5P_GPS_ALIVE_OPTION S5P_PMUREG(0x3D08)
140
141#define S5P_PAD_RET_MAUDIO_OPTION S5P_PMUREG(0x3028)
142#define S5P_PAD_RET_GPIO_OPTION S5P_PMUREG(0x3108)
143#define S5P_PAD_RET_UART_OPTION S5P_PMUREG(0x3128)
144#define S5P_PAD_RET_MMCA_OPTION S5P_PMUREG(0x3148)
145#define S5P_PAD_RET_MMCB_OPTION S5P_PMUREG(0x3168)
146#define S5P_PAD_RET_EBIA_OPTION S5P_PMUREG(0x3188)
147#define S5P_PAD_RET_EBIB_OPTION S5P_PMUREG(0x31A8)
148
149#define S5P_PMU_CAM_CONF S5P_PMUREG(0x3C00)
150#define S5P_PMU_TV_CONF S5P_PMUREG(0x3C20)
151#define S5P_PMU_MFC_CONF S5P_PMUREG(0x3C40)
152#define S5P_PMU_G3D_CONF S5P_PMUREG(0x3C60)
153#define S5P_PMU_LCD0_CONF S5P_PMUREG(0x3C80)
154#define S5P_PMU_LCD1_CONF S5P_PMUREG(0x3CA0)
155#define S5P_PMU_GPS_CONF S5P_PMUREG(0x3CE0)
156
157#define S5P_PMU_SATA_PHY_CONTROL_EN 0x1
158#define S5P_INT_LOCAL_PWR_EN 0x7
159
160#define S5P_CHECK_SLEEP 0x00000BAD
161
162#endif /* __ASM_ARCH_REGS_PMU_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/regs-sysmmu.h b/arch/arm/mach-exynos4/include/mach/regs-sysmmu.h
index 0b28e81a16f7..68ff6ad08a2b 100644
--- a/arch/arm/mach-s5pv310/include/mach/regs-sysmmu.h
+++ b/arch/arm/mach-exynos4/include/mach/regs-sysmmu.h
@@ -1,9 +1,9 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/regs-sysmmu.h 1/* linux/arch/arm/mach-exynos4/include/mach/regs-sysmmu.h
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com 4 * http://www.samsung.com
5 * 5 *
6 * S5PV310 - System MMU register 6 * EXYNOS4 - System MMU register
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
@@ -19,6 +19,10 @@
19#define S5P_MMU_FLUSH 0x00C 19#define S5P_MMU_FLUSH 0x00C
20#define S5P_PT_BASE_ADDR 0x014 20#define S5P_PT_BASE_ADDR 0x014
21#define S5P_INT_STATUS 0x018 21#define S5P_INT_STATUS 0x018
22#define S5P_INT_CLEAR 0x01C
22#define S5P_PAGE_FAULT_ADDR 0x024 23#define S5P_PAGE_FAULT_ADDR 0x024
24#define S5P_AW_FAULT_ADDR 0x028
25#define S5P_AR_FAULT_ADDR 0x02C
26#define S5P_DEFAULT_SLAVE_ADDR 0x030
23 27
24#endif /* __ASM_ARCH_REGS_SYSMMU_H */ 28#endif /* __ASM_ARCH_REGS_SYSMMU_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/smp.h b/arch/arm/mach-exynos4/include/mach/smp.h
index 393ccbd52c4a..a463dcebcfd3 100644
--- a/arch/arm/mach-s5pv310/include/mach/smp.h
+++ b/arch/arm/mach-exynos4/include/mach/smp.h
@@ -1,4 +1,4 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/smp.h 1/* linux/arch/arm/mach-exynos4/include/mach/smp.h
2 * 2 *
3 * Cloned from arch/arm/mach-realview/include/mach/smp.h 3 * Cloned from arch/arm/mach-realview/include/mach/smp.h
4*/ 4*/
diff --git a/arch/arm/mach-exynos4/include/mach/sysmmu.h b/arch/arm/mach-exynos4/include/mach/sysmmu.h
new file mode 100644
index 000000000000..6a5fbb534e82
--- /dev/null
+++ b/arch/arm/mach-exynos4/include/mach/sysmmu.h
@@ -0,0 +1,46 @@
1/* linux/arch/arm/mach-exynos4/include/mach/sysmmu.h
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Samsung sysmmu driver for EXYNOS4
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARM_ARCH_SYSMMU_H
14#define __ASM_ARM_ARCH_SYSMMU_H __FILE__
15
16enum exynos4_sysmmu_ips {
17 SYSMMU_MDMA,
18 SYSMMU_SSS,
19 SYSMMU_FIMC0,
20 SYSMMU_FIMC1,
21 SYSMMU_FIMC2,
22 SYSMMU_FIMC3,
23 SYSMMU_JPEG,
24 SYSMMU_FIMD0,
25 SYSMMU_FIMD1,
26 SYSMMU_PCIe,
27 SYSMMU_G2D,
28 SYSMMU_ROTATOR,
29 SYSMMU_MDMA2,
30 SYSMMU_TV,
31 SYSMMU_MFC_L,
32 SYSMMU_MFC_R,
33 EXYNOS4_SYSMMU_TOTAL_IPNUM,
34};
35
36#define S5P_SYSMMU_TOTAL_IPNUM EXYNOS4_SYSMMU_TOTAL_IPNUM
37
38extern const char *sysmmu_ips_name[EXYNOS4_SYSMMU_TOTAL_IPNUM];
39
40typedef enum exynos4_sysmmu_ips sysmmu_ips;
41
42void sysmmu_clk_init(struct device *dev, sysmmu_ips ips);
43void sysmmu_clk_enable(sysmmu_ips ips);
44void sysmmu_clk_disable(sysmmu_ips ips);
45
46#endif /* __ASM_ARM_ARCH_SYSMMU_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/system.h b/arch/arm/mach-exynos4/include/mach/system.h
index d10c009cf0f1..5e3220c18fc7 100644
--- a/arch/arm/mach-s5pv310/include/mach/system.h
+++ b/arch/arm/mach-exynos4/include/mach/system.h
@@ -1,9 +1,9 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/system.h 1/* linux/arch/arm/mach-exynos4/include/mach/system.h
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * S5PV310 - system support header 6 * EXYNOS4 - system support header
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/mach-s5pv310/include/mach/timex.h b/arch/arm/mach-exynos4/include/mach/timex.h
index bd2359b952b4..6d138750a708 100644
--- a/arch/arm/mach-s5pv310/include/mach/timex.h
+++ b/arch/arm/mach-exynos4/include/mach/timex.h
@@ -1,14 +1,14 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/timex.h 1/* linux/arch/arm/mach-exynos4/include/mach/timex.h
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * Copyright (c) 2003-2010 Simtec Electronics 6 * Copyright (c) 2003-2010 Simtec Electronics
7 * Ben Dooks <ben@simtec.co.uk> 7 * Ben Dooks <ben@simtec.co.uk>
8 * 8 *
9 * Based on arch/arm/mach-s5p6442/include/mach/timex.h 9 * Based on arch/arm/mach-s5p6442/include/mach/timex.h
10 * 10 *
11 * S5PV310 - time parameters 11 * EXYNOS4 - time parameters
12 * 12 *
13 * This program is free software; you can redistribute it and/or modify 13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as 14 * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/mach-s5pv310/include/mach/uncompress.h b/arch/arm/mach-exynos4/include/mach/uncompress.h
index 59593c1e2416..21d97bcd9acb 100644
--- a/arch/arm/mach-s5pv310/include/mach/uncompress.h
+++ b/arch/arm/mach-exynos4/include/mach/uncompress.h
@@ -1,9 +1,9 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/uncompress.h 1/* linux/arch/arm/mach-exynos4/include/mach/uncompress.h
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * S5PV310 - uncompress code 6 * EXYNOS4 - uncompress code
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/mach-s5pv310/include/mach/vmalloc.h b/arch/arm/mach-exynos4/include/mach/vmalloc.h
index 65759fb97581..284330e571d2 100644
--- a/arch/arm/mach-s5pv310/include/mach/vmalloc.h
+++ b/arch/arm/mach-exynos4/include/mach/vmalloc.h
@@ -1,7 +1,7 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/vmalloc.h 1/* linux/arch/arm/mach-exynos4/include/mach/vmalloc.h
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * Copyright 2010 Ben Dooks <ben-linux@fluff.org> 6 * Copyright 2010 Ben Dooks <ben-linux@fluff.org>
7 * 7 *
@@ -11,7 +11,7 @@
11 * it under the terms of the GNU General Public License version 2 as 11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation. 12 * published by the Free Software Foundation.
13 * 13 *
14 * S5PV310 vmalloc definition 14 * EXYNOS4 vmalloc definition
15*/ 15*/
16 16
17#ifndef __ASM_ARCH_VMALLOC_H 17#ifndef __ASM_ARCH_VMALLOC_H
diff --git a/arch/arm/mach-s5pv310/init.c b/arch/arm/mach-exynos4/init.c
index 182dcf42cfb4..cf91f50e43ab 100644
--- a/arch/arm/mach-s5pv310/init.c
+++ b/arch/arm/mach-exynos4/init.c
@@ -1,4 +1,4 @@
1/* linux/arch/arm/mach-s5pv310/init.c 1/* linux/arch/arm/mach-exynos4/init.c
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com/
@@ -14,7 +14,7 @@
14#include <plat/devs.h> 14#include <plat/devs.h>
15#include <plat/regs-serial.h> 15#include <plat/regs-serial.h>
16 16
17static struct s3c24xx_uart_clksrc s5pv310_serial_clocks[] = { 17static struct s3c24xx_uart_clksrc exynos4_serial_clocks[] = {
18 [0] = { 18 [0] = {
19 .name = "uclk1", 19 .name = "uclk1",
20 .divisor = 1, 20 .divisor = 1,
@@ -24,7 +24,7 @@ static struct s3c24xx_uart_clksrc s5pv310_serial_clocks[] = {
24}; 24};
25 25
26/* uart registration process */ 26/* uart registration process */
27void __init s5pv310_common_init_uarts(struct s3c2410_uartcfg *cfg, int no) 27void __init exynos4_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
28{ 28{
29 struct s3c2410_uartcfg *tcfg = cfg; 29 struct s3c2410_uartcfg *tcfg = cfg;
30 u32 ucnt; 30 u32 ucnt;
@@ -32,8 +32,8 @@ void __init s5pv310_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
32 for (ucnt = 0; ucnt < no; ucnt++, tcfg++) { 32 for (ucnt = 0; ucnt < no; ucnt++, tcfg++) {
33 if (!tcfg->clocks) { 33 if (!tcfg->clocks) {
34 tcfg->has_fracval = 1; 34 tcfg->has_fracval = 1;
35 tcfg->clocks = s5pv310_serial_clocks; 35 tcfg->clocks = exynos4_serial_clocks;
36 tcfg->clocks_size = ARRAY_SIZE(s5pv310_serial_clocks); 36 tcfg->clocks_size = ARRAY_SIZE(exynos4_serial_clocks);
37 } 37 }
38 } 38 }
39 39
diff --git a/arch/arm/mach-s5pv310/irq-combiner.c b/arch/arm/mach-exynos4/irq-combiner.c
index 1ea4a9e83bbe..31618d91ce15 100644
--- a/arch/arm/mach-s5pv310/irq-combiner.c
+++ b/arch/arm/mach-exynos4/irq-combiner.c
@@ -1,6 +1,6 @@
1/* linux/arch/arm/mach-s5pv310/irq-combiner.c 1/* linux/arch/arm/mach-exynos4/irq-combiner.c
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com 4 * http://www.samsung.com
5 * 5 *
6 * Based on arch/arm/common/gic.c 6 * Based on arch/arm/common/gic.c
diff --git a/arch/arm/mach-s5pv310/irq-eint.c b/arch/arm/mach-exynos4/irq-eint.c
index 477bd9e97f0f..4f7ad4a796e4 100644
--- a/arch/arm/mach-s5pv310/irq-eint.c
+++ b/arch/arm/mach-exynos4/irq-eint.c
@@ -1,9 +1,9 @@
1/* linux/arch/arm/mach-s5pv310/irq-eint.c 1/* linux/arch/arm/mach-exynos4/irq-eint.c
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com 4 * http://www.samsung.com
5 * 5 *
6 * S5PV310 - IRQ EINT support 6 * EXYNOS4 - IRQ EINT support
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
@@ -27,7 +27,7 @@ static DEFINE_SPINLOCK(eint_lock);
27 27
28static unsigned int eint0_15_data[16]; 28static unsigned int eint0_15_data[16];
29 29
30static unsigned int s5pv310_get_irq_nr(unsigned int number) 30static unsigned int exynos4_get_irq_nr(unsigned int number)
31{ 31{
32 u32 ret = 0; 32 u32 ret = 0;
33 33
@@ -48,7 +48,7 @@ static unsigned int s5pv310_get_irq_nr(unsigned int number)
48 return ret; 48 return ret;
49} 49}
50 50
51static inline void s5pv310_irq_eint_mask(struct irq_data *data) 51static inline void exynos4_irq_eint_mask(struct irq_data *data)
52{ 52{
53 u32 mask; 53 u32 mask;
54 54
@@ -59,7 +59,7 @@ static inline void s5pv310_irq_eint_mask(struct irq_data *data)
59 spin_unlock(&eint_lock); 59 spin_unlock(&eint_lock);
60} 60}
61 61
62static void s5pv310_irq_eint_unmask(struct irq_data *data) 62static void exynos4_irq_eint_unmask(struct irq_data *data)
63{ 63{
64 u32 mask; 64 u32 mask;
65 65
@@ -70,19 +70,19 @@ static void s5pv310_irq_eint_unmask(struct irq_data *data)
70 spin_unlock(&eint_lock); 70 spin_unlock(&eint_lock);
71} 71}
72 72
73static inline void s5pv310_irq_eint_ack(struct irq_data *data) 73static inline void exynos4_irq_eint_ack(struct irq_data *data)
74{ 74{
75 __raw_writel(eint_irq_to_bit(data->irq), 75 __raw_writel(eint_irq_to_bit(data->irq),
76 S5P_EINT_PEND(EINT_REG_NR(data->irq))); 76 S5P_EINT_PEND(EINT_REG_NR(data->irq)));
77} 77}
78 78
79static void s5pv310_irq_eint_maskack(struct irq_data *data) 79static void exynos4_irq_eint_maskack(struct irq_data *data)
80{ 80{
81 s5pv310_irq_eint_mask(data); 81 exynos4_irq_eint_mask(data);
82 s5pv310_irq_eint_ack(data); 82 exynos4_irq_eint_ack(data);
83} 83}
84 84
85static int s5pv310_irq_eint_set_type(struct irq_data *data, unsigned int type) 85static int exynos4_irq_eint_set_type(struct irq_data *data, unsigned int type)
86{ 86{
87 int offs = EINT_OFFSET(data->irq); 87 int offs = EINT_OFFSET(data->irq);
88 int shift; 88 int shift;
@@ -145,19 +145,19 @@ static int s5pv310_irq_eint_set_type(struct irq_data *data, unsigned int type)
145 return 0; 145 return 0;
146} 146}
147 147
148static struct irq_chip s5pv310_irq_eint = { 148static struct irq_chip exynos4_irq_eint = {
149 .name = "s5pv310-eint", 149 .name = "exynos4-eint",
150 .irq_mask = s5pv310_irq_eint_mask, 150 .irq_mask = exynos4_irq_eint_mask,
151 .irq_unmask = s5pv310_irq_eint_unmask, 151 .irq_unmask = exynos4_irq_eint_unmask,
152 .irq_mask_ack = s5pv310_irq_eint_maskack, 152 .irq_mask_ack = exynos4_irq_eint_maskack,
153 .irq_ack = s5pv310_irq_eint_ack, 153 .irq_ack = exynos4_irq_eint_ack,
154 .irq_set_type = s5pv310_irq_eint_set_type, 154 .irq_set_type = exynos4_irq_eint_set_type,
155#ifdef CONFIG_PM 155#ifdef CONFIG_PM
156 .irq_set_wake = s3c_irqext_wake, 156 .irq_set_wake = s3c_irqext_wake,
157#endif 157#endif
158}; 158};
159 159
160/* s5pv310_irq_demux_eint 160/* exynos4_irq_demux_eint
161 * 161 *
162 * This function demuxes the IRQ from from EINTs 16 to 31. 162 * This function demuxes the IRQ from from EINTs 16 to 31.
163 * It is designed to be inlined into the specific handler 163 * It is designed to be inlined into the specific handler
@@ -165,7 +165,7 @@ static struct irq_chip s5pv310_irq_eint = {
165 * 165 *
166 * Each EINT pend/mask registers handle eight of them. 166 * Each EINT pend/mask registers handle eight of them.
167 */ 167 */
168static inline void s5pv310_irq_demux_eint(unsigned int start) 168static inline void exynos4_irq_demux_eint(unsigned int start)
169{ 169{
170 unsigned int irq; 170 unsigned int irq;
171 171
@@ -182,13 +182,13 @@ static inline void s5pv310_irq_demux_eint(unsigned int start)
182 } 182 }
183} 183}
184 184
185static void s5pv310_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc) 185static void exynos4_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
186{ 186{
187 s5pv310_irq_demux_eint(IRQ_EINT(16)); 187 exynos4_irq_demux_eint(IRQ_EINT(16));
188 s5pv310_irq_demux_eint(IRQ_EINT(24)); 188 exynos4_irq_demux_eint(IRQ_EINT(24));
189} 189}
190 190
191static void s5pv310_irq_eint0_15(unsigned int irq, struct irq_desc *desc) 191static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
192{ 192{
193 u32 *irq_data = get_irq_data(irq); 193 u32 *irq_data = get_irq_data(irq);
194 struct irq_chip *chip = get_irq_chip(irq); 194 struct irq_chip *chip = get_irq_chip(irq);
@@ -203,27 +203,27 @@ static void s5pv310_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
203 chip->irq_unmask(&desc->irq_data); 203 chip->irq_unmask(&desc->irq_data);
204} 204}
205 205
206int __init s5pv310_init_irq_eint(void) 206int __init exynos4_init_irq_eint(void)
207{ 207{
208 int irq; 208 int irq;
209 209
210 for (irq = 0 ; irq <= 31 ; irq++) { 210 for (irq = 0 ; irq <= 31 ; irq++) {
211 set_irq_chip(IRQ_EINT(irq), &s5pv310_irq_eint); 211 set_irq_chip(IRQ_EINT(irq), &exynos4_irq_eint);
212 set_irq_handler(IRQ_EINT(irq), handle_level_irq); 212 set_irq_handler(IRQ_EINT(irq), handle_level_irq);
213 set_irq_flags(IRQ_EINT(irq), IRQF_VALID); 213 set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
214 } 214 }
215 215
216 set_irq_chained_handler(IRQ_EINT16_31, s5pv310_irq_demux_eint16_31); 216 set_irq_chained_handler(IRQ_EINT16_31, exynos4_irq_demux_eint16_31);
217 217
218 for (irq = 0 ; irq <= 15 ; irq++) { 218 for (irq = 0 ; irq <= 15 ; irq++) {
219 eint0_15_data[irq] = IRQ_EINT(irq); 219 eint0_15_data[irq] = IRQ_EINT(irq);
220 220
221 set_irq_data(s5pv310_get_irq_nr(irq), &eint0_15_data[irq]); 221 set_irq_data(exynos4_get_irq_nr(irq), &eint0_15_data[irq]);
222 set_irq_chained_handler(s5pv310_get_irq_nr(irq), 222 set_irq_chained_handler(exynos4_get_irq_nr(irq),
223 s5pv310_irq_eint0_15); 223 exynos4_irq_eint0_15);
224 } 224 }
225 225
226 return 0; 226 return 0;
227} 227}
228 228
229arch_initcall(s5pv310_init_irq_eint); 229arch_initcall(exynos4_init_irq_eint);
diff --git a/arch/arm/mach-s5pv310/localtimer.c b/arch/arm/mach-exynos4/localtimer.c
index 2784036cd8b1..2a2993ae8d86 100644
--- a/arch/arm/mach-s5pv310/localtimer.c
+++ b/arch/arm/mach-exynos4/localtimer.c
@@ -1,4 +1,4 @@
1/* linux/arch/arm/mach-s5pv310/localtimer.c 1/* linux/arch/arm/mach-exynos4/localtimer.c
2 * 2 *
3 * Cloned from linux/arch/arm/mach-realview/localtimer.c 3 * Cloned from linux/arch/arm/mach-realview/localtimer.c
4 * 4 *
diff --git a/arch/arm/mach-exynos4/mach-armlex4210.c b/arch/arm/mach-exynos4/mach-armlex4210.c
new file mode 100644
index 000000000000..b482c6285fc4
--- /dev/null
+++ b/arch/arm/mach-exynos4/mach-armlex4210.c
@@ -0,0 +1,215 @@
1/* linux/arch/arm/mach-exynos4/mach-armlex4210.c
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#include <linux/gpio.h>
12#include <linux/io.h>
13#include <linux/mmc/host.h>
14#include <linux/platform_device.h>
15#include <linux/serial_core.h>
16#include <linux/smsc911x.h>
17
18#include <asm/mach/arch.h>
19#include <asm/mach-types.h>
20
21#include <plat/cpu.h>
22#include <plat/devs.h>
23#include <plat/exynos4.h>
24#include <plat/gpio-cfg.h>
25#include <plat/regs-serial.h>
26#include <plat/regs-srom.h>
27#include <plat/sdhci.h>
28
29#include <mach/map.h>
30
31/* Following are default values for UCON, ULCON and UFCON UART registers */
32#define ARMLEX4210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
33 S3C2410_UCON_RXILEVEL | \
34 S3C2410_UCON_TXIRQMODE | \
35 S3C2410_UCON_RXIRQMODE | \
36 S3C2410_UCON_RXFIFO_TOI | \
37 S3C2443_UCON_RXERR_IRQEN)
38
39#define ARMLEX4210_ULCON_DEFAULT S3C2410_LCON_CS8
40
41#define ARMLEX4210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
42 S5PV210_UFCON_TXTRIG4 | \
43 S5PV210_UFCON_RXTRIG4)
44
45static struct s3c2410_uartcfg armlex4210_uartcfgs[] __initdata = {
46 [0] = {
47 .hwport = 0,
48 .flags = 0,
49 .ucon = ARMLEX4210_UCON_DEFAULT,
50 .ulcon = ARMLEX4210_ULCON_DEFAULT,
51 .ufcon = ARMLEX4210_UFCON_DEFAULT,
52 },
53 [1] = {
54 .hwport = 1,
55 .flags = 0,
56 .ucon = ARMLEX4210_UCON_DEFAULT,
57 .ulcon = ARMLEX4210_ULCON_DEFAULT,
58 .ufcon = ARMLEX4210_UFCON_DEFAULT,
59 },
60 [2] = {
61 .hwport = 2,
62 .flags = 0,
63 .ucon = ARMLEX4210_UCON_DEFAULT,
64 .ulcon = ARMLEX4210_ULCON_DEFAULT,
65 .ufcon = ARMLEX4210_UFCON_DEFAULT,
66 },
67 [3] = {
68 .hwport = 3,
69 .flags = 0,
70 .ucon = ARMLEX4210_UCON_DEFAULT,
71 .ulcon = ARMLEX4210_ULCON_DEFAULT,
72 .ufcon = ARMLEX4210_UFCON_DEFAULT,
73 },
74};
75
76static struct s3c_sdhci_platdata armlex4210_hsmmc0_pdata __initdata = {
77 .cd_type = S3C_SDHCI_CD_PERMANENT,
78 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
79#ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT
80 .max_width = 8,
81 .host_caps = MMC_CAP_8_BIT_DATA,
82#endif
83};
84
85static struct s3c_sdhci_platdata armlex4210_hsmmc2_pdata __initdata = {
86 .cd_type = S3C_SDHCI_CD_GPIO,
87 .ext_cd_gpio = EXYNOS4_GPX2(5),
88 .ext_cd_gpio_invert = 1,
89 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
90 .max_width = 4,
91};
92
93static struct s3c_sdhci_platdata armlex4210_hsmmc3_pdata __initdata = {
94 .cd_type = S3C_SDHCI_CD_PERMANENT,
95 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
96 .max_width = 4,
97};
98
99static void __init armlex4210_sdhci_init(void)
100{
101 s3c_sdhci0_set_platdata(&armlex4210_hsmmc0_pdata);
102 s3c_sdhci2_set_platdata(&armlex4210_hsmmc2_pdata);
103 s3c_sdhci3_set_platdata(&armlex4210_hsmmc3_pdata);
104}
105
106static void __init armlex4210_wlan_init(void)
107{
108 /* enable */
109 s3c_gpio_cfgpin(EXYNOS4_GPX2(0), S3C_GPIO_SFN(0xf));
110 s3c_gpio_setpull(EXYNOS4_GPX2(0), S3C_GPIO_PULL_UP);
111
112 /* reset */
113 s3c_gpio_cfgpin(EXYNOS4_GPX1(6), S3C_GPIO_SFN(0xf));
114 s3c_gpio_setpull(EXYNOS4_GPX1(6), S3C_GPIO_PULL_UP);
115
116 /* wakeup */
117 s3c_gpio_cfgpin(EXYNOS4_GPX1(5), S3C_GPIO_SFN(0xf));
118 s3c_gpio_setpull(EXYNOS4_GPX1(5), S3C_GPIO_PULL_UP);
119}
120
121static struct resource armlex4210_smsc911x_resources[] = {
122 [0] = {
123 .start = EXYNOS4_PA_SROM_BANK(3),
124 .end = EXYNOS4_PA_SROM_BANK(3) + SZ_64K - 1,
125 .flags = IORESOURCE_MEM,
126 },
127 [1] = {
128 .start = IRQ_EINT(27),
129 .end = IRQ_EINT(27),
130 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_HIGH,
131 },
132};
133
134static struct smsc911x_platform_config smsc9215_config = {
135 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
136 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
137 .flags = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
138 .phy_interface = PHY_INTERFACE_MODE_MII,
139 .mac = {0x00, 0x80, 0x00, 0x23, 0x45, 0x67},
140};
141
142static struct platform_device armlex4210_smsc911x = {
143 .name = "smsc911x",
144 .id = -1,
145 .num_resources = ARRAY_SIZE(armlex4210_smsc911x_resources),
146 .resource = armlex4210_smsc911x_resources,
147 .dev = {
148 .platform_data = &smsc9215_config,
149 },
150};
151
152static struct platform_device *armlex4210_devices[] __initdata = {
153 &s3c_device_hsmmc0,
154 &s3c_device_hsmmc2,
155 &s3c_device_hsmmc3,
156 &s3c_device_rtc,
157 &s3c_device_wdt,
158 &exynos4_device_sysmmu,
159 &samsung_asoc_dma,
160 &armlex4210_smsc911x,
161 &exynos4_device_ahci,
162};
163
164static void __init armlex4210_smsc911x_init(void)
165{
166 u32 cs1;
167
168 /* configure nCS1 width to 16 bits */
169 cs1 = __raw_readl(S5P_SROM_BW) &
170 ~(S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS1__SHIFT);
171 cs1 |= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) |
172 (0 << S5P_SROM_BW__WAITENABLE__SHIFT) |
173 (1 << S5P_SROM_BW__ADDRMODE__SHIFT) |
174 (1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) <<
175 S5P_SROM_BW__NCS1__SHIFT;
176 __raw_writel(cs1, S5P_SROM_BW);
177
178 /* set timing for nCS1 suitable for ethernet chip */
179 __raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) |
180 (0x9 << S5P_SROM_BCX__TACP__SHIFT) |
181 (0xc << S5P_SROM_BCX__TCAH__SHIFT) |
182 (0x1 << S5P_SROM_BCX__TCOH__SHIFT) |
183 (0x6 << S5P_SROM_BCX__TACC__SHIFT) |
184 (0x1 << S5P_SROM_BCX__TCOS__SHIFT) |
185 (0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1);
186}
187
188static void __init armlex4210_map_io(void)
189{
190 s5p_init_io(NULL, 0, S5P_VA_CHIPID);
191 s3c24xx_init_clocks(24000000);
192 s3c24xx_init_uarts(armlex4210_uartcfgs,
193 ARRAY_SIZE(armlex4210_uartcfgs));
194}
195
196static void __init armlex4210_machine_init(void)
197{
198 armlex4210_smsc911x_init();
199
200 armlex4210_sdhci_init();
201
202 armlex4210_wlan_init();
203
204 platform_add_devices(armlex4210_devices,
205 ARRAY_SIZE(armlex4210_devices));
206}
207
208MACHINE_START(ARMLEX4210, "ARMLEX4210")
209 /* Maintainer: Alim Akhtar <alim.akhtar@samsung.com> */
210 .boot_params = S5P_PA_SDRAM + 0x100,
211 .init_irq = exynos4_init_irq,
212 .map_io = armlex4210_map_io,
213 .init_machine = armlex4210_machine_init,
214 .timer = &exynos4_timer,
215MACHINE_END
diff --git a/arch/arm/mach-exynos4/mach-nuri.c b/arch/arm/mach-exynos4/mach-nuri.c
new file mode 100644
index 000000000000..b79ad010d194
--- /dev/null
+++ b/arch/arm/mach-exynos4/mach-nuri.c
@@ -0,0 +1,305 @@
1/*
2 * linux/arch/arm/mach-exynos4/mach-nuri.c
3 *
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/platform_device.h>
12#include <linux/serial_core.h>
13#include <linux/input.h>
14#include <linux/i2c.h>
15#include <linux/gpio_keys.h>
16#include <linux/gpio.h>
17#include <linux/regulator/machine.h>
18#include <linux/regulator/fixed.h>
19#include <linux/mmc/host.h>
20#include <linux/fb.h>
21#include <linux/pwm_backlight.h>
22
23#include <video/platform_lcd.h>
24
25#include <asm/mach/arch.h>
26#include <asm/mach-types.h>
27
28#include <plat/regs-serial.h>
29#include <plat/exynos4.h>
30#include <plat/cpu.h>
31#include <plat/devs.h>
32#include <plat/sdhci.h>
33
34#include <mach/map.h>
35
36/* Following are default values for UCON, ULCON and UFCON UART registers */
37#define NURI_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
38 S3C2410_UCON_RXILEVEL | \
39 S3C2410_UCON_TXIRQMODE | \
40 S3C2410_UCON_RXIRQMODE | \
41 S3C2410_UCON_RXFIFO_TOI | \
42 S3C2443_UCON_RXERR_IRQEN)
43
44#define NURI_ULCON_DEFAULT S3C2410_LCON_CS8
45
46#define NURI_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
47 S5PV210_UFCON_TXTRIG256 | \
48 S5PV210_UFCON_RXTRIG256)
49
50enum fixed_regulator_id {
51 FIXED_REG_ID_MMC = 0,
52};
53
54static struct s3c2410_uartcfg nuri_uartcfgs[] __initdata = {
55 {
56 .hwport = 0,
57 .ucon = NURI_UCON_DEFAULT,
58 .ulcon = NURI_ULCON_DEFAULT,
59 .ufcon = NURI_UFCON_DEFAULT,
60 },
61 {
62 .hwport = 1,
63 .ucon = NURI_UCON_DEFAULT,
64 .ulcon = NURI_ULCON_DEFAULT,
65 .ufcon = NURI_UFCON_DEFAULT,
66 },
67 {
68 .hwport = 2,
69 .ucon = NURI_UCON_DEFAULT,
70 .ulcon = NURI_ULCON_DEFAULT,
71 .ufcon = NURI_UFCON_DEFAULT,
72 },
73 {
74 .hwport = 3,
75 .ucon = NURI_UCON_DEFAULT,
76 .ulcon = NURI_ULCON_DEFAULT,
77 .ufcon = NURI_UFCON_DEFAULT,
78 },
79};
80
81/* eMMC */
82static struct s3c_sdhci_platdata nuri_hsmmc0_data __initdata = {
83 .max_width = 8,
84 .host_caps = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
85 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
86 MMC_CAP_DISABLE | MMC_CAP_ERASE),
87 .cd_type = S3C_SDHCI_CD_PERMANENT,
88 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
89};
90
91static struct regulator_consumer_supply emmc_supplies[] = {
92 REGULATOR_SUPPLY("vmmc", "s3c-sdhci.0"),
93 REGULATOR_SUPPLY("vmmc", "dw_mmc"),
94};
95
96static struct regulator_init_data emmc_fixed_voltage_init_data = {
97 .constraints = {
98 .name = "VMEM_VDD_2.8V",
99 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
100 },
101 .num_consumer_supplies = ARRAY_SIZE(emmc_supplies),
102 .consumer_supplies = emmc_supplies,
103};
104
105static struct fixed_voltage_config emmc_fixed_voltage_config = {
106 .supply_name = "MASSMEMORY_EN (inverted)",
107 .microvolts = 2800000,
108 .gpio = EXYNOS4_GPL1(1),
109 .enable_high = false,
110 .init_data = &emmc_fixed_voltage_init_data,
111};
112
113static struct platform_device emmc_fixed_voltage = {
114 .name = "reg-fixed-voltage",
115 .id = FIXED_REG_ID_MMC,
116 .dev = {
117 .platform_data = &emmc_fixed_voltage_config,
118 },
119};
120
121/* SD */
122static struct s3c_sdhci_platdata nuri_hsmmc2_data __initdata = {
123 .max_width = 4,
124 .host_caps = MMC_CAP_4_BIT_DATA |
125 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
126 MMC_CAP_DISABLE,
127 .ext_cd_gpio = EXYNOS4_GPX3(3), /* XEINT_27 */
128 .ext_cd_gpio_invert = 1,
129 .cd_type = S3C_SDHCI_CD_GPIO,
130 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
131};
132
133/* WLAN */
134static struct s3c_sdhci_platdata nuri_hsmmc3_data __initdata = {
135 .max_width = 4,
136 .host_caps = MMC_CAP_4_BIT_DATA |
137 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
138 .cd_type = S3C_SDHCI_CD_EXTERNAL,
139 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
140};
141
142static void __init nuri_sdhci_init(void)
143{
144 s3c_sdhci0_set_platdata(&nuri_hsmmc0_data);
145 s3c_sdhci2_set_platdata(&nuri_hsmmc2_data);
146 s3c_sdhci3_set_platdata(&nuri_hsmmc3_data);
147}
148
149/* GPIO KEYS */
150static struct gpio_keys_button nuri_gpio_keys_tables[] = {
151 {
152 .code = KEY_VOLUMEUP,
153 .gpio = EXYNOS4_GPX2(0), /* XEINT16 */
154 .desc = "gpio-keys: KEY_VOLUMEUP",
155 .type = EV_KEY,
156 .active_low = 1,
157 .debounce_interval = 1,
158 }, {
159 .code = KEY_VOLUMEDOWN,
160 .gpio = EXYNOS4_GPX2(1), /* XEINT17 */
161 .desc = "gpio-keys: KEY_VOLUMEDOWN",
162 .type = EV_KEY,
163 .active_low = 1,
164 .debounce_interval = 1,
165 }, {
166 .code = KEY_POWER,
167 .gpio = EXYNOS4_GPX2(7), /* XEINT23 */
168 .desc = "gpio-keys: KEY_POWER",
169 .type = EV_KEY,
170 .active_low = 1,
171 .wakeup = 1,
172 .debounce_interval = 1,
173 },
174};
175
176static struct gpio_keys_platform_data nuri_gpio_keys_data = {
177 .buttons = nuri_gpio_keys_tables,
178 .nbuttons = ARRAY_SIZE(nuri_gpio_keys_tables),
179};
180
181static struct platform_device nuri_gpio_keys = {
182 .name = "gpio-keys",
183 .dev = {
184 .platform_data = &nuri_gpio_keys_data,
185 },
186};
187
188static void nuri_lcd_power_on(struct plat_lcd_data *pd, unsigned int power)
189{
190 int gpio = EXYNOS4_GPE1(5);
191
192 gpio_request(gpio, "LVDS_nSHDN");
193 gpio_direction_output(gpio, power);
194 gpio_free(gpio);
195}
196
197static int nuri_bl_init(struct device *dev)
198{
199 int ret, gpio = EXYNOS4_GPE2(3);
200
201 ret = gpio_request(gpio, "LCD_LDO_EN");
202 if (!ret)
203 gpio_direction_output(gpio, 0);
204
205 return ret;
206}
207
208static int nuri_bl_notify(struct device *dev, int brightness)
209{
210 if (brightness < 1)
211 brightness = 0;
212
213 gpio_set_value(EXYNOS4_GPE2(3), 1);
214
215 return brightness;
216}
217
218static void nuri_bl_exit(struct device *dev)
219{
220 gpio_free(EXYNOS4_GPE2(3));
221}
222
223/* nuri pwm backlight */
224static struct platform_pwm_backlight_data nuri_backlight_data = {
225 .pwm_id = 0,
226 .pwm_period_ns = 30000,
227 .max_brightness = 100,
228 .dft_brightness = 50,
229 .init = nuri_bl_init,
230 .notify = nuri_bl_notify,
231 .exit = nuri_bl_exit,
232};
233
234static struct platform_device nuri_backlight_device = {
235 .name = "pwm-backlight",
236 .id = -1,
237 .dev = {
238 .parent = &s3c_device_timer[0].dev,
239 .platform_data = &nuri_backlight_data,
240 },
241};
242
243static struct plat_lcd_data nuri_lcd_platform_data = {
244 .set_power = nuri_lcd_power_on,
245};
246
247static struct platform_device nuri_lcd_device = {
248 .name = "platform-lcd",
249 .id = -1,
250 .dev = {
251 .platform_data = &nuri_lcd_platform_data,
252 },
253};
254
255/* I2C1 */
256static struct i2c_board_info i2c1_devs[] __initdata = {
257 /* Gyro, To be updated */
258};
259
260/* GPIO I2C 5 (PMIC) */
261static struct i2c_board_info i2c5_devs[] __initdata = {
262 /* max8997, To be updated */
263};
264
265static struct platform_device *nuri_devices[] __initdata = {
266 /* Samsung Platform Devices */
267 &emmc_fixed_voltage,
268 &s3c_device_hsmmc0,
269 &s3c_device_hsmmc2,
270 &s3c_device_hsmmc3,
271 &s3c_device_wdt,
272 &s3c_device_timer[0],
273
274 /* NURI Devices */
275 &nuri_gpio_keys,
276 &nuri_lcd_device,
277 &nuri_backlight_device,
278};
279
280static void __init nuri_map_io(void)
281{
282 s5p_init_io(NULL, 0, S5P_VA_CHIPID);
283 s3c24xx_init_clocks(24000000);
284 s3c24xx_init_uarts(nuri_uartcfgs, ARRAY_SIZE(nuri_uartcfgs));
285}
286
287static void __init nuri_machine_init(void)
288{
289 nuri_sdhci_init();
290
291 i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
292 i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs));
293
294 /* Last */
295 platform_add_devices(nuri_devices, ARRAY_SIZE(nuri_devices));
296}
297
298MACHINE_START(NURI, "NURI")
299 /* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */
300 .boot_params = S5P_PA_SDRAM + 0x100,
301 .init_irq = exynos4_init_irq,
302 .map_io = nuri_map_io,
303 .init_machine = nuri_machine_init,
304 .timer = &exynos4_timer,
305MACHINE_END
diff --git a/arch/arm/mach-s5pv310/mach-smdkc210.c b/arch/arm/mach-exynos4/mach-smdkc210.c
index d9cab02e23ca..25a256818122 100644
--- a/arch/arm/mach-s5pv310/mach-smdkc210.c
+++ b/arch/arm/mach-exynos4/mach-smdkc210.c
@@ -1,7 +1,7 @@
1/* linux/arch/arm/mach-s5pv310/mach-smdkc210.c 1/* linux/arch/arm/mach-exynos4/mach-smdkc210.c
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as 7 * it under the terms of the GNU General Public License version 2 as
@@ -21,7 +21,7 @@
21 21
22#include <plat/regs-serial.h> 22#include <plat/regs-serial.h>
23#include <plat/regs-srom.h> 23#include <plat/regs-srom.h>
24#include <plat/s5pv310.h> 24#include <plat/exynos4.h>
25#include <plat/cpu.h> 25#include <plat/cpu.h>
26#include <plat/devs.h> 26#include <plat/devs.h>
27#include <plat/sdhci.h> 27#include <plat/sdhci.h>
@@ -77,10 +77,10 @@ static struct s3c2410_uartcfg smdkc210_uartcfgs[] __initdata = {
77 77
78static struct s3c_sdhci_platdata smdkc210_hsmmc0_pdata __initdata = { 78static struct s3c_sdhci_platdata smdkc210_hsmmc0_pdata __initdata = {
79 .cd_type = S3C_SDHCI_CD_GPIO, 79 .cd_type = S3C_SDHCI_CD_GPIO,
80 .ext_cd_gpio = S5PV310_GPK0(2), 80 .ext_cd_gpio = EXYNOS4_GPK0(2),
81 .ext_cd_gpio_invert = 1, 81 .ext_cd_gpio_invert = 1,
82 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, 82 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
83#ifdef CONFIG_S5PV310_SDHCI_CH0_8BIT 83#ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT
84 .max_width = 8, 84 .max_width = 8,
85 .host_caps = MMC_CAP_8_BIT_DATA, 85 .host_caps = MMC_CAP_8_BIT_DATA,
86#endif 86#endif
@@ -88,17 +88,17 @@ static struct s3c_sdhci_platdata smdkc210_hsmmc0_pdata __initdata = {
88 88
89static struct s3c_sdhci_platdata smdkc210_hsmmc1_pdata __initdata = { 89static struct s3c_sdhci_platdata smdkc210_hsmmc1_pdata __initdata = {
90 .cd_type = S3C_SDHCI_CD_GPIO, 90 .cd_type = S3C_SDHCI_CD_GPIO,
91 .ext_cd_gpio = S5PV310_GPK0(2), 91 .ext_cd_gpio = EXYNOS4_GPK0(2),
92 .ext_cd_gpio_invert = 1, 92 .ext_cd_gpio_invert = 1,
93 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, 93 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
94}; 94};
95 95
96static struct s3c_sdhci_platdata smdkc210_hsmmc2_pdata __initdata = { 96static struct s3c_sdhci_platdata smdkc210_hsmmc2_pdata __initdata = {
97 .cd_type = S3C_SDHCI_CD_GPIO, 97 .cd_type = S3C_SDHCI_CD_GPIO,
98 .ext_cd_gpio = S5PV310_GPK2(2), 98 .ext_cd_gpio = EXYNOS4_GPK2(2),
99 .ext_cd_gpio_invert = 1, 99 .ext_cd_gpio_invert = 1,
100 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, 100 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
101#ifdef CONFIG_S5PV310_SDHCI_CH2_8BIT 101#ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT
102 .max_width = 8, 102 .max_width = 8,
103 .host_caps = MMC_CAP_8_BIT_DATA, 103 .host_caps = MMC_CAP_8_BIT_DATA,
104#endif 104#endif
@@ -106,15 +106,15 @@ static struct s3c_sdhci_platdata smdkc210_hsmmc2_pdata __initdata = {
106 106
107static struct s3c_sdhci_platdata smdkc210_hsmmc3_pdata __initdata = { 107static struct s3c_sdhci_platdata smdkc210_hsmmc3_pdata __initdata = {
108 .cd_type = S3C_SDHCI_CD_GPIO, 108 .cd_type = S3C_SDHCI_CD_GPIO,
109 .ext_cd_gpio = S5PV310_GPK2(2), 109 .ext_cd_gpio = EXYNOS4_GPK2(2),
110 .ext_cd_gpio_invert = 1, 110 .ext_cd_gpio_invert = 1,
111 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, 111 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
112}; 112};
113 113
114static struct resource smdkc210_smsc911x_resources[] = { 114static struct resource smdkc210_smsc911x_resources[] = {
115 [0] = { 115 [0] = {
116 .start = S5PV310_PA_SROM_BANK(1), 116 .start = EXYNOS4_PA_SROM_BANK(1),
117 .end = S5PV310_PA_SROM_BANK(1) + SZ_64K - 1, 117 .end = EXYNOS4_PA_SROM_BANK(1) + SZ_64K - 1,
118 .flags = IORESOURCE_MEM, 118 .flags = IORESOURCE_MEM,
119 }, 119 },
120 [1] = { 120 [1] = {
@@ -154,16 +154,16 @@ static struct platform_device *smdkc210_devices[] __initdata = {
154 &s3c_device_i2c1, 154 &s3c_device_i2c1,
155 &s3c_device_rtc, 155 &s3c_device_rtc,
156 &s3c_device_wdt, 156 &s3c_device_wdt,
157 &s5pv310_device_ac97, 157 &exynos4_device_ac97,
158 &s5pv310_device_i2s0, 158 &exynos4_device_i2s0,
159 &s5pv310_device_pd[PD_MFC], 159 &exynos4_device_pd[PD_MFC],
160 &s5pv310_device_pd[PD_G3D], 160 &exynos4_device_pd[PD_G3D],
161 &s5pv310_device_pd[PD_LCD0], 161 &exynos4_device_pd[PD_LCD0],
162 &s5pv310_device_pd[PD_LCD1], 162 &exynos4_device_pd[PD_LCD1],
163 &s5pv310_device_pd[PD_CAM], 163 &exynos4_device_pd[PD_CAM],
164 &s5pv310_device_pd[PD_TV], 164 &exynos4_device_pd[PD_TV],
165 &s5pv310_device_pd[PD_GPS], 165 &exynos4_device_pd[PD_GPS],
166 &s5pv310_device_sysmmu, 166 &exynos4_device_sysmmu,
167 &samsung_asoc_dma, 167 &samsung_asoc_dma,
168 &smdkc210_smsc911x, 168 &smdkc210_smsc911x,
169}; 169};
@@ -216,8 +216,8 @@ static void __init smdkc210_machine_init(void)
216MACHINE_START(SMDKC210, "SMDKC210") 216MACHINE_START(SMDKC210, "SMDKC210")
217 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */ 217 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
218 .boot_params = S5P_PA_SDRAM + 0x100, 218 .boot_params = S5P_PA_SDRAM + 0x100,
219 .init_irq = s5pv310_init_irq, 219 .init_irq = exynos4_init_irq,
220 .map_io = smdkc210_map_io, 220 .map_io = smdkc210_map_io,
221 .init_machine = smdkc210_machine_init, 221 .init_machine = smdkc210_machine_init,
222 .timer = &s5pv310_timer, 222 .timer = &exynos4_timer,
223MACHINE_END 223MACHINE_END
diff --git a/arch/arm/mach-s5pv310/mach-smdkv310.c b/arch/arm/mach-exynos4/mach-smdkv310.c
index b1cddbf3c616..88e0275143be 100644
--- a/arch/arm/mach-s5pv310/mach-smdkv310.c
+++ b/arch/arm/mach-exynos4/mach-smdkv310.c
@@ -1,7 +1,7 @@
1/* linux/arch/arm/mach-s5pv310/mach-smdkv310.c 1/* linux/arch/arm/mach-exynos4/mach-smdkv310.c
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as 7 * it under the terms of the GNU General Public License version 2 as
@@ -15,15 +15,17 @@
15#include <linux/smsc911x.h> 15#include <linux/smsc911x.h>
16#include <linux/io.h> 16#include <linux/io.h>
17#include <linux/i2c.h> 17#include <linux/i2c.h>
18#include <linux/input.h>
18 19
19#include <asm/mach/arch.h> 20#include <asm/mach/arch.h>
20#include <asm/mach-types.h> 21#include <asm/mach-types.h>
21 22
22#include <plat/regs-serial.h> 23#include <plat/regs-serial.h>
23#include <plat/regs-srom.h> 24#include <plat/regs-srom.h>
24#include <plat/s5pv310.h> 25#include <plat/exynos4.h>
25#include <plat/cpu.h> 26#include <plat/cpu.h>
26#include <plat/devs.h> 27#include <plat/devs.h>
28#include <plat/keypad.h>
27#include <plat/sdhci.h> 29#include <plat/sdhci.h>
28#include <plat/iic.h> 30#include <plat/iic.h>
29#include <plat/pd.h> 31#include <plat/pd.h>
@@ -77,10 +79,10 @@ static struct s3c2410_uartcfg smdkv310_uartcfgs[] __initdata = {
77 79
78static struct s3c_sdhci_platdata smdkv310_hsmmc0_pdata __initdata = { 80static struct s3c_sdhci_platdata smdkv310_hsmmc0_pdata __initdata = {
79 .cd_type = S3C_SDHCI_CD_GPIO, 81 .cd_type = S3C_SDHCI_CD_GPIO,
80 .ext_cd_gpio = S5PV310_GPK0(2), 82 .ext_cd_gpio = EXYNOS4_GPK0(2),
81 .ext_cd_gpio_invert = 1, 83 .ext_cd_gpio_invert = 1,
82 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, 84 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
83#ifdef CONFIG_S5PV310_SDHCI_CH0_8BIT 85#ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT
84 .max_width = 8, 86 .max_width = 8,
85 .host_caps = MMC_CAP_8_BIT_DATA, 87 .host_caps = MMC_CAP_8_BIT_DATA,
86#endif 88#endif
@@ -88,17 +90,17 @@ static struct s3c_sdhci_platdata smdkv310_hsmmc0_pdata __initdata = {
88 90
89static struct s3c_sdhci_platdata smdkv310_hsmmc1_pdata __initdata = { 91static struct s3c_sdhci_platdata smdkv310_hsmmc1_pdata __initdata = {
90 .cd_type = S3C_SDHCI_CD_GPIO, 92 .cd_type = S3C_SDHCI_CD_GPIO,
91 .ext_cd_gpio = S5PV310_GPK0(2), 93 .ext_cd_gpio = EXYNOS4_GPK0(2),
92 .ext_cd_gpio_invert = 1, 94 .ext_cd_gpio_invert = 1,
93 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, 95 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
94}; 96};
95 97
96static struct s3c_sdhci_platdata smdkv310_hsmmc2_pdata __initdata = { 98static struct s3c_sdhci_platdata smdkv310_hsmmc2_pdata __initdata = {
97 .cd_type = S3C_SDHCI_CD_GPIO, 99 .cd_type = S3C_SDHCI_CD_GPIO,
98 .ext_cd_gpio = S5PV310_GPK2(2), 100 .ext_cd_gpio = EXYNOS4_GPK2(2),
99 .ext_cd_gpio_invert = 1, 101 .ext_cd_gpio_invert = 1,
100 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, 102 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
101#ifdef CONFIG_S5PV310_SDHCI_CH2_8BIT 103#ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT
102 .max_width = 8, 104 .max_width = 8,
103 .host_caps = MMC_CAP_8_BIT_DATA, 105 .host_caps = MMC_CAP_8_BIT_DATA,
104#endif 106#endif
@@ -106,15 +108,15 @@ static struct s3c_sdhci_platdata smdkv310_hsmmc2_pdata __initdata = {
106 108
107static struct s3c_sdhci_platdata smdkv310_hsmmc3_pdata __initdata = { 109static struct s3c_sdhci_platdata smdkv310_hsmmc3_pdata __initdata = {
108 .cd_type = S3C_SDHCI_CD_GPIO, 110 .cd_type = S3C_SDHCI_CD_GPIO,
109 .ext_cd_gpio = S5PV310_GPK2(2), 111 .ext_cd_gpio = EXYNOS4_GPK2(2),
110 .ext_cd_gpio_invert = 1, 112 .ext_cd_gpio_invert = 1,
111 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, 113 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
112}; 114};
113 115
114static struct resource smdkv310_smsc911x_resources[] = { 116static struct resource smdkv310_smsc911x_resources[] = {
115 [0] = { 117 [0] = {
116 .start = S5PV310_PA_SROM_BANK(1), 118 .start = EXYNOS4_PA_SROM_BANK(1),
117 .end = S5PV310_PA_SROM_BANK(1) + SZ_64K - 1, 119 .end = EXYNOS4_PA_SROM_BANK(1) + SZ_64K - 1,
118 .flags = IORESOURCE_MEM, 120 .flags = IORESOURCE_MEM,
119 }, 121 },
120 [1] = { 122 [1] = {
@@ -142,6 +144,25 @@ static struct platform_device smdkv310_smsc911x = {
142 }, 144 },
143}; 145};
144 146
147static uint32_t smdkv310_keymap[] __initdata = {
148 /* KEY(row, col, keycode) */
149 KEY(0, 3, KEY_1), KEY(0, 4, KEY_2), KEY(0, 5, KEY_3),
150 KEY(0, 6, KEY_4), KEY(0, 7, KEY_5),
151 KEY(1, 3, KEY_A), KEY(1, 4, KEY_B), KEY(1, 5, KEY_C),
152 KEY(1, 6, KEY_D), KEY(1, 7, KEY_E)
153};
154
155static struct matrix_keymap_data smdkv310_keymap_data __initdata = {
156 .keymap = smdkv310_keymap,
157 .keymap_size = ARRAY_SIZE(smdkv310_keymap),
158};
159
160static struct samsung_keypad_platdata smdkv310_keypad_data __initdata = {
161 .keymap_data = &smdkv310_keymap_data,
162 .rows = 2,
163 .cols = 8,
164};
165
145static struct i2c_board_info i2c_devs1[] __initdata = { 166static struct i2c_board_info i2c_devs1[] __initdata = {
146 {I2C_BOARD_INFO("wm8994", 0x1a),}, 167 {I2C_BOARD_INFO("wm8994", 0x1a),},
147}; 168};
@@ -154,16 +175,17 @@ static struct platform_device *smdkv310_devices[] __initdata = {
154 &s3c_device_i2c1, 175 &s3c_device_i2c1,
155 &s3c_device_rtc, 176 &s3c_device_rtc,
156 &s3c_device_wdt, 177 &s3c_device_wdt,
157 &s5pv310_device_ac97, 178 &exynos4_device_ac97,
158 &s5pv310_device_i2s0, 179 &exynos4_device_i2s0,
159 &s5pv310_device_pd[PD_MFC], 180 &samsung_device_keypad,
160 &s5pv310_device_pd[PD_G3D], 181 &exynos4_device_pd[PD_MFC],
161 &s5pv310_device_pd[PD_LCD0], 182 &exynos4_device_pd[PD_G3D],
162 &s5pv310_device_pd[PD_LCD1], 183 &exynos4_device_pd[PD_LCD0],
163 &s5pv310_device_pd[PD_CAM], 184 &exynos4_device_pd[PD_LCD1],
164 &s5pv310_device_pd[PD_TV], 185 &exynos4_device_pd[PD_CAM],
165 &s5pv310_device_pd[PD_GPS], 186 &exynos4_device_pd[PD_TV],
166 &s5pv310_device_sysmmu, 187 &exynos4_device_pd[PD_GPS],
188 &exynos4_device_sysmmu,
167 &samsung_asoc_dma, 189 &samsung_asoc_dma,
168 &smdkv310_smsc911x, 190 &smdkv310_smsc911x,
169}; 191};
@@ -210,6 +232,8 @@ static void __init smdkv310_machine_init(void)
210 s3c_sdhci2_set_platdata(&smdkv310_hsmmc2_pdata); 232 s3c_sdhci2_set_platdata(&smdkv310_hsmmc2_pdata);
211 s3c_sdhci3_set_platdata(&smdkv310_hsmmc3_pdata); 233 s3c_sdhci3_set_platdata(&smdkv310_hsmmc3_pdata);
212 234
235 samsung_keypad_set_platdata(&smdkv310_keypad_data);
236
213 platform_add_devices(smdkv310_devices, ARRAY_SIZE(smdkv310_devices)); 237 platform_add_devices(smdkv310_devices, ARRAY_SIZE(smdkv310_devices));
214} 238}
215 239
@@ -217,8 +241,8 @@ MACHINE_START(SMDKV310, "SMDKV310")
217 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */ 241 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
218 /* Maintainer: Changhwan Youn <chaos.youn@samsung.com> */ 242 /* Maintainer: Changhwan Youn <chaos.youn@samsung.com> */
219 .boot_params = S5P_PA_SDRAM + 0x100, 243 .boot_params = S5P_PA_SDRAM + 0x100,
220 .init_irq = s5pv310_init_irq, 244 .init_irq = exynos4_init_irq,
221 .map_io = smdkv310_map_io, 245 .map_io = smdkv310_map_io,
222 .init_machine = smdkv310_machine_init, 246 .init_machine = smdkv310_machine_init,
223 .timer = &s5pv310_timer, 247 .timer = &exynos4_timer,
224MACHINE_END 248MACHINE_END
diff --git a/arch/arm/mach-exynos4/mach-universal_c210.c b/arch/arm/mach-exynos4/mach-universal_c210.c
new file mode 100644
index 000000000000..97d329fff2cf
--- /dev/null
+++ b/arch/arm/mach-exynos4/mach-universal_c210.c
@@ -0,0 +1,650 @@
1/* linux/arch/arm/mach-exynos4/mach-universal_c210.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8*/
9
10#include <linux/platform_device.h>
11#include <linux/serial_core.h>
12#include <linux/input.h>
13#include <linux/i2c.h>
14#include <linux/gpio_keys.h>
15#include <linux/gpio.h>
16#include <linux/mfd/max8998.h>
17#include <linux/regulator/machine.h>
18#include <linux/regulator/fixed.h>
19#include <linux/regulator/max8952.h>
20#include <linux/mmc/host.h>
21
22#include <asm/mach/arch.h>
23#include <asm/mach-types.h>
24
25#include <plat/regs-serial.h>
26#include <plat/exynos4.h>
27#include <plat/cpu.h>
28#include <plat/devs.h>
29#include <plat/iic.h>
30#include <plat/sdhci.h>
31
32#include <mach/map.h>
33
34/* Following are default values for UCON, ULCON and UFCON UART registers */
35#define UNIVERSAL_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
36 S3C2410_UCON_RXILEVEL | \
37 S3C2410_UCON_TXIRQMODE | \
38 S3C2410_UCON_RXIRQMODE | \
39 S3C2410_UCON_RXFIFO_TOI | \
40 S3C2443_UCON_RXERR_IRQEN)
41
42#define UNIVERSAL_ULCON_DEFAULT S3C2410_LCON_CS8
43
44#define UNIVERSAL_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
45 S5PV210_UFCON_TXTRIG256 | \
46 S5PV210_UFCON_RXTRIG256)
47
48static struct s3c2410_uartcfg universal_uartcfgs[] __initdata = {
49 [0] = {
50 .hwport = 0,
51 .ucon = UNIVERSAL_UCON_DEFAULT,
52 .ulcon = UNIVERSAL_ULCON_DEFAULT,
53 .ufcon = UNIVERSAL_UFCON_DEFAULT,
54 },
55 [1] = {
56 .hwport = 1,
57 .ucon = UNIVERSAL_UCON_DEFAULT,
58 .ulcon = UNIVERSAL_ULCON_DEFAULT,
59 .ufcon = UNIVERSAL_UFCON_DEFAULT,
60 },
61 [2] = {
62 .hwport = 2,
63 .ucon = UNIVERSAL_UCON_DEFAULT,
64 .ulcon = UNIVERSAL_ULCON_DEFAULT,
65 .ufcon = UNIVERSAL_UFCON_DEFAULT,
66 },
67 [3] = {
68 .hwport = 3,
69 .ucon = UNIVERSAL_UCON_DEFAULT,
70 .ulcon = UNIVERSAL_ULCON_DEFAULT,
71 .ufcon = UNIVERSAL_UFCON_DEFAULT,
72 },
73};
74
75static struct regulator_consumer_supply max8952_consumer =
76 REGULATOR_SUPPLY("vddarm", NULL);
77
78static struct max8952_platform_data universal_max8952_pdata __initdata = {
79 .gpio_vid0 = EXYNOS4_GPX0(3),
80 .gpio_vid1 = EXYNOS4_GPX0(4),
81 .gpio_en = -1, /* Not controllable, set "Always High" */
82 .default_mode = 0, /* vid0 = 0, vid1 = 0 */
83 .dvs_mode = { 48, 32, 28, 18 }, /* 1.25, 1.20, 1.05, 0.95V */
84 .sync_freq = 0, /* default: fastest */
85 .ramp_speed = 0, /* default: fastest */
86
87 .reg_data = {
88 .constraints = {
89 .name = "VARM_1.2V",
90 .min_uV = 770000,
91 .max_uV = 1400000,
92 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
93 .always_on = 1,
94 .boot_on = 1,
95 },
96 .num_consumer_supplies = 1,
97 .consumer_supplies = &max8952_consumer,
98 },
99};
100
101static struct regulator_consumer_supply lp3974_buck1_consumer =
102 REGULATOR_SUPPLY("vddint", NULL);
103
104static struct regulator_consumer_supply lp3974_buck2_consumer =
105 REGULATOR_SUPPLY("vddg3d", NULL);
106
107static struct regulator_init_data lp3974_buck1_data = {
108 .constraints = {
109 .name = "VINT_1.1V",
110 .min_uV = 750000,
111 .max_uV = 1500000,
112 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
113 REGULATOR_CHANGE_STATUS,
114 .boot_on = 1,
115 .state_mem = {
116 .disabled = 1,
117 },
118 },
119 .num_consumer_supplies = 1,
120 .consumer_supplies = &lp3974_buck1_consumer,
121};
122
123static struct regulator_init_data lp3974_buck2_data = {
124 .constraints = {
125 .name = "VG3D_1.1V",
126 .min_uV = 750000,
127 .max_uV = 1500000,
128 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
129 REGULATOR_CHANGE_STATUS,
130 .boot_on = 1,
131 .state_mem = {
132 .disabled = 1,
133 },
134 },
135 .num_consumer_supplies = 1,
136 .consumer_supplies = &lp3974_buck2_consumer,
137};
138
139static struct regulator_init_data lp3974_buck3_data = {
140 .constraints = {
141 .name = "VCC_1.8V",
142 .min_uV = 1800000,
143 .max_uV = 1800000,
144 .apply_uV = 1,
145 .always_on = 1,
146 .state_mem = {
147 .enabled = 1,
148 },
149 },
150};
151
152static struct regulator_init_data lp3974_buck4_data = {
153 .constraints = {
154 .name = "VMEM_1.2V",
155 .min_uV = 1200000,
156 .max_uV = 1200000,
157 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
158 .apply_uV = 1,
159 .state_mem = {
160 .disabled = 1,
161 },
162 },
163};
164
165static struct regulator_init_data lp3974_ldo2_data = {
166 .constraints = {
167 .name = "VALIVE_1.2V",
168 .min_uV = 1200000,
169 .max_uV = 1200000,
170 .apply_uV = 1,
171 .always_on = 1,
172 .state_mem = {
173 .enabled = 1,
174 },
175 },
176};
177
178static struct regulator_init_data lp3974_ldo3_data = {
179 .constraints = {
180 .name = "VUSB+MIPI_1.1V",
181 .min_uV = 1100000,
182 .max_uV = 1100000,
183 .apply_uV = 1,
184 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
185 .state_mem = {
186 .disabled = 1,
187 },
188 },
189};
190
191static struct regulator_init_data lp3974_ldo4_data = {
192 .constraints = {
193 .name = "VADC_3.3V",
194 .min_uV = 3300000,
195 .max_uV = 3300000,
196 .apply_uV = 1,
197 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
198 .state_mem = {
199 .disabled = 1,
200 },
201 },
202};
203
204static struct regulator_init_data lp3974_ldo5_data = {
205 .constraints = {
206 .name = "VTF_2.8V",
207 .min_uV = 2800000,
208 .max_uV = 2800000,
209 .apply_uV = 1,
210 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
211 .state_mem = {
212 .disabled = 1,
213 },
214 },
215};
216
217static struct regulator_init_data lp3974_ldo6_data = {
218 .constraints = {
219 .name = "LDO6",
220 .min_uV = 2000000,
221 .max_uV = 2000000,
222 .apply_uV = 1,
223 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
224 .state_mem = {
225 .disabled = 1,
226 },
227 },
228};
229
230static struct regulator_init_data lp3974_ldo7_data = {
231 .constraints = {
232 .name = "VLCD+VMIPI_1.8V",
233 .min_uV = 1800000,
234 .max_uV = 1800000,
235 .apply_uV = 1,
236 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
237 .state_mem = {
238 .disabled = 1,
239 },
240 },
241};
242
243static struct regulator_init_data lp3974_ldo8_data = {
244 .constraints = {
245 .name = "VUSB+VDAC_3.3V",
246 .min_uV = 3300000,
247 .max_uV = 3300000,
248 .apply_uV = 1,
249 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
250 .state_mem = {
251 .disabled = 1,
252 },
253 },
254};
255
256static struct regulator_init_data lp3974_ldo9_data = {
257 .constraints = {
258 .name = "VCC_2.8V",
259 .min_uV = 2800000,
260 .max_uV = 2800000,
261 .apply_uV = 1,
262 .always_on = 1,
263 .state_mem = {
264 .enabled = 1,
265 },
266 },
267};
268
269static struct regulator_init_data lp3974_ldo10_data = {
270 .constraints = {
271 .name = "VPLL_1.1V",
272 .min_uV = 1100000,
273 .max_uV = 1100000,
274 .boot_on = 1,
275 .apply_uV = 1,
276 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
277 .state_mem = {
278 .disabled = 1,
279 },
280 },
281};
282
283static struct regulator_init_data lp3974_ldo11_data = {
284 .constraints = {
285 .name = "CAM_AF_3.3V",
286 .min_uV = 3300000,
287 .max_uV = 3300000,
288 .apply_uV = 1,
289 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
290 .state_mem = {
291 .disabled = 1,
292 },
293 },
294};
295
296static struct regulator_init_data lp3974_ldo12_data = {
297 .constraints = {
298 .name = "PS_2.8V",
299 .min_uV = 2800000,
300 .max_uV = 2800000,
301 .apply_uV = 1,
302 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
303 .state_mem = {
304 .disabled = 1,
305 },
306 },
307};
308
309static struct regulator_init_data lp3974_ldo13_data = {
310 .constraints = {
311 .name = "VHIC_1.2V",
312 .min_uV = 1200000,
313 .max_uV = 1200000,
314 .apply_uV = 1,
315 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
316 .state_mem = {
317 .disabled = 1,
318 },
319 },
320};
321
322static struct regulator_init_data lp3974_ldo14_data = {
323 .constraints = {
324 .name = "CAM_I_HOST_1.8V",
325 .min_uV = 1800000,
326 .max_uV = 1800000,
327 .apply_uV = 1,
328 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
329 .state_mem = {
330 .disabled = 1,
331 },
332 },
333};
334
335static struct regulator_init_data lp3974_ldo15_data = {
336 .constraints = {
337 .name = "CAM_S_DIG+FM33_CORE_1.2V",
338 .min_uV = 1200000,
339 .max_uV = 1200000,
340 .apply_uV = 1,
341 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
342 .state_mem = {
343 .disabled = 1,
344 },
345 },
346};
347
348static struct regulator_init_data lp3974_ldo16_data = {
349 .constraints = {
350 .name = "CAM_S_ANA_2.8V",
351 .min_uV = 2800000,
352 .max_uV = 2800000,
353 .apply_uV = 1,
354 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
355 .state_mem = {
356 .disabled = 1,
357 },
358 },
359};
360
361static struct regulator_init_data lp3974_ldo17_data = {
362 .constraints = {
363 .name = "VCC_3.0V_LCD",
364 .min_uV = 3000000,
365 .max_uV = 3000000,
366 .apply_uV = 1,
367 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
368 .boot_on = 1,
369 .state_mem = {
370 .disabled = 1,
371 },
372 },
373};
374
375static struct regulator_init_data lp3974_32khz_ap_data = {
376 .constraints = {
377 .name = "32KHz AP",
378 .always_on = 1,
379 .state_mem = {
380 .enabled = 1,
381 },
382 },
383};
384
385static struct regulator_init_data lp3974_32khz_cp_data = {
386 .constraints = {
387 .name = "32KHz CP",
388 .state_mem = {
389 .disabled = 1,
390 },
391 },
392};
393
394static struct regulator_init_data lp3974_vichg_data = {
395 .constraints = {
396 .name = "VICHG",
397 .state_mem = {
398 .disabled = 1,
399 },
400 },
401};
402
403static struct regulator_init_data lp3974_esafeout1_data = {
404 .constraints = {
405 .name = "SAFEOUT1",
406 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
407 .state_mem = {
408 .enabled = 1,
409 },
410 },
411};
412
413static struct regulator_init_data lp3974_esafeout2_data = {
414 .constraints = {
415 .name = "SAFEOUT2",
416 .boot_on = 1,
417 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
418 .state_mem = {
419 .enabled = 1,
420 },
421 },
422};
423
424static struct max8998_regulator_data lp3974_regulators[] = {
425 { MAX8998_LDO2, &lp3974_ldo2_data },
426 { MAX8998_LDO3, &lp3974_ldo3_data },
427 { MAX8998_LDO4, &lp3974_ldo4_data },
428 { MAX8998_LDO5, &lp3974_ldo5_data },
429 { MAX8998_LDO6, &lp3974_ldo6_data },
430 { MAX8998_LDO7, &lp3974_ldo7_data },
431 { MAX8998_LDO8, &lp3974_ldo8_data },
432 { MAX8998_LDO9, &lp3974_ldo9_data },
433 { MAX8998_LDO10, &lp3974_ldo10_data },
434 { MAX8998_LDO11, &lp3974_ldo11_data },
435 { MAX8998_LDO12, &lp3974_ldo12_data },
436 { MAX8998_LDO13, &lp3974_ldo13_data },
437 { MAX8998_LDO14, &lp3974_ldo14_data },
438 { MAX8998_LDO15, &lp3974_ldo15_data },
439 { MAX8998_LDO16, &lp3974_ldo16_data },
440 { MAX8998_LDO17, &lp3974_ldo17_data },
441 { MAX8998_BUCK1, &lp3974_buck1_data },
442 { MAX8998_BUCK2, &lp3974_buck2_data },
443 { MAX8998_BUCK3, &lp3974_buck3_data },
444 { MAX8998_BUCK4, &lp3974_buck4_data },
445 { MAX8998_EN32KHZ_AP, &lp3974_32khz_ap_data },
446 { MAX8998_EN32KHZ_CP, &lp3974_32khz_cp_data },
447 { MAX8998_ENVICHG, &lp3974_vichg_data },
448 { MAX8998_ESAFEOUT1, &lp3974_esafeout1_data },
449 { MAX8998_ESAFEOUT2, &lp3974_esafeout2_data },
450};
451
452static struct max8998_platform_data universal_lp3974_pdata = {
453 .num_regulators = ARRAY_SIZE(lp3974_regulators),
454 .regulators = lp3974_regulators,
455 .buck1_voltage1 = 1100000, /* INT */
456 .buck1_voltage2 = 1000000,
457 .buck1_voltage3 = 1100000,
458 .buck1_voltage4 = 1000000,
459 .buck1_set1 = EXYNOS4_GPX0(5),
460 .buck1_set2 = EXYNOS4_GPX0(6),
461 .buck2_voltage1 = 1200000, /* G3D */
462 .buck2_voltage2 = 1100000,
463 .buck1_default_idx = 0,
464 .buck2_set3 = EXYNOS4_GPE2(0),
465 .buck2_default_idx = 0,
466 .wakeup = true,
467};
468
469/* GPIO I2C 5 (PMIC) */
470static struct i2c_board_info i2c5_devs[] __initdata = {
471 {
472 I2C_BOARD_INFO("max8952", 0xC0 >> 1),
473 .platform_data = &universal_max8952_pdata,
474 }, {
475 I2C_BOARD_INFO("lp3974", 0xCC >> 1),
476 .platform_data = &universal_lp3974_pdata,
477 },
478};
479
480/* GPIO KEYS */
481static struct gpio_keys_button universal_gpio_keys_tables[] = {
482 {
483 .code = KEY_VOLUMEUP,
484 .gpio = EXYNOS4_GPX2(0), /* XEINT16 */
485 .desc = "gpio-keys: KEY_VOLUMEUP",
486 .type = EV_KEY,
487 .active_low = 1,
488 .debounce_interval = 1,
489 }, {
490 .code = KEY_VOLUMEDOWN,
491 .gpio = EXYNOS4_GPX2(1), /* XEINT17 */
492 .desc = "gpio-keys: KEY_VOLUMEDOWN",
493 .type = EV_KEY,
494 .active_low = 1,
495 .debounce_interval = 1,
496 }, {
497 .code = KEY_CONFIG,
498 .gpio = EXYNOS4_GPX2(2), /* XEINT18 */
499 .desc = "gpio-keys: KEY_CONFIG",
500 .type = EV_KEY,
501 .active_low = 1,
502 .debounce_interval = 1,
503 }, {
504 .code = KEY_CAMERA,
505 .gpio = EXYNOS4_GPX2(3), /* XEINT19 */
506 .desc = "gpio-keys: KEY_CAMERA",
507 .type = EV_KEY,
508 .active_low = 1,
509 .debounce_interval = 1,
510 }, {
511 .code = KEY_OK,
512 .gpio = EXYNOS4_GPX3(5), /* XEINT29 */
513 .desc = "gpio-keys: KEY_OK",
514 .type = EV_KEY,
515 .active_low = 1,
516 .debounce_interval = 1,
517 },
518};
519
520static struct gpio_keys_platform_data universal_gpio_keys_data = {
521 .buttons = universal_gpio_keys_tables,
522 .nbuttons = ARRAY_SIZE(universal_gpio_keys_tables),
523};
524
525static struct platform_device universal_gpio_keys = {
526 .name = "gpio-keys",
527 .dev = {
528 .platform_data = &universal_gpio_keys_data,
529 },
530};
531
532/* eMMC */
533static struct s3c_sdhci_platdata universal_hsmmc0_data __initdata = {
534 .max_width = 8,
535 .host_caps = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
536 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
537 MMC_CAP_DISABLE),
538 .cd_type = S3C_SDHCI_CD_PERMANENT,
539 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
540};
541
542static struct regulator_consumer_supply mmc0_supplies[] = {
543 REGULATOR_SUPPLY("vmmc", "s3c-sdhci.0"),
544};
545
546static struct regulator_init_data mmc0_fixed_voltage_init_data = {
547 .constraints = {
548 .name = "VMEM_VDD_2.8V",
549 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
550 },
551 .num_consumer_supplies = ARRAY_SIZE(mmc0_supplies),
552 .consumer_supplies = mmc0_supplies,
553};
554
555static struct fixed_voltage_config mmc0_fixed_voltage_config = {
556 .supply_name = "MASSMEMORY_EN",
557 .microvolts = 2800000,
558 .gpio = EXYNOS4_GPE1(3),
559 .enable_high = true,
560 .init_data = &mmc0_fixed_voltage_init_data,
561};
562
563static struct platform_device mmc0_fixed_voltage = {
564 .name = "reg-fixed-voltage",
565 .id = 0,
566 .dev = {
567 .platform_data = &mmc0_fixed_voltage_config,
568 },
569};
570
571/* SD */
572static struct s3c_sdhci_platdata universal_hsmmc2_data __initdata = {
573 .max_width = 4,
574 .host_caps = MMC_CAP_4_BIT_DATA |
575 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
576 MMC_CAP_DISABLE,
577 .ext_cd_gpio = EXYNOS4_GPX3(4), /* XEINT_28 */
578 .ext_cd_gpio_invert = 1,
579 .cd_type = S3C_SDHCI_CD_GPIO,
580 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
581};
582
583/* WiFi */
584static struct s3c_sdhci_platdata universal_hsmmc3_data __initdata = {
585 .max_width = 4,
586 .host_caps = MMC_CAP_4_BIT_DATA |
587 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
588 MMC_CAP_DISABLE,
589 .cd_type = S3C_SDHCI_CD_EXTERNAL,
590};
591
592static void __init universal_sdhci_init(void)
593{
594 s3c_sdhci0_set_platdata(&universal_hsmmc0_data);
595 s3c_sdhci2_set_platdata(&universal_hsmmc2_data);
596 s3c_sdhci3_set_platdata(&universal_hsmmc3_data);
597}
598
599/* I2C0 */
600static struct i2c_board_info i2c0_devs[] __initdata = {
601 /* Camera, To be updated */
602};
603
604/* I2C1 */
605static struct i2c_board_info i2c1_devs[] __initdata = {
606 /* Gyro, To be updated */
607};
608
609static struct platform_device *universal_devices[] __initdata = {
610 /* Samsung Platform Devices */
611 &mmc0_fixed_voltage,
612 &s3c_device_hsmmc0,
613 &s3c_device_hsmmc2,
614 &s3c_device_hsmmc3,
615 &s3c_device_i2c5,
616
617 /* Universal Devices */
618 &universal_gpio_keys,
619 &s5p_device_onenand,
620};
621
622static void __init universal_map_io(void)
623{
624 s5p_init_io(NULL, 0, S5P_VA_CHIPID);
625 s3c24xx_init_clocks(24000000);
626 s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs));
627}
628
629static void __init universal_machine_init(void)
630{
631 universal_sdhci_init();
632
633 i2c_register_board_info(0, i2c0_devs, ARRAY_SIZE(i2c0_devs));
634 i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
635
636 s3c_i2c5_set_platdata(NULL);
637 i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs));
638
639 /* Last */
640 platform_add_devices(universal_devices, ARRAY_SIZE(universal_devices));
641}
642
643MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
644 /* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */
645 .boot_params = S5P_PA_SDRAM + 0x100,
646 .init_irq = exynos4_init_irq,
647 .map_io = universal_map_io,
648 .init_machine = universal_machine_init,
649 .timer = &exynos4_timer,
650MACHINE_END
diff --git a/arch/arm/mach-exynos4/mct.c b/arch/arm/mach-exynos4/mct.c
new file mode 100644
index 000000000000..af82a8fbb68b
--- /dev/null
+++ b/arch/arm/mach-exynos4/mct.c
@@ -0,0 +1,421 @@
1/* linux/arch/arm/mach-exynos4/mct.c
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS4 MCT(Multi-Core Timer) support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/sched.h>
14#include <linux/interrupt.h>
15#include <linux/irq.h>
16#include <linux/err.h>
17#include <linux/clk.h>
18#include <linux/clockchips.h>
19#include <linux/platform_device.h>
20#include <linux/delay.h>
21#include <linux/percpu.h>
22
23#include <mach/map.h>
24#include <mach/regs-mct.h>
25#include <asm/mach/time.h>
26
27static unsigned long clk_cnt_per_tick;
28static unsigned long clk_rate;
29
30struct mct_clock_event_device {
31 struct clock_event_device *evt;
32 void __iomem *base;
33};
34
35struct mct_clock_event_device mct_tick[2];
36
37static void exynos4_mct_write(unsigned int value, void *addr)
38{
39 void __iomem *stat_addr;
40 u32 mask;
41 u32 i;
42
43 __raw_writel(value, addr);
44
45 switch ((u32) addr) {
46 case (u32) EXYNOS4_MCT_G_TCON:
47 stat_addr = EXYNOS4_MCT_G_WSTAT;
48 mask = 1 << 16; /* G_TCON write status */
49 break;
50 case (u32) EXYNOS4_MCT_G_COMP0_L:
51 stat_addr = EXYNOS4_MCT_G_WSTAT;
52 mask = 1 << 0; /* G_COMP0_L write status */
53 break;
54 case (u32) EXYNOS4_MCT_G_COMP0_U:
55 stat_addr = EXYNOS4_MCT_G_WSTAT;
56 mask = 1 << 1; /* G_COMP0_U write status */
57 break;
58 case (u32) EXYNOS4_MCT_G_COMP0_ADD_INCR:
59 stat_addr = EXYNOS4_MCT_G_WSTAT;
60 mask = 1 << 2; /* G_COMP0_ADD_INCR write status */
61 break;
62 case (u32) EXYNOS4_MCT_G_CNT_L:
63 stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
64 mask = 1 << 0; /* G_CNT_L write status */
65 break;
66 case (u32) EXYNOS4_MCT_G_CNT_U:
67 stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
68 mask = 1 << 1; /* G_CNT_U write status */
69 break;
70 case (u32)(EXYNOS4_MCT_L0_BASE + MCT_L_TCON_OFFSET):
71 stat_addr = EXYNOS4_MCT_L0_BASE + MCT_L_WSTAT_OFFSET;
72 mask = 1 << 3; /* L0_TCON write status */
73 break;
74 case (u32)(EXYNOS4_MCT_L1_BASE + MCT_L_TCON_OFFSET):
75 stat_addr = EXYNOS4_MCT_L1_BASE + MCT_L_WSTAT_OFFSET;
76 mask = 1 << 3; /* L1_TCON write status */
77 break;
78 case (u32)(EXYNOS4_MCT_L0_BASE + MCT_L_TCNTB_OFFSET):
79 stat_addr = EXYNOS4_MCT_L0_BASE + MCT_L_WSTAT_OFFSET;
80 mask = 1 << 0; /* L0_TCNTB write status */
81 break;
82 case (u32)(EXYNOS4_MCT_L1_BASE + MCT_L_TCNTB_OFFSET):
83 stat_addr = EXYNOS4_MCT_L1_BASE + MCT_L_WSTAT_OFFSET;
84 mask = 1 << 0; /* L1_TCNTB write status */
85 break;
86 case (u32)(EXYNOS4_MCT_L0_BASE + MCT_L_ICNTB_OFFSET):
87 stat_addr = EXYNOS4_MCT_L0_BASE + MCT_L_WSTAT_OFFSET;
88 mask = 1 << 1; /* L0_ICNTB write status */
89 break;
90 case (u32)(EXYNOS4_MCT_L1_BASE + MCT_L_ICNTB_OFFSET):
91 stat_addr = EXYNOS4_MCT_L1_BASE + MCT_L_WSTAT_OFFSET;
92 mask = 1 << 1; /* L1_ICNTB write status */
93 break;
94 default:
95 return;
96 }
97
98 /* Wait maximum 1 ms until written values are applied */
99 for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++)
100 if (__raw_readl(stat_addr) & mask) {
101 __raw_writel(mask, stat_addr);
102 return;
103 }
104
105 panic("MCT hangs after writing %d (addr:0x%08x)\n", value, (u32)addr);
106}
107
108/* Clocksource handling */
109static void exynos4_mct_frc_start(u32 hi, u32 lo)
110{
111 u32 reg;
112
113 exynos4_mct_write(lo, EXYNOS4_MCT_G_CNT_L);
114 exynos4_mct_write(hi, EXYNOS4_MCT_G_CNT_U);
115
116 reg = __raw_readl(EXYNOS4_MCT_G_TCON);
117 reg |= MCT_G_TCON_START;
118 exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
119}
120
121static cycle_t exynos4_frc_read(struct clocksource *cs)
122{
123 unsigned int lo, hi;
124 u32 hi2 = __raw_readl(EXYNOS4_MCT_G_CNT_U);
125
126 do {
127 hi = hi2;
128 lo = __raw_readl(EXYNOS4_MCT_G_CNT_L);
129 hi2 = __raw_readl(EXYNOS4_MCT_G_CNT_U);
130 } while (hi != hi2);
131
132 return ((cycle_t)hi << 32) | lo;
133}
134
135struct clocksource mct_frc = {
136 .name = "mct-frc",
137 .rating = 400,
138 .read = exynos4_frc_read,
139 .mask = CLOCKSOURCE_MASK(64),
140 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
141};
142
143static void __init exynos4_clocksource_init(void)
144{
145 exynos4_mct_frc_start(0, 0);
146
147 if (clocksource_register_hz(&mct_frc, clk_rate))
148 panic("%s: can't register clocksource\n", mct_frc.name);
149}
150
151static void exynos4_mct_comp0_stop(void)
152{
153 unsigned int tcon;
154
155 tcon = __raw_readl(EXYNOS4_MCT_G_TCON);
156 tcon &= ~(MCT_G_TCON_COMP0_ENABLE | MCT_G_TCON_COMP0_AUTO_INC);
157
158 exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON);
159 exynos4_mct_write(0, EXYNOS4_MCT_G_INT_ENB);
160}
161
162static void exynos4_mct_comp0_start(enum clock_event_mode mode,
163 unsigned long cycles)
164{
165 unsigned int tcon;
166 cycle_t comp_cycle;
167
168 tcon = __raw_readl(EXYNOS4_MCT_G_TCON);
169
170 if (mode == CLOCK_EVT_MODE_PERIODIC) {
171 tcon |= MCT_G_TCON_COMP0_AUTO_INC;
172 exynos4_mct_write(cycles, EXYNOS4_MCT_G_COMP0_ADD_INCR);
173 }
174
175 comp_cycle = exynos4_frc_read(&mct_frc) + cycles;
176 exynos4_mct_write((u32)comp_cycle, EXYNOS4_MCT_G_COMP0_L);
177 exynos4_mct_write((u32)(comp_cycle >> 32), EXYNOS4_MCT_G_COMP0_U);
178
179 exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_ENB);
180
181 tcon |= MCT_G_TCON_COMP0_ENABLE;
182 exynos4_mct_write(tcon , EXYNOS4_MCT_G_TCON);
183}
184
185static int exynos4_comp_set_next_event(unsigned long cycles,
186 struct clock_event_device *evt)
187{
188 exynos4_mct_comp0_start(evt->mode, cycles);
189
190 return 0;
191}
192
193static void exynos4_comp_set_mode(enum clock_event_mode mode,
194 struct clock_event_device *evt)
195{
196 exynos4_mct_comp0_stop();
197
198 switch (mode) {
199 case CLOCK_EVT_MODE_PERIODIC:
200 exynos4_mct_comp0_start(mode, clk_cnt_per_tick);
201 break;
202
203 case CLOCK_EVT_MODE_ONESHOT:
204 case CLOCK_EVT_MODE_UNUSED:
205 case CLOCK_EVT_MODE_SHUTDOWN:
206 case CLOCK_EVT_MODE_RESUME:
207 break;
208 }
209}
210
211static struct clock_event_device mct_comp_device = {
212 .name = "mct-comp",
213 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
214 .rating = 250,
215 .set_next_event = exynos4_comp_set_next_event,
216 .set_mode = exynos4_comp_set_mode,
217};
218
219static irqreturn_t exynos4_mct_comp_isr(int irq, void *dev_id)
220{
221 struct clock_event_device *evt = dev_id;
222
223 exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_CSTAT);
224
225 evt->event_handler(evt);
226
227 return IRQ_HANDLED;
228}
229
230static struct irqaction mct_comp_event_irq = {
231 .name = "mct_comp_irq",
232 .flags = IRQF_TIMER | IRQF_IRQPOLL,
233 .handler = exynos4_mct_comp_isr,
234 .dev_id = &mct_comp_device,
235};
236
237static void exynos4_clockevent_init(void)
238{
239 clk_cnt_per_tick = clk_rate / 2 / HZ;
240
241 clockevents_calc_mult_shift(&mct_comp_device, clk_rate / 2, 5);
242 mct_comp_device.max_delta_ns =
243 clockevent_delta2ns(0xffffffff, &mct_comp_device);
244 mct_comp_device.min_delta_ns =
245 clockevent_delta2ns(0xf, &mct_comp_device);
246 mct_comp_device.cpumask = cpumask_of(0);
247 clockevents_register_device(&mct_comp_device);
248
249 setup_irq(IRQ_MCT_G0, &mct_comp_event_irq);
250}
251
252#ifdef CONFIG_LOCAL_TIMERS
253/* Clock event handling */
254static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt)
255{
256 unsigned long tmp;
257 unsigned long mask = MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START;
258 void __iomem *addr = mevt->base + MCT_L_TCON_OFFSET;
259
260 tmp = __raw_readl(addr);
261 if (tmp & mask) {
262 tmp &= ~mask;
263 exynos4_mct_write(tmp, addr);
264 }
265}
266
267static void exynos4_mct_tick_start(unsigned long cycles,
268 struct mct_clock_event_device *mevt)
269{
270 unsigned long tmp;
271
272 exynos4_mct_tick_stop(mevt);
273
274 tmp = (1 << 31) | cycles; /* MCT_L_UPDATE_ICNTB */
275
276 /* update interrupt count buffer */
277 exynos4_mct_write(tmp, mevt->base + MCT_L_ICNTB_OFFSET);
278
279 /* enable MCT tick interupt */
280 exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET);
281
282 tmp = __raw_readl(mevt->base + MCT_L_TCON_OFFSET);
283 tmp |= MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START |
284 MCT_L_TCON_INTERVAL_MODE;
285 exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET);
286}
287
288static int exynos4_tick_set_next_event(unsigned long cycles,
289 struct clock_event_device *evt)
290{
291 struct mct_clock_event_device *mevt = &mct_tick[smp_processor_id()];
292
293 exynos4_mct_tick_start(cycles, mevt);
294
295 return 0;
296}
297
298static inline void exynos4_tick_set_mode(enum clock_event_mode mode,
299 struct clock_event_device *evt)
300{
301 struct mct_clock_event_device *mevt = &mct_tick[smp_processor_id()];
302
303 exynos4_mct_tick_stop(mevt);
304
305 switch (mode) {
306 case CLOCK_EVT_MODE_PERIODIC:
307 exynos4_mct_tick_start(clk_cnt_per_tick, mevt);
308 break;
309
310 case CLOCK_EVT_MODE_ONESHOT:
311 case CLOCK_EVT_MODE_UNUSED:
312 case CLOCK_EVT_MODE_SHUTDOWN:
313 case CLOCK_EVT_MODE_RESUME:
314 break;
315 }
316}
317
318static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
319{
320 struct mct_clock_event_device *mevt = dev_id;
321 struct clock_event_device *evt = mevt->evt;
322
323 /*
324 * This is for supporting oneshot mode.
325 * Mct would generate interrupt periodically
326 * without explicit stopping.
327 */
328 if (evt->mode != CLOCK_EVT_MODE_PERIODIC)
329 exynos4_mct_tick_stop(mevt);
330
331 /* Clear the MCT tick interrupt */
332 exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
333
334 evt->event_handler(evt);
335
336 return IRQ_HANDLED;
337}
338
339static struct irqaction mct_tick0_event_irq = {
340 .name = "mct_tick0_irq",
341 .flags = IRQF_TIMER | IRQF_NOBALANCING,
342 .handler = exynos4_mct_tick_isr,
343};
344
345static struct irqaction mct_tick1_event_irq = {
346 .name = "mct_tick1_irq",
347 .flags = IRQF_TIMER | IRQF_NOBALANCING,
348 .handler = exynos4_mct_tick_isr,
349};
350
351static void exynos4_mct_tick_init(struct clock_event_device *evt)
352{
353 unsigned int cpu = smp_processor_id();
354
355 mct_tick[cpu].evt = evt;
356
357 if (cpu == 0) {
358 mct_tick[cpu].base = EXYNOS4_MCT_L0_BASE;
359 evt->name = "mct_tick0";
360 } else {
361 mct_tick[cpu].base = EXYNOS4_MCT_L1_BASE;
362 evt->name = "mct_tick1";
363 }
364
365 evt->cpumask = cpumask_of(cpu);
366 evt->set_next_event = exynos4_tick_set_next_event;
367 evt->set_mode = exynos4_tick_set_mode;
368 evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
369 evt->rating = 450;
370
371 clockevents_calc_mult_shift(evt, clk_rate / 2, 5);
372 evt->max_delta_ns =
373 clockevent_delta2ns(0x7fffffff, evt);
374 evt->min_delta_ns =
375 clockevent_delta2ns(0xf, evt);
376
377 clockevents_register_device(evt);
378
379 exynos4_mct_write(0x1, mct_tick[cpu].base + MCT_L_TCNTB_OFFSET);
380
381 if (cpu == 0) {
382 mct_tick0_event_irq.dev_id = &mct_tick[cpu];
383 setup_irq(IRQ_MCT_L0, &mct_tick0_event_irq);
384 } else {
385 mct_tick1_event_irq.dev_id = &mct_tick[cpu];
386 irq_set_affinity(IRQ_MCT1, cpumask_of(1));
387 setup_irq(IRQ_MCT_L1, &mct_tick1_event_irq);
388 }
389}
390
391/* Setup the local clock events for a CPU */
392void __cpuinit local_timer_setup(struct clock_event_device *evt)
393{
394 exynos4_mct_tick_init(evt);
395}
396
397int local_timer_ack(void)
398{
399 return 0;
400}
401
402#endif /* CONFIG_LOCAL_TIMERS */
403
404static void __init exynos4_timer_resources(void)
405{
406 struct clk *mct_clk;
407 mct_clk = clk_get(NULL, "xtal");
408
409 clk_rate = clk_get_rate(mct_clk);
410}
411
412static void __init exynos4_timer_init(void)
413{
414 exynos4_timer_resources();
415 exynos4_clocksource_init();
416 exynos4_clockevent_init();
417}
418
419struct sys_timer exynos4_timer = {
420 .init = exynos4_timer_init,
421};
diff --git a/arch/arm/mach-s5pv310/platsmp.c b/arch/arm/mach-exynos4/platsmp.c
index 34093b069f67..6d35878ec1aa 100644
--- a/arch/arm/mach-s5pv310/platsmp.c
+++ b/arch/arm/mach-exynos4/platsmp.c
@@ -1,7 +1,7 @@
1/* linux/arch/arm/mach-s5pv310/platsmp.c 1/* linux/arch/arm/mach-exynos4/platsmp.c
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * Cloned from linux/arch/arm/mach-vexpress/platsmp.c 6 * Cloned from linux/arch/arm/mach-vexpress/platsmp.c
7 * 7 *
@@ -28,7 +28,7 @@
28#include <mach/hardware.h> 28#include <mach/hardware.h>
29#include <mach/regs-clock.h> 29#include <mach/regs-clock.h>
30 30
31extern void s5pv310_secondary_startup(void); 31extern void exynos4_secondary_startup(void);
32 32
33/* 33/*
34 * control for which core is the next to come out of the secondary 34 * control for which core is the next to come out of the secondary
@@ -139,7 +139,7 @@ void __init smp_init_cpus(void)
139 /* sanity check */ 139 /* sanity check */
140 if (ncores > NR_CPUS) { 140 if (ncores > NR_CPUS) {
141 printk(KERN_WARNING 141 printk(KERN_WARNING
142 "S5PV310: no. of cores (%d) greater than configured " 142 "EXYNOS4: no. of cores (%d) greater than configured "
143 "maximum of %d - clipping\n", 143 "maximum of %d - clipping\n",
144 ncores, NR_CPUS); 144 ncores, NR_CPUS);
145 ncores = NR_CPUS; 145 ncores = NR_CPUS;
@@ -168,5 +168,5 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
168 * until it receives a soft interrupt, and then the 168 * until it receives a soft interrupt, and then the
169 * secondary CPU branches to this address. 169 * secondary CPU branches to this address.
170 */ 170 */
171 __raw_writel(BSYM(virt_to_phys(s5pv310_secondary_startup)), S5P_VA_SYSRAM); 171 __raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)), S5P_VA_SYSRAM);
172} 172}
diff --git a/arch/arm/mach-exynos4/pm.c b/arch/arm/mach-exynos4/pm.c
new file mode 100644
index 000000000000..10d917d9e3ad
--- /dev/null
+++ b/arch/arm/mach-exynos4/pm.c
@@ -0,0 +1,420 @@
1/* linux/arch/arm/mach-exynos4/pm.c
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS4210 - Power Management support
7 *
8 * Based on arch/arm/mach-s3c2410/pm.c
9 * Copyright (c) 2006 Simtec Electronics
10 * Ben Dooks <ben@simtec.co.uk>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15*/
16
17#include <linux/init.h>
18#include <linux/suspend.h>
19#include <linux/io.h>
20
21#include <asm/cacheflush.h>
22#include <asm/hardware/cache-l2x0.h>
23
24#include <plat/cpu.h>
25#include <plat/pm.h>
26
27#include <mach/regs-irq.h>
28#include <mach/regs-gpio.h>
29#include <mach/regs-clock.h>
30#include <mach/regs-pmu.h>
31#include <mach/pm-core.h>
32
33static struct sleep_save exynos4_sleep[] = {
34 { .reg = S5P_ARM_CORE0_LOWPWR , .val = 0x2, },
35 { .reg = S5P_DIS_IRQ_CORE0 , .val = 0x0, },
36 { .reg = S5P_DIS_IRQ_CENTRAL0 , .val = 0x0, },
37 { .reg = S5P_ARM_CORE1_LOWPWR , .val = 0x2, },
38 { .reg = S5P_DIS_IRQ_CORE1 , .val = 0x0, },
39 { .reg = S5P_DIS_IRQ_CENTRAL1 , .val = 0x0, },
40 { .reg = S5P_ARM_COMMON_LOWPWR , .val = 0x2, },
41 { .reg = S5P_L2_0_LOWPWR , .val = 0x3, },
42 { .reg = S5P_L2_1_LOWPWR , .val = 0x3, },
43 { .reg = S5P_CMU_ACLKSTOP_LOWPWR , .val = 0x0, },
44 { .reg = S5P_CMU_SCLKSTOP_LOWPWR , .val = 0x0, },
45 { .reg = S5P_CMU_RESET_LOWPWR , .val = 0x0, },
46 { .reg = S5P_APLL_SYSCLK_LOWPWR , .val = 0x0, },
47 { .reg = S5P_MPLL_SYSCLK_LOWPWR , .val = 0x0, },
48 { .reg = S5P_VPLL_SYSCLK_LOWPWR , .val = 0x0, },
49 { .reg = S5P_EPLL_SYSCLK_LOWPWR , .val = 0x0, },
50 { .reg = S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR , .val = 0x0, },
51 { .reg = S5P_CMU_RESET_GPSALIVE_LOWPWR , .val = 0x0, },
52 { .reg = S5P_CMU_CLKSTOP_CAM_LOWPWR , .val = 0x0, },
53 { .reg = S5P_CMU_CLKSTOP_TV_LOWPWR , .val = 0x0, },
54 { .reg = S5P_CMU_CLKSTOP_MFC_LOWPWR , .val = 0x0, },
55 { .reg = S5P_CMU_CLKSTOP_G3D_LOWPWR , .val = 0x0, },
56 { .reg = S5P_CMU_CLKSTOP_LCD0_LOWPWR , .val = 0x0, },
57 { .reg = S5P_CMU_CLKSTOP_LCD1_LOWPWR , .val = 0x0, },
58 { .reg = S5P_CMU_CLKSTOP_MAUDIO_LOWPWR , .val = 0x0, },
59 { .reg = S5P_CMU_CLKSTOP_GPS_LOWPWR , .val = 0x0, },
60 { .reg = S5P_CMU_RESET_CAM_LOWPWR , .val = 0x0, },
61 { .reg = S5P_CMU_RESET_TV_LOWPWR , .val = 0x0, },
62 { .reg = S5P_CMU_RESET_MFC_LOWPWR , .val = 0x0, },
63 { .reg = S5P_CMU_RESET_G3D_LOWPWR , .val = 0x0, },
64 { .reg = S5P_CMU_RESET_LCD0_LOWPWR , .val = 0x0, },
65 { .reg = S5P_CMU_RESET_LCD1_LOWPWR , .val = 0x0, },
66 { .reg = S5P_CMU_RESET_MAUDIO_LOWPWR , .val = 0x0, },
67 { .reg = S5P_CMU_RESET_GPS_LOWPWR , .val = 0x0, },
68 { .reg = S5P_TOP_BUS_LOWPWR , .val = 0x0, },
69 { .reg = S5P_TOP_RETENTION_LOWPWR , .val = 0x1, },
70 { .reg = S5P_TOP_PWR_LOWPWR , .val = 0x3, },
71 { .reg = S5P_LOGIC_RESET_LOWPWR , .val = 0x0, },
72 { .reg = S5P_ONENAND_MEM_LOWPWR , .val = 0x0, },
73 { .reg = S5P_MODIMIF_MEM_LOWPWR , .val = 0x0, },
74 { .reg = S5P_G2D_ACP_MEM_LOWPWR , .val = 0x0, },
75 { .reg = S5P_USBOTG_MEM_LOWPWR , .val = 0x0, },
76 { .reg = S5P_HSMMC_MEM_LOWPWR , .val = 0x0, },
77 { .reg = S5P_CSSYS_MEM_LOWPWR , .val = 0x0, },
78 { .reg = S5P_SECSS_MEM_LOWPWR , .val = 0x0, },
79 { .reg = S5P_PCIE_MEM_LOWPWR , .val = 0x0, },
80 { .reg = S5P_SATA_MEM_LOWPWR , .val = 0x0, },
81 { .reg = S5P_PAD_RETENTION_DRAM_LOWPWR , .val = 0x0, },
82 { .reg = S5P_PAD_RETENTION_MAUDIO_LOWPWR , .val = 0x0, },
83 { .reg = S5P_PAD_RETENTION_GPIO_LOWPWR , .val = 0x0, },
84 { .reg = S5P_PAD_RETENTION_UART_LOWPWR , .val = 0x0, },
85 { .reg = S5P_PAD_RETENTION_MMCA_LOWPWR , .val = 0x0, },
86 { .reg = S5P_PAD_RETENTION_MMCB_LOWPWR , .val = 0x0, },
87 { .reg = S5P_PAD_RETENTION_EBIA_LOWPWR , .val = 0x0, },
88 { .reg = S5P_PAD_RETENTION_EBIB_LOWPWR , .val = 0x0, },
89 { .reg = S5P_PAD_RETENTION_ISOLATION_LOWPWR , .val = 0x0, },
90 { .reg = S5P_PAD_RETENTION_ALV_SEL_LOWPWR , .val = 0x0, },
91 { .reg = S5P_XUSBXTI_LOWPWR , .val = 0x0, },
92 { .reg = S5P_XXTI_LOWPWR , .val = 0x0, },
93 { .reg = S5P_EXT_REGULATOR_LOWPWR , .val = 0x0, },
94 { .reg = S5P_GPIO_MODE_LOWPWR , .val = 0x0, },
95 { .reg = S5P_GPIO_MODE_MAUDIO_LOWPWR , .val = 0x0, },
96 { .reg = S5P_CAM_LOWPWR , .val = 0x0, },
97 { .reg = S5P_TV_LOWPWR , .val = 0x0, },
98 { .reg = S5P_MFC_LOWPWR , .val = 0x0, },
99 { .reg = S5P_G3D_LOWPWR , .val = 0x0, },
100 { .reg = S5P_LCD0_LOWPWR , .val = 0x0, },
101 { .reg = S5P_LCD1_LOWPWR , .val = 0x0, },
102 { .reg = S5P_MAUDIO_LOWPWR , .val = 0x0, },
103 { .reg = S5P_GPS_LOWPWR , .val = 0x0, },
104 { .reg = S5P_GPS_ALIVE_LOWPWR , .val = 0x0, },
105};
106
107static struct sleep_save exynos4_set_clksrc[] = {
108 { .reg = S5P_CLKSRC_MASK_TOP , .val = 0x00000001, },
109 { .reg = S5P_CLKSRC_MASK_CAM , .val = 0x11111111, },
110 { .reg = S5P_CLKSRC_MASK_TV , .val = 0x00000111, },
111 { .reg = S5P_CLKSRC_MASK_LCD0 , .val = 0x00001111, },
112 { .reg = S5P_CLKSRC_MASK_LCD1 , .val = 0x00001111, },
113 { .reg = S5P_CLKSRC_MASK_MAUDIO , .val = 0x00000001, },
114 { .reg = S5P_CLKSRC_MASK_FSYS , .val = 0x01011111, },
115 { .reg = S5P_CLKSRC_MASK_PERIL0 , .val = 0x01111111, },
116 { .reg = S5P_CLKSRC_MASK_PERIL1 , .val = 0x01110111, },
117 { .reg = S5P_CLKSRC_MASK_DMC , .val = 0x00010000, },
118};
119
120static struct sleep_save exynos4_core_save[] = {
121 /* CMU side */
122 SAVE_ITEM(S5P_CLKDIV_LEFTBUS),
123 SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS),
124 SAVE_ITEM(S5P_CLKDIV_RIGHTBUS),
125 SAVE_ITEM(S5P_CLKGATE_IP_RIGHTBUS),
126 SAVE_ITEM(S5P_EPLL_CON0),
127 SAVE_ITEM(S5P_EPLL_CON1),
128 SAVE_ITEM(S5P_VPLL_CON0),
129 SAVE_ITEM(S5P_VPLL_CON1),
130 SAVE_ITEM(S5P_CLKSRC_TOP0),
131 SAVE_ITEM(S5P_CLKSRC_TOP1),
132 SAVE_ITEM(S5P_CLKSRC_CAM),
133 SAVE_ITEM(S5P_CLKSRC_MFC),
134 SAVE_ITEM(S5P_CLKSRC_IMAGE),
135 SAVE_ITEM(S5P_CLKSRC_LCD0),
136 SAVE_ITEM(S5P_CLKSRC_LCD1),
137 SAVE_ITEM(S5P_CLKSRC_MAUDIO),
138 SAVE_ITEM(S5P_CLKSRC_FSYS),
139 SAVE_ITEM(S5P_CLKSRC_PERIL0),
140 SAVE_ITEM(S5P_CLKSRC_PERIL1),
141 SAVE_ITEM(S5P_CLKDIV_CAM),
142 SAVE_ITEM(S5P_CLKDIV_TV),
143 SAVE_ITEM(S5P_CLKDIV_MFC),
144 SAVE_ITEM(S5P_CLKDIV_G3D),
145 SAVE_ITEM(S5P_CLKDIV_IMAGE),
146 SAVE_ITEM(S5P_CLKDIV_LCD0),
147 SAVE_ITEM(S5P_CLKDIV_LCD1),
148 SAVE_ITEM(S5P_CLKDIV_MAUDIO),
149 SAVE_ITEM(S5P_CLKDIV_FSYS0),
150 SAVE_ITEM(S5P_CLKDIV_FSYS1),
151 SAVE_ITEM(S5P_CLKDIV_FSYS2),
152 SAVE_ITEM(S5P_CLKDIV_FSYS3),
153 SAVE_ITEM(S5P_CLKDIV_PERIL0),
154 SAVE_ITEM(S5P_CLKDIV_PERIL1),
155 SAVE_ITEM(S5P_CLKDIV_PERIL2),
156 SAVE_ITEM(S5P_CLKDIV_PERIL3),
157 SAVE_ITEM(S5P_CLKDIV_PERIL4),
158 SAVE_ITEM(S5P_CLKDIV_PERIL5),
159 SAVE_ITEM(S5P_CLKDIV_TOP),
160 SAVE_ITEM(S5P_CLKSRC_MASK_CAM),
161 SAVE_ITEM(S5P_CLKSRC_MASK_TV),
162 SAVE_ITEM(S5P_CLKSRC_MASK_LCD0),
163 SAVE_ITEM(S5P_CLKSRC_MASK_LCD1),
164 SAVE_ITEM(S5P_CLKSRC_MASK_MAUDIO),
165 SAVE_ITEM(S5P_CLKSRC_MASK_FSYS),
166 SAVE_ITEM(S5P_CLKSRC_MASK_PERIL0),
167 SAVE_ITEM(S5P_CLKSRC_MASK_PERIL1),
168 SAVE_ITEM(S5P_CLKGATE_SCLKCAM),
169 SAVE_ITEM(S5P_CLKGATE_IP_CAM),
170 SAVE_ITEM(S5P_CLKGATE_IP_TV),
171 SAVE_ITEM(S5P_CLKGATE_IP_MFC),
172 SAVE_ITEM(S5P_CLKGATE_IP_G3D),
173 SAVE_ITEM(S5P_CLKGATE_IP_IMAGE),
174 SAVE_ITEM(S5P_CLKGATE_IP_LCD0),
175 SAVE_ITEM(S5P_CLKGATE_IP_LCD1),
176 SAVE_ITEM(S5P_CLKGATE_IP_FSYS),
177 SAVE_ITEM(S5P_CLKGATE_IP_GPS),
178 SAVE_ITEM(S5P_CLKGATE_IP_PERIL),
179 SAVE_ITEM(S5P_CLKGATE_IP_PERIR),
180 SAVE_ITEM(S5P_CLKGATE_BLOCK),
181 SAVE_ITEM(S5P_CLKSRC_MASK_DMC),
182 SAVE_ITEM(S5P_CLKSRC_DMC),
183 SAVE_ITEM(S5P_CLKDIV_DMC0),
184 SAVE_ITEM(S5P_CLKDIV_DMC1),
185 SAVE_ITEM(S5P_CLKGATE_IP_DMC),
186 SAVE_ITEM(S5P_CLKSRC_CPU),
187 SAVE_ITEM(S5P_CLKDIV_CPU),
188 SAVE_ITEM(S5P_CLKGATE_SCLKCPU),
189 SAVE_ITEM(S5P_CLKGATE_IP_CPU),
190 /* GIC side */
191 SAVE_ITEM(S5P_VA_GIC_CPU + 0x000),
192 SAVE_ITEM(S5P_VA_GIC_CPU + 0x004),
193 SAVE_ITEM(S5P_VA_GIC_CPU + 0x008),
194 SAVE_ITEM(S5P_VA_GIC_CPU + 0x00C),
195 SAVE_ITEM(S5P_VA_GIC_CPU + 0x014),
196 SAVE_ITEM(S5P_VA_GIC_CPU + 0x018),
197 SAVE_ITEM(S5P_VA_GIC_DIST + 0x000),
198 SAVE_ITEM(S5P_VA_GIC_DIST + 0x004),
199 SAVE_ITEM(S5P_VA_GIC_DIST + 0x100),
200 SAVE_ITEM(S5P_VA_GIC_DIST + 0x104),
201 SAVE_ITEM(S5P_VA_GIC_DIST + 0x108),
202 SAVE_ITEM(S5P_VA_GIC_DIST + 0x300),
203 SAVE_ITEM(S5P_VA_GIC_DIST + 0x304),
204 SAVE_ITEM(S5P_VA_GIC_DIST + 0x308),
205 SAVE_ITEM(S5P_VA_GIC_DIST + 0x400),
206 SAVE_ITEM(S5P_VA_GIC_DIST + 0x404),
207 SAVE_ITEM(S5P_VA_GIC_DIST + 0x408),
208 SAVE_ITEM(S5P_VA_GIC_DIST + 0x40C),
209 SAVE_ITEM(S5P_VA_GIC_DIST + 0x410),
210 SAVE_ITEM(S5P_VA_GIC_DIST + 0x414),
211 SAVE_ITEM(S5P_VA_GIC_DIST + 0x418),
212 SAVE_ITEM(S5P_VA_GIC_DIST + 0x41C),
213 SAVE_ITEM(S5P_VA_GIC_DIST + 0x420),
214 SAVE_ITEM(S5P_VA_GIC_DIST + 0x424),
215 SAVE_ITEM(S5P_VA_GIC_DIST + 0x428),
216 SAVE_ITEM(S5P_VA_GIC_DIST + 0x42C),
217 SAVE_ITEM(S5P_VA_GIC_DIST + 0x430),
218 SAVE_ITEM(S5P_VA_GIC_DIST + 0x434),
219 SAVE_ITEM(S5P_VA_GIC_DIST + 0x438),
220 SAVE_ITEM(S5P_VA_GIC_DIST + 0x43C),
221 SAVE_ITEM(S5P_VA_GIC_DIST + 0x440),
222 SAVE_ITEM(S5P_VA_GIC_DIST + 0x444),
223 SAVE_ITEM(S5P_VA_GIC_DIST + 0x448),
224 SAVE_ITEM(S5P_VA_GIC_DIST + 0x44C),
225 SAVE_ITEM(S5P_VA_GIC_DIST + 0x450),
226 SAVE_ITEM(S5P_VA_GIC_DIST + 0x454),
227 SAVE_ITEM(S5P_VA_GIC_DIST + 0x458),
228 SAVE_ITEM(S5P_VA_GIC_DIST + 0x45C),
229
230 SAVE_ITEM(S5P_VA_GIC_DIST + 0x800),
231 SAVE_ITEM(S5P_VA_GIC_DIST + 0x804),
232 SAVE_ITEM(S5P_VA_GIC_DIST + 0x808),
233 SAVE_ITEM(S5P_VA_GIC_DIST + 0x80C),
234 SAVE_ITEM(S5P_VA_GIC_DIST + 0x810),
235 SAVE_ITEM(S5P_VA_GIC_DIST + 0x814),
236 SAVE_ITEM(S5P_VA_GIC_DIST + 0x818),
237 SAVE_ITEM(S5P_VA_GIC_DIST + 0x81C),
238 SAVE_ITEM(S5P_VA_GIC_DIST + 0x820),
239 SAVE_ITEM(S5P_VA_GIC_DIST + 0x824),
240 SAVE_ITEM(S5P_VA_GIC_DIST + 0x828),
241 SAVE_ITEM(S5P_VA_GIC_DIST + 0x82C),
242 SAVE_ITEM(S5P_VA_GIC_DIST + 0x830),
243 SAVE_ITEM(S5P_VA_GIC_DIST + 0x834),
244 SAVE_ITEM(S5P_VA_GIC_DIST + 0x838),
245 SAVE_ITEM(S5P_VA_GIC_DIST + 0x83C),
246 SAVE_ITEM(S5P_VA_GIC_DIST + 0x840),
247 SAVE_ITEM(S5P_VA_GIC_DIST + 0x844),
248 SAVE_ITEM(S5P_VA_GIC_DIST + 0x848),
249 SAVE_ITEM(S5P_VA_GIC_DIST + 0x84C),
250 SAVE_ITEM(S5P_VA_GIC_DIST + 0x850),
251 SAVE_ITEM(S5P_VA_GIC_DIST + 0x854),
252 SAVE_ITEM(S5P_VA_GIC_DIST + 0x858),
253 SAVE_ITEM(S5P_VA_GIC_DIST + 0x85C),
254
255 SAVE_ITEM(S5P_VA_GIC_DIST + 0xC00),
256 SAVE_ITEM(S5P_VA_GIC_DIST + 0xC04),
257 SAVE_ITEM(S5P_VA_GIC_DIST + 0xC08),
258 SAVE_ITEM(S5P_VA_GIC_DIST + 0xC0C),
259 SAVE_ITEM(S5P_VA_GIC_DIST + 0xC10),
260 SAVE_ITEM(S5P_VA_GIC_DIST + 0xC14),
261
262 SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x000),
263 SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x010),
264 SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x020),
265 SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x030),
266 SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x040),
267 SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x050),
268 SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x060),
269 SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x070),
270 SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x080),
271 SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x090),
272};
273
274static struct sleep_save exynos4_l2cc_save[] = {
275 SAVE_ITEM(S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL),
276 SAVE_ITEM(S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL),
277 SAVE_ITEM(S5P_VA_L2CC + L2X0_PREFETCH_CTRL),
278 SAVE_ITEM(S5P_VA_L2CC + L2X0_POWER_CTRL),
279 SAVE_ITEM(S5P_VA_L2CC + L2X0_AUX_CTRL),
280};
281
282void exynos4_cpu_suspend(void)
283{
284 unsigned long tmp;
285 unsigned long mask = 0xFFFFFFFF;
286
287 /* Setting Central Sequence Register for power down mode */
288
289 tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
290 tmp &= ~(S5P_CENTRAL_LOWPWR_CFG);
291 __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
292
293 /* Setting Central Sequence option Register */
294
295 tmp = __raw_readl(S5P_CENTRAL_SEQ_OPTION);
296 tmp &= ~(S5P_USE_MASK);
297 tmp |= S5P_USE_STANDBY_WFI0;
298 __raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
299
300 /* Clear all interrupt pending to avoid early wakeup */
301
302 __raw_writel(mask, (S5P_VA_GIC_DIST + 0x280));
303 __raw_writel(mask, (S5P_VA_GIC_DIST + 0x284));
304 __raw_writel(mask, (S5P_VA_GIC_DIST + 0x288));
305
306 /* Disable all interrupt */
307
308 __raw_writel(0x0, (S5P_VA_GIC_CPU + 0x000));
309 __raw_writel(0x0, (S5P_VA_GIC_DIST + 0x000));
310 __raw_writel(mask, (S5P_VA_GIC_DIST + 0x184));
311 __raw_writel(mask, (S5P_VA_GIC_DIST + 0x188));
312
313 outer_flush_all();
314
315 /* issue the standby signal into the pm unit. */
316 cpu_do_idle();
317
318 /* we should never get past here */
319 panic("sleep resumed to originator?");
320}
321
322static void exynos4_pm_prepare(void)
323{
324 u32 tmp;
325
326 s3c_pm_do_save(exynos4_core_save, ARRAY_SIZE(exynos4_core_save));
327 s3c_pm_do_save(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save));
328
329 tmp = __raw_readl(S5P_INFORM1);
330
331 /* Set value of power down register for sleep mode */
332
333 s3c_pm_do_restore_core(exynos4_sleep, ARRAY_SIZE(exynos4_sleep));
334 __raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
335
336 /* ensure at least INFORM0 has the resume address */
337
338 __raw_writel(virt_to_phys(s3c_cpu_resume), S5P_INFORM0);
339
340 /* Before enter central sequence mode, clock src register have to set */
341
342 s3c_pm_do_restore_core(exynos4_set_clksrc, ARRAY_SIZE(exynos4_set_clksrc));
343
344}
345
346static int exynos4_pm_add(struct sys_device *sysdev)
347{
348 pm_cpu_prep = exynos4_pm_prepare;
349 pm_cpu_sleep = exynos4_cpu_suspend;
350
351 return 0;
352}
353
354/* This function copy from linux/arch/arm/kernel/smp_scu.c */
355
356void exynos4_scu_enable(void __iomem *scu_base)
357{
358 u32 scu_ctrl;
359
360 scu_ctrl = __raw_readl(scu_base);
361 /* already enabled? */
362 if (scu_ctrl & 1)
363 return;
364
365 scu_ctrl |= 1;
366 __raw_writel(scu_ctrl, scu_base);
367
368 /*
369 * Ensure that the data accessed by CPU0 before the SCU was
370 * initialised is visible to the other CPUs.
371 */
372 flush_cache_all();
373}
374
375static int exynos4_pm_resume(struct sys_device *dev)
376{
377 /* For release retention */
378
379 __raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
380 __raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION);
381 __raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION);
382 __raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION);
383 __raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION);
384 __raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
385 __raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);
386
387 s3c_pm_do_restore_core(exynos4_core_save, ARRAY_SIZE(exynos4_core_save));
388
389 exynos4_scu_enable(S5P_VA_SCU);
390
391#ifdef CONFIG_CACHE_L2X0
392 s3c_pm_do_restore_core(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save));
393 outer_inv_all();
394 /* enable L2X0*/
395 writel_relaxed(1, S5P_VA_L2CC + L2X0_CTRL);
396#endif
397
398 return 0;
399}
400
401static struct sysdev_driver exynos4_pm_driver = {
402 .add = exynos4_pm_add,
403 .resume = exynos4_pm_resume,
404};
405
406static __init int exynos4_pm_drvinit(void)
407{
408 unsigned int tmp;
409
410 s3c_pm_init();
411
412 /* All wakeup disable */
413
414 tmp = __raw_readl(S5P_WAKEUP_MASK);
415 tmp |= ((0xFF << 8) | (0x1F << 1));
416 __raw_writel(tmp, S5P_WAKEUP_MASK);
417
418 return sysdev_driver_register(&exynos4_sysclass, &exynos4_pm_driver);
419}
420arch_initcall(exynos4_pm_drvinit);
diff --git a/arch/arm/mach-exynos4/setup-fimc.c b/arch/arm/mach-exynos4/setup-fimc.c
new file mode 100644
index 000000000000..6a45078d9d12
--- /dev/null
+++ b/arch/arm/mach-exynos4/setup-fimc.c
@@ -0,0 +1,44 @@
1/*
2 * Copyright (C) 2011 Samsung Electronics Co., Ltd.
3 *
4 * Exynos4 camera interface GPIO configuration.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/gpio.h>
12#include <plat/gpio-cfg.h>
13#include <plat/camport.h>
14
15int exynos4_fimc_setup_gpio(enum s5p_camport_id id)
16{
17 u32 gpio8, gpio5;
18 u32 sfn;
19 int ret;
20
21 switch (id) {
22 case S5P_CAMPORT_A:
23 gpio8 = EXYNOS4_GPJ0(0); /* PCLK, VSYNC, HREF, DATA[0:4] */
24 gpio5 = EXYNOS4_GPJ1(0); /* DATA[5:7], CLKOUT, FIELD */
25 sfn = S3C_GPIO_SFN(2);
26 break;
27
28 case S5P_CAMPORT_B:
29 gpio8 = EXYNOS4_GPE0(0); /* DATA[0:7] */
30 gpio5 = EXYNOS4_GPE1(0); /* PCLK, VSYNC, HREF, CLKOUT, FIELD */
31 sfn = S3C_GPIO_SFN(3);
32 break;
33
34 default:
35 WARN(1, "Wrong camport id: %d\n", id);
36 return -EINVAL;
37 }
38
39 ret = s3c_gpio_cfgall_range(gpio8, 8, sfn, S3C_GPIO_PULL_UP);
40 if (ret)
41 return ret;
42
43 return s3c_gpio_cfgall_range(gpio5, 5, sfn, S3C_GPIO_PULL_UP);
44}
diff --git a/arch/arm/mach-s5pv310/setup-i2c0.c b/arch/arm/mach-exynos4/setup-i2c0.c
index f47f8f3152ec..d395bd17c38b 100644
--- a/arch/arm/mach-s5pv310/setup-i2c0.c
+++ b/arch/arm/mach-exynos4/setup-i2c0.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * linux/arch/arm/mach-s5pv310/setup-i2c0.c 2 * linux/arch/arm/mach-exynos4/setup-i2c0.c
3 * 3 *
4 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd. 4 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com/ 5 * http://www.samsung.com/
@@ -21,6 +21,6 @@ struct platform_device; /* don't need the contents */
21 21
22void s3c_i2c0_cfg_gpio(struct platform_device *dev) 22void s3c_i2c0_cfg_gpio(struct platform_device *dev)
23{ 23{
24 s3c_gpio_cfgall_range(S5PV310_GPD1(0), 2, 24 s3c_gpio_cfgall_range(EXYNOS4_GPD1(0), 2,
25 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); 25 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
26} 26}
diff --git a/arch/arm/mach-s5pv310/setup-i2c1.c b/arch/arm/mach-exynos4/setup-i2c1.c
index 9d07e4e2f14c..fd7235a43f6e 100644
--- a/arch/arm/mach-s5pv310/setup-i2c1.c
+++ b/arch/arm/mach-exynos4/setup-i2c1.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * linux/arch/arm/mach-s5pv310/setup-i2c1.c 2 * linux/arch/arm/mach-exynos4/setup-i2c1.c
3 * 3 *
4 * Copyright (C) 2010 Samsung Electronics Co., Ltd. 4 * Copyright (C) 2010 Samsung Electronics Co., Ltd.
5 * 5 *
@@ -18,6 +18,6 @@ struct platform_device; /* don't need the contents */
18 18
19void s3c_i2c1_cfg_gpio(struct platform_device *dev) 19void s3c_i2c1_cfg_gpio(struct platform_device *dev)
20{ 20{
21 s3c_gpio_cfgall_range(S5PV310_GPD1(2), 2, 21 s3c_gpio_cfgall_range(EXYNOS4_GPD1(2), 2,
22 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); 22 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
23} 23}
diff --git a/arch/arm/mach-s5pv310/setup-i2c2.c b/arch/arm/mach-exynos4/setup-i2c2.c
index 4163b1233daf..2694b19e8b37 100644
--- a/arch/arm/mach-s5pv310/setup-i2c2.c
+++ b/arch/arm/mach-exynos4/setup-i2c2.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * linux/arch/arm/mach-s5pv310/setup-i2c2.c 2 * linux/arch/arm/mach-exynos4/setup-i2c2.c
3 * 3 *
4 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd. 4 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
5 * 5 *
@@ -18,6 +18,6 @@ struct platform_device; /* don't need the contents */
18 18
19void s3c_i2c2_cfg_gpio(struct platform_device *dev) 19void s3c_i2c2_cfg_gpio(struct platform_device *dev)
20{ 20{
21 s3c_gpio_cfgall_range(S5PV310_GPA0(6), 2, 21 s3c_gpio_cfgall_range(EXYNOS4_GPA0(6), 2,
22 S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP); 22 S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
23} 23}
diff --git a/arch/arm/mach-s5pv310/setup-i2c3.c b/arch/arm/mach-exynos4/setup-i2c3.c
index 180f153d2a20..379bd306993f 100644
--- a/arch/arm/mach-s5pv310/setup-i2c3.c
+++ b/arch/arm/mach-exynos4/setup-i2c3.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * linux/arch/arm/mach-s5pv310/setup-i2c3.c 2 * linux/arch/arm/mach-exynos4/setup-i2c3.c
3 * 3 *
4 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 4 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
5 * 5 *
@@ -18,6 +18,6 @@ struct platform_device; /* don't need the contents */
18 18
19void s3c_i2c3_cfg_gpio(struct platform_device *dev) 19void s3c_i2c3_cfg_gpio(struct platform_device *dev)
20{ 20{
21 s3c_gpio_cfgall_range(S5PV310_GPA1(2), 2, 21 s3c_gpio_cfgall_range(EXYNOS4_GPA1(2), 2,
22 S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP); 22 S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
23} 23}
diff --git a/arch/arm/mach-s5pv310/setup-i2c4.c b/arch/arm/mach-exynos4/setup-i2c4.c
index 909e8dfc5316..9f3c04855b76 100644
--- a/arch/arm/mach-s5pv310/setup-i2c4.c
+++ b/arch/arm/mach-exynos4/setup-i2c4.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * linux/arch/arm/mach-s5pv310/setup-i2c4.c 2 * linux/arch/arm/mach-exynos4/setup-i2c4.c
3 * 3 *
4 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 4 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
5 * 5 *
@@ -18,6 +18,6 @@ struct platform_device; /* don't need the contents */
18 18
19void s3c_i2c4_cfg_gpio(struct platform_device *dev) 19void s3c_i2c4_cfg_gpio(struct platform_device *dev)
20{ 20{
21 s3c_gpio_cfgall_range(S5PV310_GPB(2), 2, 21 s3c_gpio_cfgall_range(EXYNOS4_GPB(2), 2,
22 S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP); 22 S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
23} 23}
diff --git a/arch/arm/mach-s5pv310/setup-i2c5.c b/arch/arm/mach-exynos4/setup-i2c5.c
index 5d0fa4ac0283..77e1a1e57c76 100644
--- a/arch/arm/mach-s5pv310/setup-i2c5.c
+++ b/arch/arm/mach-exynos4/setup-i2c5.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * linux/arch/arm/mach-s5pv310/setup-i2c5.c 2 * linux/arch/arm/mach-exynos4/setup-i2c5.c
3 * 3 *
4 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 4 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
5 * 5 *
@@ -18,6 +18,6 @@ struct platform_device; /* don't need the contents */
18 18
19void s3c_i2c5_cfg_gpio(struct platform_device *dev) 19void s3c_i2c5_cfg_gpio(struct platform_device *dev)
20{ 20{
21 s3c_gpio_cfgall_range(S5PV310_GPB(6), 2, 21 s3c_gpio_cfgall_range(EXYNOS4_GPB(6), 2,
22 S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP); 22 S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
23} 23}
diff --git a/arch/arm/mach-s5pv310/setup-i2c6.c b/arch/arm/mach-exynos4/setup-i2c6.c
index 34aafab92ac4..284d12b7af0e 100644
--- a/arch/arm/mach-s5pv310/setup-i2c6.c
+++ b/arch/arm/mach-exynos4/setup-i2c6.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * linux/arch/arm/mach-s5pv310/setup-i2c6.c 2 * linux/arch/arm/mach-exynos4/setup-i2c6.c
3 * 3 *
4 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 4 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
5 * 5 *
@@ -18,6 +18,6 @@ struct platform_device; /* don't need the contents */
18 18
19void s3c_i2c6_cfg_gpio(struct platform_device *dev) 19void s3c_i2c6_cfg_gpio(struct platform_device *dev)
20{ 20{
21 s3c_gpio_cfgall_range(S5PV310_GPC1(3), 2, 21 s3c_gpio_cfgall_range(EXYNOS4_GPC1(3), 2,
22 S3C_GPIO_SFN(4), S3C_GPIO_PULL_UP); 22 S3C_GPIO_SFN(4), S3C_GPIO_PULL_UP);
23} 23}
diff --git a/arch/arm/mach-s5pv310/setup-i2c7.c b/arch/arm/mach-exynos4/setup-i2c7.c
index 9b25b8d18920..b7611ee359a2 100644
--- a/arch/arm/mach-s5pv310/setup-i2c7.c
+++ b/arch/arm/mach-exynos4/setup-i2c7.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * linux/arch/arm/mach-s5pv310/setup-i2c7.c 2 * linux/arch/arm/mach-exynos4/setup-i2c7.c
3 * 3 *
4 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 4 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
5 * 5 *
@@ -18,6 +18,6 @@ struct platform_device; /* don't need the contents */
18 18
19void s3c_i2c7_cfg_gpio(struct platform_device *dev) 19void s3c_i2c7_cfg_gpio(struct platform_device *dev)
20{ 20{
21 s3c_gpio_cfgall_range(S5PV310_GPD0(2), 2, 21 s3c_gpio_cfgall_range(EXYNOS4_GPD0(2), 2,
22 S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP); 22 S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
23} 23}
diff --git a/arch/arm/mach-exynos4/setup-keypad.c b/arch/arm/mach-exynos4/setup-keypad.c
new file mode 100644
index 000000000000..1ee0ebff111f
--- /dev/null
+++ b/arch/arm/mach-exynos4/setup-keypad.c
@@ -0,0 +1,35 @@
1/* linux/arch/arm/mach-exynos4/setup-keypad.c
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * GPIO configuration for Exynos4 KeyPad device
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/gpio.h>
14#include <plat/gpio-cfg.h>
15
16void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols)
17{
18 /* Keypads can be of various combinations, Just making sure */
19
20 if (rows > 8) {
21 /* Set all the necessary GPX2 pins: KP_ROW[0~7] */
22 s3c_gpio_cfgrange_nopull(EXYNOS4_GPX2(0), 8, S3C_GPIO_SFN(3));
23
24 /* Set all the necessary GPX3 pins: KP_ROW[8~] */
25 s3c_gpio_cfgrange_nopull(EXYNOS4_GPX3(0), (rows - 8),
26 S3C_GPIO_SFN(3));
27 } else {
28 /* Set all the necessary GPX2 pins: KP_ROW[x] */
29 s3c_gpio_cfgrange_nopull(EXYNOS4_GPX2(0), rows,
30 S3C_GPIO_SFN(3));
31 }
32
33 /* Set all the necessary GPX1 pins to special-function 3: KP_COL[x] */
34 s3c_gpio_cfgrange_nopull(EXYNOS4_GPX1(0), cols, S3C_GPIO_SFN(3));
35}
diff --git a/arch/arm/mach-s5pv310/setup-sdhci-gpio.c b/arch/arm/mach-exynos4/setup-sdhci-gpio.c
index 86d38cc49135..1b3d3a2de95c 100644
--- a/arch/arm/mach-s5pv310/setup-sdhci-gpio.c
+++ b/arch/arm/mach-exynos4/setup-sdhci-gpio.c
@@ -1,9 +1,9 @@
1/* linux/arch/arm/mach-s5pv310/setup-sdhci-gpio.c 1/* linux/arch/arm/mach-exynos4/setup-sdhci-gpio.c
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * S5PV310 - Helper functions for setting up SDHCI device(s) GPIO (HSMMC) 6 * EXYNOS4 - Helper functions for setting up SDHCI device(s) GPIO (HSMMC)
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
@@ -23,13 +23,13 @@
23#include <plat/regs-sdhci.h> 23#include <plat/regs-sdhci.h>
24#include <plat/sdhci.h> 24#include <plat/sdhci.h>
25 25
26void s5pv310_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width) 26void exynos4_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
27{ 27{
28 struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; 28 struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
29 unsigned int gpio; 29 unsigned int gpio;
30 30
31 /* Set all the necessary GPK0[0:1] pins to special-function 2 */ 31 /* Set all the necessary GPK0[0:1] pins to special-function 2 */
32 for (gpio = S5PV310_GPK0(0); gpio < S5PV310_GPK0(2); gpio++) { 32 for (gpio = EXYNOS4_GPK0(0); gpio < EXYNOS4_GPK0(2); gpio++) {
33 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); 33 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
34 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); 34 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
35 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); 35 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
@@ -37,14 +37,14 @@ void s5pv310_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
37 37
38 switch (width) { 38 switch (width) {
39 case 8: 39 case 8:
40 for (gpio = S5PV310_GPK1(3); gpio <= S5PV310_GPK1(6); gpio++) { 40 for (gpio = EXYNOS4_GPK1(3); gpio <= EXYNOS4_GPK1(6); gpio++) {
41 /* Data pin GPK1[3:6] to special-funtion 3 */ 41 /* Data pin GPK1[3:6] to special-funtion 3 */
42 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3)); 42 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
43 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); 43 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
44 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); 44 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
45 } 45 }
46 case 4: 46 case 4:
47 for (gpio = S5PV310_GPK0(3); gpio <= S5PV310_GPK0(6); gpio++) { 47 for (gpio = EXYNOS4_GPK0(3); gpio <= EXYNOS4_GPK0(6); gpio++) {
48 /* Data pin GPK0[3:6] to special-funtion 2 */ 48 /* Data pin GPK0[3:6] to special-funtion 2 */
49 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); 49 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
50 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); 50 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
@@ -55,25 +55,25 @@ void s5pv310_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
55 } 55 }
56 56
57 if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { 57 if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
58 s3c_gpio_cfgpin(S5PV310_GPK0(2), S3C_GPIO_SFN(2)); 58 s3c_gpio_cfgpin(EXYNOS4_GPK0(2), S3C_GPIO_SFN(2));
59 s3c_gpio_setpull(S5PV310_GPK0(2), S3C_GPIO_PULL_UP); 59 s3c_gpio_setpull(EXYNOS4_GPK0(2), S3C_GPIO_PULL_UP);
60 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); 60 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
61 } 61 }
62} 62}
63 63
64void s5pv310_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width) 64void exynos4_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
65{ 65{
66 struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; 66 struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
67 unsigned int gpio; 67 unsigned int gpio;
68 68
69 /* Set all the necessary GPK1[0:1] pins to special-function 2 */ 69 /* Set all the necessary GPK1[0:1] pins to special-function 2 */
70 for (gpio = S5PV310_GPK1(0); gpio < S5PV310_GPK1(2); gpio++) { 70 for (gpio = EXYNOS4_GPK1(0); gpio < EXYNOS4_GPK1(2); gpio++) {
71 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); 71 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
72 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); 72 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
73 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); 73 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
74 } 74 }
75 75
76 for (gpio = S5PV310_GPK1(3); gpio <= S5PV310_GPK1(6); gpio++) { 76 for (gpio = EXYNOS4_GPK1(3); gpio <= EXYNOS4_GPK1(6); gpio++) {
77 /* Data pin GPK1[3:6] to special-function 2 */ 77 /* Data pin GPK1[3:6] to special-function 2 */
78 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); 78 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
79 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); 79 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
@@ -81,19 +81,19 @@ void s5pv310_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
81 } 81 }
82 82
83 if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { 83 if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
84 s3c_gpio_cfgpin(S5PV310_GPK1(2), S3C_GPIO_SFN(2)); 84 s3c_gpio_cfgpin(EXYNOS4_GPK1(2), S3C_GPIO_SFN(2));
85 s3c_gpio_setpull(S5PV310_GPK1(2), S3C_GPIO_PULL_UP); 85 s3c_gpio_setpull(EXYNOS4_GPK1(2), S3C_GPIO_PULL_UP);
86 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); 86 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
87 } 87 }
88} 88}
89 89
90void s5pv310_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width) 90void exynos4_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
91{ 91{
92 struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; 92 struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
93 unsigned int gpio; 93 unsigned int gpio;
94 94
95 /* Set all the necessary GPK2[0:1] pins to special-function 2 */ 95 /* Set all the necessary GPK2[0:1] pins to special-function 2 */
96 for (gpio = S5PV310_GPK2(0); gpio < S5PV310_GPK2(2); gpio++) { 96 for (gpio = EXYNOS4_GPK2(0); gpio < EXYNOS4_GPK2(2); gpio++) {
97 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); 97 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
98 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); 98 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
99 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); 99 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
@@ -101,14 +101,14 @@ void s5pv310_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
101 101
102 switch (width) { 102 switch (width) {
103 case 8: 103 case 8:
104 for (gpio = S5PV310_GPK3(3); gpio <= S5PV310_GPK3(6); gpio++) { 104 for (gpio = EXYNOS4_GPK3(3); gpio <= EXYNOS4_GPK3(6); gpio++) {
105 /* Data pin GPK3[3:6] to special-function 3 */ 105 /* Data pin GPK3[3:6] to special-function 3 */
106 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3)); 106 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
107 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); 107 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
108 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); 108 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
109 } 109 }
110 case 4: 110 case 4:
111 for (gpio = S5PV310_GPK2(3); gpio <= S5PV310_GPK2(6); gpio++) { 111 for (gpio = EXYNOS4_GPK2(3); gpio <= EXYNOS4_GPK2(6); gpio++) {
112 /* Data pin GPK2[3:6] to special-function 2 */ 112 /* Data pin GPK2[3:6] to special-function 2 */
113 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); 113 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
114 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); 114 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
@@ -119,25 +119,25 @@ void s5pv310_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
119 } 119 }
120 120
121 if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { 121 if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
122 s3c_gpio_cfgpin(S5PV310_GPK2(2), S3C_GPIO_SFN(2)); 122 s3c_gpio_cfgpin(EXYNOS4_GPK2(2), S3C_GPIO_SFN(2));
123 s3c_gpio_setpull(S5PV310_GPK2(2), S3C_GPIO_PULL_UP); 123 s3c_gpio_setpull(EXYNOS4_GPK2(2), S3C_GPIO_PULL_UP);
124 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); 124 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
125 } 125 }
126} 126}
127 127
128void s5pv310_setup_sdhci3_cfg_gpio(struct platform_device *dev, int width) 128void exynos4_setup_sdhci3_cfg_gpio(struct platform_device *dev, int width)
129{ 129{
130 struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; 130 struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
131 unsigned int gpio; 131 unsigned int gpio;
132 132
133 /* Set all the necessary GPK3[0:1] pins to special-function 2 */ 133 /* Set all the necessary GPK3[0:1] pins to special-function 2 */
134 for (gpio = S5PV310_GPK3(0); gpio < S5PV310_GPK3(2); gpio++) { 134 for (gpio = EXYNOS4_GPK3(0); gpio < EXYNOS4_GPK3(2); gpio++) {
135 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); 135 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
136 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); 136 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
137 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); 137 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
138 } 138 }
139 139
140 for (gpio = S5PV310_GPK3(3); gpio <= S5PV310_GPK3(6); gpio++) { 140 for (gpio = EXYNOS4_GPK3(3); gpio <= EXYNOS4_GPK3(6); gpio++) {
141 /* Data pin GPK3[3:6] to special-function 2 */ 141 /* Data pin GPK3[3:6] to special-function 2 */
142 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); 142 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
143 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); 143 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
@@ -145,8 +145,8 @@ void s5pv310_setup_sdhci3_cfg_gpio(struct platform_device *dev, int width)
145 } 145 }
146 146
147 if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { 147 if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
148 s3c_gpio_cfgpin(S5PV310_GPK3(2), S3C_GPIO_SFN(2)); 148 s3c_gpio_cfgpin(EXYNOS4_GPK3(2), S3C_GPIO_SFN(2));
149 s3c_gpio_setpull(S5PV310_GPK3(2), S3C_GPIO_PULL_UP); 149 s3c_gpio_setpull(EXYNOS4_GPK3(2), S3C_GPIO_PULL_UP);
150 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); 150 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
151 } 151 }
152} 152}
diff --git a/arch/arm/mach-s5pv310/setup-sdhci.c b/arch/arm/mach-exynos4/setup-sdhci.c
index db8358fc4662..85f9433d4836 100644
--- a/arch/arm/mach-s5pv310/setup-sdhci.c
+++ b/arch/arm/mach-exynos4/setup-sdhci.c
@@ -1,9 +1,9 @@
1/* linux/arch/arm/mach-s5pv310/setup-sdhci.c 1/* linux/arch/arm/mach-exynos4/setup-sdhci.c
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * S5PV310 - Helper functions for settign up SDHCI device(s) (HSMMC) 6 * EXYNOS4 - Helper functions for settign up SDHCI device(s) (HSMMC)
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
@@ -23,14 +23,14 @@
23 23
24/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */ 24/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
25 25
26char *s5pv310_hsmmc_clksrcs[4] = { 26char *exynos4_hsmmc_clksrcs[4] = {
27 [0] = NULL, 27 [0] = NULL,
28 [1] = NULL, 28 [1] = NULL,
29 [2] = "sclk_mmc", /* mmc_bus */ 29 [2] = "sclk_mmc", /* mmc_bus */
30 [3] = NULL, 30 [3] = NULL,
31}; 31};
32 32
33void s5pv310_setup_sdhci_cfg_card(struct platform_device *dev, void __iomem *r, 33void exynos4_setup_sdhci_cfg_card(struct platform_device *dev, void __iomem *r,
34 struct mmc_ios *ios, struct mmc_card *card) 34 struct mmc_ios *ios, struct mmc_card *card)
35{ 35{
36 u32 ctrl2, ctrl3; 36 u32 ctrl2, ctrl3;
diff --git a/arch/arm/mach-exynos4/sleep.S b/arch/arm/mach-exynos4/sleep.S
new file mode 100644
index 000000000000..6b62425417a6
--- /dev/null
+++ b/arch/arm/mach-exynos4/sleep.S
@@ -0,0 +1,76 @@
1/* linux/arch/arm/mach-exynos4/sleep.S
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS4210 power Manager (Suspend-To-RAM) support
7 * Based on S3C2410 sleep code by:
8 * Ben Dooks, (c) 2004 Simtec Electronics
9 *
10 * Based on PXA/SA1100 sleep code by:
11 * Nicolas Pitre, (c) 2002 Monta Vista Software Inc
12 * Cliff Brake, (c) 2001
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
27*/
28
29#include <linux/linkage.h>
30#include <asm/assembler.h>
31#include <asm/memory.h>
32
33 .text
34
35 /*
36 * s3c_cpu_save
37 *
38 * entry:
39 * r1 = v:p offset
40 */
41
42ENTRY(s3c_cpu_save)
43
44 stmfd sp!, { r3 - r12, lr }
45 ldr r3, =resume_with_mmu
46 bl cpu_suspend
47
48 ldr r0, =pm_cpu_sleep
49 ldr r0, [ r0 ]
50 mov pc, r0
51
52resume_with_mmu:
53 ldmfd sp!, { r3 - r12, pc }
54
55 .ltorg
56
57 /*
58 * sleep magic, to allow the bootloader to check for an valid
59 * image to resume to. Must be the first word before the
60 * s3c_cpu_resume entry.
61 */
62
63 .word 0x2bedf00d
64
65 /*
66 * s3c_cpu_resume
67 *
68 * resume code entry for bootloader to call
69 *
70 * we must put this code here in the data segment as we have no
71 * other way of restoring the stack pointer after sleep, and we
72 * must not write to the code segment (code is read-only)
73 */
74
75ENTRY(s3c_cpu_resume)
76 b cpu_resume
diff --git a/arch/arm/mach-s5pv310/time.c b/arch/arm/mach-exynos4/time.c
index b262d4615331..86b9fa0d3639 100644
--- a/arch/arm/mach-s5pv310/time.c
+++ b/arch/arm/mach-exynos4/time.c
@@ -1,9 +1,9 @@
1/* linux/arch/arm/mach-s5pv310/time.c 1/* linux/arch/arm/mach-exynos4/time.c
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com 4 * http://www.samsung.com
5 * 5 *
6 * S5PV310 (and compatible) HRT support 6 * EXYNOS4 (and compatible) HRT support
7 * PWM 2/4 is used for this feature 7 * PWM 2/4 is used for this feature
8 * 8 *
9 * This program is free software; you can redistribute it and/or modify 9 * This program is free software; you can redistribute it and/or modify
@@ -33,7 +33,7 @@ static struct clk *tdiv2;
33static struct clk *tdiv4; 33static struct clk *tdiv4;
34static struct clk *timerclk; 34static struct clk *timerclk;
35 35
36static void s5pv310_pwm_stop(unsigned int pwm_id) 36static void exynos4_pwm_stop(unsigned int pwm_id)
37{ 37{
38 unsigned long tcon; 38 unsigned long tcon;
39 39
@@ -52,7 +52,7 @@ static void s5pv310_pwm_stop(unsigned int pwm_id)
52 __raw_writel(tcon, S3C2410_TCON); 52 __raw_writel(tcon, S3C2410_TCON);
53} 53}
54 54
55static void s5pv310_pwm_init(unsigned int pwm_id, unsigned long tcnt) 55static void exynos4_pwm_init(unsigned int pwm_id, unsigned long tcnt)
56{ 56{
57 unsigned long tcon; 57 unsigned long tcon;
58 58
@@ -86,7 +86,7 @@ static void s5pv310_pwm_init(unsigned int pwm_id, unsigned long tcnt)
86 } 86 }
87} 87}
88 88
89static inline void s5pv310_pwm_start(unsigned int pwm_id, bool periodic) 89static inline void exynos4_pwm_start(unsigned int pwm_id, bool periodic)
90{ 90{
91 unsigned long tcon; 91 unsigned long tcon;
92 92
@@ -117,23 +117,23 @@ static inline void s5pv310_pwm_start(unsigned int pwm_id, bool periodic)
117 __raw_writel(tcon, S3C2410_TCON); 117 __raw_writel(tcon, S3C2410_TCON);
118} 118}
119 119
120static int s5pv310_pwm_set_next_event(unsigned long cycles, 120static int exynos4_pwm_set_next_event(unsigned long cycles,
121 struct clock_event_device *evt) 121 struct clock_event_device *evt)
122{ 122{
123 s5pv310_pwm_init(2, cycles); 123 exynos4_pwm_init(2, cycles);
124 s5pv310_pwm_start(2, 0); 124 exynos4_pwm_start(2, 0);
125 return 0; 125 return 0;
126} 126}
127 127
128static void s5pv310_pwm_set_mode(enum clock_event_mode mode, 128static void exynos4_pwm_set_mode(enum clock_event_mode mode,
129 struct clock_event_device *evt) 129 struct clock_event_device *evt)
130{ 130{
131 s5pv310_pwm_stop(2); 131 exynos4_pwm_stop(2);
132 132
133 switch (mode) { 133 switch (mode) {
134 case CLOCK_EVT_MODE_PERIODIC: 134 case CLOCK_EVT_MODE_PERIODIC:
135 s5pv310_pwm_init(2, clock_count_per_tick); 135 exynos4_pwm_init(2, clock_count_per_tick);
136 s5pv310_pwm_start(2, 1); 136 exynos4_pwm_start(2, 1);
137 break; 137 break;
138 case CLOCK_EVT_MODE_ONESHOT: 138 case CLOCK_EVT_MODE_ONESHOT:
139 break; 139 break;
@@ -149,11 +149,11 @@ static struct clock_event_device pwm_event_device = {
149 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, 149 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
150 .rating = 200, 150 .rating = 200,
151 .shift = 32, 151 .shift = 32,
152 .set_next_event = s5pv310_pwm_set_next_event, 152 .set_next_event = exynos4_pwm_set_next_event,
153 .set_mode = s5pv310_pwm_set_mode, 153 .set_mode = exynos4_pwm_set_mode,
154}; 154};
155 155
156irqreturn_t s5pv310_clock_event_isr(int irq, void *dev_id) 156irqreturn_t exynos4_clock_event_isr(int irq, void *dev_id)
157{ 157{
158 struct clock_event_device *evt = &pwm_event_device; 158 struct clock_event_device *evt = &pwm_event_device;
159 159
@@ -162,13 +162,13 @@ irqreturn_t s5pv310_clock_event_isr(int irq, void *dev_id)
162 return IRQ_HANDLED; 162 return IRQ_HANDLED;
163} 163}
164 164
165static struct irqaction s5pv310_clock_event_irq = { 165static struct irqaction exynos4_clock_event_irq = {
166 .name = "pwm_timer2_irq", 166 .name = "pwm_timer2_irq",
167 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, 167 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
168 .handler = s5pv310_clock_event_isr, 168 .handler = exynos4_clock_event_isr,
169}; 169};
170 170
171static void __init s5pv310_clockevent_init(void) 171static void __init exynos4_clockevent_init(void)
172{ 172{
173 unsigned long pclk; 173 unsigned long pclk;
174 unsigned long clock_rate; 174 unsigned long clock_rate;
@@ -198,23 +198,39 @@ static void __init s5pv310_clockevent_init(void)
198 pwm_event_device.cpumask = cpumask_of(0); 198 pwm_event_device.cpumask = cpumask_of(0);
199 clockevents_register_device(&pwm_event_device); 199 clockevents_register_device(&pwm_event_device);
200 200
201 setup_irq(IRQ_TIMER2, &s5pv310_clock_event_irq); 201 setup_irq(IRQ_TIMER2, &exynos4_clock_event_irq);
202} 202}
203 203
204static cycle_t s5pv310_pwm4_read(struct clocksource *cs) 204static cycle_t exynos4_pwm4_read(struct clocksource *cs)
205{ 205{
206 return (cycle_t) ~__raw_readl(S3C_TIMERREG(0x40)); 206 return (cycle_t) ~__raw_readl(S3C_TIMERREG(0x40));
207} 207}
208 208
209static void exynos4_pwm4_resume(struct clocksource *cs)
210{
211 unsigned long pclk;
212
213 pclk = clk_get_rate(timerclk);
214
215 clk_set_rate(tdiv4, pclk / 2);
216 clk_set_parent(tin4, tdiv4);
217
218 exynos4_pwm_init(4, ~0);
219 exynos4_pwm_start(4, 1);
220}
221
209struct clocksource pwm_clocksource = { 222struct clocksource pwm_clocksource = {
210 .name = "pwm_timer4", 223 .name = "pwm_timer4",
211 .rating = 250, 224 .rating = 250,
212 .read = s5pv310_pwm4_read, 225 .read = exynos4_pwm4_read,
213 .mask = CLOCKSOURCE_MASK(32), 226 .mask = CLOCKSOURCE_MASK(32),
214 .flags = CLOCK_SOURCE_IS_CONTINUOUS , 227 .flags = CLOCK_SOURCE_IS_CONTINUOUS ,
228#ifdef CONFIG_PM
229 .resume = exynos4_pwm4_resume,
230#endif
215}; 231};
216 232
217static void __init s5pv310_clocksource_init(void) 233static void __init exynos4_clocksource_init(void)
218{ 234{
219 unsigned long pclk; 235 unsigned long pclk;
220 unsigned long clock_rate; 236 unsigned long clock_rate;
@@ -226,14 +242,14 @@ static void __init s5pv310_clocksource_init(void)
226 242
227 clock_rate = clk_get_rate(tin4); 243 clock_rate = clk_get_rate(tin4);
228 244
229 s5pv310_pwm_init(4, ~0); 245 exynos4_pwm_init(4, ~0);
230 s5pv310_pwm_start(4, 1); 246 exynos4_pwm_start(4, 1);
231 247
232 if (clocksource_register_hz(&pwm_clocksource, clock_rate)) 248 if (clocksource_register_hz(&pwm_clocksource, clock_rate))
233 panic("%s: can't register clocksource\n", pwm_clocksource.name); 249 panic("%s: can't register clocksource\n", pwm_clocksource.name);
234} 250}
235 251
236static void __init s5pv310_timer_resources(void) 252static void __init exynos4_timer_resources(void)
237{ 253{
238 struct platform_device tmpdev; 254 struct platform_device tmpdev;
239 255
@@ -267,17 +283,17 @@ static void __init s5pv310_timer_resources(void)
267 clk_enable(tin4); 283 clk_enable(tin4);
268} 284}
269 285
270static void __init s5pv310_timer_init(void) 286static void __init exynos4_timer_init(void)
271{ 287{
272#ifdef CONFIG_LOCAL_TIMERS 288#ifdef CONFIG_LOCAL_TIMERS
273 twd_base = S5P_VA_TWD; 289 twd_base = S5P_VA_TWD;
274#endif 290#endif
275 291
276 s5pv310_timer_resources(); 292 exynos4_timer_resources();
277 s5pv310_clockevent_init(); 293 exynos4_clockevent_init();
278 s5pv310_clocksource_init(); 294 exynos4_clocksource_init();
279} 295}
280 296
281struct sys_timer s5pv310_timer = { 297struct sys_timer exynos4_timer = {
282 .init = s5pv310_timer_init, 298 .init = exynos4_timer_init,
283}; 299};
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 56684b517070..5eec099e0c72 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -100,6 +100,7 @@ config MACH_MX25_3DS
100 select IMX_HAVE_PLATFORM_FSL_USB2_UDC 100 select IMX_HAVE_PLATFORM_FSL_USB2_UDC
101 select IMX_HAVE_PLATFORM_IMX2_WDT 101 select IMX_HAVE_PLATFORM_IMX2_WDT
102 select IMX_HAVE_PLATFORM_IMXDI_RTC 102 select IMX_HAVE_PLATFORM_IMXDI_RTC
103 select IMX_HAVE_PLATFORM_IMX_I2C
103 select IMX_HAVE_PLATFORM_IMX_FB 104 select IMX_HAVE_PLATFORM_IMX_FB
104 select IMX_HAVE_PLATFORM_IMX_KEYPAD 105 select IMX_HAVE_PLATFORM_IMX_KEYPAD
105 select IMX_HAVE_PLATFORM_IMX_UART 106 select IMX_HAVE_PLATFORM_IMX_UART
@@ -238,6 +239,7 @@ config MACH_MX27_3DS
238 select SOC_IMX27 239 select SOC_IMX27
239 select IMX_HAVE_PLATFORM_FSL_USB2_UDC 240 select IMX_HAVE_PLATFORM_FSL_USB2_UDC
240 select IMX_HAVE_PLATFORM_IMX2_WDT 241 select IMX_HAVE_PLATFORM_IMX2_WDT
242 select IMX_HAVE_PLATFORM_IMX_I2C
241 select IMX_HAVE_PLATFORM_IMX_KEYPAD 243 select IMX_HAVE_PLATFORM_IMX_KEYPAD
242 select IMX_HAVE_PLATFORM_IMX_UART 244 select IMX_HAVE_PLATFORM_IMX_UART
243 select IMX_HAVE_PLATFORM_MXC_EHCI 245 select IMX_HAVE_PLATFORM_MXC_EHCI
@@ -265,6 +267,7 @@ config MACH_IMX27LITE
265 bool "LogicPD MX27 LITEKIT platform" 267 bool "LogicPD MX27 LITEKIT platform"
266 select SOC_IMX27 268 select SOC_IMX27
267 select IMX_HAVE_PLATFORM_IMX_UART 269 select IMX_HAVE_PLATFORM_IMX_UART
270 select IMX_HAVE_PLATFORM_IMX_SSI
268 help 271 help
269 Include support for MX27 LITEKIT platform. This includes specific 272 Include support for MX27 LITEKIT platform. This includes specific
270 configurations for the board and its peripherals. 273 configurations for the board and its peripherals.
@@ -300,4 +303,13 @@ config MACH_MXT_TD60
300 Include support for i-MXT (aka td60) platform. This 303 Include support for i-MXT (aka td60) platform. This
301 includes specific configurations for the module and its peripherals. 304 includes specific configurations for the module and its peripherals.
302 305
306config MACH_IMX27IPCAM
307 bool "IMX27 IPCAM platform"
308 select SOC_IMX27
309 select IMX_HAVE_PLATFORM_IMX2_WDT
310 select IMX_HAVE_PLATFORM_IMX_UART
311 help
312 Include support for IMX27 IPCAM platform. This includes specific
313 configurations for the board and its peripherals.
314
303endif 315endif
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 77100bf26153..b85794d27991 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -9,10 +9,10 @@ obj-$(CONFIG_IMX_HAVE_DMA_V1) += dma-v1.o
9obj-$(CONFIG_ARCH_MX1) += clock-imx1.o mm-imx1.o 9obj-$(CONFIG_ARCH_MX1) += clock-imx1.o mm-imx1.o
10obj-$(CONFIG_MACH_MX21) += clock-imx21.o mm-imx21.o 10obj-$(CONFIG_MACH_MX21) += clock-imx21.o mm-imx21.o
11 11
12obj-$(CONFIG_ARCH_MX25) += clock-imx25.o mm-imx25.o 12obj-$(CONFIG_ARCH_MX25) += clock-imx25.o mm-imx25.o ehci-imx25.o
13 13
14obj-$(CONFIG_MACH_MX27) += cpu-imx27.o pm-imx27.o 14obj-$(CONFIG_MACH_MX27) += cpu-imx27.o pm-imx27.o
15obj-$(CONFIG_MACH_MX27) += clock-imx27.o mm-imx27.o 15obj-$(CONFIG_MACH_MX27) += clock-imx27.o mm-imx27.o ehci-imx27.o
16 16
17# Support for CMOS sensor interface 17# Support for CMOS sensor interface
18obj-$(CONFIG_MX1_VIDEO) += mx1-camera-fiq.o mx1-camera-fiq-ksym.o 18obj-$(CONFIG_MX1_VIDEO) += mx1-camera-fiq.o mx1-camera-fiq-ksym.o
@@ -36,3 +36,4 @@ obj-$(CONFIG_MACH_CPUIMX27) += mach-cpuimx27.o
36obj-$(CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD) += eukrea_mbimx27-baseboard.o 36obj-$(CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD) += eukrea_mbimx27-baseboard.o
37obj-$(CONFIG_MACH_PCA100) += mach-pca100.o 37obj-$(CONFIG_MACH_PCA100) += mach-pca100.o
38obj-$(CONFIG_MACH_MXT_TD60) += mach-mxt_td60.o 38obj-$(CONFIG_MACH_MXT_TD60) += mach-mxt_td60.o
39obj-$(CONFIG_MACH_IMX27IPCAM) += mach-imx27ipcam.o
diff --git a/arch/arm/mach-imx/clock-imx1.c b/arch/arm/mach-imx/clock-imx1.c
index 3938a563b280..dcc41728fe72 100644
--- a/arch/arm/mach-imx/clock-imx1.c
+++ b/arch/arm/mach-imx/clock-imx1.c
@@ -592,6 +592,7 @@ static struct clk_lookup lookups[] __initdata = {
592 _REGISTER_CLOCK("imx-uart.2", NULL, uart_clk) 592 _REGISTER_CLOCK("imx-uart.2", NULL, uart_clk)
593 _REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk) 593 _REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk)
594 _REGISTER_CLOCK("imx1-cspi.0", NULL, spi_clk) 594 _REGISTER_CLOCK("imx1-cspi.0", NULL, spi_clk)
595 _REGISTER_CLOCK("imx1-cspi.1", NULL, spi_clk)
595 _REGISTER_CLOCK("imx-mmc.0", NULL, sdhc_clk) 596 _REGISTER_CLOCK("imx-mmc.0", NULL, sdhc_clk)
596 _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk) 597 _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
597 _REGISTER_CLOCK(NULL, "mshc", mshc_clk) 598 _REGISTER_CLOCK(NULL, "mshc", mshc_clk)
diff --git a/arch/arm/mach-imx/clock-imx25.c b/arch/arm/mach-imx/clock-imx25.c
index daa0165b6772..a65838fc061c 100644
--- a/arch/arm/mach-imx/clock-imx25.c
+++ b/arch/arm/mach-imx/clock-imx25.c
@@ -228,6 +228,7 @@ DEFINE_CLOCK(esdhc1_per_clk, 0, CCM_CGCR0, 3, get_rate_esdhc1, NULL,
228DEFINE_CLOCK(esdhc2_ahb_clk, 0, CCM_CGCR0, 22, get_rate_esdhc2, NULL, NULL); 228DEFINE_CLOCK(esdhc2_ahb_clk, 0, CCM_CGCR0, 22, get_rate_esdhc2, NULL, NULL);
229DEFINE_CLOCK(esdhc2_per_clk, 0, CCM_CGCR0, 4, get_rate_esdhc2, NULL, 229DEFINE_CLOCK(esdhc2_per_clk, 0, CCM_CGCR0, 4, get_rate_esdhc2, NULL,
230 &esdhc2_ahb_clk); 230 &esdhc2_ahb_clk);
231DEFINE_CLOCK(sdma_ahb_clk, 0, CCM_CGCR0, 26, NULL, NULL, NULL);
231DEFINE_CLOCK(fec_ahb_clk, 0, CCM_CGCR0, 23, NULL, NULL, NULL); 232DEFINE_CLOCK(fec_ahb_clk, 0, CCM_CGCR0, 23, NULL, NULL, NULL);
232DEFINE_CLOCK(lcdc_ahb_clk, 0, CCM_CGCR0, 24, NULL, NULL, NULL); 233DEFINE_CLOCK(lcdc_ahb_clk, 0, CCM_CGCR0, 24, NULL, NULL, NULL);
233DEFINE_CLOCK(lcdc_per_clk, 0, CCM_CGCR0, 7, NULL, NULL, &lcdc_ahb_clk); 234DEFINE_CLOCK(lcdc_per_clk, 0, CCM_CGCR0, 7, NULL, NULL, &lcdc_ahb_clk);
@@ -253,6 +254,7 @@ DEFINE_CLOCK(lcdc_clk, 0, CCM_CGCR1, 29, get_rate_lcdc, NULL, &lcdc_per_clk);
253DEFINE_CLOCK(wdt_clk, 0, CCM_CGCR2, 19, get_rate_ipg, NULL, NULL); 254DEFINE_CLOCK(wdt_clk, 0, CCM_CGCR2, 19, get_rate_ipg, NULL, NULL);
254DEFINE_CLOCK(ssi1_clk, 0, CCM_CGCR2, 11, get_rate_ssi1, NULL, &ssi1_per_clk); 255DEFINE_CLOCK(ssi1_clk, 0, CCM_CGCR2, 11, get_rate_ssi1, NULL, &ssi1_per_clk);
255DEFINE_CLOCK(ssi2_clk, 1, CCM_CGCR2, 12, get_rate_ssi2, NULL, &ssi2_per_clk); 256DEFINE_CLOCK(ssi2_clk, 1, CCM_CGCR2, 12, get_rate_ssi2, NULL, &ssi2_per_clk);
257DEFINE_CLOCK(sdma_clk, 0, CCM_CGCR2, 6, get_rate_ipg, NULL, &sdma_ahb_clk);
256DEFINE_CLOCK(esdhc1_clk, 0, CCM_CGCR1, 13, get_rate_esdhc1, NULL, 258DEFINE_CLOCK(esdhc1_clk, 0, CCM_CGCR1, 13, get_rate_esdhc1, NULL,
257 &esdhc1_per_clk); 259 &esdhc1_per_clk);
258DEFINE_CLOCK(esdhc2_clk, 1, CCM_CGCR1, 14, get_rate_esdhc2, NULL, 260DEFINE_CLOCK(esdhc2_clk, 1, CCM_CGCR1, 14, get_rate_esdhc2, NULL,
@@ -304,6 +306,7 @@ static struct clk_lookup lookups[] = {
304 _REGISTER_CLOCK(NULL, "audmux", audmux_clk) 306 _REGISTER_CLOCK(NULL, "audmux", audmux_clk)
305 _REGISTER_CLOCK("flexcan.0", NULL, can1_clk) 307 _REGISTER_CLOCK("flexcan.0", NULL, can1_clk)
306 _REGISTER_CLOCK("flexcan.1", NULL, can2_clk) 308 _REGISTER_CLOCK("flexcan.1", NULL, can2_clk)
309 _REGISTER_CLOCK("imx-sdma", NULL, sdma_clk)
307}; 310};
308 311
309int __init mx25_clocks_init(void) 312int __init mx25_clocks_init(void)
diff --git a/arch/arm/mach-imx/devices-imx1.h b/arch/arm/mach-imx/devices-imx1.h
index 81979486218e..da593657ff3f 100644
--- a/arch/arm/mach-imx/devices-imx1.h
+++ b/arch/arm/mach-imx/devices-imx1.h
@@ -9,6 +9,10 @@
9#include <mach/mx1.h> 9#include <mach/mx1.h>
10#include <mach/devices-common.h> 10#include <mach/devices-common.h>
11 11
12extern const struct imx_imx_fb_data imx1_imx_fb_data __initconst;
13#define imx1_add_imx_fb(pdata) \
14 imx_add_imx_fb(&imx1_imx_fb_data, pdata)
15
12extern const struct imx_imx_i2c_data imx1_imx_i2c_data __initconst; 16extern const struct imx_imx_i2c_data imx1_imx_i2c_data __initconst;
13#define imx1_add_imx_i2c(pdata) \ 17#define imx1_add_imx_i2c(pdata) \
14 imx_add_imx_i2c(&imx1_imx_i2c_data, pdata) 18 imx_add_imx_i2c(&imx1_imx_i2c_data, pdata)
@@ -18,3 +22,10 @@ extern const struct imx_imx_uart_3irq_data imx1_imx_uart_data[] __initconst;
18 imx_add_imx_uart_3irq(&imx1_imx_uart_data[id], pdata) 22 imx_add_imx_uart_3irq(&imx1_imx_uart_data[id], pdata)
19#define imx1_add_imx_uart0(pdata) imx1_add_imx_uart(0, pdata) 23#define imx1_add_imx_uart0(pdata) imx1_add_imx_uart(0, pdata)
20#define imx1_add_imx_uart1(pdata) imx1_add_imx_uart(1, pdata) 24#define imx1_add_imx_uart1(pdata) imx1_add_imx_uart(1, pdata)
25
26extern const struct imx_spi_imx_data imx1_cspi_data[] __initconst;
27#define imx1_add_cspi(id, pdata) \
28 imx_add_spi_imx(&imx1_cspi_data[id], pdata)
29
30#define imx1_add_spi_imx0(pdata) imx1_add_cspi(0, pdata)
31#define imx1_add_spi_imx1(pdata) imx1_add_cspi(1, pdata)
diff --git a/arch/arm/mach-imx/devices-imx25.h b/arch/arm/mach-imx/devices-imx25.h
index bde33caf1b90..b591d72f6037 100644
--- a/arch/arm/mach-imx/devices-imx25.h
+++ b/arch/arm/mach-imx/devices-imx25.h
@@ -81,7 +81,11 @@ imx25_sdhci_esdhc_imx_data[] __initconst;
81 81
82extern const struct imx_spi_imx_data imx25_cspi_data[] __initconst; 82extern const struct imx_spi_imx_data imx25_cspi_data[] __initconst;
83#define imx25_add_spi_imx(id, pdata) \ 83#define imx25_add_spi_imx(id, pdata) \
84 imx_add_spi_imx(&imx25_spi_imx_data[id], pdata) 84 imx_add_spi_imx(&imx25_cspi_data[id], pdata)
85#define imx25_add_spi_imx0(pdata) imx25_add_spi_imx(0, pdata) 85#define imx25_add_spi_imx0(pdata) imx25_add_spi_imx(0, pdata)
86#define imx25_add_spi_imx1(pdata) imx25_add_spi_imx(1, pdata) 86#define imx25_add_spi_imx1(pdata) imx25_add_spi_imx(1, pdata)
87#define imx25_add_spi_imx2(pdata) imx25_add_spi_imx(2, pdata) 87#define imx25_add_spi_imx2(pdata) imx25_add_spi_imx(2, pdata)
88
89extern struct imx_mxc_pwm_data imx25_mxc_pwm_data[] __initconst;
90#define imx25_add_mxc_pwm(id) \
91 imx_add_mxc_pwm(&imx25_mxc_pwm_data[id])
diff --git a/arch/arm/mach-imx/dma-v1.c b/arch/arm/mach-imx/dma-v1.c
index e9f1769b49f5..236f1495efad 100644
--- a/arch/arm/mach-imx/dma-v1.c
+++ b/arch/arm/mach-imx/dma-v1.c
@@ -699,7 +699,7 @@ int imx_dma_request(int channel, const char *name)
699 local_irq_restore(flags); 699 local_irq_restore(flags);
700 return -EBUSY; 700 return -EBUSY;
701 } 701 }
702 memset(imxdma, 0, sizeof(imxdma)); 702 memset(imxdma, 0, sizeof(*imxdma));
703 imxdma->name = name; 703 imxdma->name = name;
704 local_irq_restore(flags); /* request_irq() can block */ 704 local_irq_restore(flags); /* request_irq() can block */
705 705
diff --git a/arch/arm/mach-imx/ehci-imx25.c b/arch/arm/mach-imx/ehci-imx25.c
new file mode 100644
index 000000000000..865daf0b09e9
--- /dev/null
+++ b/arch/arm/mach-imx/ehci-imx25.c
@@ -0,0 +1,80 @@
1/*
2 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
3 * Copyright (C) 2010 Freescale Semiconductor, Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details.
14 */
15
16#include <linux/platform_device.h>
17#include <linux/io.h>
18
19#include <mach/hardware.h>
20#include <mach/mxc_ehci.h>
21
22#define USBCTRL_OTGBASE_OFFSET 0x600
23
24#define MX25_OTG_SIC_SHIFT 29
25#define MX25_OTG_SIC_MASK (0x3 << MX25_OTG_SIC_SHIFT)
26#define MX25_OTG_PM_BIT (1 << 24)
27
28#define MX25_H1_SIC_SHIFT 21
29#define MX25_H1_SIC_MASK (0x3 << MX25_H1_SIC_SHIFT)
30#define MX25_H1_PM_BIT (1 << 8)
31#define MX25_H1_IPPUE_UP_BIT (1 << 7)
32#define MX25_H1_IPPUE_DOWN_BIT (1 << 6)
33#define MX25_H1_TLL_BIT (1 << 5)
34#define MX25_H1_USBTE_BIT (1 << 4)
35
36int mx25_initialize_usb_hw(int port, unsigned int flags)
37{
38 unsigned int v;
39
40 v = readl(MX25_IO_ADDRESS(MX25_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
41
42 switch (port) {
43 case 0: /* OTG port */
44 v &= ~(MX25_OTG_SIC_MASK | MX25_OTG_PM_BIT);
45 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_OTG_SIC_SHIFT;
46
47 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
48 v |= MX25_OTG_PM_BIT;
49
50 break;
51 case 1: /* H1 port */
52 v &= ~(MX25_H1_SIC_MASK | MX25_H1_PM_BIT | MX25_H1_TLL_BIT |
53 MX25_H1_USBTE_BIT | MX25_H1_IPPUE_DOWN_BIT | MX25_H1_IPPUE_UP_BIT);
54 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_H1_SIC_SHIFT;
55
56 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
57 v |= MX25_H1_PM_BIT;
58
59 if (!(flags & MXC_EHCI_TTL_ENABLED))
60 v |= MX25_H1_TLL_BIT;
61
62 if (flags & MXC_EHCI_INTERNAL_PHY)
63 v |= MX25_H1_USBTE_BIT;
64
65 if (flags & MXC_EHCI_IPPUE_DOWN)
66 v |= MX25_H1_IPPUE_DOWN_BIT;
67
68 if (flags & MXC_EHCI_IPPUE_UP)
69 v |= MX25_H1_IPPUE_UP_BIT;
70
71 break;
72 default:
73 return -EINVAL;
74 }
75
76 writel(v, MX25_IO_ADDRESS(MX25_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
77
78 return 0;
79}
80
diff --git a/arch/arm/mach-imx/ehci-imx27.c b/arch/arm/mach-imx/ehci-imx27.c
new file mode 100644
index 000000000000..fa69419eabdd
--- /dev/null
+++ b/arch/arm/mach-imx/ehci-imx27.c
@@ -0,0 +1,82 @@
1/*
2 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
3 * Copyright (C) 2010 Freescale Semiconductor, Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details.
14 */
15
16#include <linux/platform_device.h>
17#include <linux/io.h>
18
19#include <mach/hardware.h>
20#include <mach/mxc_ehci.h>
21
22#define USBCTRL_OTGBASE_OFFSET 0x600
23
24#define MX27_OTG_SIC_SHIFT 29
25#define MX27_OTG_SIC_MASK (0x3 << MX27_OTG_SIC_SHIFT)
26#define MX27_OTG_PM_BIT (1 << 24)
27
28#define MX27_H2_SIC_SHIFT 21
29#define MX27_H2_SIC_MASK (0x3 << MX27_H2_SIC_SHIFT)
30#define MX27_H2_PM_BIT (1 << 16)
31#define MX27_H2_DT_BIT (1 << 5)
32
33#define MX27_H1_SIC_SHIFT 13
34#define MX27_H1_SIC_MASK (0x3 << MX27_H1_SIC_SHIFT)
35#define MX27_H1_PM_BIT (1 << 8)
36#define MX27_H1_DT_BIT (1 << 4)
37
38int mx27_initialize_usb_hw(int port, unsigned int flags)
39{
40 unsigned int v;
41
42 v = readl(MX27_IO_ADDRESS(MX27_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
43
44 switch (port) {
45 case 0: /* OTG port */
46 v &= ~(MX27_OTG_SIC_MASK | MX27_OTG_PM_BIT);
47 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX27_OTG_SIC_SHIFT;
48
49 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
50 v |= MX27_OTG_PM_BIT;
51 break;
52 case 1: /* H1 port */
53 v &= ~(MX27_H1_SIC_MASK | MX27_H1_PM_BIT | MX27_H1_DT_BIT);
54 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX27_H1_SIC_SHIFT;
55
56 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
57 v |= MX27_H1_PM_BIT;
58
59 if (!(flags & MXC_EHCI_TTL_ENABLED))
60 v |= MX27_H1_DT_BIT;
61
62 break;
63 case 2: /* H2 port */
64 v &= ~(MX27_H2_SIC_MASK | MX27_H2_PM_BIT | MX27_H2_DT_BIT);
65 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX27_H2_SIC_SHIFT;
66
67 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
68 v |= MX27_H2_PM_BIT;
69
70 if (!(flags & MXC_EHCI_TTL_ENABLED))
71 v |= MX27_H2_DT_BIT;
72
73 break;
74 default:
75 return -EINVAL;
76 }
77
78 writel(v, MX27_IO_ADDRESS(MX27_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
79
80 return 0;
81}
82
diff --git a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
index 275c8589d797..fa5288018ba7 100644
--- a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
@@ -249,7 +249,7 @@ static const struct imxuart_platform_data uart_pdata __initconst = {
249 249
250#define ADS7846_PENDOWN (GPIO_PORTD | 25) 250#define ADS7846_PENDOWN (GPIO_PORTD | 25)
251 251
252static void ads7846_dev_init(void) 252static void __maybe_unused ads7846_dev_init(void)
253{ 253{
254 if (gpio_request(ADS7846_PENDOWN, "ADS7846 pendown") < 0) { 254 if (gpio_request(ADS7846_PENDOWN, "ADS7846 pendown") < 0) {
255 printk(KERN_ERR "can't get ads746 pen down GPIO\n"); 255 printk(KERN_ERR "can't get ads746 pen down GPIO\n");
@@ -268,7 +268,8 @@ static struct ads7846_platform_data ads7846_config __initdata = {
268 .keep_vref_on = 1, 268 .keep_vref_on = 1,
269}; 269};
270 270
271static struct spi_board_info eukrea_mbimx27_spi_board_info[] __initdata = { 271static struct spi_board_info __maybe_unused
272 eukrea_mbimx27_spi_board_info[] __initdata = {
272 [0] = { 273 [0] = {
273 .modalias = "ads7846", 274 .modalias = "ads7846",
274 .bus_num = 0, 275 .bus_num = 0,
@@ -357,13 +358,11 @@ void __init eukrea_mbimx27_baseboard_init(void)
357 ads7846_dev_init(); 358 ads7846_dev_init();
358#endif 359#endif
359 360
360#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
361 /* SPI_CS0 init */ 361 /* SPI_CS0 init */
362 mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT); 362 mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT);
363 imx27_add_spi_imx0(&eukrea_mbimx27_spi0_data); 363 imx27_add_spi_imx0(&eukrea_mbimx27_spi0_data);
364 spi_register_board_info(eukrea_mbimx27_spi_board_info, 364 spi_register_board_info(eukrea_mbimx27_spi_board_info,
365 ARRAY_SIZE(eukrea_mbimx27_spi_board_info)); 365 ARRAY_SIZE(eukrea_mbimx27_spi_board_info));
366#endif
367 366
368 /* Leds configuration */ 367 /* Leds configuration */
369 mxc_gpio_mode(GPIO_PORTF | 16 | GPIO_GPIO | GPIO_OUT); 368 mxc_gpio_mode(GPIO_PORTF | 16 | GPIO_GPIO | GPIO_OUT);
diff --git a/arch/arm/mach-imx/mach-cpuimx27.c b/arch/arm/mach-imx/mach-cpuimx27.c
index 6cf04da2456a..759299bb035b 100644
--- a/arch/arm/mach-imx/mach-cpuimx27.c
+++ b/arch/arm/mach-imx/mach-cpuimx27.c
@@ -209,17 +209,25 @@ static struct platform_device serial_device = {
209}; 209};
210#endif 210#endif
211 211
212#if defined(CONFIG_USB_ULPI) 212static int eukrea_cpuimx27_otg_init(struct platform_device *pdev)
213{
214 return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
215}
216
213static struct mxc_usbh_platform_data otg_pdata __initdata = { 217static struct mxc_usbh_platform_data otg_pdata __initdata = {
218 .init = eukrea_cpuimx27_otg_init,
214 .portsc = MXC_EHCI_MODE_ULPI, 219 .portsc = MXC_EHCI_MODE_ULPI,
215 .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
216}; 220};
217 221
222static int eukrea_cpuimx27_usbh2_init(struct platform_device *pdev)
223{
224 return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
225}
226
218static struct mxc_usbh_platform_data usbh2_pdata __initdata = { 227static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
228 .init = eukrea_cpuimx27_usbh2_init,
219 .portsc = MXC_EHCI_MODE_ULPI, 229 .portsc = MXC_EHCI_MODE_ULPI,
220 .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
221}; 230};
222#endif
223 231
224static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { 232static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
225 .operating_mode = FSL_USB2_DR_DEVICE, 233 .operating_mode = FSL_USB2_DR_DEVICE,
@@ -273,21 +281,19 @@ static void __init eukrea_cpuimx27_init(void)
273 platform_device_register(&serial_device); 281 platform_device_register(&serial_device);
274#endif 282#endif
275 283
276#if defined(CONFIG_USB_ULPI)
277 if (otg_mode_host) { 284 if (otg_mode_host) {
278 otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, 285 otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
279 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); 286 ULPI_OTG_DRVVBUS_EXT);
280 287 if (otg_pdata.otg)
281 imx27_add_mxc_ehci_otg(&otg_pdata); 288 imx27_add_mxc_ehci_otg(&otg_pdata);
289 } else {
290 imx27_add_fsl_usb2_udc(&otg_device_pdata);
282 } 291 }
283 292
284 usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, 293 usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
285 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); 294 ULPI_OTG_DRVVBUS_EXT);
286 295 if (usbh2_pdata.otg)
287 imx27_add_mxc_ehci_hs(2, &usbh2_pdata); 296 imx27_add_mxc_ehci_hs(2, &usbh2_pdata);
288#endif
289 if (!otg_mode_host)
290 imx27_add_fsl_usb2_udc(&otg_device_pdata);
291 297
292#ifdef CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD 298#ifdef CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD
293 eukrea_mbimx27_baseboard_init(); 299 eukrea_mbimx27_baseboard_init();
@@ -304,9 +310,10 @@ static struct sys_timer eukrea_cpuimx27_timer = {
304}; 310};
305 311
306MACHINE_START(CPUIMX27, "EUKREA CPUIMX27") 312MACHINE_START(CPUIMX27, "EUKREA CPUIMX27")
307 .boot_params = MX27_PHYS_OFFSET + 0x100, 313 .boot_params = MX27_PHYS_OFFSET + 0x100,
308 .map_io = mx27_map_io, 314 .map_io = mx27_map_io,
309 .init_irq = mx27_init_irq, 315 .init_early = imx27_init_early,
310 .init_machine = eukrea_cpuimx27_init, 316 .init_irq = mx27_init_irq,
311 .timer = &eukrea_cpuimx27_timer, 317 .timer = &eukrea_cpuimx27_timer,
318 .init_machine = eukrea_cpuimx27_init,
312MACHINE_END 319MACHINE_END
diff --git a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
index eb395aba9237..9da8d18eeb00 100644
--- a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
+++ b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
@@ -84,15 +84,25 @@ static struct i2c_board_info eukrea_cpuimx25_i2c_devices[] = {
84 }, 84 },
85}; 85};
86 86
87static int eukrea_cpuimx25_otg_init(struct platform_device *pdev)
88{
89 return mx25_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
90}
91
87static const struct mxc_usbh_platform_data otg_pdata __initconst = { 92static const struct mxc_usbh_platform_data otg_pdata __initconst = {
93 .init = eukrea_cpuimx25_otg_init,
88 .portsc = MXC_EHCI_MODE_UTMI, 94 .portsc = MXC_EHCI_MODE_UTMI,
89 .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
90}; 95};
91 96
97static int eukrea_cpuimx25_usbh2_init(struct platform_device *pdev)
98{
99 return mx25_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_SINGLE_UNI |
100 MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN);
101}
102
92static const struct mxc_usbh_platform_data usbh2_pdata __initconst = { 103static const struct mxc_usbh_platform_data usbh2_pdata __initconst = {
104 .init = eukrea_cpuimx25_usbh2_init,
93 .portsc = MXC_EHCI_MODE_SERIAL, 105 .portsc = MXC_EHCI_MODE_SERIAL,
94 .flags = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY |
95 MXC_EHCI_IPPUE_DOWN,
96}; 106};
97 107
98static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { 108static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
@@ -153,9 +163,10 @@ static struct sys_timer eukrea_cpuimx25_timer = {
153 163
154MACHINE_START(EUKREA_CPUIMX25, "Eukrea CPUIMX25") 164MACHINE_START(EUKREA_CPUIMX25, "Eukrea CPUIMX25")
155 /* Maintainer: Eukrea Electromatique */ 165 /* Maintainer: Eukrea Electromatique */
156 .boot_params = MX25_PHYS_OFFSET + 0x100, 166 .boot_params = MX25_PHYS_OFFSET + 0x100,
157 .map_io = mx25_map_io, 167 .map_io = mx25_map_io,
158 .init_irq = mx25_init_irq, 168 .init_early = imx25_init_early,
159 .init_machine = eukrea_cpuimx25_init, 169 .init_irq = mx25_init_irq,
160 .timer = &eukrea_cpuimx25_timer, 170 .timer = &eukrea_cpuimx25_timer,
171 .init_machine = eukrea_cpuimx25_init,
161MACHINE_END 172MACHINE_END
diff --git a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
index 40a3666ea632..d7e0d219726a 100644
--- a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
+++ b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
@@ -30,6 +30,7 @@
30#include <linux/gpio_keys.h> 30#include <linux/gpio_keys.h>
31#include <linux/input.h> 31#include <linux/input.h>
32#include <linux/gpio.h> 32#include <linux/gpio.h>
33#include <linux/delay.h>
33#include <asm/mach-types.h> 34#include <asm/mach-types.h>
34#include <asm/mach/arch.h> 35#include <asm/mach/arch.h>
35#include <asm/mach/time.h> 36#include <asm/mach/time.h>
@@ -66,6 +67,11 @@ static const int visstrim_m10_pins[] __initconst = {
66 PD15_AOUT_FEC_COL, 67 PD15_AOUT_FEC_COL,
67 PD16_AIN_FEC_TX_ER, 68 PD16_AIN_FEC_TX_ER,
68 PF23_AIN_FEC_TX_EN, 69 PF23_AIN_FEC_TX_EN,
70 /* SSI1 */
71 PC20_PF_SSI1_FS,
72 PC21_PF_SSI1_RXD,
73 PC22_PF_SSI1_TXD,
74 PC23_PF_SSI1_CLK,
69 /* SDHC1 */ 75 /* SDHC1 */
70 PE18_PF_SD1_D0, 76 PE18_PF_SD1_D0,
71 PE19_PF_SD1_D1, 77 PE19_PF_SD1_D1,
@@ -204,20 +210,30 @@ static struct i2c_board_info visstrim_m10_i2c_devices[] = {
204 I2C_BOARD_INFO("pca9555", 0x20), 210 I2C_BOARD_INFO("pca9555", 0x20),
205 .platform_data = &visstrim_m10_pca9555_pdata, 211 .platform_data = &visstrim_m10_pca9555_pdata,
206 }, 212 },
213 {
214 I2C_BOARD_INFO("tlv320aic32x4", 0x18),
215 }
207}; 216};
208 217
209/* USB OTG */ 218/* USB OTG */
210static int otg_phy_init(struct platform_device *pdev) 219static int otg_phy_init(struct platform_device *pdev)
211{ 220{
212 gpio_set_value(OTG_PHY_CS_GPIO, 0); 221 gpio_set_value(OTG_PHY_CS_GPIO, 0);
213 return 0; 222
223 mdelay(10);
224
225 return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
214} 226}
215 227
216static const struct mxc_usbh_platform_data 228static const struct mxc_usbh_platform_data
217visstrim_m10_usbotg_pdata __initconst = { 229visstrim_m10_usbotg_pdata __initconst = {
218 .init = otg_phy_init, 230 .init = otg_phy_init,
219 .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, 231 .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
220 .flags = MXC_EHCI_POWER_PINS_ENABLED, 232};
233
234/* SSI */
235static const struct imx_ssi_platform_data visstrim_m10_ssi_pdata __initconst = {
236 .flags = IMX_SSI_DMA | IMX_SSI_SYN,
221}; 237};
222 238
223static void __init visstrim_m10_board_init(void) 239static void __init visstrim_m10_board_init(void)
@@ -229,6 +245,7 @@ static void __init visstrim_m10_board_init(void)
229 if (ret) 245 if (ret)
230 pr_err("Failed to setup pins (%d)\n", ret); 246 pr_err("Failed to setup pins (%d)\n", ret);
231 247
248 imx27_add_imx_ssi(0, &visstrim_m10_ssi_pdata);
232 imx27_add_imx_uart0(&uart_pdata); 249 imx27_add_imx_uart0(&uart_pdata);
233 250
234 i2c_register_board_info(0, visstrim_m10_i2c_devices, 251 i2c_register_board_info(0, visstrim_m10_i2c_devices,
@@ -251,9 +268,10 @@ static struct sys_timer visstrim_m10_timer = {
251}; 268};
252 269
253MACHINE_START(IMX27_VISSTRIM_M10, "Vista Silicon Visstrim_M10") 270MACHINE_START(IMX27_VISSTRIM_M10, "Vista Silicon Visstrim_M10")
254 .boot_params = MX27_PHYS_OFFSET + 0x100, 271 .boot_params = MX27_PHYS_OFFSET + 0x100,
255 .map_io = mx27_map_io, 272 .map_io = mx27_map_io,
256 .init_irq = mx27_init_irq, 273 .init_early = imx27_init_early,
257 .init_machine = visstrim_m10_board_init, 274 .init_irq = mx27_init_irq,
258 .timer = &visstrim_m10_timer, 275 .timer = &visstrim_m10_timer,
276 .init_machine = visstrim_m10_board_init,
259MACHINE_END 277MACHINE_END
diff --git a/arch/arm/mach-imx/mach-imx27ipcam.c b/arch/arm/mach-imx/mach-imx27ipcam.c
new file mode 100644
index 000000000000..9be6cd6fbf8c
--- /dev/null
+++ b/arch/arm/mach-imx/mach-imx27ipcam.c
@@ -0,0 +1,78 @@
1/*
2 * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * Author: Fabio Estevam <fabio.estevam@freescale.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <asm/mach-types.h>
18#include <asm/mach/arch.h>
19#include <asm/mach/time.h>
20#include <mach/hardware.h>
21#include <mach/common.h>
22#include <mach/iomux-mx27.h>
23
24#include "devices-imx27.h"
25
26static const int mx27ipcam_pins[] __initconst = {
27 /* UART1 */
28 PE12_PF_UART1_TXD,
29 PE13_PF_UART1_RXD,
30 /* FEC */
31 PD0_AIN_FEC_TXD0,
32 PD1_AIN_FEC_TXD1,
33 PD2_AIN_FEC_TXD2,
34 PD3_AIN_FEC_TXD3,
35 PD4_AOUT_FEC_RX_ER,
36 PD5_AOUT_FEC_RXD1,
37 PD6_AOUT_FEC_RXD2,
38 PD7_AOUT_FEC_RXD3,
39 PD8_AF_FEC_MDIO,
40 PD9_AIN_FEC_MDC,
41 PD10_AOUT_FEC_CRS,
42 PD11_AOUT_FEC_TX_CLK,
43 PD12_AOUT_FEC_RXD0,
44 PD13_AOUT_FEC_RX_DV,
45 PD14_AOUT_FEC_RX_CLK,
46 PD15_AOUT_FEC_COL,
47 PD16_AIN_FEC_TX_ER,
48 PF23_AIN_FEC_TX_EN,
49};
50
51static void __init mx27ipcam_init(void)
52{
53 mxc_gpio_setup_multiple_pins(mx27ipcam_pins, ARRAY_SIZE(mx27ipcam_pins),
54 "mx27ipcam");
55
56 imx27_add_imx_uart0(NULL);
57 imx27_add_fec(NULL);
58 imx27_add_imx2_wdt(NULL);
59}
60
61static void __init mx27ipcam_timer_init(void)
62{
63 mx27_clocks_init(25000000);
64}
65
66static struct sys_timer mx27ipcam_timer = {
67 .init = mx27ipcam_timer_init,
68};
69
70MACHINE_START(IMX27IPCAM, "Freescale IMX27IPCAM")
71 /* maintainer: Freescale Semiconductor, Inc. */
72 .boot_params = MX27_PHYS_OFFSET + 0x100,
73 .map_io = mx27_map_io,
74 .init_early = imx27_init_early,
75 .init_irq = mx27_init_irq,
76 .timer = &mx27ipcam_timer,
77 .init_machine = mx27ipcam_init,
78MACHINE_END
diff --git a/arch/arm/mach-imx/mach-imx27lite.c b/arch/arm/mach-imx/mach-imx27lite.c
index 3a1202e47212..841140516ede 100644
--- a/arch/arm/mach-imx/mach-imx27lite.c
+++ b/arch/arm/mach-imx/mach-imx27lite.c
@@ -75,9 +75,10 @@ static struct sys_timer mx27lite_timer = {
75}; 75};
76 76
77MACHINE_START(IMX27LITE, "LogicPD i.MX27LITE") 77MACHINE_START(IMX27LITE, "LogicPD i.MX27LITE")
78 .boot_params = MX27_PHYS_OFFSET + 0x100, 78 .boot_params = MX27_PHYS_OFFSET + 0x100,
79 .map_io = mx27_map_io, 79 .map_io = mx27_map_io,
80 .init_irq = mx27_init_irq, 80 .init_early = imx27_init_early,
81 .init_machine = mx27lite_init, 81 .init_irq = mx27_init_irq,
82 .timer = &mx27lite_timer, 82 .timer = &mx27lite_timer,
83 .init_machine = mx27lite_init,
83MACHINE_END 84MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx1ads.c b/arch/arm/mach-imx/mach-mx1ads.c
index 1f446e5eb636..47cf56ac6d5b 100644
--- a/arch/arm/mach-imx/mach-mx1ads.c
+++ b/arch/arm/mach-imx/mach-mx1ads.c
@@ -144,17 +144,19 @@ struct sys_timer mx1ads_timer = {
144 144
145MACHINE_START(MX1ADS, "Freescale MX1ADS") 145MACHINE_START(MX1ADS, "Freescale MX1ADS")
146 /* Maintainer: Sascha Hauer, Pengutronix */ 146 /* Maintainer: Sascha Hauer, Pengutronix */
147 .boot_params = MX1_PHYS_OFFSET + 0x100, 147 .boot_params = MX1_PHYS_OFFSET + 0x100,
148 .map_io = mx1_map_io, 148 .map_io = mx1_map_io,
149 .init_irq = mx1_init_irq, 149 .init_early = imx1_init_early,
150 .timer = &mx1ads_timer, 150 .init_irq = mx1_init_irq,
151 .init_machine = mx1ads_init, 151 .timer = &mx1ads_timer,
152 .init_machine = mx1ads_init,
152MACHINE_END 153MACHINE_END
153 154
154MACHINE_START(MXLADS, "Freescale MXLADS") 155MACHINE_START(MXLADS, "Freescale MXLADS")
155 .boot_params = MX1_PHYS_OFFSET + 0x100, 156 .boot_params = MX1_PHYS_OFFSET + 0x100,
156 .map_io = mx1_map_io, 157 .map_io = mx1_map_io,
157 .init_irq = mx1_init_irq, 158 .init_early = imx1_init_early,
158 .timer = &mx1ads_timer, 159 .init_irq = mx1_init_irq,
159 .init_machine = mx1ads_init, 160 .timer = &mx1ads_timer,
161 .init_machine = mx1ads_init,
160MACHINE_END 162MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx21ads.c b/arch/arm/mach-imx/mach-mx21ads.c
index 0a372577c2ac..fa52a1086eae 100644
--- a/arch/arm/mach-imx/mach-mx21ads.c
+++ b/arch/arm/mach-imx/mach-mx21ads.c
@@ -304,9 +304,10 @@ static struct sys_timer mx21ads_timer = {
304 304
305MACHINE_START(MX21ADS, "Freescale i.MX21ADS") 305MACHINE_START(MX21ADS, "Freescale i.MX21ADS")
306 /* maintainer: Freescale Semiconductor, Inc. */ 306 /* maintainer: Freescale Semiconductor, Inc. */
307 .boot_params = MX21_PHYS_OFFSET + 0x100, 307 .boot_params = MX21_PHYS_OFFSET + 0x100,
308 .map_io = mx21ads_map_io, 308 .map_io = mx21ads_map_io,
309 .init_irq = mx21_init_irq, 309 .init_early = imx21_init_early,
310 .init_machine = mx21ads_board_init, 310 .init_irq = mx21_init_irq,
311 .timer = &mx21ads_timer, 311 .timer = &mx21ads_timer,
312 .init_machine = mx21ads_board_init,
312MACHINE_END 313MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx25_3ds.c b/arch/arm/mach-imx/mach-mx25_3ds.c
index 8382e7902078..06da438282aa 100644
--- a/arch/arm/mach-imx/mach-mx25_3ds.c
+++ b/arch/arm/mach-imx/mach-mx25_3ds.c
@@ -103,14 +103,18 @@ static iomux_v3_cfg_t mx25pdk_pads[] = {
103 MX25_PAD_SD1_DATA1__SD1_DATA1, 103 MX25_PAD_SD1_DATA1__SD1_DATA1,
104 MX25_PAD_SD1_DATA2__SD1_DATA2, 104 MX25_PAD_SD1_DATA2__SD1_DATA2,
105 MX25_PAD_SD1_DATA3__SD1_DATA3, 105 MX25_PAD_SD1_DATA3__SD1_DATA3,
106
107 /* I2C1 */
108 MX25_PAD_I2C1_CLK__I2C1_CLK,
109 MX25_PAD_I2C1_DAT__I2C1_DAT,
106}; 110};
107 111
108static const struct fec_platform_data mx25_fec_pdata __initconst = { 112static const struct fec_platform_data mx25_fec_pdata __initconst = {
109 .phy = PHY_INTERFACE_MODE_RMII, 113 .phy = PHY_INTERFACE_MODE_RMII,
110}; 114};
111 115
112#define FEC_ENABLE_GPIO 35 116#define FEC_ENABLE_GPIO IMX_GPIO_NR(2, 3)
113#define FEC_RESET_B_GPIO 104 117#define FEC_RESET_B_GPIO IMX_GPIO_NR(4, 8)
114 118
115static void __init mx25pdk_fec_reset(void) 119static void __init mx25pdk_fec_reset(void)
116{ 120{
@@ -185,9 +189,14 @@ static const struct matrix_keymap_data mx25pdk_keymap_data __initconst = {
185 .keymap_size = ARRAY_SIZE(mx25pdk_keymap), 189 .keymap_size = ARRAY_SIZE(mx25pdk_keymap),
186}; 190};
187 191
192static int mx25pdk_usbh2_init(struct platform_device *pdev)
193{
194 return mx25_initialize_usb_hw(pdev->id, MXC_EHCI_INTERNAL_PHY);
195}
196
188static const struct mxc_usbh_platform_data usbh2_pdata __initconst = { 197static const struct mxc_usbh_platform_data usbh2_pdata __initconst = {
198 .init = mx25pdk_usbh2_init,
189 .portsc = MXC_EHCI_MODE_SERIAL, 199 .portsc = MXC_EHCI_MODE_SERIAL,
190 .flags = MXC_EHCI_INTERNAL_PHY,
191}; 200};
192 201
193static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { 202static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
@@ -195,6 +204,10 @@ static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
195 .phy_mode = FSL_USB2_PHY_UTMI, 204 .phy_mode = FSL_USB2_PHY_UTMI,
196}; 205};
197 206
207static const struct imxi2c_platform_data mx25_3ds_i2c0_data __initconst = {
208 .bitrate = 100000,
209};
210
198static void __init mx25pdk_init(void) 211static void __init mx25pdk_init(void)
199{ 212{
200 mxc_iomux_v3_setup_multiple_pads(mx25pdk_pads, 213 mxc_iomux_v3_setup_multiple_pads(mx25pdk_pads,
@@ -213,6 +226,7 @@ static void __init mx25pdk_init(void)
213 imx25_add_imx_keypad(&mx25pdk_keymap_data); 226 imx25_add_imx_keypad(&mx25pdk_keymap_data);
214 227
215 imx25_add_sdhci_esdhc_imx(0, NULL); 228 imx25_add_sdhci_esdhc_imx(0, NULL);
229 imx25_add_imx_i2c0(&mx25_3ds_i2c0_data);
216} 230}
217 231
218static void __init mx25pdk_timer_init(void) 232static void __init mx25pdk_timer_init(void)
@@ -226,10 +240,10 @@ static struct sys_timer mx25pdk_timer = {
226 240
227MACHINE_START(MX25_3DS, "Freescale MX25PDK (3DS)") 241MACHINE_START(MX25_3DS, "Freescale MX25PDK (3DS)")
228 /* Maintainer: Freescale Semiconductor, Inc. */ 242 /* Maintainer: Freescale Semiconductor, Inc. */
229 .boot_params = MX25_PHYS_OFFSET + 0x100, 243 .boot_params = MX25_PHYS_OFFSET + 0x100,
230 .map_io = mx25_map_io, 244 .map_io = mx25_map_io,
231 .init_irq = mx25_init_irq, 245 .init_early = imx25_init_early,
232 .init_machine = mx25pdk_init, 246 .init_irq = mx25_init_irq,
233 .timer = &mx25pdk_timer, 247 .timer = &mx25pdk_timer,
248 .init_machine = mx25pdk_init,
234MACHINE_END 249MACHINE_END
235
diff --git a/arch/arm/mach-imx/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c
index 164331518bdd..614b3c00c4a0 100644
--- a/arch/arm/mach-imx/mach-mx27_3ds.c
+++ b/arch/arm/mach-imx/mach-mx27_3ds.c
@@ -98,6 +98,9 @@ static const int mx27pdk_pins[] __initconst = {
98 PD22_PF_CSPI2_SCLK, 98 PD22_PF_CSPI2_SCLK,
99 PD23_PF_CSPI2_MISO, 99 PD23_PF_CSPI2_MISO,
100 PD24_PF_CSPI2_MOSI, 100 PD24_PF_CSPI2_MOSI,
101 /* I2C1 */
102 PD17_PF_I2C_DATA,
103 PD18_PF_I2C_CLK,
101}; 104};
102 105
103static const struct imxuart_platform_data uart_pdata __initconst = { 106static const struct imxuart_platform_data uart_pdata __initconst = {
@@ -159,13 +162,15 @@ static int otg_phy_init(void)
159 return 0; 162 return 0;
160} 163}
161 164
162#if defined(CONFIG_USB_ULPI) 165static int mx27_3ds_otg_init(struct platform_device *pdev)
166{
167 return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
168}
163 169
164static struct mxc_usbh_platform_data otg_pdata __initdata = { 170static struct mxc_usbh_platform_data otg_pdata __initdata = {
171 .init = mx27_3ds_otg_init,
165 .portsc = MXC_EHCI_MODE_ULPI, 172 .portsc = MXC_EHCI_MODE_ULPI,
166 .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
167}; 173};
168#endif
169 174
170static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { 175static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
171 .operating_mode = FSL_USB2_DR_DEVICE, 176 .operating_mode = FSL_USB2_DR_DEVICE,
@@ -216,7 +221,7 @@ static struct regulator_init_data vgen_init = {
216 .consumer_supplies = vgen_consumers, 221 .consumer_supplies = vgen_consumers,
217}; 222};
218 223
219static struct mc13783_regulator_init_data mx27_3ds_regulators[] = { 224static struct mc13xxx_regulator_init_data mx27_3ds_regulators[] = {
220 { 225 {
221 .id = MC13783_REG_VMMC1, 226 .id = MC13783_REG_VMMC1,
222 .init_data = &vmmc1_init, 227 .init_data = &vmmc1_init,
@@ -227,10 +232,10 @@ static struct mc13783_regulator_init_data mx27_3ds_regulators[] = {
227}; 232};
228 233
229/* MC13783 */ 234/* MC13783 */
230static struct mc13783_platform_data mc13783_pdata __initdata = { 235static struct mc13xxx_platform_data mc13783_pdata __initdata = {
231 .regulators = mx27_3ds_regulators, 236 .regulators = mx27_3ds_regulators,
232 .num_regulators = ARRAY_SIZE(mx27_3ds_regulators), 237 .num_regulators = ARRAY_SIZE(mx27_3ds_regulators),
233 .flags = MC13783_USE_REGULATOR, 238 .flags = MC13XXX_USE_REGULATOR,
234}; 239};
235 240
236/* SPI */ 241/* SPI */
@@ -253,6 +258,9 @@ static struct spi_board_info mx27_3ds_spi_devs[] __initdata = {
253 }, 258 },
254}; 259};
255 260
261static const struct imxi2c_platform_data mx27_3ds_i2c0_data __initconst = {
262 .bitrate = 100000,
263};
256 264
257static void __init mx27pdk_init(void) 265static void __init mx27pdk_init(void)
258{ 266{
@@ -265,14 +273,15 @@ static void __init mx27pdk_init(void)
265 imx27_add_mxc_mmc(0, &sdhc1_pdata); 273 imx27_add_mxc_mmc(0, &sdhc1_pdata);
266 imx27_add_imx2_wdt(NULL); 274 imx27_add_imx2_wdt(NULL);
267 otg_phy_init(); 275 otg_phy_init();
268#if defined(CONFIG_USB_ULPI) 276
269 if (otg_mode_host) { 277 if (otg_mode_host) {
270 otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, 278 otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
271 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); 279 ULPI_OTG_DRVVBUS_EXT);
272 280
273 imx27_add_mxc_ehci_otg(&otg_pdata); 281 if (otg_pdata.otg)
282 imx27_add_mxc_ehci_otg(&otg_pdata);
274 } 283 }
275#endif 284
276 if (!otg_mode_host) 285 if (!otg_mode_host)
277 imx27_add_fsl_usb2_udc(&otg_device_pdata); 286 imx27_add_fsl_usb2_udc(&otg_device_pdata);
278 287
@@ -282,6 +291,7 @@ static void __init mx27pdk_init(void)
282 291
283 if (mxc_expio_init(MX27_CS5_BASE_ADDR, EXPIO_PARENT_INT)) 292 if (mxc_expio_init(MX27_CS5_BASE_ADDR, EXPIO_PARENT_INT))
284 pr_warn("Init of the debugboard failed, all devices on the debugboard are unusable.\n"); 293 pr_warn("Init of the debugboard failed, all devices on the debugboard are unusable.\n");
294 imx27_add_imx_i2c(0, &mx27_3ds_i2c0_data);
285} 295}
286 296
287static void __init mx27pdk_timer_init(void) 297static void __init mx27pdk_timer_init(void)
@@ -295,9 +305,10 @@ static struct sys_timer mx27pdk_timer = {
295 305
296MACHINE_START(MX27_3DS, "Freescale MX27PDK") 306MACHINE_START(MX27_3DS, "Freescale MX27PDK")
297 /* maintainer: Freescale Semiconductor, Inc. */ 307 /* maintainer: Freescale Semiconductor, Inc. */
298 .boot_params = MX27_PHYS_OFFSET + 0x100, 308 .boot_params = MX27_PHYS_OFFSET + 0x100,
299 .map_io = mx27_map_io, 309 .map_io = mx27_map_io,
300 .init_irq = mx27_init_irq, 310 .init_early = imx27_init_early,
301 .init_machine = mx27pdk_init, 311 .init_irq = mx27_init_irq,
302 .timer = &mx27pdk_timer, 312 .timer = &mx27pdk_timer,
313 .init_machine = mx27pdk_init,
303MACHINE_END 314MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx27ads.c b/arch/arm/mach-imx/mach-mx27ads.c
index b832f960fec4..367d1e4384c7 100644
--- a/arch/arm/mach-imx/mach-mx27ads.c
+++ b/arch/arm/mach-imx/mach-mx27ads.c
@@ -344,9 +344,10 @@ static void __init mx27ads_map_io(void)
344 344
345MACHINE_START(MX27ADS, "Freescale i.MX27ADS") 345MACHINE_START(MX27ADS, "Freescale i.MX27ADS")
346 /* maintainer: Freescale Semiconductor, Inc. */ 346 /* maintainer: Freescale Semiconductor, Inc. */
347 .boot_params = MX27_PHYS_OFFSET + 0x100, 347 .boot_params = MX27_PHYS_OFFSET + 0x100,
348 .map_io = mx27ads_map_io, 348 .map_io = mx27ads_map_io,
349 .init_irq = mx27_init_irq, 349 .init_early = imx27_init_early,
350 .init_machine = mx27ads_board_init, 350 .init_irq = mx27_init_irq,
351 .timer = &mx27ads_timer, 351 .timer = &mx27ads_timer,
352 .init_machine = mx27ads_board_init,
352MACHINE_END 353MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mxt_td60.c b/arch/arm/mach-imx/mach-mxt_td60.c
index 4ce71b0401db..69787c30c320 100644
--- a/arch/arm/mach-imx/mach-mxt_td60.c
+++ b/arch/arm/mach-imx/mach-mxt_td60.c
@@ -266,10 +266,10 @@ static struct sys_timer mxt_td60_timer = {
266 266
267MACHINE_START(MXT_TD60, "Maxtrack i-MXT TD60") 267MACHINE_START(MXT_TD60, "Maxtrack i-MXT TD60")
268 /* maintainer: Maxtrack Industrial */ 268 /* maintainer: Maxtrack Industrial */
269 .boot_params = MX27_PHYS_OFFSET + 0x100, 269 .boot_params = MX27_PHYS_OFFSET + 0x100,
270 .map_io = mx27_map_io, 270 .map_io = mx27_map_io,
271 .init_irq = mx27_init_irq, 271 .init_early = imx27_init_early,
272 .init_machine = mxt_td60_board_init, 272 .init_irq = mx27_init_irq,
273 .timer = &mxt_td60_timer, 273 .timer = &mxt_td60_timer,
274 .init_machine = mxt_td60_board_init,
274MACHINE_END 275MACHINE_END
275
diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c
index cccc0a0a9c72..63e182556778 100644
--- a/arch/arm/mach-imx/mach-pca100.c
+++ b/arch/arm/mach-imx/mach-pca100.c
@@ -187,7 +187,6 @@ static struct i2c_board_info pca100_i2c_devices[] = {
187 } 187 }
188}; 188};
189 189
190#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
191static struct spi_eeprom at25320 = { 190static struct spi_eeprom at25320 = {
192 .name = "at25320an", 191 .name = "at25320an",
193 .byte_len = 4096, 192 .byte_len = 4096,
@@ -211,7 +210,6 @@ static const struct spi_imx_master pca100_spi0_data __initconst = {
211 .chipselect = pca100_spi_cs, 210 .chipselect = pca100_spi_cs,
212 .num_chipselect = ARRAY_SIZE(pca100_spi_cs), 211 .num_chipselect = ARRAY_SIZE(pca100_spi_cs),
213}; 212};
214#endif
215 213
216static void pca100_ac97_warm_reset(struct snd_ac97 *ac97) 214static void pca100_ac97_warm_reset(struct snd_ac97 *ac97)
217{ 215{
@@ -269,31 +267,33 @@ static const struct imxmmc_platform_data sdhc_pdata __initconst = {
269 .exit = pca100_sdhc2_exit, 267 .exit = pca100_sdhc2_exit,
270}; 268};
271 269
272#if defined(CONFIG_USB_ULPI)
273static int otg_phy_init(struct platform_device *pdev) 270static int otg_phy_init(struct platform_device *pdev)
274{ 271{
275 gpio_set_value(OTG_PHY_CS_GPIO, 0); 272 gpio_set_value(OTG_PHY_CS_GPIO, 0);
276 return 0; 273
274 mdelay(10);
275
276 return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
277} 277}
278 278
279static struct mxc_usbh_platform_data otg_pdata __initdata = { 279static struct mxc_usbh_platform_data otg_pdata __initdata = {
280 .init = otg_phy_init, 280 .init = otg_phy_init,
281 .portsc = MXC_EHCI_MODE_ULPI, 281 .portsc = MXC_EHCI_MODE_ULPI,
282 .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
283}; 282};
284 283
285static int usbh2_phy_init(struct platform_device *pdev) 284static int usbh2_phy_init(struct platform_device *pdev)
286{ 285{
287 gpio_set_value(USBH2_PHY_CS_GPIO, 0); 286 gpio_set_value(USBH2_PHY_CS_GPIO, 0);
288 return 0; 287
288 mdelay(10);
289
290 return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
289} 291}
290 292
291static struct mxc_usbh_platform_data usbh2_pdata __initdata = { 293static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
292 .init = usbh2_phy_init, 294 .init = usbh2_phy_init,
293 .portsc = MXC_EHCI_MODE_ULPI, 295 .portsc = MXC_EHCI_MODE_ULPI,
294 .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
295}; 296};
296#endif
297 297
298static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { 298static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
299 .operating_mode = FSL_USB2_DR_DEVICE, 299 .operating_mode = FSL_USB2_DR_DEVICE,
@@ -389,36 +389,33 @@ static void __init pca100_init(void)
389 389
390 imx27_add_imx_i2c(1, &pca100_i2c1_data); 390 imx27_add_imx_i2c(1, &pca100_i2c1_data);
391 391
392#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
393 mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_IN); 392 mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_IN);
394 mxc_gpio_mode(GPIO_PORTD | 27 | GPIO_GPIO | GPIO_IN); 393 mxc_gpio_mode(GPIO_PORTD | 27 | GPIO_GPIO | GPIO_IN);
395 spi_register_board_info(pca100_spi_board_info, 394 spi_register_board_info(pca100_spi_board_info,
396 ARRAY_SIZE(pca100_spi_board_info)); 395 ARRAY_SIZE(pca100_spi_board_info));
397 imx27_add_spi_imx0(&pca100_spi0_data); 396 imx27_add_spi_imx0(&pca100_spi0_data);
398#endif
399 397
400 gpio_request(OTG_PHY_CS_GPIO, "usb-otg-cs"); 398 gpio_request(OTG_PHY_CS_GPIO, "usb-otg-cs");
401 gpio_direction_output(OTG_PHY_CS_GPIO, 1); 399 gpio_direction_output(OTG_PHY_CS_GPIO, 1);
402 gpio_request(USBH2_PHY_CS_GPIO, "usb-host2-cs"); 400 gpio_request(USBH2_PHY_CS_GPIO, "usb-host2-cs");
403 gpio_direction_output(USBH2_PHY_CS_GPIO, 1); 401 gpio_direction_output(USBH2_PHY_CS_GPIO, 1);
404 402
405#if defined(CONFIG_USB_ULPI)
406 if (otg_mode_host) { 403 if (otg_mode_host) {
407 otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, 404 otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
408 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); 405 ULPI_OTG_DRVVBUS_EXT);
409 406
410 imx27_add_mxc_ehci_otg(&otg_pdata); 407 if (otg_pdata.otg)
408 imx27_add_mxc_ehci_otg(&otg_pdata);
409 } else {
410 gpio_set_value(OTG_PHY_CS_GPIO, 0);
411 imx27_add_fsl_usb2_udc(&otg_device_pdata);
411 } 412 }
412 413
413 usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, 414 usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
414 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); 415 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
415 416
416 imx27_add_mxc_ehci_hs(2, &usbh2_pdata); 417 if (usbh2_pdata.otg)
417#endif 418 imx27_add_mxc_ehci_hs(2, &usbh2_pdata);
418 if (!otg_mode_host) {
419 gpio_set_value(OTG_PHY_CS_GPIO, 0);
420 imx27_add_fsl_usb2_udc(&otg_device_pdata);
421 }
422 419
423 imx27_add_imx_fb(&pca100_fb_data); 420 imx27_add_imx_fb(&pca100_fb_data);
424 421
@@ -437,10 +434,10 @@ static struct sys_timer pca100_timer = {
437}; 434};
438 435
439MACHINE_START(PCA100, "phyCARD-i.MX27") 436MACHINE_START(PCA100, "phyCARD-i.MX27")
440 .boot_params = MX27_PHYS_OFFSET + 0x100, 437 .boot_params = MX27_PHYS_OFFSET + 0x100,
441 .map_io = mx27_map_io, 438 .map_io = mx27_map_io,
442 .init_irq = mx27_init_irq, 439 .init_early = imx27_init_early,
443 .init_machine = pca100_init, 440 .init_irq = mx27_init_irq,
444 .timer = &pca100_timer, 441 .init_machine = pca100_init,
442 .timer = &pca100_timer,
445MACHINE_END 443MACHINE_END
446
diff --git a/arch/arm/mach-imx/mach-pcm038.c b/arch/arm/mach-imx/mach-pcm038.c
index 505614803bc6..38c77084b615 100644
--- a/arch/arm/mach-imx/mach-pcm038.c
+++ b/arch/arm/mach-imx/mach-pcm038.c
@@ -252,7 +252,7 @@ static struct regulator_init_data cam_data = {
252 .consumer_supplies = cam_consumers, 252 .consumer_supplies = cam_consumers,
253}; 253};
254 254
255static struct mc13783_regulator_init_data pcm038_regulators[] = { 255static struct mc13xxx_regulator_init_data pcm038_regulators[] = {
256 { 256 {
257 .id = MC13783_REG_VCAM, 257 .id = MC13783_REG_VCAM,
258 .init_data = &cam_data, 258 .init_data = &cam_data,
@@ -262,11 +262,11 @@ static struct mc13783_regulator_init_data pcm038_regulators[] = {
262 }, 262 },
263}; 263};
264 264
265static struct mc13783_platform_data pcm038_pmic = { 265static struct mc13xxx_platform_data pcm038_pmic = {
266 .regulators = pcm038_regulators, 266 .regulators = pcm038_regulators,
267 .num_regulators = ARRAY_SIZE(pcm038_regulators), 267 .num_regulators = ARRAY_SIZE(pcm038_regulators),
268 .flags = MC13783_USE_ADC | MC13783_USE_REGULATOR | 268 .flags = MC13XXX_USE_ADC | MC13XXX_USE_REGULATOR |
269 MC13783_USE_TOUCHSCREEN, 269 MC13XXX_USE_TOUCHSCREEN,
270}; 270};
271 271
272static struct spi_board_info pcm038_spi_board_info[] __initdata = { 272static struct spi_board_info pcm038_spi_board_info[] __initdata = {
@@ -281,9 +281,15 @@ static struct spi_board_info pcm038_spi_board_info[] __initdata = {
281 } 281 }
282}; 282};
283 283
284static int pcm038_usbh2_init(struct platform_device *pdev)
285{
286 return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED |
287 MXC_EHCI_INTERFACE_DIFF_UNI);
288}
289
284static const struct mxc_usbh_platform_data usbh2_pdata __initconst = { 290static const struct mxc_usbh_platform_data usbh2_pdata __initconst = {
291 .init = pcm038_usbh2_init,
285 .portsc = MXC_EHCI_MODE_ULPI, 292 .portsc = MXC_EHCI_MODE_ULPI,
286 .flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_DIFF_UNI,
287}; 293};
288 294
289static void __init pcm038_init(void) 295static void __init pcm038_init(void)
@@ -340,9 +346,10 @@ static struct sys_timer pcm038_timer = {
340}; 346};
341 347
342MACHINE_START(PCM038, "phyCORE-i.MX27") 348MACHINE_START(PCM038, "phyCORE-i.MX27")
343 .boot_params = MX27_PHYS_OFFSET + 0x100, 349 .boot_params = MX27_PHYS_OFFSET + 0x100,
344 .map_io = mx27_map_io, 350 .map_io = mx27_map_io,
345 .init_irq = mx27_init_irq, 351 .init_early = imx27_init_early,
346 .init_machine = pcm038_init, 352 .init_irq = mx27_init_irq,
347 .timer = &pcm038_timer, 353 .timer = &pcm038_timer,
354 .init_machine = pcm038_init,
348MACHINE_END 355MACHINE_END
diff --git a/arch/arm/mach-imx/mach-scb9328.c b/arch/arm/mach-imx/mach-scb9328.c
index eae878f306c6..dcaee043628e 100644
--- a/arch/arm/mach-imx/mach-scb9328.c
+++ b/arch/arm/mach-imx/mach-scb9328.c
@@ -145,10 +145,11 @@ static struct sys_timer scb9328_timer = {
145}; 145};
146 146
147MACHINE_START(SCB9328, "Synertronixx scb9328") 147MACHINE_START(SCB9328, "Synertronixx scb9328")
148 /* Sascha Hauer */ 148 /* Sascha Hauer */
149 .boot_params = 0x08000100, 149 .boot_params = 0x08000100,
150 .map_io = mx1_map_io, 150 .map_io = mx1_map_io,
151 .init_irq = mx1_init_irq, 151 .init_early = imx1_init_early,
152 .timer = &scb9328_timer, 152 .init_irq = mx1_init_irq,
153 .init_machine = scb9328_init, 153 .timer = &scb9328_timer,
154 .init_machine = scb9328_init,
154MACHINE_END 155MACHINE_END
diff --git a/arch/arm/mach-imx/mm-imx1.c b/arch/arm/mach-imx/mm-imx1.c
index 729ae0915af8..2e482ba5a0e7 100644
--- a/arch/arm/mach-imx/mm-imx1.c
+++ b/arch/arm/mach-imx/mm-imx1.c
@@ -23,6 +23,9 @@
23 23
24#include <mach/common.h> 24#include <mach/common.h>
25#include <mach/hardware.h> 25#include <mach/hardware.h>
26#include <mach/gpio.h>
27#include <mach/irqs.h>
28#include <mach/iomux-v1.h>
26 29
27static struct map_desc imx_io_desc[] __initdata = { 30static struct map_desc imx_io_desc[] __initdata = {
28 imx_map_entry(MX1, IO, MT_DEVICE), 31 imx_map_entry(MX1, IO, MT_DEVICE),
@@ -30,16 +33,26 @@ static struct map_desc imx_io_desc[] __initdata = {
30 33
31void __init mx1_map_io(void) 34void __init mx1_map_io(void)
32{ 35{
36 iotable_init(imx_io_desc, ARRAY_SIZE(imx_io_desc));
37}
38
39void __init imx1_init_early(void)
40{
33 mxc_set_cpu_type(MXC_CPU_MX1); 41 mxc_set_cpu_type(MXC_CPU_MX1);
34 mxc_arch_reset_init(MX1_IO_ADDRESS(MX1_WDT_BASE_ADDR)); 42 mxc_arch_reset_init(MX1_IO_ADDRESS(MX1_WDT_BASE_ADDR));
35 43 imx_iomuxv1_init(MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR),
36 iotable_init(imx_io_desc, ARRAY_SIZE(imx_io_desc)); 44 MX1_NUM_GPIO_PORT);
37} 45}
38 46
39int imx1_register_gpios(void); 47static struct mxc_gpio_port imx1_gpio_ports[] = {
48 DEFINE_IMX_GPIO_PORT_IRQ(MX1, 0, 1, MX1_GPIO_INT_PORTA),
49 DEFINE_IMX_GPIO_PORT_IRQ(MX1, 1, 2, MX1_GPIO_INT_PORTB),
50 DEFINE_IMX_GPIO_PORT_IRQ(MX1, 2, 3, MX1_GPIO_INT_PORTC),
51 DEFINE_IMX_GPIO_PORT_IRQ(MX1, 3, 4, MX1_GPIO_INT_PORTD),
52};
40 53
41void __init mx1_init_irq(void) 54void __init mx1_init_irq(void)
42{ 55{
43 mxc_init_irq(MX1_IO_ADDRESS(MX1_AVIC_BASE_ADDR)); 56 mxc_init_irq(MX1_IO_ADDRESS(MX1_AVIC_BASE_ADDR));
44 imx1_register_gpios(); 57 mxc_gpio_init(imx1_gpio_ports, ARRAY_SIZE(imx1_gpio_ports));
45} 58}
diff --git a/arch/arm/mach-imx/mm-imx21.c b/arch/arm/mach-imx/mm-imx21.c
index e728af81d1b1..7a0c500ac2c8 100644
--- a/arch/arm/mach-imx/mm-imx21.c
+++ b/arch/arm/mach-imx/mm-imx21.c
@@ -24,6 +24,9 @@
24#include <mach/common.h> 24#include <mach/common.h>
25#include <asm/pgtable.h> 25#include <asm/pgtable.h>
26#include <asm/mach/map.h> 26#include <asm/mach/map.h>
27#include <mach/gpio.h>
28#include <mach/irqs.h>
29#include <mach/iomux-v1.h>
27 30
28/* MX21 memory map definition */ 31/* MX21 memory map definition */
29static struct map_desc imx21_io_desc[] __initdata = { 32static struct map_desc imx21_io_desc[] __initdata = {
@@ -56,16 +59,28 @@ static struct map_desc imx21_io_desc[] __initdata = {
56 */ 59 */
57void __init mx21_map_io(void) 60void __init mx21_map_io(void)
58{ 61{
62 iotable_init(imx21_io_desc, ARRAY_SIZE(imx21_io_desc));
63}
64
65void __init imx21_init_early(void)
66{
59 mxc_set_cpu_type(MXC_CPU_MX21); 67 mxc_set_cpu_type(MXC_CPU_MX21);
60 mxc_arch_reset_init(MX21_IO_ADDRESS(MX21_WDOG_BASE_ADDR)); 68 mxc_arch_reset_init(MX21_IO_ADDRESS(MX21_WDOG_BASE_ADDR));
61 69 imx_iomuxv1_init(MX21_IO_ADDRESS(MX21_GPIO_BASE_ADDR),
62 iotable_init(imx21_io_desc, ARRAY_SIZE(imx21_io_desc)); 70 MX21_NUM_GPIO_PORT);
63} 71}
64 72
65int imx21_register_gpios(void); 73static struct mxc_gpio_port imx21_gpio_ports[] = {
74 DEFINE_IMX_GPIO_PORT_IRQ(MX21, 0, 1, MX21_INT_GPIO),
75 DEFINE_IMX_GPIO_PORT(MX21, 1, 2),
76 DEFINE_IMX_GPIO_PORT(MX21, 2, 3),
77 DEFINE_IMX_GPIO_PORT(MX21, 3, 4),
78 DEFINE_IMX_GPIO_PORT(MX21, 4, 5),
79 DEFINE_IMX_GPIO_PORT(MX21, 5, 6),
80};
66 81
67void __init mx21_init_irq(void) 82void __init mx21_init_irq(void)
68{ 83{
69 mxc_init_irq(MX21_IO_ADDRESS(MX21_AVIC_BASE_ADDR)); 84 mxc_init_irq(MX21_IO_ADDRESS(MX21_AVIC_BASE_ADDR));
70 imx21_register_gpios(); 85 mxc_gpio_init(imx21_gpio_ports, ARRAY_SIZE(imx21_gpio_ports));
71} 86}
diff --git a/arch/arm/mach-imx/mm-imx25.c b/arch/arm/mach-imx/mm-imx25.c
index 2edec6ce8fe7..02f7b5c7fa8e 100644
--- a/arch/arm/mach-imx/mm-imx25.c
+++ b/arch/arm/mach-imx/mm-imx25.c
@@ -27,6 +27,8 @@
27#include <mach/hardware.h> 27#include <mach/hardware.h>
28#include <mach/mx25.h> 28#include <mach/mx25.h>
29#include <mach/iomux-v3.h> 29#include <mach/iomux-v3.h>
30#include <mach/gpio.h>
31#include <mach/irqs.h>
30 32
31/* 33/*
32 * This table defines static virtual address mappings for I/O regions. 34 * This table defines static virtual address mappings for I/O regions.
@@ -45,18 +47,26 @@ static struct map_desc mx25_io_desc[] __initdata = {
45 */ 47 */
46void __init mx25_map_io(void) 48void __init mx25_map_io(void)
47{ 49{
50 iotable_init(mx25_io_desc, ARRAY_SIZE(mx25_io_desc));
51}
52
53void __init imx25_init_early(void)
54{
48 mxc_set_cpu_type(MXC_CPU_MX25); 55 mxc_set_cpu_type(MXC_CPU_MX25);
49 mxc_iomux_v3_init(MX25_IO_ADDRESS(MX25_IOMUXC_BASE_ADDR)); 56 mxc_iomux_v3_init(MX25_IO_ADDRESS(MX25_IOMUXC_BASE_ADDR));
50 mxc_arch_reset_init(MX25_IO_ADDRESS(MX25_WDOG_BASE_ADDR)); 57 mxc_arch_reset_init(MX25_IO_ADDRESS(MX25_WDOG_BASE_ADDR));
51
52 iotable_init(mx25_io_desc, ARRAY_SIZE(mx25_io_desc));
53} 58}
54 59
55int imx25_register_gpios(void); 60static struct mxc_gpio_port imx25_gpio_ports[] = {
61 DEFINE_IMX_GPIO_PORT_IRQ(MX25, 0, 1, MX25_INT_GPIO1),
62 DEFINE_IMX_GPIO_PORT_IRQ(MX25, 1, 2, MX25_INT_GPIO2),
63 DEFINE_IMX_GPIO_PORT_IRQ(MX25, 2, 3, MX25_INT_GPIO3),
64 DEFINE_IMX_GPIO_PORT_IRQ(MX25, 3, 4, MX25_INT_GPIO4),
65};
56 66
57void __init mx25_init_irq(void) 67void __init mx25_init_irq(void)
58{ 68{
59 mxc_init_irq(MX25_IO_ADDRESS(MX25_AVIC_BASE_ADDR)); 69 mxc_init_irq(MX25_IO_ADDRESS(MX25_AVIC_BASE_ADDR));
60 imx25_register_gpios(); 70 mxc_gpio_init(imx25_gpio_ports, ARRAY_SIZE(imx25_gpio_ports));
61} 71}
62 72
diff --git a/arch/arm/mach-imx/mm-imx27.c b/arch/arm/mach-imx/mm-imx27.c
index 374e48b7a412..a6761a39f08c 100644
--- a/arch/arm/mach-imx/mm-imx27.c
+++ b/arch/arm/mach-imx/mm-imx27.c
@@ -24,6 +24,9 @@
24#include <mach/common.h> 24#include <mach/common.h>
25#include <asm/pgtable.h> 25#include <asm/pgtable.h>
26#include <asm/mach/map.h> 26#include <asm/mach/map.h>
27#include <mach/gpio.h>
28#include <mach/irqs.h>
29#include <mach/iomux-v1.h>
27 30
28/* MX27 memory map definition */ 31/* MX27 memory map definition */
29static struct map_desc imx27_io_desc[] __initdata = { 32static struct map_desc imx27_io_desc[] __initdata = {
@@ -56,16 +59,28 @@ static struct map_desc imx27_io_desc[] __initdata = {
56 */ 59 */
57void __init mx27_map_io(void) 60void __init mx27_map_io(void)
58{ 61{
62 iotable_init(imx27_io_desc, ARRAY_SIZE(imx27_io_desc));
63}
64
65void __init imx27_init_early(void)
66{
59 mxc_set_cpu_type(MXC_CPU_MX27); 67 mxc_set_cpu_type(MXC_CPU_MX27);
60 mxc_arch_reset_init(MX27_IO_ADDRESS(MX27_WDOG_BASE_ADDR)); 68 mxc_arch_reset_init(MX27_IO_ADDRESS(MX27_WDOG_BASE_ADDR));
61 69 imx_iomuxv1_init(MX27_IO_ADDRESS(MX27_GPIO_BASE_ADDR),
62 iotable_init(imx27_io_desc, ARRAY_SIZE(imx27_io_desc)); 70 MX27_NUM_GPIO_PORT);
63} 71}
64 72
65int imx27_register_gpios(void); 73static struct mxc_gpio_port imx27_gpio_ports[] = {
74 DEFINE_IMX_GPIO_PORT_IRQ(MX27, 0, 1, MX27_INT_GPIO),
75 DEFINE_IMX_GPIO_PORT(MX27, 1, 2),
76 DEFINE_IMX_GPIO_PORT(MX27, 2, 3),
77 DEFINE_IMX_GPIO_PORT(MX27, 3, 4),
78 DEFINE_IMX_GPIO_PORT(MX27, 4, 5),
79 DEFINE_IMX_GPIO_PORT(MX27, 5, 6),
80};
66 81
67void __init mx27_init_irq(void) 82void __init mx27_init_irq(void)
68{ 83{
69 mxc_init_irq(MX27_IO_ADDRESS(MX27_AVIC_BASE_ADDR)); 84 mxc_init_irq(MX27_IO_ADDRESS(MX27_AVIC_BASE_ADDR));
70 imx27_register_gpios(); 85 mxc_gpio_init(imx27_gpio_ports, ARRAY_SIZE(imx27_gpio_ports));
71} 86}
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index 3688123b5ad8..20e71df3e3bb 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -21,6 +21,7 @@
21#include <net/dsa.h> 21#include <net/dsa.h>
22#include <asm/page.h> 22#include <asm/page.h>
23#include <asm/timex.h> 23#include <asm/timex.h>
24#include <asm/kexec.h>
24#include <asm/mach/map.h> 25#include <asm/mach/map.h>
25#include <asm/mach/time.h> 26#include <asm/mach/time.h>
26#include <mach/kirkwood.h> 27#include <mach/kirkwood.h>
@@ -846,9 +847,14 @@ static void __init kirkwood_wdt_init(void)
846/***************************************************************************** 847/*****************************************************************************
847 * Time handling 848 * Time handling
848 ****************************************************************************/ 849 ****************************************************************************/
850void __init kirkwood_init_early(void)
851{
852 orion_time_set_base(TIMER_VIRT_BASE);
853}
854
849int kirkwood_tclk; 855int kirkwood_tclk;
850 856
851int __init kirkwood_find_tclk(void) 857static int __init kirkwood_find_tclk(void)
852{ 858{
853 u32 dev, rev; 859 u32 dev, rev;
854 860
@@ -864,7 +870,9 @@ int __init kirkwood_find_tclk(void)
864static void __init kirkwood_timer_init(void) 870static void __init kirkwood_timer_init(void)
865{ 871{
866 kirkwood_tclk = kirkwood_find_tclk(); 872 kirkwood_tclk = kirkwood_find_tclk();
867 orion_time_init(IRQ_KIRKWOOD_BRIDGE, kirkwood_tclk); 873
874 orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
875 IRQ_KIRKWOOD_BRIDGE, kirkwood_tclk);
868} 876}
869 877
870struct sys_timer kirkwood_timer = { 878struct sys_timer kirkwood_timer = {
@@ -1003,6 +1011,10 @@ void __init kirkwood_init(void)
1003 kirkwood_xor0_init(); 1011 kirkwood_xor0_init();
1004 kirkwood_xor1_init(); 1012 kirkwood_xor1_init();
1005 kirkwood_crypto_init(); 1013 kirkwood_crypto_init();
1014
1015#ifdef CONFIG_KEXEC
1016 kexec_reinit = kirkwood_enable_pcie;
1017#endif
1006} 1018}
1007 1019
1008static int __init kirkwood_clock_gate(void) 1020static int __init kirkwood_clock_gate(void)
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index 95bb0a73adfb..b9b0f0968a36 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -27,11 +27,13 @@ struct kirkwood_asoc_platform_data;
27 */ 27 */
28void kirkwood_map_io(void); 28void kirkwood_map_io(void);
29void kirkwood_init(void); 29void kirkwood_init(void);
30void kirkwood_init_early(void);
30void kirkwood_init_irq(void); 31void kirkwood_init_irq(void);
31 32
32extern struct mbus_dram_target_info kirkwood_mbus_dram_info; 33extern struct mbus_dram_target_info kirkwood_mbus_dram_info;
33void kirkwood_setup_cpu_mbus(void); 34void kirkwood_setup_cpu_mbus(void);
34 35
36void kirkwood_enable_pcie(void);
35void kirkwood_pcie_id(u32 *dev, u32 *rev); 37void kirkwood_pcie_id(u32 *dev, u32 *rev);
36 38
37void kirkwood_ehci_init(void); 39void kirkwood_ehci_init(void);
diff --git a/arch/arm/mach-kirkwood/d2net_v2-setup.c b/arch/arm/mach-kirkwood/d2net_v2-setup.c
index a31c9499ab36..043cfd5e140b 100644
--- a/arch/arm/mach-kirkwood/d2net_v2-setup.c
+++ b/arch/arm/mach-kirkwood/d2net_v2-setup.c
@@ -224,6 +224,7 @@ MACHINE_START(D2NET_V2, "LaCie d2 Network v2")
224 .boot_params = 0x00000100, 224 .boot_params = 0x00000100,
225 .init_machine = d2net_v2_init, 225 .init_machine = d2net_v2_init,
226 .map_io = kirkwood_map_io, 226 .map_io = kirkwood_map_io,
227 .init_early = kirkwood_init_early,
227 .init_irq = kirkwood_init_irq, 228 .init_irq = kirkwood_init_irq,
228 .timer = &kirkwood_timer, 229 .timer = &kirkwood_timer,
229MACHINE_END 230MACHINE_END
diff --git a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
index 9ea71182d31a..bff04e04d679 100644
--- a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
+++ b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
@@ -100,6 +100,7 @@ MACHINE_START(DB88F6281_BP, "Marvell DB-88F6281-BP Development Board")
100 .boot_params = 0x00000100, 100 .boot_params = 0x00000100,
101 .init_machine = db88f6281_init, 101 .init_machine = db88f6281_init,
102 .map_io = kirkwood_map_io, 102 .map_io = kirkwood_map_io,
103 .init_early = kirkwood_init_early,
103 .init_irq = kirkwood_init_irq, 104 .init_irq = kirkwood_init_irq,
104 .timer = &kirkwood_timer, 105 .timer = &kirkwood_timer,
105MACHINE_END 106MACHINE_END
diff --git a/arch/arm/mach-kirkwood/dockstar-setup.c b/arch/arm/mach-kirkwood/dockstar-setup.c
index 433ea368c060..f14dfb8508c5 100644
--- a/arch/arm/mach-kirkwood/dockstar-setup.c
+++ b/arch/arm/mach-kirkwood/dockstar-setup.c
@@ -105,6 +105,7 @@ MACHINE_START(DOCKSTAR, "Seagate FreeAgent DockStar")
105 .boot_params = 0x00000100, 105 .boot_params = 0x00000100,
106 .init_machine = dockstar_init, 106 .init_machine = dockstar_init,
107 .map_io = kirkwood_map_io, 107 .map_io = kirkwood_map_io,
108 .init_early = kirkwood_init_early,
108 .init_irq = kirkwood_init_irq, 109 .init_irq = kirkwood_init_irq,
109 .timer = &kirkwood_timer, 110 .timer = &kirkwood_timer,
110MACHINE_END 111MACHINE_END
diff --git a/arch/arm/mach-kirkwood/guruplug-setup.c b/arch/arm/mach-kirkwood/guruplug-setup.c
index 8f47dc0a2fef..41d1b40696a3 100644
--- a/arch/arm/mach-kirkwood/guruplug-setup.c
+++ b/arch/arm/mach-kirkwood/guruplug-setup.c
@@ -124,6 +124,7 @@ MACHINE_START(GURUPLUG, "Marvell GuruPlug Reference Board")
124 .boot_params = 0x00000100, 124 .boot_params = 0x00000100,
125 .init_machine = guruplug_init, 125 .init_machine = guruplug_init,
126 .map_io = kirkwood_map_io, 126 .map_io = kirkwood_map_io,
127 .init_early = kirkwood_init_early,
127 .init_irq = kirkwood_init_irq, 128 .init_irq = kirkwood_init_irq,
128 .timer = &kirkwood_timer, 129 .timer = &kirkwood_timer,
129MACHINE_END 130MACHINE_END
diff --git a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
index aff0e1327e38..957bd7997d7e 100644
--- a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
+++ b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
@@ -29,9 +29,6 @@
29#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110) 29#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110)
30#define WDT_INT_REQ 0x0008 30#define WDT_INT_REQ 0x0008
31 31
32#define BRIDGE_MASK (BRIDGE_VIRT_BASE | 0x0114)
33#define BRIDGE_INT_TIMER0 0x0002
34#define BRIDGE_INT_TIMER1 0x0004
35#define BRIDGE_INT_TIMER1_CLR (~0x0004) 32#define BRIDGE_INT_TIMER1_CLR (~0x0004)
36 33
37#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200) 34#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200)
diff --git a/arch/arm/mach-kirkwood/include/mach/gpio.h b/arch/arm/mach-kirkwood/include/mach/gpio.h
index 81b335eb62ec..84f340b546c0 100644
--- a/arch/arm/mach-kirkwood/include/mach/gpio.h
+++ b/arch/arm/mach-kirkwood/include/mach/gpio.h
@@ -6,33 +6,4 @@
6 * warranty of any kind, whether express or implied. 6 * warranty of any kind, whether express or implied.
7 */ 7 */
8 8
9#ifndef __ASM_ARCH_GPIO_H
10#define __ASM_ARCH_GPIO_H
11
12#include <mach/irqs.h>
13#include <plat/gpio.h> 9#include <plat/gpio.h>
14#include <asm-generic/gpio.h> /* cansleep wrappers */
15
16#define GPIO_MAX 50
17#define GPIO_OFF(pin) (((pin) >> 5) ? 0x0140 : 0x0100)
18#define GPIO_OUT(pin) (DEV_BUS_VIRT_BASE + GPIO_OFF(pin) + 0x00)
19#define GPIO_IO_CONF(pin) (DEV_BUS_VIRT_BASE + GPIO_OFF(pin) + 0x04)
20#define GPIO_BLINK_EN(pin) (DEV_BUS_VIRT_BASE + GPIO_OFF(pin) + 0x08)
21#define GPIO_IN_POL(pin) (DEV_BUS_VIRT_BASE + GPIO_OFF(pin) + 0x0c)
22#define GPIO_DATA_IN(pin) (DEV_BUS_VIRT_BASE + GPIO_OFF(pin) + 0x10)
23#define GPIO_EDGE_CAUSE(pin) (DEV_BUS_VIRT_BASE + GPIO_OFF(pin) + 0x14)
24#define GPIO_EDGE_MASK(pin) (DEV_BUS_VIRT_BASE + GPIO_OFF(pin) + 0x18)
25#define GPIO_LEVEL_MASK(pin) (DEV_BUS_VIRT_BASE + GPIO_OFF(pin) + 0x1c)
26
27static inline int gpio_to_irq(int pin)
28{
29 return pin + IRQ_KIRKWOOD_GPIO_START;
30}
31
32static inline int irq_to_gpio(int irq)
33{
34 return irq - IRQ_KIRKWOOD_GPIO_START;
35}
36
37
38#endif
diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
index 6e924b398919..010bdeb4ac5f 100644
--- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h
+++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
@@ -69,6 +69,8 @@
69#define DEV_BUS_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x10000) 69#define DEV_BUS_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x10000)
70#define SAMPLE_AT_RESET (DEV_BUS_VIRT_BASE | 0x0030) 70#define SAMPLE_AT_RESET (DEV_BUS_VIRT_BASE | 0x0030)
71#define DEVICE_ID (DEV_BUS_VIRT_BASE | 0x0034) 71#define DEVICE_ID (DEV_BUS_VIRT_BASE | 0x0034)
72#define GPIO_LOW_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x0100)
73#define GPIO_HIGH_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x0140)
72#define RTC_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x0300) 74#define RTC_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x0300)
73#define SPI_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x0600) 75#define SPI_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x0600)
74#define I2C_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x1000) 76#define I2C_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x1000)
diff --git a/arch/arm/mach-kirkwood/irq.c b/arch/arm/mach-kirkwood/irq.c
index 28020abf49e1..cbdb5863d13b 100644
--- a/arch/arm/mach-kirkwood/irq.c
+++ b/arch/arm/mach-kirkwood/irq.c
@@ -27,31 +27,21 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
27 27
28void __init kirkwood_init_irq(void) 28void __init kirkwood_init_irq(void)
29{ 29{
30 int i;
31
32 orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF)); 30 orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF));
33 orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF)); 31 orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF));
34 32
35 /* 33 /*
36 * Mask and clear GPIO IRQ interrupts. 34 * Initialize gpiolib for GPIOs 0-49.
37 */ 35 */
38 writel(0, GPIO_LEVEL_MASK(0)); 36 orion_gpio_init(0, 32, GPIO_LOW_VIRT_BASE, 0,
39 writel(0, GPIO_EDGE_MASK(0)); 37 IRQ_KIRKWOOD_GPIO_START);
40 writel(0, GPIO_EDGE_CAUSE(0));
41 writel(0, GPIO_LEVEL_MASK(32));
42 writel(0, GPIO_EDGE_MASK(32));
43 writel(0, GPIO_EDGE_CAUSE(32));
44
45 for (i = IRQ_KIRKWOOD_GPIO_START; i < NR_IRQS; i++) {
46 set_irq_chip(i, &orion_gpio_irq_chip);
47 set_irq_handler(i, handle_level_irq);
48 irq_desc[i].status |= IRQ_LEVEL;
49 set_irq_flags(i, IRQF_VALID);
50 }
51 set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_0_7, gpio_irq_handler); 38 set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_0_7, gpio_irq_handler);
52 set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_8_15, gpio_irq_handler); 39 set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_8_15, gpio_irq_handler);
53 set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_16_23, gpio_irq_handler); 40 set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_16_23, gpio_irq_handler);
54 set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_24_31, gpio_irq_handler); 41 set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_24_31, gpio_irq_handler);
42
43 orion_gpio_init(32, 18, GPIO_HIGH_VIRT_BASE, 0,
44 IRQ_KIRKWOOD_GPIO_START + 32);
55 set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_0_7, gpio_irq_handler); 45 set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_0_7, gpio_irq_handler);
56 set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_8_15, gpio_irq_handler); 46 set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_8_15, gpio_irq_handler);
57 set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_16_23, gpio_irq_handler); 47 set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_16_23, gpio_irq_handler);
diff --git a/arch/arm/mach-kirkwood/mpp.c b/arch/arm/mach-kirkwood/mpp.c
index 27901f702feb..7ce201848067 100644
--- a/arch/arm/mach-kirkwood/mpp.c
+++ b/arch/arm/mach-kirkwood/mpp.c
@@ -49,9 +49,6 @@ void __init kirkwood_mpp_conf(unsigned int *mpp_list)
49 if (!variant_mask) 49 if (!variant_mask)
50 return; 50 return;
51 51
52 /* Initialize gpiolib. */
53 orion_gpio_init();
54
55 printk(KERN_DEBUG "initial MPP regs:"); 52 printk(KERN_DEBUG "initial MPP regs:");
56 for (i = 0; i < MPP_NR_REGS; i++) { 53 for (i = 0; i < MPP_NR_REGS; i++) {
57 mpp_ctrl[i] = readl(MPP_CTRL(i)); 54 mpp_ctrl[i] = readl(MPP_CTRL(i));
diff --git a/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c b/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
index 1e5266f57e2a..00cca22eca6f 100644
--- a/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
+++ b/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
@@ -166,6 +166,7 @@ MACHINE_START(MV88F6281GTW_GE, "Marvell 88F6281 GTW GE Board")
166 .boot_params = 0x00000100, 166 .boot_params = 0x00000100,
167 .init_machine = mv88f6281gtw_ge_init, 167 .init_machine = mv88f6281gtw_ge_init,
168 .map_io = kirkwood_map_io, 168 .map_io = kirkwood_map_io,
169 .init_early = kirkwood_init_early,
169 .init_irq = kirkwood_init_irq, 170 .init_irq = kirkwood_init_irq,
170 .timer = &kirkwood_timer, 171 .timer = &kirkwood_timer,
171MACHINE_END 172MACHINE_END
diff --git a/arch/arm/mach-kirkwood/netspace_v2-setup.c b/arch/arm/mach-kirkwood/netspace_v2-setup.c
index 65ee21fd2f3b..7cdab5776452 100644
--- a/arch/arm/mach-kirkwood/netspace_v2-setup.c
+++ b/arch/arm/mach-kirkwood/netspace_v2-setup.c
@@ -261,6 +261,7 @@ MACHINE_START(NETSPACE_V2, "LaCie Network Space v2")
261 .boot_params = 0x00000100, 261 .boot_params = 0x00000100,
262 .init_machine = netspace_v2_init, 262 .init_machine = netspace_v2_init,
263 .map_io = kirkwood_map_io, 263 .map_io = kirkwood_map_io,
264 .init_early = kirkwood_init_early,
264 .init_irq = kirkwood_init_irq, 265 .init_irq = kirkwood_init_irq,
265 .timer = &kirkwood_timer, 266 .timer = &kirkwood_timer,
266MACHINE_END 267MACHINE_END
@@ -271,6 +272,7 @@ MACHINE_START(INETSPACE_V2, "LaCie Internet Space v2")
271 .boot_params = 0x00000100, 272 .boot_params = 0x00000100,
272 .init_machine = netspace_v2_init, 273 .init_machine = netspace_v2_init,
273 .map_io = kirkwood_map_io, 274 .map_io = kirkwood_map_io,
275 .init_early = kirkwood_init_early,
274 .init_irq = kirkwood_init_irq, 276 .init_irq = kirkwood_init_irq,
275 .timer = &kirkwood_timer, 277 .timer = &kirkwood_timer,
276MACHINE_END 278MACHINE_END
@@ -281,6 +283,7 @@ MACHINE_START(NETSPACE_MAX_V2, "LaCie Network Space Max v2")
281 .boot_params = 0x00000100, 283 .boot_params = 0x00000100,
282 .init_machine = netspace_v2_init, 284 .init_machine = netspace_v2_init,
283 .map_io = kirkwood_map_io, 285 .map_io = kirkwood_map_io,
286 .init_early = kirkwood_init_early,
284 .init_irq = kirkwood_init_irq, 287 .init_irq = kirkwood_init_irq,
285 .timer = &kirkwood_timer, 288 .timer = &kirkwood_timer,
286MACHINE_END 289MACHINE_END
diff --git a/arch/arm/mach-kirkwood/netxbig_v2-setup.c b/arch/arm/mach-kirkwood/netxbig_v2-setup.c
index 93afd3c8bfd8..6be627deb0fc 100644
--- a/arch/arm/mach-kirkwood/netxbig_v2-setup.c
+++ b/arch/arm/mach-kirkwood/netxbig_v2-setup.c
@@ -402,6 +402,7 @@ MACHINE_START(NET2BIG_V2, "LaCie 2Big Network v2")
402 .boot_params = 0x00000100, 402 .boot_params = 0x00000100,
403 .init_machine = netxbig_v2_init, 403 .init_machine = netxbig_v2_init,
404 .map_io = kirkwood_map_io, 404 .map_io = kirkwood_map_io,
405 .init_early = kirkwood_init_early,
405 .init_irq = kirkwood_init_irq, 406 .init_irq = kirkwood_init_irq,
406 .timer = &kirkwood_timer, 407 .timer = &kirkwood_timer,
407MACHINE_END 408MACHINE_END
@@ -412,6 +413,7 @@ MACHINE_START(NET5BIG_V2, "LaCie 5Big Network v2")
412 .boot_params = 0x00000100, 413 .boot_params = 0x00000100,
413 .init_machine = netxbig_v2_init, 414 .init_machine = netxbig_v2_init,
414 .map_io = kirkwood_map_io, 415 .map_io = kirkwood_map_io,
416 .init_early = kirkwood_init_early,
415 .init_irq = kirkwood_init_irq, 417 .init_irq = kirkwood_init_irq,
416 .timer = &kirkwood_timer, 418 .timer = &kirkwood_timer,
417MACHINE_END 419MACHINE_END
diff --git a/arch/arm/mach-kirkwood/openrd-setup.c b/arch/arm/mach-kirkwood/openrd-setup.c
index cfcca4174e25..f69beeff4450 100644
--- a/arch/arm/mach-kirkwood/openrd-setup.c
+++ b/arch/arm/mach-kirkwood/openrd-setup.c
@@ -217,6 +217,7 @@ MACHINE_START(OPENRD_BASE, "Marvell OpenRD Base Board")
217 .boot_params = 0x00000100, 217 .boot_params = 0x00000100,
218 .init_machine = openrd_init, 218 .init_machine = openrd_init,
219 .map_io = kirkwood_map_io, 219 .map_io = kirkwood_map_io,
220 .init_early = kirkwood_init_early,
220 .init_irq = kirkwood_init_irq, 221 .init_irq = kirkwood_init_irq,
221 .timer = &kirkwood_timer, 222 .timer = &kirkwood_timer,
222MACHINE_END 223MACHINE_END
@@ -228,6 +229,7 @@ MACHINE_START(OPENRD_CLIENT, "Marvell OpenRD Client Board")
228 .boot_params = 0x00000100, 229 .boot_params = 0x00000100,
229 .init_machine = openrd_init, 230 .init_machine = openrd_init,
230 .map_io = kirkwood_map_io, 231 .map_io = kirkwood_map_io,
232 .init_early = kirkwood_init_early,
231 .init_irq = kirkwood_init_irq, 233 .init_irq = kirkwood_init_irq,
232 .timer = &kirkwood_timer, 234 .timer = &kirkwood_timer,
233MACHINE_END 235MACHINE_END
@@ -239,6 +241,7 @@ MACHINE_START(OPENRD_ULTIMATE, "Marvell OpenRD Ultimate Board")
239 .boot_params = 0x00000100, 241 .boot_params = 0x00000100,
240 .init_machine = openrd_init, 242 .init_machine = openrd_init,
241 .map_io = kirkwood_map_io, 243 .map_io = kirkwood_map_io,
244 .init_early = kirkwood_init_early,
242 .init_irq = kirkwood_init_irq, 245 .init_irq = kirkwood_init_irq,
243 .timer = &kirkwood_timer, 246 .timer = &kirkwood_timer,
244MACHINE_END 247MACHINE_END
diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c
index 513ad3102d7c..ca294ff6d5be 100644
--- a/arch/arm/mach-kirkwood/pcie.c
+++ b/arch/arm/mach-kirkwood/pcie.c
@@ -18,8 +18,16 @@
18#include <mach/bridge-regs.h> 18#include <mach/bridge-regs.h>
19#include "common.h" 19#include "common.h"
20 20
21void kirkwood_enable_pcie(void)
22{
23 u32 curr = readl(CLOCK_GATING_CTRL);
24 if (!(curr & CGC_PEX0))
25 writel(curr | CGC_PEX0, CLOCK_GATING_CTRL);
26}
27
21void __init kirkwood_pcie_id(u32 *dev, u32 *rev) 28void __init kirkwood_pcie_id(u32 *dev, u32 *rev)
22{ 29{
30 kirkwood_enable_pcie();
23 *dev = orion_pcie_dev_id((void __iomem *)PCIE_VIRT_BASE); 31 *dev = orion_pcie_dev_id((void __iomem *)PCIE_VIRT_BASE);
24 *rev = orion_pcie_rev((void __iomem *)PCIE_VIRT_BASE); 32 *rev = orion_pcie_rev((void __iomem *)PCIE_VIRT_BASE);
25} 33}
diff --git a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
index 0049614cd324..75c6601b8d87 100644
--- a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
+++ b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
@@ -82,6 +82,7 @@ MACHINE_START(RD88F6192_NAS, "Marvell RD-88F6192-NAS Development Board")
82 .boot_params = 0x00000100, 82 .boot_params = 0x00000100,
83 .init_machine = rd88f6192_init, 83 .init_machine = rd88f6192_init,
84 .map_io = kirkwood_map_io, 84 .map_io = kirkwood_map_io,
85 .init_early = kirkwood_init_early,
85 .init_irq = kirkwood_init_irq, 86 .init_irq = kirkwood_init_irq,
86 .timer = &kirkwood_timer, 87 .timer = &kirkwood_timer,
87MACHINE_END 88MACHINE_END
diff --git a/arch/arm/mach-kirkwood/rd88f6281-setup.c b/arch/arm/mach-kirkwood/rd88f6281-setup.c
index 0998a08cf42d..0f75494d5902 100644
--- a/arch/arm/mach-kirkwood/rd88f6281-setup.c
+++ b/arch/arm/mach-kirkwood/rd88f6281-setup.c
@@ -118,6 +118,7 @@ MACHINE_START(RD88F6281, "Marvell RD-88F6281 Reference Board")
118 .boot_params = 0x00000100, 118 .boot_params = 0x00000100,
119 .init_machine = rd88f6281_init, 119 .init_machine = rd88f6281_init,
120 .map_io = kirkwood_map_io, 120 .map_io = kirkwood_map_io,
121 .init_early = kirkwood_init_early,
121 .init_irq = kirkwood_init_irq, 122 .init_irq = kirkwood_init_irq,
122 .timer = &kirkwood_timer, 123 .timer = &kirkwood_timer,
123MACHINE_END 124MACHINE_END
diff --git a/arch/arm/mach-kirkwood/sheevaplug-setup.c b/arch/arm/mach-kirkwood/sheevaplug-setup.c
index d2eec35dfe0f..0a95063f6d32 100644
--- a/arch/arm/mach-kirkwood/sheevaplug-setup.c
+++ b/arch/arm/mach-kirkwood/sheevaplug-setup.c
@@ -134,6 +134,7 @@ MACHINE_START(SHEEVAPLUG, "Marvell SheevaPlug Reference Board")
134 .boot_params = 0x00000100, 134 .boot_params = 0x00000100,
135 .init_machine = sheevaplug_init, 135 .init_machine = sheevaplug_init,
136 .map_io = kirkwood_map_io, 136 .map_io = kirkwood_map_io,
137 .init_early = kirkwood_init_early,
137 .init_irq = kirkwood_init_irq, 138 .init_irq = kirkwood_init_irq,
138 .timer = &kirkwood_timer, 139 .timer = &kirkwood_timer,
139MACHINE_END 140MACHINE_END
@@ -144,6 +145,7 @@ MACHINE_START(ESATA_SHEEVAPLUG, "Marvell eSATA SheevaPlug Reference Board")
144 .boot_params = 0x00000100, 145 .boot_params = 0x00000100,
145 .init_machine = sheevaplug_init, 146 .init_machine = sheevaplug_init,
146 .map_io = kirkwood_map_io, 147 .map_io = kirkwood_map_io,
148 .init_early = kirkwood_init_early,
147 .init_irq = kirkwood_init_irq, 149 .init_irq = kirkwood_init_irq,
148 .timer = &kirkwood_timer, 150 .timer = &kirkwood_timer,
149MACHINE_END 151MACHINE_END
diff --git a/arch/arm/mach-kirkwood/t5325-setup.c b/arch/arm/mach-kirkwood/t5325-setup.c
index ce50e61aac9f..e6b9b1b22a35 100644
--- a/arch/arm/mach-kirkwood/t5325-setup.c
+++ b/arch/arm/mach-kirkwood/t5325-setup.c
@@ -23,6 +23,7 @@
23#include <linux/gpio.h> 23#include <linux/gpio.h>
24#include <linux/gpio_keys.h> 24#include <linux/gpio_keys.h>
25#include <linux/input.h> 25#include <linux/input.h>
26#include <sound/alc5623.h>
26#include <asm/mach-types.h> 27#include <asm/mach-types.h>
27#include <asm/mach/arch.h> 28#include <asm/mach/arch.h>
28#include <mach/kirkwood.h> 29#include <mach/kirkwood.h>
@@ -134,6 +135,7 @@ static unsigned int hp_t5325_mpp_config[] __initdata = {
134 MPP33_GE1_TXCTL, 135 MPP33_GE1_TXCTL,
135 MPP39_AU_I2SBCLK, 136 MPP39_AU_I2SBCLK,
136 MPP40_AU_I2SDO, 137 MPP40_AU_I2SDO,
138 MPP43_AU_I2SDI,
137 MPP41_AU_I2SLRCLK, 139 MPP41_AU_I2SLRCLK,
138 MPP42_AU_I2SMCLK, 140 MPP42_AU_I2SMCLK,
139 MPP45_GPIO, /* Power button */ 141 MPP45_GPIO, /* Power button */
@@ -141,6 +143,18 @@ static unsigned int hp_t5325_mpp_config[] __initdata = {
141 0 143 0
142}; 144};
143 145
146static struct alc5623_platform_data alc5621_data = {
147 .add_ctrl = 0x3700,
148 .jack_det_ctrl = 0x4810,
149};
150
151static struct i2c_board_info i2c_board_info[] __initdata = {
152 {
153 I2C_BOARD_INFO("alc5621", 0x1a),
154 .platform_data = &alc5621_data,
155 },
156};
157
144#define HP_T5325_GPIO_POWER_OFF 48 158#define HP_T5325_GPIO_POWER_OFF 48
145 159
146static void hp_t5325_power_off(void) 160static void hp_t5325_power_off(void)
@@ -166,6 +180,9 @@ static void __init hp_t5325_init(void)
166 kirkwood_ehci_init(); 180 kirkwood_ehci_init();
167 platform_device_register(&hp_t5325_button_device); 181 platform_device_register(&hp_t5325_button_device);
168 182
183 i2c_register_board_info(0, i2c_board_info, ARRAY_SIZE(i2c_board_info));
184 kirkwood_audio_init();
185
169 if (gpio_request(HP_T5325_GPIO_POWER_OFF, "power-off") == 0 && 186 if (gpio_request(HP_T5325_GPIO_POWER_OFF, "power-off") == 0 &&
170 gpio_direction_output(HP_T5325_GPIO_POWER_OFF, 0) == 0) 187 gpio_direction_output(HP_T5325_GPIO_POWER_OFF, 0) == 0)
171 pm_power_off = hp_t5325_power_off; 188 pm_power_off = hp_t5325_power_off;
@@ -187,6 +204,7 @@ MACHINE_START(T5325, "HP t5325 Thin Client")
187 .boot_params = 0x00000100, 204 .boot_params = 0x00000100,
188 .init_machine = hp_t5325_init, 205 .init_machine = hp_t5325_init,
189 .map_io = kirkwood_map_io, 206 .map_io = kirkwood_map_io,
207 .init_early = kirkwood_init_early,
190 .init_irq = kirkwood_init_irq, 208 .init_irq = kirkwood_init_irq,
191 .timer = &kirkwood_timer, 209 .timer = &kirkwood_timer,
192MACHINE_END 210MACHINE_END
diff --git a/arch/arm/mach-kirkwood/ts219-setup.c b/arch/arm/mach-kirkwood/ts219-setup.c
index dc999c4c5806..68f32f2bf552 100644
--- a/arch/arm/mach-kirkwood/ts219-setup.c
+++ b/arch/arm/mach-kirkwood/ts219-setup.c
@@ -135,6 +135,7 @@ MACHINE_START(TS219, "QNAP TS-119/TS-219")
135 .boot_params = 0x00000100, 135 .boot_params = 0x00000100,
136 .init_machine = qnap_ts219_init, 136 .init_machine = qnap_ts219_init,
137 .map_io = kirkwood_map_io, 137 .map_io = kirkwood_map_io,
138 .init_early = kirkwood_init_early,
138 .init_irq = kirkwood_init_irq, 139 .init_irq = kirkwood_init_irq,
139 .timer = &kirkwood_timer, 140 .timer = &kirkwood_timer,
140MACHINE_END 141MACHINE_END
diff --git a/arch/arm/mach-kirkwood/ts41x-setup.c b/arch/arm/mach-kirkwood/ts41x-setup.c
index 9a44029915e2..d5d009970705 100644
--- a/arch/arm/mach-kirkwood/ts41x-setup.c
+++ b/arch/arm/mach-kirkwood/ts41x-setup.c
@@ -154,6 +154,8 @@ static void __init qnap_ts41x_init(void)
154static int __init ts41x_pci_init(void) 154static int __init ts41x_pci_init(void)
155{ 155{
156 if (machine_is_ts41x()) { 156 if (machine_is_ts41x()) {
157 u32 dev, rev;
158
157 /* 159 /*
158 * Without this explicit reset, the PCIe SATA controller 160 * Without this explicit reset, the PCIe SATA controller
159 * (Marvell 88sx7042/sata_mv) is known to stop working 161 * (Marvell 88sx7042/sata_mv) is known to stop working
@@ -161,7 +163,11 @@ static int __init ts41x_pci_init(void)
161 */ 163 */
162 orion_pcie_reset((void __iomem *)PCIE_VIRT_BASE); 164 orion_pcie_reset((void __iomem *)PCIE_VIRT_BASE);
163 165
164 kirkwood_pcie_init(KW_PCIE0); 166 kirkwood_pcie_id(&dev, &rev);
167 if (dev == MV88F6282_DEV_ID)
168 kirkwood_pcie_init(KW_PCIE1 | KW_PCIE0);
169 else
170 kirkwood_pcie_init(KW_PCIE0);
165 } 171 }
166 172
167 return 0; 173 return 0;
@@ -173,6 +179,7 @@ MACHINE_START(TS41X, "QNAP TS-41x")
173 .boot_params = 0x00000100, 179 .boot_params = 0x00000100,
174 .init_machine = qnap_ts41x_init, 180 .init_machine = qnap_ts41x_init,
175 .map_io = kirkwood_map_io, 181 .map_io = kirkwood_map_io,
182 .init_early = kirkwood_init_early,
176 .init_irq = kirkwood_init_irq, 183 .init_irq = kirkwood_init_irq,
177 .timer = &kirkwood_timer, 184 .timer = &kirkwood_timer,
178MACHINE_END 185MACHINE_END
diff --git a/arch/arm/mach-loki/common.c b/arch/arm/mach-loki/common.c
index 818f19d7ab1f..e41e909cf8f4 100644
--- a/arch/arm/mach-loki/common.c
+++ b/arch/arm/mach-loki/common.c
@@ -18,6 +18,7 @@
18#include <asm/timex.h> 18#include <asm/timex.h>
19#include <asm/mach/map.h> 19#include <asm/mach/map.h>
20#include <asm/mach/time.h> 20#include <asm/mach/time.h>
21#include <mach/bridge-regs.h>
21#include <mach/loki.h> 22#include <mach/loki.h>
22#include <plat/orion_nand.h> 23#include <plat/orion_nand.h>
23#include <plat/time.h> 24#include <plat/time.h>
@@ -290,9 +291,15 @@ void __init loki_uart1_init(void)
290/***************************************************************************** 291/*****************************************************************************
291 * Time handling 292 * Time handling
292 ****************************************************************************/ 293 ****************************************************************************/
294void __init loki_init_early(void)
295{
296 orion_time_set_base(TIMER_VIRT_BASE);
297}
298
293static void loki_timer_init(void) 299static void loki_timer_init(void)
294{ 300{
295 orion_time_init(IRQ_LOKI_BRIDGE, LOKI_TCLK); 301 orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
302 IRQ_LOKI_BRIDGE, LOKI_TCLK);
296} 303}
297 304
298struct sys_timer loki_timer = { 305struct sys_timer loki_timer = {
diff --git a/arch/arm/mach-loki/common.h b/arch/arm/mach-loki/common.h
index 26054fd0f05e..a315dcf8887c 100644
--- a/arch/arm/mach-loki/common.h
+++ b/arch/arm/mach-loki/common.h
@@ -18,6 +18,7 @@ struct mv643xx_eth_platform_data;
18 */ 18 */
19void loki_map_io(void); 19void loki_map_io(void);
20void loki_init(void); 20void loki_init(void);
21void loki_init_early(void);
21void loki_init_irq(void); 22void loki_init_irq(void);
22 23
23extern struct mbus_dram_target_info loki_mbus_dram_info; 24extern struct mbus_dram_target_info loki_mbus_dram_info;
diff --git a/arch/arm/mach-loki/include/mach/bridge-regs.h b/arch/arm/mach-loki/include/mach/bridge-regs.h
index a3fabf70044f..fd87732097cd 100644
--- a/arch/arm/mach-loki/include/mach/bridge-regs.h
+++ b/arch/arm/mach-loki/include/mach/bridge-regs.h
@@ -17,11 +17,6 @@
17#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c) 17#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c)
18#define SOFT_RESET 0x00000001 18#define SOFT_RESET 0x00000001
19 19
20#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110)
21
22#define BRIDGE_MASK (BRIDGE_VIRT_BASE | 0x0114)
23#define BRIDGE_INT_TIMER0 0x0002
24#define BRIDGE_INT_TIMER1 0x0004
25#define BRIDGE_INT_TIMER1_CLR 0x0004 20#define BRIDGE_INT_TIMER1_CLR 0x0004
26 21
27#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200) 22#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200)
diff --git a/arch/arm/mach-loki/lb88rc8480-setup.c b/arch/arm/mach-loki/lb88rc8480-setup.c
index a1e75e7fc500..35eae4e6abb2 100644
--- a/arch/arm/mach-loki/lb88rc8480-setup.c
+++ b/arch/arm/mach-loki/lb88rc8480-setup.c
@@ -93,6 +93,7 @@ MACHINE_START(LB88RC8480, "Marvell LB88RC8480 Development Board")
93 .boot_params = 0x00000100, 93 .boot_params = 0x00000100,
94 .init_machine = lb88rc8480_init, 94 .init_machine = lb88rc8480_init,
95 .map_io = loki_map_io, 95 .map_io = loki_map_io,
96 .init_early = loki_init_early,
96 .init_irq = loki_init_irq, 97 .init_irq = loki_init_irq,
97 .timer = &loki_timer, 98 .timer = &loki_timer,
98MACHINE_END 99MACHINE_END
diff --git a/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c b/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c
index 29e390e89ff4..20f3f125ed2b 100644
--- a/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c
+++ b/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c
@@ -148,6 +148,7 @@ MACHINE_START(TERASTATION_WXL, "Buffalo Nas WXL")
148 .boot_params = 0x00000100, 148 .boot_params = 0x00000100,
149 .init_machine = wxl_init, 149 .init_machine = wxl_init,
150 .map_io = mv78xx0_map_io, 150 .map_io = mv78xx0_map_io,
151 .init_early = mv78xx0_init_early,
151 .init_irq = mv78xx0_init_irq, 152 .init_irq = mv78xx0_init_irq,
152 .timer = &mv78xx0_timer, 153 .timer = &mv78xx0_timer,
153MACHINE_END 154MACHINE_END
diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c
index 08465eb6a2c2..44fb4e55be0d 100644
--- a/arch/arm/mach-mv78xx0/common.c
+++ b/arch/arm/mach-mv78xx0/common.c
@@ -818,9 +818,15 @@ void __init mv78xx0_uart3_init(void)
818/***************************************************************************** 818/*****************************************************************************
819 * Time handling 819 * Time handling
820 ****************************************************************************/ 820 ****************************************************************************/
821void __init mv78xx0_init_early(void)
822{
823 orion_time_set_base(TIMER_VIRT_BASE);
824}
825
821static void mv78xx0_timer_init(void) 826static void mv78xx0_timer_init(void)
822{ 827{
823 orion_time_init(IRQ_MV78XX0_TIMER_1, get_tclk()); 828 orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
829 IRQ_MV78XX0_TIMER_1, get_tclk());
824} 830}
825 831
826struct sys_timer mv78xx0_timer = { 832struct sys_timer mv78xx0_timer = {
diff --git a/arch/arm/mach-mv78xx0/common.h b/arch/arm/mach-mv78xx0/common.h
index befc22475469..632e63d65e7a 100644
--- a/arch/arm/mach-mv78xx0/common.h
+++ b/arch/arm/mach-mv78xx0/common.h
@@ -20,6 +20,7 @@ struct mv_sata_platform_data;
20int mv78xx0_core_index(void); 20int mv78xx0_core_index(void);
21void mv78xx0_map_io(void); 21void mv78xx0_map_io(void);
22void mv78xx0_init(void); 22void mv78xx0_init(void);
23void mv78xx0_init_early(void);
23void mv78xx0_init_irq(void); 24void mv78xx0_init_irq(void);
24 25
25extern struct mbus_dram_target_info mv78xx0_mbus_dram_info; 26extern struct mbus_dram_target_info mv78xx0_mbus_dram_info;
diff --git a/arch/arm/mach-mv78xx0/db78x00-bp-setup.c b/arch/arm/mach-mv78xx0/db78x00-bp-setup.c
index 207c95e403b9..df5aebe5b0fa 100644
--- a/arch/arm/mach-mv78xx0/db78x00-bp-setup.c
+++ b/arch/arm/mach-mv78xx0/db78x00-bp-setup.c
@@ -96,6 +96,7 @@ MACHINE_START(DB78X00_BP, "Marvell DB-78x00-BP Development Board")
96 .boot_params = 0x00000100, 96 .boot_params = 0x00000100,
97 .init_machine = db78x00_init, 97 .init_machine = db78x00_init,
98 .map_io = mv78xx0_map_io, 98 .map_io = mv78xx0_map_io,
99 .init_early = mv78xx0_init_early,
99 .init_irq = mv78xx0_init_irq, 100 .init_irq = mv78xx0_init_irq,
100 .timer = &mv78xx0_timer, 101 .timer = &mv78xx0_timer,
101MACHINE_END 102MACHINE_END
diff --git a/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h b/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h
index 2d14c4fe294d..c64dbb96dbad 100644
--- a/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h
+++ b/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h
@@ -20,10 +20,6 @@
20#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c) 20#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c)
21#define SOFT_RESET 0x00000001 21#define SOFT_RESET 0x00000001
22 22
23#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110)
24#define BRIDGE_MASK (BRIDGE_VIRT_BASE | 0x0114)
25#define BRIDGE_INT_TIMER0 0x0002
26#define BRIDGE_INT_TIMER1 0x0004
27#define BRIDGE_INT_TIMER1_CLR (~0x0004) 23#define BRIDGE_INT_TIMER1_CLR (~0x0004)
28 24
29#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200) 25#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200)
diff --git a/arch/arm/mach-mv78xx0/include/mach/gpio.h b/arch/arm/mach-mv78xx0/include/mach/gpio.h
index d9d1535ea100..77e1b843e768 100644
--- a/arch/arm/mach-mv78xx0/include/mach/gpio.h
+++ b/arch/arm/mach-mv78xx0/include/mach/gpio.h
@@ -6,35 +6,4 @@
6 * warranty of any kind, whether express or implied. 6 * warranty of any kind, whether express or implied.
7 */ 7 */
8 8
9#ifndef __ASM_ARCH_GPIO_H
10#define __ASM_ARCH_GPIO_H
11
12#include <mach/irqs.h>
13#include <plat/gpio.h> 9#include <plat/gpio.h>
14#include <asm-generic/gpio.h> /* cansleep wrappers */
15
16extern int mv78xx0_core_index(void);
17
18#define GPIO_MAX 32
19#define GPIO_OUT(pin) (DEV_BUS_VIRT_BASE + 0x0100)
20#define GPIO_IO_CONF(pin) (DEV_BUS_VIRT_BASE + 0x0104)
21#define GPIO_BLINK_EN(pin) (DEV_BUS_VIRT_BASE + 0x0108)
22#define GPIO_IN_POL(pin) (DEV_BUS_VIRT_BASE + 0x010c)
23#define GPIO_DATA_IN(pin) (DEV_BUS_VIRT_BASE + 0x0110)
24#define GPIO_EDGE_CAUSE(pin) (DEV_BUS_VIRT_BASE + 0x0114)
25#define GPIO_MASK_OFF (mv78xx0_core_index() ? 0x18 : 0)
26#define GPIO_EDGE_MASK(pin) (DEV_BUS_VIRT_BASE + 0x0118 + GPIO_MASK_OFF)
27#define GPIO_LEVEL_MASK(pin) (DEV_BUS_VIRT_BASE + 0x011c + GPIO_MASK_OFF)
28
29static inline int gpio_to_irq(int pin)
30{
31 return pin + IRQ_MV78XX0_GPIO_START;
32}
33
34static inline int irq_to_gpio(int irq)
35{
36 return irq - IRQ_MV78XX0_GPIO_START;
37}
38
39
40#endif
diff --git a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
index 3eff39921d4d..3674497162e3 100644
--- a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
+++ b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
@@ -71,6 +71,7 @@
71#define DEV_BUS_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x10000) 71#define DEV_BUS_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x10000)
72#define SAMPLE_AT_RESET_LOW (DEV_BUS_VIRT_BASE | 0x0030) 72#define SAMPLE_AT_RESET_LOW (DEV_BUS_VIRT_BASE | 0x0030)
73#define SAMPLE_AT_RESET_HIGH (DEV_BUS_VIRT_BASE | 0x0034) 73#define SAMPLE_AT_RESET_HIGH (DEV_BUS_VIRT_BASE | 0x0034)
74#define GPIO_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x0100)
74#define I2C_0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x1000) 75#define I2C_0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x1000)
75#define I2C_1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x1100) 76#define I2C_1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x1100)
76#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2000) 77#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2000)
diff --git a/arch/arm/mach-mv78xx0/irq.c b/arch/arm/mach-mv78xx0/irq.c
index 22b4ff893b3c..08da497c39c2 100644
--- a/arch/arm/mach-mv78xx0/irq.c
+++ b/arch/arm/mach-mv78xx0/irq.c
@@ -26,28 +26,18 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
26 26
27void __init mv78xx0_init_irq(void) 27void __init mv78xx0_init_irq(void)
28{ 28{
29 int i;
30
31 /* Initialize gpiolib. */
32 orion_gpio_init();
33
34 orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF)); 29 orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF));
35 orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF)); 30 orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF));
36 orion_irq_init(64, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_ERR_OFF)); 31 orion_irq_init(64, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_ERR_OFF));
37 32
38 /* 33 /*
39 * Mask and clear GPIO IRQ interrupts. 34 * Initialize gpiolib for GPIOs 0-31. (The GPIO interrupt mask
35 * registers for core #1 are at an offset of 0x18 from those of
36 * core #0.)
40 */ 37 */
41 writel(0, GPIO_LEVEL_MASK(0)); 38 orion_gpio_init(0, 32, GPIO_VIRT_BASE,
42 writel(0, GPIO_EDGE_MASK(0)); 39 mv78xx0_core_index() ? 0x18 : 0,
43 writel(0, GPIO_EDGE_CAUSE(0)); 40 IRQ_MV78XX0_GPIO_START);
44
45 for (i = IRQ_MV78XX0_GPIO_START; i < NR_IRQS; i++) {
46 set_irq_chip(i, &orion_gpio_irq_chip);
47 set_irq_handler(i, handle_level_irq);
48 irq_desc[i].status |= IRQ_LEVEL;
49 set_irq_flags(i, IRQF_VALID);
50 }
51 set_irq_chained_handler(IRQ_MV78XX0_GPIO_0_7, gpio_irq_handler); 41 set_irq_chained_handler(IRQ_MV78XX0_GPIO_0_7, gpio_irq_handler);
52 set_irq_chained_handler(IRQ_MV78XX0_GPIO_8_15, gpio_irq_handler); 42 set_irq_chained_handler(IRQ_MV78XX0_GPIO_8_15, gpio_irq_handler);
53 set_irq_chained_handler(IRQ_MV78XX0_GPIO_16_23, gpio_irq_handler); 43 set_irq_chained_handler(IRQ_MV78XX0_GPIO_16_23, gpio_irq_handler);
diff --git a/arch/arm/mach-mv78xx0/mpp.c b/arch/arm/mach-mv78xx0/mpp.c
index 84db2dfc475c..65b72c454cb0 100644
--- a/arch/arm/mach-mv78xx0/mpp.c
+++ b/arch/arm/mach-mv78xx0/mpp.c
@@ -44,9 +44,6 @@ void __init mv78xx0_mpp_conf(unsigned int *mpp_list)
44 if (!variant_mask) 44 if (!variant_mask)
45 return; 45 return;
46 46
47 /* Initialize gpiolib. */
48 orion_gpio_init();
49
50 printk(KERN_DEBUG "initial MPP regs:"); 47 printk(KERN_DEBUG "initial MPP regs:");
51 for (i = 0; i < MPP_NR_REGS; i++) { 48 for (i = 0; i < MPP_NR_REGS; i++) {
52 mpp_ctrl[i] = readl(MPP_CTRL(i)); 49 mpp_ctrl[i] = readl(MPP_CTRL(i));
diff --git a/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c b/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c
index 3511ad4d973b..d927f14c6810 100644
--- a/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c
+++ b/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c
@@ -81,6 +81,7 @@ MACHINE_START(RD78X00_MASA, "Marvell RD-78x00-MASA Development Board")
81 .boot_params = 0x00000100, 81 .boot_params = 0x00000100,
82 .init_machine = rd78x00_masa_init, 82 .init_machine = rd78x00_masa_init,
83 .map_io = mv78xx0_map_io, 83 .map_io = mv78xx0_map_io,
84 .init_early = mv78xx0_init_early,
84 .init_irq = mv78xx0_init_irq, 85 .init_irq = mv78xx0_init_irq,
85 .timer = &mv78xx0_timer, 86 .timer = &mv78xx0_timer,
86MACHINE_END 87MACHINE_END
diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig
index 0717f887cba0..340809a7d233 100644
--- a/arch/arm/mach-mx3/Kconfig
+++ b/arch/arm/mach-mx3/Kconfig
@@ -94,6 +94,7 @@ config MACH_MX31_3DS
94 select MXC_DEBUG_BOARD 94 select MXC_DEBUG_BOARD
95 select IMX_HAVE_PLATFORM_FSL_USB2_UDC 95 select IMX_HAVE_PLATFORM_FSL_USB2_UDC
96 select IMX_HAVE_PLATFORM_IMX2_WDT 96 select IMX_HAVE_PLATFORM_IMX2_WDT
97 select IMX_HAVE_PLATFORM_IMX_I2C
97 select IMX_HAVE_PLATFORM_IMX_KEYPAD 98 select IMX_HAVE_PLATFORM_IMX_KEYPAD
98 select IMX_HAVE_PLATFORM_IMX_UART 99 select IMX_HAVE_PLATFORM_IMX_UART
99 select IMX_HAVE_PLATFORM_MXC_EHCI 100 select IMX_HAVE_PLATFORM_MXC_EHCI
@@ -183,6 +184,7 @@ config MACH_MX35_3DS
183 select MXC_DEBUG_BOARD 184 select MXC_DEBUG_BOARD
184 select IMX_HAVE_PLATFORM_FSL_USB2_UDC 185 select IMX_HAVE_PLATFORM_FSL_USB2_UDC
185 select IMX_HAVE_PLATFORM_IMX2_WDT 186 select IMX_HAVE_PLATFORM_IMX2_WDT
187 select IMX_HAVE_PLATFORM_IMX_I2C
186 select IMX_HAVE_PLATFORM_IMX_UART 188 select IMX_HAVE_PLATFORM_IMX_UART
187 select IMX_HAVE_PLATFORM_MXC_EHCI 189 select IMX_HAVE_PLATFORM_MXC_EHCI
188 select IMX_HAVE_PLATFORM_MXC_NAND 190 select IMX_HAVE_PLATFORM_MXC_NAND
@@ -199,6 +201,15 @@ config MACH_KZM_ARM11_01
199 Include support for KZM-ARM11-01. This includes specific 201 Include support for KZM-ARM11-01. This includes specific
200 configurations for the board and its peripherals. 202 configurations for the board and its peripherals.
201 203
204config MACH_BUG
205 bool "Support Buglabs BUGBase platform"
206 select SOC_IMX31
207 select IMX_HAVE_PLATFORM_IMX_UART
208 default y
209 help
210 Include support for BUGBase 1.3 platform. This includes specific
211 configurations for the board and its peripherals.
212
202config MACH_EUKREA_CPUIMX35 213config MACH_EUKREA_CPUIMX35
203 bool "Support Eukrea CPUIMX35 Platform" 214 bool "Support Eukrea CPUIMX35 Platform"
204 select SOC_IMX35 215 select SOC_IMX35
@@ -229,4 +240,18 @@ config MACH_EUKREA_MBIMXSD35_BASEBOARD
229 240
230endchoice 241endchoice
231 242
243config MACH_VPR200
244 bool "Support VPR200 platform"
245 select SOC_IMX35
246 select IMX_HAVE_PLATFORM_FSL_USB2_UDC
247 select IMX_HAVE_PLATFORM_IMX2_WDT
248 select IMX_HAVE_PLATFORM_IMX_UART
249 select IMX_HAVE_PLATFORM_IMX_I2C
250 select IMX_HAVE_PLATFORM_MXC_EHCI
251 select IMX_HAVE_PLATFORM_MXC_NAND
252 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
253 help
254 Include support for VPR200 platform. This includes specific
255 configurations for the board and its peripherals.
256
232endif 257endif
diff --git a/arch/arm/mach-mx3/Makefile b/arch/arm/mach-mx3/Makefile
index 8db13294ad27..a54faf2cf5fa 100644
--- a/arch/arm/mach-mx3/Makefile
+++ b/arch/arm/mach-mx3/Makefile
@@ -5,8 +5,8 @@
5# Object file lists. 5# Object file lists.
6 6
7obj-y := mm.o devices.o cpu.o 7obj-y := mm.o devices.o cpu.o
8obj-$(CONFIG_SOC_IMX31) += clock-imx31.o iomux-imx31.o 8obj-$(CONFIG_SOC_IMX31) += clock-imx31.o iomux-imx31.o ehci-imx31.o
9obj-$(CONFIG_SOC_IMX35) += clock-imx35.o 9obj-$(CONFIG_SOC_IMX35) += clock-imx35.o ehci-imx35.o
10obj-$(CONFIG_MACH_MX31ADS) += mach-mx31ads.o 10obj-$(CONFIG_MACH_MX31ADS) += mach-mx31ads.o
11obj-$(CONFIG_MACH_MX31LILLY) += mach-mx31lilly.o mx31lilly-db.o 11obj-$(CONFIG_MACH_MX31LILLY) += mach-mx31lilly.o mx31lilly-db.o
12obj-$(CONFIG_MACH_MX31LITE) += mach-mx31lite.o mx31lite-db.o 12obj-$(CONFIG_MACH_MX31LITE) += mach-mx31lite.o mx31lite-db.o
@@ -20,5 +20,7 @@ obj-$(CONFIG_MACH_PCM043) += mach-pcm043.o
20obj-$(CONFIG_MACH_ARMADILLO5X0) += mach-armadillo5x0.o 20obj-$(CONFIG_MACH_ARMADILLO5X0) += mach-armadillo5x0.o
21obj-$(CONFIG_MACH_MX35_3DS) += mach-mx35_3ds.o 21obj-$(CONFIG_MACH_MX35_3DS) += mach-mx35_3ds.o
22obj-$(CONFIG_MACH_KZM_ARM11_01) += mach-kzm_arm11_01.o 22obj-$(CONFIG_MACH_KZM_ARM11_01) += mach-kzm_arm11_01.o
23obj-$(CONFIG_MACH_BUG) += mach-bug.o
23obj-$(CONFIG_MACH_EUKREA_CPUIMX35) += mach-cpuimx35.o 24obj-$(CONFIG_MACH_EUKREA_CPUIMX35) += mach-cpuimx35.o
24obj-$(CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD) += eukrea_mbimxsd-baseboard.o 25obj-$(CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD) += eukrea_mbimxsd-baseboard.o
26obj-$(CONFIG_MACH_VPR200) += mach-vpr200.o
diff --git a/arch/arm/mach-mx3/devices-imx35.h b/arch/arm/mach-mx3/devices-imx35.h
index 677b18aa7ae6..d545d86cc202 100644
--- a/arch/arm/mach-mx3/devices-imx35.h
+++ b/arch/arm/mach-mx3/devices-imx35.h
@@ -35,7 +35,7 @@ extern const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst;
35#define imx35_add_imx_i2c2(pdata) imx35_add_imx_i2c(2, pdata) 35#define imx35_add_imx_i2c2(pdata) imx35_add_imx_i2c(2, pdata)
36 36
37extern const struct imx_imx_keypad_data imx35_imx_keypad_data __initconst; 37extern const struct imx_imx_keypad_data imx35_imx_keypad_data __initconst;
38#define imx31_add_imx_keypad(pdata) \ 38#define imx35_add_imx_keypad(pdata) \
39 imx_add_imx_keypad(&imx35_imx_keypad_data, pdata) 39 imx_add_imx_keypad(&imx35_imx_keypad_data, pdata)
40 40
41extern const struct imx_imx_ssi_data imx35_imx_ssi_data[] __initconst; 41extern const struct imx_imx_ssi_data imx35_imx_ssi_data[] __initconst;
diff --git a/arch/arm/mach-mx3/ehci-imx31.c b/arch/arm/mach-mx3/ehci-imx31.c
new file mode 100644
index 000000000000..314a983ac614
--- /dev/null
+++ b/arch/arm/mach-mx3/ehci-imx31.c
@@ -0,0 +1,83 @@
1/*
2 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
3 * Copyright (C) 2010 Freescale Semiconductor, Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details.
14 */
15
16#include <linux/platform_device.h>
17#include <linux/io.h>
18
19#include <mach/hardware.h>
20#include <mach/mxc_ehci.h>
21
22#define USBCTRL_OTGBASE_OFFSET 0x600
23
24#define MX31_OTG_SIC_SHIFT 29
25#define MX31_OTG_SIC_MASK (0x3 << MX31_OTG_SIC_SHIFT)
26#define MX31_OTG_PM_BIT (1 << 24)
27
28#define MX31_H2_SIC_SHIFT 21
29#define MX31_H2_SIC_MASK (0x3 << MX31_H2_SIC_SHIFT)
30#define MX31_H2_PM_BIT (1 << 16)
31#define MX31_H2_DT_BIT (1 << 5)
32
33#define MX31_H1_SIC_SHIFT 13
34#define MX31_H1_SIC_MASK (0x3 << MX31_H1_SIC_SHIFT)
35#define MX31_H1_PM_BIT (1 << 8)
36#define MX31_H1_DT_BIT (1 << 4)
37
38int mx31_initialize_usb_hw(int port, unsigned int flags)
39{
40 unsigned int v;
41
42 v = readl(MX31_IO_ADDRESS(MX31_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
43
44 switch (port) {
45 case 0: /* OTG port */
46 v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);
47 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_OTG_SIC_SHIFT;
48
49 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
50 v |= MX31_OTG_PM_BIT;
51
52 break;
53 case 1: /* H1 port */
54 v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT | MX31_H1_DT_BIT);
55 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_H1_SIC_SHIFT;
56
57 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
58 v |= MX31_H1_PM_BIT;
59
60 if (!(flags & MXC_EHCI_TTL_ENABLED))
61 v |= MX31_H1_DT_BIT;
62
63 break;
64 case 2: /* H2 port */
65 v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT | MX31_H2_DT_BIT);
66 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_H2_SIC_SHIFT;
67
68 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
69 v |= MX31_H2_PM_BIT;
70
71 if (!(flags & MXC_EHCI_TTL_ENABLED))
72 v |= MX31_H2_DT_BIT;
73
74 break;
75 default:
76 return -EINVAL;
77 }
78
79 writel(v, MX31_IO_ADDRESS(MX31_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
80
81 return 0;
82}
83
diff --git a/arch/arm/mach-mx3/ehci-imx35.c b/arch/arm/mach-mx3/ehci-imx35.c
new file mode 100644
index 000000000000..33983a478c6b
--- /dev/null
+++ b/arch/arm/mach-mx3/ehci-imx35.c
@@ -0,0 +1,80 @@
1/*
2 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
3 * Copyright (C) 2010 Freescale Semiconductor, Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details.
14 */
15
16#include <linux/platform_device.h>
17#include <linux/io.h>
18
19#include <mach/hardware.h>
20#include <mach/mxc_ehci.h>
21
22#define USBCTRL_OTGBASE_OFFSET 0x600
23
24#define MX35_OTG_SIC_SHIFT 29
25#define MX35_OTG_SIC_MASK (0x3 << MX35_OTG_SIC_SHIFT)
26#define MX35_OTG_PM_BIT (1 << 24)
27
28#define MX35_H1_SIC_SHIFT 21
29#define MX35_H1_SIC_MASK (0x3 << MX35_H1_SIC_SHIFT)
30#define MX35_H1_PM_BIT (1 << 8)
31#define MX35_H1_IPPUE_UP_BIT (1 << 7)
32#define MX35_H1_IPPUE_DOWN_BIT (1 << 6)
33#define MX35_H1_TLL_BIT (1 << 5)
34#define MX35_H1_USBTE_BIT (1 << 4)
35
36int mx35_initialize_usb_hw(int port, unsigned int flags)
37{
38 unsigned int v;
39
40 v = readl(MX35_IO_ADDRESS(MX35_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
41
42 switch (port) {
43 case 0: /* OTG port */
44 v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT);
45 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_OTG_SIC_SHIFT;
46
47 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
48 v |= MX35_OTG_PM_BIT;
49
50 break;
51 case 1: /* H1 port */
52 v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_TLL_BIT |
53 MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT);
54 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_H1_SIC_SHIFT;
55
56 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
57 v |= MX35_H1_PM_BIT;
58
59 if (!(flags & MXC_EHCI_TTL_ENABLED))
60 v |= MX35_H1_TLL_BIT;
61
62 if (flags & MXC_EHCI_INTERNAL_PHY)
63 v |= MX35_H1_USBTE_BIT;
64
65 if (flags & MXC_EHCI_IPPUE_DOWN)
66 v |= MX35_H1_IPPUE_DOWN_BIT;
67
68 if (flags & MXC_EHCI_IPPUE_UP)
69 v |= MX35_H1_IPPUE_UP_BIT;
70
71 break;
72 default:
73 return -EINVAL;
74 }
75
76 writel(v, MX35_IO_ADDRESS(MX35_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
77
78 return 0;
79}
80
diff --git a/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c
index 14a5ffc939ad..80761474c0f8 100644
--- a/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c
+++ b/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c
@@ -165,8 +165,8 @@ static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = {
165 MX35_PAD_SD1_DATA3__ESDHC1_DAT3, 165 MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
166}; 166};
167 167
168#define GPIO_LED1 (2 * 32 + 29) 168#define GPIO_LED1 IMX_GPIO_NR(3, 29)
169#define GPIO_SWITCH1 (2 * 32 + 25) 169#define GPIO_SWITCH1 IMX_GPIO_NR(3, 25)
170#define GPIO_LCDPWR (4) 170#define GPIO_LCDPWR (4)
171 171
172static void eukrea_mbimxsd_lcd_power_set(struct plat_lcd_data *pd, 172static void eukrea_mbimxsd_lcd_power_set(struct plat_lcd_data *pd,
diff --git a/arch/arm/mach-mx3/iomux-imx31.c b/arch/arm/mach-mx3/iomux-imx31.c
index a1d7fa5123dc..cf8f8099ebd7 100644
--- a/arch/arm/mach-mx3/iomux-imx31.c
+++ b/arch/arm/mach-mx3/iomux-imx31.c
@@ -97,7 +97,7 @@ EXPORT_SYMBOL(mxc_iomux_set_pad);
97 * - reserves the pin so that it is not claimed by another driver 97 * - reserves the pin so that it is not claimed by another driver
98 * - setups the iomux according to the configuration 98 * - setups the iomux according to the configuration
99 */ 99 */
100int mxc_iomux_alloc_pin(const unsigned int pin, const char *label) 100int mxc_iomux_alloc_pin(unsigned int pin, const char *label)
101{ 101{
102 unsigned pad = pin & IOMUX_PADNUM_MASK; 102 unsigned pad = pin & IOMUX_PADNUM_MASK;
103 103
@@ -118,10 +118,10 @@ int mxc_iomux_alloc_pin(const unsigned int pin, const char *label)
118} 118}
119EXPORT_SYMBOL(mxc_iomux_alloc_pin); 119EXPORT_SYMBOL(mxc_iomux_alloc_pin);
120 120
121int mxc_iomux_setup_multiple_pins(unsigned int *pin_list, unsigned count, 121int mxc_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count,
122 const char *label) 122 const char *label)
123{ 123{
124 unsigned int *p = pin_list; 124 const unsigned int *p = pin_list;
125 int i; 125 int i;
126 int ret = -EINVAL; 126 int ret = -EINVAL;
127 127
@@ -139,7 +139,7 @@ setup_error:
139} 139}
140EXPORT_SYMBOL(mxc_iomux_setup_multiple_pins); 140EXPORT_SYMBOL(mxc_iomux_setup_multiple_pins);
141 141
142void mxc_iomux_release_pin(const unsigned int pin) 142void mxc_iomux_release_pin(unsigned int pin)
143{ 143{
144 unsigned pad = pin & IOMUX_PADNUM_MASK; 144 unsigned pad = pin & IOMUX_PADNUM_MASK;
145 145
@@ -148,9 +148,9 @@ void mxc_iomux_release_pin(const unsigned int pin)
148} 148}
149EXPORT_SYMBOL(mxc_iomux_release_pin); 149EXPORT_SYMBOL(mxc_iomux_release_pin);
150 150
151void mxc_iomux_release_multiple_pins(unsigned int *pin_list, int count) 151void mxc_iomux_release_multiple_pins(const unsigned int *pin_list, int count)
152{ 152{
153 unsigned int *p = pin_list; 153 const unsigned int *p = pin_list;
154 int i; 154 int i;
155 155
156 for (i = 0; i < count; i++) { 156 for (i = 0; i < count; i++) {
diff --git a/arch/arm/mach-mx3/mach-armadillo5x0.c b/arch/arm/mach-mx3/mach-armadillo5x0.c
index 28b6f414b5d5..226829bf7c25 100644
--- a/arch/arm/mach-mx3/mach-armadillo5x0.c
+++ b/arch/arm/mach-mx3/mach-armadillo5x0.c
@@ -133,7 +133,6 @@ static int armadillo5x0_pins[] = {
133}; 133};
134 134
135/* USB */ 135/* USB */
136#if defined(CONFIG_USB_ULPI)
137 136
138#define OTG_RESET IOMUX_TO_GPIO(MX31_PIN_STXD4) 137#define OTG_RESET IOMUX_TO_GPIO(MX31_PIN_STXD4)
139#define USBH2_RESET IOMUX_TO_GPIO(MX31_PIN_SCK6) 138#define USBH2_RESET IOMUX_TO_GPIO(MX31_PIN_SCK6)
@@ -176,8 +175,10 @@ static int usbotg_init(struct platform_device *pdev)
176 gpio_set_value(OTG_RESET, 0/*LOW*/); 175 gpio_set_value(OTG_RESET, 0/*LOW*/);
177 mdelay(5); 176 mdelay(5);
178 gpio_set_value(OTG_RESET, 1/*HIGH*/); 177 gpio_set_value(OTG_RESET, 1/*HIGH*/);
178 mdelay(10);
179 179
180 return 0; 180 return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED |
181 MXC_EHCI_INTERFACE_DIFF_UNI);
181 182
182otg_free_reset: 183otg_free_reset:
183 gpio_free(OTG_RESET); 184 gpio_free(OTG_RESET);
@@ -233,8 +234,10 @@ static int usbh2_init(struct platform_device *pdev)
233 gpio_set_value(USBH2_RESET, 0/*LOW*/); 234 gpio_set_value(USBH2_RESET, 0/*LOW*/);
234 mdelay(5); 235 mdelay(5);
235 gpio_set_value(USBH2_RESET, 1/*HIGH*/); 236 gpio_set_value(USBH2_RESET, 1/*HIGH*/);
237 mdelay(10);
236 238
237 return 0; 239 return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED |
240 MXC_EHCI_INTERFACE_DIFF_UNI);
238 241
239h2_free_reset: 242h2_free_reset:
240 gpio_free(USBH2_RESET); 243 gpio_free(USBH2_RESET);
@@ -246,15 +249,12 @@ h2_free_cs:
246static struct mxc_usbh_platform_data usbotg_pdata __initdata = { 249static struct mxc_usbh_platform_data usbotg_pdata __initdata = {
247 .init = usbotg_init, 250 .init = usbotg_init,
248 .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, 251 .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
249 .flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_DIFF_UNI,
250}; 252};
251 253
252static struct mxc_usbh_platform_data usbh2_pdata __initdata = { 254static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
253 .init = usbh2_init, 255 .init = usbh2_init,
254 .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, 256 .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
255 .flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_DIFF_UNI,
256}; 257};
257#endif /* CONFIG_USB_ULPI */
258 258
259/* RTC over I2C*/ 259/* RTC over I2C*/
260#define ARMADILLO5X0_RTC_GPIO IOMUX_TO_GPIO(MX31_PIN_SRXD4) 260#define ARMADILLO5X0_RTC_GPIO IOMUX_TO_GPIO(MX31_PIN_SRXD4)
@@ -547,15 +547,15 @@ static void __init armadillo5x0_init(void)
547 i2c_register_board_info(1, &armadillo5x0_i2c_rtc, 1); 547 i2c_register_board_info(1, &armadillo5x0_i2c_rtc, 1);
548 548
549 /* USB */ 549 /* USB */
550#if defined(CONFIG_USB_ULPI) 550
551 usbotg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, 551 usbotg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
552 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); 552 ULPI_OTG_DRVVBUS_EXT);
553 usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, 553 if (usbotg_pdata.otg)
554 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); 554 imx31_add_mxc_ehci_otg(&usbotg_pdata);
555 555 usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
556 imx31_add_mxc_ehci_otg(&usbotg_pdata); 556 ULPI_OTG_DRVVBUS_EXT);
557 imx31_add_mxc_ehci_hs(2, &usbh2_pdata); 557 if (usbh2_pdata.otg)
558#endif 558 imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
559} 559}
560 560
561static void __init armadillo5x0_timer_init(void) 561static void __init armadillo5x0_timer_init(void)
@@ -569,9 +569,10 @@ static struct sys_timer armadillo5x0_timer = {
569 569
570MACHINE_START(ARMADILLO5X0, "Armadillo-500") 570MACHINE_START(ARMADILLO5X0, "Armadillo-500")
571 /* Maintainer: Alberto Panizzo */ 571 /* Maintainer: Alberto Panizzo */
572 .boot_params = MX3x_PHYS_OFFSET + 0x100, 572 .boot_params = MX3x_PHYS_OFFSET + 0x100,
573 .map_io = mx31_map_io, 573 .map_io = mx31_map_io,
574 .init_irq = mx31_init_irq, 574 .init_early = imx31_init_early,
575 .timer = &armadillo5x0_timer, 575 .init_irq = mx31_init_irq,
576 .init_machine = armadillo5x0_init, 576 .timer = &armadillo5x0_timer,
577 .init_machine = armadillo5x0_init,
577MACHINE_END 578MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-bug.c b/arch/arm/mach-mx3/mach-bug.c
new file mode 100644
index 000000000000..d137d7078ee9
--- /dev/null
+++ b/arch/arm/mach-mx3/mach-bug.c
@@ -0,0 +1,66 @@
1/*
2 * Copyright (C) 2000 Deep Blue Solutions Ltd
3 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
4 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
5 * Copyright 2011 Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/platform_device.h>
21
22#include <mach/iomux-mx3.h>
23#include <mach/imx-uart.h>
24#include <mach/hardware.h>
25#include <mach/common.h>
26
27#include <asm/mach/time.h>
28#include <asm/mach/arch.h>
29#include <asm/mach-types.h>
30
31#include "devices-imx31.h"
32
33static const struct imxuart_platform_data uart_pdata __initconst = {
34 .flags = IMXUART_HAVE_RTSCTS,
35};
36
37static const unsigned int bug_pins[] __initconst = {
38 MX31_PIN_PC_RST__CTS5,
39 MX31_PIN_PC_VS2__RTS5,
40 MX31_PIN_PC_BVD2__TXD5,
41 MX31_PIN_PC_BVD1__RXD5,
42};
43
44static void __init bug_board_init(void)
45{
46 mxc_iomux_setup_multiple_pins(bug_pins,
47 ARRAY_SIZE(bug_pins), "uart-4");
48 imx31_add_imx_uart4(&uart_pdata);
49}
50
51static void __init bug_timer_init(void)
52{
53 mx31_clocks_init(26000000);
54}
55
56static struct sys_timer bug_timer = {
57 .init = bug_timer_init,
58};
59
60MACHINE_START(BUG, "BugLabs BUGBase")
61 .map_io = mx31_map_io,
62 .init_early = imx31_init_early,
63 .init_irq = mx31_init_irq,
64 .timer = &bug_timer,
65 .init_machine = bug_board_init,
66MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-cpuimx35.c b/arch/arm/mach-mx3/mach-cpuimx35.c
index 26ae90f02582..ec63d998f647 100644
--- a/arch/arm/mach-mx3/mach-cpuimx35.c
+++ b/arch/arm/mach-mx3/mach-cpuimx35.c
@@ -60,7 +60,7 @@ static struct tsc2007_platform_data tsc2007_info = {
60 .x_plate_ohms = 180, 60 .x_plate_ohms = 180,
61}; 61};
62 62
63#define TSC2007_IRQGPIO (2 * 32 + 2) 63#define TSC2007_IRQGPIO IMX_GPIO_NR(3, 2)
64static struct i2c_board_info eukrea_cpuimx35_i2c_devices[] = { 64static struct i2c_board_info eukrea_cpuimx35_i2c_devices[] = {
65 { 65 {
66 I2C_BOARD_INFO("pcf8563", 0x51), 66 I2C_BOARD_INFO("pcf8563", 0x51),
@@ -111,15 +111,25 @@ static const struct mxc_nand_platform_data
111 .flash_bbt = 1, 111 .flash_bbt = 1,
112}; 112};
113 113
114static int eukrea_cpuimx35_otg_init(struct platform_device *pdev)
115{
116 return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
117}
118
114static const struct mxc_usbh_platform_data otg_pdata __initconst = { 119static const struct mxc_usbh_platform_data otg_pdata __initconst = {
120 .init = eukrea_cpuimx35_otg_init,
115 .portsc = MXC_EHCI_MODE_UTMI, 121 .portsc = MXC_EHCI_MODE_UTMI,
116 .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
117}; 122};
118 123
124static int eukrea_cpuimx35_usbh1_init(struct platform_device *pdev)
125{
126 return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_SINGLE_UNI |
127 MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN);
128}
129
119static const struct mxc_usbh_platform_data usbh1_pdata __initconst = { 130static const struct mxc_usbh_platform_data usbh1_pdata __initconst = {
131 .init = eukrea_cpuimx35_usbh1_init,
120 .portsc = MXC_EHCI_MODE_SERIAL, 132 .portsc = MXC_EHCI_MODE_SERIAL,
121 .flags = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY |
122 MXC_EHCI_IPPUE_DOWN,
123}; 133};
124 134
125static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { 135static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
@@ -146,7 +156,7 @@ __setup("otg_mode=", eukrea_cpuimx35_otg_mode);
146/* 156/*
147 * Board specific initialization. 157 * Board specific initialization.
148 */ 158 */
149static void __init mxc_board_init(void) 159static void __init eukrea_cpuimx35_init(void)
150{ 160{
151 mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx35_pads, 161 mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx35_pads,
152 ARRAY_SIZE(eukrea_cpuimx35_pads)); 162 ARRAY_SIZE(eukrea_cpuimx35_pads));
@@ -184,9 +194,10 @@ struct sys_timer eukrea_cpuimx35_timer = {
184 194
185MACHINE_START(EUKREA_CPUIMX35, "Eukrea CPUIMX35") 195MACHINE_START(EUKREA_CPUIMX35, "Eukrea CPUIMX35")
186 /* Maintainer: Eukrea Electromatique */ 196 /* Maintainer: Eukrea Electromatique */
187 .boot_params = MX3x_PHYS_OFFSET + 0x100, 197 .boot_params = MX3x_PHYS_OFFSET + 0x100,
188 .map_io = mx35_map_io, 198 .map_io = mx35_map_io,
189 .init_irq = mx35_init_irq, 199 .init_early = imx35_init_early,
190 .init_machine = mxc_board_init, 200 .init_irq = mx35_init_irq,
191 .timer = &eukrea_cpuimx35_timer, 201 .timer = &eukrea_cpuimx35_timer,
202 .init_machine = eukrea_cpuimx35_init,
192MACHINE_END 203MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-kzm_arm11_01.c b/arch/arm/mach-mx3/mach-kzm_arm11_01.c
index df1a6ce8e3e1..d35621d62b4d 100644
--- a/arch/arm/mach-mx3/mach-kzm_arm11_01.c
+++ b/arch/arm/mach-mx3/mach-kzm_arm11_01.c
@@ -266,17 +266,14 @@ static void __init kzm_timer_init(void)
266} 266}
267 267
268static struct sys_timer kzm_timer = { 268static struct sys_timer kzm_timer = {
269 .init = kzm_timer_init, 269 .init = kzm_timer_init,
270}; 270};
271 271
272/*
273 * The following uses standard kernel macros define in arch.h in order to
274 * initialize __mach_desc_KZM_ARM11_01 data structure.
275 */
276MACHINE_START(KZM_ARM11_01, "Kyoto Microcomputer Co., Ltd. KZM-ARM11-01") 272MACHINE_START(KZM_ARM11_01, "Kyoto Microcomputer Co., Ltd. KZM-ARM11-01")
277 .boot_params = MX3x_PHYS_OFFSET + 0x100, 273 .boot_params = MX3x_PHYS_OFFSET + 0x100,
278 .map_io = kzm_map_io, 274 .map_io = kzm_map_io,
279 .init_irq = mx31_init_irq, 275 .init_early = imx31_init_early,
280 .init_machine = kzm_board_init, 276 .init_irq = mx31_init_irq,
281 .timer = &kzm_timer, 277 .timer = &kzm_timer,
278 .init_machine = kzm_board_init,
282MACHINE_END 279MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-mx31_3ds.c b/arch/arm/mach-mx3/mach-mx31_3ds.c
index 0d65db885be7..544d3e414f58 100644
--- a/arch/arm/mach-mx3/mach-mx31_3ds.c
+++ b/arch/arm/mach-mx3/mach-mx31_3ds.c
@@ -21,9 +21,13 @@
21#include <linux/platform_device.h> 21#include <linux/platform_device.h>
22#include <linux/mfd/mc13783.h> 22#include <linux/mfd/mc13783.h>
23#include <linux/spi/spi.h> 23#include <linux/spi/spi.h>
24#include <linux/spi/l4f00242t03.h>
24#include <linux/regulator/machine.h> 25#include <linux/regulator/machine.h>
25#include <linux/usb/otg.h> 26#include <linux/usb/otg.h>
26#include <linux/usb/ulpi.h> 27#include <linux/usb/ulpi.h>
28#include <linux/memblock.h>
29
30#include <media/soc_camera.h>
27 31
28#include <mach/hardware.h> 32#include <mach/hardware.h>
29#include <asm/mach-types.h> 33#include <asm/mach-types.h>
@@ -35,6 +39,10 @@
35#include <mach/iomux-mx3.h> 39#include <mach/iomux-mx3.h>
36#include <mach/3ds_debugboard.h> 40#include <mach/3ds_debugboard.h>
37#include <mach/ulpi.h> 41#include <mach/ulpi.h>
42#include <mach/mmc.h>
43#include <mach/ipu.h>
44#include <mach/mx3fb.h>
45#include <mach/mx3_camera.h>
38 46
39#include "devices-imx31.h" 47#include "devices-imx31.h"
40#include "devices.h" 48#include "devices.h"
@@ -42,10 +50,6 @@
42/* CPLD IRQ line for external uart, external ethernet etc */ 50/* CPLD IRQ line for external uart, external ethernet etc */
43#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_1) 51#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_1)
44 52
45/*
46 * This file contains the board-specific initialization routines.
47 */
48
49static int mx31_3ds_pins[] = { 53static int mx31_3ds_pins[] = {
50 /* UART1 */ 54 /* UART1 */
51 MX31_PIN_CTS1__CTS1, 55 MX31_PIN_CTS1__CTS1,
@@ -53,6 +57,12 @@ static int mx31_3ds_pins[] = {
53 MX31_PIN_TXD1__TXD1, 57 MX31_PIN_TXD1__TXD1,
54 MX31_PIN_RXD1__RXD1, 58 MX31_PIN_RXD1__RXD1,
55 IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO), 59 IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO),
60 /*SPI0*/
61 MX31_PIN_CSPI1_SCLK__SCLK,
62 MX31_PIN_CSPI1_MOSI__MOSI,
63 MX31_PIN_CSPI1_MISO__MISO,
64 MX31_PIN_CSPI1_SPI_RDY__SPI_RDY,
65 MX31_PIN_CSPI1_SS2__SS2, /* CS for LCD */
56 /* SPI 1 */ 66 /* SPI 1 */
57 MX31_PIN_CSPI2_SCLK__SCLK, 67 MX31_PIN_CSPI2_SCLK__SCLK,
58 MX31_PIN_CSPI2_MOSI__MOSI, 68 MX31_PIN_CSPI2_MOSI__MOSI,
@@ -100,6 +110,252 @@ static int mx31_3ds_pins[] = {
100 IOMUX_MODE(MX31_PIN_PC_RW_B, IOMUX_CONFIG_ALT1), 110 IOMUX_MODE(MX31_PIN_PC_RW_B, IOMUX_CONFIG_ALT1),
101 /* USB Host2 reset */ 111 /* USB Host2 reset */
102 IOMUX_MODE(MX31_PIN_USB_BYP, IOMUX_CONFIG_GPIO), 112 IOMUX_MODE(MX31_PIN_USB_BYP, IOMUX_CONFIG_GPIO),
113 /* I2C1 */
114 MX31_PIN_I2C_CLK__I2C1_SCL,
115 MX31_PIN_I2C_DAT__I2C1_SDA,
116 /* SDHC1 */
117 MX31_PIN_SD1_DATA3__SD1_DATA3,
118 MX31_PIN_SD1_DATA2__SD1_DATA2,
119 MX31_PIN_SD1_DATA1__SD1_DATA1,
120 MX31_PIN_SD1_DATA0__SD1_DATA0,
121 MX31_PIN_SD1_CLK__SD1_CLK,
122 MX31_PIN_SD1_CMD__SD1_CMD,
123 MX31_PIN_GPIO3_1__GPIO3_1, /* Card detect */
124 MX31_PIN_GPIO3_0__GPIO3_0, /* OE */
125 /* Framebuffer */
126 MX31_PIN_LD0__LD0,
127 MX31_PIN_LD1__LD1,
128 MX31_PIN_LD2__LD2,
129 MX31_PIN_LD3__LD3,
130 MX31_PIN_LD4__LD4,
131 MX31_PIN_LD5__LD5,
132 MX31_PIN_LD6__LD6,
133 MX31_PIN_LD7__LD7,
134 MX31_PIN_LD8__LD8,
135 MX31_PIN_LD9__LD9,
136 MX31_PIN_LD10__LD10,
137 MX31_PIN_LD11__LD11,
138 MX31_PIN_LD12__LD12,
139 MX31_PIN_LD13__LD13,
140 MX31_PIN_LD14__LD14,
141 MX31_PIN_LD15__LD15,
142 MX31_PIN_LD16__LD16,
143 MX31_PIN_LD17__LD17,
144 MX31_PIN_VSYNC3__VSYNC3,
145 MX31_PIN_HSYNC__HSYNC,
146 MX31_PIN_FPSHIFT__FPSHIFT,
147 MX31_PIN_CONTRAST__CONTRAST,
148 /* CSI */
149 MX31_PIN_CSI_D6__CSI_D6,
150 MX31_PIN_CSI_D7__CSI_D7,
151 MX31_PIN_CSI_D8__CSI_D8,
152 MX31_PIN_CSI_D9__CSI_D9,
153 MX31_PIN_CSI_D10__CSI_D10,
154 MX31_PIN_CSI_D11__CSI_D11,
155 MX31_PIN_CSI_D12__CSI_D12,
156 MX31_PIN_CSI_D13__CSI_D13,
157 MX31_PIN_CSI_D14__CSI_D14,
158 MX31_PIN_CSI_D15__CSI_D15,
159 MX31_PIN_CSI_HSYNC__CSI_HSYNC,
160 MX31_PIN_CSI_MCLK__CSI_MCLK,
161 MX31_PIN_CSI_PIXCLK__CSI_PIXCLK,
162 MX31_PIN_CSI_VSYNC__CSI_VSYNC,
163 MX31_PIN_CSI_D5__GPIO3_5, /* CMOS PWDN */
164 IOMUX_MODE(MX31_PIN_RI_DTE1, IOMUX_CONFIG_GPIO), /* CMOS reset */
165};
166
167/*
168 * Camera support
169 */
170static phys_addr_t mx3_camera_base __initdata;
171#define MX31_3DS_CAMERA_BUF_SIZE SZ_8M
172
173#define MX31_3DS_GPIO_CAMERA_PW IOMUX_TO_GPIO(MX31_PIN_CSI_D5)
174#define MX31_3DS_GPIO_CAMERA_RST IOMUX_TO_GPIO(MX31_PIN_RI_DTE1)
175
176static struct gpio mx31_3ds_camera_gpios[] = {
177 { MX31_3DS_GPIO_CAMERA_PW, GPIOF_OUT_INIT_HIGH, "camera-power" },
178 { MX31_3DS_GPIO_CAMERA_RST, GPIOF_OUT_INIT_HIGH, "camera-reset" },
179};
180
181static int __init mx31_3ds_camera_alloc_dma(void)
182{
183 int dma;
184
185 if (!mx3_camera_base)
186 return -ENOMEM;
187
188 dma = dma_declare_coherent_memory(&mx3_camera.dev,
189 mx3_camera_base, mx3_camera_base,
190 MX31_3DS_CAMERA_BUF_SIZE,
191 DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
192
193 if (!(dma & DMA_MEMORY_MAP))
194 return -ENOMEM;
195
196 return 0;
197}
198
199static int mx31_3ds_camera_power(struct device *dev, int on)
200{
201 /* enable or disable the camera */
202 pr_debug("%s: %s the camera\n", __func__, on ? "ENABLE" : "DISABLE");
203 gpio_set_value(MX31_3DS_GPIO_CAMERA_PW, on ? 0 : 1);
204
205 if (!on)
206 goto out;
207
208 /* If enabled, give a reset impulse */
209 gpio_set_value(MX31_3DS_GPIO_CAMERA_RST, 0);
210 msleep(20);
211 gpio_set_value(MX31_3DS_GPIO_CAMERA_RST, 1);
212 msleep(100);
213
214out:
215 return 0;
216}
217
218static struct i2c_board_info mx31_3ds_i2c_camera = {
219 I2C_BOARD_INFO("ov2640", 0x30),
220};
221
222static struct regulator_bulk_data mx31_3ds_camera_regs[] = {
223 { .supply = "cmos_vcore" },
224 { .supply = "cmos_2v8" },
225};
226
227static struct soc_camera_link iclink_ov2640 = {
228 .bus_id = 0,
229 .board_info = &mx31_3ds_i2c_camera,
230 .i2c_adapter_id = 0,
231 .power = mx31_3ds_camera_power,
232 .regulators = mx31_3ds_camera_regs,
233 .num_regulators = ARRAY_SIZE(mx31_3ds_camera_regs),
234};
235
236static struct platform_device mx31_3ds_ov2640 = {
237 .name = "soc-camera-pdrv",
238 .id = 0,
239 .dev = {
240 .platform_data = &iclink_ov2640,
241 },
242};
243
244struct mx3_camera_pdata mx31_3ds_camera_pdata = {
245 .dma_dev = &mx3_ipu.dev,
246 .flags = MX3_CAMERA_DATAWIDTH_10,
247 .mclk_10khz = 2600,
248};
249
250/*
251 * FB support
252 */
253static const struct fb_videomode fb_modedb[] = {
254 { /* 480x640 @ 60 Hz */
255 .name = "Epson-VGA",
256 .refresh = 60,
257 .xres = 480,
258 .yres = 640,
259 .pixclock = 41701,
260 .left_margin = 20,
261 .right_margin = 41,
262 .upper_margin = 10,
263 .lower_margin = 5,
264 .hsync_len = 20,
265 .vsync_len = 10,
266 .sync = FB_SYNC_OE_ACT_HIGH | FB_SYNC_CLK_INVERT,
267 .vmode = FB_VMODE_NONINTERLACED,
268 .flag = 0,
269 },
270};
271
272static struct ipu_platform_data mx3_ipu_data = {
273 .irq_base = MXC_IPU_IRQ_START,
274};
275
276static struct mx3fb_platform_data mx3fb_pdata = {
277 .dma_dev = &mx3_ipu.dev,
278 .name = "Epson-VGA",
279 .mode = fb_modedb,
280 .num_modes = ARRAY_SIZE(fb_modedb),
281};
282
283/* LCD */
284static struct l4f00242t03_pdata mx31_3ds_l4f00242t03_pdata = {
285 .reset_gpio = IOMUX_TO_GPIO(MX31_PIN_LCS1),
286 .data_enable_gpio = IOMUX_TO_GPIO(MX31_PIN_SER_RS),
287 .core_supply = "lcd_2v8",
288 .io_supply = "vdd_lcdio",
289};
290
291/*
292 * Support for SD card slot in personality board
293 */
294#define MX31_3DS_GPIO_SDHC1_CD IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)
295#define MX31_3DS_GPIO_SDHC1_BE IOMUX_TO_GPIO(MX31_PIN_GPIO3_0)
296
297static struct gpio mx31_3ds_sdhc1_gpios[] = {
298 { MX31_3DS_GPIO_SDHC1_CD, GPIOF_IN, "sdhc1-card-detect" },
299 { MX31_3DS_GPIO_SDHC1_BE, GPIOF_OUT_INIT_LOW, "sdhc1-bus-en" },
300};
301
302static int mx31_3ds_sdhc1_init(struct device *dev,
303 irq_handler_t detect_irq,
304 void *data)
305{
306 int ret;
307
308 ret = gpio_request_array(mx31_3ds_sdhc1_gpios,
309 ARRAY_SIZE(mx31_3ds_sdhc1_gpios));
310 if (ret) {
311 pr_warning("Unable to request the SD/MMC GPIOs.\n");
312 return ret;
313 }
314
315 ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO3_1),
316 detect_irq, IRQF_DISABLED |
317 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
318 "sdhc1-detect", data);
319 if (ret) {
320 pr_warning("Unable to request the SD/MMC card-detect IRQ.\n");
321 goto gpio_free;
322 }
323
324 return 0;
325
326gpio_free:
327 gpio_free_array(mx31_3ds_sdhc1_gpios,
328 ARRAY_SIZE(mx31_3ds_sdhc1_gpios));
329 return ret;
330}
331
332static void mx31_3ds_sdhc1_exit(struct device *dev, void *data)
333{
334 free_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO3_1), data);
335 gpio_free_array(mx31_3ds_sdhc1_gpios,
336 ARRAY_SIZE(mx31_3ds_sdhc1_gpios));
337}
338
339static void mx31_3ds_sdhc1_setpower(struct device *dev, unsigned int vdd)
340{
341 /*
342 * While the voltage stuff is done by the driver, activate the
343 * Buffer Enable Pin only if there is a card in slot to fix the card
344 * voltage issue caused by bi-directional chip TXB0108 on 3Stack.
345 * Done here because at this stage we have for sure a debounced value
346 * of the presence of the card, showed by the value of vdd.
347 * 7 == ilog2(MMC_VDD_165_195)
348 */
349 if (vdd > 7)
350 gpio_set_value(MX31_3DS_GPIO_SDHC1_BE, 1);
351 else
352 gpio_set_value(MX31_3DS_GPIO_SDHC1_BE, 0);
353}
354
355static struct imxmmc_platform_data sdhc1_pdata = {
356 .init = mx31_3ds_sdhc1_init,
357 .exit = mx31_3ds_sdhc1_exit,
358 .setpower = mx31_3ds_sdhc1_setpower,
103}; 359};
104 360
105/* 361/*
@@ -138,7 +394,71 @@ static struct regulator_init_data gpo_init = {
138 } 394 }
139}; 395};
140 396
141static struct mc13783_regulator_init_data mx31_3ds_regulators[] = { 397static struct regulator_consumer_supply vmmc2_consumers[] = {
398 REGULATOR_SUPPLY("vmmc", "mxc-mmc.0"),
399};
400
401static struct regulator_init_data vmmc2_init = {
402 .constraints = {
403 .min_uV = 3000000,
404 .max_uV = 3000000,
405 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
406 REGULATOR_CHANGE_STATUS,
407 },
408 .num_consumer_supplies = ARRAY_SIZE(vmmc2_consumers),
409 .consumer_supplies = vmmc2_consumers,
410};
411
412static struct regulator_consumer_supply vmmc1_consumers[] = {
413 REGULATOR_SUPPLY("lcd_2v8", NULL),
414 REGULATOR_SUPPLY("cmos_2v8", "soc-camera-pdrv.0"),
415};
416
417static struct regulator_init_data vmmc1_init = {
418 .constraints = {
419 .min_uV = 2800000,
420 .max_uV = 2800000,
421 .apply_uV = 1,
422 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
423 REGULATOR_CHANGE_STATUS,
424 },
425 .num_consumer_supplies = ARRAY_SIZE(vmmc1_consumers),
426 .consumer_supplies = vmmc1_consumers,
427};
428
429static struct regulator_consumer_supply vgen_consumers[] = {
430 REGULATOR_SUPPLY("vdd_lcdio", NULL),
431};
432
433static struct regulator_init_data vgen_init = {
434 .constraints = {
435 .min_uV = 1800000,
436 .max_uV = 1800000,
437 .apply_uV = 1,
438 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
439 REGULATOR_CHANGE_STATUS,
440 },
441 .num_consumer_supplies = ARRAY_SIZE(vgen_consumers),
442 .consumer_supplies = vgen_consumers,
443};
444
445static struct regulator_consumer_supply vvib_consumers[] = {
446 REGULATOR_SUPPLY("cmos_vcore", "soc-camera-pdrv.0"),
447};
448
449static struct regulator_init_data vvib_init = {
450 .constraints = {
451 .min_uV = 1300000,
452 .max_uV = 1300000,
453 .apply_uV = 1,
454 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
455 REGULATOR_CHANGE_STATUS,
456 },
457 .num_consumer_supplies = ARRAY_SIZE(vvib_consumers),
458 .consumer_supplies = vvib_consumers,
459};
460
461static struct mc13xxx_regulator_init_data mx31_3ds_regulators[] = {
142 { 462 {
143 .id = MC13783_REG_PWGT1SPI, /* Power Gate for ARM core. */ 463 .id = MC13783_REG_PWGT1SPI, /* Power Gate for ARM core. */
144 .init_data = &pwgtx_init, 464 .init_data = &pwgtx_init,
@@ -152,17 +472,38 @@ static struct mc13783_regulator_init_data mx31_3ds_regulators[] = {
152 }, { 472 }, {
153 .id = MC13783_REG_GPO3, /* Turn on 3.3V */ 473 .id = MC13783_REG_GPO3, /* Turn on 3.3V */
154 .init_data = &gpo_init, 474 .init_data = &gpo_init,
475 }, {
476 .id = MC13783_REG_VMMC2, /* Power MMC/SD, WiFi/Bluetooth. */
477 .init_data = &vmmc2_init,
478 }, {
479 .id = MC13783_REG_VMMC1, /* Power LCD, CMOS, FM, GPS, Accel. */
480 .init_data = &vmmc1_init,
481 }, {
482 .id = MC13783_REG_VGEN, /* Power LCD */
483 .init_data = &vgen_init,
484 }, {
485 .id = MC13783_REG_VVIB, /* Power CMOS */
486 .init_data = &vvib_init,
155 }, 487 },
156}; 488};
157 489
158/* MC13783 */ 490/* MC13783 */
159static struct mc13783_platform_data mc13783_pdata __initdata = { 491static struct mc13xxx_platform_data mc13783_pdata __initdata = {
160 .regulators = mx31_3ds_regulators, 492 .regulators = mx31_3ds_regulators,
161 .num_regulators = ARRAY_SIZE(mx31_3ds_regulators), 493 .num_regulators = ARRAY_SIZE(mx31_3ds_regulators),
162 .flags = MC13783_USE_REGULATOR | MC13783_USE_TOUCHSCREEN, 494 .flags = MC13XXX_USE_REGULATOR | MC13XXX_USE_TOUCHSCREEN
163}; 495};
164 496
165/* SPI */ 497/* SPI */
498static int spi0_internal_chipselect[] = {
499 MXC_SPI_CS(2),
500};
501
502static const struct spi_imx_master spi0_pdata __initconst = {
503 .chipselect = spi0_internal_chipselect,
504 .num_chipselect = ARRAY_SIZE(spi0_internal_chipselect),
505};
506
166static int spi1_internal_chipselect[] = { 507static int spi1_internal_chipselect[] = {
167 MXC_SPI_CS(0), 508 MXC_SPI_CS(0),
168 MXC_SPI_CS(2), 509 MXC_SPI_CS(2),
@@ -182,6 +523,12 @@ static struct spi_board_info mx31_3ds_spi_devs[] __initdata = {
182 .platform_data = &mc13783_pdata, 523 .platform_data = &mc13783_pdata,
183 .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3), 524 .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
184 .mode = SPI_CS_HIGH, 525 .mode = SPI_CS_HIGH,
526 }, {
527 .modalias = "l4f00242t03",
528 .max_speed_hz = 5000000,
529 .bus_num = 0,
530 .chip_select = 0, /* SS2 */
531 .platform_data = &mx31_3ds_l4f00242t03_pdata,
185 }, 532 },
186}; 533};
187 534
@@ -245,6 +592,11 @@ usbotg_free_reset:
245 return err; 592 return err;
246} 593}
247 594
595static int mx31_3ds_otg_init(struct platform_device *pdev)
596{
597 return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
598}
599
248static int mx31_3ds_host2_init(struct platform_device *pdev) 600static int mx31_3ds_host2_init(struct platform_device *pdev)
249{ 601{
250 int err; 602 int err;
@@ -276,25 +628,25 @@ static int mx31_3ds_host2_init(struct platform_device *pdev)
276 628
277 mdelay(1); 629 mdelay(1);
278 gpio_set_value(USBH2_RST_B, 1); 630 gpio_set_value(USBH2_RST_B, 1);
279 return 0; 631
632 mdelay(10);
633
634 return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
280 635
281usbotg_free_reset: 636usbotg_free_reset:
282 gpio_free(USBH2_RST_B); 637 gpio_free(USBH2_RST_B);
283 return err; 638 return err;
284} 639}
285 640
286#if defined(CONFIG_USB_ULPI)
287static struct mxc_usbh_platform_data otg_pdata __initdata = { 641static struct mxc_usbh_platform_data otg_pdata __initdata = {
642 .init = mx31_3ds_otg_init,
288 .portsc = MXC_EHCI_MODE_ULPI, 643 .portsc = MXC_EHCI_MODE_ULPI,
289 .flags = MXC_EHCI_POWER_PINS_ENABLED,
290}; 644};
291 645
292static struct mxc_usbh_platform_data usbh2_pdata __initdata = { 646static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
293 .init = mx31_3ds_host2_init, 647 .init = mx31_3ds_host2_init,
294 .portsc = MXC_EHCI_MODE_ULPI, 648 .portsc = MXC_EHCI_MODE_ULPI,
295 .flags = MXC_EHCI_POWER_PINS_ENABLED,
296}; 649};
297#endif
298 650
299static const struct fsl_usb2_platform_data usbotg_pdata __initconst = { 651static const struct fsl_usb2_platform_data usbotg_pdata __initconst = {
300 .operating_mode = FSL_USB2_DR_DEVICE, 652 .operating_mode = FSL_USB2_DR_DEVICE,
@@ -320,19 +672,18 @@ static const struct imxuart_platform_data uart_pdata __initconst = {
320 .flags = IMXUART_HAVE_RTSCTS, 672 .flags = IMXUART_HAVE_RTSCTS,
321}; 673};
322 674
323/* 675static const struct imxi2c_platform_data mx31_3ds_i2c0_data __initconst = {
324 * Set up static virtual mappings. 676 .bitrate = 100000,
325 */ 677};
326static void __init mx31_3ds_map_io(void)
327{
328 mx31_map_io();
329}
330 678
331/*! 679static struct platform_device *devices[] __initdata = {
332 * Board specific initialization. 680 &mx31_3ds_ov2640,
333 */ 681};
334static void __init mxc_board_init(void) 682
683static void __init mx31_3ds_init(void)
335{ 684{
685 int ret;
686
336 mxc_iomux_setup_multiple_pins(mx31_3ds_pins, ARRAY_SIZE(mx31_3ds_pins), 687 mxc_iomux_setup_multiple_pins(mx31_3ds_pins, ARRAY_SIZE(mx31_3ds_pins),
337 "mx31_3ds"); 688 "mx31_3ds");
338 689
@@ -343,20 +694,22 @@ static void __init mxc_board_init(void)
343 spi_register_board_info(mx31_3ds_spi_devs, 694 spi_register_board_info(mx31_3ds_spi_devs,
344 ARRAY_SIZE(mx31_3ds_spi_devs)); 695 ARRAY_SIZE(mx31_3ds_spi_devs));
345 696
697 platform_add_devices(devices, ARRAY_SIZE(devices));
698
346 imx31_add_imx_keypad(&mx31_3ds_keymap_data); 699 imx31_add_imx_keypad(&mx31_3ds_keymap_data);
347 700
348 mx31_3ds_usbotg_init(); 701 mx31_3ds_usbotg_init();
349#if defined(CONFIG_USB_ULPI)
350 if (otg_mode_host) { 702 if (otg_mode_host) {
351 otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, 703 otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
352 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); 704 ULPI_OTG_DRVVBUS_EXT);
353 705 if (otg_pdata.otg)
354 imx31_add_mxc_ehci_otg(&otg_pdata); 706 imx31_add_mxc_ehci_otg(&otg_pdata);
355 } 707 }
356 usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, 708 usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
357 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); 709 ULPI_OTG_DRVVBUS_EXT);
358 imx31_add_mxc_ehci_hs(2, &usbh2_pdata); 710 if (usbh2_pdata.otg)
359#endif 711 imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
712
360 if (!otg_mode_host) 713 if (!otg_mode_host)
361 imx31_add_fsl_usb2_udc(&usbotg_pdata); 714 imx31_add_fsl_usb2_udc(&usbotg_pdata);
362 715
@@ -364,6 +717,26 @@ static void __init mxc_board_init(void)
364 printk(KERN_WARNING "Init of the debug board failed, all " 717 printk(KERN_WARNING "Init of the debug board failed, all "
365 "devices on the debug board are unusable.\n"); 718 "devices on the debug board are unusable.\n");
366 imx31_add_imx2_wdt(NULL); 719 imx31_add_imx2_wdt(NULL);
720 imx31_add_imx_i2c0(&mx31_3ds_i2c0_data);
721 imx31_add_mxc_mmc(0, &sdhc1_pdata);
722
723 imx31_add_spi_imx0(&spi0_pdata);
724 mxc_register_device(&mx3_ipu, &mx3_ipu_data);
725 mxc_register_device(&mx3_fb, &mx3fb_pdata);
726
727 /* CSI */
728 /* Camera power: default - off */
729 ret = gpio_request_array(mx31_3ds_camera_gpios,
730 ARRAY_SIZE(mx31_3ds_camera_gpios));
731 if (ret) {
732 pr_err("Failed to request camera gpios");
733 iclink_ov2640.power = NULL;
734 }
735
736 if (!mx31_3ds_camera_alloc_dma())
737 mxc_register_device(&mx3_camera, &mx31_3ds_camera_pdata);
738 else
739 pr_err("Failed to allocate dma memory for camera");
367} 740}
368 741
369static void __init mx31_3ds_timer_init(void) 742static void __init mx31_3ds_timer_init(void)
@@ -375,15 +748,22 @@ static struct sys_timer mx31_3ds_timer = {
375 .init = mx31_3ds_timer_init, 748 .init = mx31_3ds_timer_init,
376}; 749};
377 750
378/* 751static void __init mx31_3ds_reserve(void)
379 * The following uses standard kernel macros defined in arch.h in order to 752{
380 * initialize __mach_desc_MX31_3DS data structure. 753 /* reserve MX31_3DS_CAMERA_BUF_SIZE bytes for mx3-camera */
381 */ 754 mx3_camera_base = memblock_alloc(MX31_3DS_CAMERA_BUF_SIZE,
755 MX31_3DS_CAMERA_BUF_SIZE);
756 memblock_free(mx3_camera_base, MX31_3DS_CAMERA_BUF_SIZE);
757 memblock_remove(mx3_camera_base, MX31_3DS_CAMERA_BUF_SIZE);
758}
759
382MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)") 760MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)")
383 /* Maintainer: Freescale Semiconductor, Inc. */ 761 /* Maintainer: Freescale Semiconductor, Inc. */
384 .boot_params = MX3x_PHYS_OFFSET + 0x100, 762 .boot_params = MX3x_PHYS_OFFSET + 0x100,
385 .map_io = mx31_3ds_map_io, 763 .map_io = mx31_map_io,
386 .init_irq = mx31_init_irq, 764 .init_early = imx31_init_early,
387 .init_machine = mxc_board_init, 765 .init_irq = mx31_init_irq,
388 .timer = &mx31_3ds_timer, 766 .timer = &mx31_3ds_timer,
767 .init_machine = mx31_3ds_init,
768 .reserve = mx31_3ds_reserve,
389MACHINE_END 769MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-mx31ads.c b/arch/arm/mach-mx3/mach-mx31ads.c
index 88b97d62b57e..4e4b780c481d 100644
--- a/arch/arm/mach-mx3/mach-mx31ads.c
+++ b/arch/arm/mach-mx3/mach-mx31ads.c
@@ -69,12 +69,8 @@
69#define EXPIO_INT_XUART_INTB (MXC_EXP_IO_BASE + 11) 69#define EXPIO_INT_XUART_INTB (MXC_EXP_IO_BASE + 11)
70 70
71#define MXC_MAX_EXP_IO_LINES 16 71#define MXC_MAX_EXP_IO_LINES 16
72/*
73 * This file contains the board-specific initialization routines.
74 */
75 72
76#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) 73/*
77/*!
78 * The serial port definition structure. 74 * The serial port definition structure.
79 */ 75 */
80static struct plat_serial8250_port serial_platform_data[] = { 76static struct plat_serial8250_port serial_platform_data[] = {
@@ -110,14 +106,7 @@ static int __init mxc_init_extuart(void)
110{ 106{
111 return platform_device_register(&serial_device); 107 return platform_device_register(&serial_device);
112} 108}
113#else
114static inline int mxc_init_extuart(void)
115{
116 return 0;
117}
118#endif
119 109
120#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
121static const struct imxuart_platform_data uart_pdata __initconst = { 110static const struct imxuart_platform_data uart_pdata __initconst = {
122 .flags = IMXUART_HAVE_RTSCTS, 111 .flags = IMXUART_HAVE_RTSCTS,
123}; 112};
@@ -134,11 +123,6 @@ static inline void mxc_init_imx_uart(void)
134 mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins), "uart-0"); 123 mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins), "uart-0");
135 imx31_add_imx_uart0(&uart_pdata); 124 imx31_add_imx_uart0(&uart_pdata);
136} 125}
137#else /* !SERIAL_IMX */
138static inline void mxc_init_imx_uart(void)
139{
140}
141#endif /* !SERIAL_IMX */
142 126
143static void mx31ads_expio_irq_handler(u32 irq, struct irq_desc *desc) 127static void mx31ads_expio_irq_handler(u32 irq, struct irq_desc *desc)
144{ 128{
@@ -160,7 +144,7 @@ static void mx31ads_expio_irq_handler(u32 irq, struct irq_desc *desc)
160 144
161/* 145/*
162 * Disable an expio pin's interrupt by setting the bit in the imr. 146 * Disable an expio pin's interrupt by setting the bit in the imr.
163 * @param irq an expio virtual irq number 147 * @param d an expio virtual irq description
164 */ 148 */
165static void expio_mask_irq(struct irq_data *d) 149static void expio_mask_irq(struct irq_data *d)
166{ 150{
@@ -172,7 +156,7 @@ static void expio_mask_irq(struct irq_data *d)
172 156
173/* 157/*
174 * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr. 158 * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr.
175 * @param irq an expanded io virtual irq number 159 * @param d an expio virtual irq description
176 */ 160 */
177static void expio_ack_irq(struct irq_data *d) 161static void expio_ack_irq(struct irq_data *d)
178{ 162{
@@ -183,7 +167,7 @@ static void expio_ack_irq(struct irq_data *d)
183 167
184/* 168/*
185 * Enable a expio pin's interrupt by clearing the bit in the imr. 169 * Enable a expio pin's interrupt by clearing the bit in the imr.
186 * @param irq a expio virtual irq number 170 * @param d an expio virtual irq description
187 */ 171 */
188static void expio_unmask_irq(struct irq_data *d) 172static void expio_unmask_irq(struct irq_data *d)
189{ 173{
@@ -476,7 +460,6 @@ static struct wm8350_platform_data __initdata mx31_wm8350_pdata = {
476}; 460};
477#endif 461#endif
478 462
479#if defined(CONFIG_I2C_IMX) || defined(CONFIG_I2C_IMX_MODULE)
480static struct i2c_board_info __initdata mx31ads_i2c1_devices[] = { 463static struct i2c_board_info __initdata mx31ads_i2c1_devices[] = {
481#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1 464#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
482 { 465 {
@@ -497,11 +480,6 @@ static void mxc_init_i2c(void)
497 480
498 imx31_add_imx_i2c1(NULL); 481 imx31_add_imx_i2c1(NULL);
499} 482}
500#else
501static void mxc_init_i2c(void)
502{
503}
504#endif
505 483
506static unsigned int ssi_pins[] = { 484static unsigned int ssi_pins[] = {
507 MX31_PIN_SFS5__SFS5, 485 MX31_PIN_SFS5__SFS5,
@@ -516,9 +494,7 @@ static void mxc_init_audio(void)
516 mxc_iomux_setup_multiple_pins(ssi_pins, ARRAY_SIZE(ssi_pins), "ssi"); 494 mxc_iomux_setup_multiple_pins(ssi_pins, ARRAY_SIZE(ssi_pins), "ssi");
517} 495}
518 496
519/*! 497/* static mappings */
520 * This structure defines static mappings for the i.MX31ADS board.
521 */
522static struct map_desc mx31ads_io_desc[] __initdata = { 498static struct map_desc mx31ads_io_desc[] __initdata = {
523 { 499 {
524 .virtual = MX31_CS4_BASE_ADDR_VIRT, 500 .virtual = MX31_CS4_BASE_ADDR_VIRT,
@@ -528,9 +504,6 @@ static struct map_desc mx31ads_io_desc[] __initdata = {
528 }, 504 },
529}; 505};
530 506
531/*!
532 * Set up static virtual mappings.
533 */
534static void __init mx31ads_map_io(void) 507static void __init mx31ads_map_io(void)
535{ 508{
536 mx31_map_io(); 509 mx31_map_io();
@@ -543,10 +516,7 @@ static void __init mx31ads_init_irq(void)
543 mx31ads_init_expio(); 516 mx31ads_init_expio();
544} 517}
545 518
546/*! 519static void __init mx31ads_init(void)
547 * Board specific initialization.
548 */
549static void __init mxc_board_init(void)
550{ 520{
551 mxc_init_extuart(); 521 mxc_init_extuart();
552 mxc_init_imx_uart(); 522 mxc_init_imx_uart();
@@ -563,15 +533,12 @@ static struct sys_timer mx31ads_timer = {
563 .init = mx31ads_timer_init, 533 .init = mx31ads_timer_init,
564}; 534};
565 535
566/*
567 * The following uses standard kernel macros defined in arch.h in order to
568 * initialize __mach_desc_MX31ADS data structure.
569 */
570MACHINE_START(MX31ADS, "Freescale MX31ADS") 536MACHINE_START(MX31ADS, "Freescale MX31ADS")
571 /* Maintainer: Freescale Semiconductor, Inc. */ 537 /* Maintainer: Freescale Semiconductor, Inc. */
572 .boot_params = MX3x_PHYS_OFFSET + 0x100, 538 .boot_params = MX3x_PHYS_OFFSET + 0x100,
573 .map_io = mx31ads_map_io, 539 .map_io = mx31ads_map_io,
574 .init_irq = mx31ads_init_irq, 540 .init_early = imx31_init_early,
575 .init_machine = mxc_board_init, 541 .init_irq = mx31ads_init_irq,
576 .timer = &mx31ads_timer, 542 .timer = &mx31ads_timer,
543 .init_machine = mx31ads_init,
577MACHINE_END 544MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-mx31lilly.c b/arch/arm/mach-mx3/mach-mx31lilly.c
index 2c595483f356..ed95745163b8 100644
--- a/arch/arm/mach-mx3/mach-mx31lilly.c
+++ b/arch/arm/mach-mx3/mach-mx31lilly.c
@@ -24,6 +24,7 @@
24#include <linux/init.h> 24#include <linux/init.h>
25#include <linux/clk.h> 25#include <linux/clk.h>
26#include <linux/gpio.h> 26#include <linux/gpio.h>
27#include <linux/delay.h>
27#include <linux/platform_device.h> 28#include <linux/platform_device.h>
28#include <linux/interrupt.h> 29#include <linux/interrupt.h>
29#include <linux/smsc911x.h> 30#include <linux/smsc911x.h>
@@ -110,55 +111,9 @@ static struct platform_device physmap_flash_device = {
110 111
111/* USB */ 112/* USB */
112 113
113#if defined(CONFIG_USB_ULPI)
114
115#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ 114#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
116 PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) 115 PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
117 116
118static int usbotg_init(struct platform_device *pdev)
119{
120 unsigned int pins[] = {
121 MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
122 MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
123 MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
124 MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
125 MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
126 MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
127 MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
128 MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
129 MX31_PIN_USBOTG_CLK__USBOTG_CLK,
130 MX31_PIN_USBOTG_DIR__USBOTG_DIR,
131 MX31_PIN_USBOTG_NXT__USBOTG_NXT,
132 MX31_PIN_USBOTG_STP__USBOTG_STP,
133 };
134
135 mxc_iomux_setup_multiple_pins(pins, ARRAY_SIZE(pins), "USB OTG");
136
137 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG);
138 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG);
139 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG);
140 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG);
141 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG);
142 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG);
143 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG);
144 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG);
145 mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG);
146 mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG);
147 mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG);
148 mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG);
149
150 mxc_iomux_set_gpr(MUX_PGP_USB_4WIRE, true);
151 mxc_iomux_set_gpr(MUX_PGP_USB_COMMON, true);
152
153 /* chip select */
154 mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_DTR_DCE2, IOMUX_CONFIG_GPIO),
155 "USBOTG_CS");
156 gpio_request(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE2), "USBH1 CS");
157 gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE2), 0);
158
159 return 0;
160}
161
162static int usbh1_init(struct platform_device *pdev) 117static int usbh1_init(struct platform_device *pdev)
163{ 118{
164 int pins[] = { 119 int pins[] = {
@@ -183,7 +138,10 @@ static int usbh1_init(struct platform_device *pdev)
183 138
184 mxc_iomux_set_gpr(MUX_PGP_USB_SUSPEND, true); 139 mxc_iomux_set_gpr(MUX_PGP_USB_SUSPEND, true);
185 140
186 return 0; 141 mdelay(10);
142
143 return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED |
144 MXC_EHCI_INTERFACE_SINGLE_UNI);
187} 145}
188 146
189static int usbh2_init(struct platform_device *pdev) 147static int usbh2_init(struct platform_device *pdev)
@@ -220,41 +178,30 @@ static int usbh2_init(struct platform_device *pdev)
220 gpio_request(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), "USBH2 CS"); 178 gpio_request(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), "USBH2 CS");
221 gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), 0); 179 gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), 0);
222 180
223 return 0; 181 mdelay(10);
224}
225 182
226static struct mxc_usbh_platform_data usbotg_pdata = { 183 return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
227 .init = usbotg_init, 184}
228 .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
229 .flags = MXC_EHCI_POWER_PINS_ENABLED,
230};
231 185
232static const struct mxc_usbh_platform_data usbh1_pdata __initconst = { 186static const struct mxc_usbh_platform_data usbh1_pdata __initconst = {
233 .init = usbh1_init, 187 .init = usbh1_init,
234 .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL, 188 .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL,
235 .flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_SINGLE_UNI,
236}; 189};
237 190
238static struct mxc_usbh_platform_data usbh2_pdata __initdata = { 191static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
239 .init = usbh2_init, 192 .init = usbh2_init,
240 .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, 193 .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
241 .flags = MXC_EHCI_POWER_PINS_ENABLED,
242}; 194};
243 195
244static void lilly1131_usb_init(void) 196static void lilly1131_usb_init(void)
245{ 197{
246 usbotg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
247 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
248 usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
249 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
250
251 imx31_add_mxc_ehci_hs(1, &usbh1_pdata); 198 imx31_add_mxc_ehci_hs(1, &usbh1_pdata);
252 imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
253}
254 199
255#else 200 usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
256static inline void lilly1131_usb_init(void) {} 201 ULPI_OTG_DRVVBUS_EXT);
257#endif /* CONFIG_USB_ULPI */ 202 if (usbh2_pdata.otg)
203 imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
204}
258 205
259/* SPI */ 206/* SPI */
260 207
@@ -274,8 +221,8 @@ static const struct spi_imx_master spi1_pdata __initconst = {
274 .num_chipselect = ARRAY_SIZE(spi_internal_chipselect), 221 .num_chipselect = ARRAY_SIZE(spi_internal_chipselect),
275}; 222};
276 223
277static struct mc13783_platform_data mc13783_pdata __initdata = { 224static struct mc13xxx_platform_data mc13783_pdata __initdata = {
278 .flags = MC13783_USE_RTC | MC13783_USE_TOUCHSCREEN, 225 .flags = MC13XXX_USE_RTC | MC13XXX_USE_TOUCHSCREEN,
279}; 226};
280 227
281static struct spi_board_info mc13783_dev __initdata = { 228static struct spi_board_info mc13783_dev __initdata = {
@@ -347,10 +294,10 @@ static struct sys_timer mx31lilly_timer = {
347}; 294};
348 295
349MACHINE_START(LILLY1131, "INCO startec LILLY-1131") 296MACHINE_START(LILLY1131, "INCO startec LILLY-1131")
350 .boot_params = MX3x_PHYS_OFFSET + 0x100, 297 .boot_params = MX3x_PHYS_OFFSET + 0x100,
351 .map_io = mx31_map_io, 298 .map_io = mx31_map_io,
352 .init_irq = mx31_init_irq, 299 .init_early = imx31_init_early,
353 .init_machine = mx31lilly_board_init, 300 .init_irq = mx31_init_irq,
354 .timer = &mx31lilly_timer, 301 .timer = &mx31lilly_timer,
302 .init_machine = mx31lilly_board_init,
355MACHINE_END 303MACHINE_END
356
diff --git a/arch/arm/mach-mx3/mach-mx31lite.c b/arch/arm/mach-mx3/mach-mx31lite.c
index 9e64c66396e0..24a21a384bf1 100644
--- a/arch/arm/mach-mx3/mach-mx31lite.c
+++ b/arch/arm/mach-mx3/mach-mx31lite.c
@@ -27,6 +27,7 @@
27#include <linux/usb/otg.h> 27#include <linux/usb/otg.h>
28#include <linux/usb/ulpi.h> 28#include <linux/usb/ulpi.h>
29#include <linux/mtd/physmap.h> 29#include <linux/mtd/physmap.h>
30#include <linux/delay.h>
30 31
31#include <asm/mach-types.h> 32#include <asm/mach-types.h>
32#include <asm/mach/arch.h> 33#include <asm/mach/arch.h>
@@ -111,9 +112,9 @@ static const struct spi_imx_master spi1_pdata __initconst = {
111 .num_chipselect = ARRAY_SIZE(spi_internal_chipselect), 112 .num_chipselect = ARRAY_SIZE(spi_internal_chipselect),
112}; 113};
113 114
114static struct mc13783_platform_data mc13783_pdata __initdata = { 115static struct mc13xxx_platform_data mc13783_pdata __initdata = {
115 .flags = MC13783_USE_RTC | 116 .flags = MC13XXX_USE_RTC |
116 MC13783_USE_REGULATOR, 117 MC13XXX_USE_REGULATOR,
117}; 118};
118 119
119static struct spi_board_info mc13783_spi_dev __initdata = { 120static struct spi_board_info mc13783_spi_dev __initdata = {
@@ -129,7 +130,6 @@ static struct spi_board_info mc13783_spi_dev __initdata = {
129 * USB 130 * USB
130 */ 131 */
131 132
132#if defined(CONFIG_USB_ULPI)
133#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ 133#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
134 PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) 134 PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
135 135
@@ -167,15 +167,15 @@ static int usbh2_init(struct platform_device *pdev)
167 gpio_request(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), "USBH2 CS"); 167 gpio_request(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), "USBH2 CS");
168 gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), 0); 168 gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), 0);
169 169
170 return 0; 170 mdelay(10);
171
172 return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
171} 173}
172 174
173static struct mxc_usbh_platform_data usbh2_pdata __initdata = { 175static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
174 .init = usbh2_init, 176 .init = usbh2_init,
175 .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, 177 .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
176 .flags = MXC_EHCI_POWER_PINS_ENABLED,
177}; 178};
178#endif
179 179
180/* 180/*
181 * NOR flash 181 * NOR flash
@@ -227,7 +227,7 @@ void __init mx31lite_map_io(void)
227static int mx31lite_baseboard; 227static int mx31lite_baseboard;
228core_param(mx31lite_baseboard, mx31lite_baseboard, int, 0444); 228core_param(mx31lite_baseboard, mx31lite_baseboard, int, 0444);
229 229
230static void __init mxc_board_init(void) 230static void __init mx31lite_init(void)
231{ 231{
232 int ret; 232 int ret;
233 233
@@ -252,13 +252,11 @@ static void __init mxc_board_init(void)
252 imx31_add_spi_imx1(&spi1_pdata); 252 imx31_add_spi_imx1(&spi1_pdata);
253 spi_register_board_info(&mc13783_spi_dev, 1); 253 spi_register_board_info(&mc13783_spi_dev, 1);
254 254
255#if defined(CONFIG_USB_ULPI)
256 /* USB */ 255 /* USB */
257 usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, 256 usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
258 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); 257 ULPI_OTG_DRVVBUS_EXT);
259 258 if (usbh2_pdata.otg)
260 imx31_add_mxc_ehci_hs(2, &usbh2_pdata); 259 imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
261#endif
262 260
263 /* SMSC9117 IRQ pin */ 261 /* SMSC9117 IRQ pin */
264 ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_SFS6), "sms9117-irq"); 262 ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_SFS6), "sms9117-irq");
@@ -281,9 +279,10 @@ struct sys_timer mx31lite_timer = {
281 279
282MACHINE_START(MX31LITE, "LogicPD i.MX31 SOM") 280MACHINE_START(MX31LITE, "LogicPD i.MX31 SOM")
283 /* Maintainer: Freescale Semiconductor, Inc. */ 281 /* Maintainer: Freescale Semiconductor, Inc. */
284 .boot_params = MX3x_PHYS_OFFSET + 0x100, 282 .boot_params = MX3x_PHYS_OFFSET + 0x100,
285 .map_io = mx31lite_map_io, 283 .map_io = mx31lite_map_io,
286 .init_irq = mx31_init_irq, 284 .init_early = imx31_init_early,
287 .init_machine = mxc_board_init, 285 .init_irq = mx31_init_irq,
288 .timer = &mx31lite_timer, 286 .timer = &mx31lite_timer,
287 .init_machine = mx31lite_init,
289MACHINE_END 288MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-mx31moboard.c b/arch/arm/mach-mx3/mach-mx31moboard.c
index 1aa8d65fccbb..6f3692bccb8a 100644
--- a/arch/arm/mach-mx3/mach-mx31moboard.c
+++ b/arch/arm/mach-mx3/mach-mx31moboard.c
@@ -214,7 +214,7 @@ static struct regulator_init_data cam_vreg_data = {
214 .consumer_supplies = cam_consumers, 214 .consumer_supplies = cam_consumers,
215}; 215};
216 216
217static struct mc13783_regulator_init_data moboard_regulators[] = { 217static struct mc13xxx_regulator_init_data moboard_regulators[] = {
218 { 218 {
219 .id = MC13783_REG_VMMC1, 219 .id = MC13783_REG_VMMC1,
220 .init_data = &sdhc_vreg_data, 220 .init_data = &sdhc_vreg_data,
@@ -267,12 +267,12 @@ static struct mc13783_leds_platform_data moboard_leds = {
267 .tc2_period = MC13783_LED_PERIOD_10MS, 267 .tc2_period = MC13783_LED_PERIOD_10MS,
268}; 268};
269 269
270static struct mc13783_platform_data moboard_pmic = { 270static struct mc13xxx_platform_data moboard_pmic = {
271 .regulators = moboard_regulators, 271 .regulators = moboard_regulators,
272 .num_regulators = ARRAY_SIZE(moboard_regulators), 272 .num_regulators = ARRAY_SIZE(moboard_regulators),
273 .leds = &moboard_leds, 273 .leds = &moboard_leds,
274 .flags = MC13783_USE_REGULATOR | MC13783_USE_RTC | 274 .flags = MC13XXX_USE_REGULATOR | MC13XXX_USE_RTC |
275 MC13783_USE_ADC | MC13783_USE_LED, 275 MC13XXX_USE_ADC | MC13XXX_USE_LED,
276}; 276};
277 277
278static struct spi_board_info moboard_spi_board_info[] __initdata = { 278static struct spi_board_info moboard_spi_board_info[] __initdata = {
@@ -400,19 +400,24 @@ static void usb_xcvr_reset(void)
400 mdelay(1); 400 mdelay(1);
401} 401}
402 402
403#if defined(CONFIG_USB_ULPI) 403static int moboard_usbh2_init_hw(struct platform_device *pdev)
404{
405 return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
406}
404 407
405static struct mxc_usbh_platform_data usbh2_pdata __initdata = { 408static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
409 .init = moboard_usbh2_init_hw,
406 .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, 410 .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
407 .flags = MXC_EHCI_POWER_PINS_ENABLED,
408}; 411};
409 412
410static int __init moboard_usbh2_init(void) 413static int __init moboard_usbh2_init(void)
411{ 414{
412 struct platform_device *pdev; 415 struct platform_device *pdev;
413 416
414 usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, 417 usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
415 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); 418 ULPI_OTG_DRVVBUS_EXT);
419 if (!usbh2_pdata.otg)
420 return -ENODEV;
416 421
417 pdev = imx31_add_mxc_ehci_hs(2, &usbh2_pdata); 422 pdev = imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
418 if (IS_ERR(pdev)) 423 if (IS_ERR(pdev))
@@ -420,10 +425,6 @@ static int __init moboard_usbh2_init(void)
420 425
421 return 0; 426 return 0;
422} 427}
423#else
424static inline int moboard_usbh2_init(void) { return 0; }
425#endif
426
427 428
428static struct gpio_led mx31moboard_leds[] = { 429static struct gpio_led mx31moboard_leds[] = {
429 { 430 {
@@ -503,7 +504,7 @@ core_param(mx31moboard_baseboard, mx31moboard_baseboard, int, 0444);
503/* 504/*
504 * Board specific initialization. 505 * Board specific initialization.
505 */ 506 */
506static void __init mxc_board_init(void) 507static void __init mx31moboard_init(void)
507{ 508{
508 mxc_iomux_setup_multiple_pins(moboard_pins, ARRAY_SIZE(moboard_pins), 509 mxc_iomux_setup_multiple_pins(moboard_pins, ARRAY_SIZE(moboard_pins),
509 "moboard"); 510 "moboard");
@@ -564,10 +565,10 @@ struct sys_timer mx31moboard_timer = {
564 565
565MACHINE_START(MX31MOBOARD, "EPFL Mobots mx31moboard") 566MACHINE_START(MX31MOBOARD, "EPFL Mobots mx31moboard")
566 /* Maintainer: Valentin Longchamp, EPFL Mobots group */ 567 /* Maintainer: Valentin Longchamp, EPFL Mobots group */
567 .boot_params = MX3x_PHYS_OFFSET + 0x100, 568 .boot_params = MX3x_PHYS_OFFSET + 0x100,
568 .map_io = mx31_map_io, 569 .map_io = mx31_map_io,
569 .init_irq = mx31_init_irq, 570 .init_early = imx31_init_early,
570 .init_machine = mxc_board_init, 571 .init_irq = mx31_init_irq,
571 .timer = &mx31moboard_timer, 572 .timer = &mx31moboard_timer,
573 .init_machine = mx31moboard_init,
572MACHINE_END 574MACHINE_END
573
diff --git a/arch/arm/mach-mx3/mach-mx35_3ds.c b/arch/arm/mach-mx3/mach-mx35_3ds.c
index b1963f257c20..ff5fe231b8d6 100644
--- a/arch/arm/mach-mx3/mach-mx35_3ds.c
+++ b/arch/arm/mach-mx3/mach-mx35_3ds.c
@@ -118,24 +118,42 @@ static iomux_v3_cfg_t mx35pdk_pads[] = {
118 MX35_PAD_SD1_DATA1__ESDHC1_DAT1, 118 MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
119 MX35_PAD_SD1_DATA2__ESDHC1_DAT2, 119 MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
120 MX35_PAD_SD1_DATA3__ESDHC1_DAT3, 120 MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
121 /* I2C1 */
122 MX35_PAD_I2C1_CLK__I2C1_SCL,
123 MX35_PAD_I2C1_DAT__I2C1_SDA,
121}; 124};
122 125
126static int mx35_3ds_otg_init(struct platform_device *pdev)
127{
128 return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERNAL_PHY);
129}
130
123/* OTG config */ 131/* OTG config */
124static const struct fsl_usb2_platform_data usb_otg_pdata __initconst = { 132static const struct fsl_usb2_platform_data usb_otg_pdata __initconst = {
125 .operating_mode = FSL_USB2_DR_DEVICE, 133 .operating_mode = FSL_USB2_DR_DEVICE,
126 .phy_mode = FSL_USB2_PHY_UTMI_WIDE, 134 .phy_mode = FSL_USB2_PHY_UTMI_WIDE,
135 .workaround = FLS_USB2_WORKAROUND_ENGCM09152,
136/*
137 * ENGCM09152 also requires a hardware change.
138 * Please check the MX35 Chip Errata document for details.
139 */
127}; 140};
128 141
129static struct mxc_usbh_platform_data otg_pdata __initdata = { 142static struct mxc_usbh_platform_data otg_pdata __initdata = {
143 .init = mx35_3ds_otg_init,
130 .portsc = MXC_EHCI_MODE_UTMI, 144 .portsc = MXC_EHCI_MODE_UTMI,
131 .flags = MXC_EHCI_INTERNAL_PHY,
132}; 145};
133 146
147static int mx35_3ds_usbh_init(struct platform_device *pdev)
148{
149 return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_SINGLE_UNI |
150 MXC_EHCI_INTERNAL_PHY);
151}
152
134/* USB HOST config */ 153/* USB HOST config */
135static const struct mxc_usbh_platform_data usb_host_pdata __initconst = { 154static const struct mxc_usbh_platform_data usb_host_pdata __initconst = {
155 .init = mx35_3ds_usbh_init,
136 .portsc = MXC_EHCI_MODE_SERIAL, 156 .portsc = MXC_EHCI_MODE_SERIAL,
137 .flags = MXC_EHCI_INTERFACE_SINGLE_UNI |
138 MXC_EHCI_INTERNAL_PHY,
139}; 157};
140 158
141static int otg_mode_host; 159static int otg_mode_host;
@@ -153,10 +171,14 @@ static int __init mx35_3ds_otg_mode(char *options)
153} 171}
154__setup("otg_mode=", mx35_3ds_otg_mode); 172__setup("otg_mode=", mx35_3ds_otg_mode);
155 173
174static const struct imxi2c_platform_data mx35_3ds_i2c0_data __initconst = {
175 .bitrate = 100000,
176};
177
156/* 178/*
157 * Board specific initialization. 179 * Board specific initialization.
158 */ 180 */
159static void __init mxc_board_init(void) 181static void __init mx35_3ds_init(void)
160{ 182{
161 mxc_iomux_v3_setup_multiple_pads(mx35pdk_pads, ARRAY_SIZE(mx35pdk_pads)); 183 mxc_iomux_v3_setup_multiple_pads(mx35pdk_pads, ARRAY_SIZE(mx35pdk_pads));
162 184
@@ -180,6 +202,7 @@ static void __init mxc_board_init(void)
180 if (mxc_expio_init(MX35_CS5_BASE_ADDR, EXPIO_PARENT_INT)) 202 if (mxc_expio_init(MX35_CS5_BASE_ADDR, EXPIO_PARENT_INT))
181 pr_warn("Init of the debugboard failed, all " 203 pr_warn("Init of the debugboard failed, all "
182 "devices on the debugboard are unusable.\n"); 204 "devices on the debugboard are unusable.\n");
205 imx35_add_imx_i2c0(&mx35_3ds_i2c0_data);
183} 206}
184 207
185static void __init mx35pdk_timer_init(void) 208static void __init mx35pdk_timer_init(void)
@@ -193,9 +216,10 @@ struct sys_timer mx35pdk_timer = {
193 216
194MACHINE_START(MX35_3DS, "Freescale MX35PDK") 217MACHINE_START(MX35_3DS, "Freescale MX35PDK")
195 /* Maintainer: Freescale Semiconductor, Inc */ 218 /* Maintainer: Freescale Semiconductor, Inc */
196 .boot_params = MX3x_PHYS_OFFSET + 0x100, 219 .boot_params = MX3x_PHYS_OFFSET + 0x100,
197 .map_io = mx35_map_io, 220 .map_io = mx35_map_io,
198 .init_irq = mx35_init_irq, 221 .init_early = imx35_init_early,
199 .init_machine = mxc_board_init, 222 .init_irq = mx35_init_irq,
200 .timer = &mx35pdk_timer, 223 .timer = &mx35pdk_timer,
224 .init_machine = mx35_3ds_init,
201MACHINE_END 225MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-pcm037.c b/arch/arm/mach-mx3/mach-pcm037.c
index b752f6bc20a2..f07d3bded674 100644
--- a/arch/arm/mach-mx3/mach-pcm037.c
+++ b/arch/arm/mach-mx3/mach-pcm037.c
@@ -533,17 +533,25 @@ static struct platform_device pcm970_sja1000 = {
533 .num_resources = ARRAY_SIZE(pcm970_sja1000_resources), 533 .num_resources = ARRAY_SIZE(pcm970_sja1000_resources),
534}; 534};
535 535
536#if defined(CONFIG_USB_ULPI) 536static int pcm037_otg_init(struct platform_device *pdev)
537{
538 return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
539}
540
537static struct mxc_usbh_platform_data otg_pdata __initdata = { 541static struct mxc_usbh_platform_data otg_pdata __initdata = {
542 .init = pcm037_otg_init,
538 .portsc = MXC_EHCI_MODE_ULPI, 543 .portsc = MXC_EHCI_MODE_ULPI,
539 .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
540}; 544};
541 545
546static int pcm037_usbh2_init(struct platform_device *pdev)
547{
548 return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
549}
550
542static struct mxc_usbh_platform_data usbh2_pdata __initdata = { 551static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
552 .init = pcm037_usbh2_init,
543 .portsc = MXC_EHCI_MODE_ULPI, 553 .portsc = MXC_EHCI_MODE_ULPI,
544 .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
545}; 554};
546#endif
547 555
548static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { 556static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
549 .operating_mode = FSL_USB2_DR_DEVICE, 557 .operating_mode = FSL_USB2_DR_DEVICE,
@@ -568,7 +576,7 @@ __setup("otg_mode=", pcm037_otg_mode);
568/* 576/*
569 * Board specific initialization. 577 * Board specific initialization.
570 */ 578 */
571static void __init mxc_board_init(void) 579static void __init pcm037_init(void)
572{ 580{
573 int ret; 581 int ret;
574 582
@@ -646,19 +654,18 @@ static void __init mxc_board_init(void)
646 654
647 platform_device_register(&pcm970_sja1000); 655 platform_device_register(&pcm970_sja1000);
648 656
649#if defined(CONFIG_USB_ULPI)
650 if (otg_mode_host) { 657 if (otg_mode_host) {
651 otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, 658 otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
652 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); 659 ULPI_OTG_DRVVBUS_EXT);
653 660 if (otg_pdata.otg)
654 imx31_add_mxc_ehci_otg(&otg_pdata); 661 imx31_add_mxc_ehci_otg(&otg_pdata);
655 } 662 }
656 663
657 usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, 664 usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
658 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); 665 ULPI_OTG_DRVVBUS_EXT);
666 if (usbh2_pdata.otg)
667 imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
659 668
660 imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
661#endif
662 if (!otg_mode_host) 669 if (!otg_mode_host)
663 imx31_add_fsl_usb2_udc(&otg_device_pdata); 670 imx31_add_fsl_usb2_udc(&otg_device_pdata);
664 671
@@ -675,9 +682,10 @@ struct sys_timer pcm037_timer = {
675 682
676MACHINE_START(PCM037, "Phytec Phycore pcm037") 683MACHINE_START(PCM037, "Phytec Phycore pcm037")
677 /* Maintainer: Pengutronix */ 684 /* Maintainer: Pengutronix */
678 .boot_params = MX3x_PHYS_OFFSET + 0x100, 685 .boot_params = MX3x_PHYS_OFFSET + 0x100,
679 .map_io = mx31_map_io, 686 .map_io = mx31_map_io,
680 .init_irq = mx31_init_irq, 687 .init_early = imx31_init_early,
681 .init_machine = mxc_board_init, 688 .init_irq = mx31_init_irq,
682 .timer = &pcm037_timer, 689 .timer = &pcm037_timer,
690 .init_machine = pcm037_init,
683MACHINE_END 691MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-pcm037_eet.c b/arch/arm/mach-mx3/mach-pcm037_eet.c
index fda56545d2fd..df6fb07d037e 100644
--- a/arch/arm/mach-mx3/mach-pcm037_eet.c
+++ b/arch/arm/mach-mx3/mach-pcm037_eet.c
@@ -180,9 +180,7 @@ static int __init eet_init_devices(void)
180 180
181 /* SPI */ 181 /* SPI */
182 spi_register_board_info(pcm037_spi_dev, ARRAY_SIZE(pcm037_spi_dev)); 182 spi_register_board_info(pcm037_spi_dev, ARRAY_SIZE(pcm037_spi_dev));
183#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
184 imx31_add_spi_imx0(&pcm037_spi1_pdata); 183 imx31_add_spi_imx0(&pcm037_spi1_pdata);
185#endif
186 184
187 platform_device_register(&pcm037_gpio_keys_device); 185 platform_device_register(&pcm037_gpio_keys_device);
188 186
diff --git a/arch/arm/mach-mx3/mach-pcm043.c b/arch/arm/mach-mx3/mach-pcm043.c
index bcf83fc7e701..b3ecfb22d241 100644
--- a/arch/arm/mach-mx3/mach-pcm043.c
+++ b/arch/arm/mach-mx3/mach-pcm043.c
@@ -115,7 +115,6 @@ static const struct imxuart_platform_data uart_pdata __initconst = {
115 .flags = IMXUART_HAVE_RTSCTS, 115 .flags = IMXUART_HAVE_RTSCTS,
116}; 116};
117 117
118#if defined CONFIG_I2C_IMX || defined CONFIG_I2C_IMX_MODULE
119static const struct imxi2c_platform_data pcm043_i2c0_data __initconst = { 118static const struct imxi2c_platform_data pcm043_i2c0_data __initconst = {
120 .bitrate = 50000, 119 .bitrate = 50000,
121}; 120};
@@ -134,7 +133,6 @@ static struct i2c_board_info pcm043_i2c_devices[] = {
134 I2C_BOARD_INFO("pcf8563", 0x51), 133 I2C_BOARD_INFO("pcf8563", 0x51),
135 } 134 }
136}; 135};
137#endif
138 136
139static struct platform_device *devices[] __initdata = { 137static struct platform_device *devices[] __initdata = {
140 &pcm043_flash, 138 &pcm043_flash,
@@ -221,9 +219,9 @@ static iomux_v3_cfg_t pcm043_pads[] = {
221 MX35_PAD_SD1_DATA3__ESDHC1_DAT3, 219 MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
222}; 220};
223 221
224#define AC97_GPIO_TXFS (1 * 32 + 31) 222#define AC97_GPIO_TXFS IMX_GPIO_NR(2, 31)
225#define AC97_GPIO_TXD (1 * 32 + 28) 223#define AC97_GPIO_TXD IMX_GPIO_NR(2, 28)
226#define AC97_GPIO_RESET (1 * 32 + 0) 224#define AC97_GPIO_RESET IMX_GPIO_NR(2, 0)
227 225
228static void pcm043_ac97_warm_reset(struct snd_ac97 *ac97) 226static void pcm043_ac97_warm_reset(struct snd_ac97 *ac97)
229{ 227{
@@ -307,18 +305,26 @@ pcm037_nand_board_info __initconst = {
307 .hw_ecc = 1, 305 .hw_ecc = 1,
308}; 306};
309 307
310#if defined(CONFIG_USB_ULPI) 308static int pcm043_otg_init(struct platform_device *pdev)
309{
310 return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
311}
312
311static struct mxc_usbh_platform_data otg_pdata __initdata = { 313static struct mxc_usbh_platform_data otg_pdata __initdata = {
314 .init = pcm043_otg_init,
312 .portsc = MXC_EHCI_MODE_UTMI, 315 .portsc = MXC_EHCI_MODE_UTMI,
313 .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
314}; 316};
315 317
318static int pcm043_usbh1_init(struct platform_device *pdev)
319{
320 return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_SINGLE_UNI |
321 MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN);
322}
323
316static const struct mxc_usbh_platform_data usbh1_pdata __initconst = { 324static const struct mxc_usbh_platform_data usbh1_pdata __initconst = {
325 .init = pcm043_usbh1_init,
317 .portsc = MXC_EHCI_MODE_SERIAL, 326 .portsc = MXC_EHCI_MODE_SERIAL,
318 .flags = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY |
319 MXC_EHCI_IPPUE_DOWN,
320}; 327};
321#endif
322 328
323static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { 329static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
324 .operating_mode = FSL_USB2_DR_DEVICE, 330 .operating_mode = FSL_USB2_DR_DEVICE,
@@ -343,7 +349,7 @@ __setup("otg_mode=", pcm043_otg_mode);
343/* 349/*
344 * Board specific initialization. 350 * Board specific initialization.
345 */ 351 */
346static void __init mxc_board_init(void) 352static void __init pcm043_init(void)
347{ 353{
348 mxc_iomux_v3_setup_multiple_pads(pcm043_pads, ARRAY_SIZE(pcm043_pads)); 354 mxc_iomux_v3_setup_multiple_pads(pcm043_pads, ARRAY_SIZE(pcm043_pads));
349 355
@@ -369,26 +375,22 @@ static void __init mxc_board_init(void)
369 375
370 imx35_add_imx_uart1(&uart_pdata); 376 imx35_add_imx_uart1(&uart_pdata);
371 377
372#if defined CONFIG_I2C_IMX || defined CONFIG_I2C_IMX_MODULE
373 i2c_register_board_info(0, pcm043_i2c_devices, 378 i2c_register_board_info(0, pcm043_i2c_devices,
374 ARRAY_SIZE(pcm043_i2c_devices)); 379 ARRAY_SIZE(pcm043_i2c_devices));
375 380
376 imx35_add_imx_i2c0(&pcm043_i2c0_data); 381 imx35_add_imx_i2c0(&pcm043_i2c0_data);
377#endif
378 382
379 mxc_register_device(&mx3_ipu, &mx3_ipu_data); 383 mxc_register_device(&mx3_ipu, &mx3_ipu_data);
380 mxc_register_device(&mx3_fb, &mx3fb_pdata); 384 mxc_register_device(&mx3_fb, &mx3fb_pdata);
381 385
382#if defined(CONFIG_USB_ULPI)
383 if (otg_mode_host) { 386 if (otg_mode_host) {
384 otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, 387 otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
385 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); 388 ULPI_OTG_DRVVBUS_EXT);
386 389 if (otg_pdata.otg)
387 imx35_add_mxc_ehci_otg(&otg_pdata); 390 imx35_add_mxc_ehci_otg(&otg_pdata);
388 } 391 }
389
390 imx35_add_mxc_ehci_hs(&usbh1_pdata); 392 imx35_add_mxc_ehci_hs(&usbh1_pdata);
391#endif 393
392 if (!otg_mode_host) 394 if (!otg_mode_host)
393 imx35_add_fsl_usb2_udc(&otg_device_pdata); 395 imx35_add_fsl_usb2_udc(&otg_device_pdata);
394 396
@@ -407,10 +409,10 @@ struct sys_timer pcm043_timer = {
407 409
408MACHINE_START(PCM043, "Phytec Phycore pcm043") 410MACHINE_START(PCM043, "Phytec Phycore pcm043")
409 /* Maintainer: Pengutronix */ 411 /* Maintainer: Pengutronix */
410 .boot_params = MX3x_PHYS_OFFSET + 0x100, 412 .boot_params = MX3x_PHYS_OFFSET + 0x100,
411 .map_io = mx35_map_io, 413 .map_io = mx35_map_io,
412 .init_irq = mx35_init_irq, 414 .init_early = imx35_init_early,
413 .init_machine = mxc_board_init, 415 .init_irq = mx35_init_irq,
414 .timer = &pcm043_timer, 416 .timer = &pcm043_timer,
417 .init_machine = pcm043_init,
415MACHINE_END 418MACHINE_END
416
diff --git a/arch/arm/mach-mx3/mach-qong.c b/arch/arm/mach-mx3/mach-qong.c
index fd1050c40964..17f758b77623 100644
--- a/arch/arm/mach-mx3/mach-qong.c
+++ b/arch/arm/mach-mx3/mach-qong.c
@@ -54,10 +54,6 @@
54 54
55#define QONG_FPGA_IRQ IOMUX_TO_IRQ(MX31_PIN_DTR_DCE1) 55#define QONG_FPGA_IRQ IOMUX_TO_IRQ(MX31_PIN_DTR_DCE1)
56 56
57/*
58 * This file contains the board-specific initialization routines.
59 */
60
61static const struct imxuart_platform_data uart_pdata __initconst = { 57static const struct imxuart_platform_data uart_pdata __initconst = {
62 .flags = IMXUART_HAVE_RTSCTS, 58 .flags = IMXUART_HAVE_RTSCTS,
63}; 59};
@@ -247,7 +243,7 @@ static void __init qong_init_fpga(void)
247/* 243/*
248 * Board specific initialization. 244 * Board specific initialization.
249 */ 245 */
250static void __init mxc_board_init(void) 246static void __init qong_init(void)
251{ 247{
252 mxc_init_imx_uart(); 248 mxc_init_imx_uart();
253 qong_init_nor_mtd(); 249 qong_init_nor_mtd();
@@ -263,16 +259,12 @@ static struct sys_timer qong_timer = {
263 .init = qong_timer_init, 259 .init = qong_timer_init,
264}; 260};
265 261
266/*
267 * The following uses standard kernel macros defined in arch.h in order to
268 * initialize __mach_desc_QONG data structure.
269 */
270
271MACHINE_START(QONG, "Dave/DENX QongEVB-LITE") 262MACHINE_START(QONG, "Dave/DENX QongEVB-LITE")
272 /* Maintainer: DENX Software Engineering GmbH */ 263 /* Maintainer: DENX Software Engineering GmbH */
273 .boot_params = MX3x_PHYS_OFFSET + 0x100, 264 .boot_params = MX3x_PHYS_OFFSET + 0x100,
274 .map_io = mx31_map_io, 265 .map_io = mx31_map_io,
275 .init_irq = mx31_init_irq, 266 .init_early = imx31_init_early,
276 .init_machine = mxc_board_init, 267 .init_irq = mx31_init_irq,
277 .timer = &qong_timer, 268 .timer = &qong_timer,
269 .init_machine = qong_init,
278MACHINE_END 270MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-vpr200.c b/arch/arm/mach-mx3/mach-vpr200.c
new file mode 100644
index 000000000000..2cf390fbd980
--- /dev/null
+++ b/arch/arm/mach-mx3/mach-vpr200.c
@@ -0,0 +1,328 @@
1/*
2 * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2009 Marc Kleine-Budde, Pengutronix
4 * Copyright 2010 Creative Product Design
5 *
6 * Derived from mx35 3stack.
7 * Original author: Fabio Estevam <fabio.estevam@freescale.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 */
19
20#include <linux/types.h>
21#include <linux/init.h>
22#include <linux/platform_device.h>
23#include <linux/mtd/physmap.h>
24#include <linux/memory.h>
25#include <linux/gpio.h>
26
27#include <asm/mach-types.h>
28#include <asm/mach/arch.h>
29#include <asm/mach/time.h>
30
31#include <mach/hardware.h>
32#include <mach/common.h>
33#include <mach/iomux-mx35.h>
34#include <mach/irqs.h>
35#include <mach/ipu.h>
36#include <mach/mx3fb.h>
37
38#include <linux/i2c.h>
39#include <linux/i2c/at24.h>
40#include <linux/mfd/mc13xxx.h>
41#include <linux/gpio_keys.h>
42
43#include "devices-imx35.h"
44#include "devices.h"
45
46#define GPIO_LCDPWR IMX_GPIO_NR(1, 2)
47#define GPIO_PMIC_INT IMX_GPIO_NR(2, 0)
48
49#define GPIO_BUTTON1 IMX_GPIO_NR(1, 4)
50#define GPIO_BUTTON2 IMX_GPIO_NR(1, 5)
51#define GPIO_BUTTON3 IMX_GPIO_NR(1, 7)
52#define GPIO_BUTTON4 IMX_GPIO_NR(1, 8)
53#define GPIO_BUTTON5 IMX_GPIO_NR(1, 9)
54#define GPIO_BUTTON6 IMX_GPIO_NR(1, 10)
55#define GPIO_BUTTON7 IMX_GPIO_NR(1, 11)
56#define GPIO_BUTTON8 IMX_GPIO_NR(1, 12)
57
58static const struct fb_videomode fb_modedb[] = {
59 {
60 /* 800x480 @ 60 Hz */
61 .name = "PT0708048",
62 .refresh = 60,
63 .xres = 800,
64 .yres = 480,
65 .pixclock = KHZ2PICOS(33260),
66 .left_margin = 50,
67 .right_margin = 156,
68 .upper_margin = 10,
69 .lower_margin = 10,
70 .hsync_len = 1, /* note: DE only display */
71 .vsync_len = 1, /* note: DE only display */
72 .sync = FB_SYNC_CLK_IDLE_EN | FB_SYNC_OE_ACT_HIGH,
73 .vmode = FB_VMODE_NONINTERLACED,
74 .flag = 0,
75 }, {
76 /* 800x480 @ 60 Hz */
77 .name = "CTP-CLAA070LC0ACW",
78 .refresh = 60,
79 .xres = 800,
80 .yres = 480,
81 .pixclock = KHZ2PICOS(27000),
82 .left_margin = 50,
83 .right_margin = 50, /* whole line should have 900 clocks */
84 .upper_margin = 10,
85 .lower_margin = 10, /* whole frame should have 500 lines */
86 .hsync_len = 1, /* note: DE only display */
87 .vsync_len = 1, /* note: DE only display */
88 .sync = FB_SYNC_CLK_IDLE_EN | FB_SYNC_OE_ACT_HIGH,
89 .vmode = FB_VMODE_NONINTERLACED,
90 .flag = 0,
91 }
92};
93
94static struct ipu_platform_data mx3_ipu_data = {
95 .irq_base = MXC_IPU_IRQ_START,
96};
97
98static struct mx3fb_platform_data mx3fb_pdata = {
99 .dma_dev = &mx3_ipu.dev,
100 .name = "PT0708048",
101 .mode = fb_modedb,
102 .num_modes = ARRAY_SIZE(fb_modedb),
103};
104
105static struct physmap_flash_data vpr200_flash_data = {
106 .width = 2,
107};
108
109static struct resource vpr200_flash_resource = {
110 .start = MX35_CS0_BASE_ADDR,
111 .end = MX35_CS0_BASE_ADDR + SZ_64M - 1,
112 .flags = IORESOURCE_MEM,
113};
114
115static struct platform_device vpr200_flash = {
116 .name = "physmap-flash",
117 .id = 0,
118 .dev = {
119 .platform_data = &vpr200_flash_data,
120 },
121 .resource = &vpr200_flash_resource,
122 .num_resources = 1,
123};
124
125static const struct mxc_nand_platform_data
126 vpr200_nand_board_info __initconst = {
127 .width = 1,
128 .hw_ecc = 1,
129 .flash_bbt = 1,
130};
131
132#define VPR_KEY_DEBOUNCE 500
133static struct gpio_keys_button vpr200_gpio_keys_table[] = {
134 {KEY_F2, GPIO_BUTTON1, 1, "vpr-keys: F2", 0, VPR_KEY_DEBOUNCE},
135 {KEY_F3, GPIO_BUTTON2, 1, "vpr-keys: F3", 0, VPR_KEY_DEBOUNCE},
136 {KEY_F4, GPIO_BUTTON3, 1, "vpr-keys: F4", 0, VPR_KEY_DEBOUNCE},
137 {KEY_F5, GPIO_BUTTON4, 1, "vpr-keys: F5", 0, VPR_KEY_DEBOUNCE},
138 {KEY_F6, GPIO_BUTTON5, 1, "vpr-keys: F6", 0, VPR_KEY_DEBOUNCE},
139 {KEY_F7, GPIO_BUTTON6, 1, "vpr-keys: F7", 0, VPR_KEY_DEBOUNCE},
140 {KEY_F8, GPIO_BUTTON7, 1, "vpr-keys: F8", 1, VPR_KEY_DEBOUNCE},
141 {KEY_F9, GPIO_BUTTON8, 1, "vpr-keys: F9", 1, VPR_KEY_DEBOUNCE},
142};
143
144static struct gpio_keys_platform_data vpr200_gpio_keys_data = {
145 .buttons = vpr200_gpio_keys_table,
146 .nbuttons = ARRAY_SIZE(vpr200_gpio_keys_table),
147};
148
149static struct platform_device vpr200_device_gpiokeys = {
150 .name = "gpio-keys",
151 .dev = {
152 .platform_data = &vpr200_gpio_keys_data,
153 }
154};
155
156static struct mc13xxx_platform_data vpr200_pmic = {
157 .flags = MC13XXX_USE_ADC | MC13XXX_USE_TOUCHSCREEN,
158};
159
160static const struct imxi2c_platform_data vpr200_i2c0_data __initconst = {
161 .bitrate = 50000,
162};
163
164static struct at24_platform_data vpr200_eeprom = {
165 .byte_len = 2048 / 8,
166 .page_size = 1,
167};
168
169static struct i2c_board_info vpr200_i2c_devices[] = {
170 {
171 I2C_BOARD_INFO("at24", 0x50), /* E0=0, E1=0, E2=0 */
172 .platform_data = &vpr200_eeprom,
173 }, {
174 I2C_BOARD_INFO("mc13892", 0x08),
175 .platform_data = &vpr200_pmic,
176 .irq = gpio_to_irq(GPIO_PMIC_INT),
177 }
178};
179
180static iomux_v3_cfg_t vpr200_pads[] = {
181 /* UART1 */
182 MX35_PAD_TXD1__UART1_TXD_MUX,
183 MX35_PAD_RXD1__UART1_RXD_MUX,
184 /* UART3 */
185 MX35_PAD_ATA_DATA10__UART3_RXD_MUX,
186 MX35_PAD_ATA_DATA11__UART3_TXD_MUX,
187 /* FEC */
188 MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
189 MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
190 MX35_PAD_FEC_RX_DV__FEC_RX_DV,
191 MX35_PAD_FEC_COL__FEC_COL,
192 MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
193 MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
194 MX35_PAD_FEC_TX_EN__FEC_TX_EN,
195 MX35_PAD_FEC_MDC__FEC_MDC,
196 MX35_PAD_FEC_MDIO__FEC_MDIO,
197 MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
198 MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
199 MX35_PAD_FEC_CRS__FEC_CRS,
200 MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
201 MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
202 MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
203 MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
204 MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
205 MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
206 /* Display */
207 MX35_PAD_LD0__IPU_DISPB_DAT_0,
208 MX35_PAD_LD1__IPU_DISPB_DAT_1,
209 MX35_PAD_LD2__IPU_DISPB_DAT_2,
210 MX35_PAD_LD3__IPU_DISPB_DAT_3,
211 MX35_PAD_LD4__IPU_DISPB_DAT_4,
212 MX35_PAD_LD5__IPU_DISPB_DAT_5,
213 MX35_PAD_LD6__IPU_DISPB_DAT_6,
214 MX35_PAD_LD7__IPU_DISPB_DAT_7,
215 MX35_PAD_LD8__IPU_DISPB_DAT_8,
216 MX35_PAD_LD9__IPU_DISPB_DAT_9,
217 MX35_PAD_LD10__IPU_DISPB_DAT_10,
218 MX35_PAD_LD11__IPU_DISPB_DAT_11,
219 MX35_PAD_LD12__IPU_DISPB_DAT_12,
220 MX35_PAD_LD13__IPU_DISPB_DAT_13,
221 MX35_PAD_LD14__IPU_DISPB_DAT_14,
222 MX35_PAD_LD15__IPU_DISPB_DAT_15,
223 MX35_PAD_LD16__IPU_DISPB_DAT_16,
224 MX35_PAD_LD17__IPU_DISPB_DAT_17,
225 MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK,
226 MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY,
227 MX35_PAD_CONTRAST__IPU_DISPB_CONTR,
228 /* LCD Enable */
229 MX35_PAD_D3_VSYNC__GPIO1_2,
230 /* USBOTG */
231 MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR,
232 MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC,
233 /* SDCARD */
234 MX35_PAD_SD1_CMD__ESDHC1_CMD,
235 MX35_PAD_SD1_CLK__ESDHC1_CLK,
236 MX35_PAD_SD1_DATA0__ESDHC1_DAT0,
237 MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
238 MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
239 MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
240 /* PMIC */
241 MX35_PAD_GPIO2_0__GPIO2_0,
242 /* GPIO keys */
243 MX35_PAD_SCKR__GPIO1_4,
244 MX35_PAD_COMPARE__GPIO1_5,
245 MX35_PAD_SCKT__GPIO1_7,
246 MX35_PAD_FST__GPIO1_8,
247 MX35_PAD_HCKT__GPIO1_9,
248 MX35_PAD_TX5_RX0__GPIO1_10,
249 MX35_PAD_TX4_RX1__GPIO1_11,
250 MX35_PAD_TX3_RX2__GPIO1_12,
251};
252
253/* USB Device config */
254static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
255 .operating_mode = FSL_USB2_DR_DEVICE,
256 .phy_mode = FSL_USB2_PHY_UTMI,
257 .workaround = FLS_USB2_WORKAROUND_ENGCM09152,
258};
259
260/* USB HOST config */
261static const struct mxc_usbh_platform_data usb_host_pdata __initconst = {
262 .portsc = MXC_EHCI_MODE_SERIAL,
263 .flags = MXC_EHCI_INTERFACE_SINGLE_UNI |
264 MXC_EHCI_INTERNAL_PHY,
265};
266
267static struct platform_device *devices[] __initdata = {
268 &vpr200_flash,
269 &vpr200_device_gpiokeys,
270};
271
272/*
273 * Board specific initialization.
274 */
275static void __init vpr200_board_init(void)
276{
277 mxc_iomux_v3_setup_multiple_pads(vpr200_pads, ARRAY_SIZE(vpr200_pads));
278
279 imx35_add_fec(NULL);
280 imx35_add_imx2_wdt(NULL);
281
282 platform_add_devices(devices, ARRAY_SIZE(devices));
283
284 if (0 != gpio_request(GPIO_LCDPWR, "LCDPWR"))
285 printk(KERN_WARNING "vpr200: Couldn't get LCDPWR gpio\n");
286 else
287 gpio_direction_output(GPIO_LCDPWR, 0);
288
289 if (0 != gpio_request(GPIO_PMIC_INT, "PMIC_INT"))
290 printk(KERN_WARNING "vpr200: Couldn't get PMIC_INT gpio\n");
291 else
292 gpio_direction_input(GPIO_PMIC_INT);
293
294 imx35_add_imx_uart0(NULL);
295 imx35_add_imx_uart2(NULL);
296
297 mxc_register_device(&mx3_ipu, &mx3_ipu_data);
298 mxc_register_device(&mx3_fb, &mx3fb_pdata);
299
300 imx35_add_fsl_usb2_udc(&otg_device_pdata);
301 imx35_add_mxc_ehci_hs(&usb_host_pdata);
302
303 imx35_add_mxc_nand(&vpr200_nand_board_info);
304 imx35_add_sdhci_esdhc_imx(0, NULL);
305
306 i2c_register_board_info(0, vpr200_i2c_devices,
307 ARRAY_SIZE(vpr200_i2c_devices));
308
309 imx35_add_imx_i2c0(&vpr200_i2c0_data);
310}
311
312static void __init vpr200_timer_init(void)
313{
314 mx35_clocks_init();
315}
316
317struct sys_timer vpr200_timer = {
318 .init = vpr200_timer_init,
319};
320
321MACHINE_START(VPR200, "VPR200")
322 /* Maintainer: Creative Product Design */
323 .map_io = mx35_map_io,
324 .init_early = imx35_init_early,
325 .init_irq = mx35_init_irq,
326 .timer = &vpr200_timer,
327 .init_machine = vpr200_board_init,
328MACHINE_END
diff --git a/arch/arm/mach-mx3/mm.c b/arch/arm/mach-mx3/mm.c
index 47118f760244..54d7174b4202 100644
--- a/arch/arm/mach-mx3/mm.c
+++ b/arch/arm/mach-mx3/mm.c
@@ -27,14 +27,8 @@
27#include <mach/common.h> 27#include <mach/common.h>
28#include <mach/hardware.h> 28#include <mach/hardware.h>
29#include <mach/iomux-v3.h> 29#include <mach/iomux-v3.h>
30 30#include <mach/gpio.h>
31/*! 31#include <mach/irqs.h>
32 * @file mm.c
33 *
34 * @brief This file creates static virtual to physical mappings, common to all MX3 boards.
35 *
36 * @ingroup Memory
37 */
38 32
39#ifdef CONFIG_SOC_IMX31 33#ifdef CONFIG_SOC_IMX31
40static struct map_desc mx31_io_desc[] __initdata = { 34static struct map_desc mx31_io_desc[] __initdata = {
@@ -52,17 +46,25 @@ static struct map_desc mx31_io_desc[] __initdata = {
52 */ 46 */
53void __init mx31_map_io(void) 47void __init mx31_map_io(void)
54{ 48{
49 iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc));
50}
51
52void __init imx31_init_early(void)
53{
55 mxc_set_cpu_type(MXC_CPU_MX31); 54 mxc_set_cpu_type(MXC_CPU_MX31);
56 mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR)); 55 mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
57
58 iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc));
59} 56}
60 57
61int imx31_register_gpios(void); 58static struct mxc_gpio_port imx31_gpio_ports[] = {
59 DEFINE_IMX_GPIO_PORT_IRQ(MX31, 0, 1, MX31_INT_GPIO1),
60 DEFINE_IMX_GPIO_PORT_IRQ(MX31, 1, 2, MX31_INT_GPIO2),
61 DEFINE_IMX_GPIO_PORT_IRQ(MX31, 2, 3, MX31_INT_GPIO3),
62};
63
62void __init mx31_init_irq(void) 64void __init mx31_init_irq(void)
63{ 65{
64 mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR)); 66 mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR));
65 imx31_register_gpios(); 67 mxc_gpio_init(imx31_gpio_ports, ARRAY_SIZE(imx31_gpio_ports));
66} 68}
67#endif /* ifdef CONFIG_SOC_IMX31 */ 69#endif /* ifdef CONFIG_SOC_IMX31 */
68 70
@@ -77,18 +79,26 @@ static struct map_desc mx35_io_desc[] __initdata = {
77 79
78void __init mx35_map_io(void) 80void __init mx35_map_io(void)
79{ 81{
82 iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc));
83}
84
85void __init imx35_init_early(void)
86{
80 mxc_set_cpu_type(MXC_CPU_MX35); 87 mxc_set_cpu_type(MXC_CPU_MX35);
81 mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR)); 88 mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
82 mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR)); 89 mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
83
84 iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc));
85} 90}
86 91
87int imx35_register_gpios(void); 92static struct mxc_gpio_port imx35_gpio_ports[] = {
93 DEFINE_IMX_GPIO_PORT_IRQ(MX35, 0, 1, MX35_INT_GPIO1),
94 DEFINE_IMX_GPIO_PORT_IRQ(MX35, 1, 2, MX35_INT_GPIO2),
95 DEFINE_IMX_GPIO_PORT_IRQ(MX35, 2, 3, MX35_INT_GPIO3),
96};
97
88void __init mx35_init_irq(void) 98void __init mx35_init_irq(void)
89{ 99{
90 mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR)); 100 mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR));
91 imx35_register_gpios(); 101 mxc_gpio_init(imx35_gpio_ports, ARRAY_SIZE(imx35_gpio_ports));
92} 102}
93#endif /* ifdef CONFIG_SOC_IMX35 */ 103#endif /* ifdef CONFIG_SOC_IMX35 */
94 104
@@ -129,4 +139,3 @@ static int mxc_init_l2x0(void)
129 139
130arch_initcall(mxc_init_l2x0); 140arch_initcall(mxc_init_l2x0);
131#endif 141#endif
132
diff --git a/arch/arm/mach-mx3/mx31moboard-devboard.c b/arch/arm/mach-mx3/mx31moboard-devboard.c
index 94a0b9e4b7f3..6410b9c48a02 100644
--- a/arch/arm/mach-mx3/mx31moboard-devboard.c
+++ b/arch/arm/mach-mx3/mx31moboard-devboard.c
@@ -15,6 +15,7 @@
15#include <linux/gpio.h> 15#include <linux/gpio.h>
16#include <linux/init.h> 16#include <linux/init.h>
17#include <linux/interrupt.h> 17#include <linux/interrupt.h>
18#include <linux/delay.h>
18#include <linux/platform_device.h> 19#include <linux/platform_device.h>
19#include <linux/slab.h> 20#include <linux/slab.h>
20#include <linux/types.h> 21#include <linux/types.h>
@@ -149,7 +150,10 @@ static int devboard_usbh1_hw_init(struct platform_device *pdev)
149 mxc_iomux_set_pad(MX31_PIN_CSPI1_SPI_RDY, USB_PAD_CFG); 150 mxc_iomux_set_pad(MX31_PIN_CSPI1_SPI_RDY, USB_PAD_CFG);
150 mxc_iomux_set_pad(MX31_PIN_SFS6, USB_PAD_CFG); 151 mxc_iomux_set_pad(MX31_PIN_SFS6, USB_PAD_CFG);
151 152
152 return 0; 153 mdelay(10);
154
155 return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED |
156 MXC_EHCI_INTERFACE_SINGLE_UNI);
153} 157}
154 158
155#define USBH1_VBUSEN_B IOMUX_TO_GPIO(MX31_PIN_NFRE_B) 159#define USBH1_VBUSEN_B IOMUX_TO_GPIO(MX31_PIN_NFRE_B)
@@ -187,7 +191,6 @@ static int devboard_isp1105_set_vbus(struct otg_transceiver *otg, bool on)
187static struct mxc_usbh_platform_data usbh1_pdata __initdata = { 191static struct mxc_usbh_platform_data usbh1_pdata __initdata = {
188 .init = devboard_usbh1_hw_init, 192 .init = devboard_usbh1_hw_init,
189 .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL, 193 .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL,
190 .flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_SINGLE_UNI,
191}; 194};
192 195
193static int __init devboard_usbh1_init(void) 196static int __init devboard_usbh1_init(void)
diff --git a/arch/arm/mach-mx3/mx31moboard-marxbot.c b/arch/arm/mach-mx3/mx31moboard-marxbot.c
index f449a97ae1a2..57f7b00cb709 100644
--- a/arch/arm/mach-mx3/mx31moboard-marxbot.c
+++ b/arch/arm/mach-mx3/mx31moboard-marxbot.c
@@ -265,7 +265,10 @@ static int marxbot_usbh1_hw_init(struct platform_device *pdev)
265 mxc_iomux_set_pad(MX31_PIN_CSPI1_SPI_RDY, USB_PAD_CFG); 265 mxc_iomux_set_pad(MX31_PIN_CSPI1_SPI_RDY, USB_PAD_CFG);
266 mxc_iomux_set_pad(MX31_PIN_SFS6, USB_PAD_CFG); 266 mxc_iomux_set_pad(MX31_PIN_SFS6, USB_PAD_CFG);
267 267
268 return 0; 268 mdelay(10);
269
270 return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED |
271 MXC_EHCI_INTERFACE_SINGLE_UNI);
269} 272}
270 273
271#define USBH1_VBUSEN_B IOMUX_TO_GPIO(MX31_PIN_NFRE_B) 274#define USBH1_VBUSEN_B IOMUX_TO_GPIO(MX31_PIN_NFRE_B)
@@ -303,7 +306,6 @@ static int marxbot_isp1105_set_vbus(struct otg_transceiver *otg, bool on)
303static struct mxc_usbh_platform_data usbh1_pdata __initdata = { 306static struct mxc_usbh_platform_data usbh1_pdata __initdata = {
304 .init = marxbot_usbh1_hw_init, 307 .init = marxbot_usbh1_hw_init,
305 .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL, 308 .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL,
306 .flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_SINGLE_UNI,
307}; 309};
308 310
309static int __init marxbot_usbh1_init(void) 311static int __init marxbot_usbh1_init(void)
diff --git a/arch/arm/mach-mx3/mx31moboard-smartbot.c b/arch/arm/mach-mx3/mx31moboard-smartbot.c
index bbec3c82264a..35f806e737c1 100644
--- a/arch/arm/mach-mx3/mx31moboard-smartbot.c
+++ b/arch/arm/mach-mx3/mx31moboard-smartbot.c
@@ -123,17 +123,24 @@ static const struct fsl_usb2_platform_data usb_pdata __initconst = {
123 123
124#if defined(CONFIG_USB_ULPI) 124#if defined(CONFIG_USB_ULPI)
125 125
126static int smartbot_otg_init(struct platform_device *pdev)
127{
128 return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
129}
130
126static struct mxc_usbh_platform_data otg_host_pdata __initdata = { 131static struct mxc_usbh_platform_data otg_host_pdata __initdata = {
132 .init = smartbot_otg_init,
127 .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, 133 .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
128 .flags = MXC_EHCI_POWER_PINS_ENABLED,
129}; 134};
130 135
131static int __init smartbot_otg_host_init(void) 136static int __init smartbot_otg_host_init(void)
132{ 137{
133 struct platform_device *pdev; 138 struct platform_device *pdev;
134 139
135 otg_host_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, 140 otg_host_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
136 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); 141 ULPI_OTG_DRVVBUS_EXT);
142 if (!otg_host_pdata.otg)
143 return -ENODEV;
137 144
138 pdev = imx31_add_mxc_ehci_otg(&otg_host_pdata); 145 pdev = imx31_add_mxc_ehci_otg(&otg_host_pdata);
139 if (IS_ERR(pdev)) 146 if (IS_ERR(pdev))
diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig
index de4fa992fc3e..83ee08847d4d 100644
--- a/arch/arm/mach-mx5/Kconfig
+++ b/arch/arm/mach-mx5/Kconfig
@@ -1,5 +1,6 @@
1if ARCH_MX5 1if ARCH_MX5
2# ARCH_MX51 and ARCH_MX50 are left for compatibility 2# ARCH_MX50/51/53 are left to mark places where prevent multi-soc in single
3# image. So for most time, SOC_IMX50/51/53 should be used.
3 4
4config ARCH_MX50 5config ARCH_MX50
5 bool 6 bool
@@ -50,6 +51,7 @@ config MACH_MX51_BABBAGE
50config MACH_MX51_3DS 51config MACH_MX51_3DS
51 bool "Support MX51PDK (3DS)" 52 bool "Support MX51PDK (3DS)"
52 select SOC_IMX51 53 select SOC_IMX51
54 select IMX_HAVE_PLATFORM_IMX2_WDT
53 select IMX_HAVE_PLATFORM_IMX_KEYPAD 55 select IMX_HAVE_PLATFORM_IMX_KEYPAD
54 select IMX_HAVE_PLATFORM_IMX_UART 56 select IMX_HAVE_PLATFORM_IMX_UART
55 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX 57 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
@@ -112,19 +114,32 @@ config MACH_EUKREA_MBIMXSD51_BASEBOARD
112 114
113endchoice 115endchoice
114 116
115config MACH_MX51_EFIKAMX 117config MX51_EFIKA_COMMON
116 bool "Support MX51 Genesi Efika MX nettop" 118 bool
117 select SOC_IMX51 119 select SOC_IMX51
118 select IMX_HAVE_PLATFORM_IMX_UART 120 select IMX_HAVE_PLATFORM_IMX_UART
119 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX 121 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
120 select IMX_HAVE_PLATFORM_SPI_IMX 122 select IMX_HAVE_PLATFORM_SPI_IMX
123 select MXC_ULPI if USB_ULPI
124
125config MACH_MX51_EFIKAMX
126 bool "Support MX51 Genesi Efika MX nettop"
127 select MX51_EFIKA_COMMON
121 help 128 help
122 Include support for Genesi Efika MX nettop. This includes specific 129 Include support for Genesi Efika MX nettop. This includes specific
123 configurations for the board and its peripherals. 130 configurations for the board and its peripherals.
124 131
132config MACH_MX51_EFIKASB
133 bool "Support MX51 Genesi Efika Smartbook"
134 select MX51_EFIKA_COMMON
135 help
136 Include support for Genesi Efika Smartbook. This includes specific
137 configurations for the board and its peripherals.
138
125config MACH_MX53_EVK 139config MACH_MX53_EVK
126 bool "Support MX53 EVK platforms" 140 bool "Support MX53 EVK platforms"
127 select SOC_IMX53 141 select SOC_IMX53
142 select IMX_HAVE_PLATFORM_IMX2_WDT
128 select IMX_HAVE_PLATFORM_IMX_UART 143 select IMX_HAVE_PLATFORM_IMX_UART
129 select IMX_HAVE_PLATFORM_IMX_I2C 144 select IMX_HAVE_PLATFORM_IMX_I2C
130 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX 145 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
@@ -136,6 +151,8 @@ config MACH_MX53_EVK
136config MACH_MX53_SMD 151config MACH_MX53_SMD
137 bool "Support MX53 SMD platforms" 152 bool "Support MX53 SMD platforms"
138 select SOC_IMX53 153 select SOC_IMX53
154 select IMX_HAVE_PLATFORM_IMX2_WDT
155 select IMX_HAVE_PLATFORM_IMX_I2C
139 select IMX_HAVE_PLATFORM_IMX_UART 156 select IMX_HAVE_PLATFORM_IMX_UART
140 help 157 help
141 Include support for MX53 SMD platform. This includes specific 158 Include support for MX53 SMD platform. This includes specific
@@ -144,7 +161,10 @@ config MACH_MX53_SMD
144config MACH_MX53_LOCO 161config MACH_MX53_LOCO
145 bool "Support MX53 LOCO platforms" 162 bool "Support MX53 LOCO platforms"
146 select SOC_IMX53 163 select SOC_IMX53
164 select IMX_HAVE_PLATFORM_IMX2_WDT
165 select IMX_HAVE_PLATFORM_IMX_I2C
147 select IMX_HAVE_PLATFORM_IMX_UART 166 select IMX_HAVE_PLATFORM_IMX_UART
167 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
148 help 168 help
149 Include support for MX53 LOCO platform. This includes specific 169 Include support for MX53 LOCO platform. This includes specific
150 configurations for the board and its peripherals. 170 configurations for the board and its peripherals.
@@ -157,6 +177,7 @@ config MACH_MX50_RDP
157 select IMX_HAVE_PLATFORM_IMX_UART 177 select IMX_HAVE_PLATFORM_IMX_UART
158 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX 178 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
159 select IMX_HAVE_PLATFORM_SPI_IMX 179 select IMX_HAVE_PLATFORM_SPI_IMX
180 select IMX_HAVE_PLATFORM_FEC
160 help 181 help
161 Include support for MX50 reference design platform (RDP) board. This 182 Include support for MX50 reference design platform (RDP) board. This
162 includes specific configurations for the board and its peripherals. 183 includes specific configurations for the board and its peripherals.
diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile
index 0d43be98e51c..4f63048be3ca 100644
--- a/arch/arm/mach-mx5/Makefile
+++ b/arch/arm/mach-mx5/Makefile
@@ -3,7 +3,7 @@
3# 3#
4 4
5# Object file lists. 5# Object file lists.
6obj-y := cpu.o mm.o clock-mx51-mx53.o devices.o 6obj-y := cpu.o mm.o clock-mx51-mx53.o devices.o ehci.o
7obj-$(CONFIG_SOC_IMX50) += mm-mx50.o 7obj-$(CONFIG_SOC_IMX50) += mm-mx50.o
8 8
9obj-$(CONFIG_CPU_FREQ_IMX) += cpu_op-mx51.o 9obj-$(CONFIG_CPU_FREQ_IMX) += cpu_op-mx51.o
@@ -16,5 +16,7 @@ obj-$(CONFIG_MACH_EUKREA_CPUIMX51) += board-cpuimx51.o
16obj-$(CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD) += eukrea_mbimx51-baseboard.o 16obj-$(CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD) += eukrea_mbimx51-baseboard.o
17obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += board-cpuimx51sd.o 17obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += board-cpuimx51sd.o
18obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd-baseboard.o 18obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd-baseboard.o
19obj-$(CONFIG_MX51_EFIKA_COMMON) += mx51_efika.o
19obj-$(CONFIG_MACH_MX51_EFIKAMX) += board-mx51_efikamx.o 20obj-$(CONFIG_MACH_MX51_EFIKAMX) += board-mx51_efikamx.o
21obj-$(CONFIG_MACH_MX51_EFIKASB) += board-mx51_efikasb.o
20obj-$(CONFIG_MACH_MX50_RDP) += board-mx50_rdp.o 22obj-$(CONFIG_MACH_MX50_RDP) += board-mx50_rdp.o
diff --git a/arch/arm/mach-mx5/board-cpuimx51.c b/arch/arm/mach-mx5/board-cpuimx51.c
index f8652ef25f85..d0296a94c475 100644
--- a/arch/arm/mach-mx5/board-cpuimx51.c
+++ b/arch/arm/mach-mx5/board-cpuimx51.c
@@ -60,7 +60,6 @@
60#define MX51_USB_PLL_DIV_19_2_MHZ 0x01 60#define MX51_USB_PLL_DIV_19_2_MHZ 0x01
61#define MX51_USB_PLL_DIV_24_MHZ 0x02 61#define MX51_USB_PLL_DIV_24_MHZ 0x02
62 62
63#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
64static struct plat_serial8250_port serial_platform_data[] = { 63static struct plat_serial8250_port serial_platform_data[] = {
65 { 64 {
66 .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x400000), 65 .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x400000),
@@ -105,12 +104,9 @@ static struct platform_device serial_device = {
105 .platform_data = serial_platform_data, 104 .platform_data = serial_platform_data,
106 }, 105 },
107}; 106};
108#endif
109 107
110static struct platform_device *devices[] __initdata = { 108static struct platform_device *devices[] __initdata = {
111#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
112 &serial_device, 109 &serial_device,
113#endif
114}; 110};
115 111
116static iomux_v3_cfg_t eukrea_cpuimx51_pads[] = { 112static iomux_v3_cfg_t eukrea_cpuimx51_pads[] = {
@@ -188,7 +184,10 @@ static int initialize_otg_port(struct platform_device *pdev)
188 v |= MX51_USB_PLL_DIV_19_2_MHZ; 184 v |= MX51_USB_PLL_DIV_19_2_MHZ;
189 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET); 185 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
190 iounmap(usb_base); 186 iounmap(usb_base);
191 return 0; 187
188 mdelay(10);
189
190 return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY);
192} 191}
193 192
194static int initialize_usbh1_port(struct platform_device *pdev) 193static int initialize_usbh1_port(struct platform_device *pdev)
@@ -206,13 +205,16 @@ static int initialize_usbh1_port(struct platform_device *pdev)
206 v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET); 205 v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
207 __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + MX51_USB_CTRL_1_OFFSET); 206 __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + MX51_USB_CTRL_1_OFFSET);
208 iounmap(usb_base); 207 iounmap(usb_base);
209 return 0; 208
209 mdelay(10);
210
211 return mx51_initialize_usb_hw(1, MXC_EHCI_POWER_PINS_ENABLED |
212 MXC_EHCI_ITC_NO_THRESHOLD);
210} 213}
211 214
212static struct mxc_usbh_platform_data dr_utmi_config = { 215static struct mxc_usbh_platform_data dr_utmi_config = {
213 .init = initialize_otg_port, 216 .init = initialize_otg_port,
214 .portsc = MXC_EHCI_UTMI_16BIT, 217 .portsc = MXC_EHCI_UTMI_16BIT,
215 .flags = MXC_EHCI_INTERNAL_PHY,
216}; 218};
217 219
218static struct fsl_usb2_platform_data usb_pdata = { 220static struct fsl_usb2_platform_data usb_pdata = {
@@ -223,7 +225,6 @@ static struct fsl_usb2_platform_data usb_pdata = {
223static struct mxc_usbh_platform_data usbh1_config = { 225static struct mxc_usbh_platform_data usbh1_config = {
224 .init = initialize_usbh1_port, 226 .init = initialize_usbh1_port,
225 .portsc = MXC_EHCI_MODE_ULPI, 227 .portsc = MXC_EHCI_MODE_ULPI,
226 .flags = (MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_ITC_NO_THRESHOLD),
227}; 228};
228 229
229static int otg_mode_host; 230static int otg_mode_host;
@@ -298,7 +299,8 @@ MACHINE_START(EUKREA_CPUIMX51, "Eukrea CPUIMX51 Module")
298 /* Maintainer: Eric Bénard <eric@eukrea.com> */ 299 /* Maintainer: Eric Bénard <eric@eukrea.com> */
299 .boot_params = MX51_PHYS_OFFSET + 0x100, 300 .boot_params = MX51_PHYS_OFFSET + 0x100,
300 .map_io = mx51_map_io, 301 .map_io = mx51_map_io,
302 .init_early = imx51_init_early,
301 .init_irq = mx51_init_irq, 303 .init_irq = mx51_init_irq,
302 .init_machine = eukrea_cpuimx51_init,
303 .timer = &mxc_timer, 304 .timer = &mxc_timer,
305 .init_machine = eukrea_cpuimx51_init,
304MACHINE_END 306MACHINE_END
diff --git a/arch/arm/mach-mx5/board-cpuimx51sd.c b/arch/arm/mach-mx5/board-cpuimx51sd.c
index ad931895d8b6..29b180823bf5 100644
--- a/arch/arm/mach-mx5/board-cpuimx51sd.c
+++ b/arch/arm/mach-mx5/board-cpuimx51sd.c
@@ -42,6 +42,7 @@
42 42
43#include "devices-imx51.h" 43#include "devices-imx51.h"
44#include "devices.h" 44#include "devices.h"
45#include "cpu_op-mx51.h"
45 46
46#define USBH1_RST IMX_GPIO_NR(2, 28) 47#define USBH1_RST IMX_GPIO_NR(2, 28)
47#define ETH_RST IMX_GPIO_NR(2, 31) 48#define ETH_RST IMX_GPIO_NR(2, 31)
@@ -109,7 +110,7 @@ static iomux_v3_cfg_t eukrea_cpuimx51sd_pads[] = {
109 110
110 /* Touchscreen */ 111 /* Touchscreen */
111 /* IRQ */ 112 /* IRQ */
112 _MX51_PAD_CSI1_D8__GPIO3_12 | MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP | 113 _MX51_PAD_GPIO_NAND__GPIO_NAND | MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |
113 PAD_CTL_PKE | PAD_CTL_SRE_FAST | 114 PAD_CTL_PKE | PAD_CTL_SRE_FAST |
114 PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS), 115 PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS),
115}; 116};
@@ -118,15 +119,9 @@ static const struct imxuart_platform_data uart_pdata __initconst = {
118 .flags = IMXUART_HAVE_RTSCTS, 119 .flags = IMXUART_HAVE_RTSCTS,
119}; 120};
120 121
121static int ts_get_pendown_state(void)
122{
123 return gpio_get_value(TSC2007_IRQGPIO) ? 0 : 1;
124}
125
126static struct tsc2007_platform_data tsc2007_info = { 122static struct tsc2007_platform_data tsc2007_info = {
127 .model = 2007, 123 .model = 2007,
128 .x_plate_ohms = 180, 124 .x_plate_ohms = 180,
129 .get_pendown_state = ts_get_pendown_state,
130}; 125};
131 126
132static struct i2c_board_info eukrea_cpuimx51sd_i2c_devices[] = { 127static struct i2c_board_info eukrea_cpuimx51sd_i2c_devices[] = {
@@ -167,7 +162,10 @@ static int initialize_otg_port(struct platform_device *pdev)
167 v |= MX51_USB_PLL_DIV_19_2_MHZ; 162 v |= MX51_USB_PLL_DIV_19_2_MHZ;
168 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET); 163 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
169 iounmap(usb_base); 164 iounmap(usb_base);
170 return 0; 165
166 mdelay(10);
167
168 return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY);
171} 169}
172 170
173static int initialize_usbh1_port(struct platform_device *pdev) 171static int initialize_usbh1_port(struct platform_device *pdev)
@@ -186,13 +184,16 @@ static int initialize_usbh1_port(struct platform_device *pdev)
186 __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, 184 __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN,
187 usbother_base + MX51_USB_CTRL_1_OFFSET); 185 usbother_base + MX51_USB_CTRL_1_OFFSET);
188 iounmap(usb_base); 186 iounmap(usb_base);
189 return 0; 187
188 mdelay(10);
189
190 return mx51_initialize_usb_hw(1, MXC_EHCI_POWER_PINS_ENABLED |
191 MXC_EHCI_ITC_NO_THRESHOLD);
190} 192}
191 193
192static struct mxc_usbh_platform_data dr_utmi_config = { 194static struct mxc_usbh_platform_data dr_utmi_config = {
193 .init = initialize_otg_port, 195 .init = initialize_otg_port,
194 .portsc = MXC_EHCI_UTMI_16BIT, 196 .portsc = MXC_EHCI_UTMI_16BIT,
195 .flags = MXC_EHCI_INTERNAL_PHY,
196}; 197};
197 198
198static struct fsl_usb2_platform_data usb_pdata = { 199static struct fsl_usb2_platform_data usb_pdata = {
@@ -203,7 +204,6 @@ static struct fsl_usb2_platform_data usb_pdata = {
203static struct mxc_usbh_platform_data usbh1_config = { 204static struct mxc_usbh_platform_data usbh1_config = {
204 .init = initialize_usbh1_port, 205 .init = initialize_usbh1_port,
205 .portsc = MXC_EHCI_MODE_ULPI, 206 .portsc = MXC_EHCI_MODE_ULPI,
206 .flags = (MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_ITC_NO_THRESHOLD),
207}; 207};
208 208
209static int otg_mode_host; 209static int otg_mode_host;
@@ -242,7 +242,7 @@ static struct mcp251x_platform_data mcp251x_info = {
242static struct spi_board_info cpuimx51sd_spi_device[] = { 242static struct spi_board_info cpuimx51sd_spi_device[] = {
243 { 243 {
244 .modalias = "mcp2515", 244 .modalias = "mcp2515",
245 .max_speed_hz = 6500000, 245 .max_speed_hz = 10000000,
246 .bus_num = 0, 246 .bus_num = 0,
247 .mode = SPI_MODE_0, 247 .mode = SPI_MODE_0,
248 .chip_select = 0, 248 .chip_select = 0,
@@ -269,6 +269,10 @@ static void __init eukrea_cpuimx51sd_init(void)
269 mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51sd_pads, 269 mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51sd_pads,
270 ARRAY_SIZE(eukrea_cpuimx51sd_pads)); 270 ARRAY_SIZE(eukrea_cpuimx51sd_pads));
271 271
272#if defined(CONFIG_CPU_FREQ_IMX)
273 get_cpu_op = mx51_get_cpu_op;
274#endif
275
272 imx51_add_imx_uart(0, &uart_pdata); 276 imx51_add_imx_uart(0, &uart_pdata);
273 imx51_add_mxc_nand(&eukrea_cpuimx51sd_nand_board_info); 277 imx51_add_mxc_nand(&eukrea_cpuimx51sd_nand_board_info);
274 278
@@ -329,7 +333,8 @@ MACHINE_START(EUKREA_CPUIMX51SD, "Eukrea CPUIMX51SD")
329 /* Maintainer: Eric Bénard <eric@eukrea.com> */ 333 /* Maintainer: Eric Bénard <eric@eukrea.com> */
330 .boot_params = MX51_PHYS_OFFSET + 0x100, 334 .boot_params = MX51_PHYS_OFFSET + 0x100,
331 .map_io = mx51_map_io, 335 .map_io = mx51_map_io,
336 .init_early = imx51_init_early,
332 .init_irq = mx51_init_irq, 337 .init_irq = mx51_init_irq,
333 .init_machine = eukrea_cpuimx51sd_init,
334 .timer = &mxc_timer, 338 .timer = &mxc_timer,
339 .init_machine = eukrea_cpuimx51sd_init,
335MACHINE_END 340MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx50_rdp.c b/arch/arm/mach-mx5/board-mx50_rdp.c
index fd32e4c450e8..dedf7f2d6d0f 100644
--- a/arch/arm/mach-mx5/board-mx50_rdp.c
+++ b/arch/arm/mach-mx5/board-mx50_rdp.c
@@ -35,7 +35,10 @@
35#include <asm/mach/arch.h> 35#include <asm/mach/arch.h>
36#include <asm/mach/time.h> 36#include <asm/mach/time.h>
37 37
38#include "devices-mx50.h" 38#include "devices-imx50.h"
39
40#define FEC_EN IMX_GPIO_NR(6, 23)
41#define FEC_RESET_B IMX_GPIO_NR(4, 12)
39 42
40static iomux_v3_cfg_t mx50_rdp_pads[] __initdata = { 43static iomux_v3_cfg_t mx50_rdp_pads[] __initdata = {
41 /* SD1 */ 44 /* SD1 */
@@ -102,7 +105,7 @@ static iomux_v3_cfg_t mx50_rdp_pads[] __initdata = {
102 MX50_PAD_I2C3_SCL__USBOTG_OC, 105 MX50_PAD_I2C3_SCL__USBOTG_OC,
103 106
104 MX50_PAD_SSI_RXC__FEC_MDIO, 107 MX50_PAD_SSI_RXC__FEC_MDIO,
105 MX50_PAD_SSI_RXC__FEC_MDIO, 108 MX50_PAD_SSI_RXFS__FEC_MDC,
106 MX50_PAD_DISP_D0__FEC_TXCLK, 109 MX50_PAD_DISP_D0__FEC_TXCLK,
107 MX50_PAD_DISP_D1__FEC_RX_ER, 110 MX50_PAD_DISP_D1__FEC_RX_ER,
108 MX50_PAD_DISP_D2__FEC_RX_DV, 111 MX50_PAD_DISP_D2__FEC_RX_DV,
@@ -111,7 +114,6 @@ static iomux_v3_cfg_t mx50_rdp_pads[] __initdata = {
111 MX50_PAD_DISP_D5__FEC_TX_EN, 114 MX50_PAD_DISP_D5__FEC_TX_EN,
112 MX50_PAD_DISP_D6__FEC_TXD1, 115 MX50_PAD_DISP_D6__FEC_TXD1,
113 MX50_PAD_DISP_D7__FEC_TXD0, 116 MX50_PAD_DISP_D7__FEC_TXD0,
114 MX50_PAD_SSI_RXFS__FEC_MDC,
115 MX50_PAD_I2C3_SDA__GPIO_6_23, 117 MX50_PAD_I2C3_SDA__GPIO_6_23,
116 MX50_PAD_ECSPI1_SCLK__GPIO_4_12, 118 MX50_PAD_ECSPI1_SCLK__GPIO_4_12,
117 119
@@ -168,6 +170,24 @@ static const struct imxuart_platform_data uart_pdata __initconst = {
168 .flags = IMXUART_HAVE_RTSCTS, 170 .flags = IMXUART_HAVE_RTSCTS,
169}; 171};
170 172
173static const struct fec_platform_data fec_data __initconst = {
174 .phy = PHY_INTERFACE_MODE_RMII,
175};
176
177static inline void mx50_rdp_fec_reset(void)
178{
179 gpio_request(FEC_EN, "fec-en");
180 gpio_direction_output(FEC_EN, 0);
181 gpio_request(FEC_RESET_B, "fec-reset_b");
182 gpio_direction_output(FEC_RESET_B, 0);
183 msleep(1);
184 gpio_set_value(FEC_RESET_B, 1);
185}
186
187static const struct imxi2c_platform_data i2c_data __initconst = {
188 .bitrate = 100000,
189};
190
171/* 191/*
172 * Board specific initialization. 192 * Board specific initialization.
173 */ 193 */
@@ -178,6 +198,11 @@ static void __init mx50_rdp_board_init(void)
178 198
179 imx50_add_imx_uart(0, &uart_pdata); 199 imx50_add_imx_uart(0, &uart_pdata);
180 imx50_add_imx_uart(1, &uart_pdata); 200 imx50_add_imx_uart(1, &uart_pdata);
201 mx50_rdp_fec_reset();
202 imx50_add_fec(&fec_data);
203 imx50_add_imx_i2c(0, &i2c_data);
204 imx50_add_imx_i2c(1, &i2c_data);
205 imx50_add_imx_i2c(2, &i2c_data);
181} 206}
182 207
183static void __init mx50_rdp_timer_init(void) 208static void __init mx50_rdp_timer_init(void)
@@ -191,7 +216,8 @@ static struct sys_timer mx50_rdp_timer = {
191 216
192MACHINE_START(MX50_RDP, "Freescale MX50 Reference Design Platform") 217MACHINE_START(MX50_RDP, "Freescale MX50 Reference Design Platform")
193 .map_io = mx50_map_io, 218 .map_io = mx50_map_io,
219 .init_early = imx50_init_early,
194 .init_irq = mx50_init_irq, 220 .init_irq = mx50_init_irq,
195 .init_machine = mx50_rdp_board_init,
196 .timer = &mx50_rdp_timer, 221 .timer = &mx50_rdp_timer,
222 .init_machine = mx50_rdp_board_init,
197MACHINE_END 223MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx51_3ds.c b/arch/arm/mach-mx5/board-mx51_3ds.c
index 49d644842379..63dfbeafbc1e 100644
--- a/arch/arm/mach-mx5/board-mx51_3ds.c
+++ b/arch/arm/mach-mx5/board-mx51_3ds.c
@@ -71,24 +71,10 @@ static iomux_v3_cfg_t mx51_3ds_pads[] = {
71}; 71};
72 72
73/* Serial ports */ 73/* Serial ports */
74#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
75static const struct imxuart_platform_data uart_pdata __initconst = { 74static const struct imxuart_platform_data uart_pdata __initconst = {
76 .flags = IMXUART_HAVE_RTSCTS, 75 .flags = IMXUART_HAVE_RTSCTS,
77}; 76};
78 77
79static inline void mxc_init_imx_uart(void)
80{
81 imx51_add_imx_uart(0, &uart_pdata);
82 imx51_add_imx_uart(1, &uart_pdata);
83 imx51_add_imx_uart(2, &uart_pdata);
84}
85#else /* !SERIAL_IMX */
86static inline void mxc_init_imx_uart(void)
87{
88}
89#endif /* SERIAL_IMX */
90
91#if defined(CONFIG_KEYBOARD_IMX) || defined(CONFIG_KEYBOARD_IMX_MODULE)
92static int mx51_3ds_board_keymap[] = { 78static int mx51_3ds_board_keymap[] = {
93 KEY(0, 0, KEY_1), 79 KEY(0, 0, KEY_1),
94 KEY(0, 1, KEY_2), 80 KEY(0, 1, KEY_2),
@@ -124,16 +110,6 @@ static const struct matrix_keymap_data mx51_3ds_map_data __initconst = {
124 .keymap_size = ARRAY_SIZE(mx51_3ds_board_keymap), 110 .keymap_size = ARRAY_SIZE(mx51_3ds_board_keymap),
125}; 111};
126 112
127static void mxc_init_keypad(void)
128{
129 imx51_add_imx_keypad(&mx51_3ds_map_data);
130}
131#else
132static inline void mxc_init_keypad(void)
133{
134}
135#endif
136
137static int mx51_3ds_spi2_cs[] = { 113static int mx51_3ds_spi2_cs[] = {
138 MXC_SPI_CS(0), 114 MXC_SPI_CS(0),
139 MX51_3DS_ECSPI2_CS, 115 MX51_3DS_ECSPI2_CS,
@@ -157,11 +133,14 @@ static struct spi_board_info mx51_3ds_spi_nor_device[] = {
157/* 133/*
158 * Board specific initialization. 134 * Board specific initialization.
159 */ 135 */
160static void __init mxc_board_init(void) 136static void __init mx51_3ds_init(void)
161{ 137{
162 mxc_iomux_v3_setup_multiple_pads(mx51_3ds_pads, 138 mxc_iomux_v3_setup_multiple_pads(mx51_3ds_pads,
163 ARRAY_SIZE(mx51_3ds_pads)); 139 ARRAY_SIZE(mx51_3ds_pads));
164 mxc_init_imx_uart(); 140
141 imx51_add_imx_uart(0, &uart_pdata);
142 imx51_add_imx_uart(1, &uart_pdata);
143 imx51_add_imx_uart(2, &uart_pdata);
165 144
166 imx51_add_ecspi(1, &mx51_3ds_ecspi2_pdata); 145 imx51_add_ecspi(1, &mx51_3ds_ecspi2_pdata);
167 spi_register_board_info(mx51_3ds_spi_nor_device, 146 spi_register_board_info(mx51_3ds_spi_nor_device,
@@ -172,7 +151,8 @@ static void __init mxc_board_init(void)
172 "devices on the board are unusable.\n"); 151 "devices on the board are unusable.\n");
173 152
174 imx51_add_sdhci_esdhc_imx(0, NULL); 153 imx51_add_sdhci_esdhc_imx(0, NULL);
175 mxc_init_keypad(); 154 imx51_add_imx_keypad(&mx51_3ds_map_data);
155 imx51_add_imx2_wdt(0, NULL);
176} 156}
177 157
178static void __init mx51_3ds_timer_init(void) 158static void __init mx51_3ds_timer_init(void)
@@ -180,15 +160,16 @@ static void __init mx51_3ds_timer_init(void)
180 mx51_clocks_init(32768, 24000000, 22579200, 0); 160 mx51_clocks_init(32768, 24000000, 22579200, 0);
181} 161}
182 162
183static struct sys_timer mxc_timer = { 163static struct sys_timer mx51_3ds_timer = {
184 .init = mx51_3ds_timer_init, 164 .init = mx51_3ds_timer_init,
185}; 165};
186 166
187MACHINE_START(MX51_3DS, "Freescale MX51 3-Stack Board") 167MACHINE_START(MX51_3DS, "Freescale MX51 3-Stack Board")
188 /* Maintainer: Freescale Semiconductor, Inc. */ 168 /* Maintainer: Freescale Semiconductor, Inc. */
189 .boot_params = MX51_PHYS_OFFSET + 0x100, 169 .boot_params = MX51_PHYS_OFFSET + 0x100,
190 .map_io = mx51_map_io, 170 .map_io = mx51_map_io,
171 .init_early = imx51_init_early,
191 .init_irq = mx51_init_irq, 172 .init_irq = mx51_init_irq,
192 .init_machine = mxc_board_init, 173 .timer = &mx51_3ds_timer,
193 .timer = &mxc_timer, 174 .init_machine = mx51_3ds_init,
194MACHINE_END 175MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c
index 1d231e84107c..b2ecd194e76d 100644
--- a/arch/arm/mach-mx5/board-mx51_babbage.c
+++ b/arch/arm/mach-mx5/board-mx51_babbage.c
@@ -161,23 +161,10 @@ static iomux_v3_cfg_t mx51babbage_pads[] = {
161}; 161};
162 162
163/* Serial ports */ 163/* Serial ports */
164#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
165static const struct imxuart_platform_data uart_pdata __initconst = { 164static const struct imxuart_platform_data uart_pdata __initconst = {
166 .flags = IMXUART_HAVE_RTSCTS, 165 .flags = IMXUART_HAVE_RTSCTS,
167}; 166};
168 167
169static inline void mxc_init_imx_uart(void)
170{
171 imx51_add_imx_uart(0, &uart_pdata);
172 imx51_add_imx_uart(1, &uart_pdata);
173 imx51_add_imx_uart(2, &uart_pdata);
174}
175#else /* !SERIAL_IMX */
176static inline void mxc_init_imx_uart(void)
177{
178}
179#endif /* SERIAL_IMX */
180
181static const struct imxi2c_platform_data babbage_i2c_data __initconst = { 168static const struct imxi2c_platform_data babbage_i2c_data __initconst = {
182 .bitrate = 100000, 169 .bitrate = 100000,
183}; 170};
@@ -272,7 +259,10 @@ static int initialize_otg_port(struct platform_device *pdev)
272 v |= MX51_USB_PLL_DIV_19_2_MHZ; 259 v |= MX51_USB_PLL_DIV_19_2_MHZ;
273 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET); 260 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
274 iounmap(usb_base); 261 iounmap(usb_base);
275 return 0; 262
263 mdelay(10);
264
265 return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY);
276} 266}
277 267
278static int initialize_usbh1_port(struct platform_device *pdev) 268static int initialize_usbh1_port(struct platform_device *pdev)
@@ -290,13 +280,16 @@ static int initialize_usbh1_port(struct platform_device *pdev)
290 v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET); 280 v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
291 __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + MX51_USB_CTRL_1_OFFSET); 281 __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + MX51_USB_CTRL_1_OFFSET);
292 iounmap(usb_base); 282 iounmap(usb_base);
293 return 0; 283
284 mdelay(10);
285
286 return mx51_initialize_usb_hw(1, MXC_EHCI_POWER_PINS_ENABLED |
287 MXC_EHCI_ITC_NO_THRESHOLD);
294} 288}
295 289
296static struct mxc_usbh_platform_data dr_utmi_config = { 290static struct mxc_usbh_platform_data dr_utmi_config = {
297 .init = initialize_otg_port, 291 .init = initialize_otg_port,
298 .portsc = MXC_EHCI_UTMI_16BIT, 292 .portsc = MXC_EHCI_UTMI_16BIT,
299 .flags = MXC_EHCI_INTERNAL_PHY,
300}; 293};
301 294
302static struct fsl_usb2_platform_data usb_pdata = { 295static struct fsl_usb2_platform_data usb_pdata = {
@@ -307,7 +300,6 @@ static struct fsl_usb2_platform_data usb_pdata = {
307static struct mxc_usbh_platform_data usbh1_config = { 300static struct mxc_usbh_platform_data usbh1_config = {
308 .init = initialize_usbh1_port, 301 .init = initialize_usbh1_port,
309 .portsc = MXC_EHCI_MODE_ULPI, 302 .portsc = MXC_EHCI_MODE_ULPI,
310 .flags = (MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_ITC_NO_THRESHOLD),
311}; 303};
312 304
313static int otg_mode_host; 305static int otg_mode_host;
@@ -349,7 +341,7 @@ static const struct spi_imx_master mx51_babbage_spi_pdata __initconst = {
349/* 341/*
350 * Board specific initialization. 342 * Board specific initialization.
351 */ 343 */
352static void __init mxc_board_init(void) 344static void __init mx51_babbage_init(void)
353{ 345{
354 iomux_v3_cfg_t usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP; 346 iomux_v3_cfg_t usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP;
355 iomux_v3_cfg_t power_key = _MX51_PAD_EIM_A27__GPIO2_21 | 347 iomux_v3_cfg_t power_key = _MX51_PAD_EIM_A27__GPIO2_21 |
@@ -360,7 +352,11 @@ static void __init mxc_board_init(void)
360#endif 352#endif
361 mxc_iomux_v3_setup_multiple_pads(mx51babbage_pads, 353 mxc_iomux_v3_setup_multiple_pads(mx51babbage_pads,
362 ARRAY_SIZE(mx51babbage_pads)); 354 ARRAY_SIZE(mx51babbage_pads));
363 mxc_init_imx_uart(); 355
356 imx51_add_imx_uart(0, &uart_pdata);
357 imx51_add_imx_uart(1, &uart_pdata);
358 imx51_add_imx_uart(2, &uart_pdata);
359
364 babbage_fec_reset(); 360 babbage_fec_reset();
365 imx51_add_fec(NULL); 361 imx51_add_fec(NULL);
366 362
@@ -399,15 +395,16 @@ static void __init mx51_babbage_timer_init(void)
399 mx51_clocks_init(32768, 24000000, 22579200, 0); 395 mx51_clocks_init(32768, 24000000, 22579200, 0);
400} 396}
401 397
402static struct sys_timer mxc_timer = { 398static struct sys_timer mx51_babbage_timer = {
403 .init = mx51_babbage_timer_init, 399 .init = mx51_babbage_timer_init,
404}; 400};
405 401
406MACHINE_START(MX51_BABBAGE, "Freescale MX51 Babbage Board") 402MACHINE_START(MX51_BABBAGE, "Freescale MX51 Babbage Board")
407 /* Maintainer: Amit Kucheria <amit.kucheria@canonical.com> */ 403 /* Maintainer: Amit Kucheria <amit.kucheria@canonical.com> */
408 .boot_params = MX51_PHYS_OFFSET + 0x100, 404 .boot_params = MX51_PHYS_OFFSET + 0x100,
409 .map_io = mx51_map_io, 405 .map_io = mx51_map_io,
406 .init_early = imx51_init_early,
410 .init_irq = mx51_init_irq, 407 .init_irq = mx51_init_irq,
411 .init_machine = mxc_board_init, 408 .timer = &mx51_babbage_timer,
412 .timer = &mxc_timer, 409 .init_machine = mx51_babbage_init,
413MACHINE_END 410MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx51_efikamx.c b/arch/arm/mach-mx5/board-mx51_efikamx.c
index b7946f8e8d40..acab1911cb3c 100644
--- a/arch/arm/mach-mx5/board-mx51_efikamx.c
+++ b/arch/arm/mach-mx5/board-mx51_efikamx.c
@@ -25,6 +25,9 @@
25#include <linux/fsl_devices.h> 25#include <linux/fsl_devices.h>
26#include <linux/spi/flash.h> 26#include <linux/spi/flash.h>
27#include <linux/spi/spi.h> 27#include <linux/spi/spi.h>
28#include <linux/mfd/mc13892.h>
29#include <linux/regulator/machine.h>
30#include <linux/regulator/consumer.h>
28 31
29#include <mach/common.h> 32#include <mach/common.h>
30#include <mach/hardware.h> 33#include <mach/hardware.h>
@@ -40,8 +43,7 @@
40 43
41#include "devices-imx51.h" 44#include "devices-imx51.h"
42#include "devices.h" 45#include "devices.h"
43 46#include "efika.h"
44#define MX51_USB_PLL_DIV_24_MHZ 0x01
45 47
46#define EFIKAMX_PCBID0 IMX_GPIO_NR(3, 16) 48#define EFIKAMX_PCBID0 IMX_GPIO_NR(3, 16)
47#define EFIKAMX_PCBID1 IMX_GPIO_NR(3, 17) 49#define EFIKAMX_PCBID1 IMX_GPIO_NR(3, 17)
@@ -53,13 +55,14 @@
53 55
54#define EFIKAMX_POWER_KEY IMX_GPIO_NR(2, 31) 56#define EFIKAMX_POWER_KEY IMX_GPIO_NR(2, 31)
55 57
56#define EFIKAMX_SPI_CS0 IMX_GPIO_NR(4, 24)
57#define EFIKAMX_SPI_CS1 IMX_GPIO_NR(4, 25)
58
59/* board 1.1 doesn't have same reset gpio */ 58/* board 1.1 doesn't have same reset gpio */
60#define EFIKAMX_RESET1_1 IMX_GPIO_NR(3, 2) 59#define EFIKAMX_RESET1_1 IMX_GPIO_NR(3, 2)
61#define EFIKAMX_RESET IMX_GPIO_NR(1, 4) 60#define EFIKAMX_RESET IMX_GPIO_NR(1, 4)
62 61
62#define EFIKAMX_POWEROFF IMX_GPIO_NR(4, 13)
63
64#define EFIKAMX_PMIC IMX_GPIO_NR(1, 6)
65
63/* the pci ids pin have pull up. they're driven low according to board id */ 66/* the pci ids pin have pull up. they're driven low according to board id */
64#define MX51_PAD_PCBID0 IOMUX_PAD(0x518, 0x130, 3, 0x0, 0, PAD_CTL_PUS_100K_UP) 67#define MX51_PAD_PCBID0 IOMUX_PAD(0x518, 0x130, 3, 0x0, 0, PAD_CTL_PUS_100K_UP)
65#define MX51_PAD_PCBID1 IOMUX_PAD(0x51C, 0x134, 3, 0x0, 0, PAD_CTL_PUS_100K_UP) 68#define MX51_PAD_PCBID1 IOMUX_PAD(0x51C, 0x134, 3, 0x0, 0, PAD_CTL_PUS_100K_UP)
@@ -67,38 +70,11 @@
67#define MX51_PAD_PWRKEY IOMUX_PAD(0x48c, 0x0f8, 1, 0x0, 0, PAD_CTL_PUS_100K_UP | PAD_CTL_PKE) 70#define MX51_PAD_PWRKEY IOMUX_PAD(0x48c, 0x0f8, 1, 0x0, 0, PAD_CTL_PUS_100K_UP | PAD_CTL_PKE)
68 71
69static iomux_v3_cfg_t mx51efikamx_pads[] = { 72static iomux_v3_cfg_t mx51efikamx_pads[] = {
70 /* UART1 */
71 MX51_PAD_UART1_RXD__UART1_RXD,
72 MX51_PAD_UART1_TXD__UART1_TXD,
73 MX51_PAD_UART1_RTS__UART1_RTS,
74 MX51_PAD_UART1_CTS__UART1_CTS,
75 /* board id */ 73 /* board id */
76 MX51_PAD_PCBID0, 74 MX51_PAD_PCBID0,
77 MX51_PAD_PCBID1, 75 MX51_PAD_PCBID1,
78 MX51_PAD_PCBID2, 76 MX51_PAD_PCBID2,
79 77
80 /* SD 1 */
81 MX51_PAD_SD1_CMD__SD1_CMD,
82 MX51_PAD_SD1_CLK__SD1_CLK,
83 MX51_PAD_SD1_DATA0__SD1_DATA0,
84 MX51_PAD_SD1_DATA1__SD1_DATA1,
85 MX51_PAD_SD1_DATA2__SD1_DATA2,
86 MX51_PAD_SD1_DATA3__SD1_DATA3,
87
88 /* SD 2 */
89 MX51_PAD_SD2_CMD__SD2_CMD,
90 MX51_PAD_SD2_CLK__SD2_CLK,
91 MX51_PAD_SD2_DATA0__SD2_DATA0,
92 MX51_PAD_SD2_DATA1__SD2_DATA1,
93 MX51_PAD_SD2_DATA2__SD2_DATA2,
94 MX51_PAD_SD2_DATA3__SD2_DATA3,
95
96 /* SD/MMC WP/CD */
97 MX51_PAD_GPIO1_0__SD1_CD,
98 MX51_PAD_GPIO1_1__SD1_WP,
99 MX51_PAD_GPIO1_7__SD2_WP,
100 MX51_PAD_GPIO1_8__SD2_CD,
101
102 /* leds */ 78 /* leds */
103 MX51_PAD_CSI1_D9__GPIO3_13, 79 MX51_PAD_CSI1_D9__GPIO3_13,
104 MX51_PAD_CSI1_VSYNC__GPIO3_14, 80 MX51_PAD_CSI1_VSYNC__GPIO3_14,
@@ -107,64 +83,12 @@ static iomux_v3_cfg_t mx51efikamx_pads[] = {
107 /* power key */ 83 /* power key */
108 MX51_PAD_PWRKEY, 84 MX51_PAD_PWRKEY,
109 85
110 /* spi */
111 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
112 MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
113 MX51_PAD_CSPI1_SS0__GPIO4_24,
114 MX51_PAD_CSPI1_SS1__GPIO4_25,
115 MX51_PAD_CSPI1_RDY__ECSPI1_RDY,
116 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
117
118 /* reset */ 86 /* reset */
119 MX51_PAD_DI1_PIN13__GPIO3_2, 87 MX51_PAD_DI1_PIN13__GPIO3_2,
120 MX51_PAD_GPIO1_4__GPIO1_4, 88 MX51_PAD_GPIO1_4__GPIO1_4,
121};
122 89
123/* Serial ports */ 90 /* power off */
124#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE) 91 MX51_PAD_CSI2_VSYNC__GPIO4_13,
125static const struct imxuart_platform_data uart_pdata = {
126 .flags = IMXUART_HAVE_RTSCTS,
127};
128
129static inline void mxc_init_imx_uart(void)
130{
131 imx51_add_imx_uart(0, &uart_pdata);
132 imx51_add_imx_uart(1, &uart_pdata);
133 imx51_add_imx_uart(2, &uart_pdata);
134}
135#else /* !SERIAL_IMX */
136static inline void mxc_init_imx_uart(void)
137{
138}
139#endif /* SERIAL_IMX */
140
141/* This function is board specific as the bit mask for the plldiv will also
142 * be different for other Freescale SoCs, thus a common bitmask is not
143 * possible and cannot get place in /plat-mxc/ehci.c.
144 */
145static int initialize_otg_port(struct platform_device *pdev)
146{
147 u32 v;
148 void __iomem *usb_base;
149 void __iomem *usbother_base;
150 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
151 if (!usb_base)
152 return -ENOMEM;
153 usbother_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET);
154
155 /* Set the PHY clock to 19.2MHz */
156 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
157 v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
158 v |= MX51_USB_PLL_DIV_24_MHZ;
159 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
160 iounmap(usb_base);
161 return 0;
162}
163
164static struct mxc_usbh_platform_data dr_utmi_config = {
165 .init = initialize_otg_port,
166 .portsc = MXC_EHCI_UTMI_16BIT,
167 .flags = MXC_EHCI_INTERNAL_PHY,
168}; 92};
169 93
170/* PCBID2 PCBID1 PCBID0 STATE 94/* PCBID2 PCBID1 PCBID0 STATE
@@ -265,47 +189,6 @@ static const struct gpio_keys_platform_data mx51_efikamx_powerkey_data __initcon
265 .nbuttons = ARRAY_SIZE(mx51_efikamx_powerkey), 189 .nbuttons = ARRAY_SIZE(mx51_efikamx_powerkey),
266}; 190};
267 191
268static struct mtd_partition mx51_efikamx_spi_nor_partitions[] = {
269 {
270 .name = "u-boot",
271 .offset = 0,
272 .size = SZ_256K,
273 },
274 {
275 .name = "config",
276 .offset = MTDPART_OFS_APPEND,
277 .size = SZ_64K,
278 },
279};
280
281static struct flash_platform_data mx51_efikamx_spi_flash_data = {
282 .name = "spi_flash",
283 .parts = mx51_efikamx_spi_nor_partitions,
284 .nr_parts = ARRAY_SIZE(mx51_efikamx_spi_nor_partitions),
285 .type = "sst25vf032b",
286};
287
288static struct spi_board_info mx51_efikamx_spi_board_info[] __initdata = {
289 {
290 .modalias = "m25p80",
291 .max_speed_hz = 25000000,
292 .bus_num = 0,
293 .chip_select = 1,
294 .platform_data = &mx51_efikamx_spi_flash_data,
295 .irq = -1,
296 },
297};
298
299static int mx51_efikamx_spi_cs[] = {
300 EFIKAMX_SPI_CS0,
301 EFIKAMX_SPI_CS1,
302};
303
304static const struct spi_imx_master mx51_efikamx_spi_pdata __initconst = {
305 .chipselect = mx51_efikamx_spi_cs,
306 .num_chipselect = ARRAY_SIZE(mx51_efikamx_spi_cs),
307};
308
309void mx51_efikamx_reset(void) 192void mx51_efikamx_reset(void)
310{ 193{
311 if (system_rev == 0x11) 194 if (system_rev == 0x11)
@@ -314,14 +197,53 @@ void mx51_efikamx_reset(void)
314 gpio_direction_output(EFIKAMX_RESET, 0); 197 gpio_direction_output(EFIKAMX_RESET, 0);
315} 198}
316 199
317static void __init mxc_board_init(void) 200static struct regulator *pwgt1, *pwgt2, *coincell;
201
202static void mx51_efikamx_power_off(void)
203{
204 if (!IS_ERR(coincell))
205 regulator_disable(coincell);
206
207 if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) {
208 regulator_disable(pwgt2);
209 regulator_disable(pwgt1);
210 }
211 gpio_direction_output(EFIKAMX_POWEROFF, 1);
212}
213
214static int __init mx51_efikamx_power_init(void)
215{
216 if (machine_is_mx51_efikamx()) {
217 pwgt1 = regulator_get(NULL, "pwgt1");
218 pwgt2 = regulator_get(NULL, "pwgt2");
219 if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) {
220 regulator_enable(pwgt1);
221 regulator_enable(pwgt2);
222 }
223 gpio_request(EFIKAMX_POWEROFF, "poweroff");
224 pm_power_off = mx51_efikamx_power_off;
225
226 /* enable coincell charger. maybe need a small power driver ? */
227 coincell = regulator_get(NULL, "coincell");
228 if (!IS_ERR(coincell)) {
229 regulator_set_voltage(coincell, 3000000, 3000000);
230 regulator_enable(coincell);
231 }
232
233 regulator_has_full_constraints();
234 }
235
236 return 0;
237}
238late_initcall(mx51_efikamx_power_init);
239
240static void __init mx51_efikamx_init(void)
318{ 241{
319 mxc_iomux_v3_setup_multiple_pads(mx51efikamx_pads, 242 mxc_iomux_v3_setup_multiple_pads(mx51efikamx_pads,
320 ARRAY_SIZE(mx51efikamx_pads)); 243 ARRAY_SIZE(mx51efikamx_pads));
244 efika_board_common_init();
245
321 mx51_efikamx_board_id(); 246 mx51_efikamx_board_id();
322 mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
323 mxc_init_imx_uart();
324 imx51_add_sdhci_esdhc_imx(0, NULL);
325 247
326 /* on < 1.2 boards both SD controllers are used */ 248 /* on < 1.2 boards both SD controllers are used */
327 if (system_rev < 0x12) { 249 if (system_rev < 0x12) {
@@ -332,10 +254,6 @@ static void __init mxc_board_init(void)
332 platform_device_register(&mx51_efikamx_leds_device); 254 platform_device_register(&mx51_efikamx_leds_device);
333 imx51_add_gpio_keys(&mx51_efikamx_powerkey_data); 255 imx51_add_gpio_keys(&mx51_efikamx_powerkey_data);
334 256
335 spi_register_board_info(mx51_efikamx_spi_board_info,
336 ARRAY_SIZE(mx51_efikamx_spi_board_info));
337 imx51_add_ecspi(0, &mx51_efikamx_spi_pdata);
338
339 if (system_rev == 0x11) { 257 if (system_rev == 0x11) {
340 gpio_request(EFIKAMX_RESET1_1, "reset"); 258 gpio_request(EFIKAMX_RESET1_1, "reset");
341 gpio_direction_output(EFIKAMX_RESET1_1, 1); 259 gpio_direction_output(EFIKAMX_RESET1_1, 1);
@@ -343,6 +261,20 @@ static void __init mxc_board_init(void)
343 gpio_request(EFIKAMX_RESET, "reset"); 261 gpio_request(EFIKAMX_RESET, "reset");
344 gpio_direction_output(EFIKAMX_RESET, 1); 262 gpio_direction_output(EFIKAMX_RESET, 1);
345 } 263 }
264
265 /*
266 * enable wifi by default only on mx
267 * sb and mx have same wlan pin but the value to enable it are
268 * different :/
269 */
270 gpio_request(EFIKA_WLAN_EN, "wlan_en");
271 gpio_direction_output(EFIKA_WLAN_EN, 0);
272 msleep(10);
273
274 gpio_request(EFIKA_WLAN_RESET, "wlan_rst");
275 gpio_direction_output(EFIKA_WLAN_RESET, 0);
276 msleep(10);
277 gpio_set_value(EFIKA_WLAN_RESET, 1);
346} 278}
347 279
348static void __init mx51_efikamx_timer_init(void) 280static void __init mx51_efikamx_timer_init(void)
@@ -350,15 +282,16 @@ static void __init mx51_efikamx_timer_init(void)
350 mx51_clocks_init(32768, 24000000, 22579200, 24576000); 282 mx51_clocks_init(32768, 24000000, 22579200, 24576000);
351} 283}
352 284
353static struct sys_timer mxc_timer = { 285static struct sys_timer mx51_efikamx_timer = {
354 .init = mx51_efikamx_timer_init, 286 .init = mx51_efikamx_timer_init,
355}; 287};
356 288
357MACHINE_START(MX51_EFIKAMX, "Genesi EfikaMX nettop") 289MACHINE_START(MX51_EFIKAMX, "Genesi EfikaMX nettop")
358 /* Maintainer: Amit Kucheria <amit.kucheria@linaro.org> */ 290 /* Maintainer: Amit Kucheria <amit.kucheria@linaro.org> */
359 .boot_params = MX51_PHYS_OFFSET + 0x100, 291 .boot_params = MX51_PHYS_OFFSET + 0x100,
360 .map_io = mx51_map_io, 292 .map_io = mx51_map_io,
293 .init_early = imx51_init_early,
361 .init_irq = mx51_init_irq, 294 .init_irq = mx51_init_irq,
362 .init_machine = mxc_board_init, 295 .timer = &mx51_efikamx_timer,
363 .timer = &mxc_timer, 296 .init_machine = mx51_efikamx_init,
364MACHINE_END 297MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx51_efikasb.c b/arch/arm/mach-mx5/board-mx51_efikasb.c
new file mode 100644
index 000000000000..db04ce8462dc
--- /dev/null
+++ b/arch/arm/mach-mx5/board-mx51_efikasb.c
@@ -0,0 +1,283 @@
1/*
2 * Copyright (C) Arnaud Patard <arnaud.patard@rtp-net.org>
3 *
4 * based on code from the following
5 * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
6 * Copyright 2009-2010 Pegatron Corporation. All Rights Reserved.
7 * Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved.
8 *
9 * The code contained herein is licensed under the GNU General Public
10 * License. You may obtain a copy of the GNU General Public License
11 * Version 2 or later at the following locations:
12 *
13 * http://www.opensource.org/licenses/gpl-license.html
14 * http://www.gnu.org/copyleft/gpl.html
15 */
16
17#include <linux/init.h>
18#include <linux/platform_device.h>
19#include <linux/i2c.h>
20#include <linux/gpio.h>
21#include <linux/leds.h>
22#include <linux/input.h>
23#include <linux/delay.h>
24#include <linux/io.h>
25#include <linux/fsl_devices.h>
26#include <linux/spi/flash.h>
27#include <linux/spi/spi.h>
28#include <linux/mfd/mc13892.h>
29#include <linux/regulator/machine.h>
30#include <linux/regulator/consumer.h>
31#include <linux/usb/otg.h>
32#include <linux/usb/ulpi.h>
33#include <mach/ulpi.h>
34
35#include <mach/common.h>
36#include <mach/hardware.h>
37#include <mach/iomux-mx51.h>
38#include <mach/i2c.h>
39#include <mach/mxc_ehci.h>
40
41#include <asm/irq.h>
42#include <asm/setup.h>
43#include <asm/mach-types.h>
44#include <asm/mach/arch.h>
45#include <asm/mach/time.h>
46
47#include "devices-imx51.h"
48#include "devices.h"
49#include "efika.h"
50
51#define EFIKASB_USBH2_STP IMX_GPIO_NR(2, 20)
52#define EFIKASB_GREEN_LED IMX_GPIO_NR(1, 3)
53#define EFIKASB_WHITE_LED IMX_GPIO_NR(2, 25)
54#define EFIKASB_PCBID0 IMX_GPIO_NR(2, 28)
55#define EFIKASB_PCBID1 IMX_GPIO_NR(2, 29)
56#define EFIKASB_PWRKEY IMX_GPIO_NR(2, 31)
57#define EFIKASB_LID IMX_GPIO_NR(3, 14)
58#define EFIKASB_POWEROFF IMX_GPIO_NR(4, 13)
59#define EFIKASB_RFKILL IMX_GPIO_NR(3, 1)
60
61#define MX51_PAD_PWRKEY IOMUX_PAD(0x48c, 0x0f8, 1, 0x0, 0, PAD_CTL_PUS_100K_UP | PAD_CTL_PKE)
62
63static iomux_v3_cfg_t mx51efikasb_pads[] = {
64 /* USB HOST2 */
65 MX51_PAD_EIM_D16__USBH2_DATA0,
66 MX51_PAD_EIM_D17__USBH2_DATA1,
67 MX51_PAD_EIM_D18__USBH2_DATA2,
68 MX51_PAD_EIM_D19__USBH2_DATA3,
69 MX51_PAD_EIM_D20__USBH2_DATA4,
70 MX51_PAD_EIM_D21__USBH2_DATA5,
71 MX51_PAD_EIM_D22__USBH2_DATA6,
72 MX51_PAD_EIM_D23__USBH2_DATA7,
73 MX51_PAD_EIM_A24__USBH2_CLK,
74 MX51_PAD_EIM_A25__USBH2_DIR,
75 MX51_PAD_EIM_A26__USBH2_STP,
76 MX51_PAD_EIM_A27__USBH2_NXT,
77
78 /* leds */
79 MX51_PAD_EIM_CS0__GPIO2_25,
80 MX51_PAD_GPIO1_3__GPIO1_3,
81
82 /* pcb id */
83 MX51_PAD_EIM_CS3__GPIO2_28,
84 MX51_PAD_EIM_CS4__GPIO2_29,
85
86 /* lid */
87 MX51_PAD_CSI1_VSYNC__GPIO3_14,
88
89 /* power key*/
90 MX51_PAD_PWRKEY,
91
92 /* wifi/bt button */
93 MX51_PAD_DI1_PIN12__GPIO3_1,
94
95 /* power off */
96 MX51_PAD_CSI2_VSYNC__GPIO4_13,
97
98 /* wdog reset */
99 MX51_PAD_GPIO1_4__WDOG1_WDOG_B,
100
101 /* BT */
102 MX51_PAD_EIM_A17__GPIO2_11,
103};
104
105static int initialize_usbh2_port(struct platform_device *pdev)
106{
107 iomux_v3_cfg_t usbh2stp = MX51_PAD_EIM_A26__USBH2_STP;
108 iomux_v3_cfg_t usbh2gpio = MX51_PAD_EIM_A26__GPIO2_20;
109
110 mxc_iomux_v3_setup_pad(usbh2gpio);
111 gpio_request(EFIKASB_USBH2_STP, "usbh2_stp");
112 gpio_direction_output(EFIKASB_USBH2_STP, 0);
113 msleep(1);
114 gpio_set_value(EFIKASB_USBH2_STP, 1);
115 msleep(1);
116
117 gpio_free(EFIKASB_USBH2_STP);
118 mxc_iomux_v3_setup_pad(usbh2stp);
119
120 mdelay(10);
121
122 return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_ITC_NO_THRESHOLD);
123}
124
125static struct mxc_usbh_platform_data usbh2_config = {
126 .init = initialize_usbh2_port,
127 .portsc = MXC_EHCI_MODE_ULPI,
128};
129
130static void __init mx51_efikasb_usb(void)
131{
132 usbh2_config.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
133 ULPI_OTG_DRVVBUS_EXT | ULPI_OTG_EXTVBUSIND);
134 if (usbh2_config.otg)
135 mxc_register_device(&mxc_usbh2_device, &usbh2_config);
136}
137
138static struct gpio_led mx51_efikasb_leds[] = {
139 {
140 .name = "efikasb:green",
141 .default_trigger = "default-on",
142 .gpio = EFIKASB_GREEN_LED,
143 .active_low = 1,
144 },
145 {
146 .name = "efikasb:white",
147 .default_trigger = "caps",
148 .gpio = EFIKASB_WHITE_LED,
149 },
150};
151
152static struct gpio_led_platform_data mx51_efikasb_leds_data = {
153 .leds = mx51_efikasb_leds,
154 .num_leds = ARRAY_SIZE(mx51_efikasb_leds),
155};
156
157static struct platform_device mx51_efikasb_leds_device = {
158 .name = "leds-gpio",
159 .id = -1,
160 .dev = {
161 .platform_data = &mx51_efikasb_leds_data,
162 },
163};
164
165static struct gpio_keys_button mx51_efikasb_keys[] = {
166 {
167 .code = KEY_POWER,
168 .gpio = EFIKASB_PWRKEY,
169 .type = EV_PWR,
170 .desc = "Power Button",
171 .wakeup = 1,
172 .debounce_interval = 10, /* ms */
173 },
174 {
175 .code = SW_LID,
176 .gpio = EFIKASB_LID,
177 .type = EV_SW,
178 .desc = "Lid Switch",
179 },
180 {
181 /* SW_RFKILLALL vs KEY_RFKILL ? */
182 .code = SW_RFKILL_ALL,
183 .gpio = EFIKASB_RFKILL,
184 .type = EV_SW,
185 .desc = "rfkill",
186 },
187};
188
189static const struct gpio_keys_platform_data mx51_efikasb_keys_data __initconst = {
190 .buttons = mx51_efikasb_keys,
191 .nbuttons = ARRAY_SIZE(mx51_efikasb_keys),
192};
193
194static struct regulator *pwgt1, *pwgt2;
195
196static void mx51_efikasb_power_off(void)
197{
198 gpio_set_value(EFIKA_USB_PHY_RESET, 0);
199
200 if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) {
201 regulator_disable(pwgt2);
202 regulator_disable(pwgt1);
203 }
204 gpio_direction_output(EFIKASB_POWEROFF, 1);
205}
206
207static int __init mx51_efikasb_power_init(void)
208{
209 if (machine_is_mx51_efikasb()) {
210 pwgt1 = regulator_get(NULL, "pwgt1");
211 pwgt2 = regulator_get(NULL, "pwgt2");
212 if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) {
213 regulator_enable(pwgt1);
214 regulator_enable(pwgt2);
215 }
216 gpio_request(EFIKASB_POWEROFF, "poweroff");
217 pm_power_off = mx51_efikasb_power_off;
218
219 regulator_has_full_constraints();
220 }
221
222 return 0;
223}
224late_initcall(mx51_efikasb_power_init);
225
226/* 01 R1.3 board
227 10 R2.0 board */
228static void __init mx51_efikasb_board_id(void)
229{
230 int id;
231
232 gpio_request(EFIKASB_PCBID0, "pcb id0");
233 gpio_direction_input(EFIKASB_PCBID0);
234 gpio_request(EFIKASB_PCBID1, "pcb id1");
235 gpio_direction_input(EFIKASB_PCBID1);
236
237 id = gpio_get_value(EFIKASB_PCBID0);
238 id |= gpio_get_value(EFIKASB_PCBID1) << 1;
239
240 switch (id) {
241 default:
242 break;
243 case 1:
244 system_rev = 0x13;
245 break;
246 case 2:
247 system_rev = 0x20;
248 break;
249 }
250}
251
252static void __init efikasb_board_init(void)
253{
254 mxc_iomux_v3_setup_multiple_pads(mx51efikasb_pads,
255 ARRAY_SIZE(mx51efikasb_pads));
256 efika_board_common_init();
257
258 mx51_efikasb_board_id();
259 mx51_efikasb_usb();
260 imx51_add_sdhci_esdhc_imx(1, NULL);
261
262 platform_device_register(&mx51_efikasb_leds_device);
263 imx51_add_gpio_keys(&mx51_efikasb_keys_data);
264
265}
266
267static void __init mx51_efikasb_timer_init(void)
268{
269 mx51_clocks_init(32768, 24000000, 22579200, 24576000);
270}
271
272static struct sys_timer mx51_efikasb_timer = {
273 .init = mx51_efikasb_timer_init,
274};
275
276MACHINE_START(MX51_EFIKASB, "Genesi Efika Smartbook")
277 .boot_params = MX51_PHYS_OFFSET + 0x100,
278 .map_io = mx51_map_io,
279 .init_early = imx51_init_early,
280 .init_irq = mx51_init_irq,
281 .init_machine = efikasb_board_init,
282 .timer = &mx51_efikasb_timer,
283MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx53_evk.c b/arch/arm/mach-mx5/board-mx53_evk.c
index caee04c08238..7b5735c5ea59 100644
--- a/arch/arm/mach-mx5/board-mx53_evk.c
+++ b/arch/arm/mach-mx5/board-mx53_evk.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. 2 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2010 Yong Shen. <Yong.Shen@linaro.org> 3 * Copyright (C) 2010 Yong Shen. <Yong.Shen@linaro.org>
4 */ 4 */
5 5
@@ -42,28 +42,24 @@
42#include "devices-imx53.h" 42#include "devices-imx53.h"
43 43
44static iomux_v3_cfg_t mx53_evk_pads[] = { 44static iomux_v3_cfg_t mx53_evk_pads[] = {
45 MX53_PAD_CSI0_D10__UART1_TXD, 45 MX53_PAD_CSI0_DAT10__UART1_TXD_MUX,
46 MX53_PAD_CSI0_D11__UART1_RXD, 46 MX53_PAD_CSI0_DAT11__UART1_RXD_MUX,
47 MX53_PAD_ATA_DIOW__UART1_TXD,
48 MX53_PAD_ATA_DMACK__UART1_RXD,
49 47
50 MX53_PAD_ATA_BUFFER_EN__UART2_RXD, 48 MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
51 MX53_PAD_ATA_DMARQ__UART2_TXD, 49 MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
52 MX53_PAD_ATA_DIOR__UART2_RTS, 50 MX53_PAD_PATA_DIOR__UART2_RTS,
53 MX53_PAD_ATA_INTRQ__UART2_CTS, 51 MX53_PAD_PATA_INTRQ__UART2_CTS,
54 52
55 MX53_PAD_ATA_CS_0__UART3_TXD, 53 MX53_PAD_PATA_CS_0__UART3_TXD_MUX,
56 MX53_PAD_ATA_CS_1__UART3_RXD, 54 MX53_PAD_PATA_CS_1__UART3_RXD_MUX,
57 MX53_PAD_ATA_DA_1__UART3_CTS,
58 MX53_PAD_ATA_DA_2__UART3_RTS,
59 55
60 MX53_PAD_EIM_D16__CSPI1_SCLK, 56 MX53_PAD_EIM_D16__ECSPI1_SCLK,
61 MX53_PAD_EIM_D17__CSPI1_MISO, 57 MX53_PAD_EIM_D17__ECSPI1_MISO,
62 MX53_PAD_EIM_D18__CSPI1_MOSI, 58 MX53_PAD_EIM_D18__ECSPI1_MOSI,
63 59
64 /* ecspi chip select lines */ 60 /* ecspi chip select lines */
65 MX53_PAD_EIM_EB2__GPIO_2_30, 61 MX53_PAD_EIM_EB2__GPIO2_30,
66 MX53_PAD_EIM_D19__GPIO_3_19, 62 MX53_PAD_EIM_D19__GPIO3_19,
67}; 63};
68 64
69static const struct imxuart_platform_data mx53_evk_uart_pdata __initconst = { 65static const struct imxuart_platform_data mx53_evk_uart_pdata __initconst = {
@@ -72,9 +68,9 @@ static const struct imxuart_platform_data mx53_evk_uart_pdata __initconst = {
72 68
73static inline void mx53_evk_init_uart(void) 69static inline void mx53_evk_init_uart(void)
74{ 70{
75 imx53_add_imx_uart(0, &mx53_evk_uart_pdata); 71 imx53_add_imx_uart(0, NULL);
76 imx53_add_imx_uart(1, &mx53_evk_uart_pdata); 72 imx53_add_imx_uart(1, &mx53_evk_uart_pdata);
77 imx53_add_imx_uart(2, &mx53_evk_uart_pdata); 73 imx53_add_imx_uart(2, NULL);
78} 74}
79 75
80static const struct imxi2c_platform_data mx53_evk_i2c_data __initconst = { 76static const struct imxi2c_platform_data mx53_evk_i2c_data __initconst = {
@@ -139,6 +135,7 @@ static void __init mx53_evk_board_init(void)
139 spi_register_board_info(mx53_evk_spi_board_info, 135 spi_register_board_info(mx53_evk_spi_board_info,
140 ARRAY_SIZE(mx53_evk_spi_board_info)); 136 ARRAY_SIZE(mx53_evk_spi_board_info));
141 imx53_add_ecspi(0, &mx53_evk_spi_data); 137 imx53_add_ecspi(0, &mx53_evk_spi_data);
138 imx53_add_imx2_wdt(0, NULL);
142} 139}
143 140
144static void __init mx53_evk_timer_init(void) 141static void __init mx53_evk_timer_init(void)
@@ -152,7 +149,8 @@ static struct sys_timer mx53_evk_timer = {
152 149
153MACHINE_START(MX53_EVK, "Freescale MX53 EVK Board") 150MACHINE_START(MX53_EVK, "Freescale MX53 EVK Board")
154 .map_io = mx53_map_io, 151 .map_io = mx53_map_io,
152 .init_early = imx53_init_early,
155 .init_irq = mx53_init_irq, 153 .init_irq = mx53_init_irq,
156 .init_machine = mx53_evk_board_init,
157 .timer = &mx53_evk_timer, 154 .timer = &mx53_evk_timer,
155 .init_machine = mx53_evk_board_init,
158MACHINE_END 156MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx53_loco.c b/arch/arm/mach-mx5/board-mx53_loco.c
index d1348e04ace3..0a18f8d23eb0 100644
--- a/arch/arm/mach-mx5/board-mx53_loco.c
+++ b/arch/arm/mach-mx5/board-mx53_loco.c
@@ -39,33 +39,147 @@
39#define LOCO_FEC_PHY_RST IMX_GPIO_NR(7, 6) 39#define LOCO_FEC_PHY_RST IMX_GPIO_NR(7, 6)
40 40
41static iomux_v3_cfg_t mx53_loco_pads[] = { 41static iomux_v3_cfg_t mx53_loco_pads[] = {
42 MX53_PAD_CSI0_D10__UART1_TXD, 42 /* FEC */
43 MX53_PAD_CSI0_D11__UART1_RXD, 43 MX53_PAD_FEC_MDC__FEC_MDC,
44 MX53_PAD_ATA_DIOW__UART1_TXD, 44 MX53_PAD_FEC_MDIO__FEC_MDIO,
45 MX53_PAD_ATA_DMACK__UART1_RXD, 45 MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
46 46 MX53_PAD_FEC_RX_ER__FEC_RX_ER,
47 MX53_PAD_ATA_BUFFER_EN__UART2_RXD, 47 MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
48 MX53_PAD_ATA_DMARQ__UART2_TXD, 48 MX53_PAD_FEC_RXD1__FEC_RDATA_1,
49 MX53_PAD_ATA_DIOR__UART2_RTS, 49 MX53_PAD_FEC_RXD0__FEC_RDATA_0,
50 MX53_PAD_ATA_INTRQ__UART2_CTS, 50 MX53_PAD_FEC_TX_EN__FEC_TX_EN,
51 51 MX53_PAD_FEC_TXD1__FEC_TDATA_1,
52 MX53_PAD_ATA_CS_0__UART3_TXD, 52 MX53_PAD_FEC_TXD0__FEC_TDATA_0,
53 MX53_PAD_ATA_CS_1__UART3_RXD, 53 /* FEC_nRST */
54 MX53_PAD_ATA_DA_1__UART3_CTS, 54 MX53_PAD_PATA_DA_0__GPIO7_6,
55 MX53_PAD_ATA_DA_2__UART3_RTS, 55 /* FEC_nINT */
56 MX53_PAD_PATA_DATA4__GPIO2_4,
57 /* AUDMUX5 */
58 MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC,
59 MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD,
60 MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS,
61 MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD,
62 /* I2C2 */
63 MX53_PAD_KEY_COL3__I2C2_SCL,
64 MX53_PAD_KEY_ROW3__I2C2_SDA,
65 /* SD1 */
66 MX53_PAD_SD1_CMD__ESDHC1_CMD,
67 MX53_PAD_SD1_CLK__ESDHC1_CLK,
68 MX53_PAD_SD1_DATA0__ESDHC1_DAT0,
69 MX53_PAD_SD1_DATA1__ESDHC1_DAT1,
70 MX53_PAD_SD1_DATA2__ESDHC1_DAT2,
71 MX53_PAD_SD1_DATA3__ESDHC1_DAT3,
72 /* SD3 */
73 MX53_PAD_PATA_DATA8__ESDHC3_DAT0,
74 MX53_PAD_PATA_DATA9__ESDHC3_DAT1,
75 MX53_PAD_PATA_DATA10__ESDHC3_DAT2,
76 MX53_PAD_PATA_DATA11__ESDHC3_DAT3,
77 MX53_PAD_PATA_DATA0__ESDHC3_DAT4,
78 MX53_PAD_PATA_DATA1__ESDHC3_DAT5,
79 MX53_PAD_PATA_DATA2__ESDHC3_DAT6,
80 MX53_PAD_PATA_DATA3__ESDHC3_DAT7,
81 MX53_PAD_PATA_IORDY__ESDHC3_CLK,
82 MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
83 /* SD3_CD */
84 MX53_PAD_EIM_DA11__GPIO3_11,
85 /* SD3_WP */
86 MX53_PAD_EIM_DA12__GPIO3_12,
87 /* VGA */
88 MX53_PAD_EIM_OE__IPU_DI1_PIN7,
89 MX53_PAD_EIM_RW__IPU_DI1_PIN8,
90 /* DISPLB */
91 MX53_PAD_EIM_D20__IPU_SER_DISP0_CS,
92 MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK,
93 MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN,
94 MX53_PAD_EIM_D23__IPU_DI0_D0_CS,
95 /* DISP0_POWER_EN */
96 MX53_PAD_EIM_D24__GPIO3_24,
97 /* DISP0 DET INT */
98 MX53_PAD_EIM_D31__GPIO3_31,
99 /* LVDS */
100 MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3,
101 MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK,
102 MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2,
103 MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1,
104 MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0,
105 MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3,
106 MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2,
107 MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK,
108 MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1,
109 MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0,
110 /* I2C1 */
111 MX53_PAD_CSI0_DAT8__I2C1_SDA,
112 MX53_PAD_CSI0_DAT9__I2C1_SCL,
113 /* UART1 */
114 MX53_PAD_CSI0_DAT10__UART1_TXD_MUX,
115 MX53_PAD_CSI0_DAT11__UART1_RXD_MUX,
116 /* CSI0 */
117 MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12,
118 MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13,
119 MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14,
120 MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15,
121 MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16,
122 MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17,
123 MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18,
124 MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19,
125 MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC,
126 MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC,
127 MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK,
128 /* DISPLAY */
129 MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK,
130 MX53_PAD_DI0_PIN15__IPU_DI0_PIN15,
131 MX53_PAD_DI0_PIN2__IPU_DI0_PIN2,
132 MX53_PAD_DI0_PIN3__IPU_DI0_PIN3,
133 MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0,
134 MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1,
135 MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2,
136 MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3,
137 MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4,
138 MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5,
139 MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6,
140 MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7,
141 MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8,
142 MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9,
143 MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10,
144 MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11,
145 MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12,
146 MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13,
147 MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14,
148 MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15,
149 MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16,
150 MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17,
151 MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18,
152 MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19,
153 MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20,
154 MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21,
155 MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22,
156 MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23,
157 /* Audio CLK*/
158 MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK,
159 /* PWM */
160 MX53_PAD_GPIO_1__PWM2_PWMO,
161 /* SPDIF */
162 MX53_PAD_GPIO_7__SPDIF_PLOCK,
163 MX53_PAD_GPIO_17__SPDIF_OUT1,
164 /* GPIO */
165 MX53_PAD_PATA_DA_1__GPIO7_7,
166 MX53_PAD_PATA_DA_2__GPIO7_8,
167 MX53_PAD_PATA_DATA5__GPIO2_5,
168 MX53_PAD_PATA_DATA6__GPIO2_6,
169 MX53_PAD_PATA_DATA14__GPIO2_14,
170 MX53_PAD_PATA_DATA15__GPIO2_15,
171 MX53_PAD_PATA_INTRQ__GPIO7_2,
172 MX53_PAD_EIM_WAIT__GPIO5_0,
173 MX53_PAD_NANDF_WP_B__GPIO6_9,
174 MX53_PAD_NANDF_RB0__GPIO6_10,
175 MX53_PAD_NANDF_CS1__GPIO6_14,
176 MX53_PAD_NANDF_CS2__GPIO6_15,
177 MX53_PAD_NANDF_CS3__GPIO6_16,
178 MX53_PAD_GPIO_5__GPIO1_5,
179 MX53_PAD_GPIO_16__GPIO7_11,
180 MX53_PAD_GPIO_8__GPIO1_8,
56}; 181};
57 182
58static const struct imxuart_platform_data mx53_loco_uart_data __initconst = {
59 .flags = IMXUART_HAVE_RTSCTS,
60};
61
62static inline void mx53_loco_init_uart(void)
63{
64 imx53_add_imx_uart(0, &mx53_loco_uart_data);
65 imx53_add_imx_uart(1, &mx53_loco_uart_data);
66 imx53_add_imx_uart(2, &mx53_loco_uart_data);
67}
68
69static inline void mx53_loco_fec_reset(void) 183static inline void mx53_loco_fec_reset(void)
70{ 184{
71 int ret; 185 int ret;
@@ -85,13 +199,22 @@ static struct fec_platform_data mx53_loco_fec_data = {
85 .phy = PHY_INTERFACE_MODE_RMII, 199 .phy = PHY_INTERFACE_MODE_RMII,
86}; 200};
87 201
202static const struct imxi2c_platform_data mx53_loco_i2c_data __initconst = {
203 .bitrate = 100000,
204};
205
88static void __init mx53_loco_board_init(void) 206static void __init mx53_loco_board_init(void)
89{ 207{
90 mxc_iomux_v3_setup_multiple_pads(mx53_loco_pads, 208 mxc_iomux_v3_setup_multiple_pads(mx53_loco_pads,
91 ARRAY_SIZE(mx53_loco_pads)); 209 ARRAY_SIZE(mx53_loco_pads));
92 mx53_loco_init_uart(); 210 imx53_add_imx_uart(0, NULL);
93 mx53_loco_fec_reset(); 211 mx53_loco_fec_reset();
94 imx53_add_fec(&mx53_loco_fec_data); 212 imx53_add_fec(&mx53_loco_fec_data);
213 imx53_add_imx2_wdt(0, NULL);
214 imx53_add_imx_i2c(0, &mx53_loco_i2c_data);
215 imx53_add_imx_i2c(1, &mx53_loco_i2c_data);
216 imx53_add_sdhci_esdhc_imx(0, NULL);
217 imx53_add_sdhci_esdhc_imx(2, NULL);
95} 218}
96 219
97static void __init mx53_loco_timer_init(void) 220static void __init mx53_loco_timer_init(void)
@@ -105,7 +228,8 @@ static struct sys_timer mx53_loco_timer = {
105 228
106MACHINE_START(MX53_LOCO, "Freescale MX53 LOCO Board") 229MACHINE_START(MX53_LOCO, "Freescale MX53 LOCO Board")
107 .map_io = mx53_map_io, 230 .map_io = mx53_map_io,
231 .init_early = imx53_init_early,
108 .init_irq = mx53_init_irq, 232 .init_irq = mx53_init_irq,
109 .init_machine = mx53_loco_board_init,
110 .timer = &mx53_loco_timer, 233 .timer = &mx53_loco_timer,
234 .init_machine = mx53_loco_board_init,
111MACHINE_END 235MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx53_smd.c b/arch/arm/mach-mx5/board-mx53_smd.c
index 7970f7a48588..31e173267edf 100644
--- a/arch/arm/mach-mx5/board-mx53_smd.c
+++ b/arch/arm/mach-mx5/board-mx53_smd.c
@@ -39,20 +39,19 @@
39#define SMD_FEC_PHY_RST IMX_GPIO_NR(7, 6) 39#define SMD_FEC_PHY_RST IMX_GPIO_NR(7, 6)
40 40
41static iomux_v3_cfg_t mx53_smd_pads[] = { 41static iomux_v3_cfg_t mx53_smd_pads[] = {
42 MX53_PAD_CSI0_D10__UART1_TXD, 42 MX53_PAD_CSI0_DAT10__UART1_TXD_MUX,
43 MX53_PAD_CSI0_D11__UART1_RXD, 43 MX53_PAD_CSI0_DAT11__UART1_RXD_MUX,
44 MX53_PAD_ATA_DIOW__UART1_TXD, 44
45 MX53_PAD_ATA_DMACK__UART1_RXD, 45 MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
46 46 MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
47 MX53_PAD_ATA_BUFFER_EN__UART2_RXD, 47
48 MX53_PAD_ATA_DMARQ__UART2_TXD, 48 MX53_PAD_PATA_CS_0__UART3_TXD_MUX,
49 MX53_PAD_ATA_DIOR__UART2_RTS, 49 MX53_PAD_PATA_CS_1__UART3_RXD_MUX,
50 MX53_PAD_ATA_INTRQ__UART2_CTS, 50 MX53_PAD_PATA_DA_1__UART3_CTS,
51 51 MX53_PAD_PATA_DA_2__UART3_RTS,
52 MX53_PAD_ATA_CS_0__UART3_TXD, 52 /* I2C1 */
53 MX53_PAD_ATA_CS_1__UART3_RXD, 53 MX53_PAD_CSI0_DAT8__I2C1_SDA,
54 MX53_PAD_ATA_DA_1__UART3_CTS, 54 MX53_PAD_CSI0_DAT9__I2C1_SCL,
55 MX53_PAD_ATA_DA_2__UART3_RTS,
56}; 55};
57 56
58static const struct imxuart_platform_data mx53_smd_uart_data __initconst = { 57static const struct imxuart_platform_data mx53_smd_uart_data __initconst = {
@@ -61,8 +60,8 @@ static const struct imxuart_platform_data mx53_smd_uart_data __initconst = {
61 60
62static inline void mx53_smd_init_uart(void) 61static inline void mx53_smd_init_uart(void)
63{ 62{
64 imx53_add_imx_uart(0, &mx53_smd_uart_data); 63 imx53_add_imx_uart(0, NULL);
65 imx53_add_imx_uart(1, &mx53_smd_uart_data); 64 imx53_add_imx_uart(1, NULL);
66 imx53_add_imx_uart(2, &mx53_smd_uart_data); 65 imx53_add_imx_uart(2, &mx53_smd_uart_data);
67} 66}
68 67
@@ -85,6 +84,10 @@ static struct fec_platform_data mx53_smd_fec_data = {
85 .phy = PHY_INTERFACE_MODE_RMII, 84 .phy = PHY_INTERFACE_MODE_RMII,
86}; 85};
87 86
87static const struct imxi2c_platform_data mx53_smd_i2c_data __initconst = {
88 .bitrate = 100000,
89};
90
88static void __init mx53_smd_board_init(void) 91static void __init mx53_smd_board_init(void)
89{ 92{
90 mxc_iomux_v3_setup_multiple_pads(mx53_smd_pads, 93 mxc_iomux_v3_setup_multiple_pads(mx53_smd_pads,
@@ -92,6 +95,8 @@ static void __init mx53_smd_board_init(void)
92 mx53_smd_init_uart(); 95 mx53_smd_init_uart();
93 mx53_smd_fec_reset(); 96 mx53_smd_fec_reset();
94 imx53_add_fec(&mx53_smd_fec_data); 97 imx53_add_fec(&mx53_smd_fec_data);
98 imx53_add_imx2_wdt(0, NULL);
99 imx53_add_imx_i2c(0, &mx53_smd_i2c_data);
95} 100}
96 101
97static void __init mx53_smd_timer_init(void) 102static void __init mx53_smd_timer_init(void)
@@ -105,7 +110,8 @@ static struct sys_timer mx53_smd_timer = {
105 110
106MACHINE_START(MX53_SMD, "Freescale MX53 SMD Board") 111MACHINE_START(MX53_SMD, "Freescale MX53 SMD Board")
107 .map_io = mx53_map_io, 112 .map_io = mx53_map_io,
113 .init_early = imx53_init_early,
108 .init_irq = mx53_init_irq, 114 .init_irq = mx53_init_irq,
109 .init_machine = mx53_smd_board_init,
110 .timer = &mx53_smd_timer, 115 .timer = &mx53_smd_timer,
116 .init_machine = mx53_smd_board_init,
111MACHINE_END 117MACHINE_END
diff --git a/arch/arm/mach-mx5/clock-mx51-mx53.c b/arch/arm/mach-mx5/clock-mx51-mx53.c
index 0a19e7567c0b..652ace413825 100644
--- a/arch/arm/mach-mx5/clock-mx51-mx53.c
+++ b/arch/arm/mach-mx5/clock-mx51-mx53.c
@@ -42,6 +42,9 @@ static struct clk usboh3_clk;
42static struct clk emi_fast_clk; 42static struct clk emi_fast_clk;
43static struct clk ipu_clk; 43static struct clk ipu_clk;
44static struct clk mipi_hsc1_clk; 44static struct clk mipi_hsc1_clk;
45static struct clk esdhc1_clk;
46static struct clk esdhc2_clk;
47static struct clk esdhc3_mx53_clk;
45 48
46#define MAX_DPLL_WAIT_TRIES 1000 /* 1000 * udelay(1) = 1ms */ 49#define MAX_DPLL_WAIT_TRIES 1000 /* 1000 * udelay(1) = 1ms */
47 50
@@ -867,10 +870,6 @@ static struct clk gpt_32k_clk = {
867 .parent = &ckil_clk, 870 .parent = &ckil_clk,
868}; 871};
869 872
870static struct clk kpp_clk = {
871 .id = 0,
872};
873
874static struct clk dummy_clk = { 873static struct clk dummy_clk = {
875 .id = 0, 874 .id = 0,
876}; 875};
@@ -1147,10 +1146,80 @@ CLK_GET_RATE(esdhc1, 1, ESDHC1_MSHC1)
1147CLK_SET_PARENT(esdhc1, 1, ESDHC1_MSHC1) 1146CLK_SET_PARENT(esdhc1, 1, ESDHC1_MSHC1)
1148CLK_SET_RATE(esdhc1, 1, ESDHC1_MSHC1) 1147CLK_SET_RATE(esdhc1, 1, ESDHC1_MSHC1)
1149 1148
1149/* mx51 specific */
1150CLK_GET_RATE(esdhc2, 1, ESDHC2_MSHC2) 1150CLK_GET_RATE(esdhc2, 1, ESDHC2_MSHC2)
1151CLK_SET_PARENT(esdhc2, 1, ESDHC2_MSHC2) 1151CLK_SET_PARENT(esdhc2, 1, ESDHC2_MSHC2)
1152CLK_SET_RATE(esdhc2, 1, ESDHC2_MSHC2) 1152CLK_SET_RATE(esdhc2, 1, ESDHC2_MSHC2)
1153 1153
1154static int clk_esdhc3_set_parent(struct clk *clk, struct clk *parent)
1155{
1156 u32 reg;
1157
1158 reg = __raw_readl(MXC_CCM_CSCMR1);
1159 if (parent == &esdhc1_clk)
1160 reg &= ~MXC_CCM_CSCMR1_ESDHC3_CLK_SEL;
1161 else if (parent == &esdhc2_clk)
1162 reg |= MXC_CCM_CSCMR1_ESDHC3_CLK_SEL;
1163 else
1164 return -EINVAL;
1165 __raw_writel(reg, MXC_CCM_CSCMR1);
1166
1167 return 0;
1168}
1169
1170static int clk_esdhc4_set_parent(struct clk *clk, struct clk *parent)
1171{
1172 u32 reg;
1173
1174 reg = __raw_readl(MXC_CCM_CSCMR1);
1175 if (parent == &esdhc1_clk)
1176 reg &= ~MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
1177 else if (parent == &esdhc2_clk)
1178 reg |= MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
1179 else
1180 return -EINVAL;
1181 __raw_writel(reg, MXC_CCM_CSCMR1);
1182
1183 return 0;
1184}
1185
1186/* mx53 specific */
1187static int clk_esdhc2_mx53_set_parent(struct clk *clk, struct clk *parent)
1188{
1189 u32 reg;
1190
1191 reg = __raw_readl(MXC_CCM_CSCMR1);
1192 if (parent == &esdhc1_clk)
1193 reg &= ~MXC_CCM_CSCMR1_ESDHC2_MSHC2_MX53_CLK_SEL;
1194 else if (parent == &esdhc3_mx53_clk)
1195 reg |= MXC_CCM_CSCMR1_ESDHC2_MSHC2_MX53_CLK_SEL;
1196 else
1197 return -EINVAL;
1198 __raw_writel(reg, MXC_CCM_CSCMR1);
1199
1200 return 0;
1201}
1202
1203CLK_GET_RATE(esdhc3_mx53, 1, ESDHC3_MX53)
1204CLK_SET_PARENT(esdhc3_mx53, 1, ESDHC3_MX53)
1205CLK_SET_RATE(esdhc3_mx53, 1, ESDHC3_MX53)
1206
1207static int clk_esdhc4_mx53_set_parent(struct clk *clk, struct clk *parent)
1208{
1209 u32 reg;
1210
1211 reg = __raw_readl(MXC_CCM_CSCMR1);
1212 if (parent == &esdhc1_clk)
1213 reg &= ~MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
1214 else if (parent == &esdhc3_mx53_clk)
1215 reg |= MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
1216 else
1217 return -EINVAL;
1218 __raw_writel(reg, MXC_CCM_CSCMR1);
1219
1220 return 0;
1221}
1222
1154#define DEFINE_CLOCK_FULL(name, i, er, es, gr, sr, e, d, p, s) \ 1223#define DEFINE_CLOCK_FULL(name, i, er, es, gr, sr, e, d, p, s) \
1155 static struct clk name = { \ 1224 static struct clk name = { \
1156 .id = i, \ 1225 .id = i, \
@@ -1255,9 +1324,62 @@ DEFINE_CLOCK_MAX(esdhc1_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG1_OFFSET,
1255 clk_esdhc1, &pll2_sw_clk, &esdhc1_ipg_clk); 1324 clk_esdhc1, &pll2_sw_clk, &esdhc1_ipg_clk);
1256DEFINE_CLOCK_FULL(esdhc2_ipg_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG2_OFFSET, 1325DEFINE_CLOCK_FULL(esdhc2_ipg_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG2_OFFSET,
1257 NULL, NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL); 1326 NULL, NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL);
1327DEFINE_CLOCK_FULL(esdhc3_ipg_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG4_OFFSET,
1328 NULL, NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL);
1329DEFINE_CLOCK_FULL(esdhc4_ipg_clk, 3, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG6_OFFSET,
1330 NULL, NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL);
1331
1332/* mx51 specific */
1258DEFINE_CLOCK_MAX(esdhc2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG3_OFFSET, 1333DEFINE_CLOCK_MAX(esdhc2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG3_OFFSET,
1259 clk_esdhc2, &pll2_sw_clk, &esdhc2_ipg_clk); 1334 clk_esdhc2, &pll2_sw_clk, &esdhc2_ipg_clk);
1260 1335
1336static struct clk esdhc3_clk = {
1337 .id = 2,
1338 .parent = &esdhc1_clk,
1339 .set_parent = clk_esdhc3_set_parent,
1340 .enable_reg = MXC_CCM_CCGR3,
1341 .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
1342 .enable = _clk_max_enable,
1343 .disable = _clk_max_disable,
1344 .secondary = &esdhc3_ipg_clk,
1345};
1346static struct clk esdhc4_clk = {
1347 .id = 3,
1348 .parent = &esdhc1_clk,
1349 .set_parent = clk_esdhc4_set_parent,
1350 .enable_reg = MXC_CCM_CCGR3,
1351 .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
1352 .enable = _clk_max_enable,
1353 .disable = _clk_max_disable,
1354 .secondary = &esdhc4_ipg_clk,
1355};
1356
1357/* mx53 specific */
1358static struct clk esdhc2_mx53_clk = {
1359 .id = 2,
1360 .parent = &esdhc1_clk,
1361 .set_parent = clk_esdhc2_mx53_set_parent,
1362 .enable_reg = MXC_CCM_CCGR3,
1363 .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
1364 .enable = _clk_max_enable,
1365 .disable = _clk_max_disable,
1366 .secondary = &esdhc3_ipg_clk,
1367};
1368
1369DEFINE_CLOCK_MAX(esdhc3_mx53_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG5_OFFSET,
1370 clk_esdhc3_mx53, &pll2_sw_clk, &esdhc2_ipg_clk);
1371
1372static struct clk esdhc4_mx53_clk = {
1373 .id = 3,
1374 .parent = &esdhc1_clk,
1375 .set_parent = clk_esdhc4_mx53_set_parent,
1376 .enable_reg = MXC_CCM_CCGR3,
1377 .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
1378 .enable = _clk_max_enable,
1379 .disable = _clk_max_disable,
1380 .secondary = &esdhc4_ipg_clk,
1381};
1382
1261DEFINE_CLOCK(mipi_esc_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG5_OFFSET, NULL, NULL, NULL, &pll2_sw_clk); 1383DEFINE_CLOCK(mipi_esc_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG5_OFFSET, NULL, NULL, NULL, &pll2_sw_clk);
1262DEFINE_CLOCK(mipi_hsc2_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG4_OFFSET, NULL, NULL, &mipi_esc_clk, &pll2_sw_clk); 1384DEFINE_CLOCK(mipi_hsc2_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG4_OFFSET, NULL, NULL, &mipi_esc_clk, &pll2_sw_clk);
1263DEFINE_CLOCK(mipi_hsc1_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG3_OFFSET, NULL, NULL, &mipi_hsc2_clk, &pll2_sw_clk); 1385DEFINE_CLOCK(mipi_hsc1_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG3_OFFSET, NULL, NULL, &mipi_hsc2_clk, &pll2_sw_clk);
@@ -1302,7 +1424,7 @@ static struct clk_lookup mx51_lookups[] = {
1302 _REGISTER_CLOCK("mxc-ehci.2", "usb_ahb", usb_ahb_clk) 1424 _REGISTER_CLOCK("mxc-ehci.2", "usb_ahb", usb_ahb_clk)
1303 _REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk) 1425 _REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk)
1304 _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk) 1426 _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk)
1305 _REGISTER_CLOCK("imx-keypad", NULL, kpp_clk) 1427 _REGISTER_CLOCK("imx-keypad", NULL, dummy_clk)
1306 _REGISTER_CLOCK("mxc_nand", NULL, nfc_clk) 1428 _REGISTER_CLOCK("mxc_nand", NULL, nfc_clk)
1307 _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk) 1429 _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
1308 _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk) 1430 _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
@@ -1316,6 +1438,8 @@ static struct clk_lookup mx51_lookups[] = {
1316 _REGISTER_CLOCK("imx51-cspi.0", NULL, cspi_clk) 1438 _REGISTER_CLOCK("imx51-cspi.0", NULL, cspi_clk)
1317 _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk) 1439 _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk)
1318 _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_clk) 1440 _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_clk)
1441 _REGISTER_CLOCK("sdhci-esdhc-imx.2", NULL, esdhc3_clk)
1442 _REGISTER_CLOCK("sdhci-esdhc-imx.3", NULL, esdhc4_clk)
1319 _REGISTER_CLOCK(NULL, "cpu_clk", cpu_clk) 1443 _REGISTER_CLOCK(NULL, "cpu_clk", cpu_clk)
1320 _REGISTER_CLOCK(NULL, "iim_clk", iim_clk) 1444 _REGISTER_CLOCK(NULL, "iim_clk", iim_clk)
1321 _REGISTER_CLOCK("imx2-wdt.0", NULL, dummy_clk) 1445 _REGISTER_CLOCK("imx2-wdt.0", NULL, dummy_clk)
@@ -1336,10 +1460,14 @@ static struct clk_lookup mx53_lookups[] = {
1336 _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk) 1460 _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
1337 _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk) 1461 _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
1338 _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk) 1462 _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk)
1339 _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_clk) 1463 _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_mx53_clk)
1464 _REGISTER_CLOCK("sdhci-esdhc-imx.2", NULL, esdhc3_mx53_clk)
1465 _REGISTER_CLOCK("sdhci-esdhc-imx.3", NULL, esdhc4_mx53_clk)
1340 _REGISTER_CLOCK("imx53-ecspi.0", NULL, ecspi1_clk) 1466 _REGISTER_CLOCK("imx53-ecspi.0", NULL, ecspi1_clk)
1341 _REGISTER_CLOCK("imx53-ecspi.1", NULL, ecspi2_clk) 1467 _REGISTER_CLOCK("imx53-ecspi.1", NULL, ecspi2_clk)
1342 _REGISTER_CLOCK("imx53-cspi.0", NULL, cspi_clk) 1468 _REGISTER_CLOCK("imx53-cspi.0", NULL, cspi_clk)
1469 _REGISTER_CLOCK("imx2-wdt.0", NULL, dummy_clk)
1470 _REGISTER_CLOCK("imx2-wdt.1", NULL, dummy_clk)
1343}; 1471};
1344 1472
1345static void clk_tree_init(void) 1473static void clk_tree_init(void)
@@ -1427,6 +1555,14 @@ int __init mx53_clocks_init(unsigned long ckil, unsigned long osc,
1427 mx53_revision(); 1555 mx53_revision();
1428 clk_disable(&iim_clk); 1556 clk_disable(&iim_clk);
1429 1557
1558 /* Set SDHC parents to be PLL2 */
1559 clk_set_parent(&esdhc1_clk, &pll2_sw_clk);
1560 clk_set_parent(&esdhc3_mx53_clk, &pll2_sw_clk);
1561
1562 /* set SDHC root clock as 200MHZ*/
1563 clk_set_rate(&esdhc1_clk, 200000000);
1564 clk_set_rate(&esdhc3_mx53_clk, 200000000);
1565
1430 /* System timer */ 1566 /* System timer */
1431 mxc_timer_init(&gpt_clk, MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR), 1567 mxc_timer_init(&gpt_clk, MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR),
1432 MX53_INT_GPT); 1568 MX53_INT_GPT);
diff --git a/arch/arm/mach-mx5/cpu.c b/arch/arm/mach-mx5/cpu.c
index d40671da4372..df46b5e60857 100644
--- a/arch/arm/mach-mx5/cpu.c
+++ b/arch/arm/mach-mx5/cpu.c
@@ -78,11 +78,16 @@ static int get_mx53_srev(void)
78 void __iomem *iim_base = MX51_IO_ADDRESS(MX53_IIM_BASE_ADDR); 78 void __iomem *iim_base = MX51_IO_ADDRESS(MX53_IIM_BASE_ADDR);
79 u32 rev = readl(iim_base + IIM_SREV) & 0xff; 79 u32 rev = readl(iim_base + IIM_SREV) & 0xff;
80 80
81 if (rev == 0x0) 81 switch (rev) {
82 case 0x0:
82 return IMX_CHIP_REVISION_1_0; 83 return IMX_CHIP_REVISION_1_0;
83 else if (rev == 0x10) 84 case 0x2:
84 return IMX_CHIP_REVISION_2_0; 85 return IMX_CHIP_REVISION_2_0;
85 return 0; 86 case 0x3:
87 return IMX_CHIP_REVISION_2_1;
88 default:
89 return IMX_CHIP_REVISION_UNKNOWN;
90 }
86} 91}
87 92
88/* 93/*
diff --git a/arch/arm/mach-mx5/crm_regs.h b/arch/arm/mach-mx5/crm_regs.h
index b462c22f53d8..87c0c58f27a7 100644
--- a/arch/arm/mach-mx5/crm_regs.h
+++ b/arch/arm/mach-mx5/crm_regs.h
@@ -217,9 +217,12 @@
217#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET (20) 217#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET (20)
218#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK (0x3 << 20) 218#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK (0x3 << 20)
219#define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL (0x1 << 19) 219#define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL (0x1 << 19)
220#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_MX53_CLK_SEL (0x1 << 19)
220#define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 18) 221#define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 18)
221#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET (16) 222#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET (16)
222#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK (0x3 << 16) 223#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK (0x3 << 16)
224#define MXC_CCM_CSCMR1_ESDHC3_MX53_CLK_SEL_OFFSET (16)
225#define MXC_CCM_CSCMR1_ESDHC3_MX53_CLK_SEL_MASK (0x3 << 16)
223#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET (14) 226#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET (14)
224#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14) 227#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14)
225#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET (12) 228#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET (12)
@@ -271,6 +274,10 @@
271#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK (0x7 << 22) 274#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK (0x7 << 22)
272#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET (19) 275#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET (19)
273#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK (0x7 << 19) 276#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK (0x7 << 19)
277#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PRED_OFFSET (22)
278#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PRED_MASK (0x7 << 22)
279#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_OFFSET (19)
280#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_MASK (0x7 << 19)
274#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET (16) 281#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET (16)
275#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK (0x7 << 16) 282#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK (0x7 << 16)
276#define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET (14) 283#define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET (14)
diff --git a/arch/arm/mach-mx5/devices-mx50.h b/arch/arm/mach-mx5/devices-imx50.h
index 98ab07468a0e..c9e42823c7e3 100644
--- a/arch/arm/mach-mx5/devices-mx50.h
+++ b/arch/arm/mach-mx5/devices-imx50.h
@@ -24,3 +24,11 @@
24extern const struct imx_imx_uart_1irq_data imx50_imx_uart_data[] __initconst; 24extern const struct imx_imx_uart_1irq_data imx50_imx_uart_data[] __initconst;
25#define imx50_add_imx_uart(id, pdata) \ 25#define imx50_add_imx_uart(id, pdata) \
26 imx_add_imx_uart_1irq(&imx50_imx_uart_data[id], pdata) 26 imx_add_imx_uart_1irq(&imx50_imx_uart_data[id], pdata)
27
28extern const struct imx_fec_data imx50_fec_data __initconst;
29#define imx50_add_fec(pdata) \
30 imx_add_fec(&imx50_fec_data, pdata)
31
32extern const struct imx_imx_i2c_data imx50_imx_i2c_data[] __initconst;
33#define imx50_add_imx_i2c(id, pdata) \
34 imx_add_imx_i2c(&imx50_imx_i2c_data[id], pdata)
diff --git a/arch/arm/mach-mx5/devices-imx53.h b/arch/arm/mach-mx5/devices-imx53.h
index 8639735a117b..9251008dad1f 100644
--- a/arch/arm/mach-mx5/devices-imx53.h
+++ b/arch/arm/mach-mx5/devices-imx53.h
@@ -29,3 +29,7 @@ imx53_sdhci_esdhc_imx_data[] __initconst;
29extern const struct imx_spi_imx_data imx53_ecspi_data[] __initconst; 29extern const struct imx_spi_imx_data imx53_ecspi_data[] __initconst;
30#define imx53_add_ecspi(id, pdata) \ 30#define imx53_add_ecspi(id, pdata) \
31 imx_add_spi_imx(&imx53_ecspi_data[id], pdata) 31 imx_add_spi_imx(&imx53_ecspi_data[id], pdata)
32
33extern const struct imx_imx2_wdt_data imx53_imx2_wdt_data[] __initconst;
34#define imx53_add_imx2_wdt(id, pdata) \
35 imx_add_imx2_wdt(&imx53_imx2_wdt_data[id])
diff --git a/arch/arm/mach-mx5/efika.h b/arch/arm/mach-mx5/efika.h
new file mode 100644
index 000000000000..014aa985faae
--- /dev/null
+++ b/arch/arm/mach-mx5/efika.h
@@ -0,0 +1,10 @@
1#ifndef _EFIKA_H
2#define _EFIKA_H
3
4#define EFIKA_WLAN_EN IMX_GPIO_NR(2, 16)
5#define EFIKA_WLAN_RESET IMX_GPIO_NR(2, 10)
6#define EFIKA_USB_PHY_RESET IMX_GPIO_NR(2, 9)
7
8void __init efika_board_common_init(void);
9
10#endif
diff --git a/arch/arm/mach-mx5/ehci.c b/arch/arm/mach-mx5/ehci.c
new file mode 100644
index 000000000000..7ce12c804a32
--- /dev/null
+++ b/arch/arm/mach-mx5/ehci.c
@@ -0,0 +1,156 @@
1/*
2 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
3 * Copyright (C) 2010 Freescale Semiconductor, Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details.
14 */
15
16#include <linux/platform_device.h>
17#include <linux/io.h>
18
19#include <mach/hardware.h>
20#include <mach/mxc_ehci.h>
21
22#define MXC_OTG_OFFSET 0
23#define MXC_H1_OFFSET 0x200
24#define MXC_H2_OFFSET 0x400
25
26/* USB_CTRL */
27#define MXC_OTG_UCTRL_OWIE_BIT (1 << 27) /* OTG wakeup intr enable */
28#define MXC_OTG_UCTRL_OPM_BIT (1 << 24) /* OTG power mask */
29#define MXC_H1_UCTRL_H1UIE_BIT (1 << 12) /* Host1 ULPI interrupt enable */
30#define MXC_H1_UCTRL_H1WIE_BIT (1 << 11) /* HOST1 wakeup intr enable */
31#define MXC_H1_UCTRL_H1PM_BIT (1 << 8) /* HOST1 power mask */
32
33/* USB_PHY_CTRL_FUNC */
34#define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) /* OTG Disable Overcurrent Event */
35#define MXC_H1_OC_DIS_BIT (1 << 5) /* UH1 Disable Overcurrent Event */
36
37/* USBH2CTRL */
38#define MXC_H2_UCTRL_H2UIE_BIT (1 << 8)
39#define MXC_H2_UCTRL_H2WIE_BIT (1 << 7)
40#define MXC_H2_UCTRL_H2PM_BIT (1 << 4)
41
42#define MXC_USBCMD_OFFSET 0x140
43
44/* USBCMD */
45#define MXC_UCMD_ITC_NO_THRESHOLD_MASK (~(0xff << 16)) /* Interrupt Threshold Control */
46
47int mx51_initialize_usb_hw(int port, unsigned int flags)
48{
49 unsigned int v;
50 void __iomem *usb_base;
51 void __iomem *usbotg_base;
52 void __iomem *usbother_base;
53 int ret = 0;
54
55 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
56 if (!usb_base) {
57 printk(KERN_ERR "%s(): ioremap failed\n", __func__);
58 return -ENOMEM;
59 }
60
61 switch (port) {
62 case 0: /* OTG port */
63 usbotg_base = usb_base + MXC_OTG_OFFSET;
64 break;
65 case 1: /* Host 1 port */
66 usbotg_base = usb_base + MXC_H1_OFFSET;
67 break;
68 case 2: /* Host 2 port */
69 usbotg_base = usb_base + MXC_H2_OFFSET;
70 break;
71 default:
72 printk(KERN_ERR"%s no such port %d\n", __func__, port);
73 ret = -ENOENT;
74 goto error;
75 }
76 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
77
78 switch (port) {
79 case 0: /*OTG port */
80 if (flags & MXC_EHCI_INTERNAL_PHY) {
81 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
82
83 if (flags & MXC_EHCI_POWER_PINS_ENABLED) {
84 /* OC/USBPWR is not used */
85 v |= MXC_OTG_PHYCTRL_OC_DIS_BIT;
86 } else {
87 /* OC/USBPWR is used */
88 v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT;
89 }
90 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
91
92 v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
93 if (flags & MXC_EHCI_WAKEUP_ENABLED)
94 v |= MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup enable */
95 else
96 v &= ~MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup disable */
97 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
98 v |= MXC_OTG_UCTRL_OPM_BIT;
99 else
100 v &= ~MXC_OTG_UCTRL_OPM_BIT;
101 __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
102 }
103 break;
104 case 1: /* Host 1 */
105 /*Host ULPI */
106 v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
107 if (flags & MXC_EHCI_WAKEUP_ENABLED) {
108 /* HOST1 wakeup/ULPI intr enable */
109 v |= (MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);
110 } else {
111 /* HOST1 wakeup/ULPI intr disable */
112 v &= ~(MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);
113 }
114
115 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
116 v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/
117 else
118 v |= MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/
119 __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
120
121 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
122 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
123 v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */
124 else
125 v |= MXC_H1_OC_DIS_BIT; /* OC is not used */
126 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
127
128 v = __raw_readl(usbotg_base + MXC_USBCMD_OFFSET);
129 if (flags & MXC_EHCI_ITC_NO_THRESHOLD)
130 /* Interrupt Threshold Control:Immediate (no threshold) */
131 v &= MXC_UCMD_ITC_NO_THRESHOLD_MASK;
132 __raw_writel(v, usbotg_base + MXC_USBCMD_OFFSET);
133 break;
134 case 2: /* Host 2 ULPI */
135 v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET);
136 if (flags & MXC_EHCI_WAKEUP_ENABLED) {
137 /* HOST1 wakeup/ULPI intr enable */
138 v |= (MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT);
139 } else {
140 /* HOST1 wakeup/ULPI intr disable */
141 v &= ~(MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT);
142 }
143
144 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
145 v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/
146 else
147 v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/
148 __raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET);
149 break;
150 }
151
152error:
153 iounmap(usb_base);
154 return ret;
155}
156
diff --git a/arch/arm/mach-mx5/mm-mx50.c b/arch/arm/mach-mx5/mm-mx50.c
index 8c6540e58390..b9c363b514a9 100644
--- a/arch/arm/mach-mx5/mm-mx50.c
+++ b/arch/arm/mach-mx5/mm-mx50.c
@@ -26,6 +26,8 @@
26#include <mach/hardware.h> 26#include <mach/hardware.h>
27#include <mach/common.h> 27#include <mach/common.h>
28#include <mach/iomux-v3.h> 28#include <mach/iomux-v3.h>
29#include <mach/gpio.h>
30#include <mach/irqs.h>
29 31
30/* 32/*
31 * Define the MX50 memory map. 33 * Define the MX50 memory map.
@@ -44,16 +46,27 @@ static struct map_desc mx50_io_desc[] __initdata = {
44 */ 46 */
45void __init mx50_map_io(void) 47void __init mx50_map_io(void)
46{ 48{
49 iotable_init(mx50_io_desc, ARRAY_SIZE(mx50_io_desc));
50}
51
52void __init imx50_init_early(void)
53{
47 mxc_set_cpu_type(MXC_CPU_MX50); 54 mxc_set_cpu_type(MXC_CPU_MX50);
48 mxc_iomux_v3_init(MX50_IO_ADDRESS(MX50_IOMUXC_BASE_ADDR)); 55 mxc_iomux_v3_init(MX50_IO_ADDRESS(MX50_IOMUXC_BASE_ADDR));
49 mxc_arch_reset_init(MX50_IO_ADDRESS(MX50_WDOG_BASE_ADDR)); 56 mxc_arch_reset_init(MX50_IO_ADDRESS(MX50_WDOG_BASE_ADDR));
50 iotable_init(mx50_io_desc, ARRAY_SIZE(mx50_io_desc));
51} 57}
52 58
53int imx50_register_gpios(void); 59static struct mxc_gpio_port imx50_gpio_ports[] = {
60 DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 0, 1, MX50_INT_GPIO1_LOW, MX50_INT_GPIO1_HIGH),
61 DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 1, 2, MX50_INT_GPIO2_LOW, MX50_INT_GPIO2_HIGH),
62 DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 2, 3, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH),
63 DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 3, 4, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH),
64 DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 4, 5, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH),
65 DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 5, 6, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH),
66};
54 67
55void __init mx50_init_irq(void) 68void __init mx50_init_irq(void)
56{ 69{
57 tzic_init_irq(MX50_IO_ADDRESS(MX50_TZIC_BASE_ADDR)); 70 tzic_init_irq(MX50_IO_ADDRESS(MX50_TZIC_BASE_ADDR));
58 imx50_register_gpios(); 71 mxc_gpio_init(imx50_gpio_ports, ARRAY_SIZE(imx50_gpio_ports));
59} 72}
diff --git a/arch/arm/mach-mx5/mm.c b/arch/arm/mach-mx5/mm.c
index 457f9f95204b..ff557301b42b 100644
--- a/arch/arm/mach-mx5/mm.c
+++ b/arch/arm/mach-mx5/mm.c
@@ -47,18 +47,26 @@ static struct map_desc mx53_io_desc[] __initdata = {
47 */ 47 */
48void __init mx51_map_io(void) 48void __init mx51_map_io(void)
49{ 49{
50 iotable_init(mx51_io_desc, ARRAY_SIZE(mx51_io_desc));
51}
52
53void __init imx51_init_early(void)
54{
50 mxc_set_cpu_type(MXC_CPU_MX51); 55 mxc_set_cpu_type(MXC_CPU_MX51);
51 mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR)); 56 mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
52 mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR)); 57 mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
53 iotable_init(mx51_io_desc, ARRAY_SIZE(mx51_io_desc));
54} 58}
55 59
56void __init mx53_map_io(void) 60void __init mx53_map_io(void)
57{ 61{
62 iotable_init(mx53_io_desc, ARRAY_SIZE(mx53_io_desc));
63}
64
65void __init imx53_init_early(void)
66{
58 mxc_set_cpu_type(MXC_CPU_MX53); 67 mxc_set_cpu_type(MXC_CPU_MX53);
59 mxc_iomux_v3_init(MX53_IO_ADDRESS(MX53_IOMUXC_BASE_ADDR)); 68 mxc_iomux_v3_init(MX53_IO_ADDRESS(MX53_IOMUXC_BASE_ADDR));
60 mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG_BASE_ADDR)); 69 mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG1_BASE_ADDR));
61 iotable_init(mx53_io_desc, ARRAY_SIZE(mx53_io_desc));
62} 70}
63 71
64int imx51_register_gpios(void); 72int imx51_register_gpios(void);
diff --git a/arch/arm/mach-mx5/mx51_efika.c b/arch/arm/mach-mx5/mx51_efika.c
new file mode 100644
index 000000000000..51a67fc7f0ef
--- /dev/null
+++ b/arch/arm/mach-mx5/mx51_efika.c
@@ -0,0 +1,636 @@
1/*
2 * based on code from the following
3 * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
4 * Copyright 2009-2010 Pegatron Corporation. All Rights Reserved.
5 * Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved.
6 *
7 * The code contained herein is licensed under the GNU General Public
8 * License. You may obtain a copy of the GNU General Public License
9 * Version 2 or later at the following locations:
10 *
11 * http://www.opensource.org/licenses/gpl-license.html
12 * http://www.gnu.org/copyleft/gpl.html
13 */
14
15#include <linux/init.h>
16#include <linux/platform_device.h>
17#include <linux/i2c.h>
18#include <linux/gpio.h>
19#include <linux/leds.h>
20#include <linux/input.h>
21#include <linux/delay.h>
22#include <linux/io.h>
23#include <linux/fsl_devices.h>
24#include <linux/spi/flash.h>
25#include <linux/spi/spi.h>
26#include <linux/mfd/mc13892.h>
27#include <linux/regulator/machine.h>
28#include <linux/regulator/consumer.h>
29
30#include <mach/common.h>
31#include <mach/hardware.h>
32#include <mach/iomux-mx51.h>
33#include <mach/i2c.h>
34#include <mach/mxc_ehci.h>
35
36#include <linux/usb/otg.h>
37#include <linux/usb/ulpi.h>
38#include <mach/ulpi.h>
39
40#include <asm/irq.h>
41#include <asm/setup.h>
42#include <asm/mach-types.h>
43#include <asm/mach/arch.h>
44#include <asm/mach/time.h>
45#include <asm/mach-types.h>
46
47#include "devices-imx51.h"
48#include "devices.h"
49#include "efika.h"
50#include "cpu_op-mx51.h"
51
52#define MX51_USB_CTRL_1_OFFSET 0x10
53#define MX51_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
54#define MX51_USB_PLL_DIV_19_2_MHZ 0x01
55
56#define EFIKAMX_USB_HUB_RESET IMX_GPIO_NR(1, 5)
57#define EFIKAMX_USBH1_STP IMX_GPIO_NR(1, 27)
58
59#define EFIKAMX_SPI_CS0 IMX_GPIO_NR(4, 24)
60#define EFIKAMX_SPI_CS1 IMX_GPIO_NR(4, 25)
61
62#define EFIKAMX_PMIC IMX_GPIO_NR(1, 6)
63
64static iomux_v3_cfg_t mx51efika_pads[] = {
65 /* UART1 */
66 MX51_PAD_UART1_RXD__UART1_RXD,
67 MX51_PAD_UART1_TXD__UART1_TXD,
68 MX51_PAD_UART1_RTS__UART1_RTS,
69 MX51_PAD_UART1_CTS__UART1_CTS,
70
71 /* SD 1 */
72 MX51_PAD_SD1_CMD__SD1_CMD,
73 MX51_PAD_SD1_CLK__SD1_CLK,
74 MX51_PAD_SD1_DATA0__SD1_DATA0,
75 MX51_PAD_SD1_DATA1__SD1_DATA1,
76 MX51_PAD_SD1_DATA2__SD1_DATA2,
77 MX51_PAD_SD1_DATA3__SD1_DATA3,
78
79 /* SD 2 */
80 MX51_PAD_SD2_CMD__SD2_CMD,
81 MX51_PAD_SD2_CLK__SD2_CLK,
82 MX51_PAD_SD2_DATA0__SD2_DATA0,
83 MX51_PAD_SD2_DATA1__SD2_DATA1,
84 MX51_PAD_SD2_DATA2__SD2_DATA2,
85 MX51_PAD_SD2_DATA3__SD2_DATA3,
86
87 /* SD/MMC WP/CD */
88 MX51_PAD_GPIO1_0__SD1_CD,
89 MX51_PAD_GPIO1_1__SD1_WP,
90 MX51_PAD_GPIO1_7__SD2_WP,
91 MX51_PAD_GPIO1_8__SD2_CD,
92
93 /* spi */
94 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
95 MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
96 MX51_PAD_CSPI1_SS0__GPIO4_24,
97 MX51_PAD_CSPI1_SS1__GPIO4_25,
98 MX51_PAD_CSPI1_RDY__ECSPI1_RDY,
99 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
100 MX51_PAD_GPIO1_6__GPIO1_6,
101
102 /* USB HOST1 */
103 MX51_PAD_USBH1_CLK__USBH1_CLK,
104 MX51_PAD_USBH1_DIR__USBH1_DIR,
105 MX51_PAD_USBH1_NXT__USBH1_NXT,
106 MX51_PAD_USBH1_DATA0__USBH1_DATA0,
107 MX51_PAD_USBH1_DATA1__USBH1_DATA1,
108 MX51_PAD_USBH1_DATA2__USBH1_DATA2,
109 MX51_PAD_USBH1_DATA3__USBH1_DATA3,
110 MX51_PAD_USBH1_DATA4__USBH1_DATA4,
111 MX51_PAD_USBH1_DATA5__USBH1_DATA5,
112 MX51_PAD_USBH1_DATA6__USBH1_DATA6,
113 MX51_PAD_USBH1_DATA7__USBH1_DATA7,
114
115 /* USB HUB RESET */
116 MX51_PAD_GPIO1_5__GPIO1_5,
117
118 /* WLAN */
119 MX51_PAD_EIM_A22__GPIO2_16,
120 MX51_PAD_EIM_A16__GPIO2_10,
121
122 /* USB PHY RESET */
123 MX51_PAD_EIM_D27__GPIO2_9,
124};
125
126/* Serial ports */
127static const struct imxuart_platform_data uart_pdata = {
128 .flags = IMXUART_HAVE_RTSCTS,
129};
130
131/* This function is board specific as the bit mask for the plldiv will also
132 * be different for other Freescale SoCs, thus a common bitmask is not
133 * possible and cannot get place in /plat-mxc/ehci.c.
134 */
135static int initialize_otg_port(struct platform_device *pdev)
136{
137 u32 v;
138 void __iomem *usb_base;
139 void __iomem *usbother_base;
140 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
141 if (!usb_base)
142 return -ENOMEM;
143 usbother_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET);
144
145 /* Set the PHY clock to 19.2MHz */
146 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
147 v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
148 v |= MX51_USB_PLL_DIV_19_2_MHZ;
149 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
150 iounmap(usb_base);
151
152 mdelay(10);
153
154 return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_INTERNAL_PHY);
155}
156
157static struct mxc_usbh_platform_data dr_utmi_config = {
158 .init = initialize_otg_port,
159 .portsc = MXC_EHCI_UTMI_16BIT,
160};
161
162static int initialize_usbh1_port(struct platform_device *pdev)
163{
164 iomux_v3_cfg_t usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP;
165 iomux_v3_cfg_t usbh1gpio = MX51_PAD_USBH1_STP__GPIO1_27;
166 u32 v;
167 void __iomem *usb_base;
168 void __iomem *socregs_base;
169
170 mxc_iomux_v3_setup_pad(usbh1gpio);
171 gpio_request(EFIKAMX_USBH1_STP, "usbh1_stp");
172 gpio_direction_output(EFIKAMX_USBH1_STP, 0);
173 msleep(1);
174 gpio_set_value(EFIKAMX_USBH1_STP, 1);
175 msleep(1);
176
177 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
178 socregs_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET);
179
180 /* The clock for the USBH1 ULPI port will come externally */
181 /* from the PHY. */
182 v = __raw_readl(socregs_base + MX51_USB_CTRL_1_OFFSET);
183 __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN,
184 socregs_base + MX51_USB_CTRL_1_OFFSET);
185
186 iounmap(usb_base);
187
188 gpio_free(EFIKAMX_USBH1_STP);
189 mxc_iomux_v3_setup_pad(usbh1stp);
190
191 mdelay(10);
192
193 return mx51_initialize_usb_hw(0, MXC_EHCI_ITC_NO_THRESHOLD);
194}
195
196static struct mxc_usbh_platform_data usbh1_config = {
197 .init = initialize_usbh1_port,
198 .portsc = MXC_EHCI_MODE_ULPI,
199};
200
201static void mx51_efika_hubreset(void)
202{
203 gpio_request(EFIKAMX_USB_HUB_RESET, "usb_hub_rst");
204 gpio_direction_output(EFIKAMX_USB_HUB_RESET, 1);
205 msleep(1);
206 gpio_set_value(EFIKAMX_USB_HUB_RESET, 0);
207 msleep(1);
208 gpio_set_value(EFIKAMX_USB_HUB_RESET, 1);
209}
210
211static void __init mx51_efika_usb(void)
212{
213 mx51_efika_hubreset();
214
215 /* pulling it low, means no USB at all... */
216 gpio_request(EFIKA_USB_PHY_RESET, "usb_phy_reset");
217 gpio_direction_output(EFIKA_USB_PHY_RESET, 0);
218 msleep(1);
219 gpio_set_value(EFIKA_USB_PHY_RESET, 1);
220
221 usbh1_config.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
222 ULPI_OTG_DRVVBUS_EXT | ULPI_OTG_EXTVBUSIND);
223
224 mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
225 if (usbh1_config.otg)
226 mxc_register_device(&mxc_usbh1_device, &usbh1_config);
227}
228
229static struct mtd_partition mx51_efika_spi_nor_partitions[] = {
230 {
231 .name = "u-boot",
232 .offset = 0,
233 .size = SZ_256K,
234 },
235 {
236 .name = "config",
237 .offset = MTDPART_OFS_APPEND,
238 .size = SZ_64K,
239 },
240};
241
242static struct flash_platform_data mx51_efika_spi_flash_data = {
243 .name = "spi_flash",
244 .parts = mx51_efika_spi_nor_partitions,
245 .nr_parts = ARRAY_SIZE(mx51_efika_spi_nor_partitions),
246 .type = "sst25vf032b",
247};
248
249static struct regulator_consumer_supply sw1_consumers[] = {
250 {
251 .supply = "cpu_vcc",
252 }
253};
254
255static struct regulator_consumer_supply vdig_consumers[] = {
256 /* sgtl5000 */
257 REGULATOR_SUPPLY("VDDA", "1-000a"),
258 REGULATOR_SUPPLY("VDDD", "1-000a"),
259};
260
261static struct regulator_consumer_supply vvideo_consumers[] = {
262 /* sgtl5000 */
263 REGULATOR_SUPPLY("VDDIO", "1-000a"),
264};
265
266static struct regulator_consumer_supply vsd_consumers[] = {
267 REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx.0"),
268 REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx.1"),
269};
270
271static struct regulator_consumer_supply pwgt1_consumer[] = {
272 {
273 .supply = "pwgt1",
274 }
275};
276
277static struct regulator_consumer_supply pwgt2_consumer[] = {
278 {
279 .supply = "pwgt2",
280 }
281};
282
283static struct regulator_consumer_supply coincell_consumer[] = {
284 {
285 .supply = "coincell",
286 }
287};
288
289static struct regulator_init_data sw1_init = {
290 .constraints = {
291 .name = "SW1",
292 .min_uV = 600000,
293 .max_uV = 1375000,
294 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
295 .valid_modes_mask = 0,
296 .always_on = 1,
297 .boot_on = 1,
298 .state_mem = {
299 .uV = 850000,
300 .mode = REGULATOR_MODE_NORMAL,
301 .enabled = 1,
302 },
303 },
304 .num_consumer_supplies = ARRAY_SIZE(sw1_consumers),
305 .consumer_supplies = sw1_consumers,
306};
307
308static struct regulator_init_data sw2_init = {
309 .constraints = {
310 .name = "SW2",
311 .min_uV = 900000,
312 .max_uV = 1850000,
313 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
314 .always_on = 1,
315 .boot_on = 1,
316 .state_mem = {
317 .uV = 950000,
318 .mode = REGULATOR_MODE_NORMAL,
319 .enabled = 1,
320 },
321 }
322};
323
324static struct regulator_init_data sw3_init = {
325 .constraints = {
326 .name = "SW3",
327 .min_uV = 1100000,
328 .max_uV = 1850000,
329 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
330 .always_on = 1,
331 .boot_on = 1,
332 }
333};
334
335static struct regulator_init_data sw4_init = {
336 .constraints = {
337 .name = "SW4",
338 .min_uV = 1100000,
339 .max_uV = 1850000,
340 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
341 .always_on = 1,
342 .boot_on = 1,
343 }
344};
345
346static struct regulator_init_data viohi_init = {
347 .constraints = {
348 .name = "VIOHI",
349 .boot_on = 1,
350 .always_on = 1,
351 }
352};
353
354static struct regulator_init_data vusb_init = {
355 .constraints = {
356 .name = "VUSB",
357 .boot_on = 1,
358 .always_on = 1,
359 }
360};
361
362static struct regulator_init_data swbst_init = {
363 .constraints = {
364 .name = "SWBST",
365 }
366};
367
368static struct regulator_init_data vdig_init = {
369 .constraints = {
370 .name = "VDIG",
371 .min_uV = 1050000,
372 .max_uV = 1800000,
373 .valid_ops_mask =
374 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
375 .boot_on = 1,
376 .always_on = 1,
377 },
378 .num_consumer_supplies = ARRAY_SIZE(vdig_consumers),
379 .consumer_supplies = vdig_consumers,
380};
381
382static struct regulator_init_data vpll_init = {
383 .constraints = {
384 .name = "VPLL",
385 .min_uV = 1050000,
386 .max_uV = 1800000,
387 .valid_ops_mask =
388 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
389 .boot_on = 1,
390 .always_on = 1,
391 }
392};
393
394static struct regulator_init_data vusb2_init = {
395 .constraints = {
396 .name = "VUSB2",
397 .min_uV = 2400000,
398 .max_uV = 2775000,
399 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
400 .boot_on = 1,
401 .always_on = 1,
402 }
403};
404
405static struct regulator_init_data vvideo_init = {
406 .constraints = {
407 .name = "VVIDEO",
408 .min_uV = 2775000,
409 .max_uV = 2775000,
410 .valid_ops_mask =
411 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
412 .boot_on = 1,
413 .apply_uV = 1,
414 },
415 .num_consumer_supplies = ARRAY_SIZE(vvideo_consumers),
416 .consumer_supplies = vvideo_consumers,
417};
418
419static struct regulator_init_data vaudio_init = {
420 .constraints = {
421 .name = "VAUDIO",
422 .min_uV = 2300000,
423 .max_uV = 3000000,
424 .valid_ops_mask =
425 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
426 .boot_on = 1,
427 }
428};
429
430static struct regulator_init_data vsd_init = {
431 .constraints = {
432 .name = "VSD",
433 .min_uV = 1800000,
434 .max_uV = 3150000,
435 .valid_ops_mask =
436 REGULATOR_CHANGE_VOLTAGE,
437 .boot_on = 1,
438 },
439 .num_consumer_supplies = ARRAY_SIZE(vsd_consumers),
440 .consumer_supplies = vsd_consumers,
441};
442
443static struct regulator_init_data vcam_init = {
444 .constraints = {
445 .name = "VCAM",
446 .min_uV = 2500000,
447 .max_uV = 3000000,
448 .valid_ops_mask =
449 REGULATOR_CHANGE_VOLTAGE |
450 REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS,
451 .valid_modes_mask = REGULATOR_MODE_FAST | REGULATOR_MODE_NORMAL,
452 .boot_on = 1,
453 }
454};
455
456static struct regulator_init_data vgen1_init = {
457 .constraints = {
458 .name = "VGEN1",
459 .min_uV = 1200000,
460 .max_uV = 3150000,
461 .valid_ops_mask =
462 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
463 .boot_on = 1,
464 .always_on = 1,
465 }
466};
467
468static struct regulator_init_data vgen2_init = {
469 .constraints = {
470 .name = "VGEN2",
471 .min_uV = 1200000,
472 .max_uV = 3150000,
473 .valid_ops_mask =
474 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
475 .boot_on = 1,
476 .always_on = 1,
477 }
478};
479
480static struct regulator_init_data vgen3_init = {
481 .constraints = {
482 .name = "VGEN3",
483 .min_uV = 1800000,
484 .max_uV = 2900000,
485 .valid_ops_mask =
486 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
487 .boot_on = 1,
488 .always_on = 1,
489 }
490};
491
492static struct regulator_init_data gpo1_init = {
493 .constraints = {
494 .name = "GPO1",
495 }
496};
497
498static struct regulator_init_data gpo2_init = {
499 .constraints = {
500 .name = "GPO2",
501 }
502};
503
504static struct regulator_init_data gpo3_init = {
505 .constraints = {
506 .name = "GPO3",
507 }
508};
509
510static struct regulator_init_data gpo4_init = {
511 .constraints = {
512 .name = "GPO4",
513 }
514};
515
516static struct regulator_init_data pwgt1_init = {
517 .constraints = {
518 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
519 .boot_on = 1,
520 },
521 .num_consumer_supplies = ARRAY_SIZE(pwgt1_consumer),
522 .consumer_supplies = pwgt1_consumer,
523};
524
525static struct regulator_init_data pwgt2_init = {
526 .constraints = {
527 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
528 .boot_on = 1,
529 },
530 .num_consumer_supplies = ARRAY_SIZE(pwgt2_consumer),
531 .consumer_supplies = pwgt2_consumer,
532};
533
534static struct regulator_init_data vcoincell_init = {
535 .constraints = {
536 .name = "COINCELL",
537 .min_uV = 3000000,
538 .max_uV = 3000000,
539 .valid_ops_mask =
540 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
541 },
542 .num_consumer_supplies = ARRAY_SIZE(coincell_consumer),
543 .consumer_supplies = coincell_consumer,
544};
545
546static struct mc13xxx_regulator_init_data mx51_efika_regulators[] = {
547 { .id = MC13892_SW1, .init_data = &sw1_init },
548 { .id = MC13892_SW2, .init_data = &sw2_init },
549 { .id = MC13892_SW3, .init_data = &sw3_init },
550 { .id = MC13892_SW4, .init_data = &sw4_init },
551 { .id = MC13892_SWBST, .init_data = &swbst_init },
552 { .id = MC13892_VIOHI, .init_data = &viohi_init },
553 { .id = MC13892_VPLL, .init_data = &vpll_init },
554 { .id = MC13892_VDIG, .init_data = &vdig_init },
555 { .id = MC13892_VSD, .init_data = &vsd_init },
556 { .id = MC13892_VUSB2, .init_data = &vusb2_init },
557 { .id = MC13892_VVIDEO, .init_data = &vvideo_init },
558 { .id = MC13892_VAUDIO, .init_data = &vaudio_init },
559 { .id = MC13892_VCAM, .init_data = &vcam_init },
560 { .id = MC13892_VGEN1, .init_data = &vgen1_init },
561 { .id = MC13892_VGEN2, .init_data = &vgen2_init },
562 { .id = MC13892_VGEN3, .init_data = &vgen3_init },
563 { .id = MC13892_VUSB, .init_data = &vusb_init },
564 { .id = MC13892_GPO1, .init_data = &gpo1_init },
565 { .id = MC13892_GPO2, .init_data = &gpo2_init },
566 { .id = MC13892_GPO3, .init_data = &gpo3_init },
567 { .id = MC13892_GPO4, .init_data = &gpo4_init },
568 { .id = MC13892_PWGT1SPI, .init_data = &pwgt1_init },
569 { .id = MC13892_PWGT2SPI, .init_data = &pwgt2_init },
570 { .id = MC13892_VCOINCELL, .init_data = &vcoincell_init },
571};
572
573static struct mc13xxx_platform_data mx51_efika_mc13892_data = {
574 .flags = MC13XXX_USE_RTC | MC13XXX_USE_REGULATOR,
575 .num_regulators = ARRAY_SIZE(mx51_efika_regulators),
576 .regulators = mx51_efika_regulators,
577};
578
579static struct spi_board_info mx51_efika_spi_board_info[] __initdata = {
580 {
581 .modalias = "m25p80",
582 .max_speed_hz = 25000000,
583 .bus_num = 0,
584 .chip_select = 1,
585 .platform_data = &mx51_efika_spi_flash_data,
586 .irq = -1,
587 },
588 {
589 .modalias = "mc13892",
590 .max_speed_hz = 1000000,
591 .bus_num = 0,
592 .chip_select = 0,
593 .platform_data = &mx51_efika_mc13892_data,
594 .irq = gpio_to_irq(EFIKAMX_PMIC),
595 },
596};
597
598static int mx51_efika_spi_cs[] = {
599 EFIKAMX_SPI_CS0,
600 EFIKAMX_SPI_CS1,
601};
602
603static const struct spi_imx_master mx51_efika_spi_pdata __initconst = {
604 .chipselect = mx51_efika_spi_cs,
605 .num_chipselect = ARRAY_SIZE(mx51_efika_spi_cs),
606};
607
608void __init efika_board_common_init(void)
609{
610 mxc_iomux_v3_setup_multiple_pads(mx51efika_pads,
611 ARRAY_SIZE(mx51efika_pads));
612 imx51_add_imx_uart(0, &uart_pdata);
613 mx51_efika_usb();
614 imx51_add_sdhci_esdhc_imx(0, NULL);
615
616 /* FIXME: comes from original code. check this. */
617 if (mx51_revision() < IMX_CHIP_REVISION_2_0)
618 sw2_init.constraints.state_mem.uV = 1100000;
619 else if (mx51_revision() == IMX_CHIP_REVISION_2_0) {
620 sw2_init.constraints.state_mem.uV = 1250000;
621 sw1_init.constraints.state_mem.uV = 1000000;
622 }
623 if (machine_is_mx51_efikasb())
624 vgen1_init.constraints.max_uV = 1200000;
625
626 gpio_request(EFIKAMX_PMIC, "pmic irq");
627 gpio_direction_input(EFIKAMX_PMIC);
628 spi_register_board_info(mx51_efika_spi_board_info,
629 ARRAY_SIZE(mx51_efika_spi_board_info));
630 imx51_add_ecspi(0, &mx51_efika_spi_pdata);
631
632#if defined(CONFIG_CPU_FREQ_IMX)
633 get_cpu_op = mx51_get_cpu_op;
634#endif
635}
636
diff --git a/arch/arm/mach-mxc91231/iomux.c b/arch/arm/mach-mxc91231/iomux.c
index 405d9b19d891..66fc41cbf2ca 100644
--- a/arch/arm/mach-mxc91231/iomux.c
+++ b/arch/arm/mach-mxc91231/iomux.c
@@ -50,7 +50,7 @@ unsigned long mxc_pin_alloc_map[NB_PORTS * 32 / BITS_PER_LONG];
50/* 50/*
51 * set the mode for a IOMUX pin. 51 * set the mode for a IOMUX pin.
52 */ 52 */
53int mxc_iomux_mode(const unsigned int pin_mode) 53int mxc_iomux_mode(unsigned int pin_mode)
54{ 54{
55 u32 side, field, l, mode, ret = 0; 55 u32 side, field, l, mode, ret = 0;
56 void __iomem *reg; 56 void __iomem *reg;
@@ -114,7 +114,7 @@ EXPORT_SYMBOL(mxc_iomux_set_pad);
114 * - reserves the pin so that it is not claimed by another driver 114 * - reserves the pin so that it is not claimed by another driver
115 * - setups the iomux according to the configuration 115 * - setups the iomux according to the configuration
116 */ 116 */
117int mxc_iomux_alloc_pin(const unsigned int pin_mode, const char *label) 117int mxc_iomux_alloc_pin(unsigned int pin_mode, const char *label)
118{ 118{
119 unsigned pad = PIN_GLOBAL_NUM(pin_mode); 119 unsigned pad = PIN_GLOBAL_NUM(pin_mode);
120 if (pad >= (PIN_MAX + 1)) { 120 if (pad >= (PIN_MAX + 1)) {
@@ -134,10 +134,10 @@ int mxc_iomux_alloc_pin(const unsigned int pin_mode, const char *label)
134} 134}
135EXPORT_SYMBOL(mxc_iomux_alloc_pin); 135EXPORT_SYMBOL(mxc_iomux_alloc_pin);
136 136
137int mxc_iomux_setup_multiple_pins(unsigned int *pin_list, unsigned count, 137int mxc_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count,
138 const char *label) 138 const char *label)
139{ 139{
140 unsigned int *p = pin_list; 140 const unsigned int *p = pin_list;
141 int i; 141 int i;
142 int ret = -EINVAL; 142 int ret = -EINVAL;
143 143
@@ -155,7 +155,7 @@ setup_error:
155} 155}
156EXPORT_SYMBOL(mxc_iomux_setup_multiple_pins); 156EXPORT_SYMBOL(mxc_iomux_setup_multiple_pins);
157 157
158void mxc_iomux_release_pin(const unsigned int pin_mode) 158void mxc_iomux_release_pin(unsigned int pin_mode)
159{ 159{
160 unsigned pad = PIN_GLOBAL_NUM(pin_mode); 160 unsigned pad = PIN_GLOBAL_NUM(pin_mode);
161 161
@@ -164,9 +164,9 @@ void mxc_iomux_release_pin(const unsigned int pin_mode)
164} 164}
165EXPORT_SYMBOL(mxc_iomux_release_pin); 165EXPORT_SYMBOL(mxc_iomux_release_pin);
166 166
167void mxc_iomux_release_multiple_pins(unsigned int *pin_list, int count) 167void mxc_iomux_release_multiple_pins(const unsigned int *pin_list, int count)
168{ 168{
169 unsigned int *p = pin_list; 169 const unsigned int *p = pin_list;
170 int i; 170 int i;
171 171
172 for (i = 0; i < count; i++) { 172 for (i = 0; i < count; i++) {
diff --git a/arch/arm/mach-mxc91231/magx-zn5.c b/arch/arm/mach-mxc91231/magx-zn5.c
index 395d83be8c98..f31a45e5a0b8 100644
--- a/arch/arm/mach-mxc91231/magx-zn5.c
+++ b/arch/arm/mach-mxc91231/magx-zn5.c
@@ -53,9 +53,10 @@ struct sys_timer zn5_timer = {
53}; 53};
54 54
55MACHINE_START(MAGX_ZN5, "Motorola Zn5") 55MACHINE_START(MAGX_ZN5, "Motorola Zn5")
56 .boot_params = MXC91231_PHYS_OFFSET + 0x100, 56 .boot_params = MXC91231_PHYS_OFFSET + 0x100,
57 .map_io = mxc91231_map_io, 57 .map_io = mxc91231_map_io,
58 .init_irq = mxc91231_init_irq, 58 .init_early = mxc91231_init_early,
59 .timer = &zn5_timer, 59 .init_irq = mxc91231_init_irq,
60 .init_machine = zn5_init, 60 .timer = &zn5_timer,
61 .init_machine = zn5_init,
61MACHINE_END 62MACHINE_END
diff --git a/arch/arm/mach-mxc91231/mm.c b/arch/arm/mach-mxc91231/mm.c
index 7652c301da88..a77f6daf6a26 100644
--- a/arch/arm/mach-mxc91231/mm.c
+++ b/arch/arm/mach-mxc91231/mm.c
@@ -45,11 +45,14 @@ static struct map_desc mxc91231_io_desc[] __initdata = {
45 */ 45 */
46void __init mxc91231_map_io(void) 46void __init mxc91231_map_io(void)
47{ 47{
48 mxc_set_cpu_type(MXC_CPU_MXC91231);
49
50 iotable_init(mxc91231_io_desc, ARRAY_SIZE(mxc91231_io_desc)); 48 iotable_init(mxc91231_io_desc, ARRAY_SIZE(mxc91231_io_desc));
51} 49}
52 50
51void __init mxc91231_init_early(void)
52{
53 mxc_set_cpu_type(MXC_CPU_MXC91231);
54}
55
53int mxc91231_register_gpios(void); 56int mxc91231_register_gpios(void);
54 57
55void __init mxc91231_init_irq(void) 58void __init mxc91231_init_irq(void)
diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig
index 8bfc8df54617..4f6f174af6c8 100644
--- a/arch/arm/mach-mxs/Kconfig
+++ b/arch/arm/mach-mxs/Kconfig
@@ -2,13 +2,18 @@ if ARCH_MXS
2 2
3source "arch/arm/mach-mxs/devices/Kconfig" 3source "arch/arm/mach-mxs/devices/Kconfig"
4 4
5config MXS_OCOTP
6 bool
7
5config SOC_IMX23 8config SOC_IMX23
6 bool 9 bool
7 select CPU_ARM926T 10 select CPU_ARM926T
11 select HAVE_PWM
8 12
9config SOC_IMX28 13config SOC_IMX28
10 bool 14 bool
11 select CPU_ARM926T 15 select CPU_ARM926T
16 select HAVE_PWM
12 17
13comment "MXS platforms:" 18comment "MXS platforms:"
14 19
@@ -16,6 +21,8 @@ config MACH_MX23EVK
16 bool "Support MX23EVK Platform" 21 bool "Support MX23EVK Platform"
17 select SOC_IMX23 22 select SOC_IMX23
18 select MXS_HAVE_AMBA_DUART 23 select MXS_HAVE_AMBA_DUART
24 select MXS_HAVE_PLATFORM_AUART
25 select MXS_HAVE_PLATFORM_MXSFB
19 default y 26 default y
20 help 27 help
21 Include support for MX23EVK platform. This includes specific 28 Include support for MX23EVK platform. This includes specific
@@ -25,10 +32,27 @@ config MACH_MX28EVK
25 bool "Support MX28EVK Platform" 32 bool "Support MX28EVK Platform"
26 select SOC_IMX28 33 select SOC_IMX28
27 select MXS_HAVE_AMBA_DUART 34 select MXS_HAVE_AMBA_DUART
35 select MXS_HAVE_PLATFORM_AUART
28 select MXS_HAVE_PLATFORM_FEC 36 select MXS_HAVE_PLATFORM_FEC
37 select MXS_HAVE_PLATFORM_FLEXCAN
38 select MXS_HAVE_PLATFORM_MXSFB
39 select MXS_OCOTP
29 default y 40 default y
30 help 41 help
31 Include support for MX28EVK platform. This includes specific 42 Include support for MX28EVK platform. This includes specific
32 configurations for the board and its peripherals. 43 configurations for the board and its peripherals.
33 44
45config MODULE_TX28
46 bool
47 select SOC_IMX28
48 select MXS_HAVE_AMBA_DUART
49 select MXS_HAVE_PLATFORM_AUART
50 select MXS_HAVE_PLATFORM_FEC
51 select MXS_HAVE_PLATFORM_MXS_I2C
52 select MXS_HAVE_PLATFORM_MXS_PWM
53
54config MACH_TX28
55 bool "Ka-Ro TX28 module"
56 select MODULE_TX28
57
34endif 58endif
diff --git a/arch/arm/mach-mxs/Makefile b/arch/arm/mach-mxs/Makefile
index 39d3f9c2a841..2f1f6141ca71 100644
--- a/arch/arm/mach-mxs/Makefile
+++ b/arch/arm/mach-mxs/Makefile
@@ -1,10 +1,15 @@
1# Common support 1# Common support
2obj-y := clock.o devices.o gpio.o icoll.o iomux.o system.o timer.o 2obj-y := clock.o devices.o gpio.o icoll.o iomux.o system.o timer.o
3 3
4obj-$(CONFIG_MXS_OCOTP) += ocotp.o
5obj-$(CONFIG_PM) += pm.o
6
4obj-$(CONFIG_SOC_IMX23) += clock-mx23.o mm-mx23.o 7obj-$(CONFIG_SOC_IMX23) += clock-mx23.o mm-mx23.o
5obj-$(CONFIG_SOC_IMX28) += clock-mx28.o mm-mx28.o 8obj-$(CONFIG_SOC_IMX28) += clock-mx28.o mm-mx28.o
6 9
7obj-$(CONFIG_MACH_MX23EVK) += mach-mx23evk.o 10obj-$(CONFIG_MACH_MX23EVK) += mach-mx23evk.o
8obj-$(CONFIG_MACH_MX28EVK) += mach-mx28evk.o 11obj-$(CONFIG_MACH_MX28EVK) += mach-mx28evk.o
12obj-$(CONFIG_MODULE_TX28) += module-tx28.o
13obj-$(CONFIG_MACH_TX28) += mach-tx28.o
9 14
10obj-y += devices/ 15obj-y += devices/
diff --git a/arch/arm/mach-mxs/clock-mx23.c b/arch/arm/mach-mxs/clock-mx23.c
index ca72a05ed9c1..d133c7f30940 100644
--- a/arch/arm/mach-mxs/clock-mx23.c
+++ b/arch/arm/mach-mxs/clock-mx23.c
@@ -442,11 +442,18 @@ static struct clk_lookup lookups[] = {
442 _REGISTER_CLOCK("duart", "apb_pclk", xbus_clk) 442 _REGISTER_CLOCK("duart", "apb_pclk", xbus_clk)
443 /* for amba-pl011 driver */ 443 /* for amba-pl011 driver */
444 _REGISTER_CLOCK("duart", NULL, uart_clk) 444 _REGISTER_CLOCK("duart", NULL, uart_clk)
445 _REGISTER_CLOCK("mxs-auart.0", NULL, uart_clk)
445 _REGISTER_CLOCK("rtc", NULL, rtc_clk) 446 _REGISTER_CLOCK("rtc", NULL, rtc_clk)
446 _REGISTER_CLOCK(NULL, "hclk", hbus_clk) 447 _REGISTER_CLOCK("mxs-dma-apbh", NULL, hbus_clk)
448 _REGISTER_CLOCK("mxs-dma-apbx", NULL, xbus_clk)
447 _REGISTER_CLOCK(NULL, "usb", usb_clk) 449 _REGISTER_CLOCK(NULL, "usb", usb_clk)
448 _REGISTER_CLOCK(NULL, "audio", audio_clk) 450 _REGISTER_CLOCK(NULL, "audio", audio_clk)
449 _REGISTER_CLOCK(NULL, "pwm", pwm_clk) 451 _REGISTER_CLOCK("mxs-pwm.0", NULL, pwm_clk)
452 _REGISTER_CLOCK("mxs-pwm.1", NULL, pwm_clk)
453 _REGISTER_CLOCK("mxs-pwm.2", NULL, pwm_clk)
454 _REGISTER_CLOCK("mxs-pwm.3", NULL, pwm_clk)
455 _REGISTER_CLOCK("mxs-pwm.4", NULL, pwm_clk)
456 _REGISTER_CLOCK("imx23-fb", NULL, lcdif_clk)
450}; 457};
451 458
452static int clk_misc_init(void) 459static int clk_misc_init(void)
diff --git a/arch/arm/mach-mxs/clock-mx28.c b/arch/arm/mach-mxs/clock-mx28.c
index fd1c4c54b8e5..5e489a2b2023 100644
--- a/arch/arm/mach-mxs/clock-mx28.c
+++ b/arch/arm/mach-mxs/clock-mx28.c
@@ -609,17 +609,30 @@ static struct clk_lookup lookups[] = {
609 _REGISTER_CLOCK("duart", NULL, uart_clk) 609 _REGISTER_CLOCK("duart", NULL, uart_clk)
610 _REGISTER_CLOCK("imx28-fec.0", NULL, fec_clk) 610 _REGISTER_CLOCK("imx28-fec.0", NULL, fec_clk)
611 _REGISTER_CLOCK("imx28-fec.1", NULL, fec_clk) 611 _REGISTER_CLOCK("imx28-fec.1", NULL, fec_clk)
612 _REGISTER_CLOCK("mxs-auart.0", NULL, uart_clk)
613 _REGISTER_CLOCK("mxs-auart.1", NULL, uart_clk)
614 _REGISTER_CLOCK("mxs-auart.2", NULL, uart_clk)
615 _REGISTER_CLOCK("mxs-auart.3", NULL, uart_clk)
616 _REGISTER_CLOCK("mxs-auart.4", NULL, uart_clk)
612 _REGISTER_CLOCK("rtc", NULL, rtc_clk) 617 _REGISTER_CLOCK("rtc", NULL, rtc_clk)
613 _REGISTER_CLOCK("pll2", NULL, pll2_clk) 618 _REGISTER_CLOCK("pll2", NULL, pll2_clk)
614 _REGISTER_CLOCK(NULL, "hclk", hbus_clk) 619 _REGISTER_CLOCK("mxs-dma-apbh", NULL, hbus_clk)
615 _REGISTER_CLOCK(NULL, "xclk", xbus_clk) 620 _REGISTER_CLOCK("mxs-dma-apbx", NULL, xbus_clk)
616 _REGISTER_CLOCK(NULL, "can0", can0_clk) 621 _REGISTER_CLOCK("flexcan.0", NULL, can0_clk)
617 _REGISTER_CLOCK(NULL, "can1", can1_clk) 622 _REGISTER_CLOCK("flexcan.1", NULL, can1_clk)
618 _REGISTER_CLOCK(NULL, "usb0", usb0_clk) 623 _REGISTER_CLOCK(NULL, "usb0", usb0_clk)
619 _REGISTER_CLOCK(NULL, "usb1", usb1_clk) 624 _REGISTER_CLOCK(NULL, "usb1", usb1_clk)
620 _REGISTER_CLOCK(NULL, "pwm", pwm_clk) 625 _REGISTER_CLOCK("mxs-pwm.0", NULL, pwm_clk)
626 _REGISTER_CLOCK("mxs-pwm.1", NULL, pwm_clk)
627 _REGISTER_CLOCK("mxs-pwm.2", NULL, pwm_clk)
628 _REGISTER_CLOCK("mxs-pwm.3", NULL, pwm_clk)
629 _REGISTER_CLOCK("mxs-pwm.4", NULL, pwm_clk)
630 _REGISTER_CLOCK("mxs-pwm.5", NULL, pwm_clk)
631 _REGISTER_CLOCK("mxs-pwm.6", NULL, pwm_clk)
632 _REGISTER_CLOCK("mxs-pwm.7", NULL, pwm_clk)
621 _REGISTER_CLOCK(NULL, "lradc", lradc_clk) 633 _REGISTER_CLOCK(NULL, "lradc", lradc_clk)
622 _REGISTER_CLOCK(NULL, "spdif", spdif_clk) 634 _REGISTER_CLOCK(NULL, "spdif", spdif_clk)
635 _REGISTER_CLOCK("imx28-fb", NULL, lcdif_clk)
623}; 636};
624 637
625static int clk_misc_init(void) 638static int clk_misc_init(void)
@@ -737,6 +750,8 @@ int __init mx28_clocks_init(void)
737 clk_enable(&emi_clk); 750 clk_enable(&emi_clk);
738 clk_enable(&uart_clk); 751 clk_enable(&uart_clk);
739 752
753 clk_set_parent(&lcdif_clk, &ref_pix_clk);
754
740 clkdev_add_table(lookups, ARRAY_SIZE(lookups)); 755 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
741 756
742 mxs_timer_init(&clk32k_clk, MX28_INT_TIMER0); 757 mxs_timer_init(&clk32k_clk, MX28_INT_TIMER0);
diff --git a/arch/arm/mach-mxs/devices-mx23.h b/arch/arm/mach-mxs/devices-mx23.h
index 1256788561d0..c7e14f4e3669 100644
--- a/arch/arm/mach-mxs/devices-mx23.h
+++ b/arch/arm/mach-mxs/devices-mx23.h
@@ -10,7 +10,18 @@
10 */ 10 */
11#include <mach/mx23.h> 11#include <mach/mx23.h>
12#include <mach/devices-common.h> 12#include <mach/devices-common.h>
13#include <mach/mxsfb.h>
13 14
14extern const struct amba_device mx23_duart_device __initconst; 15extern const struct amba_device mx23_duart_device __initconst;
15#define mx23_add_duart() \ 16#define mx23_add_duart() \
16 mxs_add_duart(&mx23_duart_device) 17 mxs_add_duart(&mx23_duart_device)
18
19extern const struct mxs_auart_data mx23_auart_data[] __initconst;
20#define mx23_add_auart(id) mxs_add_auart(&mx23_auart_data[id])
21#define mx23_add_auart0() mx23_add_auart(0)
22#define mx23_add_auart1() mx23_add_auart(1)
23
24#define mx23_add_mxs_pwm(id) mxs_add_mxs_pwm(MX23_PWM_BASE_ADDR, id)
25
26struct platform_device *__init mx23_add_mxsfb(
27 const struct mxsfb_platform_data *pdata);
diff --git a/arch/arm/mach-mxs/devices-mx28.h b/arch/arm/mach-mxs/devices-mx28.h
index 33773a6333a2..9d08555c4cf0 100644
--- a/arch/arm/mach-mxs/devices-mx28.h
+++ b/arch/arm/mach-mxs/devices-mx28.h
@@ -10,11 +10,34 @@
10 */ 10 */
11#include <mach/mx28.h> 11#include <mach/mx28.h>
12#include <mach/devices-common.h> 12#include <mach/devices-common.h>
13#include <mach/mxsfb.h>
13 14
14extern const struct amba_device mx28_duart_device __initconst; 15extern const struct amba_device mx28_duart_device __initconst;
15#define mx28_add_duart() \ 16#define mx28_add_duart() \
16 mxs_add_duart(&mx28_duart_device) 17 mxs_add_duart(&mx28_duart_device)
17 18
19extern const struct mxs_auart_data mx28_auart_data[] __initconst;
20#define mx28_add_auart(id) mxs_add_auart(&mx28_auart_data[id])
21#define mx28_add_auart0() mx28_add_auart(0)
22#define mx28_add_auart1() mx28_add_auart(1)
23#define mx28_add_auart2() mx28_add_auart(2)
24#define mx28_add_auart3() mx28_add_auart(3)
25#define mx28_add_auart4() mx28_add_auart(4)
26
18extern const struct mxs_fec_data mx28_fec_data[] __initconst; 27extern const struct mxs_fec_data mx28_fec_data[] __initconst;
19#define mx28_add_fec(id, pdata) \ 28#define mx28_add_fec(id, pdata) \
20 mxs_add_fec(&mx28_fec_data[id], pdata) 29 mxs_add_fec(&mx28_fec_data[id], pdata)
30
31extern const struct mxs_flexcan_data mx28_flexcan_data[] __initconst;
32#define mx28_add_flexcan(id, pdata) \
33 mxs_add_flexcan(&mx28_flexcan_data[id], pdata)
34#define mx28_add_flexcan0(pdata) mx28_add_flexcan(0, pdata)
35#define mx28_add_flexcan1(pdata) mx28_add_flexcan(1, pdata)
36
37extern const struct mxs_i2c_data mx28_mxs_i2c_data[] __initconst;
38#define mx28_add_mxs_i2c(id) mxs_add_mxs_i2c(&mx28_mxs_i2c_data[id])
39
40#define mx28_add_mxs_pwm(id) mxs_add_mxs_pwm(MX28_PWM_BASE_ADDR, id)
41
42struct platform_device *__init mx28_add_mxsfb(
43 const struct mxsfb_platform_data *pdata);
diff --git a/arch/arm/mach-mxs/devices.c b/arch/arm/mach-mxs/devices.c
index c20d54740b0b..cfdb6b284702 100644
--- a/arch/arm/mach-mxs/devices.c
+++ b/arch/arm/mach-mxs/devices.c
@@ -66,6 +66,8 @@ struct platform_device *__init mxs_add_platform_device_dmamask(
66 ret = platform_device_add(pdev); 66 ret = platform_device_add(pdev);
67 if (ret) { 67 if (ret) {
68err: 68err:
69 if (dmamask)
70 kfree(pdev->dev.dma_mask);
69 platform_device_put(pdev); 71 platform_device_put(pdev);
70 return ERR_PTR(ret); 72 return ERR_PTR(ret);
71 } 73 }
diff --git a/arch/arm/mach-mxs/devices/Kconfig b/arch/arm/mach-mxs/devices/Kconfig
index cf7dc1ae575b..1451ad060d82 100644
--- a/arch/arm/mach-mxs/devices/Kconfig
+++ b/arch/arm/mach-mxs/devices/Kconfig
@@ -2,5 +2,21 @@ config MXS_HAVE_AMBA_DUART
2 bool 2 bool
3 select ARM_AMBA 3 select ARM_AMBA
4 4
5config MXS_HAVE_PLATFORM_AUART
6 bool
7
5config MXS_HAVE_PLATFORM_FEC 8config MXS_HAVE_PLATFORM_FEC
6 bool 9 bool
10
11config MXS_HAVE_PLATFORM_FLEXCAN
12 select HAVE_CAN_FLEXCAN if CAN
13 bool
14
15config MXS_HAVE_PLATFORM_MXS_I2C
16 bool
17
18config MXS_HAVE_PLATFORM_MXS_PWM
19 bool
20
21config MXS_HAVE_PLATFORM_MXSFB
22 bool
diff --git a/arch/arm/mach-mxs/devices/Makefile b/arch/arm/mach-mxs/devices/Makefile
index d0a09f6934b8..0d9bea30b0a2 100644
--- a/arch/arm/mach-mxs/devices/Makefile
+++ b/arch/arm/mach-mxs/devices/Makefile
@@ -1,2 +1,8 @@
1obj-$(CONFIG_MXS_HAVE_AMBA_DUART) += amba-duart.o 1obj-$(CONFIG_MXS_HAVE_AMBA_DUART) += amba-duart.o
2obj-$(CONFIG_MXS_HAVE_PLATFORM_AUART) += platform-auart.o
3obj-y += platform-dma.o
2obj-$(CONFIG_MXS_HAVE_PLATFORM_FEC) += platform-fec.o 4obj-$(CONFIG_MXS_HAVE_PLATFORM_FEC) += platform-fec.o
5obj-$(CONFIG_MXS_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o
6obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_I2C) += platform-mxs-i2c.o
7obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_PWM) += platform-mxs-pwm.o
8obj-$(CONFIG_MXS_HAVE_PLATFORM_MXSFB) += platform-mxsfb.o
diff --git a/arch/arm/mach-mxs/devices/platform-auart.c b/arch/arm/mach-mxs/devices/platform-auart.c
new file mode 100644
index 000000000000..796606cce0ce
--- /dev/null
+++ b/arch/arm/mach-mxs/devices/platform-auart.c
@@ -0,0 +1,64 @@
1/*
2 * Copyright (C) 2010 Pengutronix
3 * Sascha Hauer <s.hauer@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9#include <asm/sizes.h>
10#include <mach/mx23.h>
11#include <mach/mx28.h>
12#include <mach/devices-common.h>
13
14#define mxs_auart_data_entry_single(soc, _id, hwid) \
15 { \
16 .id = _id, \
17 .iobase = soc ## _AUART ## hwid ## _BASE_ADDR, \
18 .irq = soc ## _INT_AUART ## hwid, \
19 }
20
21#define mxs_auart_data_entry(soc, _id, hwid) \
22 [_id] = mxs_auart_data_entry_single(soc, _id, hwid)
23
24#ifdef CONFIG_SOC_IMX23
25const struct mxs_auart_data mx23_auart_data[] __initconst = {
26#define mx23_auart_data_entry(_id, hwid) \
27 mxs_auart_data_entry(MX23, _id, hwid)
28 mx23_auart_data_entry(0, 1),
29 mx23_auart_data_entry(1, 2),
30};
31#endif
32
33#ifdef CONFIG_SOC_IMX28
34const struct mxs_auart_data mx28_auart_data[] __initconst = {
35#define mx28_auart_data_entry(_id) \
36 mxs_auart_data_entry(MX28, _id, _id)
37 mx28_auart_data_entry(0),
38 mx28_auart_data_entry(1),
39 mx28_auart_data_entry(2),
40 mx28_auart_data_entry(3),
41 mx28_auart_data_entry(4),
42};
43#endif
44
45struct platform_device *__init mxs_add_auart(
46 const struct mxs_auart_data *data)
47{
48 struct resource res[] = {
49 {
50 .start = data->iobase,
51 .end = data->iobase + SZ_8K - 1,
52 .flags = IORESOURCE_MEM,
53 }, {
54 .start = data->irq,
55 .end = data->irq,
56 .flags = IORESOURCE_IRQ,
57 },
58 };
59
60 return mxs_add_platform_device_dmamask("mxs-auart", data->id,
61 res, ARRAY_SIZE(res), NULL, 0,
62 DMA_BIT_MASK(32));
63}
64
diff --git a/arch/arm/mach-mxs/devices/platform-dma.c b/arch/arm/mach-mxs/devices/platform-dma.c
new file mode 100644
index 000000000000..295c4424d5d9
--- /dev/null
+++ b/arch/arm/mach-mxs/devices/platform-dma.c
@@ -0,0 +1,49 @@
1/*
2 * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it under
5 * the terms of the GNU General Public License version 2 as published by the
6 * Free Software Foundation.
7 */
8#include <linux/compiler.h>
9#include <linux/err.h>
10#include <linux/init.h>
11
12#include <mach/mx23.h>
13#include <mach/mx28.h>
14#include <mach/devices-common.h>
15
16static struct platform_device *__init mxs_add_dma(const char *devid,
17 resource_size_t base)
18{
19 struct resource res[] = {
20 {
21 .start = base,
22 .end = base + SZ_8K - 1,
23 .flags = IORESOURCE_MEM,
24 }
25 };
26
27 return mxs_add_platform_device_dmamask(devid, -1,
28 res, ARRAY_SIZE(res), NULL, 0,
29 DMA_BIT_MASK(32));
30}
31
32static int __init mxs_add_mxs_dma(void)
33{
34 char *apbh = "mxs-dma-apbh";
35 char *apbx = "mxs-dma-apbx";
36
37 if (cpu_is_mx23()) {
38 mxs_add_dma(apbh, MX23_APBH_DMA_BASE_ADDR);
39 mxs_add_dma(apbx, MX23_APBX_DMA_BASE_ADDR);
40 }
41
42 if (cpu_is_mx28()) {
43 mxs_add_dma(apbh, MX28_APBH_DMA_BASE_ADDR);
44 mxs_add_dma(apbx, MX28_APBX_DMA_BASE_ADDR);
45 }
46
47 return 0;
48}
49arch_initcall(mxs_add_mxs_dma);
diff --git a/arch/arm/mach-mxs/devices/platform-fec.c b/arch/arm/mach-mxs/devices/platform-fec.c
index c42dff72b46c..9859cf283335 100644
--- a/arch/arm/mach-mxs/devices/platform-fec.c
+++ b/arch/arm/mach-mxs/devices/platform-fec.c
@@ -45,6 +45,7 @@ struct platform_device *__init mxs_add_fec(
45 }, 45 },
46 }; 46 };
47 47
48 return mxs_add_platform_device("imx28-fec", data->id, 48 return mxs_add_platform_device_dmamask("imx28-fec", data->id,
49 res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); 49 res, ARRAY_SIZE(res), pdata, sizeof(*pdata),
50 DMA_BIT_MASK(32));
50} 51}
diff --git a/arch/arm/mach-mxs/devices/platform-flexcan.c b/arch/arm/mach-mxs/devices/platform-flexcan.c
new file mode 100644
index 000000000000..43a6b4bae6fe
--- /dev/null
+++ b/arch/arm/mach-mxs/devices/platform-flexcan.c
@@ -0,0 +1,51 @@
1/*
2 * Copyright (C) 2010, 2011 Pengutronix,
3 * Marc Kleine-Budde <kernel@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9#include <asm/sizes.h>
10#include <mach/mx28.h>
11#include <mach/devices-common.h>
12
13#define mxs_flexcan_data_entry_single(soc, _id, _hwid, _size) \
14 { \
15 .id = _id, \
16 .iobase = soc ## _CAN ## _hwid ## _BASE_ADDR, \
17 .iosize = _size, \
18 .irq = soc ## _INT_CAN ## _hwid, \
19 }
20
21#define mxs_flexcan_data_entry(soc, _id, _hwid, _size) \
22 [_id] = mxs_flexcan_data_entry_single(soc, _id, _hwid, _size)
23
24#ifdef CONFIG_SOC_IMX28
25const struct mxs_flexcan_data mx28_flexcan_data[] __initconst = {
26#define mx28_flexcan_data_entry(_id, _hwid) \
27 mxs_flexcan_data_entry_single(MX28, _id, _hwid, SZ_8K)
28 mx28_flexcan_data_entry(0, 0),
29 mx28_flexcan_data_entry(1, 1),
30};
31#endif /* ifdef CONFIG_SOC_IMX28 */
32
33struct platform_device *__init mxs_add_flexcan(
34 const struct mxs_flexcan_data *data,
35 const struct flexcan_platform_data *pdata)
36{
37 struct resource res[] = {
38 {
39 .start = data->iobase,
40 .end = data->iobase + data->iosize - 1,
41 .flags = IORESOURCE_MEM,
42 }, {
43 .start = data->irq,
44 .end = data->irq,
45 .flags = IORESOURCE_IRQ,
46 },
47 };
48
49 return mxs_add_platform_device("flexcan", data->id,
50 res, ARRAY_SIZE(res), pdata, sizeof(*pdata));
51}
diff --git a/arch/arm/mach-mxs/devices/platform-mxs-i2c.c b/arch/arm/mach-mxs/devices/platform-mxs-i2c.c
new file mode 100644
index 000000000000..eab3a06836d6
--- /dev/null
+++ b/arch/arm/mach-mxs/devices/platform-mxs-i2c.c
@@ -0,0 +1,51 @@
1/*
2 * Copyright (C) 2011 Pengutronix
3 * Wolfram Sang <w.sang@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9#include <asm/sizes.h>
10#include <mach/mx28.h>
11#include <mach/devices-common.h>
12
13#define mxs_i2c_data_entry_single(soc, _id) \
14 { \
15 .id = _id, \
16 .iobase = soc ## _I2C ## _id ## _BASE_ADDR, \
17 .errirq = soc ## _INT_I2C ## _id ## _ERROR, \
18 .dmairq = soc ## _INT_I2C ## _id ## _DMA, \
19 }
20
21#define mxs_i2c_data_entry(soc, _id) \
22 [_id] = mxs_i2c_data_entry_single(soc, _id)
23
24#ifdef CONFIG_SOC_IMX28
25const struct mxs_i2c_data mx28_mxs_i2c_data[] __initconst = {
26 mxs_i2c_data_entry(MX28, 0),
27 mxs_i2c_data_entry(MX28, 1),
28};
29#endif
30
31struct platform_device *__init mxs_add_mxs_i2c(const struct mxs_i2c_data *data)
32{
33 struct resource res[] = {
34 {
35 .start = data->iobase,
36 .end = data->iobase + SZ_8K - 1,
37 .flags = IORESOURCE_MEM,
38 }, {
39 .start = data->errirq,
40 .end = data->errirq,
41 .flags = IORESOURCE_IRQ,
42 }, {
43 .start = data->dmairq,
44 .end = data->dmairq,
45 .flags = IORESOURCE_IRQ,
46 },
47 };
48
49 return mxs_add_platform_device("mxs-i2c", data->id, res,
50 ARRAY_SIZE(res), NULL, 0);
51}
diff --git a/arch/arm/mach-mxs/devices/platform-mxs-pwm.c b/arch/arm/mach-mxs/devices/platform-mxs-pwm.c
new file mode 100644
index 000000000000..680f5a902936
--- /dev/null
+++ b/arch/arm/mach-mxs/devices/platform-mxs-pwm.c
@@ -0,0 +1,22 @@
1/*
2 * Copyright (C) 2010 Pengutronix
3 * Sascha Hauer <s.hauer@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9#include <asm/sizes.h>
10#include <mach/devices-common.h>
11
12struct platform_device *__init mxs_add_mxs_pwm(resource_size_t iobase, int id)
13{
14 struct resource res = {
15 .flags = IORESOURCE_MEM,
16 };
17
18 res.start = iobase + 0x10 + 0x20 * id;
19 res.end = res.start + 0x1f;
20
21 return mxs_add_platform_device("mxs-pwm", id, &res, 1, NULL, 0);
22}
diff --git a/arch/arm/mach-mxs/devices/platform-mxsfb.c b/arch/arm/mach-mxs/devices/platform-mxsfb.c
new file mode 100644
index 000000000000..bf72c9b8dbdd
--- /dev/null
+++ b/arch/arm/mach-mxs/devices/platform-mxsfb.c
@@ -0,0 +1,46 @@
1/*
2 * Copyright (C) 2011 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
3 *
4 * This program is free software; you can redistribute it and/or modify it under
5 * the terms of the GNU General Public License version 2 as published by the
6 * Free Software Foundation.
7 */
8#include <asm/sizes.h>
9#include <mach/mx23.h>
10#include <mach/mx28.h>
11#include <mach/devices-common.h>
12#include <mach/mxsfb.h>
13
14#ifdef CONFIG_SOC_IMX23
15struct platform_device *__init mx23_add_mxsfb(
16 const struct mxsfb_platform_data *pdata)
17{
18 struct resource res[] = {
19 {
20 .start = MX23_LCDIF_BASE_ADDR,
21 .end = MX23_LCDIF_BASE_ADDR + SZ_8K - 1,
22 .flags = IORESOURCE_MEM,
23 },
24 };
25
26 return mxs_add_platform_device_dmamask("imx23-fb", -1,
27 res, ARRAY_SIZE(res), pdata, sizeof(*pdata), DMA_BIT_MASK(32));
28}
29#endif /* ifdef CONFIG_SOC_IMX23 */
30
31#ifdef CONFIG_SOC_IMX28
32struct platform_device *__init mx28_add_mxsfb(
33 const struct mxsfb_platform_data *pdata)
34{
35 struct resource res[] = {
36 {
37 .start = MX28_LCDIF_BASE_ADDR,
38 .end = MX28_LCDIF_BASE_ADDR + SZ_8K - 1,
39 .flags = IORESOURCE_MEM,
40 },
41 };
42
43 return mxs_add_platform_device_dmamask("imx28-fb", -1,
44 res, ARRAY_SIZE(res), pdata, sizeof(*pdata), DMA_BIT_MASK(32));
45}
46#endif /* ifdef CONFIG_SOC_IMX28 */
diff --git a/arch/arm/mach-mxs/gpio.c b/arch/arm/mach-mxs/gpio.c
index 61991e4dde44..56fa2ed15222 100644
--- a/arch/arm/mach-mxs/gpio.c
+++ b/arch/arm/mach-mxs/gpio.c
@@ -182,6 +182,7 @@ static int mxs_gpio_set_wake_irq(struct irq_data *d, unsigned int enable)
182} 182}
183 183
184static struct irq_chip gpio_irq_chip = { 184static struct irq_chip gpio_irq_chip = {
185 .name = "mxs gpio",
185 .irq_ack = mxs_gpio_ack_irq, 186 .irq_ack = mxs_gpio_ack_irq,
186 .irq_mask = mxs_gpio_mask_irq, 187 .irq_mask = mxs_gpio_mask_irq,
187 .irq_unmask = mxs_gpio_unmask_irq, 188 .irq_unmask = mxs_gpio_unmask_irq,
@@ -289,39 +290,42 @@ int __init mxs_gpio_init(struct mxs_gpio_port *port, int cnt)
289 return 0; 290 return 0;
290} 291}
291 292
292#define DEFINE_MXS_GPIO_PORT(soc, _id) \ 293#define MX23_GPIO_BASE MX23_IO_ADDRESS(MX23_PINCTRL_BASE_ADDR)
294#define MX28_GPIO_BASE MX28_IO_ADDRESS(MX28_PINCTRL_BASE_ADDR)
295
296#define DEFINE_MXS_GPIO_PORT(_base, _irq, _id) \
293 { \ 297 { \
294 .chip.label = "gpio-" #_id, \ 298 .chip.label = "gpio-" #_id, \
295 .id = _id, \ 299 .id = _id, \
296 .irq = soc ## _INT_GPIO ## _id, \ 300 .irq = _irq, \
297 .base = soc ## _IO_ADDRESS( \ 301 .base = _base, \
298 soc ## _PINCTRL ## _BASE_ADDR), \
299 .virtual_irq_start = MXS_GPIO_IRQ_START + (_id) * 32, \ 302 .virtual_irq_start = MXS_GPIO_IRQ_START + (_id) * 32, \
300 } 303 }
301 304
302#define DEFINE_REGISTER_FUNCTION(prefix) \
303int __init prefix ## _register_gpios(void) \
304{ \
305 return mxs_gpio_init(prefix ## _gpio_ports, \
306 ARRAY_SIZE(prefix ## _gpio_ports)); \
307}
308
309#ifdef CONFIG_SOC_IMX23 305#ifdef CONFIG_SOC_IMX23
310static struct mxs_gpio_port mx23_gpio_ports[] = { 306static struct mxs_gpio_port mx23_gpio_ports[] = {
311 DEFINE_MXS_GPIO_PORT(MX23, 0), 307 DEFINE_MXS_GPIO_PORT(MX23_GPIO_BASE, MX23_INT_GPIO0, 0),
312 DEFINE_MXS_GPIO_PORT(MX23, 1), 308 DEFINE_MXS_GPIO_PORT(MX23_GPIO_BASE, MX23_INT_GPIO1, 1),
313 DEFINE_MXS_GPIO_PORT(MX23, 2), 309 DEFINE_MXS_GPIO_PORT(MX23_GPIO_BASE, MX23_INT_GPIO2, 2),
314}; 310};
315DEFINE_REGISTER_FUNCTION(mx23) 311
312int __init mx23_register_gpios(void)
313{
314 return mxs_gpio_init(mx23_gpio_ports, ARRAY_SIZE(mx23_gpio_ports));
315}
316#endif 316#endif
317 317
318#ifdef CONFIG_SOC_IMX28 318#ifdef CONFIG_SOC_IMX28
319static struct mxs_gpio_port mx28_gpio_ports[] = { 319static struct mxs_gpio_port mx28_gpio_ports[] = {
320 DEFINE_MXS_GPIO_PORT(MX28, 0), 320 DEFINE_MXS_GPIO_PORT(MX28_GPIO_BASE, MX28_INT_GPIO0, 0),
321 DEFINE_MXS_GPIO_PORT(MX28, 1), 321 DEFINE_MXS_GPIO_PORT(MX28_GPIO_BASE, MX28_INT_GPIO1, 1),
322 DEFINE_MXS_GPIO_PORT(MX28, 2), 322 DEFINE_MXS_GPIO_PORT(MX28_GPIO_BASE, MX28_INT_GPIO2, 2),
323 DEFINE_MXS_GPIO_PORT(MX28, 3), 323 DEFINE_MXS_GPIO_PORT(MX28_GPIO_BASE, MX28_INT_GPIO3, 3),
324 DEFINE_MXS_GPIO_PORT(MX28, 4), 324 DEFINE_MXS_GPIO_PORT(MX28_GPIO_BASE, MX28_INT_GPIO4, 4),
325}; 325};
326DEFINE_REGISTER_FUNCTION(mx28) 326
327int __init mx28_register_gpios(void)
328{
329 return mxs_gpio_init(mx28_gpio_ports, ARRAY_SIZE(mx28_gpio_ports));
330}
327#endif 331#endif
diff --git a/arch/arm/mach-mxs/include/mach/common.h b/arch/arm/mach-mxs/include/mach/common.h
index 59133eb3cc96..635bb5d9a20a 100644
--- a/arch/arm/mach-mxs/include/mach/common.h
+++ b/arch/arm/mach-mxs/include/mach/common.h
@@ -13,6 +13,7 @@
13 13
14struct clk; 14struct clk;
15 15
16extern const u32 *mxs_get_ocotp(void);
16extern int mxs_reset_block(void __iomem *); 17extern int mxs_reset_block(void __iomem *);
17extern void mxs_timer_init(struct clk *, int); 18extern void mxs_timer_init(struct clk *, int);
18 19
diff --git a/arch/arm/mach-mxs/include/mach/devices-common.h b/arch/arm/mach-mxs/include/mach/devices-common.h
index 6c3d1a103433..71f24484b044 100644
--- a/arch/arm/mach-mxs/include/mach/devices-common.h
+++ b/arch/arm/mach-mxs/include/mach/devices-common.h
@@ -30,6 +30,16 @@ int __init mxs_add_amba_device(const struct amba_device *dev);
30/* duart */ 30/* duart */
31int __init mxs_add_duart(const struct amba_device *dev); 31int __init mxs_add_duart(const struct amba_device *dev);
32 32
33/* auart */
34struct mxs_auart_data {
35 int id;
36 resource_size_t iobase;
37 resource_size_t iosize;
38 resource_size_t irq;
39};
40struct platform_device *__init mxs_add_auart(
41 const struct mxs_auart_data *data);
42
33/* fec */ 43/* fec */
34#include <linux/fec.h> 44#include <linux/fec.h>
35struct mxs_fec_data { 45struct mxs_fec_data {
@@ -41,3 +51,28 @@ struct mxs_fec_data {
41struct platform_device *__init mxs_add_fec( 51struct platform_device *__init mxs_add_fec(
42 const struct mxs_fec_data *data, 52 const struct mxs_fec_data *data,
43 const struct fec_platform_data *pdata); 53 const struct fec_platform_data *pdata);
54
55/* flexcan */
56#include <linux/can/platform/flexcan.h>
57struct mxs_flexcan_data {
58 int id;
59 resource_size_t iobase;
60 resource_size_t iosize;
61 resource_size_t irq;
62};
63struct platform_device *__init mxs_add_flexcan(
64 const struct mxs_flexcan_data *data,
65 const struct flexcan_platform_data *pdata);
66
67/* i2c */
68struct mxs_i2c_data {
69 int id;
70 resource_size_t iobase;
71 resource_size_t errirq;
72 resource_size_t dmairq;
73};
74struct platform_device * __init mxs_add_mxs_i2c(const struct mxs_i2c_data *data);
75
76/* pwm */
77struct platform_device *__init mxs_add_mxs_pwm(
78 resource_size_t iobase, int id);
diff --git a/arch/arm/mach-mxs/include/mach/iomux-mx23.h b/arch/arm/mach-mxs/include/mach/iomux-mx23.h
index 94e5dd83cdb8..b0190a4822f2 100644
--- a/arch/arm/mach-mxs/include/mach/iomux-mx23.h
+++ b/arch/arm/mach-mxs/include/mach/iomux-mx23.h
@@ -254,102 +254,102 @@
254#define MX23_PAD_ROTARYB__GPMI_CE3N MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_2) 254#define MX23_PAD_ROTARYB__GPMI_CE3N MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_2)
255 255
256/* MUXSEL_GPIO */ 256/* MUXSEL_GPIO */
257#define MX23_PAD_GPMI_D00__GPO_0_0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_GPIO) 257#define MX23_PAD_GPMI_D00__GPIO_0_0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_GPIO)
258#define MX23_PAD_GPMI_D01__GPO_0_1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_GPIO) 258#define MX23_PAD_GPMI_D01__GPIO_0_1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_GPIO)
259#define MX23_PAD_GPMI_D02__GPO_0_2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_GPIO) 259#define MX23_PAD_GPMI_D02__GPIO_0_2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_GPIO)
260#define MX23_PAD_GPMI_D03__GPO_0_3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_GPIO) 260#define MX23_PAD_GPMI_D03__GPIO_0_3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_GPIO)
261#define MX23_PAD_GPMI_D04__GPO_0_4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_GPIO) 261#define MX23_PAD_GPMI_D04__GPIO_0_4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_GPIO)
262#define MX23_PAD_GPMI_D05__GPO_0_5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_GPIO) 262#define MX23_PAD_GPMI_D05__GPIO_0_5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_GPIO)
263#define MX23_PAD_GPMI_D06__GPO_0_6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_GPIO) 263#define MX23_PAD_GPMI_D06__GPIO_0_6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_GPIO)
264#define MX23_PAD_GPMI_D07__GPO_0_7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_GPIO) 264#define MX23_PAD_GPMI_D07__GPIO_0_7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_GPIO)
265#define MX23_PAD_GPMI_D08__GPO_0_8 MXS_IOMUX_PAD_NAKED(0, 8, PAD_MUXSEL_GPIO) 265#define MX23_PAD_GPMI_D08__GPIO_0_8 MXS_IOMUX_PAD_NAKED(0, 8, PAD_MUXSEL_GPIO)
266#define MX23_PAD_GPMI_D09__GPO_0_9 MXS_IOMUX_PAD_NAKED(0, 9, PAD_MUXSEL_GPIO) 266#define MX23_PAD_GPMI_D09__GPIO_0_9 MXS_IOMUX_PAD_NAKED(0, 9, PAD_MUXSEL_GPIO)
267#define MX23_PAD_GPMI_D10__GPO_0_10 MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_GPIO) 267#define MX23_PAD_GPMI_D10__GPIO_0_10 MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_GPIO)
268#define MX23_PAD_GPMI_D11__GPO_0_11 MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_GPIO) 268#define MX23_PAD_GPMI_D11__GPIO_0_11 MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_GPIO)
269#define MX23_PAD_GPMI_D12__GPO_0_12 MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_GPIO) 269#define MX23_PAD_GPMI_D12__GPIO_0_12 MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_GPIO)
270#define MX23_PAD_GPMI_D13__GPO_0_13 MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_GPIO) 270#define MX23_PAD_GPMI_D13__GPIO_0_13 MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_GPIO)
271#define MX23_PAD_GPMI_D14__GPO_0_14 MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_GPIO) 271#define MX23_PAD_GPMI_D14__GPIO_0_14 MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_GPIO)
272#define MX23_PAD_GPMI_D15__GPO_0_15 MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_GPIO) 272#define MX23_PAD_GPMI_D15__GPIO_0_15 MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_GPIO)
273#define MX23_PAD_GPMI_CLE__GPO_0_16 MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_GPIO) 273#define MX23_PAD_GPMI_CLE__GPIO_0_16 MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_GPIO)
274#define MX23_PAD_GPMI_ALE__GPO_0_17 MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_GPIO) 274#define MX23_PAD_GPMI_ALE__GPIO_0_17 MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_GPIO)
275#define MX23_PAD_GPMI_CE2N__GPO_0_18 MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_GPIO) 275#define MX23_PAD_GPMI_CE2N__GPIO_0_18 MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_GPIO)
276#define MX23_PAD_GPMI_RDY0__GPO_0_19 MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_GPIO) 276#define MX23_PAD_GPMI_RDY0__GPIO_0_19 MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_GPIO)
277#define MX23_PAD_GPMI_RDY1__GPO_0_20 MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_GPIO) 277#define MX23_PAD_GPMI_RDY1__GPIO_0_20 MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_GPIO)
278#define MX23_PAD_GPMI_RDY2__GPO_0_21 MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_GPIO) 278#define MX23_PAD_GPMI_RDY2__GPIO_0_21 MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_GPIO)
279#define MX23_PAD_GPMI_RDY3__GPO_0_22 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_GPIO) 279#define MX23_PAD_GPMI_RDY3__GPIO_0_22 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_GPIO)
280#define MX23_PAD_GPMI_WPN__GPO_0_23 MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_GPIO) 280#define MX23_PAD_GPMI_WPN__GPIO_0_23 MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_GPIO)
281#define MX23_PAD_GPMI_WRN__GPO_0_24 MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_GPIO) 281#define MX23_PAD_GPMI_WRN__GPIO_0_24 MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_GPIO)
282#define MX23_PAD_GPMI_RDN__GPO_0_25 MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_GPIO) 282#define MX23_PAD_GPMI_RDN__GPIO_0_25 MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_GPIO)
283#define MX23_PAD_AUART1_CTS__GPO_0_26 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_GPIO) 283#define MX23_PAD_AUART1_CTS__GPIO_0_26 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_GPIO)
284#define MX23_PAD_AUART1_RTS__GPO_0_27 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_GPIO) 284#define MX23_PAD_AUART1_RTS__GPIO_0_27 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_GPIO)
285#define MX23_PAD_AUART1_RX__GPO_0_28 MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_GPIO) 285#define MX23_PAD_AUART1_RX__GPIO_0_28 MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_GPIO)
286#define MX23_PAD_AUART1_TX__GPO_0_29 MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_GPIO) 286#define MX23_PAD_AUART1_TX__GPIO_0_29 MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_GPIO)
287#define MX23_PAD_I2C_SCL__GPO_0_30 MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_GPIO) 287#define MX23_PAD_I2C_SCL__GPIO_0_30 MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_GPIO)
288#define MX23_PAD_I2C_SDA__GPO_0_31 MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_GPIO) 288#define MX23_PAD_I2C_SDA__GPIO_0_31 MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_GPIO)
289 289
290#define MX23_PAD_LCD_D00__GPO_1_0 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_GPIO) 290#define MX23_PAD_LCD_D00__GPIO_1_0 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_GPIO)
291#define MX23_PAD_LCD_D01__GPO_1_1 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_GPIO) 291#define MX23_PAD_LCD_D01__GPIO_1_1 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_GPIO)
292#define MX23_PAD_LCD_D02__GPO_1_2 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_GPIO) 292#define MX23_PAD_LCD_D02__GPIO_1_2 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_GPIO)
293#define MX23_PAD_LCD_D03__GPO_1_3 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_GPIO) 293#define MX23_PAD_LCD_D03__GPIO_1_3 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_GPIO)
294#define MX23_PAD_LCD_D04__GPO_1_4 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_GPIO) 294#define MX23_PAD_LCD_D04__GPIO_1_4 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_GPIO)
295#define MX23_PAD_LCD_D05__GPO_1_5 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_GPIO) 295#define MX23_PAD_LCD_D05__GPIO_1_5 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_GPIO)
296#define MX23_PAD_LCD_D06__GPO_1_6 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_GPIO) 296#define MX23_PAD_LCD_D06__GPIO_1_6 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_GPIO)
297#define MX23_PAD_LCD_D07__GPO_1_7 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_GPIO) 297#define MX23_PAD_LCD_D07__GPIO_1_7 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_GPIO)
298#define MX23_PAD_LCD_D08__GPO_1_8 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_GPIO) 298#define MX23_PAD_LCD_D08__GPIO_1_8 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_GPIO)
299#define MX23_PAD_LCD_D09__GPO_1_9 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_GPIO) 299#define MX23_PAD_LCD_D09__GPIO_1_9 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_GPIO)
300#define MX23_PAD_LCD_D10__GPO_1_10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_GPIO) 300#define MX23_PAD_LCD_D10__GPIO_1_10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_GPIO)
301#define MX23_PAD_LCD_D11__GPO_1_11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_GPIO) 301#define MX23_PAD_LCD_D11__GPIO_1_11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_GPIO)
302#define MX23_PAD_LCD_D12__GPO_1_12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_GPIO) 302#define MX23_PAD_LCD_D12__GPIO_1_12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_GPIO)
303#define MX23_PAD_LCD_D13__GPO_1_13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_GPIO) 303#define MX23_PAD_LCD_D13__GPIO_1_13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_GPIO)
304#define MX23_PAD_LCD_D14__GPO_1_14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_GPIO) 304#define MX23_PAD_LCD_D14__GPIO_1_14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_GPIO)
305#define MX23_PAD_LCD_D15__GPO_1_15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_GPIO) 305#define MX23_PAD_LCD_D15__GPIO_1_15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_GPIO)
306#define MX23_PAD_LCD_D16__GPO_1_16 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_GPIO) 306#define MX23_PAD_LCD_D16__GPIO_1_16 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_GPIO)
307#define MX23_PAD_LCD_D17__GPO_1_17 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_GPIO) 307#define MX23_PAD_LCD_D17__GPIO_1_17 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_GPIO)
308#define MX23_PAD_LCD_RESET__GPO_1_18 MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_GPIO) 308#define MX23_PAD_LCD_RESET__GPIO_1_18 MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_GPIO)
309#define MX23_PAD_LCD_RS__GPO_1_19 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_GPIO) 309#define MX23_PAD_LCD_RS__GPIO_1_19 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_GPIO)
310#define MX23_PAD_LCD_WR__GPO_1_20 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_GPIO) 310#define MX23_PAD_LCD_WR__GPIO_1_20 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_GPIO)
311#define MX23_PAD_LCD_CS__GPO_1_21 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_GPIO) 311#define MX23_PAD_LCD_CS__GPIO_1_21 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_GPIO)
312#define MX23_PAD_LCD_DOTCK__GPO_1_22 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_GPIO) 312#define MX23_PAD_LCD_DOTCK__GPIO_1_22 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_GPIO)
313#define MX23_PAD_LCD_ENABLE__GPO_1_23 MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_GPIO) 313#define MX23_PAD_LCD_ENABLE__GPIO_1_23 MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_GPIO)
314#define MX23_PAD_LCD_HSYNC__GPO_1_24 MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_GPIO) 314#define MX23_PAD_LCD_HSYNC__GPIO_1_24 MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_GPIO)
315#define MX23_PAD_LCD_VSYNC__GPO_1_25 MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_GPIO) 315#define MX23_PAD_LCD_VSYNC__GPIO_1_25 MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_GPIO)
316#define MX23_PAD_PWM0__GPO_1_26 MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_GPIO) 316#define MX23_PAD_PWM0__GPIO_1_26 MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_GPIO)
317#define MX23_PAD_PWM1__GPO_1_27 MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_GPIO) 317#define MX23_PAD_PWM1__GPIO_1_27 MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_GPIO)
318#define MX23_PAD_PWM2__GPO_1_28 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_GPIO) 318#define MX23_PAD_PWM2__GPIO_1_28 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_GPIO)
319#define MX23_PAD_PWM3__GPO_1_29 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_GPIO) 319#define MX23_PAD_PWM3__GPIO_1_29 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_GPIO)
320#define MX23_PAD_PWM4__GPO_1_30 MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_GPIO) 320#define MX23_PAD_PWM4__GPIO_1_30 MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_GPIO)
321 321
322#define MX23_PAD_SSP1_CMD__GPO_2_0 MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_GPIO) 322#define MX23_PAD_SSP1_CMD__GPIO_2_0 MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_GPIO)
323#define MX23_PAD_SSP1_DETECT__GPO_2_1 MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_GPIO) 323#define MX23_PAD_SSP1_DETECT__GPIO_2_1 MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_GPIO)
324#define MX23_PAD_SSP1_DATA0__GPO_2_2 MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_GPIO) 324#define MX23_PAD_SSP1_DATA0__GPIO_2_2 MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_GPIO)
325#define MX23_PAD_SSP1_DATA1__GPO_2_3 MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_GPIO) 325#define MX23_PAD_SSP1_DATA1__GPIO_2_3 MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_GPIO)
326#define MX23_PAD_SSP1_DATA2__GPO_2_4 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_GPIO) 326#define MX23_PAD_SSP1_DATA2__GPIO_2_4 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_GPIO)
327#define MX23_PAD_SSP1_DATA3__GPO_2_5 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_GPIO) 327#define MX23_PAD_SSP1_DATA3__GPIO_2_5 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_GPIO)
328#define MX23_PAD_SSP1_SCK__GPO_2_6 MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_GPIO) 328#define MX23_PAD_SSP1_SCK__GPIO_2_6 MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_GPIO)
329#define MX23_PAD_ROTARYA__GPO_2_7 MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_GPIO) 329#define MX23_PAD_ROTARYA__GPIO_2_7 MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_GPIO)
330#define MX23_PAD_ROTARYB__GPO_2_8 MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_GPIO) 330#define MX23_PAD_ROTARYB__GPIO_2_8 MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_GPIO)
331#define MX23_PAD_EMI_A00__GPO_2_9 MXS_IOMUX_PAD_NAKED(2, 9, PAD_MUXSEL_GPIO) 331#define MX23_PAD_EMI_A00__GPIO_2_9 MXS_IOMUX_PAD_NAKED(2, 9, PAD_MUXSEL_GPIO)
332#define MX23_PAD_EMI_A01__GPO_2_10 MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_GPIO) 332#define MX23_PAD_EMI_A01__GPIO_2_10 MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_GPIO)
333#define MX23_PAD_EMI_A02__GPO_2_11 MXS_IOMUX_PAD_NAKED(2, 11, PAD_MUXSEL_GPIO) 333#define MX23_PAD_EMI_A02__GPIO_2_11 MXS_IOMUX_PAD_NAKED(2, 11, PAD_MUXSEL_GPIO)
334#define MX23_PAD_EMI_A03__GPO_2_12 MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_GPIO) 334#define MX23_PAD_EMI_A03__GPIO_2_12 MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_GPIO)
335#define MX23_PAD_EMI_A04__GPO_2_13 MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_GPIO) 335#define MX23_PAD_EMI_A04__GPIO_2_13 MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_GPIO)
336#define MX23_PAD_EMI_A05__GPO_2_14 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_GPIO) 336#define MX23_PAD_EMI_A05__GPIO_2_14 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_GPIO)
337#define MX23_PAD_EMI_A06__GPO_2_15 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_GPIO) 337#define MX23_PAD_EMI_A06__GPIO_2_15 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_GPIO)
338#define MX23_PAD_EMI_A07__GPO_2_16 MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_GPIO) 338#define MX23_PAD_EMI_A07__GPIO_2_16 MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_GPIO)
339#define MX23_PAD_EMI_A08__GPO_2_17 MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_GPIO) 339#define MX23_PAD_EMI_A08__GPIO_2_17 MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_GPIO)
340#define MX23_PAD_EMI_A09__GPO_2_18 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_GPIO) 340#define MX23_PAD_EMI_A09__GPIO_2_18 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_GPIO)
341#define MX23_PAD_EMI_A10__GPO_2_19 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_GPIO) 341#define MX23_PAD_EMI_A10__GPIO_2_19 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_GPIO)
342#define MX23_PAD_EMI_A11__GPO_2_20 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_GPIO) 342#define MX23_PAD_EMI_A11__GPIO_2_20 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_GPIO)
343#define MX23_PAD_EMI_A12__GPO_2_21 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_GPIO) 343#define MX23_PAD_EMI_A12__GPIO_2_21 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_GPIO)
344#define MX23_PAD_EMI_BA0__GPO_2_22 MXS_IOMUX_PAD_NAKED(2, 22, PAD_MUXSEL_GPIO) 344#define MX23_PAD_EMI_BA0__GPIO_2_22 MXS_IOMUX_PAD_NAKED(2, 22, PAD_MUXSEL_GPIO)
345#define MX23_PAD_EMI_BA1__GPO_2_23 MXS_IOMUX_PAD_NAKED(2, 23, PAD_MUXSEL_GPIO) 345#define MX23_PAD_EMI_BA1__GPIO_2_23 MXS_IOMUX_PAD_NAKED(2, 23, PAD_MUXSEL_GPIO)
346#define MX23_PAD_EMI_CASN__GPO_2_24 MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_GPIO) 346#define MX23_PAD_EMI_CASN__GPIO_2_24 MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_GPIO)
347#define MX23_PAD_EMI_CE0N__GPO_2_25 MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_GPIO) 347#define MX23_PAD_EMI_CE0N__GPIO_2_25 MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_GPIO)
348#define MX23_PAD_EMI_CE1N__GPO_2_26 MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_GPIO) 348#define MX23_PAD_EMI_CE1N__GPIO_2_26 MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_GPIO)
349#define MX23_PAD_GPMI_CE1N__GPO_2_27 MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_GPIO) 349#define MX23_PAD_GPMI_CE1N__GPIO_2_27 MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_GPIO)
350#define MX23_PAD_GPMI_CE0N__GPO_2_28 MXS_IOMUX_PAD_NAKED(2, 28, PAD_MUXSEL_GPIO) 350#define MX23_PAD_GPMI_CE0N__GPIO_2_28 MXS_IOMUX_PAD_NAKED(2, 28, PAD_MUXSEL_GPIO)
351#define MX23_PAD_EMI_CKE__GPO_2_29 MXS_IOMUX_PAD_NAKED(2, 29, PAD_MUXSEL_GPIO) 351#define MX23_PAD_EMI_CKE__GPIO_2_29 MXS_IOMUX_PAD_NAKED(2, 29, PAD_MUXSEL_GPIO)
352#define MX23_PAD_EMI_RASN__GPO_2_30 MXS_IOMUX_PAD_NAKED(2, 30, PAD_MUXSEL_GPIO) 352#define MX23_PAD_EMI_RASN__GPIO_2_30 MXS_IOMUX_PAD_NAKED(2, 30, PAD_MUXSEL_GPIO)
353#define MX23_PAD_EMI_WEN__GPO_2_31 MXS_IOMUX_PAD_NAKED(2, 31, PAD_MUXSEL_GPIO) 353#define MX23_PAD_EMI_WEN__GPIO_2_31 MXS_IOMUX_PAD_NAKED(2, 31, PAD_MUXSEL_GPIO)
354 354
355#endif /* __MACH_IOMUX_MX23_H__ */ 355#endif /* __MACH_IOMUX_MX23_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/iomux.h b/arch/arm/mach-mxs/include/mach/iomux.h
index fe558e3c5a9a..7abdf58b8bb7 100644
--- a/arch/arm/mach-mxs/include/mach/iomux.h
+++ b/arch/arm/mach-mxs/include/mach/iomux.h
@@ -91,6 +91,9 @@ typedef u32 iomux_cfg_t;
91#define MXS_PAD_PULLUP ((PAD_PULLUP << MXS_PAD_PULL_SHIFT) | \ 91#define MXS_PAD_PULLUP ((PAD_PULLUP << MXS_PAD_PULL_SHIFT) | \
92 MXS_PAD_PULL_VALID_MASK) 92 MXS_PAD_PULL_VALID_MASK)
93 93
94/* generic pad control used in most cases */
95#define MXS_PAD_CTRL (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL)
96
94#define MXS_IOMUX_PAD(_bank, _pin, _muxsel, _ma, _vol, _pull) \ 97#define MXS_IOMUX_PAD(_bank, _pin, _muxsel, _ma, _vol, _pull) \
95 (((iomux_cfg_t)(_bank) << MXS_PAD_BANK_SHIFT) | \ 98 (((iomux_cfg_t)(_bank) << MXS_PAD_BANK_SHIFT) | \
96 ((iomux_cfg_t)(_pin) << MXS_PAD_PIN_SHIFT) | \ 99 ((iomux_cfg_t)(_pin) << MXS_PAD_PIN_SHIFT) | \
diff --git a/arch/arm/mach-mxs/include/mach/mx23.h b/arch/arm/mach-mxs/include/mach/mx23.h
index 9edd02ec8e30..c0a18c23084a 100644
--- a/arch/arm/mach-mxs/include/mach/mx23.h
+++ b/arch/arm/mach-mxs/include/mach/mx23.h
@@ -93,7 +93,7 @@
93#define MX23_INT_USB_WAKEUP 12 93#define MX23_INT_USB_WAKEUP 12
94#define MX23_INT_GPMI_DMA 13 94#define MX23_INT_GPMI_DMA 13
95#define MX23_INT_SSP1_DMA 14 95#define MX23_INT_SSP1_DMA 14
96#define MX23_INT_SSP_ERROR 15 96#define MX23_INT_SSP1_ERROR 15
97#define MX23_INT_GPIO0 16 97#define MX23_INT_GPIO0 16
98#define MX23_INT_GPIO1 17 98#define MX23_INT_GPIO1 17
99#define MX23_INT_GPIO2 18 99#define MX23_INT_GPIO2 18
@@ -101,9 +101,9 @@
101#define MX23_INT_SSP2_DMA 20 101#define MX23_INT_SSP2_DMA 20
102#define MX23_INT_ECC8_IRQ 21 102#define MX23_INT_ECC8_IRQ 21
103#define MX23_INT_RTC_ALARM 22 103#define MX23_INT_RTC_ALARM 22
104#define MX23_INT_UARTAPP_TX_DMA 23 104#define MX23_INT_AUART1_TX_DMA 23
105#define MX23_INT_UARTAPP_INTERNAL 24 105#define MX23_INT_AUART1 24
106#define MX23_INT_UARTAPP_RX_DMA 25 106#define MX23_INT_AUART1_RX_DMA 25
107#define MX23_INT_I2C_DMA 26 107#define MX23_INT_I2C_DMA 26
108#define MX23_INT_I2C_ERROR 27 108#define MX23_INT_I2C_ERROR 27
109#define MX23_INT_TIMER0 28 109#define MX23_INT_TIMER0 28
@@ -135,11 +135,35 @@
135#define MX23_INT_DCP 54 135#define MX23_INT_DCP 54
136#define MX23_INT_BCH 56 136#define MX23_INT_BCH 56
137#define MX23_INT_PXP 57 137#define MX23_INT_PXP 57
138#define MX23_INT_UARTAPP2_TX_DMA 58 138#define MX23_INT_AUART2_TX_DMA 58
139#define MX23_INT_UARTAPP2_INTERNAL 59 139#define MX23_INT_AUART2 59
140#define MX23_INT_UARTAPP2_RX_DMA 60 140#define MX23_INT_AUART2_RX_DMA 60
141#define MX23_INT_VDAC_DETECT 61 141#define MX23_INT_VDAC_DETECT 61
142#define MX23_INT_VDD5V_DROOP 64 142#define MX23_INT_VDD5V_DROOP 64
143#define MX23_INT_DCDC4P2_BO 65 143#define MX23_INT_DCDC4P2_BO 65
144 144
145/*
146 * APBH DMA
147 */
148#define MX23_DMA_SSP1 1
149#define MX23_DMA_SSP2 2
150#define MX23_DMA_GPMI0 4
151#define MX23_DMA_GPMI1 5
152#define MX23_DMA_GPMI2 6
153#define MX23_DMA_GPMI3 7
154
155/*
156 * APBX DMA
157 */
158#define MX23_DMA_ADC 0
159#define MX23_DMA_DAC 1
160#define MX23_DMA_SPDIF 2
161#define MX23_DMA_I2C 3
162#define MX23_DMA_SAIF0 4
163#define MX23_DMA_UART0_RX 6
164#define MX23_DMA_UART0_TX 7
165#define MX23_DMA_UART1_RX 8
166#define MX23_DMA_UART1_TX 9
167#define MX23_DMA_SAIF1 10
168
145#endif /* __MACH_MX23_H__ */ 169#endif /* __MACH_MX23_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/mx28.h b/arch/arm/mach-mxs/include/mach/mx28.h
index 0716745267ad..75d86118b76a 100644
--- a/arch/arm/mach-mxs/include/mach/mx28.h
+++ b/arch/arm/mach-mxs/include/mach/mx28.h
@@ -163,10 +163,10 @@
163#define MX28_INT_USB0 93 163#define MX28_INT_USB0 93
164#define MX28_INT_USB1_WAKEUP 94 164#define MX28_INT_USB1_WAKEUP 94
165#define MX28_INT_USB0_WAKEUP 95 165#define MX28_INT_USB0_WAKEUP 95
166#define MX28_INT_SSP0 96 166#define MX28_INT_SSP0_ERROR 96
167#define MX28_INT_SSP1 97 167#define MX28_INT_SSP1_ERROR 97
168#define MX28_INT_SSP2 98 168#define MX28_INT_SSP2_ERROR 98
169#define MX28_INT_SSP3 99 169#define MX28_INT_SSP3_ERROR 99
170#define MX28_INT_ENET_SWI 100 170#define MX28_INT_ENET_SWI 100
171#define MX28_INT_ENET_MAC0 101 171#define MX28_INT_ENET_MAC0 101
172#define MX28_INT_ENET_MAC1 102 172#define MX28_INT_ENET_MAC1 102
@@ -185,4 +185,41 @@
185#define MX28_INT_GPIO1 126 185#define MX28_INT_GPIO1 126
186#define MX28_INT_GPIO0 127 186#define MX28_INT_GPIO0 127
187 187
188/*
189 * APBH DMA
190 */
191#define MX28_DMA_SSP0 0
192#define MX28_DMA_SSP1 1
193#define MX28_DMA_SSP2 2
194#define MX28_DMA_SSP3 3
195#define MX28_DMA_GPMI0 4
196#define MX28_DMA_GPMI1 5
197#define MX28_DMA_GPMI2 6
198#define MX28_DMA_GPMI3 7
199#define MX28_DMA_GPMI4 8
200#define MX28_DMA_GPMI5 9
201#define MX28_DMA_GPMI6 10
202#define MX28_DMA_GPMI7 11
203#define MX28_DMA_HSADC 12
204#define MX28_DMA_LCDIF 13
205
206/*
207 * APBX DMA
208 */
209#define MX28_DMA_AUART4_RX 0
210#define MX28_DMA_AUART4_TX 1
211#define MX28_DMA_SPDIF_TX 2
212#define MX28_DMA_SAIF0 4
213#define MX28_DMA_SAIF1 5
214#define MX28_DMA_I2C0 6
215#define MX28_DMA_I2C1 7
216#define MX28_DMA_AUART0_RX 8
217#define MX28_DMA_AUART0_TX 9
218#define MX28_DMA_AUART1_RX 10
219#define MX28_DMA_AUART1_TX 11
220#define MX28_DMA_AUART2_RX 12
221#define MX28_DMA_AUART2_TX 13
222#define MX28_DMA_AUART3_RX 14
223#define MX28_DMA_AUART3_TX 15
224
188#endif /* __MACH_MX28_H__ */ 225#endif /* __MACH_MX28_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/mxs.h b/arch/arm/mach-mxs/include/mach/mxs.h
index f186c08c2911..35a89dd27242 100644
--- a/arch/arm/mach-mxs/include/mach/mxs.h
+++ b/arch/arm/mach-mxs/include/mach/mxs.h
@@ -28,8 +28,13 @@
28/* 28/*
29 * MXS CPU types 29 * MXS CPU types
30 */ 30 */
31#define cpu_is_mx23() (machine_is_mx23evk()) 31#define cpu_is_mx23() ( \
32#define cpu_is_mx28() (machine_is_mx28evk()) 32 machine_is_mx23evk() || \
33 0)
34#define cpu_is_mx28() ( \
35 machine_is_mx28evk() || \
36 machine_is_tx28() || \
37 0)
33 38
34/* 39/*
35 * IO addresses common to MXS-based 40 * IO addresses common to MXS-based
diff --git a/arch/arm/mach-mxs/include/mach/mxsfb.h b/arch/arm/mach-mxs/include/mach/mxsfb.h
new file mode 100644
index 000000000000..e4d79791515e
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/mxsfb.h
@@ -0,0 +1,49 @@
1/*
2 * This program is free software; you can redistribute it and/or
3 * modify it under the terms of the GNU General Public License
4 * as published by the Free Software Foundation; either version 2
5 * of the License, or (at your option) any later version.
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
14 * MA 02110-1301, USA.
15 */
16
17#ifndef __MACH_FB_H
18#define __MACH_FB_H
19
20#include <linux/fb.h>
21
22#define STMLCDIF_8BIT 1 /** pixel data bus to the display is of 8 bit width */
23#define STMLCDIF_16BIT 0 /** pixel data bus to the display is of 16 bit width */
24#define STMLCDIF_18BIT 2 /** pixel data bus to the display is of 18 bit width */
25#define STMLCDIF_24BIT 3 /** pixel data bus to the display is of 24 bit width */
26
27#define FB_SYNC_DATA_ENABLE_HIGH_ACT (1 << 6)
28#define FB_SYNC_DOTCLK_FAILING_ACT (1 << 7) /* failing/negtive edge sampling */
29
30struct mxsfb_platform_data {
31 struct fb_videomode *mode_list;
32 unsigned mode_count;
33
34 unsigned default_bpp;
35
36 unsigned dotclk_delay; /* refer manual HW_LCDIF_VDCTRL4 register */
37 unsigned ld_intf_width; /* refer STMLCDIF_* macros */
38
39 unsigned fb_size; /* Size of the video memory. If zero a
40 * default will be used
41 */
42 unsigned long fb_phys; /* physical address for the video memory. If
43 * zero the framebuffer memory will be dynamically
44 * allocated. If specified,fb_size must also be specified.
45 * fb_phys must be unused by Linux.
46 */
47};
48
49#endif /* __MACH_FB_H */
diff --git a/arch/arm/mach-mxs/include/mach/uncompress.h b/arch/arm/mach-mxs/include/mach/uncompress.h
index a005e76f34f9..f12a1732d8b8 100644
--- a/arch/arm/mach-mxs/include/mach/uncompress.h
+++ b/arch/arm/mach-mxs/include/mach/uncompress.h
@@ -63,6 +63,7 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
63 mxs_duart_base = MX23_DUART_BASE_ADDR; 63 mxs_duart_base = MX23_DUART_BASE_ADDR;
64 break; 64 break;
65 case MACH_TYPE_MX28EVK: 65 case MACH_TYPE_MX28EVK:
66 case MACH_TYPE_TX28:
66 mxs_duart_base = MX28_DUART_BASE_ADDR; 67 mxs_duart_base = MX28_DUART_BASE_ADDR;
67 break; 68 break;
68 default: 69 default:
diff --git a/arch/arm/mach-mxs/mach-mx23evk.c b/arch/arm/mach-mxs/mach-mx23evk.c
index aa0640052f58..a66994f0518f 100644
--- a/arch/arm/mach-mxs/mach-mx23evk.c
+++ b/arch/arm/mach-mxs/mach-mx23evk.c
@@ -26,17 +26,103 @@
26 26
27#include "devices-mx23.h" 27#include "devices-mx23.h"
28 28
29#define MX23EVK_LCD_ENABLE MXS_GPIO_NR(1, 18)
30#define MX23EVK_BL_ENABLE MXS_GPIO_NR(1, 28)
31
29static const iomux_cfg_t mx23evk_pads[] __initconst = { 32static const iomux_cfg_t mx23evk_pads[] __initconst = {
30 /* duart */ 33 /* duart */
31 MX23_PAD_PWM0__DUART_RX | MXS_PAD_4MA, 34 MX23_PAD_PWM0__DUART_RX | MXS_PAD_CTRL,
32 MX23_PAD_PWM1__DUART_TX | MXS_PAD_4MA, 35 MX23_PAD_PWM1__DUART_TX | MXS_PAD_CTRL,
36
37 /* auart */
38 MX23_PAD_AUART1_RX__AUART1_RX | MXS_PAD_CTRL,
39 MX23_PAD_AUART1_TX__AUART1_TX | MXS_PAD_CTRL,
40 MX23_PAD_AUART1_CTS__AUART1_CTS | MXS_PAD_CTRL,
41 MX23_PAD_AUART1_RTS__AUART1_RTS | MXS_PAD_CTRL,
42
43 /* mxsfb (lcdif) */
44 MX23_PAD_LCD_D00__LCD_D00 | MXS_PAD_CTRL,
45 MX23_PAD_LCD_D01__LCD_D01 | MXS_PAD_CTRL,
46 MX23_PAD_LCD_D02__LCD_D02 | MXS_PAD_CTRL,
47 MX23_PAD_LCD_D03__LCD_D03 | MXS_PAD_CTRL,
48 MX23_PAD_LCD_D04__LCD_D04 | MXS_PAD_CTRL,
49 MX23_PAD_LCD_D05__LCD_D05 | MXS_PAD_CTRL,
50 MX23_PAD_LCD_D06__LCD_D06 | MXS_PAD_CTRL,
51 MX23_PAD_LCD_D07__LCD_D07 | MXS_PAD_CTRL,
52 MX23_PAD_LCD_D08__LCD_D08 | MXS_PAD_CTRL,
53 MX23_PAD_LCD_D09__LCD_D09 | MXS_PAD_CTRL,
54 MX23_PAD_LCD_D10__LCD_D10 | MXS_PAD_CTRL,
55 MX23_PAD_LCD_D11__LCD_D11 | MXS_PAD_CTRL,
56 MX23_PAD_LCD_D12__LCD_D12 | MXS_PAD_CTRL,
57 MX23_PAD_LCD_D13__LCD_D13 | MXS_PAD_CTRL,
58 MX23_PAD_LCD_D14__LCD_D14 | MXS_PAD_CTRL,
59 MX23_PAD_LCD_D15__LCD_D15 | MXS_PAD_CTRL,
60 MX23_PAD_LCD_D16__LCD_D16 | MXS_PAD_CTRL,
61 MX23_PAD_LCD_D17__LCD_D17 | MXS_PAD_CTRL,
62 MX23_PAD_GPMI_D08__LCD_D18 | MXS_PAD_CTRL,
63 MX23_PAD_GPMI_D09__LCD_D19 | MXS_PAD_CTRL,
64 MX23_PAD_GPMI_D10__LCD_D20 | MXS_PAD_CTRL,
65 MX23_PAD_GPMI_D11__LCD_D21 | MXS_PAD_CTRL,
66 MX23_PAD_GPMI_D12__LCD_D22 | MXS_PAD_CTRL,
67 MX23_PAD_GPMI_D13__LCD_D23 | MXS_PAD_CTRL,
68 MX23_PAD_LCD_VSYNC__LCD_VSYNC | MXS_PAD_CTRL,
69 MX23_PAD_LCD_HSYNC__LCD_HSYNC | MXS_PAD_CTRL,
70 MX23_PAD_LCD_DOTCK__LCD_DOTCK | MXS_PAD_CTRL,
71 MX23_PAD_LCD_ENABLE__LCD_ENABLE | MXS_PAD_CTRL,
72 /* LCD panel enable */
73 MX23_PAD_LCD_RESET__GPIO_1_18 | MXS_PAD_CTRL,
74 /* backlight control */
75 MX23_PAD_PWM2__GPIO_1_28 | MXS_PAD_CTRL,
76};
77
78/* mxsfb (lcdif) */
79static struct fb_videomode mx23evk_video_modes[] = {
80 {
81 .name = "Samsung-LMS430HF02",
82 .refresh = 60,
83 .xres = 480,
84 .yres = 272,
85 .pixclock = 108096, /* picosecond (9.2 MHz) */
86 .left_margin = 15,
87 .right_margin = 8,
88 .upper_margin = 12,
89 .lower_margin = 4,
90 .hsync_len = 1,
91 .vsync_len = 1,
92 .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT |
93 FB_SYNC_DOTCLK_FAILING_ACT,
94 },
95};
96
97static const struct mxsfb_platform_data mx23evk_mxsfb_pdata __initconst = {
98 .mode_list = mx23evk_video_modes,
99 .mode_count = ARRAY_SIZE(mx23evk_video_modes),
100 .default_bpp = 32,
101 .ld_intf_width = STMLCDIF_24BIT,
33}; 102};
34 103
35static void __init mx23evk_init(void) 104static void __init mx23evk_init(void)
36{ 105{
106 int ret;
107
37 mxs_iomux_setup_multiple_pads(mx23evk_pads, ARRAY_SIZE(mx23evk_pads)); 108 mxs_iomux_setup_multiple_pads(mx23evk_pads, ARRAY_SIZE(mx23evk_pads));
38 109
39 mx23_add_duart(); 110 mx23_add_duart();
111 mx23_add_auart0();
112
113 ret = gpio_request_one(MX23EVK_LCD_ENABLE, GPIOF_DIR_OUT, "lcd-enable");
114 if (ret)
115 pr_warn("failed to request gpio lcd-enable: %d\n", ret);
116 else
117 gpio_set_value(MX23EVK_LCD_ENABLE, 1);
118
119 ret = gpio_request_one(MX23EVK_BL_ENABLE, GPIOF_DIR_OUT, "bl-enable");
120 if (ret)
121 pr_warn("failed to request gpio bl-enable: %d\n", ret);
122 else
123 gpio_set_value(MX23EVK_BL_ENABLE, 1);
124
125 mx23_add_mxsfb(&mx23evk_mxsfb_pdata);
40} 126}
41 127
42static void __init mx23evk_timer_init(void) 128static void __init mx23evk_timer_init(void)
diff --git a/arch/arm/mach-mxs/mach-mx28evk.c b/arch/arm/mach-mxs/mach-mx28evk.c
index 8e2c5975001e..08002d02267a 100644
--- a/arch/arm/mach-mxs/mach-mx28evk.c
+++ b/arch/arm/mach-mxs/mach-mx28evk.c
@@ -28,54 +28,93 @@
28#include "devices-mx28.h" 28#include "devices-mx28.h"
29#include "gpio.h" 29#include "gpio.h"
30 30
31#define MX28EVK_FLEXCAN_SWITCH MXS_GPIO_NR(2, 13)
31#define MX28EVK_FEC_PHY_POWER MXS_GPIO_NR(2, 15) 32#define MX28EVK_FEC_PHY_POWER MXS_GPIO_NR(2, 15)
33#define MX28EVK_BL_ENABLE MXS_GPIO_NR(3, 18)
34#define MX28EVK_LCD_ENABLE MXS_GPIO_NR(3, 30)
32#define MX28EVK_FEC_PHY_RESET MXS_GPIO_NR(4, 13) 35#define MX28EVK_FEC_PHY_RESET MXS_GPIO_NR(4, 13)
33 36
34static const iomux_cfg_t mx28evk_pads[] __initconst = { 37static const iomux_cfg_t mx28evk_pads[] __initconst = {
35 /* duart */ 38 /* duart */
36 MX28_PAD_PWM0__DUART_RX | 39 MX28_PAD_PWM0__DUART_RX | MXS_PAD_CTRL,
37 (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), 40 MX28_PAD_PWM1__DUART_TX | MXS_PAD_CTRL,
38 MX28_PAD_PWM1__DUART_TX |
39 (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
40 41
42 /* auart0 */
43 MX28_PAD_AUART0_RX__AUART0_RX | MXS_PAD_CTRL,
44 MX28_PAD_AUART0_TX__AUART0_TX | MXS_PAD_CTRL,
45 MX28_PAD_AUART0_CTS__AUART0_CTS | MXS_PAD_CTRL,
46 MX28_PAD_AUART0_RTS__AUART0_RTS | MXS_PAD_CTRL,
47 /* auart3 */
48 MX28_PAD_AUART3_RX__AUART3_RX | MXS_PAD_CTRL,
49 MX28_PAD_AUART3_TX__AUART3_TX | MXS_PAD_CTRL,
50 MX28_PAD_AUART3_CTS__AUART3_CTS | MXS_PAD_CTRL,
51 MX28_PAD_AUART3_RTS__AUART3_RTS | MXS_PAD_CTRL,
52
53#define MXS_PAD_FEC (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP)
41 /* fec0 */ 54 /* fec0 */
42 MX28_PAD_ENET0_MDC__ENET0_MDC | 55 MX28_PAD_ENET0_MDC__ENET0_MDC | MXS_PAD_FEC,
43 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), 56 MX28_PAD_ENET0_MDIO__ENET0_MDIO | MXS_PAD_FEC,
44 MX28_PAD_ENET0_MDIO__ENET0_MDIO | 57 MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MXS_PAD_FEC,
45 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), 58 MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MXS_PAD_FEC,
46 MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | 59 MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MXS_PAD_FEC,
47 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), 60 MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MXS_PAD_FEC,
48 MX28_PAD_ENET0_RXD0__ENET0_RXD0 | 61 MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MXS_PAD_FEC,
49 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), 62 MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MXS_PAD_FEC,
50 MX28_PAD_ENET0_RXD1__ENET0_RXD1 | 63 MX28_PAD_ENET_CLK__CLKCTRL_ENET | MXS_PAD_FEC,
51 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
52 MX28_PAD_ENET0_TX_EN__ENET0_TX_EN |
53 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
54 MX28_PAD_ENET0_TXD0__ENET0_TXD0 |
55 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
56 MX28_PAD_ENET0_TXD1__ENET0_TXD1 |
57 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
58 MX28_PAD_ENET_CLK__CLKCTRL_ENET |
59 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
60 /* fec1 */ 64 /* fec1 */
61 MX28_PAD_ENET0_CRS__ENET1_RX_EN | 65 MX28_PAD_ENET0_CRS__ENET1_RX_EN | MXS_PAD_FEC,
62 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), 66 MX28_PAD_ENET0_RXD2__ENET1_RXD0 | MXS_PAD_FEC,
63 MX28_PAD_ENET0_RXD2__ENET1_RXD0 | 67 MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MXS_PAD_FEC,
64 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), 68 MX28_PAD_ENET0_COL__ENET1_TX_EN | MXS_PAD_FEC,
65 MX28_PAD_ENET0_RXD3__ENET1_RXD1 | 69 MX28_PAD_ENET0_TXD2__ENET1_TXD0 | MXS_PAD_FEC,
66 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), 70 MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MXS_PAD_FEC,
67 MX28_PAD_ENET0_COL__ENET1_TX_EN |
68 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
69 MX28_PAD_ENET0_TXD2__ENET1_TXD0 |
70 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
71 MX28_PAD_ENET0_TXD3__ENET1_TXD1 |
72 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
73 /* phy power line */ 71 /* phy power line */
74 MX28_PAD_SSP1_DATA3__GPIO_2_15 | 72 MX28_PAD_SSP1_DATA3__GPIO_2_15 | MXS_PAD_CTRL,
75 (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
76 /* phy reset line */ 73 /* phy reset line */
77 MX28_PAD_ENET0_RX_CLK__GPIO_4_13 | 74 MX28_PAD_ENET0_RX_CLK__GPIO_4_13 | MXS_PAD_CTRL,
78 (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), 75
76 /* flexcan0 */
77 MX28_PAD_GPMI_RDY2__CAN0_TX,
78 MX28_PAD_GPMI_RDY3__CAN0_RX,
79 /* flexcan1 */
80 MX28_PAD_GPMI_CE2N__CAN1_TX,
81 MX28_PAD_GPMI_CE3N__CAN1_RX,
82 /* transceiver power control */
83 MX28_PAD_SSP1_CMD__GPIO_2_13,
84
85 /* mxsfb (lcdif) */
86 MX28_PAD_LCD_D00__LCD_D0 | MXS_PAD_CTRL,
87 MX28_PAD_LCD_D01__LCD_D1 | MXS_PAD_CTRL,
88 MX28_PAD_LCD_D02__LCD_D2 | MXS_PAD_CTRL,
89 MX28_PAD_LCD_D03__LCD_D3 | MXS_PAD_CTRL,
90 MX28_PAD_LCD_D04__LCD_D4 | MXS_PAD_CTRL,
91 MX28_PAD_LCD_D05__LCD_D5 | MXS_PAD_CTRL,
92 MX28_PAD_LCD_D06__LCD_D6 | MXS_PAD_CTRL,
93 MX28_PAD_LCD_D07__LCD_D7 | MXS_PAD_CTRL,
94 MX28_PAD_LCD_D08__LCD_D8 | MXS_PAD_CTRL,
95 MX28_PAD_LCD_D09__LCD_D9 | MXS_PAD_CTRL,
96 MX28_PAD_LCD_D10__LCD_D10 | MXS_PAD_CTRL,
97 MX28_PAD_LCD_D11__LCD_D11 | MXS_PAD_CTRL,
98 MX28_PAD_LCD_D12__LCD_D12 | MXS_PAD_CTRL,
99 MX28_PAD_LCD_D13__LCD_D13 | MXS_PAD_CTRL,
100 MX28_PAD_LCD_D14__LCD_D14 | MXS_PAD_CTRL,
101 MX28_PAD_LCD_D15__LCD_D15 | MXS_PAD_CTRL,
102 MX28_PAD_LCD_D16__LCD_D16 | MXS_PAD_CTRL,
103 MX28_PAD_LCD_D17__LCD_D17 | MXS_PAD_CTRL,
104 MX28_PAD_LCD_D18__LCD_D18 | MXS_PAD_CTRL,
105 MX28_PAD_LCD_D19__LCD_D19 | MXS_PAD_CTRL,
106 MX28_PAD_LCD_D20__LCD_D20 | MXS_PAD_CTRL,
107 MX28_PAD_LCD_D21__LCD_D21 | MXS_PAD_CTRL,
108 MX28_PAD_LCD_D22__LCD_D22 | MXS_PAD_CTRL,
109 MX28_PAD_LCD_D23__LCD_D23 | MXS_PAD_CTRL,
110 MX28_PAD_LCD_RD_E__LCD_VSYNC | MXS_PAD_CTRL,
111 MX28_PAD_LCD_WR_RWN__LCD_HSYNC | MXS_PAD_CTRL,
112 MX28_PAD_LCD_RS__LCD_DOTCLK | MXS_PAD_CTRL,
113 MX28_PAD_LCD_CS__LCD_ENABLE | MXS_PAD_CTRL,
114 /* LCD panel enable */
115 MX28_PAD_LCD_RESET__GPIO_3_30 | MXS_PAD_CTRL,
116 /* backlight control */
117 MX28_PAD_PWM2__GPIO_3_18 | MXS_PAD_CTRL,
79}; 118};
80 119
81/* fec */ 120/* fec */
@@ -119,7 +158,7 @@ static void __init mx28evk_fec_reset(void)
119 gpio_set_value(MX28EVK_FEC_PHY_RESET, 1); 158 gpio_set_value(MX28EVK_FEC_PHY_RESET, 1);
120} 159}
121 160
122static struct fec_platform_data mx28_fec_pdata[] = { 161static struct fec_platform_data mx28_fec_pdata[] __initdata = {
123 { 162 {
124 /* fec0 */ 163 /* fec0 */
125 .phy = PHY_INTERFACE_MODE_RMII, 164 .phy = PHY_INTERFACE_MODE_RMII,
@@ -129,15 +168,135 @@ static struct fec_platform_data mx28_fec_pdata[] = {
129 }, 168 },
130}; 169};
131 170
171static int __init mx28evk_fec_get_mac(void)
172{
173 int i;
174 u32 val;
175 const u32 *ocotp = mxs_get_ocotp();
176
177 if (!ocotp)
178 goto error;
179
180 /*
181 * OCOTP only stores the last 4 octets for each mac address,
182 * so hard-code Freescale OUI (00:04:9f) here.
183 */
184 for (i = 0; i < 2; i++) {
185 val = ocotp[i * 4];
186 mx28_fec_pdata[i].mac[0] = 0x00;
187 mx28_fec_pdata[i].mac[1] = 0x04;
188 mx28_fec_pdata[i].mac[2] = 0x9f;
189 mx28_fec_pdata[i].mac[3] = (val >> 16) & 0xff;
190 mx28_fec_pdata[i].mac[4] = (val >> 8) & 0xff;
191 mx28_fec_pdata[i].mac[5] = (val >> 0) & 0xff;
192 }
193
194 return 0;
195
196error:
197 pr_err("%s: timeout when reading fec mac from OCOTP\n", __func__);
198 return -ETIMEDOUT;
199}
200
201/*
202 * MX28EVK_FLEXCAN_SWITCH is shared between both flexcan controllers
203 */
204static int flexcan0_en, flexcan1_en;
205
206static void mx28evk_flexcan_switch(void)
207{
208 if (flexcan0_en || flexcan1_en)
209 gpio_set_value(MX28EVK_FLEXCAN_SWITCH, 1);
210 else
211 gpio_set_value(MX28EVK_FLEXCAN_SWITCH, 0);
212}
213
214static void mx28evk_flexcan0_switch(int enable)
215{
216 flexcan0_en = enable;
217 mx28evk_flexcan_switch();
218}
219
220static void mx28evk_flexcan1_switch(int enable)
221{
222 flexcan1_en = enable;
223 mx28evk_flexcan_switch();
224}
225
226static const struct flexcan_platform_data
227 mx28evk_flexcan_pdata[] __initconst = {
228 {
229 .transceiver_switch = mx28evk_flexcan0_switch,
230 }, {
231 .transceiver_switch = mx28evk_flexcan1_switch,
232 }
233};
234
235/* mxsfb (lcdif) */
236static struct fb_videomode mx28evk_video_modes[] = {
237 {
238 .name = "Seiko-43WVF1G",
239 .refresh = 60,
240 .xres = 800,
241 .yres = 480,
242 .pixclock = 29851, /* picosecond (33.5 MHz) */
243 .left_margin = 89,
244 .right_margin = 164,
245 .upper_margin = 23,
246 .lower_margin = 10,
247 .hsync_len = 10,
248 .vsync_len = 10,
249 .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT |
250 FB_SYNC_DOTCLK_FAILING_ACT,
251 },
252};
253
254static const struct mxsfb_platform_data mx28evk_mxsfb_pdata __initconst = {
255 .mode_list = mx28evk_video_modes,
256 .mode_count = ARRAY_SIZE(mx28evk_video_modes),
257 .default_bpp = 32,
258 .ld_intf_width = STMLCDIF_24BIT,
259};
260
132static void __init mx28evk_init(void) 261static void __init mx28evk_init(void)
133{ 262{
263 int ret;
264
134 mxs_iomux_setup_multiple_pads(mx28evk_pads, ARRAY_SIZE(mx28evk_pads)); 265 mxs_iomux_setup_multiple_pads(mx28evk_pads, ARRAY_SIZE(mx28evk_pads));
135 266
136 mx28_add_duart(); 267 mx28_add_duart();
268 mx28_add_auart0();
269 mx28_add_auart3();
270
271 if (mx28evk_fec_get_mac())
272 pr_warn("%s: failed on fec mac setup\n", __func__);
137 273
138 mx28evk_fec_reset(); 274 mx28evk_fec_reset();
139 mx28_add_fec(0, &mx28_fec_pdata[0]); 275 mx28_add_fec(0, &mx28_fec_pdata[0]);
140 mx28_add_fec(1, &mx28_fec_pdata[1]); 276 mx28_add_fec(1, &mx28_fec_pdata[1]);
277
278 ret = gpio_request_one(MX28EVK_FLEXCAN_SWITCH, GPIOF_DIR_OUT,
279 "flexcan-switch");
280 if (ret) {
281 pr_err("failed to request gpio flexcan-switch: %d\n", ret);
282 } else {
283 mx28_add_flexcan(0, &mx28evk_flexcan_pdata[0]);
284 mx28_add_flexcan(1, &mx28evk_flexcan_pdata[1]);
285 }
286
287 ret = gpio_request_one(MX28EVK_LCD_ENABLE, GPIOF_DIR_OUT, "lcd-enable");
288 if (ret)
289 pr_warn("failed to request gpio lcd-enable: %d\n", ret);
290 else
291 gpio_set_value(MX28EVK_LCD_ENABLE, 1);
292
293 ret = gpio_request_one(MX28EVK_BL_ENABLE, GPIOF_DIR_OUT, "bl-enable");
294 if (ret)
295 pr_warn("failed to request gpio bl-enable: %d\n", ret);
296 else
297 gpio_set_value(MX28EVK_BL_ENABLE, 1);
298
299 mx28_add_mxsfb(&mx28evk_mxsfb_pdata);
141} 300}
142 301
143static void __init mx28evk_timer_init(void) 302static void __init mx28evk_timer_init(void)
diff --git a/arch/arm/mach-mxs/mach-tx28.c b/arch/arm/mach-mxs/mach-tx28.c
new file mode 100644
index 000000000000..b65e3719cbc4
--- /dev/null
+++ b/arch/arm/mach-mxs/mach-tx28.c
@@ -0,0 +1,183 @@
1/*
2 * Copyright (C) 2010 <LW@KARO-electronics.de>
3 *
4 * based on: mach-mx28_evk.c
5 * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * version 2 as published by the Free Software Foundation
10 */
11#include <linux/kernel.h>
12#include <linux/gpio.h>
13#include <linux/leds.h>
14#include <linux/platform_device.h>
15#include <linux/spi/spi.h>
16#include <linux/spi/spi_gpio.h>
17#include <linux/i2c.h>
18
19#include <asm/mach/arch.h>
20#include <asm/mach/time.h>
21
22#include <mach/common.h>
23#include <mach/iomux-mx28.h>
24
25#include "devices-mx28.h"
26#include "module-tx28.h"
27
28#define TX28_STK5_GPIO_LED MXS_GPIO_NR(4, 10)
29
30static const iomux_cfg_t tx28_stk5v3_pads[] __initconst = {
31 /* LED */
32 MX28_PAD_ENET0_RXD3__GPIO_4_10 |
33 MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL,
34
35 /* framebuffer */
36#define LCD_MODE (MXS_PAD_3V3 | MXS_PAD_4MA)
37 MX28_PAD_LCD_D00__LCD_D0 | LCD_MODE,
38 MX28_PAD_LCD_D01__LCD_D1 | LCD_MODE,
39 MX28_PAD_LCD_D02__LCD_D2 | LCD_MODE,
40 MX28_PAD_LCD_D03__LCD_D3 | LCD_MODE,
41 MX28_PAD_LCD_D04__LCD_D4 | LCD_MODE,
42 MX28_PAD_LCD_D05__LCD_D5 | LCD_MODE,
43 MX28_PAD_LCD_D06__LCD_D6 | LCD_MODE,
44 MX28_PAD_LCD_D07__LCD_D7 | LCD_MODE,
45 MX28_PAD_LCD_D08__LCD_D8 | LCD_MODE,
46 MX28_PAD_LCD_D09__LCD_D9 | LCD_MODE,
47 MX28_PAD_LCD_D10__LCD_D10 | LCD_MODE,
48 MX28_PAD_LCD_D11__LCD_D11 | LCD_MODE,
49 MX28_PAD_LCD_D12__LCD_D12 | LCD_MODE,
50 MX28_PAD_LCD_D13__LCD_D13 | LCD_MODE,
51 MX28_PAD_LCD_D14__LCD_D14 | LCD_MODE,
52 MX28_PAD_LCD_D15__LCD_D15 | LCD_MODE,
53 MX28_PAD_LCD_D16__LCD_D16 | LCD_MODE,
54 MX28_PAD_LCD_D17__LCD_D17 | LCD_MODE,
55 MX28_PAD_LCD_D18__LCD_D18 | LCD_MODE,
56 MX28_PAD_LCD_D19__LCD_D19 | LCD_MODE,
57 MX28_PAD_LCD_D20__LCD_D20 | LCD_MODE,
58 MX28_PAD_LCD_D21__LCD_D21 | LCD_MODE,
59 MX28_PAD_LCD_D22__LCD_D22 | LCD_MODE,
60 MX28_PAD_LCD_D23__LCD_D23 | LCD_MODE,
61 MX28_PAD_LCD_RD_E__LCD_VSYNC | LCD_MODE,
62 MX28_PAD_LCD_WR_RWN__LCD_HSYNC | LCD_MODE,
63 MX28_PAD_LCD_RS__LCD_DOTCLK | LCD_MODE,
64 MX28_PAD_LCD_CS__LCD_CS | LCD_MODE,
65 MX28_PAD_LCD_VSYNC__LCD_VSYNC | LCD_MODE,
66 MX28_PAD_LCD_HSYNC__LCD_HSYNC | LCD_MODE,
67 MX28_PAD_LCD_DOTCLK__LCD_DOTCLK | LCD_MODE,
68 MX28_PAD_LCD_ENABLE__GPIO_1_31 | LCD_MODE,
69 MX28_PAD_LCD_RESET__GPIO_3_30 | LCD_MODE,
70 MX28_PAD_PWM0__PWM_0 | LCD_MODE,
71
72 /* UART1 */
73 MX28_PAD_AUART0_CTS__DUART_RX,
74 MX28_PAD_AUART0_RTS__DUART_TX,
75 MX28_PAD_AUART0_TX__DUART_RTS,
76 MX28_PAD_AUART0_RX__DUART_CTS,
77
78 /* UART2 */
79 MX28_PAD_AUART1_RX__AUART1_RX,
80 MX28_PAD_AUART1_TX__AUART1_TX,
81 MX28_PAD_AUART1_RTS__AUART1_RTS,
82 MX28_PAD_AUART1_CTS__AUART1_CTS,
83
84 /* CAN */
85 MX28_PAD_GPMI_RDY2__CAN0_TX,
86 MX28_PAD_GPMI_RDY3__CAN0_RX,
87
88 /* I2C */
89 MX28_PAD_I2C0_SCL__I2C0_SCL,
90 MX28_PAD_I2C0_SDA__I2C0_SDA,
91
92 /* TSC2007 */
93 MX28_PAD_SAIF0_MCLK__GPIO_3_20 | MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP,
94
95 /* MMC0 */
96 MX28_PAD_SSP0_DATA0__SSP0_D0 |
97 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
98 MX28_PAD_SSP0_DATA1__SSP0_D1 |
99 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
100 MX28_PAD_SSP0_DATA2__SSP0_D2 |
101 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
102 MX28_PAD_SSP0_DATA3__SSP0_D3 |
103 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
104 MX28_PAD_SSP0_DATA4__SSP0_D4 |
105 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
106 MX28_PAD_SSP0_DATA5__SSP0_D5 |
107 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
108 MX28_PAD_SSP0_DATA6__SSP0_D6 |
109 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
110 MX28_PAD_SSP0_DATA7__SSP0_D7 |
111 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
112 MX28_PAD_SSP0_CMD__SSP0_CMD |
113 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
114 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT |
115 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
116 MX28_PAD_SSP0_SCK__SSP0_SCK |
117 (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
118};
119
120static struct gpio_led tx28_stk5v3_leds[] = {
121 {
122 .name = "GPIO-LED",
123 .default_trigger = "heartbeat",
124 .gpio = TX28_STK5_GPIO_LED,
125 },
126};
127
128static const struct gpio_led_platform_data tx28_stk5v3_led_data __initconst = {
129 .leds = tx28_stk5v3_leds,
130 .num_leds = ARRAY_SIZE(tx28_stk5v3_leds),
131};
132
133static struct spi_board_info tx28_spi_board_info[] = {
134 {
135 .modalias = "spidev",
136 .max_speed_hz = 20000000,
137 .bus_num = 0,
138 .chip_select = 1,
139 .controller_data = (void *)SPI_GPIO_NO_CHIPSELECT,
140 .mode = SPI_MODE_0,
141 },
142};
143
144static struct i2c_board_info tx28_stk5v3_i2c_boardinfo[] __initdata = {
145 {
146 I2C_BOARD_INFO("ds1339", 0x68),
147 },
148};
149
150static void __init tx28_stk5v3_init(void)
151{
152 mxs_iomux_setup_multiple_pads(tx28_stk5v3_pads,
153 ARRAY_SIZE(tx28_stk5v3_pads));
154
155 mx28_add_duart(); /* UART1 */
156 mx28_add_auart(1); /* UART2 */
157
158 tx28_add_fec0();
159 /* spi via ssp will be added when available */
160 spi_register_board_info(tx28_spi_board_info,
161 ARRAY_SIZE(tx28_spi_board_info));
162 mxs_add_platform_device("leds-gpio", 0, NULL, 0,
163 &tx28_stk5v3_led_data, sizeof(tx28_stk5v3_led_data));
164 mx28_add_mxs_i2c(0);
165 i2c_register_board_info(0, tx28_stk5v3_i2c_boardinfo,
166 ARRAY_SIZE(tx28_stk5v3_i2c_boardinfo));
167}
168
169static void __init tx28_timer_init(void)
170{
171 mx28_clocks_init();
172}
173
174static struct sys_timer tx28_timer = {
175 .init = tx28_timer_init,
176};
177
178MACHINE_START(TX28, "Ka-Ro electronics TX28 module")
179 .map_io = mx28_map_io,
180 .init_irq = mx28_init_irq,
181 .init_machine = tx28_stk5v3_init,
182 .timer = &tx28_timer,
183MACHINE_END
diff --git a/arch/arm/mach-mxs/module-tx28.c b/arch/arm/mach-mxs/module-tx28.c
new file mode 100644
index 000000000000..fa0b154da67b
--- /dev/null
+++ b/arch/arm/mach-mxs/module-tx28.c
@@ -0,0 +1,131 @@
1/*
2 * Copyright (C) 2010 <LW@KARO-electronics.de>
3 *
4 * This program is free software; you can redistribute it and/or modify it under
5 * the terms of the GNU General Public License version 2 as published by the
6 * Free Software Foundation.
7 */
8
9#include <linux/delay.h>
10#include <linux/fec.h>
11#include <linux/gpio.h>
12
13#include <mach/iomux-mx28.h>
14#include "../devices-mx28.h"
15
16#include "module-tx28.h"
17
18#define TX28_FEC_PHY_POWER MXS_GPIO_NR(3, 29)
19#define TX28_FEC_PHY_RESET MXS_GPIO_NR(4, 13)
20
21static const iomux_cfg_t tx28_fec_gpio_pads[] __initconst = {
22 /* PHY POWER */
23 MX28_PAD_PWM4__GPIO_3_29 |
24 MXS_PAD_4MA | MXS_PAD_NOPULL | MXS_PAD_3V3,
25 /* PHY RESET */
26 MX28_PAD_ENET0_RX_CLK__GPIO_4_13 |
27 MXS_PAD_4MA | MXS_PAD_NOPULL | MXS_PAD_3V3,
28 /* Mode strap pins 0-2 */
29 MX28_PAD_ENET0_RXD0__GPIO_4_3 |
30 MXS_PAD_8MA | MXS_PAD_PULLUP | MXS_PAD_3V3,
31 MX28_PAD_ENET0_RXD1__GPIO_4_4 |
32 MXS_PAD_8MA | MXS_PAD_PULLUP | MXS_PAD_3V3,
33 MX28_PAD_ENET0_RX_EN__GPIO_4_2 |
34 MXS_PAD_8MA | MXS_PAD_PULLUP | MXS_PAD_3V3,
35 /* nINT */
36 MX28_PAD_ENET0_TX_CLK__GPIO_4_5 |
37 MXS_PAD_4MA | MXS_PAD_NOPULL | MXS_PAD_3V3,
38
39 MX28_PAD_ENET0_MDC__GPIO_4_0,
40 MX28_PAD_ENET0_MDIO__GPIO_4_1,
41 MX28_PAD_ENET0_TX_EN__GPIO_4_6,
42 MX28_PAD_ENET0_TXD0__GPIO_4_7,
43 MX28_PAD_ENET0_TXD1__GPIO_4_8,
44 MX28_PAD_ENET_CLK__GPIO_4_16,
45};
46
47#define FEC_MODE (MXS_PAD_8MA | MXS_PAD_PULLUP | MXS_PAD_3V3)
48static const iomux_cfg_t tx28_fec_pads[] __initconst = {
49 MX28_PAD_ENET0_MDC__ENET0_MDC | FEC_MODE,
50 MX28_PAD_ENET0_MDIO__ENET0_MDIO | FEC_MODE,
51 MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | FEC_MODE,
52 MX28_PAD_ENET0_RXD0__ENET0_RXD0 | FEC_MODE,
53 MX28_PAD_ENET0_RXD1__ENET0_RXD1 | FEC_MODE,
54 MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | FEC_MODE,
55 MX28_PAD_ENET0_TXD0__ENET0_TXD0 | FEC_MODE,
56 MX28_PAD_ENET0_TXD1__ENET0_TXD1 | FEC_MODE,
57 MX28_PAD_ENET_CLK__CLKCTRL_ENET | FEC_MODE,
58};
59
60static const struct fec_platform_data tx28_fec_data __initconst = {
61 .phy = PHY_INTERFACE_MODE_RMII,
62};
63
64int __init tx28_add_fec0(void)
65{
66 int i, ret;
67
68 pr_debug("%s: Switching FEC PHY power off\n", __func__);
69 ret = mxs_iomux_setup_multiple_pads(tx28_fec_gpio_pads,
70 ARRAY_SIZE(tx28_fec_gpio_pads));
71 for (i = 0; i < ARRAY_SIZE(tx28_fec_gpio_pads); i++) {
72 unsigned int gpio = MXS_GPIO_NR(PAD_BANK(tx28_fec_gpio_pads[i]),
73 PAD_PIN(tx28_fec_gpio_pads[i]));
74
75 ret = gpio_request(gpio, "FEC");
76 if (ret) {
77 pr_err("Failed to request GPIO_%d_%d: %d\n",
78 PAD_BANK(tx28_fec_gpio_pads[i]),
79 PAD_PIN(tx28_fec_gpio_pads[i]), ret);
80 goto free_gpios;
81 }
82 ret = gpio_direction_output(gpio, 0);
83 if (ret) {
84 pr_err("Failed to set direction of GPIO_%d_%d to output: %d\n",
85 gpio / 32 + 1, gpio % 32, ret);
86 goto free_gpios;
87 }
88 }
89
90 /* Power up fec phy */
91 pr_debug("%s: Switching FEC PHY power on\n", __func__);
92 ret = gpio_direction_output(TX28_FEC_PHY_POWER, 1);
93 if (ret) {
94 pr_err("Failed to power on PHY: %d\n", ret);
95 goto free_gpios;
96 }
97 mdelay(26); /* 25ms according to data sheet */
98
99 /* nINT */
100 gpio_direction_input(MXS_GPIO_NR(4, 5));
101 /* Mode strap pins */
102 gpio_direction_output(MXS_GPIO_NR(4, 2), 1);
103 gpio_direction_output(MXS_GPIO_NR(4, 3), 1);
104 gpio_direction_output(MXS_GPIO_NR(4, 4), 1);
105
106 udelay(100); /* minimum assertion time for nRST */
107
108 pr_debug("%s: Deasserting FEC PHY RESET\n", __func__);
109 gpio_set_value(TX28_FEC_PHY_RESET, 1);
110
111 ret = mxs_iomux_setup_multiple_pads(tx28_fec_pads,
112 ARRAY_SIZE(tx28_fec_pads));
113 if (ret) {
114 pr_debug("%s: mxs_iomux_setup_multiple_pads() failed with rc: %d\n",
115 __func__, ret);
116 goto free_gpios;
117 }
118 pr_debug("%s: Registering FEC device\n", __func__);
119 mx28_add_fec(0, &tx28_fec_data);
120 return 0;
121
122free_gpios:
123 while (--i >= 0) {
124 unsigned int gpio = MXS_GPIO_NR(PAD_BANK(tx28_fec_gpio_pads[i]),
125 PAD_PIN(tx28_fec_gpio_pads[i]));
126
127 gpio_free(gpio);
128 }
129
130 return ret;
131}
diff --git a/arch/arm/mach-mxs/module-tx28.h b/arch/arm/mach-mxs/module-tx28.h
new file mode 100644
index 000000000000..df9e1b6e81bf
--- /dev/null
+++ b/arch/arm/mach-mxs/module-tx28.h
@@ -0,0 +1,9 @@
1/*
2 * Copyright (C) 2010 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9int __init tx28_add_fec0(void);
diff --git a/arch/arm/mach-mxs/ocotp.c b/arch/arm/mach-mxs/ocotp.c
new file mode 100644
index 000000000000..65157a35dbba
--- /dev/null
+++ b/arch/arm/mach-mxs/ocotp.c
@@ -0,0 +1,90 @@
1/*
2 * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <linux/delay.h>
16#include <linux/err.h>
17#include <linux/mutex.h>
18
19#include <mach/mxs.h>
20
21#define OCOTP_WORD_OFFSET 0x20
22#define OCOTP_WORD_COUNT 0x20
23
24#define BM_OCOTP_CTRL_BUSY (1 << 8)
25#define BM_OCOTP_CTRL_ERROR (1 << 9)
26#define BM_OCOTP_CTRL_RD_BANK_OPEN (1 << 12)
27
28static DEFINE_MUTEX(ocotp_mutex);
29static u32 ocotp_words[OCOTP_WORD_COUNT];
30
31const u32 *mxs_get_ocotp(void)
32{
33 void __iomem *ocotp_base = MXS_IO_ADDRESS(MXS_OCOTP_BASE_ADDR);
34 int timeout = 0x400;
35 size_t i;
36 static int once = 0;
37
38 if (once)
39 return ocotp_words;
40
41 mutex_lock(&ocotp_mutex);
42
43 /*
44 * clk_enable(hbus_clk) for ocotp can be skipped
45 * as it must be on when system is running.
46 */
47
48 /* try to clear ERROR bit */
49 __mxs_clrl(BM_OCOTP_CTRL_ERROR, ocotp_base);
50
51 /* check both BUSY and ERROR cleared */
52 while ((__raw_readl(ocotp_base) &
53 (BM_OCOTP_CTRL_BUSY | BM_OCOTP_CTRL_ERROR)) && --timeout)
54 cpu_relax();
55
56 if (unlikely(!timeout))
57 goto error_unlock;
58
59 /* open OCOTP banks for read */
60 __mxs_setl(BM_OCOTP_CTRL_RD_BANK_OPEN, ocotp_base);
61
62 /* approximately wait 32 hclk cycles */
63 udelay(1);
64
65 /* poll BUSY bit becoming cleared */
66 timeout = 0x400;
67 while ((__raw_readl(ocotp_base) & BM_OCOTP_CTRL_BUSY) && --timeout)
68 cpu_relax();
69
70 if (unlikely(!timeout))
71 goto error_unlock;
72
73 for (i = 0; i < OCOTP_WORD_COUNT; i++)
74 ocotp_words[i] = __raw_readl(ocotp_base + OCOTP_WORD_OFFSET +
75 i * 0x10);
76
77 /* close banks for power saving */
78 __mxs_clrl(BM_OCOTP_CTRL_RD_BANK_OPEN, ocotp_base);
79
80 once = 1;
81
82 mutex_unlock(&ocotp_mutex);
83
84 return ocotp_words;
85
86error_unlock:
87 mutex_unlock(&ocotp_mutex);
88 pr_err("%s: timeout in reading OCOTP\n", __func__);
89 return NULL;
90}
diff --git a/arch/arm/mach-mxs/pm.c b/arch/arm/mach-mxs/pm.c
new file mode 100644
index 000000000000..fb042da29bda
--- /dev/null
+++ b/arch/arm/mach-mxs/pm.c
@@ -0,0 +1,43 @@
1/*
2 * Copyright (C) 2010 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <linux/kernel.h>
16#include <linux/suspend.h>
17#include <linux/io.h>
18#include <mach/system.h>
19
20static int mxs_suspend_enter(suspend_state_t state)
21{
22 switch (state) {
23 case PM_SUSPEND_MEM:
24 arch_idle();
25 break;
26
27 default:
28 return -EINVAL;
29 }
30 return 0;
31}
32
33static struct platform_suspend_ops mxs_suspend_ops = {
34 .enter = mxs_suspend_enter,
35 .valid = suspend_valid_only_mem,
36};
37
38static int __init mxs_pm_init(void)
39{
40 suspend_set_ops(&mxs_suspend_ops);
41 return 0;
42}
43device_initcall(mxs_pm_init);
diff --git a/arch/arm/mach-mxs/regs-clkctrl-mx23.h b/arch/arm/mach-mxs/regs-clkctrl-mx23.h
index dbc04747b691..0ea5c9d0e2b2 100644
--- a/arch/arm/mach-mxs/regs-clkctrl-mx23.h
+++ b/arch/arm/mach-mxs/regs-clkctrl-mx23.h
@@ -33,10 +33,6 @@
33#define HW_CLKCTRL_PLLCTRL0_CLR (0x00000008) 33#define HW_CLKCTRL_PLLCTRL0_CLR (0x00000008)
34#define HW_CLKCTRL_PLLCTRL0_TOG (0x0000000c) 34#define HW_CLKCTRL_PLLCTRL0_TOG (0x0000000c)
35 35
36#define BP_CLKCTRL_PLLCTRL0_RSRVD6 30
37#define BM_CLKCTRL_PLLCTRL0_RSRVD6 0xC0000000
38#define BF_CLKCTRL_PLLCTRL0_RSRVD6(v) \
39 (((v) << 30) & BM_CLKCTRL_PLLCTRL0_RSRVD6)
40#define BP_CLKCTRL_PLLCTRL0_LFR_SEL 28 36#define BP_CLKCTRL_PLLCTRL0_LFR_SEL 28
41#define BM_CLKCTRL_PLLCTRL0_LFR_SEL 0x30000000 37#define BM_CLKCTRL_PLLCTRL0_LFR_SEL 0x30000000
42#define BF_CLKCTRL_PLLCTRL0_LFR_SEL(v) \ 38#define BF_CLKCTRL_PLLCTRL0_LFR_SEL(v) \
@@ -45,10 +41,6 @@
45#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_2 0x1 41#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_2 0x1
46#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_05 0x2 42#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_05 0x2
47#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__UNDEFINED 0x3 43#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__UNDEFINED 0x3
48#define BP_CLKCTRL_PLLCTRL0_RSRVD5 26
49#define BM_CLKCTRL_PLLCTRL0_RSRVD5 0x0C000000
50#define BF_CLKCTRL_PLLCTRL0_RSRVD5(v) \
51 (((v) << 26) & BM_CLKCTRL_PLLCTRL0_RSRVD5)
52#define BP_CLKCTRL_PLLCTRL0_CP_SEL 24 44#define BP_CLKCTRL_PLLCTRL0_CP_SEL 24
53#define BM_CLKCTRL_PLLCTRL0_CP_SEL 0x03000000 45#define BM_CLKCTRL_PLLCTRL0_CP_SEL 0x03000000
54#define BF_CLKCTRL_PLLCTRL0_CP_SEL(v) \ 46#define BF_CLKCTRL_PLLCTRL0_CP_SEL(v) \
@@ -57,10 +49,6 @@
57#define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_2 0x1 49#define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_2 0x1
58#define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_05 0x2 50#define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_05 0x2
59#define BV_CLKCTRL_PLLCTRL0_CP_SEL__UNDEFINED 0x3 51#define BV_CLKCTRL_PLLCTRL0_CP_SEL__UNDEFINED 0x3
60#define BP_CLKCTRL_PLLCTRL0_RSRVD4 22
61#define BM_CLKCTRL_PLLCTRL0_RSRVD4 0x00C00000
62#define BF_CLKCTRL_PLLCTRL0_RSRVD4(v) \
63 (((v) << 22) & BM_CLKCTRL_PLLCTRL0_RSRVD4)
64#define BP_CLKCTRL_PLLCTRL0_DIV_SEL 20 52#define BP_CLKCTRL_PLLCTRL0_DIV_SEL 20
65#define BM_CLKCTRL_PLLCTRL0_DIV_SEL 0x00300000 53#define BM_CLKCTRL_PLLCTRL0_DIV_SEL 0x00300000
66#define BF_CLKCTRL_PLLCTRL0_DIV_SEL(v) \ 54#define BF_CLKCTRL_PLLCTRL0_DIV_SEL(v) \
@@ -69,23 +57,13 @@
69#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWER 0x1 57#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWER 0x1
70#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWEST 0x2 58#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWEST 0x2
71#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__UNDEFINED 0x3 59#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__UNDEFINED 0x3
72#define BM_CLKCTRL_PLLCTRL0_RSRVD3 0x00080000
73#define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS 0x00040000 60#define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS 0x00040000
74#define BM_CLKCTRL_PLLCTRL0_RSRVD2 0x00020000
75#define BM_CLKCTRL_PLLCTRL0_POWER 0x00010000 61#define BM_CLKCTRL_PLLCTRL0_POWER 0x00010000
76#define BP_CLKCTRL_PLLCTRL0_RSRVD1 0
77#define BM_CLKCTRL_PLLCTRL0_RSRVD1 0x0000FFFF
78#define BF_CLKCTRL_PLLCTRL0_RSRVD1(v) \
79 (((v) << 0) & BM_CLKCTRL_PLLCTRL0_RSRVD1)
80 62
81#define HW_CLKCTRL_PLLCTRL1 (0x00000010) 63#define HW_CLKCTRL_PLLCTRL1 (0x00000010)
82 64
83#define BM_CLKCTRL_PLLCTRL1_LOCK 0x80000000 65#define BM_CLKCTRL_PLLCTRL1_LOCK 0x80000000
84#define BM_CLKCTRL_PLLCTRL1_FORCE_LOCK 0x40000000 66#define BM_CLKCTRL_PLLCTRL1_FORCE_LOCK 0x40000000
85#define BP_CLKCTRL_PLLCTRL1_RSRVD1 16
86#define BM_CLKCTRL_PLLCTRL1_RSRVD1 0x3FFF0000
87#define BF_CLKCTRL_PLLCTRL1_RSRVD1(v) \
88 (((v) << 16) & BM_CLKCTRL_PLLCTRL1_RSRVD1)
89#define BP_CLKCTRL_PLLCTRL1_LOCK_COUNT 0 67#define BP_CLKCTRL_PLLCTRL1_LOCK_COUNT 0
90#define BM_CLKCTRL_PLLCTRL1_LOCK_COUNT 0x0000FFFF 68#define BM_CLKCTRL_PLLCTRL1_LOCK_COUNT 0x0000FFFF
91#define BF_CLKCTRL_PLLCTRL1_LOCK_COUNT(v) \ 69#define BF_CLKCTRL_PLLCTRL1_LOCK_COUNT(v) \
@@ -96,29 +74,15 @@
96#define HW_CLKCTRL_CPU_CLR (0x00000028) 74#define HW_CLKCTRL_CPU_CLR (0x00000028)
97#define HW_CLKCTRL_CPU_TOG (0x0000002c) 75#define HW_CLKCTRL_CPU_TOG (0x0000002c)
98 76
99#define BP_CLKCTRL_CPU_RSRVD5 30
100#define BM_CLKCTRL_CPU_RSRVD5 0xC0000000
101#define BF_CLKCTRL_CPU_RSRVD5(v) \
102 (((v) << 30) & BM_CLKCTRL_CPU_RSRVD5)
103#define BM_CLKCTRL_CPU_BUSY_REF_XTAL 0x20000000 77#define BM_CLKCTRL_CPU_BUSY_REF_XTAL 0x20000000
104#define BM_CLKCTRL_CPU_BUSY_REF_CPU 0x10000000 78#define BM_CLKCTRL_CPU_BUSY_REF_CPU 0x10000000
105#define BM_CLKCTRL_CPU_RSRVD4 0x08000000
106#define BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN 0x04000000 79#define BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN 0x04000000
107#define BP_CLKCTRL_CPU_DIV_XTAL 16 80#define BP_CLKCTRL_CPU_DIV_XTAL 16
108#define BM_CLKCTRL_CPU_DIV_XTAL 0x03FF0000 81#define BM_CLKCTRL_CPU_DIV_XTAL 0x03FF0000
109#define BF_CLKCTRL_CPU_DIV_XTAL(v) \ 82#define BF_CLKCTRL_CPU_DIV_XTAL(v) \
110 (((v) << 16) & BM_CLKCTRL_CPU_DIV_XTAL) 83 (((v) << 16) & BM_CLKCTRL_CPU_DIV_XTAL)
111#define BP_CLKCTRL_CPU_RSRVD3 13
112#define BM_CLKCTRL_CPU_RSRVD3 0x0000E000
113#define BF_CLKCTRL_CPU_RSRVD3(v) \
114 (((v) << 13) & BM_CLKCTRL_CPU_RSRVD3)
115#define BM_CLKCTRL_CPU_INTERRUPT_WAIT 0x00001000 84#define BM_CLKCTRL_CPU_INTERRUPT_WAIT 0x00001000
116#define BM_CLKCTRL_CPU_RSRVD2 0x00000800
117#define BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN 0x00000400 85#define BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN 0x00000400
118#define BP_CLKCTRL_CPU_RSRVD1 6
119#define BM_CLKCTRL_CPU_RSRVD1 0x000003C0
120#define BF_CLKCTRL_CPU_RSRVD1(v) \
121 (((v) << 6) & BM_CLKCTRL_CPU_RSRVD1)
122#define BP_CLKCTRL_CPU_DIV_CPU 0 86#define BP_CLKCTRL_CPU_DIV_CPU 0
123#define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F 87#define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F
124#define BF_CLKCTRL_CPU_DIV_CPU(v) \ 88#define BF_CLKCTRL_CPU_DIV_CPU(v) \
@@ -129,10 +93,6 @@
129#define HW_CLKCTRL_HBUS_CLR (0x00000038) 93#define HW_CLKCTRL_HBUS_CLR (0x00000038)
130#define HW_CLKCTRL_HBUS_TOG (0x0000003c) 94#define HW_CLKCTRL_HBUS_TOG (0x0000003c)
131 95
132#define BP_CLKCTRL_HBUS_RSRVD4 30
133#define BM_CLKCTRL_HBUS_RSRVD4 0xC0000000
134#define BF_CLKCTRL_HBUS_RSRVD4(v) \
135 (((v) << 30) & BM_CLKCTRL_HBUS_RSRVD4)
136#define BM_CLKCTRL_HBUS_BUSY 0x20000000 96#define BM_CLKCTRL_HBUS_BUSY 0x20000000
137#define BM_CLKCTRL_HBUS_DCP_AS_ENABLE 0x10000000 97#define BM_CLKCTRL_HBUS_DCP_AS_ENABLE 0x10000000
138#define BM_CLKCTRL_HBUS_PXP_AS_ENABLE 0x08000000 98#define BM_CLKCTRL_HBUS_PXP_AS_ENABLE 0x08000000
@@ -143,7 +103,6 @@
143#define BM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE 0x00400000 103#define BM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE 0x00400000
144#define BM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE 0x00200000 104#define BM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE 0x00200000
145#define BM_CLKCTRL_HBUS_AUTO_SLOW_MODE 0x00100000 105#define BM_CLKCTRL_HBUS_AUTO_SLOW_MODE 0x00100000
146#define BM_CLKCTRL_HBUS_RSRVD2 0x00080000
147#define BP_CLKCTRL_HBUS_SLOW_DIV 16 106#define BP_CLKCTRL_HBUS_SLOW_DIV 16
148#define BM_CLKCTRL_HBUS_SLOW_DIV 0x00070000 107#define BM_CLKCTRL_HBUS_SLOW_DIV 0x00070000
149#define BF_CLKCTRL_HBUS_SLOW_DIV(v) \ 108#define BF_CLKCTRL_HBUS_SLOW_DIV(v) \
@@ -154,10 +113,6 @@
154#define BV_CLKCTRL_HBUS_SLOW_DIV__BY8 0x3 113#define BV_CLKCTRL_HBUS_SLOW_DIV__BY8 0x3
155#define BV_CLKCTRL_HBUS_SLOW_DIV__BY16 0x4 114#define BV_CLKCTRL_HBUS_SLOW_DIV__BY16 0x4
156#define BV_CLKCTRL_HBUS_SLOW_DIV__BY32 0x5 115#define BV_CLKCTRL_HBUS_SLOW_DIV__BY32 0x5
157#define BP_CLKCTRL_HBUS_RSRVD1 6
158#define BM_CLKCTRL_HBUS_RSRVD1 0x0000FFC0
159#define BF_CLKCTRL_HBUS_RSRVD1(v) \
160 (((v) << 6) & BM_CLKCTRL_HBUS_RSRVD1)
161#define BM_CLKCTRL_HBUS_DIV_FRAC_EN 0x00000020 116#define BM_CLKCTRL_HBUS_DIV_FRAC_EN 0x00000020
162#define BP_CLKCTRL_HBUS_DIV 0 117#define BP_CLKCTRL_HBUS_DIV 0
163#define BM_CLKCTRL_HBUS_DIV 0x0000001F 118#define BM_CLKCTRL_HBUS_DIV 0x0000001F
@@ -167,10 +122,6 @@
167#define HW_CLKCTRL_XBUS (0x00000040) 122#define HW_CLKCTRL_XBUS (0x00000040)
168 123
169#define BM_CLKCTRL_XBUS_BUSY 0x80000000 124#define BM_CLKCTRL_XBUS_BUSY 0x80000000
170#define BP_CLKCTRL_XBUS_RSRVD1 11
171#define BM_CLKCTRL_XBUS_RSRVD1 0x7FFFF800
172#define BF_CLKCTRL_XBUS_RSRVD1(v) \
173 (((v) << 11) & BM_CLKCTRL_XBUS_RSRVD1)
174#define BM_CLKCTRL_XBUS_DIV_FRAC_EN 0x00000400 125#define BM_CLKCTRL_XBUS_DIV_FRAC_EN 0x00000400
175#define BP_CLKCTRL_XBUS_DIV 0 126#define BP_CLKCTRL_XBUS_DIV 0
176#define BM_CLKCTRL_XBUS_DIV 0x000003FF 127#define BM_CLKCTRL_XBUS_DIV 0x000003FF
@@ -192,10 +143,6 @@
192#define BM_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE 0x08000000 143#define BM_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE 0x08000000
193#define BP_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 26 144#define BP_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 26
194#define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 0x04000000 145#define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 0x04000000
195#define BP_CLKCTRL_XTAL_RSRVD1 2
196#define BM_CLKCTRL_XTAL_RSRVD1 0x03FFFFFC
197#define BF_CLKCTRL_XTAL_RSRVD1(v) \
198 (((v) << 2) & BM_CLKCTRL_XTAL_RSRVD1)
199#define BP_CLKCTRL_XTAL_DIV_UART 0 146#define BP_CLKCTRL_XTAL_DIV_UART 0
200#define BM_CLKCTRL_XTAL_DIV_UART 0x00000003 147#define BM_CLKCTRL_XTAL_DIV_UART 0x00000003
201#define BF_CLKCTRL_XTAL_DIV_UART(v) \ 148#define BF_CLKCTRL_XTAL_DIV_UART(v) \
@@ -205,12 +152,7 @@
205 152
206#define BP_CLKCTRL_PIX_CLKGATE 31 153#define BP_CLKCTRL_PIX_CLKGATE 31
207#define BM_CLKCTRL_PIX_CLKGATE 0x80000000 154#define BM_CLKCTRL_PIX_CLKGATE 0x80000000
208#define BM_CLKCTRL_PIX_RSRVD2 0x40000000
209#define BM_CLKCTRL_PIX_BUSY 0x20000000 155#define BM_CLKCTRL_PIX_BUSY 0x20000000
210#define BP_CLKCTRL_PIX_RSRVD1 13
211#define BM_CLKCTRL_PIX_RSRVD1 0x1FFFE000
212#define BF_CLKCTRL_PIX_RSRVD1(v) \
213 (((v) << 13) & BM_CLKCTRL_PIX_RSRVD1)
214#define BM_CLKCTRL_PIX_DIV_FRAC_EN 0x00001000 156#define BM_CLKCTRL_PIX_DIV_FRAC_EN 0x00001000
215#define BP_CLKCTRL_PIX_DIV 0 157#define BP_CLKCTRL_PIX_DIV 0
216#define BM_CLKCTRL_PIX_DIV 0x00000FFF 158#define BM_CLKCTRL_PIX_DIV 0x00000FFF
@@ -221,12 +163,7 @@
221 163
222#define BP_CLKCTRL_SSP_CLKGATE 31 164#define BP_CLKCTRL_SSP_CLKGATE 31
223#define BM_CLKCTRL_SSP_CLKGATE 0x80000000 165#define BM_CLKCTRL_SSP_CLKGATE 0x80000000
224#define BM_CLKCTRL_SSP_RSRVD2 0x40000000
225#define BM_CLKCTRL_SSP_BUSY 0x20000000 166#define BM_CLKCTRL_SSP_BUSY 0x20000000
226#define BP_CLKCTRL_SSP_RSRVD1 10
227#define BM_CLKCTRL_SSP_RSRVD1 0x1FFFFC00
228#define BF_CLKCTRL_SSP_RSRVD1(v) \
229 (((v) << 10) & BM_CLKCTRL_SSP_RSRVD1)
230#define BM_CLKCTRL_SSP_DIV_FRAC_EN 0x00000200 167#define BM_CLKCTRL_SSP_DIV_FRAC_EN 0x00000200
231#define BP_CLKCTRL_SSP_DIV 0 168#define BP_CLKCTRL_SSP_DIV 0
232#define BM_CLKCTRL_SSP_DIV 0x000001FF 169#define BM_CLKCTRL_SSP_DIV 0x000001FF
@@ -237,12 +174,7 @@
237 174
238#define BP_CLKCTRL_GPMI_CLKGATE 31 175#define BP_CLKCTRL_GPMI_CLKGATE 31
239#define BM_CLKCTRL_GPMI_CLKGATE 0x80000000 176#define BM_CLKCTRL_GPMI_CLKGATE 0x80000000
240#define BM_CLKCTRL_GPMI_RSRVD2 0x40000000
241#define BM_CLKCTRL_GPMI_BUSY 0x20000000 177#define BM_CLKCTRL_GPMI_BUSY 0x20000000
242#define BP_CLKCTRL_GPMI_RSRVD1 11
243#define BM_CLKCTRL_GPMI_RSRVD1 0x1FFFF800
244#define BF_CLKCTRL_GPMI_RSRVD1(v) \
245 (((v) << 11) & BM_CLKCTRL_GPMI_RSRVD1)
246#define BM_CLKCTRL_GPMI_DIV_FRAC_EN 0x00000400 178#define BM_CLKCTRL_GPMI_DIV_FRAC_EN 0x00000400
247#define BP_CLKCTRL_GPMI_DIV 0 179#define BP_CLKCTRL_GPMI_DIV 0
248#define BM_CLKCTRL_GPMI_DIV 0x000003FF 180#define BM_CLKCTRL_GPMI_DIV 0x000003FF
@@ -252,10 +184,6 @@
252#define HW_CLKCTRL_SPDIF (0x00000090) 184#define HW_CLKCTRL_SPDIF (0x00000090)
253 185
254#define BM_CLKCTRL_SPDIF_CLKGATE 0x80000000 186#define BM_CLKCTRL_SPDIF_CLKGATE 0x80000000
255#define BP_CLKCTRL_SPDIF_RSRVD 0
256#define BM_CLKCTRL_SPDIF_RSRVD 0x7FFFFFFF
257#define BF_CLKCTRL_SPDIF_RSRVD(v) \
258 (((v) << 0) & BM_CLKCTRL_SPDIF_RSRVD)
259 187
260#define HW_CLKCTRL_EMI (0x000000a0) 188#define HW_CLKCTRL_EMI (0x000000a0)
261 189
@@ -266,24 +194,12 @@
266#define BM_CLKCTRL_EMI_BUSY_REF_EMI 0x10000000 194#define BM_CLKCTRL_EMI_BUSY_REF_EMI 0x10000000
267#define BM_CLKCTRL_EMI_BUSY_REF_CPU 0x08000000 195#define BM_CLKCTRL_EMI_BUSY_REF_CPU 0x08000000
268#define BM_CLKCTRL_EMI_BUSY_SYNC_MODE 0x04000000 196#define BM_CLKCTRL_EMI_BUSY_SYNC_MODE 0x04000000
269#define BP_CLKCTRL_EMI_RSRVD3 18
270#define BM_CLKCTRL_EMI_RSRVD3 0x03FC0000
271#define BF_CLKCTRL_EMI_RSRVD3(v) \
272 (((v) << 18) & BM_CLKCTRL_EMI_RSRVD3)
273#define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC 0x00020000 197#define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC 0x00020000
274#define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE 0x00010000 198#define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE 0x00010000
275#define BP_CLKCTRL_EMI_RSRVD2 12
276#define BM_CLKCTRL_EMI_RSRVD2 0x0000F000
277#define BF_CLKCTRL_EMI_RSRVD2(v) \
278 (((v) << 12) & BM_CLKCTRL_EMI_RSRVD2)
279#define BP_CLKCTRL_EMI_DIV_XTAL 8 199#define BP_CLKCTRL_EMI_DIV_XTAL 8
280#define BM_CLKCTRL_EMI_DIV_XTAL 0x00000F00 200#define BM_CLKCTRL_EMI_DIV_XTAL 0x00000F00
281#define BF_CLKCTRL_EMI_DIV_XTAL(v) \ 201#define BF_CLKCTRL_EMI_DIV_XTAL(v) \
282 (((v) << 8) & BM_CLKCTRL_EMI_DIV_XTAL) 202 (((v) << 8) & BM_CLKCTRL_EMI_DIV_XTAL)
283#define BP_CLKCTRL_EMI_RSRVD1 6
284#define BM_CLKCTRL_EMI_RSRVD1 0x000000C0
285#define BF_CLKCTRL_EMI_RSRVD1(v) \
286 (((v) << 6) & BM_CLKCTRL_EMI_RSRVD1)
287#define BP_CLKCTRL_EMI_DIV_EMI 0 203#define BP_CLKCTRL_EMI_DIV_EMI 0
288#define BM_CLKCTRL_EMI_DIV_EMI 0x0000003F 204#define BM_CLKCTRL_EMI_DIV_EMI 0x0000003F
289#define BF_CLKCTRL_EMI_DIV_EMI(v) \ 205#define BF_CLKCTRL_EMI_DIV_EMI(v) \
@@ -292,22 +208,13 @@
292#define HW_CLKCTRL_IR (0x000000b0) 208#define HW_CLKCTRL_IR (0x000000b0)
293 209
294#define BM_CLKCTRL_IR_CLKGATE 0x80000000 210#define BM_CLKCTRL_IR_CLKGATE 0x80000000
295#define BM_CLKCTRL_IR_RSRVD3 0x40000000
296#define BM_CLKCTRL_IR_AUTO_DIV 0x20000000 211#define BM_CLKCTRL_IR_AUTO_DIV 0x20000000
297#define BM_CLKCTRL_IR_IR_BUSY 0x10000000 212#define BM_CLKCTRL_IR_IR_BUSY 0x10000000
298#define BM_CLKCTRL_IR_IROV_BUSY 0x08000000 213#define BM_CLKCTRL_IR_IROV_BUSY 0x08000000
299#define BP_CLKCTRL_IR_RSRVD2 25
300#define BM_CLKCTRL_IR_RSRVD2 0x06000000
301#define BF_CLKCTRL_IR_RSRVD2(v) \
302 (((v) << 25) & BM_CLKCTRL_IR_RSRVD2)
303#define BP_CLKCTRL_IR_IROV_DIV 16 214#define BP_CLKCTRL_IR_IROV_DIV 16
304#define BM_CLKCTRL_IR_IROV_DIV 0x01FF0000 215#define BM_CLKCTRL_IR_IROV_DIV 0x01FF0000
305#define BF_CLKCTRL_IR_IROV_DIV(v) \ 216#define BF_CLKCTRL_IR_IROV_DIV(v) \
306 (((v) << 16) & BM_CLKCTRL_IR_IROV_DIV) 217 (((v) << 16) & BM_CLKCTRL_IR_IROV_DIV)
307#define BP_CLKCTRL_IR_RSRVD1 10
308#define BM_CLKCTRL_IR_RSRVD1 0x0000FC00
309#define BF_CLKCTRL_IR_RSRVD1(v) \
310 (((v) << 10) & BM_CLKCTRL_IR_RSRVD1)
311#define BP_CLKCTRL_IR_IR_DIV 0 218#define BP_CLKCTRL_IR_IR_DIV 0
312#define BM_CLKCTRL_IR_IR_DIV 0x000003FF 219#define BM_CLKCTRL_IR_IR_DIV 0x000003FF
313#define BF_CLKCTRL_IR_IR_DIV(v) \ 220#define BF_CLKCTRL_IR_IR_DIV(v) \
@@ -316,12 +223,7 @@
316#define HW_CLKCTRL_SAIF (0x000000c0) 223#define HW_CLKCTRL_SAIF (0x000000c0)
317 224
318#define BM_CLKCTRL_SAIF_CLKGATE 0x80000000 225#define BM_CLKCTRL_SAIF_CLKGATE 0x80000000
319#define BM_CLKCTRL_SAIF_RSRVD2 0x40000000
320#define BM_CLKCTRL_SAIF_BUSY 0x20000000 226#define BM_CLKCTRL_SAIF_BUSY 0x20000000
321#define BP_CLKCTRL_SAIF_RSRVD1 17
322#define BM_CLKCTRL_SAIF_RSRVD1 0x1FFE0000
323#define BF_CLKCTRL_SAIF_RSRVD1(v) \
324 (((v) << 17) & BM_CLKCTRL_SAIF_RSRVD1)
325#define BM_CLKCTRL_SAIF_DIV_FRAC_EN 0x00010000 227#define BM_CLKCTRL_SAIF_DIV_FRAC_EN 0x00010000
326#define BP_CLKCTRL_SAIF_DIV 0 228#define BP_CLKCTRL_SAIF_DIV 0
327#define BM_CLKCTRL_SAIF_DIV 0x0000FFFF 229#define BM_CLKCTRL_SAIF_DIV 0x0000FFFF
@@ -332,20 +234,11 @@
332 234
333#define BM_CLKCTRL_TV_CLK_TV108M_GATE 0x80000000 235#define BM_CLKCTRL_TV_CLK_TV108M_GATE 0x80000000
334#define BM_CLKCTRL_TV_CLK_TV_GATE 0x40000000 236#define BM_CLKCTRL_TV_CLK_TV_GATE 0x40000000
335#define BP_CLKCTRL_TV_RSRVD 0
336#define BM_CLKCTRL_TV_RSRVD 0x3FFFFFFF
337#define BF_CLKCTRL_TV_RSRVD(v) \
338 (((v) << 0) & BM_CLKCTRL_TV_RSRVD)
339 237
340#define HW_CLKCTRL_ETM (0x000000e0) 238#define HW_CLKCTRL_ETM (0x000000e0)
341 239
342#define BM_CLKCTRL_ETM_CLKGATE 0x80000000 240#define BM_CLKCTRL_ETM_CLKGATE 0x80000000
343#define BM_CLKCTRL_ETM_RSRVD2 0x40000000
344#define BM_CLKCTRL_ETM_BUSY 0x20000000 241#define BM_CLKCTRL_ETM_BUSY 0x20000000
345#define BP_CLKCTRL_ETM_RSRVD1 7
346#define BM_CLKCTRL_ETM_RSRVD1 0x1FFFFF80
347#define BF_CLKCTRL_ETM_RSRVD1(v) \
348 (((v) << 7) & BM_CLKCTRL_ETM_RSRVD1)
349#define BM_CLKCTRL_ETM_DIV_FRAC_EN 0x00000040 242#define BM_CLKCTRL_ETM_DIV_FRAC_EN 0x00000040
350#define BP_CLKCTRL_ETM_DIV 0 243#define BP_CLKCTRL_ETM_DIV 0
351#define BM_CLKCTRL_ETM_DIV 0x0000003F 244#define BM_CLKCTRL_ETM_DIV 0x0000003F
@@ -393,36 +286,23 @@
393 286
394#define BM_CLKCTRL_FRAC1_CLKGATEVID 0x80000000 287#define BM_CLKCTRL_FRAC1_CLKGATEVID 0x80000000
395#define BM_CLKCTRL_FRAC1_VID_STABLE 0x40000000 288#define BM_CLKCTRL_FRAC1_VID_STABLE 0x40000000
396#define BP_CLKCTRL_FRAC1_RSRVD1 0
397#define BM_CLKCTRL_FRAC1_RSRVD1 0x3FFFFFFF
398#define BF_CLKCTRL_FRAC1_RSRVD1(v) \
399 (((v) << 0) & BM_CLKCTRL_FRAC1_RSRVD1)
400 289
401#define HW_CLKCTRL_CLKSEQ (0x00000110) 290#define HW_CLKCTRL_CLKSEQ (0x00000110)
402#define HW_CLKCTRL_CLKSEQ_SET (0x00000114) 291#define HW_CLKCTRL_CLKSEQ_SET (0x00000114)
403#define HW_CLKCTRL_CLKSEQ_CLR (0x00000118) 292#define HW_CLKCTRL_CLKSEQ_CLR (0x00000118)
404#define HW_CLKCTRL_CLKSEQ_TOG (0x0000011c) 293#define HW_CLKCTRL_CLKSEQ_TOG (0x0000011c)
405 294
406#define BP_CLKCTRL_CLKSEQ_RSRVD1 9
407#define BM_CLKCTRL_CLKSEQ_RSRVD1 0xFFFFFE00
408#define BF_CLKCTRL_CLKSEQ_RSRVD1(v) \
409 (((v) << 9) & BM_CLKCTRL_CLKSEQ_RSRVD1)
410#define BM_CLKCTRL_CLKSEQ_BYPASS_ETM 0x00000100 295#define BM_CLKCTRL_CLKSEQ_BYPASS_ETM 0x00000100
411#define BM_CLKCTRL_CLKSEQ_BYPASS_CPU 0x00000080 296#define BM_CLKCTRL_CLKSEQ_BYPASS_CPU 0x00000080
412#define BM_CLKCTRL_CLKSEQ_BYPASS_EMI 0x00000040 297#define BM_CLKCTRL_CLKSEQ_BYPASS_EMI 0x00000040
413#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP 0x00000020 298#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP 0x00000020
414#define BM_CLKCTRL_CLKSEQ_BYPASS_GPMI 0x00000010 299#define BM_CLKCTRL_CLKSEQ_BYPASS_GPMI 0x00000010
415#define BM_CLKCTRL_CLKSEQ_BYPASS_IR 0x00000008 300#define BM_CLKCTRL_CLKSEQ_BYPASS_IR 0x00000008
416#define BM_CLKCTRL_CLKSEQ_RSRVD0 0x00000004
417#define BM_CLKCTRL_CLKSEQ_BYPASS_PIX 0x00000002 301#define BM_CLKCTRL_CLKSEQ_BYPASS_PIX 0x00000002
418#define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF 0x00000001 302#define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF 0x00000001
419 303
420#define HW_CLKCTRL_RESET (0x00000120) 304#define HW_CLKCTRL_RESET (0x00000120)
421 305
422#define BP_CLKCTRL_RESET_RSRVD 2
423#define BM_CLKCTRL_RESET_RSRVD 0xFFFFFFFC
424#define BF_CLKCTRL_RESET_RSRVD(v) \
425 (((v) << 2) & BM_CLKCTRL_RESET_RSRVD)
426#define BM_CLKCTRL_RESET_CHIP 0x00000002 306#define BM_CLKCTRL_RESET_CHIP 0x00000002
427#define BM_CLKCTRL_RESET_DIG 0x00000001 307#define BM_CLKCTRL_RESET_DIG 0x00000001
428 308
@@ -432,10 +312,6 @@
432#define BM_CLKCTRL_STATUS_CPU_LIMIT 0xC0000000 312#define BM_CLKCTRL_STATUS_CPU_LIMIT 0xC0000000
433#define BF_CLKCTRL_STATUS_CPU_LIMIT(v) \ 313#define BF_CLKCTRL_STATUS_CPU_LIMIT(v) \
434 (((v) << 30) & BM_CLKCTRL_STATUS_CPU_LIMIT) 314 (((v) << 30) & BM_CLKCTRL_STATUS_CPU_LIMIT)
435#define BP_CLKCTRL_STATUS_RSRVD 0
436#define BM_CLKCTRL_STATUS_RSRVD 0x3FFFFFFF
437#define BF_CLKCTRL_STATUS_RSRVD(v) \
438 (((v) << 0) & BM_CLKCTRL_STATUS_RSRVD)
439 315
440#define HW_CLKCTRL_VERSION (0x00000140) 316#define HW_CLKCTRL_VERSION (0x00000140)
441 317
diff --git a/arch/arm/mach-mxs/regs-clkctrl-mx28.h b/arch/arm/mach-mxs/regs-clkctrl-mx28.h
index 661df18755f7..7d1b061d7943 100644
--- a/arch/arm/mach-mxs/regs-clkctrl-mx28.h
+++ b/arch/arm/mach-mxs/regs-clkctrl-mx28.h
@@ -31,10 +31,6 @@
31#define HW_CLKCTRL_PLL0CTRL0_CLR (0x00000008) 31#define HW_CLKCTRL_PLL0CTRL0_CLR (0x00000008)
32#define HW_CLKCTRL_PLL0CTRL0_TOG (0x0000000c) 32#define HW_CLKCTRL_PLL0CTRL0_TOG (0x0000000c)
33 33
34#define BP_CLKCTRL_PLL0CTRL0_RSRVD6 30
35#define BM_CLKCTRL_PLL0CTRL0_RSRVD6 0xC0000000
36#define BF_CLKCTRL_PLL0CTRL0_RSRVD6(v) \
37 (((v) << 30) & BM_CLKCTRL_PLL0CTRL0_RSRVD6)
38#define BP_CLKCTRL_PLL0CTRL0_LFR_SEL 28 34#define BP_CLKCTRL_PLL0CTRL0_LFR_SEL 28
39#define BM_CLKCTRL_PLL0CTRL0_LFR_SEL 0x30000000 35#define BM_CLKCTRL_PLL0CTRL0_LFR_SEL 0x30000000
40#define BF_CLKCTRL_PLL0CTRL0_LFR_SEL(v) \ 36#define BF_CLKCTRL_PLL0CTRL0_LFR_SEL(v) \
@@ -43,10 +39,6 @@
43#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__TIMES_2 0x1 39#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__TIMES_2 0x1
44#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__TIMES_05 0x2 40#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__TIMES_05 0x2
45#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__UNDEFINED 0x3 41#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__UNDEFINED 0x3
46#define BP_CLKCTRL_PLL0CTRL0_RSRVD5 26
47#define BM_CLKCTRL_PLL0CTRL0_RSRVD5 0x0C000000
48#define BF_CLKCTRL_PLL0CTRL0_RSRVD5(v) \
49 (((v) << 26) & BM_CLKCTRL_PLL0CTRL0_RSRVD5)
50#define BP_CLKCTRL_PLL0CTRL0_CP_SEL 24 42#define BP_CLKCTRL_PLL0CTRL0_CP_SEL 24
51#define BM_CLKCTRL_PLL0CTRL0_CP_SEL 0x03000000 43#define BM_CLKCTRL_PLL0CTRL0_CP_SEL 0x03000000
52#define BF_CLKCTRL_PLL0CTRL0_CP_SEL(v) \ 44#define BF_CLKCTRL_PLL0CTRL0_CP_SEL(v) \
@@ -55,10 +47,6 @@
55#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__TIMES_2 0x1 47#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__TIMES_2 0x1
56#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__TIMES_05 0x2 48#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__TIMES_05 0x2
57#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__UNDEFINED 0x3 49#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__UNDEFINED 0x3
58#define BP_CLKCTRL_PLL0CTRL0_RSRVD4 22
59#define BM_CLKCTRL_PLL0CTRL0_RSRVD4 0x00C00000
60#define BF_CLKCTRL_PLL0CTRL0_RSRVD4(v) \
61 (((v) << 22) & BM_CLKCTRL_PLL0CTRL0_RSRVD4)
62#define BP_CLKCTRL_PLL0CTRL0_DIV_SEL 20 50#define BP_CLKCTRL_PLL0CTRL0_DIV_SEL 20
63#define BM_CLKCTRL_PLL0CTRL0_DIV_SEL 0x00300000 51#define BM_CLKCTRL_PLL0CTRL0_DIV_SEL 0x00300000
64#define BF_CLKCTRL_PLL0CTRL0_DIV_SEL(v) \ 52#define BF_CLKCTRL_PLL0CTRL0_DIV_SEL(v) \
@@ -67,22 +55,13 @@
67#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__LOWER 0x1 55#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__LOWER 0x1
68#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__LOWEST 0x2 56#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__LOWEST 0x2
69#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__UNDEFINED 0x3 57#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__UNDEFINED 0x3
70#define BM_CLKCTRL_PLL0CTRL0_RSRVD3 0x00080000
71#define BM_CLKCTRL_PLL0CTRL0_EN_USB_CLKS 0x00040000 58#define BM_CLKCTRL_PLL0CTRL0_EN_USB_CLKS 0x00040000
72#define BM_CLKCTRL_PLL0CTRL0_POWER 0x00020000 59#define BM_CLKCTRL_PLL0CTRL0_POWER 0x00020000
73#define BP_CLKCTRL_PLL0CTRL0_RSRVD1 0
74#define BM_CLKCTRL_PLL0CTRL0_RSRVD1 0x0001FFFF
75#define BF_CLKCTRL_PLL0CTRL0_RSRVD1(v) \
76 (((v) << 0) & BM_CLKCTRL_PLL0CTRL0_RSRVD1)
77 60
78#define HW_CLKCTRL_PLL0CTRL1 (0x00000010) 61#define HW_CLKCTRL_PLL0CTRL1 (0x00000010)
79 62
80#define BM_CLKCTRL_PLL0CTRL1_LOCK 0x80000000 63#define BM_CLKCTRL_PLL0CTRL1_LOCK 0x80000000
81#define BM_CLKCTRL_PLL0CTRL1_FORCE_LOCK 0x40000000 64#define BM_CLKCTRL_PLL0CTRL1_FORCE_LOCK 0x40000000
82#define BP_CLKCTRL_PLL0CTRL1_RSRVD1 16
83#define BM_CLKCTRL_PLL0CTRL1_RSRVD1 0x3FFF0000
84#define BF_CLKCTRL_PLL0CTRL1_RSRVD1(v) \
85 (((v) << 16) & BM_CLKCTRL_PLL0CTRL1_RSRVD1)
86#define BP_CLKCTRL_PLL0CTRL1_LOCK_COUNT 0 65#define BP_CLKCTRL_PLL0CTRL1_LOCK_COUNT 0
87#define BM_CLKCTRL_PLL0CTRL1_LOCK_COUNT 0x0000FFFF 66#define BM_CLKCTRL_PLL0CTRL1_LOCK_COUNT 0x0000FFFF
88#define BF_CLKCTRL_PLL0CTRL1_LOCK_COUNT(v) \ 67#define BF_CLKCTRL_PLL0CTRL1_LOCK_COUNT(v) \
@@ -94,7 +73,6 @@
94#define HW_CLKCTRL_PLL1CTRL0_TOG (0x0000002c) 73#define HW_CLKCTRL_PLL1CTRL0_TOG (0x0000002c)
95 74
96#define BM_CLKCTRL_PLL1CTRL0_CLKGATEEMI 0x80000000 75#define BM_CLKCTRL_PLL1CTRL0_CLKGATEEMI 0x80000000
97#define BM_CLKCTRL_PLL1CTRL0_RSRVD6 0x40000000
98#define BP_CLKCTRL_PLL1CTRL0_LFR_SEL 28 76#define BP_CLKCTRL_PLL1CTRL0_LFR_SEL 28
99#define BM_CLKCTRL_PLL1CTRL0_LFR_SEL 0x30000000 77#define BM_CLKCTRL_PLL1CTRL0_LFR_SEL 0x30000000
100#define BF_CLKCTRL_PLL1CTRL0_LFR_SEL(v) \ 78#define BF_CLKCTRL_PLL1CTRL0_LFR_SEL(v) \
@@ -103,10 +81,6 @@
103#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__TIMES_2 0x1 81#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__TIMES_2 0x1
104#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__TIMES_05 0x2 82#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__TIMES_05 0x2
105#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__UNDEFINED 0x3 83#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__UNDEFINED 0x3
106#define BP_CLKCTRL_PLL1CTRL0_RSRVD5 26
107#define BM_CLKCTRL_PLL1CTRL0_RSRVD5 0x0C000000
108#define BF_CLKCTRL_PLL1CTRL0_RSRVD5(v) \
109 (((v) << 26) & BM_CLKCTRL_PLL1CTRL0_RSRVD5)
110#define BP_CLKCTRL_PLL1CTRL0_CP_SEL 24 84#define BP_CLKCTRL_PLL1CTRL0_CP_SEL 24
111#define BM_CLKCTRL_PLL1CTRL0_CP_SEL 0x03000000 85#define BM_CLKCTRL_PLL1CTRL0_CP_SEL 0x03000000
112#define BF_CLKCTRL_PLL1CTRL0_CP_SEL(v) \ 86#define BF_CLKCTRL_PLL1CTRL0_CP_SEL(v) \
@@ -115,10 +89,6 @@
115#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__TIMES_2 0x1 89#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__TIMES_2 0x1
116#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__TIMES_05 0x2 90#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__TIMES_05 0x2
117#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__UNDEFINED 0x3 91#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__UNDEFINED 0x3
118#define BP_CLKCTRL_PLL1CTRL0_RSRVD4 22
119#define BM_CLKCTRL_PLL1CTRL0_RSRVD4 0x00C00000
120#define BF_CLKCTRL_PLL1CTRL0_RSRVD4(v) \
121 (((v) << 22) & BM_CLKCTRL_PLL1CTRL0_RSRVD4)
122#define BP_CLKCTRL_PLL1CTRL0_DIV_SEL 20 92#define BP_CLKCTRL_PLL1CTRL0_DIV_SEL 20
123#define BM_CLKCTRL_PLL1CTRL0_DIV_SEL 0x00300000 93#define BM_CLKCTRL_PLL1CTRL0_DIV_SEL 0x00300000
124#define BF_CLKCTRL_PLL1CTRL0_DIV_SEL(v) \ 94#define BF_CLKCTRL_PLL1CTRL0_DIV_SEL(v) \
@@ -127,22 +97,13 @@
127#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__LOWER 0x1 97#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__LOWER 0x1
128#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__LOWEST 0x2 98#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__LOWEST 0x2
129#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__UNDEFINED 0x3 99#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__UNDEFINED 0x3
130#define BM_CLKCTRL_PLL1CTRL0_RSRVD3 0x00080000
131#define BM_CLKCTRL_PLL1CTRL0_EN_USB_CLKS 0x00040000 100#define BM_CLKCTRL_PLL1CTRL0_EN_USB_CLKS 0x00040000
132#define BM_CLKCTRL_PLL1CTRL0_POWER 0x00020000 101#define BM_CLKCTRL_PLL1CTRL0_POWER 0x00020000
133#define BP_CLKCTRL_PLL1CTRL0_RSRVD1 0
134#define BM_CLKCTRL_PLL1CTRL0_RSRVD1 0x0001FFFF
135#define BF_CLKCTRL_PLL1CTRL0_RSRVD1(v) \
136 (((v) << 0) & BM_CLKCTRL_PLL1CTRL0_RSRVD1)
137 102
138#define HW_CLKCTRL_PLL1CTRL1 (0x00000030) 103#define HW_CLKCTRL_PLL1CTRL1 (0x00000030)
139 104
140#define BM_CLKCTRL_PLL1CTRL1_LOCK 0x80000000 105#define BM_CLKCTRL_PLL1CTRL1_LOCK 0x80000000
141#define BM_CLKCTRL_PLL1CTRL1_FORCE_LOCK 0x40000000 106#define BM_CLKCTRL_PLL1CTRL1_FORCE_LOCK 0x40000000
142#define BP_CLKCTRL_PLL1CTRL1_RSRVD1 16
143#define BM_CLKCTRL_PLL1CTRL1_RSRVD1 0x3FFF0000
144#define BF_CLKCTRL_PLL1CTRL1_RSRVD1(v) \
145 (((v) << 16) & BM_CLKCTRL_PLL1CTRL1_RSRVD1)
146#define BP_CLKCTRL_PLL1CTRL1_LOCK_COUNT 0 107#define BP_CLKCTRL_PLL1CTRL1_LOCK_COUNT 0
147#define BM_CLKCTRL_PLL1CTRL1_LOCK_COUNT 0x0000FFFF 108#define BM_CLKCTRL_PLL1CTRL1_LOCK_COUNT 0x0000FFFF
148#define BF_CLKCTRL_PLL1CTRL1_LOCK_COUNT(v) \ 109#define BF_CLKCTRL_PLL1CTRL1_LOCK_COUNT(v) \
@@ -154,51 +115,31 @@
154#define HW_CLKCTRL_PLL2CTRL0_TOG (0x0000004c) 115#define HW_CLKCTRL_PLL2CTRL0_TOG (0x0000004c)
155 116
156#define BM_CLKCTRL_PLL2CTRL0_CLKGATE 0x80000000 117#define BM_CLKCTRL_PLL2CTRL0_CLKGATE 0x80000000
157#define BM_CLKCTRL_PLL2CTRL0_RSRVD3 0x40000000
158#define BP_CLKCTRL_PLL2CTRL0_LFR_SEL 28 118#define BP_CLKCTRL_PLL2CTRL0_LFR_SEL 28
159#define BM_CLKCTRL_PLL2CTRL0_LFR_SEL 0x30000000 119#define BM_CLKCTRL_PLL2CTRL0_LFR_SEL 0x30000000
160#define BF_CLKCTRL_PLL2CTRL0_LFR_SEL(v) \ 120#define BF_CLKCTRL_PLL2CTRL0_LFR_SEL(v) \
161 (((v) << 28) & BM_CLKCTRL_PLL2CTRL0_LFR_SEL) 121 (((v) << 28) & BM_CLKCTRL_PLL2CTRL0_LFR_SEL)
162#define BM_CLKCTRL_PLL2CTRL0_RSRVD2 0x08000000
163#define BM_CLKCTRL_PLL2CTRL0_HOLD_RING_OFF_B 0x04000000 122#define BM_CLKCTRL_PLL2CTRL0_HOLD_RING_OFF_B 0x04000000
164#define BP_CLKCTRL_PLL2CTRL0_CP_SEL 24 123#define BP_CLKCTRL_PLL2CTRL0_CP_SEL 24
165#define BM_CLKCTRL_PLL2CTRL0_CP_SEL 0x03000000 124#define BM_CLKCTRL_PLL2CTRL0_CP_SEL 0x03000000
166#define BF_CLKCTRL_PLL2CTRL0_CP_SEL(v) \ 125#define BF_CLKCTRL_PLL2CTRL0_CP_SEL(v) \
167 (((v) << 24) & BM_CLKCTRL_PLL2CTRL0_CP_SEL) 126 (((v) << 24) & BM_CLKCTRL_PLL2CTRL0_CP_SEL)
168#define BM_CLKCTRL_PLL2CTRL0_POWER 0x00800000 127#define BM_CLKCTRL_PLL2CTRL0_POWER 0x00800000
169#define BP_CLKCTRL_PLL2CTRL0_RSRVD1 0
170#define BM_CLKCTRL_PLL2CTRL0_RSRVD1 0x007FFFFF
171#define BF_CLKCTRL_PLL2CTRL0_RSRVD1(v) \
172 (((v) << 0) & BM_CLKCTRL_PLL2CTRL0_RSRVD1)
173 128
174#define HW_CLKCTRL_CPU (0x00000050) 129#define HW_CLKCTRL_CPU (0x00000050)
175#define HW_CLKCTRL_CPU_SET (0x00000054) 130#define HW_CLKCTRL_CPU_SET (0x00000054)
176#define HW_CLKCTRL_CPU_CLR (0x00000058) 131#define HW_CLKCTRL_CPU_CLR (0x00000058)
177#define HW_CLKCTRL_CPU_TOG (0x0000005c) 132#define HW_CLKCTRL_CPU_TOG (0x0000005c)
178 133
179#define BP_CLKCTRL_CPU_RSRVD5 30
180#define BM_CLKCTRL_CPU_RSRVD5 0xC0000000
181#define BF_CLKCTRL_CPU_RSRVD5(v) \
182 (((v) << 30) & BM_CLKCTRL_CPU_RSRVD5)
183#define BM_CLKCTRL_CPU_BUSY_REF_XTAL 0x20000000 134#define BM_CLKCTRL_CPU_BUSY_REF_XTAL 0x20000000
184#define BM_CLKCTRL_CPU_BUSY_REF_CPU 0x10000000 135#define BM_CLKCTRL_CPU_BUSY_REF_CPU 0x10000000
185#define BM_CLKCTRL_CPU_RSRVD4 0x08000000
186#define BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN 0x04000000 136#define BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN 0x04000000
187#define BP_CLKCTRL_CPU_DIV_XTAL 16 137#define BP_CLKCTRL_CPU_DIV_XTAL 16
188#define BM_CLKCTRL_CPU_DIV_XTAL 0x03FF0000 138#define BM_CLKCTRL_CPU_DIV_XTAL 0x03FF0000
189#define BF_CLKCTRL_CPU_DIV_XTAL(v) \ 139#define BF_CLKCTRL_CPU_DIV_XTAL(v) \
190 (((v) << 16) & BM_CLKCTRL_CPU_DIV_XTAL) 140 (((v) << 16) & BM_CLKCTRL_CPU_DIV_XTAL)
191#define BP_CLKCTRL_CPU_RSRVD3 13
192#define BM_CLKCTRL_CPU_RSRVD3 0x0000E000
193#define BF_CLKCTRL_CPU_RSRVD3(v) \
194 (((v) << 13) & BM_CLKCTRL_CPU_RSRVD3)
195#define BM_CLKCTRL_CPU_INTERRUPT_WAIT 0x00001000 141#define BM_CLKCTRL_CPU_INTERRUPT_WAIT 0x00001000
196#define BM_CLKCTRL_CPU_RSRVD2 0x00000800
197#define BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN 0x00000400 142#define BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN 0x00000400
198#define BP_CLKCTRL_CPU_RSRVD1 6
199#define BM_CLKCTRL_CPU_RSRVD1 0x000003C0
200#define BF_CLKCTRL_CPU_RSRVD1(v) \
201 (((v) << 6) & BM_CLKCTRL_CPU_RSRVD1)
202#define BP_CLKCTRL_CPU_DIV_CPU 0 143#define BP_CLKCTRL_CPU_DIV_CPU 0
203#define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F 144#define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F
204#define BF_CLKCTRL_CPU_DIV_CPU(v) \ 145#define BF_CLKCTRL_CPU_DIV_CPU(v) \
@@ -212,7 +153,6 @@
212#define BM_CLKCTRL_HBUS_ASM_BUSY 0x80000000 153#define BM_CLKCTRL_HBUS_ASM_BUSY 0x80000000
213#define BM_CLKCTRL_HBUS_DCP_AS_ENABLE 0x40000000 154#define BM_CLKCTRL_HBUS_DCP_AS_ENABLE 0x40000000
214#define BM_CLKCTRL_HBUS_PXP_AS_ENABLE 0x20000000 155#define BM_CLKCTRL_HBUS_PXP_AS_ENABLE 0x20000000
215#define BM_CLKCTRL_HBUS_RSRVD2 0x10000000
216#define BM_CLKCTRL_HBUS_ASM_EMIPORT_AS_ENABLE 0x08000000 156#define BM_CLKCTRL_HBUS_ASM_EMIPORT_AS_ENABLE 0x08000000
217#define BM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE 0x04000000 157#define BM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE 0x04000000
218#define BM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE 0x02000000 158#define BM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE 0x02000000
@@ -232,10 +172,6 @@
232#define BV_CLKCTRL_HBUS_SLOW_DIV__BY8 0x3 172#define BV_CLKCTRL_HBUS_SLOW_DIV__BY8 0x3
233#define BV_CLKCTRL_HBUS_SLOW_DIV__BY16 0x4 173#define BV_CLKCTRL_HBUS_SLOW_DIV__BY16 0x4
234#define BV_CLKCTRL_HBUS_SLOW_DIV__BY32 0x5 174#define BV_CLKCTRL_HBUS_SLOW_DIV__BY32 0x5
235#define BP_CLKCTRL_HBUS_RSRVD1 6
236#define BM_CLKCTRL_HBUS_RSRVD1 0x0000FFC0
237#define BF_CLKCTRL_HBUS_RSRVD1(v) \
238 (((v) << 6) & BM_CLKCTRL_HBUS_RSRVD1)
239#define BM_CLKCTRL_HBUS_DIV_FRAC_EN 0x00000020 175#define BM_CLKCTRL_HBUS_DIV_FRAC_EN 0x00000020
240#define BP_CLKCTRL_HBUS_DIV 0 176#define BP_CLKCTRL_HBUS_DIV 0
241#define BM_CLKCTRL_HBUS_DIV 0x0000001F 177#define BM_CLKCTRL_HBUS_DIV 0x0000001F
@@ -245,10 +181,6 @@
245#define HW_CLKCTRL_XBUS (0x00000070) 181#define HW_CLKCTRL_XBUS (0x00000070)
246 182
247#define BM_CLKCTRL_XBUS_BUSY 0x80000000 183#define BM_CLKCTRL_XBUS_BUSY 0x80000000
248#define BP_CLKCTRL_XBUS_RSRVD1 12
249#define BM_CLKCTRL_XBUS_RSRVD1 0x7FFFF000
250#define BF_CLKCTRL_XBUS_RSRVD1(v) \
251 (((v) << 12) & BM_CLKCTRL_XBUS_RSRVD1)
252#define BM_CLKCTRL_XBUS_AUTO_CLEAR_DIV_ENABLE 0x00000800 184#define BM_CLKCTRL_XBUS_AUTO_CLEAR_DIV_ENABLE 0x00000800
253#define BM_CLKCTRL_XBUS_DIV_FRAC_EN 0x00000400 185#define BM_CLKCTRL_XBUS_DIV_FRAC_EN 0x00000400
254#define BP_CLKCTRL_XBUS_DIV 0 186#define BP_CLKCTRL_XBUS_DIV 0
@@ -263,19 +195,10 @@
263 195
264#define BP_CLKCTRL_XTAL_UART_CLK_GATE 31 196#define BP_CLKCTRL_XTAL_UART_CLK_GATE 31
265#define BM_CLKCTRL_XTAL_UART_CLK_GATE 0x80000000 197#define BM_CLKCTRL_XTAL_UART_CLK_GATE 0x80000000
266#define BM_CLKCTRL_XTAL_RSRVD3 0x40000000
267#define BP_CLKCTRL_XTAL_PWM_CLK24M_GATE 29 198#define BP_CLKCTRL_XTAL_PWM_CLK24M_GATE 29
268#define BM_CLKCTRL_XTAL_PWM_CLK24M_GATE 0x20000000 199#define BM_CLKCTRL_XTAL_PWM_CLK24M_GATE 0x20000000
269#define BP_CLKCTRL_XTAL_RSRVD2 27
270#define BM_CLKCTRL_XTAL_RSRVD2 0x18000000
271#define BF_CLKCTRL_XTAL_RSRVD2(v) \
272 (((v) << 27) & BM_CLKCTRL_XTAL_RSRVD2)
273#define BP_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 26 200#define BP_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 26
274#define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 0x04000000 201#define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 0x04000000
275#define BP_CLKCTRL_XTAL_RSRVD1 2
276#define BM_CLKCTRL_XTAL_RSRVD1 0x03FFFFFC
277#define BF_CLKCTRL_XTAL_RSRVD1(v) \
278 (((v) << 2) & BM_CLKCTRL_XTAL_RSRVD1)
279#define BP_CLKCTRL_XTAL_DIV_UART 0 202#define BP_CLKCTRL_XTAL_DIV_UART 0
280#define BM_CLKCTRL_XTAL_DIV_UART 0x00000003 203#define BM_CLKCTRL_XTAL_DIV_UART 0x00000003
281#define BF_CLKCTRL_XTAL_DIV_UART(v) \ 204#define BF_CLKCTRL_XTAL_DIV_UART(v) \
@@ -285,12 +208,7 @@
285 208
286#define BP_CLKCTRL_SSP0_CLKGATE 31 209#define BP_CLKCTRL_SSP0_CLKGATE 31
287#define BM_CLKCTRL_SSP0_CLKGATE 0x80000000 210#define BM_CLKCTRL_SSP0_CLKGATE 0x80000000
288#define BM_CLKCTRL_SSP0_RSRVD2 0x40000000
289#define BM_CLKCTRL_SSP0_BUSY 0x20000000 211#define BM_CLKCTRL_SSP0_BUSY 0x20000000
290#define BP_CLKCTRL_SSP0_RSRVD1 10
291#define BM_CLKCTRL_SSP0_RSRVD1 0x1FFFFC00
292#define BF_CLKCTRL_SSP0_RSRVD1(v) \
293 (((v) << 10) & BM_CLKCTRL_SSP0_RSRVD1)
294#define BM_CLKCTRL_SSP0_DIV_FRAC_EN 0x00000200 212#define BM_CLKCTRL_SSP0_DIV_FRAC_EN 0x00000200
295#define BP_CLKCTRL_SSP0_DIV 0 213#define BP_CLKCTRL_SSP0_DIV 0
296#define BM_CLKCTRL_SSP0_DIV 0x000001FF 214#define BM_CLKCTRL_SSP0_DIV 0x000001FF
@@ -301,12 +219,7 @@
301 219
302#define BP_CLKCTRL_SSP1_CLKGATE 31 220#define BP_CLKCTRL_SSP1_CLKGATE 31
303#define BM_CLKCTRL_SSP1_CLKGATE 0x80000000 221#define BM_CLKCTRL_SSP1_CLKGATE 0x80000000
304#define BM_CLKCTRL_SSP1_RSRVD2 0x40000000
305#define BM_CLKCTRL_SSP1_BUSY 0x20000000 222#define BM_CLKCTRL_SSP1_BUSY 0x20000000
306#define BP_CLKCTRL_SSP1_RSRVD1 10
307#define BM_CLKCTRL_SSP1_RSRVD1 0x1FFFFC00
308#define BF_CLKCTRL_SSP1_RSRVD1(v) \
309 (((v) << 10) & BM_CLKCTRL_SSP1_RSRVD1)
310#define BM_CLKCTRL_SSP1_DIV_FRAC_EN 0x00000200 223#define BM_CLKCTRL_SSP1_DIV_FRAC_EN 0x00000200
311#define BP_CLKCTRL_SSP1_DIV 0 224#define BP_CLKCTRL_SSP1_DIV 0
312#define BM_CLKCTRL_SSP1_DIV 0x000001FF 225#define BM_CLKCTRL_SSP1_DIV 0x000001FF
@@ -317,12 +230,7 @@
317 230
318#define BP_CLKCTRL_SSP2_CLKGATE 31 231#define BP_CLKCTRL_SSP2_CLKGATE 31
319#define BM_CLKCTRL_SSP2_CLKGATE 0x80000000 232#define BM_CLKCTRL_SSP2_CLKGATE 0x80000000
320#define BM_CLKCTRL_SSP2_RSRVD2 0x40000000
321#define BM_CLKCTRL_SSP2_BUSY 0x20000000 233#define BM_CLKCTRL_SSP2_BUSY 0x20000000
322#define BP_CLKCTRL_SSP2_RSRVD1 10
323#define BM_CLKCTRL_SSP2_RSRVD1 0x1FFFFC00
324#define BF_CLKCTRL_SSP2_RSRVD1(v) \
325 (((v) << 10) & BM_CLKCTRL_SSP2_RSRVD1)
326#define BM_CLKCTRL_SSP2_DIV_FRAC_EN 0x00000200 234#define BM_CLKCTRL_SSP2_DIV_FRAC_EN 0x00000200
327#define BP_CLKCTRL_SSP2_DIV 0 235#define BP_CLKCTRL_SSP2_DIV 0
328#define BM_CLKCTRL_SSP2_DIV 0x000001FF 236#define BM_CLKCTRL_SSP2_DIV 0x000001FF
@@ -333,12 +241,7 @@
333 241
334#define BP_CLKCTRL_SSP3_CLKGATE 31 242#define BP_CLKCTRL_SSP3_CLKGATE 31
335#define BM_CLKCTRL_SSP3_CLKGATE 0x80000000 243#define BM_CLKCTRL_SSP3_CLKGATE 0x80000000
336#define BM_CLKCTRL_SSP3_RSRVD2 0x40000000
337#define BM_CLKCTRL_SSP3_BUSY 0x20000000 244#define BM_CLKCTRL_SSP3_BUSY 0x20000000
338#define BP_CLKCTRL_SSP3_RSRVD1 10
339#define BM_CLKCTRL_SSP3_RSRVD1 0x1FFFFC00
340#define BF_CLKCTRL_SSP3_RSRVD1(v) \
341 (((v) << 10) & BM_CLKCTRL_SSP3_RSRVD1)
342#define BM_CLKCTRL_SSP3_DIV_FRAC_EN 0x00000200 245#define BM_CLKCTRL_SSP3_DIV_FRAC_EN 0x00000200
343#define BP_CLKCTRL_SSP3_DIV 0 246#define BP_CLKCTRL_SSP3_DIV 0
344#define BM_CLKCTRL_SSP3_DIV 0x000001FF 247#define BM_CLKCTRL_SSP3_DIV 0x000001FF
@@ -349,12 +252,7 @@
349 252
350#define BP_CLKCTRL_GPMI_CLKGATE 31 253#define BP_CLKCTRL_GPMI_CLKGATE 31
351#define BM_CLKCTRL_GPMI_CLKGATE 0x80000000 254#define BM_CLKCTRL_GPMI_CLKGATE 0x80000000
352#define BM_CLKCTRL_GPMI_RSRVD2 0x40000000
353#define BM_CLKCTRL_GPMI_BUSY 0x20000000 255#define BM_CLKCTRL_GPMI_BUSY 0x20000000
354#define BP_CLKCTRL_GPMI_RSRVD1 11
355#define BM_CLKCTRL_GPMI_RSRVD1 0x1FFFF800
356#define BF_CLKCTRL_GPMI_RSRVD1(v) \
357 (((v) << 11) & BM_CLKCTRL_GPMI_RSRVD1)
358#define BM_CLKCTRL_GPMI_DIV_FRAC_EN 0x00000400 256#define BM_CLKCTRL_GPMI_DIV_FRAC_EN 0x00000400
359#define BP_CLKCTRL_GPMI_DIV 0 257#define BP_CLKCTRL_GPMI_DIV 0
360#define BM_CLKCTRL_GPMI_DIV 0x000003FF 258#define BM_CLKCTRL_GPMI_DIV 0x000003FF
@@ -365,10 +263,6 @@
365 263
366#define BP_CLKCTRL_SPDIF_CLKGATE 31 264#define BP_CLKCTRL_SPDIF_CLKGATE 31
367#define BM_CLKCTRL_SPDIF_CLKGATE 0x80000000 265#define BM_CLKCTRL_SPDIF_CLKGATE 0x80000000
368#define BP_CLKCTRL_SPDIF_RSRVD 0
369#define BM_CLKCTRL_SPDIF_RSRVD 0x7FFFFFFF
370#define BF_CLKCTRL_SPDIF_RSRVD(v) \
371 (((v) << 0) & BM_CLKCTRL_SPDIF_RSRVD)
372 266
373#define HW_CLKCTRL_EMI (0x000000f0) 267#define HW_CLKCTRL_EMI (0x000000f0)
374 268
@@ -379,24 +273,12 @@
379#define BM_CLKCTRL_EMI_BUSY_REF_EMI 0x10000000 273#define BM_CLKCTRL_EMI_BUSY_REF_EMI 0x10000000
380#define BM_CLKCTRL_EMI_BUSY_REF_CPU 0x08000000 274#define BM_CLKCTRL_EMI_BUSY_REF_CPU 0x08000000
381#define BM_CLKCTRL_EMI_BUSY_SYNC_MODE 0x04000000 275#define BM_CLKCTRL_EMI_BUSY_SYNC_MODE 0x04000000
382#define BP_CLKCTRL_EMI_RSRVD3 18
383#define BM_CLKCTRL_EMI_RSRVD3 0x03FC0000
384#define BF_CLKCTRL_EMI_RSRVD3(v) \
385 (((v) << 18) & BM_CLKCTRL_EMI_RSRVD3)
386#define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC 0x00020000 276#define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC 0x00020000
387#define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE 0x00010000 277#define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE 0x00010000
388#define BP_CLKCTRL_EMI_RSRVD2 12
389#define BM_CLKCTRL_EMI_RSRVD2 0x0000F000
390#define BF_CLKCTRL_EMI_RSRVD2(v) \
391 (((v) << 12) & BM_CLKCTRL_EMI_RSRVD2)
392#define BP_CLKCTRL_EMI_DIV_XTAL 8 278#define BP_CLKCTRL_EMI_DIV_XTAL 8
393#define BM_CLKCTRL_EMI_DIV_XTAL 0x00000F00 279#define BM_CLKCTRL_EMI_DIV_XTAL 0x00000F00
394#define BF_CLKCTRL_EMI_DIV_XTAL(v) \ 280#define BF_CLKCTRL_EMI_DIV_XTAL(v) \
395 (((v) << 8) & BM_CLKCTRL_EMI_DIV_XTAL) 281 (((v) << 8) & BM_CLKCTRL_EMI_DIV_XTAL)
396#define BP_CLKCTRL_EMI_RSRVD1 6
397#define BM_CLKCTRL_EMI_RSRVD1 0x000000C0
398#define BF_CLKCTRL_EMI_RSRVD1(v) \
399 (((v) << 6) & BM_CLKCTRL_EMI_RSRVD1)
400#define BP_CLKCTRL_EMI_DIV_EMI 0 282#define BP_CLKCTRL_EMI_DIV_EMI 0
401#define BM_CLKCTRL_EMI_DIV_EMI 0x0000003F 283#define BM_CLKCTRL_EMI_DIV_EMI 0x0000003F
402#define BF_CLKCTRL_EMI_DIV_EMI(v) \ 284#define BF_CLKCTRL_EMI_DIV_EMI(v) \
@@ -406,12 +288,7 @@
406 288
407#define BP_CLKCTRL_SAIF0_CLKGATE 31 289#define BP_CLKCTRL_SAIF0_CLKGATE 31
408#define BM_CLKCTRL_SAIF0_CLKGATE 0x80000000 290#define BM_CLKCTRL_SAIF0_CLKGATE 0x80000000
409#define BM_CLKCTRL_SAIF0_RSRVD2 0x40000000
410#define BM_CLKCTRL_SAIF0_BUSY 0x20000000 291#define BM_CLKCTRL_SAIF0_BUSY 0x20000000
411#define BP_CLKCTRL_SAIF0_RSRVD1 17
412#define BM_CLKCTRL_SAIF0_RSRVD1 0x1FFE0000
413#define BF_CLKCTRL_SAIF0_RSRVD1(v) \
414 (((v) << 17) & BM_CLKCTRL_SAIF0_RSRVD1)
415#define BM_CLKCTRL_SAIF0_DIV_FRAC_EN 0x00010000 292#define BM_CLKCTRL_SAIF0_DIV_FRAC_EN 0x00010000
416#define BP_CLKCTRL_SAIF0_DIV 0 293#define BP_CLKCTRL_SAIF0_DIV 0
417#define BM_CLKCTRL_SAIF0_DIV 0x0000FFFF 294#define BM_CLKCTRL_SAIF0_DIV 0x0000FFFF
@@ -422,12 +299,7 @@
422 299
423#define BP_CLKCTRL_SAIF1_CLKGATE 31 300#define BP_CLKCTRL_SAIF1_CLKGATE 31
424#define BM_CLKCTRL_SAIF1_CLKGATE 0x80000000 301#define BM_CLKCTRL_SAIF1_CLKGATE 0x80000000
425#define BM_CLKCTRL_SAIF1_RSRVD2 0x40000000
426#define BM_CLKCTRL_SAIF1_BUSY 0x20000000 302#define BM_CLKCTRL_SAIF1_BUSY 0x20000000
427#define BP_CLKCTRL_SAIF1_RSRVD1 17
428#define BM_CLKCTRL_SAIF1_RSRVD1 0x1FFE0000
429#define BF_CLKCTRL_SAIF1_RSRVD1(v) \
430 (((v) << 17) & BM_CLKCTRL_SAIF1_RSRVD1)
431#define BM_CLKCTRL_SAIF1_DIV_FRAC_EN 0x00010000 303#define BM_CLKCTRL_SAIF1_DIV_FRAC_EN 0x00010000
432#define BP_CLKCTRL_SAIF1_DIV 0 304#define BP_CLKCTRL_SAIF1_DIV 0
433#define BM_CLKCTRL_SAIF1_DIV 0x0000FFFF 305#define BM_CLKCTRL_SAIF1_DIV 0x0000FFFF
@@ -438,12 +310,7 @@
438 310
439#define BP_CLKCTRL_DIS_LCDIF_CLKGATE 31 311#define BP_CLKCTRL_DIS_LCDIF_CLKGATE 31
440#define BM_CLKCTRL_DIS_LCDIF_CLKGATE 0x80000000 312#define BM_CLKCTRL_DIS_LCDIF_CLKGATE 0x80000000
441#define BM_CLKCTRL_DIS_LCDIF_RSRVD2 0x40000000
442#define BM_CLKCTRL_DIS_LCDIF_BUSY 0x20000000 313#define BM_CLKCTRL_DIS_LCDIF_BUSY 0x20000000
443#define BP_CLKCTRL_DIS_LCDIF_RSRVD1 14
444#define BM_CLKCTRL_DIS_LCDIF_RSRVD1 0x1FFFC000
445#define BF_CLKCTRL_DIS_LCDIF_RSRVD1(v) \
446 (((v) << 14) & BM_CLKCTRL_DIS_LCDIF_RSRVD1)
447#define BM_CLKCTRL_DIS_LCDIF_DIV_FRAC_EN 0x00002000 314#define BM_CLKCTRL_DIS_LCDIF_DIV_FRAC_EN 0x00002000
448#define BP_CLKCTRL_DIS_LCDIF_DIV 0 315#define BP_CLKCTRL_DIS_LCDIF_DIV 0
449#define BM_CLKCTRL_DIS_LCDIF_DIV 0x00001FFF 316#define BM_CLKCTRL_DIS_LCDIF_DIV 0x00001FFF
@@ -453,12 +320,7 @@
453#define HW_CLKCTRL_ETM (0x00000130) 320#define HW_CLKCTRL_ETM (0x00000130)
454 321
455#define BM_CLKCTRL_ETM_CLKGATE 0x80000000 322#define BM_CLKCTRL_ETM_CLKGATE 0x80000000
456#define BM_CLKCTRL_ETM_RSRVD2 0x40000000
457#define BM_CLKCTRL_ETM_BUSY 0x20000000 323#define BM_CLKCTRL_ETM_BUSY 0x20000000
458#define BP_CLKCTRL_ETM_RSRVD1 8
459#define BM_CLKCTRL_ETM_RSRVD1 0x1FFFFF00
460#define BF_CLKCTRL_ETM_RSRVD1(v) \
461 (((v) << 8) & BM_CLKCTRL_ETM_RSRVD1)
462#define BM_CLKCTRL_ETM_DIV_FRAC_EN 0x00000080 324#define BM_CLKCTRL_ETM_DIV_FRAC_EN 0x00000080
463#define BP_CLKCTRL_ETM_DIV 0 325#define BP_CLKCTRL_ETM_DIV 0
464#define BM_CLKCTRL_ETM_DIV 0x0000007F 326#define BM_CLKCTRL_ETM_DIV 0x0000007F
@@ -471,7 +333,6 @@
471#define BP_CLKCTRL_ENET_DISABLE 30 333#define BP_CLKCTRL_ENET_DISABLE 30
472#define BM_CLKCTRL_ENET_DISABLE 0x40000000 334#define BM_CLKCTRL_ENET_DISABLE 0x40000000
473#define BM_CLKCTRL_ENET_STATUS 0x20000000 335#define BM_CLKCTRL_ENET_STATUS 0x20000000
474#define BM_CLKCTRL_ENET_RSRVD1 0x10000000
475#define BM_CLKCTRL_ENET_BUSY_TIME 0x08000000 336#define BM_CLKCTRL_ENET_BUSY_TIME 0x08000000
476#define BP_CLKCTRL_ENET_DIV_TIME 21 337#define BP_CLKCTRL_ENET_DIV_TIME 21
477#define BM_CLKCTRL_ENET_DIV_TIME 0x07E00000 338#define BM_CLKCTRL_ENET_DIV_TIME 0x07E00000
@@ -493,37 +354,23 @@
493#define BM_CLKCTRL_ENET_CLK_OUT_EN 0x00040000 354#define BM_CLKCTRL_ENET_CLK_OUT_EN 0x00040000
494#define BM_CLKCTRL_ENET_RESET_BY_SW_CHIP 0x00020000 355#define BM_CLKCTRL_ENET_RESET_BY_SW_CHIP 0x00020000
495#define BM_CLKCTRL_ENET_RESET_BY_SW 0x00010000 356#define BM_CLKCTRL_ENET_RESET_BY_SW 0x00010000
496#define BP_CLKCTRL_ENET_RSRVD0 0
497#define BM_CLKCTRL_ENET_RSRVD0 0x0000FFFF
498#define BF_CLKCTRL_ENET_RSRVD0(v) \
499 (((v) << 0) & BM_CLKCTRL_ENET_RSRVD0)
500 357
501#define HW_CLKCTRL_HSADC (0x00000150) 358#define HW_CLKCTRL_HSADC (0x00000150)
502 359
503#define BM_CLKCTRL_HSADC_RSRVD2 0x80000000
504#define BM_CLKCTRL_HSADC_RESETB 0x40000000 360#define BM_CLKCTRL_HSADC_RESETB 0x40000000
505#define BP_CLKCTRL_HSADC_FREQDIV 28 361#define BP_CLKCTRL_HSADC_FREQDIV 28
506#define BM_CLKCTRL_HSADC_FREQDIV 0x30000000 362#define BM_CLKCTRL_HSADC_FREQDIV 0x30000000
507#define BF_CLKCTRL_HSADC_FREQDIV(v) \ 363#define BF_CLKCTRL_HSADC_FREQDIV(v) \
508 (((v) << 28) & BM_CLKCTRL_HSADC_FREQDIV) 364 (((v) << 28) & BM_CLKCTRL_HSADC_FREQDIV)
509#define BP_CLKCTRL_HSADC_RSRVD1 0
510#define BM_CLKCTRL_HSADC_RSRVD1 0x0FFFFFFF
511#define BF_CLKCTRL_HSADC_RSRVD1(v) \
512 (((v) << 0) & BM_CLKCTRL_HSADC_RSRVD1)
513 365
514#define HW_CLKCTRL_FLEXCAN (0x00000160) 366#define HW_CLKCTRL_FLEXCAN (0x00000160)
515 367
516#define BM_CLKCTRL_FLEXCAN_RSRVD2 0x80000000
517#define BP_CLKCTRL_FLEXCAN_STOP_CAN0 30 368#define BP_CLKCTRL_FLEXCAN_STOP_CAN0 30
518#define BM_CLKCTRL_FLEXCAN_STOP_CAN0 0x40000000 369#define BM_CLKCTRL_FLEXCAN_STOP_CAN0 0x40000000
519#define BM_CLKCTRL_FLEXCAN_CAN0_STATUS 0x20000000 370#define BM_CLKCTRL_FLEXCAN_CAN0_STATUS 0x20000000
520#define BP_CLKCTRL_FLEXCAN_STOP_CAN1 28 371#define BP_CLKCTRL_FLEXCAN_STOP_CAN1 28
521#define BM_CLKCTRL_FLEXCAN_STOP_CAN1 0x10000000 372#define BM_CLKCTRL_FLEXCAN_STOP_CAN1 0x10000000
522#define BM_CLKCTRL_FLEXCAN_CAN1_STATUS 0x08000000 373#define BM_CLKCTRL_FLEXCAN_CAN1_STATUS 0x08000000
523#define BP_CLKCTRL_FLEXCAN_RSRVD1 0
524#define BM_CLKCTRL_FLEXCAN_RSRVD1 0x07FFFFFF
525#define BF_CLKCTRL_FLEXCAN_RSRVD1(v) \
526 (((v) << 0) & BM_CLKCTRL_FLEXCAN_RSRVD1)
527 374
528#define HW_CLKCTRL_FRAC0 (0x000001b0) 375#define HW_CLKCTRL_FRAC0 (0x000001b0)
529#define HW_CLKCTRL_FRAC0_SET (0x000001b4) 376#define HW_CLKCTRL_FRAC0_SET (0x000001b4)
@@ -564,10 +411,6 @@
564#define HW_CLKCTRL_FRAC1_CLR (0x000001c8) 411#define HW_CLKCTRL_FRAC1_CLR (0x000001c8)
565#define HW_CLKCTRL_FRAC1_TOG (0x000001cc) 412#define HW_CLKCTRL_FRAC1_TOG (0x000001cc)
566 413
567#define BP_CLKCTRL_FRAC1_RSRVD2 24
568#define BM_CLKCTRL_FRAC1_RSRVD2 0xFF000000
569#define BF_CLKCTRL_FRAC1_RSRVD2(v) \
570 (((v) << 24) & BM_CLKCTRL_FRAC1_RSRVD2)
571#define BP_CLKCTRL_FRAC1_CLKGATEGPMI 23 414#define BP_CLKCTRL_FRAC1_CLKGATEGPMI 23
572#define BM_CLKCTRL_FRAC1_CLKGATEGPMI 0x00800000 415#define BM_CLKCTRL_FRAC1_CLKGATEGPMI 0x00800000
573#define BM_CLKCTRL_FRAC1_GPMI_STABLE 0x00400000 416#define BM_CLKCTRL_FRAC1_GPMI_STABLE 0x00400000
@@ -595,22 +438,10 @@
595#define HW_CLKCTRL_CLKSEQ_CLR (0x000001d8) 438#define HW_CLKCTRL_CLKSEQ_CLR (0x000001d8)
596#define HW_CLKCTRL_CLKSEQ_TOG (0x000001dc) 439#define HW_CLKCTRL_CLKSEQ_TOG (0x000001dc)
597 440
598#define BP_CLKCTRL_CLKSEQ_RSRVD0 19
599#define BM_CLKCTRL_CLKSEQ_RSRVD0 0xFFF80000
600#define BF_CLKCTRL_CLKSEQ_RSRVD0(v) \
601 (((v) << 19) & BM_CLKCTRL_CLKSEQ_RSRVD0)
602#define BM_CLKCTRL_CLKSEQ_BYPASS_CPU 0x00040000 441#define BM_CLKCTRL_CLKSEQ_BYPASS_CPU 0x00040000
603#define BP_CLKCTRL_CLKSEQ_RSRVD1 15
604#define BM_CLKCTRL_CLKSEQ_RSRVD1 0x00038000
605#define BF_CLKCTRL_CLKSEQ_RSRVD1(v) \
606 (((v) << 15) & BM_CLKCTRL_CLKSEQ_RSRVD1)
607#define BM_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF 0x00004000 442#define BM_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF 0x00004000
608#define BV_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF__BYPASS 0x1 443#define BV_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF__BYPASS 0x1
609#define BV_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF__PFD 0x0 444#define BV_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF__PFD 0x0
610#define BP_CLKCTRL_CLKSEQ_RSRVD2 9
611#define BM_CLKCTRL_CLKSEQ_RSRVD2 0x00003E00
612#define BF_CLKCTRL_CLKSEQ_RSRVD2(v) \
613 (((v) << 9) & BM_CLKCTRL_CLKSEQ_RSRVD2)
614#define BM_CLKCTRL_CLKSEQ_BYPASS_ETM 0x00000100 445#define BM_CLKCTRL_CLKSEQ_BYPASS_ETM 0x00000100
615#define BM_CLKCTRL_CLKSEQ_BYPASS_EMI 0x00000080 446#define BM_CLKCTRL_CLKSEQ_BYPASS_EMI 0x00000080
616#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP3 0x00000040 447#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP3 0x00000040
@@ -623,10 +454,6 @@
623 454
624#define HW_CLKCTRL_RESET (0x000001e0) 455#define HW_CLKCTRL_RESET (0x000001e0)
625 456
626#define BP_CLKCTRL_RESET_RSRVD 6
627#define BM_CLKCTRL_RESET_RSRVD 0xFFFFFFC0
628#define BF_CLKCTRL_RESET_RSRVD(v) \
629 (((v) << 6) & BM_CLKCTRL_RESET_RSRVD)
630#define BM_CLKCTRL_RESET_WDOG_POR_DISABLE 0x00000020 457#define BM_CLKCTRL_RESET_WDOG_POR_DISABLE 0x00000020
631#define BM_CLKCTRL_RESET_EXTERNAL_RESET_ENABLE 0x00000010 458#define BM_CLKCTRL_RESET_EXTERNAL_RESET_ENABLE 0x00000010
632#define BM_CLKCTRL_RESET_THERMAL_RESET_ENABLE 0x00000008 459#define BM_CLKCTRL_RESET_THERMAL_RESET_ENABLE 0x00000008
@@ -640,10 +467,6 @@
640#define BM_CLKCTRL_STATUS_CPU_LIMIT 0xC0000000 467#define BM_CLKCTRL_STATUS_CPU_LIMIT 0xC0000000
641#define BF_CLKCTRL_STATUS_CPU_LIMIT(v) \ 468#define BF_CLKCTRL_STATUS_CPU_LIMIT(v) \
642 (((v) << 30) & BM_CLKCTRL_STATUS_CPU_LIMIT) 469 (((v) << 30) & BM_CLKCTRL_STATUS_CPU_LIMIT)
643#define BP_CLKCTRL_STATUS_RSRVD 0
644#define BM_CLKCTRL_STATUS_RSRVD 0x3FFFFFFF
645#define BF_CLKCTRL_STATUS_RSRVD(v) \
646 (((v) << 0) & BM_CLKCTRL_STATUS_RSRVD)
647 470
648#define HW_CLKCTRL_VERSION (0x00000200) 471#define HW_CLKCTRL_VERSION (0x00000200)
649 472
diff --git a/arch/arm/mach-mxs/system.c b/arch/arm/mach-mxs/system.c
index 9343d7edd4f6..20ec3bddf7cd 100644
--- a/arch/arm/mach-mxs/system.c
+++ b/arch/arm/mach-mxs/system.c
@@ -22,6 +22,7 @@
22#include <linux/err.h> 22#include <linux/err.h>
23#include <linux/delay.h> 23#include <linux/delay.h>
24#include <linux/init.h> 24#include <linux/init.h>
25#include <linux/module.h>
25 26
26#include <asm/proc-fns.h> 27#include <asm/proc-fns.h>
27#include <asm/system.h> 28#include <asm/system.h>
@@ -135,3 +136,4 @@ error:
135 pr_err("%s(%p): module reset timeout\n", __func__, reset_addr); 136 pr_err("%s(%p): module reset timeout\n", __func__, reset_addr);
136 return -ETIMEDOUT; 137 return -ETIMEDOUT;
137} 138}
139EXPORT_SYMBOL(mxs_reset_block);
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index 8dc2c76d2260..986c3bf4e6b8 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -26,6 +26,7 @@
26#include <asm/mach/arch.h> 26#include <asm/mach/arch.h>
27#include <asm/mach/map.h> 27#include <asm/mach/map.h>
28#include <asm/mach/time.h> 28#include <asm/mach/time.h>
29#include <mach/bridge-regs.h>
29#include <mach/hardware.h> 30#include <mach/hardware.h>
30#include <mach/orion5x.h> 31#include <mach/orion5x.h>
31#include <plat/ehci-orion.h> 32#include <plat/ehci-orion.h>
@@ -599,6 +600,11 @@ void __init orion5x_wdt_init(void)
599/***************************************************************************** 600/*****************************************************************************
600 * Time handling 601 * Time handling
601 ****************************************************************************/ 602 ****************************************************************************/
603void __init orion5x_init_early(void)
604{
605 orion_time_set_base(TIMER_VIRT_BASE);
606}
607
602int orion5x_tclk; 608int orion5x_tclk;
603 609
604int __init orion5x_find_tclk(void) 610int __init orion5x_find_tclk(void)
@@ -616,7 +622,9 @@ int __init orion5x_find_tclk(void)
616static void orion5x_timer_init(void) 622static void orion5x_timer_init(void)
617{ 623{
618 orion5x_tclk = orion5x_find_tclk(); 624 orion5x_tclk = orion5x_find_tclk();
619 orion_time_init(IRQ_ORION5X_BRIDGE, orion5x_tclk); 625
626 orion_time_init(ORION5X_BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
627 IRQ_ORION5X_BRIDGE, orion5x_tclk);
620} 628}
621 629
622struct sys_timer orion5x_timer = { 630struct sys_timer orion5x_timer = {
diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h
index 8f004503c96d..f2b2b35e8646 100644
--- a/arch/arm/mach-orion5x/common.h
+++ b/arch/arm/mach-orion5x/common.h
@@ -9,6 +9,7 @@ struct mv_sata_platform_data;
9 * Basic Orion init functions used early by machine-setup. 9 * Basic Orion init functions used early by machine-setup.
10 */ 10 */
11void orion5x_map_io(void); 11void orion5x_map_io(void);
12void orion5x_init_early(void);
12void orion5x_init_irq(void); 13void orion5x_init_irq(void);
13void orion5x_init(void); 14void orion5x_init(void);
14extern int orion5x_tclk; 15extern int orion5x_tclk;
diff --git a/arch/arm/mach-orion5x/d2net-setup.c b/arch/arm/mach-orion5x/d2net-setup.c
index b1c451f5ee27..425807579303 100644
--- a/arch/arm/mach-orion5x/d2net-setup.c
+++ b/arch/arm/mach-orion5x/d2net-setup.c
@@ -339,6 +339,7 @@ MACHINE_START(D2NET, "LaCie d2 Network")
339 .boot_params = 0x00000100, 339 .boot_params = 0x00000100,
340 .init_machine = d2net_init, 340 .init_machine = d2net_init,
341 .map_io = orion5x_map_io, 341 .map_io = orion5x_map_io,
342 .init_early = orion5x_init_early,
342 .init_irq = orion5x_init_irq, 343 .init_irq = orion5x_init_irq,
343 .timer = &orion5x_timer, 344 .timer = &orion5x_timer,
344 .fixup = tag_fixup_mem32, 345 .fixup = tag_fixup_mem32,
@@ -350,6 +351,7 @@ MACHINE_START(BIGDISK, "LaCie Big Disk Network")
350 .boot_params = 0x00000100, 351 .boot_params = 0x00000100,
351 .init_machine = d2net_init, 352 .init_machine = d2net_init,
352 .map_io = orion5x_map_io, 353 .map_io = orion5x_map_io,
354 .init_early = orion5x_init_early,
353 .init_irq = orion5x_init_irq, 355 .init_irq = orion5x_init_irq,
354 .timer = &orion5x_timer, 356 .timer = &orion5x_timer,
355 .fixup = tag_fixup_mem32, 357 .fixup = tag_fixup_mem32,
diff --git a/arch/arm/mach-orion5x/db88f5281-setup.c b/arch/arm/mach-orion5x/db88f5281-setup.c
index df1083f5b6eb..c10a11715376 100644
--- a/arch/arm/mach-orion5x/db88f5281-setup.c
+++ b/arch/arm/mach-orion5x/db88f5281-setup.c
@@ -361,6 +361,7 @@ MACHINE_START(DB88F5281, "Marvell Orion-2 Development Board")
361 .boot_params = 0x00000100, 361 .boot_params = 0x00000100,
362 .init_machine = db88f5281_init, 362 .init_machine = db88f5281_init,
363 .map_io = orion5x_map_io, 363 .map_io = orion5x_map_io,
364 .init_early = orion5x_init_early,
364 .init_irq = orion5x_init_irq, 365 .init_irq = orion5x_init_irq,
365 .timer = &orion5x_timer, 366 .timer = &orion5x_timer,
366MACHINE_END 367MACHINE_END
diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c
index 3a7bc0e36982..90ab022eabeb 100644
--- a/arch/arm/mach-orion5x/dns323-setup.c
+++ b/arch/arm/mach-orion5x/dns323-setup.c
@@ -733,6 +733,7 @@ MACHINE_START(DNS323, "D-Link DNS-323")
733 .boot_params = 0x00000100, 733 .boot_params = 0x00000100,
734 .init_machine = dns323_init, 734 .init_machine = dns323_init,
735 .map_io = orion5x_map_io, 735 .map_io = orion5x_map_io,
736 .init_early = orion5x_init_early,
736 .init_irq = orion5x_init_irq, 737 .init_irq = orion5x_init_irq,
737 .timer = &orion5x_timer, 738 .timer = &orion5x_timer,
738 .fixup = tag_fixup_mem32, 739 .fixup = tag_fixup_mem32,
diff --git a/arch/arm/mach-orion5x/edmini_v2-setup.c b/arch/arm/mach-orion5x/edmini_v2-setup.c
index ba98459f44b0..d037a90c216c 100644
--- a/arch/arm/mach-orion5x/edmini_v2-setup.c
+++ b/arch/arm/mach-orion5x/edmini_v2-setup.c
@@ -254,6 +254,7 @@ MACHINE_START(EDMINI_V2, "LaCie Ethernet Disk mini V2")
254 .boot_params = 0x00000100, 254 .boot_params = 0x00000100,
255 .init_machine = edmini_v2_init, 255 .init_machine = edmini_v2_init,
256 .map_io = orion5x_map_io, 256 .map_io = orion5x_map_io,
257 .init_early = orion5x_init_early,
257 .init_irq = orion5x_init_irq, 258 .init_irq = orion5x_init_irq,
258 .timer = &orion5x_timer, 259 .timer = &orion5x_timer,
259 .fixup = tag_fixup_mem32, 260 .fixup = tag_fixup_mem32,
diff --git a/arch/arm/mach-orion5x/include/mach/bridge-regs.h b/arch/arm/mach-orion5x/include/mach/bridge-regs.h
index 5c9744cd8ef6..96484bcd34ca 100644
--- a/arch/arm/mach-orion5x/include/mach/bridge-regs.h
+++ b/arch/arm/mach-orion5x/include/mach/bridge-regs.h
@@ -22,14 +22,12 @@
22 22
23#define CPU_SOFT_RESET (ORION5X_BRIDGE_VIRT_BASE | 0x10c) 23#define CPU_SOFT_RESET (ORION5X_BRIDGE_VIRT_BASE | 0x10c)
24 24
25#define BRIDGE_CAUSE (ORION5X_BRIDGE_VIRT_BASE | 0x110)
26
25#define POWER_MNG_CTRL_REG (ORION5X_BRIDGE_VIRT_BASE | 0x11C) 27#define POWER_MNG_CTRL_REG (ORION5X_BRIDGE_VIRT_BASE | 0x11C)
26 28
27#define BRIDGE_CAUSE (ORION5X_BRIDGE_VIRT_BASE | 0x110)
28#define WDT_INT_REQ 0x0008 29#define WDT_INT_REQ 0x0008
29 30
30#define BRIDGE_MASK (ORION5X_BRIDGE_VIRT_BASE | 0x114)
31#define BRIDGE_INT_TIMER0 0x0002
32#define BRIDGE_INT_TIMER1 0x0004
33#define BRIDGE_INT_TIMER1_CLR (~0x0004) 31#define BRIDGE_INT_TIMER1_CLR (~0x0004)
34 32
35#define MAIN_IRQ_CAUSE (ORION5X_BRIDGE_VIRT_BASE | 0x200) 33#define MAIN_IRQ_CAUSE (ORION5X_BRIDGE_VIRT_BASE | 0x200)
diff --git a/arch/arm/mach-orion5x/include/mach/gpio.h b/arch/arm/mach-orion5x/include/mach/gpio.h
index d8182e87ac16..a1d0b78decb1 100644
--- a/arch/arm/mach-orion5x/include/mach/gpio.h
+++ b/arch/arm/mach-orion5x/include/mach/gpio.h
@@ -6,32 +6,4 @@
6 * warranty of any kind, whether express or implied. 6 * warranty of any kind, whether express or implied.
7 */ 7 */
8 8
9#ifndef __ASM_ARCH_GPIO_H
10#define __ASM_ARCH_GPIO_H
11
12#include <mach/irqs.h>
13#include <plat/gpio.h> 9#include <plat/gpio.h>
14#include <asm-generic/gpio.h> /* cansleep wrappers */
15
16#define GPIO_MAX 32
17#define GPIO_OUT(pin) ORION5X_DEV_BUS_REG(0x100)
18#define GPIO_IO_CONF(pin) ORION5X_DEV_BUS_REG(0x104)
19#define GPIO_BLINK_EN(pin) ORION5X_DEV_BUS_REG(0x108)
20#define GPIO_IN_POL(pin) ORION5X_DEV_BUS_REG(0x10c)
21#define GPIO_DATA_IN(pin) ORION5X_DEV_BUS_REG(0x110)
22#define GPIO_EDGE_CAUSE(pin) ORION5X_DEV_BUS_REG(0x114)
23#define GPIO_EDGE_MASK(pin) ORION5X_DEV_BUS_REG(0x118)
24#define GPIO_LEVEL_MASK(pin) ORION5X_DEV_BUS_REG(0x11c)
25
26static inline int gpio_to_irq(int pin)
27{
28 return pin + IRQ_ORION5X_GPIO_START;
29}
30
31static inline int irq_to_gpio(int irq)
32{
33 return irq - IRQ_ORION5X_GPIO_START;
34}
35
36
37#endif
diff --git a/arch/arm/mach-orion5x/include/mach/orion5x.h b/arch/arm/mach-orion5x/include/mach/orion5x.h
index 2d8766570531..0a28bbc76891 100644
--- a/arch/arm/mach-orion5x/include/mach/orion5x.h
+++ b/arch/arm/mach-orion5x/include/mach/orion5x.h
@@ -73,6 +73,7 @@
73#define ORION5X_DEV_BUS_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x10000) 73#define ORION5X_DEV_BUS_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x10000)
74#define ORION5X_DEV_BUS_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x10000) 74#define ORION5X_DEV_BUS_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x10000)
75#define ORION5X_DEV_BUS_REG(x) (ORION5X_DEV_BUS_VIRT_BASE | (x)) 75#define ORION5X_DEV_BUS_REG(x) (ORION5X_DEV_BUS_VIRT_BASE | (x))
76#define GPIO_VIRT_BASE ORION5X_DEV_BUS_REG(0x0100)
76#define SPI_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x0600) 77#define SPI_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x0600)
77#define I2C_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x1000) 78#define I2C_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x1000)
78#define UART0_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x2000) 79#define UART0_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x2000)
diff --git a/arch/arm/mach-orion5x/irq.c b/arch/arm/mach-orion5x/irq.c
index d7512b925a85..ed85891f8699 100644
--- a/arch/arm/mach-orion5x/irq.c
+++ b/arch/arm/mach-orion5x/irq.c
@@ -28,27 +28,12 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
28 28
29void __init orion5x_init_irq(void) 29void __init orion5x_init_irq(void)
30{ 30{
31 int i;
32
33 orion_irq_init(0, (void __iomem *)MAIN_IRQ_MASK); 31 orion_irq_init(0, (void __iomem *)MAIN_IRQ_MASK);
34 32
35 /* 33 /*
36 * Mask and clear GPIO IRQ interrupts 34 * Initialize gpiolib for GPIOs 0-31.
37 */
38 writel(0x0, GPIO_LEVEL_MASK(0));
39 writel(0x0, GPIO_EDGE_MASK(0));
40 writel(0x0, GPIO_EDGE_CAUSE(0));
41
42 /*
43 * Register chained level handlers for GPIO IRQs by default.
44 * User can use set_type() if he wants to use edge types handlers.
45 */ 35 */
46 for (i = IRQ_ORION5X_GPIO_START; i < NR_IRQS; i++) { 36 orion_gpio_init(0, 32, GPIO_VIRT_BASE, 0, IRQ_ORION5X_GPIO_START);
47 set_irq_chip(i, &orion_gpio_irq_chip);
48 set_irq_handler(i, handle_level_irq);
49 irq_desc[i].status |= IRQ_LEVEL;
50 set_irq_flags(i, IRQF_VALID);
51 }
52 set_irq_chained_handler(IRQ_ORION5X_GPIO_0_7, gpio_irq_handler); 37 set_irq_chained_handler(IRQ_ORION5X_GPIO_0_7, gpio_irq_handler);
53 set_irq_chained_handler(IRQ_ORION5X_GPIO_8_15, gpio_irq_handler); 38 set_irq_chained_handler(IRQ_ORION5X_GPIO_8_15, gpio_irq_handler);
54 set_irq_chained_handler(IRQ_ORION5X_GPIO_16_23, gpio_irq_handler); 39 set_irq_chained_handler(IRQ_ORION5X_GPIO_16_23, gpio_irq_handler);
diff --git a/arch/arm/mach-orion5x/kurobox_pro-setup.c b/arch/arm/mach-orion5x/kurobox_pro-setup.c
index 4be9aa08de69..47497c76162a 100644
--- a/arch/arm/mach-orion5x/kurobox_pro-setup.c
+++ b/arch/arm/mach-orion5x/kurobox_pro-setup.c
@@ -382,6 +382,7 @@ MACHINE_START(KUROBOX_PRO, "Buffalo/Revogear Kurobox Pro")
382 .boot_params = 0x00000100, 382 .boot_params = 0x00000100,
383 .init_machine = kurobox_pro_init, 383 .init_machine = kurobox_pro_init,
384 .map_io = orion5x_map_io, 384 .map_io = orion5x_map_io,
385 .init_early = orion5x_init_early,
385 .init_irq = orion5x_init_irq, 386 .init_irq = orion5x_init_irq,
386 .timer = &orion5x_timer, 387 .timer = &orion5x_timer,
387 .fixup = tag_fixup_mem32, 388 .fixup = tag_fixup_mem32,
@@ -394,6 +395,7 @@ MACHINE_START(LINKSTATION_PRO, "Buffalo Linkstation Pro/Live")
394 .boot_params = 0x00000100, 395 .boot_params = 0x00000100,
395 .init_machine = kurobox_pro_init, 396 .init_machine = kurobox_pro_init,
396 .map_io = orion5x_map_io, 397 .map_io = orion5x_map_io,
398 .init_early = orion5x_init_early,
397 .init_irq = orion5x_init_irq, 399 .init_irq = orion5x_init_irq,
398 .timer = &orion5x_timer, 400 .timer = &orion5x_timer,
399 .fixup = tag_fixup_mem32, 401 .fixup = tag_fixup_mem32,
diff --git a/arch/arm/mach-orion5x/ls-chl-setup.c b/arch/arm/mach-orion5x/ls-chl-setup.c
index 20a9b66cbafa..6ae12aa6d759 100644
--- a/arch/arm/mach-orion5x/ls-chl-setup.c
+++ b/arch/arm/mach-orion5x/ls-chl-setup.c
@@ -321,6 +321,7 @@ MACHINE_START(LINKSTATION_LSCHL, "Buffalo Linkstation LiveV3 (LS-CHL)")
321 .boot_params = 0x00000100, 321 .boot_params = 0x00000100,
322 .init_machine = lschl_init, 322 .init_machine = lschl_init,
323 .map_io = orion5x_map_io, 323 .map_io = orion5x_map_io,
324 .init_early = orion5x_init_early,
324 .init_irq = orion5x_init_irq, 325 .init_irq = orion5x_init_irq,
325 .timer = &orion5x_timer, 326 .timer = &orion5x_timer,
326 .fixup = tag_fixup_mem32, 327 .fixup = tag_fixup_mem32,
diff --git a/arch/arm/mach-orion5x/ls_hgl-setup.c b/arch/arm/mach-orion5x/ls_hgl-setup.c
index 437364b7168e..7adafd79cf98 100644
--- a/arch/arm/mach-orion5x/ls_hgl-setup.c
+++ b/arch/arm/mach-orion5x/ls_hgl-setup.c
@@ -268,6 +268,7 @@ MACHINE_START(LINKSTATION_LS_HGL, "Buffalo Linkstation LS-HGL")
268 .boot_params = 0x00000100, 268 .boot_params = 0x00000100,
269 .init_machine = ls_hgl_init, 269 .init_machine = ls_hgl_init,
270 .map_io = orion5x_map_io, 270 .map_io = orion5x_map_io,
271 .init_early = orion5x_init_early,
271 .init_irq = orion5x_init_irq, 272 .init_irq = orion5x_init_irq,
272 .timer = &orion5x_timer, 273 .timer = &orion5x_timer,
273 .fixup = tag_fixup_mem32, 274 .fixup = tag_fixup_mem32,
diff --git a/arch/arm/mach-orion5x/lsmini-setup.c b/arch/arm/mach-orion5x/lsmini-setup.c
index ab9b0cf0a90b..869958f5c394 100644
--- a/arch/arm/mach-orion5x/lsmini-setup.c
+++ b/arch/arm/mach-orion5x/lsmini-setup.c
@@ -270,6 +270,7 @@ MACHINE_START(LINKSTATION_MINI, "Buffalo Linkstation Mini")
270 .boot_params = 0x00000100, 270 .boot_params = 0x00000100,
271 .init_machine = lsmini_init, 271 .init_machine = lsmini_init,
272 .map_io = orion5x_map_io, 272 .map_io = orion5x_map_io,
273 .init_early = orion5x_init_early,
273 .init_irq = orion5x_init_irq, 274 .init_irq = orion5x_init_irq,
274 .timer = &orion5x_timer, 275 .timer = &orion5x_timer,
275 .fixup = tag_fixup_mem32, 276 .fixup = tag_fixup_mem32,
diff --git a/arch/arm/mach-orion5x/mpp.c b/arch/arm/mach-orion5x/mpp.c
index db485d3b8144..2288207726e4 100644
--- a/arch/arm/mach-orion5x/mpp.c
+++ b/arch/arm/mach-orion5x/mpp.c
@@ -124,9 +124,6 @@ void __init orion5x_mpp_conf(struct orion5x_mpp_mode *mode)
124 u32 mpp_8_15_ctrl = readl(MPP_8_15_CTRL); 124 u32 mpp_8_15_ctrl = readl(MPP_8_15_CTRL);
125 u32 mpp_16_19_ctrl = readl(MPP_16_19_CTRL); 125 u32 mpp_16_19_ctrl = readl(MPP_16_19_CTRL);
126 126
127 /* Initialize gpiolib. */
128 orion_gpio_init();
129
130 for ( ; mode->mpp >= 0; mode++) { 127 for ( ; mode->mpp >= 0; mode++) {
131 u32 *reg; 128 u32 *reg;
132 int num_type; 129 int num_type;
diff --git a/arch/arm/mach-orion5x/mss2-setup.c b/arch/arm/mach-orion5x/mss2-setup.c
index 2f0e16cd7e81..b43b208153cb 100644
--- a/arch/arm/mach-orion5x/mss2-setup.c
+++ b/arch/arm/mach-orion5x/mss2-setup.c
@@ -264,6 +264,7 @@ MACHINE_START(MSS2, "Maxtor Shared Storage II")
264 .boot_params = 0x00000100, 264 .boot_params = 0x00000100,
265 .init_machine = mss2_init, 265 .init_machine = mss2_init,
266 .map_io = orion5x_map_io, 266 .map_io = orion5x_map_io,
267 .init_early = orion5x_init_early,
267 .init_irq = orion5x_init_irq, 268 .init_irq = orion5x_init_irq,
268 .timer = &orion5x_timer, 269 .timer = &orion5x_timer,
269 .fixup = tag_fixup_mem32 270 .fixup = tag_fixup_mem32
diff --git a/arch/arm/mach-orion5x/mv2120-setup.c b/arch/arm/mach-orion5x/mv2120-setup.c
index b3d90f25de9f..c55d071707f5 100644
--- a/arch/arm/mach-orion5x/mv2120-setup.c
+++ b/arch/arm/mach-orion5x/mv2120-setup.c
@@ -232,6 +232,7 @@ MACHINE_START(MV2120, "HP Media Vault mv2120")
232 .boot_params = 0x00000100, 232 .boot_params = 0x00000100,
233 .init_machine = mv2120_init, 233 .init_machine = mv2120_init,
234 .map_io = orion5x_map_io, 234 .map_io = orion5x_map_io,
235 .init_early = orion5x_init_early,
235 .init_irq = orion5x_init_irq, 236 .init_irq = orion5x_init_irq,
236 .timer = &orion5x_timer, 237 .timer = &orion5x_timer,
237 .fixup = tag_fixup_mem32 238 .fixup = tag_fixup_mem32
diff --git a/arch/arm/mach-orion5x/net2big-setup.c b/arch/arm/mach-orion5x/net2big-setup.c
index d6665b31665f..429ecafe9fdd 100644
--- a/arch/arm/mach-orion5x/net2big-setup.c
+++ b/arch/arm/mach-orion5x/net2big-setup.c
@@ -422,6 +422,7 @@ MACHINE_START(NET2BIG, "LaCie 2Big Network")
422 .boot_params = 0x00000100, 422 .boot_params = 0x00000100,
423 .init_machine = net2big_init, 423 .init_machine = net2big_init,
424 .map_io = orion5x_map_io, 424 .map_io = orion5x_map_io,
425 .init_early = orion5x_init_early,
425 .init_irq = orion5x_init_irq, 426 .init_irq = orion5x_init_irq,
426 .timer = &orion5x_timer, 427 .timer = &orion5x_timer,
427 .fixup = tag_fixup_mem32, 428 .fixup = tag_fixup_mem32,
diff --git a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
index f4c26fd731f4..34310ab56e29 100644
--- a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
@@ -172,6 +172,7 @@ MACHINE_START(RD88F5181L_FXO, "Marvell Orion-VoIP FXO Reference Design")
172 .boot_params = 0x00000100, 172 .boot_params = 0x00000100,
173 .init_machine = rd88f5181l_fxo_init, 173 .init_machine = rd88f5181l_fxo_init,
174 .map_io = orion5x_map_io, 174 .map_io = orion5x_map_io,
175 .init_early = orion5x_init_early,
175 .init_irq = orion5x_init_irq, 176 .init_irq = orion5x_init_irq,
176 .timer = &orion5x_timer, 177 .timer = &orion5x_timer,
177 .fixup = tag_fixup_mem32, 178 .fixup = tag_fixup_mem32,
diff --git a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
index b5942909bab0..c1f79fa014ed 100644
--- a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
@@ -184,6 +184,7 @@ MACHINE_START(RD88F5181L_GE, "Marvell Orion-VoIP GE Reference Design")
184 .boot_params = 0x00000100, 184 .boot_params = 0x00000100,
185 .init_machine = rd88f5181l_ge_init, 185 .init_machine = rd88f5181l_ge_init,
186 .map_io = orion5x_map_io, 186 .map_io = orion5x_map_io,
187 .init_early = orion5x_init_early,
187 .init_irq = orion5x_init_irq, 188 .init_irq = orion5x_init_irq,
188 .timer = &orion5x_timer, 189 .timer = &orion5x_timer,
189 .fixup = tag_fixup_mem32, 190 .fixup = tag_fixup_mem32,
diff --git a/arch/arm/mach-orion5x/rd88f5182-setup.c b/arch/arm/mach-orion5x/rd88f5182-setup.c
index 165ed87029b2..67ec6959b267 100644
--- a/arch/arm/mach-orion5x/rd88f5182-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5182-setup.c
@@ -308,6 +308,7 @@ MACHINE_START(RD88F5182, "Marvell Orion-NAS Reference Design")
308 .boot_params = 0x00000100, 308 .boot_params = 0x00000100,
309 .init_machine = rd88f5182_init, 309 .init_machine = rd88f5182_init,
310 .map_io = orion5x_map_io, 310 .map_io = orion5x_map_io,
311 .init_early = orion5x_init_early,
311 .init_irq = orion5x_init_irq, 312 .init_irq = orion5x_init_irq,
312 .timer = &orion5x_timer, 313 .timer = &orion5x_timer,
313MACHINE_END 314MACHINE_END
diff --git a/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c b/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
index 02ff45f3e2e3..b080c6966d10 100644
--- a/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
+++ b/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
@@ -126,6 +126,7 @@ MACHINE_START(RD88F6183AP_GE, "Marvell Orion-1-90 AP GE Reference Design")
126 .boot_params = 0x00000100, 126 .boot_params = 0x00000100,
127 .init_machine = rd88f6183ap_ge_init, 127 .init_machine = rd88f6183ap_ge_init,
128 .map_io = orion5x_map_io, 128 .map_io = orion5x_map_io,
129 .init_early = orion5x_init_early,
129 .init_irq = orion5x_init_irq, 130 .init_irq = orion5x_init_irq,
130 .timer = &orion5x_timer, 131 .timer = &orion5x_timer,
131 .fixup = tag_fixup_mem32, 132 .fixup = tag_fixup_mem32,
diff --git a/arch/arm/mach-orion5x/terastation_pro2-setup.c b/arch/arm/mach-orion5x/terastation_pro2-setup.c
index 4403fae5ab0e..5653ee6c71d8 100644
--- a/arch/arm/mach-orion5x/terastation_pro2-setup.c
+++ b/arch/arm/mach-orion5x/terastation_pro2-setup.c
@@ -361,6 +361,7 @@ MACHINE_START(TERASTATION_PRO2, "Buffalo Terastation Pro II/Live")
361 .boot_params = 0x00000100, 361 .boot_params = 0x00000100,
362 .init_machine = tsp2_init, 362 .init_machine = tsp2_init,
363 .map_io = orion5x_map_io, 363 .map_io = orion5x_map_io,
364 .init_early = orion5x_init_early,
364 .init_irq = orion5x_init_irq, 365 .init_irq = orion5x_init_irq,
365 .timer = &orion5x_timer, 366 .timer = &orion5x_timer,
366 .fixup = tag_fixup_mem32, 367 .fixup = tag_fixup_mem32,
diff --git a/arch/arm/mach-orion5x/ts209-setup.c b/arch/arm/mach-orion5x/ts209-setup.c
index 1e196129d763..8bbd27ea6735 100644
--- a/arch/arm/mach-orion5x/ts209-setup.c
+++ b/arch/arm/mach-orion5x/ts209-setup.c
@@ -325,6 +325,7 @@ MACHINE_START(TS209, "QNAP TS-109/TS-209")
325 .boot_params = 0x00000100, 325 .boot_params = 0x00000100,
326 .init_machine = qnap_ts209_init, 326 .init_machine = qnap_ts209_init,
327 .map_io = orion5x_map_io, 327 .map_io = orion5x_map_io,
328 .init_early = orion5x_init_early,
328 .init_irq = orion5x_init_irq, 329 .init_irq = orion5x_init_irq,
329 .timer = &orion5x_timer, 330 .timer = &orion5x_timer,
330 .fixup = tag_fixup_mem32, 331 .fixup = tag_fixup_mem32,
diff --git a/arch/arm/mach-orion5x/ts409-setup.c b/arch/arm/mach-orion5x/ts409-setup.c
index 428af2046e36..92f393f08fa4 100644
--- a/arch/arm/mach-orion5x/ts409-setup.c
+++ b/arch/arm/mach-orion5x/ts409-setup.c
@@ -314,6 +314,7 @@ MACHINE_START(TS409, "QNAP TS-409")
314 .boot_params = 0x00000100, 314 .boot_params = 0x00000100,
315 .init_machine = qnap_ts409_init, 315 .init_machine = qnap_ts409_init,
316 .map_io = orion5x_map_io, 316 .map_io = orion5x_map_io,
317 .init_early = orion5x_init_early,
317 .init_irq = orion5x_init_irq, 318 .init_irq = orion5x_init_irq,
318 .timer = &orion5x_timer, 319 .timer = &orion5x_timer,
319 .fixup = tag_fixup_mem32, 320 .fixup = tag_fixup_mem32,
diff --git a/arch/arm/mach-orion5x/ts78xx-fpga.h b/arch/arm/mach-orion5x/ts78xx-fpga.h
index 37b3d4875291..151e89e1e676 100644
--- a/arch/arm/mach-orion5x/ts78xx-fpga.h
+++ b/arch/arm/mach-orion5x/ts78xx-fpga.h
@@ -1,3 +1,4 @@
1#define TS7800_FPGA_MAGIC 0x00b480
1#define FPGAID(_magic, _rev) ((_magic << 8) + _rev) 2#define FPGAID(_magic, _rev) ((_magic << 8) + _rev)
2 3
3/* 4/*
@@ -6,11 +7,15 @@
6 */ 7 */
7enum fpga_ids { 8enum fpga_ids {
8 /* Technologic Systems */ 9 /* Technologic Systems */
9 TS7800_REV_1 = FPGAID(0x00b480, 0x01), 10 TS7800_REV_1 = FPGAID(TS7800_FPGA_MAGIC, 0x01),
10 TS7800_REV_2 = FPGAID(0x00b480, 0x02), 11 TS7800_REV_2 = FPGAID(TS7800_FPGA_MAGIC, 0x02),
11 TS7800_REV_3 = FPGAID(0x00b480, 0x03), 12 TS7800_REV_3 = FPGAID(TS7800_FPGA_MAGIC, 0x03),
12 TS7800_REV_4 = FPGAID(0x00b480, 0x04), 13 TS7800_REV_4 = FPGAID(TS7800_FPGA_MAGIC, 0x04),
13 TS7800_REV_5 = FPGAID(0x00b480, 0x05), 14 TS7800_REV_5 = FPGAID(TS7800_FPGA_MAGIC, 0x05),
15 TS7800_REV_6 = FPGAID(TS7800_FPGA_MAGIC, 0x06),
16 TS7800_REV_7 = FPGAID(TS7800_FPGA_MAGIC, 0x07),
17 TS7800_REV_8 = FPGAID(TS7800_FPGA_MAGIC, 0x08),
18 TS7800_REV_9 = FPGAID(TS7800_FPGA_MAGIC, 0x09),
14 19
15 /* Unaffordable & Expensive */ 20 /* Unaffordable & Expensive */
16 UAE_DUMMY = FPGAID(0xffffff, 0x01), 21 UAE_DUMMY = FPGAID(0xffffff, 0x01),
diff --git a/arch/arm/mach-orion5x/ts78xx-setup.c b/arch/arm/mach-orion5x/ts78xx-setup.c
index c1c1cd04bdde..8554707d20a9 100644
--- a/arch/arm/mach-orion5x/ts78xx-setup.c
+++ b/arch/arm/mach-orion5x/ts78xx-setup.c
@@ -191,6 +191,60 @@ static int ts78xx_ts_nand_dev_ready(struct mtd_info *mtd)
191 return readb(TS_NAND_CTRL) & 0x20; 191 return readb(TS_NAND_CTRL) & 0x20;
192} 192}
193 193
194static void ts78xx_ts_nand_write_buf(struct mtd_info *mtd,
195 const uint8_t *buf, int len)
196{
197 struct nand_chip *chip = mtd->priv;
198 void __iomem *io_base = chip->IO_ADDR_W;
199 unsigned long off = ((unsigned long)buf & 3);
200 int sz;
201
202 if (off) {
203 sz = min_t(int, 4 - off, len);
204 writesb(io_base, buf, sz);
205 buf += sz;
206 len -= sz;
207 }
208
209 sz = len >> 2;
210 if (sz) {
211 u32 *buf32 = (u32 *)buf;
212 writesl(io_base, buf32, sz);
213 buf += sz << 2;
214 len -= sz << 2;
215 }
216
217 if (len)
218 writesb(io_base, buf, len);
219}
220
221static void ts78xx_ts_nand_read_buf(struct mtd_info *mtd,
222 uint8_t *buf, int len)
223{
224 struct nand_chip *chip = mtd->priv;
225 void __iomem *io_base = chip->IO_ADDR_R;
226 unsigned long off = ((unsigned long)buf & 3);
227 int sz;
228
229 if (off) {
230 sz = min_t(int, 4 - off, len);
231 readsb(io_base, buf, sz);
232 buf += sz;
233 len -= sz;
234 }
235
236 sz = len >> 2;
237 if (sz) {
238 u32 *buf32 = (u32 *)buf;
239 readsl(io_base, buf32, sz);
240 buf += sz << 2;
241 len -= sz << 2;
242 }
243
244 if (len)
245 readsb(io_base, buf, len);
246}
247
194const char *ts_nand_part_probes[] = { "cmdlinepart", NULL }; 248const char *ts_nand_part_probes[] = { "cmdlinepart", NULL };
195 249
196static struct mtd_partition ts78xx_ts_nand_parts[] = { 250static struct mtd_partition ts78xx_ts_nand_parts[] = {
@@ -233,6 +287,8 @@ static struct platform_nand_data ts78xx_ts_nand_data = {
233 */ 287 */
234 .cmd_ctrl = ts78xx_ts_nand_cmd_ctrl, 288 .cmd_ctrl = ts78xx_ts_nand_cmd_ctrl,
235 .dev_ready = ts78xx_ts_nand_dev_ready, 289 .dev_ready = ts78xx_ts_nand_dev_ready,
290 .write_buf = ts78xx_ts_nand_write_buf,
291 .read_buf = ts78xx_ts_nand_read_buf,
236 }, 292 },
237}; 293};
238 294
@@ -334,14 +390,29 @@ static void ts78xx_fpga_supports(void)
334 case TS7800_REV_3: 390 case TS7800_REV_3:
335 case TS7800_REV_4: 391 case TS7800_REV_4:
336 case TS7800_REV_5: 392 case TS7800_REV_5:
393 case TS7800_REV_6:
394 case TS7800_REV_7:
395 case TS7800_REV_8:
396 case TS7800_REV_9:
337 ts78xx_fpga.supports.ts_rtc.present = 1; 397 ts78xx_fpga.supports.ts_rtc.present = 1;
338 ts78xx_fpga.supports.ts_nand.present = 1; 398 ts78xx_fpga.supports.ts_nand.present = 1;
339 ts78xx_fpga.supports.ts_rng.present = 1; 399 ts78xx_fpga.supports.ts_rng.present = 1;
340 break; 400 break;
341 default: 401 default:
342 ts78xx_fpga.supports.ts_rtc.present = 0; 402 /* enable devices if magic matches */
343 ts78xx_fpga.supports.ts_nand.present = 0; 403 switch ((ts78xx_fpga.id >> 8) & 0xffffff) {
344 ts78xx_fpga.supports.ts_rng.present = 0; 404 case TS7800_FPGA_MAGIC:
405 printk(KERN_WARNING "TS-7800 FPGA: unrecognized revision 0x%.2x\n",
406 ts78xx_fpga.id & 0xff);
407 ts78xx_fpga.supports.ts_rtc.present = 1;
408 ts78xx_fpga.supports.ts_nand.present = 1;
409 ts78xx_fpga.supports.ts_rng.present = 1;
410 break;
411 default:
412 ts78xx_fpga.supports.ts_rtc.present = 0;
413 ts78xx_fpga.supports.ts_nand.present = 0;
414 ts78xx_fpga.supports.ts_rng.present = 0;
415 }
345 } 416 }
346} 417}
347 418
@@ -553,6 +624,7 @@ MACHINE_START(TS78XX, "Technologic Systems TS-78xx SBC")
553 .boot_params = 0x00000100, 624 .boot_params = 0x00000100,
554 .init_machine = ts78xx_init, 625 .init_machine = ts78xx_init,
555 .map_io = ts78xx_map_io, 626 .map_io = ts78xx_map_io,
627 .init_early = orion5x_init_early,
556 .init_irq = orion5x_init_irq, 628 .init_irq = orion5x_init_irq,
557 .timer = &orion5x_timer, 629 .timer = &orion5x_timer,
558MACHINE_END 630MACHINE_END
diff --git a/arch/arm/mach-orion5x/wnr854t-setup.c b/arch/arm/mach-orion5x/wnr854t-setup.c
index 7994d6ec08a8..4e5216be0745 100644
--- a/arch/arm/mach-orion5x/wnr854t-setup.c
+++ b/arch/arm/mach-orion5x/wnr854t-setup.c
@@ -175,6 +175,7 @@ MACHINE_START(WNR854T, "Netgear WNR854T")
175 .boot_params = 0x00000100, 175 .boot_params = 0x00000100,
176 .init_machine = wnr854t_init, 176 .init_machine = wnr854t_init,
177 .map_io = orion5x_map_io, 177 .map_io = orion5x_map_io,
178 .init_early = orion5x_init_early,
178 .init_irq = orion5x_init_irq, 179 .init_irq = orion5x_init_irq,
179 .timer = &orion5x_timer, 180 .timer = &orion5x_timer,
180 .fixup = tag_fixup_mem32, 181 .fixup = tag_fixup_mem32,
diff --git a/arch/arm/mach-orion5x/wrt350n-v2-setup.c b/arch/arm/mach-orion5x/wrt350n-v2-setup.c
index a5989b7eb53e..fab79d09cc5c 100644
--- a/arch/arm/mach-orion5x/wrt350n-v2-setup.c
+++ b/arch/arm/mach-orion5x/wrt350n-v2-setup.c
@@ -263,6 +263,7 @@ MACHINE_START(WRT350N_V2, "Linksys WRT350N v2")
263 .boot_params = 0x00000100, 263 .boot_params = 0x00000100,
264 .init_machine = wrt350n_v2_init, 264 .init_machine = wrt350n_v2_init,
265 .map_io = orion5x_map_io, 265 .map_io = orion5x_map_io,
266 .init_early = orion5x_init_early,
266 .init_irq = orion5x_init_irq, 267 .init_irq = orion5x_init_irq,
267 .timer = &orion5x_timer, 268 .timer = &orion5x_timer,
268 .fixup = tag_fixup_mem32, 269 .fixup = tag_fixup_mem32,
diff --git a/arch/arm/mach-s3c2440/mach-gta02.c b/arch/arm/mach-s3c2440/mach-gta02.c
index 37405d9abe32..0db2411ef4bb 100644
--- a/arch/arm/mach-s3c2440/mach-gta02.c
+++ b/arch/arm/mach-s3c2440/mach-gta02.c
@@ -58,6 +58,9 @@
58#include <linux/mfd/pcf50633/pmic.h> 58#include <linux/mfd/pcf50633/pmic.h>
59#include <linux/mfd/pcf50633/backlight.h> 59#include <linux/mfd/pcf50633/backlight.h>
60 60
61#include <linux/input.h>
62#include <linux/gpio_keys.h>
63
61#include <asm/mach/arch.h> 64#include <asm/mach/arch.h>
62#include <asm/mach/map.h> 65#include <asm/mach/map.h>
63#include <asm/mach/irq.h> 66#include <asm/mach/irq.h>
@@ -86,6 +89,8 @@
86#include <plat/udc.h> 89#include <plat/udc.h>
87#include <plat/gpio-cfg.h> 90#include <plat/gpio-cfg.h>
88#include <plat/iic.h> 91#include <plat/iic.h>
92#include <plat/ts.h>
93
89 94
90static struct pcf50633 *gta02_pcf; 95static struct pcf50633 *gta02_pcf;
91 96
@@ -280,9 +285,6 @@ struct pcf50633_platform_data gta02_pcf_pdata = {
280 .valid_modes_mask = REGULATOR_MODE_NORMAL, 285 .valid_modes_mask = REGULATOR_MODE_NORMAL,
281 .always_on = 1, 286 .always_on = 1,
282 .apply_uV = 1, 287 .apply_uV = 1,
283 .state_mem = {
284 .enabled = 1,
285 },
286 }, 288 },
287 }, 289 },
288 [PCF50633_REGULATOR_DOWN1] = { 290 [PCF50633_REGULATOR_DOWN1] = {
@@ -301,9 +303,6 @@ struct pcf50633_platform_data gta02_pcf_pdata = {
301 .valid_modes_mask = REGULATOR_MODE_NORMAL, 303 .valid_modes_mask = REGULATOR_MODE_NORMAL,
302 .apply_uV = 1, 304 .apply_uV = 1,
303 .always_on = 1, 305 .always_on = 1,
304 .state_mem = {
305 .enabled = 1,
306 },
307 }, 306 },
308 }, 307 },
309 [PCF50633_REGULATOR_HCLDO] = { 308 [PCF50633_REGULATOR_HCLDO] = {
@@ -311,8 +310,8 @@ struct pcf50633_platform_data gta02_pcf_pdata = {
311 .min_uV = 2000000, 310 .min_uV = 2000000,
312 .max_uV = 3300000, 311 .max_uV = 3300000,
313 .valid_modes_mask = REGULATOR_MODE_NORMAL, 312 .valid_modes_mask = REGULATOR_MODE_NORMAL,
314 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, 313 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
315 .always_on = 1, 314 REGULATOR_CHANGE_STATUS,
316 }, 315 },
317 }, 316 },
318 [PCF50633_REGULATOR_LDO1] = { 317 [PCF50633_REGULATOR_LDO1] = {
@@ -320,10 +319,8 @@ struct pcf50633_platform_data gta02_pcf_pdata = {
320 .min_uV = 3300000, 319 .min_uV = 3300000,
321 .max_uV = 3300000, 320 .max_uV = 3300000,
322 .valid_modes_mask = REGULATOR_MODE_NORMAL, 321 .valid_modes_mask = REGULATOR_MODE_NORMAL,
322 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
323 .apply_uV = 1, 323 .apply_uV = 1,
324 .state_mem = {
325 .enabled = 0,
326 },
327 }, 324 },
328 }, 325 },
329 [PCF50633_REGULATOR_LDO2] = { 326 [PCF50633_REGULATOR_LDO2] = {
@@ -347,6 +344,7 @@ struct pcf50633_platform_data gta02_pcf_pdata = {
347 .min_uV = 3200000, 344 .min_uV = 3200000,
348 .max_uV = 3200000, 345 .max_uV = 3200000,
349 .valid_modes_mask = REGULATOR_MODE_NORMAL, 346 .valid_modes_mask = REGULATOR_MODE_NORMAL,
347 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
350 .apply_uV = 1, 348 .apply_uV = 1,
351 }, 349 },
352 }, 350 },
@@ -355,10 +353,8 @@ struct pcf50633_platform_data gta02_pcf_pdata = {
355 .min_uV = 3000000, 353 .min_uV = 3000000,
356 .max_uV = 3000000, 354 .max_uV = 3000000,
357 .valid_modes_mask = REGULATOR_MODE_NORMAL, 355 .valid_modes_mask = REGULATOR_MODE_NORMAL,
356 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
358 .apply_uV = 1, 357 .apply_uV = 1,
359 .state_mem = {
360 .enabled = 1,
361 },
362 }, 358 },
363 }, 359 },
364 [PCF50633_REGULATOR_LDO6] = { 360 [PCF50633_REGULATOR_LDO6] = {
@@ -373,9 +369,6 @@ struct pcf50633_platform_data gta02_pcf_pdata = {
373 .min_uV = 1800000, 369 .min_uV = 1800000,
374 .max_uV = 1800000, 370 .max_uV = 1800000,
375 .valid_modes_mask = REGULATOR_MODE_NORMAL, 371 .valid_modes_mask = REGULATOR_MODE_NORMAL,
376 .state_mem = {
377 .enabled = 1,
378 },
379 }, 372 },
380 }, 373 },
381 374
@@ -471,6 +464,43 @@ static struct s3c2410_hcd_info gta02_usb_info __initdata = {
471 }, 464 },
472}; 465};
473 466
467/* Touchscreen */
468static struct s3c2410_ts_mach_info gta02_ts_info = {
469 .delay = 10000,
470 .presc = 0xff, /* slow as we can go */
471 .oversampling_shift = 2,
472};
473
474/* Buttons */
475static struct gpio_keys_button gta02_buttons[] = {
476 {
477 .gpio = GTA02_GPIO_AUX_KEY,
478 .code = KEY_PHONE,
479 .desc = "Aux",
480 .type = EV_KEY,
481 .debounce_interval = 100,
482 },
483 {
484 .gpio = GTA02_GPIO_HOLD_KEY,
485 .code = KEY_PAUSE,
486 .desc = "Hold",
487 .type = EV_KEY,
488 .debounce_interval = 100,
489 },
490};
491
492static struct gpio_keys_platform_data gta02_buttons_pdata = {
493 .buttons = gta02_buttons,
494 .nbuttons = ARRAY_SIZE(gta02_buttons),
495};
496
497static struct platform_device gta02_buttons_device = {
498 .name = "gpio-keys",
499 .id = -1,
500 .dev = {
501 .platform_data = &gta02_buttons_pdata,
502 },
503};
474 504
475static void __init gta02_map_io(void) 505static void __init gta02_map_io(void)
476{ 506{
@@ -491,7 +521,11 @@ static struct platform_device *gta02_devices[] __initdata = {
491 &gta02_nor_flash, 521 &gta02_nor_flash,
492 &s3c24xx_pwm_device, 522 &s3c24xx_pwm_device,
493 &s3c_device_iis, 523 &s3c_device_iis,
524 &samsung_asoc_dma,
494 &s3c_device_i2c0, 525 &s3c_device_i2c0,
526 &gta02_buttons_device,
527 &s3c_device_adc,
528 &s3c_device_ts,
495}; 529};
496 530
497/* These guys DO need to be children of PMU. */ 531/* These guys DO need to be children of PMU. */
@@ -541,6 +575,7 @@ static void __init gta02_machine_init(void)
541#endif 575#endif
542 576
543 s3c24xx_udc_set_platdata(&gta02_udc_cfg); 577 s3c24xx_udc_set_platdata(&gta02_udc_cfg);
578 s3c24xx_ts_set_platdata(&gta02_ts_info);
544 s3c_ohci_set_platdata(&gta02_usb_info); 579 s3c_ohci_set_platdata(&gta02_usb_info);
545 s3c_nand_set_platdata(&gta02_nand_info); 580 s3c_nand_set_platdata(&gta02_nand_info);
546 s3c_i2c0_set_platdata(NULL); 581 s3c_i2c0_set_platdata(NULL);
@@ -549,6 +584,8 @@ static void __init gta02_machine_init(void)
549 584
550 platform_add_devices(gta02_devices, ARRAY_SIZE(gta02_devices)); 585 platform_add_devices(gta02_devices, ARRAY_SIZE(gta02_devices));
551 pm_power_off = gta02_poweroff; 586 pm_power_off = gta02_poweroff;
587
588 regulator_has_full_constraints();
552} 589}
553 590
554 591
diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig
index 579d2f0f4dd0..e4177e22557b 100644
--- a/arch/arm/mach-s3c64xx/Kconfig
+++ b/arch/arm/mach-s3c64xx/Kconfig
@@ -143,6 +143,7 @@ config MACH_SMDK6410
143 select S3C_DEV_USB_HSOTG 143 select S3C_DEV_USB_HSOTG
144 select S3C_DEV_WDT 144 select S3C_DEV_WDT
145 select SAMSUNG_DEV_KEYPAD 145 select SAMSUNG_DEV_KEYPAD
146 select SAMSUNG_DEV_PWM
146 select HAVE_S3C2410_WATCHDOG if WATCHDOG 147 select HAVE_S3C2410_WATCHDOG if WATCHDOG
147 select S3C64XX_SETUP_SDHCI 148 select S3C64XX_SETUP_SDHCI
148 select S3C64XX_SETUP_I2C1 149 select S3C64XX_SETUP_I2C1
@@ -231,7 +232,7 @@ config MACH_HMT
231 select S3C_DEV_NAND 232 select S3C_DEV_NAND
232 select S3C_DEV_USB_HOST 233 select S3C_DEV_USB_HOST
233 select S3C64XX_SETUP_FB_24BPP 234 select S3C64XX_SETUP_FB_24BPP
234 select HAVE_PWM 235 select SAMSUNG_DEV_PWM
235 help 236 help
236 Machine support for the Airgoo HMT 237 Machine support for the Airgoo HMT
237 238
@@ -249,8 +250,8 @@ config MACH_SMARTQ
249 select S3C64XX_SETUP_SDHCI 250 select S3C64XX_SETUP_SDHCI
250 select S3C64XX_SETUP_FB_24BPP 251 select S3C64XX_SETUP_FB_24BPP
251 select SAMSUNG_DEV_ADC 252 select SAMSUNG_DEV_ADC
253 select SAMSUNG_DEV_PWM
252 select SAMSUNG_DEV_TS 254 select SAMSUNG_DEV_TS
253 select HAVE_PWM
254 help 255 help
255 Shared machine support for SmartQ 5/7 256 Shared machine support for SmartQ 5/7
256 257
diff --git a/arch/arm/mach-s3c64xx/cpufreq.c b/arch/arm/mach-s3c64xx/cpufreq.c
index 74c0e8347de5..4375b97588b8 100644
--- a/arch/arm/mach-s3c64xx/cpufreq.c
+++ b/arch/arm/mach-s3c64xx/cpufreq.c
@@ -181,7 +181,7 @@ static void __init s3c64xx_cpufreq_config_regulator(void)
181} 181}
182#endif 182#endif
183 183
184static int __init s3c64xx_cpufreq_driver_init(struct cpufreq_policy *policy) 184static int s3c64xx_cpufreq_driver_init(struct cpufreq_policy *policy)
185{ 185{
186 int ret; 186 int ret;
187 struct cpufreq_frequency_table *freq; 187 struct cpufreq_frequency_table *freq;
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c
index a80a3163dd30..686a4f270b12 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
@@ -29,6 +29,7 @@
29#include <linux/smsc911x.h> 29#include <linux/smsc911x.h>
30#include <linux/regulator/fixed.h> 30#include <linux/regulator/fixed.h>
31#include <linux/regulator/machine.h> 31#include <linux/regulator/machine.h>
32#include <linux/pwm_backlight.h>
32 33
33#ifdef CONFIG_SMDK6410_WM1190_EV1 34#ifdef CONFIG_SMDK6410_WM1190_EV1
34#include <linux/mfd/wm8350/core.h> 35#include <linux/mfd/wm8350/core.h>
@@ -49,6 +50,7 @@
49#include <mach/hardware.h> 50#include <mach/hardware.h>
50#include <mach/regs-fb.h> 51#include <mach/regs-fb.h>
51#include <mach/map.h> 52#include <mach/map.h>
53#include <mach/gpio-bank-f.h>
52 54
53#include <asm/irq.h> 55#include <asm/irq.h>
54#include <asm/mach-types.h> 56#include <asm/mach-types.h>
@@ -119,7 +121,6 @@ static void smdk6410_lcd_power_set(struct plat_lcd_data *pd,
119{ 121{
120 if (power) { 122 if (power) {
121 gpio_direction_output(S3C64XX_GPF(13), 1); 123 gpio_direction_output(S3C64XX_GPF(13), 1);
122 gpio_direction_output(S3C64XX_GPF(15), 1);
123 124
124 /* fire nRESET on power up */ 125 /* fire nRESET on power up */
125 gpio_direction_output(S3C64XX_GPN(5), 0); 126 gpio_direction_output(S3C64XX_GPN(5), 0);
@@ -127,7 +128,6 @@ static void smdk6410_lcd_power_set(struct plat_lcd_data *pd,
127 gpio_direction_output(S3C64XX_GPN(5), 1); 128 gpio_direction_output(S3C64XX_GPN(5), 1);
128 msleep(1); 129 msleep(1);
129 } else { 130 } else {
130 gpio_direction_output(S3C64XX_GPF(15), 0);
131 gpio_direction_output(S3C64XX_GPF(13), 0); 131 gpio_direction_output(S3C64XX_GPF(13), 0);
132 } 132 }
133} 133}
@@ -270,6 +270,45 @@ static struct samsung_keypad_platdata smdk6410_keypad_data __initdata = {
270 .cols = 8, 270 .cols = 8,
271}; 271};
272 272
273static int smdk6410_backlight_init(struct device *dev)
274{
275 int ret;
276
277 ret = gpio_request(S3C64XX_GPF(15), "Backlight");
278 if (ret) {
279 printk(KERN_ERR "failed to request GPF for PWM-OUT1\n");
280 return ret;
281 }
282
283 /* Configure GPIO pin with S3C64XX_GPF15_PWM_TOUT1 */
284 s3c_gpio_cfgpin(S3C64XX_GPF(15), S3C_GPIO_SFN(2));
285
286 return 0;
287}
288
289static void smdk6410_backlight_exit(struct device *dev)
290{
291 s3c_gpio_cfgpin(S3C64XX_GPF(15), S3C_GPIO_OUTPUT);
292 gpio_free(S3C64XX_GPF(15));
293}
294
295static struct platform_pwm_backlight_data smdk6410_backlight_data = {
296 .pwm_id = 1,
297 .max_brightness = 255,
298 .dft_brightness = 255,
299 .pwm_period_ns = 78770,
300 .init = smdk6410_backlight_init,
301 .exit = smdk6410_backlight_exit,
302};
303
304static struct platform_device smdk6410_backlight_device = {
305 .name = "pwm-backlight",
306 .dev = {
307 .parent = &s3c_device_timer[1].dev,
308 .platform_data = &smdk6410_backlight_data,
309 },
310};
311
273static struct map_desc smdk6410_iodesc[] = {}; 312static struct map_desc smdk6410_iodesc[] = {};
274 313
275static struct platform_device *smdk6410_devices[] __initdata = { 314static struct platform_device *smdk6410_devices[] __initdata = {
@@ -299,6 +338,8 @@ static struct platform_device *smdk6410_devices[] __initdata = {
299 &s3c_device_rtc, 338 &s3c_device_rtc,
300 &s3c_device_ts, 339 &s3c_device_ts,
301 &s3c_device_wdt, 340 &s3c_device_wdt,
341 &s3c_device_timer[1],
342 &smdk6410_backlight_device,
302}; 343};
303 344
304#ifdef CONFIG_REGULATOR 345#ifdef CONFIG_REGULATOR
@@ -694,7 +735,6 @@ static void __init smdk6410_machine_init(void)
694 735
695 gpio_request(S3C64XX_GPN(5), "LCD power"); 736 gpio_request(S3C64XX_GPN(5), "LCD power");
696 gpio_request(S3C64XX_GPF(13), "LCD power"); 737 gpio_request(S3C64XX_GPF(13), "LCD power");
697 gpio_request(S3C64XX_GPF(15), "LCD power");
698 738
699 i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0)); 739 i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
700 i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1)); 740 i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
diff --git a/arch/arm/mach-s5p64x0/Kconfig b/arch/arm/mach-s5p64x0/Kconfig
index 164d2783d381..017af4c4293c 100644
--- a/arch/arm/mach-s5p64x0/Kconfig
+++ b/arch/arm/mach-s5p64x0/Kconfig
@@ -10,12 +10,14 @@ if ARCH_S5P64X0
10config CPU_S5P6440 10config CPU_S5P6440
11 bool 11 bool
12 select S3C_PL330_DMA 12 select S3C_PL330_DMA
13 select S5P_HRT
13 help 14 help
14 Enable S5P6440 CPU support 15 Enable S5P6440 CPU support
15 16
16config CPU_S5P6450 17config CPU_S5P6450
17 bool 18 bool
18 select S3C_PL330_DMA 19 select S3C_PL330_DMA
20 select S5P_HRT
19 help 21 help
20 Enable S5P6450 CPU support 22 Enable S5P6450 CPU support
21 23
@@ -34,6 +36,7 @@ config MACH_SMDK6440
34 select S3C_DEV_WDT 36 select S3C_DEV_WDT
35 select S3C64XX_DEV_SPI 37 select S3C64XX_DEV_SPI
36 select SAMSUNG_DEV_ADC 38 select SAMSUNG_DEV_ADC
39 select SAMSUNG_DEV_PWM
37 select SAMSUNG_DEV_TS 40 select SAMSUNG_DEV_TS
38 select S5P64X0_SETUP_I2C1 41 select S5P64X0_SETUP_I2C1
39 help 42 help
@@ -47,6 +50,7 @@ config MACH_SMDK6450
47 select S3C_DEV_WDT 50 select S3C_DEV_WDT
48 select S3C64XX_DEV_SPI 51 select S3C64XX_DEV_SPI
49 select SAMSUNG_DEV_ADC 52 select SAMSUNG_DEV_ADC
53 select SAMSUNG_DEV_PWM
50 select SAMSUNG_DEV_TS 54 select SAMSUNG_DEV_TS
51 select S5P64X0_SETUP_I2C1 55 select S5P64X0_SETUP_I2C1
52 help 56 help
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6440.c b/arch/arm/mach-s5p64x0/mach-smdk6440.c
index e5beb84e2393..2d559f10fd47 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6440.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6440.c
@@ -22,6 +22,7 @@
22#include <linux/module.h> 22#include <linux/module.h>
23#include <linux/clk.h> 23#include <linux/clk.h>
24#include <linux/gpio.h> 24#include <linux/gpio.h>
25#include <linux/pwm_backlight.h>
25 26
26#include <asm/mach/arch.h> 27#include <asm/mach/arch.h>
27#include <asm/mach/map.h> 28#include <asm/mach/map.h>
@@ -32,6 +33,7 @@
32#include <mach/map.h> 33#include <mach/map.h>
33#include <mach/regs-clock.h> 34#include <mach/regs-clock.h>
34#include <mach/i2c.h> 35#include <mach/i2c.h>
36#include <mach/regs-gpio.h>
35 37
36#include <plat/regs-serial.h> 38#include <plat/regs-serial.h>
37#include <plat/gpio-cfg.h> 39#include <plat/gpio-cfg.h>
@@ -43,6 +45,7 @@
43#include <plat/pll.h> 45#include <plat/pll.h>
44#include <plat/adc.h> 46#include <plat/adc.h>
45#include <plat/ts.h> 47#include <plat/ts.h>
48#include <plat/s5p-time.h>
46 49
47#define SMDK6440_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 50#define SMDK6440_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
48 S3C2410_UCON_RXILEVEL | \ 51 S3C2410_UCON_RXILEVEL | \
@@ -88,6 +91,45 @@ static struct s3c2410_uartcfg smdk6440_uartcfgs[] __initdata = {
88 }, 91 },
89}; 92};
90 93
94static int smdk6440_backlight_init(struct device *dev)
95{
96 int ret;
97
98 ret = gpio_request(S5P6440_GPF(15), "Backlight");
99 if (ret) {
100 printk(KERN_ERR "failed to request GPF for PWM-OUT1\n");
101 return ret;
102 }
103
104 /* Configure GPIO pin with S5P6440_GPF15_PWM_TOUT1 */
105 s3c_gpio_cfgpin(S5P6440_GPF(15), S3C_GPIO_SFN(2));
106
107 return 0;
108}
109
110static void smdk6440_backlight_exit(struct device *dev)
111{
112 s3c_gpio_cfgpin(S5P6440_GPF(15), S3C_GPIO_OUTPUT);
113 gpio_free(S5P6440_GPF(15));
114}
115
116static struct platform_pwm_backlight_data smdk6440_backlight_data = {
117 .pwm_id = 1,
118 .max_brightness = 255,
119 .dft_brightness = 255,
120 .pwm_period_ns = 78770,
121 .init = smdk6440_backlight_init,
122 .exit = smdk6440_backlight_exit,
123};
124
125static struct platform_device smdk6440_backlight_device = {
126 .name = "pwm-backlight",
127 .dev = {
128 .parent = &s3c_device_timer[1].dev,
129 .platform_data = &smdk6440_backlight_data,
130 },
131};
132
91static struct platform_device *smdk6440_devices[] __initdata = { 133static struct platform_device *smdk6440_devices[] __initdata = {
92 &s3c_device_adc, 134 &s3c_device_adc,
93 &s3c_device_rtc, 135 &s3c_device_rtc,
@@ -97,6 +139,8 @@ static struct platform_device *smdk6440_devices[] __initdata = {
97 &s3c_device_wdt, 139 &s3c_device_wdt,
98 &samsung_asoc_dma, 140 &samsung_asoc_dma,
99 &s5p6440_device_iis, 141 &s5p6440_device_iis,
142 &s3c_device_timer[1],
143 &smdk6440_backlight_device,
100}; 144};
101 145
102static struct s3c2410_platform_i2c s5p6440_i2c0_data __initdata = { 146static struct s3c2410_platform_i2c s5p6440_i2c0_data __initdata = {
@@ -136,6 +180,7 @@ static void __init smdk6440_map_io(void)
136 s5p_init_io(NULL, 0, S5P64X0_SYS_ID); 180 s5p_init_io(NULL, 0, S5P64X0_SYS_ID);
137 s3c24xx_init_clocks(12000000); 181 s3c24xx_init_clocks(12000000);
138 s3c24xx_init_uarts(smdk6440_uartcfgs, ARRAY_SIZE(smdk6440_uartcfgs)); 182 s3c24xx_init_uarts(smdk6440_uartcfgs, ARRAY_SIZE(smdk6440_uartcfgs));
183 s5p_set_timer_source(S5P_PWM3, S5P_PWM4);
139} 184}
140 185
141static void __init smdk6440_machine_init(void) 186static void __init smdk6440_machine_init(void)
@@ -159,5 +204,5 @@ MACHINE_START(SMDK6440, "SMDK6440")
159 .init_irq = s5p6440_init_irq, 204 .init_irq = s5p6440_init_irq,
160 .map_io = smdk6440_map_io, 205 .map_io = smdk6440_map_io,
161 .init_machine = smdk6440_machine_init, 206 .init_machine = smdk6440_machine_init,
162 .timer = &s3c24xx_timer, 207 .timer = &s5p_timer,
163MACHINE_END 208MACHINE_END
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6450.c b/arch/arm/mach-s5p64x0/mach-smdk6450.c
index 3a20de0a9264..d19c4690ee97 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6450.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6450.c
@@ -22,6 +22,7 @@
22#include <linux/module.h> 22#include <linux/module.h>
23#include <linux/clk.h> 23#include <linux/clk.h>
24#include <linux/gpio.h> 24#include <linux/gpio.h>
25#include <linux/pwm_backlight.h>
25 26
26#include <asm/mach/arch.h> 27#include <asm/mach/arch.h>
27#include <asm/mach/map.h> 28#include <asm/mach/map.h>
@@ -32,6 +33,7 @@
32#include <mach/map.h> 33#include <mach/map.h>
33#include <mach/regs-clock.h> 34#include <mach/regs-clock.h>
34#include <mach/i2c.h> 35#include <mach/i2c.h>
36#include <mach/regs-gpio.h>
35 37
36#include <plat/regs-serial.h> 38#include <plat/regs-serial.h>
37#include <plat/gpio-cfg.h> 39#include <plat/gpio-cfg.h>
@@ -43,6 +45,7 @@
43#include <plat/pll.h> 45#include <plat/pll.h>
44#include <plat/adc.h> 46#include <plat/adc.h>
45#include <plat/ts.h> 47#include <plat/ts.h>
48#include <plat/s5p-time.h>
46 49
47#define SMDK6450_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 50#define SMDK6450_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
48 S3C2410_UCON_RXILEVEL | \ 51 S3C2410_UCON_RXILEVEL | \
@@ -106,6 +109,45 @@ static struct s3c2410_uartcfg smdk6450_uartcfgs[] __initdata = {
106#endif 109#endif
107}; 110};
108 111
112static int smdk6450_backlight_init(struct device *dev)
113{
114 int ret;
115
116 ret = gpio_request(S5P6450_GPF(15), "Backlight");
117 if (ret) {
118 printk(KERN_ERR "failed to request GPF for PWM-OUT1\n");
119 return ret;
120 }
121
122 /* Configure GPIO pin with S5P6450_GPF15_PWM_TOUT1 */
123 s3c_gpio_cfgpin(S5P6450_GPF(15), S3C_GPIO_SFN(2));
124
125 return 0;
126}
127
128static void smdk6450_backlight_exit(struct device *dev)
129{
130 s3c_gpio_cfgpin(S5P6450_GPF(15), S3C_GPIO_OUTPUT);
131 gpio_free(S5P6450_GPF(15));
132}
133
134static struct platform_pwm_backlight_data smdk6450_backlight_data = {
135 .pwm_id = 1,
136 .max_brightness = 255,
137 .dft_brightness = 255,
138 .pwm_period_ns = 78770,
139 .init = smdk6450_backlight_init,
140 .exit = smdk6450_backlight_exit,
141};
142
143static struct platform_device smdk6450_backlight_device = {
144 .name = "pwm-backlight",
145 .dev = {
146 .parent = &s3c_device_timer[1].dev,
147 .platform_data = &smdk6450_backlight_data,
148 },
149};
150
109static struct platform_device *smdk6450_devices[] __initdata = { 151static struct platform_device *smdk6450_devices[] __initdata = {
110 &s3c_device_adc, 152 &s3c_device_adc,
111 &s3c_device_rtc, 153 &s3c_device_rtc,
@@ -115,6 +157,8 @@ static struct platform_device *smdk6450_devices[] __initdata = {
115 &s3c_device_wdt, 157 &s3c_device_wdt,
116 &samsung_asoc_dma, 158 &samsung_asoc_dma,
117 &s5p6450_device_iis0, 159 &s5p6450_device_iis0,
160 &s3c_device_timer[1],
161 &smdk6450_backlight_device,
118 /* s5p6450_device_spi0 will be added */ 162 /* s5p6450_device_spi0 will be added */
119}; 163};
120 164
@@ -155,6 +199,7 @@ static void __init smdk6450_map_io(void)
155 s5p_init_io(NULL, 0, S5P64X0_SYS_ID); 199 s5p_init_io(NULL, 0, S5P64X0_SYS_ID);
156 s3c24xx_init_clocks(19200000); 200 s3c24xx_init_clocks(19200000);
157 s3c24xx_init_uarts(smdk6450_uartcfgs, ARRAY_SIZE(smdk6450_uartcfgs)); 201 s3c24xx_init_uarts(smdk6450_uartcfgs, ARRAY_SIZE(smdk6450_uartcfgs));
202 s5p_set_timer_source(S5P_PWM3, S5P_PWM4);
158} 203}
159 204
160static void __init smdk6450_machine_init(void) 205static void __init smdk6450_machine_init(void)
@@ -178,5 +223,5 @@ MACHINE_START(SMDK6450, "SMDK6450")
178 .init_irq = s5p6450_init_irq, 223 .init_irq = s5p6450_init_irq,
179 .map_io = smdk6450_map_io, 224 .map_io = smdk6450_map_io,
180 .init_machine = smdk6450_machine_init, 225 .init_machine = smdk6450_machine_init,
181 .timer = &s3c24xx_timer, 226 .timer = &s5p_timer,
182MACHINE_END 227MACHINE_END
diff --git a/arch/arm/mach-s5pc100/Kconfig b/arch/arm/mach-s5pc100/Kconfig
index b8fbf2fcba6f..608722ff4f28 100644
--- a/arch/arm/mach-s5pc100/Kconfig
+++ b/arch/arm/mach-s5pc100/Kconfig
@@ -58,6 +58,7 @@ config MACH_SMDKC100
58 select SAMSUNG_DEV_ADC 58 select SAMSUNG_DEV_ADC
59 select SAMSUNG_DEV_IDE 59 select SAMSUNG_DEV_IDE
60 select SAMSUNG_DEV_KEYPAD 60 select SAMSUNG_DEV_KEYPAD
61 select SAMSUNG_DEV_PWM
61 select SAMSUNG_DEV_TS 62 select SAMSUNG_DEV_TS
62 select S5PC100_SETUP_FB_24BPP 63 select S5PC100_SETUP_FB_24BPP
63 select S5PC100_SETUP_I2C1 64 select S5PC100_SETUP_I2C1
diff --git a/arch/arm/mach-s5pc100/gpiolib.c b/arch/arm/mach-s5pc100/gpiolib.c
index 20856eb7dd51..2842394b28b5 100644
--- a/arch/arm/mach-s5pc100/gpiolib.c
+++ b/arch/arm/mach-s5pc100/gpiolib.c
@@ -348,6 +348,7 @@ static __init int s5pc100_gpiolib_init(void)
348 } 348 }
349 349
350 samsung_gpiolib_add_4bit_chips(s5pc100_gpio_chips, nr_chips); 350 samsung_gpiolib_add_4bit_chips(s5pc100_gpio_chips, nr_chips);
351 s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);
351 352
352 return 0; 353 return 0;
353} 354}
diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c
index dd192a27524d..0525cb3ef406 100644
--- a/arch/arm/mach-s5pc100/mach-smdkc100.c
+++ b/arch/arm/mach-s5pc100/mach-smdkc100.c
@@ -23,12 +23,15 @@
23#include <linux/fb.h> 23#include <linux/fb.h>
24#include <linux/delay.h> 24#include <linux/delay.h>
25#include <linux/input.h> 25#include <linux/input.h>
26#include <linux/pwm_backlight.h>
26 27
27#include <asm/mach/arch.h> 28#include <asm/mach/arch.h>
28#include <asm/mach/map.h> 29#include <asm/mach/map.h>
29 30
30#include <mach/map.h> 31#include <mach/map.h>
31#include <mach/regs-fb.h> 32#include <mach/regs-fb.h>
33#include <mach/regs-gpio.h>
34
32#include <video/platform_lcd.h> 35#include <video/platform_lcd.h>
33 36
34#include <asm/irq.h> 37#include <asm/irq.h>
@@ -107,9 +110,6 @@ static struct i2c_board_info i2c_devs1[] __initdata = {
107static void smdkc100_lcd_power_set(struct plat_lcd_data *pd, 110static void smdkc100_lcd_power_set(struct plat_lcd_data *pd,
108 unsigned int power) 111 unsigned int power)
109{ 112{
110 /* backlight */
111 gpio_direction_output(S5PC100_GPD(0), power);
112
113 if (power) { 113 if (power) {
114 /* module reset */ 114 /* module reset */
115 gpio_direction_output(S5PC100_GPH0(6), 1); 115 gpio_direction_output(S5PC100_GPH0(6), 1);
@@ -179,6 +179,45 @@ static struct samsung_keypad_platdata smdkc100_keypad_data __initdata = {
179 .cols = 8, 179 .cols = 8,
180}; 180};
181 181
182static int smdkc100_backlight_init(struct device *dev)
183{
184 int ret;
185
186 ret = gpio_request(S5PC100_GPD(0), "Backlight");
187 if (ret) {
188 printk(KERN_ERR "failed to request GPF for PWM-OUT0\n");
189 return ret;
190 }
191
192 /* Configure GPIO pin with S5PC100_GPD_TOUT_0 */
193 s3c_gpio_cfgpin(S5PC100_GPD(0), S3C_GPIO_SFN(2));
194
195 return 0;
196}
197
198static void smdkc100_backlight_exit(struct device *dev)
199{
200 s3c_gpio_cfgpin(S5PC100_GPD(0), S3C_GPIO_OUTPUT);
201 gpio_free(S5PC100_GPD(0));
202}
203
204static struct platform_pwm_backlight_data smdkc100_backlight_data = {
205 .pwm_id = 0,
206 .max_brightness = 255,
207 .dft_brightness = 255,
208 .pwm_period_ns = 78770,
209 .init = smdkc100_backlight_init,
210 .exit = smdkc100_backlight_exit,
211};
212
213static struct platform_device smdkc100_backlight_device = {
214 .name = "pwm-backlight",
215 .dev = {
216 .parent = &s3c_device_timer[0].dev,
217 .platform_data = &smdkc100_backlight_data,
218 },
219};
220
182static struct platform_device *smdkc100_devices[] __initdata = { 221static struct platform_device *smdkc100_devices[] __initdata = {
183 &s3c_device_adc, 222 &s3c_device_adc,
184 &s3c_device_cfcon, 223 &s3c_device_cfcon,
@@ -200,6 +239,8 @@ static struct platform_device *smdkc100_devices[] __initdata = {
200 &s5p_device_fimc1, 239 &s5p_device_fimc1,
201 &s5p_device_fimc2, 240 &s5p_device_fimc2,
202 &s5pc100_device_spdif, 241 &s5pc100_device_spdif,
242 &s3c_device_timer[0],
243 &smdkc100_backlight_device,
203}; 244};
204 245
205static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = { 246static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
@@ -233,7 +274,6 @@ static void __init smdkc100_machine_init(void)
233 s5pc100_spdif_setup_gpio(S5PC100_SPDIF_GPD); 274 s5pc100_spdif_setup_gpio(S5PC100_SPDIF_GPD);
234 275
235 /* LCD init */ 276 /* LCD init */
236 gpio_request(S5PC100_GPD(0), "GPD");
237 gpio_request(S5PC100_GPH0(6), "GPH0"); 277 gpio_request(S5PC100_GPH0(6), "GPH0");
238 smdkc100_lcd_power_set(&smdkc100_lcd_power_data, 0); 278 smdkc100_lcd_power_set(&smdkc100_lcd_power_data, 0);
239 platform_add_devices(smdkc100_devices, ARRAY_SIZE(smdkc100_devices)); 279 platform_add_devices(smdkc100_devices, ARRAY_SIZE(smdkc100_devices));
diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
index 53aabef1e9ce..37b5a97594a5 100644
--- a/arch/arm/mach-s5pv210/Kconfig
+++ b/arch/arm/mach-s5pv210/Kconfig
@@ -13,6 +13,7 @@ config CPU_S5PV210
13 bool 13 bool
14 select S3C_PL330_DMA 14 select S3C_PL330_DMA
15 select S5P_EXT_INT 15 select S5P_EXT_INT
16 select S5P_HRT
16 select S5PV210_PM if PM 17 select S5PV210_PM if PM
17 help 18 help
18 Enable S5PV210 CPU support 19 Enable S5PV210 CPU support
@@ -53,6 +54,11 @@ config S5PV210_SETUP_SDHCI_GPIO
53 help 54 help
54 Common setup code for SDHCI gpio. 55 Common setup code for SDHCI gpio.
55 56
57config S5PV210_SETUP_FIMC
58 bool
59 help
60 Common setup code for the camera interfaces.
61
56menu "S5PC110 Machines" 62menu "S5PC110 Machines"
57 63
58config MACH_AQUILA 64config MACH_AQUILA
@@ -130,6 +136,7 @@ config MACH_SMDKV210
130 select SAMSUNG_DEV_ADC 136 select SAMSUNG_DEV_ADC
131 select SAMSUNG_DEV_IDE 137 select SAMSUNG_DEV_IDE
132 select SAMSUNG_DEV_KEYPAD 138 select SAMSUNG_DEV_KEYPAD
139 select SAMSUNG_DEV_PWM
133 select SAMSUNG_DEV_TS 140 select SAMSUNG_DEV_TS
134 select S5PV210_SETUP_FB_24BPP 141 select S5PV210_SETUP_FB_24BPP
135 select S5PV210_SETUP_I2C1 142 select S5PV210_SETUP_I2C1
diff --git a/arch/arm/mach-s5pv210/Makefile b/arch/arm/mach-s5pv210/Makefile
index ff1a0db57a2f..11f17907b4e8 100644
--- a/arch/arm/mach-s5pv210/Makefile
+++ b/arch/arm/mach-s5pv210/Makefile
@@ -31,6 +31,7 @@ obj-y += dev-audio.o
31obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o 31obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o
32 32
33obj-$(CONFIG_S5PV210_SETUP_FB_24BPP) += setup-fb-24bpp.o 33obj-$(CONFIG_S5PV210_SETUP_FB_24BPP) += setup-fb-24bpp.o
34obj-$(CONFIG_S5PV210_SETUP_FIMC) += setup-fimc.o
34obj-$(CONFIG_S5PV210_SETUP_I2C1) += setup-i2c1.o 35obj-$(CONFIG_S5PV210_SETUP_I2C1) += setup-i2c1.o
35obj-$(CONFIG_S5PV210_SETUP_I2C2) += setup-i2c2.o 36obj-$(CONFIG_S5PV210_SETUP_I2C2) += setup-i2c2.o
36obj-$(CONFIG_S5PV210_SETUP_IDE) += setup-ide.o 37obj-$(CONFIG_S5PV210_SETUP_IDE) += setup-ide.o
diff --git a/arch/arm/mach-s5pv210/gpiolib.c b/arch/arm/mach-s5pv210/gpiolib.c
index ab673effd767..1ba20a703e05 100644
--- a/arch/arm/mach-s5pv210/gpiolib.c
+++ b/arch/arm/mach-s5pv210/gpiolib.c
@@ -281,6 +281,7 @@ static __init int s5pv210_gpiolib_init(void)
281 } 281 }
282 282
283 samsung_gpiolib_add_4bit_chips(s5pv210_gpio_4bit, nr_chips); 283 samsung_gpiolib_add_4bit_chips(s5pv210_gpio_4bit, nr_chips);
284 s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);
284 285
285 return 0; 286 return 0;
286} 287}
diff --git a/arch/arm/mach-s5pv210/include/mach/regs-clock.h b/arch/arm/mach-s5pv210/include/mach/regs-clock.h
index 4c45b74def5f..78925c516346 100644
--- a/arch/arm/mach-s5pv210/include/mach/regs-clock.h
+++ b/arch/arm/mach-s5pv210/include/mach/regs-clock.h
@@ -146,6 +146,10 @@
146#define S5P_OM_STAT S5P_CLKREG(0xE100) 146#define S5P_OM_STAT S5P_CLKREG(0xE100)
147#define S5P_USB_PHY_CONTROL S5P_CLKREG(0xE80C) 147#define S5P_USB_PHY_CONTROL S5P_CLKREG(0xE80C)
148#define S5P_DAC_CONTROL S5P_CLKREG(0xE810) 148#define S5P_DAC_CONTROL S5P_CLKREG(0xE810)
149#define S5P_MIPI_DPHY_CONTROL(x) S5P_CLKREG(0xE814)
150#define S5P_MIPI_DPHY_ENABLE (1 << 0)
151#define S5P_MIPI_DPHY_SRESETN (1 << 1)
152#define S5P_MIPI_DPHY_MRESETN (1 << 2)
149 153
150#define S5P_INFORM0 S5P_CLKREG(0xF000) 154#define S5P_INFORM0 S5P_CLKREG(0xF000)
151#define S5P_INFORM1 S5P_CLKREG(0xF004) 155#define S5P_INFORM1 S5P_CLKREG(0xF004)
@@ -161,7 +165,6 @@
161#define S5P_MDNIE_SEL S5P_CLKREG(0x7008) 165#define S5P_MDNIE_SEL S5P_CLKREG(0x7008)
162#define S5P_MIPI_PHY_CON0 S5P_CLKREG(0x7200) 166#define S5P_MIPI_PHY_CON0 S5P_CLKREG(0x7200)
163#define S5P_MIPI_PHY_CON1 S5P_CLKREG(0x7204) 167#define S5P_MIPI_PHY_CON1 S5P_CLKREG(0x7204)
164#define S5P_MIPI_DPHY_CONTROL S5P_CLKREG(0xE814)
165 168
166#define S5P_IDLE_CFG_TL_MASK (3 << 30) 169#define S5P_IDLE_CFG_TL_MASK (3 << 30)
167#define S5P_IDLE_CFG_TM_MASK (3 << 28) 170#define S5P_IDLE_CFG_TM_MASK (3 << 28)
diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c
index 557add4fc56c..4e1d8ff5ae59 100644
--- a/arch/arm/mach-s5pv210/mach-aquila.c
+++ b/arch/arm/mach-s5pv210/mach-aquila.c
@@ -39,6 +39,7 @@
39#include <plat/fb.h> 39#include <plat/fb.h>
40#include <plat/fimc-core.h> 40#include <plat/fimc-core.h>
41#include <plat/sdhci.h> 41#include <plat/sdhci.h>
42#include <plat/s5p-time.h>
42 43
43/* Following are default values for UCON, ULCON and UFCON UART registers */ 44/* Following are default values for UCON, ULCON and UFCON UART registers */
44#define AQUILA_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 45#define AQUILA_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
@@ -296,13 +297,11 @@ static struct regulator_init_data aquila_ldo17_data = {
296}; 297};
297 298
298/* BUCK */ 299/* BUCK */
299static struct regulator_consumer_supply buck1_consumer[] = { 300static struct regulator_consumer_supply buck1_consumer =
300 { .supply = "vddarm", }, 301 REGULATOR_SUPPLY("vddarm", NULL);
301};
302 302
303static struct regulator_consumer_supply buck2_consumer[] = { 303static struct regulator_consumer_supply buck2_consumer =
304 { .supply = "vddint", }, 304 REGULATOR_SUPPLY("vddint", NULL);
305};
306 305
307static struct regulator_init_data aquila_buck1_data = { 306static struct regulator_init_data aquila_buck1_data = {
308 .constraints = { 307 .constraints = {
@@ -313,8 +312,8 @@ static struct regulator_init_data aquila_buck1_data = {
313 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | 312 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
314 REGULATOR_CHANGE_STATUS, 313 REGULATOR_CHANGE_STATUS,
315 }, 314 },
316 .num_consumer_supplies = ARRAY_SIZE(buck1_consumer), 315 .num_consumer_supplies = 1,
317 .consumer_supplies = buck1_consumer, 316 .consumer_supplies = &buck1_consumer,
318}; 317};
319 318
320static struct regulator_init_data aquila_buck2_data = { 319static struct regulator_init_data aquila_buck2_data = {
@@ -326,8 +325,8 @@ static struct regulator_init_data aquila_buck2_data = {
326 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | 325 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
327 REGULATOR_CHANGE_STATUS, 326 REGULATOR_CHANGE_STATUS,
328 }, 327 },
329 .num_consumer_supplies = ARRAY_SIZE(buck2_consumer), 328 .num_consumer_supplies = 1,
330 .consumer_supplies = buck2_consumer, 329 .consumer_supplies = &buck2_consumer,
331}; 330};
332 331
333static struct regulator_init_data aquila_buck3_data = { 332static struct regulator_init_data aquila_buck3_data = {
@@ -391,26 +390,14 @@ static struct max8998_platform_data aquila_max8998_pdata = {
391#endif 390#endif
392 391
393static struct regulator_consumer_supply wm8994_fixed_voltage0_supplies[] = { 392static struct regulator_consumer_supply wm8994_fixed_voltage0_supplies[] = {
394 { 393 REGULATOR_SUPPLY("DBVDD", "5-001a"),
395 .dev_name = "5-001a", 394 REGULATOR_SUPPLY("AVDD2", "5-001a"),
396 .supply = "DBVDD", 395 REGULATOR_SUPPLY("CPVDD", "5-001a"),
397 }, {
398 .dev_name = "5-001a",
399 .supply = "AVDD2",
400 }, {
401 .dev_name = "5-001a",
402 .supply = "CPVDD",
403 },
404}; 396};
405 397
406static struct regulator_consumer_supply wm8994_fixed_voltage1_supplies[] = { 398static struct regulator_consumer_supply wm8994_fixed_voltage1_supplies[] = {
407 { 399 REGULATOR_SUPPLY("SPKVDD1", "5-001a"),
408 .dev_name = "5-001a", 400 REGULATOR_SUPPLY("SPKVDD2", "5-001a"),
409 .supply = "SPKVDD1",
410 }, {
411 .dev_name = "5-001a",
412 .supply = "SPKVDD2",
413 },
414}; 401};
415 402
416static struct regulator_init_data wm8994_fixed_voltage0_init_data = { 403static struct regulator_init_data wm8994_fixed_voltage0_init_data = {
@@ -459,15 +446,11 @@ static struct platform_device wm8994_fixed_voltage1 = {
459 }, 446 },
460}; 447};
461 448
462static struct regulator_consumer_supply wm8994_avdd1_supply = { 449static struct regulator_consumer_supply wm8994_avdd1_supply =
463 .dev_name = "5-001a", 450 REGULATOR_SUPPLY("AVDD1", "5-001a");
464 .supply = "AVDD1",
465};
466 451
467static struct regulator_consumer_supply wm8994_dcvdd_supply = { 452static struct regulator_consumer_supply wm8994_dcvdd_supply =
468 .dev_name = "5-001a", 453 REGULATOR_SUPPLY("DCVDD", "5-001a");
469 .supply = "DCVDD",
470};
471 454
472static struct regulator_init_data wm8994_ldo1_data = { 455static struct regulator_init_data wm8994_ldo1_data = {
473 .constraints = { 456 .constraints = {
@@ -664,6 +647,7 @@ static void __init aquila_map_io(void)
664 s5p_init_io(NULL, 0, S5P_VA_CHIPID); 647 s5p_init_io(NULL, 0, S5P_VA_CHIPID);
665 s3c24xx_init_clocks(24000000); 648 s3c24xx_init_clocks(24000000);
666 s3c24xx_init_uarts(aquila_uartcfgs, ARRAY_SIZE(aquila_uartcfgs)); 649 s3c24xx_init_uarts(aquila_uartcfgs, ARRAY_SIZE(aquila_uartcfgs));
650 s5p_set_timer_source(S5P_PWM3, S5P_PWM4);
667} 651}
668 652
669static void __init aquila_machine_init(void) 653static void __init aquila_machine_init(void)
@@ -698,5 +682,5 @@ MACHINE_START(AQUILA, "Aquila")
698 .init_irq = s5pv210_init_irq, 682 .init_irq = s5pv210_init_irq,
699 .map_io = aquila_map_io, 683 .map_io = aquila_map_io,
700 .init_machine = aquila_machine_init, 684 .init_machine = aquila_machine_init,
701 .timer = &s3c24xx_timer, 685 .timer = &s5p_timer,
702MACHINE_END 686MACHINE_END
diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c
index 056f5c769b0a..243291722c66 100644
--- a/arch/arm/mach-s5pv210/mach-goni.c
+++ b/arch/arm/mach-s5pv210/mach-goni.c
@@ -45,6 +45,7 @@
45#include <plat/keypad.h> 45#include <plat/keypad.h>
46#include <plat/sdhci.h> 46#include <plat/sdhci.h>
47#include <plat/clock.h> 47#include <plat/clock.h>
48#include <plat/s5p-time.h>
48 49
49/* Following are default values for UCON, ULCON and UFCON UART registers */ 50/* Following are default values for UCON, ULCON and UFCON UART registers */
50#define GONI_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 51#define GONI_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
@@ -108,6 +109,8 @@ static struct s3c_fb_pd_win goni_fb_win0 = {
108 }, 109 },
109 .max_bpp = 32, 110 .max_bpp = 32,
110 .default_bpp = 16, 111 .default_bpp = 16,
112 .virtual_x = 480,
113 .virtual_y = 2 * 800,
111}; 114};
112 115
113static struct s3c_fb_platdata goni_lcd_pdata __initdata = { 116static struct s3c_fb_platdata goni_lcd_pdata __initdata = {
@@ -269,10 +272,30 @@ static void __init goni_tsp_init(void)
269/* MAX8998 regulators */ 272/* MAX8998 regulators */
270#if defined(CONFIG_REGULATOR_MAX8998) || defined(CONFIG_REGULATOR_MAX8998_MODULE) 273#if defined(CONFIG_REGULATOR_MAX8998) || defined(CONFIG_REGULATOR_MAX8998_MODULE)
271 274
275static struct regulator_consumer_supply goni_ldo3_consumers[] = {
276 REGULATOR_SUPPLY("vusb_a", "s3c-hsotg"),
277};
278
272static struct regulator_consumer_supply goni_ldo5_consumers[] = { 279static struct regulator_consumer_supply goni_ldo5_consumers[] = {
273 REGULATOR_SUPPLY("vmmc", "s3c-sdhci.0"), 280 REGULATOR_SUPPLY("vmmc", "s3c-sdhci.0"),
274}; 281};
275 282
283static struct regulator_consumer_supply goni_ldo8_consumers[] = {
284 REGULATOR_SUPPLY("vusb_d", "s3c-hsotg"),
285};
286
287static struct regulator_consumer_supply goni_ldo11_consumers[] = {
288 REGULATOR_SUPPLY("vddio", "0-0030"), /* "CAM_IO_2.8V" */
289};
290
291static struct regulator_consumer_supply goni_ldo13_consumers[] = {
292 REGULATOR_SUPPLY("vdda", "0-0030"), /* "CAM_A_2.8V" */
293};
294
295static struct regulator_consumer_supply goni_ldo14_consumers[] = {
296 REGULATOR_SUPPLY("vdd_core", "0-0030"), /* "CAM_CIF_1.8V" */
297};
298
276static struct regulator_init_data goni_ldo2_data = { 299static struct regulator_init_data goni_ldo2_data = {
277 .constraints = { 300 .constraints = {
278 .name = "VALIVE_1.1V", 301 .name = "VALIVE_1.1V",
@@ -292,8 +315,10 @@ static struct regulator_init_data goni_ldo3_data = {
292 .min_uV = 1100000, 315 .min_uV = 1100000,
293 .max_uV = 1100000, 316 .max_uV = 1100000,
294 .apply_uV = 1, 317 .apply_uV = 1,
295 .always_on = 1, 318 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
296 }, 319 },
320 .num_consumer_supplies = ARRAY_SIZE(goni_ldo3_consumers),
321 .consumer_supplies = goni_ldo3_consumers,
297}; 322};
298 323
299static struct regulator_init_data goni_ldo4_data = { 324static struct regulator_init_data goni_ldo4_data = {
@@ -311,6 +336,7 @@ static struct regulator_init_data goni_ldo5_data = {
311 .min_uV = 2800000, 336 .min_uV = 2800000,
312 .max_uV = 2800000, 337 .max_uV = 2800000,
313 .apply_uV = 1, 338 .apply_uV = 1,
339 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
314 }, 340 },
315 .num_consumer_supplies = ARRAY_SIZE(goni_ldo5_consumers), 341 .num_consumer_supplies = ARRAY_SIZE(goni_ldo5_consumers),
316 .consumer_supplies = goni_ldo5_consumers, 342 .consumer_supplies = goni_ldo5_consumers,
@@ -341,8 +367,10 @@ static struct regulator_init_data goni_ldo8_data = {
341 .min_uV = 3300000, 367 .min_uV = 3300000,
342 .max_uV = 3300000, 368 .max_uV = 3300000,
343 .apply_uV = 1, 369 .apply_uV = 1,
344 .always_on = 1, 370 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
345 }, 371 },
372 .num_consumer_supplies = ARRAY_SIZE(goni_ldo8_consumers),
373 .consumer_supplies = goni_ldo8_consumers,
346}; 374};
347 375
348static struct regulator_init_data goni_ldo9_data = { 376static struct regulator_init_data goni_ldo9_data = {
@@ -351,7 +379,6 @@ static struct regulator_init_data goni_ldo9_data = {
351 .min_uV = 2800000, 379 .min_uV = 2800000,
352 .max_uV = 2800000, 380 .max_uV = 2800000,
353 .apply_uV = 1, 381 .apply_uV = 1,
354 .always_on = 1,
355 }, 382 },
356}; 383};
357 384
@@ -371,8 +398,10 @@ static struct regulator_init_data goni_ldo11_data = {
371 .min_uV = 2800000, 398 .min_uV = 2800000,
372 .max_uV = 2800000, 399 .max_uV = 2800000,
373 .apply_uV = 1, 400 .apply_uV = 1,
374 .always_on = 1, 401 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
375 }, 402 },
403 .num_consumer_supplies = ARRAY_SIZE(goni_ldo11_consumers),
404 .consumer_supplies = goni_ldo11_consumers,
376}; 405};
377 406
378static struct regulator_init_data goni_ldo12_data = { 407static struct regulator_init_data goni_ldo12_data = {
@@ -381,7 +410,6 @@ static struct regulator_init_data goni_ldo12_data = {
381 .min_uV = 1200000, 410 .min_uV = 1200000,
382 .max_uV = 1200000, 411 .max_uV = 1200000,
383 .apply_uV = 1, 412 .apply_uV = 1,
384 .always_on = 1,
385 }, 413 },
386}; 414};
387 415
@@ -391,8 +419,10 @@ static struct regulator_init_data goni_ldo13_data = {
391 .min_uV = 2800000, 419 .min_uV = 2800000,
392 .max_uV = 2800000, 420 .max_uV = 2800000,
393 .apply_uV = 1, 421 .apply_uV = 1,
394 .always_on = 1, 422 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
395 }, 423 },
424 .num_consumer_supplies = ARRAY_SIZE(goni_ldo13_consumers),
425 .consumer_supplies = goni_ldo13_consumers,
396}; 426};
397 427
398static struct regulator_init_data goni_ldo14_data = { 428static struct regulator_init_data goni_ldo14_data = {
@@ -401,8 +431,10 @@ static struct regulator_init_data goni_ldo14_data = {
401 .min_uV = 1800000, 431 .min_uV = 1800000,
402 .max_uV = 1800000, 432 .max_uV = 1800000,
403 .apply_uV = 1, 433 .apply_uV = 1,
404 .always_on = 1, 434 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
405 }, 435 },
436 .num_consumer_supplies = ARRAY_SIZE(goni_ldo14_consumers),
437 .consumer_supplies = goni_ldo14_consumers,
406}; 438};
407 439
408static struct regulator_init_data goni_ldo15_data = { 440static struct regulator_init_data goni_ldo15_data = {
@@ -411,7 +443,6 @@ static struct regulator_init_data goni_ldo15_data = {
411 .min_uV = 3300000, 443 .min_uV = 3300000,
412 .max_uV = 3300000, 444 .max_uV = 3300000,
413 .apply_uV = 1, 445 .apply_uV = 1,
414 .always_on = 1,
415 }, 446 },
416}; 447};
417 448
@@ -421,7 +452,6 @@ static struct regulator_init_data goni_ldo16_data = {
421 .min_uV = 1800000, 452 .min_uV = 1800000,
422 .max_uV = 1800000, 453 .max_uV = 1800000,
423 .apply_uV = 1, 454 .apply_uV = 1,
424 .always_on = 1,
425 }, 455 },
426}; 456};
427 457
@@ -436,13 +466,11 @@ static struct regulator_init_data goni_ldo17_data = {
436}; 466};
437 467
438/* BUCK */ 468/* BUCK */
439static struct regulator_consumer_supply buck1_consumer[] = { 469static struct regulator_consumer_supply buck1_consumer =
440 { .supply = "vddarm", }, 470 REGULATOR_SUPPLY("vddarm", NULL);
441};
442 471
443static struct regulator_consumer_supply buck2_consumer[] = { 472static struct regulator_consumer_supply buck2_consumer =
444 { .supply = "vddint", }, 473 REGULATOR_SUPPLY("vddint", NULL);
445};
446 474
447static struct regulator_init_data goni_buck1_data = { 475static struct regulator_init_data goni_buck1_data = {
448 .constraints = { 476 .constraints = {
@@ -453,8 +481,8 @@ static struct regulator_init_data goni_buck1_data = {
453 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | 481 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
454 REGULATOR_CHANGE_STATUS, 482 REGULATOR_CHANGE_STATUS,
455 }, 483 },
456 .num_consumer_supplies = ARRAY_SIZE(buck1_consumer), 484 .num_consumer_supplies = 1,
457 .consumer_supplies = buck1_consumer, 485 .consumer_supplies = &buck1_consumer,
458}; 486};
459 487
460static struct regulator_init_data goni_buck2_data = { 488static struct regulator_init_data goni_buck2_data = {
@@ -466,8 +494,8 @@ static struct regulator_init_data goni_buck2_data = {
466 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | 494 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
467 REGULATOR_CHANGE_STATUS, 495 REGULATOR_CHANGE_STATUS,
468 }, 496 },
469 .num_consumer_supplies = ARRAY_SIZE(buck2_consumer), 497 .num_consumer_supplies = 1,
470 .consumer_supplies = buck2_consumer, 498 .consumer_supplies = &buck2_consumer,
471}; 499};
472 500
473static struct regulator_init_data goni_buck3_data = { 501static struct regulator_init_data goni_buck3_data = {
@@ -531,26 +559,14 @@ static struct max8998_platform_data goni_max8998_pdata = {
531#endif 559#endif
532 560
533static struct regulator_consumer_supply wm8994_fixed_voltage0_supplies[] = { 561static struct regulator_consumer_supply wm8994_fixed_voltage0_supplies[] = {
534 { 562 REGULATOR_SUPPLY("DBVDD", "5-001a"),
535 .dev_name = "5-001a", 563 REGULATOR_SUPPLY("AVDD2", "5-001a"),
536 .supply = "DBVDD", 564 REGULATOR_SUPPLY("CPVDD", "5-001a"),
537 }, {
538 .dev_name = "5-001a",
539 .supply = "AVDD2",
540 }, {
541 .dev_name = "5-001a",
542 .supply = "CPVDD",
543 },
544}; 565};
545 566
546static struct regulator_consumer_supply wm8994_fixed_voltage1_supplies[] = { 567static struct regulator_consumer_supply wm8994_fixed_voltage1_supplies[] = {
547 { 568 REGULATOR_SUPPLY("SPKVDD1", "5-001a"),
548 .dev_name = "5-001a", 569 REGULATOR_SUPPLY("SPKVDD2", "5-001a"),
549 .supply = "SPKVDD1",
550 }, {
551 .dev_name = "5-001a",
552 .supply = "SPKVDD2",
553 },
554}; 570};
555 571
556static struct regulator_init_data wm8994_fixed_voltage0_init_data = { 572static struct regulator_init_data wm8994_fixed_voltage0_init_data = {
@@ -599,15 +615,11 @@ static struct platform_device wm8994_fixed_voltage1 = {
599 }, 615 },
600}; 616};
601 617
602static struct regulator_consumer_supply wm8994_avdd1_supply = { 618static struct regulator_consumer_supply wm8994_avdd1_supply =
603 .dev_name = "5-001a", 619 REGULATOR_SUPPLY("AVDD1", "5-001a");
604 .supply = "AVDD1",
605};
606 620
607static struct regulator_consumer_supply wm8994_dcvdd_supply = { 621static struct regulator_consumer_supply wm8994_dcvdd_supply =
608 .dev_name = "5-001a", 622 REGULATOR_SUPPLY("DCVDD", "5-001a");
609 .supply = "DCVDD",
610};
611 623
612static struct regulator_init_data wm8994_ldo1_data = { 624static struct regulator_init_data wm8994_ldo1_data = {
613 .constraints = { 625 .constraints = {
@@ -794,6 +806,7 @@ static struct platform_device *goni_devices[] __initdata = {
794 &goni_i2c_gpio5, 806 &goni_i2c_gpio5,
795 &mmc2_fixed_voltage, 807 &mmc2_fixed_voltage,
796 &goni_device_gpiokeys, 808 &goni_device_gpiokeys,
809 &s3c_device_i2c0,
797 &s5p_device_fimc0, 810 &s5p_device_fimc0,
798 &s5p_device_fimc1, 811 &s5p_device_fimc1,
799 &s5p_device_fimc2, 812 &s5p_device_fimc2,
@@ -823,6 +836,7 @@ static void __init goni_map_io(void)
823 s5p_init_io(NULL, 0, S5P_VA_CHIPID); 836 s5p_init_io(NULL, 0, S5P_VA_CHIPID);
824 s3c24xx_init_clocks(24000000); 837 s3c24xx_init_clocks(24000000);
825 s3c24xx_init_uarts(goni_uartcfgs, ARRAY_SIZE(goni_uartcfgs)); 838 s3c24xx_init_uarts(goni_uartcfgs, ARRAY_SIZE(goni_uartcfgs));
839 s5p_set_timer_source(S5P_PWM3, S5P_PWM4);
826} 840}
827 841
828static void __init goni_machine_init(void) 842static void __init goni_machine_init(void)
@@ -830,6 +844,9 @@ static void __init goni_machine_init(void)
830 /* Radio: call before I2C 1 registeration */ 844 /* Radio: call before I2C 1 registeration */
831 goni_radio_init(); 845 goni_radio_init();
832 846
847 /* I2C0 */
848 s3c_i2c0_set_platdata(NULL);
849
833 /* I2C1 */ 850 /* I2C1 */
834 s3c_i2c1_set_platdata(NULL); 851 s3c_i2c1_set_platdata(NULL);
835 i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs)); 852 i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
@@ -873,5 +890,5 @@ MACHINE_START(GONI, "GONI")
873 .init_irq = s5pv210_init_irq, 890 .init_irq = s5pv210_init_irq,
874 .map_io = goni_map_io, 891 .map_io = goni_map_io,
875 .init_machine = goni_machine_init, 892 .init_machine = goni_machine_init,
876 .timer = &s3c24xx_timer, 893 .timer = &s5p_timer,
877MACHINE_END 894MACHINE_END
diff --git a/arch/arm/mach-s5pv210/mach-smdkc110.c b/arch/arm/mach-s5pv210/mach-smdkc110.c
index ce11a02eabf3..6c412c8ceccc 100644
--- a/arch/arm/mach-s5pv210/mach-smdkc110.c
+++ b/arch/arm/mach-s5pv210/mach-smdkc110.c
@@ -30,6 +30,7 @@
30#include <plat/ata.h> 30#include <plat/ata.h>
31#include <plat/iic.h> 31#include <plat/iic.h>
32#include <plat/pm.h> 32#include <plat/pm.h>
33#include <plat/s5p-time.h>
33 34
34/* Following are default values for UCON, ULCON and UFCON UART registers */ 35/* Following are default values for UCON, ULCON and UFCON UART registers */
35#define SMDKC110_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 36#define SMDKC110_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
@@ -111,6 +112,7 @@ static void __init smdkc110_map_io(void)
111 s5p_init_io(NULL, 0, S5P_VA_CHIPID); 112 s5p_init_io(NULL, 0, S5P_VA_CHIPID);
112 s3c24xx_init_clocks(24000000); 113 s3c24xx_init_clocks(24000000);
113 s3c24xx_init_uarts(smdkv210_uartcfgs, ARRAY_SIZE(smdkv210_uartcfgs)); 114 s3c24xx_init_uarts(smdkv210_uartcfgs, ARRAY_SIZE(smdkv210_uartcfgs));
115 s5p_set_timer_source(S5P_PWM3, S5P_PWM4);
114} 116}
115 117
116static void __init smdkc110_machine_init(void) 118static void __init smdkc110_machine_init(void)
@@ -138,5 +140,5 @@ MACHINE_START(SMDKC110, "SMDKC110")
138 .init_irq = s5pv210_init_irq, 140 .init_irq = s5pv210_init_irq,
139 .map_io = smdkc110_map_io, 141 .map_io = smdkc110_map_io,
140 .init_machine = smdkc110_machine_init, 142 .init_machine = smdkc110_machine_init,
141 .timer = &s3c24xx_timer, 143 .timer = &s5p_timer,
142MACHINE_END 144MACHINE_END
diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c
index bc9fdb52a020..bc08ac42e7cc 100644
--- a/arch/arm/mach-s5pv210/mach-smdkv210.c
+++ b/arch/arm/mach-s5pv210/mach-smdkv210.c
@@ -18,6 +18,7 @@
18#include <linux/fb.h> 18#include <linux/fb.h>
19#include <linux/gpio.h> 19#include <linux/gpio.h>
20#include <linux/delay.h> 20#include <linux/delay.h>
21#include <linux/pwm_backlight.h>
21 22
22#include <asm/mach/arch.h> 23#include <asm/mach/arch.h>
23#include <asm/mach/map.h> 24#include <asm/mach/map.h>
@@ -43,6 +44,8 @@
43#include <plat/keypad.h> 44#include <plat/keypad.h>
44#include <plat/pm.h> 45#include <plat/pm.h>
45#include <plat/fb.h> 46#include <plat/fb.h>
47#include <plat/gpio-cfg.h>
48#include <plat/s5p-time.h>
46 49
47/* Following are default values for UCON, ULCON and UFCON UART registers */ 50/* Following are default values for UCON, ULCON and UFCON UART registers */
48#define SMDKV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 51#define SMDKV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
@@ -208,6 +211,45 @@ static struct s3c_fb_platdata smdkv210_lcd0_pdata __initdata = {
208 .setup_gpio = s5pv210_fb_gpio_setup_24bpp, 211 .setup_gpio = s5pv210_fb_gpio_setup_24bpp,
209}; 212};
210 213
214static int smdkv210_backlight_init(struct device *dev)
215{
216 int ret;
217
218 ret = gpio_request(S5PV210_GPD0(3), "Backlight");
219 if (ret) {
220 printk(KERN_ERR "failed to request GPD for PWM-OUT 3\n");
221 return ret;
222 }
223
224 /* Configure GPIO pin with S5PV210_GPD_0_3_TOUT_3 */
225 s3c_gpio_cfgpin(S5PV210_GPD0(3), S3C_GPIO_SFN(2));
226
227 return 0;
228}
229
230static void smdkv210_backlight_exit(struct device *dev)
231{
232 s3c_gpio_cfgpin(S5PV210_GPD0(3), S3C_GPIO_OUTPUT);
233 gpio_free(S5PV210_GPD0(3));
234}
235
236static struct platform_pwm_backlight_data smdkv210_backlight_data = {
237 .pwm_id = 3,
238 .max_brightness = 255,
239 .dft_brightness = 255,
240 .pwm_period_ns = 78770,
241 .init = smdkv210_backlight_init,
242 .exit = smdkv210_backlight_exit,
243};
244
245static struct platform_device smdkv210_backlight_device = {
246 .name = "pwm-backlight",
247 .dev = {
248 .parent = &s3c_device_timer[3].dev,
249 .platform_data = &smdkv210_backlight_data,
250 },
251};
252
211static struct platform_device *smdkv210_devices[] __initdata = { 253static struct platform_device *smdkv210_devices[] __initdata = {
212 &s3c_device_adc, 254 &s3c_device_adc,
213 &s3c_device_cfcon, 255 &s3c_device_cfcon,
@@ -229,6 +271,8 @@ static struct platform_device *smdkv210_devices[] __initdata = {
229 &samsung_device_keypad, 271 &samsung_device_keypad,
230 &smdkv210_dm9000, 272 &smdkv210_dm9000,
231 &smdkv210_lcd_lte480wv, 273 &smdkv210_lcd_lte480wv,
274 &s3c_device_timer[3],
275 &smdkv210_backlight_device,
232}; 276};
233 277
234static void __init smdkv210_dm9000_init(void) 278static void __init smdkv210_dm9000_init(void)
@@ -272,6 +316,7 @@ static void __init smdkv210_map_io(void)
272 s5p_init_io(NULL, 0, S5P_VA_CHIPID); 316 s5p_init_io(NULL, 0, S5P_VA_CHIPID);
273 s3c24xx_init_clocks(24000000); 317 s3c24xx_init_clocks(24000000);
274 s3c24xx_init_uarts(smdkv210_uartcfgs, ARRAY_SIZE(smdkv210_uartcfgs)); 318 s3c24xx_init_uarts(smdkv210_uartcfgs, ARRAY_SIZE(smdkv210_uartcfgs));
319 s5p_set_timer_source(S5P_PWM2, S5P_PWM4);
275} 320}
276 321
277static void __init smdkv210_machine_init(void) 322static void __init smdkv210_machine_init(void)
@@ -306,5 +351,5 @@ MACHINE_START(SMDKV210, "SMDKV210")
306 .init_irq = s5pv210_init_irq, 351 .init_irq = s5pv210_init_irq,
307 .map_io = smdkv210_map_io, 352 .map_io = smdkv210_map_io,
308 .init_machine = smdkv210_machine_init, 353 .init_machine = smdkv210_machine_init,
309 .timer = &s3c24xx_timer, 354 .timer = &s5p_timer,
310MACHINE_END 355MACHINE_END
diff --git a/arch/arm/mach-s5pv210/mach-torbreck.c b/arch/arm/mach-s5pv210/mach-torbreck.c
index 043c938806b0..925fc0dc6252 100644
--- a/arch/arm/mach-s5pv210/mach-torbreck.c
+++ b/arch/arm/mach-s5pv210/mach-torbreck.c
@@ -27,6 +27,7 @@
27#include <plat/devs.h> 27#include <plat/devs.h>
28#include <plat/cpu.h> 28#include <plat/cpu.h>
29#include <plat/iic.h> 29#include <plat/iic.h>
30#include <plat/s5p-time.h>
30 31
31/* Following are default values for UCON, ULCON and UFCON UART registers */ 32/* Following are default values for UCON, ULCON and UFCON UART registers */
32#define TORBRECK_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 33#define TORBRECK_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
@@ -104,6 +105,7 @@ static void __init torbreck_map_io(void)
104 s5p_init_io(NULL, 0, S5P_VA_CHIPID); 105 s5p_init_io(NULL, 0, S5P_VA_CHIPID);
105 s3c24xx_init_clocks(24000000); 106 s3c24xx_init_clocks(24000000);
106 s3c24xx_init_uarts(torbreck_uartcfgs, ARRAY_SIZE(torbreck_uartcfgs)); 107 s3c24xx_init_uarts(torbreck_uartcfgs, ARRAY_SIZE(torbreck_uartcfgs));
108 s5p_set_timer_source(S5P_PWM3, S5P_PWM4);
107} 109}
108 110
109static void __init torbreck_machine_init(void) 111static void __init torbreck_machine_init(void)
@@ -127,5 +129,5 @@ MACHINE_START(TORBRECK, "TORBRECK")
127 .init_irq = s5pv210_init_irq, 129 .init_irq = s5pv210_init_irq,
128 .map_io = torbreck_map_io, 130 .map_io = torbreck_map_io,
129 .init_machine = torbreck_machine_init, 131 .init_machine = torbreck_machine_init,
130 .timer = &s3c24xx_timer, 132 .timer = &s5p_timer,
131MACHINE_END 133MACHINE_END
diff --git a/arch/arm/mach-s5pv210/setup-fimc.c b/arch/arm/mach-s5pv210/setup-fimc.c
new file mode 100644
index 000000000000..54cc5b11be0b
--- /dev/null
+++ b/arch/arm/mach-s5pv210/setup-fimc.c
@@ -0,0 +1,43 @@
1/*
2 * Copyright (C) 2011 Samsung Electronics Co., Ltd.
3 *
4 * S5PV210 camera interface GPIO configuration.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/gpio.h>
12#include <plat/gpio-cfg.h>
13#include <plat/camport.h>
14
15int s5pv210_fimc_setup_gpio(enum s5p_camport_id id)
16{
17 u32 gpio8, gpio5;
18 int ret;
19
20 switch (id) {
21 case S5P_CAMPORT_A:
22 gpio8 = S5PV210_GPE0(0);
23 gpio5 = S5PV210_GPE1(0);
24 break;
25
26 case S5P_CAMPORT_B:
27 gpio8 = S5PV210_GPJ0(0);
28 gpio5 = S5PV210_GPJ1(0);
29 break;
30
31 default:
32 WARN(1, "Wrong camport id: %d\n", id);
33 return -EINVAL;
34 }
35
36 ret = s3c_gpio_cfgall_range(gpio8, 8, S3C_GPIO_SFN(2),
37 S3C_GPIO_PULL_UP);
38 if (ret)
39 return ret;
40
41 return s3c_gpio_cfgall_range(gpio5, 5, S3C_GPIO_SFN(2),
42 S3C_GPIO_PULL_UP);
43}
diff --git a/arch/arm/mach-s5pv310/Kconfig b/arch/arm/mach-s5pv310/Kconfig
deleted file mode 100644
index b2a9acc5185f..000000000000
--- a/arch/arm/mach-s5pv310/Kconfig
+++ /dev/null
@@ -1,151 +0,0 @@
1# arch/arm/mach-s5pv310/Kconfig
2#
3# Copyright (c) 2010 Samsung Electronics Co., Ltd.
4# http://www.samsung.com/
5#
6# Licensed under GPLv2
7
8# Configuration options for the S5PV310
9
10if ARCH_S5PV310
11
12config CPU_S5PV310
13 bool
14 select S3C_PL330_DMA
15 help
16 Enable S5PV310 CPU support
17
18config S5PV310_DEV_PD
19 bool
20 help
21 Compile in platform device definitions for Power Domain
22
23config S5PV310_SETUP_I2C1
24 bool
25 help
26 Common setup code for i2c bus 1.
27
28config S5PV310_SETUP_I2C2
29 bool
30 help
31 Common setup code for i2c bus 2.
32
33config S5PV310_SETUP_I2C3
34 bool
35 help
36 Common setup code for i2c bus 3.
37
38config S5PV310_SETUP_I2C4
39 bool
40 help
41 Common setup code for i2c bus 4.
42
43config S5PV310_SETUP_I2C5
44 bool
45 help
46 Common setup code for i2c bus 5.
47
48config S5PV310_SETUP_I2C6
49 bool
50 help
51 Common setup code for i2c bus 6.
52
53config S5PV310_SETUP_I2C7
54 bool
55 help
56 Common setup code for i2c bus 7.
57
58config S5PV310_SETUP_SDHCI
59 bool
60 select S5PV310_SETUP_SDHCI_GPIO
61 help
62 Internal helper functions for S5PV310 based SDHCI systems.
63
64config S5PV310_SETUP_SDHCI_GPIO
65 bool
66 help
67 Common setup code for SDHCI gpio.
68
69config S5PV310_DEV_SYSMMU
70 bool
71 help
72 Common setup code for SYSTEM MMU in S5PV310
73
74# machine support
75
76menu "S5PC210 Machines"
77
78config MACH_SMDKC210
79 bool "SMDKC210"
80 select CPU_S5PV310
81 select S3C_DEV_RTC
82 select S3C_DEV_WDT
83 select S3C_DEV_I2C1
84 select S3C_DEV_HSMMC
85 select S3C_DEV_HSMMC1
86 select S3C_DEV_HSMMC2
87 select S3C_DEV_HSMMC3
88 select S5PV310_DEV_PD
89 select S5PV310_SETUP_I2C1
90 select S5PV310_SETUP_SDHCI
91 select S5PV310_DEV_SYSMMU
92 help
93 Machine support for Samsung SMDKC210
94 S5PC210(MCP) is one of package option of S5PV310
95
96config MACH_UNIVERSAL_C210
97 bool "Mobile UNIVERSAL_C210 Board"
98 select CPU_S5PV310
99 select S5P_DEV_ONENAND
100 select S3C_DEV_HSMMC
101 select S3C_DEV_HSMMC2
102 select S3C_DEV_HSMMC3
103 select S5PV310_SETUP_SDHCI
104 select S3C_DEV_I2C1
105 select S5PV310_SETUP_I2C1
106 help
107 Machine support for Samsung Mobile Universal S5PC210 Reference
108 Board. S5PC210(MCP) is one of package option of S5PV310
109
110endmenu
111
112menu "S5PV310 Machines"
113
114config MACH_SMDKV310
115 bool "SMDKV310"
116 select CPU_S5PV310
117 select S3C_DEV_RTC
118 select S3C_DEV_WDT
119 select S3C_DEV_I2C1
120 select S3C_DEV_HSMMC
121 select S3C_DEV_HSMMC1
122 select S3C_DEV_HSMMC2
123 select S3C_DEV_HSMMC3
124 select S5PV310_DEV_PD
125 select S5PV310_DEV_SYSMMU
126 select S5PV310_SETUP_I2C1
127 select S5PV310_SETUP_SDHCI
128 help
129 Machine support for Samsung SMDKV310
130
131endmenu
132
133comment "Configuration for HSMMC bus width"
134
135menu "Use 8-bit bus width"
136
137config S5PV310_SDHCI_CH0_8BIT
138 bool "Channel 0 with 8-bit bus"
139 help
140 Support HSMMC Channel 0 8-bit bus.
141 If selected, Channel 1 is disabled.
142
143config S5PV310_SDHCI_CH2_8BIT
144 bool "Channel 2 with 8-bit bus"
145 help
146 Support HSMMC Channel 2 8-bit bus.
147 If selected, Channel 3 is disabled.
148
149endmenu
150
151endif
diff --git a/arch/arm/mach-s5pv310/Makefile b/arch/arm/mach-s5pv310/Makefile
deleted file mode 100644
index 036fb383b830..000000000000
--- a/arch/arm/mach-s5pv310/Makefile
+++ /dev/null
@@ -1,43 +0,0 @@
1# arch/arm/mach-s5pv310/Makefile
2#
3# Copyright (c) 2010 Samsung Electronics Co., Ltd.
4# http://www.samsung.com/
5#
6# Licensed under GPLv2
7
8obj-y :=
9obj-m :=
10obj-n :=
11obj- :=
12
13# Core support for S5PV310 system
14
15obj-$(CONFIG_CPU_S5PV310) += cpu.o init.o clock.o irq-combiner.o
16obj-$(CONFIG_CPU_S5PV310) += setup-i2c0.o time.o gpiolib.o irq-eint.o dma.o
17obj-$(CONFIG_CPU_FREQ) += cpufreq.o
18
19obj-$(CONFIG_SMP) += platsmp.o headsmp.o
20obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
21obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
22
23# machine support
24
25obj-$(CONFIG_MACH_SMDKC210) += mach-smdkc210.o
26obj-$(CONFIG_MACH_SMDKV310) += mach-smdkv310.o
27obj-$(CONFIG_MACH_UNIVERSAL_C210) += mach-universal_c210.o
28
29# device support
30
31obj-y += dev-audio.o
32obj-$(CONFIG_S5PV310_DEV_PD) += dev-pd.o
33obj-$(CONFIG_S5PV310_DEV_SYSMMU) += dev-sysmmu.o
34
35obj-$(CONFIG_S5PV310_SETUP_I2C1) += setup-i2c1.o
36obj-$(CONFIG_S5PV310_SETUP_I2C2) += setup-i2c2.o
37obj-$(CONFIG_S5PV310_SETUP_I2C3) += setup-i2c3.o
38obj-$(CONFIG_S5PV310_SETUP_I2C4) += setup-i2c4.o
39obj-$(CONFIG_S5PV310_SETUP_I2C5) += setup-i2c5.o
40obj-$(CONFIG_S5PV310_SETUP_I2C6) += setup-i2c6.o
41obj-$(CONFIG_S5PV310_SETUP_I2C7) += setup-i2c7.o
42obj-$(CONFIG_S5PV310_SETUP_SDHCI) += setup-sdhci.o
43obj-$(CONFIG_S5PV310_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
diff --git a/arch/arm/mach-s5pv310/gpiolib.c b/arch/arm/mach-s5pv310/gpiolib.c
deleted file mode 100644
index 55217b8923ec..000000000000
--- a/arch/arm/mach-s5pv310/gpiolib.c
+++ /dev/null
@@ -1,304 +0,0 @@
1/* linux/arch/arm/mach-s5pv310/gpiolib.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5PV310 - GPIOlib support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/irq.h>
15#include <linux/io.h>
16#include <linux/gpio.h>
17
18#include <mach/map.h>
19
20#include <plat/gpio-core.h>
21#include <plat/gpio-cfg.h>
22#include <plat/gpio-cfg-helpers.h>
23
24static struct s3c_gpio_cfg gpio_cfg = {
25 .set_config = s3c_gpio_setcfg_s3c64xx_4bit,
26 .set_pull = s3c_gpio_setpull_updown,
27 .get_pull = s3c_gpio_getpull_updown,
28};
29
30static struct s3c_gpio_cfg gpio_cfg_noint = {
31 .set_config = s3c_gpio_setcfg_s3c64xx_4bit,
32 .set_pull = s3c_gpio_setpull_updown,
33 .get_pull = s3c_gpio_getpull_updown,
34};
35
36/*
37 * Following are the gpio banks in v310.
38 *
39 * The 'config' member when left to NULL, is initialized to the default
40 * structure gpio_cfg in the init function below.
41 *
42 * The 'base' member is also initialized in the init function below.
43 * Note: The initialization of 'base' member of s3c_gpio_chip structure
44 * uses the above macro and depends on the banks being listed in order here.
45 */
46static struct s3c_gpio_chip s5pv310_gpio_part1_4bit[] = {
47 {
48 .chip = {
49 .base = S5PV310_GPA0(0),
50 .ngpio = S5PV310_GPIO_A0_NR,
51 .label = "GPA0",
52 },
53 }, {
54 .chip = {
55 .base = S5PV310_GPA1(0),
56 .ngpio = S5PV310_GPIO_A1_NR,
57 .label = "GPA1",
58 },
59 }, {
60 .chip = {
61 .base = S5PV310_GPB(0),
62 .ngpio = S5PV310_GPIO_B_NR,
63 .label = "GPB",
64 },
65 }, {
66 .chip = {
67 .base = S5PV310_GPC0(0),
68 .ngpio = S5PV310_GPIO_C0_NR,
69 .label = "GPC0",
70 },
71 }, {
72 .chip = {
73 .base = S5PV310_GPC1(0),
74 .ngpio = S5PV310_GPIO_C1_NR,
75 .label = "GPC1",
76 },
77 }, {
78 .chip = {
79 .base = S5PV310_GPD0(0),
80 .ngpio = S5PV310_GPIO_D0_NR,
81 .label = "GPD0",
82 },
83 }, {
84 .chip = {
85 .base = S5PV310_GPD1(0),
86 .ngpio = S5PV310_GPIO_D1_NR,
87 .label = "GPD1",
88 },
89 }, {
90 .chip = {
91 .base = S5PV310_GPE0(0),
92 .ngpio = S5PV310_GPIO_E0_NR,
93 .label = "GPE0",
94 },
95 }, {
96 .chip = {
97 .base = S5PV310_GPE1(0),
98 .ngpio = S5PV310_GPIO_E1_NR,
99 .label = "GPE1",
100 },
101 }, {
102 .chip = {
103 .base = S5PV310_GPE2(0),
104 .ngpio = S5PV310_GPIO_E2_NR,
105 .label = "GPE2",
106 },
107 }, {
108 .chip = {
109 .base = S5PV310_GPE3(0),
110 .ngpio = S5PV310_GPIO_E3_NR,
111 .label = "GPE3",
112 },
113 }, {
114 .chip = {
115 .base = S5PV310_GPE4(0),
116 .ngpio = S5PV310_GPIO_E4_NR,
117 .label = "GPE4",
118 },
119 }, {
120 .chip = {
121 .base = S5PV310_GPF0(0),
122 .ngpio = S5PV310_GPIO_F0_NR,
123 .label = "GPF0",
124 },
125 }, {
126 .chip = {
127 .base = S5PV310_GPF1(0),
128 .ngpio = S5PV310_GPIO_F1_NR,
129 .label = "GPF1",
130 },
131 }, {
132 .chip = {
133 .base = S5PV310_GPF2(0),
134 .ngpio = S5PV310_GPIO_F2_NR,
135 .label = "GPF2",
136 },
137 }, {
138 .chip = {
139 .base = S5PV310_GPF3(0),
140 .ngpio = S5PV310_GPIO_F3_NR,
141 .label = "GPF3",
142 },
143 },
144};
145
146static struct s3c_gpio_chip s5pv310_gpio_part2_4bit[] = {
147 {
148 .chip = {
149 .base = S5PV310_GPJ0(0),
150 .ngpio = S5PV310_GPIO_J0_NR,
151 .label = "GPJ0",
152 },
153 }, {
154 .chip = {
155 .base = S5PV310_GPJ1(0),
156 .ngpio = S5PV310_GPIO_J1_NR,
157 .label = "GPJ1",
158 },
159 }, {
160 .chip = {
161 .base = S5PV310_GPK0(0),
162 .ngpio = S5PV310_GPIO_K0_NR,
163 .label = "GPK0",
164 },
165 }, {
166 .chip = {
167 .base = S5PV310_GPK1(0),
168 .ngpio = S5PV310_GPIO_K1_NR,
169 .label = "GPK1",
170 },
171 }, {
172 .chip = {
173 .base = S5PV310_GPK2(0),
174 .ngpio = S5PV310_GPIO_K2_NR,
175 .label = "GPK2",
176 },
177 }, {
178 .chip = {
179 .base = S5PV310_GPK3(0),
180 .ngpio = S5PV310_GPIO_K3_NR,
181 .label = "GPK3",
182 },
183 }, {
184 .chip = {
185 .base = S5PV310_GPL0(0),
186 .ngpio = S5PV310_GPIO_L0_NR,
187 .label = "GPL0",
188 },
189 }, {
190 .chip = {
191 .base = S5PV310_GPL1(0),
192 .ngpio = S5PV310_GPIO_L1_NR,
193 .label = "GPL1",
194 },
195 }, {
196 .chip = {
197 .base = S5PV310_GPL2(0),
198 .ngpio = S5PV310_GPIO_L2_NR,
199 .label = "GPL2",
200 },
201 }, {
202 .base = (S5P_VA_GPIO2 + 0xC00),
203 .config = &gpio_cfg_noint,
204 .irq_base = IRQ_EINT(0),
205 .chip = {
206 .base = S5PV310_GPX0(0),
207 .ngpio = S5PV310_GPIO_X0_NR,
208 .label = "GPX0",
209 .to_irq = samsung_gpiolib_to_irq,
210 },
211 }, {
212 .base = (S5P_VA_GPIO2 + 0xC20),
213 .config = &gpio_cfg_noint,
214 .irq_base = IRQ_EINT(8),
215 .chip = {
216 .base = S5PV310_GPX1(0),
217 .ngpio = S5PV310_GPIO_X1_NR,
218 .label = "GPX1",
219 .to_irq = samsung_gpiolib_to_irq,
220 },
221 }, {
222 .base = (S5P_VA_GPIO2 + 0xC40),
223 .config = &gpio_cfg_noint,
224 .irq_base = IRQ_EINT(16),
225 .chip = {
226 .base = S5PV310_GPX2(0),
227 .ngpio = S5PV310_GPIO_X2_NR,
228 .label = "GPX2",
229 .to_irq = samsung_gpiolib_to_irq,
230 },
231 }, {
232 .base = (S5P_VA_GPIO2 + 0xC60),
233 .config = &gpio_cfg_noint,
234 .irq_base = IRQ_EINT(24),
235 .chip = {
236 .base = S5PV310_GPX3(0),
237 .ngpio = S5PV310_GPIO_X3_NR,
238 .label = "GPX3",
239 .to_irq = samsung_gpiolib_to_irq,
240 },
241 },
242};
243
244static struct s3c_gpio_chip s5pv310_gpio_part3_4bit[] = {
245 {
246 .chip = {
247 .base = S5PV310_GPZ(0),
248 .ngpio = S5PV310_GPIO_Z_NR,
249 .label = "GPZ",
250 },
251 },
252};
253
254static __init int s5pv310_gpiolib_init(void)
255{
256 struct s3c_gpio_chip *chip;
257 int i;
258 int nr_chips;
259
260 /* GPIO part 1 */
261
262 chip = s5pv310_gpio_part1_4bit;
263 nr_chips = ARRAY_SIZE(s5pv310_gpio_part1_4bit);
264
265 for (i = 0; i < nr_chips; i++, chip++) {
266 if (chip->config == NULL)
267 chip->config = &gpio_cfg;
268 if (chip->base == NULL)
269 chip->base = S5P_VA_GPIO1 + (i) * 0x20;
270 }
271
272 samsung_gpiolib_add_4bit_chips(s5pv310_gpio_part1_4bit, nr_chips);
273
274 /* GPIO part 2 */
275
276 chip = s5pv310_gpio_part2_4bit;
277 nr_chips = ARRAY_SIZE(s5pv310_gpio_part2_4bit);
278
279 for (i = 0; i < nr_chips; i++, chip++) {
280 if (chip->config == NULL)
281 chip->config = &gpio_cfg;
282 if (chip->base == NULL)
283 chip->base = S5P_VA_GPIO2 + (i) * 0x20;
284 }
285
286 samsung_gpiolib_add_4bit_chips(s5pv310_gpio_part2_4bit, nr_chips);
287
288 /* GPIO part 3 */
289
290 chip = s5pv310_gpio_part3_4bit;
291 nr_chips = ARRAY_SIZE(s5pv310_gpio_part3_4bit);
292
293 for (i = 0; i < nr_chips; i++, chip++) {
294 if (chip->config == NULL)
295 chip->config = &gpio_cfg;
296 if (chip->base == NULL)
297 chip->base = S5P_VA_GPIO3 + (i) * 0x20;
298 }
299
300 samsung_gpiolib_add_4bit_chips(s5pv310_gpio_part3_4bit, nr_chips);
301
302 return 0;
303}
304core_initcall(s5pv310_gpiolib_init);
diff --git a/arch/arm/mach-s5pv310/include/mach/gpio.h b/arch/arm/mach-s5pv310/include/mach/gpio.h
deleted file mode 100644
index 20cb80c23466..000000000000
--- a/arch/arm/mach-s5pv310/include/mach/gpio.h
+++ /dev/null
@@ -1,135 +0,0 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/gpio.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5PV310 - GPIO lib support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_GPIO_H
14#define __ASM_ARCH_GPIO_H __FILE__
15
16#define gpio_get_value __gpio_get_value
17#define gpio_set_value __gpio_set_value
18#define gpio_cansleep __gpio_cansleep
19#define gpio_to_irq __gpio_to_irq
20
21/* Practically, GPIO banks upto GPZ are the configurable gpio banks */
22
23/* GPIO bank sizes */
24#define S5PV310_GPIO_A0_NR (8)
25#define S5PV310_GPIO_A1_NR (6)
26#define S5PV310_GPIO_B_NR (8)
27#define S5PV310_GPIO_C0_NR (5)
28#define S5PV310_GPIO_C1_NR (5)
29#define S5PV310_GPIO_D0_NR (4)
30#define S5PV310_GPIO_D1_NR (4)
31#define S5PV310_GPIO_E0_NR (5)
32#define S5PV310_GPIO_E1_NR (8)
33#define S5PV310_GPIO_E2_NR (6)
34#define S5PV310_GPIO_E3_NR (8)
35#define S5PV310_GPIO_E4_NR (8)
36#define S5PV310_GPIO_F0_NR (8)
37#define S5PV310_GPIO_F1_NR (8)
38#define S5PV310_GPIO_F2_NR (8)
39#define S5PV310_GPIO_F3_NR (6)
40#define S5PV310_GPIO_J0_NR (8)
41#define S5PV310_GPIO_J1_NR (5)
42#define S5PV310_GPIO_K0_NR (7)
43#define S5PV310_GPIO_K1_NR (7)
44#define S5PV310_GPIO_K2_NR (7)
45#define S5PV310_GPIO_K3_NR (7)
46#define S5PV310_GPIO_L0_NR (8)
47#define S5PV310_GPIO_L1_NR (3)
48#define S5PV310_GPIO_L2_NR (8)
49#define S5PV310_GPIO_X0_NR (8)
50#define S5PV310_GPIO_X1_NR (8)
51#define S5PV310_GPIO_X2_NR (8)
52#define S5PV310_GPIO_X3_NR (8)
53#define S5PV310_GPIO_Z_NR (7)
54
55/* GPIO bank numbers */
56
57#define S5PV310_GPIO_NEXT(__gpio) \
58 ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
59
60enum s5p_gpio_number {
61 S5PV310_GPIO_A0_START = 0,
62 S5PV310_GPIO_A1_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_A0),
63 S5PV310_GPIO_B_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_A1),
64 S5PV310_GPIO_C0_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_B),
65 S5PV310_GPIO_C1_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_C0),
66 S5PV310_GPIO_D0_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_C1),
67 S5PV310_GPIO_D1_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_D0),
68 S5PV310_GPIO_E0_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_D1),
69 S5PV310_GPIO_E1_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_E0),
70 S5PV310_GPIO_E2_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_E1),
71 S5PV310_GPIO_E3_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_E2),
72 S5PV310_GPIO_E4_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_E3),
73 S5PV310_GPIO_F0_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_E4),
74 S5PV310_GPIO_F1_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_F0),
75 S5PV310_GPIO_F2_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_F1),
76 S5PV310_GPIO_F3_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_F2),
77 S5PV310_GPIO_J0_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_F3),
78 S5PV310_GPIO_J1_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_J0),
79 S5PV310_GPIO_K0_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_J1),
80 S5PV310_GPIO_K1_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_K0),
81 S5PV310_GPIO_K2_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_K1),
82 S5PV310_GPIO_K3_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_K2),
83 S5PV310_GPIO_L0_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_K3),
84 S5PV310_GPIO_L1_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_L0),
85 S5PV310_GPIO_L2_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_L1),
86 S5PV310_GPIO_X0_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_L2),
87 S5PV310_GPIO_X1_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_X0),
88 S5PV310_GPIO_X2_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_X1),
89 S5PV310_GPIO_X3_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_X2),
90 S5PV310_GPIO_Z_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_X3),
91};
92
93/* S5PV310 GPIO number definitions */
94#define S5PV310_GPA0(_nr) (S5PV310_GPIO_A0_START + (_nr))
95#define S5PV310_GPA1(_nr) (S5PV310_GPIO_A1_START + (_nr))
96#define S5PV310_GPB(_nr) (S5PV310_GPIO_B_START + (_nr))
97#define S5PV310_GPC0(_nr) (S5PV310_GPIO_C0_START + (_nr))
98#define S5PV310_GPC1(_nr) (S5PV310_GPIO_C1_START + (_nr))
99#define S5PV310_GPD0(_nr) (S5PV310_GPIO_D0_START + (_nr))
100#define S5PV310_GPD1(_nr) (S5PV310_GPIO_D1_START + (_nr))
101#define S5PV310_GPE0(_nr) (S5PV310_GPIO_E0_START + (_nr))
102#define S5PV310_GPE1(_nr) (S5PV310_GPIO_E1_START + (_nr))
103#define S5PV310_GPE2(_nr) (S5PV310_GPIO_E2_START + (_nr))
104#define S5PV310_GPE3(_nr) (S5PV310_GPIO_E3_START + (_nr))
105#define S5PV310_GPE4(_nr) (S5PV310_GPIO_E4_START + (_nr))
106#define S5PV310_GPF0(_nr) (S5PV310_GPIO_F0_START + (_nr))
107#define S5PV310_GPF1(_nr) (S5PV310_GPIO_F1_START + (_nr))
108#define S5PV310_GPF2(_nr) (S5PV310_GPIO_F2_START + (_nr))
109#define S5PV310_GPF3(_nr) (S5PV310_GPIO_F3_START + (_nr))
110#define S5PV310_GPJ0(_nr) (S5PV310_GPIO_J0_START + (_nr))
111#define S5PV310_GPJ1(_nr) (S5PV310_GPIO_J1_START + (_nr))
112#define S5PV310_GPK0(_nr) (S5PV310_GPIO_K0_START + (_nr))
113#define S5PV310_GPK1(_nr) (S5PV310_GPIO_K1_START + (_nr))
114#define S5PV310_GPK2(_nr) (S5PV310_GPIO_K2_START + (_nr))
115#define S5PV310_GPK3(_nr) (S5PV310_GPIO_K3_START + (_nr))
116#define S5PV310_GPL0(_nr) (S5PV310_GPIO_L0_START + (_nr))
117#define S5PV310_GPL1(_nr) (S5PV310_GPIO_L1_START + (_nr))
118#define S5PV310_GPL2(_nr) (S5PV310_GPIO_L2_START + (_nr))
119#define S5PV310_GPX0(_nr) (S5PV310_GPIO_X0_START + (_nr))
120#define S5PV310_GPX1(_nr) (S5PV310_GPIO_X1_START + (_nr))
121#define S5PV310_GPX2(_nr) (S5PV310_GPIO_X2_START + (_nr))
122#define S5PV310_GPX3(_nr) (S5PV310_GPIO_X3_START + (_nr))
123#define S5PV310_GPZ(_nr) (S5PV310_GPIO_Z_START + (_nr))
124
125/* the end of the S5PV310 specific gpios */
126#define S5PV310_GPIO_END (S5PV310_GPZ(S5PV310_GPIO_Z_NR) + 1)
127#define S3C_GPIO_END S5PV310_GPIO_END
128
129/* define the number of gpios we need to the one after the GPZ() range */
130#define ARCH_NR_GPIOS (S5PV310_GPZ(S5PV310_GPIO_Z_NR) + \
131 CONFIG_SAMSUNG_GPIO_EXTRA + 1)
132
133#include <asm-generic/gpio.h>
134
135#endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/map.h b/arch/arm/mach-s5pv310/include/mach/map.h
deleted file mode 100644
index 901657fa7a12..000000000000
--- a/arch/arm/mach-s5pv310/include/mach/map.h
+++ /dev/null
@@ -1,144 +0,0 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/map.h
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5PV310 - Memory map definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_MAP_H
14#define __ASM_ARCH_MAP_H __FILE__
15
16#include <plat/map-base.h>
17
18/*
19 * S5PV310 UART offset is 0x10000 but the older S5P SoCs are 0x400.
20 * So need to define it, and here is to avoid redefinition warning.
21 */
22#define S3C_UART_OFFSET (0x10000)
23
24#include <plat/map-s5p.h>
25
26#define S5PV310_PA_SYSRAM 0x02025000
27
28#define S5PV310_PA_I2S0 0x03830000
29#define S5PV310_PA_I2S1 0xE3100000
30#define S5PV310_PA_I2S2 0xE2A00000
31
32#define S5PV310_PA_PCM0 0x03840000
33#define S5PV310_PA_PCM1 0x13980000
34#define S5PV310_PA_PCM2 0x13990000
35
36#define S5PV310_PA_SROM_BANK(x) (0x04000000 + ((x) * 0x01000000))
37
38#define S5PC210_PA_ONENAND 0x0C000000
39#define S5PC210_PA_ONENAND_DMA 0x0C600000
40
41#define S5PV310_PA_CHIPID 0x10000000
42
43#define S5PV310_PA_SYSCON 0x10010000
44#define S5PV310_PA_PMU 0x10020000
45#define S5PV310_PA_CMU 0x10030000
46
47#define S5PV310_PA_WATCHDOG 0x10060000
48#define S5PV310_PA_RTC 0x10070000
49
50#define S5PV310_PA_DMC0 0x10400000
51
52#define S5PV310_PA_COMBINER 0x10448000
53
54#define S5PV310_PA_COREPERI 0x10500000
55#define S5PV310_PA_GIC_CPU 0x10500100
56#define S5PV310_PA_TWD 0x10500600
57#define S5PV310_PA_GIC_DIST 0x10501000
58#define S5PV310_PA_L2CC 0x10502000
59
60#define S5PV310_PA_MDMA 0x10810000
61#define S5PV310_PA_PDMA0 0x12680000
62#define S5PV310_PA_PDMA1 0x12690000
63
64#define S5PV310_PA_SYSMMU_MDMA 0x10A40000
65#define S5PV310_PA_SYSMMU_SSS 0x10A50000
66#define S5PV310_PA_SYSMMU_FIMC0 0x11A20000
67#define S5PV310_PA_SYSMMU_FIMC1 0x11A30000
68#define S5PV310_PA_SYSMMU_FIMC2 0x11A40000
69#define S5PV310_PA_SYSMMU_FIMC3 0x11A50000
70#define S5PV310_PA_SYSMMU_JPEG 0x11A60000
71#define S5PV310_PA_SYSMMU_FIMD0 0x11E20000
72#define S5PV310_PA_SYSMMU_FIMD1 0x12220000
73#define S5PV310_PA_SYSMMU_PCIe 0x12620000
74#define S5PV310_PA_SYSMMU_G2D 0x12A20000
75#define S5PV310_PA_SYSMMU_ROTATOR 0x12A30000
76#define S5PV310_PA_SYSMMU_MDMA2 0x12A40000
77#define S5PV310_PA_SYSMMU_TV 0x12E20000
78#define S5PV310_PA_SYSMMU_MFC_L 0x13620000
79#define S5PV310_PA_SYSMMU_MFC_R 0x13630000
80
81#define S5PV310_PA_GPIO1 0x11400000
82#define S5PV310_PA_GPIO2 0x11000000
83#define S5PV310_PA_GPIO3 0x03860000
84
85#define S5PV310_PA_MIPI_CSIS0 0x11880000
86#define S5PV310_PA_MIPI_CSIS1 0x11890000
87
88#define S5PV310_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000))
89
90#define S5PV310_PA_SROMC 0x12570000
91
92#define S5PV310_PA_UART 0x13800000
93
94#define S5PV310_PA_IIC(x) (0x13860000 + ((x) * 0x10000))
95
96#define S5PV310_PA_AC97 0x139A0000
97
98#define S5PV310_PA_TIMER 0x139D0000
99
100#define S5PV310_PA_SDRAM 0x40000000
101
102#define S5PV310_PA_SPDIF 0xE1100000
103
104/* Compatibiltiy Defines */
105
106#define S3C_PA_HSMMC0 S5PV310_PA_HSMMC(0)
107#define S3C_PA_HSMMC1 S5PV310_PA_HSMMC(1)
108#define S3C_PA_HSMMC2 S5PV310_PA_HSMMC(2)
109#define S3C_PA_HSMMC3 S5PV310_PA_HSMMC(3)
110#define S3C_PA_IIC S5PV310_PA_IIC(0)
111#define S3C_PA_IIC1 S5PV310_PA_IIC(1)
112#define S3C_PA_IIC2 S5PV310_PA_IIC(2)
113#define S3C_PA_IIC3 S5PV310_PA_IIC(3)
114#define S3C_PA_IIC4 S5PV310_PA_IIC(4)
115#define S3C_PA_IIC5 S5PV310_PA_IIC(5)
116#define S3C_PA_IIC6 S5PV310_PA_IIC(6)
117#define S3C_PA_IIC7 S5PV310_PA_IIC(7)
118#define S3C_PA_RTC S5PV310_PA_RTC
119#define S3C_PA_WDT S5PV310_PA_WATCHDOG
120
121#define S5P_PA_CHIPID S5PV310_PA_CHIPID
122#define S5P_PA_MIPI_CSIS0 S5PV310_PA_MIPI_CSIS0
123#define S5P_PA_MIPI_CSIS1 S5PV310_PA_MIPI_CSIS1
124#define S5P_PA_ONENAND S5PC210_PA_ONENAND
125#define S5P_PA_ONENAND_DMA S5PC210_PA_ONENAND_DMA
126#define S5P_PA_SDRAM S5PV310_PA_SDRAM
127#define S5P_PA_SROMC S5PV310_PA_SROMC
128#define S5P_PA_SYSCON S5PV310_PA_SYSCON
129#define S5P_PA_TIMER S5PV310_PA_TIMER
130
131/* UART */
132
133#define S3C_PA_UART S5PV310_PA_UART
134
135#define S5P_PA_UART(x) (S3C_PA_UART + ((x) * S3C_UART_OFFSET))
136#define S5P_PA_UART0 S5P_PA_UART(0)
137#define S5P_PA_UART1 S5P_PA_UART(1)
138#define S5P_PA_UART2 S5P_PA_UART(2)
139#define S5P_PA_UART3 S5P_PA_UART(3)
140#define S5P_PA_UART4 S5P_PA_UART(4)
141
142#define S5P_SZ_UART SZ_256
143
144#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/regs-gpio.h b/arch/arm/mach-s5pv310/include/mach/regs-gpio.h
deleted file mode 100644
index 82e9e0c9d452..000000000000
--- a/arch/arm/mach-s5pv310/include/mach/regs-gpio.h
+++ /dev/null
@@ -1,42 +0,0 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/regs-gpio.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5PV310 - GPIO (including EINT) register definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_REGS_GPIO_H
14#define __ASM_ARCH_REGS_GPIO_H __FILE__
15
16#include <mach/map.h>
17#include <mach/irqs.h>
18
19#define S5PV310_EINT40CON (S5P_VA_GPIO2 + 0xE00)
20#define S5P_EINT_CON(x) (S5PV310_EINT40CON + ((x) * 0x4))
21
22#define S5PV310_EINT40FLTCON0 (S5P_VA_GPIO2 + 0xE80)
23#define S5P_EINT_FLTCON(x) (S5PV310_EINT40FLTCON0 + ((x) * 0x4))
24
25#define S5PV310_EINT40MASK (S5P_VA_GPIO2 + 0xF00)
26#define S5P_EINT_MASK(x) (S5PV310_EINT40MASK + ((x) * 0x4))
27
28#define S5PV310_EINT40PEND (S5P_VA_GPIO2 + 0xF40)
29#define S5P_EINT_PEND(x) (S5PV310_EINT40PEND + ((x) * 0x4))
30
31#define EINT_REG_NR(x) (EINT_OFFSET(x) >> 3)
32
33#define eint_irq_to_bit(irq) (1 << (EINT_OFFSET(irq) & 0x7))
34
35#define EINT_MODE S3C_GPIO_SFN(0xf)
36
37#define EINT_GPIO_0(x) S5PV310_GPX0(x)
38#define EINT_GPIO_1(x) S5PV310_GPX1(x)
39#define EINT_GPIO_2(x) S5PV310_GPX2(x)
40#define EINT_GPIO_3(x) S5PV310_GPX3(x)
41
42#endif /* __ASM_ARCH_REGS_GPIO_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/regs-pmu.h b/arch/arm/mach-s5pv310/include/mach/regs-pmu.h
deleted file mode 100644
index fb333d0f6073..000000000000
--- a/arch/arm/mach-s5pv310/include/mach/regs-pmu.h
+++ /dev/null
@@ -1,30 +0,0 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/regs-pmu.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5PV310 - Power management unit definition
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_REGS_PMU_H
14#define __ASM_ARCH_REGS_PMU_H __FILE__
15
16#include <mach/map.h>
17
18#define S5P_PMUREG(x) (S5P_VA_PMU + (x))
19
20#define S5P_PMU_CAM_CONF S5P_PMUREG(0x3C00)
21#define S5P_PMU_TV_CONF S5P_PMUREG(0x3C20)
22#define S5P_PMU_MFC_CONF S5P_PMUREG(0x3C40)
23#define S5P_PMU_G3D_CONF S5P_PMUREG(0x3C60)
24#define S5P_PMU_LCD0_CONF S5P_PMUREG(0x3C80)
25#define S5P_PMU_LCD1_CONF S5P_PMUREG(0x3CA0)
26#define S5P_PMU_GPS_CONF S5P_PMUREG(0x3CE0)
27
28#define S5P_INT_LOCAL_PWR_EN 0x7
29
30#endif /* __ASM_ARCH_REGS_PMU_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/sysmmu.h b/arch/arm/mach-s5pv310/include/mach/sysmmu.h
deleted file mode 100644
index 598fc5c9211b..000000000000
--- a/arch/arm/mach-s5pv310/include/mach/sysmmu.h
+++ /dev/null
@@ -1,122 +0,0 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/sysmmu.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * Samsung sysmmu driver for S5PV310
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARM_ARCH_SYSMMU_H
14#define __ASM_ARM_ARCH_SYSMMU_H __FILE__
15
16#define S5PV310_SYSMMU_TOTAL_IPNUM 16
17#define S5P_SYSMMU_TOTAL_IPNUM S5PV310_SYSMMU_TOTAL_IPNUM
18
19enum s5pv310_sysmmu_ips {
20 SYSMMU_MDMA,
21 SYSMMU_SSS,
22 SYSMMU_FIMC0,
23 SYSMMU_FIMC1,
24 SYSMMU_FIMC2,
25 SYSMMU_FIMC3,
26 SYSMMU_JPEG,
27 SYSMMU_FIMD0,
28 SYSMMU_FIMD1,
29 SYSMMU_PCIe,
30 SYSMMU_G2D,
31 SYSMMU_ROTATOR,
32 SYSMMU_MDMA2,
33 SYSMMU_TV,
34 SYSMMU_MFC_L,
35 SYSMMU_MFC_R,
36};
37
38static char *sysmmu_ips_name[S5PV310_SYSMMU_TOTAL_IPNUM] = {
39 "SYSMMU_MDMA" ,
40 "SYSMMU_SSS" ,
41 "SYSMMU_FIMC0" ,
42 "SYSMMU_FIMC1" ,
43 "SYSMMU_FIMC2" ,
44 "SYSMMU_FIMC3" ,
45 "SYSMMU_JPEG" ,
46 "SYSMMU_FIMD0" ,
47 "SYSMMU_FIMD1" ,
48 "SYSMMU_PCIe" ,
49 "SYSMMU_G2D" ,
50 "SYSMMU_ROTATOR",
51 "SYSMMU_MDMA2" ,
52 "SYSMMU_TV" ,
53 "SYSMMU_MFC_L" ,
54 "SYSMMU_MFC_R" ,
55};
56
57typedef enum s5pv310_sysmmu_ips sysmmu_ips;
58
59struct sysmmu_tt_info {
60 unsigned long *pgd;
61 unsigned long pgd_paddr;
62 unsigned long *pte;
63};
64
65struct sysmmu_controller {
66 const char *name;
67
68 /* channels registers */
69 void __iomem *regs;
70
71 /* channel irq */
72 unsigned int irq;
73
74 sysmmu_ips ips;
75
76 /* Translation Table Info. */
77 struct sysmmu_tt_info *tt_info;
78
79 struct resource *mem;
80 struct device *dev;
81
82 /* SysMMU controller enable - true : enable */
83 bool enable;
84};
85
86/**
87 * s5p_sysmmu_enable() - enable system mmu of ip
88 * @ips: The ip connected system mmu.
89 *
90 * This function enable system mmu to transfer address
91 * from virtual address to physical address
92 */
93int s5p_sysmmu_enable(sysmmu_ips ips);
94
95/**
96 * s5p_sysmmu_disable() - disable sysmmu mmu of ip
97 * @ips: The ip connected system mmu.
98 *
99 * This function disable system mmu to transfer address
100 * from virtual address to physical address
101 */
102int s5p_sysmmu_disable(sysmmu_ips ips);
103
104/**
105 * s5p_sysmmu_set_tablebase_pgd() - set page table base address to refer page table
106 * @ips: The ip connected system mmu.
107 * @pgd: The page table base address.
108 *
109 * This function set page table base address
110 * When system mmu transfer address from virtaul address to physical address,
111 * system mmu refer address information from page table
112 */
113int s5p_sysmmu_set_tablebase_pgd(sysmmu_ips ips, unsigned long pgd);
114
115/**
116 * s5p_sysmmu_tlb_invalidate() - flush all TLB entry in system mmu
117 * @ips: The ip connected system mmu.
118 *
119 * This function flush all TLB entry in system mmu
120 */
121int s5p_sysmmu_tlb_invalidate(sysmmu_ips ips);
122#endif /* __ASM_ARM_ARCH_SYSMMU_H */
diff --git a/arch/arm/mach-s5pv310/mach-universal_c210.c b/arch/arm/mach-s5pv310/mach-universal_c210.c
deleted file mode 100644
index 36bc3cf825e3..000000000000
--- a/arch/arm/mach-s5pv310/mach-universal_c210.c
+++ /dev/null
@@ -1,237 +0,0 @@
1/* linux/arch/arm/mach-s5pv310/mach-universal_c210.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8*/
9
10#include <linux/platform_device.h>
11#include <linux/serial_core.h>
12#include <linux/input.h>
13#include <linux/i2c.h>
14#include <linux/gpio_keys.h>
15#include <linux/gpio.h>
16#include <linux/regulator/machine.h>
17#include <linux/regulator/fixed.h>
18#include <linux/mmc/host.h>
19
20#include <asm/mach/arch.h>
21#include <asm/mach-types.h>
22
23#include <plat/regs-serial.h>
24#include <plat/s5pv310.h>
25#include <plat/cpu.h>
26#include <plat/devs.h>
27#include <plat/sdhci.h>
28
29#include <mach/map.h>
30
31/* Following are default values for UCON, ULCON and UFCON UART registers */
32#define UNIVERSAL_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
33 S3C2410_UCON_RXILEVEL | \
34 S3C2410_UCON_TXIRQMODE | \
35 S3C2410_UCON_RXIRQMODE | \
36 S3C2410_UCON_RXFIFO_TOI | \
37 S3C2443_UCON_RXERR_IRQEN)
38
39#define UNIVERSAL_ULCON_DEFAULT S3C2410_LCON_CS8
40
41#define UNIVERSAL_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
42 S5PV210_UFCON_TXTRIG256 | \
43 S5PV210_UFCON_RXTRIG256)
44
45static struct s3c2410_uartcfg universal_uartcfgs[] __initdata = {
46 [0] = {
47 .hwport = 0,
48 .ucon = UNIVERSAL_UCON_DEFAULT,
49 .ulcon = UNIVERSAL_ULCON_DEFAULT,
50 .ufcon = UNIVERSAL_UFCON_DEFAULT,
51 },
52 [1] = {
53 .hwport = 1,
54 .ucon = UNIVERSAL_UCON_DEFAULT,
55 .ulcon = UNIVERSAL_ULCON_DEFAULT,
56 .ufcon = UNIVERSAL_UFCON_DEFAULT,
57 },
58 [2] = {
59 .hwport = 2,
60 .ucon = UNIVERSAL_UCON_DEFAULT,
61 .ulcon = UNIVERSAL_ULCON_DEFAULT,
62 .ufcon = UNIVERSAL_UFCON_DEFAULT,
63 },
64 [3] = {
65 .hwport = 3,
66 .ucon = UNIVERSAL_UCON_DEFAULT,
67 .ulcon = UNIVERSAL_ULCON_DEFAULT,
68 .ufcon = UNIVERSAL_UFCON_DEFAULT,
69 },
70};
71
72static struct gpio_keys_button universal_gpio_keys_tables[] = {
73 {
74 .code = KEY_VOLUMEUP,
75 .gpio = S5PV310_GPX2(0), /* XEINT16 */
76 .desc = "gpio-keys: KEY_VOLUMEUP",
77 .type = EV_KEY,
78 .active_low = 1,
79 .debounce_interval = 1,
80 }, {
81 .code = KEY_VOLUMEDOWN,
82 .gpio = S5PV310_GPX2(1), /* XEINT17 */
83 .desc = "gpio-keys: KEY_VOLUMEDOWN",
84 .type = EV_KEY,
85 .active_low = 1,
86 .debounce_interval = 1,
87 }, {
88 .code = KEY_CONFIG,
89 .gpio = S5PV310_GPX2(2), /* XEINT18 */
90 .desc = "gpio-keys: KEY_CONFIG",
91 .type = EV_KEY,
92 .active_low = 1,
93 .debounce_interval = 1,
94 }, {
95 .code = KEY_CAMERA,
96 .gpio = S5PV310_GPX2(3), /* XEINT19 */
97 .desc = "gpio-keys: KEY_CAMERA",
98 .type = EV_KEY,
99 .active_low = 1,
100 .debounce_interval = 1,
101 }, {
102 .code = KEY_OK,
103 .gpio = S5PV310_GPX3(5), /* XEINT29 */
104 .desc = "gpio-keys: KEY_OK",
105 .type = EV_KEY,
106 .active_low = 1,
107 .debounce_interval = 1,
108 },
109};
110
111static struct gpio_keys_platform_data universal_gpio_keys_data = {
112 .buttons = universal_gpio_keys_tables,
113 .nbuttons = ARRAY_SIZE(universal_gpio_keys_tables),
114};
115
116static struct platform_device universal_gpio_keys = {
117 .name = "gpio-keys",
118 .dev = {
119 .platform_data = &universal_gpio_keys_data,
120 },
121};
122
123/* eMMC */
124static struct s3c_sdhci_platdata universal_hsmmc0_data __initdata = {
125 .max_width = 8,
126 .host_caps = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
127 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
128 MMC_CAP_DISABLE),
129 .cd_type = S3C_SDHCI_CD_PERMANENT,
130 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
131};
132
133static struct regulator_consumer_supply mmc0_supplies[] = {
134 REGULATOR_SUPPLY("vmmc", "s3c-sdhci.0"),
135};
136
137static struct regulator_init_data mmc0_fixed_voltage_init_data = {
138 .constraints = {
139 .name = "VMEM_VDD_2.8V",
140 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
141 },
142 .num_consumer_supplies = ARRAY_SIZE(mmc0_supplies),
143 .consumer_supplies = mmc0_supplies,
144};
145
146static struct fixed_voltage_config mmc0_fixed_voltage_config = {
147 .supply_name = "MASSMEMORY_EN",
148 .microvolts = 2800000,
149 .gpio = S5PV310_GPE1(3),
150 .enable_high = true,
151 .init_data = &mmc0_fixed_voltage_init_data,
152};
153
154static struct platform_device mmc0_fixed_voltage = {
155 .name = "reg-fixed-voltage",
156 .id = 0,
157 .dev = {
158 .platform_data = &mmc0_fixed_voltage_config,
159 },
160};
161
162/* SD */
163static struct s3c_sdhci_platdata universal_hsmmc2_data __initdata = {
164 .max_width = 4,
165 .host_caps = MMC_CAP_4_BIT_DATA |
166 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
167 MMC_CAP_DISABLE,
168 .ext_cd_gpio = S5PV310_GPX3(4), /* XEINT_28 */
169 .ext_cd_gpio_invert = 1,
170 .cd_type = S3C_SDHCI_CD_GPIO,
171 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
172};
173
174/* WiFi */
175static struct s3c_sdhci_platdata universal_hsmmc3_data __initdata = {
176 .max_width = 4,
177 .host_caps = MMC_CAP_4_BIT_DATA |
178 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
179 MMC_CAP_DISABLE,
180 .cd_type = S3C_SDHCI_CD_EXTERNAL,
181};
182
183static void __init universal_sdhci_init(void)
184{
185 s3c_sdhci0_set_platdata(&universal_hsmmc0_data);
186 s3c_sdhci2_set_platdata(&universal_hsmmc2_data);
187 s3c_sdhci3_set_platdata(&universal_hsmmc3_data);
188}
189
190/* I2C0 */
191static struct i2c_board_info i2c0_devs[] __initdata = {
192 /* Camera, To be updated */
193};
194
195/* I2C1 */
196static struct i2c_board_info i2c1_devs[] __initdata = {
197 /* Gyro, To be updated */
198};
199
200static struct platform_device *universal_devices[] __initdata = {
201 /* Samsung Platform Devices */
202 &mmc0_fixed_voltage,
203 &s3c_device_hsmmc0,
204 &s3c_device_hsmmc2,
205 &s3c_device_hsmmc3,
206
207 /* Universal Devices */
208 &universal_gpio_keys,
209 &s5p_device_onenand,
210};
211
212static void __init universal_map_io(void)
213{
214 s5p_init_io(NULL, 0, S5P_VA_CHIPID);
215 s3c24xx_init_clocks(24000000);
216 s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs));
217}
218
219static void __init universal_machine_init(void)
220{
221 universal_sdhci_init();
222
223 i2c_register_board_info(0, i2c0_devs, ARRAY_SIZE(i2c0_devs));
224 i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
225
226 /* Last */
227 platform_add_devices(universal_devices, ARRAY_SIZE(universal_devices));
228}
229
230MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
231 /* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */
232 .boot_params = S5P_PA_SDRAM + 0x100,
233 .init_irq = s5pv310_init_irq,
234 .map_io = universal_map_io,
235 .init_machine = universal_machine_init,
236 .timer = &s5pv310_timer,
237MACHINE_END
diff --git a/arch/arm/mach-tcc8k/board-tcc8000-sdk.c b/arch/arm/mach-tcc8k/board-tcc8000-sdk.c
index fb6426ddeb77..4cb3c2dd905c 100644
--- a/arch/arm/mach-tcc8k/board-tcc8000-sdk.c
+++ b/arch/arm/mach-tcc8k/board-tcc8000-sdk.c
@@ -6,6 +6,7 @@
6 * published by the Free Software Foundation. 6 * published by the Free Software Foundation.
7 */ 7 */
8 8
9#include <linux/delay.h>
9#include <linux/init.h> 10#include <linux/init.h>
10#include <linux/kernel.h> 11#include <linux/kernel.h>
11#include <linux/platform_device.h> 12#include <linux/platform_device.h>
@@ -17,6 +18,8 @@
17#include <asm/mach/time.h> 18#include <asm/mach/time.h>
18 19
19#include <mach/clock.h> 20#include <mach/clock.h>
21#include <mach/tcc-nand.h>
22#include <mach/tcc8k-regs.h>
20 23
21#include "common.h" 24#include "common.h"
22 25
@@ -51,6 +54,22 @@ static struct sys_timer tcc8k_timer = {
51static void __init tcc8k_map_io(void) 54static void __init tcc8k_map_io(void)
52{ 55{
53 tcc8k_map_common_io(); 56 tcc8k_map_common_io();
57
58 /* set PLL0 clock to 96MHz, adapt UART0 divisor */
59 __raw_writel(0x00026003, CKC_BASE + PLL0CFG_OFFS);
60 __raw_writel(0x10000001, CKC_BASE + ACLKUART0_OFFS);
61
62 /* set PLL1 clock to 192MHz */
63 __raw_writel(0x00016003, CKC_BASE + PLL1CFG_OFFS);
64
65 /* set PLL2 clock to 48MHz */
66 __raw_writel(0x00036003, CKC_BASE + PLL2CFG_OFFS);
67
68 /* with CPU freq higher than 150 MHz, need extra DTCM wait */
69 __raw_writel(0x00000001, SCFG_BASE + DTCMWAIT_OFFS);
70
71 /* PLL locking time as specified */
72 udelay(300);
54} 73}
55 74
56MACHINE_START(TCC8000_SDK, "Telechips TCC8000-SDK Demo Board") 75MACHINE_START(TCC8000_SDK, "Telechips TCC8000-SDK Demo Board")
diff --git a/arch/arm/mach-tcc8k/clock.c b/arch/arm/mach-tcc8k/clock.c
index 3970a9cdce26..e7cdae5c77a4 100644
--- a/arch/arm/mach-tcc8k/clock.c
+++ b/arch/arm/mach-tcc8k/clock.c
@@ -45,11 +45,12 @@
45#define ACLKGSB1 (CKC_BASE + ACLKGSB1_OFFS) 45#define ACLKGSB1 (CKC_BASE + ACLKGSB1_OFFS)
46#define ACLKGSB2 (CKC_BASE + ACLKGSB2_OFFS) 46#define ACLKGSB2 (CKC_BASE + ACLKGSB2_OFFS)
47#define ACLKGSB3 (CKC_BASE + ACLKGSB3_OFFS) 47#define ACLKGSB3 (CKC_BASE + ACLKGSB3_OFFS)
48#define ACLKUSBH (CKC_BASE + ACLKUSBH_OFFS)
49#define ACLKTCT (CKC_BASE + ACLKTCT_OFFS) 48#define ACLKTCT (CKC_BASE + ACLKTCT_OFFS)
50#define ACLKTCX (CKC_BASE + ACLKTCX_OFFS) 49#define ACLKTCX (CKC_BASE + ACLKTCX_OFFS)
51#define ACLKTCZ (CKC_BASE + ACLKTCZ_OFFS) 50#define ACLKTCZ (CKC_BASE + ACLKTCZ_OFFS)
52 51
52#define ACLK_MAX_DIV (0xfff + 1)
53
53/* Crystal frequencies */ 54/* Crystal frequencies */
54static unsigned long xi_rate, xti_rate; 55static unsigned long xi_rate, xti_rate;
55 56
@@ -106,9 +107,9 @@ static int root_clk_enable(enum root_clks src)
106 return 0; 107 return 0;
107} 108}
108 109
109static int root_clk_disable(enum root_clks root_src) 110static int root_clk_disable(enum root_clks src)
110{ 111{
111 switch (root_src) { 112 switch (src) {
112 case CLK_SRC_PLL0: return pll_enable(0, 0); 113 case CLK_SRC_PLL0: return pll_enable(0, 0);
113 case CLK_SRC_PLL1: return pll_enable(1, 0); 114 case CLK_SRC_PLL1: return pll_enable(1, 0);
114 case CLK_SRC_PLL2: return pll_enable(2, 0); 115 case CLK_SRC_PLL2: return pll_enable(2, 0);
@@ -197,7 +198,7 @@ static unsigned long get_rate_pll_div(int pll)
197 addr = CKC_BASE + CLKDIVC1_OFFS; 198 addr = CKC_BASE + CLKDIVC1_OFFS;
198 reg = __raw_readl(addr); 199 reg = __raw_readl(addr);
199 if (reg & CLKDIVC1_P2E) 200 if (reg & CLKDIVC1_P2E)
200 div = __raw_readl(addr) & 0x3f; 201 div = reg & 0x3f;
201 break; 202 break;
202 } 203 }
203 return get_rate_pll(pll) / (div + 1); 204 return get_rate_pll(pll) / (div + 1);
@@ -258,14 +259,19 @@ static unsigned long aclk_best_div(struct clk *clk, unsigned long rate)
258{ 259{
259 unsigned long div, src, freq, r1, r2; 260 unsigned long div, src, freq, r1, r2;
260 261
262 if (!rate)
263 return ACLK_MAX_DIV;
264
261 src = __raw_readl(clk->aclkreg) >> ACLK_SEL_SHIFT; 265 src = __raw_readl(clk->aclkreg) >> ACLK_SEL_SHIFT;
262 src &= CLK_SRC_MASK; 266 src &= CLK_SRC_MASK;
263 freq = root_clk_get_rate(src); 267 freq = root_clk_get_rate(src);
264 div = freq / rate + 1; 268 div = freq / rate;
269 if (!div)
270 return 1;
271 if (div >= ACLK_MAX_DIV)
272 return ACLK_MAX_DIV;
265 r1 = freq / div; 273 r1 = freq / div;
266 r2 = freq / (div + 1); 274 r2 = freq / (div + 1);
267 if (r2 >= rate)
268 return div + 1;
269 if ((rate - r2) < (r1 - rate)) 275 if ((rate - r2) < (r1 - rate))
270 return div + 1; 276 return div + 1;
271 277
@@ -287,7 +293,8 @@ static int aclk_set_rate(struct clk *clk, unsigned long rate)
287 u32 reg; 293 u32 reg;
288 294
289 reg = __raw_readl(clk->aclkreg) & ~ACLK_DIV_MASK; 295 reg = __raw_readl(clk->aclkreg) & ~ACLK_DIV_MASK;
290 reg |= aclk_best_div(clk, rate); 296 reg |= aclk_best_div(clk, rate) - 1;
297 __raw_writel(reg, clk->aclkreg);
291 return 0; 298 return 0;
292} 299}
293 300
@@ -296,15 +303,22 @@ static unsigned long get_rate_sys(struct clk *clk)
296 unsigned int src; 303 unsigned int src;
297 304
298 src = __raw_readl(CKC_BASE + CLKCTRL_OFFS) & CLK_SRC_MASK; 305 src = __raw_readl(CKC_BASE + CLKCTRL_OFFS) & CLK_SRC_MASK;
299 return root_clk_get_rate(src); 306 return root_clk_get_rate(src);
300} 307}
301 308
302static unsigned long get_rate_bus(struct clk *clk) 309static unsigned long get_rate_bus(struct clk *clk)
303{ 310{
304 unsigned int div; 311 unsigned int reg, sdiv, bdiv, rate;
305 312
306 div = (__raw_readl(CKC_BASE + CLKCTRL_OFFS) >> 4) & 0xff; 313 reg = __raw_readl(CKC_BASE + CLKCTRL_OFFS);
307 return get_rate_sys(clk) / (div + 1); 314 rate = get_rate_sys(clk);
315 sdiv = (reg >> 20) & 3;
316 if (sdiv)
317 rate /= sdiv + 1;
318 bdiv = (reg >> 4) & 0xff;
319 if (bdiv)
320 rate /= bdiv + 1;
321 return rate;
308} 322}
309 323
310static unsigned long get_rate_cpu(struct clk *clk) 324static unsigned long get_rate_cpu(struct clk *clk)
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index aa53ee22438f..513d6abec1f5 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -3,7 +3,7 @@
3 * arch/arm/mach-u300/core.c 3 * arch/arm/mach-u300/core.c
4 * 4 *
5 * 5 *
6 * Copyright (C) 2007-2010 ST-Ericsson AB 6 * Copyright (C) 2007-2010 ST-Ericsson SA
7 * License terms: GNU General Public License (GPL) version 2 7 * License terms: GNU General Public License (GPL) version 2
8 * Core platform support, IRQ handling and device definitions. 8 * Core platform support, IRQ handling and device definitions.
9 * Author: Linus Walleij <linus.walleij@stericsson.com> 9 * Author: Linus Walleij <linus.walleij@stericsson.com>
@@ -16,7 +16,9 @@
16#include <linux/device.h> 16#include <linux/device.h>
17#include <linux/mm.h> 17#include <linux/mm.h>
18#include <linux/termios.h> 18#include <linux/termios.h>
19#include <linux/dmaengine.h>
19#include <linux/amba/bus.h> 20#include <linux/amba/bus.h>
21#include <linux/amba/serial.h>
20#include <linux/platform_device.h> 22#include <linux/platform_device.h>
21#include <linux/gpio.h> 23#include <linux/gpio.h>
22#include <linux/clk.h> 24#include <linux/clk.h>
@@ -96,10 +98,20 @@ void __init u300_map_io(void)
96 * Declaration of devices found on the U300 board and 98 * Declaration of devices found on the U300 board and
97 * their respective memory locations. 99 * their respective memory locations.
98 */ 100 */
101
102static struct amba_pl011_data uart0_plat_data = {
103#ifdef CONFIG_COH901318
104 .dma_filter = coh901318_filter_id,
105 .dma_rx_param = (void *) U300_DMA_UART0_RX,
106 .dma_tx_param = (void *) U300_DMA_UART0_TX,
107#endif
108};
109
99static struct amba_device uart0_device = { 110static struct amba_device uart0_device = {
100 .dev = { 111 .dev = {
112 .coherent_dma_mask = ~0,
101 .init_name = "uart0", /* Slow device at 0x3000 offset */ 113 .init_name = "uart0", /* Slow device at 0x3000 offset */
102 .platform_data = NULL, 114 .platform_data = &uart0_plat_data,
103 }, 115 },
104 .res = { 116 .res = {
105 .start = U300_UART0_BASE, 117 .start = U300_UART0_BASE,
@@ -111,10 +123,19 @@ static struct amba_device uart0_device = {
111 123
112/* The U335 have an additional UART1 on the APP CPU */ 124/* The U335 have an additional UART1 on the APP CPU */
113#ifdef CONFIG_MACH_U300_BS335 125#ifdef CONFIG_MACH_U300_BS335
126static struct amba_pl011_data uart1_plat_data = {
127#ifdef CONFIG_COH901318
128 .dma_filter = coh901318_filter_id,
129 .dma_rx_param = (void *) U300_DMA_UART1_RX,
130 .dma_tx_param = (void *) U300_DMA_UART1_TX,
131#endif
132};
133
114static struct amba_device uart1_device = { 134static struct amba_device uart1_device = {
115 .dev = { 135 .dev = {
136 .coherent_dma_mask = ~0,
116 .init_name = "uart1", /* Fast device at 0x7000 offset */ 137 .init_name = "uart1", /* Fast device at 0x7000 offset */
117 .platform_data = NULL, 138 .platform_data = &uart1_plat_data,
118 }, 139 },
119 .res = { 140 .res = {
120 .start = U300_UART1_BASE, 141 .start = U300_UART1_BASE,
@@ -960,42 +981,37 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
960 .priority_high = 0, 981 .priority_high = 0,
961 .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x220, 982 .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x220,
962 }, 983 },
984 /*
985 * Don't set up device address, burst count or size of src
986 * or dst bus for this peripheral - handled by PrimeCell
987 * DMA extension.
988 */
963 { 989 {
964 .number = U300_DMA_MMCSD_RX_TX, 990 .number = U300_DMA_MMCSD_RX_TX,
965 .name = "MMCSD RX TX", 991 .name = "MMCSD RX TX",
966 .priority_high = 0, 992 .priority_high = 0,
967 .dev_addr = U300_MMCSD_BASE + 0x080,
968 .param.config = COH901318_CX_CFG_CH_DISABLE | 993 .param.config = COH901318_CX_CFG_CH_DISABLE |
969 COH901318_CX_CFG_LCR_DISABLE | 994 COH901318_CX_CFG_LCR_DISABLE |
970 COH901318_CX_CFG_TC_IRQ_ENABLE | 995 COH901318_CX_CFG_TC_IRQ_ENABLE |
971 COH901318_CX_CFG_BE_IRQ_ENABLE, 996 COH901318_CX_CFG_BE_IRQ_ENABLE,
972 .param.ctrl_lli_chained = 0 | 997 .param.ctrl_lli_chained = 0 |
973 COH901318_CX_CTRL_TC_ENABLE | 998 COH901318_CX_CTRL_TC_ENABLE |
974 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
975 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
976 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
977 COH901318_CX_CTRL_MASTER_MODE_M1RW | 999 COH901318_CX_CTRL_MASTER_MODE_M1RW |
978 COH901318_CX_CTRL_TCP_ENABLE | 1000 COH901318_CX_CTRL_TCP_ENABLE |
979 COH901318_CX_CTRL_TC_IRQ_ENABLE | 1001 COH901318_CX_CTRL_TC_IRQ_DISABLE |
980 COH901318_CX_CTRL_HSP_ENABLE | 1002 COH901318_CX_CTRL_HSP_ENABLE |
981 COH901318_CX_CTRL_HSS_DISABLE | 1003 COH901318_CX_CTRL_HSS_DISABLE |
982 COH901318_CX_CTRL_DDMA_LEGACY, 1004 COH901318_CX_CTRL_DDMA_LEGACY,
983 .param.ctrl_lli = 0 | 1005 .param.ctrl_lli = 0 |
984 COH901318_CX_CTRL_TC_ENABLE | 1006 COH901318_CX_CTRL_TC_ENABLE |
985 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
986 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
987 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
988 COH901318_CX_CTRL_MASTER_MODE_M1RW | 1007 COH901318_CX_CTRL_MASTER_MODE_M1RW |
989 COH901318_CX_CTRL_TCP_ENABLE | 1008 COH901318_CX_CTRL_TCP_ENABLE |
990 COH901318_CX_CTRL_TC_IRQ_ENABLE | 1009 COH901318_CX_CTRL_TC_IRQ_DISABLE |
991 COH901318_CX_CTRL_HSP_ENABLE | 1010 COH901318_CX_CTRL_HSP_ENABLE |
992 COH901318_CX_CTRL_HSS_DISABLE | 1011 COH901318_CX_CTRL_HSS_DISABLE |
993 COH901318_CX_CTRL_DDMA_LEGACY, 1012 COH901318_CX_CTRL_DDMA_LEGACY,
994 .param.ctrl_lli_last = 0 | 1013 .param.ctrl_lli_last = 0 |
995 COH901318_CX_CTRL_TC_ENABLE | 1014 COH901318_CX_CTRL_TC_ENABLE |
996 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
997 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
998 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
999 COH901318_CX_CTRL_MASTER_MODE_M1RW | 1015 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1000 COH901318_CX_CTRL_TCP_DISABLE | 1016 COH901318_CX_CTRL_TCP_DISABLE |
1001 COH901318_CX_CTRL_TC_IRQ_ENABLE | 1017 COH901318_CX_CTRL_TC_IRQ_ENABLE |
@@ -1014,15 +1030,76 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
1014 .name = "MSPRO RX", 1030 .name = "MSPRO RX",
1015 .priority_high = 0, 1031 .priority_high = 0,
1016 }, 1032 },
1033 /*
1034 * Don't set up device address, burst count or size of src
1035 * or dst bus for this peripheral - handled by PrimeCell
1036 * DMA extension.
1037 */
1017 { 1038 {
1018 .number = U300_DMA_UART0_TX, 1039 .number = U300_DMA_UART0_TX,
1019 .name = "UART0 TX", 1040 .name = "UART0 TX",
1020 .priority_high = 0, 1041 .priority_high = 0,
1042 .param.config = COH901318_CX_CFG_CH_DISABLE |
1043 COH901318_CX_CFG_LCR_DISABLE |
1044 COH901318_CX_CFG_TC_IRQ_ENABLE |
1045 COH901318_CX_CFG_BE_IRQ_ENABLE,
1046 .param.ctrl_lli_chained = 0 |
1047 COH901318_CX_CTRL_TC_ENABLE |
1048 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1049 COH901318_CX_CTRL_TCP_ENABLE |
1050 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1051 COH901318_CX_CTRL_HSP_ENABLE |
1052 COH901318_CX_CTRL_HSS_DISABLE |
1053 COH901318_CX_CTRL_DDMA_LEGACY,
1054 .param.ctrl_lli = 0 |
1055 COH901318_CX_CTRL_TC_ENABLE |
1056 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1057 COH901318_CX_CTRL_TCP_ENABLE |
1058 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1059 COH901318_CX_CTRL_HSP_ENABLE |
1060 COH901318_CX_CTRL_HSS_DISABLE |
1061 COH901318_CX_CTRL_DDMA_LEGACY,
1062 .param.ctrl_lli_last = 0 |
1063 COH901318_CX_CTRL_TC_ENABLE |
1064 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1065 COH901318_CX_CTRL_TCP_ENABLE |
1066 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1067 COH901318_CX_CTRL_HSP_ENABLE |
1068 COH901318_CX_CTRL_HSS_DISABLE |
1069 COH901318_CX_CTRL_DDMA_LEGACY,
1021 }, 1070 },
1022 { 1071 {
1023 .number = U300_DMA_UART0_RX, 1072 .number = U300_DMA_UART0_RX,
1024 .name = "UART0 RX", 1073 .name = "UART0 RX",
1025 .priority_high = 0, 1074 .priority_high = 0,
1075 .param.config = COH901318_CX_CFG_CH_DISABLE |
1076 COH901318_CX_CFG_LCR_DISABLE |
1077 COH901318_CX_CFG_TC_IRQ_ENABLE |
1078 COH901318_CX_CFG_BE_IRQ_ENABLE,
1079 .param.ctrl_lli_chained = 0 |
1080 COH901318_CX_CTRL_TC_ENABLE |
1081 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1082 COH901318_CX_CTRL_TCP_ENABLE |
1083 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1084 COH901318_CX_CTRL_HSP_ENABLE |
1085 COH901318_CX_CTRL_HSS_DISABLE |
1086 COH901318_CX_CTRL_DDMA_LEGACY,
1087 .param.ctrl_lli = 0 |
1088 COH901318_CX_CTRL_TC_ENABLE |
1089 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1090 COH901318_CX_CTRL_TCP_ENABLE |
1091 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1092 COH901318_CX_CTRL_HSP_ENABLE |
1093 COH901318_CX_CTRL_HSS_DISABLE |
1094 COH901318_CX_CTRL_DDMA_LEGACY,
1095 .param.ctrl_lli_last = 0 |
1096 COH901318_CX_CTRL_TC_ENABLE |
1097 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1098 COH901318_CX_CTRL_TCP_ENABLE |
1099 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1100 COH901318_CX_CTRL_HSP_ENABLE |
1101 COH901318_CX_CTRL_HSS_DISABLE |
1102 COH901318_CX_CTRL_DDMA_LEGACY,
1026 }, 1103 },
1027 { 1104 {
1028 .number = U300_DMA_APEX_TX, 1105 .number = U300_DMA_APEX_TX,
@@ -1080,7 +1157,7 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
1080 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | 1157 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1081 COH901318_CX_CTRL_MASTER_MODE_M1RW | 1158 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1082 COH901318_CX_CTRL_TCP_ENABLE | 1159 COH901318_CX_CTRL_TCP_ENABLE |
1083 COH901318_CX_CTRL_TC_IRQ_ENABLE | 1160 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1084 COH901318_CX_CTRL_HSP_ENABLE | 1161 COH901318_CX_CTRL_HSP_ENABLE |
1085 COH901318_CX_CTRL_HSS_DISABLE | 1162 COH901318_CX_CTRL_HSS_DISABLE |
1086 COH901318_CX_CTRL_DDMA_LEGACY | 1163 COH901318_CX_CTRL_DDMA_LEGACY |
@@ -1252,15 +1329,77 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
1252 .name = "XGAM PDI", 1329 .name = "XGAM PDI",
1253 .priority_high = 0, 1330 .priority_high = 0,
1254 }, 1331 },
1332 /*
1333 * Don't set up device address, burst count or size of src
1334 * or dst bus for this peripheral - handled by PrimeCell
1335 * DMA extension.
1336 */
1255 { 1337 {
1256 .number = U300_DMA_SPI_TX, 1338 .number = U300_DMA_SPI_TX,
1257 .name = "SPI TX", 1339 .name = "SPI TX",
1258 .priority_high = 0, 1340 .priority_high = 0,
1341 .param.config = COH901318_CX_CFG_CH_DISABLE |
1342 COH901318_CX_CFG_LCR_DISABLE |
1343 COH901318_CX_CFG_TC_IRQ_ENABLE |
1344 COH901318_CX_CFG_BE_IRQ_ENABLE,
1345 .param.ctrl_lli_chained = 0 |
1346 COH901318_CX_CTRL_TC_ENABLE |
1347 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1348 COH901318_CX_CTRL_TCP_DISABLE |
1349 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1350 COH901318_CX_CTRL_HSP_ENABLE |
1351 COH901318_CX_CTRL_HSS_DISABLE |
1352 COH901318_CX_CTRL_DDMA_LEGACY,
1353 .param.ctrl_lli = 0 |
1354 COH901318_CX_CTRL_TC_ENABLE |
1355 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1356 COH901318_CX_CTRL_TCP_DISABLE |
1357 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1358 COH901318_CX_CTRL_HSP_ENABLE |
1359 COH901318_CX_CTRL_HSS_DISABLE |
1360 COH901318_CX_CTRL_DDMA_LEGACY,
1361 .param.ctrl_lli_last = 0 |
1362 COH901318_CX_CTRL_TC_ENABLE |
1363 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1364 COH901318_CX_CTRL_TCP_DISABLE |
1365 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1366 COH901318_CX_CTRL_HSP_ENABLE |
1367 COH901318_CX_CTRL_HSS_DISABLE |
1368 COH901318_CX_CTRL_DDMA_LEGACY,
1259 }, 1369 },
1260 { 1370 {
1261 .number = U300_DMA_SPI_RX, 1371 .number = U300_DMA_SPI_RX,
1262 .name = "SPI RX", 1372 .name = "SPI RX",
1263 .priority_high = 0, 1373 .priority_high = 0,
1374 .param.config = COH901318_CX_CFG_CH_DISABLE |
1375 COH901318_CX_CFG_LCR_DISABLE |
1376 COH901318_CX_CFG_TC_IRQ_ENABLE |
1377 COH901318_CX_CFG_BE_IRQ_ENABLE,
1378 .param.ctrl_lli_chained = 0 |
1379 COH901318_CX_CTRL_TC_ENABLE |
1380 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1381 COH901318_CX_CTRL_TCP_DISABLE |
1382 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1383 COH901318_CX_CTRL_HSP_ENABLE |
1384 COH901318_CX_CTRL_HSS_DISABLE |
1385 COH901318_CX_CTRL_DDMA_LEGACY,
1386 .param.ctrl_lli = 0 |
1387 COH901318_CX_CTRL_TC_ENABLE |
1388 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1389 COH901318_CX_CTRL_TCP_DISABLE |
1390 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1391 COH901318_CX_CTRL_HSP_ENABLE |
1392 COH901318_CX_CTRL_HSS_DISABLE |
1393 COH901318_CX_CTRL_DDMA_LEGACY,
1394 .param.ctrl_lli_last = 0 |
1395 COH901318_CX_CTRL_TC_ENABLE |
1396 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1397 COH901318_CX_CTRL_TCP_DISABLE |
1398 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1399 COH901318_CX_CTRL_HSP_ENABLE |
1400 COH901318_CX_CTRL_HSS_DISABLE |
1401 COH901318_CX_CTRL_DDMA_LEGACY,
1402
1264 }, 1403 },
1265 { 1404 {
1266 .number = U300_DMA_GENERAL_PURPOSE_0, 1405 .number = U300_DMA_GENERAL_PURPOSE_0,
@@ -1617,7 +1756,7 @@ static void __init u300_init_check_chip(void)
1617#endif 1756#endif
1618#ifdef CONFIG_MACH_U300_BS335 1757#ifdef CONFIG_MACH_U300_BS335
1619 if ((val & 0xFF00U) != 0xf000 && (val & 0xFF00U) != 0xf100) { 1758 if ((val & 0xFF00U) != 0xf000 && (val & 0xFF00U) != 0xf100) {
1620 printk(KERN_ERR "Platform configured for BS365 " \ 1759 printk(KERN_ERR "Platform configured for BS335 " \
1621 " with DB3350 but %s detected, expect problems!", 1760 " with DB3350 but %s detected, expect problems!",
1622 chipname); 1761 chipname);
1623 } 1762 }
@@ -1692,12 +1831,12 @@ void __init u300_init_devices(void)
1692 /* Register subdevices on the I2C buses */ 1831 /* Register subdevices on the I2C buses */
1693 u300_i2c_register_board_devices(); 1832 u300_i2c_register_board_devices();
1694 1833
1695 /* Register subdevices on the SPI bus */
1696 u300_spi_register_board_devices();
1697
1698 /* Register the platform devices */ 1834 /* Register the platform devices */
1699 platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs)); 1835 platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
1700 1836
1837 /* Register subdevices on the SPI bus */
1838 u300_spi_register_board_devices();
1839
1701#ifndef CONFIG_MACH_U300_SEMI_IS_SHARED 1840#ifndef CONFIG_MACH_U300_SEMI_IS_SHARED
1702 /* 1841 /*
1703 * Enable SEMI self refresh. Self-refresh of the SDRAM is entered when 1842 * Enable SEMI self refresh. Self-refresh of the SDRAM is entered when
diff --git a/arch/arm/mach-u300/include/mach/coh901318.h b/arch/arm/mach-u300/include/mach/coh901318.h
index 6193aaa47794..7c3b2b2d25b6 100644
--- a/arch/arm/mach-u300/include/mach/coh901318.h
+++ b/arch/arm/mach-u300/include/mach/coh901318.h
@@ -102,6 +102,7 @@ struct coh901318_platform {
102 const int max_channels; 102 const int max_channels;
103}; 103};
104 104
105#ifdef CONFIG_COH901318
105/** 106/**
106 * coh901318_filter_id() - DMA channel filter function 107 * coh901318_filter_id() - DMA channel filter function
107 * @chan: dma channel handle 108 * @chan: dma channel handle
@@ -110,6 +111,12 @@ struct coh901318_platform {
110 * In dma_request_channel() it specifies what channel id to be requested 111 * In dma_request_channel() it specifies what channel id to be requested
111 */ 112 */
112bool coh901318_filter_id(struct dma_chan *chan, void *chan_id); 113bool coh901318_filter_id(struct dma_chan *chan, void *chan_id);
114#else
115static inline bool coh901318_filter_id(struct dma_chan *chan, void *chan_id)
116{
117 return false;
118}
119#endif
113 120
114/* 121/*
115 * DMA Controller - this access the static mappings of the coh901318 dma. 122 * DMA Controller - this access the static mappings of the coh901318 dma.
diff --git a/arch/arm/mach-u300/mmc.c b/arch/arm/mach-u300/mmc.c
index de1ac9ad2213..677ccef5cd32 100644
--- a/arch/arm/mach-u300/mmc.c
+++ b/arch/arm/mach-u300/mmc.c
@@ -3,159 +3,52 @@
3 * arch/arm/mach-u300/mmc.c 3 * arch/arm/mach-u300/mmc.c
4 * 4 *
5 * 5 *
6 * Copyright (C) 2009 ST-Ericsson AB 6 * Copyright (C) 2009 ST-Ericsson SA
7 * License terms: GNU General Public License (GPL) version 2 7 * License terms: GNU General Public License (GPL) version 2
8 * 8 *
9 * Author: Linus Walleij <linus.walleij@stericsson.com> 9 * Author: Linus Walleij <linus.walleij@stericsson.com>
10 * Author: Johan Lundin <johan.lundin@stericsson.com> 10 * Author: Johan Lundin
11 * Author: Jonas Aaberg <jonas.aberg@stericsson.com> 11 * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
12 */ 12 */
13#include <linux/device.h> 13#include <linux/device.h>
14#include <linux/amba/bus.h> 14#include <linux/amba/bus.h>
15#include <linux/mmc/host.h> 15#include <linux/mmc/host.h>
16#include <linux/input.h>
17#include <linux/workqueue.h>
18#include <linux/delay.h>
19#include <linux/regulator/consumer.h>
20#include <linux/regulator/machine.h>
21#include <linux/gpio.h> 16#include <linux/gpio.h>
17#include <linux/dmaengine.h>
22#include <linux/amba/mmci.h> 18#include <linux/amba/mmci.h>
23#include <linux/slab.h> 19#include <linux/slab.h>
20#include <mach/coh901318.h>
21#include <mach/dma_channels.h>
24 22
25#include "mmc.h" 23#include "mmc.h"
26#include "padmux.h" 24#include "padmux.h"
27 25
28struct mmci_card_event { 26static struct mmci_platform_data mmc0_plat_data = {
29 struct input_dev *mmc_input; 27 /*
30 int mmc_inserted; 28 * Do not set ocr_mask or voltage translation function,
31 struct work_struct workq; 29 * we have a regulator we can control instead.
32 struct mmci_platform_data mmc0_plat_data; 30 */
31 /* Nominally 2.85V on our platform */
32 .f_max = 24000000,
33 .gpio_wp = -1,
34 .gpio_cd = U300_GPIO_PIN_MMC_CD,
35 .cd_invert = true,
36 .capabilities = MMC_CAP_MMC_HIGHSPEED |
37 MMC_CAP_SD_HIGHSPEED | MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
38#ifdef CONFIG_COH901318
39 .dma_filter = coh901318_filter_id,
40 .dma_rx_param = (void *) U300_DMA_MMCSD_RX_TX,
41 /* Don't specify a TX channel, this RX channel is bidirectional */
42#endif
33}; 43};
34 44
35static unsigned int mmc_status(struct device *dev)
36{
37 struct mmci_card_event *mmci_card = container_of(
38 dev->platform_data,
39 struct mmci_card_event, mmc0_plat_data);
40
41 return mmci_card->mmc_inserted;
42}
43
44static int mmci_callback(void *data)
45{
46 struct mmci_card_event *mmci_card = data;
47
48 disable_irq_on_gpio_pin(U300_GPIO_PIN_MMC_CD);
49 schedule_work(&mmci_card->workq);
50
51 return 0;
52}
53
54
55static ssize_t gpio_show(struct device *dev, struct device_attribute *attr,
56 char *buf)
57{
58 struct mmci_card_event *mmci_card = container_of(
59 dev->platform_data,
60 struct mmci_card_event, mmc0_plat_data);
61
62
63 return sprintf(buf, "%d\n", !mmci_card->mmc_inserted);
64}
65
66static DEVICE_ATTR(mmc_inserted, S_IRUGO, gpio_show, NULL);
67
68static void _mmci_callback(struct work_struct *ws)
69{
70
71 struct mmci_card_event *mmci_card = container_of(
72 ws,
73 struct mmci_card_event, workq);
74
75 mdelay(20);
76
77 mmci_card->mmc_inserted = !gpio_get_value(U300_GPIO_PIN_MMC_CD);
78
79 input_report_switch(mmci_card->mmc_input, KEY_INSERT,
80 mmci_card->mmc_inserted);
81 input_sync(mmci_card->mmc_input);
82
83 pr_debug("MMC/SD card was %s\n",
84 mmci_card->mmc_inserted ? "inserted" : "removed");
85
86 enable_irq_on_gpio_pin(U300_GPIO_PIN_MMC_CD, mmci_card->mmc_inserted);
87}
88
89int __devinit mmc_init(struct amba_device *adev) 45int __devinit mmc_init(struct amba_device *adev)
90{ 46{
91 struct mmci_card_event *mmci_card;
92 struct device *mmcsd_device = &adev->dev; 47 struct device *mmcsd_device = &adev->dev;
93 struct pmx *pmx; 48 struct pmx *pmx;
94 int ret = 0; 49 int ret = 0;
95 50
96 mmci_card = kzalloc(sizeof(struct mmci_card_event), GFP_KERNEL); 51 mmcsd_device->platform_data = &mmc0_plat_data;
97 if (!mmci_card)
98 return -ENOMEM;
99
100 /*
101 * Do not set ocr_mask or voltage translation function,
102 * we have a regulator we can control instead.
103 */
104 /* Nominally 2.85V on our platform */
105 mmci_card->mmc0_plat_data.f_max = 24000000;
106 mmci_card->mmc0_plat_data.status = mmc_status;
107 mmci_card->mmc0_plat_data.gpio_wp = -1;
108 mmci_card->mmc0_plat_data.gpio_cd = -1;
109 mmci_card->mmc0_plat_data.capabilities = MMC_CAP_MMC_HIGHSPEED |
110 MMC_CAP_SD_HIGHSPEED | MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA;
111
112 mmcsd_device->platform_data = (void *) &mmci_card->mmc0_plat_data;
113
114 INIT_WORK(&mmci_card->workq, _mmci_callback);
115
116 ret = gpio_request(U300_GPIO_PIN_MMC_CD, "MMC card detection");
117 if (ret) {
118 printk(KERN_CRIT "Could not allocate MMC card detection " \
119 "GPIO pin\n");
120 goto out;
121 }
122
123 ret = gpio_direction_input(U300_GPIO_PIN_MMC_CD);
124 if (ret) {
125 printk(KERN_CRIT "Invalid GPIO pin requested\n");
126 goto out;
127 }
128
129 ret = sysfs_create_file(&mmcsd_device->kobj,
130 &dev_attr_mmc_inserted.attr);
131 if (ret)
132 goto out;
133
134 mmci_card->mmc_input = input_allocate_device();
135 if (!mmci_card->mmc_input) {
136 printk(KERN_CRIT "Could not allocate MMC input device\n");
137 return -ENOMEM;
138 }
139
140 mmci_card->mmc_input->name = "MMC insert notification";
141 mmci_card->mmc_input->id.bustype = BUS_HOST;
142 mmci_card->mmc_input->id.vendor = 0;
143 mmci_card->mmc_input->id.product = 0;
144 mmci_card->mmc_input->id.version = 0x0100;
145 mmci_card->mmc_input->dev.parent = mmcsd_device;
146 input_set_capability(mmci_card->mmc_input, EV_SW, KEY_INSERT);
147
148 /*
149 * Since this must always be compiled into the kernel, this input
150 * is never unregistered or free:ed.
151 */
152 ret = input_register_device(mmci_card->mmc_input);
153 if (ret) {
154 input_free_device(mmci_card->mmc_input);
155 goto out;
156 }
157
158 input_set_drvdata(mmci_card->mmc_input, mmci_card);
159 52
160 /* 53 /*
161 * Setup padmuxing for MMC. Since this must always be 54 * Setup padmuxing for MMC. Since this must always be
@@ -171,12 +64,5 @@ int __devinit mmc_init(struct amba_device *adev)
171 pr_warning("Could not activate padmuxing\n"); 64 pr_warning("Could not activate padmuxing\n");
172 } 65 }
173 66
174 ret = gpio_register_callback(U300_GPIO_PIN_MMC_CD, mmci_callback,
175 mmci_card);
176
177 schedule_work(&mmci_card->workq);
178
179 printk(KERN_INFO "Registered MMC insert/remove notification\n");
180out:
181 return ret; 67 return ret;
182} 68}
diff --git a/arch/arm/mach-u300/spi.c b/arch/arm/mach-u300/spi.c
index 00869def5420..5767208f1c1d 100644
--- a/arch/arm/mach-u300/spi.c
+++ b/arch/arm/mach-u300/spi.c
@@ -11,6 +11,9 @@
11#include <linux/spi/spi.h> 11#include <linux/spi/spi.h>
12#include <linux/amba/pl022.h> 12#include <linux/amba/pl022.h>
13#include <linux/err.h> 13#include <linux/err.h>
14#include <mach/coh901318.h>
15#include <mach/dma_channels.h>
16
14#include "padmux.h" 17#include "padmux.h"
15 18
16/* 19/*
@@ -30,11 +33,8 @@ static void select_dummy_chip(u32 chipselect)
30} 33}
31 34
32struct pl022_config_chip dummy_chip_info = { 35struct pl022_config_chip dummy_chip_info = {
33 /* 36 /* available POLLING_TRANSFER, INTERRUPT_TRANSFER, DMA_TRANSFER */
34 * available POLLING_TRANSFER and INTERRUPT_TRANSFER, 37 .com_mode = DMA_TRANSFER,
35 * DMA_TRANSFER does not work
36 */
37 .com_mode = INTERRUPT_TRANSFER,
38 .iface = SSP_INTERFACE_MOTOROLA_SPI, 38 .iface = SSP_INTERFACE_MOTOROLA_SPI,
39 /* We can only act as master but SSP_SLAVE is possible in theory */ 39 /* We can only act as master but SSP_SLAVE is possible in theory */
40 .hierarchy = SSP_MASTER, 40 .hierarchy = SSP_MASTER,
@@ -75,8 +75,6 @@ static struct spi_board_info u300_spi_devices[] = {
75static struct pl022_ssp_controller ssp_platform_data = { 75static struct pl022_ssp_controller ssp_platform_data = {
76 /* If you have several SPI buses this varies, we have only bus 0 */ 76 /* If you have several SPI buses this varies, we have only bus 0 */
77 .bus_id = 0, 77 .bus_id = 0,
78 /* Set this to 1 when we think we got DMA working */
79 .enable_dma = 0,
80 /* 78 /*
81 * On the APP CPU GPIO 4, 5 and 6 are connected as generic 79 * On the APP CPU GPIO 4, 5 and 6 are connected as generic
82 * chip selects for SPI. (Same on U330, U335 and U365.) 80 * chip selects for SPI. (Same on U330, U335 and U365.)
@@ -84,6 +82,14 @@ static struct pl022_ssp_controller ssp_platform_data = {
84 * and do padmuxing accordingly too. 82 * and do padmuxing accordingly too.
85 */ 83 */
86 .num_chipselect = 3, 84 .num_chipselect = 3,
85#ifdef CONFIG_COH901318
86 .enable_dma = 1,
87 .dma_filter = coh901318_filter_id,
88 .dma_rx_param = (void *) U300_DMA_SPI_RX,
89 .dma_tx_param = (void *) U300_DMA_SPI_TX,
90#else
91 .enable_dma = 0,
92#endif
87}; 93};
88 94
89 95
@@ -109,6 +115,7 @@ void __init u300_spi_init(struct amba_device *adev)
109 } 115 }
110 116
111} 117}
118
112void __init u300_spi_register_board_devices(void) 119void __init u300_spi_register_board_devices(void)
113{ 120{
114 /* Register any SPI devices */ 121 /* Register any SPI devices */
diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile
index 53ebb429e971..b549a8fb4231 100644
--- a/arch/arm/mach-ux500/Makefile
+++ b/arch/arm/mach-ux500/Makefile
@@ -3,16 +3,18 @@
3# 3#
4 4
5obj-y := clock.o cpu.o devices.o devices-common.o \ 5obj-y := clock.o cpu.o devices.o devices-common.o \
6 id.o 6 id.o usb.o
7obj-$(CONFIG_UX500_SOC_DB5500) += cpu-db5500.o dma-db5500.o 7obj-$(CONFIG_UX500_SOC_DB5500) += cpu-db5500.o dma-db5500.o
8obj-$(CONFIG_UX500_SOC_DB8500) += cpu-db8500.o devices-db8500.o prcmu.o 8obj-$(CONFIG_UX500_SOC_DB8500) += cpu-db8500.o devices-db8500.o prcmu.o
9obj-$(CONFIG_MACH_U8500) += board-mop500.o board-mop500-sdi.o \ 9obj-$(CONFIG_MACH_U8500) += board-mop500.o board-mop500-sdi.o \
10 board-mop500-keypads.o 10 board-mop500-regulators.o \
11 board-mop500-uib.o board-mop500-stuib.o \
12 board-mop500-u8500uib.o \
13 board-mop500-pins.o
11obj-$(CONFIG_MACH_U5500) += board-u5500.o board-u5500-sdi.o 14obj-$(CONFIG_MACH_U5500) += board-u5500.o board-u5500-sdi.o
12obj-$(CONFIG_SMP) += platsmp.o headsmp.o 15obj-$(CONFIG_SMP) += platsmp.o headsmp.o
13obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o 16obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
14obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o 17obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
15obj-$(CONFIG_REGULATOR_AB8500) += board-mop500-regulators.o
16obj-$(CONFIG_U5500_MODEM_IRQ) += modem-irq-db5500.o 18obj-$(CONFIG_U5500_MODEM_IRQ) += modem-irq-db5500.o
17obj-$(CONFIG_U5500_MBOX) += mbox-db5500.o 19obj-$(CONFIG_U5500_MBOX) += mbox-db5500.o
18obj-$(CONFIG_CPU_FREQ) += cpufreq.o 20obj-$(CONFIG_CPU_FREQ) += cpufreq.o
diff --git a/arch/arm/mach-ux500/board-mop500-keypads.c b/arch/arm/mach-ux500/board-mop500-keypads.c
deleted file mode 100644
index 70318c354d32..000000000000
--- a/arch/arm/mach-ux500/board-mop500-keypads.c
+++ /dev/null
@@ -1,229 +0,0 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License Terms: GNU General Public License v2
5 *
6 * Keypad layouts for various boards
7 */
8
9#include <linux/i2c.h>
10#include <linux/gpio.h>
11#include <linux/interrupt.h>
12#include <linux/platform_device.h>
13#include <linux/mfd/stmpe.h>
14#include <linux/mfd/tc3589x.h>
15#include <linux/input/matrix_keypad.h>
16
17#include <plat/pincfg.h>
18#include <plat/ske.h>
19
20#include <mach/devices.h>
21#include <mach/hardware.h>
22
23#include "devices-db8500.h"
24#include "board-mop500.h"
25
26/* STMPE/SKE keypad use this key layout */
27static const unsigned int mop500_keymap[] = {
28 KEY(2, 5, KEY_END),
29 KEY(4, 1, KEY_POWER),
30 KEY(3, 5, KEY_VOLUMEDOWN),
31 KEY(1, 3, KEY_3),
32 KEY(5, 2, KEY_RIGHT),
33 KEY(5, 0, KEY_9),
34
35 KEY(0, 5, KEY_MENU),
36 KEY(7, 6, KEY_ENTER),
37 KEY(4, 5, KEY_0),
38 KEY(6, 7, KEY_2),
39 KEY(3, 4, KEY_UP),
40 KEY(3, 3, KEY_DOWN),
41
42 KEY(6, 4, KEY_SEND),
43 KEY(6, 2, KEY_BACK),
44 KEY(4, 2, KEY_VOLUMEUP),
45 KEY(5, 5, KEY_1),
46 KEY(4, 3, KEY_LEFT),
47 KEY(3, 2, KEY_7),
48};
49
50static const struct matrix_keymap_data mop500_keymap_data = {
51 .keymap = mop500_keymap,
52 .keymap_size = ARRAY_SIZE(mop500_keymap),
53};
54
55/*
56 * Nomadik SKE keypad
57 */
58#define ROW_PIN_I0 164
59#define ROW_PIN_I1 163
60#define ROW_PIN_I2 162
61#define ROW_PIN_I3 161
62#define ROW_PIN_I4 156
63#define ROW_PIN_I5 155
64#define ROW_PIN_I6 154
65#define ROW_PIN_I7 153
66#define COL_PIN_O0 168
67#define COL_PIN_O1 167
68#define COL_PIN_O2 166
69#define COL_PIN_O3 165
70#define COL_PIN_O4 160
71#define COL_PIN_O5 159
72#define COL_PIN_O6 158
73#define COL_PIN_O7 157
74
75#define SKE_KPD_MAX_ROWS 8
76#define SKE_KPD_MAX_COLS 8
77
78static int ske_kp_rows[] = {
79 ROW_PIN_I0, ROW_PIN_I1, ROW_PIN_I2, ROW_PIN_I3,
80 ROW_PIN_I4, ROW_PIN_I5, ROW_PIN_I6, ROW_PIN_I7,
81};
82
83/*
84 * ske_set_gpio_row: request and set gpio rows
85 */
86static int ske_set_gpio_row(int gpio)
87{
88 int ret;
89
90 ret = gpio_request(gpio, "ske-kp");
91 if (ret < 0) {
92 pr_err("ske_set_gpio_row: gpio request failed\n");
93 return ret;
94 }
95
96 ret = gpio_direction_output(gpio, 1);
97 if (ret < 0) {
98 pr_err("ske_set_gpio_row: gpio direction failed\n");
99 gpio_free(gpio);
100 }
101
102 return ret;
103}
104
105/*
106 * ske_kp_init - enable the gpio configuration
107 */
108static int ske_kp_init(void)
109{
110 int ret, i;
111
112 for (i = 0; i < SKE_KPD_MAX_ROWS; i++) {
113 ret = ske_set_gpio_row(ske_kp_rows[i]);
114 if (ret < 0) {
115 pr_err("ske_kp_init: failed init\n");
116 return ret;
117 }
118 }
119
120 return 0;
121}
122
123static struct ske_keypad_platform_data ske_keypad_board = {
124 .init = ske_kp_init,
125 .keymap_data = &mop500_keymap_data,
126 .no_autorepeat = true,
127 .krow = SKE_KPD_MAX_ROWS, /* 8x8 matrix */
128 .kcol = SKE_KPD_MAX_COLS,
129 .debounce_ms = 40, /* in millisecs */
130};
131
132/*
133 * STMPE1601
134 */
135static struct stmpe_keypad_platform_data stmpe1601_keypad_data = {
136 .debounce_ms = 64,
137 .scan_count = 8,
138 .no_autorepeat = true,
139 .keymap_data = &mop500_keymap_data,
140};
141
142static struct stmpe_platform_data stmpe1601_data = {
143 .id = 1,
144 .blocks = STMPE_BLOCK_KEYPAD,
145 .irq_trigger = IRQF_TRIGGER_FALLING,
146 .irq_base = MOP500_STMPE1601_IRQ(0),
147 .keypad = &stmpe1601_keypad_data,
148 .autosleep = true,
149 .autosleep_timeout = 1024,
150};
151
152static struct i2c_board_info mop500_i2c0_devices_stuib[] = {
153 {
154 I2C_BOARD_INFO("stmpe1601", 0x40),
155 .irq = NOMADIK_GPIO_TO_IRQ(218),
156 .platform_data = &stmpe1601_data,
157 .flags = I2C_CLIENT_WAKE,
158 },
159};
160
161/*
162 * TC35893
163 */
164
165static const unsigned int uib_keymap[] = {
166 KEY(3, 1, KEY_END),
167 KEY(4, 1, KEY_POWER),
168 KEY(6, 4, KEY_VOLUMEDOWN),
169 KEY(4, 2, KEY_EMAIL),
170 KEY(3, 3, KEY_RIGHT),
171 KEY(2, 5, KEY_BACKSPACE),
172
173 KEY(6, 7, KEY_MENU),
174 KEY(5, 0, KEY_ENTER),
175 KEY(4, 3, KEY_0),
176 KEY(3, 4, KEY_DOT),
177 KEY(5, 2, KEY_UP),
178 KEY(3, 5, KEY_DOWN),
179
180 KEY(4, 5, KEY_SEND),
181 KEY(0, 5, KEY_BACK),
182 KEY(6, 2, KEY_VOLUMEUP),
183 KEY(1, 3, KEY_SPACE),
184 KEY(7, 6, KEY_LEFT),
185 KEY(5, 5, KEY_SEARCH),
186};
187
188static struct matrix_keymap_data uib_keymap_data = {
189 .keymap = uib_keymap,
190 .keymap_size = ARRAY_SIZE(uib_keymap),
191};
192
193static struct tc3589x_keypad_platform_data tc35893_data = {
194 .krow = TC_KPD_ROWS,
195 .kcol = TC_KPD_COLUMNS,
196 .debounce_period = TC_KPD_DEBOUNCE_PERIOD,
197 .settle_time = TC_KPD_SETTLE_TIME,
198 .irqtype = IRQF_TRIGGER_FALLING,
199 .enable_wakeup = true,
200 .keymap_data = &uib_keymap_data,
201 .no_autorepeat = true,
202};
203
204static struct tc3589x_platform_data tc3589x_keypad_data = {
205 .block = TC3589x_BLOCK_KEYPAD,
206 .keypad = &tc35893_data,
207 .irq_base = MOP500_EGPIO_IRQ_BASE,
208};
209
210static struct i2c_board_info mop500_i2c0_devices_uib[] = {
211 {
212 I2C_BOARD_INFO("tc3589x", 0x44),
213 .platform_data = &tc3589x_keypad_data,
214 .irq = NOMADIK_GPIO_TO_IRQ(218),
215 .flags = I2C_CLIENT_WAKE,
216 },
217};
218
219void mop500_keypad_init(void)
220{
221 db8500_add_ske_keypad(&ske_keypad_board);
222
223 i2c_register_board_info(0, mop500_i2c0_devices_stuib,
224 ARRAY_SIZE(mop500_i2c0_devices_stuib));
225
226 i2c_register_board_info(0, mop500_i2c0_devices_uib,
227 ARRAY_SIZE(mop500_i2c0_devices_uib));
228
229}
diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c
new file mode 100644
index 000000000000..fd4cf1ca5efd
--- /dev/null
+++ b/arch/arm/mach-ux500/board-mop500-pins.c
@@ -0,0 +1,241 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License terms: GNU General Public License (GPL) version 2
5 */
6
7#include <linux/kernel.h>
8#include <linux/init.h>
9#include <linux/gpio.h>
10
11#include <asm/mach-types.h>
12#include <plat/pincfg.h>
13#include <mach/hardware.h>
14
15#include "pins-db8500.h"
16
17static pin_cfg_t mop500_pins_common[] = {
18 /* I2C */
19 GPIO147_I2C0_SCL,
20 GPIO148_I2C0_SDA,
21 GPIO16_I2C1_SCL,
22 GPIO17_I2C1_SDA,
23 GPIO10_I2C2_SDA,
24 GPIO11_I2C2_SCL,
25 GPIO229_I2C3_SDA,
26 GPIO230_I2C3_SCL,
27
28 /* MSP0 */
29 GPIO12_MSP0_TXD,
30 GPIO13_MSP0_TFS,
31 GPIO14_MSP0_TCK,
32 GPIO15_MSP0_RXD,
33
34 /* MSP2: HDMI */
35 GPIO193_MSP2_TXD,
36 GPIO194_MSP2_TCK,
37 GPIO195_MSP2_TFS,
38 GPIO196_MSP2_RXD | PIN_OUTPUT_LOW,
39
40 /* Touch screen INTERFACE */
41 GPIO84_GPIO | PIN_INPUT_PULLUP, /* TOUCH_INT1 */
42
43 /* STMPE1601/tc35893 keypad IRQ */
44 GPIO218_GPIO | PIN_INPUT_PULLUP,
45
46 /* MMC0 (MicroSD card) */
47 GPIO18_MC0_CMDDIR | PIN_OUTPUT_HIGH,
48 GPIO19_MC0_DAT0DIR | PIN_OUTPUT_HIGH,
49 GPIO20_MC0_DAT2DIR | PIN_OUTPUT_HIGH,
50
51 GPIO22_MC0_FBCLK | PIN_INPUT_NOPULL,
52 GPIO23_MC0_CLK | PIN_OUTPUT_LOW,
53 GPIO24_MC0_CMD | PIN_INPUT_PULLUP,
54 GPIO25_MC0_DAT0 | PIN_INPUT_PULLUP,
55 GPIO26_MC0_DAT1 | PIN_INPUT_PULLUP,
56 GPIO27_MC0_DAT2 | PIN_INPUT_PULLUP,
57 GPIO28_MC0_DAT3 | PIN_INPUT_PULLUP,
58
59 /* SDI1 (SDIO) */
60 GPIO208_MC1_CLK | PIN_OUTPUT_LOW,
61 GPIO209_MC1_FBCLK | PIN_INPUT_NOPULL,
62 GPIO210_MC1_CMD | PIN_INPUT_PULLUP,
63 GPIO211_MC1_DAT0 | PIN_INPUT_PULLUP,
64 GPIO212_MC1_DAT1 | PIN_INPUT_PULLUP,
65 GPIO213_MC1_DAT2 | PIN_INPUT_PULLUP,
66 GPIO214_MC1_DAT3 | PIN_INPUT_PULLUP,
67
68 /* MMC2 (On-board DATA INTERFACE eMMC) */
69 GPIO128_MC2_CLK | PIN_OUTPUT_LOW,
70 GPIO129_MC2_CMD | PIN_INPUT_PULLUP,
71 GPIO130_MC2_FBCLK | PIN_INPUT_NOPULL,
72 GPIO131_MC2_DAT0 | PIN_INPUT_PULLUP,
73 GPIO132_MC2_DAT1 | PIN_INPUT_PULLUP,
74 GPIO133_MC2_DAT2 | PIN_INPUT_PULLUP,
75 GPIO134_MC2_DAT3 | PIN_INPUT_PULLUP,
76 GPIO135_MC2_DAT4 | PIN_INPUT_PULLUP,
77 GPIO136_MC2_DAT5 | PIN_INPUT_PULLUP,
78 GPIO137_MC2_DAT6 | PIN_INPUT_PULLUP,
79 GPIO138_MC2_DAT7 | PIN_INPUT_PULLUP,
80
81 /* MMC4 (On-board STORAGE INTERFACE eMMC) */
82 GPIO197_MC4_DAT3 | PIN_INPUT_PULLUP,
83 GPIO198_MC4_DAT2 | PIN_INPUT_PULLUP,
84 GPIO199_MC4_DAT1 | PIN_INPUT_PULLUP,
85 GPIO200_MC4_DAT0 | PIN_INPUT_PULLUP,
86 GPIO201_MC4_CMD | PIN_INPUT_PULLUP,
87 GPIO202_MC4_FBCLK | PIN_INPUT_NOPULL,
88 GPIO203_MC4_CLK | PIN_OUTPUT_LOW,
89 GPIO204_MC4_DAT7 | PIN_INPUT_PULLUP,
90 GPIO205_MC4_DAT6 | PIN_INPUT_PULLUP,
91 GPIO206_MC4_DAT5 | PIN_INPUT_PULLUP,
92 GPIO207_MC4_DAT4 | PIN_INPUT_PULLUP,
93
94 /* SKE keypad */
95 GPIO153_KP_I7,
96 GPIO154_KP_I6,
97 GPIO155_KP_I5,
98 GPIO156_KP_I4,
99 GPIO157_KP_O7,
100 GPIO158_KP_O6,
101 GPIO159_KP_O5,
102 GPIO160_KP_O4,
103 GPIO161_KP_I3,
104 GPIO162_KP_I2,
105 GPIO163_KP_I1,
106 GPIO164_KP_I0,
107 GPIO165_KP_O3,
108 GPIO166_KP_O2,
109 GPIO167_KP_O1,
110 GPIO168_KP_O0,
111
112 /* UART */
113 GPIO0_U0_CTSn | PIN_INPUT_PULLUP,
114 GPIO1_U0_RTSn | PIN_OUTPUT_HIGH,
115 GPIO2_U0_RXD | PIN_INPUT_PULLUP,
116 GPIO3_U0_TXD | PIN_OUTPUT_HIGH,
117
118 GPIO29_U2_RXD | PIN_INPUT_PULLUP,
119 GPIO30_U2_TXD | PIN_OUTPUT_HIGH,
120 GPIO31_U2_CTSn | PIN_INPUT_PULLUP,
121 GPIO32_U2_RTSn | PIN_OUTPUT_HIGH,
122
123 /* Display & HDMI HW sync */
124 GPIO68_LCD_VSI0 | PIN_INPUT_PULLUP,
125 GPIO69_LCD_VSI1 | PIN_INPUT_PULLUP,
126};
127
128static pin_cfg_t mop500_pins_default[] = {
129 /* SSP0 */
130 GPIO143_SSP0_CLK,
131 GPIO144_SSP0_FRM,
132 GPIO145_SSP0_RXD | PIN_PULL_DOWN,
133 GPIO146_SSP0_TXD,
134
135
136 GPIO217_GPIO | PIN_INPUT_PULLUP, /* TC35892 IRQ */
137
138 /* SDI0 (MicroSD card) */
139 GPIO21_MC0_DAT31DIR | PIN_OUTPUT_HIGH,
140
141 /* UART */
142 GPIO4_U1_RXD | PIN_INPUT_PULLUP,
143 GPIO5_U1_TXD | PIN_OUTPUT_HIGH,
144 GPIO6_U1_CTSn | PIN_INPUT_PULLUP,
145 GPIO7_U1_RTSn | PIN_OUTPUT_HIGH,
146};
147
148static pin_cfg_t mop500_pins_hrefv60[] = {
149 /* WLAN */
150 GPIO4_GPIO | PIN_INPUT_PULLUP,/* WLAN_IRQ */
151 GPIO85_GPIO | PIN_OUTPUT_LOW,/* WLAN_ENA */
152
153 /* XENON Flashgun INTERFACE */
154 GPIO6_IP_GPIO0 | PIN_INPUT_PULLUP,/* XENON_FLASH_ID */
155 GPIO7_IP_GPIO1 | PIN_INPUT_PULLUP,/* XENON_READY */
156 GPIO170_GPIO | PIN_OUTPUT_LOW, /* XENON_CHARGE */
157
158 /* Assistant LED INTERFACE */
159 GPIO21_GPIO | PIN_OUTPUT_LOW, /* XENON_EN1 */
160 GPIO64_IP_GPIO4 | PIN_OUTPUT_LOW, /* XENON_EN2 */
161
162 /* Magnetometer */
163 GPIO31_GPIO | PIN_INPUT_PULLUP, /* magnetometer_INT */
164 GPIO32_GPIO | PIN_INPUT_PULLDOWN, /* Magnetometer DRDY */
165
166 /* Display Interface */
167 GPIO65_GPIO | PIN_OUTPUT_LOW, /* DISP1 RST */
168 GPIO66_GPIO | PIN_OUTPUT_LOW, /* DISP2 RST */
169
170 /* Touch screen INTERFACE */
171 GPIO143_GPIO | PIN_OUTPUT_LOW,/*TOUCH_RST1 */
172
173 /* Touch screen INTERFACE 2 */
174 GPIO67_GPIO | PIN_INPUT_PULLUP, /* TOUCH_INT2 */
175 GPIO146_GPIO | PIN_OUTPUT_LOW,/*TOUCH_RST2 */
176
177 /* ETM_PTM_TRACE INTERFACE */
178 GPIO70_GPIO | PIN_OUTPUT_LOW,/* ETM_PTM_DATA23 */
179 GPIO71_GPIO | PIN_OUTPUT_LOW,/* ETM_PTM_DATA22 */
180 GPIO72_GPIO | PIN_OUTPUT_LOW,/* ETM_PTM_DATA21 */
181 GPIO73_GPIO | PIN_OUTPUT_LOW,/* ETM_PTM_DATA20 */
182 GPIO74_GPIO | PIN_OUTPUT_LOW,/* ETM_PTM_DATA19 */
183
184 /* NAHJ INTERFACE */
185 GPIO76_GPIO | PIN_OUTPUT_LOW,/* NAHJ_CTRL */
186 GPIO216_GPIO | PIN_OUTPUT_HIGH,/* NAHJ_CTRL_INV */
187
188 /* NFC INTERFACE */
189 GPIO77_GPIO | PIN_OUTPUT_LOW, /* NFC_ENA */
190 GPIO144_GPIO | PIN_INPUT_PULLDOWN, /* NFC_IRQ */
191 GPIO142_GPIO | PIN_OUTPUT_LOW, /* NFC_RESET */
192
193 /* Keyboard MATRIX INTERFACE */
194 GPIO90_MC5_CMD | PIN_OUTPUT_LOW, /* KP_O_1 */
195 GPIO87_MC5_DAT1 | PIN_OUTPUT_LOW, /* KP_O_2 */
196 GPIO86_MC5_DAT0 | PIN_OUTPUT_LOW, /* KP_O_3 */
197 GPIO96_KP_O6 | PIN_OUTPUT_LOW, /* KP_O_6 */
198 GPIO94_KP_O7 | PIN_OUTPUT_LOW, /* KP_O_7 */
199 GPIO93_MC5_DAT4 | PIN_INPUT_PULLUP, /* KP_I_0 */
200 GPIO89_MC5_DAT3 | PIN_INPUT_PULLUP, /* KP_I_2 */
201 GPIO88_MC5_DAT2 | PIN_INPUT_PULLUP, /* KP_I_3 */
202 GPIO91_GPIO | PIN_INPUT_PULLUP, /* FORCE_SENSING_INT */
203 GPIO92_GPIO | PIN_OUTPUT_LOW, /* FORCE_SENSING_RST */
204 GPIO97_GPIO | PIN_OUTPUT_LOW, /* FORCE_SENSING_WU */
205
206 /* DiPro Sensor Interface */
207 GPIO139_GPIO | PIN_INPUT_PULLUP, /* DIPRO_INT */
208
209 /* HAL SWITCH INTERFACE */
210 GPIO145_GPIO | PIN_INPUT_PULLDOWN,/* HAL_SW */
211
212 /* Audio Amplifier Interface */
213 GPIO149_GPIO | PIN_OUTPUT_LOW, /* VAUDIO_HF_EN */
214
215 /* GBF INTERFACE */
216 GPIO171_GPIO | PIN_OUTPUT_LOW, /* GBF_ENA_RESET */
217
218 /* MSP : HDTV INTERFACE */
219 GPIO192_GPIO | PIN_INPUT_PULLDOWN,
220
221 /* ACCELEROMETER_INTERFACE */
222 GPIO82_GPIO | PIN_INPUT_PULLUP, /* ACC_INT1 */
223 GPIO83_GPIO | PIN_INPUT_PULLUP, /* ACC_INT2 */
224
225 /* Proximity Sensor */
226 GPIO217_GPIO | PIN_INPUT_PULLUP,
227
228
229};
230
231void __init mop500_pins_init(void)
232{
233 nmk_config_pins(mop500_pins_common,
234 ARRAY_SIZE(mop500_pins_common));
235 if (machine_is_hrefv60())
236 nmk_config_pins(mop500_pins_hrefv60,
237 ARRAY_SIZE(mop500_pins_hrefv60));
238 else
239 nmk_config_pins(mop500_pins_default,
240 ARRAY_SIZE(mop500_pins_default));
241}
diff --git a/arch/arm/mach-ux500/board-mop500-regulators.c b/arch/arm/mach-ux500/board-mop500-regulators.c
index 533967c2d095..875c91b2f8a4 100644
--- a/arch/arm/mach-ux500/board-mop500-regulators.c
+++ b/arch/arm/mach-ux500/board-mop500-regulators.c
@@ -11,6 +11,56 @@
11#include <linux/kernel.h> 11#include <linux/kernel.h>
12#include <linux/regulator/machine.h> 12#include <linux/regulator/machine.h>
13#include <linux/regulator/ab8500.h> 13#include <linux/regulator/ab8500.h>
14#include "board-mop500-regulators.h"
15
16static struct regulator_consumer_supply ab8500_vaux1_consumers[] = {
17 /* External displays, connector on board 2v5 power supply */
18 REGULATOR_SUPPLY("vaux12v5", "mcde.0"),
19 /* SFH7741 proximity sensor */
20 REGULATOR_SUPPLY("vcc", "gpio-keys.0"),
21 /* BH1780GLS ambient light sensor */
22 REGULATOR_SUPPLY("vcc", "2-0029"),
23 /* lsm303dlh accelerometer */
24 REGULATOR_SUPPLY("vdd", "3-0018"),
25 /* lsm303dlh magnetometer */
26 REGULATOR_SUPPLY("vdd", "3-001e"),
27 /* Rohm BU21013 Touchscreen devices */
28 REGULATOR_SUPPLY("avdd", "3-005c"),
29 REGULATOR_SUPPLY("avdd", "3-005d"),
30 /* Synaptics RMI4 Touchscreen device */
31 REGULATOR_SUPPLY("vdd", "3-004b"),
32};
33
34static struct regulator_consumer_supply ab8500_vaux2_consumers[] = {
35 /* On-board eMMC power */
36 REGULATOR_SUPPLY("vmmc", "sdi4"),
37 /* AB8500 audio codec */
38 REGULATOR_SUPPLY("vcc-N2158", "ab8500-codec.0"),
39};
40
41static struct regulator_consumer_supply ab8500_vaux3_consumers[] = {
42 /* External MMC slot power */
43 REGULATOR_SUPPLY("vmmc", "sdi0"),
44};
45
46static struct regulator_consumer_supply ab8500_vtvout_consumers[] = {
47 /* TV-out DENC supply */
48 REGULATOR_SUPPLY("vtvout", "ab8500-denc.0"),
49 /* Internal general-purpose ADC */
50 REGULATOR_SUPPLY("vddadc", "ab8500-gpadc.0"),
51};
52
53static struct regulator_consumer_supply ab8500_vintcore_consumers[] = {
54 /* SoC core supply, no device */
55 REGULATOR_SUPPLY("v-intcore", NULL),
56 /* USB Transciever */
57 REGULATOR_SUPPLY("vddulpivio18", "ab8500-usb.0"),
58};
59
60static struct regulator_consumer_supply ab8500_vana_consumers[] = {
61 /* External displays, connector on board, 1v8 power supply */
62 REGULATOR_SUPPLY("vsmps2", "mcde.0"),
63};
14 64
15/* AB8500 regulators */ 65/* AB8500 regulators */
16struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS] = { 66struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS] = {
@@ -23,6 +73,8 @@ struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS] = {
23 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | 73 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
24 REGULATOR_CHANGE_STATUS, 74 REGULATOR_CHANGE_STATUS,
25 }, 75 },
76 .num_consumer_supplies = ARRAY_SIZE(ab8500_vaux1_consumers),
77 .consumer_supplies = ab8500_vaux1_consumers,
26 }, 78 },
27 /* supplies to the on-board eMMC */ 79 /* supplies to the on-board eMMC */
28 [AB8500_LDO_AUX2] = { 80 [AB8500_LDO_AUX2] = {
@@ -33,6 +85,8 @@ struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS] = {
33 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | 85 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
34 REGULATOR_CHANGE_STATUS, 86 REGULATOR_CHANGE_STATUS,
35 }, 87 },
88 .num_consumer_supplies = ARRAY_SIZE(ab8500_vaux2_consumers),
89 .consumer_supplies = ab8500_vaux2_consumers,
36 }, 90 },
37 /* supply for VAUX3, supplies to SDcard slots */ 91 /* supply for VAUX3, supplies to SDcard slots */
38 [AB8500_LDO_AUX3] = { 92 [AB8500_LDO_AUX3] = {
@@ -43,6 +97,8 @@ struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS] = {
43 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | 97 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
44 REGULATOR_CHANGE_STATUS, 98 REGULATOR_CHANGE_STATUS,
45 }, 99 },
100 .num_consumer_supplies = ARRAY_SIZE(ab8500_vaux3_consumers),
101 .consumer_supplies = ab8500_vaux3_consumers,
46 }, 102 },
47 /* supply for tvout, gpadc, TVOUT LDO */ 103 /* supply for tvout, gpadc, TVOUT LDO */
48 [AB8500_LDO_TVOUT] = { 104 [AB8500_LDO_TVOUT] = {
@@ -50,6 +106,8 @@ struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS] = {
50 .name = "V-TVOUT", 106 .name = "V-TVOUT",
51 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 107 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
52 }, 108 },
109 .num_consumer_supplies = ARRAY_SIZE(ab8500_vtvout_consumers),
110 .consumer_supplies = ab8500_vtvout_consumers,
53 }, 111 },
54 /* supply for ab8500-vaudio, VAUDIO LDO */ 112 /* supply for ab8500-vaudio, VAUDIO LDO */
55 [AB8500_LDO_AUDIO] = { 113 [AB8500_LDO_AUDIO] = {
@@ -85,6 +143,8 @@ struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS] = {
85 .name = "V-INTCORE", 143 .name = "V-INTCORE",
86 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 144 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
87 }, 145 },
146 .num_consumer_supplies = ARRAY_SIZE(ab8500_vintcore_consumers),
147 .consumer_supplies = ab8500_vintcore_consumers,
88 }, 148 },
89 /* supply for U8500 CSI/DSI, VANA LDO */ 149 /* supply for U8500 CSI/DSI, VANA LDO */
90 [AB8500_LDO_ANA] = { 150 [AB8500_LDO_ANA] = {
@@ -92,5 +152,7 @@ struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS] = {
92 .name = "V-CSI/DSI", 152 .name = "V-CSI/DSI",
93 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 153 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
94 }, 154 },
155 .num_consumer_supplies = ARRAY_SIZE(ab8500_vana_consumers),
156 .consumer_supplies = ab8500_vana_consumers,
95 }, 157 },
96}; 158};
diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c
index 4b996676594e..bf0b02414e5b 100644
--- a/arch/arm/mach-ux500/board-mop500-sdi.c
+++ b/arch/arm/mach-ux500/board-mop500-sdi.c
@@ -12,56 +12,14 @@
12#include <linux/mmc/host.h> 12#include <linux/mmc/host.h>
13#include <linux/platform_device.h> 13#include <linux/platform_device.h>
14 14
15#include <plat/pincfg.h> 15#include <asm/mach-types.h>
16#include <plat/ste_dma40.h>
16#include <mach/devices.h> 17#include <mach/devices.h>
17#include <mach/hardware.h> 18#include <mach/hardware.h>
18 19
19#include "devices-db8500.h" 20#include "devices-db8500.h"
20#include "pins-db8500.h"
21#include "board-mop500.h" 21#include "board-mop500.h"
22 22#include "ste-dma40-db8500.h"
23static pin_cfg_t mop500_sdi_pins[] = {
24 /* SDI0 (MicroSD slot) */
25 GPIO18_MC0_CMDDIR,
26 GPIO19_MC0_DAT0DIR,
27 GPIO20_MC0_DAT2DIR,
28 GPIO21_MC0_DAT31DIR,
29 GPIO22_MC0_FBCLK,
30 GPIO23_MC0_CLK,
31 GPIO24_MC0_CMD,
32 GPIO25_MC0_DAT0,
33 GPIO26_MC0_DAT1,
34 GPIO27_MC0_DAT2,
35 GPIO28_MC0_DAT3,
36
37 /* SDI4 (on-board eMMC) */
38 GPIO197_MC4_DAT3,
39 GPIO198_MC4_DAT2,
40 GPIO199_MC4_DAT1,
41 GPIO200_MC4_DAT0,
42 GPIO201_MC4_CMD,
43 GPIO202_MC4_FBCLK,
44 GPIO203_MC4_CLK,
45 GPIO204_MC4_DAT7,
46 GPIO205_MC4_DAT6,
47 GPIO206_MC4_DAT5,
48 GPIO207_MC4_DAT4,
49};
50
51static pin_cfg_t mop500_sdi2_pins[] = {
52 /* SDI2 (POP eMMC) */
53 GPIO128_MC2_CLK,
54 GPIO129_MC2_CMD,
55 GPIO130_MC2_FBCLK,
56 GPIO131_MC2_DAT0,
57 GPIO132_MC2_DAT1,
58 GPIO133_MC2_DAT2,
59 GPIO134_MC2_DAT3,
60 GPIO135_MC2_DAT4,
61 GPIO136_MC2_DAT5,
62 GPIO137_MC2_DAT6,
63 GPIO138_MC2_DAT7,
64};
65 23
66/* 24/*
67 * SDI 0 (MicroSD slot) 25 * SDI 0 (MicroSD slot)
@@ -86,48 +44,134 @@ static u32 mop500_sdi0_vdd_handler(struct device *dev, unsigned int vdd,
86 MCI_DATA2DIREN | MCI_DATA31DIREN; 44 MCI_DATA2DIREN | MCI_DATA31DIREN;
87} 45}
88 46
47#ifdef CONFIG_STE_DMA40
48struct stedma40_chan_cfg mop500_sdi0_dma_cfg_rx = {
49 .mode = STEDMA40_MODE_LOGICAL,
50 .dir = STEDMA40_PERIPH_TO_MEM,
51 .src_dev_type = DB8500_DMA_DEV29_SD_MM0_RX,
52 .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
53 .src_info.data_width = STEDMA40_WORD_WIDTH,
54 .dst_info.data_width = STEDMA40_WORD_WIDTH,
55};
56
57static struct stedma40_chan_cfg mop500_sdi0_dma_cfg_tx = {
58 .mode = STEDMA40_MODE_LOGICAL,
59 .dir = STEDMA40_MEM_TO_PERIPH,
60 .src_dev_type = STEDMA40_DEV_SRC_MEMORY,
61 .dst_dev_type = DB8500_DMA_DEV29_SD_MM0_TX,
62 .src_info.data_width = STEDMA40_WORD_WIDTH,
63 .dst_info.data_width = STEDMA40_WORD_WIDTH,
64};
65#endif
66
89static struct mmci_platform_data mop500_sdi0_data = { 67static struct mmci_platform_data mop500_sdi0_data = {
90 .vdd_handler = mop500_sdi0_vdd_handler, 68 .vdd_handler = mop500_sdi0_vdd_handler,
91 .ocr_mask = MMC_VDD_29_30, 69 .ocr_mask = MMC_VDD_29_30,
92 .f_max = 100000000, 70 .f_max = 100000000,
93 .capabilities = MMC_CAP_4_BIT_DATA, 71 .capabilities = MMC_CAP_4_BIT_DATA,
94 .gpio_cd = GPIO_SDMMC_CD,
95 .gpio_wp = -1, 72 .gpio_wp = -1,
73#ifdef CONFIG_STE_DMA40
74 .dma_filter = stedma40_filter,
75 .dma_rx_param = &mop500_sdi0_dma_cfg_rx,
76 .dma_tx_param = &mop500_sdi0_dma_cfg_tx,
77#endif
96}; 78};
97 79
98void mop500_sdi_tc35892_init(void) 80/* GPIO pins used by the sdi0 level shifter */
81static int sdi0_en = -1;
82static int sdi0_vsel = -1;
83
84static void sdi0_configure(void)
99{ 85{
100 int ret; 86 int ret;
101 87
102 ret = gpio_request(GPIO_SDMMC_EN, "SDMMC_EN"); 88 ret = gpio_request(sdi0_en, "level shifter enable");
103 if (!ret) 89 if (!ret)
104 ret = gpio_request(GPIO_SDMMC_1V8_3V_SEL, 90 ret = gpio_request(sdi0_vsel,
105 "GPIO_SDMMC_1V8_3V_SEL"); 91 "level shifter 1v8-3v select");
106 if (ret) 92
93 if (ret) {
94 pr_warning("unable to config sdi0 gpios for level shifter.\n");
107 return; 95 return;
96 }
108 97
109 gpio_direction_output(GPIO_SDMMC_1V8_3V_SEL, 1); 98 /* Select the default 2.9V and enable level shifter */
110 gpio_direction_output(GPIO_SDMMC_EN, 0); 99 gpio_direction_output(sdi0_vsel, 0);
100 gpio_direction_output(sdi0_en, 1);
111 101
102 /* Add the device */
112 db8500_add_sdi0(&mop500_sdi0_data); 103 db8500_add_sdi0(&mop500_sdi0_data);
113} 104}
114 105
106void mop500_sdi_tc35892_init(void)
107{
108 mop500_sdi0_data.gpio_cd = GPIO_SDMMC_CD;
109 sdi0_en = GPIO_SDMMC_EN;
110 sdi0_vsel = GPIO_SDMMC_1V8_3V_SEL;
111 sdi0_configure();
112}
113
115/* 114/*
116 * SDI 2 (POP eMMC, not on DB8500ed) 115 * SDI 2 (POP eMMC, not on DB8500ed)
117 */ 116 */
118 117
118#ifdef CONFIG_STE_DMA40
119struct stedma40_chan_cfg mop500_sdi2_dma_cfg_rx = {
120 .mode = STEDMA40_MODE_LOGICAL,
121 .dir = STEDMA40_PERIPH_TO_MEM,
122 .src_dev_type = DB8500_DMA_DEV28_SD_MM2_RX,
123 .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
124 .src_info.data_width = STEDMA40_WORD_WIDTH,
125 .dst_info.data_width = STEDMA40_WORD_WIDTH,
126};
127
128static struct stedma40_chan_cfg mop500_sdi2_dma_cfg_tx = {
129 .mode = STEDMA40_MODE_LOGICAL,
130 .dir = STEDMA40_MEM_TO_PERIPH,
131 .src_dev_type = STEDMA40_DEV_SRC_MEMORY,
132 .dst_dev_type = DB8500_DMA_DEV28_SD_MM2_TX,
133 .src_info.data_width = STEDMA40_WORD_WIDTH,
134 .dst_info.data_width = STEDMA40_WORD_WIDTH,
135};
136#endif
137
119static struct mmci_platform_data mop500_sdi2_data = { 138static struct mmci_platform_data mop500_sdi2_data = {
120 .ocr_mask = MMC_VDD_165_195, 139 .ocr_mask = MMC_VDD_165_195,
121 .f_max = 100000000, 140 .f_max = 100000000,
122 .capabilities = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, 141 .capabilities = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
123 .gpio_cd = -1, 142 .gpio_cd = -1,
124 .gpio_wp = -1, 143 .gpio_wp = -1,
144#ifdef CONFIG_STE_DMA40
145 .dma_filter = stedma40_filter,
146 .dma_rx_param = &mop500_sdi2_dma_cfg_rx,
147 .dma_tx_param = &mop500_sdi2_dma_cfg_tx,
148#endif
125}; 149};
126 150
127/* 151/*
128 * SDI 4 (on-board eMMC) 152 * SDI 4 (on-board eMMC)
129 */ 153 */
130 154
155#ifdef CONFIG_STE_DMA40
156struct stedma40_chan_cfg mop500_sdi4_dma_cfg_rx = {
157 .mode = STEDMA40_MODE_LOGICAL,
158 .dir = STEDMA40_PERIPH_TO_MEM,
159 .src_dev_type = DB8500_DMA_DEV42_SD_MM4_RX,
160 .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
161 .src_info.data_width = STEDMA40_WORD_WIDTH,
162 .dst_info.data_width = STEDMA40_WORD_WIDTH,
163};
164
165static struct stedma40_chan_cfg mop500_sdi4_dma_cfg_tx = {
166 .mode = STEDMA40_MODE_LOGICAL,
167 .dir = STEDMA40_MEM_TO_PERIPH,
168 .src_dev_type = STEDMA40_DEV_SRC_MEMORY,
169 .dst_dev_type = DB8500_DMA_DEV42_SD_MM4_TX,
170 .src_info.data_width = STEDMA40_WORD_WIDTH,
171 .dst_info.data_width = STEDMA40_WORD_WIDTH,
172};
173#endif
174
131static struct mmci_platform_data mop500_sdi4_data = { 175static struct mmci_platform_data mop500_sdi4_data = {
132 .ocr_mask = MMC_VDD_29_30, 176 .ocr_mask = MMC_VDD_29_30,
133 .f_max = 100000000, 177 .f_max = 100000000,
@@ -135,26 +179,32 @@ static struct mmci_platform_data mop500_sdi4_data = {
135 MMC_CAP_MMC_HIGHSPEED, 179 MMC_CAP_MMC_HIGHSPEED,
136 .gpio_cd = -1, 180 .gpio_cd = -1,
137 .gpio_wp = -1, 181 .gpio_wp = -1,
182#ifdef CONFIG_STE_DMA40
183 .dma_filter = stedma40_filter,
184 .dma_rx_param = &mop500_sdi4_dma_cfg_rx,
185 .dma_tx_param = &mop500_sdi4_dma_cfg_tx,
186#endif
138}; 187};
139 188
140void __init mop500_sdi_init(void) 189void __init mop500_sdi_init(void)
141{ 190{
142 nmk_config_pins(mop500_sdi_pins, ARRAY_SIZE(mop500_sdi_pins)); 191 /* PoP:ed eMMC on top of DB8500 v1.0 has problems with high speed */
192 if (!cpu_is_u8500v10())
193 mop500_sdi2_data.capabilities |= MMC_CAP_MMC_HIGHSPEED;
194 db8500_add_sdi2(&mop500_sdi2_data);
195
196 /* On-board eMMC */
197 db8500_add_sdi4(&mop500_sdi4_data);
143 198
199 if (machine_is_hrefv60()) {
200 mop500_sdi0_data.gpio_cd = HREFV60_SDMMC_CD_GPIO;
201 sdi0_en = HREFV60_SDMMC_EN_GPIO;
202 sdi0_vsel = HREFV60_SDMMC_1V8_3V_GPIO;
203 sdi0_configure();
204 }
144 /* 205 /*
145 * sdi0 will finally be added when the TC35892 initializes and calls 206 * On boards with the TC35892 GPIO expander, sdi0 will finally
207 * be added when the TC35892 initializes and calls
146 * mop500_sdi_tc35892_init() above. 208 * mop500_sdi_tc35892_init() above.
147 */ 209 */
148
149 /* PoP:ed eMMC */
150 if (!cpu_is_u8500ed()) {
151 nmk_config_pins(mop500_sdi2_pins, ARRAY_SIZE(mop500_sdi2_pins));
152 /* POP eMMC on v1.0 has problems with high speed */
153 if (!cpu_is_u8500v10())
154 mop500_sdi2_data.capabilities |= MMC_CAP_MMC_HIGHSPEED;
155 db8500_add_sdi2(&mop500_sdi2_data);
156 }
157
158 /* On-board eMMC */
159 db8500_add_sdi4(&mop500_sdi4_data);
160} 210}
diff --git a/arch/arm/mach-ux500/board-mop500-stuib.c b/arch/arm/mach-ux500/board-mop500-stuib.c
new file mode 100644
index 000000000000..8c979770d872
--- /dev/null
+++ b/arch/arm/mach-ux500/board-mop500-stuib.c
@@ -0,0 +1,205 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License terms: GNU General Public License (GPL), version 2
5 */
6
7#include <linux/kernel.h>
8#include <linux/init.h>
9#include <linux/mfd/stmpe.h>
10#include <linux/input/bu21013.h>
11#include <linux/gpio.h>
12#include <linux/interrupt.h>
13#include <linux/i2c.h>
14#include <linux/input/matrix_keypad.h>
15#include <asm/mach-types.h>
16
17#include "board-mop500.h"
18
19/* STMPE/SKE keypad use this key layout */
20static const unsigned int mop500_keymap[] = {
21 KEY(2, 5, KEY_END),
22 KEY(4, 1, KEY_POWER),
23 KEY(3, 5, KEY_VOLUMEDOWN),
24 KEY(1, 3, KEY_3),
25 KEY(5, 2, KEY_RIGHT),
26 KEY(5, 0, KEY_9),
27
28 KEY(0, 5, KEY_MENU),
29 KEY(7, 6, KEY_ENTER),
30 KEY(4, 5, KEY_0),
31 KEY(6, 7, KEY_2),
32 KEY(3, 4, KEY_UP),
33 KEY(3, 3, KEY_DOWN),
34
35 KEY(6, 4, KEY_SEND),
36 KEY(6, 2, KEY_BACK),
37 KEY(4, 2, KEY_VOLUMEUP),
38 KEY(5, 5, KEY_1),
39 KEY(4, 3, KEY_LEFT),
40 KEY(3, 2, KEY_7),
41};
42
43static const struct matrix_keymap_data mop500_keymap_data = {
44 .keymap = mop500_keymap,
45 .keymap_size = ARRAY_SIZE(mop500_keymap),
46};
47/*
48 * STMPE1601
49 */
50static struct stmpe_keypad_platform_data stmpe1601_keypad_data = {
51 .debounce_ms = 64,
52 .scan_count = 8,
53 .no_autorepeat = true,
54 .keymap_data = &mop500_keymap_data,
55};
56
57static struct stmpe_platform_data stmpe1601_data = {
58 .id = 1,
59 .blocks = STMPE_BLOCK_KEYPAD,
60 .irq_trigger = IRQF_TRIGGER_FALLING,
61 .irq_base = MOP500_STMPE1601_IRQ(0),
62 .keypad = &stmpe1601_keypad_data,
63 .autosleep = true,
64 .autosleep_timeout = 1024,
65};
66
67static struct i2c_board_info __initdata mop500_i2c0_devices_stuib[] = {
68 {
69 I2C_BOARD_INFO("stmpe1601", 0x40),
70 .irq = NOMADIK_GPIO_TO_IRQ(218),
71 .platform_data = &stmpe1601_data,
72 .flags = I2C_CLIENT_WAKE,
73 },
74};
75
76/*
77 * BU21013 ROHM touchscreen interface on the STUIBs
78 */
79
80/* tracks number of bu21013 devices being enabled */
81static int bu21013_devices;
82
83#define TOUCH_GPIO_PIN 84
84
85#define TOUCH_XMAX 384
86#define TOUCH_YMAX 704
87
88#define PRCMU_CLOCK_OCR 0x1CC
89#define TSC_EXT_CLOCK_9_6MHZ 0x840000
90
91/**
92 * bu21013_gpio_board_init : configures the touch panel.
93 * @reset_pin: reset pin number
94 * This function can be used to configures
95 * the voltage and reset the touch panel controller.
96 */
97static int bu21013_gpio_board_init(int reset_pin)
98{
99 int retval = 0;
100
101 bu21013_devices++;
102 if (bu21013_devices == 1) {
103 retval = gpio_request(reset_pin, "touchp_reset");
104 if (retval) {
105 printk(KERN_ERR "Unable to request gpio reset_pin");
106 return retval;
107 }
108 retval = gpio_direction_output(reset_pin, 1);
109 if (retval < 0) {
110 printk(KERN_ERR "%s: gpio direction failed\n",
111 __func__);
112 return retval;
113 }
114 }
115
116 return retval;
117}
118
119/**
120 * bu21013_gpio_board_exit : deconfigures the touch panel controller
121 * @reset_pin: reset pin number
122 * This function can be used to deconfigures the chip selection
123 * for touch panel controller.
124 */
125static int bu21013_gpio_board_exit(int reset_pin)
126{
127 int retval = 0;
128
129 if (bu21013_devices == 1) {
130 retval = gpio_direction_output(reset_pin, 0);
131 if (retval < 0) {
132 printk(KERN_ERR "%s: gpio direction failed\n",
133 __func__);
134 return retval;
135 }
136 gpio_set_value(reset_pin, 0);
137 }
138 bu21013_devices--;
139
140 return retval;
141}
142
143/**
144 * bu21013_read_pin_val : get the interrupt pin value
145 * This function can be used to get the interrupt pin value for touch panel
146 * controller.
147 */
148static int bu21013_read_pin_val(void)
149{
150 return gpio_get_value(TOUCH_GPIO_PIN);
151}
152
153static struct bu21013_platform_device tsc_plat_device = {
154 .cs_en = bu21013_gpio_board_init,
155 .cs_dis = bu21013_gpio_board_exit,
156 .irq_read_val = bu21013_read_pin_val,
157 .irq = NOMADIK_GPIO_TO_IRQ(TOUCH_GPIO_PIN),
158 .touch_x_max = TOUCH_XMAX,
159 .touch_y_max = TOUCH_YMAX,
160 .ext_clk = false,
161 .x_flip = false,
162 .y_flip = true,
163};
164
165static struct bu21013_platform_device tsc_plat2_device = {
166 .cs_en = bu21013_gpio_board_init,
167 .cs_dis = bu21013_gpio_board_exit,
168 .irq_read_val = bu21013_read_pin_val,
169 .irq = NOMADIK_GPIO_TO_IRQ(TOUCH_GPIO_PIN),
170 .touch_x_max = TOUCH_XMAX,
171 .touch_y_max = TOUCH_YMAX,
172 .ext_clk = false,
173 .x_flip = false,
174 .y_flip = true,
175};
176
177static struct i2c_board_info __initdata u8500_i2c3_devices_stuib[] = {
178 {
179 I2C_BOARD_INFO("bu21013_tp", 0x5C),
180 .platform_data = &tsc_plat_device,
181 },
182 {
183 I2C_BOARD_INFO("bu21013_tp", 0x5D),
184 .platform_data = &tsc_plat2_device,
185 },
186
187};
188
189void __init mop500_stuib_init(void)
190{
191 if (machine_is_hrefv60()) {
192 tsc_plat_device.cs_pin = HREFV60_TOUCH_RST_GPIO;
193 tsc_plat2_device.cs_pin = HREFV60_TOUCH_RST_GPIO;
194 } else {
195 tsc_plat_device.cs_pin = GPIO_BU21013_CS;
196 tsc_plat2_device.cs_pin = GPIO_BU21013_CS;
197
198 }
199
200 mop500_uib_i2c_add(0, mop500_i2c0_devices_stuib,
201 ARRAY_SIZE(mop500_i2c0_devices_stuib));
202
203 mop500_uib_i2c_add(3, u8500_i2c3_devices_stuib,
204 ARRAY_SIZE(u8500_i2c3_devices_stuib));
205}
diff --git a/arch/arm/mach-ux500/board-mop500-u8500uib.c b/arch/arm/mach-ux500/board-mop500-u8500uib.c
new file mode 100644
index 000000000000..d8a8734a0eba
--- /dev/null
+++ b/arch/arm/mach-ux500/board-mop500-u8500uib.c
@@ -0,0 +1,111 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * Board data for the U8500 UIB, also known as the New UIB
5 * License terms: GNU General Public License (GPL), version 2
6 */
7
8#include <linux/kernel.h>
9#include <linux/init.h>
10#include <linux/i2c.h>
11#include <linux/gpio.h>
12#include <linux/interrupt.h>
13#include <linux/mfd/tc3589x.h>
14#include <linux/input/matrix_keypad.h>
15#include <../drivers/staging/ste_rmi4/synaptics_i2c_rmi4.h>
16
17#include <mach/gpio.h>
18#include <mach/irqs.h>
19
20#include "board-mop500.h"
21
22/*
23 * Synaptics RMI4 touchscreen interface on the U8500 UIB
24 */
25
26/*
27 * Descriptor structure.
28 * Describes the number of i2c devices on the bus that speak RMI.
29 */
30static struct synaptics_rmi4_platform_data rmi4_i2c_dev_platformdata = {
31 .irq_number = NOMADIK_GPIO_TO_IRQ(84),
32 .irq_type = (IRQF_TRIGGER_FALLING | IRQF_SHARED),
33 .x_flip = false,
34 .y_flip = true,
35 .regulator_en = false,
36};
37
38static struct i2c_board_info __initdata mop500_i2c3_devices_u8500[] = {
39 {
40 I2C_BOARD_INFO("synaptics_rmi4_i2c", 0x4B),
41 .platform_data = &rmi4_i2c_dev_platformdata,
42 },
43};
44
45/*
46 * TC35893
47 */
48static const unsigned int u8500_keymap[] = {
49 KEY(3, 1, KEY_END),
50 KEY(4, 1, KEY_POWER),
51 KEY(6, 4, KEY_VOLUMEDOWN),
52 KEY(4, 2, KEY_EMAIL),
53 KEY(3, 3, KEY_RIGHT),
54 KEY(2, 5, KEY_BACKSPACE),
55
56 KEY(6, 7, KEY_MENU),
57 KEY(5, 0, KEY_ENTER),
58 KEY(4, 3, KEY_0),
59 KEY(3, 4, KEY_DOT),
60 KEY(5, 2, KEY_UP),
61 KEY(3, 5, KEY_DOWN),
62
63 KEY(4, 5, KEY_SEND),
64 KEY(0, 5, KEY_BACK),
65 KEY(6, 2, KEY_VOLUMEUP),
66 KEY(1, 3, KEY_SPACE),
67 KEY(7, 6, KEY_LEFT),
68 KEY(5, 5, KEY_SEARCH),
69};
70
71static struct matrix_keymap_data u8500_keymap_data = {
72 .keymap = u8500_keymap,
73 .keymap_size = ARRAY_SIZE(u8500_keymap),
74};
75
76static struct tc3589x_keypad_platform_data tc35893_data = {
77 .krow = TC_KPD_ROWS,
78 .kcol = TC_KPD_COLUMNS,
79 .debounce_period = TC_KPD_DEBOUNCE_PERIOD,
80 .settle_time = TC_KPD_SETTLE_TIME,
81 .irqtype = IRQF_TRIGGER_FALLING,
82 .enable_wakeup = true,
83 .keymap_data = &u8500_keymap_data,
84 .no_autorepeat = true,
85};
86
87static struct tc3589x_platform_data tc3589x_keypad_data = {
88 .block = TC3589x_BLOCK_KEYPAD,
89 .keypad = &tc35893_data,
90 .irq_base = MOP500_EGPIO_IRQ_BASE,
91};
92
93static struct i2c_board_info __initdata mop500_i2c0_devices_u8500[] = {
94 {
95 I2C_BOARD_INFO("tc3589x", 0x44),
96 .platform_data = &tc3589x_keypad_data,
97 .irq = NOMADIK_GPIO_TO_IRQ(218),
98 .flags = I2C_CLIENT_WAKE,
99 },
100};
101
102
103void __init mop500_u8500uib_init(void)
104{
105 mop500_uib_i2c_add(3, mop500_i2c3_devices_u8500,
106 ARRAY_SIZE(mop500_i2c3_devices_u8500));
107
108 mop500_uib_i2c_add(0, mop500_i2c0_devices_u8500,
109 ARRAY_SIZE(mop500_i2c0_devices_u8500));
110
111}
diff --git a/arch/arm/mach-ux500/board-mop500-uib.c b/arch/arm/mach-ux500/board-mop500-uib.c
new file mode 100644
index 000000000000..69cce41f602a
--- /dev/null
+++ b/arch/arm/mach-ux500/board-mop500-uib.c
@@ -0,0 +1,135 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
5 * License terms: GNU General Public License (GPL), version 2
6 */
7
8#define pr_fmt(fmt) "mop500-uib: " fmt
9
10#include <linux/kernel.h>
11#include <linux/init.h>
12#include <linux/i2c.h>
13
14#include <mach/hardware.h>
15#include "board-mop500.h"
16
17enum mop500_uib {
18 STUIB,
19 U8500UIB,
20};
21
22struct uib {
23 const char *name;
24 const char *option;
25 void (*init)(void);
26};
27
28static struct __initdata uib mop500_uibs[] = {
29 [STUIB] = {
30 .name = "ST-UIB",
31 .option = "stuib",
32 .init = mop500_stuib_init,
33 },
34 [U8500UIB] = {
35 .name = "U8500-UIB",
36 .option = "u8500uib",
37 .init = mop500_u8500uib_init,
38 },
39};
40
41static struct uib *mop500_uib;
42
43static int __init mop500_uib_setup(char *str)
44{
45 int i;
46
47 for (i = 0; i < ARRAY_SIZE(mop500_uibs); i++) {
48 struct uib *uib = &mop500_uibs[i];
49
50 if (!strcmp(str, uib->option)) {
51 mop500_uib = uib;
52 break;
53 }
54 }
55
56 if (i == ARRAY_SIZE(mop500_uibs))
57 pr_err("invalid uib= option (%s)\n", str);
58
59 return 1;
60}
61__setup("uib=", mop500_uib_setup);
62
63/*
64 * The UIBs are detected after the I2C host controllers are registered, so
65 * i2c_register_board_info() can't be used.
66 */
67void mop500_uib_i2c_add(int busnum, struct i2c_board_info *info,
68 unsigned n)
69{
70 struct i2c_adapter *adap;
71 struct i2c_client *client;
72 int i;
73
74 adap = i2c_get_adapter(busnum);
75 if (!adap) {
76 pr_err("failed to get adapter i2c%d\n", busnum);
77 return;
78 }
79
80 for (i = 0; i < n; i++) {
81 client = i2c_new_device(adap, &info[i]);
82 if (!client)
83 pr_err("failed to register %s to i2c%d\n",
84 info[i].type, busnum);
85 }
86
87 i2c_put_adapter(adap);
88}
89
90static void __init __mop500_uib_init(struct uib *uib, const char *why)
91{
92 pr_info("%s (%s)\n", uib->name, why);
93 uib->init();
94}
95
96/*
97 * Detect the UIB attached based on the presence or absence of i2c devices.
98 */
99static int __init mop500_uib_init(void)
100{
101 struct uib *uib = mop500_uib;
102 struct i2c_adapter *i2c0;
103 int ret;
104
105 if (!cpu_is_u8500())
106 return -ENODEV;
107
108 if (uib) {
109 __mop500_uib_init(uib, "from uib= boot argument");
110 return 0;
111 }
112
113 i2c0 = i2c_get_adapter(0);
114 if (!i2c0) {
115 __mop500_uib_init(&mop500_uibs[STUIB],
116 "fallback, could not get i2c0");
117 return -ENODEV;
118 }
119
120 /* U8500-UIB has the TC35893 at 0x44 on I2C0, the ST-UIB doesn't. */
121 ret = i2c_smbus_xfer(i2c0, 0x44, 0, I2C_SMBUS_WRITE, 0,
122 I2C_SMBUS_QUICK, NULL);
123 i2c_put_adapter(i2c0);
124
125 if (ret == 0)
126 uib = &mop500_uibs[U8500UIB];
127 else
128 uib = &mop500_uibs[STUIB];
129
130 __mop500_uib_init(uib, "detected");
131
132 return 0;
133}
134
135module_init(mop500_uib_init);
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index a393f57ed2a8..8790d984cac8 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -17,68 +17,30 @@
17#include <linux/gpio.h> 17#include <linux/gpio.h>
18#include <linux/amba/bus.h> 18#include <linux/amba/bus.h>
19#include <linux/amba/pl022.h> 19#include <linux/amba/pl022.h>
20#include <linux/amba/serial.h>
20#include <linux/spi/spi.h> 21#include <linux/spi/spi.h>
21#include <linux/mfd/ab8500.h> 22#include <linux/mfd/ab8500.h>
22#include <linux/mfd/tc3589x.h> 23#include <linux/mfd/tc3589x.h>
24#include <linux/leds-lp5521.h>
25#include <linux/input.h>
26#include <linux/gpio_keys.h>
23 27
24#include <asm/mach-types.h> 28#include <asm/mach-types.h>
25#include <asm/mach/arch.h> 29#include <asm/mach/arch.h>
26 30
27#include <plat/pincfg.h>
28#include <plat/i2c.h> 31#include <plat/i2c.h>
32#include <plat/ste_dma40.h>
29 33
30#include <mach/hardware.h> 34#include <mach/hardware.h>
31#include <mach/setup.h> 35#include <mach/setup.h>
32#include <mach/devices.h> 36#include <mach/devices.h>
33#include <mach/irqs.h> 37#include <mach/irqs.h>
34 38
39#include "ste-dma40-db8500.h"
35#include "devices-db8500.h" 40#include "devices-db8500.h"
36#include "pins-db8500.h"
37#include "board-mop500.h" 41#include "board-mop500.h"
38#include "board-mop500-regulators.h" 42#include "board-mop500-regulators.h"
39 43
40static pin_cfg_t mop500_pins[] = {
41 /* SSP0 */
42 GPIO143_SSP0_CLK,
43 GPIO144_SSP0_FRM,
44 GPIO145_SSP0_RXD,
45 GPIO146_SSP0_TXD,
46
47 /* I2C */
48 GPIO147_I2C0_SCL,
49 GPIO148_I2C0_SDA,
50 GPIO16_I2C1_SCL,
51 GPIO17_I2C1_SDA,
52 GPIO10_I2C2_SDA,
53 GPIO11_I2C2_SCL,
54 GPIO229_I2C3_SDA,
55 GPIO230_I2C3_SCL,
56
57 /* SKE keypad */
58 GPIO153_KP_I7,
59 GPIO154_KP_I6,
60 GPIO155_KP_I5,
61 GPIO156_KP_I4,
62 GPIO157_KP_O7,
63 GPIO158_KP_O6,
64 GPIO159_KP_O5,
65 GPIO160_KP_O4,
66 GPIO161_KP_I3,
67 GPIO162_KP_I2,
68 GPIO163_KP_I1,
69 GPIO164_KP_I0,
70 GPIO165_KP_O3,
71 GPIO166_KP_O2,
72 GPIO167_KP_O1,
73 GPIO168_KP_O0,
74
75 /* GPIO_EXP_INT */
76 GPIO217_GPIO,
77
78 /* STMPE1601 IRQ */
79 GPIO218_GPIO | PIN_INPUT_PULLUP,
80};
81
82static struct ab8500_platform_data ab8500_platdata = { 44static struct ab8500_platform_data ab8500_platdata = {
83 .irq_base = MOP500_AB8500_IRQ_BASE, 45 .irq_base = MOP500_AB8500_IRQ_BASE,
84 .regulator = ab8500_regulators, 46 .regulator = ab8500_regulators,
@@ -103,16 +65,6 @@ struct platform_device ab8500_device = {
103 .resource = ab8500_resources, 65 .resource = ab8500_resources,
104}; 66};
105 67
106static struct pl022_ssp_controller ssp0_platform_data = {
107 .bus_id = 0,
108 /* pl022 not yet supports dma */
109 .enable_dma = 0,
110 /* on this platform, gpio 31,142,144,214 &
111 * 224 are connected as chip selects
112 */
113 .num_chipselect = 5,
114};
115
116/* 68/*
117 * TC35892 69 * TC35892
118 */ 70 */
@@ -133,14 +85,81 @@ static struct tc3589x_platform_data mop500_tc35892_data = {
133 .irq_base = MOP500_EGPIO_IRQ_BASE, 85 .irq_base = MOP500_EGPIO_IRQ_BASE,
134}; 86};
135 87
88static struct lp5521_led_config lp5521_pri_led[] = {
89 [0] = {
90 .chan_nr = 0,
91 .led_current = 0x2f,
92 .max_current = 0x5f,
93 },
94 [1] = {
95 .chan_nr = 1,
96 .led_current = 0x2f,
97 .max_current = 0x5f,
98 },
99 [2] = {
100 .chan_nr = 2,
101 .led_current = 0x2f,
102 .max_current = 0x5f,
103 },
104};
105
106static struct lp5521_platform_data __initdata lp5521_pri_data = {
107 .label = "lp5521_pri",
108 .led_config = &lp5521_pri_led[0],
109 .num_channels = 3,
110 .clock_mode = LP5521_CLOCK_EXT,
111};
112
113static struct lp5521_led_config lp5521_sec_led[] = {
114 [0] = {
115 .chan_nr = 0,
116 .led_current = 0x2f,
117 .max_current = 0x5f,
118 },
119 [1] = {
120 .chan_nr = 1,
121 .led_current = 0x2f,
122 .max_current = 0x5f,
123 },
124 [2] = {
125 .chan_nr = 2,
126 .led_current = 0x2f,
127 .max_current = 0x5f,
128 },
129};
130
131static struct lp5521_platform_data __initdata lp5521_sec_data = {
132 .label = "lp5521_sec",
133 .led_config = &lp5521_sec_led[0],
134 .num_channels = 3,
135 .clock_mode = LP5521_CLOCK_EXT,
136};
137
136static struct i2c_board_info mop500_i2c0_devices[] = { 138static struct i2c_board_info mop500_i2c0_devices[] = {
137 { 139 {
138 I2C_BOARD_INFO("tc3589x", 0x42), 140 I2C_BOARD_INFO("tc3589x", 0x42),
139 .irq = NOMADIK_GPIO_TO_IRQ(217), 141 .irq = NOMADIK_GPIO_TO_IRQ(217),
140 .platform_data = &mop500_tc35892_data, 142 .platform_data = &mop500_tc35892_data,
141 }, 143 },
142}; 144};
143 145
146static struct i2c_board_info __initdata mop500_i2c2_devices[] = {
147 {
148 /* lp5521 LED driver, 1st device */
149 I2C_BOARD_INFO("lp5521", 0x33),
150 .platform_data = &lp5521_pri_data,
151 },
152 {
153 /* lp5521 LED driver, 2st device */
154 I2C_BOARD_INFO("lp5521", 0x34),
155 .platform_data = &lp5521_sec_data,
156 },
157 {
158 /* Light sensor Rohm BH1780GLI */
159 I2C_BOARD_INFO("bh1780", 0x29),
160 },
161};
162
144#define U8500_I2C_CONTROLLER(id, _slsu, _tft, _rft, clk, _sm) \ 163#define U8500_I2C_CONTROLLER(id, _slsu, _tft, _rft, clk, _sm) \
145static struct nmk_i2c_controller u8500_i2c##id##_data = { \ 164static struct nmk_i2c_controller u8500_i2c##id##_data = { \
146 /* \ 165 /* \
@@ -178,8 +197,93 @@ static void __init mop500_i2c_init(void)
178 db8500_add_i2c3(&u8500_i2c3_data); 197 db8500_add_i2c3(&u8500_i2c3_data);
179} 198}
180 199
200static struct gpio_keys_button mop500_gpio_keys[] = {
201 {
202 .desc = "SFH7741 Proximity Sensor",
203 .type = EV_SW,
204 .code = SW_FRONT_PROXIMITY,
205 .active_low = 0,
206 .can_disable = 1,
207 }
208};
209
210static struct regulator *prox_regulator;
211static int mop500_prox_activate(struct device *dev);
212static void mop500_prox_deactivate(struct device *dev);
213
214static struct gpio_keys_platform_data mop500_gpio_keys_data = {
215 .buttons = mop500_gpio_keys,
216 .nbuttons = ARRAY_SIZE(mop500_gpio_keys),
217 .enable = mop500_prox_activate,
218 .disable = mop500_prox_deactivate,
219};
220
221static struct platform_device mop500_gpio_keys_device = {
222 .name = "gpio-keys",
223 .id = 0,
224 .dev = {
225 .platform_data = &mop500_gpio_keys_data,
226 },
227};
228
229static int mop500_prox_activate(struct device *dev)
230{
231 prox_regulator = regulator_get(&mop500_gpio_keys_device.dev,
232 "vcc");
233 if (IS_ERR(prox_regulator)) {
234 dev_err(&mop500_gpio_keys_device.dev,
235 "no regulator\n");
236 return PTR_ERR(prox_regulator);
237 }
238 regulator_enable(prox_regulator);
239 return 0;
240}
241
242static void mop500_prox_deactivate(struct device *dev)
243{
244 regulator_disable(prox_regulator);
245 regulator_put(prox_regulator);
246}
247
181/* add any platform devices here - TODO */ 248/* add any platform devices here - TODO */
182static struct platform_device *platform_devs[] __initdata = { 249static struct platform_device *platform_devs[] __initdata = {
250 &mop500_gpio_keys_device,
251};
252
253#ifdef CONFIG_STE_DMA40
254static struct stedma40_chan_cfg ssp0_dma_cfg_rx = {
255 .mode = STEDMA40_MODE_LOGICAL,
256 .dir = STEDMA40_PERIPH_TO_MEM,
257 .src_dev_type = DB8500_DMA_DEV8_SSP0_RX,
258 .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
259 .src_info.data_width = STEDMA40_BYTE_WIDTH,
260 .dst_info.data_width = STEDMA40_BYTE_WIDTH,
261};
262
263static struct stedma40_chan_cfg ssp0_dma_cfg_tx = {
264 .mode = STEDMA40_MODE_LOGICAL,
265 .dir = STEDMA40_MEM_TO_PERIPH,
266 .src_dev_type = STEDMA40_DEV_SRC_MEMORY,
267 .dst_dev_type = DB8500_DMA_DEV8_SSP0_TX,
268 .src_info.data_width = STEDMA40_BYTE_WIDTH,
269 .dst_info.data_width = STEDMA40_BYTE_WIDTH,
270};
271#endif
272
273static struct pl022_ssp_controller ssp0_platform_data = {
274 .bus_id = 0,
275#ifdef CONFIG_STE_DMA40
276 .enable_dma = 1,
277 .dma_filter = stedma40_filter,
278 .dma_rx_param = &ssp0_dma_cfg_rx,
279 .dma_tx_param = &ssp0_dma_cfg_tx,
280#else
281 .enable_dma = 0,
282#endif
283 /* on this platform, gpio 31,142,144,214 &
284 * 224 are connected as chip selects
285 */
286 .num_chipselect = 5,
183}; 287};
184 288
185static void __init mop500_spi_init(void) 289static void __init mop500_spi_init(void)
@@ -187,18 +291,108 @@ static void __init mop500_spi_init(void)
187 db8500_add_ssp0(&ssp0_platform_data); 291 db8500_add_ssp0(&ssp0_platform_data);
188} 292}
189 293
294#ifdef CONFIG_STE_DMA40
295static struct stedma40_chan_cfg uart0_dma_cfg_rx = {
296 .mode = STEDMA40_MODE_LOGICAL,
297 .dir = STEDMA40_PERIPH_TO_MEM,
298 .src_dev_type = DB8500_DMA_DEV13_UART0_RX,
299 .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
300 .src_info.data_width = STEDMA40_BYTE_WIDTH,
301 .dst_info.data_width = STEDMA40_BYTE_WIDTH,
302};
303
304static struct stedma40_chan_cfg uart0_dma_cfg_tx = {
305 .mode = STEDMA40_MODE_LOGICAL,
306 .dir = STEDMA40_MEM_TO_PERIPH,
307 .src_dev_type = STEDMA40_DEV_SRC_MEMORY,
308 .dst_dev_type = DB8500_DMA_DEV13_UART0_TX,
309 .src_info.data_width = STEDMA40_BYTE_WIDTH,
310 .dst_info.data_width = STEDMA40_BYTE_WIDTH,
311};
312
313static struct stedma40_chan_cfg uart1_dma_cfg_rx = {
314 .mode = STEDMA40_MODE_LOGICAL,
315 .dir = STEDMA40_PERIPH_TO_MEM,
316 .src_dev_type = DB8500_DMA_DEV12_UART1_RX,
317 .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
318 .src_info.data_width = STEDMA40_BYTE_WIDTH,
319 .dst_info.data_width = STEDMA40_BYTE_WIDTH,
320};
321
322static struct stedma40_chan_cfg uart1_dma_cfg_tx = {
323 .mode = STEDMA40_MODE_LOGICAL,
324 .dir = STEDMA40_MEM_TO_PERIPH,
325 .src_dev_type = STEDMA40_DEV_SRC_MEMORY,
326 .dst_dev_type = DB8500_DMA_DEV12_UART1_TX,
327 .src_info.data_width = STEDMA40_BYTE_WIDTH,
328 .dst_info.data_width = STEDMA40_BYTE_WIDTH,
329};
330
331static struct stedma40_chan_cfg uart2_dma_cfg_rx = {
332 .mode = STEDMA40_MODE_LOGICAL,
333 .dir = STEDMA40_PERIPH_TO_MEM,
334 .src_dev_type = DB8500_DMA_DEV11_UART2_RX,
335 .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
336 .src_info.data_width = STEDMA40_BYTE_WIDTH,
337 .dst_info.data_width = STEDMA40_BYTE_WIDTH,
338};
339
340static struct stedma40_chan_cfg uart2_dma_cfg_tx = {
341 .mode = STEDMA40_MODE_LOGICAL,
342 .dir = STEDMA40_MEM_TO_PERIPH,
343 .src_dev_type = STEDMA40_DEV_SRC_MEMORY,
344 .dst_dev_type = DB8500_DMA_DEV11_UART2_TX,
345 .src_info.data_width = STEDMA40_BYTE_WIDTH,
346 .dst_info.data_width = STEDMA40_BYTE_WIDTH,
347};
348#endif
349
350static struct amba_pl011_data uart0_plat = {
351#ifdef CONFIG_STE_DMA40
352 .dma_filter = stedma40_filter,
353 .dma_rx_param = &uart0_dma_cfg_rx,
354 .dma_tx_param = &uart0_dma_cfg_tx,
355#endif
356};
357
358static struct amba_pl011_data uart1_plat = {
359#ifdef CONFIG_STE_DMA40
360 .dma_filter = stedma40_filter,
361 .dma_rx_param = &uart1_dma_cfg_rx,
362 .dma_tx_param = &uart1_dma_cfg_tx,
363#endif
364};
365
366static struct amba_pl011_data uart2_plat = {
367#ifdef CONFIG_STE_DMA40
368 .dma_filter = stedma40_filter,
369 .dma_rx_param = &uart2_dma_cfg_rx,
370 .dma_tx_param = &uart2_dma_cfg_tx,
371#endif
372};
373
190static void __init mop500_uart_init(void) 374static void __init mop500_uart_init(void)
191{ 375{
192 db8500_add_uart0(); 376 db8500_add_uart0(&uart0_plat);
193 db8500_add_uart1(); 377 db8500_add_uart1(&uart1_plat);
194 db8500_add_uart2(); 378 db8500_add_uart2(&uart2_plat);
195} 379}
196 380
197static void __init u8500_init_machine(void) 381static void __init mop500_init_machine(void)
198{ 382{
383 /*
384 * The HREFv60 board removed a GPIO expander and routed
385 * all these GPIO pins to the internal GPIO controller
386 * instead.
387 */
388 if (machine_is_hrefv60())
389 mop500_gpio_keys[0].gpio = HREFV60_PROX_SENSE_GPIO;
390 else
391 mop500_gpio_keys[0].gpio = GPIO_PROX_SENSOR;
392
199 u8500_init_devices(); 393 u8500_init_devices();
200 394
201 nmk_config_pins(mop500_pins, ARRAY_SIZE(mop500_pins)); 395 mop500_pins_init();
202 396
203 platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs)); 397 platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
204 398
@@ -207,12 +401,12 @@ static void __init u8500_init_machine(void)
207 mop500_spi_init(); 401 mop500_spi_init();
208 mop500_uart_init(); 402 mop500_uart_init();
209 403
210 mop500_keypad_init();
211
212 platform_device_register(&ab8500_device); 404 platform_device_register(&ab8500_device);
213 405
214 i2c_register_board_info(0, mop500_i2c0_devices, 406 i2c_register_board_info(0, mop500_i2c0_devices,
215 ARRAY_SIZE(mop500_i2c0_devices)); 407 ARRAY_SIZE(mop500_i2c0_devices));
408 i2c_register_board_info(2, mop500_i2c2_devices,
409 ARRAY_SIZE(mop500_i2c2_devices));
216} 410}
217 411
218MACHINE_START(U8500, "ST-Ericsson MOP500 platform") 412MACHINE_START(U8500, "ST-Ericsson MOP500 platform")
@@ -222,5 +416,13 @@ MACHINE_START(U8500, "ST-Ericsson MOP500 platform")
222 .init_irq = ux500_init_irq, 416 .init_irq = ux500_init_irq,
223 /* we re-use nomadik timer here */ 417 /* we re-use nomadik timer here */
224 .timer = &ux500_timer, 418 .timer = &ux500_timer,
225 .init_machine = u8500_init_machine, 419 .init_machine = mop500_init_machine,
420MACHINE_END
421
422MACHINE_START(HREFV60, "ST-Ericsson U8500 Platform HREFv60+")
423 .boot_params = 0x100,
424 .map_io = u8500_map_io,
425 .init_irq = ux500_init_irq,
426 .timer = &ux500_timer,
427 .init_machine = mop500_init_machine,
226MACHINE_END 428MACHINE_END
diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h
index 3104ae2a02c2..56722f4be71b 100644
--- a/arch/arm/mach-ux500/board-mop500.h
+++ b/arch/arm/mach-ux500/board-mop500.h
@@ -7,15 +7,36 @@
7#ifndef __BOARD_MOP500_H 7#ifndef __BOARD_MOP500_H
8#define __BOARD_MOP500_H 8#define __BOARD_MOP500_H
9 9
10#define MOP500_EGPIO(x) (NOMADIK_NR_GPIO + (x)) 10/* HREFv60-specific GPIO assignments, this board has no GPIO expander */
11#define HREFV60_TOUCH_RST_GPIO 143
12#define HREFV60_PROX_SENSE_GPIO 217
13#define HREFV60_HAL_SW_GPIO 145
14#define HREFV60_SDMMC_EN_GPIO 169
15#define HREFV60_SDMMC_1V8_3V_GPIO 5
16#define HREFV60_SDMMC_CD_GPIO 95
17#define HREFV60_ACCEL_INT1_GPIO 82
18#define HREFV60_ACCEL_INT2_GPIO 83
19#define HREFV60_MAGNET_DRDY_GPIO 32
20#define HREFV60_DISP1_RST_GPIO 65
21#define HREFV60_DISP2_RST_GPIO 66
11 22
12/* GPIOs on the TC35892 expander */ 23/* GPIOs on the TC35892 expander */
24#define MOP500_EGPIO(x) (NOMADIK_NR_GPIO + (x))
13#define GPIO_SDMMC_CD MOP500_EGPIO(3) 25#define GPIO_SDMMC_CD MOP500_EGPIO(3)
26#define GPIO_PROX_SENSOR MOP500_EGPIO(7)
27#define GPIO_BU21013_CS MOP500_EGPIO(13)
14#define GPIO_SDMMC_EN MOP500_EGPIO(17) 28#define GPIO_SDMMC_EN MOP500_EGPIO(17)
15#define GPIO_SDMMC_1V8_3V_SEL MOP500_EGPIO(18) 29#define GPIO_SDMMC_1V8_3V_SEL MOP500_EGPIO(18)
16 30
31struct i2c_board_info;
32
17extern void mop500_sdi_init(void); 33extern void mop500_sdi_init(void);
18extern void mop500_sdi_tc35892_init(void); 34extern void mop500_sdi_tc35892_init(void);
19extern void mop500_keypad_init(void); 35void __init mop500_u8500uib_init(void);
36void __init mop500_stuib_init(void);
37void __init mop500_pins_init(void);
38
39void mop500_uib_i2c_add(int busnum, struct i2c_board_info *info,
40 unsigned n);
20 41
21#endif 42#endif
diff --git a/arch/arm/mach-ux500/board-u5500-sdi.c b/arch/arm/mach-ux500/board-u5500-sdi.c
index 54712acc0394..739fb4c5b160 100644
--- a/arch/arm/mach-ux500/board-u5500-sdi.c
+++ b/arch/arm/mach-ux500/board-u5500-sdi.c
@@ -31,6 +31,26 @@ static pin_cfg_t u5500_sdi_pins[] = {
31 GPIO14_MC0_CLK | PIN_DIR_OUTPUT | PIN_VAL_LOW, 31 GPIO14_MC0_CLK | PIN_DIR_OUTPUT | PIN_VAL_LOW,
32}; 32};
33 33
34#ifdef CONFIG_STE_DMA40
35struct stedma40_chan_cfg u5500_sdi0_dma_cfg_rx = {
36 .mode = STEDMA40_MODE_LOGICAL,
37 .dir = STEDMA40_PERIPH_TO_MEM,
38 .src_dev_type = DB5500_DMA_DEV24_SDMMC0_RX,
39 .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
40 .src_info.data_width = STEDMA40_WORD_WIDTH,
41 .dst_info.data_width = STEDMA40_WORD_WIDTH,
42};
43
44static struct stedma40_chan_cfg u5500_sdi0_dma_cfg_tx = {
45 .mode = STEDMA40_MODE_LOGICAL,
46 .dir = STEDMA40_MEM_TO_PERIPH,
47 .src_dev_type = STEDMA40_DEV_SRC_MEMORY,
48 .dst_dev_type = DB5500_DMA_DEV24_SDMMC0_TX,
49 .src_info.data_width = STEDMA40_WORD_WIDTH,
50 .dst_info.data_width = STEDMA40_WORD_WIDTH,
51};
52#endif
53
34static struct mmci_platform_data u5500_sdi0_data = { 54static struct mmci_platform_data u5500_sdi0_data = {
35 .ocr_mask = MMC_VDD_165_195, 55 .ocr_mask = MMC_VDD_165_195,
36 .f_max = 50000000, 56 .f_max = 50000000,
@@ -39,6 +59,11 @@ static struct mmci_platform_data u5500_sdi0_data = {
39 MMC_CAP_MMC_HIGHSPEED, 59 MMC_CAP_MMC_HIGHSPEED,
40 .gpio_cd = -1, 60 .gpio_cd = -1,
41 .gpio_wp = -1, 61 .gpio_wp = -1,
62#ifdef CONFIG_STE_DMA40
63 .dma_filter = stedma40_filter,
64 .dma_rx_param = &u5500_sdi0_dma_cfg_rx,
65 .dma_tx_param = &u5500_sdi0_dma_cfg_tx,
66#endif
42}; 67};
43 68
44void __init u5500_sdi_init(void) 69void __init u5500_sdi_init(void)
diff --git a/arch/arm/mach-ux500/board-u5500.c b/arch/arm/mach-ux500/board-u5500.c
index 39d370c1f3b4..44fd3b5c33ec 100644
--- a/arch/arm/mach-ux500/board-u5500.c
+++ b/arch/arm/mach-ux500/board-u5500.c
@@ -22,9 +22,9 @@
22 22
23static void __init u5500_uart_init(void) 23static void __init u5500_uart_init(void)
24{ 24{
25 db5500_add_uart0(); 25 db5500_add_uart0(NULL);
26 db5500_add_uart1(); 26 db5500_add_uart1(NULL);
27 db5500_add_uart2(); 27 db5500_add_uart2(NULL);
28} 28}
29 29
30static void __init u5500_init_machine(void) 30static void __init u5500_init_machine(void)
diff --git a/arch/arm/mach-ux500/clock.c b/arch/arm/mach-ux500/clock.c
index b2b0a3b9be8f..32ce90840ee1 100644
--- a/arch/arm/mach-ux500/clock.c
+++ b/arch/arm/mach-ux500/clock.c
@@ -313,7 +313,7 @@ static DEFINE_PRCMU_CLK_RATE(uartclk, 0x0, 5, UARTCLK, 38400000);
313static DEFINE_PRCMU_CLK(msp02clk, 0x0, 6, MSP02CLK); 313static DEFINE_PRCMU_CLK(msp02clk, 0x0, 6, MSP02CLK);
314static DEFINE_PRCMU_CLK(msp1clk, 0x0, 7, MSP1CLK); /* v1 */ 314static DEFINE_PRCMU_CLK(msp1clk, 0x0, 7, MSP1CLK); /* v1 */
315static DEFINE_PRCMU_CLK_RATE(i2cclk, 0x0, 8, I2CCLK, 48000000); 315static DEFINE_PRCMU_CLK_RATE(i2cclk, 0x0, 8, I2CCLK, 48000000);
316static DEFINE_PRCMU_CLK_RATE(sdmmcclk, 0x0, 9, SDMMCCLK, 50000000); 316static DEFINE_PRCMU_CLK_RATE(sdmmcclk, 0x0, 9, SDMMCCLK, 100000000);
317static DEFINE_PRCMU_CLK(slimclk, 0x0, 10, SLIMCLK); 317static DEFINE_PRCMU_CLK(slimclk, 0x0, 10, SLIMCLK);
318static DEFINE_PRCMU_CLK(per1clk, 0x0, 11, PER1CLK); 318static DEFINE_PRCMU_CLK(per1clk, 0x0, 11, PER1CLK);
319static DEFINE_PRCMU_CLK(per2clk, 0x0, 12, PER2CLK); 319static DEFINE_PRCMU_CLK(per2clk, 0x0, 12, PER2CLK);
@@ -520,7 +520,7 @@ static struct clk_lookup u8500_ed_clks[] = {
520 CLK(ssp0_ed, "ssp0", NULL), 520 CLK(ssp0_ed, "ssp0", NULL),
521 521
522 /* Peripheral Cluster #5 */ 522 /* Peripheral Cluster #5 */
523 CLK(usb_ed, "musb_hdrc.0", "usb"), 523 CLK(usb_ed, "musb-ux500.0", "usb"),
524 524
525 /* Peripheral Cluster #6 */ 525 /* Peripheral Cluster #6 */
526 CLK(dmc_ed, "dmc", NULL), 526 CLK(dmc_ed, "dmc", NULL),
@@ -561,7 +561,7 @@ static struct clk_lookup u8500_v1_clks[] = {
561 CLK(ssp0_v1, "ssp0", NULL), 561 CLK(ssp0_v1, "ssp0", NULL),
562 562
563 /* Peripheral Cluster #5 */ 563 /* Peripheral Cluster #5 */
564 CLK(usb_v1, "musb_hdrc.0", "usb"), 564 CLK(usb_v1, "musb-ux500.0", "usb"),
565 565
566 /* Peripheral Cluster #6 */ 566 /* Peripheral Cluster #6 */
567 CLK(mtu1_v1, "mtu1", NULL), 567 CLK(mtu1_v1, "mtu1", NULL),
diff --git a/arch/arm/mach-ux500/cpu-db5500.c b/arch/arm/mach-ux500/cpu-db5500.c
index af04e0891a78..c9dc2eff3cb2 100644
--- a/arch/arm/mach-ux500/cpu-db5500.c
+++ b/arch/arm/mach-ux500/cpu-db5500.c
@@ -11,6 +11,7 @@
11#include <linux/irq.h> 11#include <linux/irq.h>
12 12
13#include <asm/mach/map.h> 13#include <asm/mach/map.h>
14#include <asm/pmu.h>
14 15
15#include <plat/gpio.h> 16#include <plat/gpio.h>
16 17
@@ -18,8 +19,10 @@
18#include <mach/devices.h> 19#include <mach/devices.h>
19#include <mach/setup.h> 20#include <mach/setup.h>
20#include <mach/irqs.h> 21#include <mach/irqs.h>
22#include <mach/usb.h>
21 23
22#include "devices-db5500.h" 24#include "devices-db5500.h"
25#include "ste-dma40-db5500.h"
23 26
24static struct map_desc u5500_uart_io_desc[] __initdata = { 27static struct map_desc u5500_uart_io_desc[] __initdata = {
25 __IO_DEV_DESC(U5500_UART0_BASE, SZ_4K), 28 __IO_DEV_DESC(U5500_UART0_BASE, SZ_4K),
@@ -43,6 +46,26 @@ static struct map_desc u5500_io_desc[] __initdata = {
43 __IO_DEV_DESC(U5500_PRCMU_BASE, SZ_4K), 46 __IO_DEV_DESC(U5500_PRCMU_BASE, SZ_4K),
44}; 47};
45 48
49static struct resource db5500_pmu_resources[] = {
50 [0] = {
51 .start = IRQ_DB5500_PMU0,
52 .end = IRQ_DB5500_PMU0,
53 .flags = IORESOURCE_IRQ,
54 },
55 [1] = {
56 .start = IRQ_DB5500_PMU1,
57 .end = IRQ_DB5500_PMU1,
58 .flags = IORESOURCE_IRQ,
59 },
60};
61
62static struct platform_device db5500_pmu_device = {
63 .name = "arm-pmu",
64 .id = ARM_PMU_DEVICE_CPU,
65 .num_resources = ARRAY_SIZE(db5500_pmu_resources),
66 .resource = db5500_pmu_resources,
67};
68
46static struct resource mbox0_resources[] = { 69static struct resource mbox0_resources[] = {
47 { 70 {
48 .name = "mbox_peer", 71 .name = "mbox_peer",
@@ -127,7 +150,8 @@ static struct platform_device mbox2_device = {
127 .num_resources = ARRAY_SIZE(mbox2_resources), 150 .num_resources = ARRAY_SIZE(mbox2_resources),
128}; 151};
129 152
130static struct platform_device *u5500_platform_devs[] __initdata = { 153static struct platform_device *db5500_platform_devs[] __initdata = {
154 &db5500_pmu_device,
131 &mbox0_device, 155 &mbox0_device,
132 &mbox1_device, 156 &mbox1_device,
133 &mbox2_device, 157 &mbox2_device,
@@ -166,12 +190,35 @@ void __init u5500_map_io(void)
166 iotable_init(u5500_io_desc, ARRAY_SIZE(u5500_io_desc)); 190 iotable_init(u5500_io_desc, ARRAY_SIZE(u5500_io_desc));
167} 191}
168 192
193static int usb_db5500_rx_dma_cfg[] = {
194 DB5500_DMA_DEV4_USB_OTG_IEP_1_9,
195 DB5500_DMA_DEV5_USB_OTG_IEP_2_10,
196 DB5500_DMA_DEV6_USB_OTG_IEP_3_11,
197 DB5500_DMA_DEV20_USB_OTG_IEP_4_12,
198 DB5500_DMA_DEV21_USB_OTG_IEP_5_13,
199 DB5500_DMA_DEV22_USB_OTG_IEP_6_14,
200 DB5500_DMA_DEV23_USB_OTG_IEP_7_15,
201 DB5500_DMA_DEV38_USB_OTG_IEP_8
202};
203
204static int usb_db5500_tx_dma_cfg[] = {
205 DB5500_DMA_DEV4_USB_OTG_OEP_1_9,
206 DB5500_DMA_DEV5_USB_OTG_OEP_2_10,
207 DB5500_DMA_DEV6_USB_OTG_OEP_3_11,
208 DB5500_DMA_DEV20_USB_OTG_OEP_4_12,
209 DB5500_DMA_DEV21_USB_OTG_OEP_5_13,
210 DB5500_DMA_DEV22_USB_OTG_OEP_6_14,
211 DB5500_DMA_DEV23_USB_OTG_OEP_7_15,
212 DB5500_DMA_DEV38_USB_OTG_OEP_8
213};
214
169void __init u5500_init_devices(void) 215void __init u5500_init_devices(void)
170{ 216{
171 db5500_add_gpios(); 217 db5500_add_gpios();
172 db5500_dma_init(); 218 db5500_dma_init();
173 db5500_add_rtc(); 219 db5500_add_rtc();
220 db5500_add_usb(usb_db5500_rx_dma_cfg, usb_db5500_tx_dma_cfg);
174 221
175 platform_add_devices(u5500_platform_devs, 222 platform_add_devices(db5500_platform_devs,
176 ARRAY_SIZE(u5500_platform_devs)); 223 ARRAY_SIZE(db5500_platform_devs));
177} 224}
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 1748fbc58530..516126cb357d 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -12,21 +12,21 @@
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/device.h> 13#include <linux/device.h>
14#include <linux/amba/bus.h> 14#include <linux/amba/bus.h>
15#include <linux/interrupt.h>
15#include <linux/irq.h> 16#include <linux/irq.h>
16#include <linux/gpio.h> 17#include <linux/gpio.h>
17#include <linux/platform_device.h> 18#include <linux/platform_device.h>
18#include <linux/io.h> 19#include <linux/io.h>
19 20
20#include <asm/mach/map.h> 21#include <asm/mach/map.h>
22#include <asm/pmu.h>
21#include <mach/hardware.h> 23#include <mach/hardware.h>
22#include <mach/setup.h> 24#include <mach/setup.h>
23#include <mach/devices.h> 25#include <mach/devices.h>
26#include <mach/usb.h>
24 27
25#include "devices-db8500.h" 28#include "devices-db8500.h"
26 29#include "ste-dma40-db8500.h"
27static struct platform_device *platform_devs[] __initdata = {
28 &u8500_dma40_device,
29};
30 30
31/* minimum static i/o mapping required to boot U8500 platforms */ 31/* minimum static i/o mapping required to boot U8500 platforms */
32static struct map_desc u8500_uart_io_desc[] __initdata = { 32static struct map_desc u8500_uart_io_desc[] __initdata = {
@@ -89,6 +89,51 @@ void __init u8500_map_io(void)
89 iotable_init(u8500_v2_io_desc, ARRAY_SIZE(u8500_v2_io_desc)); 89 iotable_init(u8500_v2_io_desc, ARRAY_SIZE(u8500_v2_io_desc));
90} 90}
91 91
92static struct resource db8500_pmu_resources[] = {
93 [0] = {
94 .start = IRQ_DB8500_PMU,
95 .end = IRQ_DB8500_PMU,
96 .flags = IORESOURCE_IRQ,
97 },
98};
99
100/*
101 * The PMU IRQ lines of two cores are wired together into a single interrupt.
102 * Bounce the interrupt to the other core if it's not ours.
103 */
104static irqreturn_t db8500_pmu_handler(int irq, void *dev, irq_handler_t handler)
105{
106 irqreturn_t ret = handler(irq, dev);
107 int other = !smp_processor_id();
108
109 if (ret == IRQ_NONE && cpu_online(other))
110 irq_set_affinity(irq, cpumask_of(other));
111
112 /*
113 * We should be able to get away with the amount of IRQ_NONEs we give,
114 * while still having the spurious IRQ detection code kick in if the
115 * interrupt really starts hitting spuriously.
116 */
117 return ret;
118}
119
120static struct arm_pmu_platdata db8500_pmu_platdata = {
121 .handle_irq = db8500_pmu_handler,
122};
123
124static struct platform_device db8500_pmu_device = {
125 .name = "arm-pmu",
126 .id = ARM_PMU_DEVICE_CPU,
127 .num_resources = ARRAY_SIZE(db8500_pmu_resources),
128 .resource = db8500_pmu_resources,
129 .dev.platform_data = &db8500_pmu_platdata,
130};
131
132static struct platform_device *platform_devs[] __initdata = {
133 &u8500_dma40_device,
134 &db8500_pmu_device,
135};
136
92static resource_size_t __initdata db8500_gpio_base[] = { 137static resource_size_t __initdata db8500_gpio_base[] = {
93 U8500_GPIOBANK0_BASE, 138 U8500_GPIOBANK0_BASE,
94 U8500_GPIOBANK1_BASE, 139 U8500_GPIOBANK1_BASE,
@@ -111,6 +156,28 @@ static void __init db8500_add_gpios(void)
111 IRQ_DB8500_GPIO0, &pdata); 156 IRQ_DB8500_GPIO0, &pdata);
112} 157}
113 158
159static int usb_db8500_rx_dma_cfg[] = {
160 DB8500_DMA_DEV38_USB_OTG_IEP_1_9,
161 DB8500_DMA_DEV37_USB_OTG_IEP_2_10,
162 DB8500_DMA_DEV36_USB_OTG_IEP_3_11,
163 DB8500_DMA_DEV19_USB_OTG_IEP_4_12,
164 DB8500_DMA_DEV18_USB_OTG_IEP_5_13,
165 DB8500_DMA_DEV17_USB_OTG_IEP_6_14,
166 DB8500_DMA_DEV16_USB_OTG_IEP_7_15,
167 DB8500_DMA_DEV39_USB_OTG_IEP_8
168};
169
170static int usb_db8500_tx_dma_cfg[] = {
171 DB8500_DMA_DEV38_USB_OTG_OEP_1_9,
172 DB8500_DMA_DEV37_USB_OTG_OEP_2_10,
173 DB8500_DMA_DEV36_USB_OTG_OEP_3_11,
174 DB8500_DMA_DEV19_USB_OTG_OEP_4_12,
175 DB8500_DMA_DEV18_USB_OTG_OEP_5_13,
176 DB8500_DMA_DEV17_USB_OTG_OEP_6_14,
177 DB8500_DMA_DEV16_USB_OTG_OEP_7_15,
178 DB8500_DMA_DEV39_USB_OTG_OEP_8
179};
180
114/* 181/*
115 * This function is called from the board init 182 * This function is called from the board init
116 */ 183 */
@@ -121,6 +188,7 @@ void __init u8500_init_devices(void)
121 188
122 db8500_add_rtc(); 189 db8500_add_rtc();
123 db8500_add_gpios(); 190 db8500_add_gpios();
191 db8500_add_usb(usb_db8500_rx_dma_cfg, usb_db8500_tx_dma_cfg);
124 192
125 platform_device_register_simple("cpufreq-u8500", -1, NULL, 0); 193 platform_device_register_simple("cpufreq-u8500", -1, NULL, 0);
126 platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs)); 194 platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
diff --git a/arch/arm/mach-ux500/devices-common.c b/arch/arm/mach-ux500/devices-common.c
index fe69f5fac1bb..13a4ce046ae5 100644
--- a/arch/arm/mach-ux500/devices-common.c
+++ b/arch/arm/mach-ux500/devices-common.c
@@ -139,6 +139,7 @@ void dbx500_add_gpios(resource_size_t *base, int num, int irq,
139 for (i = 0; i < num; i++, first += 32, irq++) { 139 for (i = 0; i < num; i++, first += 32, irq++) {
140 pdata->first_gpio = first; 140 pdata->first_gpio = first;
141 pdata->first_irq = NOMADIK_GPIO_TO_IRQ(first); 141 pdata->first_irq = NOMADIK_GPIO_TO_IRQ(first);
142 pdata->num_gpio = 32;
142 143
143 dbx500_add_gpio(i, base[i], irq, pdata); 144 dbx500_add_gpio(i, base[i], irq, pdata);
144 } 145 }
diff --git a/arch/arm/mach-ux500/devices-common.h b/arch/arm/mach-ux500/devices-common.h
index cbadc117d2db..c719b5a1d913 100644
--- a/arch/arm/mach-ux500/devices-common.h
+++ b/arch/arm/mach-ux500/devices-common.h
@@ -42,10 +42,13 @@ dbx500_add_sdi(const char *name, resource_size_t base, int irq,
42 return dbx500_add_amba_device(name, base, irq, pdata, 0); 42 return dbx500_add_amba_device(name, base, irq, pdata, 0);
43} 43}
44 44
45struct amba_pl011_data;
46
45static inline struct amba_device * 47static inline struct amba_device *
46dbx500_add_uart(const char *name, resource_size_t base, int irq) 48dbx500_add_uart(const char *name, resource_size_t base, int irq,
49 struct amba_pl011_data *pdata)
47{ 50{
48 return dbx500_add_amba_device(name, base, irq, NULL, 0); 51 return dbx500_add_amba_device(name, base, irq, pdata, 0);
49} 52}
50 53
51struct nmk_i2c_controller; 54struct nmk_i2c_controller;
diff --git a/arch/arm/mach-ux500/devices-db5500.h b/arch/arm/mach-ux500/devices-db5500.h
index c8d7901c1f2d..94627f7783b0 100644
--- a/arch/arm/mach-ux500/devices-db5500.h
+++ b/arch/arm/mach-ux500/devices-db5500.h
@@ -34,6 +34,9 @@
34#define db5500_add_rtc() \ 34#define db5500_add_rtc() \
35 dbx500_add_rtc(U5500_RTC_BASE, IRQ_DB5500_RTC); 35 dbx500_add_rtc(U5500_RTC_BASE, IRQ_DB5500_RTC);
36 36
37#define db5500_add_usb(rx_cfg, tx_cfg) \
38 ux500_add_usb(U5500_USBOTG_BASE, IRQ_DB5500_USBOTG, rx_cfg, tx_cfg)
39
37#define db5500_add_sdi0(pdata) \ 40#define db5500_add_sdi0(pdata) \
38 dbx500_add_sdi("sdi0", U5500_SDI0_BASE, IRQ_DB5500_SDMMC0, pdata) 41 dbx500_add_sdi("sdi0", U5500_SDI0_BASE, IRQ_DB5500_SDMMC0, pdata)
39#define db5500_add_sdi1(pdata) \ 42#define db5500_add_sdi1(pdata) \
@@ -54,13 +57,13 @@
54#define db5500_add_spi3(pdata) \ 57#define db5500_add_spi3(pdata) \
55 dbx500_add_spi("spi3", U5500_SPI3_BASE, IRQ_DB5500_SPI3, pdata) 58 dbx500_add_spi("spi3", U5500_SPI3_BASE, IRQ_DB5500_SPI3, pdata)
56 59
57#define db5500_add_uart0() \ 60#define db5500_add_uart0(plat) \
58 dbx500_add_uart("uart0", U5500_UART0_BASE, IRQ_DB5500_UART0) 61 dbx500_add_uart("uart0", U5500_UART0_BASE, IRQ_DB5500_UART0, plat)
59#define db5500_add_uart1() \ 62#define db5500_add_uart1(plat) \
60 dbx500_add_uart("uart1", U5500_UART1_BASE, IRQ_DB5500_UART1) 63 dbx500_add_uart("uart1", U5500_UART1_BASE, IRQ_DB5500_UART1, plat)
61#define db5500_add_uart2() \ 64#define db5500_add_uart2(plat) \
62 dbx500_add_uart("uart2", U5500_UART2_BASE, IRQ_DB5500_UART2) 65 dbx500_add_uart("uart2", U5500_UART2_BASE, IRQ_DB5500_UART2, plat)
63#define db5500_add_uart3() \ 66#define db5500_add_uart3(plat) \
64 dbx500_add_uart("uart3", U5500_UART3_BASE, IRQ_DB5500_UART3) 67 dbx500_add_uart("uart3", U5500_UART3_BASE, IRQ_DB5500_UART3, plat)
65 68
66#endif 69#endif
diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c
index 23c695d54977..73b17404b194 100644
--- a/arch/arm/mach-ux500/devices-db8500.c
+++ b/arch/arm/mach-ux500/devices-db8500.c
@@ -11,6 +11,7 @@
11#include <linux/io.h> 11#include <linux/io.h>
12#include <linux/gpio.h> 12#include <linux/gpio.h>
13#include <linux/amba/bus.h> 13#include <linux/amba/bus.h>
14#include <linux/amba/pl022.h>
14 15
15#include <plat/ste_dma40.h> 16#include <plat/ste_dma40.h>
16 17
@@ -67,12 +68,72 @@ struct stedma40_chan_cfg dma40_memcpy_conf_log = {
67 68
68/* 69/*
69 * Mapping between destination event lines and physical device address. 70 * Mapping between destination event lines and physical device address.
70 * The event line is tied to a device and therefor the address is constant. 71 * The event line is tied to a device and therefore the address is constant.
72 * When the address comes from a primecell it will be configured in runtime
73 * and we set the address to -1 as a placeholder.
71 */ 74 */
72static const dma_addr_t dma40_tx_map[DB8500_DMA_NR_DEV]; 75static const dma_addr_t dma40_tx_map[DB8500_DMA_NR_DEV] = {
76 /* MUSB - these will be runtime-reconfigured */
77 [DB8500_DMA_DEV39_USB_OTG_OEP_8] = -1,
78 [DB8500_DMA_DEV16_USB_OTG_OEP_7_15] = -1,
79 [DB8500_DMA_DEV17_USB_OTG_OEP_6_14] = -1,
80 [DB8500_DMA_DEV18_USB_OTG_OEP_5_13] = -1,
81 [DB8500_DMA_DEV19_USB_OTG_OEP_4_12] = -1,
82 [DB8500_DMA_DEV36_USB_OTG_OEP_3_11] = -1,
83 [DB8500_DMA_DEV37_USB_OTG_OEP_2_10] = -1,
84 [DB8500_DMA_DEV38_USB_OTG_OEP_1_9] = -1,
85 /* PrimeCells - run-time configured */
86 [DB8500_DMA_DEV0_SPI0_TX] = -1,
87 [DB8500_DMA_DEV1_SD_MMC0_TX] = -1,
88 [DB8500_DMA_DEV2_SD_MMC1_TX] = -1,
89 [DB8500_DMA_DEV3_SD_MMC2_TX] = -1,
90 [DB8500_DMA_DEV8_SSP0_TX] = -1,
91 [DB8500_DMA_DEV9_SSP1_TX] = -1,
92 [DB8500_DMA_DEV11_UART2_TX] = -1,
93 [DB8500_DMA_DEV12_UART1_TX] = -1,
94 [DB8500_DMA_DEV13_UART0_TX] = -1,
95 [DB8500_DMA_DEV28_SD_MM2_TX] = -1,
96 [DB8500_DMA_DEV29_SD_MM0_TX] = -1,
97 [DB8500_DMA_DEV32_SD_MM1_TX] = -1,
98 [DB8500_DMA_DEV33_SPI2_TX] = -1,
99 [DB8500_DMA_DEV35_SPI1_TX] = -1,
100 [DB8500_DMA_DEV40_SPI3_TX] = -1,
101 [DB8500_DMA_DEV41_SD_MM3_TX] = -1,
102 [DB8500_DMA_DEV42_SD_MM4_TX] = -1,
103 [DB8500_DMA_DEV43_SD_MM5_TX] = -1,
104};
73 105
74/* Mapping between source event lines and physical device address */ 106/* Mapping between source event lines and physical device address */
75static const dma_addr_t dma40_rx_map[DB8500_DMA_NR_DEV]; 107static const dma_addr_t dma40_rx_map[DB8500_DMA_NR_DEV] = {
108 /* MUSB - these will be runtime-reconfigured */
109 [DB8500_DMA_DEV39_USB_OTG_IEP_8] = -1,
110 [DB8500_DMA_DEV16_USB_OTG_IEP_7_15] = -1,
111 [DB8500_DMA_DEV17_USB_OTG_IEP_6_14] = -1,
112 [DB8500_DMA_DEV18_USB_OTG_IEP_5_13] = -1,
113 [DB8500_DMA_DEV19_USB_OTG_IEP_4_12] = -1,
114 [DB8500_DMA_DEV36_USB_OTG_IEP_3_11] = -1,
115 [DB8500_DMA_DEV37_USB_OTG_IEP_2_10] = -1,
116 [DB8500_DMA_DEV38_USB_OTG_IEP_1_9] = -1,
117 /* PrimeCells */
118 [DB8500_DMA_DEV0_SPI0_RX] = -1,
119 [DB8500_DMA_DEV1_SD_MMC0_RX] = -1,
120 [DB8500_DMA_DEV2_SD_MMC1_RX] = -1,
121 [DB8500_DMA_DEV3_SD_MMC2_RX] = -1,
122 [DB8500_DMA_DEV8_SSP0_RX] = -1,
123 [DB8500_DMA_DEV9_SSP1_RX] = -1,
124 [DB8500_DMA_DEV11_UART2_RX] = -1,
125 [DB8500_DMA_DEV12_UART1_RX] = -1,
126 [DB8500_DMA_DEV13_UART0_RX] = -1,
127 [DB8500_DMA_DEV28_SD_MM2_RX] = -1,
128 [DB8500_DMA_DEV29_SD_MM0_RX] = -1,
129 [DB8500_DMA_DEV32_SD_MM1_RX] = -1,
130 [DB8500_DMA_DEV33_SPI2_RX] = -1,
131 [DB8500_DMA_DEV35_SPI1_RX] = -1,
132 [DB8500_DMA_DEV40_SPI3_RX] = -1,
133 [DB8500_DMA_DEV41_SD_MM3_RX] = -1,
134 [DB8500_DMA_DEV42_SD_MM4_RX] = -1,
135 [DB8500_DMA_DEV43_SD_MM5_RX] = -1,
136};
76 137
77/* Reserved event lines for memcpy only */ 138/* Reserved event lines for memcpy only */
78static int dma40_memcpy_event[] = { 139static int dma40_memcpy_event[] = {
diff --git a/arch/arm/mach-ux500/devices-db8500.h b/arch/arm/mach-ux500/devices-db8500.h
index 3a770c756979..9cc6f8f5d3e6 100644
--- a/arch/arm/mach-ux500/devices-db8500.h
+++ b/arch/arm/mach-ux500/devices-db8500.h
@@ -61,6 +61,9 @@ db8500_add_ssp(const char *name, resource_size_t base, int irq,
61#define db8500_add_rtc() \ 61#define db8500_add_rtc() \
62 dbx500_add_rtc(U8500_RTC_BASE, IRQ_DB8500_RTC); 62 dbx500_add_rtc(U8500_RTC_BASE, IRQ_DB8500_RTC);
63 63
64#define db8500_add_usb(rx_cfg, tx_cfg) \
65 ux500_add_usb(U8500_USBOTG_BASE, IRQ_DB8500_USBOTG, rx_cfg, tx_cfg)
66
64#define db8500_add_sdi0(pdata) \ 67#define db8500_add_sdi0(pdata) \
65 dbx500_add_sdi("sdi0", U8500_SDI0_BASE, IRQ_DB8500_SDMMC0, pdata) 68 dbx500_add_sdi("sdi0", U8500_SDI0_BASE, IRQ_DB8500_SDMMC0, pdata)
66#define db8500_add_sdi1(pdata) \ 69#define db8500_add_sdi1(pdata) \
@@ -88,11 +91,11 @@ db8500_add_ssp(const char *name, resource_size_t base, int irq,
88#define db8500_add_spi3(pdata) \ 91#define db8500_add_spi3(pdata) \
89 dbx500_add_spi("spi3", U8500_SPI3_BASE, IRQ_DB8500_SPI3, pdata) 92 dbx500_add_spi("spi3", U8500_SPI3_BASE, IRQ_DB8500_SPI3, pdata)
90 93
91#define db8500_add_uart0() \ 94#define db8500_add_uart0(pdata) \
92 dbx500_add_uart("uart0", U8500_UART0_BASE, IRQ_DB8500_UART0) 95 dbx500_add_uart("uart0", U8500_UART0_BASE, IRQ_DB8500_UART0, pdata)
93#define db8500_add_uart1() \ 96#define db8500_add_uart1(pdata) \
94 dbx500_add_uart("uart1", U8500_UART1_BASE, IRQ_DB8500_UART1) 97 dbx500_add_uart("uart1", U8500_UART1_BASE, IRQ_DB8500_UART1, pdata)
95#define db8500_add_uart2() \ 98#define db8500_add_uart2(pdata) \
96 dbx500_add_uart("uart2", U8500_UART2_BASE, IRQ_DB8500_UART2) 99 dbx500_add_uart("uart2", U8500_UART2_BASE, IRQ_DB8500_UART2, pdata)
97 100
98#endif 101#endif
diff --git a/arch/arm/mach-ux500/dma-db5500.c b/arch/arm/mach-ux500/dma-db5500.c
index 32a061f8a95b..1cfab68ae417 100644
--- a/arch/arm/mach-ux500/dma-db5500.c
+++ b/arch/arm/mach-ux500/dma-db5500.c
@@ -73,11 +73,27 @@ static struct stedma40_chan_cfg dma40_memcpy_conf_log = {
73 */ 73 */
74static const dma_addr_t dma40_rx_map[DB5500_DMA_NR_DEV] = { 74static const dma_addr_t dma40_rx_map[DB5500_DMA_NR_DEV] = {
75 [DB5500_DMA_DEV24_SDMMC0_RX] = -1, 75 [DB5500_DMA_DEV24_SDMMC0_RX] = -1,
76 [DB5500_DMA_DEV38_USB_OTG_IEP_8] = -1,
77 [DB5500_DMA_DEV23_USB_OTG_IEP_7_15] = -1,
78 [DB5500_DMA_DEV22_USB_OTG_IEP_6_14] = -1,
79 [DB5500_DMA_DEV21_USB_OTG_IEP_5_13] = -1,
80 [DB5500_DMA_DEV20_USB_OTG_IEP_4_12] = -1,
81 [DB5500_DMA_DEV6_USB_OTG_IEP_3_11] = -1,
82 [DB5500_DMA_DEV5_USB_OTG_IEP_2_10] = -1,
83 [DB5500_DMA_DEV4_USB_OTG_IEP_1_9] = -1,
76}; 84};
77 85
78/* Mapping between destination event lines and physical device address */ 86/* Mapping between destination event lines and physical device address */
79static const dma_addr_t dma40_tx_map[DB5500_DMA_NR_DEV] = { 87static const dma_addr_t dma40_tx_map[DB5500_DMA_NR_DEV] = {
80 [DB5500_DMA_DEV24_SDMMC0_TX] = -1, 88 [DB5500_DMA_DEV24_SDMMC0_TX] = -1,
89 [DB5500_DMA_DEV38_USB_OTG_OEP_8] = -1,
90 [DB5500_DMA_DEV23_USB_OTG_OEP_7_15] = -1,
91 [DB5500_DMA_DEV22_USB_OTG_OEP_6_14] = -1,
92 [DB5500_DMA_DEV21_USB_OTG_OEP_5_13] = -1,
93 [DB5500_DMA_DEV20_USB_OTG_OEP_4_12] = -1,
94 [DB5500_DMA_DEV6_USB_OTG_OEP_3_11] = -1,
95 [DB5500_DMA_DEV5_USB_OTG_OEP_2_10] = -1,
96 [DB5500_DMA_DEV4_USB_OTG_OEP_1_9] = -1,
81}; 97};
82 98
83static int dma40_memcpy_event[] = { 99static int dma40_memcpy_event[] = {
diff --git a/arch/arm/mach-ux500/include/mach/uncompress.h b/arch/arm/mach-ux500/include/mach/uncompress.h
index 9a6614c6808e..ab0fe1432fae 100644
--- a/arch/arm/mach-ux500/include/mach/uncompress.h
+++ b/arch/arm/mach-ux500/include/mach/uncompress.h
@@ -50,7 +50,11 @@ static void flush(void)
50 50
51static inline void arch_decomp_setup(void) 51static inline void arch_decomp_setup(void)
52{ 52{
53 if (machine_is_u8500()) 53 /* Check in run time if we run on an U8500 or U5500 */
54 if (machine_is_u8500() ||
55 machine_is_svp8500v1() ||
56 machine_is_svp8500v2() ||
57 machine_is_hrefv60())
54 ux500_uart_base = U8500_UART2_BASE; 58 ux500_uart_base = U8500_UART2_BASE;
55 else if (machine_is_u5500()) 59 else if (machine_is_u5500())
56 ux500_uart_base = U5500_UART0_BASE; 60 ux500_uart_base = U5500_UART0_BASE;
diff --git a/arch/arm/mach-ux500/include/mach/usb.h b/arch/arm/mach-ux500/include/mach/usb.h
new file mode 100644
index 000000000000..d3739d418813
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/usb.h
@@ -0,0 +1,25 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2011
3 *
4 * Author: Mian Yousaf Kaukab <mian.yousaf.kaukab@stericsson.com>
5 * License terms: GNU General Public License (GPL) version 2
6 */
7#ifndef __ASM_ARCH_USB_H
8#define __ASM_ARCH_USB_H
9
10#include <linux/dmaengine.h>
11
12#define UX500_MUSB_DMA_NUM_RX_CHANNELS 8
13#define UX500_MUSB_DMA_NUM_TX_CHANNELS 8
14
15struct ux500_musb_board_data {
16 void **dma_rx_param_array;
17 void **dma_tx_param_array;
18 u32 num_rx_channels;
19 u32 num_tx_channels;
20 bool (*dma_filter)(struct dma_chan *chan, void *filter_param);
21};
22
23void ux500_add_usb(resource_size_t base, int irq, int *dma_rx_cfg,
24 int *dma_tx_cfg);
25#endif
diff --git a/arch/arm/mach-ux500/usb.c b/arch/arm/mach-ux500/usb.c
new file mode 100644
index 000000000000..82e535953fd9
--- /dev/null
+++ b/arch/arm/mach-ux500/usb.c
@@ -0,0 +1,160 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2011
3 *
4 * Author: Mian Yousaf Kaukab <mian.yousaf.kaukab@stericsson.com>
5 * License terms: GNU General Public License (GPL) version 2
6 */
7#include <linux/platform_device.h>
8#include <linux/usb/musb.h>
9#include <plat/ste_dma40.h>
10#include <mach/hardware.h>
11#include <mach/usb.h>
12
13#define MUSB_DMA40_RX_CH { \
14 .mode = STEDMA40_MODE_LOGICAL, \
15 .dir = STEDMA40_PERIPH_TO_MEM, \
16 .dst_dev_type = STEDMA40_DEV_DST_MEMORY, \
17 .src_info.data_width = STEDMA40_WORD_WIDTH, \
18 .dst_info.data_width = STEDMA40_WORD_WIDTH, \
19 .src_info.psize = STEDMA40_PSIZE_LOG_16, \
20 .dst_info.psize = STEDMA40_PSIZE_LOG_16, \
21 }
22
23#define MUSB_DMA40_TX_CH { \
24 .mode = STEDMA40_MODE_LOGICAL, \
25 .dir = STEDMA40_MEM_TO_PERIPH, \
26 .src_dev_type = STEDMA40_DEV_SRC_MEMORY, \
27 .src_info.data_width = STEDMA40_WORD_WIDTH, \
28 .dst_info.data_width = STEDMA40_WORD_WIDTH, \
29 .src_info.psize = STEDMA40_PSIZE_LOG_16, \
30 .dst_info.psize = STEDMA40_PSIZE_LOG_16, \
31 }
32
33static struct stedma40_chan_cfg musb_dma_rx_ch[UX500_MUSB_DMA_NUM_RX_CHANNELS]
34 = {
35 MUSB_DMA40_RX_CH,
36 MUSB_DMA40_RX_CH,
37 MUSB_DMA40_RX_CH,
38 MUSB_DMA40_RX_CH,
39 MUSB_DMA40_RX_CH,
40 MUSB_DMA40_RX_CH,
41 MUSB_DMA40_RX_CH,
42 MUSB_DMA40_RX_CH
43};
44
45static struct stedma40_chan_cfg musb_dma_tx_ch[UX500_MUSB_DMA_NUM_TX_CHANNELS]
46 = {
47 MUSB_DMA40_TX_CH,
48 MUSB_DMA40_TX_CH,
49 MUSB_DMA40_TX_CH,
50 MUSB_DMA40_TX_CH,
51 MUSB_DMA40_TX_CH,
52 MUSB_DMA40_TX_CH,
53 MUSB_DMA40_TX_CH,
54 MUSB_DMA40_TX_CH,
55};
56
57static void *ux500_dma_rx_param_array[UX500_MUSB_DMA_NUM_RX_CHANNELS] = {
58 &musb_dma_rx_ch[0],
59 &musb_dma_rx_ch[1],
60 &musb_dma_rx_ch[2],
61 &musb_dma_rx_ch[3],
62 &musb_dma_rx_ch[4],
63 &musb_dma_rx_ch[5],
64 &musb_dma_rx_ch[6],
65 &musb_dma_rx_ch[7]
66};
67
68static void *ux500_dma_tx_param_array[UX500_MUSB_DMA_NUM_TX_CHANNELS] = {
69 &musb_dma_tx_ch[0],
70 &musb_dma_tx_ch[1],
71 &musb_dma_tx_ch[2],
72 &musb_dma_tx_ch[3],
73 &musb_dma_tx_ch[4],
74 &musb_dma_tx_ch[5],
75 &musb_dma_tx_ch[6],
76 &musb_dma_tx_ch[7]
77};
78
79static struct ux500_musb_board_data musb_board_data = {
80 .dma_rx_param_array = ux500_dma_rx_param_array,
81 .dma_tx_param_array = ux500_dma_tx_param_array,
82 .num_rx_channels = UX500_MUSB_DMA_NUM_RX_CHANNELS,
83 .num_tx_channels = UX500_MUSB_DMA_NUM_TX_CHANNELS,
84 .dma_filter = stedma40_filter,
85};
86
87static u64 ux500_musb_dmamask = DMA_BIT_MASK(32);
88
89static struct musb_hdrc_config musb_hdrc_config = {
90 .multipoint = true,
91 .dyn_fifo = true,
92 .num_eps = 16,
93 .ram_bits = 16,
94};
95
96static struct musb_hdrc_platform_data musb_platform_data = {
97#if defined(CONFIG_USB_MUSB_OTG)
98 .mode = MUSB_OTG,
99#elif defined(CONFIG_USB_MUSB_PERIPHERAL)
100 .mode = MUSB_PERIPHERAL,
101#else /* defined(CONFIG_USB_MUSB_HOST) */
102 .mode = MUSB_HOST,
103#endif
104 .config = &musb_hdrc_config,
105 .board_data = &musb_board_data,
106};
107
108static struct resource usb_resources[] = {
109 [0] = {
110 .name = "usb-mem",
111 .flags = IORESOURCE_MEM,
112 },
113
114 [1] = {
115 .name = "mc", /* hard-coded in musb */
116 .flags = IORESOURCE_IRQ,
117 },
118};
119
120struct platform_device ux500_musb_device = {
121 .name = "musb-ux500",
122 .id = 0,
123 .dev = {
124 .platform_data = &musb_platform_data,
125 .dma_mask = &ux500_musb_dmamask,
126 .coherent_dma_mask = DMA_BIT_MASK(32),
127 },
128 .num_resources = ARRAY_SIZE(usb_resources),
129 .resource = usb_resources,
130};
131
132static inline void ux500_usb_dma_update_rx_ch_config(int *src_dev_type)
133{
134 u32 idx;
135
136 for (idx = 0; idx < UX500_MUSB_DMA_NUM_RX_CHANNELS; idx++)
137 musb_dma_rx_ch[idx].src_dev_type = src_dev_type[idx];
138}
139
140static inline void ux500_usb_dma_update_tx_ch_config(int *dst_dev_type)
141{
142 u32 idx;
143
144 for (idx = 0; idx < UX500_MUSB_DMA_NUM_TX_CHANNELS; idx++)
145 musb_dma_tx_ch[idx].dst_dev_type = dst_dev_type[idx];
146}
147
148void ux500_add_usb(resource_size_t base, int irq, int *dma_rx_cfg,
149 int *dma_tx_cfg)
150{
151 ux500_musb_device.resource[0].start = base;
152 ux500_musb_device.resource[0].end = base + SZ_64K - 1;
153 ux500_musb_device.resource[1].start = irq;
154 ux500_musb_device.resource[1].end = irq;
155
156 ux500_usb_dma_update_rx_ch_config(dma_rx_cfg);
157 ux500_usb_dma_update_tx_ch_config(dma_tx_cfg);
158
159 platform_device_register(&ux500_musb_device);
160}
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 89266382b536..0074b8dba793 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -819,8 +819,8 @@ config CACHE_FEROCEON_L2_WRITETHROUGH
819config CACHE_L2X0 819config CACHE_L2X0
820 bool "Enable the L2x0 outer cache controller" 820 bool "Enable the L2x0 outer cache controller"
821 depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \ 821 depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
822 REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX || \ 822 REALVIEW_EB_A9MP || SOC_IMX35 || SOC_IMX31 || MACH_REALVIEW_PBX || \
823 ARCH_NOMADIK || ARCH_OMAP4 || ARCH_S5PV310 || ARCH_TEGRA || \ 823 ARCH_NOMADIK || ARCH_OMAP4 || ARCH_EXYNOS4 || ARCH_TEGRA || \
824 ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE 824 ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE
825 default y 825 default y
826 select OUTER_CACHE 826 select OUTER_CACHE
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index 389f21795015..b0cb4258e382 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -33,6 +33,7 @@ config ARCH_MX3
33config ARCH_MXC91231 33config ARCH_MXC91231
34 bool "MXC91231-based" 34 bool "MXC91231-based"
35 select CPU_V6 35 select CPU_V6
36 select MXC_AVIC
36 help 37 help
37 This enables support for systems based on the Freescale MXC91231 family 38 This enables support for systems based on the Freescale MXC91231 family
38 39
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
index 5fd20e96876c..a1387875a491 100644
--- a/arch/arm/plat-mxc/Makefile
+++ b/arch/arm/plat-mxc/Makefile
@@ -13,7 +13,6 @@ obj-$(CONFIG_IMX_HAVE_IOMUX_V1) += iomux-v1.o
13obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o 13obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o
14obj-$(CONFIG_IRAM_ALLOC) += iram_alloc.o 14obj-$(CONFIG_IRAM_ALLOC) += iram_alloc.o
15obj-$(CONFIG_MXC_PWM) += pwm.o 15obj-$(CONFIG_MXC_PWM) += pwm.o
16obj-$(CONFIG_USB_EHCI_MXC) += ehci.o
17obj-$(CONFIG_MXC_ULPI) += ulpi.o 16obj-$(CONFIG_MXC_ULPI) += ulpi.o
18obj-$(CONFIG_MXC_USE_EPIT) += epit.o 17obj-$(CONFIG_MXC_USE_EPIT) += epit.o
19obj-$(CONFIG_ARCH_MXC_AUDMUX_V1) += audmux-v1.o 18obj-$(CONFIG_ARCH_MXC_AUDMUX_V1) += audmux-v1.o
diff --git a/arch/arm/plat-mxc/devices.c b/arch/arm/plat-mxc/devices.c
index e9bcefe79a43..eee1b6096a08 100644
--- a/arch/arm/plat-mxc/devices.c
+++ b/arch/arm/plat-mxc/devices.c
@@ -81,6 +81,8 @@ struct platform_device *__init imx_add_platform_device_dmamask(
81 ret = platform_device_add(pdev); 81 ret = platform_device_add(pdev);
82 if (ret) { 82 if (ret) {
83err: 83err:
84 if (dmamask)
85 kfree(pdev->dev.dma_mask);
84 platform_device_put(pdev); 86 platform_device_put(pdev);
85 return ERR_PTR(ret); 87 return ERR_PTR(ret);
86 } 88 }
diff --git a/arch/arm/plat-mxc/devices/platform-fec.c b/arch/arm/plat-mxc/devices/platform-fec.c
index b50c3517d083..6561c9df5f0d 100644
--- a/arch/arm/plat-mxc/devices/platform-fec.c
+++ b/arch/arm/plat-mxc/devices/platform-fec.c
@@ -31,6 +31,11 @@ const struct imx_fec_data imx35_fec_data __initconst =
31 imx_fec_data_entry_single(MX35); 31 imx_fec_data_entry_single(MX35);
32#endif 32#endif
33 33
34#ifdef CONFIG_SOC_IMX50
35const struct imx_fec_data imx50_fec_data __initconst =
36 imx_fec_data_entry_single(MX50);
37#endif
38
34#ifdef CONFIG_SOC_IMX51 39#ifdef CONFIG_SOC_IMX51
35const struct imx_fec_data imx51_fec_data __initconst = 40const struct imx_fec_data imx51_fec_data __initconst =
36 imx_fec_data_entry_single(MX51); 41 imx_fec_data_entry_single(MX51);
@@ -57,7 +62,7 @@ struct platform_device *__init imx_add_fec(
57 }, 62 },
58 }; 63 };
59 64
60 return imx_add_platform_device("fec", 0 /* -1? */, 65 return imx_add_platform_device_dmamask("fec", 0,
61 res, ARRAY_SIZE(res), 66 res, ARRAY_SIZE(res),
62 pdata, sizeof(*pdata)); 67 pdata, sizeof(*pdata), DMA_BIT_MASK(32));
63} 68}
diff --git a/arch/arm/plat-mxc/devices/platform-imx-dma.c b/arch/arm/plat-mxc/devices/platform-imx-dma.c
index 33530d2d5ed1..3538b85ede91 100644
--- a/arch/arm/plat-mxc/devices/platform-imx-dma.c
+++ b/arch/arm/plat-mxc/devices/platform-imx-dma.c
@@ -94,7 +94,7 @@ static struct sdma_script_start_addrs addr_imx25_to1 = {
94}; 94};
95#endif 95#endif
96 96
97#ifdef CONFIG_ARCH_MX31 97#ifdef CONFIG_SOC_IMX31
98static struct sdma_script_start_addrs addr_imx31_to1 = { 98static struct sdma_script_start_addrs addr_imx31_to1 = {
99 .per_2_per_addr = 1677, 99 .per_2_per_addr = 1677,
100}; 100};
@@ -106,7 +106,7 @@ static struct sdma_script_start_addrs addr_imx31_to2 = {
106}; 106};
107#endif 107#endif
108 108
109#ifdef CONFIG_ARCH_MX35 109#ifdef CONFIG_SOC_IMX35
110static struct sdma_script_start_addrs addr_imx35_to1 = { 110static struct sdma_script_start_addrs addr_imx35_to1 = {
111 .ap_2_ap_addr = 642, 111 .ap_2_ap_addr = 642,
112 .uart_2_mcu_addr = 817, 112 .uart_2_mcu_addr = 817,
@@ -194,7 +194,7 @@ static int __init imxXX_add_imx_dma(void)
194 } else 194 } else
195#endif 195#endif
196 196
197#if defined(CONFIG_ARCH_MX51) 197#if defined(CONFIG_SOC_IMX51)
198 if (cpu_is_mx51()) { 198 if (cpu_is_mx51()) {
199 imx51_imx_sdma_data.pdata.script_addrs = &addr_imx51_to1; 199 imx51_imx_sdma_data.pdata.script_addrs = &addr_imx51_to1;
200 ret = imx_add_imx_sdma(&imx51_imx_sdma_data); 200 ret = imx_add_imx_sdma(&imx51_imx_sdma_data);
diff --git a/arch/arm/plat-mxc/devices/platform-imx-fb.c b/arch/arm/plat-mxc/devices/platform-imx-fb.c
index 6100a7d824dd..79a1cb18a5b0 100644
--- a/arch/arm/plat-mxc/devices/platform-imx-fb.c
+++ b/arch/arm/plat-mxc/devices/platform-imx-fb.c
@@ -16,6 +16,11 @@
16 .irq = soc ## _INT_LCDC, \ 16 .irq = soc ## _INT_LCDC, \
17 } 17 }
18 18
19#ifdef CONFIG_SOC_IMX1
20const struct imx_imx_fb_data imx1_imx_fb_data __initconst =
21 imx_imx_fb_data_entry_single(MX1, SZ_4K);
22#endif /* ifdef CONFIG_SOC_IMX1 */
23
19#ifdef CONFIG_SOC_IMX21 24#ifdef CONFIG_SOC_IMX21
20const struct imx_imx_fb_data imx21_imx_fb_data __initconst = 25const struct imx_imx_fb_data imx21_imx_fb_data __initconst =
21 imx_imx_fb_data_entry_single(MX21, SZ_4K); 26 imx_imx_fb_data_entry_single(MX21, SZ_4K);
diff --git a/arch/arm/plat-mxc/devices/platform-imx-i2c.c b/arch/arm/plat-mxc/devices/platform-imx-i2c.c
index 7ba94e1bbda3..2ab74f0da9a6 100644
--- a/arch/arm/plat-mxc/devices/platform-imx-i2c.c
+++ b/arch/arm/plat-mxc/devices/platform-imx-i2c.c
@@ -69,6 +69,16 @@ const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst = {
69}; 69};
70#endif /* ifdef CONFIG_SOC_IMX35 */ 70#endif /* ifdef CONFIG_SOC_IMX35 */
71 71
72#ifdef CONFIG_SOC_IMX50
73const struct imx_imx_i2c_data imx50_imx_i2c_data[] __initconst = {
74#define imx50_imx_i2c_data_entry(_id, _hwid) \
75 imx_imx_i2c_data_entry(MX50, _id, _hwid, SZ_4K)
76 imx50_imx_i2c_data_entry(0, 1),
77 imx50_imx_i2c_data_entry(1, 2),
78 imx50_imx_i2c_data_entry(2, 3),
79};
80#endif /* ifdef CONFIG_SOC_IMX51 */
81
72#ifdef CONFIG_SOC_IMX51 82#ifdef CONFIG_SOC_IMX51
73const struct imx_imx_i2c_data imx51_imx_i2c_data[] __initconst = { 83const struct imx_imx_i2c_data imx51_imx_i2c_data[] __initconst = {
74#define imx51_imx_i2c_data_entry(_id, _hwid) \ 84#define imx51_imx_i2c_data_entry(_id, _hwid) \
diff --git a/arch/arm/plat-mxc/devices/platform-imx2-wdt.c b/arch/arm/plat-mxc/devices/platform-imx2-wdt.c
index e0aec61177f4..5e07ef2bf1c4 100644
--- a/arch/arm/plat-mxc/devices/platform-imx2-wdt.c
+++ b/arch/arm/plat-mxc/devices/platform-imx2-wdt.c
@@ -53,6 +53,15 @@ const struct imx_imx2_wdt_data imx51_imx2_wdt_data[] __initconst = {
53}; 53};
54#endif /* ifdef CONFIG_SOC_IMX51 */ 54#endif /* ifdef CONFIG_SOC_IMX51 */
55 55
56#ifdef CONFIG_SOC_IMX53
57const struct imx_imx2_wdt_data imx53_imx2_wdt_data[] __initconst = {
58#define imx53_imx2_wdt_data_entry(_id, _hwid) \
59 imx_imx2_wdt_data_entry(MX53, _id, _hwid, SZ_16K)
60 imx53_imx2_wdt_data_entry(0, 1),
61 imx53_imx2_wdt_data_entry(1, 2),
62};
63#endif /* ifdef CONFIG_SOC_IMX53 */
64
56struct platform_device *__init imx_add_imx2_wdt( 65struct platform_device *__init imx_add_imx2_wdt(
57 const struct imx_imx2_wdt_data *data) 66 const struct imx_imx2_wdt_data *data)
58{ 67{
diff --git a/arch/arm/plat-mxc/devices/platform-spi_imx.c b/arch/arm/plat-mxc/devices/platform-spi_imx.c
index 013c85f20b58..f4a60ab6763b 100644
--- a/arch/arm/plat-mxc/devices/platform-spi_imx.c
+++ b/arch/arm/plat-mxc/devices/platform-spi_imx.c
@@ -21,6 +21,15 @@
21#define imx_spi_imx_data_entry(soc, type, devid, id, hwid, size) \ 21#define imx_spi_imx_data_entry(soc, type, devid, id, hwid, size) \
22 [id] = imx_spi_imx_data_entry_single(soc, type, devid, id, hwid, size) 22 [id] = imx_spi_imx_data_entry_single(soc, type, devid, id, hwid, size)
23 23
24#ifdef CONFIG_SOC_IMX1
25const struct imx_spi_imx_data imx1_cspi_data[] __initconst = {
26#define imx1_cspi_data_entry(_id, _hwid) \
27 imx_spi_imx_data_entry(MX1, CSPI, "imx1-cspi", _id, _hwid, SZ_4K)
28 imx1_cspi_data_entry(0, 1),
29 imx1_cspi_data_entry(1, 2),
30};
31#endif
32
24#ifdef CONFIG_SOC_IMX21 33#ifdef CONFIG_SOC_IMX21
25const struct imx_spi_imx_data imx21_cspi_data[] __initconst = { 34const struct imx_spi_imx_data imx21_cspi_data[] __initconst = {
26#define imx21_cspi_data_entry(_id, _hwid) \ 35#define imx21_cspi_data_entry(_id, _hwid) \
diff --git a/arch/arm/plat-mxc/ehci.c b/arch/arm/plat-mxc/ehci.c
deleted file mode 100644
index 8772ce346a58..000000000000
--- a/arch/arm/plat-mxc/ehci.c
+++ /dev/null
@@ -1,369 +0,0 @@
1/*
2 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
3 * Copyright (C) 2010 Freescale Semiconductor, Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details.
14 */
15
16#include <linux/platform_device.h>
17#include <linux/io.h>
18
19#include <mach/hardware.h>
20#include <mach/mxc_ehci.h>
21
22#define USBCTRL_OTGBASE_OFFSET 0x600
23
24#define MX31_OTG_SIC_SHIFT 29
25#define MX31_OTG_SIC_MASK (0x3 << MX31_OTG_SIC_SHIFT)
26#define MX31_OTG_PM_BIT (1 << 24)
27
28#define MX31_H2_SIC_SHIFT 21
29#define MX31_H2_SIC_MASK (0x3 << MX31_H2_SIC_SHIFT)
30#define MX31_H2_PM_BIT (1 << 16)
31#define MX31_H2_DT_BIT (1 << 5)
32
33#define MX31_H1_SIC_SHIFT 13
34#define MX31_H1_SIC_MASK (0x3 << MX31_H1_SIC_SHIFT)
35#define MX31_H1_PM_BIT (1 << 8)
36#define MX31_H1_DT_BIT (1 << 4)
37
38#define MX35_OTG_SIC_SHIFT 29
39#define MX35_OTG_SIC_MASK (0x3 << MX35_OTG_SIC_SHIFT)
40#define MX35_OTG_PM_BIT (1 << 24)
41
42#define MX35_H1_SIC_SHIFT 21
43#define MX35_H1_SIC_MASK (0x3 << MX35_H1_SIC_SHIFT)
44#define MX35_H1_PM_BIT (1 << 8)
45#define MX35_H1_IPPUE_UP_BIT (1 << 7)
46#define MX35_H1_IPPUE_DOWN_BIT (1 << 6)
47#define MX35_H1_TLL_BIT (1 << 5)
48#define MX35_H1_USBTE_BIT (1 << 4)
49
50#define MXC_OTG_OFFSET 0
51#define MXC_H1_OFFSET 0x200
52#define MXC_H2_OFFSET 0x400
53
54/* USB_CTRL */
55#define MXC_OTG_UCTRL_OWIE_BIT (1 << 27) /* OTG wakeup intr enable */
56#define MXC_OTG_UCTRL_OPM_BIT (1 << 24) /* OTG power mask */
57#define MXC_H1_UCTRL_H1UIE_BIT (1 << 12) /* Host1 ULPI interrupt enable */
58#define MXC_H1_UCTRL_H1WIE_BIT (1 << 11) /* HOST1 wakeup intr enable */
59#define MXC_H1_UCTRL_H1PM_BIT (1 << 8) /* HOST1 power mask */
60
61/* USB_PHY_CTRL_FUNC */
62#define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) /* OTG Disable Overcurrent Event */
63#define MXC_H1_OC_DIS_BIT (1 << 5) /* UH1 Disable Overcurrent Event */
64
65/* USBH2CTRL */
66#define MXC_H2_UCTRL_H2UIE_BIT (1 << 8)
67#define MXC_H2_UCTRL_H2WIE_BIT (1 << 7)
68#define MXC_H2_UCTRL_H2PM_BIT (1 << 4)
69
70#define MXC_USBCMD_OFFSET 0x140
71
72/* USBCMD */
73#define MXC_UCMD_ITC_NO_THRESHOLD_MASK (~(0xff << 16)) /* Interrupt Threshold Control */
74
75int mxc_initialize_usb_hw(int port, unsigned int flags)
76{
77 unsigned int v;
78#if defined(CONFIG_SOC_IMX25)
79 if (cpu_is_mx25()) {
80 v = readl(MX25_IO_ADDRESS(MX25_USB_BASE_ADDR +
81 USBCTRL_OTGBASE_OFFSET));
82
83 switch (port) {
84 case 0: /* OTG port */
85 v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT);
86 v |= (flags & MXC_EHCI_INTERFACE_MASK)
87 << MX35_OTG_SIC_SHIFT;
88 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
89 v |= MX35_OTG_PM_BIT;
90
91 break;
92 case 1: /* H1 port */
93 v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_TLL_BIT |
94 MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT);
95 v |= (flags & MXC_EHCI_INTERFACE_MASK)
96 << MX35_H1_SIC_SHIFT;
97 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
98 v |= MX35_H1_PM_BIT;
99
100 if (!(flags & MXC_EHCI_TTL_ENABLED))
101 v |= MX35_H1_TLL_BIT;
102
103 if (flags & MXC_EHCI_INTERNAL_PHY)
104 v |= MX35_H1_USBTE_BIT;
105
106 if (flags & MXC_EHCI_IPPUE_DOWN)
107 v |= MX35_H1_IPPUE_DOWN_BIT;
108
109 if (flags & MXC_EHCI_IPPUE_UP)
110 v |= MX35_H1_IPPUE_UP_BIT;
111
112 break;
113 default:
114 return -EINVAL;
115 }
116
117 writel(v, MX25_IO_ADDRESS(MX25_USB_BASE_ADDR +
118 USBCTRL_OTGBASE_OFFSET));
119 return 0;
120 }
121#endif /* if defined(CONFIG_SOC_IMX25) */
122#if defined(CONFIG_ARCH_MX3)
123 if (cpu_is_mx31()) {
124 v = readl(MX31_IO_ADDRESS(MX31_USB_BASE_ADDR +
125 USBCTRL_OTGBASE_OFFSET));
126
127 switch (port) {
128 case 0: /* OTG port */
129 v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);
130 v |= (flags & MXC_EHCI_INTERFACE_MASK)
131 << MX31_OTG_SIC_SHIFT;
132 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
133 v |= MX31_OTG_PM_BIT;
134
135 break;
136 case 1: /* H1 port */
137 v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT | MX31_H1_DT_BIT);
138 v |= (flags & MXC_EHCI_INTERFACE_MASK)
139 << MX31_H1_SIC_SHIFT;
140 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
141 v |= MX31_H1_PM_BIT;
142
143 if (!(flags & MXC_EHCI_TTL_ENABLED))
144 v |= MX31_H1_DT_BIT;
145
146 break;
147 case 2: /* H2 port */
148 v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT | MX31_H2_DT_BIT);
149 v |= (flags & MXC_EHCI_INTERFACE_MASK)
150 << MX31_H2_SIC_SHIFT;
151 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
152 v |= MX31_H2_PM_BIT;
153
154 if (!(flags & MXC_EHCI_TTL_ENABLED))
155 v |= MX31_H2_DT_BIT;
156
157 break;
158 default:
159 return -EINVAL;
160 }
161
162 writel(v, MX31_IO_ADDRESS(MX31_USB_BASE_ADDR +
163 USBCTRL_OTGBASE_OFFSET));
164 return 0;
165 }
166
167 if (cpu_is_mx35()) {
168 v = readl(MX35_IO_ADDRESS(MX35_USB_BASE_ADDR +
169 USBCTRL_OTGBASE_OFFSET));
170
171 switch (port) {
172 case 0: /* OTG port */
173 v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT);
174 v |= (flags & MXC_EHCI_INTERFACE_MASK)
175 << MX35_OTG_SIC_SHIFT;
176 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
177 v |= MX35_OTG_PM_BIT;
178
179 break;
180 case 1: /* H1 port */
181 v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_TLL_BIT |
182 MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT);
183 v |= (flags & MXC_EHCI_INTERFACE_MASK)
184 << MX35_H1_SIC_SHIFT;
185 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
186 v |= MX35_H1_PM_BIT;
187
188 if (!(flags & MXC_EHCI_TTL_ENABLED))
189 v |= MX35_H1_TLL_BIT;
190
191 if (flags & MXC_EHCI_INTERNAL_PHY)
192 v |= MX35_H1_USBTE_BIT;
193
194 if (flags & MXC_EHCI_IPPUE_DOWN)
195 v |= MX35_H1_IPPUE_DOWN_BIT;
196
197 if (flags & MXC_EHCI_IPPUE_UP)
198 v |= MX35_H1_IPPUE_UP_BIT;
199
200 break;
201 default:
202 return -EINVAL;
203 }
204
205 writel(v, MX35_IO_ADDRESS(MX35_USB_BASE_ADDR +
206 USBCTRL_OTGBASE_OFFSET));
207 return 0;
208 }
209#endif /* CONFIG_ARCH_MX3 */
210#ifdef CONFIG_MACH_MX27
211 if (cpu_is_mx27()) {
212 /* On i.MX27 we can use the i.MX31 USBCTRL bits, they
213 * are identical
214 */
215 v = readl(MX27_IO_ADDRESS(MX27_USB_BASE_ADDR +
216 USBCTRL_OTGBASE_OFFSET));
217 switch (port) {
218 case 0: /* OTG port */
219 v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);
220 v |= (flags & MXC_EHCI_INTERFACE_MASK)
221 << MX31_OTG_SIC_SHIFT;
222 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
223 v |= MX31_OTG_PM_BIT;
224 break;
225 case 1: /* H1 port */
226 v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT | MX31_H1_DT_BIT);
227 v |= (flags & MXC_EHCI_INTERFACE_MASK)
228 << MX31_H1_SIC_SHIFT;
229 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
230 v |= MX31_H1_PM_BIT;
231
232 if (!(flags & MXC_EHCI_TTL_ENABLED))
233 v |= MX31_H1_DT_BIT;
234
235 break;
236 case 2: /* H2 port */
237 v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT | MX31_H2_DT_BIT);
238 v |= (flags & MXC_EHCI_INTERFACE_MASK)
239 << MX31_H2_SIC_SHIFT;
240 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
241 v |= MX31_H2_PM_BIT;
242
243 if (!(flags & MXC_EHCI_TTL_ENABLED))
244 v |= MX31_H2_DT_BIT;
245
246 break;
247 default:
248 return -EINVAL;
249 }
250 writel(v, MX27_IO_ADDRESS(MX27_USB_BASE_ADDR +
251 USBCTRL_OTGBASE_OFFSET));
252 return 0;
253 }
254#endif /* CONFIG_MACH_MX27 */
255#ifdef CONFIG_SOC_IMX51
256 if (cpu_is_mx51()) {
257 void __iomem *usb_base;
258 void __iomem *usbotg_base;
259 void __iomem *usbother_base;
260 int ret = 0;
261
262 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
263 if (!usb_base) {
264 printk(KERN_ERR "%s(): ioremap failed\n", __func__);
265 return -ENOMEM;
266 }
267
268 switch (port) {
269 case 0: /* OTG port */
270 usbotg_base = usb_base + MXC_OTG_OFFSET;
271 break;
272 case 1: /* Host 1 port */
273 usbotg_base = usb_base + MXC_H1_OFFSET;
274 break;
275 case 2: /* Host 2 port */
276 usbotg_base = usb_base + MXC_H2_OFFSET;
277 break;
278 default:
279 printk(KERN_ERR"%s no such port %d\n", __func__, port);
280 ret = -ENOENT;
281 goto error;
282 }
283 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
284
285 switch (port) {
286 case 0: /*OTG port */
287 if (flags & MXC_EHCI_INTERNAL_PHY) {
288 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
289
290 if (flags & MXC_EHCI_POWER_PINS_ENABLED) {
291 /* OC/USBPWR is not used */
292 v |= MXC_OTG_PHYCTRL_OC_DIS_BIT;
293 } else {
294 /* OC/USBPWR is used */
295 v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT;
296 }
297 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
298
299 v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
300 if (flags & MXC_EHCI_WAKEUP_ENABLED)
301 v |= MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup enable */
302 else
303 v &= ~MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup disable */
304 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
305 v |= MXC_OTG_UCTRL_OPM_BIT;
306 else
307 v &= ~MXC_OTG_UCTRL_OPM_BIT;
308 __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
309 }
310 break;
311 case 1: /* Host 1 */
312 /*Host ULPI */
313 v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
314 if (flags & MXC_EHCI_WAKEUP_ENABLED) {
315 /* HOST1 wakeup/ULPI intr enable */
316 v |= (MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);
317 } else {
318 /* HOST1 wakeup/ULPI intr disable */
319 v &= ~(MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);
320 }
321
322 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
323 v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/
324 else
325 v |= MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/
326 __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
327
328 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
329 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
330 v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */
331 else
332 v |= MXC_H1_OC_DIS_BIT; /* OC is not used */
333 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
334
335 v = __raw_readl(usbotg_base + MXC_USBCMD_OFFSET);
336 if (flags & MXC_EHCI_ITC_NO_THRESHOLD)
337 /* Interrupt Threshold Control:Immediate (no threshold) */
338 v &= MXC_UCMD_ITC_NO_THRESHOLD_MASK;
339 __raw_writel(v, usbotg_base + MXC_USBCMD_OFFSET);
340 break;
341 case 2: /* Host 2 ULPI */
342 v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET);
343 if (flags & MXC_EHCI_WAKEUP_ENABLED) {
344 /* HOST1 wakeup/ULPI intr enable */
345 v |= (MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT);
346 } else {
347 /* HOST1 wakeup/ULPI intr disable */
348 v &= ~(MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT);
349 }
350
351 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
352 v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/
353 else
354 v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/
355 __raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET);
356 break;
357 }
358
359error:
360 iounmap(usb_base);
361 return ret;
362 }
363#endif
364 printk(KERN_WARNING
365 "%s() unable to setup USBCONTROL for this CPU\n", __func__);
366 return -EINVAL;
367}
368EXPORT_SYMBOL(mxc_initialize_usb_hw);
369
diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c
index d17b3c996b84..57d59855f9ec 100644
--- a/arch/arm/plat-mxc/gpio.c
+++ b/arch/arm/plat-mxc/gpio.c
@@ -233,6 +233,7 @@ static int gpio_set_wake_irq(struct irq_data *d, u32 enable)
233} 233}
234 234
235static struct irq_chip gpio_irq_chip = { 235static struct irq_chip gpio_irq_chip = {
236 .name = "GPIO",
236 .irq_ack = gpio_ack_irq, 237 .irq_ack = gpio_ack_irq,
237 .irq_mask = gpio_mask_irq, 238 .irq_mask = gpio_mask_irq,
238 .irq_unmask = gpio_unmask_irq, 239 .irq_unmask = gpio_unmask_irq,
@@ -349,113 +350,3 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt)
349 350
350 return 0; 351 return 0;
351} 352}
352
353#define DEFINE_IMX_GPIO_PORT_IRQ_HIGH(soc, _id, _hwid, _irq, _irq_high) \
354 { \
355 .chip.label = "gpio-" #_id, \
356 .irq = _irq, \
357 .irq_high = _irq_high, \
358 .base = soc ## _IO_ADDRESS( \
359 soc ## _GPIO ## _hwid ## _BASE_ADDR), \
360 .virtual_irq_start = MXC_GPIO_IRQ_START + (_id) * 32, \
361 }
362
363#define DEFINE_IMX_GPIO_PORT_IRQ(soc, _id, _hwid, _irq) \
364 DEFINE_IMX_GPIO_PORT_IRQ_HIGH(soc, _id, _hwid, _irq, 0)
365#define DEFINE_IMX_GPIO_PORT(soc, _id, _hwid) \
366 DEFINE_IMX_GPIO_PORT_IRQ(soc, _id, _hwid, 0)
367
368#define DEFINE_REGISTER_FUNCTION(prefix) \
369int __init prefix ## _register_gpios(void) \
370{ \
371 return mxc_gpio_init(prefix ## _gpio_ports, \
372 ARRAY_SIZE(prefix ## _gpio_ports)); \
373}
374
375#if defined(CONFIG_SOC_IMX1)
376static struct mxc_gpio_port imx1_gpio_ports[] = {
377 DEFINE_IMX_GPIO_PORT_IRQ(MX1, 0, 1, MX1_GPIO_INT_PORTA),
378 DEFINE_IMX_GPIO_PORT_IRQ(MX1, 1, 2, MX1_GPIO_INT_PORTB),
379 DEFINE_IMX_GPIO_PORT_IRQ(MX1, 2, 3, MX1_GPIO_INT_PORTC),
380 DEFINE_IMX_GPIO_PORT_IRQ(MX1, 3, 4, MX1_GPIO_INT_PORTD),
381};
382
383DEFINE_REGISTER_FUNCTION(imx1)
384
385#endif /* if defined(CONFIG_SOC_IMX1) */
386
387#if defined(CONFIG_SOC_IMX21)
388static struct mxc_gpio_port imx21_gpio_ports[] = {
389 DEFINE_IMX_GPIO_PORT_IRQ(MX21, 0, 1, MX21_INT_GPIO),
390 DEFINE_IMX_GPIO_PORT(MX21, 1, 2),
391 DEFINE_IMX_GPIO_PORT(MX21, 2, 3),
392 DEFINE_IMX_GPIO_PORT(MX21, 3, 4),
393 DEFINE_IMX_GPIO_PORT(MX21, 4, 5),
394 DEFINE_IMX_GPIO_PORT(MX21, 5, 6),
395};
396
397DEFINE_REGISTER_FUNCTION(imx21)
398
399#endif /* if defined(CONFIG_SOC_IMX21) */
400
401#if defined(CONFIG_SOC_IMX25)
402static struct mxc_gpio_port imx25_gpio_ports[] = {
403 DEFINE_IMX_GPIO_PORT_IRQ(MX25, 0, 1, MX25_INT_GPIO1),
404 DEFINE_IMX_GPIO_PORT_IRQ(MX25, 1, 2, MX25_INT_GPIO2),
405 DEFINE_IMX_GPIO_PORT_IRQ(MX25, 2, 3, MX25_INT_GPIO3),
406 DEFINE_IMX_GPIO_PORT_IRQ(MX25, 3, 4, MX25_INT_GPIO4),
407};
408
409DEFINE_REGISTER_FUNCTION(imx25)
410
411#endif /* if defined(CONFIG_SOC_IMX25) */
412
413#if defined(CONFIG_SOC_IMX27)
414static struct mxc_gpio_port imx27_gpio_ports[] = {
415 DEFINE_IMX_GPIO_PORT_IRQ(MX27, 0, 1, MX27_INT_GPIO),
416 DEFINE_IMX_GPIO_PORT(MX27, 1, 2),
417 DEFINE_IMX_GPIO_PORT(MX27, 2, 3),
418 DEFINE_IMX_GPIO_PORT(MX27, 3, 4),
419 DEFINE_IMX_GPIO_PORT(MX27, 4, 5),
420 DEFINE_IMX_GPIO_PORT(MX27, 5, 6),
421};
422
423DEFINE_REGISTER_FUNCTION(imx27)
424
425#endif /* if defined(CONFIG_SOC_IMX27) */
426
427#if defined(CONFIG_SOC_IMX31)
428static struct mxc_gpio_port imx31_gpio_ports[] = {
429 DEFINE_IMX_GPIO_PORT_IRQ(MX31, 0, 1, MX31_INT_GPIO1),
430 DEFINE_IMX_GPIO_PORT_IRQ(MX31, 1, 2, MX31_INT_GPIO2),
431 DEFINE_IMX_GPIO_PORT_IRQ(MX31, 2, 3, MX31_INT_GPIO3),
432};
433
434DEFINE_REGISTER_FUNCTION(imx31)
435
436#endif /* if defined(CONFIG_SOC_IMX31) */
437
438#if defined(CONFIG_SOC_IMX35)
439static struct mxc_gpio_port imx35_gpio_ports[] = {
440 DEFINE_IMX_GPIO_PORT_IRQ(MX35, 0, 1, MX35_INT_GPIO1),
441 DEFINE_IMX_GPIO_PORT_IRQ(MX35, 1, 2, MX35_INT_GPIO2),
442 DEFINE_IMX_GPIO_PORT_IRQ(MX35, 2, 3, MX35_INT_GPIO3),
443};
444
445DEFINE_REGISTER_FUNCTION(imx35)
446
447#endif /* if defined(CONFIG_SOC_IMX35) */
448
449#if defined(CONFIG_SOC_IMX50)
450static struct mxc_gpio_port imx50_gpio_ports[] = {
451 DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 0, 1, MX50_INT_GPIO1_LOW, MX50_INT_GPIO1_HIGH),
452 DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 1, 2, MX50_INT_GPIO2_LOW, MX50_INT_GPIO2_HIGH),
453 DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 2, 3, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH),
454 DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 3, 4, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH),
455 DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 4, 5, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH),
456 DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 5, 6, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH),
457};
458
459DEFINE_REGISTER_FUNCTION(imx50)
460
461#endif /* if defined(CONFIG_SOC_IMX50) */
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index aea2cd3b6d15..a22ebe11a602 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -24,6 +24,16 @@ extern void mx50_map_io(void);
24extern void mx51_map_io(void); 24extern void mx51_map_io(void);
25extern void mx53_map_io(void); 25extern void mx53_map_io(void);
26extern void mxc91231_map_io(void); 26extern void mxc91231_map_io(void);
27extern void imx1_init_early(void);
28extern void imx21_init_early(void);
29extern void imx25_init_early(void);
30extern void imx27_init_early(void);
31extern void imx31_init_early(void);
32extern void imx35_init_early(void);
33extern void imx50_init_early(void);
34extern void imx51_init_early(void);
35extern void imx53_init_early(void);
36extern void mxc91231_init_early(void);
27extern void mxc_init_irq(void __iomem *); 37extern void mxc_init_irq(void __iomem *);
28extern void tzic_init_irq(void __iomem *); 38extern void tzic_init_irq(void __iomem *);
29extern void mx1_init_irq(void); 39extern void mx1_init_irq(void);
diff --git a/arch/arm/plat-mxc/include/mach/gpio.h b/arch/arm/plat-mxc/include/mach/gpio.h
index 0044e2f1bea8..a2747f12813e 100644
--- a/arch/arm/plat-mxc/include/mach/gpio.h
+++ b/arch/arm/plat-mxc/include/mach/gpio.h
@@ -46,6 +46,21 @@ struct mxc_gpio_port {
46 spinlock_t lock; 46 spinlock_t lock;
47}; 47};
48 48
49#define DEFINE_IMX_GPIO_PORT_IRQ_HIGH(soc, _id, _hwid, _irq, _irq_high) \
50 { \
51 .chip.label = "gpio-" #_id, \
52 .irq = _irq, \
53 .irq_high = _irq_high, \
54 .base = soc ## _IO_ADDRESS( \
55 soc ## _GPIO ## _hwid ## _BASE_ADDR), \
56 .virtual_irq_start = MXC_GPIO_IRQ_START + (_id) * 32, \
57 }
58
59#define DEFINE_IMX_GPIO_PORT_IRQ(soc, _id, _hwid, _irq) \
60 DEFINE_IMX_GPIO_PORT_IRQ_HIGH(soc, _id, _hwid, _irq, 0)
61#define DEFINE_IMX_GPIO_PORT(soc, _id, _hwid) \
62 DEFINE_IMX_GPIO_PORT_IRQ(soc, _id, _hwid, 0)
63
49int mxc_gpio_init(struct mxc_gpio_port*, int); 64int mxc_gpio_init(struct mxc_gpio_port*, int);
50 65
51#endif 66#endif
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx3.h b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
index cbaed295a2bf..c92f0b1f216f 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
@@ -112,12 +112,12 @@ enum iomux_gp_func {
112 * - setups the iomux according to the configuration 112 * - setups the iomux according to the configuration
113 * - if the pin is configured as a GPIO, we claim it through kernel gpiolib 113 * - if the pin is configured as a GPIO, we claim it through kernel gpiolib
114 */ 114 */
115int mxc_iomux_alloc_pin(const unsigned int pin, const char *label); 115int mxc_iomux_alloc_pin(unsigned int pin, const char *label);
116/* 116/*
117 * setups mutliple pins 117 * setups mutliple pins
118 * convenient way to call the above function with tables 118 * convenient way to call the above function with tables
119 */ 119 */
120int mxc_iomux_setup_multiple_pins(unsigned int *pin_list, unsigned count, 120int mxc_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count,
121 const char *label); 121 const char *label);
122 122
123/* 123/*
@@ -126,12 +126,12 @@ int mxc_iomux_setup_multiple_pins(unsigned int *pin_list, unsigned count,
126 * - frees the GPIO if the pin was configured as GPIO 126 * - frees the GPIO if the pin was configured as GPIO
127 * - DOES NOT reconfigure the IOMUX in its reset state 127 * - DOES NOT reconfigure the IOMUX in its reset state
128 */ 128 */
129void mxc_iomux_release_pin(const unsigned int pin); 129void mxc_iomux_release_pin(unsigned int pin);
130/* 130/*
131 * releases multiple pins 131 * releases multiple pins
132 * convenvient way to call the above function with tables 132 * convenvient way to call the above function with tables
133 */ 133 */
134void mxc_iomux_release_multiple_pins(unsigned int *pin_list, int count); 134void mxc_iomux_release_multiple_pins(const unsigned int *pin_list, int count);
135 135
136/* 136/*
137 * This function enables/disables the general purpose function for a particular 137 * This function enables/disables the general purpose function for a particular
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx35.h b/arch/arm/plat-mxc/include/mach/iomux-mx35.h
index 2a24bae1b878..3117c18bbbd9 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx35.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx35.h
@@ -989,13 +989,13 @@
989#define MX35_PAD_ATA_DATA2__IPU_DIAGB_9 IOMUX_PAD(0x6e8, 0x284, 6, 0x0, 0, NO_PAD_CTRL) 989#define MX35_PAD_ATA_DATA2__IPU_DIAGB_9 IOMUX_PAD(0x6e8, 0x284, 6, 0x0, 0, NO_PAD_CTRL)
990#define MX35_PAD_ATA_DATA2__ARM11P_TOP_TRACE_28 IOMUX_PAD(0x6e8, 0x284, 7, 0x0, 0, NO_PAD_CTRL) 990#define MX35_PAD_ATA_DATA2__ARM11P_TOP_TRACE_28 IOMUX_PAD(0x6e8, 0x284, 7, 0x0, 0, NO_PAD_CTRL)
991 991
992#define MX35_PAD_ATA_DATA3__ATA_DATA_3 IOMUX_PAD(0x6e8, 0x288, 0, 0x0, 0, NO_PAD_CTRL) 992#define MX35_PAD_ATA_DATA3__ATA_DATA_3 IOMUX_PAD(0x6ec, 0x288, 0, 0x0, 0, NO_PAD_CTRL)
993#define MX35_PAD_ATA_DATA3__ESDHC3_CLK IOMUX_PAD(0x6e8, 0x288, 1, 0x814, 1, NO_PAD_CTRL) 993#define MX35_PAD_ATA_DATA3__ESDHC3_CLK IOMUX_PAD(0x6ec, 0x288, 1, 0x814, 1, NO_PAD_CTRL)
994#define MX35_PAD_ATA_DATA3__USB_TOP_USBOTG_DATA_5 IOMUX_PAD(0x6e8, 0x288, 2, 0x9b8, 1, NO_PAD_CTRL) 994#define MX35_PAD_ATA_DATA3__USB_TOP_USBOTG_DATA_5 IOMUX_PAD(0x6ec, 0x288, 2, 0x9b8, 1, NO_PAD_CTRL)
995#define MX35_PAD_ATA_DATA3__CSPI2_SCLK IOMUX_PAD(0x6e8, 0x288, 4, 0x7e0, 2, NO_PAD_CTRL) 995#define MX35_PAD_ATA_DATA3__CSPI2_SCLK IOMUX_PAD(0x6ec, 0x288, 4, 0x7e0, 2, NO_PAD_CTRL)
996#define MX35_PAD_ATA_DATA3__GPIO2_16 IOMUX_PAD(0x6e8, 0x288, 5, 0x884, 1, NO_PAD_CTRL) 996#define MX35_PAD_ATA_DATA3__GPIO2_16 IOMUX_PAD(0x6ec, 0x288, 5, 0x884, 1, NO_PAD_CTRL)
997#define MX35_PAD_ATA_DATA3__IPU_DIAGB_10 IOMUX_PAD(0x6e8, 0x288, 6, 0x0, 0, NO_PAD_CTRL) 997#define MX35_PAD_ATA_DATA3__IPU_DIAGB_10 IOMUX_PAD(0x6ec, 0x288, 6, 0x0, 0, NO_PAD_CTRL)
998#define MX35_PAD_ATA_DATA3__ARM11P_TOP_TRACE_29 IOMUX_PAD(0x6e8, 0x288, 7, 0x0, 0, NO_PAD_CTRL) 998#define MX35_PAD_ATA_DATA3__ARM11P_TOP_TRACE_29 IOMUX_PAD(0x6ec, 0x288, 7, 0x0, 0, NO_PAD_CTRL)
999 999
1000#define MX35_PAD_ATA_DATA4__ATA_DATA_4 IOMUX_PAD(0x6f0, 0x28c, 0, 0x0, 0, NO_PAD_CTRL) 1000#define MX35_PAD_ATA_DATA4__ATA_DATA_4 IOMUX_PAD(0x6f0, 0x28c, 0, 0x0, 0, NO_PAD_CTRL)
1001#define MX35_PAD_ATA_DATA4__ESDHC3_CMD IOMUX_PAD(0x6f0, 0x28c, 1, 0x818, 1, NO_PAD_CTRL) 1001#define MX35_PAD_ATA_DATA4__ESDHC3_CMD IOMUX_PAD(0x6f0, 0x28c, 1, 0x818, 1, NO_PAD_CTRL)
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx50.h b/arch/arm/plat-mxc/include/mach/iomux-mx50.h
index 058a922ca147..98e7fd0b9083 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx50.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx50.h
@@ -86,7 +86,7 @@
86#define MX50_PAD_I2C1_SCL__I2C1_SCL IOMUX_PAD(0x2EC, 0x40, IOMUX_CONFIG_SION, 0x0, 0, \ 86#define MX50_PAD_I2C1_SCL__I2C1_SCL IOMUX_PAD(0x2EC, 0x40, IOMUX_CONFIG_SION, 0x0, 0, \
87 MX50_I2C_PAD_CTRL) 87 MX50_I2C_PAD_CTRL)
88#define MX50_PAD_I2C1_SCL__GPIO_6_18 IOMUX_PAD(0x2EC, 0x40, 1, 0x0, 0, NO_PAD_CTRL) 88#define MX50_PAD_I2C1_SCL__GPIO_6_18 IOMUX_PAD(0x2EC, 0x40, 1, 0x0, 0, NO_PAD_CTRL)
89#define MX50_PAD_I2C1_SCL__UART2_TXD IOMUX_PAD(0x2EC, 0x40, 2, 0x7cc, 0, MX50_UART_PAD_CTRL) 89#define MX50_PAD_I2C1_SCL__UART2_TXD IOMUX_PAD(0x2EC, 0x40, 2, 0x0, 0, MX50_UART_PAD_CTRL)
90 90
91#define MX50_PAD_I2C1_SDA__I2C1_SDA IOMUX_PAD(0x2F0, 0x44, IOMUX_CONFIG_SION, 0x0, 0, \ 91#define MX50_PAD_I2C1_SDA__I2C1_SDA IOMUX_PAD(0x2F0, 0x44, IOMUX_CONFIG_SION, 0x0, 0, \
92 MX50_I2C_PAD_CTRL) 92 MX50_I2C_PAD_CTRL)
@@ -96,7 +96,7 @@
96#define MX50_PAD_I2C2_SCL__I2C2_SCL IOMUX_PAD(0x2F4, 0x48, IOMUX_CONFIG_SION, 0x0, 0, \ 96#define MX50_PAD_I2C2_SCL__I2C2_SCL IOMUX_PAD(0x2F4, 0x48, IOMUX_CONFIG_SION, 0x0, 0, \
97 MX50_I2C_PAD_CTRL) 97 MX50_I2C_PAD_CTRL)
98#define MX50_PAD_I2C2_SCL__GPIO_6_20 IOMUX_PAD(0x2F4, 0x48, 1, 0x0, 0, NO_PAD_CTRL) 98#define MX50_PAD_I2C2_SCL__GPIO_6_20 IOMUX_PAD(0x2F4, 0x48, 1, 0x0, 0, NO_PAD_CTRL)
99#define MX50_PAD_I2C2_SCL__UART2_CTS IOMUX_PAD(0x2F4, 0x48, 2, 0x7c8, 0, MX50_UART_PAD_CTRL) 99#define MX50_PAD_I2C2_SCL__UART2_CTS IOMUX_PAD(0x2F4, 0x48, 2, 0x0, 0, MX50_UART_PAD_CTRL)
100#define MX50_PAD_I2C2_SCL__DCDC_OK IOMUX_PAD(0x2F4, 0x48, 7, 0x0, 0, NO_PAD_CTRL) 100#define MX50_PAD_I2C2_SCL__DCDC_OK IOMUX_PAD(0x2F4, 0x48, 7, 0x0, 0, NO_PAD_CTRL)
101 101
102#define MX50_PAD_I2C2_SDA__I2C2_SDA IOMUX_PAD(0x2F8, 0x4C, IOMUX_CONFIG_SION, 0x0, 0, \ 102#define MX50_PAD_I2C2_SDA__I2C2_SDA IOMUX_PAD(0x2F8, 0x4C, IOMUX_CONFIG_SION, 0x0, 0, \
@@ -172,7 +172,7 @@
172 172
173#define MX50_PAD_SSI_RXFS__AUD3_RXFS IOMUX_PAD(0x328, 0x7C, 0, 0x0, 0, NO_PAD_CTRL) 173#define MX50_PAD_SSI_RXFS__AUD3_RXFS IOMUX_PAD(0x328, 0x7C, 0, 0x0, 0, NO_PAD_CTRL)
174#define MX50_PAD_SSI_RXFS__GPIO_6_4 IOMUX_PAD(0x328, 0x7C, 1, 0x0, 0, NO_PAD_CTRL) 174#define MX50_PAD_SSI_RXFS__GPIO_6_4 IOMUX_PAD(0x328, 0x7C, 1, 0x0, 0, NO_PAD_CTRL)
175#define MX50_PAD_SSI_RXFS__UART5_TXD IOMUX_PAD(0x328, 0x7C, 2, 0x7e4, 0, MX50_UART_PAD_CTRL) 175#define MX50_PAD_SSI_RXFS__UART5_TXD IOMUX_PAD(0x328, 0x7C, 2, 0x0, 0, MX50_UART_PAD_CTRL)
176#define MX50_PAD_SSI_RXFS__WEIM_D6 IOMUX_PAD(0x328, 0x7C, 3, 0x804, 0, NO_PAD_CTRL) 176#define MX50_PAD_SSI_RXFS__WEIM_D6 IOMUX_PAD(0x328, 0x7C, 3, 0x804, 0, NO_PAD_CTRL)
177#define MX50_PAD_SSI_RXFS__CSPI_SS2 IOMUX_PAD(0x328, 0x7C, 4, 0x6f0, 0, MX50_CSPI_SS_PAD) 177#define MX50_PAD_SSI_RXFS__CSPI_SS2 IOMUX_PAD(0x328, 0x7C, 4, 0x6f0, 0, MX50_CSPI_SS_PAD)
178#define MX50_PAD_SSI_RXFS__FEC_COL IOMUX_PAD(0x328, 0x7C, 5, 0x770, 0, PAD_CTL_DSE_HIGH) 178#define MX50_PAD_SSI_RXFS__FEC_COL IOMUX_PAD(0x328, 0x7C, 5, 0x770, 0, PAD_CTL_DSE_HIGH)
@@ -186,25 +186,25 @@
186#define MX50_PAD_SSI_RXC__FEC_RX_CLK IOMUX_PAD(0x32C, 0x80, 5, 0x780, 0, NO_PAD_CTRL) 186#define MX50_PAD_SSI_RXC__FEC_RX_CLK IOMUX_PAD(0x32C, 0x80, 5, 0x780, 0, NO_PAD_CTRL)
187#define MX50_PAD_SSI_RXC__FEC_MDIO IOMUX_PAD(0x32C, 0x80, 6, 0x774, 1, MX50_FEC_PAD_CTRL) 187#define MX50_PAD_SSI_RXC__FEC_MDIO IOMUX_PAD(0x32C, 0x80, 6, 0x774, 1, MX50_FEC_PAD_CTRL)
188 188
189#define MX50_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x330, 0x84, 0, 0x7c4, 0, MX50_UART_PAD_CTRL) 189#define MX50_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x330, 0x84, 0, 0x0, 0, MX50_UART_PAD_CTRL)
190#define MX50_PAD_UART1_TXD__GPIO_6_6 IOMUX_PAD(0x330, 0x84, 1, 0x0, 0, NO_PAD_CTRL) 190#define MX50_PAD_UART1_TXD__GPIO_6_6 IOMUX_PAD(0x330, 0x84, 1, 0x0, 0, NO_PAD_CTRL)
191 191
192#define MX50_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x334, 0x88, 0, 0x7c4, 1, MX50_UART_PAD_CTRL) 192#define MX50_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x334, 0x88, 0, 0x7c4, 1, MX50_UART_PAD_CTRL)
193#define MX50_PAD_UART1_RXD__GPIO_6_7 IOMUX_PAD(0x334, 0x88, 1, 0x0, 0, NO_PAD_CTRL) 193#define MX50_PAD_UART1_RXD__GPIO_6_7 IOMUX_PAD(0x334, 0x88, 1, 0x0, 0, NO_PAD_CTRL)
194 194
195#define MX50_PAD_UART1_CTS__UART1_CTS IOMUX_PAD(0x338, 0x8C, 0, 0x7c0, 0, MX50_UART_PAD_CTRL) 195#define MX50_PAD_UART1_CTS__UART1_CTS IOMUX_PAD(0x338, 0x8C, 0, 0x0, 0, MX50_UART_PAD_CTRL)
196#define MX50_PAD_UART1_CTS__GPIO_6_8 IOMUX_PAD(0x338, 0x8C, 1, 0x0, 0, NO_PAD_CTRL) 196#define MX50_PAD_UART1_CTS__GPIO_6_8 IOMUX_PAD(0x338, 0x8C, 1, 0x0, 0, NO_PAD_CTRL)
197#define MX50_PAD_UART1_CTS__UART5_TXD IOMUX_PAD(0x338, 0x8C, 2, 0x7e4, 2, MX50_UART_PAD_CTRL) 197#define MX50_PAD_UART1_CTS__UART5_TXD IOMUX_PAD(0x338, 0x8C, 2, 0x0, 0, MX50_UART_PAD_CTRL)
198#define MX50_PAD_UART1_CTS__SD4_D4 IOMUX_PAD(0x338, 0x8C, 4, 0x760, 0, MX50_SD_PAD_CTRL) 198#define MX50_PAD_UART1_CTS__SD4_D4 IOMUX_PAD(0x338, 0x8C, 4, 0x760, 0, MX50_SD_PAD_CTRL)
199#define MX50_PAD_UART1_CTS__SD4_CMD IOMUX_PAD(0x338, 0x8C, 5, 0x74c, 0, MX50_SD_PAD_CTRL) 199#define MX50_PAD_UART1_CTS__SD4_CMD IOMUX_PAD(0x338, 0x8C, 5, 0x74c, 0, MX50_SD_PAD_CTRL)
200 200
201#define MX50_PAD_UART1_RTS__UART1_RTS IOMUX_PAD(0x33C, 0x90, 0, 0x7c0, 1, MX50_UART_PAD_CTRL) 201#define MX50_PAD_UART1_RTS__UART1_RTS IOMUX_PAD(0x33C, 0x90, 0, 0x7c0, 1, MX50_UART_PAD_CTRL)
202#define MX50_PAD_UART1_RTS__GPIO_6_9 IOMUX_PAD(0x33C, 0x90, 1, 0x0, 0, NO_PAD_CTRL) 202#define MX50_PAD_UART1_RTS__GPIO_6_9 IOMUX_PAD(0x33C, 0x90, 1, 0x0, 0, NO_PAD_CTRL)
203#define MX50_PAD_UART1_RTS__UART5_RXD IOMUX_PAD(0x33C, 0x90, 2, 0x7e4, 3, MX50_UART_PAD_CTRL) 203#define MX50_PAD_UART1_RTS__UART5_RXD IOMUX_PAD(0x33C, 0x90, 2, 0x7e4, 3, MX50_UART_PAD_CTRL)
204#define MX50_PAD_UART1_RTS__SD4_D5 IOMUX_PAD(0x33C, 0x90, 4, 0x0, 1, MX50_SD_PAD_CTRL) 204#define MX50_PAD_UART1_RTS__SD4_D5 IOMUX_PAD(0x33C, 0x90, 4, 0x764, 0, MX50_SD_PAD_CTRL)
205#define MX50_PAD_UART1_RTS__SD4_CLK IOMUX_PAD(0x33C, 0x90, 5, 0x0, 1, MX50_SD_PAD_CTRL) 205#define MX50_PAD_UART1_RTS__SD4_CLK IOMUX_PAD(0x33C, 0x90, 5, 0x748, 0, MX50_SD_PAD_CTRL)
206 206
207#define MX50_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x340, 0x94, 0, 0x7cc, 2, MX50_UART_PAD_CTRL) 207#define MX50_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x340, 0x94, 0, 0x0, 0, MX50_UART_PAD_CTRL)
208#define MX50_PAD_UART2_TXD__GPIO_6_10 IOMUX_PAD(0x340, 0x94, 1, 0x0, 0, NO_PAD_CTRL) 208#define MX50_PAD_UART2_TXD__GPIO_6_10 IOMUX_PAD(0x340, 0x94, 1, 0x0, 0, NO_PAD_CTRL)
209#define MX50_PAD_UART2_TXD__SD4_D6 IOMUX_PAD(0x340, 0x94, 4, 0x768, 0, MX50_SD_PAD_CTRL) 209#define MX50_PAD_UART2_TXD__SD4_D6 IOMUX_PAD(0x340, 0x94, 4, 0x768, 0, MX50_SD_PAD_CTRL)
210#define MX50_PAD_UART2_TXD__SD4_D4 IOMUX_PAD(0x340, 0x94, 5, 0x760, 1, MX50_SD_PAD_CTRL) 210#define MX50_PAD_UART2_TXD__SD4_D4 IOMUX_PAD(0x340, 0x94, 5, 0x760, 1, MX50_SD_PAD_CTRL)
@@ -214,7 +214,7 @@
214#define MX50_PAD_UART2_RXD__SD4_D7 IOMUX_PAD(0x344, 0x98, 4, 0x76c, 0, MX50_SD_PAD_CTRL) 214#define MX50_PAD_UART2_RXD__SD4_D7 IOMUX_PAD(0x344, 0x98, 4, 0x76c, 0, MX50_SD_PAD_CTRL)
215#define MX50_PAD_UART2_RXD__SD4_D5 IOMUX_PAD(0x344, 0x98, 5, 0x764, 1, MX50_SD_PAD_CTRL) 215#define MX50_PAD_UART2_RXD__SD4_D5 IOMUX_PAD(0x344, 0x98, 5, 0x764, 1, MX50_SD_PAD_CTRL)
216 216
217#define MX50_PAD_UART2_CTS__UART2_CTS IOMUX_PAD(0x348, 0x9C, 0, 0x7c8, 2, MX50_UART_PAD_CTRL) 217#define MX50_PAD_UART2_CTS__UART2_CTS IOMUX_PAD(0x348, 0x9C, 0, 0x0, 0, MX50_UART_PAD_CTRL)
218#define MX50_PAD_UART2_CTS__GPIO_6_12 IOMUX_PAD(0x348, 0x9C, 1, 0x0, 0, NO_PAD_CTRL) 218#define MX50_PAD_UART2_CTS__GPIO_6_12 IOMUX_PAD(0x348, 0x9C, 1, 0x0, 0, NO_PAD_CTRL)
219#define MX50_PAD_UART2_CTS__SD4_CMD IOMUX_PAD(0x348, 0x9C, 4, 0x74c, 1, MX50_SD_PAD_CTRL) 219#define MX50_PAD_UART2_CTS__SD4_CMD IOMUX_PAD(0x348, 0x9C, 4, 0x74c, 1, MX50_SD_PAD_CTRL)
220#define MX50_PAD_UART2_CTS__SD4_D6 IOMUX_PAD(0x348, 0x9C, 5, 0x768, 1, MX50_SD_PAD_CTRL) 220#define MX50_PAD_UART2_CTS__SD4_D6 IOMUX_PAD(0x348, 0x9C, 5, 0x768, 1, MX50_SD_PAD_CTRL)
@@ -224,7 +224,7 @@
224#define MX50_PAD_UART2_RTS__SD4_CLK IOMUX_PAD(0x34C, 0xA0, 4, 0x748, 1, MX50_SD_PAD_CTRL) 224#define MX50_PAD_UART2_RTS__SD4_CLK IOMUX_PAD(0x34C, 0xA0, 4, 0x748, 1, MX50_SD_PAD_CTRL)
225#define MX50_PAD_UART2_RTS__SD4_D7 IOMUX_PAD(0x34C, 0xA0, 5, 0x76c, 1, MX50_SD_PAD_CTRL) 225#define MX50_PAD_UART2_RTS__SD4_D7 IOMUX_PAD(0x34C, 0xA0, 5, 0x76c, 1, MX50_SD_PAD_CTRL)
226 226
227#define MX50_PAD_UART3_TXD__UART3_TXD IOMUX_PAD(0x350, 0xA4, 0, 0x7d4, 0, MX50_UART_PAD_CTRL) 227#define MX50_PAD_UART3_TXD__UART3_TXD IOMUX_PAD(0x350, 0xA4, 0, 0x0, 0, MX50_UART_PAD_CTRL)
228#define MX50_PAD_UART3_TXD__GPIO_6_14 IOMUX_PAD(0x350, 0xA4, 1, 0x0, 0, NO_PAD_CTRL) 228#define MX50_PAD_UART3_TXD__GPIO_6_14 IOMUX_PAD(0x350, 0xA4, 1, 0x0, 0, NO_PAD_CTRL)
229#define MX50_PAD_UART3_TXD__SD1_D4 IOMUX_PAD(0x350, 0xA4, 3, 0x0, 0, MX50_SD_PAD_CTRL) 229#define MX50_PAD_UART3_TXD__SD1_D4 IOMUX_PAD(0x350, 0xA4, 3, 0x0, 0, MX50_SD_PAD_CTRL)
230#define MX50_PAD_UART3_TXD__SD4_D0 IOMUX_PAD(0x350, 0xA4, 4, 0x750, 0, MX50_SD_PAD_CTRL) 230#define MX50_PAD_UART3_TXD__SD4_D0 IOMUX_PAD(0x350, 0xA4, 4, 0x750, 0, MX50_SD_PAD_CTRL)
@@ -238,9 +238,9 @@
238#define MX50_PAD_UART3_RXD__SD2_CD IOMUX_PAD(0x354, 0xA8, 5, 0x740, 0, MX50_SD_PAD_CTRL) 238#define MX50_PAD_UART3_RXD__SD2_CD IOMUX_PAD(0x354, 0xA8, 5, 0x740, 0, MX50_SD_PAD_CTRL)
239#define MX50_PAD_UART3_RXD__WEIM_D13 IOMUX_PAD(0x354, 0xA8, 6, 0x820, 0, NO_PAD_CTRL) 239#define MX50_PAD_UART3_RXD__WEIM_D13 IOMUX_PAD(0x354, 0xA8, 6, 0x820, 0, NO_PAD_CTRL)
240 240
241#define MX50_PAD_UART4_TXD__UART4_TXD IOMUX_PAD(0x358, 0xAC, 0, 0x7dc, 0, MX50_UART_PAD_CTRL) 241#define MX50_PAD_UART4_TXD__UART4_TXD IOMUX_PAD(0x358, 0xAC, 0, 0x0, 0, MX50_UART_PAD_CTRL)
242#define MX50_PAD_UART4_TXD__GPIO_6_16 IOMUX_PAD(0x358, 0xAC, 1, 0x0, 0, NO_PAD_CTRL) 242#define MX50_PAD_UART4_TXD__GPIO_6_16 IOMUX_PAD(0x358, 0xAC, 1, 0x0, 0, NO_PAD_CTRL)
243#define MX50_PAD_UART4_TXD__UART3_CTS IOMUX_PAD(0x358, 0xAC, 2, 0x7d0, 0, MX50_UART_PAD_CTRL) 243#define MX50_PAD_UART4_TXD__UART3_CTS IOMUX_PAD(0x358, 0xAC, 2, 0x0, 0, MX50_UART_PAD_CTRL)
244#define MX50_PAD_UART4_TXD__SD1_D6 IOMUX_PAD(0x358, 0xAC, 3, 0x0, 0, MX50_SD_PAD_CTRL) 244#define MX50_PAD_UART4_TXD__SD1_D6 IOMUX_PAD(0x358, 0xAC, 3, 0x0, 0, MX50_SD_PAD_CTRL)
245#define MX50_PAD_UART4_TXD__SD4_D2 IOMUX_PAD(0x358, 0xAC, 4, 0x758, 0, MX50_SD_PAD_CTRL) 245#define MX50_PAD_UART4_TXD__SD4_D2 IOMUX_PAD(0x358, 0xAC, 4, 0x758, 0, MX50_SD_PAD_CTRL)
246#define MX50_PAD_UART4_TXD__SD2_LCTL IOMUX_PAD(0x358, 0xAC, 5, 0x0, 0, MX50_SD_PAD_CTRL) 246#define MX50_PAD_UART4_TXD__SD2_LCTL IOMUX_PAD(0x358, 0xAC, 5, 0x0, 0, MX50_SD_PAD_CTRL)
@@ -278,7 +278,7 @@
278#define MX50_PAD_ECSPI1_MOSI__GPIO_4_13 IOMUX_PAD(0x374, 0xC8, 1, 0x0, 0, NO_PAD_CTRL) 278#define MX50_PAD_ECSPI1_MOSI__GPIO_4_13 IOMUX_PAD(0x374, 0xC8, 1, 0x0, 0, NO_PAD_CTRL)
279#define MX50_PAD_ECSPI1_MOSI__CSPI_SS1 IOMUX_PAD(0x374, 0xC8, 2, 0x6ec, 1, MX50_CSPI_SS_PAD) 279#define MX50_PAD_ECSPI1_MOSI__CSPI_SS1 IOMUX_PAD(0x374, 0xC8, 2, 0x6ec, 1, MX50_CSPI_SS_PAD)
280#define MX50_PAD_ECSPI1_MOSI__ECSPI2_SS1 IOMUX_PAD(0x374, 0xC8, 3, 0x0, 0, MX50_CSPI_SS_PAD) 280#define MX50_PAD_ECSPI1_MOSI__ECSPI2_SS1 IOMUX_PAD(0x374, 0xC8, 3, 0x0, 0, MX50_CSPI_SS_PAD)
281#define MX50_PAD_ECSPI1_MOSI__UART3_CTS IOMUX_PAD(0x374, 0xC8, 4, 0x7d0, 3, MX50_UART_PAD_CTRL) 281#define MX50_PAD_ECSPI1_MOSI__UART3_CTS IOMUX_PAD(0x374, 0xC8, 4, 0x0, 0, MX50_UART_PAD_CTRL)
282#define MX50_PAD_ECSPI1_MOSI__EPDC_SDCE7 IOMUX_PAD(0x374, 0xC8, 5, 0x0, 0, NO_PAD_CTRL) 282#define MX50_PAD_ECSPI1_MOSI__EPDC_SDCE7 IOMUX_PAD(0x374, 0xC8, 5, 0x0, 0, NO_PAD_CTRL)
283#define MX50_PAD_ECSPI1_MOSI__WEIM_D9 IOMUX_PAD(0x374, 0xC8, 7, 0x810, 0, NO_PAD_CTRL) 283#define MX50_PAD_ECSPI1_MOSI__WEIM_D9 IOMUX_PAD(0x374, 0xC8, 7, 0x810, 0, NO_PAD_CTRL)
284 284
@@ -294,7 +294,7 @@
294#define MX50_PAD_ECSPI1_SS0__GPIO_4_15 IOMUX_PAD(0x37C, 0xD0, 1, 0x0, 0, PAD_CTL_PUS_100K_UP) 294#define MX50_PAD_ECSPI1_SS0__GPIO_4_15 IOMUX_PAD(0x37C, 0xD0, 1, 0x0, 0, PAD_CTL_PUS_100K_UP)
295#define MX50_PAD_ECSPI1_SS0__CSPI_SS3 IOMUX_PAD(0x37C, 0xD0, 2, 0x6f4, 1, MX50_CSPI_SS_PAD) 295#define MX50_PAD_ECSPI1_SS0__CSPI_SS3 IOMUX_PAD(0x37C, 0xD0, 2, 0x6f4, 1, MX50_CSPI_SS_PAD)
296#define MX50_PAD_ECSPI1_SS0__ECSPI2_SS3 IOMUX_PAD(0x37C, 0xD0, 3, 0x0, 0, MX50_CSPI_SS_PAD) 296#define MX50_PAD_ECSPI1_SS0__ECSPI2_SS3 IOMUX_PAD(0x37C, 0xD0, 3, 0x0, 0, MX50_CSPI_SS_PAD)
297#define MX50_PAD_ECSPI1_SS0__UART4_CTS IOMUX_PAD(0x37C, 0xD0, 4, 0x7d8, 1, MX50_UART_PAD_CTRL) 297#define MX50_PAD_ECSPI1_SS0__UART4_CTS IOMUX_PAD(0x37C, 0xD0, 4, 0x0, 0, MX50_UART_PAD_CTRL)
298#define MX50_PAD_ECSPI1_SS0__EPDC_SDCE9 IOMUX_PAD(0x37C, 0xD0, 5, 0x0, 0, NO_PAD_CTRL) 298#define MX50_PAD_ECSPI1_SS0__EPDC_SDCE9 IOMUX_PAD(0x37C, 0xD0, 5, 0x0, 0, NO_PAD_CTRL)
299#define MX50_PAD_ECSPI1_SS0__WEIM_D11 IOMUX_PAD(0x37C, 0xD0, 7, 0x818, 0, NO_PAD_CTRL) 299#define MX50_PAD_ECSPI1_SS0__WEIM_D11 IOMUX_PAD(0x37C, 0xD0, 7, 0x818, 0, NO_PAD_CTRL)
300 300
@@ -311,17 +311,17 @@
311#define MX50_PAD_ECSPI2_MOSI__GPIO_4_17 IOMUX_PAD(0x384, 0xD8, 1, 0x0, 0, NO_PAD_CTRL) 311#define MX50_PAD_ECSPI2_MOSI__GPIO_4_17 IOMUX_PAD(0x384, 0xD8, 1, 0x0, 0, NO_PAD_CTRL)
312#define MX50_PAD_ECSPI2_MOSI__ELCDIF_RD IOMUX_PAD(0x384, 0xD8, 2, 0x0, 0, NO_PAD_CTRL) 312#define MX50_PAD_ECSPI2_MOSI__ELCDIF_RD IOMUX_PAD(0x384, 0xD8, 2, 0x0, 0, NO_PAD_CTRL)
313#define MX50_PAD_ECSPI2_MOSI__ECSPI1_SS1 IOMUX_PAD(0x384, 0xD8, 3, 0x0, 0, MX50_CSPI_SS_PAD) 313#define MX50_PAD_ECSPI2_MOSI__ECSPI1_SS1 IOMUX_PAD(0x384, 0xD8, 3, 0x0, 0, MX50_CSPI_SS_PAD)
314#define MX50_PAD_ECSPI2_MOSI__UART5_CTS IOMUX_PAD(0x384, 0xD8, 4, 0x7e0, 1, MX50_UART_PAD_CTRL) 314#define MX50_PAD_ECSPI2_MOSI__UART5_CTS IOMUX_PAD(0x384, 0xD8, 4, 0x0, 0, MX50_UART_PAD_CTRL)
315#define MX50_PAD_ECSPI2_MOSI__ELCDIF_EN IOMUX_PAD(0x384, 0xD8, 5, 0x0, 0, NO_PAD_CTRL) 315#define MX50_PAD_ECSPI2_MOSI__ELCDIF_EN IOMUX_PAD(0x384, 0xD8, 5, 0x0, 0, NO_PAD_CTRL)
316#define MX50_PAD_ECSPI2_MOSI__NANDF_CEN5 IOMUX_PAD(0x384, 0xD8, 6, 0x0, 0, NO_PAD_CTRL) 316#define MX50_PAD_ECSPI2_MOSI__NANDF_CEN5 IOMUX_PAD(0x384, 0xD8, 6, 0x0, 0, NO_PAD_CTRL)
317#define MX50_PAD_ECSPI2_MOSI__WEIM_D9 IOMUX_PAD(0x384, 0xD8, 7, 0x810, 1, NO_PAD_CTRL) 317#define MX50_PAD_ECSPI2_MOSI__WEIM_D9 IOMUX_PAD(0x384, 0xD8, 7, 0x810, 1, NO_PAD_CTRL)
318 318
319#define MX50_PAD_ECSPI2_MISO__ECSPI2_MISO IOMUX_PAD(0x388, 0xDC, 0, 0x73c, 0, NO_PAD_CTRL) 319#define MX50_PAD_ECSPI2_MISO__ECSPI2_MISO IOMUX_PAD(0x388, 0xDC, 0, 0x0, 0, NO_PAD_CTRL)
320#define MX50_PAD_ECSPI2_MISO__GPIO_4_18 IOMUX_PAD(0x388, 0xDC, 1, 0x0, 0, PAD_CTL_PUS_100K_UP) 320#define MX50_PAD_ECSPI2_MISO__GPIO_4_18 IOMUX_PAD(0x388, 0xDC, 1, 0x0, 0, PAD_CTL_PUS_100K_UP)
321#define MX50_PAD_ECSPI2_MISO__ELCDIF_RS IOMUX_PAD(0x388, 0xDC, 2, 0x0, 0, NO_PAD_CTRL) 321#define MX50_PAD_ECSPI2_MISO__ELCDIF_RS IOMUX_PAD(0x388, 0xDC, 2, 0x0, 0, NO_PAD_CTRL)
322#define MX50_PAD_ECSPI2_MISO__ECSPI1_SS2 IOMUX_PAD(0x388, 0xDC, 3, 0x0, 0, MX50_CSPI_SS_PAD) 322#define MX50_PAD_ECSPI2_MISO__ECSPI1_SS2 IOMUX_PAD(0x388, 0xDC, 3, 0x0, 0, MX50_CSPI_SS_PAD)
323#define MX50_PAD_ECSPI2_MISO__UART5_TXD IOMUX_PAD(0x388, 0xDC, 4, 0x7e4, 4, MX50_UART_PAD_CTRL) 323#define MX50_PAD_ECSPI2_MISO__UART5_TXD IOMUX_PAD(0x388, 0xDC, 4, 0x0, 0, MX50_UART_PAD_CTRL)
324#define MX50_PAD_ECSPI2_MISO__ELCDIF_VSYNC IOMUX_PAD(0x388, 0xDC, 5, 0x0, 0, NO_PAD_CTRL) 324#define MX50_PAD_ECSPI2_MISO__ELCDIF_VSYNC IOMUX_PAD(0x388, 0xDC, 5, 0x73c, 0, NO_PAD_CTRL)
325#define MX50_PAD_ECSPI2_MISO__NANDF_CEN6 IOMUX_PAD(0x388, 0xDC, 6, 0x0, 0, NO_PAD_CTRL) 325#define MX50_PAD_ECSPI2_MISO__NANDF_CEN6 IOMUX_PAD(0x388, 0xDC, 6, 0x0, 0, NO_PAD_CTRL)
326#define MX50_PAD_ECSPI2_MISO__WEIM_D10 IOMUX_PAD(0x388, 0xDC, 7, 0x814, 1, NO_PAD_CTRL) 326#define MX50_PAD_ECSPI2_MISO__WEIM_D10 IOMUX_PAD(0x388, 0xDC, 7, 0x814, 1, NO_PAD_CTRL)
327 327
@@ -503,7 +503,7 @@
503#define MX50_PAD_DISP_RD__ELCDIF_EN IOMUX_PAD(0x430, 0x150, 2, 0x0, 0, MX50_ELCDIF_PAD_CTRL) 503#define MX50_PAD_DISP_RD__ELCDIF_EN IOMUX_PAD(0x430, 0x150, 2, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
504#define MX50_PAD_DISP_RD__WEIM_A25 IOMUX_PAD(0x430, 0x150, 3, 0x0, 0, NO_PAD_CTRL) 504#define MX50_PAD_DISP_RD__WEIM_A25 IOMUX_PAD(0x430, 0x150, 3, 0x0, 0, NO_PAD_CTRL)
505 505
506#define MX50_PAD_DISP_RS__ELCDIF_RS IOMUX_PAD(0x434, 0x154, 0, 0x73c, 1, MX50_ELCDIF_PAD_CTRL) 506#define MX50_PAD_DISP_RS__ELCDIF_RS IOMUX_PAD(0x434, 0x154, 0, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
507#define MX50_PAD_DISP_RS__GPIO_2_17 IOMUX_PAD(0x434, 0x154, 1, 0x0, 0, NO_PAD_CTRL) 507#define MX50_PAD_DISP_RS__GPIO_2_17 IOMUX_PAD(0x434, 0x154, 1, 0x0, 0, NO_PAD_CTRL)
508#define MX50_PAD_DISP_RS__ELCDIF_VSYNC IOMUX_PAD(0x434, 0x154, 2, 0x73c, 1, MX50_ELCDIF_PAD_CTRL) 508#define MX50_PAD_DISP_RS__ELCDIF_VSYNC IOMUX_PAD(0x434, 0x154, 2, 0x73c, 1, MX50_ELCDIF_PAD_CTRL)
509#define MX50_PAD_DISP_RS__WEIM_A26 IOMUX_PAD(0x434, 0x154, 3, 0x0, 0, NO_PAD_CTRL) 509#define MX50_PAD_DISP_RS__WEIM_A26 IOMUX_PAD(0x434, 0x154, 3, 0x0, 0, NO_PAD_CTRL)
@@ -691,8 +691,8 @@
691 691
692#define MX50_PAD_EPDC_D9__EPDC_D9 IOMUX_PAD(0x570, 0x1D4, 0, 0x0, 0, NO_PAD_CTRL) 692#define MX50_PAD_EPDC_D9__EPDC_D9 IOMUX_PAD(0x570, 0x1D4, 0, 0x0, 0, NO_PAD_CTRL)
693#define MX50_PAD_EPDC_D9__GPIO_3_9 IOMUX_PAD(0x570, 0x1D4, 1, 0x0, 0, NO_PAD_CTRL) 693#define MX50_PAD_EPDC_D9__GPIO_3_9 IOMUX_PAD(0x570, 0x1D4, 1, 0x0, 0, NO_PAD_CTRL)
694#define MX50_PAD_EPDC_D9__WEIM_D9 IOMUX_PAD(0x570, 0x1D4, 2, 0x0, 0, NO_PAD_CTRL) 694#define MX50_PAD_EPDC_D9__WEIM_D9 IOMUX_PAD(0x570, 0x1D4, 2, 0x810, 2, NO_PAD_CTRL)
695#define MX50_PAD_EPDC_D9__ELCDIF_D25 IOMUX_PAD(0x570, 0x1D4, 3, 0x810, 2, MX50_ELCDIF_PAD_CTRL) 695#define MX50_PAD_EPDC_D9__ELCDIF_D25 IOMUX_PAD(0x570, 0x1D4, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
696 696
697#define MX50_PAD_EPDC_D10__EPDC_D10 IOMUX_PAD(0x574, 0x1D8, 0, 0x0, 0, NO_PAD_CTRL) 697#define MX50_PAD_EPDC_D10__EPDC_D10 IOMUX_PAD(0x574, 0x1D8, 0, 0x0, 0, NO_PAD_CTRL)
698#define MX50_PAD_EPDC_D10__GPIO_3_10 IOMUX_PAD(0x574, 0x1D8, 1, 0x0, 0, NO_PAD_CTRL) 698#define MX50_PAD_EPDC_D10__GPIO_3_10 IOMUX_PAD(0x574, 0x1D8, 1, 0x0, 0, NO_PAD_CTRL)
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
index b6767f90ef14..df6acc066fb1 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx51.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
@@ -473,7 +473,7 @@
473#define _MX51_PAD_UART2_RXD__UART2_RXD IOMUX_PAD(0x628, 0x238, 0, 0x09ec, 2, 0) 473#define _MX51_PAD_UART2_RXD__UART2_RXD IOMUX_PAD(0x628, 0x238, 0, 0x09ec, 2, 0)
474#define _MX51_PAD_UART2_TXD__FIRI_RXD IOMUX_PAD(0x62c, 0x23c, 1, 0x0000, 0, 0) 474#define _MX51_PAD_UART2_TXD__FIRI_RXD IOMUX_PAD(0x62c, 0x23c, 1, 0x0000, 0, 0)
475#define _MX51_PAD_UART2_TXD__GPIO1_21 IOMUX_PAD(0x62c, 0x23c, 3, 0x0000, 0, 0) 475#define _MX51_PAD_UART2_TXD__GPIO1_21 IOMUX_PAD(0x62c, 0x23c, 3, 0x0000, 0, 0)
476#define _MX51_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x62c, 0x23c, 0, 0x09ec, 3, 0) 476#define _MX51_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x62c, 0x23c, 0, 0x0000, 0, 0)
477#define _MX51_PAD_UART3_RXD__CSI1_D0 IOMUX_PAD(0x630, 0x240, 2, 0x0000, 0, 0) 477#define _MX51_PAD_UART3_RXD__CSI1_D0 IOMUX_PAD(0x630, 0x240, 2, 0x0000, 0, 0)
478#define _MX51_PAD_UART3_RXD__GPIO1_22 IOMUX_PAD(0x630, 0x240, 3, 0x0000, 0, 0) 478#define _MX51_PAD_UART3_RXD__GPIO1_22 IOMUX_PAD(0x630, 0x240, 3, 0x0000, 0, 0)
479#define _MX51_PAD_UART3_RXD__UART1_DTR IOMUX_PAD(0x630, 0x240, 0, 0x0000, 0, 0) 479#define _MX51_PAD_UART3_RXD__UART1_DTR IOMUX_PAD(0x630, 0x240, 0, 0x0000, 0, 0)
@@ -528,7 +528,7 @@
528#define _MX51_PAD_USBH1_DATA1__UART2_RXD IOMUX_PAD(0x68c, 0x28c, 1, 0x09ec, 4, 0) 528#define _MX51_PAD_USBH1_DATA1__UART2_RXD IOMUX_PAD(0x68c, 0x28c, 1, 0x09ec, 4, 0)
529#define _MX51_PAD_USBH1_DATA1__USBH1_DATA1 IOMUX_PAD(0x68c, 0x28c, 0, 0x0000, 0, 0) 529#define _MX51_PAD_USBH1_DATA1__USBH1_DATA1 IOMUX_PAD(0x68c, 0x28c, 0, 0x0000, 0, 0)
530#define _MX51_PAD_USBH1_DATA2__GPIO1_13 IOMUX_PAD(0x690, 0x290, 2, 0x0000, 0, 0) 530#define _MX51_PAD_USBH1_DATA2__GPIO1_13 IOMUX_PAD(0x690, 0x290, 2, 0x0000, 0, 0)
531#define _MX51_PAD_USBH1_DATA2__UART2_TXD IOMUX_PAD(0x690, 0x290, 1, 0x09ec, 5, 0) 531#define _MX51_PAD_USBH1_DATA2__UART2_TXD IOMUX_PAD(0x690, 0x290, 1, 0x0000, 0, 0)
532#define _MX51_PAD_USBH1_DATA2__USBH1_DATA2 IOMUX_PAD(0x690, 0x290, 0, 0x0000, 0, 0) 532#define _MX51_PAD_USBH1_DATA2__USBH1_DATA2 IOMUX_PAD(0x690, 0x290, 0, 0x0000, 0, 0)
533#define _MX51_PAD_USBH1_DATA3__GPIO1_14 IOMUX_PAD(0x694, 0x294, 2, 0x0000, 0, 0) 533#define _MX51_PAD_USBH1_DATA3__GPIO1_14 IOMUX_PAD(0x694, 0x294, 2, 0x0000, 0, 0)
534#define _MX51_PAD_USBH1_DATA3__UART2_RTS IOMUX_PAD(0x694, 0x294, 1, 0x09e8, 5, 0) 534#define _MX51_PAD_USBH1_DATA3__UART2_RTS IOMUX_PAD(0x694, 0x294, 1, 0x09e8, 5, 0)
@@ -985,11 +985,11 @@
985#define MX51_PAD_NANDF_WE_B__GPIO3_3 (_MX51_PAD_NANDF_WE_B__GPIO3_3 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) 985#define MX51_PAD_NANDF_WE_B__GPIO3_3 (_MX51_PAD_NANDF_WE_B__GPIO3_3 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
986#define MX51_PAD_NANDF_WE_B__NANDF_WE_B (_MX51_PAD_NANDF_WE_B__NANDF_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL)) 986#define MX51_PAD_NANDF_WE_B__NANDF_WE_B (_MX51_PAD_NANDF_WE_B__NANDF_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL))
987#define MX51_PAD_NANDF_WE_B__PATA_DIOW (_MX51_PAD_NANDF_WE_B__PATA_DIOW | MUX_PAD_CTRL(NO_PAD_CTRL)) 987#define MX51_PAD_NANDF_WE_B__PATA_DIOW (_MX51_PAD_NANDF_WE_B__PATA_DIOW | MUX_PAD_CTRL(NO_PAD_CTRL))
988#define MX51_PAD_NANDF_WE_B__SD3_DATA0 (_MX51_PAD_NANDF_WE_B__SD3_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL)) 988#define MX51_PAD_NANDF_WE_B__SD3_DATA0 (_MX51_PAD_NANDF_WE_B__SD3_DATA0 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
989#define MX51_PAD_NANDF_RE_B__GPIO3_4 (_MX51_PAD_NANDF_RE_B__GPIO3_4 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) 989#define MX51_PAD_NANDF_RE_B__GPIO3_4 (_MX51_PAD_NANDF_RE_B__GPIO3_4 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
990#define MX51_PAD_NANDF_RE_B__NANDF_RE_B (_MX51_PAD_NANDF_RE_B__NANDF_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL)) 990#define MX51_PAD_NANDF_RE_B__NANDF_RE_B (_MX51_PAD_NANDF_RE_B__NANDF_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL))
991#define MX51_PAD_NANDF_RE_B__PATA_DIOR (_MX51_PAD_NANDF_RE_B__PATA_DIOR | MUX_PAD_CTRL(NO_PAD_CTRL)) 991#define MX51_PAD_NANDF_RE_B__PATA_DIOR (_MX51_PAD_NANDF_RE_B__PATA_DIOR | MUX_PAD_CTRL(NO_PAD_CTRL))
992#define MX51_PAD_NANDF_RE_B__SD3_DATA1 (_MX51_PAD_NANDF_RE_B__SD3_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) 992#define MX51_PAD_NANDF_RE_B__SD3_DATA1 (_MX51_PAD_NANDF_RE_B__SD3_DATA1 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
993#define MX51_PAD_NANDF_ALE__GPIO3_5 (_MX51_PAD_NANDF_ALE__GPIO3_5 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) 993#define MX51_PAD_NANDF_ALE__GPIO3_5 (_MX51_PAD_NANDF_ALE__GPIO3_5 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
994#define MX51_PAD_NANDF_ALE__NANDF_ALE (_MX51_PAD_NANDF_ALE__NANDF_ALE | MUX_PAD_CTRL(NO_PAD_CTRL)) 994#define MX51_PAD_NANDF_ALE__NANDF_ALE (_MX51_PAD_NANDF_ALE__NANDF_ALE | MUX_PAD_CTRL(NO_PAD_CTRL))
995#define MX51_PAD_NANDF_ALE__PATA_BUFFER_EN (_MX51_PAD_NANDF_ALE__PATA_BUFFER_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) 995#define MX51_PAD_NANDF_ALE__PATA_BUFFER_EN (_MX51_PAD_NANDF_ALE__PATA_BUFFER_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
@@ -999,18 +999,18 @@
999#define MX51_PAD_NANDF_WP_B__GPIO3_7 (_MX51_PAD_NANDF_WP_B__GPIO3_7 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) 999#define MX51_PAD_NANDF_WP_B__GPIO3_7 (_MX51_PAD_NANDF_WP_B__GPIO3_7 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1000#define MX51_PAD_NANDF_WP_B__NANDF_WP_B (_MX51_PAD_NANDF_WP_B__NANDF_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL)) 1000#define MX51_PAD_NANDF_WP_B__NANDF_WP_B (_MX51_PAD_NANDF_WP_B__NANDF_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL))
1001#define MX51_PAD_NANDF_WP_B__PATA_DMACK (_MX51_PAD_NANDF_WP_B__PATA_DMACK | MUX_PAD_CTRL(NO_PAD_CTRL)) 1001#define MX51_PAD_NANDF_WP_B__PATA_DMACK (_MX51_PAD_NANDF_WP_B__PATA_DMACK | MUX_PAD_CTRL(NO_PAD_CTRL))
1002#define MX51_PAD_NANDF_WP_B__SD3_DATA2 (_MX51_PAD_NANDF_WP_B__SD3_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1002#define MX51_PAD_NANDF_WP_B__SD3_DATA2 (_MX51_PAD_NANDF_WP_B__SD3_DATA2 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
1003#define MX51_PAD_NANDF_RB0__ECSPI2_SS1 (_MX51_PAD_NANDF_RB0__ECSPI2_SS1 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) 1003#define MX51_PAD_NANDF_RB0__ECSPI2_SS1 (_MX51_PAD_NANDF_RB0__ECSPI2_SS1 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1004#define MX51_PAD_NANDF_RB0__GPIO3_8 (_MX51_PAD_NANDF_RB0__GPIO3_8 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) 1004#define MX51_PAD_NANDF_RB0__GPIO3_8 (_MX51_PAD_NANDF_RB0__GPIO3_8 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1005#define MX51_PAD_NANDF_RB0__NANDF_RB0 (_MX51_PAD_NANDF_RB0__NANDF_RB0 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1005#define MX51_PAD_NANDF_RB0__NANDF_RB0 (_MX51_PAD_NANDF_RB0__NANDF_RB0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1006#define MX51_PAD_NANDF_RB0__PATA_DMARQ (_MX51_PAD_NANDF_RB0__PATA_DMARQ | MUX_PAD_CTRL(NO_PAD_CTRL)) 1006#define MX51_PAD_NANDF_RB0__PATA_DMARQ (_MX51_PAD_NANDF_RB0__PATA_DMARQ | MUX_PAD_CTRL(NO_PAD_CTRL))
1007#define MX51_PAD_NANDF_RB0__SD3_DATA3 (_MX51_PAD_NANDF_RB0__SD3_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1007#define MX51_PAD_NANDF_RB0__SD3_DATA3 (_MX51_PAD_NANDF_RB0__SD3_DATA3 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
1008#define MX51_PAD_NANDF_RB1__CSPI_MOSI (_MX51_PAD_NANDF_RB1__CSPI_MOSI | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) 1008#define MX51_PAD_NANDF_RB1__CSPI_MOSI (_MX51_PAD_NANDF_RB1__CSPI_MOSI | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1009#define MX51_PAD_NANDF_RB1__ECSPI2_RDY (_MX51_PAD_NANDF_RB1__ECSPI2_RDY | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) 1009#define MX51_PAD_NANDF_RB1__ECSPI2_RDY (_MX51_PAD_NANDF_RB1__ECSPI2_RDY | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1010#define MX51_PAD_NANDF_RB1__GPIO3_9 (_MX51_PAD_NANDF_RB1__GPIO3_9 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) 1010#define MX51_PAD_NANDF_RB1__GPIO3_9 (_MX51_PAD_NANDF_RB1__GPIO3_9 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1011#define MX51_PAD_NANDF_RB1__NANDF_RB1 (_MX51_PAD_NANDF_RB1__NANDF_RB1 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1011#define MX51_PAD_NANDF_RB1__NANDF_RB1 (_MX51_PAD_NANDF_RB1__NANDF_RB1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1012#define MX51_PAD_NANDF_RB1__PATA_IORDY (_MX51_PAD_NANDF_RB1__PATA_IORDY | MUX_PAD_CTRL(NO_PAD_CTRL)) 1012#define MX51_PAD_NANDF_RB1__PATA_IORDY (_MX51_PAD_NANDF_RB1__PATA_IORDY | MUX_PAD_CTRL(NO_PAD_CTRL))
1013#define MX51_PAD_NANDF_RB1__SD4_CMD (_MX51_PAD_NANDF_RB1__SD4_CMD | MUX_PAD_CTRL(NO_PAD_CTRL)) 1013#define MX51_PAD_NANDF_RB1__SD4_CMD (_MX51_PAD_NANDF_RB1__SD4_CMD | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
1014#define MX51_PAD_NANDF_RB2__DISP2_WAIT (_MX51_PAD_NANDF_RB2__DISP2_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL)) 1014#define MX51_PAD_NANDF_RB2__DISP2_WAIT (_MX51_PAD_NANDF_RB2__DISP2_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL))
1015#define MX51_PAD_NANDF_RB2__ECSPI2_SCLK (_MX51_PAD_NANDF_RB2__ECSPI2_SCLK | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) 1015#define MX51_PAD_NANDF_RB2__ECSPI2_SCLK (_MX51_PAD_NANDF_RB2__ECSPI2_SCLK | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1016#define MX51_PAD_NANDF_RB2__FEC_COL (_MX51_PAD_NANDF_RB2__FEC_COL | MUX_PAD_CTRL(MX51_PAD_CTRL_2)) 1016#define MX51_PAD_NANDF_RB2__FEC_COL (_MX51_PAD_NANDF_RB2__FEC_COL | MUX_PAD_CTRL(MX51_PAD_CTRL_2))
@@ -1036,41 +1036,41 @@
1036#define MX51_PAD_NANDF_CS2__GPIO3_18 (_MX51_PAD_NANDF_CS2__GPIO3_18 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) 1036#define MX51_PAD_NANDF_CS2__GPIO3_18 (_MX51_PAD_NANDF_CS2__GPIO3_18 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1037#define MX51_PAD_NANDF_CS2__NANDF_CS2 (_MX51_PAD_NANDF_CS2__NANDF_CS2 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1037#define MX51_PAD_NANDF_CS2__NANDF_CS2 (_MX51_PAD_NANDF_CS2__NANDF_CS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1038#define MX51_PAD_NANDF_CS2__PATA_CS_0 (_MX51_PAD_NANDF_CS2__PATA_CS_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1038#define MX51_PAD_NANDF_CS2__PATA_CS_0 (_MX51_PAD_NANDF_CS2__PATA_CS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1039#define MX51_PAD_NANDF_CS2__SD4_CLK (_MX51_PAD_NANDF_CS2__SD4_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) 1039#define MX51_PAD_NANDF_CS2__SD4_CLK (_MX51_PAD_NANDF_CS2__SD4_CLK | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS))
1040#define MX51_PAD_NANDF_CS2__USBH3_H1_DP (_MX51_PAD_NANDF_CS2__USBH3_H1_DP | MUX_PAD_CTRL(NO_PAD_CTRL)) 1040#define MX51_PAD_NANDF_CS2__USBH3_H1_DP (_MX51_PAD_NANDF_CS2__USBH3_H1_DP | MUX_PAD_CTRL(NO_PAD_CTRL))
1041#define MX51_PAD_NANDF_CS3__FEC_MDC (_MX51_PAD_NANDF_CS3__FEC_MDC | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) 1041#define MX51_PAD_NANDF_CS3__FEC_MDC (_MX51_PAD_NANDF_CS3__FEC_MDC | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
1042#define MX51_PAD_NANDF_CS3__GPIO3_19 (_MX51_PAD_NANDF_CS3__GPIO3_19 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) 1042#define MX51_PAD_NANDF_CS3__GPIO3_19 (_MX51_PAD_NANDF_CS3__GPIO3_19 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1043#define MX51_PAD_NANDF_CS3__NANDF_CS3 (_MX51_PAD_NANDF_CS3__NANDF_CS3 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1043#define MX51_PAD_NANDF_CS3__NANDF_CS3 (_MX51_PAD_NANDF_CS3__NANDF_CS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1044#define MX51_PAD_NANDF_CS3__PATA_CS_1 (_MX51_PAD_NANDF_CS3__PATA_CS_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1044#define MX51_PAD_NANDF_CS3__PATA_CS_1 (_MX51_PAD_NANDF_CS3__PATA_CS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1045#define MX51_PAD_NANDF_CS3__SD4_DAT0 (_MX51_PAD_NANDF_CS3__SD4_DAT0 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1045#define MX51_PAD_NANDF_CS3__SD4_DAT0 (_MX51_PAD_NANDF_CS3__SD4_DAT0 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
1046#define MX51_PAD_NANDF_CS3__USBH3_H1_DM (_MX51_PAD_NANDF_CS3__USBH3_H1_DM | MUX_PAD_CTRL(NO_PAD_CTRL)) 1046#define MX51_PAD_NANDF_CS3__USBH3_H1_DM (_MX51_PAD_NANDF_CS3__USBH3_H1_DM | MUX_PAD_CTRL(NO_PAD_CTRL))
1047#define MX51_PAD_NANDF_CS4__FEC_TDATA1 (_MX51_PAD_NANDF_CS4__FEC_TDATA1 | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) 1047#define MX51_PAD_NANDF_CS4__FEC_TDATA1 (_MX51_PAD_NANDF_CS4__FEC_TDATA1 | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
1048#define MX51_PAD_NANDF_CS4__GPIO3_20 (_MX51_PAD_NANDF_CS4__GPIO3_20 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) 1048#define MX51_PAD_NANDF_CS4__GPIO3_20 (_MX51_PAD_NANDF_CS4__GPIO3_20 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1049#define MX51_PAD_NANDF_CS4__NANDF_CS4 (_MX51_PAD_NANDF_CS4__NANDF_CS4 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1049#define MX51_PAD_NANDF_CS4__NANDF_CS4 (_MX51_PAD_NANDF_CS4__NANDF_CS4 | MUX_PAD_CTRL(NO_PAD_CTRL))
1050#define MX51_PAD_NANDF_CS4__PATA_DA_0 (_MX51_PAD_NANDF_CS4__PATA_DA_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1050#define MX51_PAD_NANDF_CS4__PATA_DA_0 (_MX51_PAD_NANDF_CS4__PATA_DA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1051#define MX51_PAD_NANDF_CS4__SD4_DAT1 (_MX51_PAD_NANDF_CS4__SD4_DAT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1051#define MX51_PAD_NANDF_CS4__SD4_DAT1 (_MX51_PAD_NANDF_CS4__SD4_DAT1 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
1052#define MX51_PAD_NANDF_CS4__USBH3_STP (_MX51_PAD_NANDF_CS4__USBH3_STP | MUX_PAD_CTRL(NO_PAD_CTRL)) 1052#define MX51_PAD_NANDF_CS4__USBH3_STP (_MX51_PAD_NANDF_CS4__USBH3_STP | MUX_PAD_CTRL(NO_PAD_CTRL))
1053#define MX51_PAD_NANDF_CS5__FEC_TDATA2 (_MX51_PAD_NANDF_CS5__FEC_TDATA2 | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) 1053#define MX51_PAD_NANDF_CS5__FEC_TDATA2 (_MX51_PAD_NANDF_CS5__FEC_TDATA2 | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
1054#define MX51_PAD_NANDF_CS5__GPIO3_21 (_MX51_PAD_NANDF_CS5__GPIO3_21 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) 1054#define MX51_PAD_NANDF_CS5__GPIO3_21 (_MX51_PAD_NANDF_CS5__GPIO3_21 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1055#define MX51_PAD_NANDF_CS5__NANDF_CS5 (_MX51_PAD_NANDF_CS5__NANDF_CS5 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1055#define MX51_PAD_NANDF_CS5__NANDF_CS5 (_MX51_PAD_NANDF_CS5__NANDF_CS5 | MUX_PAD_CTRL(NO_PAD_CTRL))
1056#define MX51_PAD_NANDF_CS5__PATA_DA_1 (_MX51_PAD_NANDF_CS5__PATA_DA_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1056#define MX51_PAD_NANDF_CS5__PATA_DA_1 (_MX51_PAD_NANDF_CS5__PATA_DA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1057#define MX51_PAD_NANDF_CS5__SD4_DAT2 (_MX51_PAD_NANDF_CS5__SD4_DAT2 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1057#define MX51_PAD_NANDF_CS5__SD4_DAT2 (_MX51_PAD_NANDF_CS5__SD4_DAT2 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
1058#define MX51_PAD_NANDF_CS5__USBH3_DIR (_MX51_PAD_NANDF_CS5__USBH3_DIR | MUX_PAD_CTRL(NO_PAD_CTRL)) 1058#define MX51_PAD_NANDF_CS5__USBH3_DIR (_MX51_PAD_NANDF_CS5__USBH3_DIR | MUX_PAD_CTRL(NO_PAD_CTRL))
1059#define MX51_PAD_NANDF_CS6__CSPI_SS3 (_MX51_PAD_NANDF_CS6__CSPI_SS3 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) 1059#define MX51_PAD_NANDF_CS6__CSPI_SS3 (_MX51_PAD_NANDF_CS6__CSPI_SS3 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1060#define MX51_PAD_NANDF_CS6__FEC_TDATA3 (_MX51_PAD_NANDF_CS6__FEC_TDATA3 | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) 1060#define MX51_PAD_NANDF_CS6__FEC_TDATA3 (_MX51_PAD_NANDF_CS6__FEC_TDATA3 | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
1061#define MX51_PAD_NANDF_CS6__GPIO3_22 (_MX51_PAD_NANDF_CS6__GPIO3_22 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) 1061#define MX51_PAD_NANDF_CS6__GPIO3_22 (_MX51_PAD_NANDF_CS6__GPIO3_22 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1062#define MX51_PAD_NANDF_CS6__NANDF_CS6 (_MX51_PAD_NANDF_CS6__NANDF_CS6 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1062#define MX51_PAD_NANDF_CS6__NANDF_CS6 (_MX51_PAD_NANDF_CS6__NANDF_CS6 | MUX_PAD_CTRL(NO_PAD_CTRL))
1063#define MX51_PAD_NANDF_CS6__PATA_DA_2 (_MX51_PAD_NANDF_CS6__PATA_DA_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1063#define MX51_PAD_NANDF_CS6__PATA_DA_2 (_MX51_PAD_NANDF_CS6__PATA_DA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1064#define MX51_PAD_NANDF_CS6__SD4_DAT3 (_MX51_PAD_NANDF_CS6__SD4_DAT3 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1064#define MX51_PAD_NANDF_CS6__SD4_DAT3 (_MX51_PAD_NANDF_CS6__SD4_DAT3 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
1065#define MX51_PAD_NANDF_CS7__FEC_TX_EN (_MX51_PAD_NANDF_CS7__FEC_TX_EN | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) 1065#define MX51_PAD_NANDF_CS7__FEC_TX_EN (_MX51_PAD_NANDF_CS7__FEC_TX_EN | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
1066#define MX51_PAD_NANDF_CS7__GPIO3_23 (_MX51_PAD_NANDF_CS7__GPIO3_23 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) 1066#define MX51_PAD_NANDF_CS7__GPIO3_23 (_MX51_PAD_NANDF_CS7__GPIO3_23 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1067#define MX51_PAD_NANDF_CS7__NANDF_CS7 (_MX51_PAD_NANDF_CS7__NANDF_CS7 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1067#define MX51_PAD_NANDF_CS7__NANDF_CS7 (_MX51_PAD_NANDF_CS7__NANDF_CS7 | MUX_PAD_CTRL(NO_PAD_CTRL))
1068#define MX51_PAD_NANDF_CS7__SD3_CLK (_MX51_PAD_NANDF_CS7__SD3_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) 1068#define MX51_PAD_NANDF_CS7__SD3_CLK (_MX51_PAD_NANDF_CS7__SD3_CLK | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS))
1069#define MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0 (_MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) 1069#define MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0 (_MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1070#define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK (_MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK | MUX_PAD_CTRL(MX51_PAD_CTRL_4)) 1070#define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK (_MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK | MUX_PAD_CTRL(MX51_PAD_CTRL_4))
1071#define MX51_PAD_NANDF_RDY_INT__GPIO3_24 (_MX51_PAD_NANDF_RDY_INT__GPIO3_24 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) 1071#define MX51_PAD_NANDF_RDY_INT__GPIO3_24 (_MX51_PAD_NANDF_RDY_INT__GPIO3_24 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1072#define MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT (_MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT | MUX_PAD_CTRL(NO_PAD_CTRL)) 1072#define MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT (_MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT | MUX_PAD_CTRL(NO_PAD_CTRL))
1073#define MX51_PAD_NANDF_RDY_INT__SD3_CMD (_MX51_PAD_NANDF_RDY_INT__SD3_CMD | MUX_PAD_CTRL(NO_PAD_CTRL)) 1073#define MX51_PAD_NANDF_RDY_INT__SD3_CMD (_MX51_PAD_NANDF_RDY_INT__SD3_CMD | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
1074#define MX51_PAD_NANDF_D15__ECSPI2_MOSI (_MX51_PAD_NANDF_D15__ECSPI2_MOSI | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) 1074#define MX51_PAD_NANDF_D15__ECSPI2_MOSI (_MX51_PAD_NANDF_D15__ECSPI2_MOSI | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1075#define MX51_PAD_NANDF_D15__GPIO3_25 (_MX51_PAD_NANDF_D15__GPIO3_25 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) 1075#define MX51_PAD_NANDF_D15__GPIO3_25 (_MX51_PAD_NANDF_D15__GPIO3_25 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1076#define MX51_PAD_NANDF_D15__NANDF_D15 (_MX51_PAD_NANDF_D15__NANDF_D15 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1076#define MX51_PAD_NANDF_D15__NANDF_D15 (_MX51_PAD_NANDF_D15__NANDF_D15 | MUX_PAD_CTRL(NO_PAD_CTRL))
@@ -1479,26 +1479,26 @@
1479#define MX51_PAD_SD1_CLK__SD1_CLK (_MX51_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)) 1479#define MX51_PAD_SD1_CLK__SD1_CLK (_MX51_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS))
1480#define MX51_PAD_SD1_DATA0__AUD5_TXD (_MX51_PAD_SD1_DATA0__AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) 1480#define MX51_PAD_SD1_DATA0__AUD5_TXD (_MX51_PAD_SD1_DATA0__AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
1481#define MX51_PAD_SD1_DATA0__CSPI_MISO (_MX51_PAD_SD1_DATA0__CSPI_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) 1481#define MX51_PAD_SD1_DATA0__CSPI_MISO (_MX51_PAD_SD1_DATA0__CSPI_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1482#define MX51_PAD_SD1_DATA0__SD1_DATA0 (_MX51_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1482#define MX51_PAD_SD1_DATA0__SD1_DATA0 (_MX51_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
1483#define MX51_PAD_EIM_DA0__EIM_DA0 (_MX51_PAD_EIM_DA0__EIM_DA0 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1483#define MX51_PAD_EIM_DA0__EIM_DA0 (_MX51_PAD_EIM_DA0__EIM_DA0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1484#define MX51_PAD_EIM_DA1__EIM_DA1 (_MX51_PAD_EIM_DA1__EIM_DA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1484#define MX51_PAD_EIM_DA1__EIM_DA1 (_MX51_PAD_EIM_DA1__EIM_DA1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1485#define MX51_PAD_EIM_DA2__EIM_DA2 (_MX51_PAD_EIM_DA2__EIM_DA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1485#define MX51_PAD_EIM_DA2__EIM_DA2 (_MX51_PAD_EIM_DA2__EIM_DA2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1486#define MX51_PAD_EIM_DA3__EIM_DA3 (_MX51_PAD_EIM_DA3__EIM_DA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1486#define MX51_PAD_EIM_DA3__EIM_DA3 (_MX51_PAD_EIM_DA3__EIM_DA3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1487#define MX51_PAD_SD1_DATA1__AUD5_RXD (_MX51_PAD_SD1_DATA1__AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) 1487#define MX51_PAD_SD1_DATA1__AUD5_RXD (_MX51_PAD_SD1_DATA1__AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
1488#define MX51_PAD_SD1_DATA1__SD1_DATA1 (_MX51_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1488#define MX51_PAD_SD1_DATA1__SD1_DATA1 (_MX51_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
1489#define MX51_PAD_EIM_DA4__EIM_DA4 (_MX51_PAD_EIM_DA4__EIM_DA4 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1489#define MX51_PAD_EIM_DA4__EIM_DA4 (_MX51_PAD_EIM_DA4__EIM_DA4 | MUX_PAD_CTRL(NO_PAD_CTRL))
1490#define MX51_PAD_EIM_DA5__EIM_DA5 (_MX51_PAD_EIM_DA5__EIM_DA5 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1490#define MX51_PAD_EIM_DA5__EIM_DA5 (_MX51_PAD_EIM_DA5__EIM_DA5 | MUX_PAD_CTRL(NO_PAD_CTRL))
1491#define MX51_PAD_EIM_DA6__EIM_DA6 (_MX51_PAD_EIM_DA6__EIM_DA6 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1491#define MX51_PAD_EIM_DA6__EIM_DA6 (_MX51_PAD_EIM_DA6__EIM_DA6 | MUX_PAD_CTRL(NO_PAD_CTRL))
1492#define MX51_PAD_EIM_DA7__EIM_DA7 (_MX51_PAD_EIM_DA7__EIM_DA7 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1492#define MX51_PAD_EIM_DA7__EIM_DA7 (_MX51_PAD_EIM_DA7__EIM_DA7 | MUX_PAD_CTRL(NO_PAD_CTRL))
1493#define MX51_PAD_SD1_DATA2__AUD5_TXC (_MX51_PAD_SD1_DATA2__AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) 1493#define MX51_PAD_SD1_DATA2__AUD5_TXC (_MX51_PAD_SD1_DATA2__AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
1494#define MX51_PAD_SD1_DATA2__SD1_DATA2 (_MX51_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1494#define MX51_PAD_SD1_DATA2__SD1_DATA2 (_MX51_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
1495#define MX51_PAD_EIM_DA10__EIM_DA10 (_MX51_PAD_EIM_DA10__EIM_DA10 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1495#define MX51_PAD_EIM_DA10__EIM_DA10 (_MX51_PAD_EIM_DA10__EIM_DA10 | MUX_PAD_CTRL(NO_PAD_CTRL))
1496#define MX51_PAD_EIM_DA11__EIM_DA11 (_MX51_PAD_EIM_DA11__EIM_DA11 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1496#define MX51_PAD_EIM_DA11__EIM_DA11 (_MX51_PAD_EIM_DA11__EIM_DA11 | MUX_PAD_CTRL(NO_PAD_CTRL))
1497#define MX51_PAD_EIM_DA8__EIM_DA8 (_MX51_PAD_EIM_DA8__EIM_DA8 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1497#define MX51_PAD_EIM_DA8__EIM_DA8 (_MX51_PAD_EIM_DA8__EIM_DA8 | MUX_PAD_CTRL(NO_PAD_CTRL))
1498#define MX51_PAD_EIM_DA9__EIM_DA9 (_MX51_PAD_EIM_DA9__EIM_DA9 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1498#define MX51_PAD_EIM_DA9__EIM_DA9 (_MX51_PAD_EIM_DA9__EIM_DA9 | MUX_PAD_CTRL(NO_PAD_CTRL))
1499#define MX51_PAD_SD1_DATA3__AUD5_TXFS (_MX51_PAD_SD1_DATA3__AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) 1499#define MX51_PAD_SD1_DATA3__AUD5_TXFS (_MX51_PAD_SD1_DATA3__AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
1500#define MX51_PAD_SD1_DATA3__CSPI_SS1 (_MX51_PAD_SD1_DATA3__CSPI_SS1 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) 1500#define MX51_PAD_SD1_DATA3__CSPI_SS1 (_MX51_PAD_SD1_DATA3__CSPI_SS1 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1501#define MX51_PAD_SD1_DATA3__SD1_DATA3 (_MX51_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1501#define MX51_PAD_SD1_DATA3__SD1_DATA3 (_MX51_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
1502#define MX51_PAD_GPIO1_0__CSPI_SS2 (_MX51_PAD_GPIO1_0__CSPI_SS2 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) 1502#define MX51_PAD_GPIO1_0__CSPI_SS2 (_MX51_PAD_GPIO1_0__CSPI_SS2 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1503#define MX51_PAD_GPIO1_0__GPIO1_0 (_MX51_PAD_GPIO1_0__GPIO1_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1503#define MX51_PAD_GPIO1_0__GPIO1_0 (_MX51_PAD_GPIO1_0__GPIO1_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1504#define MX51_PAD_GPIO1_0__SD1_CD (_MX51_PAD_GPIO1_0__SD1_CD | MUX_PAD_CTRL(MX51_ESDHC_PAD_CTRL)) 1504#define MX51_PAD_GPIO1_0__SD1_CD (_MX51_PAD_GPIO1_0__SD1_CD | MUX_PAD_CTRL(MX51_ESDHC_PAD_CTRL))
@@ -1517,16 +1517,16 @@
1517#define MX51_PAD_SD2_CLK__SD2_CLK (_MX51_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)) 1517#define MX51_PAD_SD2_CLK__SD2_CLK (_MX51_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS))
1518#define MX51_PAD_SD2_DATA0__CSPI_MISO (_MX51_PAD_SD2_DATA0__CSPI_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) 1518#define MX51_PAD_SD2_DATA0__CSPI_MISO (_MX51_PAD_SD2_DATA0__CSPI_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1519#define MX51_PAD_SD2_DATA0__SD1_DAT4 (_MX51_PAD_SD2_DATA0__SD1_DAT4 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1519#define MX51_PAD_SD2_DATA0__SD1_DAT4 (_MX51_PAD_SD2_DATA0__SD1_DAT4 | MUX_PAD_CTRL(NO_PAD_CTRL))
1520#define MX51_PAD_SD2_DATA0__SD2_DATA0 (_MX51_PAD_SD2_DATA0__SD2_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1520#define MX51_PAD_SD2_DATA0__SD2_DATA0 (_MX51_PAD_SD2_DATA0__SD2_DATA0 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
1521#define MX51_PAD_SD2_DATA1__SD1_DAT5 (_MX51_PAD_SD2_DATA1__SD1_DAT5 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1521#define MX51_PAD_SD2_DATA1__SD1_DAT5 (_MX51_PAD_SD2_DATA1__SD1_DAT5 | MUX_PAD_CTRL(NO_PAD_CTRL))
1522#define MX51_PAD_SD2_DATA1__SD2_DATA1 (_MX51_PAD_SD2_DATA1__SD2_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1522#define MX51_PAD_SD2_DATA1__SD2_DATA1 (_MX51_PAD_SD2_DATA1__SD2_DATA1 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
1523#define MX51_PAD_SD2_DATA1__USBH3_H2_DP (_MX51_PAD_SD2_DATA1__USBH3_H2_DP | MUX_PAD_CTRL(NO_PAD_CTRL)) 1523#define MX51_PAD_SD2_DATA1__USBH3_H2_DP (_MX51_PAD_SD2_DATA1__USBH3_H2_DP | MUX_PAD_CTRL(NO_PAD_CTRL))
1524#define MX51_PAD_SD2_DATA2__SD1_DAT6 (_MX51_PAD_SD2_DATA2__SD1_DAT6 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1524#define MX51_PAD_SD2_DATA2__SD1_DAT6 (_MX51_PAD_SD2_DATA2__SD1_DAT6 | MUX_PAD_CTRL(NO_PAD_CTRL))
1525#define MX51_PAD_SD2_DATA2__SD2_DATA2 (_MX51_PAD_SD2_DATA2__SD2_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1525#define MX51_PAD_SD2_DATA2__SD2_DATA2 (_MX51_PAD_SD2_DATA2__SD2_DATA2 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
1526#define MX51_PAD_SD2_DATA2__USBH3_H2_DM (_MX51_PAD_SD2_DATA2__USBH3_H2_DM | MUX_PAD_CTRL(NO_PAD_CTRL)) 1526#define MX51_PAD_SD2_DATA2__USBH3_H2_DM (_MX51_PAD_SD2_DATA2__USBH3_H2_DM | MUX_PAD_CTRL(NO_PAD_CTRL))
1527#define MX51_PAD_SD2_DATA3__CSPI_SS2 (_MX51_PAD_SD2_DATA3__CSPI_SS2 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) 1527#define MX51_PAD_SD2_DATA3__CSPI_SS2 (_MX51_PAD_SD2_DATA3__CSPI_SS2 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1528#define MX51_PAD_SD2_DATA3__SD1_DAT7 (_MX51_PAD_SD2_DATA3__SD1_DAT7 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1528#define MX51_PAD_SD2_DATA3__SD1_DAT7 (_MX51_PAD_SD2_DATA3__SD1_DAT7 | MUX_PAD_CTRL(NO_PAD_CTRL))
1529#define MX51_PAD_SD2_DATA3__SD2_DATA3 (_MX51_PAD_SD2_DATA3__SD2_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1529#define MX51_PAD_SD2_DATA3__SD2_DATA3 (_MX51_PAD_SD2_DATA3__SD2_DATA3 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
1530#define MX51_PAD_GPIO1_2__CCM_OUT_2 (_MX51_PAD_GPIO1_2__CCM_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1530#define MX51_PAD_GPIO1_2__CCM_OUT_2 (_MX51_PAD_GPIO1_2__CCM_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1531#define MX51_PAD_GPIO1_2__GPIO1_2 (_MX51_PAD_GPIO1_2__GPIO1_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1531#define MX51_PAD_GPIO1_2__GPIO1_2 (_MX51_PAD_GPIO1_2__GPIO1_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1532#define MX51_PAD_GPIO1_2__I2C2_SCL (_MX51_PAD_GPIO1_2__I2C2_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) 1532#define MX51_PAD_GPIO1_2__I2C2_SCL (_MX51_PAD_GPIO1_2__I2C2_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx53.h b/arch/arm/plat-mxc/include/mach/iomux-mx53.h
index 68e11d7ab79d..e95d9cb8aeb7 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx53.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx53.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. 2 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify 4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by 5 * it under the terms of the GNU General Public License as published by
@@ -21,305 +21,2358 @@
21 21
22#include <mach/iomux-v3.h> 22#include <mach/iomux-v3.h>
23 23
24/*
25 * various IOMUX alternate output functions (1-7)
26 */
27typedef enum iomux_config {
28 IOMUX_CONFIG_ALT0,
29 IOMUX_CONFIG_ALT1,
30 IOMUX_CONFIG_ALT2,
31 IOMUX_CONFIG_ALT3,
32 IOMUX_CONFIG_ALT4,
33 IOMUX_CONFIG_ALT5,
34 IOMUX_CONFIG_ALT6,
35 IOMUX_CONFIG_ALT7,
36 IOMUX_CONFIG_GPIO, /* added to help user use GPIO mode */
37} iomux_pin_cfg_t;
38
39/* These 2 defines are for pins that may not have a mux register, but could 24/* These 2 defines are for pins that may not have a mux register, but could
40 * have a pad setting register, and vice-versa. */ 25 * have a pad setting register, and vice-versa. */
41#define NON_MUX_I 0x00
42#define NON_PAD_I 0x00 26#define NON_PAD_I 0x00
43 27
44#define MX53_UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 28#define MX53_UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
45 PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 29 PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
46/* UART1 */ 30#define MX53_SDHC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \
47#define MX53_PAD_CSI0_D10__UART1_TXD IOMUX_PAD(0x414, 0xE8, 2, 0x0, 0, MX53_UART_PAD_CTRL) 31 PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH | \
48#define MX53_PAD_CSI0_D11__UART1_RXD IOMUX_PAD(0x418, 0xEC, 2, 0x878, 1, MX53_UART_PAD_CTRL) 32 PAD_CTL_SRE_FAST)
49#define MX53_PAD_ATA_DIOW__UART1_TXD IOMUX_PAD(0x5F0, 0x270, 3, 0x0, 0, MX53_UART_PAD_CTRL)
50#define MX53_PAD_ATA_DMACK__UART1_RXD IOMUX_PAD(0x5F4, 0x274, 3, 0x880, 3, MX53_UART_PAD_CTRL)
51
52/* UART2 */
53#define MX53_PAD_ATA_BUFFER_EN__UART2_RXD IOMUX_PAD(0x5FC, 0x27C, 3, 0x880, 3, MX53_UART_PAD_CTRL)
54#define MX53_PAD_ATA_DMARQ__UART2_TXD IOMUX_PAD(0x5F8, 0x278, 3, 0x0, 0, MX53_UART_PAD_CTRL)
55#define MX53_PAD_ATA_DIOR__UART2_RTS IOMUX_PAD(0x604, 0x284, 3, 0x87C, 3, MX53_UART_PAD_CTRL)
56#define MX53_PAD_ATA_INTRQ__UART2_CTS IOMUX_PAD(0x600, 0x280, 3, 0x0, 0, MX53_UART_PAD_CTRL)
57 33
58/* UART3 */ 34#define _MX53_PAD_GPIO_19__KPP_COL_5 IOMUX_PAD(0x348, 0x20, 0, 0x840, 0, 0)
59#define MX53_PAD_ATA_CS_0__UART3_TXD IOMUX_PAD(0x61C, 0x29C, 4, 0x0, 0, MX53_UART_PAD_CTRL) 35#define _MX53_PAD_GPIO_19__GPIO4_5 IOMUX_PAD(0x348, 0x20, 1, 0x0, 0, 0)
60#define MX53_PAD_ATA_CS_1__UART3_RXD IOMUX_PAD(0x620, 0x2A0, 4, 0x888, 3, MX53_UART_PAD_CTRL) 36#define _MX53_PAD_GPIO_19__CCM_CLKO IOMUX_PAD(0x348, 0x20, 2, 0x0, 0, 0)
61#define MX53_PAD_ATA_DA_1__UART3_CTS IOMUX_PAD(0x614, 0x294, 4, 0x0, 0, MX53_UART_PAD_CTRL) 37#define _MX53_PAD_GPIO_19__SPDIF_OUT1 IOMUX_PAD(0x348, 0x20, 3, 0x0, 0, 0)
62#define MX53_PAD_ATA_DA_2__UART3_RTS IOMUX_PAD(0x618, 0x298, 4, 0x884, 5, MX53_UART_PAD_CTRL) 38#define _MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 IOMUX_PAD(0x348, 0x20, 4, 0x0, 0, 0)
39#define _MX53_PAD_GPIO_19__ECSPI1_RDY IOMUX_PAD(0x348, 0x20, 5, 0x0, 0, 0)
40#define _MX53_PAD_GPIO_19__FEC_TDATA_3 IOMUX_PAD(0x348, 0x20, 6, 0x0, 0, 0)
41#define _MX53_PAD_GPIO_19__SRC_INT_BOOT IOMUX_PAD(0x348, 0x20,7, 0x0, 0, 0)
42#define _MX53_PAD_KEY_COL0__KPP_COL_0 IOMUX_PAD(0x34C, 0x24, o, 0x0, 0, 0)
43#define _MX53_PAD_KEY_COL0__GPIO4_6 IOMUX_PAD(0x34C, 0x24, 1, 0x0, 0, 0)
44#define _MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC IOMUX_PAD(0x34C, 0x24, 2, 0x758, 0, 0)
45#define _MX53_PAD_KEY_COL0__UART4_TXD_MUX IOMUX_PAD(0x34C, 0x24, 4, 0x890, 0, 0)
46#define _MX53_PAD_KEY_COL0__ECSPI1_SCLK IOMUX_PAD(0x34C, 0x24, 5, 0x79C, 0, 0)
47#define _MX53_PAD_KEY_COL0__FEC_RDATA_3 IOMUX_PAD(0x34C, 0x24, 6, 0x0, 0, 0)
48#define _MX53_PAD_KEY_COL0__SRC_ANY_PU_RST IOMUX_PAD(0x34C, 0x24, 7, 0x0, 0, 0)
49#define _MX53_PAD_KEY_ROW0__KPP_ROW_0 IOMUX_PAD(0x350, 0x28, 0, 0x0, 0, 0)
50#define _MX53_PAD_KEY_ROW0__GPIO4_7 IOMUX_PAD(0x350, 0x28, 1, 0x0, 0, 0)
51#define _MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD IOMUX_PAD(0x350, 0x28, 2, 0x74C, 0, 0)
52#define _MX53_PAD_KEY_ROW0__UART4_RXD_MUX IOMUX_PAD(0x350, 0x28, 4, 0x890, 1, 0)
53#define _MX53_PAD_KEY_ROW0__ECSPI1_MOSI IOMUX_PAD(0x350, 0x28, 5, 0x7A4, 0, 0)
54#define _MX53_PAD_KEY_ROW0__FEC_TX_ER IOMUX_PAD(0x350, 0x28, 6, 0x0, 0, 0)
55#define _MX53_PAD_KEY_COL1__KPP_COL_1 IOMUX_PAD(0x354, 0x2C, 0, 0x0, 0, 0)
56#define _MX53_PAD_KEY_COL1__GPIO4_8 IOMUX_PAD(0x354, 0x2C, 1, 0x0, 0, 0)
57#define _MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS IOMUX_PAD(0x354, 0x2C, 2, 0x75C, 0, 0)
58#define _MX53_PAD_KEY_COL1__UART5_TXD_MUX IOMUX_PAD(0x354, 0x2C, 4, 0x898, 0, 0)
59#define _MX53_PAD_KEY_COL1__ECSPI1_MISO IOMUX_PAD(0x354, 0x2C, 5, 0x7A0, 0, 0)
60#define _MX53_PAD_KEY_COL1__FEC_RX_CLK IOMUX_PAD(0x354, 0x2C, 6, 0x808, 0, 0)
61#define _MX53_PAD_KEY_COL1__USBPHY1_TXREADY IOMUX_PAD(0x354, 0x2C, 7, 0x0, 0, 0)
62#define _MX53_PAD_KEY_ROW1__KPP_ROW_1 IOMUX_PAD(0x358, 0x30, 0, 0x0, 0, 0)
63#define _MX53_PAD_KEY_ROW1__GPIO4_9 IOMUX_PAD(0x358, 0x30, 1, 0x0, 0, 0)
64#define _MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD IOMUX_PAD(0x358, 0x30, 2, 0x748, 0, 0)
65#define _MX53_PAD_KEY_ROW1__UART5_RXD_MUX IOMUX_PAD(0x358, 0x30, 4, 0x898, 1, 0)
66#define _MX53_PAD_KEY_ROW1__ECSPI1_SS0 IOMUX_PAD(0x358, 0x30, 5, 0x7A8, 0, 0)
67#define _MX53_PAD_KEY_ROW1__FEC_COL IOMUX_PAD(0x358, 0x30, 6, 0x800, 0, 0)
68#define _MX53_PAD_KEY_ROW1__USBPHY1_RXVALID IOMUX_PAD(0x358, 0x30, 7, 0x0, 0, 0)
69#define _MX53_PAD_KEY_COL2__KPP_COL_2 IOMUX_PAD(0x35C, 0x34, 0, 0x0, 0, 0)
70#define _MX53_PAD_KEY_COL2__GPIO4_10 IOMUX_PAD(0x35C, 0x34, 1, 0x0, 0, 0)
71#define _MX53_PAD_KEY_COL2__CAN1_TXCAN IOMUX_PAD(0x35C, 0x34, 2, 0x0, 0, 0)
72#define _MX53_PAD_KEY_COL2__FEC_MDIO IOMUX_PAD(0x35C, 0x34, 4, 0x804, 0, 0)
73#define _MX53_PAD_KEY_COL2__ECSPI1_SS1 IOMUX_PAD(0x35C, 0x34, 5, 0x7AC, 0, 0)
74#define _MX53_PAD_KEY_COL2__FEC_RDATA_2 IOMUX_PAD(0x35C, 0x34, 6, 0x0, 0, 0)
75#define _MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE IOMUX_PAD(0x35C, 0x34, 7, 0x0, 0, 0)
76#define _MX53_PAD_KEY_ROW2__KPP_ROW_2 IOMUX_PAD(0x360, 0x38, 0, 0x0, 0, 0)
77#define _MX53_PAD_KEY_ROW2__GPIO4_11 IOMUX_PAD(0x360, 0x38, 1, 0x0, 0, 0)
78#define _MX53_PAD_KEY_ROW2__CAN1_RXCAN IOMUX_PAD(0x360, 0x38, 2, 0x760, 0, 0)
79#define _MX53_PAD_KEY_ROW2__FEC_MDC IOMUX_PAD(0x360, 0x38, 4, 0x0, 0, 0)
80#define _MX53_PAD_KEY_ROW2__ECSPI1_SS2 IOMUX_PAD(0x360, 0x38, 5, 0x7B0, 0, 0)
81#define _MX53_PAD_KEY_ROW2__FEC_TDATA_2 IOMUX_PAD(0x360, 0x38, 6, 0x0, 0, 0)
82#define _MX53_PAD_KEY_ROW2__USBPHY1_RXERROR IOMUX_PAD(0x360, 0x38, 7, 0x0, 0, 0)
83#define _MX53_PAD_KEY_COL3__KPP_COL_3 IOMUX_PAD(0x364, 0x3C, 0, 0x0, 0, 0)
84#define _MX53_PAD_KEY_COL3__GPIO4_12 IOMUX_PAD(0x364, 0x3C, 1, 0x0, 0, 0)
85#define _MX53_PAD_KEY_COL3__USBOH3_H2_DP IOMUX_PAD(0x364, 0x3C, 2, 0x0, 0, 0)
86#define _MX53_PAD_KEY_COL3__SPDIF_IN1 IOMUX_PAD(0x364, 0x3C, 3, 0x870, 0, 0)
87#define _MX53_PAD_KEY_COL3__I2C2_SCL IOMUX_PAD(0x364, 0x3C, 4 | IOMUX_CONFIG_SION, 0x81C, 0, 0)
88#define _MX53_PAD_KEY_COL3__ECSPI1_SS3 IOMUX_PAD(0x364, 0x3C, 5, 0x7B4, 0, 0)
89#define _MX53_PAD_KEY_COL3__FEC_CRS IOMUX_PAD(0x364, 0x3C, 6, 0x0, 0, 0)
90#define _MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK IOMUX_PAD(0x364, 0x3C, 7, 0x0, 0, 0)
91#define _MX53_PAD_KEY_ROW3__KPP_ROW_3 IOMUX_PAD(0x368, 0x40, 0, 0x0, 0, 0)
92#define _MX53_PAD_KEY_ROW3__GPIO4_13 IOMUX_PAD(0x368, 0x40, 1, 0x0, 0, 0)
93#define _MX53_PAD_KEY_ROW3__USBOH3_H2_DM IOMUX_PAD(0x368, 0x40, 2, 0x0, 0, 0)
94#define _MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK IOMUX_PAD(0x368, 0x40, 3, 0x768, 0, 0)
95#define _MX53_PAD_KEY_ROW3__I2C2_SDA IOMUX_PAD(0x368, 0x40, 4 | IOMUX_CONFIG_SION, 0x820, 0, 0)
96#define _MX53_PAD_KEY_ROW3__OSC32K_32K_OUT IOMUX_PAD(0x368, 0x40, 5, 0x0, 0, 0)
97#define _MX53_PAD_KEY_ROW3__CCM_PLL4_BYP IOMUX_PAD(0x368, 0x40, 6, 0x77C, 0, 0)
98#define _MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0 IOMUX_PAD(0x368, 0x40, 7, 0x0, 0, 0)
99#define _MX53_PAD_KEY_COL4__KPP_COL_4 IOMUX_PAD(0x36C, 0x44, 0, 0x0, 0, 0)
100#define _MX53_PAD_KEY_COL4__GPIO4_14 IOMUX_PAD(0x36C, 0x44, 1, 0x0, 0, 0)
101#define _MX53_PAD_KEY_COL4__CAN2_TXCAN IOMUX_PAD(0x36C, 0x44, 2, 0x0, 0, 0)
102#define _MX53_PAD_KEY_COL4__IPU_SISG_4 IOMUX_PAD(0x36C, 0x44, 3, 0x0, 0, 0)
103#define _MX53_PAD_KEY_COL4__UART5_RTS IOMUX_PAD(0x36C, 0x44, 4, 0x894, 0, 0)
104#define _MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC IOMUX_PAD(0x36C, 0x44, 5, 0x89C, 0, 0)
105#define _MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1 IOMUX_PAD(0x36C, 0x44, 7, 0x0, 0, 0)
106#define _MX53_PAD_KEY_ROW4__KPP_ROW_4 IOMUX_PAD(0x370, 0x48, 0, 0x0, 0, 0)
107#define _MX53_PAD_KEY_ROW4__GPIO4_15 IOMUX_PAD(0x370, 0x48, 1, 0x0, 0, 0)
108#define _MX53_PAD_KEY_ROW4__CAN2_RXCAN IOMUX_PAD(0x370, 0x48, 2, 0x764, 0, 0)
109#define _MX53_PAD_KEY_ROW4__IPU_SISG_5 IOMUX_PAD(0x370, 0x48, 3, 0x0, 0, 0)
110#define _MX53_PAD_KEY_ROW4__UART5_CTS IOMUX_PAD(0x370, 0x48, 4, 0x894, 1, 0)
111#define _MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR IOMUX_PAD(0x370, 0x48, 5, 0x0, 0, 0)
112#define _MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID IOMUX_PAD(0x370, 0x48, 7, 0x0, 0, 0)
113#define _MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK IOMUX_PAD(0x378, 0x4C, 0, 0x0, 0, 0)
114#define _MX53_PAD_DI0_DISP_CLK__GPIO4_16 IOMUX_PAD(0x378, 0x4C, 1, 0x0, 0, 0)
115#define _MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR IOMUX_PAD(0x378, 0x4C, 2, 0x0, 0, 0)
116#define _MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 IOMUX_PAD(0x378, 0x4C, 5, 0x0, 0, 0)
117#define _MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0 IOMUX_PAD(0x378, 0x4C, 6, 0x0, 0, 0)
118#define _MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID IOMUX_PAD(0x378, 0x4C, 7, 0x0, 0, 0)
119#define _MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 IOMUX_PAD(0x37C, 0x50, 0, 0x0, 0, 0)
120#define _MX53_PAD_DI0_PIN15__GPIO4_17 IOMUX_PAD(0x37C, 0x50, 1, 0x0, 0, 0)
121#define _MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC IOMUX_PAD(0x37C, 0x50, 2, 0x0, 0, 0)
122#define _MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 IOMUX_PAD(0x37C, 0x50, 5, 0x0, 0, 0)
123#define _MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1 IOMUX_PAD(0x37C, 0x50, 6, 0x0, 0, 0)
124#define _MX53_PAD_DI0_PIN15__USBPHY1_BVALID IOMUX_PAD(0x37C, 0x50, 7, 0x0, 0, 0)
125#define _MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 IOMUX_PAD(0x380, 0x54, 0, 0x0, 0, 0)
126#define _MX53_PAD_DI0_PIN2__GPIO4_18 IOMUX_PAD(0x380, 0x54, 1, 0x0, 0, 0)
127#define _MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD IOMUX_PAD(0x380, 0x54, 2, 0x0, 0, 0)
128#define _MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 IOMUX_PAD(0x380, 0x54, 5, 0x0, 0, 0)
129#define _MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2 IOMUX_PAD(0x380, 0x54, 6, 0x0, 0, 0)
130#define _MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION IOMUX_PAD(0x380, 0x54, 7, 0x0, 0, 0)
131#define _MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 IOMUX_PAD(0x384, 0x58, 0, 0x0, 0, 0)
132#define _MX53_PAD_DI0_PIN3__GPIO4_19 IOMUX_PAD(0x384, 0x58, 1, 0x0, 0, 0)
133#define _MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS IOMUX_PAD(0x384, 0x58, 2, 0x0, 0, 0)
134#define _MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 IOMUX_PAD(0x384, 0x58, 5, 0x0, 0, 0)
135#define _MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3 IOMUX_PAD(0x384, 0x58, 6, 0x0, 0, 0)
136#define _MX53_PAD_DI0_PIN3__USBPHY1_IDDIG IOMUX_PAD(0x384, 0x58, 7, 0x0, 0, 0)
137#define _MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 IOMUX_PAD(0x388, 0x5C, 0, 0x0, 0, 0)
138#define _MX53_PAD_DI0_PIN4__GPIO4_20 IOMUX_PAD(0x388, 0x5C, 1, 0x0, 0, 0)
139#define _MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD IOMUX_PAD(0x388, 0x5C, 2, 0x0, 0, 0)
140#define _MX53_PAD_DI0_PIN4__ESDHC1_WP IOMUX_PAD(0x388, 0x5C, 3, 0x7FC, 0, 0)
141#define _MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD IOMUX_PAD(0x388, 0x5C, 5, 0x0, 0, 0)
142#define _MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4 IOMUX_PAD(0x388, 0x5C, 6, 0x0, 0, 0)
143#define _MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT IOMUX_PAD(0x388, 0x5C, 7, 0x0, 0, 0)
144#define _MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 IOMUX_PAD(0x38C, 0x60, 0, 0x0, 0, 0)
145#define _MX53_PAD_DISP0_DAT0__GPIO4_21 IOMUX_PAD(0x38C, 0x60, 1, 0x0, 0, 0)
146#define _MX53_PAD_DISP0_DAT0__CSPI_SCLK IOMUX_PAD(0x38C, 0x60, 2, 0x780, 0, 0)
147#define _MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0 IOMUX_PAD(0x38C, 0x60, 3, 0x0, 0, 0)
148#define _MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN IOMUX_PAD(0x38C, 0x60, 5, 0x0, 0, 0)
149#define _MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5 IOMUX_PAD(0x38C, 0x60, 6, 0x0, 0, 0)
150#define _MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY IOMUX_PAD(0x38C, 0x60, 7, 0x0, 0, 0)
151#define _MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 IOMUX_PAD(0x390, 0x64, 0, 0x0, 0, 0)
152#define _MX53_PAD_DISP0_DAT1__GPIO4_22 IOMUX_PAD(0x390, 0x64, 1, 0x0, 0, 0)
153#define _MX53_PAD_DISP0_DAT1__CSPI_MOSI IOMUX_PAD(0x390, 0x64, 2, 0x788, 0, 0)
154#define _MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1 IOMUX_PAD(0x390, 0x64, 3, 0x0, 0, 0)
155#define _MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL IOMUX_PAD(0x390, 0x64, 5, 0x0, 0, 0)
156#define _MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6 IOMUX_PAD(0x390, 0x64, 6, 0x0, 0, 0)
157#define _MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID IOMUX_PAD(0x390, 0x64, 7, 0x0, 0, 0)
158#define _MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 IOMUX_PAD(0x394, 0x68, 0, 0x0, 0, 0)
159#define _MX53_PAD_DISP0_DAT2__GPIO4_23 IOMUX_PAD(0x394, 0x68, 1, 0x0, 0, 0)
160#define _MX53_PAD_DISP0_DAT2__CSPI_MISO IOMUX_PAD(0x394, 0x68, 2, 0x784, 0, 0)
161#define _MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2 IOMUX_PAD(0x394, 0x68, 3, 0x0, 0, 0)
162#define _MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE IOMUX_PAD(0x394, 0x68, 5, 0x0, 0, 0)
163#define _MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7 IOMUX_PAD(0x394, 0x68, 6, 0x0, 0, 0)
164#define _MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE IOMUX_PAD(0x394, 0x68, 7, 0x0, 0, 0)
165#define _MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 IOMUX_PAD(0x398, 0x6C, 0, 0x0, 0, 0)
166#define _MX53_PAD_DISP0_DAT3__GPIO4_24 IOMUX_PAD(0x398, 0x6C, 1, 0x0, 0, 0)
167#define _MX53_PAD_DISP0_DAT3__CSPI_SS0 IOMUX_PAD(0x398, 0x6C, 2, 0x78C, 0, 0)
168#define _MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3 IOMUX_PAD(0x398, 0x6C, 3, 0x0, 0, 0)
169#define _MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR IOMUX_PAD(0x398, 0x6C, 5, 0x0, 0, 0)
170#define _MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8 IOMUX_PAD(0x398, 0x6C, 6, 0x0, 0, 0)
171#define _MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR IOMUX_PAD(0x398, 0x6C, 7, 0x0, 0, 0)
172#define _MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 IOMUX_PAD(0x39C, 0x70, 0, 0x0, 0, 0)
173#define _MX53_PAD_DISP0_DAT4__GPIO4_25 IOMUX_PAD(0x39C, 0x70, 1, 0x0, 0, 0)
174#define _MX53_PAD_DISP0_DAT4__CSPI_SS1 IOMUX_PAD(0x39C, 0x70, 2, 0x790, 0, 0)
175#define _MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4 IOMUX_PAD(0x39C, 0x70, 3, 0x0, 0, 0)
176#define _MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB IOMUX_PAD(0x39C, 0x70, 5, 0x0, 0, 0)
177#define _MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9 IOMUX_PAD(0x39C, 0x70, 6, 0x0, 0, 0)
178#define _MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK IOMUX_PAD(0x39C, 0x70, 7, 0x0, 0, 0)
179#define _MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 IOMUX_PAD(0x3A0, 0x74, 0, 0x0, 0, 0)
180#define _MX53_PAD_DISP0_DAT5__GPIO4_26 IOMUX_PAD(0x3A0, 0x74, 1, 0x0, 0, 0)
181#define _MX53_PAD_DISP0_DAT5__CSPI_SS2 IOMUX_PAD(0x3A0, 0x74, 2, 0x794, 0, 0)
182#define _MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5 IOMUX_PAD(0x3A0, 0x74, 3, 0x0, 0, 0)
183#define _MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS IOMUX_PAD(0x3A0, 0x74, 5, 0x0, 0, 0)
184#define _MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10 IOMUX_PAD(0x3A0, 0x74, 6, 0x0, 0, 0)
185#define _MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0 IOMUX_PAD(0x3A0, 0x74, 7, 0x0, 0, 0)
186#define _MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 IOMUX_PAD(0x3A4, 0x78, 0, 0x0, 0, 0)
187#define _MX53_PAD_DISP0_DAT6__GPIO4_27 IOMUX_PAD(0x3A4, 0x78, 1, 0x0, 0, 0)
188#define _MX53_PAD_DISP0_DAT6__CSPI_SS3 IOMUX_PAD(0x3A4, 0x78, 2, 0x798, 0, 0)
189#define _MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6 IOMUX_PAD(0x3A4, 0x78, 3, 0x0, 0, 0)
190#define _MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE IOMUX_PAD(0x3A4, 0x78, 5, 0x0, 0, 0)
191#define _MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11 IOMUX_PAD(0x3A4, 0x78, 6, 0x0, 0, 0)
192#define _MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1 IOMUX_PAD(0x3A4, 0x78, 7, 0x0, 0, 0)
193#define _MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 IOMUX_PAD(0x3A8, 0x7C, 0, 0x0, 0, 0)
194#define _MX53_PAD_DISP0_DAT7__GPIO4_28 IOMUX_PAD(0x3A8, 0x7C, 1, 0x0, 0, 0)
195#define _MX53_PAD_DISP0_DAT7__CSPI_RDY IOMUX_PAD(0x3A8, 0x7C, 2, 0x0, 0, 0)
196#define _MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7 IOMUX_PAD(0x3A8, 0x7C, 3, 0x0, 0, 0)
197#define _MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 IOMUX_PAD(0x3A8, 0x7C, 5, 0x0, 0, 0)
198#define _MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12 IOMUX_PAD(0x3A8, 0x7C, 6, 0x0, 0, 0)
199#define _MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID IOMUX_PAD(0x3A8, 0x7C, 7, 0x0, 0, 0)
200#define _MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 IOMUX_PAD(0x3AC, 0x80, 0, 0x0, 0, 0)
201#define _MX53_PAD_DISP0_DAT8__GPIO4_29 IOMUX_PAD(0x3AC, 0x80, 1, 0x0, 0, 0)
202#define _MX53_PAD_DISP0_DAT8__PWM1_PWMO IOMUX_PAD(0x3AC, 0x80, 2, 0x0, 0, 0)
203#define _MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B IOMUX_PAD(0x3AC, 0x80, 3, 0x0, 0, 0)
204#define _MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 IOMUX_PAD(0x3AC, 0x80, 5, 0x0, 0, 0)
205#define _MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13 IOMUX_PAD(0x3AC, 0x80, 6, 0x0, 0, 0)
206#define _MX53_PAD_DISP0_DAT8__USBPHY2_AVALID IOMUX_PAD(0x3AC, 0x80, 7, 0x0, 0, 0)
207#define _MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 IOMUX_PAD(0x3B0, 0x84, 0, 0x0, 0, 0)
208#define _MX53_PAD_DISP0_DAT9__GPIO4_30 IOMUX_PAD(0x3B0, 0x84, 1, 0x0, 0, 0)
209#define _MX53_PAD_DISP0_DAT9__PWM2_PWMO IOMUX_PAD(0x3B0, 0x84, 2, 0x0, 0, 0)
210#define _MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B IOMUX_PAD(0x3B0, 0x84, 3, 0x0, 0, 0)
211#define _MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 IOMUX_PAD(0x3B0, 0x84, 5, 0x0, 0, 0)
212#define _MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14 IOMUX_PAD(0x3B0, 0x84, 6, 0x0, 0, 0)
213#define _MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0 IOMUX_PAD(0x3B0, 0x84, 7, 0x0, 0, 0)
214#define _MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 IOMUX_PAD(0x3B4, 0x88, 0, 0x0, 0, 0)
215#define _MX53_PAD_DISP0_DAT10__GPIO4_31 IOMUX_PAD(0x3B4, 0x88, 1, 0x0, 0, 0)
216#define _MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP IOMUX_PAD(0x3B4, 0x88, 2, 0x0, 0, 0)
217#define _MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 IOMUX_PAD(0x3B4, 0x88, 5, 0x0, 0, 0)
218#define _MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15 IOMUX_PAD(0x3B4, 0x88, 6, 0x0, 0, 0)
219#define _MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1 IOMUX_PAD(0x3B4, 0x88, 7, 0x0, 0, 0)
220#define _MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 IOMUX_PAD(0x3B8, 0x8C, 0, 0x0, 0, 0)
221#define _MX53_PAD_DISP0_DAT11__GPIO5_5 IOMUX_PAD(0x3B8, 0x8C, 1, 0x0, 0, 0)
222#define _MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT IOMUX_PAD(0x3B8, 0x8C, 2, 0x0, 0, 0)
223#define _MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 IOMUX_PAD(0x3B8, 0x8C, 5, 0x0, 0, 0)
224#define _MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16 IOMUX_PAD(0x3B8, 0x8C, 6, 0x0, 0, 0)
225#define _MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2 IOMUX_PAD(0x3B8, 0x8C, 7, 0x0, 0, 0)
226#define _MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 IOMUX_PAD(0x3BC, 0x90, 0, 0x0, 0, 0)
227#define _MX53_PAD_DISP0_DAT12__GPIO5_6 IOMUX_PAD(0x3BC, 0x90, 1, 0x0, 0, 0)
228#define _MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK IOMUX_PAD(0x3BC, 0x90, 2, 0x0, 0, 0)
229#define _MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 IOMUX_PAD(0x3BC, 0x90, 5, 0x0, 0, 0)
230#define _MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17 IOMUX_PAD(0x3BC, 0x90, 6, 0x0, 0, 0)
231#define _MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3 IOMUX_PAD(0x3BC, 0x90, 7, 0x0, 0, 0)
232#define _MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 IOMUX_PAD(0x3C0, 0x94, 0, 0x0, 0, 0)
233#define _MX53_PAD_DISP0_DAT13__GPIO5_7 IOMUX_PAD(0x3C0, 0x94, 1, 0x0, 0, 0)
234#define _MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS IOMUX_PAD(0x3C0, 0x94, 3, 0x754, 0, 0)
235#define _MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 IOMUX_PAD(0x3C0, 0x94, 5, 0x0, 0, 0)
236#define _MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18 IOMUX_PAD(0x3C0, 0x94, 6, 0x0, 0, 0)
237#define _MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4 IOMUX_PAD(0x3C0, 0x94, 7, 0x0, 0, 0)
238#define _MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 IOMUX_PAD(0x3C4, 0x98, 0, 0x0, 0, 0)
239#define _MX53_PAD_DISP0_DAT14__GPIO5_8 IOMUX_PAD(0x3C4, 0x98, 1, 0x0, 0, 0)
240#define _MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC IOMUX_PAD(0x3C4, 0x98, 3, 0x750, 0, 0)
241#define _MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 IOMUX_PAD(0x3C4, 0x98, 5, 0x0, 0, 0)
242#define _MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19 IOMUX_PAD(0x3C4, 0x98, 6, 0x0, 0, 0)
243#define _MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5 IOMUX_PAD(0x3C4, 0x98, 7, 0x0, 0, 0)
244#define _MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 IOMUX_PAD(0x3C8, 0x9C, 0, 0x0, 0, 0)
245#define _MX53_PAD_DISP0_DAT15__GPIO5_9 IOMUX_PAD(0x3C8, 0x9C, 1, 0x0, 0, 0)
246#define _MX53_PAD_DISP0_DAT15__ECSPI1_SS1 IOMUX_PAD(0x3C8, 0x9C, 2, 0x7AC, 1, 0)
247#define _MX53_PAD_DISP0_DAT15__ECSPI2_SS1 IOMUX_PAD(0x3C8, 0x9C, 3, 0x7C8, 0, 0)
248#define _MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 IOMUX_PAD(0x3C8, 0x9C, 5, 0x0, 0, 0)
249#define _MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20 IOMUX_PAD(0x3C8, 0x9C, 6, 0x0, 0, 0)
250#define _MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6 IOMUX_PAD(0x3C8, 0x9C, 7, 0x0, 0, 0)
251#define _MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 IOMUX_PAD(0x3CC, 0xA0, 0, 0x0, 0, 0)
252#define _MX53_PAD_DISP0_DAT16__GPIO5_10 IOMUX_PAD(0x3CC, 0xA0, 1, 0x0, 0, 0)
253#define _MX53_PAD_DISP0_DAT16__ECSPI2_MOSI IOMUX_PAD(0x3CC, 0xA0, 2, 0x7C0, 0, 0)
254#define _MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC IOMUX_PAD(0x3CC, 0xA0, 3, 0x758, 1, 0)
255#define _MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 IOMUX_PAD(0x3CC, 0xA0, 4, 0x868, 0, 0)
256#define _MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3 IOMUX_PAD(0x3CC, 0xA0, 5, 0x0, 0, 0)
257#define _MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21 IOMUX_PAD(0x3CC, 0xA0, 6, 0x0, 0, 0)
258#define _MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7 IOMUX_PAD(0x3CC, 0xA0, 7, 0x0, 0, 0)
259#define _MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 IOMUX_PAD(0x3D0, 0xA4, 0, 0x0, 0, 0)
260#define _MX53_PAD_DISP0_DAT17__GPIO5_11 IOMUX_PAD(0x3D0, 0xA4, 1, 0x0, 0, 0)
261#define _MX53_PAD_DISP0_DAT17__ECSPI2_MISO IOMUX_PAD(0x3D0, 0xA4, 2, 0x7BC, 0, 0)
262#define _MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD IOMUX_PAD(0x3D0, 0xA4, 3, 0x74C, 1, 0)
263#define _MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 IOMUX_PAD(0x3D0, 0xA4, 4, 0x86C, 0, 0)
264#define _MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4 IOMUX_PAD(0x3D0, 0xA4, 5, 0x0, 0, 0)
265#define _MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22 IOMUX_PAD(0x3D0, 0xA4, 6, 0x0, 0, 0)
266#define _MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 IOMUX_PAD(0x3D4, 0xA8, 0, 0x0, 0, 0)
267#define _MX53_PAD_DISP0_DAT18__GPIO5_12 IOMUX_PAD(0x3D4, 0xA8, 1, 0x0, 0, 0)
268#define _MX53_PAD_DISP0_DAT18__ECSPI2_SS0 IOMUX_PAD(0x3D4, 0xA8, 2, 0x7C4, 0, 0)
269#define _MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS IOMUX_PAD(0x3D4, 0xA8, 3, 0x75C, 1, 0)
270#define _MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS IOMUX_PAD(0x3D4, 0xA8, 4, 0x73C, 0, 0)
271#define _MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5 IOMUX_PAD(0x3D4, 0xA8, 5, 0x0, 0, 0)
272#define _MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23 IOMUX_PAD(0x3D4, 0xA8, 6, 0x0, 0, 0)
273#define _MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2 IOMUX_PAD(0x3D4, 0xA8, 7, 0x0, 0, 0)
274#define _MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 IOMUX_PAD(0x3D8, 0xAC, 0, 0x0, 0, 0)
275#define _MX53_PAD_DISP0_DAT19__GPIO5_13 IOMUX_PAD(0x3D8, 0xAC, 1, 0x0, 0, 0)
276#define _MX53_PAD_DISP0_DAT19__ECSPI2_SCLK IOMUX_PAD(0x3D8, 0xAC, 2, 0x7B8, 0, 0)
277#define _MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD IOMUX_PAD(0x3D8, 0xAC, 3, 0x748, 1, 0)
278#define _MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC IOMUX_PAD(0x3D8, 0xAC, 4, 0x738, 0, 0)
279#define _MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6 IOMUX_PAD(0x3D8, 0xAC, 5, 0x0, 0, 0)
280#define _MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24 IOMUX_PAD(0x3D8, 0xAC, 6, 0x0, 0, 0)
281#define _MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3 IOMUX_PAD(0x3D8, 0xAC, 7, 0x0, 0, 0)
282#define _MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 IOMUX_PAD(0x3DC, 0xB0, 0, 0x0, 0, 0)
283#define _MX53_PAD_DISP0_DAT20__GPIO5_14 IOMUX_PAD(0x3DC, 0xB0, 1, 0x0, 0, 0)
284#define _MX53_PAD_DISP0_DAT20__ECSPI1_SCLK IOMUX_PAD(0x3DC, 0xB0, 2, 0x79C, 1, 0)
285#define _MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC IOMUX_PAD(0x3DC, 0xB0, 3, 0x740, 0, 0)
286#define _MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 IOMUX_PAD(0x3DC, 0xB0, 5, 0x0, 0, 0)
287#define _MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25 IOMUX_PAD(0x3DC, 0xB0, 6, 0x0, 0, 0)
288#define _MX53_PAD_DISP0_DAT20__SATA_PHY_TDI IOMUX_PAD(0x3DC, 0xB0, 7, 0x0, 0, 0)
289#define _MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 IOMUX_PAD(0x3E0, 0xB4, 0, 0x0, 0, 0)
290#define _MX53_PAD_DISP0_DAT21__GPIO5_15 IOMUX_PAD(0x3E0, 0xB4, 1, 0x0, 0, 0)
291#define _MX53_PAD_DISP0_DAT21__ECSPI1_MOSI IOMUX_PAD(0x3E0, 0xB4, 2, 0x7A4, 1, 0)
292#define _MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD IOMUX_PAD(0x3E0, 0xB4, 3, 0x734, 0, 0)
293#define _MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 IOMUX_PAD(0x3E0, 0xB4, 5, 0x0, 0, 0)
294#define _MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26 IOMUX_PAD(0x3E0, 0xB4, 6, 0x0, 0, 0)
295#define _MX53_PAD_DISP0_DAT21__SATA_PHY_TDO IOMUX_PAD(0x3E0, 0xB4, 7, 0x0, 0, 0)
296#define _MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 IOMUX_PAD(0x3E4, 0xB8, 0, 0x0, 0, 0)
297#define _MX53_PAD_DISP0_DAT22__GPIO5_16 IOMUX_PAD(0x3E4, 0xB8, 1, 0x0, 0, 0)
298#define _MX53_PAD_DISP0_DAT22__ECSPI1_MISO IOMUX_PAD(0x3E4, 0xB8, 2, 0x7A0, 1, 0)
299#define _MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS IOMUX_PAD(0x3E4, 0xB8, 3, 0x744, 0, 0)
300#define _MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 IOMUX_PAD(0x3E4, 0xB8, 5, 0x0, 0, 0)
301#define _MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27 IOMUX_PAD(0x3E4, 0xB8, 6, 0x0, 0, 0)
302#define _MX53_PAD_DISP0_DAT22__SATA_PHY_TCK IOMUX_PAD(0x3E4, 0xB8, 7, 0x0, 0, 0)
303#define _MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 IOMUX_PAD(0x3E8, 0xBC, 0, 0x0, 0, 0)
304#define _MX53_PAD_DISP0_DAT23__GPIO5_17 IOMUX_PAD(0x3E8, 0xBC, 1, 0x0, 0, 0)
305#define _MX53_PAD_DISP0_DAT23__ECSPI1_SS0 IOMUX_PAD(0x3E8, 0xBC, 2, 0x7A8, 1, 0)
306#define _MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD IOMUX_PAD(0x3E8, 0xBC, 3, 0x730, 0, 0)
307#define _MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 IOMUX_PAD(0x3E8, 0xBC, 5, 0x0, 0, 0)
308#define _MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28 IOMUX_PAD(0x3E8, 0xBC, 6, 0x0, 0, 0)
309#define _MX53_PAD_DISP0_DAT23__SATA_PHY_TMS IOMUX_PAD(0x3E8, 0xBC, 7, 0x0, 0, 0)
310#define _MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK IOMUX_PAD(0x3EC, 0xC0, 0, 0x0, 0, 0)
311#define _MX53_PAD_CSI0_PIXCLK__GPIO5_18 IOMUX_PAD(0x3EC, 0xC0, 1, 0x0, 0, 0)
312#define _MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 IOMUX_PAD(0x3EC, 0xC0, 5, 0x0, 0, 0)
313#define _MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29 IOMUX_PAD(0x3EC, 0xC0, 6, 0x0, 0, 0)
314#define _MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC IOMUX_PAD(0x3F0, 0xC4, 0, 0x0, 0, 0)
315#define _MX53_PAD_CSI0_MCLK__GPIO5_19 IOMUX_PAD(0x3F0, 0xC4, 1, 0x0, 0, 0)
316#define _MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK IOMUX_PAD(0x3F0, 0xC4, 2, 0x0, 0, 0)
317#define _MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 IOMUX_PAD(0x3F0, 0xC4, 5, 0x0, 0, 0)
318#define _MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30 IOMUX_PAD(0x3F0, 0xC4, 6, 0x0, 0, 0)
319#define _MX53_PAD_CSI0_MCLK__TPIU_TRCTL IOMUX_PAD(0x3F0, 0xC4, 7, 0x0, 0, 0)
320#define _MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN IOMUX_PAD(0x3F4, 0xC8, 0, 0x0, 0, 0)
321#define _MX53_PAD_CSI0_DATA_EN__GPIO5_20 IOMUX_PAD(0x3F4, 0xC8, 1, 0x0, 0, 0)
322#define _MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 IOMUX_PAD(0x3F4, 0xC8, 5, 0x0, 0, 0)
323#define _MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31 IOMUX_PAD(0x3F4, 0xC8, 6, 0x0, 0, 0)
324#define _MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK IOMUX_PAD(0x3F4, 0xC8, 7, 0x0, 0, 0)
325#define _MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC IOMUX_PAD(0x3F8, 0xCC, 0, 0x0, 0, 0)
326#define _MX53_PAD_CSI0_VSYNC__GPIO5_21 IOMUX_PAD(0x3F8, 0xCC, 1, 0x0, 0, 0)
327#define _MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 IOMUX_PAD(0x3F8, 0xCC, 5, 0x0, 0, 0)
328#define _MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32 IOMUX_PAD(0x3F8, 0xCC, 6, 0x0, 0, 0)
329#define _MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0 IOMUX_PAD(0x3F8, 0xCC, 7, 0x0, 0, 0)
330#define _MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 IOMUX_PAD(0x3FC, 0xD0, 0, 0x0, 0, 0)
331#define _MX53_PAD_CSI0_DAT4__GPIO5_22 IOMUX_PAD(0x3FC, 0xD0, 1, 0x0, 0, 0)
332#define _MX53_PAD_CSI0_DAT4__KPP_COL_5 IOMUX_PAD(0x3FC, 0xD0, 2, 0x840, 1, 0)
333#define _MX53_PAD_CSI0_DAT4__ECSPI1_SCLK IOMUX_PAD(0x3FC, 0xD0, 3, 0x79C, 2, 0)
334#define _MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP IOMUX_PAD(0x3FC, 0xD0, 4, 0x0, 0, 0)
335#define _MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC IOMUX_PAD(0x3FC, 0xD0, 5, 0x0, 0, 0)
336#define _MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33 IOMUX_PAD(0x3FC, 0xD0, 6, 0x0, 0, 0)
337#define _MX53_PAD_CSI0_DAT4__TPIU_TRACE_1 IOMUX_PAD(0x3FC, 0xD0, 7, 0x0, 0, 0)
338#define _MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 IOMUX_PAD(0x400, 0xD4, 0, 0x0, 0, 0)
339#define _MX53_PAD_CSI0_DAT5__GPIO5_23 IOMUX_PAD(0x400, 0xD4, 1, 0x0, 0, 0)
340#define _MX53_PAD_CSI0_DAT5__KPP_ROW_5 IOMUX_PAD(0x400, 0xD4, 2, 0x84C, 0, 0)
341#define _MX53_PAD_CSI0_DAT5__ECSPI1_MOSI IOMUX_PAD(0x400, 0xD4, 3, 0x7A4, 2, 0)
342#define _MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT IOMUX_PAD(0x400, 0xD4, 4, 0x0, 0, 0)
343#define _MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD IOMUX_PAD(0x400, 0xD4, 5, 0x0, 0, 0)
344#define _MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34 IOMUX_PAD(0x400, 0xD4, 6, 0x0, 0, 0)
345#define _MX53_PAD_CSI0_DAT5__TPIU_TRACE_2 IOMUX_PAD(0x400, 0xD4, 7, 0x0, 0, 0)
346#define _MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 IOMUX_PAD(0x404, 0xD8, 0, 0x0, 0, 0)
347#define _MX53_PAD_CSI0_DAT6__GPIO5_24 IOMUX_PAD(0x404, 0xD8, 1, 0x0, 0, 0)
348#define _MX53_PAD_CSI0_DAT6__KPP_COL_6 IOMUX_PAD(0x404, 0xD8, 2, 0x844, 0, 0)
349#define _MX53_PAD_CSI0_DAT6__ECSPI1_MISO IOMUX_PAD(0x404, 0xD8, 3, 0x7A0, 2, 0)
350#define _MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK IOMUX_PAD(0x404, 0xD8, 4, 0x0, 0, 0)
351#define _MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS IOMUX_PAD(0x404, 0xD8, 5, 0x0, 0, 0)
352#define _MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35 IOMUX_PAD(0x404, 0xD8, 6, 0x0, 0, 0)
353#define _MX53_PAD_CSI0_DAT6__TPIU_TRACE_3 IOMUX_PAD(0x404, 0xD8, 7, 0x0, 0, 0)
354#define _MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 IOMUX_PAD(0x408, 0xDC, 0, 0x0, 0, 0)
355#define _MX53_PAD_CSI0_DAT7__GPIO5_25 IOMUX_PAD(0x408, 0xDC, 1, 0x0, 0, 0)
356#define _MX53_PAD_CSI0_DAT7__KPP_ROW_6 IOMUX_PAD(0x408, 0xDC, 2, 0x850, 0, 0)
357#define _MX53_PAD_CSI0_DAT7__ECSPI1_SS0 IOMUX_PAD(0x408, 0xDC, 3, 0x7A8, 2, 0)
358#define _MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR IOMUX_PAD(0x408, 0xDC, 4, 0x0, 0, 0)
359#define _MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD IOMUX_PAD(0x408, 0xDC, 5, 0x0, 0, 0)
360#define _MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36 IOMUX_PAD(0x408, 0xDC, 6, 0x0, 0, 0)
361#define _MX53_PAD_CSI0_DAT7__TPIU_TRACE_4 IOMUX_PAD(0x408, 0xDC, 7, 0x0, 0, 0)
362#define _MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 IOMUX_PAD(0x40C, 0xE0, 0, 0x0, 0, 0)
363#define _MX53_PAD_CSI0_DAT8__GPIO5_26 IOMUX_PAD(0x40C, 0xE0, 1, 0x0, 0, 0)
364#define _MX53_PAD_CSI0_DAT8__KPP_COL_7 IOMUX_PAD(0x40C, 0xE0, 2, 0x848, 0, 0)
365#define _MX53_PAD_CSI0_DAT8__ECSPI2_SCLK IOMUX_PAD(0x40C, 0xE0, 3, 0x7B8, 1, 0)
366#define _MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC IOMUX_PAD(0x40C, 0xE0, 4, 0x0, 0, 0)
367#define _MX53_PAD_CSI0_DAT8__I2C1_SDA IOMUX_PAD(0x40C, 0xE0, 5 | IOMUX_CONFIG_SION, 0x818, 0, 0)
368#define _MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37 IOMUX_PAD(0x40C, 0xE0, 6, 0x0, 0, 0)
369#define _MX53_PAD_CSI0_DAT8__TPIU_TRACE_5 IOMUX_PAD(0x40C, 0xE0, 7, 0x0, 0, 0)
370#define _MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 IOMUX_PAD(0x410, 0xE4, 0, 0x0, 0, 0)
371#define _MX53_PAD_CSI0_DAT9__GPIO5_27 IOMUX_PAD(0x410, 0xE4, 1, 0x0, 0, 0)
372#define _MX53_PAD_CSI0_DAT9__KPP_ROW_7 IOMUX_PAD(0x410, 0xE4, 2, 0x854, 0, 0)
373#define _MX53_PAD_CSI0_DAT9__ECSPI2_MOSI IOMUX_PAD(0x410, 0xE4, 3, 0x7C0, 1, 0)
374#define _MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR IOMUX_PAD(0x410, 0xE4, 4, 0x0, 0, 0)
375#define _MX53_PAD_CSI0_DAT9__I2C1_SCL IOMUX_PAD(0x410, 0xE4, 5 | IOMUX_CONFIG_SION, 0x814, 0, 0)
376#define _MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38 IOMUX_PAD(0x410, 0xE4, 6, 0x0, 0, 0)
377#define _MX53_PAD_CSI0_DAT9__TPIU_TRACE_6 IOMUX_PAD(0x410, 0xE4, 7, 0x0, 0, 0)
378#define _MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 IOMUX_PAD(0x414, 0xE8, 0, 0x0, 0, 0)
379#define _MX53_PAD_CSI0_DAT10__GPIO5_28 IOMUX_PAD(0x414, 0xE8, 1, 0x0, 0, 0)
380#define _MX53_PAD_CSI0_DAT10__UART1_TXD_MUX IOMUX_PAD(0x414, 0xE8, 2, 0x878, 0, 0)
381#define _MX53_PAD_CSI0_DAT10__ECSPI2_MISO IOMUX_PAD(0x414, 0xE8, 3, 0x7BC, 1, 0)
382#define _MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC IOMUX_PAD(0x414, 0xE8, 4, 0x0, 0, 0)
383#define _MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 IOMUX_PAD(0x414, 0xE8, 5, 0x0, 0, 0)
384#define _MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39 IOMUX_PAD(0x414, 0xE8, 6, 0x0, 0, 0)
385#define _MX53_PAD_CSI0_DAT10__TPIU_TRACE_7 IOMUX_PAD(0x414, 0xE8, 7, 0x0, 0, 0)
386#define _MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 IOMUX_PAD(0x418, 0xEC, 0, 0x0, 0, 0)
387#define _MX53_PAD_CSI0_DAT11__GPIO5_29 IOMUX_PAD(0x418, 0xEC, 1, 0x0, 0, 0)
388#define _MX53_PAD_CSI0_DAT11__UART1_RXD_MUX IOMUX_PAD(0x418, 0xEC, 2, 0x878, 1, 0)
389#define _MX53_PAD_CSI0_DAT11__ECSPI2_SS0 IOMUX_PAD(0x418, 0xEC, 3, 0x7C4, 1, 0)
390#define _MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS IOMUX_PAD(0x418, 0xEC, 4, 0x0, 0, 0)
391#define _MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 IOMUX_PAD(0x418, 0xEC, 5, 0x0, 0, 0)
392#define _MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40 IOMUX_PAD(0x418, 0xEC, 6, 0x0, 0, 0)
393#define _MX53_PAD_CSI0_DAT11__TPIU_TRACE_8 IOMUX_PAD(0x418, 0xEC, 7, 0x0, 0, 0)
394#define _MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 IOMUX_PAD(0x41C, 0xF0, 0, 0x0, 0, 0)
395#define _MX53_PAD_CSI0_DAT12__GPIO5_30 IOMUX_PAD(0x41C, 0xF0, 1, 0x0, 0, 0)
396#define _MX53_PAD_CSI0_DAT12__UART4_TXD_MUX IOMUX_PAD(0x41C, 0xF0, 2, 0x890, 2, 0)
397#define _MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0 IOMUX_PAD(0x41C, 0xF0, 4, 0x0, 0, 0)
398#define _MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 IOMUX_PAD(0x41C, 0xF0, 5, 0x0, 0, 0)
399#define _MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41 IOMUX_PAD(0x41C, 0xF0, 6, 0x0, 0, 0)
400#define _MX53_PAD_CSI0_DAT12__TPIU_TRACE_9 IOMUX_PAD(0x41C, 0xF0, 7, 0x0, 0, 0)
401#define _MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 IOMUX_PAD(0x420, 0xF4, 0, 0x0, 0, 0)
402#define _MX53_PAD_CSI0_DAT13__GPIO5_31 IOMUX_PAD(0x420, 0xF4, 1, 0x0, 0, 0)
403#define _MX53_PAD_CSI0_DAT13__UART4_RXD_MUX IOMUX_PAD(0x420, 0xF4, 2, 0x890, 3, 0)
404#define _MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1 IOMUX_PAD(0x420, 0xF4, 4, 0x0, 0, 0)
405#define _MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 IOMUX_PAD(0x420, 0xF4, 5, 0x0, 0, 0)
406#define _MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42 IOMUX_PAD(0x420, 0xF4, 6, 0x0, 0, 0)
407#define _MX53_PAD_CSI0_DAT13__TPIU_TRACE_10 IOMUX_PAD(0x420, 0xF4, 7, 0x0, 0, 0)
408#define _MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 IOMUX_PAD(0x424, 0xF8, 0, 0x0, 0, 0)
409#define _MX53_PAD_CSI0_DAT14__GPIO6_0 IOMUX_PAD(0x424, 0xF8, 1, 0x0, 0, 0)
410#define _MX53_PAD_CSI0_DAT14__UART5_TXD_MUX IOMUX_PAD(0x424, 0xF8, 2, 0x898, 2, 0)
411#define _MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2 IOMUX_PAD(0x424, 0xF8, 4, 0x0, 0, 0)
412#define _MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 IOMUX_PAD(0x424, 0xF8, 5, 0x0, 0, 0)
413#define _MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43 IOMUX_PAD(0x424, 0xF8, 6, 0x0, 0, 0)
414#define _MX53_PAD_CSI0_DAT14__TPIU_TRACE_11 IOMUX_PAD(0x424, 0xF8, 7, 0x0, 0, 0)
415#define _MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 IOMUX_PAD(0x428, 0xFC, 0, 0x0, 0, 0)
416#define _MX53_PAD_CSI0_DAT15__GPIO6_1 IOMUX_PAD(0x428, 0xFC, 1, 0x0, 0, 0)
417#define _MX53_PAD_CSI0_DAT15__UART5_RXD_MUX IOMUX_PAD(0x428, 0xFC, 2, 0x898, 3, 0)
418#define _MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3 IOMUX_PAD(0x428, 0xFC, 4, 0x0, 0, 0)
419#define _MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 IOMUX_PAD(0x428, 0xFC, 5, 0x0, 0, 0)
420#define _MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44 IOMUX_PAD(0x428, 0xFC, 6, 0x0, 0, 0)
421#define _MX53_PAD_CSI0_DAT15__TPIU_TRACE_12 IOMUX_PAD(0x428, 0xFC, 7, 0x0, 0, 0)
422#define _MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 IOMUX_PAD(0x42C, 0x100, 0, 0x0, 0, 0)
423#define _MX53_PAD_CSI0_DAT16__GPIO6_2 IOMUX_PAD(0x42C, 0x100, 1, 0x0, 0, 0)
424#define _MX53_PAD_CSI0_DAT16__UART4_RTS IOMUX_PAD(0x42C, 0x100, 2, 0x88C, 0, 0)
425#define _MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4 IOMUX_PAD(0x42C, 0x100, 4, 0x0, 0, 0)
426#define _MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 IOMUX_PAD(0x42C, 0x100, 5, 0x0, 0, 0)
427#define _MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45 IOMUX_PAD(0x42C, 0x100, 6, 0x0, 0, 0)
428#define _MX53_PAD_CSI0_DAT16__TPIU_TRACE_13 IOMUX_PAD(0x42C, 0x100, 7, 0x0, 0, 0)
429#define _MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 IOMUX_PAD(0x430, 0x104, 0, 0x0, 0, 0)
430#define _MX53_PAD_CSI0_DAT17__GPIO6_3 IOMUX_PAD(0x430, 0x104, 1, 0x0, 0, 0)
431#define _MX53_PAD_CSI0_DAT17__UART4_CTS IOMUX_PAD(0x430, 0x104, 2, 0x88C, 1, 0)
432#define _MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5 IOMUX_PAD(0x430, 0x104, 4, 0x0, 0, 0)
433#define _MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 IOMUX_PAD(0x430, 0x104, 5, 0x0, 0, 0)
434#define _MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46 IOMUX_PAD(0x430, 0x104, 6, 0x0, 0, 0)
435#define _MX53_PAD_CSI0_DAT17__TPIU_TRACE_14 IOMUX_PAD(0x430, 0x104, 7, 0x0, 0, 0)
436#define _MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 IOMUX_PAD(0x434, 0x108, 0, 0x0, 0, 0)
437#define _MX53_PAD_CSI0_DAT18__GPIO6_4 IOMUX_PAD(0x434, 0x108, 1, 0x0, 0, 0)
438#define _MX53_PAD_CSI0_DAT18__UART5_RTS IOMUX_PAD(0x434, 0x108, 2, 0x894, 2, 0)
439#define _MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6 IOMUX_PAD(0x434, 0x108, 4, 0x0, 0, 0)
440#define _MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 IOMUX_PAD(0x434, 0x108, 5, 0x0, 0, 0)
441#define _MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47 IOMUX_PAD(0x434, 0x108, 6, 0x0, 0, 0)
442#define _MX53_PAD_CSI0_DAT18__TPIU_TRACE_15 IOMUX_PAD(0x434, 0x108, 7, 0x0, 0, 0)
443#define _MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 IOMUX_PAD(0x438, 0x10C, 0, 0x0, 0, 0)
444#define _MX53_PAD_CSI0_DAT19__GPIO6_5 IOMUX_PAD(0x438, 0x10C, 1, 0x0, 0, 0)
445#define _MX53_PAD_CSI0_DAT19__UART5_CTS IOMUX_PAD(0x438, 0x10C, 2, 0x894, 3, 0)
446#define _MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7 IOMUX_PAD(0x438, 0x10C, 4, 0x0, 0, 0)
447#define _MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 IOMUX_PAD(0x438, 0x10C, 5, 0x0, 0, 0)
448#define _MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48 IOMUX_PAD(0x438, 0x10C, 6, 0x0, 0, 0)
449#define _MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK IOMUX_PAD(0x438, 0x10C, 7, 0x0, 0, 0)
450#define _MX53_PAD_EIM_A25__EMI_WEIM_A_25 IOMUX_PAD(0x458, 0x110, 0, 0x0, 0, 0)
451#define _MX53_PAD_EIM_A25__GPIO5_2 IOMUX_PAD(0x458, 0x110, 1, 0x0, 0, 0)
452#define _MX53_PAD_EIM_A25__ECSPI2_RDY IOMUX_PAD(0x458, 0x110, 2, 0x0, 0, 0)
453#define _MX53_PAD_EIM_A25__IPU_DI1_PIN12 IOMUX_PAD(0x458, 0x110, 3, 0x0, 0, 0)
454#define _MX53_PAD_EIM_A25__CSPI_SS1 IOMUX_PAD(0x458, 0x110, 4, 0x790, 1, 0)
455#define _MX53_PAD_EIM_A25__IPU_DI0_D1_CS IOMUX_PAD(0x458, 0x110, 6, 0x0, 0, 0)
456#define _MX53_PAD_EIM_A25__USBPHY1_BISTOK IOMUX_PAD(0x458, 0x110, 7, 0x0, 0, 0)
457#define _MX53_PAD_EIM_EB2__EMI_WEIM_EB_2 IOMUX_PAD(0x45C, 0x114, 0, 0x0, 0, 0)
458#define _MX53_PAD_EIM_EB2__GPIO2_30 IOMUX_PAD(0x45C, 0x114, 1, 0x0, 0, 0)
459#define _MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK IOMUX_PAD(0x45C, 0x114, 2, 0x76C, 0, 0)
460#define _MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS IOMUX_PAD(0x45C, 0x114, 3, 0x0, 0, 0)
461#define _MX53_PAD_EIM_EB2__ECSPI1_SS0 IOMUX_PAD(0x45C, 0x114, 4, 0x7A8, 3, 0)
462#define _MX53_PAD_EIM_EB2__I2C2_SCL IOMUX_PAD(0x45C, 0x114, 5 | IOMUX_CONFIG_SION, 0x81C, 1, 0)
463#define _MX53_PAD_EIM_D16__EMI_WEIM_D_16 IOMUX_PAD(0x460, 0x118, 0, 0x0, 0, 0)
464#define _MX53_PAD_EIM_D16__GPIO3_16 IOMUX_PAD(0x460, 0x118, 1, 0x0, 0, 0)
465#define _MX53_PAD_EIM_D16__IPU_DI0_PIN5 IOMUX_PAD(0x460, 0x118, 2, 0x0, 0, 0)
466#define _MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK IOMUX_PAD(0x460, 0x118, 3, 0x0, 0, 0)
467#define _MX53_PAD_EIM_D16__ECSPI1_SCLK IOMUX_PAD(0x460, 0x118, 4, 0x79C, 3, 0)
468#define _MX53_PAD_EIM_D16__I2C2_SDA IOMUX_PAD(0x460, 0x118, 5, 0x820, 1, 0)
469#define _MX53_PAD_EIM_D17__EMI_WEIM_D_17 IOMUX_PAD(0x464, 0x11C, 0, 0x0, 0, 0)
470#define _MX53_PAD_EIM_D17__GPIO3_17 IOMUX_PAD(0x464, 0x11C, 1, 0x0, 0, 0)
471#define _MX53_PAD_EIM_D17__IPU_DI0_PIN6 IOMUX_PAD(0x464, 0x11C, 2, 0x0, 0, 0)
472#define _MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN IOMUX_PAD(0x464, 0x11C, 3, 0x830, 0, 0)
473#define _MX53_PAD_EIM_D17__ECSPI1_MISO IOMUX_PAD(0x464, 0x11C, 4, 0x7A0, 3, 0)
474#define _MX53_PAD_EIM_D17__I2C3_SCL IOMUX_PAD(0x464, 0x11C, 5, 0x824, 0, 0)
475#define _MX53_PAD_EIM_D18__EMI_WEIM_D_18 IOMUX_PAD(0x468, 0x120, 0, 0x0, 0, 0)
476#define _MX53_PAD_EIM_D18__GPIO3_18 IOMUX_PAD(0x468, 0x120, 1, 0x0, 0, 0)
477#define _MX53_PAD_EIM_D18__IPU_DI0_PIN7 IOMUX_PAD(0x468, 0x120, 2, 0x0, 0, 0)
478#define _MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO IOMUX_PAD(0x468, 0x120, 3, 0x830, 1, 0)
479#define _MX53_PAD_EIM_D18__ECSPI1_MOSI IOMUX_PAD(0x468, 0x120, 4, 0x7A4, 3, 0)
480#define _MX53_PAD_EIM_D18__I2C3_SDA IOMUX_PAD(0x468, 0x120, 5, 0x828, 0, 0)
481#define _MX53_PAD_EIM_D18__IPU_DI1_D0_CS IOMUX_PAD(0x468, 0x120, 6, 0x0, 0, 0)
482#define _MX53_PAD_EIM_D19__EMI_WEIM_D_19 IOMUX_PAD(0x46C, 0x124, 0, 0x0, 0, 0)
483#define _MX53_PAD_EIM_D19__GPIO3_19 IOMUX_PAD(0x46C, 0x124, 1, 0x0, 0, 0)
484#define _MX53_PAD_EIM_D19__IPU_DI0_PIN8 IOMUX_PAD(0x46C, 0x124, 2, 0x0, 0, 0)
485#define _MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS IOMUX_PAD(0x46C, 0x124, 3, 0x0, 0, 0)
486#define _MX53_PAD_EIM_D19__ECSPI1_SS1 IOMUX_PAD(0x46C, 0x124, 4, 0x7AC, 2, 0)
487#define _MX53_PAD_EIM_D19__EPIT1_EPITO IOMUX_PAD(0x46C, 0x124, 5, 0x0, 0, 0)
488#define _MX53_PAD_EIM_D19__UART1_CTS IOMUX_PAD(0x46C, 0x124, 6, 0x874, 0, 0)
489#define _MX53_PAD_EIM_D19__USBOH3_USBH2_OC IOMUX_PAD(0x46C, 0x124, 7, 0x8A4, 0, 0)
490#define _MX53_PAD_EIM_D20__EMI_WEIM_D_20 IOMUX_PAD(0x470, 0x128, 0, 0x0, 0, 0)
491#define _MX53_PAD_EIM_D20__GPIO3_20 IOMUX_PAD(0x470, 0x128, 1, 0x0, 0, 0)
492#define _MX53_PAD_EIM_D20__IPU_DI0_PIN16 IOMUX_PAD(0x470, 0x128, 2, 0x0, 0, 0)
493#define _MX53_PAD_EIM_D20__IPU_SER_DISP0_CS IOMUX_PAD(0x470, 0x128, 3, 0x0, 0, 0)
494#define _MX53_PAD_EIM_D20__CSPI_SS0 IOMUX_PAD(0x470, 0x128, 4, 0x78C, 1, 0)
495#define _MX53_PAD_EIM_D20__EPIT2_EPITO IOMUX_PAD(0x470, 0x128, 5, 0x0, 0, 0)
496#define _MX53_PAD_EIM_D20__UART1_RTS IOMUX_PAD(0x470, 0x128, 6, 0x874, 1, 0)
497#define _MX53_PAD_EIM_D20__USBOH3_USBH2_PWR IOMUX_PAD(0x470, 0x128, 7, 0x0, 0, 0)
498#define _MX53_PAD_EIM_D21__EMI_WEIM_D_21 IOMUX_PAD(0x474, 0x12C, 0, 0x0, 0, 0)
499#define _MX53_PAD_EIM_D21__GPIO3_21 IOMUX_PAD(0x474, 0x12C, 1, 0x0, 0, 0)
500#define _MX53_PAD_EIM_D21__IPU_DI0_PIN17 IOMUX_PAD(0x474, 0x12C, 2, 0x0, 0, 0)
501#define _MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK IOMUX_PAD(0x474, 0x12C, 3, 0x0, 0, 0)
502#define _MX53_PAD_EIM_D21__CSPI_SCLK IOMUX_PAD(0x474, 0x12C, 4, 0x780, 1, 0)
503#define _MX53_PAD_EIM_D21__I2C1_SCL IOMUX_PAD(0x474, 0x12C, 5, 0x814, 1, 0)
504#define _MX53_PAD_EIM_D21__USBOH3_USBOTG_OC IOMUX_PAD(0x474, 0x12C, 6, 0x89C, 1, 0)
505#define _MX53_PAD_EIM_D22__EMI_WEIM_D_22 IOMUX_PAD(0x478, 0x130, 0, 0x0, 0, 0)
506#define _MX53_PAD_EIM_D22__GPIO3_22 IOMUX_PAD(0x478, 0x130, 1, 0x0, 0, 0)
507#define _MX53_PAD_EIM_D22__IPU_DI0_PIN1 IOMUX_PAD(0x478, 0x130, 2, 0x0, 0, 0)
508#define _MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN IOMUX_PAD(0x478, 0x130, 3, 0x82C, 0, 0)
509#define _MX53_PAD_EIM_D22__CSPI_MISO IOMUX_PAD(0x478, 0x130, 4, 0x784, 1, 0)
510#define _MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR IOMUX_PAD(0x478, 0x130, 6, 0x0, 0, 0)
511#define _MX53_PAD_EIM_D23__EMI_WEIM_D_23 IOMUX_PAD(0x47C, 0x134, 0, 0x0, 0, 0)
512#define _MX53_PAD_EIM_D23__GPIO3_23 IOMUX_PAD(0x47C, 0x134, 1, 0x0, 0, 0)
513#define _MX53_PAD_EIM_D23__UART3_CTS IOMUX_PAD(0x47C, 0x134, 2, 0x884, 0, 0)
514#define _MX53_PAD_EIM_D23__UART1_DCD IOMUX_PAD(0x47C, 0x134, 3, 0x0, 0, 0)
515#define _MX53_PAD_EIM_D23__IPU_DI0_D0_CS IOMUX_PAD(0x47C, 0x134, 4, 0x0, 0, 0)
516#define _MX53_PAD_EIM_D23__IPU_DI1_PIN2 IOMUX_PAD(0x47C, 0x134, 5, 0x0, 0, 0)
517#define _MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN IOMUX_PAD(0x47C, 0x134, 6, 0x834, 0, 0)
518#define _MX53_PAD_EIM_D23__IPU_DI1_PIN14 IOMUX_PAD(0x47C, 0x134, 7, 0x0, 0, 0)
519#define _MX53_PAD_EIM_EB3__EMI_WEIM_EB_3 IOMUX_PAD(0x480, 0x138, 0, 0x0, 0, 0)
520#define _MX53_PAD_EIM_EB3__GPIO2_31 IOMUX_PAD(0x480, 0x138, 1, 0x0, 0, 0)
521#define _MX53_PAD_EIM_EB3__UART3_RTS IOMUX_PAD(0x480, 0x138, 2, 0x884, 1, 0)
522#define _MX53_PAD_EIM_EB3__UART1_RI IOMUX_PAD(0x480, 0x138, 3, 0x0, 0, 0)
523#define _MX53_PAD_EIM_EB3__IPU_DI1_PIN3 IOMUX_PAD(0x480, 0x138, 5, 0x0, 0, 0)
524#define _MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC IOMUX_PAD(0x480, 0x138, 6, 0x838, 0, 0)
525#define _MX53_PAD_EIM_EB3__IPU_DI1_PIN16 IOMUX_PAD(0x480, 0x138, 7, 0x0, 0, 0)
526#define _MX53_PAD_EIM_D24__EMI_WEIM_D_24 IOMUX_PAD(0x484, 0x13C, 0, 0x0, 0, 0)
527#define _MX53_PAD_EIM_D24__GPIO3_24 IOMUX_PAD(0x484, 0x13C, 1, 0x0, 0, 0)
528#define _MX53_PAD_EIM_D24__UART3_TXD_MUX IOMUX_PAD(0x484, 0x13C, 2, 0x888, 0, 0)
529#define _MX53_PAD_EIM_D24__ECSPI1_SS2 IOMUX_PAD(0x484, 0x13C, 3, 0x7B0, 1, 0)
530#define _MX53_PAD_EIM_D24__CSPI_SS2 IOMUX_PAD(0x484, 0x13C, 4, 0x794, 1, 0)
531#define _MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS IOMUX_PAD(0x484, 0x13C, 5, 0x754, 1, 0)
532#define _MX53_PAD_EIM_D24__ECSPI2_SS2 IOMUX_PAD(0x484, 0x13C, 6, 0x0, 0, 0)
533#define _MX53_PAD_EIM_D24__UART1_DTR IOMUX_PAD(0x484, 0x13C, 7, 0x0, 0, 0)
534#define _MX53_PAD_EIM_D25__EMI_WEIM_D_25 IOMUX_PAD(0x488, 0x140, 0, 0x0, 0, 0)
535#define _MX53_PAD_EIM_D25__GPIO3_25 IOMUX_PAD(0x488, 0x140, 1, 0x0, 0, 0)
536#define _MX53_PAD_EIM_D25__UART3_RXD_MUX IOMUX_PAD(0x488, 0x140, 2, 0x888, 1, 0)
537#define _MX53_PAD_EIM_D25__ECSPI1_SS3 IOMUX_PAD(0x488, 0x140, 3, 0x7B4, 1, 0)
538#define _MX53_PAD_EIM_D25__CSPI_SS3 IOMUX_PAD(0x488, 0x140, 4, 0x798, 1, 0)
539#define _MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC IOMUX_PAD(0x488, 0x140, 5, 0x750, 1, 0)
540#define _MX53_PAD_EIM_D25__ECSPI2_SS3 IOMUX_PAD(0x488, 0x140, 6, 0x0, 0, 0)
541#define _MX53_PAD_EIM_D25__UART1_DSR IOMUX_PAD(0x488, 0x140, 7, 0x0, 0, 0)
542#define _MX53_PAD_EIM_D26__EMI_WEIM_D_26 IOMUX_PAD(0x48C, 0x144, 0, 0x0, 0, 0)
543#define _MX53_PAD_EIM_D26__GPIO3_26 IOMUX_PAD(0x48C, 0x144, 1, 0x0, 0, 0)
544#define _MX53_PAD_EIM_D26__UART2_TXD_MUX IOMUX_PAD(0x48C, 0x144, 2, 0x880, 0, 0)
545#define _MX53_PAD_EIM_D26__FIRI_RXD IOMUX_PAD(0x48C, 0x144, 3, 0x80C, 0, 0)
546#define _MX53_PAD_EIM_D26__IPU_CSI0_D_1 IOMUX_PAD(0x48C, 0x144, 4, 0x0, 0, 0)
547#define _MX53_PAD_EIM_D26__IPU_DI1_PIN11 IOMUX_PAD(0x48C, 0x144, 5, 0x0, 0, 0)
548#define _MX53_PAD_EIM_D26__IPU_SISG_2 IOMUX_PAD(0x48C, 0x144, 6, 0x0, 0, 0)
549#define _MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 IOMUX_PAD(0x48C, 0x144, 7, 0x0, 0, 0)
550#define _MX53_PAD_EIM_D27__EMI_WEIM_D_27 IOMUX_PAD(0x490, 0x148, 0, 0x0, 0, 0)
551#define _MX53_PAD_EIM_D27__GPIO3_27 IOMUX_PAD(0x490, 0x148, 1, 0x0, 0, 0)
552#define _MX53_PAD_EIM_D27__UART2_RXD_MUX IOMUX_PAD(0x490, 0x148, 2, 0x880, 1, 0)
553#define _MX53_PAD_EIM_D27__FIRI_TXD IOMUX_PAD(0x490, 0x148, 3, 0x0, 0, 0)
554#define _MX53_PAD_EIM_D27__IPU_CSI0_D_0 IOMUX_PAD(0x490, 0x148, 4, 0x0, 0, 0)
555#define _MX53_PAD_EIM_D27__IPU_DI1_PIN13 IOMUX_PAD(0x490, 0x148, 5, 0x0, 0, 0)
556#define _MX53_PAD_EIM_D27__IPU_SISG_3 IOMUX_PAD(0x490, 0x148, 6, 0x0, 0, 0)
557#define _MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 IOMUX_PAD(0x490, 0x148, 7, 0x0, 0, 0)
558#define _MX53_PAD_EIM_D28__EMI_WEIM_D_28 IOMUX_PAD(0x494, 0x14C, 0, 0x0, 0, 0)
559#define _MX53_PAD_EIM_D28__GPIO3_28 IOMUX_PAD(0x494, 0x14C, 1, 0x0, 0, 0)
560#define _MX53_PAD_EIM_D28__UART2_CTS IOMUX_PAD(0x494, 0x14C, 2, 0x87C, 0, 0)
561#define _MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO IOMUX_PAD(0x494, 0x14C, 3, 0x82C, 1, 0)
562#define _MX53_PAD_EIM_D28__CSPI_MOSI IOMUX_PAD(0x494, 0x14C, 4, 0x788, 1, 0)
563#define _MX53_PAD_EIM_D28__I2C1_SDA IOMUX_PAD(0x494, 0x14C, 5, 0x818, 1, 0)
564#define _MX53_PAD_EIM_D28__IPU_EXT_TRIG IOMUX_PAD(0x494, 0x14C, 6, 0x0, 0, 0)
565#define _MX53_PAD_EIM_D28__IPU_DI0_PIN13 IOMUX_PAD(0x494, 0x14C, 7, 0x0, 0, 0)
566#define _MX53_PAD_EIM_D29__EMI_WEIM_D_29 IOMUX_PAD(0x498, 0x150, 0, 0x0, 0, 0)
567#define _MX53_PAD_EIM_D29__GPIO3_29 IOMUX_PAD(0x498, 0x150, 1, 0x0, 0, 0)
568#define _MX53_PAD_EIM_D29__UART2_RTS IOMUX_PAD(0x498, 0x150, 2, 0x87C, 1, 0)
569#define _MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS IOMUX_PAD(0x498, 0x150, 3, 0x0, 0, 0)
570#define _MX53_PAD_EIM_D29__CSPI_SS0 IOMUX_PAD(0x498, 0x150, 4, 0x78C, 2, 0)
571#define _MX53_PAD_EIM_D29__IPU_DI1_PIN15 IOMUX_PAD(0x498, 0x150, 5, 0x0, 0, 0)
572#define _MX53_PAD_EIM_D29__IPU_CSI1_VSYNC IOMUX_PAD(0x498, 0x150, 6, 0x83C, 0, 0)
573#define _MX53_PAD_EIM_D29__IPU_DI0_PIN14 IOMUX_PAD(0x498, 0x150, 7, 0x0, 0, 0)
574#define _MX53_PAD_EIM_D30__EMI_WEIM_D_30 IOMUX_PAD(0x49C, 0x154, 0, 0x0, 0, 0)
575#define _MX53_PAD_EIM_D30__GPIO3_30 IOMUX_PAD(0x49C, 0x154, 1, 0x0, 0, 0)
576#define _MX53_PAD_EIM_D30__UART3_CTS IOMUX_PAD(0x49C, 0x154, 2, 0x884, 2, 0)
577#define _MX53_PAD_EIM_D30__IPU_CSI0_D_3 IOMUX_PAD(0x49C, 0x154, 3, 0x0, 0, 0)
578#define _MX53_PAD_EIM_D30__IPU_DI0_PIN11 IOMUX_PAD(0x49C, 0x154, 4, 0x0, 0, 0)
579#define _MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 IOMUX_PAD(0x49C, 0x154, 5, 0x0, 0, 0)
580#define _MX53_PAD_EIM_D30__USBOH3_USBH1_OC IOMUX_PAD(0x49C, 0x154, 6, 0x8A0, 0, 0)
581#define _MX53_PAD_EIM_D30__USBOH3_USBH2_OC IOMUX_PAD(0x49C, 0x154, 7, 0x8A4, 1, 0)
582#define _MX53_PAD_EIM_D31__EMI_WEIM_D_31 IOMUX_PAD(0x4A0, 0x158, 0, 0x0, 0, 0)
583#define _MX53_PAD_EIM_D31__GPIO3_31 IOMUX_PAD(0x4A0, 0x158, 1, 0x0, 0, 0)
584#define _MX53_PAD_EIM_D31__UART3_RTS IOMUX_PAD(0x4A0, 0x158, 2, 0x884, 3, 0)
585#define _MX53_PAD_EIM_D31__IPU_CSI0_D_2 IOMUX_PAD(0x4A0, 0x158, 3, 0x0, 0, 0)
586#define _MX53_PAD_EIM_D31__IPU_DI0_PIN12 IOMUX_PAD(0x4A0, 0x158, 4, 0x0, 0, 0)
587#define _MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 IOMUX_PAD(0x4A0, 0x158, 5, 0x0, 0, 0)
588#define _MX53_PAD_EIM_D31__USBOH3_USBH1_PWR IOMUX_PAD(0x4A0, 0x158, 6, 0x0, 0, 0)
589#define _MX53_PAD_EIM_D31__USBOH3_USBH2_PWR IOMUX_PAD(0x4A0, 0x158, 7, 0x0, 0, 0)
590#define _MX53_PAD_EIM_A24__EMI_WEIM_A_24 IOMUX_PAD(0x4A8, 0x15C, 0, 0x0, 0, 0)
591#define _MX53_PAD_EIM_A24__GPIO5_4 IOMUX_PAD(0x4A8, 0x15C, 1, 0x0, 0, 0)
592#define _MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 IOMUX_PAD(0x4A8, 0x15C, 2, 0x0, 0, 0)
593#define _MX53_PAD_EIM_A24__IPU_CSI1_D_19 IOMUX_PAD(0x4A8, 0x15C, 3, 0x0, 0, 0)
594#define _MX53_PAD_EIM_A24__IPU_SISG_2 IOMUX_PAD(0x4A8, 0x15C, 6, 0x0, 0, 0)
595#define _MX53_PAD_EIM_A24__USBPHY2_BVALID IOMUX_PAD(0x4A8, 0x15C, 7, 0x0, 0, 0)
596#define _MX53_PAD_EIM_A23__EMI_WEIM_A_23 IOMUX_PAD(0x4AC, 0x160, 0, 0x0, 0, 0)
597#define _MX53_PAD_EIM_A23__GPIO6_6 IOMUX_PAD(0x4AC, 0x160, 1, 0x0, 0, 0)
598#define _MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 IOMUX_PAD(0x4AC, 0x160, 2, 0x0, 0, 0)
599#define _MX53_PAD_EIM_A23__IPU_CSI1_D_18 IOMUX_PAD(0x4AC, 0x160, 3, 0x0, 0, 0)
600#define _MX53_PAD_EIM_A23__IPU_SISG_3 IOMUX_PAD(0x4AC, 0x160, 6, 0x0, 0, 0)
601#define _MX53_PAD_EIM_A23__USBPHY2_ENDSESSION IOMUX_PAD(0x4AC, 0x160, 7, 0x0, 0, 0)
602#define _MX53_PAD_EIM_A22__EMI_WEIM_A_22 IOMUX_PAD(0x4B0, 0x164, 0, 0x0, 0, 0)
603#define _MX53_PAD_EIM_A22__GPIO2_16 IOMUX_PAD(0x4B0, 0x164, 1, 0x0, 0, 0)
604#define _MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 IOMUX_PAD(0x4B0, 0x164, 2, 0x0, 0, 0)
605#define _MX53_PAD_EIM_A22__IPU_CSI1_D_17 IOMUX_PAD(0x4B0, 0x164, 3, 0x0, 0, 0)
606#define _MX53_PAD_EIM_A22__SRC_BT_CFG1_7 IOMUX_PAD(0x4B0, 0x164, 7, 0x0, 0, 0)
607#define _MX53_PAD_EIM_A21__EMI_WEIM_A_21 IOMUX_PAD(0x4B4, 0x168, 0, 0x0, 0, 0)
608#define _MX53_PAD_EIM_A21__GPIO2_17 IOMUX_PAD(0x4B4, 0x168, 1, 0x0, 0, 0)
609#define _MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 IOMUX_PAD(0x4B4, 0x168, 2, 0x0, 0, 0)
610#define _MX53_PAD_EIM_A21__IPU_CSI1_D_16 IOMUX_PAD(0x4B4, 0x168, 3, 0x0, 0, 0)
611#define _MX53_PAD_EIM_A21__SRC_BT_CFG1_6 IOMUX_PAD(0x4B4, 0x168, 7, 0x0, 0, 0)
612#define _MX53_PAD_EIM_A20__EMI_WEIM_A_20 IOMUX_PAD(0x4B8, 0x16C, 0, 0x0, 0, 0)
613#define _MX53_PAD_EIM_A20__GPIO2_18 IOMUX_PAD(0x4B8, 0x16C, 1, 0x0, 0, 0)
614#define _MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 IOMUX_PAD(0x4B8, 0x16C, 2, 0x0, 0, 0)
615#define _MX53_PAD_EIM_A20__IPU_CSI1_D_15 IOMUX_PAD(0x4B8, 0x16C, 3, 0x0, 0, 0)
616#define _MX53_PAD_EIM_A20__SRC_BT_CFG1_5 IOMUX_PAD(0x4B8, 0x16C, 7, 0x0, 0, 0)
617#define _MX53_PAD_EIM_A19__EMI_WEIM_A_19 IOMUX_PAD(0x4BC, 0x170, 0, 0x0, 0, 0)
618#define _MX53_PAD_EIM_A19__GPIO2_19 IOMUX_PAD(0x4BC, 0x170, 1, 0x0, 0, 0)
619#define _MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 IOMUX_PAD(0x4BC, 0x170, 2, 0x0, 0, 0)
620#define _MX53_PAD_EIM_A19__IPU_CSI1_D_14 IOMUX_PAD(0x4BC, 0x170, 3, 0x0, 0, 0)
621#define _MX53_PAD_EIM_A19__SRC_BT_CFG1_4 IOMUX_PAD(0x4BC, 0x170, 7, 0x0, 0, 0)
622#define _MX53_PAD_EIM_A18__EMI_WEIM_A_18 IOMUX_PAD(0x4C0, 0x174, 0, 0x0, 0, 0)
623#define _MX53_PAD_EIM_A18__GPIO2_20 IOMUX_PAD(0x4C0, 0x174, 1, 0x0, 0, 0)
624#define _MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 IOMUX_PAD(0x4C0, 0x174, 2, 0x0, 0, 0)
625#define _MX53_PAD_EIM_A18__IPU_CSI1_D_13 IOMUX_PAD(0x4C0, 0x174, 3, 0x0, 0, 0)
626#define _MX53_PAD_EIM_A18__SRC_BT_CFG1_3 IOMUX_PAD(0x4C0, 0x174, 7, 0x0, 0, 0)
627#define _MX53_PAD_EIM_A17__EMI_WEIM_A_17 IOMUX_PAD(0x4C4, 0x178, 0, 0x0, 0, 0)
628#define _MX53_PAD_EIM_A17__GPIO2_21 IOMUX_PAD(0x4C4, 0x178, 1, 0x0, 0, 0)
629#define _MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 IOMUX_PAD(0x4C4, 0x178, 2, 0x0, 0, 0)
630#define _MX53_PAD_EIM_A17__IPU_CSI1_D_12 IOMUX_PAD(0x4C4, 0x178, 3, 0x0, 0, 0)
631#define _MX53_PAD_EIM_A17__SRC_BT_CFG1_2 IOMUX_PAD(0x4C4, 0x178, 7, 0x0, 0, 0)
632#define _MX53_PAD_EIM_A16__EMI_WEIM_A_16 IOMUX_PAD(0x4C8, 0x17C, 0, 0x0, 0, 0)
633#define _MX53_PAD_EIM_A16__GPIO2_22 IOMUX_PAD(0x4C8, 0x17C, 1, 0x0, 0, 0)
634#define _MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK IOMUX_PAD(0x4C8, 0x17C, 2, 0x0, 0, 0)
635#define _MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK IOMUX_PAD(0x4C8, 0x17C, 3, 0x0, 0, 0)
636#define _MX53_PAD_EIM_A16__SRC_BT_CFG1_1 IOMUX_PAD(0x4C8, 0x17C, 7, 0x0, 0, 0)
637#define _MX53_PAD_EIM_CS0__EMI_WEIM_CS_0 IOMUX_PAD(0x4CC, 0x180, 0, 0x0, 0, 0)
638#define _MX53_PAD_EIM_CS0__GPIO2_23 IOMUX_PAD(0x4CC, 0x180, 1, 0x0, 0, 0)
639#define _MX53_PAD_EIM_CS0__ECSPI2_SCLK IOMUX_PAD(0x4CC, 0x180, 2, 0x7B8, 2, 0)
640#define _MX53_PAD_EIM_CS0__IPU_DI1_PIN5 IOMUX_PAD(0x4CC, 0x180, 3, 0x0, 0, 0)
641#define _MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 IOMUX_PAD(0x4D0, 0x184, 0, 0x0, 0, 0)
642#define _MX53_PAD_EIM_CS1__GPIO2_24 IOMUX_PAD(0x4D0, 0x184, 1, 0x0, 0, 0)
643#define _MX53_PAD_EIM_CS1__ECSPI2_MOSI IOMUX_PAD(0x4D0, 0x184, 2, 0x7C0, 2, 0)
644#define _MX53_PAD_EIM_CS1__IPU_DI1_PIN6 IOMUX_PAD(0x4D0, 0x184, 3, 0x0, 0, 0)
645#define _MX53_PAD_EIM_OE__EMI_WEIM_OE IOMUX_PAD(0x4D4, 0x188, 0, 0x0, 0, 0)
646#define _MX53_PAD_EIM_OE__GPIO2_25 IOMUX_PAD(0x4D4, 0x188, 1, 0x0, 0, 0)
647#define _MX53_PAD_EIM_OE__ECSPI2_MISO IOMUX_PAD(0x4D4, 0x188, 2, 0x7BC, 2, 0)
648#define _MX53_PAD_EIM_OE__IPU_DI1_PIN7 IOMUX_PAD(0x4D4, 0x188, 3, 0x0, 0, 0)
649#define _MX53_PAD_EIM_OE__USBPHY2_IDDIG IOMUX_PAD(0x4D4, 0x188, 7, 0x0, 0, 0)
650#define _MX53_PAD_EIM_RW__EMI_WEIM_RW IOMUX_PAD(0x4D8, 0x18C, 0, 0x0, 0, 0)
651#define _MX53_PAD_EIM_RW__GPIO2_26 IOMUX_PAD(0x4D8, 0x18C, 1, 0x0, 0, 0)
652#define _MX53_PAD_EIM_RW__ECSPI2_SS0 IOMUX_PAD(0x4D8, 0x18C, 2, 0x7C4, 2, 0)
653#define _MX53_PAD_EIM_RW__IPU_DI1_PIN8 IOMUX_PAD(0x4D8, 0x18C, 3, 0x0, 0, 0)
654#define _MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT IOMUX_PAD(0x4D8, 0x18C, 7, 0x0, 0, 0)
655#define _MX53_PAD_EIM_LBA__EMI_WEIM_LBA IOMUX_PAD(0x4DC, 0x190, 0, 0x0, 0, 0)
656#define _MX53_PAD_EIM_LBA__GPIO2_27 IOMUX_PAD(0x4DC, 0x190, 1, 0x0, 0, 0)
657#define _MX53_PAD_EIM_LBA__ECSPI2_SS1 IOMUX_PAD(0x4DC, 0x190, 2, 0x7C8, 1, 0)
658#define _MX53_PAD_EIM_LBA__IPU_DI1_PIN17 IOMUX_PAD(0x4DC, 0x190, 3, 0x0, 0, 0)
659#define _MX53_PAD_EIM_LBA__SRC_BT_CFG1_0 IOMUX_PAD(0x4DC, 0x190, 7, 0x0, 0, 0)
660#define _MX53_PAD_EIM_EB0__EMI_WEIM_EB_0 IOMUX_PAD(0x4E4, 0x194, 0, 0x0, 0, 0)
661#define _MX53_PAD_EIM_EB0__GPIO2_28 IOMUX_PAD(0x4E4, 0x194, 1, 0x0, 0, 0)
662#define _MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 IOMUX_PAD(0x4E4, 0x194, 3, 0x0, 0, 0)
663#define _MX53_PAD_EIM_EB0__IPU_CSI1_D_11 IOMUX_PAD(0x4E4, 0x194, 4, 0x0, 0, 0)
664#define _MX53_PAD_EIM_EB0__GPC_PMIC_RDY IOMUX_PAD(0x4E4, 0x194, 5, 0x810, 0, 0)
665#define _MX53_PAD_EIM_EB0__SRC_BT_CFG2_7 IOMUX_PAD(0x4E4, 0x194, 7, 0x0, 0, 0)
666#define _MX53_PAD_EIM_EB1__EMI_WEIM_EB_1 IOMUX_PAD(0x4E8, 0x198, 0, 0x0, 0, 0)
667#define _MX53_PAD_EIM_EB1__GPIO2_29 IOMUX_PAD(0x4E8, 0x198, 1, 0x0, 0, 0)
668#define _MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 IOMUX_PAD(0x4E8, 0x198, 3, 0x0, 0, 0)
669#define _MX53_PAD_EIM_EB1__IPU_CSI1_D_10 IOMUX_PAD(0x4E8, 0x198, 4, 0x0, 0, 0)
670#define _MX53_PAD_EIM_EB1__SRC_BT_CFG2_6 IOMUX_PAD(0x4E8, 0x198, 7, 0x0, 0, 0)
671#define _MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 IOMUX_PAD(0x4EC, 0x19C, 0, 0x0, 0, 0)
672#define _MX53_PAD_EIM_DA0__GPIO3_0 IOMUX_PAD(0x4EC, 0x19C, 1, 0x0, 0, 0)
673#define _MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 IOMUX_PAD(0x4EC, 0x19C, 3, 0x0, 0, 0)
674#define _MX53_PAD_EIM_DA0__IPU_CSI1_D_9 IOMUX_PAD(0x4EC, 0x19C, 4, 0x0, 0, 0)
675#define _MX53_PAD_EIM_DA0__SRC_BT_CFG2_5 IOMUX_PAD(0x4EC, 0x19C, 7, 0x0, 0, 0)
676#define _MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 IOMUX_PAD(0x4F0, 0x1A0, 0, 0x0, 0, 0)
677#define _MX53_PAD_EIM_DA1__GPIO3_1 IOMUX_PAD(0x4F0, 0x1A0, 1, 0x0, 0, 0)
678#define _MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 IOMUX_PAD(0x4F0, 0x1A0, 3, 0x0, 0, 0)
679#define _MX53_PAD_EIM_DA1__IPU_CSI1_D_8 IOMUX_PAD(0x4F0, 0x1A0, 4, 0x0, 0, 0)
680#define _MX53_PAD_EIM_DA1__SRC_BT_CFG2_4 IOMUX_PAD(0x4F0, 0x1A0, 7, 0x0, 0, 0)
681#define _MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 IOMUX_PAD(0x4F4, 0x1A4, 0, 0x0, 0, 0)
682#define _MX53_PAD_EIM_DA2__GPIO3_2 IOMUX_PAD(0x4F4, 0x1A4, 1, 0x0, 0, 0)
683#define _MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 IOMUX_PAD(0x4F4, 0x1A4, 3, 0x0, 0, 0)
684#define _MX53_PAD_EIM_DA2__IPU_CSI1_D_7 IOMUX_PAD(0x4F4, 0x1A4, 4, 0x0, 0, 0)
685#define _MX53_PAD_EIM_DA2__SRC_BT_CFG2_3 IOMUX_PAD(0x4F4, 0x1A4, 7, 0x0, 0, 0)
686#define _MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 IOMUX_PAD(0x4F8, 0x1A8, 0, 0x0, 0, 0)
687#define _MX53_PAD_EIM_DA3__GPIO3_3 IOMUX_PAD(0x4F8, 0x1A8, 1, 0x0, 0, 0)
688#define _MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 IOMUX_PAD(0x4F8, 0x1A8, 3, 0x0, 0, 0)
689#define _MX53_PAD_EIM_DA3__IPU_CSI1_D_6 IOMUX_PAD(0x4F8, 0x1A8, 4, 0x0, 0, 0)
690#define _MX53_PAD_EIM_DA3__SRC_BT_CFG2_2 IOMUX_PAD(0x4F8, 0x1A8, 7, 0x0, 0, 0)
691#define _MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 IOMUX_PAD(0x4FC, 0x1AC, 0, 0x0, 0, 0)
692#define _MX53_PAD_EIM_DA4__GPIO3_4 IOMUX_PAD(0x4FC, 0x1AC, 1, 0x0, 0, 0)
693#define _MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 IOMUX_PAD(0x4FC, 0x1AC, 3, 0x0, 0, 0)
694#define _MX53_PAD_EIM_DA4__IPU_CSI1_D_5 IOMUX_PAD(0x4FC, 0x1AC, 4, 0x0, 0, 0)
695#define _MX53_PAD_EIM_DA4__SRC_BT_CFG3_7 IOMUX_PAD(0x4FC, 0x1AC, 7, 0x0, 0, 0)
696#define _MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 IOMUX_PAD(0x500, 0x1B0, 0, 0x0, 0, 0)
697#define _MX53_PAD_EIM_DA5__GPIO3_5 IOMUX_PAD(0x500, 0x1B0, 1, 0x0, 0, 0)
698#define _MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 IOMUX_PAD(0x500, 0x1B0, 3, 0x0, 0, 0)
699#define _MX53_PAD_EIM_DA5__IPU_CSI1_D_4 IOMUX_PAD(0x500, 0x1B0, 4, 0x0, 0, 0)
700#define _MX53_PAD_EIM_DA5__SRC_BT_CFG3_6 IOMUX_PAD(0x500, 0x1B0, 17, 0x0, 0, 0)
701#define _MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 IOMUX_PAD(0x504, 0x1B4, 0, 0x0, 0, 0)
702#define _MX53_PAD_EIM_DA6__GPIO3_6 IOMUX_PAD(0x504, 0x1B4, 1, 0x0, 0, 0)
703#define _MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 IOMUX_PAD(0x504, 0x1B4, 3, 0x0, 0, 0)
704#define _MX53_PAD_EIM_DA6__IPU_CSI1_D_3 IOMUX_PAD(0x504, 0x1B4, 4, 0x0, 0, 0)
705#define _MX53_PAD_EIM_DA6__SRC_BT_CFG3_5 IOMUX_PAD(0x504, 0x1B4, 7, 0x0, 0, 0)
706#define _MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 IOMUX_PAD(0x508, 0x1B8, 0, 0x0, 0, 0)
707#define _MX53_PAD_EIM_DA7__GPIO3_7 IOMUX_PAD(0x508, 0x1B8, 1, 0x0, 0, 0)
708#define _MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 IOMUX_PAD(0x508, 0x1B8, 3, 0x0, 0, 0)
709#define _MX53_PAD_EIM_DA7__IPU_CSI1_D_2 IOMUX_PAD(0x508, 0x1B8, 4, 0x0, 0, 0)
710#define _MX53_PAD_EIM_DA7__SRC_BT_CFG3_4 IOMUX_PAD(0x508, 0x1B8, 7, 0x0, 0, 0)
711#define _MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8 IOMUX_PAD(0x50C, 0x1BC, 0, 0x0, 0, 0)
712#define _MX53_PAD_EIM_DA8__GPIO3_8 IOMUX_PAD(0x50C, 0x1BC, 1, 0x0, 0, 0)
713#define _MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 IOMUX_PAD(0x50C, 0x1BC, 3, 0x0, 0, 0)
714#define _MX53_PAD_EIM_DA8__IPU_CSI1_D_1 IOMUX_PAD(0x50C, 0x1BC, 4, 0x0, 0, 0)
715#define _MX53_PAD_EIM_DA8__SRC_BT_CFG3_3 IOMUX_PAD(0x50C, 0x1BC, 7, 0x0, 0, 0)
716#define _MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9 IOMUX_PAD(0x510, 0x1C0, 0, 0x0, 0, 0)
717#define _MX53_PAD_EIM_DA9__GPIO3_9 IOMUX_PAD(0x510, 0x1C0, 1, 0x0, 0, 0)
718#define _MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 IOMUX_PAD(0x510, 0x1C0, 3, 0x0, 0, 0)
719#define _MX53_PAD_EIM_DA9__IPU_CSI1_D_0 IOMUX_PAD(0x510, 0x1C0, 4, 0x0, 0, 0)
720#define _MX53_PAD_EIM_DA9__SRC_BT_CFG3_2 IOMUX_PAD(0x510, 0x1C0, 7, 0x0, 0, 0)
721#define _MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10 IOMUX_PAD(0x514, 0x1C4, 0, 0x0, 0, 0)
722#define _MX53_PAD_EIM_DA10__GPIO3_10 IOMUX_PAD(0x514, 0x1C4, 1, 0x0, 0, 0)
723#define _MX53_PAD_EIM_DA10__IPU_DI1_PIN15 IOMUX_PAD(0x514, 0x1C4, 3, 0x0, 0, 0)
724#define _MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN IOMUX_PAD(0x514, 0x1C4, 4, 0x834, 1, 0)
725#define _MX53_PAD_EIM_DA10__SRC_BT_CFG3_1 IOMUX_PAD(0x514, 0x1C4, 7, 0x0, 0, 0)
726#define _MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11 IOMUX_PAD(0x518, 0x1C8, 0, 0x0, 0, 0)
727#define _MX53_PAD_EIM_DA11__GPIO3_11 IOMUX_PAD(0x518, 0x1C8, 1, 0x0, 0, 0)
728#define _MX53_PAD_EIM_DA11__IPU_DI1_PIN2 IOMUX_PAD(0x518, 0x1C8, 3, 0x0, 0, 0)
729#define _MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC IOMUX_PAD(0x518, 0x1C8, 4, 0x838, 1, 0)
730#define _MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12 IOMUX_PAD(0x51C, 0x1CC, 0, 0x0, 0, 0)
731#define _MX53_PAD_EIM_DA12__GPIO3_12 IOMUX_PAD(0x51C, 0x1CC, 1, 0x0, 0, 0)
732#define _MX53_PAD_EIM_DA12__IPU_DI1_PIN3 IOMUX_PAD(0x51C, 0x1CC, 3, 0x0, 0, 0)
733#define _MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC IOMUX_PAD(0x51C, 0x1CC, 4, 0x83C, 1, 0)
734#define _MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13 IOMUX_PAD(0x520, 0x1D0, 0, 0x0, 0, 0)
735#define _MX53_PAD_EIM_DA13__GPIO3_13 IOMUX_PAD(0x520, 0x1D0, 1, 0x0, 0, 0)
736#define _MX53_PAD_EIM_DA13__IPU_DI1_D0_CS IOMUX_PAD(0x520, 0x1D0, 3, 0x0, 0, 0)
737#define _MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK IOMUX_PAD(0x520, 0x1D0, 4, 0x76C, 1, 0)
738#define _MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14 IOMUX_PAD(0x524, 0x1D4, 0, 0x0, 0, 0)
739#define _MX53_PAD_EIM_DA14__GPIO3_14 IOMUX_PAD(0x524, 0x1D4, 1, 0x0, 0, 0)
740#define _MX53_PAD_EIM_DA14__IPU_DI1_D1_CS IOMUX_PAD(0x524, 0x1D4, 3, 0x0, 0, 0)
741#define _MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK IOMUX_PAD(0x524, 0x1D4, 4, 0x0, 0, 0)
742#define _MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15 IOMUX_PAD(0x528, 0x1D8, 0, 0x0, 0, 0)
743#define _MX53_PAD_EIM_DA15__GPIO3_15 IOMUX_PAD(0x528, 0x1D8, 1, 0x0, 0, 0)
744#define _MX53_PAD_EIM_DA15__IPU_DI1_PIN1 IOMUX_PAD(0x528, 0x1D8, 3, 0x0, 0, 0)
745#define _MX53_PAD_EIM_DA15__IPU_DI1_PIN4 IOMUX_PAD(0x528, 0x1D8, 4, 0x0, 0, 0)
746#define _MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B IOMUX_PAD(0x52C, 0x1DC, 0, 0x0, 0, 0)
747#define _MX53_PAD_NANDF_WE_B__GPIO6_12 IOMUX_PAD(0x52C, 0x1DC, 1, 0x0, 0, 0)
748#define _MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B IOMUX_PAD(0x530, 0x1E0, 0, 0x0, 0, 0)
749#define _MX53_PAD_NANDF_RE_B__GPIO6_13 IOMUX_PAD(0x530, 0x1E0, 1, 0x0, 0, 0)
750#define _MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT IOMUX_PAD(0x534, 0x1E4, 0, 0x0, 0, 0)
751#define _MX53_PAD_EIM_WAIT__GPIO5_0 IOMUX_PAD(0x534, 0x1E4, 1, 0x0, 0, 0)
752#define _MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B IOMUX_PAD(0x534, 0x1E4, 2, 0x0, 0, 0)
753#define _MX53_PAD_LVDS1_TX3_P__GPIO6_22 IOMUX_PAD(NON_PAD_I, 0x1EC, 0, 0x0, 0, 0)
754#define _MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 IOMUX_PAD(NON_PAD_I, 0x1EC, 1, 0x0, 0, 0)
755#define _MX53_PAD_LVDS1_TX2_P__GPIO6_24 IOMUX_PAD(NON_PAD_I, 0x1F0, 0, 0x0, 0, 0)
756#define _MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 IOMUX_PAD(NON_PAD_I, 0x1F0, 1, 0x0, 0, 0)
757#define _MX53_PAD_LVDS1_CLK_P__GPIO6_26 IOMUX_PAD(NON_PAD_I, 0x1F4, 0, 0x0, 0, 0)
758#define _MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK IOMUX_PAD(NON_PAD_I, 0x1F4, 1, 0x0, 0, 0)
759#define _MX53_PAD_LVDS1_TX1_P__GPIO6_28 IOMUX_PAD(NON_PAD_I, 0x1F8, 0, 0x0, 0, 0)
760#define _MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 IOMUX_PAD(NON_PAD_I, 0x1F8, 1, 0x0, 0, 0)
761#define _MX53_PAD_LVDS1_TX0_P__GPIO6_30 IOMUX_PAD(NON_PAD_I, 0x1FC, 0, 0x0, 0, 0)
762#define _MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 IOMUX_PAD(NON_PAD_I, 0x1FC, 1, 0x0, 0, 0)
763#define _MX53_PAD_LVDS0_TX3_P__GPIO7_22 IOMUX_PAD(NON_PAD_I, 0x200, 0, 0x0, 0, 0)
764#define _MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 IOMUX_PAD(NON_PAD_I, 0x200, 1, 0x0, 0, 0)
765#define _MX53_PAD_LVDS0_CLK_P__GPIO7_24 IOMUX_PAD(NON_PAD_I, 0x204, 0, 0x0, 0, 0)
766#define _MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK IOMUX_PAD(NON_PAD_I, 0x204, 1, 0x0, 0, 0)
767#define _MX53_PAD_LVDS0_TX2_P__GPIO7_26 IOMUX_PAD(NON_PAD_I, 0x208, 0, 0x0, 0, 0)
768#define _MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 IOMUX_PAD(NON_PAD_I, 0x208, 1, 0x0, 0, 0)
769#define _MX53_PAD_LVDS0_TX1_P__GPIO7_28 IOMUX_PAD(NON_PAD_I, 0x20C, 0, 0x0, 0, 0)
770#define _MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 IOMUX_PAD(NON_PAD_I, 0x20C, 1, 0x0, 0, 0)
771#define _MX53_PAD_LVDS0_TX0_P__GPIO7_30 IOMUX_PAD(NON_PAD_I, 0x210, 0, 0x0, 0, 0)
772#define _MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 IOMUX_PAD(NON_PAD_I, 0x210, 1, 0x0, 0, 0)
773#define _MX53_PAD_GPIO_10__GPIO4_0 IOMUX_PAD(0x540, 0x214, 0, 0x0, 0, 0)
774#define _MX53_PAD_GPIO_10__OSC32k_32K_OUT IOMUX_PAD(0x540, 0x214, 1, 0x0, 0, 0)
775#define _MX53_PAD_GPIO_11__GPIO4_1 IOMUX_PAD(0x544, 0x218, 0, 0x0, 0, 0)
776#define _MX53_PAD_GPIO_12__GPIO4_2 IOMUX_PAD(0x548, 0x21C, 0, 0x0, 0, 0)
777#define _MX53_PAD_GPIO_13__GPIO4_3 IOMUX_PAD(0x54C, 0x220, 0, 0x0, 0, 0)
778#define _MX53_PAD_GPIO_14__GPIO4_4 IOMUX_PAD(0x550, 0x224, 0, 0x0, 0, 0)
779#define _MX53_PAD_NANDF_CLE__EMI_NANDF_CLE IOMUX_PAD(0x5A0, 0x228, 0, 0x0, 0, 0)
780#define _MX53_PAD_NANDF_CLE__GPIO6_7 IOMUX_PAD(0x5A0, 0x228, 1, 0x0, 0, 0)
781#define _MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0 IOMUX_PAD(0x5A0, 0x228, 7, 0x0, 0, 0)
782#define _MX53_PAD_NANDF_ALE__EMI_NANDF_ALE IOMUX_PAD(0x5A4, 0x22C, 0, 0x0, 0, 0)
783#define _MX53_PAD_NANDF_ALE__GPIO6_8 IOMUX_PAD(0x5A4, 0x22C, 1, 0x0, 0, 0)
784#define _MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1 IOMUX_PAD(0x5A4, 0x22C, 7, 0x0, 0, 0)
785#define _MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B IOMUX_PAD(0x5A8, 0x230, 0, 0x0, 0, 0)
786#define _MX53_PAD_NANDF_WP_B__GPIO6_9 IOMUX_PAD(0x5A8, 0x230, 1, 0x0, 0, 0)
787#define _MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2 IOMUX_PAD(0x5A8, 0x230, 7, 0x0, 0, 0)
788#define _MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 IOMUX_PAD(0x5AC, 0x234, 0, 0x0, 0, 0)
789#define _MX53_PAD_NANDF_RB0__GPIO6_10 IOMUX_PAD(0x5AC, 0x234, 1, 0x0, 0, 0)
790#define _MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3 IOMUX_PAD(0x5AC, 0x234, 7, 0x0, 0, 0)
791#define _MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 IOMUX_PAD(0x5B0, 0x238, 0, 0x0, 0, 0)
792#define _MX53_PAD_NANDF_CS0__GPIO6_11 IOMUX_PAD(0x5B0, 0x238, 1, 0x0, 0, 0)
793#define _MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4 IOMUX_PAD(0x5B0, 0x238, 7, 0x0, 0, 0)
794#define _MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1 IOMUX_PAD(0x5B4, 0x23C, 0, 0x0, 0, 0)
795#define _MX53_PAD_NANDF_CS1__GPIO6_14 IOMUX_PAD(0x5B4, 0x23C, 1, 0x0, 0, 0)
796#define _MX53_PAD_NANDF_CS1__MLB_MLBCLK IOMUX_PAD(0x5B4, 0x23C, 6, 0x858, 0, 0)
797#define _MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5 IOMUX_PAD(0x5B4, 0x23C, 7, 0x0, 0, 0)
798#define _MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2 IOMUX_PAD(0x5B8, 0x240, 0, 0x0, 0, 0)
799#define _MX53_PAD_NANDF_CS2__GPIO6_15 IOMUX_PAD(0x5B8, 0x240, 1, 0x0, 0, 0)
800#define _MX53_PAD_NANDF_CS2__IPU_SISG_0 IOMUX_PAD(0x5B8, 0x240, 2, 0x0, 0, 0)
801#define _MX53_PAD_NANDF_CS2__ESAI1_TX0 IOMUX_PAD(0x5B8, 0x240, 3, 0x7E4, 0, 0)
802#define _MX53_PAD_NANDF_CS2__EMI_WEIM_CRE IOMUX_PAD(0x5B8, 0x240, 4, 0x0, 0, 0)
803#define _MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK IOMUX_PAD(0x5B8, 0x240, 5, 0x0, 0, 0)
804#define _MX53_PAD_NANDF_CS2__MLB_MLBSIG IOMUX_PAD(0x5B8, 0x240, 6, 0x860, 0, 0)
805#define _MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6 IOMUX_PAD(0x5B8, 0x240, 7, 0x0, 0, 0)
806#define _MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3 IOMUX_PAD(0x5BC, 0x244, 0, 0x0, 0, 0)
807#define _MX53_PAD_NANDF_CS3__GPIO6_16 IOMUX_PAD(0x5BC, 0x244, 1, 0x0, 0, 0)
808#define _MX53_PAD_NANDF_CS3__IPU_SISG_1 IOMUX_PAD(0x5BC, 0x244, 2, 0x0, 0, 0)
809#define _MX53_PAD_NANDF_CS3__ESAI1_TX1 IOMUX_PAD(0x5BC, 0x244, 3, 0x7E8, 0, 0)
810#define _MX53_PAD_NANDF_CS3__EMI_WEIM_A_26 IOMUX_PAD(0x5BC, 0x244, 4, 0x0, 0, 0)
811#define _MX53_PAD_NANDF_CS3__MLB_MLBDAT IOMUX_PAD(0x5BC, 0x244, 6, 0x85C, 0, 0)
812#define _MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7 IOMUX_PAD(0x5BC, 0x244, 7, 0x0, 0, 0)
813#define _MX53_PAD_FEC_MDIO__FEC_MDIO IOMUX_PAD(0x5C4, 0x248, 0, 0x804, 1, 0)
814#define _MX53_PAD_FEC_MDIO__GPIO1_22 IOMUX_PAD(0x5C4, 0x248, 1, 0x0, 0, 0)
815#define _MX53_PAD_FEC_MDIO__ESAI1_SCKR IOMUX_PAD(0x5C4, 0x248, 2, 0x7DC, 0, 0)
816#define _MX53_PAD_FEC_MDIO__FEC_COL IOMUX_PAD(0x5C4, 0x248, 3, 0x800, 1, 0)
817#define _MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2 IOMUX_PAD(0x5C4, 0x248, 4, 0x0, 0, 0)
818#define _MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3 IOMUX_PAD(0x5C4, 0x248, 5, 0x0, 0, 0)
819#define _MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49 IOMUX_PAD(0x5C4, 0x248, 6, 0x0, 0, 0)
820#define _MX53_PAD_FEC_REF_CLK__FEC_TX_CLK IOMUX_PAD(0x5C8, 0x24C, 0, 0x0, 0, 0)
821#define _MX53_PAD_FEC_REF_CLK__GPIO1_23 IOMUX_PAD(0x5C8, 0x24C, 1, 0x0, 0, 0)
822#define _MX53_PAD_FEC_REF_CLK__ESAI1_FSR IOMUX_PAD(0x5C8, 0x24C, 2, 0x7CC, 0, 0)
823#define _MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 IOMUX_PAD(0x5C8, 0x24C, 5, 0x0, 0, 0)
824#define _MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50 IOMUX_PAD(0x5C8, 0x24C, 6, 0x0, 0, 0)
825#define _MX53_PAD_FEC_RX_ER__FEC_RX_ER IOMUX_PAD(0x5CC, 0x250, 0, 0x0, 0, 0)
826#define _MX53_PAD_FEC_RX_ER__GPIO1_24 IOMUX_PAD(0x5CC, 0x250, 1, 0x0, 0, 0)
827#define _MX53_PAD_FEC_RX_ER__ESAI1_HCKR IOMUX_PAD(0x5CC, 0x250, 2, 0x7D4, 0, 0)
828#define _MX53_PAD_FEC_RX_ER__FEC_RX_CLK IOMUX_PAD(0x5CC, 0x250, 3, 0x808, 1, 0)
829#define _MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3 IOMUX_PAD(0x5CC, 0x250, 4, 0x0, 0, 0)
830#define _MX53_PAD_FEC_CRS_DV__FEC_RX_DV IOMUX_PAD(0x5D0, 0x254, 0, 0x0, 0, 0)
831#define _MX53_PAD_FEC_CRS_DV__GPIO1_25 IOMUX_PAD(0x5D0, 0x254, 1, 0x0, 0, 0)
832#define _MX53_PAD_FEC_CRS_DV__ESAI1_SCKT IOMUX_PAD(0x5D0, 0x254, 2, 0x7E0, 0, 0)
833#define _MX53_PAD_FEC_RXD1__FEC_RDATA_1 IOMUX_PAD(0x5D4, 0x258, 0, 0x0, 0, 0)
834#define _MX53_PAD_FEC_RXD1__GPIO1_26 IOMUX_PAD(0x5D4, 0x258, 1, 0x0, 0, 0)
835#define _MX53_PAD_FEC_RXD1__ESAI1_FST IOMUX_PAD(0x5D4, 0x258, 2, 0x7D0, 0, 0)
836#define _MX53_PAD_FEC_RXD1__MLB_MLBSIG IOMUX_PAD(0x5D4, 0x258, 3, 0x860, 1, 0)
837#define _MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1 IOMUX_PAD(0x5D4, 0x258, 4, 0x0, 0, 0)
838#define _MX53_PAD_FEC_RXD0__FEC_RDATA_0 IOMUX_PAD(0x5D8, 0x25C, 0, 0x0, 0, 0)
839#define _MX53_PAD_FEC_RXD0__GPIO1_27 IOMUX_PAD(0x5D8, 0x25C, 1, 0x0, 0, 0)
840#define _MX53_PAD_FEC_RXD0__ESAI1_HCKT IOMUX_PAD(0x5D8, 0x25C, 2, 0x7D8, 0, 0)
841#define _MX53_PAD_FEC_RXD0__OSC32k_32K_OUT IOMUX_PAD(0x5D8, 0x25C, 3, 0x0, 0, 0)
842#define _MX53_PAD_FEC_TX_EN__FEC_TX_EN IOMUX_PAD(0x5DC, 0x260, 0, 0x0, 0, 0)
843#define _MX53_PAD_FEC_TX_EN__GPIO1_28 IOMUX_PAD(0x5DC, 0x260, 1, 0x0, 0, 0)
844#define _MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2 IOMUX_PAD(0x5DC, 0x260, 2, 0x7F0, 0, 0)
845#define _MX53_PAD_FEC_TXD1__FEC_TDATA_1 IOMUX_PAD(0x5E0, 0x264, 0, 0x0, 0, 0)
846#define _MX53_PAD_FEC_TXD1__GPIO1_29 IOMUX_PAD(0x5E0, 0x264, 1, 0x0, 0, 0)
847#define _MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3 IOMUX_PAD(0x5E0, 0x264, 2, 0x7EC, 0, 0)
848#define _MX53_PAD_FEC_TXD1__MLB_MLBCLK IOMUX_PAD(0x5E0, 0x264, 3, 0x858, 1, 0)
849#define _MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK IOMUX_PAD(0x5E0, 0x264, 4, 0x0, 0, 0)
850#define _MX53_PAD_FEC_TXD0__FEC_TDATA_0 IOMUX_PAD(0x5E4, 0x268, 0, 0x0, 0, 0)
851#define _MX53_PAD_FEC_TXD0__GPIO1_30 IOMUX_PAD(0x5E4, 0x268, 1, 0x0, 0, 0)
852#define _MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1 IOMUX_PAD(0x5E4, 0x268, 2, 0x7F4, 0, 0)
853#define _MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0 IOMUX_PAD(0x5E4, 0x268, 7, 0x0, 0, 0)
854#define _MX53_PAD_FEC_MDC__FEC_MDC IOMUX_PAD(0x5E8, 0x26C, 0, 0x0, 0, 0)
855#define _MX53_PAD_FEC_MDC__GPIO1_31 IOMUX_PAD(0x5E8, 0x26C, 1, 0x0, 0, 0)
856#define _MX53_PAD_FEC_MDC__ESAI1_TX5_RX0 IOMUX_PAD(0x5E8, 0x26C, 2, 0x7F8, 0, 0)
857#define _MX53_PAD_FEC_MDC__MLB_MLBDAT IOMUX_PAD(0x5E8, 0x26C, 3, 0x85C, 1, 0)
858#define _MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG IOMUX_PAD(0x5E8, 0x26C, 4, 0x0, 0, 0)
859#define _MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1 IOMUX_PAD(0x5E8, 0x26C, 7, 0x0, 0, 0)
860#define _MX53_PAD_PATA_DIOW__PATA_DIOW IOMUX_PAD(0x5F0, 0x270, 0, 0x0, 0, 0)
861#define _MX53_PAD_PATA_DIOW__GPIO6_17 IOMUX_PAD(0x5F0, 0x270, 1, 0x0, 0, 0)
862#define _MX53_PAD_PATA_DIOW__UART1_TXD_MUX IOMUX_PAD(0x5F0, 0x270, 3, 0x878, 2, 0)
863#define _MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2 IOMUX_PAD(0x5F0, 0x270, 7, 0x0, 0, 0)
864#define _MX53_PAD_PATA_DMACK__PATA_DMACK IOMUX_PAD(0x5F4, 0x274, 0, 0x0, 0, 0)
865#define _MX53_PAD_PATA_DMACK__GPIO6_18 IOMUX_PAD(0x5F4, 0x274, 1, 0x0, 0, 0)
866#define _MX53_PAD_PATA_DMACK__UART1_RXD_MUX IOMUX_PAD(0x5F4, 0x274, 3, 0x878, 3, 0)
867#define _MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3 IOMUX_PAD(0x5F4, 0x274, 7, 0x0, 0, 0)
868#define _MX53_PAD_PATA_DMARQ__PATA_DMARQ IOMUX_PAD(0x5F8, 0x278, 0, 0x0, 0, 0)
869#define _MX53_PAD_PATA_DMARQ__GPIO7_0 IOMUX_PAD(0x5F8, 0x278, 1, 0x0, 0, 0)
870#define _MX53_PAD_PATA_DMARQ__UART2_TXD_MUX IOMUX_PAD(0x5F8, 0x278, 3, 0x880, 2, 0)
871#define _MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0 IOMUX_PAD(0x5F8, 0x278, 5, 0x0, 0, 0)
872#define _MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4 IOMUX_PAD(0x5F8, 0x278, 7, 0x0, 0, 0)
873#define _MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN IOMUX_PAD(0x5FC, 0x27C, 0, 0x0, 0, 0)
874#define _MX53_PAD_PATA_BUFFER_EN__GPIO7_1 IOMUX_PAD(0x5FC, 0x27C, 1, 0x0, 0, 0)
875#define _MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX IOMUX_PAD(0x5FC, 0x27C, 3, 0x880, 3, 0)
876#define _MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1 IOMUX_PAD(0x5FC, 0x27C, 5, 0x0, 0, 0)
877#define _MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5 IOMUX_PAD(0x5FC, 0x27C, 7, 0x0, 0, 0)
878#define _MX53_PAD_PATA_INTRQ__PATA_INTRQ IOMUX_PAD(0x600, 0x280, 0, 0x0, 0, 0)
879#define _MX53_PAD_PATA_INTRQ__GPIO7_2 IOMUX_PAD(0x600, 0x280, 1, 0x0, 0, 0)
880#define _MX53_PAD_PATA_INTRQ__UART2_CTS IOMUX_PAD(0x600, 0x280, 3, 0x87C, 2, 0)
881#define _MX53_PAD_PATA_INTRQ__CAN1_TXCAN IOMUX_PAD(0x600, 0x280, 4, 0x0, 0, 0)
882#define _MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2 IOMUX_PAD(0x600, 0x280, 5, 0x0, 0, 0)
883#define _MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6 IOMUX_PAD(0x600, 0x280, 7, 0x0, 0, 0)
884#define _MX53_PAD_PATA_DIOR__PATA_DIOR IOMUX_PAD(0x604, 0x284, 0, 0x0, 0, 0)
885#define _MX53_PAD_PATA_DIOR__GPIO7_3 IOMUX_PAD(0x604, 0x284, 1, 0x0, 0, 0)
886#define _MX53_PAD_PATA_DIOR__UART2_RTS IOMUX_PAD(0x604, 0x284, 3, 0x87C, 3, 0)
887#define _MX53_PAD_PATA_DIOR__CAN1_RXCAN IOMUX_PAD(0x604, 0x284, 4, 0x760, 1, 0)
888#define _MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7 IOMUX_PAD(0x604, 0x284, 7, 0x0, 0, 0)
889#define _MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B IOMUX_PAD(0x608, 0x288, 0, 0x0, 0, 0)
890#define _MX53_PAD_PATA_RESET_B__GPIO7_4 IOMUX_PAD(0x608, 0x288, 1, 0x0, 0, 0)
891#define _MX53_PAD_PATA_RESET_B__ESDHC3_CMD IOMUX_PAD(0x608, 0x288, 2, 0x0, 0, 0)
892#define _MX53_PAD_PATA_RESET_B__UART1_CTS IOMUX_PAD(0x608, 0x288, 3, 0x874, 2, 0)
893#define _MX53_PAD_PATA_RESET_B__CAN2_TXCAN IOMUX_PAD(0x608, 0x288, 4, 0x0, 0, 0)
894#define _MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0 IOMUX_PAD(0x608, 0x288, 7, 0x0, 0, 0)
895#define _MX53_PAD_PATA_IORDY__PATA_IORDY IOMUX_PAD(0x60C, 0x28C, 0, 0x0, 0, 0)
896#define _MX53_PAD_PATA_IORDY__GPIO7_5 IOMUX_PAD(0x60C, 0x28C, 1, 0x0, 0, 0)
897#define _MX53_PAD_PATA_IORDY__ESDHC3_CLK IOMUX_PAD(0x60C, 0x28C, 2, 0x0, 0, 0)
898#define _MX53_PAD_PATA_IORDY__UART1_RTS IOMUX_PAD(0x60C, 0x28C, 3, 0x874, 3, 0)
899#define _MX53_PAD_PATA_IORDY__CAN2_RXCAN IOMUX_PAD(0x60C, 0x28C, 4, 0x764, 1, 0)
900#define _MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1 IOMUX_PAD(0x60C, 0x28C, 7, 0x0, 0, 0)
901#define _MX53_PAD_PATA_DA_0__PATA_DA_0 IOMUX_PAD(0x610, 0x290, 0, 0x0, 0, 0)
902#define _MX53_PAD_PATA_DA_0__GPIO7_6 IOMUX_PAD(0x610, 0x290, 1, 0x0, 0, 0)
903#define _MX53_PAD_PATA_DA_0__ESDHC3_RST IOMUX_PAD(0x610, 0x290, 2, 0x0, 0, 0)
904#define _MX53_PAD_PATA_DA_0__OWIRE_LINE IOMUX_PAD(0x610, 0x290, 4, 0x864, 0, 0)
905#define _MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2 IOMUX_PAD(0x610, 0x290, 7, 0x0, 0, 0)
906#define _MX53_PAD_PATA_DA_1__PATA_DA_1 IOMUX_PAD(0x614, 0x294, 0, 0x0, 0, 0)
907#define _MX53_PAD_PATA_DA_1__GPIO7_7 IOMUX_PAD(0x614, 0x294, 1, 0x0, 0, 0)
908#define _MX53_PAD_PATA_DA_1__ESDHC4_CMD IOMUX_PAD(0x614, 0x294, 2, 0x0, 0, 0)
909#define _MX53_PAD_PATA_DA_1__UART3_CTS IOMUX_PAD(0x614, 0x294, 4, 0x884, 4, 0)
910#define _MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3 IOMUX_PAD(0x614, 0x294, 7, 0x0, 0, 0)
911#define _MX53_PAD_PATA_DA_2__PATA_DA_2 IOMUX_PAD(0x618, 0x298, 0, 0x0, 0, 0)
912#define _MX53_PAD_PATA_DA_2__GPIO7_8 IOMUX_PAD(0x618, 0x298, 1, 0x0, 0, 0)
913#define _MX53_PAD_PATA_DA_2__ESDHC4_CLK IOMUX_PAD(0x618, 0x298, 2, 0x0, 0, 0)
914#define _MX53_PAD_PATA_DA_2__UART3_RTS IOMUX_PAD(0x618, 0x298, 4, 0x884, 5, 0)
915#define _MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4 IOMUX_PAD(0x618, 0x298, 7, 0x0, 0, 0)
916#define _MX53_PAD_PATA_CS_0__PATA_CS_0 IOMUX_PAD(0x61C, 0x29C, 0, 0x0, 0, 0)
917#define _MX53_PAD_PATA_CS_0__GPIO7_9 IOMUX_PAD(0x61C, 0x29C, 1, 0x0, 0, 0)
918#define _MX53_PAD_PATA_CS_0__UART3_TXD_MUX IOMUX_PAD(0x61C, 0x29C, 4, 0x888, 2, 0)
919#define _MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5 IOMUX_PAD(0x61C, 0x29C, 7, 0x0, 0, 0)
920#define _MX53_PAD_PATA_CS_1__PATA_CS_1 IOMUX_PAD(0x620, 0x2A0, 0, 0x0, 0, 0)
921#define _MX53_PAD_PATA_CS_1__GPIO7_10 IOMUX_PAD(0x620, 0x2A0, 1, 0x0, 0, 0)
922#define _MX53_PAD_PATA_CS_1__UART3_RXD_MUX IOMUX_PAD(0x620, 0x2A0, 4, 0x888, 3, 0)
923#define _MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6 IOMUX_PAD(0x620, 0x2A0, 7, 0x0, 0, 0)
924#define _MX53_PAD_PATA_DATA0__PATA_DATA_0 IOMUX_PAD(0x628, 0x2A4, 0, 0x0, 0, 0)
925#define _MX53_PAD_PATA_DATA0__GPIO2_0 IOMUX_PAD(0x628, 0x2A4, 1, 0x0, 0, 0)
926#define _MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 IOMUX_PAD(0x628, 0x2A4, 3, 0x0, 0, 0)
927#define _MX53_PAD_PATA_DATA0__ESDHC3_DAT4 IOMUX_PAD(0x628, 0x2A4, 4, 0x0, 0, 0)
928#define _MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0 IOMUX_PAD(0x628, 0x2A4, 5, 0x0, 0, 0)
929#define _MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0 IOMUX_PAD(0x628, 0x2A4, 6, 0x0, 0, 0)
930#define _MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7 IOMUX_PAD(0x628, 0x2A4, 7, 0x0, 0, 0)
931#define _MX53_PAD_PATA_DATA1__PATA_DATA_1 IOMUX_PAD(0x62C, 0x2A8, 0, 0x0, 0, 0)
932#define _MX53_PAD_PATA_DATA1__GPIO2_1 IOMUX_PAD(0x62C, 0x2A8, 1, 0x0, 0, 0)
933#define _MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 IOMUX_PAD(0x62C, 0x2A8, 3, 0x0, 0, 0)
934#define _MX53_PAD_PATA_DATA1__ESDHC3_DAT5 IOMUX_PAD(0x62C, 0x2A8, 4, 0x0, 0, 0)
935#define _MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1 IOMUX_PAD(0x62C, 0x2A8, 5, 0x0, 0, 0)
936#define _MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1 IOMUX_PAD(0x62C, 0x2A8, 6, 0x0, 0, 0)
937#define _MX53_PAD_PATA_DATA2__PATA_DATA_2 IOMUX_PAD(0x630, 0x2AC, 0, 0x0, 0, 0)
938#define _MX53_PAD_PATA_DATA2__GPIO2_2 IOMUX_PAD(0x630, 0x2AC, 1, 0x0, 0, 0)
939#define _MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 IOMUX_PAD(0x630, 0x2AC, 3, 0x0, 0, 0)
940#define _MX53_PAD_PATA_DATA2__ESDHC3_DAT6 IOMUX_PAD(0x630, 0x2AC, 4, 0x0, 0, 0)
941#define _MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2 IOMUX_PAD(0x630, 0x2AC, 5, 0x0, 0, 0)
942#define _MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2 IOMUX_PAD(0x630, 0x2AC, 6, 0x0, 0, 0)
943#define _MX53_PAD_PATA_DATA3__PATA_DATA_3 IOMUX_PAD(0x634, 0x2B0, 0, 0x0, 0, 0)
944#define _MX53_PAD_PATA_DATA3__GPIO2_3 IOMUX_PAD(0x634, 0x2B0, 1, 0x0, 0, 0)
945#define _MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 IOMUX_PAD(0x634, 0x2B0, 3, 0x0, 0, 0)
946#define _MX53_PAD_PATA_DATA3__ESDHC3_DAT7 IOMUX_PAD(0x634, 0x2B0, 4, 0x0, 0, 0)
947#define _MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3 IOMUX_PAD(0x634, 0x2B0, 5, 0x0, 0, 0)
948#define _MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3 IOMUX_PAD(0x634, 0x2B0, 6, 0x0, 0, 0)
949#define _MX53_PAD_PATA_DATA4__PATA_DATA_4 IOMUX_PAD(0x638, 0x2B4, 0, 0x0, 0, 0)
950#define _MX53_PAD_PATA_DATA4__GPIO2_4 IOMUX_PAD(0x638, 0x2B4, 1, 0x0, 0, 0)
951#define _MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 IOMUX_PAD(0x638, 0x2B4, 3, 0x0, 0, 0)
952#define _MX53_PAD_PATA_DATA4__ESDHC4_DAT4 IOMUX_PAD(0x638, 0x2B4, 4, 0x0, 0, 0)
953#define _MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4 IOMUX_PAD(0x638, 0x2B4, 5, 0x0, 0, 0)
954#define _MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4 IOMUX_PAD(0x638, 0x2B4, 6, 0x0, 0, 0)
955#define _MX53_PAD_PATA_DATA5__PATA_DATA_5 IOMUX_PAD(0x63C, 0x2B8, 0, 0x0, 0, 0)
956#define _MX53_PAD_PATA_DATA5__GPIO2_5 IOMUX_PAD(0x63C, 0x2B8, 1, 0x0, 0, 0)
957#define _MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 IOMUX_PAD(0x63C, 0x2B8, 3, 0x0, 0, 0)
958#define _MX53_PAD_PATA_DATA5__ESDHC4_DAT5 IOMUX_PAD(0x63C, 0x2B8, 4, 0x0, 0, 0)
959#define _MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5 IOMUX_PAD(0x63C, 0x2B8, 5, 0x0, 0, 0)
960#define _MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5 IOMUX_PAD(0x63C, 0x2B8, 6, 0x0, 0, 0)
961#define _MX53_PAD_PATA_DATA6__PATA_DATA_6 IOMUX_PAD(0x640, 0x2BC, 1, 0x0, 0, 0)
962#define _MX53_PAD_PATA_DATA6__GPIO2_6 IOMUX_PAD(0x640, 0x2BC, 1, 0x0, 0, 0)
963#define _MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 IOMUX_PAD(0x640, 0x2BC, 1, 0x0, 0, 0)
964#define _MX53_PAD_PATA_DATA6__ESDHC4_DAT6 IOMUX_PAD(0x640, 0x2BC, 1, 0x0, 0, 0)
965#define _MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6 IOMUX_PAD(0x640, 0x2BC, 1, 0x0, 0, 0)
966#define _MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6 IOMUX_PAD(0x640, 0x2BC, 1, 0x0, 0, 0)
967#define _MX53_PAD_PATA_DATA7__PATA_DATA_7 IOMUX_PAD(0x644, 0x2C0, 0, 0x0, 0, 0)
968#define _MX53_PAD_PATA_DATA7__GPIO2_7 IOMUX_PAD(0x644, 0x2C0, 1, 0x0, 0, 0)
969#define _MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 IOMUX_PAD(0x644, 0x2C0, 3, 0x0, 0, 0)
970#define _MX53_PAD_PATA_DATA7__ESDHC4_DAT7 IOMUX_PAD(0x644, 0x2C0, 4, 0x0, 0, 0)
971#define _MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7 IOMUX_PAD(0x644, 0x2C0, 5, 0x0, 0, 0)
972#define _MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7 IOMUX_PAD(0x644, 0x2C0, 6, 0x0, 0, 0)
973#define _MX53_PAD_PATA_DATA8__PATA_DATA_8 IOMUX_PAD(0x648, 0x2C4, 0, 0x0, 0, 0)
974#define _MX53_PAD_PATA_DATA8__GPIO2_8 IOMUX_PAD(0x648, 0x2C4, 1, 0x0, 0, 0)
975#define _MX53_PAD_PATA_DATA8__ESDHC1_DAT4 IOMUX_PAD(0x648, 0x2C4, 2, 0x0, 0, 0)
976#define _MX53_PAD_PATA_DATA8__EMI_NANDF_D_8 IOMUX_PAD(0x648, 0x2C4, 3, 0x0, 0, 0)
977#define _MX53_PAD_PATA_DATA8__ESDHC3_DAT0 IOMUX_PAD(0x648, 0x2C4, 4, 0x0, 0, 0)
978#define _MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8 IOMUX_PAD(0x648, 0x2C4, 5, 0x0, 0, 0)
979#define _MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8 IOMUX_PAD(0x648, 0x2C4, 6, 0x0, 0, 0)
980#define _MX53_PAD_PATA_DATA9__PATA_DATA_9 IOMUX_PAD(0x64C, 0x2C8, 0, 0x0, 0, 0)
981#define _MX53_PAD_PATA_DATA9__GPIO2_9 IOMUX_PAD(0x64C, 0x2C8, 1, 0x0, 0, 0)
982#define _MX53_PAD_PATA_DATA9__ESDHC1_DAT5 IOMUX_PAD(0x64C, 0x2C8, 2, 0x0, 0, 0)
983#define _MX53_PAD_PATA_DATA9__EMI_NANDF_D_9 IOMUX_PAD(0x64C, 0x2C8, 3, 0x0, 0, 0)
984#define _MX53_PAD_PATA_DATA9__ESDHC3_DAT1 IOMUX_PAD(0x64C, 0x2C8, 4, 0x0, 0, 0)
985#define _MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9 IOMUX_PAD(0x64C, 0x2C8, 5, 0x0, 0, 0)
986#define _MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9 IOMUX_PAD(0x64C, 0x2C8, 6, 0x0, 0, 0)
987#define _MX53_PAD_PATA_DATA10__PATA_DATA_10 IOMUX_PAD(0x650, 0x2CC, 0, 0x0, 0, 0)
988#define _MX53_PAD_PATA_DATA10__GPIO2_10 IOMUX_PAD(0x650, 0x2CC, 1, 0x0, 0, 0)
989#define _MX53_PAD_PATA_DATA10__ESDHC1_DAT6 IOMUX_PAD(0x650, 0x2CC, 2, 0x0, 0, 0)
990#define _MX53_PAD_PATA_DATA10__EMI_NANDF_D_10 IOMUX_PAD(0x650, 0x2CC, 3, 0x0, 0, 0)
991#define _MX53_PAD_PATA_DATA10__ESDHC3_DAT2 IOMUX_PAD(0x650, 0x2CC, 4, 0x0, 0, 0)
992#define _MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10 IOMUX_PAD(0x650, 0x2CC, 5, 0x0, 0, 0)
993#define _MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10 IOMUX_PAD(0x650, 0x2CC, 6, 0x0, 0, 0)
994#define _MX53_PAD_PATA_DATA11__PATA_DATA_11 IOMUX_PAD(0x654, 0x2D0, 0, 0x0, 0, 0)
995#define _MX53_PAD_PATA_DATA11__GPIO2_11 IOMUX_PAD(0x654, 0x2D0, 1, 0x0, 0, 0)
996#define _MX53_PAD_PATA_DATA11__ESDHC1_DAT7 IOMUX_PAD(0x654, 0x2D0, 2, 0x0, 0, 0)
997#define _MX53_PAD_PATA_DATA11__EMI_NANDF_D_11 IOMUX_PAD(0x654, 0x2D0, 3, 0x0, 0, 0)
998#define _MX53_PAD_PATA_DATA11__ESDHC3_DAT3 IOMUX_PAD(0x654, 0x2D0, 4, 0x0, 0, 0)
999#define _MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11 IOMUX_PAD(0x654, 0x2D0, 5, 0x0, 0, 0)
1000#define _MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11 IOMUX_PAD(0x654, 0x2D0, 6, 0x0, 0, 0)
1001#define _MX53_PAD_PATA_DATA12__PATA_DATA_12 IOMUX_PAD(0x658, 0x2D4, 0, 0x0, 0, 0)
1002#define _MX53_PAD_PATA_DATA12__GPIO2_12 IOMUX_PAD(0x658, 0x2D4, 1, 0x0, 0, 0)
1003#define _MX53_PAD_PATA_DATA12__ESDHC2_DAT4 IOMUX_PAD(0x658, 0x2D4, 2, 0x0, 0, 0)
1004#define _MX53_PAD_PATA_DATA12__EMI_NANDF_D_12 IOMUX_PAD(0x658, 0x2D4, 3, 0x0, 0, 0)
1005#define _MX53_PAD_PATA_DATA12__ESDHC4_DAT0 IOMUX_PAD(0x658, 0x2D4, 4, 0x0, 0, 0)
1006#define _MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12 IOMUX_PAD(0x658, 0x2D4, 5, 0x0, 0, 0)
1007#define _MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12 IOMUX_PAD(0x658, 0x2D4, 6, 0x0, 0, 0)
1008#define _MX53_PAD_PATA_DATA13__PATA_DATA_13 IOMUX_PAD(0x65C, 0x2D8, 0, 0x0, 0, 0)
1009#define _MX53_PAD_PATA_DATA13__GPIO2_13 IOMUX_PAD(0x65C, 0x2D8, 1, 0x0, 0, 0)
1010#define _MX53_PAD_PATA_DATA13__ESDHC2_DAT5 IOMUX_PAD(0x65C, 0x2D8, 2, 0x0, 0, 0)
1011#define _MX53_PAD_PATA_DATA13__EMI_NANDF_D_13 IOMUX_PAD(0x65C, 0x2D8, 3, 0x0, 0, 0)
1012#define _MX53_PAD_PATA_DATA13__ESDHC4_DAT1 IOMUX_PAD(0x65C, 0x2D8, 4, 0x0, 0, 0)
1013#define _MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13 IOMUX_PAD(0x65C, 0x2D8, 5, 0x0, 0, 0)
1014#define _MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13 IOMUX_PAD(0x65C, 0x2D8, 6, 0x0, 0, 0)
1015#define _MX53_PAD_PATA_DATA14__PATA_DATA_14 IOMUX_PAD(0x660, 0x2DC, 0, 0x0, 0, 0)
1016#define _MX53_PAD_PATA_DATA14__GPIO2_14 IOMUX_PAD(0x660, 0x2DC, 1, 0x0, 0, 0)
1017#define _MX53_PAD_PATA_DATA14__ESDHC2_DAT6 IOMUX_PAD(0x660, 0x2DC, 2, 0x0, 0, 0)
1018#define _MX53_PAD_PATA_DATA14__EMI_NANDF_D_14 IOMUX_PAD(0x660, 0x2DC, 3, 0x0, 0, 0)
1019#define _MX53_PAD_PATA_DATA14__ESDHC4_DAT2 IOMUX_PAD(0x660, 0x2DC, 4, 0x0, 0, 0)
1020#define _MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14 IOMUX_PAD(0x660, 0x2DC, 5, 0x0, 0, 0)
1021#define _MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14 IOMUX_PAD(0x660, 0x2DC, 6, 0x0, 0, 0)
1022#define _MX53_PAD_PATA_DATA15__PATA_DATA_15 IOMUX_PAD(0x664, 0x2E0, 0, 0x0, 0, 0)
1023#define _MX53_PAD_PATA_DATA15__GPIO2_15 IOMUX_PAD(0x664, 0x2E0, 1, 0x0, 0, 0)
1024#define _MX53_PAD_PATA_DATA15__ESDHC2_DAT7 IOMUX_PAD(0x664, 0x2E0, 2, 0x0, 0, 0)
1025#define _MX53_PAD_PATA_DATA15__EMI_NANDF_D_15 IOMUX_PAD(0x664, 0x2E0, 3, 0x0, 0, 0)
1026#define _MX53_PAD_PATA_DATA15__ESDHC4_DAT3 IOMUX_PAD(0x664, 0x2E0, 4, 0x0, 0, 0)
1027#define _MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15 IOMUX_PAD(0x664, 0x2E0, 5, 0x0, 0, 0)
1028#define _MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15 IOMUX_PAD(0x664, 0x2E0, 6, 0x0, 0, 0)
1029#define _MX53_PAD_SD1_DATA0__ESDHC1_DAT0 IOMUX_PAD(0x66C, 0x2E4, 0, 0x0, 0, 0)
1030#define _MX53_PAD_SD1_DATA0__GPIO1_16 IOMUX_PAD(0x66C, 0x2E4, 1, 0x0, 0, 0)
1031#define _MX53_PAD_SD1_DATA0__GPT_CAPIN1 IOMUX_PAD(0x66C, 0x2E4, 3, 0x0, 0, 0)
1032#define _MX53_PAD_SD1_DATA0__CSPI_MISO IOMUX_PAD(0x66C, 0x2E4, 5, 0x784, 2, 0)
1033#define _MX53_PAD_SD1_DATA0__CCM_PLL3_BYP IOMUX_PAD(0x66C, 0x2E4, 7, 0x778, 0, 0)
1034#define _MX53_PAD_SD1_DATA1__ESDHC1_DAT1 IOMUX_PAD(0x670, 0x2E8, 0, 0x0, 0, 0)
1035#define _MX53_PAD_SD1_DATA1__GPIO1_17 IOMUX_PAD(0x670, 0x2E8, 1, 0x0, 0, 0)
1036#define _MX53_PAD_SD1_DATA1__GPT_CAPIN2 IOMUX_PAD(0x670, 0x2E8, 3, 0x0, 0, 0)
1037#define _MX53_PAD_SD1_DATA1__CSPI_SS0 IOMUX_PAD(0x670, 0x2E8, 5, 0x78C, 3, 0)
1038#define _MX53_PAD_SD1_DATA1__CCM_PLL4_BYP IOMUX_PAD(0x670, 0x2E8, 7, 0x77C, 1, 0)
1039#define _MX53_PAD_SD1_CMD__ESDHC1_CMD IOMUX_PAD(0x674, 0x2EC, IOMUX_CONFIG_SION, 0x0, 0, 0)
1040#define _MX53_PAD_SD1_CMD__GPIO1_18 IOMUX_PAD(0x674, 0x2EC, 1, 0x0, 0, 0)
1041#define _MX53_PAD_SD1_CMD__GPT_CMPOUT1 IOMUX_PAD(0x674, 0x2EC, 3, 0x0, 0, 0)
1042#define _MX53_PAD_SD1_CMD__CSPI_MOSI IOMUX_PAD(0x674, 0x2EC, 5, 0x788, 2, 0)
1043#define _MX53_PAD_SD1_CMD__CCM_PLL1_BYP IOMUX_PAD(0x674, 0x2EC, 7, 0x770, 0, 0)
1044#define _MX53_PAD_SD1_DATA2__ESDHC1_DAT2 IOMUX_PAD(0x678, 0x2F0, 0, 0x0, 0, 0)
1045#define _MX53_PAD_SD1_DATA2__GPIO1_19 IOMUX_PAD(0x678, 0x2F0, 1, 0x0, 0, 0)
1046#define _MX53_PAD_SD1_DATA2__GPT_CMPOUT2 IOMUX_PAD(0x678, 0x2F0, 2, 0x0, 0, 0)
1047#define _MX53_PAD_SD1_DATA2__PWM2_PWMO IOMUX_PAD(0x678, 0x2F0, 3, 0x0, 0, 0)
1048#define _MX53_PAD_SD1_DATA2__WDOG1_WDOG_B IOMUX_PAD(0x678, 0x2F0, 4, 0x0, 0, 0)
1049#define _MX53_PAD_SD1_DATA2__CSPI_SS1 IOMUX_PAD(0x678, 0x2F0, 5, 0x790, 2, 0)
1050#define _MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB IOMUX_PAD(0x678, 0x2F0, 6, 0x0, 0, 0)
1051#define _MX53_PAD_SD1_DATA2__CCM_PLL2_BYP IOMUX_PAD(0x678, 0x2F0, 7, 0x774, 0, 0)
1052#define _MX53_PAD_SD1_CLK__ESDHC1_CLK IOMUX_PAD(0x67C, 0x2F4, 0, 0x0, 0, 0)
1053#define _MX53_PAD_SD1_CLK__GPIO1_20 IOMUX_PAD(0x67C, 0x2F4, 1, 0x0, 0, 0)
1054#define _MX53_PAD_SD1_CLK__OSC32k_32K_OUT IOMUX_PAD(0x67C, 0x2F4, 2, 0x0, 0, 0)
1055#define _MX53_PAD_SD1_CLK__GPT_CLKIN IOMUX_PAD(0x67C, 0x2F4, 3, 0x0, 0, 0)
1056#define _MX53_PAD_SD1_CLK__CSPI_SCLK IOMUX_PAD(0x67C, 0x2F4, 5, 0x780, 2, 0)
1057#define _MX53_PAD_SD1_CLK__SATA_PHY_DTB_0 IOMUX_PAD(0x67C, 0x2F4, 7, 0x0, 0, 0)
1058#define _MX53_PAD_SD1_DATA3__ESDHC1_DAT3 IOMUX_PAD(0x680, 0x2F8, 0, 0x0, 0, 0)
1059#define _MX53_PAD_SD1_DATA3__GPIO1_21 IOMUX_PAD(0x680, 0x2F8, 1, 0x0, 0, 0)
1060#define _MX53_PAD_SD1_DATA3__GPT_CMPOUT3 IOMUX_PAD(0x680, 0x2F8, 2, 0x0, 0, 0)
1061#define _MX53_PAD_SD1_DATA3__PWM1_PWMO IOMUX_PAD(0x680, 0x2F8, 3, 0x0, 0, 0)
1062#define _MX53_PAD_SD1_DATA3__WDOG2_WDOG_B IOMUX_PAD(0x680, 0x2F8, 4, 0x0, 0, 0)
1063#define _MX53_PAD_SD1_DATA3__CSPI_SS2 IOMUX_PAD(0x680, 0x2F8, 5, 0x794, 2, 0)
1064#define _MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB IOMUX_PAD(0x680, 0x2F8, 6, 0x0, 0, 0)
1065#define _MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1 IOMUX_PAD(0x680, 0x2F8, 7, 0x0, 0, 0)
1066#define _MX53_PAD_SD2_CLK__ESDHC2_CLK IOMUX_PAD(0x688, 0x2FC, 0, 0x0, 0, 0)
1067#define _MX53_PAD_SD2_CLK__GPIO1_10 IOMUX_PAD(0x688, 0x2FC, 1, 0x0, 0, 0)
1068#define _MX53_PAD_SD2_CLK__KPP_COL_5 IOMUX_PAD(0x688, 0x2FC, 2, 0x840, 2, 0)
1069#define _MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS IOMUX_PAD(0x688, 0x2FC, 3, 0x73C, 1, 0)
1070#define _MX53_PAD_SD2_CLK__CSPI_SCLK IOMUX_PAD(0x688, 0x2FC, 5, 0x780, 3, 0)
1071#define _MX53_PAD_SD2_CLK__SCC_RANDOM_V IOMUX_PAD(0x688, 0x2FC, 7, 0x0, 0, 0)
1072#define _MX53_PAD_SD2_CMD__ESDHC2_CMD IOMUX_PAD(0x68C, 0x300, 0, 0x0, 0, 0)
1073#define _MX53_PAD_SD2_CMD__GPIO1_11 IOMUX_PAD(0x68C, 0x300, 1, 0x0, 0, 0)
1074#define _MX53_PAD_SD2_CMD__KPP_ROW_5 IOMUX_PAD(0x68C, 0x300, 2, 0x84C, 1, 0)
1075#define _MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC IOMUX_PAD(0x68C, 0x300, 3, 0x738, 1, 0)
1076#define _MX53_PAD_SD2_CMD__CSPI_MOSI IOMUX_PAD(0x68C, 0x300, 5, 0x788, 3, 0)
1077#define _MX53_PAD_SD2_CMD__SCC_RANDOM IOMUX_PAD(0x68C, 0x300, 7, 0x0, 0, 0)
1078#define _MX53_PAD_SD2_DATA3__ESDHC2_DAT3 IOMUX_PAD(0x690, 0x304, 0, 0x0, 0, 0)
1079#define _MX53_PAD_SD2_DATA3__GPIO1_12 IOMUX_PAD(0x690, 0x304, 1, 0x0, 0, 0)
1080#define _MX53_PAD_SD2_DATA3__KPP_COL_6 IOMUX_PAD(0x690, 0x304, 2, 0x844, 1, 0)
1081#define _MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC IOMUX_PAD(0x690, 0x304, 3, 0x740, 1, 0)
1082#define _MX53_PAD_SD2_DATA3__CSPI_SS2 IOMUX_PAD(0x690, 0x304, 5, 0x794, 3, 0)
1083#define _MX53_PAD_SD2_DATA3__SJC_DONE IOMUX_PAD(0x690, 0x304, 7, 0x0, 0, 0)
1084#define _MX53_PAD_SD2_DATA2__ESDHC2_DAT2 IOMUX_PAD(0x694, 0x308, 0, 0x0, 0, 0)
1085#define _MX53_PAD_SD2_DATA2__GPIO1_13 IOMUX_PAD(0x694, 0x308, 1, 0x0, 0, 0)
1086#define _MX53_PAD_SD2_DATA2__KPP_ROW_6 IOMUX_PAD(0x694, 0x308, 2, 0x850, 1, 0)
1087#define _MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD IOMUX_PAD(0x694, 0x308, 3, 0x734, 1, 0)
1088#define _MX53_PAD_SD2_DATA2__CSPI_SS1 IOMUX_PAD(0x694, 0x308, 5, 0x790, 3, 0)
1089#define _MX53_PAD_SD2_DATA2__SJC_FAIL IOMUX_PAD(0x694, 0x308, 7, 0x0, 0, 0)
1090#define _MX53_PAD_SD2_DATA1__ESDHC2_DAT1 IOMUX_PAD(0x698, 0x30C, 0, 0x0, 0, 0)
1091#define _MX53_PAD_SD2_DATA1__GPIO1_14 IOMUX_PAD(0x698, 0x30C, 1, 0x0, 0, 0)
1092#define _MX53_PAD_SD2_DATA1__KPP_COL_7 IOMUX_PAD(0x698, 0x30C, 2, 0x848, 1, 0)
1093#define _MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS IOMUX_PAD(0x698, 0x30C, 3, 0x744, 0, 0)
1094#define _MX53_PAD_SD2_DATA1__CSPI_SS0 IOMUX_PAD(0x698, 0x30C, 5, 0x78C, 4, 0)
1095#define _MX53_PAD_SD2_DATA1__RTIC_SEC_VIO IOMUX_PAD(0x698, 0x30C, 7, 0x0, 0, 0)
1096#define _MX53_PAD_SD2_DATA0__ESDHC2_DAT0 IOMUX_PAD(0x69C, 0x310, 0, 0x0, 0, 0)
1097#define _MX53_PAD_SD2_DATA0__GPIO1_15 IOMUX_PAD(0x69C, 0x310, 1, 0x0, 0, 0)
1098#define _MX53_PAD_SD2_DATA0__KPP_ROW_7 IOMUX_PAD(0x69C, 0x310, 2, 0x854, 1, 0)
1099#define _MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD IOMUX_PAD(0x69C, 0x310, 3, 0x730, 1, 0)
1100#define _MX53_PAD_SD2_DATA0__CSPI_MISO IOMUX_PAD(0x69C, 0x310, 5, 0x784, 3, 0)
1101#define _MX53_PAD_SD2_DATA0__RTIC_DONE_INT IOMUX_PAD(0x69C, 0x310, 7, 0x0, 0, 0)
1102#define _MX53_PAD_GPIO_0__CCM_CLKO IOMUX_PAD(0x6A4, 0x314, 0, 0x0, 0, 0)
1103#define _MX53_PAD_GPIO_0__GPIO1_0 IOMUX_PAD(0x6A4, 0x314, 1, 0x0, 0, 0)
1104#define _MX53_PAD_GPIO_0__KPP_COL_5 IOMUX_PAD(0x6A4, 0x314, 2, 0x840, 3, 0)
1105#define _MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK IOMUX_PAD(0x6A4, 0x314, 3, 0x0, 0, 0)
1106#define _MX53_PAD_GPIO_0__EPIT1_EPITO IOMUX_PAD(0x6A4, 0x314, 4, 0x0, 0, 0)
1107#define _MX53_PAD_GPIO_0__SRTC_ALARM_DEB IOMUX_PAD(0x6A4, 0x314, 5, 0x0, 0, 0)
1108#define _MX53_PAD_GPIO_0__USBOH3_USBH1_PWR IOMUX_PAD(0x6A4, 0x314, 6, 0x0, 0, 0)
1109#define _MX53_PAD_GPIO_0__CSU_TD IOMUX_PAD(0x6A4, 0x314, 7, 0x0, 0, 0)
1110#define _MX53_PAD_GPIO_1__ESAI1_SCKR IOMUX_PAD(0x6A8, 0x318, 0, 0x7DC, 1, 0)
1111#define _MX53_PAD_GPIO_1__GPIO1_1 IOMUX_PAD(0x6A8, 0x318, 1, 0x0, 0, 0)
1112#define _MX53_PAD_GPIO_1__KPP_ROW_5 IOMUX_PAD(0x6A8, 0x318, 2, 0x84C, 2, 0)
1113#define _MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK IOMUX_PAD(0x6A8, 0x318, 3, 0x0, 0, 0)
1114#define _MX53_PAD_GPIO_1__PWM2_PWMO IOMUX_PAD(0x6A8, 0x318, 4, 0x0, 0, 0)
1115#define _MX53_PAD_GPIO_1__WDOG2_WDOG_B IOMUX_PAD(0x6A8, 0x318, 5, 0x0, 0, 0)
1116#define _MX53_PAD_GPIO_1__ESDHC1_CD IOMUX_PAD(0x6A8, 0x318, 6, 0x0, 0, 0)
1117#define _MX53_PAD_GPIO_1__SRC_TESTER_ACK IOMUX_PAD(0x6A8, 0x318, 7, 0x0, 0, 0)
1118#define _MX53_PAD_GPIO_9__ESAI1_FSR IOMUX_PAD(0x6AC, 0x31C, 0, 0x7CC, 1, 0)
1119#define _MX53_PAD_GPIO_9__GPIO1_9 IOMUX_PAD(0x6AC, 0x31C, 1, 0x0, 0, 0)
1120#define _MX53_PAD_GPIO_9__KPP_COL_6 IOMUX_PAD(0x6AC, 0x31C, 2, 0x844, 2, 0)
1121#define _MX53_PAD_GPIO_9__CCM_REF_EN_B IOMUX_PAD(0x6AC, 0x31C, 3, 0x0, 0, 0)
1122#define _MX53_PAD_GPIO_9__PWM1_PWMO IOMUX_PAD(0x6AC, 0x31C, 4, 0x0, 0, 0)
1123#define _MX53_PAD_GPIO_9__WDOG1_WDOG_B IOMUX_PAD(0x6AC, 0x31C, 5, 0x0, 0, 0)
1124#define _MX53_PAD_GPIO_9__ESDHC1_WP IOMUX_PAD(0x6AC, 0x31C, 6, 0x7FC, 1, 0)
1125#define _MX53_PAD_GPIO_9__SCC_FAIL_STATE IOMUX_PAD(0x6AC, 0x31C, 7, 0x0, 0, 0)
1126#define _MX53_PAD_GPIO_3__ESAI1_HCKR IOMUX_PAD(0x6B0, 0x320, 0, 0x7D4, 1, 0)
1127#define _MX53_PAD_GPIO_3__GPIO1_3 IOMUX_PAD(0x6B0, 0x320, 1, 0x0, 0, 0)
1128#define _MX53_PAD_GPIO_3__I2C3_SCL IOMUX_PAD(0x6B0, 0x320, 2 | IOMUX_CONFIG_SION, 0x824, 1, 0)
1129#define _MX53_PAD_GPIO_3__DPLLIP1_TOG_EN IOMUX_PAD(0x6B0, 0x320, 3, 0x0, 0, 0)
1130#define _MX53_PAD_GPIO_3__CCM_CLKO2 IOMUX_PAD(0x6B0, 0x320, 4, 0x0, 0, 0)
1131#define _MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 IOMUX_PAD(0x6B0, 0x320, 5, 0x0, 0, 0)
1132#define _MX53_PAD_GPIO_3__USBOH3_USBH1_OC IOMUX_PAD(0x6B0, 0x320, 6, 0x8A0, 1, 0)
1133#define _MX53_PAD_GPIO_3__MLB_MLBCLK IOMUX_PAD(0x6B0, 0x320, 7, 0x858, 2, 0)
1134#define _MX53_PAD_GPIO_6__ESAI1_SCKT IOMUX_PAD(0x6B4, 0x324, 0, 0x7E0, 1, 0)
1135#define _MX53_PAD_GPIO_6__GPIO1_6 IOMUX_PAD(0x6B4, 0x324, 1, 0x0, 0, 0)
1136#define _MX53_PAD_GPIO_6__I2C3_SDA IOMUX_PAD(0x6B4, 0x324, 2 | IOMUX_CONFIG_SION, 0x828, 1, 0)
1137#define _MX53_PAD_GPIO_6__CCM_CCM_OUT_0 IOMUX_PAD(0x6B4, 0x324, 3, 0x0, 0, 0)
1138#define _MX53_PAD_GPIO_6__CSU_CSU_INT_DEB IOMUX_PAD(0x6B4, 0x324, 4, 0x0, 0, 0)
1139#define _MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 IOMUX_PAD(0x6B4, 0x324, 5, 0x0, 0, 0)
1140#define _MX53_PAD_GPIO_6__ESDHC2_LCTL IOMUX_PAD(0x6B4, 0x324, 6, 0x0, 0, 0)
1141#define _MX53_PAD_GPIO_6__MLB_MLBSIG IOMUX_PAD(0x6B4, 0x324, 7, 0x860, 2, 0)
1142#define _MX53_PAD_GPIO_2__ESAI1_FST IOMUX_PAD(0x6B8, 0x328, 0, 0x7D0, 1, 0)
1143#define _MX53_PAD_GPIO_2__GPIO1_2 IOMUX_PAD(0x6B8, 0x328, 1, 0x0, 0, 0)
1144#define _MX53_PAD_GPIO_2__KPP_ROW_6 IOMUX_PAD(0x6B8, 0x328, 2, 0x850, 2, 0)
1145#define _MX53_PAD_GPIO_2__CCM_CCM_OUT_1 IOMUX_PAD(0x6B8, 0x328, 3, 0x0, 0, 0)
1146#define _MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 IOMUX_PAD(0x6B8, 0x328, 4, 0x0, 0, 0)
1147#define _MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 IOMUX_PAD(0x6B8, 0x328, 5, 0x0, 0, 0)
1148#define _MX53_PAD_GPIO_2__ESDHC2_WP IOMUX_PAD(0x6B8, 0x328, 6, 0x0, 0, 0)
1149#define _MX53_PAD_GPIO_2__MLB_MLBDAT IOMUX_PAD(0x6B8, 0x328, 7, 0x85C, 2, 0)
1150#define _MX53_PAD_GPIO_4__ESAI1_HCKT IOMUX_PAD(0x6BC, 0x32C, 0, 0x7D8, 1, 0)
1151#define _MX53_PAD_GPIO_4__GPIO1_4 IOMUX_PAD(0x6BC, 0x32C, 1, 0x0, 0, 0)
1152#define _MX53_PAD_GPIO_4__KPP_COL_7 IOMUX_PAD(0x6BC, 0x32C, 2, 0x848, 2, 0)
1153#define _MX53_PAD_GPIO_4__CCM_CCM_OUT_2 IOMUX_PAD(0x6BC, 0x32C, 3, 0x0, 0, 0)
1154#define _MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 IOMUX_PAD(0x6BC, 0x32C, 4, 0x0, 0, 0)
1155#define _MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 IOMUX_PAD(0x6BC, 0x32C, 5, 0x0, 0, 0)
1156#define _MX53_PAD_GPIO_4__ESDHC2_CD IOMUX_PAD(0x6BC, 0x32C, 6, 0x0, 0, 0)
1157#define _MX53_PAD_GPIO_4__SCC_SEC_STATE IOMUX_PAD(0x6BC, 0x32C, 7, 0x0, 0, 0)
1158#define _MX53_PAD_GPIO_5__ESAI1_TX2_RX3 IOMUX_PAD(0x6C0, 0x330, 0, 0x7EC, 1, 0)
1159#define _MX53_PAD_GPIO_5__GPIO1_5 IOMUX_PAD(0x6C0, 0x330, 1, 0x0, 0, 0)
1160#define _MX53_PAD_GPIO_5__KPP_ROW_7 IOMUX_PAD(0x6C0, 0x330, 2, 0x854, 2, 0)
1161#define _MX53_PAD_GPIO_5__CCM_CLKO IOMUX_PAD(0x6C0, 0x330, 3, 0x0, 0, 0)
1162#define _MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 IOMUX_PAD(0x6C0, 0x330, 4, 0x0, 0, 0)
1163#define _MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 IOMUX_PAD(0x6C0, 0x330, 5, 0x0, 0, 0)
1164#define _MX53_PAD_GPIO_5__I2C3_SCL IOMUX_PAD(0x6C0, 0x330, 6, 0x824, 2, 0)
1165#define _MX53_PAD_GPIO_5__CCM_PLL1_BYP IOMUX_PAD(0x6C0, 0x330, 7, 0x770, 1, 0)
1166#define _MX53_PAD_GPIO_7__ESAI1_TX4_RX1 IOMUX_PAD(0x6C4, 0x334, 0, 0x7F4, 1, 0)
1167#define _MX53_PAD_GPIO_7__GPIO1_7 IOMUX_PAD(0x6C4, 0x334, 1, 0x0, 0, 0)
1168#define _MX53_PAD_GPIO_7__EPIT1_EPITO IOMUX_PAD(0x6C4, 0x334, 2, 0x0, 0, 0)
1169#define _MX53_PAD_GPIO_7__CAN1_TXCAN IOMUX_PAD(0x6C4, 0x334, 3, 0x0, 0, 0)
1170#define _MX53_PAD_GPIO_7__UART2_TXD_MUX IOMUX_PAD(0x6C4, 0x334, 4, 0x880, 4, 0)
1171#define _MX53_PAD_GPIO_7__FIRI_RXD IOMUX_PAD(0x6C4, 0x334, 5, 0x80C, 1, 0)
1172#define _MX53_PAD_GPIO_7__SPDIF_PLOCK IOMUX_PAD(0x6C4, 0x334, 6, 0x0, 0, 0)
1173#define _MX53_PAD_GPIO_7__CCM_PLL2_BYP IOMUX_PAD(0x6C4, 0x334, 7, 0x774, 1, 0)
1174#define _MX53_PAD_GPIO_8__ESAI1_TX5_RX0 IOMUX_PAD(0x6C8, 0x338, 0, 0x7F8, 1, 0)
1175#define _MX53_PAD_GPIO_8__GPIO1_8 IOMUX_PAD(0x6C8, 0x338, 1, 0x0, 0, 0)
1176#define _MX53_PAD_GPIO_8__EPIT2_EPITO IOMUX_PAD(0x6C8, 0x338, 2, 0x0, 0, 0)
1177#define _MX53_PAD_GPIO_8__CAN1_RXCAN IOMUX_PAD(0x6C8, 0x338, 3, 0x760, 3, 0)
1178#define _MX53_PAD_GPIO_8__UART2_RXD_MUX IOMUX_PAD(0x6C8, 0x338, 4, 0x880, 5, 0)
1179#define _MX53_PAD_GPIO_8__FIRI_TXD IOMUX_PAD(0x6C8, 0x338, 5, 0x0, 0, 0)
1180#define _MX53_PAD_GPIO_8__SPDIF_SRCLK IOMUX_PAD(0x6C8, 0x338, 6, 0x0, 0, 0)
1181#define _MX53_PAD_GPIO_8__CCM_PLL3_BYP IOMUX_PAD(0x6C8, 0x338, 7, 0x778, 1, 0)
1182#define _MX53_PAD_GPIO_16__ESAI1_TX3_RX2 IOMUX_PAD(0x6CC, 0x33C, 0, 0x7F0, 1, 0)
1183#define _MX53_PAD_GPIO_16__GPIO7_11 IOMUX_PAD(0x6CC, 0x33C, 1, 0x0, 0, 0)
1184#define _MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT IOMUX_PAD(0x6CC, 0x33C, 2, 0x0, 0, 0)
1185#define _MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1 IOMUX_PAD(0x6CC, 0x33C, 4, 0x0, 0, 0)
1186#define _MX53_PAD_GPIO_16__SPDIF_IN1 IOMUX_PAD(0x6CC, 0x33C, 5, 0x870, 1, 0)
1187#define _MX53_PAD_GPIO_16__I2C3_SDA IOMUX_PAD(0x6CC, 0x33C, 6 | IOMUX_CONFIG_SION, 0x828, 2, 0)
1188#define _MX53_PAD_GPIO_16__SJC_DE_B IOMUX_PAD(0x6CC, 0x33C, 7, 0x0, 0, 0)
1189#define _MX53_PAD_GPIO_17__ESAI1_TX0 IOMUX_PAD(0x6D0, 0x340, 0, 0x7E4, 1, 0)
1190#define _MX53_PAD_GPIO_17__GPIO7_12 IOMUX_PAD(0x6D0, 0x340, 1, 0x0, 0, 0)
1191#define _MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0 IOMUX_PAD(0x6D0, 0x340, 2, 0x868, 1, 0)
1192#define _MX53_PAD_GPIO_17__GPC_PMIC_RDY IOMUX_PAD(0x6D0, 0x340, 3, 0x810, 1, 0)
1193#define _MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG IOMUX_PAD(0x6D0, 0x340, 4, 0x0, 0, 0)
1194#define _MX53_PAD_GPIO_17__SPDIF_OUT1 IOMUX_PAD(0x6D0, 0x340, 5, 0x0, 0, 0)
1195#define _MX53_PAD_GPIO_17__IPU_SNOOP2 IOMUX_PAD(0x6D0, 0x340, 6, 0x0, 0, 0)
1196#define _MX53_PAD_GPIO_17__SJC_JTAG_ACT IOMUX_PAD(0x6D0, 0x340, 7, 0x0, 0, 0)
1197#define _MX53_PAD_GPIO_18__ESAI1_TX1 IOMUX_PAD(0x6D4, 0x344, 0, 0x7E8, 1, 0)
1198#define _MX53_PAD_GPIO_18__GPIO7_13 IOMUX_PAD(0x6D4, 0x344, 1, 0x0, 0, 0)
1199#define _MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1 IOMUX_PAD(0x6D4, 0x344, 2, 0x86C, 1, 0)
1200#define _MX53_PAD_GPIO_18__OWIRE_LINE IOMUX_PAD(0x6D4, 0x344, 3, 0x864, 1, 0)
1201#define _MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG IOMUX_PAD(0x6D4, 0x344, 4, 0x0, 0, 0)
1202#define _MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK IOMUX_PAD(0x6D4, 0x344, 5, 0x768, 1, 0)
1203#define _MX53_PAD_GPIO_18__ESDHC1_LCTL IOMUX_PAD(0x6D4, 0x344, 6, 0x0, 0, 0)
1204#define _MX53_PAD_GPIO_18__SRC_SYSTEM_RST IOMUX_PAD(0x6D4, 0x344, 7, 0x0, 0, 0)
63 1205
64#define MX53_PAD_GPIO_19__GPIO_4_5 IOMUX_PAD(0x348, 0x20,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1206#define MX53_PAD_GPIO_19__KPP_COL_5 (_MX53_PAD_GPIO_19__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
65#define MX53_PAD_KEY_COL0__GPIO_4_6 IOMUX_PAD(0x34C, 0x24,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1207#define MX53_PAD_GPIO_19__GPIO4_5 (_MX53_PAD_GPIO_19__GPIO4_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
66#define MX53_PAD_KEY_ROW0__GPIO_4_7 IOMUX_PAD(0x350, 0x28,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1208#define MX53_PAD_GPIO_19__CCM_CLKO (_MX53_PAD_GPIO_19__CCM_CLKO | MUX_PAD_CTRL(NO_PAD_CTRL))
67#define MX53_PAD_KEY_COL1__GPIO_4_8 IOMUX_PAD(0x354, 0x2C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1209#define MX53_PAD_GPIO_19__SPDIF_OUT1 (_MX53_PAD_GPIO_19__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
68#define MX53_PAD_KEY_ROW1__GPIO_4_9 IOMUX_PAD(0x358, 0x30,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1210#define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 (_MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 | MUX_PAD_CTRL(NO_PAD_CTRL))
69#define MX53_PAD_KEY_COL2__GPIO_4_10 IOMUX_PAD(0x35C, 0x34,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1211#define MX53_PAD_GPIO_19__ECSPI1_RDY (_MX53_PAD_GPIO_19__ECSPI1_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
70#define MX53_PAD_KEY_ROW2__GPIO_4_11 IOMUX_PAD(0x360, 0x38,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1212#define MX53_PAD_GPIO_19__FEC_TDATA_3 (_MX53_PAD_GPIO_19__FEC_TDATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
71#define MX53_PAD_KEY_COL3__GPIO_4_12 IOMUX_PAD(0x364, 0x3C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1213#define MX53_PAD_GPIO_19__SRC_INT_BOOT (_MX53_PAD_GPIO_19__SRC_INT_BOOT | MUX_PAD_CTRL(NO_PAD_CTRL))
72#define MX53_PAD_KEY_ROW3__GPIO_4_13 IOMUX_PAD(0x368, 0x40,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1214#define MX53_PAD_KEY_COL0__KPP_COL_0 (_MX53_PAD_KEY_COL0__KPP_COL_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
73#define MX53_PAD_KEY_COL4__GPIO_4_14 IOMUX_PAD(0x36C, 0x44,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1215#define MX53_PAD_KEY_COL0__GPIO4_6 (_MX53_PAD_KEY_COL0__GPIO4_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
74#define MX53_PAD_KEY_ROW4__GPIO_4_15 IOMUX_PAD(0x370, 0x48,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1216#define MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC (_MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
75#define MX53_PAD_NVCC_KEYPAD__NVCC_KEYPAD IOMUX_PAD(0x374, NON_MUX_I,IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1217#define MX53_PAD_KEY_COL0__UART4_TXD_MUX (_MX53_PAD_KEY_COL0__UART4_TXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL))
76#define MX53_PAD_DI0_DISP_CLK__GPIO_4_16 IOMUX_PAD(0x378, 0x4C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1218#define MX53_PAD_KEY_COL0__ECSPI1_SCLK (_MX53_PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
77#define MX53_PAD_DI0_PIN15__GPIO_4_17 IOMUX_PAD(0x37C, 0x50,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1219#define MX53_PAD_KEY_COL0__FEC_RDATA_3 (_MX53_PAD_KEY_COL0__FEC_RDATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
78#define MX53_PAD_DI0_PIN2__GPIO_4_18 IOMUX_PAD(0x380, 0x54,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1220#define MX53_PAD_KEY_COL0__SRC_ANY_PU_RST (_MX53_PAD_KEY_COL0__SRC_ANY_PU_RST | MUX_PAD_CTRL(NO_PAD_CTRL))
79#define MX53_PAD_DI0_PIN3__GPIO_4_19 IOMUX_PAD(0x384, 0x58,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1221#define MX53_PAD_KEY_ROW0__KPP_ROW_0 (_MX53_PAD_KEY_ROW0__KPP_ROW_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
80#define MX53_PAD_DI0_PIN4__GPIO_4_20 IOMUX_PAD(0x388, 0x5C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1222#define MX53_PAD_KEY_ROW0__GPIO4_7 (_MX53_PAD_KEY_ROW0__GPIO4_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
81#define MX53_PAD_DISP0_DAT0__GPIO_4_21 IOMUX_PAD(0x38C, 0x60,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1223#define MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD (_MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
82#define MX53_PAD_DISP0_DAT1__GPIO_4_22 IOMUX_PAD(0x390, 0x64,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1224#define MX53_PAD_KEY_ROW0__UART4_RXD_MUX (_MX53_PAD_KEY_ROW0__UART4_RXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL))
83#define MX53_PAD_DISP0_DAT2__GPIO_4_23 IOMUX_PAD(0x394, 0x68,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1225#define MX53_PAD_KEY_ROW0__ECSPI1_MOSI (_MX53_PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
84#define MX53_PAD_DISP0_DAT3__GPIO_4_24 IOMUX_PAD(0x398, 0x6C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1226#define MX53_PAD_KEY_ROW0__FEC_TX_ER (_MX53_PAD_KEY_ROW0__FEC_TX_ER | MUX_PAD_CTRL(NO_PAD_CTRL))
85#define MX53_PAD_DISP0_DAT4__GPIO_4_25 IOMUX_PAD(0x39C, 0x70,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1227#define MX53_PAD_KEY_COL1__KPP_COL_1 (_MX53_PAD_KEY_COL1__KPP_COL_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
86#define MX53_PAD_DISP0_DAT5__GPIO_4_26 IOMUX_PAD(0x3A0, 0x74,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1228#define MX53_PAD_KEY_COL1__GPIO4_8 (_MX53_PAD_KEY_COL1__GPIO4_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
87#define MX53_PAD_DISP0_DAT6__GPIO_4_27 IOMUX_PAD(0x3A4, 0x78,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1229#define MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS (_MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
88#define MX53_PAD_DISP0_DAT7__GPIO_4_28 IOMUX_PAD(0x3A8, 0x7C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1230#define MX53_PAD_KEY_COL1__UART5_TXD_MUX (_MX53_PAD_KEY_COL1__UART5_TXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL))
89#define MX53_PAD_DISP0_DAT8__GPIO_4_29 IOMUX_PAD(0x3AC, 0x80,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1231#define MX53_PAD_KEY_COL1__ECSPI1_MISO (_MX53_PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
90#define MX53_PAD_DISP0_DAT9__GPIO_4_30 IOMUX_PAD(0x3B0, 0x84,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1232#define MX53_PAD_KEY_COL1__FEC_RX_CLK (_MX53_PAD_KEY_COL1__FEC_RX_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
91#define MX53_PAD_DISP0_DAT10__GPIO_4_31 IOMUX_PAD(0x3B4, 0x88,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1233#define MX53_PAD_KEY_COL1__USBPHY1_TXREADY (_MX53_PAD_KEY_COL1__USBPHY1_TXREADY | MUX_PAD_CTRL(NO_PAD_CTRL))
92#define MX53_PAD_DISP0_DAT11__GPIO_5_5 IOMUX_PAD(0x3B8, 0x8C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1234#define MX53_PAD_KEY_ROW1__KPP_ROW_1 (_MX53_PAD_KEY_ROW1__KPP_ROW_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
93#define MX53_PAD_DISP0_DAT12__GPIO_5_6 IOMUX_PAD(0x3BC, 0x90,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1235#define MX53_PAD_KEY_ROW1__GPIO4_9 (_MX53_PAD_KEY_ROW1__GPIO4_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
94#define MX53_PAD_DISP0_DAT13__GPIO_5_7 IOMUX_PAD(0x3C0, 0x94,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1236#define MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD (_MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
95#define MX53_PAD_DISP0_DAT14__GPIO_5_8 IOMUX_PAD(0x3C4, 0x98,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1237#define MX53_PAD_KEY_ROW1__UART5_RXD_MUX (_MX53_PAD_KEY_ROW1__UART5_RXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL))
96#define MX53_PAD_DISP0_DAT15__GPIO_5_9 IOMUX_PAD(0x3C8, 0x9C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1238#define MX53_PAD_KEY_ROW1__ECSPI1_SS0 (_MX53_PAD_KEY_ROW1__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
97#define MX53_PAD_DISP0_DAT16__GPIO_5_10 IOMUX_PAD(0x3CC, 0xA0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1239#define MX53_PAD_KEY_ROW1__FEC_COL (_MX53_PAD_KEY_ROW1__FEC_COL | MUX_PAD_CTRL(NO_PAD_CTRL))
98#define MX53_PAD_DISP0_DAT17__GPIO_5_11 IOMUX_PAD(0x3D0, 0xA4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1240#define MX53_PAD_KEY_ROW1__USBPHY1_RXVALID (_MX53_PAD_KEY_ROW1__USBPHY1_RXVALID | MUX_PAD_CTRL(NO_PAD_CTRL))
99#define MX53_PAD_DISP0_DAT18__GPIO_5_12 IOMUX_PAD(0x3D4, 0xA8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1241#define MX53_PAD_KEY_COL2__KPP_COL_2 (_MX53_PAD_KEY_COL2__KPP_COL_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
100#define MX53_PAD_DISP0_DAT19__GPIO_5_13 IOMUX_PAD(0x3D8, 0xAC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1242#define MX53_PAD_KEY_COL2__GPIO4_10 (_MX53_PAD_KEY_COL2__GPIO4_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
101#define MX53_PAD_DISP0_DAT20__GPIO_5_14 IOMUX_PAD(0x3DC, 0xB0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1243#define MX53_PAD_KEY_COL2__CAN1_TXCAN (_MX53_PAD_KEY_COL2__CAN1_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
102#define MX53_PAD_DISP0_DAT21__GPIO_5_15 IOMUX_PAD(0x3E0, 0xB4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1244#define MX53_PAD_KEY_COL2__FEC_MDIO (_MX53_PAD_KEY_COL2__FEC_MDIO | MUX_PAD_CTRL(NO_PAD_CTRL))
103#define MX53_PAD_DISP0_DAT22__GPIO_5_16 IOMUX_PAD(0x3E4, 0xB8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1245#define MX53_PAD_KEY_COL2__ECSPI1_SS1 (_MX53_PAD_KEY_COL2__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
104#define MX53_PAD_DISP0_DAT23__GPIO_5_17 IOMUX_PAD(0x3E8, 0xBC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1246#define MX53_PAD_KEY_COL2__FEC_RDATA_2 (_MX53_PAD_KEY_COL2__FEC_RDATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
105#define MX53_PAD_CSI0_PIXCLK__GPIO_5_18 IOMUX_PAD(0x3EC, 0xC0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1247#define MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE (_MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE | MUX_PAD_CTRL(NO_PAD_CTRL))
106#define MX53_PAD_CSI0_MCLK__GPIO_5_19 IOMUX_PAD(0x3F0, 0xC4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1248#define MX53_PAD_KEY_ROW2__KPP_ROW_2 (_MX53_PAD_KEY_ROW2__KPP_ROW_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
107#define MX53_PAD_CSI0_DATA_EN__GPIO_5_20 IOMUX_PAD(0x3F4, 0xC8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1249#define MX53_PAD_KEY_ROW2__GPIO4_11 (_MX53_PAD_KEY_ROW2__GPIO4_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
108#define MX53_PAD_CSI0_VSYNC__GPIO_5_21 IOMUX_PAD(0x3F8, 0xCC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1250#define MX53_PAD_KEY_ROW2__CAN1_RXCAN (_MX53_PAD_KEY_ROW2__CAN1_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
109#define MX53_PAD_CSI0_D4__GPIO_5_22 IOMUX_PAD(0x3FC, 0xD0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1251#define MX53_PAD_KEY_ROW2__FEC_MDC (_MX53_PAD_KEY_ROW2__FEC_MDC | MUX_PAD_CTRL(NO_PAD_CTRL))
110#define MX53_PAD_CSI0_D5__GPIO_5_23 IOMUX_PAD(0x400, 0xD4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1252#define MX53_PAD_KEY_ROW2__ECSPI1_SS2 (_MX53_PAD_KEY_ROW2__ECSPI1_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
111#define MX53_PAD_CSI0_D6__GPIO_5_24 IOMUX_PAD(0x404, 0xD8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1253#define MX53_PAD_KEY_ROW2__FEC_TDATA_2 (_MX53_PAD_KEY_ROW2__FEC_TDATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
112#define MX53_PAD_CSI0_D7__GPIO_5_25 IOMUX_PAD(0x408, 0xDC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1254#define MX53_PAD_KEY_ROW2__USBPHY1_RXERROR (_MX53_PAD_KEY_ROW2__USBPHY1_RXERROR | MUX_PAD_CTRL(NO_PAD_CTRL))
113#define MX53_PAD_CSI0_D8__GPIO_5_26 IOMUX_PAD(0x40C, 0xE0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1255#define MX53_PAD_KEY_COL3__KPP_COL_3 (_MX53_PAD_KEY_COL3__KPP_COL_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
114#define MX53_PAD_CSI0_D9__GPIO_5_27 IOMUX_PAD(0x410, 0xE4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1256#define MX53_PAD_KEY_COL3__GPIO4_12 (_MX53_PAD_KEY_COL3__GPIO4_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
115#define MX53_PAD_CSI0_D10__GPIO_5_28 IOMUX_PAD(0x414, 0xE8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1257#define MX53_PAD_KEY_COL3__USBOH3_H2_DP (_MX53_PAD_KEY_COL3__USBOH3_H2_DP | MUX_PAD_CTRL(NO_PAD_CTRL))
116#define MX53_PAD_CSI0_D11__GPIO_5_29 IOMUX_PAD(0x418, 0xEC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1258#define MX53_PAD_KEY_COL3__SPDIF_IN1 (_MX53_PAD_KEY_COL3__SPDIF_IN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
117#define MX53_PAD_CSI0_D12__GPIO_5_30 IOMUX_PAD(0x41C, 0xF0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1259#define MX53_PAD_KEY_COL3__I2C2_SCL (_MX53_PAD_KEY_COL3__I2C2_SCL | MUX_PAD_CTRL(NO_PAD_CTRL))
118#define MX53_PAD_CSI0_D13__GPIO_5_31 IOMUX_PAD(0x420, 0xF4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1260#define MX53_PAD_KEY_COL3__ECSPI1_SS3 (_MX53_PAD_KEY_COL3__ECSPI1_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
119#define MX53_PAD_CSI0_D14__GPIO_6_0 IOMUX_PAD(0x424, 0xF8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1261#define MX53_PAD_KEY_COL3__FEC_CRS (_MX53_PAD_KEY_COL3__FEC_CRS | MUX_PAD_CTRL(NO_PAD_CTRL))
120#define MX53_PAD_CSI0_D15__GPIO_6_1 IOMUX_PAD(0x428, 0xFC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1262#define MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK (_MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK | MUX_PAD_CTRL(NO_PAD_CTRL))
121#define MX53_PAD_CSI0_D16__GPIO_6_2 IOMUX_PAD(0x42C, 0x100,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1263#define MX53_PAD_KEY_ROW3__KPP_ROW_3 (_MX53_PAD_KEY_ROW3__KPP_ROW_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
122#define MX53_PAD_CSI0_D17__GPIO_6_3 IOMUX_PAD(0x430, 0x104,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1264#define MX53_PAD_KEY_ROW3__GPIO4_13 (_MX53_PAD_KEY_ROW3__GPIO4_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
123#define MX53_PAD_CSI0_D18__GPIO_6_4 IOMUX_PAD(0x434, 0x108,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1265#define MX53_PAD_KEY_ROW3__USBOH3_H2_DM (_MX53_PAD_KEY_ROW3__USBOH3_H2_DM | MUX_PAD_CTRL(NO_PAD_CTRL))
124#define MX53_PAD_CSI0_D19__GPIO_6_5 IOMUX_PAD(0x438, 0x10C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1266#define MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK (_MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
125#define MX53_PAD_NVCC_CSI0__NVCC_CSI0 IOMUX_PAD(0x43C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1267#define MX53_PAD_KEY_ROW3__I2C2_SDA (_MX53_PAD_KEY_ROW3__I2C2_SDA | MUX_PAD_CTRL(NO_PAD_CTRL))
126#define MX53_PAD_JTAG_TMS__JTAG_TMS IOMUX_PAD(0x440, NON_MUX_I,IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1268#define MX53_PAD_KEY_ROW3__OSC32K_32K_OUT (_MX53_PAD_KEY_ROW3__OSC32K_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
127#define MX53_PAD_JTAG_MOD__JTAG_MOD IOMUX_PAD(0x444, NON_MUX_I,IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1269#define MX53_PAD_KEY_ROW3__CCM_PLL4_BYP (_MX53_PAD_KEY_ROW3__CCM_PLL4_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
128#define MX53_PAD_JTAG_TRSTB__JTAG_TRSTB IOMUX_PAD(0x448, NON_MUX_I,IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1270#define MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0 (_MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
129#define MX53_PAD_JTAG_TDI__JTAG_TDI IOMUX_PAD(0x44C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1271#define MX53_PAD_KEY_COL4__KPP_COL_4 (_MX53_PAD_KEY_COL4__KPP_COL_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
130#define MX53_PAD_JTAG_TCK__JTAG_TCK IOMUX_PAD(0x450, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1272#define MX53_PAD_KEY_COL4__GPIO4_14 (_MX53_PAD_KEY_COL4__GPIO4_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
131#define MX53_PAD_JTAG_TDO__JTAG_TDO IOMUX_PAD(0x454, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1273#define MX53_PAD_KEY_COL4__CAN2_TXCAN (_MX53_PAD_KEY_COL4__CAN2_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
132#define MX53_PAD_EIM_A25__GPIO_5_2 IOMUX_PAD(0x458, 0x110,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1274#define MX53_PAD_KEY_COL4__IPU_SISG_4 (_MX53_PAD_KEY_COL4__IPU_SISG_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
133#define MX53_PAD_EIM_EB2__GPIO_2_30 IOMUX_PAD(0x45C, 0x114,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1275#define MX53_PAD_KEY_COL4__UART5_RTS (_MX53_PAD_KEY_COL4__UART5_RTS | MUX_PAD_CTRL(NO_PAD_CTRL))
134#define MX53_PAD_EIM_D16__GPIO_3_16 IOMUX_PAD(0x460, 0x118,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1276#define MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC (_MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
135#define MX53_PAD_EIM_D17__GPIO_3_17 IOMUX_PAD(0x464, 0x11C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1277#define MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1 (_MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
136#define MX53_PAD_EIM_D18__GPIO_3_18 IOMUX_PAD(0x468, 0x120,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1278#define MX53_PAD_KEY_ROW4__KPP_ROW_4 (_MX53_PAD_KEY_ROW4__KPP_ROW_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
137#define MX53_PAD_EIM_D16__CSPI1_SCLK IOMUX_PAD(0x460, 0x118,IOMUX_CONFIG_ALT4, 0x79c, 3, NO_PAD_CTRL) 1279#define MX53_PAD_KEY_ROW4__GPIO4_15 (_MX53_PAD_KEY_ROW4__GPIO4_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
138#define MX53_PAD_EIM_D17__CSPI1_MISO IOMUX_PAD(0x464, 0x11C,IOMUX_CONFIG_ALT4, 0x7a0, 3, NO_PAD_CTRL) 1280#define MX53_PAD_KEY_ROW4__CAN2_RXCAN (_MX53_PAD_KEY_ROW4__CAN2_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
139#define MX53_PAD_EIM_D18__CSPI1_MOSI IOMUX_PAD(0x468, 0x120,IOMUX_CONFIG_ALT4, 0x7a4, 3, NO_PAD_CTRL) 1281#define MX53_PAD_KEY_ROW4__IPU_SISG_5 (_MX53_PAD_KEY_ROW4__IPU_SISG_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
140#define MX53_PAD_EIM_D19__GPIO_3_19 IOMUX_PAD(0x46C, 0x124,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1282#define MX53_PAD_KEY_ROW4__UART5_CTS (_MX53_PAD_KEY_ROW4__UART5_CTS | MUX_PAD_CTRL(NO_PAD_CTRL))
141#define MX53_PAD_EIM_D20__GPIO_3_20 IOMUX_PAD(0x470, 0x128,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1283#define MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR (_MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
142#define MX53_PAD_EIM_D21__GPIO_3_21 IOMUX_PAD(0x474, 0x12C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1284#define MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID (_MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID | MUX_PAD_CTRL(NO_PAD_CTRL))
143#define MX53_PAD_EIM_D22__GPIO_3_22 IOMUX_PAD(0x478, 0x130,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1285#define MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK (_MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
144#define MX53_PAD_EIM_D23__GPIO_3_23 IOMUX_PAD(0x47C, 0x134,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1286#define MX53_PAD_DI0_DISP_CLK__GPIO4_16 (_MX53_PAD_DI0_DISP_CLK__GPIO4_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
145#define MX53_PAD_EIM_EB3__GPIO_2_31 IOMUX_PAD(0x480, 0x138,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1287#define MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR (_MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR | MUX_PAD_CTRL(NO_PAD_CTRL))
146#define MX53_PAD_EIM_D24__GPIO_3_24 IOMUX_PAD(0x484, 0x13C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1288#define MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 (_MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
147#define MX53_PAD_EIM_D25__GPIO_3_25 IOMUX_PAD(0x488, 0x140,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1289#define MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0 (_MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
148#define MX53_PAD_EIM_D26__GPIO_3_26 IOMUX_PAD(0x48C, 0x144,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1290#define MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID (_MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID | MUX_PAD_CTRL(NO_PAD_CTRL))
149#define MX53_PAD_EIM_D27__GPIO_3_27 IOMUX_PAD(0x490, 0x148,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1291#define MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 (_MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL))
150#define MX53_PAD_EIM_D28__GPIO_3_28 IOMUX_PAD(0x494, 0x14C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1292#define MX53_PAD_DI0_PIN15__GPIO4_17 (_MX53_PAD_DI0_PIN15__GPIO4_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
151#define MX53_PAD_EIM_D29__GPIO_3_29 IOMUX_PAD(0x498, 0x150,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1293#define MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC (_MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
152#define MX53_PAD_EIM_D30__GPIO_3_30 IOMUX_PAD(0x49C, 0x154,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1294#define MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 (_MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
153#define MX53_PAD_EIM_D31__GPIO_3_31 IOMUX_PAD(0x4A0, 0x158,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1295#define MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1 (_MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
154#define MX53_PAD_NVCC_EIM1__NVCC_EIM1 IOMUX_PAD(0x4A4, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1296#define MX53_PAD_DI0_PIN15__USBPHY1_BVALID (_MX53_PAD_DI0_PIN15__USBPHY1_BVALID | MUX_PAD_CTRL(NO_PAD_CTRL))
155#define MX53_PAD_EIM_A24__GPIO_5_4 IOMUX_PAD(0x4A8, 0x15C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1297#define MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 (_MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL))
156#define MX53_PAD_EIM_A23__GPIO_6_6 IOMUX_PAD(0x4AC, 0x160,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1298#define MX53_PAD_DI0_PIN2__GPIO4_18 (_MX53_PAD_DI0_PIN2__GPIO4_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
157#define MX53_PAD_EIM_A22__GPIO_2_16 IOMUX_PAD(0x4B0, 0x164,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1299#define MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD (_MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
158#define MX53_PAD_EIM_A21__GPIO_2_17 IOMUX_PAD(0x4B4, 0x168,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1300#define MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 (_MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
159#define MX53_PAD_EIM_A20__GPIO_2_18 IOMUX_PAD(0x4B8, 0x16C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1301#define MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2 (_MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
160#define MX53_PAD_EIM_A19__GPIO_2_19 IOMUX_PAD(0x4BC, 0x170,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1302#define MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION (_MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION | MUX_PAD_CTRL(NO_PAD_CTRL))
161#define MX53_PAD_EIM_A18__GPIO_2_20 IOMUX_PAD(0x4C0, 0x174,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1303#define MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 (_MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL))
162#define MX53_PAD_EIM_A17__GPIO_2_21 IOMUX_PAD(0x4C4, 0x178,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1304#define MX53_PAD_DI0_PIN3__GPIO4_19 (_MX53_PAD_DI0_PIN3__GPIO4_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
163#define MX53_PAD_EIM_A16__GPIO_2_22 IOMUX_PAD(0x4C8, 0x17C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1305#define MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS (_MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
164#define MX53_PAD_EIM_CS0__GPIO_2_23 IOMUX_PAD(0x4CC, 0x180,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1306#define MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 (_MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
165#define MX53_PAD_EIM_CS1__GPIO_2_24 IOMUX_PAD(0x4D0, 0x184,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1307#define MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3 (_MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
166#define MX53_PAD_EIM_OE__GPIO_2_25 IOMUX_PAD(0x4D4, 0x188,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1308#define MX53_PAD_DI0_PIN3__USBPHY1_IDDIG (_MX53_PAD_DI0_PIN3__USBPHY1_IDDIG | MUX_PAD_CTRL(NO_PAD_CTRL))
167#define MX53_PAD_EIM_RW__GPIO_2_26 IOMUX_PAD(0x4D8, 0x18C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1309#define MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 (_MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 | MUX_PAD_CTRL(NO_PAD_CTRL))
168#define MX53_PAD_EIM_LBA__GPIO_2_27 IOMUX_PAD(0x4DC, 0x190,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1310#define MX53_PAD_DI0_PIN4__GPIO4_20 (_MX53_PAD_DI0_PIN4__GPIO4_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
169#define MX53_PAD_NVCC_EIM4__NVCC_EIM4 IOMUX_PAD(0x4E0, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1311#define MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD (_MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
170#define MX53_PAD_EIM_EB0__GPIO_2_28 IOMUX_PAD(0x4E4, 0x194,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1312#define MX53_PAD_DI0_PIN4__ESDHC1_WP (_MX53_PAD_DI0_PIN4__ESDHC1_WP | MUX_PAD_CTRL(NO_PAD_CTRL))
171#define MX53_PAD_EIM_EB1__GPIO_2_29 IOMUX_PAD(0x4E8, 0x198,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1313#define MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD (_MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD | MUX_PAD_CTRL(NO_PAD_CTRL))
172#define MX53_PAD_EIM_DA0__GPIO_3_0 IOMUX_PAD(0x4EC, 0x19C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1314#define MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4 (_MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
173#define MX53_PAD_EIM_DA1__GPIO_3_1 IOMUX_PAD(0x4F0, 0x1A0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1315#define MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT (_MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT | MUX_PAD_CTRL(NO_PAD_CTRL))
174#define MX53_PAD_EIM_DA2__GPIO_3_2 IOMUX_PAD(0x4F4, 0x1A4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1316#define MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 (_MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
175#define MX53_PAD_EIM_DA3__GPIO_3_3 IOMUX_PAD(0x4F8, 0x1A8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1317#define MX53_PAD_DISP0_DAT0__GPIO4_21 (_MX53_PAD_DISP0_DAT0__GPIO4_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
176#define MX53_PAD_EIM_DA4__GPIO_3_4 IOMUX_PAD(0x4FC, 0x1AC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1318#define MX53_PAD_DISP0_DAT0__CSPI_SCLK (_MX53_PAD_DISP0_DAT0__CSPI_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
177#define MX53_PAD_EIM_DA5__GPIO_3_5 IOMUX_PAD(0x500, 0x1B0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1319#define MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0 (_MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
178#define MX53_PAD_EIM_DA6__GPIO_3_6 IOMUX_PAD(0x504, 0x1B4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1320#define MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN (_MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN | MUX_PAD_CTRL(NO_PAD_CTRL))
179#define MX53_PAD_EIM_DA7__GPIO_3_7 IOMUX_PAD(0x508, 0x1B8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1321#define MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5 (_MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
180#define MX53_PAD_EIM_DA8__GPIO_3_8 IOMUX_PAD(0x50C, 0x1BC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1322#define MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY (_MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY | MUX_PAD_CTRL(NO_PAD_CTRL))
181#define MX53_PAD_EIM_DA9__GPIO_3_9 IOMUX_PAD(0x510, 0x1C0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1323#define MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 (_MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
182#define MX53_PAD_EIM_DA10__GPIO_3_10 IOMUX_PAD(0x514, 0x1C4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1324#define MX53_PAD_DISP0_DAT1__GPIO4_22 (_MX53_PAD_DISP0_DAT1__GPIO4_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
183#define MX53_PAD_EIM_DA11__GPIO_3_11 IOMUX_PAD(0x518, 0x1C8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1325#define MX53_PAD_DISP0_DAT1__CSPI_MOSI (_MX53_PAD_DISP0_DAT1__CSPI_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
184#define MX53_PAD_EIM_DA12__GPIO_3_12 IOMUX_PAD(0x51C, 0x1CC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1326#define MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1 (_MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
185#define MX53_PAD_EIM_DA13__GPIO_3_13 IOMUX_PAD(0x520, 0x1D0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1327#define MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL (_MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL | MUX_PAD_CTRL(NO_PAD_CTRL))
186#define MX53_PAD_EIM_DA14__GPIO_3_14 IOMUX_PAD(0x524, 0x1D4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1328#define MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6 (_MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
187#define MX53_PAD_EIM_DA15__GPIO_3_15 IOMUX_PAD(0x528, 0x1D8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1329#define MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID (_MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID | MUX_PAD_CTRL(NO_PAD_CTRL))
188#define MX53_PAD_NANDF_WE_B__GPIO_6_12 IOMUX_PAD(0x52C, 0x1DC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1330#define MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 (_MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
189#define MX53_PAD_NANDF_RE_B__GPIO_6_13 IOMUX_PAD(0x530, 0x1E0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1331#define MX53_PAD_DISP0_DAT2__GPIO4_23 (_MX53_PAD_DISP0_DAT2__GPIO4_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
190#define MX53_PAD_EIM_WAIT__GPIO_5_0 IOMUX_PAD(0x534, 0x1E4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1332#define MX53_PAD_DISP0_DAT2__CSPI_MISO (_MX53_PAD_DISP0_DAT2__CSPI_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
191#define MX53_PAD_EIM_BCLK__EIM_BCLK IOMUX_PAD(0x538, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1333#define MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2 (_MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
192#define MX53_PAD_NVCC_EIM7__NVCC_EIM7 IOMUX_PAD(0x53C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1334#define MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE (_MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE | MUX_PAD_CTRL(NO_PAD_CTRL))
193#define MX53_PAD_LVDS1_TX3_P__GPIO_6_22 IOMUX_PAD(NON_PAD_I, 0x1EC, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1335#define MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7 (_MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
194#define MX53_PAD_LVDS1_TX2_P__GPIO_6_24 IOMUX_PAD(NON_PAD_I, 0x1F0, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1336#define MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE (_MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE | MUX_PAD_CTRL(NO_PAD_CTRL))
195#define MX53_PAD_LVDS1_CLK_P__GPIO_6_26 IOMUX_PAD(NON_PAD_I, 0x1F4, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1337#define MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 (_MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
196#define MX53_PAD_LVDS1_TX1_P__GPIO_6_28 IOMUX_PAD(NON_PAD_I, 0x1F8, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1338#define MX53_PAD_DISP0_DAT3__GPIO4_24 (_MX53_PAD_DISP0_DAT3__GPIO4_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
197#define MX53_PAD_LVDS1_TX0_P__GPIO_6_30 IOMUX_PAD(NON_PAD_I, 0x1FC, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1339#define MX53_PAD_DISP0_DAT3__CSPI_SS0 (_MX53_PAD_DISP0_DAT3__CSPI_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
198#define MX53_PAD_LVDS0_TX3_P__GPIO_7_22 IOMUX_PAD(NON_PAD_I, 0x200, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1340#define MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3 (_MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
199#define MX53_PAD_LVDS0_CLK_P__GPIO_7_24 IOMUX_PAD(NON_PAD_I, 0x204, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1341#define MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR (_MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR | MUX_PAD_CTRL(NO_PAD_CTRL))
200#define MX53_PAD_LVDS0_TX2_P__GPIO_7_26 IOMUX_PAD(NON_PAD_I, 0x208, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1342#define MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8 (_MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
201#define MX53_PAD_LVDS0_TX1_P__GPIO_7_28 IOMUX_PAD(NON_PAD_I, 0x20C, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1343#define MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR (_MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR | MUX_PAD_CTRL(NO_PAD_CTRL))
202#define MX53_PAD_LVDS0_TX0_P__GPIO_7_30 IOMUX_PAD(NON_PAD_I, 0x210, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1344#define MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 (_MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
203#define MX53_PAD_GPIO_10__GPIO_4_0 IOMUX_PAD(0x540, 0x214, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1345#define MX53_PAD_DISP0_DAT4__GPIO4_25 (_MX53_PAD_DISP0_DAT4__GPIO4_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
204#define MX53_PAD_GPIO_11__GPIO_4_1 IOMUX_PAD(0x544, 0x218, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1346#define MX53_PAD_DISP0_DAT4__CSPI_SS1 (_MX53_PAD_DISP0_DAT4__CSPI_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
205#define MX53_PAD_GPIO_12__GPIO_4_2 IOMUX_PAD(0x548, 0x21C, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1347#define MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4 (_MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
206#define MX53_PAD_GPIO_13__GPIO_4_3 IOMUX_PAD(0x54C, 0x220, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1348#define MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB (_MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB | MUX_PAD_CTRL(NO_PAD_CTRL))
207#define MX53_PAD_GPIO_14__GPIO_4_4 IOMUX_PAD(0x550, 0x224, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1349#define MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9 (_MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
208#define MX53_PAD_DRAM_DQM3__DRAM_DQM3 IOMUX_PAD(0x554, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1350#define MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK (_MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK | MUX_PAD_CTRL(NO_PAD_CTRL))
209#define MX53_PAD_DRAM_SDQS3__DRAM_SDQS3 IOMUX_PAD(0x558, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1351#define MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 (_MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
210#define MX53_PAD_DRAM_SDCKE1__DRAM_SDCKE1 IOMUX_PAD(0x55C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1352#define MX53_PAD_DISP0_DAT5__GPIO4_26 (_MX53_PAD_DISP0_DAT5__GPIO4_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
211#define MX53_PAD_DRAM_DQM2__DRAM_DQM2 IOMUX_PAD(0x560, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1353#define MX53_PAD_DISP0_DAT5__CSPI_SS2 (_MX53_PAD_DISP0_DAT5__CSPI_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
212#define MX53_PAD_DRAM_SDODT1__DRAM_SDODT1 IOMUX_PAD(0x564, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1354#define MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5 (_MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
213#define MX53_PAD_DRAM_SDQS2__DRAM_SDQS2 IOMUX_PAD(0x568, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1355#define MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS (_MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS | MUX_PAD_CTRL(NO_PAD_CTRL))
214#define MX53_PAD_DRAM_RESET__DRAM_RESET IOMUX_PAD(0x56C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1356#define MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10 (_MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
215#define MX53_PAD_DRAM_SDCLK1__DRAM_SDCLK1 IOMUX_PAD(0x570, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1357#define MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0 (_MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
216#define MX53_PAD_DRAM_CAS__DRAM_CAS IOMUX_PAD(0x574, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1358#define MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 (_MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
217#define MX53_PAD_DRAM_SDCLK0__DRAM_SDCLK0 IOMUX_PAD(0x578, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1359#define MX53_PAD_DISP0_DAT6__GPIO4_27 (_MX53_PAD_DISP0_DAT6__GPIO4_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
218#define MX53_PAD_DRAM_SDQS0__DRAM_SDQS0 IOMUX_PAD(0x57C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1360#define MX53_PAD_DISP0_DAT6__CSPI_SS3 (_MX53_PAD_DISP0_DAT6__CSPI_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
219#define MX53_PAD_DRAM_SDODT0__DRAM_SDODT0 IOMUX_PAD(0x580, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1361#define MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6 (_MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
220#define MX53_PAD_DRAM_DQM0__DRAM_DQM0 IOMUX_PAD(0x584, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1362#define MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE (_MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE | MUX_PAD_CTRL(NO_PAD_CTRL))
221#define MX53_PAD_DRAM_RAS__DRAM_RAS IOMUX_PAD(0x588, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1363#define MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11 (_MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
222#define MX53_PAD_DRAM_SDCKE0__DRAM_SDCKE0 IOMUX_PAD(0x58C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1364#define MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1 (_MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
223#define MX53_PAD_DRAM_SDQS1__DRAM_SDQS1 IOMUX_PAD(0x590, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1365#define MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 (_MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
224#define MX53_PAD_DRAM_DQM1__DRAM_DQM1 IOMUX_PAD(0x594, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1366#define MX53_PAD_DISP0_DAT7__GPIO4_28 (_MX53_PAD_DISP0_DAT7__GPIO4_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
225#define MX53_PAD_PMIC_ON_REQ__PMIC_ON_REQ IOMUX_PAD(0x598, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1367#define MX53_PAD_DISP0_DAT7__CSPI_RDY (_MX53_PAD_DISP0_DAT7__CSPI_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
226#define MX53_PAD_PMIC_STBY_REQ__PMIC_STBY_REQ IOMUX_PAD(0x59C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1368#define MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7 (_MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
227#define MX53_PAD_NANDF_CLE__GPIO_6_7 IOMUX_PAD(0x5A0, 0x228,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1369#define MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 (_MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
228#define MX53_PAD_NANDF_ALE__GPIO_6_8 IOMUX_PAD(0x5A4, 0x22C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1370#define MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12 (_MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
229#define MX53_PAD_NANDF_WP_B__GPIO_6_9 IOMUX_PAD(0x5A8, 0x230,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1371#define MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID (_MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID | MUX_PAD_CTRL(NO_PAD_CTRL))
230#define MX53_PAD_NANDF_RB0__GPIO_6_10 IOMUX_PAD(0x5AC, 0x234,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1372#define MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 (_MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
231#define MX53_PAD_NANDF_CS0__GPIO_6_11 IOMUX_PAD(0x5B0, 0x238,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1373#define MX53_PAD_DISP0_DAT8__GPIO4_29 (_MX53_PAD_DISP0_DAT8__GPIO4_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
232#define MX53_PAD_NANDF_CS1__GPIO_6_14 IOMUX_PAD(0x5B4, 0x23C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1374#define MX53_PAD_DISP0_DAT8__PWM1_PWMO (_MX53_PAD_DISP0_DAT8__PWM1_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
233#define MX53_PAD_NANDF_CS2__GPIO_6_15 IOMUX_PAD(0x5B8, 0x240,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1375#define MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B (_MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
234#define MX53_PAD_NANDF_CS3__GPIO_6_16 IOMUX_PAD(0x5BC, 0x244,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1376#define MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 (_MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
235#define MX53_PAD_NVCC_NANDF__NVCC_NANDF IOMUX_PAD(0x5C0, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1377#define MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13 (_MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
236#define MX53_PAD_FEC_MDIO__GPIO_1_22 IOMUX_PAD(0x5C4, 0x248,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1378#define MX53_PAD_DISP0_DAT8__USBPHY2_AVALID (_MX53_PAD_DISP0_DAT8__USBPHY2_AVALID | MUX_PAD_CTRL(NO_PAD_CTRL))
237#define MX53_PAD_FEC_REF_CLK__GPIO_1_23 IOMUX_PAD(0x5C8, 0x24C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1379#define MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 (_MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
238#define MX53_PAD_FEC_RX_ER__GPIO_1_24 IOMUX_PAD(0x5CC, 0x250,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1380#define MX53_PAD_DISP0_DAT9__GPIO4_30 (_MX53_PAD_DISP0_DAT9__GPIO4_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
239#define MX53_PAD_FEC_CRS_DV__GPIO_1_25 IOMUX_PAD(0x5D0, 0x254,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1381#define MX53_PAD_DISP0_DAT9__PWM2_PWMO (_MX53_PAD_DISP0_DAT9__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
240#define MX53_PAD_FEC_RXD1__GPIO_1_26 IOMUX_PAD(0x5D4, 0x258,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1382#define MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B (_MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
241#define MX53_PAD_FEC_RXD0__GPIO_1_27 IOMUX_PAD(0x5D8, 0x25C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1383#define MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 (_MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
242#define MX53_PAD_FEC_TX_EN__GPIO_1_28 IOMUX_PAD(0x5DC, 0x260,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1384#define MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14 (_MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
243#define MX53_PAD_FEC_TXD1__GPIO_1_29 IOMUX_PAD(0x5E0, 0x264,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1385#define MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0 (_MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
244#define MX53_PAD_FEC_TXD0__GPIO_1_30 IOMUX_PAD(0x5E4, 0x268,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1386#define MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 (_MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
245#define MX53_PAD_FEC_MDC__GPIO_1_31 IOMUX_PAD(0x5E8, 0x26C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1387#define MX53_PAD_DISP0_DAT10__GPIO4_31 (_MX53_PAD_DISP0_DAT10__GPIO4_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
246#define MX53_PAD_NVCC_FEC__NVCC_FEC IOMUX_PAD(0x5EC, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1388#define MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP (_MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP | MUX_PAD_CTRL(NO_PAD_CTRL))
247#define MX53_PAD_ATA_DIOW__GPIO_6_17 IOMUX_PAD(0x5F0, 0x270,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1389#define MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 (_MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
248#define MX53_PAD_ATA_DMACK__GPIO_6_18 IOMUX_PAD(0x5F4, 0x274,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1390#define MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15 (_MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
249#define MX53_PAD_ATA_DMARQ__GPIO_7_0 IOMUX_PAD(0x5F8, 0x278,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1391#define MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1 (_MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
250#define MX53_PAD_ATA_BUFFER_EN__GPIO_7_1 IOMUX_PAD(0x5FC, 0x27C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1392#define MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 (_MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
251#define MX53_PAD_ATA_INTRQ__GPIO_7_2 IOMUX_PAD(0x600, 0x280,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1393#define MX53_PAD_DISP0_DAT11__GPIO5_5 (_MX53_PAD_DISP0_DAT11__GPIO5_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
252#define MX53_PAD_ATA_DIOR__GPIO_7_3 IOMUX_PAD(0x604, 0x284,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1394#define MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT (_MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT | MUX_PAD_CTRL(NO_PAD_CTRL))
253#define MX53_PAD_ATA_RESET_B__GPIO_7_4 IOMUX_PAD(0x608, 0x288,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1395#define MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 (_MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
254#define MX53_PAD_ATA_IORDY__GPIO_7_5 IOMUX_PAD(0x60C, 0x28C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1396#define MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16 (_MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
255#define MX53_PAD_ATA_DA_0__GPIO_7_6 IOMUX_PAD(0x610, 0x290,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1397#define MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2 (_MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
256#define MX53_PAD_ATA_DA_1__GPIO_7_7 IOMUX_PAD(0x614, 0x294,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1398#define MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 (_MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
257#define MX53_PAD_ATA_DA_2__GPIO_7_8 IOMUX_PAD(0x618, 0x298,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1399#define MX53_PAD_DISP0_DAT12__GPIO5_6 (_MX53_PAD_DISP0_DAT12__GPIO5_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
258#define MX53_PAD_ATA_CS_0__GPIO_7_9 IOMUX_PAD(0x61C, 0x29C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1400#define MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK (_MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
259#define MX53_PAD_ATA_CS_1__GPIO_7_10 IOMUX_PAD(0x620, 0x2A0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1401#define MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 (_MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
260#define MX53_PAD_NVCC_ATA2__NVCC_ATA2 IOMUX_PAD(0x624, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1402#define MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17 (_MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
261#define MX53_PAD_ATA_DATA0__GPIO_2_0 IOMUX_PAD(0x628, 0x2A4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1403#define MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3 (_MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
262#define MX53_PAD_ATA_DATA1__GPIO_2_1 IOMUX_PAD(0x62C, 0x2A8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1404#define MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 (_MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
263#define MX53_PAD_ATA_DATA2__GPIO_2_2 IOMUX_PAD(0x630, 0x2AC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1405#define MX53_PAD_DISP0_DAT13__GPIO5_7 (_MX53_PAD_DISP0_DAT13__GPIO5_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
264#define MX53_PAD_ATA_DATA3__GPIO_2_3 IOMUX_PAD(0x634, 0x2B0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1406#define MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS (_MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
265#define MX53_PAD_ATA_DATA4__GPIO_2_4 IOMUX_PAD(0x638, 0x2B4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1407#define MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 (_MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
266#define MX53_PAD_ATA_DATA5__GPIO_2_5 IOMUX_PAD(0x63C, 0x2B8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1408#define MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18 (_MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
267#define MX53_PAD_ATA_DATA6__GPIO_2_6 IOMUX_PAD(0x640, 0x2BC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1409#define MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4 (_MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
268#define MX53_PAD_ATA_DATA7__GPIO_2_7 IOMUX_PAD(0x644, 0x2C0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1410#define MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 (_MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
269#define MX53_PAD_ATA_DATA8__GPIO_2_8 IOMUX_PAD(0x648, 0x2C4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1411#define MX53_PAD_DISP0_DAT14__GPIO5_8 (_MX53_PAD_DISP0_DAT14__GPIO5_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
270#define MX53_PAD_ATA_DATA9__GPIO_2_9 IOMUX_PAD(0x64C, 0x2C8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1412#define MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC (_MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
271#define MX53_PAD_ATA_DATA10__GPIO_2_10 IOMUX_PAD(0x650, 0x2CC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1413#define MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 (_MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
272#define MX53_PAD_ATA_DATA11__GPIO_2_11 IOMUX_PAD(0x654, 0x2D0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1414#define MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19 (_MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
273#define MX53_PAD_ATA_DATA12__GPIO_2_12 IOMUX_PAD(0x658, 0x2D4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1415#define MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5 (_MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
274#define MX53_PAD_ATA_DATA13__GPIO_2_13 IOMUX_PAD(0x65C, 0x2D8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1416#define MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 (_MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
275#define MX53_PAD_ATA_DATA14__GPIO_2_14 IOMUX_PAD(0x660, 0x2DC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1417#define MX53_PAD_DISP0_DAT15__GPIO5_9 (_MX53_PAD_DISP0_DAT15__GPIO5_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
276#define MX53_PAD_ATA_DATA15__GPIO_2_15 IOMUX_PAD(0x664, 0x2E0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1418#define MX53_PAD_DISP0_DAT15__ECSPI1_SS1 (_MX53_PAD_DISP0_DAT15__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
277#define MX53_PAD_NVCC_ATA0__NVCC_ATA0 IOMUX_PAD(0x668, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1419#define MX53_PAD_DISP0_DAT15__ECSPI2_SS1 (_MX53_PAD_DISP0_DAT15__ECSPI2_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
278#define MX53_PAD_SD1_DATA0__GPIO_1_16 IOMUX_PAD(0x66C, 0x2E4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1420#define MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 (_MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
279#define MX53_PAD_SD1_DATA1__GPIO_1_17 IOMUX_PAD(0x670, 0x2E8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1421#define MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20 (_MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
280#define MX53_PAD_SD1_CMD__GPIO_1_18 IOMUX_PAD(0x674, 0x2EC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1422#define MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6 (_MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
281#define MX53_PAD_SD1_DATA2__GPIO_1_19 IOMUX_PAD(0x678, 0x2F0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1423#define MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 (_MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
282#define MX53_PAD_SD1_CLK__GPIO_1_20 IOMUX_PAD(0x67C, 0x2F4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1424#define MX53_PAD_DISP0_DAT16__GPIO5_10 (_MX53_PAD_DISP0_DAT16__GPIO5_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
283#define MX53_PAD_SD1_DATA3__GPIO_1_21 IOMUX_PAD(0x680, 0x2F8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1425#define MX53_PAD_DISP0_DAT16__ECSPI2_MOSI (_MX53_PAD_DISP0_DAT16__ECSPI2_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
284#define MX53_PAD_NVCC_SD1__NVCC_SD1 IOMUX_PAD(0x684, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1426#define MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC (_MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
285#define MX53_PAD_SD2_CLK__GPIO_1_10 IOMUX_PAD(0x688, 0x2FC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1427#define MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 (_MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
286#define MX53_PAD_SD2_CMD__GPIO_1_11 IOMUX_PAD(0x68C, 0x300,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1428#define MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3 (_MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
287#define MX53_PAD_SD2_DATA3__GPIO_1_12 IOMUX_PAD(0x690, 0x304,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1429#define MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21 (_MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
288#define MX53_PAD_SD2_DATA2__GPIO_1_13 IOMUX_PAD(0x694, 0x308,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1430#define MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7 (_MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
289#define MX53_PAD_SD2_DATA1__GPIO_1_14 IOMUX_PAD(0x698, 0x30C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1431#define MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 (_MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
290#define MX53_PAD_SD2_DATA0__GPIO_1_15 IOMUX_PAD(0x69C, 0x310,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1432#define MX53_PAD_DISP0_DAT17__GPIO5_11 (_MX53_PAD_DISP0_DAT17__GPIO5_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
291#define MX53_PAD_NVCC_SD2__NVCC_SD2 IOMUX_PAD(0x6A0, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1433#define MX53_PAD_DISP0_DAT17__ECSPI2_MISO (_MX53_PAD_DISP0_DAT17__ECSPI2_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
292#define MX53_PAD_GPIO_0__GPIO_1_0 IOMUX_PAD(0x6A4, 0x314,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1434#define MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD (_MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
293#define MX53_PAD_GPIO_1__GPIO_1_1 IOMUX_PAD(0x6A8, 0x318,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1435#define MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 (_MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
294#define MX53_PAD_GPIO_9__GPIO_1_9 IOMUX_PAD(0x6AC, 0x31C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1436#define MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4 (_MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
295#define MX53_PAD_GPIO_3__GPIO_1_3 IOMUX_PAD(0x6B0, 0x320,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1437#define MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22 (_MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
296#define MX53_PAD_GPIO_6__GPIO_1_6 IOMUX_PAD(0x6B4, 0x324,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1438#define MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 (_MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
297#define MX53_PAD_GPIO_2__GPIO_1_2 IOMUX_PAD(0x6B8, 0x328,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1439#define MX53_PAD_DISP0_DAT18__GPIO5_12 (_MX53_PAD_DISP0_DAT18__GPIO5_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
298#define MX53_PAD_GPIO_4__GPIO_1_4 IOMUX_PAD(0x6BC, 0x32C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1440#define MX53_PAD_DISP0_DAT18__ECSPI2_SS0 (_MX53_PAD_DISP0_DAT18__ECSPI2_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
299#define MX53_PAD_GPIO_5__GPIO_1_5 IOMUX_PAD(0x6C0, 0x330,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1441#define MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS (_MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
300#define MX53_PAD_GPIO_7__GPIO_1_7 IOMUX_PAD(0x6C4, 0x334,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1442#define MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS (_MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
301#define MX53_PAD_GPIO_8__GPIO_1_8 IOMUX_PAD(0x6C8, 0x338,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1443#define MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5 (_MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
302#define MX53_PAD_GPIO_16__GPIO_7_11 IOMUX_PAD(0x6CC, 0x33C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1444#define MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23 (_MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
303#define MX53_PAD_GPIO_17__GPIO_7_12 IOMUX_PAD(0x6D0, 0x340,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1445#define MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2 (_MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
304#define MX53_PAD_GPIO_18__GPIO_7_13 IOMUX_PAD(0x6D4, 0x344,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1446#define MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 (_MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
305#define MX53_PAD_NVCC_GPIO__NVCC_GPIO IOMUX_PAD(0x6D8, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1447#define MX53_PAD_DISP0_DAT19__GPIO5_13 (_MX53_PAD_DISP0_DAT19__GPIO5_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
306#define MX53_PAD_POR_B__POR_B IOMUX_PAD(0x6DC, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1448#define MX53_PAD_DISP0_DAT19__ECSPI2_SCLK (_MX53_PAD_DISP0_DAT19__ECSPI2_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
307#define MX53_PAD_BOOT_MODE1__BOOT_MODE1 IOMUX_PAD(0x6E0, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1449#define MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD (_MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
308#define MX53_PAD_RESET_IN_B__RESET_IN_B IOMUX_PAD(0x6E4, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1450#define MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC (_MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
309#define MX53_PAD_BOOT_MODE0__BOOT_MODE0 IOMUX_PAD(0x6E8, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1451#define MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6 (_MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
310#define MX53_PAD_TEST_MODE__TEST_MODE IOMUX_PAD(0x6EC, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1452#define MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24 (_MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
311#define MX53_PAD_GRP_ADDDS__GRP_ADDDS IOMUX_PAD(0x6F0, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1453#define MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3 (_MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
312#define MX53_PAD_GRP_DDRMODE_CTL__GRP_DDRMODE_CTL IOMUX_PAD(0x6F4, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1454#define MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 (_MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
313#define MX53_PAD_GRP_DDRPKE__GRP_DDRPKE IOMUX_PAD(0x6FC, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1455#define MX53_PAD_DISP0_DAT20__GPIO5_14 (_MX53_PAD_DISP0_DAT20__GPIO5_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
314#define MX53_PAD_GRP_DDRPK__GRP_DDRPK IOMUX_PAD(0x708, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1456#define MX53_PAD_DISP0_DAT20__ECSPI1_SCLK (_MX53_PAD_DISP0_DAT20__ECSPI1_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
315#define MX53_PAD_GRP_TERM_CTL3__GRP_TERM_CTL3 IOMUX_PAD(0x70C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1457#define MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC (_MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
316#define MX53_PAD_GRP_DDRHYS__GRP_DDRHYS IOMUX_PAD(0x710, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1458#define MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 (_MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
317#define MX53_PAD_GRP_DDRMODE__GRP_DDRMODE IOMUX_PAD(0x714, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1459#define MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25 (_MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
318#define MX53_PAD_GRP_B0DS__GRP_B0DS IOMUX_PAD(0x718, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1460#define MX53_PAD_DISP0_DAT20__SATA_PHY_TDI (_MX53_PAD_DISP0_DAT20__SATA_PHY_TDI | MUX_PAD_CTRL(NO_PAD_CTRL))
319#define MX53_PAD_GRP_B1DS__GRP_B1DS IOMUX_PAD(0x71C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1461#define MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 (_MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
320#define MX53_PAD_GRP_CTLDS__GRP_CTLDS IOMUX_PAD(0x720, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1462#define MX53_PAD_DISP0_DAT21__GPIO5_15 (_MX53_PAD_DISP0_DAT21__GPIO5_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
321#define MX53_PAD_GRP_DDR_TYPE__GRP_DDR_TYPE IOMUX_PAD(0x724, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1463#define MX53_PAD_DISP0_DAT21__ECSPI1_MOSI (_MX53_PAD_DISP0_DAT21__ECSPI1_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
322#define MX53_PAD_GRP_B2DS__GRP_B2DS IOMUX_PAD(0x728, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1464#define MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD (_MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
323#define MX53_PAD_GRP_B3DS__GRP_B3DS IOMUX_PAD(0x72C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1465#define MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 (_MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1466#define MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26 (_MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
1467#define MX53_PAD_DISP0_DAT21__SATA_PHY_TDO (_MX53_PAD_DISP0_DAT21__SATA_PHY_TDO | MUX_PAD_CTRL(NO_PAD_CTRL))
1468#define MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 (_MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
1469#define MX53_PAD_DISP0_DAT22__GPIO5_16 (_MX53_PAD_DISP0_DAT22__GPIO5_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
1470#define MX53_PAD_DISP0_DAT22__ECSPI1_MISO (_MX53_PAD_DISP0_DAT22__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
1471#define MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS (_MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
1472#define MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 (_MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1473#define MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27 (_MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
1474#define MX53_PAD_DISP0_DAT22__SATA_PHY_TCK (_MX53_PAD_DISP0_DAT22__SATA_PHY_TCK | MUX_PAD_CTRL(NO_PAD_CTRL))
1475#define MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 (_MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
1476#define MX53_PAD_DISP0_DAT23__GPIO5_17 (_MX53_PAD_DISP0_DAT23__GPIO5_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
1477#define MX53_PAD_DISP0_DAT23__ECSPI1_SS0 (_MX53_PAD_DISP0_DAT23__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1478#define MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD (_MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
1479#define MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 (_MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1480#define MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28 (_MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
1481#define MX53_PAD_DISP0_DAT23__SATA_PHY_TMS (_MX53_PAD_DISP0_DAT23__SATA_PHY_TMS | MUX_PAD_CTRL(NO_PAD_CTRL))
1482#define MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK (_MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
1483#define MX53_PAD_CSI0_PIXCLK__GPIO5_18 (_MX53_PAD_CSI0_PIXCLK__GPIO5_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
1484#define MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 (_MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1485#define MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29 (_MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
1486#define MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC (_MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
1487#define MX53_PAD_CSI0_MCLK__GPIO5_19 (_MX53_PAD_CSI0_MCLK__GPIO5_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
1488#define MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK (_MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
1489#define MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 (_MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1490#define MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30 (_MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
1491#define MX53_PAD_CSI0_MCLK__TPIU_TRCTL (_MX53_PAD_CSI0_MCLK__TPIU_TRCTL | MUX_PAD_CTRL(NO_PAD_CTRL))
1492#define MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN (_MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
1493#define MX53_PAD_CSI0_DATA_EN__GPIO5_20 (_MX53_PAD_CSI0_DATA_EN__GPIO5_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
1494#define MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 (_MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1495#define MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31 (_MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
1496#define MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK (_MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
1497#define MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC (_MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
1498#define MX53_PAD_CSI0_VSYNC__GPIO5_21 (_MX53_PAD_CSI0_VSYNC__GPIO5_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
1499#define MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 (_MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1500#define MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32 (_MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32 | MUX_PAD_CTRL(NO_PAD_CTRL))
1501#define MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0 (_MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1502#define MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 (_MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
1503#define MX53_PAD_CSI0_DAT4__GPIO5_22 (_MX53_PAD_CSI0_DAT4__GPIO5_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
1504#define MX53_PAD_CSI0_DAT4__KPP_COL_5 (_MX53_PAD_CSI0_DAT4__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
1505#define MX53_PAD_CSI0_DAT4__ECSPI1_SCLK (_MX53_PAD_CSI0_DAT4__ECSPI1_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
1506#define MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP (_MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP | MUX_PAD_CTRL(NO_PAD_CTRL))
1507#define MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC (_MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
1508#define MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33 (_MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33 | MUX_PAD_CTRL(NO_PAD_CTRL))
1509#define MX53_PAD_CSI0_DAT4__TPIU_TRACE_1 (_MX53_PAD_CSI0_DAT4__TPIU_TRACE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1510#define MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 (_MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
1511#define MX53_PAD_CSI0_DAT5__GPIO5_23 (_MX53_PAD_CSI0_DAT5__GPIO5_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
1512#define MX53_PAD_CSI0_DAT5__KPP_ROW_5 (_MX53_PAD_CSI0_DAT5__KPP_ROW_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
1513#define MX53_PAD_CSI0_DAT5__ECSPI1_MOSI (_MX53_PAD_CSI0_DAT5__ECSPI1_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
1514#define MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT (_MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT | MUX_PAD_CTRL(NO_PAD_CTRL))
1515#define MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD (_MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
1516#define MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34 (_MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34 | MUX_PAD_CTRL(NO_PAD_CTRL))
1517#define MX53_PAD_CSI0_DAT5__TPIU_TRACE_2 (_MX53_PAD_CSI0_DAT5__TPIU_TRACE_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1518#define MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 (_MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
1519#define MX53_PAD_CSI0_DAT6__GPIO5_24 (_MX53_PAD_CSI0_DAT6__GPIO5_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
1520#define MX53_PAD_CSI0_DAT6__KPP_COL_6 (_MX53_PAD_CSI0_DAT6__KPP_COL_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
1521#define MX53_PAD_CSI0_DAT6__ECSPI1_MISO (_MX53_PAD_CSI0_DAT6__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
1522#define MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK (_MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
1523#define MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS (_MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
1524#define MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35 (_MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35 | MUX_PAD_CTRL(NO_PAD_CTRL))
1525#define MX53_PAD_CSI0_DAT6__TPIU_TRACE_3 (_MX53_PAD_CSI0_DAT6__TPIU_TRACE_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1526#define MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 (_MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
1527#define MX53_PAD_CSI0_DAT7__GPIO5_25 (_MX53_PAD_CSI0_DAT7__GPIO5_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
1528#define MX53_PAD_CSI0_DAT7__KPP_ROW_6 (_MX53_PAD_CSI0_DAT7__KPP_ROW_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
1529#define MX53_PAD_CSI0_DAT7__ECSPI1_SS0 (_MX53_PAD_CSI0_DAT7__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1530#define MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR (_MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR | MUX_PAD_CTRL(NO_PAD_CTRL))
1531#define MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD (_MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
1532#define MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36 (_MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36 | MUX_PAD_CTRL(NO_PAD_CTRL))
1533#define MX53_PAD_CSI0_DAT7__TPIU_TRACE_4 (_MX53_PAD_CSI0_DAT7__TPIU_TRACE_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
1534#define MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 (_MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
1535#define MX53_PAD_CSI0_DAT8__GPIO5_26 (_MX53_PAD_CSI0_DAT8__GPIO5_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
1536#define MX53_PAD_CSI0_DAT8__KPP_COL_7 (_MX53_PAD_CSI0_DAT8__KPP_COL_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
1537#define MX53_PAD_CSI0_DAT8__ECSPI2_SCLK (_MX53_PAD_CSI0_DAT8__ECSPI2_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
1538#define MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC (_MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
1539#define MX53_PAD_CSI0_DAT8__I2C1_SDA (_MX53_PAD_CSI0_DAT8__I2C1_SDA | MUX_PAD_CTRL(NO_PAD_CTRL))
1540#define MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37 (_MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37 | MUX_PAD_CTRL(NO_PAD_CTRL))
1541#define MX53_PAD_CSI0_DAT8__TPIU_TRACE_5 (_MX53_PAD_CSI0_DAT8__TPIU_TRACE_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
1542#define MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 (_MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
1543#define MX53_PAD_CSI0_DAT9__GPIO5_27 (_MX53_PAD_CSI0_DAT9__GPIO5_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
1544#define MX53_PAD_CSI0_DAT9__KPP_ROW_7 (_MX53_PAD_CSI0_DAT9__KPP_ROW_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
1545#define MX53_PAD_CSI0_DAT9__ECSPI2_MOSI (_MX53_PAD_CSI0_DAT9__ECSPI2_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
1546#define MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR (_MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
1547#define MX53_PAD_CSI0_DAT9__I2C1_SCL (_MX53_PAD_CSI0_DAT9__I2C1_SCL | MUX_PAD_CTRL(NO_PAD_CTRL))
1548#define MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38 (_MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38 | MUX_PAD_CTRL(NO_PAD_CTRL))
1549#define MX53_PAD_CSI0_DAT9__TPIU_TRACE_6 (_MX53_PAD_CSI0_DAT9__TPIU_TRACE_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
1550#define MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 (_MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
1551#define MX53_PAD_CSI0_DAT10__GPIO5_28 (_MX53_PAD_CSI0_DAT10__GPIO5_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
1552#define MX53_PAD_CSI0_DAT10__UART1_TXD_MUX (_MX53_PAD_CSI0_DAT10__UART1_TXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
1553#define MX53_PAD_CSI0_DAT10__ECSPI2_MISO (_MX53_PAD_CSI0_DAT10__ECSPI2_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
1554#define MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC (_MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
1555#define MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 (_MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
1556#define MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39 (_MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39 | MUX_PAD_CTRL(NO_PAD_CTRL))
1557#define MX53_PAD_CSI0_DAT10__TPIU_TRACE_7 (_MX53_PAD_CSI0_DAT10__TPIU_TRACE_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
1558#define MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 (_MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
1559#define MX53_PAD_CSI0_DAT11__GPIO5_29 (_MX53_PAD_CSI0_DAT11__GPIO5_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
1560#define MX53_PAD_CSI0_DAT11__UART1_RXD_MUX (_MX53_PAD_CSI0_DAT11__UART1_RXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
1561#define MX53_PAD_CSI0_DAT11__ECSPI2_SS0 (_MX53_PAD_CSI0_DAT11__ECSPI2_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1562#define MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS (_MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
1563#define MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 (_MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
1564#define MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40 (_MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40 | MUX_PAD_CTRL(NO_PAD_CTRL))
1565#define MX53_PAD_CSI0_DAT11__TPIU_TRACE_8 (_MX53_PAD_CSI0_DAT11__TPIU_TRACE_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
1566#define MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 (_MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
1567#define MX53_PAD_CSI0_DAT12__GPIO5_30 (_MX53_PAD_CSI0_DAT12__GPIO5_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
1568#define MX53_PAD_CSI0_DAT12__UART4_TXD_MUX (_MX53_PAD_CSI0_DAT12__UART4_TXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL))
1569#define MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0 (_MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1570#define MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 (_MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
1571#define MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41 (_MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41 | MUX_PAD_CTRL(NO_PAD_CTRL))
1572#define MX53_PAD_CSI0_DAT12__TPIU_TRACE_9 (_MX53_PAD_CSI0_DAT12__TPIU_TRACE_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
1573#define MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 (_MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
1574#define MX53_PAD_CSI0_DAT13__GPIO5_31 (_MX53_PAD_CSI0_DAT13__GPIO5_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
1575#define MX53_PAD_CSI0_DAT13__UART4_RXD_MUX (_MX53_PAD_CSI0_DAT13__UART4_RXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL))
1576#define MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1 (_MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1577#define MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 (_MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
1578#define MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42 (_MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42 | MUX_PAD_CTRL(NO_PAD_CTRL))
1579#define MX53_PAD_CSI0_DAT13__TPIU_TRACE_10 (_MX53_PAD_CSI0_DAT13__TPIU_TRACE_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
1580#define MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 (_MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
1581#define MX53_PAD_CSI0_DAT14__GPIO6_0 (_MX53_PAD_CSI0_DAT14__GPIO6_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1582#define MX53_PAD_CSI0_DAT14__UART5_TXD_MUX (_MX53_PAD_CSI0_DAT14__UART5_TXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL))
1583#define MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2 (_MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1584#define MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 (_MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
1585#define MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43 (_MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43 | MUX_PAD_CTRL(NO_PAD_CTRL))
1586#define MX53_PAD_CSI0_DAT14__TPIU_TRACE_11 (_MX53_PAD_CSI0_DAT14__TPIU_TRACE_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
1587#define MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 (_MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
1588#define MX53_PAD_CSI0_DAT15__GPIO6_1 (_MX53_PAD_CSI0_DAT15__GPIO6_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1589#define MX53_PAD_CSI0_DAT15__UART5_RXD_MUX (_MX53_PAD_CSI0_DAT15__UART5_RXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL))
1590#define MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3 (_MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1591#define MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 (_MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
1592#define MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44 (_MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44 | MUX_PAD_CTRL(NO_PAD_CTRL))
1593#define MX53_PAD_CSI0_DAT15__TPIU_TRACE_12 (_MX53_PAD_CSI0_DAT15__TPIU_TRACE_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
1594#define MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 (_MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
1595#define MX53_PAD_CSI0_DAT16__GPIO6_2 (_MX53_PAD_CSI0_DAT16__GPIO6_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1596#define MX53_PAD_CSI0_DAT16__UART4_RTS (_MX53_PAD_CSI0_DAT16__UART4_RTS | MUX_PAD_CTRL(NO_PAD_CTRL))
1597#define MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4 (_MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
1598#define MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 (_MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
1599#define MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45 (_MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45 | MUX_PAD_CTRL(NO_PAD_CTRL))
1600#define MX53_PAD_CSI0_DAT16__TPIU_TRACE_13 (_MX53_PAD_CSI0_DAT16__TPIU_TRACE_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
1601#define MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 (_MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
1602#define MX53_PAD_CSI0_DAT17__GPIO6_3 (_MX53_PAD_CSI0_DAT17__GPIO6_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1603#define MX53_PAD_CSI0_DAT17__UART4_CTS (_MX53_PAD_CSI0_DAT17__UART4_CTS | MUX_PAD_CTRL(NO_PAD_CTRL))
1604#define MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5 (_MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
1605#define MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 (_MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
1606#define MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46 (_MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46 | MUX_PAD_CTRL(NO_PAD_CTRL))
1607#define MX53_PAD_CSI0_DAT17__TPIU_TRACE_14 (_MX53_PAD_CSI0_DAT17__TPIU_TRACE_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
1608#define MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 (_MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
1609#define MX53_PAD_CSI0_DAT18__GPIO6_4 (_MX53_PAD_CSI0_DAT18__GPIO6_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
1610#define MX53_PAD_CSI0_DAT18__UART5_RTS (_MX53_PAD_CSI0_DAT18__UART5_RTS | MUX_PAD_CTRL(NO_PAD_CTRL))
1611#define MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6 (_MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
1612#define MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 (_MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
1613#define MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47 (_MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47 | MUX_PAD_CTRL(NO_PAD_CTRL))
1614#define MX53_PAD_CSI0_DAT18__TPIU_TRACE_15 (_MX53_PAD_CSI0_DAT18__TPIU_TRACE_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
1615#define MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 (_MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
1616#define MX53_PAD_CSI0_DAT19__GPIO6_5 (_MX53_PAD_CSI0_DAT19__GPIO6_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
1617#define MX53_PAD_CSI0_DAT19__UART5_CTS (_MX53_PAD_CSI0_DAT19__UART5_CTS | MUX_PAD_CTRL(NO_PAD_CTRL))
1618#define MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7 (_MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
1619#define MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 (_MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
1620#define MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48 (_MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48 | MUX_PAD_CTRL(NO_PAD_CTRL))
1621#define MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK (_MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK | MUX_PAD_CTRL(NO_PAD_CTRL))
1622#define MX53_PAD_EIM_A25__EMI_WEIM_A_25 (_MX53_PAD_EIM_A25__EMI_WEIM_A_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
1623#define MX53_PAD_EIM_A25__GPIO5_2 (_MX53_PAD_EIM_A25__GPIO5_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1624#define MX53_PAD_EIM_A25__ECSPI2_RDY (_MX53_PAD_EIM_A25__ECSPI2_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
1625#define MX53_PAD_EIM_A25__IPU_DI1_PIN12 (_MX53_PAD_EIM_A25__IPU_DI1_PIN12 | MUX_PAD_CTRL(NO_PAD_CTRL))
1626#define MX53_PAD_EIM_A25__CSPI_SS1 (_MX53_PAD_EIM_A25__CSPI_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1627#define MX53_PAD_EIM_A25__IPU_DI0_D1_CS (_MX53_PAD_EIM_A25__IPU_DI0_D1_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
1628#define MX53_PAD_EIM_A25__USBPHY1_BISTOK (_MX53_PAD_EIM_A25__USBPHY1_BISTOK | MUX_PAD_CTRL(NO_PAD_CTRL))
1629#define MX53_PAD_EIM_EB2__EMI_WEIM_EB_2 (_MX53_PAD_EIM_EB2__EMI_WEIM_EB_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1630#define MX53_PAD_EIM_EB2__GPIO2_30 (_MX53_PAD_EIM_EB2__GPIO2_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
1631#define MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK (_MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
1632#define MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS (_MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
1633#define MX53_PAD_EIM_EB2__ECSPI1_SS0 (_MX53_PAD_EIM_EB2__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1634#define MX53_PAD_EIM_EB2__I2C2_SCL (_MX53_PAD_EIM_EB2__I2C2_SCL | MUX_PAD_CTRL(NO_PAD_CTRL))
1635#define MX53_PAD_EIM_D16__EMI_WEIM_D_16 (_MX53_PAD_EIM_D16__EMI_WEIM_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
1636#define MX53_PAD_EIM_D16__GPIO3_16 (_MX53_PAD_EIM_D16__GPIO3_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
1637#define MX53_PAD_EIM_D16__IPU_DI0_PIN5 (_MX53_PAD_EIM_D16__IPU_DI0_PIN5 | MUX_PAD_CTRL(NO_PAD_CTRL))
1638#define MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK (_MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
1639#define MX53_PAD_EIM_D16__ECSPI1_SCLK (_MX53_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
1640#define MX53_PAD_EIM_D16__I2C2_SDA (_MX53_PAD_EIM_D16__I2C2_SDA | MUX_PAD_CTRL(NO_PAD_CTRL))
1641#define MX53_PAD_EIM_D17__EMI_WEIM_D_17 (_MX53_PAD_EIM_D17__EMI_WEIM_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
1642#define MX53_PAD_EIM_D17__GPIO3_17 (_MX53_PAD_EIM_D17__GPIO3_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
1643#define MX53_PAD_EIM_D17__IPU_DI0_PIN6 (_MX53_PAD_EIM_D17__IPU_DI0_PIN6 | MUX_PAD_CTRL(NO_PAD_CTRL))
1644#define MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN (_MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN | MUX_PAD_CTRL(NO_PAD_CTRL))
1645#define MX53_PAD_EIM_D17__ECSPI1_MISO (_MX53_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
1646#define MX53_PAD_EIM_D17__I2C3_SCL (_MX53_PAD_EIM_D17__I2C3_SCL | MUX_PAD_CTRL(NO_PAD_CTRL))
1647#define MX53_PAD_EIM_D18__EMI_WEIM_D_18 (_MX53_PAD_EIM_D18__EMI_WEIM_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
1648#define MX53_PAD_EIM_D18__GPIO3_18 (_MX53_PAD_EIM_D18__GPIO3_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
1649#define MX53_PAD_EIM_D18__IPU_DI0_PIN7 (_MX53_PAD_EIM_D18__IPU_DI0_PIN7 | MUX_PAD_CTRL(NO_PAD_CTRL))
1650#define MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO (_MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO | MUX_PAD_CTRL(NO_PAD_CTRL))
1651#define MX53_PAD_EIM_D18__ECSPI1_MOSI (_MX53_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
1652#define MX53_PAD_EIM_D18__I2C3_SDA (_MX53_PAD_EIM_D18__I2C3_SDA | MUX_PAD_CTRL(NO_PAD_CTRL))
1653#define MX53_PAD_EIM_D18__IPU_DI1_D0_CS (_MX53_PAD_EIM_D18__IPU_DI1_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
1654#define MX53_PAD_EIM_D19__EMI_WEIM_D_19 (_MX53_PAD_EIM_D19__EMI_WEIM_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
1655#define MX53_PAD_EIM_D19__GPIO3_19 (_MX53_PAD_EIM_D19__GPIO3_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
1656#define MX53_PAD_EIM_D19__IPU_DI0_PIN8 (_MX53_PAD_EIM_D19__IPU_DI0_PIN8 | MUX_PAD_CTRL(NO_PAD_CTRL))
1657#define MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS (_MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS | MUX_PAD_CTRL(NO_PAD_CTRL))
1658#define MX53_PAD_EIM_D19__ECSPI1_SS1 (_MX53_PAD_EIM_D19__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1659#define MX53_PAD_EIM_D19__EPIT1_EPITO (_MX53_PAD_EIM_D19__EPIT1_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL))
1660#define MX53_PAD_EIM_D19__UART1_CTS (_MX53_PAD_EIM_D19__UART1_CTS | MUX_PAD_CTRL(NO_PAD_CTRL))
1661#define MX53_PAD_EIM_D19__USBOH3_USBH2_OC (_MX53_PAD_EIM_D19__USBOH3_USBH2_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
1662#define MX53_PAD_EIM_D20__EMI_WEIM_D_20 (_MX53_PAD_EIM_D20__EMI_WEIM_D_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
1663#define MX53_PAD_EIM_D20__GPIO3_20 (_MX53_PAD_EIM_D20__GPIO3_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
1664#define MX53_PAD_EIM_D20__IPU_DI0_PIN16 (_MX53_PAD_EIM_D20__IPU_DI0_PIN16 | MUX_PAD_CTRL(NO_PAD_CTRL))
1665#define MX53_PAD_EIM_D20__IPU_SER_DISP0_CS (_MX53_PAD_EIM_D20__IPU_SER_DISP0_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
1666#define MX53_PAD_EIM_D20__CSPI_SS0 (_MX53_PAD_EIM_D20__CSPI_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1667#define MX53_PAD_EIM_D20__EPIT2_EPITO (_MX53_PAD_EIM_D20__EPIT2_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL))
1668#define MX53_PAD_EIM_D20__UART1_RTS (_MX53_PAD_EIM_D20__UART1_RTS | MUX_PAD_CTRL(NO_PAD_CTRL))
1669#define MX53_PAD_EIM_D20__USBOH3_USBH2_PWR (_MX53_PAD_EIM_D20__USBOH3_USBH2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
1670#define MX53_PAD_EIM_D21__EMI_WEIM_D_21 (_MX53_PAD_EIM_D21__EMI_WEIM_D_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
1671#define MX53_PAD_EIM_D21__GPIO3_21 (_MX53_PAD_EIM_D21__GPIO3_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
1672#define MX53_PAD_EIM_D21__IPU_DI0_PIN17 (_MX53_PAD_EIM_D21__IPU_DI0_PIN17 | MUX_PAD_CTRL(NO_PAD_CTRL))
1673#define MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK (_MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
1674#define MX53_PAD_EIM_D21__CSPI_SCLK (_MX53_PAD_EIM_D21__CSPI_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
1675#define MX53_PAD_EIM_D21__I2C1_SCL (_MX53_PAD_EIM_D21__I2C1_SCL | MUX_PAD_CTRL(NO_PAD_CTRL))
1676#define MX53_PAD_EIM_D21__USBOH3_USBOTG_OC (_MX53_PAD_EIM_D21__USBOH3_USBOTG_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
1677#define MX53_PAD_EIM_D22__EMI_WEIM_D_22 (_MX53_PAD_EIM_D22__EMI_WEIM_D_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
1678#define MX53_PAD_EIM_D22__GPIO3_22 (_MX53_PAD_EIM_D22__GPIO3_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
1679#define MX53_PAD_EIM_D22__IPU_DI0_PIN1 (_MX53_PAD_EIM_D22__IPU_DI0_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1680#define MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN (_MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN | MUX_PAD_CTRL(NO_PAD_CTRL))
1681#define MX53_PAD_EIM_D22__CSPI_MISO (_MX53_PAD_EIM_D22__CSPI_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
1682#define MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR (_MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
1683#define MX53_PAD_EIM_D23__EMI_WEIM_D_23 (_MX53_PAD_EIM_D23__EMI_WEIM_D_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
1684#define MX53_PAD_EIM_D23__GPIO3_23 (_MX53_PAD_EIM_D23__GPIO3_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
1685#define MX53_PAD_EIM_D23__UART3_CTS (_MX53_PAD_EIM_D23__UART3_CTS | MUX_PAD_CTRL(NO_PAD_CTRL))
1686#define MX53_PAD_EIM_D23__UART1_DCD (_MX53_PAD_EIM_D23__UART1_DCD | MUX_PAD_CTRL(NO_PAD_CTRL))
1687#define MX53_PAD_EIM_D23__IPU_DI0_D0_CS (_MX53_PAD_EIM_D23__IPU_DI0_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
1688#define MX53_PAD_EIM_D23__IPU_DI1_PIN2 (_MX53_PAD_EIM_D23__IPU_DI1_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1689#define MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN (_MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
1690#define MX53_PAD_EIM_D23__IPU_DI1_PIN14 (_MX53_PAD_EIM_D23__IPU_DI1_PIN14 | MUX_PAD_CTRL(NO_PAD_CTRL))
1691#define MX53_PAD_EIM_EB3__EMI_WEIM_EB_3 (_MX53_PAD_EIM_EB3__EMI_WEIM_EB_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1692#define MX53_PAD_EIM_EB3__GPIO2_31 (_MX53_PAD_EIM_EB3__GPIO2_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
1693#define MX53_PAD_EIM_EB3__UART3_RTS (_MX53_PAD_EIM_EB3__UART3_RTS | MUX_PAD_CTRL(NO_PAD_CTRL))
1694#define MX53_PAD_EIM_EB3__UART1_RI (_MX53_PAD_EIM_EB3__UART1_RI | MUX_PAD_CTRL(NO_PAD_CTRL))
1695#define MX53_PAD_EIM_EB3__IPU_DI1_PIN3 (_MX53_PAD_EIM_EB3__IPU_DI1_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1696#define MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC (_MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
1697#define MX53_PAD_EIM_EB3__IPU_DI1_PIN16 (_MX53_PAD_EIM_EB3__IPU_DI1_PIN16 | MUX_PAD_CTRL(NO_PAD_CTRL))
1698#define MX53_PAD_EIM_D24__EMI_WEIM_D_24 (_MX53_PAD_EIM_D24__EMI_WEIM_D_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
1699#define MX53_PAD_EIM_D24__GPIO3_24 (_MX53_PAD_EIM_D24__GPIO3_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
1700#define MX53_PAD_EIM_D24__UART3_TXD_MUX (_MX53_PAD_EIM_D24__UART3_TXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL))
1701#define MX53_PAD_EIM_D24__ECSPI1_SS2 (_MX53_PAD_EIM_D24__ECSPI1_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1702#define MX53_PAD_EIM_D24__CSPI_SS2 (_MX53_PAD_EIM_D24__CSPI_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1703#define MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS (_MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
1704#define MX53_PAD_EIM_D24__ECSPI2_SS2 (_MX53_PAD_EIM_D24__ECSPI2_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1705#define MX53_PAD_EIM_D24__UART1_DTR (_MX53_PAD_EIM_D24__UART1_DTR | MUX_PAD_CTRL(NO_PAD_CTRL))
1706#define MX53_PAD_EIM_D25__EMI_WEIM_D_25 (_MX53_PAD_EIM_D25__EMI_WEIM_D_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
1707#define MX53_PAD_EIM_D25__GPIO3_25 (_MX53_PAD_EIM_D25__GPIO3_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
1708#define MX53_PAD_EIM_D25__UART3_RXD_MUX (_MX53_PAD_EIM_D25__UART3_RXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL))
1709#define MX53_PAD_EIM_D25__ECSPI1_SS3 (_MX53_PAD_EIM_D25__ECSPI1_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1710#define MX53_PAD_EIM_D25__CSPI_SS3 (_MX53_PAD_EIM_D25__CSPI_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1711#define MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC (_MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
1712#define MX53_PAD_EIM_D25__ECSPI2_SS3 (_MX53_PAD_EIM_D25__ECSPI2_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1713#define MX53_PAD_EIM_D25__UART1_DSR (_MX53_PAD_EIM_D25__UART1_DSR | MUX_PAD_CTRL(NO_PAD_CTRL))
1714#define MX53_PAD_EIM_D26__EMI_WEIM_D_26 (_MX53_PAD_EIM_D26__EMI_WEIM_D_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
1715#define MX53_PAD_EIM_D26__GPIO3_26 (_MX53_PAD_EIM_D26__GPIO3_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
1716#define MX53_PAD_EIM_D26__UART2_TXD_MUX (_MX53_PAD_EIM_D26__UART2_TXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL))
1717#define MX53_PAD_EIM_D26__FIRI_RXD (_MX53_PAD_EIM_D26__FIRI_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
1718#define MX53_PAD_EIM_D26__IPU_CSI0_D_1 (_MX53_PAD_EIM_D26__IPU_CSI0_D_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1719#define MX53_PAD_EIM_D26__IPU_DI1_PIN11 (_MX53_PAD_EIM_D26__IPU_DI1_PIN11 | MUX_PAD_CTRL(NO_PAD_CTRL))
1720#define MX53_PAD_EIM_D26__IPU_SISG_2 (_MX53_PAD_EIM_D26__IPU_SISG_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1721#define MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 (_MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
1722#define MX53_PAD_EIM_D27__EMI_WEIM_D_27 (_MX53_PAD_EIM_D27__EMI_WEIM_D_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
1723#define MX53_PAD_EIM_D27__GPIO3_27 (_MX53_PAD_EIM_D27__GPIO3_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
1724#define MX53_PAD_EIM_D27__UART2_RXD_MUX (_MX53_PAD_EIM_D27__UART2_RXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL))
1725#define MX53_PAD_EIM_D27__FIRI_TXD (_MX53_PAD_EIM_D27__FIRI_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
1726#define MX53_PAD_EIM_D27__IPU_CSI0_D_0 (_MX53_PAD_EIM_D27__IPU_CSI0_D_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1727#define MX53_PAD_EIM_D27__IPU_DI1_PIN13 (_MX53_PAD_EIM_D27__IPU_DI1_PIN13 | MUX_PAD_CTRL(NO_PAD_CTRL))
1728#define MX53_PAD_EIM_D27__IPU_SISG_3 (_MX53_PAD_EIM_D27__IPU_SISG_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1729#define MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 (_MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
1730#define MX53_PAD_EIM_D28__EMI_WEIM_D_28 (_MX53_PAD_EIM_D28__EMI_WEIM_D_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
1731#define MX53_PAD_EIM_D28__GPIO3_28 (_MX53_PAD_EIM_D28__GPIO3_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
1732#define MX53_PAD_EIM_D28__UART2_CTS (_MX53_PAD_EIM_D28__UART2_CTS | MUX_PAD_CTRL(NO_PAD_CTRL))
1733#define MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO (_MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO | MUX_PAD_CTRL(NO_PAD_CTRL))
1734#define MX53_PAD_EIM_D28__CSPI_MOSI (_MX53_PAD_EIM_D28__CSPI_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
1735#define MX53_PAD_EIM_D28__I2C1_SDA (_MX53_PAD_EIM_D28__I2C1_SDA | MUX_PAD_CTRL(NO_PAD_CTRL))
1736#define MX53_PAD_EIM_D28__IPU_EXT_TRIG (_MX53_PAD_EIM_D28__IPU_EXT_TRIG | MUX_PAD_CTRL(NO_PAD_CTRL))
1737#define MX53_PAD_EIM_D28__IPU_DI0_PIN13 (_MX53_PAD_EIM_D28__IPU_DI0_PIN13 | MUX_PAD_CTRL(NO_PAD_CTRL))
1738#define MX53_PAD_EIM_D29__EMI_WEIM_D_29 (_MX53_PAD_EIM_D29__EMI_WEIM_D_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
1739#define MX53_PAD_EIM_D29__GPIO3_29 (_MX53_PAD_EIM_D29__GPIO3_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
1740#define MX53_PAD_EIM_D29__UART2_RTS (_MX53_PAD_EIM_D29__UART2_RTS | MUX_PAD_CTRL(NO_PAD_CTRL))
1741#define MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS (_MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS | MUX_PAD_CTRL(NO_PAD_CTRL))
1742#define MX53_PAD_EIM_D29__CSPI_SS0 (_MX53_PAD_EIM_D29__CSPI_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1743#define MX53_PAD_EIM_D29__IPU_DI1_PIN15 (_MX53_PAD_EIM_D29__IPU_DI1_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL))
1744#define MX53_PAD_EIM_D29__IPU_CSI1_VSYNC (_MX53_PAD_EIM_D29__IPU_CSI1_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
1745#define MX53_PAD_EIM_D29__IPU_DI0_PIN14 (_MX53_PAD_EIM_D29__IPU_DI0_PIN14 | MUX_PAD_CTRL(NO_PAD_CTRL))
1746#define MX53_PAD_EIM_D30__EMI_WEIM_D_30 (_MX53_PAD_EIM_D30__EMI_WEIM_D_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
1747#define MX53_PAD_EIM_D30__GPIO3_30 (_MX53_PAD_EIM_D30__GPIO3_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
1748#define MX53_PAD_EIM_D30__UART3_CTS (_MX53_PAD_EIM_D30__UART3_CTS | MUX_PAD_CTRL(NO_PAD_CTRL))
1749#define MX53_PAD_EIM_D30__IPU_CSI0_D_3 (_MX53_PAD_EIM_D30__IPU_CSI0_D_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1750#define MX53_PAD_EIM_D30__IPU_DI0_PIN11 (_MX53_PAD_EIM_D30__IPU_DI0_PIN11 | MUX_PAD_CTRL(NO_PAD_CTRL))
1751#define MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 (_MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
1752#define MX53_PAD_EIM_D30__USBOH3_USBH1_OC (_MX53_PAD_EIM_D30__USBOH3_USBH1_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
1753#define MX53_PAD_EIM_D30__USBOH3_USBH2_OC (_MX53_PAD_EIM_D30__USBOH3_USBH2_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
1754#define MX53_PAD_EIM_D31__EMI_WEIM_D_31 (_MX53_PAD_EIM_D31__EMI_WEIM_D_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
1755#define MX53_PAD_EIM_D31__GPIO3_31 (_MX53_PAD_EIM_D31__GPIO3_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
1756#define MX53_PAD_EIM_D31__UART3_RTS (_MX53_PAD_EIM_D31__UART3_RTS | MUX_PAD_CTRL(NO_PAD_CTRL))
1757#define MX53_PAD_EIM_D31__IPU_CSI0_D_2 (_MX53_PAD_EIM_D31__IPU_CSI0_D_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1758#define MX53_PAD_EIM_D31__IPU_DI0_PIN12 (_MX53_PAD_EIM_D31__IPU_DI0_PIN12 | MUX_PAD_CTRL(NO_PAD_CTRL))
1759#define MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 (_MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
1760#define MX53_PAD_EIM_D31__USBOH3_USBH1_PWR (_MX53_PAD_EIM_D31__USBOH3_USBH1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
1761#define MX53_PAD_EIM_D31__USBOH3_USBH2_PWR (_MX53_PAD_EIM_D31__USBOH3_USBH2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
1762#define MX53_PAD_EIM_A24__EMI_WEIM_A_24 (_MX53_PAD_EIM_A24__EMI_WEIM_A_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
1763#define MX53_PAD_EIM_A24__GPIO5_4 (_MX53_PAD_EIM_A24__GPIO5_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
1764#define MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 (_MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
1765#define MX53_PAD_EIM_A24__IPU_CSI1_D_19 (_MX53_PAD_EIM_A24__IPU_CSI1_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
1766#define MX53_PAD_EIM_A24__IPU_SISG_2 (_MX53_PAD_EIM_A24__IPU_SISG_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1767#define MX53_PAD_EIM_A24__USBPHY2_BVALID (_MX53_PAD_EIM_A24__USBPHY2_BVALID | MUX_PAD_CTRL(NO_PAD_CTRL))
1768#define MX53_PAD_EIM_A23__EMI_WEIM_A_23 (_MX53_PAD_EIM_A23__EMI_WEIM_A_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
1769#define MX53_PAD_EIM_A23__GPIO6_6 (_MX53_PAD_EIM_A23__GPIO6_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
1770#define MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 (_MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
1771#define MX53_PAD_EIM_A23__IPU_CSI1_D_18 (_MX53_PAD_EIM_A23__IPU_CSI1_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
1772#define MX53_PAD_EIM_A23__IPU_SISG_3 (_MX53_PAD_EIM_A23__IPU_SISG_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1773#define MX53_PAD_EIM_A23__USBPHY2_ENDSESSION (_MX53_PAD_EIM_A23__USBPHY2_ENDSESSION | MUX_PAD_CTRL(NO_PAD_CTRL))
1774#define MX53_PAD_EIM_A22__EMI_WEIM_A_22 (_MX53_PAD_EIM_A22__EMI_WEIM_A_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
1775#define MX53_PAD_EIM_A22__GPIO2_16 (_MX53_PAD_EIM_A22__GPIO2_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
1776#define MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 (_MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
1777#define MX53_PAD_EIM_A22__IPU_CSI1_D_17 (_MX53_PAD_EIM_A22__IPU_CSI1_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
1778#define MX53_PAD_EIM_A22__SRC_BT_CFG1_7 (_MX53_PAD_EIM_A22__SRC_BT_CFG1_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
1779#define MX53_PAD_EIM_A21__EMI_WEIM_A_21 (_MX53_PAD_EIM_A21__EMI_WEIM_A_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
1780#define MX53_PAD_EIM_A21__GPIO2_17 (_MX53_PAD_EIM_A21__GPIO2_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
1781#define MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 (_MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
1782#define MX53_PAD_EIM_A21__IPU_CSI1_D_16 (_MX53_PAD_EIM_A21__IPU_CSI1_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
1783#define MX53_PAD_EIM_A21__SRC_BT_CFG1_6 (_MX53_PAD_EIM_A21__SRC_BT_CFG1_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
1784#define MX53_PAD_EIM_A20__EMI_WEIM_A_20 (_MX53_PAD_EIM_A20__EMI_WEIM_A_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
1785#define MX53_PAD_EIM_A20__GPIO2_18 (_MX53_PAD_EIM_A20__GPIO2_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
1786#define MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 (_MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
1787#define MX53_PAD_EIM_A20__IPU_CSI1_D_15 (_MX53_PAD_EIM_A20__IPU_CSI1_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
1788#define MX53_PAD_EIM_A20__SRC_BT_CFG1_5 (_MX53_PAD_EIM_A20__SRC_BT_CFG1_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
1789#define MX53_PAD_EIM_A19__EMI_WEIM_A_19 (_MX53_PAD_EIM_A19__EMI_WEIM_A_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
1790#define MX53_PAD_EIM_A19__GPIO2_19 (_MX53_PAD_EIM_A19__GPIO2_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
1791#define MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 (_MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
1792#define MX53_PAD_EIM_A19__IPU_CSI1_D_14 (_MX53_PAD_EIM_A19__IPU_CSI1_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
1793#define MX53_PAD_EIM_A19__SRC_BT_CFG1_4 (_MX53_PAD_EIM_A19__SRC_BT_CFG1_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
1794#define MX53_PAD_EIM_A18__EMI_WEIM_A_18 (_MX53_PAD_EIM_A18__EMI_WEIM_A_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
1795#define MX53_PAD_EIM_A18__GPIO2_20 (_MX53_PAD_EIM_A18__GPIO2_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
1796#define MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 (_MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
1797#define MX53_PAD_EIM_A18__IPU_CSI1_D_13 (_MX53_PAD_EIM_A18__IPU_CSI1_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
1798#define MX53_PAD_EIM_A18__SRC_BT_CFG1_3 (_MX53_PAD_EIM_A18__SRC_BT_CFG1_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1799#define MX53_PAD_EIM_A17__EMI_WEIM_A_17 (_MX53_PAD_EIM_A17__EMI_WEIM_A_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
1800#define MX53_PAD_EIM_A17__GPIO2_21 (_MX53_PAD_EIM_A17__GPIO2_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
1801#define MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 (_MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
1802#define MX53_PAD_EIM_A17__IPU_CSI1_D_12 (_MX53_PAD_EIM_A17__IPU_CSI1_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
1803#define MX53_PAD_EIM_A17__SRC_BT_CFG1_2 (_MX53_PAD_EIM_A17__SRC_BT_CFG1_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1804#define MX53_PAD_EIM_A16__EMI_WEIM_A_16 (_MX53_PAD_EIM_A16__EMI_WEIM_A_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
1805#define MX53_PAD_EIM_A16__GPIO2_22 (_MX53_PAD_EIM_A16__GPIO2_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
1806#define MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK (_MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
1807#define MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK (_MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
1808#define MX53_PAD_EIM_A16__SRC_BT_CFG1_1 (_MX53_PAD_EIM_A16__SRC_BT_CFG1_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1809#define MX53_PAD_EIM_CS0__EMI_WEIM_CS_0 (_MX53_PAD_EIM_CS0__EMI_WEIM_CS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1810#define MX53_PAD_EIM_CS0__GPIO2_23 (_MX53_PAD_EIM_CS0__GPIO2_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
1811#define MX53_PAD_EIM_CS0__ECSPI2_SCLK (_MX53_PAD_EIM_CS0__ECSPI2_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
1812#define MX53_PAD_EIM_CS0__IPU_DI1_PIN5 (_MX53_PAD_EIM_CS0__IPU_DI1_PIN5 | MUX_PAD_CTRL(NO_PAD_CTRL))
1813#define MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 (_MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1814#define MX53_PAD_EIM_CS1__GPIO2_24 (_MX53_PAD_EIM_CS1__GPIO2_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
1815#define MX53_PAD_EIM_CS1__ECSPI2_MOSI (_MX53_PAD_EIM_CS1__ECSPI2_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
1816#define MX53_PAD_EIM_CS1__IPU_DI1_PIN6 (_MX53_PAD_EIM_CS1__IPU_DI1_PIN6 | MUX_PAD_CTRL(NO_PAD_CTRL))
1817#define MX53_PAD_EIM_OE__EMI_WEIM_OE (_MX53_PAD_EIM_OE__EMI_WEIM_OE | MUX_PAD_CTRL(NO_PAD_CTRL))
1818#define MX53_PAD_EIM_OE__GPIO2_25 (_MX53_PAD_EIM_OE__GPIO2_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
1819#define MX53_PAD_EIM_OE__ECSPI2_MISO (_MX53_PAD_EIM_OE__ECSPI2_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
1820#define MX53_PAD_EIM_OE__IPU_DI1_PIN7 (_MX53_PAD_EIM_OE__IPU_DI1_PIN7 | MUX_PAD_CTRL(NO_PAD_CTRL))
1821#define MX53_PAD_EIM_OE__USBPHY2_IDDIG (_MX53_PAD_EIM_OE__USBPHY2_IDDIG | MUX_PAD_CTRL(NO_PAD_CTRL))
1822#define MX53_PAD_EIM_RW__EMI_WEIM_RW (_MX53_PAD_EIM_RW__EMI_WEIM_RW | MUX_PAD_CTRL(NO_PAD_CTRL))
1823#define MX53_PAD_EIM_RW__GPIO2_26 (_MX53_PAD_EIM_RW__GPIO2_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
1824#define MX53_PAD_EIM_RW__ECSPI2_SS0 (_MX53_PAD_EIM_RW__ECSPI2_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1825#define MX53_PAD_EIM_RW__IPU_DI1_PIN8 (_MX53_PAD_EIM_RW__IPU_DI1_PIN8 | MUX_PAD_CTRL(NO_PAD_CTRL))
1826#define MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT (_MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT | MUX_PAD_CTRL(NO_PAD_CTRL))
1827#define MX53_PAD_EIM_LBA__EMI_WEIM_LBA (_MX53_PAD_EIM_LBA__EMI_WEIM_LBA | MUX_PAD_CTRL(NO_PAD_CTRL))
1828#define MX53_PAD_EIM_LBA__GPIO2_27 (_MX53_PAD_EIM_LBA__GPIO2_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
1829#define MX53_PAD_EIM_LBA__ECSPI2_SS1 (_MX53_PAD_EIM_LBA__ECSPI2_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1830#define MX53_PAD_EIM_LBA__IPU_DI1_PIN17 (_MX53_PAD_EIM_LBA__IPU_DI1_PIN17 | MUX_PAD_CTRL(NO_PAD_CTRL))
1831#define MX53_PAD_EIM_LBA__SRC_BT_CFG1_0 (_MX53_PAD_EIM_LBA__SRC_BT_CFG1_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1832#define MX53_PAD_EIM_EB0__EMI_WEIM_EB_0 (_MX53_PAD_EIM_EB0__EMI_WEIM_EB_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1833#define MX53_PAD_EIM_EB0__GPIO2_28 (_MX53_PAD_EIM_EB0__GPIO2_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
1834#define MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 (_MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
1835#define MX53_PAD_EIM_EB0__IPU_CSI1_D_11 (_MX53_PAD_EIM_EB0__IPU_CSI1_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
1836#define MX53_PAD_EIM_EB0__GPC_PMIC_RDY (_MX53_PAD_EIM_EB0__GPC_PMIC_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
1837#define MX53_PAD_EIM_EB0__SRC_BT_CFG2_7 (_MX53_PAD_EIM_EB0__SRC_BT_CFG2_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
1838#define MX53_PAD_EIM_EB1__EMI_WEIM_EB_1 (_MX53_PAD_EIM_EB1__EMI_WEIM_EB_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1839#define MX53_PAD_EIM_EB1__GPIO2_29 (_MX53_PAD_EIM_EB1__GPIO2_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
1840#define MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 (_MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
1841#define MX53_PAD_EIM_EB1__IPU_CSI1_D_10 (_MX53_PAD_EIM_EB1__IPU_CSI1_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
1842#define MX53_PAD_EIM_EB1__SRC_BT_CFG2_6 (_MX53_PAD_EIM_EB1__SRC_BT_CFG2_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
1843#define MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 (_MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1844#define MX53_PAD_EIM_DA0__GPIO3_0 (_MX53_PAD_EIM_DA0__GPIO3_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1845#define MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 (_MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
1846#define MX53_PAD_EIM_DA0__IPU_CSI1_D_9 (_MX53_PAD_EIM_DA0__IPU_CSI1_D_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
1847#define MX53_PAD_EIM_DA0__SRC_BT_CFG2_5 (_MX53_PAD_EIM_DA0__SRC_BT_CFG2_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
1848#define MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 (_MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1849#define MX53_PAD_EIM_DA1__GPIO3_1 (_MX53_PAD_EIM_DA1__GPIO3_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1850#define MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 (_MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
1851#define MX53_PAD_EIM_DA1__IPU_CSI1_D_8 (_MX53_PAD_EIM_DA1__IPU_CSI1_D_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
1852#define MX53_PAD_EIM_DA1__SRC_BT_CFG2_4 (_MX53_PAD_EIM_DA1__SRC_BT_CFG2_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
1853#define MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 (_MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1854#define MX53_PAD_EIM_DA2__GPIO3_2 (_MX53_PAD_EIM_DA2__GPIO3_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1855#define MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 (_MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
1856#define MX53_PAD_EIM_DA2__IPU_CSI1_D_7 (_MX53_PAD_EIM_DA2__IPU_CSI1_D_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
1857#define MX53_PAD_EIM_DA2__SRC_BT_CFG2_3 (_MX53_PAD_EIM_DA2__SRC_BT_CFG2_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1858#define MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 (_MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1859#define MX53_PAD_EIM_DA3__GPIO3_3 (_MX53_PAD_EIM_DA3__GPIO3_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1860#define MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 (_MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
1861#define MX53_PAD_EIM_DA3__IPU_CSI1_D_6 (_MX53_PAD_EIM_DA3__IPU_CSI1_D_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
1862#define MX53_PAD_EIM_DA3__SRC_BT_CFG2_2 (_MX53_PAD_EIM_DA3__SRC_BT_CFG2_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1863#define MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 (_MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
1864#define MX53_PAD_EIM_DA4__GPIO3_4 (_MX53_PAD_EIM_DA4__GPIO3_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
1865#define MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 (_MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
1866#define MX53_PAD_EIM_DA4__IPU_CSI1_D_5 (_MX53_PAD_EIM_DA4__IPU_CSI1_D_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
1867#define MX53_PAD_EIM_DA4__SRC_BT_CFG3_7 (_MX53_PAD_EIM_DA4__SRC_BT_CFG3_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
1868#define MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 (_MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
1869#define MX53_PAD_EIM_DA5__GPIO3_5 (_MX53_PAD_EIM_DA5__GPIO3_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
1870#define MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 (_MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
1871#define MX53_PAD_EIM_DA5__IPU_CSI1_D_4 (_MX53_PAD_EIM_DA5__IPU_CSI1_D_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
1872#define MX53_PAD_EIM_DA5__SRC_BT_CFG3_6 (_MX53_PAD_EIM_DA5__SRC_BT_CFG3_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
1873#define MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 (_MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
1874#define MX53_PAD_EIM_DA6__GPIO3_6 (_MX53_PAD_EIM_DA6__GPIO3_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
1875#define MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 (_MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1876#define MX53_PAD_EIM_DA6__IPU_CSI1_D_3 (_MX53_PAD_EIM_DA6__IPU_CSI1_D_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1877#define MX53_PAD_EIM_DA6__SRC_BT_CFG3_5 (_MX53_PAD_EIM_DA6__SRC_BT_CFG3_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
1878#define MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 (_MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
1879#define MX53_PAD_EIM_DA7__GPIO3_7 (_MX53_PAD_EIM_DA7__GPIO3_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
1880#define MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 (_MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1881#define MX53_PAD_EIM_DA7__IPU_CSI1_D_2 (_MX53_PAD_EIM_DA7__IPU_CSI1_D_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1882#define MX53_PAD_EIM_DA7__SRC_BT_CFG3_4 (_MX53_PAD_EIM_DA7__SRC_BT_CFG3_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
1883#define MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8 (_MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
1884#define MX53_PAD_EIM_DA8__GPIO3_8 (_MX53_PAD_EIM_DA8__GPIO3_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
1885#define MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 (_MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1886#define MX53_PAD_EIM_DA8__IPU_CSI1_D_1 (_MX53_PAD_EIM_DA8__IPU_CSI1_D_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1887#define MX53_PAD_EIM_DA8__SRC_BT_CFG3_3 (_MX53_PAD_EIM_DA8__SRC_BT_CFG3_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1888#define MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9 (_MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
1889#define MX53_PAD_EIM_DA9__GPIO3_9 (_MX53_PAD_EIM_DA9__GPIO3_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
1890#define MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 (_MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1891#define MX53_PAD_EIM_DA9__IPU_CSI1_D_0 (_MX53_PAD_EIM_DA9__IPU_CSI1_D_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1892#define MX53_PAD_EIM_DA9__SRC_BT_CFG3_2 (_MX53_PAD_EIM_DA9__SRC_BT_CFG3_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1893#define MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10 (_MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
1894#define MX53_PAD_EIM_DA10__GPIO3_10 (_MX53_PAD_EIM_DA10__GPIO3_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
1895#define MX53_PAD_EIM_DA10__IPU_DI1_PIN15 (_MX53_PAD_EIM_DA10__IPU_DI1_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL))
1896#define MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN (_MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
1897#define MX53_PAD_EIM_DA10__SRC_BT_CFG3_1 (_MX53_PAD_EIM_DA10__SRC_BT_CFG3_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1898#define MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11 (_MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
1899#define MX53_PAD_EIM_DA11__GPIO3_11 (_MX53_PAD_EIM_DA11__GPIO3_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
1900#define MX53_PAD_EIM_DA11__IPU_DI1_PIN2 (_MX53_PAD_EIM_DA11__IPU_DI1_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1901#define MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC (_MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
1902#define MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12 (_MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
1903#define MX53_PAD_EIM_DA12__GPIO3_12 (_MX53_PAD_EIM_DA12__GPIO3_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
1904#define MX53_PAD_EIM_DA12__IPU_DI1_PIN3 (_MX53_PAD_EIM_DA12__IPU_DI1_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1905#define MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC (_MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
1906#define MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13 (_MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
1907#define MX53_PAD_EIM_DA13__GPIO3_13 (_MX53_PAD_EIM_DA13__GPIO3_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
1908#define MX53_PAD_EIM_DA13__IPU_DI1_D0_CS (_MX53_PAD_EIM_DA13__IPU_DI1_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
1909#define MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK (_MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
1910#define MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14 (_MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
1911#define MX53_PAD_EIM_DA14__GPIO3_14 (_MX53_PAD_EIM_DA14__GPIO3_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
1912#define MX53_PAD_EIM_DA14__IPU_DI1_D1_CS (_MX53_PAD_EIM_DA14__IPU_DI1_D1_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
1913#define MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK (_MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
1914#define MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15 (_MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
1915#define MX53_PAD_EIM_DA15__GPIO3_15 (_MX53_PAD_EIM_DA15__GPIO3_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
1916#define MX53_PAD_EIM_DA15__IPU_DI1_PIN1 (_MX53_PAD_EIM_DA15__IPU_DI1_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1917#define MX53_PAD_EIM_DA15__IPU_DI1_PIN4 (_MX53_PAD_EIM_DA15__IPU_DI1_PIN4 | MUX_PAD_CTRL(NO_PAD_CTRL))
1918#define MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B (_MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL))
1919#define MX53_PAD_NANDF_WE_B__GPIO6_12 (_MX53_PAD_NANDF_WE_B__GPIO6_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
1920#define MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B (_MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL))
1921#define MX53_PAD_NANDF_RE_B__GPIO6_13 (_MX53_PAD_NANDF_RE_B__GPIO6_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
1922#define MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT (_MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL))
1923#define MX53_PAD_EIM_WAIT__GPIO5_0 (_MX53_PAD_EIM_WAIT__GPIO5_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1924#define MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B (_MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B | MUX_PAD_CTRL(NO_PAD_CTRL))
1925#define MX53_PAD_LVDS1_TX3_P__GPIO6_22 (_MX53_PAD_LVDS1_TX3_P__GPIO6_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
1926#define MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 (_MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1927#define MX53_PAD_LVDS1_TX2_P__GPIO6_24 (_MX53_PAD_LVDS1_TX2_P__GPIO6_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
1928#define MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 (_MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1929#define MX53_PAD_LVDS1_CLK_P__GPIO6_26 (_MX53_PAD_LVDS1_CLK_P__GPIO6_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
1930#define MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK (_MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
1931#define MX53_PAD_LVDS1_TX1_P__GPIO6_28 (_MX53_PAD_LVDS1_TX1_P__GPIO6_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
1932#define MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 (_MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1933#define MX53_PAD_LVDS1_TX0_P__GPIO6_30 (_MX53_PAD_LVDS1_TX0_P__GPIO6_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
1934#define MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 (_MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1935#define MX53_PAD_LVDS0_TX3_P__GPIO7_22 (_MX53_PAD_LVDS0_TX3_P__GPIO7_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
1936#define MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 (_MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1937#define MX53_PAD_LVDS0_CLK_P__GPIO7_24 (_MX53_PAD_LVDS0_CLK_P__GPIO7_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
1938#define MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK (_MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
1939#define MX53_PAD_LVDS0_TX2_P__GPIO7_26 (_MX53_PAD_LVDS0_TX2_P__GPIO7_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
1940#define MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 (_MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1941#define MX53_PAD_LVDS0_TX1_P__GPIO7_28 (_MX53_PAD_LVDS0_TX1_P__GPIO7_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
1942#define MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 (_MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1943#define MX53_PAD_LVDS0_TX0_P__GPIO7_30 (_MX53_PAD_LVDS0_TX0_P__GPIO7_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
1944#define MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 (_MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1945#define MX53_PAD_GPIO_10__GPIO4_0 (_MX53_PAD_GPIO_10__GPIO4_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1946#define MX53_PAD_GPIO_10__OSC32k_32K_OUT (_MX53_PAD_GPIO_10__OSC32k_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
1947#define MX53_PAD_GPIO_11__GPIO4_1 (_MX53_PAD_GPIO_11__GPIO4_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1948#define MX53_PAD_GPIO_12__GPIO4_2 (_MX53_PAD_GPIO_12__GPIO4_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1949#define MX53_PAD_GPIO_13__GPIO4_3 (_MX53_PAD_GPIO_13__GPIO4_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1950#define MX53_PAD_GPIO_14__GPIO4_4 (_MX53_PAD_GPIO_14__GPIO4_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
1951#define MX53_PAD_NANDF_CLE__EMI_NANDF_CLE (_MX53_PAD_NANDF_CLE__EMI_NANDF_CLE | MUX_PAD_CTRL(NO_PAD_CTRL))
1952#define MX53_PAD_NANDF_CLE__GPIO6_7 (_MX53_PAD_NANDF_CLE__GPIO6_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
1953#define MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0 (_MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1954#define MX53_PAD_NANDF_ALE__EMI_NANDF_ALE (_MX53_PAD_NANDF_ALE__EMI_NANDF_ALE | MUX_PAD_CTRL(NO_PAD_CTRL))
1955#define MX53_PAD_NANDF_ALE__GPIO6_8 (_MX53_PAD_NANDF_ALE__GPIO6_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
1956#define MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1 (_MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1957#define MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B (_MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL))
1958#define MX53_PAD_NANDF_WP_B__GPIO6_9 (_MX53_PAD_NANDF_WP_B__GPIO6_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
1959#define MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2 (_MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1960#define MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 (_MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1961#define MX53_PAD_NANDF_RB0__GPIO6_10 (_MX53_PAD_NANDF_RB0__GPIO6_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
1962#define MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3 (_MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1963#define MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 (_MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1964#define MX53_PAD_NANDF_CS0__GPIO6_11 (_MX53_PAD_NANDF_CS0__GPIO6_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
1965#define MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4 (_MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
1966#define MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1 (_MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1967#define MX53_PAD_NANDF_CS1__GPIO6_14 (_MX53_PAD_NANDF_CS1__GPIO6_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
1968#define MX53_PAD_NANDF_CS1__MLB_MLBCLK (_MX53_PAD_NANDF_CS1__MLB_MLBCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
1969#define MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5 (_MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
1970#define MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2 (_MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1971#define MX53_PAD_NANDF_CS2__GPIO6_15 (_MX53_PAD_NANDF_CS2__GPIO6_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
1972#define MX53_PAD_NANDF_CS2__IPU_SISG_0 (_MX53_PAD_NANDF_CS2__IPU_SISG_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1973#define MX53_PAD_NANDF_CS2__ESAI1_TX0 (_MX53_PAD_NANDF_CS2__ESAI1_TX0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1974#define MX53_PAD_NANDF_CS2__EMI_WEIM_CRE (_MX53_PAD_NANDF_CS2__EMI_WEIM_CRE | MUX_PAD_CTRL(NO_PAD_CTRL))
1975#define MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK (_MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
1976#define MX53_PAD_NANDF_CS2__MLB_MLBSIG (_MX53_PAD_NANDF_CS2__MLB_MLBSIG | MUX_PAD_CTRL(NO_PAD_CTRL))
1977#define MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6 (_MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
1978#define MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3 (_MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1979#define MX53_PAD_NANDF_CS3__GPIO6_16 (_MX53_PAD_NANDF_CS3__GPIO6_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
1980#define MX53_PAD_NANDF_CS3__IPU_SISG_1 (_MX53_PAD_NANDF_CS3__IPU_SISG_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1981#define MX53_PAD_NANDF_CS3__ESAI1_TX1 (_MX53_PAD_NANDF_CS3__ESAI1_TX1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1982#define MX53_PAD_NANDF_CS3__EMI_WEIM_A_26 (_MX53_PAD_NANDF_CS3__EMI_WEIM_A_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
1983#define MX53_PAD_NANDF_CS3__MLB_MLBDAT (_MX53_PAD_NANDF_CS3__MLB_MLBDAT | MUX_PAD_CTRL(NO_PAD_CTRL))
1984#define MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7 (_MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
1985#define MX53_PAD_FEC_MDIO__FEC_MDIO (_MX53_PAD_FEC_MDIO__FEC_MDIO | MUX_PAD_CTRL(NO_PAD_CTRL))
1986#define MX53_PAD_FEC_MDIO__GPIO1_22 (_MX53_PAD_FEC_MDIO__GPIO1_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
1987#define MX53_PAD_FEC_MDIO__ESAI1_SCKR (_MX53_PAD_FEC_MDIO__ESAI1_SCKR | MUX_PAD_CTRL(NO_PAD_CTRL))
1988#define MX53_PAD_FEC_MDIO__FEC_COL (_MX53_PAD_FEC_MDIO__FEC_COL | MUX_PAD_CTRL(NO_PAD_CTRL))
1989#define MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2 (_MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1990#define MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3 (_MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1991#define MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49 (_MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49 | MUX_PAD_CTRL(NO_PAD_CTRL))
1992#define MX53_PAD_FEC_REF_CLK__FEC_TX_CLK (_MX53_PAD_FEC_REF_CLK__FEC_TX_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
1993#define MX53_PAD_FEC_REF_CLK__GPIO1_23 (_MX53_PAD_FEC_REF_CLK__GPIO1_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
1994#define MX53_PAD_FEC_REF_CLK__ESAI1_FSR (_MX53_PAD_FEC_REF_CLK__ESAI1_FSR | MUX_PAD_CTRL(NO_PAD_CTRL))
1995#define MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 (_MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
1996#define MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50 (_MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50 | MUX_PAD_CTRL(NO_PAD_CTRL))
1997#define MX53_PAD_FEC_RX_ER__FEC_RX_ER (_MX53_PAD_FEC_RX_ER__FEC_RX_ER | MUX_PAD_CTRL(NO_PAD_CTRL))
1998#define MX53_PAD_FEC_RX_ER__GPIO1_24 (_MX53_PAD_FEC_RX_ER__GPIO1_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
1999#define MX53_PAD_FEC_RX_ER__ESAI1_HCKR (_MX53_PAD_FEC_RX_ER__ESAI1_HCKR | MUX_PAD_CTRL(NO_PAD_CTRL))
2000#define MX53_PAD_FEC_RX_ER__FEC_RX_CLK (_MX53_PAD_FEC_RX_ER__FEC_RX_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
2001#define MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3 (_MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
2002#define MX53_PAD_FEC_CRS_DV__FEC_RX_DV (_MX53_PAD_FEC_CRS_DV__FEC_RX_DV | MUX_PAD_CTRL(NO_PAD_CTRL))
2003#define MX53_PAD_FEC_CRS_DV__GPIO1_25 (_MX53_PAD_FEC_CRS_DV__GPIO1_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
2004#define MX53_PAD_FEC_CRS_DV__ESAI1_SCKT (_MX53_PAD_FEC_CRS_DV__ESAI1_SCKT | MUX_PAD_CTRL(NO_PAD_CTRL))
2005#define MX53_PAD_FEC_RXD1__FEC_RDATA_1 (_MX53_PAD_FEC_RXD1__FEC_RDATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
2006#define MX53_PAD_FEC_RXD1__GPIO1_26 (_MX53_PAD_FEC_RXD1__GPIO1_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
2007#define MX53_PAD_FEC_RXD1__ESAI1_FST (_MX53_PAD_FEC_RXD1__ESAI1_FST | MUX_PAD_CTRL(NO_PAD_CTRL))
2008#define MX53_PAD_FEC_RXD1__MLB_MLBSIG (_MX53_PAD_FEC_RXD1__MLB_MLBSIG | MUX_PAD_CTRL(NO_PAD_CTRL))
2009#define MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1 (_MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
2010#define MX53_PAD_FEC_RXD0__FEC_RDATA_0 (_MX53_PAD_FEC_RXD0__FEC_RDATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
2011#define MX53_PAD_FEC_RXD0__GPIO1_27 (_MX53_PAD_FEC_RXD0__GPIO1_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
2012#define MX53_PAD_FEC_RXD0__ESAI1_HCKT (_MX53_PAD_FEC_RXD0__ESAI1_HCKT | MUX_PAD_CTRL(NO_PAD_CTRL))
2013#define MX53_PAD_FEC_RXD0__OSC32k_32K_OUT (_MX53_PAD_FEC_RXD0__OSC32k_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
2014#define MX53_PAD_FEC_TX_EN__FEC_TX_EN (_MX53_PAD_FEC_TX_EN__FEC_TX_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
2015#define MX53_PAD_FEC_TX_EN__GPIO1_28 (_MX53_PAD_FEC_TX_EN__GPIO1_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
2016#define MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2 (_MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2 | MUX_PAD_CTRL(NO_PAD_CTRL))
2017#define MX53_PAD_FEC_TXD1__FEC_TDATA_1 (_MX53_PAD_FEC_TXD1__FEC_TDATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
2018#define MX53_PAD_FEC_TXD1__GPIO1_29 (_MX53_PAD_FEC_TXD1__GPIO1_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
2019#define MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3 (_MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3 | MUX_PAD_CTRL(NO_PAD_CTRL))
2020#define MX53_PAD_FEC_TXD1__MLB_MLBCLK (_MX53_PAD_FEC_TXD1__MLB_MLBCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
2021#define MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK (_MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
2022#define MX53_PAD_FEC_TXD0__FEC_TDATA_0 (_MX53_PAD_FEC_TXD0__FEC_TDATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
2023#define MX53_PAD_FEC_TXD0__GPIO1_30 (_MX53_PAD_FEC_TXD0__GPIO1_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
2024#define MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1 (_MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1 | MUX_PAD_CTRL(NO_PAD_CTRL))
2025#define MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0 (_MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
2026#define MX53_PAD_FEC_MDC__FEC_MDC (_MX53_PAD_FEC_MDC__FEC_MDC | MUX_PAD_CTRL(NO_PAD_CTRL))
2027#define MX53_PAD_FEC_MDC__GPIO1_31 (_MX53_PAD_FEC_MDC__GPIO1_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
2028#define MX53_PAD_FEC_MDC__ESAI1_TX5_RX0 (_MX53_PAD_FEC_MDC__ESAI1_TX5_RX0 | MUX_PAD_CTRL(NO_PAD_CTRL))
2029#define MX53_PAD_FEC_MDC__MLB_MLBDAT (_MX53_PAD_FEC_MDC__MLB_MLBDAT | MUX_PAD_CTRL(NO_PAD_CTRL))
2030#define MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG (_MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG | MUX_PAD_CTRL(NO_PAD_CTRL))
2031#define MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1 (_MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
2032#define MX53_PAD_PATA_DIOW__PATA_DIOW (_MX53_PAD_PATA_DIOW__PATA_DIOW | MUX_PAD_CTRL(NO_PAD_CTRL))
2033#define MX53_PAD_PATA_DIOW__GPIO6_17 (_MX53_PAD_PATA_DIOW__GPIO6_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
2034#define MX53_PAD_PATA_DIOW__UART1_TXD_MUX (_MX53_PAD_PATA_DIOW__UART1_TXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
2035#define MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2 (_MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
2036#define MX53_PAD_PATA_DMACK__PATA_DMACK (_MX53_PAD_PATA_DMACK__PATA_DMACK | MUX_PAD_CTRL(NO_PAD_CTRL))
2037#define MX53_PAD_PATA_DMACK__GPIO6_18 (_MX53_PAD_PATA_DMACK__GPIO6_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
2038#define MX53_PAD_PATA_DMACK__UART1_RXD_MUX (_MX53_PAD_PATA_DMACK__UART1_RXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
2039#define MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3 (_MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
2040#define MX53_PAD_PATA_DMARQ__PATA_DMARQ (_MX53_PAD_PATA_DMARQ__PATA_DMARQ | MUX_PAD_CTRL(NO_PAD_CTRL))
2041#define MX53_PAD_PATA_DMARQ__GPIO7_0 (_MX53_PAD_PATA_DMARQ__GPIO7_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
2042#define MX53_PAD_PATA_DMARQ__UART2_TXD_MUX (_MX53_PAD_PATA_DMARQ__UART2_TXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
2043#define MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0 (_MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
2044#define MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4 (_MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
2045#define MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN (_MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
2046#define MX53_PAD_PATA_BUFFER_EN__GPIO7_1 (_MX53_PAD_PATA_BUFFER_EN__GPIO7_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
2047#define MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX (_MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
2048#define MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1 (_MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
2049#define MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5 (_MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
2050#define MX53_PAD_PATA_INTRQ__PATA_INTRQ (_MX53_PAD_PATA_INTRQ__PATA_INTRQ | MUX_PAD_CTRL(NO_PAD_CTRL))
2051#define MX53_PAD_PATA_INTRQ__GPIO7_2 (_MX53_PAD_PATA_INTRQ__GPIO7_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
2052#define MX53_PAD_PATA_INTRQ__UART2_CTS (_MX53_PAD_PATA_INTRQ__UART2_CTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
2053#define MX53_PAD_PATA_INTRQ__CAN1_TXCAN (_MX53_PAD_PATA_INTRQ__CAN1_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
2054#define MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2 (_MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
2055#define MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6 (_MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
2056#define MX53_PAD_PATA_DIOR__PATA_DIOR (_MX53_PAD_PATA_DIOR__PATA_DIOR | MUX_PAD_CTRL(NO_PAD_CTRL))
2057#define MX53_PAD_PATA_DIOR__GPIO7_3 (_MX53_PAD_PATA_DIOR__GPIO7_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
2058#define MX53_PAD_PATA_DIOR__UART2_RTS (_MX53_PAD_PATA_DIOR__UART2_RTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
2059#define MX53_PAD_PATA_DIOR__CAN1_RXCAN (_MX53_PAD_PATA_DIOR__CAN1_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
2060#define MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7 (_MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
2061#define MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B (_MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B | MUX_PAD_CTRL(NO_PAD_CTRL))
2062#define MX53_PAD_PATA_RESET_B__GPIO7_4 (_MX53_PAD_PATA_RESET_B__GPIO7_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
2063#define MX53_PAD_PATA_RESET_B__ESDHC3_CMD (_MX53_PAD_PATA_RESET_B__ESDHC3_CMD | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2064#define MX53_PAD_PATA_RESET_B__UART1_CTS (_MX53_PAD_PATA_RESET_B__UART1_CTS | MUX_PAD_CTRL(NO_PAD_CTRL))
2065#define MX53_PAD_PATA_RESET_B__CAN2_TXCAN (_MX53_PAD_PATA_RESET_B__CAN2_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
2066#define MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0 (_MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
2067#define MX53_PAD_PATA_IORDY__PATA_IORDY (_MX53_PAD_PATA_IORDY__PATA_IORDY | MUX_PAD_CTRL(NO_PAD_CTRL))
2068#define MX53_PAD_PATA_IORDY__GPIO7_5 (_MX53_PAD_PATA_IORDY__GPIO7_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
2069#define MX53_PAD_PATA_IORDY__ESDHC3_CLK (_MX53_PAD_PATA_IORDY__ESDHC3_CLK | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2070#define MX53_PAD_PATA_IORDY__UART1_RTS (_MX53_PAD_PATA_IORDY__UART1_RTS | MUX_PAD_CTRL(NO_PAD_CTRL))
2071#define MX53_PAD_PATA_IORDY__CAN2_RXCAN (_MX53_PAD_PATA_IORDY__CAN2_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
2072#define MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1 (_MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
2073#define MX53_PAD_PATA_DA_0__PATA_DA_0 (_MX53_PAD_PATA_DA_0__PATA_DA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
2074#define MX53_PAD_PATA_DA_0__GPIO7_6 (_MX53_PAD_PATA_DA_0__GPIO7_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
2075#define MX53_PAD_PATA_DA_0__ESDHC3_RST (_MX53_PAD_PATA_DA_0__ESDHC3_RST | MUX_PAD_CTRL(NO_PAD_CTRL))
2076#define MX53_PAD_PATA_DA_0__OWIRE_LINE (_MX53_PAD_PATA_DA_0__OWIRE_LINE | MUX_PAD_CTRL(NO_PAD_CTRL))
2077#define MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2 (_MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
2078#define MX53_PAD_PATA_DA_1__PATA_DA_1 (_MX53_PAD_PATA_DA_1__PATA_DA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
2079#define MX53_PAD_PATA_DA_1__GPIO7_7 (_MX53_PAD_PATA_DA_1__GPIO7_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
2080#define MX53_PAD_PATA_DA_1__ESDHC4_CMD (_MX53_PAD_PATA_DA_1__ESDHC4_CMD | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2081#define MX53_PAD_PATA_DA_1__UART3_CTS (_MX53_PAD_PATA_DA_1__UART3_CTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
2082#define MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3 (_MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
2083#define MX53_PAD_PATA_DA_2__PATA_DA_2 (_MX53_PAD_PATA_DA_2__PATA_DA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
2084#define MX53_PAD_PATA_DA_2__GPIO7_8 (_MX53_PAD_PATA_DA_2__GPIO7_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
2085#define MX53_PAD_PATA_DA_2__ESDHC4_CLK (_MX53_PAD_PATA_DA_2__ESDHC4_CLK | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2086#define MX53_PAD_PATA_DA_2__UART3_RTS (_MX53_PAD_PATA_DA_2__UART3_RTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
2087#define MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4 (_MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
2088#define MX53_PAD_PATA_CS_0__PATA_CS_0 (_MX53_PAD_PATA_CS_0__PATA_CS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
2089#define MX53_PAD_PATA_CS_0__GPIO7_9 (_MX53_PAD_PATA_CS_0__GPIO7_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
2090#define MX53_PAD_PATA_CS_0__UART3_TXD_MUX (_MX53_PAD_PATA_CS_0__UART3_TXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
2091#define MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5 (_MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
2092#define MX53_PAD_PATA_CS_1__PATA_CS_1 (_MX53_PAD_PATA_CS_1__PATA_CS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
2093#define MX53_PAD_PATA_CS_1__GPIO7_10 (_MX53_PAD_PATA_CS_1__GPIO7_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
2094#define MX53_PAD_PATA_CS_1__UART3_RXD_MUX (_MX53_PAD_PATA_CS_1__UART3_RXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
2095#define MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6 (_MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
2096#define MX53_PAD_PATA_DATA0__PATA_DATA_0 (_MX53_PAD_PATA_DATA0__PATA_DATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
2097#define MX53_PAD_PATA_DATA0__GPIO2_0 (_MX53_PAD_PATA_DATA0__GPIO2_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
2098#define MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 (_MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
2099#define MX53_PAD_PATA_DATA0__ESDHC3_DAT4 (_MX53_PAD_PATA_DATA0__ESDHC3_DAT4 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2100#define MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0 (_MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
2101#define MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0 (_MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
2102#define MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7 (_MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
2103#define MX53_PAD_PATA_DATA1__PATA_DATA_1 (_MX53_PAD_PATA_DATA1__PATA_DATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
2104#define MX53_PAD_PATA_DATA1__GPIO2_1 (_MX53_PAD_PATA_DATA1__GPIO2_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
2105#define MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 (_MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
2106#define MX53_PAD_PATA_DATA1__ESDHC3_DAT5 (_MX53_PAD_PATA_DATA1__ESDHC3_DAT5 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2107#define MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1 (_MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
2108#define MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1 (_MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
2109#define MX53_PAD_PATA_DATA2__PATA_DATA_2 (_MX53_PAD_PATA_DATA2__PATA_DATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
2110#define MX53_PAD_PATA_DATA2__GPIO2_2 (_MX53_PAD_PATA_DATA2__GPIO2_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
2111#define MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 (_MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
2112#define MX53_PAD_PATA_DATA2__ESDHC3_DAT6 (_MX53_PAD_PATA_DATA2__ESDHC3_DAT6 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2113#define MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2 (_MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
2114#define MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2 (_MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
2115#define MX53_PAD_PATA_DATA3__PATA_DATA_3 (_MX53_PAD_PATA_DATA3__PATA_DATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
2116#define MX53_PAD_PATA_DATA3__GPIO2_3 (_MX53_PAD_PATA_DATA3__GPIO2_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
2117#define MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 (_MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
2118#define MX53_PAD_PATA_DATA3__ESDHC3_DAT7 (_MX53_PAD_PATA_DATA3__ESDHC3_DAT7 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2119#define MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3 (_MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
2120#define MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3 (_MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
2121#define MX53_PAD_PATA_DATA4__PATA_DATA_4 (_MX53_PAD_PATA_DATA4__PATA_DATA_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
2122#define MX53_PAD_PATA_DATA4__GPIO2_4 (_MX53_PAD_PATA_DATA4__GPIO2_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
2123#define MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 (_MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
2124#define MX53_PAD_PATA_DATA4__ESDHC4_DAT4 (_MX53_PAD_PATA_DATA4__ESDHC4_DAT4 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2125#define MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4 (_MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
2126#define MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4 (_MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
2127#define MX53_PAD_PATA_DATA5__PATA_DATA_5 (_MX53_PAD_PATA_DATA5__PATA_DATA_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
2128#define MX53_PAD_PATA_DATA5__GPIO2_5 (_MX53_PAD_PATA_DATA5__GPIO2_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
2129#define MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 (_MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
2130#define MX53_PAD_PATA_DATA5__ESDHC4_DAT5 (_MX53_PAD_PATA_DATA5__ESDHC4_DAT5 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2131#define MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5 (_MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
2132#define MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5 (_MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
2133#define MX53_PAD_PATA_DATA6__PATA_DATA_6 (_MX53_PAD_PATA_DATA6__PATA_DATA_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
2134#define MX53_PAD_PATA_DATA6__GPIO2_6 (_MX53_PAD_PATA_DATA6__GPIO2_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
2135#define MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 (_MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
2136#define MX53_PAD_PATA_DATA6__ESDHC4_DAT6 (_MX53_PAD_PATA_DATA6__ESDHC4_DAT6 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2137#define MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6 (_MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
2138#define MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6 (_MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
2139#define MX53_PAD_PATA_DATA7__PATA_DATA_7 (_MX53_PAD_PATA_DATA7__PATA_DATA_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
2140#define MX53_PAD_PATA_DATA7__GPIO2_7 (_MX53_PAD_PATA_DATA7__GPIO2_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
2141#define MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 (_MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
2142#define MX53_PAD_PATA_DATA7__ESDHC4_DAT7 (_MX53_PAD_PATA_DATA7__ESDHC4_DAT7 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2143#define MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7 (_MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
2144#define MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7 (_MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
2145#define MX53_PAD_PATA_DATA8__PATA_DATA_8 (_MX53_PAD_PATA_DATA8__PATA_DATA_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
2146#define MX53_PAD_PATA_DATA8__GPIO2_8 (_MX53_PAD_PATA_DATA8__GPIO2_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
2147#define MX53_PAD_PATA_DATA8__ESDHC1_DAT4 (_MX53_PAD_PATA_DATA8__ESDHC1_DAT4 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2148#define MX53_PAD_PATA_DATA8__EMI_NANDF_D_8 (_MX53_PAD_PATA_DATA8__EMI_NANDF_D_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
2149#define MX53_PAD_PATA_DATA8__ESDHC3_DAT0 (_MX53_PAD_PATA_DATA8__ESDHC3_DAT0 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2150#define MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8 (_MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
2151#define MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8 (_MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
2152#define MX53_PAD_PATA_DATA9__PATA_DATA_9 (_MX53_PAD_PATA_DATA9__PATA_DATA_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
2153#define MX53_PAD_PATA_DATA9__GPIO2_9 (_MX53_PAD_PATA_DATA9__GPIO2_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
2154#define MX53_PAD_PATA_DATA9__ESDHC1_DAT5 (_MX53_PAD_PATA_DATA9__ESDHC1_DAT5 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2155#define MX53_PAD_PATA_DATA9__EMI_NANDF_D_9 (_MX53_PAD_PATA_DATA9__EMI_NANDF_D_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
2156#define MX53_PAD_PATA_DATA9__ESDHC3_DAT1 (_MX53_PAD_PATA_DATA9__ESDHC3_DAT1 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2157#define MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9 (_MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
2158#define MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9 (_MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
2159#define MX53_PAD_PATA_DATA10__PATA_DATA_10 (_MX53_PAD_PATA_DATA10__PATA_DATA_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
2160#define MX53_PAD_PATA_DATA10__GPIO2_10 (_MX53_PAD_PATA_DATA10__GPIO2_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
2161#define MX53_PAD_PATA_DATA10__ESDHC1_DAT6 (_MX53_PAD_PATA_DATA10__ESDHC1_DAT6 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2162#define MX53_PAD_PATA_DATA10__EMI_NANDF_D_10 (_MX53_PAD_PATA_DATA10__EMI_NANDF_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
2163#define MX53_PAD_PATA_DATA10__ESDHC3_DAT2 (_MX53_PAD_PATA_DATA10__ESDHC3_DAT2 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2164#define MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10 (_MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
2165#define MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10 (_MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
2166#define MX53_PAD_PATA_DATA11__PATA_DATA_11 (_MX53_PAD_PATA_DATA11__PATA_DATA_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
2167#define MX53_PAD_PATA_DATA11__GPIO2_11 (_MX53_PAD_PATA_DATA11__GPIO2_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
2168#define MX53_PAD_PATA_DATA11__ESDHC1_DAT7 (_MX53_PAD_PATA_DATA11__ESDHC1_DAT7 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2169#define MX53_PAD_PATA_DATA11__EMI_NANDF_D_11 (_MX53_PAD_PATA_DATA11__EMI_NANDF_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
2170#define MX53_PAD_PATA_DATA11__ESDHC3_DAT3 (_MX53_PAD_PATA_DATA11__ESDHC3_DAT3 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2171#define MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11 (_MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
2172#define MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11 (_MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
2173#define MX53_PAD_PATA_DATA12__PATA_DATA_12 (_MX53_PAD_PATA_DATA12__PATA_DATA_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
2174#define MX53_PAD_PATA_DATA12__GPIO2_12 (_MX53_PAD_PATA_DATA12__GPIO2_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
2175#define MX53_PAD_PATA_DATA12__ESDHC2_DAT4 (_MX53_PAD_PATA_DATA12__ESDHC2_DAT4 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2176#define MX53_PAD_PATA_DATA12__EMI_NANDF_D_12 (_MX53_PAD_PATA_DATA12__EMI_NANDF_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
2177#define MX53_PAD_PATA_DATA12__ESDHC4_DAT0 (_MX53_PAD_PATA_DATA12__ESDHC4_DAT0 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2178#define MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12 (_MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
2179#define MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12 (_MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
2180#define MX53_PAD_PATA_DATA13__PATA_DATA_13 (_MX53_PAD_PATA_DATA13__PATA_DATA_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
2181#define MX53_PAD_PATA_DATA13__GPIO2_13 (_MX53_PAD_PATA_DATA13__GPIO2_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
2182#define MX53_PAD_PATA_DATA13__ESDHC2_DAT5 (_MX53_PAD_PATA_DATA13__ESDHC2_DAT5 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2183#define MX53_PAD_PATA_DATA13__EMI_NANDF_D_13 (_MX53_PAD_PATA_DATA13__EMI_NANDF_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
2184#define MX53_PAD_PATA_DATA13__ESDHC4_DAT1 (_MX53_PAD_PATA_DATA13__ESDHC4_DAT1 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2185#define MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13 (_MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
2186#define MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13 (_MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
2187#define MX53_PAD_PATA_DATA14__PATA_DATA_14 (_MX53_PAD_PATA_DATA14__PATA_DATA_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
2188#define MX53_PAD_PATA_DATA14__GPIO2_14 (_MX53_PAD_PATA_DATA14__GPIO2_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
2189#define MX53_PAD_PATA_DATA14__ESDHC2_DAT6 (_MX53_PAD_PATA_DATA14__ESDHC2_DAT6 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2190#define MX53_PAD_PATA_DATA14__EMI_NANDF_D_14 (_MX53_PAD_PATA_DATA14__EMI_NANDF_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
2191#define MX53_PAD_PATA_DATA14__ESDHC4_DAT2 (_MX53_PAD_PATA_DATA14__ESDHC4_DAT2 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2192#define MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14 (_MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
2193#define MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14 (_MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
2194#define MX53_PAD_PATA_DATA15__PATA_DATA_15 (_MX53_PAD_PATA_DATA15__PATA_DATA_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
2195#define MX53_PAD_PATA_DATA15__GPIO2_15 (_MX53_PAD_PATA_DATA15__GPIO2_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
2196#define MX53_PAD_PATA_DATA15__ESDHC2_DAT7 (_MX53_PAD_PATA_DATA15__ESDHC2_DAT7 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2197#define MX53_PAD_PATA_DATA15__EMI_NANDF_D_15 (_MX53_PAD_PATA_DATA15__EMI_NANDF_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
2198#define MX53_PAD_PATA_DATA15__ESDHC4_DAT3 (_MX53_PAD_PATA_DATA15__ESDHC4_DAT3 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2199#define MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15 (_MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
2200#define MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15 (_MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
2201#define MX53_PAD_SD1_DATA0__ESDHC1_DAT0 (_MX53_PAD_SD1_DATA0__ESDHC1_DAT0 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2202#define MX53_PAD_SD1_DATA0__GPIO1_16 (_MX53_PAD_SD1_DATA0__GPIO1_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
2203#define MX53_PAD_SD1_DATA0__GPT_CAPIN1 (_MX53_PAD_SD1_DATA0__GPT_CAPIN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
2204#define MX53_PAD_SD1_DATA0__CSPI_MISO (_MX53_PAD_SD1_DATA0__CSPI_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
2205#define MX53_PAD_SD1_DATA0__CCM_PLL3_BYP (_MX53_PAD_SD1_DATA0__CCM_PLL3_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
2206#define MX53_PAD_SD1_DATA1__ESDHC1_DAT1 (_MX53_PAD_SD1_DATA1__ESDHC1_DAT1 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2207#define MX53_PAD_SD1_DATA1__GPIO1_17 (_MX53_PAD_SD1_DATA1__GPIO1_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
2208#define MX53_PAD_SD1_DATA1__GPT_CAPIN2 (_MX53_PAD_SD1_DATA1__GPT_CAPIN2 | MUX_PAD_CTRL(NO_PAD_CTRL))
2209#define MX53_PAD_SD1_DATA1__CSPI_SS0 (_MX53_PAD_SD1_DATA1__CSPI_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
2210#define MX53_PAD_SD1_DATA1__CCM_PLL4_BYP (_MX53_PAD_SD1_DATA1__CCM_PLL4_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
2211#define MX53_PAD_SD1_CMD__ESDHC1_CMD (_MX53_PAD_SD1_CMD__ESDHC1_CMD | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2212#define MX53_PAD_SD1_CMD__GPIO1_18 (_MX53_PAD_SD1_CMD__GPIO1_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
2213#define MX53_PAD_SD1_CMD__GPT_CMPOUT1 (_MX53_PAD_SD1_CMD__GPT_CMPOUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
2214#define MX53_PAD_SD1_CMD__CSPI_MOSI (_MX53_PAD_SD1_CMD__CSPI_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
2215#define MX53_PAD_SD1_CMD__CCM_PLL1_BYP (_MX53_PAD_SD1_CMD__CCM_PLL1_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
2216#define MX53_PAD_SD1_DATA2__ESDHC1_DAT2 (_MX53_PAD_SD1_DATA2__ESDHC1_DAT2 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2217#define MX53_PAD_SD1_DATA2__GPIO1_19 (_MX53_PAD_SD1_DATA2__GPIO1_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
2218#define MX53_PAD_SD1_DATA2__GPT_CMPOUT2 (_MX53_PAD_SD1_DATA2__GPT_CMPOUT2 | MUX_PAD_CTRL(NO_PAD_CTRL))
2219#define MX53_PAD_SD1_DATA2__PWM2_PWMO (_MX53_PAD_SD1_DATA2__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
2220#define MX53_PAD_SD1_DATA2__WDOG1_WDOG_B (_MX53_PAD_SD1_DATA2__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
2221#define MX53_PAD_SD1_DATA2__CSPI_SS1 (_MX53_PAD_SD1_DATA2__CSPI_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
2222#define MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB (_MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB | MUX_PAD_CTRL(NO_PAD_CTRL))
2223#define MX53_PAD_SD1_DATA2__CCM_PLL2_BYP (_MX53_PAD_SD1_DATA2__CCM_PLL2_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
2224#define MX53_PAD_SD1_CLK__ESDHC1_CLK (_MX53_PAD_SD1_CLK__ESDHC1_CLK | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2225#define MX53_PAD_SD1_CLK__GPIO1_20 (_MX53_PAD_SD1_CLK__GPIO1_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
2226#define MX53_PAD_SD1_CLK__OSC32k_32K_OUT (_MX53_PAD_SD1_CLK__OSC32k_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
2227#define MX53_PAD_SD1_CLK__GPT_CLKIN (_MX53_PAD_SD1_CLK__GPT_CLKIN | MUX_PAD_CTRL(NO_PAD_CTRL))
2228#define MX53_PAD_SD1_CLK__CSPI_SCLK (_MX53_PAD_SD1_CLK__CSPI_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
2229#define MX53_PAD_SD1_CLK__SATA_PHY_DTB_0 (_MX53_PAD_SD1_CLK__SATA_PHY_DTB_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
2230#define MX53_PAD_SD1_DATA3__ESDHC1_DAT3 (_MX53_PAD_SD1_DATA3__ESDHC1_DAT3 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2231#define MX53_PAD_SD1_DATA3__GPIO1_21 (_MX53_PAD_SD1_DATA3__GPIO1_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
2232#define MX53_PAD_SD1_DATA3__GPT_CMPOUT3 (_MX53_PAD_SD1_DATA3__GPT_CMPOUT3 | MUX_PAD_CTRL(NO_PAD_CTRL))
2233#define MX53_PAD_SD1_DATA3__PWM1_PWMO (_MX53_PAD_SD1_DATA3__PWM1_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
2234#define MX53_PAD_SD1_DATA3__WDOG2_WDOG_B (_MX53_PAD_SD1_DATA3__WDOG2_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
2235#define MX53_PAD_SD1_DATA3__CSPI_SS2 (_MX53_PAD_SD1_DATA3__CSPI_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
2236#define MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB (_MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB | MUX_PAD_CTRL(NO_PAD_CTRL))
2237#define MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1 (_MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
2238#define MX53_PAD_SD2_CLK__ESDHC2_CLK (_MX53_PAD_SD2_CLK__ESDHC2_CLK | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2239#define MX53_PAD_SD2_CLK__GPIO1_10 (_MX53_PAD_SD2_CLK__GPIO1_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
2240#define MX53_PAD_SD2_CLK__KPP_COL_5 (_MX53_PAD_SD2_CLK__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
2241#define MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS (_MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
2242#define MX53_PAD_SD2_CLK__CSPI_SCLK (_MX53_PAD_SD2_CLK__CSPI_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
2243#define MX53_PAD_SD2_CLK__SCC_RANDOM_V (_MX53_PAD_SD2_CLK__SCC_RANDOM_V | MUX_PAD_CTRL(NO_PAD_CTRL))
2244#define MX53_PAD_SD2_CMD__ESDHC2_CMD (_MX53_PAD_SD2_CMD__ESDHC2_CMD | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2245#define MX53_PAD_SD2_CMD__GPIO1_11 (_MX53_PAD_SD2_CMD__GPIO1_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
2246#define MX53_PAD_SD2_CMD__KPP_ROW_5 (_MX53_PAD_SD2_CMD__KPP_ROW_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
2247#define MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC (_MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
2248#define MX53_PAD_SD2_CMD__CSPI_MOSI (_MX53_PAD_SD2_CMD__CSPI_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
2249#define MX53_PAD_SD2_CMD__SCC_RANDOM (_MX53_PAD_SD2_CMD__SCC_RANDOM | MUX_PAD_CTRL(NO_PAD_CTRL))
2250#define MX53_PAD_SD2_DATA3__ESDHC2_DAT3 (_MX53_PAD_SD2_DATA3__ESDHC2_DAT3 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2251#define MX53_PAD_SD2_DATA3__GPIO1_12 (_MX53_PAD_SD2_DATA3__GPIO1_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
2252#define MX53_PAD_SD2_DATA3__KPP_COL_6 (_MX53_PAD_SD2_DATA3__KPP_COL_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
2253#define MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC (_MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
2254#define MX53_PAD_SD2_DATA3__CSPI_SS2 (_MX53_PAD_SD2_DATA3__CSPI_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
2255#define MX53_PAD_SD2_DATA3__SJC_DONE (_MX53_PAD_SD2_DATA3__SJC_DONE | MUX_PAD_CTRL(NO_PAD_CTRL))
2256#define MX53_PAD_SD2_DATA2__ESDHC2_DAT2 (_MX53_PAD_SD2_DATA2__ESDHC2_DAT2 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2257#define MX53_PAD_SD2_DATA2__GPIO1_13 (_MX53_PAD_SD2_DATA2__GPIO1_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
2258#define MX53_PAD_SD2_DATA2__KPP_ROW_6 (_MX53_PAD_SD2_DATA2__KPP_ROW_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
2259#define MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD (_MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
2260#define MX53_PAD_SD2_DATA2__CSPI_SS1 (_MX53_PAD_SD2_DATA2__CSPI_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
2261#define MX53_PAD_SD2_DATA2__SJC_FAIL (_MX53_PAD_SD2_DATA2__SJC_FAIL | MUX_PAD_CTRL(NO_PAD_CTRL))
2262#define MX53_PAD_SD2_DATA1__ESDHC2_DAT1 (_MX53_PAD_SD2_DATA1__ESDHC2_DAT1 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2263#define MX53_PAD_SD2_DATA1__GPIO1_14 (_MX53_PAD_SD2_DATA1__GPIO1_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
2264#define MX53_PAD_SD2_DATA1__KPP_COL_7 (_MX53_PAD_SD2_DATA1__KPP_COL_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
2265#define MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS (_MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
2266#define MX53_PAD_SD2_DATA1__CSPI_SS0 (_MX53_PAD_SD2_DATA1__CSPI_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
2267#define MX53_PAD_SD2_DATA1__RTIC_SEC_VIO (_MX53_PAD_SD2_DATA1__RTIC_SEC_VIO | MUX_PAD_CTRL(NO_PAD_CTRL))
2268#define MX53_PAD_SD2_DATA0__ESDHC2_DAT0 (_MX53_PAD_SD2_DATA0__ESDHC2_DAT0 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2269#define MX53_PAD_SD2_DATA0__GPIO1_15 (_MX53_PAD_SD2_DATA0__GPIO1_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
2270#define MX53_PAD_SD2_DATA0__KPP_ROW_7 (_MX53_PAD_SD2_DATA0__KPP_ROW_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
2271#define MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD (_MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
2272#define MX53_PAD_SD2_DATA0__CSPI_MISO (_MX53_PAD_SD2_DATA0__CSPI_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
2273#define MX53_PAD_SD2_DATA0__RTIC_DONE_INT (_MX53_PAD_SD2_DATA0__RTIC_DONE_INT | MUX_PAD_CTRL(NO_PAD_CTRL))
2274#define MX53_PAD_GPIO_0__CCM_CLKO (_MX53_PAD_GPIO_0__CCM_CLKO | MUX_PAD_CTRL(NO_PAD_CTRL))
2275#define MX53_PAD_GPIO_0__GPIO1_0 (_MX53_PAD_GPIO_0__GPIO1_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
2276#define MX53_PAD_GPIO_0__KPP_COL_5 (_MX53_PAD_GPIO_0__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
2277#define MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK (_MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
2278#define MX53_PAD_GPIO_0__EPIT1_EPITO (_MX53_PAD_GPIO_0__EPIT1_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL))
2279#define MX53_PAD_GPIO_0__SRTC_ALARM_DEB (_MX53_PAD_GPIO_0__SRTC_ALARM_DEB | MUX_PAD_CTRL(NO_PAD_CTRL))
2280#define MX53_PAD_GPIO_0__USBOH3_USBH1_PWR (_MX53_PAD_GPIO_0__USBOH3_USBH1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
2281#define MX53_PAD_GPIO_0__CSU_TD (_MX53_PAD_GPIO_0__CSU_TD | MUX_PAD_CTRL(NO_PAD_CTRL))
2282#define MX53_PAD_GPIO_1__ESAI1_SCKR (_MX53_PAD_GPIO_1__ESAI1_SCKR | MUX_PAD_CTRL(NO_PAD_CTRL))
2283#define MX53_PAD_GPIO_1__GPIO1_1 (_MX53_PAD_GPIO_1__GPIO1_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
2284#define MX53_PAD_GPIO_1__KPP_ROW_5 (_MX53_PAD_GPIO_1__KPP_ROW_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
2285#define MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK (_MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
2286#define MX53_PAD_GPIO_1__PWM2_PWMO (_MX53_PAD_GPIO_1__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
2287#define MX53_PAD_GPIO_1__WDOG2_WDOG_B (_MX53_PAD_GPIO_1__WDOG2_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
2288#define MX53_PAD_GPIO_1__ESDHC1_CD (_MX53_PAD_GPIO_1__ESDHC1_CD | MUX_PAD_CTRL(NO_PAD_CTRL))
2289#define MX53_PAD_GPIO_1__SRC_TESTER_ACK (_MX53_PAD_GPIO_1__SRC_TESTER_ACK | MUX_PAD_CTRL(NO_PAD_CTRL))
2290#define MX53_PAD_GPIO_9__ESAI1_FSR (_MX53_PAD_GPIO_9__ESAI1_FSR | MUX_PAD_CTRL(NO_PAD_CTRL))
2291#define MX53_PAD_GPIO_9__GPIO1_9 (_MX53_PAD_GPIO_9__GPIO1_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
2292#define MX53_PAD_GPIO_9__KPP_COL_6 (_MX53_PAD_GPIO_9__KPP_COL_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
2293#define MX53_PAD_GPIO_9__CCM_REF_EN_B (_MX53_PAD_GPIO_9__CCM_REF_EN_B | MUX_PAD_CTRL(NO_PAD_CTRL))
2294#define MX53_PAD_GPIO_9__PWM1_PWMO (_MX53_PAD_GPIO_9__PWM1_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
2295#define MX53_PAD_GPIO_9__WDOG1_WDOG_B (_MX53_PAD_GPIO_9__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
2296#define MX53_PAD_GPIO_9__ESDHC1_WP (_MX53_PAD_GPIO_9__ESDHC1_WP | MUX_PAD_CTRL(NO_PAD_CTRL))
2297#define MX53_PAD_GPIO_9__SCC_FAIL_STATE (_MX53_PAD_GPIO_9__SCC_FAIL_STATE | MUX_PAD_CTRL(NO_PAD_CTRL))
2298#define MX53_PAD_GPIO_3__ESAI1_HCKR (_MX53_PAD_GPIO_3__ESAI1_HCKR | MUX_PAD_CTRL(NO_PAD_CTRL))
2299#define MX53_PAD_GPIO_3__GPIO1_3 (_MX53_PAD_GPIO_3__GPIO1_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
2300#define MX53_PAD_GPIO_3__I2C3_SCL (_MX53_PAD_GPIO_3__I2C3_SCL | MUX_PAD_CTRL(NO_PAD_CTRL))
2301#define MX53_PAD_GPIO_3__DPLLIP1_TOG_EN (_MX53_PAD_GPIO_3__DPLLIP1_TOG_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
2302#define MX53_PAD_GPIO_3__CCM_CLKO2 (_MX53_PAD_GPIO_3__CCM_CLKO2 | MUX_PAD_CTRL(NO_PAD_CTRL))
2303#define MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 (_MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 | MUX_PAD_CTRL(NO_PAD_CTRL))
2304#define MX53_PAD_GPIO_3__USBOH3_USBH1_OC (_MX53_PAD_GPIO_3__USBOH3_USBH1_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
2305#define MX53_PAD_GPIO_3__MLB_MLBCLK (_MX53_PAD_GPIO_3__MLB_MLBCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
2306#define MX53_PAD_GPIO_6__ESAI1_SCKT (_MX53_PAD_GPIO_6__ESAI1_SCKT | MUX_PAD_CTRL(NO_PAD_CTRL))
2307#define MX53_PAD_GPIO_6__GPIO1_6 (_MX53_PAD_GPIO_6__GPIO1_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
2308#define MX53_PAD_GPIO_6__I2C3_SDA (_MX53_PAD_GPIO_6__I2C3_SDA | MUX_PAD_CTRL(NO_PAD_CTRL))
2309#define MX53_PAD_GPIO_6__CCM_CCM_OUT_0 (_MX53_PAD_GPIO_6__CCM_CCM_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
2310#define MX53_PAD_GPIO_6__CSU_CSU_INT_DEB (_MX53_PAD_GPIO_6__CSU_CSU_INT_DEB | MUX_PAD_CTRL(NO_PAD_CTRL))
2311#define MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 (_MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
2312#define MX53_PAD_GPIO_6__ESDHC2_LCTL (_MX53_PAD_GPIO_6__ESDHC2_LCTL | MUX_PAD_CTRL(NO_PAD_CTRL))
2313#define MX53_PAD_GPIO_6__MLB_MLBSIG (_MX53_PAD_GPIO_6__MLB_MLBSIG | MUX_PAD_CTRL(NO_PAD_CTRL))
2314#define MX53_PAD_GPIO_2__ESAI1_FST (_MX53_PAD_GPIO_2__ESAI1_FST | MUX_PAD_CTRL(NO_PAD_CTRL))
2315#define MX53_PAD_GPIO_2__GPIO1_2 (_MX53_PAD_GPIO_2__GPIO1_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
2316#define MX53_PAD_GPIO_2__KPP_ROW_6 (_MX53_PAD_GPIO_2__KPP_ROW_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
2317#define MX53_PAD_GPIO_2__CCM_CCM_OUT_1 (_MX53_PAD_GPIO_2__CCM_CCM_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
2318#define MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 (_MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
2319#define MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 (_MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 | MUX_PAD_CTRL(NO_PAD_CTRL))
2320#define MX53_PAD_GPIO_2__ESDHC2_WP (_MX53_PAD_GPIO_2__ESDHC2_WP | MUX_PAD_CTRL(NO_PAD_CTRL))
2321#define MX53_PAD_GPIO_2__MLB_MLBDAT (_MX53_PAD_GPIO_2__MLB_MLBDAT | MUX_PAD_CTRL(NO_PAD_CTRL))
2322#define MX53_PAD_GPIO_4__ESAI1_HCKT (_MX53_PAD_GPIO_4__ESAI1_HCKT | MUX_PAD_CTRL(NO_PAD_CTRL))
2323#define MX53_PAD_GPIO_4__GPIO1_4 (_MX53_PAD_GPIO_4__GPIO1_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
2324#define MX53_PAD_GPIO_4__KPP_COL_7 (_MX53_PAD_GPIO_4__KPP_COL_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
2325#define MX53_PAD_GPIO_4__CCM_CCM_OUT_2 (_MX53_PAD_GPIO_4__CCM_CCM_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
2326#define MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 (_MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
2327#define MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 (_MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 | MUX_PAD_CTRL(NO_PAD_CTRL))
2328#define MX53_PAD_GPIO_4__ESDHC2_CD (_MX53_PAD_GPIO_4__ESDHC2_CD | MUX_PAD_CTRL(NO_PAD_CTRL))
2329#define MX53_PAD_GPIO_4__SCC_SEC_STATE (_MX53_PAD_GPIO_4__SCC_SEC_STATE | MUX_PAD_CTRL(NO_PAD_CTRL))
2330#define MX53_PAD_GPIO_5__ESAI1_TX2_RX3 (_MX53_PAD_GPIO_5__ESAI1_TX2_RX3 | MUX_PAD_CTRL(NO_PAD_CTRL))
2331#define MX53_PAD_GPIO_5__GPIO1_5 (_MX53_PAD_GPIO_5__GPIO1_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
2332#define MX53_PAD_GPIO_5__KPP_ROW_7 (_MX53_PAD_GPIO_5__KPP_ROW_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
2333#define MX53_PAD_GPIO_5__CCM_CLKO (_MX53_PAD_GPIO_5__CCM_CLKO | MUX_PAD_CTRL(NO_PAD_CTRL))
2334#define MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 (_MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
2335#define MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 (_MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 | MUX_PAD_CTRL(NO_PAD_CTRL))
2336#define MX53_PAD_GPIO_5__I2C3_SCL (_MX53_PAD_GPIO_5__I2C3_SCL | MUX_PAD_CTRL(NO_PAD_CTRL))
2337#define MX53_PAD_GPIO_5__CCM_PLL1_BYP (_MX53_PAD_GPIO_5__CCM_PLL1_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
2338#define MX53_PAD_GPIO_7__ESAI1_TX4_RX1 (_MX53_PAD_GPIO_7__ESAI1_TX4_RX1 | MUX_PAD_CTRL(NO_PAD_CTRL))
2339#define MX53_PAD_GPIO_7__GPIO1_7 (_MX53_PAD_GPIO_7__GPIO1_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
2340#define MX53_PAD_GPIO_7__EPIT1_EPITO (_MX53_PAD_GPIO_7__EPIT1_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL))
2341#define MX53_PAD_GPIO_7__CAN1_TXCAN (_MX53_PAD_GPIO_7__CAN1_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
2342#define MX53_PAD_GPIO_7__UART2_TXD_MUX (_MX53_PAD_GPIO_7__UART2_TXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL))
2343#define MX53_PAD_GPIO_7__FIRI_RXD (_MX53_PAD_GPIO_7__FIRI_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
2344#define MX53_PAD_GPIO_7__SPDIF_PLOCK (_MX53_PAD_GPIO_7__SPDIF_PLOCK | MUX_PAD_CTRL(NO_PAD_CTRL))
2345#define MX53_PAD_GPIO_7__CCM_PLL2_BYP (_MX53_PAD_GPIO_7__CCM_PLL2_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
2346#define MX53_PAD_GPIO_8__ESAI1_TX5_RX0 (_MX53_PAD_GPIO_8__ESAI1_TX5_RX0 | MUX_PAD_CTRL(NO_PAD_CTRL))
2347#define MX53_PAD_GPIO_8__GPIO1_8 (_MX53_PAD_GPIO_8__GPIO1_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
2348#define MX53_PAD_GPIO_8__EPIT2_EPITO (_MX53_PAD_GPIO_8__EPIT2_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL))
2349#define MX53_PAD_GPIO_8__CAN1_RXCAN (_MX53_PAD_GPIO_8__CAN1_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
2350#define MX53_PAD_GPIO_8__UART2_RXD_MUX (_MX53_PAD_GPIO_8__UART2_RXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL))
2351#define MX53_PAD_GPIO_8__FIRI_TXD (_MX53_PAD_GPIO_8__FIRI_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
2352#define MX53_PAD_GPIO_8__SPDIF_SRCLK (_MX53_PAD_GPIO_8__SPDIF_SRCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
2353#define MX53_PAD_GPIO_8__CCM_PLL3_BYP (_MX53_PAD_GPIO_8__CCM_PLL3_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
2354#define MX53_PAD_GPIO_16__ESAI1_TX3_RX2 (_MX53_PAD_GPIO_16__ESAI1_TX3_RX2 | MUX_PAD_CTRL(NO_PAD_CTRL))
2355#define MX53_PAD_GPIO_16__GPIO7_11 (_MX53_PAD_GPIO_16__GPIO7_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
2356#define MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT (_MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT | MUX_PAD_CTRL(NO_PAD_CTRL))
2357#define MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1 (_MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1 | MUX_PAD_CTRL(NO_PAD_CTRL))
2358#define MX53_PAD_GPIO_16__SPDIF_IN1 (_MX53_PAD_GPIO_16__SPDIF_IN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
2359#define MX53_PAD_GPIO_16__I2C3_SDA (_MX53_PAD_GPIO_16__I2C3_SDA | MUX_PAD_CTRL(NO_PAD_CTRL))
2360#define MX53_PAD_GPIO_16__SJC_DE_B (_MX53_PAD_GPIO_16__SJC_DE_B | MUX_PAD_CTRL(NO_PAD_CTRL))
2361#define MX53_PAD_GPIO_17__ESAI1_TX0 (_MX53_PAD_GPIO_17__ESAI1_TX0 | MUX_PAD_CTRL(NO_PAD_CTRL))
2362#define MX53_PAD_GPIO_17__GPIO7_12 (_MX53_PAD_GPIO_17__GPIO7_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
2363#define MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0 (_MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
2364#define MX53_PAD_GPIO_17__GPC_PMIC_RDY (_MX53_PAD_GPIO_17__GPC_PMIC_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
2365#define MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG (_MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG | MUX_PAD_CTRL(NO_PAD_CTRL))
2366#define MX53_PAD_GPIO_17__SPDIF_OUT1 (_MX53_PAD_GPIO_17__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
2367#define MX53_PAD_GPIO_17__IPU_SNOOP2 (_MX53_PAD_GPIO_17__IPU_SNOOP2 | MUX_PAD_CTRL(NO_PAD_CTRL))
2368#define MX53_PAD_GPIO_17__SJC_JTAG_ACT (_MX53_PAD_GPIO_17__SJC_JTAG_ACT | MUX_PAD_CTRL(NO_PAD_CTRL))
2369#define MX53_PAD_GPIO_18__ESAI1_TX1 (_MX53_PAD_GPIO_18__ESAI1_TX1 | MUX_PAD_CTRL(NO_PAD_CTRL))
2370#define MX53_PAD_GPIO_18__GPIO7_13 (_MX53_PAD_GPIO_18__GPIO7_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
2371#define MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1 (_MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
2372#define MX53_PAD_GPIO_18__OWIRE_LINE (_MX53_PAD_GPIO_18__OWIRE_LINE | MUX_PAD_CTRL(NO_PAD_CTRL))
2373#define MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG (_MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG | MUX_PAD_CTRL(NO_PAD_CTRL))
2374#define MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK (_MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
2375#define MX53_PAD_GPIO_18__ESDHC1_LCTL (_MX53_PAD_GPIO_18__ESDHC1_LCTL | MUX_PAD_CTRL(NO_PAD_CTRL))
2376#define MX53_PAD_GPIO_18__SRC_SYSTEM_RST (_MX53_PAD_GPIO_18__SRC_SYSTEM_RST | MUX_PAD_CTRL(NO_PAD_CTRL))
324 2377
325#endif /* __MACH_IOMUX_MX53_H__ */ 2378#endif /* __MACH_IOMUX_MX53_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h b/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h
index 15d59510f597..bf28df0d58b7 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h
@@ -46,12 +46,12 @@
46 * - setups the iomux according to the configuration 46 * - setups the iomux according to the configuration
47 * - if the pin is configured as a GPIO, we claim it through kernel gpiolib 47 * - if the pin is configured as a GPIO, we claim it through kernel gpiolib
48 */ 48 */
49int mxc_iomux_alloc_pin(const unsigned int pin_mode, const char *label); 49int mxc_iomux_alloc_pin(unsigned int pin_mode, const char *label);
50/* 50/*
51 * setups mutliple pins 51 * setups mutliple pins
52 * convenient way to call the above function with tables 52 * convenient way to call the above function with tables
53 */ 53 */
54int mxc_iomux_setup_multiple_pins(unsigned int *pin_list, unsigned count, 54int mxc_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count,
55 const char *label); 55 const char *label);
56 56
57/* 57/*
@@ -60,12 +60,12 @@ int mxc_iomux_setup_multiple_pins(unsigned int *pin_list, unsigned count,
60 * - frees the GPIO if the pin was configured as GPIO 60 * - frees the GPIO if the pin was configured as GPIO
61 * - DOES NOT reconfigure the IOMUX in its reset state 61 * - DOES NOT reconfigure the IOMUX in its reset state
62 */ 62 */
63void mxc_iomux_release_pin(const unsigned int pin_mode); 63void mxc_iomux_release_pin(unsigned int pin_mode);
64/* 64/*
65 * releases multiple pins 65 * releases multiple pins
66 * convenvient way to call the above function with tables 66 * convenvient way to call the above function with tables
67 */ 67 */
68void mxc_iomux_release_multiple_pins(unsigned int *pin_list, int count); 68void mxc_iomux_release_multiple_pins(const unsigned int *pin_list, int count);
69 69
70#define MUX_SIDE_AP (0) 70#define MUX_SIDE_AP (0)
71#define MUX_SIDE_SP (1) 71#define MUX_SIDE_SP (1)
diff --git a/arch/arm/plat-mxc/include/mach/iomux-v1.h b/arch/arm/plat-mxc/include/mach/iomux-v1.h
index 884f5753f279..c07d30210c57 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-v1.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-v1.h
@@ -100,4 +100,6 @@ extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
100 const char *label); 100 const char *label);
101extern void mxc_gpio_release_multiple_pins(const int *pin_list, int count); 101extern void mxc_gpio_release_multiple_pins(const int *pin_list, int count);
102 102
103extern int __init imx_iomuxv1_init(void __iomem *base, int numports);
104
103#endif /* __MACH_IOMUX_V1_H__ */ 105#endif /* __MACH_IOMUX_V1_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h
index ba65c9231a78..a3d930d3e65d 100644
--- a/arch/arm/plat-mxc/include/mach/irqs.h
+++ b/arch/arm/plat-mxc/include/mach/irqs.h
@@ -23,17 +23,17 @@
23#define MXC_GPIO_IRQ_START MXC_INTERNAL_IRQS 23#define MXC_GPIO_IRQ_START MXC_INTERNAL_IRQS
24 24
25/* these are ordered by size to support multi-SoC kernels */ 25/* these are ordered by size to support multi-SoC kernels */
26#if defined CONFIG_ARCH_MX53 26#if defined CONFIG_SOC_IMX53
27#define MXC_GPIO_IRQS (32 * 7) 27#define MXC_GPIO_IRQS (32 * 7)
28#elif defined CONFIG_ARCH_MX2 28#elif defined CONFIG_ARCH_MX2
29#define MXC_GPIO_IRQS (32 * 6) 29#define MXC_GPIO_IRQS (32 * 6)
30#elif defined CONFIG_ARCH_MX50 30#elif defined CONFIG_SOC_IMX50
31#define MXC_GPIO_IRQS (32 * 6) 31#define MXC_GPIO_IRQS (32 * 6)
32#elif defined CONFIG_ARCH_MX1 32#elif defined CONFIG_ARCH_MX1
33#define MXC_GPIO_IRQS (32 * 4) 33#define MXC_GPIO_IRQS (32 * 4)
34#elif defined CONFIG_ARCH_MX25 34#elif defined CONFIG_ARCH_MX25
35#define MXC_GPIO_IRQS (32 * 4) 35#define MXC_GPIO_IRQS (32 * 4)
36#elif defined CONFIG_ARCH_MX51 36#elif defined CONFIG_SOC_IMX51
37#define MXC_GPIO_IRQS (32 * 4) 37#define MXC_GPIO_IRQS (32 * 4)
38#elif defined CONFIG_ARCH_MXC91231 38#elif defined CONFIG_ARCH_MXC91231
39#define MXC_GPIO_IRQS (32 * 4) 39#define MXC_GPIO_IRQS (32 * 4)
diff --git a/arch/arm/plat-mxc/include/mach/mx1.h b/arch/arm/plat-mxc/include/mach/mx1.h
index 75d96214b831..97b19e7800bc 100644
--- a/arch/arm/plat-mxc/include/mach/mx1.h
+++ b/arch/arm/plat-mxc/include/mach/mx1.h
@@ -54,13 +54,13 @@
54#define MX1_AIPI2_BASE_ADDR (0x10000 + MX1_IO_BASE_ADDR) 54#define MX1_AIPI2_BASE_ADDR (0x10000 + MX1_IO_BASE_ADDR)
55#define MX1_SIM_BASE_ADDR (0x11000 + MX1_IO_BASE_ADDR) 55#define MX1_SIM_BASE_ADDR (0x11000 + MX1_IO_BASE_ADDR)
56#define MX1_USBD_BASE_ADDR (0x12000 + MX1_IO_BASE_ADDR) 56#define MX1_USBD_BASE_ADDR (0x12000 + MX1_IO_BASE_ADDR)
57#define MX1_SPI1_BASE_ADDR (0x13000 + MX1_IO_BASE_ADDR) 57#define MX1_CSPI1_BASE_ADDR (0x13000 + MX1_IO_BASE_ADDR)
58#define MX1_MMC_BASE_ADDR (0x14000 + MX1_IO_BASE_ADDR) 58#define MX1_MMC_BASE_ADDR (0x14000 + MX1_IO_BASE_ADDR)
59#define MX1_ASP_BASE_ADDR (0x15000 + MX1_IO_BASE_ADDR) 59#define MX1_ASP_BASE_ADDR (0x15000 + MX1_IO_BASE_ADDR)
60#define MX1_BTA_BASE_ADDR (0x16000 + MX1_IO_BASE_ADDR) 60#define MX1_BTA_BASE_ADDR (0x16000 + MX1_IO_BASE_ADDR)
61#define MX1_I2C_BASE_ADDR (0x17000 + MX1_IO_BASE_ADDR) 61#define MX1_I2C_BASE_ADDR (0x17000 + MX1_IO_BASE_ADDR)
62#define MX1_SSI_BASE_ADDR (0x18000 + MX1_IO_BASE_ADDR) 62#define MX1_SSI_BASE_ADDR (0x18000 + MX1_IO_BASE_ADDR)
63#define MX1_SPI2_BASE_ADDR (0x19000 + MX1_IO_BASE_ADDR) 63#define MX1_CSPI2_BASE_ADDR (0x19000 + MX1_IO_BASE_ADDR)
64#define MX1_MSHC_BASE_ADDR (0x1A000 + MX1_IO_BASE_ADDR) 64#define MX1_MSHC_BASE_ADDR (0x1A000 + MX1_IO_BASE_ADDR)
65#define MX1_CCM_BASE_ADDR (0x1B000 + MX1_IO_BASE_ADDR) 65#define MX1_CCM_BASE_ADDR (0x1B000 + MX1_IO_BASE_ADDR)
66#define MX1_SCM_BASE_ADDR (0x1B804 + MX1_IO_BASE_ADDR) 66#define MX1_SCM_BASE_ADDR (0x1B804 + MX1_IO_BASE_ADDR)
@@ -89,7 +89,7 @@
89#define MX1_GPIO_INT_PORTA 11 89#define MX1_GPIO_INT_PORTA 11
90#define MX1_GPIO_INT_PORTB 12 90#define MX1_GPIO_INT_PORTB 12
91#define MX1_GPIO_INT_PORTC 13 91#define MX1_GPIO_INT_PORTC 13
92#define MX1_LCDC_INT 14 92#define MX1_INT_LCDC 14
93#define MX1_SIM_INT 15 93#define MX1_SIM_INT 15
94#define MX1_SIM_DATA_INT 16 94#define MX1_SIM_DATA_INT 16
95#define MX1_RTC_INT 17 95#define MX1_RTC_INT 17
@@ -112,7 +112,8 @@
112#define MX1_PWM_INT 34 112#define MX1_PWM_INT 34
113#define MX1_SDHC_INT 35 113#define MX1_SDHC_INT 35
114#define MX1_INT_I2C 39 114#define MX1_INT_I2C 39
115#define MX1_CSPI_INT 41 115#define MX1_INT_CSPI2 40
116#define MX1_INT_CSPI1 41
116#define MX1_SSI_TX_INT 42 117#define MX1_SSI_TX_INT 42
117#define MX1_SSI_TX_ERR_INT 43 118#define MX1_SSI_TX_ERR_INT 43
118#define MX1_SSI_RX_INT 44 119#define MX1_SSI_RX_INT 44
diff --git a/arch/arm/plat-mxc/include/mach/mx53.h b/arch/arm/plat-mxc/include/mach/mx53.h
index d7a8e52181ea..ace17864575e 100644
--- a/arch/arm/plat-mxc/include/mach/mx53.h
+++ b/arch/arm/plat-mxc/include/mach/mx53.h
@@ -79,7 +79,7 @@
79#define MX53_GPIO3_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x0008C000) 79#define MX53_GPIO3_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x0008C000)
80#define MX53_GPIO4_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00090000) 80#define MX53_GPIO4_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00090000)
81#define MX53_KPP_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00094000) 81#define MX53_KPP_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00094000)
82#define MX53_WDOG_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00098000) 82#define MX53_WDOG1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00098000)
83#define MX53_WDOG2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x0009C000) 83#define MX53_WDOG2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x0009C000)
84#define MX53_GPT1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A0000) 84#define MX53_GPT1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A0000)
85#define MX53_SRTC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A4000) 85#define MX53_SRTC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A4000)
diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h
index 04c7a26b1f26..7e072637eefa 100644
--- a/arch/arm/plat-mxc/include/mach/mxc.h
+++ b/arch/arm/plat-mxc/include/mach/mxc.h
@@ -103,7 +103,7 @@ extern unsigned int __mxc_cpu_type;
103# define cpu_is_mx27() (0) 103# define cpu_is_mx27() (0)
104#endif 104#endif
105 105
106#ifdef CONFIG_ARCH_MX31 106#ifdef CONFIG_SOC_IMX31
107# ifdef mxc_cpu_type 107# ifdef mxc_cpu_type
108# undef mxc_cpu_type 108# undef mxc_cpu_type
109# define mxc_cpu_type __mxc_cpu_type 109# define mxc_cpu_type __mxc_cpu_type
@@ -115,7 +115,7 @@ extern unsigned int __mxc_cpu_type;
115# define cpu_is_mx31() (0) 115# define cpu_is_mx31() (0)
116#endif 116#endif
117 117
118#ifdef CONFIG_ARCH_MX35 118#ifdef CONFIG_SOC_IMX35
119# ifdef mxc_cpu_type 119# ifdef mxc_cpu_type
120# undef mxc_cpu_type 120# undef mxc_cpu_type
121# define mxc_cpu_type __mxc_cpu_type 121# define mxc_cpu_type __mxc_cpu_type
@@ -127,7 +127,7 @@ extern unsigned int __mxc_cpu_type;
127# define cpu_is_mx35() (0) 127# define cpu_is_mx35() (0)
128#endif 128#endif
129 129
130#ifdef CONFIG_ARCH_MX50 130#ifdef CONFIG_SOC_IMX50
131# ifdef mxc_cpu_type 131# ifdef mxc_cpu_type
132# undef mxc_cpu_type 132# undef mxc_cpu_type
133# define mxc_cpu_type __mxc_cpu_type 133# define mxc_cpu_type __mxc_cpu_type
@@ -139,7 +139,7 @@ extern unsigned int __mxc_cpu_type;
139# define cpu_is_mx50() (0) 139# define cpu_is_mx50() (0)
140#endif 140#endif
141 141
142#ifdef CONFIG_ARCH_MX51 142#ifdef CONFIG_SOC_IMX51
143# ifdef mxc_cpu_type 143# ifdef mxc_cpu_type
144# undef mxc_cpu_type 144# undef mxc_cpu_type
145# define mxc_cpu_type __mxc_cpu_type 145# define mxc_cpu_type __mxc_cpu_type
@@ -151,7 +151,7 @@ extern unsigned int __mxc_cpu_type;
151# define cpu_is_mx51() (0) 151# define cpu_is_mx51() (0)
152#endif 152#endif
153 153
154#ifdef CONFIG_ARCH_MX53 154#ifdef CONFIG_SOC_IMX53
155# ifdef mxc_cpu_type 155# ifdef mxc_cpu_type
156# undef mxc_cpu_type 156# undef mxc_cpu_type
157# define mxc_cpu_type __mxc_cpu_type 157# define mxc_cpu_type __mxc_cpu_type
diff --git a/arch/arm/plat-mxc/include/mach/mxc_ehci.h b/arch/arm/plat-mxc/include/mach/mxc_ehci.h
index a523a4079299..2c159dc2398b 100644
--- a/arch/arm/plat-mxc/include/mach/mxc_ehci.h
+++ b/arch/arm/plat-mxc/include/mach/mxc_ehci.h
@@ -44,11 +44,14 @@ struct mxc_usbh_platform_data {
44 int (*exit)(struct platform_device *pdev); 44 int (*exit)(struct platform_device *pdev);
45 45
46 unsigned int portsc; 46 unsigned int portsc;
47 unsigned int flags;
48 struct otg_transceiver *otg; 47 struct otg_transceiver *otg;
49}; 48};
50 49
51int mxc_initialize_usb_hw(int port, unsigned int flags); 50int mx51_initialize_usb_hw(int port, unsigned int flags);
51int mx25_initialize_usb_hw(int port, unsigned int flags);
52int mx31_initialize_usb_hw(int port, unsigned int flags);
53int mx35_initialize_usb_hw(int port, unsigned int flags);
54int mx27_initialize_usb_hw(int port, unsigned int flags);
52 55
53#endif /* __INCLUDE_ASM_ARCH_MXC_EHCI_H */ 56#endif /* __INCLUDE_ASM_ARCH_MXC_EHCI_H */
54 57
diff --git a/arch/arm/plat-mxc/include/mach/ulpi.h b/arch/arm/plat-mxc/include/mach/ulpi.h
index 96b6ab4c40c3..f9161c96d7bd 100644
--- a/arch/arm/plat-mxc/include/mach/ulpi.h
+++ b/arch/arm/plat-mxc/include/mach/ulpi.h
@@ -1,6 +1,15 @@
1#ifndef __MACH_ULPI_H 1#ifndef __MACH_ULPI_H
2#define __MACH_ULPI_H 2#define __MACH_ULPI_H
3 3
4#ifdef CONFIG_USB_ULPI
5struct otg_transceiver *imx_otg_ulpi_create(unsigned int flags);
6#else
7static inline struct otg_transceiver *imx_otg_ulpi_create(unsigned int flags)
8{
9 return NULL;
10}
11#endif
12
4extern struct otg_io_access_ops mxc_ulpi_access_ops; 13extern struct otg_io_access_ops mxc_ulpi_access_ops;
5 14
6#endif /* __MACH_ULPI_H */ 15#endif /* __MACH_ULPI_H */
diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h
index ff469c4f1d76..4864b0afd440 100644
--- a/arch/arm/plat-mxc/include/mach/uncompress.h
+++ b/arch/arm/plat-mxc/include/mach/uncompress.h
@@ -62,6 +62,7 @@ static inline void flush(void)
62#define MX2X_UART1_BASE_ADDR 0x1000a000 62#define MX2X_UART1_BASE_ADDR 0x1000a000
63#define MX3X_UART1_BASE_ADDR 0x43F90000 63#define MX3X_UART1_BASE_ADDR 0x43F90000
64#define MX3X_UART2_BASE_ADDR 0x43F94000 64#define MX3X_UART2_BASE_ADDR 0x43F94000
65#define MX3X_UART5_BASE_ADDR 0x43FB4000
65#define MX51_UART1_BASE_ADDR 0x73fbc000 66#define MX51_UART1_BASE_ADDR 0x73fbc000
66#define MX50_UART1_BASE_ADDR 0x53fbc000 67#define MX50_UART1_BASE_ADDR 0x53fbc000
67#define MX53_UART1_BASE_ADDR 0x53fbc000 68#define MX53_UART1_BASE_ADDR 0x53fbc000
@@ -83,6 +84,7 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id)
83 case MACH_TYPE_MX21ADS: 84 case MACH_TYPE_MX21ADS:
84 case MACH_TYPE_PCA100: 85 case MACH_TYPE_PCA100:
85 case MACH_TYPE_MXT_TD60: 86 case MACH_TYPE_MXT_TD60:
87 case MACH_TYPE_IMX27IPCAM:
86 uart_base = MX2X_UART1_BASE_ADDR; 88 uart_base = MX2X_UART1_BASE_ADDR;
87 break; 89 break;
88 case MACH_TYPE_MX31LITE: 90 case MACH_TYPE_MX31LITE:
@@ -101,6 +103,9 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id)
101 case MACH_TYPE_MAGX_ZN5: 103 case MACH_TYPE_MAGX_ZN5:
102 uart_base = MX3X_UART2_BASE_ADDR; 104 uart_base = MX3X_UART2_BASE_ADDR;
103 break; 105 break;
106 case MACH_TYPE_BUG:
107 uart_base = MX3X_UART5_BASE_ADDR;
108 break;
104 case MACH_TYPE_MX51_BABBAGE: 109 case MACH_TYPE_MX51_BABBAGE:
105 case MACH_TYPE_EUKREA_CPUIMX51SD: 110 case MACH_TYPE_EUKREA_CPUIMX51SD:
106 case MACH_TYPE_MX51_3DS: 111 case MACH_TYPE_MX51_3DS:
@@ -110,6 +115,8 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id)
110 uart_base = MX50_UART1_BASE_ADDR; 115 uart_base = MX50_UART1_BASE_ADDR;
111 break; 116 break;
112 case MACH_TYPE_MX53_EVK: 117 case MACH_TYPE_MX53_EVK:
118 case MACH_TYPE_MX53_LOCO:
119 case MACH_TYPE_MX53_SMD:
113 uart_base = MX53_UART1_BASE_ADDR; 120 uart_base = MX53_UART1_BASE_ADDR;
114 break; 121 break;
115 default: 122 default:
diff --git a/arch/arm/plat-mxc/iomux-v1.c b/arch/arm/plat-mxc/iomux-v1.c
index 960a02cbcbaf..3238c10d4e02 100644
--- a/arch/arm/plat-mxc/iomux-v1.c
+++ b/arch/arm/plat-mxc/iomux-v1.c
@@ -211,28 +211,10 @@ void mxc_gpio_release_multiple_pins(const int *pin_list, int count)
211} 211}
212EXPORT_SYMBOL(mxc_gpio_release_multiple_pins); 212EXPORT_SYMBOL(mxc_gpio_release_multiple_pins);
213 213
214static int imx_iomuxv1_init(void) 214int __init imx_iomuxv1_init(void __iomem *base, int numports)
215{ 215{
216#ifdef CONFIG_ARCH_MX1 216 imx_iomuxv1_baseaddr = base;
217 if (cpu_is_mx1()) { 217 imx_iomuxv1_numports = numports;
218 imx_iomuxv1_baseaddr = MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR);
219 imx_iomuxv1_numports = MX1_NUM_GPIO_PORT;
220 } else
221#endif
222#ifdef CONFIG_MACH_MX21
223 if (cpu_is_mx21()) {
224 imx_iomuxv1_baseaddr = MX21_IO_ADDRESS(MX21_GPIO_BASE_ADDR);
225 imx_iomuxv1_numports = MX21_NUM_GPIO_PORT;
226 } else
227#endif
228#ifdef CONFIG_MACH_MX27
229 if (cpu_is_mx27()) {
230 imx_iomuxv1_baseaddr = MX27_IO_ADDRESS(MX27_GPIO_BASE_ADDR);
231 imx_iomuxv1_numports = MX27_NUM_GPIO_PORT;
232 } else
233#endif
234 return -ENODEV;
235 218
236 return 0; 219 return 0;
237} 220}
238pure_initcall(imx_iomuxv1_init);
diff --git a/arch/arm/plat-mxc/ulpi.c b/arch/arm/plat-mxc/ulpi.c
index 582c6dfaba4a..477e45bea1be 100644
--- a/arch/arm/plat-mxc/ulpi.c
+++ b/arch/arm/plat-mxc/ulpi.c
@@ -22,6 +22,7 @@
22#include <linux/io.h> 22#include <linux/io.h>
23#include <linux/delay.h> 23#include <linux/delay.h>
24#include <linux/usb/otg.h> 24#include <linux/usb/otg.h>
25#include <linux/usb/ulpi.h>
25 26
26#include <mach/ulpi.h> 27#include <mach/ulpi.h>
27 28
@@ -111,3 +112,7 @@ struct otg_io_access_ops mxc_ulpi_access_ops = {
111}; 112};
112EXPORT_SYMBOL_GPL(mxc_ulpi_access_ops); 113EXPORT_SYMBOL_GPL(mxc_ulpi_access_ops);
113 114
115struct otg_transceiver *imx_otg_ulpi_create(unsigned int flags)
116{
117 return otg_ulpi_create(&mxc_ulpi_access_ops, flags);
118}
diff --git a/arch/arm/plat-nomadik/gpio.c b/arch/arm/plat-nomadik/gpio.c
index 1e88ecb846d1..70620426ee55 100644
--- a/arch/arm/plat-nomadik/gpio.c
+++ b/arch/arm/plat-nomadik/gpio.c
@@ -30,23 +30,39 @@
30/* 30/*
31 * The GPIO module in the Nomadik family of Systems-on-Chip is an 31 * The GPIO module in the Nomadik family of Systems-on-Chip is an
32 * AMBA device, managing 32 pins and alternate functions. The logic block 32 * AMBA device, managing 32 pins and alternate functions. The logic block
33 * is currently only used in the Nomadik. 33 * is currently used in the Nomadik and ux500.
34 * 34 *
35 * Symbols in this file are called "nmk_gpio" for "nomadik gpio" 35 * Symbols in this file are called "nmk_gpio" for "nomadik gpio"
36 */ 36 */
37 37
38#define NMK_GPIO_PER_CHIP 32 38#define NMK_GPIO_PER_CHIP 32
39
39struct nmk_gpio_chip { 40struct nmk_gpio_chip {
40 struct gpio_chip chip; 41 struct gpio_chip chip;
41 void __iomem *addr; 42 void __iomem *addr;
42 struct clk *clk; 43 struct clk *clk;
44 unsigned int bank;
43 unsigned int parent_irq; 45 unsigned int parent_irq;
46 int secondary_parent_irq;
47 u32 (*get_secondary_status)(unsigned int bank);
48 void (*set_ioforce)(bool enable);
44 spinlock_t lock; 49 spinlock_t lock;
45 /* Keep track of configured edges */ 50 /* Keep track of configured edges */
46 u32 edge_rising; 51 u32 edge_rising;
47 u32 edge_falling; 52 u32 edge_falling;
53 u32 real_wake;
54 u32 rwimsc;
55 u32 fwimsc;
56 u32 slpm;
48}; 57};
49 58
59static struct nmk_gpio_chip *
60nmk_gpio_chips[DIV_ROUND_UP(ARCH_NR_GPIOS, NMK_GPIO_PER_CHIP)];
61
62static DEFINE_SPINLOCK(nmk_gpio_slpm_lock);
63
64#define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips)
65
50static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip, 66static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip,
51 unsigned offset, int gpio_mode) 67 unsigned offset, int gpio_mode)
52{ 68{
@@ -118,8 +134,35 @@ static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip,
118 __nmk_gpio_set_output(nmk_chip, offset, val); 134 __nmk_gpio_set_output(nmk_chip, offset, val);
119} 135}
120 136
137static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip,
138 unsigned offset, int gpio_mode,
139 bool glitch)
140{
141 u32 rwimsc = readl(nmk_chip->addr + NMK_GPIO_RWIMSC);
142 u32 fwimsc = readl(nmk_chip->addr + NMK_GPIO_FWIMSC);
143
144 if (glitch && nmk_chip->set_ioforce) {
145 u32 bit = BIT(offset);
146
147 /* Prevent spurious wakeups */
148 writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC);
149 writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC);
150
151 nmk_chip->set_ioforce(true);
152 }
153
154 __nmk_gpio_set_mode(nmk_chip, offset, gpio_mode);
155
156 if (glitch && nmk_chip->set_ioforce) {
157 nmk_chip->set_ioforce(false);
158
159 writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC);
160 writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC);
161 }
162}
163
121static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset, 164static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset,
122 pin_cfg_t cfg, bool sleep) 165 pin_cfg_t cfg, bool sleep, unsigned int *slpmregs)
123{ 166{
124 static const char *afnames[] = { 167 static const char *afnames[] = {
125 [NMK_GPIO_ALT_GPIO] = "GPIO", 168 [NMK_GPIO_ALT_GPIO] = "GPIO",
@@ -144,6 +187,7 @@ static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset,
144 int slpm = PIN_SLPM(cfg); 187 int slpm = PIN_SLPM(cfg);
145 int output = PIN_DIR(cfg); 188 int output = PIN_DIR(cfg);
146 int val = PIN_VAL(cfg); 189 int val = PIN_VAL(cfg);
190 bool glitch = af == NMK_GPIO_ALT_C;
147 191
148 dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: af %s, pull %s, slpm %s (%s%s)\n", 192 dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: af %s, pull %s, slpm %s (%s%s)\n",
149 pin, cfg, afnames[af], pullnames[pull], slpmnames[slpm], 193 pin, cfg, afnames[af], pullnames[pull], slpmnames[slpm],
@@ -155,6 +199,8 @@ static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset,
155 int slpm_output = PIN_SLPM_DIR(cfg); 199 int slpm_output = PIN_SLPM_DIR(cfg);
156 int slpm_val = PIN_SLPM_VAL(cfg); 200 int slpm_val = PIN_SLPM_VAL(cfg);
157 201
202 af = NMK_GPIO_ALT_GPIO;
203
158 /* 204 /*
159 * The SLPM_* values are normal values + 1 to allow zero to 205 * The SLPM_* values are normal values + 1 to allow zero to
160 * mean "same as normal". 206 * mean "same as normal".
@@ -180,8 +226,116 @@ static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset,
180 __nmk_gpio_set_pull(nmk_chip, offset, pull); 226 __nmk_gpio_set_pull(nmk_chip, offset, pull);
181 } 227 }
182 228
183 __nmk_gpio_set_slpm(nmk_chip, offset, slpm); 229 /*
184 __nmk_gpio_set_mode(nmk_chip, offset, af); 230 * If we've backed up the SLPM registers (glitch workaround), modify
231 * the backups since they will be restored.
232 */
233 if (slpmregs) {
234 if (slpm == NMK_GPIO_SLPM_NOCHANGE)
235 slpmregs[nmk_chip->bank] |= BIT(offset);
236 else
237 slpmregs[nmk_chip->bank] &= ~BIT(offset);
238 } else
239 __nmk_gpio_set_slpm(nmk_chip, offset, slpm);
240
241 __nmk_gpio_set_mode_safe(nmk_chip, offset, af, glitch);
242}
243
244/*
245 * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
246 * - Save SLPM registers
247 * - Set SLPM=0 for the IOs you want to switch and others to 1
248 * - Configure the GPIO registers for the IOs that are being switched
249 * - Set IOFORCE=1
250 * - Modify the AFLSA/B registers for the IOs that are being switched
251 * - Set IOFORCE=0
252 * - Restore SLPM registers
253 * - Any spurious wake up event during switch sequence to be ignored and
254 * cleared
255 */
256static void nmk_gpio_glitch_slpm_init(unsigned int *slpm)
257{
258 int i;
259
260 for (i = 0; i < NUM_BANKS; i++) {
261 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
262 unsigned int temp = slpm[i];
263
264 if (!chip)
265 break;
266
267 slpm[i] = readl(chip->addr + NMK_GPIO_SLPC);
268 writel(temp, chip->addr + NMK_GPIO_SLPC);
269 }
270}
271
272static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm)
273{
274 int i;
275
276 for (i = 0; i < NUM_BANKS; i++) {
277 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
278
279 if (!chip)
280 break;
281
282 writel(slpm[i], chip->addr + NMK_GPIO_SLPC);
283 }
284}
285
286static int __nmk_config_pins(pin_cfg_t *cfgs, int num, bool sleep)
287{
288 static unsigned int slpm[NUM_BANKS];
289 unsigned long flags;
290 bool glitch = false;
291 int ret = 0;
292 int i;
293
294 for (i = 0; i < num; i++) {
295 if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C) {
296 glitch = true;
297 break;
298 }
299 }
300
301 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
302
303 if (glitch) {
304 memset(slpm, 0xff, sizeof(slpm));
305
306 for (i = 0; i < num; i++) {
307 int pin = PIN_NUM(cfgs[i]);
308 int offset = pin % NMK_GPIO_PER_CHIP;
309
310 if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C)
311 slpm[pin / NMK_GPIO_PER_CHIP] &= ~BIT(offset);
312 }
313
314 nmk_gpio_glitch_slpm_init(slpm);
315 }
316
317 for (i = 0; i < num; i++) {
318 struct nmk_gpio_chip *nmk_chip;
319 int pin = PIN_NUM(cfgs[i]);
320
321 nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(pin));
322 if (!nmk_chip) {
323 ret = -EINVAL;
324 break;
325 }
326
327 spin_lock(&nmk_chip->lock);
328 __nmk_config_pin(nmk_chip, pin - nmk_chip->chip.base,
329 cfgs[i], sleep, glitch ? slpm : NULL);
330 spin_unlock(&nmk_chip->lock);
331 }
332
333 if (glitch)
334 nmk_gpio_glitch_slpm_restore(slpm);
335
336 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
337
338 return ret;
185} 339}
186 340
187/** 341/**
@@ -200,19 +354,7 @@ static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset,
200 */ 354 */
201int nmk_config_pin(pin_cfg_t cfg, bool sleep) 355int nmk_config_pin(pin_cfg_t cfg, bool sleep)
202{ 356{
203 struct nmk_gpio_chip *nmk_chip; 357 return __nmk_config_pins(&cfg, 1, sleep);
204 int gpio = PIN_NUM(cfg);
205 unsigned long flags;
206
207 nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
208 if (!nmk_chip)
209 return -EINVAL;
210
211 spin_lock_irqsave(&nmk_chip->lock, flags);
212 __nmk_config_pin(nmk_chip, gpio - nmk_chip->chip.base, cfg, sleep);
213 spin_unlock_irqrestore(&nmk_chip->lock, flags);
214
215 return 0;
216} 358}
217EXPORT_SYMBOL(nmk_config_pin); 359EXPORT_SYMBOL(nmk_config_pin);
218 360
@@ -226,31 +368,13 @@ EXPORT_SYMBOL(nmk_config_pin);
226 */ 368 */
227int nmk_config_pins(pin_cfg_t *cfgs, int num) 369int nmk_config_pins(pin_cfg_t *cfgs, int num)
228{ 370{
229 int ret = 0; 371 return __nmk_config_pins(cfgs, num, false);
230 int i;
231
232 for (i = 0; i < num; i++) {
233 ret = nmk_config_pin(cfgs[i], false);
234 if (ret)
235 break;
236 }
237
238 return ret;
239} 372}
240EXPORT_SYMBOL(nmk_config_pins); 373EXPORT_SYMBOL(nmk_config_pins);
241 374
242int nmk_config_pins_sleep(pin_cfg_t *cfgs, int num) 375int nmk_config_pins_sleep(pin_cfg_t *cfgs, int num)
243{ 376{
244 int ret = 0; 377 return __nmk_config_pins(cfgs, num, true);
245 int i;
246
247 for (i = 0; i < num; i++) {
248 ret = nmk_config_pin(cfgs[i], true);
249 if (ret)
250 break;
251 }
252
253 return ret;
254} 378}
255EXPORT_SYMBOL(nmk_config_pins_sleep); 379EXPORT_SYMBOL(nmk_config_pins_sleep);
256 380
@@ -277,9 +401,13 @@ int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode)
277 if (!nmk_chip) 401 if (!nmk_chip)
278 return -EINVAL; 402 return -EINVAL;
279 403
280 spin_lock_irqsave(&nmk_chip->lock, flags); 404 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
405 spin_lock(&nmk_chip->lock);
406
281 __nmk_gpio_set_slpm(nmk_chip, gpio - nmk_chip->chip.base, mode); 407 __nmk_gpio_set_slpm(nmk_chip, gpio - nmk_chip->chip.base, mode);
282 spin_unlock_irqrestore(&nmk_chip->lock, flags); 408
409 spin_unlock(&nmk_chip->lock);
410 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
283 411
284 return 0; 412 return 0;
285} 413}
@@ -314,6 +442,15 @@ int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull)
314} 442}
315 443
316/* Mode functions */ 444/* Mode functions */
445/**
446 * nmk_gpio_set_mode() - set the mux mode of a gpio pin
447 * @gpio: pin number
448 * @gpio_mode: one of NMK_GPIO_ALT_GPIO, NMK_GPIO_ALT_A,
449 * NMK_GPIO_ALT_B, and NMK_GPIO_ALT_C
450 *
451 * Sets the mode of the specified pin to one of the alternate functions or
452 * plain GPIO.
453 */
317int nmk_gpio_set_mode(int gpio, int gpio_mode) 454int nmk_gpio_set_mode(int gpio, int gpio_mode)
318{ 455{
319 struct nmk_gpio_chip *nmk_chip; 456 struct nmk_gpio_chip *nmk_chip;
@@ -401,8 +538,20 @@ static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip,
401 } 538 }
402} 539}
403 540
404static int nmk_gpio_irq_modify(struct irq_data *d, enum nmk_gpio_irq_type which, 541static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip,
405 bool enable) 542 int gpio, bool on)
543{
544#ifdef CONFIG_ARCH_U8500
545 if (cpu_is_u8500v2()) {
546 __nmk_gpio_set_slpm(nmk_chip, gpio - nmk_chip->chip.base,
547 on ? NMK_GPIO_SLPM_WAKEUP_ENABLE
548 : NMK_GPIO_SLPM_WAKEUP_DISABLE);
549 }
550#endif
551 __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on);
552}
553
554static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable)
406{ 555{
407 int gpio; 556 int gpio;
408 struct nmk_gpio_chip *nmk_chip; 557 struct nmk_gpio_chip *nmk_chip;
@@ -415,44 +564,58 @@ static int nmk_gpio_irq_modify(struct irq_data *d, enum nmk_gpio_irq_type which,
415 if (!nmk_chip) 564 if (!nmk_chip)
416 return -EINVAL; 565 return -EINVAL;
417 566
418 spin_lock_irqsave(&nmk_chip->lock, flags); 567 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
419 __nmk_gpio_irq_modify(nmk_chip, gpio, which, enable); 568 spin_lock(&nmk_chip->lock);
420 spin_unlock_irqrestore(&nmk_chip->lock, flags); 569
570 __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, enable);
571
572 if (!(nmk_chip->real_wake & bitmask))
573 __nmk_gpio_set_wake(nmk_chip, gpio, enable);
574
575 spin_unlock(&nmk_chip->lock);
576 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
421 577
422 return 0; 578 return 0;
423} 579}
424 580
425static void nmk_gpio_irq_mask(struct irq_data *d) 581static void nmk_gpio_irq_mask(struct irq_data *d)
426{ 582{
427 nmk_gpio_irq_modify(d, NORMAL, false); 583 nmk_gpio_irq_maskunmask(d, false);
428} 584}
429 585
430static void nmk_gpio_irq_unmask(struct irq_data *d) 586static void nmk_gpio_irq_unmask(struct irq_data *d)
431{ 587{
432 nmk_gpio_irq_modify(d, NORMAL, true); 588 nmk_gpio_irq_maskunmask(d, true);
433} 589}
434 590
435static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on) 591static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
436{ 592{
593 struct irq_desc *desc = irq_to_desc(d->irq);
594 bool enabled = !(desc->status & IRQ_DISABLED);
437 struct nmk_gpio_chip *nmk_chip; 595 struct nmk_gpio_chip *nmk_chip;
438 unsigned long flags; 596 unsigned long flags;
597 u32 bitmask;
439 int gpio; 598 int gpio;
440 599
441 gpio = NOMADIK_IRQ_TO_GPIO(d->irq); 600 gpio = NOMADIK_IRQ_TO_GPIO(d->irq);
442 nmk_chip = irq_data_get_irq_chip_data(d); 601 nmk_chip = irq_data_get_irq_chip_data(d);
443 if (!nmk_chip) 602 if (!nmk_chip)
444 return -EINVAL; 603 return -EINVAL;
604 bitmask = nmk_gpio_get_bitmask(gpio);
445 605
446 spin_lock_irqsave(&nmk_chip->lock, flags); 606 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
447#ifdef CONFIG_ARCH_U8500 607 spin_lock(&nmk_chip->lock);
448 if (cpu_is_u8500v2()) { 608
449 __nmk_gpio_set_slpm(nmk_chip, gpio, 609 if (!enabled)
450 on ? NMK_GPIO_SLPM_WAKEUP_ENABLE 610 __nmk_gpio_set_wake(nmk_chip, gpio, on);
451 : NMK_GPIO_SLPM_WAKEUP_DISABLE); 611
452 } 612 if (on)
453#endif 613 nmk_chip->real_wake |= bitmask;
454 __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on); 614 else
455 spin_unlock_irqrestore(&nmk_chip->lock, flags); 615 nmk_chip->real_wake &= ~bitmask;
616
617 spin_unlock(&nmk_chip->lock);
618 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
456 619
457 return 0; 620 return 0;
458} 621}
@@ -483,7 +646,7 @@ static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type)
483 if (enabled) 646 if (enabled)
484 __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, false); 647 __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, false);
485 648
486 if (wake) 649 if (enabled || wake)
487 __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, false); 650 __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, false);
488 651
489 nmk_chip->edge_rising &= ~bitmask; 652 nmk_chip->edge_rising &= ~bitmask;
@@ -497,7 +660,7 @@ static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type)
497 if (enabled) 660 if (enabled)
498 __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, true); 661 __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, true);
499 662
500 if (wake) 663 if (enabled || wake)
501 __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, true); 664 __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, true);
502 665
503 spin_unlock_irqrestore(&nmk_chip->lock, flags); 666 spin_unlock_irqrestore(&nmk_chip->lock, flags);
@@ -514,12 +677,11 @@ static struct irq_chip nmk_gpio_irq_chip = {
514 .irq_set_wake = nmk_gpio_irq_set_wake, 677 .irq_set_wake = nmk_gpio_irq_set_wake,
515}; 678};
516 679
517static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) 680static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc,
681 u32 status)
518{ 682{
519 struct nmk_gpio_chip *nmk_chip; 683 struct nmk_gpio_chip *nmk_chip;
520 struct irq_chip *host_chip = get_irq_chip(irq); 684 struct irq_chip *host_chip = get_irq_chip(irq);
521 unsigned int gpio_irq;
522 u32 pending;
523 unsigned int first_irq; 685 unsigned int first_irq;
524 686
525 if (host_chip->irq_mask_ack) 687 if (host_chip->irq_mask_ack)
@@ -532,29 +694,56 @@ static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
532 694
533 nmk_chip = get_irq_data(irq); 695 nmk_chip = get_irq_data(irq);
534 first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base); 696 first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base);
535 while ( (pending = readl(nmk_chip->addr + NMK_GPIO_IS)) ) { 697 while (status) {
536 gpio_irq = first_irq + __ffs(pending); 698 int bit = __ffs(status);
537 generic_handle_irq(gpio_irq); 699
700 generic_handle_irq(first_irq + bit);
701 status &= ~BIT(bit);
538 } 702 }
539 703
540 host_chip->irq_unmask(&desc->irq_data); 704 host_chip->irq_unmask(&desc->irq_data);
541} 705}
542 706
707static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
708{
709 struct nmk_gpio_chip *nmk_chip = get_irq_data(irq);
710 u32 status = readl(nmk_chip->addr + NMK_GPIO_IS);
711
712 __nmk_gpio_irq_handler(irq, desc, status);
713}
714
715static void nmk_gpio_secondary_irq_handler(unsigned int irq,
716 struct irq_desc *desc)
717{
718 struct nmk_gpio_chip *nmk_chip = get_irq_data(irq);
719 u32 status = nmk_chip->get_secondary_status(nmk_chip->bank);
720
721 __nmk_gpio_irq_handler(irq, desc, status);
722}
723
543static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip) 724static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip)
544{ 725{
545 unsigned int first_irq; 726 unsigned int first_irq;
546 int i; 727 int i;
547 728
548 first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base); 729 first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base);
549 for (i = first_irq; i < first_irq + NMK_GPIO_PER_CHIP; i++) { 730 for (i = first_irq; i < first_irq + nmk_chip->chip.ngpio; i++) {
550 set_irq_chip(i, &nmk_gpio_irq_chip); 731 set_irq_chip(i, &nmk_gpio_irq_chip);
551 set_irq_handler(i, handle_edge_irq); 732 set_irq_handler(i, handle_edge_irq);
552 set_irq_flags(i, IRQF_VALID); 733 set_irq_flags(i, IRQF_VALID);
553 set_irq_chip_data(i, nmk_chip); 734 set_irq_chip_data(i, nmk_chip);
554 set_irq_type(i, IRQ_TYPE_EDGE_FALLING); 735 set_irq_type(i, IRQ_TYPE_EDGE_FALLING);
555 } 736 }
737
556 set_irq_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler); 738 set_irq_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler);
557 set_irq_data(nmk_chip->parent_irq, nmk_chip); 739 set_irq_data(nmk_chip->parent_irq, nmk_chip);
740
741 if (nmk_chip->secondary_parent_irq >= 0) {
742 set_irq_chained_handler(nmk_chip->secondary_parent_irq,
743 nmk_gpio_secondary_irq_handler);
744 set_irq_data(nmk_chip->secondary_parent_irq, nmk_chip);
745 }
746
558 return 0; 747 return 0;
559} 748}
560 749
@@ -605,6 +794,97 @@ static int nmk_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
605 return NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base) + offset; 794 return NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base) + offset;
606} 795}
607 796
797#ifdef CONFIG_DEBUG_FS
798
799#include <linux/seq_file.h>
800
801static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
802{
803 int mode;
804 unsigned i;
805 unsigned gpio = chip->base;
806 int is_out;
807 struct nmk_gpio_chip *nmk_chip =
808 container_of(chip, struct nmk_gpio_chip, chip);
809 const char *modes[] = {
810 [NMK_GPIO_ALT_GPIO] = "gpio",
811 [NMK_GPIO_ALT_A] = "altA",
812 [NMK_GPIO_ALT_B] = "altB",
813 [NMK_GPIO_ALT_C] = "altC",
814 };
815
816 for (i = 0; i < chip->ngpio; i++, gpio++) {
817 const char *label = gpiochip_is_requested(chip, i);
818 bool pull;
819 u32 bit = 1 << i;
820
821 if (!label)
822 continue;
823
824 is_out = readl(nmk_chip->addr + NMK_GPIO_DIR) & bit;
825 pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit);
826 mode = nmk_gpio_get_mode(gpio);
827 seq_printf(s, " gpio-%-3d (%-20.20s) %s %s %s %s",
828 gpio, label,
829 is_out ? "out" : "in ",
830 chip->get
831 ? (chip->get(chip, i) ? "hi" : "lo")
832 : "? ",
833 (mode < 0) ? "unknown" : modes[mode],
834 pull ? "pull" : "none");
835
836 if (!is_out) {
837 int irq = gpio_to_irq(gpio);
838 struct irq_desc *desc = irq_to_desc(irq);
839
840 /* This races with request_irq(), set_irq_type(),
841 * and set_irq_wake() ... but those are "rare".
842 *
843 * More significantly, trigger type flags aren't
844 * currently maintained by genirq.
845 */
846 if (irq >= 0 && desc->action) {
847 char *trigger;
848
849 switch (desc->status & IRQ_TYPE_SENSE_MASK) {
850 case IRQ_TYPE_NONE:
851 trigger = "(default)";
852 break;
853 case IRQ_TYPE_EDGE_FALLING:
854 trigger = "edge-falling";
855 break;
856 case IRQ_TYPE_EDGE_RISING:
857 trigger = "edge-rising";
858 break;
859 case IRQ_TYPE_EDGE_BOTH:
860 trigger = "edge-both";
861 break;
862 case IRQ_TYPE_LEVEL_HIGH:
863 trigger = "level-high";
864 break;
865 case IRQ_TYPE_LEVEL_LOW:
866 trigger = "level-low";
867 break;
868 default:
869 trigger = "?trigger?";
870 break;
871 }
872
873 seq_printf(s, " irq-%d %s%s",
874 irq, trigger,
875 (desc->status & IRQ_WAKEUP)
876 ? " wakeup" : "");
877 }
878 }
879
880 seq_printf(s, "\n");
881 }
882}
883
884#else
885#define nmk_gpio_dbg_show NULL
886#endif
887
608/* This structure is replicated for each GPIO block allocated at probe time */ 888/* This structure is replicated for each GPIO block allocated at probe time */
609static struct gpio_chip nmk_gpio_template = { 889static struct gpio_chip nmk_gpio_template = {
610 .direction_input = nmk_gpio_make_input, 890 .direction_input = nmk_gpio_make_input,
@@ -612,10 +892,64 @@ static struct gpio_chip nmk_gpio_template = {
612 .direction_output = nmk_gpio_make_output, 892 .direction_output = nmk_gpio_make_output,
613 .set = nmk_gpio_set_output, 893 .set = nmk_gpio_set_output,
614 .to_irq = nmk_gpio_to_irq, 894 .to_irq = nmk_gpio_to_irq,
615 .ngpio = NMK_GPIO_PER_CHIP, 895 .dbg_show = nmk_gpio_dbg_show,
616 .can_sleep = 0, 896 .can_sleep = 0,
617}; 897};
618 898
899/*
900 * Called from the suspend/resume path to only keep the real wakeup interrupts
901 * (those that have had set_irq_wake() called on them) as wakeup interrupts,
902 * and not the rest of the interrupts which we needed to have as wakeups for
903 * cpuidle.
904 *
905 * PM ops are not used since this needs to be done at the end, after all the
906 * other drivers are done with their suspend callbacks.
907 */
908void nmk_gpio_wakeups_suspend(void)
909{
910 int i;
911
912 for (i = 0; i < NUM_BANKS; i++) {
913 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
914
915 if (!chip)
916 break;
917
918 chip->rwimsc = readl(chip->addr + NMK_GPIO_RWIMSC);
919 chip->fwimsc = readl(chip->addr + NMK_GPIO_FWIMSC);
920
921 writel(chip->rwimsc & chip->real_wake,
922 chip->addr + NMK_GPIO_RWIMSC);
923 writel(chip->fwimsc & chip->real_wake,
924 chip->addr + NMK_GPIO_FWIMSC);
925
926 if (cpu_is_u8500v2()) {
927 chip->slpm = readl(chip->addr + NMK_GPIO_SLPC);
928
929 /* 0 -> wakeup enable */
930 writel(~chip->real_wake, chip->addr + NMK_GPIO_SLPC);
931 }
932 }
933}
934
935void nmk_gpio_wakeups_resume(void)
936{
937 int i;
938
939 for (i = 0; i < NUM_BANKS; i++) {
940 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
941
942 if (!chip)
943 break;
944
945 writel(chip->rwimsc, chip->addr + NMK_GPIO_RWIMSC);
946 writel(chip->fwimsc, chip->addr + NMK_GPIO_FWIMSC);
947
948 if (cpu_is_u8500v2())
949 writel(chip->slpm, chip->addr + NMK_GPIO_SLPC);
950 }
951}
952
619static int __devinit nmk_gpio_probe(struct platform_device *dev) 953static int __devinit nmk_gpio_probe(struct platform_device *dev)
620{ 954{
621 struct nmk_gpio_platform_data *pdata = dev->dev.platform_data; 955 struct nmk_gpio_platform_data *pdata = dev->dev.platform_data;
@@ -623,6 +957,7 @@ static int __devinit nmk_gpio_probe(struct platform_device *dev)
623 struct gpio_chip *chip; 957 struct gpio_chip *chip;
624 struct resource *res; 958 struct resource *res;
625 struct clk *clk; 959 struct clk *clk;
960 int secondary_irq;
626 int irq; 961 int irq;
627 int ret; 962 int ret;
628 963
@@ -641,6 +976,12 @@ static int __devinit nmk_gpio_probe(struct platform_device *dev)
641 goto out; 976 goto out;
642 } 977 }
643 978
979 secondary_irq = platform_get_irq(dev, 1);
980 if (secondary_irq >= 0 && !pdata->get_secondary_status) {
981 ret = -EINVAL;
982 goto out;
983 }
984
644 if (request_mem_region(res->start, resource_size(res), 985 if (request_mem_region(res->start, resource_size(res),
645 dev_name(&dev->dev)) == NULL) { 986 dev_name(&dev->dev)) == NULL) {
646 ret = -EBUSY; 987 ret = -EBUSY;
@@ -664,14 +1005,19 @@ static int __devinit nmk_gpio_probe(struct platform_device *dev)
664 * The virt address in nmk_chip->addr is in the nomadik register space, 1005 * The virt address in nmk_chip->addr is in the nomadik register space,
665 * so we can simply convert the resource address, without remapping 1006 * so we can simply convert the resource address, without remapping
666 */ 1007 */
1008 nmk_chip->bank = dev->id;
667 nmk_chip->clk = clk; 1009 nmk_chip->clk = clk;
668 nmk_chip->addr = io_p2v(res->start); 1010 nmk_chip->addr = io_p2v(res->start);
669 nmk_chip->chip = nmk_gpio_template; 1011 nmk_chip->chip = nmk_gpio_template;
670 nmk_chip->parent_irq = irq; 1012 nmk_chip->parent_irq = irq;
1013 nmk_chip->secondary_parent_irq = secondary_irq;
1014 nmk_chip->get_secondary_status = pdata->get_secondary_status;
1015 nmk_chip->set_ioforce = pdata->set_ioforce;
671 spin_lock_init(&nmk_chip->lock); 1016 spin_lock_init(&nmk_chip->lock);
672 1017
673 chip = &nmk_chip->chip; 1018 chip = &nmk_chip->chip;
674 chip->base = pdata->first_gpio; 1019 chip->base = pdata->first_gpio;
1020 chip->ngpio = pdata->num_gpio;
675 chip->label = pdata->name ?: dev_name(&dev->dev); 1021 chip->label = pdata->name ?: dev_name(&dev->dev);
676 chip->dev = &dev->dev; 1022 chip->dev = &dev->dev;
677 chip->owner = THIS_MODULE; 1023 chip->owner = THIS_MODULE;
@@ -680,6 +1026,9 @@ static int __devinit nmk_gpio_probe(struct platform_device *dev)
680 if (ret) 1026 if (ret)
681 goto out_free; 1027 goto out_free;
682 1028
1029 BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips));
1030
1031 nmk_gpio_chips[nmk_chip->bank] = nmk_chip;
683 platform_set_drvdata(dev, nmk_chip); 1032 platform_set_drvdata(dev, nmk_chip);
684 1033
685 nmk_gpio_init_irq(nmk_chip); 1034 nmk_gpio_init_irq(nmk_chip);
@@ -705,10 +1054,8 @@ static struct platform_driver nmk_gpio_driver = {
705 .driver = { 1054 .driver = {
706 .owner = THIS_MODULE, 1055 .owner = THIS_MODULE,
707 .name = "gpio", 1056 .name = "gpio",
708 }, 1057 },
709 .probe = nmk_gpio_probe, 1058 .probe = nmk_gpio_probe,
710 .suspend = NULL, /* to be done */
711 .resume = NULL,
712}; 1059};
713 1060
714static int __init nmk_gpio_init(void) 1061static int __init nmk_gpio_init(void)
diff --git a/arch/arm/plat-nomadik/include/plat/gpio.h b/arch/arm/plat-nomadik/include/plat/gpio.h
index 67b113d639d8..1b9f6f0843d1 100644
--- a/arch/arm/plat-nomadik/include/plat/gpio.h
+++ b/arch/arm/plat-nomadik/include/plat/gpio.h
@@ -75,6 +75,9 @@ extern int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull);
75extern int nmk_gpio_set_mode(int gpio, int gpio_mode); 75extern int nmk_gpio_set_mode(int gpio, int gpio_mode);
76extern int nmk_gpio_get_mode(int gpio); 76extern int nmk_gpio_get_mode(int gpio);
77 77
78extern void nmk_gpio_wakeups_suspend(void);
79extern void nmk_gpio_wakeups_resume(void);
80
78/* 81/*
79 * Platform data to register a block: only the initial gpio/irq number. 82 * Platform data to register a block: only the initial gpio/irq number.
80 */ 83 */
@@ -82,6 +85,9 @@ struct nmk_gpio_platform_data {
82 char *name; 85 char *name;
83 int first_gpio; 86 int first_gpio;
84 int first_irq; 87 int first_irq;
88 int num_gpio;
89 u32 (*get_secondary_status)(unsigned int bank);
90 void (*set_ioforce)(bool enable);
85}; 91};
86 92
87#endif /* __ASM_PLAT_GPIO_H */ 93#endif /* __ASM_PLAT_GPIO_H */
diff --git a/arch/arm/plat-orion/gpio.c b/arch/arm/plat-orion/gpio.c
index 5f3522314815..078894bc3b9a 100644
--- a/arch/arm/plat-orion/gpio.c
+++ b/arch/arm/plat-orion/gpio.c
@@ -17,55 +17,123 @@
17#include <linux/io.h> 17#include <linux/io.h>
18#include <linux/gpio.h> 18#include <linux/gpio.h>
19 19
20static DEFINE_SPINLOCK(gpio_lock); 20/*
21static unsigned long gpio_valid_input[BITS_TO_LONGS(GPIO_MAX)]; 21 * GPIO unit register offsets.
22static unsigned long gpio_valid_output[BITS_TO_LONGS(GPIO_MAX)]; 22 */
23#define GPIO_OUT_OFF 0x0000
24#define GPIO_IO_CONF_OFF 0x0004
25#define GPIO_BLINK_EN_OFF 0x0008
26#define GPIO_IN_POL_OFF 0x000c
27#define GPIO_DATA_IN_OFF 0x0010
28#define GPIO_EDGE_CAUSE_OFF 0x0014
29#define GPIO_EDGE_MASK_OFF 0x0018
30#define GPIO_LEVEL_MASK_OFF 0x001c
31
32struct orion_gpio_chip {
33 struct gpio_chip chip;
34 spinlock_t lock;
35 void __iomem *base;
36 unsigned long valid_input;
37 unsigned long valid_output;
38 int mask_offset;
39 int secondary_irq_base;
40};
41
42static void __iomem *GPIO_OUT(struct orion_gpio_chip *ochip)
43{
44 return ochip->base + GPIO_OUT_OFF;
45}
46
47static void __iomem *GPIO_IO_CONF(struct orion_gpio_chip *ochip)
48{
49 return ochip->base + GPIO_IO_CONF_OFF;
50}
51
52static void __iomem *GPIO_BLINK_EN(struct orion_gpio_chip *ochip)
53{
54 return ochip->base + GPIO_BLINK_EN_OFF;
55}
56
57static void __iomem *GPIO_IN_POL(struct orion_gpio_chip *ochip)
58{
59 return ochip->base + GPIO_IN_POL_OFF;
60}
61
62static void __iomem *GPIO_DATA_IN(struct orion_gpio_chip *ochip)
63{
64 return ochip->base + GPIO_DATA_IN_OFF;
65}
66
67static void __iomem *GPIO_EDGE_CAUSE(struct orion_gpio_chip *ochip)
68{
69 return ochip->base + GPIO_EDGE_CAUSE_OFF;
70}
71
72static void __iomem *GPIO_EDGE_MASK(struct orion_gpio_chip *ochip)
73{
74 return ochip->base + ochip->mask_offset + GPIO_EDGE_MASK_OFF;
75}
76
77static void __iomem *GPIO_LEVEL_MASK(struct orion_gpio_chip *ochip)
78{
79 return ochip->base + ochip->mask_offset + GPIO_LEVEL_MASK_OFF;
80}
81
23 82
24static inline void __set_direction(unsigned pin, int input) 83static struct orion_gpio_chip orion_gpio_chips[2];
84static int orion_gpio_chip_count;
85
86static inline void
87__set_direction(struct orion_gpio_chip *ochip, unsigned pin, int input)
25{ 88{
26 u32 u; 89 u32 u;
27 90
28 u = readl(GPIO_IO_CONF(pin)); 91 u = readl(GPIO_IO_CONF(ochip));
29 if (input) 92 if (input)
30 u |= 1 << (pin & 31); 93 u |= 1 << pin;
31 else 94 else
32 u &= ~(1 << (pin & 31)); 95 u &= ~(1 << pin);
33 writel(u, GPIO_IO_CONF(pin)); 96 writel(u, GPIO_IO_CONF(ochip));
34} 97}
35 98
36static void __set_level(unsigned pin, int high) 99static void __set_level(struct orion_gpio_chip *ochip, unsigned pin, int high)
37{ 100{
38 u32 u; 101 u32 u;
39 102
40 u = readl(GPIO_OUT(pin)); 103 u = readl(GPIO_OUT(ochip));
41 if (high) 104 if (high)
42 u |= 1 << (pin & 31); 105 u |= 1 << pin;
43 else 106 else
44 u &= ~(1 << (pin & 31)); 107 u &= ~(1 << pin);
45 writel(u, GPIO_OUT(pin)); 108 writel(u, GPIO_OUT(ochip));
46} 109}
47 110
48static inline void __set_blinking(unsigned pin, int blink) 111static inline void
112__set_blinking(struct orion_gpio_chip *ochip, unsigned pin, int blink)
49{ 113{
50 u32 u; 114 u32 u;
51 115
52 u = readl(GPIO_BLINK_EN(pin)); 116 u = readl(GPIO_BLINK_EN(ochip));
53 if (blink) 117 if (blink)
54 u |= 1 << (pin & 31); 118 u |= 1 << pin;
55 else 119 else
56 u &= ~(1 << (pin & 31)); 120 u &= ~(1 << pin);
57 writel(u, GPIO_BLINK_EN(pin)); 121 writel(u, GPIO_BLINK_EN(ochip));
58} 122}
59 123
60static inline int orion_gpio_is_valid(unsigned pin, int mode) 124static inline int
125orion_gpio_is_valid(struct orion_gpio_chip *ochip, unsigned pin, int mode)
61{ 126{
62 if (pin < GPIO_MAX) { 127 if (pin >= ochip->chip.ngpio)
63 if ((mode & GPIO_INPUT_OK) && !test_bit(pin, gpio_valid_input)) 128 goto err_out;
64 goto err_out; 129
65 if ((mode & GPIO_OUTPUT_OK) && !test_bit(pin, gpio_valid_output)) 130 if ((mode & GPIO_INPUT_OK) && !test_bit(pin, &ochip->valid_input))
66 goto err_out; 131 goto err_out;
67 return true; 132
68 } 133 if ((mode & GPIO_OUTPUT_OK) && !test_bit(pin, &ochip->valid_output))
134 goto err_out;
135
136 return 1;
69 137
70err_out: 138err_out:
71 pr_debug("%s: invalid GPIO %d\n", __func__, pin); 139 pr_debug("%s: invalid GPIO %d\n", __func__, pin);
@@ -75,134 +143,155 @@ err_out:
75/* 143/*
76 * GENERIC_GPIO primitives. 144 * GENERIC_GPIO primitives.
77 */ 145 */
146static int orion_gpio_request(struct gpio_chip *chip, unsigned pin)
147{
148 struct orion_gpio_chip *ochip =
149 container_of(chip, struct orion_gpio_chip, chip);
150
151 if (orion_gpio_is_valid(ochip, pin, GPIO_INPUT_OK) ||
152 orion_gpio_is_valid(ochip, pin, GPIO_OUTPUT_OK))
153 return 0;
154
155 return -EINVAL;
156}
157
78static int orion_gpio_direction_input(struct gpio_chip *chip, unsigned pin) 158static int orion_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
79{ 159{
160 struct orion_gpio_chip *ochip =
161 container_of(chip, struct orion_gpio_chip, chip);
80 unsigned long flags; 162 unsigned long flags;
81 163
82 if (!orion_gpio_is_valid(pin, GPIO_INPUT_OK)) 164 if (!orion_gpio_is_valid(ochip, pin, GPIO_INPUT_OK))
83 return -EINVAL; 165 return -EINVAL;
84 166
85 spin_lock_irqsave(&gpio_lock, flags); 167 spin_lock_irqsave(&ochip->lock, flags);
86 168 __set_direction(ochip, pin, 1);
87 /* Configure GPIO direction. */ 169 spin_unlock_irqrestore(&ochip->lock, flags);
88 __set_direction(pin, 1);
89
90 spin_unlock_irqrestore(&gpio_lock, flags);
91 170
92 return 0; 171 return 0;
93} 172}
94 173
95static int orion_gpio_get_value(struct gpio_chip *chip, unsigned pin) 174static int orion_gpio_get(struct gpio_chip *chip, unsigned pin)
96{ 175{
176 struct orion_gpio_chip *ochip =
177 container_of(chip, struct orion_gpio_chip, chip);
97 int val; 178 int val;
98 179
99 if (readl(GPIO_IO_CONF(pin)) & (1 << (pin & 31))) 180 if (readl(GPIO_IO_CONF(ochip)) & (1 << pin)) {
100 val = readl(GPIO_DATA_IN(pin)) ^ readl(GPIO_IN_POL(pin)); 181 val = readl(GPIO_DATA_IN(ochip)) ^ readl(GPIO_IN_POL(ochip));
101 else 182 } else {
102 val = readl(GPIO_OUT(pin)); 183 val = readl(GPIO_OUT(ochip));
184 }
103 185
104 return (val >> (pin & 31)) & 1; 186 return (val >> pin) & 1;
105} 187}
106 188
107static int orion_gpio_direction_output(struct gpio_chip *chip, unsigned pin, 189static int
108 int value) 190orion_gpio_direction_output(struct gpio_chip *chip, unsigned pin, int value)
109{ 191{
192 struct orion_gpio_chip *ochip =
193 container_of(chip, struct orion_gpio_chip, chip);
110 unsigned long flags; 194 unsigned long flags;
111 195
112 if (!orion_gpio_is_valid(pin, GPIO_OUTPUT_OK)) 196 if (!orion_gpio_is_valid(ochip, pin, GPIO_OUTPUT_OK))
113 return -EINVAL; 197 return -EINVAL;
114 198
115 spin_lock_irqsave(&gpio_lock, flags); 199 spin_lock_irqsave(&ochip->lock, flags);
116 200 __set_blinking(ochip, pin, 0);
117 /* Disable blinking. */ 201 __set_level(ochip, pin, value);
118 __set_blinking(pin, 0); 202 __set_direction(ochip, pin, 0);
119 203 spin_unlock_irqrestore(&ochip->lock, flags);
120 /* Configure GPIO output value. */
121 __set_level(pin, value);
122
123 /* Configure GPIO direction. */
124 __set_direction(pin, 0);
125
126 spin_unlock_irqrestore(&gpio_lock, flags);
127 204
128 return 0; 205 return 0;
129} 206}
130 207
131static void orion_gpio_set_value(struct gpio_chip *chip, unsigned pin, 208static void orion_gpio_set(struct gpio_chip *chip, unsigned pin, int value)
132 int value)
133{ 209{
210 struct orion_gpio_chip *ochip =
211 container_of(chip, struct orion_gpio_chip, chip);
134 unsigned long flags; 212 unsigned long flags;
135 213
136 spin_lock_irqsave(&gpio_lock, flags); 214 spin_lock_irqsave(&ochip->lock, flags);
137 215 __set_level(ochip, pin, value);
138 /* Configure GPIO output value. */ 216 spin_unlock_irqrestore(&ochip->lock, flags);
139 __set_level(pin, value);
140
141 spin_unlock_irqrestore(&gpio_lock, flags);
142} 217}
143 218
144static int orion_gpio_request(struct gpio_chip *chip, unsigned pin) 219static int orion_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
145{ 220{
146 if (orion_gpio_is_valid(pin, GPIO_INPUT_OK) || 221 struct orion_gpio_chip *ochip =
147 orion_gpio_is_valid(pin, GPIO_OUTPUT_OK)) 222 container_of(chip, struct orion_gpio_chip, chip);
148 return 0;
149 return -EINVAL;
150}
151 223
152static struct gpio_chip orion_gpiochip = { 224 return ochip->secondary_irq_base + pin;
153 .label = "orion_gpio",
154 .direction_input = orion_gpio_direction_input,
155 .get = orion_gpio_get_value,
156 .direction_output = orion_gpio_direction_output,
157 .set = orion_gpio_set_value,
158 .request = orion_gpio_request,
159 .base = 0,
160 .ngpio = GPIO_MAX,
161 .can_sleep = 0,
162};
163
164void __init orion_gpio_init(void)
165{
166 gpiochip_add(&orion_gpiochip);
167} 225}
168 226
227
169/* 228/*
170 * Orion-specific GPIO API extensions. 229 * Orion-specific GPIO API extensions.
171 */ 230 */
231static struct orion_gpio_chip *orion_gpio_chip_find(int pin)
232{
233 int i;
234
235 for (i = 0; i < orion_gpio_chip_count; i++) {
236 struct orion_gpio_chip *ochip = orion_gpio_chips + i;
237 struct gpio_chip *chip = &ochip->chip;
238
239 if (pin >= chip->base && pin < chip->base + chip->ngpio)
240 return ochip;
241 }
242
243 return NULL;
244}
245
172void __init orion_gpio_set_unused(unsigned pin) 246void __init orion_gpio_set_unused(unsigned pin)
173{ 247{
248 struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin);
249
250 if (ochip == NULL)
251 return;
252
253 pin -= ochip->chip.base;
254
174 /* Configure as output, drive low. */ 255 /* Configure as output, drive low. */
175 __set_level(pin, 0); 256 __set_level(ochip, pin, 0);
176 __set_direction(pin, 0); 257 __set_direction(ochip, pin, 0);
177} 258}
178 259
179void __init orion_gpio_set_valid(unsigned pin, int mode) 260void __init orion_gpio_set_valid(unsigned pin, int mode)
180{ 261{
262 struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin);
263
264 if (ochip == NULL)
265 return;
266
267 pin -= ochip->chip.base;
268
181 if (mode == 1) 269 if (mode == 1)
182 mode = GPIO_INPUT_OK | GPIO_OUTPUT_OK; 270 mode = GPIO_INPUT_OK | GPIO_OUTPUT_OK;
271
183 if (mode & GPIO_INPUT_OK) 272 if (mode & GPIO_INPUT_OK)
184 __set_bit(pin, gpio_valid_input); 273 __set_bit(pin, &ochip->valid_input);
185 else 274 else
186 __clear_bit(pin, gpio_valid_input); 275 __clear_bit(pin, &ochip->valid_input);
276
187 if (mode & GPIO_OUTPUT_OK) 277 if (mode & GPIO_OUTPUT_OK)
188 __set_bit(pin, gpio_valid_output); 278 __set_bit(pin, &ochip->valid_output);
189 else 279 else
190 __clear_bit(pin, gpio_valid_output); 280 __clear_bit(pin, &ochip->valid_output);
191} 281}
192 282
193void orion_gpio_set_blink(unsigned pin, int blink) 283void orion_gpio_set_blink(unsigned pin, int blink)
194{ 284{
285 struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin);
195 unsigned long flags; 286 unsigned long flags;
196 287
197 spin_lock_irqsave(&gpio_lock, flags); 288 if (ochip == NULL)
289 return;
198 290
199 /* Set output value to zero. */ 291 spin_lock_irqsave(&ochip->lock, flags);
200 __set_level(pin, 0); 292 __set_level(ochip, pin, 0);
201 293 __set_blinking(ochip, pin, blink);
202 /* Set blinking. */ 294 spin_unlock_irqrestore(&ochip->lock, flags);
203 __set_blinking(pin, blink);
204
205 spin_unlock_irqrestore(&gpio_lock, flags);
206} 295}
207EXPORT_SYMBOL(orion_gpio_set_blink); 296EXPORT_SYMBOL(orion_gpio_set_blink);
208 297
@@ -234,59 +323,78 @@ EXPORT_SYMBOL(orion_gpio_set_blink);
234 ****************************************************************************/ 323 ****************************************************************************/
235static void gpio_irq_ack(struct irq_data *d) 324static void gpio_irq_ack(struct irq_data *d)
236{ 325{
237 int type = irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK; 326 struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d);
327 int type;
328
329 type = irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK;
238 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { 330 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
239 int pin = irq_to_gpio(d->irq); 331 int pin = d->irq - ochip->secondary_irq_base;
240 writel(~(1 << (pin & 31)), GPIO_EDGE_CAUSE(pin)); 332
333 writel(~(1 << pin), GPIO_EDGE_CAUSE(ochip));
241 } 334 }
242} 335}
243 336
244static void gpio_irq_mask(struct irq_data *d) 337static void gpio_irq_mask(struct irq_data *d)
245{ 338{
246 int pin = irq_to_gpio(d->irq); 339 struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d);
247 int type = irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK; 340 int type;
248 u32 reg = (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) ? 341 void __iomem *reg;
249 GPIO_EDGE_MASK(pin) : GPIO_LEVEL_MASK(pin); 342 int pin;
250 u32 u = readl(reg); 343
251 u &= ~(1 << (pin & 31)); 344 type = irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK;
252 writel(u, reg); 345 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
346 reg = GPIO_EDGE_MASK(ochip);
347 else
348 reg = GPIO_LEVEL_MASK(ochip);
349
350 pin = d->irq - ochip->secondary_irq_base;
351
352 writel(readl(reg) & ~(1 << pin), reg);
253} 353}
254 354
255static void gpio_irq_unmask(struct irq_data *d) 355static void gpio_irq_unmask(struct irq_data *d)
256{ 356{
257 int pin = irq_to_gpio(d->irq); 357 struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d);
258 int type = irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK; 358 int type;
259 u32 reg = (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) ? 359 void __iomem *reg;
260 GPIO_EDGE_MASK(pin) : GPIO_LEVEL_MASK(pin); 360 int pin;
261 u32 u = readl(reg); 361
262 u |= 1 << (pin & 31); 362 type = irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK;
263 writel(u, reg); 363 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
364 reg = GPIO_EDGE_MASK(ochip);
365 else
366 reg = GPIO_LEVEL_MASK(ochip);
367
368 pin = d->irq - ochip->secondary_irq_base;
369
370 writel(readl(reg) | (1 << pin), reg);
264} 371}
265 372
266static int gpio_irq_set_type(struct irq_data *d, u32 type) 373static int gpio_irq_set_type(struct irq_data *d, u32 type)
267{ 374{
268 int pin = irq_to_gpio(d->irq); 375 struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d);
269 struct irq_desc *desc; 376 int pin;
270 u32 u; 377 u32 u;
271 378
272 u = readl(GPIO_IO_CONF(pin)) & (1 << (pin & 31)); 379 pin = d->irq - ochip->secondary_irq_base;
380
381 u = readl(GPIO_IO_CONF(ochip)) & (1 << pin);
273 if (!u) { 382 if (!u) {
274 printk(KERN_ERR "orion gpio_irq_set_type failed " 383 printk(KERN_ERR "orion gpio_irq_set_type failed "
275 "(irq %d, pin %d).\n", d->irq, pin); 384 "(irq %d, pin %d).\n", d->irq, pin);
276 return -EINVAL; 385 return -EINVAL;
277 } 386 }
278 387
279 desc = irq_desc + d->irq;
280
281 /* 388 /*
282 * Set edge/level type. 389 * Set edge/level type.
283 */ 390 */
284 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { 391 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
285 desc->handle_irq = handle_edge_irq; 392 set_irq_handler(d->irq, handle_edge_irq);
286 } else if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { 393 } else if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
287 desc->handle_irq = handle_level_irq; 394 set_irq_handler(d->irq, handle_level_irq);
288 } else { 395 } else {
289 printk(KERN_ERR "failed to set irq=%d (type=%d)\n", d->irq, type); 396 printk(KERN_ERR "failed to set irq=%d (type=%d)\n",
397 d->irq, type);
290 return -EINVAL; 398 return -EINVAL;
291 } 399 }
292 400
@@ -294,31 +402,29 @@ static int gpio_irq_set_type(struct irq_data *d, u32 type)
294 * Configure interrupt polarity. 402 * Configure interrupt polarity.
295 */ 403 */
296 if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH) { 404 if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH) {
297 u = readl(GPIO_IN_POL(pin)); 405 u = readl(GPIO_IN_POL(ochip));
298 u &= ~(1 << (pin & 31)); 406 u &= ~(1 << pin);
299 writel(u, GPIO_IN_POL(pin)); 407 writel(u, GPIO_IN_POL(ochip));
300 } else if (type == IRQ_TYPE_EDGE_FALLING || type == IRQ_TYPE_LEVEL_LOW) { 408 } else if (type == IRQ_TYPE_EDGE_FALLING || type == IRQ_TYPE_LEVEL_LOW) {
301 u = readl(GPIO_IN_POL(pin)); 409 u = readl(GPIO_IN_POL(ochip));
302 u |= 1 << (pin & 31); 410 u |= 1 << pin;
303 writel(u, GPIO_IN_POL(pin)); 411 writel(u, GPIO_IN_POL(ochip));
304 } else if (type == IRQ_TYPE_EDGE_BOTH) { 412 } else if (type == IRQ_TYPE_EDGE_BOTH) {
305 u32 v; 413 u32 v;
306 414
307 v = readl(GPIO_IN_POL(pin)) ^ readl(GPIO_DATA_IN(pin)); 415 v = readl(GPIO_IN_POL(ochip)) ^ readl(GPIO_DATA_IN(ochip));
308 416
309 /* 417 /*
310 * set initial polarity based on current input level 418 * set initial polarity based on current input level
311 */ 419 */
312 u = readl(GPIO_IN_POL(pin)); 420 u = readl(GPIO_IN_POL(ochip));
313 if (v & (1 << (pin & 31))) 421 if (v & (1 << pin))
314 u |= 1 << (pin & 31); /* falling */ 422 u |= 1 << pin; /* falling */
315 else 423 else
316 u &= ~(1 << (pin & 31)); /* rising */ 424 u &= ~(1 << pin); /* rising */
317 writel(u, GPIO_IN_POL(pin)); 425 writel(u, GPIO_IN_POL(ochip));
318 } 426 }
319 427
320 desc->status = (desc->status & ~IRQ_TYPE_SENSE_MASK) | type;
321
322 return 0; 428 return 0;
323} 429}
324 430
@@ -330,29 +436,87 @@ struct irq_chip orion_gpio_irq_chip = {
330 .irq_set_type = gpio_irq_set_type, 436 .irq_set_type = gpio_irq_set_type,
331}; 437};
332 438
439void __init orion_gpio_init(int gpio_base, int ngpio,
440 u32 base, int mask_offset, int secondary_irq_base)
441{
442 struct orion_gpio_chip *ochip;
443 int i;
444
445 if (orion_gpio_chip_count == ARRAY_SIZE(orion_gpio_chips))
446 return;
447
448 ochip = orion_gpio_chips + orion_gpio_chip_count;
449 ochip->chip.label = "orion_gpio";
450 ochip->chip.request = orion_gpio_request;
451 ochip->chip.direction_input = orion_gpio_direction_input;
452 ochip->chip.get = orion_gpio_get;
453 ochip->chip.direction_output = orion_gpio_direction_output;
454 ochip->chip.set = orion_gpio_set;
455 ochip->chip.to_irq = orion_gpio_to_irq;
456 ochip->chip.base = gpio_base;
457 ochip->chip.ngpio = ngpio;
458 ochip->chip.can_sleep = 0;
459 spin_lock_init(&ochip->lock);
460 ochip->base = (void __iomem *)base;
461 ochip->valid_input = 0;
462 ochip->valid_output = 0;
463 ochip->mask_offset = mask_offset;
464 ochip->secondary_irq_base = secondary_irq_base;
465
466 gpiochip_add(&ochip->chip);
467
468 orion_gpio_chip_count++;
469
470 /*
471 * Mask and clear GPIO interrupts.
472 */
473 writel(0, GPIO_EDGE_CAUSE(ochip));
474 writel(0, GPIO_EDGE_MASK(ochip));
475 writel(0, GPIO_LEVEL_MASK(ochip));
476
477 for (i = 0; i < ngpio; i++) {
478 unsigned int irq = secondary_irq_base + i;
479
480 set_irq_chip(irq, &orion_gpio_irq_chip);
481 set_irq_handler(irq, handle_level_irq);
482 set_irq_chip_data(irq, ochip);
483 irq_desc[irq].status |= IRQ_LEVEL;
484 set_irq_flags(irq, IRQF_VALID);
485 }
486}
487
333void orion_gpio_irq_handler(int pinoff) 488void orion_gpio_irq_handler(int pinoff)
334{ 489{
490 struct orion_gpio_chip *ochip;
335 u32 cause; 491 u32 cause;
336 int pin; 492 int i;
337 493
338 cause = readl(GPIO_DATA_IN(pinoff)) & readl(GPIO_LEVEL_MASK(pinoff)); 494 ochip = orion_gpio_chip_find(pinoff);
339 cause |= readl(GPIO_EDGE_CAUSE(pinoff)) & readl(GPIO_EDGE_MASK(pinoff)); 495 if (ochip == NULL)
496 return;
340 497
341 for (pin = pinoff; pin < pinoff + 8; pin++) { 498 cause = readl(GPIO_DATA_IN(ochip)) & readl(GPIO_LEVEL_MASK(ochip));
342 int irq = gpio_to_irq(pin); 499 cause |= readl(GPIO_EDGE_CAUSE(ochip)) & readl(GPIO_EDGE_MASK(ochip));
343 struct irq_desc *desc = irq_desc + irq;
344 500
345 if (!(cause & (1 << (pin & 31)))) 501 for (i = 0; i < ochip->chip.ngpio; i++) {
502 int irq;
503 struct irq_desc *desc;
504
505 irq = ochip->secondary_irq_base + i;
506
507 if (!(cause & (1 << i)))
346 continue; 508 continue;
347 509
510 desc = irq_desc + irq;
348 if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { 511 if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
349 /* Swap polarity (race with GPIO line) */ 512 /* Swap polarity (race with GPIO line) */
350 u32 polarity; 513 u32 polarity;
351 514
352 polarity = readl(GPIO_IN_POL(pin)); 515 polarity = readl(GPIO_IN_POL(ochip));
353 polarity ^= 1 << (pin & 31); 516 polarity ^= 1 << i;
354 writel(polarity, GPIO_IN_POL(pin)); 517 writel(polarity, GPIO_IN_POL(ochip));
355 } 518 }
519
356 desc_handle_irq(irq, desc); 520 desc_handle_irq(irq, desc);
357 } 521 }
358} 522}
diff --git a/arch/arm/plat-orion/include/plat/gpio.h b/arch/arm/plat-orion/include/plat/gpio.h
index 07c430fdc9ef..5578b9803fc6 100644
--- a/arch/arm/plat-orion/include/plat/gpio.h
+++ b/arch/arm/plat-orion/include/plat/gpio.h
@@ -12,6 +12,7 @@
12#define __PLAT_GPIO_H 12#define __PLAT_GPIO_H
13 13
14#include <linux/init.h> 14#include <linux/init.h>
15#include <asm-generic/gpio.h>
15 16
16/* 17/*
17 * GENERIC_GPIO primitives. 18 * GENERIC_GPIO primitives.
@@ -19,6 +20,7 @@
19#define gpio_get_value __gpio_get_value 20#define gpio_get_value __gpio_get_value
20#define gpio_set_value __gpio_set_value 21#define gpio_set_value __gpio_set_value
21#define gpio_cansleep __gpio_cansleep 22#define gpio_cansleep __gpio_cansleep
23#define gpio_to_irq __gpio_to_irq
22 24
23/* 25/*
24 * Orion-specific GPIO API extensions. 26 * Orion-specific GPIO API extensions.
@@ -31,7 +33,8 @@ void orion_gpio_set_blink(unsigned pin, int blink);
31void orion_gpio_set_valid(unsigned pin, int mode); 33void orion_gpio_set_valid(unsigned pin, int mode);
32 34
33/* Initialize gpiolib. */ 35/* Initialize gpiolib. */
34void __init orion_gpio_init(void); 36void __init orion_gpio_init(int gpio_base, int ngpio,
37 u32 base, int mask_offset, int secondary_irq_base);
35 38
36/* 39/*
37 * GPIO interrupt handling. 40 * GPIO interrupt handling.
diff --git a/arch/arm/plat-orion/include/plat/time.h b/arch/arm/plat-orion/include/plat/time.h
index c06ca35f3613..4d5f1f6e18df 100644
--- a/arch/arm/plat-orion/include/plat/time.h
+++ b/arch/arm/plat-orion/include/plat/time.h
@@ -11,7 +11,10 @@
11#ifndef __PLAT_TIME_H 11#ifndef __PLAT_TIME_H
12#define __PLAT_TIME_H 12#define __PLAT_TIME_H
13 13
14void orion_time_init(unsigned int irq, unsigned int tclk); 14void orion_time_set_base(u32 timer_base);
15
16void orion_time_init(u32 bridge_base, u32 bridge_timer1_clr_mask,
17 unsigned int irq, unsigned int tclk);
15 18
16 19
17#endif 20#endif
diff --git a/arch/arm/plat-orion/time.c b/arch/arm/plat-orion/time.c
index c3da2478b2aa..742b0323c57b 100644
--- a/arch/arm/plat-orion/time.c
+++ b/arch/arm/plat-orion/time.c
@@ -18,28 +18,42 @@
18#include <linux/interrupt.h> 18#include <linux/interrupt.h>
19#include <linux/irq.h> 19#include <linux/irq.h>
20#include <asm/sched_clock.h> 20#include <asm/sched_clock.h>
21#include <asm/mach/time.h>
22#include <mach/bridge-regs.h>
23#include <mach/hardware.h>
24 21
25/* 22/*
26 * Number of timer ticks per jiffy. 23 * MBus bridge block registers.
27 */ 24 */
28static u32 ticks_per_jiffy; 25#define BRIDGE_CAUSE_OFF 0x0110
26#define BRIDGE_MASK_OFF 0x0114
27#define BRIDGE_INT_TIMER0 0x0002
28#define BRIDGE_INT_TIMER1 0x0004
29 29
30 30
31/* 31/*
32 * Timer block registers. 32 * Timer block registers.
33 */ 33 */
34#define TIMER_CTRL (TIMER_VIRT_BASE + 0x0000) 34#define TIMER_CTRL_OFF 0x0000
35#define TIMER0_EN 0x0001 35#define TIMER0_EN 0x0001
36#define TIMER0_RELOAD_EN 0x0002 36#define TIMER0_RELOAD_EN 0x0002
37#define TIMER1_EN 0x0004 37#define TIMER1_EN 0x0004
38#define TIMER1_RELOAD_EN 0x0008 38#define TIMER1_RELOAD_EN 0x0008
39#define TIMER0_RELOAD (TIMER_VIRT_BASE + 0x0010) 39#define TIMER0_RELOAD_OFF 0x0010
40#define TIMER0_VAL (TIMER_VIRT_BASE + 0x0014) 40#define TIMER0_VAL_OFF 0x0014
41#define TIMER1_RELOAD (TIMER_VIRT_BASE + 0x0018) 41#define TIMER1_RELOAD_OFF 0x0018
42#define TIMER1_VAL (TIMER_VIRT_BASE + 0x001c) 42#define TIMER1_VAL_OFF 0x001c
43
44
45/*
46 * SoC-specific data.
47 */
48static void __iomem *bridge_base;
49static u32 bridge_timer1_clr_mask;
50static void __iomem *timer_base;
51
52
53/*
54 * Number of timer ticks per jiffy.
55 */
56static u32 ticks_per_jiffy;
43 57
44 58
45/* 59/*
@@ -50,14 +64,14 @@ static DEFINE_CLOCK_DATA(cd);
50 64
51unsigned long long notrace sched_clock(void) 65unsigned long long notrace sched_clock(void)
52{ 66{
53 u32 cyc = 0xffffffff - readl(TIMER0_VAL); 67 u32 cyc = ~readl(timer_base + TIMER0_VAL_OFF);
54 return cyc_to_sched_clock(&cd, cyc, (u32)~0); 68 return cyc_to_sched_clock(&cd, cyc, (u32)~0);
55} 69}
56 70
57 71
58static void notrace orion_update_sched_clock(void) 72static void notrace orion_update_sched_clock(void)
59{ 73{
60 u32 cyc = 0xffffffff - readl(TIMER0_VAL); 74 u32 cyc = ~readl(timer_base + TIMER0_VAL_OFF);
61 update_sched_clock(&cd, cyc, (u32)~0); 75 update_sched_clock(&cd, cyc, (u32)~0);
62} 76}
63 77
@@ -71,7 +85,7 @@ static void __init setup_sched_clock(unsigned long tclk)
71 */ 85 */
72static cycle_t orion_clksrc_read(struct clocksource *cs) 86static cycle_t orion_clksrc_read(struct clocksource *cs)
73{ 87{
74 return 0xffffffff - readl(TIMER0_VAL); 88 return 0xffffffff - readl(timer_base + TIMER0_VAL_OFF);
75} 89}
76 90
77static struct clocksource orion_clksrc = { 91static struct clocksource orion_clksrc = {
@@ -101,23 +115,23 @@ orion_clkevt_next_event(unsigned long delta, struct clock_event_device *dev)
101 /* 115 /*
102 * Clear and enable clockevent timer interrupt. 116 * Clear and enable clockevent timer interrupt.
103 */ 117 */
104 writel(BRIDGE_INT_TIMER1_CLR, BRIDGE_CAUSE); 118 writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF);
105 119
106 u = readl(BRIDGE_MASK); 120 u = readl(bridge_base + BRIDGE_MASK_OFF);
107 u |= BRIDGE_INT_TIMER1; 121 u |= BRIDGE_INT_TIMER1;
108 writel(u, BRIDGE_MASK); 122 writel(u, bridge_base + BRIDGE_MASK_OFF);
109 123
110 /* 124 /*
111 * Setup new clockevent timer value. 125 * Setup new clockevent timer value.
112 */ 126 */
113 writel(delta, TIMER1_VAL); 127 writel(delta, timer_base + TIMER1_VAL_OFF);
114 128
115 /* 129 /*
116 * Enable the timer. 130 * Enable the timer.
117 */ 131 */
118 u = readl(TIMER_CTRL); 132 u = readl(timer_base + TIMER_CTRL_OFF);
119 u = (u & ~TIMER1_RELOAD_EN) | TIMER1_EN; 133 u = (u & ~TIMER1_RELOAD_EN) | TIMER1_EN;
120 writel(u, TIMER_CTRL); 134 writel(u, timer_base + TIMER_CTRL_OFF);
121 135
122 local_irq_restore(flags); 136 local_irq_restore(flags);
123 137
@@ -135,37 +149,38 @@ orion_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev)
135 /* 149 /*
136 * Setup timer to fire at 1/HZ intervals. 150 * Setup timer to fire at 1/HZ intervals.
137 */ 151 */
138 writel(ticks_per_jiffy - 1, TIMER1_RELOAD); 152 writel(ticks_per_jiffy - 1, timer_base + TIMER1_RELOAD_OFF);
139 writel(ticks_per_jiffy - 1, TIMER1_VAL); 153 writel(ticks_per_jiffy - 1, timer_base + TIMER1_VAL_OFF);
140 154
141 /* 155 /*
142 * Enable timer interrupt. 156 * Enable timer interrupt.
143 */ 157 */
144 u = readl(BRIDGE_MASK); 158 u = readl(bridge_base + BRIDGE_MASK_OFF);
145 writel(u | BRIDGE_INT_TIMER1, BRIDGE_MASK); 159 writel(u | BRIDGE_INT_TIMER1, bridge_base + BRIDGE_MASK_OFF);
146 160
147 /* 161 /*
148 * Enable timer. 162 * Enable timer.
149 */ 163 */
150 u = readl(TIMER_CTRL); 164 u = readl(timer_base + TIMER_CTRL_OFF);
151 writel(u | TIMER1_EN | TIMER1_RELOAD_EN, TIMER_CTRL); 165 writel(u | TIMER1_EN | TIMER1_RELOAD_EN,
166 timer_base + TIMER_CTRL_OFF);
152 } else { 167 } else {
153 /* 168 /*
154 * Disable timer. 169 * Disable timer.
155 */ 170 */
156 u = readl(TIMER_CTRL); 171 u = readl(timer_base + TIMER_CTRL_OFF);
157 writel(u & ~TIMER1_EN, TIMER_CTRL); 172 writel(u & ~TIMER1_EN, timer_base + TIMER_CTRL_OFF);
158 173
159 /* 174 /*
160 * Disable timer interrupt. 175 * Disable timer interrupt.
161 */ 176 */
162 u = readl(BRIDGE_MASK); 177 u = readl(bridge_base + BRIDGE_MASK_OFF);
163 writel(u & ~BRIDGE_INT_TIMER1, BRIDGE_MASK); 178 writel(u & ~BRIDGE_INT_TIMER1, bridge_base + BRIDGE_MASK_OFF);
164 179
165 /* 180 /*
166 * ACK pending timer interrupt. 181 * ACK pending timer interrupt.
167 */ 182 */
168 writel(BRIDGE_INT_TIMER1_CLR, BRIDGE_CAUSE); 183 writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF);
169 184
170 } 185 }
171 local_irq_restore(flags); 186 local_irq_restore(flags);
@@ -185,7 +200,7 @@ static irqreturn_t orion_timer_interrupt(int irq, void *dev_id)
185 /* 200 /*
186 * ACK timer interrupt and call event handler. 201 * ACK timer interrupt and call event handler.
187 */ 202 */
188 writel(BRIDGE_INT_TIMER1_CLR, BRIDGE_CAUSE); 203 writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF);
189 orion_clkevt.event_handler(&orion_clkevt); 204 orion_clkevt.event_handler(&orion_clkevt);
190 205
191 return IRQ_HANDLED; 206 return IRQ_HANDLED;
@@ -197,31 +212,45 @@ static struct irqaction orion_timer_irq = {
197 .handler = orion_timer_interrupt 212 .handler = orion_timer_interrupt
198}; 213};
199 214
200void __init orion_time_init(unsigned int irq, unsigned int tclk) 215void __init
216orion_time_set_base(u32 _timer_base)
217{
218 timer_base = (void __iomem *)_timer_base;
219}
220
221void __init
222orion_time_init(u32 _bridge_base, u32 _bridge_timer1_clr_mask,
223 unsigned int irq, unsigned int tclk)
201{ 224{
202 u32 u; 225 u32 u;
203 226
227 /*
228 * Set SoC-specific data.
229 */
230 bridge_base = (void __iomem *)_bridge_base;
231 bridge_timer1_clr_mask = _bridge_timer1_clr_mask;
232
204 ticks_per_jiffy = (tclk + HZ/2) / HZ; 233 ticks_per_jiffy = (tclk + HZ/2) / HZ;
205 234
206 /* 235 /*
207 * Set scale and timer for sched_clock 236 * Set scale and timer for sched_clock.
208 */ 237 */
209 setup_sched_clock(tclk); 238 setup_sched_clock(tclk);
210 239
211 /* 240 /*
212 * Setup free-running clocksource timer (interrupts 241 * Setup free-running clocksource timer (interrupts
213 * disabled.) 242 * disabled).
214 */ 243 */
215 writel(0xffffffff, TIMER0_VAL); 244 writel(0xffffffff, timer_base + TIMER0_VAL_OFF);
216 writel(0xffffffff, TIMER0_RELOAD); 245 writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF);
217 u = readl(BRIDGE_MASK); 246 u = readl(bridge_base + BRIDGE_MASK_OFF);
218 writel(u & ~BRIDGE_INT_TIMER0, BRIDGE_MASK); 247 writel(u & ~BRIDGE_INT_TIMER0, bridge_base + BRIDGE_MASK_OFF);
219 u = readl(TIMER_CTRL); 248 u = readl(timer_base + TIMER_CTRL_OFF);
220 writel(u | TIMER0_EN | TIMER0_RELOAD_EN, TIMER_CTRL); 249 writel(u | TIMER0_EN | TIMER0_RELOAD_EN, timer_base + TIMER_CTRL_OFF);
221 clocksource_register_hz(&orion_clksrc, tclk); 250 clocksource_register_hz(&orion_clksrc, tclk);
222 251
223 /* 252 /*
224 * Setup clockevent timer (interrupt-driven.) 253 * Setup clockevent timer (interrupt-driven).
225 */ 254 */
226 setup_irq(irq, &orion_timer_irq); 255 setup_irq(irq, &orion_timer_irq);
227 orion_clkevt.mult = div_sc(tclk, NSEC_PER_SEC, orion_clkevt.shift); 256 orion_clkevt.mult = div_sc(tclk, NSEC_PER_SEC, orion_clkevt.shift);
diff --git a/arch/arm/plat-s3c24xx/Kconfig b/arch/arm/plat-s3c24xx/Kconfig
index eb105e61c746..d9c4096ebf45 100644
--- a/arch/arm/plat-s3c24xx/Kconfig
+++ b/arch/arm/plat-s3c24xx/Kconfig
@@ -56,13 +56,6 @@ config S3C24XX_DCLK
56 help 56 help
57 Clock code for supporting DCLK/CLKOUT on S3C24XX architectures 57 Clock code for supporting DCLK/CLKOUT on S3C24XX architectures
58 58
59config S3C24XX_PWM
60 bool "PWM device support"
61 select HAVE_PWM
62 help
63 Support for exporting the PWM timer blocks via the pwm device
64 system.
65
66# gpio configurations 59# gpio configurations
67 60
68config S3C24XX_GPIO_EXTRA 61config S3C24XX_GPIO_EXTRA
diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig
index 557f8c507f6d..849229716586 100644
--- a/arch/arm/plat-s5p/Kconfig
+++ b/arch/arm/plat-s5p/Kconfig
@@ -7,10 +7,10 @@
7 7
8config PLAT_S5P 8config PLAT_S5P
9 bool 9 bool
10 depends on (ARCH_S5P64X0 || ARCH_S5P6442 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_S5PV310) 10 depends on (ARCH_S5P64X0 || ARCH_S5P6442 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS4)
11 default y 11 default y
12 select ARM_VIC if !ARCH_S5PV310 12 select ARM_VIC if !ARCH_EXYNOS4
13 select ARM_GIC if ARCH_S5PV310 13 select ARM_GIC if ARCH_EXYNOS4
14 select NO_IOPORT 14 select NO_IOPORT
15 select ARCH_REQUIRE_GPIOLIB 15 select ARCH_REQUIRE_GPIOLIB
16 select S3C_GPIO_TRACK 16 select S3C_GPIO_TRACK
@@ -37,11 +37,16 @@ config S5P_GPIO_INT
37 help 37 help
38 Common code for the GPIO interrupts (other than external interrupts.) 38 Common code for the GPIO interrupts (other than external interrupts.)
39 39
40config S5P_HRT
41 bool
42 help
43 Use the High Resolution timer support
44
40comment "System MMU" 45comment "System MMU"
41 46
42config S5P_SYSTEM_MMU 47config S5P_SYSTEM_MMU
43 bool "S5P SYSTEM MMU" 48 bool "S5P SYSTEM MMU"
44 depends on ARCH_S5PV310 49 depends on ARCH_EXYNOS4
45 help 50 help
46 Say Y here if you want to enable System MMU 51 Say Y here if you want to enable System MMU
47 52
@@ -60,6 +65,11 @@ config S5P_DEV_FIMC2
60 help 65 help
61 Compile in platform device definitions for FIMC controller 2 66 Compile in platform device definitions for FIMC controller 2
62 67
68config S5P_DEV_FIMC3
69 bool
70 help
71 Compile in platform device definitions for FIMC controller 3
72
63config S5P_DEV_ONENAND 73config S5P_DEV_ONENAND
64 bool 74 bool
65 help 75 help
@@ -74,3 +84,8 @@ config S5P_DEV_CSIS1
74 bool 84 bool
75 help 85 help
76 Compile in platform device definitions for MIPI-CSIS channel 1 86 Compile in platform device definitions for MIPI-CSIS channel 1
87
88config S5P_SETUP_MIPIPHY
89 bool
90 help
91 Compile in common setup code for MIPI-CSIS and MIPI-DSIM devices
diff --git a/arch/arm/plat-s5p/Makefile b/arch/arm/plat-s5p/Makefile
index 4bd5cf908977..42afff7f60be 100644
--- a/arch/arm/plat-s5p/Makefile
+++ b/arch/arm/plat-s5p/Makefile
@@ -22,12 +22,15 @@ obj-$(CONFIG_S5P_GPIO_INT) += irq-gpioint.o
22obj-$(CONFIG_S5P_SYSTEM_MMU) += sysmmu.o 22obj-$(CONFIG_S5P_SYSTEM_MMU) += sysmmu.o
23obj-$(CONFIG_PM) += pm.o 23obj-$(CONFIG_PM) += pm.o
24obj-$(CONFIG_PM) += irq-pm.o 24obj-$(CONFIG_PM) += irq-pm.o
25obj-$(CONFIG_S5P_HRT) += s5p-time.o
25 26
26# devices 27# devices
27 28
28obj-$(CONFIG_S5P_DEV_FIMC0) += dev-fimc0.o 29obj-$(CONFIG_S5P_DEV_FIMC0) += dev-fimc0.o
29obj-$(CONFIG_S5P_DEV_FIMC1) += dev-fimc1.o 30obj-$(CONFIG_S5P_DEV_FIMC1) += dev-fimc1.o
30obj-$(CONFIG_S5P_DEV_FIMC2) += dev-fimc2.o 31obj-$(CONFIG_S5P_DEV_FIMC2) += dev-fimc2.o
32obj-$(CONFIG_S5P_DEV_FIMC3) += dev-fimc3.o
31obj-$(CONFIG_S5P_DEV_ONENAND) += dev-onenand.o 33obj-$(CONFIG_S5P_DEV_ONENAND) += dev-onenand.o
32obj-$(CONFIG_S5P_DEV_CSIS0) += dev-csis0.o 34obj-$(CONFIG_S5P_DEV_CSIS0) += dev-csis0.o
33obj-$(CONFIG_S5P_DEV_CSIS1) += dev-csis1.o 35obj-$(CONFIG_S5P_DEV_CSIS1) += dev-csis1.o
36obj-$(CONFIG_S5P_SETUP_MIPIPHY) += setup-mipiphy.o
diff --git a/arch/arm/plat-s5p/cpu.c b/arch/arm/plat-s5p/cpu.c
index 047d31c1bbd8..c3bfe9b13acf 100644
--- a/arch/arm/plat-s5p/cpu.c
+++ b/arch/arm/plat-s5p/cpu.c
@@ -1,7 +1,7 @@
1/* linux/arch/arm/plat-s5p/cpu.c 1/* linux/arch/arm/plat-s5p/cpu.c
2 * 2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * S5P CPU Support 6 * S5P CPU Support
7 * 7 *
@@ -12,17 +12,20 @@
12 12
13#include <linux/init.h> 13#include <linux/init.h>
14#include <linux/module.h> 14#include <linux/module.h>
15#include <mach/map.h> 15
16#include <asm/mach/arch.h> 16#include <asm/mach/arch.h>
17#include <asm/mach/map.h> 17#include <asm/mach/map.h>
18
19#include <mach/map.h>
18#include <mach/regs-clock.h> 20#include <mach/regs-clock.h>
21
19#include <plat/cpu.h> 22#include <plat/cpu.h>
20#include <plat/s5p6440.h> 23#include <plat/s5p6440.h>
21#include <plat/s5p6442.h> 24#include <plat/s5p6442.h>
22#include <plat/s5p6450.h> 25#include <plat/s5p6450.h>
23#include <plat/s5pc100.h> 26#include <plat/s5pc100.h>
24#include <plat/s5pv210.h> 27#include <plat/s5pv210.h>
25#include <plat/s5pv310.h> 28#include <plat/exynos4.h>
26 29
27/* table of supported CPUs */ 30/* table of supported CPUs */
28 31
@@ -31,7 +34,7 @@ static const char name_s5p6442[] = "S5P6442";
31static const char name_s5p6450[] = "S5P6450"; 34static const char name_s5p6450[] = "S5P6450";
32static const char name_s5pc100[] = "S5PC100"; 35static const char name_s5pc100[] = "S5PC100";
33static const char name_s5pv210[] = "S5PV210/S5PC110"; 36static const char name_s5pv210[] = "S5PV210/S5PC110";
34static const char name_s5pv310[] = "S5PV310"; 37static const char name_exynos4210[] = "EXYNOS4210";
35 38
36static struct cpu_table cpu_ids[] __initdata = { 39static struct cpu_table cpu_ids[] __initdata = {
37 { 40 {
@@ -75,13 +78,13 @@ static struct cpu_table cpu_ids[] __initdata = {
75 .init = s5pv210_init, 78 .init = s5pv210_init,
76 .name = name_s5pv210, 79 .name = name_s5pv210,
77 }, { 80 }, {
78 .idcode = 0x43200000, 81 .idcode = 0x43210000,
79 .idmask = 0xfffff000, 82 .idmask = 0xfffff000,
80 .map_io = s5pv310_map_io, 83 .map_io = exynos4_map_io,
81 .init_clocks = s5pv310_init_clocks, 84 .init_clocks = exynos4_init_clocks,
82 .init_uarts = s5pv310_init_uarts, 85 .init_uarts = exynos4_init_uarts,
83 .init = s5pv310_init, 86 .init = exynos4_init,
84 .name = name_s5pv310, 87 .name = name_exynos4210,
85 }, 88 },
86}; 89};
87 90
diff --git a/arch/arm/plat-s5p/dev-csis0.c b/arch/arm/plat-s5p/dev-csis0.c
index dfab1c85f54f..e3aabef5e347 100644
--- a/arch/arm/plat-s5p/dev-csis0.c
+++ b/arch/arm/plat-s5p/dev-csis0.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (C) 2010 Samsung Electronics 2 * Copyright (C) 2010-2011 Samsung Electronics Co., Ltd.
3 * 3 *
4 * S5P series device definition for MIPI-CSIS channel 0 4 * S5P series device definition for MIPI-CSIS channel 0
5 * 5 *
diff --git a/arch/arm/plat-s5p/dev-csis1.c b/arch/arm/plat-s5p/dev-csis1.c
index e3053f27fbbf..08b91b580207 100644
--- a/arch/arm/plat-s5p/dev-csis1.c
+++ b/arch/arm/plat-s5p/dev-csis1.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (C) 2010 Samsung Electronics 2 * Copyright (C) 2010-2011 Samsung Electronics Co., Ltd.
3 * 3 *
4 * S5P series device definition for MIPI-CSIS channel 1 4 * S5P series device definition for MIPI-CSIS channel 1
5 * 5 *
diff --git a/arch/arm/plat-s5p/dev-fimc3.c b/arch/arm/plat-s5p/dev-fimc3.c
new file mode 100644
index 000000000000..ef31beca386c
--- /dev/null
+++ b/arch/arm/plat-s5p/dev-fimc3.c
@@ -0,0 +1,43 @@
1/* linux/arch/arm/plat-s5p/dev-fimc3.c
2 *
3 * Copyright (c) 2010 Samsung Electronics
4 *
5 * Base S5P FIMC3 resource and device definitions
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/kernel.h>
13#include <linux/dma-mapping.h>
14#include <linux/platform_device.h>
15#include <linux/interrupt.h>
16#include <linux/ioport.h>
17#include <mach/map.h>
18
19static struct resource s5p_fimc3_resource[] = {
20 [0] = {
21 .start = S5P_PA_FIMC3,
22 .end = S5P_PA_FIMC3 + SZ_4K - 1,
23 .flags = IORESOURCE_MEM,
24 },
25 [1] = {
26 .start = IRQ_FIMC3,
27 .end = IRQ_FIMC3,
28 .flags = IORESOURCE_IRQ,
29 },
30};
31
32static u64 s5p_fimc3_dma_mask = DMA_BIT_MASK(32);
33
34struct platform_device s5p_device_fimc3 = {
35 .name = "s5p-fimc",
36 .id = 3,
37 .num_resources = ARRAY_SIZE(s5p_fimc3_resource),
38 .resource = s5p_fimc3_resource,
39 .dev = {
40 .dma_mask = &s5p_fimc3_dma_mask,
41 .coherent_dma_mask = DMA_BIT_MASK(32),
42 },
43};
diff --git a/arch/arm/plat-s5p/include/plat/camport.h b/arch/arm/plat-s5p/include/plat/camport.h
new file mode 100644
index 000000000000..71688c8ba288
--- /dev/null
+++ b/arch/arm/plat-s5p/include/plat/camport.h
@@ -0,0 +1,28 @@
1/*
2 * Copyright (C) 2011 Samsung Electronics Co., Ltd.
3 *
4 * S5P series camera interface helper functions
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef PLAT_S5P_CAMPORT_H_
12#define PLAT_S5P_CAMPORT_H_ __FILE__
13
14enum s5p_camport_id {
15 S5P_CAMPORT_A,
16 S5P_CAMPORT_B,
17};
18
19/*
20 * The helper functions to configure GPIO for the camera parallel bus.
21 * The camera port can be multiplexed with any FIMC entity, even multiple
22 * FIMC entities are allowed to be attached to a single port simultaneously.
23 * These functions are to be used in the board setup code.
24 */
25int s5pv210_fimc_setup_gpio(enum s5p_camport_id id);
26int exynos4_fimc_setup_gpio(enum s5p_camport_id id);
27
28#endif
diff --git a/arch/arm/plat-s5p/include/plat/csis.h b/arch/arm/plat-s5p/include/plat/csis.h
deleted file mode 100644
index 51e308c7981d..000000000000
--- a/arch/arm/plat-s5p/include/plat/csis.h
+++ /dev/null
@@ -1,28 +0,0 @@
1/*
2 * Copyright (C) 2010 Samsung Electronics
3 *
4 * S5P series MIPI CSI slave device support
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef PLAT_S5P_CSIS_H_
12#define PLAT_S5P_CSIS_H_ __FILE__
13
14/**
15 * struct s5p_platform_mipi_csis - platform data for MIPI-CSIS
16 * @clk_rate: bus clock frequency
17 * @lanes: number of data lanes used
18 * @alignment: data alignment in bits
19 * @hs_settle: HS-RX settle time
20 */
21struct s5p_platform_mipi_csis {
22 unsigned long clk_rate;
23 u8 lanes;
24 u8 alignment;
25 u8 hs_settle;
26};
27
28#endif /* PLAT_S5P_CSIS_H_ */
diff --git a/arch/arm/plat-s5p/include/plat/exynos4.h b/arch/arm/plat-s5p/include/plat/exynos4.h
new file mode 100644
index 000000000000..907caab53dcf
--- /dev/null
+++ b/arch/arm/plat-s5p/include/plat/exynos4.h
@@ -0,0 +1,34 @@
1/* linux/arch/arm/plat-s5p/include/plat/exynos4.h
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Header file for exynos4 cpu support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13/* Common init code for EXYNOS4 related SoCs */
14
15extern void exynos4_common_init_uarts(struct s3c2410_uartcfg *cfg, int no);
16extern void exynos4_register_clocks(void);
17extern void exynos4_setup_clocks(void);
18
19#ifdef CONFIG_CPU_EXYNOS4210
20
21extern int exynos4_init(void);
22extern void exynos4_init_irq(void);
23extern void exynos4_map_io(void);
24extern void exynos4_init_clocks(int xtal);
25extern struct sys_timer exynos4_timer;
26
27#define exynos4_init_uarts exynos4_common_init_uarts
28
29#else
30#define exynos4_init_clocks NULL
31#define exynos4_init_uarts NULL
32#define exynos4_map_io NULL
33#define exynos4_init NULL
34#endif
diff --git a/arch/arm/plat-s5p/include/plat/mipi_csis.h b/arch/arm/plat-s5p/include/plat/mipi_csis.h
new file mode 100644
index 000000000000..9bd254c5ed22
--- /dev/null
+++ b/arch/arm/plat-s5p/include/plat/mipi_csis.h
@@ -0,0 +1,43 @@
1/*
2 * Copyright (C) 2010-2011 Samsung Electronics Co., Ltd.
3 *
4 * S5P series MIPI CSI slave device support
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef PLAT_S5P_MIPI_CSIS_H_
12#define PLAT_S5P_MIPI_CSIS_H_ __FILE__
13
14struct platform_device;
15
16/**
17 * struct s5p_platform_mipi_csis - platform data for S5P MIPI-CSIS driver
18 * @clk_rate: bus clock frequency
19 * @lanes: number of data lanes used
20 * @alignment: data alignment in bits
21 * @hs_settle: HS-RX settle time
22 * @fixed_phy_vdd: false to enable external D-PHY regulator management in the
23 * driver or true in case this regulator has no enable function
24 * @phy_enable: pointer to a callback controlling D-PHY enable/reset
25 */
26struct s5p_platform_mipi_csis {
27 unsigned long clk_rate;
28 u8 lanes;
29 u8 alignment;
30 u8 hs_settle;
31 bool fixed_phy_vdd;
32 int (*phy_enable)(struct platform_device *pdev, bool on);
33};
34
35/**
36 * s5p_csis_phy_enable - global MIPI-CSI receiver D-PHY control
37 * @pdev: MIPI-CSIS platform device
38 * @on: true to enable D-PHY and deassert its reset
39 * false to disable D-PHY
40 */
41int s5p_csis_phy_enable(struct platform_device *pdev, bool on);
42
43#endif /* PLAT_S5P_MIPI_CSIS_H_ */
diff --git a/arch/arm/plat-s5p/include/plat/s5p-time.h b/arch/arm/plat-s5p/include/plat/s5p-time.h
new file mode 100644
index 000000000000..575e88109db8
--- /dev/null
+++ b/arch/arm/plat-s5p/include/plat/s5p-time.h
@@ -0,0 +1,40 @@
1/* linux/arch/arm/plat-s5p/include/plat/s5p-time.h
2 *
3 * Copyright 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * Header file for s5p time support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_PLAT_S5P_TIME_H
14#define __ASM_PLAT_S5P_TIME_H __FILE__
15
16/* S5P HR-Timer Clock mode */
17enum s5p_timer_mode {
18 S5P_PWM0,
19 S5P_PWM1,
20 S5P_PWM2,
21 S5P_PWM3,
22 S5P_PWM4,
23};
24
25struct s5p_timer_source {
26 unsigned int event_id;
27 unsigned int source_id;
28};
29
30/* Be able to sleep for atleast 4 seconds (usually more) */
31#define S5PTIMER_MIN_RANGE 4
32
33#define TCNT_MAX 0xffffffff
34#define NON_PERIODIC 0
35#define PERIODIC 1
36
37extern void __init s5p_set_timer_source(enum s5p_timer_mode event,
38 enum s5p_timer_mode source);
39extern struct sys_timer s5p_timer;
40#endif /* __ASM_PLAT_S5P_TIME_H */
diff --git a/arch/arm/plat-s5p/include/plat/s5pv310.h b/arch/arm/plat-s5p/include/plat/s5pv310.h
deleted file mode 100644
index 769c991ceb37..000000000000
--- a/arch/arm/plat-s5p/include/plat/s5pv310.h
+++ /dev/null
@@ -1,34 +0,0 @@
1/* linux/arch/arm/plat-s5p/include/plat/s5pv310.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * Header file for s5pv310 cpu support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13/* Common init code for S5PV310 related SoCs */
14
15extern void s5pv310_common_init_uarts(struct s3c2410_uartcfg *cfg, int no);
16extern void s5pv310_register_clocks(void);
17extern void s5pv310_setup_clocks(void);
18
19#ifdef CONFIG_CPU_S5PV310
20
21extern int s5pv310_init(void);
22extern void s5pv310_init_irq(void);
23extern void s5pv310_map_io(void);
24extern void s5pv310_init_clocks(int xtal);
25extern struct sys_timer s5pv310_timer;
26
27#define s5pv310_init_uarts s5pv310_common_init_uarts
28
29#else
30#define s5pv310_init_clocks NULL
31#define s5pv310_init_uarts NULL
32#define s5pv310_map_io NULL
33#define s5pv310_init NULL
34#endif
diff --git a/arch/arm/plat-s5p/include/plat/sysmmu.h b/arch/arm/plat-s5p/include/plat/sysmmu.h
new file mode 100644
index 000000000000..bf5283c2a19d
--- /dev/null
+++ b/arch/arm/plat-s5p/include/plat/sysmmu.h
@@ -0,0 +1,95 @@
1/* linux/arch/arm/plat-s5p/include/plat/sysmmu.h
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Samsung System MMU driver for S5P platform
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM__PLAT_SYSMMU_H
14#define __ASM__PLAT_SYSMMU_H __FILE__
15
16enum S5P_SYSMMU_INTERRUPT_TYPE {
17 SYSMMU_PAGEFAULT,
18 SYSMMU_AR_MULTIHIT,
19 SYSMMU_AW_MULTIHIT,
20 SYSMMU_BUSERROR,
21 SYSMMU_AR_SECURITY,
22 SYSMMU_AR_ACCESS,
23 SYSMMU_AW_SECURITY,
24 SYSMMU_AW_PROTECTION, /* 7 */
25 SYSMMU_FAULTS_NUM
26};
27
28#ifdef CONFIG_S5P_SYSTEM_MMU
29
30#include <mach/sysmmu.h>
31
32/**
33 * s5p_sysmmu_enable() - enable system mmu of ip
34 * @ips: The ip connected system mmu.
35 * #pgd: Base physical address of the 1st level page table
36 *
37 * This function enable system mmu to transfer address
38 * from virtual address to physical address
39 */
40void s5p_sysmmu_enable(sysmmu_ips ips, unsigned long pgd);
41
42/**
43 * s5p_sysmmu_disable() - disable sysmmu mmu of ip
44 * @ips: The ip connected system mmu.
45 *
46 * This function disable system mmu to transfer address
47 * from virtual address to physical address
48 */
49void s5p_sysmmu_disable(sysmmu_ips ips);
50
51/**
52 * s5p_sysmmu_set_tablebase_pgd() - set page table base address to refer page table
53 * @ips: The ip connected system mmu.
54 * @pgd: The page table base address.
55 *
56 * This function set page table base address
57 * When system mmu transfer address from virtaul address to physical address,
58 * system mmu refer address information from page table
59 */
60void s5p_sysmmu_set_tablebase_pgd(sysmmu_ips ips, unsigned long pgd);
61
62/**
63 * s5p_sysmmu_tlb_invalidate() - flush all TLB entry in system mmu
64 * @ips: The ip connected system mmu.
65 *
66 * This function flush all TLB entry in system mmu
67 */
68void s5p_sysmmu_tlb_invalidate(sysmmu_ips ips);
69
70/** s5p_sysmmu_set_fault_handler() - Fault handler for System MMUs
71 * @itype: type of fault.
72 * @pgtable_base: the physical address of page table base. This is 0 if @ips is
73 * SYSMMU_BUSERROR.
74 * @fault_addr: the device (virtual) address that the System MMU tried to
75 * translated. This is 0 if @ips is SYSMMU_BUSERROR.
76 * Called when interrupt occurred by the System MMUs
77 * The device drivers of peripheral devices that has a System MMU can implement
78 * a fault handler to resolve address translation fault by System MMU.
79 * The meanings of return value and parameters are described below.
80
81 * return value: non-zero if the fault is correctly resolved.
82 * zero if the fault is not handled.
83 */
84void s5p_sysmmu_set_fault_handler(sysmmu_ips ips,
85 int (*handler)(enum S5P_SYSMMU_INTERRUPT_TYPE itype,
86 unsigned long pgtable_base,
87 unsigned long fault_addr));
88#else
89#define s5p_sysmmu_enable(ips, pgd) do { } while (0)
90#define s5p_sysmmu_disable(ips) do { } while (0)
91#define s5p_sysmmu_set_tablebase_pgd(ips, pgd) do { } while (0)
92#define s5p_sysmmu_tlb_invalidate(ips) do { } while (0)
93#define s5p_sysmmu_set_fault_handler(ips, handler) do { } while (0)
94#endif
95#endif /* __ASM_PLAT_SYSMMU_H */
diff --git a/arch/arm/plat-s5p/irq-gpioint.c b/arch/arm/plat-s5p/irq-gpioint.c
index 3b6bf89d1739..cd87d3256e03 100644
--- a/arch/arm/plat-s5p/irq-gpioint.c
+++ b/arch/arm/plat-s5p/irq-gpioint.c
@@ -17,82 +17,79 @@
17#include <linux/irq.h> 17#include <linux/irq.h>
18#include <linux/io.h> 18#include <linux/io.h>
19#include <linux/gpio.h> 19#include <linux/gpio.h>
20#include <linux/slab.h>
20 21
21#include <mach/map.h> 22#include <mach/map.h>
22#include <plat/gpio-core.h> 23#include <plat/gpio-core.h>
23#include <plat/gpio-cfg.h> 24#include <plat/gpio-cfg.h>
24 25
25#define S5P_GPIOREG(x) (S5P_VA_GPIO + (x)) 26#define GPIO_BASE(chip) (((unsigned long)(chip)->base) & 0xFFFFF000u)
26 27
27#define GPIOINT_CON_OFFSET 0x700 28#define CON_OFFSET 0x700
28#define GPIOINT_MASK_OFFSET 0x900 29#define MASK_OFFSET 0x900
29#define GPIOINT_PEND_OFFSET 0xA00 30#define PEND_OFFSET 0xA00
31#define REG_OFFSET(x) ((x) << 2)
30 32
31static struct s3c_gpio_chip *irq_chips[S5P_GPIOINT_GROUP_MAXNR]; 33struct s5p_gpioint_bank {
32 34 struct list_head list;
33static int s5p_gpioint_get_group(struct irq_data *data) 35 int start;
34{ 36 int nr_groups;
35 struct gpio_chip *chip = irq_data_get_irq_data(data); 37 int irq;
36 struct s3c_gpio_chip *s3c_chip = container_of(chip, 38 struct s3c_gpio_chip **chips;
37 struct s3c_gpio_chip, chip); 39 void (*handler)(unsigned int, struct irq_desc *);
38 int group; 40};
39
40 for (group = 0; group < S5P_GPIOINT_GROUP_MAXNR; group++)
41 if (s3c_chip == irq_chips[group])
42 break;
43 41
44 return group; 42LIST_HEAD(banks);
45}
46 43
47static int s5p_gpioint_get_offset(struct irq_data *data) 44static int s5p_gpioint_get_offset(struct irq_data *data)
48{ 45{
49 struct gpio_chip *chip = irq_data_get_irq_data(data); 46 struct s3c_gpio_chip *chip = irq_data_get_irq_data(data);
50 struct s3c_gpio_chip *s3c_chip = container_of(chip, 47 return data->irq - chip->irq_base;
51 struct s3c_gpio_chip, chip);
52
53 return data->irq - s3c_chip->irq_base;
54} 48}
55 49
56static void s5p_gpioint_ack(struct irq_data *data) 50static void s5p_gpioint_ack(struct irq_data *data)
57{ 51{
52 struct s3c_gpio_chip *chip = irq_data_get_irq_data(data);
58 int group, offset, pend_offset; 53 int group, offset, pend_offset;
59 unsigned int value; 54 unsigned int value;
60 55
61 group = s5p_gpioint_get_group(data); 56 group = chip->group;
62 offset = s5p_gpioint_get_offset(data); 57 offset = s5p_gpioint_get_offset(data);
63 pend_offset = group << 2; 58 pend_offset = REG_OFFSET(group);
64 59
65 value = __raw_readl(S5P_GPIOREG(GPIOINT_PEND_OFFSET) + pend_offset); 60 value = __raw_readl(GPIO_BASE(chip) + PEND_OFFSET + pend_offset);
66 value |= 1 << offset; 61 value |= BIT(offset);
67 __raw_writel(value, S5P_GPIOREG(GPIOINT_PEND_OFFSET) + pend_offset); 62 __raw_writel(value, GPIO_BASE(chip) + PEND_OFFSET + pend_offset);
68} 63}
69 64
70static void s5p_gpioint_mask(struct irq_data *data) 65static void s5p_gpioint_mask(struct irq_data *data)
71{ 66{
67 struct s3c_gpio_chip *chip = irq_data_get_irq_data(data);
72 int group, offset, mask_offset; 68 int group, offset, mask_offset;
73 unsigned int value; 69 unsigned int value;
74 70
75 group = s5p_gpioint_get_group(data); 71 group = chip->group;
76 offset = s5p_gpioint_get_offset(data); 72 offset = s5p_gpioint_get_offset(data);
77 mask_offset = group << 2; 73 mask_offset = REG_OFFSET(group);
78 74
79 value = __raw_readl(S5P_GPIOREG(GPIOINT_MASK_OFFSET) + mask_offset); 75 value = __raw_readl(GPIO_BASE(chip) + MASK_OFFSET + mask_offset);
80 value |= 1 << offset; 76 value |= BIT(offset);
81 __raw_writel(value, S5P_GPIOREG(GPIOINT_MASK_OFFSET) + mask_offset); 77 __raw_writel(value, GPIO_BASE(chip) + MASK_OFFSET + mask_offset);
82} 78}
83 79
84static void s5p_gpioint_unmask(struct irq_data *data) 80static void s5p_gpioint_unmask(struct irq_data *data)
85{ 81{
82 struct s3c_gpio_chip *chip = irq_data_get_irq_data(data);
86 int group, offset, mask_offset; 83 int group, offset, mask_offset;
87 unsigned int value; 84 unsigned int value;
88 85
89 group = s5p_gpioint_get_group(data); 86 group = chip->group;
90 offset = s5p_gpioint_get_offset(data); 87 offset = s5p_gpioint_get_offset(data);
91 mask_offset = group << 2; 88 mask_offset = REG_OFFSET(group);
92 89
93 value = __raw_readl(S5P_GPIOREG(GPIOINT_MASK_OFFSET) + mask_offset); 90 value = __raw_readl(GPIO_BASE(chip) + MASK_OFFSET + mask_offset);
94 value &= ~(1 << offset); 91 value &= ~BIT(offset);
95 __raw_writel(value, S5P_GPIOREG(GPIOINT_MASK_OFFSET) + mask_offset); 92 __raw_writel(value, GPIO_BASE(chip) + MASK_OFFSET + mask_offset);
96} 93}
97 94
98static void s5p_gpioint_mask_ack(struct irq_data *data) 95static void s5p_gpioint_mask_ack(struct irq_data *data)
@@ -103,12 +100,13 @@ static void s5p_gpioint_mask_ack(struct irq_data *data)
103 100
104static int s5p_gpioint_set_type(struct irq_data *data, unsigned int type) 101static int s5p_gpioint_set_type(struct irq_data *data, unsigned int type)
105{ 102{
103 struct s3c_gpio_chip *chip = irq_data_get_irq_data(data);
106 int group, offset, con_offset; 104 int group, offset, con_offset;
107 unsigned int value; 105 unsigned int value;
108 106
109 group = s5p_gpioint_get_group(data); 107 group = chip->group;
110 offset = s5p_gpioint_get_offset(data); 108 offset = s5p_gpioint_get_offset(data);
111 con_offset = group << 2; 109 con_offset = REG_OFFSET(group);
112 110
113 switch (type) { 111 switch (type) {
114 case IRQ_TYPE_EDGE_RISING: 112 case IRQ_TYPE_EDGE_RISING:
@@ -132,15 +130,15 @@ static int s5p_gpioint_set_type(struct irq_data *data, unsigned int type)
132 return -EINVAL; 130 return -EINVAL;
133 } 131 }
134 132
135 value = __raw_readl(S5P_GPIOREG(GPIOINT_CON_OFFSET) + con_offset); 133 value = __raw_readl(GPIO_BASE(chip) + CON_OFFSET + con_offset);
136 value &= ~(0x7 << (offset * 0x4)); 134 value &= ~(0x7 << (offset * 0x4));
137 value |= (type << (offset * 0x4)); 135 value |= (type << (offset * 0x4));
138 __raw_writel(value, S5P_GPIOREG(GPIOINT_CON_OFFSET) + con_offset); 136 __raw_writel(value, GPIO_BASE(chip) + CON_OFFSET + con_offset);
139 137
140 return 0; 138 return 0;
141} 139}
142 140
143struct irq_chip s5p_gpioint = { 141static struct irq_chip s5p_gpioint = {
144 .name = "s5p_gpioint", 142 .name = "s5p_gpioint",
145 .irq_ack = s5p_gpioint_ack, 143 .irq_ack = s5p_gpioint_ack,
146 .irq_mask = s5p_gpioint_mask, 144 .irq_mask = s5p_gpioint_mask,
@@ -151,30 +149,29 @@ struct irq_chip s5p_gpioint = {
151 149
152static void s5p_gpioint_handler(unsigned int irq, struct irq_desc *desc) 150static void s5p_gpioint_handler(unsigned int irq, struct irq_desc *desc)
153{ 151{
154 int group, offset, pend_offset, mask_offset; 152 struct s5p_gpioint_bank *bank = get_irq_data(irq);
155 int real_irq; 153 int group, pend_offset, mask_offset;
156 unsigned int pend, mask; 154 unsigned int pend, mask;
157 155
158 for (group = 0; group < S5P_GPIOINT_GROUP_MAXNR; group++) { 156 for (group = 0; group < bank->nr_groups; group++) {
159 pend_offset = group << 2; 157 struct s3c_gpio_chip *chip = bank->chips[group];
160 pend = __raw_readl(S5P_GPIOREG(GPIOINT_PEND_OFFSET) + 158 if (!chip)
161 pend_offset); 159 continue;
160
161 pend_offset = REG_OFFSET(group);
162 pend = __raw_readl(GPIO_BASE(chip) + PEND_OFFSET + pend_offset);
162 if (!pend) 163 if (!pend)
163 continue; 164 continue;
164 165
165 mask_offset = group << 2; 166 mask_offset = REG_OFFSET(group);
166 mask = __raw_readl(S5P_GPIOREG(GPIOINT_MASK_OFFSET) + 167 mask = __raw_readl(GPIO_BASE(chip) + MASK_OFFSET + mask_offset);
167 mask_offset);
168 pend &= ~mask; 168 pend &= ~mask;
169 169
170 for (offset = 0; offset < 8; offset++) { 170 while (pend) {
171 if (pend & (1 << offset)) { 171 int offset = fls(pend) - 1;
172 struct s3c_gpio_chip *chip = irq_chips[group]; 172 int real_irq = chip->irq_base + offset;
173 if (chip) { 173 generic_handle_irq(real_irq);
174 real_irq = chip->irq_base + offset; 174 pend &= ~BIT(offset);
175 generic_handle_irq(real_irq);
176 }
177 }
178 } 175 }
179 } 176 }
180} 177}
@@ -182,27 +179,48 @@ static void s5p_gpioint_handler(unsigned int irq, struct irq_desc *desc)
182static __init int s5p_gpioint_add(struct s3c_gpio_chip *chip) 179static __init int s5p_gpioint_add(struct s3c_gpio_chip *chip)
183{ 180{
184 static int used_gpioint_groups = 0; 181 static int used_gpioint_groups = 0;
185 static bool handler_registered = 0;
186 int irq, group = chip->group; 182 int irq, group = chip->group;
187 int i; 183 int i;
184 struct s5p_gpioint_bank *bank = NULL;
188 185
189 if (used_gpioint_groups >= S5P_GPIOINT_GROUP_COUNT) 186 if (used_gpioint_groups >= S5P_GPIOINT_GROUP_COUNT)
190 return -ENOMEM; 187 return -ENOMEM;
191 188
189 list_for_each_entry(bank, &banks, list) {
190 if (group >= bank->start &&
191 group < bank->start + bank->nr_groups)
192 break;
193 }
194 if (!bank)
195 return -EINVAL;
196
197 if (!bank->handler) {
198 bank->chips = kzalloc(sizeof(struct s3c_gpio_chip *) *
199 bank->nr_groups, GFP_KERNEL);
200 if (!bank->chips)
201 return -ENOMEM;
202
203 set_irq_chained_handler(bank->irq, s5p_gpioint_handler);
204 set_irq_data(bank->irq, bank);
205 bank->handler = s5p_gpioint_handler;
206 printk(KERN_INFO "Registered chained gpio int handler for interrupt %d.\n",
207 bank->irq);
208 }
209
210 /*
211 * chained GPIO irq has been sucessfully registered, allocate new gpio
212 * int group and assign irq nubmers
213 */
214
192 chip->irq_base = S5P_GPIOINT_BASE + 215 chip->irq_base = S5P_GPIOINT_BASE +
193 used_gpioint_groups * S5P_GPIOINT_GROUP_SIZE; 216 used_gpioint_groups * S5P_GPIOINT_GROUP_SIZE;
194 used_gpioint_groups++; 217 used_gpioint_groups++;
195 218
196 if (!handler_registered) { 219 bank->chips[group - bank->start] = chip;
197 set_irq_chained_handler(IRQ_GPIOINT, s5p_gpioint_handler);
198 handler_registered = 1;
199 }
200
201 irq_chips[group] = chip;
202 for (i = 0; i < chip->chip.ngpio; i++) { 220 for (i = 0; i < chip->chip.ngpio; i++) {
203 irq = chip->irq_base + i; 221 irq = chip->irq_base + i;
204 set_irq_chip(irq, &s5p_gpioint); 222 set_irq_chip(irq, &s5p_gpioint);
205 set_irq_data(irq, &chip->chip); 223 set_irq_data(irq, chip);
206 set_irq_handler(irq, handle_level_irq); 224 set_irq_handler(irq, handle_level_irq);
207 set_irq_flags(irq, IRQF_VALID); 225 set_irq_flags(irq, IRQF_VALID);
208 } 226 }
@@ -235,3 +253,19 @@ int __init s5p_register_gpio_interrupt(int pin)
235 } 253 }
236 return ret; 254 return ret;
237} 255}
256
257int __init s5p_register_gpioint_bank(int chain_irq, int start, int nr_groups)
258{
259 struct s5p_gpioint_bank *bank;
260
261 bank = kzalloc(sizeof(*bank), GFP_KERNEL);
262 if (!bank)
263 return -ENOMEM;
264
265 bank->start = start;
266 bank->nr_groups = nr_groups;
267 bank->irq = chain_irq;
268
269 list_add_tail(&bank->list, &banks);
270 return 0;
271}
diff --git a/arch/arm/plat-s5p/s5p-time.c b/arch/arm/plat-s5p/s5p-time.c
new file mode 100644
index 000000000000..8090403eec0f
--- /dev/null
+++ b/arch/arm/plat-s5p/s5p-time.c
@@ -0,0 +1,448 @@
1/* linux/arch/arm/plat-s5p/s5p-time.c
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5P - Common hr-timer support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/sched.h>
14#include <linux/interrupt.h>
15#include <linux/irq.h>
16#include <linux/err.h>
17#include <linux/clk.h>
18#include <linux/clockchips.h>
19#include <linux/platform_device.h>
20
21#include <asm/smp_twd.h>
22#include <asm/mach/time.h>
23#include <asm/mach/arch.h>
24#include <asm/mach/map.h>
25#include <asm/sched_clock.h>
26
27#include <mach/map.h>
28#include <plat/devs.h>
29#include <plat/regs-timer.h>
30#include <plat/s5p-time.h>
31
32static struct clk *tin_event;
33static struct clk *tin_source;
34static struct clk *tdiv_event;
35static struct clk *tdiv_source;
36static struct clk *timerclk;
37static struct s5p_timer_source timer_source;
38static unsigned long clock_count_per_tick;
39static void s5p_timer_resume(void);
40
41static void s5p_time_stop(enum s5p_timer_mode mode)
42{
43 unsigned long tcon;
44
45 tcon = __raw_readl(S3C2410_TCON);
46
47 switch (mode) {
48 case S5P_PWM0:
49 tcon &= ~S3C2410_TCON_T0START;
50 break;
51
52 case S5P_PWM1:
53 tcon &= ~S3C2410_TCON_T1START;
54 break;
55
56 case S5P_PWM2:
57 tcon &= ~S3C2410_TCON_T2START;
58 break;
59
60 case S5P_PWM3:
61 tcon &= ~S3C2410_TCON_T3START;
62 break;
63
64 case S5P_PWM4:
65 tcon &= ~S3C2410_TCON_T4START;
66 break;
67
68 default:
69 printk(KERN_ERR "Invalid Timer %d\n", mode);
70 break;
71 }
72 __raw_writel(tcon, S3C2410_TCON);
73}
74
75static void s5p_time_setup(enum s5p_timer_mode mode, unsigned long tcnt)
76{
77 unsigned long tcon;
78
79 tcon = __raw_readl(S3C2410_TCON);
80
81 tcnt--;
82
83 switch (mode) {
84 case S5P_PWM0:
85 tcon &= ~(0x0f << 0);
86 tcon |= S3C2410_TCON_T0MANUALUPD;
87 break;
88
89 case S5P_PWM1:
90 tcon &= ~(0x0f << 8);
91 tcon |= S3C2410_TCON_T1MANUALUPD;
92 break;
93
94 case S5P_PWM2:
95 tcon &= ~(0x0f << 12);
96 tcon |= S3C2410_TCON_T2MANUALUPD;
97 break;
98
99 case S5P_PWM3:
100 tcon &= ~(0x0f << 16);
101 tcon |= S3C2410_TCON_T3MANUALUPD;
102 break;
103
104 case S5P_PWM4:
105 tcon &= ~(0x07 << 20);
106 tcon |= S3C2410_TCON_T4MANUALUPD;
107 break;
108
109 default:
110 printk(KERN_ERR "Invalid Timer %d\n", mode);
111 break;
112 }
113
114 __raw_writel(tcnt, S3C2410_TCNTB(mode));
115 __raw_writel(tcnt, S3C2410_TCMPB(mode));
116 __raw_writel(tcon, S3C2410_TCON);
117}
118
119static void s5p_time_start(enum s5p_timer_mode mode, bool periodic)
120{
121 unsigned long tcon;
122
123 tcon = __raw_readl(S3C2410_TCON);
124
125 switch (mode) {
126 case S5P_PWM0:
127 tcon |= S3C2410_TCON_T0START;
128 tcon &= ~S3C2410_TCON_T0MANUALUPD;
129
130 if (periodic)
131 tcon |= S3C2410_TCON_T0RELOAD;
132 else
133 tcon &= ~S3C2410_TCON_T0RELOAD;
134 break;
135
136 case S5P_PWM1:
137 tcon |= S3C2410_TCON_T1START;
138 tcon &= ~S3C2410_TCON_T1MANUALUPD;
139
140 if (periodic)
141 tcon |= S3C2410_TCON_T1RELOAD;
142 else
143 tcon &= ~S3C2410_TCON_T1RELOAD;
144 break;
145
146 case S5P_PWM2:
147 tcon |= S3C2410_TCON_T2START;
148 tcon &= ~S3C2410_TCON_T2MANUALUPD;
149
150 if (periodic)
151 tcon |= S3C2410_TCON_T2RELOAD;
152 else
153 tcon &= ~S3C2410_TCON_T2RELOAD;
154 break;
155
156 case S5P_PWM3:
157 tcon |= S3C2410_TCON_T3START;
158 tcon &= ~S3C2410_TCON_T3MANUALUPD;
159
160 if (periodic)
161 tcon |= S3C2410_TCON_T3RELOAD;
162 else
163 tcon &= ~S3C2410_TCON_T3RELOAD;
164 break;
165
166 case S5P_PWM4:
167 tcon |= S3C2410_TCON_T4START;
168 tcon &= ~S3C2410_TCON_T4MANUALUPD;
169
170 if (periodic)
171 tcon |= S3C2410_TCON_T4RELOAD;
172 else
173 tcon &= ~S3C2410_TCON_T4RELOAD;
174 break;
175
176 default:
177 printk(KERN_ERR "Invalid Timer %d\n", mode);
178 break;
179 }
180 __raw_writel(tcon, S3C2410_TCON);
181}
182
183static int s5p_set_next_event(unsigned long cycles,
184 struct clock_event_device *evt)
185{
186 s5p_time_setup(timer_source.event_id, cycles);
187 s5p_time_start(timer_source.event_id, NON_PERIODIC);
188
189 return 0;
190}
191
192static void s5p_set_mode(enum clock_event_mode mode,
193 struct clock_event_device *evt)
194{
195 s5p_time_stop(timer_source.event_id);
196
197 switch (mode) {
198 case CLOCK_EVT_MODE_PERIODIC:
199 s5p_time_setup(timer_source.event_id, clock_count_per_tick);
200 s5p_time_start(timer_source.event_id, PERIODIC);
201 break;
202
203 case CLOCK_EVT_MODE_ONESHOT:
204 break;
205
206 case CLOCK_EVT_MODE_UNUSED:
207 case CLOCK_EVT_MODE_SHUTDOWN:
208 break;
209
210 case CLOCK_EVT_MODE_RESUME:
211 s5p_timer_resume();
212 break;
213 }
214}
215
216static void s5p_timer_resume(void)
217{
218 /* event timer restart */
219 s5p_time_setup(timer_source.event_id, clock_count_per_tick);
220 s5p_time_start(timer_source.event_id, PERIODIC);
221
222 /* source timer restart */
223 s5p_time_setup(timer_source.source_id, TCNT_MAX);
224 s5p_time_start(timer_source.source_id, PERIODIC);
225}
226
227void __init s5p_set_timer_source(enum s5p_timer_mode event,
228 enum s5p_timer_mode source)
229{
230 s3c_device_timer[event].dev.bus = &platform_bus_type;
231 s3c_device_timer[source].dev.bus = &platform_bus_type;
232
233 timer_source.event_id = event;
234 timer_source.source_id = source;
235}
236
237static struct clock_event_device time_event_device = {
238 .name = "s5p_event_timer",
239 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
240 .rating = 200,
241 .set_next_event = s5p_set_next_event,
242 .set_mode = s5p_set_mode,
243};
244
245static irqreturn_t s5p_clock_event_isr(int irq, void *dev_id)
246{
247 struct clock_event_device *evt = dev_id;
248
249 evt->event_handler(evt);
250
251 return IRQ_HANDLED;
252}
253
254static struct irqaction s5p_clock_event_irq = {
255 .name = "s5p_time_irq",
256 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
257 .handler = s5p_clock_event_isr,
258 .dev_id = &time_event_device,
259};
260
261static void __init s5p_clockevent_init(void)
262{
263 unsigned long pclk;
264 unsigned long clock_rate;
265 unsigned int irq_number;
266 struct clk *tscaler;
267
268 pclk = clk_get_rate(timerclk);
269
270 tscaler = clk_get_parent(tdiv_event);
271
272 clk_set_rate(tscaler, pclk / 2);
273 clk_set_rate(tdiv_event, pclk / 2);
274 clk_set_parent(tin_event, tdiv_event);
275
276 clock_rate = clk_get_rate(tin_event);
277 clock_count_per_tick = clock_rate / HZ;
278
279 clockevents_calc_mult_shift(&time_event_device,
280 clock_rate, S5PTIMER_MIN_RANGE);
281 time_event_device.max_delta_ns =
282 clockevent_delta2ns(-1, &time_event_device);
283 time_event_device.min_delta_ns =
284 clockevent_delta2ns(1, &time_event_device);
285
286 time_event_device.cpumask = cpumask_of(0);
287 clockevents_register_device(&time_event_device);
288
289 irq_number = timer_source.event_id + IRQ_TIMER0;
290 setup_irq(irq_number, &s5p_clock_event_irq);
291}
292
293static cycle_t s5p_timer_read(struct clocksource *cs)
294{
295 unsigned long offset = 0;
296
297 switch (timer_source.source_id) {
298 case S5P_PWM0:
299 case S5P_PWM1:
300 case S5P_PWM2:
301 case S5P_PWM3:
302 offset = (timer_source.source_id * 0x0c) + 0x14;
303 break;
304
305 case S5P_PWM4:
306 offset = 0x40;
307 break;
308
309 default:
310 printk(KERN_ERR "Invalid Timer %d\n", timer_source.source_id);
311 return 0;
312 }
313
314 return (cycle_t) ~__raw_readl(S3C_TIMERREG(offset));
315}
316
317/*
318 * Override the global weak sched_clock symbol with this
319 * local implementation which uses the clocksource to get some
320 * better resolution when scheduling the kernel. We accept that
321 * this wraps around for now, since it is just a relative time
322 * stamp. (Inspired by U300 implementation.)
323 */
324static DEFINE_CLOCK_DATA(cd);
325
326unsigned long long notrace sched_clock(void)
327{
328 u32 cyc;
329 unsigned long offset = 0;
330
331 switch (timer_source.source_id) {
332 case S5P_PWM0:
333 case S5P_PWM1:
334 case S5P_PWM2:
335 case S5P_PWM3:
336 offset = (timer_source.source_id * 0x0c) + 0x14;
337 break;
338
339 case S5P_PWM4:
340 offset = 0x40;
341 break;
342
343 default:
344 printk(KERN_ERR "Invalid Timer %d\n", timer_source.source_id);
345 return 0;
346 }
347
348 cyc = ~__raw_readl(S3C_TIMERREG(offset));
349 return cyc_to_sched_clock(&cd, cyc, (u32)~0);
350}
351
352static void notrace s5p_update_sched_clock(void)
353{
354 u32 cyc;
355 unsigned long offset = 0;
356
357 switch (timer_source.source_id) {
358 case S5P_PWM0:
359 case S5P_PWM1:
360 case S5P_PWM2:
361 case S5P_PWM3:
362 offset = (timer_source.source_id * 0x0c) + 0x14;
363 break;
364
365 case S5P_PWM4:
366 offset = 0x40;
367 break;
368
369 default:
370 printk(KERN_ERR "Invalid Timer %d\n", timer_source.source_id);
371 }
372
373 cyc = ~__raw_readl(S3C_TIMERREG(offset));
374 update_sched_clock(&cd, cyc, (u32)~0);
375}
376
377struct clocksource time_clocksource = {
378 .name = "s5p_clocksource_timer",
379 .rating = 250,
380 .read = s5p_timer_read,
381 .mask = CLOCKSOURCE_MASK(32),
382 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
383};
384
385static void __init s5p_clocksource_init(void)
386{
387 unsigned long pclk;
388 unsigned long clock_rate;
389
390 pclk = clk_get_rate(timerclk);
391
392 clk_set_rate(tdiv_source, pclk / 2);
393 clk_set_parent(tin_source, tdiv_source);
394
395 clock_rate = clk_get_rate(tin_source);
396
397 init_sched_clock(&cd, s5p_update_sched_clock, 32, clock_rate);
398
399 s5p_time_setup(timer_source.source_id, TCNT_MAX);
400 s5p_time_start(timer_source.source_id, PERIODIC);
401
402 if (clocksource_register_hz(&time_clocksource, clock_rate))
403 panic("%s: can't register clocksource\n", time_clocksource.name);
404}
405
406static void __init s5p_timer_resources(void)
407{
408
409 unsigned long event_id = timer_source.event_id;
410 unsigned long source_id = timer_source.source_id;
411
412 timerclk = clk_get(NULL, "timers");
413 if (IS_ERR(timerclk))
414 panic("failed to get timers clock for timer");
415
416 clk_enable(timerclk);
417
418 tin_event = clk_get(&s3c_device_timer[event_id].dev, "pwm-tin");
419 if (IS_ERR(tin_event))
420 panic("failed to get pwm-tin clock for event timer");
421
422 tdiv_event = clk_get(&s3c_device_timer[event_id].dev, "pwm-tdiv");
423 if (IS_ERR(tdiv_event))
424 panic("failed to get pwm-tdiv clock for event timer");
425
426 clk_enable(tin_event);
427
428 tin_source = clk_get(&s3c_device_timer[source_id].dev, "pwm-tin");
429 if (IS_ERR(tin_source))
430 panic("failed to get pwm-tin clock for source timer");
431
432 tdiv_source = clk_get(&s3c_device_timer[source_id].dev, "pwm-tdiv");
433 if (IS_ERR(tdiv_source))
434 panic("failed to get pwm-tdiv clock for source timer");
435
436 clk_enable(tin_source);
437}
438
439static void __init s5p_timer_init(void)
440{
441 s5p_timer_resources();
442 s5p_clockevent_init();
443 s5p_clocksource_init();
444}
445
446struct sys_timer s5p_timer = {
447 .init = s5p_timer_init,
448};
diff --git a/arch/arm/plat-s5p/setup-mipiphy.c b/arch/arm/plat-s5p/setup-mipiphy.c
new file mode 100644
index 000000000000..683c466c0e6a
--- /dev/null
+++ b/arch/arm/plat-s5p/setup-mipiphy.c
@@ -0,0 +1,63 @@
1/*
2 * Copyright (C) 2011 Samsung Electronics Co., Ltd.
3 *
4 * S5P - Helper functions for MIPI-CSIS and MIPI-DSIM D-PHY control
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/kernel.h>
12#include <linux/platform_device.h>
13#include <linux/io.h>
14#include <linux/spinlock.h>
15#include <mach/regs-clock.h>
16
17static int __s5p_mipi_phy_control(struct platform_device *pdev,
18 bool on, u32 reset)
19{
20 static DEFINE_SPINLOCK(lock);
21 void __iomem *addr;
22 unsigned long flags;
23 int pid;
24 u32 cfg;
25
26 if (!pdev)
27 return -EINVAL;
28
29 pid = (pdev->id == -1) ? 0 : pdev->id;
30
31 if (pid != 0 && pid != 1)
32 return -EINVAL;
33
34 addr = S5P_MIPI_DPHY_CONTROL(pid);
35
36 spin_lock_irqsave(&lock, flags);
37
38 cfg = __raw_readl(addr);
39 cfg = on ? (cfg | reset) : (cfg & ~reset);
40 __raw_writel(cfg, addr);
41
42 if (on) {
43 cfg |= S5P_MIPI_DPHY_ENABLE;
44 } else if (!(cfg & (S5P_MIPI_DPHY_SRESETN |
45 S5P_MIPI_DPHY_MRESETN) & ~reset)) {
46 cfg &= ~S5P_MIPI_DPHY_ENABLE;
47 }
48
49 __raw_writel(cfg, addr);
50 spin_unlock_irqrestore(&lock, flags);
51
52 return 0;
53}
54
55int s5p_csis_phy_enable(struct platform_device *pdev, bool on)
56{
57 return __s5p_mipi_phy_control(pdev, on, S5P_MIPI_DPHY_SRESETN);
58}
59
60int s5p_dsim_phy_enable(struct platform_device *pdev, bool on)
61{
62 return __s5p_mipi_phy_control(pdev, on, S5P_MIPI_DPHY_MRESETN);
63}
diff --git a/arch/arm/plat-s5p/sysmmu.c b/arch/arm/plat-s5p/sysmmu.c
index ffe8a48bc3c1..54f5eddc921d 100644
--- a/arch/arm/plat-s5p/sysmmu.c
+++ b/arch/arm/plat-s5p/sysmmu.c
@@ -12,280 +12,266 @@
12#include <linux/interrupt.h> 12#include <linux/interrupt.h>
13#include <linux/platform_device.h> 13#include <linux/platform_device.h>
14 14
15#include <asm/pgtable.h>
16
15#include <mach/map.h> 17#include <mach/map.h>
16#include <mach/regs-sysmmu.h> 18#include <mach/regs-sysmmu.h>
17#include <mach/sysmmu.h> 19#include <plat/sysmmu.h>
20
21#define CTRL_ENABLE 0x5
22#define CTRL_BLOCK 0x7
23#define CTRL_DISABLE 0x0
24
25static struct device *dev;
26
27static unsigned short fault_reg_offset[SYSMMU_FAULTS_NUM] = {
28 S5P_PAGE_FAULT_ADDR,
29 S5P_AR_FAULT_ADDR,
30 S5P_AW_FAULT_ADDR,
31 S5P_DEFAULT_SLAVE_ADDR,
32 S5P_AR_FAULT_ADDR,
33 S5P_AR_FAULT_ADDR,
34 S5P_AW_FAULT_ADDR,
35 S5P_AW_FAULT_ADDR
36};
37
38static char *sysmmu_fault_name[SYSMMU_FAULTS_NUM] = {
39 "PAGE FAULT",
40 "AR MULTI-HIT FAULT",
41 "AW MULTI-HIT FAULT",
42 "BUS ERROR",
43 "AR SECURITY PROTECTION FAULT",
44 "AR ACCESS PROTECTION FAULT",
45 "AW SECURITY PROTECTION FAULT",
46 "AW ACCESS PROTECTION FAULT"
47};
18 48
19struct sysmmu_controller s5p_sysmmu_cntlrs[S5P_SYSMMU_TOTAL_IPNUM]; 49static int (*fault_handlers[S5P_SYSMMU_TOTAL_IPNUM])(
50 enum S5P_SYSMMU_INTERRUPT_TYPE itype,
51 unsigned long pgtable_base,
52 unsigned long fault_addr);
20 53
21void s5p_sysmmu_register(struct sysmmu_controller *sysmmuconp) 54/*
55 * If adjacent 2 bits are true, the system MMU is enabled.
56 * The system MMU is disabled, otherwise.
57 */
58static unsigned long sysmmu_states;
59
60static inline void set_sysmmu_active(sysmmu_ips ips)
22{ 61{
23 unsigned int reg_mmu_ctrl; 62 sysmmu_states |= 3 << (ips * 2);
24 unsigned int reg_mmu_status;
25 unsigned int reg_pt_base_addr;
26 unsigned int reg_int_status;
27 unsigned int reg_page_ft_addr;
28
29 reg_int_status = __raw_readl(sysmmuconp->regs + S5P_INT_STATUS);
30 reg_mmu_ctrl = __raw_readl(sysmmuconp->regs + S5P_MMU_CTRL);
31 reg_mmu_status = __raw_readl(sysmmuconp->regs + S5P_MMU_STATUS);
32 reg_pt_base_addr = __raw_readl(sysmmuconp->regs + S5P_PT_BASE_ADDR);
33 reg_page_ft_addr = __raw_readl(sysmmuconp->regs + S5P_PAGE_FAULT_ADDR);
34
35 printk(KERN_INFO "%s: ips:%s\n", __func__, sysmmuconp->name);
36 printk(KERN_INFO "%s: MMU_CTRL:0x%X, ", __func__, reg_mmu_ctrl);
37 printk(KERN_INFO "MMU_STATUS:0x%X, PT_BASE_ADDR:0x%X\n", reg_mmu_status, reg_pt_base_addr);
38 printk(KERN_INFO "%s: INT_STATUS:0x%X, PAGE_FAULT_ADDR:0x%X\n", __func__, reg_int_status, reg_page_ft_addr);
39
40 switch (reg_int_status & 0xFF) {
41 case 0x1:
42 printk(KERN_INFO "%s: Page fault\n", __func__);
43 printk(KERN_INFO "%s: Virtual address causing last page fault or bus error : 0x%x\n", __func__ , reg_page_ft_addr);
44 break;
45 case 0x2:
46 printk(KERN_INFO "%s: AR multi-hit fault\n", __func__);
47 break;
48 case 0x4:
49 printk(KERN_INFO "%s: AW multi-hit fault\n", __func__);
50 break;
51 case 0x8:
52 printk(KERN_INFO "%s: Bus error\n", __func__);
53 break;
54 case 0x10:
55 printk(KERN_INFO "%s: AR Security protection fault\n", __func__);
56 break;
57 case 0x20:
58 printk(KERN_INFO "%s: AR Access protection fault\n", __func__);
59 break;
60 case 0x40:
61 printk(KERN_INFO "%s: AW Security protection fault\n", __func__);
62 break;
63 case 0x80:
64 printk(KERN_INFO "%s: AW Access protection fault\n", __func__);
65 break;
66 }
67} 63}
68 64
69static irqreturn_t s5p_sysmmu_irq(int irq, void *dev_id) 65static inline void set_sysmmu_inactive(sysmmu_ips ips)
70{ 66{
71 unsigned int i; 67 sysmmu_states &= ~(3 << (ips * 2));
72 unsigned int reg_int_status;
73 struct sysmmu_controller *sysmmuconp;
74
75 for (i = 0; i < S5P_SYSMMU_TOTAL_IPNUM; i++) {
76 sysmmuconp = &s5p_sysmmu_cntlrs[i];
77
78 if (sysmmuconp->enable == true) {
79 reg_int_status = __raw_readl(sysmmuconp->regs + S5P_INT_STATUS);
80
81 if (reg_int_status & 0xFF)
82 s5p_sysmmu_register(sysmmuconp);
83 }
84 }
85 return IRQ_HANDLED;
86} 68}
87 69
88int s5p_sysmmu_set_tablebase_pgd(sysmmu_ips ips, unsigned long pgd) 70static inline int is_sysmmu_active(sysmmu_ips ips)
89{ 71{
90 struct sysmmu_controller *sysmmuconp = NULL; 72 return sysmmu_states & (3 << (ips * 2));
91 73}
92 sysmmuconp = &s5p_sysmmu_cntlrs[ips];
93
94 if (sysmmuconp == NULL) {
95 printk(KERN_ERR "failed to get ip's sysmmu info\n");
96 return 1;
97 }
98
99 /* Set sysmmu page table base address */
100 __raw_writel(pgd, sysmmuconp->regs + S5P_PT_BASE_ADDR);
101 74
102 if (s5p_sysmmu_tlb_invalidate(ips) != 0) 75static void __iomem *sysmmusfrs[S5P_SYSMMU_TOTAL_IPNUM];
103 printk(KERN_ERR "failed s5p_sysmmu_tlb_invalidate\n");
104 76
105 return 0; 77static inline void sysmmu_block(sysmmu_ips ips)
78{
79 __raw_writel(CTRL_BLOCK, sysmmusfrs[ips] + S5P_MMU_CTRL);
80 dev_dbg(dev, "%s is blocked.\n", sysmmu_ips_name[ips]);
106} 81}
107 82
108static int s5p_sysmmu_set_tablebase(sysmmu_ips ips) 83static inline void sysmmu_unblock(sysmmu_ips ips)
109{ 84{
110 unsigned int pg; 85 __raw_writel(CTRL_ENABLE, sysmmusfrs[ips] + S5P_MMU_CTRL);
111 struct sysmmu_controller *sysmmuconp; 86 dev_dbg(dev, "%s is unblocked.\n", sysmmu_ips_name[ips]);
87}
112 88
113 sysmmuconp = &s5p_sysmmu_cntlrs[ips]; 89static inline void __sysmmu_tlb_invalidate(sysmmu_ips ips)
90{
91 __raw_writel(0x1, sysmmusfrs[ips] + S5P_MMU_FLUSH);
92 dev_dbg(dev, "TLB of %s is invalidated.\n", sysmmu_ips_name[ips]);
93}
114 94
115 if (sysmmuconp == NULL) { 95static inline void __sysmmu_set_ptbase(sysmmu_ips ips, unsigned long pgd)
116 printk(KERN_ERR "failed to get ip's sysmmu info\n"); 96{
117 return 1; 97 if (unlikely(pgd == 0)) {
98 pgd = (unsigned long)ZERO_PAGE(0);
99 __raw_writel(0x20, sysmmusfrs[ips] + S5P_MMU_CFG); /* 4KB LV1 */
100 } else {
101 __raw_writel(0x0, sysmmusfrs[ips] + S5P_MMU_CFG); /* 16KB LV1 */
118 } 102 }
119 103
120 __asm__("mrc p15, 0, %0, c2, c0, 0" \ 104 __raw_writel(pgd, sysmmusfrs[ips] + S5P_PT_BASE_ADDR);
121 : "=r" (pg) : : "cc"); \
122 pg &= ~0x3fff;
123 105
124 printk(KERN_INFO "%s: CP15 TTBR0 : 0x%x\n", __func__, pg); 106 dev_dbg(dev, "Page table base of %s is initialized with 0x%08lX.\n",
125 107 sysmmu_ips_name[ips], pgd);
126 /* Set sysmmu page table base address */ 108 __sysmmu_tlb_invalidate(ips);
127 __raw_writel(pg, sysmmuconp->regs + S5P_PT_BASE_ADDR); 109}
128 110
129 return 0; 111void sysmmu_set_fault_handler(sysmmu_ips ips,
112 int (*handler)(enum S5P_SYSMMU_INTERRUPT_TYPE itype,
113 unsigned long pgtable_base,
114 unsigned long fault_addr))
115{
116 BUG_ON(!((ips >= SYSMMU_MDMA) && (ips < S5P_SYSMMU_TOTAL_IPNUM)));
117 fault_handlers[ips] = handler;
130} 118}
131 119
132int s5p_sysmmu_enable(sysmmu_ips ips) 120static irqreturn_t s5p_sysmmu_irq(int irq, void *dev_id)
133{ 121{
134 unsigned int reg; 122 /* SYSMMU is in blocked when interrupt occurred. */
123 unsigned long base = 0;
124 sysmmu_ips ips = (sysmmu_ips)dev_id;
125 enum S5P_SYSMMU_INTERRUPT_TYPE itype;
135 126
136 struct sysmmu_controller *sysmmuconp; 127 itype = (enum S5P_SYSMMU_INTERRUPT_TYPE)
128 __ffs(__raw_readl(sysmmusfrs[ips] + S5P_INT_STATUS));
137 129
138 sysmmuconp = &s5p_sysmmu_cntlrs[ips]; 130 BUG_ON(!((itype >= 0) && (itype < 8)));
139 131
140 if (sysmmuconp == NULL) { 132 dev_alert(dev, "%s occurred by %s.\n", sysmmu_fault_name[itype],
141 printk(KERN_ERR "failed to get ip's sysmmu info\n"); 133 sysmmu_ips_name[ips]);
142 return 1;
143 }
144 134
145 s5p_sysmmu_set_tablebase(ips); 135 if (fault_handlers[ips]) {
136 unsigned long addr;
146 137
147 /* replacement policy : LRU */ 138 base = __raw_readl(sysmmusfrs[ips] + S5P_PT_BASE_ADDR);
148 reg = __raw_readl(sysmmuconp->regs + S5P_MMU_CFG); 139 addr = __raw_readl(sysmmusfrs[ips] + fault_reg_offset[itype]);
149 reg |= 0x1;
150 __raw_writel(reg, sysmmuconp->regs + S5P_MMU_CFG);
151 140
152 /* Enable interrupt, Enable MMU */ 141 if (fault_handlers[ips](itype, base, addr)) {
153 reg = __raw_readl(sysmmuconp->regs + S5P_MMU_CTRL); 142 __raw_writel(1 << itype,
154 reg |= (0x1 << 2) | (0x1 << 0); 143 sysmmusfrs[ips] + S5P_INT_CLEAR);
144 dev_notice(dev, "%s from %s is resolved."
145 " Retrying translation.\n",
146 sysmmu_fault_name[itype], sysmmu_ips_name[ips]);
147 } else {
148 base = 0;
149 }
150 }
155 151
156 __raw_writel(reg, sysmmuconp->regs + S5P_MMU_CTRL); 152 sysmmu_unblock(ips);
157 153
158 sysmmuconp->enable = true; 154 if (!base)
155 dev_notice(dev, "%s from %s is not handled.\n",
156 sysmmu_fault_name[itype], sysmmu_ips_name[ips]);
159 157
160 return 0; 158 return IRQ_HANDLED;
161} 159}
162 160
163int s5p_sysmmu_disable(sysmmu_ips ips) 161void s5p_sysmmu_set_tablebase_pgd(sysmmu_ips ips, unsigned long pgd)
164{ 162{
165 unsigned int reg; 163 if (is_sysmmu_active(ips)) {
166 164 sysmmu_block(ips);
167 struct sysmmu_controller *sysmmuconp = NULL; 165 __sysmmu_set_ptbase(ips, pgd);
168 166 sysmmu_unblock(ips);
169 if (ips > S5P_SYSMMU_TOTAL_IPNUM) 167 } else {
170 printk(KERN_ERR "failed to get ips parameter\n"); 168 dev_dbg(dev, "%s is disabled. "
171 169 "Skipping initializing page table base.\n",
172 sysmmuconp = &s5p_sysmmu_cntlrs[ips]; 170 sysmmu_ips_name[ips]);
173
174 if (sysmmuconp == NULL) {
175 printk(KERN_ERR "failed to get ip's sysmmu info\n");
176 return 1;
177 } 171 }
172}
178 173
179 reg = __raw_readl(sysmmuconp->regs + S5P_MMU_CFG); 174void s5p_sysmmu_enable(sysmmu_ips ips, unsigned long pgd)
180 175{
181 /* replacement policy : LRU */ 176 if (!is_sysmmu_active(ips)) {
182 reg |= 0x1; 177 sysmmu_clk_enable(ips);
183 __raw_writel(reg, sysmmuconp->regs + S5P_MMU_CFG);
184
185 reg = __raw_readl(sysmmuconp->regs + S5P_MMU_CTRL);
186 178
187 /* Disable MMU */ 179 __sysmmu_set_ptbase(ips, pgd);
188 reg &= ~0x1;
189 __raw_writel(reg, sysmmuconp->regs + S5P_MMU_CTRL);
190 180
191 sysmmuconp->enable = false; 181 __raw_writel(CTRL_ENABLE, sysmmusfrs[ips] + S5P_MMU_CTRL);
192 182
193 return 0; 183 set_sysmmu_active(ips);
184 dev_dbg(dev, "%s is enabled.\n", sysmmu_ips_name[ips]);
185 } else {
186 dev_dbg(dev, "%s is already enabled.\n", sysmmu_ips_name[ips]);
187 }
194} 188}
195 189
196int s5p_sysmmu_tlb_invalidate(sysmmu_ips ips) 190void s5p_sysmmu_disable(sysmmu_ips ips)
197{ 191{
198 unsigned int reg; 192 if (is_sysmmu_active(ips)) {
199 struct sysmmu_controller *sysmmuconp = NULL; 193 __raw_writel(CTRL_DISABLE, sysmmusfrs[ips] + S5P_MMU_CTRL);
200 194 set_sysmmu_inactive(ips);
201 sysmmuconp = &s5p_sysmmu_cntlrs[ips]; 195 sysmmu_clk_disable(ips);
202 196 dev_dbg(dev, "%s is disabled.\n", sysmmu_ips_name[ips]);
203 if (sysmmuconp == NULL) { 197 } else {
204 printk(KERN_ERR "failed to get ip's sysmmu info\n"); 198 dev_dbg(dev, "%s is already disabled.\n", sysmmu_ips_name[ips]);
205 return 1;
206 } 199 }
200}
207 201
208 /* set Block MMU for flush TLB */ 202void s5p_sysmmu_tlb_invalidate(sysmmu_ips ips)
209 reg = __raw_readl(sysmmuconp->regs + S5P_MMU_CTRL); 203{
210 reg |= 0x1 << 1; 204 if (is_sysmmu_active(ips)) {
211 __raw_writel(reg, sysmmuconp->regs + S5P_MMU_CTRL); 205 sysmmu_block(ips);
212 206 __sysmmu_tlb_invalidate(ips);
213 /* flush all TLB entry */ 207 sysmmu_unblock(ips);
214 __raw_writel(0x1, sysmmuconp->regs + S5P_MMU_FLUSH); 208 } else {
215 209 dev_dbg(dev, "%s is disabled. "
216 /* set Un-block MMU after flush TLB */ 210 "Skipping invalidating TLB.\n", sysmmu_ips_name[ips]);
217 reg = __raw_readl(sysmmuconp->regs + S5P_MMU_CTRL); 211 }
218 reg &= ~(0x1 << 1);
219 __raw_writel(reg, sysmmuconp->regs + S5P_MMU_CTRL);
220
221 return 0;
222} 212}
223 213
224static int s5p_sysmmu_probe(struct platform_device *pdev) 214static int s5p_sysmmu_probe(struct platform_device *pdev)
225{ 215{
226 int i; 216 int i, ret;
227 int ret; 217 struct resource *res, *mem;
228 struct resource *res; 218
229 struct sysmmu_controller *sysmmuconp; 219 dev = &pdev->dev;
230 sysmmu_ips ips;
231 220
232 for (i = 0; i < S5P_SYSMMU_TOTAL_IPNUM; i++) { 221 for (i = 0; i < S5P_SYSMMU_TOTAL_IPNUM; i++) {
233 sysmmuconp = &s5p_sysmmu_cntlrs[i]; 222 int irq;
234 if (sysmmuconp == NULL) {
235 printk(KERN_ERR "failed to get ip's sysmmu info\n");
236 ret = -ENOENT;
237 goto err_res;
238 }
239 223
240 sysmmuconp->name = sysmmu_ips_name[i]; 224 sysmmu_clk_init(dev, i);
225 sysmmu_clk_disable(i);
241 226
242 res = platform_get_resource(pdev, IORESOURCE_MEM, i); 227 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
243 if (!res) { 228 if (!res) {
244 printk(KERN_ERR "failed to get sysmmu resource\n"); 229 dev_err(dev, "Failed to get the resource of %s.\n",
230 sysmmu_ips_name[i]);
245 ret = -ENODEV; 231 ret = -ENODEV;
246 goto err_res; 232 goto err_res;
247 } 233 }
248 234
249 sysmmuconp->mem = request_mem_region(res->start, 235 mem = request_mem_region(res->start,
250 ((res->end) - (res->start)) + 1, pdev->name); 236 ((res->end) - (res->start)) + 1, pdev->name);
251 if (!sysmmuconp->mem) { 237 if (!mem) {
252 pr_err("failed to request sysmmu memory region\n"); 238 dev_err(dev, "Failed to request the memory region of %s.\n",
239 sysmmu_ips_name[i]);
253 ret = -EBUSY; 240 ret = -EBUSY;
254 goto err_res; 241 goto err_res;
255 } 242 }
256 243
257 sysmmuconp->regs = ioremap(res->start, res->end - res->start + 1); 244 sysmmusfrs[i] = ioremap(res->start, res->end - res->start + 1);
258 if (!sysmmuconp->regs) { 245 if (!sysmmusfrs[i]) {
259 pr_err("failed to sysmmu ioremap\n"); 246 dev_err(dev, "Failed to ioremap() for %s.\n",
247 sysmmu_ips_name[i]);
260 ret = -ENXIO; 248 ret = -ENXIO;
261 goto err_reg; 249 goto err_reg;
262 } 250 }
263 251
264 sysmmuconp->irq = platform_get_irq(pdev, i); 252 irq = platform_get_irq(pdev, i);
265 if (sysmmuconp->irq <= 0) { 253 if (irq <= 0) {
266 pr_err("failed to get sysmmu irq resource\n"); 254 dev_err(dev, "Failed to get the IRQ resource of %s.\n",
255 sysmmu_ips_name[i]);
267 ret = -ENOENT; 256 ret = -ENOENT;
268 goto err_map; 257 goto err_map;
269 } 258 }
270 259
271 ret = request_irq(sysmmuconp->irq, s5p_sysmmu_irq, IRQF_DISABLED, pdev->name, sysmmuconp); 260 if (request_irq(irq, s5p_sysmmu_irq, IRQF_DISABLED,
272 if (ret) { 261 pdev->name, (void *)i)) {
273 pr_err("failed to request irq\n"); 262 dev_err(dev, "Failed to request IRQ for %s.\n",
263 sysmmu_ips_name[i]);
274 ret = -ENOENT; 264 ret = -ENOENT;
275 goto err_map; 265 goto err_map;
276 } 266 }
277
278 ips = (sysmmu_ips)i;
279
280 sysmmuconp->ips = ips;
281 } 267 }
282 268
283 return 0; 269 return 0;
284 270
285err_reg:
286 release_mem_region((resource_size_t)sysmmuconp->mem, (resource_size_t)((res->end) - (res->start) + 1));
287err_map: 271err_map:
288 iounmap(sysmmuconp->regs); 272 iounmap(sysmmusfrs[i]);
273err_reg:
274 release_mem_region(mem->start, resource_size(mem));
289err_res: 275err_res:
290 return ret; 276 return ret;
291} 277}
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index 32be05cf82a3..be72100b81b4 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -273,6 +273,19 @@ config SAMSUNG_DEV_KEYPAD
273 help 273 help
274 Compile in platform device definitions for keypad 274 Compile in platform device definitions for keypad
275 275
276config SAMSUNG_DEV_PWM
277 bool
278 default y if ARCH_S3C2410
279 help
280 Compile in platform device definition for PWM Timer
281
282config S3C24XX_PWM
283 bool "PWM device support"
284 select HAVE_PWM
285 help
286 Support for exporting the PWM timer blocks via the pwm device
287 system
288
276# DMA 289# DMA
277 290
278config S3C_DMA 291config S3C_DMA
diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile
index 29932f88a8d6..e9de58a2e294 100644
--- a/arch/arm/plat-samsung/Makefile
+++ b/arch/arm/plat-samsung/Makefile
@@ -59,6 +59,7 @@ obj-$(CONFIG_SAMSUNG_DEV_ADC) += dev-adc.o
59obj-$(CONFIG_SAMSUNG_DEV_IDE) += dev-ide.o 59obj-$(CONFIG_SAMSUNG_DEV_IDE) += dev-ide.o
60obj-$(CONFIG_SAMSUNG_DEV_TS) += dev-ts.o 60obj-$(CONFIG_SAMSUNG_DEV_TS) += dev-ts.o
61obj-$(CONFIG_SAMSUNG_DEV_KEYPAD) += dev-keypad.o 61obj-$(CONFIG_SAMSUNG_DEV_KEYPAD) += dev-keypad.o
62obj-$(CONFIG_SAMSUNG_DEV_PWM) += dev-pwm.o
62 63
63# DMA support 64# DMA support
64 65
diff --git a/arch/arm/plat-samsung/dev-pwm.c b/arch/arm/plat-samsung/dev-pwm.c
new file mode 100644
index 000000000000..dab47b0e1900
--- /dev/null
+++ b/arch/arm/plat-samsung/dev-pwm.c
@@ -0,0 +1,53 @@
1/* linux/arch/arm/plat-samsung/dev-pwm.c
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Copyright (c) 2007 Ben Dooks
7 * Copyright (c) 2008 Simtec Electronics
8 * Ben Dooks <ben@simtec.co.uk>, <ben-linux@fluff.org>
9 *
10 * S3C series device definition for the PWM timer
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17#include <linux/kernel.h>
18#include <linux/platform_device.h>
19
20#include <mach/irqs.h>
21
22#include <plat/devs.h>
23
24#define TIMER_RESOURCE_SIZE (1)
25
26#define TIMER_RESOURCE(_tmr, _irq) \
27 (struct resource [TIMER_RESOURCE_SIZE]) { \
28 [0] = { \
29 .start = _irq, \
30 .end = _irq, \
31 .flags = IORESOURCE_IRQ \
32 } \
33 }
34
35#define DEFINE_S3C_TIMER(_tmr_no, _irq) \
36 .name = "s3c24xx-pwm", \
37 .id = _tmr_no, \
38 .num_resources = TIMER_RESOURCE_SIZE, \
39 .resource = TIMER_RESOURCE(_tmr_no, _irq), \
40
41/*
42 * since we already have an static mapping for the timer,
43 * we do not bother setting any IO resource for the base.
44 */
45
46struct platform_device s3c_device_timer[] = {
47 [0] = { DEFINE_S3C_TIMER(0, IRQ_TIMER0) },
48 [1] = { DEFINE_S3C_TIMER(1, IRQ_TIMER1) },
49 [2] = { DEFINE_S3C_TIMER(2, IRQ_TIMER2) },
50 [3] = { DEFINE_S3C_TIMER(3, IRQ_TIMER3) },
51 [4] = { DEFINE_S3C_TIMER(4, IRQ_TIMER4) },
52};
53EXPORT_SYMBOL(s3c_device_timer);
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index 9addb3dfb4bc..cedfff51c82b 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -82,6 +82,7 @@ extern struct sysdev_class s3c64xx_sysclass;
82extern struct sysdev_class s5p64x0_sysclass; 82extern struct sysdev_class s5p64x0_sysclass;
83extern struct sysdev_class s5p6442_sysclass; 83extern struct sysdev_class s5p6442_sysclass;
84extern struct sysdev_class s5pv210_sysclass; 84extern struct sysdev_class s5pv210_sysclass;
85extern struct sysdev_class exynos4_sysclass;
85 86
86extern void (*s5pc1xx_idle)(void); 87extern void (*s5pc1xx_idle)(void);
87 88
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h
index b4d208b42957..f0da6b70fba4 100644
--- a/arch/arm/plat-samsung/include/plat/devs.h
+++ b/arch/arm/plat-samsung/include/plat/devs.h
@@ -1,5 +1,8 @@
1/* arch/arm/plat-samsung/include/plat/devs.h 1/* arch/arm/plat-samsung/include/plat/devs.h
2 * 2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
3 * Copyright (c) 2004 Simtec Electronics 6 * Copyright (c) 2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk> 7 * Ben Dooks <ben@simtec.co.uk>
5 * 8 *
@@ -96,15 +99,16 @@ extern struct platform_device s5pv210_device_iis1;
96extern struct platform_device s5pv210_device_iis2; 99extern struct platform_device s5pv210_device_iis2;
97extern struct platform_device s5pv210_device_spdif; 100extern struct platform_device s5pv210_device_spdif;
98 101
99extern struct platform_device s5pv310_device_ac97; 102extern struct platform_device exynos4_device_ac97;
100extern struct platform_device s5pv310_device_pcm0; 103extern struct platform_device exynos4_device_pcm0;
101extern struct platform_device s5pv310_device_pcm1; 104extern struct platform_device exynos4_device_pcm1;
102extern struct platform_device s5pv310_device_pcm2; 105extern struct platform_device exynos4_device_pcm2;
103extern struct platform_device s5pv310_device_i2s0; 106extern struct platform_device exynos4_device_i2s0;
104extern struct platform_device s5pv310_device_i2s1; 107extern struct platform_device exynos4_device_i2s1;
105extern struct platform_device s5pv310_device_i2s2; 108extern struct platform_device exynos4_device_i2s2;
106extern struct platform_device s5pv310_device_spdif; 109extern struct platform_device exynos4_device_spdif;
107extern struct platform_device s5pv310_device_pd[]; 110extern struct platform_device exynos4_device_pd[];
111extern struct platform_device exynos4_device_ahci;
108 112
109extern struct platform_device s5p6442_device_pcm0; 113extern struct platform_device s5p6442_device_pcm0;
110extern struct platform_device s5p6442_device_pcm1; 114extern struct platform_device s5p6442_device_pcm1;
@@ -133,11 +137,12 @@ extern struct platform_device samsung_device_keypad;
133extern struct platform_device s5p_device_fimc0; 137extern struct platform_device s5p_device_fimc0;
134extern struct platform_device s5p_device_fimc1; 138extern struct platform_device s5p_device_fimc1;
135extern struct platform_device s5p_device_fimc2; 139extern struct platform_device s5p_device_fimc2;
140extern struct platform_device s5p_device_fimc3;
136 141
137extern struct platform_device s5p_device_mipi_csis0; 142extern struct platform_device s5p_device_mipi_csis0;
138extern struct platform_device s5p_device_mipi_csis1; 143extern struct platform_device s5p_device_mipi_csis1;
139 144
140extern struct platform_device s5pv310_device_sysmmu; 145extern struct platform_device exynos4_device_sysmmu;
141 146
142/* s3c2440 specific devices */ 147/* s3c2440 specific devices */
143 148
diff --git a/arch/arm/plat-samsung/include/plat/fimc-core.h b/arch/arm/plat-samsung/include/plat/fimc-core.h
index 81a3bfeeccad..945a99d59563 100644
--- a/arch/arm/plat-samsung/include/plat/fimc-core.h
+++ b/arch/arm/plat-samsung/include/plat/fimc-core.h
@@ -38,6 +38,11 @@ static inline void s3c_fimc_setname(int id, char *name)
38 s5p_device_fimc2.name = name; 38 s5p_device_fimc2.name = name;
39 break; 39 break;
40#endif 40#endif
41#ifdef CONFIG_S5P_DEV_FIMC3
42 case 3:
43 s5p_device_fimc3.name = name;
44 break;
45#endif
41 } 46 }
42} 47}
43 48
diff --git a/arch/arm/plat-samsung/include/plat/gpio-cfg.h b/arch/arm/plat-samsung/include/plat/gpio-cfg.h
index e4b5cf126fa9..5e04fa6eda74 100644
--- a/arch/arm/plat-samsung/include/plat/gpio-cfg.h
+++ b/arch/arm/plat-samsung/include/plat/gpio-cfg.h
@@ -225,4 +225,20 @@ extern int s5p_gpio_set_drvstr(unsigned int pin, s5p_gpio_drvstr_t drvstr);
225 */ 225 */
226extern int s5p_register_gpio_interrupt(int pin); 226extern int s5p_register_gpio_interrupt(int pin);
227 227
228/** s5p_register_gpioint_bank() - add gpio bank for further gpio interrupt
229 * registration (see s5p_register_gpio_interrupt function)
230 * @chain_irq: chained irq number for the gpio int handler for this bank
231 * @start: start gpio group number of this bank
232 * @nr_groups: number of gpio groups handled by this bank
233 *
234 * This functions registers initial information about gpio banks that
235 * can be later used by the s5p_register_gpio_interrupt() function to
236 * enable support for gpio interrupt for particular gpio group.
237 */
238#ifdef CONFIG_S5P_GPIO_INT
239extern int s5p_register_gpioint_bank(int chain_irq, int start, int nr_groups);
240#else
241#define s5p_register_gpioint_bank(chain_irq, start, nr_groups) do { } while (0)
242#endif
243
228#endif /* __PLAT_GPIO_CFG_H */ 244#endif /* __PLAT_GPIO_CFG_H */
diff --git a/arch/arm/plat-samsung/include/plat/pd.h b/arch/arm/plat-samsung/include/plat/pd.h
index 5f0ad85783db..abb4bc32716a 100644
--- a/arch/arm/plat-samsung/include/plat/pd.h
+++ b/arch/arm/plat-samsung/include/plat/pd.h
@@ -1,6 +1,6 @@
1/* linux/arch/arm/plat-samsung/include/plat/pd.h 1/* linux/arch/arm/plat-samsung/include/plat/pd.h
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com 4 * http://www.samsung.com
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
@@ -17,7 +17,7 @@ struct samsung_pd_info {
17 void __iomem *base; 17 void __iomem *base;
18}; 18};
19 19
20enum s5pv310_pd_block { 20enum exynos4_pd_block {
21 PD_MFC, 21 PD_MFC,
22 PD_G3D, 22 PD_G3D,
23 PD_LCD0, 23 PD_LCD0,
diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h
index 5a41a0b69eec..b0bdf16549d5 100644
--- a/arch/arm/plat-samsung/include/plat/sdhci.h
+++ b/arch/arm/plat-samsung/include/plat/sdhci.h
@@ -1,4 +1,7 @@
1/* linux/arch/arm/plat-s3c/include/plat/sdhci.h 1/* linux/arch/arm/plat-samsung/include/plat/sdhci.h
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
2 * 5 *
3 * Copyright 2008 Openmoko, Inc. 6 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics 7 * Copyright 2008 Simtec Electronics
@@ -119,10 +122,10 @@ extern void s5pv210_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
119extern void s5pv210_setup_sdhci1_cfg_gpio(struct platform_device *, int w); 122extern void s5pv210_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
120extern void s5pv210_setup_sdhci2_cfg_gpio(struct platform_device *, int w); 123extern void s5pv210_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
121extern void s5pv210_setup_sdhci3_cfg_gpio(struct platform_device *, int w); 124extern void s5pv210_setup_sdhci3_cfg_gpio(struct platform_device *, int w);
122extern void s5pv310_setup_sdhci0_cfg_gpio(struct platform_device *, int w); 125extern void exynos4_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
123extern void s5pv310_setup_sdhci1_cfg_gpio(struct platform_device *, int w); 126extern void exynos4_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
124extern void s5pv310_setup_sdhci2_cfg_gpio(struct platform_device *, int w); 127extern void exynos4_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
125extern void s5pv310_setup_sdhci3_cfg_gpio(struct platform_device *, int w); 128extern void exynos4_setup_sdhci3_cfg_gpio(struct platform_device *, int w);
126 129
127/* S3C2416 SDHCI setup */ 130/* S3C2416 SDHCI setup */
128 131
@@ -334,57 +337,57 @@ static inline void s5pv210_default_sdhci3(void) { }
334 337
335#endif /* CONFIG_S5PV210_SETUP_SDHCI */ 338#endif /* CONFIG_S5PV210_SETUP_SDHCI */
336 339
337/* S5PV310 SDHCI setup */ 340/* EXYNOS4 SDHCI setup */
338#ifdef CONFIG_S5PV310_SETUP_SDHCI 341#ifdef CONFIG_EXYNOS4_SETUP_SDHCI
339extern char *s5pv310_hsmmc_clksrcs[4]; 342extern char *exynos4_hsmmc_clksrcs[4];
340 343
341extern void s5pv310_setup_sdhci_cfg_card(struct platform_device *dev, 344extern void exynos4_setup_sdhci_cfg_card(struct platform_device *dev,
342 void __iomem *r, 345 void __iomem *r,
343 struct mmc_ios *ios, 346 struct mmc_ios *ios,
344 struct mmc_card *card); 347 struct mmc_card *card);
345 348
346static inline void s5pv310_default_sdhci0(void) 349static inline void exynos4_default_sdhci0(void)
347{ 350{
348#ifdef CONFIG_S3C_DEV_HSMMC 351#ifdef CONFIG_S3C_DEV_HSMMC
349 s3c_hsmmc0_def_platdata.clocks = s5pv310_hsmmc_clksrcs; 352 s3c_hsmmc0_def_platdata.clocks = exynos4_hsmmc_clksrcs;
350 s3c_hsmmc0_def_platdata.cfg_gpio = s5pv310_setup_sdhci0_cfg_gpio; 353 s3c_hsmmc0_def_platdata.cfg_gpio = exynos4_setup_sdhci0_cfg_gpio;
351 s3c_hsmmc0_def_platdata.cfg_card = s5pv310_setup_sdhci_cfg_card; 354 s3c_hsmmc0_def_platdata.cfg_card = exynos4_setup_sdhci_cfg_card;
352#endif 355#endif
353} 356}
354 357
355static inline void s5pv310_default_sdhci1(void) 358static inline void exynos4_default_sdhci1(void)
356{ 359{
357#ifdef CONFIG_S3C_DEV_HSMMC1 360#ifdef CONFIG_S3C_DEV_HSMMC1
358 s3c_hsmmc1_def_platdata.clocks = s5pv310_hsmmc_clksrcs; 361 s3c_hsmmc1_def_platdata.clocks = exynos4_hsmmc_clksrcs;
359 s3c_hsmmc1_def_platdata.cfg_gpio = s5pv310_setup_sdhci1_cfg_gpio; 362 s3c_hsmmc1_def_platdata.cfg_gpio = exynos4_setup_sdhci1_cfg_gpio;
360 s3c_hsmmc1_def_platdata.cfg_card = s5pv310_setup_sdhci_cfg_card; 363 s3c_hsmmc1_def_platdata.cfg_card = exynos4_setup_sdhci_cfg_card;
361#endif 364#endif
362} 365}
363 366
364static inline void s5pv310_default_sdhci2(void) 367static inline void exynos4_default_sdhci2(void)
365{ 368{
366#ifdef CONFIG_S3C_DEV_HSMMC2 369#ifdef CONFIG_S3C_DEV_HSMMC2
367 s3c_hsmmc2_def_platdata.clocks = s5pv310_hsmmc_clksrcs; 370 s3c_hsmmc2_def_platdata.clocks = exynos4_hsmmc_clksrcs;
368 s3c_hsmmc2_def_platdata.cfg_gpio = s5pv310_setup_sdhci2_cfg_gpio; 371 s3c_hsmmc2_def_platdata.cfg_gpio = exynos4_setup_sdhci2_cfg_gpio;
369 s3c_hsmmc2_def_platdata.cfg_card = s5pv310_setup_sdhci_cfg_card; 372 s3c_hsmmc2_def_platdata.cfg_card = exynos4_setup_sdhci_cfg_card;
370#endif 373#endif
371} 374}
372 375
373static inline void s5pv310_default_sdhci3(void) 376static inline void exynos4_default_sdhci3(void)
374{ 377{
375#ifdef CONFIG_S3C_DEV_HSMMC3 378#ifdef CONFIG_S3C_DEV_HSMMC3
376 s3c_hsmmc3_def_platdata.clocks = s5pv310_hsmmc_clksrcs; 379 s3c_hsmmc3_def_platdata.clocks = exynos4_hsmmc_clksrcs;
377 s3c_hsmmc3_def_platdata.cfg_gpio = s5pv310_setup_sdhci3_cfg_gpio; 380 s3c_hsmmc3_def_platdata.cfg_gpio = exynos4_setup_sdhci3_cfg_gpio;
378 s3c_hsmmc3_def_platdata.cfg_card = s5pv310_setup_sdhci_cfg_card; 381 s3c_hsmmc3_def_platdata.cfg_card = exynos4_setup_sdhci_cfg_card;
379#endif 382#endif
380} 383}
381 384
382#else 385#else
383static inline void s5pv310_default_sdhci0(void) { } 386static inline void exynos4_default_sdhci0(void) { }
384static inline void s5pv310_default_sdhci1(void) { } 387static inline void exynos4_default_sdhci1(void) { }
385static inline void s5pv310_default_sdhci2(void) { } 388static inline void exynos4_default_sdhci2(void) { }
386static inline void s5pv310_default_sdhci3(void) { } 389static inline void exynos4_default_sdhci3(void) { }
387 390
388#endif /* CONFIG_S5PV310_SETUP_SDHCI */ 391#endif /* CONFIG_EXYNOS4_SETUP_SDHCI */
389 392
390#endif /* __PLAT_S3C_SDHCI_H */ 393#endif /* __PLAT_S3C_SDHCI_H */
diff --git a/arch/arm/plat-samsung/pwm.c b/arch/arm/plat-samsung/pwm.c
index 2eeb49fa056d..f37457c52064 100644
--- a/arch/arm/plat-samsung/pwm.c
+++ b/arch/arm/plat-samsung/pwm.c
@@ -20,10 +20,8 @@
20#include <linux/io.h> 20#include <linux/io.h>
21#include <linux/pwm.h> 21#include <linux/pwm.h>
22 22
23#include <mach/irqs.h>
24#include <mach/map.h> 23#include <mach/map.h>
25 24
26#include <plat/devs.h>
27#include <plat/regs-timer.h> 25#include <plat/regs-timer.h>
28 26
29struct pwm_device { 27struct pwm_device {
@@ -47,37 +45,6 @@ struct pwm_device {
47 45
48static struct clk *clk_scaler[2]; 46static struct clk *clk_scaler[2];
49 47
50/* Standard setup for a timer block. */
51
52#define TIMER_RESOURCE_SIZE (1)
53
54#define TIMER_RESOURCE(_tmr, _irq) \
55 (struct resource [TIMER_RESOURCE_SIZE]) { \
56 [0] = { \
57 .start = _irq, \
58 .end = _irq, \
59 .flags = IORESOURCE_IRQ \
60 } \
61 }
62
63#define DEFINE_S3C_TIMER(_tmr_no, _irq) \
64 .name = "s3c24xx-pwm", \
65 .id = _tmr_no, \
66 .num_resources = TIMER_RESOURCE_SIZE, \
67 .resource = TIMER_RESOURCE(_tmr_no, _irq), \
68
69/* since we already have an static mapping for the timer, we do not
70 * bother setting any IO resource for the base.
71 */
72
73struct platform_device s3c_device_timer[] = {
74 [0] = { DEFINE_S3C_TIMER(0, IRQ_TIMER0) },
75 [1] = { DEFINE_S3C_TIMER(1, IRQ_TIMER1) },
76 [2] = { DEFINE_S3C_TIMER(2, IRQ_TIMER2) },
77 [3] = { DEFINE_S3C_TIMER(3, IRQ_TIMER3) },
78 [4] = { DEFINE_S3C_TIMER(4, IRQ_TIMER4) },
79};
80
81static inline int pwm_is_tdiv(struct pwm_device *pwm) 48static inline int pwm_is_tdiv(struct pwm_device *pwm)
82{ 49{
83 return clk_get_parent(pwm->clk) == pwm->clk_div; 50 return clk_get_parent(pwm->clk) == pwm->clk_div;