diff options
Diffstat (limited to 'arch/arm')
406 files changed, 8497 insertions, 13896 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 26f7e3b4373c..1fd9bcd25b4d 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig | |||
| @@ -273,7 +273,7 @@ config ARCH_INTEGRATOR | |||
| 273 | select ARM_AMBA | 273 | select ARM_AMBA |
| 274 | select ARCH_HAS_CPUFREQ | 274 | select ARCH_HAS_CPUFREQ |
| 275 | select COMMON_CLK | 275 | select COMMON_CLK |
| 276 | select CLK_VERSATILE | 276 | select COMMON_CLK_VERSATILE |
| 277 | select HAVE_TCM | 277 | select HAVE_TCM |
| 278 | select ICST | 278 | select ICST |
| 279 | select GENERIC_CLOCKEVENTS | 279 | select GENERIC_CLOCKEVENTS |
| @@ -289,13 +289,12 @@ config ARCH_INTEGRATOR | |||
| 289 | config ARCH_REALVIEW | 289 | config ARCH_REALVIEW |
| 290 | bool "ARM Ltd. RealView family" | 290 | bool "ARM Ltd. RealView family" |
| 291 | select ARM_AMBA | 291 | select ARM_AMBA |
| 292 | select CLKDEV_LOOKUP | 292 | select COMMON_CLK |
| 293 | select HAVE_MACH_CLKDEV | 293 | select COMMON_CLK_VERSATILE |
| 294 | select ICST | 294 | select ICST |
| 295 | select GENERIC_CLOCKEVENTS | 295 | select GENERIC_CLOCKEVENTS |
| 296 | select ARCH_WANT_OPTIONAL_GPIOLIB | 296 | select ARCH_WANT_OPTIONAL_GPIOLIB |
| 297 | select PLAT_VERSATILE | 297 | select PLAT_VERSATILE |
| 298 | select PLAT_VERSATILE_CLOCK | ||
| 299 | select PLAT_VERSATILE_CLCD | 298 | select PLAT_VERSATILE_CLCD |
| 300 | select ARM_TIMER_SP804 | 299 | select ARM_TIMER_SP804 |
| 301 | select GPIO_PL061 if GPIOLIB | 300 | select GPIO_PL061 if GPIOLIB |
| @@ -413,7 +412,7 @@ config ARCH_PRIMA2 | |||
| 413 | select NO_IOPORT | 412 | select NO_IOPORT |
| 414 | select ARCH_REQUIRE_GPIOLIB | 413 | select ARCH_REQUIRE_GPIOLIB |
| 415 | select GENERIC_CLOCKEVENTS | 414 | select GENERIC_CLOCKEVENTS |
| 416 | select CLKDEV_LOOKUP | 415 | select COMMON_CLK |
| 417 | select GENERIC_IRQ_CHIP | 416 | select GENERIC_IRQ_CHIP |
| 418 | select MIGHT_HAVE_CACHE_L2X0 | 417 | select MIGHT_HAVE_CACHE_L2X0 |
| 419 | select PINCTRL | 418 | select PINCTRL |
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index f15f82bf3a50..e968a52e4881 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug | |||
| @@ -356,15 +356,15 @@ choice | |||
| 356 | is nothing connected to read from the DCC. | 356 | is nothing connected to read from the DCC. |
| 357 | 357 | ||
| 358 | config DEBUG_SEMIHOSTING | 358 | config DEBUG_SEMIHOSTING |
| 359 | bool "Kernel low-level debug output via semihosting I" | 359 | bool "Kernel low-level debug output via semihosting I/O" |
| 360 | help | 360 | help |
| 361 | Semihosting enables code running on an ARM target to use | 361 | Semihosting enables code running on an ARM target to use |
| 362 | the I/O facilities on a host debugger/emulator through a | 362 | the I/O facilities on a host debugger/emulator through a |
| 363 | simple SVC calls. The host debugger or emulator must have | 363 | simple SVC call. The host debugger or emulator must have |
| 364 | semihosting enabled for the special svc call to be trapped | 364 | semihosting enabled for the special svc call to be trapped |
| 365 | otherwise the kernel will crash. | 365 | otherwise the kernel will crash. |
| 366 | 366 | ||
| 367 | This is known to work with OpenOCD, as wellas | 367 | This is known to work with OpenOCD, as well as |
| 368 | ARM's Fast Models, or any other controlling environment | 368 | ARM's Fast Models, or any other controlling environment |
| 369 | that implements semihosting. | 369 | that implements semihosting. |
| 370 | 370 | ||
diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 30eae87ead6d..a051dfbdd7db 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile | |||
| @@ -284,10 +284,10 @@ zImage Image xipImage bootpImage uImage: vmlinux | |||
| 284 | zinstall uinstall install: vmlinux | 284 | zinstall uinstall install: vmlinux |
| 285 | $(Q)$(MAKE) $(build)=$(boot) MACHINE=$(MACHINE) $@ | 285 | $(Q)$(MAKE) $(build)=$(boot) MACHINE=$(MACHINE) $@ |
| 286 | 286 | ||
| 287 | %.dtb: | 287 | %.dtb: scripts |
| 288 | $(Q)$(MAKE) $(build)=$(boot) MACHINE=$(MACHINE) $(boot)/$@ | 288 | $(Q)$(MAKE) $(build)=$(boot) MACHINE=$(MACHINE) $(boot)/$@ |
| 289 | 289 | ||
| 290 | dtbs: | 290 | dtbs: scripts |
| 291 | $(Q)$(MAKE) $(build)=$(boot) MACHINE=$(MACHINE) $(boot)/$@ | 291 | $(Q)$(MAKE) $(build)=$(boot) MACHINE=$(MACHINE) $(boot)/$@ |
| 292 | 292 | ||
| 293 | # We use MRPROPER_FILES and CLEAN_FILES now | 293 | # We use MRPROPER_FILES and CLEAN_FILES now |
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index b8c64b80bafc..81769c1341fa 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S | |||
| @@ -659,10 +659,14 @@ __armv7_mmu_cache_on: | |||
| 659 | #ifdef CONFIG_CPU_ENDIAN_BE8 | 659 | #ifdef CONFIG_CPU_ENDIAN_BE8 |
| 660 | orr r0, r0, #1 << 25 @ big-endian page tables | 660 | orr r0, r0, #1 << 25 @ big-endian page tables |
| 661 | #endif | 661 | #endif |
| 662 | mrcne p15, 0, r6, c2, c0, 2 @ read ttb control reg | ||
| 662 | orrne r0, r0, #1 @ MMU enabled | 663 | orrne r0, r0, #1 @ MMU enabled |
| 663 | movne r1, #0xfffffffd @ domain 0 = client | 664 | movne r1, #0xfffffffd @ domain 0 = client |
| 665 | bic r6, r6, #1 << 31 @ 32-bit translation system | ||
| 666 | bic r6, r6, #3 << 0 @ use only ttbr0 | ||
| 664 | mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer | 667 | mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer |
| 665 | mcrne p15, 0, r1, c3, c0, 0 @ load domain access control | 668 | mcrne p15, 0, r1, c3, c0, 0 @ load domain access control |
| 669 | mcrne p15, 0, r6, c2, c0, 2 @ load ttb control | ||
| 666 | #endif | 670 | #endif |
| 667 | mcr p15, 0, r0, c7, c5, 4 @ ISB | 671 | mcr p15, 0, r0, c7, c5, 4 @ ISB |
| 668 | mcr p15, 0, r0, c1, c0, 0 @ load control register | 672 | mcr p15, 0, r0, c1, c0, 0 @ load control register |
diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts index a9af4db7234c..c634f87e230e 100644 --- a/arch/arm/boot/dts/am335x-bone.dts +++ b/arch/arm/boot/dts/am335x-bone.dts | |||
| @@ -17,4 +17,64 @@ | |||
| 17 | device_type = "memory"; | 17 | device_type = "memory"; |
| 18 | reg = <0x80000000 0x10000000>; /* 256 MB */ | 18 | reg = <0x80000000 0x10000000>; /* 256 MB */ |
| 19 | }; | 19 | }; |
| 20 | |||
| 21 | ocp { | ||
| 22 | uart1: serial@44e09000 { | ||
| 23 | status = "okay"; | ||
| 24 | }; | ||
| 25 | |||
| 26 | i2c1: i2c@44e0b000 { | ||
| 27 | status = "okay"; | ||
| 28 | clock-frequency = <400000>; | ||
| 29 | |||
| 30 | tps: tps@24 { | ||
| 31 | reg = <0x24>; | ||
| 32 | }; | ||
| 33 | |||
| 34 | }; | ||
| 35 | }; | ||
| 36 | }; | ||
| 37 | |||
| 38 | /include/ "tps65217.dtsi" | ||
| 39 | |||
| 40 | &tps { | ||
| 41 | regulators { | ||
| 42 | dcdc1_reg: regulator@0 { | ||
| 43 | regulator-always-on; | ||
| 44 | }; | ||
| 45 | |||
| 46 | dcdc2_reg: regulator@1 { | ||
| 47 | /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ | ||
| 48 | regulator-name = "vdd_mpu"; | ||
| 49 | regulator-min-microvolt = <925000>; | ||
| 50 | regulator-max-microvolt = <1325000>; | ||
| 51 | regulator-boot-on; | ||
| 52 | regulator-always-on; | ||
| 53 | }; | ||
| 54 | |||
| 55 | dcdc3_reg: regulator@2 { | ||
| 56 | /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ | ||
| 57 | regulator-name = "vdd_core"; | ||
| 58 | regulator-min-microvolt = <925000>; | ||
| 59 | regulator-max-microvolt = <1150000>; | ||
| 60 | regulator-boot-on; | ||
| 61 | regulator-always-on; | ||
| 62 | }; | ||
| 63 | |||
| 64 | ldo1_reg: regulator@3 { | ||
| 65 | regulator-always-on; | ||
| 66 | }; | ||
| 67 | |||
| 68 | ldo2_reg: regulator@4 { | ||
| 69 | regulator-always-on; | ||
| 70 | }; | ||
| 71 | |||
| 72 | ldo3_reg: regulator@5 { | ||
| 73 | regulator-always-on; | ||
| 74 | }; | ||
| 75 | |||
| 76 | ldo4_reg: regulator@6 { | ||
| 77 | regulator-always-on; | ||
| 78 | }; | ||
| 79 | }; | ||
| 20 | }; | 80 | }; |
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts index d6a97d9eff72..185d6325a458 100644 --- a/arch/arm/boot/dts/am335x-evm.dts +++ b/arch/arm/boot/dts/am335x-evm.dts | |||
| @@ -17,4 +17,104 @@ | |||
| 17 | device_type = "memory"; | 17 | device_type = "memory"; |
| 18 | reg = <0x80000000 0x10000000>; /* 256 MB */ | 18 | reg = <0x80000000 0x10000000>; /* 256 MB */ |
| 19 | }; | 19 | }; |
| 20 | |||
| 21 | ocp { | ||
| 22 | uart1: serial@44e09000 { | ||
| 23 | status = "okay"; | ||
| 24 | }; | ||
| 25 | |||
| 26 | i2c1: i2c@44e0b000 { | ||
| 27 | status = "okay"; | ||
| 28 | clock-frequency = <400000>; | ||
| 29 | |||
| 30 | tps: tps@2d { | ||
| 31 | reg = <0x2d>; | ||
| 32 | }; | ||
| 33 | }; | ||
| 34 | }; | ||
| 35 | |||
| 36 | vbat: fixedregulator@0 { | ||
| 37 | compatible = "regulator-fixed"; | ||
| 38 | regulator-name = "vbat"; | ||
| 39 | regulator-min-microvolt = <5000000>; | ||
| 40 | regulator-max-microvolt = <5000000>; | ||
| 41 | regulator-boot-on; | ||
| 42 | }; | ||
| 43 | }; | ||
| 44 | |||
| 45 | /include/ "tps65910.dtsi" | ||
| 46 | |||
| 47 | &tps { | ||
| 48 | vcc1-supply = <&vbat>; | ||
| 49 | vcc2-supply = <&vbat>; | ||
| 50 | vcc3-supply = <&vbat>; | ||
| 51 | vcc4-supply = <&vbat>; | ||
| 52 | vcc5-supply = <&vbat>; | ||
| 53 | vcc6-supply = <&vbat>; | ||
| 54 | vcc7-supply = <&vbat>; | ||
| 55 | vccio-supply = <&vbat>; | ||
| 56 | |||
| 57 | regulators { | ||
| 58 | vrtc_reg: regulator@0 { | ||
| 59 | regulator-always-on; | ||
| 60 | }; | ||
| 61 | |||
| 62 | vio_reg: regulator@1 { | ||
| 63 | regulator-always-on; | ||
| 64 | }; | ||
| 65 | |||
| 66 | vdd1_reg: regulator@2 { | ||
| 67 | /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ | ||
| 68 | regulator-name = "vdd_mpu"; | ||
| 69 | regulator-min-microvolt = <912500>; | ||
| 70 | regulator-max-microvolt = <1312500>; | ||
| 71 | regulator-boot-on; | ||
| 72 | regulator-always-on; | ||
| 73 | }; | ||
| 74 | |||
| 75 | vdd2_reg: regulator@3 { | ||
| 76 | /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ | ||
| 77 | regulator-name = "vdd_core"; | ||
| 78 | regulator-min-microvolt = <912500>; | ||
| 79 | regulator-max-microvolt = <1150000>; | ||
| 80 | regulator-boot-on; | ||
| 81 | regulator-always-on; | ||
| 82 | }; | ||
| 83 | |||
| 84 | vdd3_reg: regulator@4 { | ||
| 85 | regulator-always-on; | ||
| 86 | }; | ||
| 87 | |||
| 88 | vdig1_reg: regulator@5 { | ||
| 89 | regulator-always-on; | ||
| 90 | }; | ||
| 91 | |||
| 92 | vdig2_reg: regulator@6 { | ||
| 93 | regulator-always-on; | ||
| 94 | }; | ||
| 95 | |||
| 96 | vpll_reg: regulator@7 { | ||
| 97 | regulator-always-on; | ||
| 98 | }; | ||
| 99 | |||
| 100 | vdac_reg: regulator@8 { | ||
| 101 | regulator-always-on; | ||
| 102 | }; | ||
| 103 | |||
| 104 | vaux1_reg: regulator@9 { | ||
| 105 | regulator-always-on; | ||
| 106 | }; | ||
| 107 | |||
| 108 | vaux2_reg: regulator@10 { | ||
| 109 | regulator-always-on; | ||
| 110 | }; | ||
| 111 | |||
| 112 | vaux33_reg: regulator@11 { | ||
| 113 | regulator-always-on; | ||
| 114 | }; | ||
| 115 | |||
| 116 | vmmc_reg: regulator@12 { | ||
| 117 | regulator-always-on; | ||
| 118 | }; | ||
| 119 | }; | ||
| 20 | }; | 120 | }; |
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index bd0cff3f808c..bb31bff01998 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi | |||
| @@ -69,95 +69,146 @@ | |||
| 69 | #gpio-cells = <2>; | 69 | #gpio-cells = <2>; |
| 70 | interrupt-controller; | 70 | interrupt-controller; |
| 71 | #interrupt-cells = <1>; | 71 | #interrupt-cells = <1>; |
| 72 | reg = <0x44e07000 0x1000>; | ||
| 73 | interrupt-parent = <&intc>; | ||
| 74 | interrupts = <96>; | ||
| 72 | }; | 75 | }; |
| 73 | 76 | ||
| 74 | gpio2: gpio@4804C000 { | 77 | gpio2: gpio@4804c000 { |
| 75 | compatible = "ti,omap4-gpio"; | 78 | compatible = "ti,omap4-gpio"; |
| 76 | ti,hwmods = "gpio2"; | 79 | ti,hwmods = "gpio2"; |
| 77 | gpio-controller; | 80 | gpio-controller; |
| 78 | #gpio-cells = <2>; | 81 | #gpio-cells = <2>; |
| 79 | interrupt-controller; | 82 | interrupt-controller; |
| 80 | #interrupt-cells = <1>; | 83 | #interrupt-cells = <1>; |
| 84 | reg = <0x4804c000 0x1000>; | ||
| 85 | interrupt-parent = <&intc>; | ||
| 86 | interrupts = <98>; | ||
| 81 | }; | 87 | }; |
| 82 | 88 | ||
| 83 | gpio3: gpio@481AC000 { | 89 | gpio3: gpio@481ac000 { |
| 84 | compatible = "ti,omap4-gpio"; | 90 | compatible = "ti,omap4-gpio"; |
| 85 | ti,hwmods = "gpio3"; | 91 | ti,hwmods = "gpio3"; |
| 86 | gpio-controller; | 92 | gpio-controller; |
| 87 | #gpio-cells = <2>; | 93 | #gpio-cells = <2>; |
| 88 | interrupt-controller; | 94 | interrupt-controller; |
| 89 | #interrupt-cells = <1>; | 95 | #interrupt-cells = <1>; |
| 96 | reg = <0x481ac000 0x1000>; | ||
| 97 | interrupt-parent = <&intc>; | ||
| 98 | interrupts = <32>; | ||
| 90 | }; | 99 | }; |
| 91 | 100 | ||
| 92 | gpio4: gpio@481AE000 { | 101 | gpio4: gpio@481ae000 { |
| 93 | compatible = "ti,omap4-gpio"; | 102 | compatible = "ti,omap4-gpio"; |
| 94 | ti,hwmods = "gpio4"; | 103 | ti,hwmods = "gpio4"; |
| 95 | gpio-controller; | 104 | gpio-controller; |
| 96 | #gpio-cells = <2>; | 105 | #gpio-cells = <2>; |
| 97 | interrupt-controller; | 106 | interrupt-controller; |
| 98 | #interrupt-cells = <1>; | 107 | #interrupt-cells = <1>; |
| 108 | reg = <0x481ae000 0x1000>; | ||
| 109 | interrupt-parent = <&intc>; | ||
| 110 | interrupts = <62>; | ||
| 99 | }; | 111 | }; |
| 100 | 112 | ||
| 101 | uart1: serial@44E09000 { | 113 | uart1: serial@44e09000 { |
| 102 | compatible = "ti,omap3-uart"; | 114 | compatible = "ti,omap3-uart"; |
| 103 | ti,hwmods = "uart1"; | 115 | ti,hwmods = "uart1"; |
| 104 | clock-frequency = <48000000>; | 116 | clock-frequency = <48000000>; |
| 117 | reg = <0x44e09000 0x2000>; | ||
| 118 | interrupt-parent = <&intc>; | ||
| 119 | interrupts = <72>; | ||
| 120 | status = "disabled"; | ||
| 105 | }; | 121 | }; |
| 106 | 122 | ||
| 107 | uart2: serial@48022000 { | 123 | uart2: serial@48022000 { |
| 108 | compatible = "ti,omap3-uart"; | 124 | compatible = "ti,omap3-uart"; |
| 109 | ti,hwmods = "uart2"; | 125 | ti,hwmods = "uart2"; |
| 110 | clock-frequency = <48000000>; | 126 | clock-frequency = <48000000>; |
| 127 | reg = <0x48022000 0x2000>; | ||
| 128 | interrupt-parent = <&intc>; | ||
| 129 | interrupts = <73>; | ||
| 130 | status = "disabled"; | ||
| 111 | }; | 131 | }; |
| 112 | 132 | ||
| 113 | uart3: serial@48024000 { | 133 | uart3: serial@48024000 { |
| 114 | compatible = "ti,omap3-uart"; | 134 | compatible = "ti,omap3-uart"; |
| 115 | ti,hwmods = "uart3"; | 135 | ti,hwmods = "uart3"; |
| 116 | clock-frequency = <48000000>; | 136 | clock-frequency = <48000000>; |
| 137 | reg = <0x48024000 0x2000>; | ||
| 138 | interrupt-parent = <&intc>; | ||
| 139 | interrupts = <74>; | ||
| 140 | status = "disabled"; | ||
| 117 | }; | 141 | }; |
| 118 | 142 | ||
| 119 | uart4: serial@481A6000 { | 143 | uart4: serial@481a6000 { |
| 120 | compatible = "ti,omap3-uart"; | 144 | compatible = "ti,omap3-uart"; |
| 121 | ti,hwmods = "uart4"; | 145 | ti,hwmods = "uart4"; |
| 122 | clock-frequency = <48000000>; | 146 | clock-frequency = <48000000>; |
| 147 | reg = <0x481a6000 0x2000>; | ||
| 148 | interrupt-parent = <&intc>; | ||
| 149 | interrupts = <44>; | ||
| 150 | status = "disabled"; | ||
| 123 | }; | 151 | }; |
| 124 | 152 | ||
| 125 | uart5: serial@481A8000 { | 153 | uart5: serial@481a8000 { |
| 126 | compatible = "ti,omap3-uart"; | 154 | compatible = "ti,omap3-uart"; |
| 127 | ti,hwmods = "uart5"; | 155 | ti,hwmods = "uart5"; |
| 128 | clock-frequency = <48000000>; | 156 | clock-frequency = <48000000>; |
| 157 | reg = <0x481a8000 0x2000>; | ||
| 158 | interrupt-parent = <&intc>; | ||
| 159 | interrupts = <45>; | ||
| 160 | status = "disabled"; | ||
| 129 | }; | 161 | }; |
| 130 | 162 | ||
| 131 | uart6: serial@481AA000 { | 163 | uart6: serial@481aa000 { |
| 132 | compatible = "ti,omap3-uart"; | 164 | compatible = "ti,omap3-uart"; |
| 133 | ti,hwmods = "uart6"; | 165 | ti,hwmods = "uart6"; |
| 134 | clock-frequency = <48000000>; | 166 | clock-frequency = <48000000>; |
| 167 | reg = <0x481aa000 0x2000>; | ||
| 168 | interrupt-parent = <&intc>; | ||
| 169 | interrupts = <46>; | ||
| 170 | status = "disabled"; | ||
| 135 | }; | 171 | }; |
| 136 | 172 | ||
| 137 | i2c1: i2c@44E0B000 { | 173 | i2c1: i2c@44e0b000 { |
| 138 | compatible = "ti,omap4-i2c"; | 174 | compatible = "ti,omap4-i2c"; |
| 139 | #address-cells = <1>; | 175 | #address-cells = <1>; |
| 140 | #size-cells = <0>; | 176 | #size-cells = <0>; |
| 141 | ti,hwmods = "i2c1"; | 177 | ti,hwmods = "i2c1"; |
| 178 | reg = <0x44e0b000 0x1000>; | ||
| 179 | interrupt-parent = <&intc>; | ||
| 180 | interrupts = <70>; | ||
| 181 | status = "disabled"; | ||
| 142 | }; | 182 | }; |
| 143 | 183 | ||
| 144 | i2c2: i2c@4802A000 { | 184 | i2c2: i2c@4802a000 { |
| 145 | compatible = "ti,omap4-i2c"; | 185 | compatible = "ti,omap4-i2c"; |
| 146 | #address-cells = <1>; | 186 | #address-cells = <1>; |
| 147 | #size-cells = <0>; | 187 | #size-cells = <0>; |
| 148 | ti,hwmods = "i2c2"; | 188 | ti,hwmods = "i2c2"; |
| 189 | reg = <0x4802a000 0x1000>; | ||
| 190 | interrupt-parent = <&intc>; | ||
| 191 | interrupts = <71>; | ||
| 192 | status = "disabled"; | ||
| 149 | }; | 193 | }; |
| 150 | 194 | ||
| 151 | i2c3: i2c@4819C000 { | 195 | i2c3: i2c@4819c000 { |
| 152 | compatible = "ti,omap4-i2c"; | 196 | compatible = "ti,omap4-i2c"; |
| 153 | #address-cells = <1>; | 197 | #address-cells = <1>; |
| 154 | #size-cells = <0>; | 198 | #size-cells = <0>; |
| 155 | ti,hwmods = "i2c3"; | 199 | ti,hwmods = "i2c3"; |
| 200 | reg = <0x4819c000 0x1000>; | ||
| 201 | interrupt-parent = <&intc>; | ||
| 202 | interrupts = <30>; | ||
| 203 | status = "disabled"; | ||
| 156 | }; | 204 | }; |
| 157 | 205 | ||
| 158 | wdt2: wdt@44e35000 { | 206 | wdt2: wdt@44e35000 { |
| 159 | compatible = "ti,omap3-wdt"; | 207 | compatible = "ti,omap3-wdt"; |
| 160 | ti,hwmods = "wd_timer2"; | 208 | ti,hwmods = "wd_timer2"; |
| 209 | reg = <0x44e35000 0x1000>; | ||
| 210 | interrupt-parent = <&intc>; | ||
| 211 | interrupts = <91>; | ||
| 161 | }; | 212 | }; |
| 162 | }; | 213 | }; |
| 163 | }; | 214 | }; |
diff --git a/arch/arm/boot/dts/db8500.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi index 3180a9c588b9..748ba7aa746c 100644 --- a/arch/arm/boot/dts/db8500.dtsi +++ b/arch/arm/boot/dts/dbx5x0.dtsi | |||
| @@ -194,6 +194,8 @@ | |||
| 194 | interrupts = <0 47 0x4>; | 194 | interrupts = <0 47 0x4>; |
| 195 | #address-cells = <1>; | 195 | #address-cells = <1>; |
| 196 | #size-cells = <1>; | 196 | #size-cells = <1>; |
| 197 | interrupt-controller; | ||
| 198 | #interrupt-cells = <2>; | ||
| 197 | ranges; | 199 | ranges; |
| 198 | 200 | ||
| 199 | prcmu-timer-4@80157450 { | 201 | prcmu-timer-4@80157450 { |
| @@ -330,6 +332,7 @@ | |||
| 330 | ab8500@5 { | 332 | ab8500@5 { |
| 331 | compatible = "stericsson,ab8500"; | 333 | compatible = "stericsson,ab8500"; |
| 332 | reg = <5>; /* mailbox 5 is i2c */ | 334 | reg = <5>; /* mailbox 5 is i2c */ |
| 335 | interrupt-parent = <&intc>; | ||
| 333 | interrupts = <0 40 0x4>; | 336 | interrupts = <0 40 0x4>; |
| 334 | interrupt-controller; | 337 | interrupt-controller; |
| 335 | #interrupt-cells = <2>; | 338 | #interrupt-cells = <2>; |
| @@ -371,7 +374,7 @@ | |||
| 371 | }; | 374 | }; |
| 372 | 375 | ||
| 373 | ab8500-ponkey { | 376 | ab8500-ponkey { |
| 374 | compatible = "stericsson,ab8500-ponkey"; | 377 | compatible = "stericsson,ab8500-poweron-key"; |
| 375 | interrupts = <6 0x4 | 378 | interrupts = <6 0x4 |
| 376 | 7 0x4>; | 379 | 7 0x4>; |
| 377 | interrupt-names = "ONKEY_DBF", "ONKEY_DBR"; | 380 | interrupt-names = "ONKEY_DBF", "ONKEY_DBR"; |
| @@ -389,6 +392,12 @@ | |||
| 389 | compatible = "stericsson,ab8500-debug"; | 392 | compatible = "stericsson,ab8500-debug"; |
| 390 | }; | 393 | }; |
| 391 | 394 | ||
| 395 | codec: ab8500-codec { | ||
| 396 | compatible = "stericsson,ab8500-codec"; | ||
| 397 | |||
| 398 | stericsson,earpeice-cmv = <950>; /* Units in mV. */ | ||
| 399 | }; | ||
| 400 | |||
| 392 | ab8500-regulators { | 401 | ab8500-regulators { |
| 393 | compatible = "stericsson,ab8500-regulator"; | 402 | compatible = "stericsson,ab8500-regulator"; |
| 394 | 403 | ||
| @@ -471,48 +480,63 @@ | |||
| 471 | }; | 480 | }; |
| 472 | 481 | ||
| 473 | i2c@80004000 { | 482 | i2c@80004000 { |
| 474 | compatible = "stericsson,db8500-i2c", "st,nomadik-i2c"; | 483 | compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; |
| 475 | reg = <0x80004000 0x1000>; | 484 | reg = <0x80004000 0x1000>; |
| 476 | interrupts = <0 21 0x4>; | 485 | interrupts = <0 21 0x4>; |
| 477 | #address-cells = <1>; | 486 | #address-cells = <1>; |
| 478 | #size-cells = <0>; | 487 | #size-cells = <0>; |
| 488 | v-i2c-supply = <&db8500_vape_reg>; | ||
| 489 | |||
| 490 | clock-frequency = <400000>; | ||
| 479 | }; | 491 | }; |
| 480 | 492 | ||
| 481 | i2c@80122000 { | 493 | i2c@80122000 { |
| 482 | compatible = "stericsson,db8500-i2c", "st,nomadik-i2c"; | 494 | compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; |
| 483 | reg = <0x80122000 0x1000>; | 495 | reg = <0x80122000 0x1000>; |
| 484 | interrupts = <0 22 0x4>; | 496 | interrupts = <0 22 0x4>; |
| 485 | #address-cells = <1>; | 497 | #address-cells = <1>; |
| 486 | #size-cells = <0>; | 498 | #size-cells = <0>; |
| 499 | v-i2c-supply = <&db8500_vape_reg>; | ||
| 500 | |||
| 501 | clock-frequency = <400000>; | ||
| 487 | }; | 502 | }; |
| 488 | 503 | ||
| 489 | i2c@80128000 { | 504 | i2c@80128000 { |
| 490 | compatible = "stericsson,db8500-i2c", "st,nomadik-i2c"; | 505 | compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; |
| 491 | reg = <0x80128000 0x1000>; | 506 | reg = <0x80128000 0x1000>; |
| 492 | interrupts = <0 55 0x4>; | 507 | interrupts = <0 55 0x4>; |
| 493 | #address-cells = <1>; | 508 | #address-cells = <1>; |
| 494 | #size-cells = <0>; | 509 | #size-cells = <0>; |
| 510 | v-i2c-supply = <&db8500_vape_reg>; | ||
| 511 | |||
| 512 | clock-frequency = <400000>; | ||
| 495 | }; | 513 | }; |
| 496 | 514 | ||
| 497 | i2c@80110000 { | 515 | i2c@80110000 { |
| 498 | compatible = "stericsson,db8500-i2c", "st,nomadik-i2c"; | 516 | compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; |
| 499 | reg = <0x80110000 0x1000>; | 517 | reg = <0x80110000 0x1000>; |
| 500 | interrupts = <0 12 0x4>; | 518 | interrupts = <0 12 0x4>; |
| 501 | #address-cells = <1>; | 519 | #address-cells = <1>; |
| 502 | #size-cells = <0>; | 520 | #size-cells = <0>; |
| 521 | v-i2c-supply = <&db8500_vape_reg>; | ||
| 522 | |||
| 523 | clock-frequency = <400000>; | ||
| 503 | }; | 524 | }; |
| 504 | 525 | ||
| 505 | i2c@8012a000 { | 526 | i2c@8012a000 { |
| 506 | compatible = "stericsson,db8500-i2c", "st,nomadik-i2c"; | 527 | compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; |
| 507 | reg = <0x8012a000 0x1000>; | 528 | reg = <0x8012a000 0x1000>; |
| 508 | interrupts = <0 51 0x4>; | 529 | interrupts = <0 51 0x4>; |
| 509 | #address-cells = <1>; | 530 | #address-cells = <1>; |
| 510 | #size-cells = <0>; | 531 | #size-cells = <0>; |
| 532 | v-i2c-supply = <&db8500_vape_reg>; | ||
| 533 | |||
| 534 | clock-frequency = <400000>; | ||
| 511 | }; | 535 | }; |
| 512 | 536 | ||
| 513 | ssp@80002000 { | 537 | ssp@80002000 { |
| 514 | compatible = "arm,pl022", "arm,primecell"; | 538 | compatible = "arm,pl022", "arm,primecell"; |
| 515 | reg = <80002000 0x1000>; | 539 | reg = <0x80002000 0x1000>; |
| 516 | interrupts = <0 14 0x4>; | 540 | interrupts = <0 14 0x4>; |
| 517 | #address-cells = <1>; | 541 | #address-cells = <1>; |
| 518 | #size-cells = <0>; | 542 | #size-cells = <0>; |
| @@ -580,6 +604,39 @@ | |||
| 580 | status = "disabled"; | 604 | status = "disabled"; |
| 581 | }; | 605 | }; |
| 582 | 606 | ||
| 607 | msp0: msp@80123000 { | ||
| 608 | compatible = "stericsson,ux500-msp-i2s"; | ||
| 609 | reg = <0x80123000 0x1000>; | ||
| 610 | interrupts = <0 31 0x4>; | ||
| 611 | v-ape-supply = <&db8500_vape_reg>; | ||
| 612 | status = "disabled"; | ||
| 613 | }; | ||
| 614 | |||
| 615 | msp1: msp@80124000 { | ||
| 616 | compatible = "stericsson,ux500-msp-i2s"; | ||
| 617 | reg = <0x80124000 0x1000>; | ||
| 618 | interrupts = <0 62 0x4>; | ||
| 619 | v-ape-supply = <&db8500_vape_reg>; | ||
| 620 | status = "disabled"; | ||
| 621 | }; | ||
| 622 | |||
| 623 | // HDMI sound | ||
| 624 | msp2: msp@80117000 { | ||
| 625 | compatible = "stericsson,ux500-msp-i2s"; | ||
| 626 | reg = <0x80117000 0x1000>; | ||
| 627 | interrupts = <0 98 0x4>; | ||
| 628 | v-ape-supply = <&db8500_vape_reg>; | ||
| 629 | status = "disabled"; | ||
| 630 | }; | ||
| 631 | |||
| 632 | msp3: msp@80125000 { | ||
| 633 | compatible = "stericsson,ux500-msp-i2s"; | ||
| 634 | reg = <0x80125000 0x1000>; | ||
| 635 | interrupts = <0 62 0x4>; | ||
| 636 | v-ape-supply = <&db8500_vape_reg>; | ||
| 637 | status = "disabled"; | ||
| 638 | }; | ||
| 639 | |||
| 583 | external-bus@50000000 { | 640 | external-bus@50000000 { |
| 584 | compatible = "simple-bus"; | 641 | compatible = "simple-bus"; |
| 585 | reg = <0x50000000 0x4000000>; | 642 | reg = <0x50000000 0x4000000>; |
diff --git a/arch/arm/boot/dts/ea3250.dts b/arch/arm/boot/dts/ea3250.dts index d79b28d9c963..a4ba31b23c88 100644 --- a/arch/arm/boot/dts/ea3250.dts +++ b/arch/arm/boot/dts/ea3250.dts | |||
| @@ -166,9 +166,116 @@ | |||
| 166 | #size-cells = <0>; | 166 | #size-cells = <0>; |
| 167 | autorepeat; | 167 | autorepeat; |
| 168 | button@21 { | 168 | button@21 { |
| 169 | label = "GPIO Key UP"; | 169 | label = "Interrupt Key"; |
| 170 | linux,code = <103>; | 170 | linux,code = <103>; |
| 171 | gpios = <&gpio 4 1 0>; /* GPI_P3 1 */ | 171 | gpios = <&gpio 4 1 0>; /* GPI_P3 1 */ |
| 172 | }; | 172 | }; |
| 173 | key1 { | ||
| 174 | label = "KEY1"; | ||
| 175 | linux,code = <1>; | ||
| 176 | gpios = <&pca9532 0 0>; | ||
| 177 | }; | ||
| 178 | key2 { | ||
| 179 | label = "KEY2"; | ||
| 180 | linux,code = <2>; | ||
| 181 | gpios = <&pca9532 1 0>; | ||
| 182 | }; | ||
| 183 | key3 { | ||
| 184 | label = "KEY3"; | ||
| 185 | linux,code = <3>; | ||
| 186 | gpios = <&pca9532 2 0>; | ||
| 187 | }; | ||
| 188 | key4 { | ||
| 189 | label = "KEY4"; | ||
| 190 | linux,code = <4>; | ||
| 191 | gpios = <&pca9532 3 0>; | ||
| 192 | }; | ||
| 193 | joy0 { | ||
| 194 | label = "Joystick Key 0"; | ||
| 195 | linux,code = <10>; | ||
| 196 | gpios = <&gpio 2 0 0>; /* P2.0 */ | ||
| 197 | }; | ||
| 198 | joy1 { | ||
| 199 | label = "Joystick Key 1"; | ||
| 200 | linux,code = <11>; | ||
| 201 | gpios = <&gpio 2 1 0>; /* P2.1 */ | ||
| 202 | }; | ||
| 203 | joy2 { | ||
| 204 | label = "Joystick Key 2"; | ||
| 205 | linux,code = <12>; | ||
| 206 | gpios = <&gpio 2 2 0>; /* P2.2 */ | ||
| 207 | }; | ||
| 208 | joy3 { | ||
| 209 | label = "Joystick Key 3"; | ||
| 210 | linux,code = <13>; | ||
| 211 | gpios = <&gpio 2 3 0>; /* P2.3 */ | ||
| 212 | }; | ||
| 213 | joy4 { | ||
| 214 | label = "Joystick Key 4"; | ||
| 215 | linux,code = <14>; | ||
| 216 | gpios = <&gpio 2 4 0>; /* P2.4 */ | ||
| 217 | }; | ||
| 218 | }; | ||
| 219 | |||
| 220 | leds { | ||
| 221 | compatible = "gpio-leds"; | ||
| 222 | |||
| 223 | /* LEDs on OEM Board */ | ||
| 224 | |||
| 225 | led1 { | ||
| 226 | gpios = <&gpio 5 14 1>; /* GPO_P3 14, GPIO 93, active low */ | ||
| 227 | linux,default-trigger = "timer"; | ||
| 228 | default-state = "off"; | ||
| 229 | }; | ||
| 230 | |||
| 231 | led2 { | ||
| 232 | gpios = <&gpio 2 10 1>; /* P2.10, active low */ | ||
| 233 | default-state = "off"; | ||
| 234 | }; | ||
| 235 | |||
| 236 | led3 { | ||
| 237 | gpios = <&gpio 2 11 1>; /* P2.11, active low */ | ||
| 238 | default-state = "off"; | ||
| 239 | }; | ||
| 240 | |||
| 241 | led4 { | ||
| 242 | gpios = <&gpio 2 12 1>; /* P2.12, active low */ | ||
| 243 | default-state = "off"; | ||
| 244 | }; | ||
| 245 | |||
| 246 | /* LEDs on Base Board */ | ||
| 247 | |||
| 248 | lede1 { | ||
| 249 | gpios = <&pca9532 8 0>; | ||
| 250 | default-state = "off"; | ||
| 251 | }; | ||
| 252 | lede2 { | ||
| 253 | gpios = <&pca9532 9 0>; | ||
| 254 | default-state = "off"; | ||
| 255 | }; | ||
| 256 | lede3 { | ||
| 257 | gpios = <&pca9532 10 0>; | ||
| 258 | default-state = "off"; | ||
| 259 | }; | ||
| 260 | lede4 { | ||
| 261 | gpios = <&pca9532 11 0>; | ||
| 262 | default-state = "off"; | ||
| 263 | }; | ||
| 264 | lede5 { | ||
| 265 | gpios = <&pca9532 12 0>; | ||
| 266 | default-state = "off"; | ||
| 267 | }; | ||
| 268 | lede6 { | ||
| 269 | gpios = <&pca9532 13 0>; | ||
| 270 | default-state = "off"; | ||
| 271 | }; | ||
| 272 | lede7 { | ||
| 273 | gpios = <&pca9532 14 0>; | ||
| 274 | default-state = "off"; | ||
| 275 | }; | ||
| 276 | lede8 { | ||
| 277 | gpios = <&pca9532 15 0>; | ||
| 278 | default-state = "off"; | ||
| 279 | }; | ||
| 173 | }; | 280 | }; |
| 174 | }; | 281 | }; |
diff --git a/arch/arm/boot/dts/elpida_ecb240abacn.dtsi b/arch/arm/boot/dts/elpida_ecb240abacn.dtsi new file mode 100644 index 000000000000..f97f70f83374 --- /dev/null +++ b/arch/arm/boot/dts/elpida_ecb240abacn.dtsi | |||
| @@ -0,0 +1,67 @@ | |||
| 1 | /* | ||
| 2 | * Common devices used in different OMAP boards | ||
| 3 | */ | ||
| 4 | |||
| 5 | / { | ||
| 6 | elpida_ECB240ABACN: lpddr2 { | ||
| 7 | compatible = "Elpida,ECB240ABACN","jedec,lpddr2-s4"; | ||
| 8 | density = <2048>; | ||
| 9 | io-width = <32>; | ||
| 10 | |||
| 11 | tRPab-min-tck = <3>; | ||
| 12 | tRCD-min-tck = <3>; | ||
| 13 | tWR-min-tck = <3>; | ||
| 14 | tRASmin-min-tck = <3>; | ||
| 15 | tRRD-min-tck = <2>; | ||
| 16 | tWTR-min-tck = <2>; | ||
| 17 | tXP-min-tck = <2>; | ||
| 18 | tRTP-min-tck = <2>; | ||
| 19 | tCKE-min-tck = <3>; | ||
| 20 | tCKESR-min-tck = <3>; | ||
| 21 | tFAW-min-tck = <8>; | ||
| 22 | |||
| 23 | timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 { | ||
| 24 | compatible = "jedec,lpddr2-timings"; | ||
| 25 | min-freq = <10000000>; | ||
| 26 | max-freq = <400000000>; | ||
| 27 | tRPab = <21000>; | ||
| 28 | tRCD = <18000>; | ||
| 29 | tWR = <15000>; | ||
| 30 | tRAS-min = <42000>; | ||
| 31 | tRRD = <10000>; | ||
| 32 | tWTR = <7500>; | ||
| 33 | tXP = <7500>; | ||
| 34 | tRTP = <7500>; | ||
| 35 | tCKESR = <15000>; | ||
| 36 | tDQSCK-max = <5500>; | ||
| 37 | tFAW = <50000>; | ||
| 38 | tZQCS = <90000>; | ||
| 39 | tZQCL = <360000>; | ||
| 40 | tZQinit = <1000000>; | ||
| 41 | tRAS-max-ns = <70000>; | ||
| 42 | tDQSCK-max-derated = <6000>; | ||
| 43 | }; | ||
| 44 | |||
| 45 | timings_elpida_ECB240ABACN_200mhz: lpddr2-timings@1 { | ||
| 46 | compatible = "jedec,lpddr2-timings"; | ||
| 47 | min-freq = <10000000>; | ||
| 48 | max-freq = <200000000>; | ||
| 49 | tRPab = <21000>; | ||
| 50 | tRCD = <18000>; | ||
| 51 | tWR = <15000>; | ||
| 52 | tRAS-min = <42000>; | ||
| 53 | tRRD = <10000>; | ||
| 54 | tWTR = <10000>; | ||
| 55 | tXP = <7500>; | ||
| 56 | tRTP = <7500>; | ||
| 57 | tCKESR = <15000>; | ||
| 58 | tDQSCK-max = <5500>; | ||
| 59 | tFAW = <50000>; | ||
| 60 | tZQCS = <90000>; | ||
| 61 | tZQCL = <360000>; | ||
| 62 | tZQinit = <1000000>; | ||
| 63 | tRAS-max-ns = <70000>; | ||
| 64 | tDQSCK-max-derated = <6000>; | ||
| 65 | }; | ||
| 66 | }; | ||
| 67 | }; | ||
diff --git a/arch/arm/boot/dts/hrefv60plus.dts b/arch/arm/boot/dts/hrefv60plus.dts new file mode 100644 index 000000000000..2131d77dc9c9 --- /dev/null +++ b/arch/arm/boot/dts/hrefv60plus.dts | |||
| @@ -0,0 +1,95 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2012 ST-Ericsson AB | ||
| 3 | * | ||
| 4 | * The code contained herein is licensed under the GNU General Public | ||
| 5 | * License. You may obtain a copy of the GNU General Public License | ||
| 6 | * Version 2 or later at the following locations: | ||
| 7 | * | ||
| 8 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 9 | * http://www.gnu.org/copyleft/gpl.html | ||
| 10 | */ | ||
| 11 | |||
| 12 | /dts-v1/; | ||
| 13 | /include/ "dbx5x0.dtsi" | ||
| 14 | |||
| 15 | / { | ||
| 16 | model = "ST-Ericsson HREF platform with Device Tree"; | ||
| 17 | compatible = "st-ericsson,hrefv60+"; | ||
| 18 | |||
| 19 | memory { | ||
| 20 | reg = <0x00000000 0x20000000>; | ||
| 21 | }; | ||
| 22 | |||
| 23 | soc-u9500 { | ||
| 24 | uart@80120000 { | ||
| 25 | status = "okay"; | ||
| 26 | }; | ||
| 27 | |||
| 28 | uart@80121000 { | ||
| 29 | status = "okay"; | ||
| 30 | }; | ||
| 31 | |||
| 32 | uart@80007000 { | ||
| 33 | status = "okay"; | ||
| 34 | }; | ||
| 35 | |||
| 36 | i2c@80004000 { | ||
| 37 | tc3589x@42 { | ||
| 38 | compatible = "tc3589x"; | ||
| 39 | reg = <0x42>; | ||
| 40 | interrupt-parent = <&gpio6>; | ||
| 41 | interrupts = <25 0x1>; | ||
| 42 | |||
| 43 | interrupt-controller; | ||
| 44 | #interrupt-cells = <2>; | ||
| 45 | |||
| 46 | tc3589x_gpio: tc3589x_gpio { | ||
| 47 | compatible = "tc3589x-gpio"; | ||
| 48 | interrupts = <0 0x1>; | ||
| 49 | |||
| 50 | interrupt-controller; | ||
| 51 | #interrupt-cells = <2>; | ||
| 52 | gpio-controller; | ||
| 53 | #gpio-cells = <2>; | ||
| 54 | }; | ||
| 55 | }; | ||
| 56 | |||
| 57 | tps61052@33 { | ||
| 58 | compatible = "tps61052"; | ||
| 59 | reg = <0x33>; | ||
| 60 | }; | ||
| 61 | }; | ||
| 62 | |||
| 63 | i2c@80128000 { | ||
| 64 | lp5521@0x33 { | ||
| 65 | compatible = "lp5521"; | ||
| 66 | reg = <0x33>; | ||
| 67 | }; | ||
| 68 | |||
| 69 | lp5521@0x34 { | ||
| 70 | compatible = "lp5521"; | ||
| 71 | reg = <0x34>; | ||
| 72 | }; | ||
| 73 | |||
| 74 | bh1780@0x29 { | ||
| 75 | compatible = "rohm,bh1780gli"; | ||
| 76 | reg = <0x33>; | ||
| 77 | }; | ||
| 78 | }; | ||
| 79 | |||
| 80 | sound { | ||
| 81 | compatible = "stericsson,snd-soc-mop500"; | ||
| 82 | |||
| 83 | stericsson,cpu-dai = <&msp1 &msp3>; | ||
| 84 | stericsson,audio-codec = <&codec>; | ||
| 85 | }; | ||
| 86 | |||
| 87 | msp1: msp@80124000 { | ||
| 88 | status = "okay"; | ||
| 89 | }; | ||
| 90 | |||
| 91 | msp3: msp@80125000 { | ||
| 92 | status = "okay"; | ||
| 93 | }; | ||
| 94 | }; | ||
| 95 | }; | ||
diff --git a/arch/arm/boot/dts/imx23-evk.dts b/arch/arm/boot/dts/imx23-evk.dts index e3486f486b40..035c13f9d3c0 100644 --- a/arch/arm/boot/dts/imx23-evk.dts +++ b/arch/arm/boot/dts/imx23-evk.dts | |||
| @@ -42,12 +42,13 @@ | |||
| 42 | pinctrl-names = "default"; | 42 | pinctrl-names = "default"; |
| 43 | pinctrl-0 = <&hog_pins_a>; | 43 | pinctrl-0 = <&hog_pins_a>; |
| 44 | 44 | ||
| 45 | hog_pins_a: hog-gpios@0 { | 45 | hog_pins_a: hog@0 { |
| 46 | reg = <0>; | 46 | reg = <0>; |
| 47 | fsl,pinmux-ids = < | 47 | fsl,pinmux-ids = < |
| 48 | 0x1123 /* MX23_PAD_LCD_RESET__GPIO_1_18 */ | 48 | 0x1123 /* MX23_PAD_LCD_RESET__GPIO_1_18 */ |
| 49 | 0x11d3 /* MX23_PAD_PWM3__GPIO_1_29 */ | 49 | 0x11d3 /* MX23_PAD_PWM3__GPIO_1_29 */ |
| 50 | 0x11e3 /* MX23_PAD_PWM4__GPIO_1_30 */ | 50 | 0x11e3 /* MX23_PAD_PWM4__GPIO_1_30 */ |
| 51 | 0x2010 /* MX23_PAD_SSP1_DETECT__SSP1_DETECT */ | ||
| 51 | >; | 52 | >; |
| 52 | fsl,drive-strength = <0>; | 53 | fsl,drive-strength = <0>; |
| 53 | fsl,voltage = <1>; | 54 | fsl,voltage = <1>; |
diff --git a/arch/arm/boot/dts/imx23-olinuxino.dts b/arch/arm/boot/dts/imx23-olinuxino.dts index 20912b1d8893..384d8b66f337 100644 --- a/arch/arm/boot/dts/imx23-olinuxino.dts +++ b/arch/arm/boot/dts/imx23-olinuxino.dts | |||
| @@ -31,6 +31,22 @@ | |||
| 31 | bus-width = <4>; | 31 | bus-width = <4>; |
| 32 | status = "okay"; | 32 | status = "okay"; |
| 33 | }; | 33 | }; |
| 34 | |||
| 35 | pinctrl@80018000 { | ||
| 36 | pinctrl-names = "default"; | ||
| 37 | pinctrl-0 = <&hog_pins_a>; | ||
| 38 | |||
| 39 | hog_pins_a: hog@0 { | ||
| 40 | reg = <0>; | ||
| 41 | fsl,pinmux-ids = < | ||
| 42 | 0x2013 /* MX23_PAD_SSP1_DETECT__GPIO_2_1 */ | ||
| 43 | 0x0113 /* MX23_PAD_GPMI_ALE__GPIO_0_17 */ | ||
| 44 | >; | ||
| 45 | fsl,drive-strength = <0>; | ||
| 46 | fsl,voltage = <1>; | ||
| 47 | fsl,pull-up = <0>; | ||
| 48 | }; | ||
| 49 | }; | ||
| 34 | }; | 50 | }; |
| 35 | 51 | ||
| 36 | apbx@80040000 { | 52 | apbx@80040000 { |
| @@ -39,6 +55,47 @@ | |||
| 39 | pinctrl-0 = <&duart_pins_a>; | 55 | pinctrl-0 = <&duart_pins_a>; |
| 40 | status = "okay"; | 56 | status = "okay"; |
| 41 | }; | 57 | }; |
| 58 | |||
| 59 | auart0: serial@8006c000 { | ||
| 60 | pinctrl-names = "default"; | ||
| 61 | pinctrl-0 = <&auart0_2pins_a>; | ||
| 62 | status = "okay"; | ||
| 63 | }; | ||
| 64 | |||
| 65 | usbphy0: usbphy@8007c000 { | ||
| 66 | status = "okay"; | ||
| 67 | }; | ||
| 68 | }; | ||
| 69 | }; | ||
| 70 | |||
| 71 | ahb@80080000 { | ||
| 72 | usb0: usb@80080000 { | ||
| 73 | vbus-supply = <®_usb0_vbus>; | ||
| 74 | status = "okay"; | ||
| 75 | }; | ||
| 76 | }; | ||
| 77 | |||
| 78 | regulators { | ||
| 79 | compatible = "simple-bus"; | ||
| 80 | |||
| 81 | reg_usb0_vbus: usb0_vbus { | ||
| 82 | compatible = "regulator-fixed"; | ||
| 83 | regulator-name = "usb0_vbus"; | ||
| 84 | regulator-min-microvolt = <5000000>; | ||
| 85 | regulator-max-microvolt = <5000000>; | ||
| 86 | enable-active-high; | ||
| 87 | startup-delay-us = <300>; /* LAN9215 requires a POR of 200us minimum */ | ||
| 88 | gpio = <&gpio0 17 0>; | ||
| 89 | }; | ||
| 90 | }; | ||
| 91 | |||
| 92 | leds { | ||
| 93 | compatible = "gpio-leds"; | ||
| 94 | |||
| 95 | user { | ||
| 96 | label = "green"; | ||
| 97 | gpios = <&gpio2 1 0>; | ||
| 98 | linux,default-trigger = "default-on"; | ||
| 42 | }; | 99 | }; |
| 43 | }; | 100 | }; |
| 44 | }; | 101 | }; |
diff --git a/arch/arm/boot/dts/imx23-stmp378x_devb.dts b/arch/arm/boot/dts/imx23-stmp378x_devb.dts index 757a327ff3e8..85c3864b6a56 100644 --- a/arch/arm/boot/dts/imx23-stmp378x_devb.dts +++ b/arch/arm/boot/dts/imx23-stmp378x_devb.dts | |||
| @@ -36,7 +36,7 @@ | |||
| 36 | pinctrl-names = "default"; | 36 | pinctrl-names = "default"; |
| 37 | pinctrl-0 = <&hog_pins_a>; | 37 | pinctrl-0 = <&hog_pins_a>; |
| 38 | 38 | ||
| 39 | hog_pins_a: hog-gpios@0 { | 39 | hog_pins_a: hog@0 { |
| 40 | reg = <0>; | 40 | reg = <0>; |
| 41 | fsl,pinmux-ids = < | 41 | fsl,pinmux-ids = < |
| 42 | 0x11d3 /* MX23_PAD_PWM3__GPIO_1_29 */ | 42 | 0x11d3 /* MX23_PAD_PWM3__GPIO_1_29 */ |
diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi index e6138310e5ce..3f3b6fc229b3 100644 --- a/arch/arm/boot/dts/imx23.dtsi +++ b/arch/arm/boot/dts/imx23.dtsi | |||
| @@ -52,6 +52,7 @@ | |||
| 52 | dma-apbh@80004000 { | 52 | dma-apbh@80004000 { |
| 53 | compatible = "fsl,imx23-dma-apbh"; | 53 | compatible = "fsl,imx23-dma-apbh"; |
| 54 | reg = <0x80004000 0x2000>; | 54 | reg = <0x80004000 0x2000>; |
| 55 | clocks = <&clks 15>; | ||
| 55 | }; | 56 | }; |
| 56 | 57 | ||
| 57 | ecc@80008000 { | 58 | ecc@80008000 { |
| @@ -67,6 +68,7 @@ | |||
| 67 | reg-names = "gpmi-nand", "bch"; | 68 | reg-names = "gpmi-nand", "bch"; |
| 68 | interrupts = <13>, <56>; | 69 | interrupts = <13>, <56>; |
| 69 | interrupt-names = "gpmi-dma", "bch"; | 70 | interrupt-names = "gpmi-dma", "bch"; |
| 71 | clocks = <&clks 34>; | ||
| 70 | fsl,gpmi-dma-channel = <4>; | 72 | fsl,gpmi-dma-channel = <4>; |
| 71 | status = "disabled"; | 73 | status = "disabled"; |
| 72 | }; | 74 | }; |
| @@ -74,6 +76,7 @@ | |||
| 74 | ssp0: ssp@80010000 { | 76 | ssp0: ssp@80010000 { |
| 75 | reg = <0x80010000 0x2000>; | 77 | reg = <0x80010000 0x2000>; |
| 76 | interrupts = <15 14>; | 78 | interrupts = <15 14>; |
| 79 | clocks = <&clks 33>; | ||
| 77 | fsl,ssp-dma-channel = <1>; | 80 | fsl,ssp-dma-channel = <1>; |
| 78 | status = "disabled"; | 81 | status = "disabled"; |
| 79 | }; | 82 | }; |
| @@ -140,6 +143,17 @@ | |||
| 140 | fsl,pull-up = <0>; | 143 | fsl,pull-up = <0>; |
| 141 | }; | 144 | }; |
| 142 | 145 | ||
| 146 | auart0_2pins_a: auart0-2pins@0 { | ||
| 147 | reg = <0>; | ||
| 148 | fsl,pinmux-ids = < | ||
| 149 | 0x01e2 /* MX23_PAD_I2C_SCL__AUART1_TX */ | ||
| 150 | 0x01f2 /* MX23_PAD_I2C_SDA__AUART1_RX */ | ||
| 151 | >; | ||
| 152 | fsl,drive-strength = <0>; | ||
| 153 | fsl,voltage = <1>; | ||
| 154 | fsl,pull-up = <0>; | ||
| 155 | }; | ||
| 156 | |||
| 143 | gpmi_pins_a: gpmi-nand@0 { | 157 | gpmi_pins_a: gpmi-nand@0 { |
| 144 | reg = <0>; | 158 | reg = <0>; |
| 145 | fsl,pinmux-ids = < | 159 | fsl,pinmux-ids = < |
| @@ -183,7 +197,6 @@ | |||
| 183 | 0x2040 /* MX23_PAD_SSP1_DATA2__SSP1_DATA2 */ | 197 | 0x2040 /* MX23_PAD_SSP1_DATA2__SSP1_DATA2 */ |
| 184 | 0x2050 /* MX23_PAD_SSP1_DATA3__SSP1_DATA3 */ | 198 | 0x2050 /* MX23_PAD_SSP1_DATA3__SSP1_DATA3 */ |
| 185 | 0x2000 /* MX23_PAD_SSP1_CMD__SSP1_CMD */ | 199 | 0x2000 /* MX23_PAD_SSP1_CMD__SSP1_CMD */ |
| 186 | 0x2010 /* MX23_PAD_SSP1_DETECT__SSP1_DETECT */ | ||
| 187 | 0x2060 /* MX23_PAD_SSP1_SCK__SSP1_SCK */ | 200 | 0x2060 /* MX23_PAD_SSP1_SCK__SSP1_SCK */ |
| 188 | >; | 201 | >; |
| 189 | fsl,drive-strength = <1>; | 202 | fsl,drive-strength = <1>; |
| @@ -280,6 +293,7 @@ | |||
| 280 | dma-apbx@80024000 { | 293 | dma-apbx@80024000 { |
| 281 | compatible = "fsl,imx23-dma-apbx"; | 294 | compatible = "fsl,imx23-dma-apbx"; |
| 282 | reg = <0x80024000 0x2000>; | 295 | reg = <0x80024000 0x2000>; |
| 296 | clocks = <&clks 16>; | ||
| 283 | }; | 297 | }; |
| 284 | 298 | ||
| 285 | dcp@80028000 { | 299 | dcp@80028000 { |
| @@ -306,12 +320,14 @@ | |||
| 306 | compatible = "fsl,imx23-lcdif"; | 320 | compatible = "fsl,imx23-lcdif"; |
| 307 | reg = <0x80030000 2000>; | 321 | reg = <0x80030000 2000>; |
| 308 | interrupts = <46 45>; | 322 | interrupts = <46 45>; |
| 323 | clocks = <&clks 38>; | ||
| 309 | status = "disabled"; | 324 | status = "disabled"; |
| 310 | }; | 325 | }; |
| 311 | 326 | ||
| 312 | ssp1: ssp@80034000 { | 327 | ssp1: ssp@80034000 { |
| 313 | reg = <0x80034000 0x2000>; | 328 | reg = <0x80034000 0x2000>; |
| 314 | interrupts = <2 20>; | 329 | interrupts = <2 20>; |
| 330 | clocks = <&clks 33>; | ||
| 315 | fsl,ssp-dma-channel = <2>; | 331 | fsl,ssp-dma-channel = <2>; |
| 316 | status = "disabled"; | 332 | status = "disabled"; |
| 317 | }; | 333 | }; |
| @@ -329,9 +345,10 @@ | |||
| 329 | reg = <0x80040000 0x40000>; | 345 | reg = <0x80040000 0x40000>; |
| 330 | ranges; | 346 | ranges; |
| 331 | 347 | ||
| 332 | clkctl@80040000 { | 348 | clks: clkctrl@80040000 { |
| 349 | compatible = "fsl,imx23-clkctrl"; | ||
| 333 | reg = <0x80040000 0x2000>; | 350 | reg = <0x80040000 0x2000>; |
| 334 | status = "disabled"; | 351 | #clock-cells = <1>; |
| 335 | }; | 352 | }; |
| 336 | 353 | ||
| 337 | saif0: saif@80042000 { | 354 | saif0: saif@80042000 { |
| @@ -383,6 +400,7 @@ | |||
| 383 | pwm: pwm@80064000 { | 400 | pwm: pwm@80064000 { |
| 384 | compatible = "fsl,imx23-pwm"; | 401 | compatible = "fsl,imx23-pwm"; |
| 385 | reg = <0x80064000 0x2000>; | 402 | reg = <0x80064000 0x2000>; |
| 403 | clocks = <&clks 30>; | ||
| 386 | #pwm-cells = <2>; | 404 | #pwm-cells = <2>; |
| 387 | fsl,pwm-number = <5>; | 405 | fsl,pwm-number = <5>; |
| 388 | status = "disabled"; | 406 | status = "disabled"; |
| @@ -397,6 +415,7 @@ | |||
| 397 | compatible = "fsl,imx23-auart"; | 415 | compatible = "fsl,imx23-auart"; |
| 398 | reg = <0x8006c000 0x2000>; | 416 | reg = <0x8006c000 0x2000>; |
| 399 | interrupts = <24 25 23>; | 417 | interrupts = <24 25 23>; |
| 418 | clocks = <&clks 32>; | ||
| 400 | status = "disabled"; | 419 | status = "disabled"; |
| 401 | }; | 420 | }; |
| 402 | 421 | ||
| @@ -404,6 +423,7 @@ | |||
| 404 | compatible = "fsl,imx23-auart"; | 423 | compatible = "fsl,imx23-auart"; |
| 405 | reg = <0x8006e000 0x2000>; | 424 | reg = <0x8006e000 0x2000>; |
| 406 | interrupts = <59 60 58>; | 425 | interrupts = <59 60 58>; |
| 426 | clocks = <&clks 32>; | ||
| 407 | status = "disabled"; | 427 | status = "disabled"; |
| 408 | }; | 428 | }; |
| 409 | 429 | ||
| @@ -411,11 +431,15 @@ | |||
| 411 | compatible = "arm,pl011", "arm,primecell"; | 431 | compatible = "arm,pl011", "arm,primecell"; |
| 412 | reg = <0x80070000 0x2000>; | 432 | reg = <0x80070000 0x2000>; |
| 413 | interrupts = <0>; | 433 | interrupts = <0>; |
| 434 | clocks = <&clks 32>, <&clks 16>; | ||
| 435 | clock-names = "uart", "apb_pclk"; | ||
| 414 | status = "disabled"; | 436 | status = "disabled"; |
| 415 | }; | 437 | }; |
| 416 | 438 | ||
| 417 | usbphy@8007c000 { | 439 | usbphy0: usbphy@8007c000 { |
| 440 | compatible = "fsl,imx23-usbphy"; | ||
| 418 | reg = <0x8007c000 0x2000>; | 441 | reg = <0x8007c000 0x2000>; |
| 442 | clocks = <&clks 41>; | ||
| 419 | status = "disabled"; | 443 | status = "disabled"; |
| 420 | }; | 444 | }; |
| 421 | }; | 445 | }; |
| @@ -428,8 +452,12 @@ | |||
| 428 | reg = <0x80080000 0x80000>; | 452 | reg = <0x80080000 0x80000>; |
| 429 | ranges; | 453 | ranges; |
| 430 | 454 | ||
| 431 | usbctrl@80080000 { | 455 | usb0: usb@80080000 { |
| 456 | compatible = "fsl,imx23-usb", "fsl,imx27-usb"; | ||
| 432 | reg = <0x80080000 0x40000>; | 457 | reg = <0x80080000 0x40000>; |
| 458 | interrupts = <11>; | ||
| 459 | fsl,usbphy = <&usbphy0>; | ||
| 460 | clocks = <&clks 40>; | ||
| 433 | status = "disabled"; | 461 | status = "disabled"; |
| 434 | }; | 462 | }; |
| 435 | }; | 463 | }; |
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore.dts b/arch/arm/boot/dts/imx27-phytec-phycore.dts index 2b0ff60247a4..777caa33cd85 100644 --- a/arch/arm/boot/dts/imx27-phytec-phycore.dts +++ b/arch/arm/boot/dts/imx27-phytec-phycore.dts | |||
| @@ -23,10 +23,6 @@ | |||
| 23 | soc { | 23 | soc { |
| 24 | aipi@10000000 { /* aipi */ | 24 | aipi@10000000 { /* aipi */ |
| 25 | 25 | ||
| 26 | wdog@10002000 { | ||
| 27 | status = "okay"; | ||
| 28 | }; | ||
| 29 | |||
| 30 | serial@1000a000 { | 26 | serial@1000a000 { |
| 31 | fsl,uart-has-rtscts; | 27 | fsl,uart-has-rtscts; |
| 32 | status = "okay"; | 28 | status = "okay"; |
diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi index 5303ab680a34..3e54f1498841 100644 --- a/arch/arm/boot/dts/imx27.dtsi +++ b/arch/arm/boot/dts/imx27.dtsi | |||
| @@ -62,7 +62,6 @@ | |||
| 62 | compatible = "fsl,imx27-wdt", "fsl,imx21-wdt"; | 62 | compatible = "fsl,imx27-wdt", "fsl,imx21-wdt"; |
| 63 | reg = <0x10002000 0x4000>; | 63 | reg = <0x10002000 0x4000>; |
| 64 | interrupts = <27>; | 64 | interrupts = <27>; |
| 65 | status = "disabled"; | ||
| 66 | }; | 65 | }; |
| 67 | 66 | ||
| 68 | uart1: serial@1000a000 { | 67 | uart1: serial@1000a000 { |
diff --git a/arch/arm/boot/dts/imx28-apx4devkit.dts b/arch/arm/boot/dts/imx28-apx4devkit.dts index b383417a558f..5171667a7763 100644 --- a/arch/arm/boot/dts/imx28-apx4devkit.dts +++ b/arch/arm/boot/dts/imx28-apx4devkit.dts | |||
| @@ -37,7 +37,7 @@ | |||
| 37 | pinctrl-names = "default"; | 37 | pinctrl-names = "default"; |
| 38 | pinctrl-0 = <&hog_pins_a>; | 38 | pinctrl-0 = <&hog_pins_a>; |
| 39 | 39 | ||
| 40 | hog_pins_a: hog-gpios@0 { | 40 | hog_pins_a: hog@0 { |
| 41 | reg = <0>; | 41 | reg = <0>; |
| 42 | fsl,pinmux-ids = < | 42 | fsl,pinmux-ids = < |
| 43 | 0x0113 /* MX28_PAD_GPMI_CE1N__GPIO_0_17 */ | 43 | 0x0113 /* MX28_PAD_GPMI_CE1N__GPIO_0_17 */ |
diff --git a/arch/arm/boot/dts/imx28-cfa10049.dts b/arch/arm/boot/dts/imx28-cfa10049.dts new file mode 100644 index 000000000000..05c892e931e3 --- /dev/null +++ b/arch/arm/boot/dts/imx28-cfa10049.dts | |||
| @@ -0,0 +1,99 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2012 Free Electrons | ||
| 3 | * | ||
| 4 | * The code contained herein is licensed under the GNU General Public | ||
| 5 | * License. You may obtain a copy of the GNU General Public License | ||
| 6 | * Version 2 or later at the following locations: | ||
| 7 | * | ||
| 8 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 9 | * http://www.gnu.org/copyleft/gpl.html | ||
| 10 | */ | ||
| 11 | |||
| 12 | /* | ||
| 13 | * The CFA-10049 is an expansion board for the CFA-10036 module, thus we | ||
| 14 | * need to include the CFA-10036 DTS. | ||
| 15 | */ | ||
| 16 | /include/ "imx28-cfa10036.dts" | ||
| 17 | |||
| 18 | / { | ||
| 19 | model = "Crystalfontz CFA-10049 Board"; | ||
| 20 | compatible = "crystalfontz,cfa10049", "crystalfontz,cfa10036", "fsl,imx28"; | ||
| 21 | |||
| 22 | apb@80000000 { | ||
| 23 | apbh@80000000 { | ||
| 24 | pinctrl@80018000 { | ||
| 25 | spi3_pins_cfa10049: spi3-cfa10049@0 { | ||
| 26 | reg = <0>; | ||
| 27 | fsl,pinmux-ids = < | ||
| 28 | 0x0181 /* MX28_PAD_GPMI_RDN__SSP3_SCK */ | ||
| 29 | 0x01c1 /* MX28_PAD_GPMI_RESETN__SSP3_CMD */ | ||
| 30 | 0x0111 /* MX28_PAD_GPMI_CE1N__SSP3_D3 */ | ||
| 31 | 0x01a2 /* MX28_PAD_GPMI_ALE__SSP3_D4 */ | ||
| 32 | >; | ||
| 33 | fsl,drive-strength = <1>; | ||
| 34 | fsl,voltage = <1>; | ||
| 35 | fsl,pull-up = <1>; | ||
| 36 | }; | ||
| 37 | }; | ||
| 38 | |||
| 39 | ssp3: ssp@80016000 { | ||
| 40 | compatible = "fsl,imx28-spi"; | ||
| 41 | pinctrl-names = "default"; | ||
| 42 | pinctrl-0 = <&spi3_pins_cfa10049>; | ||
| 43 | status = "okay"; | ||
| 44 | |||
| 45 | gpio5: gpio5@0 { | ||
| 46 | compatible = "fairchild,74hc595"; | ||
| 47 | gpio-controller; | ||
| 48 | #gpio-cells = <2>; | ||
| 49 | reg = <0>; | ||
| 50 | registers-number = <2>; | ||
| 51 | spi-max-frequency = <100000>; | ||
| 52 | }; | ||
| 53 | |||
| 54 | gpio6: gpio6@1 { | ||
| 55 | compatible = "fairchild,74hc595"; | ||
| 56 | gpio-controller; | ||
| 57 | #gpio-cells = <2>; | ||
| 58 | reg = <1>; | ||
| 59 | registers-number = <4>; | ||
| 60 | spi-max-frequency = <100000>; | ||
| 61 | }; | ||
| 62 | |||
| 63 | }; | ||
| 64 | }; | ||
| 65 | |||
| 66 | apbx@80040000 { | ||
| 67 | i2c1: i2c@8005a000 { | ||
| 68 | pinctrl-names = "default"; | ||
| 69 | pinctrl-0 = <&i2c1_pins_a>; | ||
| 70 | status = "okay"; | ||
| 71 | }; | ||
| 72 | |||
| 73 | usbphy1: usbphy@8007e000 { | ||
| 74 | status = "okay"; | ||
| 75 | }; | ||
| 76 | }; | ||
| 77 | }; | ||
| 78 | |||
| 79 | ahb@80080000 { | ||
| 80 | usb1: usb@80090000 { | ||
| 81 | vbus-supply = <®_usb1_vbus>; | ||
| 82 | pinctrl-0 = <&usbphy1_pins_a>; | ||
| 83 | pinctrl-names = "default"; | ||
| 84 | status = "okay"; | ||
| 85 | }; | ||
| 86 | }; | ||
| 87 | |||
| 88 | regulators { | ||
| 89 | compatible = "simple-bus"; | ||
| 90 | |||
| 91 | reg_usb1_vbus: usb1_vbus { | ||
| 92 | compatible = "regulator-fixed"; | ||
| 93 | regulator-name = "usb1_vbus"; | ||
| 94 | regulator-min-microvolt = <5000000>; | ||
| 95 | regulator-max-microvolt = <5000000>; | ||
| 96 | gpio = <&gpio0 7 1>; | ||
| 97 | }; | ||
| 98 | }; | ||
| 99 | }; | ||
diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts index 773c0e84d1fb..a0ad71ca3a44 100644 --- a/arch/arm/boot/dts/imx28-evk.dts +++ b/arch/arm/boot/dts/imx28-evk.dts | |||
| @@ -46,11 +46,28 @@ | |||
| 46 | wp-gpios = <&gpio0 28 0>; | 46 | wp-gpios = <&gpio0 28 0>; |
| 47 | }; | 47 | }; |
| 48 | 48 | ||
| 49 | ssp2: ssp@80014000 { | ||
| 50 | #address-cells = <1>; | ||
| 51 | #size-cells = <0>; | ||
| 52 | compatible = "fsl,imx28-spi"; | ||
| 53 | pinctrl-names = "default"; | ||
| 54 | pinctrl-0 = <&spi2_pins_a>; | ||
| 55 | status = "okay"; | ||
| 56 | |||
| 57 | flash: m25p80@0 { | ||
| 58 | #address-cells = <1>; | ||
| 59 | #size-cells = <1>; | ||
| 60 | compatible = "sst,sst25vf016b"; | ||
| 61 | spi-max-frequency = <40000000>; | ||
| 62 | reg = <0>; | ||
| 63 | }; | ||
| 64 | }; | ||
| 65 | |||
| 49 | pinctrl@80018000 { | 66 | pinctrl@80018000 { |
| 50 | pinctrl-names = "default"; | 67 | pinctrl-names = "default"; |
| 51 | pinctrl-0 = <&hog_pins_a>; | 68 | pinctrl-0 = <&hog_pins_a>; |
| 52 | 69 | ||
| 53 | hog_pins_a: hog-gpios@0 { | 70 | hog_pins_a: hog@0 { |
| 54 | reg = <0>; | 71 | reg = <0>; |
| 55 | fsl,pinmux-ids = < | 72 | fsl,pinmux-ids = < |
| 56 | 0x20d3 /* MX28_PAD_SSP1_CMD__GPIO_2_13 */ | 73 | 0x20d3 /* MX28_PAD_SSP1_CMD__GPIO_2_13 */ |
| @@ -128,6 +145,10 @@ | |||
| 128 | status = "okay"; | 145 | status = "okay"; |
| 129 | }; | 146 | }; |
| 130 | 147 | ||
| 148 | lradc@80050000 { | ||
| 149 | status = "okay"; | ||
| 150 | }; | ||
| 151 | |||
| 131 | i2c0: i2c@80058000 { | 152 | i2c0: i2c@80058000 { |
| 132 | pinctrl-names = "default"; | 153 | pinctrl-names = "default"; |
| 133 | pinctrl-0 = <&i2c0_pins_a>; | 154 | pinctrl-0 = <&i2c0_pins_a>; |
| @@ -140,6 +161,12 @@ | |||
| 140 | VDDIO-supply = <®_3p3v>; | 161 | VDDIO-supply = <®_3p3v>; |
| 141 | 162 | ||
| 142 | }; | 163 | }; |
| 164 | |||
| 165 | at24@51 { | ||
| 166 | compatible = "at24,24c32"; | ||
| 167 | pagesize = <32>; | ||
| 168 | reg = <0x51>; | ||
| 169 | }; | ||
| 143 | }; | 170 | }; |
| 144 | 171 | ||
| 145 | pwm: pwm@80064000 { | 172 | pwm: pwm@80064000 { |
diff --git a/arch/arm/boot/dts/imx28-m28evk.dts b/arch/arm/boot/dts/imx28-m28evk.dts index 183a3fd2d859..3bab6b00c52d 100644 --- a/arch/arm/boot/dts/imx28-m28evk.dts +++ b/arch/arm/boot/dts/imx28-m28evk.dts | |||
| @@ -23,6 +23,8 @@ | |||
| 23 | apb@80000000 { | 23 | apb@80000000 { |
| 24 | apbh@80000000 { | 24 | apbh@80000000 { |
| 25 | gpmi-nand@8000c000 { | 25 | gpmi-nand@8000c000 { |
| 26 | #address-cells = <1>; | ||
| 27 | #size-cells = <1>; | ||
| 26 | pinctrl-names = "default"; | 28 | pinctrl-names = "default"; |
| 27 | pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>; | 29 | pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>; |
| 28 | status = "okay"; | 30 | status = "okay"; |
| @@ -61,19 +63,40 @@ | |||
| 61 | &mmc0_cd_cfg | 63 | &mmc0_cd_cfg |
| 62 | &mmc0_sck_cfg>; | 64 | &mmc0_sck_cfg>; |
| 63 | bus-width = <8>; | 65 | bus-width = <8>; |
| 64 | wp-gpios = <&gpio3 10 1>; | 66 | wp-gpios = <&gpio3 10 0>; |
| 67 | vmmc-supply = <®_vddio_sd0>; | ||
| 65 | status = "okay"; | 68 | status = "okay"; |
| 66 | }; | 69 | }; |
| 67 | 70 | ||
| 71 | ssp2: ssp@80014000 { | ||
| 72 | #address-cells = <1>; | ||
| 73 | #size-cells = <0>; | ||
| 74 | compatible = "fsl,imx28-spi"; | ||
| 75 | pinctrl-names = "default"; | ||
| 76 | pinctrl-0 = <&spi2_pins_a>; | ||
| 77 | status = "okay"; | ||
| 78 | |||
| 79 | flash: m25p80@0 { | ||
| 80 | #address-cells = <1>; | ||
| 81 | #size-cells = <1>; | ||
| 82 | compatible = "m25p80"; | ||
| 83 | spi-max-frequency = <40000000>; | ||
| 84 | reg = <0>; | ||
| 85 | }; | ||
| 86 | }; | ||
| 87 | |||
| 68 | pinctrl@80018000 { | 88 | pinctrl@80018000 { |
| 69 | pinctrl-names = "default"; | 89 | pinctrl-names = "default"; |
| 70 | pinctrl-0 = <&hog_pins_a>; | 90 | pinctrl-0 = <&hog_pins_a>; |
| 71 | 91 | ||
| 72 | hog_pins_a: hog-gpios@0 { | 92 | hog_pins_a: hog@0 { |
| 73 | reg = <0>; | 93 | reg = <0>; |
| 74 | fsl,pinmux-ids = < | 94 | fsl,pinmux-ids = < |
| 95 | 0x31c3 /* MX28_PAD_PWM3__GPIO_3_28 */ | ||
| 75 | 0x30a3 /* MX28_PAD_AUART2_CTS__GPIO_3_10 */ | 96 | 0x30a3 /* MX28_PAD_AUART2_CTS__GPIO_3_10 */ |
| 76 | 0x30b3 /* MX28_PAD_AUART2_RTS__GPIO_3_11 */ | 97 | 0x30b3 /* MX28_PAD_AUART2_RTS__GPIO_3_11 */ |
| 98 | 0x30c3 /* MX28_PAD_AUART3_RX__GPIO_3_12 */ | ||
| 99 | 0x30d3 /* MX28_PAD_AUART3_TX__GPIO_3_13 */ | ||
| 77 | >; | 100 | >; |
| 78 | fsl,drive-strength = <0>; | 101 | fsl,drive-strength = <0>; |
| 79 | fsl,voltage = <1>; | 102 | fsl,voltage = <1>; |
| @@ -129,6 +152,7 @@ | |||
| 129 | i2c0: i2c@80058000 { | 152 | i2c0: i2c@80058000 { |
| 130 | pinctrl-names = "default"; | 153 | pinctrl-names = "default"; |
| 131 | pinctrl-0 = <&i2c0_pins_a>; | 154 | pinctrl-0 = <&i2c0_pins_a>; |
| 155 | clock-frequency = <400000>; | ||
| 132 | status = "okay"; | 156 | status = "okay"; |
| 133 | 157 | ||
| 134 | sgtl5000: codec@0a { | 158 | sgtl5000: codec@0a { |
| @@ -151,32 +175,51 @@ | |||
| 151 | }; | 175 | }; |
| 152 | }; | 176 | }; |
| 153 | 177 | ||
| 178 | lradc@80050000 { | ||
| 179 | status = "okay"; | ||
| 180 | }; | ||
| 181 | |||
| 154 | duart: serial@80074000 { | 182 | duart: serial@80074000 { |
| 155 | pinctrl-names = "default"; | 183 | pinctrl-names = "default"; |
| 156 | pinctrl-0 = <&duart_pins_a>; | 184 | pinctrl-0 = <&duart_pins_a>; |
| 157 | status = "okay"; | 185 | status = "okay"; |
| 158 | }; | 186 | }; |
| 159 | 187 | ||
| 160 | auart0: serial@8006a000 { | 188 | usbphy0: usbphy@8007c000 { |
| 161 | pinctrl-names = "default"; | ||
| 162 | pinctrl-0 = <&auart0_2pins_a>; | ||
| 163 | status = "okay"; | 189 | status = "okay"; |
| 164 | }; | 190 | }; |
| 165 | 191 | ||
| 166 | auart3: serial@80070000 { | 192 | usbphy1: usbphy@8007e000 { |
| 193 | status = "okay"; | ||
| 194 | }; | ||
| 195 | |||
| 196 | auart0: serial@8006a000 { | ||
| 167 | pinctrl-names = "default"; | 197 | pinctrl-names = "default"; |
| 168 | pinctrl-0 = <&auart3_pins_a>; | 198 | pinctrl-0 = <&auart0_2pins_a>; |
| 169 | status = "okay"; | 199 | status = "okay"; |
| 170 | }; | 200 | }; |
| 171 | }; | 201 | }; |
| 172 | }; | 202 | }; |
| 173 | 203 | ||
| 174 | ahb@80080000 { | 204 | ahb@80080000 { |
| 205 | usb0: usb@80080000 { | ||
| 206 | vbus-supply = <®_usb0_vbus>; | ||
| 207 | pinctrl-names = "default"; | ||
| 208 | pinctrl-0 = <&usbphy0_pins_a>; | ||
| 209 | status = "okay"; | ||
| 210 | }; | ||
| 211 | |||
| 212 | usb1: usb@80090000 { | ||
| 213 | vbus-supply = <®_usb1_vbus>; | ||
| 214 | pinctrl-names = "default"; | ||
| 215 | pinctrl-0 = <&usbphy1_pins_a>; | ||
| 216 | status = "okay"; | ||
| 217 | }; | ||
| 218 | |||
| 175 | mac0: ethernet@800f0000 { | 219 | mac0: ethernet@800f0000 { |
| 176 | phy-mode = "rmii"; | 220 | phy-mode = "rmii"; |
| 177 | pinctrl-names = "default"; | 221 | pinctrl-names = "default"; |
| 178 | pinctrl-0 = <&mac0_pins_a>; | 222 | pinctrl-0 = <&mac0_pins_a>; |
| 179 | phy-reset-gpios = <&gpio3 11 0>; | ||
| 180 | status = "okay"; | 223 | status = "okay"; |
| 181 | }; | 224 | }; |
| 182 | 225 | ||
| @@ -198,6 +241,30 @@ | |||
| 198 | regulator-max-microvolt = <3300000>; | 241 | regulator-max-microvolt = <3300000>; |
| 199 | regulator-always-on; | 242 | regulator-always-on; |
| 200 | }; | 243 | }; |
| 244 | |||
| 245 | reg_vddio_sd0: vddio-sd0 { | ||
| 246 | compatible = "regulator-fixed"; | ||
| 247 | regulator-name = "vddio-sd0"; | ||
| 248 | regulator-min-microvolt = <3300000>; | ||
| 249 | regulator-max-microvolt = <3300000>; | ||
| 250 | gpio = <&gpio3 28 0>; | ||
| 251 | }; | ||
| 252 | |||
| 253 | reg_usb0_vbus: usb0_vbus { | ||
| 254 | compatible = "regulator-fixed"; | ||
| 255 | regulator-name = "usb0_vbus"; | ||
| 256 | regulator-min-microvolt = <5000000>; | ||
| 257 | regulator-max-microvolt = <5000000>; | ||
| 258 | gpio = <&gpio3 12 0>; | ||
| 259 | }; | ||
| 260 | |||
| 261 | reg_usb1_vbus: usb1_vbus { | ||
| 262 | compatible = "regulator-fixed"; | ||
| 263 | regulator-name = "usb1_vbus"; | ||
| 264 | regulator-min-microvolt = <5000000>; | ||
| 265 | regulator-max-microvolt = <5000000>; | ||
| 266 | gpio = <&gpio3 13 0>; | ||
| 267 | }; | ||
| 201 | }; | 268 | }; |
| 202 | 269 | ||
| 203 | sound { | 270 | sound { |
diff --git a/arch/arm/boot/dts/imx28-tx28.dts b/arch/arm/boot/dts/imx28-tx28.dts index 62bf767409a6..37be532f0055 100644 --- a/arch/arm/boot/dts/imx28-tx28.dts +++ b/arch/arm/boot/dts/imx28-tx28.dts | |||
| @@ -25,7 +25,7 @@ | |||
| 25 | pinctrl-names = "default"; | 25 | pinctrl-names = "default"; |
| 26 | pinctrl-0 = <&hog_pins_a>; | 26 | pinctrl-0 = <&hog_pins_a>; |
| 27 | 27 | ||
| 28 | hog_pins_a: hog-gpios@0 { | 28 | hog_pins_a: hog@0 { |
| 29 | reg = <0>; | 29 | reg = <0>; |
| 30 | fsl,pinmux-ids = < | 30 | fsl,pinmux-ids = < |
| 31 | 0x40a3 /* MX28_PAD_ENET0_RXD3__GPIO_4_10 */ | 31 | 0x40a3 /* MX28_PAD_ENET0_RXD3__GPIO_4_10 */ |
| @@ -34,6 +34,24 @@ | |||
| 34 | fsl,voltage = <1>; | 34 | fsl,voltage = <1>; |
| 35 | fsl,pull-up = <0>; | 35 | fsl,pull-up = <0>; |
| 36 | }; | 36 | }; |
| 37 | |||
| 38 | mac0_pins_gpio: mac0-gpio-mode@0 { | ||
| 39 | reg = <0>; | ||
| 40 | fsl,pinmux-ids = < | ||
| 41 | 0x4003 /* MX28_PAD_ENET0_MDC__GPIO_4_0 */ | ||
| 42 | 0x4013 /* MX28_PAD_ENET0_MDIO__GPIO_4_1 */ | ||
| 43 | 0x4023 /* MX28_PAD_ENET0_RX_EN__GPIO_4_2 */ | ||
| 44 | 0x4033 /* MX28_PAD_ENET0_RXD0__GPIO_4_3 */ | ||
| 45 | 0x4043 /* MX28_PAD_ENET0_RXD1__GPIO_4_4 */ | ||
| 46 | 0x4063 /* MX28_PAD_ENET0_TX_EN__GPIO_4_6 */ | ||
| 47 | 0x4073 /* MX28_PAD_ENET0_TXD0__GPIO_4_7 */ | ||
| 48 | 0x4083 /* MX28_PAD_ENET0_TXD1__GPIO_4_8 */ | ||
| 49 | 0x4103 /* MX28_PAD_ENET_CLK__GPIO_4_16 */ | ||
| 50 | >; | ||
| 51 | fsl,drive-strength = <0>; | ||
| 52 | fsl,voltage = <1>; | ||
| 53 | fsl,pull-up = <0>; | ||
| 54 | }; | ||
| 37 | }; | 55 | }; |
| 38 | }; | 56 | }; |
| 39 | 57 | ||
| @@ -72,8 +90,9 @@ | |||
| 72 | ahb@80080000 { | 90 | ahb@80080000 { |
| 73 | mac0: ethernet@800f0000 { | 91 | mac0: ethernet@800f0000 { |
| 74 | phy-mode = "rmii"; | 92 | phy-mode = "rmii"; |
| 75 | pinctrl-names = "default"; | 93 | pinctrl-names = "default", "gpio_mode"; |
| 76 | pinctrl-0 = <&mac0_pins_a>; | 94 | pinctrl-0 = <&mac0_pins_a>; |
| 95 | pinctrl-1 = <&mac0_pins_gpio>; | ||
| 77 | status = "okay"; | 96 | status = "okay"; |
| 78 | }; | 97 | }; |
| 79 | }; | 98 | }; |
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi index 3fa6d190fab4..724147eab84b 100644 --- a/arch/arm/boot/dts/imx28.dtsi +++ b/arch/arm/boot/dts/imx28.dtsi | |||
| @@ -27,6 +27,8 @@ | |||
| 27 | serial2 = &auart2; | 27 | serial2 = &auart2; |
| 28 | serial3 = &auart3; | 28 | serial3 = &auart3; |
| 29 | serial4 = &auart4; | 29 | serial4 = &auart4; |
| 30 | ethernet0 = &mac0; | ||
| 31 | ethernet1 = &mac1; | ||
| 30 | }; | 32 | }; |
| 31 | 33 | ||
| 32 | cpus { | 34 | cpus { |
| @@ -65,6 +67,7 @@ | |||
| 65 | dma-apbh@80004000 { | 67 | dma-apbh@80004000 { |
| 66 | compatible = "fsl,imx28-dma-apbh"; | 68 | compatible = "fsl,imx28-dma-apbh"; |
| 67 | reg = <0x80004000 0x2000>; | 69 | reg = <0x80004000 0x2000>; |
| 70 | clocks = <&clks 25>; | ||
| 68 | }; | 71 | }; |
| 69 | 72 | ||
| 70 | perfmon@80006000 { | 73 | perfmon@80006000 { |
| @@ -81,34 +84,47 @@ | |||
| 81 | reg-names = "gpmi-nand", "bch"; | 84 | reg-names = "gpmi-nand", "bch"; |
| 82 | interrupts = <88>, <41>; | 85 | interrupts = <88>, <41>; |
| 83 | interrupt-names = "gpmi-dma", "bch"; | 86 | interrupt-names = "gpmi-dma", "bch"; |
| 87 | clocks = <&clks 50>; | ||
| 84 | fsl,gpmi-dma-channel = <4>; | 88 | fsl,gpmi-dma-channel = <4>; |
| 85 | status = "disabled"; | 89 | status = "disabled"; |
| 86 | }; | 90 | }; |
| 87 | 91 | ||
| 88 | ssp0: ssp@80010000 { | 92 | ssp0: ssp@80010000 { |
| 93 | #address-cells = <1>; | ||
| 94 | #size-cells = <0>; | ||
| 89 | reg = <0x80010000 0x2000>; | 95 | reg = <0x80010000 0x2000>; |
| 90 | interrupts = <96 82>; | 96 | interrupts = <96 82>; |
| 97 | clocks = <&clks 46>; | ||
| 91 | fsl,ssp-dma-channel = <0>; | 98 | fsl,ssp-dma-channel = <0>; |
| 92 | status = "disabled"; | 99 | status = "disabled"; |
| 93 | }; | 100 | }; |
| 94 | 101 | ||
| 95 | ssp1: ssp@80012000 { | 102 | ssp1: ssp@80012000 { |
| 103 | #address-cells = <1>; | ||
| 104 | #size-cells = <0>; | ||
| 96 | reg = <0x80012000 0x2000>; | 105 | reg = <0x80012000 0x2000>; |
| 97 | interrupts = <97 83>; | 106 | interrupts = <97 83>; |
| 107 | clocks = <&clks 47>; | ||
| 98 | fsl,ssp-dma-channel = <1>; | 108 | fsl,ssp-dma-channel = <1>; |
| 99 | status = "disabled"; | 109 | status = "disabled"; |
| 100 | }; | 110 | }; |
| 101 | 111 | ||
| 102 | ssp2: ssp@80014000 { | 112 | ssp2: ssp@80014000 { |
| 113 | #address-cells = <1>; | ||
| 114 | #size-cells = <0>; | ||
| 103 | reg = <0x80014000 0x2000>; | 115 | reg = <0x80014000 0x2000>; |
| 104 | interrupts = <98 84>; | 116 | interrupts = <98 84>; |
| 117 | clocks = <&clks 48>; | ||
| 105 | fsl,ssp-dma-channel = <2>; | 118 | fsl,ssp-dma-channel = <2>; |
| 106 | status = "disabled"; | 119 | status = "disabled"; |
| 107 | }; | 120 | }; |
| 108 | 121 | ||
| 109 | ssp3: ssp@80016000 { | 122 | ssp3: ssp@80016000 { |
| 123 | #address-cells = <1>; | ||
| 124 | #size-cells = <0>; | ||
| 110 | reg = <0x80016000 0x2000>; | 125 | reg = <0x80016000 0x2000>; |
| 111 | interrupts = <99 85>; | 126 | interrupts = <99 85>; |
| 127 | clocks = <&clks 49>; | ||
| 112 | fsl,ssp-dma-channel = <3>; | 128 | fsl,ssp-dma-channel = <3>; |
| 113 | status = "disabled"; | 129 | status = "disabled"; |
| 114 | }; | 130 | }; |
| @@ -410,6 +426,28 @@ | |||
| 410 | fsl,pull-up = <1>; | 426 | fsl,pull-up = <1>; |
| 411 | }; | 427 | }; |
| 412 | 428 | ||
| 429 | i2c0_pins_b: i2c0@1 { | ||
| 430 | reg = <1>; | ||
| 431 | fsl,pinmux-ids = < | ||
| 432 | 0x3001 /* MX28_PAD_AUART0_RX__I2C0_SCL */ | ||
| 433 | 0x3011 /* MX28_PAD_AUART0_TX__I2C0_SDA */ | ||
| 434 | >; | ||
| 435 | fsl,drive-strength = <1>; | ||
| 436 | fsl,voltage = <1>; | ||
| 437 | fsl,pull-up = <1>; | ||
| 438 | }; | ||
| 439 | |||
| 440 | i2c1_pins_a: i2c1@0 { | ||
| 441 | reg = <0>; | ||
| 442 | fsl,pinmux-ids = < | ||
| 443 | 0x3101 /* MX28_PAD_PWM0__I2C1_SCL */ | ||
| 444 | 0x3111 /* MX28_PAD_PWM1__I2C1_SDA */ | ||
| 445 | >; | ||
| 446 | fsl,drive-strength = <1>; | ||
| 447 | fsl,voltage = <1>; | ||
| 448 | fsl,pull-up = <1>; | ||
| 449 | }; | ||
| 450 | |||
| 413 | saif0_pins_a: saif0@0 { | 451 | saif0_pins_a: saif0@0 { |
| 414 | reg = <0>; | 452 | reg = <0>; |
| 415 | fsl,pinmux-ids = < | 453 | fsl,pinmux-ids = < |
| @@ -453,6 +491,16 @@ | |||
| 453 | fsl,pull-up = <0>; | 491 | fsl,pull-up = <0>; |
| 454 | }; | 492 | }; |
| 455 | 493 | ||
| 494 | pwm4_pins_a: pwm4@0 { | ||
| 495 | reg = <0>; | ||
| 496 | fsl,pinmux-ids = < | ||
| 497 | 0x31d0 /* MX28_PAD_PWM4__PWM_4 */ | ||
| 498 | >; | ||
| 499 | fsl,drive-strength = <0>; | ||
| 500 | fsl,voltage = <1>; | ||
| 501 | fsl,pull-up = <0>; | ||
| 502 | }; | ||
| 503 | |||
| 456 | lcdif_24bit_pins_a: lcdif-24bit@0 { | 504 | lcdif_24bit_pins_a: lcdif-24bit@0 { |
| 457 | reg = <0>; | 505 | reg = <0>; |
| 458 | fsl,pinmux-ids = < | 506 | fsl,pinmux-ids = < |
| @@ -507,6 +555,49 @@ | |||
| 507 | fsl,voltage = <1>; | 555 | fsl,voltage = <1>; |
| 508 | fsl,pull-up = <0>; | 556 | fsl,pull-up = <0>; |
| 509 | }; | 557 | }; |
| 558 | |||
| 559 | spi2_pins_a: spi2@0 { | ||
| 560 | reg = <0>; | ||
| 561 | fsl,pinmux-ids = < | ||
| 562 | 0x2100 /* MX28_PAD_SSP2_SCK__SSP2_SCK */ | ||
| 563 | 0x2110 /* MX28_PAD_SSP2_MOSI__SSP2_CMD */ | ||
| 564 | 0x2120 /* MX28_PAD_SSP2_MISO__SSP2_D0 */ | ||
| 565 | 0x2130 /* MX28_PAD_SSP2_SS0__SSP2_D3 */ | ||
| 566 | >; | ||
| 567 | fsl,drive-strength = <1>; | ||
| 568 | fsl,voltage = <1>; | ||
| 569 | fsl,pull-up = <1>; | ||
| 570 | }; | ||
| 571 | |||
| 572 | usbphy0_pins_a: usbphy0@0 { | ||
| 573 | reg = <0>; | ||
| 574 | fsl,pinmux-ids = < | ||
| 575 | 0x2152 /* MX28_PAD_SSP2_SS2__USB0_OVERCURRENT */ | ||
| 576 | >; | ||
| 577 | fsl,drive-strength = <2>; | ||
| 578 | fsl,voltage = <1>; | ||
| 579 | fsl,pull-up = <0>; | ||
| 580 | }; | ||
| 581 | |||
| 582 | usbphy0_pins_b: usbphy0@1 { | ||
| 583 | reg = <1>; | ||
| 584 | fsl,pinmux-ids = < | ||
| 585 | 0x3061 /* MX28_PAD_AUART1_CTS__USB0_OVERCURRENT */ | ||
| 586 | >; | ||
| 587 | fsl,drive-strength = <2>; | ||
| 588 | fsl,voltage = <1>; | ||
| 589 | fsl,pull-up = <0>; | ||
| 590 | }; | ||
| 591 | |||
| 592 | usbphy1_pins_a: usbphy1@0 { | ||
| 593 | reg = <0>; | ||
| 594 | fsl,pinmux-ids = < | ||
| 595 | 0x2142 /* MX28_PAD_SSP2_SS1__USB1_OVERCURRENT */ | ||
| 596 | >; | ||
| 597 | fsl,drive-strength = <2>; | ||
| 598 | fsl,voltage = <1>; | ||
| 599 | fsl,pull-up = <0>; | ||
| 600 | }; | ||
| 510 | }; | 601 | }; |
| 511 | 602 | ||
| 512 | digctl@8001c000 { | 603 | digctl@8001c000 { |
| @@ -523,6 +614,7 @@ | |||
| 523 | dma-apbx@80024000 { | 614 | dma-apbx@80024000 { |
| 524 | compatible = "fsl,imx28-dma-apbx"; | 615 | compatible = "fsl,imx28-dma-apbx"; |
| 525 | reg = <0x80024000 0x2000>; | 616 | reg = <0x80024000 0x2000>; |
| 617 | clocks = <&clks 26>; | ||
| 526 | }; | 618 | }; |
| 527 | 619 | ||
| 528 | dcp@80028000 { | 620 | dcp@80028000 { |
| @@ -551,6 +643,7 @@ | |||
| 551 | compatible = "fsl,imx28-lcdif"; | 643 | compatible = "fsl,imx28-lcdif"; |
| 552 | reg = <0x80030000 0x2000>; | 644 | reg = <0x80030000 0x2000>; |
| 553 | interrupts = <38 86>; | 645 | interrupts = <38 86>; |
| 646 | clocks = <&clks 55>; | ||
| 554 | status = "disabled"; | 647 | status = "disabled"; |
| 555 | }; | 648 | }; |
| 556 | 649 | ||
| @@ -558,6 +651,8 @@ | |||
| 558 | compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan"; | 651 | compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan"; |
| 559 | reg = <0x80032000 0x2000>; | 652 | reg = <0x80032000 0x2000>; |
| 560 | interrupts = <8>; | 653 | interrupts = <8>; |
| 654 | clocks = <&clks 58>, <&clks 58>; | ||
| 655 | clock-names = "ipg", "per"; | ||
| 561 | status = "disabled"; | 656 | status = "disabled"; |
| 562 | }; | 657 | }; |
| 563 | 658 | ||
| @@ -565,6 +660,8 @@ | |||
| 565 | compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan"; | 660 | compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan"; |
| 566 | reg = <0x80034000 0x2000>; | 661 | reg = <0x80034000 0x2000>; |
| 567 | interrupts = <9>; | 662 | interrupts = <9>; |
| 663 | clocks = <&clks 59>, <&clks 59>; | ||
| 664 | clock-names = "ipg", "per"; | ||
| 568 | status = "disabled"; | 665 | status = "disabled"; |
| 569 | }; | 666 | }; |
| 570 | 667 | ||
| @@ -611,15 +708,17 @@ | |||
| 611 | reg = <0x80040000 0x40000>; | 708 | reg = <0x80040000 0x40000>; |
| 612 | ranges; | 709 | ranges; |
| 613 | 710 | ||
| 614 | clkctl@80040000 { | 711 | clks: clkctrl@80040000 { |
| 712 | compatible = "fsl,imx28-clkctrl"; | ||
| 615 | reg = <0x80040000 0x2000>; | 713 | reg = <0x80040000 0x2000>; |
| 616 | status = "disabled"; | 714 | #clock-cells = <1>; |
| 617 | }; | 715 | }; |
| 618 | 716 | ||
| 619 | saif0: saif@80042000 { | 717 | saif0: saif@80042000 { |
| 620 | compatible = "fsl,imx28-saif"; | 718 | compatible = "fsl,imx28-saif"; |
| 621 | reg = <0x80042000 0x2000>; | 719 | reg = <0x80042000 0x2000>; |
| 622 | interrupts = <59 80>; | 720 | interrupts = <59 80>; |
| 721 | clocks = <&clks 53>; | ||
| 623 | fsl,saif-dma-channel = <4>; | 722 | fsl,saif-dma-channel = <4>; |
| 624 | status = "disabled"; | 723 | status = "disabled"; |
| 625 | }; | 724 | }; |
| @@ -633,12 +732,16 @@ | |||
| 633 | compatible = "fsl,imx28-saif"; | 732 | compatible = "fsl,imx28-saif"; |
| 634 | reg = <0x80046000 0x2000>; | 733 | reg = <0x80046000 0x2000>; |
| 635 | interrupts = <58 81>; | 734 | interrupts = <58 81>; |
| 735 | clocks = <&clks 54>; | ||
| 636 | fsl,saif-dma-channel = <5>; | 736 | fsl,saif-dma-channel = <5>; |
| 637 | status = "disabled"; | 737 | status = "disabled"; |
| 638 | }; | 738 | }; |
| 639 | 739 | ||
| 640 | lradc@80050000 { | 740 | lradc@80050000 { |
| 741 | compatible = "fsl,imx28-lradc"; | ||
| 641 | reg = <0x80050000 0x2000>; | 742 | reg = <0x80050000 0x2000>; |
| 743 | interrupts = <10 14 15 16 17 18 19 | ||
| 744 | 20 21 22 23 24 25>; | ||
| 642 | status = "disabled"; | 745 | status = "disabled"; |
| 643 | }; | 746 | }; |
| 644 | 747 | ||
| @@ -677,6 +780,7 @@ | |||
| 677 | pwm: pwm@80064000 { | 780 | pwm: pwm@80064000 { |
| 678 | compatible = "fsl,imx28-pwm", "fsl,imx23-pwm"; | 781 | compatible = "fsl,imx28-pwm", "fsl,imx23-pwm"; |
| 679 | reg = <0x80064000 0x2000>; | 782 | reg = <0x80064000 0x2000>; |
| 783 | clocks = <&clks 44>; | ||
| 680 | #pwm-cells = <2>; | 784 | #pwm-cells = <2>; |
| 681 | fsl,pwm-number = <8>; | 785 | fsl,pwm-number = <8>; |
| 682 | status = "disabled"; | 786 | status = "disabled"; |
| @@ -691,6 +795,7 @@ | |||
| 691 | compatible = "fsl,imx28-auart", "fsl,imx23-auart"; | 795 | compatible = "fsl,imx28-auart", "fsl,imx23-auart"; |
| 692 | reg = <0x8006a000 0x2000>; | 796 | reg = <0x8006a000 0x2000>; |
| 693 | interrupts = <112 70 71>; | 797 | interrupts = <112 70 71>; |
| 798 | clocks = <&clks 45>; | ||
| 694 | status = "disabled"; | 799 | status = "disabled"; |
| 695 | }; | 800 | }; |
| 696 | 801 | ||
| @@ -698,6 +803,7 @@ | |||
| 698 | compatible = "fsl,imx28-auart", "fsl,imx23-auart"; | 803 | compatible = "fsl,imx28-auart", "fsl,imx23-auart"; |
| 699 | reg = <0x8006c000 0x2000>; | 804 | reg = <0x8006c000 0x2000>; |
| 700 | interrupts = <113 72 73>; | 805 | interrupts = <113 72 73>; |
| 806 | clocks = <&clks 45>; | ||
| 701 | status = "disabled"; | 807 | status = "disabled"; |
| 702 | }; | 808 | }; |
| 703 | 809 | ||
| @@ -705,6 +811,7 @@ | |||
| 705 | compatible = "fsl,imx28-auart", "fsl,imx23-auart"; | 811 | compatible = "fsl,imx28-auart", "fsl,imx23-auart"; |
| 706 | reg = <0x8006e000 0x2000>; | 812 | reg = <0x8006e000 0x2000>; |
| 707 | interrupts = <114 74 75>; | 813 | interrupts = <114 74 75>; |
| 814 | clocks = <&clks 45>; | ||
| 708 | status = "disabled"; | 815 | status = "disabled"; |
| 709 | }; | 816 | }; |
| 710 | 817 | ||
| @@ -712,6 +819,7 @@ | |||
| 712 | compatible = "fsl,imx28-auart", "fsl,imx23-auart"; | 819 | compatible = "fsl,imx28-auart", "fsl,imx23-auart"; |
| 713 | reg = <0x80070000 0x2000>; | 820 | reg = <0x80070000 0x2000>; |
| 714 | interrupts = <115 76 77>; | 821 | interrupts = <115 76 77>; |
| 822 | clocks = <&clks 45>; | ||
| 715 | status = "disabled"; | 823 | status = "disabled"; |
| 716 | }; | 824 | }; |
| 717 | 825 | ||
| @@ -719,6 +827,7 @@ | |||
| 719 | compatible = "fsl,imx28-auart", "fsl,imx23-auart"; | 827 | compatible = "fsl,imx28-auart", "fsl,imx23-auart"; |
| 720 | reg = <0x80072000 0x2000>; | 828 | reg = <0x80072000 0x2000>; |
| 721 | interrupts = <116 78 79>; | 829 | interrupts = <116 78 79>; |
| 830 | clocks = <&clks 45>; | ||
| 722 | status = "disabled"; | 831 | status = "disabled"; |
| 723 | }; | 832 | }; |
| 724 | 833 | ||
| @@ -726,18 +835,22 @@ | |||
| 726 | compatible = "arm,pl011", "arm,primecell"; | 835 | compatible = "arm,pl011", "arm,primecell"; |
| 727 | reg = <0x80074000 0x1000>; | 836 | reg = <0x80074000 0x1000>; |
| 728 | interrupts = <47>; | 837 | interrupts = <47>; |
| 838 | clocks = <&clks 45>, <&clks 26>; | ||
| 839 | clock-names = "uart", "apb_pclk"; | ||
| 729 | status = "disabled"; | 840 | status = "disabled"; |
| 730 | }; | 841 | }; |
| 731 | 842 | ||
| 732 | usbphy0: usbphy@8007c000 { | 843 | usbphy0: usbphy@8007c000 { |
| 733 | compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy"; | 844 | compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy"; |
| 734 | reg = <0x8007c000 0x2000>; | 845 | reg = <0x8007c000 0x2000>; |
| 846 | clocks = <&clks 62>; | ||
| 735 | status = "disabled"; | 847 | status = "disabled"; |
| 736 | }; | 848 | }; |
| 737 | 849 | ||
| 738 | usbphy1: usbphy@8007e000 { | 850 | usbphy1: usbphy@8007e000 { |
| 739 | compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy"; | 851 | compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy"; |
| 740 | reg = <0x8007e000 0x2000>; | 852 | reg = <0x8007e000 0x2000>; |
| 853 | clocks = <&clks 63>; | ||
| 741 | status = "disabled"; | 854 | status = "disabled"; |
| 742 | }; | 855 | }; |
| 743 | }; | 856 | }; |
| @@ -754,6 +867,7 @@ | |||
| 754 | compatible = "fsl,imx28-usb", "fsl,imx27-usb"; | 867 | compatible = "fsl,imx28-usb", "fsl,imx27-usb"; |
| 755 | reg = <0x80080000 0x10000>; | 868 | reg = <0x80080000 0x10000>; |
| 756 | interrupts = <93>; | 869 | interrupts = <93>; |
| 870 | clocks = <&clks 60>; | ||
| 757 | fsl,usbphy = <&usbphy0>; | 871 | fsl,usbphy = <&usbphy0>; |
| 758 | status = "disabled"; | 872 | status = "disabled"; |
| 759 | }; | 873 | }; |
| @@ -762,6 +876,7 @@ | |||
| 762 | compatible = "fsl,imx28-usb", "fsl,imx27-usb"; | 876 | compatible = "fsl,imx28-usb", "fsl,imx27-usb"; |
| 763 | reg = <0x80090000 0x10000>; | 877 | reg = <0x80090000 0x10000>; |
| 764 | interrupts = <92>; | 878 | interrupts = <92>; |
| 879 | clocks = <&clks 61>; | ||
| 765 | fsl,usbphy = <&usbphy1>; | 880 | fsl,usbphy = <&usbphy1>; |
| 766 | status = "disabled"; | 881 | status = "disabled"; |
| 767 | }; | 882 | }; |
| @@ -775,6 +890,8 @@ | |||
| 775 | compatible = "fsl,imx28-fec"; | 890 | compatible = "fsl,imx28-fec"; |
| 776 | reg = <0x800f0000 0x4000>; | 891 | reg = <0x800f0000 0x4000>; |
| 777 | interrupts = <101>; | 892 | interrupts = <101>; |
| 893 | clocks = <&clks 57>, <&clks 57>; | ||
| 894 | clock-names = "ipg", "ahb"; | ||
| 778 | status = "disabled"; | 895 | status = "disabled"; |
| 779 | }; | 896 | }; |
| 780 | 897 | ||
| @@ -782,6 +899,8 @@ | |||
| 782 | compatible = "fsl,imx28-fec"; | 899 | compatible = "fsl,imx28-fec"; |
| 783 | reg = <0x800f4000 0x4000>; | 900 | reg = <0x800f4000 0x4000>; |
| 784 | interrupts = <102>; | 901 | interrupts = <102>; |
| 902 | clocks = <&clks 57>, <&clks 57>; | ||
| 903 | clock-names = "ipg", "ahb"; | ||
| 785 | status = "disabled"; | 904 | status = "disabled"; |
| 786 | }; | 905 | }; |
| 787 | 906 | ||
diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts index 59d9789e5508..cbd2b1c7487b 100644 --- a/arch/arm/boot/dts/imx51-babbage.dts +++ b/arch/arm/boot/dts/imx51-babbage.dts | |||
| @@ -25,23 +25,31 @@ | |||
| 25 | aips@70000000 { /* aips-1 */ | 25 | aips@70000000 { /* aips-1 */ |
| 26 | spba@70000000 { | 26 | spba@70000000 { |
| 27 | esdhc@70004000 { /* ESDHC1 */ | 27 | esdhc@70004000 { /* ESDHC1 */ |
| 28 | pinctrl-names = "default"; | ||
| 29 | pinctrl-0 = <&pinctrl_esdhc1_1>; | ||
| 28 | fsl,cd-controller; | 30 | fsl,cd-controller; |
| 29 | fsl,wp-controller; | 31 | fsl,wp-controller; |
| 30 | status = "okay"; | 32 | status = "okay"; |
| 31 | }; | 33 | }; |
| 32 | 34 | ||
| 33 | esdhc@70008000 { /* ESDHC2 */ | 35 | esdhc@70008000 { /* ESDHC2 */ |
| 36 | pinctrl-names = "default"; | ||
| 37 | pinctrl-0 = <&pinctrl_esdhc2_1>; | ||
| 34 | cd-gpios = <&gpio1 6 0>; | 38 | cd-gpios = <&gpio1 6 0>; |
| 35 | wp-gpios = <&gpio1 5 0>; | 39 | wp-gpios = <&gpio1 5 0>; |
| 36 | status = "okay"; | 40 | status = "okay"; |
| 37 | }; | 41 | }; |
| 38 | 42 | ||
| 39 | uart3: serial@7000c000 { | 43 | uart3: serial@7000c000 { |
| 44 | pinctrl-names = "default"; | ||
| 45 | pinctrl-0 = <&pinctrl_uart3_1>; | ||
| 40 | fsl,uart-has-rtscts; | 46 | fsl,uart-has-rtscts; |
| 41 | status = "okay"; | 47 | status = "okay"; |
| 42 | }; | 48 | }; |
| 43 | 49 | ||
| 44 | ecspi@70010000 { /* ECSPI1 */ | 50 | ecspi@70010000 { /* ECSPI1 */ |
| 51 | pinctrl-names = "default"; | ||
| 52 | pinctrl-0 = <&pinctrl_ecspi1_1>; | ||
| 45 | fsl,spi-num-chipselects = <2>; | 53 | fsl,spi-num-chipselects = <2>; |
| 46 | cs-gpios = <&gpio4 24 0>, <&gpio4 25 0>; | 54 | cs-gpios = <&gpio4 24 0>, <&gpio4 25 0>; |
| 47 | status = "okay"; | 55 | status = "okay"; |
| @@ -169,31 +177,43 @@ | |||
| 169 | }; | 177 | }; |
| 170 | }; | 178 | }; |
| 171 | 179 | ||
| 172 | wdog@73f98000 { /* WDOG1 */ | ||
| 173 | status = "okay"; | ||
| 174 | }; | ||
| 175 | |||
| 176 | iomuxc@73fa8000 { | 180 | iomuxc@73fa8000 { |
| 177 | compatible = "fsl,imx51-iomuxc-babbage"; | 181 | pinctrl-names = "default"; |
| 178 | reg = <0x73fa8000 0x4000>; | 182 | pinctrl-0 = <&pinctrl_hog>; |
| 183 | |||
| 184 | hog { | ||
| 185 | pinctrl_hog: hoggrp { | ||
| 186 | fsl,pins = < | ||
| 187 | 694 0x20d5 /* MX51_PAD_GPIO1_0__SD1_CD */ | ||
| 188 | 697 0x20d5 /* MX51_PAD_GPIO1_1__SD1_WP */ | ||
| 189 | 737 0x100 /* MX51_PAD_GPIO1_5__GPIO1_5 */ | ||
| 190 | 740 0x100 /* MX51_PAD_GPIO1_6__GPIO1_6 */ | ||
| 191 | 121 0x5 /* MX51_PAD_EIM_A27__GPIO2_21 */ | ||
| 192 | 402 0x85 /* MX51_PAD_CSPI1_SS0__GPIO4_24 */ | ||
| 193 | 405 0x85 /* MX51_PAD_CSPI1_SS1__GPIO4_25 */ | ||
| 194 | >; | ||
| 195 | }; | ||
| 196 | }; | ||
| 179 | }; | 197 | }; |
| 180 | 198 | ||
| 181 | uart1: serial@73fbc000 { | 199 | uart1: serial@73fbc000 { |
| 200 | pinctrl-names = "default"; | ||
| 201 | pinctrl-0 = <&pinctrl_uart1_1>; | ||
| 182 | fsl,uart-has-rtscts; | 202 | fsl,uart-has-rtscts; |
| 183 | status = "okay"; | 203 | status = "okay"; |
| 184 | }; | 204 | }; |
| 185 | 205 | ||
| 186 | uart2: serial@73fc0000 { | 206 | uart2: serial@73fc0000 { |
| 207 | pinctrl-names = "default"; | ||
| 208 | pinctrl-0 = <&pinctrl_uart2_1>; | ||
| 187 | status = "okay"; | 209 | status = "okay"; |
| 188 | }; | 210 | }; |
| 189 | }; | 211 | }; |
| 190 | 212 | ||
| 191 | aips@80000000 { /* aips-2 */ | 213 | aips@80000000 { /* aips-2 */ |
| 192 | sdma@83fb0000 { | ||
| 193 | fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin"; | ||
| 194 | }; | ||
| 195 | |||
| 196 | i2c@83fc4000 { /* I2C2 */ | 214 | i2c@83fc4000 { /* I2C2 */ |
| 215 | pinctrl-names = "default"; | ||
| 216 | pinctrl-0 = <&pinctrl_i2c2_1>; | ||
| 197 | status = "okay"; | 217 | status = "okay"; |
| 198 | 218 | ||
| 199 | sgtl5000: codec@0a { | 219 | sgtl5000: codec@0a { |
| @@ -206,10 +226,14 @@ | |||
| 206 | }; | 226 | }; |
| 207 | 227 | ||
| 208 | audmux@83fd0000 { | 228 | audmux@83fd0000 { |
| 229 | pinctrl-names = "default"; | ||
| 230 | pinctrl-0 = <&pinctrl_audmux_1>; | ||
| 209 | status = "okay"; | 231 | status = "okay"; |
| 210 | }; | 232 | }; |
| 211 | 233 | ||
| 212 | ethernet@83fec000 { | 234 | ethernet@83fec000 { |
| 235 | pinctrl-names = "default"; | ||
| 236 | pinctrl-0 = <&pinctrl_fec_1>; | ||
| 213 | phy-mode = "mii"; | 237 | phy-mode = "mii"; |
| 214 | status = "okay"; | 238 | status = "okay"; |
| 215 | }; | 239 | }; |
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index aba28dc87fc8..2f71a91ca98e 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi | |||
| @@ -130,6 +130,34 @@ | |||
| 130 | }; | 130 | }; |
| 131 | }; | 131 | }; |
| 132 | 132 | ||
| 133 | usb@73f80000 { | ||
| 134 | compatible = "fsl,imx51-usb", "fsl,imx27-usb"; | ||
| 135 | reg = <0x73f80000 0x0200>; | ||
| 136 | interrupts = <18>; | ||
| 137 | status = "disabled"; | ||
| 138 | }; | ||
| 139 | |||
| 140 | usb@73f80200 { | ||
| 141 | compatible = "fsl,imx51-usb", "fsl,imx27-usb"; | ||
| 142 | reg = <0x73f80200 0x0200>; | ||
| 143 | interrupts = <14>; | ||
| 144 | status = "disabled"; | ||
| 145 | }; | ||
| 146 | |||
| 147 | usb@73f80400 { | ||
| 148 | compatible = "fsl,imx51-usb", "fsl,imx27-usb"; | ||
| 149 | reg = <0x73f80400 0x0200>; | ||
| 150 | interrupts = <16>; | ||
| 151 | status = "disabled"; | ||
| 152 | }; | ||
| 153 | |||
| 154 | usb@73f80600 { | ||
| 155 | compatible = "fsl,imx51-usb", "fsl,imx27-usb"; | ||
| 156 | reg = <0x73f80600 0x0200>; | ||
| 157 | interrupts = <17>; | ||
| 158 | status = "disabled"; | ||
| 159 | }; | ||
| 160 | |||
| 133 | gpio1: gpio@73f84000 { | 161 | gpio1: gpio@73f84000 { |
| 134 | compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; | 162 | compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; |
| 135 | reg = <0x73f84000 0x4000>; | 163 | reg = <0x73f84000 0x4000>; |
| @@ -174,7 +202,6 @@ | |||
| 174 | compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; | 202 | compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; |
| 175 | reg = <0x73f98000 0x4000>; | 203 | reg = <0x73f98000 0x4000>; |
| 176 | interrupts = <58>; | 204 | interrupts = <58>; |
| 177 | status = "disabled"; | ||
| 178 | }; | 205 | }; |
| 179 | 206 | ||
| 180 | wdog@73f9c000 { /* WDOG2 */ | 207 | wdog@73f9c000 { /* WDOG2 */ |
| @@ -184,6 +211,122 @@ | |||
| 184 | status = "disabled"; | 211 | status = "disabled"; |
| 185 | }; | 212 | }; |
| 186 | 213 | ||
| 214 | iomuxc@73fa8000 { | ||
| 215 | compatible = "fsl,imx51-iomuxc"; | ||
| 216 | reg = <0x73fa8000 0x4000>; | ||
| 217 | |||
| 218 | audmux { | ||
| 219 | pinctrl_audmux_1: audmuxgrp-1 { | ||
| 220 | fsl,pins = < | ||
| 221 | 384 0x80000000 /* MX51_PAD_AUD3_BB_TXD__AUD3_TXD */ | ||
| 222 | 386 0x80000000 /* MX51_PAD_AUD3_BB_RXD__AUD3_RXD */ | ||
| 223 | 389 0x80000000 /* MX51_PAD_AUD3_BB_CK__AUD3_TXC */ | ||
| 224 | 391 0x80000000 /* MX51_PAD_AUD3_BB_FS__AUD3_TXFS */ | ||
| 225 | >; | ||
| 226 | }; | ||
| 227 | }; | ||
| 228 | |||
| 229 | fec { | ||
| 230 | pinctrl_fec_1: fecgrp-1 { | ||
| 231 | fsl,pins = < | ||
| 232 | 128 0x80000000 /* MX51_PAD_EIM_EB2__FEC_MDIO */ | ||
| 233 | 134 0x80000000 /* MX51_PAD_EIM_EB3__FEC_RDATA1 */ | ||
| 234 | 146 0x80000000 /* MX51_PAD_EIM_CS2__FEC_RDATA2 */ | ||
| 235 | 152 0x80000000 /* MX51_PAD_EIM_CS3__FEC_RDATA3 */ | ||
| 236 | 158 0x80000000 /* MX51_PAD_EIM_CS4__FEC_RX_ER */ | ||
| 237 | 165 0x80000000 /* MX51_PAD_EIM_CS5__FEC_CRS */ | ||
| 238 | 206 0x80000000 /* MX51_PAD_NANDF_RB2__FEC_COL */ | ||
| 239 | 213 0x80000000 /* MX51_PAD_NANDF_RB3__FEC_RX_CLK */ | ||
| 240 | 293 0x80000000 /* MX51_PAD_NANDF_D9__FEC_RDATA0 */ | ||
| 241 | 298 0x80000000 /* MX51_PAD_NANDF_D8__FEC_TDATA0 */ | ||
| 242 | 225 0x80000000 /* MX51_PAD_NANDF_CS2__FEC_TX_ER */ | ||
| 243 | 231 0x80000000 /* MX51_PAD_NANDF_CS3__FEC_MDC */ | ||
| 244 | 237 0x80000000 /* MX51_PAD_NANDF_CS4__FEC_TDATA1 */ | ||
| 245 | 243 0x80000000 /* MX51_PAD_NANDF_CS5__FEC_TDATA2 */ | ||
| 246 | 250 0x80000000 /* MX51_PAD_NANDF_CS6__FEC_TDATA3 */ | ||
| 247 | 255 0x80000000 /* MX51_PAD_NANDF_CS7__FEC_TX_EN */ | ||
| 248 | 260 0x80000000 /* MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK */ | ||
| 249 | >; | ||
| 250 | }; | ||
| 251 | }; | ||
| 252 | |||
| 253 | ecspi1 { | ||
| 254 | pinctrl_ecspi1_1: ecspi1grp-1 { | ||
| 255 | fsl,pins = < | ||
| 256 | 398 0x185 /* MX51_PAD_CSPI1_MISO__ECSPI1_MISO */ | ||
| 257 | 394 0x185 /* MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI */ | ||
| 258 | 409 0x185 /* MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK */ | ||
| 259 | >; | ||
| 260 | }; | ||
| 261 | }; | ||
| 262 | |||
| 263 | esdhc1 { | ||
| 264 | pinctrl_esdhc1_1: esdhc1grp-1 { | ||
| 265 | fsl,pins = < | ||
| 266 | 666 0x400020d5 /* MX51_PAD_SD1_CMD__SD1_CMD */ | ||
| 267 | 669 0x20d5 /* MX51_PAD_SD1_CLK__SD1_CLK */ | ||
| 268 | 672 0x20d5 /* MX51_PAD_SD1_DATA0__SD1_DATA0 */ | ||
| 269 | 678 0x20d5 /* MX51_PAD_SD1_DATA1__SD1_DATA1 */ | ||
| 270 | 684 0x20d5 /* MX51_PAD_SD1_DATA2__SD1_DATA2 */ | ||
| 271 | 691 0x20d5 /* MX51_PAD_SD1_DATA3__SD1_DATA3 */ | ||
| 272 | >; | ||
| 273 | }; | ||
| 274 | }; | ||
| 275 | |||
| 276 | esdhc2 { | ||
| 277 | pinctrl_esdhc2_1: esdhc2grp-1 { | ||
| 278 | fsl,pins = < | ||
| 279 | 704 0x400020d5 /* MX51_PAD_SD2_CMD__SD2_CMD */ | ||
| 280 | 707 0x20d5 /* MX51_PAD_SD2_CLK__SD2_CLK */ | ||
| 281 | 710 0x20d5 /* MX51_PAD_SD2_DATA0__SD2_DATA0 */ | ||
| 282 | 712 0x20d5 /* MX51_PAD_SD2_DATA1__SD2_DATA1 */ | ||
| 283 | 715 0x20d5 /* MX51_PAD_SD2_DATA2__SD2_DATA2 */ | ||
| 284 | 719 0x20d5 /* MX51_PAD_SD2_DATA3__SD2_DATA3 */ | ||
| 285 | >; | ||
| 286 | }; | ||
| 287 | }; | ||
| 288 | |||
| 289 | i2c2 { | ||
| 290 | pinctrl_i2c2_1: i2c2grp-1 { | ||
| 291 | fsl,pins = < | ||
| 292 | 449 0x400001ed /* MX51_PAD_KEY_COL4__I2C2_SCL */ | ||
| 293 | 454 0x400001ed /* MX51_PAD_KEY_COL5__I2C2_SDA */ | ||
| 294 | >; | ||
| 295 | }; | ||
| 296 | }; | ||
| 297 | |||
| 298 | uart1 { | ||
| 299 | pinctrl_uart1_1: uart1grp-1 { | ||
| 300 | fsl,pins = < | ||
| 301 | 413 0x1c5 /* MX51_PAD_UART1_RXD__UART1_RXD */ | ||
| 302 | 416 0x1c5 /* MX51_PAD_UART1_TXD__UART1_TXD */ | ||
| 303 | 418 0x1c5 /* MX51_PAD_UART1_RTS__UART1_RTS */ | ||
| 304 | 420 0x1c5 /* MX51_PAD_UART1_CTS__UART1_CTS */ | ||
| 305 | >; | ||
| 306 | }; | ||
| 307 | }; | ||
| 308 | |||
| 309 | uart2 { | ||
| 310 | pinctrl_uart2_1: uart2grp-1 { | ||
| 311 | fsl,pins = < | ||
| 312 | 423 0x1c5 /* MX51_PAD_UART2_RXD__UART2_RXD */ | ||
| 313 | 426 0x1c5 /* MX51_PAD_UART2_TXD__UART2_TXD */ | ||
| 314 | >; | ||
| 315 | }; | ||
| 316 | }; | ||
| 317 | |||
| 318 | uart3 { | ||
| 319 | pinctrl_uart3_1: uart3grp-1 { | ||
| 320 | fsl,pins = < | ||
| 321 | 54 0x1c5 /* MX51_PAD_EIM_D25__UART3_RXD */ | ||
| 322 | 59 0x1c5 /* MX51_PAD_EIM_D26__UART3_TXD */ | ||
| 323 | 65 0x1c5 /* MX51_PAD_EIM_D27__UART3_RTS */ | ||
| 324 | 49 0x1c5 /* MX51_PAD_EIM_D24__UART3_CTS */ | ||
| 325 | >; | ||
| 326 | }; | ||
| 327 | }; | ||
| 328 | }; | ||
| 329 | |||
| 187 | uart1: serial@73fbc000 { | 330 | uart1: serial@73fbc000 { |
| 188 | compatible = "fsl,imx51-uart", "fsl,imx21-uart"; | 331 | compatible = "fsl,imx51-uart", "fsl,imx21-uart"; |
| 189 | reg = <0x73fbc000 0x4000>; | 332 | reg = <0x73fbc000 0x4000>; |
| @@ -219,6 +362,7 @@ | |||
| 219 | compatible = "fsl,imx51-sdma", "fsl,imx35-sdma"; | 362 | compatible = "fsl,imx51-sdma", "fsl,imx35-sdma"; |
| 220 | reg = <0x83fb0000 0x4000>; | 363 | reg = <0x83fb0000 0x4000>; |
| 221 | interrupts = <6>; | 364 | interrupts = <6>; |
| 365 | fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin"; | ||
| 222 | }; | 366 | }; |
| 223 | 367 | ||
| 224 | cspi@83fc0000 { | 368 | cspi@83fc0000 { |
diff --git a/arch/arm/boot/dts/imx53-ard.dts b/arch/arm/boot/dts/imx53-ard.dts index da895e93a999..4be76f223526 100644 --- a/arch/arm/boot/dts/imx53-ard.dts +++ b/arch/arm/boot/dts/imx53-ard.dts | |||
| @@ -25,31 +25,66 @@ | |||
| 25 | aips@50000000 { /* AIPS1 */ | 25 | aips@50000000 { /* AIPS1 */ |
| 26 | spba@50000000 { | 26 | spba@50000000 { |
| 27 | esdhc@50004000 { /* ESDHC1 */ | 27 | esdhc@50004000 { /* ESDHC1 */ |
| 28 | pinctrl-names = "default"; | ||
| 29 | pinctrl-0 = <&pinctrl_esdhc1_2>; | ||
| 28 | cd-gpios = <&gpio1 1 0>; | 30 | cd-gpios = <&gpio1 1 0>; |
| 29 | wp-gpios = <&gpio1 9 0>; | 31 | wp-gpios = <&gpio1 9 0>; |
| 30 | status = "okay"; | 32 | status = "okay"; |
| 31 | }; | 33 | }; |
| 32 | }; | 34 | }; |
| 33 | 35 | ||
| 34 | wdog@53f98000 { /* WDOG1 */ | ||
| 35 | status = "okay"; | ||
| 36 | }; | ||
| 37 | |||
| 38 | iomuxc@53fa8000 { | 36 | iomuxc@53fa8000 { |
| 39 | compatible = "fsl,imx53-iomuxc-ard"; | 37 | pinctrl-names = "default"; |
| 40 | reg = <0x53fa8000 0x4000>; | 38 | pinctrl-0 = <&pinctrl_hog>; |
| 39 | |||
| 40 | hog { | ||
| 41 | pinctrl_hog: hoggrp { | ||
| 42 | fsl,pins = < | ||
| 43 | 1077 0x80000000 /* MX53_PAD_GPIO_1__GPIO1_1 */ | ||
| 44 | 1085 0x80000000 /* MX53_PAD_GPIO_9__GPIO1_9 */ | ||
| 45 | 486 0x80000000 /* MX53_PAD_EIM_EB3__GPIO2_31 */ | ||
| 46 | 739 0x80000000 /* MX53_PAD_GPIO_10__GPIO4_0 */ | ||
| 47 | 218 0x80000000 /* MX53_PAD_DISP0_DAT16__GPIO5_10 */ | ||
| 48 | 226 0x80000000 /* MX53_PAD_DISP0_DAT17__GPIO5_11 */ | ||
| 49 | 233 0x80000000 /* MX53_PAD_DISP0_DAT18__GPIO5_12 */ | ||
| 50 | 241 0x80000000 /* MX53_PAD_DISP0_DAT19__GPIO5_13 */ | ||
| 51 | 429 0x80000000 /* MX53_PAD_EIM_D16__EMI_WEIM_D_16 */ | ||
| 52 | 435 0x80000000 /* MX53_PAD_EIM_D17__EMI_WEIM_D_17 */ | ||
| 53 | 441 0x80000000 /* MX53_PAD_EIM_D18__EMI_WEIM_D_18 */ | ||
| 54 | 448 0x80000000 /* MX53_PAD_EIM_D19__EMI_WEIM_D_19 */ | ||
| 55 | 456 0x80000000 /* MX53_PAD_EIM_D20__EMI_WEIM_D_20 */ | ||
| 56 | 464 0x80000000 /* MX53_PAD_EIM_D21__EMI_WEIM_D_21 */ | ||
| 57 | 471 0x80000000 /* MX53_PAD_EIM_D22__EMI_WEIM_D_22 */ | ||
| 58 | 477 0x80000000 /* MX53_PAD_EIM_D23__EMI_WEIM_D_23 */ | ||
| 59 | 492 0x80000000 /* MX53_PAD_EIM_D24__EMI_WEIM_D_24 */ | ||
| 60 | 500 0x80000000 /* MX53_PAD_EIM_D25__EMI_WEIM_D_25 */ | ||
| 61 | 508 0x80000000 /* MX53_PAD_EIM_D26__EMI_WEIM_D_26 */ | ||
| 62 | 516 0x80000000 /* MX53_PAD_EIM_D27__EMI_WEIM_D_27 */ | ||
| 63 | 524 0x80000000 /* MX53_PAD_EIM_D28__EMI_WEIM_D_28 */ | ||
| 64 | 532 0x80000000 /* MX53_PAD_EIM_D29__EMI_WEIM_D_29 */ | ||
| 65 | 540 0x80000000 /* MX53_PAD_EIM_D30__EMI_WEIM_D_30 */ | ||
| 66 | 548 0x80000000 /* MX53_PAD_EIM_D31__EMI_WEIM_D_31 */ | ||
| 67 | 637 0x80000000 /* MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 */ | ||
| 68 | 642 0x80000000 /* MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 */ | ||
| 69 | 647 0x80000000 /* MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 */ | ||
| 70 | 652 0x80000000 /* MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 */ | ||
| 71 | 657 0x80000000 /* MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 */ | ||
| 72 | 662 0x80000000 /* MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 */ | ||
| 73 | 667 0x80000000 /* MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 */ | ||
| 74 | 611 0x80000000 /* MX53_PAD_EIM_OE__EMI_WEIM_OE */ | ||
| 75 | 616 0x80000000 /* MX53_PAD_EIM_RW__EMI_WEIM_RW */ | ||
| 76 | 607 0x80000000 /* MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 */ | ||
| 77 | >; | ||
| 78 | }; | ||
| 79 | }; | ||
| 41 | }; | 80 | }; |
| 42 | 81 | ||
| 43 | uart1: serial@53fbc000 { | 82 | uart1: serial@53fbc000 { |
| 83 | pinctrl-names = "default"; | ||
| 84 | pinctrl-0 = <&pinctrl_uart1_2>; | ||
| 44 | status = "okay"; | 85 | status = "okay"; |
| 45 | }; | 86 | }; |
| 46 | }; | 87 | }; |
| 47 | |||
| 48 | aips@60000000 { /* AIPS2 */ | ||
| 49 | sdma@63fb0000 { | ||
| 50 | fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; | ||
| 51 | }; | ||
| 52 | }; | ||
| 53 | }; | 88 | }; |
| 54 | 89 | ||
| 55 | eim-cs1@f4000000 { | 90 | eim-cs1@f4000000 { |
diff --git a/arch/arm/boot/dts/imx53-evk.dts b/arch/arm/boot/dts/imx53-evk.dts index 9c798034675e..a124d1e25258 100644 --- a/arch/arm/boot/dts/imx53-evk.dts +++ b/arch/arm/boot/dts/imx53-evk.dts | |||
| @@ -25,12 +25,16 @@ | |||
| 25 | aips@50000000 { /* AIPS1 */ | 25 | aips@50000000 { /* AIPS1 */ |
| 26 | spba@50000000 { | 26 | spba@50000000 { |
| 27 | esdhc@50004000 { /* ESDHC1 */ | 27 | esdhc@50004000 { /* ESDHC1 */ |
| 28 | pinctrl-names = "default"; | ||
| 29 | pinctrl-0 = <&pinctrl_esdhc1_1>; | ||
| 28 | cd-gpios = <&gpio3 13 0>; | 30 | cd-gpios = <&gpio3 13 0>; |
| 29 | wp-gpios = <&gpio3 14 0>; | 31 | wp-gpios = <&gpio3 14 0>; |
| 30 | status = "okay"; | 32 | status = "okay"; |
| 31 | }; | 33 | }; |
| 32 | 34 | ||
| 33 | ecspi@50010000 { /* ECSPI1 */ | 35 | ecspi@50010000 { /* ECSPI1 */ |
| 36 | pinctrl-names = "default"; | ||
| 37 | pinctrl-0 = <&pinctrl_ecspi1_1>; | ||
| 34 | fsl,spi-num-chipselects = <2>; | 38 | fsl,spi-num-chipselects = <2>; |
| 35 | cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>; | 39 | cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>; |
| 36 | status = "okay"; | 40 | status = "okay"; |
| @@ -56,32 +60,45 @@ | |||
| 56 | }; | 60 | }; |
| 57 | 61 | ||
| 58 | esdhc@50020000 { /* ESDHC3 */ | 62 | esdhc@50020000 { /* ESDHC3 */ |
| 63 | pinctrl-names = "default"; | ||
| 64 | pinctrl-0 = <&pinctrl_esdhc3_1>; | ||
| 59 | cd-gpios = <&gpio3 11 0>; | 65 | cd-gpios = <&gpio3 11 0>; |
| 60 | wp-gpios = <&gpio3 12 0>; | 66 | wp-gpios = <&gpio3 12 0>; |
| 61 | status = "okay"; | 67 | status = "okay"; |
| 62 | }; | 68 | }; |
| 63 | }; | 69 | }; |
| 64 | 70 | ||
| 65 | wdog@53f98000 { /* WDOG1 */ | ||
| 66 | status = "okay"; | ||
| 67 | }; | ||
| 68 | |||
| 69 | iomuxc@53fa8000 { | 71 | iomuxc@53fa8000 { |
| 70 | compatible = "fsl,imx53-iomuxc-evk"; | 72 | pinctrl-names = "default"; |
| 71 | reg = <0x53fa8000 0x4000>; | 73 | pinctrl-0 = <&pinctrl_hog>; |
| 74 | |||
| 75 | hog { | ||
| 76 | pinctrl_hog: hoggrp { | ||
| 77 | fsl,pins = < | ||
| 78 | 424 0x80000000 /* MX53_PAD_EIM_EB2__GPIO2_30 */ | ||
| 79 | 449 0x80000000 /* MX53_PAD_EIM_D19__GPIO3_19 */ | ||
| 80 | 693 0x80000000 /* MX53_PAD_EIM_DA11__GPIO3_11 */ | ||
| 81 | 697 0x80000000 /* MX53_PAD_EIM_DA12__GPIO3_12 */ | ||
| 82 | 701 0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */ | ||
| 83 | 705 0x80000000 /* MX53_PAD_EIM_DA14__GPIO3_14 */ | ||
| 84 | 868 0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */ | ||
| 85 | 873 0x80000000 /* MX53_PAD_PATA_DA_1__GPIO7_7 */ | ||
| 86 | >; | ||
| 87 | }; | ||
| 88 | }; | ||
| 72 | }; | 89 | }; |
| 73 | 90 | ||
| 74 | uart1: serial@53fbc000 { | 91 | uart1: serial@53fbc000 { |
| 92 | pinctrl-names = "default"; | ||
| 93 | pinctrl-0 = <&pinctrl_uart1_1>; | ||
| 75 | status = "okay"; | 94 | status = "okay"; |
| 76 | }; | 95 | }; |
| 77 | }; | 96 | }; |
| 78 | 97 | ||
| 79 | aips@60000000 { /* AIPS2 */ | 98 | aips@60000000 { /* AIPS2 */ |
| 80 | sdma@63fb0000 { | ||
| 81 | fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; | ||
| 82 | }; | ||
| 83 | |||
| 84 | i2c@63fc4000 { /* I2C2 */ | 99 | i2c@63fc4000 { /* I2C2 */ |
| 100 | pinctrl-names = "default"; | ||
| 101 | pinctrl-0 = <&pinctrl_i2c2_1>; | ||
| 85 | status = "okay"; | 102 | status = "okay"; |
| 86 | 103 | ||
| 87 | pmic: mc13892@08 { | 104 | pmic: mc13892@08 { |
| @@ -96,6 +113,8 @@ | |||
| 96 | }; | 113 | }; |
| 97 | 114 | ||
| 98 | ethernet@63fec000 { | 115 | ethernet@63fec000 { |
| 116 | pinctrl-names = "default"; | ||
| 117 | pinctrl-0 = <&pinctrl_fec_1>; | ||
| 99 | phy-mode = "rmii"; | 118 | phy-mode = "rmii"; |
| 100 | phy-reset-gpios = <&gpio7 6 0>; | 119 | phy-reset-gpios = <&gpio7 6 0>; |
| 101 | status = "okay"; | 120 | status = "okay"; |
diff --git a/arch/arm/boot/dts/imx53-qsb.dts b/arch/arm/boot/dts/imx53-qsb.dts index 2d803a9a6949..08948af86d1a 100644 --- a/arch/arm/boot/dts/imx53-qsb.dts +++ b/arch/arm/boot/dts/imx53-qsb.dts | |||
| @@ -25,6 +25,8 @@ | |||
| 25 | aips@50000000 { /* AIPS1 */ | 25 | aips@50000000 { /* AIPS1 */ |
| 26 | spba@50000000 { | 26 | spba@50000000 { |
| 27 | esdhc@50004000 { /* ESDHC1 */ | 27 | esdhc@50004000 { /* ESDHC1 */ |
| 28 | pinctrl-names = "default"; | ||
| 29 | pinctrl-0 = <&pinctrl_esdhc1_1>; | ||
| 28 | cd-gpios = <&gpio3 13 0>; | 30 | cd-gpios = <&gpio3 13 0>; |
| 29 | status = "okay"; | 31 | status = "okay"; |
| 30 | }; | 32 | }; |
| @@ -35,32 +37,46 @@ | |||
| 35 | }; | 37 | }; |
| 36 | 38 | ||
| 37 | esdhc@50020000 { /* ESDHC3 */ | 39 | esdhc@50020000 { /* ESDHC3 */ |
| 40 | pinctrl-names = "default"; | ||
| 41 | pinctrl-0 = <&pinctrl_esdhc3_1>; | ||
| 38 | cd-gpios = <&gpio3 11 0>; | 42 | cd-gpios = <&gpio3 11 0>; |
| 39 | wp-gpios = <&gpio3 12 0>; | 43 | wp-gpios = <&gpio3 12 0>; |
| 40 | status = "okay"; | 44 | status = "okay"; |
| 41 | }; | 45 | }; |
| 42 | }; | 46 | }; |
| 43 | 47 | ||
| 44 | wdog@53f98000 { /* WDOG1 */ | ||
| 45 | status = "okay"; | ||
| 46 | }; | ||
| 47 | |||
| 48 | iomuxc@53fa8000 { | 48 | iomuxc@53fa8000 { |
| 49 | compatible = "fsl,imx53-iomuxc-qsb"; | 49 | pinctrl-names = "default"; |
| 50 | reg = <0x53fa8000 0x4000>; | 50 | pinctrl-0 = <&pinctrl_hog>; |
| 51 | |||
| 52 | hog { | ||
| 53 | pinctrl_hog: hoggrp { | ||
| 54 | fsl,pins = < | ||
| 55 | 1071 0x80000000 /* MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK */ | ||
| 56 | 1141 0x80000000 /* MX53_PAD_GPIO_8__GPIO1_8 */ | ||
| 57 | 982 0x80000000 /* MX53_PAD_PATA_DATA14__GPIO2_14 */ | ||
| 58 | 989 0x80000000 /* MX53_PAD_PATA_DATA15__GPIO2_15 */ | ||
| 59 | 693 0x80000000 /* MX53_PAD_EIM_DA11__GPIO3_11 */ | ||
| 60 | 697 0x80000000 /* MX53_PAD_EIM_DA12__GPIO3_12 */ | ||
| 61 | 701 0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */ | ||
| 62 | 868 0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */ | ||
| 63 | 873 0x80000000 /* MX53_PAD_PATA_DA_1__GPIO7_7 */ | ||
| 64 | >; | ||
| 65 | }; | ||
| 66 | }; | ||
| 51 | }; | 67 | }; |
| 52 | 68 | ||
| 53 | uart1: serial@53fbc000 { | 69 | uart1: serial@53fbc000 { |
| 70 | pinctrl-names = "default"; | ||
| 71 | pinctrl-0 = <&pinctrl_uart1_1>; | ||
| 54 | status = "okay"; | 72 | status = "okay"; |
| 55 | }; | 73 | }; |
| 56 | }; | 74 | }; |
| 57 | 75 | ||
| 58 | aips@60000000 { /* AIPS2 */ | 76 | aips@60000000 { /* AIPS2 */ |
| 59 | sdma@63fb0000 { | ||
| 60 | fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; | ||
| 61 | }; | ||
| 62 | |||
| 63 | i2c@63fc4000 { /* I2C2 */ | 77 | i2c@63fc4000 { /* I2C2 */ |
| 78 | pinctrl-names = "default"; | ||
| 79 | pinctrl-0 = <&pinctrl_i2c2_1>; | ||
| 64 | status = "okay"; | 80 | status = "okay"; |
| 65 | 81 | ||
| 66 | sgtl5000: codec@0a { | 82 | sgtl5000: codec@0a { |
| @@ -72,6 +88,8 @@ | |||
| 72 | }; | 88 | }; |
| 73 | 89 | ||
| 74 | i2c@63fc8000 { /* I2C1 */ | 90 | i2c@63fc8000 { /* I2C1 */ |
| 91 | pinctrl-names = "default"; | ||
| 92 | pinctrl-0 = <&pinctrl_i2c1_1>; | ||
| 75 | status = "okay"; | 93 | status = "okay"; |
| 76 | 94 | ||
| 77 | accelerometer: mma8450@1c { | 95 | accelerometer: mma8450@1c { |
| @@ -158,10 +176,14 @@ | |||
| 158 | }; | 176 | }; |
| 159 | 177 | ||
| 160 | audmux@63fd0000 { | 178 | audmux@63fd0000 { |
| 179 | pinctrl-names = "default"; | ||
| 180 | pinctrl-0 = <&pinctrl_audmux_1>; | ||
| 161 | status = "okay"; | 181 | status = "okay"; |
| 162 | }; | 182 | }; |
| 163 | 183 | ||
| 164 | ethernet@63fec000 { | 184 | ethernet@63fec000 { |
| 185 | pinctrl-names = "default"; | ||
| 186 | pinctrl-0 = <&pinctrl_fec_1>; | ||
| 165 | phy-mode = "rmii"; | 187 | phy-mode = "rmii"; |
| 166 | phy-reset-gpios = <&gpio7 6 0>; | 188 | phy-reset-gpios = <&gpio7 6 0>; |
| 167 | status = "okay"; | 189 | status = "okay"; |
diff --git a/arch/arm/boot/dts/imx53-smd.dts b/arch/arm/boot/dts/imx53-smd.dts index 08091029168e..06c68580c842 100644 --- a/arch/arm/boot/dts/imx53-smd.dts +++ b/arch/arm/boot/dts/imx53-smd.dts | |||
| @@ -25,22 +25,30 @@ | |||
| 25 | aips@50000000 { /* AIPS1 */ | 25 | aips@50000000 { /* AIPS1 */ |
| 26 | spba@50000000 { | 26 | spba@50000000 { |
| 27 | esdhc@50004000 { /* ESDHC1 */ | 27 | esdhc@50004000 { /* ESDHC1 */ |
| 28 | pinctrl-names = "default"; | ||
| 29 | pinctrl-0 = <&pinctrl_esdhc1_1>; | ||
| 28 | cd-gpios = <&gpio3 13 0>; | 30 | cd-gpios = <&gpio3 13 0>; |
| 29 | wp-gpios = <&gpio4 11 0>; | 31 | wp-gpios = <&gpio4 11 0>; |
| 30 | status = "okay"; | 32 | status = "okay"; |
| 31 | }; | 33 | }; |
| 32 | 34 | ||
| 33 | esdhc@50008000 { /* ESDHC2 */ | 35 | esdhc@50008000 { /* ESDHC2 */ |
| 36 | pinctrl-names = "default"; | ||
| 37 | pinctrl-0 = <&pinctrl_esdhc2_1>; | ||
| 34 | non-removable; | 38 | non-removable; |
| 35 | status = "okay"; | 39 | status = "okay"; |
| 36 | }; | 40 | }; |
| 37 | 41 | ||
| 38 | uart3: serial@5000c000 { | 42 | uart3: serial@5000c000 { |
| 43 | pinctrl-names = "default"; | ||
| 44 | pinctrl-0 = <&pinctrl_uart3_1>; | ||
| 39 | fsl,uart-has-rtscts; | 45 | fsl,uart-has-rtscts; |
| 40 | status = "okay"; | 46 | status = "okay"; |
| 41 | }; | 47 | }; |
| 42 | 48 | ||
| 43 | ecspi@50010000 { /* ECSPI1 */ | 49 | ecspi@50010000 { /* ECSPI1 */ |
| 50 | pinctrl-names = "default"; | ||
| 51 | pinctrl-0 = <&pinctrl_ecspi1_1>; | ||
| 44 | fsl,spi-num-chipselects = <2>; | 52 | fsl,spi-num-chipselects = <2>; |
| 45 | cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>; | 53 | cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>; |
| 46 | status = "okay"; | 54 | status = "okay"; |
| @@ -72,35 +80,49 @@ | |||
| 72 | }; | 80 | }; |
| 73 | 81 | ||
| 74 | esdhc@50020000 { /* ESDHC3 */ | 82 | esdhc@50020000 { /* ESDHC3 */ |
| 83 | pinctrl-names = "default"; | ||
| 84 | pinctrl-0 = <&pinctrl_esdhc3_1>; | ||
| 75 | non-removable; | 85 | non-removable; |
| 76 | status = "okay"; | 86 | status = "okay"; |
| 77 | }; | 87 | }; |
| 78 | }; | 88 | }; |
| 79 | 89 | ||
| 80 | wdog@53f98000 { /* WDOG1 */ | ||
| 81 | status = "okay"; | ||
| 82 | }; | ||
| 83 | |||
| 84 | iomuxc@53fa8000 { | 90 | iomuxc@53fa8000 { |
| 85 | compatible = "fsl,imx53-iomuxc-smd"; | 91 | pinctrl-names = "default"; |
| 86 | reg = <0x53fa8000 0x4000>; | 92 | pinctrl-0 = <&pinctrl_hog>; |
| 93 | |||
| 94 | hog { | ||
| 95 | pinctrl_hog: hoggrp { | ||
| 96 | fsl,pins = < | ||
| 97 | 982 0x80000000 /* MX53_PAD_PATA_DATA14__GPIO2_14 */ | ||
| 98 | 989 0x80000000 /* MX53_PAD_PATA_DATA15__GPIO2_15 */ | ||
| 99 | 424 0x80000000 /* MX53_PAD_EIM_EB2__GPIO2_30 */ | ||
| 100 | 701 0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */ | ||
| 101 | 449 0x80000000 /* MX53_PAD_EIM_D19__GPIO3_19 */ | ||
| 102 | 43 0x80000000 /* MX53_PAD_KEY_ROW2__GPIO4_11 */ | ||
| 103 | 868 0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */ | ||
| 104 | >; | ||
| 105 | }; | ||
| 106 | }; | ||
| 87 | }; | 107 | }; |
| 88 | 108 | ||
| 89 | uart1: serial@53fbc000 { | 109 | uart1: serial@53fbc000 { |
| 110 | pinctrl-names = "default"; | ||
| 111 | pinctrl-0 = <&pinctrl_uart1_1>; | ||
| 90 | status = "okay"; | 112 | status = "okay"; |
| 91 | }; | 113 | }; |
| 92 | 114 | ||
| 93 | uart2: serial@53fc0000 { | 115 | uart2: serial@53fc0000 { |
| 116 | pinctrl-names = "default"; | ||
| 117 | pinctrl-0 = <&pinctrl_uart2_1>; | ||
| 94 | status = "okay"; | 118 | status = "okay"; |
| 95 | }; | 119 | }; |
| 96 | }; | 120 | }; |
| 97 | 121 | ||
| 98 | aips@60000000 { /* AIPS2 */ | 122 | aips@60000000 { /* AIPS2 */ |
| 99 | sdma@63fb0000 { | ||
| 100 | fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; | ||
| 101 | }; | ||
| 102 | |||
| 103 | i2c@63fc4000 { /* I2C2 */ | 123 | i2c@63fc4000 { /* I2C2 */ |
| 124 | pinctrl-names = "default"; | ||
| 125 | pinctrl-0 = <&pinctrl_i2c2_1>; | ||
| 104 | status = "okay"; | 126 | status = "okay"; |
| 105 | 127 | ||
| 106 | codec: sgtl5000@0a { | 128 | codec: sgtl5000@0a { |
| @@ -120,6 +142,8 @@ | |||
| 120 | }; | 142 | }; |
| 121 | 143 | ||
| 122 | i2c@63fc8000 { /* I2C1 */ | 144 | i2c@63fc8000 { /* I2C1 */ |
| 145 | pinctrl-names = "default"; | ||
| 146 | pinctrl-0 = <&pinctrl_i2c1_1>; | ||
| 123 | status = "okay"; | 147 | status = "okay"; |
| 124 | 148 | ||
| 125 | accelerometer: mma8450@1c { | 149 | accelerometer: mma8450@1c { |
| @@ -139,6 +163,8 @@ | |||
| 139 | }; | 163 | }; |
| 140 | 164 | ||
| 141 | ethernet@63fec000 { | 165 | ethernet@63fec000 { |
| 166 | pinctrl-names = "default"; | ||
| 167 | pinctrl-0 = <&pinctrl_fec_1>; | ||
| 142 | phy-mode = "rmii"; | 168 | phy-mode = "rmii"; |
| 143 | phy-reset-gpios = <&gpio7 6 0>; | 169 | phy-reset-gpios = <&gpio7 6 0>; |
| 144 | status = "okay"; | 170 | status = "okay"; |
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index cd37165edce5..221cf3321b0a 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi | |||
| @@ -135,6 +135,34 @@ | |||
| 135 | }; | 135 | }; |
| 136 | }; | 136 | }; |
| 137 | 137 | ||
| 138 | usb@53f80000 { | ||
| 139 | compatible = "fsl,imx53-usb", "fsl,imx27-usb"; | ||
| 140 | reg = <0x53f80000 0x0200>; | ||
| 141 | interrupts = <18>; | ||
| 142 | status = "disabled"; | ||
| 143 | }; | ||
| 144 | |||
| 145 | usb@53f80200 { | ||
| 146 | compatible = "fsl,imx53-usb", "fsl,imx27-usb"; | ||
| 147 | reg = <0x53f80200 0x0200>; | ||
| 148 | interrupts = <14>; | ||
| 149 | status = "disabled"; | ||
| 150 | }; | ||
| 151 | |||
| 152 | usb@53f80400 { | ||
| 153 | compatible = "fsl,imx53-usb", "fsl,imx27-usb"; | ||
| 154 | reg = <0x53f80400 0x0200>; | ||
| 155 | interrupts = <16>; | ||
| 156 | status = "disabled"; | ||
| 157 | }; | ||
| 158 | |||
| 159 | usb@53f80600 { | ||
| 160 | compatible = "fsl,imx53-usb", "fsl,imx27-usb"; | ||
| 161 | reg = <0x53f80600 0x0200>; | ||
| 162 | interrupts = <17>; | ||
| 163 | status = "disabled"; | ||
| 164 | }; | ||
| 165 | |||
| 138 | gpio1: gpio@53f84000 { | 166 | gpio1: gpio@53f84000 { |
| 139 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; | 167 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
| 140 | reg = <0x53f84000 0x4000>; | 168 | reg = <0x53f84000 0x4000>; |
| @@ -179,7 +207,6 @@ | |||
| 179 | compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; | 207 | compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; |
| 180 | reg = <0x53f98000 0x4000>; | 208 | reg = <0x53f98000 0x4000>; |
| 181 | interrupts = <58>; | 209 | interrupts = <58>; |
| 182 | status = "disabled"; | ||
| 183 | }; | 210 | }; |
| 184 | 211 | ||
| 185 | wdog@53f9c000 { /* WDOG2 */ | 212 | wdog@53f9c000 { /* WDOG2 */ |
| @@ -189,6 +216,161 @@ | |||
| 189 | status = "disabled"; | 216 | status = "disabled"; |
| 190 | }; | 217 | }; |
| 191 | 218 | ||
| 219 | iomuxc@53fa8000 { | ||
| 220 | compatible = "fsl,imx53-iomuxc"; | ||
| 221 | reg = <0x53fa8000 0x4000>; | ||
| 222 | |||
| 223 | audmux { | ||
| 224 | pinctrl_audmux_1: audmuxgrp-1 { | ||
| 225 | fsl,pins = < | ||
| 226 | 10 0x80000000 /* MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC */ | ||
| 227 | 17 0x80000000 /* MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD */ | ||
| 228 | 23 0x80000000 /* MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS */ | ||
| 229 | 30 0x80000000 /* MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD */ | ||
| 230 | >; | ||
| 231 | }; | ||
| 232 | }; | ||
| 233 | |||
| 234 | fec { | ||
| 235 | pinctrl_fec_1: fecgrp-1 { | ||
| 236 | fsl,pins = < | ||
| 237 | 820 0x80000000 /* MX53_PAD_FEC_MDC__FEC_MDC */ | ||
| 238 | 779 0x80000000 /* MX53_PAD_FEC_MDIO__FEC_MDIO */ | ||
| 239 | 786 0x80000000 /* MX53_PAD_FEC_REF_CLK__FEC_TX_CLK */ | ||
| 240 | 791 0x80000000 /* MX53_PAD_FEC_RX_ER__FEC_RX_ER */ | ||
| 241 | 796 0x80000000 /* MX53_PAD_FEC_CRS_DV__FEC_RX_DV */ | ||
| 242 | 799 0x80000000 /* MX53_PAD_FEC_RXD1__FEC_RDATA_1 */ | ||
| 243 | 804 0x80000000 /* MX53_PAD_FEC_RXD0__FEC_RDATA_0 */ | ||
| 244 | 808 0x80000000 /* MX53_PAD_FEC_TX_EN__FEC_TX_EN */ | ||
| 245 | 811 0x80000000 /* MX53_PAD_FEC_TXD1__FEC_TDATA_1 */ | ||
| 246 | 816 0x80000000 /* MX53_PAD_FEC_TXD0__FEC_TDATA_0 */ | ||
| 247 | >; | ||
| 248 | }; | ||
| 249 | }; | ||
| 250 | |||
| 251 | ecspi1 { | ||
| 252 | pinctrl_ecspi1_1: ecspi1grp-1 { | ||
| 253 | fsl,pins = < | ||
| 254 | 433 0x80000000 /* MX53_PAD_EIM_D16__ECSPI1_SCLK */ | ||
| 255 | 439 0x80000000 /* MX53_PAD_EIM_D17__ECSPI1_MISO */ | ||
| 256 | 445 0x80000000 /* MX53_PAD_EIM_D18__ECSPI1_MOSI */ | ||
| 257 | >; | ||
| 258 | }; | ||
| 259 | }; | ||
| 260 | |||
| 261 | esdhc1 { | ||
| 262 | pinctrl_esdhc1_1: esdhc1grp-1 { | ||
| 263 | fsl,pins = < | ||
| 264 | 995 0x1d5 /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */ | ||
| 265 | 1000 0x1d5 /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */ | ||
| 266 | 1010 0x1d5 /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */ | ||
| 267 | 1024 0x1d5 /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */ | ||
| 268 | 1005 0x1d5 /* MX53_PAD_SD1_CMD__ESDHC1_CMD */ | ||
| 269 | 1018 0x1d5 /* MX53_PAD_SD1_CLK__ESDHC1_CLK */ | ||
| 270 | >; | ||
| 271 | }; | ||
| 272 | |||
| 273 | pinctrl_esdhc1_2: esdhc1grp-2 { | ||
| 274 | fsl,pins = < | ||
| 275 | 995 0x1d5 /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */ | ||
| 276 | 1000 0x1d5 /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */ | ||
| 277 | 1010 0x1d5 /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */ | ||
| 278 | 1024 0x1d5 /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */ | ||
| 279 | 941 0x1d5 /* MX53_PAD_PATA_DATA8__ESDHC1_DAT4 */ | ||
| 280 | 948 0x1d5 /* MX53_PAD_PATA_DATA9__ESDHC1_DAT5 */ | ||
| 281 | 955 0x1d5 /* MX53_PAD_PATA_DATA10__ESDHC1_DAT6 */ | ||
| 282 | 962 0x1d5 /* MX53_PAD_PATA_DATA11__ESDHC1_DAT7 */ | ||
| 283 | 1005 0x1d5 /* MX53_PAD_SD1_CMD__ESDHC1_CMD */ | ||
| 284 | 1018 0x1d5 /* MX53_PAD_SD1_CLK__ESDHC1_CLK */ | ||
| 285 | >; | ||
| 286 | }; | ||
| 287 | }; | ||
| 288 | |||
| 289 | esdhc2 { | ||
| 290 | pinctrl_esdhc2_1: esdhc2grp-1 { | ||
| 291 | fsl,pins = < | ||
| 292 | 1038 0x1d5 /* MX53_PAD_SD2_CMD__ESDHC2_CMD */ | ||
| 293 | 1032 0x1d5 /* MX53_PAD_SD2_CLK__ESDHC2_CLK */ | ||
| 294 | 1062 0x1d5 /* MX53_PAD_SD2_DATA0__ESDHC2_DAT0 */ | ||
| 295 | 1056 0x1d5 /* MX53_PAD_SD2_DATA1__ESDHC2_DAT1 */ | ||
| 296 | 1050 0x1d5 /* MX53_PAD_SD2_DATA2__ESDHC2_DAT2 */ | ||
| 297 | 1044 0x1d5 /* MX53_PAD_SD2_DATA3__ESDHC2_DAT3 */ | ||
| 298 | >; | ||
| 299 | }; | ||
| 300 | }; | ||
| 301 | |||
| 302 | esdhc3 { | ||
| 303 | pinctrl_esdhc3_1: esdhc3grp-1 { | ||
| 304 | fsl,pins = < | ||
| 305 | 943 0x1d5 /* MX53_PAD_PATA_DATA8__ESDHC3_DAT0 */ | ||
| 306 | 950 0x1d5 /* MX53_PAD_PATA_DATA9__ESDHC3_DAT1 */ | ||
| 307 | 957 0x1d5 /* MX53_PAD_PATA_DATA10__ESDHC3_DAT2 */ | ||
| 308 | 964 0x1d5 /* MX53_PAD_PATA_DATA11__ESDHC3_DAT3 */ | ||
| 309 | 893 0x1d5 /* MX53_PAD_PATA_DATA0__ESDHC3_DAT4 */ | ||
| 310 | 900 0x1d5 /* MX53_PAD_PATA_DATA1__ESDHC3_DAT5 */ | ||
| 311 | 906 0x1d5 /* MX53_PAD_PATA_DATA2__ESDHC3_DAT6 */ | ||
| 312 | 912 0x1d5 /* MX53_PAD_PATA_DATA3__ESDHC3_DAT7 */ | ||
| 313 | 857 0x1d5 /* MX53_PAD_PATA_RESET_B__ESDHC3_CMD */ | ||
| 314 | 863 0x1d5 /* MX53_PAD_PATA_IORDY__ESDHC3_CLK */ | ||
| 315 | >; | ||
| 316 | }; | ||
| 317 | }; | ||
| 318 | |||
| 319 | i2c1 { | ||
| 320 | pinctrl_i2c1_1: i2c1grp-1 { | ||
| 321 | fsl,pins = < | ||
| 322 | 333 0xc0000000 /* MX53_PAD_CSI0_DAT8__I2C1_SDA */ | ||
| 323 | 341 0xc0000000 /* MX53_PAD_CSI0_DAT9__I2C1_SCL */ | ||
| 324 | >; | ||
| 325 | }; | ||
| 326 | }; | ||
| 327 | |||
| 328 | i2c2 { | ||
| 329 | pinctrl_i2c2_1: i2c2grp-1 { | ||
| 330 | fsl,pins = < | ||
| 331 | 61 0xc0000000 /* MX53_PAD_KEY_ROW3__I2C2_SDA */ | ||
| 332 | 53 0xc0000000 /* MX53_PAD_KEY_COL3__I2C2_SCL */ | ||
| 333 | >; | ||
| 334 | }; | ||
| 335 | }; | ||
| 336 | |||
| 337 | uart1 { | ||
| 338 | pinctrl_uart1_1: uart1grp-1 { | ||
| 339 | fsl,pins = < | ||
| 340 | 346 0x1c5 /* MX53_PAD_CSI0_DAT10__UART1_TXD_MUX */ | ||
| 341 | 354 0x1c5 /* MX53_PAD_CSI0_DAT11__UART1_RXD_MUX */ | ||
| 342 | >; | ||
| 343 | }; | ||
| 344 | |||
| 345 | pinctrl_uart1_2: uart1grp-2 { | ||
| 346 | fsl,pins = < | ||
| 347 | 828 0x1c5 /* MX53_PAD_PATA_DIOW__UART1_TXD_MUX */ | ||
| 348 | 832 0x1c5 /* MX53_PAD_PATA_DMACK__UART1_RXD_MUX */ | ||
| 349 | >; | ||
| 350 | }; | ||
| 351 | }; | ||
| 352 | |||
| 353 | uart2 { | ||
| 354 | pinctrl_uart2_1: uart2grp-1 { | ||
| 355 | fsl,pins = < | ||
| 356 | 841 0x1c5 /* MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX */ | ||
| 357 | 836 0x1c5 /* MX53_PAD_PATA_DMARQ__UART2_TXD_MUX */ | ||
| 358 | >; | ||
| 359 | }; | ||
| 360 | }; | ||
| 361 | |||
| 362 | uart3 { | ||
| 363 | pinctrl_uart3_1: uart3grp-1 { | ||
| 364 | fsl,pins = < | ||
| 365 | 884 0x1c5 /* MX53_PAD_PATA_CS_0__UART3_TXD_MUX */ | ||
| 366 | 888 0x1c5 /* MX53_PAD_PATA_CS_1__UART3_RXD_MUX */ | ||
| 367 | 875 0x1c5 /* MX53_PAD_PATA_DA_1__UART3_CTS */ | ||
| 368 | 880 0x1c5 /* MX53_PAD_PATA_DA_2__UART3_RTS */ | ||
| 369 | >; | ||
| 370 | }; | ||
| 371 | }; | ||
| 372 | }; | ||
| 373 | |||
| 192 | uart1: serial@53fbc000 { | 374 | uart1: serial@53fbc000 { |
| 193 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; | 375 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; |
| 194 | reg = <0x53fbc000 0x4000>; | 376 | reg = <0x53fbc000 0x4000>; |
| @@ -203,6 +385,20 @@ | |||
| 203 | status = "disabled"; | 385 | status = "disabled"; |
| 204 | }; | 386 | }; |
| 205 | 387 | ||
| 388 | can1: can@53fc8000 { | ||
| 389 | compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan"; | ||
| 390 | reg = <0x53fc8000 0x4000>; | ||
| 391 | interrupts = <82>; | ||
| 392 | status = "disabled"; | ||
| 393 | }; | ||
| 394 | |||
| 395 | can2: can@53fcc000 { | ||
| 396 | compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan"; | ||
| 397 | reg = <0x53fcc000 0x4000>; | ||
| 398 | interrupts = <83>; | ||
| 399 | status = "disabled"; | ||
| 400 | }; | ||
| 401 | |||
| 206 | gpio5: gpio@53fdc000 { | 402 | gpio5: gpio@53fdc000 { |
| 207 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; | 403 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
| 208 | reg = <0x53fdc000 0x4000>; | 404 | reg = <0x53fdc000 0x4000>; |
| @@ -277,6 +473,7 @@ | |||
| 277 | compatible = "fsl,imx53-sdma", "fsl,imx35-sdma"; | 473 | compatible = "fsl,imx53-sdma", "fsl,imx35-sdma"; |
| 278 | reg = <0x63fb0000 0x4000>; | 474 | reg = <0x63fb0000 0x4000>; |
| 279 | interrupts = <6>; | 475 | interrupts = <6>; |
| 476 | fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; | ||
| 280 | }; | 477 | }; |
| 281 | 478 | ||
| 282 | cspi@63fc0000 { | 479 | cspi@63fc0000 { |
diff --git a/arch/arm/boot/dts/imx6q-arm2.dts b/arch/arm/boot/dts/imx6q-arm2.dts index d792581672cc..15df4c105e89 100644 --- a/arch/arm/boot/dts/imx6q-arm2.dts +++ b/arch/arm/boot/dts/imx6q-arm2.dts | |||
| @@ -28,8 +28,27 @@ | |||
| 28 | status = "disabled"; /* gpmi nand conflicts with SD */ | 28 | status = "disabled"; /* gpmi nand conflicts with SD */ |
| 29 | }; | 29 | }; |
| 30 | 30 | ||
| 31 | aips-bus@02000000 { /* AIPS1 */ | ||
| 32 | iomuxc@020e0000 { | ||
| 33 | pinctrl-names = "default"; | ||
| 34 | pinctrl-0 = <&pinctrl_hog>; | ||
| 35 | |||
| 36 | hog { | ||
| 37 | pinctrl_hog: hoggrp { | ||
| 38 | fsl,pins = < | ||
| 39 | 176 0x80000000 /* MX6Q_PAD_EIM_D25__GPIO_3_25 */ | ||
| 40 | 1363 0x80000000 /* MX6Q_PAD_NANDF_CS0__GPIO_6_11 */ | ||
| 41 | 1369 0x80000000 /* MX6Q_PAD_NANDF_CS1__GPIO_6_14 */ | ||
| 42 | >; | ||
| 43 | }; | ||
| 44 | }; | ||
| 45 | }; | ||
| 46 | }; | ||
| 47 | |||
| 31 | aips-bus@02100000 { /* AIPS2 */ | 48 | aips-bus@02100000 { /* AIPS2 */ |
| 32 | ethernet@02188000 { | 49 | ethernet@02188000 { |
| 50 | pinctrl-names = "default"; | ||
| 51 | pinctrl-0 = <&pinctrl_enet_2>; | ||
| 33 | phy-mode = "rgmii"; | 52 | phy-mode = "rgmii"; |
| 34 | status = "okay"; | 53 | status = "okay"; |
| 35 | }; | 54 | }; |
| @@ -52,6 +71,8 @@ | |||
| 52 | }; | 71 | }; |
| 53 | 72 | ||
| 54 | uart4: serial@021f0000 { | 73 | uart4: serial@021f0000 { |
| 74 | pinctrl-names = "default"; | ||
| 75 | pinctrl-0 = <&pinctrl_uart4_1>; | ||
| 55 | status = "okay"; | 76 | status = "okay"; |
| 56 | }; | 77 | }; |
| 57 | }; | 78 | }; |
diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts index 72f30f3e6171..d152328285a1 100644 --- a/arch/arm/boot/dts/imx6q-sabrelite.dts +++ b/arch/arm/boot/dts/imx6q-sabrelite.dts | |||
| @@ -46,15 +46,20 @@ | |||
| 46 | 46 | ||
| 47 | iomuxc@020e0000 { | 47 | iomuxc@020e0000 { |
| 48 | pinctrl-names = "default"; | 48 | pinctrl-names = "default"; |
| 49 | pinctrl-0 = <&pinctrl_gpio_hog>; | 49 | pinctrl-0 = <&pinctrl_hog>; |
| 50 | 50 | ||
| 51 | gpios { | 51 | hog { |
| 52 | pinctrl_gpio_hog: gpiohog { | 52 | pinctrl_hog: hoggrp { |
| 53 | fsl,pins = < | 53 | fsl,pins = < |
| 54 | 144 0x80000000 /* MX6Q_PAD_EIM_D22__GPIO_3_22 */ | 54 | 1450 0x80000000 /* MX6Q_PAD_NANDF_D6__GPIO_2_6 */ |
| 55 | 121 0x80000000 /* MX6Q_PAD_EIM_D19__GPIO_3_19 */ | 55 | 1458 0x80000000 /* MX6Q_PAD_NANDF_D7__GPIO_2_7 */ |
| 56 | 953 0x80000000 /* MX6Q_PAD_GPIO_0__CCM_CLKO */ | 56 | 121 0x80000000 /* MX6Q_PAD_EIM_D19__GPIO_3_19 */ |
| 57 | >; | 57 | 144 0x80000000 /* MX6Q_PAD_EIM_D22__GPIO_3_22 */ |
| 58 | 152 0x80000000 /* MX6Q_PAD_EIM_D23__GPIO_3_23 */ | ||
| 59 | 1262 0x80000000 /* MX6Q_PAD_SD3_DAT5__GPIO_7_0 */ | ||
| 60 | 1270 0x1f0b0 /* MX6Q_PAD_SD3_DAT4__GPIO_7_1 */ | ||
| 61 | 953 0x80000000 /* MX6Q_PAD_GPIO_0__CCM_CLKO */ | ||
| 62 | >; | ||
| 58 | }; | 63 | }; |
| 59 | }; | 64 | }; |
| 60 | }; | 65 | }; |
| @@ -63,6 +68,9 @@ | |||
| 63 | aips-bus@02100000 { /* AIPS2 */ | 68 | aips-bus@02100000 { /* AIPS2 */ |
| 64 | usb@02184000 { /* USB OTG */ | 69 | usb@02184000 { /* USB OTG */ |
| 65 | vbus-supply = <®_usb_otg_vbus>; | 70 | vbus-supply = <®_usb_otg_vbus>; |
| 71 | pinctrl-names = "default"; | ||
| 72 | pinctrl-0 = <&pinctrl_usbotg_1>; | ||
| 73 | disable-over-current; | ||
| 66 | status = "okay"; | 74 | status = "okay"; |
| 67 | }; | 75 | }; |
| 68 | 76 | ||
| @@ -71,12 +79,16 @@ | |||
| 71 | }; | 79 | }; |
| 72 | 80 | ||
| 73 | ethernet@02188000 { | 81 | ethernet@02188000 { |
| 82 | pinctrl-names = "default"; | ||
| 83 | pinctrl-0 = <&pinctrl_enet_1>; | ||
| 74 | phy-mode = "rgmii"; | 84 | phy-mode = "rgmii"; |
| 75 | phy-reset-gpios = <&gpio3 23 0>; | 85 | phy-reset-gpios = <&gpio3 23 0>; |
| 76 | status = "okay"; | 86 | status = "okay"; |
| 77 | }; | 87 | }; |
| 78 | 88 | ||
| 79 | usdhc@02198000 { /* uSDHC3 */ | 89 | usdhc@02198000 { /* uSDHC3 */ |
| 90 | pinctrl-names = "default"; | ||
| 91 | pinctrl-0 = <&pinctrl_usdhc3_2>; | ||
| 80 | cd-gpios = <&gpio7 0 0>; | 92 | cd-gpios = <&gpio7 0 0>; |
| 81 | wp-gpios = <&gpio7 1 0>; | 93 | wp-gpios = <&gpio7 1 0>; |
| 82 | vmmc-supply = <®_3p3v>; | 94 | vmmc-supply = <®_3p3v>; |
| @@ -84,6 +96,8 @@ | |||
| 84 | }; | 96 | }; |
| 85 | 97 | ||
| 86 | usdhc@0219c000 { /* uSDHC4 */ | 98 | usdhc@0219c000 { /* uSDHC4 */ |
| 99 | pinctrl-names = "default"; | ||
| 100 | pinctrl-0 = <&pinctrl_usdhc4_2>; | ||
| 87 | cd-gpios = <&gpio2 6 0>; | 101 | cd-gpios = <&gpio2 6 0>; |
| 88 | wp-gpios = <&gpio2 7 0>; | 102 | wp-gpios = <&gpio2 7 0>; |
| 89 | vmmc-supply = <®_3p3v>; | 103 | vmmc-supply = <®_3p3v>; |
| @@ -99,7 +113,7 @@ | |||
| 99 | uart2: serial@021e8000 { | 113 | uart2: serial@021e8000 { |
| 100 | status = "okay"; | 114 | status = "okay"; |
| 101 | pinctrl-names = "default"; | 115 | pinctrl-names = "default"; |
| 102 | pinctrl-0 = <&pinctrl_serial2_1>; | 116 | pinctrl-0 = <&pinctrl_uart2_1>; |
| 103 | }; | 117 | }; |
| 104 | 118 | ||
| 105 | i2c@021a0000 { /* I2C1 */ | 119 | i2c@021a0000 { /* I2C1 */ |
| @@ -111,6 +125,7 @@ | |||
| 111 | codec: sgtl5000@0a { | 125 | codec: sgtl5000@0a { |
| 112 | compatible = "fsl,sgtl5000"; | 126 | compatible = "fsl,sgtl5000"; |
| 113 | reg = <0x0a>; | 127 | reg = <0x0a>; |
| 128 | clocks = <&clks 169>; | ||
| 114 | VDDA-supply = <®_2p5v>; | 129 | VDDA-supply = <®_2p5v>; |
| 115 | VDDIO-supply = <®_3p3v>; | 130 | VDDIO-supply = <®_3p3v>; |
| 116 | }; | 131 | }; |
diff --git a/arch/arm/boot/dts/imx6q-sabresd.dts b/arch/arm/boot/dts/imx6q-sabresd.dts index 07509a181178..e596c28c214d 100644 --- a/arch/arm/boot/dts/imx6q-sabresd.dts +++ b/arch/arm/boot/dts/imx6q-sabresd.dts | |||
| @@ -22,28 +22,51 @@ | |||
| 22 | }; | 22 | }; |
| 23 | 23 | ||
| 24 | soc { | 24 | soc { |
| 25 | |||
| 26 | aips-bus@02000000 { /* AIPS1 */ | 25 | aips-bus@02000000 { /* AIPS1 */ |
| 27 | spba-bus@02000000 { | 26 | spba-bus@02000000 { |
| 28 | uart1: serial@02020000 { | 27 | uart1: serial@02020000 { |
| 28 | pinctrl-names = "default"; | ||
| 29 | pinctrl-0 = <&pinctrl_uart1_1>; | ||
| 29 | status = "okay"; | 30 | status = "okay"; |
| 30 | }; | 31 | }; |
| 31 | }; | 32 | }; |
| 33 | |||
| 34 | iomuxc@020e0000 { | ||
| 35 | pinctrl-names = "default"; | ||
| 36 | pinctrl-0 = <&pinctrl_hog>; | ||
| 37 | |||
| 38 | hog { | ||
| 39 | pinctrl_hog: hoggrp { | ||
| 40 | fsl,pins = < | ||
| 41 | 1402 0x80000000 /* MX6Q_PAD_NANDF_D0__GPIO_2_0 */ | ||
| 42 | 1410 0x80000000 /* MX6Q_PAD_NANDF_D1__GPIO_2_1 */ | ||
| 43 | 1418 0x80000000 /* MX6Q_PAD_NANDF_D2__GPIO_2_2 */ | ||
| 44 | 1426 0x80000000 /* MX6Q_PAD_NANDF_D3__GPIO_2_3 */ | ||
| 45 | >; | ||
| 46 | }; | ||
| 47 | }; | ||
| 48 | }; | ||
| 32 | }; | 49 | }; |
| 33 | 50 | ||
| 34 | aips-bus@02100000 { /* AIPS2 */ | 51 | aips-bus@02100000 { /* AIPS2 */ |
| 35 | ethernet@02188000 { | 52 | ethernet@02188000 { |
| 53 | pinctrl-names = "default"; | ||
| 54 | pinctrl-0 = <&pinctrl_enet_1>; | ||
| 36 | phy-mode = "rgmii"; | 55 | phy-mode = "rgmii"; |
| 37 | status = "okay"; | 56 | status = "okay"; |
| 38 | }; | 57 | }; |
| 39 | 58 | ||
| 40 | usdhc@02194000 { /* uSDHC2 */ | 59 | usdhc@02194000 { /* uSDHC2 */ |
| 60 | pinctrl-names = "default"; | ||
| 61 | pinctrl-0 = <&pinctrl_usdhc2_1>; | ||
| 41 | cd-gpios = <&gpio2 2 0>; | 62 | cd-gpios = <&gpio2 2 0>; |
| 42 | wp-gpios = <&gpio2 3 0>; | 63 | wp-gpios = <&gpio2 3 0>; |
| 43 | status = "okay"; | 64 | status = "okay"; |
| 44 | }; | 65 | }; |
| 45 | 66 | ||
| 46 | usdhc@02198000 { /* uSDHC3 */ | 67 | usdhc@02198000 { /* uSDHC3 */ |
| 68 | pinctrl-names = "default"; | ||
| 69 | pinctrl-0 = <&pinctrl_usdhc3_1>; | ||
| 47 | cd-gpios = <&gpio2 0 0>; | 70 | cd-gpios = <&gpio2 0 0>; |
| 48 | wp-gpios = <&gpio2 1 0>; | 71 | wp-gpios = <&gpio2 1 0>; |
| 49 | status = "okay"; | 72 | status = "okay"; |
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index fd57079f71a9..35e5895ba3df 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi | |||
| @@ -97,18 +97,23 @@ | |||
| 97 | dma-apbh@00110000 { | 97 | dma-apbh@00110000 { |
| 98 | compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; | 98 | compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; |
| 99 | reg = <0x00110000 0x2000>; | 99 | reg = <0x00110000 0x2000>; |
| 100 | clocks = <&clks 106>; | ||
| 100 | }; | 101 | }; |
| 101 | 102 | ||
| 102 | gpmi-nand@00112000 { | 103 | gpmi-nand@00112000 { |
| 103 | compatible = "fsl,imx6q-gpmi-nand"; | 104 | compatible = "fsl,imx6q-gpmi-nand"; |
| 104 | #address-cells = <1>; | 105 | #address-cells = <1>; |
| 105 | #size-cells = <1>; | 106 | #size-cells = <1>; |
| 106 | reg = <0x00112000 0x2000>, <0x00114000 0x2000>; | 107 | reg = <0x00112000 0x2000>, <0x00114000 0x2000>; |
| 107 | reg-names = "gpmi-nand", "bch"; | 108 | reg-names = "gpmi-nand", "bch"; |
| 108 | interrupts = <0 13 0x04>, <0 15 0x04>; | 109 | interrupts = <0 13 0x04>, <0 15 0x04>; |
| 109 | interrupt-names = "gpmi-dma", "bch"; | 110 | interrupt-names = "gpmi-dma", "bch"; |
| 110 | fsl,gpmi-dma-channel = <0>; | 111 | clocks = <&clks 152>, <&clks 153>, <&clks 151>, |
| 111 | status = "disabled"; | 112 | <&clks 150>, <&clks 149>; |
| 113 | clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", | ||
| 114 | "gpmi_bch_apb", "per1_bch"; | ||
| 115 | fsl,gpmi-dma-channel = <0>; | ||
| 116 | status = "disabled"; | ||
| 112 | }; | 117 | }; |
| 113 | 118 | ||
| 114 | timer@00a00600 { | 119 | timer@00a00600 { |
| @@ -150,6 +155,8 @@ | |||
| 150 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; | 155 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; |
| 151 | reg = <0x02008000 0x4000>; | 156 | reg = <0x02008000 0x4000>; |
| 152 | interrupts = <0 31 0x04>; | 157 | interrupts = <0 31 0x04>; |
| 158 | clocks = <&clks 112>, <&clks 112>; | ||
| 159 | clock-names = "ipg", "per"; | ||
| 153 | status = "disabled"; | 160 | status = "disabled"; |
| 154 | }; | 161 | }; |
| 155 | 162 | ||
| @@ -159,6 +166,8 @@ | |||
| 159 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; | 166 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; |
| 160 | reg = <0x0200c000 0x4000>; | 167 | reg = <0x0200c000 0x4000>; |
| 161 | interrupts = <0 32 0x04>; | 168 | interrupts = <0 32 0x04>; |
| 169 | clocks = <&clks 113>, <&clks 113>; | ||
| 170 | clock-names = "ipg", "per"; | ||
| 162 | status = "disabled"; | 171 | status = "disabled"; |
| 163 | }; | 172 | }; |
| 164 | 173 | ||
| @@ -168,6 +177,8 @@ | |||
| 168 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; | 177 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; |
| 169 | reg = <0x02010000 0x4000>; | 178 | reg = <0x02010000 0x4000>; |
| 170 | interrupts = <0 33 0x04>; | 179 | interrupts = <0 33 0x04>; |
| 180 | clocks = <&clks 114>, <&clks 114>; | ||
| 181 | clock-names = "ipg", "per"; | ||
| 171 | status = "disabled"; | 182 | status = "disabled"; |
| 172 | }; | 183 | }; |
| 173 | 184 | ||
| @@ -177,6 +188,8 @@ | |||
| 177 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; | 188 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; |
| 178 | reg = <0x02014000 0x4000>; | 189 | reg = <0x02014000 0x4000>; |
| 179 | interrupts = <0 34 0x04>; | 190 | interrupts = <0 34 0x04>; |
| 191 | clocks = <&clks 115>, <&clks 115>; | ||
| 192 | clock-names = "ipg", "per"; | ||
| 180 | status = "disabled"; | 193 | status = "disabled"; |
| 181 | }; | 194 | }; |
| 182 | 195 | ||
| @@ -186,6 +199,8 @@ | |||
| 186 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; | 199 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; |
| 187 | reg = <0x02018000 0x4000>; | 200 | reg = <0x02018000 0x4000>; |
| 188 | interrupts = <0 35 0x04>; | 201 | interrupts = <0 35 0x04>; |
| 202 | clocks = <&clks 116>, <&clks 116>; | ||
| 203 | clock-names = "ipg", "per"; | ||
| 189 | status = "disabled"; | 204 | status = "disabled"; |
| 190 | }; | 205 | }; |
| 191 | 206 | ||
| @@ -193,6 +208,8 @@ | |||
| 193 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; | 208 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
| 194 | reg = <0x02020000 0x4000>; | 209 | reg = <0x02020000 0x4000>; |
| 195 | interrupts = <0 26 0x04>; | 210 | interrupts = <0 26 0x04>; |
| 211 | clocks = <&clks 160>, <&clks 161>; | ||
| 212 | clock-names = "ipg", "per"; | ||
| 196 | status = "disabled"; | 213 | status = "disabled"; |
| 197 | }; | 214 | }; |
| 198 | 215 | ||
| @@ -205,6 +222,7 @@ | |||
| 205 | compatible = "fsl,imx6q-ssi","fsl,imx21-ssi"; | 222 | compatible = "fsl,imx6q-ssi","fsl,imx21-ssi"; |
| 206 | reg = <0x02028000 0x4000>; | 223 | reg = <0x02028000 0x4000>; |
| 207 | interrupts = <0 46 0x04>; | 224 | interrupts = <0 46 0x04>; |
| 225 | clocks = <&clks 178>; | ||
| 208 | fsl,fifo-depth = <15>; | 226 | fsl,fifo-depth = <15>; |
| 209 | fsl,ssi-dma-events = <38 37>; | 227 | fsl,ssi-dma-events = <38 37>; |
| 210 | status = "disabled"; | 228 | status = "disabled"; |
| @@ -214,6 +232,7 @@ | |||
| 214 | compatible = "fsl,imx6q-ssi","fsl,imx21-ssi"; | 232 | compatible = "fsl,imx6q-ssi","fsl,imx21-ssi"; |
| 215 | reg = <0x0202c000 0x4000>; | 233 | reg = <0x0202c000 0x4000>; |
| 216 | interrupts = <0 47 0x04>; | 234 | interrupts = <0 47 0x04>; |
| 235 | clocks = <&clks 179>; | ||
| 217 | fsl,fifo-depth = <15>; | 236 | fsl,fifo-depth = <15>; |
| 218 | fsl,ssi-dma-events = <42 41>; | 237 | fsl,ssi-dma-events = <42 41>; |
| 219 | status = "disabled"; | 238 | status = "disabled"; |
| @@ -223,6 +242,7 @@ | |||
| 223 | compatible = "fsl,imx6q-ssi","fsl,imx21-ssi"; | 242 | compatible = "fsl,imx6q-ssi","fsl,imx21-ssi"; |
| 224 | reg = <0x02030000 0x4000>; | 243 | reg = <0x02030000 0x4000>; |
| 225 | interrupts = <0 48 0x04>; | 244 | interrupts = <0 48 0x04>; |
| 245 | clocks = <&clks 180>; | ||
| 226 | fsl,fifo-depth = <15>; | 246 | fsl,fifo-depth = <15>; |
| 227 | fsl,ssi-dma-events = <46 45>; | 247 | fsl,ssi-dma-events = <46 45>; |
| 228 | status = "disabled"; | 248 | status = "disabled"; |
| @@ -362,20 +382,22 @@ | |||
| 362 | compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; | 382 | compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; |
| 363 | reg = <0x020bc000 0x4000>; | 383 | reg = <0x020bc000 0x4000>; |
| 364 | interrupts = <0 80 0x04>; | 384 | interrupts = <0 80 0x04>; |
| 365 | status = "disabled"; | 385 | clocks = <&clks 0>; |
| 366 | }; | 386 | }; |
| 367 | 387 | ||
| 368 | wdog@020c0000 { /* WDOG2 */ | 388 | wdog@020c0000 { /* WDOG2 */ |
| 369 | compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; | 389 | compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; |
| 370 | reg = <0x020c0000 0x4000>; | 390 | reg = <0x020c0000 0x4000>; |
| 371 | interrupts = <0 81 0x04>; | 391 | interrupts = <0 81 0x04>; |
| 392 | clocks = <&clks 0>; | ||
| 372 | status = "disabled"; | 393 | status = "disabled"; |
| 373 | }; | 394 | }; |
| 374 | 395 | ||
| 375 | ccm@020c4000 { | 396 | clks: ccm@020c4000 { |
| 376 | compatible = "fsl,imx6q-ccm"; | 397 | compatible = "fsl,imx6q-ccm"; |
| 377 | reg = <0x020c4000 0x4000>; | 398 | reg = <0x020c4000 0x4000>; |
| 378 | interrupts = <0 87 0x04 0 88 0x04>; | 399 | interrupts = <0 87 0x04 0 88 0x04>; |
| 400 | #clock-cells = <1>; | ||
| 379 | }; | 401 | }; |
| 380 | 402 | ||
| 381 | anatop@020c8000 { | 403 | anatop@020c8000 { |
| @@ -472,12 +494,14 @@ | |||
| 472 | compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; | 494 | compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; |
| 473 | reg = <0x020c9000 0x1000>; | 495 | reg = <0x020c9000 0x1000>; |
| 474 | interrupts = <0 44 0x04>; | 496 | interrupts = <0 44 0x04>; |
| 497 | clocks = <&clks 182>; | ||
| 475 | }; | 498 | }; |
| 476 | 499 | ||
| 477 | usbphy2: usbphy@020ca000 { | 500 | usbphy2: usbphy@020ca000 { |
| 478 | compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; | 501 | compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; |
| 479 | reg = <0x020ca000 0x1000>; | 502 | reg = <0x020ca000 0x1000>; |
| 480 | interrupts = <0 45 0x04>; | 503 | interrupts = <0 45 0x04>; |
| 504 | clocks = <&clks 183>; | ||
| 481 | }; | 505 | }; |
| 482 | 506 | ||
| 483 | snvs@020cc000 { | 507 | snvs@020cc000 { |
| @@ -514,86 +538,207 @@ | |||
| 514 | /* shared pinctrl settings */ | 538 | /* shared pinctrl settings */ |
| 515 | audmux { | 539 | audmux { |
| 516 | pinctrl_audmux_1: audmux-1 { | 540 | pinctrl_audmux_1: audmux-1 { |
| 517 | fsl,pins = <18 0x80000000 /* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */ | 541 | fsl,pins = < |
| 518 | 1586 0x80000000 /* MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */ | 542 | 18 0x80000000 /* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */ |
| 519 | 11 0x80000000 /* MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */ | 543 | 1586 0x80000000 /* MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */ |
| 520 | 3 0x80000000>; /* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */ | 544 | 11 0x80000000 /* MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */ |
| 545 | 3 0x80000000 /* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */ | ||
| 546 | >; | ||
| 547 | }; | ||
| 548 | }; | ||
| 549 | |||
| 550 | ecspi1 { | ||
| 551 | pinctrl_ecspi1_1: ecspi1grp-1 { | ||
| 552 | fsl,pins = < | ||
| 553 | 101 0x100b1 /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */ | ||
| 554 | 109 0x100b1 /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */ | ||
| 555 | 94 0x100b1 /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */ | ||
| 556 | >; | ||
| 557 | }; | ||
| 558 | }; | ||
| 559 | |||
| 560 | enet { | ||
| 561 | pinctrl_enet_1: enetgrp-1 { | ||
| 562 | fsl,pins = < | ||
| 563 | 695 0x1b0b0 /* MX6Q_PAD_ENET_MDIO__ENET_MDIO */ | ||
| 564 | 756 0x1b0b0 /* MX6Q_PAD_ENET_MDC__ENET_MDC */ | ||
| 565 | 24 0x1b0b0 /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */ | ||
| 566 | 30 0x1b0b0 /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */ | ||
| 567 | 34 0x1b0b0 /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */ | ||
| 568 | 39 0x1b0b0 /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */ | ||
| 569 | 44 0x1b0b0 /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */ | ||
| 570 | 56 0x1b0b0 /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */ | ||
| 571 | 702 0x1b0b0 /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */ | ||
| 572 | 74 0x1b0b0 /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */ | ||
| 573 | 52 0x1b0b0 /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */ | ||
| 574 | 61 0x1b0b0 /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */ | ||
| 575 | 66 0x1b0b0 /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */ | ||
| 576 | 70 0x1b0b0 /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */ | ||
| 577 | 48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */ | ||
| 578 | >; | ||
| 579 | }; | ||
| 580 | |||
| 581 | pinctrl_enet_2: enetgrp-2 { | ||
| 582 | fsl,pins = < | ||
| 583 | 890 0x1b0b0 /* MX6Q_PAD_KEY_COL1__ENET_MDIO */ | ||
| 584 | 909 0x1b0b0 /* MX6Q_PAD_KEY_COL2__ENET_MDC */ | ||
| 585 | 24 0x1b0b0 /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */ | ||
| 586 | 30 0x1b0b0 /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */ | ||
| 587 | 34 0x1b0b0 /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */ | ||
| 588 | 39 0x1b0b0 /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */ | ||
| 589 | 44 0x1b0b0 /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */ | ||
| 590 | 56 0x1b0b0 /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */ | ||
| 591 | 702 0x1b0b0 /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */ | ||
| 592 | 74 0x1b0b0 /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */ | ||
| 593 | 52 0x1b0b0 /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */ | ||
| 594 | 61 0x1b0b0 /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */ | ||
| 595 | 66 0x1b0b0 /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */ | ||
| 596 | 70 0x1b0b0 /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */ | ||
| 597 | 48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */ | ||
| 598 | >; | ||
| 521 | }; | 599 | }; |
| 522 | }; | 600 | }; |
| 523 | 601 | ||
| 524 | gpmi-nand { | 602 | gpmi-nand { |
| 525 | pinctrl_gpmi_nand_1: gpmi-nand-1 { | 603 | pinctrl_gpmi_nand_1: gpmi-nand-1 { |
| 526 | fsl,pins = <1328 0xb0b1 /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */ | 604 | fsl,pins = < |
| 527 | 1336 0xb0b1 /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */ | 605 | 1328 0xb0b1 /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */ |
| 528 | 1344 0xb0b1 /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */ | 606 | 1336 0xb0b1 /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */ |
| 529 | 1352 0xb000 /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */ | 607 | 1344 0xb0b1 /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */ |
| 530 | 1360 0xb0b1 /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */ | 608 | 1352 0xb000 /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */ |
| 531 | 1365 0xb0b1 /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */ | 609 | 1360 0xb0b1 /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */ |
| 532 | 1371 0xb0b1 /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */ | 610 | 1365 0xb0b1 /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */ |
| 533 | 1378 0xb0b1 /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */ | 611 | 1371 0xb0b1 /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */ |
| 534 | 1387 0xb0b1 /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */ | 612 | 1378 0xb0b1 /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */ |
| 535 | 1393 0xb0b1 /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */ | 613 | 1387 0xb0b1 /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */ |
| 536 | 1397 0xb0b1 /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */ | 614 | 1393 0xb0b1 /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */ |
| 537 | 1405 0xb0b1 /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */ | 615 | 1397 0xb0b1 /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */ |
| 538 | 1413 0xb0b1 /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */ | 616 | 1405 0xb0b1 /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */ |
| 539 | 1421 0xb0b1 /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */ | 617 | 1413 0xb0b1 /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */ |
| 540 | 1429 0xb0b1 /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */ | 618 | 1421 0xb0b1 /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */ |
| 541 | 1437 0xb0b1 /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */ | 619 | 1429 0xb0b1 /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */ |
| 542 | 1445 0xb0b1 /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */ | 620 | 1437 0xb0b1 /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */ |
| 543 | 1453 0xb0b1 /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */ | 621 | 1445 0xb0b1 /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */ |
| 544 | 1463 0x00b1>; /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */ | 622 | 1453 0xb0b1 /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */ |
| 623 | 1463 0x00b1 /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */ | ||
| 624 | >; | ||
| 545 | }; | 625 | }; |
| 546 | }; | 626 | }; |
| 547 | 627 | ||
| 548 | i2c1 { | 628 | i2c1 { |
| 549 | pinctrl_i2c1_1: i2c1grp-1 { | 629 | pinctrl_i2c1_1: i2c1grp-1 { |
| 550 | fsl,pins = <137 0x4001b8b1 /* MX6Q_PAD_EIM_D21__I2C1_SCL */ | 630 | fsl,pins = < |
| 551 | 196 0x4001b8b1>; /* MX6Q_PAD_EIM_D28__I2C1_SDA */ | 631 | 137 0x4001b8b1 /* MX6Q_PAD_EIM_D21__I2C1_SCL */ |
| 632 | 196 0x4001b8b1 /* MX6Q_PAD_EIM_D28__I2C1_SDA */ | ||
| 633 | >; | ||
| 634 | }; | ||
| 635 | }; | ||
| 636 | |||
| 637 | uart1 { | ||
| 638 | pinctrl_uart1_1: uart1grp-1 { | ||
| 639 | fsl,pins = < | ||
| 640 | 1140 0x1b0b1 /* MX6Q_PAD_CSI0_DAT10__UART1_TXD */ | ||
| 641 | 1148 0x1b0b1 /* MX6Q_PAD_CSI0_DAT11__UART1_RXD */ | ||
| 642 | >; | ||
| 552 | }; | 643 | }; |
| 553 | }; | 644 | }; |
| 554 | 645 | ||
| 555 | serial2 { | 646 | uart2 { |
| 556 | pinctrl_serial2_1: serial2grp-1 { | 647 | pinctrl_uart2_1: uart2grp-1 { |
| 557 | fsl,pins = <183 0x1b0b1 /* MX6Q_PAD_EIM_D26__UART2_TXD */ | 648 | fsl,pins = < |
| 558 | 191 0x1b0b1>; /* MX6Q_PAD_EIM_D27__UART2_RXD */ | 649 | 183 0x1b0b1 /* MX6Q_PAD_EIM_D26__UART2_TXD */ |
| 650 | 191 0x1b0b1 /* MX6Q_PAD_EIM_D27__UART2_RXD */ | ||
| 651 | >; | ||
| 652 | }; | ||
| 653 | }; | ||
| 654 | |||
| 655 | uart4 { | ||
| 656 | pinctrl_uart4_1: uart4grp-1 { | ||
| 657 | fsl,pins = < | ||
| 658 | 877 0x1b0b1 /* MX6Q_PAD_KEY_COL0__UART4_TXD */ | ||
| 659 | 885 0x1b0b1 /* MX6Q_PAD_KEY_ROW0__UART4_RXD */ | ||
| 660 | >; | ||
| 661 | }; | ||
| 662 | }; | ||
| 663 | |||
| 664 | usbotg { | ||
| 665 | pinctrl_usbotg_1: usbotggrp-1 { | ||
| 666 | fsl,pins = < | ||
| 667 | 1592 0x17059 /* MX6Q_PAD_GPIO_1__ANATOP_USBOTG_ID */ | ||
| 668 | >; | ||
| 669 | }; | ||
| 670 | }; | ||
| 671 | |||
| 672 | usdhc2 { | ||
| 673 | pinctrl_usdhc2_1: usdhc2grp-1 { | ||
| 674 | fsl,pins = < | ||
| 675 | 1577 0x17059 /* MX6Q_PAD_SD2_CMD__USDHC2_CMD */ | ||
| 676 | 1569 0x10059 /* MX6Q_PAD_SD2_CLK__USDHC2_CLK */ | ||
| 677 | 16 0x17059 /* MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 */ | ||
| 678 | 0 0x17059 /* MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 */ | ||
| 679 | 8 0x17059 /* MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 */ | ||
| 680 | 1583 0x17059 /* MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 */ | ||
| 681 | 1430 0x17059 /* MX6Q_PAD_NANDF_D4__USDHC2_DAT4 */ | ||
| 682 | 1438 0x17059 /* MX6Q_PAD_NANDF_D5__USDHC2_DAT5 */ | ||
| 683 | 1446 0x17059 /* MX6Q_PAD_NANDF_D6__USDHC2_DAT6 */ | ||
| 684 | 1454 0x17059 /* MX6Q_PAD_NANDF_D7__USDHC2_DAT7 */ | ||
| 685 | >; | ||
| 559 | }; | 686 | }; |
| 560 | }; | 687 | }; |
| 561 | 688 | ||
| 562 | usdhc3 { | 689 | usdhc3 { |
| 563 | pinctrl_usdhc3_1: usdhc3grp-1 { | 690 | pinctrl_usdhc3_1: usdhc3grp-1 { |
| 564 | fsl,pins = <1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */ | 691 | fsl,pins = < |
| 565 | 1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */ | 692 | 1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */ |
| 566 | 1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */ | 693 | 1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */ |
| 567 | 1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */ | 694 | 1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */ |
| 568 | 1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */ | 695 | 1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */ |
| 569 | 1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */ | 696 | 1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */ |
| 570 | 1265 0x17059 /* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */ | 697 | 1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */ |
| 571 | 1257 0x17059 /* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */ | 698 | 1265 0x17059 /* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */ |
| 572 | 1249 0x17059 /* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */ | 699 | 1257 0x17059 /* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */ |
| 573 | 1241 0x17059>; /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */ | 700 | 1249 0x17059 /* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */ |
| 701 | 1241 0x17059 /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */ | ||
| 702 | >; | ||
| 703 | }; | ||
| 704 | |||
| 705 | pinctrl_usdhc3_2: usdhc3grp-2 { | ||
| 706 | fsl,pins = < | ||
| 707 | 1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */ | ||
| 708 | 1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */ | ||
| 709 | 1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */ | ||
| 710 | 1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */ | ||
| 711 | 1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */ | ||
| 712 | 1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */ | ||
| 713 | >; | ||
| 574 | }; | 714 | }; |
| 575 | }; | 715 | }; |
| 576 | 716 | ||
| 577 | usdhc4 { | 717 | usdhc4 { |
| 578 | pinctrl_usdhc4_1: usdhc4grp-1 { | 718 | pinctrl_usdhc4_1: usdhc4grp-1 { |
| 579 | fsl,pins = <1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */ | 719 | fsl,pins = < |
| 580 | 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */ | 720 | 1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */ |
| 581 | 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */ | 721 | 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */ |
| 582 | 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */ | 722 | 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */ |
| 583 | 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */ | 723 | 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */ |
| 584 | 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */ | 724 | 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */ |
| 585 | 1493 0x17059 /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */ | 725 | 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */ |
| 586 | 1501 0x17059 /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */ | 726 | 1493 0x17059 /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */ |
| 587 | 1509 0x17059 /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */ | 727 | 1501 0x17059 /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */ |
| 588 | 1517 0x17059>; /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */ | 728 | 1509 0x17059 /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */ |
| 729 | 1517 0x17059 /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */ | ||
| 730 | >; | ||
| 589 | }; | 731 | }; |
| 590 | }; | ||
| 591 | 732 | ||
| 592 | ecspi1 { | 733 | pinctrl_usdhc4_2: usdhc4grp-2 { |
| 593 | pinctrl_ecspi1_1: ecspi1grp-1 { | 734 | fsl,pins = < |
| 594 | fsl,pins = <101 0x100b1 /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */ | 735 | 1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */ |
| 595 | 109 0x100b1 /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */ | 736 | 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */ |
| 596 | 94 0x100b1>; /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */ | 737 | 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */ |
| 738 | 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */ | ||
| 739 | 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */ | ||
| 740 | 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */ | ||
| 741 | >; | ||
| 597 | }; | 742 | }; |
| 598 | }; | 743 | }; |
| 599 | }; | 744 | }; |
| @@ -612,6 +757,9 @@ | |||
| 612 | compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma"; | 757 | compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma"; |
| 613 | reg = <0x020ec000 0x4000>; | 758 | reg = <0x020ec000 0x4000>; |
| 614 | interrupts = <0 2 0x04>; | 759 | interrupts = <0 2 0x04>; |
| 760 | clocks = <&clks 155>, <&clks 155>; | ||
| 761 | clock-names = "ipg", "ahb"; | ||
| 762 | fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q-to1.bin"; | ||
| 615 | }; | 763 | }; |
| 616 | }; | 764 | }; |
| 617 | 765 | ||
| @@ -635,7 +783,9 @@ | |||
| 635 | compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; | 783 | compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; |
| 636 | reg = <0x02184000 0x200>; | 784 | reg = <0x02184000 0x200>; |
| 637 | interrupts = <0 43 0x04>; | 785 | interrupts = <0 43 0x04>; |
| 786 | clocks = <&clks 162>; | ||
| 638 | fsl,usbphy = <&usbphy1>; | 787 | fsl,usbphy = <&usbphy1>; |
| 788 | fsl,usbmisc = <&usbmisc 0>; | ||
| 639 | status = "disabled"; | 789 | status = "disabled"; |
| 640 | }; | 790 | }; |
| 641 | 791 | ||
| @@ -643,7 +793,9 @@ | |||
| 643 | compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; | 793 | compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; |
| 644 | reg = <0x02184200 0x200>; | 794 | reg = <0x02184200 0x200>; |
| 645 | interrupts = <0 40 0x04>; | 795 | interrupts = <0 40 0x04>; |
| 796 | clocks = <&clks 162>; | ||
| 646 | fsl,usbphy = <&usbphy2>; | 797 | fsl,usbphy = <&usbphy2>; |
| 798 | fsl,usbmisc = <&usbmisc 1>; | ||
| 647 | status = "disabled"; | 799 | status = "disabled"; |
| 648 | }; | 800 | }; |
| 649 | 801 | ||
| @@ -651,6 +803,8 @@ | |||
| 651 | compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; | 803 | compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; |
| 652 | reg = <0x02184400 0x200>; | 804 | reg = <0x02184400 0x200>; |
| 653 | interrupts = <0 41 0x04>; | 805 | interrupts = <0 41 0x04>; |
| 806 | clocks = <&clks 162>; | ||
| 807 | fsl,usbmisc = <&usbmisc 2>; | ||
| 654 | status = "disabled"; | 808 | status = "disabled"; |
| 655 | }; | 809 | }; |
| 656 | 810 | ||
| @@ -658,13 +812,24 @@ | |||
| 658 | compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; | 812 | compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; |
| 659 | reg = <0x02184600 0x200>; | 813 | reg = <0x02184600 0x200>; |
| 660 | interrupts = <0 42 0x04>; | 814 | interrupts = <0 42 0x04>; |
| 815 | clocks = <&clks 162>; | ||
| 816 | fsl,usbmisc = <&usbmisc 3>; | ||
| 661 | status = "disabled"; | 817 | status = "disabled"; |
| 662 | }; | 818 | }; |
| 663 | 819 | ||
| 820 | usbmisc: usbmisc@02184800 { | ||
| 821 | #index-cells = <1>; | ||
| 822 | compatible = "fsl,imx6q-usbmisc"; | ||
| 823 | reg = <0x02184800 0x200>; | ||
| 824 | clocks = <&clks 162>; | ||
| 825 | }; | ||
| 826 | |||
| 664 | ethernet@02188000 { | 827 | ethernet@02188000 { |
| 665 | compatible = "fsl,imx6q-fec"; | 828 | compatible = "fsl,imx6q-fec"; |
| 666 | reg = <0x02188000 0x4000>; | 829 | reg = <0x02188000 0x4000>; |
| 667 | interrupts = <0 118 0x04 0 119 0x04>; | 830 | interrupts = <0 118 0x04 0 119 0x04>; |
| 831 | clocks = <&clks 117>, <&clks 117>; | ||
| 832 | clock-names = "ipg", "ahb"; | ||
| 668 | status = "disabled"; | 833 | status = "disabled"; |
| 669 | }; | 834 | }; |
| 670 | 835 | ||
| @@ -677,6 +842,8 @@ | |||
| 677 | compatible = "fsl,imx6q-usdhc"; | 842 | compatible = "fsl,imx6q-usdhc"; |
| 678 | reg = <0x02190000 0x4000>; | 843 | reg = <0x02190000 0x4000>; |
| 679 | interrupts = <0 22 0x04>; | 844 | interrupts = <0 22 0x04>; |
| 845 | clocks = <&clks 163>, <&clks 163>, <&clks 163>; | ||
| 846 | clock-names = "ipg", "ahb", "per"; | ||
| 680 | status = "disabled"; | 847 | status = "disabled"; |
| 681 | }; | 848 | }; |
| 682 | 849 | ||
| @@ -684,6 +851,8 @@ | |||
| 684 | compatible = "fsl,imx6q-usdhc"; | 851 | compatible = "fsl,imx6q-usdhc"; |
| 685 | reg = <0x02194000 0x4000>; | 852 | reg = <0x02194000 0x4000>; |
| 686 | interrupts = <0 23 0x04>; | 853 | interrupts = <0 23 0x04>; |
| 854 | clocks = <&clks 164>, <&clks 164>, <&clks 164>; | ||
| 855 | clock-names = "ipg", "ahb", "per"; | ||
| 687 | status = "disabled"; | 856 | status = "disabled"; |
| 688 | }; | 857 | }; |
| 689 | 858 | ||
| @@ -691,6 +860,8 @@ | |||
| 691 | compatible = "fsl,imx6q-usdhc"; | 860 | compatible = "fsl,imx6q-usdhc"; |
| 692 | reg = <0x02198000 0x4000>; | 861 | reg = <0x02198000 0x4000>; |
| 693 | interrupts = <0 24 0x04>; | 862 | interrupts = <0 24 0x04>; |
| 863 | clocks = <&clks 165>, <&clks 165>, <&clks 165>; | ||
| 864 | clock-names = "ipg", "ahb", "per"; | ||
| 694 | status = "disabled"; | 865 | status = "disabled"; |
| 695 | }; | 866 | }; |
| 696 | 867 | ||
| @@ -698,6 +869,8 @@ | |||
| 698 | compatible = "fsl,imx6q-usdhc"; | 869 | compatible = "fsl,imx6q-usdhc"; |
| 699 | reg = <0x0219c000 0x4000>; | 870 | reg = <0x0219c000 0x4000>; |
| 700 | interrupts = <0 25 0x04>; | 871 | interrupts = <0 25 0x04>; |
| 872 | clocks = <&clks 166>, <&clks 166>, <&clks 166>; | ||
| 873 | clock-names = "ipg", "ahb", "per"; | ||
| 701 | status = "disabled"; | 874 | status = "disabled"; |
| 702 | }; | 875 | }; |
| 703 | 876 | ||
| @@ -707,6 +880,7 @@ | |||
| 707 | compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c"; | 880 | compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c"; |
| 708 | reg = <0x021a0000 0x4000>; | 881 | reg = <0x021a0000 0x4000>; |
| 709 | interrupts = <0 36 0x04>; | 882 | interrupts = <0 36 0x04>; |
| 883 | clocks = <&clks 125>; | ||
| 710 | status = "disabled"; | 884 | status = "disabled"; |
| 711 | }; | 885 | }; |
| 712 | 886 | ||
| @@ -716,6 +890,7 @@ | |||
| 716 | compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c"; | 890 | compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c"; |
| 717 | reg = <0x021a4000 0x4000>; | 891 | reg = <0x021a4000 0x4000>; |
| 718 | interrupts = <0 37 0x04>; | 892 | interrupts = <0 37 0x04>; |
| 893 | clocks = <&clks 126>; | ||
| 719 | status = "disabled"; | 894 | status = "disabled"; |
| 720 | }; | 895 | }; |
| 721 | 896 | ||
| @@ -725,6 +900,7 @@ | |||
| 725 | compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c"; | 900 | compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c"; |
| 726 | reg = <0x021a8000 0x4000>; | 901 | reg = <0x021a8000 0x4000>; |
| 727 | interrupts = <0 38 0x04>; | 902 | interrupts = <0 38 0x04>; |
| 903 | clocks = <&clks 127>; | ||
| 728 | status = "disabled"; | 904 | status = "disabled"; |
| 729 | }; | 905 | }; |
| 730 | 906 | ||
| @@ -788,6 +964,8 @@ | |||
| 788 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; | 964 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
| 789 | reg = <0x021e8000 0x4000>; | 965 | reg = <0x021e8000 0x4000>; |
| 790 | interrupts = <0 27 0x04>; | 966 | interrupts = <0 27 0x04>; |
| 967 | clocks = <&clks 160>, <&clks 161>; | ||
| 968 | clock-names = "ipg", "per"; | ||
| 791 | status = "disabled"; | 969 | status = "disabled"; |
| 792 | }; | 970 | }; |
| 793 | 971 | ||
| @@ -795,6 +973,8 @@ | |||
| 795 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; | 973 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
| 796 | reg = <0x021ec000 0x4000>; | 974 | reg = <0x021ec000 0x4000>; |
| 797 | interrupts = <0 28 0x04>; | 975 | interrupts = <0 28 0x04>; |
| 976 | clocks = <&clks 160>, <&clks 161>; | ||
| 977 | clock-names = "ipg", "per"; | ||
| 798 | status = "disabled"; | 978 | status = "disabled"; |
| 799 | }; | 979 | }; |
| 800 | 980 | ||
| @@ -802,6 +982,8 @@ | |||
| 802 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; | 982 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
| 803 | reg = <0x021f0000 0x4000>; | 983 | reg = <0x021f0000 0x4000>; |
| 804 | interrupts = <0 29 0x04>; | 984 | interrupts = <0 29 0x04>; |
| 985 | clocks = <&clks 160>, <&clks 161>; | ||
| 986 | clock-names = "ipg", "per"; | ||
| 805 | status = "disabled"; | 987 | status = "disabled"; |
| 806 | }; | 988 | }; |
| 807 | 989 | ||
| @@ -809,6 +991,8 @@ | |||
| 809 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; | 991 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
| 810 | reg = <0x021f4000 0x4000>; | 992 | reg = <0x021f4000 0x4000>; |
| 811 | interrupts = <0 30 0x04>; | 993 | interrupts = <0 30 0x04>; |
| 994 | clocks = <&clks 160>, <&clks 161>; | ||
| 995 | clock-names = "ipg", "per"; | ||
| 812 | status = "disabled"; | 996 | status = "disabled"; |
| 813 | }; | 997 | }; |
| 814 | }; | 998 | }; |
diff --git a/arch/arm/boot/dts/mmp2.dtsi b/arch/arm/boot/dts/mmp2.dtsi index 80f74e256408..0514fb41627e 100644 --- a/arch/arm/boot/dts/mmp2.dtsi +++ b/arch/arm/boot/dts/mmp2.dtsi | |||
| @@ -26,6 +26,11 @@ | |||
| 26 | interrupt-parent = <&intc>; | 26 | interrupt-parent = <&intc>; |
| 27 | ranges; | 27 | ranges; |
| 28 | 28 | ||
| 29 | L2: l2-cache { | ||
| 30 | compatible = "marvell,tauros2-cache"; | ||
| 31 | marvell,tauros2-cache-features = <0x3>; | ||
| 32 | }; | ||
| 33 | |||
| 29 | axi@d4200000 { /* AXI */ | 34 | axi@d4200000 { /* AXI */ |
| 30 | compatible = "mrvl,axi-bus", "simple-bus"; | 35 | compatible = "mrvl,axi-bus", "simple-bus"; |
| 31 | #address-cells = <1>; | 36 | #address-cells = <1>; |
diff --git a/arch/arm/boot/dts/msm8660-surf.dts b/arch/arm/boot/dts/msm8660-surf.dts index 45bc4bb04e57..31f2157cd7d7 100644 --- a/arch/arm/boot/dts/msm8660-surf.dts +++ b/arch/arm/boot/dts/msm8660-surf.dts | |||
| @@ -7,7 +7,7 @@ | |||
| 7 | compatible = "qcom,msm8660-surf", "qcom,msm8660"; | 7 | compatible = "qcom,msm8660-surf", "qcom,msm8660"; |
| 8 | interrupt-parent = <&intc>; | 8 | interrupt-parent = <&intc>; |
| 9 | 9 | ||
| 10 | intc: interrupt-controller@02080000 { | 10 | intc: interrupt-controller@2080000 { |
| 11 | compatible = "qcom,msm-8660-qgic"; | 11 | compatible = "qcom,msm-8660-qgic"; |
| 12 | interrupt-controller; | 12 | interrupt-controller; |
| 13 | #interrupt-cells = <3>; | 13 | #interrupt-cells = <3>; |
| @@ -15,6 +15,23 @@ | |||
| 15 | < 0x02081000 0x1000 >; | 15 | < 0x02081000 0x1000 >; |
| 16 | }; | 16 | }; |
| 17 | 17 | ||
| 18 | timer@2000004 { | ||
| 19 | compatible = "qcom,msm-gpt", "qcom,msm-timer"; | ||
| 20 | interrupts = <1 1 0x301>; | ||
| 21 | reg = <0x02000004 0x10>; | ||
| 22 | clock-frequency = <32768>; | ||
| 23 | cpu-offset = <0x40000>; | ||
| 24 | }; | ||
| 25 | |||
| 26 | timer@2000024 { | ||
| 27 | compatible = "qcom,msm-dgt", "qcom,msm-timer"; | ||
| 28 | interrupts = <1 0 0x301>; | ||
| 29 | reg = <0x02000024 0x10>, | ||
| 30 | <0x02000034 0x4>; | ||
| 31 | clock-frequency = <6750000>; | ||
| 32 | cpu-offset = <0x40000>; | ||
| 33 | }; | ||
| 34 | |||
| 18 | serial@19c400000 { | 35 | serial@19c400000 { |
| 19 | compatible = "qcom,msm-hsuart", "qcom,msm-uart"; | 36 | compatible = "qcom,msm-hsuart", "qcom,msm-uart"; |
| 20 | reg = <0x19c40000 0x1000>, | 37 | reg = <0x19c40000 0x1000>, |
diff --git a/arch/arm/boot/dts/msm8960-cdp.dts b/arch/arm/boot/dts/msm8960-cdp.dts new file mode 100644 index 000000000000..9e621b5ad3dd --- /dev/null +++ b/arch/arm/boot/dts/msm8960-cdp.dts | |||
| @@ -0,0 +1,41 @@ | |||
| 1 | /dts-v1/; | ||
| 2 | |||
| 3 | /include/ "skeleton.dtsi" | ||
| 4 | |||
| 5 | / { | ||
| 6 | model = "Qualcomm MSM8960 CDP"; | ||
| 7 | compatible = "qcom,msm8960-cdp", "qcom,msm8960"; | ||
| 8 | interrupt-parent = <&intc>; | ||
| 9 | |||
| 10 | intc: interrupt-controller@2000000 { | ||
| 11 | compatible = "qcom,msm-qgic2"; | ||
| 12 | interrupt-controller; | ||
| 13 | #interrupt-cells = <3>; | ||
| 14 | reg = < 0x02000000 0x1000 >, | ||
| 15 | < 0x02002000 0x1000 >; | ||
| 16 | }; | ||
| 17 | |||
| 18 | timer@200a004 { | ||
| 19 | compatible = "qcom,msm-gpt", "qcom,msm-timer"; | ||
| 20 | interrupts = <1 2 0x301>; | ||
| 21 | reg = <0x0200a004 0x10>; | ||
| 22 | clock-frequency = <32768>; | ||
| 23 | cpu-offset = <0x80000>; | ||
| 24 | }; | ||
| 25 | |||
| 26 | timer@200a024 { | ||
| 27 | compatible = "qcom,msm-dgt", "qcom,msm-timer"; | ||
| 28 | interrupts = <1 1 0x301>; | ||
| 29 | reg = <0x0200a024 0x10>, | ||
| 30 | <0x0200a034 0x4>; | ||
| 31 | clock-frequency = <6750000>; | ||
| 32 | cpu-offset = <0x80000>; | ||
| 33 | }; | ||
| 34 | |||
| 35 | serial@19c400000 { | ||
| 36 | compatible = "qcom,msm-hsuart", "qcom,msm-uart"; | ||
| 37 | reg = <0x16440000 0x1000>, | ||
| 38 | <0x16400000 0x1000>; | ||
| 39 | interrupts = <0 154 0x0>; | ||
| 40 | }; | ||
| 41 | }; | ||
diff --git a/arch/arm/boot/dts/omap2420-h4.dts b/arch/arm/boot/dts/omap2420-h4.dts index 25b50b759dec..77b84e17c477 100644 --- a/arch/arm/boot/dts/omap2420-h4.dts +++ b/arch/arm/boot/dts/omap2420-h4.dts | |||
| @@ -7,7 +7,7 @@ | |||
| 7 | */ | 7 | */ |
| 8 | /dts-v1/; | 8 | /dts-v1/; |
| 9 | 9 | ||
| 10 | /include/ "omap2.dtsi" | 10 | /include/ "omap2420.dtsi" |
| 11 | 11 | ||
| 12 | / { | 12 | / { |
| 13 | model = "TI OMAP2420 H4 board"; | 13 | model = "TI OMAP2420 H4 board"; |
diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi new file mode 100644 index 000000000000..bfd76b4a0ddc --- /dev/null +++ b/arch/arm/boot/dts/omap2420.dtsi | |||
| @@ -0,0 +1,48 @@ | |||
| 1 | /* | ||
| 2 | * Device Tree Source for OMAP2420 SoC | ||
| 3 | * | ||
| 4 | * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public License | ||
| 7 | * version 2. This program is licensed "as is" without any warranty of any | ||
| 8 | * kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | |||
| 11 | /include/ "omap2.dtsi" | ||
| 12 | |||
| 13 | / { | ||
| 14 | compatible = "ti,omap2420", "ti,omap2"; | ||
| 15 | |||
| 16 | ocp { | ||
| 17 | omap2420_pmx: pinmux@48000030 { | ||
| 18 | compatible = "ti,omap2420-padconf", "pinctrl-single"; | ||
| 19 | reg = <0x48000030 0x0113>; | ||
| 20 | #address-cells = <1>; | ||
| 21 | #size-cells = <0>; | ||
| 22 | pinctrl-single,register-width = <8>; | ||
| 23 | pinctrl-single,function-mask = <0x3f>; | ||
| 24 | }; | ||
| 25 | |||
| 26 | mcbsp1: mcbsp@48074000 { | ||
| 27 | compatible = "ti,omap2420-mcbsp"; | ||
| 28 | reg = <0x48074000 0xff>; | ||
| 29 | reg-names = "mpu"; | ||
| 30 | interrupts = <59>, /* TX interrupt */ | ||
| 31 | <60>; /* RX interrupt */ | ||
| 32 | interrupt-names = "tx", "rx"; | ||
| 33 | interrupt-parent = <&intc>; | ||
| 34 | ti,hwmods = "mcbsp1"; | ||
| 35 | }; | ||
| 36 | |||
| 37 | mcbsp2: mcbsp@48076000 { | ||
| 38 | compatible = "ti,omap2420-mcbsp"; | ||
| 39 | reg = <0x48076000 0xff>; | ||
| 40 | reg-names = "mpu"; | ||
| 41 | interrupts = <62>, /* TX interrupt */ | ||
| 42 | <63>; /* RX interrupt */ | ||
| 43 | interrupt-names = "tx", "rx"; | ||
| 44 | interrupt-parent = <&intc>; | ||
| 45 | ti,hwmods = "mcbsp2"; | ||
| 46 | }; | ||
| 47 | }; | ||
| 48 | }; | ||
diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi new file mode 100644 index 000000000000..4565d9750f4d --- /dev/null +++ b/arch/arm/boot/dts/omap2430.dtsi | |||
| @@ -0,0 +1,92 @@ | |||
| 1 | /* | ||
| 2 | * Device Tree Source for OMAP243x SoC | ||
| 3 | * | ||
| 4 | * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public License | ||
| 7 | * version 2. This program is licensed "as is" without any warranty of any | ||
| 8 | * kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | |||
| 11 | /include/ "omap2.dtsi" | ||
| 12 | |||
| 13 | / { | ||
| 14 | compatible = "ti,omap2430", "ti,omap2"; | ||
| 15 | |||
| 16 | ocp { | ||
| 17 | omap2430_pmx: pinmux@49002030 { | ||
| 18 | compatible = "ti,omap2430-padconf", "pinctrl-single"; | ||
| 19 | reg = <0x49002030 0x0154>; | ||
| 20 | #address-cells = <1>; | ||
| 21 | #size-cells = <0>; | ||
| 22 | pinctrl-single,register-width = <8>; | ||
| 23 | pinctrl-single,function-mask = <0x3f>; | ||
| 24 | }; | ||
| 25 | |||
| 26 | mcbsp1: mcbsp@48074000 { | ||
| 27 | compatible = "ti,omap2430-mcbsp"; | ||
| 28 | reg = <0x48074000 0xff>; | ||
| 29 | reg-names = "mpu"; | ||
| 30 | interrupts = <64>, /* OCP compliant interrupt */ | ||
| 31 | <59>, /* TX interrupt */ | ||
| 32 | <60>, /* RX interrupt */ | ||
| 33 | <61>; /* RX overflow interrupt */ | ||
| 34 | interrupt-names = "common", "tx", "rx", "rx_overflow"; | ||
| 35 | interrupt-parent = <&intc>; | ||
| 36 | ti,buffer-size = <128>; | ||
| 37 | ti,hwmods = "mcbsp1"; | ||
| 38 | }; | ||
| 39 | |||
| 40 | mcbsp2: mcbsp@48076000 { | ||
| 41 | compatible = "ti,omap2430-mcbsp"; | ||
| 42 | reg = <0x48076000 0xff>; | ||
| 43 | reg-names = "mpu"; | ||
| 44 | interrupts = <16>, /* OCP compliant interrupt */ | ||
| 45 | <62>, /* TX interrupt */ | ||
| 46 | <63>; /* RX interrupt */ | ||
| 47 | interrupt-names = "common", "tx", "rx"; | ||
| 48 | interrupt-parent = <&intc>; | ||
| 49 | ti,buffer-size = <128>; | ||
| 50 | ti,hwmods = "mcbsp2"; | ||
| 51 | }; | ||
| 52 | |||
| 53 | mcbsp3: mcbsp@4808c000 { | ||
| 54 | compatible = "ti,omap2430-mcbsp"; | ||
| 55 | reg = <0x4808c000 0xff>; | ||
| 56 | reg-names = "mpu"; | ||
| 57 | interrupts = <17>, /* OCP compliant interrupt */ | ||
| 58 | <89>, /* TX interrupt */ | ||
| 59 | <90>; /* RX interrupt */ | ||
| 60 | interrupt-names = "common", "tx", "rx"; | ||
| 61 | interrupt-parent = <&intc>; | ||
| 62 | ti,buffer-size = <128>; | ||
| 63 | ti,hwmods = "mcbsp3"; | ||
| 64 | }; | ||
| 65 | |||
| 66 | mcbsp4: mcbsp@4808e000 { | ||
| 67 | compatible = "ti,omap2430-mcbsp"; | ||
| 68 | reg = <0x4808e000 0xff>; | ||
| 69 | reg-names = "mpu"; | ||
| 70 | interrupts = <18>, /* OCP compliant interrupt */ | ||
| 71 | <54>, /* TX interrupt */ | ||
| 72 | <55>; /* RX interrupt */ | ||
| 73 | interrupt-names = "common", "tx", "rx"; | ||
| 74 | interrupt-parent = <&intc>; | ||
| 75 | ti,buffer-size = <128>; | ||
| 76 | ti,hwmods = "mcbsp4"; | ||
| 77 | }; | ||
| 78 | |||
| 79 | mcbsp5: mcbsp@48096000 { | ||
| 80 | compatible = "ti,omap2430-mcbsp"; | ||
| 81 | reg = <0x48096000 0xff>; | ||
| 82 | reg-names = "mpu"; | ||
| 83 | interrupts = <19>, /* OCP compliant interrupt */ | ||
| 84 | <81>, /* TX interrupt */ | ||
| 85 | <82>; /* RX interrupt */ | ||
| 86 | interrupt-names = "common", "tx", "rx"; | ||
| 87 | interrupt-parent = <&intc>; | ||
| 88 | ti,buffer-size = <128>; | ||
| 89 | ti,hwmods = "mcbsp5"; | ||
| 90 | }; | ||
| 91 | }; | ||
| 92 | }; | ||
diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts index cdcb98c7e075..c38cf76df81f 100644 --- a/arch/arm/boot/dts/omap3-beagle.dts +++ b/arch/arm/boot/dts/omap3-beagle-xm.dts | |||
| @@ -7,16 +7,44 @@ | |||
| 7 | */ | 7 | */ |
| 8 | /dts-v1/; | 8 | /dts-v1/; |
| 9 | 9 | ||
| 10 | /include/ "omap3.dtsi" | 10 | /include/ "omap36xx.dtsi" |
| 11 | 11 | ||
| 12 | / { | 12 | / { |
| 13 | model = "TI OMAP3 BeagleBoard"; | 13 | model = "TI OMAP3 BeagleBoard xM"; |
| 14 | compatible = "ti,omap3-beagle", "ti,omap3"; | 14 | compatible = "ti,omap3-beagle-xm, ti,omap3-beagle", "ti,omap3"; |
| 15 | 15 | ||
| 16 | memory { | 16 | memory { |
| 17 | device_type = "memory"; | 17 | device_type = "memory"; |
| 18 | reg = <0x80000000 0x20000000>; /* 512 MB */ | 18 | reg = <0x80000000 0x20000000>; /* 512 MB */ |
| 19 | }; | 19 | }; |
| 20 | |||
| 21 | leds { | ||
| 22 | compatible = "gpio-leds"; | ||
| 23 | pmu_stat { | ||
| 24 | label = "beagleboard::pmu_stat"; | ||
| 25 | gpios = <&twl_gpio 19 0>; /* LEDB */ | ||
| 26 | }; | ||
| 27 | |||
| 28 | heartbeat { | ||
| 29 | label = "beagleboard::usr0"; | ||
| 30 | gpios = <&gpio5 22 0>; /* 150 -> D6 LED */ | ||
| 31 | linux,default-trigger = "heartbeat"; | ||
| 32 | }; | ||
| 33 | |||
| 34 | mmc { | ||
| 35 | label = "beagleboard::usr1"; | ||
| 36 | gpios = <&gpio5 21 0>; /* 149 -> D7 LED */ | ||
| 37 | linux,default-trigger = "mmc0"; | ||
| 38 | }; | ||
| 39 | }; | ||
| 40 | |||
| 41 | sound { | ||
| 42 | compatible = "ti,omap-twl4030"; | ||
| 43 | ti,model = "omap3beagle"; | ||
| 44 | |||
| 45 | ti,mcbsp = <&mcbsp2>; | ||
| 46 | ti,codec = <&twl_audio>; | ||
| 47 | }; | ||
| 20 | }; | 48 | }; |
| 21 | 49 | ||
| 22 | &i2c1 { | 50 | &i2c1 { |
| @@ -27,11 +55,17 @@ | |||
| 27 | interrupts = <7>; /* SYS_NIRQ cascaded to intc */ | 55 | interrupts = <7>; /* SYS_NIRQ cascaded to intc */ |
| 28 | interrupt-parent = <&intc>; | 56 | interrupt-parent = <&intc>; |
| 29 | 57 | ||
| 30 | vsim: regulator@10 { | 58 | vsim: regulator-vsim { |
| 31 | compatible = "ti,twl4030-vsim"; | 59 | compatible = "ti,twl4030-vsim"; |
| 32 | regulator-min-microvolt = <1800000>; | 60 | regulator-min-microvolt = <1800000>; |
| 33 | regulator-max-microvolt = <3000000>; | 61 | regulator-max-microvolt = <3000000>; |
| 34 | }; | 62 | }; |
| 63 | |||
| 64 | twl_audio: audio { | ||
| 65 | compatible = "ti,twl4030-audio"; | ||
| 66 | codec { | ||
| 67 | }; | ||
| 68 | }; | ||
| 35 | }; | 69 | }; |
| 36 | }; | 70 | }; |
| 37 | 71 | ||
| @@ -67,3 +101,15 @@ | |||
| 67 | &mmc3 { | 101 | &mmc3 { |
| 68 | status = "disabled"; | 102 | status = "disabled"; |
| 69 | }; | 103 | }; |
| 104 | |||
| 105 | &twl_gpio { | ||
| 106 | ti,use-leds; | ||
| 107 | /* pullups: BIT(1) */ | ||
| 108 | ti,pullups = <0x000002>; | ||
| 109 | /* | ||
| 110 | * pulldowns: | ||
| 111 | * BIT(2), BIT(6), BIT(7), BIT(8), BIT(13) | ||
| 112 | * BIT(15), BIT(16), BIT(17) | ||
| 113 | */ | ||
| 114 | ti,pulldowns = <0x03a1c4>; | ||
| 115 | }; | ||
diff --git a/arch/arm/boot/dts/omap3-evm.dts b/arch/arm/boot/dts/omap3-evm.dts index f349ee9182ce..e8ba1c247a39 100644 --- a/arch/arm/boot/dts/omap3-evm.dts +++ b/arch/arm/boot/dts/omap3-evm.dts | |||
| @@ -17,6 +17,15 @@ | |||
| 17 | device_type = "memory"; | 17 | device_type = "memory"; |
| 18 | reg = <0x80000000 0x10000000>; /* 256 MB */ | 18 | reg = <0x80000000 0x10000000>; /* 256 MB */ |
| 19 | }; | 19 | }; |
| 20 | |||
| 21 | leds { | ||
| 22 | compatible = "gpio-leds"; | ||
| 23 | ledb { | ||
| 24 | label = "omap3evm::ledb"; | ||
| 25 | gpios = <&twl_gpio 19 0>; /* LEDB */ | ||
| 26 | linux,default-trigger = "default-on"; | ||
| 27 | }; | ||
| 28 | }; | ||
| 20 | }; | 29 | }; |
| 21 | 30 | ||
| 22 | &i2c1 { | 31 | &i2c1 { |
| @@ -46,3 +55,7 @@ | |||
| 46 | reg = <0x5c>; | 55 | reg = <0x5c>; |
| 47 | }; | 56 | }; |
| 48 | }; | 57 | }; |
| 58 | |||
| 59 | &twl_gpio { | ||
| 60 | ti,use-leds; | ||
| 61 | }; | ||
diff --git a/arch/arm/boot/dts/omap3-overo.dtsi b/arch/arm/boot/dts/omap3-overo.dtsi new file mode 100644 index 000000000000..89808ce01673 --- /dev/null +++ b/arch/arm/boot/dts/omap3-overo.dtsi | |||
| @@ -0,0 +1,57 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2012 Florian Vaussard, EPFL Mobots group | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | */ | ||
| 8 | |||
| 9 | /* | ||
| 10 | * The Gumstix Overo must be combined with an expansion board. | ||
| 11 | */ | ||
| 12 | /dts-v1/; | ||
| 13 | |||
| 14 | /include/ "omap3.dtsi" | ||
| 15 | |||
| 16 | / { | ||
| 17 | leds { | ||
| 18 | compatible = "gpio-leds"; | ||
| 19 | overo { | ||
| 20 | label = "overo:blue:COM"; | ||
| 21 | gpios = <&twl_gpio 19 0>; | ||
| 22 | linux,default-trigger = "mmc0"; | ||
| 23 | }; | ||
| 24 | }; | ||
| 25 | }; | ||
| 26 | |||
| 27 | &i2c1 { | ||
| 28 | clock-frequency = <2600000>; | ||
| 29 | |||
| 30 | twl: twl@48 { | ||
| 31 | reg = <0x48>; | ||
| 32 | interrupts = <7>; /* SYS_NIRQ cascaded to intc */ | ||
| 33 | interrupt-parent = <&intc>; | ||
| 34 | }; | ||
| 35 | }; | ||
| 36 | |||
| 37 | /include/ "twl4030.dtsi" | ||
| 38 | |||
| 39 | /* i2c2 pins are used for gpio */ | ||
| 40 | &i2c2 { | ||
| 41 | status = "disabled"; | ||
| 42 | }; | ||
| 43 | |||
| 44 | /* on board microSD slot */ | ||
| 45 | &mmc1 { | ||
| 46 | vmmc-supply = <&vmmc1>; | ||
| 47 | bus-width = <4>; | ||
| 48 | }; | ||
| 49 | |||
| 50 | /* optional on board WiFi */ | ||
| 51 | &mmc2 { | ||
| 52 | bus-width = <4>; | ||
| 53 | }; | ||
| 54 | |||
| 55 | &twl_gpio { | ||
| 56 | ti,use-leds; | ||
| 57 | }; | ||
diff --git a/arch/arm/boot/dts/omap3-tobi.dts b/arch/arm/boot/dts/omap3-tobi.dts new file mode 100644 index 000000000000..a13d12de77ff --- /dev/null +++ b/arch/arm/boot/dts/omap3-tobi.dts | |||
| @@ -0,0 +1,35 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2012 Florian Vaussard, EPFL Mobots group | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | */ | ||
| 8 | |||
| 9 | /* | ||
| 10 | * Tobi expansion board is manufactured by Gumstix Inc. | ||
| 11 | */ | ||
| 12 | |||
| 13 | /include/ "omap3-overo.dtsi" | ||
| 14 | |||
| 15 | / { | ||
| 16 | model = "TI OMAP3 Gumstix Overo on Tobi"; | ||
| 17 | compatible = "ti,omap3-tobi", "ti,omap3-overo", "ti,omap3"; | ||
| 18 | |||
| 19 | leds { | ||
| 20 | compatible = "gpio-leds"; | ||
| 21 | heartbeat { | ||
| 22 | label = "overo:red:gpio21"; | ||
| 23 | gpios = <&gpio1 21 0>; | ||
| 24 | linux,default-trigger = "heartbeat"; | ||
| 25 | }; | ||
| 26 | }; | ||
| 27 | }; | ||
| 28 | |||
| 29 | &i2c3 { | ||
| 30 | clock-frequency = <100000>; | ||
| 31 | }; | ||
| 32 | |||
| 33 | &mmc3 { | ||
| 34 | status = "disabled"; | ||
| 35 | }; | ||
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi index 810947198208..f38ea8771b44 100644 --- a/arch/arm/boot/dts/omap3.dtsi +++ b/arch/arm/boot/dts/omap3.dtsi | |||
| @@ -17,7 +17,6 @@ | |||
| 17 | serial0 = &uart1; | 17 | serial0 = &uart1; |
| 18 | serial1 = &uart2; | 18 | serial1 = &uart2; |
| 19 | serial2 = &uart3; | 19 | serial2 = &uart3; |
| 20 | serial3 = &uart4; | ||
| 21 | }; | 20 | }; |
| 22 | 21 | ||
| 23 | cpus { | 22 | cpus { |
| @@ -69,6 +68,24 @@ | |||
| 69 | reg = <0x48200000 0x1000>; | 68 | reg = <0x48200000 0x1000>; |
| 70 | }; | 69 | }; |
| 71 | 70 | ||
| 71 | omap3_pmx_core: pinmux@48002030 { | ||
| 72 | compatible = "ti,omap3-padconf", "pinctrl-single"; | ||
| 73 | reg = <0x48002030 0x05cc>; | ||
| 74 | #address-cells = <1>; | ||
| 75 | #size-cells = <0>; | ||
| 76 | pinctrl-single,register-width = <16>; | ||
| 77 | pinctrl-single,function-mask = <0x7fff>; | ||
| 78 | }; | ||
| 79 | |||
| 80 | omap3_pmx_wkup: pinmux@0x48002a58 { | ||
| 81 | compatible = "ti,omap3-padconf", "pinctrl-single"; | ||
| 82 | reg = <0x48002a58 0x5c>; | ||
| 83 | #address-cells = <1>; | ||
| 84 | #size-cells = <0>; | ||
| 85 | pinctrl-single,register-width = <16>; | ||
| 86 | pinctrl-single,function-mask = <0x7fff>; | ||
| 87 | }; | ||
| 88 | |||
| 72 | gpio1: gpio@48310000 { | 89 | gpio1: gpio@48310000 { |
| 73 | compatible = "ti,omap3-gpio"; | 90 | compatible = "ti,omap3-gpio"; |
| 74 | ti,hwmods = "gpio1"; | 91 | ti,hwmods = "gpio1"; |
| @@ -141,12 +158,6 @@ | |||
| 141 | clock-frequency = <48000000>; | 158 | clock-frequency = <48000000>; |
| 142 | }; | 159 | }; |
| 143 | 160 | ||
| 144 | uart4: serial@49042000 { | ||
| 145 | compatible = "ti,omap3-uart"; | ||
| 146 | ti,hwmods = "uart4"; | ||
| 147 | clock-frequency = <48000000>; | ||
| 148 | }; | ||
| 149 | |||
| 150 | i2c1: i2c@48070000 { | 161 | i2c1: i2c@48070000 { |
| 151 | compatible = "ti,omap3-i2c"; | 162 | compatible = "ti,omap3-i2c"; |
| 152 | #address-cells = <1>; | 163 | #address-cells = <1>; |
| @@ -220,5 +231,74 @@ | |||
| 220 | compatible = "ti,omap3-wdt"; | 231 | compatible = "ti,omap3-wdt"; |
| 221 | ti,hwmods = "wd_timer2"; | 232 | ti,hwmods = "wd_timer2"; |
| 222 | }; | 233 | }; |
| 234 | |||
| 235 | mcbsp1: mcbsp@48074000 { | ||
| 236 | compatible = "ti,omap3-mcbsp"; | ||
| 237 | reg = <0x48074000 0xff>; | ||
| 238 | reg-names = "mpu"; | ||
| 239 | interrupts = <16>, /* OCP compliant interrupt */ | ||
| 240 | <59>, /* TX interrupt */ | ||
| 241 | <60>; /* RX interrupt */ | ||
| 242 | interrupt-names = "common", "tx", "rx"; | ||
| 243 | interrupt-parent = <&intc>; | ||
| 244 | ti,buffer-size = <128>; | ||
| 245 | ti,hwmods = "mcbsp1"; | ||
| 246 | }; | ||
| 247 | |||
| 248 | mcbsp2: mcbsp@49022000 { | ||
| 249 | compatible = "ti,omap3-mcbsp"; | ||
| 250 | reg = <0x49022000 0xff>, | ||
| 251 | <0x49028000 0xff>; | ||
| 252 | reg-names = "mpu", "sidetone"; | ||
| 253 | interrupts = <17>, /* OCP compliant interrupt */ | ||
| 254 | <62>, /* TX interrupt */ | ||
| 255 | <63>, /* RX interrupt */ | ||
| 256 | <4>; /* Sidetone */ | ||
| 257 | interrupt-names = "common", "tx", "rx", "sidetone"; | ||
| 258 | interrupt-parent = <&intc>; | ||
| 259 | ti,buffer-size = <1280>; | ||
| 260 | ti,hwmods = "mcbsp2"; | ||
| 261 | }; | ||
| 262 | |||
| 263 | mcbsp3: mcbsp@49024000 { | ||
| 264 | compatible = "ti,omap3-mcbsp"; | ||
| 265 | reg = <0x49024000 0xff>, | ||
| 266 | <0x4902a000 0xff>; | ||
| 267 | reg-names = "mpu", "sidetone"; | ||
| 268 | interrupts = <22>, /* OCP compliant interrupt */ | ||
| 269 | <89>, /* TX interrupt */ | ||
| 270 | <90>, /* RX interrupt */ | ||
| 271 | <5>; /* Sidetone */ | ||
| 272 | interrupt-names = "common", "tx", "rx", "sidetone"; | ||
| 273 | interrupt-parent = <&intc>; | ||
| 274 | ti,buffer-size = <128>; | ||
| 275 | ti,hwmods = "mcbsp3"; | ||
| 276 | }; | ||
| 277 | |||
| 278 | mcbsp4: mcbsp@49026000 { | ||
| 279 | compatible = "ti,omap3-mcbsp"; | ||
| 280 | reg = <0x49026000 0xff>; | ||
| 281 | reg-names = "mpu"; | ||
| 282 | interrupts = <23>, /* OCP compliant interrupt */ | ||
| 283 | <54>, /* TX interrupt */ | ||
| 284 | <55>; /* RX interrupt */ | ||
| 285 | interrupt-names = "common", "tx", "rx"; | ||
| 286 | interrupt-parent = <&intc>; | ||
| 287 | ti,buffer-size = <128>; | ||
| 288 | ti,hwmods = "mcbsp4"; | ||
| 289 | }; | ||
| 290 | |||
| 291 | mcbsp5: mcbsp@48096000 { | ||
| 292 | compatible = "ti,omap3-mcbsp"; | ||
| 293 | reg = <0x48096000 0xff>; | ||
| 294 | reg-names = "mpu"; | ||
| 295 | interrupts = <27>, /* OCP compliant interrupt */ | ||
| 296 | <81>, /* TX interrupt */ | ||
| 297 | <82>; /* RX interrupt */ | ||
| 298 | interrupt-names = "common", "tx", "rx"; | ||
| 299 | interrupt-parent = <&intc>; | ||
| 300 | ti,buffer-size = <128>; | ||
| 301 | ti,hwmods = "mcbsp5"; | ||
| 302 | }; | ||
| 223 | }; | 303 | }; |
| 224 | }; | 304 | }; |
diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi new file mode 100644 index 000000000000..96bf0287cb9f --- /dev/null +++ b/arch/arm/boot/dts/omap36xx.dtsi | |||
| @@ -0,0 +1,25 @@ | |||
| 1 | /* | ||
| 2 | * Device Tree Source for OMAP3 SoC | ||
| 3 | * | ||
| 4 | * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public License | ||
| 7 | * version 2. This program is licensed "as is" without any warranty of any | ||
| 8 | * kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | |||
| 11 | /include/ "omap3.dtsi" | ||
| 12 | |||
| 13 | / { | ||
| 14 | aliases { | ||
| 15 | serial3 = &uart4; | ||
| 16 | }; | ||
| 17 | |||
| 18 | ocp { | ||
| 19 | uart4: serial@49042000 { | ||
| 20 | compatible = "ti,omap3-uart"; | ||
| 21 | ti,hwmods = "uart4"; | ||
| 22 | clock-frequency = <48000000>; | ||
| 23 | }; | ||
| 24 | }; | ||
| 25 | }; | ||
diff --git a/arch/arm/boot/dts/omap4-panda.dts b/arch/arm/boot/dts/omap4-panda.dts index 9880c12877b3..20b966ee1bb3 100644 --- a/arch/arm/boot/dts/omap4-panda.dts +++ b/arch/arm/boot/dts/omap4-panda.dts | |||
| @@ -8,6 +8,7 @@ | |||
| 8 | /dts-v1/; | 8 | /dts-v1/; |
| 9 | 9 | ||
| 10 | /include/ "omap4.dtsi" | 10 | /include/ "omap4.dtsi" |
| 11 | /include/ "elpida_ecb240abacn.dtsi" | ||
| 11 | 12 | ||
| 12 | / { | 13 | / { |
| 13 | model = "TI OMAP4 PandaBoard"; | 14 | model = "TI OMAP4 PandaBoard"; |
| @@ -126,3 +127,13 @@ | |||
| 126 | ti,non-removable; | 127 | ti,non-removable; |
| 127 | bus-width = <4>; | 128 | bus-width = <4>; |
| 128 | }; | 129 | }; |
| 130 | |||
| 131 | &emif1 { | ||
| 132 | cs1-used; | ||
| 133 | device-handle = <&elpida_ECB240ABACN>; | ||
| 134 | }; | ||
| 135 | |||
| 136 | &emif2 { | ||
| 137 | cs1-used; | ||
| 138 | device-handle = <&elpida_ECB240ABACN>; | ||
| 139 | }; | ||
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts index 72216e932fc0..94a23b39033d 100644 --- a/arch/arm/boot/dts/omap4-sdp.dts +++ b/arch/arm/boot/dts/omap4-sdp.dts | |||
| @@ -8,6 +8,7 @@ | |||
| 8 | /dts-v1/; | 8 | /dts-v1/; |
| 9 | 9 | ||
| 10 | /include/ "omap4.dtsi" | 10 | /include/ "omap4.dtsi" |
| 11 | /include/ "elpida_ecb240abacn.dtsi" | ||
| 11 | 12 | ||
| 12 | / { | 13 | / { |
| 13 | model = "TI OMAP4 SDP board"; | 14 | model = "TI OMAP4 SDP board"; |
| @@ -18,7 +19,7 @@ | |||
| 18 | reg = <0x80000000 0x40000000>; /* 1 GB */ | 19 | reg = <0x80000000 0x40000000>; /* 1 GB */ |
| 19 | }; | 20 | }; |
| 20 | 21 | ||
| 21 | vdd_eth: fixedregulator@0 { | 22 | vdd_eth: fixedregulator-vdd-eth { |
| 22 | compatible = "regulator-fixed"; | 23 | compatible = "regulator-fixed"; |
| 23 | regulator-name = "VDD_ETH"; | 24 | regulator-name = "VDD_ETH"; |
| 24 | regulator-min-microvolt = <3300000>; | 25 | regulator-min-microvolt = <3300000>; |
| @@ -28,7 +29,7 @@ | |||
| 28 | regulator-boot-on; | 29 | regulator-boot-on; |
| 29 | }; | 30 | }; |
| 30 | 31 | ||
| 31 | vbat: fixedregulator@2 { | 32 | vbat: fixedregulator-vbat { |
| 32 | compatible = "regulator-fixed"; | 33 | compatible = "regulator-fixed"; |
| 33 | regulator-name = "VBAT"; | 34 | regulator-name = "VBAT"; |
| 34 | regulator-min-microvolt = <3750000>; | 35 | regulator-min-microvolt = <3750000>; |
| @@ -115,6 +116,33 @@ | |||
| 115 | }; | 116 | }; |
| 116 | }; | 117 | }; |
| 117 | 118 | ||
| 119 | &omap4_pmx_core { | ||
| 120 | uart2_pins: pinmux_uart2_pins { | ||
| 121 | pinctrl-single,pins = < | ||
| 122 | 0xd8 0x118 /* uart2_cts.uart2_cts INPUT_PULLUP | MODE0 */ | ||
| 123 | 0xda 0 /* uart2_rts.uart2_rts OUTPUT | MODE0 */ | ||
| 124 | 0xdc 0x118 /* uart2_rx.uart2_rx INPUT_PULLUP | MODE0 */ | ||
| 125 | 0xde 0 /* uart2_tx.uart2_tx OUTPUT | MODE0 */ | ||
| 126 | >; | ||
| 127 | }; | ||
| 128 | |||
| 129 | uart3_pins: pinmux_uart3_pins { | ||
| 130 | pinctrl-single,pins = < | ||
| 131 | 0x100 0x118 /* uart3_cts_rctx.uart3_cts_rctx INPUT_PULLUP | MODE0 */ | ||
| 132 | 0x102 0 /* uart3_rts_sd.uart3_rts_sd OUTPUT | MODE0 */ | ||
| 133 | 0x104 0x100 /* uart3_rx_irrx.uart3_rx_irrx INPUT | MODE0 */ | ||
| 134 | 0x106 0 /* uart3_tx_irtx.uart3_tx_irtx OUTPUT | MODE0 */ | ||
| 135 | >; | ||
| 136 | }; | ||
| 137 | |||
| 138 | uart4_pins: pinmux_uart4_pins { | ||
| 139 | pinctrl-single,pins = < | ||
| 140 | 0x11c 0x100 /* uart4_rx.uart4_rx INPUT | MODE0 */ | ||
| 141 | 0x11e 0 /* uart4_tx.uart4_tx OUTPUT | MODE0 */ | ||
| 142 | >; | ||
| 143 | }; | ||
| 144 | }; | ||
| 145 | |||
| 118 | &i2c1 { | 146 | &i2c1 { |
| 119 | clock-frequency = <400000>; | 147 | clock-frequency = <400000>; |
| 120 | 148 | ||
| @@ -226,3 +254,98 @@ | |||
| 226 | bus-width = <4>; | 254 | bus-width = <4>; |
| 227 | ti,non-removable; | 255 | ti,non-removable; |
| 228 | }; | 256 | }; |
| 257 | |||
| 258 | &emif1 { | ||
| 259 | cs1-used; | ||
| 260 | device-handle = <&elpida_ECB240ABACN>; | ||
| 261 | }; | ||
| 262 | |||
| 263 | &emif2 { | ||
| 264 | cs1-used; | ||
| 265 | device-handle = <&elpida_ECB240ABACN>; | ||
| 266 | }; | ||
| 267 | |||
| 268 | &keypad { | ||
| 269 | keypad,num-rows = <8>; | ||
| 270 | keypad,num-columns = <8>; | ||
| 271 | linux,keymap = <0x00000012 /* KEY_E */ | ||
| 272 | 0x00010013 /* KEY_R */ | ||
| 273 | 0x00020014 /* KEY_T */ | ||
| 274 | 0x00030066 /* KEY_HOME */ | ||
| 275 | 0x0004003f /* KEY_F5 */ | ||
| 276 | 0x000500f0 /* KEY_UNKNOWN */ | ||
| 277 | 0x00060017 /* KEY_I */ | ||
| 278 | 0x0007002a /* KEY_LEFTSHIFT */ | ||
| 279 | 0x01000020 /* KEY_D*/ | ||
| 280 | 0x01010021 /* KEY_F */ | ||
| 281 | 0x01020022 /* KEY_G */ | ||
| 282 | 0x010300e7 /* KEY_SEND */ | ||
| 283 | 0x01040040 /* KEY_F6 */ | ||
| 284 | 0x010500f0 /* KEY_UNKNOWN */ | ||
| 285 | 0x01060025 /* KEY_K */ | ||
| 286 | 0x0107001c /* KEY_ENTER */ | ||
| 287 | 0x0200002d /* KEY_X */ | ||
| 288 | 0x0201002e /* KEY_C */ | ||
| 289 | 0x0202002f /* KEY_V */ | ||
| 290 | 0x0203006b /* KEY_END */ | ||
| 291 | 0x02040041 /* KEY_F7 */ | ||
| 292 | 0x020500f0 /* KEY_UNKNOWN */ | ||
| 293 | 0x02060034 /* KEY_DOT */ | ||
| 294 | 0x0207003a /* KEY_CAPSLOCK */ | ||
| 295 | 0x0300002c /* KEY_Z */ | ||
| 296 | 0x0301004e /* KEY_KPLUS */ | ||
| 297 | 0x03020030 /* KEY_B */ | ||
| 298 | 0x0303003b /* KEY_F1 */ | ||
| 299 | 0x03040042 /* KEY_F8 */ | ||
| 300 | 0x030500f0 /* KEY_UNKNOWN */ | ||
| 301 | 0x03060018 /* KEY_O */ | ||
| 302 | 0x03070039 /* KEY_SPACE */ | ||
| 303 | 0x04000011 /* KEY_W */ | ||
| 304 | 0x04010015 /* KEY_Y */ | ||
| 305 | 0x04020016 /* KEY_U */ | ||
| 306 | 0x0403003c /* KEY_F2 */ | ||
| 307 | 0x04040073 /* KEY_VOLUMEUP */ | ||
| 308 | 0x040500f0 /* KEY_UNKNOWN */ | ||
| 309 | 0x04060026 /* KEY_L */ | ||
| 310 | 0x04070069 /* KEY_LEFT */ | ||
| 311 | 0x0500001f /* KEY_S */ | ||
| 312 | 0x05010023 /* KEY_H */ | ||
| 313 | 0x05020024 /* KEY_J */ | ||
| 314 | 0x0503003d /* KEY_F3 */ | ||
| 315 | 0x05040043 /* KEY_F9 */ | ||
| 316 | 0x05050072 /* KEY_VOLUMEDOWN */ | ||
| 317 | 0x05060032 /* KEY_M */ | ||
| 318 | 0x0507006a /* KEY_RIGHT */ | ||
| 319 | 0x06000010 /* KEY_Q */ | ||
| 320 | 0x0601001e /* KEY_A */ | ||
| 321 | 0x06020031 /* KEY_N */ | ||
| 322 | 0x0603009e /* KEY_BACK */ | ||
| 323 | 0x0604000e /* KEY_BACKSPACE */ | ||
| 324 | 0x060500f0 /* KEY_UNKNOWN */ | ||
| 325 | 0x06060019 /* KEY_P */ | ||
| 326 | 0x06070067 /* KEY_UP */ | ||
| 327 | 0x07000094 /* KEY_PROG1 */ | ||
| 328 | 0x07010095 /* KEY_PROG2 */ | ||
| 329 | 0x070200ca /* KEY_PROG3 */ | ||
| 330 | 0x070300cb /* KEY_PROG4 */ | ||
| 331 | 0x0704003e /* KEY_F4 */ | ||
| 332 | 0x070500f0 /* KEY_UNKNOWN */ | ||
| 333 | 0x07060160 /* KEY_OK */ | ||
| 334 | 0x0707006c>; /* KEY_DOWN */ | ||
| 335 | linux,input-no-autorepeat; | ||
| 336 | }; | ||
| 337 | |||
| 338 | &uart2 { | ||
| 339 | pinctrl-names = "default"; | ||
| 340 | pinctrl-0 = <&uart2_pins>; | ||
| 341 | }; | ||
| 342 | |||
| 343 | &uart3 { | ||
| 344 | pinctrl-names = "default"; | ||
| 345 | pinctrl-0 = <&uart3_pins>; | ||
| 346 | }; | ||
| 347 | |||
| 348 | &uart4 { | ||
| 349 | pinctrl-names = "default"; | ||
| 350 | pinctrl-0 = <&uart4_pins>; | ||
| 351 | }; | ||
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 04cbbcb6ff91..5d1c48459e6e 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi | |||
| @@ -30,12 +30,35 @@ | |||
| 30 | cpus { | 30 | cpus { |
| 31 | cpu@0 { | 31 | cpu@0 { |
| 32 | compatible = "arm,cortex-a9"; | 32 | compatible = "arm,cortex-a9"; |
| 33 | next-level-cache = <&L2>; | ||
| 33 | }; | 34 | }; |
| 34 | cpu@1 { | 35 | cpu@1 { |
| 35 | compatible = "arm,cortex-a9"; | 36 | compatible = "arm,cortex-a9"; |
| 37 | next-level-cache = <&L2>; | ||
| 36 | }; | 38 | }; |
| 37 | }; | 39 | }; |
| 38 | 40 | ||
| 41 | gic: interrupt-controller@48241000 { | ||
| 42 | compatible = "arm,cortex-a9-gic"; | ||
| 43 | interrupt-controller; | ||
| 44 | #interrupt-cells = <3>; | ||
| 45 | reg = <0x48241000 0x1000>, | ||
| 46 | <0x48240100 0x0100>; | ||
| 47 | }; | ||
| 48 | |||
| 49 | L2: l2-cache-controller@48242000 { | ||
| 50 | compatible = "arm,pl310-cache"; | ||
| 51 | reg = <0x48242000 0x1000>; | ||
| 52 | cache-unified; | ||
| 53 | cache-level = <2>; | ||
| 54 | }; | ||
| 55 | |||
| 56 | local-timer@0x48240600 { | ||
| 57 | compatible = "arm,cortex-a9-twd-timer"; | ||
| 58 | reg = <0x48240600 0x20>; | ||
| 59 | interrupts = <1 13 0x304>; | ||
| 60 | }; | ||
| 61 | |||
| 39 | /* | 62 | /* |
| 40 | * The soc node represents the soc top level view. It is uses for IPs | 63 | * The soc node represents the soc top level view. It is uses for IPs |
| 41 | * that are not memory mapped in the MPU view or for the MPU itself. | 64 | * that are not memory mapped in the MPU view or for the MPU itself. |
| @@ -61,30 +84,6 @@ | |||
| 61 | /* | 84 | /* |
| 62 | * XXX: Use a flat representation of the OMAP4 interconnect. | 85 | * XXX: Use a flat representation of the OMAP4 interconnect. |
| 63 | * The real OMAP interconnect network is quite complex. | 86 | * The real OMAP interconnect network is quite complex. |
| 64 | * | ||
| 65 | * MPU -+-- MPU_PRIVATE - GIC, L2 | ||
| 66 | * | | ||
| 67 | * +----------------+----------+ | ||
| 68 | * | | | | ||
| 69 | * + +- EMIF - DDR | | ||
| 70 | * | | | | ||
| 71 | * | + +--------+ | ||
| 72 | * | | | | ||
| 73 | * | +- L4_ABE - AESS, MCBSP, TIMERs... | ||
| 74 | * | | | ||
| 75 | * +- L3_MAIN --+- L4_CORE - IPs... | ||
| 76 | * | | ||
| 77 | * +- L4_PER - IPs... | ||
| 78 | * | | ||
| 79 | * +- L4_CFG -+- L4_WKUP - IPs... | ||
| 80 | * | | | ||
| 81 | * | +- IPs... | ||
| 82 | * +- IPU ----+ | ||
| 83 | * | | | ||
| 84 | * +- DSP ----+ | ||
| 85 | * | | | ||
| 86 | * +- DSS ----+ | ||
| 87 | * | ||
| 88 | * Since that will not bring real advantage to represent that in DT for | 87 | * Since that will not bring real advantage to represent that in DT for |
| 89 | * the moment, just use a fake OCP bus entry to represent the whole bus | 88 | * the moment, just use a fake OCP bus entry to represent the whole bus |
| 90 | * hierarchy. | 89 | * hierarchy. |
| @@ -96,16 +95,27 @@ | |||
| 96 | ranges; | 95 | ranges; |
| 97 | ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3"; | 96 | ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3"; |
| 98 | 97 | ||
| 99 | gic: interrupt-controller@48241000 { | 98 | omap4_pmx_core: pinmux@4a100040 { |
| 100 | compatible = "arm,cortex-a9-gic"; | 99 | compatible = "ti,omap4-padconf", "pinctrl-single"; |
| 101 | interrupt-controller; | 100 | reg = <0x4a100040 0x0196>; |
| 102 | #interrupt-cells = <3>; | 101 | #address-cells = <1>; |
| 103 | reg = <0x48241000 0x1000>, | 102 | #size-cells = <0>; |
| 104 | <0x48240100 0x0100>; | 103 | pinctrl-single,register-width = <16>; |
| 104 | pinctrl-single,function-mask = <0x7fff>; | ||
| 105 | }; | ||
| 106 | omap4_pmx_wkup: pinmux@4a31e040 { | ||
| 107 | compatible = "ti,omap4-padconf", "pinctrl-single"; | ||
| 108 | reg = <0x4a31e040 0x0038>; | ||
| 109 | #address-cells = <1>; | ||
| 110 | #size-cells = <0>; | ||
| 111 | pinctrl-single,register-width = <16>; | ||
| 112 | pinctrl-single,function-mask = <0x7fff>; | ||
| 105 | }; | 113 | }; |
| 106 | 114 | ||
| 107 | gpio1: gpio@4a310000 { | 115 | gpio1: gpio@4a310000 { |
| 108 | compatible = "ti,omap4-gpio"; | 116 | compatible = "ti,omap4-gpio"; |
| 117 | reg = <0x4a310000 0x200>; | ||
| 118 | interrupts = <0 29 0x4>; | ||
| 109 | ti,hwmods = "gpio1"; | 119 | ti,hwmods = "gpio1"; |
| 110 | gpio-controller; | 120 | gpio-controller; |
| 111 | #gpio-cells = <2>; | 121 | #gpio-cells = <2>; |
| @@ -115,6 +125,8 @@ | |||
| 115 | 125 | ||
| 116 | gpio2: gpio@48055000 { | 126 | gpio2: gpio@48055000 { |
| 117 | compatible = "ti,omap4-gpio"; | 127 | compatible = "ti,omap4-gpio"; |
| 128 | reg = <0x48055000 0x200>; | ||
| 129 | interrupts = <0 30 0x4>; | ||
| 118 | ti,hwmods = "gpio2"; | 130 | ti,hwmods = "gpio2"; |
| 119 | gpio-controller; | 131 | gpio-controller; |
| 120 | #gpio-cells = <2>; | 132 | #gpio-cells = <2>; |
| @@ -124,6 +136,8 @@ | |||
| 124 | 136 | ||
| 125 | gpio3: gpio@48057000 { | 137 | gpio3: gpio@48057000 { |
| 126 | compatible = "ti,omap4-gpio"; | 138 | compatible = "ti,omap4-gpio"; |
| 139 | reg = <0x48057000 0x200>; | ||
| 140 | interrupts = <0 31 0x4>; | ||
| 127 | ti,hwmods = "gpio3"; | 141 | ti,hwmods = "gpio3"; |
| 128 | gpio-controller; | 142 | gpio-controller; |
| 129 | #gpio-cells = <2>; | 143 | #gpio-cells = <2>; |
| @@ -133,6 +147,8 @@ | |||
| 133 | 147 | ||
| 134 | gpio4: gpio@48059000 { | 148 | gpio4: gpio@48059000 { |
| 135 | compatible = "ti,omap4-gpio"; | 149 | compatible = "ti,omap4-gpio"; |
| 150 | reg = <0x48059000 0x200>; | ||
| 151 | interrupts = <0 32 0x4>; | ||
| 136 | ti,hwmods = "gpio4"; | 152 | ti,hwmods = "gpio4"; |
| 137 | gpio-controller; | 153 | gpio-controller; |
| 138 | #gpio-cells = <2>; | 154 | #gpio-cells = <2>; |
| @@ -142,6 +158,8 @@ | |||
| 142 | 158 | ||
| 143 | gpio5: gpio@4805b000 { | 159 | gpio5: gpio@4805b000 { |
| 144 | compatible = "ti,omap4-gpio"; | 160 | compatible = "ti,omap4-gpio"; |
| 161 | reg = <0x4805b000 0x200>; | ||
| 162 | interrupts = <0 33 0x4>; | ||
| 145 | ti,hwmods = "gpio5"; | 163 | ti,hwmods = "gpio5"; |
| 146 | gpio-controller; | 164 | gpio-controller; |
| 147 | #gpio-cells = <2>; | 165 | #gpio-cells = <2>; |
| @@ -151,6 +169,8 @@ | |||
| 151 | 169 | ||
| 152 | gpio6: gpio@4805d000 { | 170 | gpio6: gpio@4805d000 { |
| 153 | compatible = "ti,omap4-gpio"; | 171 | compatible = "ti,omap4-gpio"; |
| 172 | reg = <0x4805d000 0x200>; | ||
| 173 | interrupts = <0 34 0x4>; | ||
| 154 | ti,hwmods = "gpio6"; | 174 | ti,hwmods = "gpio6"; |
| 155 | gpio-controller; | 175 | gpio-controller; |
| 156 | #gpio-cells = <2>; | 176 | #gpio-cells = <2>; |
| @@ -160,30 +180,40 @@ | |||
| 160 | 180 | ||
| 161 | uart1: serial@4806a000 { | 181 | uart1: serial@4806a000 { |
| 162 | compatible = "ti,omap4-uart"; | 182 | compatible = "ti,omap4-uart"; |
| 183 | reg = <0x4806a000 0x100>; | ||
| 184 | interrupts = <0 72 0x4>; | ||
| 163 | ti,hwmods = "uart1"; | 185 | ti,hwmods = "uart1"; |
| 164 | clock-frequency = <48000000>; | 186 | clock-frequency = <48000000>; |
| 165 | }; | 187 | }; |
| 166 | 188 | ||
| 167 | uart2: serial@4806c000 { | 189 | uart2: serial@4806c000 { |
| 168 | compatible = "ti,omap4-uart"; | 190 | compatible = "ti,omap4-uart"; |
| 191 | reg = <0x4806c000 0x100>; | ||
| 192 | interrupts = <0 73 0x4>; | ||
| 169 | ti,hwmods = "uart2"; | 193 | ti,hwmods = "uart2"; |
| 170 | clock-frequency = <48000000>; | 194 | clock-frequency = <48000000>; |
| 171 | }; | 195 | }; |
| 172 | 196 | ||
| 173 | uart3: serial@48020000 { | 197 | uart3: serial@48020000 { |
| 174 | compatible = "ti,omap4-uart"; | 198 | compatible = "ti,omap4-uart"; |
| 199 | reg = <0x48020000 0x100>; | ||
| 200 | interrupts = <0 74 0x4>; | ||
| 175 | ti,hwmods = "uart3"; | 201 | ti,hwmods = "uart3"; |
| 176 | clock-frequency = <48000000>; | 202 | clock-frequency = <48000000>; |
| 177 | }; | 203 | }; |
| 178 | 204 | ||
| 179 | uart4: serial@4806e000 { | 205 | uart4: serial@4806e000 { |
| 180 | compatible = "ti,omap4-uart"; | 206 | compatible = "ti,omap4-uart"; |
| 207 | reg = <0x4806e000 0x100>; | ||
| 208 | interrupts = <0 70 0x4>; | ||
| 181 | ti,hwmods = "uart4"; | 209 | ti,hwmods = "uart4"; |
| 182 | clock-frequency = <48000000>; | 210 | clock-frequency = <48000000>; |
| 183 | }; | 211 | }; |
| 184 | 212 | ||
| 185 | i2c1: i2c@48070000 { | 213 | i2c1: i2c@48070000 { |
| 186 | compatible = "ti,omap4-i2c"; | 214 | compatible = "ti,omap4-i2c"; |
| 215 | reg = <0x48070000 0x100>; | ||
| 216 | interrupts = <0 56 0x4>; | ||
| 187 | #address-cells = <1>; | 217 | #address-cells = <1>; |
| 188 | #size-cells = <0>; | 218 | #size-cells = <0>; |
| 189 | ti,hwmods = "i2c1"; | 219 | ti,hwmods = "i2c1"; |
| @@ -191,6 +221,8 @@ | |||
| 191 | 221 | ||
| 192 | i2c2: i2c@48072000 { | 222 | i2c2: i2c@48072000 { |
| 193 | compatible = "ti,omap4-i2c"; | 223 | compatible = "ti,omap4-i2c"; |
| 224 | reg = <0x48072000 0x100>; | ||
| 225 | interrupts = <0 57 0x4>; | ||
| 194 | #address-cells = <1>; | 226 | #address-cells = <1>; |
| 195 | #size-cells = <0>; | 227 | #size-cells = <0>; |
| 196 | ti,hwmods = "i2c2"; | 228 | ti,hwmods = "i2c2"; |
| @@ -198,6 +230,8 @@ | |||
| 198 | 230 | ||
| 199 | i2c3: i2c@48060000 { | 231 | i2c3: i2c@48060000 { |
| 200 | compatible = "ti,omap4-i2c"; | 232 | compatible = "ti,omap4-i2c"; |
| 233 | reg = <0x48060000 0x100>; | ||
| 234 | interrupts = <0 61 0x4>; | ||
| 201 | #address-cells = <1>; | 235 | #address-cells = <1>; |
| 202 | #size-cells = <0>; | 236 | #size-cells = <0>; |
| 203 | ti,hwmods = "i2c3"; | 237 | ti,hwmods = "i2c3"; |
| @@ -205,6 +239,8 @@ | |||
| 205 | 239 | ||
| 206 | i2c4: i2c@48350000 { | 240 | i2c4: i2c@48350000 { |
| 207 | compatible = "ti,omap4-i2c"; | 241 | compatible = "ti,omap4-i2c"; |
| 242 | reg = <0x48350000 0x100>; | ||
| 243 | interrupts = <0 62 0x4>; | ||
| 208 | #address-cells = <1>; | 244 | #address-cells = <1>; |
| 209 | #size-cells = <0>; | 245 | #size-cells = <0>; |
| 210 | ti,hwmods = "i2c4"; | 246 | ti,hwmods = "i2c4"; |
| @@ -212,6 +248,8 @@ | |||
| 212 | 248 | ||
| 213 | mcspi1: spi@48098000 { | 249 | mcspi1: spi@48098000 { |
| 214 | compatible = "ti,omap4-mcspi"; | 250 | compatible = "ti,omap4-mcspi"; |
| 251 | reg = <0x48098000 0x200>; | ||
| 252 | interrupts = <0 65 0x4>; | ||
| 215 | #address-cells = <1>; | 253 | #address-cells = <1>; |
| 216 | #size-cells = <0>; | 254 | #size-cells = <0>; |
| 217 | ti,hwmods = "mcspi1"; | 255 | ti,hwmods = "mcspi1"; |
| @@ -220,6 +258,8 @@ | |||
| 220 | 258 | ||
| 221 | mcspi2: spi@4809a000 { | 259 | mcspi2: spi@4809a000 { |
| 222 | compatible = "ti,omap4-mcspi"; | 260 | compatible = "ti,omap4-mcspi"; |
| 261 | reg = <0x4809a000 0x200>; | ||
| 262 | interrupts = <0 66 0x4>; | ||
| 223 | #address-cells = <1>; | 263 | #address-cells = <1>; |
| 224 | #size-cells = <0>; | 264 | #size-cells = <0>; |
| 225 | ti,hwmods = "mcspi2"; | 265 | ti,hwmods = "mcspi2"; |
| @@ -228,6 +268,8 @@ | |||
| 228 | 268 | ||
| 229 | mcspi3: spi@480b8000 { | 269 | mcspi3: spi@480b8000 { |
| 230 | compatible = "ti,omap4-mcspi"; | 270 | compatible = "ti,omap4-mcspi"; |
| 271 | reg = <0x480b8000 0x200>; | ||
| 272 | interrupts = <0 91 0x4>; | ||
| 231 | #address-cells = <1>; | 273 | #address-cells = <1>; |
| 232 | #size-cells = <0>; | 274 | #size-cells = <0>; |
| 233 | ti,hwmods = "mcspi3"; | 275 | ti,hwmods = "mcspi3"; |
| @@ -236,6 +278,8 @@ | |||
| 236 | 278 | ||
| 237 | mcspi4: spi@480ba000 { | 279 | mcspi4: spi@480ba000 { |
| 238 | compatible = "ti,omap4-mcspi"; | 280 | compatible = "ti,omap4-mcspi"; |
| 281 | reg = <0x480ba000 0x200>; | ||
| 282 | interrupts = <0 48 0x4>; | ||
| 239 | #address-cells = <1>; | 283 | #address-cells = <1>; |
| 240 | #size-cells = <0>; | 284 | #size-cells = <0>; |
| 241 | ti,hwmods = "mcspi4"; | 285 | ti,hwmods = "mcspi4"; |
| @@ -244,6 +288,8 @@ | |||
| 244 | 288 | ||
| 245 | mmc1: mmc@4809c000 { | 289 | mmc1: mmc@4809c000 { |
| 246 | compatible = "ti,omap4-hsmmc"; | 290 | compatible = "ti,omap4-hsmmc"; |
| 291 | reg = <0x4809c000 0x400>; | ||
| 292 | interrupts = <0 83 0x4>; | ||
| 247 | ti,hwmods = "mmc1"; | 293 | ti,hwmods = "mmc1"; |
| 248 | ti,dual-volt; | 294 | ti,dual-volt; |
| 249 | ti,needs-special-reset; | 295 | ti,needs-special-reset; |
| @@ -251,30 +297,40 @@ | |||
| 251 | 297 | ||
| 252 | mmc2: mmc@480b4000 { | 298 | mmc2: mmc@480b4000 { |
| 253 | compatible = "ti,omap4-hsmmc"; | 299 | compatible = "ti,omap4-hsmmc"; |
| 300 | reg = <0x480b4000 0x400>; | ||
| 301 | interrupts = <0 86 0x4>; | ||
| 254 | ti,hwmods = "mmc2"; | 302 | ti,hwmods = "mmc2"; |
| 255 | ti,needs-special-reset; | 303 | ti,needs-special-reset; |
| 256 | }; | 304 | }; |
| 257 | 305 | ||
| 258 | mmc3: mmc@480ad000 { | 306 | mmc3: mmc@480ad000 { |
| 259 | compatible = "ti,omap4-hsmmc"; | 307 | compatible = "ti,omap4-hsmmc"; |
| 308 | reg = <0x480ad000 0x400>; | ||
| 309 | interrupts = <0 94 0x4>; | ||
| 260 | ti,hwmods = "mmc3"; | 310 | ti,hwmods = "mmc3"; |
| 261 | ti,needs-special-reset; | 311 | ti,needs-special-reset; |
| 262 | }; | 312 | }; |
| 263 | 313 | ||
| 264 | mmc4: mmc@480d1000 { | 314 | mmc4: mmc@480d1000 { |
| 265 | compatible = "ti,omap4-hsmmc"; | 315 | compatible = "ti,omap4-hsmmc"; |
| 316 | reg = <0x480d1000 0x400>; | ||
| 317 | interrupts = <0 96 0x4>; | ||
| 266 | ti,hwmods = "mmc4"; | 318 | ti,hwmods = "mmc4"; |
| 267 | ti,needs-special-reset; | 319 | ti,needs-special-reset; |
| 268 | }; | 320 | }; |
| 269 | 321 | ||
| 270 | mmc5: mmc@480d5000 { | 322 | mmc5: mmc@480d5000 { |
| 271 | compatible = "ti,omap4-hsmmc"; | 323 | compatible = "ti,omap4-hsmmc"; |
| 324 | reg = <0x480d5000 0x400>; | ||
| 325 | interrupts = <0 59 0x4>; | ||
| 272 | ti,hwmods = "mmc5"; | 326 | ti,hwmods = "mmc5"; |
| 273 | ti,needs-special-reset; | 327 | ti,needs-special-reset; |
| 274 | }; | 328 | }; |
| 275 | 329 | ||
| 276 | wdt2: wdt@4a314000 { | 330 | wdt2: wdt@4a314000 { |
| 277 | compatible = "ti,omap4-wdt", "ti,omap3-wdt"; | 331 | compatible = "ti,omap4-wdt", "ti,omap3-wdt"; |
| 332 | reg = <0x4a314000 0x80>; | ||
| 333 | interrupts = <0 80 0x4>; | ||
| 278 | ti,hwmods = "wd_timer2"; | 334 | ti,hwmods = "wd_timer2"; |
| 279 | }; | 335 | }; |
| 280 | 336 | ||
| @@ -282,6 +338,7 @@ | |||
| 282 | compatible = "ti,omap4-mcpdm"; | 338 | compatible = "ti,omap4-mcpdm"; |
| 283 | reg = <0x40132000 0x7f>, /* MPU private access */ | 339 | reg = <0x40132000 0x7f>, /* MPU private access */ |
| 284 | <0x49032000 0x7f>; /* L3 Interconnect */ | 340 | <0x49032000 0x7f>; /* L3 Interconnect */ |
| 341 | reg-names = "mpu", "dma"; | ||
| 285 | interrupts = <0 112 0x4>; | 342 | interrupts = <0 112 0x4>; |
| 286 | interrupt-parent = <&gic>; | 343 | interrupt-parent = <&gic>; |
| 287 | ti,hwmods = "mcpdm"; | 344 | ti,hwmods = "mcpdm"; |
| @@ -291,9 +348,87 @@ | |||
| 291 | compatible = "ti,omap4-dmic"; | 348 | compatible = "ti,omap4-dmic"; |
| 292 | reg = <0x4012e000 0x7f>, /* MPU private access */ | 349 | reg = <0x4012e000 0x7f>, /* MPU private access */ |
| 293 | <0x4902e000 0x7f>; /* L3 Interconnect */ | 350 | <0x4902e000 0x7f>; /* L3 Interconnect */ |
| 351 | reg-names = "mpu", "dma"; | ||
| 294 | interrupts = <0 114 0x4>; | 352 | interrupts = <0 114 0x4>; |
| 295 | interrupt-parent = <&gic>; | 353 | interrupt-parent = <&gic>; |
| 296 | ti,hwmods = "dmic"; | 354 | ti,hwmods = "dmic"; |
| 297 | }; | 355 | }; |
| 356 | |||
| 357 | mcbsp1: mcbsp@40122000 { | ||
| 358 | compatible = "ti,omap4-mcbsp"; | ||
| 359 | reg = <0x40122000 0xff>, /* MPU private access */ | ||
| 360 | <0x49022000 0xff>; /* L3 Interconnect */ | ||
| 361 | reg-names = "mpu", "dma"; | ||
| 362 | interrupts = <0 17 0x4>; | ||
| 363 | interrupt-names = "common"; | ||
| 364 | interrupt-parent = <&gic>; | ||
| 365 | ti,buffer-size = <128>; | ||
| 366 | ti,hwmods = "mcbsp1"; | ||
| 367 | }; | ||
| 368 | |||
| 369 | mcbsp2: mcbsp@40124000 { | ||
| 370 | compatible = "ti,omap4-mcbsp"; | ||
| 371 | reg = <0x40124000 0xff>, /* MPU private access */ | ||
| 372 | <0x49024000 0xff>; /* L3 Interconnect */ | ||
| 373 | reg-names = "mpu", "dma"; | ||
| 374 | interrupts = <0 22 0x4>; | ||
| 375 | interrupt-names = "common"; | ||
| 376 | interrupt-parent = <&gic>; | ||
| 377 | ti,buffer-size = <128>; | ||
| 378 | ti,hwmods = "mcbsp2"; | ||
| 379 | }; | ||
| 380 | |||
| 381 | mcbsp3: mcbsp@40126000 { | ||
| 382 | compatible = "ti,omap4-mcbsp"; | ||
| 383 | reg = <0x40126000 0xff>, /* MPU private access */ | ||
| 384 | <0x49026000 0xff>; /* L3 Interconnect */ | ||
| 385 | reg-names = "mpu", "dma"; | ||
| 386 | interrupts = <0 23 0x4>; | ||
| 387 | interrupt-names = "common"; | ||
| 388 | interrupt-parent = <&gic>; | ||
| 389 | ti,buffer-size = <128>; | ||
| 390 | ti,hwmods = "mcbsp3"; | ||
| 391 | }; | ||
| 392 | |||
| 393 | mcbsp4: mcbsp@48096000 { | ||
| 394 | compatible = "ti,omap4-mcbsp"; | ||
| 395 | reg = <0x48096000 0xff>; /* L4 Interconnect */ | ||
| 396 | reg-names = "mpu"; | ||
| 397 | interrupts = <0 16 0x4>; | ||
| 398 | interrupt-names = "common"; | ||
| 399 | interrupt-parent = <&gic>; | ||
| 400 | ti,buffer-size = <128>; | ||
| 401 | ti,hwmods = "mcbsp4"; | ||
| 402 | }; | ||
| 403 | |||
| 404 | keypad: keypad@4a31c000 { | ||
| 405 | compatible = "ti,omap4-keypad"; | ||
| 406 | reg = <0x4a31c000 0x80>; | ||
| 407 | interrupts = <0 120 0x4>; | ||
| 408 | reg-names = "mpu"; | ||
| 409 | ti,hwmods = "kbd"; | ||
| 410 | }; | ||
| 411 | |||
| 412 | emif1: emif@4c000000 { | ||
| 413 | compatible = "ti,emif-4d"; | ||
| 414 | reg = <0x4c000000 0x100>; | ||
| 415 | interrupts = <0 110 0x4>; | ||
| 416 | ti,hwmods = "emif1"; | ||
| 417 | phy-type = <1>; | ||
| 418 | hw-caps-read-idle-ctrl; | ||
| 419 | hw-caps-ll-interface; | ||
| 420 | hw-caps-temp-alert; | ||
| 421 | }; | ||
| 422 | |||
| 423 | emif2: emif@4d000000 { | ||
| 424 | compatible = "ti,emif-4d"; | ||
| 425 | reg = <0x4d000000 0x100>; | ||
| 426 | interrupts = <0 111 0x4>; | ||
| 427 | ti,hwmods = "emif2"; | ||
| 428 | phy-type = <1>; | ||
| 429 | hw-caps-read-idle-ctrl; | ||
| 430 | hw-caps-ll-interface; | ||
| 431 | hw-caps-temp-alert; | ||
| 432 | }; | ||
| 298 | }; | 433 | }; |
| 299 | }; | 434 | }; |
diff --git a/arch/arm/boot/dts/omap5-evm.dts b/arch/arm/boot/dts/omap5-evm.dts index 200c39ad1c82..9c41a3f311aa 100644 --- a/arch/arm/boot/dts/omap5-evm.dts +++ b/arch/arm/boot/dts/omap5-evm.dts | |||
| @@ -17,4 +17,68 @@ | |||
| 17 | device_type = "memory"; | 17 | device_type = "memory"; |
| 18 | reg = <0x80000000 0x40000000>; /* 1 GB */ | 18 | reg = <0x80000000 0x40000000>; /* 1 GB */ |
| 19 | }; | 19 | }; |
| 20 | |||
| 21 | vmmcsd_fixed: fixedregulator-mmcsd { | ||
| 22 | compatible = "regulator-fixed"; | ||
| 23 | regulator-name = "vmmcsd_fixed"; | ||
| 24 | regulator-min-microvolt = <3000000>; | ||
| 25 | regulator-max-microvolt = <3000000>; | ||
| 26 | }; | ||
| 27 | |||
| 28 | }; | ||
| 29 | |||
| 30 | &mmc1 { | ||
| 31 | vmmc-supply = <&vmmcsd_fixed>; | ||
| 32 | bus-width = <4>; | ||
| 33 | }; | ||
| 34 | |||
| 35 | &mmc2 { | ||
| 36 | vmmc-supply = <&vmmcsd_fixed>; | ||
| 37 | bus-width = <8>; | ||
| 38 | ti,non-removable; | ||
| 39 | }; | ||
| 40 | |||
| 41 | &mmc3 { | ||
| 42 | bus-width = <4>; | ||
| 43 | ti,non-removable; | ||
| 44 | }; | ||
| 45 | |||
| 46 | &mmc4 { | ||
| 47 | status = "disabled"; | ||
| 48 | }; | ||
| 49 | |||
| 50 | &mmc5 { | ||
| 51 | status = "disabled"; | ||
| 52 | }; | ||
| 53 | |||
| 54 | &i2c2 { | ||
| 55 | clock-frequency = <400000>; | ||
| 56 | |||
| 57 | /* Pressure Sensor */ | ||
| 58 | bmp085@77 { | ||
| 59 | compatible = "bosch,bmp085"; | ||
| 60 | reg = <0x77>; | ||
| 61 | }; | ||
| 62 | }; | ||
| 63 | |||
| 64 | &i2c4 { | ||
| 65 | clock-frequency = <400000>; | ||
| 66 | |||
| 67 | /* Temperature Sensor */ | ||
| 68 | tmp102@48{ | ||
| 69 | compatible = "ti,tmp102"; | ||
| 70 | reg = <0x48>; | ||
| 71 | }; | ||
| 72 | }; | ||
| 73 | |||
| 74 | &keypad { | ||
| 75 | keypad,num-rows = <8>; | ||
| 76 | keypad,num-columns = <8>; | ||
| 77 | linux,keymap = <0x02020073 /* VOLUP */ | ||
| 78 | 0x02030072 /* VOLDOWM */ | ||
| 79 | 0x020400e7 /* SEND */ | ||
| 80 | 0x02050066 /* HOME */ | ||
| 81 | 0x0206006b /* END */ | ||
| 82 | 0x020700d9>; /* SEARCH */ | ||
| 83 | linux,input-no-autorepeat; | ||
| 20 | }; | 84 | }; |
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index 57e527083746..5db33f481a33 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi | |||
| @@ -33,9 +33,21 @@ | |||
| 33 | cpus { | 33 | cpus { |
| 34 | cpu@0 { | 34 | cpu@0 { |
| 35 | compatible = "arm,cortex-a15"; | 35 | compatible = "arm,cortex-a15"; |
| 36 | timer { | ||
| 37 | compatible = "arm,armv7-timer"; | ||
| 38 | /* 14th PPI IRQ, active low level-sensitive */ | ||
| 39 | interrupts = <1 14 0x308>; | ||
| 40 | clock-frequency = <6144000>; | ||
| 41 | }; | ||
| 36 | }; | 42 | }; |
| 37 | cpu@1 { | 43 | cpu@1 { |
| 38 | compatible = "arm,cortex-a15"; | 44 | compatible = "arm,cortex-a15"; |
| 45 | timer { | ||
| 46 | compatible = "arm,armv7-timer"; | ||
| 47 | /* 14th PPI IRQ, active low level-sensitive */ | ||
| 48 | interrupts = <1 14 0x308>; | ||
| 49 | clock-frequency = <6144000>; | ||
| 50 | }; | ||
| 39 | }; | 51 | }; |
| 40 | }; | 52 | }; |
| 41 | 53 | ||
| @@ -145,6 +157,41 @@ | |||
| 145 | #interrupt-cells = <1>; | 157 | #interrupt-cells = <1>; |
| 146 | }; | 158 | }; |
| 147 | 159 | ||
| 160 | i2c1: i2c@48070000 { | ||
| 161 | compatible = "ti,omap4-i2c"; | ||
| 162 | #address-cells = <1>; | ||
| 163 | #size-cells = <0>; | ||
| 164 | ti,hwmods = "i2c1"; | ||
| 165 | }; | ||
| 166 | |||
| 167 | i2c2: i2c@48072000 { | ||
| 168 | compatible = "ti,omap4-i2c"; | ||
| 169 | #address-cells = <1>; | ||
| 170 | #size-cells = <0>; | ||
| 171 | ti,hwmods = "i2c2"; | ||
| 172 | }; | ||
| 173 | |||
| 174 | i2c3: i2c@48060000 { | ||
| 175 | compatible = "ti,omap4-i2c"; | ||
| 176 | #address-cells = <1>; | ||
| 177 | #size-cells = <0>; | ||
| 178 | ti,hwmods = "i2c3"; | ||
| 179 | }; | ||
| 180 | |||
| 181 | i2c4: i2c@4807A000 { | ||
| 182 | compatible = "ti,omap4-i2c"; | ||
| 183 | #address-cells = <1>; | ||
| 184 | #size-cells = <0>; | ||
| 185 | ti,hwmods = "i2c4"; | ||
| 186 | }; | ||
| 187 | |||
| 188 | i2c5: i2c@4807C000 { | ||
| 189 | compatible = "ti,omap4-i2c"; | ||
| 190 | #address-cells = <1>; | ||
| 191 | #size-cells = <0>; | ||
| 192 | ti,hwmods = "i2c5"; | ||
| 193 | }; | ||
| 194 | |||
| 148 | uart1: serial@4806a000 { | 195 | uart1: serial@4806a000 { |
| 149 | compatible = "ti,omap4-uart"; | 196 | compatible = "ti,omap4-uart"; |
| 150 | ti,hwmods = "uart1"; | 197 | ti,hwmods = "uart1"; |
| @@ -180,5 +227,97 @@ | |||
| 180 | ti,hwmods = "uart6"; | 227 | ti,hwmods = "uart6"; |
| 181 | clock-frequency = <48000000>; | 228 | clock-frequency = <48000000>; |
| 182 | }; | 229 | }; |
| 230 | |||
| 231 | mmc1: mmc@4809c000 { | ||
| 232 | compatible = "ti,omap4-hsmmc"; | ||
| 233 | ti,hwmods = "mmc1"; | ||
| 234 | ti,dual-volt; | ||
| 235 | ti,needs-special-reset; | ||
| 236 | }; | ||
| 237 | |||
| 238 | mmc2: mmc@480b4000 { | ||
| 239 | compatible = "ti,omap4-hsmmc"; | ||
| 240 | ti,hwmods = "mmc2"; | ||
| 241 | ti,needs-special-reset; | ||
| 242 | }; | ||
| 243 | |||
| 244 | mmc3: mmc@480ad000 { | ||
| 245 | compatible = "ti,omap4-hsmmc"; | ||
| 246 | ti,hwmods = "mmc3"; | ||
| 247 | ti,needs-special-reset; | ||
| 248 | }; | ||
| 249 | |||
| 250 | mmc4: mmc@480d1000 { | ||
| 251 | compatible = "ti,omap4-hsmmc"; | ||
| 252 | ti,hwmods = "mmc4"; | ||
| 253 | ti,needs-special-reset; | ||
| 254 | }; | ||
| 255 | |||
| 256 | mmc5: mmc@480d5000 { | ||
| 257 | compatible = "ti,omap4-hsmmc"; | ||
| 258 | ti,hwmods = "mmc5"; | ||
| 259 | ti,needs-special-reset; | ||
| 260 | }; | ||
| 261 | |||
| 262 | keypad: keypad@4ae1c000 { | ||
| 263 | compatible = "ti,omap4-keypad"; | ||
| 264 | ti,hwmods = "kbd"; | ||
| 265 | }; | ||
| 266 | |||
| 267 | mcpdm: mcpdm@40132000 { | ||
| 268 | compatible = "ti,omap4-mcpdm"; | ||
| 269 | reg = <0x40132000 0x7f>, /* MPU private access */ | ||
| 270 | <0x49032000 0x7f>; /* L3 Interconnect */ | ||
| 271 | reg-names = "mpu", "dma"; | ||
| 272 | interrupts = <0 112 0x4>; | ||
| 273 | interrupt-parent = <&gic>; | ||
| 274 | ti,hwmods = "mcpdm"; | ||
| 275 | }; | ||
| 276 | |||
| 277 | dmic: dmic@4012e000 { | ||
| 278 | compatible = "ti,omap4-dmic"; | ||
| 279 | reg = <0x4012e000 0x7f>, /* MPU private access */ | ||
| 280 | <0x4902e000 0x7f>; /* L3 Interconnect */ | ||
| 281 | reg-names = "mpu", "dma"; | ||
| 282 | interrupts = <0 114 0x4>; | ||
| 283 | interrupt-parent = <&gic>; | ||
| 284 | ti,hwmods = "dmic"; | ||
| 285 | }; | ||
| 286 | |||
| 287 | mcbsp1: mcbsp@40122000 { | ||
| 288 | compatible = "ti,omap4-mcbsp"; | ||
| 289 | reg = <0x40122000 0xff>, /* MPU private access */ | ||
| 290 | <0x49022000 0xff>; /* L3 Interconnect */ | ||
| 291 | reg-names = "mpu", "dma"; | ||
| 292 | interrupts = <0 17 0x4>; | ||
| 293 | interrupt-names = "common"; | ||
| 294 | interrupt-parent = <&gic>; | ||
| 295 | ti,buffer-size = <128>; | ||
| 296 | ti,hwmods = "mcbsp1"; | ||
| 297 | }; | ||
| 298 | |||
| 299 | mcbsp2: mcbsp@40124000 { | ||
| 300 | compatible = "ti,omap4-mcbsp"; | ||
| 301 | reg = <0x40124000 0xff>, /* MPU private access */ | ||
| 302 | <0x49024000 0xff>; /* L3 Interconnect */ | ||
| 303 | reg-names = "mpu", "dma"; | ||
| 304 | interrupts = <0 22 0x4>; | ||
| 305 | interrupt-names = "common"; | ||
| 306 | interrupt-parent = <&gic>; | ||
| 307 | ti,buffer-size = <128>; | ||
| 308 | ti,hwmods = "mcbsp2"; | ||
| 309 | }; | ||
| 310 | |||
| 311 | mcbsp3: mcbsp@40126000 { | ||
| 312 | compatible = "ti,omap4-mcbsp"; | ||
| 313 | reg = <0x40126000 0xff>, /* MPU private access */ | ||
| 314 | <0x49026000 0xff>; /* L3 Interconnect */ | ||
| 315 | reg-names = "mpu", "dma"; | ||
| 316 | interrupts = <0 23 0x4>; | ||
| 317 | interrupt-names = "common"; | ||
| 318 | interrupt-parent = <&gic>; | ||
| 319 | ti,buffer-size = <128>; | ||
| 320 | ti,hwmods = "mcbsp3"; | ||
| 321 | }; | ||
| 183 | }; | 322 | }; |
| 184 | }; | 323 | }; |
diff --git a/arch/arm/boot/dts/phy3250.dts b/arch/arm/boot/dts/phy3250.dts index 802ec5b2fd00..a7ad85e4b8f9 100644 --- a/arch/arm/boot/dts/phy3250.dts +++ b/arch/arm/boot/dts/phy3250.dts | |||
| @@ -135,13 +135,11 @@ | |||
| 135 | ssp0: ssp@20084000 { | 135 | ssp0: ssp@20084000 { |
| 136 | #address-cells = <1>; | 136 | #address-cells = <1>; |
| 137 | #size-cells = <0>; | 137 | #size-cells = <0>; |
| 138 | pl022,num-chipselects = <1>; | 138 | num-cs = <1>; |
| 139 | cs-gpios = <&gpio 3 5 0>; | 139 | cs-gpios = <&gpio 3 5 0>; |
| 140 | 140 | ||
| 141 | eeprom: at25@0 { | 141 | eeprom: at25@0 { |
| 142 | pl022,hierarchy = <0>; | ||
| 143 | pl022,interface = <0>; | 142 | pl022,interface = <0>; |
| 144 | pl022,slave-tx-disable = <0>; | ||
| 145 | pl022,com-mode = <0>; | 143 | pl022,com-mode = <0>; |
| 146 | pl022,rx-level-trig = <1>; | 144 | pl022,rx-level-trig = <1>; |
| 147 | pl022,tx-level-trig = <1>; | 145 | pl022,tx-level-trig = <1>; |
diff --git a/arch/arm/boot/dts/prima2-cb.dts b/arch/arm/boot/dts/prima2-cb.dts deleted file mode 100644 index 34ae3a64ba25..000000000000 --- a/arch/arm/boot/dts/prima2-cb.dts +++ /dev/null | |||
| @@ -1,424 +0,0 @@ | |||
| 1 | /dts-v1/; | ||
| 2 | / { | ||
| 3 | model = "SiRF Prima2 eVB"; | ||
| 4 | compatible = "sirf,prima2-cb", "sirf,prima2"; | ||
| 5 | #address-cells = <1>; | ||
| 6 | #size-cells = <1>; | ||
| 7 | interrupt-parent = <&intc>; | ||
| 8 | |||
| 9 | memory { | ||
| 10 | reg = <0x00000000 0x20000000>; | ||
| 11 | }; | ||
| 12 | |||
| 13 | chosen { | ||
| 14 | bootargs = "mem=512M real_root=/dev/mmcblk0p2 console=ttyS0 panel=1 bootsplash=true bpp=16 androidboot.console=ttyS1"; | ||
| 15 | linux,stdout-path = &uart1; | ||
| 16 | }; | ||
| 17 | |||
| 18 | cpus { | ||
| 19 | #address-cells = <1>; | ||
| 20 | #size-cells = <0>; | ||
| 21 | |||
| 22 | cpu@0 { | ||
| 23 | reg = <0x0>; | ||
| 24 | d-cache-line-size = <32>; | ||
| 25 | i-cache-line-size = <32>; | ||
| 26 | d-cache-size = <32768>; | ||
| 27 | i-cache-size = <32768>; | ||
| 28 | /* from bootloader */ | ||
| 29 | timebase-frequency = <0>; | ||
| 30 | bus-frequency = <0>; | ||
| 31 | clock-frequency = <0>; | ||
| 32 | }; | ||
| 33 | }; | ||
| 34 | |||
| 35 | axi { | ||
| 36 | compatible = "simple-bus"; | ||
| 37 | #address-cells = <1>; | ||
| 38 | #size-cells = <1>; | ||
| 39 | ranges = <0x40000000 0x40000000 0x80000000>; | ||
| 40 | |||
| 41 | l2-cache-controller@80040000 { | ||
| 42 | compatible = "arm,pl310-cache", "sirf,prima2-pl310-cache"; | ||
| 43 | reg = <0x80040000 0x1000>; | ||
| 44 | interrupts = <59>; | ||
| 45 | arm,tag-latency = <1 1 1>; | ||
| 46 | arm,data-latency = <1 1 1>; | ||
| 47 | arm,filter-ranges = <0 0x40000000>; | ||
| 48 | }; | ||
| 49 | |||
| 50 | intc: interrupt-controller@80020000 { | ||
| 51 | #interrupt-cells = <1>; | ||
| 52 | interrupt-controller; | ||
| 53 | compatible = "sirf,prima2-intc"; | ||
| 54 | reg = <0x80020000 0x1000>; | ||
| 55 | }; | ||
| 56 | |||
| 57 | sys-iobg { | ||
| 58 | compatible = "simple-bus"; | ||
| 59 | #address-cells = <1>; | ||
| 60 | #size-cells = <1>; | ||
| 61 | ranges = <0x88000000 0x88000000 0x40000>; | ||
| 62 | |||
| 63 | clock-controller@88000000 { | ||
| 64 | compatible = "sirf,prima2-clkc"; | ||
| 65 | reg = <0x88000000 0x1000>; | ||
| 66 | interrupts = <3>; | ||
| 67 | }; | ||
| 68 | |||
| 69 | reset-controller@88010000 { | ||
| 70 | compatible = "sirf,prima2-rstc"; | ||
| 71 | reg = <0x88010000 0x1000>; | ||
| 72 | }; | ||
| 73 | |||
| 74 | rsc-controller@88020000 { | ||
| 75 | compatible = "sirf,prima2-rsc"; | ||
| 76 | reg = <0x88020000 0x1000>; | ||
| 77 | }; | ||
| 78 | }; | ||
| 79 | |||
| 80 | mem-iobg { | ||
| 81 | compatible = "simple-bus"; | ||
| 82 | #address-cells = <1>; | ||
| 83 | #size-cells = <1>; | ||
| 84 | ranges = <0x90000000 0x90000000 0x10000>; | ||
| 85 | |||
| 86 | memory-controller@90000000 { | ||
| 87 | compatible = "sirf,prima2-memc"; | ||
| 88 | reg = <0x90000000 0x10000>; | ||
| 89 | interrupts = <27>; | ||
| 90 | }; | ||
| 91 | }; | ||
| 92 | |||
| 93 | disp-iobg { | ||
| 94 | compatible = "simple-bus"; | ||
| 95 | #address-cells = <1>; | ||
| 96 | #size-cells = <1>; | ||
| 97 | ranges = <0x90010000 0x90010000 0x30000>; | ||
| 98 | |||
| 99 | display@90010000 { | ||
| 100 | compatible = "sirf,prima2-lcd"; | ||
| 101 | reg = <0x90010000 0x20000>; | ||
| 102 | interrupts = <30>; | ||
| 103 | }; | ||
| 104 | |||
| 105 | vpp@90020000 { | ||
| 106 | compatible = "sirf,prima2-vpp"; | ||
| 107 | reg = <0x90020000 0x10000>; | ||
| 108 | interrupts = <31>; | ||
| 109 | }; | ||
| 110 | }; | ||
| 111 | |||
| 112 | graphics-iobg { | ||
| 113 | compatible = "simple-bus"; | ||
| 114 | #address-cells = <1>; | ||
| 115 | #size-cells = <1>; | ||
| 116 | ranges = <0x98000000 0x98000000 0x8000000>; | ||
| 117 | |||
| 118 | graphics@98000000 { | ||
| 119 | compatible = "powervr,sgx531"; | ||
| 120 | reg = <0x98000000 0x8000000>; | ||
| 121 | interrupts = <6>; | ||
| 122 | }; | ||
| 123 | }; | ||
| 124 | |||
| 125 | multimedia-iobg { | ||
| 126 | compatible = "simple-bus"; | ||
| 127 | #address-cells = <1>; | ||
| 128 | #size-cells = <1>; | ||
| 129 | ranges = <0xa0000000 0xa0000000 0x8000000>; | ||
| 130 | |||
| 131 | multimedia@a0000000 { | ||
| 132 | compatible = "sirf,prima2-video-codec"; | ||
| 133 | reg = <0xa0000000 0x8000000>; | ||
| 134 | interrupts = <5>; | ||
| 135 | }; | ||
| 136 | }; | ||
| 137 | |||
| 138 | dsp-iobg { | ||
| 139 | compatible = "simple-bus"; | ||
| 140 | #address-cells = <1>; | ||
| 141 | #size-cells = <1>; | ||
| 142 | ranges = <0xa8000000 0xa8000000 0x2000000>; | ||
| 143 | |||
| 144 | dspif@a8000000 { | ||
| 145 | compatible = "sirf,prima2-dspif"; | ||
| 146 | reg = <0xa8000000 0x10000>; | ||
| 147 | interrupts = <9>; | ||
| 148 | }; | ||
| 149 | |||
| 150 | gps@a8010000 { | ||
| 151 | compatible = "sirf,prima2-gps"; | ||
| 152 | reg = <0xa8010000 0x10000>; | ||
| 153 | interrupts = <7>; | ||
| 154 | }; | ||
| 155 | |||
| 156 | dsp@a9000000 { | ||
| 157 | compatible = "sirf,prima2-dsp"; | ||
| 158 | reg = <0xa9000000 0x1000000>; | ||
| 159 | interrupts = <8>; | ||
| 160 | }; | ||
| 161 | }; | ||
| 162 | |||
| 163 | peri-iobg { | ||
| 164 | compatible = "simple-bus"; | ||
| 165 | #address-cells = <1>; | ||
| 166 | #size-cells = <1>; | ||
| 167 | ranges = <0xb0000000 0xb0000000 0x180000>; | ||
| 168 | |||
| 169 | timer@b0020000 { | ||
| 170 | compatible = "sirf,prima2-tick"; | ||
| 171 | reg = <0xb0020000 0x1000>; | ||
| 172 | interrupts = <0>; | ||
| 173 | }; | ||
| 174 | |||
| 175 | nand@b0030000 { | ||
| 176 | compatible = "sirf,prima2-nand"; | ||
| 177 | reg = <0xb0030000 0x10000>; | ||
| 178 | interrupts = <41>; | ||
| 179 | }; | ||
| 180 | |||
| 181 | audio@b0040000 { | ||
| 182 | compatible = "sirf,prima2-audio"; | ||
| 183 | reg = <0xb0040000 0x10000>; | ||
| 184 | interrupts = <35>; | ||
| 185 | }; | ||
| 186 | |||
| 187 | uart0: uart@b0050000 { | ||
| 188 | cell-index = <0>; | ||
| 189 | compatible = "sirf,prima2-uart"; | ||
| 190 | reg = <0xb0050000 0x10000>; | ||
| 191 | interrupts = <17>; | ||
| 192 | }; | ||
| 193 | |||
| 194 | uart1: uart@b0060000 { | ||
| 195 | cell-index = <1>; | ||
| 196 | compatible = "sirf,prima2-uart"; | ||
| 197 | reg = <0xb0060000 0x10000>; | ||
| 198 | interrupts = <18>; | ||
| 199 | }; | ||
| 200 | |||
| 201 | uart2: uart@b0070000 { | ||
| 202 | cell-index = <2>; | ||
| 203 | compatible = "sirf,prima2-uart"; | ||
| 204 | reg = <0xb0070000 0x10000>; | ||
| 205 | interrupts = <19>; | ||
| 206 | }; | ||
| 207 | |||
| 208 | usp0: usp@b0080000 { | ||
| 209 | cell-index = <0>; | ||
| 210 | compatible = "sirf,prima2-usp"; | ||
| 211 | reg = <0xb0080000 0x10000>; | ||
| 212 | interrupts = <20>; | ||
| 213 | }; | ||
| 214 | |||
| 215 | usp1: usp@b0090000 { | ||
| 216 | cell-index = <1>; | ||
| 217 | compatible = "sirf,prima2-usp"; | ||
| 218 | reg = <0xb0090000 0x10000>; | ||
| 219 | interrupts = <21>; | ||
| 220 | }; | ||
| 221 | |||
| 222 | usp2: usp@b00a0000 { | ||
| 223 | cell-index = <2>; | ||
| 224 | compatible = "sirf,prima2-usp"; | ||
| 225 | reg = <0xb00a0000 0x10000>; | ||
| 226 | interrupts = <22>; | ||
| 227 | }; | ||
| 228 | |||
| 229 | dmac0: dma-controller@b00b0000 { | ||
| 230 | cell-index = <0>; | ||
| 231 | compatible = "sirf,prima2-dmac"; | ||
| 232 | reg = <0xb00b0000 0x10000>; | ||
| 233 | interrupts = <12>; | ||
| 234 | }; | ||
| 235 | |||
| 236 | dmac1: dma-controller@b0160000 { | ||
| 237 | cell-index = <1>; | ||
| 238 | compatible = "sirf,prima2-dmac"; | ||
| 239 | reg = <0xb0160000 0x10000>; | ||
| 240 | interrupts = <13>; | ||
| 241 | }; | ||
| 242 | |||
| 243 | vip@b00C0000 { | ||
| 244 | compatible = "sirf,prima2-vip"; | ||
| 245 | reg = <0xb00C0000 0x10000>; | ||
| 246 | }; | ||
| 247 | |||
| 248 | spi0: spi@b00d0000 { | ||
| 249 | cell-index = <0>; | ||
| 250 | compatible = "sirf,prima2-spi"; | ||
| 251 | reg = <0xb00d0000 0x10000>; | ||
| 252 | interrupts = <15>; | ||
| 253 | }; | ||
| 254 | |||
| 255 | spi1: spi@b0170000 { | ||
| 256 | cell-index = <1>; | ||
| 257 | compatible = "sirf,prima2-spi"; | ||
| 258 | reg = <0xb0170000 0x10000>; | ||
| 259 | interrupts = <16>; | ||
| 260 | }; | ||
| 261 | |||
| 262 | i2c0: i2c@b00e0000 { | ||
| 263 | cell-index = <0>; | ||
| 264 | compatible = "sirf,prima2-i2c"; | ||
| 265 | reg = <0xb00e0000 0x10000>; | ||
| 266 | interrupts = <24>; | ||
| 267 | }; | ||
| 268 | |||
| 269 | i2c1: i2c@b00f0000 { | ||
| 270 | cell-index = <1>; | ||
| 271 | compatible = "sirf,prima2-i2c"; | ||
| 272 | reg = <0xb00f0000 0x10000>; | ||
| 273 | interrupts = <25>; | ||
| 274 | }; | ||
| 275 | |||
| 276 | tsc@b0110000 { | ||
| 277 | compatible = "sirf,prima2-tsc"; | ||
| 278 | reg = <0xb0110000 0x10000>; | ||
| 279 | interrupts = <33>; | ||
| 280 | }; | ||
| 281 | |||
| 282 | gpio: gpio-controller@b0120000 { | ||
| 283 | #gpio-cells = <2>; | ||
| 284 | #interrupt-cells = <2>; | ||
| 285 | compatible = "sirf,prima2-gpio-pinmux"; | ||
| 286 | reg = <0xb0120000 0x10000>; | ||
| 287 | gpio-controller; | ||
| 288 | interrupt-controller; | ||
| 289 | }; | ||
| 290 | |||
| 291 | pwm@b0130000 { | ||
| 292 | compatible = "sirf,prima2-pwm"; | ||
| 293 | reg = <0xb0130000 0x10000>; | ||
| 294 | }; | ||
| 295 | |||
| 296 | efusesys@b0140000 { | ||
| 297 | compatible = "sirf,prima2-efuse"; | ||
| 298 | reg = <0xb0140000 0x10000>; | ||
| 299 | }; | ||
| 300 | |||
| 301 | pulsec@b0150000 { | ||
| 302 | compatible = "sirf,prima2-pulsec"; | ||
| 303 | reg = <0xb0150000 0x10000>; | ||
| 304 | interrupts = <48>; | ||
| 305 | }; | ||
| 306 | |||
| 307 | pci-iobg { | ||
| 308 | compatible = "sirf,prima2-pciiobg", "simple-bus"; | ||
| 309 | #address-cells = <1>; | ||
| 310 | #size-cells = <1>; | ||
| 311 | ranges = <0x56000000 0x56000000 0x1b00000>; | ||
| 312 | |||
| 313 | sd0: sdhci@56000000 { | ||
| 314 | cell-index = <0>; | ||
| 315 | compatible = "sirf,prima2-sdhc"; | ||
| 316 | reg = <0x56000000 0x100000>; | ||
| 317 | interrupts = <38>; | ||
| 318 | }; | ||
| 319 | |||
| 320 | sd1: sdhci@56100000 { | ||
| 321 | cell-index = <1>; | ||
| 322 | compatible = "sirf,prima2-sdhc"; | ||
| 323 | reg = <0x56100000 0x100000>; | ||
| 324 | interrupts = <38>; | ||
| 325 | }; | ||
| 326 | |||
| 327 | sd2: sdhci@56200000 { | ||
| 328 | cell-index = <2>; | ||
| 329 | compatible = "sirf,prima2-sdhc"; | ||
| 330 | reg = <0x56200000 0x100000>; | ||
| 331 | interrupts = <23>; | ||
| 332 | }; | ||
| 333 | |||
| 334 | sd3: sdhci@56300000 { | ||
| 335 | cell-index = <3>; | ||
| 336 | compatible = "sirf,prima2-sdhc"; | ||
| 337 | reg = <0x56300000 0x100000>; | ||
| 338 | interrupts = <23>; | ||
| 339 | }; | ||
| 340 | |||
| 341 | sd4: sdhci@56400000 { | ||
| 342 | cell-index = <4>; | ||
| 343 | compatible = "sirf,prima2-sdhc"; | ||
| 344 | reg = <0x56400000 0x100000>; | ||
| 345 | interrupts = <39>; | ||
| 346 | }; | ||
| 347 | |||
| 348 | sd5: sdhci@56500000 { | ||
| 349 | cell-index = <5>; | ||
| 350 | compatible = "sirf,prima2-sdhc"; | ||
| 351 | reg = <0x56500000 0x100000>; | ||
| 352 | interrupts = <39>; | ||
| 353 | }; | ||
| 354 | |||
| 355 | pci-copy@57900000 { | ||
| 356 | compatible = "sirf,prima2-pcicp"; | ||
| 357 | reg = <0x57900000 0x100000>; | ||
| 358 | interrupts = <40>; | ||
| 359 | }; | ||
| 360 | |||
| 361 | rom-interface@57a00000 { | ||
| 362 | compatible = "sirf,prima2-romif"; | ||
| 363 | reg = <0x57a00000 0x100000>; | ||
| 364 | }; | ||
| 365 | }; | ||
| 366 | }; | ||
| 367 | |||
| 368 | rtc-iobg { | ||
| 369 | compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus"; | ||
| 370 | #address-cells = <1>; | ||
| 371 | #size-cells = <1>; | ||
| 372 | reg = <0x80030000 0x10000>; | ||
| 373 | |||
| 374 | gpsrtc@1000 { | ||
| 375 | compatible = "sirf,prima2-gpsrtc"; | ||
| 376 | reg = <0x1000 0x1000>; | ||
| 377 | interrupts = <55 56 57>; | ||
| 378 | }; | ||
| 379 | |||
| 380 | sysrtc@2000 { | ||
| 381 | compatible = "sirf,prima2-sysrtc"; | ||
| 382 | reg = <0x2000 0x1000>; | ||
| 383 | interrupts = <52 53 54>; | ||
| 384 | }; | ||
| 385 | |||
| 386 | pwrc@3000 { | ||
| 387 | compatible = "sirf,prima2-pwrc"; | ||
| 388 | reg = <0x3000 0x1000>; | ||
| 389 | interrupts = <32>; | ||
| 390 | }; | ||
| 391 | }; | ||
| 392 | |||
| 393 | uus-iobg { | ||
| 394 | compatible = "simple-bus"; | ||
| 395 | #address-cells = <1>; | ||
| 396 | #size-cells = <1>; | ||
| 397 | ranges = <0xb8000000 0xb8000000 0x40000>; | ||
| 398 | |||
| 399 | usb0: usb@b00e0000 { | ||
| 400 | compatible = "chipidea,ci13611a-prima2"; | ||
| 401 | reg = <0xb8000000 0x10000>; | ||
| 402 | interrupts = <10>; | ||
| 403 | }; | ||
| 404 | |||
| 405 | usb1: usb@b00f0000 { | ||
| 406 | compatible = "chipidea,ci13611a-prima2"; | ||
| 407 | reg = <0xb8010000 0x10000>; | ||
| 408 | interrupts = <11>; | ||
| 409 | }; | ||
| 410 | |||
| 411 | sata@b00f0000 { | ||
| 412 | compatible = "synopsys,dwc-ahsata"; | ||
| 413 | reg = <0xb8020000 0x10000>; | ||
| 414 | interrupts = <37>; | ||
| 415 | }; | ||
| 416 | |||
| 417 | security@b00f0000 { | ||
| 418 | compatible = "sirf,prima2-security"; | ||
| 419 | reg = <0xb8030000 0x10000>; | ||
| 420 | interrupts = <42>; | ||
| 421 | }; | ||
| 422 | }; | ||
| 423 | }; | ||
| 424 | }; | ||
diff --git a/arch/arm/boot/dts/prima2-evb.dts b/arch/arm/boot/dts/prima2-evb.dts new file mode 100644 index 000000000000..57286b4e7b87 --- /dev/null +++ b/arch/arm/boot/dts/prima2-evb.dts | |||
| @@ -0,0 +1,37 @@ | |||
| 1 | /* | ||
| 2 | * DTS file for CSR SiRFprimaII Evaluation Board | ||
| 3 | * | ||
| 4 | * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company. | ||
| 5 | * | ||
| 6 | * Licensed under GPLv2 or later. | ||
| 7 | */ | ||
| 8 | |||
| 9 | /dts-v1/; | ||
| 10 | |||
| 11 | /include/ "prima2.dtsi" | ||
| 12 | |||
| 13 | / { | ||
| 14 | model = "CSR SiRFprimaII Evaluation Board"; | ||
| 15 | compatible = "sirf,prima2", "sirf,prima2-cb"; | ||
| 16 | |||
| 17 | memory { | ||
| 18 | reg = <0x00000000 0x20000000>; | ||
| 19 | }; | ||
| 20 | |||
| 21 | axi { | ||
| 22 | peri-iobg { | ||
| 23 | uart@b0060000 { | ||
| 24 | pinctrl-names = "default"; | ||
| 25 | pinctrl-0 = <&uart1_pins_a>; | ||
| 26 | }; | ||
| 27 | spi@b00d0000 { | ||
| 28 | pinctrl-names = "default"; | ||
| 29 | pinctrl-0 = <&spi0_pins_a>; | ||
| 30 | }; | ||
| 31 | spi@b0170000 { | ||
| 32 | pinctrl-names = "default"; | ||
| 33 | pinctrl-0 = <&spi1_pins_a>; | ||
| 34 | }; | ||
| 35 | }; | ||
| 36 | }; | ||
| 37 | }; | ||
diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi new file mode 100644 index 000000000000..055fca542120 --- /dev/null +++ b/arch/arm/boot/dts/prima2.dtsi | |||
| @@ -0,0 +1,640 @@ | |||
| 1 | /* | ||
| 2 | * DTS file for CSR SiRFprimaII SoC | ||
| 3 | * | ||
| 4 | * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company. | ||
| 5 | * | ||
| 6 | * Licensed under GPLv2 or later. | ||
| 7 | */ | ||
| 8 | |||
| 9 | /include/ "skeleton.dtsi" | ||
| 10 | / { | ||
| 11 | compatible = "sirf,prima2"; | ||
| 12 | #address-cells = <1>; | ||
| 13 | #size-cells = <1>; | ||
| 14 | interrupt-parent = <&intc>; | ||
| 15 | |||
| 16 | cpus { | ||
| 17 | #address-cells = <1>; | ||
| 18 | #size-cells = <0>; | ||
| 19 | |||
| 20 | cpu@0 { | ||
| 21 | reg = <0x0>; | ||
| 22 | d-cache-line-size = <32>; | ||
| 23 | i-cache-line-size = <32>; | ||
| 24 | d-cache-size = <32768>; | ||
| 25 | i-cache-size = <32768>; | ||
| 26 | /* from bootloader */ | ||
| 27 | timebase-frequency = <0>; | ||
| 28 | bus-frequency = <0>; | ||
| 29 | clock-frequency = <0>; | ||
| 30 | }; | ||
| 31 | }; | ||
| 32 | |||
| 33 | axi { | ||
| 34 | compatible = "simple-bus"; | ||
| 35 | #address-cells = <1>; | ||
| 36 | #size-cells = <1>; | ||
| 37 | ranges = <0x40000000 0x40000000 0x80000000>; | ||
| 38 | |||
| 39 | l2-cache-controller@80040000 { | ||
| 40 | compatible = "arm,pl310-cache", "sirf,prima2-pl310-cache"; | ||
| 41 | reg = <0x80040000 0x1000>; | ||
| 42 | interrupts = <59>; | ||
| 43 | arm,tag-latency = <1 1 1>; | ||
| 44 | arm,data-latency = <1 1 1>; | ||
| 45 | arm,filter-ranges = <0 0x40000000>; | ||
| 46 | }; | ||
| 47 | |||
| 48 | intc: interrupt-controller@80020000 { | ||
| 49 | #interrupt-cells = <1>; | ||
| 50 | interrupt-controller; | ||
| 51 | compatible = "sirf,prima2-intc"; | ||
| 52 | reg = <0x80020000 0x1000>; | ||
| 53 | }; | ||
| 54 | |||
| 55 | sys-iobg { | ||
| 56 | compatible = "simple-bus"; | ||
| 57 | #address-cells = <1>; | ||
| 58 | #size-cells = <1>; | ||
| 59 | ranges = <0x88000000 0x88000000 0x40000>; | ||
| 60 | |||
| 61 | clock-controller@88000000 { | ||
| 62 | compatible = "sirf,prima2-clkc"; | ||
| 63 | reg = <0x88000000 0x1000>; | ||
| 64 | interrupts = <3>; | ||
| 65 | }; | ||
| 66 | |||
| 67 | reset-controller@88010000 { | ||
| 68 | compatible = "sirf,prima2-rstc"; | ||
| 69 | reg = <0x88010000 0x1000>; | ||
| 70 | }; | ||
| 71 | |||
| 72 | rsc-controller@88020000 { | ||
| 73 | compatible = "sirf,prima2-rsc"; | ||
| 74 | reg = <0x88020000 0x1000>; | ||
| 75 | }; | ||
| 76 | }; | ||
| 77 | |||
| 78 | mem-iobg { | ||
| 79 | compatible = "simple-bus"; | ||
| 80 | #address-cells = <1>; | ||
| 81 | #size-cells = <1>; | ||
| 82 | ranges = <0x90000000 0x90000000 0x10000>; | ||
| 83 | |||
| 84 | memory-controller@90000000 { | ||
| 85 | compatible = "sirf,prima2-memc"; | ||
| 86 | reg = <0x90000000 0x10000>; | ||
| 87 | interrupts = <27>; | ||
| 88 | }; | ||
| 89 | }; | ||
| 90 | |||
| 91 | disp-iobg { | ||
| 92 | compatible = "simple-bus"; | ||
| 93 | #address-cells = <1>; | ||
| 94 | #size-cells = <1>; | ||
| 95 | ranges = <0x90010000 0x90010000 0x30000>; | ||
| 96 | |||
| 97 | display@90010000 { | ||
| 98 | compatible = "sirf,prima2-lcd"; | ||
| 99 | reg = <0x90010000 0x20000>; | ||
| 100 | interrupts = <30>; | ||
| 101 | }; | ||
| 102 | |||
| 103 | vpp@90020000 { | ||
| 104 | compatible = "sirf,prima2-vpp"; | ||
| 105 | reg = <0x90020000 0x10000>; | ||
| 106 | interrupts = <31>; | ||
| 107 | }; | ||
| 108 | }; | ||
| 109 | |||
| 110 | graphics-iobg { | ||
| 111 | compatible = "simple-bus"; | ||
| 112 | #address-cells = <1>; | ||
| 113 | #size-cells = <1>; | ||
| 114 | ranges = <0x98000000 0x98000000 0x8000000>; | ||
| 115 | |||
| 116 | graphics@98000000 { | ||
| 117 | compatible = "powervr,sgx531"; | ||
| 118 | reg = <0x98000000 0x8000000>; | ||
| 119 | interrupts = <6>; | ||
| 120 | }; | ||
| 121 | }; | ||
| 122 | |||
| 123 | multimedia-iobg { | ||
| 124 | compatible = "simple-bus"; | ||
| 125 | #address-cells = <1>; | ||
| 126 | #size-cells = <1>; | ||
| 127 | ranges = <0xa0000000 0xa0000000 0x8000000>; | ||
| 128 | |||
| 129 | multimedia@a0000000 { | ||
| 130 | compatible = "sirf,prima2-video-codec"; | ||
| 131 | reg = <0xa0000000 0x8000000>; | ||
| 132 | interrupts = <5>; | ||
| 133 | }; | ||
| 134 | }; | ||
| 135 | |||
| 136 | dsp-iobg { | ||
| 137 | compatible = "simple-bus"; | ||
| 138 | #address-cells = <1>; | ||
| 139 | #size-cells = <1>; | ||
| 140 | ranges = <0xa8000000 0xa8000000 0x2000000>; | ||
| 141 | |||
| 142 | dspif@a8000000 { | ||
| 143 | compatible = "sirf,prima2-dspif"; | ||
| 144 | reg = <0xa8000000 0x10000>; | ||
| 145 | interrupts = <9>; | ||
| 146 | }; | ||
| 147 | |||
| 148 | gps@a8010000 { | ||
| 149 | compatible = "sirf,prima2-gps"; | ||
| 150 | reg = <0xa8010000 0x10000>; | ||
| 151 | interrupts = <7>; | ||
| 152 | }; | ||
| 153 | |||
| 154 | dsp@a9000000 { | ||
| 155 | compatible = "sirf,prima2-dsp"; | ||
| 156 | reg = <0xa9000000 0x1000000>; | ||
| 157 | interrupts = <8>; | ||
| 158 | }; | ||
| 159 | }; | ||
| 160 | |||
| 161 | peri-iobg { | ||
| 162 | compatible = "simple-bus"; | ||
| 163 | #address-cells = <1>; | ||
| 164 | #size-cells = <1>; | ||
| 165 | ranges = <0xb0000000 0xb0000000 0x180000>; | ||
| 166 | |||
| 167 | timer@b0020000 { | ||
| 168 | compatible = "sirf,prima2-tick"; | ||
| 169 | reg = <0xb0020000 0x1000>; | ||
| 170 | interrupts = <0>; | ||
| 171 | }; | ||
| 172 | |||
| 173 | nand@b0030000 { | ||
| 174 | compatible = "sirf,prima2-nand"; | ||
| 175 | reg = <0xb0030000 0x10000>; | ||
| 176 | interrupts = <41>; | ||
| 177 | }; | ||
| 178 | |||
| 179 | audio@b0040000 { | ||
| 180 | compatible = "sirf,prima2-audio"; | ||
| 181 | reg = <0xb0040000 0x10000>; | ||
| 182 | interrupts = <35>; | ||
| 183 | }; | ||
| 184 | |||
| 185 | uart0: uart@b0050000 { | ||
| 186 | cell-index = <0>; | ||
| 187 | compatible = "sirf,prima2-uart"; | ||
| 188 | reg = <0xb0050000 0x10000>; | ||
| 189 | interrupts = <17>; | ||
| 190 | }; | ||
| 191 | |||
| 192 | uart1: uart@b0060000 { | ||
| 193 | cell-index = <1>; | ||
| 194 | compatible = "sirf,prima2-uart"; | ||
| 195 | reg = <0xb0060000 0x10000>; | ||
| 196 | interrupts = <18>; | ||
| 197 | }; | ||
| 198 | |||
| 199 | uart2: uart@b0070000 { | ||
| 200 | cell-index = <2>; | ||
| 201 | compatible = "sirf,prima2-uart"; | ||
| 202 | reg = <0xb0070000 0x10000>; | ||
| 203 | interrupts = <19>; | ||
| 204 | }; | ||
| 205 | |||
| 206 | usp0: usp@b0080000 { | ||
| 207 | cell-index = <0>; | ||
| 208 | compatible = "sirf,prima2-usp"; | ||
| 209 | reg = <0xb0080000 0x10000>; | ||
| 210 | interrupts = <20>; | ||
| 211 | }; | ||
| 212 | |||
| 213 | usp1: usp@b0090000 { | ||
| 214 | cell-index = <1>; | ||
| 215 | compatible = "sirf,prima2-usp"; | ||
| 216 | reg = <0xb0090000 0x10000>; | ||
| 217 | interrupts = <21>; | ||
| 218 | }; | ||
| 219 | |||
| 220 | usp2: usp@b00a0000 { | ||
| 221 | cell-index = <2>; | ||
| 222 | compatible = "sirf,prima2-usp"; | ||
| 223 | reg = <0xb00a0000 0x10000>; | ||
| 224 | interrupts = <22>; | ||
| 225 | }; | ||
| 226 | |||
| 227 | dmac0: dma-controller@b00b0000 { | ||
| 228 | cell-index = <0>; | ||
| 229 | compatible = "sirf,prima2-dmac"; | ||
| 230 | reg = <0xb00b0000 0x10000>; | ||
| 231 | interrupts = <12>; | ||
| 232 | }; | ||
| 233 | |||
| 234 | dmac1: dma-controller@b0160000 { | ||
| 235 | cell-index = <1>; | ||
| 236 | compatible = "sirf,prima2-dmac"; | ||
| 237 | reg = <0xb0160000 0x10000>; | ||
| 238 | interrupts = <13>; | ||
| 239 | }; | ||
| 240 | |||
| 241 | vip@b00C0000 { | ||
| 242 | compatible = "sirf,prima2-vip"; | ||
| 243 | reg = <0xb00C0000 0x10000>; | ||
| 244 | }; | ||
| 245 | |||
| 246 | spi0: spi@b00d0000 { | ||
| 247 | cell-index = <0>; | ||
| 248 | compatible = "sirf,prima2-spi"; | ||
| 249 | reg = <0xb00d0000 0x10000>; | ||
| 250 | interrupts = <15>; | ||
| 251 | }; | ||
| 252 | |||
| 253 | spi1: spi@b0170000 { | ||
| 254 | cell-index = <1>; | ||
| 255 | compatible = "sirf,prima2-spi"; | ||
| 256 | reg = <0xb0170000 0x10000>; | ||
| 257 | interrupts = <16>; | ||
| 258 | }; | ||
| 259 | |||
| 260 | i2c0: i2c@b00e0000 { | ||
| 261 | cell-index = <0>; | ||
| 262 | compatible = "sirf,prima2-i2c"; | ||
| 263 | reg = <0xb00e0000 0x10000>; | ||
| 264 | interrupts = <24>; | ||
| 265 | }; | ||
| 266 | |||
| 267 | i2c1: i2c@b00f0000 { | ||
| 268 | cell-index = <1>; | ||
| 269 | compatible = "sirf,prima2-i2c"; | ||
| 270 | reg = <0xb00f0000 0x10000>; | ||
| 271 | interrupts = <25>; | ||
| 272 | }; | ||
| 273 | |||
| 274 | tsc@b0110000 { | ||
| 275 | compatible = "sirf,prima2-tsc"; | ||
| 276 | reg = <0xb0110000 0x10000>; | ||
| 277 | interrupts = <33>; | ||
| 278 | }; | ||
| 279 | |||
| 280 | gpio: pinctrl@b0120000 { | ||
| 281 | #gpio-cells = <2>; | ||
| 282 | #interrupt-cells = <2>; | ||
| 283 | compatible = "sirf,prima2-pinctrl"; | ||
| 284 | reg = <0xb0120000 0x10000>; | ||
| 285 | interrupts = <43 44 45 46 47>; | ||
| 286 | gpio-controller; | ||
| 287 | interrupt-controller; | ||
| 288 | |||
| 289 | lcd_16pins_a: lcd0@0 { | ||
| 290 | lcd { | ||
| 291 | sirf,pins = "lcd_16bitsgrp"; | ||
| 292 | sirf,function = "lcd_16bits"; | ||
| 293 | }; | ||
| 294 | }; | ||
| 295 | lcd_18pins_a: lcd0@1 { | ||
| 296 | lcd { | ||
| 297 | sirf,pins = "lcd_18bitsgrp"; | ||
| 298 | sirf,function = "lcd_18bits"; | ||
| 299 | }; | ||
| 300 | }; | ||
| 301 | lcd_24pins_a: lcd0@2 { | ||
| 302 | lcd { | ||
| 303 | sirf,pins = "lcd_24bitsgrp"; | ||
| 304 | sirf,function = "lcd_24bits"; | ||
| 305 | }; | ||
| 306 | }; | ||
| 307 | lcdrom_pins_a: lcdrom0@0 { | ||
| 308 | lcd { | ||
| 309 | sirf,pins = "lcdromgrp"; | ||
| 310 | sirf,function = "lcdrom"; | ||
| 311 | }; | ||
| 312 | }; | ||
| 313 | uart0_pins_a: uart0@0 { | ||
| 314 | uart { | ||
| 315 | sirf,pins = "uart0grp"; | ||
| 316 | sirf,function = "uart0"; | ||
| 317 | }; | ||
| 318 | }; | ||
| 319 | uart1_pins_a: uart1@0 { | ||
| 320 | uart { | ||
| 321 | sirf,pins = "uart1grp"; | ||
| 322 | sirf,function = "uart1"; | ||
| 323 | }; | ||
| 324 | }; | ||
| 325 | uart2_pins_a: uart2@0 { | ||
| 326 | uart { | ||
| 327 | sirf,pins = "uart2grp"; | ||
| 328 | sirf,function = "uart2"; | ||
| 329 | }; | ||
| 330 | }; | ||
| 331 | uart2_noflow_pins_a: uart2@1 { | ||
| 332 | uart { | ||
| 333 | sirf,pins = "uart2_nostreamctrlgrp"; | ||
| 334 | sirf,function = "uart2_nostreamctrl"; | ||
| 335 | }; | ||
| 336 | }; | ||
| 337 | spi0_pins_a: spi0@0 { | ||
| 338 | spi { | ||
| 339 | sirf,pins = "spi0grp"; | ||
| 340 | sirf,function = "spi0"; | ||
| 341 | }; | ||
| 342 | }; | ||
| 343 | spi1_pins_a: spi1@0 { | ||
| 344 | spi { | ||
| 345 | sirf,pins = "spi1grp"; | ||
| 346 | sirf,function = "spi1"; | ||
| 347 | }; | ||
| 348 | }; | ||
| 349 | i2c0_pins_a: i2c0@0 { | ||
| 350 | i2c { | ||
| 351 | sirf,pins = "i2c0grp"; | ||
| 352 | sirf,function = "i2c0"; | ||
| 353 | }; | ||
| 354 | }; | ||
| 355 | i2c1_pins_a: i2c1@0 { | ||
| 356 | i2c { | ||
| 357 | sirf,pins = "i2c1grp"; | ||
| 358 | sirf,function = "i2c1"; | ||
| 359 | }; | ||
| 360 | }; | ||
| 361 | pwm0_pins_a: pwm0@0 { | ||
| 362 | pwm { | ||
| 363 | sirf,pins = "pwm0grp"; | ||
| 364 | sirf,function = "pwm0"; | ||
| 365 | }; | ||
| 366 | }; | ||
| 367 | pwm1_pins_a: pwm1@0 { | ||
| 368 | pwm { | ||
| 369 | sirf,pins = "pwm1grp"; | ||
| 370 | sirf,function = "pwm1"; | ||
| 371 | }; | ||
| 372 | }; | ||
| 373 | pwm2_pins_a: pwm2@0 { | ||
| 374 | pwm { | ||
| 375 | sirf,pins = "pwm2grp"; | ||
| 376 | sirf,function = "pwm2"; | ||
| 377 | }; | ||
| 378 | }; | ||
| 379 | pwm3_pins_a: pwm3@0 { | ||
| 380 | pwm { | ||
| 381 | sirf,pins = "pwm3grp"; | ||
| 382 | sirf,function = "pwm3"; | ||
| 383 | }; | ||
| 384 | }; | ||
| 385 | gps_pins_a: gps@0 { | ||
| 386 | gps { | ||
| 387 | sirf,pins = "gpsgrp"; | ||
| 388 | sirf,function = "gps"; | ||
| 389 | }; | ||
| 390 | }; | ||
| 391 | vip_pins_a: vip@0 { | ||
| 392 | vip { | ||
| 393 | sirf,pins = "vipgrp"; | ||
| 394 | sirf,function = "vip"; | ||
| 395 | }; | ||
| 396 | }; | ||
| 397 | sdmmc0_pins_a: sdmmc0@0 { | ||
| 398 | sdmmc0 { | ||
| 399 | sirf,pins = "sdmmc0grp"; | ||
| 400 | sirf,function = "sdmmc0"; | ||
| 401 | }; | ||
| 402 | }; | ||
| 403 | sdmmc1_pins_a: sdmmc1@0 { | ||
| 404 | sdmmc1 { | ||
| 405 | sirf,pins = "sdmmc1grp"; | ||
| 406 | sirf,function = "sdmmc1"; | ||
| 407 | }; | ||
| 408 | }; | ||
| 409 | sdmmc2_pins_a: sdmmc2@0 { | ||
| 410 | sdmmc2 { | ||
| 411 | sirf,pins = "sdmmc2grp"; | ||
| 412 | sirf,function = "sdmmc2"; | ||
| 413 | }; | ||
| 414 | }; | ||
| 415 | sdmmc3_pins_a: sdmmc3@0 { | ||
| 416 | sdmmc3 { | ||
| 417 | sirf,pins = "sdmmc3grp"; | ||
| 418 | sirf,function = "sdmmc3"; | ||
| 419 | }; | ||
| 420 | }; | ||
| 421 | sdmmc4_pins_a: sdmmc4@0 { | ||
| 422 | sdmmc4 { | ||
| 423 | sirf,pins = "sdmmc4grp"; | ||
| 424 | sirf,function = "sdmmc4"; | ||
| 425 | }; | ||
| 426 | }; | ||
| 427 | sdmmc5_pins_a: sdmmc5@0 { | ||
| 428 | sdmmc5 { | ||
| 429 | sirf,pins = "sdmmc5grp"; | ||
| 430 | sirf,function = "sdmmc5"; | ||
| 431 | }; | ||
| 432 | }; | ||
| 433 | i2s_pins_a: i2s@0 { | ||
| 434 | i2s { | ||
| 435 | sirf,pins = "i2sgrp"; | ||
| 436 | sirf,function = "i2s"; | ||
| 437 | }; | ||
| 438 | }; | ||
| 439 | ac97_pins_a: ac97@0 { | ||
| 440 | ac97 { | ||
| 441 | sirf,pins = "ac97grp"; | ||
| 442 | sirf,function = "ac97"; | ||
| 443 | }; | ||
| 444 | }; | ||
| 445 | nand_pins_a: nand@0 { | ||
| 446 | nand { | ||
| 447 | sirf,pins = "nandgrp"; | ||
| 448 | sirf,function = "nand"; | ||
| 449 | }; | ||
| 450 | }; | ||
| 451 | usp0_pins_a: usp0@0 { | ||
| 452 | usp0 { | ||
| 453 | sirf,pins = "usp0grp"; | ||
| 454 | sirf,function = "usp0"; | ||
| 455 | }; | ||
| 456 | }; | ||
| 457 | usp1_pins_a: usp1@0 { | ||
| 458 | usp1 { | ||
| 459 | sirf,pins = "usp1grp"; | ||
| 460 | sirf,function = "usp1"; | ||
| 461 | }; | ||
| 462 | }; | ||
| 463 | usp2_pins_a: usp2@0 { | ||
| 464 | usp2 { | ||
| 465 | sirf,pins = "usp2grp"; | ||
| 466 | sirf,function = "usp2"; | ||
| 467 | }; | ||
| 468 | }; | ||
| 469 | usb0_utmi_drvbus_pins_a: usb0_utmi_drvbus@0 { | ||
| 470 | usb0_utmi_drvbus { | ||
| 471 | sirf,pins = "usb0_utmi_drvbusgrp"; | ||
| 472 | sirf,function = "usb0_utmi_drvbus"; | ||
| 473 | }; | ||
| 474 | }; | ||
| 475 | usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus@0 { | ||
| 476 | usb1_utmi_drvbus { | ||
| 477 | sirf,pins = "usb1_utmi_drvbusgrp"; | ||
| 478 | sirf,function = "usb1_utmi_drvbus"; | ||
| 479 | }; | ||
| 480 | }; | ||
| 481 | warm_rst_pins_a: warm_rst@0 { | ||
| 482 | warm_rst { | ||
| 483 | sirf,pins = "warm_rstgrp"; | ||
| 484 | sirf,function = "warm_rst"; | ||
| 485 | }; | ||
| 486 | }; | ||
| 487 | pulse_count_pins_a: pulse_count@0 { | ||
| 488 | pulse_count { | ||
| 489 | sirf,pins = "pulse_countgrp"; | ||
| 490 | sirf,function = "pulse_count"; | ||
| 491 | }; | ||
| 492 | }; | ||
| 493 | cko0_rst_pins_a: cko0_rst@0 { | ||
| 494 | cko0_rst { | ||
| 495 | sirf,pins = "cko0_rstgrp"; | ||
| 496 | sirf,function = "cko0_rst"; | ||
| 497 | }; | ||
| 498 | }; | ||
| 499 | cko1_rst_pins_a: cko1_rst@0 { | ||
| 500 | cko1_rst { | ||
| 501 | sirf,pins = "cko1_rstgrp"; | ||
| 502 | sirf,function = "cko1_rst"; | ||
| 503 | }; | ||
| 504 | }; | ||
| 505 | }; | ||
| 506 | |||
| 507 | pwm@b0130000 { | ||
| 508 | compatible = "sirf,prima2-pwm"; | ||
| 509 | reg = <0xb0130000 0x10000>; | ||
| 510 | }; | ||
| 511 | |||
| 512 | efusesys@b0140000 { | ||
| 513 | compatible = "sirf,prima2-efuse"; | ||
| 514 | reg = <0xb0140000 0x10000>; | ||
| 515 | }; | ||
| 516 | |||
| 517 | pulsec@b0150000 { | ||
| 518 | compatible = "sirf,prima2-pulsec"; | ||
| 519 | reg = <0xb0150000 0x10000>; | ||
| 520 | interrupts = <48>; | ||
| 521 | }; | ||
| 522 | |||
| 523 | pci-iobg { | ||
| 524 | compatible = "sirf,prima2-pciiobg", "simple-bus"; | ||
| 525 | #address-cells = <1>; | ||
| 526 | #size-cells = <1>; | ||
| 527 | ranges = <0x56000000 0x56000000 0x1b00000>; | ||
| 528 | |||
| 529 | sd0: sdhci@56000000 { | ||
| 530 | cell-index = <0>; | ||
| 531 | compatible = "sirf,prima2-sdhc"; | ||
| 532 | reg = <0x56000000 0x100000>; | ||
| 533 | interrupts = <38>; | ||
| 534 | }; | ||
| 535 | |||
| 536 | sd1: sdhci@56100000 { | ||
| 537 | cell-index = <1>; | ||
| 538 | compatible = "sirf,prima2-sdhc"; | ||
| 539 | reg = <0x56100000 0x100000>; | ||
| 540 | interrupts = <38>; | ||
| 541 | }; | ||
| 542 | |||
| 543 | sd2: sdhci@56200000 { | ||
| 544 | cell-index = <2>; | ||
| 545 | compatible = "sirf,prima2-sdhc"; | ||
| 546 | reg = <0x56200000 0x100000>; | ||
| 547 | interrupts = <23>; | ||
| 548 | }; | ||
| 549 | |||
| 550 | sd3: sdhci@56300000 { | ||
| 551 | cell-index = <3>; | ||
| 552 | compatible = "sirf,prima2-sdhc"; | ||
| 553 | reg = <0x56300000 0x100000>; | ||
| 554 | interrupts = <23>; | ||
| 555 | }; | ||
| 556 | |||
| 557 | sd4: sdhci@56400000 { | ||
| 558 | cell-index = <4>; | ||
| 559 | compatible = "sirf,prima2-sdhc"; | ||
| 560 | reg = <0x56400000 0x100000>; | ||
| 561 | interrupts = <39>; | ||
| 562 | }; | ||
| 563 | |||
| 564 | sd5: sdhci@56500000 { | ||
| 565 | cell-index = <5>; | ||
| 566 | compatible = "sirf,prima2-sdhc"; | ||
| 567 | reg = <0x56500000 0x100000>; | ||
| 568 | interrupts = <39>; | ||
| 569 | }; | ||
| 570 | |||
| 571 | pci-copy@57900000 { | ||
| 572 | compatible = "sirf,prima2-pcicp"; | ||
| 573 | reg = <0x57900000 0x100000>; | ||
| 574 | interrupts = <40>; | ||
| 575 | }; | ||
| 576 | |||
| 577 | rom-interface@57a00000 { | ||
| 578 | compatible = "sirf,prima2-romif"; | ||
| 579 | reg = <0x57a00000 0x100000>; | ||
| 580 | }; | ||
| 581 | }; | ||
| 582 | }; | ||
| 583 | |||
| 584 | rtc-iobg { | ||
| 585 | compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus"; | ||
| 586 | #address-cells = <1>; | ||
| 587 | #size-cells = <1>; | ||
| 588 | reg = <0x80030000 0x10000>; | ||
| 589 | |||
| 590 | gpsrtc@1000 { | ||
| 591 | compatible = "sirf,prima2-gpsrtc"; | ||
| 592 | reg = <0x1000 0x1000>; | ||
| 593 | interrupts = <55 56 57>; | ||
| 594 | }; | ||
| 595 | |||
| 596 | sysrtc@2000 { | ||
| 597 | compatible = "sirf,prima2-sysrtc"; | ||
| 598 | reg = <0x2000 0x1000>; | ||
| 599 | interrupts = <52 53 54>; | ||
| 600 | }; | ||
| 601 | |||
| 602 | pwrc@3000 { | ||
| 603 | compatible = "sirf,prima2-pwrc"; | ||
| 604 | reg = <0x3000 0x1000>; | ||
| 605 | interrupts = <32>; | ||
| 606 | }; | ||
| 607 | }; | ||
| 608 | |||
| 609 | uus-iobg { | ||
| 610 | compatible = "simple-bus"; | ||
| 611 | #address-cells = <1>; | ||
| 612 | #size-cells = <1>; | ||
| 613 | ranges = <0xb8000000 0xb8000000 0x40000>; | ||
| 614 | |||
| 615 | usb0: usb@b00e0000 { | ||
| 616 | compatible = "chipidea,ci13611a-prima2"; | ||
| 617 | reg = <0xb8000000 0x10000>; | ||
| 618 | interrupts = <10>; | ||
| 619 | }; | ||
| 620 | |||
| 621 | usb1: usb@b00f0000 { | ||
| 622 | compatible = "chipidea,ci13611a-prima2"; | ||
| 623 | reg = <0xb8010000 0x10000>; | ||
| 624 | interrupts = <11>; | ||
| 625 | }; | ||
| 626 | |||
| 627 | sata@b00f0000 { | ||
| 628 | compatible = "synopsys,dwc-ahsata"; | ||
| 629 | reg = <0xb8020000 0x10000>; | ||
| 630 | interrupts = <37>; | ||
| 631 | }; | ||
| 632 | |||
| 633 | security@b00f0000 { | ||
| 634 | compatible = "sirf,prima2-security"; | ||
| 635 | reg = <0xb8030000 0x10000>; | ||
| 636 | interrupts = <42>; | ||
| 637 | }; | ||
| 638 | }; | ||
| 639 | }; | ||
| 640 | }; | ||
diff --git a/arch/arm/boot/dts/pxa27x.dtsi b/arch/arm/boot/dts/pxa27x.dtsi new file mode 100644 index 000000000000..d7c5d721a5c7 --- /dev/null +++ b/arch/arm/boot/dts/pxa27x.dtsi | |||
| @@ -0,0 +1,14 @@ | |||
| 1 | /* The pxa3xx skeleton simply augments the 2xx version */ | ||
| 2 | /include/ "pxa2xx.dtsi" | ||
| 3 | |||
| 4 | / { | ||
| 5 | model = "Marvell PXA27x familiy SoC"; | ||
| 6 | compatible = "marvell,pxa27x"; | ||
| 7 | |||
| 8 | pxabus { | ||
| 9 | pxairq: interrupt-controller@40d00000 { | ||
| 10 | marvell,intc-priority; | ||
| 11 | marvell,intc-nr-irqs = <34>; | ||
| 12 | }; | ||
| 13 | }; | ||
| 14 | }; | ||
diff --git a/arch/arm/boot/dts/pxa2xx.dtsi b/arch/arm/boot/dts/pxa2xx.dtsi new file mode 100644 index 000000000000..f18aad35e8b3 --- /dev/null +++ b/arch/arm/boot/dts/pxa2xx.dtsi | |||
| @@ -0,0 +1,132 @@ | |||
| 1 | /* | ||
| 2 | * pxa2xx.dtsi - Device Tree Include file for Marvell PXA2xx family SoC | ||
| 3 | * | ||
| 4 | * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> | ||
| 5 | * | ||
| 6 | * Licensed under GPLv2 or later. | ||
| 7 | */ | ||
| 8 | |||
| 9 | /include/ "skeleton.dtsi" | ||
| 10 | |||
| 11 | / { | ||
| 12 | model = "Marvell PXA2xx family SoC"; | ||
| 13 | compatible = "marvell,pxa2xx"; | ||
| 14 | interrupt-parent = <&pxairq>; | ||
| 15 | |||
| 16 | aliases { | ||
| 17 | serial0 = &ffuart; | ||
| 18 | serial1 = &btuart; | ||
| 19 | serial2 = &stuart; | ||
| 20 | serial3 = &hwuart; | ||
| 21 | i2c0 = &pwri2c; | ||
| 22 | i2c1 = &pxai2c1; | ||
| 23 | }; | ||
| 24 | |||
| 25 | cpus { | ||
| 26 | cpu@0 { | ||
| 27 | compatible = "arm,xscale"; | ||
| 28 | }; | ||
| 29 | }; | ||
| 30 | |||
| 31 | pxabus { | ||
| 32 | compatible = "simple-bus"; | ||
| 33 | #address-cells = <1>; | ||
| 34 | #size-cells = <1>; | ||
| 35 | ranges; | ||
| 36 | |||
| 37 | pxairq: interrupt-controller@40d00000 { | ||
| 38 | #interrupt-cells = <1>; | ||
| 39 | compatible = "marvell,pxa-intc"; | ||
| 40 | interrupt-controller; | ||
| 41 | interrupt-parent; | ||
| 42 | marvell,intc-nr-irqs = <32>; | ||
| 43 | reg = <0x40d00000 0xd0>; | ||
| 44 | }; | ||
| 45 | |||
| 46 | gpio: gpio@40e00000 { | ||
| 47 | compatible = "mrvl,pxa-gpio"; | ||
| 48 | #address-cells = <0x1>; | ||
| 49 | #size-cells = <0x1>; | ||
| 50 | reg = <0x40e00000 0x10000>; | ||
| 51 | gpio-controller; | ||
| 52 | #gpio-cells = <0x2>; | ||
| 53 | interrupts = <10>; | ||
| 54 | interrupt-names = "gpio_mux"; | ||
| 55 | interrupt-controller; | ||
| 56 | #interrupt-cells = <0x2>; | ||
| 57 | ranges; | ||
| 58 | |||
| 59 | gcb0: gpio@40e00000 { | ||
| 60 | reg = <0x40e00000 0x4>; | ||
| 61 | }; | ||
| 62 | |||
| 63 | gcb1: gpio@40e00004 { | ||
| 64 | reg = <0x40e00004 0x4>; | ||
| 65 | }; | ||
| 66 | |||
| 67 | gcb2: gpio@40e00008 { | ||
| 68 | reg = <0x40e00008 0x4>; | ||
| 69 | }; | ||
| 70 | gcb3: gpio@40e0000c { | ||
| 71 | reg = <0x40e0000c 0x4>; | ||
| 72 | }; | ||
| 73 | }; | ||
| 74 | |||
| 75 | ffuart: uart@40100000 { | ||
| 76 | compatible = "mrvl,pxa-uart"; | ||
| 77 | reg = <0x40100000 0x30>; | ||
| 78 | interrupts = <22>; | ||
| 79 | status = "disabled"; | ||
| 80 | }; | ||
| 81 | |||
| 82 | btuart: uart@40200000 { | ||
| 83 | compatible = "mrvl,pxa-uart"; | ||
| 84 | reg = <0x40200000 0x30>; | ||
| 85 | interrupts = <21>; | ||
| 86 | status = "disabled"; | ||
| 87 | }; | ||
| 88 | |||
| 89 | stuart: uart@40700000 { | ||
| 90 | compatible = "mrvl,pxa-uart"; | ||
| 91 | reg = <0x40700000 0x30>; | ||
| 92 | interrupts = <20>; | ||
| 93 | status = "disabled"; | ||
| 94 | }; | ||
| 95 | |||
| 96 | hwuart: uart@41100000 { | ||
| 97 | compatible = "mrvl,pxa-uart"; | ||
| 98 | reg = <0x41100000 0x30>; | ||
| 99 | interrupts = <7>; | ||
| 100 | status = "disabled"; | ||
| 101 | }; | ||
| 102 | |||
| 103 | pxai2c1: i2c@40301680 { | ||
| 104 | compatible = "mrvl,pxa-i2c"; | ||
| 105 | reg = <0x40301680 0x30>; | ||
| 106 | interrupts = <18>; | ||
| 107 | #address-cells = <0x1>; | ||
| 108 | #size-cells = <0>; | ||
| 109 | status = "disabled"; | ||
| 110 | }; | ||
| 111 | |||
| 112 | usb0: ohci@4c000000 { | ||
| 113 | compatible = "mrvl,pxa-ohci"; | ||
| 114 | reg = <0x4c000000 0x10000>; | ||
| 115 | interrupts = <3>; | ||
| 116 | status = "disabled"; | ||
| 117 | }; | ||
| 118 | |||
| 119 | mmc0: mmc@41100000 { | ||
| 120 | compatible = "mrvl,pxa-mmc"; | ||
| 121 | reg = <0x41100000 0x1000>; | ||
| 122 | interrupts = <23>; | ||
| 123 | status = "disabled"; | ||
| 124 | }; | ||
| 125 | |||
| 126 | rtc@40900000 { | ||
| 127 | compatible = "marvell,pxa-rtc"; | ||
| 128 | reg = <0x40900000 0x3c>; | ||
| 129 | interrupts = <30 31>; | ||
| 130 | }; | ||
| 131 | }; | ||
| 132 | }; | ||
diff --git a/arch/arm/boot/dts/pxa3xx.dtsi b/arch/arm/boot/dts/pxa3xx.dtsi new file mode 100644 index 000000000000..f9d92da86783 --- /dev/null +++ b/arch/arm/boot/dts/pxa3xx.dtsi | |||
| @@ -0,0 +1,32 @@ | |||
| 1 | /* The pxa3xx skeleton simply augments the 2xx version */ | ||
| 2 | /include/ "pxa2xx.dtsi" | ||
| 3 | |||
| 4 | / { | ||
| 5 | model = "Marvell PXA3xx familiy SoC"; | ||
| 6 | compatible = "marvell,pxa3xx"; | ||
| 7 | |||
| 8 | pxabus { | ||
| 9 | pwri2c: i2c@40f500c0 { | ||
| 10 | compatible = "mrvl,pwri2c"; | ||
| 11 | reg = <0x40f500c0 0x30>; | ||
| 12 | interrupts = <6>; | ||
| 13 | #address-cells = <0x1>; | ||
| 14 | #size-cells = <0>; | ||
| 15 | status = "disabled"; | ||
| 16 | }; | ||
| 17 | |||
| 18 | nand0: nand@43100000 { | ||
| 19 | compatible = "marvell,pxa3xx-nand"; | ||
| 20 | reg = <0x43100000 90>; | ||
| 21 | interrupts = <45>; | ||
| 22 | #address-cells = <1>; | ||
| 23 | #size-cells = <1>; | ||
| 24 | status = "disabled"; | ||
| 25 | }; | ||
| 26 | |||
| 27 | pxairq: interrupt-controller@40d00000 { | ||
| 28 | marvell,intc-priority; | ||
| 29 | marvell,intc-nr-irqs = <56>; | ||
| 30 | }; | ||
| 31 | }; | ||
| 32 | }; | ||
diff --git a/arch/arm/boot/dts/pxa910.dtsi b/arch/arm/boot/dts/pxa910.dtsi index aebf32de73b4..a3be44d86bcd 100644 --- a/arch/arm/boot/dts/pxa910.dtsi +++ b/arch/arm/boot/dts/pxa910.dtsi | |||
| @@ -25,6 +25,11 @@ | |||
| 25 | interrupt-parent = <&intc>; | 25 | interrupt-parent = <&intc>; |
| 26 | ranges; | 26 | ranges; |
| 27 | 27 | ||
| 28 | L2: l2-cache { | ||
| 29 | compatible = "marvell,tauros2-cache"; | ||
| 30 | marvell,tauros2-cache-features = <0x3>; | ||
| 31 | }; | ||
| 32 | |||
| 28 | axi@d4200000 { /* AXI */ | 33 | axi@d4200000 { /* AXI */ |
| 29 | compatible = "mrvl,axi-bus", "simple-bus"; | 34 | compatible = "mrvl,axi-bus", "simple-bus"; |
| 30 | #address-cells = <1>; | 35 | #address-cells = <1>; |
diff --git a/arch/arm/boot/dts/snowball.dts b/arch/arm/boot/dts/snowball.dts index 7e334d4cae21..702c0baa6004 100644 --- a/arch/arm/boot/dts/snowball.dts +++ b/arch/arm/boot/dts/snowball.dts | |||
| @@ -10,7 +10,7 @@ | |||
| 10 | */ | 10 | */ |
| 11 | 11 | ||
| 12 | /dts-v1/; | 12 | /dts-v1/; |
| 13 | /include/ "db8500.dtsi" | 13 | /include/ "dbx5x0.dtsi" |
| 14 | 14 | ||
| 15 | / { | 15 | / { |
| 16 | model = "Calao Systems Snowball platform with device tree"; | 16 | model = "Calao Systems Snowball platform with device tree"; |
| @@ -83,6 +83,22 @@ | |||
| 83 | }; | 83 | }; |
| 84 | 84 | ||
| 85 | soc-u9500 { | 85 | soc-u9500 { |
| 86 | |||
| 87 | sound { | ||
| 88 | compatible = "stericsson,snd-soc-mop500"; | ||
| 89 | |||
| 90 | stericsson,cpu-dai = <&msp1 &msp3>; | ||
| 91 | stericsson,audio-codec = <&codec>; | ||
| 92 | }; | ||
| 93 | |||
| 94 | msp1: msp@80124000 { | ||
| 95 | status = "okay"; | ||
| 96 | }; | ||
| 97 | |||
| 98 | msp3: msp@80125000 { | ||
| 99 | status = "okay"; | ||
| 100 | }; | ||
| 101 | |||
| 86 | external-bus@50000000 { | 102 | external-bus@50000000 { |
| 87 | status = "okay"; | 103 | status = "okay"; |
| 88 | 104 | ||
| @@ -111,7 +127,6 @@ | |||
| 111 | mmc-cap-mmc-highspeed; | 127 | mmc-cap-mmc-highspeed; |
| 112 | vmmc-supply = <&ab8500_ldo_aux3_reg>; | 128 | vmmc-supply = <&ab8500_ldo_aux3_reg>; |
| 113 | 129 | ||
| 114 | #gpio-cells = <1>; | ||
| 115 | cd-gpios = <&gpio6 26 0x4>; // 218 | 130 | cd-gpios = <&gpio6 26 0x4>; // 218 |
| 116 | cd-inverted; | 131 | cd-inverted; |
| 117 | 132 | ||
diff --git a/arch/arm/boot/dts/tegra20-medcom-wide.dts b/arch/arm/boot/dts/tegra20-medcom-wide.dts new file mode 100644 index 000000000000..a2d6d6541f83 --- /dev/null +++ b/arch/arm/boot/dts/tegra20-medcom-wide.dts | |||
| @@ -0,0 +1,58 @@ | |||
| 1 | /dts-v1/; | ||
| 2 | |||
| 3 | /include/ "tegra20-tamonten.dtsi" | ||
| 4 | |||
| 5 | / { | ||
| 6 | model = "Avionic Design Medcom-Wide board"; | ||
| 7 | compatible = "ad,medcom-wide", "ad,tamonten", "nvidia,tegra20"; | ||
| 8 | |||
| 9 | i2c@7000c000 { | ||
| 10 | wm8903: wm8903@1a { | ||
| 11 | compatible = "wlf,wm8903"; | ||
| 12 | reg = <0x1a>; | ||
| 13 | interrupt-parent = <&gpio>; | ||
| 14 | interrupts = <187 0x04>; | ||
| 15 | |||
| 16 | gpio-controller; | ||
| 17 | #gpio-cells = <2>; | ||
| 18 | |||
| 19 | micdet-cfg = <0>; | ||
| 20 | micdet-delay = <100>; | ||
| 21 | gpio-cfg = <0xffffffff | ||
| 22 | 0xffffffff | ||
| 23 | 0 | ||
| 24 | 0xffffffff | ||
| 25 | 0xffffffff>; | ||
| 26 | }; | ||
| 27 | }; | ||
| 28 | |||
| 29 | backlight { | ||
| 30 | compatible = "pwm-backlight"; | ||
| 31 | pwms = <&pwm 0 5000000>; | ||
| 32 | |||
| 33 | brightness-levels = <0 4 8 16 32 64 128 255>; | ||
| 34 | default-brightness-level = <6>; | ||
| 35 | }; | ||
| 36 | |||
| 37 | sound { | ||
| 38 | compatible = "ad,tegra-audio-wm8903-medcom-wide", | ||
| 39 | "nvidia,tegra-audio-wm8903"; | ||
| 40 | nvidia,model = "Avionic Design Medcom-Wide"; | ||
| 41 | |||
| 42 | nvidia,audio-routing = | ||
| 43 | "Headphone Jack", "HPOUTR", | ||
| 44 | "Headphone Jack", "HPOUTL", | ||
| 45 | "Int Spk", "ROP", | ||
| 46 | "Int Spk", "RON", | ||
| 47 | "Int Spk", "LOP", | ||
| 48 | "Int Spk", "LON", | ||
| 49 | "Mic Jack", "MICBIAS", | ||
| 50 | "IN1L", "Mic Jack"; | ||
| 51 | |||
| 52 | nvidia,i2s-controller = <&tegra_i2s1>; | ||
| 53 | nvidia,audio-codec = <&wm8903>; | ||
| 54 | |||
| 55 | nvidia,spkr-en-gpios = <&wm8903 2 0>; | ||
| 56 | nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ | ||
| 57 | }; | ||
| 58 | }; | ||
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index 684a9e1ff7e9..ddf287f52d49 100644 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts | |||
| @@ -272,12 +272,170 @@ | |||
| 272 | status = "okay"; | 272 | status = "okay"; |
| 273 | clock-frequency = <400000>; | 273 | clock-frequency = <400000>; |
| 274 | 274 | ||
| 275 | pmic: tps6586x@34 { | ||
| 276 | compatible = "ti,tps6586x"; | ||
| 277 | reg = <0x34>; | ||
| 278 | interrupts = <0 86 0x4>; | ||
| 279 | |||
| 280 | #gpio-cells = <2>; | ||
| 281 | gpio-controller; | ||
| 282 | |||
| 283 | sys-supply = <&p5valw_reg>; | ||
| 284 | vin-sm0-supply = <&sys_reg>; | ||
| 285 | vin-sm1-supply = <&sys_reg>; | ||
| 286 | vin-sm2-supply = <&sys_reg>; | ||
| 287 | vinldo01-supply = <&sm2_reg>; | ||
| 288 | vinldo23-supply = <&sm2_reg>; | ||
| 289 | vinldo4-supply = <&sm2_reg>; | ||
| 290 | vinldo678-supply = <&sm2_reg>; | ||
| 291 | vinldo9-supply = <&sm2_reg>; | ||
| 292 | |||
| 293 | regulators { | ||
| 294 | #address-cells = <1>; | ||
| 295 | #size-cells = <0>; | ||
| 296 | |||
| 297 | sys_reg: regulator@0 { | ||
| 298 | reg = <0>; | ||
| 299 | regulator-compatible = "sys"; | ||
| 300 | regulator-name = "vdd_sys"; | ||
| 301 | regulator-always-on; | ||
| 302 | }; | ||
| 303 | |||
| 304 | regulator@1 { | ||
| 305 | reg = <1>; | ||
| 306 | regulator-compatible = "sm0"; | ||
| 307 | regulator-name = "+1.2vs_sm0,vdd_core"; | ||
| 308 | regulator-min-microvolt = <1200000>; | ||
| 309 | regulator-max-microvolt = <1200000>; | ||
| 310 | regulator-always-on; | ||
| 311 | }; | ||
| 312 | |||
| 313 | regulator@2 { | ||
| 314 | reg = <2>; | ||
| 315 | regulator-compatible = "sm1"; | ||
| 316 | regulator-name = "+1.0vs_sm1,vdd_cpu"; | ||
| 317 | regulator-min-microvolt = <1000000>; | ||
| 318 | regulator-max-microvolt = <1000000>; | ||
| 319 | regulator-always-on; | ||
| 320 | }; | ||
| 321 | |||
| 322 | sm2_reg: regulator@3 { | ||
| 323 | reg = <3>; | ||
| 324 | regulator-compatible = "sm2"; | ||
| 325 | regulator-name = "+3.7vs_sm2,vin_ldo*"; | ||
| 326 | regulator-min-microvolt = <3700000>; | ||
| 327 | regulator-max-microvolt = <3700000>; | ||
| 328 | regulator-always-on; | ||
| 329 | }; | ||
| 330 | |||
| 331 | /* LDO0 is not connected to anything */ | ||
| 332 | |||
| 333 | regulator@5 { | ||
| 334 | reg = <5>; | ||
| 335 | regulator-compatible = "ldo1"; | ||
| 336 | regulator-name = "+1.1vs_ldo1,avdd_pll*"; | ||
| 337 | regulator-min-microvolt = <1100000>; | ||
| 338 | regulator-max-microvolt = <1100000>; | ||
| 339 | regulator-always-on; | ||
| 340 | }; | ||
| 341 | |||
| 342 | regulator@6 { | ||
| 343 | reg = <6>; | ||
| 344 | regulator-compatible = "ldo2"; | ||
| 345 | regulator-name = "+1.2vs_ldo2,vdd_rtc"; | ||
| 346 | regulator-min-microvolt = <1200000>; | ||
| 347 | regulator-max-microvolt = <1200000>; | ||
| 348 | }; | ||
| 349 | |||
| 350 | regulator@7 { | ||
| 351 | reg = <7>; | ||
| 352 | regulator-compatible = "ldo3"; | ||
| 353 | regulator-name = "+3.3vs_ldo3,avdd_usb*"; | ||
| 354 | regulator-min-microvolt = <3300000>; | ||
| 355 | regulator-max-microvolt = <3300000>; | ||
| 356 | regulator-always-on; | ||
| 357 | }; | ||
| 358 | |||
| 359 | regulator@8 { | ||
| 360 | reg = <8>; | ||
| 361 | regulator-compatible = "ldo4"; | ||
| 362 | regulator-name = "+1.8vs_ldo4,avdd_osc,vddio_sys"; | ||
| 363 | regulator-min-microvolt = <1800000>; | ||
| 364 | regulator-max-microvolt = <1800000>; | ||
| 365 | regulator-always-on; | ||
| 366 | }; | ||
| 367 | |||
| 368 | regulator@9 { | ||
| 369 | reg = <9>; | ||
| 370 | regulator-compatible = "ldo5"; | ||
| 371 | regulator-name = "+2.85vs_ldo5,vcore_mmc"; | ||
| 372 | regulator-min-microvolt = <2850000>; | ||
| 373 | regulator-max-microvolt = <2850000>; | ||
| 374 | regulator-always-on; | ||
| 375 | }; | ||
| 376 | |||
| 377 | regulator@10 { | ||
| 378 | reg = <10>; | ||
| 379 | regulator-compatible = "ldo6"; | ||
| 380 | /* | ||
| 381 | * Research indicates this should be | ||
| 382 | * 1.8v; other boards that use this | ||
| 383 | * rail for the same purpose need it | ||
| 384 | * set to 1.8v. The schematic signal | ||
| 385 | * name is incorrect; perhaps copied | ||
| 386 | * from an incorrect NVIDIA reference. | ||
| 387 | */ | ||
| 388 | regulator-name = "+2.85vs_ldo6,avdd_vdac"; | ||
| 389 | regulator-min-microvolt = <1800000>; | ||
| 390 | regulator-max-microvolt = <1800000>; | ||
| 391 | }; | ||
| 392 | |||
| 393 | regulator@11 { | ||
| 394 | reg = <11>; | ||
| 395 | regulator-compatible = "ldo7"; | ||
| 396 | regulator-name = "+3.3vs_ldo7,avdd_hdmi"; | ||
| 397 | regulator-min-microvolt = <3300000>; | ||
| 398 | regulator-max-microvolt = <3300000>; | ||
| 399 | }; | ||
| 400 | |||
| 401 | regulator@12 { | ||
| 402 | reg = <12>; | ||
| 403 | regulator-compatible = "ldo8"; | ||
| 404 | regulator-name = "+1.8vs_ldo8,avdd_hdmi_pll"; | ||
| 405 | regulator-min-microvolt = <1800000>; | ||
| 406 | regulator-max-microvolt = <1800000>; | ||
| 407 | }; | ||
| 408 | |||
| 409 | regulator@13 { | ||
| 410 | reg = <13>; | ||
| 411 | regulator-compatible = "ldo9"; | ||
| 412 | regulator-name = "+2.85vs_ldo9,vdd_ddr_rx"; | ||
| 413 | regulator-min-microvolt = <2850000>; | ||
| 414 | regulator-max-microvolt = <2850000>; | ||
| 415 | regulator-always-on; | ||
| 416 | }; | ||
| 417 | |||
| 418 | regulator@14 { | ||
| 419 | reg = <14>; | ||
| 420 | regulator-compatible = "ldo_rtc"; | ||
| 421 | regulator-name = "+3.3vs_rtc"; | ||
| 422 | regulator-min-microvolt = <3300000>; | ||
| 423 | regulator-max-microvolt = <3300000>; | ||
| 424 | regulator-always-on; | ||
| 425 | }; | ||
| 426 | }; | ||
| 427 | }; | ||
| 428 | |||
| 275 | adt7461@4c { | 429 | adt7461@4c { |
| 276 | compatible = "adi,adt7461"; | 430 | compatible = "adi,adt7461"; |
| 277 | reg = <0x4c>; | 431 | reg = <0x4c>; |
| 278 | }; | 432 | }; |
| 279 | }; | 433 | }; |
| 280 | 434 | ||
| 435 | pmc { | ||
| 436 | nvidia,invert-interrupt; | ||
| 437 | }; | ||
| 438 | |||
| 281 | usb@c5000000 { | 439 | usb@c5000000 { |
| 282 | status = "okay"; | 440 | status = "okay"; |
| 283 | }; | 441 | }; |
| @@ -325,6 +483,21 @@ | |||
| 325 | }; | 483 | }; |
| 326 | }; | 484 | }; |
| 327 | 485 | ||
| 486 | regulators { | ||
| 487 | compatible = "simple-bus"; | ||
| 488 | #address-cells = <1>; | ||
| 489 | #size-cells = <0>; | ||
| 490 | |||
| 491 | p5valw_reg: regulator@0 { | ||
| 492 | compatible = "regulator-fixed"; | ||
| 493 | reg = <0>; | ||
| 494 | regulator-name = "+5valw"; | ||
| 495 | regulator-min-microvolt = <5000000>; | ||
| 496 | regulator-max-microvolt = <5000000>; | ||
| 497 | regulator-always-on; | ||
| 498 | }; | ||
| 499 | }; | ||
| 500 | |||
| 328 | sound { | 501 | sound { |
| 329 | compatible = "nvidia,tegra-audio-alc5632-paz00", | 502 | compatible = "nvidia,tegra-audio-alc5632-paz00", |
| 330 | "nvidia,tegra-audio-alc5632"; | 503 | "nvidia,tegra-audio-alc5632"; |
diff --git a/arch/arm/boot/dts/tegra20-plutux.dts b/arch/arm/boot/dts/tegra20-plutux.dts new file mode 100644 index 000000000000..331a3ef24d59 --- /dev/null +++ b/arch/arm/boot/dts/tegra20-plutux.dts | |||
| @@ -0,0 +1,50 @@ | |||
| 1 | /dts-v1/; | ||
| 2 | |||
| 3 | /include/ "tegra20-tamonten.dtsi" | ||
| 4 | |||
| 5 | / { | ||
| 6 | model = "Avionic Design Plutux board"; | ||
| 7 | compatible = "ad,plutux", "ad,tamonten", "nvidia,tegra20"; | ||
| 8 | |||
| 9 | i2c@7000c000 { | ||
| 10 | wm8903: wm8903@1a { | ||
| 11 | compatible = "wlf,wm8903"; | ||
| 12 | reg = <0x1a>; | ||
| 13 | interrupt-parent = <&gpio>; | ||
| 14 | interrupts = <187 0x04>; | ||
| 15 | |||
| 16 | gpio-controller; | ||
| 17 | #gpio-cells = <2>; | ||
| 18 | |||
| 19 | micdet-cfg = <0>; | ||
| 20 | micdet-delay = <100>; | ||
| 21 | gpio-cfg = <0xffffffff | ||
| 22 | 0xffffffff | ||
| 23 | 0 | ||
| 24 | 0xffffffff | ||
| 25 | 0xffffffff>; | ||
| 26 | }; | ||
| 27 | }; | ||
| 28 | |||
| 29 | sound { | ||
| 30 | compatible = "ad,tegra-audio-plutux", | ||
| 31 | "nvidia,tegra-audio-wm8903"; | ||
| 32 | nvidia,model = "Avionic Design Plutux"; | ||
| 33 | |||
| 34 | nvidia,audio-routing = | ||
| 35 | "Headphone Jack", "HPOUTR", | ||
| 36 | "Headphone Jack", "HPOUTL", | ||
| 37 | "Int Spk", "ROP", | ||
| 38 | "Int Spk", "RON", | ||
| 39 | "Int Spk", "LOP", | ||
| 40 | "Int Spk", "LON", | ||
| 41 | "Mic Jack", "MICBIAS", | ||
| 42 | "IN1L", "Mic Jack"; | ||
| 43 | |||
| 44 | nvidia,i2s-controller = <&tegra_i2s1>; | ||
| 45 | nvidia,audio-codec = <&wm8903>; | ||
| 46 | |||
| 47 | nvidia,spkr-en-gpios = <&wm8903 2 0>; | ||
| 48 | nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ | ||
| 49 | }; | ||
| 50 | }; | ||
diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts index 85e621ab2968..e60dc7124e92 100644 --- a/arch/arm/boot/dts/tegra20-seaboard.dts +++ b/arch/arm/boot/dts/tegra20-seaboard.dts | |||
| @@ -374,6 +374,154 @@ | |||
| 374 | status = "okay"; | 374 | status = "okay"; |
| 375 | clock-frequency = <400000>; | 375 | clock-frequency = <400000>; |
| 376 | 376 | ||
| 377 | pmic: tps6586x@34 { | ||
| 378 | compatible = "ti,tps6586x"; | ||
| 379 | reg = <0x34>; | ||
| 380 | interrupts = <0 86 0x4>; | ||
| 381 | |||
| 382 | ti,system-power-controller; | ||
| 383 | |||
| 384 | #gpio-cells = <2>; | ||
| 385 | gpio-controller; | ||
| 386 | |||
| 387 | sys-supply = <&vdd_5v0_reg>; | ||
| 388 | vin-sm0-supply = <&sys_reg>; | ||
| 389 | vin-sm1-supply = <&sys_reg>; | ||
| 390 | vin-sm2-supply = <&sys_reg>; | ||
| 391 | vinldo01-supply = <&sm2_reg>; | ||
| 392 | vinldo23-supply = <&sm2_reg>; | ||
| 393 | vinldo4-supply = <&sm2_reg>; | ||
| 394 | vinldo678-supply = <&sm2_reg>; | ||
| 395 | vinldo9-supply = <&sm2_reg>; | ||
| 396 | |||
| 397 | regulators { | ||
| 398 | #address-cells = <1>; | ||
| 399 | #size-cells = <0>; | ||
| 400 | |||
| 401 | sys_reg: regulator@0 { | ||
| 402 | reg = <0>; | ||
| 403 | regulator-compatible = "sys"; | ||
| 404 | regulator-name = "vdd_sys"; | ||
| 405 | regulator-always-on; | ||
| 406 | }; | ||
| 407 | |||
| 408 | regulator@1 { | ||
| 409 | reg = <1>; | ||
| 410 | regulator-compatible = "sm0"; | ||
| 411 | regulator-name = "vdd_sm0,vdd_core"; | ||
| 412 | regulator-min-microvolt = <1300000>; | ||
| 413 | regulator-max-microvolt = <1300000>; | ||
| 414 | regulator-always-on; | ||
| 415 | }; | ||
| 416 | |||
| 417 | regulator@2 { | ||
| 418 | reg = <2>; | ||
| 419 | regulator-compatible = "sm1"; | ||
| 420 | regulator-name = "vdd_sm1,vdd_cpu"; | ||
| 421 | regulator-min-microvolt = <1125000>; | ||
| 422 | regulator-max-microvolt = <1125000>; | ||
| 423 | regulator-always-on; | ||
| 424 | }; | ||
| 425 | |||
| 426 | sm2_reg: regulator@3 { | ||
| 427 | reg = <3>; | ||
| 428 | regulator-compatible = "sm2"; | ||
| 429 | regulator-name = "vdd_sm2,vin_ldo*"; | ||
| 430 | regulator-min-microvolt = <3700000>; | ||
| 431 | regulator-max-microvolt = <3700000>; | ||
| 432 | regulator-always-on; | ||
| 433 | }; | ||
| 434 | |||
| 435 | /* LDO0 is not connected to anything */ | ||
| 436 | |||
| 437 | regulator@5 { | ||
| 438 | reg = <5>; | ||
| 439 | regulator-compatible = "ldo1"; | ||
| 440 | regulator-name = "vdd_ldo1,avdd_pll*"; | ||
| 441 | regulator-min-microvolt = <1100000>; | ||
| 442 | regulator-max-microvolt = <1100000>; | ||
| 443 | regulator-always-on; | ||
| 444 | }; | ||
| 445 | |||
| 446 | regulator@6 { | ||
| 447 | reg = <6>; | ||
| 448 | regulator-compatible = "ldo2"; | ||
| 449 | regulator-name = "vdd_ldo2,vdd_rtc"; | ||
| 450 | regulator-min-microvolt = <1200000>; | ||
| 451 | regulator-max-microvolt = <1200000>; | ||
| 452 | }; | ||
| 453 | |||
| 454 | regulator@7 { | ||
| 455 | reg = <7>; | ||
| 456 | regulator-compatible = "ldo3"; | ||
| 457 | regulator-name = "vdd_ldo3,avdd_usb*"; | ||
| 458 | regulator-min-microvolt = <3300000>; | ||
| 459 | regulator-max-microvolt = <3300000>; | ||
| 460 | regulator-always-on; | ||
| 461 | }; | ||
| 462 | |||
| 463 | regulator@8 { | ||
| 464 | reg = <8>; | ||
| 465 | regulator-compatible = "ldo4"; | ||
| 466 | regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; | ||
| 467 | regulator-min-microvolt = <1800000>; | ||
| 468 | regulator-max-microvolt = <1800000>; | ||
| 469 | regulator-always-on; | ||
| 470 | }; | ||
| 471 | |||
| 472 | regulator@9 { | ||
| 473 | reg = <9>; | ||
| 474 | regulator-compatible = "ldo5"; | ||
| 475 | regulator-name = "vdd_ldo5,vcore_mmc"; | ||
| 476 | regulator-min-microvolt = <2850000>; | ||
| 477 | regulator-max-microvolt = <2850000>; | ||
| 478 | regulator-always-on; | ||
| 479 | }; | ||
| 480 | |||
| 481 | regulator@10 { | ||
| 482 | reg = <10>; | ||
| 483 | regulator-compatible = "ldo6"; | ||
| 484 | regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam"; | ||
| 485 | regulator-min-microvolt = <1800000>; | ||
| 486 | regulator-max-microvolt = <1800000>; | ||
| 487 | }; | ||
| 488 | |||
| 489 | regulator@11 { | ||
| 490 | reg = <11>; | ||
| 491 | regulator-compatible = "ldo7"; | ||
| 492 | regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse"; | ||
| 493 | regulator-min-microvolt = <3300000>; | ||
| 494 | regulator-max-microvolt = <3300000>; | ||
| 495 | }; | ||
| 496 | |||
| 497 | regulator@12 { | ||
| 498 | reg = <12>; | ||
| 499 | regulator-compatible = "ldo8"; | ||
| 500 | regulator-name = "vdd_ldo8,avdd_hdmi_pll"; | ||
| 501 | regulator-min-microvolt = <1800000>; | ||
| 502 | regulator-max-microvolt = <1800000>; | ||
| 503 | }; | ||
| 504 | |||
| 505 | regulator@13 { | ||
| 506 | reg = <13>; | ||
| 507 | regulator-compatible = "ldo9"; | ||
| 508 | regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx"; | ||
| 509 | regulator-min-microvolt = <2850000>; | ||
| 510 | regulator-max-microvolt = <2850000>; | ||
| 511 | regulator-always-on; | ||
| 512 | }; | ||
| 513 | |||
| 514 | regulator@14 { | ||
| 515 | reg = <14>; | ||
| 516 | regulator-compatible = "ldo_rtc"; | ||
| 517 | regulator-name = "vdd_rtc_out,vdd_cell"; | ||
| 518 | regulator-min-microvolt = <3300000>; | ||
| 519 | regulator-max-microvolt = <3300000>; | ||
| 520 | regulator-always-on; | ||
| 521 | }; | ||
| 522 | }; | ||
| 523 | }; | ||
| 524 | |||
| 377 | temperature-sensor@4c { | 525 | temperature-sensor@4c { |
| 378 | compatible = "nct1008"; | 526 | compatible = "nct1008"; |
| 379 | reg = <0x4c>; | 527 | reg = <0x4c>; |
| @@ -387,6 +535,10 @@ | |||
| 387 | }; | 535 | }; |
| 388 | }; | 536 | }; |
| 389 | 537 | ||
| 538 | pmc { | ||
| 539 | nvidia,invert-interrupt; | ||
| 540 | }; | ||
| 541 | |||
| 390 | memory-controller@0x7000f400 { | 542 | memory-controller@0x7000f400 { |
| 391 | emc-table@190000 { | 543 | emc-table@190000 { |
| 392 | reg = <190000>; | 544 | reg = <190000>; |
| @@ -473,6 +625,40 @@ | |||
| 473 | }; | 625 | }; |
| 474 | }; | 626 | }; |
| 475 | 627 | ||
| 628 | regulators { | ||
| 629 | compatible = "simple-bus"; | ||
| 630 | #address-cells = <1>; | ||
| 631 | #size-cells = <0>; | ||
| 632 | |||
| 633 | vdd_5v0_reg: regulator@0 { | ||
| 634 | compatible = "regulator-fixed"; | ||
| 635 | reg = <0>; | ||
| 636 | regulator-name = "vdd_5v0"; | ||
| 637 | regulator-min-microvolt = <5000000>; | ||
| 638 | regulator-max-microvolt = <5000000>; | ||
| 639 | regulator-always-on; | ||
| 640 | }; | ||
| 641 | |||
| 642 | regulator@1 { | ||
| 643 | compatible = "regulator-fixed"; | ||
| 644 | reg = <1>; | ||
| 645 | regulator-name = "vdd_1v5"; | ||
| 646 | regulator-min-microvolt = <1500000>; | ||
| 647 | regulator-max-microvolt = <1500000>; | ||
| 648 | gpio = <&pmic 0 0>; | ||
| 649 | }; | ||
| 650 | |||
| 651 | regulator@2 { | ||
| 652 | compatible = "regulator-fixed"; | ||
| 653 | reg = <2>; | ||
| 654 | regulator-name = "vdd_1v2"; | ||
| 655 | regulator-min-microvolt = <1200000>; | ||
| 656 | regulator-max-microvolt = <1200000>; | ||
| 657 | gpio = <&pmic 1 0>; | ||
| 658 | enable-active-high; | ||
| 659 | }; | ||
| 660 | }; | ||
| 661 | |||
| 476 | sound { | 662 | sound { |
| 477 | compatible = "nvidia,tegra-audio-wm8903-seaboard", | 663 | compatible = "nvidia,tegra-audio-wm8903-seaboard", |
| 478 | "nvidia,tegra-audio-wm8903"; | 664 | "nvidia,tegra-audio-wm8903"; |
diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi new file mode 100644 index 000000000000..f18cec9f6a77 --- /dev/null +++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi | |||
| @@ -0,0 +1,449 @@ | |||
| 1 | /include/ "tegra20.dtsi" | ||
| 2 | |||
| 3 | / { | ||
| 4 | model = "Avionic Design Tamonten SOM"; | ||
| 5 | compatible = "ad,tamonten", "nvidia,tegra20"; | ||
| 6 | |||
| 7 | memory { | ||
| 8 | reg = <0x00000000 0x20000000>; | ||
| 9 | }; | ||
| 10 | |||
| 11 | pinmux { | ||
| 12 | pinctrl-names = "default"; | ||
| 13 | pinctrl-0 = <&state_default>; | ||
| 14 | |||
| 15 | state_default: pinmux { | ||
| 16 | ata { | ||
| 17 | nvidia,pins = "ata"; | ||
| 18 | nvidia,function = "ide"; | ||
| 19 | }; | ||
| 20 | atb { | ||
| 21 | nvidia,pins = "atb", "gma", "gme"; | ||
| 22 | nvidia,function = "sdio4"; | ||
| 23 | }; | ||
| 24 | atc { | ||
| 25 | nvidia,pins = "atc"; | ||
| 26 | nvidia,function = "nand"; | ||
| 27 | }; | ||
| 28 | atd { | ||
| 29 | nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu", | ||
| 30 | "spia", "spib", "spic"; | ||
| 31 | nvidia,function = "gmi"; | ||
| 32 | }; | ||
| 33 | cdev1 { | ||
| 34 | nvidia,pins = "cdev1"; | ||
| 35 | nvidia,function = "plla_out"; | ||
| 36 | }; | ||
| 37 | cdev2 { | ||
| 38 | nvidia,pins = "cdev2"; | ||
| 39 | nvidia,function = "pllp_out4"; | ||
| 40 | }; | ||
| 41 | crtp { | ||
| 42 | nvidia,pins = "crtp"; | ||
| 43 | nvidia,function = "crt"; | ||
| 44 | }; | ||
| 45 | csus { | ||
| 46 | nvidia,pins = "csus"; | ||
| 47 | nvidia,function = "vi_sensor_clk"; | ||
| 48 | }; | ||
| 49 | dap1 { | ||
| 50 | nvidia,pins = "dap1"; | ||
| 51 | nvidia,function = "dap1"; | ||
| 52 | }; | ||
| 53 | dap2 { | ||
| 54 | nvidia,pins = "dap2"; | ||
| 55 | nvidia,function = "dap2"; | ||
| 56 | }; | ||
| 57 | dap3 { | ||
| 58 | nvidia,pins = "dap3"; | ||
| 59 | nvidia,function = "dap3"; | ||
| 60 | }; | ||
| 61 | dap4 { | ||
| 62 | nvidia,pins = "dap4"; | ||
| 63 | nvidia,function = "dap4"; | ||
| 64 | }; | ||
| 65 | ddc { | ||
| 66 | nvidia,pins = "ddc"; | ||
| 67 | nvidia,function = "i2c2"; | ||
| 68 | }; | ||
| 69 | dta { | ||
| 70 | nvidia,pins = "dta", "dtd"; | ||
| 71 | nvidia,function = "sdio2"; | ||
| 72 | }; | ||
| 73 | dtb { | ||
| 74 | nvidia,pins = "dtb", "dtc", "dte"; | ||
| 75 | nvidia,function = "rsvd1"; | ||
| 76 | }; | ||
| 77 | dtf { | ||
| 78 | nvidia,pins = "dtf"; | ||
| 79 | nvidia,function = "i2c3"; | ||
| 80 | }; | ||
| 81 | gmc { | ||
| 82 | nvidia,pins = "gmc"; | ||
| 83 | nvidia,function = "uartd"; | ||
| 84 | }; | ||
| 85 | gpu7 { | ||
| 86 | nvidia,pins = "gpu7"; | ||
| 87 | nvidia,function = "rtck"; | ||
| 88 | }; | ||
| 89 | gpv { | ||
| 90 | nvidia,pins = "gpv", "slxa", "slxk"; | ||
| 91 | nvidia,function = "pcie"; | ||
| 92 | }; | ||
| 93 | hdint { | ||
| 94 | nvidia,pins = "hdint", "pta"; | ||
| 95 | nvidia,function = "hdmi"; | ||
| 96 | }; | ||
| 97 | i2cp { | ||
| 98 | nvidia,pins = "i2cp"; | ||
| 99 | nvidia,function = "i2cp"; | ||
| 100 | }; | ||
| 101 | irrx { | ||
| 102 | nvidia,pins = "irrx", "irtx"; | ||
| 103 | nvidia,function = "uarta"; | ||
| 104 | }; | ||
| 105 | kbca { | ||
| 106 | nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", | ||
| 107 | "kbce", "kbcf"; | ||
| 108 | nvidia,function = "kbc"; | ||
| 109 | }; | ||
| 110 | lcsn { | ||
| 111 | nvidia,pins = "lcsn", "ld0", "ld1", "ld2", | ||
| 112 | "ld3", "ld4", "ld5", "ld6", "ld7", | ||
| 113 | "ld8", "ld9", "ld10", "ld11", "ld12", | ||
| 114 | "ld13", "ld14", "ld15", "ld16", "ld17", | ||
| 115 | "ldc", "ldi", "lhp0", "lhp1", "lhp2", | ||
| 116 | "lhs", "lm0", "lm1", "lpp", "lpw0", | ||
| 117 | "lpw1", "lpw2", "lsc0", "lsc1", "lsck", | ||
| 118 | "lsda", "lsdi", "lspi", "lvp0", "lvp1", | ||
| 119 | "lvs"; | ||
| 120 | nvidia,function = "displaya"; | ||
| 121 | }; | ||
| 122 | owc { | ||
| 123 | nvidia,pins = "owc", "spdi", "spdo", "uac"; | ||
| 124 | nvidia,function = "rsvd2"; | ||
| 125 | }; | ||
| 126 | pmc { | ||
| 127 | nvidia,pins = "pmc"; | ||
| 128 | nvidia,function = "pwr_on"; | ||
| 129 | }; | ||
| 130 | rm { | ||
| 131 | nvidia,pins = "rm"; | ||
| 132 | nvidia,function = "i2c1"; | ||
| 133 | }; | ||
| 134 | sdb { | ||
| 135 | nvidia,pins = "sdb", "sdc", "sdd"; | ||
| 136 | nvidia,function = "pwm"; | ||
| 137 | }; | ||
| 138 | sdio1 { | ||
| 139 | nvidia,pins = "sdio1"; | ||
| 140 | nvidia,function = "sdio1"; | ||
| 141 | }; | ||
| 142 | slxc { | ||
| 143 | nvidia,pins = "slxc", "slxd"; | ||
| 144 | nvidia,function = "spdif"; | ||
| 145 | }; | ||
| 146 | spid { | ||
| 147 | nvidia,pins = "spid", "spie", "spif"; | ||
| 148 | nvidia,function = "spi1"; | ||
| 149 | }; | ||
| 150 | spig { | ||
| 151 | nvidia,pins = "spig", "spih"; | ||
| 152 | nvidia,function = "spi2_alt"; | ||
| 153 | }; | ||
| 154 | uaa { | ||
| 155 | nvidia,pins = "uaa", "uab", "uda"; | ||
| 156 | nvidia,function = "ulpi"; | ||
| 157 | }; | ||
| 158 | uad { | ||
| 159 | nvidia,pins = "uad"; | ||
| 160 | nvidia,function = "irda"; | ||
| 161 | }; | ||
| 162 | uca { | ||
| 163 | nvidia,pins = "uca", "ucb"; | ||
| 164 | nvidia,function = "uartc"; | ||
| 165 | }; | ||
| 166 | conf_ata { | ||
| 167 | nvidia,pins = "ata", "atb", "atc", "atd", "ate", | ||
| 168 | "cdev1", "cdev2", "dap1", "dtb", "gma", | ||
| 169 | "gmb", "gmc", "gmd", "gme", "gpu7", | ||
| 170 | "gpv", "i2cp", "pta", "rm", "slxa", | ||
| 171 | "slxk", "spia", "spib", "uac"; | ||
| 172 | nvidia,pull = <0>; | ||
| 173 | nvidia,tristate = <0>; | ||
| 174 | }; | ||
| 175 | conf_ck32 { | ||
| 176 | nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", | ||
| 177 | "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; | ||
| 178 | nvidia,pull = <0>; | ||
| 179 | }; | ||
| 180 | conf_csus { | ||
| 181 | nvidia,pins = "csus", "spid", "spif"; | ||
| 182 | nvidia,pull = <1>; | ||
| 183 | nvidia,tristate = <1>; | ||
| 184 | }; | ||
| 185 | conf_crtp { | ||
| 186 | nvidia,pins = "crtp", "dap2", "dap3", "dap4", | ||
| 187 | "dtc", "dte", "dtf", "gpu", "sdio1", | ||
| 188 | "slxc", "slxd", "spdi", "spdo", "spig", | ||
| 189 | "uda"; | ||
| 190 | nvidia,pull = <0>; | ||
| 191 | nvidia,tristate = <1>; | ||
| 192 | }; | ||
| 193 | conf_ddc { | ||
| 194 | nvidia,pins = "ddc", "dta", "dtd", "kbca", | ||
| 195 | "kbcb", "kbcc", "kbcd", "kbce", "kbcf", | ||
| 196 | "sdc"; | ||
| 197 | nvidia,pull = <2>; | ||
| 198 | nvidia,tristate = <0>; | ||
| 199 | }; | ||
| 200 | conf_hdint { | ||
| 201 | nvidia,pins = "hdint", "lcsn", "ldc", "lm1", | ||
| 202 | "lpw1", "lsc1", "lsck", "lsda", "lsdi", | ||
| 203 | "lvp0", "owc", "sdb"; | ||
| 204 | nvidia,tristate = <1>; | ||
| 205 | }; | ||
| 206 | conf_irrx { | ||
| 207 | nvidia,pins = "irrx", "irtx", "sdd", "spic", | ||
| 208 | "spie", "spih", "uaa", "uab", "uad", | ||
| 209 | "uca", "ucb"; | ||
| 210 | nvidia,pull = <2>; | ||
| 211 | nvidia,tristate = <1>; | ||
| 212 | }; | ||
| 213 | conf_lc { | ||
| 214 | nvidia,pins = "lc", "ls"; | ||
| 215 | nvidia,pull = <2>; | ||
| 216 | }; | ||
| 217 | conf_ld0 { | ||
| 218 | nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", | ||
| 219 | "ld5", "ld6", "ld7", "ld8", "ld9", | ||
| 220 | "ld10", "ld11", "ld12", "ld13", "ld14", | ||
| 221 | "ld15", "ld16", "ld17", "ldi", "lhp0", | ||
| 222 | "lhp1", "lhp2", "lhs", "lm0", "lpp", | ||
| 223 | "lpw0", "lpw2", "lsc0", "lspi", "lvp1", | ||
| 224 | "lvs", "pmc"; | ||
| 225 | nvidia,tristate = <0>; | ||
| 226 | }; | ||
| 227 | conf_ld17_0 { | ||
| 228 | nvidia,pins = "ld17_0", "ld19_18", "ld21_20", | ||
| 229 | "ld23_22"; | ||
| 230 | nvidia,pull = <1>; | ||
| 231 | }; | ||
| 232 | }; | ||
| 233 | }; | ||
| 234 | |||
| 235 | i2s@70002800 { | ||
| 236 | status = "okay"; | ||
| 237 | }; | ||
| 238 | |||
| 239 | serial@70006300 { | ||
| 240 | clock-frequency = <216000000>; | ||
| 241 | status = "okay"; | ||
| 242 | }; | ||
| 243 | |||
| 244 | i2c@7000c000 { | ||
| 245 | clock-frequency = <400000>; | ||
| 246 | status = "okay"; | ||
| 247 | }; | ||
| 248 | |||
| 249 | i2c@7000d000 { | ||
| 250 | clock-frequency = <400000>; | ||
| 251 | status = "okay"; | ||
| 252 | |||
| 253 | pmic: tps6586x@34 { | ||
| 254 | compatible = "ti,tps6586x"; | ||
| 255 | reg = <0x34>; | ||
| 256 | interrupts = <0 86 0x4>; | ||
| 257 | |||
| 258 | ti,system-power-controller; | ||
| 259 | |||
| 260 | #gpio-cells = <2>; | ||
| 261 | gpio-controller; | ||
| 262 | |||
| 263 | sys-supply = <&vdd_5v0_reg>; | ||
| 264 | vin-sm0-supply = <&sys_reg>; | ||
| 265 | vin-sm1-supply = <&sys_reg>; | ||
| 266 | vin-sm2-supply = <&sys_reg>; | ||
| 267 | vinldo01-supply = <&sm2_reg>; | ||
| 268 | vinldo23-supply = <&sm2_reg>; | ||
| 269 | vinldo4-supply = <&sm2_reg>; | ||
| 270 | vinldo678-supply = <&sm2_reg>; | ||
| 271 | vinldo9-supply = <&sm2_reg>; | ||
| 272 | |||
| 273 | regulators { | ||
| 274 | #address-cells = <1>; | ||
| 275 | #size-cells = <0>; | ||
| 276 | |||
| 277 | sys_reg: regulator@0 { | ||
| 278 | reg = <0>; | ||
| 279 | regulator-compatible = "sys"; | ||
| 280 | regulator-name = "vdd_sys"; | ||
| 281 | regulator-always-on; | ||
| 282 | }; | ||
| 283 | |||
| 284 | regulator@1 { | ||
| 285 | reg = <1>; | ||
| 286 | regulator-compatible = "sm0"; | ||
| 287 | regulator-name = "vdd_sys_sm0,vdd_core"; | ||
| 288 | regulator-min-microvolt = <1200000>; | ||
| 289 | regulator-max-microvolt = <1200000>; | ||
| 290 | regulator-always-on; | ||
| 291 | }; | ||
| 292 | |||
| 293 | regulator@2 { | ||
| 294 | reg = <2>; | ||
| 295 | regulator-compatible = "sm1"; | ||
| 296 | regulator-name = "vdd_sys_sm1,vdd_cpu"; | ||
| 297 | regulator-min-microvolt = <1000000>; | ||
| 298 | regulator-max-microvolt = <1000000>; | ||
| 299 | regulator-always-on; | ||
| 300 | }; | ||
| 301 | |||
| 302 | sm2_reg: regulator@3 { | ||
| 303 | reg = <3>; | ||
| 304 | regulator-compatible = "sm2"; | ||
| 305 | regulator-name = "vdd_sys_sm2,vin_ldo*"; | ||
| 306 | regulator-min-microvolt = <3700000>; | ||
| 307 | regulator-max-microvolt = <3700000>; | ||
| 308 | regulator-always-on; | ||
| 309 | }; | ||
| 310 | |||
| 311 | regulator@4 { | ||
| 312 | reg = <4>; | ||
| 313 | regulator-compatible = "ldo0"; | ||
| 314 | regulator-name = "vdd_ldo0,vddio_pex_clk"; | ||
| 315 | regulator-min-microvolt = <3300000>; | ||
| 316 | regulator-max-microvolt = <3300000>; | ||
| 317 | }; | ||
| 318 | |||
| 319 | regulator@5 { | ||
| 320 | reg = <5>; | ||
| 321 | regulator-compatible = "ldo1"; | ||
| 322 | regulator-name = "vdd_ldo1,avdd_pll*"; | ||
| 323 | regulator-min-microvolt = <1100000>; | ||
| 324 | regulator-max-microvolt = <1100000>; | ||
| 325 | regulator-always-on; | ||
| 326 | }; | ||
| 327 | |||
| 328 | regulator@6 { | ||
| 329 | reg = <6>; | ||
| 330 | regulator-compatible = "ldo2"; | ||
| 331 | regulator-name = "vdd_ldo2,vdd_rtc"; | ||
| 332 | regulator-min-microvolt = <1200000>; | ||
| 333 | regulator-max-microvolt = <1200000>; | ||
| 334 | }; | ||
| 335 | |||
| 336 | regulator@7 { | ||
| 337 | reg = <7>; | ||
| 338 | regulator-compatible = "ldo3"; | ||
| 339 | regulator-name = "vdd_ldo3,avdd_usb*"; | ||
| 340 | regulator-min-microvolt = <3300000>; | ||
| 341 | regulator-max-microvolt = <3300000>; | ||
| 342 | regulator-always-on; | ||
| 343 | }; | ||
| 344 | |||
| 345 | regulator@8 { | ||
| 346 | reg = <8>; | ||
| 347 | regulator-compatible = "ldo4"; | ||
| 348 | regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; | ||
| 349 | regulator-min-microvolt = <1800000>; | ||
| 350 | regulator-max-microvolt = <1800000>; | ||
| 351 | regulator-always-on; | ||
| 352 | }; | ||
| 353 | |||
| 354 | regulator@9 { | ||
| 355 | reg = <9>; | ||
| 356 | regulator-compatible = "ldo5"; | ||
| 357 | regulator-name = "vdd_ldo5,vcore_mmc"; | ||
| 358 | regulator-min-microvolt = <2850000>; | ||
| 359 | regulator-max-microvolt = <2850000>; | ||
| 360 | }; | ||
| 361 | |||
| 362 | regulator@10 { | ||
| 363 | reg = <10>; | ||
| 364 | regulator-compatible = "ldo6"; | ||
| 365 | regulator-name = "vdd_ldo6,avdd_vdac"; | ||
| 366 | /* | ||
| 367 | * According to the Tegra 2 Automotive | ||
| 368 | * DataSheet, a typical value for this | ||
| 369 | * would be 2.8V, but the PMIC only | ||
| 370 | * supports 2.85V. | ||
| 371 | */ | ||
| 372 | regulator-min-microvolt = <2850000>; | ||
| 373 | regulator-max-microvolt = <2850000>; | ||
| 374 | }; | ||
| 375 | |||
| 376 | regulator@11 { | ||
| 377 | reg = <11>; | ||
| 378 | regulator-compatible = "ldo7"; | ||
| 379 | regulator-name = "vdd_ldo7,avdd_hdmi"; | ||
| 380 | regulator-min-microvolt = <3300000>; | ||
| 381 | regulator-max-microvolt = <3300000>; | ||
| 382 | }; | ||
| 383 | |||
| 384 | regulator@12 { | ||
| 385 | reg = <12>; | ||
| 386 | regulator-compatible = "ldo8"; | ||
| 387 | regulator-name = "vdd_ldo8,avdd_hdmi_pll"; | ||
| 388 | regulator-min-microvolt = <1800000>; | ||
| 389 | regulator-max-microvolt = <1800000>; | ||
| 390 | }; | ||
| 391 | |||
| 392 | regulator@13 { | ||
| 393 | reg = <13>; | ||
| 394 | regulator-compatible = "ldo9"; | ||
| 395 | regulator-name = "vdd_ldo9,vdd_ddr_rx,avdd_cam"; | ||
| 396 | /* | ||
| 397 | * According to the Tegra 2 Automotive | ||
| 398 | * DataSheet, a typical value for this | ||
| 399 | * would be 2.8V, but the PMIC only | ||
| 400 | * supports 2.85V. | ||
| 401 | */ | ||
| 402 | regulator-min-microvolt = <2850000>; | ||
| 403 | regulator-max-microvolt = <2850000>; | ||
| 404 | regulator-always-on; | ||
| 405 | }; | ||
| 406 | |||
| 407 | regulator@14 { | ||
| 408 | reg = <14>; | ||
| 409 | regulator-compatible = "ldo_rtc"; | ||
| 410 | regulator-name = "vdd_rtc_out"; | ||
| 411 | regulator-min-microvolt = <3300000>; | ||
| 412 | regulator-max-microvolt = <3300000>; | ||
| 413 | regulator-always-on; | ||
| 414 | }; | ||
| 415 | }; | ||
| 416 | }; | ||
| 417 | }; | ||
| 418 | |||
| 419 | pmc { | ||
| 420 | nvidia,invert-interrupt; | ||
| 421 | }; | ||
| 422 | |||
| 423 | usb@c5008000 { | ||
| 424 | status = "okay"; | ||
| 425 | }; | ||
| 426 | |||
| 427 | sdhci@c8000600 { | ||
| 428 | cd-gpios = <&gpio 58 0>; /* gpio PH2 */ | ||
| 429 | wp-gpios = <&gpio 59 0>; /* gpio PH3 */ | ||
| 430 | bus-width = <4>; | ||
| 431 | status = "okay"; | ||
| 432 | }; | ||
| 433 | |||
| 434 | regulators { | ||
| 435 | compatible = "simple-bus"; | ||
| 436 | |||
| 437 | #address-cells = <1>; | ||
| 438 | #size-cells = <0>; | ||
| 439 | |||
| 440 | vdd_5v0_reg: regulator@0 { | ||
| 441 | compatible = "regulator-fixed"; | ||
| 442 | reg = <0>; | ||
| 443 | regulator-name = "vdd_5v0"; | ||
| 444 | regulator-min-microvolt = <5000000>; | ||
| 445 | regulator-max-microvolt = <5000000>; | ||
| 446 | regulator-always-on; | ||
| 447 | }; | ||
| 448 | }; | ||
| 449 | }; | ||
diff --git a/arch/arm/boot/dts/tegra20-tec.dts b/arch/arm/boot/dts/tegra20-tec.dts new file mode 100644 index 000000000000..9aff31b0fe4a --- /dev/null +++ b/arch/arm/boot/dts/tegra20-tec.dts | |||
| @@ -0,0 +1,53 @@ | |||
| 1 | /dts-v1/; | ||
| 2 | |||
| 3 | /include/ "tegra20-tamonten.dtsi" | ||
| 4 | |||
| 5 | / { | ||
| 6 | model = "Avionic Design Tamonten Evaluation Carrier"; | ||
| 7 | compatible = "ad,tec", "ad,tamonten", "nvidia,tegra20"; | ||
| 8 | |||
| 9 | i2c@7000c000 { | ||
| 10 | clock-frequency = <400000>; | ||
| 11 | status = "okay"; | ||
| 12 | |||
| 13 | wm8903: wm8903@1a { | ||
| 14 | compatible = "wlf,wm8903"; | ||
| 15 | reg = <0x1a>; | ||
| 16 | interrupt-parent = <&gpio>; | ||
| 17 | interrupts = <187 0x04>; | ||
| 18 | |||
| 19 | gpio-controller; | ||
| 20 | #gpio-cells = <2>; | ||
| 21 | |||
| 22 | micdet-cfg = <0>; | ||
| 23 | micdet-delay = <100>; | ||
| 24 | gpio-cfg = <0xffffffff | ||
| 25 | 0xffffffff | ||
| 26 | 0 | ||
| 27 | 0xffffffff | ||
| 28 | 0xffffffff>; | ||
| 29 | }; | ||
| 30 | }; | ||
| 31 | |||
| 32 | sound { | ||
| 33 | compatible = "ad,tegra-audio-wm8903-tec", | ||
| 34 | "nvidia,tegra-audio-wm8903"; | ||
| 35 | nvidia,model = "Avionic Design TEC"; | ||
| 36 | |||
| 37 | nvidia,audio-routing = | ||
| 38 | "Headphone Jack", "HPOUTR", | ||
| 39 | "Headphone Jack", "HPOUTL", | ||
| 40 | "Int Spk", "ROP", | ||
| 41 | "Int Spk", "RON", | ||
| 42 | "Int Spk", "LOP", | ||
| 43 | "Int Spk", "LON", | ||
| 44 | "Mic Jack", "MICBIAS", | ||
| 45 | "IN1L", "Mic Jack"; | ||
| 46 | |||
| 47 | nvidia,i2s-controller = <&tegra_i2s1>; | ||
| 48 | nvidia,audio-codec = <&wm8903>; | ||
| 49 | |||
| 50 | nvidia,spkr-en-gpios = <&wm8903 2 0>; | ||
| 51 | nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ | ||
| 52 | }; | ||
| 53 | }; | ||
diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts index be90544e6b59..3e5952fcfbc5 100644 --- a/arch/arm/boot/dts/tegra20-ventana.dts +++ b/arch/arm/boot/dts/tegra20-ventana.dts | |||
| @@ -289,6 +289,158 @@ | |||
| 289 | i2c@7000d000 { | 289 | i2c@7000d000 { |
| 290 | status = "okay"; | 290 | status = "okay"; |
| 291 | clock-frequency = <400000>; | 291 | clock-frequency = <400000>; |
| 292 | |||
| 293 | pmic: tps6586x@34 { | ||
| 294 | compatible = "ti,tps6586x"; | ||
| 295 | reg = <0x34>; | ||
| 296 | interrupts = <0 86 0x4>; | ||
| 297 | |||
| 298 | ti,system-power-controller; | ||
| 299 | |||
| 300 | #gpio-cells = <2>; | ||
| 301 | gpio-controller; | ||
| 302 | |||
| 303 | sys-supply = <&vdd_5v0_reg>; | ||
| 304 | vin-sm0-supply = <&sys_reg>; | ||
| 305 | vin-sm1-supply = <&sys_reg>; | ||
| 306 | vin-sm2-supply = <&sys_reg>; | ||
| 307 | vinldo01-supply = <&sm2_reg>; | ||
| 308 | vinldo23-supply = <&sm2_reg>; | ||
| 309 | vinldo4-supply = <&sm2_reg>; | ||
| 310 | vinldo678-supply = <&sm2_reg>; | ||
| 311 | vinldo9-supply = <&sm2_reg>; | ||
| 312 | |||
| 313 | regulators { | ||
| 314 | #address-cells = <1>; | ||
| 315 | #size-cells = <0>; | ||
| 316 | |||
| 317 | sys_reg: regulator@0 { | ||
| 318 | reg = <0>; | ||
| 319 | regulator-compatible = "sys"; | ||
| 320 | regulator-name = "vdd_sys"; | ||
| 321 | regulator-always-on; | ||
| 322 | }; | ||
| 323 | |||
| 324 | regulator@1 { | ||
| 325 | reg = <1>; | ||
| 326 | regulator-compatible = "sm0"; | ||
| 327 | regulator-name = "vdd_sm0,vdd_core"; | ||
| 328 | regulator-min-microvolt = <1200000>; | ||
| 329 | regulator-max-microvolt = <1200000>; | ||
| 330 | regulator-always-on; | ||
| 331 | }; | ||
| 332 | |||
| 333 | regulator@2 { | ||
| 334 | reg = <2>; | ||
| 335 | regulator-compatible = "sm1"; | ||
| 336 | regulator-name = "vdd_sm1,vdd_cpu"; | ||
| 337 | regulator-min-microvolt = <1000000>; | ||
| 338 | regulator-max-microvolt = <1000000>; | ||
| 339 | regulator-always-on; | ||
| 340 | }; | ||
| 341 | |||
| 342 | sm2_reg: regulator@3 { | ||
| 343 | reg = <3>; | ||
| 344 | regulator-compatible = "sm2"; | ||
| 345 | regulator-name = "vdd_sm2,vin_ldo*"; | ||
| 346 | regulator-min-microvolt = <3700000>; | ||
| 347 | regulator-max-microvolt = <3700000>; | ||
| 348 | regulator-always-on; | ||
| 349 | }; | ||
| 350 | |||
| 351 | /* LDO0 is not connected to anything */ | ||
| 352 | |||
| 353 | regulator@5 { | ||
| 354 | reg = <5>; | ||
| 355 | regulator-compatible = "ldo1"; | ||
| 356 | regulator-name = "vdd_ldo1,avdd_pll*"; | ||
| 357 | regulator-min-microvolt = <1100000>; | ||
| 358 | regulator-max-microvolt = <1100000>; | ||
| 359 | regulator-always-on; | ||
| 360 | }; | ||
| 361 | |||
| 362 | regulator@6 { | ||
| 363 | reg = <6>; | ||
| 364 | regulator-compatible = "ldo2"; | ||
| 365 | regulator-name = "vdd_ldo2,vdd_rtc"; | ||
| 366 | regulator-min-microvolt = <1200000>; | ||
| 367 | regulator-max-microvolt = <1200000>; | ||
| 368 | }; | ||
| 369 | |||
| 370 | regulator@7 { | ||
| 371 | reg = <7>; | ||
| 372 | regulator-compatible = "ldo3"; | ||
| 373 | regulator-name = "vdd_ldo3,avdd_usb*"; | ||
| 374 | regulator-min-microvolt = <3300000>; | ||
| 375 | regulator-max-microvolt = <3300000>; | ||
| 376 | regulator-always-on; | ||
| 377 | }; | ||
| 378 | |||
| 379 | regulator@8 { | ||
| 380 | reg = <8>; | ||
| 381 | regulator-compatible = "ldo4"; | ||
| 382 | regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; | ||
| 383 | regulator-min-microvolt = <1800000>; | ||
| 384 | regulator-max-microvolt = <1800000>; | ||
| 385 | regulator-always-on; | ||
| 386 | }; | ||
| 387 | |||
| 388 | regulator@9 { | ||
| 389 | reg = <9>; | ||
| 390 | regulator-compatible = "ldo5"; | ||
| 391 | regulator-name = "vdd_ldo5,vcore_mmc"; | ||
| 392 | regulator-min-microvolt = <2850000>; | ||
| 393 | regulator-max-microvolt = <2850000>; | ||
| 394 | regulator-always-on; | ||
| 395 | }; | ||
| 396 | |||
| 397 | regulator@10 { | ||
| 398 | reg = <10>; | ||
| 399 | regulator-compatible = "ldo6"; | ||
| 400 | regulator-name = "vdd_ldo6,avdd_vdac"; | ||
| 401 | regulator-min-microvolt = <1800000>; | ||
| 402 | regulator-max-microvolt = <1800000>; | ||
| 403 | }; | ||
| 404 | |||
| 405 | regulator@11 { | ||
| 406 | reg = <11>; | ||
| 407 | regulator-compatible = "ldo7"; | ||
| 408 | regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse"; | ||
| 409 | regulator-min-microvolt = <3300000>; | ||
| 410 | regulator-max-microvolt = <3300000>; | ||
| 411 | }; | ||
| 412 | |||
| 413 | regulator@12 { | ||
| 414 | reg = <12>; | ||
| 415 | regulator-compatible = "ldo8"; | ||
| 416 | regulator-name = "vdd_ldo8,avdd_hdmi_pll"; | ||
| 417 | regulator-min-microvolt = <1800000>; | ||
| 418 | regulator-max-microvolt = <1800000>; | ||
| 419 | }; | ||
| 420 | |||
| 421 | regulator@13 { | ||
| 422 | reg = <13>; | ||
| 423 | regulator-compatible = "ldo9"; | ||
| 424 | regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx"; | ||
| 425 | regulator-min-microvolt = <2850000>; | ||
| 426 | regulator-max-microvolt = <2850000>; | ||
| 427 | regulator-always-on; | ||
| 428 | }; | ||
| 429 | |||
| 430 | regulator@14 { | ||
| 431 | reg = <14>; | ||
| 432 | regulator-compatible = "ldo_rtc"; | ||
| 433 | regulator-name = "vdd_rtc_out,vdd_cell"; | ||
| 434 | regulator-min-microvolt = <3300000>; | ||
| 435 | regulator-max-microvolt = <3300000>; | ||
| 436 | regulator-always-on; | ||
| 437 | }; | ||
| 438 | }; | ||
| 439 | }; | ||
| 440 | }; | ||
| 441 | |||
| 442 | pmc { | ||
| 443 | nvidia,invert-interrupt; | ||
| 292 | }; | 444 | }; |
| 293 | 445 | ||
| 294 | usb@c5000000 { | 446 | usb@c5000000 { |
| @@ -317,6 +469,60 @@ | |||
| 317 | bus-width = <8>; | 469 | bus-width = <8>; |
| 318 | }; | 470 | }; |
| 319 | 471 | ||
| 472 | regulators { | ||
| 473 | compatible = "simple-bus"; | ||
| 474 | #address-cells = <1>; | ||
| 475 | #size-cells = <0>; | ||
| 476 | |||
| 477 | vdd_5v0_reg: regulator@0 { | ||
| 478 | compatible = "regulator-fixed"; | ||
| 479 | reg = <0>; | ||
| 480 | regulator-name = "vdd_5v0"; | ||
| 481 | regulator-min-microvolt = <5000000>; | ||
| 482 | regulator-max-microvolt = <5000000>; | ||
| 483 | regulator-always-on; | ||
| 484 | }; | ||
| 485 | |||
| 486 | regulator@1 { | ||
| 487 | compatible = "regulator-fixed"; | ||
| 488 | reg = <1>; | ||
| 489 | regulator-name = "vdd_1v5"; | ||
| 490 | regulator-min-microvolt = <1500000>; | ||
| 491 | regulator-max-microvolt = <1500000>; | ||
| 492 | gpio = <&pmic 0 0>; | ||
| 493 | }; | ||
| 494 | |||
| 495 | regulator@2 { | ||
| 496 | compatible = "regulator-fixed"; | ||
| 497 | reg = <2>; | ||
| 498 | regulator-name = "vdd_1v2"; | ||
| 499 | regulator-min-microvolt = <1200000>; | ||
| 500 | regulator-max-microvolt = <1200000>; | ||
| 501 | gpio = <&pmic 1 0>; | ||
| 502 | enable-active-high; | ||
| 503 | }; | ||
| 504 | |||
| 505 | regulator@3 { | ||
| 506 | compatible = "regulator-fixed"; | ||
| 507 | reg = <3>; | ||
| 508 | regulator-name = "vdd_pnl"; | ||
| 509 | regulator-min-microvolt = <2800000>; | ||
| 510 | regulator-max-microvolt = <2800000>; | ||
| 511 | gpio = <&gpio 22 0>; /* gpio PC6 */ | ||
| 512 | enable-active-high; | ||
| 513 | }; | ||
| 514 | |||
| 515 | regulator@4 { | ||
| 516 | compatible = "regulator-fixed"; | ||
| 517 | reg = <4>; | ||
| 518 | regulator-name = "vdd_bl"; | ||
| 519 | regulator-min-microvolt = <2800000>; | ||
| 520 | regulator-max-microvolt = <2800000>; | ||
| 521 | gpio = <&gpio 176 0>; /* gpio PW0 */ | ||
| 522 | enable-active-high; | ||
| 523 | }; | ||
| 524 | }; | ||
| 525 | |||
| 320 | sound { | 526 | sound { |
| 321 | compatible = "nvidia,tegra-audio-wm8903-ventana", | 527 | compatible = "nvidia,tegra-audio-wm8903-ventana", |
| 322 | "nvidia,tegra-audio-wm8903"; | 528 | "nvidia,tegra-audio-wm8903"; |
diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts index 6916310bf58f..c636d002d6d8 100644 --- a/arch/arm/boot/dts/tegra20-whistler.dts +++ b/arch/arm/boot/dts/tegra20-whistler.dts | |||
| @@ -261,6 +261,286 @@ | |||
| 261 | gpio-controller; | 261 | gpio-controller; |
| 262 | #gpio-cells = <2>; | 262 | #gpio-cells = <2>; |
| 263 | }; | 263 | }; |
| 264 | |||
| 265 | max8907@3c { | ||
| 266 | compatible = "maxim,max8907"; | ||
| 267 | reg = <0x3c>; | ||
| 268 | interrupts = <0 86 0x4>; | ||
| 269 | |||
| 270 | maxim,system-power-controller; | ||
| 271 | |||
| 272 | mbatt-supply = <&usb0_vbus_reg>; | ||
| 273 | in-v1-supply = <&mbatt_reg>; | ||
| 274 | in-v2-supply = <&mbatt_reg>; | ||
| 275 | in-v3-supply = <&mbatt_reg>; | ||
| 276 | in1-supply = <&mbatt_reg>; | ||
| 277 | in2-supply = <&nvvdd_sv3_reg>; | ||
| 278 | in3-supply = <&mbatt_reg>; | ||
| 279 | in4-supply = <&mbatt_reg>; | ||
| 280 | in5-supply = <&mbatt_reg>; | ||
| 281 | in6-supply = <&mbatt_reg>; | ||
| 282 | in7-supply = <&mbatt_reg>; | ||
| 283 | in8-supply = <&mbatt_reg>; | ||
| 284 | in9-supply = <&mbatt_reg>; | ||
| 285 | in10-supply = <&mbatt_reg>; | ||
| 286 | in11-supply = <&mbatt_reg>; | ||
| 287 | in12-supply = <&mbatt_reg>; | ||
| 288 | in13-supply = <&mbatt_reg>; | ||
| 289 | in14-supply = <&mbatt_reg>; | ||
| 290 | in15-supply = <&mbatt_reg>; | ||
| 291 | in16-supply = <&mbatt_reg>; | ||
| 292 | in17-supply = <&nvvdd_sv3_reg>; | ||
| 293 | in18-supply = <&nvvdd_sv3_reg>; | ||
| 294 | in19-supply = <&mbatt_reg>; | ||
| 295 | in20-supply = <&mbatt_reg>; | ||
| 296 | |||
| 297 | regulators { | ||
| 298 | #address-cells = <1>; | ||
| 299 | #size-cells = <0>; | ||
| 300 | |||
| 301 | mbatt_reg: regulator@0 { | ||
| 302 | reg = <0>; | ||
| 303 | regulator-compatible = "mbatt"; | ||
| 304 | regulator-name = "vbat_pmu"; | ||
| 305 | regulator-always-on; | ||
| 306 | }; | ||
| 307 | |||
| 308 | regulator@1 { | ||
| 309 | reg = <1>; | ||
| 310 | regulator-compatible = "sd1"; | ||
| 311 | regulator-name = "nvvdd_sv1,vdd_cpu_pmu"; | ||
| 312 | regulator-min-microvolt = <1000000>; | ||
| 313 | regulator-max-microvolt = <1000000>; | ||
| 314 | regulator-always-on; | ||
| 315 | }; | ||
| 316 | |||
| 317 | regulator@2 { | ||
| 318 | reg = <2>; | ||
| 319 | regulator-compatible = "sd2"; | ||
| 320 | regulator-name = "nvvdd_sv2,vdd_core"; | ||
| 321 | regulator-min-microvolt = <1200000>; | ||
| 322 | regulator-max-microvolt = <1200000>; | ||
| 323 | regulator-always-on; | ||
| 324 | }; | ||
| 325 | |||
| 326 | nvvdd_sv3_reg: regulator@3 { | ||
| 327 | reg = <3>; | ||
| 328 | regulator-compatible = "sd3"; | ||
| 329 | regulator-name = "nvvdd_sv3"; | ||
| 330 | regulator-min-microvolt = <1800000>; | ||
| 331 | regulator-max-microvolt = <1800000>; | ||
| 332 | regulator-always-on; | ||
| 333 | }; | ||
| 334 | |||
| 335 | regulator@4 { | ||
| 336 | reg = <4>; | ||
| 337 | regulator-compatible = "ldo1"; | ||
| 338 | regulator-name = "nvvdd_ldo1,vddio_rx_ddr,vcore_acc"; | ||
| 339 | regulator-min-microvolt = <3300000>; | ||
| 340 | regulator-max-microvolt = <3300000>; | ||
| 341 | regulator-always-on; | ||
| 342 | }; | ||
| 343 | |||
| 344 | regulator@5 { | ||
| 345 | reg = <5>; | ||
| 346 | regulator-compatible = "ldo2"; | ||
| 347 | regulator-name = "nvvdd_ldo2,avdd_pll*"; | ||
| 348 | regulator-min-microvolt = <1100000>; | ||
| 349 | regulator-max-microvolt = <1100000>; | ||
| 350 | regulator-always-on; | ||
| 351 | }; | ||
| 352 | |||
| 353 | regulator@6 { | ||
| 354 | reg = <6>; | ||
| 355 | regulator-compatible = "ldo3"; | ||
| 356 | regulator-name = "nvvdd_ldo3,vcom_1v8b"; | ||
| 357 | regulator-min-microvolt = <1800000>; | ||
| 358 | regulator-max-microvolt = <1800000>; | ||
| 359 | regulator-always-on; | ||
| 360 | }; | ||
| 361 | |||
| 362 | regulator@7 { | ||
| 363 | reg = <7>; | ||
| 364 | regulator-compatible = "ldo4"; | ||
| 365 | regulator-name = "nvvdd_ldo4,avdd_usb*"; | ||
| 366 | regulator-min-microvolt = <3300000>; | ||
| 367 | regulator-max-microvolt = <3300000>; | ||
| 368 | regulator-always-on; | ||
| 369 | }; | ||
| 370 | |||
| 371 | regulator@8 { | ||
| 372 | reg = <8>; | ||
| 373 | regulator-compatible = "ldo5"; | ||
| 374 | regulator-name = "nvvdd_ldo5,vcore_mmc,avdd_lcd1,vddio_1wire"; | ||
| 375 | regulator-min-microvolt = <2800000>; | ||
| 376 | regulator-max-microvolt = <2800000>; | ||
| 377 | regulator-always-on; | ||
| 378 | }; | ||
| 379 | |||
| 380 | regulator@9 { | ||
| 381 | reg = <9>; | ||
| 382 | regulator-compatible = "ldo6"; | ||
| 383 | regulator-name = "nvvdd_ldo6,avdd_hdmi_pll"; | ||
| 384 | regulator-min-microvolt = <1800000>; | ||
| 385 | regulator-max-microvolt = <1800000>; | ||
| 386 | }; | ||
| 387 | |||
| 388 | regulator@10 { | ||
| 389 | reg = <10>; | ||
| 390 | regulator-compatible = "ldo7"; | ||
| 391 | regulator-name = "nvvdd_ldo7,avddio_audio"; | ||
| 392 | regulator-min-microvolt = <2800000>; | ||
| 393 | regulator-max-microvolt = <2800000>; | ||
| 394 | regulator-always-on; | ||
| 395 | }; | ||
| 396 | |||
| 397 | regulator@11 { | ||
| 398 | reg = <11>; | ||
| 399 | regulator-compatible = "ldo8"; | ||
| 400 | regulator-name = "nvvdd_ldo8,vcom_3v0,vcore_cmps"; | ||
| 401 | regulator-min-microvolt = <3000000>; | ||
| 402 | regulator-max-microvolt = <3000000>; | ||
| 403 | }; | ||
| 404 | |||
| 405 | regulator@12 { | ||
| 406 | reg = <12>; | ||
| 407 | regulator-compatible = "ldo9"; | ||
| 408 | regulator-name = "nvvdd_ldo9,avdd_cam*"; | ||
| 409 | regulator-min-microvolt = <2800000>; | ||
| 410 | regulator-max-microvolt = <2800000>; | ||
| 411 | }; | ||
| 412 | |||
| 413 | regulator@13 { | ||
| 414 | reg = <13>; | ||
| 415 | regulator-compatible = "ldo10"; | ||
| 416 | regulator-name = "nvvdd_ldo10,avdd_usb_ic_3v0"; | ||
| 417 | regulator-min-microvolt = <3000000>; | ||
| 418 | regulator-max-microvolt = <3000000>; | ||
| 419 | regulator-always-on; | ||
| 420 | }; | ||
| 421 | |||
| 422 | regulator@14 { | ||
| 423 | reg = <14>; | ||
| 424 | regulator-compatible = "ldo11"; | ||
| 425 | regulator-name = "nvvdd_ldo11,vddio_pex_clk,vcom_33,avdd_hdmi"; | ||
| 426 | regulator-min-microvolt = <3300000>; | ||
| 427 | regulator-max-microvolt = <3300000>; | ||
| 428 | }; | ||
| 429 | |||
| 430 | regulator@15 { | ||
| 431 | reg = <15>; | ||
| 432 | regulator-compatible = "ldo12"; | ||
| 433 | regulator-name = "nvvdd_ldo12,vddio_sdio"; | ||
| 434 | regulator-min-microvolt = <2800000>; | ||
| 435 | regulator-max-microvolt = <2800000>; | ||
| 436 | regulator-always-on; | ||
| 437 | }; | ||
| 438 | |||
| 439 | regulator@16 { | ||
| 440 | reg = <16>; | ||
| 441 | regulator-compatible = "ldo13"; | ||
| 442 | regulator-name = "nvvdd_ldo13,vcore_phtn,vdd_af"; | ||
| 443 | regulator-min-microvolt = <2800000>; | ||
| 444 | regulator-max-microvolt = <2800000>; | ||
| 445 | }; | ||
| 446 | |||
| 447 | regulator@17 { | ||
| 448 | reg = <17>; | ||
| 449 | regulator-compatible = "ldo14"; | ||
| 450 | regulator-name = "nvvdd_ldo14,avdd_vdac"; | ||
| 451 | regulator-min-microvolt = <2800000>; | ||
| 452 | regulator-max-microvolt = <2800000>; | ||
| 453 | }; | ||
| 454 | |||
| 455 | regulator@18 { | ||
| 456 | reg = <18>; | ||
| 457 | regulator-compatible = "ldo15"; | ||
| 458 | regulator-name = "nvvdd_ldo15,vcore_temp,vddio_hdcp"; | ||
| 459 | regulator-min-microvolt = <3300000>; | ||
| 460 | regulator-max-microvolt = <3300000>; | ||
| 461 | }; | ||
| 462 | |||
| 463 | regulator@19 { | ||
| 464 | reg = <19>; | ||
| 465 | regulator-compatible = "ldo16"; | ||
| 466 | regulator-name = "nvvdd_ldo16,vdd_dbrtr"; | ||
| 467 | regulator-min-microvolt = <1300000>; | ||
| 468 | regulator-max-microvolt = <1300000>; | ||
| 469 | }; | ||
| 470 | |||
| 471 | regulator@20 { | ||
| 472 | reg = <20>; | ||
| 473 | regulator-compatible = "ldo17"; | ||
| 474 | regulator-name = "nvvdd_ldo17,vddio_mipi"; | ||
| 475 | regulator-min-microvolt = <1200000>; | ||
| 476 | regulator-max-microvolt = <1200000>; | ||
| 477 | }; | ||
| 478 | |||
| 479 | regulator@21 { | ||
| 480 | reg = <21>; | ||
| 481 | regulator-compatible = "ldo18"; | ||
| 482 | regulator-name = "nvvdd_ldo18,vddio_vi,vcore_cam*"; | ||
| 483 | regulator-min-microvolt = <1800000>; | ||
| 484 | regulator-max-microvolt = <1800000>; | ||
| 485 | }; | ||
| 486 | |||
| 487 | regulator@22 { | ||
| 488 | reg = <22>; | ||
| 489 | regulator-compatible = "ldo19"; | ||
| 490 | regulator-name = "nvvdd_ldo19,avdd_lcd2,vddio_lx"; | ||
| 491 | regulator-min-microvolt = <2800000>; | ||
| 492 | regulator-max-microvolt = <2800000>; | ||
| 493 | }; | ||
| 494 | |||
| 495 | regulator@23 { | ||
| 496 | reg = <23>; | ||
| 497 | regulator-compatible = "ldo20"; | ||
| 498 | regulator-name = "nvvdd_ldo20,vddio_ddr_1v2,vddio_hsic,vcom_1v2"; | ||
| 499 | regulator-min-microvolt = <1200000>; | ||
| 500 | regulator-max-microvolt = <1200000>; | ||
| 501 | regulator-always-on; | ||
| 502 | }; | ||
| 503 | |||
| 504 | regulator@24 { | ||
| 505 | reg = <24>; | ||
| 506 | regulator-compatible = "out5v"; | ||
| 507 | regulator-name = "usb0_vbus_reg"; | ||
| 508 | }; | ||
| 509 | |||
| 510 | regulator@25 { | ||
| 511 | reg = <25>; | ||
| 512 | regulator-compatible = "out33v"; | ||
| 513 | regulator-name = "pmu_out3v3"; | ||
| 514 | }; | ||
| 515 | |||
| 516 | regulator@26 { | ||
| 517 | reg = <26>; | ||
| 518 | regulator-compatible = "bbat"; | ||
| 519 | regulator-name = "pmu_bbat"; | ||
| 520 | regulator-min-microvolt = <2400000>; | ||
| 521 | regulator-max-microvolt = <2400000>; | ||
| 522 | regulator-always-on; | ||
| 523 | }; | ||
| 524 | |||
| 525 | regulator@27 { | ||
| 526 | reg = <27>; | ||
| 527 | regulator-compatible = "sdby"; | ||
| 528 | regulator-name = "vdd_aon"; | ||
| 529 | regulator-always-on; | ||
| 530 | }; | ||
| 531 | |||
| 532 | regulator@28 { | ||
| 533 | reg = <28>; | ||
| 534 | regulator-compatible = "vrtc"; | ||
| 535 | regulator-name = "vrtc,pmu_vccadc"; | ||
| 536 | regulator-always-on; | ||
| 537 | }; | ||
| 538 | }; | ||
| 539 | }; | ||
| 540 | }; | ||
| 541 | |||
| 542 | pmc { | ||
| 543 | nvidia,invert-interrupt; | ||
| 264 | }; | 544 | }; |
| 265 | 545 | ||
| 266 | usb@c5000000 { | 546 | usb@c5000000 { |
| @@ -284,6 +564,21 @@ | |||
| 284 | bus-width = <8>; | 564 | bus-width = <8>; |
| 285 | }; | 565 | }; |
| 286 | 566 | ||
| 567 | regulators { | ||
| 568 | compatible = "simple-bus"; | ||
| 569 | #address-cells = <1>; | ||
| 570 | #size-cells = <0>; | ||
| 571 | |||
| 572 | usb0_vbus_reg: regulator { | ||
| 573 | compatible = "regulator-fixed"; | ||
| 574 | reg = <0>; | ||
| 575 | regulator-name = "usb0_vbus"; | ||
| 576 | regulator-min-microvolt = <5000000>; | ||
| 577 | regulator-max-microvolt = <5000000>; | ||
| 578 | regulator-always-on; | ||
| 579 | }; | ||
| 580 | }; | ||
| 581 | |||
| 287 | sound { | 582 | sound { |
| 288 | compatible = "nvidia,tegra-audio-wm8753-whistler", | 583 | compatible = "nvidia,tegra-audio-wm8753-whistler", |
| 289 | "nvidia,tegra-audio-wm8753"; | 584 | "nvidia,tegra-audio-wm8753"; |
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 405d1673904e..67a6cd910b96 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi | |||
| @@ -123,7 +123,7 @@ | |||
| 123 | status = "disabled"; | 123 | status = "disabled"; |
| 124 | }; | 124 | }; |
| 125 | 125 | ||
| 126 | pwm { | 126 | pwm: pwm { |
| 127 | compatible = "nvidia,tegra20-pwm"; | 127 | compatible = "nvidia,tegra20-pwm"; |
| 128 | reg = <0x7000a000 0x100>; | 128 | reg = <0x7000a000 0x100>; |
| 129 | #pwm-cells = <2>; | 129 | #pwm-cells = <2>; |
diff --git a/arch/arm/boot/dts/tegra30-cardhu-a02.dts b/arch/arm/boot/dts/tegra30-cardhu-a02.dts new file mode 100644 index 000000000000..dd4222f00eca --- /dev/null +++ b/arch/arm/boot/dts/tegra30-cardhu-a02.dts | |||
| @@ -0,0 +1,87 @@ | |||
| 1 | /dts-v1/; | ||
| 2 | |||
| 3 | /include/ "tegra30-cardhu.dtsi" | ||
| 4 | |||
| 5 | /* This dts file support the cardhu A02 version of board */ | ||
| 6 | |||
| 7 | / { | ||
| 8 | model = "NVIDIA Tegra30 Cardhu A02 evaluation board"; | ||
| 9 | compatible = "nvidia,cardhu-a02", "nvidia,cardhu", "nvidia,tegra30"; | ||
| 10 | |||
| 11 | regulators { | ||
| 12 | compatible = "simple-bus"; | ||
| 13 | #address-cells = <1>; | ||
| 14 | #size-cells = <0>; | ||
| 15 | |||
| 16 | ddr_reg: regulator@100 { | ||
| 17 | compatible = "regulator-fixed"; | ||
| 18 | reg = <100>; | ||
| 19 | regulator-name = "vdd_ddr"; | ||
| 20 | regulator-min-microvolt = <1500000>; | ||
| 21 | regulator-max-microvolt = <1500000>; | ||
| 22 | regulator-always-on; | ||
| 23 | regulator-boot-on; | ||
| 24 | enable-active-high; | ||
| 25 | gpio = <&pmic 6 0>; | ||
| 26 | }; | ||
| 27 | |||
| 28 | sys_3v3_reg: regulator@101 { | ||
| 29 | compatible = "regulator-fixed"; | ||
| 30 | reg = <101>; | ||
| 31 | regulator-name = "sys_3v3"; | ||
| 32 | regulator-min-microvolt = <3300000>; | ||
| 33 | regulator-max-microvolt = <3300000>; | ||
| 34 | regulator-always-on; | ||
| 35 | regulator-boot-on; | ||
| 36 | enable-active-high; | ||
| 37 | gpio = <&pmic 7 0>; | ||
| 38 | }; | ||
| 39 | |||
| 40 | usb1_vbus_reg: regulator@102 { | ||
| 41 | compatible = "regulator-fixed"; | ||
| 42 | reg = <102>; | ||
| 43 | regulator-name = "usb1_vbus"; | ||
| 44 | regulator-min-microvolt = <5000000>; | ||
| 45 | regulator-max-microvolt = <5000000>; | ||
| 46 | enable-active-high; | ||
| 47 | gpio = <&gpio 68 0>; /* GPIO PI4 */ | ||
| 48 | gpio-open-drain; | ||
| 49 | vin-supply = <&vdd_5v0_reg>; | ||
| 50 | }; | ||
| 51 | |||
| 52 | usb3_vbus_reg: regulator@103 { | ||
| 53 | compatible = "regulator-fixed"; | ||
| 54 | reg = <103>; | ||
| 55 | regulator-name = "usb3_vbus"; | ||
| 56 | regulator-min-microvolt = <5000000>; | ||
| 57 | regulator-max-microvolt = <5000000>; | ||
| 58 | enable-active-high; | ||
| 59 | gpio = <&gpio 63 0>; /* GPIO PH7 */ | ||
| 60 | gpio-open-drain; | ||
| 61 | vin-supply = <&vdd_5v0_reg>; | ||
| 62 | }; | ||
| 63 | |||
| 64 | vdd_5v0_reg: regulator@104 { | ||
| 65 | compatible = "regulator-fixed"; | ||
| 66 | reg = <104>; | ||
| 67 | regulator-name = "5v0"; | ||
| 68 | regulator-min-microvolt = <5000000>; | ||
| 69 | regulator-max-microvolt = <5000000>; | ||
| 70 | enable-active-high; | ||
| 71 | gpio = <&pmic 2 0>; | ||
| 72 | }; | ||
| 73 | |||
| 74 | vdd_bl_reg: regulator@105 { | ||
| 75 | compatible = "regulator-fixed"; | ||
| 76 | reg = <105>; | ||
| 77 | regulator-name = "vdd_bl"; | ||
| 78 | regulator-min-microvolt = <5000000>; | ||
| 79 | regulator-max-microvolt = <5000000>; | ||
| 80 | regulator-always-on; | ||
| 81 | regulator-boot-on; | ||
| 82 | enable-active-high; | ||
| 83 | gpio = <&gpio 83 0>; /* GPIO PK3 */ | ||
| 84 | }; | ||
| 85 | }; | ||
| 86 | }; | ||
| 87 | |||
diff --git a/arch/arm/boot/dts/tegra30-cardhu-a04.dts b/arch/arm/boot/dts/tegra30-cardhu-a04.dts new file mode 100644 index 000000000000..0828f097ca86 --- /dev/null +++ b/arch/arm/boot/dts/tegra30-cardhu-a04.dts | |||
| @@ -0,0 +1,98 @@ | |||
| 1 | /dts-v1/; | ||
| 2 | |||
| 3 | /include/ "tegra30-cardhu.dtsi" | ||
| 4 | |||
| 5 | /* This dts file support the cardhu A04 and later versions of board */ | ||
| 6 | |||
| 7 | / { | ||
| 8 | model = "NVIDIA Tegra30 Cardhu A04 (A05, A06, A07) evaluation board"; | ||
| 9 | compatible = "nvidia,cardhu-a04", "nvidia,cardhu", "nvidia,tegra30"; | ||
| 10 | |||
| 11 | regulators { | ||
| 12 | compatible = "simple-bus"; | ||
| 13 | #address-cells = <1>; | ||
| 14 | #size-cells = <0>; | ||
| 15 | |||
| 16 | ddr_reg: regulator@100 { | ||
| 17 | compatible = "regulator-fixed"; | ||
| 18 | regulator-name = "ddr"; | ||
| 19 | reg = <100>; | ||
| 20 | regulator-min-microvolt = <1500000>; | ||
| 21 | regulator-max-microvolt = <1500000>; | ||
| 22 | regulator-always-on; | ||
| 23 | regulator-boot-on; | ||
| 24 | enable-active-high; | ||
| 25 | gpio = <&pmic 7 0>; | ||
| 26 | }; | ||
| 27 | |||
| 28 | sys_3v3_reg: regulator@101 { | ||
| 29 | compatible = "regulator-fixed"; | ||
| 30 | reg = <101>; | ||
| 31 | regulator-name = "sys_3v3"; | ||
| 32 | regulator-min-microvolt = <3300000>; | ||
| 33 | regulator-max-microvolt = <3300000>; | ||
| 34 | regulator-always-on; | ||
| 35 | regulator-boot-on; | ||
| 36 | enable-active-high; | ||
| 37 | gpio = <&pmic 6 0>; | ||
| 38 | }; | ||
| 39 | |||
| 40 | usb1_vbus_reg: regulator@102 { | ||
| 41 | compatible = "regulator-fixed"; | ||
| 42 | reg = <102>; | ||
| 43 | regulator-name = "usb1_vbus"; | ||
| 44 | regulator-min-microvolt = <5000000>; | ||
| 45 | regulator-max-microvolt = <5000000>; | ||
| 46 | enable-active-high; | ||
| 47 | gpio = <&gpio 238 0>; /* GPIO PDD6 */ | ||
| 48 | gpio-open-drain; | ||
| 49 | vin-supply = <&vdd_5v0_reg>; | ||
| 50 | }; | ||
| 51 | |||
| 52 | usb3_vbus_reg: regulator@103 { | ||
| 53 | compatible = "regulator-fixed"; | ||
| 54 | reg = <103>; | ||
| 55 | regulator-name = "usb3_vbus"; | ||
| 56 | regulator-min-microvolt = <5000000>; | ||
| 57 | regulator-max-microvolt = <5000000>; | ||
| 58 | enable-active-high; | ||
| 59 | gpio = <&gpio 236 0>; /* GPIO PDD4 */ | ||
| 60 | gpio-open-drain; | ||
| 61 | vin-supply = <&vdd_5v0_reg>; | ||
| 62 | }; | ||
| 63 | |||
| 64 | vdd_5v0_reg: regulator@104 { | ||
| 65 | compatible = "regulator-fixed"; | ||
| 66 | reg = <104>; | ||
| 67 | regulator-name = "5v0"; | ||
| 68 | regulator-min-microvolt = <5000000>; | ||
| 69 | regulator-max-microvolt = <5000000>; | ||
| 70 | enable-active-high; | ||
| 71 | gpio = <&pmic 8 0>; | ||
| 72 | }; | ||
| 73 | |||
| 74 | vdd_bl_reg: regulator@105 { | ||
| 75 | compatible = "regulator-fixed"; | ||
| 76 | reg = <105>; | ||
| 77 | regulator-name = "vdd_bl"; | ||
| 78 | regulator-min-microvolt = <5000000>; | ||
| 79 | regulator-max-microvolt = <5000000>; | ||
| 80 | regulator-always-on; | ||
| 81 | regulator-boot-on; | ||
| 82 | enable-active-high; | ||
| 83 | gpio = <&gpio 234 0>; /* GPIO PDD2 */ | ||
| 84 | }; | ||
| 85 | |||
| 86 | vdd_bl2_reg: regulator@106 { | ||
| 87 | compatible = "regulator-fixed"; | ||
| 88 | reg = <106>; | ||
| 89 | regulator-name = "vdd_bl2"; | ||
| 90 | regulator-min-microvolt = <5000000>; | ||
| 91 | regulator-max-microvolt = <5000000>; | ||
| 92 | regulator-always-on; | ||
| 93 | regulator-boot-on; | ||
| 94 | enable-active-high; | ||
| 95 | gpio = <&gpio 232 0>; /* GPIO PDD0 */ | ||
| 96 | }; | ||
| 97 | }; | ||
| 98 | }; | ||
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dts b/arch/arm/boot/dts/tegra30-cardhu.dts deleted file mode 100644 index c169bced131e..000000000000 --- a/arch/arm/boot/dts/tegra30-cardhu.dts +++ /dev/null | |||
| @@ -1,171 +0,0 @@ | |||
| 1 | /dts-v1/; | ||
| 2 | |||
| 3 | /include/ "tegra30.dtsi" | ||
| 4 | |||
| 5 | / { | ||
| 6 | model = "NVIDIA Tegra30 Cardhu evaluation board"; | ||
| 7 | compatible = "nvidia,cardhu", "nvidia,tegra30"; | ||
| 8 | |||
| 9 | memory { | ||
| 10 | reg = <0x80000000 0x40000000>; | ||
| 11 | }; | ||
| 12 | |||
| 13 | pinmux { | ||
| 14 | pinctrl-names = "default"; | ||
| 15 | pinctrl-0 = <&state_default>; | ||
| 16 | |||
| 17 | state_default: pinmux { | ||
| 18 | sdmmc1_clk_pz0 { | ||
| 19 | nvidia,pins = "sdmmc1_clk_pz0"; | ||
| 20 | nvidia,function = "sdmmc1"; | ||
| 21 | nvidia,pull = <0>; | ||
| 22 | nvidia,tristate = <0>; | ||
| 23 | }; | ||
| 24 | sdmmc1_cmd_pz1 { | ||
| 25 | nvidia,pins = "sdmmc1_cmd_pz1", | ||
| 26 | "sdmmc1_dat0_py7", | ||
| 27 | "sdmmc1_dat1_py6", | ||
| 28 | "sdmmc1_dat2_py5", | ||
| 29 | "sdmmc1_dat3_py4"; | ||
| 30 | nvidia,function = "sdmmc1"; | ||
| 31 | nvidia,pull = <2>; | ||
| 32 | nvidia,tristate = <0>; | ||
| 33 | }; | ||
| 34 | sdmmc4_clk_pcc4 { | ||
| 35 | nvidia,pins = "sdmmc4_clk_pcc4", | ||
| 36 | "sdmmc4_rst_n_pcc3"; | ||
| 37 | nvidia,function = "sdmmc4"; | ||
| 38 | nvidia,pull = <0>; | ||
| 39 | nvidia,tristate = <0>; | ||
| 40 | }; | ||
| 41 | sdmmc4_dat0_paa0 { | ||
| 42 | nvidia,pins = "sdmmc4_dat0_paa0", | ||
| 43 | "sdmmc4_dat1_paa1", | ||
| 44 | "sdmmc4_dat2_paa2", | ||
| 45 | "sdmmc4_dat3_paa3", | ||
| 46 | "sdmmc4_dat4_paa4", | ||
| 47 | "sdmmc4_dat5_paa5", | ||
| 48 | "sdmmc4_dat6_paa6", | ||
| 49 | "sdmmc4_dat7_paa7"; | ||
| 50 | nvidia,function = "sdmmc4"; | ||
| 51 | nvidia,pull = <2>; | ||
| 52 | nvidia,tristate = <0>; | ||
| 53 | }; | ||
| 54 | dap2_fs_pa2 { | ||
| 55 | nvidia,pins = "dap2_fs_pa2", | ||
| 56 | "dap2_sclk_pa3", | ||
| 57 | "dap2_din_pa4", | ||
| 58 | "dap2_dout_pa5"; | ||
| 59 | nvidia,function = "i2s1"; | ||
| 60 | nvidia,pull = <0>; | ||
| 61 | nvidia,tristate = <0>; | ||
| 62 | }; | ||
| 63 | }; | ||
| 64 | }; | ||
| 65 | |||
| 66 | serial@70006000 { | ||
| 67 | status = "okay"; | ||
| 68 | clock-frequency = <408000000>; | ||
| 69 | }; | ||
| 70 | |||
| 71 | i2c@7000c000 { | ||
| 72 | status = "okay"; | ||
| 73 | clock-frequency = <100000>; | ||
| 74 | }; | ||
| 75 | |||
| 76 | i2c@7000c400 { | ||
| 77 | status = "okay"; | ||
| 78 | clock-frequency = <100000>; | ||
| 79 | }; | ||
| 80 | |||
| 81 | i2c@7000c500 { | ||
| 82 | status = "okay"; | ||
| 83 | clock-frequency = <100000>; | ||
| 84 | |||
| 85 | /* ALS and Proximity sensor */ | ||
| 86 | isl29028@44 { | ||
| 87 | compatible = "isil,isl29028"; | ||
| 88 | reg = <0x44>; | ||
| 89 | interrupt-parent = <&gpio>; | ||
| 90 | interrupts = <88 0x04>; /*gpio PL0 */ | ||
| 91 | }; | ||
| 92 | }; | ||
| 93 | |||
| 94 | i2c@7000c700 { | ||
| 95 | status = "okay"; | ||
| 96 | clock-frequency = <100000>; | ||
| 97 | }; | ||
| 98 | |||
| 99 | i2c@7000d000 { | ||
| 100 | status = "okay"; | ||
| 101 | clock-frequency = <100000>; | ||
| 102 | |||
| 103 | wm8903: wm8903@1a { | ||
| 104 | compatible = "wlf,wm8903"; | ||
| 105 | reg = <0x1a>; | ||
| 106 | interrupt-parent = <&gpio>; | ||
| 107 | interrupts = <179 0x04>; /* gpio PW3 */ | ||
| 108 | |||
| 109 | gpio-controller; | ||
| 110 | #gpio-cells = <2>; | ||
| 111 | |||
| 112 | micdet-cfg = <0>; | ||
| 113 | micdet-delay = <100>; | ||
| 114 | gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>; | ||
| 115 | }; | ||
| 116 | |||
| 117 | tps62361 { | ||
| 118 | compatible = "ti,tps62361"; | ||
| 119 | reg = <0x60>; | ||
| 120 | |||
| 121 | regulator-name = "tps62361-vout"; | ||
| 122 | regulator-min-microvolt = <500000>; | ||
| 123 | regulator-max-microvolt = <1500000>; | ||
| 124 | regulator-boot-on; | ||
| 125 | regulator-always-on; | ||
| 126 | ti,vsel0-state-high; | ||
| 127 | ti,vsel1-state-high; | ||
| 128 | }; | ||
| 129 | }; | ||
| 130 | |||
| 131 | ahub { | ||
| 132 | i2s@70080400 { | ||
| 133 | status = "okay"; | ||
| 134 | }; | ||
| 135 | }; | ||
| 136 | |||
| 137 | sdhci@78000000 { | ||
| 138 | status = "okay"; | ||
| 139 | cd-gpios = <&gpio 69 0>; /* gpio PI5 */ | ||
| 140 | wp-gpios = <&gpio 155 0>; /* gpio PT3 */ | ||
| 141 | power-gpios = <&gpio 31 0>; /* gpio PD7 */ | ||
| 142 | bus-width = <4>; | ||
| 143 | }; | ||
| 144 | |||
| 145 | sdhci@78000600 { | ||
| 146 | status = "okay"; | ||
| 147 | bus-width = <8>; | ||
| 148 | }; | ||
| 149 | |||
| 150 | sound { | ||
| 151 | compatible = "nvidia,tegra-audio-wm8903-cardhu", | ||
| 152 | "nvidia,tegra-audio-wm8903"; | ||
| 153 | nvidia,model = "NVIDIA Tegra Cardhu"; | ||
| 154 | |||
| 155 | nvidia,audio-routing = | ||
| 156 | "Headphone Jack", "HPOUTR", | ||
| 157 | "Headphone Jack", "HPOUTL", | ||
| 158 | "Int Spk", "ROP", | ||
| 159 | "Int Spk", "RON", | ||
| 160 | "Int Spk", "LOP", | ||
| 161 | "Int Spk", "LON", | ||
| 162 | "Mic Jack", "MICBIAS", | ||
| 163 | "IN1L", "Mic Jack"; | ||
| 164 | |||
| 165 | nvidia,i2s-controller = <&tegra_i2s1>; | ||
| 166 | nvidia,audio-codec = <&wm8903>; | ||
| 167 | |||
| 168 | nvidia,spkr-en-gpios = <&wm8903 2 0>; | ||
| 169 | nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ | ||
| 170 | }; | ||
| 171 | }; | ||
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi new file mode 100644 index 000000000000..d10c9c5a3606 --- /dev/null +++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi | |||
| @@ -0,0 +1,475 @@ | |||
| 1 | /include/ "tegra30.dtsi" | ||
| 2 | |||
| 3 | /** | ||
| 4 | * This file contains common DT entry for all fab version of Cardhu. | ||
| 5 | * There is multiple fab version of Cardhu starting from A01 to A07. | ||
| 6 | * Cardhu fab version A01 and A03 are not supported. Cardhu fab version | ||
| 7 | * A02 will have different sets of GPIOs for fixed regulator compare to | ||
| 8 | * Cardhu fab version A04. The Cardhu fab version A05, A06, A07 are | ||
| 9 | * compatible with fab version A04. Based on Cardhu fab version, the | ||
| 10 | * related dts file need to be chosen like for Cardhu fab version A02, | ||
| 11 | * use tegra30-cardhu-a02.dts, Cardhu fab version A04 and later, use | ||
| 12 | * tegra30-cardhu-a04.dts. | ||
| 13 | * The identification of board is done in two ways, by looking the sticker | ||
| 14 | * on PCB and by reading board id eeprom. | ||
| 15 | * The stciker will have number like 600-81291-1000-002 C.3. In this 4th | ||
| 16 | * number is the fab version like here it is 002 and hence fab version A02. | ||
| 17 | * The (downstream internal) U-Boot of Cardhu display the board-id as | ||
| 18 | * follows: | ||
| 19 | * BoardID: 0C5B, SKU: 0A01, Fab: 02, Rev: 45.00 | ||
| 20 | * In this Fab version is 02 i.e. A02. | ||
| 21 | * The BoardID I2C eeprom is interfaced through i2c5 (pwr_i2c address 0x56). | ||
| 22 | * The location 0x8 of this eeprom contains the Fab version. It is 1 byte | ||
| 23 | * wide. | ||
| 24 | */ | ||
| 25 | |||
| 26 | / { | ||
| 27 | model = "NVIDIA Tegra30 Cardhu evaluation board"; | ||
| 28 | compatible = "nvidia,cardhu", "nvidia,tegra30"; | ||
| 29 | |||
| 30 | memory { | ||
| 31 | reg = <0x80000000 0x40000000>; | ||
| 32 | }; | ||
| 33 | |||
| 34 | pinmux { | ||
| 35 | pinctrl-names = "default"; | ||
| 36 | pinctrl-0 = <&state_default>; | ||
| 37 | |||
| 38 | state_default: pinmux { | ||
| 39 | sdmmc1_clk_pz0 { | ||
| 40 | nvidia,pins = "sdmmc1_clk_pz0"; | ||
| 41 | nvidia,function = "sdmmc1"; | ||
| 42 | nvidia,pull = <0>; | ||
| 43 | nvidia,tristate = <0>; | ||
| 44 | }; | ||
| 45 | sdmmc1_cmd_pz1 { | ||
| 46 | nvidia,pins = "sdmmc1_cmd_pz1", | ||
| 47 | "sdmmc1_dat0_py7", | ||
| 48 | "sdmmc1_dat1_py6", | ||
| 49 | "sdmmc1_dat2_py5", | ||
| 50 | "sdmmc1_dat3_py4"; | ||
| 51 | nvidia,function = "sdmmc1"; | ||
| 52 | nvidia,pull = <2>; | ||
| 53 | nvidia,tristate = <0>; | ||
| 54 | }; | ||
| 55 | sdmmc4_clk_pcc4 { | ||
| 56 | nvidia,pins = "sdmmc4_clk_pcc4", | ||
| 57 | "sdmmc4_rst_n_pcc3"; | ||
| 58 | nvidia,function = "sdmmc4"; | ||
| 59 | nvidia,pull = <0>; | ||
| 60 | nvidia,tristate = <0>; | ||
| 61 | }; | ||
| 62 | sdmmc4_dat0_paa0 { | ||
| 63 | nvidia,pins = "sdmmc4_dat0_paa0", | ||
| 64 | "sdmmc4_dat1_paa1", | ||
| 65 | "sdmmc4_dat2_paa2", | ||
| 66 | "sdmmc4_dat3_paa3", | ||
| 67 | "sdmmc4_dat4_paa4", | ||
| 68 | "sdmmc4_dat5_paa5", | ||
| 69 | "sdmmc4_dat6_paa6", | ||
| 70 | "sdmmc4_dat7_paa7"; | ||
| 71 | nvidia,function = "sdmmc4"; | ||
| 72 | nvidia,pull = <2>; | ||
| 73 | nvidia,tristate = <0>; | ||
| 74 | }; | ||
| 75 | dap2_fs_pa2 { | ||
| 76 | nvidia,pins = "dap2_fs_pa2", | ||
| 77 | "dap2_sclk_pa3", | ||
| 78 | "dap2_din_pa4", | ||
| 79 | "dap2_dout_pa5"; | ||
| 80 | nvidia,function = "i2s1"; | ||
| 81 | nvidia,pull = <0>; | ||
| 82 | nvidia,tristate = <0>; | ||
| 83 | }; | ||
| 84 | }; | ||
| 85 | }; | ||
| 86 | |||
| 87 | serial@70006000 { | ||
| 88 | status = "okay"; | ||
| 89 | clock-frequency = <408000000>; | ||
| 90 | }; | ||
| 91 | |||
| 92 | i2c@7000c000 { | ||
| 93 | status = "okay"; | ||
| 94 | clock-frequency = <100000>; | ||
| 95 | }; | ||
| 96 | |||
| 97 | i2c@7000c400 { | ||
| 98 | status = "okay"; | ||
| 99 | clock-frequency = <100000>; | ||
| 100 | }; | ||
| 101 | |||
| 102 | i2c@7000c500 { | ||
| 103 | status = "okay"; | ||
| 104 | clock-frequency = <100000>; | ||
| 105 | |||
| 106 | /* ALS and Proximity sensor */ | ||
| 107 | isl29028@44 { | ||
| 108 | compatible = "isil,isl29028"; | ||
| 109 | reg = <0x44>; | ||
| 110 | interrupt-parent = <&gpio>; | ||
| 111 | interrupts = <88 0x04>; /*gpio PL0 */ | ||
| 112 | }; | ||
| 113 | }; | ||
| 114 | |||
| 115 | i2c@7000c700 { | ||
| 116 | status = "okay"; | ||
| 117 | clock-frequency = <100000>; | ||
| 118 | }; | ||
| 119 | |||
| 120 | i2c@7000d000 { | ||
| 121 | status = "okay"; | ||
| 122 | clock-frequency = <100000>; | ||
| 123 | |||
| 124 | wm8903: wm8903@1a { | ||
| 125 | compatible = "wlf,wm8903"; | ||
| 126 | reg = <0x1a>; | ||
| 127 | interrupt-parent = <&gpio>; | ||
| 128 | interrupts = <179 0x04>; /* gpio PW3 */ | ||
| 129 | |||
| 130 | gpio-controller; | ||
| 131 | #gpio-cells = <2>; | ||
| 132 | |||
| 133 | micdet-cfg = <0>; | ||
| 134 | micdet-delay = <100>; | ||
| 135 | gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>; | ||
| 136 | }; | ||
| 137 | |||
| 138 | tps62361 { | ||
| 139 | compatible = "ti,tps62361"; | ||
| 140 | reg = <0x60>; | ||
| 141 | |||
| 142 | regulator-name = "tps62361-vout"; | ||
| 143 | regulator-min-microvolt = <500000>; | ||
| 144 | regulator-max-microvolt = <1500000>; | ||
| 145 | regulator-boot-on; | ||
| 146 | regulator-always-on; | ||
| 147 | ti,vsel0-state-high; | ||
| 148 | ti,vsel1-state-high; | ||
| 149 | }; | ||
| 150 | |||
| 151 | pmic: tps65911@2d { | ||
| 152 | compatible = "ti,tps65911"; | ||
| 153 | reg = <0x2d>; | ||
| 154 | |||
| 155 | interrupts = <0 86 0x4>; | ||
| 156 | #interrupt-cells = <2>; | ||
| 157 | interrupt-controller; | ||
| 158 | |||
| 159 | ti,system-power-controller; | ||
| 160 | |||
| 161 | #gpio-cells = <2>; | ||
| 162 | gpio-controller; | ||
| 163 | |||
| 164 | vcc1-supply = <&vdd_ac_bat_reg>; | ||
| 165 | vcc2-supply = <&vdd_ac_bat_reg>; | ||
| 166 | vcc3-supply = <&vio_reg>; | ||
| 167 | vcc4-supply = <&vdd_5v0_reg>; | ||
| 168 | vcc5-supply = <&vdd_ac_bat_reg>; | ||
| 169 | vcc6-supply = <&vdd2_reg>; | ||
| 170 | vcc7-supply = <&vdd_ac_bat_reg>; | ||
| 171 | vccio-supply = <&vdd_ac_bat_reg>; | ||
| 172 | |||
| 173 | regulators { | ||
| 174 | #address-cells = <1>; | ||
| 175 | #size-cells = <0>; | ||
| 176 | |||
| 177 | vdd1_reg: regulator@0 { | ||
| 178 | reg = <0>; | ||
| 179 | regulator-compatible = "vdd1"; | ||
| 180 | regulator-name = "vddio_ddr_1v2"; | ||
| 181 | regulator-min-microvolt = <1200000>; | ||
| 182 | regulator-max-microvolt = <1200000>; | ||
| 183 | regulator-always-on; | ||
| 184 | }; | ||
| 185 | |||
| 186 | vdd2_reg: regulator@1 { | ||
| 187 | reg = <1>; | ||
| 188 | regulator-compatible = "vdd2"; | ||
| 189 | regulator-name = "vdd_1v5_gen"; | ||
| 190 | regulator-min-microvolt = <1500000>; | ||
| 191 | regulator-max-microvolt = <1500000>; | ||
| 192 | regulator-always-on; | ||
| 193 | }; | ||
| 194 | |||
| 195 | vddctrl_reg: regulator@2 { | ||
| 196 | reg = <2>; | ||
| 197 | regulator-compatible = "vddctrl"; | ||
| 198 | regulator-name = "vdd_cpu,vdd_sys"; | ||
| 199 | regulator-min-microvolt = <1000000>; | ||
| 200 | regulator-max-microvolt = <1000000>; | ||
| 201 | regulator-always-on; | ||
| 202 | }; | ||
| 203 | |||
| 204 | vio_reg: regulator@3 { | ||
| 205 | reg = <3>; | ||
| 206 | regulator-compatible = "vio"; | ||
| 207 | regulator-name = "vdd_1v8_gen"; | ||
| 208 | regulator-min-microvolt = <1800000>; | ||
| 209 | regulator-max-microvolt = <1800000>; | ||
| 210 | regulator-always-on; | ||
| 211 | }; | ||
| 212 | |||
| 213 | ldo1_reg: regulator@4 { | ||
| 214 | reg = <4>; | ||
| 215 | regulator-compatible = "ldo1"; | ||
| 216 | regulator-name = "vdd_pexa,vdd_pexb"; | ||
| 217 | regulator-min-microvolt = <1050000>; | ||
| 218 | regulator-max-microvolt = <1050000>; | ||
| 219 | }; | ||
| 220 | |||
| 221 | ldo2_reg: regulator@5 { | ||
| 222 | reg = <5>; | ||
| 223 | regulator-compatible = "ldo2"; | ||
| 224 | regulator-name = "vdd_sata,avdd_plle"; | ||
| 225 | regulator-min-microvolt = <1050000>; | ||
| 226 | regulator-max-microvolt = <1050000>; | ||
| 227 | }; | ||
| 228 | |||
| 229 | /* LDO3 is not connected to anything */ | ||
| 230 | |||
| 231 | ldo4_reg: regulator@7 { | ||
| 232 | reg = <7>; | ||
| 233 | regulator-compatible = "ldo4"; | ||
| 234 | regulator-name = "vdd_rtc"; | ||
| 235 | regulator-min-microvolt = <1200000>; | ||
| 236 | regulator-max-microvolt = <1200000>; | ||
| 237 | regulator-always-on; | ||
| 238 | }; | ||
| 239 | |||
| 240 | ldo5_reg: regulator@8 { | ||
| 241 | reg = <8>; | ||
| 242 | regulator-compatible = "ldo5"; | ||
| 243 | regulator-name = "vddio_sdmmc,avdd_vdac"; | ||
| 244 | regulator-min-microvolt = <3300000>; | ||
| 245 | regulator-max-microvolt = <3300000>; | ||
| 246 | regulator-always-on; | ||
| 247 | }; | ||
| 248 | |||
| 249 | ldo6_reg: regulator@9 { | ||
| 250 | reg = <9>; | ||
| 251 | regulator-compatible = "ldo6"; | ||
| 252 | regulator-name = "avdd_dsi_csi,pwrdet_mipi"; | ||
| 253 | regulator-min-microvolt = <1200000>; | ||
| 254 | regulator-max-microvolt = <1200000>; | ||
| 255 | }; | ||
| 256 | |||
| 257 | ldo7_reg: regulator@10 { | ||
| 258 | reg = <10>; | ||
| 259 | regulator-compatible = "ldo7"; | ||
| 260 | regulator-name = "vdd_pllm,x,u,a_p_c_s"; | ||
| 261 | regulator-min-microvolt = <1200000>; | ||
| 262 | regulator-max-microvolt = <1200000>; | ||
| 263 | regulator-always-on; | ||
| 264 | }; | ||
| 265 | |||
| 266 | ldo8_reg: regulator@11 { | ||
| 267 | reg = <11>; | ||
| 268 | regulator-compatible = "ldo8"; | ||
| 269 | regulator-name = "vdd_ddr_hs"; | ||
| 270 | regulator-min-microvolt = <1000000>; | ||
| 271 | regulator-max-microvolt = <1000000>; | ||
| 272 | regulator-always-on; | ||
| 273 | }; | ||
| 274 | }; | ||
| 275 | }; | ||
| 276 | }; | ||
| 277 | |||
| 278 | ahub { | ||
| 279 | i2s@70080400 { | ||
| 280 | status = "okay"; | ||
| 281 | }; | ||
| 282 | }; | ||
| 283 | |||
| 284 | pmc { | ||
| 285 | status = "okay"; | ||
| 286 | nvidia,invert-interrupt; | ||
| 287 | }; | ||
| 288 | |||
| 289 | sdhci@78000000 { | ||
| 290 | status = "okay"; | ||
| 291 | cd-gpios = <&gpio 69 0>; /* gpio PI5 */ | ||
| 292 | wp-gpios = <&gpio 155 0>; /* gpio PT3 */ | ||
| 293 | power-gpios = <&gpio 31 0>; /* gpio PD7 */ | ||
| 294 | bus-width = <4>; | ||
| 295 | }; | ||
| 296 | |||
| 297 | sdhci@78000600 { | ||
| 298 | status = "okay"; | ||
| 299 | bus-width = <8>; | ||
| 300 | }; | ||
| 301 | |||
| 302 | regulators { | ||
| 303 | compatible = "simple-bus"; | ||
| 304 | #address-cells = <1>; | ||
| 305 | #size-cells = <0>; | ||
| 306 | |||
| 307 | vdd_ac_bat_reg: regulator@0 { | ||
| 308 | compatible = "regulator-fixed"; | ||
| 309 | reg = <0>; | ||
| 310 | regulator-name = "vdd_ac_bat"; | ||
| 311 | regulator-min-microvolt = <5000000>; | ||
| 312 | regulator-max-microvolt = <5000000>; | ||
| 313 | regulator-always-on; | ||
| 314 | }; | ||
| 315 | |||
| 316 | cam_1v8_reg: regulator@1 { | ||
| 317 | compatible = "regulator-fixed"; | ||
| 318 | reg = <1>; | ||
| 319 | regulator-name = "cam_1v8"; | ||
| 320 | regulator-min-microvolt = <1800000>; | ||
| 321 | regulator-max-microvolt = <1800000>; | ||
| 322 | enable-active-high; | ||
| 323 | gpio = <&gpio 220 0>; /* gpio PBB4 */ | ||
| 324 | vin-supply = <&vio_reg>; | ||
| 325 | }; | ||
| 326 | |||
| 327 | cp_5v_reg: regulator@2 { | ||
| 328 | compatible = "regulator-fixed"; | ||
| 329 | reg = <2>; | ||
| 330 | regulator-name = "cp_5v"; | ||
| 331 | regulator-min-microvolt = <5000000>; | ||
| 332 | regulator-max-microvolt = <5000000>; | ||
| 333 | regulator-boot-on; | ||
| 334 | regulator-always-on; | ||
| 335 | enable-active-high; | ||
| 336 | gpio = <&pmic 0 0>; /* PMIC TPS65911 GPIO0 */ | ||
| 337 | }; | ||
| 338 | |||
| 339 | emmc_3v3_reg: regulator@3 { | ||
| 340 | compatible = "regulator-fixed"; | ||
| 341 | reg = <3>; | ||
| 342 | regulator-name = "emmc_3v3"; | ||
| 343 | regulator-min-microvolt = <3300000>; | ||
| 344 | regulator-max-microvolt = <3300000>; | ||
| 345 | regulator-always-on; | ||
| 346 | regulator-boot-on; | ||
| 347 | enable-active-high; | ||
| 348 | gpio = <&gpio 25 0>; /* gpio PD1 */ | ||
| 349 | vin-supply = <&sys_3v3_reg>; | ||
| 350 | }; | ||
| 351 | |||
| 352 | modem_3v3_reg: regulator@4 { | ||
| 353 | compatible = "regulator-fixed"; | ||
| 354 | reg = <4>; | ||
| 355 | regulator-name = "modem_3v3"; | ||
| 356 | regulator-min-microvolt = <3300000>; | ||
| 357 | regulator-max-microvolt = <3300000>; | ||
| 358 | enable-active-high; | ||
| 359 | gpio = <&gpio 30 0>; /* gpio PD6 */ | ||
| 360 | }; | ||
| 361 | |||
| 362 | pex_hvdd_3v3_reg: regulator@5 { | ||
| 363 | compatible = "regulator-fixed"; | ||
| 364 | reg = <5>; | ||
| 365 | regulator-name = "pex_hvdd_3v3"; | ||
| 366 | regulator-min-microvolt = <3300000>; | ||
| 367 | regulator-max-microvolt = <3300000>; | ||
| 368 | enable-active-high; | ||
| 369 | gpio = <&gpio 95 0>; /* gpio PL7 */ | ||
| 370 | vin-supply = <&sys_3v3_reg>; | ||
| 371 | }; | ||
| 372 | |||
| 373 | vdd_cam1_ldo_reg: regulator@6 { | ||
| 374 | compatible = "regulator-fixed"; | ||
| 375 | reg = <6>; | ||
| 376 | regulator-name = "vdd_cam1_ldo"; | ||
| 377 | regulator-min-microvolt = <2800000>; | ||
| 378 | regulator-max-microvolt = <2800000>; | ||
| 379 | enable-active-high; | ||
| 380 | gpio = <&gpio 142 0>; /* gpio PR6 */ | ||
| 381 | vin-supply = <&sys_3v3_reg>; | ||
| 382 | }; | ||
| 383 | |||
| 384 | vdd_cam2_ldo_reg: regulator@7 { | ||
| 385 | compatible = "regulator-fixed"; | ||
| 386 | reg = <7>; | ||
| 387 | regulator-name = "vdd_cam2_ldo"; | ||
| 388 | regulator-min-microvolt = <2800000>; | ||
| 389 | regulator-max-microvolt = <2800000>; | ||
| 390 | enable-active-high; | ||
| 391 | gpio = <&gpio 143 0>; /* gpio PR7 */ | ||
| 392 | vin-supply = <&sys_3v3_reg>; | ||
| 393 | }; | ||
| 394 | |||
| 395 | vdd_cam3_ldo_reg: regulator@8 { | ||
| 396 | compatible = "regulator-fixed"; | ||
| 397 | reg = <8>; | ||
| 398 | regulator-name = "vdd_cam3_ldo"; | ||
| 399 | regulator-min-microvolt = <3300000>; | ||
| 400 | regulator-max-microvolt = <3300000>; | ||
| 401 | enable-active-high; | ||
| 402 | gpio = <&gpio 144 0>; /* gpio PS0 */ | ||
| 403 | vin-supply = <&sys_3v3_reg>; | ||
| 404 | }; | ||
| 405 | |||
| 406 | vdd_com_reg: regulator@9 { | ||
| 407 | compatible = "regulator-fixed"; | ||
| 408 | reg = <9>; | ||
| 409 | regulator-name = "vdd_com"; | ||
| 410 | regulator-min-microvolt = <3300000>; | ||
| 411 | regulator-max-microvolt = <3300000>; | ||
| 412 | enable-active-high; | ||
| 413 | gpio = <&gpio 24 0>; /* gpio PD0 */ | ||
| 414 | vin-supply = <&sys_3v3_reg>; | ||
| 415 | }; | ||
| 416 | |||
| 417 | vdd_fuse_3v3_reg: regulator@10 { | ||
| 418 | compatible = "regulator-fixed"; | ||
| 419 | reg = <10>; | ||
| 420 | regulator-name = "vdd_fuse_3v3"; | ||
| 421 | regulator-min-microvolt = <3300000>; | ||
| 422 | regulator-max-microvolt = <3300000>; | ||
| 423 | enable-active-high; | ||
| 424 | gpio = <&gpio 94 0>; /* gpio PL6 */ | ||
| 425 | vin-supply = <&sys_3v3_reg>; | ||
| 426 | }; | ||
| 427 | |||
| 428 | vdd_pnl1_reg: regulator@11 { | ||
| 429 | compatible = "regulator-fixed"; | ||
| 430 | reg = <11>; | ||
| 431 | regulator-name = "vdd_pnl1"; | ||
| 432 | regulator-min-microvolt = <3300000>; | ||
| 433 | regulator-max-microvolt = <3300000>; | ||
| 434 | regulator-always-on; | ||
| 435 | regulator-boot-on; | ||
| 436 | enable-active-high; | ||
| 437 | gpio = <&gpio 92 0>; /* gpio PL4 */ | ||
| 438 | vin-supply = <&sys_3v3_reg>; | ||
| 439 | }; | ||
| 440 | |||
| 441 | vdd_vid_reg: regulator@12 { | ||
| 442 | compatible = "regulator-fixed"; | ||
| 443 | reg = <12>; | ||
| 444 | regulator-name = "vddio_vid"; | ||
| 445 | regulator-min-microvolt = <5000000>; | ||
| 446 | regulator-max-microvolt = <5000000>; | ||
| 447 | enable-active-high; | ||
| 448 | gpio = <&gpio 152 0>; /* GPIO PT0 */ | ||
| 449 | gpio-open-drain; | ||
| 450 | vin-supply = <&vdd_5v0_reg>; | ||
| 451 | }; | ||
| 452 | }; | ||
| 453 | |||
| 454 | sound { | ||
| 455 | compatible = "nvidia,tegra-audio-wm8903-cardhu", | ||
| 456 | "nvidia,tegra-audio-wm8903"; | ||
| 457 | nvidia,model = "NVIDIA Tegra Cardhu"; | ||
| 458 | |||
| 459 | nvidia,audio-routing = | ||
| 460 | "Headphone Jack", "HPOUTR", | ||
| 461 | "Headphone Jack", "HPOUTL", | ||
| 462 | "Int Spk", "ROP", | ||
| 463 | "Int Spk", "RON", | ||
| 464 | "Int Spk", "LOP", | ||
| 465 | "Int Spk", "LON", | ||
| 466 | "Mic Jack", "MICBIAS", | ||
| 467 | "IN1L", "Mic Jack"; | ||
| 468 | |||
| 469 | nvidia,i2s-controller = <&tegra_i2s1>; | ||
| 470 | nvidia,audio-codec = <&wm8903>; | ||
| 471 | |||
| 472 | nvidia,spkr-en-gpios = <&wm8903 2 0>; | ||
| 473 | nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ | ||
| 474 | }; | ||
| 475 | }; | ||
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 3e4334d14efb..b1497c7d7d68 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi | |||
| @@ -117,7 +117,7 @@ | |||
| 117 | status = "disabled"; | 117 | status = "disabled"; |
| 118 | }; | 118 | }; |
| 119 | 119 | ||
| 120 | pwm { | 120 | pwm: pwm { |
| 121 | compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm"; | 121 | compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm"; |
| 122 | reg = <0x7000a000 0x100>; | 122 | reg = <0x7000a000 0x100>; |
| 123 | #pwm-cells = <2>; | 123 | #pwm-cells = <2>; |
diff --git a/arch/arm/boot/dts/tps65217.dtsi b/arch/arm/boot/dts/tps65217.dtsi new file mode 100644 index 000000000000..a63272422d76 --- /dev/null +++ b/arch/arm/boot/dts/tps65217.dtsi | |||
| @@ -0,0 +1,56 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | */ | ||
| 8 | |||
| 9 | /* | ||
| 10 | * Integrated Power Management Chip | ||
| 11 | * http://www.ti.com/lit/ds/symlink/tps65217.pdf | ||
| 12 | */ | ||
| 13 | |||
| 14 | &tps { | ||
| 15 | compatible = "ti,tps65217"; | ||
| 16 | |||
| 17 | regulators { | ||
| 18 | #address-cells = <1>; | ||
| 19 | #size-cells = <0>; | ||
| 20 | |||
| 21 | dcdc1_reg: regulator@0 { | ||
| 22 | reg = <0>; | ||
| 23 | regulator-compatible = "dcdc1"; | ||
| 24 | }; | ||
| 25 | |||
| 26 | dcdc2_reg: regulator@1 { | ||
| 27 | reg = <1>; | ||
| 28 | regulator-compatible = "dcdc2"; | ||
| 29 | }; | ||
| 30 | |||
| 31 | dcdc3_reg: regulator@2 { | ||
| 32 | reg = <2>; | ||
| 33 | regulator-compatible = "dcdc3"; | ||
| 34 | }; | ||
| 35 | |||
| 36 | ldo1_reg: regulator@3 { | ||
| 37 | reg = <3>; | ||
| 38 | regulator-compatible = "ldo1"; | ||
| 39 | }; | ||
| 40 | |||
| 41 | ldo2_reg: regulator@4 { | ||
| 42 | reg = <4>; | ||
| 43 | regulator-compatible = "ldo2"; | ||
| 44 | }; | ||
| 45 | |||
| 46 | ldo3_reg: regulator@5 { | ||
| 47 | reg = <5>; | ||
| 48 | regulator-compatible = "ldo3"; | ||
| 49 | }; | ||
| 50 | |||
| 51 | ldo4_reg: regulator@6 { | ||
| 52 | reg = <6>; | ||
| 53 | regulator-compatible = "ldo4"; | ||
| 54 | }; | ||
| 55 | }; | ||
| 56 | }; | ||
diff --git a/arch/arm/boot/dts/tps65910.dtsi b/arch/arm/boot/dts/tps65910.dtsi new file mode 100644 index 000000000000..92693a89160e --- /dev/null +++ b/arch/arm/boot/dts/tps65910.dtsi | |||
| @@ -0,0 +1,86 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | */ | ||
| 8 | |||
| 9 | /* | ||
| 10 | * Integrated Power Management Chip | ||
| 11 | * http://www.ti.com/lit/ds/symlink/tps65910.pdf | ||
| 12 | */ | ||
| 13 | |||
| 14 | &tps { | ||
| 15 | compatible = "ti,tps65910"; | ||
| 16 | |||
| 17 | regulators { | ||
| 18 | #address-cells = <1>; | ||
| 19 | #size-cells = <0>; | ||
| 20 | |||
| 21 | vrtc_reg: regulator@0 { | ||
| 22 | reg = <0>; | ||
| 23 | regulator-compatible = "vrtc"; | ||
| 24 | }; | ||
| 25 | |||
| 26 | vio_reg: regulator@1 { | ||
| 27 | reg = <1>; | ||
| 28 | regulator-compatible = "vio"; | ||
| 29 | }; | ||
| 30 | |||
| 31 | vdd1_reg: regulator@2 { | ||
| 32 | reg = <2>; | ||
| 33 | regulator-compatible = "vdd1"; | ||
| 34 | }; | ||
| 35 | |||
| 36 | vdd2_reg: regulator@3 { | ||
| 37 | reg = <3>; | ||
| 38 | regulator-compatible = "vdd2"; | ||
| 39 | }; | ||
| 40 | |||
| 41 | vdd3_reg: regulator@4 { | ||
| 42 | reg = <4>; | ||
| 43 | regulator-compatible = "vdd3"; | ||
| 44 | }; | ||
| 45 | |||
| 46 | vdig1_reg: regulator@5 { | ||
| 47 | reg = <5>; | ||
| 48 | regulator-compatible = "vdig1"; | ||
| 49 | }; | ||
| 50 | |||
| 51 | vdig2_reg: regulator@6 { | ||
| 52 | reg = <6>; | ||
| 53 | regulator-compatible = "vdig2"; | ||
| 54 | }; | ||
| 55 | |||
| 56 | vpll_reg: regulator@7 { | ||
| 57 | reg = <7>; | ||
| 58 | regulator-compatible = "vpll"; | ||
| 59 | }; | ||
| 60 | |||
| 61 | vdac_reg: regulator@8 { | ||
| 62 | reg = <8>; | ||
| 63 | regulator-compatible = "vdac"; | ||
| 64 | }; | ||
| 65 | |||
| 66 | vaux1_reg: regulator@9 { | ||
| 67 | reg = <9>; | ||
| 68 | regulator-compatible = "vaux1"; | ||
| 69 | }; | ||
| 70 | |||
| 71 | vaux2_reg: regulator@10 { | ||
| 72 | reg = <10>; | ||
| 73 | regulator-compatible = "vaux2"; | ||
| 74 | }; | ||
| 75 | |||
| 76 | vaux33_reg: regulator@11 { | ||
| 77 | reg = <11>; | ||
| 78 | regulator-compatible = "vaux33"; | ||
| 79 | }; | ||
| 80 | |||
| 81 | vmmc_reg: regulator@12 { | ||
| 82 | reg = <12>; | ||
| 83 | regulator-compatible = "vmmc"; | ||
| 84 | }; | ||
| 85 | }; | ||
| 86 | }; | ||
diff --git a/arch/arm/boot/dts/twl4030.dtsi b/arch/arm/boot/dts/twl4030.dtsi index 22f4d1394ed3..ff000172c93c 100644 --- a/arch/arm/boot/dts/twl4030.dtsi +++ b/arch/arm/boot/dts/twl4030.dtsi | |||
| @@ -19,19 +19,19 @@ | |||
| 19 | interrupts = <11>; | 19 | interrupts = <11>; |
| 20 | }; | 20 | }; |
| 21 | 21 | ||
| 22 | vdac: regulator@0 { | 22 | vdac: regulator-vdac { |
| 23 | compatible = "ti,twl4030-vdac"; | 23 | compatible = "ti,twl4030-vdac"; |
| 24 | regulator-min-microvolt = <1800000>; | 24 | regulator-min-microvolt = <1800000>; |
| 25 | regulator-max-microvolt = <1800000>; | 25 | regulator-max-microvolt = <1800000>; |
| 26 | }; | 26 | }; |
| 27 | 27 | ||
| 28 | vpll2: regulator@1 { | 28 | vpll2: regulator-vpll2 { |
| 29 | compatible = "ti,twl4030-vpll2"; | 29 | compatible = "ti,twl4030-vpll2"; |
| 30 | regulator-min-microvolt = <1800000>; | 30 | regulator-min-microvolt = <1800000>; |
| 31 | regulator-max-microvolt = <1800000>; | 31 | regulator-max-microvolt = <1800000>; |
| 32 | }; | 32 | }; |
| 33 | 33 | ||
| 34 | vmmc1: regulator@2 { | 34 | vmmc1: regulator-vmmc1 { |
| 35 | compatible = "ti,twl4030-vmmc1"; | 35 | compatible = "ti,twl4030-vmmc1"; |
| 36 | regulator-min-microvolt = <1850000>; | 36 | regulator-min-microvolt = <1850000>; |
| 37 | regulator-max-microvolt = <3150000>; | 37 | regulator-max-microvolt = <3150000>; |
diff --git a/arch/arm/boot/dts/twl6030.dtsi b/arch/arm/boot/dts/twl6030.dtsi index d351b27d7213..123e2c40218a 100644 --- a/arch/arm/boot/dts/twl6030.dtsi +++ b/arch/arm/boot/dts/twl6030.dtsi | |||
| @@ -20,70 +20,70 @@ | |||
| 20 | interrupts = <11>; | 20 | interrupts = <11>; |
| 21 | }; | 21 | }; |
| 22 | 22 | ||
| 23 | vaux1: regulator@0 { | 23 | vaux1: regulator-vaux1 { |
| 24 | compatible = "ti,twl6030-vaux1"; | 24 | compatible = "ti,twl6030-vaux1"; |
| 25 | regulator-min-microvolt = <1000000>; | 25 | regulator-min-microvolt = <1000000>; |
| 26 | regulator-max-microvolt = <3000000>; | 26 | regulator-max-microvolt = <3000000>; |
| 27 | }; | 27 | }; |
| 28 | 28 | ||
| 29 | vaux2: regulator@1 { | 29 | vaux2: regulator-vaux2 { |
| 30 | compatible = "ti,twl6030-vaux2"; | 30 | compatible = "ti,twl6030-vaux2"; |
| 31 | regulator-min-microvolt = <1200000>; | 31 | regulator-min-microvolt = <1200000>; |
| 32 | regulator-max-microvolt = <2800000>; | 32 | regulator-max-microvolt = <2800000>; |
| 33 | }; | 33 | }; |
| 34 | 34 | ||
| 35 | vaux3: regulator@2 { | 35 | vaux3: regulator-vaux3 { |
| 36 | compatible = "ti,twl6030-vaux3"; | 36 | compatible = "ti,twl6030-vaux3"; |
| 37 | regulator-min-microvolt = <1000000>; | 37 | regulator-min-microvolt = <1000000>; |
| 38 | regulator-max-microvolt = <3000000>; | 38 | regulator-max-microvolt = <3000000>; |
| 39 | }; | 39 | }; |
| 40 | 40 | ||
| 41 | vmmc: regulator@3 { | 41 | vmmc: regulator-vmmc { |
| 42 | compatible = "ti,twl6030-vmmc"; | 42 | compatible = "ti,twl6030-vmmc"; |
| 43 | regulator-min-microvolt = <1200000>; | 43 | regulator-min-microvolt = <1200000>; |
| 44 | regulator-max-microvolt = <3000000>; | 44 | regulator-max-microvolt = <3000000>; |
| 45 | }; | 45 | }; |
| 46 | 46 | ||
| 47 | vpp: regulator@4 { | 47 | vpp: regulator-vpp { |
| 48 | compatible = "ti,twl6030-vpp"; | 48 | compatible = "ti,twl6030-vpp"; |
| 49 | regulator-min-microvolt = <1800000>; | 49 | regulator-min-microvolt = <1800000>; |
| 50 | regulator-max-microvolt = <2500000>; | 50 | regulator-max-microvolt = <2500000>; |
| 51 | }; | 51 | }; |
| 52 | 52 | ||
| 53 | vusim: regulator@5 { | 53 | vusim: regulator-vusim { |
| 54 | compatible = "ti,twl6030-vusim"; | 54 | compatible = "ti,twl6030-vusim"; |
| 55 | regulator-min-microvolt = <1200000>; | 55 | regulator-min-microvolt = <1200000>; |
| 56 | regulator-max-microvolt = <2900000>; | 56 | regulator-max-microvolt = <2900000>; |
| 57 | }; | 57 | }; |
| 58 | 58 | ||
| 59 | vdac: regulator@6 { | 59 | vdac: regulator-vdac { |
| 60 | compatible = "ti,twl6030-vdac"; | 60 | compatible = "ti,twl6030-vdac"; |
| 61 | }; | 61 | }; |
| 62 | 62 | ||
| 63 | vana: regulator@7 { | 63 | vana: regulator-vana { |
| 64 | compatible = "ti,twl6030-vana"; | 64 | compatible = "ti,twl6030-vana"; |
| 65 | }; | 65 | }; |
| 66 | 66 | ||
| 67 | vcxio: regulator@8 { | 67 | vcxio: regulator-vcxio { |
| 68 | compatible = "ti,twl6030-vcxio"; | 68 | compatible = "ti,twl6030-vcxio"; |
| 69 | regulator-always-on; | 69 | regulator-always-on; |
| 70 | }; | 70 | }; |
| 71 | 71 | ||
| 72 | vusb: regulator@9 { | 72 | vusb: regulator-vusb { |
| 73 | compatible = "ti,twl6030-vusb"; | 73 | compatible = "ti,twl6030-vusb"; |
| 74 | }; | 74 | }; |
| 75 | 75 | ||
| 76 | v1v8: regulator@10 { | 76 | v1v8: regulator-v1v8 { |
| 77 | compatible = "ti,twl6030-v1v8"; | 77 | compatible = "ti,twl6030-v1v8"; |
| 78 | regulator-always-on; | 78 | regulator-always-on; |
| 79 | }; | 79 | }; |
| 80 | 80 | ||
| 81 | v2v1: regulator@11 { | 81 | v2v1: regulator-v2v1 { |
| 82 | compatible = "ti,twl6030-v2v1"; | 82 | compatible = "ti,twl6030-v2v1"; |
| 83 | regulator-always-on; | 83 | regulator-always-on; |
| 84 | }; | 84 | }; |
| 85 | 85 | ||
| 86 | clk32kg: regulator@12 { | 86 | clk32kg: regulator-clk32kg { |
| 87 | compatible = "ti,twl6030-clk32kg"; | 87 | compatible = "ti,twl6030-clk32kg"; |
| 88 | }; | 88 | }; |
| 89 | }; | 89 | }; |
diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig index 3c9f32f9b6b4..565132d02105 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig | |||
| @@ -32,9 +32,7 @@ CONFIG_MACH_VPR200=y | |||
| 32 | CONFIG_MACH_IMX51_DT=y | 32 | CONFIG_MACH_IMX51_DT=y |
| 33 | CONFIG_MACH_MX51_3DS=y | 33 | CONFIG_MACH_MX51_3DS=y |
| 34 | CONFIG_MACH_EUKREA_CPUIMX51SD=y | 34 | CONFIG_MACH_EUKREA_CPUIMX51SD=y |
| 35 | CONFIG_MACH_MX51_EFIKAMX=y | 35 | CONFIG_SOC_IMX53=y |
| 36 | CONFIG_MACH_MX51_EFIKASB=y | ||
| 37 | CONFIG_MACH_IMX53_DT=y | ||
| 38 | CONFIG_SOC_IMX6Q=y | 36 | CONFIG_SOC_IMX6Q=y |
| 39 | CONFIG_MXC_PWM=y | 37 | CONFIG_MXC_PWM=y |
| 40 | CONFIG_SMP=y | 38 | CONFIG_SMP=y |
diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig index 4edcfb4e4dee..36d60dda310c 100644 --- a/arch/arm/configs/mxs_defconfig +++ b/arch/arm/configs/mxs_defconfig | |||
| @@ -23,12 +23,6 @@ CONFIG_BLK_DEV_INTEGRITY=y | |||
| 23 | # CONFIG_IOSCHED_CFQ is not set | 23 | # CONFIG_IOSCHED_CFQ is not set |
| 24 | CONFIG_ARCH_MXS=y | 24 | CONFIG_ARCH_MXS=y |
| 25 | CONFIG_MACH_MXS_DT=y | 25 | CONFIG_MACH_MXS_DT=y |
| 26 | CONFIG_MACH_MX23EVK=y | ||
| 27 | CONFIG_MACH_MX28EVK=y | ||
| 28 | CONFIG_MACH_STMP378X_DEVB=y | ||
| 29 | CONFIG_MACH_TX28=y | ||
| 30 | CONFIG_MACH_M28EVK=y | ||
| 31 | CONFIG_MACH_APX4DEVKIT=y | ||
| 32 | # CONFIG_ARM_THUMB is not set | 26 | # CONFIG_ARM_THUMB is not set |
| 33 | CONFIG_NO_HZ=y | 27 | CONFIG_NO_HZ=y |
| 34 | CONFIG_HIGH_RES_TIMERS=y | 28 | CONFIG_HIGH_RES_TIMERS=y |
diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig index e58edc36b406..62303043db9c 100644 --- a/arch/arm/configs/omap2plus_defconfig +++ b/arch/arm/configs/omap2plus_defconfig | |||
| @@ -123,6 +123,7 @@ CONFIG_HW_RANDOM=y | |||
| 123 | CONFIG_I2C_CHARDEV=y | 123 | CONFIG_I2C_CHARDEV=y |
| 124 | CONFIG_SPI=y | 124 | CONFIG_SPI=y |
| 125 | CONFIG_SPI_OMAP24XX=y | 125 | CONFIG_SPI_OMAP24XX=y |
| 126 | CONFIG_PINCTRL_SINGLE=y | ||
| 126 | CONFIG_DEBUG_GPIO=y | 127 | CONFIG_DEBUG_GPIO=y |
| 127 | CONFIG_GPIO_SYSFS=y | 128 | CONFIG_GPIO_SYSFS=y |
| 128 | CONFIG_GPIO_TWL4030=y | 129 | CONFIG_GPIO_TWL4030=y |
diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h index 03fb93621d0d..5c8b3bf4d825 100644 --- a/arch/arm/include/asm/assembler.h +++ b/arch/arm/include/asm/assembler.h | |||
| @@ -320,4 +320,12 @@ | |||
| 320 | .size \name , . - \name | 320 | .size \name , . - \name |
| 321 | .endm | 321 | .endm |
| 322 | 322 | ||
| 323 | .macro check_uaccess, addr:req, size:req, limit:req, tmp:req, bad:req | ||
| 324 | #ifndef CONFIG_CPU_USE_DOMAINS | ||
| 325 | adds \tmp, \addr, #\size - 1 | ||
| 326 | sbcccs \tmp, \tmp, \limit | ||
| 327 | bcs \bad | ||
| 328 | #endif | ||
| 329 | .endm | ||
| 330 | |||
| 323 | #endif /* __ASM_ASSEMBLER_H__ */ | 331 | #endif /* __ASM_ASSEMBLER_H__ */ |
diff --git a/arch/arm/include/asm/hardware/cache-tauros2.h b/arch/arm/include/asm/hardware/cache-tauros2.h index 538f17ca905b..295e2e40151b 100644 --- a/arch/arm/include/asm/hardware/cache-tauros2.h +++ b/arch/arm/include/asm/hardware/cache-tauros2.h | |||
| @@ -8,4 +8,7 @@ | |||
| 8 | * warranty of any kind, whether express or implied. | 8 | * warranty of any kind, whether express or implied. |
| 9 | */ | 9 | */ |
| 10 | 10 | ||
| 11 | extern void __init tauros2_init(void); | 11 | #define CACHE_TAUROS2_PREFETCH_ON (1 << 0) |
| 12 | #define CACHE_TAUROS2_LINEFILL_BURST8 (1 << 1) | ||
| 13 | |||
| 14 | extern void __init tauros2_init(unsigned int features); | ||
diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h index e965f1b560f1..5f6ddcc56452 100644 --- a/arch/arm/include/asm/memory.h +++ b/arch/arm/include/asm/memory.h | |||
| @@ -187,6 +187,7 @@ static inline unsigned long __phys_to_virt(unsigned long x) | |||
| 187 | #define __phys_to_virt(x) ((x) - PHYS_OFFSET + PAGE_OFFSET) | 187 | #define __phys_to_virt(x) ((x) - PHYS_OFFSET + PAGE_OFFSET) |
| 188 | #endif | 188 | #endif |
| 189 | #endif | 189 | #endif |
| 190 | #endif /* __ASSEMBLY__ */ | ||
| 190 | 191 | ||
| 191 | #ifndef PHYS_OFFSET | 192 | #ifndef PHYS_OFFSET |
| 192 | #ifdef PLAT_PHYS_OFFSET | 193 | #ifdef PLAT_PHYS_OFFSET |
| @@ -196,6 +197,8 @@ static inline unsigned long __phys_to_virt(unsigned long x) | |||
| 196 | #endif | 197 | #endif |
| 197 | #endif | 198 | #endif |
| 198 | 199 | ||
| 200 | #ifndef __ASSEMBLY__ | ||
| 201 | |||
| 199 | /* | 202 | /* |
| 200 | * PFNs are used to describe any physical page; this means | 203 | * PFNs are used to describe any physical page; this means |
| 201 | * PFN 0 == physical address 0. | 204 | * PFN 0 == physical address 0. |
diff --git a/arch/arm/include/asm/tlb.h b/arch/arm/include/asm/tlb.h index 314d4664eae7..99a19512ee26 100644 --- a/arch/arm/include/asm/tlb.h +++ b/arch/arm/include/asm/tlb.h | |||
| @@ -199,6 +199,9 @@ static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte, | |||
| 199 | { | 199 | { |
| 200 | pgtable_page_dtor(pte); | 200 | pgtable_page_dtor(pte); |
| 201 | 201 | ||
| 202 | #ifdef CONFIG_ARM_LPAE | ||
| 203 | tlb_add_flush(tlb, addr); | ||
| 204 | #else | ||
| 202 | /* | 205 | /* |
| 203 | * With the classic ARM MMU, a pte page has two corresponding pmd | 206 | * With the classic ARM MMU, a pte page has two corresponding pmd |
| 204 | * entries, each covering 1MB. | 207 | * entries, each covering 1MB. |
| @@ -206,6 +209,7 @@ static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte, | |||
| 206 | addr &= PMD_MASK; | 209 | addr &= PMD_MASK; |
| 207 | tlb_add_flush(tlb, addr + SZ_1M - PAGE_SIZE); | 210 | tlb_add_flush(tlb, addr + SZ_1M - PAGE_SIZE); |
| 208 | tlb_add_flush(tlb, addr + SZ_1M); | 211 | tlb_add_flush(tlb, addr + SZ_1M); |
| 212 | #endif | ||
| 209 | 213 | ||
| 210 | tlb_remove_page(tlb, pte); | 214 | tlb_remove_page(tlb, pte); |
| 211 | } | 215 | } |
diff --git a/arch/arm/include/asm/uaccess.h b/arch/arm/include/asm/uaccess.h index 479a6352e0b5..77bd79f2ffdb 100644 --- a/arch/arm/include/asm/uaccess.h +++ b/arch/arm/include/asm/uaccess.h | |||
| @@ -101,28 +101,39 @@ extern int __get_user_1(void *); | |||
| 101 | extern int __get_user_2(void *); | 101 | extern int __get_user_2(void *); |
| 102 | extern int __get_user_4(void *); | 102 | extern int __get_user_4(void *); |
| 103 | 103 | ||
| 104 | #define __get_user_x(__r2,__p,__e,__s,__i...) \ | 104 | #define __GUP_CLOBBER_1 "lr", "cc" |
| 105 | #ifdef CONFIG_CPU_USE_DOMAINS | ||
| 106 | #define __GUP_CLOBBER_2 "ip", "lr", "cc" | ||
| 107 | #else | ||
| 108 | #define __GUP_CLOBBER_2 "lr", "cc" | ||
| 109 | #endif | ||
| 110 | #define __GUP_CLOBBER_4 "lr", "cc" | ||
| 111 | |||
| 112 | #define __get_user_x(__r2,__p,__e,__l,__s) \ | ||
| 105 | __asm__ __volatile__ ( \ | 113 | __asm__ __volatile__ ( \ |
| 106 | __asmeq("%0", "r0") __asmeq("%1", "r2") \ | 114 | __asmeq("%0", "r0") __asmeq("%1", "r2") \ |
| 115 | __asmeq("%3", "r1") \ | ||
| 107 | "bl __get_user_" #__s \ | 116 | "bl __get_user_" #__s \ |
| 108 | : "=&r" (__e), "=r" (__r2) \ | 117 | : "=&r" (__e), "=r" (__r2) \ |
| 109 | : "0" (__p) \ | 118 | : "0" (__p), "r" (__l) \ |
| 110 | : __i, "cc") | 119 | : __GUP_CLOBBER_##__s) |
| 111 | 120 | ||
| 112 | #define get_user(x,p) \ | 121 | #define __get_user_check(x,p) \ |
| 113 | ({ \ | 122 | ({ \ |
| 123 | unsigned long __limit = current_thread_info()->addr_limit - 1; \ | ||
| 114 | register const typeof(*(p)) __user *__p asm("r0") = (p);\ | 124 | register const typeof(*(p)) __user *__p asm("r0") = (p);\ |
| 115 | register unsigned long __r2 asm("r2"); \ | 125 | register unsigned long __r2 asm("r2"); \ |
| 126 | register unsigned long __l asm("r1") = __limit; \ | ||
| 116 | register int __e asm("r0"); \ | 127 | register int __e asm("r0"); \ |
| 117 | switch (sizeof(*(__p))) { \ | 128 | switch (sizeof(*(__p))) { \ |
| 118 | case 1: \ | 129 | case 1: \ |
| 119 | __get_user_x(__r2, __p, __e, 1, "lr"); \ | 130 | __get_user_x(__r2, __p, __e, __l, 1); \ |
| 120 | break; \ | 131 | break; \ |
| 121 | case 2: \ | 132 | case 2: \ |
| 122 | __get_user_x(__r2, __p, __e, 2, "r3", "lr"); \ | 133 | __get_user_x(__r2, __p, __e, __l, 2); \ |
| 123 | break; \ | 134 | break; \ |
| 124 | case 4: \ | 135 | case 4: \ |
| 125 | __get_user_x(__r2, __p, __e, 4, "lr"); \ | 136 | __get_user_x(__r2, __p, __e, __l, 4); \ |
| 126 | break; \ | 137 | break; \ |
| 127 | default: __e = __get_user_bad(); break; \ | 138 | default: __e = __get_user_bad(); break; \ |
| 128 | } \ | 139 | } \ |
| @@ -130,42 +141,57 @@ extern int __get_user_4(void *); | |||
| 130 | __e; \ | 141 | __e; \ |
| 131 | }) | 142 | }) |
| 132 | 143 | ||
| 144 | #define get_user(x,p) \ | ||
| 145 | ({ \ | ||
| 146 | might_fault(); \ | ||
| 147 | __get_user_check(x,p); \ | ||
| 148 | }) | ||
| 149 | |||
| 133 | extern int __put_user_1(void *, unsigned int); | 150 | extern int __put_user_1(void *, unsigned int); |
| 134 | extern int __put_user_2(void *, unsigned int); | 151 | extern int __put_user_2(void *, unsigned int); |
| 135 | extern int __put_user_4(void *, unsigned int); | 152 | extern int __put_user_4(void *, unsigned int); |
| 136 | extern int __put_user_8(void *, unsigned long long); | 153 | extern int __put_user_8(void *, unsigned long long); |
| 137 | 154 | ||
| 138 | #define __put_user_x(__r2,__p,__e,__s) \ | 155 | #define __put_user_x(__r2,__p,__e,__l,__s) \ |
| 139 | __asm__ __volatile__ ( \ | 156 | __asm__ __volatile__ ( \ |
| 140 | __asmeq("%0", "r0") __asmeq("%2", "r2") \ | 157 | __asmeq("%0", "r0") __asmeq("%2", "r2") \ |
| 158 | __asmeq("%3", "r1") \ | ||
| 141 | "bl __put_user_" #__s \ | 159 | "bl __put_user_" #__s \ |
| 142 | : "=&r" (__e) \ | 160 | : "=&r" (__e) \ |
| 143 | : "0" (__p), "r" (__r2) \ | 161 | : "0" (__p), "r" (__r2), "r" (__l) \ |
| 144 | : "ip", "lr", "cc") | 162 | : "ip", "lr", "cc") |
| 145 | 163 | ||
| 146 | #define put_user(x,p) \ | 164 | #define __put_user_check(x,p) \ |
| 147 | ({ \ | 165 | ({ \ |
| 166 | unsigned long __limit = current_thread_info()->addr_limit - 1; \ | ||
| 148 | register const typeof(*(p)) __r2 asm("r2") = (x); \ | 167 | register const typeof(*(p)) __r2 asm("r2") = (x); \ |
| 149 | register const typeof(*(p)) __user *__p asm("r0") = (p);\ | 168 | register const typeof(*(p)) __user *__p asm("r0") = (p);\ |
| 169 | register unsigned long __l asm("r1") = __limit; \ | ||
| 150 | register int __e asm("r0"); \ | 170 | register int __e asm("r0"); \ |
| 151 | switch (sizeof(*(__p))) { \ | 171 | switch (sizeof(*(__p))) { \ |
| 152 | case 1: \ | 172 | case 1: \ |
| 153 | __put_user_x(__r2, __p, __e, 1); \ | 173 | __put_user_x(__r2, __p, __e, __l, 1); \ |
| 154 | break; \ | 174 | break; \ |
| 155 | case 2: \ | 175 | case 2: \ |
| 156 | __put_user_x(__r2, __p, __e, 2); \ | 176 | __put_user_x(__r2, __p, __e, __l, 2); \ |
| 157 | break; \ | 177 | break; \ |
| 158 | case 4: \ | 178 | case 4: \ |
| 159 | __put_user_x(__r2, __p, __e, 4); \ | 179 | __put_user_x(__r2, __p, __e, __l, 4); \ |
| 160 | break; \ | 180 | break; \ |
| 161 | case 8: \ | 181 | case 8: \ |
| 162 | __put_user_x(__r2, __p, __e, 8); \ | 182 | __put_user_x(__r2, __p, __e, __l, 8); \ |
| 163 | break; \ | 183 | break; \ |
| 164 | default: __e = __put_user_bad(); break; \ | 184 | default: __e = __put_user_bad(); break; \ |
| 165 | } \ | 185 | } \ |
| 166 | __e; \ | 186 | __e; \ |
| 167 | }) | 187 | }) |
| 168 | 188 | ||
| 189 | #define put_user(x,p) \ | ||
| 190 | ({ \ | ||
| 191 | might_fault(); \ | ||
| 192 | __put_user_check(x,p); \ | ||
| 193 | }) | ||
| 194 | |||
| 169 | #else /* CONFIG_MMU */ | 195 | #else /* CONFIG_MMU */ |
| 170 | 196 | ||
| 171 | /* | 197 | /* |
| @@ -219,6 +245,7 @@ do { \ | |||
| 219 | unsigned long __gu_addr = (unsigned long)(ptr); \ | 245 | unsigned long __gu_addr = (unsigned long)(ptr); \ |
| 220 | unsigned long __gu_val; \ | 246 | unsigned long __gu_val; \ |
| 221 | __chk_user_ptr(ptr); \ | 247 | __chk_user_ptr(ptr); \ |
| 248 | might_fault(); \ | ||
| 222 | switch (sizeof(*(ptr))) { \ | 249 | switch (sizeof(*(ptr))) { \ |
| 223 | case 1: __get_user_asm_byte(__gu_val,__gu_addr,err); break; \ | 250 | case 1: __get_user_asm_byte(__gu_val,__gu_addr,err); break; \ |
| 224 | case 2: __get_user_asm_half(__gu_val,__gu_addr,err); break; \ | 251 | case 2: __get_user_asm_half(__gu_val,__gu_addr,err); break; \ |
| @@ -300,6 +327,7 @@ do { \ | |||
| 300 | unsigned long __pu_addr = (unsigned long)(ptr); \ | 327 | unsigned long __pu_addr = (unsigned long)(ptr); \ |
| 301 | __typeof__(*(ptr)) __pu_val = (x); \ | 328 | __typeof__(*(ptr)) __pu_val = (x); \ |
| 302 | __chk_user_ptr(ptr); \ | 329 | __chk_user_ptr(ptr); \ |
| 330 | might_fault(); \ | ||
| 303 | switch (sizeof(*(ptr))) { \ | 331 | switch (sizeof(*(ptr))) { \ |
| 304 | case 1: __put_user_asm_byte(__pu_val,__pu_addr,err); break; \ | 332 | case 1: __put_user_asm_byte(__pu_val,__pu_addr,err); break; \ |
| 305 | case 2: __put_user_asm_half(__pu_val,__pu_addr,err); break; \ | 333 | case 2: __put_user_asm_half(__pu_val,__pu_addr,err); break; \ |
diff --git a/arch/arm/kernel/hw_breakpoint.c b/arch/arm/kernel/hw_breakpoint.c index ba386bd94107..281bf3301241 100644 --- a/arch/arm/kernel/hw_breakpoint.c +++ b/arch/arm/kernel/hw_breakpoint.c | |||
| @@ -159,6 +159,12 @@ static int debug_arch_supported(void) | |||
| 159 | arch >= ARM_DEBUG_ARCH_V7_1; | 159 | arch >= ARM_DEBUG_ARCH_V7_1; |
| 160 | } | 160 | } |
| 161 | 161 | ||
| 162 | /* Can we determine the watchpoint access type from the fsr? */ | ||
| 163 | static int debug_exception_updates_fsr(void) | ||
| 164 | { | ||
| 165 | return 0; | ||
| 166 | } | ||
| 167 | |||
| 162 | /* Determine number of WRP registers available. */ | 168 | /* Determine number of WRP registers available. */ |
| 163 | static int get_num_wrp_resources(void) | 169 | static int get_num_wrp_resources(void) |
| 164 | { | 170 | { |
| @@ -604,13 +610,14 @@ int arch_validate_hwbkpt_settings(struct perf_event *bp) | |||
| 604 | /* Aligned */ | 610 | /* Aligned */ |
| 605 | break; | 611 | break; |
| 606 | case 1: | 612 | case 1: |
| 607 | /* Allow single byte watchpoint. */ | ||
| 608 | if (info->ctrl.len == ARM_BREAKPOINT_LEN_1) | ||
| 609 | break; | ||
| 610 | case 2: | 613 | case 2: |
| 611 | /* Allow halfword watchpoints and breakpoints. */ | 614 | /* Allow halfword watchpoints and breakpoints. */ |
| 612 | if (info->ctrl.len == ARM_BREAKPOINT_LEN_2) | 615 | if (info->ctrl.len == ARM_BREAKPOINT_LEN_2) |
| 613 | break; | 616 | break; |
| 617 | case 3: | ||
| 618 | /* Allow single byte watchpoint. */ | ||
| 619 | if (info->ctrl.len == ARM_BREAKPOINT_LEN_1) | ||
| 620 | break; | ||
| 614 | default: | 621 | default: |
| 615 | ret = -EINVAL; | 622 | ret = -EINVAL; |
| 616 | goto out; | 623 | goto out; |
| @@ -619,18 +626,35 @@ int arch_validate_hwbkpt_settings(struct perf_event *bp) | |||
| 619 | info->address &= ~alignment_mask; | 626 | info->address &= ~alignment_mask; |
| 620 | info->ctrl.len <<= offset; | 627 | info->ctrl.len <<= offset; |
| 621 | 628 | ||
| 622 | /* | 629 | if (!bp->overflow_handler) { |
| 623 | * Currently we rely on an overflow handler to take | 630 | /* |
| 624 | * care of single-stepping the breakpoint when it fires. | 631 | * Mismatch breakpoints are required for single-stepping |
| 625 | * In the case of userspace breakpoints on a core with V7 debug, | 632 | * breakpoints. |
| 626 | * we can use the mismatch feature as a poor-man's hardware | 633 | */ |
| 627 | * single-step, but this only works for per-task breakpoints. | 634 | if (!core_has_mismatch_brps()) |
| 628 | */ | 635 | return -EINVAL; |
| 629 | if (!bp->overflow_handler && (arch_check_bp_in_kernelspace(bp) || | 636 | |
| 630 | !core_has_mismatch_brps() || !bp->hw.bp_target)) { | 637 | /* We don't allow mismatch breakpoints in kernel space. */ |
| 631 | pr_warning("overflow handler required but none found\n"); | 638 | if (arch_check_bp_in_kernelspace(bp)) |
| 632 | ret = -EINVAL; | 639 | return -EPERM; |
| 640 | |||
| 641 | /* | ||
| 642 | * Per-cpu breakpoints are not supported by our stepping | ||
| 643 | * mechanism. | ||
| 644 | */ | ||
| 645 | if (!bp->hw.bp_target) | ||
| 646 | return -EINVAL; | ||
| 647 | |||
| 648 | /* | ||
| 649 | * We only support specific access types if the fsr | ||
| 650 | * reports them. | ||
| 651 | */ | ||
| 652 | if (!debug_exception_updates_fsr() && | ||
| 653 | (info->ctrl.type == ARM_BREAKPOINT_LOAD || | ||
| 654 | info->ctrl.type == ARM_BREAKPOINT_STORE)) | ||
| 655 | return -EINVAL; | ||
| 633 | } | 656 | } |
| 657 | |||
| 634 | out: | 658 | out: |
| 635 | return ret; | 659 | return ret; |
| 636 | } | 660 | } |
| @@ -706,10 +730,12 @@ static void watchpoint_handler(unsigned long addr, unsigned int fsr, | |||
| 706 | goto unlock; | 730 | goto unlock; |
| 707 | 731 | ||
| 708 | /* Check that the access type matches. */ | 732 | /* Check that the access type matches. */ |
| 709 | access = (fsr & ARM_FSR_ACCESS_MASK) ? HW_BREAKPOINT_W : | 733 | if (debug_exception_updates_fsr()) { |
| 710 | HW_BREAKPOINT_R; | 734 | access = (fsr & ARM_FSR_ACCESS_MASK) ? |
| 711 | if (!(access & hw_breakpoint_type(wp))) | 735 | HW_BREAKPOINT_W : HW_BREAKPOINT_R; |
| 712 | goto unlock; | 736 | if (!(access & hw_breakpoint_type(wp))) |
| 737 | goto unlock; | ||
| 738 | } | ||
| 713 | 739 | ||
| 714 | /* We have a winner. */ | 740 | /* We have a winner. */ |
| 715 | info->trigger = addr; | 741 | info->trigger = addr; |
diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c index f7945218b8c6..b0179b89a04c 100644 --- a/arch/arm/kernel/traps.c +++ b/arch/arm/kernel/traps.c | |||
| @@ -420,20 +420,23 @@ asmlinkage void __exception do_undefinstr(struct pt_regs *regs) | |||
| 420 | #endif | 420 | #endif |
| 421 | instr = *(u32 *) pc; | 421 | instr = *(u32 *) pc; |
| 422 | } else if (thumb_mode(regs)) { | 422 | } else if (thumb_mode(regs)) { |
| 423 | get_user(instr, (u16 __user *)pc); | 423 | if (get_user(instr, (u16 __user *)pc)) |
| 424 | goto die_sig; | ||
| 424 | if (is_wide_instruction(instr)) { | 425 | if (is_wide_instruction(instr)) { |
| 425 | unsigned int instr2; | 426 | unsigned int instr2; |
| 426 | get_user(instr2, (u16 __user *)pc+1); | 427 | if (get_user(instr2, (u16 __user *)pc+1)) |
| 428 | goto die_sig; | ||
| 427 | instr <<= 16; | 429 | instr <<= 16; |
| 428 | instr |= instr2; | 430 | instr |= instr2; |
| 429 | } | 431 | } |
| 430 | } else { | 432 | } else if (get_user(instr, (u32 __user *)pc)) { |
| 431 | get_user(instr, (u32 __user *)pc); | 433 | goto die_sig; |
| 432 | } | 434 | } |
| 433 | 435 | ||
| 434 | if (call_undef_hook(regs, instr) == 0) | 436 | if (call_undef_hook(regs, instr) == 0) |
| 435 | return; | 437 | return; |
| 436 | 438 | ||
| 439 | die_sig: | ||
| 437 | #ifdef CONFIG_DEBUG_USER | 440 | #ifdef CONFIG_DEBUG_USER |
| 438 | if (user_debug & UDBG_UNDEFINED) { | 441 | if (user_debug & UDBG_UNDEFINED) { |
| 439 | printk(KERN_INFO "%s (%d): undefined instruction: pc=%p\n", | 442 | printk(KERN_INFO "%s (%d): undefined instruction: pc=%p\n", |
diff --git a/arch/arm/lib/delay.c b/arch/arm/lib/delay.c index d6dacc69254e..395d5fbb8fa2 100644 --- a/arch/arm/lib/delay.c +++ b/arch/arm/lib/delay.c | |||
| @@ -59,6 +59,7 @@ void __init init_current_timer_delay(unsigned long freq) | |||
| 59 | { | 59 | { |
| 60 | pr_info("Switching to timer-based delay loop\n"); | 60 | pr_info("Switching to timer-based delay loop\n"); |
| 61 | lpj_fine = freq / HZ; | 61 | lpj_fine = freq / HZ; |
| 62 | loops_per_jiffy = lpj_fine; | ||
| 62 | arm_delay_ops.delay = __timer_delay; | 63 | arm_delay_ops.delay = __timer_delay; |
| 63 | arm_delay_ops.const_udelay = __timer_const_udelay; | 64 | arm_delay_ops.const_udelay = __timer_const_udelay; |
| 64 | arm_delay_ops.udelay = __timer_udelay; | 65 | arm_delay_ops.udelay = __timer_udelay; |
diff --git a/arch/arm/lib/getuser.S b/arch/arm/lib/getuser.S index 11093a7c3e32..9b06bb41fca6 100644 --- a/arch/arm/lib/getuser.S +++ b/arch/arm/lib/getuser.S | |||
| @@ -16,8 +16,9 @@ | |||
| 16 | * __get_user_X | 16 | * __get_user_X |
| 17 | * | 17 | * |
| 18 | * Inputs: r0 contains the address | 18 | * Inputs: r0 contains the address |
| 19 | * r1 contains the address limit, which must be preserved | ||
| 19 | * Outputs: r0 is the error code | 20 | * Outputs: r0 is the error code |
| 20 | * r2, r3 contains the zero-extended value | 21 | * r2 contains the zero-extended value |
| 21 | * lr corrupted | 22 | * lr corrupted |
| 22 | * | 23 | * |
| 23 | * No other registers must be altered. (see <asm/uaccess.h> | 24 | * No other registers must be altered. (see <asm/uaccess.h> |
| @@ -27,33 +28,39 @@ | |||
| 27 | * Note also that it is intended that __get_user_bad is not global. | 28 | * Note also that it is intended that __get_user_bad is not global. |
| 28 | */ | 29 | */ |
| 29 | #include <linux/linkage.h> | 30 | #include <linux/linkage.h> |
| 31 | #include <asm/assembler.h> | ||
| 30 | #include <asm/errno.h> | 32 | #include <asm/errno.h> |
| 31 | #include <asm/domain.h> | 33 | #include <asm/domain.h> |
| 32 | 34 | ||
| 33 | ENTRY(__get_user_1) | 35 | ENTRY(__get_user_1) |
| 36 | check_uaccess r0, 1, r1, r2, __get_user_bad | ||
| 34 | 1: TUSER(ldrb) r2, [r0] | 37 | 1: TUSER(ldrb) r2, [r0] |
| 35 | mov r0, #0 | 38 | mov r0, #0 |
| 36 | mov pc, lr | 39 | mov pc, lr |
| 37 | ENDPROC(__get_user_1) | 40 | ENDPROC(__get_user_1) |
| 38 | 41 | ||
| 39 | ENTRY(__get_user_2) | 42 | ENTRY(__get_user_2) |
| 40 | #ifdef CONFIG_THUMB2_KERNEL | 43 | check_uaccess r0, 2, r1, r2, __get_user_bad |
| 41 | 2: TUSER(ldrb) r2, [r0] | 44 | #ifdef CONFIG_CPU_USE_DOMAINS |
| 42 | 3: TUSER(ldrb) r3, [r0, #1] | 45 | rb .req ip |
| 46 | 2: ldrbt r2, [r0], #1 | ||
| 47 | 3: ldrbt rb, [r0], #0 | ||
| 43 | #else | 48 | #else |
| 44 | 2: TUSER(ldrb) r2, [r0], #1 | 49 | rb .req r0 |
| 45 | 3: TUSER(ldrb) r3, [r0] | 50 | 2: ldrb r2, [r0] |
| 51 | 3: ldrb rb, [r0, #1] | ||
| 46 | #endif | 52 | #endif |
| 47 | #ifndef __ARMEB__ | 53 | #ifndef __ARMEB__ |
| 48 | orr r2, r2, r3, lsl #8 | 54 | orr r2, r2, rb, lsl #8 |
| 49 | #else | 55 | #else |
| 50 | orr r2, r3, r2, lsl #8 | 56 | orr r2, rb, r2, lsl #8 |
| 51 | #endif | 57 | #endif |
| 52 | mov r0, #0 | 58 | mov r0, #0 |
| 53 | mov pc, lr | 59 | mov pc, lr |
| 54 | ENDPROC(__get_user_2) | 60 | ENDPROC(__get_user_2) |
| 55 | 61 | ||
| 56 | ENTRY(__get_user_4) | 62 | ENTRY(__get_user_4) |
| 63 | check_uaccess r0, 4, r1, r2, __get_user_bad | ||
| 57 | 4: TUSER(ldr) r2, [r0] | 64 | 4: TUSER(ldr) r2, [r0] |
| 58 | mov r0, #0 | 65 | mov r0, #0 |
| 59 | mov pc, lr | 66 | mov pc, lr |
diff --git a/arch/arm/lib/putuser.S b/arch/arm/lib/putuser.S index 7db25990c589..3d73dcb959b0 100644 --- a/arch/arm/lib/putuser.S +++ b/arch/arm/lib/putuser.S | |||
| @@ -16,6 +16,7 @@ | |||
| 16 | * __put_user_X | 16 | * __put_user_X |
| 17 | * | 17 | * |
| 18 | * Inputs: r0 contains the address | 18 | * Inputs: r0 contains the address |
| 19 | * r1 contains the address limit, which must be preserved | ||
| 19 | * r2, r3 contains the value | 20 | * r2, r3 contains the value |
| 20 | * Outputs: r0 is the error code | 21 | * Outputs: r0 is the error code |
| 21 | * lr corrupted | 22 | * lr corrupted |
| @@ -27,16 +28,19 @@ | |||
| 27 | * Note also that it is intended that __put_user_bad is not global. | 28 | * Note also that it is intended that __put_user_bad is not global. |
| 28 | */ | 29 | */ |
| 29 | #include <linux/linkage.h> | 30 | #include <linux/linkage.h> |
| 31 | #include <asm/assembler.h> | ||
| 30 | #include <asm/errno.h> | 32 | #include <asm/errno.h> |
| 31 | #include <asm/domain.h> | 33 | #include <asm/domain.h> |
| 32 | 34 | ||
| 33 | ENTRY(__put_user_1) | 35 | ENTRY(__put_user_1) |
| 36 | check_uaccess r0, 1, r1, ip, __put_user_bad | ||
| 34 | 1: TUSER(strb) r2, [r0] | 37 | 1: TUSER(strb) r2, [r0] |
| 35 | mov r0, #0 | 38 | mov r0, #0 |
| 36 | mov pc, lr | 39 | mov pc, lr |
| 37 | ENDPROC(__put_user_1) | 40 | ENDPROC(__put_user_1) |
| 38 | 41 | ||
| 39 | ENTRY(__put_user_2) | 42 | ENTRY(__put_user_2) |
| 43 | check_uaccess r0, 2, r1, ip, __put_user_bad | ||
| 40 | mov ip, r2, lsr #8 | 44 | mov ip, r2, lsr #8 |
| 41 | #ifdef CONFIG_THUMB2_KERNEL | 45 | #ifdef CONFIG_THUMB2_KERNEL |
| 42 | #ifndef __ARMEB__ | 46 | #ifndef __ARMEB__ |
| @@ -60,12 +64,14 @@ ENTRY(__put_user_2) | |||
| 60 | ENDPROC(__put_user_2) | 64 | ENDPROC(__put_user_2) |
| 61 | 65 | ||
| 62 | ENTRY(__put_user_4) | 66 | ENTRY(__put_user_4) |
| 67 | check_uaccess r0, 4, r1, ip, __put_user_bad | ||
| 63 | 4: TUSER(str) r2, [r0] | 68 | 4: TUSER(str) r2, [r0] |
| 64 | mov r0, #0 | 69 | mov r0, #0 |
| 65 | mov pc, lr | 70 | mov pc, lr |
| 66 | ENDPROC(__put_user_4) | 71 | ENDPROC(__put_user_4) |
| 67 | 72 | ||
| 68 | ENTRY(__put_user_8) | 73 | ENTRY(__put_user_8) |
| 74 | check_uaccess r0, 8, r1, ip, __put_user_bad | ||
| 69 | #ifdef CONFIG_THUMB2_KERNEL | 75 | #ifdef CONFIG_THUMB2_KERNEL |
| 70 | 5: TUSER(str) r2, [r0] | 76 | 5: TUSER(str) r2, [r0] |
| 71 | 6: TUSER(str) r3, [r0, #4] | 77 | 6: TUSER(str) r3, [r0, #4] |
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c index 6321567d8eaa..e5a97d97e38d 100644 --- a/arch/arm/mach-dove/common.c +++ b/arch/arm/mach-dove/common.c | |||
| @@ -289,7 +289,7 @@ void __init dove_init(void) | |||
| 289 | printk(KERN_INFO "TCLK = %dMHz\n", (get_tclk() + 499999) / 1000000); | 289 | printk(KERN_INFO "TCLK = %dMHz\n", (get_tclk() + 499999) / 1000000); |
| 290 | 290 | ||
| 291 | #ifdef CONFIG_CACHE_TAUROS2 | 291 | #ifdef CONFIG_CACHE_TAUROS2 |
| 292 | tauros2_init(); | 292 | tauros2_init(0); |
| 293 | #endif | 293 | #endif |
| 294 | dove_setup_cpu_mbus(); | 294 | dove_setup_cpu_mbus(); |
| 295 | 295 | ||
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index afd542ad6f97..7ca5fe45945f 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig | |||
| @@ -101,13 +101,8 @@ config SOC_IMX51 | |||
| 101 | select SOC_IMX5 | 101 | select SOC_IMX5 |
| 102 | select ARCH_MX5 | 102 | select ARCH_MX5 |
| 103 | select ARCH_MX51 | 103 | select ARCH_MX51 |
| 104 | 104 | select PINCTRL | |
| 105 | config SOC_IMX53 | 105 | select PINCTRL_IMX51 |
| 106 | bool | ||
| 107 | select SOC_IMX5 | ||
| 108 | select ARCH_MX5 | ||
| 109 | select ARCH_MX53 | ||
| 110 | select HAVE_CAN_FLEXCAN if CAN | ||
| 111 | 106 | ||
| 112 | if ARCH_IMX_V4_V5 | 107 | if ARCH_IMX_V4_V5 |
| 113 | 108 | ||
| @@ -561,7 +556,6 @@ config MACH_BUG | |||
| 561 | config MACH_IMX31_DT | 556 | config MACH_IMX31_DT |
| 562 | bool "Support i.MX31 platforms from device tree" | 557 | bool "Support i.MX31 platforms from device tree" |
| 563 | select SOC_IMX31 | 558 | select SOC_IMX31 |
| 564 | select USE_OF | ||
| 565 | help | 559 | help |
| 566 | Include support for Freescale i.MX31 based platforms | 560 | Include support for Freescale i.MX31 based platforms |
| 567 | using the device tree for discovery. | 561 | using the device tree for discovery. |
| @@ -737,95 +731,19 @@ config MACH_EUKREA_MBIMXSD51_BASEBOARD | |||
| 737 | 731 | ||
| 738 | endchoice | 732 | endchoice |
| 739 | 733 | ||
| 740 | config MX51_EFIKA_COMMON | 734 | comment "Device tree only" |
| 741 | bool | ||
| 742 | select SOC_IMX51 | ||
| 743 | select IMX_HAVE_PLATFORM_IMX_UART | ||
| 744 | select IMX_HAVE_PLATFORM_MXC_EHCI | ||
| 745 | select IMX_HAVE_PLATFORM_PATA_IMX | ||
| 746 | select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX | ||
| 747 | select IMX_HAVE_PLATFORM_SPI_IMX | ||
| 748 | select MXC_ULPI if USB_ULPI | ||
| 749 | |||
| 750 | config MACH_MX51_EFIKAMX | ||
| 751 | bool "Support MX51 Genesi Efika MX nettop" | ||
| 752 | select LEDS_GPIO_REGISTER | ||
| 753 | select MX51_EFIKA_COMMON | ||
| 754 | help | ||
| 755 | Include support for Genesi Efika MX nettop. This includes specific | ||
| 756 | configurations for the board and its peripherals. | ||
| 757 | |||
| 758 | config MACH_MX51_EFIKASB | ||
| 759 | bool "Support MX51 Genesi Efika Smartbook" | ||
| 760 | select LEDS_GPIO_REGISTER | ||
| 761 | select MX51_EFIKA_COMMON | ||
| 762 | help | ||
| 763 | Include support for Genesi Efika Smartbook. This includes specific | ||
| 764 | configurations for the board and its peripherals. | ||
| 765 | |||
| 766 | comment "i.MX53 machines:" | ||
| 767 | |||
| 768 | config MACH_IMX53_DT | ||
| 769 | bool "Support i.MX53 platforms from device tree" | ||
| 770 | select SOC_IMX53 | ||
| 771 | select MACH_MX53_ARD | ||
| 772 | select MACH_MX53_EVK | ||
| 773 | select MACH_MX53_LOCO | ||
| 774 | select MACH_MX53_SMD | ||
| 775 | help | ||
| 776 | Include support for Freescale i.MX53 based platforms | ||
| 777 | using the device tree for discovery | ||
| 778 | |||
| 779 | config MACH_MX53_EVK | ||
| 780 | bool "Support MX53 EVK platforms" | ||
| 781 | select SOC_IMX53 | ||
| 782 | select IMX_HAVE_PLATFORM_IMX2_WDT | ||
| 783 | select IMX_HAVE_PLATFORM_IMX_UART | ||
| 784 | select IMX_HAVE_PLATFORM_IMX_I2C | ||
| 785 | select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX | ||
| 786 | select IMX_HAVE_PLATFORM_SPI_IMX | ||
| 787 | select LEDS_GPIO_REGISTER | ||
| 788 | help | ||
| 789 | Include support for MX53 EVK platform. This includes specific | ||
| 790 | configurations for the board and its peripherals. | ||
| 791 | |||
| 792 | config MACH_MX53_SMD | ||
| 793 | bool "Support MX53 SMD platforms" | ||
| 794 | select SOC_IMX53 | ||
| 795 | select IMX_HAVE_PLATFORM_IMX2_WDT | ||
| 796 | select IMX_HAVE_PLATFORM_IMX_I2C | ||
| 797 | select IMX_HAVE_PLATFORM_IMX_UART | ||
| 798 | select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX | ||
| 799 | help | ||
| 800 | Include support for MX53 SMD platform. This includes specific | ||
| 801 | configurations for the board and its peripherals. | ||
| 802 | 735 | ||
| 803 | config MACH_MX53_LOCO | 736 | config SOC_IMX53 |
| 804 | bool "Support MX53 LOCO platforms" | 737 | bool "i.MX53 support" |
| 805 | select SOC_IMX53 | 738 | select SOC_IMX5 |
| 806 | select IMX_HAVE_PLATFORM_IMX2_WDT | 739 | select ARCH_MX5 |
| 807 | select IMX_HAVE_PLATFORM_IMX_I2C | 740 | select ARCH_MX53 |
| 808 | select IMX_HAVE_PLATFORM_IMX_UART | 741 | select HAVE_CAN_FLEXCAN if CAN |
| 809 | select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX | 742 | select PINCTRL |
| 810 | select IMX_HAVE_PLATFORM_GPIO_KEYS | 743 | select PINCTRL_IMX53 |
| 811 | select LEDS_GPIO_REGISTER | ||
| 812 | help | ||
| 813 | Include support for MX53 LOCO platform. This includes specific | ||
| 814 | configurations for the board and its peripherals. | ||
| 815 | 744 | ||
| 816 | config MACH_MX53_ARD | ||
| 817 | bool "Support MX53 ARD platforms" | ||
| 818 | select SOC_IMX53 | ||
| 819 | select IMX_HAVE_PLATFORM_IMX2_WDT | ||
| 820 | select IMX_HAVE_PLATFORM_IMX_I2C | ||
| 821 | select IMX_HAVE_PLATFORM_IMX_UART | ||
| 822 | select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX | ||
| 823 | select IMX_HAVE_PLATFORM_GPIO_KEYS | ||
| 824 | help | 745 | help |
| 825 | Include support for MX53 ARD platform. This includes specific | 746 | This enables support for Freescale i.MX53 processor. |
| 826 | configurations for the board and its peripherals. | ||
| 827 | |||
| 828 | comment "i.MX6 family:" | ||
| 829 | 747 | ||
| 830 | config SOC_IMX6Q | 748 | config SOC_IMX6Q |
| 831 | bool "i.MX6 Quad support" | 749 | bool "i.MX6 Quad support" |
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index d004d37ad9d8..f4c0e757d805 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile | |||
| @@ -83,16 +83,9 @@ endif | |||
| 83 | # i.MX5 based machines | 83 | # i.MX5 based machines |
| 84 | obj-$(CONFIG_MACH_MX51_BABBAGE) += mach-mx51_babbage.o | 84 | obj-$(CONFIG_MACH_MX51_BABBAGE) += mach-mx51_babbage.o |
| 85 | obj-$(CONFIG_MACH_MX51_3DS) += mach-mx51_3ds.o | 85 | obj-$(CONFIG_MACH_MX51_3DS) += mach-mx51_3ds.o |
| 86 | obj-$(CONFIG_MACH_MX53_EVK) += mach-mx53_evk.o | ||
| 87 | obj-$(CONFIG_MACH_MX53_SMD) += mach-mx53_smd.o | ||
| 88 | obj-$(CONFIG_MACH_MX53_LOCO) += mach-mx53_loco.o | ||
| 89 | obj-$(CONFIG_MACH_MX53_ARD) += mach-mx53_ard.o | ||
| 90 | obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += mach-cpuimx51sd.o | 86 | obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += mach-cpuimx51sd.o |
| 91 | obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd51-baseboard.o | 87 | obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd51-baseboard.o |
| 92 | obj-$(CONFIG_MX51_EFIKA_COMMON) += mx51_efika.o | ||
| 93 | obj-$(CONFIG_MACH_MX51_EFIKAMX) += mach-mx51_efikamx.o | ||
| 94 | obj-$(CONFIG_MACH_MX51_EFIKASB) += mach-mx51_efikasb.o | ||
| 95 | obj-$(CONFIG_MACH_MX50_RDP) += mach-mx50_rdp.o | 88 | obj-$(CONFIG_MACH_MX50_RDP) += mach-mx50_rdp.o |
| 96 | 89 | ||
| 97 | obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o | 90 | obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o |
| 98 | obj-$(CONFIG_MACH_IMX53_DT) += imx53-dt.o | 91 | obj-$(CONFIG_SOC_IMX53) += mach-imx53.o |
diff --git a/arch/arm/mach-imx/Makefile.boot b/arch/arm/mach-imx/Makefile.boot index 05541cf4a878..c60967629e27 100644 --- a/arch/arm/mach-imx/Makefile.boot +++ b/arch/arm/mach-imx/Makefile.boot | |||
| @@ -39,8 +39,12 @@ params_phys-$(CONFIG_SOC_IMX6Q) := 0x10000100 | |||
| 39 | initrd_phys-$(CONFIG_SOC_IMX6Q) := 0x10800000 | 39 | initrd_phys-$(CONFIG_SOC_IMX6Q) := 0x10800000 |
| 40 | 40 | ||
| 41 | dtb-$(CONFIG_MACH_IMX51_DT) += imx51-babbage.dtb | 41 | dtb-$(CONFIG_MACH_IMX51_DT) += imx51-babbage.dtb |
| 42 | dtb-$(CONFIG_MACH_IMX53_DT) += imx53-ard.dtb imx53-evk.dtb \ | 42 | |
| 43 | imx53-qsb.dtb imx53-smd.dtb | 43 | dtb-$(CONFIG_SOC_IMX53) += imx53-ard.dtb \ |
| 44 | imx53-evk.dtb \ | ||
| 45 | imx53-qsb.dtb \ | ||
| 46 | imx53-smd.dtb \ | ||
| 47 | |||
| 44 | dtb-$(CONFIG_SOC_IMX6Q) += imx6q-arm2.dtb \ | 48 | dtb-$(CONFIG_SOC_IMX6Q) += imx6q-arm2.dtb \ |
| 45 | imx6q-sabrelite.dtb \ | 49 | imx6q-sabrelite.dtb \ |
| 46 | imx6q-sabresd.dtb \ | 50 | imx6q-sabresd.dtb \ |
diff --git a/arch/arm/mach-imx/clk-imx25.c b/arch/arm/mach-imx/clk-imx25.c index fdd8cc87c9fe..4431a62fff5b 100644 --- a/arch/arm/mach-imx/clk-imx25.c +++ b/arch/arm/mach-imx/clk-imx25.c | |||
| @@ -222,10 +222,8 @@ int __init mx25_clocks_init(void) | |||
| 222 | clk_register_clkdev(clk[lcdc_ipg], "ipg", "imx-fb.0"); | 222 | clk_register_clkdev(clk[lcdc_ipg], "ipg", "imx-fb.0"); |
| 223 | clk_register_clkdev(clk[lcdc_ahb], "ahb", "imx-fb.0"); | 223 | clk_register_clkdev(clk[lcdc_ahb], "ahb", "imx-fb.0"); |
| 224 | clk_register_clkdev(clk[wdt_ipg], NULL, "imx2-wdt.0"); | 224 | clk_register_clkdev(clk[wdt_ipg], NULL, "imx2-wdt.0"); |
| 225 | clk_register_clkdev(clk[ssi1_ipg_per], "per", "imx-ssi.0"); | 225 | clk_register_clkdev(clk[ssi1_ipg], NULL, "imx-ssi.0"); |
| 226 | clk_register_clkdev(clk[ssi1_ipg], "ipg", "imx-ssi.0"); | 226 | clk_register_clkdev(clk[ssi2_ipg], NULL, "imx-ssi.1"); |
| 227 | clk_register_clkdev(clk[ssi2_ipg_per], "per", "imx-ssi.1"); | ||
| 228 | clk_register_clkdev(clk[ssi2_ipg], "ipg", "imx-ssi.1"); | ||
| 229 | clk_register_clkdev(clk[esdhc1_ipg_per], "per", "sdhci-esdhc-imx25.0"); | 227 | clk_register_clkdev(clk[esdhc1_ipg_per], "per", "sdhci-esdhc-imx25.0"); |
| 230 | clk_register_clkdev(clk[esdhc1_ipg], "ipg", "sdhci-esdhc-imx25.0"); | 228 | clk_register_clkdev(clk[esdhc1_ipg], "ipg", "sdhci-esdhc-imx25.0"); |
| 231 | clk_register_clkdev(clk[esdhc1_ahb], "ahb", "sdhci-esdhc-imx25.0"); | 229 | clk_register_clkdev(clk[esdhc1_ahb], "ahb", "sdhci-esdhc-imx25.0"); |
diff --git a/arch/arm/mach-imx/clk-imx35.c b/arch/arm/mach-imx/clk-imx35.c index c6422fb10bae..65fb8bcd86cb 100644 --- a/arch/arm/mach-imx/clk-imx35.c +++ b/arch/arm/mach-imx/clk-imx35.c | |||
| @@ -230,10 +230,8 @@ int __init mx35_clocks_init() | |||
| 230 | clk_register_clkdev(clk[ipu_gate], NULL, "mx3_sdc_fb"); | 230 | clk_register_clkdev(clk[ipu_gate], NULL, "mx3_sdc_fb"); |
| 231 | clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1"); | 231 | clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1"); |
| 232 | clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma"); | 232 | clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma"); |
| 233 | clk_register_clkdev(clk[ipg], "ipg", "imx-ssi.0"); | 233 | clk_register_clkdev(clk[ssi1_gate], NULL, "imx-ssi.0"); |
| 234 | clk_register_clkdev(clk[ssi1_div_post], "per", "imx-ssi.0"); | 234 | clk_register_clkdev(clk[ssi2_gate], NULL, "imx-ssi.1"); |
| 235 | clk_register_clkdev(clk[ipg], "ipg", "imx-ssi.1"); | ||
| 236 | clk_register_clkdev(clk[ssi2_div_post], "per", "imx-ssi.1"); | ||
| 237 | /* i.mx35 has the i.mx21 type uart */ | 235 | /* i.mx35 has the i.mx21 type uart */ |
| 238 | clk_register_clkdev(clk[uart1_gate], "per", "imx21-uart.0"); | 236 | clk_register_clkdev(clk[uart1_gate], "per", "imx21-uart.0"); |
| 239 | clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.0"); | 237 | clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.0"); |
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index 4233d9e3531d..3ec242f3341e 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c | |||
| @@ -157,6 +157,7 @@ enum mx6q_clks { | |||
| 157 | }; | 157 | }; |
| 158 | 158 | ||
| 159 | static struct clk *clk[clk_max]; | 159 | static struct clk *clk[clk_max]; |
| 160 | static struct clk_onecell_data clk_data; | ||
| 160 | 161 | ||
| 161 | static enum mx6q_clks const clks_init_on[] __initconst = { | 162 | static enum mx6q_clks const clks_init_on[] __initconst = { |
| 162 | mmdc_ch0_axi, rom, | 163 | mmdc_ch0_axi, rom, |
| @@ -394,52 +395,24 @@ int __init mx6q_clocks_init(void) | |||
| 394 | pr_err("i.MX6q clk %d: register failed with %ld\n", | 395 | pr_err("i.MX6q clk %d: register failed with %ld\n", |
| 395 | i, PTR_ERR(clk[i])); | 396 | i, PTR_ERR(clk[i])); |
| 396 | 397 | ||
| 398 | clk_data.clks = clk; | ||
| 399 | clk_data.clk_num = ARRAY_SIZE(clk); | ||
| 400 | of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); | ||
| 401 | |||
| 397 | clk_register_clkdev(clk[gpt_ipg], "ipg", "imx-gpt.0"); | 402 | clk_register_clkdev(clk[gpt_ipg], "ipg", "imx-gpt.0"); |
| 398 | clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0"); | 403 | clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0"); |
| 399 | clk_register_clkdev(clk[twd], NULL, "smp_twd"); | 404 | clk_register_clkdev(clk[twd], NULL, "smp_twd"); |
| 400 | clk_register_clkdev(clk[apbh_dma], NULL, "110000.dma-apbh"); | ||
| 401 | clk_register_clkdev(clk[per1_bch], "per1_bch", "112000.gpmi-nand"); | ||
| 402 | clk_register_clkdev(clk[gpmi_bch_apb], "gpmi_bch_apb", "112000.gpmi-nand"); | ||
| 403 | clk_register_clkdev(clk[gpmi_bch], "gpmi_bch", "112000.gpmi-nand"); | ||
| 404 | clk_register_clkdev(clk[gpmi_apb], "gpmi_apb", "112000.gpmi-nand"); | ||
| 405 | clk_register_clkdev(clk[gpmi_io], "gpmi_io", "112000.gpmi-nand"); | ||
| 406 | clk_register_clkdev(clk[usboh3], NULL, "2184000.usb"); | ||
| 407 | clk_register_clkdev(clk[usboh3], NULL, "2184200.usb"); | ||
| 408 | clk_register_clkdev(clk[usboh3], NULL, "2184400.usb"); | ||
| 409 | clk_register_clkdev(clk[usboh3], NULL, "2184600.usb"); | ||
| 410 | clk_register_clkdev(clk[usbphy1], NULL, "20c9000.usbphy"); | ||
| 411 | clk_register_clkdev(clk[usbphy2], NULL, "20ca000.usbphy"); | ||
| 412 | clk_register_clkdev(clk[uart_serial], "per", "2020000.serial"); | ||
| 413 | clk_register_clkdev(clk[uart_ipg], "ipg", "2020000.serial"); | ||
| 414 | clk_register_clkdev(clk[uart_serial], "per", "21e8000.serial"); | ||
| 415 | clk_register_clkdev(clk[uart_ipg], "ipg", "21e8000.serial"); | ||
| 416 | clk_register_clkdev(clk[uart_serial], "per", "21ec000.serial"); | ||
| 417 | clk_register_clkdev(clk[uart_ipg], "ipg", "21ec000.serial"); | ||
| 418 | clk_register_clkdev(clk[uart_serial], "per", "21f0000.serial"); | ||
| 419 | clk_register_clkdev(clk[uart_ipg], "ipg", "21f0000.serial"); | ||
| 420 | clk_register_clkdev(clk[uart_serial], "per", "21f4000.serial"); | ||
| 421 | clk_register_clkdev(clk[uart_ipg], "ipg", "21f4000.serial"); | ||
| 422 | clk_register_clkdev(clk[enet], NULL, "2188000.ethernet"); | ||
| 423 | clk_register_clkdev(clk[usdhc1], NULL, "2190000.usdhc"); | ||
| 424 | clk_register_clkdev(clk[usdhc2], NULL, "2194000.usdhc"); | ||
| 425 | clk_register_clkdev(clk[usdhc3], NULL, "2198000.usdhc"); | ||
| 426 | clk_register_clkdev(clk[usdhc4], NULL, "219c000.usdhc"); | ||
| 427 | clk_register_clkdev(clk[i2c1], NULL, "21a0000.i2c"); | ||
| 428 | clk_register_clkdev(clk[i2c2], NULL, "21a4000.i2c"); | ||
| 429 | clk_register_clkdev(clk[i2c3], NULL, "21a8000.i2c"); | ||
| 430 | clk_register_clkdev(clk[ecspi1], NULL, "2008000.ecspi"); | ||
| 431 | clk_register_clkdev(clk[ecspi2], NULL, "200c000.ecspi"); | ||
| 432 | clk_register_clkdev(clk[ecspi3], NULL, "2010000.ecspi"); | ||
| 433 | clk_register_clkdev(clk[ecspi4], NULL, "2014000.ecspi"); | ||
| 434 | clk_register_clkdev(clk[ecspi5], NULL, "2018000.ecspi"); | ||
| 435 | clk_register_clkdev(clk[sdma], NULL, "20ec000.sdma"); | ||
| 436 | clk_register_clkdev(clk[dummy], NULL, "20bc000.wdog"); | ||
| 437 | clk_register_clkdev(clk[dummy], NULL, "20c0000.wdog"); | ||
| 438 | clk_register_clkdev(clk[ssi1_ipg], NULL, "2028000.ssi"); | ||
| 439 | clk_register_clkdev(clk[cko1_sel], "cko1_sel", NULL); | 405 | clk_register_clkdev(clk[cko1_sel], "cko1_sel", NULL); |
| 440 | clk_register_clkdev(clk[ahb], "ahb", NULL); | 406 | clk_register_clkdev(clk[ahb], "ahb", NULL); |
| 441 | clk_register_clkdev(clk[cko1], "cko1", NULL); | 407 | clk_register_clkdev(clk[cko1], "cko1", NULL); |
| 442 | 408 | ||
| 409 | /* | ||
| 410 | * The gpmi needs 100MHz frequency in the EDO/Sync mode, | ||
| 411 | * We can not get the 100MHz from the pll2_pfd0_352m. | ||
| 412 | * So choose pll2_pfd2_396m as enfc_sel's parent. | ||
| 413 | */ | ||
| 414 | clk_set_parent(clk[enfc_sel], clk[pll2_pfd2_396m]); | ||
| 415 | |||
| 443 | for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) | 416 | for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) |
| 444 | clk_prepare_enable(clk[clks_init_on[i]]); | 417 | clk_prepare_enable(clk[clks_init_on[i]]); |
| 445 | 418 | ||
diff --git a/arch/arm/mach-imx/devices-imx53.h b/arch/arm/mach-imx/devices-imx53.h deleted file mode 100644 index 77e0db96c448..000000000000 --- a/arch/arm/mach-imx/devices-imx53.h +++ /dev/null | |||
| @@ -1,48 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2010 Yong Shen. <Yong.Shen@linaro.org> | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify it under | ||
| 5 | * the terms of the GNU General Public License version 2 as published by the | ||
| 6 | * Free Software Foundation. | ||
| 7 | */ | ||
| 8 | #include <mach/mx53.h> | ||
| 9 | #include <mach/devices-common.h> | ||
| 10 | |||
| 11 | extern const struct imx_fec_data imx53_fec_data; | ||
| 12 | #define imx53_add_fec(pdata) \ | ||
| 13 | imx_add_fec(&imx53_fec_data, pdata) | ||
| 14 | |||
| 15 | extern const struct imx_imx_uart_1irq_data imx53_imx_uart_data[]; | ||
| 16 | #define imx53_add_imx_uart(id, pdata) \ | ||
| 17 | imx_add_imx_uart_1irq(&imx53_imx_uart_data[id], pdata) | ||
| 18 | |||
| 19 | |||
| 20 | extern const struct imx_imx_i2c_data imx53_imx_i2c_data[]; | ||
| 21 | #define imx53_add_imx_i2c(id, pdata) \ | ||
| 22 | imx_add_imx_i2c(&imx53_imx_i2c_data[id], pdata) | ||
| 23 | |||
| 24 | extern const struct imx_sdhci_esdhc_imx_data imx53_sdhci_esdhc_imx_data[]; | ||
| 25 | #define imx53_add_sdhci_esdhc_imx(id, pdata) \ | ||
| 26 | imx_add_sdhci_esdhc_imx(&imx53_sdhci_esdhc_imx_data[id], pdata) | ||
| 27 | |||
| 28 | extern const struct imx_spi_imx_data imx53_ecspi_data[]; | ||
| 29 | #define imx53_add_ecspi(id, pdata) \ | ||
| 30 | imx_add_spi_imx(&imx53_ecspi_data[id], pdata) | ||
| 31 | |||
| 32 | extern const struct imx_imx2_wdt_data imx53_imx2_wdt_data[]; | ||
| 33 | #define imx53_add_imx2_wdt(id) \ | ||
| 34 | imx_add_imx2_wdt(&imx53_imx2_wdt_data[id]) | ||
| 35 | |||
| 36 | extern const struct imx_imx_ssi_data imx53_imx_ssi_data[]; | ||
| 37 | #define imx53_add_imx_ssi(id, pdata) \ | ||
| 38 | imx_add_imx_ssi(&imx53_imx_ssi_data[id], pdata) | ||
| 39 | |||
| 40 | extern const struct imx_imx_keypad_data imx53_imx_keypad_data; | ||
| 41 | #define imx53_add_imx_keypad(pdata) \ | ||
| 42 | imx_add_imx_keypad(&imx53_imx_keypad_data, pdata) | ||
| 43 | |||
| 44 | extern const struct imx_pata_imx_data imx53_pata_imx_data; | ||
| 45 | #define imx53_add_pata_imx() \ | ||
| 46 | imx_add_pata_imx(&imx53_pata_imx_data) | ||
| 47 | |||
| 48 | extern struct platform_device *__init imx53_add_ahci_imx(void); | ||
diff --git a/arch/arm/mach-imx/efika.h b/arch/arm/mach-imx/efika.h deleted file mode 100644 index 014aa985faae..000000000000 --- a/arch/arm/mach-imx/efika.h +++ /dev/null | |||
| @@ -1,10 +0,0 @@ | |||
| 1 | #ifndef _EFIKA_H | ||
| 2 | #define _EFIKA_H | ||
| 3 | |||
| 4 | #define EFIKA_WLAN_EN IMX_GPIO_NR(2, 16) | ||
| 5 | #define EFIKA_WLAN_RESET IMX_GPIO_NR(2, 10) | ||
| 6 | #define EFIKA_USB_PHY_RESET IMX_GPIO_NR(2, 9) | ||
| 7 | |||
| 8 | void __init efika_board_common_init(void); | ||
| 9 | |||
| 10 | #endif | ||
diff --git a/arch/arm/mach-imx/imx51-dt.c b/arch/arm/mach-imx/imx51-dt.c index d4067fe36357..f233b4bb2342 100644 --- a/arch/arm/mach-imx/imx51-dt.c +++ b/arch/arm/mach-imx/imx51-dt.c | |||
| @@ -13,7 +13,6 @@ | |||
| 13 | #include <linux/irq.h> | 13 | #include <linux/irq.h> |
| 14 | #include <linux/of_irq.h> | 14 | #include <linux/of_irq.h> |
| 15 | #include <linux/of_platform.h> | 15 | #include <linux/of_platform.h> |
| 16 | #include <linux/pinctrl/machine.h> | ||
| 17 | #include <asm/mach/arch.h> | 16 | #include <asm/mach/arch.h> |
| 18 | #include <asm/mach/time.h> | 17 | #include <asm/mach/time.h> |
| 19 | #include <mach/common.h> | 18 | #include <mach/common.h> |
| @@ -44,27 +43,8 @@ static const struct of_dev_auxdata imx51_auxdata_lookup[] __initconst = { | |||
| 44 | { /* sentinel */ } | 43 | { /* sentinel */ } |
| 45 | }; | 44 | }; |
| 46 | 45 | ||
| 47 | static const struct of_device_id imx51_iomuxc_of_match[] __initconst = { | ||
| 48 | { .compatible = "fsl,imx51-iomuxc-babbage", .data = imx51_babbage_common_init, }, | ||
| 49 | { /* sentinel */ } | ||
| 50 | }; | ||
| 51 | |||
| 52 | static void __init imx51_dt_init(void) | 46 | static void __init imx51_dt_init(void) |
| 53 | { | 47 | { |
| 54 | struct device_node *node; | ||
| 55 | const struct of_device_id *of_id; | ||
| 56 | void (*func)(void); | ||
| 57 | |||
| 58 | pinctrl_provide_dummies(); | ||
| 59 | |||
| 60 | node = of_find_matching_node(NULL, imx51_iomuxc_of_match); | ||
| 61 | if (node) { | ||
| 62 | of_id = of_match_node(imx51_iomuxc_of_match, node); | ||
| 63 | func = of_id->data; | ||
| 64 | func(); | ||
| 65 | of_node_put(node); | ||
| 66 | } | ||
| 67 | |||
| 68 | of_platform_populate(NULL, of_default_bus_match_table, | 48 | of_platform_populate(NULL, of_default_bus_match_table, |
| 69 | imx51_auxdata_lookup, NULL); | 49 | imx51_auxdata_lookup, NULL); |
| 70 | } | 50 | } |
| @@ -79,7 +59,6 @@ static struct sys_timer imx51_timer = { | |||
| 79 | }; | 59 | }; |
| 80 | 60 | ||
| 81 | static const char *imx51_dt_board_compat[] __initdata = { | 61 | static const char *imx51_dt_board_compat[] __initdata = { |
| 82 | "fsl,imx51-babbage", | ||
| 83 | "fsl,imx51", | 62 | "fsl,imx51", |
| 84 | NULL | 63 | NULL |
| 85 | }; | 64 | }; |
diff --git a/arch/arm/mach-imx/imx53-dt.c b/arch/arm/mach-imx/mach-imx53.c index 1b7a2fc36591..29711e95579f 100644 --- a/arch/arm/mach-imx/imx53-dt.c +++ b/arch/arm/mach-imx/mach-imx53.c | |||
| @@ -17,7 +17,6 @@ | |||
| 17 | #include <linux/irq.h> | 17 | #include <linux/irq.h> |
| 18 | #include <linux/of_irq.h> | 18 | #include <linux/of_irq.h> |
| 19 | #include <linux/of_platform.h> | 19 | #include <linux/of_platform.h> |
| 20 | #include <linux/pinctrl/machine.h> | ||
| 21 | #include <asm/mach/arch.h> | 20 | #include <asm/mach/arch.h> |
| 22 | #include <asm/mach/time.h> | 21 | #include <asm/mach/time.h> |
| 23 | #include <mach/common.h> | 22 | #include <mach/common.h> |
| @@ -51,14 +50,6 @@ static const struct of_dev_auxdata imx53_auxdata_lookup[] __initconst = { | |||
| 51 | { /* sentinel */ } | 50 | { /* sentinel */ } |
| 52 | }; | 51 | }; |
| 53 | 52 | ||
| 54 | static const struct of_device_id imx53_iomuxc_of_match[] __initconst = { | ||
| 55 | { .compatible = "fsl,imx53-iomuxc-ard", .data = imx53_ard_common_init, }, | ||
| 56 | { .compatible = "fsl,imx53-iomuxc-evk", .data = imx53_evk_common_init, }, | ||
| 57 | { .compatible = "fsl,imx53-iomuxc-qsb", .data = imx53_qsb_common_init, }, | ||
| 58 | { .compatible = "fsl,imx53-iomuxc-smd", .data = imx53_smd_common_init, }, | ||
| 59 | { /* sentinel */ } | ||
| 60 | }; | ||
| 61 | |||
| 62 | static void __init imx53_qsb_init(void) | 53 | static void __init imx53_qsb_init(void) |
| 63 | { | 54 | { |
| 64 | struct clk *clk; | 55 | struct clk *clk; |
| @@ -74,20 +65,6 @@ static void __init imx53_qsb_init(void) | |||
| 74 | 65 | ||
| 75 | static void __init imx53_dt_init(void) | 66 | static void __init imx53_dt_init(void) |
| 76 | { | 67 | { |
| 77 | struct device_node *node; | ||
| 78 | const struct of_device_id *of_id; | ||
| 79 | void (*func)(void); | ||
| 80 | |||
| 81 | pinctrl_provide_dummies(); | ||
| 82 | |||
| 83 | node = of_find_matching_node(NULL, imx53_iomuxc_of_match); | ||
| 84 | if (node) { | ||
| 85 | of_id = of_match_node(imx53_iomuxc_of_match, node); | ||
| 86 | func = of_id->data; | ||
| 87 | func(); | ||
| 88 | of_node_put(node); | ||
| 89 | } | ||
| 90 | |||
| 91 | if (of_machine_is_compatible("fsl,imx53-qsb")) | 68 | if (of_machine_is_compatible("fsl,imx53-qsb")) |
| 92 | imx53_qsb_init(); | 69 | imx53_qsb_init(); |
| 93 | 70 | ||
| @@ -105,10 +82,6 @@ static struct sys_timer imx53_timer = { | |||
| 105 | }; | 82 | }; |
| 106 | 83 | ||
| 107 | static const char *imx53_dt_board_compat[] __initdata = { | 84 | static const char *imx53_dt_board_compat[] __initdata = { |
| 108 | "fsl,imx53-ard", | ||
| 109 | "fsl,imx53-evk", | ||
| 110 | "fsl,imx53-qsb", | ||
| 111 | "fsl,imx53-smd", | ||
| 112 | "fsl,imx53", | 85 | "fsl,imx53", |
| 113 | NULL | 86 | NULL |
| 114 | }; | 87 | }; |
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c index 045b3f6a387d..692b4b143bb1 100644 --- a/arch/arm/mach-imx/mach-imx6q.c +++ b/arch/arm/mach-imx/mach-imx6q.c | |||
| @@ -22,7 +22,6 @@ | |||
| 22 | #include <linux/of_address.h> | 22 | #include <linux/of_address.h> |
| 23 | #include <linux/of_irq.h> | 23 | #include <linux/of_irq.h> |
| 24 | #include <linux/of_platform.h> | 24 | #include <linux/of_platform.h> |
| 25 | #include <linux/pinctrl/machine.h> | ||
| 26 | #include <linux/phy.h> | 25 | #include <linux/phy.h> |
| 27 | #include <linux/micrel_phy.h> | 26 | #include <linux/micrel_phy.h> |
| 28 | #include <linux/mfd/anatop.h> | 27 | #include <linux/mfd/anatop.h> |
| @@ -100,7 +99,6 @@ static void __init imx6q_sabrelite_cko1_setup(void) | |||
| 100 | clk_set_parent(cko1_sel, ahb); | 99 | clk_set_parent(cko1_sel, ahb); |
| 101 | rate = clk_round_rate(cko1, 16000000); | 100 | rate = clk_round_rate(cko1, 16000000); |
| 102 | clk_set_rate(cko1, rate); | 101 | clk_set_rate(cko1, rate); |
| 103 | clk_register_clkdev(cko1, NULL, "0-000a"); | ||
| 104 | put_clk: | 102 | put_clk: |
| 105 | if (!IS_ERR(cko1_sel)) | 103 | if (!IS_ERR(cko1_sel)) |
| 106 | clk_put(cko1_sel); | 104 | clk_put(cko1_sel); |
| @@ -159,12 +157,6 @@ static void __init imx6q_usb_init(void) | |||
| 159 | 157 | ||
| 160 | static void __init imx6q_init_machine(void) | 158 | static void __init imx6q_init_machine(void) |
| 161 | { | 159 | { |
| 162 | /* | ||
| 163 | * This should be removed when all imx6q boards have pinctrl | ||
| 164 | * states for devices defined in device tree. | ||
| 165 | */ | ||
| 166 | pinctrl_provide_dummies(); | ||
| 167 | |||
| 168 | if (of_machine_is_compatible("fsl,imx6q-sabrelite")) | 160 | if (of_machine_is_compatible("fsl,imx6q-sabrelite")) |
| 169 | imx6q_sabrelite_init(); | 161 | imx6q_sabrelite_init(); |
| 170 | 162 | ||
| @@ -218,9 +210,6 @@ static struct sys_timer imx6q_timer = { | |||
| 218 | }; | 210 | }; |
| 219 | 211 | ||
| 220 | static const char *imx6q_dt_compat[] __initdata = { | 212 | static const char *imx6q_dt_compat[] __initdata = { |
| 221 | "fsl,imx6q-arm2", | ||
| 222 | "fsl,imx6q-sabrelite", | ||
| 223 | "fsl,imx6q-sabresd", | ||
| 224 | "fsl,imx6q", | 213 | "fsl,imx6q", |
| 225 | NULL, | 214 | NULL, |
| 226 | }; | 215 | }; |
diff --git a/arch/arm/mach-imx/mach-mx51_efikamx.c b/arch/arm/mach-imx/mach-mx51_efikamx.c deleted file mode 100644 index 8d09c0126cab..000000000000 --- a/arch/arm/mach-imx/mach-mx51_efikamx.c +++ /dev/null | |||
| @@ -1,300 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2010 Linaro Limited | ||
| 3 | * | ||
| 4 | * based on code from the following | ||
| 5 | * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 6 | * Copyright 2009-2010 Pegatron Corporation. All Rights Reserved. | ||
| 7 | * Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved. | ||
| 8 | * | ||
| 9 | * The code contained herein is licensed under the GNU General Public | ||
| 10 | * License. You may obtain a copy of the GNU General Public License | ||
| 11 | * Version 2 or later at the following locations: | ||
| 12 | * | ||
| 13 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 14 | * http://www.gnu.org/copyleft/gpl.html | ||
| 15 | */ | ||
| 16 | |||
| 17 | #include <linux/init.h> | ||
| 18 | #include <linux/platform_device.h> | ||
| 19 | #include <linux/i2c.h> | ||
| 20 | #include <linux/gpio.h> | ||
| 21 | #include <linux/leds.h> | ||
| 22 | #include <linux/input.h> | ||
| 23 | #include <linux/delay.h> | ||
| 24 | #include <linux/io.h> | ||
| 25 | #include <linux/spi/flash.h> | ||
| 26 | #include <linux/spi/spi.h> | ||
| 27 | #include <linux/mfd/mc13892.h> | ||
| 28 | #include <linux/regulator/machine.h> | ||
| 29 | #include <linux/regulator/consumer.h> | ||
| 30 | |||
| 31 | #include <mach/common.h> | ||
| 32 | #include <mach/hardware.h> | ||
| 33 | #include <mach/iomux-mx51.h> | ||
| 34 | |||
| 35 | #include <asm/setup.h> | ||
| 36 | #include <asm/system_info.h> | ||
| 37 | #include <asm/mach-types.h> | ||
| 38 | #include <asm/mach/arch.h> | ||
| 39 | #include <asm/mach/time.h> | ||
| 40 | |||
| 41 | #include "devices-imx51.h" | ||
| 42 | #include "efika.h" | ||
| 43 | |||
| 44 | #define EFIKAMX_PCBID0 IMX_GPIO_NR(3, 16) | ||
| 45 | #define EFIKAMX_PCBID1 IMX_GPIO_NR(3, 17) | ||
| 46 | #define EFIKAMX_PCBID2 IMX_GPIO_NR(3, 11) | ||
| 47 | |||
| 48 | #define EFIKAMX_BLUE_LED IMX_GPIO_NR(3, 13) | ||
| 49 | #define EFIKAMX_GREEN_LED IMX_GPIO_NR(3, 14) | ||
| 50 | #define EFIKAMX_RED_LED IMX_GPIO_NR(3, 15) | ||
| 51 | |||
| 52 | #define EFIKAMX_POWER_KEY IMX_GPIO_NR(2, 31) | ||
| 53 | |||
| 54 | /* board 1.1 doesn't have same reset gpio */ | ||
| 55 | #define EFIKAMX_RESET1_1 IMX_GPIO_NR(3, 2) | ||
| 56 | #define EFIKAMX_RESET IMX_GPIO_NR(1, 4) | ||
| 57 | |||
| 58 | #define EFIKAMX_POWEROFF IMX_GPIO_NR(4, 13) | ||
| 59 | |||
| 60 | #define EFIKAMX_PMIC IMX_GPIO_NR(1, 6) | ||
| 61 | |||
| 62 | /* the pci ids pin have pull up. they're driven low according to board id */ | ||
| 63 | #define MX51_PAD_PCBID0 IOMUX_PAD(0x518, 0x130, 3, 0x0, 0, PAD_CTL_PUS_100K_UP) | ||
| 64 | #define MX51_PAD_PCBID1 IOMUX_PAD(0x51C, 0x134, 3, 0x0, 0, PAD_CTL_PUS_100K_UP) | ||
| 65 | #define MX51_PAD_PCBID2 IOMUX_PAD(0x504, 0x128, 3, 0x0, 0, PAD_CTL_PUS_100K_UP) | ||
| 66 | #define MX51_PAD_PWRKEY IOMUX_PAD(0x48c, 0x0f8, 1, 0x0, 0, PAD_CTL_PUS_100K_UP | PAD_CTL_PKE) | ||
| 67 | |||
| 68 | static iomux_v3_cfg_t mx51efikamx_pads[] = { | ||
| 69 | /* board id */ | ||
| 70 | MX51_PAD_PCBID0, | ||
| 71 | MX51_PAD_PCBID1, | ||
| 72 | MX51_PAD_PCBID2, | ||
| 73 | |||
| 74 | /* leds */ | ||
| 75 | MX51_PAD_CSI1_D9__GPIO3_13, | ||
| 76 | MX51_PAD_CSI1_VSYNC__GPIO3_14, | ||
| 77 | MX51_PAD_CSI1_HSYNC__GPIO3_15, | ||
| 78 | |||
| 79 | /* power key */ | ||
| 80 | MX51_PAD_PWRKEY, | ||
| 81 | |||
| 82 | /* reset */ | ||
| 83 | MX51_PAD_DI1_PIN13__GPIO3_2, | ||
| 84 | MX51_PAD_GPIO1_4__GPIO1_4, | ||
| 85 | |||
| 86 | /* power off */ | ||
| 87 | MX51_PAD_CSI2_VSYNC__GPIO4_13, | ||
| 88 | }; | ||
| 89 | |||
| 90 | /* PCBID2 PCBID1 PCBID0 STATE | ||
| 91 | 1 1 1 ER1:rev1.1 | ||
| 92 | 1 1 0 ER2:rev1.2 | ||
| 93 | 1 0 1 ER3:rev1.3 | ||
| 94 | 1 0 0 ER4:rev1.4 | ||
| 95 | */ | ||
| 96 | static void __init mx51_efikamx_board_id(void) | ||
| 97 | { | ||
| 98 | int id; | ||
| 99 | |||
| 100 | /* things are taking time to settle */ | ||
| 101 | msleep(150); | ||
| 102 | |||
| 103 | gpio_request(EFIKAMX_PCBID0, "pcbid0"); | ||
| 104 | gpio_direction_input(EFIKAMX_PCBID0); | ||
| 105 | gpio_request(EFIKAMX_PCBID1, "pcbid1"); | ||
| 106 | gpio_direction_input(EFIKAMX_PCBID1); | ||
| 107 | gpio_request(EFIKAMX_PCBID2, "pcbid2"); | ||
| 108 | gpio_direction_input(EFIKAMX_PCBID2); | ||
| 109 | |||
| 110 | id = gpio_get_value(EFIKAMX_PCBID0) ? 1 : 0; | ||
| 111 | id |= (gpio_get_value(EFIKAMX_PCBID1) ? 1 : 0) << 1; | ||
| 112 | id |= (gpio_get_value(EFIKAMX_PCBID2) ? 1 : 0) << 2; | ||
| 113 | |||
| 114 | switch (id) { | ||
| 115 | case 7: | ||
| 116 | system_rev = 0x11; | ||
| 117 | break; | ||
| 118 | case 6: | ||
| 119 | system_rev = 0x12; | ||
| 120 | break; | ||
| 121 | case 5: | ||
| 122 | system_rev = 0x13; | ||
| 123 | break; | ||
| 124 | case 4: | ||
| 125 | system_rev = 0x14; | ||
| 126 | break; | ||
| 127 | default: | ||
| 128 | system_rev = 0x10; | ||
| 129 | break; | ||
| 130 | } | ||
| 131 | |||
| 132 | if ((system_rev == 0x10) | ||
| 133 | || (system_rev == 0x12) | ||
| 134 | || (system_rev == 0x14)) { | ||
| 135 | printk(KERN_WARNING | ||
| 136 | "EfikaMX: Unsupported board revision 1.%u!\n", | ||
| 137 | system_rev & 0xf); | ||
| 138 | } | ||
| 139 | } | ||
| 140 | |||
| 141 | static struct gpio_led mx51_efikamx_leds[] __initdata = { | ||
| 142 | { | ||
| 143 | .name = "efikamx:green", | ||
| 144 | .default_trigger = "default-on", | ||
| 145 | .gpio = EFIKAMX_GREEN_LED, | ||
| 146 | }, | ||
| 147 | { | ||
| 148 | .name = "efikamx:red", | ||
| 149 | .default_trigger = "ide-disk", | ||
| 150 | .gpio = EFIKAMX_RED_LED, | ||
| 151 | }, | ||
| 152 | { | ||
| 153 | .name = "efikamx:blue", | ||
| 154 | .default_trigger = "mmc0", | ||
| 155 | .gpio = EFIKAMX_BLUE_LED, | ||
| 156 | }, | ||
| 157 | }; | ||
| 158 | |||
| 159 | static const struct gpio_led_platform_data | ||
| 160 | mx51_efikamx_leds_data __initconst = { | ||
| 161 | .leds = mx51_efikamx_leds, | ||
| 162 | .num_leds = ARRAY_SIZE(mx51_efikamx_leds), | ||
| 163 | }; | ||
| 164 | |||
| 165 | static struct esdhc_platform_data sd_pdata = { | ||
| 166 | .cd_type = ESDHC_CD_CONTROLLER, | ||
| 167 | .wp_type = ESDHC_WP_CONTROLLER, | ||
| 168 | }; | ||
| 169 | |||
| 170 | static struct gpio_keys_button mx51_efikamx_powerkey[] = { | ||
| 171 | { | ||
| 172 | .code = KEY_POWER, | ||
| 173 | .gpio = EFIKAMX_POWER_KEY, | ||
| 174 | .type = EV_PWR, | ||
| 175 | .desc = "Power Button (CM)", | ||
| 176 | .wakeup = 1, | ||
| 177 | .debounce_interval = 10, /* ms */ | ||
| 178 | }, | ||
| 179 | }; | ||
| 180 | |||
| 181 | static const struct gpio_keys_platform_data mx51_efikamx_powerkey_data __initconst = { | ||
| 182 | .buttons = mx51_efikamx_powerkey, | ||
| 183 | .nbuttons = ARRAY_SIZE(mx51_efikamx_powerkey), | ||
| 184 | }; | ||
| 185 | |||
| 186 | static void mx51_efikamx_restart(char mode, const char *cmd) | ||
| 187 | { | ||
| 188 | if (system_rev == 0x11) | ||
| 189 | gpio_direction_output(EFIKAMX_RESET1_1, 0); | ||
| 190 | else | ||
| 191 | gpio_direction_output(EFIKAMX_RESET, 0); | ||
| 192 | } | ||
| 193 | |||
| 194 | static struct regulator *pwgt1, *pwgt2, *coincell; | ||
| 195 | |||
| 196 | static void mx51_efikamx_power_off(void) | ||
| 197 | { | ||
| 198 | if (!IS_ERR(coincell)) | ||
| 199 | regulator_disable(coincell); | ||
| 200 | |||
| 201 | if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) { | ||
| 202 | regulator_disable(pwgt2); | ||
| 203 | regulator_disable(pwgt1); | ||
| 204 | } | ||
| 205 | gpio_direction_output(EFIKAMX_POWEROFF, 1); | ||
| 206 | } | ||
| 207 | |||
| 208 | static int __init mx51_efikamx_power_init(void) | ||
| 209 | { | ||
| 210 | pwgt1 = regulator_get(NULL, "pwgt1"); | ||
| 211 | pwgt2 = regulator_get(NULL, "pwgt2"); | ||
| 212 | if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) { | ||
| 213 | regulator_enable(pwgt1); | ||
| 214 | regulator_enable(pwgt2); | ||
| 215 | } | ||
| 216 | gpio_request(EFIKAMX_POWEROFF, "poweroff"); | ||
| 217 | pm_power_off = mx51_efikamx_power_off; | ||
| 218 | |||
| 219 | /* enable coincell charger. maybe need a small power driver ? */ | ||
| 220 | coincell = regulator_get(NULL, "coincell"); | ||
| 221 | if (!IS_ERR(coincell)) { | ||
| 222 | regulator_set_voltage(coincell, 3000000, 3000000); | ||
| 223 | regulator_enable(coincell); | ||
| 224 | } | ||
| 225 | |||
| 226 | regulator_has_full_constraints(); | ||
| 227 | |||
| 228 | return 0; | ||
| 229 | } | ||
| 230 | |||
| 231 | static void __init mx51_efikamx_init_late(void) | ||
| 232 | { | ||
| 233 | imx51_init_late(); | ||
| 234 | mx51_efikamx_power_init(); | ||
| 235 | } | ||
| 236 | |||
| 237 | static void __init mx51_efikamx_init(void) | ||
| 238 | { | ||
| 239 | imx51_soc_init(); | ||
| 240 | |||
| 241 | mxc_iomux_v3_setup_multiple_pads(mx51efikamx_pads, | ||
| 242 | ARRAY_SIZE(mx51efikamx_pads)); | ||
| 243 | efika_board_common_init(); | ||
| 244 | |||
| 245 | mx51_efikamx_board_id(); | ||
| 246 | |||
| 247 | /* on < 1.2 boards both SD controllers are used */ | ||
| 248 | if (system_rev < 0x12) { | ||
| 249 | imx51_add_sdhci_esdhc_imx(0, NULL); | ||
| 250 | imx51_add_sdhci_esdhc_imx(1, &sd_pdata); | ||
| 251 | mx51_efikamx_leds[2].default_trigger = "mmc1"; | ||
| 252 | } else | ||
| 253 | imx51_add_sdhci_esdhc_imx(0, &sd_pdata); | ||
| 254 | |||
| 255 | gpio_led_register_device(-1, &mx51_efikamx_leds_data); | ||
| 256 | imx_add_gpio_keys(&mx51_efikamx_powerkey_data); | ||
| 257 | |||
| 258 | if (system_rev == 0x11) { | ||
| 259 | gpio_request(EFIKAMX_RESET1_1, "reset"); | ||
| 260 | gpio_direction_output(EFIKAMX_RESET1_1, 1); | ||
| 261 | } else { | ||
| 262 | gpio_request(EFIKAMX_RESET, "reset"); | ||
| 263 | gpio_direction_output(EFIKAMX_RESET, 1); | ||
| 264 | } | ||
| 265 | |||
| 266 | /* | ||
| 267 | * enable wifi by default only on mx | ||
| 268 | * sb and mx have same wlan pin but the value to enable it are | ||
| 269 | * different :/ | ||
| 270 | */ | ||
| 271 | gpio_request(EFIKA_WLAN_EN, "wlan_en"); | ||
| 272 | gpio_direction_output(EFIKA_WLAN_EN, 0); | ||
| 273 | msleep(10); | ||
| 274 | |||
| 275 | gpio_request(EFIKA_WLAN_RESET, "wlan_rst"); | ||
| 276 | gpio_direction_output(EFIKA_WLAN_RESET, 0); | ||
| 277 | msleep(10); | ||
| 278 | gpio_set_value(EFIKA_WLAN_RESET, 1); | ||
| 279 | } | ||
| 280 | |||
| 281 | static void __init mx51_efikamx_timer_init(void) | ||
| 282 | { | ||
| 283 | mx51_clocks_init(32768, 24000000, 22579200, 24576000); | ||
| 284 | } | ||
| 285 | |||
| 286 | static struct sys_timer mx51_efikamx_timer = { | ||
| 287 | .init = mx51_efikamx_timer_init, | ||
| 288 | }; | ||
| 289 | |||
| 290 | MACHINE_START(MX51_EFIKAMX, "Genesi Efika MX (Smarttop)") | ||
| 291 | .atag_offset = 0x100, | ||
| 292 | .map_io = mx51_map_io, | ||
| 293 | .init_early = imx51_init_early, | ||
| 294 | .init_irq = mx51_init_irq, | ||
| 295 | .handle_irq = imx51_handle_irq, | ||
| 296 | .timer = &mx51_efikamx_timer, | ||
| 297 | .init_machine = mx51_efikamx_init, | ||
| 298 | .init_late = mx51_efikamx_init_late, | ||
| 299 | .restart = mx51_efikamx_restart, | ||
| 300 | MACHINE_END | ||
diff --git a/arch/arm/mach-imx/mach-mx51_efikasb.c b/arch/arm/mach-imx/mach-mx51_efikasb.c deleted file mode 100644 index fdbd181b97ef..000000000000 --- a/arch/arm/mach-imx/mach-mx51_efikasb.c +++ /dev/null | |||
| @@ -1,296 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) Arnaud Patard <arnaud.patard@rtp-net.org> | ||
| 3 | * | ||
| 4 | * based on code from the following | ||
| 5 | * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 6 | * Copyright 2009-2010 Pegatron Corporation. All Rights Reserved. | ||
| 7 | * Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved. | ||
| 8 | * | ||
| 9 | * The code contained herein is licensed under the GNU General Public | ||
| 10 | * License. You may obtain a copy of the GNU General Public License | ||
| 11 | * Version 2 or later at the following locations: | ||
| 12 | * | ||
| 13 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 14 | * http://www.gnu.org/copyleft/gpl.html | ||
| 15 | */ | ||
| 16 | |||
| 17 | #include <linux/init.h> | ||
| 18 | #include <linux/platform_device.h> | ||
| 19 | #include <linux/i2c.h> | ||
| 20 | #include <linux/gpio.h> | ||
| 21 | #include <linux/leds.h> | ||
| 22 | #include <linux/input.h> | ||
| 23 | #include <linux/delay.h> | ||
| 24 | #include <linux/io.h> | ||
| 25 | #include <linux/spi/flash.h> | ||
| 26 | #include <linux/spi/spi.h> | ||
| 27 | #include <linux/mfd/mc13892.h> | ||
| 28 | #include <linux/regulator/machine.h> | ||
| 29 | #include <linux/regulator/consumer.h> | ||
| 30 | #include <linux/usb/otg.h> | ||
| 31 | #include <linux/usb/ulpi.h> | ||
| 32 | #include <mach/ulpi.h> | ||
| 33 | |||
| 34 | #include <mach/common.h> | ||
| 35 | #include <mach/hardware.h> | ||
| 36 | #include <mach/iomux-mx51.h> | ||
| 37 | |||
| 38 | #include <asm/setup.h> | ||
| 39 | #include <asm/system_info.h> | ||
| 40 | #include <asm/mach-types.h> | ||
| 41 | #include <asm/mach/arch.h> | ||
| 42 | #include <asm/mach/time.h> | ||
| 43 | |||
| 44 | #include "devices-imx51.h" | ||
| 45 | #include "efika.h" | ||
| 46 | |||
| 47 | #define EFIKASB_USBH2_STP IMX_GPIO_NR(2, 20) | ||
| 48 | #define EFIKASB_GREEN_LED IMX_GPIO_NR(1, 3) | ||
| 49 | #define EFIKASB_WHITE_LED IMX_GPIO_NR(2, 25) | ||
| 50 | #define EFIKASB_PCBID0 IMX_GPIO_NR(2, 28) | ||
| 51 | #define EFIKASB_PCBID1 IMX_GPIO_NR(2, 29) | ||
| 52 | #define EFIKASB_PWRKEY IMX_GPIO_NR(2, 31) | ||
| 53 | #define EFIKASB_LID IMX_GPIO_NR(3, 14) | ||
| 54 | #define EFIKASB_POWEROFF IMX_GPIO_NR(4, 13) | ||
| 55 | #define EFIKASB_RFKILL IMX_GPIO_NR(3, 1) | ||
| 56 | |||
| 57 | #define MX51_PAD_PWRKEY IOMUX_PAD(0x48c, 0x0f8, 1, 0x0, 0, PAD_CTL_PUS_100K_UP | PAD_CTL_PKE) | ||
| 58 | #define MX51_PAD_SD1_CD IOMUX_PAD(0x47c, 0x0e8, 1, __NA_, 0, MX51_ESDHC_PAD_CTRL) | ||
| 59 | |||
| 60 | static iomux_v3_cfg_t mx51efikasb_pads[] = { | ||
| 61 | /* USB HOST2 */ | ||
| 62 | MX51_PAD_EIM_D16__USBH2_DATA0, | ||
| 63 | MX51_PAD_EIM_D17__USBH2_DATA1, | ||
| 64 | MX51_PAD_EIM_D18__USBH2_DATA2, | ||
| 65 | MX51_PAD_EIM_D19__USBH2_DATA3, | ||
| 66 | MX51_PAD_EIM_D20__USBH2_DATA4, | ||
| 67 | MX51_PAD_EIM_D21__USBH2_DATA5, | ||
| 68 | MX51_PAD_EIM_D22__USBH2_DATA6, | ||
| 69 | MX51_PAD_EIM_D23__USBH2_DATA7, | ||
| 70 | MX51_PAD_EIM_A24__USBH2_CLK, | ||
| 71 | MX51_PAD_EIM_A25__USBH2_DIR, | ||
| 72 | MX51_PAD_EIM_A26__USBH2_STP, | ||
| 73 | MX51_PAD_EIM_A27__USBH2_NXT, | ||
| 74 | |||
| 75 | /* leds */ | ||
| 76 | MX51_PAD_EIM_CS0__GPIO2_25, | ||
| 77 | MX51_PAD_GPIO1_3__GPIO1_3, | ||
| 78 | |||
| 79 | /* pcb id */ | ||
| 80 | MX51_PAD_EIM_CS3__GPIO2_28, | ||
| 81 | MX51_PAD_EIM_CS4__GPIO2_29, | ||
| 82 | |||
| 83 | /* lid */ | ||
| 84 | MX51_PAD_CSI1_VSYNC__GPIO3_14, | ||
| 85 | |||
| 86 | /* power key*/ | ||
| 87 | MX51_PAD_PWRKEY, | ||
| 88 | |||
| 89 | /* wifi/bt button */ | ||
| 90 | MX51_PAD_DI1_PIN12__GPIO3_1, | ||
| 91 | |||
| 92 | /* power off */ | ||
| 93 | MX51_PAD_CSI2_VSYNC__GPIO4_13, | ||
| 94 | |||
| 95 | /* wdog reset */ | ||
| 96 | MX51_PAD_GPIO1_4__WDOG1_WDOG_B, | ||
| 97 | |||
| 98 | /* BT */ | ||
| 99 | MX51_PAD_EIM_A17__GPIO2_11, | ||
| 100 | |||
| 101 | MX51_PAD_SD1_CD, | ||
| 102 | }; | ||
| 103 | |||
| 104 | static int initialize_usbh2_port(struct platform_device *pdev) | ||
| 105 | { | ||
| 106 | iomux_v3_cfg_t usbh2stp = MX51_PAD_EIM_A26__USBH2_STP; | ||
| 107 | iomux_v3_cfg_t usbh2gpio = MX51_PAD_EIM_A26__GPIO2_20; | ||
| 108 | |||
| 109 | mxc_iomux_v3_setup_pad(usbh2gpio); | ||
| 110 | gpio_request(EFIKASB_USBH2_STP, "usbh2_stp"); | ||
| 111 | gpio_direction_output(EFIKASB_USBH2_STP, 0); | ||
| 112 | msleep(1); | ||
| 113 | gpio_set_value(EFIKASB_USBH2_STP, 1); | ||
| 114 | msleep(1); | ||
| 115 | |||
| 116 | gpio_free(EFIKASB_USBH2_STP); | ||
| 117 | mxc_iomux_v3_setup_pad(usbh2stp); | ||
| 118 | |||
| 119 | mdelay(10); | ||
| 120 | |||
| 121 | return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_ITC_NO_THRESHOLD); | ||
| 122 | } | ||
| 123 | |||
| 124 | static struct mxc_usbh_platform_data usbh2_config __initdata = { | ||
| 125 | .init = initialize_usbh2_port, | ||
| 126 | .portsc = MXC_EHCI_MODE_ULPI, | ||
| 127 | }; | ||
| 128 | |||
| 129 | static void __init mx51_efikasb_usb(void) | ||
| 130 | { | ||
| 131 | usbh2_config.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | | ||
| 132 | ULPI_OTG_DRVVBUS_EXT | ULPI_OTG_EXTVBUSIND); | ||
| 133 | if (usbh2_config.otg) | ||
| 134 | imx51_add_mxc_ehci_hs(2, &usbh2_config); | ||
| 135 | } | ||
| 136 | |||
| 137 | static const struct gpio_led mx51_efikasb_leds[] __initconst = { | ||
| 138 | { | ||
| 139 | .name = "efikasb:green", | ||
| 140 | .default_trigger = "default-on", | ||
| 141 | .gpio = EFIKASB_GREEN_LED, | ||
| 142 | .active_low = 1, | ||
| 143 | }, | ||
| 144 | { | ||
| 145 | .name = "efikasb:white", | ||
| 146 | .default_trigger = "caps", | ||
| 147 | .gpio = EFIKASB_WHITE_LED, | ||
| 148 | }, | ||
| 149 | }; | ||
| 150 | |||
| 151 | static const struct gpio_led_platform_data | ||
| 152 | mx51_efikasb_leds_data __initconst = { | ||
| 153 | .leds = mx51_efikasb_leds, | ||
| 154 | .num_leds = ARRAY_SIZE(mx51_efikasb_leds), | ||
| 155 | }; | ||
| 156 | |||
| 157 | static struct gpio_keys_button mx51_efikasb_keys[] = { | ||
| 158 | { | ||
| 159 | .code = KEY_POWER, | ||
| 160 | .gpio = EFIKASB_PWRKEY, | ||
| 161 | .type = EV_KEY, | ||
| 162 | .desc = "Power Button", | ||
| 163 | .wakeup = 1, | ||
| 164 | .active_low = 1, | ||
| 165 | }, | ||
| 166 | { | ||
| 167 | .code = SW_LID, | ||
| 168 | .gpio = EFIKASB_LID, | ||
| 169 | .type = EV_SW, | ||
| 170 | .desc = "Lid Switch", | ||
| 171 | .active_low = 1, | ||
| 172 | }, | ||
| 173 | { | ||
| 174 | .code = KEY_RFKILL, | ||
| 175 | .gpio = EFIKASB_RFKILL, | ||
| 176 | .type = EV_KEY, | ||
| 177 | .desc = "rfkill", | ||
| 178 | .active_low = 1, | ||
| 179 | }, | ||
| 180 | }; | ||
| 181 | |||
| 182 | static const struct gpio_keys_platform_data mx51_efikasb_keys_data __initconst = { | ||
| 183 | .buttons = mx51_efikasb_keys, | ||
| 184 | .nbuttons = ARRAY_SIZE(mx51_efikasb_keys), | ||
| 185 | }; | ||
| 186 | |||
| 187 | static struct esdhc_platform_data sd0_pdata = { | ||
| 188 | #define EFIKASB_SD1_CD IMX_GPIO_NR(2, 27) | ||
| 189 | .cd_gpio = EFIKASB_SD1_CD, | ||
| 190 | .cd_type = ESDHC_CD_GPIO, | ||
| 191 | .wp_type = ESDHC_WP_CONTROLLER, | ||
| 192 | }; | ||
| 193 | |||
| 194 | static struct esdhc_platform_data sd1_pdata = { | ||
| 195 | .cd_type = ESDHC_CD_CONTROLLER, | ||
| 196 | .wp_type = ESDHC_WP_CONTROLLER, | ||
| 197 | }; | ||
| 198 | |||
| 199 | static struct regulator *pwgt1, *pwgt2; | ||
| 200 | |||
| 201 | static void mx51_efikasb_power_off(void) | ||
| 202 | { | ||
| 203 | gpio_set_value(EFIKA_USB_PHY_RESET, 0); | ||
| 204 | |||
| 205 | if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) { | ||
| 206 | regulator_disable(pwgt2); | ||
| 207 | regulator_disable(pwgt1); | ||
| 208 | } | ||
| 209 | gpio_direction_output(EFIKASB_POWEROFF, 1); | ||
| 210 | } | ||
| 211 | |||
| 212 | static int __init mx51_efikasb_power_init(void) | ||
| 213 | { | ||
| 214 | pwgt1 = regulator_get(NULL, "pwgt1"); | ||
| 215 | pwgt2 = regulator_get(NULL, "pwgt2"); | ||
| 216 | if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) { | ||
| 217 | regulator_enable(pwgt1); | ||
| 218 | regulator_enable(pwgt2); | ||
| 219 | } | ||
| 220 | gpio_request(EFIKASB_POWEROFF, "poweroff"); | ||
| 221 | pm_power_off = mx51_efikasb_power_off; | ||
| 222 | |||
| 223 | regulator_has_full_constraints(); | ||
| 224 | |||
| 225 | return 0; | ||
| 226 | } | ||
| 227 | |||
| 228 | static void __init mx51_efikasb_init_late(void) | ||
| 229 | { | ||
| 230 | imx51_init_late(); | ||
| 231 | mx51_efikasb_power_init(); | ||
| 232 | } | ||
| 233 | |||
| 234 | /* 01 R1.3 board | ||
| 235 | 10 R2.0 board */ | ||
| 236 | static void __init mx51_efikasb_board_id(void) | ||
| 237 | { | ||
| 238 | int id; | ||
| 239 | |||
| 240 | gpio_request(EFIKASB_PCBID0, "pcb id0"); | ||
| 241 | gpio_direction_input(EFIKASB_PCBID0); | ||
| 242 | gpio_request(EFIKASB_PCBID1, "pcb id1"); | ||
| 243 | gpio_direction_input(EFIKASB_PCBID1); | ||
| 244 | |||
| 245 | id = gpio_get_value(EFIKASB_PCBID0) ? 1 : 0; | ||
| 246 | id |= (gpio_get_value(EFIKASB_PCBID1) ? 1 : 0) << 1; | ||
| 247 | |||
| 248 | switch (id) { | ||
| 249 | default: | ||
| 250 | break; | ||
| 251 | case 1: | ||
| 252 | system_rev = 0x13; | ||
| 253 | break; | ||
| 254 | case 2: | ||
| 255 | system_rev = 0x20; | ||
| 256 | break; | ||
| 257 | } | ||
| 258 | } | ||
| 259 | |||
| 260 | static void __init efikasb_board_init(void) | ||
| 261 | { | ||
| 262 | imx51_soc_init(); | ||
| 263 | |||
| 264 | mxc_iomux_v3_setup_multiple_pads(mx51efikasb_pads, | ||
| 265 | ARRAY_SIZE(mx51efikasb_pads)); | ||
| 266 | efika_board_common_init(); | ||
| 267 | |||
| 268 | mx51_efikasb_board_id(); | ||
| 269 | mx51_efikasb_usb(); | ||
| 270 | imx51_add_sdhci_esdhc_imx(0, &sd0_pdata); | ||
| 271 | imx51_add_sdhci_esdhc_imx(1, &sd1_pdata); | ||
| 272 | |||
| 273 | gpio_led_register_device(-1, &mx51_efikasb_leds_data); | ||
| 274 | imx_add_gpio_keys(&mx51_efikasb_keys_data); | ||
| 275 | } | ||
| 276 | |||
| 277 | static void __init mx51_efikasb_timer_init(void) | ||
| 278 | { | ||
| 279 | mx51_clocks_init(32768, 24000000, 22579200, 24576000); | ||
| 280 | } | ||
| 281 | |||
| 282 | static struct sys_timer mx51_efikasb_timer = { | ||
| 283 | .init = mx51_efikasb_timer_init, | ||
| 284 | }; | ||
| 285 | |||
| 286 | MACHINE_START(MX51_EFIKASB, "Genesi Efika MX (Smartbook)") | ||
| 287 | .atag_offset = 0x100, | ||
| 288 | .map_io = mx51_map_io, | ||
| 289 | .init_early = imx51_init_early, | ||
| 290 | .init_irq = mx51_init_irq, | ||
| 291 | .handle_irq = imx51_handle_irq, | ||
| 292 | .init_machine = efikasb_board_init, | ||
| 293 | .init_late = mx51_efikasb_init_late, | ||
| 294 | .timer = &mx51_efikasb_timer, | ||
| 295 | .restart = mxc_restart, | ||
| 296 | MACHINE_END | ||
diff --git a/arch/arm/mach-imx/mach-mx53_ard.c b/arch/arm/mach-imx/mach-mx53_ard.c deleted file mode 100644 index 6c28e65f424d..000000000000 --- a/arch/arm/mach-imx/mach-mx53_ard.c +++ /dev/null | |||
| @@ -1,272 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | */ | ||
| 4 | |||
| 5 | /* | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | |||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | |||
| 16 | * You should have received a copy of the GNU General Public License along | ||
| 17 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 18 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. | ||
| 19 | */ | ||
| 20 | |||
| 21 | #include <linux/init.h> | ||
| 22 | #include <linux/clk.h> | ||
| 23 | #include <linux/delay.h> | ||
| 24 | #include <linux/gpio.h> | ||
| 25 | #include <linux/smsc911x.h> | ||
| 26 | #include <linux/regulator/machine.h> | ||
| 27 | #include <linux/regulator/fixed.h> | ||
| 28 | |||
| 29 | #include <mach/common.h> | ||
| 30 | #include <mach/hardware.h> | ||
| 31 | #include <mach/iomux-mx53.h> | ||
| 32 | |||
| 33 | #include <asm/mach-types.h> | ||
| 34 | #include <asm/mach/arch.h> | ||
| 35 | #include <asm/mach/time.h> | ||
| 36 | |||
| 37 | #include "devices-imx53.h" | ||
| 38 | |||
| 39 | #define ARD_ETHERNET_INT_B IMX_GPIO_NR(2, 31) | ||
| 40 | #define ARD_SD1_CD IMX_GPIO_NR(1, 1) | ||
| 41 | #define ARD_SD1_WP IMX_GPIO_NR(1, 9) | ||
| 42 | #define ARD_I2CPORTEXP_B IMX_GPIO_NR(2, 3) | ||
| 43 | #define ARD_VOLUMEDOWN IMX_GPIO_NR(4, 0) | ||
| 44 | #define ARD_HOME IMX_GPIO_NR(5, 10) | ||
| 45 | #define ARD_BACK IMX_GPIO_NR(5, 11) | ||
| 46 | #define ARD_PROG IMX_GPIO_NR(5, 12) | ||
| 47 | #define ARD_VOLUMEUP IMX_GPIO_NR(5, 13) | ||
| 48 | |||
| 49 | static iomux_v3_cfg_t mx53_ard_pads[] = { | ||
| 50 | /* UART1 */ | ||
| 51 | MX53_PAD_PATA_DIOW__UART1_TXD_MUX, | ||
| 52 | MX53_PAD_PATA_DMACK__UART1_RXD_MUX, | ||
| 53 | /* WEIM for CS1 */ | ||
| 54 | MX53_PAD_EIM_EB3__GPIO2_31, /* ETHERNET_INT_B */ | ||
| 55 | MX53_PAD_EIM_D16__EMI_WEIM_D_16, | ||
| 56 | MX53_PAD_EIM_D17__EMI_WEIM_D_17, | ||
| 57 | MX53_PAD_EIM_D18__EMI_WEIM_D_18, | ||
| 58 | MX53_PAD_EIM_D19__EMI_WEIM_D_19, | ||
| 59 | MX53_PAD_EIM_D20__EMI_WEIM_D_20, | ||
| 60 | MX53_PAD_EIM_D21__EMI_WEIM_D_21, | ||
| 61 | MX53_PAD_EIM_D22__EMI_WEIM_D_22, | ||
| 62 | MX53_PAD_EIM_D23__EMI_WEIM_D_23, | ||
| 63 | MX53_PAD_EIM_D24__EMI_WEIM_D_24, | ||
| 64 | MX53_PAD_EIM_D25__EMI_WEIM_D_25, | ||
| 65 | MX53_PAD_EIM_D26__EMI_WEIM_D_26, | ||
| 66 | MX53_PAD_EIM_D27__EMI_WEIM_D_27, | ||
| 67 | MX53_PAD_EIM_D28__EMI_WEIM_D_28, | ||
| 68 | MX53_PAD_EIM_D29__EMI_WEIM_D_29, | ||
| 69 | MX53_PAD_EIM_D30__EMI_WEIM_D_30, | ||
| 70 | MX53_PAD_EIM_D31__EMI_WEIM_D_31, | ||
| 71 | MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0, | ||
| 72 | MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1, | ||
| 73 | MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2, | ||
| 74 | MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3, | ||
| 75 | MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4, | ||
| 76 | MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5, | ||
| 77 | MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6, | ||
| 78 | MX53_PAD_EIM_OE__EMI_WEIM_OE, | ||
| 79 | MX53_PAD_EIM_RW__EMI_WEIM_RW, | ||
| 80 | MX53_PAD_EIM_CS1__EMI_WEIM_CS_1, | ||
| 81 | /* SDHC1 */ | ||
| 82 | MX53_PAD_SD1_CMD__ESDHC1_CMD, | ||
| 83 | MX53_PAD_SD1_CLK__ESDHC1_CLK, | ||
| 84 | MX53_PAD_SD1_DATA0__ESDHC1_DAT0, | ||
| 85 | MX53_PAD_SD1_DATA1__ESDHC1_DAT1, | ||
| 86 | MX53_PAD_SD1_DATA2__ESDHC1_DAT2, | ||
| 87 | MX53_PAD_SD1_DATA3__ESDHC1_DAT3, | ||
| 88 | MX53_PAD_PATA_DATA8__ESDHC1_DAT4, | ||
| 89 | MX53_PAD_PATA_DATA9__ESDHC1_DAT5, | ||
| 90 | MX53_PAD_PATA_DATA10__ESDHC1_DAT6, | ||
| 91 | MX53_PAD_PATA_DATA11__ESDHC1_DAT7, | ||
| 92 | MX53_PAD_GPIO_1__GPIO1_1, | ||
| 93 | MX53_PAD_GPIO_9__GPIO1_9, | ||
| 94 | /* I2C2 */ | ||
| 95 | MX53_PAD_EIM_EB2__I2C2_SCL, | ||
| 96 | MX53_PAD_KEY_ROW3__I2C2_SDA, | ||
| 97 | /* I2C3 */ | ||
| 98 | MX53_PAD_GPIO_3__I2C3_SCL, | ||
| 99 | MX53_PAD_GPIO_16__I2C3_SDA, | ||
| 100 | /* GPIO */ | ||
| 101 | MX53_PAD_DISP0_DAT16__GPIO5_10, /* home */ | ||
| 102 | MX53_PAD_DISP0_DAT17__GPIO5_11, /* back */ | ||
| 103 | MX53_PAD_DISP0_DAT18__GPIO5_12, /* prog */ | ||
| 104 | MX53_PAD_DISP0_DAT19__GPIO5_13, /* vol up */ | ||
| 105 | MX53_PAD_GPIO_10__GPIO4_0, /* vol down */ | ||
| 106 | }; | ||
| 107 | |||
| 108 | #define GPIO_BUTTON(gpio_num, ev_code, act_low, descr, wake) \ | ||
| 109 | { \ | ||
| 110 | .gpio = gpio_num, \ | ||
| 111 | .type = EV_KEY, \ | ||
| 112 | .code = ev_code, \ | ||
| 113 | .active_low = act_low, \ | ||
| 114 | .desc = "btn " descr, \ | ||
| 115 | .wakeup = wake, \ | ||
| 116 | } | ||
| 117 | |||
| 118 | static struct gpio_keys_button ard_buttons[] = { | ||
| 119 | GPIO_BUTTON(ARD_HOME, KEY_HOME, 1, "home", 0), | ||
| 120 | GPIO_BUTTON(ARD_BACK, KEY_BACK, 1, "back", 0), | ||
| 121 | GPIO_BUTTON(ARD_PROG, KEY_PROGRAM, 1, "program", 0), | ||
| 122 | GPIO_BUTTON(ARD_VOLUMEUP, KEY_VOLUMEUP, 1, "volume-up", 0), | ||
| 123 | GPIO_BUTTON(ARD_VOLUMEDOWN, KEY_VOLUMEDOWN, 1, "volume-down", 0), | ||
| 124 | }; | ||
| 125 | |||
| 126 | static const struct gpio_keys_platform_data ard_button_data __initconst = { | ||
| 127 | .buttons = ard_buttons, | ||
| 128 | .nbuttons = ARRAY_SIZE(ard_buttons), | ||
| 129 | }; | ||
| 130 | |||
| 131 | static struct resource ard_smsc911x_resources[] = { | ||
| 132 | { | ||
| 133 | .start = MX53_CS1_64MB_BASE_ADDR, | ||
| 134 | .end = MX53_CS1_64MB_BASE_ADDR + SZ_32M - 1, | ||
| 135 | .flags = IORESOURCE_MEM, | ||
| 136 | }, | ||
| 137 | { | ||
| 138 | /* irq number is run-time assigned */ | ||
| 139 | .flags = IORESOURCE_IRQ, | ||
| 140 | }, | ||
| 141 | }; | ||
| 142 | |||
| 143 | struct smsc911x_platform_config ard_smsc911x_config = { | ||
| 144 | .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, | ||
| 145 | .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, | ||
| 146 | .flags = SMSC911X_USE_32BIT, | ||
| 147 | }; | ||
| 148 | |||
| 149 | static struct platform_device ard_smsc_lan9220_device = { | ||
| 150 | .name = "smsc911x", | ||
| 151 | .id = -1, | ||
| 152 | .num_resources = ARRAY_SIZE(ard_smsc911x_resources), | ||
| 153 | .resource = ard_smsc911x_resources, | ||
| 154 | .dev = { | ||
| 155 | .platform_data = &ard_smsc911x_config, | ||
| 156 | }, | ||
| 157 | }; | ||
| 158 | |||
| 159 | static const struct esdhc_platform_data mx53_ard_sd1_data __initconst = { | ||
| 160 | .cd_gpio = ARD_SD1_CD, | ||
| 161 | .wp_gpio = ARD_SD1_WP, | ||
| 162 | }; | ||
| 163 | |||
| 164 | static struct imxi2c_platform_data mx53_ard_i2c2_data = { | ||
| 165 | .bitrate = 50000, | ||
| 166 | }; | ||
| 167 | |||
| 168 | static struct imxi2c_platform_data mx53_ard_i2c3_data = { | ||
| 169 | .bitrate = 400000, | ||
| 170 | }; | ||
| 171 | |||
| 172 | static void __init mx53_ard_io_init(void) | ||
| 173 | { | ||
| 174 | gpio_request(ARD_ETHERNET_INT_B, "eth-int-b"); | ||
| 175 | gpio_direction_input(ARD_ETHERNET_INT_B); | ||
| 176 | |||
| 177 | gpio_request(ARD_I2CPORTEXP_B, "i2cptexp-rst"); | ||
| 178 | gpio_direction_output(ARD_I2CPORTEXP_B, 1); | ||
| 179 | } | ||
| 180 | |||
| 181 | /* Config CS1 settings for ethernet controller */ | ||
| 182 | static int weim_cs_config(void) | ||
| 183 | { | ||
| 184 | u32 reg; | ||
| 185 | void __iomem *weim_base, *iomuxc_base; | ||
| 186 | |||
| 187 | weim_base = ioremap(MX53_WEIM_BASE_ADDR, SZ_4K); | ||
| 188 | if (!weim_base) | ||
| 189 | return -ENOMEM; | ||
| 190 | |||
| 191 | iomuxc_base = ioremap(MX53_IOMUXC_BASE_ADDR, SZ_4K); | ||
| 192 | if (!iomuxc_base) { | ||
| 193 | iounmap(weim_base); | ||
| 194 | return -ENOMEM; | ||
| 195 | } | ||
| 196 | |||
| 197 | /* CS1 timings for LAN9220 */ | ||
| 198 | writel(0x20001, (weim_base + 0x18)); | ||
| 199 | writel(0x0, (weim_base + 0x1C)); | ||
| 200 | writel(0x16000202, (weim_base + 0x20)); | ||
| 201 | writel(0x00000002, (weim_base + 0x24)); | ||
| 202 | writel(0x16002082, (weim_base + 0x28)); | ||
| 203 | writel(0x00000000, (weim_base + 0x2C)); | ||
| 204 | writel(0x00000000, (weim_base + 0x90)); | ||
| 205 | |||
| 206 | /* specify 64 MB on CS1 and CS0 on GPR1 */ | ||
| 207 | reg = readl(iomuxc_base + 0x4); | ||
| 208 | reg &= ~0x3F; | ||
| 209 | reg |= 0x1B; | ||
| 210 | writel(reg, (iomuxc_base + 0x4)); | ||
| 211 | |||
| 212 | iounmap(iomuxc_base); | ||
| 213 | iounmap(weim_base); | ||
| 214 | |||
| 215 | return 0; | ||
| 216 | } | ||
| 217 | |||
| 218 | static struct regulator_consumer_supply dummy_supplies[] = { | ||
| 219 | REGULATOR_SUPPLY("vdd33a", "smsc911x"), | ||
| 220 | REGULATOR_SUPPLY("vddvario", "smsc911x"), | ||
| 221 | }; | ||
| 222 | |||
| 223 | void __init imx53_ard_common_init(void) | ||
| 224 | { | ||
| 225 | mxc_iomux_v3_setup_multiple_pads(mx53_ard_pads, | ||
| 226 | ARRAY_SIZE(mx53_ard_pads)); | ||
| 227 | weim_cs_config(); | ||
| 228 | } | ||
| 229 | |||
| 230 | static struct platform_device *devices[] __initdata = { | ||
| 231 | &ard_smsc_lan9220_device, | ||
| 232 | }; | ||
| 233 | |||
| 234 | static void __init mx53_ard_board_init(void) | ||
| 235 | { | ||
| 236 | imx53_soc_init(); | ||
| 237 | imx53_add_imx_uart(0, NULL); | ||
| 238 | |||
| 239 | imx53_ard_common_init(); | ||
| 240 | mx53_ard_io_init(); | ||
| 241 | regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies)); | ||
| 242 | ard_smsc911x_resources[1].start = gpio_to_irq(ARD_ETHERNET_INT_B); | ||
| 243 | ard_smsc911x_resources[1].end = gpio_to_irq(ARD_ETHERNET_INT_B); | ||
| 244 | platform_add_devices(devices, ARRAY_SIZE(devices)); | ||
| 245 | |||
| 246 | imx53_add_sdhci_esdhc_imx(0, &mx53_ard_sd1_data); | ||
| 247 | imx53_add_imx2_wdt(0); | ||
| 248 | imx53_add_imx_i2c(1, &mx53_ard_i2c2_data); | ||
| 249 | imx53_add_imx_i2c(2, &mx53_ard_i2c3_data); | ||
| 250 | imx_add_gpio_keys(&ard_button_data); | ||
| 251 | imx53_add_ahci_imx(); | ||
| 252 | } | ||
| 253 | |||
| 254 | static void __init mx53_ard_timer_init(void) | ||
| 255 | { | ||
| 256 | mx53_clocks_init(32768, 24000000, 22579200, 0); | ||
| 257 | } | ||
| 258 | |||
| 259 | static struct sys_timer mx53_ard_timer = { | ||
| 260 | .init = mx53_ard_timer_init, | ||
| 261 | }; | ||
| 262 | |||
| 263 | MACHINE_START(MX53_ARD, "Freescale MX53 ARD Board") | ||
| 264 | .map_io = mx53_map_io, | ||
| 265 | .init_early = imx53_init_early, | ||
| 266 | .init_irq = mx53_init_irq, | ||
| 267 | .handle_irq = imx53_handle_irq, | ||
| 268 | .timer = &mx53_ard_timer, | ||
| 269 | .init_machine = mx53_ard_board_init, | ||
| 270 | .init_late = imx53_init_late, | ||
| 271 | .restart = mxc_restart, | ||
| 272 | MACHINE_END | ||
diff --git a/arch/arm/mach-imx/mach-mx53_evk.c b/arch/arm/mach-imx/mach-mx53_evk.c deleted file mode 100644 index 09fe2197b491..000000000000 --- a/arch/arm/mach-imx/mach-mx53_evk.c +++ /dev/null | |||
| @@ -1,179 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | * Copyright (C) 2010 Yong Shen. <Yong.Shen@linaro.org> | ||
| 4 | */ | ||
| 5 | |||
| 6 | /* | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | |||
| 12 | * This program is distributed in the hope that it will be useful, | ||
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 15 | * GNU General Public License for more details. | ||
| 16 | |||
| 17 | * You should have received a copy of the GNU General Public License along | ||
| 18 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. | ||
| 20 | */ | ||
| 21 | |||
| 22 | #include <linux/init.h> | ||
| 23 | #include <linux/clk.h> | ||
| 24 | #include <linux/delay.h> | ||
| 25 | #include <linux/gpio.h> | ||
| 26 | #include <linux/spi/flash.h> | ||
| 27 | #include <linux/spi/spi.h> | ||
| 28 | #include <mach/common.h> | ||
| 29 | #include <mach/hardware.h> | ||
| 30 | #include <asm/mach-types.h> | ||
| 31 | #include <asm/mach/arch.h> | ||
| 32 | #include <asm/mach/time.h> | ||
| 33 | #include <mach/iomux-mx53.h> | ||
| 34 | |||
| 35 | #define MX53_EVK_FEC_PHY_RST IMX_GPIO_NR(7, 6) | ||
| 36 | #define EVK_ECSPI1_CS0 IMX_GPIO_NR(2, 30) | ||
| 37 | #define EVK_ECSPI1_CS1 IMX_GPIO_NR(3, 19) | ||
| 38 | #define MX53EVK_LED IMX_GPIO_NR(7, 7) | ||
| 39 | |||
| 40 | #include "devices-imx53.h" | ||
| 41 | |||
| 42 | static iomux_v3_cfg_t mx53_evk_pads[] = { | ||
| 43 | MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, | ||
| 44 | MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, | ||
| 45 | |||
| 46 | MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX, | ||
| 47 | MX53_PAD_PATA_DMARQ__UART2_TXD_MUX, | ||
| 48 | MX53_PAD_PATA_DIOR__UART2_RTS, | ||
| 49 | MX53_PAD_PATA_INTRQ__UART2_CTS, | ||
| 50 | |||
| 51 | MX53_PAD_PATA_CS_0__UART3_TXD_MUX, | ||
| 52 | MX53_PAD_PATA_CS_1__UART3_RXD_MUX, | ||
| 53 | |||
| 54 | MX53_PAD_EIM_D16__ECSPI1_SCLK, | ||
| 55 | MX53_PAD_EIM_D17__ECSPI1_MISO, | ||
| 56 | MX53_PAD_EIM_D18__ECSPI1_MOSI, | ||
| 57 | |||
| 58 | /* ecspi chip select lines */ | ||
| 59 | MX53_PAD_EIM_EB2__GPIO2_30, | ||
| 60 | MX53_PAD_EIM_D19__GPIO3_19, | ||
| 61 | /* LED */ | ||
| 62 | MX53_PAD_PATA_DA_1__GPIO7_7, | ||
| 63 | }; | ||
| 64 | |||
| 65 | static const struct imxuart_platform_data mx53_evk_uart_pdata __initconst = { | ||
| 66 | .flags = IMXUART_HAVE_RTSCTS, | ||
| 67 | }; | ||
| 68 | |||
| 69 | static const struct gpio_led mx53evk_leds[] __initconst = { | ||
| 70 | { | ||
| 71 | .name = "green", | ||
| 72 | .default_trigger = "heartbeat", | ||
| 73 | .gpio = MX53EVK_LED, | ||
| 74 | }, | ||
| 75 | }; | ||
| 76 | |||
| 77 | static const struct gpio_led_platform_data mx53evk_leds_data __initconst = { | ||
| 78 | .leds = mx53evk_leds, | ||
| 79 | .num_leds = ARRAY_SIZE(mx53evk_leds), | ||
| 80 | }; | ||
| 81 | |||
| 82 | static inline void mx53_evk_init_uart(void) | ||
| 83 | { | ||
| 84 | imx53_add_imx_uart(0, NULL); | ||
| 85 | imx53_add_imx_uart(1, &mx53_evk_uart_pdata); | ||
| 86 | imx53_add_imx_uart(2, NULL); | ||
| 87 | } | ||
| 88 | |||
| 89 | static const struct imxi2c_platform_data mx53_evk_i2c_data __initconst = { | ||
| 90 | .bitrate = 100000, | ||
| 91 | }; | ||
| 92 | |||
| 93 | static inline void mx53_evk_fec_reset(void) | ||
| 94 | { | ||
| 95 | int ret; | ||
| 96 | |||
| 97 | /* reset FEC PHY */ | ||
| 98 | ret = gpio_request_one(MX53_EVK_FEC_PHY_RST, GPIOF_OUT_INIT_LOW, | ||
| 99 | "fec-phy-reset"); | ||
| 100 | if (ret) { | ||
| 101 | printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret); | ||
| 102 | return; | ||
| 103 | } | ||
| 104 | msleep(1); | ||
| 105 | gpio_set_value(MX53_EVK_FEC_PHY_RST, 1); | ||
| 106 | } | ||
| 107 | |||
| 108 | static const struct fec_platform_data mx53_evk_fec_pdata __initconst = { | ||
| 109 | .phy = PHY_INTERFACE_MODE_RMII, | ||
| 110 | }; | ||
| 111 | |||
| 112 | static struct spi_board_info mx53_evk_spi_board_info[] __initdata = { | ||
| 113 | { | ||
| 114 | .modalias = "mtd_dataflash", | ||
| 115 | .max_speed_hz = 25000000, | ||
| 116 | .bus_num = 0, | ||
| 117 | .chip_select = 1, | ||
| 118 | .mode = SPI_MODE_0, | ||
| 119 | .platform_data = NULL, | ||
| 120 | }, | ||
| 121 | }; | ||
| 122 | |||
| 123 | static int mx53_evk_spi_cs[] = { | ||
| 124 | EVK_ECSPI1_CS0, | ||
| 125 | EVK_ECSPI1_CS1, | ||
| 126 | }; | ||
| 127 | |||
| 128 | static const struct spi_imx_master mx53_evk_spi_data __initconst = { | ||
| 129 | .chipselect = mx53_evk_spi_cs, | ||
| 130 | .num_chipselect = ARRAY_SIZE(mx53_evk_spi_cs), | ||
| 131 | }; | ||
| 132 | |||
| 133 | void __init imx53_evk_common_init(void) | ||
| 134 | { | ||
| 135 | mxc_iomux_v3_setup_multiple_pads(mx53_evk_pads, | ||
| 136 | ARRAY_SIZE(mx53_evk_pads)); | ||
| 137 | } | ||
| 138 | |||
| 139 | static void __init mx53_evk_board_init(void) | ||
| 140 | { | ||
| 141 | imx53_soc_init(); | ||
| 142 | imx53_evk_common_init(); | ||
| 143 | |||
| 144 | mx53_evk_init_uart(); | ||
| 145 | mx53_evk_fec_reset(); | ||
| 146 | imx53_add_fec(&mx53_evk_fec_pdata); | ||
| 147 | |||
| 148 | imx53_add_imx_i2c(0, &mx53_evk_i2c_data); | ||
| 149 | imx53_add_imx_i2c(1, &mx53_evk_i2c_data); | ||
| 150 | |||
| 151 | imx53_add_sdhci_esdhc_imx(0, NULL); | ||
| 152 | imx53_add_sdhci_esdhc_imx(1, NULL); | ||
| 153 | |||
| 154 | spi_register_board_info(mx53_evk_spi_board_info, | ||
| 155 | ARRAY_SIZE(mx53_evk_spi_board_info)); | ||
| 156 | imx53_add_ecspi(0, &mx53_evk_spi_data); | ||
| 157 | imx53_add_imx2_wdt(0); | ||
| 158 | gpio_led_register_device(-1, &mx53evk_leds_data); | ||
| 159 | } | ||
| 160 | |||
| 161 | static void __init mx53_evk_timer_init(void) | ||
| 162 | { | ||
| 163 | mx53_clocks_init(32768, 24000000, 22579200, 0); | ||
| 164 | } | ||
| 165 | |||
| 166 | static struct sys_timer mx53_evk_timer = { | ||
| 167 | .init = mx53_evk_timer_init, | ||
| 168 | }; | ||
| 169 | |||
| 170 | MACHINE_START(MX53_EVK, "Freescale MX53 EVK Board") | ||
| 171 | .map_io = mx53_map_io, | ||
| 172 | .init_early = imx53_init_early, | ||
| 173 | .init_irq = mx53_init_irq, | ||
| 174 | .handle_irq = imx53_handle_irq, | ||
| 175 | .timer = &mx53_evk_timer, | ||
| 176 | .init_machine = mx53_evk_board_init, | ||
| 177 | .init_late = imx53_init_late, | ||
| 178 | .restart = mxc_restart, | ||
| 179 | MACHINE_END | ||
diff --git a/arch/arm/mach-imx/mach-mx53_loco.c b/arch/arm/mach-imx/mach-mx53_loco.c deleted file mode 100644 index 8abe23c1d3c8..000000000000 --- a/arch/arm/mach-imx/mach-mx53_loco.c +++ /dev/null | |||
| @@ -1,321 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | */ | ||
| 4 | |||
| 5 | /* | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | |||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | |||
| 16 | * You should have received a copy of the GNU General Public License along | ||
| 17 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 18 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. | ||
| 19 | */ | ||
| 20 | |||
| 21 | #include <linux/init.h> | ||
| 22 | #include <linux/clk.h> | ||
| 23 | #include <linux/delay.h> | ||
| 24 | #include <linux/gpio.h> | ||
| 25 | #include <linux/i2c.h> | ||
| 26 | |||
| 27 | #include <mach/common.h> | ||
| 28 | #include <mach/hardware.h> | ||
| 29 | #include <mach/iomux-mx53.h> | ||
| 30 | |||
| 31 | #include <asm/mach-types.h> | ||
| 32 | #include <asm/mach/arch.h> | ||
| 33 | #include <asm/mach/time.h> | ||
| 34 | |||
| 35 | #include "devices-imx53.h" | ||
| 36 | |||
| 37 | #define MX53_LOCO_POWER IMX_GPIO_NR(1, 8) | ||
| 38 | #define MX53_LOCO_UI1 IMX_GPIO_NR(2, 14) | ||
| 39 | #define MX53_LOCO_UI2 IMX_GPIO_NR(2, 15) | ||
| 40 | #define LOCO_FEC_PHY_RST IMX_GPIO_NR(7, 6) | ||
| 41 | #define LOCO_LED IMX_GPIO_NR(7, 7) | ||
| 42 | #define LOCO_SD3_CD IMX_GPIO_NR(3, 11) | ||
| 43 | #define LOCO_SD3_WP IMX_GPIO_NR(3, 12) | ||
| 44 | #define LOCO_SD1_CD IMX_GPIO_NR(3, 13) | ||
| 45 | #define LOCO_ACCEL_EN IMX_GPIO_NR(6, 14) | ||
| 46 | |||
| 47 | static iomux_v3_cfg_t mx53_loco_pads[] = { | ||
| 48 | /* FEC */ | ||
| 49 | MX53_PAD_FEC_MDC__FEC_MDC, | ||
| 50 | MX53_PAD_FEC_MDIO__FEC_MDIO, | ||
| 51 | MX53_PAD_FEC_REF_CLK__FEC_TX_CLK, | ||
| 52 | MX53_PAD_FEC_RX_ER__FEC_RX_ER, | ||
| 53 | MX53_PAD_FEC_CRS_DV__FEC_RX_DV, | ||
| 54 | MX53_PAD_FEC_RXD1__FEC_RDATA_1, | ||
| 55 | MX53_PAD_FEC_RXD0__FEC_RDATA_0, | ||
| 56 | MX53_PAD_FEC_TX_EN__FEC_TX_EN, | ||
| 57 | MX53_PAD_FEC_TXD1__FEC_TDATA_1, | ||
| 58 | MX53_PAD_FEC_TXD0__FEC_TDATA_0, | ||
| 59 | /* FEC_nRST */ | ||
| 60 | MX53_PAD_PATA_DA_0__GPIO7_6, | ||
| 61 | /* FEC_nINT */ | ||
| 62 | MX53_PAD_PATA_DATA4__GPIO2_4, | ||
| 63 | /* AUDMUX5 */ | ||
| 64 | MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC, | ||
| 65 | MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD, | ||
| 66 | MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS, | ||
| 67 | MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD, | ||
| 68 | /* I2C1 */ | ||
| 69 | MX53_PAD_CSI0_DAT8__I2C1_SDA, | ||
| 70 | MX53_PAD_CSI0_DAT9__I2C1_SCL, | ||
| 71 | MX53_PAD_NANDF_CS1__GPIO6_14, /* Accelerometer Enable */ | ||
| 72 | /* I2C2 */ | ||
| 73 | MX53_PAD_KEY_COL3__I2C2_SCL, | ||
| 74 | MX53_PAD_KEY_ROW3__I2C2_SDA, | ||
| 75 | /* SD1 */ | ||
| 76 | MX53_PAD_SD1_CMD__ESDHC1_CMD, | ||
| 77 | MX53_PAD_SD1_CLK__ESDHC1_CLK, | ||
| 78 | MX53_PAD_SD1_DATA0__ESDHC1_DAT0, | ||
| 79 | MX53_PAD_SD1_DATA1__ESDHC1_DAT1, | ||
| 80 | MX53_PAD_SD1_DATA2__ESDHC1_DAT2, | ||
| 81 | MX53_PAD_SD1_DATA3__ESDHC1_DAT3, | ||
| 82 | /* SD1_CD */ | ||
| 83 | MX53_PAD_EIM_DA13__GPIO3_13, | ||
| 84 | /* SD3 */ | ||
| 85 | MX53_PAD_PATA_DATA8__ESDHC3_DAT0, | ||
| 86 | MX53_PAD_PATA_DATA9__ESDHC3_DAT1, | ||
| 87 | MX53_PAD_PATA_DATA10__ESDHC3_DAT2, | ||
| 88 | MX53_PAD_PATA_DATA11__ESDHC3_DAT3, | ||
| 89 | MX53_PAD_PATA_DATA0__ESDHC3_DAT4, | ||
| 90 | MX53_PAD_PATA_DATA1__ESDHC3_DAT5, | ||
| 91 | MX53_PAD_PATA_DATA2__ESDHC3_DAT6, | ||
| 92 | MX53_PAD_PATA_DATA3__ESDHC3_DAT7, | ||
| 93 | MX53_PAD_PATA_IORDY__ESDHC3_CLK, | ||
| 94 | MX53_PAD_PATA_RESET_B__ESDHC3_CMD, | ||
| 95 | /* SD3_CD */ | ||
| 96 | MX53_PAD_EIM_DA11__GPIO3_11, | ||
| 97 | /* SD3_WP */ | ||
| 98 | MX53_PAD_EIM_DA12__GPIO3_12, | ||
| 99 | /* VGA */ | ||
| 100 | MX53_PAD_EIM_OE__IPU_DI1_PIN7, | ||
| 101 | MX53_PAD_EIM_RW__IPU_DI1_PIN8, | ||
| 102 | /* DISPLB */ | ||
| 103 | MX53_PAD_EIM_D20__IPU_SER_DISP0_CS, | ||
| 104 | MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK, | ||
| 105 | MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN, | ||
| 106 | MX53_PAD_EIM_D23__IPU_DI0_D0_CS, | ||
| 107 | /* DISP0_POWER_EN */ | ||
| 108 | MX53_PAD_EIM_D24__GPIO3_24, | ||
| 109 | /* DISP0 DET INT */ | ||
| 110 | MX53_PAD_EIM_D31__GPIO3_31, | ||
| 111 | /* LVDS */ | ||
| 112 | MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3, | ||
| 113 | MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK, | ||
| 114 | MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2, | ||
| 115 | MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1, | ||
| 116 | MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0, | ||
| 117 | MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3, | ||
| 118 | MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2, | ||
| 119 | MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK, | ||
| 120 | MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1, | ||
| 121 | MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0, | ||
| 122 | /* I2C1 */ | ||
| 123 | MX53_PAD_CSI0_DAT8__I2C1_SDA, | ||
| 124 | MX53_PAD_CSI0_DAT9__I2C1_SCL, | ||
| 125 | /* UART1 */ | ||
| 126 | MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, | ||
| 127 | MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, | ||
| 128 | /* CSI0 */ | ||
| 129 | MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12, | ||
| 130 | MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13, | ||
| 131 | MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14, | ||
| 132 | MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15, | ||
| 133 | MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16, | ||
| 134 | MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17, | ||
| 135 | MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18, | ||
| 136 | MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19, | ||
| 137 | MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC, | ||
| 138 | MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC, | ||
| 139 | MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK, | ||
| 140 | /* DISPLAY */ | ||
| 141 | MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK, | ||
| 142 | MX53_PAD_DI0_PIN15__IPU_DI0_PIN15, | ||
| 143 | MX53_PAD_DI0_PIN2__IPU_DI0_PIN2, | ||
| 144 | MX53_PAD_DI0_PIN3__IPU_DI0_PIN3, | ||
| 145 | MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0, | ||
| 146 | MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1, | ||
| 147 | MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2, | ||
| 148 | MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3, | ||
| 149 | MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4, | ||
| 150 | MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5, | ||
| 151 | MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6, | ||
| 152 | MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7, | ||
| 153 | MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8, | ||
| 154 | MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9, | ||
| 155 | MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10, | ||
| 156 | MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11, | ||
| 157 | MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12, | ||
| 158 | MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13, | ||
| 159 | MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14, | ||
| 160 | MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15, | ||
| 161 | MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16, | ||
| 162 | MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17, | ||
| 163 | MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18, | ||
| 164 | MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19, | ||
| 165 | MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20, | ||
| 166 | MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21, | ||
| 167 | MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22, | ||
| 168 | MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23, | ||
| 169 | /* Audio CLK*/ | ||
| 170 | MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK, | ||
| 171 | /* PWM */ | ||
| 172 | MX53_PAD_GPIO_1__PWM2_PWMO, | ||
| 173 | /* SPDIF */ | ||
| 174 | MX53_PAD_GPIO_7__SPDIF_PLOCK, | ||
| 175 | MX53_PAD_GPIO_17__SPDIF_OUT1, | ||
| 176 | /* GPIO */ | ||
| 177 | MX53_PAD_PATA_DA_1__GPIO7_7, /* LED */ | ||
| 178 | MX53_PAD_PATA_DA_2__GPIO7_8, | ||
| 179 | MX53_PAD_PATA_DATA5__GPIO2_5, | ||
| 180 | MX53_PAD_PATA_DATA6__GPIO2_6, | ||
| 181 | MX53_PAD_PATA_DATA14__GPIO2_14, | ||
| 182 | MX53_PAD_PATA_DATA15__GPIO2_15, | ||
| 183 | MX53_PAD_PATA_INTRQ__GPIO7_2, | ||
| 184 | MX53_PAD_EIM_WAIT__GPIO5_0, | ||
| 185 | MX53_PAD_NANDF_WP_B__GPIO6_9, | ||
| 186 | MX53_PAD_NANDF_RB0__GPIO6_10, | ||
| 187 | MX53_PAD_NANDF_CS1__GPIO6_14, | ||
| 188 | MX53_PAD_NANDF_CS2__GPIO6_15, | ||
| 189 | MX53_PAD_NANDF_CS3__GPIO6_16, | ||
| 190 | MX53_PAD_GPIO_5__GPIO1_5, | ||
| 191 | MX53_PAD_GPIO_16__GPIO7_11, | ||
| 192 | MX53_PAD_GPIO_8__GPIO1_8, | ||
| 193 | }; | ||
| 194 | |||
| 195 | #define GPIO_BUTTON(gpio_num, ev_code, act_low, descr, wake) \ | ||
| 196 | { \ | ||
| 197 | .gpio = gpio_num, \ | ||
| 198 | .type = EV_KEY, \ | ||
| 199 | .code = ev_code, \ | ||
| 200 | .active_low = act_low, \ | ||
| 201 | .desc = "btn " descr, \ | ||
| 202 | .wakeup = wake, \ | ||
| 203 | } | ||
| 204 | |||
| 205 | static struct gpio_keys_button loco_buttons[] = { | ||
| 206 | GPIO_BUTTON(MX53_LOCO_POWER, KEY_POWER, 1, "power", 0), | ||
| 207 | GPIO_BUTTON(MX53_LOCO_UI1, KEY_VOLUMEUP, 1, "volume-up", 0), | ||
| 208 | GPIO_BUTTON(MX53_LOCO_UI2, KEY_VOLUMEDOWN, 1, "volume-down", 0), | ||
| 209 | }; | ||
| 210 | |||
| 211 | static const struct gpio_keys_platform_data loco_button_data __initconst = { | ||
| 212 | .buttons = loco_buttons, | ||
| 213 | .nbuttons = ARRAY_SIZE(loco_buttons), | ||
| 214 | }; | ||
| 215 | |||
| 216 | static const struct esdhc_platform_data mx53_loco_sd1_data __initconst = { | ||
| 217 | .cd_gpio = LOCO_SD1_CD, | ||
| 218 | .cd_type = ESDHC_CD_GPIO, | ||
| 219 | .wp_type = ESDHC_WP_NONE, | ||
| 220 | }; | ||
| 221 | |||
| 222 | static const struct esdhc_platform_data mx53_loco_sd3_data __initconst = { | ||
| 223 | .cd_gpio = LOCO_SD3_CD, | ||
| 224 | .wp_gpio = LOCO_SD3_WP, | ||
| 225 | .cd_type = ESDHC_CD_GPIO, | ||
| 226 | .wp_type = ESDHC_WP_GPIO, | ||
| 227 | }; | ||
| 228 | |||
| 229 | static inline void mx53_loco_fec_reset(void) | ||
| 230 | { | ||
| 231 | int ret; | ||
| 232 | |||
| 233 | /* reset FEC PHY */ | ||
| 234 | ret = gpio_request(LOCO_FEC_PHY_RST, "fec-phy-reset"); | ||
| 235 | if (ret) { | ||
| 236 | printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret); | ||
| 237 | return; | ||
| 238 | } | ||
| 239 | gpio_direction_output(LOCO_FEC_PHY_RST, 0); | ||
| 240 | msleep(1); | ||
| 241 | gpio_set_value(LOCO_FEC_PHY_RST, 1); | ||
| 242 | } | ||
| 243 | |||
| 244 | static const struct fec_platform_data mx53_loco_fec_data __initconst = { | ||
| 245 | .phy = PHY_INTERFACE_MODE_RMII, | ||
| 246 | }; | ||
| 247 | |||
| 248 | static const struct imxi2c_platform_data mx53_loco_i2c_data __initconst = { | ||
| 249 | .bitrate = 100000, | ||
| 250 | }; | ||
| 251 | |||
| 252 | static const struct gpio_led mx53loco_leds[] __initconst = { | ||
| 253 | { | ||
| 254 | .name = "green", | ||
| 255 | .default_trigger = "heartbeat", | ||
| 256 | .gpio = LOCO_LED, | ||
| 257 | }, | ||
| 258 | }; | ||
| 259 | |||
| 260 | static const struct gpio_led_platform_data mx53loco_leds_data __initconst = { | ||
| 261 | .leds = mx53loco_leds, | ||
| 262 | .num_leds = ARRAY_SIZE(mx53loco_leds), | ||
| 263 | }; | ||
| 264 | |||
| 265 | void __init imx53_qsb_common_init(void) | ||
| 266 | { | ||
| 267 | mxc_iomux_v3_setup_multiple_pads(mx53_loco_pads, | ||
| 268 | ARRAY_SIZE(mx53_loco_pads)); | ||
| 269 | } | ||
| 270 | |||
| 271 | static struct i2c_board_info mx53loco_i2c_devices[] = { | ||
| 272 | { | ||
| 273 | I2C_BOARD_INFO("mma8450", 0x1C), | ||
| 274 | }, | ||
| 275 | }; | ||
| 276 | |||
| 277 | static void __init mx53_loco_board_init(void) | ||
| 278 | { | ||
| 279 | int ret; | ||
| 280 | imx53_soc_init(); | ||
| 281 | imx53_qsb_common_init(); | ||
| 282 | |||
| 283 | imx53_add_imx_uart(0, NULL); | ||
| 284 | mx53_loco_fec_reset(); | ||
| 285 | imx53_add_fec(&mx53_loco_fec_data); | ||
| 286 | imx53_add_imx2_wdt(0); | ||
| 287 | |||
| 288 | ret = gpio_request_one(LOCO_ACCEL_EN, GPIOF_OUT_INIT_HIGH, "accel_en"); | ||
| 289 | if (ret) | ||
| 290 | pr_err("Cannot request ACCEL_EN pin: %d\n", ret); | ||
| 291 | |||
| 292 | i2c_register_board_info(0, mx53loco_i2c_devices, | ||
| 293 | ARRAY_SIZE(mx53loco_i2c_devices)); | ||
| 294 | imx53_add_imx_i2c(0, &mx53_loco_i2c_data); | ||
| 295 | imx53_add_imx_i2c(1, &mx53_loco_i2c_data); | ||
| 296 | imx53_add_sdhci_esdhc_imx(0, &mx53_loco_sd1_data); | ||
| 297 | imx53_add_sdhci_esdhc_imx(2, &mx53_loco_sd3_data); | ||
| 298 | imx_add_gpio_keys(&loco_button_data); | ||
| 299 | gpio_led_register_device(-1, &mx53loco_leds_data); | ||
| 300 | imx53_add_ahci_imx(); | ||
| 301 | } | ||
| 302 | |||
| 303 | static void __init mx53_loco_timer_init(void) | ||
| 304 | { | ||
| 305 | mx53_clocks_init(32768, 24000000, 0, 0); | ||
| 306 | } | ||
| 307 | |||
| 308 | static struct sys_timer mx53_loco_timer = { | ||
| 309 | .init = mx53_loco_timer_init, | ||
| 310 | }; | ||
| 311 | |||
| 312 | MACHINE_START(MX53_LOCO, "Freescale MX53 LOCO Board") | ||
| 313 | .map_io = mx53_map_io, | ||
| 314 | .init_early = imx53_init_early, | ||
| 315 | .init_irq = mx53_init_irq, | ||
| 316 | .handle_irq = imx53_handle_irq, | ||
| 317 | .timer = &mx53_loco_timer, | ||
| 318 | .init_machine = mx53_loco_board_init, | ||
| 319 | .init_late = imx53_init_late, | ||
| 320 | .restart = mxc_restart, | ||
| 321 | MACHINE_END | ||
diff --git a/arch/arm/mach-imx/mach-mx53_smd.c b/arch/arm/mach-imx/mach-mx53_smd.c deleted file mode 100644 index b15d6a6d3b68..000000000000 --- a/arch/arm/mach-imx/mach-mx53_smd.c +++ /dev/null | |||
| @@ -1,168 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | */ | ||
| 4 | |||
| 5 | /* | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | |||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | |||
| 16 | * You should have received a copy of the GNU General Public License along | ||
| 17 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 18 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. | ||
| 19 | */ | ||
| 20 | |||
| 21 | #include <linux/init.h> | ||
| 22 | #include <linux/clk.h> | ||
| 23 | #include <linux/delay.h> | ||
| 24 | #include <linux/gpio.h> | ||
| 25 | |||
| 26 | #include <mach/common.h> | ||
| 27 | #include <mach/hardware.h> | ||
| 28 | #include <mach/iomux-mx53.h> | ||
| 29 | |||
| 30 | #include <asm/mach-types.h> | ||
| 31 | #include <asm/mach/arch.h> | ||
| 32 | #include <asm/mach/time.h> | ||
| 33 | |||
| 34 | #include "devices-imx53.h" | ||
| 35 | |||
| 36 | #define SMD_FEC_PHY_RST IMX_GPIO_NR(7, 6) | ||
| 37 | #define MX53_SMD_SATA_PWR_EN IMX_GPIO_NR(3, 3) | ||
| 38 | |||
| 39 | static iomux_v3_cfg_t mx53_smd_pads[] = { | ||
| 40 | MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, | ||
| 41 | MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, | ||
| 42 | |||
| 43 | MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX, | ||
| 44 | MX53_PAD_PATA_DMARQ__UART2_TXD_MUX, | ||
| 45 | |||
| 46 | MX53_PAD_PATA_CS_0__UART3_TXD_MUX, | ||
| 47 | MX53_PAD_PATA_CS_1__UART3_RXD_MUX, | ||
| 48 | MX53_PAD_PATA_DA_1__UART3_CTS, | ||
| 49 | MX53_PAD_PATA_DA_2__UART3_RTS, | ||
| 50 | /* I2C1 */ | ||
| 51 | MX53_PAD_CSI0_DAT8__I2C1_SDA, | ||
| 52 | MX53_PAD_CSI0_DAT9__I2C1_SCL, | ||
| 53 | /* SD1 */ | ||
| 54 | MX53_PAD_SD1_CMD__ESDHC1_CMD, | ||
| 55 | MX53_PAD_SD1_CLK__ESDHC1_CLK, | ||
| 56 | MX53_PAD_SD1_DATA0__ESDHC1_DAT0, | ||
| 57 | MX53_PAD_SD1_DATA1__ESDHC1_DAT1, | ||
| 58 | MX53_PAD_SD1_DATA2__ESDHC1_DAT2, | ||
| 59 | MX53_PAD_SD1_DATA3__ESDHC1_DAT3, | ||
| 60 | /* SD2 */ | ||
| 61 | MX53_PAD_SD2_CMD__ESDHC2_CMD, | ||
| 62 | MX53_PAD_SD2_CLK__ESDHC2_CLK, | ||
| 63 | MX53_PAD_SD2_DATA0__ESDHC2_DAT0, | ||
| 64 | MX53_PAD_SD2_DATA1__ESDHC2_DAT1, | ||
| 65 | MX53_PAD_SD2_DATA2__ESDHC2_DAT2, | ||
| 66 | MX53_PAD_SD2_DATA3__ESDHC2_DAT3, | ||
| 67 | /* SD3 */ | ||
| 68 | MX53_PAD_PATA_DATA8__ESDHC3_DAT0, | ||
| 69 | MX53_PAD_PATA_DATA9__ESDHC3_DAT1, | ||
| 70 | MX53_PAD_PATA_DATA10__ESDHC3_DAT2, | ||
| 71 | MX53_PAD_PATA_DATA11__ESDHC3_DAT3, | ||
| 72 | MX53_PAD_PATA_DATA0__ESDHC3_DAT4, | ||
| 73 | MX53_PAD_PATA_DATA1__ESDHC3_DAT5, | ||
| 74 | MX53_PAD_PATA_DATA2__ESDHC3_DAT6, | ||
| 75 | MX53_PAD_PATA_DATA3__ESDHC3_DAT7, | ||
| 76 | MX53_PAD_PATA_IORDY__ESDHC3_CLK, | ||
| 77 | MX53_PAD_PATA_RESET_B__ESDHC3_CMD, | ||
| 78 | }; | ||
| 79 | |||
| 80 | static const struct imxuart_platform_data mx53_smd_uart_data __initconst = { | ||
| 81 | .flags = IMXUART_HAVE_RTSCTS, | ||
| 82 | }; | ||
| 83 | |||
| 84 | static inline void mx53_smd_init_uart(void) | ||
| 85 | { | ||
| 86 | imx53_add_imx_uart(0, NULL); | ||
| 87 | imx53_add_imx_uart(1, NULL); | ||
| 88 | imx53_add_imx_uart(2, &mx53_smd_uart_data); | ||
| 89 | } | ||
| 90 | |||
| 91 | static inline void mx53_smd_fec_reset(void) | ||
| 92 | { | ||
| 93 | int ret; | ||
| 94 | |||
| 95 | /* reset FEC PHY */ | ||
| 96 | ret = gpio_request(SMD_FEC_PHY_RST, "fec-phy-reset"); | ||
| 97 | if (ret) { | ||
| 98 | printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret); | ||
| 99 | return; | ||
| 100 | } | ||
| 101 | gpio_direction_output(SMD_FEC_PHY_RST, 0); | ||
| 102 | msleep(1); | ||
| 103 | gpio_set_value(SMD_FEC_PHY_RST, 1); | ||
| 104 | } | ||
| 105 | |||
| 106 | static const struct fec_platform_data mx53_smd_fec_data __initconst = { | ||
| 107 | .phy = PHY_INTERFACE_MODE_RMII, | ||
| 108 | }; | ||
| 109 | |||
| 110 | static const struct imxi2c_platform_data mx53_smd_i2c_data __initconst = { | ||
| 111 | .bitrate = 100000, | ||
| 112 | }; | ||
| 113 | |||
| 114 | static inline void mx53_smd_ahci_pwr_on(void) | ||
| 115 | { | ||
| 116 | int ret; | ||
| 117 | |||
| 118 | /* Enable SATA PWR */ | ||
| 119 | ret = gpio_request_one(MX53_SMD_SATA_PWR_EN, | ||
| 120 | GPIOF_DIR_OUT | GPIOF_INIT_HIGH, "ahci-sata-pwr"); | ||
| 121 | if (ret) { | ||
| 122 | pr_err("failed to enable SATA_PWR_EN: %d\n", ret); | ||
| 123 | return; | ||
| 124 | } | ||
| 125 | } | ||
| 126 | |||
| 127 | void __init imx53_smd_common_init(void) | ||
| 128 | { | ||
| 129 | mxc_iomux_v3_setup_multiple_pads(mx53_smd_pads, | ||
| 130 | ARRAY_SIZE(mx53_smd_pads)); | ||
| 131 | } | ||
| 132 | |||
| 133 | static void __init mx53_smd_board_init(void) | ||
| 134 | { | ||
| 135 | imx53_soc_init(); | ||
| 136 | imx53_smd_common_init(); | ||
| 137 | |||
| 138 | mx53_smd_init_uart(); | ||
| 139 | mx53_smd_fec_reset(); | ||
| 140 | imx53_add_fec(&mx53_smd_fec_data); | ||
| 141 | imx53_add_imx2_wdt(0); | ||
| 142 | imx53_add_imx_i2c(0, &mx53_smd_i2c_data); | ||
| 143 | imx53_add_sdhci_esdhc_imx(0, NULL); | ||
| 144 | imx53_add_sdhci_esdhc_imx(1, NULL); | ||
| 145 | imx53_add_sdhci_esdhc_imx(2, NULL); | ||
| 146 | mx53_smd_ahci_pwr_on(); | ||
| 147 | imx53_add_ahci_imx(); | ||
| 148 | } | ||
| 149 | |||
| 150 | static void __init mx53_smd_timer_init(void) | ||
| 151 | { | ||
| 152 | mx53_clocks_init(32768, 24000000, 22579200, 0); | ||
| 153 | } | ||
| 154 | |||
| 155 | static struct sys_timer mx53_smd_timer = { | ||
| 156 | .init = mx53_smd_timer_init, | ||
| 157 | }; | ||
| 158 | |||
| 159 | MACHINE_START(MX53_SMD, "Freescale MX53 SMD Board") | ||
| 160 | .map_io = mx53_map_io, | ||
| 161 | .init_early = imx53_init_early, | ||
| 162 | .init_irq = mx53_init_irq, | ||
| 163 | .handle_irq = imx53_handle_irq, | ||
| 164 | .timer = &mx53_smd_timer, | ||
| 165 | .init_machine = mx53_smd_board_init, | ||
| 166 | .init_late = imx53_init_late, | ||
| 167 | .restart = mxc_restart, | ||
| 168 | MACHINE_END | ||
diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c index 52d8f534be10..acb0aadb4255 100644 --- a/arch/arm/mach-imx/mm-imx5.c +++ b/arch/arm/mach-imx/mm-imx5.c | |||
| @@ -128,25 +128,6 @@ static struct sdma_platform_data imx51_sdma_pdata __initdata = { | |||
| 128 | .script_addrs = &imx51_sdma_script, | 128 | .script_addrs = &imx51_sdma_script, |
| 129 | }; | 129 | }; |
| 130 | 130 | ||
| 131 | static struct sdma_script_start_addrs imx53_sdma_script __initdata = { | ||
| 132 | .ap_2_ap_addr = 642, | ||
| 133 | .app_2_mcu_addr = 683, | ||
| 134 | .mcu_2_app_addr = 747, | ||
| 135 | .uart_2_mcu_addr = 817, | ||
| 136 | .shp_2_mcu_addr = 891, | ||
| 137 | .mcu_2_shp_addr = 960, | ||
| 138 | .uartsh_2_mcu_addr = 1032, | ||
| 139 | .spdif_2_mcu_addr = 1100, | ||
| 140 | .mcu_2_spdif_addr = 1134, | ||
| 141 | .firi_2_mcu_addr = 1193, | ||
| 142 | .mcu_2_firi_addr = 1290, | ||
| 143 | }; | ||
| 144 | |||
| 145 | static struct sdma_platform_data imx53_sdma_pdata __initdata = { | ||
| 146 | .fw_name = "sdma-imx53.bin", | ||
| 147 | .script_addrs = &imx53_sdma_script, | ||
| 148 | }; | ||
| 149 | |||
| 150 | static const struct resource imx50_audmux_res[] __initconst = { | 131 | static const struct resource imx50_audmux_res[] __initconst = { |
| 151 | DEFINE_RES_MEM(MX50_AUDMUX_BASE_ADDR, SZ_16K), | 132 | DEFINE_RES_MEM(MX50_AUDMUX_BASE_ADDR, SZ_16K), |
| 152 | }; | 133 | }; |
| @@ -155,10 +136,6 @@ static const struct resource imx51_audmux_res[] __initconst = { | |||
| 155 | DEFINE_RES_MEM(MX51_AUDMUX_BASE_ADDR, SZ_16K), | 136 | DEFINE_RES_MEM(MX51_AUDMUX_BASE_ADDR, SZ_16K), |
| 156 | }; | 137 | }; |
| 157 | 138 | ||
| 158 | static const struct resource imx53_audmux_res[] __initconst = { | ||
| 159 | DEFINE_RES_MEM(MX53_AUDMUX_BASE_ADDR, SZ_16K), | ||
| 160 | }; | ||
| 161 | |||
| 162 | void __init imx50_soc_init(void) | 139 | void __init imx50_soc_init(void) |
| 163 | { | 140 | { |
| 164 | /* i.mx50 has the i.mx35 type gpio */ | 141 | /* i.mx50 has the i.mx35 type gpio */ |
| @@ -196,30 +173,6 @@ void __init imx51_soc_init(void) | |||
| 196 | ARRAY_SIZE(imx51_audmux_res)); | 173 | ARRAY_SIZE(imx51_audmux_res)); |
| 197 | } | 174 | } |
| 198 | 175 | ||
| 199 | void __init imx53_soc_init(void) | ||
| 200 | { | ||
| 201 | /* i.mx53 has the i.mx35 type gpio */ | ||
| 202 | mxc_register_gpio("imx35-gpio", 0, MX53_GPIO1_BASE_ADDR, SZ_16K, MX53_INT_GPIO1_LOW, MX53_INT_GPIO1_HIGH); | ||
| 203 | mxc_register_gpio("imx35-gpio", 1, MX53_GPIO2_BASE_ADDR, SZ_16K, MX53_INT_GPIO2_LOW, MX53_INT_GPIO2_HIGH); | ||
| 204 | mxc_register_gpio("imx35-gpio", 2, MX53_GPIO3_BASE_ADDR, SZ_16K, MX53_INT_GPIO3_LOW, MX53_INT_GPIO3_HIGH); | ||
| 205 | mxc_register_gpio("imx35-gpio", 3, MX53_GPIO4_BASE_ADDR, SZ_16K, MX53_INT_GPIO4_LOW, MX53_INT_GPIO4_HIGH); | ||
| 206 | mxc_register_gpio("imx35-gpio", 4, MX53_GPIO5_BASE_ADDR, SZ_16K, MX53_INT_GPIO5_LOW, MX53_INT_GPIO5_HIGH); | ||
| 207 | mxc_register_gpio("imx35-gpio", 5, MX53_GPIO6_BASE_ADDR, SZ_16K, MX53_INT_GPIO6_LOW, MX53_INT_GPIO6_HIGH); | ||
| 208 | mxc_register_gpio("imx35-gpio", 6, MX53_GPIO7_BASE_ADDR, SZ_16K, MX53_INT_GPIO7_LOW, MX53_INT_GPIO7_HIGH); | ||
| 209 | |||
| 210 | pinctrl_provide_dummies(); | ||
| 211 | /* i.mx53 has the i.mx35 type sdma */ | ||
| 212 | imx_add_imx_sdma("imx35-sdma", MX53_SDMA_BASE_ADDR, MX53_INT_SDMA, &imx53_sdma_pdata); | ||
| 213 | |||
| 214 | /* Setup AIPS registers */ | ||
| 215 | imx_set_aips(MX53_IO_ADDRESS(MX53_AIPS1_BASE_ADDR)); | ||
| 216 | imx_set_aips(MX53_IO_ADDRESS(MX53_AIPS2_BASE_ADDR)); | ||
| 217 | |||
| 218 | /* i.mx53 has the i.mx31 type audmux */ | ||
| 219 | platform_device_register_simple("imx31-audmux", 0, imx53_audmux_res, | ||
| 220 | ARRAY_SIZE(imx53_audmux_res)); | ||
| 221 | } | ||
| 222 | |||
| 223 | void __init imx51_init_late(void) | 176 | void __init imx51_init_late(void) |
| 224 | { | 177 | { |
| 225 | mx51_neon_fixup(); | 178 | mx51_neon_fixup(); |
diff --git a/arch/arm/mach-imx/mx51_efika.c b/arch/arm/mach-imx/mx51_efika.c deleted file mode 100644 index ee870c49bc63..000000000000 --- a/arch/arm/mach-imx/mx51_efika.c +++ /dev/null | |||
| @@ -1,633 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * based on code from the following | ||
| 3 | * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 4 | * Copyright 2009-2010 Pegatron Corporation. All Rights Reserved. | ||
| 5 | * Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved. | ||
| 6 | * | ||
| 7 | * The code contained herein is licensed under the GNU General Public | ||
| 8 | * License. You may obtain a copy of the GNU General Public License | ||
| 9 | * Version 2 or later at the following locations: | ||
| 10 | * | ||
| 11 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 12 | * http://www.gnu.org/copyleft/gpl.html | ||
| 13 | */ | ||
| 14 | |||
| 15 | #include <linux/init.h> | ||
| 16 | #include <linux/platform_device.h> | ||
| 17 | #include <linux/i2c.h> | ||
| 18 | #include <linux/gpio.h> | ||
| 19 | #include <linux/leds.h> | ||
| 20 | #include <linux/input.h> | ||
| 21 | #include <linux/delay.h> | ||
| 22 | #include <linux/io.h> | ||
| 23 | #include <linux/spi/flash.h> | ||
| 24 | #include <linux/spi/spi.h> | ||
| 25 | #include <linux/mfd/mc13892.h> | ||
| 26 | #include <linux/regulator/machine.h> | ||
| 27 | #include <linux/regulator/consumer.h> | ||
| 28 | |||
| 29 | #include <mach/common.h> | ||
| 30 | #include <mach/hardware.h> | ||
| 31 | #include <mach/iomux-mx51.h> | ||
| 32 | |||
| 33 | #include <linux/usb/otg.h> | ||
| 34 | #include <linux/usb/ulpi.h> | ||
| 35 | #include <mach/ulpi.h> | ||
| 36 | |||
| 37 | #include <asm/setup.h> | ||
| 38 | #include <asm/mach-types.h> | ||
| 39 | #include <asm/mach/arch.h> | ||
| 40 | #include <asm/mach/time.h> | ||
| 41 | |||
| 42 | #include "devices-imx51.h" | ||
| 43 | #include "efika.h" | ||
| 44 | #include "cpu_op-mx51.h" | ||
| 45 | |||
| 46 | #define MX51_USB_CTRL_1_OFFSET 0x10 | ||
| 47 | #define MX51_USB_CTRL_UH1_EXT_CLK_EN (1 << 25) | ||
| 48 | #define MX51_USB_PLL_DIV_19_2_MHZ 0x01 | ||
| 49 | |||
| 50 | #define EFIKAMX_USB_HUB_RESET IMX_GPIO_NR(1, 5) | ||
| 51 | #define EFIKAMX_USBH1_STP IMX_GPIO_NR(1, 27) | ||
| 52 | |||
| 53 | #define EFIKAMX_SPI_CS0 IMX_GPIO_NR(4, 24) | ||
| 54 | #define EFIKAMX_SPI_CS1 IMX_GPIO_NR(4, 25) | ||
| 55 | |||
| 56 | #define EFIKAMX_PMIC IMX_GPIO_NR(1, 6) | ||
| 57 | |||
| 58 | static iomux_v3_cfg_t mx51efika_pads[] = { | ||
| 59 | /* UART1 */ | ||
| 60 | MX51_PAD_UART1_RXD__UART1_RXD, | ||
| 61 | MX51_PAD_UART1_TXD__UART1_TXD, | ||
| 62 | MX51_PAD_UART1_RTS__UART1_RTS, | ||
| 63 | MX51_PAD_UART1_CTS__UART1_CTS, | ||
| 64 | |||
| 65 | /* SD 1 */ | ||
| 66 | MX51_PAD_SD1_CMD__SD1_CMD, | ||
| 67 | MX51_PAD_SD1_CLK__SD1_CLK, | ||
| 68 | MX51_PAD_SD1_DATA0__SD1_DATA0, | ||
| 69 | MX51_PAD_SD1_DATA1__SD1_DATA1, | ||
| 70 | MX51_PAD_SD1_DATA2__SD1_DATA2, | ||
| 71 | MX51_PAD_SD1_DATA3__SD1_DATA3, | ||
| 72 | |||
| 73 | /* SD 2 */ | ||
| 74 | MX51_PAD_SD2_CMD__SD2_CMD, | ||
| 75 | MX51_PAD_SD2_CLK__SD2_CLK, | ||
| 76 | MX51_PAD_SD2_DATA0__SD2_DATA0, | ||
| 77 | MX51_PAD_SD2_DATA1__SD2_DATA1, | ||
| 78 | MX51_PAD_SD2_DATA2__SD2_DATA2, | ||
| 79 | MX51_PAD_SD2_DATA3__SD2_DATA3, | ||
| 80 | |||
| 81 | /* SD/MMC WP/CD */ | ||
| 82 | MX51_PAD_GPIO1_0__SD1_CD, | ||
| 83 | MX51_PAD_GPIO1_1__SD1_WP, | ||
| 84 | MX51_PAD_GPIO1_7__SD2_WP, | ||
| 85 | MX51_PAD_GPIO1_8__SD2_CD, | ||
| 86 | |||
| 87 | /* spi */ | ||
| 88 | MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI, | ||
| 89 | MX51_PAD_CSPI1_MISO__ECSPI1_MISO, | ||
| 90 | MX51_PAD_CSPI1_SS0__GPIO4_24, | ||
| 91 | MX51_PAD_CSPI1_SS1__GPIO4_25, | ||
| 92 | MX51_PAD_CSPI1_RDY__ECSPI1_RDY, | ||
| 93 | MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK, | ||
| 94 | MX51_PAD_GPIO1_6__GPIO1_6, | ||
| 95 | |||
| 96 | /* USB HOST1 */ | ||
| 97 | MX51_PAD_USBH1_CLK__USBH1_CLK, | ||
| 98 | MX51_PAD_USBH1_DIR__USBH1_DIR, | ||
| 99 | MX51_PAD_USBH1_NXT__USBH1_NXT, | ||
| 100 | MX51_PAD_USBH1_DATA0__USBH1_DATA0, | ||
| 101 | MX51_PAD_USBH1_DATA1__USBH1_DATA1, | ||
| 102 | MX51_PAD_USBH1_DATA2__USBH1_DATA2, | ||
| 103 | MX51_PAD_USBH1_DATA3__USBH1_DATA3, | ||
| 104 | MX51_PAD_USBH1_DATA4__USBH1_DATA4, | ||
| 105 | MX51_PAD_USBH1_DATA5__USBH1_DATA5, | ||
| 106 | MX51_PAD_USBH1_DATA6__USBH1_DATA6, | ||
| 107 | MX51_PAD_USBH1_DATA7__USBH1_DATA7, | ||
| 108 | |||
| 109 | /* USB HUB RESET */ | ||
| 110 | MX51_PAD_GPIO1_5__GPIO1_5, | ||
| 111 | |||
| 112 | /* WLAN */ | ||
| 113 | MX51_PAD_EIM_A22__GPIO2_16, | ||
| 114 | MX51_PAD_EIM_A16__GPIO2_10, | ||
| 115 | |||
| 116 | /* USB PHY RESET */ | ||
| 117 | MX51_PAD_EIM_D27__GPIO2_9, | ||
| 118 | }; | ||
| 119 | |||
| 120 | /* Serial ports */ | ||
| 121 | static const struct imxuart_platform_data uart_pdata = { | ||
| 122 | .flags = IMXUART_HAVE_RTSCTS, | ||
| 123 | }; | ||
| 124 | |||
| 125 | /* This function is board specific as the bit mask for the plldiv will also | ||
| 126 | * be different for other Freescale SoCs, thus a common bitmask is not | ||
| 127 | * possible and cannot get place in /plat-mxc/ehci.c. | ||
| 128 | */ | ||
| 129 | static int initialize_otg_port(struct platform_device *pdev) | ||
| 130 | { | ||
| 131 | u32 v; | ||
| 132 | void __iomem *usb_base; | ||
| 133 | void __iomem *usbother_base; | ||
| 134 | usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K); | ||
| 135 | if (!usb_base) | ||
| 136 | return -ENOMEM; | ||
| 137 | usbother_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET); | ||
| 138 | |||
| 139 | /* Set the PHY clock to 19.2MHz */ | ||
| 140 | v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET); | ||
| 141 | v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK; | ||
| 142 | v |= MX51_USB_PLL_DIV_19_2_MHZ; | ||
| 143 | __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET); | ||
| 144 | iounmap(usb_base); | ||
| 145 | |||
| 146 | mdelay(10); | ||
| 147 | |||
| 148 | return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_INTERNAL_PHY); | ||
| 149 | } | ||
| 150 | |||
| 151 | static const struct mxc_usbh_platform_data dr_utmi_config __initconst = { | ||
| 152 | .init = initialize_otg_port, | ||
| 153 | .portsc = MXC_EHCI_UTMI_16BIT, | ||
| 154 | }; | ||
| 155 | |||
| 156 | static int initialize_usbh1_port(struct platform_device *pdev) | ||
| 157 | { | ||
| 158 | iomux_v3_cfg_t usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP; | ||
| 159 | iomux_v3_cfg_t usbh1gpio = MX51_PAD_USBH1_STP__GPIO1_27; | ||
| 160 | u32 v; | ||
| 161 | void __iomem *usb_base; | ||
| 162 | void __iomem *socregs_base; | ||
| 163 | |||
| 164 | mxc_iomux_v3_setup_pad(usbh1gpio); | ||
| 165 | gpio_request(EFIKAMX_USBH1_STP, "usbh1_stp"); | ||
| 166 | gpio_direction_output(EFIKAMX_USBH1_STP, 0); | ||
| 167 | msleep(1); | ||
| 168 | gpio_set_value(EFIKAMX_USBH1_STP, 1); | ||
| 169 | msleep(1); | ||
| 170 | |||
| 171 | usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K); | ||
| 172 | socregs_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET); | ||
| 173 | |||
| 174 | /* The clock for the USBH1 ULPI port will come externally */ | ||
| 175 | /* from the PHY. */ | ||
| 176 | v = __raw_readl(socregs_base + MX51_USB_CTRL_1_OFFSET); | ||
| 177 | __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, | ||
| 178 | socregs_base + MX51_USB_CTRL_1_OFFSET); | ||
| 179 | |||
| 180 | iounmap(usb_base); | ||
| 181 | |||
| 182 | gpio_free(EFIKAMX_USBH1_STP); | ||
| 183 | mxc_iomux_v3_setup_pad(usbh1stp); | ||
| 184 | |||
| 185 | mdelay(10); | ||
| 186 | |||
| 187 | return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_ITC_NO_THRESHOLD); | ||
| 188 | } | ||
| 189 | |||
| 190 | static struct mxc_usbh_platform_data usbh1_config __initdata = { | ||
| 191 | .init = initialize_usbh1_port, | ||
| 192 | .portsc = MXC_EHCI_MODE_ULPI, | ||
| 193 | }; | ||
| 194 | |||
| 195 | static void mx51_efika_hubreset(void) | ||
| 196 | { | ||
| 197 | gpio_request(EFIKAMX_USB_HUB_RESET, "usb_hub_rst"); | ||
| 198 | gpio_direction_output(EFIKAMX_USB_HUB_RESET, 1); | ||
| 199 | msleep(1); | ||
| 200 | gpio_set_value(EFIKAMX_USB_HUB_RESET, 0); | ||
| 201 | msleep(1); | ||
| 202 | gpio_set_value(EFIKAMX_USB_HUB_RESET, 1); | ||
| 203 | } | ||
| 204 | |||
| 205 | static void __init mx51_efika_usb(void) | ||
| 206 | { | ||
| 207 | mx51_efika_hubreset(); | ||
| 208 | |||
| 209 | /* pulling it low, means no USB at all... */ | ||
| 210 | gpio_request(EFIKA_USB_PHY_RESET, "usb_phy_reset"); | ||
| 211 | gpio_direction_output(EFIKA_USB_PHY_RESET, 0); | ||
| 212 | msleep(1); | ||
| 213 | gpio_set_value(EFIKA_USB_PHY_RESET, 1); | ||
| 214 | |||
| 215 | usbh1_config.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | | ||
| 216 | ULPI_OTG_DRVVBUS_EXT | ULPI_OTG_EXTVBUSIND); | ||
| 217 | |||
| 218 | imx51_add_mxc_ehci_otg(&dr_utmi_config); | ||
| 219 | if (usbh1_config.otg) | ||
| 220 | imx51_add_mxc_ehci_hs(1, &usbh1_config); | ||
| 221 | } | ||
| 222 | |||
| 223 | static struct mtd_partition mx51_efika_spi_nor_partitions[] = { | ||
| 224 | { | ||
| 225 | .name = "u-boot", | ||
| 226 | .offset = 0, | ||
| 227 | .size = SZ_256K, | ||
| 228 | }, | ||
| 229 | { | ||
| 230 | .name = "config", | ||
| 231 | .offset = MTDPART_OFS_APPEND, | ||
| 232 | .size = SZ_64K, | ||
| 233 | }, | ||
| 234 | }; | ||
| 235 | |||
| 236 | static struct flash_platform_data mx51_efika_spi_flash_data = { | ||
| 237 | .name = "spi_flash", | ||
| 238 | .parts = mx51_efika_spi_nor_partitions, | ||
| 239 | .nr_parts = ARRAY_SIZE(mx51_efika_spi_nor_partitions), | ||
| 240 | .type = "sst25vf032b", | ||
| 241 | }; | ||
| 242 | |||
| 243 | static struct regulator_consumer_supply sw1_consumers[] = { | ||
| 244 | { | ||
| 245 | .supply = "cpu_vcc", | ||
| 246 | } | ||
| 247 | }; | ||
| 248 | |||
| 249 | static struct regulator_consumer_supply vdig_consumers[] = { | ||
| 250 | /* sgtl5000 */ | ||
| 251 | REGULATOR_SUPPLY("VDDA", "1-000a"), | ||
| 252 | REGULATOR_SUPPLY("VDDD", "1-000a"), | ||
| 253 | }; | ||
| 254 | |||
| 255 | static struct regulator_consumer_supply vvideo_consumers[] = { | ||
| 256 | /* sgtl5000 */ | ||
| 257 | REGULATOR_SUPPLY("VDDIO", "1-000a"), | ||
| 258 | }; | ||
| 259 | |||
| 260 | static struct regulator_consumer_supply vsd_consumers[] = { | ||
| 261 | REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx51.0"), | ||
| 262 | REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx51.1"), | ||
| 263 | }; | ||
| 264 | |||
| 265 | static struct regulator_consumer_supply pwgt1_consumer[] = { | ||
| 266 | { | ||
| 267 | .supply = "pwgt1", | ||
| 268 | } | ||
| 269 | }; | ||
| 270 | |||
| 271 | static struct regulator_consumer_supply pwgt2_consumer[] = { | ||
| 272 | { | ||
| 273 | .supply = "pwgt2", | ||
| 274 | } | ||
| 275 | }; | ||
| 276 | |||
| 277 | static struct regulator_consumer_supply coincell_consumer[] = { | ||
| 278 | { | ||
| 279 | .supply = "coincell", | ||
| 280 | } | ||
| 281 | }; | ||
| 282 | |||
| 283 | static struct regulator_init_data sw1_init = { | ||
| 284 | .constraints = { | ||
| 285 | .name = "SW1", | ||
| 286 | .min_uV = 600000, | ||
| 287 | .max_uV = 1375000, | ||
| 288 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, | ||
| 289 | .valid_modes_mask = 0, | ||
| 290 | .always_on = 1, | ||
| 291 | .boot_on = 1, | ||
| 292 | .state_mem = { | ||
| 293 | .uV = 850000, | ||
| 294 | .mode = REGULATOR_MODE_NORMAL, | ||
| 295 | .enabled = 1, | ||
| 296 | }, | ||
| 297 | }, | ||
| 298 | .num_consumer_supplies = ARRAY_SIZE(sw1_consumers), | ||
| 299 | .consumer_supplies = sw1_consumers, | ||
| 300 | }; | ||
| 301 | |||
| 302 | static struct regulator_init_data sw2_init = { | ||
| 303 | .constraints = { | ||
| 304 | .name = "SW2", | ||
| 305 | .min_uV = 900000, | ||
| 306 | .max_uV = 1850000, | ||
| 307 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, | ||
| 308 | .always_on = 1, | ||
| 309 | .boot_on = 1, | ||
| 310 | .state_mem = { | ||
| 311 | .uV = 950000, | ||
| 312 | .mode = REGULATOR_MODE_NORMAL, | ||
| 313 | .enabled = 1, | ||
| 314 | }, | ||
| 315 | } | ||
| 316 | }; | ||
| 317 | |||
| 318 | static struct regulator_init_data sw3_init = { | ||
| 319 | .constraints = { | ||
| 320 | .name = "SW3", | ||
| 321 | .min_uV = 1100000, | ||
| 322 | .max_uV = 1850000, | ||
| 323 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, | ||
| 324 | .always_on = 1, | ||
| 325 | .boot_on = 1, | ||
| 326 | } | ||
| 327 | }; | ||
| 328 | |||
| 329 | static struct regulator_init_data sw4_init = { | ||
| 330 | .constraints = { | ||
| 331 | .name = "SW4", | ||
| 332 | .min_uV = 1100000, | ||
| 333 | .max_uV = 1850000, | ||
| 334 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, | ||
| 335 | .always_on = 1, | ||
| 336 | .boot_on = 1, | ||
| 337 | } | ||
| 338 | }; | ||
| 339 | |||
| 340 | static struct regulator_init_data viohi_init = { | ||
| 341 | .constraints = { | ||
| 342 | .name = "VIOHI", | ||
| 343 | .boot_on = 1, | ||
| 344 | .always_on = 1, | ||
| 345 | } | ||
| 346 | }; | ||
| 347 | |||
| 348 | static struct regulator_init_data vusb_init = { | ||
| 349 | .constraints = { | ||
| 350 | .name = "VUSB", | ||
| 351 | .boot_on = 1, | ||
| 352 | .always_on = 1, | ||
| 353 | } | ||
| 354 | }; | ||
| 355 | |||
| 356 | static struct regulator_init_data swbst_init = { | ||
| 357 | .constraints = { | ||
| 358 | .name = "SWBST", | ||
| 359 | } | ||
| 360 | }; | ||
| 361 | |||
| 362 | static struct regulator_init_data vdig_init = { | ||
| 363 | .constraints = { | ||
| 364 | .name = "VDIG", | ||
| 365 | .min_uV = 1050000, | ||
| 366 | .max_uV = 1800000, | ||
| 367 | .valid_ops_mask = | ||
| 368 | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS, | ||
| 369 | .boot_on = 1, | ||
| 370 | .always_on = 1, | ||
| 371 | }, | ||
| 372 | .num_consumer_supplies = ARRAY_SIZE(vdig_consumers), | ||
| 373 | .consumer_supplies = vdig_consumers, | ||
| 374 | }; | ||
| 375 | |||
| 376 | static struct regulator_init_data vpll_init = { | ||
| 377 | .constraints = { | ||
| 378 | .name = "VPLL", | ||
| 379 | .min_uV = 1050000, | ||
| 380 | .max_uV = 1800000, | ||
| 381 | .valid_ops_mask = | ||
| 382 | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS, | ||
| 383 | .boot_on = 1, | ||
| 384 | .always_on = 1, | ||
| 385 | } | ||
| 386 | }; | ||
| 387 | |||
| 388 | static struct regulator_init_data vusb2_init = { | ||
| 389 | .constraints = { | ||
| 390 | .name = "VUSB2", | ||
| 391 | .min_uV = 2400000, | ||
| 392 | .max_uV = 2775000, | ||
| 393 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, | ||
| 394 | .boot_on = 1, | ||
| 395 | .always_on = 1, | ||
| 396 | } | ||
| 397 | }; | ||
| 398 | |||
| 399 | static struct regulator_init_data vvideo_init = { | ||
| 400 | .constraints = { | ||
| 401 | .name = "VVIDEO", | ||
| 402 | .min_uV = 2775000, | ||
| 403 | .max_uV = 2775000, | ||
| 404 | .valid_ops_mask = | ||
| 405 | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS, | ||
| 406 | .boot_on = 1, | ||
| 407 | .apply_uV = 1, | ||
| 408 | }, | ||
| 409 | .num_consumer_supplies = ARRAY_SIZE(vvideo_consumers), | ||
| 410 | .consumer_supplies = vvideo_consumers, | ||
| 411 | }; | ||
| 412 | |||
| 413 | static struct regulator_init_data vaudio_init = { | ||
| 414 | .constraints = { | ||
| 415 | .name = "VAUDIO", | ||
| 416 | .min_uV = 2300000, | ||
| 417 | .max_uV = 3000000, | ||
| 418 | .valid_ops_mask = | ||
| 419 | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS, | ||
| 420 | .boot_on = 1, | ||
| 421 | } | ||
| 422 | }; | ||
| 423 | |||
| 424 | static struct regulator_init_data vsd_init = { | ||
| 425 | .constraints = { | ||
| 426 | .name = "VSD", | ||
| 427 | .min_uV = 1800000, | ||
| 428 | .max_uV = 3150000, | ||
| 429 | .valid_ops_mask = | ||
| 430 | REGULATOR_CHANGE_VOLTAGE, | ||
| 431 | .boot_on = 1, | ||
| 432 | }, | ||
| 433 | .num_consumer_supplies = ARRAY_SIZE(vsd_consumers), | ||
| 434 | .consumer_supplies = vsd_consumers, | ||
| 435 | }; | ||
| 436 | |||
| 437 | static struct regulator_init_data vcam_init = { | ||
| 438 | .constraints = { | ||
| 439 | .name = "VCAM", | ||
| 440 | .min_uV = 2500000, | ||
| 441 | .max_uV = 3000000, | ||
| 442 | .valid_ops_mask = | ||
| 443 | REGULATOR_CHANGE_VOLTAGE | | ||
| 444 | REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS, | ||
| 445 | .valid_modes_mask = REGULATOR_MODE_FAST | REGULATOR_MODE_NORMAL, | ||
| 446 | .boot_on = 1, | ||
| 447 | } | ||
| 448 | }; | ||
| 449 | |||
| 450 | static struct regulator_init_data vgen1_init = { | ||
| 451 | .constraints = { | ||
| 452 | .name = "VGEN1", | ||
| 453 | .min_uV = 1200000, | ||
| 454 | .max_uV = 3150000, | ||
| 455 | .valid_ops_mask = | ||
| 456 | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS, | ||
| 457 | .boot_on = 1, | ||
| 458 | .always_on = 1, | ||
| 459 | } | ||
| 460 | }; | ||
| 461 | |||
| 462 | static struct regulator_init_data vgen2_init = { | ||
| 463 | .constraints = { | ||
| 464 | .name = "VGEN2", | ||
| 465 | .min_uV = 1200000, | ||
| 466 | .max_uV = 3150000, | ||
| 467 | .valid_ops_mask = | ||
| 468 | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS, | ||
| 469 | .boot_on = 1, | ||
| 470 | .always_on = 1, | ||
| 471 | } | ||
| 472 | }; | ||
| 473 | |||
| 474 | static struct regulator_init_data vgen3_init = { | ||
| 475 | .constraints = { | ||
| 476 | .name = "VGEN3", | ||
| 477 | .min_uV = 1800000, | ||
| 478 | .max_uV = 2900000, | ||
| 479 | .valid_ops_mask = | ||
| 480 | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS, | ||
| 481 | .boot_on = 1, | ||
| 482 | .always_on = 1, | ||
| 483 | } | ||
| 484 | }; | ||
| 485 | |||
| 486 | static struct regulator_init_data gpo1_init = { | ||
| 487 | .constraints = { | ||
| 488 | .name = "GPO1", | ||
| 489 | } | ||
| 490 | }; | ||
| 491 | |||
| 492 | static struct regulator_init_data gpo2_init = { | ||
| 493 | .constraints = { | ||
| 494 | .name = "GPO2", | ||
| 495 | } | ||
| 496 | }; | ||
| 497 | |||
| 498 | static struct regulator_init_data gpo3_init = { | ||
| 499 | .constraints = { | ||
| 500 | .name = "GPO3", | ||
| 501 | } | ||
| 502 | }; | ||
| 503 | |||
| 504 | static struct regulator_init_data gpo4_init = { | ||
| 505 | .constraints = { | ||
| 506 | .name = "GPO4", | ||
| 507 | } | ||
| 508 | }; | ||
| 509 | |||
| 510 | static struct regulator_init_data pwgt1_init = { | ||
| 511 | .constraints = { | ||
| 512 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | ||
| 513 | .boot_on = 1, | ||
| 514 | }, | ||
| 515 | .num_consumer_supplies = ARRAY_SIZE(pwgt1_consumer), | ||
| 516 | .consumer_supplies = pwgt1_consumer, | ||
| 517 | }; | ||
| 518 | |||
| 519 | static struct regulator_init_data pwgt2_init = { | ||
| 520 | .constraints = { | ||
| 521 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | ||
| 522 | .boot_on = 1, | ||
| 523 | }, | ||
| 524 | .num_consumer_supplies = ARRAY_SIZE(pwgt2_consumer), | ||
| 525 | .consumer_supplies = pwgt2_consumer, | ||
| 526 | }; | ||
| 527 | |||
| 528 | static struct regulator_init_data vcoincell_init = { | ||
| 529 | .constraints = { | ||
| 530 | .name = "COINCELL", | ||
| 531 | .min_uV = 3000000, | ||
| 532 | .max_uV = 3000000, | ||
| 533 | .valid_ops_mask = | ||
| 534 | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS, | ||
| 535 | }, | ||
| 536 | .num_consumer_supplies = ARRAY_SIZE(coincell_consumer), | ||
| 537 | .consumer_supplies = coincell_consumer, | ||
| 538 | }; | ||
| 539 | |||
| 540 | static struct mc13xxx_regulator_init_data mx51_efika_regulators[] = { | ||
| 541 | { .id = MC13892_SW1, .init_data = &sw1_init }, | ||
| 542 | { .id = MC13892_SW2, .init_data = &sw2_init }, | ||
| 543 | { .id = MC13892_SW3, .init_data = &sw3_init }, | ||
| 544 | { .id = MC13892_SW4, .init_data = &sw4_init }, | ||
| 545 | { .id = MC13892_SWBST, .init_data = &swbst_init }, | ||
| 546 | { .id = MC13892_VIOHI, .init_data = &viohi_init }, | ||
| 547 | { .id = MC13892_VPLL, .init_data = &vpll_init }, | ||
| 548 | { .id = MC13892_VDIG, .init_data = &vdig_init }, | ||
| 549 | { .id = MC13892_VSD, .init_data = &vsd_init }, | ||
| 550 | { .id = MC13892_VUSB2, .init_data = &vusb2_init }, | ||
| 551 | { .id = MC13892_VVIDEO, .init_data = &vvideo_init }, | ||
| 552 | { .id = MC13892_VAUDIO, .init_data = &vaudio_init }, | ||
| 553 | { .id = MC13892_VCAM, .init_data = &vcam_init }, | ||
| 554 | { .id = MC13892_VGEN1, .init_data = &vgen1_init }, | ||
| 555 | { .id = MC13892_VGEN2, .init_data = &vgen2_init }, | ||
| 556 | { .id = MC13892_VGEN3, .init_data = &vgen3_init }, | ||
| 557 | { .id = MC13892_VUSB, .init_data = &vusb_init }, | ||
| 558 | { .id = MC13892_GPO1, .init_data = &gpo1_init }, | ||
| 559 | { .id = MC13892_GPO2, .init_data = &gpo2_init }, | ||
| 560 | { .id = MC13892_GPO3, .init_data = &gpo3_init }, | ||
| 561 | { .id = MC13892_GPO4, .init_data = &gpo4_init }, | ||
| 562 | { .id = MC13892_PWGT1SPI, .init_data = &pwgt1_init }, | ||
| 563 | { .id = MC13892_PWGT2SPI, .init_data = &pwgt2_init }, | ||
| 564 | { .id = MC13892_VCOINCELL, .init_data = &vcoincell_init }, | ||
| 565 | }; | ||
| 566 | |||
| 567 | static struct mc13xxx_platform_data mx51_efika_mc13892_data = { | ||
| 568 | .flags = MC13XXX_USE_RTC, | ||
| 569 | .regulators = { | ||
| 570 | .num_regulators = ARRAY_SIZE(mx51_efika_regulators), | ||
| 571 | .regulators = mx51_efika_regulators, | ||
| 572 | }, | ||
| 573 | }; | ||
| 574 | |||
| 575 | static struct spi_board_info mx51_efika_spi_board_info[] __initdata = { | ||
| 576 | { | ||
| 577 | .modalias = "m25p80", | ||
| 578 | .max_speed_hz = 25000000, | ||
| 579 | .bus_num = 0, | ||
| 580 | .chip_select = 1, | ||
| 581 | .platform_data = &mx51_efika_spi_flash_data, | ||
| 582 | .irq = -1, | ||
| 583 | }, | ||
| 584 | { | ||
| 585 | .modalias = "mc13892", | ||
| 586 | .max_speed_hz = 1000000, | ||
| 587 | .bus_num = 0, | ||
| 588 | .chip_select = 0, | ||
| 589 | .platform_data = &mx51_efika_mc13892_data, | ||
| 590 | /* irq number is run-time assigned */ | ||
| 591 | }, | ||
| 592 | }; | ||
| 593 | |||
| 594 | static int mx51_efika_spi_cs[] = { | ||
| 595 | EFIKAMX_SPI_CS0, | ||
| 596 | EFIKAMX_SPI_CS1, | ||
| 597 | }; | ||
| 598 | |||
| 599 | static const struct spi_imx_master mx51_efika_spi_pdata __initconst = { | ||
| 600 | .chipselect = mx51_efika_spi_cs, | ||
| 601 | .num_chipselect = ARRAY_SIZE(mx51_efika_spi_cs), | ||
| 602 | }; | ||
| 603 | |||
| 604 | void __init efika_board_common_init(void) | ||
| 605 | { | ||
| 606 | mxc_iomux_v3_setup_multiple_pads(mx51efika_pads, | ||
| 607 | ARRAY_SIZE(mx51efika_pads)); | ||
| 608 | imx51_add_imx_uart(0, &uart_pdata); | ||
| 609 | mx51_efika_usb(); | ||
| 610 | |||
| 611 | /* FIXME: comes from original code. check this. */ | ||
| 612 | if (mx51_revision() < IMX_CHIP_REVISION_2_0) | ||
| 613 | sw2_init.constraints.state_mem.uV = 1100000; | ||
| 614 | else if (mx51_revision() == IMX_CHIP_REVISION_2_0) { | ||
| 615 | sw2_init.constraints.state_mem.uV = 1250000; | ||
| 616 | sw1_init.constraints.state_mem.uV = 1000000; | ||
| 617 | } | ||
| 618 | if (machine_is_mx51_efikasb()) | ||
| 619 | vgen1_init.constraints.max_uV = 1200000; | ||
| 620 | |||
| 621 | gpio_request(EFIKAMX_PMIC, "pmic irq"); | ||
| 622 | gpio_direction_input(EFIKAMX_PMIC); | ||
| 623 | mx51_efika_spi_board_info[1].irq = gpio_to_irq(EFIKAMX_PMIC); | ||
| 624 | spi_register_board_info(mx51_efika_spi_board_info, | ||
| 625 | ARRAY_SIZE(mx51_efika_spi_board_info)); | ||
| 626 | imx51_add_ecspi(0, &mx51_efika_spi_pdata); | ||
| 627 | |||
| 628 | imx51_add_pata_imx(); | ||
| 629 | |||
| 630 | #if defined(CONFIG_CPU_FREQ_IMX) | ||
| 631 | get_cpu_op = mx51_get_cpu_op; | ||
| 632 | #endif | ||
| 633 | } | ||
diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig index 7fddd01b85b9..d697d07a1bf0 100644 --- a/arch/arm/mach-mmp/Kconfig +++ b/arch/arm/mach-mmp/Kconfig | |||
| @@ -108,18 +108,21 @@ endmenu | |||
| 108 | config CPU_PXA168 | 108 | config CPU_PXA168 |
| 109 | bool | 109 | bool |
| 110 | select CPU_MOHAWK | 110 | select CPU_MOHAWK |
| 111 | select COMMON_CLK | ||
| 111 | help | 112 | help |
| 112 | Select code specific to PXA168 | 113 | Select code specific to PXA168 |
| 113 | 114 | ||
| 114 | config CPU_PXA910 | 115 | config CPU_PXA910 |
| 115 | bool | 116 | bool |
| 116 | select CPU_MOHAWK | 117 | select CPU_MOHAWK |
| 118 | select COMMON_CLK | ||
| 117 | help | 119 | help |
| 118 | Select code specific to PXA910 | 120 | Select code specific to PXA910 |
| 119 | 121 | ||
| 120 | config CPU_MMP2 | 122 | config CPU_MMP2 |
| 121 | bool | 123 | bool |
| 122 | select CPU_PJ4 | 124 | select CPU_PJ4 |
| 125 | select COMMON_CLK | ||
| 123 | help | 126 | help |
| 124 | Select code specific to MMP2. MMP2 is ARMv7 compatible. | 127 | Select code specific to MMP2. MMP2 is ARMv7 compatible. |
| 125 | 128 | ||
diff --git a/arch/arm/mach-mmp/mmp2.c b/arch/arm/mach-mmp/mmp2.c index c709a24a9d25..c2bb95cf1a82 100644 --- a/arch/arm/mach-mmp/mmp2.c +++ b/arch/arm/mach-mmp/mmp2.c | |||
| @@ -163,7 +163,7 @@ static int __init mmp2_init(void) | |||
| 163 | { | 163 | { |
| 164 | if (cpu_is_mmp2()) { | 164 | if (cpu_is_mmp2()) { |
| 165 | #ifdef CONFIG_CACHE_TAUROS2 | 165 | #ifdef CONFIG_CACHE_TAUROS2 |
| 166 | tauros2_init(); | 166 | tauros2_init(0); |
| 167 | #endif | 167 | #endif |
| 168 | mfp_init_base(MFPR_VIRT_BASE); | 168 | mfp_init_base(MFPR_VIRT_BASE); |
| 169 | mfp_init_addr(mmp2_addr_map); | 169 | mfp_init_addr(mmp2_addr_map); |
diff --git a/arch/arm/mach-mmp/pxa910.c b/arch/arm/mach-mmp/pxa910.c index 6da52e9f2bdc..51ac8d1898c1 100644 --- a/arch/arm/mach-mmp/pxa910.c +++ b/arch/arm/mach-mmp/pxa910.c | |||
| @@ -14,6 +14,7 @@ | |||
| 14 | #include <linux/io.h> | 14 | #include <linux/io.h> |
| 15 | #include <linux/platform_device.h> | 15 | #include <linux/platform_device.h> |
| 16 | 16 | ||
| 17 | #include <asm/hardware/cache-tauros2.h> | ||
| 17 | #include <asm/mach/time.h> | 18 | #include <asm/mach/time.h> |
| 18 | #include <mach/addr-map.h> | 19 | #include <mach/addr-map.h> |
| 19 | #include <mach/regs-apbc.h> | 20 | #include <mach/regs-apbc.h> |
| @@ -116,6 +117,9 @@ static struct clk_lookup pxa910_clkregs[] = { | |||
| 116 | static int __init pxa910_init(void) | 117 | static int __init pxa910_init(void) |
| 117 | { | 118 | { |
| 118 | if (cpu_is_pxa910()) { | 119 | if (cpu_is_pxa910()) { |
| 120 | #ifdef CONFIG_CACHE_TAUROS2 | ||
| 121 | tauros2_init(0); | ||
| 122 | #endif | ||
| 119 | mfp_init_base(MFPR_VIRT_BASE); | 123 | mfp_init_base(MFPR_VIRT_BASE); |
| 120 | mfp_init_addr(pxa910_mfp_addr_map); | 124 | mfp_init_addr(pxa910_mfp_addr_map); |
| 121 | pxa_init_dma(IRQ_PXA910_DMA_INT0, 32); | 125 | pxa_init_dma(IRQ_PXA910_DMA_INT0, 32); |
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig index 1cd40ad301d3..b2740c800e8c 100644 --- a/arch/arm/mach-msm/Kconfig +++ b/arch/arm/mach-msm/Kconfig | |||
| @@ -38,8 +38,6 @@ config ARCH_QSD8X50 | |||
| 38 | 38 | ||
| 39 | config ARCH_MSM8X60 | 39 | config ARCH_MSM8X60 |
| 40 | bool "MSM8X60" | 40 | bool "MSM8X60" |
| 41 | select MACH_MSM8X60_SURF if (!MACH_MSM8X60_RUMI3 && !MACH_MSM8X60_SIM \ | ||
| 42 | && !MACH_MSM8X60_FFA) | ||
| 43 | select ARCH_MSM_SCORPIONMP | 41 | select ARCH_MSM_SCORPIONMP |
| 44 | select ARM_GIC | 42 | select ARM_GIC |
| 45 | select CPU_V7 | 43 | select CPU_V7 |
| @@ -47,16 +45,17 @@ config ARCH_MSM8X60 | |||
| 47 | select GPIO_MSM_V2 | 45 | select GPIO_MSM_V2 |
| 48 | select MSM_GPIOMUX | 46 | select MSM_GPIOMUX |
| 49 | select MSM_SCM if SMP | 47 | select MSM_SCM if SMP |
| 48 | select USE_OF | ||
| 50 | 49 | ||
| 51 | config ARCH_MSM8960 | 50 | config ARCH_MSM8960 |
| 52 | bool "MSM8960" | 51 | bool "MSM8960" |
| 53 | select ARCH_MSM_SCORPIONMP | 52 | select ARCH_MSM_SCORPIONMP |
| 54 | select MACH_MSM8960_SIM if (!MACH_MSM8960_RUMI3) | ||
| 55 | select ARM_GIC | 53 | select ARM_GIC |
| 56 | select CPU_V7 | 54 | select CPU_V7 |
| 57 | select MSM_V2_TLMM | 55 | select MSM_V2_TLMM |
| 58 | select MSM_GPIOMUX | 56 | select MSM_GPIOMUX |
| 59 | select MSM_SCM if SMP | 57 | select MSM_SCM if SMP |
| 58 | select USE_OF | ||
| 60 | 59 | ||
| 61 | endchoice | 60 | endchoice |
| 62 | 61 | ||
| @@ -112,42 +111,6 @@ config MACH_QSD8X50A_ST1_5 | |||
| 112 | help | 111 | help |
| 113 | Support for the Qualcomm ST1.5. | 112 | Support for the Qualcomm ST1.5. |
| 114 | 113 | ||
| 115 | config MACH_MSM8X60_RUMI3 | ||
| 116 | depends on ARCH_MSM8X60 | ||
| 117 | bool "MSM8x60 RUMI3" | ||
| 118 | help | ||
| 119 | Support for the Qualcomm MSM8x60 RUMI3 emulator. | ||
| 120 | |||
| 121 | config MACH_MSM8X60_SURF | ||
| 122 | depends on ARCH_MSM8X60 | ||
| 123 | bool "MSM8x60 SURF" | ||
| 124 | help | ||
| 125 | Support for the Qualcomm MSM8x60 SURF eval board. | ||
| 126 | |||
| 127 | config MACH_MSM8X60_SIM | ||
| 128 | depends on ARCH_MSM8X60 | ||
| 129 | bool "MSM8x60 Simulator" | ||
| 130 | help | ||
| 131 | Support for the Qualcomm MSM8x60 simulator. | ||
| 132 | |||
| 133 | config MACH_MSM8X60_FFA | ||
| 134 | depends on ARCH_MSM8X60 | ||
| 135 | bool "MSM8x60 FFA" | ||
| 136 | help | ||
| 137 | Support for the Qualcomm MSM8x60 FFA eval board. | ||
| 138 | |||
| 139 | config MACH_MSM8960_SIM | ||
| 140 | depends on ARCH_MSM8960 | ||
| 141 | bool "MSM8960 Simulator" | ||
| 142 | help | ||
| 143 | Support for the Qualcomm MSM8960 simulator. | ||
| 144 | |||
| 145 | config MACH_MSM8960_RUMI3 | ||
| 146 | depends on ARCH_MSM8960 | ||
| 147 | bool "MSM8960 RUMI3" | ||
| 148 | help | ||
| 149 | Support for the Qualcomm MSM8960 RUMI3 emulator. | ||
| 150 | |||
| 151 | endmenu | 114 | endmenu |
| 152 | 115 | ||
| 153 | config MSM_SMD_PKG3 | 116 | config MSM_SMD_PKG3 |
diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile index 4ad3969b9881..17519faf082f 100644 --- a/arch/arm/mach-msm/Makefile +++ b/arch/arm/mach-msm/Makefile | |||
| @@ -1,11 +1,11 @@ | |||
| 1 | obj-y += io.o idle.o timer.o | 1 | obj-y += io.o timer.o |
| 2 | obj-y += clock.o | 2 | obj-y += clock.o |
| 3 | obj-$(CONFIG_DEBUG_FS) += clock-debug.o | 3 | obj-$(CONFIG_DEBUG_FS) += clock-debug.o |
| 4 | 4 | ||
| 5 | obj-$(CONFIG_MSM_VIC) += irq-vic.o | 5 | obj-$(CONFIG_MSM_VIC) += irq-vic.o |
| 6 | obj-$(CONFIG_MSM_IOMMU) += devices-iommu.o | 6 | obj-$(CONFIG_MSM_IOMMU) += devices-iommu.o |
| 7 | 7 | ||
| 8 | obj-$(CONFIG_ARCH_MSM7X00A) += dma.o irq.o acpuclock-arm11.o | 8 | obj-$(CONFIG_ARCH_MSM7X00A) += dma.o irq.o |
| 9 | obj-$(CONFIG_ARCH_MSM7X30) += dma.o | 9 | obj-$(CONFIG_ARCH_MSM7X30) += dma.o |
| 10 | obj-$(CONFIG_ARCH_QSD8X50) += dma.o sirc.o | 10 | obj-$(CONFIG_ARCH_QSD8X50) += dma.o sirc.o |
| 11 | 11 | ||
| @@ -25,8 +25,8 @@ obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o board-trout-mmc.o b | |||
| 25 | obj-$(CONFIG_MACH_HALIBUT) += board-halibut.o devices-msm7x00.o | 25 | obj-$(CONFIG_MACH_HALIBUT) += board-halibut.o devices-msm7x00.o |
| 26 | obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o | 26 | obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o |
| 27 | obj-$(CONFIG_ARCH_QSD8X50) += board-qsd8x50.o devices-qsd8x50.o | 27 | obj-$(CONFIG_ARCH_QSD8X50) += board-qsd8x50.o devices-qsd8x50.o |
| 28 | obj-$(CONFIG_ARCH_MSM8X60) += board-msm8x60.o | 28 | obj-$(CONFIG_ARCH_MSM8X60) += board-dt-8660.o |
| 29 | obj-$(CONFIG_ARCH_MSM8960) += board-msm8960.o devices-msm8960.o | 29 | obj-$(CONFIG_ARCH_MSM8960) += board-dt-8960.o |
| 30 | 30 | ||
| 31 | obj-$(CONFIG_ARCH_MSM7X30) += gpiomux-v1.o gpiomux.o | 31 | obj-$(CONFIG_ARCH_MSM7X30) += gpiomux-v1.o gpiomux.o |
| 32 | obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-8x50.o gpiomux-v1.o gpiomux.o | 32 | obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-8x50.o gpiomux-v1.o gpiomux.o |
diff --git a/arch/arm/mach-msm/Makefile.boot b/arch/arm/mach-msm/Makefile.boot index 9b803a578b4d..f7d6ae9c3487 100644 --- a/arch/arm/mach-msm/Makefile.boot +++ b/arch/arm/mach-msm/Makefile.boot | |||
| @@ -1,3 +1,6 @@ | |||
| 1 | zreladdr-y += 0x10008000 | 1 | zreladdr-y += 0x10008000 |
| 2 | params_phys-y := 0x10000100 | 2 | params_phys-y := 0x10000100 |
| 3 | initrd_phys-y := 0x10800000 | 3 | initrd_phys-y := 0x10800000 |
| 4 | |||
| 5 | dtb-$(CONFIG_ARCH_MSM8X60) += msm8660-surf.dtb | ||
| 6 | dtb-$(CONFIG_ARCH_MSM8960) += msm8960-cdp.dtb | ||
diff --git a/arch/arm/mach-msm/acpuclock-arm11.c b/arch/arm/mach-msm/acpuclock-arm11.c deleted file mode 100644 index 805d4ee53f7e..000000000000 --- a/arch/arm/mach-msm/acpuclock-arm11.c +++ /dev/null | |||
| @@ -1,525 +0,0 @@ | |||
| 1 | /* arch/arm/mach-msm/acpuclock.c | ||
| 2 | * | ||
| 3 | * MSM architecture clock driver | ||
| 4 | * | ||
| 5 | * Copyright (C) 2007 Google, Inc. | ||
| 6 | * Copyright (c) 2007 QUALCOMM Incorporated | ||
| 7 | * Author: San Mehat <san@android.com> | ||
| 8 | * | ||
| 9 | * This software is licensed under the terms of the GNU General Public | ||
| 10 | * License version 2, as published by the Free Software Foundation, and | ||
| 11 | * may be copied, distributed, and modified under those terms. | ||
| 12 | * | ||
| 13 | * This program is distributed in the hope that it will be useful, | ||
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 16 | * GNU General Public License for more details. | ||
| 17 | * | ||
| 18 | */ | ||
| 19 | |||
| 20 | #include <linux/kernel.h> | ||
| 21 | #include <linux/init.h> | ||
| 22 | #include <linux/list.h> | ||
| 23 | #include <linux/errno.h> | ||
| 24 | #include <linux/string.h> | ||
| 25 | #include <linux/delay.h> | ||
| 26 | #include <linux/clk.h> | ||
| 27 | #include <linux/cpufreq.h> | ||
| 28 | #include <linux/mutex.h> | ||
| 29 | #include <linux/io.h> | ||
| 30 | #include <mach/board.h> | ||
| 31 | #include <mach/msm_iomap.h> | ||
| 32 | |||
| 33 | #include "proc_comm.h" | ||
| 34 | #include "acpuclock.h" | ||
| 35 | |||
| 36 | |||
| 37 | #define A11S_CLK_CNTL_ADDR (MSM_CSR_BASE + 0x100) | ||
| 38 | #define A11S_CLK_SEL_ADDR (MSM_CSR_BASE + 0x104) | ||
| 39 | #define A11S_VDD_SVS_PLEVEL_ADDR (MSM_CSR_BASE + 0x124) | ||
| 40 | |||
| 41 | /* | ||
| 42 | * ARM11 clock configuration for specific ACPU speeds | ||
| 43 | */ | ||
| 44 | |||
| 45 | #define ACPU_PLL_TCXO -1 | ||
| 46 | #define ACPU_PLL_0 0 | ||
| 47 | #define ACPU_PLL_1 1 | ||
| 48 | #define ACPU_PLL_2 2 | ||
| 49 | #define ACPU_PLL_3 3 | ||
| 50 | |||
| 51 | #define PERF_SWITCH_DEBUG 0 | ||
| 52 | #define PERF_SWITCH_STEP_DEBUG 0 | ||
| 53 | |||
| 54 | struct clock_state | ||
| 55 | { | ||
| 56 | struct clkctl_acpu_speed *current_speed; | ||
| 57 | struct mutex lock; | ||
| 58 | uint32_t acpu_switch_time_us; | ||
| 59 | uint32_t max_speed_delta_khz; | ||
| 60 | uint32_t vdd_switch_time_us; | ||
| 61 | unsigned long power_collapse_khz; | ||
| 62 | unsigned long wait_for_irq_khz; | ||
| 63 | }; | ||
| 64 | |||
| 65 | static struct clk *ebi1_clk; | ||
| 66 | static struct clock_state drv_state = { 0 }; | ||
| 67 | |||
| 68 | static void __init acpuclk_init(void); | ||
| 69 | |||
| 70 | /* MSM7201A Levels 3-6 all correspond to 1.2V, level 7 corresponds to 1.325V. */ | ||
| 71 | enum { | ||
| 72 | VDD_0 = 0, | ||
| 73 | VDD_1 = 1, | ||
| 74 | VDD_2 = 2, | ||
| 75 | VDD_3 = 3, | ||
| 76 | VDD_4 = 3, | ||
| 77 | VDD_5 = 3, | ||
| 78 | VDD_6 = 3, | ||
| 79 | VDD_7 = 7, | ||
| 80 | VDD_END | ||
| 81 | }; | ||
| 82 | |||
| 83 | struct clkctl_acpu_speed { | ||
| 84 | unsigned int a11clk_khz; | ||
| 85 | int pll; | ||
| 86 | unsigned int a11clk_src_sel; | ||
| 87 | unsigned int a11clk_src_div; | ||
| 88 | unsigned int ahbclk_khz; | ||
| 89 | unsigned int ahbclk_div; | ||
| 90 | int vdd; | ||
| 91 | unsigned int axiclk_khz; | ||
| 92 | unsigned long lpj; /* loops_per_jiffy */ | ||
| 93 | /* Index in acpu_freq_tbl[] for steppings. */ | ||
| 94 | short down; | ||
| 95 | short up; | ||
| 96 | }; | ||
| 97 | |||
| 98 | /* | ||
| 99 | * ACPU speed table. Complete table is shown but certain speeds are commented | ||
| 100 | * out to optimized speed switching. Initialize loops_per_jiffy to 0. | ||
| 101 | * | ||
| 102 | * Table stepping up/down is optimized for 256mhz jumps while staying on the | ||
| 103 | * same PLL. | ||
| 104 | */ | ||
| 105 | #if (0) | ||
| 106 | static struct clkctl_acpu_speed acpu_freq_tbl[] = { | ||
| 107 | { 19200, ACPU_PLL_TCXO, 0, 0, 19200, 0, VDD_0, 30720, 0, 0, 8 }, | ||
| 108 | { 61440, ACPU_PLL_0, 4, 3, 61440, 0, VDD_0, 30720, 0, 0, 8 }, | ||
| 109 | { 81920, ACPU_PLL_0, 4, 2, 40960, 1, VDD_0, 61440, 0, 0, 8 }, | ||
| 110 | { 96000, ACPU_PLL_1, 1, 7, 48000, 1, VDD_0, 61440, 0, 0, 9 }, | ||
| 111 | { 122880, ACPU_PLL_0, 4, 1, 61440, 1, VDD_3, 61440, 0, 0, 8 }, | ||
| 112 | { 128000, ACPU_PLL_1, 1, 5, 64000, 1, VDD_3, 61440, 0, 0, 12 }, | ||
| 113 | { 176000, ACPU_PLL_2, 2, 5, 88000, 1, VDD_3, 61440, 0, 0, 11 }, | ||
| 114 | { 192000, ACPU_PLL_1, 1, 3, 64000, 2, VDD_3, 61440, 0, 0, 12 }, | ||
| 115 | { 245760, ACPU_PLL_0, 4, 0, 81920, 2, VDD_4, 61440, 0, 0, 12 }, | ||
| 116 | { 256000, ACPU_PLL_1, 1, 2, 128000, 2, VDD_5, 128000, 0, 0, 12 }, | ||
| 117 | { 264000, ACPU_PLL_2, 2, 3, 88000, 2, VDD_5, 128000, 0, 6, 13 }, | ||
| 118 | { 352000, ACPU_PLL_2, 2, 2, 88000, 3, VDD_5, 128000, 0, 6, 13 }, | ||
| 119 | { 384000, ACPU_PLL_1, 1, 1, 128000, 2, VDD_6, 128000, 0, 5, -1 }, | ||
| 120 | { 528000, ACPU_PLL_2, 2, 1, 132000, 3, VDD_7, 128000, 0, 11, -1 }, | ||
| 121 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, | ||
| 122 | }; | ||
| 123 | #else /* Table of freq we currently use. */ | ||
| 124 | static struct clkctl_acpu_speed acpu_freq_tbl[] = { | ||
| 125 | { 19200, ACPU_PLL_TCXO, 0, 0, 19200, 0, VDD_0, 30720, 0, 0, 4 }, | ||
| 126 | { 122880, ACPU_PLL_0, 4, 1, 61440, 1, VDD_3, 61440, 0, 0, 4 }, | ||
| 127 | { 128000, ACPU_PLL_1, 1, 5, 64000, 1, VDD_3, 61440, 0, 0, 6 }, | ||
| 128 | { 176000, ACPU_PLL_2, 2, 5, 88000, 1, VDD_3, 61440, 0, 0, 5 }, | ||
| 129 | { 245760, ACPU_PLL_0, 4, 0, 81920, 2, VDD_4, 61440, 0, 0, 5 }, | ||
| 130 | { 352000, ACPU_PLL_2, 2, 2, 88000, 3, VDD_5, 128000, 0, 3, 7 }, | ||
| 131 | { 384000, ACPU_PLL_1, 1, 1, 128000, 2, VDD_6, 128000, 0, 2, -1 }, | ||
| 132 | { 528000, ACPU_PLL_2, 2, 1, 132000, 3, VDD_7, 128000, 0, 5, -1 }, | ||
| 133 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, | ||
| 134 | }; | ||
| 135 | #endif | ||
| 136 | |||
| 137 | |||
| 138 | #ifdef CONFIG_CPU_FREQ_TABLE | ||
| 139 | static struct cpufreq_frequency_table freq_table[] = { | ||
| 140 | { 0, 122880 }, | ||
| 141 | { 1, 128000 }, | ||
| 142 | { 2, 245760 }, | ||
| 143 | { 3, 384000 }, | ||
| 144 | { 4, 528000 }, | ||
| 145 | { 5, CPUFREQ_TABLE_END }, | ||
| 146 | }; | ||
| 147 | #endif | ||
| 148 | |||
| 149 | static int pc_pll_request(unsigned id, unsigned on) | ||
| 150 | { | ||
| 151 | int res; | ||
| 152 | on = !!on; | ||
| 153 | |||
| 154 | #if PERF_SWITCH_DEBUG | ||
| 155 | if (on) | ||
| 156 | printk(KERN_DEBUG "Enabling PLL %d\n", id); | ||
| 157 | else | ||
| 158 | printk(KERN_DEBUG "Disabling PLL %d\n", id); | ||
| 159 | #endif | ||
| 160 | |||
| 161 | res = msm_proc_comm(PCOM_CLKCTL_RPC_PLL_REQUEST, &id, &on); | ||
| 162 | if (res < 0) | ||
| 163 | return res; | ||
| 164 | |||
| 165 | #if PERF_SWITCH_DEBUG | ||
| 166 | if (on) | ||
| 167 | printk(KERN_DEBUG "PLL %d enabled\n", id); | ||
| 168 | else | ||
| 169 | printk(KERN_DEBUG "PLL %d disabled\n", id); | ||
| 170 | #endif | ||
| 171 | return res; | ||
| 172 | } | ||
| 173 | |||
| 174 | |||
| 175 | /*---------------------------------------------------------------------------- | ||
| 176 | * ARM11 'owned' clock control | ||
| 177 | *---------------------------------------------------------------------------*/ | ||
| 178 | |||
| 179 | unsigned long acpuclk_power_collapse(void) { | ||
| 180 | int ret = acpuclk_get_rate(); | ||
| 181 | ret *= 1000; | ||
| 182 | if (ret > drv_state.power_collapse_khz) | ||
| 183 | acpuclk_set_rate(drv_state.power_collapse_khz, 1); | ||
| 184 | return ret; | ||
| 185 | } | ||
| 186 | |||
| 187 | unsigned long acpuclk_get_wfi_rate(void) | ||
| 188 | { | ||
| 189 | return drv_state.wait_for_irq_khz; | ||
| 190 | } | ||
| 191 | |||
| 192 | unsigned long acpuclk_wait_for_irq(void) { | ||
| 193 | int ret = acpuclk_get_rate(); | ||
| 194 | ret *= 1000; | ||
| 195 | if (ret > drv_state.wait_for_irq_khz) | ||
| 196 | acpuclk_set_rate(drv_state.wait_for_irq_khz, 1); | ||
| 197 | return ret; | ||
| 198 | } | ||
| 199 | |||
| 200 | static int acpuclk_set_vdd_level(int vdd) | ||
| 201 | { | ||
| 202 | uint32_t current_vdd; | ||
| 203 | |||
| 204 | current_vdd = readl(A11S_VDD_SVS_PLEVEL_ADDR) & 0x07; | ||
| 205 | |||
| 206 | #if PERF_SWITCH_DEBUG | ||
| 207 | printk(KERN_DEBUG "acpuclock: Switching VDD from %u -> %d\n", | ||
| 208 | current_vdd, vdd); | ||
| 209 | #endif | ||
| 210 | writel((1 << 7) | (vdd << 3), A11S_VDD_SVS_PLEVEL_ADDR); | ||
| 211 | udelay(drv_state.vdd_switch_time_us); | ||
| 212 | if ((readl(A11S_VDD_SVS_PLEVEL_ADDR) & 0x7) != vdd) { | ||
| 213 | #if PERF_SWITCH_DEBUG | ||
| 214 | printk(KERN_ERR "acpuclock: VDD set failed\n"); | ||
| 215 | #endif | ||
| 216 | return -EIO; | ||
| 217 | } | ||
| 218 | |||
| 219 | #if PERF_SWITCH_DEBUG | ||
| 220 | printk(KERN_DEBUG "acpuclock: VDD switched\n"); | ||
| 221 | #endif | ||
| 222 | return 0; | ||
| 223 | } | ||
| 224 | |||
| 225 | /* Set proper dividers for the given clock speed. */ | ||
| 226 | static void acpuclk_set_div(const struct clkctl_acpu_speed *hunt_s) { | ||
| 227 | uint32_t reg_clkctl, reg_clksel, clk_div; | ||
| 228 | |||
| 229 | /* AHB_CLK_DIV */ | ||
| 230 | clk_div = (readl(A11S_CLK_SEL_ADDR) >> 1) & 0x03; | ||
| 231 | /* | ||
| 232 | * If the new clock divider is higher than the previous, then | ||
| 233 | * program the divider before switching the clock | ||
| 234 | */ | ||
| 235 | if (hunt_s->ahbclk_div > clk_div) { | ||
| 236 | reg_clksel = readl(A11S_CLK_SEL_ADDR); | ||
| 237 | reg_clksel &= ~(0x3 << 1); | ||
| 238 | reg_clksel |= (hunt_s->ahbclk_div << 1); | ||
| 239 | writel(reg_clksel, A11S_CLK_SEL_ADDR); | ||
| 240 | } | ||
| 241 | if ((readl(A11S_CLK_SEL_ADDR) & 0x01) == 0) { | ||
| 242 | /* SRC0 */ | ||
| 243 | |||
| 244 | /* Program clock source */ | ||
| 245 | reg_clkctl = readl(A11S_CLK_CNTL_ADDR); | ||
| 246 | reg_clkctl &= ~(0x07 << 4); | ||
| 247 | reg_clkctl |= (hunt_s->a11clk_src_sel << 4); | ||
| 248 | writel(reg_clkctl, A11S_CLK_CNTL_ADDR); | ||
| 249 | |||
| 250 | /* Program clock divider */ | ||
| 251 | reg_clkctl = readl(A11S_CLK_CNTL_ADDR); | ||
| 252 | reg_clkctl &= ~0xf; | ||
| 253 | reg_clkctl |= hunt_s->a11clk_src_div; | ||
| 254 | writel(reg_clkctl, A11S_CLK_CNTL_ADDR); | ||
| 255 | |||
| 256 | /* Program clock source selection */ | ||
| 257 | reg_clksel = readl(A11S_CLK_SEL_ADDR); | ||
| 258 | reg_clksel |= 1; /* CLK_SEL_SRC1NO == SRC1 */ | ||
| 259 | writel(reg_clksel, A11S_CLK_SEL_ADDR); | ||
| 260 | } else { | ||
| 261 | /* SRC1 */ | ||
| 262 | |||
| 263 | /* Program clock source */ | ||
| 264 | reg_clkctl = readl(A11S_CLK_CNTL_ADDR); | ||
| 265 | reg_clkctl &= ~(0x07 << 12); | ||
| 266 | reg_clkctl |= (hunt_s->a11clk_src_sel << 12); | ||
| 267 | writel(reg_clkctl, A11S_CLK_CNTL_ADDR); | ||
| 268 | |||
| 269 | /* Program clock divider */ | ||
| 270 | reg_clkctl = readl(A11S_CLK_CNTL_ADDR); | ||
| 271 | reg_clkctl &= ~(0xf << 8); | ||
| 272 | reg_clkctl |= (hunt_s->a11clk_src_div << 8); | ||
| 273 | writel(reg_clkctl, A11S_CLK_CNTL_ADDR); | ||
| 274 | |||
| 275 | /* Program clock source selection */ | ||
| 276 | reg_clksel = readl(A11S_CLK_SEL_ADDR); | ||
| 277 | reg_clksel &= ~1; /* CLK_SEL_SRC1NO == SRC0 */ | ||
| 278 | writel(reg_clksel, A11S_CLK_SEL_ADDR); | ||
| 279 | } | ||
| 280 | |||
| 281 | /* | ||
| 282 | * If the new clock divider is lower than the previous, then | ||
| 283 | * program the divider after switching the clock | ||
| 284 | */ | ||
| 285 | if (hunt_s->ahbclk_div < clk_div) { | ||
| 286 | reg_clksel = readl(A11S_CLK_SEL_ADDR); | ||
| 287 | reg_clksel &= ~(0x3 << 1); | ||
| 288 | reg_clksel |= (hunt_s->ahbclk_div << 1); | ||
| 289 | writel(reg_clksel, A11S_CLK_SEL_ADDR); | ||
| 290 | } | ||
| 291 | } | ||
| 292 | |||
| 293 | int acpuclk_set_rate(unsigned long rate, int for_power_collapse) | ||
| 294 | { | ||
| 295 | uint32_t reg_clkctl; | ||
| 296 | struct clkctl_acpu_speed *cur_s, *tgt_s, *strt_s; | ||
| 297 | int rc = 0; | ||
| 298 | unsigned int plls_enabled = 0, pll; | ||
| 299 | |||
| 300 | strt_s = cur_s = drv_state.current_speed; | ||
| 301 | |||
| 302 | WARN_ONCE(cur_s == NULL, "acpuclk_set_rate: not initialized\n"); | ||
| 303 | if (cur_s == NULL) | ||
| 304 | return -ENOENT; | ||
| 305 | |||
| 306 | if (rate == (cur_s->a11clk_khz * 1000)) | ||
| 307 | return 0; | ||
| 308 | |||
| 309 | for (tgt_s = acpu_freq_tbl; tgt_s->a11clk_khz != 0; tgt_s++) { | ||
| 310 | if (tgt_s->a11clk_khz == (rate / 1000)) | ||
| 311 | break; | ||
| 312 | } | ||
| 313 | |||
| 314 | if (tgt_s->a11clk_khz == 0) | ||
| 315 | return -EINVAL; | ||
| 316 | |||
| 317 | /* Choose the highest speed speed at or below 'rate' with same PLL. */ | ||
| 318 | if (for_power_collapse && tgt_s->a11clk_khz < cur_s->a11clk_khz) { | ||
| 319 | while (tgt_s->pll != ACPU_PLL_TCXO && tgt_s->pll != cur_s->pll) | ||
| 320 | tgt_s--; | ||
| 321 | } | ||
| 322 | |||
| 323 | if (strt_s->pll != ACPU_PLL_TCXO) | ||
| 324 | plls_enabled |= 1 << strt_s->pll; | ||
| 325 | |||
| 326 | if (!for_power_collapse) { | ||
| 327 | mutex_lock(&drv_state.lock); | ||
| 328 | if (strt_s->pll != tgt_s->pll && tgt_s->pll != ACPU_PLL_TCXO) { | ||
| 329 | rc = pc_pll_request(tgt_s->pll, 1); | ||
| 330 | if (rc < 0) { | ||
| 331 | pr_err("PLL%d enable failed (%d)\n", | ||
| 332 | tgt_s->pll, rc); | ||
| 333 | goto out; | ||
| 334 | } | ||
| 335 | plls_enabled |= 1 << tgt_s->pll; | ||
| 336 | } | ||
| 337 | /* Increase VDD if needed. */ | ||
| 338 | if (tgt_s->vdd > cur_s->vdd) { | ||
| 339 | if ((rc = acpuclk_set_vdd_level(tgt_s->vdd)) < 0) { | ||
| 340 | printk(KERN_ERR "Unable to switch ACPU vdd\n"); | ||
| 341 | goto out; | ||
| 342 | } | ||
| 343 | } | ||
| 344 | } | ||
| 345 | |||
| 346 | /* Set wait states for CPU between frequency changes */ | ||
| 347 | reg_clkctl = readl(A11S_CLK_CNTL_ADDR); | ||
| 348 | reg_clkctl |= (100 << 16); /* set WT_ST_CNT */ | ||
| 349 | writel(reg_clkctl, A11S_CLK_CNTL_ADDR); | ||
| 350 | |||
| 351 | #if PERF_SWITCH_DEBUG | ||
| 352 | printk(KERN_INFO "acpuclock: Switching from ACPU rate %u -> %u\n", | ||
| 353 | strt_s->a11clk_khz * 1000, tgt_s->a11clk_khz * 1000); | ||
| 354 | #endif | ||
| 355 | |||
| 356 | while (cur_s != tgt_s) { | ||
| 357 | /* | ||
| 358 | * Always jump to target freq if within 256mhz, regulardless of | ||
| 359 | * PLL. If differnece is greater, use the predefinied | ||
| 360 | * steppings in the table. | ||
| 361 | */ | ||
| 362 | int d = abs((int)(cur_s->a11clk_khz - tgt_s->a11clk_khz)); | ||
| 363 | if (d > drv_state.max_speed_delta_khz) { | ||
| 364 | /* Step up or down depending on target vs current. */ | ||
| 365 | int clk_index = tgt_s->a11clk_khz > cur_s->a11clk_khz ? | ||
| 366 | cur_s->up : cur_s->down; | ||
| 367 | if (clk_index < 0) { /* This should not happen. */ | ||
| 368 | printk(KERN_ERR "cur:%u target: %u\n", | ||
| 369 | cur_s->a11clk_khz, tgt_s->a11clk_khz); | ||
| 370 | rc = -EINVAL; | ||
| 371 | goto out; | ||
| 372 | } | ||
| 373 | cur_s = &acpu_freq_tbl[clk_index]; | ||
| 374 | } else { | ||
| 375 | cur_s = tgt_s; | ||
| 376 | } | ||
| 377 | #if PERF_SWITCH_STEP_DEBUG | ||
| 378 | printk(KERN_DEBUG "%s: STEP khz = %u, pll = %d\n", | ||
| 379 | __FUNCTION__, cur_s->a11clk_khz, cur_s->pll); | ||
| 380 | #endif | ||
| 381 | if (!for_power_collapse&& cur_s->pll != ACPU_PLL_TCXO | ||
| 382 | && !(plls_enabled & (1 << cur_s->pll))) { | ||
| 383 | rc = pc_pll_request(cur_s->pll, 1); | ||
| 384 | if (rc < 0) { | ||
| 385 | pr_err("PLL%d enable failed (%d)\n", | ||
| 386 | cur_s->pll, rc); | ||
| 387 | goto out; | ||
| 388 | } | ||
| 389 | plls_enabled |= 1 << cur_s->pll; | ||
| 390 | } | ||
| 391 | |||
| 392 | acpuclk_set_div(cur_s); | ||
| 393 | drv_state.current_speed = cur_s; | ||
| 394 | /* Re-adjust lpj for the new clock speed. */ | ||
| 395 | loops_per_jiffy = cur_s->lpj; | ||
| 396 | udelay(drv_state.acpu_switch_time_us); | ||
| 397 | } | ||
| 398 | |||
| 399 | /* Nothing else to do for power collapse. */ | ||
| 400 | if (for_power_collapse) | ||
| 401 | return 0; | ||
| 402 | |||
| 403 | /* Disable PLLs we are not using anymore. */ | ||
| 404 | plls_enabled &= ~(1 << tgt_s->pll); | ||
| 405 | for (pll = ACPU_PLL_0; pll <= ACPU_PLL_2; pll++) | ||
| 406 | if (plls_enabled & (1 << pll)) { | ||
| 407 | rc = pc_pll_request(pll, 0); | ||
| 408 | if (rc < 0) { | ||
| 409 | pr_err("PLL%d disable failed (%d)\n", pll, rc); | ||
| 410 | goto out; | ||
| 411 | } | ||
| 412 | } | ||
| 413 | |||
| 414 | /* Change the AXI bus frequency if we can. */ | ||
| 415 | if (strt_s->axiclk_khz != tgt_s->axiclk_khz) { | ||
| 416 | rc = clk_set_rate(ebi1_clk, tgt_s->axiclk_khz * 1000); | ||
| 417 | if (rc < 0) | ||
| 418 | pr_err("Setting AXI min rate failed!\n"); | ||
| 419 | } | ||
| 420 | |||
| 421 | /* Drop VDD level if we can. */ | ||
| 422 | if (tgt_s->vdd < strt_s->vdd) { | ||
| 423 | if (acpuclk_set_vdd_level(tgt_s->vdd) < 0) | ||
| 424 | printk(KERN_ERR "acpuclock: Unable to drop ACPU vdd\n"); | ||
| 425 | } | ||
| 426 | |||
| 427 | #if PERF_SWITCH_DEBUG | ||
| 428 | printk(KERN_DEBUG "%s: ACPU speed change complete\n", __FUNCTION__); | ||
| 429 | #endif | ||
| 430 | out: | ||
| 431 | if (!for_power_collapse) | ||
| 432 | mutex_unlock(&drv_state.lock); | ||
| 433 | return rc; | ||
| 434 | } | ||
| 435 | |||
| 436 | static void __init acpuclk_init(void) | ||
| 437 | { | ||
| 438 | struct clkctl_acpu_speed *speed; | ||
| 439 | uint32_t div, sel; | ||
| 440 | int rc; | ||
| 441 | |||
| 442 | /* | ||
| 443 | * Determine the rate of ACPU clock | ||
| 444 | */ | ||
| 445 | |||
| 446 | if (!(readl(A11S_CLK_SEL_ADDR) & 0x01)) { /* CLK_SEL_SRC1N0 */ | ||
| 447 | /* CLK_SRC0_SEL */ | ||
| 448 | sel = (readl(A11S_CLK_CNTL_ADDR) >> 12) & 0x7; | ||
| 449 | /* CLK_SRC0_DIV */ | ||
| 450 | div = (readl(A11S_CLK_CNTL_ADDR) >> 8) & 0x0f; | ||
| 451 | } else { | ||
| 452 | /* CLK_SRC1_SEL */ | ||
| 453 | sel = (readl(A11S_CLK_CNTL_ADDR) >> 4) & 0x07; | ||
| 454 | /* CLK_SRC1_DIV */ | ||
| 455 | div = readl(A11S_CLK_CNTL_ADDR) & 0x0f; | ||
| 456 | } | ||
| 457 | |||
| 458 | for (speed = acpu_freq_tbl; speed->a11clk_khz != 0; speed++) { | ||
| 459 | if (speed->a11clk_src_sel == sel | ||
| 460 | && (speed->a11clk_src_div == div)) | ||
| 461 | break; | ||
| 462 | } | ||
| 463 | if (speed->a11clk_khz == 0) { | ||
| 464 | printk(KERN_WARNING "Warning - ACPU clock reports invalid speed\n"); | ||
| 465 | return; | ||
| 466 | } | ||
| 467 | |||
| 468 | drv_state.current_speed = speed; | ||
| 469 | |||
| 470 | rc = clk_set_rate(ebi1_clk, speed->axiclk_khz * 1000); | ||
| 471 | if (rc < 0) | ||
| 472 | pr_err("Setting AXI min rate failed!\n"); | ||
| 473 | |||
| 474 | printk(KERN_INFO "ACPU running at %d KHz\n", speed->a11clk_khz); | ||
| 475 | } | ||
| 476 | |||
| 477 | unsigned long acpuclk_get_rate(void) | ||
| 478 | { | ||
| 479 | WARN_ONCE(drv_state.current_speed == NULL, | ||
| 480 | "acpuclk_get_rate: not initialized\n"); | ||
| 481 | if (drv_state.current_speed) | ||
| 482 | return drv_state.current_speed->a11clk_khz; | ||
| 483 | else | ||
| 484 | return 0; | ||
| 485 | } | ||
| 486 | |||
| 487 | uint32_t acpuclk_get_switch_time(void) | ||
| 488 | { | ||
| 489 | return drv_state.acpu_switch_time_us; | ||
| 490 | } | ||
| 491 | |||
| 492 | /*---------------------------------------------------------------------------- | ||
| 493 | * Clock driver initialization | ||
| 494 | *---------------------------------------------------------------------------*/ | ||
| 495 | |||
| 496 | /* Initialize the lpj field in the acpu_freq_tbl. */ | ||
| 497 | static void __init lpj_init(void) | ||
| 498 | { | ||
| 499 | int i; | ||
| 500 | const struct clkctl_acpu_speed *base_clk = drv_state.current_speed; | ||
| 501 | for (i = 0; acpu_freq_tbl[i].a11clk_khz; i++) { | ||
| 502 | acpu_freq_tbl[i].lpj = cpufreq_scale(loops_per_jiffy, | ||
| 503 | base_clk->a11clk_khz, | ||
| 504 | acpu_freq_tbl[i].a11clk_khz); | ||
| 505 | } | ||
| 506 | } | ||
| 507 | |||
| 508 | void __init msm_acpu_clock_init(struct msm_acpu_clock_platform_data *clkdata) | ||
| 509 | { | ||
| 510 | pr_info("acpu_clock_init()\n"); | ||
| 511 | |||
| 512 | ebi1_clk = clk_get(NULL, "ebi1_clk"); | ||
| 513 | |||
| 514 | mutex_init(&drv_state.lock); | ||
| 515 | drv_state.acpu_switch_time_us = clkdata->acpu_switch_time_us; | ||
| 516 | drv_state.max_speed_delta_khz = clkdata->max_speed_delta_khz; | ||
| 517 | drv_state.vdd_switch_time_us = clkdata->vdd_switch_time_us; | ||
| 518 | drv_state.power_collapse_khz = clkdata->power_collapse_khz; | ||
| 519 | drv_state.wait_for_irq_khz = clkdata->wait_for_irq_khz; | ||
| 520 | acpuclk_init(); | ||
| 521 | lpj_init(); | ||
| 522 | #ifdef CONFIG_CPU_FREQ_TABLE | ||
| 523 | cpufreq_frequency_table_get_attr(freq_table, smp_processor_id()); | ||
| 524 | #endif | ||
| 525 | } | ||
diff --git a/arch/arm/mach-msm/acpuclock.h b/arch/arm/mach-msm/acpuclock.h deleted file mode 100644 index 415de2eb9a5e..000000000000 --- a/arch/arm/mach-msm/acpuclock.h +++ /dev/null | |||
| @@ -1,32 +0,0 @@ | |||
| 1 | /* arch/arm/mach-msm/acpuclock.h | ||
| 2 | * | ||
| 3 | * MSM architecture clock driver header | ||
| 4 | * | ||
| 5 | * Copyright (C) 2007 Google, Inc. | ||
| 6 | * Copyright (c) 2007 QUALCOMM Incorporated | ||
| 7 | * Author: San Mehat <san@android.com> | ||
| 8 | * | ||
| 9 | * This software is licensed under the terms of the GNU General Public | ||
| 10 | * License version 2, as published by the Free Software Foundation, and | ||
| 11 | * may be copied, distributed, and modified under those terms. | ||
| 12 | * | ||
| 13 | * This program is distributed in the hope that it will be useful, | ||
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 16 | * GNU General Public License for more details. | ||
| 17 | * | ||
| 18 | */ | ||
| 19 | |||
| 20 | #ifndef __ARCH_ARM_MACH_MSM_ACPUCLOCK_H | ||
| 21 | #define __ARCH_ARM_MACH_MSM_ACPUCLOCK_H | ||
| 22 | |||
| 23 | int acpuclk_set_rate(unsigned long rate, int for_power_collapse); | ||
| 24 | unsigned long acpuclk_get_rate(void); | ||
| 25 | uint32_t acpuclk_get_switch_time(void); | ||
| 26 | unsigned long acpuclk_wait_for_irq(void); | ||
| 27 | unsigned long acpuclk_power_collapse(void); | ||
| 28 | unsigned long acpuclk_get_wfi_rate(void); | ||
| 29 | |||
| 30 | |||
| 31 | #endif | ||
| 32 | |||
diff --git a/arch/arm/mach-msm/board-dt-8660.c b/arch/arm/mach-msm/board-dt-8660.c new file mode 100644 index 000000000000..f77f57f39104 --- /dev/null +++ b/arch/arm/mach-msm/board-dt-8660.c | |||
| @@ -0,0 +1,63 @@ | |||
| 1 | /* Copyright (c) 2010-2012, The Linux Foundation. All rights reserved. | ||
| 2 | * | ||
| 3 | * This program is free software; you can redistribute it and/or modify | ||
| 4 | * it under the terms of the GNU General Public License version 2 and | ||
| 5 | * only version 2 as published by the Free Software Foundation. | ||
| 6 | * | ||
| 7 | * This program is distributed in the hope that it will be useful, | ||
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 10 | * GNU General Public License for more details. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #include <linux/init.h> | ||
| 14 | #include <linux/of.h> | ||
| 15 | #include <linux/of_irq.h> | ||
| 16 | #include <linux/of_platform.h> | ||
| 17 | |||
| 18 | #include <asm/mach/arch.h> | ||
| 19 | #include <asm/hardware/gic.h> | ||
| 20 | |||
| 21 | #include <mach/board.h> | ||
| 22 | #include "common.h" | ||
| 23 | |||
| 24 | static const struct of_device_id msm_dt_gic_match[] __initconst = { | ||
| 25 | { .compatible = "qcom,msm-8660-qgic", .data = gic_of_init }, | ||
| 26 | {} | ||
| 27 | }; | ||
| 28 | |||
| 29 | static void __init msm8x60_init_irq(void) | ||
| 30 | { | ||
| 31 | of_irq_init(msm_dt_gic_match); | ||
| 32 | } | ||
| 33 | |||
| 34 | static void __init msm8x60_init_late(void) | ||
| 35 | { | ||
| 36 | smd_debugfs_init(); | ||
| 37 | } | ||
| 38 | |||
| 39 | static struct of_dev_auxdata msm_auxdata_lookup[] __initdata = { | ||
| 40 | {} | ||
| 41 | }; | ||
| 42 | |||
| 43 | static void __init msm8x60_dt_init(void) | ||
| 44 | { | ||
| 45 | of_platform_populate(NULL, of_default_bus_match_table, | ||
| 46 | msm_auxdata_lookup, NULL); | ||
| 47 | } | ||
| 48 | |||
| 49 | static const char *msm8x60_fluid_match[] __initdata = { | ||
| 50 | "qcom,msm8660-fluid", | ||
| 51 | "qcom,msm8660-surf", | ||
| 52 | NULL | ||
| 53 | }; | ||
| 54 | |||
| 55 | DT_MACHINE_START(MSM_DT, "Qualcomm MSM (Flattened Device Tree)") | ||
| 56 | .map_io = msm_map_msm8x60_io, | ||
| 57 | .init_irq = msm8x60_init_irq, | ||
| 58 | .handle_irq = gic_handle_irq, | ||
| 59 | .init_machine = msm8x60_dt_init, | ||
| 60 | .init_late = msm8x60_init_late, | ||
| 61 | .timer = &msm_dt_timer, | ||
| 62 | .dt_compat = msm8x60_fluid_match, | ||
| 63 | MACHINE_END | ||
diff --git a/arch/arm/mach-msm/board-dt-8960.c b/arch/arm/mach-msm/board-dt-8960.c new file mode 100644 index 000000000000..8df99b8f3c92 --- /dev/null +++ b/arch/arm/mach-msm/board-dt-8960.c | |||
| @@ -0,0 +1,49 @@ | |||
| 1 | /* Copyright (c) 2012, The Linux Foundation. All rights reserved. | ||
| 2 | * | ||
| 3 | * This program is free software; you can redistribute it and/or modify | ||
| 4 | * it under the terms of the GNU General Public License version 2 and | ||
| 5 | * only version 2 as published by the Free Software Foundation. | ||
| 6 | * | ||
| 7 | * This program is distributed in the hope that it will be useful, | ||
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 10 | * GNU General Public License for more details. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #include <linux/init.h> | ||
| 14 | #include <linux/of_irq.h> | ||
| 15 | #include <linux/of_platform.h> | ||
| 16 | |||
| 17 | #include <asm/hardware/gic.h> | ||
| 18 | #include <asm/mach/arch.h> | ||
| 19 | |||
| 20 | #include "common.h" | ||
| 21 | |||
| 22 | static const struct of_device_id msm_dt_gic_match[] __initconst = { | ||
| 23 | { .compatible = "qcom,msm-qgic2", .data = gic_of_init }, | ||
| 24 | { } | ||
| 25 | }; | ||
| 26 | |||
| 27 | static void __init msm_dt_init_irq(void) | ||
| 28 | { | ||
| 29 | of_irq_init(msm_dt_gic_match); | ||
| 30 | } | ||
| 31 | |||
| 32 | static void __init msm_dt_init(void) | ||
| 33 | { | ||
| 34 | of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); | ||
| 35 | } | ||
| 36 | |||
| 37 | static const char * const msm8960_dt_match[] __initconst = { | ||
| 38 | "qcom,msm8960-cdp", | ||
| 39 | NULL | ||
| 40 | }; | ||
| 41 | |||
| 42 | DT_MACHINE_START(MSM8960_DT, "Qualcomm MSM (Flattened Device Tree)") | ||
| 43 | .map_io = msm_map_msm8960_io, | ||
| 44 | .init_irq = msm_dt_init_irq, | ||
| 45 | .timer = &msm_dt_timer, | ||
| 46 | .init_machine = msm_dt_init, | ||
| 47 | .dt_compat = msm8960_dt_match, | ||
| 48 | .handle_irq = gic_handle_irq, | ||
| 49 | MACHINE_END | ||
diff --git a/arch/arm/mach-msm/board-halibut.c b/arch/arm/mach-msm/board-halibut.c index 4fa3e99d9a62..6ce542e2e21c 100644 --- a/arch/arm/mach-msm/board-halibut.c +++ b/arch/arm/mach-msm/board-halibut.c | |||
| @@ -36,6 +36,7 @@ | |||
| 36 | #include <linux/mtd/partitions.h> | 36 | #include <linux/mtd/partitions.h> |
| 37 | 37 | ||
| 38 | #include "devices.h" | 38 | #include "devices.h" |
| 39 | #include "common.h" | ||
| 39 | 40 | ||
| 40 | static struct resource smc91x_resources[] = { | 41 | static struct resource smc91x_resources[] = { |
| 41 | [0] = { | 42 | [0] = { |
| @@ -66,8 +67,6 @@ static struct platform_device *devices[] __initdata = { | |||
| 66 | &smc91x_device, | 67 | &smc91x_device, |
| 67 | }; | 68 | }; |
| 68 | 69 | ||
| 69 | extern struct sys_timer msm_timer; | ||
| 70 | |||
| 71 | static void __init halibut_init_early(void) | 70 | static void __init halibut_init_early(void) |
| 72 | { | 71 | { |
| 73 | arch_ioremap_caller = __msm_ioremap_caller; | 72 | arch_ioremap_caller = __msm_ioremap_caller; |
| @@ -107,5 +106,5 @@ MACHINE_START(HALIBUT, "Halibut Board (QCT SURF7200A)") | |||
| 107 | .init_irq = halibut_init_irq, | 106 | .init_irq = halibut_init_irq, |
| 108 | .init_machine = halibut_init, | 107 | .init_machine = halibut_init, |
| 109 | .init_late = halibut_init_late, | 108 | .init_late = halibut_init_late, |
| 110 | .timer = &msm_timer, | 109 | .timer = &msm7x01_timer, |
| 111 | MACHINE_END | 110 | MACHINE_END |
diff --git a/arch/arm/mach-msm/board-mahimahi.c b/arch/arm/mach-msm/board-mahimahi.c index cf1f89a5dc62..df00bc03ce74 100644 --- a/arch/arm/mach-msm/board-mahimahi.c +++ b/arch/arm/mach-msm/board-mahimahi.c | |||
| @@ -30,7 +30,6 @@ | |||
| 30 | 30 | ||
| 31 | #include <mach/board.h> | 31 | #include <mach/board.h> |
| 32 | #include <mach/hardware.h> | 32 | #include <mach/hardware.h> |
| 33 | #include <mach/system.h> | ||
| 34 | 33 | ||
| 35 | #include "board-mahimahi.h" | 34 | #include "board-mahimahi.h" |
| 36 | #include "devices.h" | 35 | #include "devices.h" |
diff --git a/arch/arm/mach-msm/board-msm7x27.c b/arch/arm/mach-msm/board-msm7x27.c deleted file mode 100644 index 451ab1d43c92..000000000000 --- a/arch/arm/mach-msm/board-msm7x27.c +++ /dev/null | |||
| @@ -1,170 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2007 Google, Inc. | ||
| 3 | * Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved. | ||
| 4 | * Author: Brian Swetland <swetland@google.com> | ||
| 5 | * | ||
| 6 | * This software is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2, as published by the Free Software Foundation, and | ||
| 8 | * may be copied, distributed, and modified under those terms. | ||
| 9 | * | ||
| 10 | * This program is distributed in the hope that it will be useful, | ||
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 13 | * GNU General Public License for more details. | ||
| 14 | * | ||
| 15 | */ | ||
| 16 | #include <linux/gpio.h> | ||
| 17 | #include <linux/kernel.h> | ||
| 18 | #include <linux/init.h> | ||
| 19 | #include <linux/platform_device.h> | ||
| 20 | #include <linux/input.h> | ||
| 21 | #include <linux/io.h> | ||
| 22 | #include <linux/delay.h> | ||
| 23 | #include <linux/power_supply.h> | ||
| 24 | |||
| 25 | #include <mach/hardware.h> | ||
| 26 | #include <asm/mach-types.h> | ||
| 27 | #include <asm/mach/arch.h> | ||
| 28 | #include <asm/mach/map.h> | ||
| 29 | #include <asm/mach/flash.h> | ||
| 30 | #include <asm/setup.h> | ||
| 31 | #ifdef CONFIG_CACHE_L2X0 | ||
| 32 | #include <asm/hardware/cache-l2x0.h> | ||
| 33 | #endif | ||
| 34 | |||
| 35 | #include <mach/vreg.h> | ||
| 36 | #include <mach/mpp.h> | ||
| 37 | #include <mach/board.h> | ||
| 38 | #include <mach/msm_iomap.h> | ||
| 39 | |||
| 40 | #include <linux/mtd/nand.h> | ||
| 41 | #include <linux/mtd/partitions.h> | ||
| 42 | |||
| 43 | #include "devices.h" | ||
| 44 | #include "socinfo.h" | ||
| 45 | #include "clock.h" | ||
| 46 | |||
| 47 | static struct resource smc91x_resources[] = { | ||
| 48 | [0] = { | ||
| 49 | .start = 0x9C004300, | ||
| 50 | .end = 0x9C0043ff, | ||
| 51 | .flags = IORESOURCE_MEM, | ||
| 52 | }, | ||
| 53 | [1] = { | ||
| 54 | .start = MSM_GPIO_TO_INT(132), | ||
| 55 | .end = MSM_GPIO_TO_INT(132), | ||
| 56 | .flags = IORESOURCE_IRQ, | ||
| 57 | }, | ||
| 58 | }; | ||
| 59 | |||
| 60 | static struct platform_device smc91x_device = { | ||
| 61 | .name = "smc91x", | ||
| 62 | .id = 0, | ||
| 63 | .num_resources = ARRAY_SIZE(smc91x_resources), | ||
| 64 | .resource = smc91x_resources, | ||
| 65 | }; | ||
| 66 | |||
| 67 | static struct platform_device *devices[] __initdata = { | ||
| 68 | &msm_device_uart3, | ||
| 69 | &msm_device_smd, | ||
| 70 | &msm_device_dmov, | ||
| 71 | &msm_device_nand, | ||
| 72 | &smc91x_device, | ||
| 73 | }; | ||
| 74 | |||
| 75 | extern struct sys_timer msm_timer; | ||
| 76 | |||
| 77 | static void __init msm7x2x_init_irq(void) | ||
| 78 | { | ||
| 79 | msm_init_irq(); | ||
| 80 | } | ||
| 81 | |||
| 82 | static void __init msm7x2x_init(void) | ||
| 83 | { | ||
| 84 | if (socinfo_init() < 0) | ||
| 85 | BUG(); | ||
| 86 | |||
| 87 | if (machine_is_msm7x25_ffa() || machine_is_msm7x27_ffa()) { | ||
| 88 | smc91x_resources[0].start = 0x98000300; | ||
| 89 | smc91x_resources[0].end = 0x980003ff; | ||
| 90 | smc91x_resources[1].start = MSM_GPIO_TO_INT(85); | ||
| 91 | smc91x_resources[1].end = MSM_GPIO_TO_INT(85); | ||
| 92 | if (gpio_tlmm_config(GPIO_CFG(85, 0, | ||
| 93 | GPIO_INPUT, | ||
| 94 | GPIO_PULL_DOWN, | ||
| 95 | GPIO_2MA), | ||
| 96 | GPIO_ENABLE)) { | ||
| 97 | printk(KERN_ERR | ||
| 98 | "%s: Err: Config GPIO-85 INT\n", | ||
| 99 | __func__); | ||
| 100 | } | ||
| 101 | } | ||
| 102 | |||
| 103 | platform_add_devices(devices, ARRAY_SIZE(devices)); | ||
| 104 | } | ||
| 105 | |||
| 106 | static void __init msm7x2x_map_io(void) | ||
| 107 | { | ||
| 108 | msm_map_common_io(); | ||
| 109 | /* Technically dependent on the SoC but using machine_is | ||
| 110 | * macros since socinfo is not available this early and there | ||
| 111 | * are plans to restructure the code which will eliminate the | ||
| 112 | * need for socinfo. | ||
| 113 | */ | ||
| 114 | if (machine_is_msm7x27_surf() || machine_is_msm7x27_ffa()) | ||
| 115 | msm_clock_init(msm_clocks_7x27, msm_num_clocks_7x27); | ||
| 116 | |||
| 117 | if (machine_is_msm7x25_surf() || machine_is_msm7x25_ffa()) | ||
| 118 | msm_clock_init(msm_clocks_7x25, msm_num_clocks_7x25); | ||
| 119 | |||
| 120 | #ifdef CONFIG_CACHE_L2X0 | ||
| 121 | if (machine_is_msm7x27_surf() || machine_is_msm7x27_ffa()) { | ||
| 122 | /* 7x27 has 256KB L2 cache: | ||
| 123 | 64Kb/Way and 4-Way Associativity; | ||
| 124 | R/W latency: 3 cycles; | ||
| 125 | evmon/parity/share disabled. */ | ||
| 126 | l2x0_init(MSM_L2CC_BASE, 0x00068012, 0xfe000000); | ||
| 127 | } | ||
| 128 | #endif | ||
| 129 | } | ||
| 130 | |||
| 131 | static void __init msm7x2x_init_late(void) | ||
| 132 | { | ||
| 133 | smd_debugfs_init(); | ||
| 134 | } | ||
| 135 | |||
| 136 | MACHINE_START(MSM7X27_SURF, "QCT MSM7x27 SURF") | ||
| 137 | .atag_offset = 0x100, | ||
| 138 | .map_io = msm7x2x_map_io, | ||
| 139 | .init_irq = msm7x2x_init_irq, | ||
| 140 | .init_machine = msm7x2x_init, | ||
| 141 | .init_late = msm7x2x_init_late, | ||
| 142 | .timer = &msm_timer, | ||
| 143 | MACHINE_END | ||
| 144 | |||
| 145 | MACHINE_START(MSM7X27_FFA, "QCT MSM7x27 FFA") | ||
| 146 | .atag_offset = 0x100, | ||
| 147 | .map_io = msm7x2x_map_io, | ||
| 148 | .init_irq = msm7x2x_init_irq, | ||
| 149 | .init_machine = msm7x2x_init, | ||
| 150 | .init_late = msm7x2x_init_late, | ||
| 151 | .timer = &msm_timer, | ||
| 152 | MACHINE_END | ||
| 153 | |||
| 154 | MACHINE_START(MSM7X25_SURF, "QCT MSM7x25 SURF") | ||
| 155 | .atag_offset = 0x100, | ||
| 156 | .map_io = msm7x2x_map_io, | ||
| 157 | .init_irq = msm7x2x_init_irq, | ||
| 158 | .init_machine = msm7x2x_init, | ||
| 159 | .init_late = msm7x2x_init_late, | ||
| 160 | .timer = &msm_timer, | ||
| 161 | MACHINE_END | ||
| 162 | |||
| 163 | MACHINE_START(MSM7X25_FFA, "QCT MSM7x25 FFA") | ||
| 164 | .atag_offset = 0x100, | ||
| 165 | .map_io = msm7x2x_map_io, | ||
| 166 | .init_irq = msm7x2x_init_irq, | ||
| 167 | .init_machine = msm7x2x_init, | ||
| 168 | .init_late = msm7x2x_init_late, | ||
| 169 | .timer = &msm_timer, | ||
| 170 | MACHINE_END | ||
diff --git a/arch/arm/mach-msm/board-msm7x30.c b/arch/arm/mach-msm/board-msm7x30.c index a5001378135d..effa6f4336c7 100644 --- a/arch/arm/mach-msm/board-msm7x30.c +++ b/arch/arm/mach-msm/board-msm7x30.c | |||
| @@ -38,8 +38,7 @@ | |||
| 38 | #include "devices.h" | 38 | #include "devices.h" |
| 39 | #include "gpiomux.h" | 39 | #include "gpiomux.h" |
| 40 | #include "proc_comm.h" | 40 | #include "proc_comm.h" |
| 41 | 41 | #include "common.h" | |
| 42 | extern struct sys_timer msm_timer; | ||
| 43 | 42 | ||
| 44 | static void __init msm7x30_fixup(struct tag *tag, char **cmdline, | 43 | static void __init msm7x30_fixup(struct tag *tag, char **cmdline, |
| 45 | struct meminfo *mi) | 44 | struct meminfo *mi) |
| @@ -132,7 +131,7 @@ MACHINE_START(MSM7X30_SURF, "QCT MSM7X30 SURF") | |||
| 132 | .init_irq = msm7x30_init_irq, | 131 | .init_irq = msm7x30_init_irq, |
| 133 | .init_machine = msm7x30_init, | 132 | .init_machine = msm7x30_init, |
| 134 | .init_late = msm7x30_init_late, | 133 | .init_late = msm7x30_init_late, |
| 135 | .timer = &msm_timer, | 134 | .timer = &msm7x30_timer, |
| 136 | MACHINE_END | 135 | MACHINE_END |
| 137 | 136 | ||
| 138 | MACHINE_START(MSM7X30_FFA, "QCT MSM7X30 FFA") | 137 | MACHINE_START(MSM7X30_FFA, "QCT MSM7X30 FFA") |
| @@ -143,7 +142,7 @@ MACHINE_START(MSM7X30_FFA, "QCT MSM7X30 FFA") | |||
| 143 | .init_irq = msm7x30_init_irq, | 142 | .init_irq = msm7x30_init_irq, |
| 144 | .init_machine = msm7x30_init, | 143 | .init_machine = msm7x30_init, |
| 145 | .init_late = msm7x30_init_late, | 144 | .init_late = msm7x30_init_late, |
| 146 | .timer = &msm_timer, | 145 | .timer = &msm7x30_timer, |
| 147 | MACHINE_END | 146 | MACHINE_END |
| 148 | 147 | ||
| 149 | MACHINE_START(MSM7X30_FLUID, "QCT MSM7X30 FLUID") | 148 | MACHINE_START(MSM7X30_FLUID, "QCT MSM7X30 FLUID") |
| @@ -154,5 +153,5 @@ MACHINE_START(MSM7X30_FLUID, "QCT MSM7X30 FLUID") | |||
| 154 | .init_irq = msm7x30_init_irq, | 153 | .init_irq = msm7x30_init_irq, |
| 155 | .init_machine = msm7x30_init, | 154 | .init_machine = msm7x30_init, |
| 156 | .init_late = msm7x30_init_late, | 155 | .init_late = msm7x30_init_late, |
| 157 | .timer = &msm_timer, | 156 | .timer = &msm7x30_timer, |
| 158 | MACHINE_END | 157 | MACHINE_END |
diff --git a/arch/arm/mach-msm/board-msm8960.c b/arch/arm/mach-msm/board-msm8960.c deleted file mode 100644 index 65f4a1daa2e5..000000000000 --- a/arch/arm/mach-msm/board-msm8960.c +++ /dev/null | |||
| @@ -1,122 +0,0 @@ | |||
| 1 | /* Copyright (c) 2011, Code Aurora Forum. All rights reserved. | ||
| 2 | * | ||
| 3 | * This program is free software; you can redistribute it and/or modify | ||
| 4 | * it under the terms of the GNU General Public License version 2 and | ||
| 5 | * only version 2 as published by the Free Software Foundation. | ||
| 6 | * | ||
| 7 | * This program is distributed in the hope that it will be useful, | ||
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 10 | * GNU General Public License for more details. | ||
| 11 | * | ||
| 12 | * You should have received a copy of the GNU General Public License | ||
| 13 | * along with this program; if not, write to the Free Software | ||
| 14 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA | ||
| 15 | * 02110-1301, USA. | ||
| 16 | * | ||
| 17 | */ | ||
| 18 | #include <linux/kernel.h> | ||
| 19 | #include <linux/platform_device.h> | ||
| 20 | #include <linux/io.h> | ||
| 21 | #include <linux/irq.h> | ||
| 22 | #include <linux/clkdev.h> | ||
| 23 | #include <linux/memblock.h> | ||
| 24 | |||
| 25 | #include <asm/mach-types.h> | ||
| 26 | #include <asm/mach/arch.h> | ||
| 27 | #include <asm/hardware/gic.h> | ||
| 28 | #include <asm/setup.h> | ||
| 29 | |||
| 30 | #include <mach/board.h> | ||
| 31 | #include <mach/msm_iomap.h> | ||
| 32 | |||
| 33 | #include "devices.h" | ||
| 34 | |||
| 35 | static void __init msm8960_fixup(struct tag *tag, char **cmdline, | ||
| 36 | struct meminfo *mi) | ||
| 37 | { | ||
| 38 | for (; tag->hdr.size; tag = tag_next(tag)) | ||
| 39 | if (tag->hdr.tag == ATAG_MEM && | ||
| 40 | tag->u.mem.start == 0x40200000) { | ||
| 41 | tag->u.mem.start = 0x40000000; | ||
| 42 | tag->u.mem.size += SZ_2M; | ||
| 43 | } | ||
| 44 | } | ||
| 45 | |||
| 46 | static void __init msm8960_reserve(void) | ||
| 47 | { | ||
| 48 | memblock_remove(0x40000000, SZ_2M); | ||
| 49 | } | ||
| 50 | |||
| 51 | static void __init msm8960_map_io(void) | ||
| 52 | { | ||
| 53 | msm_map_msm8960_io(); | ||
| 54 | } | ||
| 55 | |||
| 56 | static void __init msm8960_init_irq(void) | ||
| 57 | { | ||
| 58 | unsigned int i; | ||
| 59 | gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE, | ||
| 60 | (void *)MSM_QGIC_CPU_BASE); | ||
| 61 | |||
| 62 | /* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */ | ||
| 63 | writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4); | ||
| 64 | |||
| 65 | if (machine_is_msm8960_rumi3()) | ||
| 66 | writel(0x0000FFFF, MSM_QGIC_DIST_BASE + GIC_DIST_ENABLE_SET); | ||
| 67 | |||
| 68 | /* FIXME: Not installing AVS_SVICINT and AVS_SVICINTSWDONE yet | ||
| 69 | * as they are configured as level, which does not play nice with | ||
| 70 | * handle_percpu_irq. | ||
| 71 | */ | ||
| 72 | for (i = GIC_PPI_START; i < GIC_SPI_START; i++) { | ||
| 73 | if (i != AVS_SVICINT && i != AVS_SVICINTSWDONE) | ||
| 74 | irq_set_handler(i, handle_percpu_irq); | ||
| 75 | } | ||
| 76 | } | ||
| 77 | |||
| 78 | static struct platform_device *sim_devices[] __initdata = { | ||
| 79 | &msm8960_device_uart_gsbi2, | ||
| 80 | }; | ||
| 81 | |||
| 82 | static struct platform_device *rumi3_devices[] __initdata = { | ||
| 83 | &msm8960_device_uart_gsbi5, | ||
| 84 | }; | ||
| 85 | |||
| 86 | static void __init msm8960_sim_init(void) | ||
| 87 | { | ||
| 88 | platform_add_devices(sim_devices, ARRAY_SIZE(sim_devices)); | ||
| 89 | } | ||
| 90 | |||
| 91 | static void __init msm8960_rumi3_init(void) | ||
| 92 | { | ||
| 93 | platform_add_devices(rumi3_devices, ARRAY_SIZE(rumi3_devices)); | ||
| 94 | } | ||
| 95 | |||
| 96 | static void __init msm8960_init_late(void) | ||
| 97 | { | ||
| 98 | smd_debugfs_init(); | ||
| 99 | } | ||
| 100 | |||
| 101 | MACHINE_START(MSM8960_SIM, "QCT MSM8960 SIMULATOR") | ||
| 102 | .fixup = msm8960_fixup, | ||
| 103 | .reserve = msm8960_reserve, | ||
| 104 | .map_io = msm8960_map_io, | ||
| 105 | .init_irq = msm8960_init_irq, | ||
| 106 | .timer = &msm_timer, | ||
| 107 | .handle_irq = gic_handle_irq, | ||
| 108 | .init_machine = msm8960_sim_init, | ||
| 109 | .init_late = msm8960_init_late, | ||
| 110 | MACHINE_END | ||
| 111 | |||
| 112 | MACHINE_START(MSM8960_RUMI3, "QCT MSM8960 RUMI3") | ||
| 113 | .fixup = msm8960_fixup, | ||
| 114 | .reserve = msm8960_reserve, | ||
| 115 | .map_io = msm8960_map_io, | ||
| 116 | .init_irq = msm8960_init_irq, | ||
| 117 | .timer = &msm_timer, | ||
| 118 | .handle_irq = gic_handle_irq, | ||
| 119 | .init_machine = msm8960_rumi3_init, | ||
| 120 | .init_late = msm8960_init_late, | ||
| 121 | MACHINE_END | ||
| 122 | |||
diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c deleted file mode 100644 index e37a724cd1eb..000000000000 --- a/arch/arm/mach-msm/board-msm8x60.c +++ /dev/null | |||
| @@ -1,166 +0,0 @@ | |||
| 1 | /* Copyright (c) 2010, 2011, Code Aurora Forum. All rights reserved. | ||
| 2 | * | ||
| 3 | * This program is free software; you can redistribute it and/or modify | ||
| 4 | * it under the terms of the GNU General Public License version 2 and | ||
| 5 | * only version 2 as published by the Free Software Foundation. | ||
| 6 | * | ||
| 7 | * This program is distributed in the hope that it will be useful, | ||
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 10 | * GNU General Public License for more details. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #include <linux/kernel.h> | ||
| 14 | #include <linux/platform_device.h> | ||
| 15 | #include <linux/io.h> | ||
| 16 | #include <linux/irq.h> | ||
| 17 | #include <linux/irqdomain.h> | ||
| 18 | #include <linux/of.h> | ||
| 19 | #include <linux/of_address.h> | ||
| 20 | #include <linux/of_irq.h> | ||
| 21 | #include <linux/of_platform.h> | ||
| 22 | #include <linux/memblock.h> | ||
| 23 | |||
| 24 | #include <asm/mach-types.h> | ||
| 25 | #include <asm/mach/arch.h> | ||
| 26 | #include <asm/hardware/gic.h> | ||
| 27 | #include <asm/setup.h> | ||
| 28 | |||
| 29 | #include <mach/board.h> | ||
| 30 | #include <mach/msm_iomap.h> | ||
| 31 | |||
| 32 | static void __init msm8x60_fixup(struct tag *tag, char **cmdline, | ||
| 33 | struct meminfo *mi) | ||
| 34 | { | ||
| 35 | for (; tag->hdr.size; tag = tag_next(tag)) | ||
| 36 | if (tag->hdr.tag == ATAG_MEM && | ||
| 37 | tag->u.mem.start == 0x40200000) { | ||
| 38 | tag->u.mem.start = 0x40000000; | ||
| 39 | tag->u.mem.size += SZ_2M; | ||
| 40 | } | ||
| 41 | } | ||
| 42 | |||
| 43 | static void __init msm8x60_reserve(void) | ||
| 44 | { | ||
| 45 | memblock_remove(0x40000000, SZ_2M); | ||
| 46 | } | ||
| 47 | |||
| 48 | static void __init msm8x60_map_io(void) | ||
| 49 | { | ||
| 50 | msm_map_msm8x60_io(); | ||
| 51 | } | ||
| 52 | |||
| 53 | #ifdef CONFIG_OF | ||
| 54 | static struct of_device_id msm_dt_gic_match[] __initdata = { | ||
| 55 | { .compatible = "qcom,msm-8660-qgic", .data = gic_of_init }, | ||
| 56 | {} | ||
| 57 | }; | ||
| 58 | #endif | ||
| 59 | |||
| 60 | static void __init msm8x60_init_irq(void) | ||
| 61 | { | ||
| 62 | if (!of_have_populated_dt()) | ||
| 63 | gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE, | ||
| 64 | (void *)MSM_QGIC_CPU_BASE); | ||
| 65 | #ifdef CONFIG_OF | ||
| 66 | else | ||
| 67 | of_irq_init(msm_dt_gic_match); | ||
| 68 | #endif | ||
| 69 | |||
| 70 | /* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */ | ||
| 71 | writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4); | ||
| 72 | |||
| 73 | /* RUMI does not adhere to GIC spec by enabling STIs by default. | ||
| 74 | * Enable/clear is supposed to be RO for STIs, but is RW on RUMI. | ||
| 75 | */ | ||
| 76 | if (!machine_is_msm8x60_sim()) | ||
| 77 | writel(0x0000FFFF, MSM_QGIC_DIST_BASE + GIC_DIST_ENABLE_SET); | ||
| 78 | } | ||
| 79 | |||
| 80 | static void __init msm8x60_init(void) | ||
| 81 | { | ||
| 82 | } | ||
| 83 | |||
| 84 | static void __init msm8x60_init_late(void) | ||
| 85 | { | ||
| 86 | smd_debugfs_init(); | ||
| 87 | } | ||
| 88 | |||
| 89 | #ifdef CONFIG_OF | ||
| 90 | static struct of_dev_auxdata msm_auxdata_lookup[] __initdata = { | ||
| 91 | {} | ||
| 92 | }; | ||
| 93 | |||
| 94 | static void __init msm8x60_dt_init(void) | ||
| 95 | { | ||
| 96 | if (of_machine_is_compatible("qcom,msm8660-surf")) { | ||
| 97 | printk(KERN_INFO "Init surf UART registers\n"); | ||
| 98 | msm8x60_init_uart12dm(); | ||
| 99 | } | ||
| 100 | |||
| 101 | of_platform_populate(NULL, of_default_bus_match_table, | ||
| 102 | msm_auxdata_lookup, NULL); | ||
| 103 | } | ||
| 104 | |||
| 105 | static const char *msm8x60_fluid_match[] __initdata = { | ||
| 106 | "qcom,msm8660-fluid", | ||
| 107 | "qcom,msm8660-surf", | ||
| 108 | NULL | ||
| 109 | }; | ||
| 110 | #endif /* CONFIG_OF */ | ||
| 111 | |||
| 112 | MACHINE_START(MSM8X60_RUMI3, "QCT MSM8X60 RUMI3") | ||
| 113 | .fixup = msm8x60_fixup, | ||
| 114 | .reserve = msm8x60_reserve, | ||
| 115 | .map_io = msm8x60_map_io, | ||
| 116 | .init_irq = msm8x60_init_irq, | ||
| 117 | .handle_irq = gic_handle_irq, | ||
| 118 | .init_machine = msm8x60_init, | ||
| 119 | .init_late = msm8x60_init_late, | ||
| 120 | .timer = &msm_timer, | ||
| 121 | MACHINE_END | ||
| 122 | |||
| 123 | MACHINE_START(MSM8X60_SURF, "QCT MSM8X60 SURF") | ||
| 124 | .fixup = msm8x60_fixup, | ||
| 125 | .reserve = msm8x60_reserve, | ||
| 126 | .map_io = msm8x60_map_io, | ||
| 127 | .init_irq = msm8x60_init_irq, | ||
| 128 | .handle_irq = gic_handle_irq, | ||
| 129 | .init_machine = msm8x60_init, | ||
| 130 | .init_late = msm8x60_init_late, | ||
| 131 | .timer = &msm_timer, | ||
| 132 | MACHINE_END | ||
| 133 | |||
| 134 | MACHINE_START(MSM8X60_SIM, "QCT MSM8X60 SIMULATOR") | ||
| 135 | .fixup = msm8x60_fixup, | ||
| 136 | .reserve = msm8x60_reserve, | ||
| 137 | .map_io = msm8x60_map_io, | ||
| 138 | .init_irq = msm8x60_init_irq, | ||
| 139 | .handle_irq = gic_handle_irq, | ||
| 140 | .init_machine = msm8x60_init, | ||
| 141 | .init_late = msm8x60_init_late, | ||
| 142 | .timer = &msm_timer, | ||
| 143 | MACHINE_END | ||
| 144 | |||
| 145 | MACHINE_START(MSM8X60_FFA, "QCT MSM8X60 FFA") | ||
| 146 | .fixup = msm8x60_fixup, | ||
| 147 | .reserve = msm8x60_reserve, | ||
| 148 | .map_io = msm8x60_map_io, | ||
| 149 | .init_irq = msm8x60_init_irq, | ||
| 150 | .handle_irq = gic_handle_irq, | ||
| 151 | .init_machine = msm8x60_init, | ||
| 152 | .init_late = msm8x60_init_late, | ||
| 153 | .timer = &msm_timer, | ||
| 154 | MACHINE_END | ||
| 155 | |||
| 156 | #ifdef CONFIG_OF | ||
| 157 | /* TODO: General device tree support for all MSM. */ | ||
| 158 | DT_MACHINE_START(MSM_DT, "Qualcomm MSM (Flattened Device Tree)") | ||
| 159 | .map_io = msm8x60_map_io, | ||
| 160 | .init_irq = msm8x60_init_irq, | ||
| 161 | .init_machine = msm8x60_dt_init, | ||
| 162 | .init_late = msm8x60_init_late, | ||
| 163 | .timer = &msm_timer, | ||
| 164 | .dt_compat = msm8x60_fluid_match, | ||
| 165 | MACHINE_END | ||
| 166 | #endif /* CONFIG_OF */ | ||
diff --git a/arch/arm/mach-msm/board-qsd8x50.c b/arch/arm/mach-msm/board-qsd8x50.c index c8fe0edb9761..b16b71abf5f6 100644 --- a/arch/arm/mach-msm/board-qsd8x50.c +++ b/arch/arm/mach-msm/board-qsd8x50.c | |||
| @@ -35,8 +35,7 @@ | |||
| 35 | #include <mach/mmc.h> | 35 | #include <mach/mmc.h> |
| 36 | 36 | ||
| 37 | #include "devices.h" | 37 | #include "devices.h" |
| 38 | 38 | #include "common.h" | |
| 39 | extern struct sys_timer msm_timer; | ||
| 40 | 39 | ||
| 41 | static const resource_size_t qsd8x50_surf_smc91x_base __initdata = 0x70000300; | 40 | static const resource_size_t qsd8x50_surf_smc91x_base __initdata = 0x70000300; |
| 42 | static const unsigned qsd8x50_surf_smc91x_gpio __initdata = 156; | 41 | static const unsigned qsd8x50_surf_smc91x_gpio __initdata = 156; |
| @@ -201,7 +200,7 @@ MACHINE_START(QSD8X50_SURF, "QCT QSD8X50 SURF") | |||
| 201 | .init_irq = qsd8x50_init_irq, | 200 | .init_irq = qsd8x50_init_irq, |
| 202 | .init_machine = qsd8x50_init, | 201 | .init_machine = qsd8x50_init, |
| 203 | .init_late = qsd8x50_init_late, | 202 | .init_late = qsd8x50_init_late, |
| 204 | .timer = &msm_timer, | 203 | .timer = &qsd8x50_timer, |
| 205 | MACHINE_END | 204 | MACHINE_END |
| 206 | 205 | ||
| 207 | MACHINE_START(QSD8X50A_ST1_5, "QCT QSD8X50A ST1.5") | 206 | MACHINE_START(QSD8X50A_ST1_5, "QCT QSD8X50A ST1.5") |
| @@ -210,5 +209,5 @@ MACHINE_START(QSD8X50A_ST1_5, "QCT QSD8X50A ST1.5") | |||
| 210 | .init_irq = qsd8x50_init_irq, | 209 | .init_irq = qsd8x50_init_irq, |
| 211 | .init_machine = qsd8x50_init, | 210 | .init_machine = qsd8x50_init, |
| 212 | .init_late = qsd8x50_init_late, | 211 | .init_late = qsd8x50_init_late, |
| 213 | .timer = &msm_timer, | 212 | .timer = &qsd8x50_timer, |
| 214 | MACHINE_END | 213 | MACHINE_END |
diff --git a/arch/arm/mach-msm/board-sapphire.c b/arch/arm/mach-msm/board-sapphire.c index 2e569ab10eef..b7b0fc7e3278 100644 --- a/arch/arm/mach-msm/board-sapphire.c +++ b/arch/arm/mach-msm/board-sapphire.c | |||
| @@ -27,7 +27,6 @@ | |||
| 27 | #include <asm/mach/arch.h> | 27 | #include <asm/mach/arch.h> |
| 28 | #include <asm/mach/map.h> | 28 | #include <asm/mach/map.h> |
| 29 | #include <asm/mach/flash.h> | 29 | #include <asm/mach/flash.h> |
| 30 | #include <mach/system.h> | ||
| 31 | #include <mach/vreg.h> | 30 | #include <mach/vreg.h> |
| 32 | #include <mach/board.h> | 31 | #include <mach/board.h> |
| 33 | 32 | ||
diff --git a/arch/arm/mach-msm/board-trout.c b/arch/arm/mach-msm/board-trout.c index bbe13f12fa01..4ba0800e243e 100644 --- a/arch/arm/mach-msm/board-trout.c +++ b/arch/arm/mach-msm/board-trout.c | |||
| @@ -31,6 +31,7 @@ | |||
| 31 | 31 | ||
| 32 | #include "devices.h" | 32 | #include "devices.h" |
| 33 | #include "board-trout.h" | 33 | #include "board-trout.h" |
| 34 | #include "common.h" | ||
| 34 | 35 | ||
| 35 | extern int trout_init_mmc(unsigned int); | 36 | extern int trout_init_mmc(unsigned int); |
| 36 | 37 | ||
| @@ -42,8 +43,6 @@ static struct platform_device *devices[] __initdata = { | |||
| 42 | &msm_device_i2c, | 43 | &msm_device_i2c, |
| 43 | }; | 44 | }; |
| 44 | 45 | ||
| 45 | extern struct sys_timer msm_timer; | ||
| 46 | |||
| 47 | static void __init trout_init_early(void) | 46 | static void __init trout_init_early(void) |
| 48 | { | 47 | { |
| 49 | arch_ioremap_caller = __msm_ioremap_caller; | 48 | arch_ioremap_caller = __msm_ioremap_caller; |
| @@ -111,5 +110,5 @@ MACHINE_START(TROUT, "HTC Dream") | |||
| 111 | .init_irq = trout_init_irq, | 110 | .init_irq = trout_init_irq, |
| 112 | .init_machine = trout_init, | 111 | .init_machine = trout_init, |
| 113 | .init_late = trout_init_late, | 112 | .init_late = trout_init_late, |
| 114 | .timer = &msm_timer, | 113 | .timer = &msm7x01_timer, |
| 115 | MACHINE_END | 114 | MACHINE_END |
diff --git a/arch/arm/mach-msm/clock-pcom.c b/arch/arm/mach-msm/clock-pcom.c index 63b711311086..a52c970df157 100644 --- a/arch/arm/mach-msm/clock-pcom.c +++ b/arch/arm/mach-msm/clock-pcom.c | |||
| @@ -25,7 +25,7 @@ | |||
| 25 | /* | 25 | /* |
| 26 | * glue for the proc_comm interface | 26 | * glue for the proc_comm interface |
| 27 | */ | 27 | */ |
| 28 | int pc_clk_enable(unsigned id) | 28 | static int pc_clk_enable(unsigned id) |
| 29 | { | 29 | { |
| 30 | int rc = msm_proc_comm(PCOM_CLKCTL_RPC_ENABLE, &id, NULL); | 30 | int rc = msm_proc_comm(PCOM_CLKCTL_RPC_ENABLE, &id, NULL); |
| 31 | if (rc < 0) | 31 | if (rc < 0) |
| @@ -34,7 +34,7 @@ int pc_clk_enable(unsigned id) | |||
| 34 | return (int)id < 0 ? -EINVAL : 0; | 34 | return (int)id < 0 ? -EINVAL : 0; |
| 35 | } | 35 | } |
| 36 | 36 | ||
| 37 | void pc_clk_disable(unsigned id) | 37 | static void pc_clk_disable(unsigned id) |
| 38 | { | 38 | { |
| 39 | msm_proc_comm(PCOM_CLKCTL_RPC_DISABLE, &id, NULL); | 39 | msm_proc_comm(PCOM_CLKCTL_RPC_DISABLE, &id, NULL); |
| 40 | } | 40 | } |
| @@ -54,7 +54,7 @@ int pc_clk_reset(unsigned id, enum clk_reset_action action) | |||
| 54 | return (int)id < 0 ? -EINVAL : 0; | 54 | return (int)id < 0 ? -EINVAL : 0; |
| 55 | } | 55 | } |
| 56 | 56 | ||
| 57 | int pc_clk_set_rate(unsigned id, unsigned rate) | 57 | static int pc_clk_set_rate(unsigned id, unsigned rate) |
| 58 | { | 58 | { |
| 59 | /* The rate _might_ be rounded off to the nearest KHz value by the | 59 | /* The rate _might_ be rounded off to the nearest KHz value by the |
| 60 | * remote function. So a return value of 0 doesn't necessarily mean | 60 | * remote function. So a return value of 0 doesn't necessarily mean |
| @@ -67,7 +67,7 @@ int pc_clk_set_rate(unsigned id, unsigned rate) | |||
| 67 | return (int)id < 0 ? -EINVAL : 0; | 67 | return (int)id < 0 ? -EINVAL : 0; |
| 68 | } | 68 | } |
| 69 | 69 | ||
| 70 | int pc_clk_set_min_rate(unsigned id, unsigned rate) | 70 | static int pc_clk_set_min_rate(unsigned id, unsigned rate) |
| 71 | { | 71 | { |
| 72 | int rc = msm_proc_comm(PCOM_CLKCTL_RPC_MIN_RATE, &id, &rate); | 72 | int rc = msm_proc_comm(PCOM_CLKCTL_RPC_MIN_RATE, &id, &rate); |
| 73 | if (rc < 0) | 73 | if (rc < 0) |
| @@ -76,7 +76,7 @@ int pc_clk_set_min_rate(unsigned id, unsigned rate) | |||
| 76 | return (int)id < 0 ? -EINVAL : 0; | 76 | return (int)id < 0 ? -EINVAL : 0; |
| 77 | } | 77 | } |
| 78 | 78 | ||
| 79 | int pc_clk_set_max_rate(unsigned id, unsigned rate) | 79 | static int pc_clk_set_max_rate(unsigned id, unsigned rate) |
| 80 | { | 80 | { |
| 81 | int rc = msm_proc_comm(PCOM_CLKCTL_RPC_MAX_RATE, &id, &rate); | 81 | int rc = msm_proc_comm(PCOM_CLKCTL_RPC_MAX_RATE, &id, &rate); |
| 82 | if (rc < 0) | 82 | if (rc < 0) |
| @@ -85,7 +85,7 @@ int pc_clk_set_max_rate(unsigned id, unsigned rate) | |||
| 85 | return (int)id < 0 ? -EINVAL : 0; | 85 | return (int)id < 0 ? -EINVAL : 0; |
| 86 | } | 86 | } |
| 87 | 87 | ||
| 88 | int pc_clk_set_flags(unsigned id, unsigned flags) | 88 | static int pc_clk_set_flags(unsigned id, unsigned flags) |
| 89 | { | 89 | { |
| 90 | int rc = msm_proc_comm(PCOM_CLKCTL_RPC_SET_FLAGS, &id, &flags); | 90 | int rc = msm_proc_comm(PCOM_CLKCTL_RPC_SET_FLAGS, &id, &flags); |
| 91 | if (rc < 0) | 91 | if (rc < 0) |
| @@ -94,7 +94,7 @@ int pc_clk_set_flags(unsigned id, unsigned flags) | |||
| 94 | return (int)id < 0 ? -EINVAL : 0; | 94 | return (int)id < 0 ? -EINVAL : 0; |
| 95 | } | 95 | } |
| 96 | 96 | ||
| 97 | unsigned pc_clk_get_rate(unsigned id) | 97 | static unsigned pc_clk_get_rate(unsigned id) |
| 98 | { | 98 | { |
| 99 | if (msm_proc_comm(PCOM_CLKCTL_RPC_RATE, &id, NULL)) | 99 | if (msm_proc_comm(PCOM_CLKCTL_RPC_RATE, &id, NULL)) |
| 100 | return 0; | 100 | return 0; |
| @@ -102,7 +102,7 @@ unsigned pc_clk_get_rate(unsigned id) | |||
| 102 | return id; | 102 | return id; |
| 103 | } | 103 | } |
| 104 | 104 | ||
| 105 | unsigned pc_clk_is_enabled(unsigned id) | 105 | static unsigned pc_clk_is_enabled(unsigned id) |
| 106 | { | 106 | { |
| 107 | if (msm_proc_comm(PCOM_CLKCTL_RPC_ENABLED, &id, NULL)) | 107 | if (msm_proc_comm(PCOM_CLKCTL_RPC_ENABLED, &id, NULL)) |
| 108 | return 0; | 108 | return 0; |
| @@ -110,7 +110,7 @@ unsigned pc_clk_is_enabled(unsigned id) | |||
| 110 | return id; | 110 | return id; |
| 111 | } | 111 | } |
| 112 | 112 | ||
| 113 | long pc_clk_round_rate(unsigned id, unsigned rate) | 113 | static long pc_clk_round_rate(unsigned id, unsigned rate) |
| 114 | { | 114 | { |
| 115 | 115 | ||
| 116 | /* Not really supported; pc_clk_set_rate() does rounding on it's own. */ | 116 | /* Not really supported; pc_clk_set_rate() does rounding on it's own. */ |
diff --git a/arch/arm/mach-msm/common.h b/arch/arm/mach-msm/common.h new file mode 100644 index 000000000000..d68e5d7854f5 --- /dev/null +++ b/arch/arm/mach-msm/common.h | |||
| @@ -0,0 +1,30 @@ | |||
| 1 | /* Copyright (c) 2012, The Linux Foundation. All rights reserved. | ||
| 2 | * | ||
| 3 | * This program is free software; you can redistribute it and/or modify | ||
| 4 | * it under the terms of the GNU General Public License version 2 and | ||
| 5 | * only version 2 as published by the Free Software Foundation. | ||
| 6 | * | ||
| 7 | * This program is distributed in the hope that it will be useful, | ||
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 10 | * GNU General Public License for more details. | ||
| 11 | */ | ||
| 12 | #ifndef __MACH_COMMON_H | ||
| 13 | #define __MACH_COMMON_H | ||
| 14 | |||
| 15 | extern struct sys_timer msm7x01_timer; | ||
| 16 | extern struct sys_timer msm7x30_timer; | ||
| 17 | extern struct sys_timer msm_dt_timer; | ||
| 18 | extern struct sys_timer qsd8x50_timer; | ||
| 19 | |||
| 20 | extern void msm_map_common_io(void); | ||
| 21 | extern void msm_map_msm7x30_io(void); | ||
| 22 | extern void msm_map_msm8x60_io(void); | ||
| 23 | extern void msm_map_msm8960_io(void); | ||
| 24 | extern void msm_map_qsd8x50_io(void); | ||
| 25 | |||
| 26 | extern void __iomem *__msm_ioremap_caller(unsigned long phys_addr, size_t size, | ||
| 27 | unsigned int mtype, void *caller); | ||
| 28 | |||
| 29 | |||
| 30 | #endif | ||
diff --git a/arch/arm/mach-msm/devices-msm8960.c b/arch/arm/mach-msm/devices-msm8960.c deleted file mode 100644 index d9e1f26475de..000000000000 --- a/arch/arm/mach-msm/devices-msm8960.c +++ /dev/null | |||
| @@ -1,85 +0,0 @@ | |||
| 1 | /* Copyright (c) 2011, Code Aurora Forum. All rights reserved. | ||
| 2 | * | ||
| 3 | * This program is free software; you can redistribute it and/or modify | ||
| 4 | * it under the terms of the GNU General Public License version 2 and | ||
| 5 | * only version 2 as published by the Free Software Foundation. | ||
| 6 | * | ||
| 7 | * This program is distributed in the hope that it will be useful, | ||
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 10 | * GNU General Public License for more details. | ||
| 11 | * | ||
| 12 | * You should have received a copy of the GNU General Public License | ||
| 13 | * along with this program; if not, write to the Free Software | ||
| 14 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA | ||
| 15 | * 02110-1301, USA. | ||
| 16 | */ | ||
| 17 | |||
| 18 | #include <linux/kernel.h> | ||
| 19 | #include <linux/platform_device.h> | ||
| 20 | |||
| 21 | #include <linux/dma-mapping.h> | ||
| 22 | #include <mach/irqs-8960.h> | ||
| 23 | #include <mach/board.h> | ||
| 24 | |||
| 25 | #include "devices.h" | ||
| 26 | |||
| 27 | #define MSM_GSBI2_PHYS 0x16100000 | ||
| 28 | #define MSM_UART2DM_PHYS (MSM_GSBI2_PHYS + 0x40000) | ||
| 29 | |||
| 30 | #define MSM_GSBI5_PHYS 0x16400000 | ||
| 31 | #define MSM_UART5DM_PHYS (MSM_GSBI5_PHYS + 0x40000) | ||
| 32 | |||
| 33 | static struct resource resources_uart_gsbi2[] = { | ||
| 34 | { | ||
| 35 | .start = GSBI2_UARTDM_IRQ, | ||
| 36 | .end = GSBI2_UARTDM_IRQ, | ||
| 37 | .flags = IORESOURCE_IRQ, | ||
| 38 | }, | ||
| 39 | { | ||
| 40 | .start = MSM_UART2DM_PHYS, | ||
| 41 | .end = MSM_UART2DM_PHYS + PAGE_SIZE - 1, | ||
| 42 | .name = "uart_resource", | ||
| 43 | .flags = IORESOURCE_MEM, | ||
| 44 | }, | ||
| 45 | { | ||
| 46 | .start = MSM_GSBI2_PHYS, | ||
| 47 | .end = MSM_GSBI2_PHYS + PAGE_SIZE - 1, | ||
| 48 | .name = "gsbi_resource", | ||
| 49 | .flags = IORESOURCE_MEM, | ||
| 50 | }, | ||
| 51 | }; | ||
| 52 | |||
| 53 | struct platform_device msm8960_device_uart_gsbi2 = { | ||
| 54 | .name = "msm_serial", | ||
| 55 | .id = 0, | ||
| 56 | .num_resources = ARRAY_SIZE(resources_uart_gsbi2), | ||
| 57 | .resource = resources_uart_gsbi2, | ||
| 58 | }; | ||
| 59 | |||
| 60 | static struct resource resources_uart_gsbi5[] = { | ||
| 61 | { | ||
| 62 | .start = GSBI5_UARTDM_IRQ, | ||
| 63 | .end = GSBI5_UARTDM_IRQ, | ||
| 64 | .flags = IORESOURCE_IRQ, | ||
| 65 | }, | ||
| 66 | { | ||
| 67 | .start = MSM_UART5DM_PHYS, | ||
| 68 | .end = MSM_UART5DM_PHYS + PAGE_SIZE - 1, | ||
| 69 | .name = "uart_resource", | ||
| 70 | .flags = IORESOURCE_MEM, | ||
| 71 | }, | ||
| 72 | { | ||
| 73 | .start = MSM_GSBI5_PHYS, | ||
| 74 | .end = MSM_GSBI5_PHYS + PAGE_SIZE - 1, | ||
| 75 | .name = "gsbi_resource", | ||
| 76 | .flags = IORESOURCE_MEM, | ||
| 77 | }, | ||
| 78 | }; | ||
| 79 | |||
| 80 | struct platform_device msm8960_device_uart_gsbi5 = { | ||
| 81 | .name = "msm_serial", | ||
| 82 | .id = 0, | ||
| 83 | .num_resources = ARRAY_SIZE(resources_uart_gsbi5), | ||
| 84 | .resource = resources_uart_gsbi5, | ||
| 85 | }; | ||
diff --git a/arch/arm/mach-msm/dma.c b/arch/arm/mach-msm/dma.c index 02cae5e2951c..354b91d4c3ac 100644 --- a/arch/arm/mach-msm/dma.c +++ b/arch/arm/mach-msm/dma.c | |||
| @@ -223,8 +223,7 @@ static irqreturn_t msm_datamover_irq_handler(int irq, void *dev_id) | |||
| 223 | PRINT_FLOW("msm_datamover_irq_handler id %d, status %x\n", id, ch_status); | 223 | PRINT_FLOW("msm_datamover_irq_handler id %d, status %x\n", id, ch_status); |
| 224 | if ((ch_status & DMOV_STATUS_CMD_PTR_RDY) && !list_empty(&ready_commands[id])) { | 224 | if ((ch_status & DMOV_STATUS_CMD_PTR_RDY) && !list_empty(&ready_commands[id])) { |
| 225 | cmd = list_entry(ready_commands[id].next, typeof(*cmd), list); | 225 | cmd = list_entry(ready_commands[id].next, typeof(*cmd), list); |
| 226 | list_del(&cmd->list); | 226 | list_move_tail(&cmd->list, &active_commands[id]); |
| 227 | list_add_tail(&cmd->list, &active_commands[id]); | ||
| 228 | if (cmd->execute_func) | 227 | if (cmd->execute_func) |
| 229 | cmd->execute_func(cmd); | 228 | cmd->execute_func(cmd); |
| 230 | PRINT_FLOW("msm_datamover_irq_handler id %d, start command\n", id); | 229 | PRINT_FLOW("msm_datamover_irq_handler id %d, start command\n", id); |
diff --git a/arch/arm/mach-msm/idle.c b/arch/arm/mach-msm/idle.c deleted file mode 100644 index 0c9e13c65743..000000000000 --- a/arch/arm/mach-msm/idle.c +++ /dev/null | |||
| @@ -1,49 +0,0 @@ | |||
| 1 | /* arch/arm/mach-msm/idle.c | ||
| 2 | * | ||
| 3 | * Idle processing for MSM7K - work around bugs with SWFI. | ||
| 4 | * | ||
| 5 | * Copyright (c) 2007 QUALCOMM Incorporated. | ||
| 6 | * Copyright (C) 2007 Google, Inc. | ||
| 7 | * | ||
| 8 | * This software is licensed under the terms of the GNU General Public | ||
| 9 | * License version 2, as published by the Free Software Foundation, and | ||
| 10 | * may be copied, distributed, and modified under those terms. | ||
| 11 | * | ||
| 12 | * This program is distributed in the hope that it will be useful, | ||
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 15 | * GNU General Public License for more details. | ||
| 16 | * | ||
| 17 | */ | ||
| 18 | |||
| 19 | #include <linux/init.h> | ||
| 20 | #include <asm/system.h> | ||
| 21 | |||
| 22 | static void msm_idle(void) | ||
| 23 | { | ||
| 24 | #ifdef CONFIG_MSM7X00A_IDLE | ||
| 25 | asm volatile ( | ||
| 26 | |||
| 27 | "mrc p15, 0, r1, c1, c0, 0 /* read current CR */ \n\t" | ||
| 28 | "bic r0, r1, #(1 << 2) /* clear dcache bit */ \n\t" | ||
| 29 | "bic r0, r0, #(1 << 12) /* clear icache bit */ \n\t" | ||
| 30 | "mcr p15, 0, r0, c1, c0, 0 /* disable d/i cache */ \n\t" | ||
| 31 | |||
| 32 | "mov r0, #0 /* prepare wfi value */ \n\t" | ||
| 33 | "mcr p15, 0, r0, c7, c10, 0 /* flush the cache */ \n\t" | ||
| 34 | "mcr p15, 0, r0, c7, c10, 4 /* memory barrier */ \n\t" | ||
| 35 | "mcr p15, 0, r0, c7, c0, 4 /* wait for interrupt */ \n\t" | ||
| 36 | |||
| 37 | "mcr p15, 0, r1, c1, c0, 0 /* restore d/i cache */ \n\t" | ||
| 38 | |||
| 39 | : : : "r0","r1" ); | ||
| 40 | #endif | ||
| 41 | } | ||
| 42 | |||
| 43 | static int __init msm_idle_init(void) | ||
| 44 | { | ||
| 45 | arm_pm_idle = msm_idle; | ||
| 46 | return 0; | ||
| 47 | } | ||
| 48 | |||
| 49 | arch_initcall(msm_idle_init); | ||
diff --git a/arch/arm/mach-msm/include/mach/board.h b/arch/arm/mach-msm/include/mach/board.h index 435f8edfafd1..0a0c393d8e31 100644 --- a/arch/arm/mach-msm/include/mach/board.h +++ b/arch/arm/mach-msm/include/mach/board.h | |||
| @@ -22,27 +22,14 @@ | |||
| 22 | 22 | ||
| 23 | /* platform device data structures */ | 23 | /* platform device data structures */ |
| 24 | 24 | ||
| 25 | struct msm_acpu_clock_platform_data | ||
| 26 | { | ||
| 27 | uint32_t acpu_switch_time_us; | ||
| 28 | uint32_t max_speed_delta_khz; | ||
| 29 | uint32_t vdd_switch_time_us; | ||
| 30 | unsigned long power_collapse_khz; | ||
| 31 | unsigned long wait_for_irq_khz; | ||
| 32 | }; | ||
| 33 | |||
| 34 | struct clk_lookup; | 25 | struct clk_lookup; |
| 35 | 26 | ||
| 36 | extern struct sys_timer msm_timer; | ||
| 37 | |||
| 38 | /* common init routines for use by arch/arm/mach-msm/board-*.c */ | 27 | /* common init routines for use by arch/arm/mach-msm/board-*.c */ |
| 39 | 28 | ||
| 40 | void __init msm_add_devices(void); | 29 | void __init msm_add_devices(void); |
| 41 | void __init msm_map_common_io(void); | ||
| 42 | void __init msm_init_irq(void); | 30 | void __init msm_init_irq(void); |
| 43 | void __init msm_init_gpio(void); | 31 | void __init msm_init_gpio(void); |
| 44 | void __init msm_clock_init(struct clk_lookup *clock_tbl, unsigned num_clocks); | 32 | void __init msm_clock_init(struct clk_lookup *clock_tbl, unsigned num_clocks); |
| 45 | void __init msm_acpu_clock_init(struct msm_acpu_clock_platform_data *); | ||
| 46 | int __init msm_add_sdcc(unsigned int controller, | 33 | int __init msm_add_sdcc(unsigned int controller, |
| 47 | struct msm_mmc_platform_data *plat, | 34 | struct msm_mmc_platform_data *plat, |
| 48 | unsigned int stat_irq, unsigned long stat_irq_flags); | 35 | unsigned int stat_irq, unsigned long stat_irq_flags); |
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h b/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h index 6c4046c21296..67dc0e98b958 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h | |||
| @@ -105,11 +105,4 @@ | |||
| 105 | #define MSM_AD5_PHYS 0xAC000000 | 105 | #define MSM_AD5_PHYS 0xAC000000 |
| 106 | #define MSM_AD5_SIZE (SZ_1M*13) | 106 | #define MSM_AD5_SIZE (SZ_1M*13) |
| 107 | 107 | ||
| 108 | #ifndef __ASSEMBLY__ | ||
| 109 | |||
| 110 | extern void __iomem *__msm_ioremap_caller(unsigned long phys_addr, size_t size, | ||
| 111 | unsigned int mtype, void *caller); | ||
| 112 | |||
| 113 | #endif | ||
| 114 | |||
| 115 | #endif | 108 | #endif |
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h b/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h index f944fe65a657..198202c267c8 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h | |||
| @@ -100,8 +100,4 @@ | |||
| 100 | #define MSM_HSUSB_PHYS 0xA3600000 | 100 | #define MSM_HSUSB_PHYS 0xA3600000 |
| 101 | #define MSM_HSUSB_SIZE SZ_1K | 101 | #define MSM_HSUSB_SIZE SZ_1K |
| 102 | 102 | ||
| 103 | #ifndef __ASSEMBLY__ | ||
| 104 | extern void msm_map_msm7x30_io(void); | ||
| 105 | #endif | ||
| 106 | |||
| 107 | #endif | 103 | #endif |
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8960.h b/arch/arm/mach-msm/include/mach/msm_iomap-8960.h index a1752c0284fc..9819a556acae 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap-8960.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap-8960.h | |||
| @@ -46,12 +46,8 @@ | |||
| 46 | #define MSM8960_TMR0_SIZE SZ_4K | 46 | #define MSM8960_TMR0_SIZE SZ_4K |
| 47 | 47 | ||
| 48 | #ifdef CONFIG_DEBUG_MSM8960_UART | 48 | #ifdef CONFIG_DEBUG_MSM8960_UART |
| 49 | #define MSM_DEBUG_UART_BASE 0xE1040000 | 49 | #define MSM_DEBUG_UART_BASE 0xF0040000 |
| 50 | #define MSM_DEBUG_UART_PHYS 0x16440000 | 50 | #define MSM_DEBUG_UART_PHYS 0x16440000 |
| 51 | #endif | 51 | #endif |
| 52 | 52 | ||
| 53 | #ifndef __ASSEMBLY__ | ||
| 54 | extern void msm_map_msm8960_io(void); | ||
| 55 | #endif | ||
| 56 | |||
| 57 | #endif | 53 | #endif |
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h index da77cc1d545d..0faa894729b7 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h | |||
| @@ -122,8 +122,4 @@ | |||
| 122 | #define MSM_SDC4_PHYS 0xA0600000 | 122 | #define MSM_SDC4_PHYS 0xA0600000 |
| 123 | #define MSM_SDC4_SIZE SZ_4K | 123 | #define MSM_SDC4_SIZE SZ_4K |
| 124 | 124 | ||
| 125 | #ifndef __ASSEMBLY__ | ||
| 126 | extern void msm_map_qsd8x50_io(void); | ||
| 127 | #endif | ||
| 128 | |||
| 129 | #endif | 125 | #endif |
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h index 5aed57dc808c..c6d38f1d0c98 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h | |||
| @@ -63,12 +63,8 @@ | |||
| 63 | #define MSM8X60_TMR0_SIZE SZ_4K | 63 | #define MSM8X60_TMR0_SIZE SZ_4K |
| 64 | 64 | ||
| 65 | #ifdef CONFIG_DEBUG_MSM8660_UART | 65 | #ifdef CONFIG_DEBUG_MSM8660_UART |
| 66 | #define MSM_DEBUG_UART_BASE 0xE1040000 | 66 | #define MSM_DEBUG_UART_BASE 0xF0040000 |
| 67 | #define MSM_DEBUG_UART_PHYS 0x19C40000 | 67 | #define MSM_DEBUG_UART_PHYS 0x19C40000 |
| 68 | #endif | 68 | #endif |
| 69 | 69 | ||
| 70 | #ifndef __ASSEMBLY__ | ||
| 71 | extern void msm_map_msm8x60_io(void); | ||
| 72 | #endif | ||
| 73 | |||
| 74 | #endif | 70 | #endif |
diff --git a/arch/arm/mach-msm/include/mach/system.h b/arch/arm/mach-msm/include/mach/system.h deleted file mode 100644 index f5fb2ec87ffe..000000000000 --- a/arch/arm/mach-msm/include/mach/system.h +++ /dev/null | |||
| @@ -1,19 +0,0 @@ | |||
| 1 | /* arch/arm/mach-msm/include/mach/system.h | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Google, Inc. | ||
| 4 | * | ||
| 5 | * This software is licensed under the terms of the GNU General Public | ||
| 6 | * License version 2, as published by the Free Software Foundation, and | ||
| 7 | * may be copied, distributed, and modified under those terms. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | * | ||
| 14 | */ | ||
| 15 | |||
| 16 | /* low level hardware reset hook -- for example, hitting the | ||
| 17 | * PSHOLD line on the PMIC to hard reset the system | ||
| 18 | */ | ||
| 19 | extern void (*msm_hw_reset_hook)(void); | ||
diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c index a1e7b1168850..3854f6f20ce2 100644 --- a/arch/arm/mach-msm/io.c +++ b/arch/arm/mach-msm/io.c | |||
| @@ -29,30 +29,32 @@ | |||
| 29 | 29 | ||
| 30 | #include <mach/board.h> | 30 | #include <mach/board.h> |
| 31 | 31 | ||
| 32 | #define MSM_CHIP_DEVICE(name, chip) { \ | 32 | #include "common.h" |
| 33 | |||
| 34 | #define MSM_CHIP_DEVICE_TYPE(name, chip, mem_type) { \ | ||
| 33 | .virtual = (unsigned long) MSM_##name##_BASE, \ | 35 | .virtual = (unsigned long) MSM_##name##_BASE, \ |
| 34 | .pfn = __phys_to_pfn(chip##_##name##_PHYS), \ | 36 | .pfn = __phys_to_pfn(chip##_##name##_PHYS), \ |
| 35 | .length = chip##_##name##_SIZE, \ | 37 | .length = chip##_##name##_SIZE, \ |
| 36 | .type = MT_DEVICE_NONSHARED, \ | 38 | .type = mem_type, \ |
| 37 | } | 39 | } |
| 38 | 40 | ||
| 41 | #define MSM_DEVICE_TYPE(name, mem_type) \ | ||
| 42 | MSM_CHIP_DEVICE_TYPE(name, MSM, mem_type) | ||
| 43 | #define MSM_CHIP_DEVICE(name, chip) \ | ||
| 44 | MSM_CHIP_DEVICE_TYPE(name, chip, MT_DEVICE) | ||
| 39 | #define MSM_DEVICE(name) MSM_CHIP_DEVICE(name, MSM) | 45 | #define MSM_DEVICE(name) MSM_CHIP_DEVICE(name, MSM) |
| 40 | 46 | ||
| 41 | #if defined(CONFIG_ARCH_MSM7X00A) || defined(CONFIG_ARCH_MSM7X27) \ | 47 | #if defined(CONFIG_ARCH_MSM7X00A) |
| 42 | || defined(CONFIG_ARCH_MSM7X25) | ||
| 43 | static struct map_desc msm_io_desc[] __initdata = { | 48 | static struct map_desc msm_io_desc[] __initdata = { |
| 44 | MSM_DEVICE(VIC), | 49 | MSM_DEVICE_TYPE(VIC, MT_DEVICE_NONSHARED), |
| 45 | MSM_CHIP_DEVICE(CSR, MSM7X00), | 50 | MSM_CHIP_DEVICE_TYPE(CSR, MSM7X00, MT_DEVICE_NONSHARED), |
| 46 | MSM_DEVICE(DMOV), | 51 | MSM_DEVICE_TYPE(DMOV, MT_DEVICE_NONSHARED), |
| 47 | MSM_CHIP_DEVICE(GPIO1, MSM7X00), | 52 | MSM_CHIP_DEVICE_TYPE(GPIO1, MSM7X00, MT_DEVICE_NONSHARED), |
| 48 | MSM_CHIP_DEVICE(GPIO2, MSM7X00), | 53 | MSM_CHIP_DEVICE_TYPE(GPIO2, MSM7X00, MT_DEVICE_NONSHARED), |
| 49 | MSM_DEVICE(CLK_CTL), | 54 | MSM_DEVICE_TYPE(CLK_CTL, MT_DEVICE_NONSHARED), |
| 50 | #if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \ | 55 | #if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \ |
| 51 | defined(CONFIG_DEBUG_MSM_UART3) | 56 | defined(CONFIG_DEBUG_MSM_UART3) |
| 52 | MSM_DEVICE(DEBUG_UART), | 57 | MSM_DEVICE_TYPE(DEBUG_UART, MT_DEVICE_NONSHARED), |
| 53 | #endif | ||
| 54 | #ifdef CONFIG_ARCH_MSM7X30 | ||
| 55 | MSM_DEVICE(GCC), | ||
| 56 | #endif | 58 | #endif |
| 57 | { | 59 | { |
| 58 | .virtual = (unsigned long) MSM_SHARED_RAM_BASE, | 60 | .virtual = (unsigned long) MSM_SHARED_RAM_BASE, |
diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-msm/platsmp.c index e012dc8391cf..2d791e6b4ad1 100644 --- a/arch/arm/mach-msm/platsmp.c +++ b/arch/arm/mach-msm/platsmp.c | |||
| @@ -22,17 +22,12 @@ | |||
| 22 | #include <asm/mach-types.h> | 22 | #include <asm/mach-types.h> |
| 23 | #include <asm/smp_plat.h> | 23 | #include <asm/smp_plat.h> |
| 24 | 24 | ||
| 25 | #include <mach/msm_iomap.h> | ||
| 26 | |||
| 27 | #include "scm-boot.h" | 25 | #include "scm-boot.h" |
| 28 | 26 | ||
| 29 | #define VDD_SC1_ARRAY_CLAMP_GFS_CTL 0x15A0 | 27 | #define VDD_SC1_ARRAY_CLAMP_GFS_CTL 0x15A0 |
| 30 | #define SCSS_CPU1CORE_RESET 0xD80 | 28 | #define SCSS_CPU1CORE_RESET 0xD80 |
| 31 | #define SCSS_DBG_STATUS_CORE_PWRDUP 0xE64 | 29 | #define SCSS_DBG_STATUS_CORE_PWRDUP 0xE64 |
| 32 | 30 | ||
| 33 | /* Mask for edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */ | ||
| 34 | #define GIC_PPI_EDGE_MASK 0xFFFFD7FF | ||
| 35 | |||
| 36 | extern void msm_secondary_startup(void); | 31 | extern void msm_secondary_startup(void); |
| 37 | /* | 32 | /* |
| 38 | * control for which core is the next to come out of the secondary | 33 | * control for which core is the next to come out of the secondary |
| @@ -50,9 +45,6 @@ static inline int get_core_count(void) | |||
| 50 | 45 | ||
| 51 | void __cpuinit platform_secondary_init(unsigned int cpu) | 46 | void __cpuinit platform_secondary_init(unsigned int cpu) |
| 52 | { | 47 | { |
| 53 | /* Configure edge-triggered PPIs */ | ||
| 54 | writel(GIC_PPI_EDGE_MASK, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4); | ||
| 55 | |||
| 56 | /* | 48 | /* |
| 57 | * if any interrupts are already enabled for the primary | 49 | * if any interrupts are already enabled for the primary |
| 58 | * core (e.g. timer irq), then they will not have been enabled | 50 | * core (e.g. timer irq), then they will not have been enabled |
diff --git a/arch/arm/mach-msm/proc_comm.c b/arch/arm/mach-msm/proc_comm.c index 9980dc736e7b..8f1eecd88186 100644 --- a/arch/arm/mach-msm/proc_comm.c +++ b/arch/arm/mach-msm/proc_comm.c | |||
| @@ -19,7 +19,6 @@ | |||
| 19 | #include <linux/io.h> | 19 | #include <linux/io.h> |
| 20 | #include <linux/spinlock.h> | 20 | #include <linux/spinlock.h> |
| 21 | #include <mach/msm_iomap.h> | 21 | #include <mach/msm_iomap.h> |
| 22 | #include <mach/system.h> | ||
| 23 | 22 | ||
| 24 | #include "proc_comm.h" | 23 | #include "proc_comm.h" |
| 25 | 24 | ||
diff --git a/arch/arm/mach-msm/smd.c b/arch/arm/mach-msm/smd.c index 657be73297db..84183ed2ef79 100644 --- a/arch/arm/mach-msm/smd.c +++ b/arch/arm/mach-msm/smd.c | |||
| @@ -30,7 +30,6 @@ | |||
| 30 | #include <linux/delay.h> | 30 | #include <linux/delay.h> |
| 31 | 31 | ||
| 32 | #include <mach/msm_smd.h> | 32 | #include <mach/msm_smd.h> |
| 33 | #include <mach/system.h> | ||
| 34 | 33 | ||
| 35 | #include "smd_private.h" | 34 | #include "smd_private.h" |
| 36 | #include "proc_comm.h" | 35 | #include "proc_comm.h" |
| @@ -39,8 +38,6 @@ | |||
| 39 | #define CONFIG_QDSP6 1 | 38 | #define CONFIG_QDSP6 1 |
| 40 | #endif | 39 | #endif |
| 41 | 40 | ||
| 42 | void (*msm_hw_reset_hook)(void); | ||
| 43 | |||
| 44 | #define MODULE_NAME "msm_smd" | 41 | #define MODULE_NAME "msm_smd" |
| 45 | 42 | ||
| 46 | enum { | 43 | enum { |
| @@ -101,10 +98,6 @@ static void handle_modem_crash(void) | |||
| 101 | pr_err("ARM9 has CRASHED\n"); | 98 | pr_err("ARM9 has CRASHED\n"); |
| 102 | smd_diag(); | 99 | smd_diag(); |
| 103 | 100 | ||
| 104 | /* hard reboot if possible */ | ||
| 105 | if (msm_hw_reset_hook) | ||
| 106 | msm_hw_reset_hook(); | ||
| 107 | |||
| 108 | /* in this case the modem or watchdog should reboot us */ | 101 | /* in this case the modem or watchdog should reboot us */ |
| 109 | for (;;) | 102 | for (;;) |
| 110 | ; | 103 | ; |
diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c index 812808254936..476549a8a709 100644 --- a/arch/arm/mach-msm/timer.c +++ b/arch/arm/mach-msm/timer.c | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * | 2 | * |
| 3 | * Copyright (C) 2007 Google, Inc. | 3 | * Copyright (C) 2007 Google, Inc. |
| 4 | * Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved. | 4 | * Copyright (c) 2009-2012, The Linux Foundation. All rights reserved. |
| 5 | * | 5 | * |
| 6 | * This software is licensed under the terms of the GNU General Public | 6 | * This software is licensed under the terms of the GNU General Public |
| 7 | * License version 2, as published by the Free Software Foundation, and | 7 | * License version 2, as published by the Free Software Foundation, and |
| @@ -20,15 +20,16 @@ | |||
| 20 | #include <linux/interrupt.h> | 20 | #include <linux/interrupt.h> |
| 21 | #include <linux/irq.h> | 21 | #include <linux/irq.h> |
| 22 | #include <linux/io.h> | 22 | #include <linux/io.h> |
| 23 | #include <linux/of.h> | ||
| 24 | #include <linux/of_address.h> | ||
| 25 | #include <linux/of_irq.h> | ||
| 23 | 26 | ||
| 24 | #include <asm/mach/time.h> | 27 | #include <asm/mach/time.h> |
| 25 | #include <asm/hardware/gic.h> | 28 | #include <asm/hardware/gic.h> |
| 26 | #include <asm/localtimer.h> | 29 | #include <asm/localtimer.h> |
| 27 | #include <asm/sched_clock.h> | 30 | #include <asm/sched_clock.h> |
| 28 | 31 | ||
| 29 | #include <mach/msm_iomap.h> | 32 | #include "common.h" |
| 30 | #include <mach/cpu.h> | ||
| 31 | #include <mach/board.h> | ||
| 32 | 33 | ||
| 33 | #define TIMER_MATCH_VAL 0x0000 | 34 | #define TIMER_MATCH_VAL 0x0000 |
| 34 | #define TIMER_COUNT_VAL 0x0004 | 35 | #define TIMER_COUNT_VAL 0x0004 |
| @@ -36,7 +37,6 @@ | |||
| 36 | #define TIMER_ENABLE_CLR_ON_MATCH_EN BIT(1) | 37 | #define TIMER_ENABLE_CLR_ON_MATCH_EN BIT(1) |
| 37 | #define TIMER_ENABLE_EN BIT(0) | 38 | #define TIMER_ENABLE_EN BIT(0) |
| 38 | #define TIMER_CLEAR 0x000C | 39 | #define TIMER_CLEAR 0x000C |
| 39 | #define DGT_CLK_CTL 0x0034 | ||
| 40 | #define DGT_CLK_CTL_DIV_4 0x3 | 40 | #define DGT_CLK_CTL_DIV_4 0x3 |
| 41 | 41 | ||
| 42 | #define GPT_HZ 32768 | 42 | #define GPT_HZ 32768 |
| @@ -101,7 +101,7 @@ static struct clock_event_device msm_clockevent = { | |||
| 101 | 101 | ||
| 102 | static union { | 102 | static union { |
| 103 | struct clock_event_device *evt; | 103 | struct clock_event_device *evt; |
| 104 | struct clock_event_device __percpu **percpu_evt; | 104 | struct clock_event_device * __percpu *percpu_evt; |
| 105 | } msm_evt; | 105 | } msm_evt; |
| 106 | 106 | ||
| 107 | static void __iomem *source_base; | 107 | static void __iomem *source_base; |
| @@ -151,7 +151,7 @@ static int __cpuinit msm_local_timer_setup(struct clock_event_device *evt) | |||
| 151 | 151 | ||
| 152 | *__this_cpu_ptr(msm_evt.percpu_evt) = evt; | 152 | *__this_cpu_ptr(msm_evt.percpu_evt) = evt; |
| 153 | clockevents_register_device(evt); | 153 | clockevents_register_device(evt); |
| 154 | enable_percpu_irq(evt->irq, 0); | 154 | enable_percpu_irq(evt->irq, IRQ_TYPE_EDGE_RISING); |
| 155 | return 0; | 155 | return 0; |
| 156 | } | 156 | } |
| 157 | 157 | ||
| @@ -172,44 +172,21 @@ static notrace u32 msm_sched_clock_read(void) | |||
| 172 | return msm_clocksource.read(&msm_clocksource); | 172 | return msm_clocksource.read(&msm_clocksource); |
| 173 | } | 173 | } |
| 174 | 174 | ||
| 175 | static void __init msm_timer_init(void) | 175 | static void __init msm_timer_init(u32 dgt_hz, int sched_bits, int irq, |
| 176 | bool percpu) | ||
| 176 | { | 177 | { |
| 177 | struct clock_event_device *ce = &msm_clockevent; | 178 | struct clock_event_device *ce = &msm_clockevent; |
| 178 | struct clocksource *cs = &msm_clocksource; | 179 | struct clocksource *cs = &msm_clocksource; |
| 179 | int res; | 180 | int res; |
| 180 | u32 dgt_hz; | ||
| 181 | |||
| 182 | if (cpu_is_msm7x01()) { | ||
| 183 | event_base = MSM_CSR_BASE; | ||
| 184 | source_base = MSM_CSR_BASE + 0x10; | ||
| 185 | dgt_hz = 19200000 >> MSM_DGT_SHIFT; /* 600 KHz */ | ||
| 186 | cs->read = msm_read_timer_count_shift; | ||
| 187 | cs->mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT)); | ||
| 188 | } else if (cpu_is_msm7x30()) { | ||
| 189 | event_base = MSM_CSR_BASE + 0x04; | ||
| 190 | source_base = MSM_CSR_BASE + 0x24; | ||
| 191 | dgt_hz = 24576000 / 4; | ||
| 192 | } else if (cpu_is_qsd8x50()) { | ||
| 193 | event_base = MSM_CSR_BASE; | ||
| 194 | source_base = MSM_CSR_BASE + 0x10; | ||
| 195 | dgt_hz = 19200000 / 4; | ||
| 196 | } else if (cpu_is_msm8x60() || cpu_is_msm8960()) { | ||
| 197 | event_base = MSM_TMR_BASE + 0x04; | ||
| 198 | /* Use CPU0's timer as the global clock source. */ | ||
| 199 | source_base = MSM_TMR0_BASE + 0x24; | ||
| 200 | dgt_hz = 27000000 / 4; | ||
| 201 | writel_relaxed(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL); | ||
| 202 | } else | ||
| 203 | BUG(); | ||
| 204 | 181 | ||
| 205 | writel_relaxed(0, event_base + TIMER_ENABLE); | 182 | writel_relaxed(0, event_base + TIMER_ENABLE); |
| 206 | writel_relaxed(0, event_base + TIMER_CLEAR); | 183 | writel_relaxed(0, event_base + TIMER_CLEAR); |
| 207 | writel_relaxed(~0, event_base + TIMER_MATCH_VAL); | 184 | writel_relaxed(~0, event_base + TIMER_MATCH_VAL); |
| 208 | ce->cpumask = cpumask_of(0); | 185 | ce->cpumask = cpumask_of(0); |
| 186 | ce->irq = irq; | ||
| 209 | 187 | ||
| 210 | ce->irq = INT_GP_TIMER_EXP; | ||
| 211 | clockevents_config_and_register(ce, GPT_HZ, 4, 0xffffffff); | 188 | clockevents_config_and_register(ce, GPT_HZ, 4, 0xffffffff); |
| 212 | if (cpu_is_msm8x60() || cpu_is_msm8960()) { | 189 | if (percpu) { |
| 213 | msm_evt.percpu_evt = alloc_percpu(struct clock_event_device *); | 190 | msm_evt.percpu_evt = alloc_percpu(struct clock_event_device *); |
| 214 | if (!msm_evt.percpu_evt) { | 191 | if (!msm_evt.percpu_evt) { |
| 215 | pr_err("memory allocation failed for %s\n", ce->name); | 192 | pr_err("memory allocation failed for %s\n", ce->name); |
| @@ -219,7 +196,7 @@ static void __init msm_timer_init(void) | |||
| 219 | res = request_percpu_irq(ce->irq, msm_timer_interrupt, | 196 | res = request_percpu_irq(ce->irq, msm_timer_interrupt, |
| 220 | ce->name, msm_evt.percpu_evt); | 197 | ce->name, msm_evt.percpu_evt); |
| 221 | if (!res) { | 198 | if (!res) { |
| 222 | enable_percpu_irq(ce->irq, 0); | 199 | enable_percpu_irq(ce->irq, IRQ_TYPE_EDGE_RISING); |
| 223 | #ifdef CONFIG_LOCAL_TIMERS | 200 | #ifdef CONFIG_LOCAL_TIMERS |
| 224 | local_timer_register(&msm_local_timer_ops); | 201 | local_timer_register(&msm_local_timer_ops); |
| 225 | #endif | 202 | #endif |
| @@ -238,10 +215,143 @@ err: | |||
| 238 | res = clocksource_register_hz(cs, dgt_hz); | 215 | res = clocksource_register_hz(cs, dgt_hz); |
| 239 | if (res) | 216 | if (res) |
| 240 | pr_err("clocksource_register failed\n"); | 217 | pr_err("clocksource_register failed\n"); |
| 241 | setup_sched_clock(msm_sched_clock_read, | 218 | setup_sched_clock(msm_sched_clock_read, sched_bits, dgt_hz); |
| 242 | cpu_is_msm7x01() ? 32 - MSM_DGT_SHIFT : 32, dgt_hz); | ||
| 243 | } | 219 | } |
| 244 | 220 | ||
| 245 | struct sys_timer msm_timer = { | 221 | #ifdef CONFIG_OF |
| 246 | .init = msm_timer_init | 222 | static const struct of_device_id msm_dgt_match[] __initconst = { |
| 223 | { .compatible = "qcom,msm-dgt" }, | ||
| 224 | { }, | ||
| 225 | }; | ||
| 226 | |||
| 227 | static const struct of_device_id msm_gpt_match[] __initconst = { | ||
| 228 | { .compatible = "qcom,msm-gpt" }, | ||
| 229 | { }, | ||
| 230 | }; | ||
| 231 | |||
| 232 | static void __init msm_dt_timer_init(void) | ||
| 233 | { | ||
| 234 | struct device_node *np; | ||
| 235 | u32 freq; | ||
| 236 | int irq; | ||
| 237 | struct resource res; | ||
| 238 | u32 percpu_offset; | ||
| 239 | void __iomem *dgt_clk_ctl; | ||
| 240 | |||
| 241 | np = of_find_matching_node(NULL, msm_gpt_match); | ||
| 242 | if (!np) { | ||
| 243 | pr_err("Can't find GPT DT node\n"); | ||
| 244 | return; | ||
| 245 | } | ||
| 246 | |||
| 247 | event_base = of_iomap(np, 0); | ||
| 248 | if (!event_base) { | ||
| 249 | pr_err("Failed to map event base\n"); | ||
| 250 | return; | ||
| 251 | } | ||
| 252 | |||
| 253 | irq = irq_of_parse_and_map(np, 0); | ||
| 254 | if (irq <= 0) { | ||
| 255 | pr_err("Can't get irq\n"); | ||
| 256 | return; | ||
| 257 | } | ||
| 258 | of_node_put(np); | ||
| 259 | |||
| 260 | np = of_find_matching_node(NULL, msm_dgt_match); | ||
| 261 | if (!np) { | ||
| 262 | pr_err("Can't find DGT DT node\n"); | ||
| 263 | return; | ||
| 264 | } | ||
| 265 | |||
| 266 | if (of_property_read_u32(np, "cpu-offset", &percpu_offset)) | ||
| 267 | percpu_offset = 0; | ||
| 268 | |||
| 269 | if (of_address_to_resource(np, 0, &res)) { | ||
| 270 | pr_err("Failed to parse DGT resource\n"); | ||
| 271 | return; | ||
| 272 | } | ||
| 273 | |||
| 274 | source_base = ioremap(res.start + percpu_offset, resource_size(&res)); | ||
| 275 | if (!source_base) { | ||
| 276 | pr_err("Failed to map source base\n"); | ||
| 277 | return; | ||
| 278 | } | ||
| 279 | |||
| 280 | if (!of_address_to_resource(np, 1, &res)) { | ||
| 281 | dgt_clk_ctl = ioremap(res.start + percpu_offset, | ||
| 282 | resource_size(&res)); | ||
| 283 | if (!dgt_clk_ctl) { | ||
| 284 | pr_err("Failed to map DGT control base\n"); | ||
| 285 | return; | ||
| 286 | } | ||
| 287 | writel_relaxed(DGT_CLK_CTL_DIV_4, dgt_clk_ctl); | ||
| 288 | iounmap(dgt_clk_ctl); | ||
| 289 | } | ||
| 290 | |||
| 291 | if (of_property_read_u32(np, "clock-frequency", &freq)) { | ||
| 292 | pr_err("Unknown frequency\n"); | ||
| 293 | return; | ||
| 294 | } | ||
| 295 | of_node_put(np); | ||
| 296 | |||
| 297 | msm_timer_init(freq, 32, irq, !!percpu_offset); | ||
| 298 | } | ||
| 299 | |||
| 300 | struct sys_timer msm_dt_timer = { | ||
| 301 | .init = msm_dt_timer_init | ||
| 302 | }; | ||
| 303 | #endif | ||
| 304 | |||
| 305 | static int __init msm_timer_map(phys_addr_t event, phys_addr_t source) | ||
| 306 | { | ||
| 307 | event_base = ioremap(event, SZ_64); | ||
| 308 | if (!event_base) { | ||
| 309 | pr_err("Failed to map event base\n"); | ||
| 310 | return 1; | ||
| 311 | } | ||
| 312 | source_base = ioremap(source, SZ_64); | ||
| 313 | if (!source_base) { | ||
| 314 | pr_err("Failed to map source base\n"); | ||
| 315 | return 1; | ||
| 316 | } | ||
| 317 | return 0; | ||
| 318 | } | ||
| 319 | |||
| 320 | static void __init msm7x01_timer_init(void) | ||
| 321 | { | ||
| 322 | struct clocksource *cs = &msm_clocksource; | ||
| 323 | |||
| 324 | if (msm_timer_map(0xc0100000, 0xc0100010)) | ||
| 325 | return; | ||
| 326 | cs->read = msm_read_timer_count_shift; | ||
| 327 | cs->mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT)); | ||
| 328 | /* 600 KHz */ | ||
| 329 | msm_timer_init(19200000 >> MSM_DGT_SHIFT, 32 - MSM_DGT_SHIFT, 7, | ||
| 330 | false); | ||
| 331 | } | ||
| 332 | |||
| 333 | struct sys_timer msm7x01_timer = { | ||
| 334 | .init = msm7x01_timer_init | ||
| 335 | }; | ||
| 336 | |||
| 337 | static void __init msm7x30_timer_init(void) | ||
| 338 | { | ||
| 339 | if (msm_timer_map(0xc0100004, 0xc0100024)) | ||
| 340 | return; | ||
| 341 | msm_timer_init(24576000 / 4, 32, 1, false); | ||
| 342 | } | ||
| 343 | |||
| 344 | struct sys_timer msm7x30_timer = { | ||
| 345 | .init = msm7x30_timer_init | ||
| 346 | }; | ||
| 347 | |||
| 348 | static void __init qsd8x50_timer_init(void) | ||
| 349 | { | ||
| 350 | if (msm_timer_map(0xAC100000, 0xAC100010)) | ||
| 351 | return; | ||
| 352 | msm_timer_init(19200000 / 4, 32, 7, false); | ||
| 353 | } | ||
| 354 | |||
| 355 | struct sys_timer qsd8x50_timer = { | ||
| 356 | .init = qsd8x50_timer_init | ||
| 247 | }; | 357 | }; |
diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig index 9a8bbda195b2..ecc431909d6f 100644 --- a/arch/arm/mach-mxs/Kconfig +++ b/arch/arm/mach-mxs/Kconfig | |||
| @@ -1,7 +1,5 @@ | |||
| 1 | if ARCH_MXS | 1 | if ARCH_MXS |
| 2 | 2 | ||
| 3 | source "arch/arm/mach-mxs/devices/Kconfig" | ||
| 4 | |||
| 5 | config SOC_IMX23 | 3 | config SOC_IMX23 |
| 6 | bool | 4 | bool |
| 7 | select ARM_AMBA | 5 | select ARM_AMBA |
| @@ -27,91 +25,4 @@ config MACH_MXS_DT | |||
| 27 | Include support for Freescale MXS platforms(i.MX23 and i.MX28) | 25 | Include support for Freescale MXS platforms(i.MX23 and i.MX28) |
| 28 | using the device tree for discovery | 26 | using the device tree for discovery |
| 29 | 27 | ||
| 30 | config MACH_STMP378X_DEVB | ||
| 31 | bool "Support STMP378x_devb Platform" | ||
| 32 | select SOC_IMX23 | ||
| 33 | select MXS_HAVE_AMBA_DUART | ||
| 34 | select MXS_HAVE_PLATFORM_AUART | ||
| 35 | select MXS_HAVE_PLATFORM_MXS_MMC | ||
| 36 | select MXS_HAVE_PLATFORM_RTC_STMP3XXX | ||
| 37 | help | ||
| 38 | Include support for STMP378x-devb platform. This includes specific | ||
| 39 | configurations for the board and its peripherals. | ||
| 40 | |||
| 41 | config MACH_MX23EVK | ||
| 42 | bool "Support MX23EVK Platform" | ||
| 43 | select SOC_IMX23 | ||
| 44 | select MXS_HAVE_AMBA_DUART | ||
| 45 | select MXS_HAVE_PLATFORM_AUART | ||
| 46 | select MXS_HAVE_PLATFORM_MXS_MMC | ||
| 47 | select MXS_HAVE_PLATFORM_MXSFB | ||
| 48 | select MXS_HAVE_PLATFORM_RTC_STMP3XXX | ||
| 49 | help | ||
| 50 | Include support for MX23EVK platform. This includes specific | ||
| 51 | configurations for the board and its peripherals. | ||
| 52 | |||
| 53 | config MACH_MX28EVK | ||
| 54 | bool "Support MX28EVK Platform" | ||
| 55 | select SOC_IMX28 | ||
| 56 | select LEDS_GPIO_REGISTER | ||
| 57 | select MXS_HAVE_AMBA_DUART | ||
| 58 | select MXS_HAVE_PLATFORM_AUART | ||
| 59 | select MXS_HAVE_PLATFORM_FEC | ||
| 60 | select MXS_HAVE_PLATFORM_FLEXCAN | ||
| 61 | select MXS_HAVE_PLATFORM_MXS_MMC | ||
| 62 | select MXS_HAVE_PLATFORM_MXSFB | ||
| 63 | select MXS_HAVE_PLATFORM_MXS_SAIF | ||
| 64 | select MXS_HAVE_PLATFORM_MXS_I2C | ||
| 65 | select MXS_HAVE_PLATFORM_RTC_STMP3XXX | ||
| 66 | help | ||
| 67 | Include support for MX28EVK platform. This includes specific | ||
| 68 | configurations for the board and its peripherals. | ||
| 69 | |||
| 70 | config MODULE_TX28 | ||
| 71 | bool | ||
| 72 | select SOC_IMX28 | ||
| 73 | select LEDS_GPIO_REGISTER | ||
| 74 | select MXS_HAVE_AMBA_DUART | ||
| 75 | select MXS_HAVE_PLATFORM_AUART | ||
| 76 | select MXS_HAVE_PLATFORM_FEC | ||
| 77 | select MXS_HAVE_PLATFORM_MXS_I2C | ||
| 78 | select MXS_HAVE_PLATFORM_MXS_MMC | ||
| 79 | select MXS_HAVE_PLATFORM_MXS_PWM | ||
| 80 | select MXS_HAVE_PLATFORM_RTC_STMP3XXX | ||
| 81 | |||
| 82 | config MODULE_M28 | ||
| 83 | bool | ||
| 84 | select SOC_IMX28 | ||
| 85 | select LEDS_GPIO_REGISTER | ||
| 86 | select MXS_HAVE_AMBA_DUART | ||
| 87 | select MXS_HAVE_PLATFORM_AUART | ||
| 88 | select MXS_HAVE_PLATFORM_FEC | ||
| 89 | select MXS_HAVE_PLATFORM_FLEXCAN | ||
| 90 | select MXS_HAVE_PLATFORM_MXS_I2C | ||
| 91 | select MXS_HAVE_PLATFORM_MXS_MMC | ||
| 92 | select MXS_HAVE_PLATFORM_MXSFB | ||
| 93 | |||
| 94 | config MODULE_APX4 | ||
| 95 | bool | ||
| 96 | select SOC_IMX28 | ||
| 97 | select LEDS_GPIO_REGISTER | ||
| 98 | select MXS_HAVE_AMBA_DUART | ||
| 99 | select MXS_HAVE_PLATFORM_AUART | ||
| 100 | select MXS_HAVE_PLATFORM_FEC | ||
| 101 | select MXS_HAVE_PLATFORM_MXS_I2C | ||
| 102 | select MXS_HAVE_PLATFORM_MXS_MMC | ||
| 103 | select MXS_HAVE_PLATFORM_MXS_SAIF | ||
| 104 | |||
| 105 | config MACH_TX28 | ||
| 106 | bool "Ka-Ro TX28 module" | ||
| 107 | select MODULE_TX28 | ||
| 108 | |||
| 109 | config MACH_M28EVK | ||
| 110 | bool "Support DENX M28EVK Platform" | ||
| 111 | select MODULE_M28 | ||
| 112 | |||
| 113 | config MACH_APX4DEVKIT | ||
| 114 | bool "Support Bluegiga APX4 Development Kit" | ||
| 115 | select MODULE_APX4 | ||
| 116 | |||
| 117 | endif | 28 | endif |
diff --git a/arch/arm/mach-mxs/Makefile b/arch/arm/mach-mxs/Makefile index fed3695a1339..3d3c8a973062 100644 --- a/arch/arm/mach-mxs/Makefile +++ b/arch/arm/mach-mxs/Makefile | |||
| @@ -1,15 +1,6 @@ | |||
| 1 | # Common support | 1 | # Common support |
| 2 | obj-y := devices.o icoll.o iomux.o ocotp.o system.o timer.o mm.o | 2 | obj-y := icoll.o ocotp.o system.o timer.o mm.o |
| 3 | 3 | ||
| 4 | obj-$(CONFIG_PM) += pm.o | 4 | obj-$(CONFIG_PM) += pm.o |
| 5 | 5 | ||
| 6 | obj-$(CONFIG_MACH_MXS_DT) += mach-mxs.o | 6 | obj-$(CONFIG_MACH_MXS_DT) += mach-mxs.o |
| 7 | obj-$(CONFIG_MACH_STMP378X_DEVB) += mach-stmp378x_devb.o | ||
| 8 | obj-$(CONFIG_MACH_MX23EVK) += mach-mx23evk.o | ||
| 9 | obj-$(CONFIG_MACH_MX28EVK) += mach-mx28evk.o | ||
| 10 | obj-$(CONFIG_MACH_M28EVK) += mach-m28evk.o | ||
| 11 | obj-$(CONFIG_MACH_APX4DEVKIT) += mach-apx4devkit.o | ||
| 12 | obj-$(CONFIG_MODULE_TX28) += module-tx28.o | ||
| 13 | obj-$(CONFIG_MACH_TX28) += mach-tx28.o | ||
| 14 | |||
| 15 | obj-y += devices/ | ||
diff --git a/arch/arm/mach-mxs/Makefile.boot b/arch/arm/mach-mxs/Makefile.boot index 4582999cf080..8bd23a8558db 100644 --- a/arch/arm/mach-mxs/Makefile.boot +++ b/arch/arm/mach-mxs/Makefile.boot | |||
| @@ -5,6 +5,7 @@ dtb-y += imx23-evk.dtb \ | |||
| 5 | imx23-stmp378x_devb.dtb \ | 5 | imx23-stmp378x_devb.dtb \ |
| 6 | imx28-apx4devkit.dtb \ | 6 | imx28-apx4devkit.dtb \ |
| 7 | imx28-cfa10036.dtb \ | 7 | imx28-cfa10036.dtb \ |
| 8 | imx28-cfa10049.dtb \ | ||
| 8 | imx28-evk.dtb \ | 9 | imx28-evk.dtb \ |
| 9 | imx28-m28evk.dtb \ | 10 | imx28-m28evk.dtb \ |
| 10 | imx28-tx28.dtb \ | 11 | imx28-tx28.dtb \ |
diff --git a/arch/arm/mach-mxs/devices-mx23.h b/arch/arm/mach-mxs/devices-mx23.h deleted file mode 100644 index 9ee5cede3d42..000000000000 --- a/arch/arm/mach-mxs/devices-mx23.h +++ /dev/null | |||
| @@ -1,43 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2010 Pengutronix | ||
| 3 | * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> | ||
| 4 | * | ||
| 5 | * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify it under | ||
| 8 | * the terms of the GNU General Public License version 2 as published by the | ||
| 9 | * Free Software Foundation. | ||
| 10 | */ | ||
| 11 | #include <mach/mx23.h> | ||
| 12 | #include <mach/devices-common.h> | ||
| 13 | #include <linux/mxsfb.h> | ||
| 14 | #include <linux/amba/bus.h> | ||
| 15 | |||
| 16 | static inline int mx23_add_duart(void) | ||
| 17 | { | ||
| 18 | struct amba_device *d; | ||
| 19 | |||
| 20 | d = amba_ahb_device_add(NULL, "duart", MX23_DUART_BASE_ADDR, SZ_8K, | ||
| 21 | MX23_INT_DUART, 0, 0, 0); | ||
| 22 | return IS_ERR(d) ? PTR_ERR(d) : 0; | ||
| 23 | } | ||
| 24 | |||
| 25 | extern const struct mxs_auart_data mx23_auart_data[] __initconst; | ||
| 26 | #define mx23_add_auart(id) mxs_add_auart(&mx23_auart_data[id]) | ||
| 27 | #define mx23_add_auart0() mx23_add_auart(0) | ||
| 28 | #define mx23_add_auart1() mx23_add_auart(1) | ||
| 29 | |||
| 30 | extern const struct mxs_gpmi_nand_data mx23_gpmi_nand_data __initconst; | ||
| 31 | #define mx23_add_gpmi_nand(pdata) \ | ||
| 32 | mxs_add_gpmi_nand(pdata, &mx23_gpmi_nand_data) | ||
| 33 | |||
| 34 | extern const struct mxs_mxs_mmc_data mx23_mxs_mmc_data[] __initconst; | ||
| 35 | #define mx23_add_mxs_mmc(id, pdata) \ | ||
| 36 | mxs_add_mxs_mmc(&mx23_mxs_mmc_data[id], pdata) | ||
| 37 | |||
| 38 | #define mx23_add_mxs_pwm(id) mxs_add_mxs_pwm(MX23_PWM_BASE_ADDR, id) | ||
| 39 | |||
| 40 | struct platform_device *__init mx23_add_mxsfb( | ||
| 41 | const struct mxsfb_platform_data *pdata); | ||
| 42 | |||
| 43 | struct platform_device *__init mx23_add_rtc_stmp3xxx(void); | ||
diff --git a/arch/arm/mach-mxs/devices-mx28.h b/arch/arm/mach-mxs/devices-mx28.h deleted file mode 100644 index fcab431060f4..000000000000 --- a/arch/arm/mach-mxs/devices-mx28.h +++ /dev/null | |||
| @@ -1,63 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2010 Pengutronix | ||
| 3 | * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> | ||
| 4 | * | ||
| 5 | * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify it under | ||
| 8 | * the terms of the GNU General Public License version 2 as published by the | ||
| 9 | * Free Software Foundation. | ||
| 10 | */ | ||
| 11 | #include <mach/mx28.h> | ||
| 12 | #include <mach/devices-common.h> | ||
| 13 | #include <linux/mxsfb.h> | ||
| 14 | #include <linux/amba/bus.h> | ||
| 15 | |||
| 16 | static inline int mx28_add_duart(void) | ||
| 17 | { | ||
| 18 | struct amba_device *d; | ||
| 19 | |||
| 20 | d = amba_ahb_device_add(NULL, "duart", MX28_DUART_BASE_ADDR, SZ_8K, | ||
| 21 | MX28_INT_DUART, 0, 0, 0); | ||
| 22 | return IS_ERR(d) ? PTR_ERR(d) : 0; | ||
| 23 | } | ||
| 24 | |||
| 25 | extern const struct mxs_auart_data mx28_auart_data[] __initconst; | ||
| 26 | #define mx28_add_auart(id) mxs_add_auart(&mx28_auart_data[id]) | ||
| 27 | #define mx28_add_auart0() mx28_add_auart(0) | ||
| 28 | #define mx28_add_auart1() mx28_add_auart(1) | ||
| 29 | #define mx28_add_auart2() mx28_add_auart(2) | ||
| 30 | #define mx28_add_auart3() mx28_add_auart(3) | ||
| 31 | #define mx28_add_auart4() mx28_add_auart(4) | ||
| 32 | |||
| 33 | extern const struct mxs_fec_data mx28_fec_data[] __initconst; | ||
| 34 | #define mx28_add_fec(id, pdata) \ | ||
| 35 | mxs_add_fec(&mx28_fec_data[id], pdata) | ||
| 36 | |||
| 37 | extern const struct mxs_flexcan_data mx28_flexcan_data[] __initconst; | ||
| 38 | #define mx28_add_flexcan(id, pdata) \ | ||
| 39 | mxs_add_flexcan(&mx28_flexcan_data[id], pdata) | ||
| 40 | #define mx28_add_flexcan0(pdata) mx28_add_flexcan(0, pdata) | ||
| 41 | #define mx28_add_flexcan1(pdata) mx28_add_flexcan(1, pdata) | ||
| 42 | |||
| 43 | extern const struct mxs_gpmi_nand_data mx28_gpmi_nand_data __initconst; | ||
| 44 | #define mx28_add_gpmi_nand(pdata) \ | ||
| 45 | mxs_add_gpmi_nand(pdata, &mx28_gpmi_nand_data) | ||
| 46 | |||
| 47 | extern const struct mxs_mxs_i2c_data mx28_mxs_i2c_data[] __initconst; | ||
| 48 | #define mx28_add_mxs_i2c(id) mxs_add_mxs_i2c(&mx28_mxs_i2c_data[id]) | ||
| 49 | |||
| 50 | extern const struct mxs_mxs_mmc_data mx28_mxs_mmc_data[] __initconst; | ||
| 51 | #define mx28_add_mxs_mmc(id, pdata) \ | ||
| 52 | mxs_add_mxs_mmc(&mx28_mxs_mmc_data[id], pdata) | ||
| 53 | |||
| 54 | #define mx28_add_mxs_pwm(id) mxs_add_mxs_pwm(MX28_PWM_BASE_ADDR, id) | ||
| 55 | |||
| 56 | struct platform_device *__init mx28_add_mxsfb( | ||
| 57 | const struct mxsfb_platform_data *pdata); | ||
| 58 | |||
| 59 | extern const struct mxs_saif_data mx28_saif_data[] __initconst; | ||
| 60 | #define mx28_add_saif(id, pdata) \ | ||
| 61 | mxs_add_saif(&mx28_saif_data[id], pdata) | ||
| 62 | |||
| 63 | struct platform_device *__init mx28_add_rtc_stmp3xxx(void); | ||
diff --git a/arch/arm/mach-mxs/devices.c b/arch/arm/mach-mxs/devices.c deleted file mode 100644 index cf50b5a66dda..000000000000 --- a/arch/arm/mach-mxs/devices.c +++ /dev/null | |||
| @@ -1,87 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2008 Sascha Hauer, kernel@pengutronix.de | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or | ||
| 5 | * modify it under the terms of the GNU General Public License | ||
| 6 | * as published by the Free Software Foundation; either version 2 | ||
| 7 | * of the License, or (at your option) any later version. | ||
| 8 | * This program is distributed in the hope that it will be useful, | ||
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 11 | * GNU General Public License for more details. | ||
| 12 | * | ||
| 13 | * You should have received a copy of the GNU General Public License | ||
| 14 | * along with this program; if not, write to the Free Software | ||
| 15 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, | ||
| 16 | * Boston, MA 02110-1301, USA. | ||
| 17 | */ | ||
| 18 | |||
| 19 | #include <linux/kernel.h> | ||
| 20 | #include <linux/slab.h> | ||
| 21 | #include <linux/init.h> | ||
| 22 | #include <linux/platform_device.h> | ||
| 23 | #include <linux/amba/bus.h> | ||
| 24 | |||
| 25 | struct platform_device *__init mxs_add_platform_device_dmamask( | ||
| 26 | const char *name, int id, | ||
| 27 | const struct resource *res, unsigned int num_resources, | ||
| 28 | const void *data, size_t size_data, u64 dmamask) | ||
| 29 | { | ||
| 30 | int ret = -ENOMEM; | ||
| 31 | struct platform_device *pdev; | ||
| 32 | |||
| 33 | pdev = platform_device_alloc(name, id); | ||
| 34 | if (!pdev) | ||
| 35 | goto err; | ||
| 36 | |||
| 37 | if (dmamask) { | ||
| 38 | /* | ||
| 39 | * This memory isn't freed when the device is put, | ||
| 40 | * I don't have a nice idea for that though. Conceptually | ||
| 41 | * dma_mask in struct device should not be a pointer. | ||
| 42 | * See http://thread.gmane.org/gmane.linux.kernel.pci/9081 | ||
| 43 | */ | ||
| 44 | pdev->dev.dma_mask = | ||
| 45 | kmalloc(sizeof(*pdev->dev.dma_mask), GFP_KERNEL); | ||
| 46 | if (!pdev->dev.dma_mask) | ||
| 47 | /* ret is still -ENOMEM; */ | ||
| 48 | goto err; | ||
| 49 | |||
| 50 | *pdev->dev.dma_mask = dmamask; | ||
| 51 | pdev->dev.coherent_dma_mask = dmamask; | ||
| 52 | } | ||
| 53 | |||
| 54 | if (res) { | ||
| 55 | ret = platform_device_add_resources(pdev, res, num_resources); | ||
| 56 | if (ret) | ||
| 57 | goto err; | ||
| 58 | } | ||
| 59 | |||
| 60 | if (data) { | ||
| 61 | ret = platform_device_add_data(pdev, data, size_data); | ||
| 62 | if (ret) | ||
| 63 | goto err; | ||
| 64 | } | ||
| 65 | |||
| 66 | ret = platform_device_add(pdev); | ||
| 67 | if (ret) { | ||
| 68 | err: | ||
| 69 | if (dmamask) | ||
| 70 | kfree(pdev->dev.dma_mask); | ||
| 71 | platform_device_put(pdev); | ||
| 72 | return ERR_PTR(ret); | ||
| 73 | } | ||
| 74 | |||
| 75 | return pdev; | ||
| 76 | } | ||
| 77 | |||
| 78 | struct device mxs_apbh_bus = { | ||
| 79 | .init_name = "mxs_apbh", | ||
| 80 | .parent = &platform_bus, | ||
| 81 | }; | ||
| 82 | |||
| 83 | static int __init mxs_device_init(void) | ||
| 84 | { | ||
| 85 | return device_register(&mxs_apbh_bus); | ||
| 86 | } | ||
| 87 | core_initcall(mxs_device_init); | ||
diff --git a/arch/arm/mach-mxs/devices/Kconfig b/arch/arm/mach-mxs/devices/Kconfig deleted file mode 100644 index 19659de1c4e8..000000000000 --- a/arch/arm/mach-mxs/devices/Kconfig +++ /dev/null | |||
| @@ -1,33 +0,0 @@ | |||
| 1 | config MXS_HAVE_AMBA_DUART | ||
| 2 | bool | ||
| 3 | |||
| 4 | config MXS_HAVE_PLATFORM_AUART | ||
| 5 | bool | ||
| 6 | |||
| 7 | config MXS_HAVE_PLATFORM_FEC | ||
| 8 | bool | ||
| 9 | |||
| 10 | config MXS_HAVE_PLATFORM_FLEXCAN | ||
| 11 | select HAVE_CAN_FLEXCAN if CAN | ||
| 12 | bool | ||
| 13 | |||
| 14 | config MXS_HAVE_PLATFORM_GPMI_NAND | ||
| 15 | bool | ||
| 16 | |||
| 17 | config MXS_HAVE_PLATFORM_MXS_I2C | ||
| 18 | bool | ||
| 19 | |||
| 20 | config MXS_HAVE_PLATFORM_MXS_MMC | ||
| 21 | bool | ||
| 22 | |||
| 23 | config MXS_HAVE_PLATFORM_MXS_PWM | ||
| 24 | bool | ||
| 25 | |||
| 26 | config MXS_HAVE_PLATFORM_MXSFB | ||
| 27 | bool | ||
| 28 | |||
| 29 | config MXS_HAVE_PLATFORM_MXS_SAIF | ||
| 30 | bool | ||
| 31 | |||
| 32 | config MXS_HAVE_PLATFORM_RTC_STMP3XXX | ||
| 33 | bool | ||
diff --git a/arch/arm/mach-mxs/devices/Makefile b/arch/arm/mach-mxs/devices/Makefile deleted file mode 100644 index 5f72d9787444..000000000000 --- a/arch/arm/mach-mxs/devices/Makefile +++ /dev/null | |||
| @@ -1,12 +0,0 @@ | |||
| 1 | obj-$(CONFIG_MXS_HAVE_PLATFORM_AUART) += platform-auart.o | ||
| 2 | obj-y += platform-dma.o | ||
| 3 | obj-$(CONFIG_MXS_HAVE_PLATFORM_FEC) += platform-fec.o | ||
| 4 | obj-$(CONFIG_MXS_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o | ||
| 5 | obj-$(CONFIG_MXS_HAVE_PLATFORM_GPMI_NAND) += platform-gpmi-nand.o | ||
| 6 | obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_I2C) += platform-mxs-i2c.o | ||
| 7 | obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_MMC) += platform-mxs-mmc.o | ||
| 8 | obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_PWM) += platform-mxs-pwm.o | ||
| 9 | obj-y += platform-gpio-mxs.o | ||
| 10 | obj-$(CONFIG_MXS_HAVE_PLATFORM_MXSFB) += platform-mxsfb.o | ||
| 11 | obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_SAIF) += platform-mxs-saif.o | ||
| 12 | obj-$(CONFIG_MXS_HAVE_PLATFORM_RTC_STMP3XXX) += platform-rtc-stmp3xxx.o | ||
diff --git a/arch/arm/mach-mxs/devices/platform-auart.c b/arch/arm/mach-mxs/devices/platform-auart.c deleted file mode 100644 index 27608f5d2ac8..000000000000 --- a/arch/arm/mach-mxs/devices/platform-auart.c +++ /dev/null | |||
| @@ -1,65 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2010 Pengutronix | ||
| 3 | * Sascha Hauer <s.hauer@pengutronix.de> | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it under | ||
| 6 | * the terms of the GNU General Public License version 2 as published by the | ||
| 7 | * Free Software Foundation. | ||
| 8 | */ | ||
| 9 | #include <linux/dma-mapping.h> | ||
| 10 | #include <asm/sizes.h> | ||
| 11 | #include <mach/mx23.h> | ||
| 12 | #include <mach/mx28.h> | ||
| 13 | #include <mach/devices-common.h> | ||
| 14 | |||
| 15 | #define mxs_auart_data_entry_single(soc, _id, hwid) \ | ||
| 16 | { \ | ||
| 17 | .id = _id, \ | ||
| 18 | .iobase = soc ## _AUART ## hwid ## _BASE_ADDR, \ | ||
| 19 | .irq = soc ## _INT_AUART ## hwid, \ | ||
| 20 | } | ||
| 21 | |||
| 22 | #define mxs_auart_data_entry(soc, _id, hwid) \ | ||
| 23 | [_id] = mxs_auart_data_entry_single(soc, _id, hwid) | ||
| 24 | |||
| 25 | #ifdef CONFIG_SOC_IMX23 | ||
| 26 | const struct mxs_auart_data mx23_auart_data[] __initconst = { | ||
| 27 | #define mx23_auart_data_entry(_id, hwid) \ | ||
| 28 | mxs_auart_data_entry(MX23, _id, hwid) | ||
| 29 | mx23_auart_data_entry(0, 1), | ||
| 30 | mx23_auart_data_entry(1, 2), | ||
| 31 | }; | ||
| 32 | #endif | ||
| 33 | |||
| 34 | #ifdef CONFIG_SOC_IMX28 | ||
| 35 | const struct mxs_auart_data mx28_auart_data[] __initconst = { | ||
| 36 | #define mx28_auart_data_entry(_id) \ | ||
| 37 | mxs_auart_data_entry(MX28, _id, _id) | ||
| 38 | mx28_auart_data_entry(0), | ||
| 39 | mx28_auart_data_entry(1), | ||
| 40 | mx28_auart_data_entry(2), | ||
| 41 | mx28_auart_data_entry(3), | ||
| 42 | mx28_auart_data_entry(4), | ||
| 43 | }; | ||
| 44 | #endif | ||
| 45 | |||
| 46 | struct platform_device *__init mxs_add_auart( | ||
| 47 | const struct mxs_auart_data *data) | ||
| 48 | { | ||
| 49 | struct resource res[] = { | ||
| 50 | { | ||
| 51 | .start = data->iobase, | ||
| 52 | .end = data->iobase + SZ_8K - 1, | ||
| 53 | .flags = IORESOURCE_MEM, | ||
| 54 | }, { | ||
| 55 | .start = data->irq, | ||
| 56 | .end = data->irq, | ||
| 57 | .flags = IORESOURCE_IRQ, | ||
| 58 | }, | ||
| 59 | }; | ||
| 60 | |||
| 61 | return mxs_add_platform_device_dmamask("mxs-auart", data->id, | ||
| 62 | res, ARRAY_SIZE(res), NULL, 0, | ||
| 63 | DMA_BIT_MASK(32)); | ||
| 64 | } | ||
| 65 | |||
diff --git a/arch/arm/mach-mxs/devices/platform-dma.c b/arch/arm/mach-mxs/devices/platform-dma.c deleted file mode 100644 index 46824501de00..000000000000 --- a/arch/arm/mach-mxs/devices/platform-dma.c +++ /dev/null | |||
| @@ -1,31 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify it under | ||
| 5 | * the terms of the GNU General Public License version 2 as published by the | ||
| 6 | * Free Software Foundation. | ||
| 7 | */ | ||
| 8 | #include <linux/compiler.h> | ||
| 9 | #include <linux/dma-mapping.h> | ||
| 10 | #include <linux/err.h> | ||
| 11 | #include <linux/init.h> | ||
| 12 | |||
| 13 | #include <mach/mx23.h> | ||
| 14 | #include <mach/mx28.h> | ||
| 15 | #include <mach/devices-common.h> | ||
| 16 | |||
| 17 | struct platform_device *__init mxs_add_dma(const char *devid, | ||
| 18 | resource_size_t base) | ||
| 19 | { | ||
| 20 | struct resource res[] = { | ||
| 21 | { | ||
| 22 | .start = base, | ||
| 23 | .end = base + SZ_8K - 1, | ||
| 24 | .flags = IORESOURCE_MEM, | ||
| 25 | } | ||
| 26 | }; | ||
| 27 | |||
| 28 | return mxs_add_platform_device_dmamask(devid, -1, | ||
| 29 | res, ARRAY_SIZE(res), NULL, 0, | ||
| 30 | DMA_BIT_MASK(32)); | ||
| 31 | } | ||
diff --git a/arch/arm/mach-mxs/devices/platform-fec.c b/arch/arm/mach-mxs/devices/platform-fec.c deleted file mode 100644 index ae96a4fd8f14..000000000000 --- a/arch/arm/mach-mxs/devices/platform-fec.c +++ /dev/null | |||
| @@ -1,52 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2010 Pengutronix | ||
| 3 | * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it under | ||
| 6 | * the terms of the GNU General Public License version 2 as published by the | ||
| 7 | * Free Software Foundation. | ||
| 8 | */ | ||
| 9 | #include <linux/dma-mapping.h> | ||
| 10 | #include <asm/sizes.h> | ||
| 11 | #include <mach/mx28.h> | ||
| 12 | #include <mach/devices-common.h> | ||
| 13 | |||
| 14 | #define mxs_fec_data_entry_single(soc, _id) \ | ||
| 15 | { \ | ||
| 16 | .id = _id, \ | ||
| 17 | .iobase = soc ## _ENET_MAC ## _id ## _BASE_ADDR, \ | ||
| 18 | .irq = soc ## _INT_ENET_MAC ## _id, \ | ||
| 19 | } | ||
| 20 | |||
| 21 | #define mxs_fec_data_entry(soc, _id) \ | ||
| 22 | [_id] = mxs_fec_data_entry_single(soc, _id) | ||
| 23 | |||
| 24 | #ifdef CONFIG_SOC_IMX28 | ||
| 25 | const struct mxs_fec_data mx28_fec_data[] __initconst = { | ||
| 26 | #define mx28_fec_data_entry(_id) \ | ||
| 27 | mxs_fec_data_entry(MX28, _id) | ||
| 28 | mx28_fec_data_entry(0), | ||
| 29 | mx28_fec_data_entry(1), | ||
| 30 | }; | ||
| 31 | #endif | ||
| 32 | |||
| 33 | struct platform_device *__init mxs_add_fec( | ||
| 34 | const struct mxs_fec_data *data, | ||
| 35 | const struct fec_platform_data *pdata) | ||
| 36 | { | ||
| 37 | struct resource res[] = { | ||
| 38 | { | ||
| 39 | .start = data->iobase, | ||
| 40 | .end = data->iobase + SZ_16K - 1, | ||
| 41 | .flags = IORESOURCE_MEM, | ||
| 42 | }, { | ||
| 43 | .start = data->irq, | ||
| 44 | .end = data->irq, | ||
| 45 | .flags = IORESOURCE_IRQ, | ||
| 46 | }, | ||
| 47 | }; | ||
| 48 | |||
| 49 | return mxs_add_platform_device_dmamask("imx28-fec", data->id, | ||
| 50 | res, ARRAY_SIZE(res), pdata, sizeof(*pdata), | ||
| 51 | DMA_BIT_MASK(32)); | ||
| 52 | } | ||
diff --git a/arch/arm/mach-mxs/devices/platform-flexcan.c b/arch/arm/mach-mxs/devices/platform-flexcan.c deleted file mode 100644 index 43a6b4bae6fe..000000000000 --- a/arch/arm/mach-mxs/devices/platform-flexcan.c +++ /dev/null | |||
| @@ -1,51 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2010, 2011 Pengutronix, | ||
| 3 | * Marc Kleine-Budde <kernel@pengutronix.de> | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it under | ||
| 6 | * the terms of the GNU General Public License version 2 as published by the | ||
| 7 | * Free Software Foundation. | ||
| 8 | */ | ||
| 9 | #include <asm/sizes.h> | ||
| 10 | #include <mach/mx28.h> | ||
| 11 | #include <mach/devices-common.h> | ||
| 12 | |||
| 13 | #define mxs_flexcan_data_entry_single(soc, _id, _hwid, _size) \ | ||
| 14 | { \ | ||
| 15 | .id = _id, \ | ||
| 16 | .iobase = soc ## _CAN ## _hwid ## _BASE_ADDR, \ | ||
| 17 | .iosize = _size, \ | ||
| 18 | .irq = soc ## _INT_CAN ## _hwid, \ | ||
| 19 | } | ||
| 20 | |||
| 21 | #define mxs_flexcan_data_entry(soc, _id, _hwid, _size) \ | ||
| 22 | [_id] = mxs_flexcan_data_entry_single(soc, _id, _hwid, _size) | ||
| 23 | |||
| 24 | #ifdef CONFIG_SOC_IMX28 | ||
| 25 | const struct mxs_flexcan_data mx28_flexcan_data[] __initconst = { | ||
| 26 | #define mx28_flexcan_data_entry(_id, _hwid) \ | ||
| 27 | mxs_flexcan_data_entry_single(MX28, _id, _hwid, SZ_8K) | ||
| 28 | mx28_flexcan_data_entry(0, 0), | ||
| 29 | mx28_flexcan_data_entry(1, 1), | ||
| 30 | }; | ||
| 31 | #endif /* ifdef CONFIG_SOC_IMX28 */ | ||
| 32 | |||
| 33 | struct platform_device *__init mxs_add_flexcan( | ||
| 34 | const struct mxs_flexcan_data *data, | ||
| 35 | const struct flexcan_platform_data *pdata) | ||
| 36 | { | ||
| 37 | struct resource res[] = { | ||
| 38 | { | ||
| 39 | .start = data->iobase, | ||
| 40 | .end = data->iobase + data->iosize - 1, | ||
| 41 | .flags = IORESOURCE_MEM, | ||
| 42 | }, { | ||
| 43 | .start = data->irq, | ||
| 44 | .end = data->irq, | ||
| 45 | .flags = IORESOURCE_IRQ, | ||
| 46 | }, | ||
| 47 | }; | ||
| 48 | |||
| 49 | return mxs_add_platform_device("flexcan", data->id, | ||
| 50 | res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); | ||
| 51 | } | ||
diff --git a/arch/arm/mach-mxs/devices/platform-gpio-mxs.c b/arch/arm/mach-mxs/devices/platform-gpio-mxs.c deleted file mode 100644 index cd99f19ec637..000000000000 --- a/arch/arm/mach-mxs/devices/platform-gpio-mxs.c +++ /dev/null | |||
| @@ -1,33 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify it under | ||
| 5 | * the terms of the GNU General Public License version 2 as published by the | ||
| 6 | * Free Software Foundation. | ||
| 7 | */ | ||
| 8 | #include <linux/compiler.h> | ||
| 9 | #include <linux/err.h> | ||
| 10 | #include <linux/init.h> | ||
| 11 | |||
| 12 | #include <mach/mx23.h> | ||
| 13 | #include <mach/mx28.h> | ||
| 14 | #include <mach/devices-common.h> | ||
| 15 | |||
| 16 | struct platform_device *__init mxs_add_gpio( | ||
| 17 | char *name, int id, resource_size_t iobase, int irq) | ||
| 18 | { | ||
| 19 | struct resource res[] = { | ||
| 20 | { | ||
| 21 | .start = iobase, | ||
| 22 | .end = iobase + SZ_8K - 1, | ||
| 23 | .flags = IORESOURCE_MEM, | ||
| 24 | }, { | ||
| 25 | .start = irq, | ||
| 26 | .end = irq, | ||
| 27 | .flags = IORESOURCE_IRQ, | ||
| 28 | }, | ||
| 29 | }; | ||
| 30 | |||
| 31 | return platform_device_register_resndata(&mxs_apbh_bus, | ||
| 32 | name, id, res, ARRAY_SIZE(res), NULL, 0); | ||
| 33 | } | ||
diff --git a/arch/arm/mach-mxs/devices/platform-gpmi-nand.c b/arch/arm/mach-mxs/devices/platform-gpmi-nand.c deleted file mode 100644 index 3e22df5944a8..000000000000 --- a/arch/arm/mach-mxs/devices/platform-gpmi-nand.c +++ /dev/null | |||
| @@ -1,81 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License as published by | ||
| 6 | * the Free Software Foundation; either version 2 of the License, or | ||
| 7 | * (at your option) any later version. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | * | ||
| 14 | * You should have received a copy of the GNU General Public License along | ||
| 15 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 16 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. | ||
| 17 | */ | ||
| 18 | #include <asm/sizes.h> | ||
| 19 | #include <mach/mx23.h> | ||
| 20 | #include <mach/mx28.h> | ||
| 21 | #include <mach/devices-common.h> | ||
| 22 | #include <linux/dma-mapping.h> | ||
| 23 | |||
| 24 | #ifdef CONFIG_SOC_IMX23 | ||
| 25 | const struct mxs_gpmi_nand_data mx23_gpmi_nand_data __initconst = { | ||
| 26 | .devid = "imx23-gpmi-nand", | ||
| 27 | .res = { | ||
| 28 | /* GPMI */ | ||
| 29 | DEFINE_RES_MEM_NAMED(MX23_GPMI_BASE_ADDR, SZ_8K, | ||
| 30 | GPMI_NAND_GPMI_REGS_ADDR_RES_NAME), | ||
| 31 | DEFINE_RES_IRQ_NAMED(MX23_INT_GPMI_ATTENTION, | ||
| 32 | GPMI_NAND_GPMI_INTERRUPT_RES_NAME), | ||
| 33 | /* BCH */ | ||
| 34 | DEFINE_RES_MEM_NAMED(MX23_BCH_BASE_ADDR, SZ_8K, | ||
| 35 | GPMI_NAND_BCH_REGS_ADDR_RES_NAME), | ||
| 36 | DEFINE_RES_IRQ_NAMED(MX23_INT_BCH, | ||
| 37 | GPMI_NAND_BCH_INTERRUPT_RES_NAME), | ||
| 38 | /* DMA */ | ||
| 39 | DEFINE_RES_NAMED(MX23_DMA_GPMI0, | ||
| 40 | MX23_DMA_GPMI3 - MX23_DMA_GPMI0 + 1, | ||
| 41 | GPMI_NAND_DMA_CHANNELS_RES_NAME, | ||
| 42 | IORESOURCE_DMA), | ||
| 43 | DEFINE_RES_IRQ_NAMED(MX23_INT_GPMI_DMA, | ||
| 44 | GPMI_NAND_DMA_INTERRUPT_RES_NAME), | ||
| 45 | }, | ||
| 46 | }; | ||
| 47 | #endif | ||
| 48 | |||
| 49 | #ifdef CONFIG_SOC_IMX28 | ||
| 50 | const struct mxs_gpmi_nand_data mx28_gpmi_nand_data __initconst = { | ||
| 51 | .devid = "imx28-gpmi-nand", | ||
| 52 | .res = { | ||
| 53 | /* GPMI */ | ||
| 54 | DEFINE_RES_MEM_NAMED(MX28_GPMI_BASE_ADDR, SZ_8K, | ||
| 55 | GPMI_NAND_GPMI_REGS_ADDR_RES_NAME), | ||
| 56 | DEFINE_RES_IRQ_NAMED(MX28_INT_GPMI, | ||
| 57 | GPMI_NAND_GPMI_INTERRUPT_RES_NAME), | ||
| 58 | /* BCH */ | ||
| 59 | DEFINE_RES_MEM_NAMED(MX28_BCH_BASE_ADDR, SZ_8K, | ||
| 60 | GPMI_NAND_BCH_REGS_ADDR_RES_NAME), | ||
| 61 | DEFINE_RES_IRQ_NAMED(MX28_INT_BCH, | ||
| 62 | GPMI_NAND_BCH_INTERRUPT_RES_NAME), | ||
| 63 | /* DMA */ | ||
| 64 | DEFINE_RES_NAMED(MX28_DMA_GPMI0, | ||
| 65 | MX28_DMA_GPMI7 - MX28_DMA_GPMI0 + 1, | ||
| 66 | GPMI_NAND_DMA_CHANNELS_RES_NAME, | ||
| 67 | IORESOURCE_DMA), | ||
| 68 | DEFINE_RES_IRQ_NAMED(MX28_INT_GPMI_DMA, | ||
| 69 | GPMI_NAND_DMA_INTERRUPT_RES_NAME), | ||
| 70 | }, | ||
| 71 | }; | ||
| 72 | #endif | ||
| 73 | |||
| 74 | struct platform_device *__init | ||
| 75 | mxs_add_gpmi_nand(const struct gpmi_nand_platform_data *pdata, | ||
| 76 | const struct mxs_gpmi_nand_data *data) | ||
| 77 | { | ||
| 78 | return mxs_add_platform_device_dmamask(data->devid, -1, | ||
| 79 | data->res, GPMI_NAND_RES_SIZE, | ||
| 80 | pdata, sizeof(*pdata), DMA_BIT_MASK(32)); | ||
| 81 | } | ||
diff --git a/arch/arm/mach-mxs/devices/platform-mxs-i2c.c b/arch/arm/mach-mxs/devices/platform-mxs-i2c.c deleted file mode 100644 index 79222ec8ede1..000000000000 --- a/arch/arm/mach-mxs/devices/platform-mxs-i2c.c +++ /dev/null | |||
| @@ -1,52 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2011 Pengutronix | ||
| 3 | * Wolfram Sang <w.sang@pengutronix.de> | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it under | ||
| 6 | * the terms of the GNU General Public License version 2 as published by the | ||
| 7 | * Free Software Foundation. | ||
| 8 | */ | ||
| 9 | #include <asm/sizes.h> | ||
| 10 | #include <mach/mx28.h> | ||
| 11 | #include <mach/devices-common.h> | ||
| 12 | |||
| 13 | #define mxs_i2c_data_entry_single(soc, _id) \ | ||
| 14 | { \ | ||
| 15 | .id = _id, \ | ||
| 16 | .iobase = soc ## _I2C ## _id ## _BASE_ADDR, \ | ||
| 17 | .errirq = soc ## _INT_I2C ## _id ## _ERROR, \ | ||
| 18 | .dmairq = soc ## _INT_I2C ## _id ## _DMA, \ | ||
| 19 | } | ||
| 20 | |||
| 21 | #define mxs_i2c_data_entry(soc, _id) \ | ||
| 22 | [_id] = mxs_i2c_data_entry_single(soc, _id) | ||
| 23 | |||
| 24 | #ifdef CONFIG_SOC_IMX28 | ||
| 25 | const struct mxs_mxs_i2c_data mx28_mxs_i2c_data[] __initconst = { | ||
| 26 | mxs_i2c_data_entry(MX28, 0), | ||
| 27 | mxs_i2c_data_entry(MX28, 1), | ||
| 28 | }; | ||
| 29 | #endif | ||
| 30 | |||
| 31 | struct platform_device *__init mxs_add_mxs_i2c( | ||
| 32 | const struct mxs_mxs_i2c_data *data) | ||
| 33 | { | ||
| 34 | struct resource res[] = { | ||
| 35 | { | ||
| 36 | .start = data->iobase, | ||
| 37 | .end = data->iobase + SZ_8K - 1, | ||
| 38 | .flags = IORESOURCE_MEM, | ||
| 39 | }, { | ||
| 40 | .start = data->errirq, | ||
| 41 | .end = data->errirq, | ||
| 42 | .flags = IORESOURCE_IRQ, | ||
| 43 | }, { | ||
| 44 | .start = data->dmairq, | ||
| 45 | .end = data->dmairq, | ||
| 46 | .flags = IORESOURCE_IRQ, | ||
| 47 | }, | ||
| 48 | }; | ||
| 49 | |||
| 50 | return mxs_add_platform_device("mxs-i2c", data->id, res, | ||
| 51 | ARRAY_SIZE(res), NULL, 0); | ||
| 52 | } | ||
diff --git a/arch/arm/mach-mxs/devices/platform-mxs-mmc.c b/arch/arm/mach-mxs/devices/platform-mxs-mmc.c deleted file mode 100644 index b33c9d05c552..000000000000 --- a/arch/arm/mach-mxs/devices/platform-mxs-mmc.c +++ /dev/null | |||
| @@ -1,76 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2010 Pengutronix | ||
| 3 | * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> | ||
| 4 | * | ||
| 5 | * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify it under | ||
| 8 | * the terms of the GNU General Public License version 2 as published by the | ||
| 9 | * Free Software Foundation. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #include <linux/compiler.h> | ||
| 13 | #include <linux/err.h> | ||
| 14 | #include <linux/init.h> | ||
| 15 | |||
| 16 | #include <mach/mx23.h> | ||
| 17 | #include <mach/mx28.h> | ||
| 18 | #include <mach/devices-common.h> | ||
| 19 | |||
| 20 | #define mxs_mxs_mmc_data_entry_single(soc, _devid, _id, hwid) \ | ||
| 21 | { \ | ||
| 22 | .devid = _devid, \ | ||
| 23 | .id = _id, \ | ||
| 24 | .iobase = soc ## _SSP ## hwid ## _BASE_ADDR, \ | ||
| 25 | .dma = soc ## _DMA_SSP ## hwid, \ | ||
| 26 | .irq_err = soc ## _INT_SSP ## hwid ## _ERROR, \ | ||
| 27 | .irq_dma = soc ## _INT_SSP ## hwid ## _DMA, \ | ||
| 28 | } | ||
| 29 | |||
| 30 | #define mxs_mxs_mmc_data_entry(soc, _devid, _id, hwid) \ | ||
| 31 | [_id] = mxs_mxs_mmc_data_entry_single(soc, _devid, _id, hwid) | ||
| 32 | |||
| 33 | |||
| 34 | #ifdef CONFIG_SOC_IMX23 | ||
| 35 | const struct mxs_mxs_mmc_data mx23_mxs_mmc_data[] __initconst = { | ||
| 36 | mxs_mxs_mmc_data_entry(MX23, "imx23-mmc", 0, 1), | ||
| 37 | mxs_mxs_mmc_data_entry(MX23, "imx23-mmc", 1, 2), | ||
| 38 | }; | ||
| 39 | #endif | ||
| 40 | |||
| 41 | #ifdef CONFIG_SOC_IMX28 | ||
| 42 | const struct mxs_mxs_mmc_data mx28_mxs_mmc_data[] __initconst = { | ||
| 43 | mxs_mxs_mmc_data_entry(MX28, "imx28-mmc", 0, 0), | ||
| 44 | mxs_mxs_mmc_data_entry(MX28, "imx28-mmc", 1, 1), | ||
| 45 | mxs_mxs_mmc_data_entry(MX28, "imx28-mmc", 2, 2), | ||
| 46 | mxs_mxs_mmc_data_entry(MX28, "imx28-mmc", 3, 3), | ||
| 47 | }; | ||
| 48 | #endif | ||
| 49 | |||
| 50 | struct platform_device *__init mxs_add_mxs_mmc( | ||
| 51 | const struct mxs_mxs_mmc_data *data, | ||
| 52 | const struct mxs_mmc_platform_data *pdata) | ||
| 53 | { | ||
| 54 | struct resource res[] = { | ||
| 55 | { | ||
| 56 | .start = data->iobase, | ||
| 57 | .end = data->iobase + SZ_8K - 1, | ||
| 58 | .flags = IORESOURCE_MEM, | ||
| 59 | }, { | ||
| 60 | .start = data->dma, | ||
| 61 | .end = data->dma, | ||
| 62 | .flags = IORESOURCE_DMA, | ||
| 63 | }, { | ||
| 64 | .start = data->irq_err, | ||
| 65 | .end = data->irq_err, | ||
| 66 | .flags = IORESOURCE_IRQ, | ||
| 67 | }, { | ||
| 68 | .start = data->irq_dma, | ||
| 69 | .end = data->irq_dma, | ||
| 70 | .flags = IORESOURCE_IRQ, | ||
| 71 | }, | ||
| 72 | }; | ||
| 73 | |||
| 74 | return mxs_add_platform_device(data->devid, data->id, | ||
| 75 | res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); | ||
| 76 | } | ||
diff --git a/arch/arm/mach-mxs/devices/platform-mxs-pwm.c b/arch/arm/mach-mxs/devices/platform-mxs-pwm.c deleted file mode 100644 index 680f5a902936..000000000000 --- a/arch/arm/mach-mxs/devices/platform-mxs-pwm.c +++ /dev/null | |||
| @@ -1,22 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2010 Pengutronix | ||
| 3 | * Sascha Hauer <s.hauer@pengutronix.de> | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it under | ||
| 6 | * the terms of the GNU General Public License version 2 as published by the | ||
| 7 | * Free Software Foundation. | ||
| 8 | */ | ||
| 9 | #include <asm/sizes.h> | ||
| 10 | #include <mach/devices-common.h> | ||
| 11 | |||
| 12 | struct platform_device *__init mxs_add_mxs_pwm(resource_size_t iobase, int id) | ||
| 13 | { | ||
| 14 | struct resource res = { | ||
| 15 | .flags = IORESOURCE_MEM, | ||
| 16 | }; | ||
| 17 | |||
| 18 | res.start = iobase + 0x10 + 0x20 * id; | ||
| 19 | res.end = res.start + 0x1f; | ||
| 20 | |||
| 21 | return mxs_add_platform_device("mxs-pwm", id, &res, 1, NULL, 0); | ||
| 22 | } | ||
diff --git a/arch/arm/mach-mxs/devices/platform-mxs-saif.c b/arch/arm/mach-mxs/devices/platform-mxs-saif.c deleted file mode 100644 index f6e3a60b4201..000000000000 --- a/arch/arm/mach-mxs/devices/platform-mxs-saif.c +++ /dev/null | |||
| @@ -1,61 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify it under | ||
| 5 | * the terms of the GNU General Public License version 2 as published by the | ||
| 6 | * Free Software Foundation. | ||
| 7 | */ | ||
| 8 | #include <linux/compiler.h> | ||
| 9 | #include <linux/err.h> | ||
| 10 | #include <linux/init.h> | ||
| 11 | |||
| 12 | #include <mach/mx23.h> | ||
| 13 | #include <mach/mx28.h> | ||
| 14 | #include <mach/devices-common.h> | ||
| 15 | |||
| 16 | #define mxs_saif_data_entry_single(soc, _id) \ | ||
| 17 | { \ | ||
| 18 | .id = _id, \ | ||
| 19 | .iobase = soc ## _SAIF ## _id ## _BASE_ADDR, \ | ||
| 20 | .irq = soc ## _INT_SAIF ## _id, \ | ||
| 21 | .dma = soc ## _DMA_SAIF ## _id, \ | ||
| 22 | .dmairq = soc ## _INT_SAIF ## _id ##_DMA, \ | ||
| 23 | } | ||
| 24 | |||
| 25 | #define mxs_saif_data_entry(soc, _id) \ | ||
| 26 | [_id] = mxs_saif_data_entry_single(soc, _id) | ||
| 27 | |||
| 28 | #ifdef CONFIG_SOC_IMX28 | ||
| 29 | const struct mxs_saif_data mx28_saif_data[] __initconst = { | ||
| 30 | mxs_saif_data_entry(MX28, 0), | ||
| 31 | mxs_saif_data_entry(MX28, 1), | ||
| 32 | }; | ||
| 33 | #endif | ||
| 34 | |||
| 35 | struct platform_device *__init mxs_add_saif(const struct mxs_saif_data *data, | ||
| 36 | const struct mxs_saif_platform_data *pdata) | ||
| 37 | { | ||
| 38 | struct resource res[] = { | ||
| 39 | { | ||
| 40 | .start = data->iobase, | ||
| 41 | .end = data->iobase + SZ_4K - 1, | ||
| 42 | .flags = IORESOURCE_MEM, | ||
| 43 | }, { | ||
| 44 | .start = data->irq, | ||
| 45 | .end = data->irq, | ||
| 46 | .flags = IORESOURCE_IRQ, | ||
| 47 | }, { | ||
| 48 | .start = data->dma, | ||
| 49 | .end = data->dma, | ||
| 50 | .flags = IORESOURCE_DMA, | ||
| 51 | }, { | ||
| 52 | .start = data->dmairq, | ||
| 53 | .end = data->dmairq, | ||
| 54 | .flags = IORESOURCE_IRQ, | ||
| 55 | }, | ||
| 56 | |||
| 57 | }; | ||
| 58 | |||
| 59 | return mxs_add_platform_device("mxs-saif", data->id, res, | ||
| 60 | ARRAY_SIZE(res), pdata, sizeof(*pdata)); | ||
| 61 | } | ||
diff --git a/arch/arm/mach-mxs/devices/platform-mxsfb.c b/arch/arm/mach-mxs/devices/platform-mxsfb.c deleted file mode 100644 index 76b53f73418e..000000000000 --- a/arch/arm/mach-mxs/devices/platform-mxsfb.c +++ /dev/null | |||
| @@ -1,47 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2011 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify it under | ||
| 5 | * the terms of the GNU General Public License version 2 as published by the | ||
| 6 | * Free Software Foundation. | ||
| 7 | */ | ||
| 8 | #include <linux/dma-mapping.h> | ||
| 9 | #include <asm/sizes.h> | ||
| 10 | #include <mach/mx23.h> | ||
| 11 | #include <mach/mx28.h> | ||
| 12 | #include <mach/devices-common.h> | ||
| 13 | #include <linux/mxsfb.h> | ||
| 14 | |||
| 15 | #ifdef CONFIG_SOC_IMX23 | ||
| 16 | struct platform_device *__init mx23_add_mxsfb( | ||
| 17 | const struct mxsfb_platform_data *pdata) | ||
| 18 | { | ||
| 19 | struct resource res[] = { | ||
| 20 | { | ||
| 21 | .start = MX23_LCDIF_BASE_ADDR, | ||
| 22 | .end = MX23_LCDIF_BASE_ADDR + SZ_8K - 1, | ||
| 23 | .flags = IORESOURCE_MEM, | ||
| 24 | }, | ||
| 25 | }; | ||
| 26 | |||
| 27 | return mxs_add_platform_device_dmamask("imx23-fb", -1, | ||
| 28 | res, ARRAY_SIZE(res), pdata, sizeof(*pdata), DMA_BIT_MASK(32)); | ||
| 29 | } | ||
| 30 | #endif /* ifdef CONFIG_SOC_IMX23 */ | ||
| 31 | |||
| 32 | #ifdef CONFIG_SOC_IMX28 | ||
| 33 | struct platform_device *__init mx28_add_mxsfb( | ||
| 34 | const struct mxsfb_platform_data *pdata) | ||
| 35 | { | ||
| 36 | struct resource res[] = { | ||
| 37 | { | ||
| 38 | .start = MX28_LCDIF_BASE_ADDR, | ||
| 39 | .end = MX28_LCDIF_BASE_ADDR + SZ_8K - 1, | ||
| 40 | .flags = IORESOURCE_MEM, | ||
| 41 | }, | ||
| 42 | }; | ||
| 43 | |||
| 44 | return mxs_add_platform_device_dmamask("imx28-fb", -1, | ||
| 45 | res, ARRAY_SIZE(res), pdata, sizeof(*pdata), DMA_BIT_MASK(32)); | ||
| 46 | } | ||
| 47 | #endif /* ifdef CONFIG_SOC_IMX28 */ | ||
diff --git a/arch/arm/mach-mxs/devices/platform-rtc-stmp3xxx.c b/arch/arm/mach-mxs/devices/platform-rtc-stmp3xxx.c deleted file mode 100644 index 639eaee15553..000000000000 --- a/arch/arm/mach-mxs/devices/platform-rtc-stmp3xxx.c +++ /dev/null | |||
| @@ -1,51 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2011 Pengutronix, Wolfram Sang <w.sang@pengutronix.de> | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify it under | ||
| 5 | * the terms of the GNU General Public License version 2 as published by the | ||
| 6 | * Free Software Foundation. | ||
| 7 | */ | ||
| 8 | #include <asm/sizes.h> | ||
| 9 | #include <mach/mx23.h> | ||
| 10 | #include <mach/mx28.h> | ||
| 11 | #include <mach/devices-common.h> | ||
| 12 | |||
| 13 | #ifdef CONFIG_SOC_IMX23 | ||
| 14 | struct platform_device *__init mx23_add_rtc_stmp3xxx(void) | ||
| 15 | { | ||
| 16 | struct resource res[] = { | ||
| 17 | { | ||
| 18 | .start = MX23_RTC_BASE_ADDR, | ||
| 19 | .end = MX23_RTC_BASE_ADDR + SZ_8K - 1, | ||
| 20 | .flags = IORESOURCE_MEM, | ||
| 21 | }, { | ||
| 22 | .start = MX23_INT_RTC_ALARM, | ||
| 23 | .end = MX23_INT_RTC_ALARM, | ||
| 24 | .flags = IORESOURCE_IRQ, | ||
| 25 | }, | ||
| 26 | }; | ||
| 27 | |||
| 28 | return mxs_add_platform_device("stmp3xxx-rtc", 0, res, ARRAY_SIZE(res), | ||
| 29 | NULL, 0); | ||
| 30 | } | ||
| 31 | #endif /* CONFIG_SOC_IMX23 */ | ||
| 32 | |||
| 33 | #ifdef CONFIG_SOC_IMX28 | ||
| 34 | struct platform_device *__init mx28_add_rtc_stmp3xxx(void) | ||
| 35 | { | ||
| 36 | struct resource res[] = { | ||
| 37 | { | ||
| 38 | .start = MX28_RTC_BASE_ADDR, | ||
| 39 | .end = MX28_RTC_BASE_ADDR + SZ_8K - 1, | ||
| 40 | .flags = IORESOURCE_MEM, | ||
| 41 | }, { | ||
| 42 | .start = MX28_INT_RTC_ALARM, | ||
| 43 | .end = MX28_INT_RTC_ALARM, | ||
| 44 | .flags = IORESOURCE_IRQ, | ||
| 45 | }, | ||
| 46 | }; | ||
| 47 | |||
| 48 | return mxs_add_platform_device("stmp3xxx-rtc", 0, res, ARRAY_SIZE(res), | ||
| 49 | NULL, 0); | ||
| 50 | } | ||
| 51 | #endif /* CONFIG_SOC_IMX28 */ | ||
diff --git a/arch/arm/mach-mxs/include/mach/common.h b/arch/arm/mach-mxs/include/mach/common.h index de6c7ba42544..4dec79563f19 100644 --- a/arch/arm/mach-mxs/include/mach/common.h +++ b/arch/arm/mach-mxs/include/mach/common.h | |||
| @@ -17,21 +17,12 @@ extern void mxs_timer_init(int); | |||
| 17 | extern void mxs_restart(char, const char *); | 17 | extern void mxs_restart(char, const char *); |
| 18 | extern int mxs_saif_clkmux_select(unsigned int clkmux); | 18 | extern int mxs_saif_clkmux_select(unsigned int clkmux); |
| 19 | 19 | ||
| 20 | extern void mx23_soc_init(void); | ||
| 21 | extern int mx23_clocks_init(void); | 20 | extern int mx23_clocks_init(void); |
| 22 | extern void mx23_map_io(void); | 21 | extern void mx23_map_io(void); |
| 23 | extern void mx23_init_irq(void); | ||
| 24 | 22 | ||
| 25 | extern void mx28_soc_init(void); | ||
| 26 | extern int mx28_clocks_init(void); | 23 | extern int mx28_clocks_init(void); |
| 27 | extern void mx28_map_io(void); | 24 | extern void mx28_map_io(void); |
| 28 | extern void mx28_init_irq(void); | ||
| 29 | 25 | ||
| 30 | extern void icoll_init_irq(void); | 26 | extern void icoll_init_irq(void); |
| 31 | 27 | ||
| 32 | extern struct platform_device *mxs_add_dma(const char *devid, | ||
| 33 | resource_size_t base); | ||
| 34 | extern struct platform_device *mxs_add_gpio(char *name, int id, | ||
| 35 | resource_size_t iobase, int irq); | ||
| 36 | |||
| 37 | #endif /* __MACH_MXS_COMMON_H__ */ | 28 | #endif /* __MACH_MXS_COMMON_H__ */ |
diff --git a/arch/arm/mach-mxs/include/mach/devices-common.h b/arch/arm/mach-mxs/include/mach/devices-common.h deleted file mode 100644 index e8b1d958240b..000000000000 --- a/arch/arm/mach-mxs/include/mach/devices-common.h +++ /dev/null | |||
| @@ -1,114 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2009-2010 Pengutronix | ||
| 3 | * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it under | ||
| 6 | * the terms of the GNU General Public License version 2 as published by the | ||
| 7 | * Free Software Foundation. | ||
| 8 | */ | ||
| 9 | #include <linux/kernel.h> | ||
| 10 | #include <linux/platform_device.h> | ||
| 11 | #include <linux/init.h> | ||
| 12 | #include <linux/amba/bus.h> | ||
| 13 | |||
| 14 | extern struct device mxs_apbh_bus; | ||
| 15 | |||
| 16 | struct platform_device *mxs_add_platform_device_dmamask( | ||
| 17 | const char *name, int id, | ||
| 18 | const struct resource *res, unsigned int num_resources, | ||
| 19 | const void *data, size_t size_data, u64 dmamask); | ||
| 20 | |||
| 21 | static inline struct platform_device *mxs_add_platform_device( | ||
| 22 | const char *name, int id, | ||
| 23 | const struct resource *res, unsigned int num_resources, | ||
| 24 | const void *data, size_t size_data) | ||
| 25 | { | ||
| 26 | return mxs_add_platform_device_dmamask( | ||
| 27 | name, id, res, num_resources, data, size_data, 0); | ||
| 28 | } | ||
| 29 | |||
| 30 | /* auart */ | ||
| 31 | struct mxs_auart_data { | ||
| 32 | int id; | ||
| 33 | resource_size_t iobase; | ||
| 34 | resource_size_t iosize; | ||
| 35 | resource_size_t irq; | ||
| 36 | }; | ||
| 37 | struct platform_device *__init mxs_add_auart( | ||
| 38 | const struct mxs_auart_data *data); | ||
| 39 | |||
| 40 | /* fec */ | ||
| 41 | #include <linux/fec.h> | ||
| 42 | struct mxs_fec_data { | ||
| 43 | int id; | ||
| 44 | resource_size_t iobase; | ||
| 45 | resource_size_t iosize; | ||
| 46 | resource_size_t irq; | ||
| 47 | }; | ||
| 48 | struct platform_device *__init mxs_add_fec( | ||
| 49 | const struct mxs_fec_data *data, | ||
| 50 | const struct fec_platform_data *pdata); | ||
| 51 | |||
| 52 | /* flexcan */ | ||
| 53 | #include <linux/can/platform/flexcan.h> | ||
| 54 | struct mxs_flexcan_data { | ||
| 55 | int id; | ||
| 56 | resource_size_t iobase; | ||
| 57 | resource_size_t iosize; | ||
| 58 | resource_size_t irq; | ||
| 59 | }; | ||
| 60 | struct platform_device *__init mxs_add_flexcan( | ||
| 61 | const struct mxs_flexcan_data *data, | ||
| 62 | const struct flexcan_platform_data *pdata); | ||
| 63 | |||
| 64 | /* gpmi-nand */ | ||
| 65 | #include <linux/mtd/gpmi-nand.h> | ||
| 66 | struct mxs_gpmi_nand_data { | ||
| 67 | const char *devid; | ||
| 68 | const struct resource res[GPMI_NAND_RES_SIZE]; | ||
| 69 | }; | ||
| 70 | struct platform_device *__init | ||
| 71 | mxs_add_gpmi_nand(const struct gpmi_nand_platform_data *pdata, | ||
| 72 | const struct mxs_gpmi_nand_data *data); | ||
| 73 | |||
| 74 | /* i2c */ | ||
| 75 | struct mxs_mxs_i2c_data { | ||
| 76 | int id; | ||
| 77 | resource_size_t iobase; | ||
| 78 | resource_size_t errirq; | ||
| 79 | resource_size_t dmairq; | ||
| 80 | }; | ||
| 81 | struct platform_device * __init mxs_add_mxs_i2c( | ||
| 82 | const struct mxs_mxs_i2c_data *data); | ||
| 83 | |||
| 84 | /* mmc */ | ||
| 85 | #include <linux/mmc/mxs-mmc.h> | ||
| 86 | struct mxs_mxs_mmc_data { | ||
| 87 | const char *devid; | ||
| 88 | int id; | ||
| 89 | resource_size_t iobase; | ||
| 90 | resource_size_t dma; | ||
| 91 | resource_size_t irq_err; | ||
| 92 | resource_size_t irq_dma; | ||
| 93 | }; | ||
| 94 | struct platform_device *__init mxs_add_mxs_mmc( | ||
| 95 | const struct mxs_mxs_mmc_data *data, | ||
| 96 | const struct mxs_mmc_platform_data *pdata); | ||
| 97 | |||
| 98 | /* pwm */ | ||
| 99 | struct platform_device *__init mxs_add_mxs_pwm( | ||
| 100 | resource_size_t iobase, int id); | ||
| 101 | |||
| 102 | /* saif */ | ||
| 103 | #include <sound/saif.h> | ||
| 104 | struct mxs_saif_data { | ||
| 105 | int id; | ||
| 106 | resource_size_t iobase; | ||
| 107 | resource_size_t irq; | ||
| 108 | resource_size_t dma; | ||
| 109 | resource_size_t dmairq; | ||
| 110 | }; | ||
| 111 | |||
| 112 | struct platform_device *__init mxs_add_saif( | ||
| 113 | const struct mxs_saif_data *data, | ||
| 114 | const struct mxs_saif_platform_data *pdata); | ||
diff --git a/arch/arm/mach-mxs/include/mach/iomux-mx23.h b/arch/arm/mach-mxs/include/mach/iomux-mx23.h deleted file mode 100644 index b0190a4822f2..000000000000 --- a/arch/arm/mach-mxs/include/mach/iomux-mx23.h +++ /dev/null | |||
| @@ -1,355 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com> | ||
| 3 | * Copyright (C) 2010 Freescale Semiconductor, Inc. | ||
| 4 | * | ||
| 5 | * The code contained herein is licensed under the GNU General Public | ||
| 6 | * License. You may obtain a copy of the GNU General Public License | ||
| 7 | * Version 2 or later at the following locations: | ||
| 8 | * | ||
| 9 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 10 | * http://www.gnu.org/copyleft/gpl.html | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __MACH_IOMUX_MX23_H__ | ||
| 14 | #define __MACH_IOMUX_MX23_H__ | ||
| 15 | |||
| 16 | #include <mach/iomux.h> | ||
| 17 | |||
| 18 | /* | ||
| 19 | * The naming convention for the pad modes is MX23_PAD_<padname>__<padmode> | ||
| 20 | * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num> | ||
| 21 | * See also iomux.h | ||
| 22 | * | ||
| 23 | * BANK PIN MUX | ||
| 24 | */ | ||
| 25 | /* MUXSEL_0 */ | ||
| 26 | #define MX23_PAD_GPMI_D00__GPMI_D00 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_0) | ||
| 27 | #define MX23_PAD_GPMI_D01__GPMI_D01 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_0) | ||
| 28 | #define MX23_PAD_GPMI_D02__GPMI_D02 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_0) | ||
| 29 | #define MX23_PAD_GPMI_D03__GPMI_D03 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_0) | ||
| 30 | #define MX23_PAD_GPMI_D04__GPMI_D04 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_0) | ||
| 31 | #define MX23_PAD_GPMI_D05__GPMI_D05 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_0) | ||
| 32 | #define MX23_PAD_GPMI_D06__GPMI_D06 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_0) | ||
| 33 | #define MX23_PAD_GPMI_D07__GPMI_D07 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_0) | ||
| 34 | #define MX23_PAD_GPMI_D08__GPMI_D08 MXS_IOMUX_PAD_NAKED(0, 8, PAD_MUXSEL_0) | ||
| 35 | #define MX23_PAD_GPMI_D09__GPMI_D09 MXS_IOMUX_PAD_NAKED(0, 9, PAD_MUXSEL_0) | ||
| 36 | #define MX23_PAD_GPMI_D10__GPMI_D10 MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_0) | ||
| 37 | #define MX23_PAD_GPMI_D11__GPMI_D11 MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_0) | ||
| 38 | #define MX23_PAD_GPMI_D12__GPMI_D12 MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_0) | ||
| 39 | #define MX23_PAD_GPMI_D13__GPMI_D13 MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_0) | ||
| 40 | #define MX23_PAD_GPMI_D14__GPMI_D14 MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_0) | ||
| 41 | #define MX23_PAD_GPMI_D15__GPMI_D15 MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_0) | ||
| 42 | #define MX23_PAD_GPMI_CLE__GPMI_CLE MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_0) | ||
| 43 | #define MX23_PAD_GPMI_ALE__GPMI_ALE MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_0) | ||
| 44 | #define MX23_PAD_GPMI_CE2N__GPMI_CE2N MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_0) | ||
| 45 | #define MX23_PAD_GPMI_RDY0__GPMI_RDY0 MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_0) | ||
| 46 | #define MX23_PAD_GPMI_RDY1__GPMI_RDY1 MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_0) | ||
| 47 | #define MX23_PAD_GPMI_RDY2__GPMI_RDY2 MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_0) | ||
| 48 | #define MX23_PAD_GPMI_RDY3__GPMI_RDY3 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_0) | ||
| 49 | #define MX23_PAD_GPMI_WPN__GPMI_WPN MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_0) | ||
| 50 | #define MX23_PAD_GPMI_WRN__GPMI_WRN MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_0) | ||
| 51 | #define MX23_PAD_GPMI_RDN__GPMI_RDN MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_0) | ||
| 52 | #define MX23_PAD_AUART1_CTS__AUART1_CTS MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_0) | ||
| 53 | #define MX23_PAD_AUART1_RTS__AUART1_RTS MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_0) | ||
| 54 | #define MX23_PAD_AUART1_RX__AUART1_RX MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_0) | ||
| 55 | #define MX23_PAD_AUART1_TX__AUART1_TX MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_0) | ||
| 56 | #define MX23_PAD_I2C_SCL__I2C_SCL MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_0) | ||
| 57 | #define MX23_PAD_I2C_SDA__I2C_SDA MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_0) | ||
| 58 | |||
| 59 | #define MX23_PAD_LCD_D00__LCD_D00 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_0) | ||
| 60 | #define MX23_PAD_LCD_D01__LCD_D01 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_0) | ||
| 61 | #define MX23_PAD_LCD_D02__LCD_D02 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_0) | ||
| 62 | #define MX23_PAD_LCD_D03__LCD_D03 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_0) | ||
| 63 | #define MX23_PAD_LCD_D04__LCD_D04 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_0) | ||
| 64 | #define MX23_PAD_LCD_D05__LCD_D05 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_0) | ||
| 65 | #define MX23_PAD_LCD_D06__LCD_D06 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_0) | ||
| 66 | #define MX23_PAD_LCD_D07__LCD_D07 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_0) | ||
| 67 | #define MX23_PAD_LCD_D08__LCD_D08 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_0) | ||
| 68 | #define MX23_PAD_LCD_D09__LCD_D09 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_0) | ||
| 69 | #define MX23_PAD_LCD_D10__LCD_D10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_0) | ||
| 70 | #define MX23_PAD_LCD_D11__LCD_D11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_0) | ||
| 71 | #define MX23_PAD_LCD_D12__LCD_D12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_0) | ||
| 72 | #define MX23_PAD_LCD_D13__LCD_D13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_0) | ||
| 73 | #define MX23_PAD_LCD_D14__LCD_D14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_0) | ||
| 74 | #define MX23_PAD_LCD_D15__LCD_D15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_0) | ||
| 75 | #define MX23_PAD_LCD_D16__LCD_D16 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_0) | ||
| 76 | #define MX23_PAD_LCD_D17__LCD_D17 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_0) | ||
| 77 | #define MX23_PAD_LCD_RESET__LCD_RESET MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_0) | ||
| 78 | #define MX23_PAD_LCD_RS__LCD_RS MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_0) | ||
| 79 | #define MX23_PAD_LCD_WR__LCD_WR MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_0) | ||
| 80 | #define MX23_PAD_LCD_CS__LCD_CS MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_0) | ||
| 81 | #define MX23_PAD_LCD_DOTCK__LCD_DOTCK MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_0) | ||
| 82 | #define MX23_PAD_LCD_ENABLE__LCD_ENABLE MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_0) | ||
| 83 | #define MX23_PAD_LCD_HSYNC__LCD_HSYNC MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_0) | ||
| 84 | #define MX23_PAD_LCD_VSYNC__LCD_VSYNC MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_0) | ||
| 85 | #define MX23_PAD_PWM0__PWM0 MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_0) | ||
| 86 | #define MX23_PAD_PWM1__PWM1 MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_0) | ||
| 87 | #define MX23_PAD_PWM2__PWM2 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_0) | ||
| 88 | #define MX23_PAD_PWM3__PWM3 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_0) | ||
| 89 | #define MX23_PAD_PWM4__PWM4 MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_0) | ||
| 90 | |||
| 91 | #define MX23_PAD_SSP1_CMD__SSP1_CMD MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_0) | ||
| 92 | #define MX23_PAD_SSP1_DETECT__SSP1_DETECT MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_0) | ||
| 93 | #define MX23_PAD_SSP1_DATA0__SSP1_DATA0 MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_0) | ||
| 94 | #define MX23_PAD_SSP1_DATA1__SSP1_DATA1 MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_0) | ||
| 95 | #define MX23_PAD_SSP1_DATA2__SSP1_DATA2 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_0) | ||
| 96 | #define MX23_PAD_SSP1_DATA3__SSP1_DATA3 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_0) | ||
| 97 | #define MX23_PAD_SSP1_SCK__SSP1_SCK MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_0) | ||
| 98 | #define MX23_PAD_ROTARYA__ROTARYA MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_0) | ||
| 99 | #define MX23_PAD_ROTARYB__ROTARYB MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_0) | ||
| 100 | #define MX23_PAD_EMI_A00__EMI_A00 MXS_IOMUX_PAD_NAKED(2, 9, PAD_MUXSEL_0) | ||
| 101 | #define MX23_PAD_EMI_A01__EMI_A01 MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_0) | ||
| 102 | #define MX23_PAD_EMI_A02__EMI_A02 MXS_IOMUX_PAD_NAKED(2, 11, PAD_MUXSEL_0) | ||
| 103 | #define MX23_PAD_EMI_A03__EMI_A03 MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_0) | ||
| 104 | #define MX23_PAD_EMI_A04__EMI_A04 MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_0) | ||
| 105 | #define MX23_PAD_EMI_A05__EMI_A05 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_0) | ||
| 106 | #define MX23_PAD_EMI_A06__EMI_A06 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_0) | ||
| 107 | #define MX23_PAD_EMI_A07__EMI_A07 MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_0) | ||
| 108 | #define MX23_PAD_EMI_A08__EMI_A08 MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_0) | ||
| 109 | #define MX23_PAD_EMI_A09__EMI_A09 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_0) | ||
| 110 | #define MX23_PAD_EMI_A10__EMI_A10 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_0) | ||
| 111 | #define MX23_PAD_EMI_A11__EMI_A11 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_0) | ||
| 112 | #define MX23_PAD_EMI_A12__EMI_A12 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_0) | ||
| 113 | #define MX23_PAD_EMI_BA0__EMI_BA0 MXS_IOMUX_PAD_NAKED(2, 22, PAD_MUXSEL_0) | ||
| 114 | #define MX23_PAD_EMI_BA1__EMI_BA1 MXS_IOMUX_PAD_NAKED(2, 23, PAD_MUXSEL_0) | ||
| 115 | #define MX23_PAD_EMI_CASN__EMI_CASN MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_0) | ||
| 116 | #define MX23_PAD_EMI_CE0N__EMI_CE0N MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_0) | ||
| 117 | #define MX23_PAD_EMI_CE1N__EMI_CE1N MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_0) | ||
| 118 | #define MX23_PAD_GPMI_CE1N__GPMI_CE1N MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_0) | ||
| 119 | #define MX23_PAD_GPMI_CE0N__GPMI_CE0N MXS_IOMUX_PAD_NAKED(2, 28, PAD_MUXSEL_0) | ||
| 120 | #define MX23_PAD_EMI_CKE__EMI_CKE MXS_IOMUX_PAD_NAKED(2, 29, PAD_MUXSEL_0) | ||
| 121 | #define MX23_PAD_EMI_RASN__EMI_RASN MXS_IOMUX_PAD_NAKED(2, 30, PAD_MUXSEL_0) | ||
| 122 | #define MX23_PAD_EMI_WEN__EMI_WEN MXS_IOMUX_PAD_NAKED(2, 31, PAD_MUXSEL_0) | ||
| 123 | |||
| 124 | #define MX23_PAD_EMI_D00__EMI_D00 MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_0) | ||
| 125 | #define MX23_PAD_EMI_D01__EMI_D01 MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_0) | ||
| 126 | #define MX23_PAD_EMI_D02__EMI_D02 MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_0) | ||
| 127 | #define MX23_PAD_EMI_D03__EMI_D03 MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_0) | ||
| 128 | #define MX23_PAD_EMI_D04__EMI_D04 MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_0) | ||
| 129 | #define MX23_PAD_EMI_D05__EMI_D05 MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_0) | ||
| 130 | #define MX23_PAD_EMI_D06__EMI_D06 MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_0) | ||
| 131 | #define MX23_PAD_EMI_D07__EMI_D07 MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_0) | ||
| 132 | #define MX23_PAD_EMI_D08__EMI_D08 MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_0) | ||
| 133 | #define MX23_PAD_EMI_D09__EMI_D09 MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_0) | ||
| 134 | #define MX23_PAD_EMI_D10__EMI_D10 MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_0) | ||
| 135 | #define MX23_PAD_EMI_D11__EMI_D11 MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_0) | ||
| 136 | #define MX23_PAD_EMI_D12__EMI_D12 MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_0) | ||
| 137 | #define MX23_PAD_EMI_D13__EMI_D13 MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_0) | ||
| 138 | #define MX23_PAD_EMI_D14__EMI_D14 MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_0) | ||
| 139 | #define MX23_PAD_EMI_D15__EMI_D15 MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_0) | ||
| 140 | #define MX23_PAD_EMI_DQM0__EMI_DQM0 MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_0) | ||
| 141 | #define MX23_PAD_EMI_DQM1__EMI_DQM1 MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_0) | ||
| 142 | #define MX23_PAD_EMI_DQS0__EMI_DQS0 MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_0) | ||
| 143 | #define MX23_PAD_EMI_DQS1__EMI_DQS1 MXS_IOMUX_PAD_NAKED(3, 19, PAD_MUXSEL_0) | ||
| 144 | #define MX23_PAD_EMI_CLK__EMI_CLK MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_0) | ||
| 145 | #define MX23_PAD_EMI_CLKN__EMI_CLKN MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_0) | ||
| 146 | |||
| 147 | /* MUXSEL_1 */ | ||
| 148 | #define MX23_PAD_GPMI_D00__LCD_D8 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_1) | ||
| 149 | #define MX23_PAD_GPMI_D01__LCD_D9 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_1) | ||
| 150 | #define MX23_PAD_GPMI_D02__LCD_D10 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_1) | ||
| 151 | #define MX23_PAD_GPMI_D03__LCD_D11 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_1) | ||
| 152 | #define MX23_PAD_GPMI_D04__LCD_D12 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_1) | ||
| 153 | #define MX23_PAD_GPMI_D05__LCD_D13 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_1) | ||
| 154 | #define MX23_PAD_GPMI_D06__LCD_D14 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_1) | ||
| 155 | #define MX23_PAD_GPMI_D07__LCD_D15 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_1) | ||
| 156 | #define MX23_PAD_GPMI_D08__LCD_D18 MXS_IOMUX_PAD_NAKED(0, 8, PAD_MUXSEL_1) | ||
| 157 | #define MX23_PAD_GPMI_D09__LCD_D19 MXS_IOMUX_PAD_NAKED(0, 9, PAD_MUXSEL_1) | ||
| 158 | #define MX23_PAD_GPMI_D10__LCD_D20 MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_1) | ||
| 159 | #define MX23_PAD_GPMI_D11__LCD_D21 MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_1) | ||
| 160 | #define MX23_PAD_GPMI_D12__LCD_D22 MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_1) | ||
| 161 | #define MX23_PAD_GPMI_D13__LCD_D23 MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_1) | ||
| 162 | #define MX23_PAD_GPMI_D14__AUART2_RX MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_1) | ||
| 163 | #define MX23_PAD_GPMI_D15__AUART2_TX MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_1) | ||
| 164 | #define MX23_PAD_GPMI_CLE__LCD_D16 MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_1) | ||
| 165 | #define MX23_PAD_GPMI_ALE__LCD_D17 MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_1) | ||
| 166 | #define MX23_PAD_GPMI_CE2N__ATA_A2 MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_1) | ||
| 167 | #define MX23_PAD_AUART1_RTS__IR_CLK MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_1) | ||
| 168 | #define MX23_PAD_AUART1_RX__IR_RX MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_1) | ||
| 169 | #define MX23_PAD_AUART1_TX__IR_TX MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_1) | ||
| 170 | #define MX23_PAD_I2C_SCL__GPMI_RDY2 MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_1) | ||
| 171 | #define MX23_PAD_I2C_SDA__GPMI_CE2N MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_1) | ||
| 172 | |||
| 173 | #define MX23_PAD_LCD_D00__ETM_DA8 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_1) | ||
| 174 | #define MX23_PAD_LCD_D01__ETM_DA9 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_1) | ||
| 175 | #define MX23_PAD_LCD_D02__ETM_DA10 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_1) | ||
| 176 | #define MX23_PAD_LCD_D03__ETM_DA11 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_1) | ||
| 177 | #define MX23_PAD_LCD_D04__ETM_DA12 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_1) | ||
| 178 | #define MX23_PAD_LCD_D05__ETM_DA13 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_1) | ||
| 179 | #define MX23_PAD_LCD_D06__ETM_DA14 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_1) | ||
| 180 | #define MX23_PAD_LCD_D07__ETM_DA15 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_1) | ||
| 181 | #define MX23_PAD_LCD_D08__ETM_DA0 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_1) | ||
| 182 | #define MX23_PAD_LCD_D09__ETM_DA1 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_1) | ||
| 183 | #define MX23_PAD_LCD_D10__ETM_DA2 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_1) | ||
| 184 | #define MX23_PAD_LCD_D11__ETM_DA3 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_1) | ||
| 185 | #define MX23_PAD_LCD_D12__ETM_DA4 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_1) | ||
| 186 | #define MX23_PAD_LCD_D13__ETM_DA5 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_1) | ||
| 187 | #define MX23_PAD_LCD_D14__ETM_DA6 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_1) | ||
| 188 | #define MX23_PAD_LCD_D15__ETM_DA7 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_1) | ||
| 189 | #define MX23_PAD_LCD_RESET__ETM_TCTL MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_1) | ||
| 190 | #define MX23_PAD_LCD_RS__ETM_TCLK MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_1) | ||
| 191 | #define MX23_PAD_LCD_DOTCK__GPMI_RDY3 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_1) | ||
| 192 | #define MX23_PAD_LCD_ENABLE__I2C_SCL MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_1) | ||
| 193 | #define MX23_PAD_LCD_HSYNC__I2C_SDA MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_1) | ||
| 194 | #define MX23_PAD_LCD_VSYNC__LCD_BUSY MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_1) | ||
| 195 | #define MX23_PAD_PWM0__ROTARYA MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_1) | ||
| 196 | #define MX23_PAD_PWM1__ROTARYB MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_1) | ||
| 197 | #define MX23_PAD_PWM2__GPMI_RDY3 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_1) | ||
| 198 | #define MX23_PAD_PWM3__ETM_TCTL MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_1) | ||
| 199 | #define MX23_PAD_PWM4__ETM_TCLK MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_1) | ||
| 200 | |||
| 201 | #define MX23_PAD_SSP1_DETECT__GPMI_CE3N MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_1) | ||
| 202 | #define MX23_PAD_SSP1_DATA1__I2C_SCL MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_1) | ||
| 203 | #define MX23_PAD_SSP1_DATA2__I2C_SDA MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_1) | ||
| 204 | #define MX23_PAD_ROTARYA__AUART2_RTS MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_1) | ||
| 205 | #define MX23_PAD_ROTARYB__AUART2_CTS MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_1) | ||
| 206 | |||
| 207 | /* MUXSEL_2 */ | ||
| 208 | #define MX23_PAD_GPMI_D00__SSP2_DATA0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_2) | ||
| 209 | #define MX23_PAD_GPMI_D01__SSP2_DATA1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_2) | ||
| 210 | #define MX23_PAD_GPMI_D02__SSP2_DATA2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_2) | ||
| 211 | #define MX23_PAD_GPMI_D03__SSP2_DATA3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_2) | ||
| 212 | #define MX23_PAD_GPMI_D04__SSP2_DATA4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_2) | ||
| 213 | #define MX23_PAD_GPMI_D05__SSP2_DATA5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_2) | ||
| 214 | #define MX23_PAD_GPMI_D06__SSP2_DATA6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_2) | ||
| 215 | #define MX23_PAD_GPMI_D07__SSP2_DATA7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_2) | ||
| 216 | #define MX23_PAD_GPMI_D08__SSP1_DATA4 MXS_IOMUX_PAD_NAKED(0, 8, PAD_MUXSEL_2) | ||
| 217 | #define MX23_PAD_GPMI_D09__SSP1_DATA5 MXS_IOMUX_PAD_NAKED(0, 9, PAD_MUXSEL_2) | ||
| 218 | #define MX23_PAD_GPMI_D10__SSP1_DATA6 MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_2) | ||
| 219 | #define MX23_PAD_GPMI_D11__SSP1_DATA7 MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_2) | ||
| 220 | #define MX23_PAD_GPMI_D15__GPMI_CE3N MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_2) | ||
| 221 | #define MX23_PAD_GPMI_RDY0__SSP2_DETECT MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_2) | ||
| 222 | #define MX23_PAD_GPMI_RDY1__SSP2_CMD MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_2) | ||
| 223 | #define MX23_PAD_GPMI_WRN__SSP2_SCK MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_2) | ||
| 224 | #define MX23_PAD_AUART1_CTS__SSP1_DATA4 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_2) | ||
| 225 | #define MX23_PAD_AUART1_RTS__SSP1_DATA5 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_2) | ||
| 226 | #define MX23_PAD_AUART1_RX__SSP1_DATA6 MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_2) | ||
| 227 | #define MX23_PAD_AUART1_TX__SSP1_DATA7 MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_2) | ||
| 228 | #define MX23_PAD_I2C_SCL__AUART1_TX MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_2) | ||
| 229 | #define MX23_PAD_I2C_SDA__AUART1_RX MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_2) | ||
| 230 | |||
| 231 | #define MX23_PAD_LCD_D08__SAIF2_SDATA0 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_2) | ||
| 232 | #define MX23_PAD_LCD_D09__SAIF1_SDATA0 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_2) | ||
| 233 | #define MX23_PAD_LCD_D10__SAIF_MCLK_BITCLK MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_2) | ||
| 234 | #define MX23_PAD_LCD_D11__SAIF_LRCLK MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_2) | ||
| 235 | #define MX23_PAD_LCD_D12__SAIF2_SDATA1 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_2) | ||
| 236 | #define MX23_PAD_LCD_D13__SAIF2_SDATA2 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_2) | ||
| 237 | #define MX23_PAD_LCD_D14__SAIF1_SDATA2 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_2) | ||
| 238 | #define MX23_PAD_LCD_D15__SAIF1_SDATA1 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_2) | ||
| 239 | #define MX23_PAD_LCD_D16__SAIF_ALT_BITCLK MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_2) | ||
| 240 | #define MX23_PAD_LCD_RESET__GPMI_CE3N MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_2) | ||
| 241 | #define MX23_PAD_PWM0__DUART_RX MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_2) | ||
| 242 | #define MX23_PAD_PWM1__DUART_TX MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_2) | ||
| 243 | #define MX23_PAD_PWM3__AUART1_CTS MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_2) | ||
| 244 | #define MX23_PAD_PWM4__AUART1_RTS MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_2) | ||
| 245 | |||
| 246 | #define MX23_PAD_SSP1_CMD__JTAG_TDO MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_2) | ||
| 247 | #define MX23_PAD_SSP1_DETECT__USB_OTG_ID MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_2) | ||
| 248 | #define MX23_PAD_SSP1_DATA0__JTAG_TDI MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_2) | ||
| 249 | #define MX23_PAD_SSP1_DATA1__JTAG_TCLK MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_2) | ||
| 250 | #define MX23_PAD_SSP1_DATA2__JTAG_RTCK MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_2) | ||
| 251 | #define MX23_PAD_SSP1_DATA3__JTAG_TMS MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_2) | ||
| 252 | #define MX23_PAD_SSP1_SCK__JTAG_TRST MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_2) | ||
| 253 | #define MX23_PAD_ROTARYA__SPDIF MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_2) | ||
| 254 | #define MX23_PAD_ROTARYB__GPMI_CE3N MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_2) | ||
| 255 | |||
| 256 | /* MUXSEL_GPIO */ | ||
| 257 | #define MX23_PAD_GPMI_D00__GPIO_0_0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_GPIO) | ||
| 258 | #define MX23_PAD_GPMI_D01__GPIO_0_1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_GPIO) | ||
| 259 | #define MX23_PAD_GPMI_D02__GPIO_0_2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_GPIO) | ||
| 260 | #define MX23_PAD_GPMI_D03__GPIO_0_3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_GPIO) | ||
| 261 | #define MX23_PAD_GPMI_D04__GPIO_0_4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_GPIO) | ||
| 262 | #define MX23_PAD_GPMI_D05__GPIO_0_5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_GPIO) | ||
| 263 | #define MX23_PAD_GPMI_D06__GPIO_0_6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_GPIO) | ||
| 264 | #define MX23_PAD_GPMI_D07__GPIO_0_7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_GPIO) | ||
| 265 | #define MX23_PAD_GPMI_D08__GPIO_0_8 MXS_IOMUX_PAD_NAKED(0, 8, PAD_MUXSEL_GPIO) | ||
| 266 | #define MX23_PAD_GPMI_D09__GPIO_0_9 MXS_IOMUX_PAD_NAKED(0, 9, PAD_MUXSEL_GPIO) | ||
| 267 | #define MX23_PAD_GPMI_D10__GPIO_0_10 MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_GPIO) | ||
| 268 | #define MX23_PAD_GPMI_D11__GPIO_0_11 MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_GPIO) | ||
| 269 | #define MX23_PAD_GPMI_D12__GPIO_0_12 MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_GPIO) | ||
| 270 | #define MX23_PAD_GPMI_D13__GPIO_0_13 MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_GPIO) | ||
| 271 | #define MX23_PAD_GPMI_D14__GPIO_0_14 MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_GPIO) | ||
| 272 | #define MX23_PAD_GPMI_D15__GPIO_0_15 MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_GPIO) | ||
| 273 | #define MX23_PAD_GPMI_CLE__GPIO_0_16 MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_GPIO) | ||
| 274 | #define MX23_PAD_GPMI_ALE__GPIO_0_17 MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_GPIO) | ||
| 275 | #define MX23_PAD_GPMI_CE2N__GPIO_0_18 MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_GPIO) | ||
| 276 | #define MX23_PAD_GPMI_RDY0__GPIO_0_19 MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_GPIO) | ||
| 277 | #define MX23_PAD_GPMI_RDY1__GPIO_0_20 MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_GPIO) | ||
| 278 | #define MX23_PAD_GPMI_RDY2__GPIO_0_21 MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_GPIO) | ||
| 279 | #define MX23_PAD_GPMI_RDY3__GPIO_0_22 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_GPIO) | ||
| 280 | #define MX23_PAD_GPMI_WPN__GPIO_0_23 MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_GPIO) | ||
| 281 | #define MX23_PAD_GPMI_WRN__GPIO_0_24 MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_GPIO) | ||
| 282 | #define MX23_PAD_GPMI_RDN__GPIO_0_25 MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_GPIO) | ||
| 283 | #define MX23_PAD_AUART1_CTS__GPIO_0_26 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_GPIO) | ||
| 284 | #define MX23_PAD_AUART1_RTS__GPIO_0_27 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_GPIO) | ||
| 285 | #define MX23_PAD_AUART1_RX__GPIO_0_28 MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_GPIO) | ||
| 286 | #define MX23_PAD_AUART1_TX__GPIO_0_29 MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_GPIO) | ||
| 287 | #define MX23_PAD_I2C_SCL__GPIO_0_30 MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_GPIO) | ||
| 288 | #define MX23_PAD_I2C_SDA__GPIO_0_31 MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_GPIO) | ||
| 289 | |||
| 290 | #define MX23_PAD_LCD_D00__GPIO_1_0 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_GPIO) | ||
| 291 | #define MX23_PAD_LCD_D01__GPIO_1_1 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_GPIO) | ||
| 292 | #define MX23_PAD_LCD_D02__GPIO_1_2 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_GPIO) | ||
| 293 | #define MX23_PAD_LCD_D03__GPIO_1_3 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_GPIO) | ||
| 294 | #define MX23_PAD_LCD_D04__GPIO_1_4 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_GPIO) | ||
| 295 | #define MX23_PAD_LCD_D05__GPIO_1_5 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_GPIO) | ||
| 296 | #define MX23_PAD_LCD_D06__GPIO_1_6 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_GPIO) | ||
| 297 | #define MX23_PAD_LCD_D07__GPIO_1_7 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_GPIO) | ||
| 298 | #define MX23_PAD_LCD_D08__GPIO_1_8 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_GPIO) | ||
| 299 | #define MX23_PAD_LCD_D09__GPIO_1_9 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_GPIO) | ||
| 300 | #define MX23_PAD_LCD_D10__GPIO_1_10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_GPIO) | ||
| 301 | #define MX23_PAD_LCD_D11__GPIO_1_11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_GPIO) | ||
| 302 | #define MX23_PAD_LCD_D12__GPIO_1_12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_GPIO) | ||
| 303 | #define MX23_PAD_LCD_D13__GPIO_1_13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_GPIO) | ||
| 304 | #define MX23_PAD_LCD_D14__GPIO_1_14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_GPIO) | ||
| 305 | #define MX23_PAD_LCD_D15__GPIO_1_15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_GPIO) | ||
| 306 | #define MX23_PAD_LCD_D16__GPIO_1_16 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_GPIO) | ||
| 307 | #define MX23_PAD_LCD_D17__GPIO_1_17 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_GPIO) | ||
| 308 | #define MX23_PAD_LCD_RESET__GPIO_1_18 MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_GPIO) | ||
| 309 | #define MX23_PAD_LCD_RS__GPIO_1_19 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_GPIO) | ||
| 310 | #define MX23_PAD_LCD_WR__GPIO_1_20 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_GPIO) | ||
| 311 | #define MX23_PAD_LCD_CS__GPIO_1_21 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_GPIO) | ||
| 312 | #define MX23_PAD_LCD_DOTCK__GPIO_1_22 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_GPIO) | ||
| 313 | #define MX23_PAD_LCD_ENABLE__GPIO_1_23 MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_GPIO) | ||
| 314 | #define MX23_PAD_LCD_HSYNC__GPIO_1_24 MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_GPIO) | ||
| 315 | #define MX23_PAD_LCD_VSYNC__GPIO_1_25 MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_GPIO) | ||
| 316 | #define MX23_PAD_PWM0__GPIO_1_26 MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_GPIO) | ||
| 317 | #define MX23_PAD_PWM1__GPIO_1_27 MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_GPIO) | ||
| 318 | #define MX23_PAD_PWM2__GPIO_1_28 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_GPIO) | ||
| 319 | #define MX23_PAD_PWM3__GPIO_1_29 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_GPIO) | ||
| 320 | #define MX23_PAD_PWM4__GPIO_1_30 MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_GPIO) | ||
| 321 | |||
| 322 | #define MX23_PAD_SSP1_CMD__GPIO_2_0 MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_GPIO) | ||
| 323 | #define MX23_PAD_SSP1_DETECT__GPIO_2_1 MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_GPIO) | ||
| 324 | #define MX23_PAD_SSP1_DATA0__GPIO_2_2 MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_GPIO) | ||
| 325 | #define MX23_PAD_SSP1_DATA1__GPIO_2_3 MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_GPIO) | ||
| 326 | #define MX23_PAD_SSP1_DATA2__GPIO_2_4 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_GPIO) | ||
| 327 | #define MX23_PAD_SSP1_DATA3__GPIO_2_5 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_GPIO) | ||
| 328 | #define MX23_PAD_SSP1_SCK__GPIO_2_6 MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_GPIO) | ||
| 329 | #define MX23_PAD_ROTARYA__GPIO_2_7 MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_GPIO) | ||
| 330 | #define MX23_PAD_ROTARYB__GPIO_2_8 MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_GPIO) | ||
| 331 | #define MX23_PAD_EMI_A00__GPIO_2_9 MXS_IOMUX_PAD_NAKED(2, 9, PAD_MUXSEL_GPIO) | ||
| 332 | #define MX23_PAD_EMI_A01__GPIO_2_10 MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_GPIO) | ||
| 333 | #define MX23_PAD_EMI_A02__GPIO_2_11 MXS_IOMUX_PAD_NAKED(2, 11, PAD_MUXSEL_GPIO) | ||
| 334 | #define MX23_PAD_EMI_A03__GPIO_2_12 MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_GPIO) | ||
| 335 | #define MX23_PAD_EMI_A04__GPIO_2_13 MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_GPIO) | ||
| 336 | #define MX23_PAD_EMI_A05__GPIO_2_14 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_GPIO) | ||
| 337 | #define MX23_PAD_EMI_A06__GPIO_2_15 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_GPIO) | ||
| 338 | #define MX23_PAD_EMI_A07__GPIO_2_16 MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_GPIO) | ||
| 339 | #define MX23_PAD_EMI_A08__GPIO_2_17 MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_GPIO) | ||
| 340 | #define MX23_PAD_EMI_A09__GPIO_2_18 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_GPIO) | ||
| 341 | #define MX23_PAD_EMI_A10__GPIO_2_19 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_GPIO) | ||
| 342 | #define MX23_PAD_EMI_A11__GPIO_2_20 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_GPIO) | ||
| 343 | #define MX23_PAD_EMI_A12__GPIO_2_21 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_GPIO) | ||
| 344 | #define MX23_PAD_EMI_BA0__GPIO_2_22 MXS_IOMUX_PAD_NAKED(2, 22, PAD_MUXSEL_GPIO) | ||
| 345 | #define MX23_PAD_EMI_BA1__GPIO_2_23 MXS_IOMUX_PAD_NAKED(2, 23, PAD_MUXSEL_GPIO) | ||
| 346 | #define MX23_PAD_EMI_CASN__GPIO_2_24 MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_GPIO) | ||
| 347 | #define MX23_PAD_EMI_CE0N__GPIO_2_25 MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_GPIO) | ||
| 348 | #define MX23_PAD_EMI_CE1N__GPIO_2_26 MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_GPIO) | ||
| 349 | #define MX23_PAD_GPMI_CE1N__GPIO_2_27 MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_GPIO) | ||
| 350 | #define MX23_PAD_GPMI_CE0N__GPIO_2_28 MXS_IOMUX_PAD_NAKED(2, 28, PAD_MUXSEL_GPIO) | ||
| 351 | #define MX23_PAD_EMI_CKE__GPIO_2_29 MXS_IOMUX_PAD_NAKED(2, 29, PAD_MUXSEL_GPIO) | ||
| 352 | #define MX23_PAD_EMI_RASN__GPIO_2_30 MXS_IOMUX_PAD_NAKED(2, 30, PAD_MUXSEL_GPIO) | ||
| 353 | #define MX23_PAD_EMI_WEN__GPIO_2_31 MXS_IOMUX_PAD_NAKED(2, 31, PAD_MUXSEL_GPIO) | ||
| 354 | |||
| 355 | #endif /* __MACH_IOMUX_MX23_H__ */ | ||
diff --git a/arch/arm/mach-mxs/include/mach/iomux-mx28.h b/arch/arm/mach-mxs/include/mach/iomux-mx28.h deleted file mode 100644 index f50fefd10520..000000000000 --- a/arch/arm/mach-mxs/include/mach/iomux-mx28.h +++ /dev/null | |||
| @@ -1,537 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com> | ||
| 3 | * Copyright (C) 2010 Freescale Semiconductor, Inc. | ||
| 4 | * | ||
| 5 | * The code contained herein is licensed under the GNU General Public | ||
| 6 | * License. You may obtain a copy of the GNU General Public License | ||
| 7 | * Version 2 or later at the following locations: | ||
| 8 | * | ||
| 9 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 10 | * http://www.gnu.org/copyleft/gpl.html | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __MACH_IOMUX_MX28_H__ | ||
| 14 | #define __MACH_IOMUX_MX28_H__ | ||
| 15 | |||
| 16 | #include <mach/iomux.h> | ||
| 17 | |||
| 18 | /* | ||
| 19 | * The naming convention for the pad modes is MX28_PAD_<padname>__<padmode> | ||
| 20 | * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num> | ||
| 21 | * See also iomux.h | ||
| 22 | * | ||
| 23 | * BANK PIN MUX | ||
| 24 | */ | ||
| 25 | /* MUXSEL_0 */ | ||
| 26 | #define MX28_PAD_GPMI_D00__GPMI_D0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_0) | ||
| 27 | #define MX28_PAD_GPMI_D01__GPMI_D1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_0) | ||
| 28 | #define MX28_PAD_GPMI_D02__GPMI_D2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_0) | ||
| 29 | #define MX28_PAD_GPMI_D03__GPMI_D3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_0) | ||
| 30 | #define MX28_PAD_GPMI_D04__GPMI_D4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_0) | ||
| 31 | #define MX28_PAD_GPMI_D05__GPMI_D5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_0) | ||
| 32 | #define MX28_PAD_GPMI_D06__GPMI_D6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_0) | ||
| 33 | #define MX28_PAD_GPMI_D07__GPMI_D7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_0) | ||
| 34 | #define MX28_PAD_GPMI_CE0N__GPMI_CE0N MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_0) | ||
| 35 | #define MX28_PAD_GPMI_CE1N__GPMI_CE1N MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_0) | ||
| 36 | #define MX28_PAD_GPMI_CE2N__GPMI_CE2N MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_0) | ||
| 37 | #define MX28_PAD_GPMI_CE3N__GPMI_CE3N MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_0) | ||
| 38 | #define MX28_PAD_GPMI_RDY0__GPMI_READY0 MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_0) | ||
| 39 | #define MX28_PAD_GPMI_RDY1__GPMI_READY1 MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_0) | ||
| 40 | #define MX28_PAD_GPMI_RDY2__GPMI_READY2 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_0) | ||
| 41 | #define MX28_PAD_GPMI_RDY3__GPMI_READY3 MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_0) | ||
| 42 | #define MX28_PAD_GPMI_RDN__GPMI_RDN MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_0) | ||
| 43 | #define MX28_PAD_GPMI_WRN__GPMI_WRN MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_0) | ||
| 44 | #define MX28_PAD_GPMI_ALE__GPMI_ALE MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_0) | ||
| 45 | #define MX28_PAD_GPMI_CLE__GPMI_CLE MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_0) | ||
| 46 | #define MX28_PAD_GPMI_RESETN__GPMI_RESETN MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_0) | ||
| 47 | |||
| 48 | #define MX28_PAD_LCD_D00__LCD_D0 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_0) | ||
| 49 | #define MX28_PAD_LCD_D01__LCD_D1 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_0) | ||
| 50 | #define MX28_PAD_LCD_D02__LCD_D2 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_0) | ||
| 51 | #define MX28_PAD_LCD_D03__LCD_D3 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_0) | ||
| 52 | #define MX28_PAD_LCD_D04__LCD_D4 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_0) | ||
| 53 | #define MX28_PAD_LCD_D05__LCD_D5 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_0) | ||
| 54 | #define MX28_PAD_LCD_D06__LCD_D6 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_0) | ||
| 55 | #define MX28_PAD_LCD_D07__LCD_D7 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_0) | ||
| 56 | #define MX28_PAD_LCD_D08__LCD_D8 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_0) | ||
| 57 | #define MX28_PAD_LCD_D09__LCD_D9 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_0) | ||
| 58 | #define MX28_PAD_LCD_D10__LCD_D10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_0) | ||
| 59 | #define MX28_PAD_LCD_D11__LCD_D11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_0) | ||
| 60 | #define MX28_PAD_LCD_D12__LCD_D12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_0) | ||
| 61 | #define MX28_PAD_LCD_D13__LCD_D13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_0) | ||
| 62 | #define MX28_PAD_LCD_D14__LCD_D14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_0) | ||
| 63 | #define MX28_PAD_LCD_D15__LCD_D15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_0) | ||
| 64 | #define MX28_PAD_LCD_D16__LCD_D16 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_0) | ||
| 65 | #define MX28_PAD_LCD_D17__LCD_D17 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_0) | ||
| 66 | #define MX28_PAD_LCD_D18__LCD_D18 MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_0) | ||
| 67 | #define MX28_PAD_LCD_D19__LCD_D19 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_0) | ||
| 68 | #define MX28_PAD_LCD_D20__LCD_D20 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_0) | ||
| 69 | #define MX28_PAD_LCD_D21__LCD_D21 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_0) | ||
| 70 | #define MX28_PAD_LCD_D22__LCD_D22 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_0) | ||
| 71 | #define MX28_PAD_LCD_D23__LCD_D23 MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_0) | ||
| 72 | #define MX28_PAD_LCD_RD_E__LCD_RD_E MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_0) | ||
| 73 | #define MX28_PAD_LCD_WR_RWN__LCD_WR_RWN MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_0) | ||
| 74 | #define MX28_PAD_LCD_RS__LCD_RS MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_0) | ||
| 75 | #define MX28_PAD_LCD_CS__LCD_CS MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_0) | ||
| 76 | #define MX28_PAD_LCD_VSYNC__LCD_VSYNC MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_0) | ||
| 77 | #define MX28_PAD_LCD_HSYNC__LCD_HSYNC MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_0) | ||
| 78 | #define MX28_PAD_LCD_DOTCLK__LCD_DOTCLK MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_0) | ||
| 79 | #define MX28_PAD_LCD_ENABLE__LCD_ENABLE MXS_IOMUX_PAD_NAKED(1, 31, PAD_MUXSEL_0) | ||
| 80 | |||
| 81 | #define MX28_PAD_SSP0_DATA0__SSP0_D0 MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_0) | ||
| 82 | #define MX28_PAD_SSP0_DATA1__SSP0_D1 MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_0) | ||
| 83 | #define MX28_PAD_SSP0_DATA2__SSP0_D2 MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_0) | ||
| 84 | #define MX28_PAD_SSP0_DATA3__SSP0_D3 MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_0) | ||
| 85 | #define MX28_PAD_SSP0_DATA4__SSP0_D4 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_0) | ||
| 86 | #define MX28_PAD_SSP0_DATA5__SSP0_D5 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_0) | ||
| 87 | #define MX28_PAD_SSP0_DATA6__SSP0_D6 MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_0) | ||
| 88 | #define MX28_PAD_SSP0_DATA7__SSP0_D7 MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_0) | ||
| 89 | #define MX28_PAD_SSP0_CMD__SSP0_CMD MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_0) | ||
| 90 | #define MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT MXS_IOMUX_PAD_NAKED(2, 9, PAD_MUXSEL_0) | ||
| 91 | #define MX28_PAD_SSP0_SCK__SSP0_SCK MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_0) | ||
| 92 | #define MX28_PAD_SSP1_SCK__SSP1_SCK MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_0) | ||
| 93 | #define MX28_PAD_SSP1_CMD__SSP1_CMD MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_0) | ||
| 94 | #define MX28_PAD_SSP1_DATA0__SSP1_D0 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_0) | ||
| 95 | #define MX28_PAD_SSP1_DATA3__SSP1_D3 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_0) | ||
| 96 | #define MX28_PAD_SSP2_SCK__SSP2_SCK MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_0) | ||
| 97 | #define MX28_PAD_SSP2_MOSI__SSP2_CMD MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_0) | ||
| 98 | #define MX28_PAD_SSP2_MISO__SSP2_D0 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_0) | ||
| 99 | #define MX28_PAD_SSP2_SS0__SSP2_D3 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_0) | ||
| 100 | #define MX28_PAD_SSP2_SS1__SSP2_D4 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_0) | ||
| 101 | #define MX28_PAD_SSP2_SS2__SSP2_D5 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_0) | ||
| 102 | #define MX28_PAD_SSP3_SCK__SSP3_SCK MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_0) | ||
| 103 | #define MX28_PAD_SSP3_MOSI__SSP3_CMD MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_0) | ||
| 104 | #define MX28_PAD_SSP3_MISO__SSP3_D0 MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_0) | ||
| 105 | #define MX28_PAD_SSP3_SS0__SSP3_D3 MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_0) | ||
| 106 | |||
| 107 | #define MX28_PAD_AUART0_RX__AUART0_RX MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_0) | ||
| 108 | #define MX28_PAD_AUART0_TX__AUART0_TX MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_0) | ||
| 109 | #define MX28_PAD_AUART0_CTS__AUART0_CTS MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_0) | ||
| 110 | #define MX28_PAD_AUART0_RTS__AUART0_RTS MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_0) | ||
| 111 | #define MX28_PAD_AUART1_RX__AUART1_RX MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_0) | ||
| 112 | #define MX28_PAD_AUART1_TX__AUART1_TX MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_0) | ||
| 113 | #define MX28_PAD_AUART1_CTS__AUART1_CTS MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_0) | ||
| 114 | #define MX28_PAD_AUART1_RTS__AUART1_RTS MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_0) | ||
| 115 | #define MX28_PAD_AUART2_RX__AUART2_RX MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_0) | ||
| 116 | #define MX28_PAD_AUART2_TX__AUART2_TX MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_0) | ||
| 117 | #define MX28_PAD_AUART2_CTS__AUART2_CTS MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_0) | ||
| 118 | #define MX28_PAD_AUART2_RTS__AUART2_RTS MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_0) | ||
| 119 | #define MX28_PAD_AUART3_RX__AUART3_RX MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_0) | ||
| 120 | #define MX28_PAD_AUART3_TX__AUART3_TX MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_0) | ||
| 121 | #define MX28_PAD_AUART3_CTS__AUART3_CTS MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_0) | ||
| 122 | #define MX28_PAD_AUART3_RTS__AUART3_RTS MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_0) | ||
| 123 | #define MX28_PAD_PWM0__PWM_0 MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_0) | ||
| 124 | #define MX28_PAD_PWM1__PWM_1 MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_0) | ||
| 125 | #define MX28_PAD_PWM2__PWM_2 MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_0) | ||
| 126 | #define MX28_PAD_SAIF0_MCLK__SAIF0_MCLK MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_0) | ||
| 127 | #define MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_0) | ||
| 128 | #define MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_0) | ||
| 129 | #define MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_0) | ||
| 130 | #define MX28_PAD_I2C0_SCL__I2C0_SCL MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_0) | ||
| 131 | #define MX28_PAD_I2C0_SDA__I2C0_SDA MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_0) | ||
| 132 | #define MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_0) | ||
| 133 | #define MX28_PAD_SPDIF__SPDIF_TX MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_0) | ||
| 134 | #define MX28_PAD_PWM3__PWM_3 MXS_IOMUX_PAD_NAKED(3, 28, PAD_MUXSEL_0) | ||
| 135 | #define MX28_PAD_PWM4__PWM_4 MXS_IOMUX_PAD_NAKED(3, 29, PAD_MUXSEL_0) | ||
| 136 | #define MX28_PAD_LCD_RESET__LCD_RESET MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_0) | ||
| 137 | |||
| 138 | #define MX28_PAD_ENET0_MDC__ENET0_MDC MXS_IOMUX_PAD_NAKED(4, 0, PAD_MUXSEL_0) | ||
| 139 | #define MX28_PAD_ENET0_MDIO__ENET0_MDIO MXS_IOMUX_PAD_NAKED(4, 1, PAD_MUXSEL_0) | ||
| 140 | #define MX28_PAD_ENET0_RX_EN__ENET0_RX_EN MXS_IOMUX_PAD_NAKED(4, 2, PAD_MUXSEL_0) | ||
| 141 | #define MX28_PAD_ENET0_RXD0__ENET0_RXD0 MXS_IOMUX_PAD_NAKED(4, 3, PAD_MUXSEL_0) | ||
| 142 | #define MX28_PAD_ENET0_RXD1__ENET0_RXD1 MXS_IOMUX_PAD_NAKED(4, 4, PAD_MUXSEL_0) | ||
| 143 | #define MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK MXS_IOMUX_PAD_NAKED(4, 5, PAD_MUXSEL_0) | ||
| 144 | #define MX28_PAD_ENET0_TX_EN__ENET0_TX_EN MXS_IOMUX_PAD_NAKED(4, 6, PAD_MUXSEL_0) | ||
| 145 | #define MX28_PAD_ENET0_TXD0__ENET0_TXD0 MXS_IOMUX_PAD_NAKED(4, 7, PAD_MUXSEL_0) | ||
| 146 | #define MX28_PAD_ENET0_TXD1__ENET0_TXD1 MXS_IOMUX_PAD_NAKED(4, 8, PAD_MUXSEL_0) | ||
| 147 | #define MX28_PAD_ENET0_RXD2__ENET0_RXD2 MXS_IOMUX_PAD_NAKED(4, 9, PAD_MUXSEL_0) | ||
| 148 | #define MX28_PAD_ENET0_RXD3__ENET0_RXD3 MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_0) | ||
| 149 | #define MX28_PAD_ENET0_TXD2__ENET0_TXD2 MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_0) | ||
| 150 | #define MX28_PAD_ENET0_TXD3__ENET0_TXD3 MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_0) | ||
| 151 | #define MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_0) | ||
| 152 | #define MX28_PAD_ENET0_COL__ENET0_COL MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_0) | ||
| 153 | #define MX28_PAD_ENET0_CRS__ENET0_CRS MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_0) | ||
| 154 | #define MX28_PAD_ENET_CLK__CLKCTRL_ENET MXS_IOMUX_PAD_NAKED(4, 16, PAD_MUXSEL_0) | ||
| 155 | #define MX28_PAD_JTAG_RTCK__JTAG_RTCK MXS_IOMUX_PAD_NAKED(4, 20, PAD_MUXSEL_0) | ||
| 156 | |||
| 157 | #define MX28_PAD_EMI_D00__EMI_DATA0 MXS_IOMUX_PAD_NAKED(5, 0, PAD_MUXSEL_0) | ||
| 158 | #define MX28_PAD_EMI_D01__EMI_DATA1 MXS_IOMUX_PAD_NAKED(5, 1, PAD_MUXSEL_0) | ||
| 159 | #define MX28_PAD_EMI_D02__EMI_DATA2 MXS_IOMUX_PAD_NAKED(5, 2, PAD_MUXSEL_0) | ||
| 160 | #define MX28_PAD_EMI_D03__EMI_DATA3 MXS_IOMUX_PAD_NAKED(5, 3, PAD_MUXSEL_0) | ||
| 161 | #define MX28_PAD_EMI_D04__EMI_DATA4 MXS_IOMUX_PAD_NAKED(5, 4, PAD_MUXSEL_0) | ||
| 162 | #define MX28_PAD_EMI_D05__EMI_DATA5 MXS_IOMUX_PAD_NAKED(5, 5, PAD_MUXSEL_0) | ||
| 163 | #define MX28_PAD_EMI_D06__EMI_DATA6 MXS_IOMUX_PAD_NAKED(5, 6, PAD_MUXSEL_0) | ||
| 164 | #define MX28_PAD_EMI_D07__EMI_DATA7 MXS_IOMUX_PAD_NAKED(5, 7, PAD_MUXSEL_0) | ||
| 165 | #define MX28_PAD_EMI_D08__EMI_DATA8 MXS_IOMUX_PAD_NAKED(5, 8, PAD_MUXSEL_0) | ||
| 166 | #define MX28_PAD_EMI_D09__EMI_DATA9 MXS_IOMUX_PAD_NAKED(5, 9, PAD_MUXSEL_0) | ||
| 167 | #define MX28_PAD_EMI_D10__EMI_DATA10 MXS_IOMUX_PAD_NAKED(5, 10, PAD_MUXSEL_0) | ||
| 168 | #define MX28_PAD_EMI_D11__EMI_DATA11 MXS_IOMUX_PAD_NAKED(5, 11, PAD_MUXSEL_0) | ||
| 169 | #define MX28_PAD_EMI_D12__EMI_DATA12 MXS_IOMUX_PAD_NAKED(5, 12, PAD_MUXSEL_0) | ||
| 170 | #define MX28_PAD_EMI_D13__EMI_DATA13 MXS_IOMUX_PAD_NAKED(5, 13, PAD_MUXSEL_0) | ||
| 171 | #define MX28_PAD_EMI_D14__EMI_DATA14 MXS_IOMUX_PAD_NAKED(5, 14, PAD_MUXSEL_0) | ||
| 172 | #define MX28_PAD_EMI_D15__EMI_DATA15 MXS_IOMUX_PAD_NAKED(5, 15, PAD_MUXSEL_0) | ||
| 173 | #define MX28_PAD_EMI_ODT0__EMI_ODT0 MXS_IOMUX_PAD_NAKED(5, 16, PAD_MUXSEL_0) | ||
| 174 | #define MX28_PAD_EMI_DQM0__EMI_DQM0 MXS_IOMUX_PAD_NAKED(5, 17, PAD_MUXSEL_0) | ||
| 175 | #define MX28_PAD_EMI_ODT1__EMI_ODT1 MXS_IOMUX_PAD_NAKED(5, 18, PAD_MUXSEL_0) | ||
| 176 | #define MX28_PAD_EMI_DQM1__EMI_DQM1 MXS_IOMUX_PAD_NAKED(5, 19, PAD_MUXSEL_0) | ||
| 177 | #define MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK MXS_IOMUX_PAD_NAKED(5, 20, PAD_MUXSEL_0) | ||
| 178 | #define MX28_PAD_EMI_CLK__EMI_CLK MXS_IOMUX_PAD_NAKED(5, 21, PAD_MUXSEL_0) | ||
| 179 | #define MX28_PAD_EMI_DQS0__EMI_DQS0 MXS_IOMUX_PAD_NAKED(5, 22, PAD_MUXSEL_0) | ||
| 180 | #define MX28_PAD_EMI_DQS1__EMI_DQS1 MXS_IOMUX_PAD_NAKED(5, 23, PAD_MUXSEL_0) | ||
| 181 | #define MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN MXS_IOMUX_PAD_NAKED(5, 26, PAD_MUXSEL_0) | ||
| 182 | |||
| 183 | #define MX28_PAD_EMI_A00__EMI_ADDR0 MXS_IOMUX_PAD_NAKED(6, 0, PAD_MUXSEL_0) | ||
| 184 | #define MX28_PAD_EMI_A01__EMI_ADDR1 MXS_IOMUX_PAD_NAKED(6, 1, PAD_MUXSEL_0) | ||
| 185 | #define MX28_PAD_EMI_A02__EMI_ADDR2 MXS_IOMUX_PAD_NAKED(6, 2, PAD_MUXSEL_0) | ||
| 186 | #define MX28_PAD_EMI_A03__EMI_ADDR3 MXS_IOMUX_PAD_NAKED(6, 3, PAD_MUXSEL_0) | ||
| 187 | #define MX28_PAD_EMI_A04__EMI_ADDR4 MXS_IOMUX_PAD_NAKED(6, 4, PAD_MUXSEL_0) | ||
| 188 | #define MX28_PAD_EMI_A05__EMI_ADDR5 MXS_IOMUX_PAD_NAKED(6, 5, PAD_MUXSEL_0) | ||
| 189 | #define MX28_PAD_EMI_A06__EMI_ADDR6 MXS_IOMUX_PAD_NAKED(6, 6, PAD_MUXSEL_0) | ||
| 190 | #define MX28_PAD_EMI_A07__EMI_ADDR7 MXS_IOMUX_PAD_NAKED(6, 7, PAD_MUXSEL_0) | ||
| 191 | #define MX28_PAD_EMI_A08__EMI_ADDR8 MXS_IOMUX_PAD_NAKED(6, 8, PAD_MUXSEL_0) | ||
| 192 | #define MX28_PAD_EMI_A09__EMI_ADDR9 MXS_IOMUX_PAD_NAKED(6, 9, PAD_MUXSEL_0) | ||
| 193 | #define MX28_PAD_EMI_A10__EMI_ADDR10 MXS_IOMUX_PAD_NAKED(6, 10, PAD_MUXSEL_0) | ||
| 194 | #define MX28_PAD_EMI_A11__EMI_ADDR11 MXS_IOMUX_PAD_NAKED(6, 11, PAD_MUXSEL_0) | ||
| 195 | #define MX28_PAD_EMI_A12__EMI_ADDR12 MXS_IOMUX_PAD_NAKED(6, 12, PAD_MUXSEL_0) | ||
| 196 | #define MX28_PAD_EMI_A13__EMI_ADDR13 MXS_IOMUX_PAD_NAKED(6, 13, PAD_MUXSEL_0) | ||
| 197 | #define MX28_PAD_EMI_A14__EMI_ADDR14 MXS_IOMUX_PAD_NAKED(6, 14, PAD_MUXSEL_0) | ||
| 198 | #define MX28_PAD_EMI_BA0__EMI_BA0 MXS_IOMUX_PAD_NAKED(6, 16, PAD_MUXSEL_0) | ||
| 199 | #define MX28_PAD_EMI_BA1__EMI_BA1 MXS_IOMUX_PAD_NAKED(6, 17, PAD_MUXSEL_0) | ||
| 200 | #define MX28_PAD_EMI_BA2__EMI_BA2 MXS_IOMUX_PAD_NAKED(6, 18, PAD_MUXSEL_0) | ||
| 201 | #define MX28_PAD_EMI_CASN__EMI_CASN MXS_IOMUX_PAD_NAKED(6, 19, PAD_MUXSEL_0) | ||
| 202 | #define MX28_PAD_EMI_RASN__EMI_RASN MXS_IOMUX_PAD_NAKED(6, 20, PAD_MUXSEL_0) | ||
| 203 | #define MX28_PAD_EMI_WEN__EMI_WEN MXS_IOMUX_PAD_NAKED(6, 21, PAD_MUXSEL_0) | ||
| 204 | #define MX28_PAD_EMI_CE0N__EMI_CE0N MXS_IOMUX_PAD_NAKED(6, 22, PAD_MUXSEL_0) | ||
| 205 | #define MX28_PAD_EMI_CE1N__EMI_CE1N MXS_IOMUX_PAD_NAKED(6, 23, PAD_MUXSEL_0) | ||
| 206 | #define MX28_PAD_EMI_CKE__EMI_CKE MXS_IOMUX_PAD_NAKED(6, 24, PAD_MUXSEL_0) | ||
| 207 | |||
| 208 | /* MUXSEL_1 */ | ||
| 209 | #define MX28_PAD_GPMI_D00__SSP1_D0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_1) | ||
| 210 | #define MX28_PAD_GPMI_D01__SSP1_D1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_1) | ||
| 211 | #define MX28_PAD_GPMI_D02__SSP1_D2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_1) | ||
| 212 | #define MX28_PAD_GPMI_D03__SSP1_D3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_1) | ||
| 213 | #define MX28_PAD_GPMI_D04__SSP1_D4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_1) | ||
| 214 | #define MX28_PAD_GPMI_D05__SSP1_D5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_1) | ||
| 215 | #define MX28_PAD_GPMI_D06__SSP1_D6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_1) | ||
| 216 | #define MX28_PAD_GPMI_D07__SSP1_D7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_1) | ||
| 217 | #define MX28_PAD_GPMI_CE0N__SSP3_D0 MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_1) | ||
| 218 | #define MX28_PAD_GPMI_CE1N__SSP3_D3 MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_1) | ||
| 219 | #define MX28_PAD_GPMI_CE2N__CAN1_TX MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_1) | ||
| 220 | #define MX28_PAD_GPMI_CE3N__CAN1_RX MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_1) | ||
| 221 | #define MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_1) | ||
| 222 | #define MX28_PAD_GPMI_RDY1__SSP1_CMD MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_1) | ||
| 223 | #define MX28_PAD_GPMI_RDY2__CAN0_TX MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_1) | ||
| 224 | #define MX28_PAD_GPMI_RDY3__CAN0_RX MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_1) | ||
| 225 | #define MX28_PAD_GPMI_RDN__SSP3_SCK MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_1) | ||
| 226 | #define MX28_PAD_GPMI_WRN__SSP1_SCK MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_1) | ||
| 227 | #define MX28_PAD_GPMI_ALE__SSP3_D1 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_1) | ||
| 228 | #define MX28_PAD_GPMI_CLE__SSP3_D2 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_1) | ||
| 229 | #define MX28_PAD_GPMI_RESETN__SSP3_CMD MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_1) | ||
| 230 | |||
| 231 | #define MX28_PAD_LCD_D03__ETM_DA8 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_1) | ||
| 232 | #define MX28_PAD_LCD_D04__ETM_DA9 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_1) | ||
| 233 | #define MX28_PAD_LCD_D08__ETM_DA3 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_1) | ||
| 234 | #define MX28_PAD_LCD_D09__ETM_DA4 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_1) | ||
| 235 | #define MX28_PAD_LCD_D20__ENET1_1588_EVENT2_OUT MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_1) | ||
| 236 | #define MX28_PAD_LCD_D21__ENET1_1588_EVENT2_IN MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_1) | ||
| 237 | #define MX28_PAD_LCD_D22__ENET1_1588_EVENT3_OUT MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_1) | ||
| 238 | #define MX28_PAD_LCD_D23__ENET1_1588_EVENT3_IN MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_1) | ||
| 239 | #define MX28_PAD_LCD_RD_E__LCD_VSYNC MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_1) | ||
| 240 | #define MX28_PAD_LCD_WR_RWN__LCD_HSYNC MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_1) | ||
| 241 | #define MX28_PAD_LCD_RS__LCD_DOTCLK MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_1) | ||
| 242 | #define MX28_PAD_LCD_CS__LCD_ENABLE MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_1) | ||
| 243 | #define MX28_PAD_LCD_VSYNC__SAIF1_SDATA0 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_1) | ||
| 244 | #define MX28_PAD_LCD_HSYNC__SAIF1_SDATA1 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_1) | ||
| 245 | #define MX28_PAD_LCD_DOTCLK__SAIF1_MCLK MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_1) | ||
| 246 | |||
| 247 | #define MX28_PAD_SSP0_DATA4__SSP2_D0 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_1) | ||
| 248 | #define MX28_PAD_SSP0_DATA5__SSP2_D3 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_1) | ||
| 249 | #define MX28_PAD_SSP0_DATA6__SSP2_CMD MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_1) | ||
| 250 | #define MX28_PAD_SSP0_DATA7__SSP2_SCK MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_1) | ||
| 251 | #define MX28_PAD_SSP1_SCK__SSP2_D1 MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_1) | ||
| 252 | #define MX28_PAD_SSP1_CMD__SSP2_D2 MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_1) | ||
| 253 | #define MX28_PAD_SSP1_DATA0__SSP2_D6 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_1) | ||
| 254 | #define MX28_PAD_SSP1_DATA3__SSP2_D7 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_1) | ||
| 255 | #define MX28_PAD_SSP2_SCK__AUART2_RX MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_1) | ||
| 256 | #define MX28_PAD_SSP2_MOSI__AUART2_TX MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_1) | ||
| 257 | #define MX28_PAD_SSP2_MISO__AUART3_RX MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_1) | ||
| 258 | #define MX28_PAD_SSP2_SS0__AUART3_TX MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_1) | ||
| 259 | #define MX28_PAD_SSP2_SS1__SSP2_D1 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_1) | ||
| 260 | #define MX28_PAD_SSP2_SS2__SSP2_D2 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_1) | ||
| 261 | #define MX28_PAD_SSP3_SCK__AUART4_TX MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_1) | ||
| 262 | #define MX28_PAD_SSP3_MOSI__AUART4_RX MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_1) | ||
| 263 | #define MX28_PAD_SSP3_MISO__AUART4_RTS MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_1) | ||
| 264 | #define MX28_PAD_SSP3_SS0__AUART4_CTS MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_1) | ||
| 265 | |||
| 266 | #define MX28_PAD_AUART0_RX__I2C0_SCL MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_1) | ||
| 267 | #define MX28_PAD_AUART0_TX__I2C0_SDA MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_1) | ||
| 268 | #define MX28_PAD_AUART0_CTS__AUART4_RX MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_1) | ||
| 269 | #define MX28_PAD_AUART0_RTS__AUART4_TX MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_1) | ||
| 270 | #define MX28_PAD_AUART1_RX__SSP2_CARD_DETECT MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_1) | ||
| 271 | #define MX28_PAD_AUART1_TX__SSP3_CARD_DETECT MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_1) | ||
| 272 | #define MX28_PAD_AUART1_CTS__USB0_OVERCURRENT MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_1) | ||
| 273 | #define MX28_PAD_AUART1_RTS__USB0_ID MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_1) | ||
| 274 | #define MX28_PAD_AUART2_RX__SSP3_D1 MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_1) | ||
| 275 | #define MX28_PAD_AUART2_TX__SSP3_D2 MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_1) | ||
| 276 | #define MX28_PAD_AUART2_CTS__I2C1_SCL MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_1) | ||
| 277 | #define MX28_PAD_AUART2_RTS__I2C1_SDA MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_1) | ||
| 278 | #define MX28_PAD_AUART3_RX__CAN0_TX MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_1) | ||
| 279 | #define MX28_PAD_AUART3_TX__CAN0_RX MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_1) | ||
| 280 | #define MX28_PAD_AUART3_CTS__CAN1_TX MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_1) | ||
| 281 | #define MX28_PAD_AUART3_RTS__CAN1_RX MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_1) | ||
| 282 | #define MX28_PAD_PWM0__I2C1_SCL MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_1) | ||
| 283 | #define MX28_PAD_PWM1__I2C1_SDA MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_1) | ||
| 284 | #define MX28_PAD_PWM2__USB0_ID MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_1) | ||
| 285 | #define MX28_PAD_SAIF0_MCLK__PWM_3 MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_1) | ||
| 286 | #define MX28_PAD_SAIF0_LRCLK__PWM_4 MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_1) | ||
| 287 | #define MX28_PAD_SAIF0_BITCLK__PWM_5 MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_1) | ||
| 288 | #define MX28_PAD_SAIF0_SDATA0__PWM_6 MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_1) | ||
| 289 | #define MX28_PAD_I2C0_SCL__TIMROT_ROTARYA MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_1) | ||
| 290 | #define MX28_PAD_I2C0_SDA__TIMROT_ROTARYB MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_1) | ||
| 291 | #define MX28_PAD_SAIF1_SDATA0__PWM_7 MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_1) | ||
| 292 | #define MX28_PAD_LCD_RESET__LCD_VSYNC MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_1) | ||
| 293 | |||
| 294 | #define MX28_PAD_ENET0_MDC__GPMI_CE4N MXS_IOMUX_PAD_NAKED(4, 0, PAD_MUXSEL_1) | ||
| 295 | #define MX28_PAD_ENET0_MDIO__GPMI_CE5N MXS_IOMUX_PAD_NAKED(4, 1, PAD_MUXSEL_1) | ||
| 296 | #define MX28_PAD_ENET0_RX_EN__GPMI_CE6N MXS_IOMUX_PAD_NAKED(4, 2, PAD_MUXSEL_1) | ||
| 297 | #define MX28_PAD_ENET0_RXD0__GPMI_CE7N MXS_IOMUX_PAD_NAKED(4, 3, PAD_MUXSEL_1) | ||
| 298 | #define MX28_PAD_ENET0_RXD1__GPMI_READY4 MXS_IOMUX_PAD_NAKED(4, 4, PAD_MUXSEL_1) | ||
| 299 | #define MX28_PAD_ENET0_TX_CLK__HSADC_TRIGGER MXS_IOMUX_PAD_NAKED(4, 5, PAD_MUXSEL_1) | ||
| 300 | #define MX28_PAD_ENET0_TX_EN__GPMI_READY5 MXS_IOMUX_PAD_NAKED(4, 6, PAD_MUXSEL_1) | ||
| 301 | #define MX28_PAD_ENET0_TXD0__GPMI_READY6 MXS_IOMUX_PAD_NAKED(4, 7, PAD_MUXSEL_1) | ||
| 302 | #define MX28_PAD_ENET0_TXD1__GPMI_READY7 MXS_IOMUX_PAD_NAKED(4, 8, PAD_MUXSEL_1) | ||
| 303 | #define MX28_PAD_ENET0_RXD2__ENET1_RXD0 MXS_IOMUX_PAD_NAKED(4, 9, PAD_MUXSEL_1) | ||
| 304 | #define MX28_PAD_ENET0_RXD3__ENET1_RXD1 MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_1) | ||
| 305 | #define MX28_PAD_ENET0_TXD2__ENET1_TXD0 MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_1) | ||
| 306 | #define MX28_PAD_ENET0_TXD3__ENET1_TXD1 MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_1) | ||
| 307 | #define MX28_PAD_ENET0_RX_CLK__ENET0_RX_ER MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_1) | ||
| 308 | #define MX28_PAD_ENET0_COL__ENET1_TX_EN MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_1) | ||
| 309 | #define MX28_PAD_ENET0_CRS__ENET1_RX_EN MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_1) | ||
| 310 | |||
| 311 | /* MUXSEL_2 */ | ||
| 312 | #define MX28_PAD_GPMI_CE2N__ENET0_RX_ER MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_2) | ||
| 313 | #define MX28_PAD_GPMI_CE3N__SAIF1_MCLK MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_2) | ||
| 314 | #define MX28_PAD_GPMI_RDY0__USB0_ID MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_2) | ||
| 315 | #define MX28_PAD_GPMI_RDY2__ENET0_TX_ER MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_2) | ||
| 316 | #define MX28_PAD_GPMI_RDY3__HSADC_TRIGGER MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_2) | ||
| 317 | #define MX28_PAD_GPMI_ALE__SSP3_D4 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_2) | ||
| 318 | #define MX28_PAD_GPMI_CLE__SSP3_D5 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_2) | ||
| 319 | |||
| 320 | #define MX28_PAD_LCD_D00__ETM_DA0 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_2) | ||
| 321 | #define MX28_PAD_LCD_D01__ETM_DA1 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_2) | ||
| 322 | #define MX28_PAD_LCD_D02__ETM_DA2 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_2) | ||
| 323 | #define MX28_PAD_LCD_D03__ETM_DA3 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_2) | ||
| 324 | #define MX28_PAD_LCD_D04__ETM_DA4 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_2) | ||
| 325 | #define MX28_PAD_LCD_D05__ETM_DA5 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_2) | ||
| 326 | #define MX28_PAD_LCD_D06__ETM_DA6 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_2) | ||
| 327 | #define MX28_PAD_LCD_D07__ETM_DA7 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_2) | ||
| 328 | #define MX28_PAD_LCD_D08__ETM_DA8 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_2) | ||
| 329 | #define MX28_PAD_LCD_D09__ETM_DA9 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_2) | ||
| 330 | #define MX28_PAD_LCD_D10__ETM_DA10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_2) | ||
| 331 | #define MX28_PAD_LCD_D11__ETM_DA11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_2) | ||
| 332 | #define MX28_PAD_LCD_D12__ETM_DA12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_2) | ||
| 333 | #define MX28_PAD_LCD_D13__ETM_DA13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_2) | ||
| 334 | #define MX28_PAD_LCD_D14__ETM_DA14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_2) | ||
| 335 | #define MX28_PAD_LCD_D15__ETM_DA15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_2) | ||
| 336 | #define MX28_PAD_LCD_D16__ETM_DA7 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_2) | ||
| 337 | #define MX28_PAD_LCD_D17__ETM_DA6 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_2) | ||
| 338 | #define MX28_PAD_LCD_D18__ETM_DA5 MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_2) | ||
| 339 | #define MX28_PAD_LCD_D19__ETM_DA4 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_2) | ||
| 340 | #define MX28_PAD_LCD_D20__ETM_DA3 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_2) | ||
| 341 | #define MX28_PAD_LCD_D21__ETM_DA2 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_2) | ||
| 342 | #define MX28_PAD_LCD_D22__ETM_DA1 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_2) | ||
| 343 | #define MX28_PAD_LCD_D23__ETM_DA0 MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_2) | ||
| 344 | #define MX28_PAD_LCD_RD_E__ETM_TCTL MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_2) | ||
| 345 | #define MX28_PAD_LCD_WR_RWN__ETM_TCLK MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_2) | ||
| 346 | #define MX28_PAD_LCD_HSYNC__ETM_TCTL MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_2) | ||
| 347 | #define MX28_PAD_LCD_DOTCLK__ETM_TCLK MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_2) | ||
| 348 | |||
| 349 | #define MX28_PAD_SSP1_SCK__ENET0_1588_EVENT2_OUT MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_2) | ||
| 350 | #define MX28_PAD_SSP1_CMD__ENET0_1588_EVENT2_IN MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_2) | ||
| 351 | #define MX28_PAD_SSP1_DATA0__ENET0_1588_EVENT3_OUT MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_2) | ||
| 352 | #define MX28_PAD_SSP1_DATA3__ENET0_1588_EVENT3_IN MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_2) | ||
| 353 | #define MX28_PAD_SSP2_SCK__SAIF0_SDATA1 MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_2) | ||
| 354 | #define MX28_PAD_SSP2_MOSI__SAIF0_SDATA2 MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_2) | ||
| 355 | #define MX28_PAD_SSP2_MISO__SAIF1_SDATA1 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_2) | ||
| 356 | #define MX28_PAD_SSP2_SS0__SAIF1_SDATA2 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_2) | ||
| 357 | #define MX28_PAD_SSP2_SS1__USB1_OVERCURRENT MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_2) | ||
| 358 | #define MX28_PAD_SSP2_SS2__USB0_OVERCURRENT MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_2) | ||
| 359 | #define MX28_PAD_SSP3_SCK__ENET1_1588_EVENT0_OUT MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_2) | ||
| 360 | #define MX28_PAD_SSP3_MOSI__ENET1_1588_EVENT0_IN MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_2) | ||
| 361 | #define MX28_PAD_SSP3_MISO__ENET1_1588_EVENT1_OUT MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_2) | ||
| 362 | #define MX28_PAD_SSP3_SS0__ENET1_1588_EVENT1_IN MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_2) | ||
| 363 | |||
| 364 | #define MX28_PAD_AUART0_RX__DUART_CTS MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_2) | ||
| 365 | #define MX28_PAD_AUART0_TX__DUART_RTS MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_2) | ||
| 366 | #define MX28_PAD_AUART0_CTS__DUART_RX MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_2) | ||
| 367 | #define MX28_PAD_AUART0_RTS__DUART_TX MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_2) | ||
| 368 | #define MX28_PAD_AUART1_RX__PWM_0 MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_2) | ||
| 369 | #define MX28_PAD_AUART1_TX__PWM_1 MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_2) | ||
| 370 | #define MX28_PAD_AUART1_CTS__TIMROT_ROTARYA MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_2) | ||
| 371 | #define MX28_PAD_AUART1_RTS__TIMROT_ROTARYB MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_2) | ||
| 372 | #define MX28_PAD_AUART2_RX__SSP3_D4 MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_2) | ||
| 373 | #define MX28_PAD_AUART2_TX__SSP3_D5 MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_2) | ||
| 374 | #define MX28_PAD_AUART2_CTS__SAIF1_BITCLK MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_2) | ||
| 375 | #define MX28_PAD_AUART2_RTS__SAIF1_LRCLK MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_2) | ||
| 376 | #define MX28_PAD_AUART3_RX__ENET0_1588_EVENT0_OUT MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_2) | ||
| 377 | #define MX28_PAD_AUART3_TX__ENET0_1588_EVENT0_IN MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_2) | ||
| 378 | #define MX28_PAD_AUART3_CTS__ENET0_1588_EVENT1_OUT MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_2) | ||
| 379 | #define MX28_PAD_AUART3_RTS__ENET0_1588_EVENT1_IN MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_2) | ||
| 380 | #define MX28_PAD_PWM0__DUART_RX MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_2) | ||
| 381 | #define MX28_PAD_PWM1__DUART_TX MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_2) | ||
| 382 | #define MX28_PAD_PWM2__USB1_OVERCURRENT MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_2) | ||
| 383 | #define MX28_PAD_SAIF0_MCLK__AUART4_CTS MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_2) | ||
| 384 | #define MX28_PAD_SAIF0_LRCLK__AUART4_RTS MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_2) | ||
| 385 | #define MX28_PAD_SAIF0_BITCLK__AUART4_RX MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_2) | ||
| 386 | #define MX28_PAD_SAIF0_SDATA0__AUART4_TX MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_2) | ||
| 387 | #define MX28_PAD_I2C0_SCL__DUART_RX MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_2) | ||
| 388 | #define MX28_PAD_I2C0_SDA__DUART_TX MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_2) | ||
| 389 | #define MX28_PAD_SAIF1_SDATA0__SAIF0_SDATA1 MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_2) | ||
| 390 | #define MX28_PAD_SPDIF__ENET1_RX_ER MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_2) | ||
| 391 | |||
| 392 | #define MX28_PAD_ENET0_MDC__SAIF0_SDATA1 MXS_IOMUX_PAD_NAKED(4, 0, PAD_MUXSEL_2) | ||
| 393 | #define MX28_PAD_ENET0_MDIO__SAIF0_SDATA2 MXS_IOMUX_PAD_NAKED(4, 1, PAD_MUXSEL_2) | ||
| 394 | #define MX28_PAD_ENET0_RX_EN__SAIF1_SDATA1 MXS_IOMUX_PAD_NAKED(4, 2, PAD_MUXSEL_2) | ||
| 395 | #define MX28_PAD_ENET0_RXD0__SAIF1_SDATA2 MXS_IOMUX_PAD_NAKED(4, 3, PAD_MUXSEL_2) | ||
| 396 | #define MX28_PAD_ENET0_TX_CLK__ENET0_1588_EVENT2_OUT MXS_IOMUX_PAD_NAKED(4, 5, PAD_MUXSEL_2) | ||
| 397 | #define MX28_PAD_ENET0_RXD2__ENET0_1588_EVENT0_OUT MXS_IOMUX_PAD_NAKED(4, 9, PAD_MUXSEL_2) | ||
| 398 | #define MX28_PAD_ENET0_RXD3__ENET0_1588_EVENT0_IN MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_2) | ||
| 399 | #define MX28_PAD_ENET0_TXD2__ENET0_1588_EVENT1_OUT MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_2) | ||
| 400 | #define MX28_PAD_ENET0_TXD3__ENET0_1588_EVENT1_IN MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_2) | ||
| 401 | #define MX28_PAD_ENET0_RX_CLK__ENET0_1588_EVENT2_IN MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_2) | ||
| 402 | #define MX28_PAD_ENET0_COL__ENET0_1588_EVENT3_OUT MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_2) | ||
| 403 | #define MX28_PAD_ENET0_CRS__ENET0_1588_EVENT3_IN MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_2) | ||
| 404 | |||
| 405 | /* MUXSEL_GPIO */ | ||
| 406 | #define MX28_PAD_GPMI_D00__GPIO_0_0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_GPIO) | ||
| 407 | #define MX28_PAD_GPMI_D01__GPIO_0_1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_GPIO) | ||
| 408 | #define MX28_PAD_GPMI_D02__GPIO_0_2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_GPIO) | ||
| 409 | #define MX28_PAD_GPMI_D03__GPIO_0_3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_GPIO) | ||
| 410 | #define MX28_PAD_GPMI_D04__GPIO_0_4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_GPIO) | ||
| 411 | #define MX28_PAD_GPMI_D05__GPIO_0_5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_GPIO) | ||
| 412 | #define MX28_PAD_GPMI_D06__GPIO_0_6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_GPIO) | ||
| 413 | #define MX28_PAD_GPMI_D07__GPIO_0_7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_GPIO) | ||
| 414 | #define MX28_PAD_GPMI_CE0N__GPIO_0_16 MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_GPIO) | ||
| 415 | #define MX28_PAD_GPMI_CE1N__GPIO_0_17 MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_GPIO) | ||
| 416 | #define MX28_PAD_GPMI_CE2N__GPIO_0_18 MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_GPIO) | ||
| 417 | #define MX28_PAD_GPMI_CE3N__GPIO_0_19 MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_GPIO) | ||
| 418 | #define MX28_PAD_GPMI_RDY0__GPIO_0_20 MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_GPIO) | ||
| 419 | #define MX28_PAD_GPMI_RDY1__GPIO_0_21 MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_GPIO) | ||
| 420 | #define MX28_PAD_GPMI_RDY2__GPIO_0_22 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_GPIO) | ||
| 421 | #define MX28_PAD_GPMI_RDY3__GPIO_0_23 MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_GPIO) | ||
| 422 | #define MX28_PAD_GPMI_RDN__GPIO_0_24 MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_GPIO) | ||
| 423 | #define MX28_PAD_GPMI_WRN__GPIO_0_25 MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_GPIO) | ||
| 424 | #define MX28_PAD_GPMI_ALE__GPIO_0_26 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_GPIO) | ||
| 425 | #define MX28_PAD_GPMI_CLE__GPIO_0_27 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_GPIO) | ||
| 426 | #define MX28_PAD_GPMI_RESETN__GPIO_0_28 MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_GPIO) | ||
| 427 | |||
| 428 | #define MX28_PAD_LCD_D00__GPIO_1_0 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_GPIO) | ||
| 429 | #define MX28_PAD_LCD_D01__GPIO_1_1 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_GPIO) | ||
| 430 | #define MX28_PAD_LCD_D02__GPIO_1_2 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_GPIO) | ||
| 431 | #define MX28_PAD_LCD_D03__GPIO_1_3 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_GPIO) | ||
| 432 | #define MX28_PAD_LCD_D04__GPIO_1_4 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_GPIO) | ||
| 433 | #define MX28_PAD_LCD_D05__GPIO_1_5 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_GPIO) | ||
| 434 | #define MX28_PAD_LCD_D06__GPIO_1_6 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_GPIO) | ||
| 435 | #define MX28_PAD_LCD_D07__GPIO_1_7 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_GPIO) | ||
| 436 | #define MX28_PAD_LCD_D08__GPIO_1_8 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_GPIO) | ||
| 437 | #define MX28_PAD_LCD_D09__GPIO_1_9 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_GPIO) | ||
| 438 | #define MX28_PAD_LCD_D10__GPIO_1_10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_GPIO) | ||
| 439 | #define MX28_PAD_LCD_D11__GPIO_1_11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_GPIO) | ||
| 440 | #define MX28_PAD_LCD_D12__GPIO_1_12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_GPIO) | ||
| 441 | #define MX28_PAD_LCD_D13__GPIO_1_13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_GPIO) | ||
| 442 | #define MX28_PAD_LCD_D14__GPIO_1_14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_GPIO) | ||
| 443 | #define MX28_PAD_LCD_D15__GPIO_1_15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_GPIO) | ||
| 444 | #define MX28_PAD_LCD_D16__GPIO_1_16 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_GPIO) | ||
| 445 | #define MX28_PAD_LCD_D17__GPIO_1_17 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_GPIO) | ||
| 446 | #define MX28_PAD_LCD_D18__GPIO_1_18 MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_GPIO) | ||
| 447 | #define MX28_PAD_LCD_D19__GPIO_1_19 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_GPIO) | ||
| 448 | #define MX28_PAD_LCD_D20__GPIO_1_20 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_GPIO) | ||
| 449 | #define MX28_PAD_LCD_D21__GPIO_1_21 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_GPIO) | ||
| 450 | #define MX28_PAD_LCD_D22__GPIO_1_22 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_GPIO) | ||
| 451 | #define MX28_PAD_LCD_D23__GPIO_1_23 MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_GPIO) | ||
| 452 | #define MX28_PAD_LCD_RD_E__GPIO_1_24 MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_GPIO) | ||
| 453 | #define MX28_PAD_LCD_WR_RWN__GPIO_1_25 MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_GPIO) | ||
| 454 | #define MX28_PAD_LCD_RS__GPIO_1_26 MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_GPIO) | ||
| 455 | #define MX28_PAD_LCD_CS__GPIO_1_27 MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_GPIO) | ||
| 456 | #define MX28_PAD_LCD_VSYNC__GPIO_1_28 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_GPIO) | ||
| 457 | #define MX28_PAD_LCD_HSYNC__GPIO_1_29 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_GPIO) | ||
| 458 | #define MX28_PAD_LCD_DOTCLK__GPIO_1_30 MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_GPIO) | ||
| 459 | #define MX28_PAD_LCD_ENABLE__GPIO_1_31 MXS_IOMUX_PAD_NAKED(1, 31, PAD_MUXSEL_GPIO) | ||
| 460 | |||
| 461 | #define MX28_PAD_SSP0_DATA0__GPIO_2_0 MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_GPIO) | ||
| 462 | #define MX28_PAD_SSP0_DATA1__GPIO_2_1 MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_GPIO) | ||
| 463 | #define MX28_PAD_SSP0_DATA2__GPIO_2_2 MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_GPIO) | ||
| 464 | #define MX28_PAD_SSP0_DATA3__GPIO_2_3 MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_GPIO) | ||
| 465 | #define MX28_PAD_SSP0_DATA4__GPIO_2_4 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_GPIO) | ||
| 466 | #define MX28_PAD_SSP0_DATA5__GPIO_2_5 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_GPIO) | ||
| 467 | #define MX28_PAD_SSP0_DATA6__GPIO_2_6 MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_GPIO) | ||
| 468 | #define MX28_PAD_SSP0_DATA7__GPIO_2_7 MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_GPIO) | ||
| 469 | #define MX28_PAD_SSP0_CMD__GPIO_2_8 MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_GPIO) | ||
| 470 | #define MX28_PAD_SSP0_DETECT__GPIO_2_9 MXS_IOMUX_PAD_NAKED(2, 9, PAD_MUXSEL_GPIO) | ||
| 471 | #define MX28_PAD_SSP0_SCK__GPIO_2_10 MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_GPIO) | ||
| 472 | #define MX28_PAD_SSP1_SCK__GPIO_2_12 MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_GPIO) | ||
| 473 | #define MX28_PAD_SSP1_CMD__GPIO_2_13 MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_GPIO) | ||
| 474 | #define MX28_PAD_SSP1_DATA0__GPIO_2_14 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_GPIO) | ||
| 475 | #define MX28_PAD_SSP1_DATA3__GPIO_2_15 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_GPIO) | ||
| 476 | #define MX28_PAD_SSP2_SCK__GPIO_2_16 MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_GPIO) | ||
| 477 | #define MX28_PAD_SSP2_MOSI__GPIO_2_17 MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_GPIO) | ||
| 478 | #define MX28_PAD_SSP2_MISO__GPIO_2_18 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_GPIO) | ||
| 479 | #define MX28_PAD_SSP2_SS0__GPIO_2_19 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_GPIO) | ||
| 480 | #define MX28_PAD_SSP2_SS1__GPIO_2_20 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_GPIO) | ||
| 481 | #define MX28_PAD_SSP2_SS2__GPIO_2_21 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_GPIO) | ||
| 482 | #define MX28_PAD_SSP3_SCK__GPIO_2_24 MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_GPIO) | ||
| 483 | #define MX28_PAD_SSP3_MOSI__GPIO_2_25 MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_GPIO) | ||
| 484 | #define MX28_PAD_SSP3_MISO__GPIO_2_26 MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_GPIO) | ||
| 485 | #define MX28_PAD_SSP3_SS0__GPIO_2_27 MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_GPIO) | ||
| 486 | |||
| 487 | #define MX28_PAD_AUART0_RX__GPIO_3_0 MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_GPIO) | ||
| 488 | #define MX28_PAD_AUART0_TX__GPIO_3_1 MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_GPIO) | ||
| 489 | #define MX28_PAD_AUART0_CTS__GPIO_3_2 MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_GPIO) | ||
| 490 | #define MX28_PAD_AUART0_RTS__GPIO_3_3 MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_GPIO) | ||
| 491 | #define MX28_PAD_AUART1_RX__GPIO_3_4 MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_GPIO) | ||
| 492 | #define MX28_PAD_AUART1_TX__GPIO_3_5 MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_GPIO) | ||
| 493 | #define MX28_PAD_AUART1_CTS__GPIO_3_6 MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_GPIO) | ||
| 494 | #define MX28_PAD_AUART1_RTS__GPIO_3_7 MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_GPIO) | ||
| 495 | #define MX28_PAD_AUART2_RX__GPIO_3_8 MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_GPIO) | ||
| 496 | #define MX28_PAD_AUART2_TX__GPIO_3_9 MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_GPIO) | ||
| 497 | #define MX28_PAD_AUART2_CTS__GPIO_3_10 MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_GPIO) | ||
| 498 | #define MX28_PAD_AUART2_RTS__GPIO_3_11 MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_GPIO) | ||
| 499 | #define MX28_PAD_AUART3_RX__GPIO_3_12 MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_GPIO) | ||
| 500 | #define MX28_PAD_AUART3_TX__GPIO_3_13 MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_GPIO) | ||
| 501 | #define MX28_PAD_AUART3_CTS__GPIO_3_14 MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_GPIO) | ||
| 502 | #define MX28_PAD_AUART3_RTS__GPIO_3_15 MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_GPIO) | ||
| 503 | #define MX28_PAD_PWM0__GPIO_3_16 MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_GPIO) | ||
| 504 | #define MX28_PAD_PWM1__GPIO_3_17 MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_GPIO) | ||
| 505 | #define MX28_PAD_PWM2__GPIO_3_18 MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_GPIO) | ||
| 506 | #define MX28_PAD_SAIF0_MCLK__GPIO_3_20 MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_GPIO) | ||
| 507 | #define MX28_PAD_SAIF0_LRCLK__GPIO_3_21 MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_GPIO) | ||
| 508 | #define MX28_PAD_SAIF0_BITCLK__GPIO_3_22 MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_GPIO) | ||
| 509 | #define MX28_PAD_SAIF0_SDATA0__GPIO_3_23 MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_GPIO) | ||
| 510 | #define MX28_PAD_I2C0_SCL__GPIO_3_24 MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_GPIO) | ||
| 511 | #define MX28_PAD_I2C0_SDA__GPIO_3_25 MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_GPIO) | ||
| 512 | #define MX28_PAD_SAIF1_SDATA0__GPIO_3_26 MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_GPIO) | ||
| 513 | #define MX28_PAD_SPDIF__GPIO_3_27 MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_GPIO) | ||
| 514 | #define MX28_PAD_PWM3__GPIO_3_28 MXS_IOMUX_PAD_NAKED(3, 28, PAD_MUXSEL_GPIO) | ||
| 515 | #define MX28_PAD_PWM4__GPIO_3_29 MXS_IOMUX_PAD_NAKED(3, 29, PAD_MUXSEL_GPIO) | ||
| 516 | #define MX28_PAD_LCD_RESET__GPIO_3_30 MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_GPIO) | ||
| 517 | |||
| 518 | #define MX28_PAD_ENET0_MDC__GPIO_4_0 MXS_IOMUX_PAD_NAKED(4, 0, PAD_MUXSEL_GPIO) | ||
| 519 | #define MX28_PAD_ENET0_MDIO__GPIO_4_1 MXS_IOMUX_PAD_NAKED(4, 1, PAD_MUXSEL_GPIO) | ||
| 520 | #define MX28_PAD_ENET0_RX_EN__GPIO_4_2 MXS_IOMUX_PAD_NAKED(4, 2, PAD_MUXSEL_GPIO) | ||
| 521 | #define MX28_PAD_ENET0_RXD0__GPIO_4_3 MXS_IOMUX_PAD_NAKED(4, 3, PAD_MUXSEL_GPIO) | ||
| 522 | #define MX28_PAD_ENET0_RXD1__GPIO_4_4 MXS_IOMUX_PAD_NAKED(4, 4, PAD_MUXSEL_GPIO) | ||
| 523 | #define MX28_PAD_ENET0_TX_CLK__GPIO_4_5 MXS_IOMUX_PAD_NAKED(4, 5, PAD_MUXSEL_GPIO) | ||
| 524 | #define MX28_PAD_ENET0_TX_EN__GPIO_4_6 MXS_IOMUX_PAD_NAKED(4, 6, PAD_MUXSEL_GPIO) | ||
| 525 | #define MX28_PAD_ENET0_TXD0__GPIO_4_7 MXS_IOMUX_PAD_NAKED(4, 7, PAD_MUXSEL_GPIO) | ||
| 526 | #define MX28_PAD_ENET0_TXD1__GPIO_4_8 MXS_IOMUX_PAD_NAKED(4, 8, PAD_MUXSEL_GPIO) | ||
| 527 | #define MX28_PAD_ENET0_RXD2__GPIO_4_9 MXS_IOMUX_PAD_NAKED(4, 9, PAD_MUXSEL_GPIO) | ||
| 528 | #define MX28_PAD_ENET0_RXD3__GPIO_4_10 MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_GPIO) | ||
| 529 | #define MX28_PAD_ENET0_TXD2__GPIO_4_11 MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_GPIO) | ||
| 530 | #define MX28_PAD_ENET0_TXD3__GPIO_4_12 MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_GPIO) | ||
| 531 | #define MX28_PAD_ENET0_RX_CLK__GPIO_4_13 MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_GPIO) | ||
| 532 | #define MX28_PAD_ENET0_COL__GPIO_4_14 MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_GPIO) | ||
| 533 | #define MX28_PAD_ENET0_CRS__GPIO_4_15 MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_GPIO) | ||
| 534 | #define MX28_PAD_ENET_CLK__GPIO_4_16 MXS_IOMUX_PAD_NAKED(4, 16, PAD_MUXSEL_GPIO) | ||
| 535 | #define MX28_PAD_JTAG_RTCK__GPIO_4_20 MXS_IOMUX_PAD_NAKED(4, 20, PAD_MUXSEL_GPIO) | ||
| 536 | |||
| 537 | #endif /* __MACH_IOMUX_MX28_H__ */ | ||
diff --git a/arch/arm/mach-mxs/include/mach/iomux.h b/arch/arm/mach-mxs/include/mach/iomux.h deleted file mode 100644 index 7abdf58b8bb7..000000000000 --- a/arch/arm/mach-mxs/include/mach/iomux.h +++ /dev/null | |||
| @@ -1,168 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH, | ||
| 3 | * <armlinux@phytec.de> | ||
| 4 | * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public License | ||
| 8 | * as published by the Free Software Foundation; either version 2 | ||
| 9 | * of the License, or (at your option) any later version. | ||
| 10 | * This program is distributed in the hope that it will be useful, | ||
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 13 | * GNU General Public License for more details. | ||
| 14 | * | ||
| 15 | * You should have received a copy of the GNU General Public License | ||
| 16 | * along with this program; if not, write to the Free Software | ||
| 17 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | ||
| 18 | * MA 02110-1301, USA. | ||
| 19 | */ | ||
| 20 | |||
| 21 | #ifndef __MACH_MXS_IOMUX_H__ | ||
| 22 | #define __MACH_MXS_IOMUX_H__ | ||
| 23 | |||
| 24 | /* | ||
| 25 | * IOMUX/PAD Bit field definitions | ||
| 26 | * | ||
| 27 | * PAD_BANK: 0..2 (3) | ||
| 28 | * PAD_PIN: 3..7 (5) | ||
| 29 | * PAD_MUXSEL: 8..9 (2) | ||
| 30 | * PAD_MA: 10..11 (2) | ||
| 31 | * PAD_MA_VALID: 12 (1) | ||
| 32 | * PAD_VOL: 13 (1) | ||
| 33 | * PAD_VOL_VALID: 14 (1) | ||
| 34 | * PAD_PULL: 15 (1) | ||
| 35 | * PAD_PULL_VALID: 16 (1) | ||
| 36 | * RESERVED: 17..31 (15) | ||
| 37 | */ | ||
| 38 | typedef u32 iomux_cfg_t; | ||
| 39 | |||
| 40 | #define MXS_PAD_BANK_SHIFT 0 | ||
| 41 | #define MXS_PAD_BANK_MASK ((iomux_cfg_t)0x7 << MXS_PAD_BANK_SHIFT) | ||
| 42 | #define MXS_PAD_PIN_SHIFT 3 | ||
| 43 | #define MXS_PAD_PIN_MASK ((iomux_cfg_t)0x1f << MXS_PAD_PIN_SHIFT) | ||
| 44 | #define MXS_PAD_MUXSEL_SHIFT 8 | ||
| 45 | #define MXS_PAD_MUXSEL_MASK ((iomux_cfg_t)0x3 << MXS_PAD_MUXSEL_SHIFT) | ||
| 46 | #define MXS_PAD_MA_SHIFT 10 | ||
| 47 | #define MXS_PAD_MA_MASK ((iomux_cfg_t)0x3 << MXS_PAD_MA_SHIFT) | ||
| 48 | #define MXS_PAD_MA_VALID_SHIFT 12 | ||
| 49 | #define MXS_PAD_MA_VALID_MASK ((iomux_cfg_t)0x1 << MXS_PAD_MA_VALID_SHIFT) | ||
| 50 | #define MXS_PAD_VOL_SHIFT 13 | ||
| 51 | #define MXS_PAD_VOL_MASK ((iomux_cfg_t)0x1 << MXS_PAD_VOL_SHIFT) | ||
| 52 | #define MXS_PAD_VOL_VALID_SHIFT 14 | ||
| 53 | #define MXS_PAD_VOL_VALID_MASK ((iomux_cfg_t)0x1 << MXS_PAD_VOL_VALID_SHIFT) | ||
| 54 | #define MXS_PAD_PULL_SHIFT 15 | ||
| 55 | #define MXS_PAD_PULL_MASK ((iomux_cfg_t)0x1 << MXS_PAD_PULL_SHIFT) | ||
| 56 | #define MXS_PAD_PULL_VALID_SHIFT 16 | ||
| 57 | #define MXS_PAD_PULL_VALID_MASK ((iomux_cfg_t)0x1 << MXS_PAD_PULL_VALID_SHIFT) | ||
| 58 | |||
| 59 | #define PAD_MUXSEL_0 0 | ||
| 60 | #define PAD_MUXSEL_1 1 | ||
| 61 | #define PAD_MUXSEL_2 2 | ||
| 62 | #define PAD_MUXSEL_GPIO 3 | ||
| 63 | |||
| 64 | #define PAD_4MA 0 | ||
| 65 | #define PAD_8MA 1 | ||
| 66 | #define PAD_12MA 2 | ||
| 67 | #define PAD_16MA 3 | ||
| 68 | |||
| 69 | #define PAD_1V8 0 | ||
| 70 | #define PAD_3V3 1 | ||
| 71 | |||
| 72 | #define PAD_NOPULL 0 | ||
| 73 | #define PAD_PULLUP 1 | ||
| 74 | |||
| 75 | #define MXS_PAD_4MA ((PAD_4MA << MXS_PAD_MA_SHIFT) | \ | ||
| 76 | MXS_PAD_MA_VALID_MASK) | ||
| 77 | #define MXS_PAD_8MA ((PAD_8MA << MXS_PAD_MA_SHIFT) | \ | ||
| 78 | MXS_PAD_MA_VALID_MASK) | ||
| 79 | #define MXS_PAD_12MA ((PAD_12MA << MXS_PAD_MA_SHIFT) | \ | ||
| 80 | MXS_PAD_MA_VALID_MASK) | ||
| 81 | #define MXS_PAD_16MA ((PAD_16MA << MXS_PAD_MA_SHIFT) | \ | ||
| 82 | MXS_PAD_MA_VALID_MASK) | ||
| 83 | |||
| 84 | #define MXS_PAD_1V8 ((PAD_1V8 << MXS_PAD_VOL_SHIFT) | \ | ||
| 85 | MXS_PAD_VOL_VALID_MASK) | ||
| 86 | #define MXS_PAD_3V3 ((PAD_3V3 << MXS_PAD_VOL_SHIFT) | \ | ||
| 87 | MXS_PAD_VOL_VALID_MASK) | ||
| 88 | |||
| 89 | #define MXS_PAD_NOPULL ((PAD_NOPULL << MXS_PAD_PULL_SHIFT) | \ | ||
| 90 | MXS_PAD_PULL_VALID_MASK) | ||
| 91 | #define MXS_PAD_PULLUP ((PAD_PULLUP << MXS_PAD_PULL_SHIFT) | \ | ||
| 92 | MXS_PAD_PULL_VALID_MASK) | ||
| 93 | |||
| 94 | /* generic pad control used in most cases */ | ||
| 95 | #define MXS_PAD_CTRL (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL) | ||
| 96 | |||
| 97 | #define MXS_IOMUX_PAD(_bank, _pin, _muxsel, _ma, _vol, _pull) \ | ||
| 98 | (((iomux_cfg_t)(_bank) << MXS_PAD_BANK_SHIFT) | \ | ||
| 99 | ((iomux_cfg_t)(_pin) << MXS_PAD_PIN_SHIFT) | \ | ||
| 100 | ((iomux_cfg_t)(_muxsel) << MXS_PAD_MUXSEL_SHIFT) | \ | ||
| 101 | ((iomux_cfg_t)(_ma) << MXS_PAD_MA_SHIFT) | \ | ||
| 102 | ((iomux_cfg_t)(_vol) << MXS_PAD_VOL_SHIFT) | \ | ||
| 103 | ((iomux_cfg_t)(_pull) << MXS_PAD_PULL_SHIFT)) | ||
| 104 | |||
| 105 | /* | ||
| 106 | * A pad becomes naked, when none of mA, vol or pull | ||
| 107 | * validity bits is set. | ||
| 108 | */ | ||
| 109 | #define MXS_IOMUX_PAD_NAKED(_bank, _pin, _muxsel) \ | ||
| 110 | MXS_IOMUX_PAD(_bank, _pin, _muxsel, 0, 0, 0) | ||
| 111 | |||
| 112 | static inline unsigned int PAD_BANK(iomux_cfg_t pad) | ||
| 113 | { | ||
| 114 | return (pad & MXS_PAD_BANK_MASK) >> MXS_PAD_BANK_SHIFT; | ||
| 115 | } | ||
| 116 | |||
| 117 | static inline unsigned int PAD_PIN(iomux_cfg_t pad) | ||
| 118 | { | ||
| 119 | return (pad & MXS_PAD_PIN_MASK) >> MXS_PAD_PIN_SHIFT; | ||
| 120 | } | ||
| 121 | |||
| 122 | static inline unsigned int PAD_MUXSEL(iomux_cfg_t pad) | ||
| 123 | { | ||
| 124 | return (pad & MXS_PAD_MUXSEL_MASK) >> MXS_PAD_MUXSEL_SHIFT; | ||
| 125 | } | ||
| 126 | |||
| 127 | static inline unsigned int PAD_MA(iomux_cfg_t pad) | ||
| 128 | { | ||
| 129 | return (pad & MXS_PAD_MA_MASK) >> MXS_PAD_MA_SHIFT; | ||
| 130 | } | ||
| 131 | |||
| 132 | static inline unsigned int PAD_MA_VALID(iomux_cfg_t pad) | ||
| 133 | { | ||
| 134 | return (pad & MXS_PAD_MA_VALID_MASK) >> MXS_PAD_MA_VALID_SHIFT; | ||
| 135 | } | ||
| 136 | |||
| 137 | static inline unsigned int PAD_VOL(iomux_cfg_t pad) | ||
| 138 | { | ||
| 139 | return (pad & MXS_PAD_VOL_MASK) >> MXS_PAD_VOL_SHIFT; | ||
| 140 | } | ||
| 141 | |||
| 142 | static inline unsigned int PAD_VOL_VALID(iomux_cfg_t pad) | ||
| 143 | { | ||
| 144 | return (pad & MXS_PAD_VOL_VALID_MASK) >> MXS_PAD_VOL_VALID_SHIFT; | ||
| 145 | } | ||
| 146 | |||
| 147 | static inline unsigned int PAD_PULL(iomux_cfg_t pad) | ||
| 148 | { | ||
| 149 | return (pad & MXS_PAD_PULL_MASK) >> MXS_PAD_PULL_SHIFT; | ||
| 150 | } | ||
| 151 | |||
| 152 | static inline unsigned int PAD_PULL_VALID(iomux_cfg_t pad) | ||
| 153 | { | ||
| 154 | return (pad & MXS_PAD_PULL_VALID_MASK) >> MXS_PAD_PULL_VALID_SHIFT; | ||
| 155 | } | ||
| 156 | |||
| 157 | /* | ||
| 158 | * configures a single pad in the iomuxer | ||
| 159 | */ | ||
| 160 | int mxs_iomux_setup_pad(iomux_cfg_t pad); | ||
| 161 | |||
| 162 | /* | ||
| 163 | * configures multiple pads | ||
| 164 | * convenient way to call the above function with tables | ||
| 165 | */ | ||
| 166 | int mxs_iomux_setup_multiple_pads(const iomux_cfg_t *pad_list, unsigned count); | ||
| 167 | |||
| 168 | #endif /* __MACH_MXS_IOMUX_H__*/ | ||
diff --git a/arch/arm/mach-mxs/iomux.c b/arch/arm/mach-mxs/iomux.c deleted file mode 100644 index 0e804e2f11f4..000000000000 --- a/arch/arm/mach-mxs/iomux.c +++ /dev/null | |||
| @@ -1,101 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2004-2006,2010 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> | ||
| 4 | * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH, | ||
| 5 | * <armlinux@phytec.de> | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or | ||
| 8 | * modify it under the terms of the GNU General Public License | ||
| 9 | * as published by the Free Software Foundation; either version 2 | ||
| 10 | * of the License, or (at your option) any later version. | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | ||
| 19 | * MA 02110-1301, USA. | ||
| 20 | */ | ||
| 21 | |||
| 22 | #include <linux/errno.h> | ||
| 23 | #include <linux/init.h> | ||
| 24 | #include <linux/kernel.h> | ||
| 25 | #include <linux/module.h> | ||
| 26 | #include <linux/string.h> | ||
| 27 | #include <linux/gpio.h> | ||
| 28 | |||
| 29 | #include <asm/mach/map.h> | ||
| 30 | |||
| 31 | #include <mach/mxs.h> | ||
| 32 | #include <mach/iomux.h> | ||
| 33 | |||
| 34 | /* | ||
| 35 | * configures a single pad in the iomuxer | ||
| 36 | */ | ||
| 37 | int mxs_iomux_setup_pad(iomux_cfg_t pad) | ||
| 38 | { | ||
| 39 | u32 reg, ofs, bp, bm; | ||
| 40 | void __iomem *iomux_base = MXS_IO_ADDRESS(MXS_PINCTRL_BASE_ADDR); | ||
| 41 | |||
| 42 | /* muxsel */ | ||
| 43 | ofs = 0x100; | ||
| 44 | ofs += PAD_BANK(pad) * 0x20 + PAD_PIN(pad) / 16 * 0x10; | ||
| 45 | bp = PAD_PIN(pad) % 16 * 2; | ||
| 46 | bm = 0x3 << bp; | ||
| 47 | reg = __raw_readl(iomux_base + ofs); | ||
| 48 | reg &= ~bm; | ||
| 49 | reg |= PAD_MUXSEL(pad) << bp; | ||
| 50 | __raw_writel(reg, iomux_base + ofs); | ||
| 51 | |||
| 52 | /* drive */ | ||
| 53 | ofs = cpu_is_mx23() ? 0x200 : 0x300; | ||
| 54 | ofs += PAD_BANK(pad) * 0x40 + PAD_PIN(pad) / 8 * 0x10; | ||
| 55 | /* mA */ | ||
| 56 | if (PAD_MA_VALID(pad)) { | ||
| 57 | bp = PAD_PIN(pad) % 8 * 4; | ||
| 58 | bm = 0x3 << bp; | ||
| 59 | reg = __raw_readl(iomux_base + ofs); | ||
| 60 | reg &= ~bm; | ||
| 61 | reg |= PAD_MA(pad) << bp; | ||
| 62 | __raw_writel(reg, iomux_base + ofs); | ||
| 63 | } | ||
| 64 | /* vol */ | ||
| 65 | if (PAD_VOL_VALID(pad)) { | ||
| 66 | bp = PAD_PIN(pad) % 8 * 4 + 2; | ||
| 67 | if (PAD_VOL(pad)) | ||
| 68 | __mxs_setl(1 << bp, iomux_base + ofs); | ||
| 69 | else | ||
| 70 | __mxs_clrl(1 << bp, iomux_base + ofs); | ||
| 71 | } | ||
| 72 | |||
| 73 | /* pull */ | ||
| 74 | if (PAD_PULL_VALID(pad)) { | ||
| 75 | ofs = cpu_is_mx23() ? 0x400 : 0x600; | ||
| 76 | ofs += PAD_BANK(pad) * 0x10; | ||
| 77 | bp = PAD_PIN(pad); | ||
| 78 | if (PAD_PULL(pad)) | ||
| 79 | __mxs_setl(1 << bp, iomux_base + ofs); | ||
| 80 | else | ||
| 81 | __mxs_clrl(1 << bp, iomux_base + ofs); | ||
| 82 | } | ||
| 83 | |||
| 84 | return 0; | ||
| 85 | } | ||
| 86 | |||
| 87 | int mxs_iomux_setup_multiple_pads(const iomux_cfg_t *pad_list, unsigned count) | ||
| 88 | { | ||
| 89 | const iomux_cfg_t *p = pad_list; | ||
| 90 | int i; | ||
| 91 | int ret; | ||
| 92 | |||
| 93 | for (i = 0; i < count; i++) { | ||
| 94 | ret = mxs_iomux_setup_pad(*p); | ||
| 95 | if (ret) | ||
| 96 | return ret; | ||
| 97 | p++; | ||
| 98 | } | ||
| 99 | |||
| 100 | return 0; | ||
| 101 | } | ||
diff --git a/arch/arm/mach-mxs/mach-apx4devkit.c b/arch/arm/mach-mxs/mach-apx4devkit.c deleted file mode 100644 index f5f061757deb..000000000000 --- a/arch/arm/mach-mxs/mach-apx4devkit.c +++ /dev/null | |||
| @@ -1,273 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2011-2012 | ||
| 3 | * Lauri Hintsala, Bluegiga, <lauri.hintsala@bluegiga.com> | ||
| 4 | * Veli-Pekka Peltola, Bluegiga, <veli-pekka.peltola@bluegiga.com> | ||
| 5 | * | ||
| 6 | * based on: mach-mx28evk.c | ||
| 7 | * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License as published by | ||
| 11 | * the Free Software Foundation; either version 2 of the License, or | ||
| 12 | * (at your option) any later version. | ||
| 13 | * | ||
| 14 | * This program is distributed in the hope that it will be useful, | ||
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 17 | * GNU General Public License for more details. | ||
| 18 | */ | ||
| 19 | |||
| 20 | #include <linux/delay.h> | ||
| 21 | #include <linux/platform_device.h> | ||
| 22 | #include <linux/gpio.h> | ||
| 23 | #include <linux/leds.h> | ||
| 24 | #include <linux/clk.h> | ||
| 25 | #include <linux/i2c.h> | ||
| 26 | #include <linux/regulator/machine.h> | ||
| 27 | #include <linux/regulator/fixed.h> | ||
| 28 | #include <linux/micrel_phy.h> | ||
| 29 | |||
| 30 | #include <asm/mach-types.h> | ||
| 31 | #include <asm/mach/arch.h> | ||
| 32 | #include <asm/mach/time.h> | ||
| 33 | |||
| 34 | #include <mach/common.h> | ||
| 35 | #include <mach/digctl.h> | ||
| 36 | #include <mach/iomux-mx28.h> | ||
| 37 | |||
| 38 | #include "devices-mx28.h" | ||
| 39 | |||
| 40 | #define APX4DEVKIT_GPIO_USERLED MXS_GPIO_NR(3, 28) | ||
| 41 | |||
| 42 | static const iomux_cfg_t apx4devkit_pads[] __initconst = { | ||
| 43 | /* duart */ | ||
| 44 | MX28_PAD_PWM0__DUART_RX | MXS_PAD_CTRL, | ||
| 45 | MX28_PAD_PWM1__DUART_TX | MXS_PAD_CTRL, | ||
| 46 | |||
| 47 | /* auart0 */ | ||
| 48 | MX28_PAD_AUART0_RX__AUART0_RX | MXS_PAD_CTRL, | ||
| 49 | MX28_PAD_AUART0_TX__AUART0_TX | MXS_PAD_CTRL, | ||
| 50 | MX28_PAD_AUART0_CTS__AUART0_CTS | MXS_PAD_CTRL, | ||
| 51 | MX28_PAD_AUART0_RTS__AUART0_RTS | MXS_PAD_CTRL, | ||
| 52 | |||
| 53 | /* auart1 */ | ||
| 54 | MX28_PAD_AUART1_RX__AUART1_RX | MXS_PAD_CTRL, | ||
| 55 | MX28_PAD_AUART1_TX__AUART1_TX | MXS_PAD_CTRL, | ||
| 56 | |||
| 57 | /* auart2 */ | ||
| 58 | MX28_PAD_SSP2_SCK__AUART2_RX | MXS_PAD_CTRL, | ||
| 59 | MX28_PAD_SSP2_MOSI__AUART2_TX | MXS_PAD_CTRL, | ||
| 60 | |||
| 61 | /* auart3 */ | ||
| 62 | MX28_PAD_SSP2_MISO__AUART3_RX | MXS_PAD_CTRL, | ||
| 63 | MX28_PAD_SSP2_SS0__AUART3_TX | MXS_PAD_CTRL, | ||
| 64 | |||
| 65 | #define MXS_PAD_FEC (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP) | ||
| 66 | /* fec0 */ | ||
| 67 | MX28_PAD_ENET0_MDC__ENET0_MDC | MXS_PAD_FEC, | ||
| 68 | MX28_PAD_ENET0_MDIO__ENET0_MDIO | MXS_PAD_FEC, | ||
| 69 | MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MXS_PAD_FEC, | ||
| 70 | MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MXS_PAD_FEC, | ||
| 71 | MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MXS_PAD_FEC, | ||
| 72 | MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MXS_PAD_FEC, | ||
| 73 | MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MXS_PAD_FEC, | ||
| 74 | MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MXS_PAD_FEC, | ||
| 75 | MX28_PAD_ENET_CLK__CLKCTRL_ENET | MXS_PAD_FEC, | ||
| 76 | |||
| 77 | /* i2c */ | ||
| 78 | MX28_PAD_I2C0_SCL__I2C0_SCL, | ||
| 79 | MX28_PAD_I2C0_SDA__I2C0_SDA, | ||
| 80 | |||
| 81 | /* mmc0 */ | ||
| 82 | MX28_PAD_SSP0_DATA0__SSP0_D0 | | ||
| 83 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 84 | MX28_PAD_SSP0_DATA1__SSP0_D1 | | ||
| 85 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 86 | MX28_PAD_SSP0_DATA2__SSP0_D2 | | ||
| 87 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 88 | MX28_PAD_SSP0_DATA3__SSP0_D3 | | ||
| 89 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 90 | MX28_PAD_SSP0_DATA4__SSP0_D4 | | ||
| 91 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 92 | MX28_PAD_SSP0_DATA5__SSP0_D5 | | ||
| 93 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 94 | MX28_PAD_SSP0_DATA6__SSP0_D6 | | ||
| 95 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 96 | MX28_PAD_SSP0_DATA7__SSP0_D7 | | ||
| 97 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 98 | MX28_PAD_SSP0_CMD__SSP0_CMD | | ||
| 99 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 100 | MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT | | ||
| 101 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), | ||
| 102 | MX28_PAD_SSP0_SCK__SSP0_SCK | | ||
| 103 | (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), | ||
| 104 | |||
| 105 | /* led */ | ||
| 106 | MX28_PAD_PWM3__GPIO_3_28 | MXS_PAD_CTRL, | ||
| 107 | |||
| 108 | /* saif0 & saif1 */ | ||
| 109 | MX28_PAD_SAIF0_MCLK__SAIF0_MCLK | | ||
| 110 | (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 111 | MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK | | ||
| 112 | (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 113 | MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK | | ||
| 114 | (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 115 | MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 | | ||
| 116 | (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 117 | MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 | | ||
| 118 | (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 119 | }; | ||
| 120 | |||
| 121 | /* led */ | ||
| 122 | static const struct gpio_led apx4devkit_leds[] __initconst = { | ||
| 123 | { | ||
| 124 | .name = "user-led", | ||
| 125 | .default_trigger = "heartbeat", | ||
| 126 | .gpio = APX4DEVKIT_GPIO_USERLED, | ||
| 127 | }, | ||
| 128 | }; | ||
| 129 | |||
| 130 | static const struct gpio_led_platform_data apx4devkit_led_data __initconst = { | ||
| 131 | .leds = apx4devkit_leds, | ||
| 132 | .num_leds = ARRAY_SIZE(apx4devkit_leds), | ||
| 133 | }; | ||
| 134 | |||
| 135 | static const struct fec_platform_data mx28_fec_pdata __initconst = { | ||
| 136 | .phy = PHY_INTERFACE_MODE_RMII, | ||
| 137 | }; | ||
| 138 | |||
| 139 | static const struct mxs_mmc_platform_data apx4devkit_mmc_pdata __initconst = { | ||
| 140 | .wp_gpio = -EINVAL, | ||
| 141 | .flags = SLOTF_4_BIT_CAPABLE, | ||
| 142 | }; | ||
| 143 | |||
| 144 | static const struct i2c_board_info apx4devkit_i2c_boardinfo[] __initconst = { | ||
| 145 | { I2C_BOARD_INFO("sgtl5000", 0x0a) }, /* ASoC */ | ||
| 146 | { I2C_BOARD_INFO("pcf8563", 0x51) }, /* RTC */ | ||
| 147 | }; | ||
| 148 | |||
| 149 | #if defined(CONFIG_REGULATOR_FIXED_VOLTAGE) || \ | ||
| 150 | defined(CONFIG_REGULATOR_FIXED_VOLTAGE_MODULE) | ||
| 151 | static struct regulator_consumer_supply apx4devkit_audio_consumer_supplies[] = { | ||
| 152 | REGULATOR_SUPPLY("VDDA", "0-000a"), | ||
| 153 | REGULATOR_SUPPLY("VDDIO", "0-000a"), | ||
| 154 | }; | ||
| 155 | |||
| 156 | static struct regulator_init_data apx4devkit_vdd_reg_init_data = { | ||
| 157 | .constraints = { | ||
| 158 | .name = "3V3", | ||
| 159 | .always_on = 1, | ||
| 160 | }, | ||
| 161 | .consumer_supplies = apx4devkit_audio_consumer_supplies, | ||
| 162 | .num_consumer_supplies = ARRAY_SIZE(apx4devkit_audio_consumer_supplies), | ||
| 163 | }; | ||
| 164 | |||
| 165 | static struct fixed_voltage_config apx4devkit_vdd_pdata = { | ||
| 166 | .supply_name = "board-3V3", | ||
| 167 | .microvolts = 3300000, | ||
| 168 | .gpio = -EINVAL, | ||
| 169 | .enabled_at_boot = 1, | ||
| 170 | .init_data = &apx4devkit_vdd_reg_init_data, | ||
| 171 | }; | ||
| 172 | |||
| 173 | static struct platform_device apx4devkit_voltage_regulator = { | ||
| 174 | .name = "reg-fixed-voltage", | ||
| 175 | .id = -1, | ||
| 176 | .num_resources = 0, | ||
| 177 | .dev = { | ||
| 178 | .platform_data = &apx4devkit_vdd_pdata, | ||
| 179 | }, | ||
| 180 | }; | ||
| 181 | |||
| 182 | static void __init apx4devkit_add_regulators(void) | ||
| 183 | { | ||
| 184 | platform_device_register(&apx4devkit_voltage_regulator); | ||
| 185 | } | ||
| 186 | #else | ||
| 187 | static void __init apx4devkit_add_regulators(void) {} | ||
| 188 | #endif | ||
| 189 | |||
| 190 | static const struct mxs_saif_platform_data | ||
| 191 | apx4devkit_mxs_saif_pdata[] __initconst = { | ||
| 192 | /* working on EXTMSTR0 mode (saif0 master, saif1 slave) */ | ||
| 193 | { | ||
| 194 | .master_mode = 1, | ||
| 195 | .master_id = 0, | ||
| 196 | }, { | ||
| 197 | .master_mode = 0, | ||
| 198 | .master_id = 0, | ||
| 199 | }, | ||
| 200 | }; | ||
| 201 | |||
| 202 | static int apx4devkit_phy_fixup(struct phy_device *phy) | ||
| 203 | { | ||
| 204 | phy->dev_flags |= MICREL_PHY_50MHZ_CLK; | ||
| 205 | return 0; | ||
| 206 | } | ||
| 207 | |||
| 208 | static void __init apx4devkit_fec_phy_clk_enable(void) | ||
| 209 | { | ||
| 210 | struct clk *clk; | ||
| 211 | |||
| 212 | /* Enable fec phy clock */ | ||
| 213 | clk = clk_get_sys("enet_out", NULL); | ||
| 214 | if (!IS_ERR(clk)) | ||
| 215 | clk_prepare_enable(clk); | ||
| 216 | } | ||
| 217 | |||
| 218 | static void __init apx4devkit_init(void) | ||
| 219 | { | ||
| 220 | mx28_soc_init(); | ||
| 221 | |||
| 222 | mxs_iomux_setup_multiple_pads(apx4devkit_pads, | ||
| 223 | ARRAY_SIZE(apx4devkit_pads)); | ||
| 224 | |||
| 225 | mx28_add_duart(); | ||
| 226 | mx28_add_auart0(); | ||
| 227 | mx28_add_auart1(); | ||
| 228 | mx28_add_auart2(); | ||
| 229 | mx28_add_auart3(); | ||
| 230 | |||
| 231 | /* | ||
| 232 | * Register fixup for the Micrel KS8031 PHY clock | ||
| 233 | * (shares same ID with KS8051) | ||
| 234 | */ | ||
| 235 | phy_register_fixup_for_uid(PHY_ID_KS8051, MICREL_PHY_ID_MASK, | ||
| 236 | apx4devkit_phy_fixup); | ||
| 237 | |||
| 238 | apx4devkit_fec_phy_clk_enable(); | ||
| 239 | mx28_add_fec(0, &mx28_fec_pdata); | ||
| 240 | |||
| 241 | mx28_add_mxs_mmc(0, &apx4devkit_mmc_pdata); | ||
| 242 | |||
| 243 | gpio_led_register_device(0, &apx4devkit_led_data); | ||
| 244 | |||
| 245 | mxs_saif_clkmux_select(MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0); | ||
| 246 | mx28_add_saif(0, &apx4devkit_mxs_saif_pdata[0]); | ||
| 247 | mx28_add_saif(1, &apx4devkit_mxs_saif_pdata[1]); | ||
| 248 | |||
| 249 | apx4devkit_add_regulators(); | ||
| 250 | |||
| 251 | mx28_add_mxs_i2c(0); | ||
| 252 | i2c_register_board_info(0, apx4devkit_i2c_boardinfo, | ||
| 253 | ARRAY_SIZE(apx4devkit_i2c_boardinfo)); | ||
| 254 | |||
| 255 | mxs_add_platform_device("mxs-sgtl5000", 0, NULL, 0, NULL, 0); | ||
| 256 | } | ||
| 257 | |||
| 258 | static void __init apx4devkit_timer_init(void) | ||
| 259 | { | ||
| 260 | mx28_clocks_init(); | ||
| 261 | } | ||
| 262 | |||
| 263 | static struct sys_timer apx4devkit_timer = { | ||
| 264 | .init = apx4devkit_timer_init, | ||
| 265 | }; | ||
| 266 | |||
| 267 | MACHINE_START(APX4DEVKIT, "Bluegiga APX4 Development Kit") | ||
| 268 | .map_io = mx28_map_io, | ||
| 269 | .init_irq = mx28_init_irq, | ||
| 270 | .timer = &apx4devkit_timer, | ||
| 271 | .init_machine = apx4devkit_init, | ||
| 272 | .restart = mxs_restart, | ||
| 273 | MACHINE_END | ||
diff --git a/arch/arm/mach-mxs/mach-m28evk.c b/arch/arm/mach-mxs/mach-m28evk.c deleted file mode 100644 index 4c00c879b893..000000000000 --- a/arch/arm/mach-mxs/mach-m28evk.c +++ /dev/null | |||
| @@ -1,366 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2011 | ||
| 3 | * Stefano Babic, DENX Software Engineering, <sbabic@denx.de> | ||
| 4 | * | ||
| 5 | * based on: mach-mx28_evk.c | ||
| 6 | * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License as published by | ||
| 10 | * the Free Software Foundation; either version 2 of the License, or | ||
| 11 | * (at your option) any later version. | ||
| 12 | * | ||
| 13 | * This program is distributed in the hope that it will be useful, | ||
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 16 | * GNU General Public License for more details. | ||
| 17 | */ | ||
| 18 | |||
| 19 | #include <linux/delay.h> | ||
| 20 | #include <linux/platform_device.h> | ||
| 21 | #include <linux/gpio.h> | ||
| 22 | #include <linux/leds.h> | ||
| 23 | #include <linux/irq.h> | ||
| 24 | #include <linux/clk.h> | ||
| 25 | #include <linux/i2c.h> | ||
| 26 | #include <linux/i2c/at24.h> | ||
| 27 | |||
| 28 | #include <asm/mach-types.h> | ||
| 29 | #include <asm/mach/arch.h> | ||
| 30 | #include <asm/mach/time.h> | ||
| 31 | |||
| 32 | #include <mach/common.h> | ||
| 33 | #include <mach/iomux-mx28.h> | ||
| 34 | |||
| 35 | #include "devices-mx28.h" | ||
| 36 | |||
| 37 | #define M28EVK_GPIO_USERLED1 MXS_GPIO_NR(3, 16) | ||
| 38 | #define M28EVK_GPIO_USERLED2 MXS_GPIO_NR(3, 17) | ||
| 39 | |||
| 40 | #define MX28EVK_BL_ENABLE MXS_GPIO_NR(3, 18) | ||
| 41 | #define M28EVK_LCD_ENABLE MXS_GPIO_NR(3, 28) | ||
| 42 | |||
| 43 | #define MX28EVK_MMC0_WRITE_PROTECT MXS_GPIO_NR(2, 12) | ||
| 44 | #define MX28EVK_MMC1_WRITE_PROTECT MXS_GPIO_NR(0, 28) | ||
| 45 | |||
| 46 | static const iomux_cfg_t m28evk_pads[] __initconst = { | ||
| 47 | /* duart */ | ||
| 48 | MX28_PAD_AUART0_CTS__DUART_RX | MXS_PAD_CTRL, | ||
| 49 | MX28_PAD_AUART0_RTS__DUART_TX | MXS_PAD_CTRL, | ||
| 50 | |||
| 51 | /* auart0 */ | ||
| 52 | MX28_PAD_AUART0_RX__AUART0_RX | MXS_PAD_CTRL, | ||
| 53 | MX28_PAD_AUART0_TX__AUART0_TX | MXS_PAD_CTRL, | ||
| 54 | |||
| 55 | /* auart3 */ | ||
| 56 | MX28_PAD_AUART3_RX__AUART3_RX | MXS_PAD_CTRL, | ||
| 57 | MX28_PAD_AUART3_TX__AUART3_TX | MXS_PAD_CTRL, | ||
| 58 | MX28_PAD_AUART3_CTS__AUART3_CTS | MXS_PAD_CTRL, | ||
| 59 | MX28_PAD_AUART3_RTS__AUART3_RTS | MXS_PAD_CTRL, | ||
| 60 | |||
| 61 | #define MXS_PAD_FEC (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP) | ||
| 62 | /* fec0 */ | ||
| 63 | MX28_PAD_ENET0_MDC__ENET0_MDC | MXS_PAD_FEC, | ||
| 64 | MX28_PAD_ENET0_MDIO__ENET0_MDIO | MXS_PAD_FEC, | ||
| 65 | MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MXS_PAD_FEC, | ||
| 66 | MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MXS_PAD_FEC, | ||
| 67 | MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MXS_PAD_FEC, | ||
| 68 | MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MXS_PAD_FEC, | ||
| 69 | MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MXS_PAD_FEC, | ||
| 70 | MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MXS_PAD_FEC, | ||
| 71 | MX28_PAD_ENET_CLK__CLKCTRL_ENET | MXS_PAD_FEC, | ||
| 72 | /* fec1 */ | ||
| 73 | MX28_PAD_ENET0_CRS__ENET1_RX_EN | MXS_PAD_FEC, | ||
| 74 | MX28_PAD_ENET0_RXD2__ENET1_RXD0 | MXS_PAD_FEC, | ||
| 75 | MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MXS_PAD_FEC, | ||
| 76 | MX28_PAD_ENET0_COL__ENET1_TX_EN | MXS_PAD_FEC, | ||
| 77 | MX28_PAD_ENET0_TXD2__ENET1_TXD0 | MXS_PAD_FEC, | ||
| 78 | MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MXS_PAD_FEC, | ||
| 79 | |||
| 80 | /* flexcan0 */ | ||
| 81 | MX28_PAD_GPMI_RDY2__CAN0_TX, | ||
| 82 | MX28_PAD_GPMI_RDY3__CAN0_RX, | ||
| 83 | |||
| 84 | /* flexcan1 */ | ||
| 85 | MX28_PAD_GPMI_CE2N__CAN1_TX, | ||
| 86 | MX28_PAD_GPMI_CE3N__CAN1_RX, | ||
| 87 | |||
| 88 | /* I2C */ | ||
| 89 | MX28_PAD_I2C0_SCL__I2C0_SCL, | ||
| 90 | MX28_PAD_I2C0_SDA__I2C0_SDA, | ||
| 91 | |||
| 92 | /* mxsfb (lcdif) */ | ||
| 93 | MX28_PAD_LCD_D00__LCD_D0 | MXS_PAD_CTRL, | ||
| 94 | MX28_PAD_LCD_D01__LCD_D1 | MXS_PAD_CTRL, | ||
| 95 | MX28_PAD_LCD_D02__LCD_D2 | MXS_PAD_CTRL, | ||
| 96 | MX28_PAD_LCD_D03__LCD_D3 | MXS_PAD_CTRL, | ||
| 97 | MX28_PAD_LCD_D04__LCD_D4 | MXS_PAD_CTRL, | ||
| 98 | MX28_PAD_LCD_D05__LCD_D5 | MXS_PAD_CTRL, | ||
| 99 | MX28_PAD_LCD_D06__LCD_D6 | MXS_PAD_CTRL, | ||
| 100 | MX28_PAD_LCD_D07__LCD_D7 | MXS_PAD_CTRL, | ||
| 101 | MX28_PAD_LCD_D08__LCD_D8 | MXS_PAD_CTRL, | ||
| 102 | MX28_PAD_LCD_D09__LCD_D9 | MXS_PAD_CTRL, | ||
| 103 | MX28_PAD_LCD_D10__LCD_D10 | MXS_PAD_CTRL, | ||
| 104 | MX28_PAD_LCD_D11__LCD_D11 | MXS_PAD_CTRL, | ||
| 105 | MX28_PAD_LCD_D12__LCD_D12 | MXS_PAD_CTRL, | ||
| 106 | MX28_PAD_LCD_D13__LCD_D13 | MXS_PAD_CTRL, | ||
| 107 | MX28_PAD_LCD_D14__LCD_D14 | MXS_PAD_CTRL, | ||
| 108 | MX28_PAD_LCD_D15__LCD_D15 | MXS_PAD_CTRL, | ||
| 109 | MX28_PAD_LCD_D16__LCD_D16 | MXS_PAD_CTRL, | ||
| 110 | MX28_PAD_LCD_D17__LCD_D17 | MXS_PAD_CTRL, | ||
| 111 | MX28_PAD_LCD_D18__LCD_D18 | MXS_PAD_CTRL, | ||
| 112 | MX28_PAD_LCD_D19__LCD_D19 | MXS_PAD_CTRL, | ||
| 113 | MX28_PAD_LCD_D20__LCD_D20 | MXS_PAD_CTRL, | ||
| 114 | MX28_PAD_LCD_D21__LCD_D21 | MXS_PAD_CTRL, | ||
| 115 | MX28_PAD_LCD_D22__LCD_D22 | MXS_PAD_CTRL, | ||
| 116 | MX28_PAD_LCD_D23__LCD_D23 | MXS_PAD_CTRL, | ||
| 117 | |||
| 118 | MX28_PAD_LCD_ENABLE__LCD_ENABLE | MXS_PAD_CTRL, | ||
| 119 | MX28_PAD_LCD_DOTCLK__LCD_DOTCLK | MXS_PAD_CTRL, | ||
| 120 | |||
| 121 | /* mmc0 */ | ||
| 122 | MX28_PAD_SSP0_DATA0__SSP0_D0 | | ||
| 123 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 124 | MX28_PAD_SSP0_DATA1__SSP0_D1 | | ||
| 125 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 126 | MX28_PAD_SSP0_DATA2__SSP0_D2 | | ||
| 127 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 128 | MX28_PAD_SSP0_DATA3__SSP0_D3 | | ||
| 129 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 130 | MX28_PAD_SSP0_DATA4__SSP0_D4 | | ||
| 131 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 132 | MX28_PAD_SSP0_DATA5__SSP0_D5 | | ||
| 133 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 134 | MX28_PAD_SSP0_DATA6__SSP0_D6 | | ||
| 135 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 136 | MX28_PAD_SSP0_DATA7__SSP0_D7 | | ||
| 137 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 138 | MX28_PAD_SSP0_CMD__SSP0_CMD | | ||
| 139 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 140 | MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT | | ||
| 141 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), | ||
| 142 | MX28_PAD_SSP0_SCK__SSP0_SCK | | ||
| 143 | (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), | ||
| 144 | |||
| 145 | /* mmc1 */ | ||
| 146 | MX28_PAD_GPMI_D00__SSP1_D0 | | ||
| 147 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 148 | MX28_PAD_GPMI_D01__SSP1_D1 | | ||
| 149 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 150 | MX28_PAD_GPMI_D02__SSP1_D2 | | ||
| 151 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 152 | MX28_PAD_GPMI_D03__SSP1_D3 | | ||
| 153 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 154 | MX28_PAD_GPMI_D04__SSP1_D4 | | ||
| 155 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 156 | MX28_PAD_GPMI_D05__SSP1_D5 | | ||
| 157 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 158 | MX28_PAD_GPMI_D06__SSP1_D6 | | ||
| 159 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 160 | MX28_PAD_GPMI_D07__SSP1_D7 | | ||
| 161 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 162 | MX28_PAD_GPMI_RDY1__SSP1_CMD | | ||
| 163 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 164 | MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT | | ||
| 165 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), | ||
| 166 | MX28_PAD_GPMI_WRN__SSP1_SCK | | ||
| 167 | (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), | ||
| 168 | /* write protect */ | ||
| 169 | MX28_PAD_GPMI_RESETN__GPIO_0_28 | | ||
| 170 | (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), | ||
| 171 | /* slot power enable */ | ||
| 172 | MX28_PAD_PWM4__GPIO_3_29 | | ||
| 173 | (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), | ||
| 174 | |||
| 175 | /* led */ | ||
| 176 | MX28_PAD_PWM0__GPIO_3_16 | MXS_PAD_CTRL, | ||
| 177 | MX28_PAD_PWM1__GPIO_3_17 | MXS_PAD_CTRL, | ||
| 178 | |||
| 179 | /* nand */ | ||
| 180 | MX28_PAD_GPMI_D00__GPMI_D0 | | ||
| 181 | (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL), | ||
| 182 | MX28_PAD_GPMI_D01__GPMI_D1 | | ||
| 183 | (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL), | ||
| 184 | MX28_PAD_GPMI_D02__GPMI_D2 | | ||
| 185 | (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL), | ||
| 186 | MX28_PAD_GPMI_D03__GPMI_D3 | | ||
| 187 | (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL), | ||
| 188 | MX28_PAD_GPMI_D04__GPMI_D4 | | ||
| 189 | (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL), | ||
| 190 | MX28_PAD_GPMI_D05__GPMI_D5 | | ||
| 191 | (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL), | ||
| 192 | MX28_PAD_GPMI_D06__GPMI_D6 | | ||
| 193 | (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL), | ||
| 194 | MX28_PAD_GPMI_D07__GPMI_D7 | | ||
| 195 | (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL), | ||
| 196 | MX28_PAD_GPMI_CE0N__GPMI_CE0N | | ||
| 197 | (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL), | ||
| 198 | MX28_PAD_GPMI_RDY0__GPMI_READY0 | | ||
| 199 | (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL), | ||
| 200 | MX28_PAD_GPMI_RDN__GPMI_RDN | | ||
| 201 | (MXS_PAD_12MA | MXS_PAD_1V8 | MXS_PAD_PULLUP), | ||
| 202 | MX28_PAD_GPMI_WRN__GPMI_WRN | | ||
| 203 | (MXS_PAD_12MA | MXS_PAD_1V8 | MXS_PAD_PULLUP), | ||
| 204 | MX28_PAD_GPMI_ALE__GPMI_ALE | | ||
| 205 | (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_PULLUP), | ||
| 206 | MX28_PAD_GPMI_CLE__GPMI_CLE | | ||
| 207 | (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_PULLUP), | ||
| 208 | MX28_PAD_GPMI_RESETN__GPMI_RESETN | | ||
| 209 | (MXS_PAD_12MA | MXS_PAD_1V8 | MXS_PAD_PULLUP), | ||
| 210 | |||
| 211 | /* Backlight */ | ||
| 212 | MX28_PAD_PWM3__GPIO_3_28 | MXS_PAD_CTRL, | ||
| 213 | }; | ||
| 214 | |||
| 215 | /* led */ | ||
| 216 | static const struct gpio_led m28evk_leds[] __initconst = { | ||
| 217 | { | ||
| 218 | .name = "user-led1", | ||
| 219 | .default_trigger = "heartbeat", | ||
| 220 | .gpio = M28EVK_GPIO_USERLED1, | ||
| 221 | }, | ||
| 222 | { | ||
| 223 | .name = "user-led2", | ||
| 224 | .default_trigger = "heartbeat", | ||
| 225 | .gpio = M28EVK_GPIO_USERLED2, | ||
| 226 | }, | ||
| 227 | }; | ||
| 228 | |||
| 229 | static const struct gpio_led_platform_data m28evk_led_data __initconst = { | ||
| 230 | .leds = m28evk_leds, | ||
| 231 | .num_leds = ARRAY_SIZE(m28evk_leds), | ||
| 232 | }; | ||
| 233 | |||
| 234 | static struct fec_platform_data mx28_fec_pdata[] __initdata = { | ||
| 235 | { | ||
| 236 | /* fec0 */ | ||
| 237 | .phy = PHY_INTERFACE_MODE_RMII, | ||
| 238 | }, { | ||
| 239 | /* fec1 */ | ||
| 240 | .phy = PHY_INTERFACE_MODE_RMII, | ||
| 241 | }, | ||
| 242 | }; | ||
| 243 | |||
| 244 | static int __init m28evk_fec_get_mac(void) | ||
| 245 | { | ||
| 246 | int i; | ||
| 247 | u32 val; | ||
| 248 | const u32 *ocotp = mxs_get_ocotp(); | ||
| 249 | |||
| 250 | if (!ocotp) | ||
| 251 | return -ETIMEDOUT; | ||
| 252 | |||
| 253 | /* | ||
| 254 | * OCOTP only stores the last 4 octets for each mac address, | ||
| 255 | * so hard-code DENX OUI (C0:E5:4E) here. | ||
| 256 | */ | ||
| 257 | for (i = 0; i < 2; i++) { | ||
| 258 | val = ocotp[i]; | ||
| 259 | mx28_fec_pdata[i].mac[0] = 0xC0; | ||
| 260 | mx28_fec_pdata[i].mac[1] = 0xE5; | ||
| 261 | mx28_fec_pdata[i].mac[2] = 0x4E; | ||
| 262 | mx28_fec_pdata[i].mac[3] = (val >> 16) & 0xff; | ||
| 263 | mx28_fec_pdata[i].mac[4] = (val >> 8) & 0xff; | ||
| 264 | mx28_fec_pdata[i].mac[5] = (val >> 0) & 0xff; | ||
| 265 | } | ||
| 266 | |||
| 267 | return 0; | ||
| 268 | } | ||
| 269 | |||
| 270 | /* mxsfb (lcdif) */ | ||
| 271 | static struct fb_videomode m28evk_video_modes[] = { | ||
| 272 | { | ||
| 273 | .name = "Ampire AM-800480R2TMQW-T01H", | ||
| 274 | .refresh = 60, | ||
| 275 | .xres = 800, | ||
| 276 | .yres = 480, | ||
| 277 | .pixclock = 30066, /* picosecond (33.26 MHz) */ | ||
| 278 | .left_margin = 0, | ||
| 279 | .right_margin = 256, | ||
| 280 | .upper_margin = 0, | ||
| 281 | .lower_margin = 45, | ||
| 282 | .hsync_len = 1, | ||
| 283 | .vsync_len = 1, | ||
| 284 | .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT, | ||
| 285 | }, | ||
| 286 | }; | ||
| 287 | |||
| 288 | static const struct mxsfb_platform_data m28evk_mxsfb_pdata __initconst = { | ||
| 289 | .mode_list = m28evk_video_modes, | ||
| 290 | .mode_count = ARRAY_SIZE(m28evk_video_modes), | ||
| 291 | .default_bpp = 16, | ||
| 292 | .ld_intf_width = STMLCDIF_18BIT, | ||
| 293 | }; | ||
| 294 | |||
| 295 | static struct at24_platform_data m28evk_eeprom = { | ||
| 296 | .byte_len = 16384, | ||
| 297 | .page_size = 32, | ||
| 298 | .flags = AT24_FLAG_ADDR16, | ||
| 299 | }; | ||
| 300 | |||
| 301 | static struct i2c_board_info m28_stk5v3_i2c_boardinfo[] __initdata = { | ||
| 302 | { | ||
| 303 | I2C_BOARD_INFO("at24", 0x51), /* E0=1, E1=0, E2=0 */ | ||
| 304 | .platform_data = &m28evk_eeprom, | ||
| 305 | }, | ||
| 306 | }; | ||
| 307 | |||
| 308 | static struct mxs_mmc_platform_data m28evk_mmc_pdata[] __initdata = { | ||
| 309 | { | ||
| 310 | /* mmc0 */ | ||
| 311 | .wp_gpio = MX28EVK_MMC0_WRITE_PROTECT, | ||
| 312 | .flags = SLOTF_8_BIT_CAPABLE, | ||
| 313 | }, { | ||
| 314 | /* mmc1 */ | ||
| 315 | .wp_gpio = MX28EVK_MMC1_WRITE_PROTECT, | ||
| 316 | .flags = SLOTF_8_BIT_CAPABLE, | ||
| 317 | }, | ||
| 318 | }; | ||
| 319 | |||
| 320 | static void __init m28evk_init(void) | ||
| 321 | { | ||
| 322 | mx28_soc_init(); | ||
| 323 | |||
| 324 | mxs_iomux_setup_multiple_pads(m28evk_pads, ARRAY_SIZE(m28evk_pads)); | ||
| 325 | |||
| 326 | mx28_add_duart(); | ||
| 327 | mx28_add_auart0(); | ||
| 328 | mx28_add_auart3(); | ||
| 329 | |||
| 330 | if (!m28evk_fec_get_mac()) { | ||
| 331 | mx28_add_fec(0, &mx28_fec_pdata[0]); | ||
| 332 | mx28_add_fec(1, &mx28_fec_pdata[1]); | ||
| 333 | } | ||
| 334 | |||
| 335 | mx28_add_flexcan(0, NULL); | ||
| 336 | mx28_add_flexcan(1, NULL); | ||
| 337 | |||
| 338 | mx28_add_mxsfb(&m28evk_mxsfb_pdata); | ||
| 339 | |||
| 340 | mx28_add_mxs_mmc(0, &m28evk_mmc_pdata[0]); | ||
| 341 | mx28_add_mxs_mmc(1, &m28evk_mmc_pdata[1]); | ||
| 342 | |||
| 343 | gpio_led_register_device(0, &m28evk_led_data); | ||
| 344 | |||
| 345 | /* I2C */ | ||
| 346 | mx28_add_mxs_i2c(0); | ||
| 347 | i2c_register_board_info(0, m28_stk5v3_i2c_boardinfo, | ||
| 348 | ARRAY_SIZE(m28_stk5v3_i2c_boardinfo)); | ||
| 349 | } | ||
| 350 | |||
| 351 | static void __init m28evk_timer_init(void) | ||
| 352 | { | ||
| 353 | mx28_clocks_init(); | ||
| 354 | } | ||
| 355 | |||
| 356 | static struct sys_timer m28evk_timer = { | ||
| 357 | .init = m28evk_timer_init, | ||
| 358 | }; | ||
| 359 | |||
| 360 | MACHINE_START(M28EVK, "DENX M28 EVK") | ||
| 361 | .map_io = mx28_map_io, | ||
| 362 | .init_irq = mx28_init_irq, | ||
| 363 | .timer = &m28evk_timer, | ||
| 364 | .init_machine = m28evk_init, | ||
| 365 | .restart = mxs_restart, | ||
| 366 | MACHINE_END | ||
diff --git a/arch/arm/mach-mxs/mach-mx23evk.c b/arch/arm/mach-mxs/mach-mx23evk.c deleted file mode 100644 index e7272a41939d..000000000000 --- a/arch/arm/mach-mxs/mach-mx23evk.c +++ /dev/null | |||
| @@ -1,190 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License as published by | ||
| 6 | * the Free Software Foundation; either version 2 of the License, or | ||
| 7 | * (at your option) any later version. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #include <linux/delay.h> | ||
| 16 | #include <linux/platform_device.h> | ||
| 17 | #include <linux/gpio.h> | ||
| 18 | |||
| 19 | #include <asm/mach-types.h> | ||
| 20 | #include <asm/mach/arch.h> | ||
| 21 | #include <asm/mach/time.h> | ||
| 22 | |||
| 23 | #include <mach/common.h> | ||
| 24 | #include <mach/iomux-mx23.h> | ||
| 25 | |||
| 26 | #include "devices-mx23.h" | ||
| 27 | |||
| 28 | #define MX23EVK_LCD_ENABLE MXS_GPIO_NR(1, 18) | ||
| 29 | #define MX23EVK_BL_ENABLE MXS_GPIO_NR(1, 28) | ||
| 30 | #define MX23EVK_MMC0_WRITE_PROTECT MXS_GPIO_NR(1, 30) | ||
| 31 | #define MX23EVK_MMC0_SLOT_POWER MXS_GPIO_NR(1, 29) | ||
| 32 | |||
| 33 | static const iomux_cfg_t mx23evk_pads[] __initconst = { | ||
| 34 | /* duart */ | ||
| 35 | MX23_PAD_PWM0__DUART_RX | MXS_PAD_CTRL, | ||
| 36 | MX23_PAD_PWM1__DUART_TX | MXS_PAD_CTRL, | ||
| 37 | |||
| 38 | /* auart */ | ||
| 39 | MX23_PAD_AUART1_RX__AUART1_RX | MXS_PAD_CTRL, | ||
| 40 | MX23_PAD_AUART1_TX__AUART1_TX | MXS_PAD_CTRL, | ||
| 41 | MX23_PAD_AUART1_CTS__AUART1_CTS | MXS_PAD_CTRL, | ||
| 42 | MX23_PAD_AUART1_RTS__AUART1_RTS | MXS_PAD_CTRL, | ||
| 43 | |||
| 44 | /* mxsfb (lcdif) */ | ||
| 45 | MX23_PAD_LCD_D00__LCD_D00 | MXS_PAD_CTRL, | ||
| 46 | MX23_PAD_LCD_D01__LCD_D01 | MXS_PAD_CTRL, | ||
| 47 | MX23_PAD_LCD_D02__LCD_D02 | MXS_PAD_CTRL, | ||
| 48 | MX23_PAD_LCD_D03__LCD_D03 | MXS_PAD_CTRL, | ||
| 49 | MX23_PAD_LCD_D04__LCD_D04 | MXS_PAD_CTRL, | ||
| 50 | MX23_PAD_LCD_D05__LCD_D05 | MXS_PAD_CTRL, | ||
| 51 | MX23_PAD_LCD_D06__LCD_D06 | MXS_PAD_CTRL, | ||
| 52 | MX23_PAD_LCD_D07__LCD_D07 | MXS_PAD_CTRL, | ||
| 53 | MX23_PAD_LCD_D08__LCD_D08 | MXS_PAD_CTRL, | ||
| 54 | MX23_PAD_LCD_D09__LCD_D09 | MXS_PAD_CTRL, | ||
| 55 | MX23_PAD_LCD_D10__LCD_D10 | MXS_PAD_CTRL, | ||
| 56 | MX23_PAD_LCD_D11__LCD_D11 | MXS_PAD_CTRL, | ||
| 57 | MX23_PAD_LCD_D12__LCD_D12 | MXS_PAD_CTRL, | ||
| 58 | MX23_PAD_LCD_D13__LCD_D13 | MXS_PAD_CTRL, | ||
| 59 | MX23_PAD_LCD_D14__LCD_D14 | MXS_PAD_CTRL, | ||
| 60 | MX23_PAD_LCD_D15__LCD_D15 | MXS_PAD_CTRL, | ||
| 61 | MX23_PAD_LCD_D16__LCD_D16 | MXS_PAD_CTRL, | ||
| 62 | MX23_PAD_LCD_D17__LCD_D17 | MXS_PAD_CTRL, | ||
| 63 | MX23_PAD_GPMI_D08__LCD_D18 | MXS_PAD_CTRL, | ||
| 64 | MX23_PAD_GPMI_D09__LCD_D19 | MXS_PAD_CTRL, | ||
| 65 | MX23_PAD_GPMI_D10__LCD_D20 | MXS_PAD_CTRL, | ||
| 66 | MX23_PAD_GPMI_D11__LCD_D21 | MXS_PAD_CTRL, | ||
| 67 | MX23_PAD_GPMI_D12__LCD_D22 | MXS_PAD_CTRL, | ||
| 68 | MX23_PAD_GPMI_D13__LCD_D23 | MXS_PAD_CTRL, | ||
| 69 | MX23_PAD_LCD_VSYNC__LCD_VSYNC | MXS_PAD_CTRL, | ||
| 70 | MX23_PAD_LCD_HSYNC__LCD_HSYNC | MXS_PAD_CTRL, | ||
| 71 | MX23_PAD_LCD_DOTCK__LCD_DOTCK | MXS_PAD_CTRL, | ||
| 72 | MX23_PAD_LCD_ENABLE__LCD_ENABLE | MXS_PAD_CTRL, | ||
| 73 | /* LCD panel enable */ | ||
| 74 | MX23_PAD_LCD_RESET__GPIO_1_18 | MXS_PAD_CTRL, | ||
| 75 | /* backlight control */ | ||
| 76 | MX23_PAD_PWM2__GPIO_1_28 | MXS_PAD_CTRL, | ||
| 77 | |||
| 78 | /* mmc */ | ||
| 79 | MX23_PAD_SSP1_DATA0__SSP1_DATA0 | | ||
| 80 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 81 | MX23_PAD_SSP1_DATA1__SSP1_DATA1 | | ||
| 82 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 83 | MX23_PAD_SSP1_DATA2__SSP1_DATA2 | | ||
| 84 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 85 | MX23_PAD_SSP1_DATA3__SSP1_DATA3 | | ||
| 86 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 87 | MX23_PAD_GPMI_D08__SSP1_DATA4 | | ||
| 88 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 89 | MX23_PAD_GPMI_D09__SSP1_DATA5 | | ||
| 90 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 91 | MX23_PAD_GPMI_D10__SSP1_DATA6 | | ||
| 92 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 93 | MX23_PAD_GPMI_D11__SSP1_DATA7 | | ||
| 94 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 95 | MX23_PAD_SSP1_CMD__SSP1_CMD | | ||
| 96 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 97 | MX23_PAD_SSP1_DETECT__SSP1_DETECT | | ||
| 98 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), | ||
| 99 | MX23_PAD_SSP1_SCK__SSP1_SCK | | ||
| 100 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), | ||
| 101 | /* write protect */ | ||
| 102 | MX23_PAD_PWM4__GPIO_1_30 | | ||
| 103 | (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), | ||
| 104 | /* slot power enable */ | ||
| 105 | MX23_PAD_PWM3__GPIO_1_29 | | ||
| 106 | (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), | ||
| 107 | }; | ||
| 108 | |||
| 109 | /* mxsfb (lcdif) */ | ||
| 110 | static struct fb_videomode mx23evk_video_modes[] = { | ||
| 111 | { | ||
| 112 | .name = "Samsung-LMS430HF02", | ||
| 113 | .refresh = 60, | ||
| 114 | .xres = 480, | ||
| 115 | .yres = 272, | ||
| 116 | .pixclock = 108096, /* picosecond (9.2 MHz) */ | ||
| 117 | .left_margin = 15, | ||
| 118 | .right_margin = 8, | ||
| 119 | .upper_margin = 12, | ||
| 120 | .lower_margin = 4, | ||
| 121 | .hsync_len = 1, | ||
| 122 | .vsync_len = 1, | ||
| 123 | .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT | | ||
| 124 | FB_SYNC_DOTCLK_FAILING_ACT, | ||
| 125 | }, | ||
| 126 | }; | ||
| 127 | |||
| 128 | static const struct mxsfb_platform_data mx23evk_mxsfb_pdata __initconst = { | ||
| 129 | .mode_list = mx23evk_video_modes, | ||
| 130 | .mode_count = ARRAY_SIZE(mx23evk_video_modes), | ||
| 131 | .default_bpp = 32, | ||
| 132 | .ld_intf_width = STMLCDIF_24BIT, | ||
| 133 | }; | ||
| 134 | |||
| 135 | static struct mxs_mmc_platform_data mx23evk_mmc_pdata __initdata = { | ||
| 136 | .wp_gpio = MX23EVK_MMC0_WRITE_PROTECT, | ||
| 137 | .flags = SLOTF_8_BIT_CAPABLE, | ||
| 138 | }; | ||
| 139 | |||
| 140 | static void __init mx23evk_init(void) | ||
| 141 | { | ||
| 142 | int ret; | ||
| 143 | |||
| 144 | mx23_soc_init(); | ||
| 145 | |||
| 146 | mxs_iomux_setup_multiple_pads(mx23evk_pads, ARRAY_SIZE(mx23evk_pads)); | ||
| 147 | |||
| 148 | mx23_add_duart(); | ||
| 149 | mx23_add_auart0(); | ||
| 150 | |||
| 151 | /* power on mmc slot by writing 0 to the gpio */ | ||
| 152 | ret = gpio_request_one(MX23EVK_MMC0_SLOT_POWER, GPIOF_OUT_INIT_LOW, | ||
| 153 | "mmc0-slot-power"); | ||
| 154 | if (ret) | ||
| 155 | pr_warn("failed to request gpio mmc0-slot-power: %d\n", ret); | ||
| 156 | mx23_add_mxs_mmc(0, &mx23evk_mmc_pdata); | ||
| 157 | |||
| 158 | ret = gpio_request_one(MX23EVK_LCD_ENABLE, GPIOF_DIR_OUT, "lcd-enable"); | ||
| 159 | if (ret) | ||
| 160 | pr_warn("failed to request gpio lcd-enable: %d\n", ret); | ||
| 161 | else | ||
| 162 | gpio_set_value(MX23EVK_LCD_ENABLE, 1); | ||
| 163 | |||
| 164 | ret = gpio_request_one(MX23EVK_BL_ENABLE, GPIOF_DIR_OUT, "bl-enable"); | ||
| 165 | if (ret) | ||
| 166 | pr_warn("failed to request gpio bl-enable: %d\n", ret); | ||
| 167 | else | ||
| 168 | gpio_set_value(MX23EVK_BL_ENABLE, 1); | ||
| 169 | |||
| 170 | mx23_add_mxsfb(&mx23evk_mxsfb_pdata); | ||
| 171 | mx23_add_rtc_stmp3xxx(); | ||
| 172 | } | ||
| 173 | |||
| 174 | static void __init mx23evk_timer_init(void) | ||
| 175 | { | ||
| 176 | mx23_clocks_init(); | ||
| 177 | } | ||
| 178 | |||
| 179 | static struct sys_timer mx23evk_timer = { | ||
| 180 | .init = mx23evk_timer_init, | ||
| 181 | }; | ||
| 182 | |||
| 183 | MACHINE_START(MX23EVK, "Freescale MX23 EVK") | ||
| 184 | /* Maintainer: Freescale Semiconductor, Inc. */ | ||
| 185 | .map_io = mx23_map_io, | ||
| 186 | .init_irq = mx23_init_irq, | ||
| 187 | .timer = &mx23evk_timer, | ||
| 188 | .init_machine = mx23evk_init, | ||
| 189 | .restart = mxs_restart, | ||
| 190 | MACHINE_END | ||
diff --git a/arch/arm/mach-mxs/mach-mx28evk.c b/arch/arm/mach-mxs/mach-mx28evk.c deleted file mode 100644 index dafd48e86c8c..000000000000 --- a/arch/arm/mach-mxs/mach-mx28evk.c +++ /dev/null | |||
| @@ -1,477 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License as published by | ||
| 6 | * the Free Software Foundation; either version 2 of the License, or | ||
| 7 | * (at your option) any later version. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #include <linux/delay.h> | ||
| 16 | #include <linux/platform_device.h> | ||
| 17 | #include <linux/gpio.h> | ||
| 18 | #include <linux/leds.h> | ||
| 19 | #include <linux/clk.h> | ||
| 20 | #include <linux/i2c.h> | ||
| 21 | #include <linux/regulator/machine.h> | ||
| 22 | #include <linux/regulator/fixed.h> | ||
| 23 | |||
| 24 | #include <asm/mach-types.h> | ||
| 25 | #include <asm/mach/arch.h> | ||
| 26 | #include <asm/mach/time.h> | ||
| 27 | |||
| 28 | #include <mach/common.h> | ||
| 29 | #include <mach/iomux-mx28.h> | ||
| 30 | #include <mach/digctl.h> | ||
| 31 | |||
| 32 | #include "devices-mx28.h" | ||
| 33 | |||
| 34 | #define MX28EVK_FLEXCAN_SWITCH MXS_GPIO_NR(2, 13) | ||
| 35 | #define MX28EVK_FEC_PHY_POWER MXS_GPIO_NR(2, 15) | ||
| 36 | #define MX28EVK_GPIO_LED MXS_GPIO_NR(3, 5) | ||
| 37 | #define MX28EVK_BL_ENABLE MXS_GPIO_NR(3, 18) | ||
| 38 | #define MX28EVK_LCD_ENABLE MXS_GPIO_NR(3, 30) | ||
| 39 | #define MX28EVK_FEC_PHY_RESET MXS_GPIO_NR(4, 13) | ||
| 40 | |||
| 41 | #define MX28EVK_MMC0_WRITE_PROTECT MXS_GPIO_NR(2, 12) | ||
| 42 | #define MX28EVK_MMC1_WRITE_PROTECT MXS_GPIO_NR(0, 28) | ||
| 43 | #define MX28EVK_MMC0_SLOT_POWER MXS_GPIO_NR(3, 28) | ||
| 44 | #define MX28EVK_MMC1_SLOT_POWER MXS_GPIO_NR(3, 29) | ||
| 45 | |||
| 46 | static const iomux_cfg_t mx28evk_pads[] __initconst = { | ||
| 47 | /* duart */ | ||
| 48 | MX28_PAD_PWM0__DUART_RX | MXS_PAD_CTRL, | ||
| 49 | MX28_PAD_PWM1__DUART_TX | MXS_PAD_CTRL, | ||
| 50 | |||
| 51 | /* auart0 */ | ||
| 52 | MX28_PAD_AUART0_RX__AUART0_RX | MXS_PAD_CTRL, | ||
| 53 | MX28_PAD_AUART0_TX__AUART0_TX | MXS_PAD_CTRL, | ||
| 54 | MX28_PAD_AUART0_CTS__AUART0_CTS | MXS_PAD_CTRL, | ||
| 55 | MX28_PAD_AUART0_RTS__AUART0_RTS | MXS_PAD_CTRL, | ||
| 56 | /* auart3 */ | ||
| 57 | MX28_PAD_AUART3_RX__AUART3_RX | MXS_PAD_CTRL, | ||
| 58 | MX28_PAD_AUART3_TX__AUART3_TX | MXS_PAD_CTRL, | ||
| 59 | MX28_PAD_AUART3_CTS__AUART3_CTS | MXS_PAD_CTRL, | ||
| 60 | MX28_PAD_AUART3_RTS__AUART3_RTS | MXS_PAD_CTRL, | ||
| 61 | |||
| 62 | #define MXS_PAD_FEC (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP) | ||
| 63 | /* fec0 */ | ||
| 64 | MX28_PAD_ENET0_MDC__ENET0_MDC | MXS_PAD_FEC, | ||
| 65 | MX28_PAD_ENET0_MDIO__ENET0_MDIO | MXS_PAD_FEC, | ||
| 66 | MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MXS_PAD_FEC, | ||
| 67 | MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MXS_PAD_FEC, | ||
| 68 | MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MXS_PAD_FEC, | ||
| 69 | MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MXS_PAD_FEC, | ||
| 70 | MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MXS_PAD_FEC, | ||
| 71 | MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MXS_PAD_FEC, | ||
| 72 | MX28_PAD_ENET_CLK__CLKCTRL_ENET | MXS_PAD_FEC, | ||
| 73 | /* fec1 */ | ||
| 74 | MX28_PAD_ENET0_CRS__ENET1_RX_EN | MXS_PAD_FEC, | ||
| 75 | MX28_PAD_ENET0_RXD2__ENET1_RXD0 | MXS_PAD_FEC, | ||
| 76 | MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MXS_PAD_FEC, | ||
| 77 | MX28_PAD_ENET0_COL__ENET1_TX_EN | MXS_PAD_FEC, | ||
| 78 | MX28_PAD_ENET0_TXD2__ENET1_TXD0 | MXS_PAD_FEC, | ||
| 79 | MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MXS_PAD_FEC, | ||
| 80 | /* phy power line */ | ||
| 81 | MX28_PAD_SSP1_DATA3__GPIO_2_15 | MXS_PAD_CTRL, | ||
| 82 | /* phy reset line */ | ||
| 83 | MX28_PAD_ENET0_RX_CLK__GPIO_4_13 | MXS_PAD_CTRL, | ||
| 84 | |||
| 85 | /* flexcan0 */ | ||
| 86 | MX28_PAD_GPMI_RDY2__CAN0_TX, | ||
| 87 | MX28_PAD_GPMI_RDY3__CAN0_RX, | ||
| 88 | /* flexcan1 */ | ||
| 89 | MX28_PAD_GPMI_CE2N__CAN1_TX, | ||
| 90 | MX28_PAD_GPMI_CE3N__CAN1_RX, | ||
| 91 | /* transceiver power control */ | ||
| 92 | MX28_PAD_SSP1_CMD__GPIO_2_13, | ||
| 93 | |||
| 94 | /* mxsfb (lcdif) */ | ||
| 95 | MX28_PAD_LCD_D00__LCD_D0 | MXS_PAD_CTRL, | ||
| 96 | MX28_PAD_LCD_D01__LCD_D1 | MXS_PAD_CTRL, | ||
| 97 | MX28_PAD_LCD_D02__LCD_D2 | MXS_PAD_CTRL, | ||
| 98 | MX28_PAD_LCD_D03__LCD_D3 | MXS_PAD_CTRL, | ||
| 99 | MX28_PAD_LCD_D04__LCD_D4 | MXS_PAD_CTRL, | ||
| 100 | MX28_PAD_LCD_D05__LCD_D5 | MXS_PAD_CTRL, | ||
| 101 | MX28_PAD_LCD_D06__LCD_D6 | MXS_PAD_CTRL, | ||
| 102 | MX28_PAD_LCD_D07__LCD_D7 | MXS_PAD_CTRL, | ||
| 103 | MX28_PAD_LCD_D08__LCD_D8 | MXS_PAD_CTRL, | ||
| 104 | MX28_PAD_LCD_D09__LCD_D9 | MXS_PAD_CTRL, | ||
| 105 | MX28_PAD_LCD_D10__LCD_D10 | MXS_PAD_CTRL, | ||
| 106 | MX28_PAD_LCD_D11__LCD_D11 | MXS_PAD_CTRL, | ||
| 107 | MX28_PAD_LCD_D12__LCD_D12 | MXS_PAD_CTRL, | ||
| 108 | MX28_PAD_LCD_D13__LCD_D13 | MXS_PAD_CTRL, | ||
| 109 | MX28_PAD_LCD_D14__LCD_D14 | MXS_PAD_CTRL, | ||
| 110 | MX28_PAD_LCD_D15__LCD_D15 | MXS_PAD_CTRL, | ||
| 111 | MX28_PAD_LCD_D16__LCD_D16 | MXS_PAD_CTRL, | ||
| 112 | MX28_PAD_LCD_D17__LCD_D17 | MXS_PAD_CTRL, | ||
| 113 | MX28_PAD_LCD_D18__LCD_D18 | MXS_PAD_CTRL, | ||
| 114 | MX28_PAD_LCD_D19__LCD_D19 | MXS_PAD_CTRL, | ||
| 115 | MX28_PAD_LCD_D20__LCD_D20 | MXS_PAD_CTRL, | ||
| 116 | MX28_PAD_LCD_D21__LCD_D21 | MXS_PAD_CTRL, | ||
| 117 | MX28_PAD_LCD_D22__LCD_D22 | MXS_PAD_CTRL, | ||
| 118 | MX28_PAD_LCD_D23__LCD_D23 | MXS_PAD_CTRL, | ||
| 119 | MX28_PAD_LCD_RD_E__LCD_VSYNC | MXS_PAD_CTRL, | ||
| 120 | MX28_PAD_LCD_WR_RWN__LCD_HSYNC | MXS_PAD_CTRL, | ||
| 121 | MX28_PAD_LCD_RS__LCD_DOTCLK | MXS_PAD_CTRL, | ||
| 122 | MX28_PAD_LCD_CS__LCD_ENABLE | MXS_PAD_CTRL, | ||
| 123 | /* LCD panel enable */ | ||
| 124 | MX28_PAD_LCD_RESET__GPIO_3_30 | MXS_PAD_CTRL, | ||
| 125 | /* backlight control */ | ||
| 126 | MX28_PAD_PWM2__GPIO_3_18 | MXS_PAD_CTRL, | ||
| 127 | /* mmc0 */ | ||
| 128 | MX28_PAD_SSP0_DATA0__SSP0_D0 | | ||
| 129 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 130 | MX28_PAD_SSP0_DATA1__SSP0_D1 | | ||
| 131 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 132 | MX28_PAD_SSP0_DATA2__SSP0_D2 | | ||
| 133 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 134 | MX28_PAD_SSP0_DATA3__SSP0_D3 | | ||
| 135 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 136 | MX28_PAD_SSP0_DATA4__SSP0_D4 | | ||
| 137 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 138 | MX28_PAD_SSP0_DATA5__SSP0_D5 | | ||
| 139 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 140 | MX28_PAD_SSP0_DATA6__SSP0_D6 | | ||
| 141 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 142 | MX28_PAD_SSP0_DATA7__SSP0_D7 | | ||
| 143 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 144 | MX28_PAD_SSP0_CMD__SSP0_CMD | | ||
| 145 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 146 | MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT | | ||
| 147 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), | ||
| 148 | MX28_PAD_SSP0_SCK__SSP0_SCK | | ||
| 149 | (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), | ||
| 150 | /* write protect */ | ||
| 151 | MX28_PAD_SSP1_SCK__GPIO_2_12 | | ||
| 152 | (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), | ||
| 153 | /* slot power enable */ | ||
| 154 | MX28_PAD_PWM3__GPIO_3_28 | | ||
| 155 | (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), | ||
| 156 | |||
| 157 | /* mmc1 */ | ||
| 158 | MX28_PAD_GPMI_D00__SSP1_D0 | | ||
| 159 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 160 | MX28_PAD_GPMI_D01__SSP1_D1 | | ||
| 161 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 162 | MX28_PAD_GPMI_D02__SSP1_D2 | | ||
| 163 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 164 | MX28_PAD_GPMI_D03__SSP1_D3 | | ||
| 165 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 166 | MX28_PAD_GPMI_D04__SSP1_D4 | | ||
| 167 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 168 | MX28_PAD_GPMI_D05__SSP1_D5 | | ||
| 169 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 170 | MX28_PAD_GPMI_D06__SSP1_D6 | | ||
| 171 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 172 | MX28_PAD_GPMI_D07__SSP1_D7 | | ||
| 173 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 174 | MX28_PAD_GPMI_RDY1__SSP1_CMD | | ||
| 175 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 176 | MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT | | ||
| 177 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), | ||
| 178 | MX28_PAD_GPMI_WRN__SSP1_SCK | | ||
| 179 | (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), | ||
| 180 | /* write protect */ | ||
| 181 | MX28_PAD_GPMI_RESETN__GPIO_0_28 | | ||
| 182 | (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), | ||
| 183 | /* slot power enable */ | ||
| 184 | MX28_PAD_PWM4__GPIO_3_29 | | ||
| 185 | (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), | ||
| 186 | |||
| 187 | /* led */ | ||
| 188 | MX28_PAD_AUART1_TX__GPIO_3_5 | MXS_PAD_CTRL, | ||
| 189 | |||
| 190 | /* I2C */ | ||
| 191 | MX28_PAD_I2C0_SCL__I2C0_SCL | | ||
| 192 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 193 | MX28_PAD_I2C0_SDA__I2C0_SDA | | ||
| 194 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 195 | |||
| 196 | /* saif0 & saif1 */ | ||
| 197 | MX28_PAD_SAIF0_MCLK__SAIF0_MCLK | | ||
| 198 | (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 199 | MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK | | ||
| 200 | (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 201 | MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK | | ||
| 202 | (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 203 | MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 | | ||
| 204 | (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 205 | MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 | | ||
| 206 | (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 207 | }; | ||
| 208 | |||
| 209 | /* led */ | ||
| 210 | static const struct gpio_led mx28evk_leds[] __initconst = { | ||
| 211 | { | ||
| 212 | .name = "GPIO-LED", | ||
| 213 | .default_trigger = "heartbeat", | ||
| 214 | .gpio = MX28EVK_GPIO_LED, | ||
| 215 | }, | ||
| 216 | }; | ||
| 217 | |||
| 218 | static const struct gpio_led_platform_data mx28evk_led_data __initconst = { | ||
| 219 | .leds = mx28evk_leds, | ||
| 220 | .num_leds = ARRAY_SIZE(mx28evk_leds), | ||
| 221 | }; | ||
| 222 | |||
| 223 | /* fec */ | ||
| 224 | static void __init mx28evk_fec_reset(void) | ||
| 225 | { | ||
| 226 | struct clk *clk; | ||
| 227 | |||
| 228 | /* Enable fec phy clock */ | ||
| 229 | clk = clk_get_sys("enet_out", NULL); | ||
| 230 | if (!IS_ERR(clk)) | ||
| 231 | clk_prepare_enable(clk); | ||
| 232 | |||
| 233 | gpio_set_value(MX28EVK_FEC_PHY_RESET, 0); | ||
| 234 | mdelay(1); | ||
| 235 | gpio_set_value(MX28EVK_FEC_PHY_RESET, 1); | ||
| 236 | } | ||
| 237 | |||
| 238 | static struct fec_platform_data mx28_fec_pdata[] __initdata = { | ||
| 239 | { | ||
| 240 | /* fec0 */ | ||
| 241 | .phy = PHY_INTERFACE_MODE_RMII, | ||
| 242 | }, { | ||
| 243 | /* fec1 */ | ||
| 244 | .phy = PHY_INTERFACE_MODE_RMII, | ||
| 245 | }, | ||
| 246 | }; | ||
| 247 | |||
| 248 | static int __init mx28evk_fec_get_mac(void) | ||
| 249 | { | ||
| 250 | int i; | ||
| 251 | u32 val; | ||
| 252 | const u32 *ocotp = mxs_get_ocotp(); | ||
| 253 | |||
| 254 | if (!ocotp) | ||
| 255 | return -ETIMEDOUT; | ||
| 256 | |||
| 257 | /* | ||
| 258 | * OCOTP only stores the last 4 octets for each mac address, | ||
| 259 | * so hard-code Freescale OUI (00:04:9f) here. | ||
| 260 | */ | ||
| 261 | for (i = 0; i < 2; i++) { | ||
| 262 | val = ocotp[i]; | ||
| 263 | mx28_fec_pdata[i].mac[0] = 0x00; | ||
| 264 | mx28_fec_pdata[i].mac[1] = 0x04; | ||
| 265 | mx28_fec_pdata[i].mac[2] = 0x9f; | ||
| 266 | mx28_fec_pdata[i].mac[3] = (val >> 16) & 0xff; | ||
| 267 | mx28_fec_pdata[i].mac[4] = (val >> 8) & 0xff; | ||
| 268 | mx28_fec_pdata[i].mac[5] = (val >> 0) & 0xff; | ||
| 269 | } | ||
| 270 | |||
| 271 | return 0; | ||
| 272 | } | ||
| 273 | |||
| 274 | /* | ||
| 275 | * MX28EVK_FLEXCAN_SWITCH is shared between both flexcan controllers | ||
| 276 | */ | ||
| 277 | static int flexcan0_en, flexcan1_en; | ||
| 278 | |||
| 279 | static void mx28evk_flexcan_switch(void) | ||
| 280 | { | ||
| 281 | if (flexcan0_en || flexcan1_en) | ||
| 282 | gpio_set_value(MX28EVK_FLEXCAN_SWITCH, 1); | ||
| 283 | else | ||
| 284 | gpio_set_value(MX28EVK_FLEXCAN_SWITCH, 0); | ||
| 285 | } | ||
| 286 | |||
| 287 | static void mx28evk_flexcan0_switch(int enable) | ||
| 288 | { | ||
| 289 | flexcan0_en = enable; | ||
| 290 | mx28evk_flexcan_switch(); | ||
| 291 | } | ||
| 292 | |||
| 293 | static void mx28evk_flexcan1_switch(int enable) | ||
| 294 | { | ||
| 295 | flexcan1_en = enable; | ||
| 296 | mx28evk_flexcan_switch(); | ||
| 297 | } | ||
| 298 | |||
| 299 | static const struct flexcan_platform_data | ||
| 300 | mx28evk_flexcan_pdata[] __initconst = { | ||
| 301 | { | ||
| 302 | .transceiver_switch = mx28evk_flexcan0_switch, | ||
| 303 | }, { | ||
| 304 | .transceiver_switch = mx28evk_flexcan1_switch, | ||
| 305 | } | ||
| 306 | }; | ||
| 307 | |||
| 308 | /* mxsfb (lcdif) */ | ||
| 309 | static struct fb_videomode mx28evk_video_modes[] = { | ||
| 310 | { | ||
| 311 | .name = "Seiko-43WVF1G", | ||
| 312 | .refresh = 60, | ||
| 313 | .xres = 800, | ||
| 314 | .yres = 480, | ||
| 315 | .pixclock = 29851, /* picosecond (33.5 MHz) */ | ||
| 316 | .left_margin = 89, | ||
| 317 | .right_margin = 164, | ||
| 318 | .upper_margin = 23, | ||
| 319 | .lower_margin = 10, | ||
| 320 | .hsync_len = 10, | ||
| 321 | .vsync_len = 10, | ||
| 322 | .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT | | ||
| 323 | FB_SYNC_DOTCLK_FAILING_ACT, | ||
| 324 | }, | ||
| 325 | }; | ||
| 326 | |||
| 327 | static const struct mxsfb_platform_data mx28evk_mxsfb_pdata __initconst = { | ||
| 328 | .mode_list = mx28evk_video_modes, | ||
| 329 | .mode_count = ARRAY_SIZE(mx28evk_video_modes), | ||
| 330 | .default_bpp = 32, | ||
| 331 | .ld_intf_width = STMLCDIF_24BIT, | ||
| 332 | }; | ||
| 333 | |||
| 334 | static struct mxs_mmc_platform_data mx28evk_mmc_pdata[] __initdata = { | ||
| 335 | { | ||
| 336 | /* mmc0 */ | ||
| 337 | .wp_gpio = MX28EVK_MMC0_WRITE_PROTECT, | ||
| 338 | .flags = SLOTF_8_BIT_CAPABLE, | ||
| 339 | }, { | ||
| 340 | /* mmc1 */ | ||
| 341 | .wp_gpio = MX28EVK_MMC1_WRITE_PROTECT, | ||
| 342 | .flags = SLOTF_8_BIT_CAPABLE, | ||
| 343 | }, | ||
| 344 | }; | ||
| 345 | |||
| 346 | static struct i2c_board_info mxs_i2c0_board_info[] __initdata = { | ||
| 347 | { | ||
| 348 | I2C_BOARD_INFO("sgtl5000", 0x0a), | ||
| 349 | }, | ||
| 350 | }; | ||
| 351 | |||
| 352 | #if defined(CONFIG_REGULATOR_FIXED_VOLTAGE) || defined(CONFIG_REGULATOR_FIXED_VOLTAGE_MODULE) | ||
| 353 | static struct regulator_consumer_supply mx28evk_audio_consumer_supplies[] = { | ||
| 354 | REGULATOR_SUPPLY("VDDA", "0-000a"), | ||
| 355 | REGULATOR_SUPPLY("VDDIO", "0-000a"), | ||
| 356 | }; | ||
| 357 | |||
| 358 | static struct regulator_init_data mx28evk_vdd_reg_init_data = { | ||
| 359 | .constraints = { | ||
| 360 | .name = "3V3", | ||
| 361 | .always_on = 1, | ||
| 362 | }, | ||
| 363 | .consumer_supplies = mx28evk_audio_consumer_supplies, | ||
| 364 | .num_consumer_supplies = ARRAY_SIZE(mx28evk_audio_consumer_supplies), | ||
| 365 | }; | ||
| 366 | |||
| 367 | static struct fixed_voltage_config mx28evk_vdd_pdata = { | ||
| 368 | .supply_name = "board-3V3", | ||
| 369 | .microvolts = 3300000, | ||
| 370 | .gpio = -EINVAL, | ||
| 371 | .enabled_at_boot = 1, | ||
| 372 | .init_data = &mx28evk_vdd_reg_init_data, | ||
| 373 | }; | ||
| 374 | static struct platform_device mx28evk_voltage_regulator = { | ||
| 375 | .name = "reg-fixed-voltage", | ||
| 376 | .id = -1, | ||
| 377 | .num_resources = 0, | ||
| 378 | .dev = { | ||
| 379 | .platform_data = &mx28evk_vdd_pdata, | ||
| 380 | }, | ||
| 381 | }; | ||
| 382 | static void __init mx28evk_add_regulators(void) | ||
| 383 | { | ||
| 384 | platform_device_register(&mx28evk_voltage_regulator); | ||
| 385 | } | ||
| 386 | #else | ||
| 387 | static void __init mx28evk_add_regulators(void) {} | ||
| 388 | #endif | ||
| 389 | |||
| 390 | static const struct gpio mx28evk_gpios[] __initconst = { | ||
| 391 | { MX28EVK_LCD_ENABLE, GPIOF_OUT_INIT_HIGH, "lcd-enable" }, | ||
| 392 | { MX28EVK_BL_ENABLE, GPIOF_OUT_INIT_HIGH, "bl-enable" }, | ||
| 393 | { MX28EVK_FLEXCAN_SWITCH, GPIOF_DIR_OUT, "flexcan-switch" }, | ||
| 394 | { MX28EVK_MMC0_SLOT_POWER, GPIOF_OUT_INIT_LOW, "mmc0-slot-power" }, | ||
| 395 | { MX28EVK_MMC1_SLOT_POWER, GPIOF_OUT_INIT_LOW, "mmc1-slot-power" }, | ||
| 396 | { MX28EVK_FEC_PHY_POWER, GPIOF_OUT_INIT_LOW, "fec-phy-power" }, | ||
| 397 | { MX28EVK_FEC_PHY_RESET, GPIOF_DIR_OUT, "fec-phy-reset" }, | ||
| 398 | }; | ||
| 399 | |||
| 400 | static const struct mxs_saif_platform_data | ||
| 401 | mx28evk_mxs_saif_pdata[] __initconst = { | ||
| 402 | /* working on EXTMSTR0 mode (saif0 master, saif1 slave) */ | ||
| 403 | { | ||
| 404 | .master_mode = 1, | ||
| 405 | .master_id = 0, | ||
| 406 | }, { | ||
| 407 | .master_mode = 0, | ||
| 408 | .master_id = 0, | ||
| 409 | }, | ||
| 410 | }; | ||
| 411 | |||
| 412 | static void __init mx28evk_init(void) | ||
| 413 | { | ||
| 414 | int ret; | ||
| 415 | |||
| 416 | mx28_soc_init(); | ||
| 417 | |||
| 418 | mxs_iomux_setup_multiple_pads(mx28evk_pads, ARRAY_SIZE(mx28evk_pads)); | ||
| 419 | |||
| 420 | mx28_add_duart(); | ||
| 421 | mx28_add_auart0(); | ||
| 422 | mx28_add_auart3(); | ||
| 423 | |||
| 424 | if (mx28evk_fec_get_mac()) | ||
| 425 | pr_warn("%s: failed on fec mac setup\n", __func__); | ||
| 426 | |||
| 427 | ret = gpio_request_array(mx28evk_gpios, ARRAY_SIZE(mx28evk_gpios)); | ||
| 428 | if (ret) | ||
| 429 | pr_err("One or more GPIOs failed to be requested: %d\n", ret); | ||
| 430 | |||
| 431 | mx28evk_fec_reset(); | ||
| 432 | mx28_add_fec(0, &mx28_fec_pdata[0]); | ||
| 433 | mx28_add_fec(1, &mx28_fec_pdata[1]); | ||
| 434 | |||
| 435 | mx28_add_flexcan(0, &mx28evk_flexcan_pdata[0]); | ||
| 436 | mx28_add_flexcan(1, &mx28evk_flexcan_pdata[1]); | ||
| 437 | |||
| 438 | mx28_add_mxsfb(&mx28evk_mxsfb_pdata); | ||
| 439 | |||
| 440 | mxs_saif_clkmux_select(MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0); | ||
| 441 | mx28_add_saif(0, &mx28evk_mxs_saif_pdata[0]); | ||
| 442 | mx28_add_saif(1, &mx28evk_mxs_saif_pdata[1]); | ||
| 443 | |||
| 444 | mx28_add_mxs_i2c(0); | ||
| 445 | i2c_register_board_info(0, mxs_i2c0_board_info, | ||
| 446 | ARRAY_SIZE(mxs_i2c0_board_info)); | ||
| 447 | |||
| 448 | mx28evk_add_regulators(); | ||
| 449 | |||
| 450 | mxs_add_platform_device("mxs-sgtl5000", 0, NULL, 0, | ||
| 451 | NULL, 0); | ||
| 452 | |||
| 453 | mx28_add_mxs_mmc(0, &mx28evk_mmc_pdata[0]); | ||
| 454 | mx28_add_mxs_mmc(1, &mx28evk_mmc_pdata[1]); | ||
| 455 | |||
| 456 | mx28_add_rtc_stmp3xxx(); | ||
| 457 | |||
| 458 | gpio_led_register_device(0, &mx28evk_led_data); | ||
| 459 | } | ||
| 460 | |||
| 461 | static void __init mx28evk_timer_init(void) | ||
| 462 | { | ||
| 463 | mx28_clocks_init(); | ||
| 464 | } | ||
| 465 | |||
| 466 | static struct sys_timer mx28evk_timer = { | ||
| 467 | .init = mx28evk_timer_init, | ||
| 468 | }; | ||
| 469 | |||
| 470 | MACHINE_START(MX28EVK, "Freescale MX28 EVK") | ||
| 471 | /* Maintainer: Freescale Semiconductor, Inc. */ | ||
| 472 | .map_io = mx28_map_io, | ||
| 473 | .init_irq = mx28_init_irq, | ||
| 474 | .timer = &mx28evk_timer, | ||
| 475 | .init_machine = mx28evk_init, | ||
| 476 | .restart = mxs_restart, | ||
| 477 | MACHINE_END | ||
diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c index 8dabfe81d07c..433af893ad8a 100644 --- a/arch/arm/mach-mxs/mach-mxs.c +++ b/arch/arm/mach-mxs/mach-mxs.c | |||
| @@ -12,8 +12,10 @@ | |||
| 12 | 12 | ||
| 13 | #include <linux/clk.h> | 13 | #include <linux/clk.h> |
| 14 | #include <linux/clkdev.h> | 14 | #include <linux/clkdev.h> |
| 15 | #include <linux/can/platform/flexcan.h> | ||
| 16 | #include <linux/delay.h> | ||
| 15 | #include <linux/err.h> | 17 | #include <linux/err.h> |
| 16 | #include <linux/init.h> | 18 | #include <linux/gpio.h> |
| 17 | #include <linux/init.h> | 19 | #include <linux/init.h> |
| 18 | #include <linux/irqdomain.h> | 20 | #include <linux/irqdomain.h> |
| 19 | #include <linux/micrel_phy.h> | 21 | #include <linux/micrel_phy.h> |
| @@ -21,9 +23,12 @@ | |||
| 21 | #include <linux/of_irq.h> | 23 | #include <linux/of_irq.h> |
| 22 | #include <linux/of_platform.h> | 24 | #include <linux/of_platform.h> |
| 23 | #include <linux/phy.h> | 25 | #include <linux/phy.h> |
| 26 | #include <linux/pinctrl/consumer.h> | ||
| 24 | #include <asm/mach/arch.h> | 27 | #include <asm/mach/arch.h> |
| 25 | #include <asm/mach/time.h> | 28 | #include <asm/mach/time.h> |
| 26 | #include <mach/common.h> | 29 | #include <mach/common.h> |
| 30 | #include <mach/digctl.h> | ||
| 31 | #include <mach/mxs.h> | ||
| 27 | 32 | ||
| 28 | static struct fb_videomode mx23evk_video_modes[] = { | 33 | static struct fb_videomode mx23evk_video_modes[] = { |
| 29 | { | 34 | { |
| @@ -99,9 +104,40 @@ static struct fb_videomode apx4devkit_video_modes[] = { | |||
| 99 | 104 | ||
| 100 | static struct mxsfb_platform_data mxsfb_pdata __initdata; | 105 | static struct mxsfb_platform_data mxsfb_pdata __initdata; |
| 101 | 106 | ||
| 107 | /* | ||
| 108 | * MX28EVK_FLEXCAN_SWITCH is shared between both flexcan controllers | ||
| 109 | */ | ||
| 110 | #define MX28EVK_FLEXCAN_SWITCH MXS_GPIO_NR(2, 13) | ||
| 111 | |||
| 112 | static int flexcan0_en, flexcan1_en; | ||
| 113 | |||
| 114 | static void mx28evk_flexcan_switch(void) | ||
| 115 | { | ||
| 116 | if (flexcan0_en || flexcan1_en) | ||
| 117 | gpio_set_value(MX28EVK_FLEXCAN_SWITCH, 1); | ||
| 118 | else | ||
| 119 | gpio_set_value(MX28EVK_FLEXCAN_SWITCH, 0); | ||
| 120 | } | ||
| 121 | |||
| 122 | static void mx28evk_flexcan0_switch(int enable) | ||
| 123 | { | ||
| 124 | flexcan0_en = enable; | ||
| 125 | mx28evk_flexcan_switch(); | ||
| 126 | } | ||
| 127 | |||
| 128 | static void mx28evk_flexcan1_switch(int enable) | ||
| 129 | { | ||
| 130 | flexcan1_en = enable; | ||
| 131 | mx28evk_flexcan_switch(); | ||
| 132 | } | ||
| 133 | |||
| 134 | static struct flexcan_platform_data flexcan_pdata[2]; | ||
| 135 | |||
| 102 | static struct of_dev_auxdata mxs_auxdata_lookup[] __initdata = { | 136 | static struct of_dev_auxdata mxs_auxdata_lookup[] __initdata = { |
| 103 | OF_DEV_AUXDATA("fsl,imx23-lcdif", 0x80030000, NULL, &mxsfb_pdata), | 137 | OF_DEV_AUXDATA("fsl,imx23-lcdif", 0x80030000, NULL, &mxsfb_pdata), |
| 104 | OF_DEV_AUXDATA("fsl,imx28-lcdif", 0x80030000, NULL, &mxsfb_pdata), | 138 | OF_DEV_AUXDATA("fsl,imx28-lcdif", 0x80030000, NULL, &mxsfb_pdata), |
| 139 | OF_DEV_AUXDATA("fsl,imx28-flexcan", 0x80032000, NULL, &flexcan_pdata[0]), | ||
| 140 | OF_DEV_AUXDATA("fsl,imx28-flexcan", 0x80034000, NULL, &flexcan_pdata[1]), | ||
| 105 | { /* sentinel */ } | 141 | { /* sentinel */ } |
| 106 | }; | 142 | }; |
| 107 | 143 | ||
| @@ -237,13 +273,21 @@ static void __init imx28_evk_init(void) | |||
| 237 | mxsfb_pdata.mode_count = ARRAY_SIZE(mx28evk_video_modes); | 273 | mxsfb_pdata.mode_count = ARRAY_SIZE(mx28evk_video_modes); |
| 238 | mxsfb_pdata.default_bpp = 32; | 274 | mxsfb_pdata.default_bpp = 32; |
| 239 | mxsfb_pdata.ld_intf_width = STMLCDIF_24BIT; | 275 | mxsfb_pdata.ld_intf_width = STMLCDIF_24BIT; |
| 276 | |||
| 277 | mxs_saif_clkmux_select(MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0); | ||
| 240 | } | 278 | } |
| 241 | 279 | ||
| 242 | static void __init m28evk_init(void) | 280 | static void __init imx28_evk_post_init(void) |
| 243 | { | 281 | { |
| 244 | enable_clk_enet_out(); | 282 | if (!gpio_request_one(MX28EVK_FLEXCAN_SWITCH, GPIOF_DIR_OUT, |
| 245 | update_fec_mac_prop(OUI_DENX); | 283 | "flexcan-switch")) { |
| 284 | flexcan_pdata[0].transceiver_switch = mx28evk_flexcan0_switch; | ||
| 285 | flexcan_pdata[1].transceiver_switch = mx28evk_flexcan1_switch; | ||
| 286 | } | ||
| 287 | } | ||
| 246 | 288 | ||
| 289 | static void __init m28evk_init(void) | ||
| 290 | { | ||
| 247 | mxsfb_pdata.mode_list = m28evk_video_modes; | 291 | mxsfb_pdata.mode_list = m28evk_video_modes; |
| 248 | mxsfb_pdata.mode_count = ARRAY_SIZE(m28evk_video_modes); | 292 | mxsfb_pdata.mode_count = ARRAY_SIZE(m28evk_video_modes); |
| 249 | mxsfb_pdata.default_bpp = 16; | 293 | mxsfb_pdata.default_bpp = 16; |
| @@ -270,6 +314,80 @@ static void __init apx4devkit_init(void) | |||
| 270 | mxsfb_pdata.ld_intf_width = STMLCDIF_24BIT; | 314 | mxsfb_pdata.ld_intf_width = STMLCDIF_24BIT; |
| 271 | } | 315 | } |
| 272 | 316 | ||
| 317 | #define ENET0_MDC__GPIO_4_0 MXS_GPIO_NR(4, 0) | ||
| 318 | #define ENET0_MDIO__GPIO_4_1 MXS_GPIO_NR(4, 1) | ||
| 319 | #define ENET0_RX_EN__GPIO_4_2 MXS_GPIO_NR(4, 2) | ||
| 320 | #define ENET0_RXD0__GPIO_4_3 MXS_GPIO_NR(4, 3) | ||
| 321 | #define ENET0_RXD1__GPIO_4_4 MXS_GPIO_NR(4, 4) | ||
| 322 | #define ENET0_TX_EN__GPIO_4_6 MXS_GPIO_NR(4, 6) | ||
| 323 | #define ENET0_TXD0__GPIO_4_7 MXS_GPIO_NR(4, 7) | ||
| 324 | #define ENET0_TXD1__GPIO_4_8 MXS_GPIO_NR(4, 8) | ||
| 325 | #define ENET_CLK__GPIO_4_16 MXS_GPIO_NR(4, 16) | ||
| 326 | |||
| 327 | #define TX28_FEC_PHY_POWER MXS_GPIO_NR(3, 29) | ||
| 328 | #define TX28_FEC_PHY_RESET MXS_GPIO_NR(4, 13) | ||
| 329 | #define TX28_FEC_nINT MXS_GPIO_NR(4, 5) | ||
| 330 | |||
| 331 | static const struct gpio tx28_gpios[] __initconst = { | ||
| 332 | { ENET0_MDC__GPIO_4_0, GPIOF_OUT_INIT_LOW, "GPIO_4_0" }, | ||
| 333 | { ENET0_MDIO__GPIO_4_1, GPIOF_OUT_INIT_LOW, "GPIO_4_1" }, | ||
| 334 | { ENET0_RX_EN__GPIO_4_2, GPIOF_OUT_INIT_LOW, "GPIO_4_2" }, | ||
| 335 | { ENET0_RXD0__GPIO_4_3, GPIOF_OUT_INIT_LOW, "GPIO_4_3" }, | ||
| 336 | { ENET0_RXD1__GPIO_4_4, GPIOF_OUT_INIT_LOW, "GPIO_4_4" }, | ||
| 337 | { ENET0_TX_EN__GPIO_4_6, GPIOF_OUT_INIT_LOW, "GPIO_4_6" }, | ||
| 338 | { ENET0_TXD0__GPIO_4_7, GPIOF_OUT_INIT_LOW, "GPIO_4_7" }, | ||
| 339 | { ENET0_TXD1__GPIO_4_8, GPIOF_OUT_INIT_LOW, "GPIO_4_8" }, | ||
| 340 | { ENET_CLK__GPIO_4_16, GPIOF_OUT_INIT_LOW, "GPIO_4_16" }, | ||
| 341 | { TX28_FEC_PHY_POWER, GPIOF_OUT_INIT_LOW, "fec-phy-power" }, | ||
| 342 | { TX28_FEC_PHY_RESET, GPIOF_OUT_INIT_LOW, "fec-phy-reset" }, | ||
| 343 | { TX28_FEC_nINT, GPIOF_DIR_IN, "fec-int" }, | ||
| 344 | }; | ||
| 345 | |||
| 346 | static void __init tx28_post_init(void) | ||
| 347 | { | ||
| 348 | struct device_node *np; | ||
| 349 | struct platform_device *pdev; | ||
| 350 | struct pinctrl *pctl; | ||
| 351 | int ret; | ||
| 352 | |||
| 353 | enable_clk_enet_out(); | ||
| 354 | |||
| 355 | np = of_find_compatible_node(NULL, NULL, "fsl,imx28-fec"); | ||
| 356 | pdev = of_find_device_by_node(np); | ||
| 357 | if (!pdev) { | ||
| 358 | pr_err("%s: failed to find fec device\n", __func__); | ||
| 359 | return; | ||
| 360 | } | ||
| 361 | |||
| 362 | pctl = pinctrl_get_select(&pdev->dev, "gpio_mode"); | ||
| 363 | if (IS_ERR(pctl)) { | ||
| 364 | pr_err("%s: failed to get pinctrl state\n", __func__); | ||
| 365 | return; | ||
| 366 | } | ||
| 367 | |||
| 368 | ret = gpio_request_array(tx28_gpios, ARRAY_SIZE(tx28_gpios)); | ||
| 369 | if (ret) { | ||
| 370 | pr_err("%s: failed to request gpios: %d\n", __func__, ret); | ||
| 371 | return; | ||
| 372 | } | ||
| 373 | |||
| 374 | /* Power up fec phy */ | ||
| 375 | gpio_set_value(TX28_FEC_PHY_POWER, 1); | ||
| 376 | msleep(26); /* 25ms according to data sheet */ | ||
| 377 | |||
| 378 | /* Mode strap pins */ | ||
| 379 | gpio_set_value(ENET0_RX_EN__GPIO_4_2, 1); | ||
| 380 | gpio_set_value(ENET0_RXD0__GPIO_4_3, 1); | ||
| 381 | gpio_set_value(ENET0_RXD1__GPIO_4_4, 1); | ||
| 382 | |||
| 383 | udelay(100); /* minimum assertion time for nRST */ | ||
| 384 | |||
| 385 | /* Deasserting FEC PHY RESET */ | ||
| 386 | gpio_set_value(TX28_FEC_PHY_RESET, 1); | ||
| 387 | |||
| 388 | pinctrl_put(pctl); | ||
| 389 | } | ||
| 390 | |||
| 273 | static void __init mxs_machine_init(void) | 391 | static void __init mxs_machine_init(void) |
| 274 | { | 392 | { |
| 275 | if (of_machine_is_compatible("fsl,imx28-evk")) | 393 | if (of_machine_is_compatible("fsl,imx28-evk")) |
| @@ -283,22 +401,20 @@ static void __init mxs_machine_init(void) | |||
| 283 | 401 | ||
| 284 | of_platform_populate(NULL, of_default_bus_match_table, | 402 | of_platform_populate(NULL, of_default_bus_match_table, |
| 285 | mxs_auxdata_lookup, NULL); | 403 | mxs_auxdata_lookup, NULL); |
| 404 | |||
| 405 | if (of_machine_is_compatible("karo,tx28")) | ||
| 406 | tx28_post_init(); | ||
| 407 | |||
| 408 | if (of_machine_is_compatible("fsl,imx28-evk")) | ||
| 409 | imx28_evk_post_init(); | ||
| 286 | } | 410 | } |
| 287 | 411 | ||
| 288 | static const char *imx23_dt_compat[] __initdata = { | 412 | static const char *imx23_dt_compat[] __initdata = { |
| 289 | "fsl,imx23-evk", | ||
| 290 | "fsl,stmp378x_devb" | ||
| 291 | "olimex,imx23-olinuxino", | ||
| 292 | "fsl,imx23", | 413 | "fsl,imx23", |
| 293 | NULL, | 414 | NULL, |
| 294 | }; | 415 | }; |
| 295 | 416 | ||
| 296 | static const char *imx28_dt_compat[] __initdata = { | 417 | static const char *imx28_dt_compat[] __initdata = { |
| 297 | "bluegiga,apx4devkit", | ||
| 298 | "crystalfontz,cfa10036", | ||
| 299 | "denx,m28evk", | ||
| 300 | "fsl,imx28-evk", | ||
| 301 | "karo,tx28", | ||
| 302 | "fsl,imx28", | 418 | "fsl,imx28", |
| 303 | NULL, | 419 | NULL, |
| 304 | }; | 420 | }; |
diff --git a/arch/arm/mach-mxs/mach-stmp378x_devb.c b/arch/arm/mach-mxs/mach-stmp378x_devb.c deleted file mode 100644 index 6548965e4a76..000000000000 --- a/arch/arm/mach-mxs/mach-stmp378x_devb.c +++ /dev/null | |||
| @@ -1,123 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * board setup for STMP378x-Development-Board | ||
| 3 | * | ||
| 4 | * based on mx23evk board setup and information gained form the original | ||
| 5 | * plat-stmp based board setup, now converted to mach-mxs. | ||
| 6 | * | ||
| 7 | * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 8 | * Copyright (C) 2011 Wolfram Sang, Pengutronix e.K. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License as published by | ||
| 12 | * the Free Software Foundation; version 2 of the License. | ||
| 13 | * | ||
| 14 | * This program is distributed in the hope that it will be useful, | ||
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 17 | * GNU General Public License for more details. | ||
| 18 | */ | ||
| 19 | |||
| 20 | #include <linux/platform_device.h> | ||
| 21 | #include <linux/gpio.h> | ||
| 22 | #include <linux/spi/spi.h> | ||
| 23 | |||
| 24 | #include <asm/mach-types.h> | ||
| 25 | #include <asm/mach/arch.h> | ||
| 26 | #include <asm/mach/time.h> | ||
| 27 | |||
| 28 | #include <mach/common.h> | ||
| 29 | #include <mach/iomux-mx23.h> | ||
| 30 | |||
| 31 | #include "devices-mx23.h" | ||
| 32 | |||
| 33 | #define STMP378X_DEVB_MMC0_WRITE_PROTECT MXS_GPIO_NR(1, 30) | ||
| 34 | #define STMP378X_DEVB_MMC0_SLOT_POWER MXS_GPIO_NR(1, 29) | ||
| 35 | |||
| 36 | #define STMP378X_DEVB_PAD_AUART (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL) | ||
| 37 | |||
| 38 | static const iomux_cfg_t stmp378x_dvb_pads[] __initconst = { | ||
| 39 | /* duart (extended setup missing in old boardcode, too */ | ||
| 40 | MX23_PAD_PWM0__DUART_RX, | ||
| 41 | MX23_PAD_PWM1__DUART_TX, | ||
| 42 | |||
| 43 | /* auart */ | ||
| 44 | MX23_PAD_AUART1_RX__AUART1_RX | STMP378X_DEVB_PAD_AUART, | ||
| 45 | MX23_PAD_AUART1_TX__AUART1_TX | STMP378X_DEVB_PAD_AUART, | ||
| 46 | MX23_PAD_AUART1_CTS__AUART1_CTS | STMP378X_DEVB_PAD_AUART, | ||
| 47 | MX23_PAD_AUART1_RTS__AUART1_RTS | STMP378X_DEVB_PAD_AUART, | ||
| 48 | |||
| 49 | /* mmc */ | ||
| 50 | MX23_PAD_SSP1_DATA0__SSP1_DATA0 | | ||
| 51 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 52 | MX23_PAD_SSP1_DATA1__SSP1_DATA1 | | ||
| 53 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 54 | MX23_PAD_SSP1_DATA2__SSP1_DATA2 | | ||
| 55 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 56 | MX23_PAD_SSP1_DATA3__SSP1_DATA3 | | ||
| 57 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 58 | MX23_PAD_SSP1_CMD__SSP1_CMD | | ||
| 59 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 60 | MX23_PAD_SSP1_DETECT__SSP1_DETECT | | ||
| 61 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), | ||
| 62 | MX23_PAD_SSP1_SCK__SSP1_SCK | | ||
| 63 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), | ||
| 64 | MX23_PAD_PWM4__GPIO_1_30 | MXS_PAD_CTRL, /* write protect */ | ||
| 65 | MX23_PAD_PWM3__GPIO_1_29 | MXS_PAD_CTRL, /* power enable */ | ||
| 66 | }; | ||
| 67 | |||
| 68 | static struct mxs_mmc_platform_data stmp378x_dvb_mmc_pdata __initdata = { | ||
| 69 | .wp_gpio = STMP378X_DEVB_MMC0_WRITE_PROTECT, | ||
| 70 | }; | ||
| 71 | |||
| 72 | static struct spi_board_info spi_board_info[] __initdata = { | ||
| 73 | #if defined(CONFIG_ENC28J60) || defined(CONFIG_ENC28J60_MODULE) | ||
| 74 | { | ||
| 75 | .modalias = "enc28j60", | ||
| 76 | .max_speed_hz = 6 * 1000 * 1000, | ||
| 77 | .bus_num = 1, | ||
| 78 | .chip_select = 0, | ||
| 79 | .platform_data = NULL, | ||
| 80 | }, | ||
| 81 | #endif | ||
| 82 | }; | ||
| 83 | |||
| 84 | static void __init stmp378x_dvb_init(void) | ||
| 85 | { | ||
| 86 | int ret; | ||
| 87 | |||
| 88 | mx23_soc_init(); | ||
| 89 | |||
| 90 | mxs_iomux_setup_multiple_pads(stmp378x_dvb_pads, | ||
| 91 | ARRAY_SIZE(stmp378x_dvb_pads)); | ||
| 92 | |||
| 93 | mx23_add_duart(); | ||
| 94 | mx23_add_auart0(); | ||
| 95 | mx23_add_rtc_stmp3xxx(); | ||
| 96 | |||
| 97 | /* power on mmc slot */ | ||
| 98 | ret = gpio_request_one(STMP378X_DEVB_MMC0_SLOT_POWER, | ||
| 99 | GPIOF_OUT_INIT_LOW, "mmc0-slot-power"); | ||
| 100 | if (ret) | ||
| 101 | pr_warn("could not power mmc (%d)\n", ret); | ||
| 102 | |||
| 103 | mx23_add_mxs_mmc(0, &stmp378x_dvb_mmc_pdata); | ||
| 104 | |||
| 105 | spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info)); | ||
| 106 | } | ||
| 107 | |||
| 108 | static void __init stmp378x_dvb_timer_init(void) | ||
| 109 | { | ||
| 110 | mx23_clocks_init(); | ||
| 111 | } | ||
| 112 | |||
| 113 | static struct sys_timer stmp378x_dvb_timer = { | ||
| 114 | .init = stmp378x_dvb_timer_init, | ||
| 115 | }; | ||
| 116 | |||
| 117 | MACHINE_START(STMP378X, "STMP378X") | ||
| 118 | .map_io = mx23_map_io, | ||
| 119 | .init_irq = mx23_init_irq, | ||
| 120 | .timer = &stmp378x_dvb_timer, | ||
| 121 | .init_machine = stmp378x_dvb_init, | ||
| 122 | .restart = mxs_restart, | ||
| 123 | MACHINE_END | ||
diff --git a/arch/arm/mach-mxs/mach-tx28.c b/arch/arm/mach-mxs/mach-tx28.c deleted file mode 100644 index 8837029de1a4..000000000000 --- a/arch/arm/mach-mxs/mach-tx28.c +++ /dev/null | |||
| @@ -1,184 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2010 <LW@KARO-electronics.de> | ||
| 3 | * | ||
| 4 | * based on: mach-mx28_evk.c | ||
| 5 | * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or | ||
| 8 | * modify it under the terms of the GNU General Public License | ||
| 9 | * version 2 as published by the Free Software Foundation | ||
| 10 | */ | ||
| 11 | #include <linux/kernel.h> | ||
| 12 | #include <linux/gpio.h> | ||
| 13 | #include <linux/leds.h> | ||
| 14 | #include <linux/platform_device.h> | ||
| 15 | #include <linux/spi/spi.h> | ||
| 16 | #include <linux/spi/spi_gpio.h> | ||
| 17 | #include <linux/i2c.h> | ||
| 18 | |||
| 19 | #include <asm/mach/arch.h> | ||
| 20 | #include <asm/mach/time.h> | ||
| 21 | |||
| 22 | #include <mach/common.h> | ||
| 23 | #include <mach/iomux-mx28.h> | ||
| 24 | |||
| 25 | #include "devices-mx28.h" | ||
| 26 | #include "module-tx28.h" | ||
| 27 | |||
| 28 | #define TX28_STK5_GPIO_LED MXS_GPIO_NR(4, 10) | ||
| 29 | |||
| 30 | static const iomux_cfg_t tx28_stk5v3_pads[] __initconst = { | ||
| 31 | /* LED */ | ||
| 32 | MX28_PAD_ENET0_RXD3__GPIO_4_10 | | ||
| 33 | MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL, | ||
| 34 | |||
| 35 | /* framebuffer */ | ||
| 36 | #define LCD_MODE (MXS_PAD_3V3 | MXS_PAD_4MA) | ||
| 37 | MX28_PAD_LCD_D00__LCD_D0 | LCD_MODE, | ||
| 38 | MX28_PAD_LCD_D01__LCD_D1 | LCD_MODE, | ||
| 39 | MX28_PAD_LCD_D02__LCD_D2 | LCD_MODE, | ||
| 40 | MX28_PAD_LCD_D03__LCD_D3 | LCD_MODE, | ||
| 41 | MX28_PAD_LCD_D04__LCD_D4 | LCD_MODE, | ||
| 42 | MX28_PAD_LCD_D05__LCD_D5 | LCD_MODE, | ||
| 43 | MX28_PAD_LCD_D06__LCD_D6 | LCD_MODE, | ||
| 44 | MX28_PAD_LCD_D07__LCD_D7 | LCD_MODE, | ||
| 45 | MX28_PAD_LCD_D08__LCD_D8 | LCD_MODE, | ||
| 46 | MX28_PAD_LCD_D09__LCD_D9 | LCD_MODE, | ||
| 47 | MX28_PAD_LCD_D10__LCD_D10 | LCD_MODE, | ||
| 48 | MX28_PAD_LCD_D11__LCD_D11 | LCD_MODE, | ||
| 49 | MX28_PAD_LCD_D12__LCD_D12 | LCD_MODE, | ||
| 50 | MX28_PAD_LCD_D13__LCD_D13 | LCD_MODE, | ||
| 51 | MX28_PAD_LCD_D14__LCD_D14 | LCD_MODE, | ||
| 52 | MX28_PAD_LCD_D15__LCD_D15 | LCD_MODE, | ||
| 53 | MX28_PAD_LCD_D16__LCD_D16 | LCD_MODE, | ||
| 54 | MX28_PAD_LCD_D17__LCD_D17 | LCD_MODE, | ||
| 55 | MX28_PAD_LCD_D18__LCD_D18 | LCD_MODE, | ||
| 56 | MX28_PAD_LCD_D19__LCD_D19 | LCD_MODE, | ||
| 57 | MX28_PAD_LCD_D20__LCD_D20 | LCD_MODE, | ||
| 58 | MX28_PAD_LCD_D21__LCD_D21 | LCD_MODE, | ||
| 59 | MX28_PAD_LCD_D22__LCD_D22 | LCD_MODE, | ||
| 60 | MX28_PAD_LCD_D23__LCD_D23 | LCD_MODE, | ||
| 61 | MX28_PAD_LCD_RD_E__LCD_VSYNC | LCD_MODE, | ||
| 62 | MX28_PAD_LCD_WR_RWN__LCD_HSYNC | LCD_MODE, | ||
| 63 | MX28_PAD_LCD_RS__LCD_DOTCLK | LCD_MODE, | ||
| 64 | MX28_PAD_LCD_CS__LCD_CS | LCD_MODE, | ||
| 65 | MX28_PAD_LCD_VSYNC__LCD_VSYNC | LCD_MODE, | ||
| 66 | MX28_PAD_LCD_HSYNC__LCD_HSYNC | LCD_MODE, | ||
| 67 | MX28_PAD_LCD_DOTCLK__LCD_DOTCLK | LCD_MODE, | ||
| 68 | MX28_PAD_LCD_ENABLE__GPIO_1_31 | LCD_MODE, | ||
| 69 | MX28_PAD_LCD_RESET__GPIO_3_30 | LCD_MODE, | ||
| 70 | MX28_PAD_PWM0__PWM_0 | LCD_MODE, | ||
| 71 | |||
| 72 | /* UART1 */ | ||
| 73 | MX28_PAD_AUART0_CTS__DUART_RX, | ||
| 74 | MX28_PAD_AUART0_RTS__DUART_TX, | ||
| 75 | MX28_PAD_AUART0_TX__DUART_RTS, | ||
| 76 | MX28_PAD_AUART0_RX__DUART_CTS, | ||
| 77 | |||
| 78 | /* UART2 */ | ||
| 79 | MX28_PAD_AUART1_RX__AUART1_RX, | ||
| 80 | MX28_PAD_AUART1_TX__AUART1_TX, | ||
| 81 | MX28_PAD_AUART1_RTS__AUART1_RTS, | ||
| 82 | MX28_PAD_AUART1_CTS__AUART1_CTS, | ||
| 83 | |||
| 84 | /* CAN */ | ||
| 85 | MX28_PAD_GPMI_RDY2__CAN0_TX, | ||
| 86 | MX28_PAD_GPMI_RDY3__CAN0_RX, | ||
| 87 | |||
| 88 | /* I2C */ | ||
| 89 | MX28_PAD_I2C0_SCL__I2C0_SCL, | ||
| 90 | MX28_PAD_I2C0_SDA__I2C0_SDA, | ||
| 91 | |||
| 92 | /* TSC2007 */ | ||
| 93 | MX28_PAD_SAIF0_MCLK__GPIO_3_20 | MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP, | ||
| 94 | |||
| 95 | /* MMC0 */ | ||
| 96 | MX28_PAD_SSP0_DATA0__SSP0_D0 | | ||
| 97 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 98 | MX28_PAD_SSP0_DATA1__SSP0_D1 | | ||
| 99 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 100 | MX28_PAD_SSP0_DATA2__SSP0_D2 | | ||
| 101 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 102 | MX28_PAD_SSP0_DATA3__SSP0_D3 | | ||
| 103 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 104 | MX28_PAD_SSP0_CMD__SSP0_CMD | | ||
| 105 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 106 | MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT | | ||
| 107 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), | ||
| 108 | MX28_PAD_SSP0_SCK__SSP0_SCK | | ||
| 109 | (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), | ||
| 110 | }; | ||
| 111 | |||
| 112 | static const struct gpio_led tx28_stk5v3_leds[] __initconst = { | ||
| 113 | { | ||
| 114 | .name = "GPIO-LED", | ||
| 115 | .default_trigger = "heartbeat", | ||
| 116 | .gpio = TX28_STK5_GPIO_LED, | ||
| 117 | }, | ||
| 118 | }; | ||
| 119 | |||
| 120 | static const struct gpio_led_platform_data tx28_stk5v3_led_data __initconst = { | ||
| 121 | .leds = tx28_stk5v3_leds, | ||
| 122 | .num_leds = ARRAY_SIZE(tx28_stk5v3_leds), | ||
| 123 | }; | ||
| 124 | |||
| 125 | static struct spi_board_info tx28_spi_board_info[] = { | ||
| 126 | { | ||
| 127 | .modalias = "spidev", | ||
| 128 | .max_speed_hz = 20000000, | ||
| 129 | .bus_num = 0, | ||
| 130 | .chip_select = 1, | ||
| 131 | .controller_data = (void *)SPI_GPIO_NO_CHIPSELECT, | ||
| 132 | .mode = SPI_MODE_0, | ||
| 133 | }, | ||
| 134 | }; | ||
| 135 | |||
| 136 | static struct i2c_board_info tx28_stk5v3_i2c_boardinfo[] __initdata = { | ||
| 137 | { | ||
| 138 | I2C_BOARD_INFO("ds1339", 0x68), | ||
| 139 | }, | ||
| 140 | }; | ||
| 141 | |||
| 142 | static struct mxs_mmc_platform_data tx28_mmc0_pdata __initdata = { | ||
| 143 | .wp_gpio = -EINVAL, | ||
| 144 | .flags = SLOTF_4_BIT_CAPABLE, | ||
| 145 | }; | ||
| 146 | |||
| 147 | static void __init tx28_stk5v3_init(void) | ||
| 148 | { | ||
| 149 | mx28_soc_init(); | ||
| 150 | |||
| 151 | mxs_iomux_setup_multiple_pads(tx28_stk5v3_pads, | ||
| 152 | ARRAY_SIZE(tx28_stk5v3_pads)); | ||
| 153 | |||
| 154 | mx28_add_duart(); /* UART1 */ | ||
| 155 | mx28_add_auart(1); /* UART2 */ | ||
| 156 | |||
| 157 | tx28_add_fec0(); | ||
| 158 | /* spi via ssp will be added when available */ | ||
| 159 | spi_register_board_info(tx28_spi_board_info, | ||
| 160 | ARRAY_SIZE(tx28_spi_board_info)); | ||
| 161 | gpio_led_register_device(0, &tx28_stk5v3_led_data); | ||
| 162 | mx28_add_mxs_i2c(0); | ||
| 163 | i2c_register_board_info(0, tx28_stk5v3_i2c_boardinfo, | ||
| 164 | ARRAY_SIZE(tx28_stk5v3_i2c_boardinfo)); | ||
| 165 | mx28_add_mxs_mmc(0, &tx28_mmc0_pdata); | ||
| 166 | mx28_add_rtc_stmp3xxx(); | ||
| 167 | } | ||
| 168 | |||
| 169 | static void __init tx28_timer_init(void) | ||
| 170 | { | ||
| 171 | mx28_clocks_init(); | ||
| 172 | } | ||
| 173 | |||
| 174 | static struct sys_timer tx28_timer = { | ||
| 175 | .init = tx28_timer_init, | ||
| 176 | }; | ||
| 177 | |||
| 178 | MACHINE_START(TX28, "Ka-Ro electronics TX28 module") | ||
| 179 | .map_io = mx28_map_io, | ||
| 180 | .init_irq = mx28_init_irq, | ||
| 181 | .timer = &tx28_timer, | ||
| 182 | .init_machine = tx28_stk5v3_init, | ||
| 183 | .restart = mxs_restart, | ||
| 184 | MACHINE_END | ||
diff --git a/arch/arm/mach-mxs/mm.c b/arch/arm/mach-mxs/mm.c index dccb67a9e7c4..a4294aa9f301 100644 --- a/arch/arm/mach-mxs/mm.c +++ b/arch/arm/mach-mxs/mm.c | |||
| @@ -13,14 +13,11 @@ | |||
| 13 | 13 | ||
| 14 | #include <linux/mm.h> | 14 | #include <linux/mm.h> |
| 15 | #include <linux/init.h> | 15 | #include <linux/init.h> |
| 16 | #include <linux/pinctrl/machine.h> | ||
| 17 | 16 | ||
| 18 | #include <asm/mach/map.h> | 17 | #include <asm/mach/map.h> |
| 19 | 18 | ||
| 20 | #include <mach/mx23.h> | 19 | #include <mach/mx23.h> |
| 21 | #include <mach/mx28.h> | 20 | #include <mach/mx28.h> |
| 22 | #include <mach/common.h> | ||
| 23 | #include <mach/iomux.h> | ||
| 24 | 21 | ||
| 25 | /* | 22 | /* |
| 26 | * Define the MX23 memory map. | 23 | * Define the MX23 memory map. |
| @@ -48,43 +45,7 @@ void __init mx23_map_io(void) | |||
| 48 | iotable_init(mx23_io_desc, ARRAY_SIZE(mx23_io_desc)); | 45 | iotable_init(mx23_io_desc, ARRAY_SIZE(mx23_io_desc)); |
| 49 | } | 46 | } |
| 50 | 47 | ||
| 51 | void __init mx23_init_irq(void) | ||
| 52 | { | ||
| 53 | icoll_init_irq(); | ||
| 54 | } | ||
| 55 | |||
| 56 | void __init mx28_map_io(void) | 48 | void __init mx28_map_io(void) |
| 57 | { | 49 | { |
| 58 | iotable_init(mx28_io_desc, ARRAY_SIZE(mx28_io_desc)); | 50 | iotable_init(mx28_io_desc, ARRAY_SIZE(mx28_io_desc)); |
| 59 | } | 51 | } |
| 60 | |||
| 61 | void __init mx28_init_irq(void) | ||
| 62 | { | ||
| 63 | icoll_init_irq(); | ||
| 64 | } | ||
| 65 | |||
| 66 | void __init mx23_soc_init(void) | ||
| 67 | { | ||
| 68 | pinctrl_provide_dummies(); | ||
| 69 | |||
| 70 | mxs_add_dma("imx23-dma-apbh", MX23_APBH_DMA_BASE_ADDR); | ||
| 71 | mxs_add_dma("imx23-dma-apbx", MX23_APBX_DMA_BASE_ADDR); | ||
| 72 | |||
| 73 | mxs_add_gpio("imx23-gpio", 0, MX23_PINCTRL_BASE_ADDR, MX23_INT_GPIO0); | ||
| 74 | mxs_add_gpio("imx23-gpio", 1, MX23_PINCTRL_BASE_ADDR, MX23_INT_GPIO1); | ||
| 75 | mxs_add_gpio("imx23-gpio", 2, MX23_PINCTRL_BASE_ADDR, MX23_INT_GPIO2); | ||
| 76 | } | ||
| 77 | |||
| 78 | void __init mx28_soc_init(void) | ||
| 79 | { | ||
| 80 | pinctrl_provide_dummies(); | ||
| 81 | |||
| 82 | mxs_add_dma("imx28-dma-apbh", MX23_APBH_DMA_BASE_ADDR); | ||
| 83 | mxs_add_dma("imx28-dma-apbx", MX23_APBX_DMA_BASE_ADDR); | ||
| 84 | |||
| 85 | mxs_add_gpio("imx28-gpio", 0, MX28_PINCTRL_BASE_ADDR, MX28_INT_GPIO0); | ||
| 86 | mxs_add_gpio("imx28-gpio", 1, MX28_PINCTRL_BASE_ADDR, MX28_INT_GPIO1); | ||
| 87 | mxs_add_gpio("imx28-gpio", 2, MX28_PINCTRL_BASE_ADDR, MX28_INT_GPIO2); | ||
| 88 | mxs_add_gpio("imx28-gpio", 3, MX28_PINCTRL_BASE_ADDR, MX28_INT_GPIO3); | ||
| 89 | mxs_add_gpio("imx28-gpio", 4, MX28_PINCTRL_BASE_ADDR, MX28_INT_GPIO4); | ||
| 90 | } | ||
diff --git a/arch/arm/mach-mxs/module-tx28.c b/arch/arm/mach-mxs/module-tx28.c deleted file mode 100644 index 0f71f82101cc..000000000000 --- a/arch/arm/mach-mxs/module-tx28.c +++ /dev/null | |||
| @@ -1,160 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2010 <LW@KARO-electronics.de> | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify it under | ||
| 5 | * the terms of the GNU General Public License version 2 as published by the | ||
| 6 | * Free Software Foundation. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #include <linux/delay.h> | ||
| 10 | #include <linux/fec.h> | ||
| 11 | #include <linux/gpio.h> | ||
| 12 | |||
| 13 | #include <mach/iomux-mx28.h> | ||
| 14 | #include "devices-mx28.h" | ||
| 15 | |||
| 16 | #include "module-tx28.h" | ||
| 17 | |||
| 18 | #define TX28_FEC_PHY_POWER MXS_GPIO_NR(3, 29) | ||
| 19 | #define TX28_FEC_PHY_RESET MXS_GPIO_NR(4, 13) | ||
| 20 | |||
| 21 | static const iomux_cfg_t tx28_fec_gpio_pads[] __initconst = { | ||
| 22 | /* PHY POWER */ | ||
| 23 | MX28_PAD_PWM4__GPIO_3_29 | | ||
| 24 | MXS_PAD_4MA | MXS_PAD_NOPULL | MXS_PAD_3V3, | ||
| 25 | /* PHY RESET */ | ||
| 26 | MX28_PAD_ENET0_RX_CLK__GPIO_4_13 | | ||
| 27 | MXS_PAD_4MA | MXS_PAD_NOPULL | MXS_PAD_3V3, | ||
| 28 | /* Mode strap pins 0-2 */ | ||
| 29 | MX28_PAD_ENET0_RXD0__GPIO_4_3 | | ||
| 30 | MXS_PAD_8MA | MXS_PAD_PULLUP | MXS_PAD_3V3, | ||
| 31 | MX28_PAD_ENET0_RXD1__GPIO_4_4 | | ||
| 32 | MXS_PAD_8MA | MXS_PAD_PULLUP | MXS_PAD_3V3, | ||
| 33 | MX28_PAD_ENET0_RX_EN__GPIO_4_2 | | ||
| 34 | MXS_PAD_8MA | MXS_PAD_PULLUP | MXS_PAD_3V3, | ||
| 35 | /* nINT */ | ||
| 36 | MX28_PAD_ENET0_TX_CLK__GPIO_4_5 | | ||
| 37 | MXS_PAD_4MA | MXS_PAD_NOPULL | MXS_PAD_3V3, | ||
| 38 | |||
| 39 | MX28_PAD_ENET0_MDC__GPIO_4_0, | ||
| 40 | MX28_PAD_ENET0_MDIO__GPIO_4_1, | ||
| 41 | MX28_PAD_ENET0_TX_EN__GPIO_4_6, | ||
| 42 | MX28_PAD_ENET0_TXD0__GPIO_4_7, | ||
| 43 | MX28_PAD_ENET0_TXD1__GPIO_4_8, | ||
| 44 | MX28_PAD_ENET_CLK__GPIO_4_16, | ||
| 45 | }; | ||
| 46 | |||
| 47 | #define FEC_MODE (MXS_PAD_8MA | MXS_PAD_PULLUP | MXS_PAD_3V3) | ||
| 48 | static const iomux_cfg_t tx28_fec0_pads[] __initconst = { | ||
| 49 | MX28_PAD_ENET0_MDC__ENET0_MDC | FEC_MODE, | ||
| 50 | MX28_PAD_ENET0_MDIO__ENET0_MDIO | FEC_MODE, | ||
| 51 | MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | FEC_MODE, | ||
| 52 | MX28_PAD_ENET0_RXD0__ENET0_RXD0 | FEC_MODE, | ||
| 53 | MX28_PAD_ENET0_RXD1__ENET0_RXD1 | FEC_MODE, | ||
| 54 | MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | FEC_MODE, | ||
| 55 | MX28_PAD_ENET0_TXD0__ENET0_TXD0 | FEC_MODE, | ||
| 56 | MX28_PAD_ENET0_TXD1__ENET0_TXD1 | FEC_MODE, | ||
| 57 | MX28_PAD_ENET_CLK__CLKCTRL_ENET | FEC_MODE, | ||
| 58 | }; | ||
| 59 | |||
| 60 | static const iomux_cfg_t tx28_fec1_pads[] __initconst = { | ||
| 61 | MX28_PAD_ENET0_RXD2__ENET1_RXD0, | ||
| 62 | MX28_PAD_ENET0_RXD3__ENET1_RXD1, | ||
| 63 | MX28_PAD_ENET0_TXD2__ENET1_TXD0, | ||
| 64 | MX28_PAD_ENET0_TXD3__ENET1_TXD1, | ||
| 65 | MX28_PAD_ENET0_COL__ENET1_TX_EN, | ||
| 66 | MX28_PAD_ENET0_CRS__ENET1_RX_EN, | ||
| 67 | }; | ||
| 68 | |||
| 69 | static const struct fec_platform_data tx28_fec0_data __initconst = { | ||
| 70 | .phy = PHY_INTERFACE_MODE_RMII, | ||
| 71 | }; | ||
| 72 | |||
| 73 | static const struct fec_platform_data tx28_fec1_data __initconst = { | ||
| 74 | .phy = PHY_INTERFACE_MODE_RMII, | ||
| 75 | }; | ||
| 76 | |||
| 77 | int __init tx28_add_fec0(void) | ||
| 78 | { | ||
| 79 | int i, ret; | ||
| 80 | |||
| 81 | pr_debug("%s: Switching FEC PHY power off\n", __func__); | ||
| 82 | ret = mxs_iomux_setup_multiple_pads(tx28_fec_gpio_pads, | ||
| 83 | ARRAY_SIZE(tx28_fec_gpio_pads)); | ||
| 84 | for (i = 0; i < ARRAY_SIZE(tx28_fec_gpio_pads); i++) { | ||
| 85 | unsigned int gpio = MXS_GPIO_NR(PAD_BANK(tx28_fec_gpio_pads[i]), | ||
| 86 | PAD_PIN(tx28_fec_gpio_pads[i])); | ||
| 87 | |||
| 88 | ret = gpio_request(gpio, "FEC"); | ||
| 89 | if (ret) { | ||
| 90 | pr_err("Failed to request GPIO_%d_%d: %d\n", | ||
| 91 | PAD_BANK(tx28_fec_gpio_pads[i]), | ||
| 92 | PAD_PIN(tx28_fec_gpio_pads[i]), ret); | ||
| 93 | goto free_gpios; | ||
| 94 | } | ||
| 95 | ret = gpio_direction_output(gpio, 0); | ||
| 96 | if (ret) { | ||
| 97 | pr_err("Failed to set direction of GPIO_%d_%d to output: %d\n", | ||
| 98 | gpio / 32 + 1, gpio % 32, ret); | ||
| 99 | goto free_gpios; | ||
| 100 | } | ||
| 101 | } | ||
| 102 | |||
| 103 | /* Power up fec phy */ | ||
| 104 | pr_debug("%s: Switching FEC PHY power on\n", __func__); | ||
| 105 | ret = gpio_direction_output(TX28_FEC_PHY_POWER, 1); | ||
| 106 | if (ret) { | ||
| 107 | pr_err("Failed to power on PHY: %d\n", ret); | ||
| 108 | goto free_gpios; | ||
| 109 | } | ||
| 110 | mdelay(26); /* 25ms according to data sheet */ | ||
| 111 | |||
| 112 | /* nINT */ | ||
| 113 | gpio_direction_input(MXS_GPIO_NR(4, 5)); | ||
| 114 | /* Mode strap pins */ | ||
| 115 | gpio_direction_output(MXS_GPIO_NR(4, 2), 1); | ||
| 116 | gpio_direction_output(MXS_GPIO_NR(4, 3), 1); | ||
| 117 | gpio_direction_output(MXS_GPIO_NR(4, 4), 1); | ||
| 118 | |||
| 119 | udelay(100); /* minimum assertion time for nRST */ | ||
| 120 | |||
| 121 | pr_debug("%s: Deasserting FEC PHY RESET\n", __func__); | ||
| 122 | gpio_set_value(TX28_FEC_PHY_RESET, 1); | ||
| 123 | |||
| 124 | ret = mxs_iomux_setup_multiple_pads(tx28_fec0_pads, | ||
| 125 | ARRAY_SIZE(tx28_fec0_pads)); | ||
| 126 | if (ret) { | ||
| 127 | pr_debug("%s: mxs_iomux_setup_multiple_pads() failed with rc: %d\n", | ||
| 128 | __func__, ret); | ||
| 129 | goto free_gpios; | ||
| 130 | } | ||
| 131 | pr_debug("%s: Registering FEC0 device\n", __func__); | ||
| 132 | mx28_add_fec(0, &tx28_fec0_data); | ||
| 133 | return 0; | ||
| 134 | |||
| 135 | free_gpios: | ||
| 136 | while (--i >= 0) { | ||
| 137 | unsigned int gpio = MXS_GPIO_NR(PAD_BANK(tx28_fec_gpio_pads[i]), | ||
| 138 | PAD_PIN(tx28_fec_gpio_pads[i])); | ||
| 139 | |||
| 140 | gpio_free(gpio); | ||
| 141 | } | ||
| 142 | |||
| 143 | return ret; | ||
| 144 | } | ||
| 145 | |||
| 146 | int __init tx28_add_fec1(void) | ||
| 147 | { | ||
| 148 | int ret; | ||
| 149 | |||
| 150 | ret = mxs_iomux_setup_multiple_pads(tx28_fec1_pads, | ||
| 151 | ARRAY_SIZE(tx28_fec1_pads)); | ||
| 152 | if (ret) { | ||
| 153 | pr_debug("%s: mxs_iomux_setup_multiple_pads() failed with rc: %d\n", | ||
| 154 | __func__, ret); | ||
| 155 | return ret; | ||
| 156 | } | ||
| 157 | pr_debug("%s: Registering FEC1 device\n", __func__); | ||
| 158 | mx28_add_fec(1, &tx28_fec1_data); | ||
| 159 | return 0; | ||
| 160 | } | ||
diff --git a/arch/arm/mach-mxs/module-tx28.h b/arch/arm/mach-mxs/module-tx28.h deleted file mode 100644 index 8ed425457d30..000000000000 --- a/arch/arm/mach-mxs/module-tx28.h +++ /dev/null | |||
| @@ -1,10 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2010 Pengutronix | ||
| 3 | * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it under | ||
| 6 | * the terms of the GNU General Public License version 2 as published by the | ||
| 7 | * Free Software Foundation. | ||
| 8 | */ | ||
| 9 | int __init tx28_add_fec0(void); | ||
| 10 | int __init tx28_add_fec1(void); | ||
diff --git a/arch/arm/mach-omap1/ams-delta-fiq-handler.S b/arch/arm/mach-omap1/ams-delta-fiq-handler.S index a051cb8ae57f..d2b6acce8fc1 100644 --- a/arch/arm/mach-omap1/ams-delta-fiq-handler.S +++ b/arch/arm/mach-omap1/ams-delta-fiq-handler.S | |||
| @@ -18,6 +18,7 @@ | |||
| 18 | 18 | ||
| 19 | #include <plat/board-ams-delta.h> | 19 | #include <plat/board-ams-delta.h> |
| 20 | 20 | ||
| 21 | #include <mach/irqs.h> | ||
| 21 | #include <mach/ams-delta-fiq.h> | 22 | #include <mach/ams-delta-fiq.h> |
| 22 | 23 | ||
| 23 | #include "iomap.h" | 24 | #include "iomap.h" |
diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c index c53469802c03..6f192c4900b1 100644 --- a/arch/arm/mach-omap1/board-ams-delta.c +++ b/arch/arm/mach-omap1/board-ams-delta.c | |||
| @@ -26,6 +26,7 @@ | |||
| 26 | #include <linux/export.h> | 26 | #include <linux/export.h> |
| 27 | #include <linux/omapfb.h> | 27 | #include <linux/omapfb.h> |
| 28 | #include <linux/io.h> | 28 | #include <linux/io.h> |
| 29 | #include <linux/platform_data/gpio-omap.h> | ||
| 29 | 30 | ||
| 30 | #include <media/soc_camera.h> | 31 | #include <media/soc_camera.h> |
| 31 | 32 | ||
| @@ -37,7 +38,6 @@ | |||
| 37 | #include <plat/board-ams-delta.h> | 38 | #include <plat/board-ams-delta.h> |
| 38 | #include <plat/keypad.h> | 39 | #include <plat/keypad.h> |
| 39 | #include <plat/mux.h> | 40 | #include <plat/mux.h> |
| 40 | #include <plat/board.h> | ||
| 41 | 41 | ||
| 42 | #include <mach/hardware.h> | 42 | #include <mach/hardware.h> |
| 43 | #include <mach/ams-delta-fiq.h> | 43 | #include <mach/ams-delta-fiq.h> |
diff --git a/arch/arm/mach-omap1/board-fsample.c b/arch/arm/mach-omap1/board-fsample.c index 6872f3fd400f..6d985521a39e 100644 --- a/arch/arm/mach-omap1/board-fsample.c +++ b/arch/arm/mach-omap1/board-fsample.c | |||
| @@ -32,7 +32,6 @@ | |||
| 32 | #include <plat/flash.h> | 32 | #include <plat/flash.h> |
| 33 | #include <plat/fpga.h> | 33 | #include <plat/fpga.h> |
| 34 | #include <plat/keypad.h> | 34 | #include <plat/keypad.h> |
| 35 | #include <plat/board.h> | ||
| 36 | 35 | ||
| 37 | #include <mach/hardware.h> | 36 | #include <mach/hardware.h> |
| 38 | 37 | ||
diff --git a/arch/arm/mach-omap1/board-generic.c b/arch/arm/mach-omap1/board-generic.c index 6ec385e2b98e..04b5fdaff831 100644 --- a/arch/arm/mach-omap1/board-generic.c +++ b/arch/arm/mach-omap1/board-generic.c | |||
| @@ -23,7 +23,6 @@ | |||
| 23 | #include <asm/mach/map.h> | 23 | #include <asm/mach/map.h> |
| 24 | 24 | ||
| 25 | #include <plat/mux.h> | 25 | #include <plat/mux.h> |
| 26 | #include <plat/board.h> | ||
| 27 | 26 | ||
| 28 | #include <mach/usb.h> | 27 | #include <mach/usb.h> |
| 29 | 28 | ||
| @@ -52,9 +51,6 @@ static struct omap_usb_config generic1610_usb_config __initdata = { | |||
| 52 | }; | 51 | }; |
| 53 | #endif | 52 | #endif |
| 54 | 53 | ||
| 55 | static struct omap_board_config_kernel generic_config[] __initdata = { | ||
| 56 | }; | ||
| 57 | |||
| 58 | static void __init omap_generic_init(void) | 54 | static void __init omap_generic_init(void) |
| 59 | { | 55 | { |
| 60 | #ifdef CONFIG_ARCH_OMAP15XX | 56 | #ifdef CONFIG_ARCH_OMAP15XX |
| @@ -76,8 +72,6 @@ static void __init omap_generic_init(void) | |||
| 76 | } | 72 | } |
| 77 | #endif | 73 | #endif |
| 78 | 74 | ||
| 79 | omap_board_config = generic_config; | ||
| 80 | omap_board_config_size = ARRAY_SIZE(generic_config); | ||
| 81 | omap_serial_init(); | 75 | omap_serial_init(); |
| 82 | omap_register_i2c_bus(1, 100, NULL, 0); | 76 | omap_register_i2c_bus(1, 100, NULL, 0); |
| 83 | } | 77 | } |
diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c index b3f6e943e661..a5ac352d68d3 100644 --- a/arch/arm/mach-omap1/board-htcherald.c +++ b/arch/arm/mach-omap1/board-htcherald.c | |||
| @@ -41,8 +41,7 @@ | |||
| 41 | #include <asm/mach-types.h> | 41 | #include <asm/mach-types.h> |
| 42 | #include <asm/mach/arch.h> | 42 | #include <asm/mach/arch.h> |
| 43 | 43 | ||
| 44 | #include <plat/omap7xx.h> | 44 | #include <mach/omap7xx.h> |
| 45 | #include <plat/board.h> | ||
| 46 | #include <plat/keypad.h> | 45 | #include <plat/keypad.h> |
| 47 | #include <plat/mmc.h> | 46 | #include <plat/mmc.h> |
| 48 | 47 | ||
diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c index 2c0ca8fc3380..ec01f03d0446 100644 --- a/arch/arm/mach-omap1/board-nokia770.c +++ b/arch/arm/mach-omap1/board-nokia770.c | |||
| @@ -26,7 +26,6 @@ | |||
| 26 | #include <asm/mach/map.h> | 26 | #include <asm/mach/map.h> |
| 27 | 27 | ||
| 28 | #include <plat/mux.h> | 28 | #include <plat/mux.h> |
| 29 | #include <plat/board.h> | ||
| 30 | #include <plat/keypad.h> | 29 | #include <plat/keypad.h> |
| 31 | #include <plat/lcd_mipid.h> | 30 | #include <plat/lcd_mipid.h> |
| 32 | #include <plat/mmc.h> | 31 | #include <plat/mmc.h> |
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c index 8784705edb60..3b2d9071022a 100644 --- a/arch/arm/mach-omap1/board-osk.c +++ b/arch/arm/mach-omap1/board-osk.c | |||
| @@ -39,6 +39,8 @@ | |||
| 39 | #include <linux/mtd/partitions.h> | 39 | #include <linux/mtd/partitions.h> |
| 40 | #include <linux/mtd/physmap.h> | 40 | #include <linux/mtd/physmap.h> |
| 41 | #include <linux/i2c/tps65010.h> | 41 | #include <linux/i2c/tps65010.h> |
| 42 | #include <linux/platform_data/gpio-omap.h> | ||
| 43 | #include <linux/platform_data/omap1_bl.h> | ||
| 42 | 44 | ||
| 43 | #include <asm/mach-types.h> | 45 | #include <asm/mach-types.h> |
| 44 | #include <asm/mach/arch.h> | 46 | #include <asm/mach/arch.h> |
diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c index 26bcb9defcdc..49f8d745ea1f 100644 --- a/arch/arm/mach-omap1/board-palmte.c +++ b/arch/arm/mach-omap1/board-palmte.c | |||
| @@ -28,6 +28,7 @@ | |||
| 28 | #include <linux/interrupt.h> | 28 | #include <linux/interrupt.h> |
| 29 | #include <linux/apm-emulation.h> | 29 | #include <linux/apm-emulation.h> |
| 30 | #include <linux/omapfb.h> | 30 | #include <linux/omapfb.h> |
| 31 | #include <linux/platform_data/omap1_bl.h> | ||
| 31 | 32 | ||
| 32 | #include <asm/mach-types.h> | 33 | #include <asm/mach-types.h> |
| 33 | #include <asm/mach/arch.h> | 34 | #include <asm/mach/arch.h> |
| @@ -37,7 +38,6 @@ | |||
| 37 | #include <plat/mux.h> | 38 | #include <plat/mux.h> |
| 38 | #include <plat/tc.h> | 39 | #include <plat/tc.h> |
| 39 | #include <plat/dma.h> | 40 | #include <plat/dma.h> |
| 40 | #include <plat/board.h> | ||
| 41 | #include <plat/irda.h> | 41 | #include <plat/irda.h> |
| 42 | #include <plat/keypad.h> | 42 | #include <plat/keypad.h> |
| 43 | 43 | ||
diff --git a/arch/arm/mach-omap1/board-palmtt.c b/arch/arm/mach-omap1/board-palmtt.c index 4d099446dfa8..01523cd78e58 100644 --- a/arch/arm/mach-omap1/board-palmtt.c +++ b/arch/arm/mach-omap1/board-palmtt.c | |||
| @@ -27,6 +27,7 @@ | |||
| 27 | #include <linux/omapfb.h> | 27 | #include <linux/omapfb.h> |
| 28 | #include <linux/spi/spi.h> | 28 | #include <linux/spi/spi.h> |
| 29 | #include <linux/spi/ads7846.h> | 29 | #include <linux/spi/ads7846.h> |
| 30 | #include <linux/platform_data/omap1_bl.h> | ||
| 30 | 31 | ||
| 31 | #include <asm/mach-types.h> | 32 | #include <asm/mach-types.h> |
| 32 | #include <asm/mach/arch.h> | 33 | #include <asm/mach/arch.h> |
| @@ -37,7 +38,6 @@ | |||
| 37 | #include <plat/mux.h> | 38 | #include <plat/mux.h> |
| 38 | #include <plat/dma.h> | 39 | #include <plat/dma.h> |
| 39 | #include <plat/tc.h> | 40 | #include <plat/tc.h> |
| 40 | #include <plat/board.h> | ||
| 41 | #include <plat/irda.h> | 41 | #include <plat/irda.h> |
| 42 | #include <plat/keypad.h> | 42 | #include <plat/keypad.h> |
| 43 | 43 | ||
diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c index 355980321c2d..a7abce69043a 100644 --- a/arch/arm/mach-omap1/board-palmz71.c +++ b/arch/arm/mach-omap1/board-palmz71.c | |||
| @@ -30,6 +30,7 @@ | |||
| 30 | #include <linux/omapfb.h> | 30 | #include <linux/omapfb.h> |
| 31 | #include <linux/spi/spi.h> | 31 | #include <linux/spi/spi.h> |
| 32 | #include <linux/spi/ads7846.h> | 32 | #include <linux/spi/ads7846.h> |
| 33 | #include <linux/platform_data/omap1_bl.h> | ||
| 33 | 34 | ||
| 34 | #include <asm/mach-types.h> | 35 | #include <asm/mach-types.h> |
| 35 | #include <asm/mach/arch.h> | 36 | #include <asm/mach/arch.h> |
| @@ -39,7 +40,6 @@ | |||
| 39 | #include <plat/mux.h> | 40 | #include <plat/mux.h> |
| 40 | #include <plat/dma.h> | 41 | #include <plat/dma.h> |
| 41 | #include <plat/tc.h> | 42 | #include <plat/tc.h> |
| 42 | #include <plat/board.h> | ||
| 43 | #include <plat/irda.h> | 43 | #include <plat/irda.h> |
| 44 | #include <plat/keypad.h> | 44 | #include <plat/keypad.h> |
| 45 | 45 | ||
diff --git a/arch/arm/mach-omap1/board-perseus2.c b/arch/arm/mach-omap1/board-perseus2.c index 703d55ecffe2..277e0bc60a43 100644 --- a/arch/arm/mach-omap1/board-perseus2.c +++ b/arch/arm/mach-omap1/board-perseus2.c | |||
| @@ -32,7 +32,6 @@ | |||
| 32 | #include <plat/fpga.h> | 32 | #include <plat/fpga.h> |
| 33 | #include <plat/flash.h> | 33 | #include <plat/flash.h> |
| 34 | #include <plat/keypad.h> | 34 | #include <plat/keypad.h> |
| 35 | #include <plat/board.h> | ||
| 36 | 35 | ||
| 37 | #include <mach/hardware.h> | 36 | #include <mach/hardware.h> |
| 38 | 37 | ||
diff --git a/arch/arm/mach-omap1/board-sx1.c b/arch/arm/mach-omap1/board-sx1.c index 8c665bd16ac2..2e1fff26a2f3 100644 --- a/arch/arm/mach-omap1/board-sx1.c +++ b/arch/arm/mach-omap1/board-sx1.c | |||
| @@ -38,7 +38,6 @@ | |||
| 38 | #include <plat/dma.h> | 38 | #include <plat/dma.h> |
| 39 | #include <plat/irda.h> | 39 | #include <plat/irda.h> |
| 40 | #include <plat/tc.h> | 40 | #include <plat/tc.h> |
| 41 | #include <plat/board.h> | ||
| 42 | #include <plat/keypad.h> | 41 | #include <plat/keypad.h> |
| 43 | #include <plat/board-sx1.h> | 42 | #include <plat/board-sx1.h> |
| 44 | 43 | ||
diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c index 3497769eb353..1668af3017de 100644 --- a/arch/arm/mach-omap1/board-voiceblue.c +++ b/arch/arm/mach-omap1/board-voiceblue.c | |||
| @@ -35,7 +35,6 @@ | |||
| 35 | #include <plat/flash.h> | 35 | #include <plat/flash.h> |
| 36 | #include <plat/mux.h> | 36 | #include <plat/mux.h> |
| 37 | #include <plat/tc.h> | 37 | #include <plat/tc.h> |
| 38 | #include <plat/board.h> | ||
| 39 | 38 | ||
| 40 | #include <mach/hardware.h> | 39 | #include <mach/hardware.h> |
| 41 | #include <mach/usb.h> | 40 | #include <mach/usb.h> |
| @@ -155,9 +154,6 @@ static struct omap_usb_config voiceblue_usb_config __initdata = { | |||
| 155 | .pins[2] = 6, | 154 | .pins[2] = 6, |
| 156 | }; | 155 | }; |
| 157 | 156 | ||
| 158 | static struct omap_board_config_kernel voiceblue_config[] = { | ||
| 159 | }; | ||
| 160 | |||
| 161 | #define MACHINE_PANICED 1 | 157 | #define MACHINE_PANICED 1 |
| 162 | #define MACHINE_REBOOTING 2 | 158 | #define MACHINE_REBOOTING 2 |
| 163 | #define MACHINE_REBOOT 4 | 159 | #define MACHINE_REBOOT 4 |
| @@ -275,8 +271,6 @@ static void __init voiceblue_init(void) | |||
| 275 | voiceblue_smc91x_resources[1].start = gpio_to_irq(8); | 271 | voiceblue_smc91x_resources[1].start = gpio_to_irq(8); |
| 276 | voiceblue_smc91x_resources[1].end = gpio_to_irq(8); | 272 | voiceblue_smc91x_resources[1].end = gpio_to_irq(8); |
| 277 | platform_add_devices(voiceblue_devices, ARRAY_SIZE(voiceblue_devices)); | 273 | platform_add_devices(voiceblue_devices, ARRAY_SIZE(voiceblue_devices)); |
| 278 | omap_board_config = voiceblue_config; | ||
| 279 | omap_board_config_size = ARRAY_SIZE(voiceblue_config); | ||
| 280 | omap_serial_init(); | 274 | omap_serial_init(); |
| 281 | omap1_usb_init(&voiceblue_usb_config); | 275 | omap1_usb_init(&voiceblue_usb_config); |
| 282 | omap_register_i2c_bus(1, 100, NULL, 0); | 276 | omap_register_i2c_bus(1, 100, NULL, 0); |
diff --git a/arch/arm/mach-omap1/clock_data.c b/arch/arm/mach-omap1/clock_data.c index c007d80dfb62..6a32b9b0dc30 100644 --- a/arch/arm/mach-omap1/clock_data.c +++ b/arch/arm/mach-omap1/clock_data.c | |||
| @@ -25,7 +25,6 @@ | |||
| 25 | #include <plat/clock.h> | 25 | #include <plat/clock.h> |
| 26 | #include <plat/cpu.h> | 26 | #include <plat/cpu.h> |
| 27 | #include <plat/clkdev_omap.h> | 27 | #include <plat/clkdev_omap.h> |
| 28 | #include <plat/board.h> | ||
| 29 | #include <plat/sram.h> /* for omap_sram_reprogram_clock() */ | 28 | #include <plat/sram.h> /* for omap_sram_reprogram_clock() */ |
| 30 | 29 | ||
| 31 | #include <mach/hardware.h> | 30 | #include <mach/hardware.h> |
| @@ -788,7 +787,6 @@ u32 cpu_mask; | |||
| 788 | int __init omap1_clk_init(void) | 787 | int __init omap1_clk_init(void) |
| 789 | { | 788 | { |
| 790 | struct omap_clk *c; | 789 | struct omap_clk *c; |
| 791 | const struct omap_clock_config *info; | ||
| 792 | int crystal_type = 0; /* Default 12 MHz */ | 790 | int crystal_type = 0; /* Default 12 MHz */ |
| 793 | u32 reg; | 791 | u32 reg; |
| 794 | 792 | ||
| @@ -837,12 +835,6 @@ int __init omap1_clk_init(void) | |||
| 837 | ck_dpll1_p = clk_get(NULL, "ck_dpll1"); | 835 | ck_dpll1_p = clk_get(NULL, "ck_dpll1"); |
| 838 | ck_ref_p = clk_get(NULL, "ck_ref"); | 836 | ck_ref_p = clk_get(NULL, "ck_ref"); |
| 839 | 837 | ||
| 840 | info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config); | ||
| 841 | if (info != NULL) { | ||
| 842 | if (!cpu_is_omap15xx()) | ||
| 843 | crystal_type = info->system_clock_type; | ||
| 844 | } | ||
| 845 | |||
| 846 | if (cpu_is_omap7xx()) | 838 | if (cpu_is_omap7xx()) |
| 847 | ck_ref.rate = 13000000; | 839 | ck_ref.rate = 13000000; |
| 848 | if (cpu_is_omap16xx() && crystal_type == 2) | 840 | if (cpu_is_omap16xx() && crystal_type == 2) |
diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c index fa1fa4deb6aa..05fdbd992c77 100644 --- a/arch/arm/mach-omap1/devices.c +++ b/arch/arm/mach-omap1/devices.c | |||
| @@ -20,12 +20,11 @@ | |||
| 20 | #include <asm/mach/map.h> | 20 | #include <asm/mach/map.h> |
| 21 | 21 | ||
| 22 | #include <plat/tc.h> | 22 | #include <plat/tc.h> |
| 23 | #include <plat/board.h> | ||
| 24 | #include <plat/mux.h> | 23 | #include <plat/mux.h> |
| 25 | #include <plat/dma.h> | 24 | #include <plat/dma.h> |
| 26 | #include <plat/mmc.h> | 25 | #include <plat/mmc.h> |
| 27 | #include <plat/omap7xx.h> | ||
| 28 | 26 | ||
| 27 | #include <mach/omap7xx.h> | ||
| 29 | #include <mach/camera.h> | 28 | #include <mach/camera.h> |
| 30 | #include <mach/hardware.h> | 29 | #include <mach/hardware.h> |
| 31 | 30 | ||
diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c index 3ef7d52316b4..b0b0f0f27450 100644 --- a/arch/arm/mach-omap1/dma.c +++ b/arch/arm/mach-omap1/dma.c | |||
| @@ -27,7 +27,8 @@ | |||
| 27 | 27 | ||
| 28 | #include <plat/dma.h> | 28 | #include <plat/dma.h> |
| 29 | #include <plat/tc.h> | 29 | #include <plat/tc.h> |
| 30 | #include <plat/irqs.h> | 30 | |
| 31 | #include <mach/irqs.h> | ||
| 31 | 32 | ||
| 32 | #define OMAP1_DMA_BASE (0xfffed800) | 33 | #define OMAP1_DMA_BASE (0xfffed800) |
| 33 | #define OMAP1_LOGICAL_DMA_CH_COUNT 17 | 34 | #define OMAP1_LOGICAL_DMA_CH_COUNT 17 |
diff --git a/arch/arm/mach-omap1/gpio15xx.c b/arch/arm/mach-omap1/gpio15xx.c index ebef15e5e7b7..98e6f39224a4 100644 --- a/arch/arm/mach-omap1/gpio15xx.c +++ b/arch/arm/mach-omap1/gpio15xx.c | |||
| @@ -17,6 +17,7 @@ | |||
| 17 | */ | 17 | */ |
| 18 | 18 | ||
| 19 | #include <linux/gpio.h> | 19 | #include <linux/gpio.h> |
| 20 | #include <linux/platform_data/gpio-omap.h> | ||
| 20 | 21 | ||
| 21 | #define OMAP1_MPUIO_VBASE OMAP1_MPUIO_BASE | 22 | #define OMAP1_MPUIO_VBASE OMAP1_MPUIO_BASE |
| 22 | #define OMAP1510_GPIO_BASE 0xFFFCE000 | 23 | #define OMAP1510_GPIO_BASE 0xFFFCE000 |
diff --git a/arch/arm/mach-omap1/gpio16xx.c b/arch/arm/mach-omap1/gpio16xx.c index 2a48cd2e1754..33f419236b17 100644 --- a/arch/arm/mach-omap1/gpio16xx.c +++ b/arch/arm/mach-omap1/gpio16xx.c | |||
| @@ -17,6 +17,7 @@ | |||
| 17 | */ | 17 | */ |
| 18 | 18 | ||
| 19 | #include <linux/gpio.h> | 19 | #include <linux/gpio.h> |
| 20 | #include <linux/platform_data/gpio-omap.h> | ||
| 20 | 21 | ||
| 21 | #define OMAP1610_GPIO1_BASE 0xfffbe400 | 22 | #define OMAP1610_GPIO1_BASE 0xfffbe400 |
| 22 | #define OMAP1610_GPIO2_BASE 0xfffbec00 | 23 | #define OMAP1610_GPIO2_BASE 0xfffbec00 |
diff --git a/arch/arm/mach-omap1/gpio7xx.c b/arch/arm/mach-omap1/gpio7xx.c index acf12b73eace..958ce9acee95 100644 --- a/arch/arm/mach-omap1/gpio7xx.c +++ b/arch/arm/mach-omap1/gpio7xx.c | |||
| @@ -17,6 +17,7 @@ | |||
| 17 | */ | 17 | */ |
| 18 | 18 | ||
| 19 | #include <linux/gpio.h> | 19 | #include <linux/gpio.h> |
| 20 | #include <linux/platform_data/gpio-omap.h> | ||
| 20 | 21 | ||
| 21 | #define OMAP7XX_GPIO1_BASE 0xfffbc000 | 22 | #define OMAP7XX_GPIO1_BASE 0xfffbc000 |
| 22 | #define OMAP7XX_GPIO2_BASE 0xfffbc800 | 23 | #define OMAP7XX_GPIO2_BASE 0xfffbc800 |
diff --git a/arch/arm/mach-omap1/include/mach/ams-delta-fiq.h b/arch/arm/mach-omap1/include/mach/ams-delta-fiq.h index 23eed0035ed8..adb5e7649659 100644 --- a/arch/arm/mach-omap1/include/mach/ams-delta-fiq.h +++ b/arch/arm/mach-omap1/include/mach/ams-delta-fiq.h | |||
| @@ -14,8 +14,6 @@ | |||
| 14 | #ifndef __AMS_DELTA_FIQ_H | 14 | #ifndef __AMS_DELTA_FIQ_H |
| 15 | #define __AMS_DELTA_FIQ_H | 15 | #define __AMS_DELTA_FIQ_H |
| 16 | 16 | ||
| 17 | #include <plat/irqs.h> | ||
| 18 | |||
| 19 | /* | 17 | /* |
| 20 | * Interrupt number used for passing control from FIQ to IRQ. | 18 | * Interrupt number used for passing control from FIQ to IRQ. |
| 21 | * IRQ12, described as reserved, has been selected. | 19 | * IRQ12, described as reserved, has been selected. |
diff --git a/arch/arm/mach-omap1/include/mach/gpio.h b/arch/arm/mach-omap1/include/mach/gpio.h index e737706a8fe1..ebf86c0f4f46 100644 --- a/arch/arm/mach-omap1/include/mach/gpio.h +++ b/arch/arm/mach-omap1/include/mach/gpio.h | |||
| @@ -1,5 +1,3 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * arch/arm/mach-omap1/include/mach/gpio.h | 2 | * arch/arm/mach-omap1/include/mach/gpio.h |
| 3 | */ | 3 | */ |
| 4 | |||
| 5 | #include <plat/gpio.h> | ||
diff --git a/arch/arm/mach-omap1/include/mach/hardware.h b/arch/arm/mach-omap1/include/mach/hardware.h index 01e35fa106b8..84248d250adb 100644 --- a/arch/arm/mach-omap1/include/mach/hardware.h +++ b/arch/arm/mach-omap1/include/mach/hardware.h | |||
| @@ -1,11 +1,46 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * arch/arm/mach-omap1/include/mach/hardware.h | 2 | * arch/arm/mach-omap1/include/mach/hardware.h |
| 3 | * | ||
| 4 | * Hardware definitions for TI OMAP processors and boards | ||
| 5 | * | ||
| 6 | * NOTE: Please put device driver specific defines into a separate header | ||
| 7 | * file for each driver. | ||
| 8 | * | ||
| 9 | * Copyright (C) 2001 RidgeRun, Inc. | ||
| 10 | * Author: RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com> | ||
| 11 | * | ||
| 12 | * Reorganized for Linux-2.6 by Tony Lindgren <tony@atomide.com> | ||
| 13 | * and Dirk Behme <dirk.behme@de.bosch.com> | ||
| 14 | * | ||
| 15 | * This program is free software; you can redistribute it and/or modify it | ||
| 16 | * under the terms of the GNU General Public License as published by the | ||
| 17 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 18 | * option) any later version. | ||
| 19 | * | ||
| 20 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
| 21 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
| 22 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
| 23 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
| 24 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
| 25 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
| 26 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
| 27 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
| 28 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
| 29 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
| 30 | * | ||
| 31 | * You should have received a copy of the GNU General Public License along | ||
| 32 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 33 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 3 | */ | 34 | */ |
| 4 | 35 | ||
| 5 | #ifndef __MACH_HARDWARE_H | 36 | #ifndef __ASM_ARCH_OMAP_HARDWARE_H |
| 6 | #define __MACH_HARDWARE_H | 37 | #define __ASM_ARCH_OMAP_HARDWARE_H |
| 7 | 38 | ||
| 39 | #include <asm/sizes.h> | ||
| 8 | #ifndef __ASSEMBLER__ | 40 | #ifndef __ASSEMBLER__ |
| 41 | #include <asm/types.h> | ||
| 42 | #include <plat/cpu.h> | ||
| 43 | |||
| 9 | /* | 44 | /* |
| 10 | * NOTE: Please use ioremap + __raw_read/write where possible instead of these | 45 | * NOTE: Please use ioremap + __raw_read/write where possible instead of these |
| 11 | */ | 46 | */ |
| @@ -35,7 +70,249 @@ static inline u32 omap_cs3_phys(void) | |||
| 35 | ? 0 : OMAP_CS3_PHYS; | 70 | ? 0 : OMAP_CS3_PHYS; |
| 36 | } | 71 | } |
| 37 | 72 | ||
| 73 | #endif /* ifndef __ASSEMBLER__ */ | ||
| 74 | |||
| 75 | #include <plat/serial.h> | ||
| 76 | |||
| 77 | /* | ||
| 78 | * --------------------------------------------------------------------------- | ||
| 79 | * Common definitions for all OMAP processors | ||
| 80 | * NOTE: Put all processor or board specific parts to the special header | ||
| 81 | * files. | ||
| 82 | * --------------------------------------------------------------------------- | ||
| 83 | */ | ||
| 84 | |||
| 85 | /* | ||
| 86 | * ---------------------------------------------------------------------------- | ||
| 87 | * Timers | ||
| 88 | * ---------------------------------------------------------------------------- | ||
| 89 | */ | ||
| 90 | #define OMAP_MPU_TIMER1_BASE (0xfffec500) | ||
| 91 | #define OMAP_MPU_TIMER2_BASE (0xfffec600) | ||
| 92 | #define OMAP_MPU_TIMER3_BASE (0xfffec700) | ||
| 93 | #define MPU_TIMER_FREE (1 << 6) | ||
| 94 | #define MPU_TIMER_CLOCK_ENABLE (1 << 5) | ||
| 95 | #define MPU_TIMER_AR (1 << 1) | ||
| 96 | #define MPU_TIMER_ST (1 << 0) | ||
| 97 | |||
| 98 | /* | ||
| 99 | * ---------------------------------------------------------------------------- | ||
| 100 | * Clocks | ||
| 101 | * ---------------------------------------------------------------------------- | ||
| 102 | */ | ||
| 103 | #define CLKGEN_REG_BASE (0xfffece00) | ||
| 104 | #define ARM_CKCTL (CLKGEN_REG_BASE + 0x0) | ||
| 105 | #define ARM_IDLECT1 (CLKGEN_REG_BASE + 0x4) | ||
| 106 | #define ARM_IDLECT2 (CLKGEN_REG_BASE + 0x8) | ||
| 107 | #define ARM_EWUPCT (CLKGEN_REG_BASE + 0xC) | ||
| 108 | #define ARM_RSTCT1 (CLKGEN_REG_BASE + 0x10) | ||
| 109 | #define ARM_RSTCT2 (CLKGEN_REG_BASE + 0x14) | ||
| 110 | #define ARM_SYSST (CLKGEN_REG_BASE + 0x18) | ||
| 111 | #define ARM_IDLECT3 (CLKGEN_REG_BASE + 0x24) | ||
| 112 | |||
| 113 | #define CK_RATEF 1 | ||
| 114 | #define CK_IDLEF 2 | ||
| 115 | #define CK_ENABLEF 4 | ||
| 116 | #define CK_SELECTF 8 | ||
| 117 | #define SETARM_IDLE_SHIFT | ||
| 118 | |||
| 119 | /* DPLL control registers */ | ||
| 120 | #define DPLL_CTL (0xfffecf00) | ||
| 121 | |||
| 122 | /* DSP clock control. Must use __raw_readw() and __raw_writew() with these */ | ||
| 123 | #define DSP_CONFIG_REG_BASE IOMEM(0xe1008000) | ||
| 124 | #define DSP_CKCTL (DSP_CONFIG_REG_BASE + 0x0) | ||
| 125 | #define DSP_IDLECT1 (DSP_CONFIG_REG_BASE + 0x4) | ||
| 126 | #define DSP_IDLECT2 (DSP_CONFIG_REG_BASE + 0x8) | ||
| 127 | #define DSP_RSTCT2 (DSP_CONFIG_REG_BASE + 0x14) | ||
| 128 | |||
| 129 | /* | ||
| 130 | * --------------------------------------------------------------------------- | ||
| 131 | * UPLD | ||
| 132 | * --------------------------------------------------------------------------- | ||
| 133 | */ | ||
| 134 | #define ULPD_REG_BASE (0xfffe0800) | ||
| 135 | #define ULPD_IT_STATUS (ULPD_REG_BASE + 0x14) | ||
| 136 | #define ULPD_SETUP_ANALOG_CELL_3 (ULPD_REG_BASE + 0x24) | ||
| 137 | #define ULPD_CLOCK_CTRL (ULPD_REG_BASE + 0x30) | ||
| 138 | # define DIS_USB_PVCI_CLK (1 << 5) /* no USB/FAC synch */ | ||
| 139 | # define USB_MCLK_EN (1 << 4) /* enable W4_USB_CLKO */ | ||
| 140 | #define ULPD_SOFT_REQ (ULPD_REG_BASE + 0x34) | ||
| 141 | # define SOFT_UDC_REQ (1 << 4) | ||
| 142 | # define SOFT_USB_CLK_REQ (1 << 3) | ||
| 143 | # define SOFT_DPLL_REQ (1 << 0) | ||
| 144 | #define ULPD_DPLL_CTRL (ULPD_REG_BASE + 0x3c) | ||
| 145 | #define ULPD_STATUS_REQ (ULPD_REG_BASE + 0x40) | ||
| 146 | #define ULPD_APLL_CTRL (ULPD_REG_BASE + 0x4c) | ||
| 147 | #define ULPD_POWER_CTRL (ULPD_REG_BASE + 0x50) | ||
| 148 | #define ULPD_SOFT_DISABLE_REQ_REG (ULPD_REG_BASE + 0x68) | ||
| 149 | # define DIS_MMC2_DPLL_REQ (1 << 11) | ||
| 150 | # define DIS_MMC1_DPLL_REQ (1 << 10) | ||
| 151 | # define DIS_UART3_DPLL_REQ (1 << 9) | ||
| 152 | # define DIS_UART2_DPLL_REQ (1 << 8) | ||
| 153 | # define DIS_UART1_DPLL_REQ (1 << 7) | ||
| 154 | # define DIS_USB_HOST_DPLL_REQ (1 << 6) | ||
| 155 | #define ULPD_SDW_CLK_DIV_CTRL_SEL (ULPD_REG_BASE + 0x74) | ||
| 156 | #define ULPD_CAM_CLK_CTRL (ULPD_REG_BASE + 0x7c) | ||
| 157 | |||
| 158 | /* | ||
| 159 | * --------------------------------------------------------------------------- | ||
| 160 | * Watchdog timer | ||
| 161 | * --------------------------------------------------------------------------- | ||
| 162 | */ | ||
| 163 | |||
| 164 | /* Watchdog timer within the OMAP3.2 gigacell */ | ||
| 165 | #define OMAP_MPU_WATCHDOG_BASE (0xfffec800) | ||
| 166 | #define OMAP_WDT_TIMER (OMAP_MPU_WATCHDOG_BASE + 0x0) | ||
| 167 | #define OMAP_WDT_LOAD_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4) | ||
| 168 | #define OMAP_WDT_READ_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4) | ||
| 169 | #define OMAP_WDT_TIMER_MODE (OMAP_MPU_WATCHDOG_BASE + 0x8) | ||
| 170 | |||
| 171 | /* | ||
| 172 | * --------------------------------------------------------------------------- | ||
| 173 | * Interrupts | ||
| 174 | * --------------------------------------------------------------------------- | ||
| 175 | */ | ||
| 176 | #ifdef CONFIG_ARCH_OMAP1 | ||
| 177 | |||
| 178 | /* | ||
| 179 | * XXX: These probably want to be moved to arch/arm/mach-omap/omap1/irq.c | ||
| 180 | * or something similar.. -- PFM. | ||
| 181 | */ | ||
| 182 | |||
| 183 | #define OMAP_IH1_BASE 0xfffecb00 | ||
| 184 | #define OMAP_IH2_BASE 0xfffe0000 | ||
| 185 | |||
| 186 | #define OMAP_IH1_ITR (OMAP_IH1_BASE + 0x00) | ||
| 187 | #define OMAP_IH1_MIR (OMAP_IH1_BASE + 0x04) | ||
| 188 | #define OMAP_IH1_SIR_IRQ (OMAP_IH1_BASE + 0x10) | ||
| 189 | #define OMAP_IH1_SIR_FIQ (OMAP_IH1_BASE + 0x14) | ||
| 190 | #define OMAP_IH1_CONTROL (OMAP_IH1_BASE + 0x18) | ||
| 191 | #define OMAP_IH1_ILR0 (OMAP_IH1_BASE + 0x1c) | ||
| 192 | #define OMAP_IH1_ISR (OMAP_IH1_BASE + 0x9c) | ||
| 193 | |||
| 194 | #define OMAP_IH2_ITR (OMAP_IH2_BASE + 0x00) | ||
| 195 | #define OMAP_IH2_MIR (OMAP_IH2_BASE + 0x04) | ||
| 196 | #define OMAP_IH2_SIR_IRQ (OMAP_IH2_BASE + 0x10) | ||
| 197 | #define OMAP_IH2_SIR_FIQ (OMAP_IH2_BASE + 0x14) | ||
| 198 | #define OMAP_IH2_CONTROL (OMAP_IH2_BASE + 0x18) | ||
| 199 | #define OMAP_IH2_ILR0 (OMAP_IH2_BASE + 0x1c) | ||
| 200 | #define OMAP_IH2_ISR (OMAP_IH2_BASE + 0x9c) | ||
| 201 | |||
| 202 | #define IRQ_ITR_REG_OFFSET 0x00 | ||
| 203 | #define IRQ_MIR_REG_OFFSET 0x04 | ||
| 204 | #define IRQ_SIR_IRQ_REG_OFFSET 0x10 | ||
| 205 | #define IRQ_SIR_FIQ_REG_OFFSET 0x14 | ||
| 206 | #define IRQ_CONTROL_REG_OFFSET 0x18 | ||
| 207 | #define IRQ_ISR_REG_OFFSET 0x9c | ||
| 208 | #define IRQ_ILR0_REG_OFFSET 0x1c | ||
| 209 | #define IRQ_GMR_REG_OFFSET 0xa0 | ||
| 210 | |||
| 38 | #endif | 211 | #endif |
| 39 | #endif | ||
| 40 | 212 | ||
| 41 | #include <plat/hardware.h> | 213 | /* |
| 214 | * ---------------------------------------------------------------------------- | ||
| 215 | * System control registers | ||
| 216 | * ---------------------------------------------------------------------------- | ||
| 217 | */ | ||
| 218 | #define MOD_CONF_CTRL_0 0xfffe1080 | ||
| 219 | #define MOD_CONF_CTRL_1 0xfffe1110 | ||
| 220 | |||
| 221 | /* | ||
| 222 | * ---------------------------------------------------------------------------- | ||
| 223 | * Pin multiplexing registers | ||
| 224 | * ---------------------------------------------------------------------------- | ||
| 225 | */ | ||
| 226 | #define FUNC_MUX_CTRL_0 0xfffe1000 | ||
| 227 | #define FUNC_MUX_CTRL_1 0xfffe1004 | ||
| 228 | #define FUNC_MUX_CTRL_2 0xfffe1008 | ||
| 229 | #define COMP_MODE_CTRL_0 0xfffe100c | ||
| 230 | #define FUNC_MUX_CTRL_3 0xfffe1010 | ||
| 231 | #define FUNC_MUX_CTRL_4 0xfffe1014 | ||
| 232 | #define FUNC_MUX_CTRL_5 0xfffe1018 | ||
| 233 | #define FUNC_MUX_CTRL_6 0xfffe101C | ||
| 234 | #define FUNC_MUX_CTRL_7 0xfffe1020 | ||
| 235 | #define FUNC_MUX_CTRL_8 0xfffe1024 | ||
| 236 | #define FUNC_MUX_CTRL_9 0xfffe1028 | ||
| 237 | #define FUNC_MUX_CTRL_A 0xfffe102C | ||
| 238 | #define FUNC_MUX_CTRL_B 0xfffe1030 | ||
| 239 | #define FUNC_MUX_CTRL_C 0xfffe1034 | ||
| 240 | #define FUNC_MUX_CTRL_D 0xfffe1038 | ||
| 241 | #define PULL_DWN_CTRL_0 0xfffe1040 | ||
| 242 | #define PULL_DWN_CTRL_1 0xfffe1044 | ||
| 243 | #define PULL_DWN_CTRL_2 0xfffe1048 | ||
| 244 | #define PULL_DWN_CTRL_3 0xfffe104c | ||
| 245 | #define PULL_DWN_CTRL_4 0xfffe10ac | ||
| 246 | |||
| 247 | /* OMAP-1610 specific multiplexing registers */ | ||
| 248 | #define FUNC_MUX_CTRL_E 0xfffe1090 | ||
| 249 | #define FUNC_MUX_CTRL_F 0xfffe1094 | ||
| 250 | #define FUNC_MUX_CTRL_10 0xfffe1098 | ||
| 251 | #define FUNC_MUX_CTRL_11 0xfffe109c | ||
| 252 | #define FUNC_MUX_CTRL_12 0xfffe10a0 | ||
| 253 | #define PU_PD_SEL_0 0xfffe10b4 | ||
| 254 | #define PU_PD_SEL_1 0xfffe10b8 | ||
| 255 | #define PU_PD_SEL_2 0xfffe10bc | ||
| 256 | #define PU_PD_SEL_3 0xfffe10c0 | ||
| 257 | #define PU_PD_SEL_4 0xfffe10c4 | ||
| 258 | |||
| 259 | /* Timer32K for 1610 and 1710*/ | ||
| 260 | #define OMAP_TIMER32K_BASE 0xFFFBC400 | ||
| 261 | |||
| 262 | /* | ||
| 263 | * --------------------------------------------------------------------------- | ||
| 264 | * TIPB bus interface | ||
| 265 | * --------------------------------------------------------------------------- | ||
| 266 | */ | ||
| 267 | #define TIPB_PUBLIC_CNTL_BASE 0xfffed300 | ||
| 268 | #define MPU_PUBLIC_TIPB_CNTL (TIPB_PUBLIC_CNTL_BASE + 0x8) | ||
| 269 | #define TIPB_PRIVATE_CNTL_BASE 0xfffeca00 | ||
| 270 | #define MPU_PRIVATE_TIPB_CNTL (TIPB_PRIVATE_CNTL_BASE + 0x8) | ||
| 271 | |||
| 272 | /* | ||
| 273 | * ---------------------------------------------------------------------------- | ||
| 274 | * MPUI interface | ||
| 275 | * ---------------------------------------------------------------------------- | ||
| 276 | */ | ||
| 277 | #define MPUI_BASE (0xfffec900) | ||
| 278 | #define MPUI_CTRL (MPUI_BASE + 0x0) | ||
| 279 | #define MPUI_DEBUG_ADDR (MPUI_BASE + 0x4) | ||
| 280 | #define MPUI_DEBUG_DATA (MPUI_BASE + 0x8) | ||
| 281 | #define MPUI_DEBUG_FLAG (MPUI_BASE + 0xc) | ||
| 282 | #define MPUI_STATUS_REG (MPUI_BASE + 0x10) | ||
| 283 | #define MPUI_DSP_STATUS (MPUI_BASE + 0x14) | ||
| 284 | #define MPUI_DSP_BOOT_CONFIG (MPUI_BASE + 0x18) | ||
| 285 | #define MPUI_DSP_API_CONFIG (MPUI_BASE + 0x1c) | ||
| 286 | |||
| 287 | /* | ||
| 288 | * ---------------------------------------------------------------------------- | ||
| 289 | * LED Pulse Generator | ||
| 290 | * ---------------------------------------------------------------------------- | ||
| 291 | */ | ||
| 292 | #define OMAP_LPG1_BASE 0xfffbd000 | ||
| 293 | #define OMAP_LPG2_BASE 0xfffbd800 | ||
| 294 | #define OMAP_LPG1_LCR (OMAP_LPG1_BASE + 0x00) | ||
| 295 | #define OMAP_LPG1_PMR (OMAP_LPG1_BASE + 0x04) | ||
| 296 | #define OMAP_LPG2_LCR (OMAP_LPG2_BASE + 0x00) | ||
| 297 | #define OMAP_LPG2_PMR (OMAP_LPG2_BASE + 0x04) | ||
| 298 | |||
| 299 | /* | ||
| 300 | * ---------------------------------------------------------------------------- | ||
| 301 | * Pulse-Width Light | ||
| 302 | * ---------------------------------------------------------------------------- | ||
| 303 | */ | ||
| 304 | #define OMAP_PWL_BASE 0xfffb5800 | ||
| 305 | #define OMAP_PWL_ENABLE (OMAP_PWL_BASE + 0x00) | ||
| 306 | #define OMAP_PWL_CLK_ENABLE (OMAP_PWL_BASE + 0x04) | ||
| 307 | |||
| 308 | /* | ||
| 309 | * --------------------------------------------------------------------------- | ||
| 310 | * Processor specific defines | ||
| 311 | * --------------------------------------------------------------------------- | ||
| 312 | */ | ||
| 313 | |||
| 314 | #include "omap7xx.h" | ||
| 315 | #include "omap1510.h" | ||
| 316 | #include "omap16xx.h" | ||
| 317 | |||
| 318 | #endif /* __ASM_ARCH_OMAP_HARDWARE_H */ | ||
diff --git a/arch/arm/mach-omap1/include/mach/irqs.h b/arch/arm/mach-omap1/include/mach/irqs.h index 9292fdc1cb0b..729992d7d26a 100644 --- a/arch/arm/mach-omap1/include/mach/irqs.h +++ b/arch/arm/mach-omap1/include/mach/irqs.h | |||
| @@ -1,5 +1,268 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * arch/arm/mach-omap1/include/mach/irqs.h | 2 | * arch/arm/plat-omap/include/mach/irqs.h |
| 3 | * | ||
| 4 | * Copyright (C) Greg Lonnon 2001 | ||
| 5 | * Updated for OMAP-1610 by Tony Lindgren <tony@atomide.com> | ||
| 6 | * | ||
| 7 | * Copyright (C) 2009 Texas Instruments | ||
| 8 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License as published by | ||
| 12 | * the Free Software Foundation; either version 2 of the License, or | ||
| 13 | * (at your option) any later version. | ||
| 14 | * | ||
| 15 | * This program is distributed in the hope that it will be useful, | ||
| 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 18 | * GNU General Public License for more details. | ||
| 19 | * | ||
| 20 | * You should have received a copy of the GNU General Public License | ||
| 21 | * along with this program; if not, write to the Free Software | ||
| 22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 23 | * | ||
| 24 | * NOTE: The interrupt vectors for the OMAP-1509, OMAP-1510, and OMAP-1610 | ||
| 25 | * are different. | ||
| 3 | */ | 26 | */ |
| 4 | 27 | ||
| 5 | #include <plat/irqs.h> | 28 | #ifndef __ASM_ARCH_OMAP15XX_IRQS_H |
| 29 | #define __ASM_ARCH_OMAP15XX_IRQS_H | ||
| 30 | |||
| 31 | /* | ||
| 32 | * IRQ numbers for interrupt handler 1 | ||
| 33 | * | ||
| 34 | * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below | ||
| 35 | * | ||
| 36 | */ | ||
| 37 | #define INT_CAMERA 1 | ||
| 38 | #define INT_FIQ 3 | ||
| 39 | #define INT_RTDX 6 | ||
| 40 | #define INT_DSP_MMU_ABORT 7 | ||
| 41 | #define INT_HOST 8 | ||
| 42 | #define INT_ABORT 9 | ||
| 43 | #define INT_BRIDGE_PRIV 13 | ||
| 44 | #define INT_GPIO_BANK1 14 | ||
| 45 | #define INT_UART3 15 | ||
| 46 | #define INT_TIMER3 16 | ||
| 47 | #define INT_DMA_CH0_6 19 | ||
| 48 | #define INT_DMA_CH1_7 20 | ||
| 49 | #define INT_DMA_CH2_8 21 | ||
| 50 | #define INT_DMA_CH3 22 | ||
| 51 | #define INT_DMA_CH4 23 | ||
| 52 | #define INT_DMA_CH5 24 | ||
| 53 | #define INT_TIMER1 26 | ||
| 54 | #define INT_WD_TIMER 27 | ||
| 55 | #define INT_BRIDGE_PUB 28 | ||
| 56 | #define INT_TIMER2 30 | ||
| 57 | #define INT_LCD_CTRL 31 | ||
| 58 | |||
| 59 | /* | ||
| 60 | * OMAP-1510 specific IRQ numbers for interrupt handler 1 | ||
| 61 | */ | ||
| 62 | #define INT_1510_IH2_IRQ 0 | ||
| 63 | #define INT_1510_RES2 2 | ||
| 64 | #define INT_1510_SPI_TX 4 | ||
| 65 | #define INT_1510_SPI_RX 5 | ||
| 66 | #define INT_1510_DSP_MAILBOX1 10 | ||
| 67 | #define INT_1510_DSP_MAILBOX2 11 | ||
| 68 | #define INT_1510_RES12 12 | ||
| 69 | #define INT_1510_LB_MMU 17 | ||
| 70 | #define INT_1510_RES18 18 | ||
| 71 | #define INT_1510_LOCAL_BUS 29 | ||
| 72 | |||
| 73 | /* | ||
| 74 | * OMAP-1610 specific IRQ numbers for interrupt handler 1 | ||
| 75 | */ | ||
| 76 | #define INT_1610_IH2_IRQ INT_1510_IH2_IRQ | ||
| 77 | #define INT_1610_IH2_FIQ 2 | ||
| 78 | #define INT_1610_McBSP2_TX 4 | ||
| 79 | #define INT_1610_McBSP2_RX 5 | ||
| 80 | #define INT_1610_DSP_MAILBOX1 10 | ||
| 81 | #define INT_1610_DSP_MAILBOX2 11 | ||
| 82 | #define INT_1610_LCD_LINE 12 | ||
| 83 | #define INT_1610_GPTIMER1 17 | ||
| 84 | #define INT_1610_GPTIMER2 18 | ||
| 85 | #define INT_1610_SSR_FIFO_0 29 | ||
| 86 | |||
| 87 | /* | ||
| 88 | * OMAP-7xx specific IRQ numbers for interrupt handler 1 | ||
| 89 | */ | ||
| 90 | #define INT_7XX_IH2_FIQ 0 | ||
| 91 | #define INT_7XX_IH2_IRQ 1 | ||
| 92 | #define INT_7XX_USB_NON_ISO 2 | ||
| 93 | #define INT_7XX_USB_ISO 3 | ||
| 94 | #define INT_7XX_ICR 4 | ||
| 95 | #define INT_7XX_EAC 5 | ||
| 96 | #define INT_7XX_GPIO_BANK1 6 | ||
| 97 | #define INT_7XX_GPIO_BANK2 7 | ||
| 98 | #define INT_7XX_GPIO_BANK3 8 | ||
| 99 | #define INT_7XX_McBSP2TX 10 | ||
| 100 | #define INT_7XX_McBSP2RX 11 | ||
| 101 | #define INT_7XX_McBSP2RX_OVF 12 | ||
| 102 | #define INT_7XX_LCD_LINE 14 | ||
| 103 | #define INT_7XX_GSM_PROTECT 15 | ||
| 104 | #define INT_7XX_TIMER3 16 | ||
| 105 | #define INT_7XX_GPIO_BANK5 17 | ||
| 106 | #define INT_7XX_GPIO_BANK6 18 | ||
| 107 | #define INT_7XX_SPGIO_WR 29 | ||
| 108 | |||
| 109 | /* | ||
| 110 | * IRQ numbers for interrupt handler 2 | ||
| 111 | * | ||
| 112 | * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below | ||
| 113 | */ | ||
| 114 | #define IH2_BASE 32 | ||
| 115 | |||
| 116 | #define INT_KEYBOARD (1 + IH2_BASE) | ||
| 117 | #define INT_uWireTX (2 + IH2_BASE) | ||
| 118 | #define INT_uWireRX (3 + IH2_BASE) | ||
| 119 | #define INT_I2C (4 + IH2_BASE) | ||
| 120 | #define INT_MPUIO (5 + IH2_BASE) | ||
| 121 | #define INT_USB_HHC_1 (6 + IH2_BASE) | ||
| 122 | #define INT_McBSP3TX (10 + IH2_BASE) | ||
| 123 | #define INT_McBSP3RX (11 + IH2_BASE) | ||
| 124 | #define INT_McBSP1TX (12 + IH2_BASE) | ||
| 125 | #define INT_McBSP1RX (13 + IH2_BASE) | ||
| 126 | #define INT_UART1 (14 + IH2_BASE) | ||
| 127 | #define INT_UART2 (15 + IH2_BASE) | ||
| 128 | #define INT_BT_MCSI1TX (16 + IH2_BASE) | ||
| 129 | #define INT_BT_MCSI1RX (17 + IH2_BASE) | ||
| 130 | #define INT_SOSSI_MATCH (19 + IH2_BASE) | ||
| 131 | #define INT_USB_W2FC (20 + IH2_BASE) | ||
| 132 | #define INT_1WIRE (21 + IH2_BASE) | ||
| 133 | #define INT_OS_TIMER (22 + IH2_BASE) | ||
| 134 | #define INT_MMC (23 + IH2_BASE) | ||
| 135 | #define INT_GAUGE_32K (24 + IH2_BASE) | ||
| 136 | #define INT_RTC_TIMER (25 + IH2_BASE) | ||
| 137 | #define INT_RTC_ALARM (26 + IH2_BASE) | ||
| 138 | #define INT_MEM_STICK (27 + IH2_BASE) | ||
| 139 | |||
| 140 | /* | ||
| 141 | * OMAP-1510 specific IRQ numbers for interrupt handler 2 | ||
| 142 | */ | ||
| 143 | #define INT_1510_DSP_MMU (28 + IH2_BASE) | ||
| 144 | #define INT_1510_COM_SPI_RO (31 + IH2_BASE) | ||
| 145 | |||
| 146 | /* | ||
| 147 | * OMAP-1610 specific IRQ numbers for interrupt handler 2 | ||
| 148 | */ | ||
| 149 | #define INT_1610_FAC (0 + IH2_BASE) | ||
| 150 | #define INT_1610_USB_HHC_2 (7 + IH2_BASE) | ||
| 151 | #define INT_1610_USB_OTG (8 + IH2_BASE) | ||
| 152 | #define INT_1610_SoSSI (9 + IH2_BASE) | ||
| 153 | #define INT_1610_SoSSI_MATCH (19 + IH2_BASE) | ||
| 154 | #define INT_1610_DSP_MMU (28 + IH2_BASE) | ||
| 155 | #define INT_1610_McBSP2RX_OF (31 + IH2_BASE) | ||
| 156 | #define INT_1610_STI (32 + IH2_BASE) | ||
| 157 | #define INT_1610_STI_WAKEUP (33 + IH2_BASE) | ||
| 158 | #define INT_1610_GPTIMER3 (34 + IH2_BASE) | ||
| 159 | #define INT_1610_GPTIMER4 (35 + IH2_BASE) | ||
| 160 | #define INT_1610_GPTIMER5 (36 + IH2_BASE) | ||
| 161 | #define INT_1610_GPTIMER6 (37 + IH2_BASE) | ||
| 162 | #define INT_1610_GPTIMER7 (38 + IH2_BASE) | ||
| 163 | #define INT_1610_GPTIMER8 (39 + IH2_BASE) | ||
| 164 | #define INT_1610_GPIO_BANK2 (40 + IH2_BASE) | ||
| 165 | #define INT_1610_GPIO_BANK3 (41 + IH2_BASE) | ||
| 166 | #define INT_1610_MMC2 (42 + IH2_BASE) | ||
| 167 | #define INT_1610_CF (43 + IH2_BASE) | ||
| 168 | #define INT_1610_WAKE_UP_REQ (46 + IH2_BASE) | ||
| 169 | #define INT_1610_GPIO_BANK4 (48 + IH2_BASE) | ||
| 170 | #define INT_1610_SPI (49 + IH2_BASE) | ||
| 171 | #define INT_1610_DMA_CH6 (53 + IH2_BASE) | ||
| 172 | #define INT_1610_DMA_CH7 (54 + IH2_BASE) | ||
| 173 | #define INT_1610_DMA_CH8 (55 + IH2_BASE) | ||
| 174 | #define INT_1610_DMA_CH9 (56 + IH2_BASE) | ||
| 175 | #define INT_1610_DMA_CH10 (57 + IH2_BASE) | ||
| 176 | #define INT_1610_DMA_CH11 (58 + IH2_BASE) | ||
| 177 | #define INT_1610_DMA_CH12 (59 + IH2_BASE) | ||
| 178 | #define INT_1610_DMA_CH13 (60 + IH2_BASE) | ||
| 179 | #define INT_1610_DMA_CH14 (61 + IH2_BASE) | ||
| 180 | #define INT_1610_DMA_CH15 (62 + IH2_BASE) | ||
| 181 | #define INT_1610_NAND (63 + IH2_BASE) | ||
| 182 | #define INT_1610_SHA1MD5 (91 + IH2_BASE) | ||
| 183 | |||
| 184 | /* | ||
| 185 | * OMAP-7xx specific IRQ numbers for interrupt handler 2 | ||
| 186 | */ | ||
| 187 | #define INT_7XX_HW_ERRORS (0 + IH2_BASE) | ||
| 188 | #define INT_7XX_NFIQ_PWR_FAIL (1 + IH2_BASE) | ||
| 189 | #define INT_7XX_CFCD (2 + IH2_BASE) | ||
| 190 | #define INT_7XX_CFIREQ (3 + IH2_BASE) | ||
| 191 | #define INT_7XX_I2C (4 + IH2_BASE) | ||
| 192 | #define INT_7XX_PCC (5 + IH2_BASE) | ||
| 193 | #define INT_7XX_MPU_EXT_NIRQ (6 + IH2_BASE) | ||
| 194 | #define INT_7XX_SPI_100K_1 (7 + IH2_BASE) | ||
| 195 | #define INT_7XX_SYREN_SPI (8 + IH2_BASE) | ||
| 196 | #define INT_7XX_VLYNQ (9 + IH2_BASE) | ||
| 197 | #define INT_7XX_GPIO_BANK4 (10 + IH2_BASE) | ||
| 198 | #define INT_7XX_McBSP1TX (11 + IH2_BASE) | ||
| 199 | #define INT_7XX_McBSP1RX (12 + IH2_BASE) | ||
| 200 | #define INT_7XX_McBSP1RX_OF (13 + IH2_BASE) | ||
| 201 | #define INT_7XX_UART_MODEM_IRDA_2 (14 + IH2_BASE) | ||
| 202 | #define INT_7XX_UART_MODEM_1 (15 + IH2_BASE) | ||
| 203 | #define INT_7XX_MCSI (16 + IH2_BASE) | ||
| 204 | #define INT_7XX_uWireTX (17 + IH2_BASE) | ||
| 205 | #define INT_7XX_uWireRX (18 + IH2_BASE) | ||
| 206 | #define INT_7XX_SMC_CD (19 + IH2_BASE) | ||
| 207 | #define INT_7XX_SMC_IREQ (20 + IH2_BASE) | ||
| 208 | #define INT_7XX_HDQ_1WIRE (21 + IH2_BASE) | ||
| 209 | #define INT_7XX_TIMER32K (22 + IH2_BASE) | ||
| 210 | #define INT_7XX_MMC_SDIO (23 + IH2_BASE) | ||
| 211 | #define INT_7XX_UPLD (24 + IH2_BASE) | ||
| 212 | #define INT_7XX_USB_HHC_1 (27 + IH2_BASE) | ||
| 213 | #define INT_7XX_USB_HHC_2 (28 + IH2_BASE) | ||
| 214 | #define INT_7XX_USB_GENI (29 + IH2_BASE) | ||
| 215 | #define INT_7XX_USB_OTG (30 + IH2_BASE) | ||
| 216 | #define INT_7XX_CAMERA_IF (31 + IH2_BASE) | ||
| 217 | #define INT_7XX_RNG (32 + IH2_BASE) | ||
| 218 | #define INT_7XX_DUAL_MODE_TIMER (33 + IH2_BASE) | ||
| 219 | #define INT_7XX_DBB_RF_EN (34 + IH2_BASE) | ||
| 220 | #define INT_7XX_MPUIO_KEYPAD (35 + IH2_BASE) | ||
| 221 | #define INT_7XX_SHA1_MD5 (36 + IH2_BASE) | ||
| 222 | #define INT_7XX_SPI_100K_2 (37 + IH2_BASE) | ||
| 223 | #define INT_7XX_RNG_IDLE (38 + IH2_BASE) | ||
| 224 | #define INT_7XX_MPUIO (39 + IH2_BASE) | ||
| 225 | #define INT_7XX_LLPC_LCD_CTRL_CAN_BE_OFF (40 + IH2_BASE) | ||
| 226 | #define INT_7XX_LLPC_OE_FALLING (41 + IH2_BASE) | ||
| 227 | #define INT_7XX_LLPC_OE_RISING (42 + IH2_BASE) | ||
| 228 | #define INT_7XX_LLPC_VSYNC (43 + IH2_BASE) | ||
| 229 | #define INT_7XX_WAKE_UP_REQ (46 + IH2_BASE) | ||
| 230 | #define INT_7XX_DMA_CH6 (53 + IH2_BASE) | ||
| 231 | #define INT_7XX_DMA_CH7 (54 + IH2_BASE) | ||
| 232 | #define INT_7XX_DMA_CH8 (55 + IH2_BASE) | ||
| 233 | #define INT_7XX_DMA_CH9 (56 + IH2_BASE) | ||
| 234 | #define INT_7XX_DMA_CH10 (57 + IH2_BASE) | ||
| 235 | #define INT_7XX_DMA_CH11 (58 + IH2_BASE) | ||
| 236 | #define INT_7XX_DMA_CH12 (59 + IH2_BASE) | ||
| 237 | #define INT_7XX_DMA_CH13 (60 + IH2_BASE) | ||
| 238 | #define INT_7XX_DMA_CH14 (61 + IH2_BASE) | ||
| 239 | #define INT_7XX_DMA_CH15 (62 + IH2_BASE) | ||
| 240 | #define INT_7XX_NAND (63 + IH2_BASE) | ||
| 241 | |||
| 242 | /* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730/850) and | ||
| 243 | * 16 MPUIO lines */ | ||
| 244 | #define OMAP_MAX_GPIO_LINES 192 | ||
| 245 | #define IH_GPIO_BASE (128 + IH2_BASE) | ||
| 246 | #define IH_MPUIO_BASE (OMAP_MAX_GPIO_LINES + IH_GPIO_BASE) | ||
| 247 | #define OMAP_IRQ_END (IH_MPUIO_BASE + 16) | ||
| 248 | |||
| 249 | /* External FPGA handles interrupts on Innovator boards */ | ||
| 250 | #define OMAP_FPGA_IRQ_BASE (OMAP_IRQ_END) | ||
| 251 | #ifdef CONFIG_MACH_OMAP_INNOVATOR | ||
| 252 | #define OMAP_FPGA_NR_IRQS 24 | ||
| 253 | #else | ||
| 254 | #define OMAP_FPGA_NR_IRQS 0 | ||
| 255 | #endif | ||
| 256 | #define OMAP_FPGA_IRQ_END (OMAP_FPGA_IRQ_BASE + OMAP_FPGA_NR_IRQS) | ||
| 257 | |||
| 258 | #define NR_IRQS OMAP_FPGA_IRQ_END | ||
| 259 | |||
| 260 | #define OMAP_IRQ_BIT(irq) (1 << ((irq) % 32)) | ||
| 261 | |||
| 262 | #include <mach/hardware.h> | ||
| 263 | |||
| 264 | #ifdef CONFIG_FIQ | ||
| 265 | #define FIQ_START 1024 | ||
| 266 | #endif | ||
| 267 | |||
| 268 | #endif | ||
diff --git a/arch/arm/plat-omap/include/plat/omap1510.h b/arch/arm/mach-omap1/include/mach/omap1510.h index d24004668138..8fe05d6137c0 100644 --- a/arch/arm/plat-omap/include/plat/omap1510.h +++ b/arch/arm/mach-omap1/include/mach/omap1510.h | |||
| @@ -1,5 +1,4 @@ | |||
| 1 | /* arch/arm/plat-omap/include/mach/omap1510.h | 1 | /* |
| 2 | * | ||
| 3 | * Hardware definitions for TI OMAP1510 processor. | 2 | * Hardware definitions for TI OMAP1510 processor. |
| 4 | * | 3 | * |
| 5 | * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com> | 4 | * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com> |
diff --git a/arch/arm/plat-omap/include/plat/omap16xx.h b/arch/arm/mach-omap1/include/mach/omap16xx.h index e69e1d857b45..cd1c724869c7 100644 --- a/arch/arm/plat-omap/include/plat/omap16xx.h +++ b/arch/arm/mach-omap1/include/mach/omap16xx.h | |||
| @@ -1,5 +1,4 @@ | |||
| 1 | /* arch/arm/plat-omap/include/mach/omap16xx.h | 1 | /* |
| 2 | * | ||
| 3 | * Hardware definitions for TI OMAP1610/5912/1710 processors. | 2 | * Hardware definitions for TI OMAP1610/5912/1710 processors. |
| 4 | * | 3 | * |
| 5 | * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com> | 4 | * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com> |
diff --git a/arch/arm/plat-omap/include/plat/omap7xx.h b/arch/arm/mach-omap1/include/mach/omap7xx.h index 48e4757e1e30..63da994bc609 100644 --- a/arch/arm/plat-omap/include/plat/omap7xx.h +++ b/arch/arm/mach-omap1/include/mach/omap7xx.h | |||
| @@ -1,5 +1,4 @@ | |||
| 1 | /* arch/arm/plat-omap/include/mach/omap7xx.h | 1 | /* |
| 2 | * | ||
| 3 | * Hardware definitions for TI OMAP7XX processor. | 2 | * Hardware definitions for TI OMAP7XX processor. |
| 4 | * | 3 | * |
| 5 | * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com> | 4 | * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com> |
diff --git a/arch/arm/mach-omap1/leds-h2p2-debug.c b/arch/arm/mach-omap1/leds-h2p2-debug.c index f6b14a14a957..7f4bba9fa02e 100644 --- a/arch/arm/mach-omap1/leds-h2p2-debug.c +++ b/arch/arm/mach-omap1/leds-h2p2-debug.c | |||
| @@ -14,6 +14,7 @@ | |||
| 14 | #include <linux/kernel_stat.h> | 14 | #include <linux/kernel_stat.h> |
| 15 | #include <linux/sched.h> | 15 | #include <linux/sched.h> |
| 16 | #include <linux/io.h> | 16 | #include <linux/io.h> |
| 17 | #include <linux/platform_data/gpio-omap.h> | ||
| 17 | 18 | ||
| 18 | #include <mach/hardware.h> | 19 | #include <mach/hardware.h> |
| 19 | #include <asm/leds.h> | 20 | #include <asm/leds.h> |
diff --git a/arch/arm/mach-omap1/leds.c b/arch/arm/mach-omap1/leds.c index ae6dd93b8ddc..7b1a3833165d 100644 --- a/arch/arm/mach-omap1/leds.c +++ b/arch/arm/mach-omap1/leds.c | |||
| @@ -6,6 +6,7 @@ | |||
| 6 | #include <linux/gpio.h> | 6 | #include <linux/gpio.h> |
| 7 | #include <linux/kernel.h> | 7 | #include <linux/kernel.h> |
| 8 | #include <linux/init.h> | 8 | #include <linux/init.h> |
| 9 | #include <linux/platform_data/gpio-omap.h> | ||
| 9 | 10 | ||
| 10 | #include <asm/leds.h> | 11 | #include <asm/leds.h> |
| 11 | #include <asm/mach-types.h> | 12 | #include <asm/mach-types.h> |
diff --git a/arch/arm/mach-omap1/serial.c b/arch/arm/mach-omap1/serial.c index 6809c9e56c93..0d1709b1a6fe 100644 --- a/arch/arm/mach-omap1/serial.c +++ b/arch/arm/mach-omap1/serial.c | |||
| @@ -22,7 +22,6 @@ | |||
| 22 | 22 | ||
| 23 | #include <asm/mach-types.h> | 23 | #include <asm/mach-types.h> |
| 24 | 24 | ||
| 25 | #include <plat/board.h> | ||
| 26 | #include <plat/mux.h> | 25 | #include <plat/mux.h> |
| 27 | #include <plat/fpga.h> | 26 | #include <plat/fpga.h> |
| 28 | 27 | ||
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index fcd4e85c4ddc..edc30b8b77ed 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig | |||
| @@ -18,12 +18,16 @@ config ARCH_OMAP2PLUS_TYPICAL | |||
| 18 | select TWL4030_CORE if ARCH_OMAP3 || ARCH_OMAP4 | 18 | select TWL4030_CORE if ARCH_OMAP3 || ARCH_OMAP4 |
| 19 | select TWL4030_POWER if ARCH_OMAP3 || ARCH_OMAP4 | 19 | select TWL4030_POWER if ARCH_OMAP3 || ARCH_OMAP4 |
| 20 | select HIGHMEM | 20 | select HIGHMEM |
| 21 | select PINCTRL | ||
| 21 | help | 22 | help |
| 22 | Compile a kernel suitable for booting most boards | 23 | Compile a kernel suitable for booting most boards |
| 23 | 24 | ||
| 24 | config SOC_HAS_OMAP2_SDRC | 25 | config SOC_HAS_OMAP2_SDRC |
| 25 | bool "OMAP2 SDRAM Controller support" | 26 | bool "OMAP2 SDRAM Controller support" |
| 26 | 27 | ||
| 28 | config SOC_HAS_REALTIME_COUNTER | ||
| 29 | bool "Real time free running counter" | ||
| 30 | |||
| 27 | config ARCH_OMAP2 | 31 | config ARCH_OMAP2 |
| 28 | bool "TI OMAP2" | 32 | bool "TI OMAP2" |
| 29 | depends on ARCH_OMAP2PLUS | 33 | depends on ARCH_OMAP2PLUS |
| @@ -70,6 +74,8 @@ config SOC_OMAP5 | |||
| 70 | select ARM_GIC | 74 | select ARM_GIC |
| 71 | select HAVE_SMP | 75 | select HAVE_SMP |
| 72 | select ARM_CPU_SUSPEND if PM | 76 | select ARM_CPU_SUSPEND if PM |
| 77 | select SOC_HAS_REALTIME_COUNTER | ||
| 78 | select ARM_ARCH_TIMER | ||
| 73 | 79 | ||
| 74 | comment "OMAP Core Type" | 80 | comment "OMAP Core Type" |
| 75 | depends on ARCH_OMAP2 | 81 | depends on ARCH_OMAP2 |
| @@ -232,10 +238,11 @@ config MACH_OMAP3_PANDORA | |||
| 232 | select OMAP_PACKAGE_CBB | 238 | select OMAP_PACKAGE_CBB |
| 233 | select REGULATOR_FIXED_VOLTAGE if REGULATOR | 239 | select REGULATOR_FIXED_VOLTAGE if REGULATOR |
| 234 | 240 | ||
| 235 | config MACH_OMAP3_TOUCHBOOK | 241 | config MACH_TOUCHBOOK |
| 236 | bool "OMAP3 Touch Book" | 242 | bool "OMAP3 Touch Book" |
| 237 | depends on ARCH_OMAP3 | 243 | depends on ARCH_OMAP3 |
| 238 | default y | 244 | default y |
| 245 | select OMAP_PACKAGE_CBB | ||
| 239 | 246 | ||
| 240 | config MACH_OMAP_3430SDP | 247 | config MACH_OMAP_3430SDP |
| 241 | bool "OMAP 3430 SDP board" | 248 | bool "OMAP 3430 SDP board" |
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index f6a24b3f9c4f..34c2c7f59f0a 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile | |||
| @@ -255,7 +255,7 @@ obj-$(CONFIG_MACH_OMAP_3630SDP) += board-zoom-display.o | |||
| 255 | obj-$(CONFIG_MACH_CM_T35) += board-cm-t35.o | 255 | obj-$(CONFIG_MACH_CM_T35) += board-cm-t35.o |
| 256 | obj-$(CONFIG_MACH_CM_T3517) += board-cm-t3517.o | 256 | obj-$(CONFIG_MACH_CM_T3517) += board-cm-t3517.o |
| 257 | obj-$(CONFIG_MACH_IGEP0020) += board-igep0020.o | 257 | obj-$(CONFIG_MACH_IGEP0020) += board-igep0020.o |
| 258 | obj-$(CONFIG_MACH_OMAP3_TOUCHBOOK) += board-omap3touchbook.o | 258 | obj-$(CONFIG_MACH_TOUCHBOOK) += board-omap3touchbook.o |
| 259 | obj-$(CONFIG_MACH_OMAP_4430SDP) += board-4430sdp.o | 259 | obj-$(CONFIG_MACH_OMAP_4430SDP) += board-4430sdp.o |
| 260 | obj-$(CONFIG_MACH_OMAP4_PANDA) += board-omap4panda.o | 260 | obj-$(CONFIG_MACH_OMAP4_PANDA) += board-omap4panda.o |
| 261 | 261 | ||
diff --git a/arch/arm/mach-omap2/Makefile.boot b/arch/arm/mach-omap2/Makefile.boot index b03e562acc60..be0fe9226d67 100644 --- a/arch/arm/mach-omap2/Makefile.boot +++ b/arch/arm/mach-omap2/Makefile.boot | |||
| @@ -1,3 +1,9 @@ | |||
| 1 | zreladdr-y += 0x80008000 | 1 | zreladdr-y += 0x80008000 |
| 2 | params_phys-y := 0x80000100 | 2 | params_phys-y := 0x80000100 |
| 3 | initrd_phys-y := 0x80800000 | 3 | initrd_phys-y := 0x80800000 |
| 4 | |||
| 5 | dtb-$(CONFIG_SOC_OMAP2420) += omap2420-h4.dtb | ||
| 6 | dtb-$(CONFIG_ARCH_OMAP3) += omap3-beagle-xm.dtb omap3-evm.dtb omap3-tobi.dtb | ||
| 7 | dtb-$(CONFIG_ARCH_OMAP4) += omap4-panda.dtb omap4-pandaES.dtb | ||
| 8 | dtb-$(CONFIG_ARCH_OMAP4) += omap4-var_som.dtb omap4-sdp.dtb | ||
| 9 | dtb-$(CONFIG_SOC_OMAP5) += omap5-evm.dtb | ||
diff --git a/arch/arm/plat-omap/include/plat/am33xx.h b/arch/arm/mach-omap2/am33xx.h index 06c19bb7bca6..06c19bb7bca6 100644 --- a/arch/arm/plat-omap/include/plat/am33xx.h +++ b/arch/arm/mach-omap2/am33xx.h | |||
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c index 9511584fdc4f..0900eac57d56 100644 --- a/arch/arm/mach-omap2/board-2430sdp.c +++ b/arch/arm/mach-omap2/board-2430sdp.c | |||
| @@ -33,7 +33,6 @@ | |||
| 33 | #include <asm/mach/arch.h> | 33 | #include <asm/mach/arch.h> |
| 34 | #include <asm/mach/map.h> | 34 | #include <asm/mach/map.h> |
| 35 | 35 | ||
| 36 | #include <plat/board.h> | ||
| 37 | #include "common.h" | 36 | #include "common.h" |
| 38 | #include <plat/gpmc.h> | 37 | #include <plat/gpmc.h> |
| 39 | #include <plat/usb.h> | 38 | #include <plat/usb.h> |
| @@ -212,9 +211,6 @@ static struct regulator_init_data sdp2430_vmmc1 = { | |||
| 212 | }; | 211 | }; |
| 213 | 212 | ||
| 214 | static struct twl4030_gpio_platform_data sdp2430_gpio_data = { | 213 | static struct twl4030_gpio_platform_data sdp2430_gpio_data = { |
| 215 | .gpio_base = OMAP_MAX_GPIO_LINES, | ||
| 216 | .irq_base = TWL4030_GPIO_IRQ_BASE, | ||
| 217 | .irq_end = TWL4030_GPIO_IRQ_END, | ||
| 218 | }; | 214 | }; |
| 219 | 215 | ||
| 220 | static struct twl4030_platform_data sdp2430_twldata = { | 216 | static struct twl4030_platform_data sdp2430_twldata = { |
| @@ -235,7 +231,7 @@ static int __init omap2430_i2c_init(void) | |||
| 235 | sdp2430_i2c1_boardinfo[0].irq = gpio_to_irq(78); | 231 | sdp2430_i2c1_boardinfo[0].irq = gpio_to_irq(78); |
| 236 | omap_register_i2c_bus(1, 100, sdp2430_i2c1_boardinfo, | 232 | omap_register_i2c_bus(1, 100, sdp2430_i2c1_boardinfo, |
| 237 | ARRAY_SIZE(sdp2430_i2c1_boardinfo)); | 233 | ARRAY_SIZE(sdp2430_i2c1_boardinfo)); |
| 238 | omap_pmic_init(2, 100, "twl4030", INT_24XX_SYS_NIRQ, | 234 | omap_pmic_init(2, 100, "twl4030", 7 + OMAP_INTC_START, |
| 239 | &sdp2430_twldata); | 235 | &sdp2430_twldata); |
| 240 | return 0; | 236 | return 0; |
| 241 | } | 237 | } |
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c index a98c688058a9..5453173ff57b 100644 --- a/arch/arm/mach-omap2/board-3430sdp.c +++ b/arch/arm/mach-omap2/board-3430sdp.c | |||
| @@ -25,13 +25,11 @@ | |||
| 25 | #include <linux/gpio.h> | 25 | #include <linux/gpio.h> |
| 26 | #include <linux/mmc/host.h> | 26 | #include <linux/mmc/host.h> |
| 27 | 27 | ||
| 28 | #include <mach/hardware.h> | ||
| 29 | #include <asm/mach-types.h> | 28 | #include <asm/mach-types.h> |
| 30 | #include <asm/mach/arch.h> | 29 | #include <asm/mach/arch.h> |
| 31 | #include <asm/mach/map.h> | 30 | #include <asm/mach/map.h> |
| 32 | 31 | ||
| 33 | #include <plat/mcspi.h> | 32 | #include <plat/mcspi.h> |
| 34 | #include <plat/board.h> | ||
| 35 | #include <plat/usb.h> | 33 | #include <plat/usb.h> |
| 36 | #include "common.h" | 34 | #include "common.h" |
| 37 | #include <plat/dma.h> | 35 | #include <plat/dma.h> |
| @@ -191,9 +189,6 @@ static struct omap_dss_board_info sdp3430_dss_data = { | |||
| 191 | .default_device = &sdp3430_lcd_device, | 189 | .default_device = &sdp3430_lcd_device, |
| 192 | }; | 190 | }; |
| 193 | 191 | ||
| 194 | static struct omap_board_config_kernel sdp3430_config[] __initdata = { | ||
| 195 | }; | ||
| 196 | |||
| 197 | static struct omap2_hsmmc_info mmc[] = { | 192 | static struct omap2_hsmmc_info mmc[] = { |
| 198 | { | 193 | { |
| 199 | .mmc = 1, | 194 | .mmc = 1, |
| @@ -233,9 +228,6 @@ static int sdp3430_twl_gpio_setup(struct device *dev, | |||
| 233 | } | 228 | } |
| 234 | 229 | ||
| 235 | static struct twl4030_gpio_platform_data sdp3430_gpio_data = { | 230 | static struct twl4030_gpio_platform_data sdp3430_gpio_data = { |
| 236 | .gpio_base = OMAP_MAX_GPIO_LINES, | ||
| 237 | .irq_base = TWL4030_GPIO_IRQ_BASE, | ||
| 238 | .irq_end = TWL4030_GPIO_IRQ_END, | ||
| 239 | .pulldowns = BIT(2) | BIT(6) | BIT(8) | BIT(13) | 231 | .pulldowns = BIT(2) | BIT(6) | BIT(8) | BIT(13) |
| 240 | | BIT(16) | BIT(17), | 232 | | BIT(16) | BIT(17), |
| 241 | .setup = sdp3430_twl_gpio_setup, | 233 | .setup = sdp3430_twl_gpio_setup, |
| @@ -576,8 +568,6 @@ static void __init omap_3430sdp_init(void) | |||
| 576 | int gpio_pendown; | 568 | int gpio_pendown; |
| 577 | 569 | ||
| 578 | omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); | 570 | omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); |
| 579 | omap_board_config = sdp3430_config; | ||
| 580 | omap_board_config_size = ARRAY_SIZE(sdp3430_config); | ||
| 581 | omap_hsmmc_init(mmc); | 571 | omap_hsmmc_init(mmc); |
| 582 | omap3430_i2c_init(); | 572 | omap3430_i2c_init(); |
| 583 | omap_display_init(&sdp3430_dss_data); | 573 | omap_display_init(&sdp3430_dss_data); |
diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c index 2dc9ba523c7a..8518b1345988 100644 --- a/arch/arm/mach-omap2/board-3630sdp.c +++ b/arch/arm/mach-omap2/board-3630sdp.c | |||
| @@ -17,7 +17,6 @@ | |||
| 17 | #include <asm/mach/arch.h> | 17 | #include <asm/mach/arch.h> |
| 18 | 18 | ||
| 19 | #include "common.h" | 19 | #include "common.h" |
| 20 | #include <plat/board.h> | ||
| 21 | #include <plat/gpmc-smc91x.h> | 20 | #include <plat/gpmc-smc91x.h> |
| 22 | #include <plat/usb.h> | 21 | #include <plat/usb.h> |
| 23 | 22 | ||
| @@ -67,9 +66,6 @@ static const struct usbhs_omap_board_data usbhs_bdata __initconst = { | |||
| 67 | .reset_gpio_port[2] = -EINVAL | 66 | .reset_gpio_port[2] = -EINVAL |
| 68 | }; | 67 | }; |
| 69 | 68 | ||
| 70 | static struct omap_board_config_kernel sdp_config[] __initdata = { | ||
| 71 | }; | ||
| 72 | |||
| 73 | #ifdef CONFIG_OMAP_MUX | 69 | #ifdef CONFIG_OMAP_MUX |
| 74 | static struct omap_board_mux board_mux[] __initdata = { | 70 | static struct omap_board_mux board_mux[] __initdata = { |
| 75 | { .reg_offset = OMAP_MUX_TERMINATOR }, | 71 | { .reg_offset = OMAP_MUX_TERMINATOR }, |
| @@ -197,8 +193,6 @@ static struct flash_partitions sdp_flash_partitions[] = { | |||
| 197 | static void __init omap_sdp_init(void) | 193 | static void __init omap_sdp_init(void) |
| 198 | { | 194 | { |
| 199 | omap3_mux_init(board_mux, OMAP_PACKAGE_CBP); | 195 | omap3_mux_init(board_mux, OMAP_PACKAGE_CBP); |
| 200 | omap_board_config = sdp_config; | ||
| 201 | omap_board_config_size = ARRAY_SIZE(sdp_config); | ||
| 202 | zoom_peripherals_init(); | 196 | zoom_peripherals_init(); |
| 203 | omap_sdrc_init(h8mbx00u0mer0em_sdrc_params, | 197 | omap_sdrc_init(h8mbx00u0mer0em_sdrc_params, |
| 204 | h8mbx00u0mer0em_sdrc_params); | 198 | h8mbx00u0mer0em_sdrc_params); |
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c index ad8a7d94afcd..db43e22526c0 100644 --- a/arch/arm/mach-omap2/board-4430sdp.c +++ b/arch/arm/mach-omap2/board-4430sdp.c | |||
| @@ -28,13 +28,11 @@ | |||
| 28 | #include <linux/leds_pwm.h> | 28 | #include <linux/leds_pwm.h> |
| 29 | #include <linux/platform_data/omap4-keypad.h> | 29 | #include <linux/platform_data/omap4-keypad.h> |
| 30 | 30 | ||
| 31 | #include <mach/hardware.h> | ||
| 32 | #include <asm/hardware/gic.h> | 31 | #include <asm/hardware/gic.h> |
| 33 | #include <asm/mach-types.h> | 32 | #include <asm/mach-types.h> |
| 34 | #include <asm/mach/arch.h> | 33 | #include <asm/mach/arch.h> |
| 35 | #include <asm/mach/map.h> | 34 | #include <asm/mach/map.h> |
| 36 | 35 | ||
| 37 | #include <plat/board.h> | ||
| 38 | #include "common.h" | 36 | #include "common.h" |
| 39 | #include <plat/usb.h> | 37 | #include <plat/usb.h> |
| 40 | #include <plat/mmc.h> | 38 | #include <plat/mmc.h> |
| @@ -45,6 +43,7 @@ | |||
| 45 | #include <linux/wl12xx.h> | 43 | #include <linux/wl12xx.h> |
| 46 | #include <linux/platform_data/omap-abe-twl6040.h> | 44 | #include <linux/platform_data/omap-abe-twl6040.h> |
| 47 | 45 | ||
| 46 | #include "soc.h" | ||
| 48 | #include "mux.h" | 47 | #include "mux.h" |
| 49 | #include "hsmmc.h" | 48 | #include "hsmmc.h" |
| 50 | #include "control.h" | 49 | #include "control.h" |
| @@ -544,7 +543,6 @@ static struct twl6040_platform_data twl6040_data = { | |||
| 544 | .codec = &twl6040_codec, | 543 | .codec = &twl6040_codec, |
| 545 | .vibra = &twl6040_vibra, | 544 | .vibra = &twl6040_vibra, |
| 546 | .audpwron_gpio = 127, | 545 | .audpwron_gpio = 127, |
| 547 | .irq_base = TWL6040_CODEC_IRQ_BASE, | ||
| 548 | }; | 546 | }; |
| 549 | 547 | ||
| 550 | static struct twl4030_platform_data sdp4430_twldata = { | 548 | static struct twl4030_platform_data sdp4430_twldata = { |
| @@ -581,7 +579,7 @@ static int __init omap4_i2c_init(void) | |||
| 581 | TWL_COMMON_REGULATOR_V1V8 | | 579 | TWL_COMMON_REGULATOR_V1V8 | |
| 582 | TWL_COMMON_REGULATOR_V2V1); | 580 | TWL_COMMON_REGULATOR_V2V1); |
| 583 | omap4_pmic_init("twl6030", &sdp4430_twldata, | 581 | omap4_pmic_init("twl6030", &sdp4430_twldata, |
| 584 | &twl6040_data, OMAP44XX_IRQ_SYS_2N); | 582 | &twl6040_data, 119 + OMAP44XX_IRQ_GIC_START); |
| 585 | omap_register_i2c_bus(2, 400, NULL, 0); | 583 | omap_register_i2c_bus(2, 400, NULL, 0); |
| 586 | omap_register_i2c_bus(3, 400, sdp4430_i2c_3_boardinfo, | 584 | omap_register_i2c_bus(3, 400, sdp4430_i2c_3_boardinfo, |
| 587 | ARRAY_SIZE(sdp4430_i2c_3_boardinfo)); | 585 | ARRAY_SIZE(sdp4430_i2c_3_boardinfo)); |
diff --git a/arch/arm/mach-omap2/board-am3517crane.c b/arch/arm/mach-omap2/board-am3517crane.c index 92432c28673d..318feadb1d6e 100644 --- a/arch/arm/mach-omap2/board-am3517crane.c +++ b/arch/arm/mach-omap2/board-am3517crane.c | |||
| @@ -21,12 +21,10 @@ | |||
| 21 | #include <linux/init.h> | 21 | #include <linux/init.h> |
| 22 | #include <linux/gpio.h> | 22 | #include <linux/gpio.h> |
| 23 | 23 | ||
| 24 | #include <mach/hardware.h> | ||
| 25 | #include <asm/mach-types.h> | 24 | #include <asm/mach-types.h> |
| 26 | #include <asm/mach/arch.h> | 25 | #include <asm/mach/arch.h> |
| 27 | #include <asm/mach/map.h> | 26 | #include <asm/mach/map.h> |
| 28 | 27 | ||
| 29 | #include <plat/board.h> | ||
| 30 | #include "common.h" | 28 | #include "common.h" |
| 31 | #include <plat/usb.h> | 29 | #include <plat/usb.h> |
| 32 | 30 | ||
| @@ -37,11 +35,6 @@ | |||
| 37 | #define GPIO_USB_POWER 35 | 35 | #define GPIO_USB_POWER 35 |
| 38 | #define GPIO_USB_NRESET 38 | 36 | #define GPIO_USB_NRESET 38 |
| 39 | 37 | ||
| 40 | |||
| 41 | /* Board initialization */ | ||
| 42 | static struct omap_board_config_kernel am3517_crane_config[] __initdata = { | ||
| 43 | }; | ||
| 44 | |||
| 45 | #ifdef CONFIG_OMAP_MUX | 38 | #ifdef CONFIG_OMAP_MUX |
| 46 | static struct omap_board_mux board_mux[] __initdata = { | 39 | static struct omap_board_mux board_mux[] __initdata = { |
| 47 | { .reg_offset = OMAP_MUX_TERMINATOR }, | 40 | { .reg_offset = OMAP_MUX_TERMINATOR }, |
| @@ -67,9 +60,6 @@ static void __init am3517_crane_init(void) | |||
| 67 | omap_serial_init(); | 60 | omap_serial_init(); |
| 68 | omap_sdrc_init(NULL, NULL); | 61 | omap_sdrc_init(NULL, NULL); |
| 69 | 62 | ||
| 70 | omap_board_config = am3517_crane_config; | ||
| 71 | omap_board_config_size = ARRAY_SIZE(am3517_crane_config); | ||
| 72 | |||
| 73 | /* Configure GPIO for EHCI port */ | 63 | /* Configure GPIO for EHCI port */ |
| 74 | if (omap_mux_init_gpio(GPIO_USB_NRESET, OMAP_PIN_OUTPUT)) { | 64 | if (omap_mux_init_gpio(GPIO_USB_NRESET, OMAP_PIN_OUTPUT)) { |
| 75 | pr_err("Can not configure mux for GPIO_USB_NRESET %d\n", | 65 | pr_err("Can not configure mux for GPIO_USB_NRESET %d\n", |
diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c index 18f601096ce1..403d048a00ee 100644 --- a/arch/arm/mach-omap2/board-am3517evm.c +++ b/arch/arm/mach-omap2/board-am3517evm.c | |||
| @@ -25,14 +25,13 @@ | |||
| 25 | #include <linux/can/platform/ti_hecc.h> | 25 | #include <linux/can/platform/ti_hecc.h> |
| 26 | #include <linux/davinci_emac.h> | 26 | #include <linux/davinci_emac.h> |
| 27 | #include <linux/mmc/host.h> | 27 | #include <linux/mmc/host.h> |
| 28 | #include <linux/platform_data/gpio-omap.h> | ||
| 28 | 29 | ||
| 29 | #include <mach/hardware.h> | ||
| 30 | #include <mach/am35xx.h> | 30 | #include <mach/am35xx.h> |
| 31 | #include <asm/mach-types.h> | 31 | #include <asm/mach-types.h> |
| 32 | #include <asm/mach/arch.h> | 32 | #include <asm/mach/arch.h> |
| 33 | #include <asm/mach/map.h> | 33 | #include <asm/mach/map.h> |
| 34 | 34 | ||
| 35 | #include <plat/board.h> | ||
| 36 | #include "common.h" | 35 | #include "common.h" |
| 37 | #include <plat/usb.h> | 36 | #include <plat/usb.h> |
| 38 | #include <video/omapdss.h> | 37 | #include <video/omapdss.h> |
| @@ -296,8 +295,7 @@ static struct resource am3517_hecc_resources[] = { | |||
| 296 | .flags = IORESOURCE_MEM, | 295 | .flags = IORESOURCE_MEM, |
| 297 | }, | 296 | }, |
| 298 | { | 297 | { |
| 299 | .start = INT_35XX_HECC0_IRQ, | 298 | .start = 24 + OMAP_INTC_START, |
| 300 | .end = INT_35XX_HECC0_IRQ, | ||
| 301 | .flags = IORESOURCE_IRQ, | 299 | .flags = IORESOURCE_IRQ, |
| 302 | }, | 300 | }, |
| 303 | }; | 301 | }; |
| @@ -324,9 +322,6 @@ static void am3517_evm_hecc_init(struct ti_hecc_platform_data *pdata) | |||
| 324 | platform_device_register(&am3517_hecc_device); | 322 | platform_device_register(&am3517_hecc_device); |
| 325 | } | 323 | } |
| 326 | 324 | ||
| 327 | static struct omap_board_config_kernel am3517_evm_config[] __initdata = { | ||
| 328 | }; | ||
| 329 | |||
| 330 | static struct omap2_hsmmc_info mmc[] = { | 325 | static struct omap2_hsmmc_info mmc[] = { |
| 331 | { | 326 | { |
| 332 | .mmc = 1, | 327 | .mmc = 1, |
| @@ -346,8 +341,6 @@ static struct omap2_hsmmc_info mmc[] = { | |||
| 346 | 341 | ||
| 347 | static void __init am3517_evm_init(void) | 342 | static void __init am3517_evm_init(void) |
| 348 | { | 343 | { |
| 349 | omap_board_config = am3517_evm_config; | ||
| 350 | omap_board_config_size = ARRAY_SIZE(am3517_evm_config); | ||
| 351 | omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); | 344 | omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); |
| 352 | 345 | ||
| 353 | am3517_evm_i2c_init(); | 346 | am3517_evm_i2c_init(); |
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c index e5fa46bfde2f..3e2d76f05af4 100644 --- a/arch/arm/mach-omap2/board-apollon.c +++ b/arch/arm/mach-omap2/board-apollon.c | |||
| @@ -29,13 +29,11 @@ | |||
| 29 | #include <linux/smc91x.h> | 29 | #include <linux/smc91x.h> |
| 30 | #include <linux/gpio.h> | 30 | #include <linux/gpio.h> |
| 31 | 31 | ||
| 32 | #include <mach/hardware.h> | ||
| 33 | #include <asm/mach-types.h> | 32 | #include <asm/mach-types.h> |
| 34 | #include <asm/mach/arch.h> | 33 | #include <asm/mach/arch.h> |
| 35 | #include <asm/mach/flash.h> | 34 | #include <asm/mach/flash.h> |
| 36 | 35 | ||
| 37 | #include <plat/led.h> | 36 | #include <plat/led.h> |
| 38 | #include <plat/board.h> | ||
| 39 | #include "common.h" | 37 | #include "common.h" |
| 40 | #include <plat/gpmc.h> | 38 | #include <plat/gpmc.h> |
| 41 | 39 | ||
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c index 97d719047af3..34cb90471d96 100644 --- a/arch/arm/mach-omap2/board-cm-t35.c +++ b/arch/arm/mach-omap2/board-cm-t35.c | |||
| @@ -23,6 +23,7 @@ | |||
| 23 | #include <linux/input/matrix_keypad.h> | 23 | #include <linux/input/matrix_keypad.h> |
| 24 | #include <linux/delay.h> | 24 | #include <linux/delay.h> |
| 25 | #include <linux/gpio.h> | 25 | #include <linux/gpio.h> |
| 26 | #include <linux/platform_data/gpio-omap.h> | ||
| 26 | 27 | ||
| 27 | #include <linux/i2c/at24.h> | 28 | #include <linux/i2c/at24.h> |
| 28 | #include <linux/i2c/twl.h> | 29 | #include <linux/i2c/twl.h> |
| @@ -37,7 +38,6 @@ | |||
| 37 | #include <asm/mach/arch.h> | 38 | #include <asm/mach/arch.h> |
| 38 | #include <asm/mach/map.h> | 39 | #include <asm/mach/map.h> |
| 39 | 40 | ||
| 40 | #include <plat/board.h> | ||
| 41 | #include "common.h" | 41 | #include "common.h" |
| 42 | #include <plat/nand.h> | 42 | #include <plat/nand.h> |
| 43 | #include <plat/gpmc.h> | 43 | #include <plat/gpmc.h> |
| @@ -470,9 +470,6 @@ static int cm_t35_twl_gpio_setup(struct device *dev, unsigned gpio, | |||
| 470 | } | 470 | } |
| 471 | 471 | ||
| 472 | static struct twl4030_gpio_platform_data cm_t35_gpio_data = { | 472 | static struct twl4030_gpio_platform_data cm_t35_gpio_data = { |
| 473 | .gpio_base = OMAP_MAX_GPIO_LINES, | ||
| 474 | .irq_base = TWL4030_GPIO_IRQ_BASE, | ||
| 475 | .irq_end = TWL4030_GPIO_IRQ_END, | ||
| 476 | .setup = cm_t35_twl_gpio_setup, | 473 | .setup = cm_t35_twl_gpio_setup, |
| 477 | }; | 474 | }; |
| 478 | 475 | ||
| @@ -714,13 +711,8 @@ static inline void cm_t35_init_mux(void) {} | |||
| 714 | static inline void cm_t3730_init_mux(void) {} | 711 | static inline void cm_t3730_init_mux(void) {} |
| 715 | #endif | 712 | #endif |
| 716 | 713 | ||
| 717 | static struct omap_board_config_kernel cm_t35_config[] __initdata = { | ||
| 718 | }; | ||
| 719 | |||
| 720 | static void __init cm_t3x_common_init(void) | 714 | static void __init cm_t3x_common_init(void) |
| 721 | { | 715 | { |
| 722 | omap_board_config = cm_t35_config; | ||
| 723 | omap_board_config_size = ARRAY_SIZE(cm_t35_config); | ||
| 724 | omap3_mux_init(board_mux, OMAP_PACKAGE_CUS); | 716 | omap3_mux_init(board_mux, OMAP_PACKAGE_CUS); |
| 725 | omap_serial_init(); | 717 | omap_serial_init(); |
| 726 | omap_sdrc_init(mt46h32m32lf6_sdrc_params, | 718 | omap_sdrc_init(mt46h32m32lf6_sdrc_params, |
diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c index a33ad4641d9a..27a5450751ed 100644 --- a/arch/arm/mach-omap2/board-cm-t3517.c +++ b/arch/arm/mach-omap2/board-cm-t3517.c | |||
| @@ -38,7 +38,6 @@ | |||
| 38 | #include <asm/mach/arch.h> | 38 | #include <asm/mach/arch.h> |
| 39 | #include <asm/mach/map.h> | 39 | #include <asm/mach/map.h> |
| 40 | 40 | ||
| 41 | #include <plat/board.h> | ||
| 42 | #include "common.h" | 41 | #include "common.h" |
| 43 | #include <plat/usb.h> | 42 | #include <plat/usb.h> |
| 44 | #include <plat/nand.h> | 43 | #include <plat/nand.h> |
| @@ -90,8 +89,7 @@ static struct resource cm_t3517_hecc_resources[] = { | |||
| 90 | .flags = IORESOURCE_MEM, | 89 | .flags = IORESOURCE_MEM, |
| 91 | }, | 90 | }, |
| 92 | { | 91 | { |
| 93 | .start = INT_35XX_HECC0_IRQ, | 92 | .start = 24 + OMAP_INTC_START, |
| 94 | .end = INT_35XX_HECC0_IRQ, | ||
| 95 | .flags = IORESOURCE_IRQ, | 93 | .flags = IORESOURCE_IRQ, |
| 96 | }, | 94 | }, |
| 97 | }; | 95 | }; |
| @@ -249,9 +247,6 @@ static void __init cm_t3517_init_nand(void) | |||
| 249 | static inline void cm_t3517_init_nand(void) {} | 247 | static inline void cm_t3517_init_nand(void) {} |
| 250 | #endif | 248 | #endif |
| 251 | 249 | ||
| 252 | static struct omap_board_config_kernel cm_t3517_config[] __initdata = { | ||
| 253 | }; | ||
| 254 | |||
| 255 | #ifdef CONFIG_OMAP_MUX | 250 | #ifdef CONFIG_OMAP_MUX |
| 256 | static struct omap_board_mux board_mux[] __initdata = { | 251 | static struct omap_board_mux board_mux[] __initdata = { |
| 257 | /* GPIO186 - Green LED */ | 252 | /* GPIO186 - Green LED */ |
| @@ -285,8 +280,6 @@ static void __init cm_t3517_init(void) | |||
| 285 | omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); | 280 | omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); |
| 286 | omap_serial_init(); | 281 | omap_serial_init(); |
| 287 | omap_sdrc_init(NULL, NULL); | 282 | omap_sdrc_init(NULL, NULL); |
| 288 | omap_board_config = cm_t3517_config; | ||
| 289 | omap_board_config_size = ARRAY_SIZE(cm_t3517_config); | ||
| 290 | cm_t3517_init_leds(); | 283 | cm_t3517_init_leds(); |
| 291 | cm_t3517_init_nand(); | 284 | cm_t3517_init_nand(); |
| 292 | cm_t3517_init_rtc(); | 285 | cm_t3517_init_rtc(); |
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c index 6567c1cd5572..18b63ad56274 100644 --- a/arch/arm/mach-omap2/board-devkit8000.c +++ b/arch/arm/mach-omap2/board-devkit8000.c | |||
| @@ -32,15 +32,12 @@ | |||
| 32 | 32 | ||
| 33 | #include <linux/regulator/machine.h> | 33 | #include <linux/regulator/machine.h> |
| 34 | #include <linux/i2c/twl.h> | 34 | #include <linux/i2c/twl.h> |
| 35 | |||
| 36 | #include <mach/hardware.h> | ||
| 37 | #include <mach/id.h> | 35 | #include <mach/id.h> |
| 38 | #include <asm/mach-types.h> | 36 | #include <asm/mach-types.h> |
| 39 | #include <asm/mach/arch.h> | 37 | #include <asm/mach/arch.h> |
| 40 | #include <asm/mach/map.h> | 38 | #include <asm/mach/map.h> |
| 41 | #include <asm/mach/flash.h> | 39 | #include <asm/mach/flash.h> |
| 42 | 40 | ||
| 43 | #include <plat/board.h> | ||
| 44 | #include "common.h" | 41 | #include "common.h" |
| 45 | #include <plat/gpmc.h> | 42 | #include <plat/gpmc.h> |
| 46 | #include <plat/nand.h> | 43 | #include <plat/nand.h> |
| @@ -56,7 +53,6 @@ | |||
| 56 | #include <linux/interrupt.h> | 53 | #include <linux/interrupt.h> |
| 57 | 54 | ||
| 58 | #include "sdram-micron-mt46h32m32lf-6.h" | 55 | #include "sdram-micron-mt46h32m32lf-6.h" |
| 59 | |||
| 60 | #include "mux.h" | 56 | #include "mux.h" |
| 61 | #include "hsmmc.h" | 57 | #include "hsmmc.h" |
| 62 | #include "common-board-devices.h" | 58 | #include "common-board-devices.h" |
| @@ -236,9 +232,6 @@ static int devkit8000_twl_gpio_setup(struct device *dev, | |||
| 236 | } | 232 | } |
| 237 | 233 | ||
| 238 | static struct twl4030_gpio_platform_data devkit8000_gpio_data = { | 234 | static struct twl4030_gpio_platform_data devkit8000_gpio_data = { |
| 239 | .gpio_base = OMAP_MAX_GPIO_LINES, | ||
| 240 | .irq_base = TWL4030_GPIO_IRQ_BASE, | ||
| 241 | .irq_end = TWL4030_GPIO_IRQ_END, | ||
| 242 | .use_leds = true, | 235 | .use_leds = true, |
| 243 | .pulldowns = BIT(1) | BIT(2) | BIT(6) | BIT(8) | BIT(13) | 236 | .pulldowns = BIT(1) | BIT(2) | BIT(6) | BIT(8) | BIT(13) |
| 244 | | BIT(15) | BIT(16) | BIT(17), | 237 | | BIT(15) | BIT(16) | BIT(17), |
diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c index 53c39d239d6e..9017813f9abc 100644 --- a/arch/arm/mach-omap2/board-flash.c +++ b/arch/arm/mach-omap2/board-flash.c | |||
| @@ -16,13 +16,14 @@ | |||
| 16 | #include <linux/platform_device.h> | 16 | #include <linux/platform_device.h> |
| 17 | #include <linux/mtd/physmap.h> | 17 | #include <linux/mtd/physmap.h> |
| 18 | #include <linux/io.h> | 18 | #include <linux/io.h> |
| 19 | #include <plat/irqs.h> | ||
| 20 | 19 | ||
| 20 | #include <plat/cpu.h> | ||
| 21 | #include <plat/gpmc.h> | 21 | #include <plat/gpmc.h> |
| 22 | #include <plat/nand.h> | 22 | #include <plat/nand.h> |
| 23 | #include <plat/onenand.h> | 23 | #include <plat/onenand.h> |
| 24 | #include <plat/tc.h> | 24 | #include <plat/tc.h> |
| 25 | 25 | ||
| 26 | #include "common.h" | ||
| 26 | #include "board-flash.h" | 27 | #include "board-flash.h" |
| 27 | 28 | ||
| 28 | #define REG_FPGA_REV 0x10 | 29 | #define REG_FPGA_REV 0x10 |
| @@ -140,7 +141,6 @@ __init board_nand_init(struct mtd_partition *nand_parts, | |||
| 140 | board_nand_data.devsize = nand_type; | 141 | board_nand_data.devsize = nand_type; |
| 141 | 142 | ||
| 142 | board_nand_data.ecc_opt = OMAP_ECC_HAMMING_CODE_DEFAULT; | 143 | board_nand_data.ecc_opt = OMAP_ECC_HAMMING_CODE_DEFAULT; |
| 143 | board_nand_data.gpmc_irq = OMAP_GPMC_IRQ_BASE + cs; | ||
| 144 | gpmc_nand_init(&board_nand_data); | 144 | gpmc_nand_init(&board_nand_data); |
| 145 | } | 145 | } |
| 146 | #endif /* CONFIG_MTD_NAND_OMAP2 || CONFIG_MTD_NAND_OMAP2_MODULE */ | 146 | #endif /* CONFIG_MTD_NAND_OMAP2 || CONFIG_MTD_NAND_OMAP2_MODULE */ |
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c index 6f93a20536ea..2ea7c577b295 100644 --- a/arch/arm/mach-omap2/board-generic.c +++ b/arch/arm/mach-omap2/board-generic.c | |||
| @@ -16,11 +16,9 @@ | |||
| 16 | #include <linux/of_platform.h> | 16 | #include <linux/of_platform.h> |
| 17 | #include <linux/irqdomain.h> | 17 | #include <linux/irqdomain.h> |
| 18 | 18 | ||
| 19 | #include <mach/hardware.h> | ||
| 20 | #include <asm/hardware/gic.h> | 19 | #include <asm/hardware/gic.h> |
| 21 | #include <asm/mach/arch.h> | 20 | #include <asm/mach/arch.h> |
| 22 | 21 | ||
| 23 | #include <plat/board.h> | ||
| 24 | #include "common.h" | 22 | #include "common.h" |
| 25 | #include "common-board-devices.h" | 23 | #include "common-board-devices.h" |
| 26 | 24 | ||
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c index ace20482e3e1..12569cb0eddd 100644 --- a/arch/arm/mach-omap2/board-h4.c +++ b/arch/arm/mach-omap2/board-h4.c | |||
| @@ -27,20 +27,19 @@ | |||
| 27 | #include <linux/io.h> | 27 | #include <linux/io.h> |
| 28 | #include <linux/input/matrix_keypad.h> | 28 | #include <linux/input/matrix_keypad.h> |
| 29 | 29 | ||
| 30 | #include <mach/hardware.h> | ||
| 31 | #include <asm/mach-types.h> | 30 | #include <asm/mach-types.h> |
| 32 | #include <asm/mach/arch.h> | 31 | #include <asm/mach/arch.h> |
| 33 | #include <asm/mach/map.h> | 32 | #include <asm/mach/map.h> |
| 34 | 33 | ||
| 35 | #include <plat/board.h> | ||
| 36 | #include "common.h" | ||
| 37 | #include <plat/menelaus.h> | 34 | #include <plat/menelaus.h> |
| 38 | #include <plat/dma.h> | 35 | #include <plat/dma.h> |
| 39 | #include <plat/gpmc.h> | 36 | #include <plat/gpmc.h> |
| 37 | #include <plat/debug-devices.h> | ||
| 40 | 38 | ||
| 41 | #include <video/omapdss.h> | 39 | #include <video/omapdss.h> |
| 42 | #include <video/omap-panel-generic-dpi.h> | 40 | #include <video/omap-panel-generic-dpi.h> |
| 43 | 41 | ||
| 42 | #include "common.h" | ||
| 44 | #include "mux.h" | 43 | #include "mux.h" |
| 45 | #include "control.h" | 44 | #include "control.h" |
| 46 | 45 | ||
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c index 28214483aaba..8408bb2748a6 100644 --- a/arch/arm/mach-omap2/board-igep0020.c +++ b/arch/arm/mach-omap2/board-igep0020.c | |||
| @@ -29,10 +29,10 @@ | |||
| 29 | #include <asm/mach-types.h> | 29 | #include <asm/mach-types.h> |
| 30 | #include <asm/mach/arch.h> | 30 | #include <asm/mach/arch.h> |
| 31 | 31 | ||
| 32 | #include <plat/board.h> | ||
| 33 | #include "common.h" | 32 | #include "common.h" |
| 34 | #include <plat/gpmc.h> | 33 | #include <plat/gpmc.h> |
| 35 | #include <plat/usb.h> | 34 | #include <plat/usb.h> |
| 35 | |||
| 36 | #include <video/omapdss.h> | 36 | #include <video/omapdss.h> |
| 37 | #include <video/omap-panel-tfp410.h> | 37 | #include <video/omap-panel-tfp410.h> |
| 38 | #include <plat/onenand.h> | 38 | #include <plat/onenand.h> |
| @@ -425,9 +425,6 @@ static int igep_twl_gpio_setup(struct device *dev, | |||
| 425 | }; | 425 | }; |
| 426 | 426 | ||
| 427 | static struct twl4030_gpio_platform_data igep_twl4030_gpio_pdata = { | 427 | static struct twl4030_gpio_platform_data igep_twl4030_gpio_pdata = { |
| 428 | .gpio_base = OMAP_MAX_GPIO_LINES, | ||
| 429 | .irq_base = TWL4030_GPIO_IRQ_BASE, | ||
| 430 | .irq_end = TWL4030_GPIO_IRQ_END, | ||
| 431 | .use_leds = true, | 428 | .use_leds = true, |
| 432 | .setup = igep_twl_gpio_setup, | 429 | .setup = igep_twl_gpio_setup, |
| 433 | }; | 430 | }; |
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c index ef9e82977499..3f3a552b1036 100644 --- a/arch/arm/mach-omap2/board-ldp.c +++ b/arch/arm/mach-omap2/board-ldp.c | |||
| @@ -29,18 +29,14 @@ | |||
| 29 | #include <linux/smsc911x.h> | 29 | #include <linux/smsc911x.h> |
| 30 | #include <linux/mmc/host.h> | 30 | #include <linux/mmc/host.h> |
| 31 | 31 | ||
| 32 | #include <mach/hardware.h> | ||
| 33 | #include <asm/mach-types.h> | 32 | #include <asm/mach-types.h> |
| 34 | #include <asm/mach/arch.h> | 33 | #include <asm/mach/arch.h> |
| 35 | #include <asm/mach/map.h> | 34 | #include <asm/mach/map.h> |
| 36 | 35 | ||
| 37 | #include <plat/mcspi.h> | 36 | #include <plat/mcspi.h> |
| 38 | #include <plat/board.h> | ||
| 39 | #include "common.h" | 37 | #include "common.h" |
| 40 | #include <plat/gpmc.h> | 38 | #include <plat/gpmc.h> |
| 41 | #include <mach/board-zoom.h> | 39 | #include <mach/board-zoom.h> |
| 42 | |||
| 43 | #include <asm/delay.h> | ||
| 44 | #include <plat/usb.h> | 40 | #include <plat/usb.h> |
| 45 | #include <plat/gpmc-smsc911x.h> | 41 | #include <plat/gpmc-smsc911x.h> |
| 46 | 42 | ||
| @@ -275,9 +271,6 @@ static int ldp_twl_gpio_setup(struct device *dev, unsigned gpio, unsigned ngpio) | |||
| 275 | } | 271 | } |
| 276 | 272 | ||
| 277 | static struct twl4030_gpio_platform_data ldp_gpio_data = { | 273 | static struct twl4030_gpio_platform_data ldp_gpio_data = { |
| 278 | .gpio_base = OMAP_MAX_GPIO_LINES, | ||
| 279 | .irq_base = TWL4030_GPIO_IRQ_BASE, | ||
| 280 | .irq_end = TWL4030_GPIO_IRQ_END, | ||
| 281 | .setup = ldp_twl_gpio_setup, | 274 | .setup = ldp_twl_gpio_setup, |
| 282 | }; | 275 | }; |
| 283 | 276 | ||
diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c index 677357ff61ac..d8deaea37dca 100644 --- a/arch/arm/mach-omap2/board-n8x0.c +++ b/arch/arm/mach-omap2/board-n8x0.c | |||
| @@ -25,14 +25,11 @@ | |||
| 25 | #include <asm/mach/arch.h> | 25 | #include <asm/mach/arch.h> |
| 26 | #include <asm/mach-types.h> | 26 | #include <asm/mach-types.h> |
| 27 | 27 | ||
| 28 | #include <plat/board.h> | ||
| 29 | #include "common.h" | 28 | #include "common.h" |
| 30 | #include <plat/menelaus.h> | 29 | #include <plat/menelaus.h> |
| 31 | #include <mach/irqs.h> | ||
| 32 | #include <plat/mcspi.h> | 30 | #include <plat/mcspi.h> |
| 33 | #include <plat/onenand.h> | 31 | #include <plat/onenand.h> |
| 34 | #include <plat/mmc.h> | 32 | #include <plat/mmc.h> |
| 35 | #include <plat/serial.h> | ||
| 36 | 33 | ||
| 37 | #include "mux.h" | 34 | #include "mux.h" |
| 38 | 35 | ||
| @@ -600,7 +597,7 @@ static struct menelaus_platform_data n8x0_menelaus_platform_data __initdata = { | |||
| 600 | static struct i2c_board_info __initdata n8x0_i2c_board_info_1[] __initdata = { | 597 | static struct i2c_board_info __initdata n8x0_i2c_board_info_1[] __initdata = { |
| 601 | { | 598 | { |
| 602 | I2C_BOARD_INFO("menelaus", 0x72), | 599 | I2C_BOARD_INFO("menelaus", 0x72), |
| 603 | .irq = INT_24XX_SYS_NIRQ, | 600 | .irq = 7 + OMAP_INTC_START, |
| 604 | .platform_data = &n8x0_menelaus_platform_data, | 601 | .platform_data = &n8x0_menelaus_platform_data, |
| 605 | }, | 602 | }, |
| 606 | }; | 603 | }; |
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c index 6202fc76e490..801bcb4c5e22 100644 --- a/arch/arm/mach-omap2/board-omap3beagle.c +++ b/arch/arm/mach-omap2/board-omap3beagle.c | |||
| @@ -33,13 +33,11 @@ | |||
| 33 | #include <linux/regulator/machine.h> | 33 | #include <linux/regulator/machine.h> |
| 34 | #include <linux/i2c/twl.h> | 34 | #include <linux/i2c/twl.h> |
| 35 | 35 | ||
| 36 | #include <mach/hardware.h> | ||
| 37 | #include <asm/mach-types.h> | 36 | #include <asm/mach-types.h> |
| 38 | #include <asm/mach/arch.h> | 37 | #include <asm/mach/arch.h> |
| 39 | #include <asm/mach/map.h> | 38 | #include <asm/mach/map.h> |
| 40 | #include <asm/mach/flash.h> | 39 | #include <asm/mach/flash.h> |
| 41 | 40 | ||
| 42 | #include <plat/board.h> | ||
| 43 | #include "common.h" | 41 | #include "common.h" |
| 44 | #include <video/omapdss.h> | 42 | #include <video/omapdss.h> |
| 45 | #include <video/omap-panel-tfp410.h> | 43 | #include <video/omap-panel-tfp410.h> |
| @@ -297,9 +295,6 @@ static int beagle_twl_gpio_setup(struct device *dev, | |||
| 297 | } | 295 | } |
| 298 | 296 | ||
| 299 | static struct twl4030_gpio_platform_data beagle_gpio_data = { | 297 | static struct twl4030_gpio_platform_data beagle_gpio_data = { |
| 300 | .gpio_base = OMAP_MAX_GPIO_LINES, | ||
| 301 | .irq_base = TWL4030_GPIO_IRQ_BASE, | ||
| 302 | .irq_end = TWL4030_GPIO_IRQ_END, | ||
| 303 | .use_leds = true, | 298 | .use_leds = true, |
| 304 | .pullups = BIT(1), | 299 | .pullups = BIT(1), |
| 305 | .pulldowns = BIT(2) | BIT(6) | BIT(7) | BIT(8) | BIT(13) | 300 | .pulldowns = BIT(2) | BIT(6) | BIT(7) | BIT(8) | BIT(13) |
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c index 0d362e9f9cb9..b94873d0c6b6 100644 --- a/arch/arm/mach-omap2/board-omap3evm.c +++ b/arch/arm/mach-omap2/board-omap3evm.c | |||
| @@ -40,12 +40,10 @@ | |||
| 40 | #include <linux/mmc/host.h> | 40 | #include <linux/mmc/host.h> |
| 41 | #include <linux/export.h> | 41 | #include <linux/export.h> |
| 42 | 42 | ||
| 43 | #include <mach/hardware.h> | ||
| 44 | #include <asm/mach-types.h> | 43 | #include <asm/mach-types.h> |
| 45 | #include <asm/mach/arch.h> | 44 | #include <asm/mach/arch.h> |
| 46 | #include <asm/mach/map.h> | 45 | #include <asm/mach/map.h> |
| 47 | 46 | ||
| 48 | #include <plat/board.h> | ||
| 49 | #include <plat/usb.h> | 47 | #include <plat/usb.h> |
| 50 | #include <plat/nand.h> | 48 | #include <plat/nand.h> |
| 51 | #include "common.h" | 49 | #include "common.h" |
| @@ -75,6 +73,18 @@ | |||
| 75 | #define OMAP3EVM_GEN1_ETHR_GPIO_RST 64 | 73 | #define OMAP3EVM_GEN1_ETHR_GPIO_RST 64 |
| 76 | #define OMAP3EVM_GEN2_ETHR_GPIO_RST 7 | 74 | #define OMAP3EVM_GEN2_ETHR_GPIO_RST 7 |
| 77 | 75 | ||
| 76 | /* | ||
| 77 | * OMAP35x EVM revision | ||
| 78 | * Run time detection of EVM revision is done by reading Ethernet | ||
| 79 | * PHY ID - | ||
| 80 | * GEN_1 = 0x01150000 | ||
| 81 | * GEN_2 = 0x92200000 | ||
| 82 | */ | ||
| 83 | enum { | ||
| 84 | OMAP3EVM_BOARD_GEN_1 = 0, /* EVM Rev between A - D */ | ||
| 85 | OMAP3EVM_BOARD_GEN_2, /* EVM Rev >= Rev E */ | ||
| 86 | }; | ||
| 87 | |||
| 78 | static u8 omap3_evm_version; | 88 | static u8 omap3_evm_version; |
| 79 | 89 | ||
| 80 | u8 get_omap3_evm_rev(void) | 90 | u8 get_omap3_evm_rev(void) |
| @@ -377,9 +387,6 @@ static int omap3evm_twl_gpio_setup(struct device *dev, | |||
| 377 | } | 387 | } |
| 378 | 388 | ||
| 379 | static struct twl4030_gpio_platform_data omap3evm_gpio_data = { | 389 | static struct twl4030_gpio_platform_data omap3evm_gpio_data = { |
| 380 | .gpio_base = OMAP_MAX_GPIO_LINES, | ||
| 381 | .irq_base = TWL4030_GPIO_IRQ_BASE, | ||
| 382 | .irq_end = TWL4030_GPIO_IRQ_END, | ||
| 383 | .use_leds = true, | 390 | .use_leds = true, |
| 384 | .setup = omap3evm_twl_gpio_setup, | 391 | .setup = omap3evm_twl_gpio_setup, |
| 385 | }; | 392 | }; |
| @@ -526,9 +533,6 @@ static int __init omap3_evm_i2c_init(void) | |||
| 526 | return 0; | 533 | return 0; |
| 527 | } | 534 | } |
| 528 | 535 | ||
| 529 | static struct omap_board_config_kernel omap3_evm_config[] __initdata = { | ||
| 530 | }; | ||
| 531 | |||
| 532 | static struct usbhs_omap_board_data usbhs_bdata __initdata = { | 536 | static struct usbhs_omap_board_data usbhs_bdata __initdata = { |
| 533 | 537 | ||
| 534 | .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED, | 538 | .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED, |
| @@ -688,9 +692,6 @@ static void __init omap3_evm_init(void) | |||
| 688 | obm = (cpu_is_omap3630()) ? omap36x_board_mux : omap35x_board_mux; | 692 | obm = (cpu_is_omap3630()) ? omap36x_board_mux : omap35x_board_mux; |
| 689 | omap3_mux_init(obm, OMAP_PACKAGE_CBB); | 693 | omap3_mux_init(obm, OMAP_PACKAGE_CBB); |
| 690 | 694 | ||
| 691 | omap_board_config = omap3_evm_config; | ||
| 692 | omap_board_config_size = ARRAY_SIZE(omap3_evm_config); | ||
| 693 | |||
| 694 | omap_mux_init_gpio(63, OMAP_PIN_INPUT); | 695 | omap_mux_init_gpio(63, OMAP_PIN_INPUT); |
| 695 | omap_hsmmc_init(mmc); | 696 | omap_hsmmc_init(mmc); |
| 696 | 697 | ||
diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c index fca93d1afd43..b5e56fa83c19 100644 --- a/arch/arm/mach-omap2/board-omap3logic.c +++ b/arch/arm/mach-omap2/board-omap3logic.c | |||
| @@ -30,24 +30,21 @@ | |||
| 30 | #include <linux/i2c/twl.h> | 30 | #include <linux/i2c/twl.h> |
| 31 | #include <linux/mmc/host.h> | 31 | #include <linux/mmc/host.h> |
| 32 | 32 | ||
| 33 | #include <mach/hardware.h> | ||
| 34 | #include <asm/mach-types.h> | 33 | #include <asm/mach-types.h> |
| 35 | #include <asm/mach/arch.h> | 34 | #include <asm/mach/arch.h> |
| 36 | #include <asm/mach/map.h> | 35 | #include <asm/mach/map.h> |
| 37 | 36 | ||
| 38 | #include "mux.h" | ||
| 39 | #include "hsmmc.h" | ||
| 40 | #include "control.h" | ||
| 41 | #include "common-board-devices.h" | ||
| 42 | |||
| 43 | #include <plat/mux.h> | ||
| 44 | #include <plat/board.h> | ||
| 45 | #include "common.h" | ||
| 46 | #include <plat/gpmc-smsc911x.h> | 37 | #include <plat/gpmc-smsc911x.h> |
| 47 | #include <plat/gpmc.h> | 38 | #include <plat/gpmc.h> |
| 48 | #include <plat/sdrc.h> | 39 | #include <plat/sdrc.h> |
| 49 | #include <plat/usb.h> | 40 | #include <plat/usb.h> |
| 50 | 41 | ||
| 42 | #include "common.h" | ||
| 43 | #include "mux.h" | ||
| 44 | #include "hsmmc.h" | ||
| 45 | #include "control.h" | ||
| 46 | #include "common-board-devices.h" | ||
| 47 | |||
| 51 | #define OMAP3LOGIC_SMSC911X_CS 1 | 48 | #define OMAP3LOGIC_SMSC911X_CS 1 |
| 52 | 49 | ||
| 53 | #define OMAP3530_LV_SOM_MMC_GPIO_CD 110 | 50 | #define OMAP3530_LV_SOM_MMC_GPIO_CD 110 |
| @@ -78,9 +75,6 @@ static struct regulator_init_data omap3logic_vmmc1 = { | |||
| 78 | }; | 75 | }; |
| 79 | 76 | ||
| 80 | static struct twl4030_gpio_platform_data omap3logic_gpio_data = { | 77 | static struct twl4030_gpio_platform_data omap3logic_gpio_data = { |
| 81 | .gpio_base = OMAP_MAX_GPIO_LINES, | ||
| 82 | .irq_base = TWL4030_GPIO_IRQ_BASE, | ||
| 83 | .irq_end = TWL4030_GPIO_IRQ_END, | ||
| 84 | .use_leds = true, | 78 | .use_leds = true, |
| 85 | .pullups = BIT(1), | 79 | .pullups = BIT(1), |
| 86 | .pulldowns = BIT(2) | BIT(6) | BIT(7) | BIT(8) | 80 | .pulldowns = BIT(2) | BIT(6) | BIT(7) | BIT(8) |
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c index 57aebee44fd0..e700a98feba6 100644 --- a/arch/arm/mach-omap2/board-omap3pandora.c +++ b/arch/arm/mach-omap2/board-omap3pandora.c | |||
| @@ -40,9 +40,7 @@ | |||
| 40 | #include <asm/mach/arch.h> | 40 | #include <asm/mach/arch.h> |
| 41 | #include <asm/mach/map.h> | 41 | #include <asm/mach/map.h> |
| 42 | 42 | ||
| 43 | #include <plat/board.h> | ||
| 44 | #include "common.h" | 43 | #include "common.h" |
| 45 | #include <mach/hardware.h> | ||
| 46 | #include <plat/mcspi.h> | 44 | #include <plat/mcspi.h> |
| 47 | #include <plat/usb.h> | 45 | #include <plat/usb.h> |
| 48 | #include <video/omapdss.h> | 46 | #include <video/omapdss.h> |
| @@ -321,9 +319,6 @@ static int omap3pandora_twl_gpio_setup(struct device *dev, | |||
| 321 | } | 319 | } |
| 322 | 320 | ||
| 323 | static struct twl4030_gpio_platform_data omap3pandora_gpio_data = { | 321 | static struct twl4030_gpio_platform_data omap3pandora_gpio_data = { |
| 324 | .gpio_base = OMAP_MAX_GPIO_LINES, | ||
| 325 | .irq_base = TWL4030_GPIO_IRQ_BASE, | ||
| 326 | .irq_end = TWL4030_GPIO_IRQ_END, | ||
| 327 | .setup = omap3pandora_twl_gpio_setup, | 322 | .setup = omap3pandora_twl_gpio_setup, |
| 328 | }; | 323 | }; |
| 329 | 324 | ||
diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c index b318f5602e36..b8756f0d2a08 100644 --- a/arch/arm/mach-omap2/board-omap3stalker.c +++ b/arch/arm/mach-omap2/board-omap3stalker.c | |||
| @@ -28,14 +28,17 @@ | |||
| 28 | #include <linux/regulator/machine.h> | 28 | #include <linux/regulator/machine.h> |
| 29 | #include <linux/i2c/twl.h> | 29 | #include <linux/i2c/twl.h> |
| 30 | #include <linux/mmc/host.h> | 30 | #include <linux/mmc/host.h> |
| 31 | #include <linux/input/matrix_keypad.h> | ||
| 32 | #include <linux/spi/spi.h> | ||
| 33 | #include <linux/interrupt.h> | ||
| 34 | #include <linux/smsc911x.h> | ||
| 35 | #include <linux/i2c/at24.h> | ||
| 31 | 36 | ||
| 32 | #include <mach/hardware.h> | ||
| 33 | #include <asm/mach-types.h> | 37 | #include <asm/mach-types.h> |
| 34 | #include <asm/mach/arch.h> | 38 | #include <asm/mach/arch.h> |
| 35 | #include <asm/mach/map.h> | 39 | #include <asm/mach/map.h> |
| 36 | #include <asm/mach/flash.h> | 40 | #include <asm/mach/flash.h> |
| 37 | 41 | ||
| 38 | #include <plat/board.h> | ||
| 39 | #include "common.h" | 42 | #include "common.h" |
| 40 | #include <plat/gpmc.h> | 43 | #include <plat/gpmc.h> |
| 41 | #include <plat/nand.h> | 44 | #include <plat/nand.h> |
| @@ -279,9 +282,6 @@ omap3stalker_twl_gpio_setup(struct device *dev, | |||
| 279 | } | 282 | } |
| 280 | 283 | ||
| 281 | static struct twl4030_gpio_platform_data omap3stalker_gpio_data = { | 284 | static struct twl4030_gpio_platform_data omap3stalker_gpio_data = { |
| 282 | .gpio_base = OMAP_MAX_GPIO_LINES, | ||
| 283 | .irq_base = TWL4030_GPIO_IRQ_BASE, | ||
| 284 | .irq_end = TWL4030_GPIO_IRQ_END, | ||
| 285 | .use_leds = true, | 285 | .use_leds = true, |
| 286 | .setup = omap3stalker_twl_gpio_setup, | 286 | .setup = omap3stalker_twl_gpio_setup, |
| 287 | }; | 287 | }; |
| @@ -362,9 +362,6 @@ static int __init omap3_stalker_i2c_init(void) | |||
| 362 | 362 | ||
| 363 | #define OMAP3_STALKER_TS_GPIO 175 | 363 | #define OMAP3_STALKER_TS_GPIO 175 |
| 364 | 364 | ||
| 365 | static struct omap_board_config_kernel omap3_stalker_config[] __initdata = { | ||
| 366 | }; | ||
| 367 | |||
| 368 | static struct platform_device *omap3_stalker_devices[] __initdata = { | 365 | static struct platform_device *omap3_stalker_devices[] __initdata = { |
| 369 | &keys_gpio, | 366 | &keys_gpio, |
| 370 | }; | 367 | }; |
| @@ -399,8 +396,6 @@ static void __init omap3_stalker_init(void) | |||
| 399 | { | 396 | { |
| 400 | regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies)); | 397 | regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies)); |
| 401 | omap3_mux_init(board_mux, OMAP_PACKAGE_CUS); | 398 | omap3_mux_init(board_mux, OMAP_PACKAGE_CUS); |
| 402 | omap_board_config = omap3_stalker_config; | ||
| 403 | omap_board_config_size = ARRAY_SIZE(omap3_stalker_config); | ||
| 404 | 399 | ||
| 405 | omap_mux_init_gpio(23, OMAP_PIN_INPUT); | 400 | omap_mux_init_gpio(23, OMAP_PIN_INPUT); |
| 406 | omap_hsmmc_init(mmc); | 401 | omap_hsmmc_init(mmc); |
diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c index 485d14d6a8cd..0e2f838e4009 100644 --- a/arch/arm/mach-omap2/board-omap3touchbook.c +++ b/arch/arm/mach-omap2/board-omap3touchbook.c | |||
| @@ -37,14 +37,12 @@ | |||
| 37 | #include <linux/regulator/machine.h> | 37 | #include <linux/regulator/machine.h> |
| 38 | #include <linux/i2c/twl.h> | 38 | #include <linux/i2c/twl.h> |
| 39 | 39 | ||
| 40 | #include <mach/hardware.h> | ||
| 41 | #include <asm/mach-types.h> | 40 | #include <asm/mach-types.h> |
| 42 | #include <asm/mach/arch.h> | 41 | #include <asm/mach/arch.h> |
| 43 | #include <asm/mach/map.h> | 42 | #include <asm/mach/map.h> |
| 44 | #include <asm/mach/flash.h> | 43 | #include <asm/mach/flash.h> |
| 45 | #include <asm/system_info.h> | 44 | #include <asm/system_info.h> |
| 46 | 45 | ||
| 47 | #include <plat/board.h> | ||
| 48 | #include "common.h" | 46 | #include "common.h" |
| 49 | #include <plat/gpmc.h> | 47 | #include <plat/gpmc.h> |
| 50 | #include <plat/nand.h> | 48 | #include <plat/nand.h> |
| @@ -139,9 +137,6 @@ static int touchbook_twl_gpio_setup(struct device *dev, | |||
| 139 | } | 137 | } |
| 140 | 138 | ||
| 141 | static struct twl4030_gpio_platform_data touchbook_gpio_data = { | 139 | static struct twl4030_gpio_platform_data touchbook_gpio_data = { |
| 142 | .gpio_base = OMAP_MAX_GPIO_LINES, | ||
| 143 | .irq_base = TWL4030_GPIO_IRQ_BASE, | ||
| 144 | .irq_end = TWL4030_GPIO_IRQ_END, | ||
| 145 | .use_leds = true, | 140 | .use_leds = true, |
| 146 | .pullups = BIT(1), | 141 | .pullups = BIT(1), |
| 147 | .pulldowns = BIT(2) | BIT(6) | BIT(7) | BIT(8) | BIT(13) | 142 | .pulldowns = BIT(2) | BIT(6) | BIT(7) | BIT(8) | BIT(13) |
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c index 70f6d1d25463..45fe2d3f59b1 100644 --- a/arch/arm/mach-omap2/board-omap4panda.c +++ b/arch/arm/mach-omap2/board-omap4panda.c | |||
| @@ -32,19 +32,18 @@ | |||
| 32 | #include <linux/wl12xx.h> | 32 | #include <linux/wl12xx.h> |
| 33 | #include <linux/platform_data/omap-abe-twl6040.h> | 33 | #include <linux/platform_data/omap-abe-twl6040.h> |
| 34 | 34 | ||
| 35 | #include <mach/hardware.h> | ||
| 36 | #include <asm/hardware/gic.h> | 35 | #include <asm/hardware/gic.h> |
| 37 | #include <asm/mach-types.h> | 36 | #include <asm/mach-types.h> |
| 38 | #include <asm/mach/arch.h> | 37 | #include <asm/mach/arch.h> |
| 39 | #include <asm/mach/map.h> | 38 | #include <asm/mach/map.h> |
| 40 | #include <video/omapdss.h> | 39 | #include <video/omapdss.h> |
| 41 | 40 | ||
| 42 | #include <plat/board.h> | ||
| 43 | #include "common.h" | 41 | #include "common.h" |
| 44 | #include <plat/usb.h> | 42 | #include <plat/usb.h> |
| 45 | #include <plat/mmc.h> | 43 | #include <plat/mmc.h> |
| 46 | #include <video/omap-panel-tfp410.h> | 44 | #include <video/omap-panel-tfp410.h> |
| 47 | 45 | ||
| 46 | #include "soc.h" | ||
| 48 | #include "hsmmc.h" | 47 | #include "hsmmc.h" |
| 49 | #include "control.h" | 48 | #include "control.h" |
| 50 | #include "mux.h" | 49 | #include "mux.h" |
| @@ -263,7 +262,6 @@ static struct twl6040_codec_data twl6040_codec = { | |||
| 263 | static struct twl6040_platform_data twl6040_data = { | 262 | static struct twl6040_platform_data twl6040_data = { |
| 264 | .codec = &twl6040_codec, | 263 | .codec = &twl6040_codec, |
| 265 | .audpwron_gpio = 127, | 264 | .audpwron_gpio = 127, |
| 266 | .irq_base = TWL6040_CODEC_IRQ_BASE, | ||
| 267 | }; | 265 | }; |
| 268 | 266 | ||
| 269 | /* Panda board uses the common PMIC configuration */ | 267 | /* Panda board uses the common PMIC configuration */ |
| @@ -294,7 +292,7 @@ static int __init omap4_panda_i2c_init(void) | |||
| 294 | TWL_COMMON_REGULATOR_V1V8 | | 292 | TWL_COMMON_REGULATOR_V1V8 | |
| 295 | TWL_COMMON_REGULATOR_V2V1); | 293 | TWL_COMMON_REGULATOR_V2V1); |
| 296 | omap4_pmic_init("twl6030", &omap4_panda_twldata, | 294 | omap4_pmic_init("twl6030", &omap4_panda_twldata, |
| 297 | &twl6040_data, OMAP44XX_IRQ_SYS_2N); | 295 | &twl6040_data, 119 + OMAP44XX_IRQ_GIC_START); |
| 298 | omap_register_i2c_bus(2, 400, NULL, 0); | 296 | omap_register_i2c_bus(2, 400, NULL, 0); |
| 299 | /* | 297 | /* |
| 300 | * Bus 3 is attached to the DVI port where devices like the pico DLP | 298 | * Bus 3 is attached to the DVI port where devices like the pico DLP |
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c index 779734d8ba37..7a62d1322b7a 100644 --- a/arch/arm/mach-omap2/board-overo.c +++ b/arch/arm/mach-omap2/board-overo.c | |||
| @@ -42,16 +42,13 @@ | |||
| 42 | #include <asm/mach/flash.h> | 42 | #include <asm/mach/flash.h> |
| 43 | #include <asm/mach/map.h> | 43 | #include <asm/mach/map.h> |
| 44 | 44 | ||
| 45 | #include <plat/board.h> | ||
| 46 | #include "common.h" | 45 | #include "common.h" |
| 47 | #include <video/omapdss.h> | 46 | #include <video/omapdss.h> |
| 48 | #include <video/omap-panel-generic-dpi.h> | 47 | #include <video/omap-panel-generic-dpi.h> |
| 49 | #include <video/omap-panel-tfp410.h> | 48 | #include <video/omap-panel-tfp410.h> |
| 50 | #include <plat/gpmc.h> | 49 | #include <plat/gpmc.h> |
| 51 | #include <mach/hardware.h> | ||
| 52 | #include <plat/nand.h> | 50 | #include <plat/nand.h> |
| 53 | #include <plat/mcspi.h> | 51 | #include <plat/mcspi.h> |
| 54 | #include <plat/mux.h> | ||
| 55 | #include <plat/usb.h> | 52 | #include <plat/usb.h> |
| 56 | 53 | ||
| 57 | #include "mux.h" | 54 | #include "mux.h" |
| @@ -399,9 +396,6 @@ static int overo_twl_gpio_setup(struct device *dev, | |||
| 399 | } | 396 | } |
| 400 | 397 | ||
| 401 | static struct twl4030_gpio_platform_data overo_gpio_data = { | 398 | static struct twl4030_gpio_platform_data overo_gpio_data = { |
| 402 | .gpio_base = OMAP_MAX_GPIO_LINES, | ||
| 403 | .irq_base = TWL4030_GPIO_IRQ_BASE, | ||
| 404 | .irq_end = TWL4030_GPIO_IRQ_END, | ||
| 405 | .use_leds = true, | 399 | .use_leds = true, |
| 406 | .setup = overo_twl_gpio_setup, | 400 | .setup = overo_twl_gpio_setup, |
| 407 | }; | 401 | }; |
diff --git a/arch/arm/mach-omap2/board-rm680.c b/arch/arm/mach-omap2/board-rm680.c index 0ad1bb3bdb98..00773a32524a 100644 --- a/arch/arm/mach-omap2/board-rm680.c +++ b/arch/arm/mach-omap2/board-rm680.c | |||
| @@ -27,6 +27,7 @@ | |||
| 27 | #include <plat/gpmc.h> | 27 | #include <plat/gpmc.h> |
| 28 | #include "common.h" | 28 | #include "common.h" |
| 29 | #include <plat/onenand.h> | 29 | #include <plat/onenand.h> |
| 30 | #include <plat/serial.h> | ||
| 30 | 31 | ||
| 31 | #include "mux.h" | 32 | #include "mux.h" |
| 32 | #include "hsmmc.h" | 33 | #include "hsmmc.h" |
| @@ -72,9 +73,6 @@ static struct platform_device *rm680_peripherals_devices[] __initdata = { | |||
| 72 | 73 | ||
| 73 | /* TWL */ | 74 | /* TWL */ |
| 74 | static struct twl4030_gpio_platform_data rm680_gpio_data = { | 75 | static struct twl4030_gpio_platform_data rm680_gpio_data = { |
| 75 | .gpio_base = OMAP_MAX_GPIO_LINES, | ||
| 76 | .irq_base = TWL4030_GPIO_IRQ_BASE, | ||
| 77 | .irq_end = TWL4030_GPIO_IRQ_END, | ||
| 78 | .pullups = BIT(0), | 76 | .pullups = BIT(0), |
| 79 | .pulldowns = BIT(1) | BIT(2) | BIT(8) | BIT(15), | 77 | .pulldowns = BIT(1) | BIT(2) | BIT(8) | BIT(15), |
| 80 | }; | 78 | }; |
| @@ -87,7 +85,7 @@ static struct twl4030_platform_data rm680_twl_data = { | |||
| 87 | static void __init rm680_i2c_init(void) | 85 | static void __init rm680_i2c_init(void) |
| 88 | { | 86 | { |
| 89 | omap3_pmic_get_config(&rm680_twl_data, TWL_COMMON_PDATA_USB, 0); | 87 | omap3_pmic_get_config(&rm680_twl_data, TWL_COMMON_PDATA_USB, 0); |
| 90 | omap_pmic_init(1, 2900, "twl5031", INT_34XX_SYS_NIRQ, &rm680_twl_data); | 88 | omap_pmic_init(1, 2900, "twl5031", 7 + OMAP_INTC_START, &rm680_twl_data); |
| 91 | omap_register_i2c_bus(2, 400, NULL, 0); | 89 | omap_register_i2c_bus(2, 400, NULL, 0); |
| 92 | omap_register_i2c_bus(3, 400, NULL, 0); | 90 | omap_register_i2c_bus(3, 400, NULL, 0); |
| 93 | } | 91 | } |
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c index df2534de3361..456049055daa 100644 --- a/arch/arm/mach-omap2/board-rx51-peripherals.c +++ b/arch/arm/mach-omap2/board-rx51-peripherals.c | |||
| @@ -28,7 +28,6 @@ | |||
| 28 | #include <asm/system_info.h> | 28 | #include <asm/system_info.h> |
| 29 | 29 | ||
| 30 | #include <plat/mcspi.h> | 30 | #include <plat/mcspi.h> |
| 31 | #include <plat/board.h> | ||
| 32 | #include "common.h" | 31 | #include "common.h" |
| 33 | #include <plat/dma.h> | 32 | #include <plat/dma.h> |
| 34 | #include <plat/gpmc.h> | 33 | #include <plat/gpmc.h> |
| @@ -774,9 +773,6 @@ static int rx51_twlgpio_setup(struct device *dev, unsigned gpio, unsigned n) | |||
| 774 | } | 773 | } |
| 775 | 774 | ||
| 776 | static struct twl4030_gpio_platform_data rx51_gpio_data = { | 775 | static struct twl4030_gpio_platform_data rx51_gpio_data = { |
| 777 | .gpio_base = OMAP_MAX_GPIO_LINES, | ||
| 778 | .irq_base = TWL4030_GPIO_IRQ_BASE, | ||
| 779 | .irq_end = TWL4030_GPIO_IRQ_END, | ||
| 780 | .pulldowns = BIT(0) | BIT(1) | BIT(2) | BIT(3) | 776 | .pulldowns = BIT(0) | BIT(1) | BIT(2) | BIT(3) |
| 781 | | BIT(4) | BIT(5) | 777 | | BIT(4) | BIT(5) |
| 782 | | BIT(8) | BIT(9) | BIT(10) | BIT(11) | 778 | | BIT(8) | BIT(9) | BIT(10) | BIT(11) |
| @@ -1051,7 +1047,7 @@ static int __init rx51_i2c_init(void) | |||
| 1051 | rx51_twldata.vdac->constraints.apply_uV = true; | 1047 | rx51_twldata.vdac->constraints.apply_uV = true; |
| 1052 | rx51_twldata.vdac->constraints.name = "VDAC"; | 1048 | rx51_twldata.vdac->constraints.name = "VDAC"; |
| 1053 | 1049 | ||
| 1054 | omap_pmic_init(1, 2200, "twl5030", INT_34XX_SYS_NIRQ, &rx51_twldata); | 1050 | omap_pmic_init(1, 2200, "twl5030", 7 + OMAP_INTC_START, &rx51_twldata); |
| 1055 | omap_register_i2c_bus(2, 100, rx51_peripherals_i2c_board_info_2, | 1051 | omap_register_i2c_bus(2, 100, rx51_peripherals_i2c_board_info_2, |
| 1056 | ARRAY_SIZE(rx51_peripherals_i2c_board_info_2)); | 1052 | ARRAY_SIZE(rx51_peripherals_i2c_board_info_2)); |
| 1057 | #if defined(CONFIG_SENSORS_LIS3_I2C) || defined(CONFIG_SENSORS_LIS3_I2C_MODULE) | 1053 | #if defined(CONFIG_SENSORS_LIS3_I2C) || defined(CONFIG_SENSORS_LIS3_I2C_MODULE) |
diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c index 345dd931f76f..93b466150002 100644 --- a/arch/arm/mach-omap2/board-rx51.c +++ b/arch/arm/mach-omap2/board-rx51.c | |||
| @@ -18,13 +18,11 @@ | |||
| 18 | #include <linux/gpio.h> | 18 | #include <linux/gpio.h> |
| 19 | #include <linux/leds.h> | 19 | #include <linux/leds.h> |
| 20 | 20 | ||
| 21 | #include <mach/hardware.h> | ||
| 22 | #include <asm/mach-types.h> | 21 | #include <asm/mach-types.h> |
| 23 | #include <asm/mach/arch.h> | 22 | #include <asm/mach/arch.h> |
| 24 | #include <asm/mach/map.h> | 23 | #include <asm/mach/map.h> |
| 25 | 24 | ||
| 26 | #include <plat/mcspi.h> | 25 | #include <plat/mcspi.h> |
| 27 | #include <plat/board.h> | ||
| 28 | #include "common.h" | 26 | #include "common.h" |
| 29 | #include <plat/dma.h> | 27 | #include <plat/dma.h> |
| 30 | #include <plat/gpmc.h> | 28 | #include <plat/gpmc.h> |
diff --git a/arch/arm/mach-omap2/board-ti8168evm.c b/arch/arm/mach-omap2/board-ti8168evm.c index d4c8392cadb6..c4f8833b4c3c 100644 --- a/arch/arm/mach-omap2/board-ti8168evm.c +++ b/arch/arm/mach-omap2/board-ti8168evm.c | |||
| @@ -15,13 +15,10 @@ | |||
| 15 | #include <linux/kernel.h> | 15 | #include <linux/kernel.h> |
| 16 | #include <linux/init.h> | 16 | #include <linux/init.h> |
| 17 | 17 | ||
| 18 | #include <mach/hardware.h> | ||
| 19 | #include <asm/mach-types.h> | 18 | #include <asm/mach-types.h> |
| 20 | #include <asm/mach/arch.h> | 19 | #include <asm/mach/arch.h> |
| 21 | #include <asm/mach/map.h> | 20 | #include <asm/mach/map.h> |
| 22 | 21 | ||
| 23 | #include <plat/irqs.h> | ||
| 24 | #include <plat/board.h> | ||
| 25 | #include "common.h" | 22 | #include "common.h" |
| 26 | #include <plat/usb.h> | 23 | #include <plat/usb.h> |
| 27 | 24 | ||
| @@ -32,15 +29,10 @@ static struct omap_musb_board_data musb_board_data = { | |||
| 32 | .power = 500, | 29 | .power = 500, |
| 33 | }; | 30 | }; |
| 34 | 31 | ||
| 35 | static struct omap_board_config_kernel ti81xx_evm_config[] __initdata = { | ||
| 36 | }; | ||
| 37 | |||
| 38 | static void __init ti81xx_evm_init(void) | 32 | static void __init ti81xx_evm_init(void) |
| 39 | { | 33 | { |
| 40 | omap_serial_init(); | 34 | omap_serial_init(); |
| 41 | omap_sdrc_init(NULL, NULL); | 35 | omap_sdrc_init(NULL, NULL); |
| 42 | omap_board_config = ti81xx_evm_config; | ||
| 43 | omap_board_config_size = ARRAY_SIZE(ti81xx_evm_config); | ||
| 44 | usb_musb_init(&musb_board_data); | 36 | usb_musb_init(&musb_board_data); |
| 45 | } | 37 | } |
| 46 | 38 | ||
diff --git a/arch/arm/mach-omap2/board-zoom-debugboard.c b/arch/arm/mach-omap2/board-zoom-debugboard.c index f64f44173061..5ec069e529e7 100644 --- a/arch/arm/mach-omap2/board-zoom-debugboard.c +++ b/arch/arm/mach-omap2/board-zoom-debugboard.c | |||
| @@ -22,6 +22,9 @@ | |||
| 22 | 22 | ||
| 23 | #include <mach/board-zoom.h> | 23 | #include <mach/board-zoom.h> |
| 24 | 24 | ||
| 25 | #include "soc.h" | ||
| 26 | #include "common.h" | ||
| 27 | |||
| 25 | #define ZOOM_SMSC911X_CS 7 | 28 | #define ZOOM_SMSC911X_CS 7 |
| 26 | #define ZOOM_SMSC911X_GPIO 158 | 29 | #define ZOOM_SMSC911X_GPIO 158 |
| 27 | #define ZOOM_QUADUART_CS 3 | 30 | #define ZOOM_QUADUART_CS 3 |
diff --git a/arch/arm/mach-omap2/board-zoom-display.c b/arch/arm/mach-omap2/board-zoom-display.c index 28187f134fff..ea79bc299baf 100644 --- a/arch/arm/mach-omap2/board-zoom-display.c +++ b/arch/arm/mach-omap2/board-zoom-display.c | |||
| @@ -18,6 +18,8 @@ | |||
| 18 | #include <video/omapdss.h> | 18 | #include <video/omapdss.h> |
| 19 | #include <mach/board-zoom.h> | 19 | #include <mach/board-zoom.h> |
| 20 | 20 | ||
| 21 | #include "common.h" | ||
| 22 | |||
| 21 | #define LCD_PANEL_RESET_GPIO_PROD 96 | 23 | #define LCD_PANEL_RESET_GPIO_PROD 96 |
| 22 | #define LCD_PANEL_RESET_GPIO_PILOT 55 | 24 | #define LCD_PANEL_RESET_GPIO_PILOT 55 |
| 23 | #define LCD_PANEL_QVGA_GPIO 56 | 25 | #define LCD_PANEL_QVGA_GPIO 56 |
diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c index b797cb279618..6bcc107b9fc3 100644 --- a/arch/arm/mach-omap2/board-zoom-peripherals.c +++ b/arch/arm/mach-omap2/board-zoom-peripherals.c | |||
| @@ -19,6 +19,7 @@ | |||
| 19 | #include <linux/regulator/fixed.h> | 19 | #include <linux/regulator/fixed.h> |
| 20 | #include <linux/wl12xx.h> | 20 | #include <linux/wl12xx.h> |
| 21 | #include <linux/mmc/host.h> | 21 | #include <linux/mmc/host.h> |
| 22 | #include <linux/platform_data/gpio-omap.h> | ||
| 22 | 23 | ||
| 23 | #include <asm/mach-types.h> | 24 | #include <asm/mach-types.h> |
| 24 | #include <asm/mach/arch.h> | 25 | #include <asm/mach/arch.h> |
| @@ -251,9 +252,6 @@ static void zoom2_set_hs_extmute(int mute) | |||
| 251 | } | 252 | } |
| 252 | 253 | ||
| 253 | static struct twl4030_gpio_platform_data zoom_gpio_data = { | 254 | static struct twl4030_gpio_platform_data zoom_gpio_data = { |
| 254 | .gpio_base = OMAP_MAX_GPIO_LINES, | ||
| 255 | .irq_base = TWL4030_GPIO_IRQ_BASE, | ||
| 256 | .irq_end = TWL4030_GPIO_IRQ_END, | ||
| 257 | .setup = zoom_twl_gpio_setup, | 255 | .setup = zoom_twl_gpio_setup, |
| 258 | }; | 256 | }; |
| 259 | 257 | ||
| @@ -281,7 +279,7 @@ static int __init omap_i2c_init(void) | |||
| 281 | codec_data->hs_extmute = 1; | 279 | codec_data->hs_extmute = 1; |
| 282 | codec_data->set_hs_extmute = zoom2_set_hs_extmute; | 280 | codec_data->set_hs_extmute = zoom2_set_hs_extmute; |
| 283 | } | 281 | } |
| 284 | omap_pmic_init(1, 2400, "twl5030", INT_34XX_SYS_NIRQ, &zoom_twldata); | 282 | omap_pmic_init(1, 2400, "twl5030", 7 + OMAP_INTC_START, &zoom_twldata); |
| 285 | omap_register_i2c_bus(2, 400, NULL, 0); | 283 | omap_register_i2c_bus(2, 400, NULL, 0); |
| 286 | omap_register_i2c_bus(3, 400, NULL, 0); | 284 | omap_register_i2c_bus(3, 400, NULL, 0); |
| 287 | return 0; | 285 | return 0; |
diff --git a/arch/arm/mach-omap2/board-zoom.c b/arch/arm/mach-omap2/board-zoom.c index 4e7e56142e6f..4994438e1f46 100644 --- a/arch/arm/mach-omap2/board-zoom.c +++ b/arch/arm/mach-omap2/board-zoom.c | |||
| @@ -22,7 +22,6 @@ | |||
| 22 | #include <asm/mach/arch.h> | 22 | #include <asm/mach/arch.h> |
| 23 | 23 | ||
| 24 | #include "common.h" | 24 | #include "common.h" |
| 25 | #include <plat/board.h> | ||
| 26 | #include <plat/usb.h> | 25 | #include <plat/usb.h> |
| 27 | 26 | ||
| 28 | #include <mach/board-zoom.h> | 27 | #include <mach/board-zoom.h> |
diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c index 3d9d746b221a..cabcfdba5246 100644 --- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c +++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c | |||
| @@ -33,11 +33,11 @@ | |||
| 33 | #include <linux/cpufreq.h> | 33 | #include <linux/cpufreq.h> |
| 34 | #include <linux/slab.h> | 34 | #include <linux/slab.h> |
| 35 | 35 | ||
| 36 | #include <plat/cpu.h> | ||
| 37 | #include <plat/clock.h> | 36 | #include <plat/clock.h> |
| 38 | #include <plat/sram.h> | 37 | #include <plat/sram.h> |
| 39 | #include <plat/sdrc.h> | 38 | #include <plat/sdrc.h> |
| 40 | 39 | ||
| 40 | #include "soc.h" | ||
| 41 | #include "clock.h" | 41 | #include "clock.h" |
| 42 | #include "clock2xxx.h" | 42 | #include "clock2xxx.h" |
| 43 | #include "opp2xxx.h" | 43 | #include "opp2xxx.h" |
diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c index cd7fd0f91149..ae624c3b832a 100644 --- a/arch/arm/mach-omap2/clkt_dpll.c +++ b/arch/arm/mach-omap2/clkt_dpll.c | |||
| @@ -22,8 +22,8 @@ | |||
| 22 | #include <asm/div64.h> | 22 | #include <asm/div64.h> |
| 23 | 23 | ||
| 24 | #include <plat/clock.h> | 24 | #include <plat/clock.h> |
| 25 | #include <plat/cpu.h> | ||
| 26 | 25 | ||
| 26 | #include "soc.h" | ||
| 27 | #include "clock.h" | 27 | #include "clock.h" |
| 28 | #include "cm-regbits-24xx.h" | 28 | #include "cm-regbits-24xx.h" |
| 29 | #include "cm-regbits-34xx.h" | 29 | #include "cm-regbits-34xx.h" |
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index ea3f565ba1a4..1a1f97f3ca69 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c | |||
| @@ -22,14 +22,16 @@ | |||
| 22 | #include <linux/clk.h> | 22 | #include <linux/clk.h> |
| 23 | #include <linux/io.h> | 23 | #include <linux/io.h> |
| 24 | #include <linux/bitops.h> | 24 | #include <linux/bitops.h> |
| 25 | #include <trace/events/power.h> | ||
| 26 | 25 | ||
| 27 | #include <asm/cpu.h> | 26 | #include <asm/cpu.h> |
| 27 | |||
| 28 | #include <plat/clock.h> | 28 | #include <plat/clock.h> |
| 29 | #include "clockdomain.h" | ||
| 30 | #include <plat/cpu.h> | ||
| 31 | #include <plat/prcm.h> | 29 | #include <plat/prcm.h> |
| 32 | 30 | ||
| 31 | #include <trace/events/power.h> | ||
| 32 | |||
| 33 | #include "soc.h" | ||
| 34 | #include "clockdomain.h" | ||
| 33 | #include "clock.h" | 35 | #include "clock.h" |
| 34 | #include "cm2xxx_3xxx.h" | 36 | #include "cm2xxx_3xxx.h" |
| 35 | #include "cm-regbits-24xx.h" | 37 | #include "cm-regbits-24xx.h" |
diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c index 002745181ad6..12c178dbc9f5 100644 --- a/arch/arm/mach-omap2/clock2420_data.c +++ b/arch/arm/mach-omap2/clock2420_data.c | |||
| @@ -18,9 +18,9 @@ | |||
| 18 | #include <linux/clk.h> | 18 | #include <linux/clk.h> |
| 19 | #include <linux/list.h> | 19 | #include <linux/list.h> |
| 20 | 20 | ||
| 21 | #include <plat/hardware.h> | ||
| 22 | #include <plat/clkdev_omap.h> | 21 | #include <plat/clkdev_omap.h> |
| 23 | 22 | ||
| 23 | #include "soc.h" | ||
| 24 | #include "iomap.h" | 24 | #include "iomap.h" |
| 25 | #include "clock.h" | 25 | #include "clock.h" |
| 26 | #include "clock2xxx.h" | 26 | #include "clock2xxx.h" |
diff --git a/arch/arm/mach-omap2/clock2430.c b/arch/arm/mach-omap2/clock2430.c index dfda9a3f2cb2..a8e326177466 100644 --- a/arch/arm/mach-omap2/clock2430.c +++ b/arch/arm/mach-omap2/clock2430.c | |||
| @@ -21,9 +21,9 @@ | |||
| 21 | #include <linux/clk.h> | 21 | #include <linux/clk.h> |
| 22 | #include <linux/io.h> | 22 | #include <linux/io.h> |
| 23 | 23 | ||
| 24 | #include <plat/hardware.h> | ||
| 25 | #include <plat/clock.h> | 24 | #include <plat/clock.h> |
| 26 | 25 | ||
| 26 | #include "soc.h" | ||
| 27 | #include "iomap.h" | 27 | #include "iomap.h" |
| 28 | #include "clock.h" | 28 | #include "clock.h" |
| 29 | #include "clock2xxx.h" | 29 | #include "clock2xxx.h" |
diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c index cacabb070e22..02fe1f28affc 100644 --- a/arch/arm/mach-omap2/clock2430_data.c +++ b/arch/arm/mach-omap2/clock2430_data.c | |||
| @@ -17,9 +17,9 @@ | |||
| 17 | #include <linux/clk.h> | 17 | #include <linux/clk.h> |
| 18 | #include <linux/list.h> | 18 | #include <linux/list.h> |
| 19 | 19 | ||
| 20 | #include <plat/hardware.h> | ||
| 21 | #include <plat/clkdev_omap.h> | 20 | #include <plat/clkdev_omap.h> |
| 22 | 21 | ||
| 22 | #include "soc.h" | ||
| 23 | #include "iomap.h" | 23 | #include "iomap.h" |
| 24 | #include "clock.h" | 24 | #include "clock.h" |
| 25 | #include "clock2xxx.h" | 25 | #include "clock2xxx.h" |
diff --git a/arch/arm/mach-omap2/clock2xxx.c b/arch/arm/mach-omap2/clock2xxx.c index 12500097378d..e92be1fc1a00 100644 --- a/arch/arm/mach-omap2/clock2xxx.c +++ b/arch/arm/mach-omap2/clock2xxx.c | |||
| @@ -22,9 +22,9 @@ | |||
| 22 | #include <linux/clk.h> | 22 | #include <linux/clk.h> |
| 23 | #include <linux/io.h> | 23 | #include <linux/io.h> |
| 24 | 24 | ||
| 25 | #include <plat/cpu.h> | ||
| 26 | #include <plat/clock.h> | 25 | #include <plat/clock.h> |
| 27 | 26 | ||
| 27 | #include "soc.h" | ||
| 28 | #include "clock.h" | 28 | #include "clock.h" |
| 29 | #include "clock2xxx.h" | 29 | #include "clock2xxx.h" |
| 30 | #include "cm.h" | 30 | #include "cm.h" |
diff --git a/arch/arm/mach-omap2/clock33xx_data.c b/arch/arm/mach-omap2/clock33xx_data.c index 25bbcc7ca4dc..8e06de665b14 100644 --- a/arch/arm/mach-omap2/clock33xx_data.c +++ b/arch/arm/mach-omap2/clock33xx_data.c | |||
| @@ -18,8 +18,8 @@ | |||
| 18 | #include <linux/list.h> | 18 | #include <linux/list.h> |
| 19 | #include <linux/clk.h> | 19 | #include <linux/clk.h> |
| 20 | #include <plat/clkdev_omap.h> | 20 | #include <plat/clkdev_omap.h> |
| 21 | #include <plat/am33xx.h> | ||
| 22 | 21 | ||
| 22 | #include "am33xx.h" | ||
| 23 | #include "iomap.h" | 23 | #include "iomap.h" |
| 24 | #include "control.h" | 24 | #include "control.h" |
| 25 | #include "clock.h" | 25 | #include "clock.h" |
| @@ -1036,13 +1036,13 @@ static struct omap_clk am33xx_clks[] = { | |||
| 1036 | CLK(NULL, "mmu_fck", &mmu_fck, CK_AM33XX), | 1036 | CLK(NULL, "mmu_fck", &mmu_fck, CK_AM33XX), |
| 1037 | CLK(NULL, "smartreflex0_fck", &smartreflex0_fck, CK_AM33XX), | 1037 | CLK(NULL, "smartreflex0_fck", &smartreflex0_fck, CK_AM33XX), |
| 1038 | CLK(NULL, "smartreflex1_fck", &smartreflex1_fck, CK_AM33XX), | 1038 | CLK(NULL, "smartreflex1_fck", &smartreflex1_fck, CK_AM33XX), |
| 1039 | CLK(NULL, "gpt1_fck", &timer1_fck, CK_AM33XX), | 1039 | CLK(NULL, "timer1_fck", &timer1_fck, CK_AM33XX), |
| 1040 | CLK(NULL, "gpt2_fck", &timer2_fck, CK_AM33XX), | 1040 | CLK(NULL, "timer2_fck", &timer2_fck, CK_AM33XX), |
| 1041 | CLK(NULL, "gpt3_fck", &timer3_fck, CK_AM33XX), | 1041 | CLK(NULL, "timer3_fck", &timer3_fck, CK_AM33XX), |
| 1042 | CLK(NULL, "gpt4_fck", &timer4_fck, CK_AM33XX), | 1042 | CLK(NULL, "timer4_fck", &timer4_fck, CK_AM33XX), |
| 1043 | CLK(NULL, "gpt5_fck", &timer5_fck, CK_AM33XX), | 1043 | CLK(NULL, "timer5_fck", &timer5_fck, CK_AM33XX), |
| 1044 | CLK(NULL, "gpt6_fck", &timer6_fck, CK_AM33XX), | 1044 | CLK(NULL, "timer6_fck", &timer6_fck, CK_AM33XX), |
| 1045 | CLK(NULL, "gpt7_fck", &timer7_fck, CK_AM33XX), | 1045 | CLK(NULL, "timer7_fck", &timer7_fck, CK_AM33XX), |
| 1046 | CLK(NULL, "usbotg_fck", &usbotg_fck, CK_AM33XX), | 1046 | CLK(NULL, "usbotg_fck", &usbotg_fck, CK_AM33XX), |
| 1047 | CLK(NULL, "ieee5000_fck", &ieee5000_fck, CK_AM33XX), | 1047 | CLK(NULL, "ieee5000_fck", &ieee5000_fck, CK_AM33XX), |
| 1048 | CLK(NULL, "wdt1_fck", &wdt1_fck, CK_AM33XX), | 1048 | CLK(NULL, "wdt1_fck", &wdt1_fck, CK_AM33XX), |
diff --git a/arch/arm/mach-omap2/clock3xxx.c b/arch/arm/mach-omap2/clock3xxx.c index 794d82702c85..fc2765bcdd40 100644 --- a/arch/arm/mach-omap2/clock3xxx.c +++ b/arch/arm/mach-omap2/clock3xxx.c | |||
| @@ -21,9 +21,9 @@ | |||
| 21 | #include <linux/clk.h> | 21 | #include <linux/clk.h> |
| 22 | #include <linux/io.h> | 22 | #include <linux/io.h> |
| 23 | 23 | ||
| 24 | #include <plat/hardware.h> | ||
| 25 | #include <plat/clock.h> | 24 | #include <plat/clock.h> |
| 26 | 25 | ||
| 26 | #include "soc.h" | ||
| 27 | #include "clock.h" | 27 | #include "clock.h" |
| 28 | #include "clock3xxx.h" | 28 | #include "clock3xxx.h" |
| 29 | #include "prm2xxx_3xxx.h" | 29 | #include "prm2xxx_3xxx.h" |
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c index 83bed9ad3017..10a2398e1736 100644 --- a/arch/arm/mach-omap2/clock3xxx_data.c +++ b/arch/arm/mach-omap2/clock3xxx_data.c | |||
| @@ -21,9 +21,9 @@ | |||
| 21 | #include <linux/list.h> | 21 | #include <linux/list.h> |
| 22 | #include <linux/io.h> | 22 | #include <linux/io.h> |
| 23 | 23 | ||
| 24 | #include <plat/hardware.h> | ||
| 25 | #include <plat/clkdev_omap.h> | 24 | #include <plat/clkdev_omap.h> |
| 26 | 25 | ||
| 26 | #include "soc.h" | ||
| 27 | #include "iomap.h" | 27 | #include "iomap.h" |
| 28 | #include "clock.h" | 28 | #include "clock.h" |
| 29 | #include "clock3xxx.h" | 29 | #include "clock3xxx.h" |
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c index d7f55e43b761..500682c051c1 100644 --- a/arch/arm/mach-omap2/clock44xx_data.c +++ b/arch/arm/mach-omap2/clock44xx_data.c | |||
| @@ -28,9 +28,9 @@ | |||
| 28 | #include <linux/clk.h> | 28 | #include <linux/clk.h> |
| 29 | #include <linux/io.h> | 29 | #include <linux/io.h> |
| 30 | 30 | ||
| 31 | #include <plat/hardware.h> | ||
| 32 | #include <plat/clkdev_omap.h> | 31 | #include <plat/clkdev_omap.h> |
| 33 | 32 | ||
| 33 | #include "soc.h" | ||
| 34 | #include "iomap.h" | 34 | #include "iomap.h" |
| 35 | #include "clock.h" | 35 | #include "clock.h" |
| 36 | #include "clock44xx.h" | 36 | #include "clock44xx.h" |
diff --git a/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c b/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c index a0d68dbecfa3..f99e65cfb862 100644 --- a/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c +++ b/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c | |||
| @@ -241,6 +241,52 @@ static void omap3_clkdm_deny_idle(struct clockdomain *clkdm) | |||
| 241 | _clkdm_del_autodeps(clkdm); | 241 | _clkdm_del_autodeps(clkdm); |
| 242 | } | 242 | } |
| 243 | 243 | ||
| 244 | static int omap3xxx_clkdm_clk_enable(struct clockdomain *clkdm) | ||
| 245 | { | ||
| 246 | bool hwsup = false; | ||
| 247 | |||
| 248 | if (!clkdm->clktrctrl_mask) | ||
| 249 | return 0; | ||
| 250 | |||
| 251 | hwsup = omap2_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs, | ||
| 252 | clkdm->clktrctrl_mask); | ||
| 253 | |||
| 254 | if (hwsup) { | ||
| 255 | /* Disable HW transitions when we are changing deps */ | ||
| 256 | _disable_hwsup(clkdm); | ||
| 257 | _clkdm_add_autodeps(clkdm); | ||
| 258 | _enable_hwsup(clkdm); | ||
| 259 | } else { | ||
| 260 | if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP) | ||
| 261 | omap3_clkdm_wakeup(clkdm); | ||
| 262 | } | ||
| 263 | |||
| 264 | return 0; | ||
| 265 | } | ||
| 266 | |||
| 267 | static int omap3xxx_clkdm_clk_disable(struct clockdomain *clkdm) | ||
| 268 | { | ||
| 269 | bool hwsup = false; | ||
| 270 | |||
| 271 | if (!clkdm->clktrctrl_mask) | ||
| 272 | return 0; | ||
| 273 | |||
| 274 | hwsup = omap2_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs, | ||
| 275 | clkdm->clktrctrl_mask); | ||
| 276 | |||
| 277 | if (hwsup) { | ||
| 278 | /* Disable HW transitions when we are changing deps */ | ||
| 279 | _disable_hwsup(clkdm); | ||
| 280 | _clkdm_del_autodeps(clkdm); | ||
| 281 | _enable_hwsup(clkdm); | ||
| 282 | } else { | ||
| 283 | if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP) | ||
| 284 | omap3_clkdm_sleep(clkdm); | ||
| 285 | } | ||
| 286 | |||
| 287 | return 0; | ||
| 288 | } | ||
| 289 | |||
| 244 | struct clkdm_ops omap2_clkdm_operations = { | 290 | struct clkdm_ops omap2_clkdm_operations = { |
| 245 | .clkdm_add_wkdep = omap2_clkdm_add_wkdep, | 291 | .clkdm_add_wkdep = omap2_clkdm_add_wkdep, |
| 246 | .clkdm_del_wkdep = omap2_clkdm_del_wkdep, | 292 | .clkdm_del_wkdep = omap2_clkdm_del_wkdep, |
| @@ -267,6 +313,6 @@ struct clkdm_ops omap3_clkdm_operations = { | |||
| 267 | .clkdm_wakeup = omap3_clkdm_wakeup, | 313 | .clkdm_wakeup = omap3_clkdm_wakeup, |
| 268 | .clkdm_allow_idle = omap3_clkdm_allow_idle, | 314 | .clkdm_allow_idle = omap3_clkdm_allow_idle, |
| 269 | .clkdm_deny_idle = omap3_clkdm_deny_idle, | 315 | .clkdm_deny_idle = omap3_clkdm_deny_idle, |
| 270 | .clkdm_clk_enable = omap2_clkdm_clk_enable, | 316 | .clkdm_clk_enable = omap3xxx_clkdm_clk_enable, |
| 271 | .clkdm_clk_disable = omap2_clkdm_clk_disable, | 317 | .clkdm_clk_disable = omap3xxx_clkdm_clk_disable, |
| 272 | }; | 318 | }; |
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h index 766338fe4d34..975f6bda0e0b 100644 --- a/arch/arm/mach-omap2/cm-regbits-34xx.h +++ b/arch/arm/mach-omap2/cm-regbits-34xx.h | |||
| @@ -67,6 +67,7 @@ | |||
| 67 | #define OMAP3430_EN_IVA2_DPLL_MASK (0x7 << 0) | 67 | #define OMAP3430_EN_IVA2_DPLL_MASK (0x7 << 0) |
| 68 | 68 | ||
| 69 | /* CM_IDLEST_IVA2 */ | 69 | /* CM_IDLEST_IVA2 */ |
| 70 | #define OMAP3430_ST_IVA2_SHIFT 0 | ||
| 70 | #define OMAP3430_ST_IVA2_MASK (1 << 0) | 71 | #define OMAP3430_ST_IVA2_MASK (1 << 0) |
| 71 | 72 | ||
| 72 | /* CM_IDLEST_PLL_IVA2 */ | 73 | /* CM_IDLEST_PLL_IVA2 */ |
diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.c b/arch/arm/mach-omap2/cm2xxx_3xxx.c index 389f9f8b570c..a911e76b4ecf 100644 --- a/arch/arm/mach-omap2/cm2xxx_3xxx.c +++ b/arch/arm/mach-omap2/cm2xxx_3xxx.c | |||
| @@ -18,8 +18,7 @@ | |||
| 18 | #include <linux/err.h> | 18 | #include <linux/err.h> |
| 19 | #include <linux/io.h> | 19 | #include <linux/io.h> |
| 20 | 20 | ||
| 21 | #include <plat/hardware.h> | 21 | #include "soc.h" |
| 22 | |||
| 23 | #include "iomap.h" | 22 | #include "iomap.h" |
| 24 | #include "common.h" | 23 | #include "common.h" |
| 25 | #include "cm.h" | 24 | #include "cm.h" |
diff --git a/arch/arm/mach-omap2/common-board-devices.c b/arch/arm/mach-omap2/common-board-devices.c index c1875862679f..013fedc9e131 100644 --- a/arch/arm/mach-omap2/common-board-devices.c +++ b/arch/arm/mach-omap2/common-board-devices.c | |||
| @@ -27,6 +27,7 @@ | |||
| 27 | #include <plat/mcspi.h> | 27 | #include <plat/mcspi.h> |
| 28 | #include <plat/nand.h> | 28 | #include <plat/nand.h> |
| 29 | 29 | ||
| 30 | #include "common.h" | ||
| 30 | #include "common-board-devices.h" | 31 | #include "common-board-devices.h" |
| 31 | 32 | ||
| 32 | #if defined(CONFIG_TOUCHSCREEN_ADS7846) || \ | 33 | #if defined(CONFIG_TOUCHSCREEN_ADS7846) || \ |
diff --git a/arch/arm/mach-omap2/common.c b/arch/arm/mach-omap2/common.c index 069f9725b1c3..8e43c4d885d5 100644 --- a/arch/arm/mach-omap2/common.c +++ b/arch/arm/mach-omap2/common.c | |||
| @@ -17,11 +17,10 @@ | |||
| 17 | #include <linux/clk.h> | 17 | #include <linux/clk.h> |
| 18 | #include <linux/io.h> | 18 | #include <linux/io.h> |
| 19 | 19 | ||
| 20 | #include <plat/hardware.h> | ||
| 21 | #include <plat/board.h> | ||
| 22 | #include <plat/mux.h> | 20 | #include <plat/mux.h> |
| 23 | #include <plat/clock.h> | 21 | #include <plat/clock.h> |
| 24 | 22 | ||
| 23 | #include "soc.h" | ||
| 25 | #include "iomap.h" | 24 | #include "iomap.h" |
| 26 | #include "common.h" | 25 | #include "common.h" |
| 27 | #include "sdrc.h" | 26 | #include "sdrc.h" |
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h index 1f65b1871c23..da0f5c187353 100644 --- a/arch/arm/mach-omap2/common.h +++ b/arch/arm/mach-omap2/common.h | |||
| @@ -26,11 +26,18 @@ | |||
| 26 | #define __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H | 26 | #define __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H |
| 27 | #ifndef __ASSEMBLER__ | 27 | #ifndef __ASSEMBLER__ |
| 28 | 28 | ||
| 29 | #include <linux/irq.h> | ||
| 29 | #include <linux/delay.h> | 30 | #include <linux/delay.h> |
| 30 | #include <linux/i2c/twl.h> | 31 | #include <linux/i2c/twl.h> |
| 31 | #include <plat/common.h> | 32 | |
| 32 | #include <asm/proc-fns.h> | 33 | #include <asm/proc-fns.h> |
| 33 | 34 | ||
| 35 | #include <plat/cpu.h> | ||
| 36 | #include <plat/serial.h> | ||
| 37 | #include <plat/common.h> | ||
| 38 | |||
| 39 | #define OMAP_INTC_START NR_IRQS | ||
| 40 | |||
| 34 | #ifdef CONFIG_SOC_OMAP2420 | 41 | #ifdef CONFIG_SOC_OMAP2420 |
| 35 | extern void omap242x_map_common_io(void); | 42 | extern void omap242x_map_common_io(void); |
| 36 | #else | 43 | #else |
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c index 3223b81e7532..d1ff8399a222 100644 --- a/arch/arm/mach-omap2/control.c +++ b/arch/arm/mach-omap2/control.c | |||
| @@ -15,9 +15,9 @@ | |||
| 15 | #include <linux/kernel.h> | 15 | #include <linux/kernel.h> |
| 16 | #include <linux/io.h> | 16 | #include <linux/io.h> |
| 17 | 17 | ||
| 18 | #include <plat/hardware.h> | ||
| 19 | #include <plat/sdrc.h> | 18 | #include <plat/sdrc.h> |
| 20 | 19 | ||
| 20 | #include "soc.h" | ||
| 21 | #include "iomap.h" | 21 | #include "iomap.h" |
| 22 | #include "common.h" | 22 | #include "common.h" |
| 23 | #include "cm-regbits-34xx.h" | 23 | #include "cm-regbits-34xx.h" |
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h index b8cdc8531b60..c1a5cab0f236 100644 --- a/arch/arm/mach-omap2/control.h +++ b/arch/arm/mach-omap2/control.h | |||
| @@ -21,7 +21,7 @@ | |||
| 21 | #include <mach/ctrl_module_pad_core_44xx.h> | 21 | #include <mach/ctrl_module_pad_core_44xx.h> |
| 22 | #include <mach/ctrl_module_pad_wkup_44xx.h> | 22 | #include <mach/ctrl_module_pad_wkup_44xx.h> |
| 23 | 23 | ||
| 24 | #include <plat/am33xx.h> | 24 | #include "am33xx.h" |
| 25 | 25 | ||
| 26 | #ifndef __ASSEMBLY__ | 26 | #ifndef __ASSEMBLY__ |
| 27 | #define OMAP242X_CTRL_REGADDR(reg) \ | 27 | #define OMAP242X_CTRL_REGADDR(reg) \ |
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c index f2a49a48ef59..bc2756959be5 100644 --- a/arch/arm/mach-omap2/cpuidle34xx.c +++ b/arch/arm/mach-omap2/cpuidle34xx.c | |||
| @@ -28,7 +28,6 @@ | |||
| 28 | #include <linux/cpu_pm.h> | 28 | #include <linux/cpu_pm.h> |
| 29 | 29 | ||
| 30 | #include <plat/prcm.h> | 30 | #include <plat/prcm.h> |
| 31 | #include <plat/irqs.h> | ||
| 32 | #include "powerdomain.h" | 31 | #include "powerdomain.h" |
| 33 | #include "clockdomain.h" | 32 | #include "clockdomain.h" |
| 34 | 33 | ||
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index c00c68961bb8..1efa984b1a47 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c | |||
| @@ -19,19 +19,18 @@ | |||
| 19 | #include <linux/of.h> | 19 | #include <linux/of.h> |
| 20 | #include <linux/platform_data/omap4-keypad.h> | 20 | #include <linux/platform_data/omap4-keypad.h> |
| 21 | 21 | ||
| 22 | #include <mach/hardware.h> | ||
| 23 | #include <mach/irqs.h> | ||
| 24 | #include <asm/mach-types.h> | 22 | #include <asm/mach-types.h> |
| 25 | #include <asm/mach/map.h> | 23 | #include <asm/mach/map.h> |
| 26 | #include <asm/pmu.h> | 24 | #include <asm/pmu.h> |
| 27 | 25 | ||
| 28 | #include "iomap.h" | 26 | #include "iomap.h" |
| 29 | #include <plat/board.h> | ||
| 30 | #include <plat/dma.h> | 27 | #include <plat/dma.h> |
| 31 | #include <plat/omap_hwmod.h> | 28 | #include <plat/omap_hwmod.h> |
| 32 | #include <plat/omap_device.h> | 29 | #include <plat/omap_device.h> |
| 33 | #include <plat/omap4-keypad.h> | 30 | #include <plat/omap4-keypad.h> |
| 34 | 31 | ||
| 32 | #include "soc.h" | ||
| 33 | #include "common.h" | ||
| 35 | #include "mux.h" | 34 | #include "mux.h" |
| 36 | #include "control.h" | 35 | #include "control.h" |
| 37 | #include "devices.h" | 36 | #include "devices.h" |
| @@ -112,7 +111,7 @@ static struct resource omap2cam_resources[] = { | |||
| 112 | .flags = IORESOURCE_MEM, | 111 | .flags = IORESOURCE_MEM, |
| 113 | }, | 112 | }, |
| 114 | { | 113 | { |
| 115 | .start = INT_24XX_CAM_IRQ, | 114 | .start = 24 + OMAP_INTC_START, |
| 116 | .flags = IORESOURCE_IRQ, | 115 | .flags = IORESOURCE_IRQ, |
| 117 | } | 116 | } |
| 118 | }; | 117 | }; |
| @@ -201,7 +200,7 @@ static struct resource omap3isp_resources[] = { | |||
| 201 | .flags = IORESOURCE_MEM, | 200 | .flags = IORESOURCE_MEM, |
| 202 | }, | 201 | }, |
| 203 | { | 202 | { |
| 204 | .start = INT_34XX_CAM_IRQ, | 203 | .start = 24 + OMAP_INTC_START, |
| 205 | .flags = IORESOURCE_IRQ, | 204 | .flags = IORESOURCE_IRQ, |
| 206 | } | 205 | } |
| 207 | }; | 206 | }; |
| @@ -435,14 +434,12 @@ static inline void omap_init_mcspi(void) {} | |||
| 435 | #endif | 434 | #endif |
| 436 | 435 | ||
| 437 | static struct resource omap2_pmu_resource = { | 436 | static struct resource omap2_pmu_resource = { |
| 438 | .start = 3, | 437 | .start = 3 + OMAP_INTC_START, |
| 439 | .end = 3, | ||
| 440 | .flags = IORESOURCE_IRQ, | 438 | .flags = IORESOURCE_IRQ, |
| 441 | }; | 439 | }; |
| 442 | 440 | ||
| 443 | static struct resource omap3_pmu_resource = { | 441 | static struct resource omap3_pmu_resource = { |
| 444 | .start = INT_34XX_BENCH_MPU_EMUL, | 442 | .start = 3 + OMAP_INTC_START, |
| 445 | .end = INT_34XX_BENCH_MPU_EMUL, | ||
| 446 | .flags = IORESOURCE_IRQ, | 443 | .flags = IORESOURCE_IRQ, |
| 447 | }; | 444 | }; |
| 448 | 445 | ||
| @@ -475,7 +472,7 @@ static struct resource omap2_sham_resources[] = { | |||
| 475 | .flags = IORESOURCE_MEM, | 472 | .flags = IORESOURCE_MEM, |
| 476 | }, | 473 | }, |
| 477 | { | 474 | { |
| 478 | .start = INT_24XX_SHA1MD5, | 475 | .start = 51 + OMAP_INTC_START, |
| 479 | .flags = IORESOURCE_IRQ, | 476 | .flags = IORESOURCE_IRQ, |
| 480 | } | 477 | } |
| 481 | }; | 478 | }; |
| @@ -493,7 +490,7 @@ static struct resource omap3_sham_resources[] = { | |||
| 493 | .flags = IORESOURCE_MEM, | 490 | .flags = IORESOURCE_MEM, |
| 494 | }, | 491 | }, |
| 495 | { | 492 | { |
| 496 | .start = INT_34XX_SHA1MD52_IRQ, | 493 | .start = 49 + OMAP_INTC_START, |
| 497 | .flags = IORESOURCE_IRQ, | 494 | .flags = IORESOURCE_IRQ, |
| 498 | }, | 495 | }, |
| 499 | { | 496 | { |
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c index b9c8d2f6a81f..d8318dc5ee91 100644 --- a/arch/arm/mach-omap2/dpll3xxx.c +++ b/arch/arm/mach-omap2/dpll3xxx.c | |||
| @@ -28,9 +28,9 @@ | |||
| 28 | #include <linux/bitops.h> | 28 | #include <linux/bitops.h> |
| 29 | #include <linux/clkdev.h> | 29 | #include <linux/clkdev.h> |
| 30 | 30 | ||
| 31 | #include <plat/cpu.h> | ||
| 32 | #include <plat/clock.h> | 31 | #include <plat/clock.h> |
| 33 | 32 | ||
| 33 | #include "soc.h" | ||
| 34 | #include "clock.h" | 34 | #include "clock.h" |
| 35 | #include "cm2xxx_3xxx.h" | 35 | #include "cm2xxx_3xxx.h" |
| 36 | #include "cm-regbits-34xx.h" | 36 | #include "cm-regbits-34xx.h" |
diff --git a/arch/arm/mach-omap2/dpll44xx.c b/arch/arm/mach-omap2/dpll44xx.c index 9c6a296b3dc3..09d0ccccb861 100644 --- a/arch/arm/mach-omap2/dpll44xx.c +++ b/arch/arm/mach-omap2/dpll44xx.c | |||
| @@ -15,9 +15,9 @@ | |||
| 15 | #include <linux/io.h> | 15 | #include <linux/io.h> |
| 16 | #include <linux/bitops.h> | 16 | #include <linux/bitops.h> |
| 17 | 17 | ||
| 18 | #include <plat/cpu.h> | ||
| 19 | #include <plat/clock.h> | 18 | #include <plat/clock.h> |
| 20 | 19 | ||
| 20 | #include "soc.h" | ||
| 21 | #include "clock.h" | 21 | #include "clock.h" |
| 22 | #include "clock44xx.h" | 22 | #include "clock44xx.h" |
| 23 | #include "cm-regbits-44xx.h" | 23 | #include "cm-regbits-44xx.h" |
diff --git a/arch/arm/mach-omap2/emu.c b/arch/arm/mach-omap2/emu.c index e28e761b7ab9..b3566f68a559 100644 --- a/arch/arm/mach-omap2/emu.c +++ b/arch/arm/mach-omap2/emu.c | |||
| @@ -21,8 +21,7 @@ | |||
| 21 | #include <linux/clk.h> | 21 | #include <linux/clk.h> |
| 22 | #include <linux/err.h> | 22 | #include <linux/err.h> |
| 23 | 23 | ||
| 24 | #include <mach/hardware.h> | 24 | #include "soc.h" |
| 25 | |||
| 26 | #include "iomap.h" | 25 | #include "iomap.h" |
| 27 | 26 | ||
| 28 | MODULE_LICENSE("GPL"); | 27 | MODULE_LICENSE("GPL"); |
diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c index 9ad7d489b0de..7b52bdfc59c9 100644 --- a/arch/arm/mach-omap2/gpio.c +++ b/arch/arm/mach-omap2/gpio.c | |||
| @@ -21,6 +21,7 @@ | |||
| 21 | #include <linux/slab.h> | 21 | #include <linux/slab.h> |
| 22 | #include <linux/interrupt.h> | 22 | #include <linux/interrupt.h> |
| 23 | #include <linux/of.h> | 23 | #include <linux/of.h> |
| 24 | #include <linux/platform_data/gpio-omap.h> | ||
| 24 | 25 | ||
| 25 | #include <plat/omap_hwmod.h> | 26 | #include <plat/omap_hwmod.h> |
| 26 | #include <plat/omap_device.h> | 27 | #include <plat/omap_device.h> |
diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c index 386dec8d2351..9e9f47ad6187 100644 --- a/arch/arm/mach-omap2/gpmc-nand.c +++ b/arch/arm/mach-omap2/gpmc-nand.c | |||
| @@ -16,20 +16,28 @@ | |||
| 16 | 16 | ||
| 17 | #include <asm/mach/flash.h> | 17 | #include <asm/mach/flash.h> |
| 18 | 18 | ||
| 19 | #include <plat/cpu.h> | ||
| 20 | #include <plat/nand.h> | 19 | #include <plat/nand.h> |
| 21 | #include <plat/board.h> | ||
| 22 | #include <plat/gpmc.h> | 20 | #include <plat/gpmc.h> |
| 23 | 21 | ||
| 24 | static struct resource gpmc_nand_resource = { | 22 | #include "soc.h" |
| 25 | .flags = IORESOURCE_MEM, | 23 | |
| 24 | static struct resource gpmc_nand_resource[] = { | ||
| 25 | { | ||
| 26 | .flags = IORESOURCE_MEM, | ||
| 27 | }, | ||
| 28 | { | ||
| 29 | .flags = IORESOURCE_IRQ, | ||
| 30 | }, | ||
| 31 | { | ||
| 32 | .flags = IORESOURCE_IRQ, | ||
| 33 | }, | ||
| 26 | }; | 34 | }; |
| 27 | 35 | ||
| 28 | static struct platform_device gpmc_nand_device = { | 36 | static struct platform_device gpmc_nand_device = { |
| 29 | .name = "omap2-nand", | 37 | .name = "omap2-nand", |
| 30 | .id = 0, | 38 | .id = 0, |
| 31 | .num_resources = 1, | 39 | .num_resources = ARRAY_SIZE(gpmc_nand_resource), |
| 32 | .resource = &gpmc_nand_resource, | 40 | .resource = gpmc_nand_resource, |
| 33 | }; | 41 | }; |
| 34 | 42 | ||
| 35 | static int omap2_nand_gpmc_retime(struct omap_nand_platform_data *gpmc_nand_data) | 43 | static int omap2_nand_gpmc_retime(struct omap_nand_platform_data *gpmc_nand_data) |
| @@ -75,6 +83,7 @@ static int omap2_nand_gpmc_retime(struct omap_nand_platform_data *gpmc_nand_data | |||
| 75 | gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_DEV_SIZE, 0); | 83 | gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_DEV_SIZE, 0); |
| 76 | gpmc_cs_configure(gpmc_nand_data->cs, | 84 | gpmc_cs_configure(gpmc_nand_data->cs, |
| 77 | GPMC_CONFIG_DEV_TYPE, GPMC_DEVICETYPE_NAND); | 85 | GPMC_CONFIG_DEV_TYPE, GPMC_DEVICETYPE_NAND); |
| 86 | gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_WP, 0); | ||
| 78 | err = gpmc_cs_set_timings(gpmc_nand_data->cs, &t); | 87 | err = gpmc_cs_set_timings(gpmc_nand_data->cs, &t); |
| 79 | if (err) | 88 | if (err) |
| 80 | return err; | 89 | return err; |
| @@ -90,12 +99,19 @@ int __init gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data) | |||
| 90 | gpmc_nand_device.dev.platform_data = gpmc_nand_data; | 99 | gpmc_nand_device.dev.platform_data = gpmc_nand_data; |
| 91 | 100 | ||
| 92 | err = gpmc_cs_request(gpmc_nand_data->cs, NAND_IO_SIZE, | 101 | err = gpmc_cs_request(gpmc_nand_data->cs, NAND_IO_SIZE, |
| 93 | &gpmc_nand_data->phys_base); | 102 | (unsigned long *)&gpmc_nand_resource[0].start); |
| 94 | if (err < 0) { | 103 | if (err < 0) { |
| 95 | dev_err(dev, "Cannot request GPMC CS\n"); | 104 | dev_err(dev, "Cannot request GPMC CS\n"); |
| 96 | return err; | 105 | return err; |
| 97 | } | 106 | } |
| 98 | 107 | ||
| 108 | gpmc_nand_resource[0].end = gpmc_nand_resource[0].start + | ||
| 109 | NAND_IO_SIZE - 1; | ||
| 110 | |||
| 111 | gpmc_nand_resource[1].start = | ||
| 112 | gpmc_get_client_irq(GPMC_IRQ_FIFOEVENTENABLE); | ||
| 113 | gpmc_nand_resource[2].start = | ||
| 114 | gpmc_get_client_irq(GPMC_IRQ_COUNT_EVENT); | ||
| 99 | /* Set timings in GPMC */ | 115 | /* Set timings in GPMC */ |
| 100 | err = omap2_nand_gpmc_retime(gpmc_nand_data); | 116 | err = omap2_nand_gpmc_retime(gpmc_nand_data); |
| 101 | if (err < 0) { | 117 | if (err < 0) { |
| @@ -108,6 +124,8 @@ int __init gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data) | |||
| 108 | gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_RDY_BSY, 1); | 124 | gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_RDY_BSY, 1); |
| 109 | } | 125 | } |
| 110 | 126 | ||
| 127 | gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs); | ||
| 128 | |||
| 111 | err = platform_device_register(&gpmc_nand_device); | 129 | err = platform_device_register(&gpmc_nand_device); |
| 112 | if (err < 0) { | 130 | if (err < 0) { |
| 113 | dev_err(dev, "Unable to register NAND device\n"); | 131 | dev_err(dev, "Unable to register NAND device\n"); |
diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c index a0fa9bb2bda5..b66fb8e5faaa 100644 --- a/arch/arm/mach-omap2/gpmc-onenand.c +++ b/arch/arm/mach-omap2/gpmc-onenand.c | |||
| @@ -18,16 +18,24 @@ | |||
| 18 | 18 | ||
| 19 | #include <asm/mach/flash.h> | 19 | #include <asm/mach/flash.h> |
| 20 | 20 | ||
| 21 | #include <plat/cpu.h> | ||
| 22 | #include <plat/onenand.h> | 21 | #include <plat/onenand.h> |
| 23 | #include <plat/board.h> | ||
| 24 | #include <plat/gpmc.h> | 22 | #include <plat/gpmc.h> |
| 25 | 23 | ||
| 24 | #include "soc.h" | ||
| 25 | |||
| 26 | #define ONENAND_IO_SIZE SZ_128K | ||
| 27 | |||
| 26 | static struct omap_onenand_platform_data *gpmc_onenand_data; | 28 | static struct omap_onenand_platform_data *gpmc_onenand_data; |
| 27 | 29 | ||
| 30 | static struct resource gpmc_onenand_resource = { | ||
| 31 | .flags = IORESOURCE_MEM, | ||
| 32 | }; | ||
| 33 | |||
| 28 | static struct platform_device gpmc_onenand_device = { | 34 | static struct platform_device gpmc_onenand_device = { |
| 29 | .name = "omap2-onenand", | 35 | .name = "omap2-onenand", |
| 30 | .id = -1, | 36 | .id = -1, |
| 37 | .num_resources = 1, | ||
| 38 | .resource = &gpmc_onenand_resource, | ||
| 31 | }; | 39 | }; |
| 32 | 40 | ||
| 33 | static int omap2_onenand_set_async_mode(int cs, void __iomem *onenand_base) | 41 | static int omap2_onenand_set_async_mode(int cs, void __iomem *onenand_base) |
| @@ -390,6 +398,8 @@ static int gpmc_onenand_setup(void __iomem *onenand_base, int *freq_ptr) | |||
| 390 | 398 | ||
| 391 | void __init gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data) | 399 | void __init gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data) |
| 392 | { | 400 | { |
| 401 | int err; | ||
| 402 | |||
| 393 | gpmc_onenand_data = _onenand_data; | 403 | gpmc_onenand_data = _onenand_data; |
| 394 | gpmc_onenand_data->onenand_setup = gpmc_onenand_setup; | 404 | gpmc_onenand_data->onenand_setup = gpmc_onenand_setup; |
| 395 | gpmc_onenand_device.dev.platform_data = gpmc_onenand_data; | 405 | gpmc_onenand_device.dev.platform_data = gpmc_onenand_data; |
| @@ -401,8 +411,19 @@ void __init gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data) | |||
| 401 | gpmc_onenand_data->flags |= ONENAND_SYNC_READ; | 411 | gpmc_onenand_data->flags |= ONENAND_SYNC_READ; |
| 402 | } | 412 | } |
| 403 | 413 | ||
| 414 | err = gpmc_cs_request(gpmc_onenand_data->cs, ONENAND_IO_SIZE, | ||
| 415 | (unsigned long *)&gpmc_onenand_resource.start); | ||
| 416 | if (err < 0) { | ||
| 417 | pr_err("%s: Cannot request GPMC CS\n", __func__); | ||
| 418 | return; | ||
| 419 | } | ||
| 420 | |||
| 421 | gpmc_onenand_resource.end = gpmc_onenand_resource.start + | ||
| 422 | ONENAND_IO_SIZE - 1; | ||
| 423 | |||
| 404 | if (platform_device_register(&gpmc_onenand_device) < 0) { | 424 | if (platform_device_register(&gpmc_onenand_device) < 0) { |
| 405 | printk(KERN_ERR "Unable to register OneNAND device\n"); | 425 | pr_err("%s: Unable to register OneNAND device\n", __func__); |
| 426 | gpmc_cs_free(gpmc_onenand_data->cs); | ||
| 406 | return; | 427 | return; |
| 407 | } | 428 | } |
| 408 | } | 429 | } |
diff --git a/arch/arm/mach-omap2/gpmc-smc91x.c b/arch/arm/mach-omap2/gpmc-smc91x.c index ba10c24f3d8d..245839dfc722 100644 --- a/arch/arm/mach-omap2/gpmc-smc91x.c +++ b/arch/arm/mach-omap2/gpmc-smc91x.c | |||
| @@ -17,10 +17,11 @@ | |||
| 17 | #include <linux/io.h> | 17 | #include <linux/io.h> |
| 18 | #include <linux/smc91x.h> | 18 | #include <linux/smc91x.h> |
| 19 | 19 | ||
| 20 | #include <plat/board.h> | ||
| 21 | #include <plat/gpmc.h> | 20 | #include <plat/gpmc.h> |
| 22 | #include <plat/gpmc-smc91x.h> | 21 | #include <plat/gpmc-smc91x.h> |
| 23 | 22 | ||
| 23 | #include "soc.h" | ||
| 24 | |||
| 24 | static struct omap_smc91x_platform_data *gpmc_cfg; | 25 | static struct omap_smc91x_platform_data *gpmc_cfg; |
| 25 | 26 | ||
| 26 | static struct resource gpmc_smc91x_resources[] = { | 27 | static struct resource gpmc_smc91x_resources[] = { |
diff --git a/arch/arm/mach-omap2/gpmc-smsc911x.c b/arch/arm/mach-omap2/gpmc-smsc911x.c index b6c77be3e8f7..a3a28878f0c9 100644 --- a/arch/arm/mach-omap2/gpmc-smsc911x.c +++ b/arch/arm/mach-omap2/gpmc-smsc911x.c | |||
| @@ -20,7 +20,6 @@ | |||
| 20 | #include <linux/io.h> | 20 | #include <linux/io.h> |
| 21 | #include <linux/smsc911x.h> | 21 | #include <linux/smsc911x.h> |
| 22 | 22 | ||
| 23 | #include <plat/board.h> | ||
| 24 | #include <plat/gpmc.h> | 23 | #include <plat/gpmc.h> |
| 25 | #include <plat/gpmc-smsc911x.h> | 24 | #include <plat/gpmc-smsc911x.h> |
| 26 | 25 | ||
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c index b2b5759ab0fe..055ae8bd943f 100644 --- a/arch/arm/mach-omap2/gpmc.c +++ b/arch/arm/mach-omap2/gpmc.c | |||
| @@ -28,8 +28,13 @@ | |||
| 28 | #include <asm/mach-types.h> | 28 | #include <asm/mach-types.h> |
| 29 | #include <plat/gpmc.h> | 29 | #include <plat/gpmc.h> |
| 30 | 30 | ||
| 31 | #include <plat/cpu.h> | ||
| 32 | #include <plat/gpmc.h> | ||
| 31 | #include <plat/sdrc.h> | 33 | #include <plat/sdrc.h> |
| 32 | 34 | ||
| 35 | #include "soc.h" | ||
| 36 | #include "common.h" | ||
| 37 | |||
| 33 | /* GPMC register offsets */ | 38 | /* GPMC register offsets */ |
| 34 | #define GPMC_REVISION 0x00 | 39 | #define GPMC_REVISION 0x00 |
| 35 | #define GPMC_SYSCONFIG 0x10 | 40 | #define GPMC_SYSCONFIG 0x10 |
| @@ -78,6 +83,15 @@ | |||
| 78 | #define ENABLE_PREFETCH (0x1 << 7) | 83 | #define ENABLE_PREFETCH (0x1 << 7) |
| 79 | #define DMA_MPU_MODE 2 | 84 | #define DMA_MPU_MODE 2 |
| 80 | 85 | ||
| 86 | /* XXX: Only NAND irq has been considered,currently these are the only ones used | ||
| 87 | */ | ||
| 88 | #define GPMC_NR_IRQ 2 | ||
| 89 | |||
| 90 | struct gpmc_client_irq { | ||
| 91 | unsigned irq; | ||
| 92 | u32 bitmask; | ||
| 93 | }; | ||
| 94 | |||
| 81 | /* Structure to save gpmc cs context */ | 95 | /* Structure to save gpmc cs context */ |
| 82 | struct gpmc_cs_config { | 96 | struct gpmc_cs_config { |
| 83 | u32 config1; | 97 | u32 config1; |
| @@ -105,6 +119,10 @@ struct omap3_gpmc_regs { | |||
| 105 | struct gpmc_cs_config cs_context[GPMC_CS_NUM]; | 119 | struct gpmc_cs_config cs_context[GPMC_CS_NUM]; |
| 106 | }; | 120 | }; |
| 107 | 121 | ||
| 122 | static struct gpmc_client_irq gpmc_client_irq[GPMC_NR_IRQ]; | ||
| 123 | static struct irq_chip gpmc_irq_chip; | ||
| 124 | static unsigned gpmc_irq_start; | ||
| 125 | |||
| 108 | static struct resource gpmc_mem_root; | 126 | static struct resource gpmc_mem_root; |
| 109 | static struct resource gpmc_cs_mem[GPMC_CS_NUM]; | 127 | static struct resource gpmc_cs_mem[GPMC_CS_NUM]; |
| 110 | static DEFINE_SPINLOCK(gpmc_mem_lock); | 128 | static DEFINE_SPINLOCK(gpmc_mem_lock); |
| @@ -682,6 +700,117 @@ int gpmc_prefetch_reset(int cs) | |||
| 682 | } | 700 | } |
| 683 | EXPORT_SYMBOL(gpmc_prefetch_reset); | 701 | EXPORT_SYMBOL(gpmc_prefetch_reset); |
| 684 | 702 | ||
| 703 | void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs) | ||
| 704 | { | ||
| 705 | reg->gpmc_status = gpmc_base + GPMC_STATUS; | ||
| 706 | reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET + | ||
| 707 | GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs; | ||
| 708 | reg->gpmc_nand_address = gpmc_base + GPMC_CS0_OFFSET + | ||
| 709 | GPMC_CS_NAND_ADDRESS + GPMC_CS_SIZE * cs; | ||
| 710 | reg->gpmc_nand_data = gpmc_base + GPMC_CS0_OFFSET + | ||
| 711 | GPMC_CS_NAND_DATA + GPMC_CS_SIZE * cs; | ||
| 712 | reg->gpmc_prefetch_config1 = gpmc_base + GPMC_PREFETCH_CONFIG1; | ||
| 713 | reg->gpmc_prefetch_config2 = gpmc_base + GPMC_PREFETCH_CONFIG2; | ||
| 714 | reg->gpmc_prefetch_control = gpmc_base + GPMC_PREFETCH_CONTROL; | ||
| 715 | reg->gpmc_prefetch_status = gpmc_base + GPMC_PREFETCH_STATUS; | ||
| 716 | reg->gpmc_ecc_config = gpmc_base + GPMC_ECC_CONFIG; | ||
| 717 | reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL; | ||
| 718 | reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG; | ||
| 719 | reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT; | ||
| 720 | reg->gpmc_bch_result0 = gpmc_base + GPMC_ECC_BCH_RESULT_0; | ||
| 721 | } | ||
| 722 | |||
| 723 | int gpmc_get_client_irq(unsigned irq_config) | ||
| 724 | { | ||
| 725 | int i; | ||
| 726 | |||
| 727 | if (hweight32(irq_config) > 1) | ||
| 728 | return 0; | ||
| 729 | |||
| 730 | for (i = 0; i < GPMC_NR_IRQ; i++) | ||
| 731 | if (gpmc_client_irq[i].bitmask & irq_config) | ||
| 732 | return gpmc_client_irq[i].irq; | ||
| 733 | |||
| 734 | return 0; | ||
| 735 | } | ||
| 736 | |||
| 737 | static int gpmc_irq_endis(unsigned irq, bool endis) | ||
| 738 | { | ||
| 739 | int i; | ||
| 740 | u32 regval; | ||
| 741 | |||
| 742 | for (i = 0; i < GPMC_NR_IRQ; i++) | ||
| 743 | if (irq == gpmc_client_irq[i].irq) { | ||
| 744 | regval = gpmc_read_reg(GPMC_IRQENABLE); | ||
| 745 | if (endis) | ||
| 746 | regval |= gpmc_client_irq[i].bitmask; | ||
| 747 | else | ||
| 748 | regval &= ~gpmc_client_irq[i].bitmask; | ||
| 749 | gpmc_write_reg(GPMC_IRQENABLE, regval); | ||
| 750 | break; | ||
| 751 | } | ||
| 752 | |||
| 753 | return 0; | ||
| 754 | } | ||
| 755 | |||
| 756 | static void gpmc_irq_disable(struct irq_data *p) | ||
| 757 | { | ||
| 758 | gpmc_irq_endis(p->irq, false); | ||
| 759 | } | ||
| 760 | |||
| 761 | static void gpmc_irq_enable(struct irq_data *p) | ||
| 762 | { | ||
| 763 | gpmc_irq_endis(p->irq, true); | ||
| 764 | } | ||
| 765 | |||
| 766 | static void gpmc_irq_noop(struct irq_data *data) { } | ||
| 767 | |||
| 768 | static unsigned int gpmc_irq_noop_ret(struct irq_data *data) { return 0; } | ||
| 769 | |||
| 770 | static int gpmc_setup_irq(int gpmc_irq) | ||
| 771 | { | ||
| 772 | int i; | ||
| 773 | u32 regval; | ||
| 774 | |||
| 775 | if (!gpmc_irq) | ||
| 776 | return -EINVAL; | ||
| 777 | |||
| 778 | gpmc_irq_start = irq_alloc_descs(-1, 0, GPMC_NR_IRQ, 0); | ||
| 779 | if (IS_ERR_VALUE(gpmc_irq_start)) { | ||
| 780 | pr_err("irq_alloc_descs failed\n"); | ||
| 781 | return gpmc_irq_start; | ||
| 782 | } | ||
| 783 | |||
| 784 | gpmc_irq_chip.name = "gpmc"; | ||
| 785 | gpmc_irq_chip.irq_startup = gpmc_irq_noop_ret; | ||
| 786 | gpmc_irq_chip.irq_enable = gpmc_irq_enable; | ||
| 787 | gpmc_irq_chip.irq_disable = gpmc_irq_disable; | ||
| 788 | gpmc_irq_chip.irq_shutdown = gpmc_irq_noop; | ||
| 789 | gpmc_irq_chip.irq_ack = gpmc_irq_noop; | ||
| 790 | gpmc_irq_chip.irq_mask = gpmc_irq_noop; | ||
| 791 | gpmc_irq_chip.irq_unmask = gpmc_irq_noop; | ||
| 792 | |||
| 793 | gpmc_client_irq[0].bitmask = GPMC_IRQ_FIFOEVENTENABLE; | ||
| 794 | gpmc_client_irq[1].bitmask = GPMC_IRQ_COUNT_EVENT; | ||
| 795 | |||
| 796 | for (i = 0; i < GPMC_NR_IRQ; i++) { | ||
| 797 | gpmc_client_irq[i].irq = gpmc_irq_start + i; | ||
| 798 | irq_set_chip_and_handler(gpmc_client_irq[i].irq, | ||
| 799 | &gpmc_irq_chip, handle_simple_irq); | ||
| 800 | set_irq_flags(gpmc_client_irq[i].irq, | ||
| 801 | IRQF_VALID | IRQF_NOAUTOEN); | ||
| 802 | } | ||
| 803 | |||
| 804 | /* Disable interrupts */ | ||
| 805 | gpmc_write_reg(GPMC_IRQENABLE, 0); | ||
| 806 | |||
| 807 | /* clear interrupts */ | ||
| 808 | regval = gpmc_read_reg(GPMC_IRQSTATUS); | ||
| 809 | gpmc_write_reg(GPMC_IRQSTATUS, regval); | ||
| 810 | |||
| 811 | return request_irq(gpmc_irq, gpmc_handle_irq, 0, "gpmc", NULL); | ||
| 812 | } | ||
| 813 | |||
| 685 | static void __init gpmc_mem_init(void) | 814 | static void __init gpmc_mem_init(void) |
| 686 | { | 815 | { |
| 687 | int cs; | 816 | int cs; |
| @@ -711,8 +840,8 @@ static void __init gpmc_mem_init(void) | |||
| 711 | 840 | ||
| 712 | static int __init gpmc_init(void) | 841 | static int __init gpmc_init(void) |
| 713 | { | 842 | { |
| 714 | u32 l, irq; | 843 | u32 l; |
| 715 | int cs, ret = -EINVAL; | 844 | int ret = -EINVAL; |
| 716 | int gpmc_irq; | 845 | int gpmc_irq; |
| 717 | char *ck = NULL; | 846 | char *ck = NULL; |
| 718 | 847 | ||
| @@ -722,16 +851,16 @@ static int __init gpmc_init(void) | |||
| 722 | l = OMAP2420_GPMC_BASE; | 851 | l = OMAP2420_GPMC_BASE; |
| 723 | else | 852 | else |
| 724 | l = OMAP34XX_GPMC_BASE; | 853 | l = OMAP34XX_GPMC_BASE; |
| 725 | gpmc_irq = INT_34XX_GPMC_IRQ; | 854 | gpmc_irq = 20 + OMAP_INTC_START; |
| 726 | } else if (cpu_is_omap34xx()) { | 855 | } else if (cpu_is_omap34xx()) { |
| 727 | ck = "gpmc_fck"; | 856 | ck = "gpmc_fck"; |
| 728 | l = OMAP34XX_GPMC_BASE; | 857 | l = OMAP34XX_GPMC_BASE; |
| 729 | gpmc_irq = INT_34XX_GPMC_IRQ; | 858 | gpmc_irq = 20 + OMAP_INTC_START; |
| 730 | } else if (cpu_is_omap44xx() || soc_is_omap54xx()) { | 859 | } else if (cpu_is_omap44xx() || soc_is_omap54xx()) { |
| 731 | /* Base address and irq number are same for OMAP4/5 */ | 860 | /* Base address and irq number are same for OMAP4/5 */ |
| 732 | ck = "gpmc_ck"; | 861 | ck = "gpmc_ck"; |
| 733 | l = OMAP44XX_GPMC_BASE; | 862 | l = OMAP44XX_GPMC_BASE; |
| 734 | gpmc_irq = OMAP44XX_IRQ_GPMC; | 863 | gpmc_irq = 20 + OMAP44XX_IRQ_GIC_START; |
| 735 | } | 864 | } |
| 736 | 865 | ||
| 737 | if (WARN_ON(!ck)) | 866 | if (WARN_ON(!ck)) |
| @@ -761,16 +890,7 @@ static int __init gpmc_init(void) | |||
| 761 | gpmc_write_reg(GPMC_SYSCONFIG, l); | 890 | gpmc_write_reg(GPMC_SYSCONFIG, l); |
| 762 | gpmc_mem_init(); | 891 | gpmc_mem_init(); |
| 763 | 892 | ||
| 764 | /* initalize the irq_chained */ | 893 | ret = gpmc_setup_irq(gpmc_irq); |
| 765 | irq = OMAP_GPMC_IRQ_BASE; | ||
| 766 | for (cs = 0; cs < GPMC_CS_NUM; cs++) { | ||
| 767 | irq_set_chip_and_handler(irq, &dummy_irq_chip, | ||
| 768 | handle_simple_irq); | ||
| 769 | set_irq_flags(irq, IRQF_VALID); | ||
| 770 | irq++; | ||
| 771 | } | ||
| 772 | |||
| 773 | ret = request_irq(gpmc_irq, gpmc_handle_irq, IRQF_SHARED, "gpmc", NULL); | ||
| 774 | if (ret) | 894 | if (ret) |
| 775 | pr_err("gpmc: irq-%d could not claim: err %d\n", | 895 | pr_err("gpmc: irq-%d could not claim: err %d\n", |
| 776 | gpmc_irq, ret); | 896 | gpmc_irq, ret); |
| @@ -780,12 +900,19 @@ postcore_initcall(gpmc_init); | |||
| 780 | 900 | ||
| 781 | static irqreturn_t gpmc_handle_irq(int irq, void *dev) | 901 | static irqreturn_t gpmc_handle_irq(int irq, void *dev) |
| 782 | { | 902 | { |
| 783 | u8 cs; | 903 | int i; |
| 904 | u32 regval; | ||
| 905 | |||
| 906 | regval = gpmc_read_reg(GPMC_IRQSTATUS); | ||
| 907 | |||
| 908 | if (!regval) | ||
| 909 | return IRQ_NONE; | ||
| 910 | |||
| 911 | for (i = 0; i < GPMC_NR_IRQ; i++) | ||
| 912 | if (regval & gpmc_client_irq[i].bitmask) | ||
| 913 | generic_handle_irq(gpmc_client_irq[i].irq); | ||
| 784 | 914 | ||
| 785 | /* check cs to invoke the irq */ | 915 | gpmc_write_reg(GPMC_IRQSTATUS, regval); |
| 786 | cs = ((gpmc_read_reg(GPMC_PREFETCH_CONFIG1)) >> CS_NUM_SHIFT) & 0x7; | ||
| 787 | if (OMAP_GPMC_IRQ_BASE+cs <= OMAP_GPMC_IRQ_END) | ||
| 788 | generic_handle_irq(OMAP_GPMC_IRQ_BASE+cs); | ||
| 789 | 916 | ||
| 790 | return IRQ_HANDLED; | 917 | return IRQ_HANDLED; |
| 791 | } | 918 | } |
diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c index a9675d8d1822..80399d740952 100644 --- a/arch/arm/mach-omap2/hsmmc.c +++ b/arch/arm/mach-omap2/hsmmc.c | |||
| @@ -15,6 +15,8 @@ | |||
| 15 | #include <linux/delay.h> | 15 | #include <linux/delay.h> |
| 16 | #include <linux/gpio.h> | 16 | #include <linux/gpio.h> |
| 17 | #include <mach/hardware.h> | 17 | #include <mach/hardware.h> |
| 18 | #include <linux/platform_data/gpio-omap.h> | ||
| 19 | |||
| 18 | #include <plat/mmc.h> | 20 | #include <plat/mmc.h> |
| 19 | #include <plat/omap-pm.h> | 21 | #include <plat/omap-pm.h> |
| 20 | #include <plat/mux.h> | 22 | #include <plat/mux.h> |
diff --git a/arch/arm/mach-omap2/i2c.c b/arch/arm/mach-omap2/i2c.c index a12e224eb97d..fc57e67b321f 100644 --- a/arch/arm/mach-omap2/i2c.c +++ b/arch/arm/mach-omap2/i2c.c | |||
| @@ -19,7 +19,6 @@ | |||
| 19 | * | 19 | * |
| 20 | */ | 20 | */ |
| 21 | 21 | ||
| 22 | #include <plat/cpu.h> | ||
| 23 | #include <plat/i2c.h> | 22 | #include <plat/i2c.h> |
| 24 | #include "common.h" | 23 | #include "common.h" |
| 25 | #include <plat/omap_hwmod.h> | 24 | #include <plat/omap_hwmod.h> |
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index 40373db649aa..7219df0e831a 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c | |||
| @@ -22,10 +22,10 @@ | |||
| 22 | #include <asm/cputype.h> | 22 | #include <asm/cputype.h> |
| 23 | 23 | ||
| 24 | #include "common.h" | 24 | #include "common.h" |
| 25 | #include <plat/cpu.h> | ||
| 26 | 25 | ||
| 27 | #include <mach/id.h> | 26 | #include <mach/id.h> |
| 28 | 27 | ||
| 28 | #include "soc.h" | ||
| 29 | #include "control.h" | 29 | #include "control.h" |
| 30 | 30 | ||
| 31 | static unsigned int omap_revision; | 31 | static unsigned int omap_revision; |
diff --git a/arch/arm/mach-omap2/include/mach/gpio.h b/arch/arm/mach-omap2/include/mach/gpio.h index be4d290d57ee..5621cc59c9f4 100644 --- a/arch/arm/mach-omap2/include/mach/gpio.h +++ b/arch/arm/mach-omap2/include/mach/gpio.h | |||
| @@ -1,5 +1,3 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * arch/arm/mach-omap2/include/mach/gpio.h | 2 | * arch/arm/mach-omap2/include/mach/gpio.h |
| 3 | */ | 3 | */ |
| 4 | |||
| 5 | #include <plat/gpio.h> | ||
diff --git a/arch/arm/mach-omap2/include/mach/hardware.h b/arch/arm/mach-omap2/include/mach/hardware.h index 78edf9d33f71..54492dbf6973 100644 --- a/arch/arm/mach-omap2/include/mach/hardware.h +++ b/arch/arm/mach-omap2/include/mach/hardware.h | |||
| @@ -1,5 +1,3 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * arch/arm/mach-omap2/include/mach/hardware.h | 2 | * arch/arm/mach-omap2/include/mach/hardware.h |
| 3 | */ | 3 | */ |
| 4 | |||
| 5 | #include <plat/hardware.h> | ||
diff --git a/arch/arm/mach-omap2/include/mach/irqs.h b/arch/arm/mach-omap2/include/mach/irqs.h index 44dab7725696..ba5282cafa42 100644 --- a/arch/arm/mach-omap2/include/mach/irqs.h +++ b/arch/arm/mach-omap2/include/mach/irqs.h | |||
| @@ -1,5 +1,3 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * arch/arm/mach-omap2/include/mach/irqs.h | 2 | * arch/arm/mach-omap2/include/mach/irqs.h |
| 3 | */ | 3 | */ |
| 4 | |||
| 5 | #include <plat/irqs.h> | ||
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 4d2d981ff5c5..0d79c23e9f88 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c | |||
| @@ -33,6 +33,7 @@ | |||
| 33 | #include <plat/multi.h> | 33 | #include <plat/multi.h> |
| 34 | #include <plat/dma.h> | 34 | #include <plat/dma.h> |
| 35 | 35 | ||
| 36 | #include "soc.h" | ||
| 36 | #include "iomap.h" | 37 | #include "iomap.h" |
| 37 | #include "voltage.h" | 38 | #include "voltage.h" |
| 38 | #include "powerdomain.h" | 39 | #include "powerdomain.h" |
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c index bcd83db41bbc..efed4f540adb 100644 --- a/arch/arm/mach-omap2/irq.c +++ b/arch/arm/mach-omap2/irq.c | |||
| @@ -23,8 +23,7 @@ | |||
| 23 | #include <linux/of_address.h> | 23 | #include <linux/of_address.h> |
| 24 | #include <linux/of_irq.h> | 24 | #include <linux/of_irq.h> |
| 25 | 25 | ||
| 26 | #include <mach/hardware.h> | 26 | #include "soc.h" |
| 27 | |||
| 28 | #include "iomap.h" | 27 | #include "iomap.h" |
| 29 | #include "common.h" | 28 | #include "common.h" |
| 30 | 29 | ||
| @@ -49,6 +48,8 @@ | |||
| 49 | #define OMAP3_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE) | 48 | #define OMAP3_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE) |
| 50 | #define INTCPS_SIR_IRQ_OFFSET 0x0040 /* omap2/3 active interrupt offset */ | 49 | #define INTCPS_SIR_IRQ_OFFSET 0x0040 /* omap2/3 active interrupt offset */ |
| 51 | #define ACTIVEIRQ_MASK 0x7f /* omap2/3 active interrupt bits */ | 50 | #define ACTIVEIRQ_MASK 0x7f /* omap2/3 active interrupt bits */ |
| 51 | #define INTCPS_NR_MIR_REGS 3 | ||
| 52 | #define INTCPS_NR_IRQS 96 | ||
| 52 | 53 | ||
| 53 | /* | 54 | /* |
| 54 | * OMAP2 has a number of different interrupt controllers, each interrupt | 55 | * OMAP2 has a number of different interrupt controllers, each interrupt |
diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c index 6875be837d9f..0d974565f8ca 100644 --- a/arch/arm/mach-omap2/mailbox.c +++ b/arch/arm/mach-omap2/mailbox.c | |||
| @@ -16,8 +16,10 @@ | |||
| 16 | #include <linux/platform_device.h> | 16 | #include <linux/platform_device.h> |
| 17 | #include <linux/io.h> | 17 | #include <linux/io.h> |
| 18 | #include <linux/pm_runtime.h> | 18 | #include <linux/pm_runtime.h> |
| 19 | |||
| 19 | #include <plat/mailbox.h> | 20 | #include <plat/mailbox.h> |
| 20 | #include <mach/irqs.h> | 21 | |
| 22 | #include "soc.h" | ||
| 21 | 23 | ||
| 22 | #define MAILBOX_REVISION 0x000 | 24 | #define MAILBOX_REVISION 0x000 |
| 23 | #define MAILBOX_MESSAGE(m) (0x040 + 4 * (m)) | 25 | #define MAILBOX_MESSAGE(m) (0x040 + 4 * (m)) |
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c index 577cb77db26c..d493727632e9 100644 --- a/arch/arm/mach-omap2/mcbsp.c +++ b/arch/arm/mach-omap2/mcbsp.c | |||
| @@ -18,9 +18,7 @@ | |||
| 18 | #include <linux/platform_device.h> | 18 | #include <linux/platform_device.h> |
| 19 | #include <linux/slab.h> | 19 | #include <linux/slab.h> |
| 20 | 20 | ||
| 21 | #include <mach/irqs.h> | ||
| 22 | #include <plat/dma.h> | 21 | #include <plat/dma.h> |
| 23 | #include <plat/cpu.h> | ||
| 24 | #include <plat/mcbsp.h> | 22 | #include <plat/mcbsp.h> |
| 25 | #include <plat/omap_device.h> | 23 | #include <plat/omap_device.h> |
| 26 | #include <linux/pm_runtime.h> | 24 | #include <linux/pm_runtime.h> |
diff --git a/arch/arm/mach-omap2/msdi.c b/arch/arm/mach-omap2/msdi.c index fb5bc6cf3773..9e57b4aadb06 100644 --- a/arch/arm/mach-omap2/msdi.c +++ b/arch/arm/mach-omap2/msdi.c | |||
| @@ -23,6 +23,7 @@ | |||
| 23 | 23 | ||
| 24 | #include <linux/kernel.h> | 24 | #include <linux/kernel.h> |
| 25 | #include <linux/err.h> | 25 | #include <linux/err.h> |
| 26 | #include <linux/platform_data/gpio-omap.h> | ||
| 26 | 27 | ||
| 27 | #include <plat/omap_hwmod.h> | 28 | #include <plat/omap_hwmod.h> |
| 28 | #include <plat/omap_device.h> | 29 | #include <plat/omap_device.h> |
diff --git a/arch/arm/mach-omap2/omap-iommu.c b/arch/arm/mach-omap2/omap-iommu.c index 1be8bcb52e93..df298d46707c 100644 --- a/arch/arm/mach-omap2/omap-iommu.c +++ b/arch/arm/mach-omap2/omap-iommu.c | |||
| @@ -14,7 +14,9 @@ | |||
| 14 | #include <linux/platform_device.h> | 14 | #include <linux/platform_device.h> |
| 15 | 15 | ||
| 16 | #include <plat/iommu.h> | 16 | #include <plat/iommu.h> |
| 17 | #include <plat/irqs.h> | 17 | |
| 18 | #include "soc.h" | ||
| 19 | #include "common.h" | ||
| 18 | 20 | ||
| 19 | struct iommu_device { | 21 | struct iommu_device { |
| 20 | resource_size_t base; | 22 | resource_size_t base; |
| @@ -29,7 +31,7 @@ static int num_iommu_devices; | |||
| 29 | static struct iommu_device omap3_devices[] = { | 31 | static struct iommu_device omap3_devices[] = { |
| 30 | { | 32 | { |
| 31 | .base = 0x480bd400, | 33 | .base = 0x480bd400, |
| 32 | .irq = 24, | 34 | .irq = 24 + OMAP_INTC_START, |
| 33 | .pdata = { | 35 | .pdata = { |
| 34 | .name = "isp", | 36 | .name = "isp", |
| 35 | .nr_tlb_entries = 8, | 37 | .nr_tlb_entries = 8, |
| @@ -41,7 +43,7 @@ static struct iommu_device omap3_devices[] = { | |||
| 41 | #if defined(CONFIG_OMAP_IOMMU_IVA2) | 43 | #if defined(CONFIG_OMAP_IOMMU_IVA2) |
| 42 | { | 44 | { |
| 43 | .base = 0x5d000000, | 45 | .base = 0x5d000000, |
| 44 | .irq = 28, | 46 | .irq = 28 + OMAP_INTC_START, |
| 45 | .pdata = { | 47 | .pdata = { |
| 46 | .name = "iva2", | 48 | .name = "iva2", |
| 47 | .nr_tlb_entries = 32, | 49 | .nr_tlb_entries = 32, |
| @@ -64,7 +66,7 @@ static struct platform_device *omap3_iommu_pdev[NR_OMAP3_IOMMU_DEVICES]; | |||
| 64 | static struct iommu_device omap4_devices[] = { | 66 | static struct iommu_device omap4_devices[] = { |
| 65 | { | 67 | { |
| 66 | .base = OMAP4_MMU1_BASE, | 68 | .base = OMAP4_MMU1_BASE, |
| 67 | .irq = OMAP44XX_IRQ_DUCATI_MMU, | 69 | .irq = 100 + OMAP44XX_IRQ_GIC_START, |
| 68 | .pdata = { | 70 | .pdata = { |
| 69 | .name = "ducati", | 71 | .name = "ducati", |
| 70 | .nr_tlb_entries = 32, | 72 | .nr_tlb_entries = 32, |
| @@ -75,7 +77,7 @@ static struct iommu_device omap4_devices[] = { | |||
| 75 | }, | 77 | }, |
| 76 | { | 78 | { |
| 77 | .base = OMAP4_MMU2_BASE, | 79 | .base = OMAP4_MMU2_BASE, |
| 78 | .irq = OMAP44XX_IRQ_TESLA_MMU, | 80 | .irq = 28 + OMAP44XX_IRQ_GIC_START, |
| 79 | .pdata = { | 81 | .pdata = { |
| 80 | .name = "tesla", | 82 | .name = "tesla", |
| 81 | .nr_tlb_entries = 32, | 83 | .nr_tlb_entries = 32, |
diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c b/arch/arm/mach-omap2/omap-mpuss-lowpower.c index 637a1bdf2ac4..ff4e6a0e9c7c 100644 --- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c +++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c | |||
| @@ -50,9 +50,8 @@ | |||
| 50 | #include <asm/suspend.h> | 50 | #include <asm/suspend.h> |
| 51 | #include <asm/hardware/cache-l2x0.h> | 51 | #include <asm/hardware/cache-l2x0.h> |
| 52 | 52 | ||
| 53 | #include <plat/omap44xx.h> | ||
| 54 | |||
| 55 | #include "common.h" | 53 | #include "common.h" |
| 54 | #include "omap44xx.h" | ||
| 56 | #include "omap4-sar-layout.h" | 55 | #include "omap4-sar-layout.h" |
| 57 | #include "pm.h" | 56 | #include "pm.h" |
| 58 | #include "prcm_mpu44xx.h" | 57 | #include "prcm_mpu44xx.h" |
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c index 9a35adf91232..19cc5f504f7e 100644 --- a/arch/arm/mach-omap2/omap-smp.c +++ b/arch/arm/mach-omap2/omap-smp.c | |||
| @@ -24,11 +24,11 @@ | |||
| 24 | #include <asm/hardware/gic.h> | 24 | #include <asm/hardware/gic.h> |
| 25 | #include <asm/smp_scu.h> | 25 | #include <asm/smp_scu.h> |
| 26 | 26 | ||
| 27 | #include <mach/hardware.h> | ||
| 28 | #include <mach/omap-secure.h> | 27 | #include <mach/omap-secure.h> |
| 29 | #include <mach/omap-wakeupgen.h> | 28 | #include <mach/omap-wakeupgen.h> |
| 30 | #include <asm/cputype.h> | 29 | #include <asm/cputype.h> |
| 31 | 30 | ||
| 31 | #include "soc.h" | ||
| 32 | #include "iomap.h" | 32 | #include "iomap.h" |
| 33 | #include "common.h" | 33 | #include "common.h" |
| 34 | #include "clockdomain.h" | 34 | #include "clockdomain.h" |
diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c b/arch/arm/mach-omap2/omap-wakeupgen.c index 05fdebfaa195..ecaad7d371ee 100644 --- a/arch/arm/mach-omap2/omap-wakeupgen.c +++ b/arch/arm/mach-omap2/omap-wakeupgen.c | |||
| @@ -30,6 +30,7 @@ | |||
| 30 | #include <mach/omap-wakeupgen.h> | 30 | #include <mach/omap-wakeupgen.h> |
| 31 | #include <mach/omap-secure.h> | 31 | #include <mach/omap-secure.h> |
| 32 | 32 | ||
| 33 | #include "soc.h" | ||
| 33 | #include "omap4-sar-layout.h" | 34 | #include "omap4-sar-layout.h" |
| 34 | #include "common.h" | 35 | #include "common.h" |
| 35 | 36 | ||
| @@ -46,7 +47,7 @@ | |||
| 46 | static void __iomem *wakeupgen_base; | 47 | static void __iomem *wakeupgen_base; |
| 47 | static void __iomem *sar_base; | 48 | static void __iomem *sar_base; |
| 48 | static DEFINE_SPINLOCK(wakeupgen_lock); | 49 | static DEFINE_SPINLOCK(wakeupgen_lock); |
| 49 | static unsigned int irq_target_cpu[NR_IRQS]; | 50 | static unsigned int irq_target_cpu[MAX_IRQS]; |
| 50 | static unsigned int irq_banks = MAX_NR_REG_BANKS; | 51 | static unsigned int irq_banks = MAX_NR_REG_BANKS; |
| 51 | static unsigned int max_irqs = MAX_IRQS; | 52 | static unsigned int max_irqs = MAX_IRQS; |
| 52 | static unsigned int omap_secure_apis; | 53 | static unsigned int omap_secure_apis; |
diff --git a/arch/arm/plat-omap/include/plat/omap24xx.h b/arch/arm/mach-omap2/omap24xx.h index 92df9e27cc5c..641a2c8d2eee 100644 --- a/arch/arm/plat-omap/include/plat/omap24xx.h +++ b/arch/arm/mach-omap2/omap24xx.h | |||
| @@ -1,6 +1,4 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * arch/arm/plat-omap/include/mach/omap24xx.h | ||
| 3 | * | ||
| 4 | * This file contains the processor specific definitions | 2 | * This file contains the processor specific definitions |
| 5 | * of the TI OMAP24XX. | 3 | * of the TI OMAP24XX. |
| 6 | * | 4 | * |
diff --git a/arch/arm/plat-omap/include/plat/omap34xx.h b/arch/arm/mach-omap2/omap34xx.h index 0d818acf3917..c0d1b4b1653f 100644 --- a/arch/arm/plat-omap/include/plat/omap34xx.h +++ b/arch/arm/mach-omap2/omap34xx.h | |||
| @@ -1,6 +1,4 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * arch/arm/plat-omap/include/mach/omap34xx.h | ||
| 3 | * | ||
| 4 | * This file contains the processor specific definitions of the TI OMAP34XX. | 2 | * This file contains the processor specific definitions of the TI OMAP34XX. |
| 5 | * | 3 | * |
| 6 | * Copyright (C) 2007 Texas Instruments. | 4 | * Copyright (C) 2007 Texas Instruments. |
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c index c29dee998a79..3cd2564ed5cd 100644 --- a/arch/arm/mach-omap2/omap4-common.c +++ b/arch/arm/mach-omap2/omap4-common.c | |||
| @@ -16,26 +16,25 @@ | |||
| 16 | #include <linux/io.h> | 16 | #include <linux/io.h> |
| 17 | #include <linux/platform_device.h> | 17 | #include <linux/platform_device.h> |
| 18 | #include <linux/memblock.h> | 18 | #include <linux/memblock.h> |
| 19 | #include <linux/of_irq.h> | ||
| 20 | #include <linux/of_platform.h> | ||
| 21 | #include <linux/export.h> | ||
| 19 | 22 | ||
| 20 | #include <asm/hardware/gic.h> | 23 | #include <asm/hardware/gic.h> |
| 21 | #include <asm/hardware/cache-l2x0.h> | 24 | #include <asm/hardware/cache-l2x0.h> |
| 22 | #include <asm/mach/map.h> | 25 | #include <asm/mach/map.h> |
| 23 | #include <asm/memblock.h> | 26 | #include <asm/memblock.h> |
| 24 | #include <linux/of_irq.h> | ||
| 25 | #include <linux/of_platform.h> | ||
| 26 | 27 | ||
| 27 | #include <plat/irqs.h> | ||
| 28 | #include <plat/sram.h> | 28 | #include <plat/sram.h> |
| 29 | #include <plat/omap-secure.h> | 29 | #include <plat/omap-secure.h> |
| 30 | #include <plat/mmc.h> | 30 | #include <plat/mmc.h> |
| 31 | 31 | ||
| 32 | #include <mach/hardware.h> | ||
| 33 | #include <mach/omap-wakeupgen.h> | 32 | #include <mach/omap-wakeupgen.h> |
| 34 | 33 | ||
| 34 | #include "soc.h" | ||
| 35 | #include "common.h" | 35 | #include "common.h" |
| 36 | #include "hsmmc.h" | 36 | #include "hsmmc.h" |
| 37 | #include "omap4-sar-layout.h" | 37 | #include "omap4-sar-layout.h" |
| 38 | #include <linux/export.h> | ||
| 39 | 38 | ||
| 40 | #ifdef CONFIG_CACHE_L2X0 | 39 | #ifdef CONFIG_CACHE_L2X0 |
| 41 | static void __iomem *l2cache_base; | 40 | static void __iomem *l2cache_base; |
| @@ -171,7 +170,10 @@ static int __init omap_l2_cache_init(void) | |||
| 171 | /* Enable PL310 L2 Cache controller */ | 170 | /* Enable PL310 L2 Cache controller */ |
| 172 | omap_smc1(0x102, 0x1); | 171 | omap_smc1(0x102, 0x1); |
| 173 | 172 | ||
| 174 | l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK); | 173 | if (of_have_populated_dt()) |
| 174 | l2x0_of_init(aux_ctrl, L2X0_AUX_CTRL_MASK); | ||
| 175 | else | ||
| 176 | l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK); | ||
| 175 | 177 | ||
| 176 | /* | 178 | /* |
| 177 | * Override default outer_cache.disable with a OMAP4 | 179 | * Override default outer_cache.disable with a OMAP4 |
diff --git a/arch/arm/plat-omap/include/plat/omap44xx.h b/arch/arm/mach-omap2/omap44xx.h index c0d478e55c84..43b927b2e2e8 100644 --- a/arch/arm/plat-omap/include/plat/omap44xx.h +++ b/arch/arm/mach-omap2/omap44xx.h | |||
| @@ -39,12 +39,12 @@ | |||
| 39 | #define IRQ_SIR_IRQ 0x0040 | 39 | #define IRQ_SIR_IRQ 0x0040 |
| 40 | #define OMAP44XX_GIC_DIST_BASE 0x48241000 | 40 | #define OMAP44XX_GIC_DIST_BASE 0x48241000 |
| 41 | #define OMAP44XX_GIC_CPU_BASE 0x48240100 | 41 | #define OMAP44XX_GIC_CPU_BASE 0x48240100 |
| 42 | #define OMAP44XX_IRQ_GIC_START 32 | ||
| 42 | #define OMAP44XX_SCU_BASE 0x48240000 | 43 | #define OMAP44XX_SCU_BASE 0x48240000 |
| 43 | #define OMAP44XX_LOCAL_TWD_BASE 0x48240600 | 44 | #define OMAP44XX_LOCAL_TWD_BASE 0x48240600 |
| 44 | #define OMAP44XX_L2CACHE_BASE 0x48242000 | 45 | #define OMAP44XX_L2CACHE_BASE 0x48242000 |
| 45 | #define OMAP44XX_WKUPGEN_BASE 0x48281000 | 46 | #define OMAP44XX_WKUPGEN_BASE 0x48281000 |
| 46 | #define OMAP44XX_MCPDM_BASE 0x40132000 | 47 | #define OMAP44XX_MCPDM_BASE 0x40132000 |
| 47 | #define OMAP44XX_MCPDM_L3_BASE 0x49032000 | ||
| 48 | #define OMAP44XX_SAR_RAM_BASE 0x4a326000 | 48 | #define OMAP44XX_SAR_RAM_BASE 0x4a326000 |
| 49 | 49 | ||
| 50 | #define OMAP44XX_MAILBOX_BASE (L4_44XX_BASE + 0xF4000) | 50 | #define OMAP44XX_MAILBOX_BASE (L4_44XX_BASE + 0xF4000) |
diff --git a/arch/arm/plat-omap/include/plat/omap54xx.h b/arch/arm/mach-omap2/omap54xx.h index a2582bb3cab3..a2582bb3cab3 100644 --- a/arch/arm/plat-omap/include/plat/omap54xx.h +++ b/arch/arm/mach-omap2/omap54xx.h | |||
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 6ca8e519968d..4a810f6c4c04 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c | |||
| @@ -139,14 +139,14 @@ | |||
| 139 | #include <linux/slab.h> | 139 | #include <linux/slab.h> |
| 140 | #include <linux/bootmem.h> | 140 | #include <linux/bootmem.h> |
| 141 | 141 | ||
| 142 | #include "common.h" | ||
| 143 | #include <plat/cpu.h> | ||
| 144 | #include "clockdomain.h" | ||
| 145 | #include "powerdomain.h" | ||
| 146 | #include <plat/clock.h> | 142 | #include <plat/clock.h> |
| 147 | #include <plat/omap_hwmod.h> | 143 | #include <plat/omap_hwmod.h> |
| 148 | #include <plat/prcm.h> | 144 | #include <plat/prcm.h> |
| 149 | 145 | ||
| 146 | #include "soc.h" | ||
| 147 | #include "common.h" | ||
| 148 | #include "clockdomain.h" | ||
| 149 | #include "powerdomain.h" | ||
| 150 | #include "cm2xxx_3xxx.h" | 150 | #include "cm2xxx_3xxx.h" |
| 151 | #include "cminst44xx.h" | 151 | #include "cminst44xx.h" |
| 152 | #include "prm2xxx_3xxx.h" | 152 | #include "prm2xxx_3xxx.h" |
| @@ -1889,6 +1889,7 @@ static int _enable(struct omap_hwmod *oh) | |||
| 1889 | _enable_sysc(oh); | 1889 | _enable_sysc(oh); |
| 1890 | } | 1890 | } |
| 1891 | } else { | 1891 | } else { |
| 1892 | _omap4_disable_module(oh); | ||
| 1892 | _disable_clocks(oh); | 1893 | _disable_clocks(oh); |
| 1893 | pr_debug("omap_hwmod: %s: _wait_target_ready: %d\n", | 1894 | pr_debug("omap_hwmod: %s: _wait_target_ready: %d\n", |
| 1894 | oh->name, r); | 1895 | oh->name, r); |
| @@ -3158,6 +3159,33 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res) | |||
| 3158 | } | 3159 | } |
| 3159 | 3160 | ||
| 3160 | /** | 3161 | /** |
| 3162 | * omap_hwmod_fill_dma_resources - fill struct resource array with dma data | ||
| 3163 | * @oh: struct omap_hwmod * | ||
| 3164 | * @res: pointer to the array of struct resource to fill | ||
| 3165 | * | ||
| 3166 | * Fill the struct resource array @res with dma resource data from the | ||
| 3167 | * omap_hwmod @oh. Intended to be called by code that registers | ||
| 3168 | * omap_devices. See also omap_hwmod_count_resources(). Returns the | ||
| 3169 | * number of array elements filled. | ||
| 3170 | */ | ||
| 3171 | int omap_hwmod_fill_dma_resources(struct omap_hwmod *oh, struct resource *res) | ||
| 3172 | { | ||
| 3173 | int i, sdma_reqs_cnt; | ||
| 3174 | int r = 0; | ||
| 3175 | |||
| 3176 | sdma_reqs_cnt = _count_sdma_reqs(oh); | ||
| 3177 | for (i = 0; i < sdma_reqs_cnt; i++) { | ||
| 3178 | (res + r)->name = (oh->sdma_reqs + i)->name; | ||
| 3179 | (res + r)->start = (oh->sdma_reqs + i)->dma_req; | ||
| 3180 | (res + r)->end = (oh->sdma_reqs + i)->dma_req; | ||
| 3181 | (res + r)->flags = IORESOURCE_DMA; | ||
| 3182 | r++; | ||
| 3183 | } | ||
| 3184 | |||
| 3185 | return r; | ||
| 3186 | } | ||
| 3187 | |||
| 3188 | /** | ||
| 3161 | * omap_hwmod_get_resource_byname - fetch IP block integration data by name | 3189 | * omap_hwmod_get_resource_byname - fetch IP block integration data by name |
| 3162 | * @oh: struct omap_hwmod * to operate on | 3190 | * @oh: struct omap_hwmod * to operate on |
| 3163 | * @type: one of the IORESOURCE_* constants from include/linux/ioport.h | 3191 | * @type: one of the IORESOURCE_* constants from include/linux/ioport.h |
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c index 50cfab61b0e2..4e81637640e9 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c | |||
| @@ -13,12 +13,9 @@ | |||
| 13 | * XXX these should be marked initdata for multi-OMAP kernels | 13 | * XXX these should be marked initdata for multi-OMAP kernels |
| 14 | */ | 14 | */ |
| 15 | #include <plat/omap_hwmod.h> | 15 | #include <plat/omap_hwmod.h> |
| 16 | #include <mach/irqs.h> | ||
| 17 | #include <plat/cpu.h> | ||
| 18 | #include <plat/dma.h> | 16 | #include <plat/dma.h> |
| 19 | #include <plat/serial.h> | 17 | #include <plat/serial.h> |
| 20 | #include <plat/i2c.h> | 18 | #include <plat/i2c.h> |
| 21 | #include <plat/gpio.h> | ||
| 22 | #include <plat/mcspi.h> | 19 | #include <plat/mcspi.h> |
| 23 | #include <plat/dmtimer.h> | 20 | #include <plat/dmtimer.h> |
| 24 | #include <plat/l3_2xxx.h> | 21 | #include <plat/l3_2xxx.h> |
| @@ -162,9 +159,9 @@ static struct omap_hwmod omap2420_dma_system_hwmod = { | |||
| 162 | 159 | ||
| 163 | /* mailbox */ | 160 | /* mailbox */ |
| 164 | static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = { | 161 | static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = { |
| 165 | { .name = "dsp", .irq = 26 }, | 162 | { .name = "dsp", .irq = 26 + OMAP_INTC_START, }, |
| 166 | { .name = "iva", .irq = 34 }, | 163 | { .name = "iva", .irq = 34 + OMAP_INTC_START, }, |
| 167 | { .irq = -1 } | 164 | { .irq = -1 }, |
| 168 | }; | 165 | }; |
| 169 | 166 | ||
| 170 | static struct omap_hwmod omap2420_mailbox_hwmod = { | 167 | static struct omap_hwmod omap2420_mailbox_hwmod = { |
| @@ -199,9 +196,9 @@ static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = { | |||
| 199 | 196 | ||
| 200 | /* mcbsp1 */ | 197 | /* mcbsp1 */ |
| 201 | static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = { | 198 | static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = { |
| 202 | { .name = "tx", .irq = 59 }, | 199 | { .name = "tx", .irq = 59 + OMAP_INTC_START, }, |
| 203 | { .name = "rx", .irq = 60 }, | 200 | { .name = "rx", .irq = 60 + OMAP_INTC_START, }, |
| 204 | { .irq = -1 } | 201 | { .irq = -1 }, |
| 205 | }; | 202 | }; |
| 206 | 203 | ||
| 207 | static struct omap_hwmod omap2420_mcbsp1_hwmod = { | 204 | static struct omap_hwmod omap2420_mcbsp1_hwmod = { |
| @@ -225,9 +222,9 @@ static struct omap_hwmod omap2420_mcbsp1_hwmod = { | |||
| 225 | 222 | ||
| 226 | /* mcbsp2 */ | 223 | /* mcbsp2 */ |
| 227 | static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = { | 224 | static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = { |
| 228 | { .name = "tx", .irq = 62 }, | 225 | { .name = "tx", .irq = 62 + OMAP_INTC_START, }, |
| 229 | { .name = "rx", .irq = 63 }, | 226 | { .name = "rx", .irq = 63 + OMAP_INTC_START, }, |
| 230 | { .irq = -1 } | 227 | { .irq = -1 }, |
| 231 | }; | 228 | }; |
| 232 | 229 | ||
| 233 | static struct omap_hwmod omap2420_mcbsp2_hwmod = { | 230 | static struct omap_hwmod omap2420_mcbsp2_hwmod = { |
| @@ -265,8 +262,8 @@ static struct omap_hwmod_class omap2420_msdi_hwmod_class = { | |||
| 265 | 262 | ||
| 266 | /* msdi1 */ | 263 | /* msdi1 */ |
| 267 | static struct omap_hwmod_irq_info omap2420_msdi1_irqs[] = { | 264 | static struct omap_hwmod_irq_info omap2420_msdi1_irqs[] = { |
| 268 | { .irq = 83 }, | 265 | { .irq = 83 + OMAP_INTC_START, }, |
| 269 | { .irq = -1 } | 266 | { .irq = -1 }, |
| 270 | }; | 267 | }; |
| 271 | 268 | ||
| 272 | static struct omap_hwmod_dma_info omap2420_msdi1_sdma_reqs[] = { | 269 | static struct omap_hwmod_dma_info omap2420_msdi1_sdma_reqs[] = { |
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c index 58b5bc196d32..ceb23c3fa89d 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c | |||
| @@ -13,20 +13,17 @@ | |||
| 13 | * XXX these should be marked initdata for multi-OMAP kernels | 13 | * XXX these should be marked initdata for multi-OMAP kernels |
| 14 | */ | 14 | */ |
| 15 | #include <plat/omap_hwmod.h> | 15 | #include <plat/omap_hwmod.h> |
| 16 | #include <mach/irqs.h> | ||
| 17 | #include <plat/cpu.h> | ||
| 18 | #include <plat/dma.h> | 16 | #include <plat/dma.h> |
| 19 | #include <plat/serial.h> | 17 | #include <plat/serial.h> |
| 20 | #include <plat/i2c.h> | 18 | #include <plat/i2c.h> |
| 21 | #include <plat/gpio.h> | ||
| 22 | #include <plat/mcbsp.h> | 19 | #include <plat/mcbsp.h> |
| 23 | #include <plat/mcspi.h> | 20 | #include <plat/mcspi.h> |
| 24 | #include <plat/dmtimer.h> | 21 | #include <plat/dmtimer.h> |
| 25 | #include <plat/mmc.h> | 22 | #include <plat/mmc.h> |
| 26 | #include <plat/l3_2xxx.h> | 23 | #include <plat/l3_2xxx.h> |
| 27 | 24 | ||
| 25 | #include "soc.h" | ||
| 28 | #include "omap_hwmod_common_data.h" | 26 | #include "omap_hwmod_common_data.h" |
| 29 | |||
| 30 | #include "prm-regbits-24xx.h" | 27 | #include "prm-regbits-24xx.h" |
| 31 | #include "cm-regbits-24xx.h" | 28 | #include "cm-regbits-24xx.h" |
| 32 | #include "wd_timer.h" | 29 | #include "wd_timer.h" |
| @@ -133,8 +130,8 @@ static struct omap_hwmod omap2430_i2c2_hwmod = { | |||
| 133 | 130 | ||
| 134 | /* gpio5 */ | 131 | /* gpio5 */ |
| 135 | static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = { | 132 | static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = { |
| 136 | { .irq = 33 }, /* INT_24XX_GPIO_BANK5 */ | 133 | { .irq = 33 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK5 */ |
| 137 | { .irq = -1 } | 134 | { .irq = -1 }, |
| 138 | }; | 135 | }; |
| 139 | 136 | ||
| 140 | static struct omap_hwmod omap2430_gpio5_hwmod = { | 137 | static struct omap_hwmod omap2430_gpio5_hwmod = { |
| @@ -173,8 +170,8 @@ static struct omap_hwmod omap2430_dma_system_hwmod = { | |||
| 173 | 170 | ||
| 174 | /* mailbox */ | 171 | /* mailbox */ |
| 175 | static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = { | 172 | static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = { |
| 176 | { .irq = 26 }, | 173 | { .irq = 26 + OMAP_INTC_START, }, |
| 177 | { .irq = -1 } | 174 | { .irq = -1 }, |
| 178 | }; | 175 | }; |
| 179 | 176 | ||
| 180 | static struct omap_hwmod omap2430_mailbox_hwmod = { | 177 | static struct omap_hwmod omap2430_mailbox_hwmod = { |
| @@ -195,8 +192,8 @@ static struct omap_hwmod omap2430_mailbox_hwmod = { | |||
| 195 | 192 | ||
| 196 | /* mcspi3 */ | 193 | /* mcspi3 */ |
| 197 | static struct omap_hwmod_irq_info omap2430_mcspi3_mpu_irqs[] = { | 194 | static struct omap_hwmod_irq_info omap2430_mcspi3_mpu_irqs[] = { |
| 198 | { .irq = 91 }, | 195 | { .irq = 91 + OMAP_INTC_START, }, |
| 199 | { .irq = -1 } | 196 | { .irq = -1 }, |
| 200 | }; | 197 | }; |
| 201 | 198 | ||
| 202 | static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = { | 199 | static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = { |
| @@ -250,9 +247,9 @@ static struct omap_hwmod_class usbotg_class = { | |||
| 250 | /* usb_otg_hs */ | 247 | /* usb_otg_hs */ |
| 251 | static struct omap_hwmod_irq_info omap2430_usbhsotg_mpu_irqs[] = { | 248 | static struct omap_hwmod_irq_info omap2430_usbhsotg_mpu_irqs[] = { |
| 252 | 249 | ||
| 253 | { .name = "mc", .irq = 92 }, | 250 | { .name = "mc", .irq = 92 + OMAP_INTC_START, }, |
| 254 | { .name = "dma", .irq = 93 }, | 251 | { .name = "dma", .irq = 93 + OMAP_INTC_START, }, |
| 255 | { .irq = -1 } | 252 | { .irq = -1 }, |
| 256 | }; | 253 | }; |
| 257 | 254 | ||
| 258 | static struct omap_hwmod omap2430_usbhsotg_hwmod = { | 255 | static struct omap_hwmod omap2430_usbhsotg_hwmod = { |
| @@ -303,11 +300,11 @@ static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = { | |||
| 303 | 300 | ||
| 304 | /* mcbsp1 */ | 301 | /* mcbsp1 */ |
| 305 | static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = { | 302 | static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = { |
| 306 | { .name = "tx", .irq = 59 }, | 303 | { .name = "tx", .irq = 59 + OMAP_INTC_START, }, |
| 307 | { .name = "rx", .irq = 60 }, | 304 | { .name = "rx", .irq = 60 + OMAP_INTC_START, }, |
| 308 | { .name = "ovr", .irq = 61 }, | 305 | { .name = "ovr", .irq = 61 + OMAP_INTC_START, }, |
| 309 | { .name = "common", .irq = 64 }, | 306 | { .name = "common", .irq = 64 + OMAP_INTC_START, }, |
| 310 | { .irq = -1 } | 307 | { .irq = -1 }, |
| 311 | }; | 308 | }; |
| 312 | 309 | ||
| 313 | static struct omap_hwmod omap2430_mcbsp1_hwmod = { | 310 | static struct omap_hwmod omap2430_mcbsp1_hwmod = { |
| @@ -331,10 +328,10 @@ static struct omap_hwmod omap2430_mcbsp1_hwmod = { | |||
| 331 | 328 | ||
| 332 | /* mcbsp2 */ | 329 | /* mcbsp2 */ |
| 333 | static struct omap_hwmod_irq_info omap2430_mcbsp2_irqs[] = { | 330 | static struct omap_hwmod_irq_info omap2430_mcbsp2_irqs[] = { |
| 334 | { .name = "tx", .irq = 62 }, | 331 | { .name = "tx", .irq = 62 + OMAP_INTC_START, }, |
| 335 | { .name = "rx", .irq = 63 }, | 332 | { .name = "rx", .irq = 63 + OMAP_INTC_START, }, |
| 336 | { .name = "common", .irq = 16 }, | 333 | { .name = "common", .irq = 16 + OMAP_INTC_START, }, |
| 337 | { .irq = -1 } | 334 | { .irq = -1 }, |
| 338 | }; | 335 | }; |
| 339 | 336 | ||
| 340 | static struct omap_hwmod omap2430_mcbsp2_hwmod = { | 337 | static struct omap_hwmod omap2430_mcbsp2_hwmod = { |
| @@ -358,10 +355,10 @@ static struct omap_hwmod omap2430_mcbsp2_hwmod = { | |||
| 358 | 355 | ||
| 359 | /* mcbsp3 */ | 356 | /* mcbsp3 */ |
| 360 | static struct omap_hwmod_irq_info omap2430_mcbsp3_irqs[] = { | 357 | static struct omap_hwmod_irq_info omap2430_mcbsp3_irqs[] = { |
| 361 | { .name = "tx", .irq = 89 }, | 358 | { .name = "tx", .irq = 89 + OMAP_INTC_START, }, |
| 362 | { .name = "rx", .irq = 90 }, | 359 | { .name = "rx", .irq = 90 + OMAP_INTC_START, }, |
| 363 | { .name = "common", .irq = 17 }, | 360 | { .name = "common", .irq = 17 + OMAP_INTC_START, }, |
| 364 | { .irq = -1 } | 361 | { .irq = -1 }, |
| 365 | }; | 362 | }; |
| 366 | 363 | ||
| 367 | static struct omap_hwmod omap2430_mcbsp3_hwmod = { | 364 | static struct omap_hwmod omap2430_mcbsp3_hwmod = { |
| @@ -385,10 +382,10 @@ static struct omap_hwmod omap2430_mcbsp3_hwmod = { | |||
| 385 | 382 | ||
| 386 | /* mcbsp4 */ | 383 | /* mcbsp4 */ |
| 387 | static struct omap_hwmod_irq_info omap2430_mcbsp4_irqs[] = { | 384 | static struct omap_hwmod_irq_info omap2430_mcbsp4_irqs[] = { |
| 388 | { .name = "tx", .irq = 54 }, | 385 | { .name = "tx", .irq = 54 + OMAP_INTC_START, }, |
| 389 | { .name = "rx", .irq = 55 }, | 386 | { .name = "rx", .irq = 55 + OMAP_INTC_START, }, |
| 390 | { .name = "common", .irq = 18 }, | 387 | { .name = "common", .irq = 18 + OMAP_INTC_START, }, |
| 391 | { .irq = -1 } | 388 | { .irq = -1 }, |
| 392 | }; | 389 | }; |
| 393 | 390 | ||
| 394 | static struct omap_hwmod_dma_info omap2430_mcbsp4_sdma_chs[] = { | 391 | static struct omap_hwmod_dma_info omap2430_mcbsp4_sdma_chs[] = { |
| @@ -418,10 +415,10 @@ static struct omap_hwmod omap2430_mcbsp4_hwmod = { | |||
| 418 | 415 | ||
| 419 | /* mcbsp5 */ | 416 | /* mcbsp5 */ |
| 420 | static struct omap_hwmod_irq_info omap2430_mcbsp5_irqs[] = { | 417 | static struct omap_hwmod_irq_info omap2430_mcbsp5_irqs[] = { |
| 421 | { .name = "tx", .irq = 81 }, | 418 | { .name = "tx", .irq = 81 + OMAP_INTC_START, }, |
| 422 | { .name = "rx", .irq = 82 }, | 419 | { .name = "rx", .irq = 82 + OMAP_INTC_START, }, |
| 423 | { .name = "common", .irq = 19 }, | 420 | { .name = "common", .irq = 19 + OMAP_INTC_START, }, |
| 424 | { .irq = -1 } | 421 | { .irq = -1 }, |
| 425 | }; | 422 | }; |
| 426 | 423 | ||
| 427 | static struct omap_hwmod_dma_info omap2430_mcbsp5_sdma_chs[] = { | 424 | static struct omap_hwmod_dma_info omap2430_mcbsp5_sdma_chs[] = { |
| @@ -468,8 +465,8 @@ static struct omap_hwmod_class omap2430_mmc_class = { | |||
| 468 | 465 | ||
| 469 | /* MMC/SD/SDIO1 */ | 466 | /* MMC/SD/SDIO1 */ |
| 470 | static struct omap_hwmod_irq_info omap2430_mmc1_mpu_irqs[] = { | 467 | static struct omap_hwmod_irq_info omap2430_mmc1_mpu_irqs[] = { |
| 471 | { .irq = 83 }, | 468 | { .irq = 83 + OMAP_INTC_START, }, |
| 472 | { .irq = -1 } | 469 | { .irq = -1 }, |
| 473 | }; | 470 | }; |
| 474 | 471 | ||
| 475 | static struct omap_hwmod_dma_info omap2430_mmc1_sdma_reqs[] = { | 472 | static struct omap_hwmod_dma_info omap2430_mmc1_sdma_reqs[] = { |
| @@ -509,8 +506,8 @@ static struct omap_hwmod omap2430_mmc1_hwmod = { | |||
| 509 | 506 | ||
| 510 | /* MMC/SD/SDIO2 */ | 507 | /* MMC/SD/SDIO2 */ |
| 511 | static struct omap_hwmod_irq_info omap2430_mmc2_mpu_irqs[] = { | 508 | static struct omap_hwmod_irq_info omap2430_mmc2_mpu_irqs[] = { |
| 512 | { .irq = 86 }, | 509 | { .irq = 86 + OMAP_INTC_START, }, |
| 513 | { .irq = -1 } | 510 | { .irq = -1 }, |
| 514 | }; | 511 | }; |
| 515 | 512 | ||
| 516 | static struct omap_hwmod_dma_info omap2430_mmc2_sdma_reqs[] = { | 513 | static struct omap_hwmod_dma_info omap2430_mmc2_sdma_reqs[] = { |
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c index 102d76e9e9ea..bea700e928e7 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c | |||
| @@ -15,8 +15,6 @@ | |||
| 15 | #include <plat/common.h> | 15 | #include <plat/common.h> |
| 16 | #include <plat/hdq1w.h> | 16 | #include <plat/hdq1w.h> |
| 17 | 17 | ||
| 18 | #include <mach/irqs.h> | ||
| 19 | |||
| 20 | #include "omap_hwmod_common_data.h" | 18 | #include "omap_hwmod_common_data.h" |
| 21 | 19 | ||
| 22 | /* UART */ | 20 | /* UART */ |
| @@ -182,126 +180,126 @@ struct omap_hwmod_class iva_hwmod_class = { | |||
| 182 | /* Common MPU IRQ line data */ | 180 | /* Common MPU IRQ line data */ |
| 183 | 181 | ||
| 184 | struct omap_hwmod_irq_info omap2_timer1_mpu_irqs[] = { | 182 | struct omap_hwmod_irq_info omap2_timer1_mpu_irqs[] = { |
| 185 | { .irq = 37, }, | 183 | { .irq = 37 + OMAP_INTC_START, }, |
| 186 | { .irq = -1 } | 184 | { .irq = -1 }, |
| 187 | }; | 185 | }; |
| 188 | 186 | ||
| 189 | struct omap_hwmod_irq_info omap2_timer2_mpu_irqs[] = { | 187 | struct omap_hwmod_irq_info omap2_timer2_mpu_irqs[] = { |
| 190 | { .irq = 38, }, | 188 | { .irq = 38 + OMAP_INTC_START, }, |
| 191 | { .irq = -1 } | 189 | { .irq = -1 }, |
| 192 | }; | 190 | }; |
| 193 | 191 | ||
| 194 | struct omap_hwmod_irq_info omap2_timer3_mpu_irqs[] = { | 192 | struct omap_hwmod_irq_info omap2_timer3_mpu_irqs[] = { |
| 195 | { .irq = 39, }, | 193 | { .irq = 39 + OMAP_INTC_START, }, |
| 196 | { .irq = -1 } | 194 | { .irq = -1 }, |
| 197 | }; | 195 | }; |
| 198 | 196 | ||
| 199 | struct omap_hwmod_irq_info omap2_timer4_mpu_irqs[] = { | 197 | struct omap_hwmod_irq_info omap2_timer4_mpu_irqs[] = { |
| 200 | { .irq = 40, }, | 198 | { .irq = 40 + OMAP_INTC_START, }, |
| 201 | { .irq = -1 } | 199 | { .irq = -1 }, |
| 202 | }; | 200 | }; |
| 203 | 201 | ||
| 204 | struct omap_hwmod_irq_info omap2_timer5_mpu_irqs[] = { | 202 | struct omap_hwmod_irq_info omap2_timer5_mpu_irqs[] = { |
| 205 | { .irq = 41, }, | 203 | { .irq = 41 + OMAP_INTC_START, }, |
| 206 | { .irq = -1 } | 204 | { .irq = -1 }, |
| 207 | }; | 205 | }; |
| 208 | 206 | ||
| 209 | struct omap_hwmod_irq_info omap2_timer6_mpu_irqs[] = { | 207 | struct omap_hwmod_irq_info omap2_timer6_mpu_irqs[] = { |
| 210 | { .irq = 42, }, | 208 | { .irq = 42 + OMAP_INTC_START, }, |
| 211 | { .irq = -1 } | 209 | { .irq = -1 }, |
| 212 | }; | 210 | }; |
| 213 | 211 | ||
| 214 | struct omap_hwmod_irq_info omap2_timer7_mpu_irqs[] = { | 212 | struct omap_hwmod_irq_info omap2_timer7_mpu_irqs[] = { |
| 215 | { .irq = 43, }, | 213 | { .irq = 43 + OMAP_INTC_START, }, |
| 216 | { .irq = -1 } | 214 | { .irq = -1 }, |
| 217 | }; | 215 | }; |
| 218 | 216 | ||
| 219 | struct omap_hwmod_irq_info omap2_timer8_mpu_irqs[] = { | 217 | struct omap_hwmod_irq_info omap2_timer8_mpu_irqs[] = { |
| 220 | { .irq = 44, }, | 218 | { .irq = 44 + OMAP_INTC_START, }, |
| 221 | { .irq = -1 } | 219 | { .irq = -1 }, |
| 222 | }; | 220 | }; |
| 223 | 221 | ||
| 224 | struct omap_hwmod_irq_info omap2_timer9_mpu_irqs[] = { | 222 | struct omap_hwmod_irq_info omap2_timer9_mpu_irqs[] = { |
| 225 | { .irq = 45, }, | 223 | { .irq = 45 + OMAP_INTC_START, }, |
| 226 | { .irq = -1 } | 224 | { .irq = -1 }, |
| 227 | }; | 225 | }; |
| 228 | 226 | ||
| 229 | struct omap_hwmod_irq_info omap2_timer10_mpu_irqs[] = { | 227 | struct omap_hwmod_irq_info omap2_timer10_mpu_irqs[] = { |
| 230 | { .irq = 46, }, | 228 | { .irq = 46 + OMAP_INTC_START, }, |
| 231 | { .irq = -1 } | 229 | { .irq = -1 }, |
| 232 | }; | 230 | }; |
| 233 | 231 | ||
| 234 | struct omap_hwmod_irq_info omap2_timer11_mpu_irqs[] = { | 232 | struct omap_hwmod_irq_info omap2_timer11_mpu_irqs[] = { |
| 235 | { .irq = 47, }, | 233 | { .irq = 47 + OMAP_INTC_START, }, |
| 236 | { .irq = -1 } | 234 | { .irq = -1 }, |
| 237 | }; | 235 | }; |
| 238 | 236 | ||
| 239 | struct omap_hwmod_irq_info omap2_uart1_mpu_irqs[] = { | 237 | struct omap_hwmod_irq_info omap2_uart1_mpu_irqs[] = { |
| 240 | { .irq = INT_24XX_UART1_IRQ, }, | 238 | { .irq = 72 + OMAP_INTC_START, }, |
| 241 | { .irq = -1 } | 239 | { .irq = -1 }, |
| 242 | }; | 240 | }; |
| 243 | 241 | ||
| 244 | struct omap_hwmod_irq_info omap2_uart2_mpu_irqs[] = { | 242 | struct omap_hwmod_irq_info omap2_uart2_mpu_irqs[] = { |
| 245 | { .irq = INT_24XX_UART2_IRQ, }, | 243 | { .irq = 73 + OMAP_INTC_START, }, |
| 246 | { .irq = -1 } | 244 | { .irq = -1 }, |
| 247 | }; | 245 | }; |
| 248 | 246 | ||
| 249 | struct omap_hwmod_irq_info omap2_uart3_mpu_irqs[] = { | 247 | struct omap_hwmod_irq_info omap2_uart3_mpu_irqs[] = { |
| 250 | { .irq = INT_24XX_UART3_IRQ, }, | 248 | { .irq = 74 + OMAP_INTC_START, }, |
| 251 | { .irq = -1 } | 249 | { .irq = -1 }, |
| 252 | }; | 250 | }; |
| 253 | 251 | ||
| 254 | struct omap_hwmod_irq_info omap2_dispc_irqs[] = { | 252 | struct omap_hwmod_irq_info omap2_dispc_irqs[] = { |
| 255 | { .irq = 25 }, | 253 | { .irq = 25 + OMAP_INTC_START, }, |
| 256 | { .irq = -1 } | 254 | { .irq = -1 }, |
| 257 | }; | 255 | }; |
| 258 | 256 | ||
| 259 | struct omap_hwmod_irq_info omap2_i2c1_mpu_irqs[] = { | 257 | struct omap_hwmod_irq_info omap2_i2c1_mpu_irqs[] = { |
| 260 | { .irq = INT_24XX_I2C1_IRQ, }, | 258 | { .irq = 56 + OMAP_INTC_START, }, |
| 261 | { .irq = -1 } | 259 | { .irq = -1 }, |
| 262 | }; | 260 | }; |
| 263 | 261 | ||
| 264 | struct omap_hwmod_irq_info omap2_i2c2_mpu_irqs[] = { | 262 | struct omap_hwmod_irq_info omap2_i2c2_mpu_irqs[] = { |
| 265 | { .irq = INT_24XX_I2C2_IRQ, }, | 263 | { .irq = 57 + OMAP_INTC_START, }, |
| 266 | { .irq = -1 } | 264 | { .irq = -1 }, |
| 267 | }; | 265 | }; |
| 268 | 266 | ||
| 269 | struct omap_hwmod_irq_info omap2_gpio1_irqs[] = { | 267 | struct omap_hwmod_irq_info omap2_gpio1_irqs[] = { |
| 270 | { .irq = 29 }, /* INT_24XX_GPIO_BANK1 */ | 268 | { .irq = 29 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK1 */ |
| 271 | { .irq = -1 } | 269 | { .irq = -1 }, |
| 272 | }; | 270 | }; |
| 273 | 271 | ||
| 274 | struct omap_hwmod_irq_info omap2_gpio2_irqs[] = { | 272 | struct omap_hwmod_irq_info omap2_gpio2_irqs[] = { |
| 275 | { .irq = 30 }, /* INT_24XX_GPIO_BANK2 */ | 273 | { .irq = 30 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK2 */ |
| 276 | { .irq = -1 } | 274 | { .irq = -1 }, |
| 277 | }; | 275 | }; |
| 278 | 276 | ||
| 279 | struct omap_hwmod_irq_info omap2_gpio3_irqs[] = { | 277 | struct omap_hwmod_irq_info omap2_gpio3_irqs[] = { |
| 280 | { .irq = 31 }, /* INT_24XX_GPIO_BANK3 */ | 278 | { .irq = 31 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK3 */ |
| 281 | { .irq = -1 } | 279 | { .irq = -1 }, |
| 282 | }; | 280 | }; |
| 283 | 281 | ||
| 284 | struct omap_hwmod_irq_info omap2_gpio4_irqs[] = { | 282 | struct omap_hwmod_irq_info omap2_gpio4_irqs[] = { |
| 285 | { .irq = 32 }, /* INT_24XX_GPIO_BANK4 */ | 283 | { .irq = 32 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK4 */ |
| 286 | { .irq = -1 } | 284 | { .irq = -1 }, |
| 287 | }; | 285 | }; |
| 288 | 286 | ||
| 289 | struct omap_hwmod_irq_info omap2_dma_system_irqs[] = { | 287 | struct omap_hwmod_irq_info omap2_dma_system_irqs[] = { |
| 290 | { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */ | 288 | { .name = "0", .irq = 12 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ0 */ |
| 291 | { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */ | 289 | { .name = "1", .irq = 13 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ1 */ |
| 292 | { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */ | 290 | { .name = "2", .irq = 14 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ2 */ |
| 293 | { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */ | 291 | { .name = "3", .irq = 15 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ3 */ |
| 294 | { .irq = -1 } | 292 | { .irq = -1 }, |
| 295 | }; | 293 | }; |
| 296 | 294 | ||
| 297 | struct omap_hwmod_irq_info omap2_mcspi1_mpu_irqs[] = { | 295 | struct omap_hwmod_irq_info omap2_mcspi1_mpu_irqs[] = { |
| 298 | { .irq = 65 }, | 296 | { .irq = 65 + OMAP_INTC_START, }, |
| 299 | { .irq = -1 } | 297 | { .irq = -1 }, |
| 300 | }; | 298 | }; |
| 301 | 299 | ||
| 302 | struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[] = { | 300 | struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[] = { |
| 303 | { .irq = 66 }, | 301 | { .irq = 66 + OMAP_INTC_START, }, |
| 304 | { .irq = -1 } | 302 | { .irq = -1 }, |
| 305 | }; | 303 | }; |
| 306 | 304 | ||
| 307 | struct omap_hwmod_class_sysconfig omap2_hdq1w_sysc = { | 305 | struct omap_hwmod_class_sysconfig omap2_hdq1w_sysc = { |
| @@ -320,7 +318,7 @@ struct omap_hwmod_class omap2_hdq1w_class = { | |||
| 320 | }; | 318 | }; |
| 321 | 319 | ||
| 322 | struct omap_hwmod_irq_info omap2_hdq1w_mpu_irqs[] = { | 320 | struct omap_hwmod_irq_info omap2_hdq1w_mpu_irqs[] = { |
| 323 | { .irq = 58, }, | 321 | { .irq = 58 + OMAP_INTC_START, }, |
| 324 | { .irq = -1 } | 322 | { .irq = -1 }, |
| 325 | }; | 323 | }; |
| 326 | 324 | ||
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c index afad69c6ba6e..ceb305242340 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c | |||
| @@ -10,21 +10,19 @@ | |||
| 10 | */ | 10 | */ |
| 11 | #include <plat/omap_hwmod.h> | 11 | #include <plat/omap_hwmod.h> |
| 12 | #include <plat/serial.h> | 12 | #include <plat/serial.h> |
| 13 | #include <plat/gpio.h> | 13 | #include <linux/platform_data/gpio-omap.h> |
| 14 | #include <plat/dma.h> | 14 | #include <plat/dma.h> |
| 15 | #include <plat/dmtimer.h> | 15 | #include <plat/dmtimer.h> |
| 16 | #include <plat/mcspi.h> | 16 | #include <plat/mcspi.h> |
| 17 | 17 | ||
| 18 | #include <mach/irqs.h> | ||
| 19 | |||
| 20 | #include "omap_hwmod_common_data.h" | 18 | #include "omap_hwmod_common_data.h" |
| 21 | #include "cm-regbits-24xx.h" | 19 | #include "cm-regbits-24xx.h" |
| 22 | #include "prm-regbits-24xx.h" | 20 | #include "prm-regbits-24xx.h" |
| 23 | #include "wd_timer.h" | 21 | #include "wd_timer.h" |
| 24 | 22 | ||
| 25 | struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[] = { | 23 | struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[] = { |
| 26 | { .irq = 48, }, | 24 | { .irq = 48 + OMAP_INTC_START, }, |
| 27 | { .irq = -1 } | 25 | { .irq = -1 }, |
| 28 | }; | 26 | }; |
| 29 | 27 | ||
| 30 | struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[] = { | 28 | struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[] = { |
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index c9e38200216b..8fec2cee3e14 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | |||
| @@ -15,26 +15,26 @@ | |||
| 15 | * XXX these should be marked initdata for multi-OMAP kernels | 15 | * XXX these should be marked initdata for multi-OMAP kernels |
| 16 | */ | 16 | */ |
| 17 | #include <linux/power/smartreflex.h> | 17 | #include <linux/power/smartreflex.h> |
| 18 | #include <linux/platform_data/gpio-omap.h> | ||
| 18 | 19 | ||
| 19 | #include <plat/omap_hwmod.h> | 20 | #include <plat/omap_hwmod.h> |
| 20 | #include <mach/irqs.h> | ||
| 21 | #include <plat/cpu.h> | ||
| 22 | #include <plat/dma.h> | 21 | #include <plat/dma.h> |
| 23 | #include <plat/serial.h> | 22 | #include <plat/serial.h> |
| 24 | #include <plat/l3_3xxx.h> | 23 | #include <plat/l3_3xxx.h> |
| 25 | #include <plat/l4_3xxx.h> | 24 | #include <plat/l4_3xxx.h> |
| 26 | #include <plat/i2c.h> | 25 | #include <plat/i2c.h> |
| 27 | #include <plat/gpio.h> | ||
| 28 | #include <plat/mmc.h> | 26 | #include <plat/mmc.h> |
| 29 | #include <plat/mcbsp.h> | 27 | #include <plat/mcbsp.h> |
| 30 | #include <plat/mcspi.h> | 28 | #include <plat/mcspi.h> |
| 31 | #include <plat/dmtimer.h> | 29 | #include <plat/dmtimer.h> |
| 32 | 30 | ||
| 31 | #include <mach/am35xx.h> | ||
| 32 | |||
| 33 | #include "soc.h" | ||
| 33 | #include "omap_hwmod_common_data.h" | 34 | #include "omap_hwmod_common_data.h" |
| 34 | #include "prm-regbits-34xx.h" | 35 | #include "prm-regbits-34xx.h" |
| 35 | #include "cm-regbits-34xx.h" | 36 | #include "cm-regbits-34xx.h" |
| 36 | #include "wd_timer.h" | 37 | #include "wd_timer.h" |
| 37 | #include <mach/am35xx.h> | ||
| 38 | 38 | ||
| 39 | /* | 39 | /* |
| 40 | * OMAP3xxx hardware module integration data | 40 | * OMAP3xxx hardware module integration data |
| @@ -51,9 +51,9 @@ | |||
| 51 | 51 | ||
| 52 | /* L3 */ | 52 | /* L3 */ |
| 53 | static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = { | 53 | static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = { |
| 54 | { .irq = INT_34XX_L3_DBG_IRQ }, | 54 | { .irq = 9 + OMAP_INTC_START, }, |
| 55 | { .irq = INT_34XX_L3_APP_IRQ }, | 55 | { .irq = 10 + OMAP_INTC_START, }, |
| 56 | { .irq = -1 } | 56 | { .irq = -1 }, |
| 57 | }; | 57 | }; |
| 58 | 58 | ||
| 59 | static struct omap_hwmod omap3xxx_l3_main_hwmod = { | 59 | static struct omap_hwmod omap3xxx_l3_main_hwmod = { |
| @@ -100,9 +100,9 @@ static struct omap_hwmod omap3xxx_mpu_hwmod = { | |||
| 100 | 100 | ||
| 101 | /* IVA2 (IVA2) */ | 101 | /* IVA2 (IVA2) */ |
| 102 | static struct omap_hwmod_rst_info omap3xxx_iva_resets[] = { | 102 | static struct omap_hwmod_rst_info omap3xxx_iva_resets[] = { |
| 103 | { .name = "logic", .rst_shift = 0 }, | 103 | { .name = "logic", .rst_shift = 0, .st_shift = 8 }, |
| 104 | { .name = "seq0", .rst_shift = 1 }, | 104 | { .name = "seq0", .rst_shift = 1, .st_shift = 9 }, |
| 105 | { .name = "seq1", .rst_shift = 2 }, | 105 | { .name = "seq1", .rst_shift = 2, .st_shift = 10 }, |
| 106 | }; | 106 | }; |
| 107 | 107 | ||
| 108 | static struct omap_hwmod omap3xxx_iva_hwmod = { | 108 | static struct omap_hwmod omap3xxx_iva_hwmod = { |
| @@ -112,6 +112,15 @@ static struct omap_hwmod omap3xxx_iva_hwmod = { | |||
| 112 | .rst_lines = omap3xxx_iva_resets, | 112 | .rst_lines = omap3xxx_iva_resets, |
| 113 | .rst_lines_cnt = ARRAY_SIZE(omap3xxx_iva_resets), | 113 | .rst_lines_cnt = ARRAY_SIZE(omap3xxx_iva_resets), |
| 114 | .main_clk = "iva2_ck", | 114 | .main_clk = "iva2_ck", |
| 115 | .prcm = { | ||
| 116 | .omap2 = { | ||
| 117 | .module_offs = OMAP3430_IVA2_MOD, | ||
| 118 | .prcm_reg_id = 1, | ||
| 119 | .module_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT, | ||
| 120 | .idlest_reg_id = 1, | ||
| 121 | .idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT, | ||
| 122 | } | ||
| 123 | }, | ||
| 115 | }; | 124 | }; |
| 116 | 125 | ||
| 117 | /* timer class */ | 126 | /* timer class */ |
| @@ -355,8 +364,8 @@ static struct omap_hwmod omap3xxx_timer11_hwmod = { | |||
| 355 | 364 | ||
| 356 | /* timer12 */ | 365 | /* timer12 */ |
| 357 | static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = { | 366 | static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = { |
| 358 | { .irq = 95, }, | 367 | { .irq = 95 + OMAP_INTC_START, }, |
| 359 | { .irq = -1 } | 368 | { .irq = -1 }, |
| 360 | }; | 369 | }; |
| 361 | 370 | ||
| 362 | static struct omap_hwmod omap3xxx_timer12_hwmod = { | 371 | static struct omap_hwmod omap3xxx_timer12_hwmod = { |
| @@ -490,8 +499,8 @@ static struct omap_hwmod omap3xxx_uart3_hwmod = { | |||
| 490 | 499 | ||
| 491 | /* UART4 */ | 500 | /* UART4 */ |
| 492 | static struct omap_hwmod_irq_info uart4_mpu_irqs[] = { | 501 | static struct omap_hwmod_irq_info uart4_mpu_irqs[] = { |
| 493 | { .irq = INT_36XX_UART4_IRQ, }, | 502 | { .irq = 80 + OMAP_INTC_START, }, |
| 494 | { .irq = -1 } | 503 | { .irq = -1 }, |
| 495 | }; | 504 | }; |
| 496 | 505 | ||
| 497 | static struct omap_hwmod_dma_info uart4_sdma_reqs[] = { | 506 | static struct omap_hwmod_dma_info uart4_sdma_reqs[] = { |
| @@ -518,8 +527,8 @@ static struct omap_hwmod omap36xx_uart4_hwmod = { | |||
| 518 | }; | 527 | }; |
| 519 | 528 | ||
| 520 | static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = { | 529 | static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = { |
| 521 | { .irq = INT_35XX_UART4_IRQ, }, | 530 | { .irq = 84 + OMAP_INTC_START, }, |
| 522 | { .irq = -1 } | 531 | { .irq = -1 }, |
| 523 | }; | 532 | }; |
| 524 | 533 | ||
| 525 | static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = { | 534 | static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = { |
| @@ -674,8 +683,8 @@ static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = { | |||
| 674 | }; | 683 | }; |
| 675 | 684 | ||
| 676 | static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = { | 685 | static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = { |
| 677 | { .irq = 25 }, | 686 | { .irq = 25 + OMAP_INTC_START, }, |
| 678 | { .irq = -1 } | 687 | { .irq = -1 }, |
| 679 | }; | 688 | }; |
| 680 | 689 | ||
| 681 | /* dss_dsi1 */ | 690 | /* dss_dsi1 */ |
| @@ -804,8 +813,8 @@ static struct omap_i2c_dev_attr i2c3_dev_attr = { | |||
| 804 | }; | 813 | }; |
| 805 | 814 | ||
| 806 | static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = { | 815 | static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = { |
| 807 | { .irq = INT_34XX_I2C3_IRQ, }, | 816 | { .irq = 61 + OMAP_INTC_START, }, |
| 808 | { .irq = -1 } | 817 | { .irq = -1 }, |
| 809 | }; | 818 | }; |
| 810 | 819 | ||
| 811 | static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = { | 820 | static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = { |
| @@ -963,8 +972,8 @@ static struct omap_hwmod omap3xxx_gpio4_hwmod = { | |||
| 963 | 972 | ||
| 964 | /* gpio5 */ | 973 | /* gpio5 */ |
| 965 | static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = { | 974 | static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = { |
| 966 | { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */ | 975 | { .irq = 33 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK5 */ |
| 967 | { .irq = -1 } | 976 | { .irq = -1 }, |
| 968 | }; | 977 | }; |
| 969 | 978 | ||
| 970 | static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { | 979 | static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { |
| @@ -993,8 +1002,8 @@ static struct omap_hwmod omap3xxx_gpio5_hwmod = { | |||
| 993 | 1002 | ||
| 994 | /* gpio6 */ | 1003 | /* gpio6 */ |
| 995 | static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = { | 1004 | static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = { |
| 996 | { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */ | 1005 | { .irq = 34 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK6 */ |
| 997 | { .irq = -1 } | 1006 | { .irq = -1 }, |
| 998 | }; | 1007 | }; |
| 999 | 1008 | ||
| 1000 | static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { | 1009 | static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { |
| @@ -1098,10 +1107,10 @@ static struct omap_hwmod_opt_clk mcbsp234_opt_clks[] = { | |||
| 1098 | 1107 | ||
| 1099 | /* mcbsp1 */ | 1108 | /* mcbsp1 */ |
| 1100 | static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = { | 1109 | static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = { |
| 1101 | { .name = "common", .irq = 16 }, | 1110 | { .name = "common", .irq = 16 + OMAP_INTC_START, }, |
| 1102 | { .name = "tx", .irq = 59 }, | 1111 | { .name = "tx", .irq = 59 + OMAP_INTC_START, }, |
| 1103 | { .name = "rx", .irq = 60 }, | 1112 | { .name = "rx", .irq = 60 + OMAP_INTC_START, }, |
| 1104 | { .irq = -1 } | 1113 | { .irq = -1 }, |
| 1105 | }; | 1114 | }; |
| 1106 | 1115 | ||
| 1107 | static struct omap_hwmod omap3xxx_mcbsp1_hwmod = { | 1116 | static struct omap_hwmod omap3xxx_mcbsp1_hwmod = { |
| @@ -1125,10 +1134,10 @@ static struct omap_hwmod omap3xxx_mcbsp1_hwmod = { | |||
| 1125 | 1134 | ||
| 1126 | /* mcbsp2 */ | 1135 | /* mcbsp2 */ |
| 1127 | static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = { | 1136 | static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = { |
| 1128 | { .name = "common", .irq = 17 }, | 1137 | { .name = "common", .irq = 17 + OMAP_INTC_START, }, |
| 1129 | { .name = "tx", .irq = 62 }, | 1138 | { .name = "tx", .irq = 62 + OMAP_INTC_START, }, |
| 1130 | { .name = "rx", .irq = 63 }, | 1139 | { .name = "rx", .irq = 63 + OMAP_INTC_START, }, |
| 1131 | { .irq = -1 } | 1140 | { .irq = -1 }, |
| 1132 | }; | 1141 | }; |
| 1133 | 1142 | ||
| 1134 | static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = { | 1143 | static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = { |
| @@ -1157,10 +1166,10 @@ static struct omap_hwmod omap3xxx_mcbsp2_hwmod = { | |||
| 1157 | 1166 | ||
| 1158 | /* mcbsp3 */ | 1167 | /* mcbsp3 */ |
| 1159 | static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = { | 1168 | static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = { |
| 1160 | { .name = "common", .irq = 22 }, | 1169 | { .name = "common", .irq = 22 + OMAP_INTC_START, }, |
| 1161 | { .name = "tx", .irq = 89 }, | 1170 | { .name = "tx", .irq = 89 + OMAP_INTC_START, }, |
| 1162 | { .name = "rx", .irq = 90 }, | 1171 | { .name = "rx", .irq = 90 + OMAP_INTC_START, }, |
| 1163 | { .irq = -1 } | 1172 | { .irq = -1 }, |
| 1164 | }; | 1173 | }; |
| 1165 | 1174 | ||
| 1166 | static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = { | 1175 | static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = { |
| @@ -1189,10 +1198,10 @@ static struct omap_hwmod omap3xxx_mcbsp3_hwmod = { | |||
| 1189 | 1198 | ||
| 1190 | /* mcbsp4 */ | 1199 | /* mcbsp4 */ |
| 1191 | static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = { | 1200 | static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = { |
| 1192 | { .name = "common", .irq = 23 }, | 1201 | { .name = "common", .irq = 23 + OMAP_INTC_START, }, |
| 1193 | { .name = "tx", .irq = 54 }, | 1202 | { .name = "tx", .irq = 54 + OMAP_INTC_START, }, |
| 1194 | { .name = "rx", .irq = 55 }, | 1203 | { .name = "rx", .irq = 55 + OMAP_INTC_START, }, |
| 1195 | { .irq = -1 } | 1204 | { .irq = -1 }, |
| 1196 | }; | 1205 | }; |
| 1197 | 1206 | ||
| 1198 | static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = { | 1207 | static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = { |
| @@ -1222,10 +1231,10 @@ static struct omap_hwmod omap3xxx_mcbsp4_hwmod = { | |||
| 1222 | 1231 | ||
| 1223 | /* mcbsp5 */ | 1232 | /* mcbsp5 */ |
| 1224 | static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = { | 1233 | static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = { |
| 1225 | { .name = "common", .irq = 27 }, | 1234 | { .name = "common", .irq = 27 + OMAP_INTC_START, }, |
| 1226 | { .name = "tx", .irq = 81 }, | 1235 | { .name = "tx", .irq = 81 + OMAP_INTC_START, }, |
| 1227 | { .name = "rx", .irq = 82 }, | 1236 | { .name = "rx", .irq = 82 + OMAP_INTC_START, }, |
| 1228 | { .irq = -1 } | 1237 | { .irq = -1 }, |
| 1229 | }; | 1238 | }; |
| 1230 | 1239 | ||
| 1231 | static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = { | 1240 | static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = { |
| @@ -1267,8 +1276,8 @@ static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = { | |||
| 1267 | 1276 | ||
| 1268 | /* mcbsp2_sidetone */ | 1277 | /* mcbsp2_sidetone */ |
| 1269 | static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = { | 1278 | static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = { |
| 1270 | { .name = "irq", .irq = 4 }, | 1279 | { .name = "irq", .irq = 4 + OMAP_INTC_START, }, |
| 1271 | { .irq = -1 } | 1280 | { .irq = -1 }, |
| 1272 | }; | 1281 | }; |
| 1273 | 1282 | ||
| 1274 | static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = { | 1283 | static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = { |
| @@ -1289,8 +1298,8 @@ static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = { | |||
| 1289 | 1298 | ||
| 1290 | /* mcbsp3_sidetone */ | 1299 | /* mcbsp3_sidetone */ |
| 1291 | static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = { | 1300 | static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = { |
| 1292 | { .name = "irq", .irq = 5 }, | 1301 | { .name = "irq", .irq = 5 + OMAP_INTC_START, }, |
| 1293 | { .irq = -1 } | 1302 | { .irq = -1 }, |
| 1294 | }; | 1303 | }; |
| 1295 | 1304 | ||
| 1296 | static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = { | 1305 | static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = { |
| @@ -1352,8 +1361,8 @@ static struct omap_smartreflex_dev_attr sr1_dev_attr = { | |||
| 1352 | }; | 1361 | }; |
| 1353 | 1362 | ||
| 1354 | static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = { | 1363 | static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = { |
| 1355 | { .irq = 18 }, | 1364 | { .irq = 18 + OMAP_INTC_START, }, |
| 1356 | { .irq = -1 } | 1365 | { .irq = -1 }, |
| 1357 | }; | 1366 | }; |
| 1358 | 1367 | ||
| 1359 | static struct omap_hwmod omap34xx_sr1_hwmod = { | 1368 | static struct omap_hwmod omap34xx_sr1_hwmod = { |
| @@ -1397,8 +1406,8 @@ static struct omap_smartreflex_dev_attr sr2_dev_attr = { | |||
| 1397 | }; | 1406 | }; |
| 1398 | 1407 | ||
| 1399 | static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = { | 1408 | static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = { |
| 1400 | { .irq = 19 }, | 1409 | { .irq = 19 + OMAP_INTC_START, }, |
| 1401 | { .irq = -1 } | 1410 | { .irq = -1 }, |
| 1402 | }; | 1411 | }; |
| 1403 | 1412 | ||
| 1404 | static struct omap_hwmod omap34xx_sr2_hwmod = { | 1413 | static struct omap_hwmod omap34xx_sr2_hwmod = { |
| @@ -1458,8 +1467,8 @@ static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = { | |||
| 1458 | }; | 1467 | }; |
| 1459 | 1468 | ||
| 1460 | static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = { | 1469 | static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = { |
| 1461 | { .irq = 26 }, | 1470 | { .irq = 26 + OMAP_INTC_START, }, |
| 1462 | { .irq = -1 } | 1471 | { .irq = -1 }, |
| 1463 | }; | 1472 | }; |
| 1464 | 1473 | ||
| 1465 | static struct omap_hwmod omap3xxx_mailbox_hwmod = { | 1474 | static struct omap_hwmod omap3xxx_mailbox_hwmod = { |
| @@ -1549,8 +1558,8 @@ static struct omap_hwmod omap34xx_mcspi2 = { | |||
| 1549 | 1558 | ||
| 1550 | /* mcspi3 */ | 1559 | /* mcspi3 */ |
| 1551 | static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = { | 1560 | static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = { |
| 1552 | { .name = "irq", .irq = 91 }, /* 91 */ | 1561 | { .name = "irq", .irq = 91 + OMAP_INTC_START, }, /* 91 */ |
| 1553 | { .irq = -1 } | 1562 | { .irq = -1 }, |
| 1554 | }; | 1563 | }; |
| 1555 | 1564 | ||
| 1556 | static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = { | 1565 | static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = { |
| @@ -1585,8 +1594,8 @@ static struct omap_hwmod omap34xx_mcspi3 = { | |||
| 1585 | 1594 | ||
| 1586 | /* mcspi4 */ | 1595 | /* mcspi4 */ |
| 1587 | static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = { | 1596 | static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = { |
| 1588 | { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */ | 1597 | { .name = "irq", .irq = 48 + OMAP_INTC_START, }, |
| 1589 | { .irq = -1 } | 1598 | { .irq = -1 }, |
| 1590 | }; | 1599 | }; |
| 1591 | 1600 | ||
| 1592 | static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = { | 1601 | static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = { |
| @@ -1638,9 +1647,9 @@ static struct omap_hwmod_class usbotg_class = { | |||
| 1638 | /* usb_otg_hs */ | 1647 | /* usb_otg_hs */ |
| 1639 | static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = { | 1648 | static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = { |
| 1640 | 1649 | ||
| 1641 | { .name = "mc", .irq = 92 }, | 1650 | { .name = "mc", .irq = 92 + OMAP_INTC_START, }, |
| 1642 | { .name = "dma", .irq = 93 }, | 1651 | { .name = "dma", .irq = 93 + OMAP_INTC_START, }, |
| 1643 | { .irq = -1 } | 1652 | { .irq = -1 }, |
| 1644 | }; | 1653 | }; |
| 1645 | 1654 | ||
| 1646 | static struct omap_hwmod omap3xxx_usbhsotg_hwmod = { | 1655 | static struct omap_hwmod omap3xxx_usbhsotg_hwmod = { |
| @@ -1670,8 +1679,8 @@ static struct omap_hwmod omap3xxx_usbhsotg_hwmod = { | |||
| 1670 | 1679 | ||
| 1671 | /* usb_otg_hs */ | 1680 | /* usb_otg_hs */ |
| 1672 | static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = { | 1681 | static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = { |
| 1673 | { .name = "mc", .irq = 71 }, | 1682 | { .name = "mc", .irq = 71 + OMAP_INTC_START, }, |
| 1674 | { .irq = -1 } | 1683 | { .irq = -1 }, |
| 1675 | }; | 1684 | }; |
| 1676 | 1685 | ||
| 1677 | static struct omap_hwmod_class am35xx_usbotg_class = { | 1686 | static struct omap_hwmod_class am35xx_usbotg_class = { |
| @@ -1706,8 +1715,8 @@ static struct omap_hwmod_class omap34xx_mmc_class = { | |||
| 1706 | /* MMC/SD/SDIO1 */ | 1715 | /* MMC/SD/SDIO1 */ |
| 1707 | 1716 | ||
| 1708 | static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = { | 1717 | static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = { |
| 1709 | { .irq = 83, }, | 1718 | { .irq = 83 + OMAP_INTC_START, }, |
| 1710 | { .irq = -1 } | 1719 | { .irq = -1 }, |
| 1711 | }; | 1720 | }; |
| 1712 | 1721 | ||
| 1713 | static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = { | 1722 | static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = { |
| @@ -1773,8 +1782,8 @@ static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = { | |||
| 1773 | /* MMC/SD/SDIO2 */ | 1782 | /* MMC/SD/SDIO2 */ |
| 1774 | 1783 | ||
| 1775 | static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = { | 1784 | static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = { |
| 1776 | { .irq = INT_24XX_MMC2_IRQ, }, | 1785 | { .irq = 86 + OMAP_INTC_START, }, |
| 1777 | { .irq = -1 } | 1786 | { .irq = -1 }, |
| 1778 | }; | 1787 | }; |
| 1779 | 1788 | ||
| 1780 | static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = { | 1789 | static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = { |
| @@ -1834,8 +1843,8 @@ static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = { | |||
| 1834 | /* MMC/SD/SDIO3 */ | 1843 | /* MMC/SD/SDIO3 */ |
| 1835 | 1844 | ||
| 1836 | static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = { | 1845 | static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = { |
| 1837 | { .irq = 94, }, | 1846 | { .irq = 94 + OMAP_INTC_START, }, |
| 1838 | { .irq = -1 } | 1847 | { .irq = -1 }, |
| 1839 | }; | 1848 | }; |
| 1840 | 1849 | ||
| 1841 | static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = { | 1850 | static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = { |
| @@ -1893,9 +1902,9 @@ static struct omap_hwmod_opt_clk omap3xxx_usb_host_hs_opt_clks[] = { | |||
| 1893 | }; | 1902 | }; |
| 1894 | 1903 | ||
| 1895 | static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs[] = { | 1904 | static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs[] = { |
| 1896 | { .name = "ohci-irq", .irq = 76 }, | 1905 | { .name = "ohci-irq", .irq = 76 + OMAP_INTC_START, }, |
| 1897 | { .name = "ehci-irq", .irq = 77 }, | 1906 | { .name = "ehci-irq", .irq = 77 + OMAP_INTC_START, }, |
| 1898 | { .irq = -1 } | 1907 | { .irq = -1 }, |
| 1899 | }; | 1908 | }; |
| 1900 | 1909 | ||
| 1901 | static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = { | 1910 | static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = { |
| @@ -1987,8 +1996,8 @@ static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = { | |||
| 1987 | }; | 1996 | }; |
| 1988 | 1997 | ||
| 1989 | static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = { | 1998 | static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = { |
| 1990 | { .name = "tll-irq", .irq = 78 }, | 1999 | { .name = "tll-irq", .irq = 78 + OMAP_INTC_START, }, |
| 1991 | { .irq = -1 } | 2000 | { .irq = -1 }, |
| 1992 | }; | 2001 | }; |
| 1993 | 2002 | ||
| 1994 | static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = { | 2003 | static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = { |
| @@ -3214,11 +3223,11 @@ static struct omap_hwmod_ocp_if am35xx_l4_core__mdio = { | |||
| 3214 | }; | 3223 | }; |
| 3215 | 3224 | ||
| 3216 | static struct omap_hwmod_irq_info am35xx_emac_mpu_irqs[] = { | 3225 | static struct omap_hwmod_irq_info am35xx_emac_mpu_irqs[] = { |
| 3217 | { .name = "rxthresh", .irq = INT_35XX_EMAC_C0_RXTHRESH_IRQ }, | 3226 | { .name = "rxthresh", .irq = 67 + OMAP_INTC_START, }, |
| 3218 | { .name = "rx_pulse", .irq = INT_35XX_EMAC_C0_RX_PULSE_IRQ }, | 3227 | { .name = "rx_pulse", .irq = 68 + OMAP_INTC_START, }, |
| 3219 | { .name = "tx_pulse", .irq = INT_35XX_EMAC_C0_TX_PULSE_IRQ }, | 3228 | { .name = "tx_pulse", .irq = 69 + OMAP_INTC_START }, |
| 3220 | { .name = "misc_pulse", .irq = INT_35XX_EMAC_C0_MISC_PULSE_IRQ }, | 3229 | { .name = "misc_pulse", .irq = 70 + OMAP_INTC_START }, |
| 3221 | { .irq = -1 } | 3230 | { .irq = -1 }, |
| 3222 | }; | 3231 | }; |
| 3223 | 3232 | ||
| 3224 | static struct omap_hwmod_class am35xx_emac_class = { | 3233 | static struct omap_hwmod_class am35xx_emac_class = { |
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 242aee498ceb..110be87cd995 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c | |||
| @@ -19,12 +19,11 @@ | |||
| 19 | */ | 19 | */ |
| 20 | 20 | ||
| 21 | #include <linux/io.h> | 21 | #include <linux/io.h> |
| 22 | #include <linux/platform_data/gpio-omap.h> | ||
| 22 | #include <linux/power/smartreflex.h> | 23 | #include <linux/power/smartreflex.h> |
| 23 | 24 | ||
| 24 | #include <plat/omap_hwmod.h> | 25 | #include <plat/omap_hwmod.h> |
| 25 | #include <plat/cpu.h> | ||
| 26 | #include <plat/i2c.h> | 26 | #include <plat/i2c.h> |
| 27 | #include <plat/gpio.h> | ||
| 28 | #include <plat/dma.h> | 27 | #include <plat/dma.h> |
| 29 | #include <plat/mcspi.h> | 28 | #include <plat/mcspi.h> |
| 30 | #include <plat/mcbsp.h> | 29 | #include <plat/mcbsp.h> |
| @@ -4210,7 +4209,7 @@ static struct omap_hwmod_ocp_if omap44xx_dsp__iva = { | |||
| 4210 | }; | 4209 | }; |
| 4211 | 4210 | ||
| 4212 | /* dsp -> sl2if */ | 4211 | /* dsp -> sl2if */ |
| 4213 | static struct omap_hwmod_ocp_if omap44xx_dsp__sl2if = { | 4212 | static struct omap_hwmod_ocp_if __maybe_unused omap44xx_dsp__sl2if = { |
| 4214 | .master = &omap44xx_dsp_hwmod, | 4213 | .master = &omap44xx_dsp_hwmod, |
| 4215 | .slave = &omap44xx_sl2if_hwmod, | 4214 | .slave = &omap44xx_sl2if_hwmod, |
| 4216 | .clk = "dpll_iva_m5x2_ck", | 4215 | .clk = "dpll_iva_m5x2_ck", |
| @@ -4828,7 +4827,7 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = { | |||
| 4828 | }; | 4827 | }; |
| 4829 | 4828 | ||
| 4830 | /* iva -> sl2if */ | 4829 | /* iva -> sl2if */ |
| 4831 | static struct omap_hwmod_ocp_if omap44xx_iva__sl2if = { | 4830 | static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = { |
| 4832 | .master = &omap44xx_iva_hwmod, | 4831 | .master = &omap44xx_iva_hwmod, |
| 4833 | .slave = &omap44xx_sl2if_hwmod, | 4832 | .slave = &omap44xx_sl2if_hwmod, |
| 4834 | .clk = "dpll_iva_m5x2_ck", | 4833 | .clk = "dpll_iva_m5x2_ck", |
| @@ -5362,7 +5361,7 @@ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = { | |||
| 5362 | }; | 5361 | }; |
| 5363 | 5362 | ||
| 5364 | /* l3_main_2 -> sl2if */ | 5363 | /* l3_main_2 -> sl2if */ |
| 5365 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__sl2if = { | 5364 | static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if = { |
| 5366 | .master = &omap44xx_l3_main_2_hwmod, | 5365 | .master = &omap44xx_l3_main_2_hwmod, |
| 5367 | .slave = &omap44xx_sl2if_hwmod, | 5366 | .slave = &omap44xx_sl2if_hwmod, |
| 5368 | .clk = "l3_div_ck", | 5367 | .clk = "l3_div_ck", |
| @@ -6032,7 +6031,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { | |||
| 6032 | &omap44xx_l4_abe__dmic, | 6031 | &omap44xx_l4_abe__dmic, |
| 6033 | &omap44xx_l4_abe__dmic_dma, | 6032 | &omap44xx_l4_abe__dmic_dma, |
| 6034 | &omap44xx_dsp__iva, | 6033 | &omap44xx_dsp__iva, |
| 6035 | &omap44xx_dsp__sl2if, | 6034 | /* &omap44xx_dsp__sl2if, */ |
| 6036 | &omap44xx_l4_cfg__dsp, | 6035 | &omap44xx_l4_cfg__dsp, |
| 6037 | &omap44xx_l3_main_2__dss, | 6036 | &omap44xx_l3_main_2__dss, |
| 6038 | &omap44xx_l4_per__dss, | 6037 | &omap44xx_l4_per__dss, |
| @@ -6068,7 +6067,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { | |||
| 6068 | &omap44xx_l4_per__i2c4, | 6067 | &omap44xx_l4_per__i2c4, |
| 6069 | &omap44xx_l3_main_2__ipu, | 6068 | &omap44xx_l3_main_2__ipu, |
| 6070 | &omap44xx_l3_main_2__iss, | 6069 | &omap44xx_l3_main_2__iss, |
| 6071 | &omap44xx_iva__sl2if, | 6070 | /* &omap44xx_iva__sl2if, */ |
| 6072 | &omap44xx_l3_main_2__iva, | 6071 | &omap44xx_l3_main_2__iva, |
| 6073 | &omap44xx_l4_wkup__kbd, | 6072 | &omap44xx_l4_wkup__kbd, |
| 6074 | &omap44xx_l4_cfg__mailbox, | 6073 | &omap44xx_l4_cfg__mailbox, |
| @@ -6099,7 +6098,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { | |||
| 6099 | &omap44xx_l4_cfg__cm_core, | 6098 | &omap44xx_l4_cfg__cm_core, |
| 6100 | &omap44xx_l4_wkup__prm, | 6099 | &omap44xx_l4_wkup__prm, |
| 6101 | &omap44xx_l4_wkup__scrm, | 6100 | &omap44xx_l4_wkup__scrm, |
| 6102 | &omap44xx_l3_main_2__sl2if, | 6101 | /* &omap44xx_l3_main_2__sl2if, */ |
| 6103 | &omap44xx_l4_abe__slimbus1, | 6102 | &omap44xx_l4_abe__slimbus1, |
| 6104 | &omap44xx_l4_abe__slimbus1_dma, | 6103 | &omap44xx_l4_abe__slimbus1_dma, |
| 6105 | &omap44xx_l4_per__slimbus2, | 6104 | &omap44xx_l4_per__slimbus2, |
diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.h b/arch/arm/mach-omap2/omap_hwmod_common_data.h index e7e8eeae95e5..dddb677fed68 100644 --- a/arch/arm/mach-omap2/omap_hwmod_common_data.h +++ b/arch/arm/mach-omap2/omap_hwmod_common_data.h | |||
| @@ -16,6 +16,7 @@ | |||
| 16 | 16 | ||
| 17 | #include <plat/omap_hwmod.h> | 17 | #include <plat/omap_hwmod.h> |
| 18 | 18 | ||
| 19 | #include "common.h" | ||
| 19 | #include "display.h" | 20 | #include "display.h" |
| 20 | 21 | ||
| 21 | /* Common address space across OMAP2xxx */ | 22 | /* Common address space across OMAP2xxx */ |
diff --git a/arch/arm/mach-omap2/omap_l3_noc.c b/arch/arm/mach-omap2/omap_l3_noc.c index d15225ff5c49..f447e02102bb 100644 --- a/arch/arm/mach-omap2/omap_l3_noc.c +++ b/arch/arm/mach-omap2/omap_l3_noc.c | |||
| @@ -28,6 +28,7 @@ | |||
| 28 | #include <linux/kernel.h> | 28 | #include <linux/kernel.h> |
| 29 | #include <linux/slab.h> | 29 | #include <linux/slab.h> |
| 30 | 30 | ||
| 31 | #include "soc.h" | ||
| 31 | #include "omap_l3_noc.h" | 32 | #include "omap_l3_noc.h" |
| 32 | 33 | ||
| 33 | /* | 34 | /* |
| @@ -190,7 +191,7 @@ static int __devinit omap4_l3_probe(struct platform_device *pdev) | |||
| 190 | IRQF_DISABLED, "l3-dbg-irq", l3); | 191 | IRQF_DISABLED, "l3-dbg-irq", l3); |
| 191 | if (ret) { | 192 | if (ret) { |
| 192 | pr_crit("L3: request_irq failed to register for 0x%x\n", | 193 | pr_crit("L3: request_irq failed to register for 0x%x\n", |
| 193 | OMAP44XX_IRQ_L3_DBG); | 194 | 9 + OMAP44XX_IRQ_GIC_START); |
| 194 | goto err3; | 195 | goto err3; |
| 195 | } | 196 | } |
| 196 | 197 | ||
| @@ -200,7 +201,7 @@ static int __devinit omap4_l3_probe(struct platform_device *pdev) | |||
| 200 | IRQF_DISABLED, "l3-app-irq", l3); | 201 | IRQF_DISABLED, "l3-app-irq", l3); |
| 201 | if (ret) { | 202 | if (ret) { |
| 202 | pr_crit("L3: request_irq failed to register for 0x%x\n", | 203 | pr_crit("L3: request_irq failed to register for 0x%x\n", |
| 203 | OMAP44XX_IRQ_L3_APP); | 204 | 10 + OMAP44XX_IRQ_GIC_START); |
| 204 | goto err4; | 205 | goto err4; |
| 205 | } | 206 | } |
| 206 | 207 | ||
diff --git a/arch/arm/mach-omap2/omap_phy_internal.c b/arch/arm/mach-omap2/omap_phy_internal.c index d52651a05daa..593eaea35cec 100644 --- a/arch/arm/mach-omap2/omap_phy_internal.c +++ b/arch/arm/mach-omap2/omap_phy_internal.c | |||
| @@ -29,6 +29,8 @@ | |||
| 29 | #include <linux/usb.h> | 29 | #include <linux/usb.h> |
| 30 | 30 | ||
| 31 | #include <plat/usb.h> | 31 | #include <plat/usb.h> |
| 32 | |||
| 33 | #include "soc.h" | ||
| 32 | #include "control.h" | 34 | #include "control.h" |
| 33 | 35 | ||
| 34 | /* OMAP control module register for UTMI PHY */ | 36 | /* OMAP control module register for UTMI PHY */ |
diff --git a/arch/arm/mach-omap2/opp2420_data.c b/arch/arm/mach-omap2/opp2420_data.c index 5037e76e4e23..a9e8cf21705d 100644 --- a/arch/arm/mach-omap2/opp2420_data.c +++ b/arch/arm/mach-omap2/opp2420_data.c | |||
| @@ -28,7 +28,7 @@ | |||
| 28 | * http://repository.maemo.org/pool/diablo/free/k/kernel-source-diablo/ | 28 | * http://repository.maemo.org/pool/diablo/free/k/kernel-source-diablo/ |
| 29 | */ | 29 | */ |
| 30 | 30 | ||
| 31 | #include <plat/hardware.h> | 31 | #include <linux/kernel.h> |
| 32 | 32 | ||
| 33 | #include "opp2xxx.h" | 33 | #include "opp2xxx.h" |
| 34 | #include "sdrc.h" | 34 | #include "sdrc.h" |
diff --git a/arch/arm/mach-omap2/opp2430_data.c b/arch/arm/mach-omap2/opp2430_data.c index 750805c528d8..0e75ec3e114b 100644 --- a/arch/arm/mach-omap2/opp2430_data.c +++ b/arch/arm/mach-omap2/opp2430_data.c | |||
| @@ -26,7 +26,7 @@ | |||
| 26 | * This is technically part of the OMAP2xxx clock code. | 26 | * This is technically part of the OMAP2xxx clock code. |
| 27 | */ | 27 | */ |
| 28 | 28 | ||
| 29 | #include <plat/hardware.h> | 29 | #include <linux/kernel.h> |
| 30 | 30 | ||
| 31 | #include "opp2xxx.h" | 31 | #include "opp2xxx.h" |
| 32 | #include "sdrc.h" | 32 | #include "sdrc.h" |
diff --git a/arch/arm/mach-omap2/opp3xxx_data.c b/arch/arm/mach-omap2/opp3xxx_data.c index d95f3f945d4a..75cef5f67a8a 100644 --- a/arch/arm/mach-omap2/opp3xxx_data.c +++ b/arch/arm/mach-omap2/opp3xxx_data.c | |||
| @@ -19,8 +19,6 @@ | |||
| 19 | */ | 19 | */ |
| 20 | #include <linux/module.h> | 20 | #include <linux/module.h> |
| 21 | 21 | ||
| 22 | #include <plat/cpu.h> | ||
| 23 | |||
| 24 | #include "control.h" | 22 | #include "control.h" |
| 25 | #include "omap_opp_data.h" | 23 | #include "omap_opp_data.h" |
| 26 | #include "pm.h" | 24 | #include "pm.h" |
diff --git a/arch/arm/mach-omap2/opp4xxx_data.c b/arch/arm/mach-omap2/opp4xxx_data.c index c95415da23c2..a9fd6d5fe79e 100644 --- a/arch/arm/mach-omap2/opp4xxx_data.c +++ b/arch/arm/mach-omap2/opp4xxx_data.c | |||
| @@ -20,8 +20,7 @@ | |||
| 20 | */ | 20 | */ |
| 21 | #include <linux/module.h> | 21 | #include <linux/module.h> |
| 22 | 22 | ||
| 23 | #include <plat/cpu.h> | 23 | #include "soc.h" |
| 24 | |||
| 25 | #include "control.h" | 24 | #include "control.h" |
| 26 | #include "omap_opp_data.h" | 25 | #include "omap_opp_data.h" |
| 27 | #include "pm.h" | 26 | #include "pm.h" |
diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c index 814bcd901596..3e1345fc0713 100644 --- a/arch/arm/mach-omap2/pm-debug.c +++ b/arch/arm/mach-omap2/pm-debug.c | |||
| @@ -28,7 +28,6 @@ | |||
| 28 | #include <linux/slab.h> | 28 | #include <linux/slab.h> |
| 29 | 29 | ||
| 30 | #include <plat/clock.h> | 30 | #include <plat/clock.h> |
| 31 | #include <plat/board.h> | ||
| 32 | #include "powerdomain.h" | 31 | #include "powerdomain.h" |
| 33 | #include "clockdomain.h" | 32 | #include "clockdomain.h" |
| 34 | #include <plat/dmtimer.h> | 33 | #include <plat/dmtimer.h> |
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c index 2edeffc923a6..8af6cd6ac331 100644 --- a/arch/arm/mach-omap2/pm24xx.c +++ b/arch/arm/mach-omap2/pm24xx.c | |||
| @@ -29,6 +29,7 @@ | |||
| 29 | #include <linux/irq.h> | 29 | #include <linux/irq.h> |
| 30 | #include <linux/time.h> | 30 | #include <linux/time.h> |
| 31 | #include <linux/gpio.h> | 31 | #include <linux/gpio.h> |
| 32 | #include <linux/platform_data/gpio-omap.h> | ||
| 32 | 33 | ||
| 33 | #include <asm/mach/time.h> | 34 | #include <asm/mach/time.h> |
| 34 | #include <asm/mach/irq.h> | 35 | #include <asm/mach/irq.h> |
| @@ -38,9 +39,6 @@ | |||
| 38 | #include <plat/clock.h> | 39 | #include <plat/clock.h> |
| 39 | #include <plat/sram.h> | 40 | #include <plat/sram.h> |
| 40 | #include <plat/dma.h> | 41 | #include <plat/dma.h> |
| 41 | #include <plat/board.h> | ||
| 42 | |||
| 43 | #include <mach/irqs.h> | ||
| 44 | 42 | ||
| 45 | #include "common.h" | 43 | #include "common.h" |
| 46 | #include "prm2xxx_3xxx.h" | 44 | #include "prm2xxx_3xxx.h" |
| @@ -352,16 +350,6 @@ int __init omap2_pm_init(void) | |||
| 352 | 350 | ||
| 353 | prcm_setup_regs(); | 351 | prcm_setup_regs(); |
| 354 | 352 | ||
| 355 | /* Hack to prevent MPU retention when STI console is enabled. */ | ||
| 356 | { | ||
| 357 | const struct omap_sti_console_config *sti; | ||
| 358 | |||
| 359 | sti = omap_get_config(OMAP_TAG_STI_CONSOLE, | ||
| 360 | struct omap_sti_console_config); | ||
| 361 | if (sti != NULL && sti->enable) | ||
| 362 | sti_console_enabled = 1; | ||
| 363 | } | ||
| 364 | |||
| 365 | /* | 353 | /* |
| 366 | * We copy the assembler sleep/wakeup routines to SRAM. | 354 | * We copy the assembler sleep/wakeup routines to SRAM. |
| 367 | * These routines need to be in SRAM as that's the only | 355 | * These routines need to be in SRAM as that's the only |
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index 05bd8f02723f..90480f759974 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c | |||
| @@ -28,6 +28,8 @@ | |||
| 28 | #include <linux/clk.h> | 28 | #include <linux/clk.h> |
| 29 | #include <linux/delay.h> | 29 | #include <linux/delay.h> |
| 30 | #include <linux/slab.h> | 30 | #include <linux/slab.h> |
| 31 | #include <linux/platform_data/gpio-omap.h> | ||
| 32 | |||
| 31 | #include <trace/events/power.h> | 33 | #include <trace/events/power.h> |
| 32 | 34 | ||
| 33 | #include <asm/suspend.h> | 35 | #include <asm/suspend.h> |
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c index 69b36e185e9b..ca5be83d5019 100644 --- a/arch/arm/mach-omap2/powerdomain.c +++ b/arch/arm/mach-omap2/powerdomain.c | |||
| @@ -28,11 +28,13 @@ | |||
| 28 | #include "prm44xx.h" | 28 | #include "prm44xx.h" |
| 29 | 29 | ||
| 30 | #include <asm/cpu.h> | 30 | #include <asm/cpu.h> |
| 31 | #include <plat/cpu.h> | 31 | |
| 32 | #include <plat/prcm.h> | ||
| 33 | |||
| 32 | #include "powerdomain.h" | 34 | #include "powerdomain.h" |
| 33 | #include "clockdomain.h" | 35 | #include "clockdomain.h" |
| 34 | #include <plat/prcm.h> | ||
| 35 | 36 | ||
| 37 | #include "soc.h" | ||
| 36 | #include "pm.h" | 38 | #include "pm.h" |
| 37 | 39 | ||
| 38 | #define PWRDM_TRACE_STATES_FLAG (1<<31) | 40 | #define PWRDM_TRACE_STATES_FLAG (1<<31) |
diff --git a/arch/arm/mach-omap2/powerdomains3xxx_data.c b/arch/arm/mach-omap2/powerdomains3xxx_data.c index bb883e463078..8b23d234fb55 100644 --- a/arch/arm/mach-omap2/powerdomains3xxx_data.c +++ b/arch/arm/mach-omap2/powerdomains3xxx_data.c | |||
| @@ -15,11 +15,9 @@ | |||
| 15 | #include <linux/init.h> | 15 | #include <linux/init.h> |
| 16 | #include <linux/bug.h> | 16 | #include <linux/bug.h> |
| 17 | 17 | ||
| 18 | #include <plat/cpu.h> | 18 | #include "soc.h" |
| 19 | |||
| 20 | #include "powerdomain.h" | 19 | #include "powerdomain.h" |
| 21 | #include "powerdomains2xxx_3xxx_data.h" | 20 | #include "powerdomains2xxx_3xxx_data.h" |
| 22 | |||
| 23 | #include "prcm-common.h" | 21 | #include "prcm-common.h" |
| 24 | #include "prm2xxx_3xxx.h" | 22 | #include "prm2xxx_3xxx.h" |
| 25 | #include "prm-regbits-34xx.h" | 23 | #include "prm-regbits-34xx.h" |
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c index 053e24ed3c48..9c9d23c10205 100644 --- a/arch/arm/mach-omap2/prcm.c +++ b/arch/arm/mach-omap2/prcm.c | |||
| @@ -27,7 +27,6 @@ | |||
| 27 | 27 | ||
| 28 | #include "common.h" | 28 | #include "common.h" |
| 29 | #include <plat/prcm.h> | 29 | #include <plat/prcm.h> |
| 30 | #include <plat/irqs.h> | ||
| 31 | 30 | ||
| 32 | #include "clock.h" | 31 | #include "clock.h" |
| 33 | #include "clock2xxx.h" | 32 | #include "clock2xxx.h" |
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c index a0309dea6794..9529984d8d2b 100644 --- a/arch/arm/mach-omap2/prm2xxx_3xxx.c +++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c | |||
| @@ -17,11 +17,10 @@ | |||
| 17 | #include <linux/io.h> | 17 | #include <linux/io.h> |
| 18 | #include <linux/irq.h> | 18 | #include <linux/irq.h> |
| 19 | 19 | ||
| 20 | #include "common.h" | ||
| 21 | #include <plat/cpu.h> | ||
| 22 | #include <plat/prcm.h> | 20 | #include <plat/prcm.h> |
| 23 | #include <plat/irqs.h> | ||
| 24 | 21 | ||
| 22 | #include "soc.h" | ||
| 23 | #include "common.h" | ||
| 25 | #include "vp.h" | 24 | #include "vp.h" |
| 26 | 25 | ||
| 27 | #include "prm2xxx_3xxx.h" | 26 | #include "prm2xxx_3xxx.h" |
| @@ -40,7 +39,7 @@ static struct omap_prcm_irq_setup omap3_prcm_irq_setup = { | |||
| 40 | .nr_regs = 1, | 39 | .nr_regs = 1, |
| 41 | .irqs = omap3_prcm_irqs, | 40 | .irqs = omap3_prcm_irqs, |
| 42 | .nr_irqs = ARRAY_SIZE(omap3_prcm_irqs), | 41 | .nr_irqs = ARRAY_SIZE(omap3_prcm_irqs), |
| 43 | .irq = INT_34XX_PRCM_MPU_IRQ, | 42 | .irq = 11 + OMAP_INTC_START, |
| 44 | .read_pending_irqs = &omap3xxx_prm_read_pending_irqs, | 43 | .read_pending_irqs = &omap3xxx_prm_read_pending_irqs, |
| 45 | .ocp_barrier = &omap3xxx_prm_ocp_barrier, | 44 | .ocp_barrier = &omap3xxx_prm_ocp_barrier, |
| 46 | .save_and_clear_irqen = &omap3xxx_prm_save_and_clear_irqen, | 45 | .save_and_clear_irqen = &omap3xxx_prm_save_and_clear_irqen, |
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c index bb727c2d9337..f0c4d5f4a174 100644 --- a/arch/arm/mach-omap2/prm44xx.c +++ b/arch/arm/mach-omap2/prm44xx.c | |||
| @@ -17,10 +17,9 @@ | |||
| 17 | #include <linux/err.h> | 17 | #include <linux/err.h> |
| 18 | #include <linux/io.h> | 18 | #include <linux/io.h> |
| 19 | 19 | ||
| 20 | #include <plat/cpu.h> | ||
| 21 | #include <plat/irqs.h> | ||
| 22 | #include <plat/prcm.h> | 20 | #include <plat/prcm.h> |
| 23 | 21 | ||
| 22 | #include "soc.h" | ||
| 24 | #include "iomap.h" | 23 | #include "iomap.h" |
| 25 | #include "common.h" | 24 | #include "common.h" |
| 26 | #include "vp.h" | 25 | #include "vp.h" |
| @@ -40,7 +39,7 @@ static struct omap_prcm_irq_setup omap4_prcm_irq_setup = { | |||
| 40 | .nr_regs = 2, | 39 | .nr_regs = 2, |
| 41 | .irqs = omap4_prcm_irqs, | 40 | .irqs = omap4_prcm_irqs, |
| 42 | .nr_irqs = ARRAY_SIZE(omap4_prcm_irqs), | 41 | .nr_irqs = ARRAY_SIZE(omap4_prcm_irqs), |
| 43 | .irq = OMAP44XX_IRQ_PRCM, | 42 | .irq = 11 + OMAP44XX_IRQ_GIC_START, |
| 44 | .read_pending_irqs = &omap44xx_prm_read_pending_irqs, | 43 | .read_pending_irqs = &omap44xx_prm_read_pending_irqs, |
| 45 | .ocp_barrier = &omap44xx_prm_ocp_barrier, | 44 | .ocp_barrier = &omap44xx_prm_ocp_barrier, |
| 46 | .save_and_clear_irqen = &omap44xx_prm_save_and_clear_irqen, | 45 | .save_and_clear_irqen = &omap44xx_prm_save_and_clear_irqen, |
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c index 03b126d9ad94..6b4d332be2f6 100644 --- a/arch/arm/mach-omap2/prm_common.c +++ b/arch/arm/mach-omap2/prm_common.c | |||
| @@ -26,7 +26,6 @@ | |||
| 26 | 26 | ||
| 27 | #include <plat/common.h> | 27 | #include <plat/common.h> |
| 28 | #include <plat/prcm.h> | 28 | #include <plat/prcm.h> |
| 29 | #include <plat/irqs.h> | ||
| 30 | 29 | ||
| 31 | #include "prm2xxx_3xxx.h" | 30 | #include "prm2xxx_3xxx.h" |
| 32 | #include "prm44xx.h" | 31 | #include "prm44xx.h" |
diff --git a/arch/arm/mach-omap2/sdrc2xxx.c b/arch/arm/mach-omap2/sdrc2xxx.c index 1133bb2f632b..73e55e485329 100644 --- a/arch/arm/mach-omap2/sdrc2xxx.c +++ b/arch/arm/mach-omap2/sdrc2xxx.c | |||
| @@ -24,11 +24,11 @@ | |||
| 24 | #include <linux/clk.h> | 24 | #include <linux/clk.h> |
| 25 | #include <linux/io.h> | 25 | #include <linux/io.h> |
| 26 | 26 | ||
| 27 | #include <plat/hardware.h> | ||
| 28 | #include <plat/clock.h> | 27 | #include <plat/clock.h> |
| 29 | #include <plat/sram.h> | 28 | #include <plat/sram.h> |
| 30 | #include <plat/sdrc.h> | 29 | #include <plat/sdrc.h> |
| 31 | 30 | ||
| 31 | #include "soc.h" | ||
| 32 | #include "iomap.h" | 32 | #include "iomap.h" |
| 33 | #include "common.h" | 33 | #include "common.h" |
| 34 | #include "prm2xxx_3xxx.h" | 34 | #include "prm2xxx_3xxx.h" |
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c index c1b93c752d70..7ca266e987f6 100644 --- a/arch/arm/mach-omap2/serial.c +++ b/arch/arm/mach-omap2/serial.c | |||
| @@ -29,11 +29,11 @@ | |||
| 29 | 29 | ||
| 30 | #include <plat/omap-serial.h> | 30 | #include <plat/omap-serial.h> |
| 31 | #include "common.h" | 31 | #include "common.h" |
| 32 | #include <plat/board.h> | ||
| 33 | #include <plat/dma.h> | 32 | #include <plat/dma.h> |
| 34 | #include <plat/omap_hwmod.h> | 33 | #include <plat/omap_hwmod.h> |
| 35 | #include <plat/omap_device.h> | 34 | #include <plat/omap_device.h> |
| 36 | #include <plat/omap-pm.h> | 35 | #include <plat/omap-pm.h> |
| 36 | #include <plat/serial.h> | ||
| 37 | 37 | ||
| 38 | #include "prm2xxx_3xxx.h" | 38 | #include "prm2xxx_3xxx.h" |
| 39 | #include "pm.h" | 39 | #include "pm.h" |
| @@ -81,8 +81,9 @@ static struct omap_uart_port_info omap_serial_default_info[] __initdata = { | |||
| 81 | }; | 81 | }; |
| 82 | 82 | ||
| 83 | #ifdef CONFIG_PM | 83 | #ifdef CONFIG_PM |
| 84 | static void omap_uart_enable_wakeup(struct platform_device *pdev, bool enable) | 84 | static void omap_uart_enable_wakeup(struct device *dev, bool enable) |
| 85 | { | 85 | { |
| 86 | struct platform_device *pdev = to_platform_device(dev); | ||
| 86 | struct omap_device *od = to_omap_device(pdev); | 87 | struct omap_device *od = to_omap_device(pdev); |
| 87 | 88 | ||
| 88 | if (!od) | 89 | if (!od) |
| @@ -99,15 +100,17 @@ static void omap_uart_enable_wakeup(struct platform_device *pdev, bool enable) | |||
| 99 | * in Smartidle Mode When Configured for DMA Operations. | 100 | * in Smartidle Mode When Configured for DMA Operations. |
| 100 | * WA: configure uart in force idle mode. | 101 | * WA: configure uart in force idle mode. |
| 101 | */ | 102 | */ |
| 102 | static void omap_uart_set_noidle(struct platform_device *pdev) | 103 | static void omap_uart_set_noidle(struct device *dev) |
| 103 | { | 104 | { |
| 105 | struct platform_device *pdev = to_platform_device(dev); | ||
| 104 | struct omap_device *od = to_omap_device(pdev); | 106 | struct omap_device *od = to_omap_device(pdev); |
| 105 | 107 | ||
| 106 | omap_hwmod_set_slave_idlemode(od->hwmods[0], HWMOD_IDLEMODE_NO); | 108 | omap_hwmod_set_slave_idlemode(od->hwmods[0], HWMOD_IDLEMODE_NO); |
| 107 | } | 109 | } |
| 108 | 110 | ||
| 109 | static void omap_uart_set_smartidle(struct platform_device *pdev) | 111 | static void omap_uart_set_smartidle(struct device *dev) |
| 110 | { | 112 | { |
| 113 | struct platform_device *pdev = to_platform_device(dev); | ||
| 111 | struct omap_device *od = to_omap_device(pdev); | 114 | struct omap_device *od = to_omap_device(pdev); |
| 112 | u8 idlemode; | 115 | u8 idlemode; |
| 113 | 116 | ||
| @@ -120,10 +123,10 @@ static void omap_uart_set_smartidle(struct platform_device *pdev) | |||
| 120 | } | 123 | } |
| 121 | 124 | ||
| 122 | #else | 125 | #else |
| 123 | static void omap_uart_enable_wakeup(struct platform_device *pdev, bool enable) | 126 | static void omap_uart_enable_wakeup(struct device *dev, bool enable) |
| 124 | {} | 127 | {} |
| 125 | static void omap_uart_set_noidle(struct platform_device *pdev) {} | 128 | static void omap_uart_set_noidle(struct device *dev) {} |
| 126 | static void omap_uart_set_smartidle(struct platform_device *pdev) {} | 129 | static void omap_uart_set_smartidle(struct device *dev) {} |
| 127 | #endif /* CONFIG_PM */ | 130 | #endif /* CONFIG_PM */ |
| 128 | 131 | ||
| 129 | #ifdef CONFIG_OMAP_MUX | 132 | #ifdef CONFIG_OMAP_MUX |
| @@ -304,6 +307,9 @@ void __init omap_serial_init_port(struct omap_board_data *bdata, | |||
| 304 | omap_up.dma_rx_timeout = info->dma_rx_timeout; | 307 | omap_up.dma_rx_timeout = info->dma_rx_timeout; |
| 305 | omap_up.dma_rx_poll_rate = info->dma_rx_poll_rate; | 308 | omap_up.dma_rx_poll_rate = info->dma_rx_poll_rate; |
| 306 | omap_up.autosuspend_timeout = info->autosuspend_timeout; | 309 | omap_up.autosuspend_timeout = info->autosuspend_timeout; |
| 310 | omap_up.DTR_gpio = info->DTR_gpio; | ||
| 311 | omap_up.DTR_inverted = info->DTR_inverted; | ||
| 312 | omap_up.DTR_present = info->DTR_present; | ||
| 307 | 313 | ||
| 308 | pdata = &omap_up; | 314 | pdata = &omap_up; |
| 309 | pdata_size = sizeof(struct omap_uart_port_info); | 315 | pdata_size = sizeof(struct omap_uart_port_info); |
diff --git a/arch/arm/mach-omap2/sleep24xx.S b/arch/arm/mach-omap2/sleep24xx.S index d4bf904d84ab..ce0ccd26efbd 100644 --- a/arch/arm/mach-omap2/sleep24xx.S +++ b/arch/arm/mach-omap2/sleep24xx.S | |||
| @@ -28,8 +28,7 @@ | |||
| 28 | #include <linux/linkage.h> | 28 | #include <linux/linkage.h> |
| 29 | #include <asm/assembler.h> | 29 | #include <asm/assembler.h> |
| 30 | 30 | ||
| 31 | #include <plat/omap24xx.h> | 31 | #include "omap24xx.h" |
| 32 | |||
| 33 | #include "sdrc.h" | 32 | #include "sdrc.h" |
| 34 | 33 | ||
| 35 | /* First address of reserved address space? apparently valid for OMAP2 & 3 */ | 34 | /* First address of reserved address space? apparently valid for OMAP2 & 3 */ |
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S index 1f62f23673fb..506987979c1c 100644 --- a/arch/arm/mach-omap2/sleep34xx.S +++ b/arch/arm/mach-omap2/sleep34xx.S | |||
| @@ -26,9 +26,9 @@ | |||
| 26 | 26 | ||
| 27 | #include <asm/assembler.h> | 27 | #include <asm/assembler.h> |
| 28 | 28 | ||
| 29 | #include <plat/hardware.h> | ||
| 30 | #include <plat/sram.h> | 29 | #include <plat/sram.h> |
| 31 | 30 | ||
| 31 | #include "omap34xx.h" | ||
| 32 | #include "iomap.h" | 32 | #include "iomap.h" |
| 33 | #include "cm2xxx_3xxx.h" | 33 | #include "cm2xxx_3xxx.h" |
| 34 | #include "prm2xxx_3xxx.h" | 34 | #include "prm2xxx_3xxx.h" |
diff --git a/arch/arm/mach-omap2/sleep44xx.S b/arch/arm/mach-omap2/sleep44xx.S index 91e71d8f46f0..b7d8ead4b86a 100644 --- a/arch/arm/mach-omap2/sleep44xx.S +++ b/arch/arm/mach-omap2/sleep44xx.S | |||
| @@ -14,10 +14,10 @@ | |||
| 14 | #include <asm/memory.h> | 14 | #include <asm/memory.h> |
| 15 | #include <asm/hardware/cache-l2x0.h> | 15 | #include <asm/hardware/cache-l2x0.h> |
| 16 | 16 | ||
| 17 | #include <plat/omap44xx.h> | ||
| 18 | #include <mach/omap-secure.h> | 17 | #include <mach/omap-secure.h> |
| 19 | 18 | ||
| 20 | #include "common.h" | 19 | #include "common.h" |
| 20 | #include "omap44xx.h" | ||
| 21 | #include "omap4-sar-layout.h" | 21 | #include "omap4-sar-layout.h" |
| 22 | 22 | ||
| 23 | #if defined(CONFIG_SMP) && defined(CONFIG_PM) | 23 | #if defined(CONFIG_SMP) && defined(CONFIG_PM) |
diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h new file mode 100644 index 000000000000..fc9b96daf851 --- /dev/null +++ b/arch/arm/mach-omap2/soc.h | |||
| @@ -0,0 +1,7 @@ | |||
| 1 | #include <plat/cpu.h> | ||
| 2 | #include "omap24xx.h" | ||
| 3 | #include "omap34xx.h" | ||
| 4 | #include "omap44xx.h" | ||
| 5 | #include "ti81xx.h" | ||
| 6 | #include "am33xx.h" | ||
| 7 | #include "omap54xx.h" | ||
diff --git a/arch/arm/mach-omap2/sram242x.S b/arch/arm/mach-omap2/sram242x.S index ee0bfcc1410f..8f7326cd435b 100644 --- a/arch/arm/mach-omap2/sram242x.S +++ b/arch/arm/mach-omap2/sram242x.S | |||
| @@ -32,8 +32,7 @@ | |||
| 32 | 32 | ||
| 33 | #include <asm/assembler.h> | 33 | #include <asm/assembler.h> |
| 34 | 34 | ||
| 35 | #include <mach/hardware.h> | 35 | #include "soc.h" |
| 36 | |||
| 37 | #include "iomap.h" | 36 | #include "iomap.h" |
| 38 | #include "prm2xxx_3xxx.h" | 37 | #include "prm2xxx_3xxx.h" |
| 39 | #include "cm2xxx_3xxx.h" | 38 | #include "cm2xxx_3xxx.h" |
diff --git a/arch/arm/mach-omap2/sram243x.S b/arch/arm/mach-omap2/sram243x.S index d4d39ef04769..b140d6578529 100644 --- a/arch/arm/mach-omap2/sram243x.S +++ b/arch/arm/mach-omap2/sram243x.S | |||
| @@ -32,8 +32,7 @@ | |||
| 32 | 32 | ||
| 33 | #include <asm/assembler.h> | 33 | #include <asm/assembler.h> |
| 34 | 34 | ||
| 35 | #include <mach/hardware.h> | 35 | #include "soc.h" |
| 36 | |||
| 37 | #include "iomap.h" | 36 | #include "iomap.h" |
| 38 | #include "prm2xxx_3xxx.h" | 37 | #include "prm2xxx_3xxx.h" |
| 39 | #include "cm2xxx_3xxx.h" | 38 | #include "cm2xxx_3xxx.h" |
diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S index df5a21322b0a..2d0ceaa23fb8 100644 --- a/arch/arm/mach-omap2/sram34xx.S +++ b/arch/arm/mach-omap2/sram34xx.S | |||
| @@ -29,8 +29,7 @@ | |||
| 29 | 29 | ||
| 30 | #include <asm/assembler.h> | 30 | #include <asm/assembler.h> |
| 31 | 31 | ||
| 32 | #include <mach/hardware.h> | 32 | #include "soc.h" |
| 33 | |||
| 34 | #include "iomap.h" | 33 | #include "iomap.h" |
| 35 | #include "sdrc.h" | 34 | #include "sdrc.h" |
| 36 | #include "cm2xxx_3xxx.h" | 35 | #include "cm2xxx_3xxx.h" |
diff --git a/arch/arm/plat-omap/include/plat/ti81xx.h b/arch/arm/mach-omap2/ti81xx.h index 8f9843f78422..8f9843f78422 100644 --- a/arch/arm/plat-omap/include/plat/ti81xx.h +++ b/arch/arm/mach-omap2/ti81xx.h | |||
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index 2ff6d41ec6c6..a9c9b3dbc82c 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c | |||
| @@ -36,16 +36,20 @@ | |||
| 36 | #include <linux/clocksource.h> | 36 | #include <linux/clocksource.h> |
| 37 | #include <linux/clockchips.h> | 37 | #include <linux/clockchips.h> |
| 38 | #include <linux/slab.h> | 38 | #include <linux/slab.h> |
| 39 | #include <linux/of.h> | ||
| 39 | 40 | ||
| 40 | #include <asm/mach/time.h> | 41 | #include <asm/mach/time.h> |
| 41 | #include <plat/dmtimer.h> | ||
| 42 | #include <asm/smp_twd.h> | 42 | #include <asm/smp_twd.h> |
| 43 | #include <asm/sched_clock.h> | 43 | #include <asm/sched_clock.h> |
| 44 | #include "common.h" | 44 | |
| 45 | #include <asm/arch_timer.h> | ||
| 45 | #include <plat/omap_hwmod.h> | 46 | #include <plat/omap_hwmod.h> |
| 46 | #include <plat/omap_device.h> | 47 | #include <plat/omap_device.h> |
| 48 | #include <plat/dmtimer.h> | ||
| 47 | #include <plat/omap-pm.h> | 49 | #include <plat/omap-pm.h> |
| 48 | 50 | ||
| 51 | #include "soc.h" | ||
| 52 | #include "common.h" | ||
| 49 | #include "powerdomain.h" | 53 | #include "powerdomain.h" |
| 50 | 54 | ||
| 51 | /* Parent clocks, eventually these will come from the clock framework */ | 55 | /* Parent clocks, eventually these will come from the clock framework */ |
| @@ -69,6 +73,11 @@ | |||
| 69 | #define OMAP3_SECURE_TIMER 1 | 73 | #define OMAP3_SECURE_TIMER 1 |
| 70 | #endif | 74 | #endif |
| 71 | 75 | ||
| 76 | #define REALTIME_COUNTER_BASE 0x48243200 | ||
| 77 | #define INCREMENTER_NUMERATOR_OFFSET 0x10 | ||
| 78 | #define INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x14 | ||
| 79 | #define NUMERATOR_DENUMERATOR_MASK 0xfffff000 | ||
| 80 | |||
| 72 | /* Clockevent code */ | 81 | /* Clockevent code */ |
| 73 | 82 | ||
| 74 | static struct omap_dm_timer clkev; | 83 | static struct omap_dm_timer clkev; |
| @@ -260,6 +269,7 @@ static u32 notrace dmtimer_read_sched_clock(void) | |||
| 260 | return 0; | 269 | return 0; |
| 261 | } | 270 | } |
| 262 | 271 | ||
| 272 | #ifdef CONFIG_OMAP_32K_TIMER | ||
| 263 | /* Setup free-running counter for clocksource */ | 273 | /* Setup free-running counter for clocksource */ |
| 264 | static int __init omap2_sync32k_clocksource_init(void) | 274 | static int __init omap2_sync32k_clocksource_init(void) |
| 265 | { | 275 | { |
| @@ -299,6 +309,12 @@ static int __init omap2_sync32k_clocksource_init(void) | |||
| 299 | 309 | ||
| 300 | return ret; | 310 | return ret; |
| 301 | } | 311 | } |
| 312 | #else | ||
| 313 | static inline int omap2_sync32k_clocksource_init(void) | ||
| 314 | { | ||
| 315 | return -ENODEV; | ||
| 316 | } | ||
| 317 | #endif | ||
| 302 | 318 | ||
| 303 | static void __init omap2_gptimer_clocksource_init(int gptimer_id, | 319 | static void __init omap2_gptimer_clocksource_init(int gptimer_id, |
| 304 | const char *fck_source) | 320 | const char *fck_source) |
| @@ -339,6 +355,84 @@ static void __init omap2_clocksource_init(int gptimer_id, | |||
| 339 | omap2_gptimer_clocksource_init(gptimer_id, fck_source); | 355 | omap2_gptimer_clocksource_init(gptimer_id, fck_source); |
| 340 | } | 356 | } |
| 341 | 357 | ||
| 358 | #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER | ||
| 359 | /* | ||
| 360 | * The realtime counter also called master counter, is a free-running | ||
| 361 | * counter, which is related to real time. It produces the count used | ||
| 362 | * by the CPU local timer peripherals in the MPU cluster. The timer counts | ||
| 363 | * at a rate of 6.144 MHz. Because the device operates on different clocks | ||
| 364 | * in different power modes, the master counter shifts operation between | ||
| 365 | * clocks, adjusting the increment per clock in hardware accordingly to | ||
| 366 | * maintain a constant count rate. | ||
| 367 | */ | ||
| 368 | static void __init realtime_counter_init(void) | ||
| 369 | { | ||
| 370 | void __iomem *base; | ||
| 371 | static struct clk *sys_clk; | ||
| 372 | unsigned long rate; | ||
| 373 | unsigned int reg, num, den; | ||
| 374 | |||
| 375 | base = ioremap(REALTIME_COUNTER_BASE, SZ_32); | ||
| 376 | if (!base) { | ||
| 377 | pr_err("%s: ioremap failed\n", __func__); | ||
| 378 | return; | ||
| 379 | } | ||
| 380 | sys_clk = clk_get(NULL, "sys_clkin_ck"); | ||
| 381 | if (!sys_clk) { | ||
| 382 | pr_err("%s: failed to get system clock handle\n", __func__); | ||
| 383 | iounmap(base); | ||
| 384 | return; | ||
| 385 | } | ||
| 386 | |||
| 387 | rate = clk_get_rate(sys_clk); | ||
| 388 | /* Numerator/denumerator values refer TRM Realtime Counter section */ | ||
| 389 | switch (rate) { | ||
| 390 | case 1200000: | ||
| 391 | num = 64; | ||
| 392 | den = 125; | ||
| 393 | break; | ||
| 394 | case 1300000: | ||
| 395 | num = 768; | ||
| 396 | den = 1625; | ||
| 397 | break; | ||
| 398 | case 19200000: | ||
| 399 | num = 8; | ||
| 400 | den = 25; | ||
| 401 | break; | ||
| 402 | case 2600000: | ||
| 403 | num = 384; | ||
| 404 | den = 1625; | ||
| 405 | break; | ||
| 406 | case 2700000: | ||
| 407 | num = 256; | ||
| 408 | den = 1125; | ||
| 409 | break; | ||
| 410 | case 38400000: | ||
| 411 | default: | ||
| 412 | /* Program it for 38.4 MHz */ | ||
| 413 | num = 4; | ||
| 414 | den = 25; | ||
| 415 | break; | ||
| 416 | } | ||
| 417 | |||
| 418 | /* Program numerator and denumerator registers */ | ||
| 419 | reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) & | ||
| 420 | NUMERATOR_DENUMERATOR_MASK; | ||
| 421 | reg |= num; | ||
| 422 | __raw_writel(reg, base + INCREMENTER_NUMERATOR_OFFSET); | ||
| 423 | |||
| 424 | reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) & | ||
| 425 | NUMERATOR_DENUMERATOR_MASK; | ||
| 426 | reg |= den; | ||
| 427 | __raw_writel(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET); | ||
| 428 | |||
| 429 | iounmap(base); | ||
| 430 | } | ||
| 431 | #else | ||
| 432 | static inline void __init realtime_counter_init(void) | ||
| 433 | {} | ||
| 434 | #endif | ||
| 435 | |||
| 342 | #define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src, \ | 436 | #define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src, \ |
| 343 | clksrc_nr, clksrc_src) \ | 437 | clksrc_nr, clksrc_src) \ |
| 344 | static void __init omap##name##_timer_init(void) \ | 438 | static void __init omap##name##_timer_init(void) \ |
| @@ -373,8 +467,7 @@ OMAP_SYS_TIMER(3_am33xx) | |||
| 373 | #ifdef CONFIG_ARCH_OMAP4 | 467 | #ifdef CONFIG_ARCH_OMAP4 |
| 374 | #ifdef CONFIG_LOCAL_TIMERS | 468 | #ifdef CONFIG_LOCAL_TIMERS |
| 375 | static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, | 469 | static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, |
| 376 | OMAP44XX_LOCAL_TWD_BASE, | 470 | OMAP44XX_LOCAL_TWD_BASE, 29 + OMAP_INTC_START); |
| 377 | OMAP44XX_IRQ_LOCALTIMER); | ||
| 378 | #endif | 471 | #endif |
| 379 | 472 | ||
| 380 | static void __init omap4_timer_init(void) | 473 | static void __init omap4_timer_init(void) |
| @@ -386,6 +479,11 @@ static void __init omap4_timer_init(void) | |||
| 386 | if (omap_rev() != OMAP4430_REV_ES1_0) { | 479 | if (omap_rev() != OMAP4430_REV_ES1_0) { |
| 387 | int err; | 480 | int err; |
| 388 | 481 | ||
| 482 | if (of_have_populated_dt()) { | ||
| 483 | twd_local_timer_of_register(); | ||
| 484 | return; | ||
| 485 | } | ||
| 486 | |||
| 389 | err = twd_local_timer_register(&twd_local_timer); | 487 | err = twd_local_timer_register(&twd_local_timer); |
| 390 | if (err) | 488 | if (err) |
| 391 | pr_err("twd_local_timer_register failed %d\n", err); | 489 | pr_err("twd_local_timer_register failed %d\n", err); |
| @@ -396,7 +494,18 @@ OMAP_SYS_TIMER(4) | |||
| 396 | #endif | 494 | #endif |
| 397 | 495 | ||
| 398 | #ifdef CONFIG_SOC_OMAP5 | 496 | #ifdef CONFIG_SOC_OMAP5 |
| 399 | OMAP_SYS_TIMER_INIT(5, 1, OMAP4_CLKEV_SOURCE, 2, OMAP4_MPU_SOURCE) | 497 | static void __init omap5_timer_init(void) |
| 498 | { | ||
| 499 | int err; | ||
| 500 | |||
| 501 | omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE); | ||
| 502 | omap2_clocksource_init(2, OMAP4_MPU_SOURCE); | ||
| 503 | realtime_counter_init(); | ||
| 504 | |||
| 505 | err = arch_timer_of_register(); | ||
| 506 | if (err) | ||
| 507 | pr_err("%s: arch_timer_register failed %d\n", __func__, err); | ||
| 508 | } | ||
| 400 | OMAP_SYS_TIMER(5) | 509 | OMAP_SYS_TIMER(5) |
| 401 | #endif | 510 | #endif |
| 402 | 511 | ||
diff --git a/arch/arm/mach-omap2/twl-common.c b/arch/arm/mach-omap2/twl-common.c index db5ff6642375..99be94e94547 100644 --- a/arch/arm/mach-omap2/twl-common.c +++ b/arch/arm/mach-omap2/twl-common.c | |||
| @@ -29,6 +29,7 @@ | |||
| 29 | #include <plat/i2c.h> | 29 | #include <plat/i2c.h> |
| 30 | #include <plat/usb.h> | 30 | #include <plat/usb.h> |
| 31 | 31 | ||
| 32 | #include "soc.h" | ||
| 32 | #include "twl-common.h" | 33 | #include "twl-common.h" |
| 33 | #include "pm.h" | 34 | #include "pm.h" |
| 34 | #include "voltage.h" | 35 | #include "voltage.h" |
| @@ -84,7 +85,7 @@ void __init omap4_pmic_init(const char *pmic_type, | |||
| 84 | omap_mux_init_signal("sys_nirq1", OMAP_PIN_INPUT_PULLUP | OMAP_PIN_OFF_WAKEUPENABLE); | 85 | omap_mux_init_signal("sys_nirq1", OMAP_PIN_INPUT_PULLUP | OMAP_PIN_OFF_WAKEUPENABLE); |
| 85 | strncpy(omap4_i2c1_board_info[0].type, pmic_type, | 86 | strncpy(omap4_i2c1_board_info[0].type, pmic_type, |
| 86 | sizeof(omap4_i2c1_board_info[0].type)); | 87 | sizeof(omap4_i2c1_board_info[0].type)); |
| 87 | omap4_i2c1_board_info[0].irq = OMAP44XX_IRQ_SYS_1N; | 88 | omap4_i2c1_board_info[0].irq = 7 + OMAP44XX_IRQ_GIC_START; |
| 88 | omap4_i2c1_board_info[0].platform_data = pmic_data; | 89 | omap4_i2c1_board_info[0].platform_data = pmic_data; |
| 89 | 90 | ||
| 90 | /* TWL6040 audio IC part */ | 91 | /* TWL6040 audio IC part */ |
diff --git a/arch/arm/mach-omap2/twl-common.h b/arch/arm/mach-omap2/twl-common.h index 8fe71cfd002c..d109c09ef34b 100644 --- a/arch/arm/mach-omap2/twl-common.h +++ b/arch/arm/mach-omap2/twl-common.h | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | #ifndef __OMAP_PMIC_COMMON__ | 1 | #ifndef __OMAP_PMIC_COMMON__ |
| 2 | #define __OMAP_PMIC_COMMON__ | 2 | #define __OMAP_PMIC_COMMON__ |
| 3 | 3 | ||
| 4 | #include <plat/irqs.h> | 4 | #include "common.h" |
| 5 | 5 | ||
| 6 | #define TWL_COMMON_PDATA_USB (1 << 0) | 6 | #define TWL_COMMON_PDATA_USB (1 << 0) |
| 7 | #define TWL_COMMON_PDATA_BCI (1 << 1) | 7 | #define TWL_COMMON_PDATA_BCI (1 << 1) |
| @@ -40,13 +40,13 @@ void omap_pmic_late_init(void); | |||
| 40 | static inline void omap2_pmic_init(const char *pmic_type, | 40 | static inline void omap2_pmic_init(const char *pmic_type, |
| 41 | struct twl4030_platform_data *pmic_data) | 41 | struct twl4030_platform_data *pmic_data) |
| 42 | { | 42 | { |
| 43 | omap_pmic_init(2, 2600, pmic_type, INT_24XX_SYS_NIRQ, pmic_data); | 43 | omap_pmic_init(2, 2600, pmic_type, 7 + OMAP_INTC_START, pmic_data); |
| 44 | } | 44 | } |
| 45 | 45 | ||
| 46 | static inline void omap3_pmic_init(const char *pmic_type, | 46 | static inline void omap3_pmic_init(const char *pmic_type, |
| 47 | struct twl4030_platform_data *pmic_data) | 47 | struct twl4030_platform_data *pmic_data) |
| 48 | { | 48 | { |
| 49 | omap_pmic_init(1, 2600, pmic_type, INT_34XX_SYS_NIRQ, pmic_data); | 49 | omap_pmic_init(1, 2600, pmic_type, 7 + OMAP_INTC_START, pmic_data); |
| 50 | } | 50 | } |
| 51 | 51 | ||
| 52 | void omap4_pmic_init(const char *pmic_type, | 52 | void omap4_pmic_init(const char *pmic_type, |
diff --git a/arch/arm/mach-omap2/usb-host.c b/arch/arm/mach-omap2/usb-host.c index dde8a11f47d5..ac95daaa4702 100644 --- a/arch/arm/mach-omap2/usb-host.c +++ b/arch/arm/mach-omap2/usb-host.c | |||
| @@ -25,8 +25,6 @@ | |||
| 25 | 25 | ||
| 26 | #include <asm/io.h> | 26 | #include <asm/io.h> |
| 27 | 27 | ||
| 28 | #include <mach/hardware.h> | ||
| 29 | #include <mach/irqs.h> | ||
| 30 | #include <plat/usb.h> | 28 | #include <plat/usb.h> |
| 31 | #include <plat/omap_device.h> | 29 | #include <plat/omap_device.h> |
| 32 | 30 | ||
diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c index c4a576856661..89150b2435e5 100644 --- a/arch/arm/mach-omap2/usb-musb.c +++ b/arch/arm/mach-omap2/usb-musb.c | |||
| @@ -23,14 +23,13 @@ | |||
| 23 | #include <linux/clk.h> | 23 | #include <linux/clk.h> |
| 24 | #include <linux/dma-mapping.h> | 24 | #include <linux/dma-mapping.h> |
| 25 | #include <linux/io.h> | 25 | #include <linux/io.h> |
| 26 | |||
| 27 | #include <linux/usb/musb.h> | 26 | #include <linux/usb/musb.h> |
| 28 | 27 | ||
| 29 | #include <mach/hardware.h> | ||
| 30 | #include <mach/irqs.h> | ||
| 31 | #include <mach/am35xx.h> | ||
| 32 | #include <plat/usb.h> | 28 | #include <plat/usb.h> |
| 33 | #include <plat/omap_device.h> | 29 | #include <plat/omap_device.h> |
| 30 | |||
| 31 | #include <mach/am35xx.h> | ||
| 32 | |||
| 34 | #include "mux.h" | 33 | #include "mux.h" |
| 35 | 34 | ||
| 36 | static struct musb_hdrc_config musb_config = { | 35 | static struct musb_hdrc_config musb_config = { |
diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c index 84da34f9a7cf..b451f3c13292 100644 --- a/arch/arm/mach-omap2/vc.c +++ b/arch/arm/mach-omap2/vc.c | |||
| @@ -12,8 +12,7 @@ | |||
| 12 | #include <linux/init.h> | 12 | #include <linux/init.h> |
| 13 | #include <linux/bug.h> | 13 | #include <linux/bug.h> |
| 14 | 14 | ||
| 15 | #include <plat/cpu.h> | 15 | #include "soc.h" |
| 16 | |||
| 17 | #include "voltage.h" | 16 | #include "voltage.h" |
| 18 | #include "vc.h" | 17 | #include "vc.h" |
| 19 | #include "prm-regbits-34xx.h" | 18 | #include "prm-regbits-34xx.h" |
diff --git a/arch/arm/mach-omap2/voltagedomains3xxx_data.c b/arch/arm/mach-omap2/voltagedomains3xxx_data.c index d0103c80d040..63afbfed3cbc 100644 --- a/arch/arm/mach-omap2/voltagedomains3xxx_data.c +++ b/arch/arm/mach-omap2/voltagedomains3xxx_data.c | |||
| @@ -18,9 +18,8 @@ | |||
| 18 | #include <linux/err.h> | 18 | #include <linux/err.h> |
| 19 | #include <linux/init.h> | 19 | #include <linux/init.h> |
| 20 | 20 | ||
| 21 | #include "soc.h" | ||
| 21 | #include "common.h" | 22 | #include "common.h" |
| 22 | #include <plat/cpu.h> | ||
| 23 | |||
| 24 | #include "prm-regbits-34xx.h" | 23 | #include "prm-regbits-34xx.h" |
| 25 | #include "omap_opp_data.h" | 24 | #include "omap_opp_data.h" |
| 26 | #include "voltage.h" | 25 | #include "voltage.h" |
diff --git a/arch/arm/mach-prima2/Makefile b/arch/arm/mach-prima2/Makefile index 13dd1604d951..841847d56032 100644 --- a/arch/arm/mach-prima2/Makefile +++ b/arch/arm/mach-prima2/Makefile | |||
| @@ -1,6 +1,5 @@ | |||
| 1 | obj-y := timer.o | 1 | obj-y := timer.o |
| 2 | obj-y += irq.o | 2 | obj-y += irq.o |
| 3 | obj-y += clock.o | ||
| 4 | obj-y += rstc.o | 3 | obj-y += rstc.o |
| 5 | obj-y += prima2.o | 4 | obj-y += prima2.o |
| 6 | obj-y += rtciobrg.o | 5 | obj-y += rtciobrg.o |
diff --git a/arch/arm/mach-prima2/Makefile.boot b/arch/arm/mach-prima2/Makefile.boot index c77a4883a4ee..98167da874c9 100644 --- a/arch/arm/mach-prima2/Makefile.boot +++ b/arch/arm/mach-prima2/Makefile.boot | |||
| @@ -1,3 +1,5 @@ | |||
| 1 | zreladdr-y += 0x00008000 | 1 | zreladdr-y += 0x00008000 |
| 2 | params_phys-y := 0x00000100 | 2 | params_phys-y := 0x00000100 |
| 3 | initrd_phys-y := 0x00800000 | 3 | initrd_phys-y := 0x00800000 |
| 4 | |||
| 5 | dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb | ||
diff --git a/arch/arm/mach-prima2/clock.c b/arch/arm/mach-prima2/clock.c deleted file mode 100644 index aebad7e565cf..000000000000 --- a/arch/arm/mach-prima2/clock.c +++ /dev/null | |||
| @@ -1,510 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Clock tree for CSR SiRFprimaII | ||
| 3 | * | ||
| 4 | * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. | ||
| 5 | * | ||
| 6 | * Licensed under GPLv2 or later. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #include <linux/module.h> | ||
| 10 | #include <linux/bitops.h> | ||
| 11 | #include <linux/err.h> | ||
| 12 | #include <linux/errno.h> | ||
| 13 | #include <linux/io.h> | ||
| 14 | #include <linux/clkdev.h> | ||
| 15 | #include <linux/clk.h> | ||
| 16 | #include <linux/spinlock.h> | ||
| 17 | #include <linux/of.h> | ||
| 18 | #include <linux/of_address.h> | ||
| 19 | #include <asm/mach/map.h> | ||
| 20 | #include <mach/map.h> | ||
| 21 | |||
| 22 | #define SIRFSOC_CLKC_CLK_EN0 0x0000 | ||
| 23 | #define SIRFSOC_CLKC_CLK_EN1 0x0004 | ||
| 24 | #define SIRFSOC_CLKC_REF_CFG 0x0014 | ||
| 25 | #define SIRFSOC_CLKC_CPU_CFG 0x0018 | ||
| 26 | #define SIRFSOC_CLKC_MEM_CFG 0x001c | ||
| 27 | #define SIRFSOC_CLKC_SYS_CFG 0x0020 | ||
| 28 | #define SIRFSOC_CLKC_IO_CFG 0x0024 | ||
| 29 | #define SIRFSOC_CLKC_DSP_CFG 0x0028 | ||
| 30 | #define SIRFSOC_CLKC_GFX_CFG 0x002c | ||
| 31 | #define SIRFSOC_CLKC_MM_CFG 0x0030 | ||
| 32 | #define SIRFSOC_LKC_LCD_CFG 0x0034 | ||
| 33 | #define SIRFSOC_CLKC_MMC_CFG 0x0038 | ||
| 34 | #define SIRFSOC_CLKC_PLL1_CFG0 0x0040 | ||
| 35 | #define SIRFSOC_CLKC_PLL2_CFG0 0x0044 | ||
| 36 | #define SIRFSOC_CLKC_PLL3_CFG0 0x0048 | ||
| 37 | #define SIRFSOC_CLKC_PLL1_CFG1 0x004c | ||
| 38 | #define SIRFSOC_CLKC_PLL2_CFG1 0x0050 | ||
| 39 | #define SIRFSOC_CLKC_PLL3_CFG1 0x0054 | ||
| 40 | #define SIRFSOC_CLKC_PLL1_CFG2 0x0058 | ||
| 41 | #define SIRFSOC_CLKC_PLL2_CFG2 0x005c | ||
| 42 | #define SIRFSOC_CLKC_PLL3_CFG2 0x0060 | ||
| 43 | |||
| 44 | #define SIRFSOC_CLOCK_VA_BASE SIRFSOC_VA(0x005000) | ||
| 45 | |||
| 46 | #define KHZ 1000 | ||
| 47 | #define MHZ (KHZ * KHZ) | ||
| 48 | |||
| 49 | struct clk_ops { | ||
| 50 | unsigned long (*get_rate)(struct clk *clk); | ||
| 51 | long (*round_rate)(struct clk *clk, unsigned long rate); | ||
| 52 | int (*set_rate)(struct clk *clk, unsigned long rate); | ||
| 53 | int (*enable)(struct clk *clk); | ||
| 54 | int (*disable)(struct clk *clk); | ||
| 55 | struct clk *(*get_parent)(struct clk *clk); | ||
| 56 | int (*set_parent)(struct clk *clk, struct clk *parent); | ||
| 57 | }; | ||
| 58 | |||
| 59 | struct clk { | ||
| 60 | struct clk *parent; /* parent clk */ | ||
| 61 | unsigned long rate; /* clock rate in Hz */ | ||
| 62 | signed char usage; /* clock enable count */ | ||
| 63 | signed char enable_bit; /* enable bit: 0 ~ 63 */ | ||
| 64 | unsigned short regofs; /* register offset */ | ||
| 65 | struct clk_ops *ops; /* clock operation */ | ||
| 66 | }; | ||
| 67 | |||
| 68 | static DEFINE_SPINLOCK(clocks_lock); | ||
| 69 | |||
| 70 | static inline unsigned long clkc_readl(unsigned reg) | ||
| 71 | { | ||
| 72 | return readl(SIRFSOC_CLOCK_VA_BASE + reg); | ||
| 73 | } | ||
| 74 | |||
| 75 | static inline void clkc_writel(u32 val, unsigned reg) | ||
| 76 | { | ||
| 77 | writel(val, SIRFSOC_CLOCK_VA_BASE + reg); | ||
| 78 | } | ||
| 79 | |||
| 80 | /* | ||
| 81 | * osc_rtc - real time oscillator - 32.768KHz | ||
| 82 | * osc_sys - high speed oscillator - 26MHz | ||
| 83 | */ | ||
| 84 | |||
| 85 | static struct clk clk_rtc = { | ||
| 86 | .rate = 32768, | ||
| 87 | }; | ||
| 88 | |||
| 89 | static struct clk clk_osc = { | ||
| 90 | .rate = 26 * MHZ, | ||
| 91 | }; | ||
| 92 | |||
| 93 | /* | ||
| 94 | * std pll | ||
| 95 | */ | ||
| 96 | static unsigned long std_pll_get_rate(struct clk *clk) | ||
| 97 | { | ||
| 98 | unsigned long fin = clk_get_rate(clk->parent); | ||
| 99 | u32 regcfg2 = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 - | ||
| 100 | SIRFSOC_CLKC_PLL1_CFG0; | ||
| 101 | |||
| 102 | if (clkc_readl(regcfg2) & BIT(2)) { | ||
| 103 | /* pll bypass mode */ | ||
| 104 | clk->rate = fin; | ||
| 105 | } else { | ||
| 106 | /* fout = fin * nf / nr / od */ | ||
| 107 | u32 cfg0 = clkc_readl(clk->regofs); | ||
| 108 | u32 nf = (cfg0 & (BIT(13) - 1)) + 1; | ||
| 109 | u32 nr = ((cfg0 >> 13) & (BIT(6) - 1)) + 1; | ||
| 110 | u32 od = ((cfg0 >> 19) & (BIT(4) - 1)) + 1; | ||
| 111 | WARN_ON(fin % MHZ); | ||
| 112 | clk->rate = fin / MHZ * nf / nr / od * MHZ; | ||
| 113 | } | ||
| 114 | |||
| 115 | return clk->rate; | ||
| 116 | } | ||
| 117 | |||
| 118 | static int std_pll_set_rate(struct clk *clk, unsigned long rate) | ||
| 119 | { | ||
| 120 | unsigned long fin, nf, nr, od, reg; | ||
| 121 | |||
| 122 | /* | ||
| 123 | * fout = fin * nf / (nr * od); | ||
| 124 | * set od = 1, nr = fin/MHz, so fout = nf * MHz | ||
| 125 | */ | ||
| 126 | |||
| 127 | nf = rate / MHZ; | ||
| 128 | if (unlikely((rate % MHZ) || nf > BIT(13) || nf < 1)) | ||
| 129 | return -EINVAL; | ||
| 130 | |||
| 131 | fin = clk_get_rate(clk->parent); | ||
| 132 | BUG_ON(fin < MHZ); | ||
| 133 | |||
| 134 | nr = fin / MHZ; | ||
| 135 | BUG_ON((fin % MHZ) || nr > BIT(6)); | ||
| 136 | |||
| 137 | od = 1; | ||
| 138 | |||
| 139 | reg = (nf - 1) | ((nr - 1) << 13) | ((od - 1) << 19); | ||
| 140 | clkc_writel(reg, clk->regofs); | ||
| 141 | |||
| 142 | reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG1 - SIRFSOC_CLKC_PLL1_CFG0; | ||
| 143 | clkc_writel((nf >> 1) - 1, reg); | ||
| 144 | |||
| 145 | reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 - SIRFSOC_CLKC_PLL1_CFG0; | ||
| 146 | while (!(clkc_readl(reg) & BIT(6))) | ||
| 147 | cpu_relax(); | ||
| 148 | |||
| 149 | clk->rate = 0; /* set to zero will force recalculation */ | ||
| 150 | return 0; | ||
| 151 | } | ||
| 152 | |||
| 153 | static struct clk_ops std_pll_ops = { | ||
| 154 | .get_rate = std_pll_get_rate, | ||
| 155 | .set_rate = std_pll_set_rate, | ||
| 156 | }; | ||
| 157 | |||
| 158 | static struct clk clk_pll1 = { | ||
| 159 | .parent = &clk_osc, | ||
| 160 | .regofs = SIRFSOC_CLKC_PLL1_CFG0, | ||
| 161 | .ops = &std_pll_ops, | ||
| 162 | }; | ||
| 163 | |||
| 164 | static struct clk clk_pll2 = { | ||
| 165 | .parent = &clk_osc, | ||
| 166 | .regofs = SIRFSOC_CLKC_PLL2_CFG0, | ||
| 167 | .ops = &std_pll_ops, | ||
| 168 | }; | ||
| 169 | |||
| 170 | static struct clk clk_pll3 = { | ||
| 171 | .parent = &clk_osc, | ||
| 172 | .regofs = SIRFSOC_CLKC_PLL3_CFG0, | ||
| 173 | .ops = &std_pll_ops, | ||
| 174 | }; | ||
| 175 | |||
| 176 | /* | ||
| 177 | * clock domains - cpu, mem, sys/io | ||
| 178 | */ | ||
| 179 | |||
| 180 | static struct clk clk_mem; | ||
| 181 | |||
| 182 | static struct clk *dmn_get_parent(struct clk *clk) | ||
| 183 | { | ||
| 184 | struct clk *clks[] = { | ||
| 185 | &clk_osc, &clk_rtc, &clk_pll1, &clk_pll2, &clk_pll3 | ||
| 186 | }; | ||
| 187 | u32 cfg = clkc_readl(clk->regofs); | ||
| 188 | WARN_ON((cfg & (BIT(3) - 1)) > 4); | ||
| 189 | return clks[cfg & (BIT(3) - 1)]; | ||
| 190 | } | ||
| 191 | |||
| 192 | static int dmn_set_parent(struct clk *clk, struct clk *parent) | ||
| 193 | { | ||
| 194 | const struct clk *clks[] = { | ||
| 195 | &clk_osc, &clk_rtc, &clk_pll1, &clk_pll2, &clk_pll3 | ||
| 196 | }; | ||
| 197 | u32 cfg = clkc_readl(clk->regofs); | ||
| 198 | int i; | ||
| 199 | for (i = 0; i < ARRAY_SIZE(clks); i++) { | ||
| 200 | if (clks[i] == parent) { | ||
| 201 | cfg &= ~(BIT(3) - 1); | ||
| 202 | clkc_writel(cfg | i, clk->regofs); | ||
| 203 | /* BIT(3) - switching status: 1 - busy, 0 - done */ | ||
| 204 | while (clkc_readl(clk->regofs) & BIT(3)) | ||
| 205 | cpu_relax(); | ||
| 206 | return 0; | ||
| 207 | } | ||
| 208 | } | ||
| 209 | return -EINVAL; | ||
| 210 | } | ||
| 211 | |||
| 212 | static unsigned long dmn_get_rate(struct clk *clk) | ||
| 213 | { | ||
| 214 | unsigned long fin = clk_get_rate(clk->parent); | ||
| 215 | u32 cfg = clkc_readl(clk->regofs); | ||
| 216 | if (cfg & BIT(24)) { | ||
| 217 | /* fcd bypass mode */ | ||
| 218 | clk->rate = fin; | ||
| 219 | } else { | ||
| 220 | /* | ||
| 221 | * wait count: bit[19:16], hold count: bit[23:20] | ||
| 222 | */ | ||
| 223 | u32 wait = (cfg >> 16) & (BIT(4) - 1); | ||
| 224 | u32 hold = (cfg >> 20) & (BIT(4) - 1); | ||
| 225 | |||
| 226 | clk->rate = fin / (wait + hold + 2); | ||
| 227 | } | ||
| 228 | |||
| 229 | return clk->rate; | ||
| 230 | } | ||
| 231 | |||
| 232 | static int dmn_set_rate(struct clk *clk, unsigned long rate) | ||
| 233 | { | ||
| 234 | unsigned long fin; | ||
| 235 | unsigned ratio, wait, hold, reg; | ||
| 236 | unsigned bits = (clk == &clk_mem) ? 3 : 4; | ||
| 237 | |||
| 238 | fin = clk_get_rate(clk->parent); | ||
| 239 | ratio = fin / rate; | ||
| 240 | |||
| 241 | if (unlikely(ratio < 2 || ratio > BIT(bits + 1))) | ||
| 242 | return -EINVAL; | ||
| 243 | |||
| 244 | WARN_ON(fin % rate); | ||
| 245 | |||
| 246 | wait = (ratio >> 1) - 1; | ||
| 247 | hold = ratio - wait - 2; | ||
| 248 | |||
| 249 | reg = clkc_readl(clk->regofs); | ||
| 250 | reg &= ~(((BIT(bits) - 1) << 16) | ((BIT(bits) - 1) << 20)); | ||
| 251 | reg |= (wait << 16) | (hold << 20) | BIT(25); | ||
| 252 | clkc_writel(reg, clk->regofs); | ||
| 253 | |||
| 254 | /* waiting FCD been effective */ | ||
| 255 | while (clkc_readl(clk->regofs) & BIT(25)) | ||
| 256 | cpu_relax(); | ||
| 257 | |||
| 258 | clk->rate = 0; /* set to zero will force recalculation */ | ||
| 259 | |||
| 260 | return 0; | ||
| 261 | } | ||
| 262 | |||
| 263 | /* | ||
| 264 | * cpu clock has no FCD register in Prima2, can only change pll | ||
| 265 | */ | ||
| 266 | static int cpu_set_rate(struct clk *clk, unsigned long rate) | ||
| 267 | { | ||
| 268 | int ret1, ret2; | ||
| 269 | struct clk *cur_parent, *tmp_parent; | ||
| 270 | |||
| 271 | cur_parent = dmn_get_parent(clk); | ||
| 272 | BUG_ON(cur_parent == NULL || cur_parent->usage > 1); | ||
| 273 | |||
| 274 | /* switch to tmp pll before setting parent clock's rate */ | ||
| 275 | tmp_parent = cur_parent == &clk_pll1 ? &clk_pll2 : &clk_pll1; | ||
| 276 | ret1 = dmn_set_parent(clk, tmp_parent); | ||
| 277 | BUG_ON(ret1); | ||
| 278 | |||
| 279 | ret2 = clk_set_rate(cur_parent, rate); | ||
| 280 | |||
| 281 | ret1 = dmn_set_parent(clk, cur_parent); | ||
| 282 | |||
| 283 | clk->rate = 0; /* set to zero will force recalculation */ | ||
| 284 | |||
| 285 | return ret2 ? ret2 : ret1; | ||
| 286 | } | ||
| 287 | |||
| 288 | static struct clk_ops cpu_ops = { | ||
| 289 | .get_parent = dmn_get_parent, | ||
| 290 | .set_parent = dmn_set_parent, | ||
| 291 | .set_rate = cpu_set_rate, | ||
| 292 | }; | ||
| 293 | |||
| 294 | static struct clk clk_cpu = { | ||
| 295 | .parent = &clk_pll1, | ||
| 296 | .regofs = SIRFSOC_CLKC_CPU_CFG, | ||
| 297 | .ops = &cpu_ops, | ||
| 298 | }; | ||
| 299 | |||
| 300 | |||
| 301 | static struct clk_ops msi_ops = { | ||
| 302 | .set_rate = dmn_set_rate, | ||
| 303 | .get_rate = dmn_get_rate, | ||
| 304 | .set_parent = dmn_set_parent, | ||
| 305 | .get_parent = dmn_get_parent, | ||
| 306 | }; | ||
| 307 | |||
| 308 | static struct clk clk_mem = { | ||
| 309 | .parent = &clk_pll2, | ||
| 310 | .regofs = SIRFSOC_CLKC_MEM_CFG, | ||
| 311 | .ops = &msi_ops, | ||
| 312 | }; | ||
| 313 | |||
| 314 | static struct clk clk_sys = { | ||
| 315 | .parent = &clk_pll3, | ||
| 316 | .regofs = SIRFSOC_CLKC_SYS_CFG, | ||
| 317 | .ops = &msi_ops, | ||
| 318 | }; | ||
| 319 | |||
| 320 | static struct clk clk_io = { | ||
| 321 | .parent = &clk_pll3, | ||
| 322 | .regofs = SIRFSOC_CLKC_IO_CFG, | ||
| 323 | .ops = &msi_ops, | ||
| 324 | }; | ||
| 325 | |||
| 326 | /* | ||
| 327 | * on-chip clock sets | ||
| 328 | */ | ||
| 329 | static struct clk_lookup onchip_clks[] = { | ||
| 330 | { | ||
| 331 | .dev_id = "rtc", | ||
| 332 | .clk = &clk_rtc, | ||
| 333 | }, { | ||
| 334 | .dev_id = "osc", | ||
| 335 | .clk = &clk_osc, | ||
| 336 | }, { | ||
| 337 | .dev_id = "pll1", | ||
| 338 | .clk = &clk_pll1, | ||
| 339 | }, { | ||
| 340 | .dev_id = "pll2", | ||
| 341 | .clk = &clk_pll2, | ||
| 342 | }, { | ||
| 343 | .dev_id = "pll3", | ||
| 344 | .clk = &clk_pll3, | ||
| 345 | }, { | ||
| 346 | .dev_id = "cpu", | ||
| 347 | .clk = &clk_cpu, | ||
| 348 | }, { | ||
| 349 | .dev_id = "mem", | ||
| 350 | .clk = &clk_mem, | ||
| 351 | }, { | ||
| 352 | .dev_id = "sys", | ||
| 353 | .clk = &clk_sys, | ||
| 354 | }, { | ||
| 355 | .dev_id = "io", | ||
| 356 | .clk = &clk_io, | ||
| 357 | }, | ||
| 358 | }; | ||
| 359 | |||
| 360 | int clk_enable(struct clk *clk) | ||
| 361 | { | ||
| 362 | unsigned long flags; | ||
| 363 | |||
| 364 | if (unlikely(IS_ERR_OR_NULL(clk))) | ||
| 365 | return -EINVAL; | ||
| 366 | |||
| 367 | if (clk->parent) | ||
| 368 | clk_enable(clk->parent); | ||
| 369 | |||
| 370 | spin_lock_irqsave(&clocks_lock, flags); | ||
| 371 | if (!clk->usage++ && clk->ops && clk->ops->enable) | ||
| 372 | clk->ops->enable(clk); | ||
| 373 | spin_unlock_irqrestore(&clocks_lock, flags); | ||
| 374 | return 0; | ||
| 375 | } | ||
| 376 | EXPORT_SYMBOL(clk_enable); | ||
| 377 | |||
| 378 | void clk_disable(struct clk *clk) | ||
| 379 | { | ||
| 380 | unsigned long flags; | ||
| 381 | |||
| 382 | if (unlikely(IS_ERR_OR_NULL(clk))) | ||
| 383 | return; | ||
| 384 | |||
| 385 | WARN_ON(!clk->usage); | ||
| 386 | |||
| 387 | spin_lock_irqsave(&clocks_lock, flags); | ||
| 388 | if (--clk->usage == 0 && clk->ops && clk->ops->disable) | ||
| 389 | clk->ops->disable(clk); | ||
| 390 | spin_unlock_irqrestore(&clocks_lock, flags); | ||
| 391 | |||
| 392 | if (clk->parent) | ||
| 393 | clk_disable(clk->parent); | ||
| 394 | } | ||
| 395 | EXPORT_SYMBOL(clk_disable); | ||
| 396 | |||
| 397 | unsigned long clk_get_rate(struct clk *clk) | ||
| 398 | { | ||
| 399 | if (unlikely(IS_ERR_OR_NULL(clk))) | ||
| 400 | return 0; | ||
| 401 | |||
| 402 | if (clk->rate) | ||
| 403 | return clk->rate; | ||
| 404 | |||
| 405 | if (clk->ops && clk->ops->get_rate) | ||
| 406 | return clk->ops->get_rate(clk); | ||
| 407 | |||
| 408 | return clk_get_rate(clk->parent); | ||
| 409 | } | ||
| 410 | EXPORT_SYMBOL(clk_get_rate); | ||
| 411 | |||
| 412 | long clk_round_rate(struct clk *clk, unsigned long rate) | ||
| 413 | { | ||
| 414 | if (unlikely(IS_ERR_OR_NULL(clk))) | ||
| 415 | return 0; | ||
| 416 | |||
| 417 | if (clk->ops && clk->ops->round_rate) | ||
| 418 | return clk->ops->round_rate(clk, rate); | ||
| 419 | |||
| 420 | return 0; | ||
| 421 | } | ||
| 422 | EXPORT_SYMBOL(clk_round_rate); | ||
| 423 | |||
| 424 | int clk_set_rate(struct clk *clk, unsigned long rate) | ||
| 425 | { | ||
| 426 | if (unlikely(IS_ERR_OR_NULL(clk))) | ||
| 427 | return -EINVAL; | ||
| 428 | |||
| 429 | if (!clk->ops || !clk->ops->set_rate) | ||
| 430 | return -EINVAL; | ||
| 431 | |||
| 432 | return clk->ops->set_rate(clk, rate); | ||
| 433 | } | ||
| 434 | EXPORT_SYMBOL(clk_set_rate); | ||
| 435 | |||
| 436 | int clk_set_parent(struct clk *clk, struct clk *parent) | ||
| 437 | { | ||
| 438 | int ret; | ||
| 439 | unsigned long flags; | ||
| 440 | |||
| 441 | if (unlikely(IS_ERR_OR_NULL(clk))) | ||
| 442 | return -EINVAL; | ||
| 443 | |||
| 444 | if (!clk->ops || !clk->ops->set_parent) | ||
| 445 | return -EINVAL; | ||
| 446 | |||
| 447 | spin_lock_irqsave(&clocks_lock, flags); | ||
| 448 | ret = clk->ops->set_parent(clk, parent); | ||
| 449 | if (!ret) { | ||
| 450 | parent->usage += clk->usage; | ||
| 451 | clk->parent->usage -= clk->usage; | ||
| 452 | BUG_ON(clk->parent->usage < 0); | ||
| 453 | clk->parent = parent; | ||
| 454 | } | ||
| 455 | spin_unlock_irqrestore(&clocks_lock, flags); | ||
| 456 | return ret; | ||
| 457 | } | ||
| 458 | EXPORT_SYMBOL(clk_set_parent); | ||
| 459 | |||
| 460 | struct clk *clk_get_parent(struct clk *clk) | ||
| 461 | { | ||
| 462 | unsigned long flags; | ||
| 463 | |||
| 464 | if (unlikely(IS_ERR_OR_NULL(clk))) | ||
| 465 | return NULL; | ||
| 466 | |||
| 467 | if (!clk->ops || !clk->ops->get_parent) | ||
| 468 | return clk->parent; | ||
| 469 | |||
| 470 | spin_lock_irqsave(&clocks_lock, flags); | ||
| 471 | clk->parent = clk->ops->get_parent(clk); | ||
| 472 | spin_unlock_irqrestore(&clocks_lock, flags); | ||
| 473 | return clk->parent; | ||
| 474 | } | ||
| 475 | EXPORT_SYMBOL(clk_get_parent); | ||
| 476 | |||
| 477 | static void __init sirfsoc_clk_init(void) | ||
| 478 | { | ||
| 479 | clkdev_add_table(onchip_clks, ARRAY_SIZE(onchip_clks)); | ||
| 480 | } | ||
| 481 | |||
| 482 | static struct of_device_id clkc_ids[] = { | ||
| 483 | { .compatible = "sirf,prima2-clkc" }, | ||
| 484 | {}, | ||
| 485 | }; | ||
| 486 | |||
| 487 | void __init sirfsoc_of_clk_init(void) | ||
| 488 | { | ||
| 489 | struct device_node *np; | ||
| 490 | struct resource res; | ||
| 491 | struct map_desc sirfsoc_clkc_iodesc = { | ||
| 492 | .virtual = SIRFSOC_CLOCK_VA_BASE, | ||
| 493 | .type = MT_DEVICE, | ||
| 494 | }; | ||
| 495 | |||
| 496 | np = of_find_matching_node(NULL, clkc_ids); | ||
| 497 | if (!np) | ||
| 498 | panic("unable to find compatible clkc node in dtb\n"); | ||
| 499 | |||
| 500 | if (of_address_to_resource(np, 0, &res)) | ||
| 501 | panic("unable to find clkc range in dtb"); | ||
| 502 | of_node_put(np); | ||
| 503 | |||
| 504 | sirfsoc_clkc_iodesc.pfn = __phys_to_pfn(res.start); | ||
| 505 | sirfsoc_clkc_iodesc.length = 1 + res.end - res.start; | ||
| 506 | |||
| 507 | iotable_init(&sirfsoc_clkc_iodesc, 1); | ||
| 508 | |||
| 509 | sirfsoc_clk_init(); | ||
| 510 | } | ||
diff --git a/arch/arm/mach-prima2/prima2.c b/arch/arm/mach-prima2/prima2.c index 8f0429d4b79f..e9a17aebe0d6 100644 --- a/arch/arm/mach-prima2/prima2.c +++ b/arch/arm/mach-prima2/prima2.c | |||
| @@ -38,7 +38,6 @@ static const char *prima2cb_dt_match[] __initdata = { | |||
| 38 | MACHINE_START(PRIMA2_EVB, "prima2cb") | 38 | MACHINE_START(PRIMA2_EVB, "prima2cb") |
| 39 | /* Maintainer: Barry Song <baohua.song@csr.com> */ | 39 | /* Maintainer: Barry Song <baohua.song@csr.com> */ |
| 40 | .atag_offset = 0x100, | 40 | .atag_offset = 0x100, |
| 41 | .init_early = sirfsoc_of_clk_init, | ||
| 42 | .map_io = sirfsoc_map_lluart, | 41 | .map_io = sirfsoc_map_lluart, |
| 43 | .init_irq = sirfsoc_of_irq_init, | 42 | .init_irq = sirfsoc_of_irq_init, |
| 44 | .timer = &sirfsoc_timer, | 43 | .timer = &sirfsoc_timer, |
diff --git a/arch/arm/mach-prima2/timer.c b/arch/arm/mach-prima2/timer.c index f224107de7bc..d95bf252f694 100644 --- a/arch/arm/mach-prima2/timer.c +++ b/arch/arm/mach-prima2/timer.c | |||
| @@ -21,6 +21,8 @@ | |||
| 21 | #include <asm/sched_clock.h> | 21 | #include <asm/sched_clock.h> |
| 22 | #include <asm/mach/time.h> | 22 | #include <asm/mach/time.h> |
| 23 | 23 | ||
| 24 | #include "common.h" | ||
| 25 | |||
| 24 | #define SIRFSOC_TIMER_COUNTER_LO 0x0000 | 26 | #define SIRFSOC_TIMER_COUNTER_LO 0x0000 |
| 25 | #define SIRFSOC_TIMER_COUNTER_HI 0x0004 | 27 | #define SIRFSOC_TIMER_COUNTER_HI 0x0004 |
| 26 | #define SIRFSOC_TIMER_MATCH_0 0x0008 | 28 | #define SIRFSOC_TIMER_MATCH_0 0x0008 |
| @@ -188,9 +190,13 @@ static void __init sirfsoc_clockevent_init(void) | |||
| 188 | static void __init sirfsoc_timer_init(void) | 190 | static void __init sirfsoc_timer_init(void) |
| 189 | { | 191 | { |
| 190 | unsigned long rate; | 192 | unsigned long rate; |
| 193 | struct clk *clk; | ||
| 194 | |||
| 195 | /* initialize clocking early, we want to set the OS timer */ | ||
| 196 | sirfsoc_of_clk_init(); | ||
| 191 | 197 | ||
| 192 | /* timer's input clock is io clock */ | 198 | /* timer's input clock is io clock */ |
| 193 | struct clk *clk = clk_get_sys("io", NULL); | 199 | clk = clk_get_sys("io", NULL); |
| 194 | 200 | ||
| 195 | BUG_ON(IS_ERR(clk)); | 201 | BUG_ON(IS_ERR(clk)); |
| 196 | 202 | ||
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig index fe2d1f80ef50..8e6288de69b9 100644 --- a/arch/arm/mach-pxa/Kconfig +++ b/arch/arm/mach-pxa/Kconfig | |||
| @@ -25,6 +25,18 @@ config PXA_V7_MACH_AUTO | |||
| 25 | if !ARCH_PXA_V7 | 25 | if !ARCH_PXA_V7 |
| 26 | comment "Intel/Marvell Dev Platforms (sorted by hardware release time)" | 26 | comment "Intel/Marvell Dev Platforms (sorted by hardware release time)" |
| 27 | 27 | ||
| 28 | config MACH_PXA3XX_DT | ||
| 29 | bool "Support PXA3xx platforms from device tree" | ||
| 30 | select PXA3xx | ||
| 31 | select CPU_PXA300 | ||
| 32 | select POWER_SUPPLY | ||
| 33 | select HAVE_PWM | ||
| 34 | select USE_OF | ||
| 35 | help | ||
| 36 | Include support for Marvell PXA3xx based platforms using | ||
| 37 | the device tree. Needn't select any other machine while | ||
| 38 | MACH_PXA3XX_DT is enabled. | ||
| 39 | |||
| 28 | config ARCH_LUBBOCK | 40 | config ARCH_LUBBOCK |
| 29 | bool "Intel DBPXA250 Development Platform (aka Lubbock)" | 41 | bool "Intel DBPXA250 Development Platform (aka Lubbock)" |
| 30 | select PXA25x | 42 | select PXA25x |
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile index be0f7df8685c..2bedc9ed076c 100644 --- a/arch/arm/mach-pxa/Makefile +++ b/arch/arm/mach-pxa/Makefile | |||
| @@ -26,6 +26,9 @@ obj-$(CONFIG_CPU_PXA930) += pxa930.o | |||
| 26 | 26 | ||
| 27 | # NOTE: keep the order of boards in accordance to their order in Kconfig | 27 | # NOTE: keep the order of boards in accordance to their order in Kconfig |
| 28 | 28 | ||
| 29 | # Device Tree support | ||
| 30 | obj-$(CONFIG_MACH_PXA3XX_DT) += pxa-dt.o | ||
| 31 | |||
| 29 | # Intel/Marvell Dev Platforms | 32 | # Intel/Marvell Dev Platforms |
| 30 | obj-$(CONFIG_ARCH_LUBBOCK) += lubbock.o | 33 | obj-$(CONFIG_ARCH_LUBBOCK) += lubbock.o |
| 31 | obj-$(CONFIG_MACH_MAINSTONE) += mainstone.o | 34 | obj-$(CONFIG_MACH_MAINSTONE) += mainstone.o |
diff --git a/arch/arm/mach-pxa/clock-pxa3xx.c b/arch/arm/mach-pxa/clock-pxa3xx.c index 2a37a9a8f621..d4e9499832dc 100644 --- a/arch/arm/mach-pxa/clock-pxa3xx.c +++ b/arch/arm/mach-pxa/clock-pxa3xx.c | |||
| @@ -127,8 +127,10 @@ void clk_pxa3xx_cken_enable(struct clk *clk) | |||
| 127 | 127 | ||
| 128 | if (clk->cken < 32) | 128 | if (clk->cken < 32) |
| 129 | CKENA |= mask; | 129 | CKENA |= mask; |
| 130 | else | 130 | else if (clk->cken < 64) |
| 131 | CKENB |= mask; | 131 | CKENB |= mask; |
| 132 | else | ||
| 133 | CKENC |= mask; | ||
| 132 | } | 134 | } |
| 133 | 135 | ||
| 134 | void clk_pxa3xx_cken_disable(struct clk *clk) | 136 | void clk_pxa3xx_cken_disable(struct clk *clk) |
| @@ -137,8 +139,10 @@ void clk_pxa3xx_cken_disable(struct clk *clk) | |||
| 137 | 139 | ||
| 138 | if (clk->cken < 32) | 140 | if (clk->cken < 32) |
| 139 | CKENA &= ~mask; | 141 | CKENA &= ~mask; |
| 140 | else | 142 | else if (clk->cken < 64) |
| 141 | CKENB &= ~mask; | 143 | CKENB &= ~mask; |
| 144 | else | ||
| 145 | CKENC &= ~mask; | ||
| 142 | } | 146 | } |
| 143 | 147 | ||
| 144 | const struct clkops clk_pxa3xx_cken_ops = { | 148 | const struct clkops clk_pxa3xx_cken_ops = { |
diff --git a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h index 207ecb49a61b..f4d48d20754e 100644 --- a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h +++ b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h | |||
| @@ -131,6 +131,7 @@ | |||
| 131 | #define AICSR __REG(0x41340008) /* Application Subsystem Interrupt Control/Status Register */ | 131 | #define AICSR __REG(0x41340008) /* Application Subsystem Interrupt Control/Status Register */ |
| 132 | #define CKENA __REG(0x4134000C) /* A Clock Enable Register */ | 132 | #define CKENA __REG(0x4134000C) /* A Clock Enable Register */ |
| 133 | #define CKENB __REG(0x41340010) /* B Clock Enable Register */ | 133 | #define CKENB __REG(0x41340010) /* B Clock Enable Register */ |
| 134 | #define CKENC __REG(0x41340024) /* C Clock Enable Register */ | ||
| 134 | #define AC97_DIV __REG(0x41340014) /* AC97 clock divisor value register */ | 135 | #define AC97_DIV __REG(0x41340014) /* AC97 clock divisor value register */ |
| 135 | 136 | ||
| 136 | #define ACCR_XPDIS (1 << 31) /* Core PLL Output Disable */ | 137 | #define ACCR_XPDIS (1 << 31) /* Core PLL Output Disable */ |
diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c index 5dae15ea6718..b6cc1816463e 100644 --- a/arch/arm/mach-pxa/irq.c +++ b/arch/arm/mach-pxa/irq.c | |||
| @@ -17,6 +17,8 @@ | |||
| 17 | #include <linux/syscore_ops.h> | 17 | #include <linux/syscore_ops.h> |
| 18 | #include <linux/io.h> | 18 | #include <linux/io.h> |
| 19 | #include <linux/irq.h> | 19 | #include <linux/irq.h> |
| 20 | #include <linux/of_address.h> | ||
| 21 | #include <linux/of_irq.h> | ||
| 20 | 22 | ||
| 21 | #include <asm/exception.h> | 23 | #include <asm/exception.h> |
| 22 | 24 | ||
| @@ -25,8 +27,6 @@ | |||
| 25 | 27 | ||
| 26 | #include "generic.h" | 28 | #include "generic.h" |
| 27 | 29 | ||
| 28 | #define IRQ_BASE io_p2v(0x40d00000) | ||
| 29 | |||
| 30 | #define ICIP (0x000) | 30 | #define ICIP (0x000) |
| 31 | #define ICMR (0x004) | 31 | #define ICMR (0x004) |
| 32 | #define ICLR (0x008) | 32 | #define ICLR (0x008) |
| @@ -48,22 +48,19 @@ | |||
| 48 | * This is for peripheral IRQs internal to the PXA chip. | 48 | * This is for peripheral IRQs internal to the PXA chip. |
| 49 | */ | 49 | */ |
| 50 | 50 | ||
| 51 | static void __iomem *pxa_irq_base; | ||
| 51 | static int pxa_internal_irq_nr; | 52 | static int pxa_internal_irq_nr; |
| 52 | 53 | static bool cpu_has_ipr; | |
| 53 | static inline int cpu_has_ipr(void) | ||
| 54 | { | ||
| 55 | return !cpu_is_pxa25x(); | ||
| 56 | } | ||
| 57 | 54 | ||
| 58 | static inline void __iomem *irq_base(int i) | 55 | static inline void __iomem *irq_base(int i) |
| 59 | { | 56 | { |
| 60 | static unsigned long phys_base[] = { | 57 | static unsigned long phys_base_offset[] = { |
| 61 | 0x40d00000, | 58 | 0x0, |
| 62 | 0x40d0009c, | 59 | 0x9c, |
| 63 | 0x40d00130, | 60 | 0x130, |
| 64 | }; | 61 | }; |
| 65 | 62 | ||
| 66 | return io_p2v(phys_base[i]); | 63 | return pxa_irq_base + phys_base_offset[i]; |
| 67 | } | 64 | } |
| 68 | 65 | ||
| 69 | void pxa_mask_irq(struct irq_data *d) | 66 | void pxa_mask_irq(struct irq_data *d) |
| @@ -96,8 +93,8 @@ asmlinkage void __exception_irq_entry icip_handle_irq(struct pt_regs *regs) | |||
| 96 | uint32_t icip, icmr, mask; | 93 | uint32_t icip, icmr, mask; |
| 97 | 94 | ||
| 98 | do { | 95 | do { |
| 99 | icip = __raw_readl(IRQ_BASE + ICIP); | 96 | icip = __raw_readl(pxa_irq_base + ICIP); |
| 100 | icmr = __raw_readl(IRQ_BASE + ICMR); | 97 | icmr = __raw_readl(pxa_irq_base + ICMR); |
| 101 | mask = icip & icmr; | 98 | mask = icip & icmr; |
| 102 | 99 | ||
| 103 | if (mask == 0) | 100 | if (mask == 0) |
| @@ -128,6 +125,8 @@ void __init pxa_init_irq(int irq_nr, int (*fn)(struct irq_data *, unsigned int)) | |||
| 128 | BUG_ON(irq_nr > MAX_INTERNAL_IRQS); | 125 | BUG_ON(irq_nr > MAX_INTERNAL_IRQS); |
| 129 | 126 | ||
| 130 | pxa_internal_irq_nr = irq_nr; | 127 | pxa_internal_irq_nr = irq_nr; |
| 128 | cpu_has_ipr = !cpu_is_pxa25x(); | ||
| 129 | pxa_irq_base = io_p2v(0x40d00000); | ||
| 131 | 130 | ||
| 132 | for (n = 0; n < irq_nr; n += 32) { | 131 | for (n = 0; n < irq_nr; n += 32) { |
| 133 | void __iomem *base = irq_base(n >> 5); | 132 | void __iomem *base = irq_base(n >> 5); |
| @@ -136,8 +135,8 @@ void __init pxa_init_irq(int irq_nr, int (*fn)(struct irq_data *, unsigned int)) | |||
| 136 | __raw_writel(0, base + ICLR); /* all IRQs are IRQ, not FIQ */ | 135 | __raw_writel(0, base + ICLR); /* all IRQs are IRQ, not FIQ */ |
| 137 | for (i = n; (i < (n + 32)) && (i < irq_nr); i++) { | 136 | for (i = n; (i < (n + 32)) && (i < irq_nr); i++) { |
| 138 | /* initialize interrupt priority */ | 137 | /* initialize interrupt priority */ |
| 139 | if (cpu_has_ipr()) | 138 | if (cpu_has_ipr) |
| 140 | __raw_writel(i | IPR_VALID, IRQ_BASE + IPR(i)); | 139 | __raw_writel(i | IPR_VALID, pxa_irq_base + IPR(i)); |
| 141 | 140 | ||
| 142 | irq = PXA_IRQ(i); | 141 | irq = PXA_IRQ(i); |
| 143 | irq_set_chip_and_handler(irq, &pxa_internal_irq_chip, | 142 | irq_set_chip_and_handler(irq, &pxa_internal_irq_chip, |
| @@ -168,9 +167,9 @@ static int pxa_irq_suspend(void) | |||
| 168 | __raw_writel(0, base + ICMR); | 167 | __raw_writel(0, base + ICMR); |
| 169 | } | 168 | } |
| 170 | 169 | ||
| 171 | if (cpu_has_ipr()) { | 170 | if (cpu_has_ipr) { |
| 172 | for (i = 0; i < pxa_internal_irq_nr; i++) | 171 | for (i = 0; i < pxa_internal_irq_nr; i++) |
| 173 | saved_ipr[i] = __raw_readl(IRQ_BASE + IPR(i)); | 172 | saved_ipr[i] = __raw_readl(pxa_irq_base + IPR(i)); |
| 174 | } | 173 | } |
| 175 | 174 | ||
| 176 | return 0; | 175 | return 0; |
| @@ -187,11 +186,11 @@ static void pxa_irq_resume(void) | |||
| 187 | __raw_writel(0, base + ICLR); | 186 | __raw_writel(0, base + ICLR); |
| 188 | } | 187 | } |
| 189 | 188 | ||
| 190 | if (cpu_has_ipr()) | 189 | if (cpu_has_ipr) |
| 191 | for (i = 0; i < pxa_internal_irq_nr; i++) | 190 | for (i = 0; i < pxa_internal_irq_nr; i++) |
| 192 | __raw_writel(saved_ipr[i], IRQ_BASE + IPR(i)); | 191 | __raw_writel(saved_ipr[i], pxa_irq_base + IPR(i)); |
| 193 | 192 | ||
| 194 | __raw_writel(1, IRQ_BASE + ICCR); | 193 | __raw_writel(1, pxa_irq_base + ICCR); |
| 195 | } | 194 | } |
| 196 | #else | 195 | #else |
| 197 | #define pxa_irq_suspend NULL | 196 | #define pxa_irq_suspend NULL |
| @@ -202,3 +201,93 @@ struct syscore_ops pxa_irq_syscore_ops = { | |||
| 202 | .suspend = pxa_irq_suspend, | 201 | .suspend = pxa_irq_suspend, |
| 203 | .resume = pxa_irq_resume, | 202 | .resume = pxa_irq_resume, |
| 204 | }; | 203 | }; |
| 204 | |||
| 205 | #ifdef CONFIG_OF | ||
| 206 | static struct irq_domain *pxa_irq_domain; | ||
| 207 | |||
| 208 | static int pxa_irq_map(struct irq_domain *h, unsigned int virq, | ||
| 209 | irq_hw_number_t hw) | ||
| 210 | { | ||
| 211 | void __iomem *base = irq_base(hw / 32); | ||
| 212 | |||
| 213 | /* initialize interrupt priority */ | ||
| 214 | if (cpu_has_ipr) | ||
| 215 | __raw_writel(hw | IPR_VALID, pxa_irq_base + IPR(hw)); | ||
| 216 | |||
| 217 | irq_set_chip_and_handler(hw, &pxa_internal_irq_chip, | ||
| 218 | handle_level_irq); | ||
| 219 | irq_set_chip_data(hw, base); | ||
| 220 | set_irq_flags(hw, IRQF_VALID); | ||
| 221 | |||
| 222 | return 0; | ||
| 223 | } | ||
| 224 | |||
| 225 | static struct irq_domain_ops pxa_irq_ops = { | ||
| 226 | .map = pxa_irq_map, | ||
| 227 | .xlate = irq_domain_xlate_onecell, | ||
| 228 | }; | ||
| 229 | |||
| 230 | static const struct of_device_id intc_ids[] __initconst = { | ||
| 231 | { .compatible = "marvell,pxa-intc", }, | ||
| 232 | {} | ||
| 233 | }; | ||
| 234 | |||
| 235 | void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int)) | ||
| 236 | { | ||
| 237 | struct device_node *node; | ||
| 238 | const struct of_device_id *of_id; | ||
| 239 | struct pxa_intc_conf *conf; | ||
| 240 | struct resource res; | ||
| 241 | int n, ret; | ||
| 242 | |||
| 243 | node = of_find_matching_node(NULL, intc_ids); | ||
| 244 | if (!node) { | ||
| 245 | pr_err("Failed to find interrupt controller in arch-pxa\n"); | ||
| 246 | return; | ||
| 247 | } | ||
| 248 | of_id = of_match_node(intc_ids, node); | ||
| 249 | conf = of_id->data; | ||
| 250 | |||
| 251 | ret = of_property_read_u32(node, "marvell,intc-nr-irqs", | ||
| 252 | &pxa_internal_irq_nr); | ||
| 253 | if (ret) { | ||
| 254 | pr_err("Not found marvell,intc-nr-irqs property\n"); | ||
| 255 | return; | ||
| 256 | } | ||
| 257 | |||
| 258 | ret = of_address_to_resource(node, 0, &res); | ||
| 259 | if (ret < 0) { | ||
| 260 | pr_err("No registers defined for node\n"); | ||
| 261 | return; | ||
| 262 | } | ||
| 263 | pxa_irq_base = io_p2v(res.start); | ||
| 264 | |||
| 265 | if (of_find_property(node, "marvell,intc-priority", NULL)) | ||
| 266 | cpu_has_ipr = 1; | ||
| 267 | |||
| 268 | ret = irq_alloc_descs(-1, 0, pxa_internal_irq_nr, 0); | ||
| 269 | if (ret < 0) { | ||
| 270 | pr_err("Failed to allocate IRQ numbers\n"); | ||
| 271 | return; | ||
| 272 | } | ||
| 273 | |||
| 274 | pxa_irq_domain = irq_domain_add_legacy(node, pxa_internal_irq_nr, 0, 0, | ||
| 275 | &pxa_irq_ops, NULL); | ||
| 276 | if (!pxa_irq_domain) | ||
| 277 | panic("Unable to add PXA IRQ domain\n"); | ||
| 278 | |||
| 279 | irq_set_default_host(pxa_irq_domain); | ||
| 280 | |||
| 281 | for (n = 0; n < pxa_internal_irq_nr; n += 32) { | ||
| 282 | void __iomem *base = irq_base(n >> 5); | ||
| 283 | |||
| 284 | __raw_writel(0, base + ICMR); /* disable all IRQs */ | ||
| 285 | __raw_writel(0, base + ICLR); /* all IRQs are IRQ, not FIQ */ | ||
| 286 | } | ||
| 287 | |||
| 288 | /* only unmasked interrupts kick us out of idle */ | ||
| 289 | __raw_writel(1, irq_base(0) + ICCR); | ||
| 290 | |||
| 291 | pxa_internal_irq_chip.irq_set_wake = fn; | ||
| 292 | } | ||
| 293 | #endif /* CONFIG_OF */ | ||
diff --git a/arch/arm/mach-pxa/pxa-dt.c b/arch/arm/mach-pxa/pxa-dt.c new file mode 100644 index 000000000000..c9192cea0033 --- /dev/null +++ b/arch/arm/mach-pxa/pxa-dt.c | |||
| @@ -0,0 +1,63 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-pxa/pxa-dt.c | ||
| 3 | * | ||
| 4 | * Copyright (C) 2012 Daniel Mack | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * publishhed by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/irq.h> | ||
| 12 | #include <linux/irqdomain.h> | ||
| 13 | #include <linux/of_irq.h> | ||
| 14 | #include <linux/of_platform.h> | ||
| 15 | #include <asm/mach/arch.h> | ||
| 16 | #include <asm/mach/time.h> | ||
| 17 | #include <mach/irqs.h> | ||
| 18 | #include <mach/pxa3xx.h> | ||
| 19 | |||
| 20 | #include "generic.h" | ||
| 21 | |||
| 22 | #ifdef CONFIG_PXA3xx | ||
| 23 | extern void __init pxa3xx_dt_init_irq(void); | ||
| 24 | |||
| 25 | static const struct of_dev_auxdata pxa3xx_auxdata_lookup[] __initconst = { | ||
| 26 | OF_DEV_AUXDATA("mrvl,pxa-uart", 0x40100000, "pxa2xx-uart.0", NULL), | ||
| 27 | OF_DEV_AUXDATA("mrvl,pxa-uart", 0x40200000, "pxa2xx-uart.1", NULL), | ||
| 28 | OF_DEV_AUXDATA("mrvl,pxa-uart", 0x40700000, "pxa2xx-uart.2", NULL), | ||
| 29 | OF_DEV_AUXDATA("mrvl,pxa-uart", 0x41600000, "pxa2xx-uart.3", NULL), | ||
| 30 | OF_DEV_AUXDATA("marvell,pxa-mmc", 0x41100000, "pxa2xx-mci.0", NULL), | ||
| 31 | OF_DEV_AUXDATA("mrvl,pxa-gpio", 0x40e00000, "pxa-gpio", NULL), | ||
| 32 | OF_DEV_AUXDATA("marvell,pxa-ohci", 0x4c000000, "pxa27x-ohci", NULL), | ||
| 33 | OF_DEV_AUXDATA("mrvl,pxa-i2c", 0x40301680, "pxa2xx-i2c.0", NULL), | ||
| 34 | OF_DEV_AUXDATA("mrvl,pwri2c", 0x40f500c0, "pxa3xx-i2c.1", NULL), | ||
| 35 | OF_DEV_AUXDATA("marvell,pxa3xx-nand", 0x43100000, "pxa3xx-nand", NULL), | ||
| 36 | {} | ||
| 37 | }; | ||
| 38 | |||
| 39 | static void __init pxa3xx_dt_init(void) | ||
| 40 | { | ||
| 41 | of_platform_populate(NULL, of_default_bus_match_table, | ||
| 42 | pxa3xx_auxdata_lookup, NULL); | ||
| 43 | } | ||
| 44 | |||
| 45 | static const char *pxa3xx_dt_board_compat[] __initdata = { | ||
| 46 | "marvell,pxa300", | ||
| 47 | "marvell,pxa310", | ||
| 48 | "marvell,pxa320", | ||
| 49 | NULL, | ||
| 50 | }; | ||
| 51 | #endif | ||
| 52 | |||
| 53 | #ifdef CONFIG_PXA3xx | ||
| 54 | DT_MACHINE_START(PXA_DT, "Marvell PXA3xx (Device Tree Support)") | ||
| 55 | .map_io = pxa3xx_map_io, | ||
| 56 | .init_irq = pxa3xx_dt_init_irq, | ||
| 57 | .handle_irq = pxa3xx_handle_irq, | ||
| 58 | .timer = &pxa_timer, | ||
| 59 | .restart = pxa_restart, | ||
| 60 | .init_machine = pxa3xx_dt_init, | ||
| 61 | .dt_compat = pxa3xx_dt_board_compat, | ||
| 62 | MACHINE_END | ||
| 63 | #endif | ||
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c index dffb7e813d98..ff9c9574ec3e 100644 --- a/arch/arm/mach-pxa/pxa3xx.c +++ b/arch/arm/mach-pxa/pxa3xx.c | |||
| @@ -19,6 +19,7 @@ | |||
| 19 | #include <linux/platform_device.h> | 19 | #include <linux/platform_device.h> |
| 20 | #include <linux/irq.h> | 20 | #include <linux/irq.h> |
| 21 | #include <linux/io.h> | 21 | #include <linux/io.h> |
| 22 | #include <linux/of.h> | ||
| 22 | #include <linux/syscore_ops.h> | 23 | #include <linux/syscore_ops.h> |
| 23 | #include <linux/i2c/pxa-i2c.h> | 24 | #include <linux/i2c/pxa-i2c.h> |
| 24 | 25 | ||
| @@ -40,6 +41,8 @@ | |||
| 40 | #define PECR_IE(n) ((1 << ((n) * 2)) << 28) | 41 | #define PECR_IE(n) ((1 << ((n) * 2)) << 28) |
| 41 | #define PECR_IS(n) ((1 << ((n) * 2)) << 29) | 42 | #define PECR_IS(n) ((1 << ((n) * 2)) << 29) |
| 42 | 43 | ||
| 44 | extern void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int)); | ||
| 45 | |||
| 43 | static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1); | 46 | static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1); |
| 44 | static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1); | 47 | static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1); |
| 45 | static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1); | 48 | static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1); |
| @@ -382,7 +385,7 @@ static void __init pxa_init_ext_wakeup_irq(int (*fn)(struct irq_data *, | |||
| 382 | pxa_ext_wakeup_chip.irq_set_wake = fn; | 385 | pxa_ext_wakeup_chip.irq_set_wake = fn; |
| 383 | } | 386 | } |
| 384 | 387 | ||
| 385 | void __init pxa3xx_init_irq(void) | 388 | static void __init __pxa3xx_init_irq(void) |
| 386 | { | 389 | { |
| 387 | /* enable CP6 access */ | 390 | /* enable CP6 access */ |
| 388 | u32 value; | 391 | u32 value; |
| @@ -390,10 +393,23 @@ void __init pxa3xx_init_irq(void) | |||
| 390 | value |= (1 << 6); | 393 | value |= (1 << 6); |
| 391 | __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value)); | 394 | __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value)); |
| 392 | 395 | ||
| 393 | pxa_init_irq(56, pxa3xx_set_wake); | ||
| 394 | pxa_init_ext_wakeup_irq(pxa3xx_set_wake); | 396 | pxa_init_ext_wakeup_irq(pxa3xx_set_wake); |
| 395 | } | 397 | } |
| 396 | 398 | ||
| 399 | void __init pxa3xx_init_irq(void) | ||
| 400 | { | ||
| 401 | __pxa3xx_init_irq(); | ||
| 402 | pxa_init_irq(56, pxa3xx_set_wake); | ||
| 403 | } | ||
| 404 | |||
| 405 | #ifdef CONFIG_OF | ||
| 406 | void __init pxa3xx_dt_init_irq(void) | ||
| 407 | { | ||
| 408 | __pxa3xx_init_irq(); | ||
| 409 | pxa_dt_irq_init(pxa3xx_set_wake); | ||
| 410 | } | ||
| 411 | #endif /* CONFIG_OF */ | ||
| 412 | |||
| 397 | static struct map_desc pxa3xx_io_desc[] __initdata = { | 413 | static struct map_desc pxa3xx_io_desc[] __initdata = { |
| 398 | { /* Mem Ctl */ | 414 | { /* Mem Ctl */ |
| 399 | .virtual = (unsigned long)SMEMC_VIRT, | 415 | .virtual = (unsigned long)SMEMC_VIRT, |
| @@ -466,7 +482,8 @@ static int __init pxa3xx_init(void) | |||
| 466 | register_syscore_ops(&pxa3xx_mfp_syscore_ops); | 482 | register_syscore_ops(&pxa3xx_mfp_syscore_ops); |
| 467 | register_syscore_ops(&pxa3xx_clock_syscore_ops); | 483 | register_syscore_ops(&pxa3xx_clock_syscore_ops); |
| 468 | 484 | ||
| 469 | ret = platform_add_devices(devices, ARRAY_SIZE(devices)); | 485 | if (!of_have_populated_dt()) |
| 486 | ret = platform_add_devices(devices, ARRAY_SIZE(devices)); | ||
| 470 | } | 487 | } |
| 471 | 488 | ||
| 472 | return ret; | 489 | return ret; |
diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c index 45868bb43cbd..ff007d15e0ec 100644 --- a/arch/arm/mach-realview/core.c +++ b/arch/arm/mach-realview/core.c | |||
| @@ -30,7 +30,6 @@ | |||
| 30 | #include <linux/ata_platform.h> | 30 | #include <linux/ata_platform.h> |
| 31 | #include <linux/amba/mmci.h> | 31 | #include <linux/amba/mmci.h> |
| 32 | #include <linux/gfp.h> | 32 | #include <linux/gfp.h> |
| 33 | #include <linux/clkdev.h> | ||
| 34 | #include <linux/mtd/physmap.h> | 33 | #include <linux/mtd/physmap.h> |
| 35 | 34 | ||
| 36 | #include <mach/hardware.h> | 35 | #include <mach/hardware.h> |
| @@ -226,115 +225,10 @@ struct mmci_platform_data realview_mmc1_plat_data = { | |||
| 226 | .cd_invert = true, | 225 | .cd_invert = true, |
| 227 | }; | 226 | }; |
| 228 | 227 | ||
| 229 | /* | ||
| 230 | * Clock handling | ||
| 231 | */ | ||
| 232 | static const struct icst_params realview_oscvco_params = { | ||
| 233 | .ref = 24000000, | ||
| 234 | .vco_max = ICST307_VCO_MAX, | ||
| 235 | .vco_min = ICST307_VCO_MIN, | ||
| 236 | .vd_min = 4 + 8, | ||
| 237 | .vd_max = 511 + 8, | ||
| 238 | .rd_min = 1 + 2, | ||
| 239 | .rd_max = 127 + 2, | ||
| 240 | .s2div = icst307_s2div, | ||
| 241 | .idx2s = icst307_idx2s, | ||
| 242 | }; | ||
| 243 | |||
| 244 | static void realview_oscvco_set(struct clk *clk, struct icst_vco vco) | ||
| 245 | { | ||
| 246 | void __iomem *sys_lock = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LOCK_OFFSET; | ||
| 247 | u32 val; | ||
| 248 | |||
| 249 | val = readl(clk->vcoreg) & ~0x7ffff; | ||
| 250 | val |= vco.v | (vco.r << 9) | (vco.s << 16); | ||
| 251 | |||
| 252 | writel(0xa05f, sys_lock); | ||
| 253 | writel(val, clk->vcoreg); | ||
| 254 | writel(0, sys_lock); | ||
| 255 | } | ||
| 256 | |||
| 257 | static const struct clk_ops oscvco_clk_ops = { | ||
| 258 | .round = icst_clk_round, | ||
| 259 | .set = icst_clk_set, | ||
| 260 | .setvco = realview_oscvco_set, | ||
| 261 | }; | ||
| 262 | |||
| 263 | static struct clk oscvco_clk = { | ||
| 264 | .ops = &oscvco_clk_ops, | ||
| 265 | .params = &realview_oscvco_params, | ||
| 266 | }; | ||
| 267 | |||
| 268 | /* | ||
| 269 | * These are fixed clocks. | ||
| 270 | */ | ||
| 271 | static struct clk ref24_clk = { | ||
| 272 | .rate = 24000000, | ||
| 273 | }; | ||
| 274 | |||
| 275 | static struct clk sp804_clk = { | ||
| 276 | .rate = 1000000, | ||
| 277 | }; | ||
| 278 | |||
| 279 | static struct clk dummy_apb_pclk; | ||
| 280 | |||
| 281 | static struct clk_lookup lookups[] = { | ||
| 282 | { /* Bus clock */ | ||
| 283 | .con_id = "apb_pclk", | ||
| 284 | .clk = &dummy_apb_pclk, | ||
| 285 | }, { /* UART0 */ | ||
| 286 | .dev_id = "dev:uart0", | ||
| 287 | .clk = &ref24_clk, | ||
| 288 | }, { /* UART1 */ | ||
| 289 | .dev_id = "dev:uart1", | ||
| 290 | .clk = &ref24_clk, | ||
| 291 | }, { /* UART2 */ | ||
| 292 | .dev_id = "dev:uart2", | ||
| 293 | .clk = &ref24_clk, | ||
| 294 | }, { /* UART3 */ | ||
| 295 | .dev_id = "fpga:uart3", | ||
| 296 | .clk = &ref24_clk, | ||
| 297 | }, { /* UART3 is on the dev chip in PB1176 */ | ||
| 298 | .dev_id = "dev:uart3", | ||
| 299 | .clk = &ref24_clk, | ||
| 300 | }, { /* UART4 only exists in PB1176 */ | ||
| 301 | .dev_id = "fpga:uart4", | ||
| 302 | .clk = &ref24_clk, | ||
| 303 | }, { /* KMI0 */ | ||
| 304 | .dev_id = "fpga:kmi0", | ||
| 305 | .clk = &ref24_clk, | ||
| 306 | }, { /* KMI1 */ | ||
| 307 | .dev_id = "fpga:kmi1", | ||
| 308 | .clk = &ref24_clk, | ||
| 309 | }, { /* MMC0 */ | ||
| 310 | .dev_id = "fpga:mmc0", | ||
| 311 | .clk = &ref24_clk, | ||
| 312 | }, { /* CLCD is in the PB1176 and EB DevChip */ | ||
| 313 | .dev_id = "dev:clcd", | ||
| 314 | .clk = &oscvco_clk, | ||
| 315 | }, { /* PB:CLCD */ | ||
| 316 | .dev_id = "issp:clcd", | ||
| 317 | .clk = &oscvco_clk, | ||
| 318 | }, { /* SSP */ | ||
| 319 | .dev_id = "dev:ssp0", | ||
| 320 | .clk = &ref24_clk, | ||
| 321 | }, { /* SP804 timers */ | ||
| 322 | .dev_id = "sp804", | ||
| 323 | .clk = &sp804_clk, | ||
| 324 | }, | ||
| 325 | }; | ||
| 326 | |||
| 327 | void __init realview_init_early(void) | 228 | void __init realview_init_early(void) |
| 328 | { | 229 | { |
| 329 | void __iomem *sys = __io_address(REALVIEW_SYS_BASE); | 230 | void __iomem *sys = __io_address(REALVIEW_SYS_BASE); |
| 330 | 231 | ||
| 331 | if (machine_is_realview_pb1176()) | ||
| 332 | oscvco_clk.vcoreg = sys + REALVIEW_SYS_OSC0_OFFSET; | ||
| 333 | else | ||
| 334 | oscvco_clk.vcoreg = sys + REALVIEW_SYS_OSC4_OFFSET; | ||
| 335 | |||
| 336 | clkdev_add_table(lookups, ARRAY_SIZE(lookups)); | ||
| 337 | |||
| 338 | versatile_sched_clock_init(sys + REALVIEW_SYS_24MHz_OFFSET, 24000000); | 232 | versatile_sched_clock_init(sys + REALVIEW_SYS_24MHz_OFFSET, 24000000); |
| 339 | } | 233 | } |
| 340 | 234 | ||
diff --git a/arch/arm/mach-realview/include/mach/clkdev.h b/arch/arm/mach-realview/include/mach/clkdev.h deleted file mode 100644 index e58d0771b64e..000000000000 --- a/arch/arm/mach-realview/include/mach/clkdev.h +++ /dev/null | |||
| @@ -1,16 +0,0 @@ | |||
| 1 | #ifndef __ASM_MACH_CLKDEV_H | ||
| 2 | #define __ASM_MACH_CLKDEV_H | ||
| 3 | |||
| 4 | #include <plat/clock.h> | ||
| 5 | |||
| 6 | struct clk { | ||
| 7 | unsigned long rate; | ||
| 8 | const struct clk_ops *ops; | ||
| 9 | const struct icst_params *params; | ||
| 10 | void __iomem *vcoreg; | ||
| 11 | }; | ||
| 12 | |||
| 13 | #define __clk_get(clk) ({ 1; }) | ||
| 14 | #define __clk_put(clk) do { } while (0) | ||
| 15 | |||
| 16 | #endif | ||
diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c index baf382c5e776..a33e33b76733 100644 --- a/arch/arm/mach-realview/realview_eb.c +++ b/arch/arm/mach-realview/realview_eb.c | |||
| @@ -27,6 +27,7 @@ | |||
| 27 | #include <linux/amba/mmci.h> | 27 | #include <linux/amba/mmci.h> |
| 28 | #include <linux/amba/pl022.h> | 28 | #include <linux/amba/pl022.h> |
| 29 | #include <linux/io.h> | 29 | #include <linux/io.h> |
| 30 | #include <linux/platform_data/clk-realview.h> | ||
| 30 | 31 | ||
| 31 | #include <mach/hardware.h> | 32 | #include <mach/hardware.h> |
| 32 | #include <asm/irq.h> | 33 | #include <asm/irq.h> |
| @@ -414,6 +415,7 @@ static void __init realview_eb_timer_init(void) | |||
| 414 | else | 415 | else |
| 415 | timer_irq = IRQ_EB_TIMER0_1; | 416 | timer_irq = IRQ_EB_TIMER0_1; |
| 416 | 417 | ||
| 418 | realview_clk_init(__io_address(REALVIEW_SYS_BASE), false); | ||
| 417 | realview_timer_init(timer_irq); | 419 | realview_timer_init(timer_irq); |
| 418 | realview_eb_twd_init(); | 420 | realview_eb_twd_init(); |
| 419 | } | 421 | } |
diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c index b1d7cafa1a6d..f0298cbc203e 100644 --- a/arch/arm/mach-realview/realview_pb1176.c +++ b/arch/arm/mach-realview/realview_pb1176.c | |||
| @@ -29,6 +29,7 @@ | |||
| 29 | #include <linux/mtd/physmap.h> | 29 | #include <linux/mtd/physmap.h> |
| 30 | #include <linux/mtd/partitions.h> | 30 | #include <linux/mtd/partitions.h> |
| 31 | #include <linux/io.h> | 31 | #include <linux/io.h> |
| 32 | #include <linux/platform_data/clk-realview.h> | ||
| 32 | 33 | ||
| 33 | #include <mach/hardware.h> | 34 | #include <mach/hardware.h> |
| 34 | #include <asm/irq.h> | 35 | #include <asm/irq.h> |
| @@ -326,6 +327,7 @@ static void __init realview_pb1176_timer_init(void) | |||
| 326 | timer2_va_base = __io_address(REALVIEW_PB1176_TIMER2_3_BASE); | 327 | timer2_va_base = __io_address(REALVIEW_PB1176_TIMER2_3_BASE); |
| 327 | timer3_va_base = __io_address(REALVIEW_PB1176_TIMER2_3_BASE) + 0x20; | 328 | timer3_va_base = __io_address(REALVIEW_PB1176_TIMER2_3_BASE) + 0x20; |
| 328 | 329 | ||
| 330 | realview_clk_init(__io_address(REALVIEW_SYS_BASE), true); | ||
| 329 | realview_timer_init(IRQ_DC1176_TIMER0); | 331 | realview_timer_init(IRQ_DC1176_TIMER0); |
| 330 | } | 332 | } |
| 331 | 333 | ||
diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c index a98c536e3327..1f019f76f7b5 100644 --- a/arch/arm/mach-realview/realview_pb11mp.c +++ b/arch/arm/mach-realview/realview_pb11mp.c | |||
| @@ -27,6 +27,7 @@ | |||
| 27 | #include <linux/amba/mmci.h> | 27 | #include <linux/amba/mmci.h> |
| 28 | #include <linux/amba/pl022.h> | 28 | #include <linux/amba/pl022.h> |
| 29 | #include <linux/io.h> | 29 | #include <linux/io.h> |
| 30 | #include <linux/platform_data/clk-realview.h> | ||
| 30 | 31 | ||
| 31 | #include <mach/hardware.h> | 32 | #include <mach/hardware.h> |
| 32 | #include <asm/irq.h> | 33 | #include <asm/irq.h> |
| @@ -312,6 +313,7 @@ static void __init realview_pb11mp_timer_init(void) | |||
| 312 | timer2_va_base = __io_address(REALVIEW_PB11MP_TIMER2_3_BASE); | 313 | timer2_va_base = __io_address(REALVIEW_PB11MP_TIMER2_3_BASE); |
| 313 | timer3_va_base = __io_address(REALVIEW_PB11MP_TIMER2_3_BASE) + 0x20; | 314 | timer3_va_base = __io_address(REALVIEW_PB11MP_TIMER2_3_BASE) + 0x20; |
| 314 | 315 | ||
| 316 | realview_clk_init(__io_address(REALVIEW_SYS_BASE), false); | ||
| 315 | realview_timer_init(IRQ_TC11MP_TIMER0_1); | 317 | realview_timer_init(IRQ_TC11MP_TIMER0_1); |
| 316 | realview_pb11mp_twd_init(); | 318 | realview_pb11mp_twd_init(); |
| 317 | } | 319 | } |
diff --git a/arch/arm/mach-realview/realview_pba8.c b/arch/arm/mach-realview/realview_pba8.c index 59650174e6ed..5032775dbfee 100644 --- a/arch/arm/mach-realview/realview_pba8.c +++ b/arch/arm/mach-realview/realview_pba8.c | |||
| @@ -27,6 +27,7 @@ | |||
| 27 | #include <linux/amba/mmci.h> | 27 | #include <linux/amba/mmci.h> |
| 28 | #include <linux/amba/pl022.h> | 28 | #include <linux/amba/pl022.h> |
| 29 | #include <linux/io.h> | 29 | #include <linux/io.h> |
| 30 | #include <linux/platform_data/clk-realview.h> | ||
| 30 | 31 | ||
| 31 | #include <asm/irq.h> | 32 | #include <asm/irq.h> |
| 32 | #include <asm/leds.h> | 33 | #include <asm/leds.h> |
| @@ -261,6 +262,7 @@ static void __init realview_pba8_timer_init(void) | |||
| 261 | timer2_va_base = __io_address(REALVIEW_PBA8_TIMER2_3_BASE); | 262 | timer2_va_base = __io_address(REALVIEW_PBA8_TIMER2_3_BASE); |
| 262 | timer3_va_base = __io_address(REALVIEW_PBA8_TIMER2_3_BASE) + 0x20; | 263 | timer3_va_base = __io_address(REALVIEW_PBA8_TIMER2_3_BASE) + 0x20; |
| 263 | 264 | ||
| 265 | realview_clk_init(__io_address(REALVIEW_SYS_BASE), false); | ||
| 264 | realview_timer_init(IRQ_PBA8_TIMER0_1); | 266 | realview_timer_init(IRQ_PBA8_TIMER0_1); |
| 265 | } | 267 | } |
| 266 | 268 | ||
diff --git a/arch/arm/mach-realview/realview_pbx.c b/arch/arm/mach-realview/realview_pbx.c index 3f2f605624e9..de64ba0ddb95 100644 --- a/arch/arm/mach-realview/realview_pbx.c +++ b/arch/arm/mach-realview/realview_pbx.c | |||
| @@ -26,6 +26,7 @@ | |||
| 26 | #include <linux/amba/mmci.h> | 26 | #include <linux/amba/mmci.h> |
| 27 | #include <linux/amba/pl022.h> | 27 | #include <linux/amba/pl022.h> |
| 28 | #include <linux/io.h> | 28 | #include <linux/io.h> |
| 29 | #include <linux/platform_data/clk-realview.h> | ||
| 29 | 30 | ||
| 30 | #include <asm/irq.h> | 31 | #include <asm/irq.h> |
| 31 | #include <asm/leds.h> | 32 | #include <asm/leds.h> |
| @@ -320,6 +321,7 @@ static void __init realview_pbx_timer_init(void) | |||
| 320 | timer2_va_base = __io_address(REALVIEW_PBX_TIMER2_3_BASE); | 321 | timer2_va_base = __io_address(REALVIEW_PBX_TIMER2_3_BASE); |
| 321 | timer3_va_base = __io_address(REALVIEW_PBX_TIMER2_3_BASE) + 0x20; | 322 | timer3_va_base = __io_address(REALVIEW_PBX_TIMER2_3_BASE) + 0x20; |
| 322 | 323 | ||
| 324 | realview_clk_init(__io_address(REALVIEW_SYS_BASE), false); | ||
| 323 | realview_timer_init(IRQ_PBX_TIMER0_1); | 325 | realview_timer_init(IRQ_PBX_TIMER0_1); |
| 324 | realview_pbx_twd_init(); | 326 | realview_pbx_twd_init(); |
| 325 | } | 327 | } |
diff --git a/arch/arm/mach-shmobile/Makefile.boot b/arch/arm/mach-shmobile/Makefile.boot index 498efd99338d..5e410192ffb8 100644 --- a/arch/arm/mach-shmobile/Makefile.boot +++ b/arch/arm/mach-shmobile/Makefile.boot | |||
| @@ -7,3 +7,7 @@ __ZRELADDR := $(shell /bin/bash -c 'printf "0x%08x" \ | |||
| 7 | # | 7 | # |
| 8 | #params_phys-y (Instead: Pass atags pointer in r2) | 8 | #params_phys-y (Instead: Pass atags pointer in r2) |
| 9 | #initrd_phys-y (Instead: Use compiled-in initramfs) | 9 | #initrd_phys-y (Instead: Use compiled-in initramfs) |
| 10 | |||
| 11 | dtb-$(CONFIG_MACH_KZM9G) += sh73a0-kzm9g.dtb | ||
| 12 | dtb-$(CONFIG_MACH_KZM9D) += emev2-kzm9d.dtb | ||
| 13 | dtb-$(CONFIG_MACH_ARMADILLO800EVA) += r8a7740-armadillo800eva.dtb | ||
diff --git a/arch/arm/mach-tegra/Makefile.boot b/arch/arm/mach-tegra/Makefile.boot index 7a1bb62ddcf0..54c16aade475 100644 --- a/arch/arm/mach-tegra/Makefile.boot +++ b/arch/arm/mach-tegra/Makefile.boot | |||
| @@ -3,9 +3,13 @@ params_phys-$(CONFIG_ARCH_TEGRA_2x_SOC) := 0x00000100 | |||
| 3 | initrd_phys-$(CONFIG_ARCH_TEGRA_2x_SOC) := 0x00800000 | 3 | initrd_phys-$(CONFIG_ARCH_TEGRA_2x_SOC) := 0x00800000 |
| 4 | 4 | ||
| 5 | dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-harmony.dtb | 5 | dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-harmony.dtb |
| 6 | dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-medcom-wide.dtb | ||
| 6 | dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-paz00.dtb | 7 | dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-paz00.dtb |
| 8 | dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-plutux.dtb | ||
| 7 | dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-seaboard.dtb | 9 | dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-seaboard.dtb |
| 10 | dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-tec.dtb | ||
| 8 | dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-trimslice.dtb | 11 | dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-trimslice.dtb |
| 9 | dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-ventana.dtb | 12 | dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-ventana.dtb |
| 10 | dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-whistler.dtb | 13 | dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-whistler.dtb |
| 11 | dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30-cardhu.dtb | 14 | dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30-cardhu-a02.dtb |
| 15 | dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30-cardhu-a04.dtb | ||
diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig index 53d3d46dec12..a258996d954b 100644 --- a/arch/arm/mach-ux500/Kconfig +++ b/arch/arm/mach-ux500/Kconfig | |||
| @@ -11,6 +11,7 @@ config UX500_SOC_COMMON | |||
| 11 | select CACHE_L2X0 | 11 | select CACHE_L2X0 |
| 12 | select PINCTRL | 12 | select PINCTRL |
| 13 | select PINCTRL_NOMADIK | 13 | select PINCTRL_NOMADIK |
| 14 | select COMMON_CLK | ||
| 14 | 15 | ||
| 15 | config UX500_SOC_DB8500 | 16 | config UX500_SOC_DB8500 |
| 16 | bool | 17 | bool |
diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile index 026086ff9e6c..f24710dfc395 100644 --- a/arch/arm/mach-ux500/Makefile +++ b/arch/arm/mach-ux500/Makefile | |||
| @@ -2,7 +2,7 @@ | |||
| 2 | # Makefile for the linux kernel, U8500 machine. | 2 | # Makefile for the linux kernel, U8500 machine. |
| 3 | # | 3 | # |
| 4 | 4 | ||
| 5 | obj-y := clock.o cpu.o devices.o devices-common.o \ | 5 | obj-y := cpu.o devices.o devices-common.o \ |
| 6 | id.o usb.o timer.o | 6 | id.o usb.o timer.o |
| 7 | obj-$(CONFIG_CPU_IDLE) += cpuidle.o | 7 | obj-$(CONFIG_CPU_IDLE) += cpuidle.o |
| 8 | obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o | 8 | obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o |
| @@ -12,6 +12,6 @@ obj-$(CONFIG_MACH_MOP500) += board-mop500.o board-mop500-sdi.o \ | |||
| 12 | board-mop500-uib.o board-mop500-stuib.o \ | 12 | board-mop500-uib.o board-mop500-stuib.o \ |
| 13 | board-mop500-u8500uib.o \ | 13 | board-mop500-u8500uib.o \ |
| 14 | board-mop500-pins.o \ | 14 | board-mop500-pins.o \ |
| 15 | board-mop500-msp.o | 15 | board-mop500-audio.o |
| 16 | obj-$(CONFIG_SMP) += platsmp.o headsmp.o | 16 | obj-$(CONFIG_SMP) += platsmp.o headsmp.o |
| 17 | obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o | 17 | obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o |
diff --git a/arch/arm/mach-ux500/board-mop500-msp.c b/arch/arm/mach-ux500/board-mop500-audio.c index df15646036aa..070629a95625 100644 --- a/arch/arm/mach-ux500/board-mop500-msp.c +++ b/arch/arm/mach-ux500/board-mop500-audio.c | |||
| @@ -7,7 +7,6 @@ | |||
| 7 | #include <linux/platform_device.h> | 7 | #include <linux/platform_device.h> |
| 8 | #include <linux/init.h> | 8 | #include <linux/init.h> |
| 9 | #include <linux/gpio.h> | 9 | #include <linux/gpio.h> |
| 10 | #include <linux/pinctrl/consumer.h> | ||
| 11 | 10 | ||
| 12 | #include <plat/gpio-nomadik.h> | 11 | #include <plat/gpio-nomadik.h> |
| 13 | #include <plat/pincfg.h> | 12 | #include <plat/pincfg.h> |
| @@ -23,53 +22,6 @@ | |||
| 23 | #include "devices-db8500.h" | 22 | #include "devices-db8500.h" |
| 24 | #include "pins-db8500.h" | 23 | #include "pins-db8500.h" |
| 25 | 24 | ||
| 26 | /* MSP1/3 Tx/Rx usage protection */ | ||
| 27 | static DEFINE_SPINLOCK(msp_rxtx_lock); | ||
| 28 | |||
| 29 | /* Reference Count */ | ||
| 30 | static int msp_rxtx_ref; | ||
| 31 | |||
| 32 | /* Pin modes */ | ||
| 33 | struct pinctrl *msp1_p; | ||
| 34 | struct pinctrl_state *msp1_def; | ||
| 35 | struct pinctrl_state *msp1_sleep; | ||
| 36 | |||
| 37 | int msp13_i2s_init(void) | ||
| 38 | { | ||
| 39 | int retval = 0; | ||
| 40 | unsigned long flags; | ||
| 41 | |||
| 42 | spin_lock_irqsave(&msp_rxtx_lock, flags); | ||
| 43 | if (msp_rxtx_ref == 0 && !(IS_ERR(msp1_p) || IS_ERR(msp1_def))) { | ||
| 44 | retval = pinctrl_select_state(msp1_p, msp1_def); | ||
| 45 | if (retval) | ||
| 46 | pr_err("could not set MSP1 defstate\n"); | ||
| 47 | } | ||
| 48 | if (!retval) | ||
| 49 | msp_rxtx_ref++; | ||
| 50 | spin_unlock_irqrestore(&msp_rxtx_lock, flags); | ||
| 51 | |||
| 52 | return retval; | ||
| 53 | } | ||
| 54 | |||
| 55 | int msp13_i2s_exit(void) | ||
| 56 | { | ||
| 57 | int retval = 0; | ||
| 58 | unsigned long flags; | ||
| 59 | |||
| 60 | spin_lock_irqsave(&msp_rxtx_lock, flags); | ||
| 61 | WARN_ON(!msp_rxtx_ref); | ||
| 62 | msp_rxtx_ref--; | ||
| 63 | if (msp_rxtx_ref == 0 && !(IS_ERR(msp1_p) || IS_ERR(msp1_sleep))) { | ||
| 64 | retval = pinctrl_select_state(msp1_p, msp1_sleep); | ||
| 65 | if (retval) | ||
| 66 | pr_err("could not set MSP1 sleepstate\n"); | ||
| 67 | } | ||
| 68 | spin_unlock_irqrestore(&msp_rxtx_lock, flags); | ||
| 69 | |||
| 70 | return retval; | ||
| 71 | } | ||
| 72 | |||
| 73 | static struct stedma40_chan_cfg msp0_dma_rx = { | 25 | static struct stedma40_chan_cfg msp0_dma_rx = { |
| 74 | .high_priority = true, | 26 | .high_priority = true, |
| 75 | .dir = STEDMA40_PERIPH_TO_MEM, | 27 | .dir = STEDMA40_PERIPH_TO_MEM, |
| @@ -96,7 +48,7 @@ static struct stedma40_chan_cfg msp0_dma_tx = { | |||
| 96 | /* data_width is set during configuration */ | 48 | /* data_width is set during configuration */ |
| 97 | }; | 49 | }; |
| 98 | 50 | ||
| 99 | static struct msp_i2s_platform_data msp0_platform_data = { | 51 | struct msp_i2s_platform_data msp0_platform_data = { |
| 100 | .id = MSP_I2S_0, | 52 | .id = MSP_I2S_0, |
| 101 | .msp_i2s_dma_rx = &msp0_dma_rx, | 53 | .msp_i2s_dma_rx = &msp0_dma_rx, |
| 102 | .msp_i2s_dma_tx = &msp0_dma_tx, | 54 | .msp_i2s_dma_tx = &msp0_dma_tx, |
| @@ -128,12 +80,10 @@ static struct stedma40_chan_cfg msp1_dma_tx = { | |||
| 128 | /* data_width is set during configuration */ | 80 | /* data_width is set during configuration */ |
| 129 | }; | 81 | }; |
| 130 | 82 | ||
| 131 | static struct msp_i2s_platform_data msp1_platform_data = { | 83 | struct msp_i2s_platform_data msp1_platform_data = { |
| 132 | .id = MSP_I2S_1, | 84 | .id = MSP_I2S_1, |
| 133 | .msp_i2s_dma_rx = NULL, | 85 | .msp_i2s_dma_rx = NULL, |
| 134 | .msp_i2s_dma_tx = &msp1_dma_tx, | 86 | .msp_i2s_dma_tx = &msp1_dma_tx, |
| 135 | .msp_i2s_init = msp13_i2s_init, | ||
| 136 | .msp_i2s_exit = msp13_i2s_exit, | ||
| 137 | }; | 87 | }; |
| 138 | 88 | ||
| 139 | static struct stedma40_chan_cfg msp2_dma_rx = { | 89 | static struct stedma40_chan_cfg msp2_dma_rx = { |
| @@ -193,11 +143,11 @@ static struct platform_device *db8500_add_msp_i2s(struct device *parent, | |||
| 193 | 143 | ||
| 194 | /* Platform device for ASoC MOP500 machine */ | 144 | /* Platform device for ASoC MOP500 machine */ |
| 195 | static struct platform_device snd_soc_mop500 = { | 145 | static struct platform_device snd_soc_mop500 = { |
| 196 | .name = "snd-soc-mop500", | 146 | .name = "snd-soc-mop500", |
| 197 | .id = 0, | 147 | .id = 0, |
| 198 | .dev = { | 148 | .dev = { |
| 199 | .platform_data = NULL, | 149 | .platform_data = NULL, |
| 200 | }, | 150 | }, |
| 201 | }; | 151 | }; |
| 202 | 152 | ||
| 203 | /* Platform device for Ux500-PCM */ | 153 | /* Platform device for Ux500-PCM */ |
| @@ -209,59 +159,37 @@ static struct platform_device ux500_pcm = { | |||
| 209 | }, | 159 | }, |
| 210 | }; | 160 | }; |
| 211 | 161 | ||
| 212 | static struct msp_i2s_platform_data msp2_platform_data = { | 162 | struct msp_i2s_platform_data msp2_platform_data = { |
| 213 | .id = MSP_I2S_2, | 163 | .id = MSP_I2S_2, |
| 214 | .msp_i2s_dma_rx = &msp2_dma_rx, | 164 | .msp_i2s_dma_rx = &msp2_dma_rx, |
| 215 | .msp_i2s_dma_tx = &msp2_dma_tx, | 165 | .msp_i2s_dma_tx = &msp2_dma_tx, |
| 216 | }; | 166 | }; |
| 217 | 167 | ||
| 218 | static struct msp_i2s_platform_data msp3_platform_data = { | 168 | struct msp_i2s_platform_data msp3_platform_data = { |
| 219 | .id = MSP_I2S_3, | 169 | .id = MSP_I2S_3, |
| 220 | .msp_i2s_dma_rx = &msp1_dma_rx, | 170 | .msp_i2s_dma_rx = &msp1_dma_rx, |
| 221 | .msp_i2s_dma_tx = NULL, | 171 | .msp_i2s_dma_tx = NULL, |
| 222 | .msp_i2s_init = msp13_i2s_init, | ||
| 223 | .msp_i2s_exit = msp13_i2s_exit, | ||
| 224 | }; | 172 | }; |
| 225 | 173 | ||
| 226 | int mop500_msp_init(struct device *parent) | 174 | void mop500_audio_init(struct device *parent) |
| 227 | { | 175 | { |
| 228 | struct platform_device *msp1; | ||
| 229 | |||
| 230 | pr_info("%s: Register platform-device 'snd-soc-mop500'.\n", __func__); | 176 | pr_info("%s: Register platform-device 'snd-soc-mop500'.\n", __func__); |
| 231 | platform_device_register(&snd_soc_mop500); | 177 | platform_device_register(&snd_soc_mop500); |
| 232 | 178 | ||
| 233 | pr_info("Initialize MSP I2S-devices.\n"); | 179 | pr_info("Initialize MSP I2S-devices.\n"); |
| 234 | db8500_add_msp_i2s(parent, 0, U8500_MSP0_BASE, IRQ_DB8500_MSP0, | 180 | db8500_add_msp_i2s(parent, 0, U8500_MSP0_BASE, IRQ_DB8500_MSP0, |
| 235 | &msp0_platform_data); | 181 | &msp0_platform_data); |
| 236 | msp1 = db8500_add_msp_i2s(parent, 1, U8500_MSP1_BASE, IRQ_DB8500_MSP1, | 182 | db8500_add_msp_i2s(parent, 1, U8500_MSP1_BASE, IRQ_DB8500_MSP1, |
| 237 | &msp1_platform_data); | 183 | &msp1_platform_data); |
| 238 | db8500_add_msp_i2s(parent, 2, U8500_MSP2_BASE, IRQ_DB8500_MSP2, | 184 | db8500_add_msp_i2s(parent, 2, U8500_MSP2_BASE, IRQ_DB8500_MSP2, |
| 239 | &msp2_platform_data); | 185 | &msp2_platform_data); |
| 240 | db8500_add_msp_i2s(parent, 3, U8500_MSP3_BASE, IRQ_DB8500_MSP1, | 186 | db8500_add_msp_i2s(parent, 3, U8500_MSP3_BASE, IRQ_DB8500_MSP1, |
| 241 | &msp3_platform_data); | 187 | &msp3_platform_data); |
| 188 | } | ||
| 242 | 189 | ||
| 243 | /* Get the pinctrl handle for MSP1 */ | 190 | /* Due for removal once the MSP driver has been fully DT:ed. */ |
| 244 | if (msp1) { | 191 | void mop500_of_audio_init(struct device *parent) |
| 245 | msp1_p = pinctrl_get(&msp1->dev); | 192 | { |
| 246 | if (IS_ERR(msp1_p)) | ||
| 247 | dev_err(&msp1->dev, "could not get MSP1 pinctrl\n"); | ||
| 248 | else { | ||
| 249 | msp1_def = pinctrl_lookup_state(msp1_p, | ||
| 250 | PINCTRL_STATE_DEFAULT); | ||
| 251 | if (IS_ERR(msp1_def)) { | ||
| 252 | dev_err(&msp1->dev, | ||
| 253 | "could not get MSP1 defstate\n"); | ||
| 254 | } | ||
| 255 | msp1_sleep = pinctrl_lookup_state(msp1_p, | ||
| 256 | PINCTRL_STATE_SLEEP); | ||
| 257 | if (IS_ERR(msp1_sleep)) | ||
| 258 | dev_err(&msp1->dev, | ||
| 259 | "could not get MSP1 idlestate\n"); | ||
| 260 | } | ||
| 261 | } | ||
| 262 | |||
| 263 | pr_info("%s: Register platform-device 'ux500-pcm'\n", __func__); | 193 | pr_info("%s: Register platform-device 'ux500-pcm'\n", __func__); |
| 264 | platform_device_register(&ux500_pcm); | 194 | platform_device_register(&ux500_pcm); |
| 265 | |||
| 266 | return 0; | ||
| 267 | } | 195 | } |
diff --git a/arch/arm/mach-ux500/board-mop500-msp.h b/arch/arm/mach-ux500/board-mop500-msp.h deleted file mode 100644 index 6fcfb5e2cc94..000000000000 --- a/arch/arm/mach-ux500/board-mop500-msp.h +++ /dev/null | |||
| @@ -1,14 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) ST-Ericsson SA 2012 | ||
| 3 | * | ||
| 4 | * Author: Ola Lilja <ola.o.lilja@stericsson.com>, | ||
| 5 | * for ST-Ericsson. | ||
| 6 | * | ||
| 7 | * License terms: | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as published | ||
| 11 | * by the Free Software Foundation. | ||
| 12 | */ | ||
| 13 | |||
| 14 | void mop500_msp_init(struct device *parent); | ||
diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c index 18ff781cfbe4..9c8e4a9e83ee 100644 --- a/arch/arm/mach-ux500/board-mop500-sdi.c +++ b/arch/arm/mach-ux500/board-mop500-sdi.c | |||
| @@ -152,7 +152,7 @@ static struct stedma40_chan_cfg sdi1_dma_cfg_tx = { | |||
| 152 | }; | 152 | }; |
| 153 | #endif | 153 | #endif |
| 154 | 154 | ||
| 155 | static struct mmci_platform_data mop500_sdi1_data = { | 155 | struct mmci_platform_data mop500_sdi1_data = { |
| 156 | .ocr_mask = MMC_VDD_29_30, | 156 | .ocr_mask = MMC_VDD_29_30, |
| 157 | .f_max = 50000000, | 157 | .f_max = 50000000, |
| 158 | .capabilities = MMC_CAP_4_BIT_DATA, | 158 | .capabilities = MMC_CAP_4_BIT_DATA, |
| @@ -189,7 +189,7 @@ static struct stedma40_chan_cfg mop500_sdi2_dma_cfg_tx = { | |||
| 189 | }; | 189 | }; |
| 190 | #endif | 190 | #endif |
| 191 | 191 | ||
| 192 | static struct mmci_platform_data mop500_sdi2_data = { | 192 | struct mmci_platform_data mop500_sdi2_data = { |
| 193 | .ocr_mask = MMC_VDD_165_195, | 193 | .ocr_mask = MMC_VDD_165_195, |
| 194 | .f_max = 50000000, | 194 | .f_max = 50000000, |
| 195 | .capabilities = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA | | 195 | .capabilities = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA | |
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c index a534d8880de1..12ab21d5511f 100644 --- a/arch/arm/mach-ux500/board-mop500.c +++ b/arch/arm/mach-ux500/board-mop500.c | |||
| @@ -54,7 +54,6 @@ | |||
| 54 | #include "devices-db8500.h" | 54 | #include "devices-db8500.h" |
| 55 | #include "board-mop500.h" | 55 | #include "board-mop500.h" |
| 56 | #include "board-mop500-regulators.h" | 56 | #include "board-mop500-regulators.h" |
| 57 | #include "board-mop500-msp.h" | ||
| 58 | 57 | ||
| 59 | static struct gpio_led snowball_led_array[] = { | 58 | static struct gpio_led snowball_led_array[] = { |
| 60 | { | 59 | { |
| @@ -524,33 +523,12 @@ static struct stedma40_chan_cfg uart2_dma_cfg_tx = { | |||
| 524 | }; | 523 | }; |
| 525 | #endif | 524 | #endif |
| 526 | 525 | ||
| 527 | #define PRCC_K_SOFTRST_SET 0x18 | ||
| 528 | #define PRCC_K_SOFTRST_CLEAR 0x1C | ||
| 529 | static void ux500_uart0_reset(void) | ||
| 530 | { | ||
| 531 | void __iomem *prcc_rst_set, *prcc_rst_clr; | ||
| 532 | |||
| 533 | prcc_rst_set = (void __iomem *)IO_ADDRESS(U8500_CLKRST1_BASE + | ||
| 534 | PRCC_K_SOFTRST_SET); | ||
| 535 | prcc_rst_clr = (void __iomem *)IO_ADDRESS(U8500_CLKRST1_BASE + | ||
| 536 | PRCC_K_SOFTRST_CLEAR); | ||
| 537 | |||
| 538 | /* Activate soft reset PRCC_K_SOFTRST_CLEAR */ | ||
| 539 | writel((readl(prcc_rst_clr) | 0x1), prcc_rst_clr); | ||
| 540 | udelay(1); | ||
| 541 | |||
| 542 | /* Release soft reset PRCC_K_SOFTRST_SET */ | ||
| 543 | writel((readl(prcc_rst_set) | 0x1), prcc_rst_set); | ||
| 544 | udelay(1); | ||
| 545 | } | ||
| 546 | |||
| 547 | static struct amba_pl011_data uart0_plat = { | 526 | static struct amba_pl011_data uart0_plat = { |
| 548 | #ifdef CONFIG_STE_DMA40 | 527 | #ifdef CONFIG_STE_DMA40 |
| 549 | .dma_filter = stedma40_filter, | 528 | .dma_filter = stedma40_filter, |
| 550 | .dma_rx_param = &uart0_dma_cfg_rx, | 529 | .dma_rx_param = &uart0_dma_cfg_rx, |
| 551 | .dma_tx_param = &uart0_dma_cfg_tx, | 530 | .dma_tx_param = &uart0_dma_cfg_tx, |
| 552 | #endif | 531 | #endif |
| 553 | .reset = ux500_uart0_reset, | ||
| 554 | }; | 532 | }; |
| 555 | 533 | ||
| 556 | static struct amba_pl011_data uart1_plat = { | 534 | static struct amba_pl011_data uart1_plat = { |
| @@ -608,7 +586,7 @@ static void __init mop500_init_machine(void) | |||
| 608 | mop500_i2c_init(parent); | 586 | mop500_i2c_init(parent); |
| 609 | mop500_sdi_init(parent); | 587 | mop500_sdi_init(parent); |
| 610 | mop500_spi_init(parent); | 588 | mop500_spi_init(parent); |
| 611 | mop500_msp_init(parent); | 589 | mop500_audio_init(parent); |
| 612 | mop500_uart_init(parent); | 590 | mop500_uart_init(parent); |
| 613 | 591 | ||
| 614 | u8500_cryp1_hash1_init(parent); | 592 | u8500_cryp1_hash1_init(parent); |
| @@ -642,7 +620,7 @@ static void __init snowball_init_machine(void) | |||
| 642 | mop500_i2c_init(parent); | 620 | mop500_i2c_init(parent); |
| 643 | snowball_sdi_init(parent); | 621 | snowball_sdi_init(parent); |
| 644 | mop500_spi_init(parent); | 622 | mop500_spi_init(parent); |
| 645 | mop500_msp_init(parent); | 623 | mop500_audio_init(parent); |
| 646 | mop500_uart_init(parent); | 624 | mop500_uart_init(parent); |
| 647 | 625 | ||
| 648 | /* This board has full regulator constraints */ | 626 | /* This board has full regulator constraints */ |
| @@ -674,7 +652,7 @@ static void __init hrefv60_init_machine(void) | |||
| 674 | mop500_i2c_init(parent); | 652 | mop500_i2c_init(parent); |
| 675 | hrefv60_sdi_init(parent); | 653 | hrefv60_sdi_init(parent); |
| 676 | mop500_spi_init(parent); | 654 | mop500_spi_init(parent); |
| 677 | mop500_msp_init(parent); | 655 | mop500_audio_init(parent); |
| 678 | mop500_uart_init(parent); | 656 | mop500_uart_init(parent); |
| 679 | 657 | ||
| 680 | i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices); | 658 | i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices); |
| @@ -726,12 +704,9 @@ MACHINE_END | |||
| 726 | 704 | ||
| 727 | #ifdef CONFIG_MACH_UX500_DT | 705 | #ifdef CONFIG_MACH_UX500_DT |
| 728 | 706 | ||
| 729 | static struct platform_device *snowball_of_platform_devs[] __initdata = { | ||
| 730 | &snowball_led_dev, | ||
| 731 | &snowball_key_dev, | ||
| 732 | }; | ||
| 733 | |||
| 734 | struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = { | 707 | struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = { |
| 708 | /* Requires call-back bindings. */ | ||
| 709 | OF_DEV_AUXDATA("arm,cortex-a9-pmu", 0, "arm-pmu", &db8500_pmu_platdata), | ||
| 735 | /* Requires DMA and call-back bindings. */ | 710 | /* Requires DMA and call-back bindings. */ |
| 736 | OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", &uart0_plat), | 711 | OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", &uart0_plat), |
| 737 | OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", &uart1_plat), | 712 | OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", &uart1_plat), |
| @@ -739,6 +714,8 @@ struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = { | |||
| 739 | /* Requires DMA bindings. */ | 714 | /* Requires DMA bindings. */ |
| 740 | OF_DEV_AUXDATA("arm,pl022", 0x80002000, "ssp0", &ssp0_plat), | 715 | OF_DEV_AUXDATA("arm,pl022", 0x80002000, "ssp0", &ssp0_plat), |
| 741 | OF_DEV_AUXDATA("arm,pl18x", 0x80126000, "sdi0", &mop500_sdi0_data), | 716 | OF_DEV_AUXDATA("arm,pl18x", 0x80126000, "sdi0", &mop500_sdi0_data), |
| 717 | OF_DEV_AUXDATA("arm,pl18x", 0x80118000, "sdi1", &mop500_sdi1_data), | ||
| 718 | OF_DEV_AUXDATA("arm,pl18x", 0x80005000, "sdi2", &mop500_sdi2_data), | ||
| 742 | OF_DEV_AUXDATA("arm,pl18x", 0x80114000, "sdi4", &mop500_sdi4_data), | 719 | OF_DEV_AUXDATA("arm,pl18x", 0x80114000, "sdi4", &mop500_sdi4_data), |
| 743 | /* Requires clock name bindings. */ | 720 | /* Requires clock name bindings. */ |
| 744 | OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e000, "gpio.0", NULL), | 721 | OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e000, "gpio.0", NULL), |
| @@ -757,6 +734,15 @@ struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = { | |||
| 757 | OF_DEV_AUXDATA("st,nomadik-i2c", 0x8012a000, "nmk-i2c.4", NULL), | 734 | OF_DEV_AUXDATA("st,nomadik-i2c", 0x8012a000, "nmk-i2c.4", NULL), |
| 758 | /* Requires device name bindings. */ | 735 | /* Requires device name bindings. */ |
| 759 | OF_DEV_AUXDATA("stericsson,nmk_pinctrl", 0, "pinctrl-db8500", NULL), | 736 | OF_DEV_AUXDATA("stericsson,nmk_pinctrl", 0, "pinctrl-db8500", NULL), |
| 737 | /* Requires clock name and DMA bindings. */ | ||
| 738 | OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80123000, | ||
| 739 | "ux500-msp-i2s.0", &msp0_platform_data), | ||
| 740 | OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80124000, | ||
| 741 | "ux500-msp-i2s.1", &msp1_platform_data), | ||
| 742 | OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80117000, | ||
| 743 | "ux500-msp-i2s.2", &msp2_platform_data), | ||
| 744 | OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80125000, | ||
| 745 | "ux500-msp-i2s.3", &msp3_platform_data), | ||
| 760 | {}, | 746 | {}, |
| 761 | }; | 747 | }; |
| 762 | 748 | ||
| @@ -797,7 +783,7 @@ static void __init u8500_init_machine(void) | |||
| 797 | ARRAY_SIZE(mop500_platform_devs)); | 783 | ARRAY_SIZE(mop500_platform_devs)); |
| 798 | 784 | ||
| 799 | mop500_sdi_init(parent); | 785 | mop500_sdi_init(parent); |
| 800 | mop500_msp_init(parent); | 786 | mop500_audio_init(parent); |
| 801 | i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices); | 787 | i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices); |
| 802 | i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs); | 788 | i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs); |
| 803 | i2c_register_board_info(2, mop500_i2c2_devices, | 789 | i2c_register_board_info(2, mop500_i2c2_devices, |
| @@ -806,7 +792,7 @@ static void __init u8500_init_machine(void) | |||
| 806 | mop500_uib_init(); | 792 | mop500_uib_init(); |
| 807 | 793 | ||
| 808 | } else if (of_machine_is_compatible("calaosystems,snowball-a9500")) { | 794 | } else if (of_machine_is_compatible("calaosystems,snowball-a9500")) { |
| 809 | mop500_msp_init(parent); | 795 | mop500_of_audio_init(parent); |
| 810 | } else if (of_machine_is_compatible("st-ericsson,hrefv60+")) { | 796 | } else if (of_machine_is_compatible("st-ericsson,hrefv60+")) { |
| 811 | /* | 797 | /* |
| 812 | * The HREFv60 board removed a GPIO expander and routed | 798 | * The HREFv60 board removed a GPIO expander and routed |
| @@ -817,16 +803,6 @@ static void __init u8500_init_machine(void) | |||
| 817 | platform_add_devices(mop500_platform_devs, | 803 | platform_add_devices(mop500_platform_devs, |
| 818 | ARRAY_SIZE(mop500_platform_devs)); | 804 | ARRAY_SIZE(mop500_platform_devs)); |
| 819 | 805 | ||
| 820 | hrefv60_sdi_init(parent); | ||
| 821 | mop500_msp_init(parent); | ||
| 822 | |||
| 823 | i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices); | ||
| 824 | i2c0_devs -= NUM_PRE_V60_I2C0_DEVICES; | ||
| 825 | |||
| 826 | i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs); | ||
| 827 | i2c_register_board_info(2, mop500_i2c2_devices, | ||
| 828 | ARRAY_SIZE(mop500_i2c2_devices)); | ||
| 829 | |||
| 830 | mop500_uib_init(); | 806 | mop500_uib_init(); |
| 831 | } | 807 | } |
| 832 | 808 | ||
diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h index b5bfc1a78b1a..aca39a68712a 100644 --- a/arch/arm/mach-ux500/board-mop500.h +++ b/arch/arm/mach-ux500/board-mop500.h | |||
| @@ -9,6 +9,7 @@ | |||
| 9 | 9 | ||
| 10 | /* For NOMADIK_NR_GPIO */ | 10 | /* For NOMADIK_NR_GPIO */ |
| 11 | #include <mach/irqs.h> | 11 | #include <mach/irqs.h> |
| 12 | #include <mach/msp.h> | ||
| 12 | #include <linux/amba/mmci.h> | 13 | #include <linux/amba/mmci.h> |
| 13 | 14 | ||
| 14 | /* Snowball specific GPIO assignments, this board has no GPIO expander */ | 15 | /* Snowball specific GPIO assignments, this board has no GPIO expander */ |
| @@ -80,7 +81,14 @@ | |||
| 80 | struct device; | 81 | struct device; |
| 81 | struct i2c_board_info; | 82 | struct i2c_board_info; |
| 82 | extern struct mmci_platform_data mop500_sdi0_data; | 83 | extern struct mmci_platform_data mop500_sdi0_data; |
| 84 | extern struct mmci_platform_data mop500_sdi1_data; | ||
| 85 | extern struct mmci_platform_data mop500_sdi2_data; | ||
| 83 | extern struct mmci_platform_data mop500_sdi4_data; | 86 | extern struct mmci_platform_data mop500_sdi4_data; |
| 87 | extern struct msp_i2s_platform_data msp0_platform_data; | ||
| 88 | extern struct msp_i2s_platform_data msp1_platform_data; | ||
| 89 | extern struct msp_i2s_platform_data msp2_platform_data; | ||
| 90 | extern struct msp_i2s_platform_data msp3_platform_data; | ||
| 91 | extern struct arm_pmu_platdata db8500_pmu_platdata; | ||
| 84 | 92 | ||
| 85 | extern void mop500_sdi_init(struct device *parent); | 93 | extern void mop500_sdi_init(struct device *parent); |
| 86 | extern void snowball_sdi_init(struct device *parent); | 94 | extern void snowball_sdi_init(struct device *parent); |
| @@ -91,6 +99,9 @@ void __init mop500_stuib_init(void); | |||
| 91 | void __init mop500_pinmaps_init(void); | 99 | void __init mop500_pinmaps_init(void); |
| 92 | void __init snowball_pinmaps_init(void); | 100 | void __init snowball_pinmaps_init(void); |
| 93 | void __init hrefv60_pinmaps_init(void); | 101 | void __init hrefv60_pinmaps_init(void); |
| 102 | void mop500_audio_init(struct device *parent); | ||
| 103 | /* Due for removal once the MSP driver has been fully DT:ed. */ | ||
| 104 | void mop500_of_audio_init(struct device *parent); | ||
| 94 | 105 | ||
| 95 | int __init mop500_uib_init(void); | 106 | int __init mop500_uib_init(void); |
| 96 | void mop500_uib_i2c_add(int busnum, struct i2c_board_info *info, | 107 | void mop500_uib_i2c_add(int busnum, struct i2c_board_info *info, |
diff --git a/arch/arm/mach-ux500/clock.c b/arch/arm/mach-ux500/clock.c deleted file mode 100644 index 8d73b066a18d..000000000000 --- a/arch/arm/mach-ux500/clock.c +++ /dev/null | |||
| @@ -1,715 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2009 ST-Ericsson | ||
| 3 | * Copyright (C) 2009 STMicroelectronics | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify | ||
| 6 | * it under the terms of the GNU General Public License version 2 as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | */ | ||
| 9 | #include <linux/module.h> | ||
| 10 | #include <linux/kernel.h> | ||
| 11 | #include <linux/list.h> | ||
| 12 | #include <linux/errno.h> | ||
| 13 | #include <linux/err.h> | ||
| 14 | #include <linux/clk.h> | ||
| 15 | #include <linux/io.h> | ||
| 16 | #include <linux/clkdev.h> | ||
| 17 | #include <linux/cpufreq.h> | ||
| 18 | |||
| 19 | #include <plat/mtu.h> | ||
| 20 | #include <mach/hardware.h> | ||
| 21 | #include "clock.h" | ||
| 22 | |||
| 23 | #ifdef CONFIG_DEBUG_FS | ||
| 24 | #include <linux/debugfs.h> | ||
| 25 | #include <linux/uaccess.h> /* for copy_from_user */ | ||
| 26 | static LIST_HEAD(clk_list); | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #define PRCC_PCKEN 0x00 | ||
| 30 | #define PRCC_PCKDIS 0x04 | ||
| 31 | #define PRCC_KCKEN 0x08 | ||
| 32 | #define PRCC_KCKDIS 0x0C | ||
| 33 | |||
| 34 | #define PRCM_YYCLKEN0_MGT_SET 0x510 | ||
| 35 | #define PRCM_YYCLKEN1_MGT_SET 0x514 | ||
| 36 | #define PRCM_YYCLKEN0_MGT_CLR 0x518 | ||
| 37 | #define PRCM_YYCLKEN1_MGT_CLR 0x51C | ||
| 38 | #define PRCM_YYCLKEN0_MGT_VAL 0x520 | ||
| 39 | #define PRCM_YYCLKEN1_MGT_VAL 0x524 | ||
| 40 | |||
| 41 | #define PRCM_SVAMMDSPCLK_MGT 0x008 | ||
| 42 | #define PRCM_SIAMMDSPCLK_MGT 0x00C | ||
| 43 | #define PRCM_SGACLK_MGT 0x014 | ||
| 44 | #define PRCM_UARTCLK_MGT 0x018 | ||
| 45 | #define PRCM_MSP02CLK_MGT 0x01C | ||
| 46 | #define PRCM_MSP1CLK_MGT 0x288 | ||
| 47 | #define PRCM_I2CCLK_MGT 0x020 | ||
| 48 | #define PRCM_SDMMCCLK_MGT 0x024 | ||
| 49 | #define PRCM_SLIMCLK_MGT 0x028 | ||
| 50 | #define PRCM_PER1CLK_MGT 0x02C | ||
| 51 | #define PRCM_PER2CLK_MGT 0x030 | ||
| 52 | #define PRCM_PER3CLK_MGT 0x034 | ||
| 53 | #define PRCM_PER5CLK_MGT 0x038 | ||
| 54 | #define PRCM_PER6CLK_MGT 0x03C | ||
| 55 | #define PRCM_PER7CLK_MGT 0x040 | ||
| 56 | #define PRCM_LCDCLK_MGT 0x044 | ||
| 57 | #define PRCM_BMLCLK_MGT 0x04C | ||
| 58 | #define PRCM_HSITXCLK_MGT 0x050 | ||
| 59 | #define PRCM_HSIRXCLK_MGT 0x054 | ||
| 60 | #define PRCM_HDMICLK_MGT 0x058 | ||
| 61 | #define PRCM_APEATCLK_MGT 0x05C | ||
| 62 | #define PRCM_APETRACECLK_MGT 0x060 | ||
| 63 | #define PRCM_MCDECLK_MGT 0x064 | ||
| 64 | #define PRCM_IPI2CCLK_MGT 0x068 | ||
| 65 | #define PRCM_DSIALTCLK_MGT 0x06C | ||
| 66 | #define PRCM_DMACLK_MGT 0x074 | ||
| 67 | #define PRCM_B2R2CLK_MGT 0x078 | ||
| 68 | #define PRCM_TVCLK_MGT 0x07C | ||
| 69 | #define PRCM_TCR 0x1C8 | ||
| 70 | #define PRCM_TCR_STOPPED (1 << 16) | ||
| 71 | #define PRCM_TCR_DOZE_MODE (1 << 17) | ||
| 72 | #define PRCM_UNIPROCLK_MGT 0x278 | ||
| 73 | #define PRCM_SSPCLK_MGT 0x280 | ||
| 74 | #define PRCM_RNGCLK_MGT 0x284 | ||
| 75 | #define PRCM_UICCCLK_MGT 0x27C | ||
| 76 | |||
| 77 | #define PRCM_MGT_ENABLE (1 << 8) | ||
| 78 | |||
| 79 | static DEFINE_SPINLOCK(clocks_lock); | ||
| 80 | |||
| 81 | static void __clk_enable(struct clk *clk) | ||
| 82 | { | ||
| 83 | if (clk->enabled++ == 0) { | ||
| 84 | if (clk->parent_cluster) | ||
| 85 | __clk_enable(clk->parent_cluster); | ||
| 86 | |||
| 87 | if (clk->parent_periph) | ||
| 88 | __clk_enable(clk->parent_periph); | ||
| 89 | |||
| 90 | if (clk->ops && clk->ops->enable) | ||
| 91 | clk->ops->enable(clk); | ||
| 92 | } | ||
| 93 | } | ||
| 94 | |||
| 95 | int clk_enable(struct clk *clk) | ||
| 96 | { | ||
| 97 | unsigned long flags; | ||
| 98 | |||
| 99 | spin_lock_irqsave(&clocks_lock, flags); | ||
| 100 | __clk_enable(clk); | ||
| 101 | spin_unlock_irqrestore(&clocks_lock, flags); | ||
| 102 | |||
| 103 | return 0; | ||
| 104 | } | ||
| 105 | EXPORT_SYMBOL(clk_enable); | ||
| 106 | |||
| 107 | static void __clk_disable(struct clk *clk) | ||
| 108 | { | ||
| 109 | if (--clk->enabled == 0) { | ||
| 110 | if (clk->ops && clk->ops->disable) | ||
| 111 | clk->ops->disable(clk); | ||
| 112 | |||
| 113 | if (clk->parent_periph) | ||
| 114 | __clk_disable(clk->parent_periph); | ||
| 115 | |||
| 116 | if (clk->parent_cluster) | ||
| 117 | __clk_disable(clk->parent_cluster); | ||
| 118 | } | ||
| 119 | } | ||
| 120 | |||
| 121 | void clk_disable(struct clk *clk) | ||
| 122 | { | ||
| 123 | unsigned long flags; | ||
| 124 | |||
| 125 | WARN_ON(!clk->enabled); | ||
| 126 | |||
| 127 | spin_lock_irqsave(&clocks_lock, flags); | ||
| 128 | __clk_disable(clk); | ||
| 129 | spin_unlock_irqrestore(&clocks_lock, flags); | ||
| 130 | } | ||
| 131 | EXPORT_SYMBOL(clk_disable); | ||
| 132 | |||
| 133 | /* | ||
| 134 | * The MTU has a separate, rather complex muxing setup | ||
| 135 | * with alternative parents (peripheral cluster or | ||
| 136 | * ULP or fixed 32768 Hz) depending on settings | ||
| 137 | */ | ||
| 138 | static unsigned long clk_mtu_get_rate(struct clk *clk) | ||
| 139 | { | ||
| 140 | void __iomem *addr; | ||
| 141 | u32 tcr; | ||
| 142 | int mtu = (int) clk->data; | ||
| 143 | /* | ||
| 144 | * One of these is selected eventually | ||
| 145 | * TODO: Replace the constant with a reference | ||
| 146 | * to the ULP source once this is modeled. | ||
| 147 | */ | ||
| 148 | unsigned long clk32k = 32768; | ||
| 149 | unsigned long mturate; | ||
| 150 | unsigned long retclk; | ||
| 151 | |||
| 152 | if (cpu_is_u8500_family()) | ||
| 153 | addr = __io_address(U8500_PRCMU_BASE); | ||
| 154 | else | ||
| 155 | ux500_unknown_soc(); | ||
| 156 | |||
| 157 | /* | ||
| 158 | * On a startup, always conifgure the TCR to the doze mode; | ||
| 159 | * bootloaders do it for us. Do this in the kernel too. | ||
| 160 | */ | ||
| 161 | writel(PRCM_TCR_DOZE_MODE, addr + PRCM_TCR); | ||
| 162 | |||
| 163 | tcr = readl(addr + PRCM_TCR); | ||
| 164 | |||
| 165 | /* Get the rate from the parent as a default */ | ||
| 166 | if (clk->parent_periph) | ||
| 167 | mturate = clk_get_rate(clk->parent_periph); | ||
| 168 | else if (clk->parent_cluster) | ||
| 169 | mturate = clk_get_rate(clk->parent_cluster); | ||
| 170 | else | ||
| 171 | /* We need to be connected SOMEWHERE */ | ||
| 172 | BUG(); | ||
| 173 | |||
| 174 | /* Return the clock selected for this MTU */ | ||
| 175 | if (tcr & (1 << mtu)) | ||
| 176 | retclk = clk32k; | ||
| 177 | else | ||
| 178 | retclk = mturate; | ||
| 179 | |||
| 180 | pr_info("MTU%d clock rate: %lu Hz\n", mtu, retclk); | ||
| 181 | return retclk; | ||
| 182 | } | ||
| 183 | |||
| 184 | unsigned long clk_get_rate(struct clk *clk) | ||
| 185 | { | ||
| 186 | unsigned long rate; | ||
| 187 | |||
| 188 | /* | ||
| 189 | * If there is a custom getrate callback for this clock, | ||
| 190 | * it will take precedence. | ||
| 191 | */ | ||
| 192 | if (clk->get_rate) | ||
| 193 | return clk->get_rate(clk); | ||
| 194 | |||
| 195 | if (clk->ops && clk->ops->get_rate) | ||
| 196 | return clk->ops->get_rate(clk); | ||
| 197 | |||
| 198 | rate = clk->rate; | ||
| 199 | if (!rate) { | ||
| 200 | if (clk->parent_periph) | ||
| 201 | rate = clk_get_rate(clk->parent_periph); | ||
| 202 | else if (clk->parent_cluster) | ||
| 203 | rate = clk_get_rate(clk->parent_cluster); | ||
| 204 | } | ||
| 205 | |||
| 206 | return rate; | ||
| 207 | } | ||
| 208 | EXPORT_SYMBOL(clk_get_rate); | ||
| 209 | |||
| 210 | long clk_round_rate(struct clk *clk, unsigned long rate) | ||
| 211 | { | ||
| 212 | /*TODO*/ | ||
| 213 | return rate; | ||
| 214 | } | ||
| 215 | EXPORT_SYMBOL(clk_round_rate); | ||
| 216 | |||
| 217 | int clk_set_rate(struct clk *clk, unsigned long rate) | ||
| 218 | { | ||
| 219 | clk->rate = rate; | ||
| 220 | return 0; | ||
| 221 | } | ||
| 222 | EXPORT_SYMBOL(clk_set_rate); | ||
| 223 | |||
| 224 | int clk_set_parent(struct clk *clk, struct clk *parent) | ||
| 225 | { | ||
| 226 | /*TODO*/ | ||
| 227 | return -ENOSYS; | ||
| 228 | } | ||
| 229 | EXPORT_SYMBOL(clk_set_parent); | ||
| 230 | |||
| 231 | static void clk_prcmu_enable(struct clk *clk) | ||
| 232 | { | ||
| 233 | void __iomem *cg_set_reg = __io_address(U8500_PRCMU_BASE) | ||
| 234 | + PRCM_YYCLKEN0_MGT_SET + clk->prcmu_cg_off; | ||
| 235 | |||
| 236 | writel(1 << clk->prcmu_cg_bit, cg_set_reg); | ||
| 237 | } | ||
| 238 | |||
| 239 | static void clk_prcmu_disable(struct clk *clk) | ||
| 240 | { | ||
| 241 | void __iomem *cg_clr_reg = __io_address(U8500_PRCMU_BASE) | ||
| 242 | + PRCM_YYCLKEN0_MGT_CLR + clk->prcmu_cg_off; | ||
| 243 | |||
| 244 | writel(1 << clk->prcmu_cg_bit, cg_clr_reg); | ||
| 245 | } | ||
| 246 | |||
| 247 | static struct clkops clk_prcmu_ops = { | ||
| 248 | .enable = clk_prcmu_enable, | ||
| 249 | .disable = clk_prcmu_disable, | ||
| 250 | }; | ||
| 251 | |||
| 252 | static unsigned int clkrst_base[] = { | ||
| 253 | [1] = U8500_CLKRST1_BASE, | ||
| 254 | [2] = U8500_CLKRST2_BASE, | ||
| 255 | [3] = U8500_CLKRST3_BASE, | ||
| 256 | [5] = U8500_CLKRST5_BASE, | ||
| 257 | [6] = U8500_CLKRST6_BASE, | ||
| 258 | }; | ||
| 259 | |||
| 260 | static void clk_prcc_enable(struct clk *clk) | ||
| 261 | { | ||
| 262 | void __iomem *addr = __io_address(clkrst_base[clk->cluster]); | ||
| 263 | |||
| 264 | if (clk->prcc_kernel != -1) | ||
| 265 | writel(1 << clk->prcc_kernel, addr + PRCC_KCKEN); | ||
| 266 | |||
| 267 | if (clk->prcc_bus != -1) | ||
| 268 | writel(1 << clk->prcc_bus, addr + PRCC_PCKEN); | ||
| 269 | } | ||
| 270 | |||
| 271 | static void clk_prcc_disable(struct clk *clk) | ||
| 272 | { | ||
| 273 | void __iomem *addr = __io_address(clkrst_base[clk->cluster]); | ||
| 274 | |||
| 275 | if (clk->prcc_bus != -1) | ||
| 276 | writel(1 << clk->prcc_bus, addr + PRCC_PCKDIS); | ||
| 277 | |||
| 278 | if (clk->prcc_kernel != -1) | ||
| 279 | writel(1 << clk->prcc_kernel, addr + PRCC_KCKDIS); | ||
| 280 | } | ||
| 281 | |||
| 282 | static struct clkops clk_prcc_ops = { | ||
| 283 | .enable = clk_prcc_enable, | ||
| 284 | .disable = clk_prcc_disable, | ||
| 285 | }; | ||
| 286 | |||
| 287 | static struct clk clk_32khz = { | ||
| 288 | .name = "clk_32khz", | ||
| 289 | .rate = 32000, | ||
| 290 | }; | ||
| 291 | |||
| 292 | /* | ||
| 293 | * PRCMU level clock gating | ||
| 294 | */ | ||
| 295 | |||
| 296 | /* Bank 0 */ | ||
| 297 | static DEFINE_PRCMU_CLK(svaclk, 0x0, 2, SVAMMDSPCLK); | ||
| 298 | static DEFINE_PRCMU_CLK(siaclk, 0x0, 3, SIAMMDSPCLK); | ||
| 299 | static DEFINE_PRCMU_CLK(sgaclk, 0x0, 4, SGACLK); | ||
| 300 | static DEFINE_PRCMU_CLK_RATE(uartclk, 0x0, 5, UARTCLK, 38400000); | ||
| 301 | static DEFINE_PRCMU_CLK(msp02clk, 0x0, 6, MSP02CLK); | ||
| 302 | static DEFINE_PRCMU_CLK(msp1clk, 0x0, 7, MSP1CLK); /* v1 */ | ||
| 303 | static DEFINE_PRCMU_CLK_RATE(i2cclk, 0x0, 8, I2CCLK, 48000000); | ||
| 304 | static DEFINE_PRCMU_CLK_RATE(sdmmcclk, 0x0, 9, SDMMCCLK, 100000000); | ||
| 305 | static DEFINE_PRCMU_CLK(slimclk, 0x0, 10, SLIMCLK); | ||
| 306 | static DEFINE_PRCMU_CLK(per1clk, 0x0, 11, PER1CLK); | ||
| 307 | static DEFINE_PRCMU_CLK(per2clk, 0x0, 12, PER2CLK); | ||
| 308 | static DEFINE_PRCMU_CLK(per3clk, 0x0, 13, PER3CLK); | ||
| 309 | static DEFINE_PRCMU_CLK(per5clk, 0x0, 14, PER5CLK); | ||
| 310 | static DEFINE_PRCMU_CLK_RATE(per6clk, 0x0, 15, PER6CLK, 133330000); | ||
| 311 | static DEFINE_PRCMU_CLK(lcdclk, 0x0, 17, LCDCLK); | ||
| 312 | static DEFINE_PRCMU_CLK(bmlclk, 0x0, 18, BMLCLK); | ||
| 313 | static DEFINE_PRCMU_CLK(hsitxclk, 0x0, 19, HSITXCLK); | ||
| 314 | static DEFINE_PRCMU_CLK(hsirxclk, 0x0, 20, HSIRXCLK); | ||
| 315 | static DEFINE_PRCMU_CLK(hdmiclk, 0x0, 21, HDMICLK); | ||
| 316 | static DEFINE_PRCMU_CLK(apeatclk, 0x0, 22, APEATCLK); | ||
| 317 | static DEFINE_PRCMU_CLK(apetraceclk, 0x0, 23, APETRACECLK); | ||
| 318 | static DEFINE_PRCMU_CLK(mcdeclk, 0x0, 24, MCDECLK); | ||
| 319 | static DEFINE_PRCMU_CLK(ipi2clk, 0x0, 25, IPI2CCLK); | ||
| 320 | static DEFINE_PRCMU_CLK(dsialtclk, 0x0, 26, DSIALTCLK); /* v1 */ | ||
| 321 | static DEFINE_PRCMU_CLK(dmaclk, 0x0, 27, DMACLK); | ||
| 322 | static DEFINE_PRCMU_CLK(b2r2clk, 0x0, 28, B2R2CLK); | ||
| 323 | static DEFINE_PRCMU_CLK(tvclk, 0x0, 29, TVCLK); | ||
| 324 | static DEFINE_PRCMU_CLK(uniproclk, 0x0, 30, UNIPROCLK); /* v1 */ | ||
| 325 | static DEFINE_PRCMU_CLK_RATE(sspclk, 0x0, 31, SSPCLK, 48000000); /* v1 */ | ||
| 326 | |||
| 327 | /* Bank 1 */ | ||
| 328 | static DEFINE_PRCMU_CLK(rngclk, 0x4, 0, RNGCLK); /* v1 */ | ||
| 329 | static DEFINE_PRCMU_CLK(uiccclk, 0x4, 1, UICCCLK); /* v1 */ | ||
| 330 | |||
| 331 | /* | ||
| 332 | * PRCC level clock gating | ||
| 333 | * Format: per#, clk, PCKEN bit, KCKEN bit, parent | ||
| 334 | */ | ||
| 335 | |||
| 336 | /* Peripheral Cluster #1 */ | ||
| 337 | static DEFINE_PRCC_CLK(1, msp3, 11, 10, &clk_msp1clk); | ||
| 338 | static DEFINE_PRCC_CLK(1, i2c4, 10, 9, &clk_i2cclk); | ||
| 339 | static DEFINE_PRCC_CLK(1, gpio0, 9, -1, NULL); | ||
| 340 | static DEFINE_PRCC_CLK(1, slimbus0, 8, 8, &clk_slimclk); | ||
| 341 | static DEFINE_PRCC_CLK(1, spi3, 7, -1, NULL); | ||
| 342 | static DEFINE_PRCC_CLK(1, i2c2, 6, 6, &clk_i2cclk); | ||
| 343 | static DEFINE_PRCC_CLK(1, sdi0, 5, 5, &clk_sdmmcclk); | ||
| 344 | static DEFINE_PRCC_CLK(1, msp1, 4, 4, &clk_msp1clk); | ||
| 345 | static DEFINE_PRCC_CLK(1, msp0, 3, 3, &clk_msp02clk); | ||
| 346 | static DEFINE_PRCC_CLK(1, i2c1, 2, 2, &clk_i2cclk); | ||
| 347 | static DEFINE_PRCC_CLK(1, uart1, 1, 1, &clk_uartclk); | ||
| 348 | static DEFINE_PRCC_CLK(1, uart0, 0, 0, &clk_uartclk); | ||
| 349 | |||
| 350 | /* Peripheral Cluster #2 */ | ||
| 351 | static DEFINE_PRCC_CLK(2, gpio1, 11, -1, NULL); | ||
| 352 | static DEFINE_PRCC_CLK(2, ssitx, 10, 7, NULL); | ||
| 353 | static DEFINE_PRCC_CLK(2, ssirx, 9, 6, NULL); | ||
| 354 | static DEFINE_PRCC_CLK(2, spi0, 8, -1, NULL); | ||
| 355 | static DEFINE_PRCC_CLK(2, sdi3, 7, 5, &clk_sdmmcclk); | ||
| 356 | static DEFINE_PRCC_CLK(2, sdi1, 6, 4, &clk_sdmmcclk); | ||
| 357 | static DEFINE_PRCC_CLK(2, msp2, 5, 3, &clk_msp02clk); | ||
| 358 | static DEFINE_PRCC_CLK(2, sdi4, 4, 2, &clk_sdmmcclk); | ||
| 359 | static DEFINE_PRCC_CLK(2, pwl, 3, 1, NULL); | ||
| 360 | static DEFINE_PRCC_CLK(2, spi1, 2, -1, NULL); | ||
| 361 | static DEFINE_PRCC_CLK(2, spi2, 1, -1, NULL); | ||
| 362 | static DEFINE_PRCC_CLK(2, i2c3, 0, 0, &clk_i2cclk); | ||
| 363 | |||
| 364 | /* Peripheral Cluster #3 */ | ||
| 365 | static DEFINE_PRCC_CLK(3, gpio2, 8, -1, NULL); | ||
| 366 | static DEFINE_PRCC_CLK(3, sdi5, 7, 7, &clk_sdmmcclk); | ||
| 367 | static DEFINE_PRCC_CLK(3, uart2, 6, 6, &clk_uartclk); | ||
| 368 | static DEFINE_PRCC_CLK(3, ske, 5, 5, &clk_32khz); | ||
| 369 | static DEFINE_PRCC_CLK(3, sdi2, 4, 4, &clk_sdmmcclk); | ||
| 370 | static DEFINE_PRCC_CLK(3, i2c0, 3, 3, &clk_i2cclk); | ||
| 371 | static DEFINE_PRCC_CLK(3, ssp1, 2, 2, &clk_sspclk); | ||
| 372 | static DEFINE_PRCC_CLK(3, ssp0, 1, 1, &clk_sspclk); | ||
| 373 | static DEFINE_PRCC_CLK(3, fsmc, 0, -1, NULL); | ||
| 374 | |||
| 375 | /* Peripheral Cluster #4 is in the always on domain */ | ||
| 376 | |||
| 377 | /* Peripheral Cluster #5 */ | ||
| 378 | static DEFINE_PRCC_CLK(5, gpio3, 1, -1, NULL); | ||
| 379 | static DEFINE_PRCC_CLK(5, usb, 0, 0, NULL); | ||
| 380 | |||
| 381 | /* Peripheral Cluster #6 */ | ||
| 382 | |||
| 383 | /* MTU ID in data */ | ||
| 384 | static DEFINE_PRCC_CLK_CUSTOM(6, mtu1, 9, -1, NULL, clk_mtu_get_rate, 1); | ||
| 385 | static DEFINE_PRCC_CLK_CUSTOM(6, mtu0, 8, -1, NULL, clk_mtu_get_rate, 0); | ||
| 386 | static DEFINE_PRCC_CLK(6, cfgreg, 7, 7, NULL); | ||
| 387 | static DEFINE_PRCC_CLK(6, hash1, 6, -1, NULL); | ||
| 388 | static DEFINE_PRCC_CLK(6, unipro, 5, 1, &clk_uniproclk); | ||
| 389 | static DEFINE_PRCC_CLK(6, pka, 4, -1, NULL); | ||
| 390 | static DEFINE_PRCC_CLK(6, hash0, 3, -1, NULL); | ||
| 391 | static DEFINE_PRCC_CLK(6, cryp0, 2, -1, NULL); | ||
| 392 | static DEFINE_PRCC_CLK(6, cryp1, 1, -1, NULL); | ||
| 393 | static DEFINE_PRCC_CLK(6, rng, 0, 0, &clk_rngclk); | ||
| 394 | |||
| 395 | static struct clk clk_dummy_apb_pclk = { | ||
| 396 | .name = "apb_pclk", | ||
| 397 | }; | ||
| 398 | |||
| 399 | static struct clk_lookup u8500_clks[] = { | ||
| 400 | CLK(dummy_apb_pclk, NULL, "apb_pclk"), | ||
| 401 | |||
| 402 | /* Peripheral Cluster #1 */ | ||
| 403 | CLK(gpio0, "gpio.0", NULL), | ||
| 404 | CLK(gpio0, "gpio.1", NULL), | ||
| 405 | CLK(slimbus0, "slimbus0", NULL), | ||
| 406 | CLK(i2c2, "nmk-i2c.2", NULL), | ||
| 407 | CLK(sdi0, "sdi0", NULL), | ||
| 408 | CLK(msp0, "ux500-msp-i2s.0", NULL), | ||
| 409 | CLK(i2c1, "nmk-i2c.1", NULL), | ||
| 410 | CLK(uart1, "uart1", NULL), | ||
| 411 | CLK(uart0, "uart0", NULL), | ||
| 412 | |||
| 413 | /* Peripheral Cluster #3 */ | ||
| 414 | CLK(gpio2, "gpio.2", NULL), | ||
| 415 | CLK(gpio2, "gpio.3", NULL), | ||
| 416 | CLK(gpio2, "gpio.4", NULL), | ||
| 417 | CLK(gpio2, "gpio.5", NULL), | ||
| 418 | CLK(sdi5, "sdi5", NULL), | ||
| 419 | CLK(uart2, "uart2", NULL), | ||
| 420 | CLK(ske, "ske", NULL), | ||
| 421 | CLK(ske, "nmk-ske-keypad", NULL), | ||
| 422 | CLK(sdi2, "sdi2", NULL), | ||
| 423 | CLK(i2c0, "nmk-i2c.0", NULL), | ||
| 424 | CLK(fsmc, "fsmc", NULL), | ||
| 425 | |||
| 426 | /* Peripheral Cluster #5 */ | ||
| 427 | CLK(gpio3, "gpio.8", NULL), | ||
| 428 | |||
| 429 | /* Peripheral Cluster #6 */ | ||
| 430 | CLK(hash1, "hash1", NULL), | ||
| 431 | CLK(pka, "pka", NULL), | ||
| 432 | CLK(hash0, "hash0", NULL), | ||
| 433 | CLK(cryp0, "cryp0", NULL), | ||
| 434 | CLK(cryp1, "cryp1", NULL), | ||
| 435 | |||
| 436 | /* PRCMU level clock gating */ | ||
| 437 | |||
| 438 | /* Bank 0 */ | ||
| 439 | CLK(svaclk, "sva", NULL), | ||
| 440 | CLK(siaclk, "sia", NULL), | ||
| 441 | CLK(sgaclk, "sga", NULL), | ||
| 442 | CLK(slimclk, "slim", NULL), | ||
| 443 | CLK(lcdclk, "lcd", NULL), | ||
| 444 | CLK(bmlclk, "bml", NULL), | ||
| 445 | CLK(hsitxclk, "stm-hsi.0", NULL), | ||
| 446 | CLK(hsirxclk, "stm-hsi.1", NULL), | ||
| 447 | CLK(hdmiclk, "hdmi", NULL), | ||
| 448 | CLK(apeatclk, "apeat", NULL), | ||
| 449 | CLK(apetraceclk, "apetrace", NULL), | ||
| 450 | CLK(mcdeclk, "mcde", NULL), | ||
| 451 | CLK(ipi2clk, "ipi2", NULL), | ||
| 452 | CLK(dmaclk, "dma40.0", NULL), | ||
| 453 | CLK(b2r2clk, "b2r2", NULL), | ||
| 454 | CLK(tvclk, "tv", NULL), | ||
| 455 | |||
| 456 | /* Peripheral Cluster #1 */ | ||
| 457 | CLK(i2c4, "nmk-i2c.4", NULL), | ||
| 458 | CLK(spi3, "spi3", NULL), | ||
| 459 | CLK(msp1, "ux500-msp-i2s.1", NULL), | ||
| 460 | CLK(msp3, "ux500-msp-i2s.3", NULL), | ||
| 461 | |||
| 462 | /* Peripheral Cluster #2 */ | ||
| 463 | CLK(gpio1, "gpio.6", NULL), | ||
| 464 | CLK(gpio1, "gpio.7", NULL), | ||
| 465 | CLK(ssitx, "ssitx", NULL), | ||
| 466 | CLK(ssirx, "ssirx", NULL), | ||
| 467 | CLK(spi0, "spi0", NULL), | ||
| 468 | CLK(sdi3, "sdi3", NULL), | ||
| 469 | CLK(sdi1, "sdi1", NULL), | ||
| 470 | CLK(msp2, "ux500-msp-i2s.2", NULL), | ||
| 471 | CLK(sdi4, "sdi4", NULL), | ||
| 472 | CLK(pwl, "pwl", NULL), | ||
| 473 | CLK(spi1, "spi1", NULL), | ||
| 474 | CLK(spi2, "spi2", NULL), | ||
| 475 | CLK(i2c3, "nmk-i2c.3", NULL), | ||
| 476 | |||
| 477 | /* Peripheral Cluster #3 */ | ||
| 478 | CLK(ssp1, "ssp1", NULL), | ||
| 479 | CLK(ssp0, "ssp0", NULL), | ||
| 480 | |||
| 481 | /* Peripheral Cluster #5 */ | ||
| 482 | CLK(usb, "musb-ux500.0", "usb"), | ||
| 483 | |||
| 484 | /* Peripheral Cluster #6 */ | ||
| 485 | CLK(mtu1, "mtu1", NULL), | ||
| 486 | CLK(mtu0, "mtu0", NULL), | ||
| 487 | CLK(cfgreg, "cfgreg", NULL), | ||
| 488 | CLK(hash1, "hash1", NULL), | ||
| 489 | CLK(unipro, "unipro", NULL), | ||
| 490 | CLK(rng, "rng", NULL), | ||
| 491 | |||
| 492 | /* PRCMU level clock gating */ | ||
| 493 | |||
| 494 | /* Bank 0 */ | ||
| 495 | CLK(uniproclk, "uniproclk", NULL), | ||
| 496 | CLK(dsialtclk, "dsialt", NULL), | ||
| 497 | |||
| 498 | /* Bank 1 */ | ||
| 499 | CLK(rngclk, "rng", NULL), | ||
| 500 | CLK(uiccclk, "uicc", NULL), | ||
| 501 | }; | ||
| 502 | |||
| 503 | #ifdef CONFIG_DEBUG_FS | ||
| 504 | /* | ||
| 505 | * debugfs support to trace clock tree hierarchy and attributes with | ||
| 506 | * powerdebug | ||
| 507 | */ | ||
| 508 | static struct dentry *clk_debugfs_root; | ||
| 509 | |||
| 510 | void __init clk_debugfs_add_table(struct clk_lookup *cl, size_t num) | ||
| 511 | { | ||
| 512 | while (num--) { | ||
| 513 | /* Check that the clock has not been already registered */ | ||
| 514 | if (!(cl->clk->list.prev != cl->clk->list.next)) | ||
| 515 | list_add_tail(&cl->clk->list, &clk_list); | ||
| 516 | |||
| 517 | cl++; | ||
| 518 | } | ||
| 519 | } | ||
| 520 | |||
| 521 | static ssize_t usecount_dbg_read(struct file *file, char __user *buf, | ||
| 522 | size_t size, loff_t *off) | ||
| 523 | { | ||
| 524 | struct clk *clk = file->f_dentry->d_inode->i_private; | ||
| 525 | char cusecount[128]; | ||
| 526 | unsigned int len; | ||
| 527 | |||
| 528 | len = sprintf(cusecount, "%u\n", clk->enabled); | ||
| 529 | return simple_read_from_buffer(buf, size, off, cusecount, len); | ||
| 530 | } | ||
| 531 | |||
| 532 | static ssize_t rate_dbg_read(struct file *file, char __user *buf, | ||
| 533 | size_t size, loff_t *off) | ||
| 534 | { | ||
| 535 | struct clk *clk = file->f_dentry->d_inode->i_private; | ||
| 536 | char crate[128]; | ||
| 537 | unsigned int rate; | ||
| 538 | unsigned int len; | ||
| 539 | |||
| 540 | rate = clk_get_rate(clk); | ||
| 541 | len = sprintf(crate, "%u\n", rate); | ||
| 542 | return simple_read_from_buffer(buf, size, off, crate, len); | ||
| 543 | } | ||
| 544 | |||
| 545 | static const struct file_operations usecount_fops = { | ||
| 546 | .read = usecount_dbg_read, | ||
| 547 | }; | ||
| 548 | |||
| 549 | static const struct file_operations set_rate_fops = { | ||
| 550 | .read = rate_dbg_read, | ||
| 551 | }; | ||
| 552 | |||
| 553 | static struct dentry *clk_debugfs_register_dir(struct clk *c, | ||
| 554 | struct dentry *p_dentry) | ||
| 555 | { | ||
| 556 | struct dentry *d, *clk_d; | ||
| 557 | const char *p = c->name; | ||
| 558 | |||
| 559 | if (!p) | ||
| 560 | p = "BUG"; | ||
| 561 | |||
| 562 | clk_d = debugfs_create_dir(p, p_dentry); | ||
| 563 | if (!clk_d) | ||
| 564 | return NULL; | ||
| 565 | |||
| 566 | d = debugfs_create_file("usecount", S_IRUGO, | ||
| 567 | clk_d, c, &usecount_fops); | ||
| 568 | if (!d) | ||
| 569 | goto err_out; | ||
| 570 | d = debugfs_create_file("rate", S_IRUGO, | ||
| 571 | clk_d, c, &set_rate_fops); | ||
| 572 | if (!d) | ||
| 573 | goto err_out; | ||
| 574 | /* | ||
| 575 | * TODO : not currently available in ux500 | ||
| 576 | * d = debugfs_create_x32("flags", S_IRUGO, clk_d, (u32 *)&c->flags); | ||
| 577 | * if (!d) | ||
| 578 | * goto err_out; | ||
| 579 | */ | ||
| 580 | |||
| 581 | return clk_d; | ||
| 582 | |||
| 583 | err_out: | ||
| 584 | debugfs_remove_recursive(clk_d); | ||
| 585 | return NULL; | ||
| 586 | } | ||
| 587 | |||
| 588 | static int clk_debugfs_register_one(struct clk *c) | ||
| 589 | { | ||
| 590 | struct clk *pa = c->parent_periph; | ||
| 591 | struct clk *bpa = c->parent_cluster; | ||
| 592 | |||
| 593 | if (!(bpa && !pa)) { | ||
| 594 | c->dent = clk_debugfs_register_dir(c, | ||
| 595 | pa ? pa->dent : clk_debugfs_root); | ||
| 596 | if (!c->dent) | ||
| 597 | return -ENOMEM; | ||
| 598 | } | ||
| 599 | |||
| 600 | if (bpa) { | ||
| 601 | c->dent_bus = clk_debugfs_register_dir(c, | ||
| 602 | bpa->dent_bus ? bpa->dent_bus : bpa->dent); | ||
| 603 | if ((!c->dent_bus) && (c->dent)) { | ||
| 604 | debugfs_remove_recursive(c->dent); | ||
| 605 | c->dent = NULL; | ||
| 606 | return -ENOMEM; | ||
| 607 | } | ||
| 608 | } | ||
| 609 | return 0; | ||
| 610 | } | ||
| 611 | |||
| 612 | static int clk_debugfs_register(struct clk *c) | ||
| 613 | { | ||
| 614 | int err; | ||
| 615 | struct clk *pa = c->parent_periph; | ||
| 616 | struct clk *bpa = c->parent_cluster; | ||
| 617 | |||
| 618 | if (pa && (!pa->dent && !pa->dent_bus)) { | ||
| 619 | err = clk_debugfs_register(pa); | ||
| 620 | if (err) | ||
| 621 | return err; | ||
| 622 | } | ||
| 623 | |||
| 624 | if (bpa && (!bpa->dent && !bpa->dent_bus)) { | ||
| 625 | err = clk_debugfs_register(bpa); | ||
| 626 | if (err) | ||
| 627 | return err; | ||
| 628 | } | ||
| 629 | |||
| 630 | if ((!c->dent) && (!c->dent_bus)) { | ||
| 631 | err = clk_debugfs_register_one(c); | ||
| 632 | if (err) | ||
| 633 | return err; | ||
| 634 | } | ||
| 635 | return 0; | ||
| 636 | } | ||
| 637 | |||
| 638 | int __init clk_debugfs_init(void) | ||
| 639 | { | ||
| 640 | struct clk *c; | ||
| 641 | struct dentry *d; | ||
| 642 | int err; | ||
| 643 | |||
| 644 | d = debugfs_create_dir("clock", NULL); | ||
| 645 | if (!d) | ||
| 646 | return -ENOMEM; | ||
| 647 | clk_debugfs_root = d; | ||
| 648 | |||
| 649 | list_for_each_entry(c, &clk_list, list) { | ||
| 650 | err = clk_debugfs_register(c); | ||
| 651 | if (err) | ||
| 652 | goto err_out; | ||
| 653 | } | ||
| 654 | return 0; | ||
| 655 | err_out: | ||
| 656 | debugfs_remove_recursive(clk_debugfs_root); | ||
| 657 | return err; | ||
| 658 | } | ||
| 659 | |||
| 660 | #endif /* defined(CONFIG_DEBUG_FS) */ | ||
| 661 | |||
| 662 | unsigned long clk_smp_twd_rate = 500000000; | ||
| 663 | |||
| 664 | unsigned long clk_smp_twd_get_rate(struct clk *clk) | ||
| 665 | { | ||
| 666 | return clk_smp_twd_rate; | ||
| 667 | } | ||
| 668 | |||
| 669 | static struct clk clk_smp_twd = { | ||
| 670 | .get_rate = clk_smp_twd_get_rate, | ||
| 671 | .name = "smp_twd", | ||
| 672 | }; | ||
| 673 | |||
| 674 | static struct clk_lookup clk_smp_twd_lookup = { | ||
| 675 | .dev_id = "smp_twd", | ||
| 676 | .clk = &clk_smp_twd, | ||
| 677 | }; | ||
| 678 | |||
| 679 | #ifdef CONFIG_CPU_FREQ | ||
| 680 | |||
| 681 | static int clk_twd_cpufreq_transition(struct notifier_block *nb, | ||
| 682 | unsigned long state, void *data) | ||
| 683 | { | ||
| 684 | struct cpufreq_freqs *f = data; | ||
| 685 | |||
| 686 | if (state == CPUFREQ_PRECHANGE) { | ||
| 687 | /* Save frequency in simple Hz */ | ||
| 688 | clk_smp_twd_rate = (f->new * 1000) / 2; | ||
| 689 | } | ||
| 690 | |||
| 691 | return NOTIFY_OK; | ||
| 692 | } | ||
| 693 | |||
| 694 | static struct notifier_block clk_twd_cpufreq_nb = { | ||
| 695 | .notifier_call = clk_twd_cpufreq_transition, | ||
| 696 | }; | ||
| 697 | |||
| 698 | int clk_init_smp_twd_cpufreq(void) | ||
| 699 | { | ||
| 700 | return cpufreq_register_notifier(&clk_twd_cpufreq_nb, | ||
| 701 | CPUFREQ_TRANSITION_NOTIFIER); | ||
| 702 | } | ||
| 703 | |||
| 704 | #endif | ||
| 705 | |||
| 706 | int __init clk_init(void) | ||
| 707 | { | ||
| 708 | clkdev_add_table(u8500_clks, ARRAY_SIZE(u8500_clks)); | ||
| 709 | clkdev_add(&clk_smp_twd_lookup); | ||
| 710 | |||
| 711 | #ifdef CONFIG_DEBUG_FS | ||
| 712 | clk_debugfs_add_table(u8500_clks, ARRAY_SIZE(u8500_clks)); | ||
| 713 | #endif | ||
| 714 | return 0; | ||
| 715 | } | ||
diff --git a/arch/arm/mach-ux500/clock.h b/arch/arm/mach-ux500/clock.h deleted file mode 100644 index 65d27a13f46d..000000000000 --- a/arch/arm/mach-ux500/clock.h +++ /dev/null | |||
| @@ -1,164 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2010 ST-Ericsson | ||
| 3 | * Copyright (C) 2009 STMicroelectronics | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify | ||
| 6 | * it under the terms of the GNU General Public License version 2 as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | */ | ||
| 9 | |||
| 10 | /** | ||
| 11 | * struct clkops - ux500 clock operations | ||
| 12 | * @enable: function to enable the clock | ||
| 13 | * @disable: function to disable the clock | ||
| 14 | * @get_rate: function to get the current clock rate | ||
| 15 | * | ||
| 16 | * This structure contains function pointers to functions that will be used to | ||
| 17 | * control the clock. All of these functions are optional. If get_rate is | ||
| 18 | * NULL, the rate in the struct clk will be used. | ||
| 19 | */ | ||
| 20 | struct clkops { | ||
| 21 | void (*enable) (struct clk *); | ||
| 22 | void (*disable) (struct clk *); | ||
| 23 | unsigned long (*get_rate) (struct clk *); | ||
| 24 | int (*set_parent)(struct clk *, struct clk *); | ||
| 25 | }; | ||
| 26 | |||
| 27 | /** | ||
| 28 | * struct clk - ux500 clock structure | ||
| 29 | * @ops: pointer to clkops struct used to control this clock | ||
| 30 | * @name: name, for debugging | ||
| 31 | * @enabled: refcount. positive if enabled, zero if disabled | ||
| 32 | * @get_rate: custom callback for getting the clock rate | ||
| 33 | * @data: custom per-clock data for example for the get_rate | ||
| 34 | * callback | ||
| 35 | * @rate: fixed rate for clocks which don't implement | ||
| 36 | * ops->getrate | ||
| 37 | * @prcmu_cg_off: address offset of the combined enable/disable register | ||
| 38 | * (used on u8500v1) | ||
| 39 | * @prcmu_cg_bit: bit in the combined enable/disable register (used on | ||
| 40 | * u8500v1) | ||
| 41 | * @prcmu_cg_mgt: address of the enable/disable register (used on | ||
| 42 | * u8500ed) | ||
| 43 | * @cluster: peripheral cluster number | ||
| 44 | * @prcc_bus: bit for the bus clock in the peripheral's CLKRST | ||
| 45 | * @prcc_kernel: bit for the kernel clock in the peripheral's CLKRST. | ||
| 46 | * -1 if no kernel clock exists. | ||
| 47 | * @parent_cluster: pointer to parent's cluster clk struct | ||
| 48 | * @parent_periph: pointer to parent's peripheral clk struct | ||
| 49 | * | ||
| 50 | * Peripherals are organised into clusters, and each cluster has an associated | ||
| 51 | * bus clock. Some peripherals also have a parent peripheral clock. | ||
| 52 | * | ||
| 53 | * In order to enable a clock for a peripheral, we need to enable: | ||
| 54 | * (1) the parent cluster (bus) clock at the PRCMU level | ||
| 55 | * (2) the parent peripheral clock (if any) at the PRCMU level | ||
| 56 | * (3) the peripheral's bus & kernel clock at the PRCC level | ||
| 57 | * | ||
| 58 | * (1) and (2) are handled by defining clk structs (DEFINE_PRCMU_CLK) for each | ||
| 59 | * of the cluster and peripheral clocks, and hooking these as the parents of | ||
| 60 | * the individual peripheral clocks. | ||
| 61 | * | ||
| 62 | * (3) is handled by specifying the bits in the PRCC control registers required | ||
| 63 | * to enable these clocks and modifying them in the ->enable and | ||
| 64 | * ->disable callbacks of the peripheral clocks (DEFINE_PRCC_CLK). | ||
| 65 | * | ||
| 66 | * This structure describes both the PRCMU-level clocks and PRCC-level clocks. | ||
| 67 | * The prcmu_* fields are only used for the PRCMU clocks, and the cluster, | ||
| 68 | * prcc, and parent pointers are only used for the PRCC-level clocks. | ||
| 69 | */ | ||
| 70 | struct clk { | ||
| 71 | const struct clkops *ops; | ||
| 72 | const char *name; | ||
| 73 | unsigned int enabled; | ||
| 74 | unsigned long (*get_rate)(struct clk *); | ||
| 75 | void *data; | ||
| 76 | |||
| 77 | unsigned long rate; | ||
| 78 | struct list_head list; | ||
| 79 | |||
| 80 | /* These three are only for PRCMU clks */ | ||
| 81 | |||
| 82 | unsigned int prcmu_cg_off; | ||
| 83 | unsigned int prcmu_cg_bit; | ||
| 84 | unsigned int prcmu_cg_mgt; | ||
| 85 | |||
| 86 | /* The rest are only for PRCC clks */ | ||
| 87 | |||
| 88 | int cluster; | ||
| 89 | unsigned int prcc_bus; | ||
| 90 | unsigned int prcc_kernel; | ||
| 91 | |||
| 92 | struct clk *parent_cluster; | ||
| 93 | struct clk *parent_periph; | ||
| 94 | #if defined(CONFIG_DEBUG_FS) | ||
| 95 | struct dentry *dent; /* For visible tree hierarchy */ | ||
| 96 | struct dentry *dent_bus; /* For visible tree hierarchy */ | ||
| 97 | #endif | ||
| 98 | }; | ||
| 99 | |||
| 100 | #define DEFINE_PRCMU_CLK(_name, _cg_off, _cg_bit, _reg) \ | ||
| 101 | struct clk clk_##_name = { \ | ||
| 102 | .name = #_name, \ | ||
| 103 | .ops = &clk_prcmu_ops, \ | ||
| 104 | .prcmu_cg_off = _cg_off, \ | ||
| 105 | .prcmu_cg_bit = _cg_bit, \ | ||
| 106 | .prcmu_cg_mgt = PRCM_##_reg##_MGT \ | ||
| 107 | } | ||
| 108 | |||
| 109 | #define DEFINE_PRCMU_CLK_RATE(_name, _cg_off, _cg_bit, _reg, _rate) \ | ||
| 110 | struct clk clk_##_name = { \ | ||
| 111 | .name = #_name, \ | ||
| 112 | .ops = &clk_prcmu_ops, \ | ||
| 113 | .prcmu_cg_off = _cg_off, \ | ||
| 114 | .prcmu_cg_bit = _cg_bit, \ | ||
| 115 | .rate = _rate, \ | ||
| 116 | .prcmu_cg_mgt = PRCM_##_reg##_MGT \ | ||
| 117 | } | ||
| 118 | |||
| 119 | #define DEFINE_PRCC_CLK(_pclust, _name, _bus_en, _kernel_en, _kernclk) \ | ||
| 120 | struct clk clk_##_name = { \ | ||
| 121 | .name = #_name, \ | ||
| 122 | .ops = &clk_prcc_ops, \ | ||
| 123 | .cluster = _pclust, \ | ||
| 124 | .prcc_bus = _bus_en, \ | ||
| 125 | .prcc_kernel = _kernel_en, \ | ||
| 126 | .parent_cluster = &clk_per##_pclust##clk, \ | ||
| 127 | .parent_periph = _kernclk \ | ||
| 128 | } | ||
| 129 | |||
| 130 | #define DEFINE_PRCC_CLK_CUSTOM(_pclust, _name, _bus_en, _kernel_en, _kernclk, _callback, _data) \ | ||
| 131 | struct clk clk_##_name = { \ | ||
| 132 | .name = #_name, \ | ||
| 133 | .ops = &clk_prcc_ops, \ | ||
| 134 | .cluster = _pclust, \ | ||
| 135 | .prcc_bus = _bus_en, \ | ||
| 136 | .prcc_kernel = _kernel_en, \ | ||
| 137 | .parent_cluster = &clk_per##_pclust##clk, \ | ||
| 138 | .parent_periph = _kernclk, \ | ||
| 139 | .get_rate = _callback, \ | ||
| 140 | .data = (void *) _data \ | ||
| 141 | } | ||
| 142 | |||
| 143 | |||
| 144 | #define CLK(_clk, _devname, _conname) \ | ||
| 145 | { \ | ||
| 146 | .clk = &clk_##_clk, \ | ||
| 147 | .dev_id = _devname, \ | ||
| 148 | .con_id = _conname, \ | ||
| 149 | } | ||
| 150 | |||
| 151 | int __init clk_db8500_ed_fixup(void); | ||
| 152 | int __init clk_init(void); | ||
| 153 | |||
| 154 | #ifdef CONFIG_DEBUG_FS | ||
| 155 | int clk_debugfs_init(void); | ||
| 156 | #else | ||
| 157 | static inline int clk_debugfs_init(void) { return 0; } | ||
| 158 | #endif | ||
| 159 | |||
| 160 | #ifdef CONFIG_CPU_FREQ | ||
| 161 | int clk_init_smp_twd_cpufreq(void); | ||
| 162 | #else | ||
| 163 | static inline int clk_init_smp_twd_cpufreq(void) { return 0; } | ||
| 164 | #endif | ||
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c index db3c52d56ca4..38b7f9c4788b 100644 --- a/arch/arm/mach-ux500/cpu-db8500.c +++ b/arch/arm/mach-ux500/cpu-db8500.c | |||
| @@ -138,10 +138,6 @@ static struct platform_device *platform_devs[] __initdata = { | |||
| 138 | &db8500_prcmu_device, | 138 | &db8500_prcmu_device, |
| 139 | }; | 139 | }; |
| 140 | 140 | ||
| 141 | static struct platform_device *of_platform_devs[] __initdata = { | ||
| 142 | &u8500_dma40_device, | ||
| 143 | }; | ||
| 144 | |||
| 145 | static resource_size_t __initdata db8500_gpio_base[] = { | 141 | static resource_size_t __initdata db8500_gpio_base[] = { |
| 146 | U8500_GPIOBANK0_BASE, | 142 | U8500_GPIOBANK0_BASE, |
| 147 | U8500_GPIOBANK1_BASE, | 143 | U8500_GPIOBANK1_BASE, |
| @@ -235,7 +231,6 @@ struct device * __init u8500_init_devices(struct ab8500_platform_data *ab8500) | |||
| 235 | struct device * __init u8500_of_init_devices(void) | 231 | struct device * __init u8500_of_init_devices(void) |
| 236 | { | 232 | { |
| 237 | struct device *parent; | 233 | struct device *parent; |
| 238 | int i; | ||
| 239 | 234 | ||
| 240 | parent = db8500_soc_device_init(); | 235 | parent = db8500_soc_device_init(); |
| 241 | 236 | ||
| @@ -244,8 +239,7 @@ struct device * __init u8500_of_init_devices(void) | |||
| 244 | platform_device_register_data(parent, | 239 | platform_device_register_data(parent, |
| 245 | "cpufreq-u8500", -1, NULL, 0); | 240 | "cpufreq-u8500", -1, NULL, 0); |
| 246 | 241 | ||
| 247 | for (i = 0; i < ARRAY_SIZE(of_platform_devs); i++) | 242 | u8500_dma40_device.dev.parent = parent; |
| 248 | of_platform_devs[i]->dev.parent = parent; | ||
| 249 | 243 | ||
| 250 | /* | 244 | /* |
| 251 | * Devices to be DT:ed: | 245 | * Devices to be DT:ed: |
| @@ -253,7 +247,7 @@ struct device * __init u8500_of_init_devices(void) | |||
| 253 | * db8500_pmu_device = done | 247 | * db8500_pmu_device = done |
| 254 | * db8500_prcmu_device = done | 248 | * db8500_prcmu_device = done |
| 255 | */ | 249 | */ |
| 256 | platform_add_devices(of_platform_devs, ARRAY_SIZE(of_platform_devs)); | 250 | platform_device_register(&u8500_dma40_device); |
| 257 | 251 | ||
| 258 | return parent; | 252 | return parent; |
| 259 | } | 253 | } |
diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c index e2360e7c770d..17a78ec516ff 100644 --- a/arch/arm/mach-ux500/cpu.c +++ b/arch/arm/mach-ux500/cpu.c | |||
| @@ -8,7 +8,6 @@ | |||
| 8 | 8 | ||
| 9 | #include <linux/platform_device.h> | 9 | #include <linux/platform_device.h> |
| 10 | #include <linux/io.h> | 10 | #include <linux/io.h> |
| 11 | #include <linux/clk.h> | ||
| 12 | #include <linux/mfd/db8500-prcmu.h> | 11 | #include <linux/mfd/db8500-prcmu.h> |
| 13 | #include <linux/clksrc-dbx500-prcmu.h> | 12 | #include <linux/clksrc-dbx500-prcmu.h> |
| 14 | #include <linux/sys_soc.h> | 13 | #include <linux/sys_soc.h> |
| @@ -17,6 +16,7 @@ | |||
| 17 | #include <linux/stat.h> | 16 | #include <linux/stat.h> |
| 18 | #include <linux/of.h> | 17 | #include <linux/of.h> |
| 19 | #include <linux/of_irq.h> | 18 | #include <linux/of_irq.h> |
| 19 | #include <linux/platform_data/clk-ux500.h> | ||
| 20 | 20 | ||
| 21 | #include <asm/hardware/gic.h> | 21 | #include <asm/hardware/gic.h> |
| 22 | #include <asm/mach/map.h> | 22 | #include <asm/mach/map.h> |
| @@ -25,8 +25,6 @@ | |||
| 25 | #include <mach/setup.h> | 25 | #include <mach/setup.h> |
| 26 | #include <mach/devices.h> | 26 | #include <mach/devices.h> |
| 27 | 27 | ||
| 28 | #include "clock.h" | ||
| 29 | |||
| 30 | void __iomem *_PRCMU_BASE; | 28 | void __iomem *_PRCMU_BASE; |
| 31 | 29 | ||
| 32 | /* | 30 | /* |
| @@ -70,13 +68,17 @@ void __init ux500_init_irq(void) | |||
| 70 | */ | 68 | */ |
| 71 | if (cpu_is_u8500_family()) | 69 | if (cpu_is_u8500_family()) |
| 72 | db8500_prcmu_early_init(); | 70 | db8500_prcmu_early_init(); |
| 73 | clk_init(); | 71 | |
| 72 | if (cpu_is_u8500_family()) | ||
| 73 | u8500_clk_init(); | ||
| 74 | else if (cpu_is_u9540()) | ||
| 75 | u9540_clk_init(); | ||
| 76 | else if (cpu_is_u8540()) | ||
| 77 | u8540_clk_init(); | ||
| 74 | } | 78 | } |
| 75 | 79 | ||
| 76 | void __init ux500_init_late(void) | 80 | void __init ux500_init_late(void) |
| 77 | { | 81 | { |
| 78 | clk_debugfs_init(); | ||
| 79 | clk_init_smp_twd_cpufreq(); | ||
| 80 | } | 82 | } |
| 81 | 83 | ||
| 82 | static const char * __init ux500_get_machine(void) | 84 | static const char * __init ux500_get_machine(void) |
diff --git a/arch/arm/mach-ux500/include/mach/msp.h b/arch/arm/mach-ux500/include/mach/msp.h index 798be19129ef..3cc7142eee02 100644 --- a/arch/arm/mach-ux500/include/mach/msp.h +++ b/arch/arm/mach-ux500/include/mach/msp.h | |||
| @@ -22,8 +22,6 @@ struct msp_i2s_platform_data { | |||
| 22 | enum msp_i2s_id id; | 22 | enum msp_i2s_id id; |
| 23 | struct stedma40_chan_cfg *msp_i2s_dma_rx; | 23 | struct stedma40_chan_cfg *msp_i2s_dma_rx; |
| 24 | struct stedma40_chan_cfg *msp_i2s_dma_tx; | 24 | struct stedma40_chan_cfg *msp_i2s_dma_tx; |
| 25 | int (*msp_i2s_init) (void); | ||
| 26 | int (*msp_i2s_exit) (void); | ||
| 27 | }; | 25 | }; |
| 28 | 26 | ||
| 29 | #endif | 27 | #endif |
diff --git a/arch/arm/mm/cache-tauros2.c b/arch/arm/mm/cache-tauros2.c index 23a7643e9a87..1be0f4e5e6eb 100644 --- a/arch/arm/mm/cache-tauros2.c +++ b/arch/arm/mm/cache-tauros2.c | |||
| @@ -15,8 +15,11 @@ | |||
| 15 | */ | 15 | */ |
| 16 | 16 | ||
| 17 | #include <linux/init.h> | 17 | #include <linux/init.h> |
| 18 | #include <linux/of.h> | ||
| 19 | #include <linux/of_address.h> | ||
| 18 | #include <asm/cacheflush.h> | 20 | #include <asm/cacheflush.h> |
| 19 | #include <asm/cp15.h> | 21 | #include <asm/cp15.h> |
| 22 | #include <asm/cputype.h> | ||
| 20 | #include <asm/hardware/cache-tauros2.h> | 23 | #include <asm/hardware/cache-tauros2.h> |
| 21 | 24 | ||
| 22 | 25 | ||
| @@ -144,25 +147,8 @@ static inline void __init write_extra_features(u32 u) | |||
| 144 | __asm__("mcr p15, 1, %0, c15, c1, 0" : : "r" (u)); | 147 | __asm__("mcr p15, 1, %0, c15, c1, 0" : : "r" (u)); |
| 145 | } | 148 | } |
| 146 | 149 | ||
| 147 | static void __init disable_l2_prefetch(void) | ||
| 148 | { | ||
| 149 | u32 u; | ||
| 150 | |||
| 151 | /* | ||
| 152 | * Read the CPU Extra Features register and verify that the | ||
| 153 | * Disable L2 Prefetch bit is set. | ||
| 154 | */ | ||
| 155 | u = read_extra_features(); | ||
| 156 | if (!(u & 0x01000000)) { | ||
| 157 | printk(KERN_INFO "Tauros2: Disabling L2 prefetch.\n"); | ||
| 158 | write_extra_features(u | 0x01000000); | ||
| 159 | } | ||
| 160 | } | ||
| 161 | |||
| 162 | static inline int __init cpuid_scheme(void) | 150 | static inline int __init cpuid_scheme(void) |
| 163 | { | 151 | { |
| 164 | extern int processor_id; | ||
| 165 | |||
| 166 | return !!((processor_id & 0x000f0000) == 0x000f0000); | 152 | return !!((processor_id & 0x000f0000) == 0x000f0000); |
| 167 | } | 153 | } |
| 168 | 154 | ||
| @@ -189,12 +175,36 @@ static inline void __init write_actlr(u32 actlr) | |||
| 189 | __asm__("mcr p15, 0, %0, c1, c0, 1\n" : : "r" (actlr)); | 175 | __asm__("mcr p15, 0, %0, c1, c0, 1\n" : : "r" (actlr)); |
| 190 | } | 176 | } |
| 191 | 177 | ||
| 192 | void __init tauros2_init(void) | 178 | static void enable_extra_feature(unsigned int features) |
| 179 | { | ||
| 180 | u32 u; | ||
| 181 | |||
| 182 | u = read_extra_features(); | ||
| 183 | |||
| 184 | if (features & CACHE_TAUROS2_PREFETCH_ON) | ||
| 185 | u &= ~0x01000000; | ||
| 186 | else | ||
| 187 | u |= 0x01000000; | ||
| 188 | printk(KERN_INFO "Tauros2: %s L2 prefetch.\n", | ||
| 189 | (features & CACHE_TAUROS2_PREFETCH_ON) | ||
| 190 | ? "Enabling" : "Disabling"); | ||
| 191 | |||
| 192 | if (features & CACHE_TAUROS2_LINEFILL_BURST8) | ||
| 193 | u |= 0x00100000; | ||
| 194 | else | ||
| 195 | u &= ~0x00100000; | ||
| 196 | printk(KERN_INFO "Tauros2: %s line fill burt8.\n", | ||
| 197 | (features & CACHE_TAUROS2_LINEFILL_BURST8) | ||
| 198 | ? "Enabling" : "Disabling"); | ||
| 199 | |||
| 200 | write_extra_features(u); | ||
| 201 | } | ||
| 202 | |||
| 203 | static void __init tauros2_internal_init(unsigned int features) | ||
| 193 | { | 204 | { |
| 194 | extern int processor_id; | 205 | char *mode = NULL; |
| 195 | char *mode; | ||
| 196 | 206 | ||
| 197 | disable_l2_prefetch(); | 207 | enable_extra_feature(features); |
| 198 | 208 | ||
| 199 | #ifdef CONFIG_CPU_32v5 | 209 | #ifdef CONFIG_CPU_32v5 |
| 200 | if ((processor_id & 0xff0f0000) == 0x56050000) { | 210 | if ((processor_id & 0xff0f0000) == 0x56050000) { |
| @@ -286,3 +296,34 @@ void __init tauros2_init(void) | |||
| 286 | printk(KERN_INFO "Tauros2: L2 cache support initialised " | 296 | printk(KERN_INFO "Tauros2: L2 cache support initialised " |
| 287 | "in %s mode.\n", mode); | 297 | "in %s mode.\n", mode); |
| 288 | } | 298 | } |
| 299 | |||
| 300 | #ifdef CONFIG_OF | ||
| 301 | static const struct of_device_id tauros2_ids[] __initconst = { | ||
| 302 | { .compatible = "marvell,tauros2-cache"}, | ||
| 303 | {} | ||
| 304 | }; | ||
| 305 | #endif | ||
| 306 | |||
| 307 | void __init tauros2_init(unsigned int features) | ||
| 308 | { | ||
| 309 | #ifdef CONFIG_OF | ||
| 310 | struct device_node *node; | ||
| 311 | int ret; | ||
| 312 | unsigned int f; | ||
| 313 | |||
| 314 | node = of_find_matching_node(NULL, tauros2_ids); | ||
| 315 | if (!node) { | ||
| 316 | pr_info("Not found marvell,tauros2-cache, disable it\n"); | ||
| 317 | return; | ||
| 318 | } | ||
| 319 | |||
| 320 | ret = of_property_read_u32(node, "marvell,tauros2-cache-features", &f); | ||
| 321 | if (ret) { | ||
| 322 | pr_info("Not found marvell,tauros-cache-features property, " | ||
| 323 | "disable extra features\n"); | ||
| 324 | features = 0; | ||
| 325 | } else | ||
| 326 | features = f; | ||
| 327 | #endif | ||
| 328 | tauros2_internal_init(features); | ||
| 329 | } | ||
diff --git a/arch/arm/mm/context.c b/arch/arm/mm/context.c index 119bc52ab93e..4e07eec1270d 100644 --- a/arch/arm/mm/context.c +++ b/arch/arm/mm/context.c | |||
| @@ -63,10 +63,11 @@ static int contextidr_notifier(struct notifier_block *unused, unsigned long cmd, | |||
| 63 | pid = task_pid_nr(thread->task) << ASID_BITS; | 63 | pid = task_pid_nr(thread->task) << ASID_BITS; |
| 64 | asm volatile( | 64 | asm volatile( |
| 65 | " mrc p15, 0, %0, c13, c0, 1\n" | 65 | " mrc p15, 0, %0, c13, c0, 1\n" |
| 66 | " bfi %1, %0, #0, %2\n" | 66 | " and %0, %0, %2\n" |
| 67 | " mcr p15, 0, %1, c13, c0, 1\n" | 67 | " orr %0, %0, %1\n" |
| 68 | " mcr p15, 0, %0, c13, c0, 1\n" | ||
| 68 | : "=r" (contextidr), "+r" (pid) | 69 | : "=r" (contextidr), "+r" (pid) |
| 69 | : "I" (ASID_BITS)); | 70 | : "I" (~ASID_MASK)); |
| 70 | isb(); | 71 | isb(); |
| 71 | 72 | ||
| 72 | return NOTIFY_OK; | 73 | return NOTIFY_OK; |
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c index 051204fc4617..e59c4ab71bcb 100644 --- a/arch/arm/mm/dma-mapping.c +++ b/arch/arm/mm/dma-mapping.c | |||
| @@ -489,7 +489,7 @@ static bool __in_atomic_pool(void *start, size_t size) | |||
| 489 | void *pool_start = pool->vaddr; | 489 | void *pool_start = pool->vaddr; |
| 490 | void *pool_end = pool->vaddr + pool->size; | 490 | void *pool_end = pool->vaddr + pool->size; |
| 491 | 491 | ||
| 492 | if (start < pool_start || start > pool_end) | 492 | if (start < pool_start || start >= pool_end) |
| 493 | return false; | 493 | return false; |
| 494 | 494 | ||
| 495 | if (end <= pool_end) | 495 | if (end <= pool_end) |
diff --git a/arch/arm/mm/mm.h b/arch/arm/mm/mm.h index 6776160618ef..a8ee92da3544 100644 --- a/arch/arm/mm/mm.h +++ b/arch/arm/mm/mm.h | |||
| @@ -55,6 +55,9 @@ extern void __flush_dcache_page(struct address_space *mapping, struct page *page | |||
| 55 | /* permanent static mappings from iotable_init() */ | 55 | /* permanent static mappings from iotable_init() */ |
| 56 | #define VM_ARM_STATIC_MAPPING 0x40000000 | 56 | #define VM_ARM_STATIC_MAPPING 0x40000000 |
| 57 | 57 | ||
| 58 | /* empty mapping */ | ||
| 59 | #define VM_ARM_EMPTY_MAPPING 0x20000000 | ||
| 60 | |||
| 58 | /* mapping type (attributes) for permanent static mappings */ | 61 | /* mapping type (attributes) for permanent static mappings */ |
| 59 | #define VM_ARM_MTYPE(mt) ((mt) << 20) | 62 | #define VM_ARM_MTYPE(mt) ((mt) << 20) |
| 60 | #define VM_ARM_MTYPE_MASK (0x1f << 20) | 63 | #define VM_ARM_MTYPE_MASK (0x1f << 20) |
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c index 4c2d0451e84a..c2fa21d0103e 100644 --- a/arch/arm/mm/mmu.c +++ b/arch/arm/mm/mmu.c | |||
| @@ -807,7 +807,7 @@ static void __init pmd_empty_section_gap(unsigned long addr) | |||
| 807 | vm = early_alloc_aligned(sizeof(*vm), __alignof__(*vm)); | 807 | vm = early_alloc_aligned(sizeof(*vm), __alignof__(*vm)); |
| 808 | vm->addr = (void *)addr; | 808 | vm->addr = (void *)addr; |
| 809 | vm->size = SECTION_SIZE; | 809 | vm->size = SECTION_SIZE; |
| 810 | vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING; | 810 | vm->flags = VM_IOREMAP | VM_ARM_EMPTY_MAPPING; |
| 811 | vm->caller = pmd_empty_section_gap; | 811 | vm->caller = pmd_empty_section_gap; |
| 812 | vm_area_add_early(vm); | 812 | vm_area_add_early(vm); |
| 813 | } | 813 | } |
| @@ -820,7 +820,7 @@ static void __init fill_pmd_gaps(void) | |||
| 820 | 820 | ||
| 821 | /* we're still single threaded hence no lock needed here */ | 821 | /* we're still single threaded hence no lock needed here */ |
| 822 | for (vm = vmlist; vm; vm = vm->next) { | 822 | for (vm = vmlist; vm; vm = vm->next) { |
| 823 | if (!(vm->flags & VM_ARM_STATIC_MAPPING)) | 823 | if (!(vm->flags & (VM_ARM_STATIC_MAPPING | VM_ARM_EMPTY_MAPPING))) |
| 824 | continue; | 824 | continue; |
| 825 | addr = (unsigned long)vm->addr; | 825 | addr = (unsigned long)vm->addr; |
| 826 | if (addr < next) | 826 | if (addr < next) |
| @@ -961,8 +961,8 @@ void __init sanity_check_meminfo(void) | |||
| 961 | * Check whether this memory bank would partially overlap | 961 | * Check whether this memory bank would partially overlap |
| 962 | * the vmalloc area. | 962 | * the vmalloc area. |
| 963 | */ | 963 | */ |
| 964 | if (__va(bank->start + bank->size) > vmalloc_min || | 964 | if (__va(bank->start + bank->size - 1) >= vmalloc_min || |
| 965 | __va(bank->start + bank->size) < __va(bank->start)) { | 965 | __va(bank->start + bank->size - 1) <= __va(bank->start)) { |
| 966 | unsigned long newsize = vmalloc_min - __va(bank->start); | 966 | unsigned long newsize = vmalloc_min - __va(bank->start); |
| 967 | printk(KERN_NOTICE "Truncating RAM at %.8llx-%.8llx " | 967 | printk(KERN_NOTICE "Truncating RAM at %.8llx-%.8llx " |
| 968 | "to -%.8llx (vmalloc region overlap).\n", | 968 | "to -%.8llx (vmalloc region overlap).\n", |
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h index 7128e9710417..28ba09f4ebb9 100644 --- a/arch/arm/plat-mxc/include/mach/common.h +++ b/arch/arm/plat-mxc/include/mach/common.h | |||
| @@ -52,7 +52,6 @@ extern void imx31_soc_init(void); | |||
| 52 | extern void imx35_soc_init(void); | 52 | extern void imx35_soc_init(void); |
| 53 | extern void imx50_soc_init(void); | 53 | extern void imx50_soc_init(void); |
| 54 | extern void imx51_soc_init(void); | 54 | extern void imx51_soc_init(void); |
| 55 | extern void imx53_soc_init(void); | ||
| 56 | extern void imx51_init_late(void); | 55 | extern void imx51_init_late(void); |
| 57 | extern void imx53_init_late(void); | 56 | extern void imx53_init_late(void); |
| 58 | extern void epit_timer_init(void __iomem *base, int irq); | 57 | extern void epit_timer_init(void __iomem *base, int irq); |
| @@ -137,11 +136,6 @@ extern void imx_src_prepare_restart(void); | |||
| 137 | extern void imx_gpc_init(void); | 136 | extern void imx_gpc_init(void); |
| 138 | extern void imx_gpc_pre_suspend(void); | 137 | extern void imx_gpc_pre_suspend(void); |
| 139 | extern void imx_gpc_post_resume(void); | 138 | extern void imx_gpc_post_resume(void); |
| 140 | extern void imx51_babbage_common_init(void); | ||
| 141 | extern void imx53_ard_common_init(void); | ||
| 142 | extern void imx53_evk_common_init(void); | ||
| 143 | extern void imx53_qsb_common_init(void); | ||
| 144 | extern void imx53_smd_common_init(void); | ||
| 145 | extern int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode); | 139 | extern int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode); |
| 146 | extern void imx6q_clock_map_io(void); | 140 | extern void imx6q_clock_map_io(void); |
| 147 | 141 | ||
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx53.h b/arch/arm/plat-mxc/include/mach/iomux-mx53.h deleted file mode 100644 index 9761e003bde2..000000000000 --- a/arch/arm/plat-mxc/include/mach/iomux-mx53.h +++ /dev/null | |||
| @@ -1,1219 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License as published by | ||
| 6 | * the Free Software Foundation; either version 2 of the License, or | ||
| 7 | * (at your option) any later version. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | * | ||
| 14 | * You should have received a copy of the GNU General Public License along | ||
| 15 | * with this program; if not, write to the Free Software Foundation, Inc.. | ||
| 16 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. | ||
| 17 | */ | ||
| 18 | |||
| 19 | #ifndef __MACH_IOMUX_MX53_H__ | ||
| 20 | #define __MACH_IOMUX_MX53_H__ | ||
| 21 | |||
| 22 | #include <mach/iomux-v3.h> | ||
| 23 | |||
| 24 | /* These 2 defines are for pins that may not have a mux register, but could | ||
| 25 | * have a pad setting register, and vice-versa. */ | ||
| 26 | #define __NA_ 0x00 | ||
| 27 | |||
| 28 | #define MX53_UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ | ||
| 29 | PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST | PAD_CTL_HYS) | ||
| 30 | #define MX53_SDHC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ | ||
| 31 | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH | \ | ||
| 32 | PAD_CTL_SRE_FAST) | ||
| 33 | |||
| 34 | |||
| 35 | #define MX53_PAD_GPIO_19__KPP_COL_5 IOMUX_PAD(0x348, 0x020, 0, 0x840, 0, NO_PAD_CTRL) | ||
| 36 | #define MX53_PAD_GPIO_19__GPIO4_5 IOMUX_PAD(0x348, 0x020, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 37 | #define MX53_PAD_GPIO_19__CCM_CLKO IOMUX_PAD(0x348, 0x020, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 38 | #define MX53_PAD_GPIO_19__SPDIF_OUT1 IOMUX_PAD(0x348, 0x020, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 39 | #define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 IOMUX_PAD(0x348, 0x020, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 40 | #define MX53_PAD_GPIO_19__ECSPI1_RDY IOMUX_PAD(0x348, 0x020, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 41 | #define MX53_PAD_GPIO_19__FEC_TDATA_3 IOMUX_PAD(0x348, 0x020, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 42 | #define MX53_PAD_GPIO_19__SRC_INT_BOOT IOMUX_PAD(0x348, 0x020, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 43 | #define MX53_PAD_KEY_COL0__KPP_COL_0 IOMUX_PAD(0x34C, 0x024, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 44 | #define MX53_PAD_KEY_COL0__GPIO4_6 IOMUX_PAD(0x34C, 0x024, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 45 | #define MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC IOMUX_PAD(0x34C, 0x024, 2, 0x758, 0, NO_PAD_CTRL) | ||
| 46 | #define MX53_PAD_KEY_COL0__UART4_TXD_MUX IOMUX_PAD(0x34C, 0x024, 4, __NA_, 0, MX53_UART_PAD_CTRL) | ||
| 47 | #define MX53_PAD_KEY_COL0__ECSPI1_SCLK IOMUX_PAD(0x34C, 0x024, 5, 0x79C, 0, NO_PAD_CTRL) | ||
| 48 | #define MX53_PAD_KEY_COL0__FEC_RDATA_3 IOMUX_PAD(0x34C, 0x024, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 49 | #define MX53_PAD_KEY_COL0__SRC_ANY_PU_RST IOMUX_PAD(0x34C, 0x024, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 50 | #define MX53_PAD_KEY_ROW0__KPP_ROW_0 IOMUX_PAD(0x350, 0x028, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 51 | #define MX53_PAD_KEY_ROW0__GPIO4_7 IOMUX_PAD(0x350, 0x028, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 52 | #define MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD IOMUX_PAD(0x350, 0x028, 2, 0x74C, 0, NO_PAD_CTRL) | ||
| 53 | #define MX53_PAD_KEY_ROW0__UART4_RXD_MUX IOMUX_PAD(0x350, 0x028, 4, 0x890, 1, MX53_UART_PAD_CTRL) | ||
| 54 | #define MX53_PAD_KEY_ROW0__ECSPI1_MOSI IOMUX_PAD(0x350, 0x028, 5, 0x7A4, 0, NO_PAD_CTRL) | ||
| 55 | #define MX53_PAD_KEY_ROW0__FEC_TX_ER IOMUX_PAD(0x350, 0x028, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 56 | #define MX53_PAD_KEY_COL1__KPP_COL_1 IOMUX_PAD(0x354, 0x02C, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 57 | #define MX53_PAD_KEY_COL1__GPIO4_8 IOMUX_PAD(0x354, 0x02C, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 58 | #define MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS IOMUX_PAD(0x354, 0x02C, 2, 0x75C, 0, NO_PAD_CTRL) | ||
| 59 | #define MX53_PAD_KEY_COL1__UART5_TXD_MUX IOMUX_PAD(0x354, 0x02C, 4, __NA_, 0, MX53_UART_PAD_CTRL) | ||
| 60 | #define MX53_PAD_KEY_COL1__ECSPI1_MISO IOMUX_PAD(0x354, 0x02C, 5, 0x7A0, 0, NO_PAD_CTRL) | ||
| 61 | #define MX53_PAD_KEY_COL1__FEC_RX_CLK IOMUX_PAD(0x354, 0x02C, 6, 0x808, 0, NO_PAD_CTRL) | ||
| 62 | #define MX53_PAD_KEY_COL1__USBPHY1_TXREADY IOMUX_PAD(0x354, 0x02C, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 63 | #define MX53_PAD_KEY_ROW1__KPP_ROW_1 IOMUX_PAD(0x358, 0x030, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 64 | #define MX53_PAD_KEY_ROW1__GPIO4_9 IOMUX_PAD(0x358, 0x030, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 65 | #define MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD IOMUX_PAD(0x358, 0x030, 2, 0x748, 0, NO_PAD_CTRL) | ||
| 66 | #define MX53_PAD_KEY_ROW1__UART5_RXD_MUX IOMUX_PAD(0x358, 0x030, 4, 0x898, 1, MX53_UART_PAD_CTRL) | ||
| 67 | #define MX53_PAD_KEY_ROW1__ECSPI1_SS0 IOMUX_PAD(0x358, 0x030, 5, 0x7A8, 0, NO_PAD_CTRL) | ||
| 68 | #define MX53_PAD_KEY_ROW1__FEC_COL IOMUX_PAD(0x358, 0x030, 6, 0x800, 0, NO_PAD_CTRL) | ||
| 69 | #define MX53_PAD_KEY_ROW1__USBPHY1_RXVALID IOMUX_PAD(0x358, 0x030, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 70 | #define MX53_PAD_KEY_COL2__KPP_COL_2 IOMUX_PAD(0x35C, 0x034, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 71 | #define MX53_PAD_KEY_COL2__GPIO4_10 IOMUX_PAD(0x35C, 0x034, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 72 | #define MX53_PAD_KEY_COL2__CAN1_TXCAN IOMUX_PAD(0x35C, 0x034, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 73 | #define MX53_PAD_KEY_COL2__FEC_MDIO IOMUX_PAD(0x35C, 0x034, 4, 0x804, 0, NO_PAD_CTRL) | ||
| 74 | #define MX53_PAD_KEY_COL2__ECSPI1_SS1 IOMUX_PAD(0x35C, 0x034, 5, 0x7AC, 0, NO_PAD_CTRL) | ||
| 75 | #define MX53_PAD_KEY_COL2__FEC_RDATA_2 IOMUX_PAD(0x35C, 0x034, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 76 | #define MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE IOMUX_PAD(0x35C, 0x034, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 77 | #define MX53_PAD_KEY_ROW2__KPP_ROW_2 IOMUX_PAD(0x360, 0x038, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 78 | #define MX53_PAD_KEY_ROW2__GPIO4_11 IOMUX_PAD(0x360, 0x038, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 79 | #define MX53_PAD_KEY_ROW2__CAN1_RXCAN IOMUX_PAD(0x360, 0x038, 2, 0x760, 0, NO_PAD_CTRL) | ||
| 80 | #define MX53_PAD_KEY_ROW2__FEC_MDC IOMUX_PAD(0x360, 0x038, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 81 | #define MX53_PAD_KEY_ROW2__ECSPI1_SS2 IOMUX_PAD(0x360, 0x038, 5, 0x7B0, 0, NO_PAD_CTRL) | ||
| 82 | #define MX53_PAD_KEY_ROW2__FEC_TDATA_2 IOMUX_PAD(0x360, 0x038, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 83 | #define MX53_PAD_KEY_ROW2__USBPHY1_RXERROR IOMUX_PAD(0x360, 0x038, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 84 | #define MX53_PAD_KEY_COL3__KPP_COL_3 IOMUX_PAD(0x364, 0x03C, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 85 | #define MX53_PAD_KEY_COL3__GPIO4_12 IOMUX_PAD(0x364, 0x03C, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 86 | #define MX53_PAD_KEY_COL3__USBOH3_H2_DP IOMUX_PAD(0x364, 0x03C, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 87 | #define MX53_PAD_KEY_COL3__SPDIF_IN1 IOMUX_PAD(0x364, 0x03C, 3, 0x870, 0, NO_PAD_CTRL) | ||
| 88 | #define MX53_PAD_KEY_COL3__I2C2_SCL IOMUX_PAD(0x364, 0x03C, 4 | IOMUX_CONFIG_SION, 0x81C, 0, NO_PAD_CTRL) | ||
| 89 | #define MX53_PAD_KEY_COL3__ECSPI1_SS3 IOMUX_PAD(0x364, 0x03C, 5, 0x7B4, 0, NO_PAD_CTRL) | ||
| 90 | #define MX53_PAD_KEY_COL3__FEC_CRS IOMUX_PAD(0x364, 0x03C, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 91 | #define MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK IOMUX_PAD(0x364, 0x03C, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 92 | #define MX53_PAD_KEY_ROW3__KPP_ROW_3 IOMUX_PAD(0x368, 0x040, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 93 | #define MX53_PAD_KEY_ROW3__GPIO4_13 IOMUX_PAD(0x368, 0x040, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 94 | #define MX53_PAD_KEY_ROW3__USBOH3_H2_DM IOMUX_PAD(0x368, 0x040, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 95 | #define MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK IOMUX_PAD(0x368, 0x040, 3, 0x768, 0, NO_PAD_CTRL) | ||
| 96 | #define MX53_PAD_KEY_ROW3__I2C2_SDA IOMUX_PAD(0x368, 0x040, 4 | IOMUX_CONFIG_SION, 0x820, 0, NO_PAD_CTRL) | ||
| 97 | #define MX53_PAD_KEY_ROW3__OSC32K_32K_OUT IOMUX_PAD(0x368, 0x040, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 98 | #define MX53_PAD_KEY_ROW3__CCM_PLL4_BYP IOMUX_PAD(0x368, 0x040, 6, 0x77C, 0, NO_PAD_CTRL) | ||
| 99 | #define MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0 IOMUX_PAD(0x368, 0x040, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 100 | #define MX53_PAD_KEY_COL4__KPP_COL_4 IOMUX_PAD(0x36C, 0x044, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 101 | #define MX53_PAD_KEY_COL4__GPIO4_14 IOMUX_PAD(0x36C, 0x044, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 102 | #define MX53_PAD_KEY_COL4__CAN2_TXCAN IOMUX_PAD(0x36C, 0x044, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 103 | #define MX53_PAD_KEY_COL4__IPU_SISG_4 IOMUX_PAD(0x36C, 0x044, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 104 | #define MX53_PAD_KEY_COL4__UART5_RTS IOMUX_PAD(0x36C, 0x044, 4, 0x894, 0, MX53_UART_PAD_CTRL) | ||
| 105 | #define MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC IOMUX_PAD(0x36C, 0x044, 5, 0x89C, 0, NO_PAD_CTRL) | ||
| 106 | #define MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1 IOMUX_PAD(0x36C, 0x044, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 107 | #define MX53_PAD_KEY_ROW4__KPP_ROW_4 IOMUX_PAD(0x370, 0x048, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 108 | #define MX53_PAD_KEY_ROW4__GPIO4_15 IOMUX_PAD(0x370, 0x048, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 109 | #define MX53_PAD_KEY_ROW4__CAN2_RXCAN IOMUX_PAD(0x370, 0x048, 2, 0x764, 0, NO_PAD_CTRL) | ||
| 110 | #define MX53_PAD_KEY_ROW4__IPU_SISG_5 IOMUX_PAD(0x370, 0x048, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 111 | #define MX53_PAD_KEY_ROW4__UART5_CTS IOMUX_PAD(0x370, 0x048, 4, __NA_, 0, MX53_UART_PAD_CTRL) | ||
| 112 | #define MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR IOMUX_PAD(0x370, 0x048, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 113 | #define MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID IOMUX_PAD(0x370, 0x048, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 114 | #define MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK IOMUX_PAD(0x378, 0x04C, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 115 | #define MX53_PAD_DI0_DISP_CLK__GPIO4_16 IOMUX_PAD(0x378, 0x04C, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 116 | #define MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR IOMUX_PAD(0x378, 0x04C, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 117 | #define MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 IOMUX_PAD(0x378, 0x04C, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 118 | #define MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0 IOMUX_PAD(0x378, 0x04C, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 119 | #define MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID IOMUX_PAD(0x378, 0x04C, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 120 | #define MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 IOMUX_PAD(0x37C, 0x050, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 121 | #define MX53_PAD_DI0_PIN15__GPIO4_17 IOMUX_PAD(0x37C, 0x050, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 122 | #define MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC IOMUX_PAD(0x37C, 0x050, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 123 | #define MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 IOMUX_PAD(0x37C, 0x050, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 124 | #define MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1 IOMUX_PAD(0x37C, 0x050, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 125 | #define MX53_PAD_DI0_PIN15__USBPHY1_BVALID IOMUX_PAD(0x37C, 0x050, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 126 | #define MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 IOMUX_PAD(0x380, 0x054, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 127 | #define MX53_PAD_DI0_PIN2__GPIO4_18 IOMUX_PAD(0x380, 0x054, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 128 | #define MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD IOMUX_PAD(0x380, 0x054, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 129 | #define MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 IOMUX_PAD(0x380, 0x054, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 130 | #define MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2 IOMUX_PAD(0x380, 0x054, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 131 | #define MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION IOMUX_PAD(0x380, 0x054, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 132 | #define MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 IOMUX_PAD(0x384, 0x058, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 133 | #define MX53_PAD_DI0_PIN3__GPIO4_19 IOMUX_PAD(0x384, 0x058, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 134 | #define MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS IOMUX_PAD(0x384, 0x058, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 135 | #define MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 IOMUX_PAD(0x384, 0x058, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 136 | #define MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3 IOMUX_PAD(0x384, 0x058, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 137 | #define MX53_PAD_DI0_PIN3__USBPHY1_IDDIG IOMUX_PAD(0x384, 0x058, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 138 | #define MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 IOMUX_PAD(0x388, 0x05C, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 139 | #define MX53_PAD_DI0_PIN4__GPIO4_20 IOMUX_PAD(0x388, 0x05C, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 140 | #define MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD IOMUX_PAD(0x388, 0x05C, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 141 | #define MX53_PAD_DI0_PIN4__ESDHC1_WP IOMUX_PAD(0x388, 0x05C, 3, 0x7FC, 0, NO_PAD_CTRL) | ||
| 142 | #define MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD IOMUX_PAD(0x388, 0x05C, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 143 | #define MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4 IOMUX_PAD(0x388, 0x05C, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 144 | #define MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT IOMUX_PAD(0x388, 0x05C, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 145 | #define MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 IOMUX_PAD(0x38C, 0x060, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 146 | #define MX53_PAD_DISP0_DAT0__GPIO4_21 IOMUX_PAD(0x38C, 0x060, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 147 | #define MX53_PAD_DISP0_DAT0__CSPI_SCLK IOMUX_PAD(0x38C, 0x060, 2, 0x780, 0, NO_PAD_CTRL) | ||
| 148 | #define MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0 IOMUX_PAD(0x38C, 0x060, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 149 | #define MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN IOMUX_PAD(0x38C, 0x060, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 150 | #define MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5 IOMUX_PAD(0x38C, 0x060, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 151 | #define MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY IOMUX_PAD(0x38C, 0x060, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 152 | #define MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 IOMUX_PAD(0x390, 0x064, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 153 | #define MX53_PAD_DISP0_DAT1__GPIO4_22 IOMUX_PAD(0x390, 0x064, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 154 | #define MX53_PAD_DISP0_DAT1__CSPI_MOSI IOMUX_PAD(0x390, 0x064, 2, 0x788, 0, NO_PAD_CTRL) | ||
| 155 | #define MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1 IOMUX_PAD(0x390, 0x064, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 156 | #define MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL \ | ||
| 157 | IOMUX_PAD(0x390, 0x064, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 158 | #define MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6 IOMUX_PAD(0x390, 0x064, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 159 | #define MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID IOMUX_PAD(0x390, 0x064, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 160 | #define MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 IOMUX_PAD(0x394, 0x068, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 161 | #define MX53_PAD_DISP0_DAT2__GPIO4_23 IOMUX_PAD(0x394, 0x068, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 162 | #define MX53_PAD_DISP0_DAT2__CSPI_MISO IOMUX_PAD(0x394, 0x068, 2, 0x784, 0, NO_PAD_CTRL) | ||
| 163 | #define MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2 IOMUX_PAD(0x394, 0x068, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 164 | #define MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE IOMUX_PAD(0x394, 0x068, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 165 | #define MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7 IOMUX_PAD(0x394, 0x068, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 166 | #define MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE IOMUX_PAD(0x394, 0x068, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 167 | #define MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 IOMUX_PAD(0x398, 0x06C, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 168 | #define MX53_PAD_DISP0_DAT3__GPIO4_24 IOMUX_PAD(0x398, 0x06C, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 169 | #define MX53_PAD_DISP0_DAT3__CSPI_SS0 IOMUX_PAD(0x398, 0x06C, 2, 0x78C, 0, NO_PAD_CTRL) | ||
| 170 | #define MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3 IOMUX_PAD(0x398, 0x06C, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 171 | #define MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR IOMUX_PAD(0x398, 0x06C, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 172 | #define MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8 IOMUX_PAD(0x398, 0x06C, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 173 | #define MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR IOMUX_PAD(0x398, 0x06C, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 174 | #define MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 IOMUX_PAD(0x39C, 0x070, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 175 | #define MX53_PAD_DISP0_DAT4__GPIO4_25 IOMUX_PAD(0x39C, 0x070, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 176 | #define MX53_PAD_DISP0_DAT4__CSPI_SS1 IOMUX_PAD(0x39C, 0x070, 2, 0x790, 0, NO_PAD_CTRL) | ||
| 177 | #define MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4 IOMUX_PAD(0x39C, 0x070, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 178 | #define MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB IOMUX_PAD(0x39C, 0x070, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 179 | #define MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9 IOMUX_PAD(0x39C, 0x070, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 180 | #define MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK IOMUX_PAD(0x39C, 0x070, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 181 | #define MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 IOMUX_PAD(0x3A0, 0x074, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 182 | #define MX53_PAD_DISP0_DAT5__GPIO4_26 IOMUX_PAD(0x3A0, 0x074, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 183 | #define MX53_PAD_DISP0_DAT5__CSPI_SS2 IOMUX_PAD(0x3A0, 0x074, 2, 0x794, 0, NO_PAD_CTRL) | ||
| 184 | #define MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5 IOMUX_PAD(0x3A0, 0x074, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 185 | #define MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS IOMUX_PAD(0x3A0, 0x074, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 186 | #define MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10 IOMUX_PAD(0x3A0, 0x074, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 187 | #define MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0 IOMUX_PAD(0x3A0, 0x074, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 188 | #define MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 IOMUX_PAD(0x3A4, 0x078, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 189 | #define MX53_PAD_DISP0_DAT6__GPIO4_27 IOMUX_PAD(0x3A4, 0x078, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 190 | #define MX53_PAD_DISP0_DAT6__CSPI_SS3 IOMUX_PAD(0x3A4, 0x078, 2, 0x798, 0, NO_PAD_CTRL) | ||
| 191 | #define MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6 IOMUX_PAD(0x3A4, 0x078, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 192 | #define MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE IOMUX_PAD(0x3A4, 0x078, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 193 | #define MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11 IOMUX_PAD(0x3A4, 0x078, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 194 | #define MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1 IOMUX_PAD(0x3A4, 0x078, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 195 | #define MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 IOMUX_PAD(0x3A8, 0x07C, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 196 | #define MX53_PAD_DISP0_DAT7__GPIO4_28 IOMUX_PAD(0x3A8, 0x07C, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 197 | #define MX53_PAD_DISP0_DAT7__CSPI_RDY IOMUX_PAD(0x3A8, 0x07C, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 198 | #define MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7 IOMUX_PAD(0x3A8, 0x07C, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 199 | #define MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 IOMUX_PAD(0x3A8, 0x07C, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 200 | #define MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12 IOMUX_PAD(0x3A8, 0x07C, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 201 | #define MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID IOMUX_PAD(0x3A8, 0x07C, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 202 | #define MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 IOMUX_PAD(0x3AC, 0x080, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 203 | #define MX53_PAD_DISP0_DAT8__GPIO4_29 IOMUX_PAD(0x3AC, 0x080, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 204 | #define MX53_PAD_DISP0_DAT8__PWM1_PWMO IOMUX_PAD(0x3AC, 0x080, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 205 | #define MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B IOMUX_PAD(0x3AC, 0x080, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 206 | #define MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 IOMUX_PAD(0x3AC, 0x080, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 207 | #define MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13 IOMUX_PAD(0x3AC, 0x080, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 208 | #define MX53_PAD_DISP0_DAT8__USBPHY2_AVALID IOMUX_PAD(0x3AC, 0x080, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 209 | #define MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 IOMUX_PAD(0x3B0, 0x084, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 210 | #define MX53_PAD_DISP0_DAT9__GPIO4_30 IOMUX_PAD(0x3B0, 0x084, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 211 | #define MX53_PAD_DISP0_DAT9__PWM2_PWMO IOMUX_PAD(0x3B0, 0x084, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 212 | #define MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B IOMUX_PAD(0x3B0, 0x084, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 213 | #define MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 IOMUX_PAD(0x3B0, 0x084, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 214 | #define MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14 IOMUX_PAD(0x3B0, 0x084, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 215 | #define MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0 IOMUX_PAD(0x3B0, 0x084, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 216 | #define MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 IOMUX_PAD(0x3B4, 0x088, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 217 | #define MX53_PAD_DISP0_DAT10__GPIO4_31 IOMUX_PAD(0x3B4, 0x088, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 218 | #define MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP IOMUX_PAD(0x3B4, 0x088, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 219 | #define MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 \ | ||
| 220 | IOMUX_PAD(0x3B4, 0x088, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 221 | #define MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15 IOMUX_PAD(0x3B4, 0x088, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 222 | #define MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1 IOMUX_PAD(0x3B4, 0x088, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 223 | #define MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 IOMUX_PAD(0x3B8, 0x08C, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 224 | #define MX53_PAD_DISP0_DAT11__GPIO5_5 IOMUX_PAD(0x3B8, 0x08C, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 225 | #define MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT IOMUX_PAD(0x3B8, 0x08C, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 226 | #define MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 \ | ||
| 227 | IOMUX_PAD(0x3B8, 0x08C, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 228 | #define MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16 IOMUX_PAD(0x3B8, 0x08C, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 229 | #define MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2 IOMUX_PAD(0x3B8, 0x08C, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 230 | #define MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 IOMUX_PAD(0x3BC, 0x090, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 231 | #define MX53_PAD_DISP0_DAT12__GPIO5_6 IOMUX_PAD(0x3BC, 0x090, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 232 | #define MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK IOMUX_PAD(0x3BC, 0x090, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 233 | #define MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 \ | ||
| 234 | IOMUX_PAD(0x3BC, 0x090, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 235 | #define MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17 IOMUX_PAD(0x3BC, 0x090, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 236 | #define MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3 IOMUX_PAD(0x3BC, 0x090, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 237 | #define MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 IOMUX_PAD(0x3C0, 0x094, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 238 | #define MX53_PAD_DISP0_DAT13__GPIO5_7 IOMUX_PAD(0x3C0, 0x094, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 239 | #define MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS IOMUX_PAD(0x3C0, 0x094, 3, 0x754, 0, NO_PAD_CTRL) | ||
| 240 | #define MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 \ | ||
| 241 | IOMUX_PAD(0x3C0, 0x094, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 242 | #define MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18 IOMUX_PAD(0x3C0, 0x094, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 243 | #define MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4 IOMUX_PAD(0x3C0, 0x094, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 244 | #define MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 IOMUX_PAD(0x3C4, 0x098, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 245 | #define MX53_PAD_DISP0_DAT14__GPIO5_8 IOMUX_PAD(0x3C4, 0x098, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 246 | #define MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC IOMUX_PAD(0x3C4, 0x098, 3, 0x750, 0, NO_PAD_CTRL) | ||
| 247 | #define MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 \ | ||
| 248 | IOMUX_PAD(0x3C4, 0x098, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 249 | #define MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19 IOMUX_PAD(0x3C4, 0x098, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 250 | #define MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5 IOMUX_PAD(0x3C4, 0x098, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 251 | #define MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 IOMUX_PAD(0x3C8, 0x09C, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 252 | #define MX53_PAD_DISP0_DAT15__GPIO5_9 IOMUX_PAD(0x3C8, 0x09C, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 253 | #define MX53_PAD_DISP0_DAT15__ECSPI1_SS1 IOMUX_PAD(0x3C8, 0x09C, 2, 0x7AC, 1, NO_PAD_CTRL) | ||
| 254 | #define MX53_PAD_DISP0_DAT15__ECSPI2_SS1 IOMUX_PAD(0x3C8, 0x09C, 3, 0x7C8, 0, NO_PAD_CTRL) | ||
| 255 | #define MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 \ | ||
| 256 | IOMUX_PAD(0x3C8, 0x09C, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 257 | #define MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20 IOMUX_PAD(0x3C8, 0x09C, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 258 | #define MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6 IOMUX_PAD(0x3C8, 0x09C, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 259 | #define MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 IOMUX_PAD(0x3CC, 0x0A0, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 260 | #define MX53_PAD_DISP0_DAT16__GPIO5_10 IOMUX_PAD(0x3CC, 0x0A0, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 261 | #define MX53_PAD_DISP0_DAT16__ECSPI2_MOSI IOMUX_PAD(0x3CC, 0x0A0, 2, 0x7C0, 0, NO_PAD_CTRL) | ||
| 262 | #define MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC IOMUX_PAD(0x3CC, 0x0A0, 3, 0x758, 1, NO_PAD_CTRL) | ||
| 263 | #define MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 IOMUX_PAD(0x3CC, 0x0A0, 4, 0x868, 0, NO_PAD_CTRL) | ||
| 264 | #define MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3 \ | ||
| 265 | IOMUX_PAD(0x3CC, 0x0A0, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 266 | #define MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21 IOMUX_PAD(0x3CC, 0x0A0, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 267 | #define MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7 IOMUX_PAD(0x3CC, 0x0A0, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 268 | #define MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 IOMUX_PAD(0x3D0, 0x0A4, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 269 | #define MX53_PAD_DISP0_DAT17__GPIO5_11 IOMUX_PAD(0x3D0, 0x0A4, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 270 | #define MX53_PAD_DISP0_DAT17__ECSPI2_MISO IOMUX_PAD(0x3D0, 0x0A4, 2, 0x7BC, 0, NO_PAD_CTRL) | ||
| 271 | #define MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD IOMUX_PAD(0x3D0, 0x0A4, 3, 0x74C, 1, NO_PAD_CTRL) | ||
| 272 | #define MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 IOMUX_PAD(0x3D0, 0x0A4, 4, 0x86C, 0, NO_PAD_CTRL) | ||
| 273 | #define MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4 \ | ||
| 274 | IOMUX_PAD(0x3D0, 0x0A4, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 275 | #define MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22 IOMUX_PAD(0x3D0, 0x0A4, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 276 | #define MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 IOMUX_PAD(0x3D4, 0x0A8, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 277 | #define MX53_PAD_DISP0_DAT18__GPIO5_12 IOMUX_PAD(0x3D4, 0x0A8, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 278 | #define MX53_PAD_DISP0_DAT18__ECSPI2_SS0 IOMUX_PAD(0x3D4, 0x0A8, 2, 0x7C4, 0, NO_PAD_CTRL) | ||
| 279 | #define MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS IOMUX_PAD(0x3D4, 0x0A8, 3, 0x75C, 1, NO_PAD_CTRL) | ||
| 280 | #define MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS IOMUX_PAD(0x3D4, 0x0A8, 4, 0x73C, 0, NO_PAD_CTRL) | ||
| 281 | #define MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5 \ | ||
| 282 | IOMUX_PAD(0x3D4, 0x0A8, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 283 | #define MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23 IOMUX_PAD(0x3D4, 0x0A8, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 284 | #define MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2 IOMUX_PAD(0x3D4, 0x0A8, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 285 | #define MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 IOMUX_PAD(0x3D8, 0x0AC, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 286 | #define MX53_PAD_DISP0_DAT19__GPIO5_13 IOMUX_PAD(0x3D8, 0x0AC, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 287 | #define MX53_PAD_DISP0_DAT19__ECSPI2_SCLK IOMUX_PAD(0x3D8, 0x0AC, 2, 0x7B8, 0, NO_PAD_CTRL) | ||
| 288 | #define MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD IOMUX_PAD(0x3D8, 0x0AC, 3, 0x748, 1, NO_PAD_CTRL) | ||
| 289 | #define MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC IOMUX_PAD(0x3D8, 0x0AC, 4, 0x738, 0, NO_PAD_CTRL) | ||
| 290 | #define MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6 \ | ||
| 291 | IOMUX_PAD(0x3D8, 0x0AC, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 292 | #define MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24 IOMUX_PAD(0x3D8, 0x0AC, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 293 | #define MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3 IOMUX_PAD(0x3D8, 0x0AC, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 294 | #define MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 IOMUX_PAD(0x3DC, 0x0B0, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 295 | #define MX53_PAD_DISP0_DAT20__GPIO5_14 IOMUX_PAD(0x3DC, 0x0B0, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 296 | #define MX53_PAD_DISP0_DAT20__ECSPI1_SCLK IOMUX_PAD(0x3DC, 0x0B0, 2, 0x79C, 1, NO_PAD_CTRL) | ||
| 297 | #define MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC IOMUX_PAD(0x3DC, 0x0B0, 3, 0x740, 0, NO_PAD_CTRL) | ||
| 298 | #define MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 \ | ||
| 299 | IOMUX_PAD(0x3DC, 0x0B0, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 300 | #define MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25 IOMUX_PAD(0x3DC, 0x0B0, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 301 | #define MX53_PAD_DISP0_DAT20__SATA_PHY_TDI IOMUX_PAD(0x3DC, 0x0B0, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 302 | #define MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 IOMUX_PAD(0x3E0, 0x0B4, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 303 | #define MX53_PAD_DISP0_DAT21__GPIO5_15 IOMUX_PAD(0x3E0, 0x0B4, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 304 | #define MX53_PAD_DISP0_DAT21__ECSPI1_MOSI IOMUX_PAD(0x3E0, 0x0B4, 2, 0x7A4, 1, NO_PAD_CTRL) | ||
| 305 | #define MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD IOMUX_PAD(0x3E0, 0x0B4, 3, 0x734, 0, NO_PAD_CTRL) | ||
| 306 | #define MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 IOMUX_PAD(0x3E0, 0x0B4, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 307 | #define MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26 IOMUX_PAD(0x3E0, 0x0B4, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 308 | #define MX53_PAD_DISP0_DAT21__SATA_PHY_TDO IOMUX_PAD(0x3E0, 0x0B4, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 309 | #define MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 IOMUX_PAD(0x3E4, 0x0B8, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 310 | #define MX53_PAD_DISP0_DAT22__GPIO5_16 IOMUX_PAD(0x3E4, 0x0B8, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 311 | #define MX53_PAD_DISP0_DAT22__ECSPI1_MISO IOMUX_PAD(0x3E4, 0x0B8, 2, 0x7A0, 1, NO_PAD_CTRL) | ||
| 312 | #define MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS IOMUX_PAD(0x3E4, 0x0B8, 3, 0x744, 0, NO_PAD_CTRL) | ||
| 313 | #define MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 IOMUX_PAD(0x3E4, 0x0B8, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 314 | #define MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27 IOMUX_PAD(0x3E4, 0x0B8, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 315 | #define MX53_PAD_DISP0_DAT22__SATA_PHY_TCK IOMUX_PAD(0x3E4, 0x0B8, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 316 | #define MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 IOMUX_PAD(0x3E8, 0x0BC, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 317 | #define MX53_PAD_DISP0_DAT23__GPIO5_17 IOMUX_PAD(0x3E8, 0x0BC, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 318 | #define MX53_PAD_DISP0_DAT23__ECSPI1_SS0 IOMUX_PAD(0x3E8, 0x0BC, 2, 0x7A8, 1, NO_PAD_CTRL) | ||
| 319 | #define MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD IOMUX_PAD(0x3E8, 0x0BC, 3, 0x730, 0, NO_PAD_CTRL) | ||
| 320 | #define MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 IOMUX_PAD(0x3E8, 0x0BC, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 321 | #define MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28 IOMUX_PAD(0x3E8, 0x0BC, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 322 | #define MX53_PAD_DISP0_DAT23__SATA_PHY_TMS IOMUX_PAD(0x3E8, 0x0BC, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 323 | #define MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK IOMUX_PAD(0x3EC, 0x0C0, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 324 | #define MX53_PAD_CSI0_PIXCLK__GPIO5_18 IOMUX_PAD(0x3EC, 0x0C0, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 325 | #define MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 IOMUX_PAD(0x3EC, 0x0C0, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 326 | #define MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29 IOMUX_PAD(0x3EC, 0x0C0, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 327 | #define MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC IOMUX_PAD(0x3F0, 0x0C4, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 328 | #define MX53_PAD_CSI0_MCLK__GPIO5_19 IOMUX_PAD(0x3F0, 0x0C4, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 329 | #define MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK IOMUX_PAD(0x3F0, 0x0C4, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 330 | #define MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 IOMUX_PAD(0x3F0, 0x0C4, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 331 | #define MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30 IOMUX_PAD(0x3F0, 0x0C4, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 332 | #define MX53_PAD_CSI0_MCLK__TPIU_TRCTL IOMUX_PAD(0x3F0, 0x0C4, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 333 | #define MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN IOMUX_PAD(0x3F4, 0x0C8, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 334 | #define MX53_PAD_CSI0_DATA_EN__GPIO5_20 IOMUX_PAD(0x3F4, 0x0C8, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 335 | #define MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 IOMUX_PAD(0x3F4, 0x0C8, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 336 | #define MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31 IOMUX_PAD(0x3F4, 0x0C8, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 337 | #define MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK IOMUX_PAD(0x3F4, 0x0C8, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 338 | #define MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC IOMUX_PAD(0x3F8, 0x0CC, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 339 | #define MX53_PAD_CSI0_VSYNC__GPIO5_21 IOMUX_PAD(0x3F8, 0x0CC, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 340 | #define MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 IOMUX_PAD(0x3F8, 0x0CC, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 341 | #define MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32 IOMUX_PAD(0x3F8, 0x0CC, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 342 | #define MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0 IOMUX_PAD(0x3F8, 0x0CC, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 343 | #define MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 IOMUX_PAD(0x3FC, 0x0D0, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 344 | #define MX53_PAD_CSI0_DAT4__GPIO5_22 IOMUX_PAD(0x3FC, 0x0D0, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 345 | #define MX53_PAD_CSI0_DAT4__KPP_COL_5 IOMUX_PAD(0x3FC, 0x0D0, 2, 0x840, 1, NO_PAD_CTRL) | ||
| 346 | #define MX53_PAD_CSI0_DAT4__ECSPI1_SCLK IOMUX_PAD(0x3FC, 0x0D0, 3, 0x79C, 2, NO_PAD_CTRL) | ||
| 347 | #define MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP IOMUX_PAD(0x3FC, 0x0D0, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 348 | #define MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC IOMUX_PAD(0x3FC, 0x0D0, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 349 | #define MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33 IOMUX_PAD(0x3FC, 0x0D0, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 350 | #define MX53_PAD_CSI0_DAT4__TPIU_TRACE_1 IOMUX_PAD(0x3FC, 0x0D0, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 351 | #define MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 IOMUX_PAD(0x400, 0x0D4, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 352 | #define MX53_PAD_CSI0_DAT5__GPIO5_23 IOMUX_PAD(0x400, 0x0D4, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 353 | #define MX53_PAD_CSI0_DAT5__KPP_ROW_5 IOMUX_PAD(0x400, 0x0D4, 2, 0x84C, 0, NO_PAD_CTRL) | ||
| 354 | #define MX53_PAD_CSI0_DAT5__ECSPI1_MOSI IOMUX_PAD(0x400, 0x0D4, 3, 0x7A4, 2, NO_PAD_CTRL) | ||
| 355 | #define MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT IOMUX_PAD(0x400, 0x0D4, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 356 | #define MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD IOMUX_PAD(0x400, 0x0D4, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 357 | #define MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34 IOMUX_PAD(0x400, 0x0D4, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 358 | #define MX53_PAD_CSI0_DAT5__TPIU_TRACE_2 IOMUX_PAD(0x400, 0x0D4, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 359 | #define MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 IOMUX_PAD(0x404, 0x0D8, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 360 | #define MX53_PAD_CSI0_DAT6__GPIO5_24 IOMUX_PAD(0x404, 0x0D8, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 361 | #define MX53_PAD_CSI0_DAT6__KPP_COL_6 IOMUX_PAD(0x404, 0x0D8, 2, 0x844, 0, NO_PAD_CTRL) | ||
| 362 | #define MX53_PAD_CSI0_DAT6__ECSPI1_MISO IOMUX_PAD(0x404, 0x0D8, 3, 0x7A0, 2, NO_PAD_CTRL) | ||
| 363 | #define MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK IOMUX_PAD(0x404, 0x0D8, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 364 | #define MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS IOMUX_PAD(0x404, 0x0D8, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 365 | #define MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35 IOMUX_PAD(0x404, 0x0D8, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 366 | #define MX53_PAD_CSI0_DAT6__TPIU_TRACE_3 IOMUX_PAD(0x404, 0x0D8, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 367 | #define MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 IOMUX_PAD(0x408, 0x0DC, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 368 | #define MX53_PAD_CSI0_DAT7__GPIO5_25 IOMUX_PAD(0x408, 0x0DC, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 369 | #define MX53_PAD_CSI0_DAT7__KPP_ROW_6 IOMUX_PAD(0x408, 0x0DC, 2, 0x850, 0, NO_PAD_CTRL) | ||
| 370 | #define MX53_PAD_CSI0_DAT7__ECSPI1_SS0 IOMUX_PAD(0x408, 0x0DC, 3, 0x7A8, 2, NO_PAD_CTRL) | ||
| 371 | #define MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR IOMUX_PAD(0x408, 0x0DC, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 372 | #define MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD IOMUX_PAD(0x408, 0x0DC, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 373 | #define MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36 IOMUX_PAD(0x408, 0x0DC, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 374 | #define MX53_PAD_CSI0_DAT7__TPIU_TRACE_4 IOMUX_PAD(0x408, 0x0DC, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 375 | #define MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 IOMUX_PAD(0x40C, 0x0E0, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 376 | #define MX53_PAD_CSI0_DAT8__GPIO5_26 IOMUX_PAD(0x40C, 0x0E0, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 377 | #define MX53_PAD_CSI0_DAT8__KPP_COL_7 IOMUX_PAD(0x40C, 0x0E0, 2, 0x848, 0, NO_PAD_CTRL) | ||
| 378 | #define MX53_PAD_CSI0_DAT8__ECSPI2_SCLK IOMUX_PAD(0x40C, 0x0E0, 3, 0x7B8, 1, NO_PAD_CTRL) | ||
| 379 | #define MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC IOMUX_PAD(0x40C, 0x0E0, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 380 | #define MX53_PAD_CSI0_DAT8__I2C1_SDA IOMUX_PAD(0x40C, 0x0E0, 5 | IOMUX_CONFIG_SION, 0x818, 0, NO_PAD_CTRL) | ||
| 381 | #define MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37 IOMUX_PAD(0x40C, 0x0E0, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 382 | #define MX53_PAD_CSI0_DAT8__TPIU_TRACE_5 IOMUX_PAD(0x40C, 0x0E0, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 383 | #define MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 IOMUX_PAD(0x410, 0x0E4, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 384 | #define MX53_PAD_CSI0_DAT9__GPIO5_27 IOMUX_PAD(0x410, 0x0E4, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 385 | #define MX53_PAD_CSI0_DAT9__KPP_ROW_7 IOMUX_PAD(0x410, 0x0E4, 2, 0x854, 0, NO_PAD_CTRL) | ||
| 386 | #define MX53_PAD_CSI0_DAT9__ECSPI2_MOSI IOMUX_PAD(0x410, 0x0E4, 3, 0x7C0, 1, NO_PAD_CTRL) | ||
| 387 | #define MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR IOMUX_PAD(0x410, 0x0E4, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 388 | #define MX53_PAD_CSI0_DAT9__I2C1_SCL IOMUX_PAD(0x410, 0x0E4, 5 | IOMUX_CONFIG_SION, 0x814, 0, NO_PAD_CTRL) | ||
| 389 | #define MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38 IOMUX_PAD(0x410, 0x0E4, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 390 | #define MX53_PAD_CSI0_DAT9__TPIU_TRACE_6 IOMUX_PAD(0x410, 0x0E4, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 391 | #define MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 IOMUX_PAD(0x414, 0x0E8, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 392 | #define MX53_PAD_CSI0_DAT10__GPIO5_28 IOMUX_PAD(0x414, 0x0E8, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 393 | #define MX53_PAD_CSI0_DAT10__UART1_TXD_MUX IOMUX_PAD(0x414, 0x0E8, 2, __NA_, 0, MX53_UART_PAD_CTRL) | ||
| 394 | #define MX53_PAD_CSI0_DAT10__ECSPI2_MISO IOMUX_PAD(0x414, 0x0E8, 3, 0x7BC, 1, NO_PAD_CTRL) | ||
| 395 | #define MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC IOMUX_PAD(0x414, 0x0E8, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 396 | #define MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 IOMUX_PAD(0x414, 0x0E8, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 397 | #define MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39 IOMUX_PAD(0x414, 0x0E8, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 398 | #define MX53_PAD_CSI0_DAT10__TPIU_TRACE_7 IOMUX_PAD(0x414, 0x0E8, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 399 | #define MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 IOMUX_PAD(0x418, 0x0EC, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 400 | #define MX53_PAD_CSI0_DAT11__GPIO5_29 IOMUX_PAD(0x418, 0x0EC, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 401 | #define MX53_PAD_CSI0_DAT11__UART1_RXD_MUX IOMUX_PAD(0x418, 0x0EC, 2, 0x878, 1, MX53_UART_PAD_CTRL) | ||
| 402 | #define MX53_PAD_CSI0_DAT11__ECSPI2_SS0 IOMUX_PAD(0x418, 0x0EC, 3, 0x7C4, 1, NO_PAD_CTRL) | ||
| 403 | #define MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS IOMUX_PAD(0x418, 0x0EC, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 404 | #define MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 IOMUX_PAD(0x418, 0x0EC, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 405 | #define MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40 IOMUX_PAD(0x418, 0x0EC, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 406 | #define MX53_PAD_CSI0_DAT11__TPIU_TRACE_8 IOMUX_PAD(0x418, 0x0EC, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 407 | #define MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 IOMUX_PAD(0x41C, 0x0F0, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 408 | #define MX53_PAD_CSI0_DAT12__GPIO5_30 IOMUX_PAD(0x41C, 0x0F0, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 409 | #define MX53_PAD_CSI0_DAT12__UART4_TXD_MUX IOMUX_PAD(0x41C, 0x0F0, 2, __NA_, 0, MX53_UART_PAD_CTRL) | ||
| 410 | #define MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0 IOMUX_PAD(0x41C, 0x0F0, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 411 | #define MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 IOMUX_PAD(0x41C, 0x0F0, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 412 | #define MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41 IOMUX_PAD(0x41C, 0x0F0, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 413 | #define MX53_PAD_CSI0_DAT12__TPIU_TRACE_9 IOMUX_PAD(0x41C, 0x0F0, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 414 | #define MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 IOMUX_PAD(0x420, 0x0F4, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 415 | #define MX53_PAD_CSI0_DAT13__GPIO5_31 IOMUX_PAD(0x420, 0x0F4, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 416 | #define MX53_PAD_CSI0_DAT13__UART4_RXD_MUX IOMUX_PAD(0x420, 0x0F4, 2, 0x890, 3, MX53_UART_PAD_CTRL) | ||
| 417 | #define MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1 IOMUX_PAD(0x420, 0x0F4, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 418 | #define MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 IOMUX_PAD(0x420, 0x0F4, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 419 | #define MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42 IOMUX_PAD(0x420, 0x0F4, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 420 | #define MX53_PAD_CSI0_DAT13__TPIU_TRACE_10 IOMUX_PAD(0x420, 0x0F4, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 421 | #define MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 IOMUX_PAD(0x424, 0x0F8, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 422 | #define MX53_PAD_CSI0_DAT14__GPIO6_0 IOMUX_PAD(0x424, 0x0F8, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 423 | #define MX53_PAD_CSI0_DAT14__UART5_TXD_MUX IOMUX_PAD(0x424, 0x0F8, 2, __NA_, 0, MX53_UART_PAD_CTRL) | ||
| 424 | #define MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2 IOMUX_PAD(0x424, 0x0F8, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 425 | #define MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 IOMUX_PAD(0x424, 0x0F8, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 426 | #define MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43 IOMUX_PAD(0x424, 0x0F8, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 427 | #define MX53_PAD_CSI0_DAT14__TPIU_TRACE_11 IOMUX_PAD(0x424, 0x0F8, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 428 | #define MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 IOMUX_PAD(0x428, 0x0FC, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 429 | #define MX53_PAD_CSI0_DAT15__GPIO6_1 IOMUX_PAD(0x428, 0x0FC, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 430 | #define MX53_PAD_CSI0_DAT15__UART5_RXD_MUX IOMUX_PAD(0x428, 0x0FC, 2, 0x898, 3, MX53_UART_PAD_CTRL) | ||
| 431 | #define MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3 IOMUX_PAD(0x428, 0x0FC, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 432 | #define MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 IOMUX_PAD(0x428, 0x0FC, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 433 | #define MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44 IOMUX_PAD(0x428, 0x0FC, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 434 | #define MX53_PAD_CSI0_DAT15__TPIU_TRACE_12 IOMUX_PAD(0x428, 0x0FC, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 435 | #define MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 IOMUX_PAD(0x42C, 0x100, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 436 | #define MX53_PAD_CSI0_DAT16__GPIO6_2 IOMUX_PAD(0x42C, 0x100, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 437 | #define MX53_PAD_CSI0_DAT16__UART4_RTS IOMUX_PAD(0x42C, 0x100, 2, 0x88C, 0, MX53_UART_PAD_CTRL) | ||
| 438 | #define MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4 IOMUX_PAD(0x42C, 0x100, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 439 | #define MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 IOMUX_PAD(0x42C, 0x100, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 440 | #define MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45 IOMUX_PAD(0x42C, 0x100, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 441 | #define MX53_PAD_CSI0_DAT16__TPIU_TRACE_13 IOMUX_PAD(0x42C, 0x100, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 442 | #define MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 IOMUX_PAD(0x430, 0x104, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 443 | #define MX53_PAD_CSI0_DAT17__GPIO6_3 IOMUX_PAD(0x430, 0x104, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 444 | #define MX53_PAD_CSI0_DAT17__UART4_CTS IOMUX_PAD(0x430, 0x104, 2, __NA_, 0, MX53_UART_PAD_CTRL) | ||
| 445 | #define MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5 IOMUX_PAD(0x430, 0x104, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 446 | #define MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 IOMUX_PAD(0x430, 0x104, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 447 | #define MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46 IOMUX_PAD(0x430, 0x104, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 448 | #define MX53_PAD_CSI0_DAT17__TPIU_TRACE_14 IOMUX_PAD(0x430, 0x104, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 449 | #define MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 IOMUX_PAD(0x434, 0x108, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 450 | #define MX53_PAD_CSI0_DAT18__GPIO6_4 IOMUX_PAD(0x434, 0x108, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 451 | #define MX53_PAD_CSI0_DAT18__UART5_RTS IOMUX_PAD(0x434, 0x108, 2, 0x894, 2, MX53_UART_PAD_CTRL) | ||
| 452 | #define MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6 IOMUX_PAD(0x434, 0x108, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 453 | #define MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 IOMUX_PAD(0x434, 0x108, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 454 | #define MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47 IOMUX_PAD(0x434, 0x108, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 455 | #define MX53_PAD_CSI0_DAT18__TPIU_TRACE_15 IOMUX_PAD(0x434, 0x108, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 456 | #define MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 IOMUX_PAD(0x438, 0x10C, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 457 | #define MX53_PAD_CSI0_DAT19__GPIO6_5 IOMUX_PAD(0x438, 0x10C, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 458 | #define MX53_PAD_CSI0_DAT19__UART5_CTS IOMUX_PAD(0x438, 0x10C, 2, __NA_, 0, MX53_UART_PAD_CTRL) | ||
| 459 | #define MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7 IOMUX_PAD(0x438, 0x10C, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 460 | #define MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 IOMUX_PAD(0x438, 0x10C, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 461 | #define MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48 IOMUX_PAD(0x438, 0x10C, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 462 | #define MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK IOMUX_PAD(0x438, 0x10C, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 463 | #define MX53_PAD_EIM_A25__EMI_WEIM_A_25 IOMUX_PAD(0x458, 0x110, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 464 | #define MX53_PAD_EIM_A25__GPIO5_2 IOMUX_PAD(0x458, 0x110, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 465 | #define MX53_PAD_EIM_A25__ECSPI2_RDY IOMUX_PAD(0x458, 0x110, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 466 | #define MX53_PAD_EIM_A25__IPU_DI1_PIN12 IOMUX_PAD(0x458, 0x110, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 467 | #define MX53_PAD_EIM_A25__CSPI_SS1 IOMUX_PAD(0x458, 0x110, 4, 0x790, 1, NO_PAD_CTRL) | ||
| 468 | #define MX53_PAD_EIM_A25__IPU_DI0_D1_CS IOMUX_PAD(0x458, 0x110, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 469 | #define MX53_PAD_EIM_A25__USBPHY1_BISTOK IOMUX_PAD(0x458, 0x110, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 470 | #define MX53_PAD_EIM_EB2__EMI_WEIM_EB_2 IOMUX_PAD(0x45C, 0x114, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 471 | #define MX53_PAD_EIM_EB2__GPIO2_30 IOMUX_PAD(0x45C, 0x114, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 472 | #define MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK IOMUX_PAD(0x45C, 0x114, 2, 0x76C, 0, NO_PAD_CTRL) | ||
| 473 | #define MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS IOMUX_PAD(0x45C, 0x114, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 474 | #define MX53_PAD_EIM_EB2__ECSPI1_SS0 IOMUX_PAD(0x45C, 0x114, 4, 0x7A8, 3, NO_PAD_CTRL) | ||
| 475 | #define MX53_PAD_EIM_EB2__I2C2_SCL IOMUX_PAD(0x45C, 0x114, 5 | IOMUX_CONFIG_SION, 0x81C, 1, NO_PAD_CTRL) | ||
| 476 | #define MX53_PAD_EIM_D16__EMI_WEIM_D_16 IOMUX_PAD(0x460, 0x118, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 477 | #define MX53_PAD_EIM_D16__GPIO3_16 IOMUX_PAD(0x460, 0x118, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 478 | #define MX53_PAD_EIM_D16__IPU_DI0_PIN5 IOMUX_PAD(0x460, 0x118, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 479 | #define MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK IOMUX_PAD(0x460, 0x118, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 480 | #define MX53_PAD_EIM_D16__ECSPI1_SCLK IOMUX_PAD(0x460, 0x118, 4, 0x79C, 3, NO_PAD_CTRL) | ||
| 481 | #define MX53_PAD_EIM_D16__I2C2_SDA IOMUX_PAD(0x460, 0x118, 5 | IOMUX_CONFIG_SION, 0x820, 1, NO_PAD_CTRL) | ||
| 482 | #define MX53_PAD_EIM_D17__EMI_WEIM_D_17 IOMUX_PAD(0x464, 0x11C, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 483 | #define MX53_PAD_EIM_D17__GPIO3_17 IOMUX_PAD(0x464, 0x11C, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 484 | #define MX53_PAD_EIM_D17__IPU_DI0_PIN6 IOMUX_PAD(0x464, 0x11C, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 485 | #define MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN IOMUX_PAD(0x464, 0x11C, 3, 0x830, 0, NO_PAD_CTRL) | ||
| 486 | #define MX53_PAD_EIM_D17__ECSPI1_MISO IOMUX_PAD(0x464, 0x11C, 4, 0x7A0, 3, NO_PAD_CTRL) | ||
| 487 | #define MX53_PAD_EIM_D17__I2C3_SCL IOMUX_PAD(0x464, 0x11C, 5 | IOMUX_CONFIG_SION, 0x824, 0, NO_PAD_CTRL) | ||
| 488 | #define MX53_PAD_EIM_D18__EMI_WEIM_D_18 IOMUX_PAD(0x468, 0x120, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 489 | #define MX53_PAD_EIM_D18__GPIO3_18 IOMUX_PAD(0x468, 0x120, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 490 | #define MX53_PAD_EIM_D18__IPU_DI0_PIN7 IOMUX_PAD(0x468, 0x120, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 491 | #define MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO IOMUX_PAD(0x468, 0x120, 3, 0x830, 1, NO_PAD_CTRL) | ||
| 492 | #define MX53_PAD_EIM_D18__ECSPI1_MOSI IOMUX_PAD(0x468, 0x120, 4, 0x7A4, 3, NO_PAD_CTRL) | ||
| 493 | #define MX53_PAD_EIM_D18__I2C3_SDA IOMUX_PAD(0x468, 0x120, 5 | IOMUX_CONFIG_SION, 0x828, 0, NO_PAD_CTRL) | ||
| 494 | #define MX53_PAD_EIM_D18__IPU_DI1_D0_CS IOMUX_PAD(0x468, 0x120, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 495 | #define MX53_PAD_EIM_D19__EMI_WEIM_D_19 IOMUX_PAD(0x46C, 0x124, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 496 | #define MX53_PAD_EIM_D19__GPIO3_19 IOMUX_PAD(0x46C, 0x124, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 497 | #define MX53_PAD_EIM_D19__IPU_DI0_PIN8 IOMUX_PAD(0x46C, 0x124, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 498 | #define MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS IOMUX_PAD(0x46C, 0x124, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 499 | #define MX53_PAD_EIM_D19__ECSPI1_SS1 IOMUX_PAD(0x46C, 0x124, 4, 0x7AC, 2, NO_PAD_CTRL) | ||
| 500 | #define MX53_PAD_EIM_D19__EPIT1_EPITO IOMUX_PAD(0x46C, 0x124, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 501 | #define MX53_PAD_EIM_D19__UART1_CTS IOMUX_PAD(0x46C, 0x124, 6, __NA_, 0, MX53_UART_PAD_CTRL) | ||
| 502 | #define MX53_PAD_EIM_D19__USBOH3_USBH2_OC IOMUX_PAD(0x46C, 0x124, 7, 0x8A4, 0, NO_PAD_CTRL) | ||
| 503 | #define MX53_PAD_EIM_D20__EMI_WEIM_D_20 IOMUX_PAD(0x470, 0x128, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 504 | #define MX53_PAD_EIM_D20__GPIO3_20 IOMUX_PAD(0x470, 0x128, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 505 | #define MX53_PAD_EIM_D20__IPU_DI0_PIN16 IOMUX_PAD(0x470, 0x128, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 506 | #define MX53_PAD_EIM_D20__IPU_SER_DISP0_CS IOMUX_PAD(0x470, 0x128, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 507 | #define MX53_PAD_EIM_D20__CSPI_SS0 IOMUX_PAD(0x470, 0x128, 4, 0x78C, 1, NO_PAD_CTRL) | ||
| 508 | #define MX53_PAD_EIM_D20__EPIT2_EPITO IOMUX_PAD(0x470, 0x128, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 509 | #define MX53_PAD_EIM_D20__UART1_RTS IOMUX_PAD(0x470, 0x128, 6, 0x874, 1, MX53_UART_PAD_CTRL) | ||
| 510 | #define MX53_PAD_EIM_D20__USBOH3_USBH2_PWR IOMUX_PAD(0x470, 0x128, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 511 | #define MX53_PAD_EIM_D21__EMI_WEIM_D_21 IOMUX_PAD(0x474, 0x12C, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 512 | #define MX53_PAD_EIM_D21__GPIO3_21 IOMUX_PAD(0x474, 0x12C, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 513 | #define MX53_PAD_EIM_D21__IPU_DI0_PIN17 IOMUX_PAD(0x474, 0x12C, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 514 | #define MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK IOMUX_PAD(0x474, 0x12C, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 515 | #define MX53_PAD_EIM_D21__CSPI_SCLK IOMUX_PAD(0x474, 0x12C, 4, 0x780, 1, NO_PAD_CTRL) | ||
| 516 | #define MX53_PAD_EIM_D21__I2C1_SCL IOMUX_PAD(0x474, 0x12C, 5 | IOMUX_CONFIG_SION, 0x814, 1, NO_PAD_CTRL) | ||
| 517 | #define MX53_PAD_EIM_D21__USBOH3_USBOTG_OC IOMUX_PAD(0x474, 0x12C, 6, 0x89C, 1, NO_PAD_CTRL) | ||
| 518 | #define MX53_PAD_EIM_D22__EMI_WEIM_D_22 IOMUX_PAD(0x478, 0x130, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 519 | #define MX53_PAD_EIM_D22__GPIO3_22 IOMUX_PAD(0x478, 0x130, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 520 | #define MX53_PAD_EIM_D22__IPU_DI0_PIN1 IOMUX_PAD(0x478, 0x130, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 521 | #define MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN IOMUX_PAD(0x478, 0x130, 3, 0x82C, 0, NO_PAD_CTRL) | ||
| 522 | #define MX53_PAD_EIM_D22__CSPI_MISO IOMUX_PAD(0x478, 0x130, 4, 0x784, 1, NO_PAD_CTRL) | ||
| 523 | #define MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR IOMUX_PAD(0x478, 0x130, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 524 | #define MX53_PAD_EIM_D23__EMI_WEIM_D_23 IOMUX_PAD(0x47C, 0x134, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 525 | #define MX53_PAD_EIM_D23__GPIO3_23 IOMUX_PAD(0x47C, 0x134, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 526 | #define MX53_PAD_EIM_D23__UART3_CTS IOMUX_PAD(0x47C, 0x134, 2, __NA_, 0, MX53_UART_PAD_CTRL) | ||
| 527 | #define MX53_PAD_EIM_D23__UART1_DCD IOMUX_PAD(0x47C, 0x134, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 528 | #define MX53_PAD_EIM_D23__IPU_DI0_D0_CS IOMUX_PAD(0x47C, 0x134, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 529 | #define MX53_PAD_EIM_D23__IPU_DI1_PIN2 IOMUX_PAD(0x47C, 0x134, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 530 | #define MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN IOMUX_PAD(0x47C, 0x134, 6, 0x834, 0, NO_PAD_CTRL) | ||
| 531 | #define MX53_PAD_EIM_D23__IPU_DI1_PIN14 IOMUX_PAD(0x47C, 0x134, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 532 | #define MX53_PAD_EIM_EB3__EMI_WEIM_EB_3 IOMUX_PAD(0x480, 0x138, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 533 | #define MX53_PAD_EIM_EB3__GPIO2_31 IOMUX_PAD(0x480, 0x138, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 534 | #define MX53_PAD_EIM_EB3__UART3_RTS IOMUX_PAD(0x480, 0x138, 2, 0x884, 1, MX53_UART_PAD_CTRL) | ||
| 535 | #define MX53_PAD_EIM_EB3__UART1_RI IOMUX_PAD(0x480, 0x138, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 536 | #define MX53_PAD_EIM_EB3__IPU_DI1_PIN3 IOMUX_PAD(0x480, 0x138, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 537 | #define MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC IOMUX_PAD(0x480, 0x138, 6, 0x838, 0, NO_PAD_CTRL) | ||
| 538 | #define MX53_PAD_EIM_EB3__IPU_DI1_PIN16 IOMUX_PAD(0x480, 0x138, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 539 | #define MX53_PAD_EIM_D24__EMI_WEIM_D_24 IOMUX_PAD(0x484, 0x13C, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 540 | #define MX53_PAD_EIM_D24__GPIO3_24 IOMUX_PAD(0x484, 0x13C, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 541 | #define MX53_PAD_EIM_D24__UART3_TXD_MUX IOMUX_PAD(0x484, 0x13C, 2, __NA_, 0, MX53_UART_PAD_CTRL) | ||
| 542 | #define MX53_PAD_EIM_D24__ECSPI1_SS2 IOMUX_PAD(0x484, 0x13C, 3, 0x7B0, 1, NO_PAD_CTRL) | ||
| 543 | #define MX53_PAD_EIM_D24__CSPI_SS2 IOMUX_PAD(0x484, 0x13C, 4, 0x794, 1, NO_PAD_CTRL) | ||
| 544 | #define MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS IOMUX_PAD(0x484, 0x13C, 5, 0x754, 1, NO_PAD_CTRL) | ||
| 545 | #define MX53_PAD_EIM_D24__ECSPI2_SS2 IOMUX_PAD(0x484, 0x13C, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 546 | #define MX53_PAD_EIM_D24__UART1_DTR IOMUX_PAD(0x484, 0x13C, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 547 | #define MX53_PAD_EIM_D25__EMI_WEIM_D_25 IOMUX_PAD(0x488, 0x140, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 548 | #define MX53_PAD_EIM_D25__GPIO3_25 IOMUX_PAD(0x488, 0x140, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 549 | #define MX53_PAD_EIM_D25__UART3_RXD_MUX IOMUX_PAD(0x488, 0x140, 2, 0x888, 1, MX53_UART_PAD_CTRL) | ||
| 550 | #define MX53_PAD_EIM_D25__ECSPI1_SS3 IOMUX_PAD(0x488, 0x140, 3, 0x7B4, 1, NO_PAD_CTRL) | ||
| 551 | #define MX53_PAD_EIM_D25__CSPI_SS3 IOMUX_PAD(0x488, 0x140, 4, 0x798, 1, NO_PAD_CTRL) | ||
| 552 | #define MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC IOMUX_PAD(0x488, 0x140, 5, 0x750, 1, NO_PAD_CTRL) | ||
| 553 | #define MX53_PAD_EIM_D25__ECSPI2_SS3 IOMUX_PAD(0x488, 0x140, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 554 | #define MX53_PAD_EIM_D25__UART1_DSR IOMUX_PAD(0x488, 0x140, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 555 | #define MX53_PAD_EIM_D26__EMI_WEIM_D_26 IOMUX_PAD(0x48C, 0x144, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 556 | #define MX53_PAD_EIM_D26__GPIO3_26 IOMUX_PAD(0x48C, 0x144, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 557 | #define MX53_PAD_EIM_D26__UART2_TXD_MUX IOMUX_PAD(0x48C, 0x144, 2, __NA_, 0, MX53_UART_PAD_CTRL) | ||
| 558 | #define MX53_PAD_EIM_D26__FIRI_RXD IOMUX_PAD(0x48C, 0x144, 3, 0x80C, 0, NO_PAD_CTRL) | ||
| 559 | #define MX53_PAD_EIM_D26__IPU_CSI0_D_1 IOMUX_PAD(0x48C, 0x144, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 560 | #define MX53_PAD_EIM_D26__IPU_DI1_PIN11 IOMUX_PAD(0x48C, 0x144, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 561 | #define MX53_PAD_EIM_D26__IPU_SISG_2 IOMUX_PAD(0x48C, 0x144, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 562 | #define MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 IOMUX_PAD(0x48C, 0x144, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 563 | #define MX53_PAD_EIM_D27__EMI_WEIM_D_27 IOMUX_PAD(0x490, 0x148, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 564 | #define MX53_PAD_EIM_D27__GPIO3_27 IOMUX_PAD(0x490, 0x148, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 565 | #define MX53_PAD_EIM_D27__UART2_RXD_MUX IOMUX_PAD(0x490, 0x148, 2, 0x880, 1, MX53_UART_PAD_CTRL) | ||
| 566 | #define MX53_PAD_EIM_D27__FIRI_TXD IOMUX_PAD(0x490, 0x148, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 567 | #define MX53_PAD_EIM_D27__IPU_CSI0_D_0 IOMUX_PAD(0x490, 0x148, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 568 | #define MX53_PAD_EIM_D27__IPU_DI1_PIN13 IOMUX_PAD(0x490, 0x148, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 569 | #define MX53_PAD_EIM_D27__IPU_SISG_3 IOMUX_PAD(0x490, 0x148, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 570 | #define MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 IOMUX_PAD(0x490, 0x148, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 571 | #define MX53_PAD_EIM_D28__EMI_WEIM_D_28 IOMUX_PAD(0x494, 0x14C, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 572 | #define MX53_PAD_EIM_D28__GPIO3_28 IOMUX_PAD(0x494, 0x14C, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 573 | #define MX53_PAD_EIM_D28__UART2_CTS IOMUX_PAD(0x494, 0x14C, 2, __NA_, 0, MX53_UART_PAD_CTRL) | ||
| 574 | #define MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO IOMUX_PAD(0x494, 0x14C, 3, 0x82C, 1, NO_PAD_CTRL) | ||
| 575 | #define MX53_PAD_EIM_D28__CSPI_MOSI IOMUX_PAD(0x494, 0x14C, 4, 0x788, 1, NO_PAD_CTRL) | ||
| 576 | #define MX53_PAD_EIM_D28__I2C1_SDA IOMUX_PAD(0x494, 0x14C, 5 | IOMUX_CONFIG_SION, 0x818, 1, NO_PAD_CTRL) | ||
| 577 | #define MX53_PAD_EIM_D28__IPU_EXT_TRIG IOMUX_PAD(0x494, 0x14C, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 578 | #define MX53_PAD_EIM_D28__IPU_DI0_PIN13 IOMUX_PAD(0x494, 0x14C, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 579 | #define MX53_PAD_EIM_D29__EMI_WEIM_D_29 IOMUX_PAD(0x498, 0x150, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 580 | #define MX53_PAD_EIM_D29__GPIO3_29 IOMUX_PAD(0x498, 0x150, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 581 | #define MX53_PAD_EIM_D29__UART2_RTS IOMUX_PAD(0x498, 0x150, 2, 0x87C, 1, MX53_UART_PAD_CTRL) | ||
| 582 | #define MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS IOMUX_PAD(0x498, 0x150, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 583 | #define MX53_PAD_EIM_D29__CSPI_SS0 IOMUX_PAD(0x498, 0x150, 4, 0x78C, 2, NO_PAD_CTRL) | ||
| 584 | #define MX53_PAD_EIM_D29__IPU_DI1_PIN15 IOMUX_PAD(0x498, 0x150, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 585 | #define MX53_PAD_EIM_D29__IPU_CSI1_VSYNC IOMUX_PAD(0x498, 0x150, 6, 0x83C, 0, NO_PAD_CTRL) | ||
| 586 | #define MX53_PAD_EIM_D29__IPU_DI0_PIN14 IOMUX_PAD(0x498, 0x150, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 587 | #define MX53_PAD_EIM_D30__EMI_WEIM_D_30 IOMUX_PAD(0x49C, 0x154, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 588 | #define MX53_PAD_EIM_D30__GPIO3_30 IOMUX_PAD(0x49C, 0x154, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 589 | #define MX53_PAD_EIM_D30__UART3_CTS IOMUX_PAD(0x49C, 0x154, 2, __NA_, 0, MX53_UART_PAD_CTRL) | ||
| 590 | #define MX53_PAD_EIM_D30__IPU_CSI0_D_3 IOMUX_PAD(0x49C, 0x154, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 591 | #define MX53_PAD_EIM_D30__IPU_DI0_PIN11 IOMUX_PAD(0x49C, 0x154, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 592 | #define MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 IOMUX_PAD(0x49C, 0x154, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 593 | #define MX53_PAD_EIM_D30__USBOH3_USBH1_OC IOMUX_PAD(0x49C, 0x154, 6, 0x8A0, 0, NO_PAD_CTRL) | ||
| 594 | #define MX53_PAD_EIM_D30__USBOH3_USBH2_OC IOMUX_PAD(0x49C, 0x154, 7, 0x8A4, 1, NO_PAD_CTRL) | ||
| 595 | #define MX53_PAD_EIM_D31__EMI_WEIM_D_31 IOMUX_PAD(0x4A0, 0x158, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 596 | #define MX53_PAD_EIM_D31__GPIO3_31 IOMUX_PAD(0x4A0, 0x158, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 597 | #define MX53_PAD_EIM_D31__UART3_RTS IOMUX_PAD(0x4A0, 0x158, 2, 0x884, 3, MX53_UART_PAD_CTRL) | ||
| 598 | #define MX53_PAD_EIM_D31__IPU_CSI0_D_2 IOMUX_PAD(0x4A0, 0x158, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 599 | #define MX53_PAD_EIM_D31__IPU_DI0_PIN12 IOMUX_PAD(0x4A0, 0x158, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 600 | #define MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 IOMUX_PAD(0x4A0, 0x158, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 601 | #define MX53_PAD_EIM_D31__USBOH3_USBH1_PWR IOMUX_PAD(0x4A0, 0x158, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 602 | #define MX53_PAD_EIM_D31__USBOH3_USBH2_PWR IOMUX_PAD(0x4A0, 0x158, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 603 | #define MX53_PAD_EIM_A24__EMI_WEIM_A_24 IOMUX_PAD(0x4A8, 0x15C, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 604 | #define MX53_PAD_EIM_A24__GPIO5_4 IOMUX_PAD(0x4A8, 0x15C, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 605 | #define MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 IOMUX_PAD(0x4A8, 0x15C, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 606 | #define MX53_PAD_EIM_A24__IPU_CSI1_D_19 IOMUX_PAD(0x4A8, 0x15C, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 607 | #define MX53_PAD_EIM_A24__IPU_SISG_2 IOMUX_PAD(0x4A8, 0x15C, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 608 | #define MX53_PAD_EIM_A24__USBPHY2_BVALID IOMUX_PAD(0x4A8, 0x15C, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 609 | #define MX53_PAD_EIM_A23__EMI_WEIM_A_23 IOMUX_PAD(0x4AC, 0x160, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 610 | #define MX53_PAD_EIM_A23__GPIO6_6 IOMUX_PAD(0x4AC, 0x160, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 611 | #define MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 IOMUX_PAD(0x4AC, 0x160, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 612 | #define MX53_PAD_EIM_A23__IPU_CSI1_D_18 IOMUX_PAD(0x4AC, 0x160, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 613 | #define MX53_PAD_EIM_A23__IPU_SISG_3 IOMUX_PAD(0x4AC, 0x160, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 614 | #define MX53_PAD_EIM_A23__USBPHY2_ENDSESSION IOMUX_PAD(0x4AC, 0x160, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 615 | #define MX53_PAD_EIM_A22__EMI_WEIM_A_22 IOMUX_PAD(0x4B0, 0x164, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 616 | #define MX53_PAD_EIM_A22__GPIO2_16 IOMUX_PAD(0x4B0, 0x164, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 617 | #define MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 IOMUX_PAD(0x4B0, 0x164, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 618 | #define MX53_PAD_EIM_A22__IPU_CSI1_D_17 IOMUX_PAD(0x4B0, 0x164, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 619 | #define MX53_PAD_EIM_A22__SRC_BT_CFG1_7 IOMUX_PAD(0x4B0, 0x164, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 620 | #define MX53_PAD_EIM_A21__EMI_WEIM_A_21 IOMUX_PAD(0x4B4, 0x168, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 621 | #define MX53_PAD_EIM_A21__GPIO2_17 IOMUX_PAD(0x4B4, 0x168, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 622 | #define MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 IOMUX_PAD(0x4B4, 0x168, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 623 | #define MX53_PAD_EIM_A21__IPU_CSI1_D_16 IOMUX_PAD(0x4B4, 0x168, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 624 | #define MX53_PAD_EIM_A21__SRC_BT_CFG1_6 IOMUX_PAD(0x4B4, 0x168, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 625 | #define MX53_PAD_EIM_A20__EMI_WEIM_A_20 IOMUX_PAD(0x4B8, 0x16C, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 626 | #define MX53_PAD_EIM_A20__GPIO2_18 IOMUX_PAD(0x4B8, 0x16C, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 627 | #define MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 IOMUX_PAD(0x4B8, 0x16C, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 628 | #define MX53_PAD_EIM_A20__IPU_CSI1_D_15 IOMUX_PAD(0x4B8, 0x16C, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 629 | #define MX53_PAD_EIM_A20__SRC_BT_CFG1_5 IOMUX_PAD(0x4B8, 0x16C, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 630 | #define MX53_PAD_EIM_A19__EMI_WEIM_A_19 IOMUX_PAD(0x4BC, 0x170, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 631 | #define MX53_PAD_EIM_A19__GPIO2_19 IOMUX_PAD(0x4BC, 0x170, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 632 | #define MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 IOMUX_PAD(0x4BC, 0x170, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 633 | #define MX53_PAD_EIM_A19__IPU_CSI1_D_14 IOMUX_PAD(0x4BC, 0x170, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 634 | #define MX53_PAD_EIM_A19__SRC_BT_CFG1_4 IOMUX_PAD(0x4BC, 0x170, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 635 | #define MX53_PAD_EIM_A18__EMI_WEIM_A_18 IOMUX_PAD(0x4C0, 0x174, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 636 | #define MX53_PAD_EIM_A18__GPIO2_20 IOMUX_PAD(0x4C0, 0x174, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 637 | #define MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 IOMUX_PAD(0x4C0, 0x174, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 638 | #define MX53_PAD_EIM_A18__IPU_CSI1_D_13 IOMUX_PAD(0x4C0, 0x174, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 639 | #define MX53_PAD_EIM_A18__SRC_BT_CFG1_3 IOMUX_PAD(0x4C0, 0x174, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 640 | #define MX53_PAD_EIM_A17__EMI_WEIM_A_17 IOMUX_PAD(0x4C4, 0x178, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 641 | #define MX53_PAD_EIM_A17__GPIO2_21 IOMUX_PAD(0x4C4, 0x178, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 642 | #define MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 IOMUX_PAD(0x4C4, 0x178, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 643 | #define MX53_PAD_EIM_A17__IPU_CSI1_D_12 IOMUX_PAD(0x4C4, 0x178, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 644 | #define MX53_PAD_EIM_A17__SRC_BT_CFG1_2 IOMUX_PAD(0x4C4, 0x178, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 645 | #define MX53_PAD_EIM_A16__EMI_WEIM_A_16 IOMUX_PAD(0x4C8, 0x17C, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 646 | #define MX53_PAD_EIM_A16__GPIO2_22 IOMUX_PAD(0x4C8, 0x17C, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 647 | #define MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK IOMUX_PAD(0x4C8, 0x17C, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 648 | #define MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK IOMUX_PAD(0x4C8, 0x17C, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 649 | #define MX53_PAD_EIM_A16__SRC_BT_CFG1_1 IOMUX_PAD(0x4C8, 0x17C, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 650 | #define MX53_PAD_EIM_CS0__EMI_WEIM_CS_0 IOMUX_PAD(0x4CC, 0x180, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 651 | #define MX53_PAD_EIM_CS0__GPIO2_23 IOMUX_PAD(0x4CC, 0x180, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 652 | #define MX53_PAD_EIM_CS0__ECSPI2_SCLK IOMUX_PAD(0x4CC, 0x180, 2, 0x7B8, 2, NO_PAD_CTRL) | ||
| 653 | #define MX53_PAD_EIM_CS0__IPU_DI1_PIN5 IOMUX_PAD(0x4CC, 0x180, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 654 | #define MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 IOMUX_PAD(0x4D0, 0x184, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 655 | #define MX53_PAD_EIM_CS1__GPIO2_24 IOMUX_PAD(0x4D0, 0x184, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 656 | #define MX53_PAD_EIM_CS1__ECSPI2_MOSI IOMUX_PAD(0x4D0, 0x184, 2, 0x7C0, 2, NO_PAD_CTRL) | ||
| 657 | #define MX53_PAD_EIM_CS1__IPU_DI1_PIN6 IOMUX_PAD(0x4D0, 0x184, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 658 | #define MX53_PAD_EIM_OE__EMI_WEIM_OE IOMUX_PAD(0x4D4, 0x188, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 659 | #define MX53_PAD_EIM_OE__GPIO2_25 IOMUX_PAD(0x4D4, 0x188, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 660 | #define MX53_PAD_EIM_OE__ECSPI2_MISO IOMUX_PAD(0x4D4, 0x188, 2, 0x7BC, 2, NO_PAD_CTRL) | ||
| 661 | #define MX53_PAD_EIM_OE__IPU_DI1_PIN7 IOMUX_PAD(0x4D4, 0x188, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 662 | #define MX53_PAD_EIM_OE__USBPHY2_IDDIG IOMUX_PAD(0x4D4, 0x188, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 663 | #define MX53_PAD_EIM_RW__EMI_WEIM_RW IOMUX_PAD(0x4D8, 0x18C, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 664 | #define MX53_PAD_EIM_RW__GPIO2_26 IOMUX_PAD(0x4D8, 0x18C, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 665 | #define MX53_PAD_EIM_RW__ECSPI2_SS0 IOMUX_PAD(0x4D8, 0x18C, 2, 0x7C4, 2, NO_PAD_CTRL) | ||
| 666 | #define MX53_PAD_EIM_RW__IPU_DI1_PIN8 IOMUX_PAD(0x4D8, 0x18C, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 667 | #define MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT IOMUX_PAD(0x4D8, 0x18C, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 668 | #define MX53_PAD_EIM_LBA__EMI_WEIM_LBA IOMUX_PAD(0x4DC, 0x190, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 669 | #define MX53_PAD_EIM_LBA__GPIO2_27 IOMUX_PAD(0x4DC, 0x190, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 670 | #define MX53_PAD_EIM_LBA__ECSPI2_SS1 IOMUX_PAD(0x4DC, 0x190, 2, 0x7C8, 1, NO_PAD_CTRL) | ||
| 671 | #define MX53_PAD_EIM_LBA__IPU_DI1_PIN17 IOMUX_PAD(0x4DC, 0x190, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 672 | #define MX53_PAD_EIM_LBA__SRC_BT_CFG1_0 IOMUX_PAD(0x4DC, 0x190, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 673 | #define MX53_PAD_EIM_EB0__EMI_WEIM_EB_0 IOMUX_PAD(0x4E4, 0x194, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 674 | #define MX53_PAD_EIM_EB0__GPIO2_28 IOMUX_PAD(0x4E4, 0x194, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 675 | #define MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 IOMUX_PAD(0x4E4, 0x194, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 676 | #define MX53_PAD_EIM_EB0__IPU_CSI1_D_11 IOMUX_PAD(0x4E4, 0x194, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 677 | #define MX53_PAD_EIM_EB0__GPC_PMIC_RDY IOMUX_PAD(0x4E4, 0x194, 5, 0x810, 0, NO_PAD_CTRL) | ||
| 678 | #define MX53_PAD_EIM_EB0__SRC_BT_CFG2_7 IOMUX_PAD(0x4E4, 0x194, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 679 | #define MX53_PAD_EIM_EB1__EMI_WEIM_EB_1 IOMUX_PAD(0x4E8, 0x198, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 680 | #define MX53_PAD_EIM_EB1__GPIO2_29 IOMUX_PAD(0x4E8, 0x198, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 681 | #define MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 IOMUX_PAD(0x4E8, 0x198, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 682 | #define MX53_PAD_EIM_EB1__IPU_CSI1_D_10 IOMUX_PAD(0x4E8, 0x198, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 683 | #define MX53_PAD_EIM_EB1__SRC_BT_CFG2_6 IOMUX_PAD(0x4E8, 0x198, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 684 | #define MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 IOMUX_PAD(0x4EC, 0x19C, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 685 | #define MX53_PAD_EIM_DA0__GPIO3_0 IOMUX_PAD(0x4EC, 0x19C, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 686 | #define MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 IOMUX_PAD(0x4EC, 0x19C, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 687 | #define MX53_PAD_EIM_DA0__IPU_CSI1_D_9 IOMUX_PAD(0x4EC, 0x19C, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 688 | #define MX53_PAD_EIM_DA0__SRC_BT_CFG2_5 IOMUX_PAD(0x4EC, 0x19C, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 689 | #define MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 IOMUX_PAD(0x4F0, 0x1A0, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 690 | #define MX53_PAD_EIM_DA1__GPIO3_1 IOMUX_PAD(0x4F0, 0x1A0, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 691 | #define MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 IOMUX_PAD(0x4F0, 0x1A0, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 692 | #define MX53_PAD_EIM_DA1__IPU_CSI1_D_8 IOMUX_PAD(0x4F0, 0x1A0, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 693 | #define MX53_PAD_EIM_DA1__SRC_BT_CFG2_4 IOMUX_PAD(0x4F0, 0x1A0, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 694 | #define MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 IOMUX_PAD(0x4F4, 0x1A4, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 695 | #define MX53_PAD_EIM_DA2__GPIO3_2 IOMUX_PAD(0x4F4, 0x1A4, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 696 | #define MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 IOMUX_PAD(0x4F4, 0x1A4, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 697 | #define MX53_PAD_EIM_DA2__IPU_CSI1_D_7 IOMUX_PAD(0x4F4, 0x1A4, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 698 | #define MX53_PAD_EIM_DA2__SRC_BT_CFG2_3 IOMUX_PAD(0x4F4, 0x1A4, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 699 | #define MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 IOMUX_PAD(0x4F8, 0x1A8, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 700 | #define MX53_PAD_EIM_DA3__GPIO3_3 IOMUX_PAD(0x4F8, 0x1A8, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 701 | #define MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 IOMUX_PAD(0x4F8, 0x1A8, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 702 | #define MX53_PAD_EIM_DA3__IPU_CSI1_D_6 IOMUX_PAD(0x4F8, 0x1A8, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 703 | #define MX53_PAD_EIM_DA3__SRC_BT_CFG2_2 IOMUX_PAD(0x4F8, 0x1A8, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 704 | #define MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 IOMUX_PAD(0x4FC, 0x1AC, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 705 | #define MX53_PAD_EIM_DA4__GPIO3_4 IOMUX_PAD(0x4FC, 0x1AC, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 706 | #define MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 IOMUX_PAD(0x4FC, 0x1AC, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 707 | #define MX53_PAD_EIM_DA4__IPU_CSI1_D_5 IOMUX_PAD(0x4FC, 0x1AC, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 708 | #define MX53_PAD_EIM_DA4__SRC_BT_CFG3_7 IOMUX_PAD(0x4FC, 0x1AC, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 709 | #define MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 IOMUX_PAD(0x500, 0x1B0, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 710 | #define MX53_PAD_EIM_DA5__GPIO3_5 IOMUX_PAD(0x500, 0x1B0, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 711 | #define MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 IOMUX_PAD(0x500, 0x1B0, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 712 | #define MX53_PAD_EIM_DA5__IPU_CSI1_D_4 IOMUX_PAD(0x500, 0x1B0, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 713 | #define MX53_PAD_EIM_DA5__SRC_BT_CFG3_6 IOMUX_PAD(0x500, 0x1B0, 7 | IOMUX_CONFIG_SION, __NA_, 0, NO_PAD_CTRL) | ||
| 714 | #define MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 IOMUX_PAD(0x504, 0x1B4, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 715 | #define MX53_PAD_EIM_DA6__GPIO3_6 IOMUX_PAD(0x504, 0x1B4, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 716 | #define MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 IOMUX_PAD(0x504, 0x1B4, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 717 | #define MX53_PAD_EIM_DA6__IPU_CSI1_D_3 IOMUX_PAD(0x504, 0x1B4, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 718 | #define MX53_PAD_EIM_DA6__SRC_BT_CFG3_5 IOMUX_PAD(0x504, 0x1B4, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 719 | #define MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 IOMUX_PAD(0x508, 0x1B8, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 720 | #define MX53_PAD_EIM_DA7__GPIO3_7 IOMUX_PAD(0x508, 0x1B8, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 721 | #define MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 IOMUX_PAD(0x508, 0x1B8, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 722 | #define MX53_PAD_EIM_DA7__IPU_CSI1_D_2 IOMUX_PAD(0x508, 0x1B8, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 723 | #define MX53_PAD_EIM_DA7__SRC_BT_CFG3_4 IOMUX_PAD(0x508, 0x1B8, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 724 | #define MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8 IOMUX_PAD(0x50C, 0x1BC, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 725 | #define MX53_PAD_EIM_DA8__GPIO3_8 IOMUX_PAD(0x50C, 0x1BC, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 726 | #define MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 IOMUX_PAD(0x50C, 0x1BC, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 727 | #define MX53_PAD_EIM_DA8__IPU_CSI1_D_1 IOMUX_PAD(0x50C, 0x1BC, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 728 | #define MX53_PAD_EIM_DA8__SRC_BT_CFG3_3 IOMUX_PAD(0x50C, 0x1BC, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 729 | #define MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9 IOMUX_PAD(0x510, 0x1C0, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 730 | #define MX53_PAD_EIM_DA9__GPIO3_9 IOMUX_PAD(0x510, 0x1C0, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 731 | #define MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 IOMUX_PAD(0x510, 0x1C0, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 732 | #define MX53_PAD_EIM_DA9__IPU_CSI1_D_0 IOMUX_PAD(0x510, 0x1C0, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 733 | #define MX53_PAD_EIM_DA9__SRC_BT_CFG3_2 IOMUX_PAD(0x510, 0x1C0, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 734 | #define MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10 IOMUX_PAD(0x514, 0x1C4, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 735 | #define MX53_PAD_EIM_DA10__GPIO3_10 IOMUX_PAD(0x514, 0x1C4, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 736 | #define MX53_PAD_EIM_DA10__IPU_DI1_PIN15 IOMUX_PAD(0x514, 0x1C4, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 737 | #define MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN IOMUX_PAD(0x514, 0x1C4, 4, 0x834, 1, NO_PAD_CTRL) | ||
| 738 | #define MX53_PAD_EIM_DA10__SRC_BT_CFG3_1 IOMUX_PAD(0x514, 0x1C4, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 739 | #define MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11 IOMUX_PAD(0x518, 0x1C8, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 740 | #define MX53_PAD_EIM_DA11__GPIO3_11 IOMUX_PAD(0x518, 0x1C8, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 741 | #define MX53_PAD_EIM_DA11__IPU_DI1_PIN2 IOMUX_PAD(0x518, 0x1C8, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 742 | #define MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC IOMUX_PAD(0x518, 0x1C8, 4, 0x838, 1, NO_PAD_CTRL) | ||
| 743 | #define MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12 IOMUX_PAD(0x51C, 0x1CC, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 744 | #define MX53_PAD_EIM_DA12__GPIO3_12 IOMUX_PAD(0x51C, 0x1CC, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 745 | #define MX53_PAD_EIM_DA12__IPU_DI1_PIN3 IOMUX_PAD(0x51C, 0x1CC, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 746 | #define MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC IOMUX_PAD(0x51C, 0x1CC, 4, 0x83C, 1, NO_PAD_CTRL) | ||
| 747 | #define MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13 IOMUX_PAD(0x520, 0x1D0, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 748 | #define MX53_PAD_EIM_DA13__GPIO3_13 IOMUX_PAD(0x520, 0x1D0, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 749 | #define MX53_PAD_EIM_DA13__IPU_DI1_D0_CS IOMUX_PAD(0x520, 0x1D0, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 750 | #define MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK IOMUX_PAD(0x520, 0x1D0, 4, 0x76C, 1, NO_PAD_CTRL) | ||
| 751 | #define MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14 IOMUX_PAD(0x524, 0x1D4, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 752 | #define MX53_PAD_EIM_DA14__GPIO3_14 IOMUX_PAD(0x524, 0x1D4, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 753 | #define MX53_PAD_EIM_DA14__IPU_DI1_D1_CS IOMUX_PAD(0x524, 0x1D4, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 754 | #define MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK IOMUX_PAD(0x524, 0x1D4, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 755 | #define MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15 IOMUX_PAD(0x528, 0x1D8, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 756 | #define MX53_PAD_EIM_DA15__GPIO3_15 IOMUX_PAD(0x528, 0x1D8, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 757 | #define MX53_PAD_EIM_DA15__IPU_DI1_PIN1 IOMUX_PAD(0x528, 0x1D8, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 758 | #define MX53_PAD_EIM_DA15__IPU_DI1_PIN4 IOMUX_PAD(0x528, 0x1D8, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 759 | #define MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B IOMUX_PAD(0x52C, 0x1DC, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 760 | #define MX53_PAD_NANDF_WE_B__GPIO6_12 IOMUX_PAD(0x52C, 0x1DC, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 761 | #define MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B IOMUX_PAD(0x530, 0x1E0, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 762 | #define MX53_PAD_NANDF_RE_B__GPIO6_13 IOMUX_PAD(0x530, 0x1E0, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 763 | #define MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT IOMUX_PAD(0x534, 0x1E4, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 764 | #define MX53_PAD_EIM_WAIT__GPIO5_0 IOMUX_PAD(0x534, 0x1E4, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 765 | #define MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B IOMUX_PAD(0x534, 0x1E4, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 766 | #define MX53_PAD_LVDS1_TX3_P__GPIO6_22 IOMUX_PAD(__NA_, 0x1EC, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 767 | #define MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 IOMUX_PAD(__NA_, 0x1EC, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 768 | #define MX53_PAD_LVDS1_TX2_P__GPIO6_24 IOMUX_PAD(__NA_, 0x1F0, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 769 | #define MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 IOMUX_PAD(__NA_, 0x1F0, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 770 | #define MX53_PAD_LVDS1_CLK_P__GPIO6_26 IOMUX_PAD(__NA_, 0x1F4, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 771 | #define MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK IOMUX_PAD(__NA_, 0x1F4, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 772 | #define MX53_PAD_LVDS1_TX1_P__GPIO6_28 IOMUX_PAD(__NA_, 0x1F8, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 773 | #define MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 IOMUX_PAD(__NA_, 0x1F8, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 774 | #define MX53_PAD_LVDS1_TX0_P__GPIO6_30 IOMUX_PAD(__NA_, 0x1FC, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 775 | #define MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 IOMUX_PAD(__NA_, 0x1FC, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 776 | #define MX53_PAD_LVDS0_TX3_P__GPIO7_22 IOMUX_PAD(__NA_, 0x200, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 777 | #define MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 IOMUX_PAD(__NA_, 0x200, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 778 | #define MX53_PAD_LVDS0_CLK_P__GPIO7_24 IOMUX_PAD(__NA_, 0x204, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 779 | #define MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK IOMUX_PAD(__NA_, 0x204, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 780 | #define MX53_PAD_LVDS0_TX2_P__GPIO7_26 IOMUX_PAD(__NA_, 0x208, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 781 | #define MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 IOMUX_PAD(__NA_, 0x208, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 782 | #define MX53_PAD_LVDS0_TX1_P__GPIO7_28 IOMUX_PAD(__NA_, 0x20C, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 783 | #define MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 IOMUX_PAD(__NA_, 0x20C, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 784 | #define MX53_PAD_LVDS0_TX0_P__GPIO7_30 IOMUX_PAD(__NA_, 0x210, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 785 | #define MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 IOMUX_PAD(__NA_, 0x210, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 786 | #define MX53_PAD_GPIO_10__GPIO4_0 IOMUX_PAD(0x540, 0x214, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 787 | #define MX53_PAD_GPIO_10__OSC32k_32K_OUT IOMUX_PAD(0x540, 0x214, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 788 | #define MX53_PAD_GPIO_11__GPIO4_1 IOMUX_PAD(0x544, 0x218, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 789 | #define MX53_PAD_GPIO_12__GPIO4_2 IOMUX_PAD(0x548, 0x21C, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 790 | #define MX53_PAD_GPIO_13__GPIO4_3 IOMUX_PAD(0x54C, 0x220, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 791 | #define MX53_PAD_GPIO_14__GPIO4_4 IOMUX_PAD(0x550, 0x224, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 792 | #define MX53_PAD_NANDF_CLE__EMI_NANDF_CLE IOMUX_PAD(0x5A0, 0x228, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 793 | #define MX53_PAD_NANDF_CLE__GPIO6_7 IOMUX_PAD(0x5A0, 0x228, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 794 | #define MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0 IOMUX_PAD(0x5A0, 0x228, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 795 | #define MX53_PAD_NANDF_ALE__EMI_NANDF_ALE IOMUX_PAD(0x5A4, 0x22C, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 796 | #define MX53_PAD_NANDF_ALE__GPIO6_8 IOMUX_PAD(0x5A4, 0x22C, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 797 | #define MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1 IOMUX_PAD(0x5A4, 0x22C, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 798 | #define MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B IOMUX_PAD(0x5A8, 0x230, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 799 | #define MX53_PAD_NANDF_WP_B__GPIO6_9 IOMUX_PAD(0x5A8, 0x230, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 800 | #define MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2 IOMUX_PAD(0x5A8, 0x230, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 801 | #define MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 IOMUX_PAD(0x5AC, 0x234, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 802 | #define MX53_PAD_NANDF_RB0__GPIO6_10 IOMUX_PAD(0x5AC, 0x234, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 803 | #define MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3 IOMUX_PAD(0x5AC, 0x234, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 804 | #define MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 IOMUX_PAD(0x5B0, 0x238, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 805 | #define MX53_PAD_NANDF_CS0__GPIO6_11 IOMUX_PAD(0x5B0, 0x238, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 806 | #define MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4 IOMUX_PAD(0x5B0, 0x238, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 807 | #define MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1 IOMUX_PAD(0x5B4, 0x23C, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 808 | #define MX53_PAD_NANDF_CS1__GPIO6_14 IOMUX_PAD(0x5B4, 0x23C, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 809 | #define MX53_PAD_NANDF_CS1__MLB_MLBCLK IOMUX_PAD(0x5B4, 0x23C, 6, 0x858, 0, NO_PAD_CTRL) | ||
| 810 | #define MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5 IOMUX_PAD(0x5B4, 0x23C, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 811 | #define MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2 IOMUX_PAD(0x5B8, 0x240, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 812 | #define MX53_PAD_NANDF_CS2__GPIO6_15 IOMUX_PAD(0x5B8, 0x240, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 813 | #define MX53_PAD_NANDF_CS2__IPU_SISG_0 IOMUX_PAD(0x5B8, 0x240, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 814 | #define MX53_PAD_NANDF_CS2__ESAI1_TX0 IOMUX_PAD(0x5B8, 0x240, 3, 0x7E4, 0, NO_PAD_CTRL) | ||
| 815 | #define MX53_PAD_NANDF_CS2__EMI_WEIM_CRE IOMUX_PAD(0x5B8, 0x240, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 816 | #define MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK IOMUX_PAD(0x5B8, 0x240, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 817 | #define MX53_PAD_NANDF_CS2__MLB_MLBSIG IOMUX_PAD(0x5B8, 0x240, 6, 0x860, 0, NO_PAD_CTRL) | ||
| 818 | #define MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6 IOMUX_PAD(0x5B8, 0x240, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 819 | #define MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3 IOMUX_PAD(0x5BC, 0x244, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 820 | #define MX53_PAD_NANDF_CS3__GPIO6_16 IOMUX_PAD(0x5BC, 0x244, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 821 | #define MX53_PAD_NANDF_CS3__IPU_SISG_1 IOMUX_PAD(0x5BC, 0x244, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 822 | #define MX53_PAD_NANDF_CS3__ESAI1_TX1 IOMUX_PAD(0x5BC, 0x244, 3, 0x7E8, 0, NO_PAD_CTRL) | ||
| 823 | #define MX53_PAD_NANDF_CS3__EMI_WEIM_A_26 IOMUX_PAD(0x5BC, 0x244, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 824 | #define MX53_PAD_NANDF_CS3__MLB_MLBDAT IOMUX_PAD(0x5BC, 0x244, 6, 0x85C, 0, NO_PAD_CTRL) | ||
| 825 | #define MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7 IOMUX_PAD(0x5BC, 0x244, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 826 | #define MX53_PAD_FEC_MDIO__FEC_MDIO IOMUX_PAD(0x5C4, 0x248, 0, 0x804, 1, NO_PAD_CTRL) | ||
| 827 | #define MX53_PAD_FEC_MDIO__GPIO1_22 IOMUX_PAD(0x5C4, 0x248, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 828 | #define MX53_PAD_FEC_MDIO__ESAI1_SCKR IOMUX_PAD(0x5C4, 0x248, 2, 0x7DC, 0, NO_PAD_CTRL) | ||
| 829 | #define MX53_PAD_FEC_MDIO__FEC_COL IOMUX_PAD(0x5C4, 0x248, 3, 0x800, 1, NO_PAD_CTRL) | ||
| 830 | #define MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2 IOMUX_PAD(0x5C4, 0x248, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 831 | #define MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3 IOMUX_PAD(0x5C4, 0x248, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 832 | #define MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49 IOMUX_PAD(0x5C4, 0x248, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 833 | #define MX53_PAD_FEC_REF_CLK__FEC_TX_CLK IOMUX_PAD(0x5C8, 0x24C, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 834 | #define MX53_PAD_FEC_REF_CLK__GPIO1_23 IOMUX_PAD(0x5C8, 0x24C, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 835 | #define MX53_PAD_FEC_REF_CLK__ESAI1_FSR IOMUX_PAD(0x5C8, 0x24C, 2, 0x7CC, 0, NO_PAD_CTRL) | ||
| 836 | #define MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 IOMUX_PAD(0x5C8, 0x24C, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 837 | #define MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50 IOMUX_PAD(0x5C8, 0x24C, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 838 | #define MX53_PAD_FEC_RX_ER__FEC_RX_ER IOMUX_PAD(0x5CC, 0x250, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 839 | #define MX53_PAD_FEC_RX_ER__GPIO1_24 IOMUX_PAD(0x5CC, 0x250, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 840 | #define MX53_PAD_FEC_RX_ER__ESAI1_HCKR IOMUX_PAD(0x5CC, 0x250, 2, 0x7D4, 0, NO_PAD_CTRL) | ||
| 841 | #define MX53_PAD_FEC_RX_ER__FEC_RX_CLK IOMUX_PAD(0x5CC, 0x250, 3, 0x808, 1, NO_PAD_CTRL) | ||
| 842 | #define MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3 IOMUX_PAD(0x5CC, 0x250, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 843 | #define MX53_PAD_FEC_CRS_DV__FEC_RX_DV IOMUX_PAD(0x5D0, 0x254, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 844 | #define MX53_PAD_FEC_CRS_DV__GPIO1_25 IOMUX_PAD(0x5D0, 0x254, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 845 | #define MX53_PAD_FEC_CRS_DV__ESAI1_SCKT IOMUX_PAD(0x5D0, 0x254, 2, 0x7E0, 0, NO_PAD_CTRL) | ||
| 846 | #define MX53_PAD_FEC_RXD1__FEC_RDATA_1 IOMUX_PAD(0x5D4, 0x258, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 847 | #define MX53_PAD_FEC_RXD1__GPIO1_26 IOMUX_PAD(0x5D4, 0x258, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 848 | #define MX53_PAD_FEC_RXD1__ESAI1_FST IOMUX_PAD(0x5D4, 0x258, 2, 0x7D0, 0, NO_PAD_CTRL) | ||
| 849 | #define MX53_PAD_FEC_RXD1__MLB_MLBSIG IOMUX_PAD(0x5D4, 0x258, 3, 0x860, 1, NO_PAD_CTRL) | ||
| 850 | #define MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1 IOMUX_PAD(0x5D4, 0x258, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 851 | #define MX53_PAD_FEC_RXD0__FEC_RDATA_0 IOMUX_PAD(0x5D8, 0x25C, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 852 | #define MX53_PAD_FEC_RXD0__GPIO1_27 IOMUX_PAD(0x5D8, 0x25C, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 853 | #define MX53_PAD_FEC_RXD0__ESAI1_HCKT IOMUX_PAD(0x5D8, 0x25C, 2, 0x7D8, 0, NO_PAD_CTRL) | ||
| 854 | #define MX53_PAD_FEC_RXD0__OSC32k_32K_OUT IOMUX_PAD(0x5D8, 0x25C, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 855 | #define MX53_PAD_FEC_TX_EN__FEC_TX_EN IOMUX_PAD(0x5DC, 0x260, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 856 | #define MX53_PAD_FEC_TX_EN__GPIO1_28 IOMUX_PAD(0x5DC, 0x260, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 857 | #define MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2 IOMUX_PAD(0x5DC, 0x260, 2, 0x7F0, 0, NO_PAD_CTRL) | ||
| 858 | #define MX53_PAD_FEC_TXD1__FEC_TDATA_1 IOMUX_PAD(0x5E0, 0x264, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 859 | #define MX53_PAD_FEC_TXD1__GPIO1_29 IOMUX_PAD(0x5E0, 0x264, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 860 | #define MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3 IOMUX_PAD(0x5E0, 0x264, 2, 0x7EC, 0, NO_PAD_CTRL) | ||
| 861 | #define MX53_PAD_FEC_TXD1__MLB_MLBCLK IOMUX_PAD(0x5E0, 0x264, 3, 0x858, 1, NO_PAD_CTRL) | ||
| 862 | #define MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK IOMUX_PAD(0x5E0, 0x264, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 863 | #define MX53_PAD_FEC_TXD0__FEC_TDATA_0 IOMUX_PAD(0x5E4, 0x268, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 864 | #define MX53_PAD_FEC_TXD0__GPIO1_30 IOMUX_PAD(0x5E4, 0x268, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 865 | #define MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1 IOMUX_PAD(0x5E4, 0x268, 2, 0x7F4, 0, NO_PAD_CTRL) | ||
| 866 | #define MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0 IOMUX_PAD(0x5E4, 0x268, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 867 | #define MX53_PAD_FEC_MDC__FEC_MDC IOMUX_PAD(0x5E8, 0x26C, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 868 | #define MX53_PAD_FEC_MDC__GPIO1_31 IOMUX_PAD(0x5E8, 0x26C, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 869 | #define MX53_PAD_FEC_MDC__ESAI1_TX5_RX0 IOMUX_PAD(0x5E8, 0x26C, 2, 0x7F8, 0, NO_PAD_CTRL) | ||
| 870 | #define MX53_PAD_FEC_MDC__MLB_MLBDAT IOMUX_PAD(0x5E8, 0x26C, 3, 0x85C, 1, NO_PAD_CTRL) | ||
| 871 | #define MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG IOMUX_PAD(0x5E8, 0x26C, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 872 | #define MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1 IOMUX_PAD(0x5E8, 0x26C, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 873 | #define MX53_PAD_PATA_DIOW__PATA_DIOW IOMUX_PAD(0x5F0, 0x270, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 874 | #define MX53_PAD_PATA_DIOW__GPIO6_17 IOMUX_PAD(0x5F0, 0x270, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 875 | #define MX53_PAD_PATA_DIOW__UART1_TXD_MUX IOMUX_PAD(0x5F0, 0x270, 3, __NA_, 0, MX53_UART_PAD_CTRL) | ||
| 876 | #define MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2 IOMUX_PAD(0x5F0, 0x270, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 877 | #define MX53_PAD_PATA_DMACK__PATA_DMACK IOMUX_PAD(0x5F4, 0x274, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 878 | #define MX53_PAD_PATA_DMACK__GPIO6_18 IOMUX_PAD(0x5F4, 0x274, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 879 | #define MX53_PAD_PATA_DMACK__UART1_RXD_MUX IOMUX_PAD(0x5F4, 0x274, 3, 0x878, 3, MX53_UART_PAD_CTRL) | ||
| 880 | #define MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3 IOMUX_PAD(0x5F4, 0x274, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 881 | #define MX53_PAD_PATA_DMARQ__PATA_DMARQ IOMUX_PAD(0x5F8, 0x278, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 882 | #define MX53_PAD_PATA_DMARQ__GPIO7_0 IOMUX_PAD(0x5F8, 0x278, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 883 | #define MX53_PAD_PATA_DMARQ__UART2_TXD_MUX IOMUX_PAD(0x5F8, 0x278, 3, __NA_, 0, MX53_UART_PAD_CTRL) | ||
| 884 | #define MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0 IOMUX_PAD(0x5F8, 0x278, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 885 | #define MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4 IOMUX_PAD(0x5F8, 0x278, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 886 | #define MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN IOMUX_PAD(0x5FC, 0x27C, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 887 | #define MX53_PAD_PATA_BUFFER_EN__GPIO7_1 IOMUX_PAD(0x5FC, 0x27C, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 888 | #define MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX IOMUX_PAD(0x5FC, 0x27C, 3, 0x880, 3, MX53_UART_PAD_CTRL) | ||
| 889 | #define MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1 IOMUX_PAD(0x5FC, 0x27C, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 890 | #define MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5 IOMUX_PAD(0x5FC, 0x27C, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 891 | #define MX53_PAD_PATA_INTRQ__PATA_INTRQ IOMUX_PAD(0x600, 0x280, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 892 | #define MX53_PAD_PATA_INTRQ__GPIO7_2 IOMUX_PAD(0x600, 0x280, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 893 | #define MX53_PAD_PATA_INTRQ__UART2_CTS IOMUX_PAD(0x600, 0x280, 3, __NA_, 0, MX53_UART_PAD_CTRL) | ||
| 894 | #define MX53_PAD_PATA_INTRQ__CAN1_TXCAN IOMUX_PAD(0x600, 0x280, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 895 | #define MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2 IOMUX_PAD(0x600, 0x280, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 896 | #define MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6 IOMUX_PAD(0x600, 0x280, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 897 | #define MX53_PAD_PATA_DIOR__PATA_DIOR IOMUX_PAD(0x604, 0x284, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 898 | #define MX53_PAD_PATA_DIOR__GPIO7_3 IOMUX_PAD(0x604, 0x284, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 899 | #define MX53_PAD_PATA_DIOR__UART2_RTS IOMUX_PAD(0x604, 0x284, 3, 0x87C, 3, MX53_UART_PAD_CTRL) | ||
| 900 | #define MX53_PAD_PATA_DIOR__CAN1_RXCAN IOMUX_PAD(0x604, 0x284, 4, 0x760, 1, NO_PAD_CTRL) | ||
| 901 | #define MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7 IOMUX_PAD(0x604, 0x284, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 902 | #define MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B IOMUX_PAD(0x608, 0x288, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 903 | #define MX53_PAD_PATA_RESET_B__GPIO7_4 IOMUX_PAD(0x608, 0x288, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 904 | #define MX53_PAD_PATA_RESET_B__ESDHC3_CMD IOMUX_PAD(0x608, 0x288, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 905 | #define MX53_PAD_PATA_RESET_B__UART1_CTS IOMUX_PAD(0x608, 0x288, 3, __NA_, 0, MX53_UART_PAD_CTRL) | ||
| 906 | #define MX53_PAD_PATA_RESET_B__CAN2_TXCAN IOMUX_PAD(0x608, 0x288, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 907 | #define MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0 IOMUX_PAD(0x608, 0x288, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 908 | #define MX53_PAD_PATA_IORDY__PATA_IORDY IOMUX_PAD(0x60C, 0x28C, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 909 | #define MX53_PAD_PATA_IORDY__GPIO7_5 IOMUX_PAD(0x60C, 0x28C, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 910 | #define MX53_PAD_PATA_IORDY__ESDHC3_CLK IOMUX_PAD(0x60C, 0x28C, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 911 | #define MX53_PAD_PATA_IORDY__UART1_RTS IOMUX_PAD(0x60C, 0x28C, 3, 0x874, 3, MX53_UART_PAD_CTRL) | ||
| 912 | #define MX53_PAD_PATA_IORDY__CAN2_RXCAN IOMUX_PAD(0x60C, 0x28C, 4, 0x764, 1, NO_PAD_CTRL) | ||
| 913 | #define MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1 IOMUX_PAD(0x60C, 0x28C, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 914 | #define MX53_PAD_PATA_DA_0__PATA_DA_0 IOMUX_PAD(0x610, 0x290, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 915 | #define MX53_PAD_PATA_DA_0__GPIO7_6 IOMUX_PAD(0x610, 0x290, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 916 | #define MX53_PAD_PATA_DA_0__ESDHC3_RST IOMUX_PAD(0x610, 0x290, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 917 | #define MX53_PAD_PATA_DA_0__OWIRE_LINE IOMUX_PAD(0x610, 0x290, 4, 0x864, 0, NO_PAD_CTRL) | ||
| 918 | #define MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2 IOMUX_PAD(0x610, 0x290, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 919 | #define MX53_PAD_PATA_DA_1__PATA_DA_1 IOMUX_PAD(0x614, 0x294, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 920 | #define MX53_PAD_PATA_DA_1__GPIO7_7 IOMUX_PAD(0x614, 0x294, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 921 | #define MX53_PAD_PATA_DA_1__ESDHC4_CMD IOMUX_PAD(0x614, 0x294, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 922 | #define MX53_PAD_PATA_DA_1__UART3_CTS IOMUX_PAD(0x614, 0x294, 4, __NA_, 0, MX53_UART_PAD_CTRL) | ||
| 923 | #define MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3 IOMUX_PAD(0x614, 0x294, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 924 | #define MX53_PAD_PATA_DA_2__PATA_DA_2 IOMUX_PAD(0x618, 0x298, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 925 | #define MX53_PAD_PATA_DA_2__GPIO7_8 IOMUX_PAD(0x618, 0x298, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 926 | #define MX53_PAD_PATA_DA_2__ESDHC4_CLK IOMUX_PAD(0x618, 0x298, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 927 | #define MX53_PAD_PATA_DA_2__UART3_RTS IOMUX_PAD(0x618, 0x298, 4, 0x884, 5, MX53_UART_PAD_CTRL) | ||
| 928 | #define MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4 IOMUX_PAD(0x618, 0x298, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 929 | #define MX53_PAD_PATA_CS_0__PATA_CS_0 IOMUX_PAD(0x61C, 0x29C, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 930 | #define MX53_PAD_PATA_CS_0__GPIO7_9 IOMUX_PAD(0x61C, 0x29C, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 931 | #define MX53_PAD_PATA_CS_0__UART3_TXD_MUX IOMUX_PAD(0x61C, 0x29C, 4, __NA_, 0, MX53_UART_PAD_CTRL) | ||
| 932 | #define MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5 IOMUX_PAD(0x61C, 0x29C, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 933 | #define MX53_PAD_PATA_CS_1__PATA_CS_1 IOMUX_PAD(0x620, 0x2A0, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 934 | #define MX53_PAD_PATA_CS_1__GPIO7_10 IOMUX_PAD(0x620, 0x2A0, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 935 | #define MX53_PAD_PATA_CS_1__UART3_RXD_MUX IOMUX_PAD(0x620, 0x2A0, 4, 0x888, 3, MX53_UART_PAD_CTRL) | ||
| 936 | #define MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6 IOMUX_PAD(0x620, 0x2A0, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 937 | #define MX53_PAD_PATA_DATA0__PATA_DATA_0 IOMUX_PAD(0x628, 0x2A4, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 938 | #define MX53_PAD_PATA_DATA0__GPIO2_0 IOMUX_PAD(0x628, 0x2A4, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 939 | #define MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 IOMUX_PAD(0x628, 0x2A4, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 940 | #define MX53_PAD_PATA_DATA0__ESDHC3_DAT4 IOMUX_PAD(0x628, 0x2A4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 941 | #define MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0 IOMUX_PAD(0x628, 0x2A4, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 942 | #define MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0 IOMUX_PAD(0x628, 0x2A4, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 943 | #define MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7 IOMUX_PAD(0x628, 0x2A4, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 944 | #define MX53_PAD_PATA_DATA1__PATA_DATA_1 IOMUX_PAD(0x62C, 0x2A8, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 945 | #define MX53_PAD_PATA_DATA1__GPIO2_1 IOMUX_PAD(0x62C, 0x2A8, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 946 | #define MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 IOMUX_PAD(0x62C, 0x2A8, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 947 | #define MX53_PAD_PATA_DATA1__ESDHC3_DAT5 IOMUX_PAD(0x62C, 0x2A8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 948 | #define MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1 IOMUX_PAD(0x62C, 0x2A8, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 949 | #define MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1 IOMUX_PAD(0x62C, 0x2A8, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 950 | #define MX53_PAD_PATA_DATA2__PATA_DATA_2 IOMUX_PAD(0x630, 0x2AC, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 951 | #define MX53_PAD_PATA_DATA2__GPIO2_2 IOMUX_PAD(0x630, 0x2AC, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 952 | #define MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 IOMUX_PAD(0x630, 0x2AC, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 953 | #define MX53_PAD_PATA_DATA2__ESDHC3_DAT6 IOMUX_PAD(0x630, 0x2AC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 954 | #define MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2 IOMUX_PAD(0x630, 0x2AC, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 955 | #define MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2 IOMUX_PAD(0x630, 0x2AC, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 956 | #define MX53_PAD_PATA_DATA3__PATA_DATA_3 IOMUX_PAD(0x634, 0x2B0, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 957 | #define MX53_PAD_PATA_DATA3__GPIO2_3 IOMUX_PAD(0x634, 0x2B0, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 958 | #define MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 IOMUX_PAD(0x634, 0x2B0, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 959 | #define MX53_PAD_PATA_DATA3__ESDHC3_DAT7 IOMUX_PAD(0x634, 0x2B0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 960 | #define MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3 IOMUX_PAD(0x634, 0x2B0, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 961 | #define MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3 IOMUX_PAD(0x634, 0x2B0, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 962 | #define MX53_PAD_PATA_DATA4__PATA_DATA_4 IOMUX_PAD(0x638, 0x2B4, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 963 | #define MX53_PAD_PATA_DATA4__GPIO2_4 IOMUX_PAD(0x638, 0x2B4, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 964 | #define MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 IOMUX_PAD(0x638, 0x2B4, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 965 | #define MX53_PAD_PATA_DATA4__ESDHC4_DAT4 IOMUX_PAD(0x638, 0x2B4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 966 | #define MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4 IOMUX_PAD(0x638, 0x2B4, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 967 | #define MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4 IOMUX_PAD(0x638, 0x2B4, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 968 | #define MX53_PAD_PATA_DATA5__PATA_DATA_5 IOMUX_PAD(0x63C, 0x2B8, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 969 | #define MX53_PAD_PATA_DATA5__GPIO2_5 IOMUX_PAD(0x63C, 0x2B8, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 970 | #define MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 IOMUX_PAD(0x63C, 0x2B8, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 971 | #define MX53_PAD_PATA_DATA5__ESDHC4_DAT5 IOMUX_PAD(0x63C, 0x2B8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 972 | #define MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5 IOMUX_PAD(0x63C, 0x2B8, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 973 | #define MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5 IOMUX_PAD(0x63C, 0x2B8, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 974 | #define MX53_PAD_PATA_DATA6__PATA_DATA_6 IOMUX_PAD(0x640, 0x2BC, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 975 | #define MX53_PAD_PATA_DATA6__GPIO2_6 IOMUX_PAD(0x640, 0x2BC, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 976 | #define MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 IOMUX_PAD(0x640, 0x2BC, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 977 | #define MX53_PAD_PATA_DATA6__ESDHC4_DAT6 IOMUX_PAD(0x640, 0x2BC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 978 | #define MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6 IOMUX_PAD(0x640, 0x2BC, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 979 | #define MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6 IOMUX_PAD(0x640, 0x2BC, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 980 | #define MX53_PAD_PATA_DATA7__PATA_DATA_7 IOMUX_PAD(0x644, 0x2C0, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 981 | #define MX53_PAD_PATA_DATA7__GPIO2_7 IOMUX_PAD(0x644, 0x2C0, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 982 | #define MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 IOMUX_PAD(0x644, 0x2C0, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 983 | #define MX53_PAD_PATA_DATA7__ESDHC4_DAT7 IOMUX_PAD(0x644, 0x2C0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 984 | #define MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7 IOMUX_PAD(0x644, 0x2C0, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 985 | #define MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7 IOMUX_PAD(0x644, 0x2C0, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 986 | #define MX53_PAD_PATA_DATA8__PATA_DATA_8 IOMUX_PAD(0x648, 0x2C4, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 987 | #define MX53_PAD_PATA_DATA8__GPIO2_8 IOMUX_PAD(0x648, 0x2C4, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 988 | #define MX53_PAD_PATA_DATA8__ESDHC1_DAT4 IOMUX_PAD(0x648, 0x2C4, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 989 | #define MX53_PAD_PATA_DATA8__EMI_NANDF_D_8 IOMUX_PAD(0x648, 0x2C4, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 990 | #define MX53_PAD_PATA_DATA8__ESDHC3_DAT0 IOMUX_PAD(0x648, 0x2C4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 991 | #define MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8 IOMUX_PAD(0x648, 0x2C4, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 992 | #define MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8 IOMUX_PAD(0x648, 0x2C4, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 993 | #define MX53_PAD_PATA_DATA9__PATA_DATA_9 IOMUX_PAD(0x64C, 0x2C8, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 994 | #define MX53_PAD_PATA_DATA9__GPIO2_9 IOMUX_PAD(0x64C, 0x2C8, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 995 | #define MX53_PAD_PATA_DATA9__ESDHC1_DAT5 IOMUX_PAD(0x64C, 0x2C8, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 996 | #define MX53_PAD_PATA_DATA9__EMI_NANDF_D_9 IOMUX_PAD(0x64C, 0x2C8, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 997 | #define MX53_PAD_PATA_DATA9__ESDHC3_DAT1 IOMUX_PAD(0x64C, 0x2C8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 998 | #define MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9 IOMUX_PAD(0x64C, 0x2C8, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 999 | #define MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9 IOMUX_PAD(0x64C, 0x2C8, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 1000 | #define MX53_PAD_PATA_DATA10__PATA_DATA_10 IOMUX_PAD(0x650, 0x2CC, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 1001 | #define MX53_PAD_PATA_DATA10__GPIO2_10 IOMUX_PAD(0x650, 0x2CC, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 1002 | #define MX53_PAD_PATA_DATA10__ESDHC1_DAT6 IOMUX_PAD(0x650, 0x2CC, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 1003 | #define MX53_PAD_PATA_DATA10__EMI_NANDF_D_10 IOMUX_PAD(0x650, 0x2CC, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 1004 | #define MX53_PAD_PATA_DATA10__ESDHC3_DAT2 IOMUX_PAD(0x650, 0x2CC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 1005 | #define MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10 IOMUX_PAD(0x650, 0x2CC, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 1006 | #define MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10 IOMUX_PAD(0x650, 0x2CC, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 1007 | #define MX53_PAD_PATA_DATA11__PATA_DATA_11 IOMUX_PAD(0x654, 0x2D0, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 1008 | #define MX53_PAD_PATA_DATA11__GPIO2_11 IOMUX_PAD(0x654, 0x2D0, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 1009 | #define MX53_PAD_PATA_DATA11__ESDHC1_DAT7 IOMUX_PAD(0x654, 0x2D0, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 1010 | #define MX53_PAD_PATA_DATA11__EMI_NANDF_D_11 IOMUX_PAD(0x654, 0x2D0, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 1011 | #define MX53_PAD_PATA_DATA11__ESDHC3_DAT3 IOMUX_PAD(0x654, 0x2D0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 1012 | #define MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11 IOMUX_PAD(0x654, 0x2D0, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 1013 | #define MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11 IOMUX_PAD(0x654, 0x2D0, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 1014 | #define MX53_PAD_PATA_DATA12__PATA_DATA_12 IOMUX_PAD(0x658, 0x2D4, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 1015 | #define MX53_PAD_PATA_DATA12__GPIO2_12 IOMUX_PAD(0x658, 0x2D4, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 1016 | #define MX53_PAD_PATA_DATA12__ESDHC2_DAT4 IOMUX_PAD(0x658, 0x2D4, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 1017 | #define MX53_PAD_PATA_DATA12__EMI_NANDF_D_12 IOMUX_PAD(0x658, 0x2D4, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 1018 | #define MX53_PAD_PATA_DATA12__ESDHC4_DAT0 IOMUX_PAD(0x658, 0x2D4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 1019 | #define MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12 IOMUX_PAD(0x658, 0x2D4, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 1020 | #define MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12 IOMUX_PAD(0x658, 0x2D4, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 1021 | #define MX53_PAD_PATA_DATA13__PATA_DATA_13 IOMUX_PAD(0x65C, 0x2D8, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 1022 | #define MX53_PAD_PATA_DATA13__GPIO2_13 IOMUX_PAD(0x65C, 0x2D8, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 1023 | #define MX53_PAD_PATA_DATA13__ESDHC2_DAT5 IOMUX_PAD(0x65C, 0x2D8, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 1024 | #define MX53_PAD_PATA_DATA13__EMI_NANDF_D_13 IOMUX_PAD(0x65C, 0x2D8, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 1025 | #define MX53_PAD_PATA_DATA13__ESDHC4_DAT1 IOMUX_PAD(0x65C, 0x2D8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 1026 | #define MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13 IOMUX_PAD(0x65C, 0x2D8, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 1027 | #define MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13 IOMUX_PAD(0x65C, 0x2D8, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 1028 | #define MX53_PAD_PATA_DATA14__PATA_DATA_14 IOMUX_PAD(0x660, 0x2DC, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 1029 | #define MX53_PAD_PATA_DATA14__GPIO2_14 IOMUX_PAD(0x660, 0x2DC, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 1030 | #define MX53_PAD_PATA_DATA14__ESDHC2_DAT6 IOMUX_PAD(0x660, 0x2DC, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 1031 | #define MX53_PAD_PATA_DATA14__EMI_NANDF_D_14 IOMUX_PAD(0x660, 0x2DC, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 1032 | #define MX53_PAD_PATA_DATA14__ESDHC4_DAT2 IOMUX_PAD(0x660, 0x2DC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 1033 | #define MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14 IOMUX_PAD(0x660, 0x2DC, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 1034 | #define MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14 IOMUX_PAD(0x660, 0x2DC, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 1035 | #define MX53_PAD_PATA_DATA15__PATA_DATA_15 IOMUX_PAD(0x664, 0x2E0, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 1036 | #define MX53_PAD_PATA_DATA15__GPIO2_15 IOMUX_PAD(0x664, 0x2E0, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 1037 | #define MX53_PAD_PATA_DATA15__ESDHC2_DAT7 IOMUX_PAD(0x664, 0x2E0, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 1038 | #define MX53_PAD_PATA_DATA15__EMI_NANDF_D_15 IOMUX_PAD(0x664, 0x2E0, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 1039 | #define MX53_PAD_PATA_DATA15__ESDHC4_DAT3 IOMUX_PAD(0x664, 0x2E0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 1040 | #define MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15 IOMUX_PAD(0x664, 0x2E0, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 1041 | #define MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15 IOMUX_PAD(0x664, 0x2E0, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 1042 | #define MX53_PAD_SD1_DATA0__ESDHC1_DAT0 IOMUX_PAD(0x66C, 0x2E4, 0, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 1043 | #define MX53_PAD_SD1_DATA0__GPIO1_16 IOMUX_PAD(0x66C, 0x2E4, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 1044 | #define MX53_PAD_SD1_DATA0__GPT_CAPIN1 IOMUX_PAD(0x66C, 0x2E4, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 1045 | #define MX53_PAD_SD1_DATA0__CSPI_MISO IOMUX_PAD(0x66C, 0x2E4, 5, 0x784, 2, NO_PAD_CTRL) | ||
| 1046 | #define MX53_PAD_SD1_DATA0__CCM_PLL3_BYP IOMUX_PAD(0x66C, 0x2E4, 7, 0x778, 0, NO_PAD_CTRL) | ||
| 1047 | #define MX53_PAD_SD1_DATA1__ESDHC1_DAT1 IOMUX_PAD(0x670, 0x2E8, 0, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 1048 | #define MX53_PAD_SD1_DATA1__GPIO1_17 IOMUX_PAD(0x670, 0x2E8, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 1049 | #define MX53_PAD_SD1_DATA1__GPT_CAPIN2 IOMUX_PAD(0x670, 0x2E8, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 1050 | #define MX53_PAD_SD1_DATA1__CSPI_SS0 IOMUX_PAD(0x670, 0x2E8, 5, 0x78C, 3, NO_PAD_CTRL) | ||
| 1051 | #define MX53_PAD_SD1_DATA1__CCM_PLL4_BYP IOMUX_PAD(0x670, 0x2E8, 7, 0x77C, 1, NO_PAD_CTRL) | ||
| 1052 | #define MX53_PAD_SD1_CMD__ESDHC1_CMD IOMUX_PAD(0x674, 0x2EC, 0 | IOMUX_CONFIG_SION, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 1053 | #define MX53_PAD_SD1_CMD__GPIO1_18 IOMUX_PAD(0x674, 0x2EC, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 1054 | #define MX53_PAD_SD1_CMD__GPT_CMPOUT1 IOMUX_PAD(0x674, 0x2EC, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 1055 | #define MX53_PAD_SD1_CMD__CSPI_MOSI IOMUX_PAD(0x674, 0x2EC, 5, 0x788, 2, NO_PAD_CTRL) | ||
| 1056 | #define MX53_PAD_SD1_CMD__CCM_PLL1_BYP IOMUX_PAD(0x674, 0x2EC, 7, 0x770, 0, NO_PAD_CTRL) | ||
| 1057 | #define MX53_PAD_SD1_DATA2__ESDHC1_DAT2 IOMUX_PAD(0x678, 0x2F0, 0, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 1058 | #define MX53_PAD_SD1_DATA2__GPIO1_19 IOMUX_PAD(0x678, 0x2F0, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 1059 | #define MX53_PAD_SD1_DATA2__GPT_CMPOUT2 IOMUX_PAD(0x678, 0x2F0, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 1060 | #define MX53_PAD_SD1_DATA2__PWM2_PWMO IOMUX_PAD(0x678, 0x2F0, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 1061 | #define MX53_PAD_SD1_DATA2__WDOG1_WDOG_B IOMUX_PAD(0x678, 0x2F0, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 1062 | #define MX53_PAD_SD1_DATA2__CSPI_SS1 IOMUX_PAD(0x678, 0x2F0, 5, 0x790, 2, NO_PAD_CTRL) | ||
| 1063 | #define MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB IOMUX_PAD(0x678, 0x2F0, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 1064 | #define MX53_PAD_SD1_DATA2__CCM_PLL2_BYP IOMUX_PAD(0x678, 0x2F0, 7, 0x774, 0, NO_PAD_CTRL) | ||
| 1065 | #define MX53_PAD_SD1_CLK__ESDHC1_CLK IOMUX_PAD(0x67C, 0x2F4, 0, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 1066 | #define MX53_PAD_SD1_CLK__GPIO1_20 IOMUX_PAD(0x67C, 0x2F4, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 1067 | #define MX53_PAD_SD1_CLK__OSC32k_32K_OUT IOMUX_PAD(0x67C, 0x2F4, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 1068 | #define MX53_PAD_SD1_CLK__GPT_CLKIN IOMUX_PAD(0x67C, 0x2F4, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 1069 | #define MX53_PAD_SD1_CLK__CSPI_SCLK IOMUX_PAD(0x67C, 0x2F4, 5, 0x780, 2, NO_PAD_CTRL) | ||
| 1070 | #define MX53_PAD_SD1_CLK__SATA_PHY_DTB_0 IOMUX_PAD(0x67C, 0x2F4, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 1071 | #define MX53_PAD_SD1_DATA3__ESDHC1_DAT3 IOMUX_PAD(0x680, 0x2F8, 0, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 1072 | #define MX53_PAD_SD1_DATA3__GPIO1_21 IOMUX_PAD(0x680, 0x2F8, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 1073 | #define MX53_PAD_SD1_DATA3__GPT_CMPOUT3 IOMUX_PAD(0x680, 0x2F8, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 1074 | #define MX53_PAD_SD1_DATA3__PWM1_PWMO IOMUX_PAD(0x680, 0x2F8, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 1075 | #define MX53_PAD_SD1_DATA3__WDOG2_WDOG_B IOMUX_PAD(0x680, 0x2F8, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 1076 | #define MX53_PAD_SD1_DATA3__CSPI_SS2 IOMUX_PAD(0x680, 0x2F8, 5, 0x794, 2, NO_PAD_CTRL) | ||
| 1077 | #define MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB IOMUX_PAD(0x680, 0x2F8, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 1078 | #define MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1 IOMUX_PAD(0x680, 0x2F8, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 1079 | #define MX53_PAD_SD2_CLK__ESDHC2_CLK IOMUX_PAD(0x688, 0x2FC, 0, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 1080 | #define MX53_PAD_SD2_CLK__GPIO1_10 IOMUX_PAD(0x688, 0x2FC, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 1081 | #define MX53_PAD_SD2_CLK__KPP_COL_5 IOMUX_PAD(0x688, 0x2FC, 2, 0x840, 2, NO_PAD_CTRL) | ||
| 1082 | #define MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS IOMUX_PAD(0x688, 0x2FC, 3, 0x73C, 1, NO_PAD_CTRL) | ||
| 1083 | #define MX53_PAD_SD2_CLK__CSPI_SCLK IOMUX_PAD(0x688, 0x2FC, 5, 0x780, 3, NO_PAD_CTRL) | ||
| 1084 | #define MX53_PAD_SD2_CLK__SCC_RANDOM_V IOMUX_PAD(0x688, 0x2FC, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 1085 | #define MX53_PAD_SD2_CMD__ESDHC2_CMD IOMUX_PAD(0x68C, 0x300, 0, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 1086 | #define MX53_PAD_SD2_CMD__GPIO1_11 IOMUX_PAD(0x68C, 0x300, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 1087 | #define MX53_PAD_SD2_CMD__KPP_ROW_5 IOMUX_PAD(0x68C, 0x300, 2, 0x84C, 1, NO_PAD_CTRL) | ||
| 1088 | #define MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC IOMUX_PAD(0x68C, 0x300, 3, 0x738, 1, NO_PAD_CTRL) | ||
| 1089 | #define MX53_PAD_SD2_CMD__CSPI_MOSI IOMUX_PAD(0x68C, 0x300, 5, 0x788, 3, NO_PAD_CTRL) | ||
| 1090 | #define MX53_PAD_SD2_CMD__SCC_RANDOM IOMUX_PAD(0x68C, 0x300, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 1091 | #define MX53_PAD_SD2_DATA3__ESDHC2_DAT3 IOMUX_PAD(0x690, 0x304, 0, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 1092 | #define MX53_PAD_SD2_DATA3__GPIO1_12 IOMUX_PAD(0x690, 0x304, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 1093 | #define MX53_PAD_SD2_DATA3__KPP_COL_6 IOMUX_PAD(0x690, 0x304, 2, 0x844, 1, NO_PAD_CTRL) | ||
| 1094 | #define MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC IOMUX_PAD(0x690, 0x304, 3, 0x740, 1, NO_PAD_CTRL) | ||
| 1095 | #define MX53_PAD_SD2_DATA3__CSPI_SS2 IOMUX_PAD(0x690, 0x304, 5, 0x794, 3, NO_PAD_CTRL) | ||
| 1096 | #define MX53_PAD_SD2_DATA3__SJC_DONE IOMUX_PAD(0x690, 0x304, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 1097 | #define MX53_PAD_SD2_DATA2__ESDHC2_DAT2 IOMUX_PAD(0x694, 0x308, 0, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 1098 | #define MX53_PAD_SD2_DATA2__GPIO1_13 IOMUX_PAD(0x694, 0x308, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 1099 | #define MX53_PAD_SD2_DATA2__KPP_ROW_6 IOMUX_PAD(0x694, 0x308, 2, 0x850, 1, NO_PAD_CTRL) | ||
| 1100 | #define MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD IOMUX_PAD(0x694, 0x308, 3, 0x734, 1, NO_PAD_CTRL) | ||
| 1101 | #define MX53_PAD_SD2_DATA2__CSPI_SS1 IOMUX_PAD(0x694, 0x308, 5, 0x790, 3, NO_PAD_CTRL) | ||
| 1102 | #define MX53_PAD_SD2_DATA2__SJC_FAIL IOMUX_PAD(0x694, 0x308, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 1103 | #define MX53_PAD_SD2_DATA1__ESDHC2_DAT1 IOMUX_PAD(0x698, 0x30C, 0, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 1104 | #define MX53_PAD_SD2_DATA1__GPIO1_14 IOMUX_PAD(0x698, 0x30C, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 1105 | #define MX53_PAD_SD2_DATA1__KPP_COL_7 IOMUX_PAD(0x698, 0x30C, 2, 0x848, 1, NO_PAD_CTRL) | ||
| 1106 | #define MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS IOMUX_PAD(0x698, 0x30C, 3, 0x744, 0, NO_PAD_CTRL) | ||
| 1107 | #define MX53_PAD_SD2_DATA1__CSPI_SS0 IOMUX_PAD(0x698, 0x30C, 5, 0x78C, 4, NO_PAD_CTRL) | ||
| 1108 | #define MX53_PAD_SD2_DATA1__RTIC_SEC_VIO IOMUX_PAD(0x698, 0x30C, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 1109 | #define MX53_PAD_SD2_DATA0__ESDHC2_DAT0 IOMUX_PAD(0x69C, 0x310, 0, __NA_, 0, MX53_SDHC_PAD_CTRL) | ||
| 1110 | #define MX53_PAD_SD2_DATA0__GPIO1_15 IOMUX_PAD(0x69C, 0x310, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 1111 | #define MX53_PAD_SD2_DATA0__KPP_ROW_7 IOMUX_PAD(0x69C, 0x310, 2, 0x854, 1, NO_PAD_CTRL) | ||
| 1112 | #define MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD IOMUX_PAD(0x69C, 0x310, 3, 0x730, 1, NO_PAD_CTRL) | ||
| 1113 | #define MX53_PAD_SD2_DATA0__CSPI_MISO IOMUX_PAD(0x69C, 0x310, 5, 0x784, 3, NO_PAD_CTRL) | ||
| 1114 | #define MX53_PAD_SD2_DATA0__RTIC_DONE_INT IOMUX_PAD(0x69C, 0x310, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 1115 | #define MX53_PAD_GPIO_0__CCM_CLKO IOMUX_PAD(0x6A4, 0x314, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 1116 | #define MX53_PAD_GPIO_0__GPIO1_0 IOMUX_PAD(0x6A4, 0x314, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 1117 | #define MX53_PAD_GPIO_0__KPP_COL_5 IOMUX_PAD(0x6A4, 0x314, 2, 0x840, 3, NO_PAD_CTRL) | ||
| 1118 | #define MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK IOMUX_PAD(0x6A4, 0x314, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 1119 | #define MX53_PAD_GPIO_0__EPIT1_EPITO IOMUX_PAD(0x6A4, 0x314, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 1120 | #define MX53_PAD_GPIO_0__SRTC_ALARM_DEB IOMUX_PAD(0x6A4, 0x314, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 1121 | #define MX53_PAD_GPIO_0__USBOH3_USBH1_PWR IOMUX_PAD(0x6A4, 0x314, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 1122 | #define MX53_PAD_GPIO_0__CSU_TD IOMUX_PAD(0x6A4, 0x314, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 1123 | #define MX53_PAD_GPIO_1__ESAI1_SCKR IOMUX_PAD(0x6A8, 0x318, 0, 0x7DC, 1, NO_PAD_CTRL) | ||
| 1124 | #define MX53_PAD_GPIO_1__GPIO1_1 IOMUX_PAD(0x6A8, 0x318, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 1125 | #define MX53_PAD_GPIO_1__KPP_ROW_5 IOMUX_PAD(0x6A8, 0x318, 2, 0x84C, 2, NO_PAD_CTRL) | ||
| 1126 | #define MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK IOMUX_PAD(0x6A8, 0x318, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 1127 | #define MX53_PAD_GPIO_1__PWM2_PWMO IOMUX_PAD(0x6A8, 0x318, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 1128 | #define MX53_PAD_GPIO_1__WDOG2_WDOG_B IOMUX_PAD(0x6A8, 0x318, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 1129 | #define MX53_PAD_GPIO_1__ESDHC1_CD IOMUX_PAD(0x6A8, 0x318, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 1130 | #define MX53_PAD_GPIO_1__SRC_TESTER_ACK IOMUX_PAD(0x6A8, 0x318, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 1131 | #define MX53_PAD_GPIO_9__ESAI1_FSR IOMUX_PAD(0x6AC, 0x31C, 0, 0x7CC, 1, NO_PAD_CTRL) | ||
| 1132 | #define MX53_PAD_GPIO_9__GPIO1_9 IOMUX_PAD(0x6AC, 0x31C, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 1133 | #define MX53_PAD_GPIO_9__KPP_COL_6 IOMUX_PAD(0x6AC, 0x31C, 2, 0x844, 2, NO_PAD_CTRL) | ||
| 1134 | #define MX53_PAD_GPIO_9__CCM_REF_EN_B IOMUX_PAD(0x6AC, 0x31C, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 1135 | #define MX53_PAD_GPIO_9__PWM1_PWMO IOMUX_PAD(0x6AC, 0x31C, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 1136 | #define MX53_PAD_GPIO_9__WDOG1_WDOG_B IOMUX_PAD(0x6AC, 0x31C, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 1137 | #define MX53_PAD_GPIO_9__ESDHC1_WP IOMUX_PAD(0x6AC, 0x31C, 6, 0x7FC, 1, NO_PAD_CTRL) | ||
| 1138 | #define MX53_PAD_GPIO_9__SCC_FAIL_STATE IOMUX_PAD(0x6AC, 0x31C, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 1139 | #define MX53_PAD_GPIO_3__ESAI1_HCKR IOMUX_PAD(0x6B0, 0x320, 0, 0x7D4, 1, NO_PAD_CTRL) | ||
| 1140 | #define MX53_PAD_GPIO_3__GPIO1_3 IOMUX_PAD(0x6B0, 0x320, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 1141 | #define MX53_PAD_GPIO_3__I2C3_SCL IOMUX_PAD(0x6B0, 0x320, 2 | IOMUX_CONFIG_SION, 0x824, 1, NO_PAD_CTRL) | ||
| 1142 | #define MX53_PAD_GPIO_3__DPLLIP1_TOG_EN IOMUX_PAD(0x6B0, 0x320, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 1143 | #define MX53_PAD_GPIO_3__CCM_CLKO2 IOMUX_PAD(0x6B0, 0x320, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 1144 | #define MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 IOMUX_PAD(0x6B0, 0x320, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 1145 | #define MX53_PAD_GPIO_3__USBOH3_USBH1_OC IOMUX_PAD(0x6B0, 0x320, 6, 0x8A0, 1, NO_PAD_CTRL) | ||
| 1146 | #define MX53_PAD_GPIO_3__MLB_MLBCLK IOMUX_PAD(0x6B0, 0x320, 7, 0x858, 2, NO_PAD_CTRL) | ||
| 1147 | #define MX53_PAD_GPIO_6__ESAI1_SCKT IOMUX_PAD(0x6B4, 0x324, 0, 0x7E0, 1, NO_PAD_CTRL) | ||
| 1148 | #define MX53_PAD_GPIO_6__GPIO1_6 IOMUX_PAD(0x6B4, 0x324, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 1149 | #define MX53_PAD_GPIO_6__I2C3_SDA IOMUX_PAD(0x6B4, 0x324, 2 | IOMUX_CONFIG_SION, 0x828, 1, NO_PAD_CTRL) | ||
| 1150 | #define MX53_PAD_GPIO_6__CCM_CCM_OUT_0 IOMUX_PAD(0x6B4, 0x324, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 1151 | #define MX53_PAD_GPIO_6__CSU_CSU_INT_DEB IOMUX_PAD(0x6B4, 0x324, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 1152 | #define MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 IOMUX_PAD(0x6B4, 0x324, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 1153 | #define MX53_PAD_GPIO_6__ESDHC2_LCTL IOMUX_PAD(0x6B4, 0x324, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 1154 | #define MX53_PAD_GPIO_6__MLB_MLBSIG IOMUX_PAD(0x6B4, 0x324, 7, 0x860, 2, NO_PAD_CTRL) | ||
| 1155 | #define MX53_PAD_GPIO_2__ESAI1_FST IOMUX_PAD(0x6B8, 0x328, 0, 0x7D0, 1, NO_PAD_CTRL) | ||
| 1156 | #define MX53_PAD_GPIO_2__GPIO1_2 IOMUX_PAD(0x6B8, 0x328, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 1157 | #define MX53_PAD_GPIO_2__KPP_ROW_6 IOMUX_PAD(0x6B8, 0x328, 2, 0x850, 2, NO_PAD_CTRL) | ||
| 1158 | #define MX53_PAD_GPIO_2__CCM_CCM_OUT_1 IOMUX_PAD(0x6B8, 0x328, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 1159 | #define MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 IOMUX_PAD(0x6B8, 0x328, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 1160 | #define MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 IOMUX_PAD(0x6B8, 0x328, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 1161 | #define MX53_PAD_GPIO_2__ESDHC2_WP IOMUX_PAD(0x6B8, 0x328, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 1162 | #define MX53_PAD_GPIO_2__MLB_MLBDAT IOMUX_PAD(0x6B8, 0x328, 7, 0x85C, 2, NO_PAD_CTRL) | ||
| 1163 | #define MX53_PAD_GPIO_4__ESAI1_HCKT IOMUX_PAD(0x6BC, 0x32C, 0, 0x7D8, 1, NO_PAD_CTRL) | ||
| 1164 | #define MX53_PAD_GPIO_4__GPIO1_4 IOMUX_PAD(0x6BC, 0x32C, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 1165 | #define MX53_PAD_GPIO_4__KPP_COL_7 IOMUX_PAD(0x6BC, 0x32C, 2, 0x848, 2, NO_PAD_CTRL) | ||
| 1166 | #define MX53_PAD_GPIO_4__CCM_CCM_OUT_2 IOMUX_PAD(0x6BC, 0x32C, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 1167 | #define MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 IOMUX_PAD(0x6BC, 0x32C, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 1168 | #define MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 IOMUX_PAD(0x6BC, 0x32C, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 1169 | #define MX53_PAD_GPIO_4__ESDHC2_CD IOMUX_PAD(0x6BC, 0x32C, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 1170 | #define MX53_PAD_GPIO_4__SCC_SEC_STATE IOMUX_PAD(0x6BC, 0x32C, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 1171 | #define MX53_PAD_GPIO_5__ESAI1_TX2_RX3 IOMUX_PAD(0x6C0, 0x330, 0, 0x7EC, 1, NO_PAD_CTRL) | ||
| 1172 | #define MX53_PAD_GPIO_5__GPIO1_5 IOMUX_PAD(0x6C0, 0x330, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 1173 | #define MX53_PAD_GPIO_5__KPP_ROW_7 IOMUX_PAD(0x6C0, 0x330, 2, 0x854, 2, NO_PAD_CTRL) | ||
| 1174 | #define MX53_PAD_GPIO_5__CCM_CLKO IOMUX_PAD(0x6C0, 0x330, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 1175 | #define MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 IOMUX_PAD(0x6C0, 0x330, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 1176 | #define MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 IOMUX_PAD(0x6C0, 0x330, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 1177 | #define MX53_PAD_GPIO_5__I2C3_SCL IOMUX_PAD(0x6C0, 0x330, 6 | IOMUX_CONFIG_SION, 0x824, 2, NO_PAD_CTRL) | ||
| 1178 | #define MX53_PAD_GPIO_5__CCM_PLL1_BYP IOMUX_PAD(0x6C0, 0x330, 7, 0x770, 1, NO_PAD_CTRL) | ||
| 1179 | #define MX53_PAD_GPIO_7__ESAI1_TX4_RX1 IOMUX_PAD(0x6C4, 0x334, 0, 0x7F4, 1, NO_PAD_CTRL) | ||
| 1180 | #define MX53_PAD_GPIO_7__GPIO1_7 IOMUX_PAD(0x6C4, 0x334, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 1181 | #define MX53_PAD_GPIO_7__EPIT1_EPITO IOMUX_PAD(0x6C4, 0x334, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 1182 | #define MX53_PAD_GPIO_7__CAN1_TXCAN IOMUX_PAD(0x6C4, 0x334, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 1183 | #define MX53_PAD_GPIO_7__UART2_TXD_MUX IOMUX_PAD(0x6C4, 0x334, 4, __NA_, 0, MX53_UART_PAD_CTRL) | ||
| 1184 | #define MX53_PAD_GPIO_7__FIRI_RXD IOMUX_PAD(0x6C4, 0x334, 5, 0x80C, 1, NO_PAD_CTRL) | ||
| 1185 | #define MX53_PAD_GPIO_7__SPDIF_PLOCK IOMUX_PAD(0x6C4, 0x334, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 1186 | #define MX53_PAD_GPIO_7__CCM_PLL2_BYP IOMUX_PAD(0x6C4, 0x334, 7, 0x774, 1, NO_PAD_CTRL) | ||
| 1187 | #define MX53_PAD_GPIO_8__ESAI1_TX5_RX0 IOMUX_PAD(0x6C8, 0x338, 0, 0x7F8, 1, NO_PAD_CTRL) | ||
| 1188 | #define MX53_PAD_GPIO_8__GPIO1_8 IOMUX_PAD(0x6C8, 0x338, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 1189 | #define MX53_PAD_GPIO_8__EPIT2_EPITO IOMUX_PAD(0x6C8, 0x338, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 1190 | #define MX53_PAD_GPIO_8__CAN1_RXCAN IOMUX_PAD(0x6C8, 0x338, 3, 0x760, 2, NO_PAD_CTRL) | ||
| 1191 | #define MX53_PAD_GPIO_8__UART2_RXD_MUX IOMUX_PAD(0x6C8, 0x338, 4, 0x880, 5, MX53_UART_PAD_CTRL) | ||
| 1192 | #define MX53_PAD_GPIO_8__FIRI_TXD IOMUX_PAD(0x6C8, 0x338, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 1193 | #define MX53_PAD_GPIO_8__SPDIF_SRCLK IOMUX_PAD(0x6C8, 0x338, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 1194 | #define MX53_PAD_GPIO_8__CCM_PLL3_BYP IOMUX_PAD(0x6C8, 0x338, 7, 0x778, 1, NO_PAD_CTRL) | ||
| 1195 | #define MX53_PAD_GPIO_16__ESAI1_TX3_RX2 IOMUX_PAD(0x6CC, 0x33C, 0, 0x7F0, 1, NO_PAD_CTRL) | ||
| 1196 | #define MX53_PAD_GPIO_16__GPIO7_11 IOMUX_PAD(0x6CC, 0x33C, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 1197 | #define MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT IOMUX_PAD(0x6CC, 0x33C, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 1198 | #define MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1 IOMUX_PAD(0x6CC, 0x33C, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 1199 | #define MX53_PAD_GPIO_16__SPDIF_IN1 IOMUX_PAD(0x6CC, 0x33C, 5, 0x870, 1, NO_PAD_CTRL) | ||
| 1200 | #define MX53_PAD_GPIO_16__I2C3_SDA IOMUX_PAD(0x6CC, 0x33C, 6 | IOMUX_CONFIG_SION, 0x828, 2, NO_PAD_CTRL) | ||
| 1201 | #define MX53_PAD_GPIO_16__SJC_DE_B IOMUX_PAD(0x6CC, 0x33C, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 1202 | #define MX53_PAD_GPIO_17__ESAI1_TX0 IOMUX_PAD(0x6D0, 0x340, 0, 0x7E4, 1, NO_PAD_CTRL) | ||
| 1203 | #define MX53_PAD_GPIO_17__GPIO7_12 IOMUX_PAD(0x6D0, 0x340, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 1204 | #define MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0 IOMUX_PAD(0x6D0, 0x340, 2, 0x868, 1, NO_PAD_CTRL) | ||
| 1205 | #define MX53_PAD_GPIO_17__GPC_PMIC_RDY IOMUX_PAD(0x6D0, 0x340, 3, 0x810, 1, NO_PAD_CTRL) | ||
| 1206 | #define MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG IOMUX_PAD(0x6D0, 0x340, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 1207 | #define MX53_PAD_GPIO_17__SPDIF_OUT1 IOMUX_PAD(0x6D0, 0x340, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 1208 | #define MX53_PAD_GPIO_17__IPU_SNOOP2 IOMUX_PAD(0x6D0, 0x340, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 1209 | #define MX53_PAD_GPIO_17__SJC_JTAG_ACT IOMUX_PAD(0x6D0, 0x340, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 1210 | #define MX53_PAD_GPIO_18__ESAI1_TX1 IOMUX_PAD(0x6D4, 0x344, 0, 0x7E8, 1, NO_PAD_CTRL) | ||
| 1211 | #define MX53_PAD_GPIO_18__GPIO7_13 IOMUX_PAD(0x6D4, 0x344, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 1212 | #define MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1 IOMUX_PAD(0x6D4, 0x344, 2, 0x86C, 1, NO_PAD_CTRL) | ||
| 1213 | #define MX53_PAD_GPIO_18__OWIRE_LINE IOMUX_PAD(0x6D4, 0x344, 3, 0x864, 1, NO_PAD_CTRL) | ||
| 1214 | #define MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG IOMUX_PAD(0x6D4, 0x344, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 1215 | #define MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK IOMUX_PAD(0x6D4, 0x344, 5, 0x768, 1, NO_PAD_CTRL) | ||
| 1216 | #define MX53_PAD_GPIO_18__ESDHC1_LCTL IOMUX_PAD(0x6D4, 0x344, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 1217 | #define MX53_PAD_GPIO_18__SRC_SYSTEM_RST IOMUX_PAD(0x6D4, 0x344, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 1218 | |||
| 1219 | #endif /* __MACH_IOMUX_MX53_H__ */ | ||
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig index dd36eba9506c..d15a4a6d6146 100644 --- a/arch/arm/plat-omap/Kconfig +++ b/arch/arm/plat-omap/Kconfig | |||
| @@ -25,6 +25,7 @@ config ARCH_OMAP2PLUS | |||
| 25 | bool "TI OMAP2/3/4" | 25 | bool "TI OMAP2/3/4" |
| 26 | select CLKDEV_LOOKUP | 26 | select CLKDEV_LOOKUP |
| 27 | select GENERIC_IRQ_CHIP | 27 | select GENERIC_IRQ_CHIP |
| 28 | select SPARSE_IRQ | ||
| 28 | select OMAP_DM_TIMER | 29 | select OMAP_DM_TIMER |
| 29 | select USE_OF | 30 | select USE_OF |
| 30 | select PROC_DEVICETREE if PROC_FS | 31 | select PROC_DEVICETREE if PROC_FS |
diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile index 961bf859bc0c..a017e994e006 100644 --- a/arch/arm/plat-omap/Makefile +++ b/arch/arm/plat-omap/Makefile | |||
| @@ -3,8 +3,7 @@ | |||
| 3 | # | 3 | # |
| 4 | 4 | ||
| 5 | # Common support | 5 | # Common support |
| 6 | obj-y := common.o sram.o clock.o devices.o dma.o mux.o \ | 6 | obj-y := common.o sram.o clock.o dma.o mux.o fb.o counter_32k.o |
| 7 | fb.o counter_32k.o | ||
| 8 | obj-m := | 7 | obj-m := |
| 9 | obj-n := | 8 | obj-n := |
| 10 | obj- := | 9 | obj- := |
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c index 89a3723b3538..e5778ed689d8 100644 --- a/arch/arm/plat-omap/common.c +++ b/arch/arm/plat-omap/common.c | |||
| @@ -17,52 +17,12 @@ | |||
| 17 | #include <linux/dma-mapping.h> | 17 | #include <linux/dma-mapping.h> |
| 18 | 18 | ||
| 19 | #include <plat/common.h> | 19 | #include <plat/common.h> |
| 20 | #include <plat/board.h> | ||
| 21 | #include <plat/vram.h> | 20 | #include <plat/vram.h> |
| 22 | #include <plat/dsp.h> | 21 | #include <plat/dsp.h> |
| 23 | #include <plat/dma.h> | 22 | #include <plat/dma.h> |
| 24 | 23 | ||
| 25 | #include <plat/omap-secure.h> | 24 | #include <plat/omap-secure.h> |
| 26 | 25 | ||
| 27 | |||
| 28 | #define NO_LENGTH_CHECK 0xffffffff | ||
| 29 | |||
| 30 | struct omap_board_config_kernel *omap_board_config __initdata; | ||
| 31 | int omap_board_config_size; | ||
| 32 | |||
| 33 | static const void *__init get_config(u16 tag, size_t len, | ||
| 34 | int skip, size_t *len_out) | ||
| 35 | { | ||
| 36 | struct omap_board_config_kernel *kinfo = NULL; | ||
| 37 | int i; | ||
| 38 | |||
| 39 | /* Try to find the config from the board-specific structures | ||
| 40 | * in the kernel. */ | ||
| 41 | for (i = 0; i < omap_board_config_size; i++) { | ||
| 42 | if (omap_board_config[i].tag == tag) { | ||
| 43 | if (skip == 0) { | ||
| 44 | kinfo = &omap_board_config[i]; | ||
| 45 | break; | ||
| 46 | } else { | ||
| 47 | skip--; | ||
| 48 | } | ||
| 49 | } | ||
| 50 | } | ||
| 51 | if (kinfo == NULL) | ||
| 52 | return NULL; | ||
| 53 | return kinfo->data; | ||
| 54 | } | ||
| 55 | |||
| 56 | const void *__init __omap_get_config(u16 tag, size_t len, int nr) | ||
| 57 | { | ||
| 58 | return get_config(tag, len, nr, NULL); | ||
| 59 | } | ||
| 60 | |||
| 61 | const void *__init omap_get_var_config(u16 tag, size_t *len) | ||
| 62 | { | ||
| 63 | return get_config(tag, NO_LENGTH_CHECK, 0, len); | ||
| 64 | } | ||
| 65 | |||
| 66 | void __init omap_reserve(void) | 26 | void __init omap_reserve(void) |
| 67 | { | 27 | { |
| 68 | omap_vram_reserve_sdram_memblock(); | 28 | omap_vram_reserve_sdram_memblock(); |
diff --git a/arch/arm/plat-omap/counter_32k.c b/arch/arm/plat-omap/counter_32k.c index dbf1e03029a5..2e826f1faf7b 100644 --- a/arch/arm/plat-omap/counter_32k.c +++ b/arch/arm/plat-omap/counter_32k.c | |||
| @@ -22,10 +22,7 @@ | |||
| 22 | #include <asm/mach/time.h> | 22 | #include <asm/mach/time.h> |
| 23 | #include <asm/sched_clock.h> | 23 | #include <asm/sched_clock.h> |
| 24 | 24 | ||
| 25 | #include <plat/hardware.h> | ||
| 26 | #include <plat/common.h> | 25 | #include <plat/common.h> |
| 27 | #include <plat/board.h> | ||
| 28 | |||
| 29 | #include <plat/clock.h> | 26 | #include <plat/clock.h> |
| 30 | 27 | ||
| 31 | /* OMAP2_32KSYNCNT_CR_OFF: offset of 32ksync counter register */ | 28 | /* OMAP2_32KSYNCNT_CR_OFF: offset of 32ksync counter register */ |
diff --git a/arch/arm/plat-omap/debug-devices.c b/arch/arm/plat-omap/debug-devices.c index caa1f7b6cc21..c7a4c0902b38 100644 --- a/arch/arm/plat-omap/debug-devices.c +++ b/arch/arm/plat-omap/debug-devices.c | |||
| @@ -17,9 +17,6 @@ | |||
| 17 | 17 | ||
| 18 | #include <mach/hardware.h> | 18 | #include <mach/hardware.h> |
| 19 | 19 | ||
| 20 | #include <plat/board.h> | ||
| 21 | |||
| 22 | |||
| 23 | /* Many OMAP development platforms reuse the same "debug board"; these | 20 | /* Many OMAP development platforms reuse the same "debug board"; these |
| 24 | * platforms include H2, H3, H4, and Perseus2. | 21 | * platforms include H2, H3, H4, and Perseus2. |
| 25 | */ | 22 | */ |
diff --git a/arch/arm/plat-omap/debug-leds.c b/arch/arm/plat-omap/debug-leds.c index 39407cbe34c6..195aaae65872 100644 --- a/arch/arm/plat-omap/debug-leds.c +++ b/arch/arm/plat-omap/debug-leds.c | |||
| @@ -12,6 +12,7 @@ | |||
| 12 | #include <linux/platform_device.h> | 12 | #include <linux/platform_device.h> |
| 13 | #include <linux/leds.h> | 13 | #include <linux/leds.h> |
| 14 | #include <linux/io.h> | 14 | #include <linux/io.h> |
| 15 | #include <linux/platform_data/gpio-omap.h> | ||
| 15 | 16 | ||
| 16 | #include <mach/hardware.h> | 17 | #include <mach/hardware.h> |
| 17 | #include <asm/leds.h> | 18 | #include <asm/leds.h> |
diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c deleted file mode 100644 index 1cba9273d2cb..000000000000 --- a/arch/arm/plat-omap/devices.c +++ /dev/null | |||
| @@ -1,92 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/plat-omap/devices.c | ||
| 3 | * | ||
| 4 | * Common platform device setup/initialization for OMAP1 and OMAP2 | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | */ | ||
| 11 | #include <linux/gpio.h> | ||
| 12 | #include <linux/module.h> | ||
| 13 | #include <linux/kernel.h> | ||
| 14 | #include <linux/init.h> | ||
| 15 | #include <linux/platform_device.h> | ||
| 16 | #include <linux/io.h> | ||
| 17 | #include <linux/slab.h> | ||
| 18 | #include <linux/memblock.h> | ||
| 19 | |||
| 20 | #include <mach/hardware.h> | ||
| 21 | #include <asm/mach-types.h> | ||
| 22 | #include <asm/mach/map.h> | ||
| 23 | #include <asm/memblock.h> | ||
| 24 | |||
| 25 | #include <plat/tc.h> | ||
| 26 | #include <plat/board.h> | ||
| 27 | #include <plat/mmc.h> | ||
| 28 | #include <plat/menelaus.h> | ||
| 29 | #include <plat/omap44xx.h> | ||
| 30 | |||
| 31 | /*-------------------------------------------------------------------------*/ | ||
| 32 | |||
| 33 | #if defined(CONFIG_HW_RANDOM_OMAP) || defined(CONFIG_HW_RANDOM_OMAP_MODULE) | ||
| 34 | |||
| 35 | #ifdef CONFIG_ARCH_OMAP2 | ||
| 36 | #define OMAP_RNG_BASE 0x480A0000 | ||
| 37 | #else | ||
| 38 | #define OMAP_RNG_BASE 0xfffe5000 | ||
| 39 | #endif | ||
| 40 | |||
| 41 | static struct resource rng_resources[] = { | ||
| 42 | { | ||
| 43 | .start = OMAP_RNG_BASE, | ||
| 44 | .end = OMAP_RNG_BASE + 0x4f, | ||
| 45 | .flags = IORESOURCE_MEM, | ||
| 46 | }, | ||
| 47 | }; | ||
| 48 | |||
| 49 | static struct platform_device omap_rng_device = { | ||
| 50 | .name = "omap_rng", | ||
| 51 | .id = -1, | ||
| 52 | .num_resources = ARRAY_SIZE(rng_resources), | ||
| 53 | .resource = rng_resources, | ||
| 54 | }; | ||
| 55 | |||
| 56 | static void omap_init_rng(void) | ||
| 57 | { | ||
| 58 | (void) platform_device_register(&omap_rng_device); | ||
| 59 | } | ||
| 60 | #else | ||
| 61 | static inline void omap_init_rng(void) {} | ||
| 62 | #endif | ||
| 63 | |||
| 64 | /* | ||
| 65 | * This gets called after board-specific INIT_MACHINE, and initializes most | ||
| 66 | * on-chip peripherals accessible on this board (except for few like USB): | ||
| 67 | * | ||
| 68 | * (a) Does any "standard config" pin muxing needed. Board-specific | ||
| 69 | * code will have muxed GPIO pins and done "nonstandard" setup; | ||
| 70 | * that code could live in the boot loader. | ||
| 71 | * (b) Populating board-specific platform_data with the data drivers | ||
| 72 | * rely on to handle wiring variations. | ||
| 73 | * (c) Creating platform devices as meaningful on this board and | ||
| 74 | * with this kernel configuration. | ||
| 75 | * | ||
| 76 | * Claiming GPIOs, and setting their direction and initial values, is the | ||
| 77 | * responsibility of the device drivers. So is responding to probe(). | ||
| 78 | * | ||
| 79 | * Board-specific knowledge like creating devices or pin setup is to be | ||
| 80 | * kept out of drivers as much as possible. In particular, pin setup | ||
| 81 | * may be handled by the boot loader, and drivers should expect it will | ||
| 82 | * normally have been done by the time they're probed. | ||
| 83 | */ | ||
| 84 | static int __init omap_init_devices(void) | ||
| 85 | { | ||
| 86 | /* please keep these calls, and their implementations above, | ||
| 87 | * in alphabetical order so they're easier to sort through. | ||
| 88 | */ | ||
| 89 | omap_init_rng(); | ||
| 90 | return 0; | ||
| 91 | } | ||
| 92 | arch_initcall(omap_init_devices); | ||
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c index 7fe626761e53..6dcad5873d57 100644 --- a/arch/arm/plat-omap/dma.c +++ b/arch/arm/plat-omap/dma.c | |||
| @@ -36,9 +36,8 @@ | |||
| 36 | #include <linux/slab.h> | 36 | #include <linux/slab.h> |
| 37 | #include <linux/delay.h> | 37 | #include <linux/delay.h> |
| 38 | 38 | ||
| 39 | #include <mach/hardware.h> | 39 | #include <plat/cpu.h> |
| 40 | #include <plat/dma.h> | 40 | #include <plat/dma.h> |
| 41 | |||
| 42 | #include <plat/tc.h> | 41 | #include <plat/tc.h> |
| 43 | 42 | ||
| 44 | /* | 43 | /* |
diff --git a/arch/arm/plat-omap/fb.c b/arch/arm/plat-omap/fb.c index dd6f92c99e56..bcbb9d5dc293 100644 --- a/arch/arm/plat-omap/fb.c +++ b/arch/arm/plat-omap/fb.c | |||
| @@ -33,8 +33,6 @@ | |||
| 33 | #include <mach/hardware.h> | 33 | #include <mach/hardware.h> |
| 34 | #include <asm/mach/map.h> | 34 | #include <asm/mach/map.h> |
| 35 | 35 | ||
| 36 | #include <plat/board.h> | ||
| 37 | |||
| 38 | #if defined(CONFIG_FB_OMAP) || defined(CONFIG_FB_OMAP_MODULE) | 36 | #if defined(CONFIG_FB_OMAP) || defined(CONFIG_FB_OMAP_MODULE) |
| 39 | 37 | ||
| 40 | static bool omapfb_lcd_configured; | 38 | static bool omapfb_lcd_configured; |
diff --git a/arch/arm/plat-omap/i2c.c b/arch/arm/plat-omap/i2c.c index db071bc71c4d..40bc06a7ac43 100644 --- a/arch/arm/plat-omap/i2c.c +++ b/arch/arm/plat-omap/i2c.c | |||
| @@ -39,6 +39,7 @@ | |||
| 39 | 39 | ||
| 40 | #define OMAP_I2C_SIZE 0x3f | 40 | #define OMAP_I2C_SIZE 0x3f |
| 41 | #define OMAP1_I2C_BASE 0xfffb3800 | 41 | #define OMAP1_I2C_BASE 0xfffb3800 |
| 42 | #define OMAP1_INT_I2C (32 + 4) | ||
| 42 | 43 | ||
| 43 | static const char name[] = "omap_i2c"; | 44 | static const char name[] = "omap_i2c"; |
| 44 | 45 | ||
| @@ -105,7 +106,7 @@ static inline int omap1_i2c_add_bus(int bus_id) | |||
| 105 | res = pdev->resource; | 106 | res = pdev->resource; |
| 106 | res[0].start = OMAP1_I2C_BASE; | 107 | res[0].start = OMAP1_I2C_BASE; |
| 107 | res[0].end = res[0].start + OMAP_I2C_SIZE; | 108 | res[0].end = res[0].start + OMAP_I2C_SIZE; |
| 108 | res[1].start = INT_I2C; | 109 | res[1].start = OMAP1_INT_I2C; |
| 109 | pdata = &i2c_pdata[bus_id - 1]; | 110 | pdata = &i2c_pdata[bus_id - 1]; |
| 110 | 111 | ||
| 111 | /* all OMAP1 have IP version 1 register set */ | 112 | /* all OMAP1 have IP version 1 register set */ |
diff --git a/arch/arm/plat-omap/include/plat/board.h b/arch/arm/plat-omap/include/plat/board.h deleted file mode 100644 index e62f20a5c0af..000000000000 --- a/arch/arm/plat-omap/include/plat/board.h +++ /dev/null | |||
| @@ -1,138 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/plat-omap/include/mach/board.h | ||
| 3 | * | ||
| 4 | * Information structures for board-specific data | ||
| 5 | * | ||
| 6 | * Copyright (C) 2004 Nokia Corporation | ||
| 7 | * Written by Juha Yrjölä <juha.yrjola@nokia.com> | ||
| 8 | */ | ||
| 9 | |||
| 10 | #ifndef _OMAP_BOARD_H | ||
| 11 | #define _OMAP_BOARD_H | ||
| 12 | |||
| 13 | #include <linux/types.h> | ||
| 14 | |||
| 15 | #include <plat/gpio-switch.h> | ||
| 16 | |||
| 17 | /* | ||
| 18 | * OMAP35x EVM revision | ||
| 19 | * Run time detection of EVM revision is done by reading Ethernet | ||
| 20 | * PHY ID - | ||
| 21 | * GEN_1 = 0x01150000 | ||
| 22 | * GEN_2 = 0x92200000 | ||
| 23 | */ | ||
| 24 | enum { | ||
| 25 | OMAP3EVM_BOARD_GEN_1 = 0, /* EVM Rev between A - D */ | ||
| 26 | OMAP3EVM_BOARD_GEN_2, /* EVM Rev >= Rev E */ | ||
| 27 | }; | ||
| 28 | |||
| 29 | /* Different peripheral ids */ | ||
| 30 | #define OMAP_TAG_CLOCK 0x4f01 | ||
| 31 | #define OMAP_TAG_GPIO_SWITCH 0x4f06 | ||
| 32 | #define OMAP_TAG_STI_CONSOLE 0x4f09 | ||
| 33 | #define OMAP_TAG_CAMERA_SENSOR 0x4f0a | ||
| 34 | |||
| 35 | #define OMAP_TAG_BOOT_REASON 0x4f80 | ||
| 36 | #define OMAP_TAG_FLASH_PART 0x4f81 | ||
| 37 | #define OMAP_TAG_VERSION_STR 0x4f82 | ||
| 38 | |||
| 39 | struct omap_clock_config { | ||
| 40 | /* 0 for 12 MHz, 1 for 13 MHz and 2 for 19.2 MHz */ | ||
| 41 | u8 system_clock_type; | ||
| 42 | }; | ||
| 43 | |||
| 44 | struct omap_serial_console_config { | ||
| 45 | u8 console_uart; | ||
| 46 | u32 console_speed; | ||
| 47 | }; | ||
| 48 | |||
| 49 | struct omap_sti_console_config { | ||
| 50 | unsigned enable:1; | ||
| 51 | u8 channel; | ||
| 52 | }; | ||
| 53 | |||
| 54 | struct omap_camera_sensor_config { | ||
| 55 | u16 reset_gpio; | ||
| 56 | int (*power_on)(void * data); | ||
| 57 | int (*power_off)(void * data); | ||
| 58 | }; | ||
| 59 | |||
| 60 | struct omap_lcd_config { | ||
| 61 | char panel_name[16]; | ||
| 62 | char ctrl_name[16]; | ||
| 63 | s16 nreset_gpio; | ||
| 64 | u8 data_lines; | ||
| 65 | }; | ||
| 66 | |||
| 67 | struct device; | ||
| 68 | struct fb_info; | ||
| 69 | struct omap_backlight_config { | ||
| 70 | int default_intensity; | ||
| 71 | int (*set_power)(struct device *dev, int state); | ||
| 72 | }; | ||
| 73 | |||
| 74 | struct omap_fbmem_config { | ||
| 75 | u32 start; | ||
| 76 | u32 size; | ||
| 77 | }; | ||
| 78 | |||
| 79 | struct omap_pwm_led_platform_data { | ||
| 80 | const char *name; | ||
| 81 | int intensity_timer; | ||
| 82 | int blink_timer; | ||
| 83 | void (*set_power)(struct omap_pwm_led_platform_data *self, int on_off); | ||
| 84 | }; | ||
| 85 | |||
| 86 | struct omap_uart_config { | ||
| 87 | /* Bit field of UARTs present; bit 0 --> UART1 */ | ||
| 88 | unsigned int enabled_uarts; | ||
| 89 | }; | ||
| 90 | |||
| 91 | |||
| 92 | struct omap_flash_part_config { | ||
| 93 | char part_table[0]; | ||
| 94 | }; | ||
| 95 | |||
| 96 | struct omap_boot_reason_config { | ||
| 97 | char reason_str[12]; | ||
| 98 | }; | ||
| 99 | |||
| 100 | struct omap_version_config { | ||
| 101 | char component[12]; | ||
| 102 | char version[12]; | ||
| 103 | }; | ||
| 104 | |||
| 105 | struct omap_board_config_entry { | ||
| 106 | u16 tag; | ||
| 107 | u16 len; | ||
| 108 | u8 data[0]; | ||
| 109 | }; | ||
| 110 | |||
| 111 | struct omap_board_config_kernel { | ||
| 112 | u16 tag; | ||
| 113 | const void *data; | ||
| 114 | }; | ||
| 115 | |||
| 116 | extern const void *__init __omap_get_config(u16 tag, size_t len, int nr); | ||
| 117 | |||
| 118 | #define omap_get_config(tag, type) \ | ||
| 119 | ((const type *) __omap_get_config((tag), sizeof(type), 0)) | ||
| 120 | #define omap_get_nr_config(tag, type, nr) \ | ||
| 121 | ((const type *) __omap_get_config((tag), sizeof(type), (nr))) | ||
| 122 | |||
| 123 | extern const void *__init omap_get_var_config(u16 tag, size_t *len); | ||
| 124 | |||
| 125 | extern struct omap_board_config_kernel *omap_board_config; | ||
| 126 | extern int omap_board_config_size; | ||
| 127 | |||
| 128 | |||
| 129 | /* for TI reference platforms sharing the same debug card */ | ||
| 130 | extern int debug_card_init(u32 addr, unsigned gpio); | ||
| 131 | |||
| 132 | /* OMAP3EVM revision */ | ||
| 133 | #if defined(CONFIG_MACH_OMAP3EVM) | ||
| 134 | u8 get_omap3_evm_rev(void); | ||
| 135 | #else | ||
| 136 | #define get_omap3_evm_rev() (-EINVAL) | ||
| 137 | #endif | ||
| 138 | #endif | ||
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h index bb5d08a70dbc..67da857783ce 100644 --- a/arch/arm/plat-omap/include/plat/cpu.h +++ b/arch/arm/plat-omap/include/plat/cpu.h | |||
| @@ -30,6 +30,8 @@ | |||
| 30 | #ifndef __ASM_ARCH_OMAP_CPU_H | 30 | #ifndef __ASM_ARCH_OMAP_CPU_H |
| 31 | #define __ASM_ARCH_OMAP_CPU_H | 31 | #define __ASM_ARCH_OMAP_CPU_H |
| 32 | 32 | ||
| 33 | #ifndef __ASSEMBLY__ | ||
| 34 | |||
| 33 | #include <linux/bitops.h> | 35 | #include <linux/bitops.h> |
| 34 | #include <plat/multi.h> | 36 | #include <plat/multi.h> |
| 35 | 37 | ||
| @@ -493,4 +495,5 @@ OMAP4_HAS_FEATURE(mpu_1ghz, MPU_1GHZ) | |||
| 493 | OMAP4_HAS_FEATURE(mpu_1_2ghz, MPU_1_2GHZ) | 495 | OMAP4_HAS_FEATURE(mpu_1_2ghz, MPU_1_2GHZ) |
| 494 | OMAP4_HAS_FEATURE(mpu_1_5ghz, MPU_1_5GHZ) | 496 | OMAP4_HAS_FEATURE(mpu_1_5ghz, MPU_1_5GHZ) |
| 495 | 497 | ||
| 498 | #endif /* __ASSEMBLY__ */ | ||
| 496 | #endif | 499 | #endif |
diff --git a/arch/arm/plat-omap/include/plat/debug-devices.h b/arch/arm/plat-omap/include/plat/debug-devices.h new file mode 100644 index 000000000000..a4edbd2f7484 --- /dev/null +++ b/arch/arm/plat-omap/include/plat/debug-devices.h | |||
| @@ -0,0 +1,9 @@ | |||
| 1 | #ifndef _OMAP_DEBUG_DEVICES_H | ||
| 2 | #define _OMAP_DEBUG_DEVICES_H | ||
| 3 | |||
| 4 | #include <linux/types.h> | ||
| 5 | |||
| 6 | /* for TI reference platforms sharing the same debug card */ | ||
| 7 | extern int debug_card_init(u32 addr, unsigned gpio); | ||
| 8 | |||
| 9 | #endif | ||
diff --git a/arch/arm/plat-omap/include/plat/dma.h b/arch/arm/plat-omap/include/plat/dma.h index c5811d4409b0..0a87b052f8f7 100644 --- a/arch/arm/plat-omap/include/plat/dma.h +++ b/arch/arm/plat-omap/include/plat/dma.h | |||
| @@ -31,6 +31,8 @@ | |||
| 31 | /* Move omap4 specific defines to dma-44xx.h */ | 31 | /* Move omap4 specific defines to dma-44xx.h */ |
| 32 | #include "dma-44xx.h" | 32 | #include "dma-44xx.h" |
| 33 | 33 | ||
| 34 | #define INT_DMA_LCD 25 | ||
| 35 | |||
| 34 | /* DMA channels for omap1 */ | 36 | /* DMA channels for omap1 */ |
| 35 | #define OMAP_DMA_NO_DEVICE 0 | 37 | #define OMAP_DMA_NO_DEVICE 0 |
| 36 | #define OMAP_DMA_MCSI1_TX 1 | 38 | #define OMAP_DMA_MCSI1_TX 1 |
diff --git a/arch/arm/plat-omap/include/plat/gpio-switch.h b/arch/arm/plat-omap/include/plat/gpio-switch.h deleted file mode 100644 index 10da0e07c0cf..000000000000 --- a/arch/arm/plat-omap/include/plat/gpio-switch.h +++ /dev/null | |||
| @@ -1,54 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * GPIO switch definitions | ||
| 3 | * | ||
| 4 | * Copyright (C) 2006 Nokia Corporation | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __ASM_ARCH_OMAP_GPIO_SWITCH_H | ||
| 12 | #define __ASM_ARCH_OMAP_GPIO_SWITCH_H | ||
| 13 | |||
| 14 | #include <linux/types.h> | ||
| 15 | |||
| 16 | /* Cover: | ||
| 17 | * high -> closed | ||
| 18 | * low -> open | ||
| 19 | * Connection: | ||
| 20 | * high -> connected | ||
| 21 | * low -> disconnected | ||
| 22 | * Activity: | ||
| 23 | * high -> active | ||
| 24 | * low -> inactive | ||
| 25 | * | ||
| 26 | */ | ||
| 27 | #define OMAP_GPIO_SWITCH_TYPE_COVER 0x0000 | ||
| 28 | #define OMAP_GPIO_SWITCH_TYPE_CONNECTION 0x0001 | ||
| 29 | #define OMAP_GPIO_SWITCH_TYPE_ACTIVITY 0x0002 | ||
| 30 | #define OMAP_GPIO_SWITCH_FLAG_INVERTED 0x0001 | ||
| 31 | #define OMAP_GPIO_SWITCH_FLAG_OUTPUT 0x0002 | ||
| 32 | |||
| 33 | struct omap_gpio_switch { | ||
| 34 | const char *name; | ||
| 35 | s16 gpio; | ||
| 36 | unsigned flags:4; | ||
| 37 | unsigned type:4; | ||
| 38 | |||
| 39 | /* Time in ms to debounce when transitioning from | ||
| 40 | * inactive state to active state. */ | ||
| 41 | u16 debounce_rising; | ||
| 42 | /* Same for transition from active to inactive state. */ | ||
| 43 | u16 debounce_falling; | ||
| 44 | |||
| 45 | /* notify board-specific code about state changes */ | ||
| 46 | void (* notify)(void *data, int state); | ||
| 47 | void *notify_data; | ||
| 48 | }; | ||
| 49 | |||
| 50 | /* Call at init time only */ | ||
| 51 | extern void omap_register_gpio_switches(const struct omap_gpio_switch *tbl, | ||
| 52 | int count); | ||
| 53 | |||
| 54 | #endif | ||
diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h deleted file mode 100644 index 50fb7cc000ea..000000000000 --- a/arch/arm/plat-omap/include/plat/gpio.h +++ /dev/null | |||
| @@ -1,228 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/plat-omap/include/mach/gpio.h | ||
| 3 | * | ||
| 4 | * OMAP GPIO handling defines and functions | ||
| 5 | * | ||
| 6 | * Copyright (C) 2003-2005 Nokia Corporation | ||
| 7 | * | ||
| 8 | * Written by Juha Yrjölä <juha.yrjola@nokia.com> | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License as published by | ||
| 12 | * the Free Software Foundation; either version 2 of the License, or | ||
| 13 | * (at your option) any later version. | ||
| 14 | * | ||
| 15 | * This program is distributed in the hope that it will be useful, | ||
| 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 18 | * GNU General Public License for more details. | ||
| 19 | * | ||
| 20 | * You should have received a copy of the GNU General Public License | ||
| 21 | * along with this program; if not, write to the Free Software | ||
| 22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 23 | * | ||
| 24 | */ | ||
| 25 | |||
| 26 | #ifndef __ASM_ARCH_OMAP_GPIO_H | ||
| 27 | #define __ASM_ARCH_OMAP_GPIO_H | ||
| 28 | |||
| 29 | #include <linux/io.h> | ||
| 30 | #include <linux/platform_device.h> | ||
| 31 | #include <mach/irqs.h> | ||
| 32 | |||
| 33 | #define OMAP1_MPUIO_BASE 0xfffb5000 | ||
| 34 | |||
| 35 | /* | ||
| 36 | * These are the omap15xx/16xx offsets. The omap7xx offset are | ||
| 37 | * OMAP_MPUIO_ / 2 offsets below. | ||
| 38 | */ | ||
| 39 | #define OMAP_MPUIO_INPUT_LATCH 0x00 | ||
| 40 | #define OMAP_MPUIO_OUTPUT 0x04 | ||
| 41 | #define OMAP_MPUIO_IO_CNTL 0x08 | ||
| 42 | #define OMAP_MPUIO_KBR_LATCH 0x10 | ||
| 43 | #define OMAP_MPUIO_KBC 0x14 | ||
| 44 | #define OMAP_MPUIO_GPIO_EVENT_MODE 0x18 | ||
| 45 | #define OMAP_MPUIO_GPIO_INT_EDGE 0x1c | ||
| 46 | #define OMAP_MPUIO_KBD_INT 0x20 | ||
| 47 | #define OMAP_MPUIO_GPIO_INT 0x24 | ||
| 48 | #define OMAP_MPUIO_KBD_MASKIT 0x28 | ||
| 49 | #define OMAP_MPUIO_GPIO_MASKIT 0x2c | ||
| 50 | #define OMAP_MPUIO_GPIO_DEBOUNCING 0x30 | ||
| 51 | #define OMAP_MPUIO_LATCH 0x34 | ||
| 52 | |||
| 53 | #define OMAP34XX_NR_GPIOS 6 | ||
| 54 | |||
| 55 | /* | ||
| 56 | * OMAP1510 GPIO registers | ||
| 57 | */ | ||
| 58 | #define OMAP1510_GPIO_DATA_INPUT 0x00 | ||
| 59 | #define OMAP1510_GPIO_DATA_OUTPUT 0x04 | ||
| 60 | #define OMAP1510_GPIO_DIR_CONTROL 0x08 | ||
| 61 | #define OMAP1510_GPIO_INT_CONTROL 0x0c | ||
| 62 | #define OMAP1510_GPIO_INT_MASK 0x10 | ||
| 63 | #define OMAP1510_GPIO_INT_STATUS 0x14 | ||
| 64 | #define OMAP1510_GPIO_PIN_CONTROL 0x18 | ||
| 65 | |||
| 66 | #define OMAP1510_IH_GPIO_BASE 64 | ||
| 67 | |||
| 68 | /* | ||
| 69 | * OMAP1610 specific GPIO registers | ||
| 70 | */ | ||
| 71 | #define OMAP1610_GPIO_REVISION 0x0000 | ||
| 72 | #define OMAP1610_GPIO_SYSCONFIG 0x0010 | ||
| 73 | #define OMAP1610_GPIO_SYSSTATUS 0x0014 | ||
| 74 | #define OMAP1610_GPIO_IRQSTATUS1 0x0018 | ||
| 75 | #define OMAP1610_GPIO_IRQENABLE1 0x001c | ||
| 76 | #define OMAP1610_GPIO_WAKEUPENABLE 0x0028 | ||
| 77 | #define OMAP1610_GPIO_DATAIN 0x002c | ||
| 78 | #define OMAP1610_GPIO_DATAOUT 0x0030 | ||
| 79 | #define OMAP1610_GPIO_DIRECTION 0x0034 | ||
| 80 | #define OMAP1610_GPIO_EDGE_CTRL1 0x0038 | ||
| 81 | #define OMAP1610_GPIO_EDGE_CTRL2 0x003c | ||
| 82 | #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c | ||
| 83 | #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8 | ||
| 84 | #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0 | ||
| 85 | #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc | ||
| 86 | #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8 | ||
| 87 | #define OMAP1610_GPIO_SET_DATAOUT 0x00f0 | ||
| 88 | |||
| 89 | /* | ||
| 90 | * OMAP7XX specific GPIO registers | ||
| 91 | */ | ||
| 92 | #define OMAP7XX_GPIO_DATA_INPUT 0x00 | ||
| 93 | #define OMAP7XX_GPIO_DATA_OUTPUT 0x04 | ||
| 94 | #define OMAP7XX_GPIO_DIR_CONTROL 0x08 | ||
| 95 | #define OMAP7XX_GPIO_INT_CONTROL 0x0c | ||
| 96 | #define OMAP7XX_GPIO_INT_MASK 0x10 | ||
| 97 | #define OMAP7XX_GPIO_INT_STATUS 0x14 | ||
| 98 | |||
| 99 | /* | ||
| 100 | * omap2+ specific GPIO registers | ||
| 101 | */ | ||
| 102 | #define OMAP24XX_GPIO_REVISION 0x0000 | ||
| 103 | #define OMAP24XX_GPIO_IRQSTATUS1 0x0018 | ||
| 104 | #define OMAP24XX_GPIO_IRQSTATUS2 0x0028 | ||
| 105 | #define OMAP24XX_GPIO_IRQENABLE2 0x002c | ||
| 106 | #define OMAP24XX_GPIO_IRQENABLE1 0x001c | ||
| 107 | #define OMAP24XX_GPIO_WAKE_EN 0x0020 | ||
| 108 | #define OMAP24XX_GPIO_CTRL 0x0030 | ||
| 109 | #define OMAP24XX_GPIO_OE 0x0034 | ||
| 110 | #define OMAP24XX_GPIO_DATAIN 0x0038 | ||
| 111 | #define OMAP24XX_GPIO_DATAOUT 0x003c | ||
| 112 | #define OMAP24XX_GPIO_LEVELDETECT0 0x0040 | ||
| 113 | #define OMAP24XX_GPIO_LEVELDETECT1 0x0044 | ||
| 114 | #define OMAP24XX_GPIO_RISINGDETECT 0x0048 | ||
| 115 | #define OMAP24XX_GPIO_FALLINGDETECT 0x004c | ||
| 116 | #define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050 | ||
| 117 | #define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054 | ||
| 118 | #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060 | ||
| 119 | #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064 | ||
| 120 | #define OMAP24XX_GPIO_CLEARWKUENA 0x0080 | ||
| 121 | #define OMAP24XX_GPIO_SETWKUENA 0x0084 | ||
| 122 | #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090 | ||
| 123 | #define OMAP24XX_GPIO_SETDATAOUT 0x0094 | ||
| 124 | |||
| 125 | #define OMAP4_GPIO_REVISION 0x0000 | ||
| 126 | #define OMAP4_GPIO_EOI 0x0020 | ||
| 127 | #define OMAP4_GPIO_IRQSTATUSRAW0 0x0024 | ||
| 128 | #define OMAP4_GPIO_IRQSTATUSRAW1 0x0028 | ||
| 129 | #define OMAP4_GPIO_IRQSTATUS0 0x002c | ||
| 130 | #define OMAP4_GPIO_IRQSTATUS1 0x0030 | ||
| 131 | #define OMAP4_GPIO_IRQSTATUSSET0 0x0034 | ||
| 132 | #define OMAP4_GPIO_IRQSTATUSSET1 0x0038 | ||
| 133 | #define OMAP4_GPIO_IRQSTATUSCLR0 0x003c | ||
| 134 | #define OMAP4_GPIO_IRQSTATUSCLR1 0x0040 | ||
| 135 | #define OMAP4_GPIO_IRQWAKEN0 0x0044 | ||
| 136 | #define OMAP4_GPIO_IRQWAKEN1 0x0048 | ||
| 137 | #define OMAP4_GPIO_IRQENABLE1 0x011c | ||
| 138 | #define OMAP4_GPIO_WAKE_EN 0x0120 | ||
| 139 | #define OMAP4_GPIO_IRQSTATUS2 0x0128 | ||
| 140 | #define OMAP4_GPIO_IRQENABLE2 0x012c | ||
| 141 | #define OMAP4_GPIO_CTRL 0x0130 | ||
| 142 | #define OMAP4_GPIO_OE 0x0134 | ||
| 143 | #define OMAP4_GPIO_DATAIN 0x0138 | ||
| 144 | #define OMAP4_GPIO_DATAOUT 0x013c | ||
| 145 | #define OMAP4_GPIO_LEVELDETECT0 0x0140 | ||
| 146 | #define OMAP4_GPIO_LEVELDETECT1 0x0144 | ||
| 147 | #define OMAP4_GPIO_RISINGDETECT 0x0148 | ||
| 148 | #define OMAP4_GPIO_FALLINGDETECT 0x014c | ||
| 149 | #define OMAP4_GPIO_DEBOUNCENABLE 0x0150 | ||
| 150 | #define OMAP4_GPIO_DEBOUNCINGTIME 0x0154 | ||
| 151 | #define OMAP4_GPIO_CLEARIRQENABLE1 0x0160 | ||
| 152 | #define OMAP4_GPIO_SETIRQENABLE1 0x0164 | ||
| 153 | #define OMAP4_GPIO_CLEARWKUENA 0x0180 | ||
| 154 | #define OMAP4_GPIO_SETWKUENA 0x0184 | ||
| 155 | #define OMAP4_GPIO_CLEARDATAOUT 0x0190 | ||
| 156 | #define OMAP4_GPIO_SETDATAOUT 0x0194 | ||
| 157 | |||
| 158 | #define OMAP_MPUIO(nr) (OMAP_MAX_GPIO_LINES + (nr)) | ||
| 159 | #define OMAP_GPIO_IS_MPUIO(nr) ((nr) >= OMAP_MAX_GPIO_LINES) | ||
| 160 | |||
| 161 | struct omap_gpio_dev_attr { | ||
| 162 | int bank_width; /* GPIO bank width */ | ||
| 163 | bool dbck_flag; /* dbck required or not - True for OMAP3&4 */ | ||
| 164 | }; | ||
| 165 | |||
| 166 | struct omap_gpio_reg_offs { | ||
| 167 | u16 revision; | ||
| 168 | u16 direction; | ||
| 169 | u16 datain; | ||
| 170 | u16 dataout; | ||
| 171 | u16 set_dataout; | ||
| 172 | u16 clr_dataout; | ||
| 173 | u16 irqstatus; | ||
| 174 | u16 irqstatus2; | ||
| 175 | u16 irqstatus_raw0; | ||
| 176 | u16 irqstatus_raw1; | ||
| 177 | u16 irqenable; | ||
| 178 | u16 irqenable2; | ||
| 179 | u16 set_irqenable; | ||
| 180 | u16 clr_irqenable; | ||
| 181 | u16 debounce; | ||
| 182 | u16 debounce_en; | ||
| 183 | u16 ctrl; | ||
| 184 | u16 wkup_en; | ||
| 185 | u16 leveldetect0; | ||
| 186 | u16 leveldetect1; | ||
| 187 | u16 risingdetect; | ||
| 188 | u16 fallingdetect; | ||
| 189 | u16 irqctrl; | ||
| 190 | u16 edgectrl1; | ||
| 191 | u16 edgectrl2; | ||
| 192 | u16 pinctrl; | ||
| 193 | |||
| 194 | bool irqenable_inv; | ||
| 195 | }; | ||
| 196 | |||
| 197 | struct omap_gpio_platform_data { | ||
| 198 | int bank_type; | ||
| 199 | int bank_width; /* GPIO bank width */ | ||
| 200 | int bank_stride; /* Only needed for omap1 MPUIO */ | ||
| 201 | bool dbck_flag; /* dbck required or not - True for OMAP3&4 */ | ||
| 202 | bool loses_context; /* whether the bank would ever lose context */ | ||
| 203 | bool is_mpuio; /* whether the bank is of type MPUIO */ | ||
| 204 | u32 non_wakeup_gpios; | ||
| 205 | |||
| 206 | struct omap_gpio_reg_offs *regs; | ||
| 207 | |||
| 208 | /* Return context loss count due to PM states changing */ | ||
| 209 | int (*get_context_loss_count)(struct device *dev); | ||
| 210 | }; | ||
| 211 | |||
| 212 | extern void omap2_gpio_prepare_for_idle(int off_mode); | ||
| 213 | extern void omap2_gpio_resume_after_idle(void); | ||
| 214 | extern void omap_set_gpio_debounce(int gpio, int enable); | ||
| 215 | extern void omap_set_gpio_debounce_time(int gpio, int enable); | ||
| 216 | /*-------------------------------------------------------------------------*/ | ||
| 217 | |||
| 218 | /* | ||
| 219 | * Wrappers for "new style" GPIO calls, using the new infrastructure | ||
| 220 | * which lets us plug in FPGA, I2C, and other implementations. | ||
| 221 | * | ||
| 222 | * The original OMAP-specific calls should eventually be removed. | ||
| 223 | */ | ||
| 224 | |||
| 225 | #include <linux/errno.h> | ||
| 226 | #include <asm-generic/gpio.h> | ||
| 227 | |||
| 228 | #endif | ||
diff --git a/arch/arm/plat-omap/include/plat/gpmc.h b/arch/arm/plat-omap/include/plat/gpmc.h index f37764a36072..2e6e2597178c 100644 --- a/arch/arm/plat-omap/include/plat/gpmc.h +++ b/arch/arm/plat-omap/include/plat/gpmc.h | |||
| @@ -133,6 +133,25 @@ struct gpmc_timings { | |||
| 133 | u16 wr_data_mux_bus; /* WRDATAONADMUXBUS */ | 133 | u16 wr_data_mux_bus; /* WRDATAONADMUXBUS */ |
| 134 | }; | 134 | }; |
| 135 | 135 | ||
| 136 | struct gpmc_nand_regs { | ||
| 137 | void __iomem *gpmc_status; | ||
| 138 | void __iomem *gpmc_nand_command; | ||
| 139 | void __iomem *gpmc_nand_address; | ||
| 140 | void __iomem *gpmc_nand_data; | ||
| 141 | void __iomem *gpmc_prefetch_config1; | ||
| 142 | void __iomem *gpmc_prefetch_config2; | ||
| 143 | void __iomem *gpmc_prefetch_control; | ||
| 144 | void __iomem *gpmc_prefetch_status; | ||
| 145 | void __iomem *gpmc_ecc_config; | ||
| 146 | void __iomem *gpmc_ecc_control; | ||
| 147 | void __iomem *gpmc_ecc_size_config; | ||
| 148 | void __iomem *gpmc_ecc1_result; | ||
| 149 | void __iomem *gpmc_bch_result0; | ||
| 150 | }; | ||
| 151 | |||
| 152 | extern void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs); | ||
| 153 | extern int gpmc_get_client_irq(unsigned irq_config); | ||
| 154 | |||
| 136 | extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns); | 155 | extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns); |
| 137 | extern unsigned int gpmc_ps_to_ticks(unsigned int time_ps); | 156 | extern unsigned int gpmc_ps_to_ticks(unsigned int time_ps); |
| 138 | extern unsigned int gpmc_ticks_to_ns(unsigned int ticks); | 157 | extern unsigned int gpmc_ticks_to_ns(unsigned int ticks); |
diff --git a/arch/arm/plat-omap/include/plat/hardware.h b/arch/arm/plat-omap/include/plat/hardware.h deleted file mode 100644 index ddbde38e1e33..000000000000 --- a/arch/arm/plat-omap/include/plat/hardware.h +++ /dev/null | |||
| @@ -1,293 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/plat-omap/include/mach/hardware.h | ||
| 3 | * | ||
| 4 | * Hardware definitions for TI OMAP processors and boards | ||
| 5 | * | ||
| 6 | * NOTE: Please put device driver specific defines into a separate header | ||
| 7 | * file for each driver. | ||
| 8 | * | ||
| 9 | * Copyright (C) 2001 RidgeRun, Inc. | ||
| 10 | * Author: RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com> | ||
| 11 | * | ||
| 12 | * Reorganized for Linux-2.6 by Tony Lindgren <tony@atomide.com> | ||
| 13 | * and Dirk Behme <dirk.behme@de.bosch.com> | ||
| 14 | * | ||
| 15 | * This program is free software; you can redistribute it and/or modify it | ||
| 16 | * under the terms of the GNU General Public License as published by the | ||
| 17 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 18 | * option) any later version. | ||
| 19 | * | ||
| 20 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
| 21 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
| 22 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
| 23 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
| 24 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
| 25 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
| 26 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
| 27 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
| 28 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
| 29 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
| 30 | * | ||
| 31 | * You should have received a copy of the GNU General Public License along | ||
| 32 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 33 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 34 | */ | ||
| 35 | |||
| 36 | #ifndef __ASM_ARCH_OMAP_HARDWARE_H | ||
| 37 | #define __ASM_ARCH_OMAP_HARDWARE_H | ||
| 38 | |||
| 39 | #include <asm/sizes.h> | ||
| 40 | #ifndef __ASSEMBLER__ | ||
| 41 | #include <asm/types.h> | ||
| 42 | #include <plat/cpu.h> | ||
| 43 | #endif | ||
| 44 | #include <plat/serial.h> | ||
| 45 | |||
| 46 | /* | ||
| 47 | * --------------------------------------------------------------------------- | ||
| 48 | * Common definitions for all OMAP processors | ||
| 49 | * NOTE: Put all processor or board specific parts to the special header | ||
| 50 | * files. | ||
| 51 | * --------------------------------------------------------------------------- | ||
| 52 | */ | ||
| 53 | |||
| 54 | /* | ||
| 55 | * ---------------------------------------------------------------------------- | ||
| 56 | * Timers | ||
| 57 | * ---------------------------------------------------------------------------- | ||
| 58 | */ | ||
| 59 | #define OMAP_MPU_TIMER1_BASE (0xfffec500) | ||
| 60 | #define OMAP_MPU_TIMER2_BASE (0xfffec600) | ||
| 61 | #define OMAP_MPU_TIMER3_BASE (0xfffec700) | ||
| 62 | #define MPU_TIMER_FREE (1 << 6) | ||
| 63 | #define MPU_TIMER_CLOCK_ENABLE (1 << 5) | ||
| 64 | #define MPU_TIMER_AR (1 << 1) | ||
| 65 | #define MPU_TIMER_ST (1 << 0) | ||
| 66 | |||
| 67 | /* | ||
| 68 | * ---------------------------------------------------------------------------- | ||
| 69 | * Clocks | ||
| 70 | * ---------------------------------------------------------------------------- | ||
| 71 | */ | ||
| 72 | #define CLKGEN_REG_BASE (0xfffece00) | ||
| 73 | #define ARM_CKCTL (CLKGEN_REG_BASE + 0x0) | ||
| 74 | #define ARM_IDLECT1 (CLKGEN_REG_BASE + 0x4) | ||
| 75 | #define ARM_IDLECT2 (CLKGEN_REG_BASE + 0x8) | ||
| 76 | #define ARM_EWUPCT (CLKGEN_REG_BASE + 0xC) | ||
| 77 | #define ARM_RSTCT1 (CLKGEN_REG_BASE + 0x10) | ||
| 78 | #define ARM_RSTCT2 (CLKGEN_REG_BASE + 0x14) | ||
| 79 | #define ARM_SYSST (CLKGEN_REG_BASE + 0x18) | ||
| 80 | #define ARM_IDLECT3 (CLKGEN_REG_BASE + 0x24) | ||
| 81 | |||
| 82 | #define CK_RATEF 1 | ||
| 83 | #define CK_IDLEF 2 | ||
| 84 | #define CK_ENABLEF 4 | ||
| 85 | #define CK_SELECTF 8 | ||
| 86 | #define SETARM_IDLE_SHIFT | ||
| 87 | |||
| 88 | /* DPLL control registers */ | ||
| 89 | #define DPLL_CTL (0xfffecf00) | ||
| 90 | |||
| 91 | /* DSP clock control. Must use __raw_readw() and __raw_writew() with these */ | ||
| 92 | #define DSP_CONFIG_REG_BASE IOMEM(0xe1008000) | ||
| 93 | #define DSP_CKCTL (DSP_CONFIG_REG_BASE + 0x0) | ||
| 94 | #define DSP_IDLECT1 (DSP_CONFIG_REG_BASE + 0x4) | ||
| 95 | #define DSP_IDLECT2 (DSP_CONFIG_REG_BASE + 0x8) | ||
| 96 | #define DSP_RSTCT2 (DSP_CONFIG_REG_BASE + 0x14) | ||
| 97 | |||
| 98 | /* | ||
| 99 | * --------------------------------------------------------------------------- | ||
| 100 | * UPLD | ||
| 101 | * --------------------------------------------------------------------------- | ||
| 102 | */ | ||
| 103 | #define ULPD_REG_BASE (0xfffe0800) | ||
| 104 | #define ULPD_IT_STATUS (ULPD_REG_BASE + 0x14) | ||
| 105 | #define ULPD_SETUP_ANALOG_CELL_3 (ULPD_REG_BASE + 0x24) | ||
| 106 | #define ULPD_CLOCK_CTRL (ULPD_REG_BASE + 0x30) | ||
| 107 | # define DIS_USB_PVCI_CLK (1 << 5) /* no USB/FAC synch */ | ||
| 108 | # define USB_MCLK_EN (1 << 4) /* enable W4_USB_CLKO */ | ||
| 109 | #define ULPD_SOFT_REQ (ULPD_REG_BASE + 0x34) | ||
| 110 | # define SOFT_UDC_REQ (1 << 4) | ||
| 111 | # define SOFT_USB_CLK_REQ (1 << 3) | ||
| 112 | # define SOFT_DPLL_REQ (1 << 0) | ||
| 113 | #define ULPD_DPLL_CTRL (ULPD_REG_BASE + 0x3c) | ||
| 114 | #define ULPD_STATUS_REQ (ULPD_REG_BASE + 0x40) | ||
| 115 | #define ULPD_APLL_CTRL (ULPD_REG_BASE + 0x4c) | ||
| 116 | #define ULPD_POWER_CTRL (ULPD_REG_BASE + 0x50) | ||
| 117 | #define ULPD_SOFT_DISABLE_REQ_REG (ULPD_REG_BASE + 0x68) | ||
| 118 | # define DIS_MMC2_DPLL_REQ (1 << 11) | ||
| 119 | # define DIS_MMC1_DPLL_REQ (1 << 10) | ||
| 120 | # define DIS_UART3_DPLL_REQ (1 << 9) | ||
| 121 | # define DIS_UART2_DPLL_REQ (1 << 8) | ||
| 122 | # define DIS_UART1_DPLL_REQ (1 << 7) | ||
| 123 | # define DIS_USB_HOST_DPLL_REQ (1 << 6) | ||
| 124 | #define ULPD_SDW_CLK_DIV_CTRL_SEL (ULPD_REG_BASE + 0x74) | ||
| 125 | #define ULPD_CAM_CLK_CTRL (ULPD_REG_BASE + 0x7c) | ||
| 126 | |||
| 127 | /* | ||
| 128 | * --------------------------------------------------------------------------- | ||
| 129 | * Watchdog timer | ||
| 130 | * --------------------------------------------------------------------------- | ||
| 131 | */ | ||
| 132 | |||
| 133 | /* Watchdog timer within the OMAP3.2 gigacell */ | ||
| 134 | #define OMAP_MPU_WATCHDOG_BASE (0xfffec800) | ||
| 135 | #define OMAP_WDT_TIMER (OMAP_MPU_WATCHDOG_BASE + 0x0) | ||
| 136 | #define OMAP_WDT_LOAD_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4) | ||
| 137 | #define OMAP_WDT_READ_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4) | ||
| 138 | #define OMAP_WDT_TIMER_MODE (OMAP_MPU_WATCHDOG_BASE + 0x8) | ||
| 139 | |||
| 140 | /* | ||
| 141 | * --------------------------------------------------------------------------- | ||
| 142 | * Interrupts | ||
| 143 | * --------------------------------------------------------------------------- | ||
| 144 | */ | ||
| 145 | #ifdef CONFIG_ARCH_OMAP1 | ||
| 146 | |||
| 147 | /* | ||
| 148 | * XXX: These probably want to be moved to arch/arm/mach-omap/omap1/irq.c | ||
| 149 | * or something similar.. -- PFM. | ||
| 150 | */ | ||
| 151 | |||
| 152 | #define OMAP_IH1_BASE 0xfffecb00 | ||
| 153 | #define OMAP_IH2_BASE 0xfffe0000 | ||
| 154 | |||
| 155 | #define OMAP_IH1_ITR (OMAP_IH1_BASE + 0x00) | ||
| 156 | #define OMAP_IH1_MIR (OMAP_IH1_BASE + 0x04) | ||
| 157 | #define OMAP_IH1_SIR_IRQ (OMAP_IH1_BASE + 0x10) | ||
| 158 | #define OMAP_IH1_SIR_FIQ (OMAP_IH1_BASE + 0x14) | ||
| 159 | #define OMAP_IH1_CONTROL (OMAP_IH1_BASE + 0x18) | ||
| 160 | #define OMAP_IH1_ILR0 (OMAP_IH1_BASE + 0x1c) | ||
| 161 | #define OMAP_IH1_ISR (OMAP_IH1_BASE + 0x9c) | ||
| 162 | |||
| 163 | #define OMAP_IH2_ITR (OMAP_IH2_BASE + 0x00) | ||
| 164 | #define OMAP_IH2_MIR (OMAP_IH2_BASE + 0x04) | ||
| 165 | #define OMAP_IH2_SIR_IRQ (OMAP_IH2_BASE + 0x10) | ||
| 166 | #define OMAP_IH2_SIR_FIQ (OMAP_IH2_BASE + 0x14) | ||
| 167 | #define OMAP_IH2_CONTROL (OMAP_IH2_BASE + 0x18) | ||
| 168 | #define OMAP_IH2_ILR0 (OMAP_IH2_BASE + 0x1c) | ||
| 169 | #define OMAP_IH2_ISR (OMAP_IH2_BASE + 0x9c) | ||
| 170 | |||
| 171 | #define IRQ_ITR_REG_OFFSET 0x00 | ||
| 172 | #define IRQ_MIR_REG_OFFSET 0x04 | ||
| 173 | #define IRQ_SIR_IRQ_REG_OFFSET 0x10 | ||
| 174 | #define IRQ_SIR_FIQ_REG_OFFSET 0x14 | ||
| 175 | #define IRQ_CONTROL_REG_OFFSET 0x18 | ||
| 176 | #define IRQ_ISR_REG_OFFSET 0x9c | ||
| 177 | #define IRQ_ILR0_REG_OFFSET 0x1c | ||
| 178 | #define IRQ_GMR_REG_OFFSET 0xa0 | ||
| 179 | |||
| 180 | #endif | ||
| 181 | |||
| 182 | /* | ||
| 183 | * ---------------------------------------------------------------------------- | ||
| 184 | * System control registers | ||
| 185 | * ---------------------------------------------------------------------------- | ||
| 186 | */ | ||
| 187 | #define MOD_CONF_CTRL_0 0xfffe1080 | ||
| 188 | #define MOD_CONF_CTRL_1 0xfffe1110 | ||
| 189 | |||
| 190 | /* | ||
| 191 | * ---------------------------------------------------------------------------- | ||
| 192 | * Pin multiplexing registers | ||
| 193 | * ---------------------------------------------------------------------------- | ||
| 194 | */ | ||
| 195 | #define FUNC_MUX_CTRL_0 0xfffe1000 | ||
| 196 | #define FUNC_MUX_CTRL_1 0xfffe1004 | ||
| 197 | #define FUNC_MUX_CTRL_2 0xfffe1008 | ||
| 198 | #define COMP_MODE_CTRL_0 0xfffe100c | ||
| 199 | #define FUNC_MUX_CTRL_3 0xfffe1010 | ||
| 200 | #define FUNC_MUX_CTRL_4 0xfffe1014 | ||
| 201 | #define FUNC_MUX_CTRL_5 0xfffe1018 | ||
| 202 | #define FUNC_MUX_CTRL_6 0xfffe101C | ||
| 203 | #define FUNC_MUX_CTRL_7 0xfffe1020 | ||
| 204 | #define FUNC_MUX_CTRL_8 0xfffe1024 | ||
| 205 | #define FUNC_MUX_CTRL_9 0xfffe1028 | ||
| 206 | #define FUNC_MUX_CTRL_A 0xfffe102C | ||
| 207 | #define FUNC_MUX_CTRL_B 0xfffe1030 | ||
| 208 | #define FUNC_MUX_CTRL_C 0xfffe1034 | ||
| 209 | #define FUNC_MUX_CTRL_D 0xfffe1038 | ||
| 210 | #define PULL_DWN_CTRL_0 0xfffe1040 | ||
| 211 | #define PULL_DWN_CTRL_1 0xfffe1044 | ||
| 212 | #define PULL_DWN_CTRL_2 0xfffe1048 | ||
| 213 | #define PULL_DWN_CTRL_3 0xfffe104c | ||
| 214 | #define PULL_DWN_CTRL_4 0xfffe10ac | ||
| 215 | |||
| 216 | /* OMAP-1610 specific multiplexing registers */ | ||
| 217 | #define FUNC_MUX_CTRL_E 0xfffe1090 | ||
| 218 | #define FUNC_MUX_CTRL_F 0xfffe1094 | ||
| 219 | #define FUNC_MUX_CTRL_10 0xfffe1098 | ||
| 220 | #define FUNC_MUX_CTRL_11 0xfffe109c | ||
| 221 | #define FUNC_MUX_CTRL_12 0xfffe10a0 | ||
| 222 | #define PU_PD_SEL_0 0xfffe10b4 | ||
| 223 | #define PU_PD_SEL_1 0xfffe10b8 | ||
| 224 | #define PU_PD_SEL_2 0xfffe10bc | ||
| 225 | #define PU_PD_SEL_3 0xfffe10c0 | ||
| 226 | #define PU_PD_SEL_4 0xfffe10c4 | ||
| 227 | |||
| 228 | /* Timer32K for 1610 and 1710*/ | ||
| 229 | #define OMAP_TIMER32K_BASE 0xFFFBC400 | ||
| 230 | |||
| 231 | /* | ||
| 232 | * --------------------------------------------------------------------------- | ||
| 233 | * TIPB bus interface | ||
| 234 | * --------------------------------------------------------------------------- | ||
| 235 | */ | ||
| 236 | #define TIPB_PUBLIC_CNTL_BASE 0xfffed300 | ||
| 237 | #define MPU_PUBLIC_TIPB_CNTL (TIPB_PUBLIC_CNTL_BASE + 0x8) | ||
| 238 | #define TIPB_PRIVATE_CNTL_BASE 0xfffeca00 | ||
| 239 | #define MPU_PRIVATE_TIPB_CNTL (TIPB_PRIVATE_CNTL_BASE + 0x8) | ||
| 240 | |||
| 241 | /* | ||
| 242 | * ---------------------------------------------------------------------------- | ||
| 243 | * MPUI interface | ||
| 244 | * ---------------------------------------------------------------------------- | ||
| 245 | */ | ||
| 246 | #define MPUI_BASE (0xfffec900) | ||
| 247 | #define MPUI_CTRL (MPUI_BASE + 0x0) | ||
| 248 | #define MPUI_DEBUG_ADDR (MPUI_BASE + 0x4) | ||
| 249 | #define MPUI_DEBUG_DATA (MPUI_BASE + 0x8) | ||
| 250 | #define MPUI_DEBUG_FLAG (MPUI_BASE + 0xc) | ||
| 251 | #define MPUI_STATUS_REG (MPUI_BASE + 0x10) | ||
| 252 | #define MPUI_DSP_STATUS (MPUI_BASE + 0x14) | ||
| 253 | #define MPUI_DSP_BOOT_CONFIG (MPUI_BASE + 0x18) | ||
| 254 | #define MPUI_DSP_API_CONFIG (MPUI_BASE + 0x1c) | ||
| 255 | |||
| 256 | /* | ||
| 257 | * ---------------------------------------------------------------------------- | ||
| 258 | * LED Pulse Generator | ||
| 259 | * ---------------------------------------------------------------------------- | ||
| 260 | */ | ||
| 261 | #define OMAP_LPG1_BASE 0xfffbd000 | ||
| 262 | #define OMAP_LPG2_BASE 0xfffbd800 | ||
| 263 | #define OMAP_LPG1_LCR (OMAP_LPG1_BASE + 0x00) | ||
| 264 | #define OMAP_LPG1_PMR (OMAP_LPG1_BASE + 0x04) | ||
| 265 | #define OMAP_LPG2_LCR (OMAP_LPG2_BASE + 0x00) | ||
| 266 | #define OMAP_LPG2_PMR (OMAP_LPG2_BASE + 0x04) | ||
| 267 | |||
| 268 | /* | ||
| 269 | * ---------------------------------------------------------------------------- | ||
| 270 | * Pulse-Width Light | ||
| 271 | * ---------------------------------------------------------------------------- | ||
| 272 | */ | ||
| 273 | #define OMAP_PWL_BASE 0xfffb5800 | ||
| 274 | #define OMAP_PWL_ENABLE (OMAP_PWL_BASE + 0x00) | ||
| 275 | #define OMAP_PWL_CLK_ENABLE (OMAP_PWL_BASE + 0x04) | ||
| 276 | |||
| 277 | /* | ||
| 278 | * --------------------------------------------------------------------------- | ||
| 279 | * Processor specific defines | ||
| 280 | * --------------------------------------------------------------------------- | ||
| 281 | */ | ||
| 282 | |||
| 283 | #include <plat/omap7xx.h> | ||
| 284 | #include <plat/omap1510.h> | ||
| 285 | #include <plat/omap16xx.h> | ||
| 286 | #include <plat/omap24xx.h> | ||
| 287 | #include <plat/omap34xx.h> | ||
| 288 | #include <plat/omap44xx.h> | ||
| 289 | #include <plat/ti81xx.h> | ||
| 290 | #include <plat/am33xx.h> | ||
| 291 | #include <plat/omap54xx.h> | ||
| 292 | |||
| 293 | #endif /* __ASM_ARCH_OMAP_HARDWARE_H */ | ||
diff --git a/arch/arm/plat-omap/include/plat/irqs-44xx.h b/arch/arm/plat-omap/include/plat/irqs-44xx.h deleted file mode 100644 index 518322c80116..000000000000 --- a/arch/arm/plat-omap/include/plat/irqs-44xx.h +++ /dev/null | |||
| @@ -1,144 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * OMAP4 Interrupt lines definitions | ||
| 3 | * | ||
| 4 | * Copyright (C) 2009-2010 Texas Instruments, Inc. | ||
| 5 | * | ||
| 6 | * Santosh Shilimkar (santosh.shilimkar@ti.com) | ||
| 7 | * Benoit Cousson (b-cousson@ti.com) | ||
| 8 | * | ||
| 9 | * This file is automatically generated from the OMAP hardware databases. | ||
| 10 | * We respectfully ask that any modifications to this file be coordinated | ||
| 11 | * with the public linux-omap@vger.kernel.org mailing list and the | ||
| 12 | * authors above to ensure that the autogeneration scripts are kept | ||
| 13 | * up-to-date with the file contents. | ||
| 14 | * | ||
| 15 | * This program is free software; you can redistribute it and/or modify | ||
| 16 | * it under the terms of the GNU General Public License version 2 as | ||
| 17 | * published by the Free Software Foundation. | ||
| 18 | */ | ||
| 19 | |||
| 20 | #ifndef __ARCH_ARM_MACH_OMAP2_OMAP44XX_IRQS_H | ||
| 21 | #define __ARCH_ARM_MACH_OMAP2_OMAP44XX_IRQS_H | ||
| 22 | |||
| 23 | /* OMAP44XX IRQs numbers definitions */ | ||
| 24 | #define OMAP44XX_IRQ_LOCALTIMER 29 | ||
| 25 | #define OMAP44XX_IRQ_LOCALWDT 30 | ||
| 26 | |||
| 27 | #define OMAP44XX_IRQ_GIC_START 32 | ||
| 28 | |||
| 29 | #define OMAP44XX_IRQ_PL310 (0 + OMAP44XX_IRQ_GIC_START) | ||
| 30 | #define OMAP44XX_IRQ_CTI0 (1 + OMAP44XX_IRQ_GIC_START) | ||
| 31 | #define OMAP44XX_IRQ_CTI1 (2 + OMAP44XX_IRQ_GIC_START) | ||
| 32 | #define OMAP44XX_IRQ_ELM (4 + OMAP44XX_IRQ_GIC_START) | ||
| 33 | #define OMAP44XX_IRQ_SYS_1N (7 + OMAP44XX_IRQ_GIC_START) | ||
| 34 | #define OMAP44XX_IRQ_SECURITY_EVENTS (8 + OMAP44XX_IRQ_GIC_START) | ||
| 35 | #define OMAP44XX_IRQ_L3_DBG (9 + OMAP44XX_IRQ_GIC_START) | ||
| 36 | #define OMAP44XX_IRQ_L3_APP (10 + OMAP44XX_IRQ_GIC_START) | ||
| 37 | #define OMAP44XX_IRQ_PRCM (11 + OMAP44XX_IRQ_GIC_START) | ||
| 38 | #define OMAP44XX_IRQ_SDMA_0 (12 + OMAP44XX_IRQ_GIC_START) | ||
| 39 | #define OMAP44XX_IRQ_SDMA_1 (13 + OMAP44XX_IRQ_GIC_START) | ||
| 40 | #define OMAP44XX_IRQ_SDMA_2 (14 + OMAP44XX_IRQ_GIC_START) | ||
| 41 | #define OMAP44XX_IRQ_SDMA_3 (15 + OMAP44XX_IRQ_GIC_START) | ||
| 42 | #define OMAP44XX_IRQ_MCBSP4 (16 + OMAP44XX_IRQ_GIC_START) | ||
| 43 | #define OMAP44XX_IRQ_MCBSP1 (17 + OMAP44XX_IRQ_GIC_START) | ||
| 44 | #define OMAP44XX_IRQ_SR_MCU (18 + OMAP44XX_IRQ_GIC_START) | ||
| 45 | #define OMAP44XX_IRQ_SR_CORE (19 + OMAP44XX_IRQ_GIC_START) | ||
| 46 | #define OMAP44XX_IRQ_GPMC (20 + OMAP44XX_IRQ_GIC_START) | ||
| 47 | #define OMAP44XX_IRQ_GFX (21 + OMAP44XX_IRQ_GIC_START) | ||
| 48 | #define OMAP44XX_IRQ_MCBSP2 (22 + OMAP44XX_IRQ_GIC_START) | ||
| 49 | #define OMAP44XX_IRQ_MCBSP3 (23 + OMAP44XX_IRQ_GIC_START) | ||
| 50 | #define OMAP44XX_IRQ_ISS_5 (24 + OMAP44XX_IRQ_GIC_START) | ||
| 51 | #define OMAP44XX_IRQ_DSS_DISPC (25 + OMAP44XX_IRQ_GIC_START) | ||
| 52 | #define OMAP44XX_IRQ_MAIL_U0 (26 + OMAP44XX_IRQ_GIC_START) | ||
| 53 | #define OMAP44XX_IRQ_C2C_SSCM_0 (27 + OMAP44XX_IRQ_GIC_START) | ||
| 54 | #define OMAP44XX_IRQ_TESLA_MMU (28 + OMAP44XX_IRQ_GIC_START) | ||
| 55 | #define OMAP44XX_IRQ_GPIO1 (29 + OMAP44XX_IRQ_GIC_START) | ||
| 56 | #define OMAP44XX_IRQ_GPIO2 (30 + OMAP44XX_IRQ_GIC_START) | ||
| 57 | #define OMAP44XX_IRQ_GPIO3 (31 + OMAP44XX_IRQ_GIC_START) | ||
| 58 | #define OMAP44XX_IRQ_GPIO4 (32 + OMAP44XX_IRQ_GIC_START) | ||
| 59 | #define OMAP44XX_IRQ_GPIO5 (33 + OMAP44XX_IRQ_GIC_START) | ||
| 60 | #define OMAP44XX_IRQ_GPIO6 (34 + OMAP44XX_IRQ_GIC_START) | ||
| 61 | #define OMAP44XX_IRQ_USIM (35 + OMAP44XX_IRQ_GIC_START) | ||
| 62 | #define OMAP44XX_IRQ_WDT3 (36 + OMAP44XX_IRQ_GIC_START) | ||
| 63 | #define OMAP44XX_IRQ_GPT1 (37 + OMAP44XX_IRQ_GIC_START) | ||
| 64 | #define OMAP44XX_IRQ_GPT2 (38 + OMAP44XX_IRQ_GIC_START) | ||
| 65 | #define OMAP44XX_IRQ_GPT3 (39 + OMAP44XX_IRQ_GIC_START) | ||
| 66 | #define OMAP44XX_IRQ_GPT4 (40 + OMAP44XX_IRQ_GIC_START) | ||
| 67 | #define OMAP44XX_IRQ_GPT5 (41 + OMAP44XX_IRQ_GIC_START) | ||
| 68 | #define OMAP44XX_IRQ_GPT6 (42 + OMAP44XX_IRQ_GIC_START) | ||
| 69 | #define OMAP44XX_IRQ_GPT7 (43 + OMAP44XX_IRQ_GIC_START) | ||
| 70 | #define OMAP44XX_IRQ_GPT8 (44 + OMAP44XX_IRQ_GIC_START) | ||
| 71 | #define OMAP44XX_IRQ_GPT9 (45 + OMAP44XX_IRQ_GIC_START) | ||
| 72 | #define OMAP44XX_IRQ_GPT10 (46 + OMAP44XX_IRQ_GIC_START) | ||
| 73 | #define OMAP44XX_IRQ_GPT11 (47 + OMAP44XX_IRQ_GIC_START) | ||
| 74 | #define OMAP44XX_IRQ_SPI4 (48 + OMAP44XX_IRQ_GIC_START) | ||
| 75 | #define OMAP44XX_IRQ_SHA1_S (49 + OMAP44XX_IRQ_GIC_START) | ||
| 76 | #define OMAP44XX_IRQ_FPKA_SINTREQUEST_S (50 + OMAP44XX_IRQ_GIC_START) | ||
| 77 | #define OMAP44XX_IRQ_SHA1_P (51 + OMAP44XX_IRQ_GIC_START) | ||
| 78 | #define OMAP44XX_IRQ_RNG (52 + OMAP44XX_IRQ_GIC_START) | ||
| 79 | #define OMAP44XX_IRQ_DSS_DSI1 (53 + OMAP44XX_IRQ_GIC_START) | ||
| 80 | #define OMAP44XX_IRQ_I2C1 (56 + OMAP44XX_IRQ_GIC_START) | ||
| 81 | #define OMAP44XX_IRQ_I2C2 (57 + OMAP44XX_IRQ_GIC_START) | ||
| 82 | #define OMAP44XX_IRQ_HDQ (58 + OMAP44XX_IRQ_GIC_START) | ||
| 83 | #define OMAP44XX_IRQ_MMC5 (59 + OMAP44XX_IRQ_GIC_START) | ||
| 84 | #define OMAP44XX_IRQ_I2C3 (61 + OMAP44XX_IRQ_GIC_START) | ||
| 85 | #define OMAP44XX_IRQ_I2C4 (62 + OMAP44XX_IRQ_GIC_START) | ||
| 86 | #define OMAP44XX_IRQ_AES2_S (63 + OMAP44XX_IRQ_GIC_START) | ||
| 87 | #define OMAP44XX_IRQ_AES2_P (64 + OMAP44XX_IRQ_GIC_START) | ||
| 88 | #define OMAP44XX_IRQ_SPI1 (65 + OMAP44XX_IRQ_GIC_START) | ||
| 89 | #define OMAP44XX_IRQ_SPI2 (66 + OMAP44XX_IRQ_GIC_START) | ||
| 90 | #define OMAP44XX_IRQ_HSI_P1 (67 + OMAP44XX_IRQ_GIC_START) | ||
| 91 | #define OMAP44XX_IRQ_HSI_P2 (68 + OMAP44XX_IRQ_GIC_START) | ||
| 92 | #define OMAP44XX_IRQ_FDIF_3 (69 + OMAP44XX_IRQ_GIC_START) | ||
| 93 | #define OMAP44XX_IRQ_UART4 (70 + OMAP44XX_IRQ_GIC_START) | ||
| 94 | #define OMAP44XX_IRQ_HSI_DMA (71 + OMAP44XX_IRQ_GIC_START) | ||
| 95 | #define OMAP44XX_IRQ_UART1 (72 + OMAP44XX_IRQ_GIC_START) | ||
| 96 | #define OMAP44XX_IRQ_UART2 (73 + OMAP44XX_IRQ_GIC_START) | ||
| 97 | #define OMAP44XX_IRQ_UART3 (74 + OMAP44XX_IRQ_GIC_START) | ||
| 98 | #define OMAP44XX_IRQ_PBIAS (75 + OMAP44XX_IRQ_GIC_START) | ||
| 99 | #define OMAP44XX_IRQ_OHCI (76 + OMAP44XX_IRQ_GIC_START) | ||
| 100 | #define OMAP44XX_IRQ_EHCI (77 + OMAP44XX_IRQ_GIC_START) | ||
| 101 | #define OMAP44XX_IRQ_TLL (78 + OMAP44XX_IRQ_GIC_START) | ||
| 102 | #define OMAP44XX_IRQ_AES1_S (79 + OMAP44XX_IRQ_GIC_START) | ||
| 103 | #define OMAP44XX_IRQ_WDT2 (80 + OMAP44XX_IRQ_GIC_START) | ||
| 104 | #define OMAP44XX_IRQ_DES_S (81 + OMAP44XX_IRQ_GIC_START) | ||
| 105 | #define OMAP44XX_IRQ_DES_P (82 + OMAP44XX_IRQ_GIC_START) | ||
| 106 | #define OMAP44XX_IRQ_MMC1 (83 + OMAP44XX_IRQ_GIC_START) | ||
| 107 | #define OMAP44XX_IRQ_DSS_DSI2 (84 + OMAP44XX_IRQ_GIC_START) | ||
| 108 | #define OMAP44XX_IRQ_AES1_P (85 + OMAP44XX_IRQ_GIC_START) | ||
| 109 | #define OMAP44XX_IRQ_MMC2 (86 + OMAP44XX_IRQ_GIC_START) | ||
| 110 | #define OMAP44XX_IRQ_MPU_ICR (87 + OMAP44XX_IRQ_GIC_START) | ||
| 111 | #define OMAP44XX_IRQ_C2C_SSCM_1 (88 + OMAP44XX_IRQ_GIC_START) | ||
| 112 | #define OMAP44XX_IRQ_FSUSB (89 + OMAP44XX_IRQ_GIC_START) | ||
| 113 | #define OMAP44XX_IRQ_FSUSB_SMI (90 + OMAP44XX_IRQ_GIC_START) | ||
| 114 | #define OMAP44XX_IRQ_SPI3 (91 + OMAP44XX_IRQ_GIC_START) | ||
| 115 | #define OMAP44XX_IRQ_HS_USB_MC_N (92 + OMAP44XX_IRQ_GIC_START) | ||
| 116 | #define OMAP44XX_IRQ_HS_USB_DMA_N (93 + OMAP44XX_IRQ_GIC_START) | ||
| 117 | #define OMAP44XX_IRQ_MMC3 (94 + OMAP44XX_IRQ_GIC_START) | ||
| 118 | #define OMAP44XX_IRQ_GPT12 (95 + OMAP44XX_IRQ_GIC_START) | ||
| 119 | #define OMAP44XX_IRQ_MMC4 (96 + OMAP44XX_IRQ_GIC_START) | ||
| 120 | #define OMAP44XX_IRQ_SLIMBUS1 (97 + OMAP44XX_IRQ_GIC_START) | ||
| 121 | #define OMAP44XX_IRQ_SLIMBUS2 (98 + OMAP44XX_IRQ_GIC_START) | ||
| 122 | #define OMAP44XX_IRQ_ABE (99 + OMAP44XX_IRQ_GIC_START) | ||
| 123 | #define OMAP44XX_IRQ_DUCATI_MMU (100 + OMAP44XX_IRQ_GIC_START) | ||
| 124 | #define OMAP44XX_IRQ_DSS_HDMI (101 + OMAP44XX_IRQ_GIC_START) | ||
| 125 | #define OMAP44XX_IRQ_SR_IVA (102 + OMAP44XX_IRQ_GIC_START) | ||
| 126 | #define OMAP44XX_IRQ_IVA_HD_POSYNCITRPEND_1 (103 + OMAP44XX_IRQ_GIC_START) | ||
| 127 | #define OMAP44XX_IRQ_IVA_HD_POSYNCITRPEND_0 (104 + OMAP44XX_IRQ_GIC_START) | ||
| 128 | #define OMAP44XX_IRQ_IVA_HD_POMBINTRPEND_0 (107 + OMAP44XX_IRQ_GIC_START) | ||
| 129 | #define OMAP44XX_IRQ_MCASP1_AR (108 + OMAP44XX_IRQ_GIC_START) | ||
| 130 | #define OMAP44XX_IRQ_MCASP1_AX (109 + OMAP44XX_IRQ_GIC_START) | ||
| 131 | #define OMAP44XX_IRQ_EMIF4_1 (110 + OMAP44XX_IRQ_GIC_START) | ||
| 132 | #define OMAP44XX_IRQ_EMIF4_2 (111 + OMAP44XX_IRQ_GIC_START) | ||
| 133 | #define OMAP44XX_IRQ_MCPDM (112 + OMAP44XX_IRQ_GIC_START) | ||
| 134 | #define OMAP44XX_IRQ_DMM (113 + OMAP44XX_IRQ_GIC_START) | ||
| 135 | #define OMAP44XX_IRQ_DMIC (114 + OMAP44XX_IRQ_GIC_START) | ||
| 136 | #define OMAP44XX_IRQ_CDMA_0 (115 + OMAP44XX_IRQ_GIC_START) | ||
| 137 | #define OMAP44XX_IRQ_CDMA_1 (116 + OMAP44XX_IRQ_GIC_START) | ||
| 138 | #define OMAP44XX_IRQ_CDMA_2 (117 + OMAP44XX_IRQ_GIC_START) | ||
| 139 | #define OMAP44XX_IRQ_CDMA_3 (118 + OMAP44XX_IRQ_GIC_START) | ||
| 140 | #define OMAP44XX_IRQ_SYS_2N (119 + OMAP44XX_IRQ_GIC_START) | ||
| 141 | #define OMAP44XX_IRQ_KBD_CTL (120 + OMAP44XX_IRQ_GIC_START) | ||
| 142 | #define OMAP44XX_IRQ_UNIPRO1 (124 + OMAP44XX_IRQ_GIC_START) | ||
| 143 | |||
| 144 | #endif | ||
diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h deleted file mode 100644 index 37bbbbb981b2..000000000000 --- a/arch/arm/plat-omap/include/plat/irqs.h +++ /dev/null | |||
| @@ -1,453 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/plat-omap/include/mach/irqs.h | ||
| 3 | * | ||
| 4 | * Copyright (C) Greg Lonnon 2001 | ||
| 5 | * Updated for OMAP-1610 by Tony Lindgren <tony@atomide.com> | ||
| 6 | * | ||
| 7 | * Copyright (C) 2009 Texas Instruments | ||
| 8 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License as published by | ||
| 12 | * the Free Software Foundation; either version 2 of the License, or | ||
| 13 | * (at your option) any later version. | ||
| 14 | * | ||
| 15 | * This program is distributed in the hope that it will be useful, | ||
| 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 18 | * GNU General Public License for more details. | ||
| 19 | * | ||
| 20 | * You should have received a copy of the GNU General Public License | ||
| 21 | * along with this program; if not, write to the Free Software | ||
| 22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 23 | * | ||
| 24 | * NOTE: The interrupt vectors for the OMAP-1509, OMAP-1510, and OMAP-1610 | ||
| 25 | * are different. | ||
| 26 | */ | ||
| 27 | |||
| 28 | #ifndef __ASM_ARCH_OMAP15XX_IRQS_H | ||
| 29 | #define __ASM_ARCH_OMAP15XX_IRQS_H | ||
| 30 | |||
| 31 | /* All OMAP4 specific defines are moved to irqs-44xx.h */ | ||
| 32 | #include "irqs-44xx.h" | ||
| 33 | |||
| 34 | /* | ||
| 35 | * IRQ numbers for interrupt handler 1 | ||
| 36 | * | ||
| 37 | * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below | ||
| 38 | * | ||
| 39 | */ | ||
| 40 | #define INT_CAMERA 1 | ||
| 41 | #define INT_FIQ 3 | ||
| 42 | #define INT_RTDX 6 | ||
| 43 | #define INT_DSP_MMU_ABORT 7 | ||
| 44 | #define INT_HOST 8 | ||
| 45 | #define INT_ABORT 9 | ||
| 46 | #define INT_BRIDGE_PRIV 13 | ||
| 47 | #define INT_GPIO_BANK1 14 | ||
| 48 | #define INT_UART3 15 | ||
| 49 | #define INT_TIMER3 16 | ||
| 50 | #define INT_DMA_CH0_6 19 | ||
| 51 | #define INT_DMA_CH1_7 20 | ||
| 52 | #define INT_DMA_CH2_8 21 | ||
| 53 | #define INT_DMA_CH3 22 | ||
| 54 | #define INT_DMA_CH4 23 | ||
| 55 | #define INT_DMA_CH5 24 | ||
| 56 | #define INT_DMA_LCD 25 | ||
| 57 | #define INT_TIMER1 26 | ||
| 58 | #define INT_WD_TIMER 27 | ||
| 59 | #define INT_BRIDGE_PUB 28 | ||
| 60 | #define INT_TIMER2 30 | ||
| 61 | #define INT_LCD_CTRL 31 | ||
| 62 | |||
| 63 | /* | ||
| 64 | * OMAP-1510 specific IRQ numbers for interrupt handler 1 | ||
| 65 | */ | ||
| 66 | #define INT_1510_IH2_IRQ 0 | ||
| 67 | #define INT_1510_RES2 2 | ||
| 68 | #define INT_1510_SPI_TX 4 | ||
| 69 | #define INT_1510_SPI_RX 5 | ||
| 70 | #define INT_1510_DSP_MAILBOX1 10 | ||
| 71 | #define INT_1510_DSP_MAILBOX2 11 | ||
| 72 | #define INT_1510_RES12 12 | ||
| 73 | #define INT_1510_LB_MMU 17 | ||
| 74 | #define INT_1510_RES18 18 | ||
| 75 | #define INT_1510_LOCAL_BUS 29 | ||
| 76 | |||
| 77 | /* | ||
| 78 | * OMAP-1610 specific IRQ numbers for interrupt handler 1 | ||
| 79 | */ | ||
| 80 | #define INT_1610_IH2_IRQ INT_1510_IH2_IRQ | ||
| 81 | #define INT_1610_IH2_FIQ 2 | ||
| 82 | #define INT_1610_McBSP2_TX 4 | ||
| 83 | #define INT_1610_McBSP2_RX 5 | ||
| 84 | #define INT_1610_DSP_MAILBOX1 10 | ||
| 85 | #define INT_1610_DSP_MAILBOX2 11 | ||
| 86 | #define INT_1610_LCD_LINE 12 | ||
| 87 | #define INT_1610_GPTIMER1 17 | ||
| 88 | #define INT_1610_GPTIMER2 18 | ||
| 89 | #define INT_1610_SSR_FIFO_0 29 | ||
| 90 | |||
| 91 | /* | ||
| 92 | * OMAP-7xx specific IRQ numbers for interrupt handler 1 | ||
| 93 | */ | ||
| 94 | #define INT_7XX_IH2_FIQ 0 | ||
| 95 | #define INT_7XX_IH2_IRQ 1 | ||
| 96 | #define INT_7XX_USB_NON_ISO 2 | ||
| 97 | #define INT_7XX_USB_ISO 3 | ||
| 98 | #define INT_7XX_ICR 4 | ||
| 99 | #define INT_7XX_EAC 5 | ||
| 100 | #define INT_7XX_GPIO_BANK1 6 | ||
| 101 | #define INT_7XX_GPIO_BANK2 7 | ||
| 102 | #define INT_7XX_GPIO_BANK3 8 | ||
| 103 | #define INT_7XX_McBSP2TX 10 | ||
| 104 | #define INT_7XX_McBSP2RX 11 | ||
| 105 | #define INT_7XX_McBSP2RX_OVF 12 | ||
| 106 | #define INT_7XX_LCD_LINE 14 | ||
| 107 | #define INT_7XX_GSM_PROTECT 15 | ||
| 108 | #define INT_7XX_TIMER3 16 | ||
| 109 | #define INT_7XX_GPIO_BANK5 17 | ||
| 110 | #define INT_7XX_GPIO_BANK6 18 | ||
| 111 | #define INT_7XX_SPGIO_WR 29 | ||
| 112 | |||
| 113 | /* | ||
| 114 | * IRQ numbers for interrupt handler 2 | ||
| 115 | * | ||
| 116 | * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below | ||
| 117 | */ | ||
| 118 | #define IH2_BASE 32 | ||
| 119 | |||
| 120 | #define INT_KEYBOARD (1 + IH2_BASE) | ||
| 121 | #define INT_uWireTX (2 + IH2_BASE) | ||
| 122 | #define INT_uWireRX (3 + IH2_BASE) | ||
| 123 | #define INT_I2C (4 + IH2_BASE) | ||
| 124 | #define INT_MPUIO (5 + IH2_BASE) | ||
| 125 | #define INT_USB_HHC_1 (6 + IH2_BASE) | ||
| 126 | #define INT_McBSP3TX (10 + IH2_BASE) | ||
| 127 | #define INT_McBSP3RX (11 + IH2_BASE) | ||
| 128 | #define INT_McBSP1TX (12 + IH2_BASE) | ||
| 129 | #define INT_McBSP1RX (13 + IH2_BASE) | ||
| 130 | #define INT_UART1 (14 + IH2_BASE) | ||
| 131 | #define INT_UART2 (15 + IH2_BASE) | ||
| 132 | #define INT_BT_MCSI1TX (16 + IH2_BASE) | ||
| 133 | #define INT_BT_MCSI1RX (17 + IH2_BASE) | ||
| 134 | #define INT_SOSSI_MATCH (19 + IH2_BASE) | ||
| 135 | #define INT_USB_W2FC (20 + IH2_BASE) | ||
| 136 | #define INT_1WIRE (21 + IH2_BASE) | ||
| 137 | #define INT_OS_TIMER (22 + IH2_BASE) | ||
| 138 | #define INT_MMC (23 + IH2_BASE) | ||
| 139 | #define INT_GAUGE_32K (24 + IH2_BASE) | ||
| 140 | #define INT_RTC_TIMER (25 + IH2_BASE) | ||
| 141 | #define INT_RTC_ALARM (26 + IH2_BASE) | ||
| 142 | #define INT_MEM_STICK (27 + IH2_BASE) | ||
| 143 | |||
| 144 | /* | ||
| 145 | * OMAP-1510 specific IRQ numbers for interrupt handler 2 | ||
| 146 | */ | ||
| 147 | #define INT_1510_DSP_MMU (28 + IH2_BASE) | ||
| 148 | #define INT_1510_COM_SPI_RO (31 + IH2_BASE) | ||
| 149 | |||
| 150 | /* | ||
| 151 | * OMAP-1610 specific IRQ numbers for interrupt handler 2 | ||
| 152 | */ | ||
| 153 | #define INT_1610_FAC (0 + IH2_BASE) | ||
| 154 | #define INT_1610_USB_HHC_2 (7 + IH2_BASE) | ||
| 155 | #define INT_1610_USB_OTG (8 + IH2_BASE) | ||
| 156 | #define INT_1610_SoSSI (9 + IH2_BASE) | ||
| 157 | #define INT_1610_SoSSI_MATCH (19 + IH2_BASE) | ||
| 158 | #define INT_1610_DSP_MMU (28 + IH2_BASE) | ||
| 159 | #define INT_1610_McBSP2RX_OF (31 + IH2_BASE) | ||
| 160 | #define INT_1610_STI (32 + IH2_BASE) | ||
| 161 | #define INT_1610_STI_WAKEUP (33 + IH2_BASE) | ||
| 162 | #define INT_1610_GPTIMER3 (34 + IH2_BASE) | ||
| 163 | #define INT_1610_GPTIMER4 (35 + IH2_BASE) | ||
| 164 | #define INT_1610_GPTIMER5 (36 + IH2_BASE) | ||
| 165 | #define INT_1610_GPTIMER6 (37 + IH2_BASE) | ||
| 166 | #define INT_1610_GPTIMER7 (38 + IH2_BASE) | ||
| 167 | #define INT_1610_GPTIMER8 (39 + IH2_BASE) | ||
| 168 | #define INT_1610_GPIO_BANK2 (40 + IH2_BASE) | ||
| 169 | #define INT_1610_GPIO_BANK3 (41 + IH2_BASE) | ||
| 170 | #define INT_1610_MMC2 (42 + IH2_BASE) | ||
| 171 | #define INT_1610_CF (43 + IH2_BASE) | ||
| 172 | #define INT_1610_WAKE_UP_REQ (46 + IH2_BASE) | ||
| 173 | #define INT_1610_GPIO_BANK4 (48 + IH2_BASE) | ||
| 174 | #define INT_1610_SPI (49 + IH2_BASE) | ||
| 175 | #define INT_1610_DMA_CH6 (53 + IH2_BASE) | ||
| 176 | #define INT_1610_DMA_CH7 (54 + IH2_BASE) | ||
| 177 | #define INT_1610_DMA_CH8 (55 + IH2_BASE) | ||
| 178 | #define INT_1610_DMA_CH9 (56 + IH2_BASE) | ||
| 179 | #define INT_1610_DMA_CH10 (57 + IH2_BASE) | ||
| 180 | #define INT_1610_DMA_CH11 (58 + IH2_BASE) | ||
| 181 | #define INT_1610_DMA_CH12 (59 + IH2_BASE) | ||
| 182 | #define INT_1610_DMA_CH13 (60 + IH2_BASE) | ||
| 183 | #define INT_1610_DMA_CH14 (61 + IH2_BASE) | ||
| 184 | #define INT_1610_DMA_CH15 (62 + IH2_BASE) | ||
| 185 | #define INT_1610_NAND (63 + IH2_BASE) | ||
| 186 | #define INT_1610_SHA1MD5 (91 + IH2_BASE) | ||
| 187 | |||
| 188 | /* | ||
| 189 | * OMAP-7xx specific IRQ numbers for interrupt handler 2 | ||
| 190 | */ | ||
| 191 | #define INT_7XX_HW_ERRORS (0 + IH2_BASE) | ||
| 192 | #define INT_7XX_NFIQ_PWR_FAIL (1 + IH2_BASE) | ||
| 193 | #define INT_7XX_CFCD (2 + IH2_BASE) | ||
| 194 | #define INT_7XX_CFIREQ (3 + IH2_BASE) | ||
| 195 | #define INT_7XX_I2C (4 + IH2_BASE) | ||
| 196 | #define INT_7XX_PCC (5 + IH2_BASE) | ||
| 197 | #define INT_7XX_MPU_EXT_NIRQ (6 + IH2_BASE) | ||
| 198 | #define INT_7XX_SPI_100K_1 (7 + IH2_BASE) | ||
| 199 | #define INT_7XX_SYREN_SPI (8 + IH2_BASE) | ||
| 200 | #define INT_7XX_VLYNQ (9 + IH2_BASE) | ||
| 201 | #define INT_7XX_GPIO_BANK4 (10 + IH2_BASE) | ||
| 202 | #define INT_7XX_McBSP1TX (11 + IH2_BASE) | ||
| 203 | #define INT_7XX_McBSP1RX (12 + IH2_BASE) | ||
| 204 | #define INT_7XX_McBSP1RX_OF (13 + IH2_BASE) | ||
| 205 | #define INT_7XX_UART_MODEM_IRDA_2 (14 + IH2_BASE) | ||
| 206 | #define INT_7XX_UART_MODEM_1 (15 + IH2_BASE) | ||
| 207 | #define INT_7XX_MCSI (16 + IH2_BASE) | ||
| 208 | #define INT_7XX_uWireTX (17 + IH2_BASE) | ||
| 209 | #define INT_7XX_uWireRX (18 + IH2_BASE) | ||
| 210 | #define INT_7XX_SMC_CD (19 + IH2_BASE) | ||
| 211 | #define INT_7XX_SMC_IREQ (20 + IH2_BASE) | ||
| 212 | #define INT_7XX_HDQ_1WIRE (21 + IH2_BASE) | ||
| 213 | #define INT_7XX_TIMER32K (22 + IH2_BASE) | ||
| 214 | #define INT_7XX_MMC_SDIO (23 + IH2_BASE) | ||
| 215 | #define INT_7XX_UPLD (24 + IH2_BASE) | ||
| 216 | #define INT_7XX_USB_HHC_1 (27 + IH2_BASE) | ||
| 217 | #define INT_7XX_USB_HHC_2 (28 + IH2_BASE) | ||
| 218 | #define INT_7XX_USB_GENI (29 + IH2_BASE) | ||
| 219 | #define INT_7XX_USB_OTG (30 + IH2_BASE) | ||
| 220 | #define INT_7XX_CAMERA_IF (31 + IH2_BASE) | ||
| 221 | #define INT_7XX_RNG (32 + IH2_BASE) | ||
| 222 | #define INT_7XX_DUAL_MODE_TIMER (33 + IH2_BASE) | ||
| 223 | #define INT_7XX_DBB_RF_EN (34 + IH2_BASE) | ||
| 224 | #define INT_7XX_MPUIO_KEYPAD (35 + IH2_BASE) | ||
| 225 | #define INT_7XX_SHA1_MD5 (36 + IH2_BASE) | ||
| 226 | #define INT_7XX_SPI_100K_2 (37 + IH2_BASE) | ||
| 227 | #define INT_7XX_RNG_IDLE (38 + IH2_BASE) | ||
| 228 | #define INT_7XX_MPUIO (39 + IH2_BASE) | ||
| 229 | #define INT_7XX_LLPC_LCD_CTRL_CAN_BE_OFF (40 + IH2_BASE) | ||
| 230 | #define INT_7XX_LLPC_OE_FALLING (41 + IH2_BASE) | ||
| 231 | #define INT_7XX_LLPC_OE_RISING (42 + IH2_BASE) | ||
| 232 | #define INT_7XX_LLPC_VSYNC (43 + IH2_BASE) | ||
| 233 | #define INT_7XX_WAKE_UP_REQ (46 + IH2_BASE) | ||
| 234 | #define INT_7XX_DMA_CH6 (53 + IH2_BASE) | ||
| 235 | #define INT_7XX_DMA_CH7 (54 + IH2_BASE) | ||
| 236 | #define INT_7XX_DMA_CH8 (55 + IH2_BASE) | ||
| 237 | #define INT_7XX_DMA_CH9 (56 + IH2_BASE) | ||
| 238 | #define INT_7XX_DMA_CH10 (57 + IH2_BASE) | ||
| 239 | #define INT_7XX_DMA_CH11 (58 + IH2_BASE) | ||
| 240 | #define INT_7XX_DMA_CH12 (59 + IH2_BASE) | ||
| 241 | #define INT_7XX_DMA_CH13 (60 + IH2_BASE) | ||
| 242 | #define INT_7XX_DMA_CH14 (61 + IH2_BASE) | ||
| 243 | #define INT_7XX_DMA_CH15 (62 + IH2_BASE) | ||
| 244 | #define INT_7XX_NAND (63 + IH2_BASE) | ||
| 245 | |||
| 246 | #define INT_24XX_SYS_NIRQ 7 | ||
| 247 | #define INT_24XX_SDMA_IRQ0 12 | ||
| 248 | #define INT_24XX_SDMA_IRQ1 13 | ||
| 249 | #define INT_24XX_SDMA_IRQ2 14 | ||
| 250 | #define INT_24XX_SDMA_IRQ3 15 | ||
| 251 | #define INT_24XX_CAM_IRQ 24 | ||
| 252 | #define INT_24XX_DSS_IRQ 25 | ||
| 253 | #define INT_24XX_MAIL_U0_MPU 26 | ||
| 254 | #define INT_24XX_DSP_UMA 27 | ||
| 255 | #define INT_24XX_DSP_MMU 28 | ||
| 256 | #define INT_24XX_GPIO_BANK1 29 | ||
| 257 | #define INT_24XX_GPIO_BANK2 30 | ||
| 258 | #define INT_24XX_GPIO_BANK3 31 | ||
| 259 | #define INT_24XX_GPIO_BANK4 32 | ||
| 260 | #define INT_24XX_GPIO_BANK5 33 | ||
| 261 | #define INT_24XX_MAIL_U3_MPU 34 | ||
| 262 | #define INT_24XX_GPTIMER1 37 | ||
| 263 | #define INT_24XX_GPTIMER2 38 | ||
| 264 | #define INT_24XX_GPTIMER3 39 | ||
| 265 | #define INT_24XX_GPTIMER4 40 | ||
| 266 | #define INT_24XX_GPTIMER5 41 | ||
| 267 | #define INT_24XX_GPTIMER6 42 | ||
| 268 | #define INT_24XX_GPTIMER7 43 | ||
| 269 | #define INT_24XX_GPTIMER8 44 | ||
| 270 | #define INT_24XX_GPTIMER9 45 | ||
| 271 | #define INT_24XX_GPTIMER10 46 | ||
| 272 | #define INT_24XX_GPTIMER11 47 | ||
| 273 | #define INT_24XX_GPTIMER12 48 | ||
| 274 | #define INT_24XX_SHA1MD5 51 | ||
| 275 | #define INT_24XX_MCBSP4_IRQ_TX 54 | ||
| 276 | #define INT_24XX_MCBSP4_IRQ_RX 55 | ||
| 277 | #define INT_24XX_I2C1_IRQ 56 | ||
| 278 | #define INT_24XX_I2C2_IRQ 57 | ||
| 279 | #define INT_24XX_HDQ_IRQ 58 | ||
| 280 | #define INT_24XX_MCBSP1_IRQ_TX 59 | ||
| 281 | #define INT_24XX_MCBSP1_IRQ_RX 60 | ||
| 282 | #define INT_24XX_MCBSP2_IRQ_TX 62 | ||
| 283 | #define INT_24XX_MCBSP2_IRQ_RX 63 | ||
| 284 | #define INT_24XX_SPI1_IRQ 65 | ||
| 285 | #define INT_24XX_SPI2_IRQ 66 | ||
| 286 | #define INT_24XX_UART1_IRQ 72 | ||
| 287 | #define INT_24XX_UART2_IRQ 73 | ||
| 288 | #define INT_24XX_UART3_IRQ 74 | ||
| 289 | #define INT_24XX_USB_IRQ_GEN 75 | ||
| 290 | #define INT_24XX_USB_IRQ_NISO 76 | ||
| 291 | #define INT_24XX_USB_IRQ_ISO 77 | ||
| 292 | #define INT_24XX_USB_IRQ_HGEN 78 | ||
| 293 | #define INT_24XX_USB_IRQ_HSOF 79 | ||
| 294 | #define INT_24XX_USB_IRQ_OTG 80 | ||
| 295 | #define INT_24XX_MCBSP5_IRQ_TX 81 | ||
| 296 | #define INT_24XX_MCBSP5_IRQ_RX 82 | ||
| 297 | #define INT_24XX_MMC_IRQ 83 | ||
| 298 | #define INT_24XX_MMC2_IRQ 86 | ||
| 299 | #define INT_24XX_MCBSP3_IRQ_TX 89 | ||
| 300 | #define INT_24XX_MCBSP3_IRQ_RX 90 | ||
| 301 | #define INT_24XX_SPI3_IRQ 91 | ||
| 302 | |||
| 303 | #define INT_243X_MCBSP2_IRQ 16 | ||
| 304 | #define INT_243X_MCBSP3_IRQ 17 | ||
| 305 | #define INT_243X_MCBSP4_IRQ 18 | ||
| 306 | #define INT_243X_MCBSP5_IRQ 19 | ||
| 307 | #define INT_243X_MCBSP1_IRQ 64 | ||
| 308 | #define INT_243X_HS_USB_MC 92 | ||
| 309 | #define INT_243X_HS_USB_DMA 93 | ||
| 310 | #define INT_243X_CARKIT_IRQ 94 | ||
| 311 | |||
| 312 | #define INT_34XX_BENCH_MPU_EMUL 3 | ||
| 313 | #define INT_34XX_ST_MCBSP2_IRQ 4 | ||
| 314 | #define INT_34XX_ST_MCBSP3_IRQ 5 | ||
| 315 | #define INT_34XX_SSM_ABORT_IRQ 6 | ||
| 316 | #define INT_34XX_SYS_NIRQ 7 | ||
| 317 | #define INT_34XX_D2D_FW_IRQ 8 | ||
| 318 | #define INT_34XX_L3_DBG_IRQ 9 | ||
| 319 | #define INT_34XX_L3_APP_IRQ 10 | ||
| 320 | #define INT_34XX_PRCM_MPU_IRQ 11 | ||
| 321 | #define INT_34XX_MCBSP1_IRQ 16 | ||
| 322 | #define INT_34XX_MCBSP2_IRQ 17 | ||
| 323 | #define INT_34XX_GPMC_IRQ 20 | ||
| 324 | #define INT_34XX_MCBSP3_IRQ 22 | ||
| 325 | #define INT_34XX_MCBSP4_IRQ 23 | ||
| 326 | #define INT_34XX_CAM_IRQ 24 | ||
| 327 | #define INT_34XX_MCBSP5_IRQ 27 | ||
| 328 | #define INT_34XX_GPIO_BANK1 29 | ||
| 329 | #define INT_34XX_GPIO_BANK2 30 | ||
| 330 | #define INT_34XX_GPIO_BANK3 31 | ||
| 331 | #define INT_34XX_GPIO_BANK4 32 | ||
| 332 | #define INT_34XX_GPIO_BANK5 33 | ||
| 333 | #define INT_34XX_GPIO_BANK6 34 | ||
| 334 | #define INT_34XX_USIM_IRQ 35 | ||
| 335 | #define INT_34XX_WDT3_IRQ 36 | ||
| 336 | #define INT_34XX_SPI4_IRQ 48 | ||
| 337 | #define INT_34XX_SHA1MD52_IRQ 49 | ||
| 338 | #define INT_34XX_FPKA_READY_IRQ 50 | ||
| 339 | #define INT_34XX_SHA1MD51_IRQ 51 | ||
| 340 | #define INT_34XX_RNG_IRQ 52 | ||
| 341 | #define INT_34XX_I2C3_IRQ 61 | ||
| 342 | #define INT_34XX_FPKA_ERROR_IRQ 64 | ||
| 343 | #define INT_34XX_PBIAS_IRQ 75 | ||
| 344 | #define INT_34XX_OHCI_IRQ 76 | ||
| 345 | #define INT_34XX_EHCI_IRQ 77 | ||
| 346 | #define INT_34XX_TLL_IRQ 78 | ||
| 347 | #define INT_34XX_PARTHASH_IRQ 79 | ||
| 348 | #define INT_34XX_MMC3_IRQ 94 | ||
| 349 | #define INT_34XX_GPT12_IRQ 95 | ||
| 350 | |||
| 351 | #define INT_36XX_UART4_IRQ 80 | ||
| 352 | |||
| 353 | #define INT_35XX_HECC0_IRQ 24 | ||
| 354 | #define INT_35XX_HECC1_IRQ 28 | ||
| 355 | #define INT_35XX_EMAC_C0_RXTHRESH_IRQ 67 | ||
| 356 | #define INT_35XX_EMAC_C0_RX_PULSE_IRQ 68 | ||
| 357 | #define INT_35XX_EMAC_C0_TX_PULSE_IRQ 69 | ||
| 358 | #define INT_35XX_EMAC_C0_MISC_PULSE_IRQ 70 | ||
| 359 | #define INT_35XX_USBOTG_IRQ 71 | ||
| 360 | #define INT_35XX_UART4_IRQ 84 | ||
| 361 | #define INT_35XX_CCDC_VD0_IRQ 88 | ||
| 362 | #define INT_35XX_CCDC_VD1_IRQ 92 | ||
| 363 | #define INT_35XX_CCDC_VD2_IRQ 93 | ||
| 364 | |||
| 365 | /* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730/850) and | ||
| 366 | * 16 MPUIO lines */ | ||
| 367 | #define OMAP_MAX_GPIO_LINES 192 | ||
| 368 | #define IH_GPIO_BASE (128 + IH2_BASE) | ||
| 369 | #define IH_MPUIO_BASE (OMAP_MAX_GPIO_LINES + IH_GPIO_BASE) | ||
| 370 | #define OMAP_IRQ_END (IH_MPUIO_BASE + 16) | ||
| 371 | |||
| 372 | /* External FPGA handles interrupts on Innovator boards */ | ||
| 373 | #define OMAP_FPGA_IRQ_BASE (OMAP_IRQ_END) | ||
| 374 | #ifdef CONFIG_MACH_OMAP_INNOVATOR | ||
| 375 | #define OMAP_FPGA_NR_IRQS 24 | ||
| 376 | #else | ||
| 377 | #define OMAP_FPGA_NR_IRQS 0 | ||
| 378 | #endif | ||
| 379 | #define OMAP_FPGA_IRQ_END (OMAP_FPGA_IRQ_BASE + OMAP_FPGA_NR_IRQS) | ||
| 380 | |||
| 381 | /* External TWL4030 can handle interrupts on 2430 and 34xx boards */ | ||
| 382 | #define TWL4030_IRQ_BASE (OMAP_FPGA_IRQ_END) | ||
| 383 | #ifdef CONFIG_TWL4030_CORE | ||
| 384 | #define TWL4030_BASE_NR_IRQS 8 | ||
| 385 | #define TWL4030_PWR_NR_IRQS 8 | ||
| 386 | #else | ||
| 387 | #define TWL4030_BASE_NR_IRQS 0 | ||
| 388 | #define TWL4030_PWR_NR_IRQS 0 | ||
| 389 | #endif | ||
| 390 | #define TWL4030_IRQ_END (TWL4030_IRQ_BASE + TWL4030_BASE_NR_IRQS) | ||
| 391 | #define TWL4030_PWR_IRQ_BASE TWL4030_IRQ_END | ||
| 392 | #define TWL4030_PWR_IRQ_END (TWL4030_PWR_IRQ_BASE + TWL4030_PWR_NR_IRQS) | ||
| 393 | |||
| 394 | /* External TWL4030 gpio interrupts are optional */ | ||
| 395 | #define TWL4030_GPIO_IRQ_BASE TWL4030_PWR_IRQ_END | ||
| 396 | #ifdef CONFIG_GPIO_TWL4030 | ||
| 397 | #define TWL4030_GPIO_NR_IRQS 18 | ||
| 398 | #else | ||
| 399 | #define TWL4030_GPIO_NR_IRQS 0 | ||
| 400 | #endif | ||
| 401 | #define TWL4030_GPIO_IRQ_END (TWL4030_GPIO_IRQ_BASE + TWL4030_GPIO_NR_IRQS) | ||
| 402 | |||
| 403 | #define TWL6030_IRQ_BASE (OMAP_FPGA_IRQ_END) | ||
| 404 | #ifdef CONFIG_TWL4030_CORE | ||
| 405 | #define TWL6030_BASE_NR_IRQS 20 | ||
| 406 | #else | ||
| 407 | #define TWL6030_BASE_NR_IRQS 0 | ||
| 408 | #endif | ||
| 409 | #define TWL6030_IRQ_END (TWL6030_IRQ_BASE + TWL6030_BASE_NR_IRQS) | ||
| 410 | |||
| 411 | #define TWL6040_CODEC_IRQ_BASE TWL6030_IRQ_END | ||
| 412 | #ifdef CONFIG_TWL6040_CODEC | ||
| 413 | #define TWL6040_CODEC_NR_IRQS 6 | ||
| 414 | #else | ||
| 415 | #define TWL6040_CODEC_NR_IRQS 0 | ||
| 416 | #endif | ||
| 417 | #define TWL6040_CODEC_IRQ_END (TWL6040_CODEC_IRQ_BASE + TWL6040_CODEC_NR_IRQS) | ||
| 418 | |||
| 419 | /* Total number of interrupts depends on the enabled blocks above */ | ||
| 420 | #if (TWL4030_GPIO_IRQ_END > TWL6040_CODEC_IRQ_END) | ||
| 421 | #define TWL_IRQ_END TWL4030_GPIO_IRQ_END | ||
| 422 | #else | ||
| 423 | #define TWL_IRQ_END TWL6040_CODEC_IRQ_END | ||
| 424 | #endif | ||
| 425 | |||
| 426 | /* GPMC related */ | ||
| 427 | #define OMAP_GPMC_IRQ_BASE (TWL_IRQ_END) | ||
| 428 | #define OMAP_GPMC_NR_IRQS 8 | ||
| 429 | #define OMAP_GPMC_IRQ_END (OMAP_GPMC_IRQ_BASE + OMAP_GPMC_NR_IRQS) | ||
| 430 | |||
| 431 | /* PRCM IRQ handler */ | ||
| 432 | #ifdef CONFIG_ARCH_OMAP2PLUS | ||
| 433 | #define OMAP_PRCM_IRQ_BASE (OMAP_GPMC_IRQ_END) | ||
| 434 | #define OMAP_PRCM_NR_IRQS 64 | ||
| 435 | #define OMAP_PRCM_IRQ_END (OMAP_PRCM_IRQ_BASE + OMAP_PRCM_NR_IRQS) | ||
| 436 | #else | ||
| 437 | #define OMAP_PRCM_IRQ_END OMAP_GPMC_IRQ_END | ||
| 438 | #endif | ||
| 439 | |||
| 440 | #define NR_IRQS OMAP_PRCM_IRQ_END | ||
| 441 | |||
| 442 | #define OMAP_IRQ_BIT(irq) (1 << ((irq) % 32)) | ||
| 443 | |||
| 444 | #define INTCPS_NR_MIR_REGS 3 | ||
| 445 | #define INTCPS_NR_IRQS 96 | ||
| 446 | |||
| 447 | #include <mach/hardware.h> | ||
| 448 | |||
| 449 | #ifdef CONFIG_FIQ | ||
| 450 | #define FIQ_START 1024 | ||
| 451 | #endif | ||
| 452 | |||
| 453 | #endif | ||
diff --git a/arch/arm/plat-omap/include/plat/mmc.h b/arch/arm/plat-omap/include/plat/mmc.h index eb3e4d555343..8b4e4f2da2f5 100644 --- a/arch/arm/plat-omap/include/plat/mmc.h +++ b/arch/arm/plat-omap/include/plat/mmc.h | |||
| @@ -15,7 +15,6 @@ | |||
| 15 | #include <linux/device.h> | 15 | #include <linux/device.h> |
| 16 | #include <linux/mmc/host.h> | 16 | #include <linux/mmc/host.h> |
| 17 | 17 | ||
| 18 | #include <plat/board.h> | ||
| 19 | #include <plat/omap_hwmod.h> | 18 | #include <plat/omap_hwmod.h> |
| 20 | 19 | ||
| 21 | #define OMAP15XX_NR_MMC 1 | 20 | #define OMAP15XX_NR_MMC 1 |
diff --git a/arch/arm/plat-omap/include/plat/nand.h b/arch/arm/plat-omap/include/plat/nand.h index 67fc5060183e..1a68c1e5fe53 100644 --- a/arch/arm/plat-omap/include/plat/nand.h +++ b/arch/arm/plat-omap/include/plat/nand.h | |||
| @@ -24,11 +24,10 @@ struct omap_nand_platform_data { | |||
| 24 | struct gpmc_timings *gpmc_t; | 24 | struct gpmc_timings *gpmc_t; |
| 25 | int nr_parts; | 25 | int nr_parts; |
| 26 | bool dev_ready; | 26 | bool dev_ready; |
| 27 | int gpmc_irq; | ||
| 28 | enum nand_io xfer_type; | 27 | enum nand_io xfer_type; |
| 29 | unsigned long phys_base; | ||
| 30 | int devsize; | 28 | int devsize; |
| 31 | enum omap_ecc ecc_opt; | 29 | enum omap_ecc ecc_opt; |
| 30 | struct gpmc_nand_regs reg; | ||
| 32 | }; | 31 | }; |
| 33 | 32 | ||
| 34 | /* minimum size for IO mapping */ | 33 | /* minimum size for IO mapping */ |
diff --git a/arch/arm/plat-omap/include/plat/omap-serial.h b/arch/arm/plat-omap/include/plat/omap-serial.h index 1a52725ffcf2..a531149823bb 100644 --- a/arch/arm/plat-omap/include/plat/omap-serial.h +++ b/arch/arm/plat-omap/include/plat/omap-serial.h | |||
| @@ -18,7 +18,7 @@ | |||
| 18 | #define __OMAP_SERIAL_H__ | 18 | #define __OMAP_SERIAL_H__ |
| 19 | 19 | ||
| 20 | #include <linux/serial_core.h> | 20 | #include <linux/serial_core.h> |
| 21 | #include <linux/platform_device.h> | 21 | #include <linux/device.h> |
| 22 | #include <linux/pm_qos.h> | 22 | #include <linux/pm_qos.h> |
| 23 | 23 | ||
| 24 | #include <plat/mux.h> | 24 | #include <plat/mux.h> |
| @@ -42,10 +42,10 @@ | |||
| 42 | #define OMAP_UART_WER_MOD_WKUP 0X7F | 42 | #define OMAP_UART_WER_MOD_WKUP 0X7F |
| 43 | 43 | ||
| 44 | /* Enable XON/XOFF flow control on output */ | 44 | /* Enable XON/XOFF flow control on output */ |
| 45 | #define OMAP_UART_SW_TX 0x04 | 45 | #define OMAP_UART_SW_TX 0x8 |
| 46 | 46 | ||
| 47 | /* Enable XON/XOFF flow control on input */ | 47 | /* Enable XON/XOFF flow control on input */ |
| 48 | #define OMAP_UART_SW_RX 0x04 | 48 | #define OMAP_UART_SW_RX 0x2 |
| 49 | 49 | ||
| 50 | #define OMAP_UART_SYSC_RESET 0X07 | 50 | #define OMAP_UART_SYSC_RESET 0X07 |
| 51 | #define OMAP_UART_TCR_TRIG 0X0F | 51 | #define OMAP_UART_TCR_TRIG 0X0F |
| @@ -69,11 +69,14 @@ struct omap_uart_port_info { | |||
| 69 | unsigned int dma_rx_timeout; | 69 | unsigned int dma_rx_timeout; |
| 70 | unsigned int autosuspend_timeout; | 70 | unsigned int autosuspend_timeout; |
| 71 | unsigned int dma_rx_poll_rate; | 71 | unsigned int dma_rx_poll_rate; |
| 72 | int DTR_gpio; | ||
| 73 | int DTR_inverted; | ||
| 74 | int DTR_present; | ||
| 72 | 75 | ||
| 73 | int (*get_context_loss_count)(struct device *); | 76 | int (*get_context_loss_count)(struct device *); |
| 74 | void (*set_forceidle)(struct platform_device *); | 77 | void (*set_forceidle)(struct device *); |
| 75 | void (*set_noidle)(struct platform_device *); | 78 | void (*set_noidle)(struct device *); |
| 76 | void (*enable_wakeup)(struct platform_device *, bool); | 79 | void (*enable_wakeup)(struct device *, bool); |
| 77 | }; | 80 | }; |
| 78 | 81 | ||
| 79 | struct uart_omap_dma { | 82 | struct uart_omap_dma { |
| @@ -102,39 +105,4 @@ struct uart_omap_dma { | |||
| 102 | unsigned int rx_timeout; | 105 | unsigned int rx_timeout; |
| 103 | }; | 106 | }; |
| 104 | 107 | ||
| 105 | struct uart_omap_port { | ||
| 106 | struct uart_port port; | ||
| 107 | struct uart_omap_dma uart_dma; | ||
| 108 | struct platform_device *pdev; | ||
| 109 | |||
| 110 | unsigned char ier; | ||
| 111 | unsigned char lcr; | ||
| 112 | unsigned char mcr; | ||
| 113 | unsigned char fcr; | ||
| 114 | unsigned char efr; | ||
| 115 | unsigned char dll; | ||
| 116 | unsigned char dlh; | ||
| 117 | unsigned char mdr1; | ||
| 118 | unsigned char scr; | ||
| 119 | |||
| 120 | int use_dma; | ||
| 121 | /* | ||
| 122 | * Some bits in registers are cleared on a read, so they must | ||
| 123 | * be saved whenever the register is read but the bits will not | ||
| 124 | * be immediately processed. | ||
| 125 | */ | ||
| 126 | unsigned int lsr_break_flag; | ||
| 127 | unsigned char msr_saved_flags; | ||
| 128 | char name[20]; | ||
| 129 | unsigned long port_activity; | ||
| 130 | u32 context_loss_cnt; | ||
| 131 | u32 errata; | ||
| 132 | u8 wakeups_enabled; | ||
| 133 | |||
| 134 | struct pm_qos_request pm_qos_request; | ||
| 135 | u32 latency; | ||
| 136 | u32 calc_latency; | ||
| 137 | struct work_struct qos_work; | ||
| 138 | }; | ||
| 139 | |||
| 140 | #endif /* __OMAP_SERIAL_H__ */ | 108 | #endif /* __OMAP_SERIAL_H__ */ |
diff --git a/arch/arm/plat-omap/include/plat/omap4-keypad.h b/arch/arm/plat-omap/include/plat/omap4-keypad.h index 8ad0a377a54b..20de0d5a7e77 100644 --- a/arch/arm/plat-omap/include/plat/omap4-keypad.h +++ b/arch/arm/plat-omap/include/plat/omap4-keypad.h | |||
| @@ -1,6 +1,8 @@ | |||
| 1 | #ifndef ARCH_ARM_PLAT_OMAP4_KEYPAD_H | 1 | #ifndef ARCH_ARM_PLAT_OMAP4_KEYPAD_H |
| 2 | #define ARCH_ARM_PLAT_OMAP4_KEYPAD_H | 2 | #define ARCH_ARM_PLAT_OMAP4_KEYPAD_H |
| 3 | 3 | ||
| 4 | struct omap_board_data; | ||
| 5 | |||
| 4 | extern int omap4_keyboard_init(struct omap4_keypad_platform_data *, | 6 | extern int omap4_keyboard_init(struct omap4_keypad_platform_data *, |
| 5 | struct omap_board_data *); | 7 | struct omap_board_data *); |
| 6 | #endif | 8 | #endif |
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h index 6132972aff37..5857b9cd6eb9 100644 --- a/arch/arm/plat-omap/include/plat/omap_hwmod.h +++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h | |||
| @@ -615,6 +615,7 @@ int omap_hwmod_softreset(struct omap_hwmod *oh); | |||
| 615 | 615 | ||
| 616 | int omap_hwmod_count_resources(struct omap_hwmod *oh); | 616 | int omap_hwmod_count_resources(struct omap_hwmod *oh); |
| 617 | int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res); | 617 | int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res); |
| 618 | int omap_hwmod_fill_dma_resources(struct omap_hwmod *oh, struct resource *res); | ||
| 618 | int omap_hwmod_get_resource_byname(struct omap_hwmod *oh, unsigned int type, | 619 | int omap_hwmod_get_resource_byname(struct omap_hwmod *oh, unsigned int type, |
| 619 | const char *name, struct resource *res); | 620 | const char *name, struct resource *res); |
| 620 | 621 | ||
diff --git a/arch/arm/plat-omap/include/plat/usb.h b/arch/arm/plat-omap/include/plat/usb.h index 548a4c8d63df..bd20588c356b 100644 --- a/arch/arm/plat-omap/include/plat/usb.h +++ b/arch/arm/plat-omap/include/plat/usb.h | |||
| @@ -5,7 +5,6 @@ | |||
| 5 | 5 | ||
| 6 | #include <linux/io.h> | 6 | #include <linux/io.h> |
| 7 | #include <linux/usb/musb.h> | 7 | #include <linux/usb/musb.h> |
| 8 | #include <plat/board.h> | ||
| 9 | 8 | ||
| 10 | #define OMAP3_HS_USB_PORTS 3 | 9 | #define OMAP3_HS_USB_PORTS 3 |
| 11 | 10 | ||
diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c index c490240bb82c..6f5c58096819 100644 --- a/arch/arm/plat-omap/omap_device.c +++ b/arch/arm/plat-omap/omap_device.c | |||
| @@ -370,6 +370,14 @@ static int omap_device_build_from_dt(struct platform_device *pdev) | |||
| 370 | goto odbfd_exit1; | 370 | goto odbfd_exit1; |
| 371 | } | 371 | } |
| 372 | 372 | ||
| 373 | /* Fix up missing resource names */ | ||
| 374 | for (i = 0; i < pdev->num_resources; i++) { | ||
| 375 | struct resource *r = &pdev->resource[i]; | ||
| 376 | |||
| 377 | if (r->name == NULL) | ||
| 378 | r->name = dev_name(&pdev->dev); | ||
| 379 | } | ||
| 380 | |||
| 373 | if (of_get_property(node, "ti,no_idle_on_suspend", NULL)) | 381 | if (of_get_property(node, "ti,no_idle_on_suspend", NULL)) |
| 374 | omap_device_disable_idle_on_suspend(pdev); | 382 | omap_device_disable_idle_on_suspend(pdev); |
| 375 | 383 | ||
| @@ -486,6 +494,33 @@ static int omap_device_fill_resources(struct omap_device *od, | |||
| 486 | } | 494 | } |
| 487 | 495 | ||
| 488 | /** | 496 | /** |
| 497 | * _od_fill_dma_resources - fill in array of struct resource with dma resources | ||
| 498 | * @od: struct omap_device * | ||
| 499 | * @res: pointer to an array of struct resource to be filled in | ||
| 500 | * | ||
| 501 | * Populate one or more empty struct resource pointed to by @res with | ||
| 502 | * the dma resource data for this omap_device @od. Used by | ||
| 503 | * omap_device_alloc() after calling omap_device_count_resources(). | ||
| 504 | * | ||
| 505 | * Ideally this function would not be needed at all. If we have | ||
| 506 | * mechanism to get dma resources from DT. | ||
| 507 | * | ||
| 508 | * Returns 0. | ||
| 509 | */ | ||
| 510 | static int _od_fill_dma_resources(struct omap_device *od, | ||
| 511 | struct resource *res) | ||
| 512 | { | ||
| 513 | int i, r; | ||
| 514 | |||
| 515 | for (i = 0; i < od->hwmods_cnt; i++) { | ||
| 516 | r = omap_hwmod_fill_dma_resources(od->hwmods[i], res); | ||
| 517 | res += r; | ||
| 518 | } | ||
| 519 | |||
| 520 | return 0; | ||
| 521 | } | ||
| 522 | |||
| 523 | /** | ||
| 489 | * omap_device_alloc - allocate an omap_device | 524 | * omap_device_alloc - allocate an omap_device |
| 490 | * @pdev: platform_device that will be included in this omap_device | 525 | * @pdev: platform_device that will be included in this omap_device |
| 491 | * @oh: ptr to the single omap_hwmod that backs this omap_device | 526 | * @oh: ptr to the single omap_hwmod that backs this omap_device |
| @@ -524,24 +559,44 @@ struct omap_device *omap_device_alloc(struct platform_device *pdev, | |||
| 524 | od->hwmods = hwmods; | 559 | od->hwmods = hwmods; |
| 525 | od->pdev = pdev; | 560 | od->pdev = pdev; |
| 526 | 561 | ||
| 562 | res_count = omap_device_count_resources(od); | ||
| 527 | /* | 563 | /* |
| 528 | * HACK: Ideally the resources from DT should match, and hwmod | 564 | * DT Boot: |
| 529 | * should just add the missing ones. Since the name is not | 565 | * OF framework will construct the resource structure (currently |
| 530 | * properly populated by DT, stick to hwmod resources only. | 566 | * does for MEM & IRQ resource) and we should respect/use these |
| 567 | * resources, killing hwmod dependency. | ||
| 568 | * If pdev->num_resources > 0, we assume that MEM & IRQ resources | ||
| 569 | * have been allocated by OF layer already (through DTB). | ||
| 570 | * | ||
| 571 | * Non-DT Boot: | ||
| 572 | * Here, pdev->num_resources = 0, and we should get all the | ||
| 573 | * resources from hwmod. | ||
| 574 | * | ||
| 575 | * TODO: Once DMA resource is available from OF layer, we should | ||
| 576 | * kill filling any resources from hwmod. | ||
| 531 | */ | 577 | */ |
| 532 | if (pdev->num_resources && pdev->resource) | 578 | if (res_count > pdev->num_resources) { |
| 533 | dev_warn(&pdev->dev, "%s(): resources already allocated %d\n", | 579 | /* Allocate resources memory to account for new resources */ |
| 534 | __func__, pdev->num_resources); | ||
| 535 | |||
| 536 | res_count = omap_device_count_resources(od); | ||
| 537 | if (res_count > 0) { | ||
| 538 | dev_dbg(&pdev->dev, "%s(): resources allocated from hwmod %d\n", | ||
| 539 | __func__, res_count); | ||
| 540 | res = kzalloc(sizeof(struct resource) * res_count, GFP_KERNEL); | 580 | res = kzalloc(sizeof(struct resource) * res_count, GFP_KERNEL); |
| 541 | if (!res) | 581 | if (!res) |
| 542 | goto oda_exit3; | 582 | goto oda_exit3; |
| 543 | 583 | ||
| 544 | omap_device_fill_resources(od, res); | 584 | /* |
| 585 | * If pdev->num_resources > 0, then assume that, | ||
| 586 | * MEM and IRQ resources will only come from DT and only | ||
| 587 | * fill DMA resource from hwmod layer. | ||
| 588 | */ | ||
| 589 | if (pdev->num_resources && pdev->resource) { | ||
| 590 | dev_dbg(&pdev->dev, "%s(): resources already allocated %d\n", | ||
| 591 | __func__, res_count); | ||
| 592 | memcpy(res, pdev->resource, | ||
| 593 | sizeof(struct resource) * pdev->num_resources); | ||
| 594 | _od_fill_dma_resources(od, &res[pdev->num_resources]); | ||
| 595 | } else { | ||
| 596 | dev_dbg(&pdev->dev, "%s(): using resources from hwmod %d\n", | ||
| 597 | __func__, res_count); | ||
| 598 | omap_device_fill_resources(od, res); | ||
| 599 | } | ||
| 545 | 600 | ||
| 546 | ret = platform_device_add_resources(pdev, res, res_count); | 601 | ret = platform_device_add_resources(pdev, res, res_count); |
| 547 | kfree(res); | 602 | kfree(res); |
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c index 766181cb5c95..28acb383e7df 100644 --- a/arch/arm/plat-omap/sram.c +++ b/arch/arm/plat-omap/sram.c | |||
| @@ -26,7 +26,6 @@ | |||
| 26 | #include <asm/mach/map.h> | 26 | #include <asm/mach/map.h> |
| 27 | 27 | ||
| 28 | #include <plat/sram.h> | 28 | #include <plat/sram.h> |
| 29 | #include <plat/board.h> | ||
| 30 | #include <plat/cpu.h> | 29 | #include <plat/cpu.h> |
| 31 | 30 | ||
| 32 | #include "sram.h" | 31 | #include "sram.h" |
| @@ -68,6 +67,7 @@ | |||
| 68 | 67 | ||
| 69 | static unsigned long omap_sram_start; | 68 | static unsigned long omap_sram_start; |
| 70 | static void __iomem *omap_sram_base; | 69 | static void __iomem *omap_sram_base; |
| 70 | static unsigned long omap_sram_skip; | ||
| 71 | static unsigned long omap_sram_size; | 71 | static unsigned long omap_sram_size; |
| 72 | static void __iomem *omap_sram_ceil; | 72 | static void __iomem *omap_sram_ceil; |
| 73 | 73 | ||
| @@ -106,6 +106,7 @@ static int is_sram_locked(void) | |||
| 106 | */ | 106 | */ |
| 107 | static void __init omap_detect_sram(void) | 107 | static void __init omap_detect_sram(void) |
| 108 | { | 108 | { |
| 109 | omap_sram_skip = SRAM_BOOTLOADER_SZ; | ||
| 109 | if (cpu_class_is_omap2()) { | 110 | if (cpu_class_is_omap2()) { |
| 110 | if (is_sram_locked()) { | 111 | if (is_sram_locked()) { |
| 111 | if (cpu_is_omap34xx()) { | 112 | if (cpu_is_omap34xx()) { |
| @@ -113,6 +114,7 @@ static void __init omap_detect_sram(void) | |||
| 113 | if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) || | 114 | if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) || |
| 114 | (omap_type() == OMAP2_DEVICE_TYPE_SEC)) { | 115 | (omap_type() == OMAP2_DEVICE_TYPE_SEC)) { |
| 115 | omap_sram_size = 0x7000; /* 28K */ | 116 | omap_sram_size = 0x7000; /* 28K */ |
| 117 | omap_sram_skip += SZ_16K; | ||
| 116 | } else { | 118 | } else { |
| 117 | omap_sram_size = 0x8000; /* 32K */ | 119 | omap_sram_size = 0x8000; /* 32K */ |
| 118 | } | 120 | } |
| @@ -175,8 +177,10 @@ static void __init omap_map_sram(void) | |||
| 175 | return; | 177 | return; |
| 176 | 178 | ||
| 177 | #ifdef CONFIG_OMAP4_ERRATA_I688 | 179 | #ifdef CONFIG_OMAP4_ERRATA_I688 |
| 180 | if (cpu_is_omap44xx()) { | ||
| 178 | omap_sram_start += PAGE_SIZE; | 181 | omap_sram_start += PAGE_SIZE; |
| 179 | omap_sram_size -= SZ_16K; | 182 | omap_sram_size -= SZ_16K; |
| 183 | } | ||
| 180 | #endif | 184 | #endif |
| 181 | if (cpu_is_omap34xx()) { | 185 | if (cpu_is_omap34xx()) { |
| 182 | /* | 186 | /* |
| @@ -203,8 +207,8 @@ static void __init omap_map_sram(void) | |||
| 203 | * Looks like we need to preserve some bootloader code at the | 207 | * Looks like we need to preserve some bootloader code at the |
| 204 | * beginning of SRAM for jumping to flash for reboot to work... | 208 | * beginning of SRAM for jumping to flash for reboot to work... |
| 205 | */ | 209 | */ |
| 206 | memset_io(omap_sram_base + SRAM_BOOTLOADER_SZ, 0, | 210 | memset_io(omap_sram_base + omap_sram_skip, 0, |
| 207 | omap_sram_size - SRAM_BOOTLOADER_SZ); | 211 | omap_sram_size - omap_sram_skip); |
| 208 | } | 212 | } |
| 209 | 213 | ||
| 210 | /* | 214 | /* |
| @@ -218,7 +222,7 @@ void *omap_sram_push_address(unsigned long size) | |||
| 218 | { | 222 | { |
| 219 | unsigned long available, new_ceil = (unsigned long)omap_sram_ceil; | 223 | unsigned long available, new_ceil = (unsigned long)omap_sram_ceil; |
| 220 | 224 | ||
| 221 | available = omap_sram_ceil - (omap_sram_base + SRAM_BOOTLOADER_SZ); | 225 | available = omap_sram_ceil - (omap_sram_base + omap_sram_skip); |
| 222 | 226 | ||
| 223 | if (size > available) { | 227 | if (size > available) { |
| 224 | pr_err("Not enough space in SRAM\n"); | 228 | pr_err("Not enough space in SRAM\n"); |