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-rw-r--r--arch/arm/boot/compressed/head.S6
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 390aa92ef04d..7b7d95c84641 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -396,12 +396,18 @@ __armv3_mpu_cache_on:
396 396
397 mov r0, #0 397 mov r0, #0
398 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 398 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
399 /*
400 * ?? ARMv3 MMU does not allow reading the control register,
401 * does this really work on ARMv3 MPU?
402 */
399 mrc p15, 0, r0, c1, c0, 0 @ read control reg 403 mrc p15, 0, r0, c1, c0, 0 @ read control reg
400 @ .... .... .... WC.M 404 @ .... .... .... WC.M
401 orr r0, r0, #0x000d @ .... .... .... 11.1 405 orr r0, r0, #0x000d @ .... .... .... 11.1
406 /* ?? this overwrites the value constructed above? */
402 mov r0, #0 407 mov r0, #0
403 mcr p15, 0, r0, c1, c0, 0 @ write control reg 408 mcr p15, 0, r0, c1, c0, 0 @ write control reg
404 409
410 /* ?? invalidate for the second time? */
405 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 411 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
406 mov pc, lr 412 mov pc, lr
407 413