diff options
Diffstat (limited to 'arch/arm')
-rw-r--r-- | arch/arm/mach-orion5x/addr-map.c | 14 | ||||
-rw-r--r-- | arch/arm/mach-orion5x/common.c | 36 | ||||
-rw-r--r-- | arch/arm/mach-orion5x/common.h | 2 | ||||
-rw-r--r-- | arch/arm/mach-orion5x/include/mach/orion5x.h | 6 |
4 files changed, 56 insertions, 2 deletions
diff --git a/arch/arm/mach-orion5x/addr-map.c b/arch/arm/mach-orion5x/addr-map.c index c14d12137276..6f3f77d031d0 100644 --- a/arch/arm/mach-orion5x/addr-map.c +++ b/arch/arm/mach-orion5x/addr-map.c | |||
@@ -14,6 +14,7 @@ | |||
14 | #include <linux/init.h> | 14 | #include <linux/init.h> |
15 | #include <linux/mbus.h> | 15 | #include <linux/mbus.h> |
16 | #include <linux/io.h> | 16 | #include <linux/io.h> |
17 | #include <linux/errno.h> | ||
17 | #include <mach/hardware.h> | 18 | #include <mach/hardware.h> |
18 | #include "common.h" | 19 | #include "common.h" |
19 | 20 | ||
@@ -44,6 +45,7 @@ | |||
44 | #define TARGET_DEV_BUS 1 | 45 | #define TARGET_DEV_BUS 1 |
45 | #define TARGET_PCI 3 | 46 | #define TARGET_PCI 3 |
46 | #define TARGET_PCIE 4 | 47 | #define TARGET_PCIE 4 |
48 | #define TARGET_SRAM 9 | ||
47 | #define ATTR_PCIE_MEM 0x59 | 49 | #define ATTR_PCIE_MEM 0x59 |
48 | #define ATTR_PCIE_IO 0x51 | 50 | #define ATTR_PCIE_IO 0x51 |
49 | #define ATTR_PCIE_WA 0x79 | 51 | #define ATTR_PCIE_WA 0x79 |
@@ -53,6 +55,7 @@ | |||
53 | #define ATTR_DEV_CS1 0x1d | 55 | #define ATTR_DEV_CS1 0x1d |
54 | #define ATTR_DEV_CS2 0x1b | 56 | #define ATTR_DEV_CS2 0x1b |
55 | #define ATTR_DEV_BOOT 0xf | 57 | #define ATTR_DEV_BOOT 0xf |
58 | #define ATTR_SRAM 0x0 | ||
56 | 59 | ||
57 | /* | 60 | /* |
58 | * Helpers to get DDR bank info | 61 | * Helpers to get DDR bank info |
@@ -87,13 +90,13 @@ static int __init orion5x_cpu_win_can_remap(int win) | |||
87 | return 0; | 90 | return 0; |
88 | } | 91 | } |
89 | 92 | ||
90 | static void __init setup_cpu_win(int win, u32 base, u32 size, | 93 | static int __init setup_cpu_win(int win, u32 base, u32 size, |
91 | u8 target, u8 attr, int remap) | 94 | u8 target, u8 attr, int remap) |
92 | { | 95 | { |
93 | if (win >= 8) { | 96 | if (win >= 8) { |
94 | printk(KERN_ERR "setup_cpu_win: trying to allocate " | 97 | printk(KERN_ERR "setup_cpu_win: trying to allocate " |
95 | "window %d\n", win); | 98 | "window %d\n", win); |
96 | return; | 99 | return -ENOSPC; |
97 | } | 100 | } |
98 | 101 | ||
99 | writel(base & 0xffff0000, CPU_WIN_BASE(win)); | 102 | writel(base & 0xffff0000, CPU_WIN_BASE(win)); |
@@ -107,6 +110,7 @@ static void __init setup_cpu_win(int win, u32 base, u32 size, | |||
107 | writel(remap & 0xffff0000, CPU_WIN_REMAP_LO(win)); | 110 | writel(remap & 0xffff0000, CPU_WIN_REMAP_LO(win)); |
108 | writel(0, CPU_WIN_REMAP_HI(win)); | 111 | writel(0, CPU_WIN_REMAP_HI(win)); |
109 | } | 112 | } |
113 | return 0; | ||
110 | } | 114 | } |
111 | 115 | ||
112 | void __init orion5x_setup_cpu_mbus_bridge(void) | 116 | void __init orion5x_setup_cpu_mbus_bridge(void) |
@@ -193,3 +197,9 @@ void __init orion5x_setup_pcie_wa_win(u32 base, u32 size) | |||
193 | setup_cpu_win(win_alloc_count++, base, size, | 197 | setup_cpu_win(win_alloc_count++, base, size, |
194 | TARGET_PCIE, ATTR_PCIE_WA, -1); | 198 | TARGET_PCIE, ATTR_PCIE_WA, -1); |
195 | } | 199 | } |
200 | |||
201 | int __init orion5x_setup_sram_win(void) | ||
202 | { | ||
203 | return setup_cpu_win(win_alloc_count, ORION5X_SRAM_PHYS_BASE, | ||
204 | ORION5X_SRAM_SIZE, TARGET_SRAM, ATTR_SRAM, -1); | ||
205 | } | ||
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c index c3e2bea2d054..eafcc49009ea 100644 --- a/arch/arm/mach-orion5x/common.c +++ b/arch/arm/mach-orion5x/common.c | |||
@@ -536,6 +536,42 @@ void __init orion5x_xor_init(void) | |||
536 | platform_device_register(&orion5x_xor1_channel); | 536 | platform_device_register(&orion5x_xor1_channel); |
537 | } | 537 | } |
538 | 538 | ||
539 | static struct resource orion5x_crypto_res[] = { | ||
540 | { | ||
541 | .name = "regs", | ||
542 | .start = ORION5X_CRYPTO_PHYS_BASE, | ||
543 | .end = ORION5X_CRYPTO_PHYS_BASE + 0xffff, | ||
544 | .flags = IORESOURCE_MEM, | ||
545 | }, { | ||
546 | .name = "sram", | ||
547 | .start = ORION5X_SRAM_PHYS_BASE, | ||
548 | .end = ORION5X_SRAM_PHYS_BASE + SZ_8K - 1, | ||
549 | .flags = IORESOURCE_MEM, | ||
550 | }, { | ||
551 | .name = "crypto interrupt", | ||
552 | .start = IRQ_ORION5X_CESA, | ||
553 | .end = IRQ_ORION5X_CESA, | ||
554 | .flags = IORESOURCE_IRQ, | ||
555 | }, | ||
556 | }; | ||
557 | |||
558 | static struct platform_device orion5x_crypto_device = { | ||
559 | .name = "mv_crypto", | ||
560 | .id = -1, | ||
561 | .num_resources = ARRAY_SIZE(orion5x_crypto_res), | ||
562 | .resource = orion5x_crypto_res, | ||
563 | }; | ||
564 | |||
565 | int __init orion5x_crypto_init(void) | ||
566 | { | ||
567 | int ret; | ||
568 | |||
569 | ret = orion5x_setup_sram_win(); | ||
570 | if (ret) | ||
571 | return ret; | ||
572 | |||
573 | return platform_device_register(&orion5x_crypto_device); | ||
574 | } | ||
539 | 575 | ||
540 | /***************************************************************************** | 576 | /***************************************************************************** |
541 | * Watchdog | 577 | * Watchdog |
diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h index 798b9a5e3da9..de483e83edd7 100644 --- a/arch/arm/mach-orion5x/common.h +++ b/arch/arm/mach-orion5x/common.h | |||
@@ -26,6 +26,7 @@ void orion5x_setup_dev0_win(u32 base, u32 size); | |||
26 | void orion5x_setup_dev1_win(u32 base, u32 size); | 26 | void orion5x_setup_dev1_win(u32 base, u32 size); |
27 | void orion5x_setup_dev2_win(u32 base, u32 size); | 27 | void orion5x_setup_dev2_win(u32 base, u32 size); |
28 | void orion5x_setup_pcie_wa_win(u32 base, u32 size); | 28 | void orion5x_setup_pcie_wa_win(u32 base, u32 size); |
29 | int orion5x_setup_sram_win(void); | ||
29 | 30 | ||
30 | void orion5x_ehci0_init(void); | 31 | void orion5x_ehci0_init(void); |
31 | void orion5x_ehci1_init(void); | 32 | void orion5x_ehci1_init(void); |
@@ -37,6 +38,7 @@ void orion5x_spi_init(void); | |||
37 | void orion5x_uart0_init(void); | 38 | void orion5x_uart0_init(void); |
38 | void orion5x_uart1_init(void); | 39 | void orion5x_uart1_init(void); |
39 | void orion5x_xor_init(void); | 40 | void orion5x_xor_init(void); |
41 | int orion5x_crypto_init(void); | ||
40 | 42 | ||
41 | /* | 43 | /* |
42 | * PCIe/PCI functions. | 44 | * PCIe/PCI functions. |
diff --git a/arch/arm/mach-orion5x/include/mach/orion5x.h b/arch/arm/mach-orion5x/include/mach/orion5x.h index 377a773ae53f..2d8766570531 100644 --- a/arch/arm/mach-orion5x/include/mach/orion5x.h +++ b/arch/arm/mach-orion5x/include/mach/orion5x.h | |||
@@ -24,6 +24,7 @@ | |||
24 | * f1000000 on-chip peripheral registers | 24 | * f1000000 on-chip peripheral registers |
25 | * f2000000 PCIe I/O space | 25 | * f2000000 PCIe I/O space |
26 | * f2100000 PCI I/O space | 26 | * f2100000 PCI I/O space |
27 | * f2200000 SRAM dedicated for the crypto unit | ||
27 | * f4000000 device bus mappings (boot) | 28 | * f4000000 device bus mappings (boot) |
28 | * fa000000 device bus mappings (cs0) | 29 | * fa000000 device bus mappings (cs0) |
29 | * fa800000 device bus mappings (cs2) | 30 | * fa800000 device bus mappings (cs2) |
@@ -49,6 +50,9 @@ | |||
49 | #define ORION5X_PCI_IO_BUS_BASE 0x00100000 | 50 | #define ORION5X_PCI_IO_BUS_BASE 0x00100000 |
50 | #define ORION5X_PCI_IO_SIZE SZ_1M | 51 | #define ORION5X_PCI_IO_SIZE SZ_1M |
51 | 52 | ||
53 | #define ORION5X_SRAM_PHYS_BASE (0xf2200000) | ||
54 | #define ORION5X_SRAM_SIZE SZ_8K | ||
55 | |||
52 | /* Relevant only for Orion-1/Orion-NAS */ | 56 | /* Relevant only for Orion-1/Orion-NAS */ |
53 | #define ORION5X_PCIE_WA_PHYS_BASE 0xf0000000 | 57 | #define ORION5X_PCIE_WA_PHYS_BASE 0xf0000000 |
54 | #define ORION5X_PCIE_WA_VIRT_BASE 0xfe000000 | 58 | #define ORION5X_PCIE_WA_VIRT_BASE 0xfe000000 |
@@ -94,6 +98,8 @@ | |||
94 | #define ORION5X_SATA_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x80000) | 98 | #define ORION5X_SATA_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x80000) |
95 | #define ORION5X_SATA_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x80000) | 99 | #define ORION5X_SATA_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x80000) |
96 | 100 | ||
101 | #define ORION5X_CRYPTO_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x90000) | ||
102 | |||
97 | #define ORION5X_USB1_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0xa0000) | 103 | #define ORION5X_USB1_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0xa0000) |
98 | #define ORION5X_USB1_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0xa0000) | 104 | #define ORION5X_USB1_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0xa0000) |
99 | 105 | ||