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-rw-r--r--arch/arm/mach-omap2/clock3xxx_data.c206
-rw-r--r--arch/arm/plat-omap/include/plat/clkdev_omap.h20
-rw-r--r--arch/arm/plat-omap/include/plat/clock.h11
3 files changed, 120 insertions, 117 deletions
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index b25171d9a387..27c9e145e4ef 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -120,7 +120,7 @@ static const struct clksel_rate osc_sys_13m_rates[] = {
120}; 120};
121 121
122static const struct clksel_rate osc_sys_16_8m_rates[] = { 122static const struct clksel_rate osc_sys_16_8m_rates[] = {
123 { .div = 1, .val = 5, .flags = RATE_IN_3430ES2PLUS }, 123 { .div = 1, .val = 5, .flags = RATE_IN_3430ES2PLUS_36XX },
124 { .div = 0 } 124 { .div = 0 }
125}; 125};
126 126
@@ -452,35 +452,35 @@ static struct clk dpll3_x2_ck = {
452static const struct clksel_rate div31_dpll3_rates[] = { 452static const struct clksel_rate div31_dpll3_rates[] = {
453 { .div = 1, .val = 1, .flags = RATE_IN_3XXX }, 453 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
454 { .div = 2, .val = 2, .flags = RATE_IN_3XXX }, 454 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
455 { .div = 3, .val = 3, .flags = RATE_IN_3430ES2PLUS }, 455 { .div = 3, .val = 3, .flags = RATE_IN_3430ES2PLUS_36XX },
456 { .div = 4, .val = 4, .flags = RATE_IN_3430ES2PLUS }, 456 { .div = 4, .val = 4, .flags = RATE_IN_3430ES2PLUS_36XX },
457 { .div = 5, .val = 5, .flags = RATE_IN_3430ES2PLUS }, 457 { .div = 5, .val = 5, .flags = RATE_IN_3430ES2PLUS_36XX },
458 { .div = 6, .val = 6, .flags = RATE_IN_3430ES2PLUS }, 458 { .div = 6, .val = 6, .flags = RATE_IN_3430ES2PLUS_36XX },
459 { .div = 7, .val = 7, .flags = RATE_IN_3430ES2PLUS }, 459 { .div = 7, .val = 7, .flags = RATE_IN_3430ES2PLUS_36XX },
460 { .div = 8, .val = 8, .flags = RATE_IN_3430ES2PLUS }, 460 { .div = 8, .val = 8, .flags = RATE_IN_3430ES2PLUS_36XX },
461 { .div = 9, .val = 9, .flags = RATE_IN_3430ES2PLUS }, 461 { .div = 9, .val = 9, .flags = RATE_IN_3430ES2PLUS_36XX },
462 { .div = 10, .val = 10, .flags = RATE_IN_3430ES2PLUS }, 462 { .div = 10, .val = 10, .flags = RATE_IN_3430ES2PLUS_36XX },
463 { .div = 11, .val = 11, .flags = RATE_IN_3430ES2PLUS }, 463 { .div = 11, .val = 11, .flags = RATE_IN_3430ES2PLUS_36XX },
464 { .div = 12, .val = 12, .flags = RATE_IN_3430ES2PLUS }, 464 { .div = 12, .val = 12, .flags = RATE_IN_3430ES2PLUS_36XX },
465 { .div = 13, .val = 13, .flags = RATE_IN_3430ES2PLUS }, 465 { .div = 13, .val = 13, .flags = RATE_IN_3430ES2PLUS_36XX },
466 { .div = 14, .val = 14, .flags = RATE_IN_3430ES2PLUS }, 466 { .div = 14, .val = 14, .flags = RATE_IN_3430ES2PLUS_36XX },
467 { .div = 15, .val = 15, .flags = RATE_IN_3430ES2PLUS }, 467 { .div = 15, .val = 15, .flags = RATE_IN_3430ES2PLUS_36XX },
468 { .div = 16, .val = 16, .flags = RATE_IN_3430ES2PLUS }, 468 { .div = 16, .val = 16, .flags = RATE_IN_3430ES2PLUS_36XX },
469 { .div = 17, .val = 17, .flags = RATE_IN_3430ES2PLUS }, 469 { .div = 17, .val = 17, .flags = RATE_IN_3430ES2PLUS_36XX },
470 { .div = 18, .val = 18, .flags = RATE_IN_3430ES2PLUS }, 470 { .div = 18, .val = 18, .flags = RATE_IN_3430ES2PLUS_36XX },
471 { .div = 19, .val = 19, .flags = RATE_IN_3430ES2PLUS }, 471 { .div = 19, .val = 19, .flags = RATE_IN_3430ES2PLUS_36XX },
472 { .div = 20, .val = 20, .flags = RATE_IN_3430ES2PLUS }, 472 { .div = 20, .val = 20, .flags = RATE_IN_3430ES2PLUS_36XX },
473 { .div = 21, .val = 21, .flags = RATE_IN_3430ES2PLUS }, 473 { .div = 21, .val = 21, .flags = RATE_IN_3430ES2PLUS_36XX },
474 { .div = 22, .val = 22, .flags = RATE_IN_3430ES2PLUS }, 474 { .div = 22, .val = 22, .flags = RATE_IN_3430ES2PLUS_36XX },
475 { .div = 23, .val = 23, .flags = RATE_IN_3430ES2PLUS }, 475 { .div = 23, .val = 23, .flags = RATE_IN_3430ES2PLUS_36XX },
476 { .div = 24, .val = 24, .flags = RATE_IN_3430ES2PLUS }, 476 { .div = 24, .val = 24, .flags = RATE_IN_3430ES2PLUS_36XX },
477 { .div = 25, .val = 25, .flags = RATE_IN_3430ES2PLUS }, 477 { .div = 25, .val = 25, .flags = RATE_IN_3430ES2PLUS_36XX },
478 { .div = 26, .val = 26, .flags = RATE_IN_3430ES2PLUS }, 478 { .div = 26, .val = 26, .flags = RATE_IN_3430ES2PLUS_36XX },
479 { .div = 27, .val = 27, .flags = RATE_IN_3430ES2PLUS }, 479 { .div = 27, .val = 27, .flags = RATE_IN_3430ES2PLUS_36XX },
480 { .div = 28, .val = 28, .flags = RATE_IN_3430ES2PLUS }, 480 { .div = 28, .val = 28, .flags = RATE_IN_3430ES2PLUS_36XX },
481 { .div = 29, .val = 29, .flags = RATE_IN_3430ES2PLUS }, 481 { .div = 29, .val = 29, .flags = RATE_IN_3430ES2PLUS_36XX },
482 { .div = 30, .val = 30, .flags = RATE_IN_3430ES2PLUS }, 482 { .div = 30, .val = 30, .flags = RATE_IN_3430ES2PLUS_36XX },
483 { .div = 31, .val = 31, .flags = RATE_IN_3430ES2PLUS }, 483 { .div = 31, .val = 31, .flags = RATE_IN_3430ES2PLUS_36XX },
484 { .div = 0 }, 484 { .div = 0 },
485}; 485};
486 486
@@ -3203,7 +3203,7 @@ static struct omap_clk omap3xxx_clks[] = {
3203 CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_3XXX), 3203 CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_3XXX),
3204 CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_3XXX), 3204 CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_3XXX),
3205 CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_3XXX), 3205 CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_3XXX),
3206 CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2 | CK_AM35XX), 3206 CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3207 CLK(NULL, "virt_19_2m_ck", &virt_19_2m_ck, CK_3XXX), 3207 CLK(NULL, "virt_19_2m_ck", &virt_19_2m_ck, CK_3XXX),
3208 CLK(NULL, "virt_26m_ck", &virt_26m_ck, CK_3XXX), 3208 CLK(NULL, "virt_26m_ck", &virt_26m_ck, CK_3XXX),
3209 CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck, CK_3XXX), 3209 CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck, CK_3XXX),
@@ -3220,8 +3220,8 @@ static struct omap_clk omap3xxx_clks[] = {
3220 CLK(NULL, "dpll1_ck", &dpll1_ck, CK_3XXX), 3220 CLK(NULL, "dpll1_ck", &dpll1_ck, CK_3XXX),
3221 CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck, CK_3XXX), 3221 CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck, CK_3XXX),
3222 CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_3XXX), 3222 CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_3XXX),
3223 CLK(NULL, "dpll2_ck", &dpll2_ck, CK_343X), 3223 CLK(NULL, "dpll2_ck", &dpll2_ck, CK_34XX | CK_36XX),
3224 CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck, CK_343X), 3224 CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck, CK_34XX | CK_36XX),
3225 CLK(NULL, "dpll3_ck", &dpll3_ck, CK_3XXX), 3225 CLK(NULL, "dpll3_ck", &dpll3_ck, CK_3XXX),
3226 CLK(NULL, "core_ck", &core_ck, CK_3XXX), 3226 CLK(NULL, "core_ck", &core_ck, CK_3XXX),
3227 CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck, CK_3XXX), 3227 CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck, CK_3XXX),
@@ -3250,8 +3250,8 @@ static struct omap_clk omap3xxx_clks[] = {
3250 CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck, CK_3XXX), 3250 CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck, CK_3XXX),
3251 CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_3XXX), 3251 CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_3XXX),
3252 CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX), 3252 CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX),
3253 CLK(NULL, "dpll5_ck", &dpll5_ck, CK_3430ES2 | CK_AM35XX), 3253 CLK(NULL, "dpll5_ck", &dpll5_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3254 CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2 | CK_AM35XX), 3254 CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3255 CLK(NULL, "clkout2_src_ck", &clkout2_src_ck, CK_3XXX), 3255 CLK(NULL, "clkout2_src_ck", &clkout2_src_ck, CK_3XXX),
3256 CLK(NULL, "sys_clkout2", &sys_clkout2, CK_3XXX), 3256 CLK(NULL, "sys_clkout2", &sys_clkout2, CK_3XXX),
3257 CLK(NULL, "corex2_fck", &corex2_fck, CK_3XXX), 3257 CLK(NULL, "corex2_fck", &corex2_fck, CK_3XXX),
@@ -3259,8 +3259,8 @@ static struct omap_clk omap3xxx_clks[] = {
3259 CLK(NULL, "mpu_ck", &mpu_ck, CK_3XXX), 3259 CLK(NULL, "mpu_ck", &mpu_ck, CK_3XXX),
3260 CLK(NULL, "arm_fck", &arm_fck, CK_3XXX), 3260 CLK(NULL, "arm_fck", &arm_fck, CK_3XXX),
3261 CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX), 3261 CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX),
3262 CLK(NULL, "dpll2_fck", &dpll2_fck, CK_343X), 3262 CLK(NULL, "dpll2_fck", &dpll2_fck, CK_34XX | CK_36XX),
3263 CLK(NULL, "iva2_ck", &iva2_ck, CK_343X), 3263 CLK(NULL, "iva2_ck", &iva2_ck, CK_34XX | CK_36XX),
3264 CLK(NULL, "l3_ick", &l3_ick, CK_3XXX), 3264 CLK(NULL, "l3_ick", &l3_ick, CK_3XXX),
3265 CLK(NULL, "l4_ick", &l4_ick, CK_3XXX), 3265 CLK(NULL, "l4_ick", &l4_ick, CK_3XXX),
3266 CLK(NULL, "rm_ick", &rm_ick, CK_3XXX), 3266 CLK(NULL, "rm_ick", &rm_ick, CK_3XXX),
@@ -3269,23 +3269,23 @@ static struct omap_clk omap3xxx_clks[] = {
3269 CLK(NULL, "gfx_l3_ick", &gfx_l3_ick, CK_3430ES1), 3269 CLK(NULL, "gfx_l3_ick", &gfx_l3_ick, CK_3430ES1),
3270 CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck, CK_3430ES1), 3270 CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck, CK_3430ES1),
3271 CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck, CK_3430ES1), 3271 CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck, CK_3430ES1),
3272 CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2 | CK_3517), 3272 CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2PLUS | CK_3517 | CK_36XX),
3273 CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2 | CK_3517), 3273 CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2PLUS | CK_3517 | CK_36XX),
3274 CLK(NULL, "d2d_26m_fck", &d2d_26m_fck, CK_3430ES1), 3274 CLK(NULL, "d2d_26m_fck", &d2d_26m_fck, CK_3430ES1),
3275 CLK(NULL, "modem_fck", &modem_fck, CK_343X), 3275 CLK(NULL, "modem_fck", &modem_fck, CK_34XX | CK_36XX),
3276 CLK(NULL, "sad2d_ick", &sad2d_ick, CK_343X), 3276 CLK(NULL, "sad2d_ick", &sad2d_ick, CK_34XX | CK_36XX),
3277 CLK(NULL, "mad2d_ick", &mad2d_ick, CK_343X), 3277 CLK(NULL, "mad2d_ick", &mad2d_ick, CK_34XX | CK_36XX),
3278 CLK(NULL, "gpt10_fck", &gpt10_fck, CK_3XXX), 3278 CLK(NULL, "gpt10_fck", &gpt10_fck, CK_3XXX),
3279 CLK(NULL, "gpt11_fck", &gpt11_fck, CK_3XXX), 3279 CLK(NULL, "gpt11_fck", &gpt11_fck, CK_3XXX),
3280 CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2 | CK_AM35XX), 3280 CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3281 CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2 | CK_AM35XX), 3281 CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3282 CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2 | CK_AM35XX), 3282 CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3283 CLK("omap-mcbsp.1", "prcm_fck", &core_96m_fck, CK_3XXX), 3283 CLK("omap-mcbsp.1", "prcm_fck", &core_96m_fck, CK_3XXX),
3284 CLK("omap-mcbsp.5", "prcm_fck", &core_96m_fck, CK_3XXX), 3284 CLK("omap-mcbsp.5", "prcm_fck", &core_96m_fck, CK_3XXX),
3285 CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX), 3285 CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX),
3286 CLK("mmci-omap-hs.2", "fck", &mmchs3_fck, CK_3430ES2 | CK_AM35XX), 3286 CLK("mmci-omap-hs.2", "fck", &mmchs3_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3287 CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_3XXX), 3287 CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_3XXX),
3288 CLK(NULL, "mspro_fck", &mspro_fck, CK_343X), 3288 CLK(NULL, "mspro_fck", &mspro_fck, CK_34XX | CK_36XX),
3289 CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_3XXX), 3289 CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_3XXX),
3290 CLK("omap_i2c.3", "fck", &i2c3_fck, CK_3XXX), 3290 CLK("omap_i2c.3", "fck", &i2c3_fck, CK_3XXX),
3291 CLK("omap_i2c.2", "fck", &i2c2_fck, CK_3XXX), 3291 CLK("omap_i2c.2", "fck", &i2c2_fck, CK_3XXX),
@@ -3303,26 +3303,26 @@ static struct omap_clk omap3xxx_clks[] = {
3303 CLK(NULL, "core_12m_fck", &core_12m_fck, CK_3XXX), 3303 CLK(NULL, "core_12m_fck", &core_12m_fck, CK_3XXX),
3304 CLK("omap_hdq.0", "fck", &hdq_fck, CK_3XXX), 3304 CLK("omap_hdq.0", "fck", &hdq_fck, CK_3XXX),
3305 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1, CK_3430ES1), 3305 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1, CK_3430ES1),
3306 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2, CK_3430ES2), 3306 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2, CK_3430ES2PLUS | CK_36XX),
3307 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1, CK_3430ES1), 3307 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1, CK_3430ES1),
3308 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es2, CK_3430ES2), 3308 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es2, CK_3430ES2PLUS | CK_36XX),
3309 CLK(NULL, "core_l3_ick", &core_l3_ick, CK_3XXX), 3309 CLK(NULL, "core_l3_ick", &core_l3_ick, CK_3XXX),
3310 CLK("musb_hdrc", "ick", &hsotgusb_ick_3430es1, CK_3430ES1), 3310 CLK("musb_hdrc", "ick", &hsotgusb_ick_3430es1, CK_3430ES1),
3311 CLK("musb_hdrc", "ick", &hsotgusb_ick_3430es2, CK_3430ES2), 3311 CLK("musb_hdrc", "ick", &hsotgusb_ick_3430es2, CK_3430ES2PLUS | CK_36XX),
3312 CLK(NULL, "sdrc_ick", &sdrc_ick, CK_3XXX), 3312 CLK(NULL, "sdrc_ick", &sdrc_ick, CK_3XXX),
3313 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_3XXX), 3313 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_3XXX),
3314 CLK(NULL, "security_l3_ick", &security_l3_ick, CK_343X), 3314 CLK(NULL, "security_l3_ick", &security_l3_ick, CK_34XX | CK_36XX),
3315 CLK(NULL, "pka_ick", &pka_ick, CK_343X), 3315 CLK(NULL, "pka_ick", &pka_ick, CK_34XX | CK_36XX),
3316 CLK(NULL, "core_l4_ick", &core_l4_ick, CK_3XXX), 3316 CLK(NULL, "core_l4_ick", &core_l4_ick, CK_3XXX),
3317 CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2 | CK_AM35XX), 3317 CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3318 CLK("mmci-omap-hs.2", "ick", &mmchs3_ick, CK_3430ES2 | CK_AM35XX), 3318 CLK("mmci-omap-hs.2", "ick", &mmchs3_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3319 CLK(NULL, "icr_ick", &icr_ick, CK_343X), 3319 CLK(NULL, "icr_ick", &icr_ick, CK_34XX | CK_36XX),
3320 CLK("omap-aes", "ick", &aes2_ick, CK_343X), 3320 CLK("omap-aes", "ick", &aes2_ick, CK_34XX | CK_36XX),
3321 CLK("omap-sham", "ick", &sha12_ick, CK_343X), 3321 CLK("omap-sham", "ick", &sha12_ick, CK_34XX | CK_36XX),
3322 CLK(NULL, "des2_ick", &des2_ick, CK_343X), 3322 CLK(NULL, "des2_ick", &des2_ick, CK_34XX | CK_36XX),
3323 CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_3XXX), 3323 CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_3XXX),
3324 CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_3XXX), 3324 CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_3XXX),
3325 CLK(NULL, "mspro_ick", &mspro_ick, CK_343X), 3325 CLK(NULL, "mspro_ick", &mspro_ick, CK_34XX | CK_36XX),
3326 CLK("omap_hdq.0", "ick", &hdq_ick, CK_3XXX), 3326 CLK("omap_hdq.0", "ick", &hdq_ick, CK_3XXX),
3327 CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_3XXX), 3327 CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_3XXX),
3328 CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_3XXX), 3328 CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_3XXX),
@@ -3338,37 +3338,37 @@ static struct omap_clk omap3xxx_clks[] = {
3338 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_3XXX), 3338 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_3XXX),
3339 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_3XXX), 3339 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_3XXX),
3340 CLK(NULL, "fac_ick", &fac_ick, CK_3430ES1), 3340 CLK(NULL, "fac_ick", &fac_ick, CK_3430ES1),
3341 CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_343X), 3341 CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_34XX | CK_36XX),
3342 CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_3XXX), 3342 CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_3XXX),
3343 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_343X), 3343 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_34XX | CK_36XX),
3344 CLK(NULL, "ssi_ick", &ssi_ick_3430es1, CK_3430ES1), 3344 CLK(NULL, "ssi_ick", &ssi_ick_3430es1, CK_3430ES1),
3345 CLK(NULL, "ssi_ick", &ssi_ick_3430es2, CK_3430ES2), 3345 CLK(NULL, "ssi_ick", &ssi_ick_3430es2, CK_3430ES2PLUS | CK_36XX),
3346 CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_3430ES1), 3346 CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_3430ES1),
3347 CLK(NULL, "security_l4_ick2", &security_l4_ick2, CK_343X), 3347 CLK(NULL, "security_l4_ick2", &security_l4_ick2, CK_34XX | CK_36XX),
3348 CLK(NULL, "aes1_ick", &aes1_ick, CK_343X), 3348 CLK(NULL, "aes1_ick", &aes1_ick, CK_34XX | CK_36XX),
3349 CLK("omap_rng", "ick", &rng_ick, CK_343X), 3349 CLK("omap_rng", "ick", &rng_ick, CK_34XX | CK_36XX),
3350 CLK(NULL, "sha11_ick", &sha11_ick, CK_343X), 3350 CLK(NULL, "sha11_ick", &sha11_ick, CK_34XX | CK_36XX),
3351 CLK(NULL, "des1_ick", &des1_ick, CK_343X), 3351 CLK(NULL, "des1_ick", &des1_ick, CK_34XX | CK_36XX),
3352 CLK("omapdss", "dss1_fck", &dss1_alwon_fck_3430es1, CK_3430ES1), 3352 CLK("omapdss", "dss1_fck", &dss1_alwon_fck_3430es1, CK_3430ES1),
3353 CLK("omapdss", "dss1_fck", &dss1_alwon_fck_3430es2, CK_3430ES2 | CK_AM35XX), 3353 CLK("omapdss", "dss1_fck", &dss1_alwon_fck_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3354 CLK("omapdss", "tv_fck", &dss_tv_fck, CK_3XXX), 3354 CLK("omapdss", "tv_fck", &dss_tv_fck, CK_3XXX),
3355 CLK("omapdss", "video_fck", &dss_96m_fck, CK_3XXX), 3355 CLK("omapdss", "video_fck", &dss_96m_fck, CK_3XXX),
3356 CLK("omapdss", "dss2_fck", &dss2_alwon_fck, CK_3XXX), 3356 CLK("omapdss", "dss2_fck", &dss2_alwon_fck, CK_3XXX),
3357 CLK("omapdss", "ick", &dss_ick_3430es1, CK_3430ES1), 3357 CLK("omapdss", "ick", &dss_ick_3430es1, CK_3430ES1),
3358 CLK("omapdss", "ick", &dss_ick_3430es2, CK_3430ES2 | CK_AM35XX), 3358 CLK("omapdss", "ick", &dss_ick_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3359 CLK(NULL, "cam_mclk", &cam_mclk, CK_343X), 3359 CLK(NULL, "cam_mclk", &cam_mclk, CK_34XX | CK_36XX),
3360 CLK(NULL, "cam_ick", &cam_ick, CK_343X), 3360 CLK(NULL, "cam_ick", &cam_ick, CK_34XX | CK_36XX),
3361 CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_343X), 3361 CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_34XX | CK_36XX),
3362 CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2 | CK_AM35XX), 3362 CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3363 CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2 | CK_AM35XX), 3363 CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3364 CLK(NULL, "usbhost_ick", &usbhost_ick, CK_3430ES2 | CK_AM35XX), 3364 CLK(NULL, "usbhost_ick", &usbhost_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3365 CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2), 3365 CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2PLUS | CK_36XX),
3366 CLK(NULL, "gpt1_fck", &gpt1_fck, CK_3XXX), 3366 CLK(NULL, "gpt1_fck", &gpt1_fck, CK_3XXX),
3367 CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_3XXX), 3367 CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_3XXX),
3368 CLK(NULL, "gpio1_dbck", &gpio1_dbck, CK_3XXX), 3368 CLK(NULL, "gpio1_dbck", &gpio1_dbck, CK_3XXX),
3369 CLK("omap_wdt", "fck", &wdt2_fck, CK_3XXX), 3369 CLK("omap_wdt", "fck", &wdt2_fck, CK_3XXX),
3370 CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_343X), 3370 CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_34XX | CK_36XX),
3371 CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2), 3371 CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2PLUS | CK_36XX),
3372 CLK("omap_wdt", "ick", &wdt2_ick, CK_3XXX), 3372 CLK("omap_wdt", "ick", &wdt2_ick, CK_3XXX),
3373 CLK(NULL, "wdt1_ick", &wdt1_ick, CK_3XXX), 3373 CLK(NULL, "wdt1_ick", &wdt1_ick, CK_3XXX),
3374 CLK(NULL, "gpio1_ick", &gpio1_ick, CK_3XXX), 3374 CLK(NULL, "gpio1_ick", &gpio1_ick, CK_3XXX),
@@ -3426,9 +3426,9 @@ static struct omap_clk omap3xxx_clks[] = {
3426 CLK(NULL, "atclk_fck", &atclk_fck, CK_3XXX), 3426 CLK(NULL, "atclk_fck", &atclk_fck, CK_3XXX),
3427 CLK(NULL, "traceclk_src_fck", &traceclk_src_fck, CK_3XXX), 3427 CLK(NULL, "traceclk_src_fck", &traceclk_src_fck, CK_3XXX),
3428 CLK(NULL, "traceclk_fck", &traceclk_fck, CK_3XXX), 3428 CLK(NULL, "traceclk_fck", &traceclk_fck, CK_3XXX),
3429 CLK(NULL, "sr1_fck", &sr1_fck, CK_343X), 3429 CLK(NULL, "sr1_fck", &sr1_fck, CK_34XX | CK_36XX),
3430 CLK(NULL, "sr2_fck", &sr2_fck, CK_343X), 3430 CLK(NULL, "sr2_fck", &sr2_fck, CK_34XX | CK_36XX),
3431 CLK(NULL, "sr_l4_ick", &sr_l4_ick, CK_343X), 3431 CLK(NULL, "sr_l4_ick", &sr_l4_ick, CK_34XX | CK_36XX),
3432 CLK(NULL, "secure_32k_fck", &secure_32k_fck, CK_3XXX), 3432 CLK(NULL, "secure_32k_fck", &secure_32k_fck, CK_3XXX),
3433 CLK(NULL, "gpt12_fck", &gpt12_fck, CK_3XXX), 3433 CLK(NULL, "gpt12_fck", &gpt12_fck, CK_3XXX),
3434 CLK(NULL, "wdt1_fck", &wdt1_fck, CK_3XXX), 3434 CLK(NULL, "wdt1_fck", &wdt1_fck, CK_3XXX),
@@ -3449,38 +3449,37 @@ static struct omap_clk omap3xxx_clks[] = {
3449int __init omap3xxx_clk_init(void) 3449int __init omap3xxx_clk_init(void)
3450{ 3450{
3451 struct omap_clk *c; 3451 struct omap_clk *c;
3452 u32 cpu_clkflg = CK_3XXX; 3452 u32 cpu_clkflg = 0;
3453 3453
3454 if (cpu_is_omap3517()) { 3454 if (cpu_is_omap3517()) {
3455 cpu_mask = RATE_IN_3XXX | RATE_IN_3430ES2PLUS; 3455 cpu_mask = RATE_IN_34XX;
3456 cpu_clkflg |= CK_3517; 3456 cpu_clkflg = CK_3517;
3457 } else if (cpu_is_omap3505()) { 3457 } else if (cpu_is_omap3505()) {
3458 cpu_mask = RATE_IN_3XXX | RATE_IN_3430ES2PLUS; 3458 cpu_mask = RATE_IN_34XX;
3459 cpu_clkflg |= CK_3505; 3459 cpu_clkflg = CK_3505;
3460 } else if (cpu_is_omap3630()) {
3461 cpu_mask = (RATE_IN_34XX | RATE_IN_36XX);
3462 cpu_clkflg = CK_36XX;
3460 } else if (cpu_is_omap34xx()) { 3463 } else if (cpu_is_omap34xx()) {
3461 cpu_mask = RATE_IN_3XXX;
3462 cpu_clkflg |= CK_343X;
3463
3464 /*
3465 * Update this if there are further clock changes between ES2
3466 * and production parts
3467 */
3468 if (omap_rev() == OMAP3430_REV_ES1_0) { 3464 if (omap_rev() == OMAP3430_REV_ES1_0) {
3469 /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */ 3465 cpu_mask = RATE_IN_3430ES1;
3470 cpu_clkflg |= CK_3430ES1; 3466 cpu_clkflg = CK_3430ES1;
3471 } else { 3467 } else {
3472 cpu_mask |= RATE_IN_3430ES2PLUS; 3468 /*
3473 cpu_clkflg |= CK_3430ES2; 3469 * Assume that anything that we haven't matched yet
3470 * has 3430ES2-type clocks.
3471 */
3472 cpu_mask = RATE_IN_3430ES2PLUS;
3473 cpu_clkflg = CK_3430ES2PLUS;
3474 } 3474 }
3475 } else {
3476 WARN(1, "clock: could not identify OMAP3 variant\n");
3475 } 3477 }
3476 3478
3477 if (omap3_has_192mhz_clk()) 3479 if (omap3_has_192mhz_clk())
3478 omap_96m_alwon_fck = omap_96m_alwon_fck_3630; 3480 omap_96m_alwon_fck = omap_96m_alwon_fck_3630;
3479 3481
3480 if (cpu_is_omap3630()) { 3482 if (cpu_is_omap3630()) {
3481 cpu_mask |= RATE_IN_36XX;
3482 cpu_clkflg |= CK_36XX;
3483
3484 /* 3483 /*
3485 * XXX This type of dynamic rewriting of the clock tree is 3484 * XXX This type of dynamic rewriting of the clock tree is
3486 * deprecated and should be revised soon. 3485 * deprecated and should be revised soon.
@@ -3527,10 +3526,9 @@ int __init omap3xxx_clk_init(void)
3527 3526
3528 recalculate_root_clocks(); 3527 recalculate_root_clocks();
3529 3528
3530 printk(KERN_INFO "Clocking rate (Crystal/Core/MPU): " 3529 pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
3531 "%ld.%01ld/%ld/%ld MHz\n", 3530 (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
3532 (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10, 3531 (core_ck.rate / 1000000), (arm_fck.rate / 1000000));
3533 (core_ck.rate / 1000000), (arm_fck.rate / 1000000));
3534 3532
3535 /* 3533 /*
3536 * Only enable those clocks we will need, let the drivers 3534 * Only enable those clocks we will need, let the drivers
diff --git a/arch/arm/plat-omap/include/plat/clkdev_omap.h b/arch/arm/plat-omap/include/plat/clkdev_omap.h
index bb937f3fabed..b19774c9c112 100644
--- a/arch/arm/plat-omap/include/plat/clkdev_omap.h
+++ b/arch/arm/plat-omap/include/plat/clkdev_omap.h
@@ -31,18 +31,18 @@ struct omap_clk {
31#define CK_1510 (1 << 2) 31#define CK_1510 (1 << 2)
32#define CK_16XX (1 << 3) /* 16xx, 17xx, 5912 */ 32#define CK_16XX (1 << 3) /* 16xx, 17xx, 5912 */
33#define CK_242X (1 << 4) 33#define CK_242X (1 << 4)
34#define CK_243X (1 << 5) 34#define CK_243X (1 << 5) /* 243x, 253x */
35#define CK_3XXX (1 << 6) /* OMAP3 + AM3 common clocks*/ 35#define CK_3430ES1 (1 << 6) /* 34xxES1 only */
36#define CK_343X (1 << 7) /* OMAP34xx common clocks */ 36#define CK_3430ES2PLUS (1 << 7) /* 34xxES2, ES3, non-Sitara 35xx only */
37#define CK_3430ES1 (1 << 8) /* 34xxES1 only */ 37#define CK_3505 (1 << 8)
38#define CK_3430ES2 (1 << 9) /* 34xxES2, ES3, non-Sitara 35xx only */ 38#define CK_3517 (1 << 9)
39#define CK_3505 (1 << 10) 39#define CK_36XX (1 << 10) /* 36xx/37xx-specific clocks */
40#define CK_3517 (1 << 11) 40#define CK_443X (1 << 11)
41#define CK_36XX (1 << 12) /* OMAP36xx/37xx-specific clocks */
42#define CK_443X (1 << 13)
43 41
44#define CK_AM35XX (CK_3505 | CK_3517) /* all Sitara AM35xx */
45 42
43#define CK_34XX (CK_3430ES1 | CK_3430ES2PLUS)
44#define CK_AM35XX (CK_3505 | CK_3517) /* all Sitara AM35xx */
45#define CK_3XXX (CK_34XX | CK_AM35XX | CK_36XX)
46 46
47 47
48#endif 48#endif
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index fef4696dcf67..6e223158268b 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -49,13 +49,18 @@ struct clkops {
49/* struct clksel_rate.flags possibilities */ 49/* struct clksel_rate.flags possibilities */
50#define RATE_IN_242X (1 << 0) 50#define RATE_IN_242X (1 << 0)
51#define RATE_IN_243X (1 << 1) 51#define RATE_IN_243X (1 << 1)
52#define RATE_IN_3XXX (1 << 2) /* rates common to all OMAP3 */ 52#define RATE_IN_3430ES1 (1 << 2) /* 3430ES1 rates only */
53#define RATE_IN_3430ES2 (1 << 3) /* 3430ES2 rates only */ 53#define RATE_IN_3430ES2PLUS (1 << 3) /* 3430 ES >= 2 rates only */
54#define RATE_IN_36XX (1 << 4) 54#define RATE_IN_36XX (1 << 4)
55#define RATE_IN_4430 (1 << 5) 55#define RATE_IN_4430 (1 << 5)
56 56
57#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X) 57#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X)
58#define RATE_IN_3430ES2PLUS (RATE_IN_3430ES2 | RATE_IN_36XX) 58#define RATE_IN_34XX (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS)
59#define RATE_IN_3XXX (RATE_IN_34XX | RATE_IN_36XX)
60
61/* RATE_IN_3430ES2PLUS_36XX includes 34xx/35xx with ES >=2, and all 36xx/37xx */
62#define RATE_IN_3430ES2PLUS_36XX (RATE_IN_3430ES2PLUS | RATE_IN_36XX)
63
59 64
60/** 65/**
61 * struct clksel_rate - register bitfield values corresponding to clk divisors 66 * struct clksel_rate - register bitfield values corresponding to clk divisors
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-23 18:22:04 -0500