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-rw-r--r--arch/arm/Kconfig16
-rw-r--r--arch/arm/Makefile4
-rw-r--r--arch/arm/configs/kirkwood_defconfig8
-rw-r--r--arch/arm/include/asm/elf.h4
-rw-r--r--arch/arm/include/asm/mach/pci.h1
-rw-r--r--arch/arm/include/asm/stackprotector.h38
-rw-r--r--arch/arm/kernel/asm-offsets.c3
-rw-r--r--arch/arm/kernel/entry-armv.S8
-rw-r--r--arch/arm/kernel/process.c13
-rw-r--r--arch/arm/mach-cns3xxx/Makefile3
-rw-r--r--arch/arm/mach-cns3xxx/cns3420vb.c4
-rw-r--r--arch/arm/mach-cns3xxx/devices.c111
-rw-r--r--arch/arm/mach-cns3xxx/devices.h20
-rw-r--r--arch/arm/mach-cns3xxx/include/mach/cns3xxx.h91
-rw-r--r--arch/arm/mach-cns3xxx/pcie.c389
-rw-r--r--arch/arm/mach-cns3xxx/pm.c31
-rw-r--r--arch/arm/mach-dove/common.c61
-rw-r--r--arch/arm/mach-dove/common.h2
-rw-r--r--arch/arm/mach-dove/dove-db-setup.c2
-rw-r--r--arch/arm/mach-kirkwood/Kconfig19
-rw-r--r--arch/arm/mach-kirkwood/Makefile2
-rw-r--r--arch/arm/mach-kirkwood/addr-map.c10
-rw-r--r--arch/arm/mach-kirkwood/common.c38
-rw-r--r--arch/arm/mach-kirkwood/common.h5
-rw-r--r--arch/arm/mach-kirkwood/db88f6281-bp-setup.c18
-rw-r--r--arch/arm/mach-kirkwood/include/mach/bridge-regs.h3
-rw-r--r--arch/arm/mach-kirkwood/include/mach/irqs.h1
-rw-r--r--arch/arm/mach-kirkwood/include/mach/kirkwood.h39
-rw-r--r--arch/arm/mach-kirkwood/include/mach/leds-ns2.h26
-rw-r--r--arch/arm/mach-kirkwood/mpp.c3
-rw-r--r--arch/arm/mach-kirkwood/mpp.h596
-rw-r--r--arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c2
-rw-r--r--arch/arm/mach-kirkwood/netspace_v2-setup.c104
-rw-r--r--arch/arm/mach-kirkwood/netxbig_v2-setup.c32
-rw-r--r--arch/arm/mach-kirkwood/openrd-setup.c29
-rw-r--r--arch/arm/mach-kirkwood/pcie.c174
-rw-r--r--arch/arm/mach-kirkwood/rd88f6192-nas-setup.c2
-rw-r--r--arch/arm/mach-kirkwood/rd88f6281-setup.c2
-rw-r--r--arch/arm/mach-kirkwood/t5325-setup.c194
-rw-r--r--arch/arm/mach-kirkwood/ts219-setup.c11
-rw-r--r--arch/arm/mach-kirkwood/ts41x-setup.c39
-rw-r--r--arch/arm/mach-msm/Makefile2
-rw-r--r--arch/arm/mach-msm/board-trout-gpio.c112
-rw-r--r--arch/arm/mach-msm/board-trout.h157
-rw-r--r--arch/arm/mach-msm/include/mach/gpio.h7
-rw-r--r--arch/arm/mach-orion5x/Kconfig1
-rw-r--r--arch/arm/mach-orion5x/dns323-setup.c370
-rw-r--r--arch/arm/mach-orion5x/include/mach/system.h2
-rw-r--r--arch/arm/mm/init.c19
-rw-r--r--arch/arm/mm/mmap.c4
-rw-r--r--arch/arm/plat-orion/pcie.c34
51 files changed, 2307 insertions, 559 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 9a189f757c93..738f404d5e34 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -301,6 +301,7 @@ config ARCH_CNS3XXX
301 select CPU_V6 301 select CPU_V6
302 select GENERIC_CLOCKEVENTS 302 select GENERIC_CLOCKEVENTS
303 select ARM_GIC 303 select ARM_GIC
304 select PCI_DOMAINS if PCI
304 help 305 help
305 Support for Cavium Networks CNS3XXX platform. 306 Support for Cavium Networks CNS3XXX platform.
306 307
@@ -599,6 +600,7 @@ config ARCH_MSM
599 bool "Qualcomm MSM" 600 bool "Qualcomm MSM"
600 select HAVE_CLK 601 select HAVE_CLK
601 select GENERIC_CLOCKEVENTS 602 select GENERIC_CLOCKEVENTS
603 select ARCH_REQUIRE_GPIOLIB
602 help 604 help
603 Support for Qualcomm MSM/QSD based systems. This runs on the 605 Support for Qualcomm MSM/QSD based systems. This runs on the
604 apps processor of the MSM/QSD and depends on a shared memory 606 apps processor of the MSM/QSD and depends on a shared memory
@@ -1075,7 +1077,7 @@ config ISA_DMA_API
1075 bool 1077 bool
1076 1078
1077config PCI 1079config PCI
1078 bool "PCI support" if ARCH_INTEGRATOR_AP || ARCH_VERSATILE_PB || ARCH_IXP4XX || ARCH_KS8695 || MACH_ARMCORE 1080 bool "PCI support" if ARCH_INTEGRATOR_AP || ARCH_VERSATILE_PB || ARCH_IXP4XX || ARCH_KS8695 || MACH_ARMCORE || ARCH_CNS3XXX
1079 help 1081 help
1080 Find out whether you have a PCI motherboard. PCI is the name of a 1082 Find out whether you have a PCI motherboard. PCI is the name of a
1081 bus system, i.e. the way the CPU talks to the other stuff inside 1083 bus system, i.e. the way the CPU talks to the other stuff inside
@@ -1390,6 +1392,18 @@ config UACCESS_WITH_MEMCPY
1390 However, if the CPU data cache is using a write-allocate mode, 1392 However, if the CPU data cache is using a write-allocate mode,
1391 this option is unlikely to provide any performance gain. 1393 this option is unlikely to provide any performance gain.
1392 1394
1395config CC_STACKPROTECTOR
1396 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1397 help
1398 This option turns on the -fstack-protector GCC feature. This
1399 feature puts, at the beginning of functions, a canary value on
1400 the stack just before the return address, and validates
1401 the value just before actually returning. Stack based buffer
1402 overflows (that need to overwrite this return address) now also
1403 overwrite the canary, which gets detected and the attack is then
1404 neutralized via a kernel panic.
1405 This feature requires gcc version 4.2 or above.
1406
1393endmenu 1407endmenu
1394 1408
1395menu "Boot options" 1409menu "Boot options"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 6a612c5483ce..71cbb17ff89c 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -34,6 +34,10 @@ ifeq ($(CONFIG_FRAME_POINTER),y)
34KBUILD_CFLAGS +=-fno-omit-frame-pointer -mapcs -mno-sched-prolog 34KBUILD_CFLAGS +=-fno-omit-frame-pointer -mapcs -mno-sched-prolog
35endif 35endif
36 36
37ifeq ($(CONFIG_CC_STACKPROTECTOR),y)
38KBUILD_CFLAGS +=-fstack-protector
39endif
40
37ifeq ($(CONFIG_CPU_BIG_ENDIAN),y) 41ifeq ($(CONFIG_CPU_BIG_ENDIAN),y)
38KBUILD_CPPFLAGS += -mbig-endian 42KBUILD_CPPFLAGS += -mbig-endian
39AS += -EB 43AS += -EB
diff --git a/arch/arm/configs/kirkwood_defconfig b/arch/arm/configs/kirkwood_defconfig
index f2e3a9088df6..ccc9c9959b82 100644
--- a/arch/arm/configs/kirkwood_defconfig
+++ b/arch/arm/configs/kirkwood_defconfig
@@ -13,11 +13,19 @@ CONFIG_MACH_RD88F6192_NAS=y
13CONFIG_MACH_RD88F6281=y 13CONFIG_MACH_RD88F6281=y
14CONFIG_MACH_MV88F6281GTW_GE=y 14CONFIG_MACH_MV88F6281GTW_GE=y
15CONFIG_MACH_SHEEVAPLUG=y 15CONFIG_MACH_SHEEVAPLUG=y
16CONFIG_MACH_ESATA_SHEEVAPLUG=y
17CONFIG_MACH_GURUPLUG=y
16CONFIG_MACH_TS219=y 18CONFIG_MACH_TS219=y
17CONFIG_MACH_TS41X=y 19CONFIG_MACH_TS41X=y
18CONFIG_MACH_OPENRD_BASE=y 20CONFIG_MACH_OPENRD_BASE=y
19CONFIG_MACH_OPENRD_CLIENT=y 21CONFIG_MACH_OPENRD_CLIENT=y
22CONFIG_MACH_OPENRD_ULTIMATE=y
20CONFIG_MACH_NETSPACE_V2=y 23CONFIG_MACH_NETSPACE_V2=y
24CONFIG_MACH_INETSPACE_V2=y
25CONFIG_MACH_NETSPACE_MAX_V2=y
26CONFIG_MACH_NET2BIG_V2=y
27CONFIG_MACH_NET5BIG_V2=y
28CONFIG_MACH_T5325=y
21# CONFIG_CPU_FEROCEON_OLD_ID is not set 29# CONFIG_CPU_FEROCEON_OLD_ID is not set
22CONFIG_NO_HZ=y 30CONFIG_NO_HZ=y
23CONFIG_HIGH_RES_TIMERS=y 31CONFIG_HIGH_RES_TIMERS=y
diff --git a/arch/arm/include/asm/elf.h b/arch/arm/include/asm/elf.h
index 51662feb9f1d..6750b8e45a49 100644
--- a/arch/arm/include/asm/elf.h
+++ b/arch/arm/include/asm/elf.h
@@ -121,4 +121,8 @@ int dump_task_regs(struct task_struct *t, elf_gregset_t *elfregs);
121extern void elf_set_personality(const struct elf32_hdr *); 121extern void elf_set_personality(const struct elf32_hdr *);
122#define SET_PERSONALITY(ex) elf_set_personality(&(ex)) 122#define SET_PERSONALITY(ex) elf_set_personality(&(ex))
123 123
124struct mm_struct;
125extern unsigned long arch_randomize_brk(struct mm_struct *mm);
126#define arch_randomize_brk arch_randomize_brk
127
124#endif 128#endif
diff --git a/arch/arm/include/asm/mach/pci.h b/arch/arm/include/asm/mach/pci.h
index 52f0da1e97df..16330bd0657c 100644
--- a/arch/arm/include/asm/mach/pci.h
+++ b/arch/arm/include/asm/mach/pci.h
@@ -46,6 +46,7 @@ struct pci_sys_data {
46 /* IRQ mapping */ 46 /* IRQ mapping */
47 int (*map_irq)(struct pci_dev *, u8, u8); 47 int (*map_irq)(struct pci_dev *, u8, u8);
48 struct hw_pci *hw; 48 struct hw_pci *hw;
49 void *private_data; /* platform controller private data */
49}; 50};
50 51
51/* 52/*
diff --git a/arch/arm/include/asm/stackprotector.h b/arch/arm/include/asm/stackprotector.h
new file mode 100644
index 000000000000..de003327be97
--- /dev/null
+++ b/arch/arm/include/asm/stackprotector.h
@@ -0,0 +1,38 @@
1/*
2 * GCC stack protector support.
3 *
4 * Stack protector works by putting predefined pattern at the start of
5 * the stack frame and verifying that it hasn't been overwritten when
6 * returning from the function. The pattern is called stack canary
7 * and gcc expects it to be defined by a global variable called
8 * "__stack_chk_guard" on ARM. This unfortunately means that on SMP
9 * we cannot have a different canary value per task.
10 */
11
12#ifndef _ASM_STACKPROTECTOR_H
13#define _ASM_STACKPROTECTOR_H 1
14
15#include <linux/random.h>
16#include <linux/version.h>
17
18extern unsigned long __stack_chk_guard;
19
20/*
21 * Initialize the stackprotector canary value.
22 *
23 * NOTE: this must only be called from functions that never return,
24 * and it must always be inlined.
25 */
26static __always_inline void boot_init_stack_canary(void)
27{
28 unsigned long canary;
29
30 /* Try to get a semi random initial value. */
31 get_random_bytes(&canary, sizeof(canary));
32 canary ^= LINUX_VERSION_CODE;
33
34 current->stack_canary = canary;
35 __stack_chk_guard = current->stack_canary;
36}
37
38#endif /* _ASM_STACKPROTECTOR_H */
diff --git a/arch/arm/kernel/asm-offsets.c b/arch/arm/kernel/asm-offsets.c
index 883511522fca..85f2a019f77b 100644
--- a/arch/arm/kernel/asm-offsets.c
+++ b/arch/arm/kernel/asm-offsets.c
@@ -40,6 +40,9 @@
40int main(void) 40int main(void)
41{ 41{
42 DEFINE(TSK_ACTIVE_MM, offsetof(struct task_struct, active_mm)); 42 DEFINE(TSK_ACTIVE_MM, offsetof(struct task_struct, active_mm));
43#ifdef CONFIG_CC_STACKPROTECTOR
44 DEFINE(TSK_STACK_CANARY, offsetof(struct task_struct, stack_canary));
45#endif
43 BLANK(); 46 BLANK();
44 DEFINE(TI_FLAGS, offsetof(struct thread_info, flags)); 47 DEFINE(TI_FLAGS, offsetof(struct thread_info, flags));
45 DEFINE(TI_PREEMPT, offsetof(struct thread_info, preempt_count)); 48 DEFINE(TI_PREEMPT, offsetof(struct thread_info, preempt_count));
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index 3fd7861de4d1..9ef9a8266996 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -741,6 +741,11 @@ ENTRY(__switch_to)
741 mov r4, #0xffff0fff 741 mov r4, #0xffff0fff
742 str r3, [r4, #-15] @ TLS val at 0xffff0ff0 742 str r3, [r4, #-15] @ TLS val at 0xffff0ff0
743#endif 743#endif
744#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
745 ldr r7, [r2, #TI_TASK]
746 ldr r8, =__stack_chk_guard
747 ldr r7, [r7, #TSK_STACK_CANARY]
748#endif
744#ifdef CONFIG_MMU 749#ifdef CONFIG_MMU
745 mcr p15, 0, r6, c3, c0, 0 @ Set domain register 750 mcr p15, 0, r6, c3, c0, 0 @ Set domain register
746#endif 751#endif
@@ -749,6 +754,9 @@ ENTRY(__switch_to)
749 ldr r0, =thread_notify_head 754 ldr r0, =thread_notify_head
750 mov r1, #THREAD_NOTIFY_SWITCH 755 mov r1, #THREAD_NOTIFY_SWITCH
751 bl atomic_notifier_call_chain 756 bl atomic_notifier_call_chain
757#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
758 str r7, [r8]
759#endif
752 THUMB( mov ip, r4 ) 760 THUMB( mov ip, r4 )
753 mov r0, r5 761 mov r0, r5
754 ARM( ldmia r4, {r4 - sl, fp, sp, pc} ) @ Load all regs saved previously 762 ARM( ldmia r4, {r4 - sl, fp, sp, pc} ) @ Load all regs saved previously
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index a4a9cc88bec7..43557a1eb610 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -28,6 +28,7 @@
28#include <linux/tick.h> 28#include <linux/tick.h>
29#include <linux/utsname.h> 29#include <linux/utsname.h>
30#include <linux/uaccess.h> 30#include <linux/uaccess.h>
31#include <linux/random.h>
31 32
32#include <asm/leds.h> 33#include <asm/leds.h>
33#include <asm/processor.h> 34#include <asm/processor.h>
@@ -36,6 +37,12 @@
36#include <asm/stacktrace.h> 37#include <asm/stacktrace.h>
37#include <asm/mach/time.h> 38#include <asm/mach/time.h>
38 39
40#ifdef CONFIG_CC_STACKPROTECTOR
41#include <linux/stackprotector.h>
42unsigned long __stack_chk_guard __read_mostly;
43EXPORT_SYMBOL(__stack_chk_guard);
44#endif
45
39static const char *processor_modes[] = { 46static const char *processor_modes[] = {
40 "USER_26", "FIQ_26" , "IRQ_26" , "SVC_26" , "UK4_26" , "UK5_26" , "UK6_26" , "UK7_26" , 47 "USER_26", "FIQ_26" , "IRQ_26" , "SVC_26" , "UK4_26" , "UK5_26" , "UK6_26" , "UK7_26" ,
41 "UK8_26" , "UK9_26" , "UK10_26", "UK11_26", "UK12_26", "UK13_26", "UK14_26", "UK15_26", 48 "UK8_26" , "UK9_26" , "UK10_26", "UK11_26", "UK12_26", "UK13_26", "UK14_26", "UK15_26",
@@ -426,3 +433,9 @@ unsigned long get_wchan(struct task_struct *p)
426 } while (count ++ < 16); 433 } while (count ++ < 16);
427 return 0; 434 return 0;
428} 435}
436
437unsigned long arch_randomize_brk(struct mm_struct *mm)
438{
439 unsigned long range_end = mm->brk + 0x02000000;
440 return randomize_range(mm->brk, range_end, 0) ? : mm->brk;
441}
diff --git a/arch/arm/mach-cns3xxx/Makefile b/arch/arm/mach-cns3xxx/Makefile
index 427507a2d696..11033f1c2e23 100644
--- a/arch/arm/mach-cns3xxx/Makefile
+++ b/arch/arm/mach-cns3xxx/Makefile
@@ -1,2 +1,3 @@
1obj-$(CONFIG_ARCH_CNS3XXX) += core.o pm.o 1obj-$(CONFIG_ARCH_CNS3XXX) += core.o pm.o devices.o
2obj-$(CONFIG_PCI) += pcie.o
2obj-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o 3obj-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o
diff --git a/arch/arm/mach-cns3xxx/cns3420vb.c b/arch/arm/mach-cns3xxx/cns3420vb.c
index 2e30c8288740..9df8391fd78a 100644
--- a/arch/arm/mach-cns3xxx/cns3420vb.c
+++ b/arch/arm/mach-cns3xxx/cns3420vb.c
@@ -32,6 +32,7 @@
32#include <mach/cns3xxx.h> 32#include <mach/cns3xxx.h>
33#include <mach/irqs.h> 33#include <mach/irqs.h>
34#include "core.h" 34#include "core.h"
35#include "devices.h"
35 36
36/* 37/*
37 * NOR Flash 38 * NOR Flash
@@ -117,6 +118,9 @@ static void __init cns3420_init(void)
117{ 118{
118 platform_add_devices(cns3420_pdevs, ARRAY_SIZE(cns3420_pdevs)); 119 platform_add_devices(cns3420_pdevs, ARRAY_SIZE(cns3420_pdevs));
119 120
121 cns3xxx_ahci_init();
122 cns3xxx_sdhci_init();
123
120 pm_power_off = cns3xxx_power_off; 124 pm_power_off = cns3xxx_power_off;
121} 125}
122 126
diff --git a/arch/arm/mach-cns3xxx/devices.c b/arch/arm/mach-cns3xxx/devices.c
new file mode 100644
index 000000000000..50b4d31c27c0
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/devices.c
@@ -0,0 +1,111 @@
1/*
2 * CNS3xxx common devices
3 *
4 * Copyright 2008 Cavium Networks
5 * Scott Shu
6 * Copyright 2010 MontaVista Software, LLC.
7 * Anton Vorontsov <avorontsov@mvista.com>
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/io.h>
15#include <linux/init.h>
16#include <linux/compiler.h>
17#include <linux/dma-mapping.h>
18#include <linux/platform_device.h>
19#include <mach/cns3xxx.h>
20#include <mach/irqs.h>
21#include "core.h"
22#include "devices.h"
23
24/*
25 * AHCI
26 */
27static struct resource cns3xxx_ahci_resource[] = {
28 [0] = {
29 .start = CNS3XXX_SATA2_BASE,
30 .end = CNS3XXX_SATA2_BASE + CNS3XXX_SATA2_SIZE - 1,
31 .flags = IORESOURCE_MEM,
32 },
33 [1] = {
34 .start = IRQ_CNS3XXX_SATA,
35 .end = IRQ_CNS3XXX_SATA,
36 .flags = IORESOURCE_IRQ,
37 },
38};
39
40static u64 cns3xxx_ahci_dmamask = DMA_BIT_MASK(32);
41
42static struct platform_device cns3xxx_ahci_pdev = {
43 .name = "ahci",
44 .id = 0,
45 .resource = cns3xxx_ahci_resource,
46 .num_resources = ARRAY_SIZE(cns3xxx_ahci_resource),
47 .dev = {
48 .dma_mask = &cns3xxx_ahci_dmamask,
49 .coherent_dma_mask = DMA_BIT_MASK(32),
50 },
51};
52
53void __init cns3xxx_ahci_init(void)
54{
55 u32 tmp;
56
57 tmp = __raw_readl(MISC_SATA_POWER_MODE);
58 tmp |= 0x1 << 16; /* Disable SATA PHY 0 from SLUMBER Mode */
59 tmp |= 0x1 << 17; /* Disable SATA PHY 1 from SLUMBER Mode */
60 __raw_writel(tmp, MISC_SATA_POWER_MODE);
61
62 /* Enable SATA PHY */
63 cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY0);
64 cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY1);
65
66 /* Enable SATA Clock */
67 cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_SATA);
68
69 /* De-Asscer SATA Reset */
70 cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SATA));
71
72 platform_device_register(&cns3xxx_ahci_pdev);
73}
74
75/*
76 * SDHCI
77 */
78static struct resource cns3xxx_sdhci_resources[] = {
79 [0] = {
80 .start = CNS3XXX_SDIO_BASE,
81 .end = CNS3XXX_SDIO_BASE + SZ_4K - 1,
82 .flags = IORESOURCE_MEM,
83 },
84 [1] = {
85 .start = IRQ_CNS3XXX_SDIO,
86 .end = IRQ_CNS3XXX_SDIO,
87 .flags = IORESOURCE_IRQ,
88 },
89};
90
91static struct platform_device cns3xxx_sdhci_pdev = {
92 .name = "sdhci-cns3xxx",
93 .id = 0,
94 .num_resources = ARRAY_SIZE(cns3xxx_sdhci_resources),
95 .resource = cns3xxx_sdhci_resources,
96};
97
98void __init cns3xxx_sdhci_init(void)
99{
100 u32 __iomem *gpioa = __io(CNS3XXX_MISC_BASE_VIRT + 0x0014);
101 u32 gpioa_pins = __raw_readl(gpioa);
102
103 /* MMC/SD pins share with GPIOA */
104 gpioa_pins |= 0x1fff0004;
105 __raw_writel(gpioa_pins, gpioa);
106
107 cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SDIO));
108 cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SDIO));
109
110 platform_device_register(&cns3xxx_sdhci_pdev);
111}
diff --git a/arch/arm/mach-cns3xxx/devices.h b/arch/arm/mach-cns3xxx/devices.h
new file mode 100644
index 000000000000..27e15a10aa85
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/devices.h
@@ -0,0 +1,20 @@
1/*
2 * CNS3xxx common devices
3 *
4 * Copyright 2008 Cavium Networks
5 * Scott Shu
6 * Copyright 2010 MontaVista Software, LLC.
7 * Anton Vorontsov <avorontsov@mvista.com>
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 */
13
14#ifndef __CNS3XXX_DEVICES_H_
15#define __CNS3XXX_DEVICES_H_
16
17void __init cns3xxx_ahci_init(void);
18void __init cns3xxx_sdhci_init(void);
19
20#endif /* __CNS3XXX_DEVICES_H_ */
diff --git a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h b/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
index 8a2f5a21d4ee..6dbce13771ca 100644
--- a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
+++ b/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
@@ -247,37 +247,36 @@
247 * Misc block 247 * Misc block
248 */ 248 */
249#define MISC_MEM_MAP(offs) (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + (offs)) 249#define MISC_MEM_MAP(offs) (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + (offs))
250#define MISC_MEM_MAP_VALUE(offset) (*((volatile unsigned int *)(CNS3XXX_MISC_BASE_VIRT + (offset)))) 250
251 251#define MISC_MEMORY_REMAP_REG MISC_MEM_MAP(0x00)
252#define MISC_MEMORY_REMAP_REG MISC_MEM_MAP_VALUE(0x00) 252#define MISC_CHIP_CONFIG_REG MISC_MEM_MAP(0x04)
253#define MISC_CHIP_CONFIG_REG MISC_MEM_MAP_VALUE(0x04) 253#define MISC_DEBUG_PROBE_DATA_REG MISC_MEM_MAP(0x08)
254#define MISC_DEBUG_PROBE_DATA_REG MISC_MEM_MAP_VALUE(0x08) 254#define MISC_DEBUG_PROBE_SELECTION_REG MISC_MEM_MAP(0x0C)
255#define MISC_DEBUG_PROBE_SELECTION_REG MISC_MEM_MAP_VALUE(0x0C) 255#define MISC_IO_PIN_FUNC_SELECTION_REG MISC_MEM_MAP(0x10)
256#define MISC_IO_PIN_FUNC_SELECTION_REG MISC_MEM_MAP_VALUE(0x10) 256#define MISC_GPIOA_PIN_ENABLE_REG MISC_MEM_MAP(0x14)
257#define MISC_GPIOA_PIN_ENABLE_REG MISC_MEM_MAP_VALUE(0x14) 257#define MISC_GPIOB_PIN_ENABLE_REG MISC_MEM_MAP(0x18)
258#define MISC_GPIOB_PIN_ENABLE_REG MISC_MEM_MAP_VALUE(0x18) 258#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_A MISC_MEM_MAP(0x1C)
259#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_A MISC_MEM_MAP_VALUE(0x1C) 259#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_B MISC_MEM_MAP(0x20)
260#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_B MISC_MEM_MAP_VALUE(0x20) 260#define MISC_GPIOA_15_0_PULL_CTRL_REG MISC_MEM_MAP(0x24)
261#define MISC_GPIOA_15_0_PULL_CTRL_REG MISC_MEM_MAP_VALUE(0x24) 261#define MISC_GPIOA_16_31_PULL_CTRL_REG MISC_MEM_MAP(0x28)
262#define MISC_GPIOA_16_31_PULL_CTRL_REG MISC_MEM_MAP_VALUE(0x28) 262#define MISC_GPIOB_15_0_PULL_CTRL_REG MISC_MEM_MAP(0x2C)
263#define MISC_GPIOB_15_0_PULL_CTRL_REG MISC_MEM_MAP_VALUE(0x2C) 263#define MISC_GPIOB_16_31_PULL_CTRL_REG MISC_MEM_MAP(0x30)
264#define MISC_GPIOB_16_31_PULL_CTRL_REG MISC_MEM_MAP_VALUE(0x30) 264#define MISC_IO_PULL_CTRL_REG MISC_MEM_MAP(0x34)
265#define MISC_IO_PULL_CTRL_REG MISC_MEM_MAP_VALUE(0x34) 265#define MISC_E_FUSE_31_0_REG MISC_MEM_MAP(0x40)
266#define MISC_E_FUSE_31_0_REG MISC_MEM_MAP_VALUE(0x40) 266#define MISC_E_FUSE_63_32_REG MISC_MEM_MAP(0x44)
267#define MISC_E_FUSE_63_32_REG MISC_MEM_MAP_VALUE(0x44) 267#define MISC_E_FUSE_95_64_REG MISC_MEM_MAP(0x48)
268#define MISC_E_FUSE_95_64_REG MISC_MEM_MAP_VALUE(0x48) 268#define MISC_E_FUSE_127_96_REG MISC_MEM_MAP(0x4C)
269#define MISC_E_FUSE_127_96_REG MISC_MEM_MAP_VALUE(0x4C) 269#define MISC_SOFTWARE_TEST_1_REG MISC_MEM_MAP(0x50)
270#define MISC_SOFTWARE_TEST_1_REG MISC_MEM_MAP_VALUE(0x50) 270#define MISC_SOFTWARE_TEST_2_REG MISC_MEM_MAP(0x54)
271#define MISC_SOFTWARE_TEST_2_REG MISC_MEM_MAP_VALUE(0x54) 271
272 272#define MISC_SATA_POWER_MODE MISC_MEM_MAP(0x310)
273#define MISC_SATA_POWER_MODE MISC_MEM_MAP_VALUE(0x310) 273
274 274#define MISC_USB_CFG_REG MISC_MEM_MAP(0x800)
275#define MISC_USB_CFG_REG MISC_MEM_MAP_VALUE(0x800) 275#define MISC_USB_STS_REG MISC_MEM_MAP(0x804)
276#define MISC_USB_STS_REG MISC_MEM_MAP_VALUE(0x804) 276#define MISC_USBPHY00_CFG_REG MISC_MEM_MAP(0x808)
277#define MISC_USBPHY00_CFG_REG MISC_MEM_MAP_VALUE(0x808) 277#define MISC_USBPHY01_CFG_REG MISC_MEM_MAP(0x80c)
278#define MISC_USBPHY01_CFG_REG MISC_MEM_MAP_VALUE(0x80c) 278#define MISC_USBPHY10_CFG_REG MISC_MEM_MAP(0x810)
279#define MISC_USBPHY10_CFG_REG MISC_MEM_MAP_VALUE(0x810) 279#define MISC_USBPHY11_CFG_REG MISC_MEM_MAP(0x814)
280#define MISC_USBPHY11_CFG_REG MISC_MEM_MAP_VALUE(0x814)
281 280
282#define MISC_PCIEPHY_CMCTL(x) MISC_MEM_MAP(0x900 + (x) * 0x004) 281#define MISC_PCIEPHY_CMCTL(x) MISC_MEM_MAP(0x900 + (x) * 0x004)
283#define MISC_PCIEPHY_CTL(x) MISC_MEM_MAP(0x940 + (x) * 0x100) 282#define MISC_PCIEPHY_CTL(x) MISC_MEM_MAP(0x940 + (x) * 0x100)
@@ -300,21 +299,21 @@
300/* 299/*
301 * Power management and clock control 300 * Power management and clock control
302 */ 301 */
303#define PMU_REG_VALUE(offset) (*((volatile unsigned int *)(CNS3XXX_PM_BASE_VIRT + (offset)))) 302#define PMU_MEM_MAP(offs) (void __iomem *)(CNS3XXX_PM_BASE_VIRT + (offs))
304 303
305#define PM_CLK_GATE_REG PMU_REG_VALUE(0x000) 304#define PM_CLK_GATE_REG PMU_MEM_MAP(0x000)
306#define PM_SOFT_RST_REG PMU_REG_VALUE(0x004) 305#define PM_SOFT_RST_REG PMU_MEM_MAP(0x004)
307#define PM_HS_CFG_REG PMU_REG_VALUE(0x008) 306#define PM_HS_CFG_REG PMU_MEM_MAP(0x008)
308#define PM_CACTIVE_STA_REG PMU_REG_VALUE(0x00C) 307#define PM_CACTIVE_STA_REG PMU_MEM_MAP(0x00C)
309#define PM_PWR_STA_REG PMU_REG_VALUE(0x010) 308#define PM_PWR_STA_REG PMU_MEM_MAP(0x010)
310#define PM_CLK_CTRL_REG PMU_REG_VALUE(0x014) 309#define PM_CLK_CTRL_REG PMU_MEM_MAP(0x014)
311#define PM_PLL_LCD_I2S_CTRL_REG PMU_REG_VALUE(0x018) 310#define PM_PLL_LCD_I2S_CTRL_REG PMU_MEM_MAP(0x018)
312#define PM_PLL_HM_PD_CTRL_REG PMU_REG_VALUE(0x01C) 311#define PM_PLL_HM_PD_CTRL_REG PMU_MEM_MAP(0x01C)
313#define PM_REGULAT_CTRL_REG PMU_REG_VALUE(0x020) 312#define PM_REGULAT_CTRL_REG PMU_MEM_MAP(0x020)
314#define PM_WDT_CTRL_REG PMU_REG_VALUE(0x024) 313#define PM_WDT_CTRL_REG PMU_MEM_MAP(0x024)
315#define PM_WU_CTRL0_REG PMU_REG_VALUE(0x028) 314#define PM_WU_CTRL0_REG PMU_MEM_MAP(0x028)
316#define PM_WU_CTRL1_REG PMU_REG_VALUE(0x02C) 315#define PM_WU_CTRL1_REG PMU_MEM_MAP(0x02C)
317#define PM_CSR_REG PMU_REG_VALUE(0x030) 316#define PM_CSR_REG PMU_MEM_MAP(0x030)
318 317
319/* PM_CLK_GATE_REG */ 318/* PM_CLK_GATE_REG */
320#define PM_CLK_GATE_REG_OFFSET_SDIO (25) 319#define PM_CLK_GATE_REG_OFFSET_SDIO (25)
diff --git a/arch/arm/mach-cns3xxx/pcie.c b/arch/arm/mach-cns3xxx/pcie.c
new file mode 100644
index 000000000000..38088c36936c
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/pcie.c
@@ -0,0 +1,389 @@
1/*
2 * PCI-E support for CNS3xxx
3 *
4 * Copyright 2008 Cavium Networks
5 * Richard Liu <richard.liu@caviumnetworks.com>
6 * Copyright 2010 MontaVista Software, LLC.
7 * Anton Vorontsov <avorontsov@mvista.com>
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/init.h>
15#include <linux/kernel.h>
16#include <linux/bug.h>
17#include <linux/pci.h>
18#include <linux/io.h>
19#include <linux/ioport.h>
20#include <linux/interrupt.h>
21#include <linux/ptrace.h>
22#include <asm/mach/map.h>
23#include <mach/cns3xxx.h>
24#include "core.h"
25
26enum cns3xxx_access_type {
27 CNS3XXX_HOST_TYPE = 0,
28 CNS3XXX_CFG0_TYPE,
29 CNS3XXX_CFG1_TYPE,
30 CNS3XXX_NUM_ACCESS_TYPES,
31};
32
33struct cns3xxx_pcie {
34 struct map_desc cfg_bases[CNS3XXX_NUM_ACCESS_TYPES];
35 unsigned int irqs[2];
36 struct resource res_io;
37 struct resource res_mem;
38 struct hw_pci hw_pci;
39
40 bool linked;
41};
42
43static struct cns3xxx_pcie cns3xxx_pcie[]; /* forward decl. */
44
45static struct cns3xxx_pcie *sysdata_to_cnspci(void *sysdata)
46{
47 struct pci_sys_data *root = sysdata;
48
49 return &cns3xxx_pcie[root->domain];
50}
51
52static struct cns3xxx_pcie *pdev_to_cnspci(struct pci_dev *dev)
53{
54 return sysdata_to_cnspci(dev->sysdata);
55}
56
57static struct cns3xxx_pcie *pbus_to_cnspci(struct pci_bus *bus)
58{
59 return sysdata_to_cnspci(bus->sysdata);
60}
61
62static void __iomem *cns3xxx_pci_cfg_base(struct pci_bus *bus,
63 unsigned int devfn, int where)
64{
65 struct cns3xxx_pcie *cnspci = pbus_to_cnspci(bus);
66 int busno = bus->number;
67 int slot = PCI_SLOT(devfn);
68 int offset;
69 enum cns3xxx_access_type type;
70 void __iomem *base;
71
72 /* If there is no link, just show the CNS PCI bridge. */
73 if (!cnspci->linked && (busno > 0 || slot > 0))
74 return NULL;
75
76 /*
77 * The CNS PCI bridge doesn't fit into the PCI hierarchy, though
78 * we still want to access it. For this to work, we must place
79 * the first device on the same bus as the CNS PCI bridge.
80 */
81 if (busno == 0) {
82 if (slot > 1)
83 return NULL;
84 type = slot;
85 } else {
86 type = CNS3XXX_CFG1_TYPE;
87 }
88
89 base = (void __iomem *)cnspci->cfg_bases[type].virtual;
90 offset = ((busno & 0xf) << 20) | (devfn << 12) | (where & 0xffc);
91
92 return base + offset;
93}
94
95static int cns3xxx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
96 int where, int size, u32 *val)
97{
98 u32 v;
99 void __iomem *base;
100 u32 mask = (0x1ull << (size * 8)) - 1;
101 int shift = (where % 4) * 8;
102
103 base = cns3xxx_pci_cfg_base(bus, devfn, where);
104 if (!base) {
105 *val = 0xffffffff;
106 return PCIBIOS_SUCCESSFUL;
107 }
108
109 v = __raw_readl(base);
110
111 if (bus->number == 0 && devfn == 0 &&
112 (where & 0xffc) == PCI_CLASS_REVISION) {
113 /*
114 * RC's class is 0xb, but Linux PCI driver needs 0x604
115 * for a PCIe bridge. So we must fixup the class code
116 * to 0x604 here.
117 */
118 v &= 0xff;
119 v |= 0x604 << 16;
120 }
121
122 *val = (v >> shift) & mask;
123
124 return PCIBIOS_SUCCESSFUL;
125}
126
127static int cns3xxx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
128 int where, int size, u32 val)
129{
130 u32 v;
131 void __iomem *base;
132 u32 mask = (0x1ull << (size * 8)) - 1;
133 int shift = (where % 4) * 8;
134
135 base = cns3xxx_pci_cfg_base(bus, devfn, where);
136 if (!base)
137 return PCIBIOS_SUCCESSFUL;
138
139 v = __raw_readl(base);
140
141 v &= ~(mask << shift);
142 v |= (val & mask) << shift;
143
144 __raw_writel(v, base);
145
146 return PCIBIOS_SUCCESSFUL;
147}
148
149static int cns3xxx_pci_setup(int nr, struct pci_sys_data *sys)
150{
151 struct cns3xxx_pcie *cnspci = sysdata_to_cnspci(sys);
152 struct resource *res_io = &cnspci->res_io;
153 struct resource *res_mem = &cnspci->res_mem;
154 struct resource **sysres = sys->resource;
155
156 BUG_ON(request_resource(&iomem_resource, res_io) ||
157 request_resource(&iomem_resource, res_mem));
158
159 sysres[0] = res_io;
160 sysres[1] = res_mem;
161
162 return 1;
163}
164
165static struct pci_ops cns3xxx_pcie_ops = {
166 .read = cns3xxx_pci_read_config,
167 .write = cns3xxx_pci_write_config,
168};
169
170static struct pci_bus *cns3xxx_pci_scan_bus(int nr, struct pci_sys_data *sys)
171{
172 return pci_scan_bus(sys->busnr, &cns3xxx_pcie_ops, sys);
173}
174
175static int cns3xxx_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
176{
177 struct cns3xxx_pcie *cnspci = pdev_to_cnspci(dev);
178 int irq = cnspci->irqs[slot];
179
180 pr_info("PCIe map irq: %04d:%02x:%02x.%02x slot %d, pin %d, irq: %d\n",
181 pci_domain_nr(dev->bus), dev->bus->number, PCI_SLOT(dev->devfn),
182 PCI_FUNC(dev->devfn), slot, pin, irq);
183
184 return irq;
185}
186
187static struct cns3xxx_pcie cns3xxx_pcie[] = {
188 [0] = {
189 .cfg_bases = {
190 [CNS3XXX_HOST_TYPE] = {
191 .virtual = CNS3XXX_PCIE0_HOST_BASE_VIRT,
192 .pfn = __phys_to_pfn(CNS3XXX_PCIE0_HOST_BASE),
193 .length = SZ_16M,
194 .type = MT_DEVICE,
195 },
196 [CNS3XXX_CFG0_TYPE] = {
197 .virtual = CNS3XXX_PCIE0_CFG0_BASE_VIRT,
198 .pfn = __phys_to_pfn(CNS3XXX_PCIE0_CFG0_BASE),
199 .length = SZ_16M,
200 .type = MT_DEVICE,
201 },
202 [CNS3XXX_CFG1_TYPE] = {
203 .virtual = CNS3XXX_PCIE0_CFG1_BASE_VIRT,
204 .pfn = __phys_to_pfn(CNS3XXX_PCIE0_CFG1_BASE),
205 .length = SZ_16M,
206 .type = MT_DEVICE,
207 },
208 },
209 .res_io = {
210 .name = "PCIe0 I/O space",
211 .start = CNS3XXX_PCIE0_IO_BASE,
212 .end = CNS3XXX_PCIE0_IO_BASE + SZ_16M - 1,
213 .flags = IORESOURCE_IO,
214 },
215 .res_mem = {
216 .name = "PCIe0 non-prefetchable",
217 .start = CNS3XXX_PCIE0_MEM_BASE,
218 .end = CNS3XXX_PCIE0_MEM_BASE + SZ_16M - 1,
219 .flags = IORESOURCE_MEM,
220 },
221 .irqs = { IRQ_CNS3XXX_PCIE0_RC, IRQ_CNS3XXX_PCIE0_DEVICE, },
222 .hw_pci = {
223 .domain = 0,
224 .swizzle = pci_std_swizzle,
225 .nr_controllers = 1,
226 .setup = cns3xxx_pci_setup,
227 .scan = cns3xxx_pci_scan_bus,
228 .map_irq = cns3xxx_pcie_map_irq,
229 },
230 },
231 [1] = {
232 .cfg_bases = {
233 [CNS3XXX_HOST_TYPE] = {
234 .virtual = CNS3XXX_PCIE1_HOST_BASE_VIRT,
235 .pfn = __phys_to_pfn(CNS3XXX_PCIE1_HOST_BASE),
236 .length = SZ_16M,
237 .type = MT_DEVICE,
238 },
239 [CNS3XXX_CFG0_TYPE] = {
240 .virtual = CNS3XXX_PCIE1_CFG0_BASE_VIRT,
241 .pfn = __phys_to_pfn(CNS3XXX_PCIE1_CFG0_BASE),
242 .length = SZ_16M,
243 .type = MT_DEVICE,
244 },
245 [CNS3XXX_CFG1_TYPE] = {
246 .virtual = CNS3XXX_PCIE1_CFG1_BASE_VIRT,
247 .pfn = __phys_to_pfn(CNS3XXX_PCIE1_CFG1_BASE),
248 .length = SZ_16M,
249 .type = MT_DEVICE,
250 },
251 },
252 .res_io = {
253 .name = "PCIe1 I/O space",
254 .start = CNS3XXX_PCIE1_IO_BASE,
255 .end = CNS3XXX_PCIE1_IO_BASE + SZ_16M - 1,
256 .flags = IORESOURCE_IO,
257 },
258 .res_mem = {
259 .name = "PCIe1 non-prefetchable",
260 .start = CNS3XXX_PCIE1_MEM_BASE,
261 .end = CNS3XXX_PCIE1_MEM_BASE + SZ_16M - 1,
262 .flags = IORESOURCE_MEM,
263 },
264 .irqs = { IRQ_CNS3XXX_PCIE1_RC, IRQ_CNS3XXX_PCIE1_DEVICE, },
265 .hw_pci = {
266 .domain = 1,
267 .swizzle = pci_std_swizzle,
268 .nr_controllers = 1,
269 .setup = cns3xxx_pci_setup,
270 .scan = cns3xxx_pci_scan_bus,
271 .map_irq = cns3xxx_pcie_map_irq,
272 },
273 },
274};
275
276static void __init cns3xxx_pcie_check_link(struct cns3xxx_pcie *cnspci)
277{
278 int port = cnspci->hw_pci.domain;
279 u32 reg;
280 unsigned long time;
281
282 reg = __raw_readl(MISC_PCIE_CTRL(port));
283 /*
284 * Enable Application Request to 1, it will exit L1 automatically,
285 * but when chip back, it will use another clock, still can use 0x1.
286 */
287 reg |= 0x3;
288 __raw_writel(reg, MISC_PCIE_CTRL(port));
289
290 pr_info("PCIe: Port[%d] Enable PCIe LTSSM\n", port);
291 pr_info("PCIe: Port[%d] Check data link layer...", port);
292
293 time = jiffies;
294 while (1) {
295 reg = __raw_readl(MISC_PCIE_PM_DEBUG(port));
296 if (reg & 0x1) {
297 pr_info("Link up.\n");
298 cnspci->linked = 1;
299 break;
300 } else if (time_after(jiffies, time + 50)) {
301 pr_info("Device not found.\n");
302 break;
303 }
304 }
305}
306
307static void __init cns3xxx_pcie_hw_init(struct cns3xxx_pcie *cnspci)
308{
309 int port = cnspci->hw_pci.domain;
310 struct pci_sys_data sd = {
311 .domain = port,
312 };
313 struct pci_bus bus = {
314 .number = 0,
315 .ops = &cns3xxx_pcie_ops,
316 .sysdata = &sd,
317 };
318 u32 io_base = cnspci->res_io.start >> 16;
319 u32 mem_base = cnspci->res_mem.start >> 16;
320 u32 host_base = cnspci->cfg_bases[CNS3XXX_HOST_TYPE].pfn;
321 u32 cfg0_base = cnspci->cfg_bases[CNS3XXX_CFG0_TYPE].pfn;
322 u32 devfn = 0;
323 u8 tmp8;
324 u16 pos;
325 u16 dc;
326
327 host_base = (__pfn_to_phys(host_base) - 1) >> 16;
328 cfg0_base = (__pfn_to_phys(cfg0_base) - 1) >> 16;
329
330 pci_bus_write_config_byte(&bus, devfn, PCI_PRIMARY_BUS, 0);
331 pci_bus_write_config_byte(&bus, devfn, PCI_SECONDARY_BUS, 1);
332 pci_bus_write_config_byte(&bus, devfn, PCI_SUBORDINATE_BUS, 1);
333
334 pci_bus_read_config_byte(&bus, devfn, PCI_PRIMARY_BUS, &tmp8);
335 pci_bus_read_config_byte(&bus, devfn, PCI_SECONDARY_BUS, &tmp8);
336 pci_bus_read_config_byte(&bus, devfn, PCI_SUBORDINATE_BUS, &tmp8);
337
338 pci_bus_write_config_word(&bus, devfn, PCI_MEMORY_BASE, mem_base);
339 pci_bus_write_config_word(&bus, devfn, PCI_MEMORY_LIMIT, host_base);
340 pci_bus_write_config_word(&bus, devfn, PCI_IO_BASE_UPPER16, io_base);
341 pci_bus_write_config_word(&bus, devfn, PCI_IO_LIMIT_UPPER16, cfg0_base);
342
343 if (!cnspci->linked)
344 return;
345
346 /* Set Device Max_Read_Request_Size to 128 byte */
347 devfn = PCI_DEVFN(1, 0);
348 pos = pci_bus_find_capability(&bus, devfn, PCI_CAP_ID_EXP);
349 pci_bus_read_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, &dc);
350 dc &= ~(0x3 << 12); /* Clear Device Control Register [14:12] */
351 pci_bus_write_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, dc);
352 pci_bus_read_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, &dc);
353 if (!(dc & (0x3 << 12)))
354 pr_info("PCIe: Set Device Max_Read_Request_Size to 128 byte\n");
355
356 /* Disable PCIe0 Interrupt Mask INTA to INTD */
357 __raw_writel(~0x3FFF, MISC_PCIE_INT_MASK(port));
358}
359
360static int cns3xxx_pcie_abort_handler(unsigned long addr, unsigned int fsr,
361 struct pt_regs *regs)
362{
363 if (fsr & (1 << 10))
364 regs->ARM_pc += 4;
365 return 0;
366}
367
368static int __init cns3xxx_pcie_init(void)
369{
370 int i;
371
372 hook_fault_code(16 + 6, cns3xxx_pcie_abort_handler, SIGBUS,
373 "imprecise external abort");
374
375 for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) {
376 iotable_init(cns3xxx_pcie[i].cfg_bases,
377 ARRAY_SIZE(cns3xxx_pcie[i].cfg_bases));
378 cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_PCIE(i));
379 cns3xxx_pwr_soft_rst(0x1 << PM_SOFT_RST_REG_OFFST_PCIE(i));
380 cns3xxx_pcie_check_link(&cns3xxx_pcie[i]);
381 cns3xxx_pcie_hw_init(&cns3xxx_pcie[i]);
382 pci_common_init(&cns3xxx_pcie[i].hw_pci);
383 }
384
385 pci_assign_unassigned_resources();
386
387 return 0;
388}
389device_initcall(cns3xxx_pcie_init);
diff --git a/arch/arm/mach-cns3xxx/pm.c b/arch/arm/mach-cns3xxx/pm.c
index 725e1a4fc231..38e44706feab 100644
--- a/arch/arm/mach-cns3xxx/pm.c
+++ b/arch/arm/mach-cns3xxx/pm.c
@@ -6,18 +6,25 @@
6 * published by the Free Software Foundation. 6 * published by the Free Software Foundation.
7 */ 7 */
8 8
9#include <linux/io.h>
9#include <linux/delay.h> 10#include <linux/delay.h>
10#include <mach/system.h> 11#include <mach/system.h>
11#include <mach/cns3xxx.h> 12#include <mach/cns3xxx.h>
12 13
13void cns3xxx_pwr_clk_en(unsigned int block) 14void cns3xxx_pwr_clk_en(unsigned int block)
14{ 15{
15 PM_CLK_GATE_REG |= (block & PM_CLK_GATE_REG_MASK); 16 u32 reg = __raw_readl(PM_CLK_GATE_REG);
17
18 reg |= (block & PM_CLK_GATE_REG_MASK);
19 __raw_writel(reg, PM_CLK_GATE_REG);
16} 20}
17 21
18void cns3xxx_pwr_power_up(unsigned int block) 22void cns3xxx_pwr_power_up(unsigned int block)
19{ 23{
20 PM_PLL_HM_PD_CTRL_REG &= ~(block & CNS3XXX_PWR_PLL_ALL); 24 u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG);
25
26 reg &= ~(block & CNS3XXX_PWR_PLL_ALL);
27 __raw_writel(reg, PM_PLL_HM_PD_CTRL_REG);
21 28
22 /* Wait for 300us for the PLL output clock locked. */ 29 /* Wait for 300us for the PLL output clock locked. */
23 udelay(300); 30 udelay(300);
@@ -25,22 +32,29 @@ void cns3xxx_pwr_power_up(unsigned int block)
25 32
26void cns3xxx_pwr_power_down(unsigned int block) 33void cns3xxx_pwr_power_down(unsigned int block)
27{ 34{
35 u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG);
36
28 /* write '1' to power down */ 37 /* write '1' to power down */
29 PM_PLL_HM_PD_CTRL_REG |= (block & CNS3XXX_PWR_PLL_ALL); 38 reg |= (block & CNS3XXX_PWR_PLL_ALL);
39 __raw_writel(reg, PM_PLL_HM_PD_CTRL_REG);
30}; 40};
31 41
32static void cns3xxx_pwr_soft_rst_force(unsigned int block) 42static void cns3xxx_pwr_soft_rst_force(unsigned int block)
33{ 43{
44 u32 reg = __raw_readl(PM_SOFT_RST_REG);
45
34 /* 46 /*
35 * bit 0, 28, 29 => program low to reset, 47 * bit 0, 28, 29 => program low to reset,
36 * the other else program low and then high 48 * the other else program low and then high
37 */ 49 */
38 if (block & 0x30000001) { 50 if (block & 0x30000001) {
39 PM_SOFT_RST_REG &= ~(block & PM_SOFT_RST_REG_MASK); 51 reg &= ~(block & PM_SOFT_RST_REG_MASK);
40 } else { 52 } else {
41 PM_SOFT_RST_REG &= ~(block & PM_SOFT_RST_REG_MASK); 53 reg &= ~(block & PM_SOFT_RST_REG_MASK);
42 PM_SOFT_RST_REG |= (block & PM_SOFT_RST_REG_MASK); 54 reg |= (block & PM_SOFT_RST_REG_MASK);
43 } 55 }
56
57 __raw_writel(reg, PM_SOFT_RST_REG);
44} 58}
45 59
46void cns3xxx_pwr_soft_rst(unsigned int block) 60void cns3xxx_pwr_soft_rst(unsigned int block)
@@ -73,12 +87,13 @@ void arch_reset(char mode, const char *cmd)
73 */ 87 */
74int cns3xxx_cpu_clock(void) 88int cns3xxx_cpu_clock(void)
75{ 89{
90 u32 reg = __raw_readl(PM_CLK_CTRL_REG);
76 int cpu; 91 int cpu;
77 int cpu_sel; 92 int cpu_sel;
78 int div_sel; 93 int div_sel;
79 94
80 cpu_sel = (PM_CLK_CTRL_REG >> PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL) & 0xf; 95 cpu_sel = (reg >> PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL) & 0xf;
81 div_sel = (PM_CLK_CTRL_REG >> PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV) & 0x3; 96 div_sel = (reg >> PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV) & 0x3;
82 97
83 cpu = (300 + ((cpu_sel / 3) * 100) + ((cpu_sel % 3) * 33)) >> div_sel; 98 cpu = (300 + ((cpu_sel / 3) * 100) + ((cpu_sel % 3) * 33)) >> div_sel;
84 99
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index 5da2cf402c81..f7a12586a1f5 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -752,6 +752,67 @@ void __init dove_xor1_init(void)
752 platform_device_register(&dove_xor11_channel); 752 platform_device_register(&dove_xor11_channel);
753} 753}
754 754
755/*****************************************************************************
756 * SDIO
757 ****************************************************************************/
758static u64 sdio_dmamask = DMA_BIT_MASK(32);
759
760static struct resource dove_sdio0_resources[] = {
761 {
762 .start = DOVE_SDIO0_PHYS_BASE,
763 .end = DOVE_SDIO0_PHYS_BASE + 0xff,
764 .flags = IORESOURCE_MEM,
765 }, {
766 .start = IRQ_DOVE_SDIO0,
767 .end = IRQ_DOVE_SDIO0,
768 .flags = IORESOURCE_IRQ,
769 },
770};
771
772static struct platform_device dove_sdio0 = {
773 .name = "sdhci-mv",
774 .id = 0,
775 .dev = {
776 .dma_mask = &sdio_dmamask,
777 .coherent_dma_mask = DMA_BIT_MASK(32),
778 },
779 .resource = dove_sdio0_resources,
780 .num_resources = ARRAY_SIZE(dove_sdio0_resources),
781};
782
783void __init dove_sdio0_init(void)
784{
785 platform_device_register(&dove_sdio0);
786}
787
788static struct resource dove_sdio1_resources[] = {
789 {
790 .start = DOVE_SDIO1_PHYS_BASE,
791 .end = DOVE_SDIO1_PHYS_BASE + 0xff,
792 .flags = IORESOURCE_MEM,
793 }, {
794 .start = IRQ_DOVE_SDIO1,
795 .end = IRQ_DOVE_SDIO1,
796 .flags = IORESOURCE_IRQ,
797 },
798};
799
800static struct platform_device dove_sdio1 = {
801 .name = "sdhci-mv",
802 .id = 1,
803 .dev = {
804 .dma_mask = &sdio_dmamask,
805 .coherent_dma_mask = DMA_BIT_MASK(32),
806 },
807 .resource = dove_sdio1_resources,
808 .num_resources = ARRAY_SIZE(dove_sdio1_resources),
809};
810
811void __init dove_sdio1_init(void)
812{
813 platform_device_register(&dove_sdio1);
814}
815
755void __init dove_init(void) 816void __init dove_init(void)
756{ 817{
757 int tclk; 818 int tclk;
diff --git a/arch/arm/mach-dove/common.h b/arch/arm/mach-dove/common.h
index b29e8937de4f..a51517c3fe76 100644
--- a/arch/arm/mach-dove/common.h
+++ b/arch/arm/mach-dove/common.h
@@ -36,5 +36,7 @@ void dove_uart3_init(void);
36void dove_spi0_init(void); 36void dove_spi0_init(void);
37void dove_spi1_init(void); 37void dove_spi1_init(void);
38void dove_i2c_init(void); 38void dove_i2c_init(void);
39void dove_sdio0_init(void);
40void dove_sdio1_init(void);
39 41
40#endif 42#endif
diff --git a/arch/arm/mach-dove/dove-db-setup.c b/arch/arm/mach-dove/dove-db-setup.c
index f2971b745224..bef70460fbc6 100644
--- a/arch/arm/mach-dove/dove-db-setup.c
+++ b/arch/arm/mach-dove/dove-db-setup.c
@@ -82,6 +82,8 @@ static void __init dove_db_init(void)
82 dove_ehci0_init(); 82 dove_ehci0_init();
83 dove_ehci1_init(); 83 dove_ehci1_init();
84 dove_sata_init(&dove_db_sata_data); 84 dove_sata_init(&dove_db_sata_data);
85 dove_sdio0_init();
86 dove_sdio1_init();
85 dove_spi0_init(); 87 dove_spi0_init();
86 dove_spi1_init(); 88 dove_spi1_init();
87 dove_uart0_init(); 89 dove_uart0_init();
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index 29b2163b1fe3..cc25501b57fa 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -75,6 +75,13 @@ config MACH_OPENRD_CLIENT
75 Say 'Y' here if you want your kernel to support the 75 Say 'Y' here if you want your kernel to support the
76 Marvell OpenRD Client Board. 76 Marvell OpenRD Client Board.
77 77
78config MACH_OPENRD_ULTIMATE
79 bool "Marvell OpenRD Ultimate Board"
80 select MACH_OPENRD
81 help
82 Say 'Y' here if you want your kernel to support the
83 Marvell OpenRD Ultimate Board.
84
78config MACH_NETSPACE_V2 85config MACH_NETSPACE_V2
79 bool "LaCie Network Space v2 NAS Board" 86 bool "LaCie Network Space v2 NAS Board"
80 help 87 help
@@ -87,6 +94,12 @@ config MACH_INETSPACE_V2
87 Say 'Y' here if you want your kernel to support the 94 Say 'Y' here if you want your kernel to support the
88 LaCie Internet Space v2 NAS. 95 LaCie Internet Space v2 NAS.
89 96
97config MACH_NETSPACE_MAX_V2
98 bool "LaCie Network Space Max v2 NAS Board"
99 help
100 Say 'Y' here if you want your kernel to support the
101 LaCie Network Space Max v2 NAS.
102
90config MACH_NET2BIG_V2 103config MACH_NET2BIG_V2
91 bool "LaCie 2Big Network v2 NAS Board" 104 bool "LaCie 2Big Network v2 NAS Board"
92 help 105 help
@@ -99,6 +112,12 @@ config MACH_NET5BIG_V2
99 Say 'Y' here if you want your kernel to support the 112 Say 'Y' here if you want your kernel to support the
100 LaCie 5Big Network v2 NAS. 113 LaCie 5Big Network v2 NAS.
101 114
115config MACH_T5325
116 bool "HP t5325 Thin Client"
117 help
118 Say 'Y' here if you want your kernel to support the
119 HP t5325 Thin Client.
120
102endmenu 121endmenu
103 122
104endif 123endif
diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
index c0cd5d362002..295d7baa6ae1 100644
--- a/arch/arm/mach-kirkwood/Makefile
+++ b/arch/arm/mach-kirkwood/Makefile
@@ -12,7 +12,9 @@ obj-$(CONFIG_MACH_TS41X) += ts41x-setup.o tsx1x-common.o
12obj-$(CONFIG_MACH_OPENRD) += openrd-setup.o 12obj-$(CONFIG_MACH_OPENRD) += openrd-setup.o
13obj-$(CONFIG_MACH_NETSPACE_V2) += netspace_v2-setup.o 13obj-$(CONFIG_MACH_NETSPACE_V2) += netspace_v2-setup.o
14obj-$(CONFIG_MACH_INETSPACE_V2) += netspace_v2-setup.o 14obj-$(CONFIG_MACH_INETSPACE_V2) += netspace_v2-setup.o
15obj-$(CONFIG_MACH_NETSPACE_MAX_V2) += netspace_v2-setup.o
15obj-$(CONFIG_MACH_NET2BIG_V2) += netxbig_v2-setup.o 16obj-$(CONFIG_MACH_NET2BIG_V2) += netxbig_v2-setup.o
16obj-$(CONFIG_MACH_NET5BIG_V2) += netxbig_v2-setup.o 17obj-$(CONFIG_MACH_NET5BIG_V2) += netxbig_v2-setup.o
18obj-$(CONFIG_MACH_T5325) += t5325-setup.o
17 19
18obj-$(CONFIG_CPU_IDLE) += cpuidle.o 20obj-$(CONFIG_CPU_IDLE) += cpuidle.o
diff --git a/arch/arm/mach-kirkwood/addr-map.c b/arch/arm/mach-kirkwood/addr-map.c
index 2e69168fc699..8d03bcef5182 100644
--- a/arch/arm/mach-kirkwood/addr-map.c
+++ b/arch/arm/mach-kirkwood/addr-map.c
@@ -31,6 +31,8 @@
31#define ATTR_DEV_CS0 0x3e 31#define ATTR_DEV_CS0 0x3e
32#define ATTR_PCIE_IO 0xe0 32#define ATTR_PCIE_IO 0xe0
33#define ATTR_PCIE_MEM 0xe8 33#define ATTR_PCIE_MEM 0xe8
34#define ATTR_PCIE1_IO 0xd0
35#define ATTR_PCIE1_MEM 0xd8
34#define ATTR_SRAM 0x01 36#define ATTR_SRAM 0x01
35 37
36/* 38/*
@@ -106,17 +108,21 @@ void __init kirkwood_setup_cpu_mbus(void)
106 TARGET_PCIE, ATTR_PCIE_IO, KIRKWOOD_PCIE_IO_BUS_BASE); 108 TARGET_PCIE, ATTR_PCIE_IO, KIRKWOOD_PCIE_IO_BUS_BASE);
107 setup_cpu_win(1, KIRKWOOD_PCIE_MEM_PHYS_BASE, KIRKWOOD_PCIE_MEM_SIZE, 109 setup_cpu_win(1, KIRKWOOD_PCIE_MEM_PHYS_BASE, KIRKWOOD_PCIE_MEM_SIZE,
108 TARGET_PCIE, ATTR_PCIE_MEM, KIRKWOOD_PCIE_MEM_BUS_BASE); 110 TARGET_PCIE, ATTR_PCIE_MEM, KIRKWOOD_PCIE_MEM_BUS_BASE);
111 setup_cpu_win(2, KIRKWOOD_PCIE1_IO_PHYS_BASE, KIRKWOOD_PCIE1_IO_SIZE,
112 TARGET_PCIE, ATTR_PCIE1_IO, KIRKWOOD_PCIE1_IO_BUS_BASE);
113 setup_cpu_win(3, KIRKWOOD_PCIE1_MEM_PHYS_BASE, KIRKWOOD_PCIE1_MEM_SIZE,
114 TARGET_PCIE, ATTR_PCIE1_MEM, KIRKWOOD_PCIE1_MEM_BUS_BASE);
109 115
110 /* 116 /*
111 * Setup window for NAND controller. 117 * Setup window for NAND controller.
112 */ 118 */
113 setup_cpu_win(2, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE, 119 setup_cpu_win(4, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE,
114 TARGET_DEV_BUS, ATTR_DEV_NAND, -1); 120 TARGET_DEV_BUS, ATTR_DEV_NAND, -1);
115 121
116 /* 122 /*
117 * Setup window for SRAM. 123 * Setup window for SRAM.
118 */ 124 */
119 setup_cpu_win(3, KIRKWOOD_SRAM_PHYS_BASE, KIRKWOOD_SRAM_SIZE, 125 setup_cpu_win(5, KIRKWOOD_SRAM_PHYS_BASE, KIRKWOOD_SRAM_SIZE,
120 TARGET_SRAM, ATTR_SRAM, -1); 126 TARGET_SRAM, ATTR_SRAM, -1);
121 127
122 /* 128 /*
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index 6072eaa5e66a..9dd67c7b4459 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -44,6 +44,11 @@ static struct map_desc kirkwood_io_desc[] __initdata = {
44 .length = KIRKWOOD_PCIE_IO_SIZE, 44 .length = KIRKWOOD_PCIE_IO_SIZE,
45 .type = MT_DEVICE, 45 .type = MT_DEVICE,
46 }, { 46 }, {
47 .virtual = KIRKWOOD_PCIE1_IO_VIRT_BASE,
48 .pfn = __phys_to_pfn(KIRKWOOD_PCIE1_IO_PHYS_BASE),
49 .length = KIRKWOOD_PCIE1_IO_SIZE,
50 .type = MT_DEVICE,
51 }, {
47 .virtual = KIRKWOOD_REGS_VIRT_BASE, 52 .virtual = KIRKWOOD_REGS_VIRT_BASE,
48 .pfn = __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE), 53 .pfn = __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE),
49 .length = KIRKWOOD_REGS_SIZE, 54 .length = KIRKWOOD_REGS_SIZE,
@@ -402,7 +407,7 @@ void __init kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data)
402 u32 dev, rev; 407 u32 dev, rev;
403 408
404 kirkwood_pcie_id(&dev, &rev); 409 kirkwood_pcie_id(&dev, &rev);
405 if (rev == 0) /* catch all Kirkwood Z0's */ 410 if (rev == 0 && dev != MV88F6282_DEV_ID) /* catch all Kirkwood Z0's */
406 mvsdio_data->clock = 100000000; 411 mvsdio_data->clock = 100000000;
407 else 412 else
408 mvsdio_data->clock = 200000000; 413 mvsdio_data->clock = 200000000;
@@ -847,8 +852,10 @@ int __init kirkwood_find_tclk(void)
847 u32 dev, rev; 852 u32 dev, rev;
848 853
849 kirkwood_pcie_id(&dev, &rev); 854 kirkwood_pcie_id(&dev, &rev);
850 if (dev == MV88F6281_DEV_ID && (rev == MV88F6281_REV_A0 || 855
851 rev == MV88F6281_REV_A1)) 856 if ((dev == MV88F6281_DEV_ID && (rev == MV88F6281_REV_A0 ||
857 rev == MV88F6281_REV_A1)) ||
858 (dev == MV88F6282_DEV_ID))
852 return 200000000; 859 return 200000000;
853 860
854 return 166666667; 861 return 166666667;
@@ -891,13 +898,22 @@ static char * __init kirkwood_id(void)
891 return "MV88F6192-Z0"; 898 return "MV88F6192-Z0";
892 else if (rev == MV88F6192_REV_A0) 899 else if (rev == MV88F6192_REV_A0)
893 return "MV88F6192-A0"; 900 return "MV88F6192-A0";
901 else if (rev == MV88F6192_REV_A1)
902 return "MV88F6192-A1";
894 else 903 else
895 return "MV88F6192-Rev-Unsupported"; 904 return "MV88F6192-Rev-Unsupported";
896 } else if (dev == MV88F6180_DEV_ID) { 905 } else if (dev == MV88F6180_DEV_ID) {
897 if (rev == MV88F6180_REV_A0) 906 if (rev == MV88F6180_REV_A0)
898 return "MV88F6180-Rev-A0"; 907 return "MV88F6180-Rev-A0";
908 else if (rev == MV88F6180_REV_A1)
909 return "MV88F6180-Rev-A1";
899 else 910 else
900 return "MV88F6180-Rev-Unsupported"; 911 return "MV88F6180-Rev-Unsupported";
912 } else if (dev == MV88F6282_DEV_ID) {
913 if (rev == MV88F6282_REV_A0)
914 return "MV88F6282-Rev-A0";
915 else
916 return "MV88F6282-Rev-Unsupported";
901 } else { 917 } else {
902 return "Device-Unknown"; 918 return "Device-Unknown";
903 } 919 }
@@ -949,12 +965,14 @@ void __init kirkwood_init(void)
949static int __init kirkwood_clock_gate(void) 965static int __init kirkwood_clock_gate(void)
950{ 966{
951 unsigned int curr = readl(CLOCK_GATING_CTRL); 967 unsigned int curr = readl(CLOCK_GATING_CTRL);
968 u32 dev, rev;
952 969
970 kirkwood_pcie_id(&dev, &rev);
953 printk(KERN_DEBUG "Gating clock of unused units\n"); 971 printk(KERN_DEBUG "Gating clock of unused units\n");
954 printk(KERN_DEBUG "before: 0x%08x\n", curr); 972 printk(KERN_DEBUG "before: 0x%08x\n", curr);
955 973
956 /* Make sure those units are accessible */ 974 /* Make sure those units are accessible */
957 writel(curr | CGC_SATA0 | CGC_SATA1 | CGC_PEX0, CLOCK_GATING_CTRL); 975 writel(curr | CGC_SATA0 | CGC_SATA1 | CGC_PEX0 | CGC_PEX1, CLOCK_GATING_CTRL);
958 976
959 /* For SATA: first shutdown the phy */ 977 /* For SATA: first shutdown the phy */
960 if (!(kirkwood_clk_ctrl & CGC_SATA0)) { 978 if (!(kirkwood_clk_ctrl & CGC_SATA0)) {
@@ -979,6 +997,18 @@ static int __init kirkwood_clock_gate(void)
979 writel(readl(PCIE_LINK_CTRL) & ~0x10, PCIE_LINK_CTRL); 997 writel(readl(PCIE_LINK_CTRL) & ~0x10, PCIE_LINK_CTRL);
980 } 998 }
981 999
1000 /* For PCIe 1: first shutdown the phy */
1001 if (dev == MV88F6282_DEV_ID) {
1002 if (!(kirkwood_clk_ctrl & CGC_PEX1)) {
1003 writel(readl(PCIE1_LINK_CTRL) | 0x10, PCIE1_LINK_CTRL);
1004 while (1)
1005 if (readl(PCIE1_STATUS) & 0x1)
1006 break;
1007 writel(readl(PCIE1_LINK_CTRL) & ~0x10, PCIE1_LINK_CTRL);
1008 }
1009 } else /* keep this bit set for devices that don't have PCIe1 */
1010 kirkwood_clk_ctrl |= CGC_PEX1;
1011
982 /* Now gate clock the required units */ 1012 /* Now gate clock the required units */
983 writel(kirkwood_clk_ctrl, CLOCK_GATING_CTRL); 1013 writel(kirkwood_clk_ctrl, CLOCK_GATING_CTRL);
984 printk(KERN_DEBUG " after: 0x%08x\n", readl(CLOCK_GATING_CTRL)); 1014 printk(KERN_DEBUG " after: 0x%08x\n", readl(CLOCK_GATING_CTRL));
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index 05e8a8a5692e..5b2c1c18d641 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -18,6 +18,9 @@ struct mvsdio_platform_data;
18struct mtd_partition; 18struct mtd_partition;
19struct mtd_info; 19struct mtd_info;
20 20
21#define KW_PCIE0 (1 << 0)
22#define KW_PCIE1 (1 << 1)
23
21/* 24/*
22 * Basic Kirkwood init functions used early by machine-setup. 25 * Basic Kirkwood init functions used early by machine-setup.
23 */ 26 */
@@ -34,7 +37,7 @@ void kirkwood_ehci_init(void);
34void kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data); 37void kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data);
35void kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data); 38void kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data);
36void kirkwood_ge00_switch_init(struct dsa_platform_data *d, int irq); 39void kirkwood_ge00_switch_init(struct dsa_platform_data *d, int irq);
37void kirkwood_pcie_init(void); 40void kirkwood_pcie_init(unsigned int portmask);
38void kirkwood_sata_init(struct mv_sata_platform_data *sata_data); 41void kirkwood_sata_init(struct mv_sata_platform_data *sata_data);
39void kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data); 42void kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data);
40void kirkwood_spi_init(void); 43void kirkwood_spi_init(void);
diff --git a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
index 39bdf4bcace9..16f6691e7c68 100644
--- a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
+++ b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
@@ -51,6 +51,14 @@ static struct mvsdio_platform_data db88f6281_mvsdio_data = {
51}; 51};
52 52
53static unsigned int db88f6281_mpp_config[] __initdata = { 53static unsigned int db88f6281_mpp_config[] __initdata = {
54 MPP0_NF_IO2,
55 MPP1_NF_IO3,
56 MPP2_NF_IO4,
57 MPP3_NF_IO5,
58 MPP4_NF_IO6,
59 MPP5_NF_IO7,
60 MPP18_NF_IO0,
61 MPP19_NF_IO1,
54 MPP37_GPIO, 62 MPP37_GPIO,
55 MPP38_GPIO, 63 MPP38_GPIO,
56 0 64 0
@@ -74,9 +82,15 @@ static void __init db88f6281_init(void)
74 82
75static int __init db88f6281_pci_init(void) 83static int __init db88f6281_pci_init(void)
76{ 84{
77 if (machine_is_db88f6281_bp()) 85 if (machine_is_db88f6281_bp()) {
78 kirkwood_pcie_init(); 86 u32 dev, rev;
79 87
88 kirkwood_pcie_id(&dev, &rev);
89 if (dev == MV88F6282_DEV_ID)
90 kirkwood_pcie_init(KW_PCIE1 | KW_PCIE0);
91 else
92 kirkwood_pcie_init(KW_PCIE0);
93 }
80 return 0; 94 return 0;
81} 95}
82subsys_initcall(db88f6281_pci_init); 96subsys_initcall(db88f6281_pci_init);
diff --git a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
index 418f5017c50e..aff0e1327e38 100644
--- a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
+++ b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
@@ -59,8 +59,9 @@
59#define CGC_SATA1 (1 << 15) 59#define CGC_SATA1 (1 << 15)
60#define CGC_XOR1 (1 << 16) 60#define CGC_XOR1 (1 << 16)
61#define CGC_CRYPTO (1 << 17) 61#define CGC_CRYPTO (1 << 17)
62#define CGC_PEX1 (1 << 18)
62#define CGC_GE1 (1 << 19) 63#define CGC_GE1 (1 << 19)
63#define CGC_TDM (1 << 20) 64#define CGC_TDM (1 << 20)
64#define CGC_RESERVED ((1 << 18) | (0x6 << 21)) 65#define CGC_RESERVED (0x6 << 21)
65 66
66#endif 67#endif
diff --git a/arch/arm/mach-kirkwood/include/mach/irqs.h b/arch/arm/mach-kirkwood/include/mach/irqs.h
index f00a0a45a67e..9da2eb59180b 100644
--- a/arch/arm/mach-kirkwood/include/mach/irqs.h
+++ b/arch/arm/mach-kirkwood/include/mach/irqs.h
@@ -23,6 +23,7 @@
23#define IRQ_KIRKWOOD_XOR_10 7 23#define IRQ_KIRKWOOD_XOR_10 7
24#define IRQ_KIRKWOOD_XOR_11 8 24#define IRQ_KIRKWOOD_XOR_11 8
25#define IRQ_KIRKWOOD_PCIE 9 25#define IRQ_KIRKWOOD_PCIE 9
26#define IRQ_KIRKWOOD_PCIE1 10
26#define IRQ_KIRKWOOD_GE00_SUM 11 27#define IRQ_KIRKWOOD_GE00_SUM 11
27#define IRQ_KIRKWOOD_GE01_SUM 15 28#define IRQ_KIRKWOOD_GE01_SUM 15
28#define IRQ_KIRKWOOD_USB 19 29#define IRQ_KIRKWOOD_USB 19
diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
index a15cf0ee22bd..d141af4c2744 100644
--- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h
+++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
@@ -16,36 +16,48 @@
16 * Marvell Kirkwood address maps. 16 * Marvell Kirkwood address maps.
17 * 17 *
18 * phys 18 * phys
19 * e0000000 PCIe Memory space 19 * e0000000 PCIe #0 Memory space
20 * e8000000 PCIe #1 Memory space
20 * f1000000 on-chip peripheral registers 21 * f1000000 on-chip peripheral registers
21 * f2000000 PCIe I/O space 22 * f2000000 PCIe #0 I/O space
22 * f3000000 NAND controller address window 23 * f3000000 PCIe #1 I/O space
23 * f4000000 Security Accelerator SRAM 24 * f4000000 NAND controller address window
25 * f5000000 Security Accelerator SRAM
24 * 26 *
25 * virt phys size 27 * virt phys size
26 * fee00000 f1000000 1M on-chip peripheral registers 28 * fed00000 f1000000 1M on-chip peripheral registers
27 * fef00000 f2000000 1M PCIe I/O space 29 * fee00000 f2000000 1M PCIe #0 I/O space
30 * fef00000 f3000000 1M PCIe #1 I/O space
28 */ 31 */
29 32
30#define KIRKWOOD_SRAM_PHYS_BASE 0xf4000000 33#define KIRKWOOD_SRAM_PHYS_BASE 0xf5000000
31#define KIRKWOOD_SRAM_SIZE SZ_2K 34#define KIRKWOOD_SRAM_SIZE SZ_2K
32 35
33#define KIRKWOOD_NAND_MEM_PHYS_BASE 0xf3000000 36#define KIRKWOOD_NAND_MEM_PHYS_BASE 0xf4000000
34#define KIRKWOOD_NAND_MEM_SIZE SZ_1K 37#define KIRKWOOD_NAND_MEM_SIZE SZ_1K
35 38
39#define KIRKWOOD_PCIE1_IO_PHYS_BASE 0xf3000000
40#define KIRKWOOD_PCIE1_IO_VIRT_BASE 0xfef00000
41#define KIRKWOOD_PCIE1_IO_BUS_BASE 0x00000000
42#define KIRKWOOD_PCIE1_IO_SIZE SZ_1M
43
36#define KIRKWOOD_PCIE_IO_PHYS_BASE 0xf2000000 44#define KIRKWOOD_PCIE_IO_PHYS_BASE 0xf2000000
37#define KIRKWOOD_PCIE_IO_VIRT_BASE 0xfef00000 45#define KIRKWOOD_PCIE_IO_VIRT_BASE 0xfee00000
38#define KIRKWOOD_PCIE_IO_BUS_BASE 0x00000000 46#define KIRKWOOD_PCIE_IO_BUS_BASE 0x00000000
39#define KIRKWOOD_PCIE_IO_SIZE SZ_1M 47#define KIRKWOOD_PCIE_IO_SIZE SZ_1M
40 48
41#define KIRKWOOD_REGS_PHYS_BASE 0xf1000000 49#define KIRKWOOD_REGS_PHYS_BASE 0xf1000000
42#define KIRKWOOD_REGS_VIRT_BASE 0xfee00000 50#define KIRKWOOD_REGS_VIRT_BASE 0xfed00000
43#define KIRKWOOD_REGS_SIZE SZ_1M 51#define KIRKWOOD_REGS_SIZE SZ_1M
44 52
45#define KIRKWOOD_PCIE_MEM_PHYS_BASE 0xe0000000 53#define KIRKWOOD_PCIE_MEM_PHYS_BASE 0xe0000000
46#define KIRKWOOD_PCIE_MEM_BUS_BASE 0xe0000000 54#define KIRKWOOD_PCIE_MEM_BUS_BASE 0xe0000000
47#define KIRKWOOD_PCIE_MEM_SIZE SZ_128M 55#define KIRKWOOD_PCIE_MEM_SIZE SZ_128M
48 56
57#define KIRKWOOD_PCIE1_MEM_PHYS_BASE 0xe8000000
58#define KIRKWOOD_PCIE1_MEM_BUS_BASE 0xe8000000
59#define KIRKWOOD_PCIE1_MEM_SIZE SZ_128M
60
49/* 61/*
50 * Register Map 62 * Register Map
51 */ 63 */
@@ -72,6 +84,9 @@
72#define PCIE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x40000) 84#define PCIE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x40000)
73#define PCIE_LINK_CTRL (PCIE_VIRT_BASE | 0x70) 85#define PCIE_LINK_CTRL (PCIE_VIRT_BASE | 0x70)
74#define PCIE_STATUS (PCIE_VIRT_BASE | 0x1a04) 86#define PCIE_STATUS (PCIE_VIRT_BASE | 0x1a04)
87#define PCIE1_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x44000)
88#define PCIE1_LINK_CTRL (PCIE1_VIRT_BASE | 0x70)
89#define PCIE1_STATUS (PCIE1_VIRT_BASE | 0x1a04)
75 90
76#define USB_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x50000) 91#define USB_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x50000)
77 92
@@ -107,8 +122,12 @@
107#define MV88F6192_DEV_ID 0x6192 122#define MV88F6192_DEV_ID 0x6192
108#define MV88F6192_REV_Z0 0 123#define MV88F6192_REV_Z0 0
109#define MV88F6192_REV_A0 2 124#define MV88F6192_REV_A0 2
125#define MV88F6192_REV_A1 3
110 126
111#define MV88F6180_DEV_ID 0x6180 127#define MV88F6180_DEV_ID 0x6180
112#define MV88F6180_REV_A0 2 128#define MV88F6180_REV_A0 2
129#define MV88F6180_REV_A1 3
113 130
131#define MV88F6282_DEV_ID 0x6282
132#define MV88F6282_REV_A0 0
114#endif 133#endif
diff --git a/arch/arm/mach-kirkwood/include/mach/leds-ns2.h b/arch/arm/mach-kirkwood/include/mach/leds-ns2.h
new file mode 100644
index 000000000000..e21272e5f668
--- /dev/null
+++ b/arch/arm/mach-kirkwood/include/mach/leds-ns2.h
@@ -0,0 +1,26 @@
1/*
2 * arch/arm/mach-kirkwood/include/mach/leds-ns2.h
3 *
4 * Platform data structure for Network Space v2 LED driver
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#ifndef __MACH_LEDS_NS2_H
12#define __MACH_LEDS_NS2_H
13
14struct ns2_led {
15 const char *name;
16 const char *default_trigger;
17 unsigned cmd;
18 unsigned slow;
19};
20
21struct ns2_led_platform_data {
22 int num_leds;
23 struct ns2_led *leds;
24};
25
26#endif /* __MACH_LEDS_NS2_H */
diff --git a/arch/arm/mach-kirkwood/mpp.c b/arch/arm/mach-kirkwood/mpp.c
index a5900f64e38c..065187d177c6 100644
--- a/arch/arm/mach-kirkwood/mpp.c
+++ b/arch/arm/mach-kirkwood/mpp.c
@@ -23,7 +23,8 @@ static unsigned int __init kirkwood_variant(void)
23 23
24 kirkwood_pcie_id(&dev, &rev); 24 kirkwood_pcie_id(&dev, &rev);
25 25
26 if (dev == MV88F6281_DEV_ID && rev >= MV88F6281_REV_A0) 26 if ((dev == MV88F6281_DEV_ID && rev >= MV88F6281_REV_A0) ||
27 (dev == MV88F6282_DEV_ID))
27 return MPP_F6281_MASK; 28 return MPP_F6281_MASK;
28 if (dev == MV88F6192_DEV_ID && rev >= MV88F6192_REV_A0) 29 if (dev == MV88F6192_DEV_ID && rev >= MV88F6192_REV_A0)
29 return MPP_F6192_MASK; 30 return MPP_F6192_MASK;
diff --git a/arch/arm/mach-kirkwood/mpp.h b/arch/arm/mach-kirkwood/mpp.h
index bc74278ed311..9b0a94d85c3e 100644
--- a/arch/arm/mach-kirkwood/mpp.h
+++ b/arch/arm/mach-kirkwood/mpp.h
@@ -11,7 +11,7 @@
11#ifndef __KIRKWOOD_MPP_H 11#ifndef __KIRKWOOD_MPP_H
12#define __KIRKWOOD_MPP_H 12#define __KIRKWOOD_MPP_H
13 13
14#define MPP(_num, _sel, _in, _out, _F6180, _F6190, _F6192, _F6281) ( \ 14#define MPP(_num, _sel, _in, _out, _F6180, _F6190, _F6192, _F6281, _F6282) ( \
15 /* MPP number */ ((_num) & 0xff) | \ 15 /* MPP number */ ((_num) & 0xff) | \
16 /* MPP select value */ (((_sel) & 0xf) << 8) | \ 16 /* MPP select value */ (((_sel) & 0xf) << 8) | \
17 /* may be input signal */ ((!!(_in)) << 12) | \ 17 /* may be input signal */ ((!!(_in)) << 12) | \
@@ -19,282 +19,332 @@
19 /* available on F6180 */ ((!!(_F6180)) << 14) | \ 19 /* available on F6180 */ ((!!(_F6180)) << 14) | \
20 /* available on F6190 */ ((!!(_F6190)) << 15) | \ 20 /* available on F6190 */ ((!!(_F6190)) << 15) | \
21 /* available on F6192 */ ((!!(_F6192)) << 16) | \ 21 /* available on F6192 */ ((!!(_F6192)) << 16) | \
22 /* available on F6281 */ ((!!(_F6281)) << 17)) 22 /* available on F6281 */ ((!!(_F6281)) << 17) | \
23 /* available on F6282 */ ((!!(_F6282)) << 18))
23 24
24#define MPP_NUM(x) ((x) & 0xff) 25#define MPP_NUM(x) ((x) & 0xff)
25#define MPP_SEL(x) (((x) >> 8) & 0xf) 26#define MPP_SEL(x) (((x) >> 8) & 0xf)
26 27
27 /* num sel i o 6180 6190 6192 6281 */ 28 /* num sel i o 6180 6190 6192 6281 6282 */
28 29
29#define MPP_INPUT_MASK MPP( 0, 0x0, 1, 0, 0, 0, 0, 0 ) 30#define MPP_INPUT_MASK MPP( 0, 0x0, 1, 0, 0, 0, 0, 0, 0 )
30#define MPP_OUTPUT_MASK MPP( 0, 0x0, 0, 1, 0, 0, 0, 0 ) 31#define MPP_OUTPUT_MASK MPP( 0, 0x0, 0, 1, 0, 0, 0, 0, 0 )
31 32
32#define MPP_F6180_MASK MPP( 0, 0x0, 0, 0, 1, 0, 0, 0 ) 33#define MPP_F6180_MASK MPP( 0, 0x0, 0, 0, 1, 0, 0, 0, 0 )
33#define MPP_F6190_MASK MPP( 0, 0x0, 0, 0, 0, 1, 0, 0 ) 34#define MPP_F6190_MASK MPP( 0, 0x0, 0, 0, 0, 1, 0, 0, 0 )
34#define MPP_F6192_MASK MPP( 0, 0x0, 0, 0, 0, 0, 1, 0 ) 35#define MPP_F6192_MASK MPP( 0, 0x0, 0, 0, 0, 0, 1, 0, 0 )
35#define MPP_F6281_MASK MPP( 0, 0x0, 0, 0, 0, 0, 0, 1 ) 36#define MPP_F6281_MASK MPP( 0, 0x0, 0, 0, 0, 0, 0, 1, 0 )
36 37#define MPP_F6282_MASK MPP( 0, 0x0, 0, 0, 0, 0, 0, 0, 1 )
37#define MPP0_GPIO MPP( 0, 0x0, 1, 1, 1, 1, 1, 1 ) 38
38#define MPP0_NF_IO2 MPP( 0, 0x1, 1, 1, 1, 1, 1, 1 ) 39#define MPP0_GPIO MPP( 0, 0x0, 1, 1, 1, 1, 1, 1, 1 )
39#define MPP0_SPI_SCn MPP( 0, 0x2, 0, 1, 1, 1, 1, 1 ) 40#define MPP0_NF_IO2 MPP( 0, 0x1, 1, 1, 1, 1, 1, 1, 1 )
40 41#define MPP0_SPI_SCn MPP( 0, 0x2, 0, 1, 1, 1, 1, 1, 1 )
41#define MPP1_GPO MPP( 1, 0x0, 0, 1, 1, 1, 1, 1 ) 42
42#define MPP1_NF_IO3 MPP( 1, 0x1, 1, 1, 1, 1, 1, 1 ) 43#define MPP1_GPO MPP( 1, 0x0, 0, 1, 1, 1, 1, 1, 1 )
43#define MPP1_SPI_MOSI MPP( 1, 0x2, 0, 1, 1, 1, 1, 1 ) 44#define MPP1_NF_IO3 MPP( 1, 0x1, 1, 1, 1, 1, 1, 1, 1 )
44 45#define MPP1_SPI_MOSI MPP( 1, 0x2, 0, 1, 1, 1, 1, 1, 1 )
45#define MPP2_GPO MPP( 2, 0x0, 0, 1, 1, 1, 1, 1 ) 46
46#define MPP2_NF_IO4 MPP( 2, 0x1, 1, 1, 1, 1, 1, 1 ) 47#define MPP2_GPO MPP( 2, 0x0, 0, 1, 1, 1, 1, 1, 1 )
47#define MPP2_SPI_SCK MPP( 2, 0x2, 0, 1, 1, 1, 1, 1 ) 48#define MPP2_NF_IO4 MPP( 2, 0x1, 1, 1, 1, 1, 1, 1, 1 )
48 49#define MPP2_SPI_SCK MPP( 2, 0x2, 0, 1, 1, 1, 1, 1, 1 )
49#define MPP3_GPO MPP( 3, 0x0, 0, 1, 1, 1, 1, 1 ) 50
50#define MPP3_NF_IO5 MPP( 3, 0x1, 1, 1, 1, 1, 1, 1 ) 51#define MPP3_GPO MPP( 3, 0x0, 0, 1, 1, 1, 1, 1, 1 )
51#define MPP3_SPI_MISO MPP( 3, 0x2, 1, 0, 1, 1, 1, 1 ) 52#define MPP3_NF_IO5 MPP( 3, 0x1, 1, 1, 1, 1, 1, 1, 1 )
52 53#define MPP3_SPI_MISO MPP( 3, 0x2, 1, 0, 1, 1, 1, 1, 1 )
53#define MPP4_GPIO MPP( 4, 0x0, 1, 1, 1, 1, 1, 1 ) 54
54#define MPP4_NF_IO6 MPP( 4, 0x1, 1, 1, 1, 1, 1, 1 ) 55#define MPP4_GPIO MPP( 4, 0x0, 1, 1, 1, 1, 1, 1, 1 )
55#define MPP4_UART0_RXD MPP( 4, 0x2, 1, 0, 1, 1, 1, 1 ) 56#define MPP4_NF_IO6 MPP( 4, 0x1, 1, 1, 1, 1, 1, 1, 1 )
56#define MPP4_SATA1_ACTn MPP( 4, 0x5, 0, 1, 0, 0, 1, 1 ) 57#define MPP4_UART0_RXD MPP( 4, 0x2, 1, 0, 1, 1, 1, 1, 1 )
57#define MPP4_PTP_CLK MPP( 4, 0xd, 1, 0, 1, 1, 1, 1 ) 58#define MPP4_SATA1_ACTn MPP( 4, 0x5, 0, 1, 0, 0, 1, 1, 1 )
58 59#define MPP4_LCD_VGA_HSYNC MPP( 4, 0xb, 0, 0, 0, 0, 0, 0, 1 )
59#define MPP5_GPO MPP( 5, 0x0, 0, 1, 1, 1, 1, 1 ) 60#define MPP4_PTP_CLK MPP( 4, 0xd, 1, 0, 1, 1, 1, 1, 0 )
60#define MPP5_NF_IO7 MPP( 5, 0x1, 1, 1, 1, 1, 1, 1 ) 61
61#define MPP5_UART0_TXD MPP( 5, 0x2, 0, 1, 1, 1, 1, 1 ) 62#define MPP5_GPO MPP( 5, 0x0, 0, 1, 1, 1, 1, 1, 1 )
62#define MPP5_PTP_TRIG_GEN MPP( 5, 0x4, 0, 1, 1, 1, 1, 1 ) 63#define MPP5_NF_IO7 MPP( 5, 0x1, 1, 1, 1, 1, 1, 1, 1 )
63#define MPP5_SATA0_ACTn MPP( 5, 0x5, 0, 1, 0, 1, 1, 1 ) 64#define MPP5_UART0_TXD MPP( 5, 0x2, 0, 1, 1, 1, 1, 1, 1 )
64 65#define MPP5_PTP_TRIG_GEN MPP( 5, 0x4, 0, 1, 1, 1, 1, 1, 0 )
65#define MPP6_SYSRST_OUTn MPP( 6, 0x1, 0, 1, 1, 1, 1, 1 ) 66#define MPP5_SATA0_ACTn MPP( 5, 0x5, 0, 1, 0, 1, 1, 1, 1 )
66#define MPP6_SPI_MOSI MPP( 6, 0x2, 0, 1, 1, 1, 1, 1 ) 67#define MPP5_LCD_VGA_VSYNC MPP( 5, 0xb, 0, 0, 0, 0, 0, 0, 1 )
67#define MPP6_PTP_TRIG_GEN MPP( 6, 0x3, 0, 1, 1, 1, 1, 1 ) 68
68 69#define MPP6_SYSRST_OUTn MPP( 6, 0x1, 0, 1, 1, 1, 1, 1, 1 )
69#define MPP7_GPO MPP( 7, 0x0, 0, 1, 1, 1, 1, 1 ) 70#define MPP6_SPI_MOSI MPP( 6, 0x2, 0, 1, 1, 1, 1, 1, 1 )
70#define MPP7_PEX_RST_OUTn MPP( 7, 0x1, 0, 1, 1, 1, 1, 1 ) 71#define MPP6_PTP_TRIG_GEN MPP( 6, 0x3, 0, 1, 1, 1, 1, 1, 0 )
71#define MPP7_SPI_SCn MPP( 7, 0x2, 0, 1, 1, 1, 1, 1 ) 72
72#define MPP7_PTP_TRIG_GEN MPP( 7, 0x3, 0, 1, 1, 1, 1, 1 ) 73#define MPP7_GPO MPP( 7, 0x0, 0, 1, 1, 1, 1, 1, 1 )
73 74#define MPP7_PEX_RST_OUTn MPP( 7, 0x1, 0, 1, 1, 1, 1, 1, 0 )
74#define MPP8_GPIO MPP( 8, 0x0, 1, 1, 1, 1, 1, 1 ) 75#define MPP7_SPI_SCn MPP( 7, 0x2, 0, 1, 1, 1, 1, 1, 1 )
75#define MPP8_TW_SDA MPP( 8, 0x1, 1, 1, 1, 1, 1, 1 ) 76#define MPP7_PTP_TRIG_GEN MPP( 7, 0x3, 0, 1, 1, 1, 1, 1, 0 )
76#define MPP8_UART0_RTS MPP( 8, 0x2, 0, 1, 1, 1, 1, 1 ) 77#define MPP7_LCD_PWM MPP( 7, 0xb, 0, 1, 0, 0, 0, 0, 1 )
77#define MPP8_UART1_RTS MPP( 8, 0x3, 0, 1, 1, 1, 1, 1 ) 78
78#define MPP8_MII0_RXERR MPP( 8, 0x4, 1, 0, 0, 1, 1, 1 ) 79#define MPP8_GPIO MPP( 8, 0x0, 1, 1, 1, 1, 1, 1, 1 )
79#define MPP8_SATA1_PRESENTn MPP( 8, 0x5, 0, 1, 0, 0, 1, 1 ) 80#define MPP8_TW0_SDA MPP( 8, 0x1, 1, 1, 1, 1, 1, 1, 1 )
80#define MPP8_PTP_CLK MPP( 8, 0xc, 1, 0, 1, 1, 1, 1 ) 81#define MPP8_UART0_RTS MPP( 8, 0x2, 0, 1, 1, 1, 1, 1, 1 )
81#define MPP8_MII0_COL MPP( 8, 0xd, 1, 0, 1, 1, 1, 1 ) 82#define MPP8_UART1_RTS MPP( 8, 0x3, 0, 1, 1, 1, 1, 1, 1 )
82 83#define MPP8_MII0_RXERR MPP( 8, 0x4, 1, 0, 0, 1, 1, 1, 1 )
83#define MPP9_GPIO MPP( 9, 0x0, 1, 1, 1, 1, 1, 1 ) 84#define MPP8_SATA1_PRESENTn MPP( 8, 0x5, 0, 1, 0, 0, 1, 1, 1 )
84#define MPP9_TW_SCK MPP( 9, 0x1, 1, 1, 1, 1, 1, 1 ) 85#define MPP8_PTP_CLK MPP( 8, 0xc, 1, 0, 1, 1, 1, 1, 0 )
85#define MPP9_UART0_CTS MPP( 9, 0x2, 1, 0, 1, 1, 1, 1 ) 86#define MPP8_MII0_COL MPP( 8, 0xd, 1, 0, 1, 1, 1, 1, 1 )
86#define MPP9_UART1_CTS MPP( 9, 0x3, 1, 0, 1, 1, 1, 1 ) 87
87#define MPP9_SATA0_PRESENTn MPP( 9, 0x5, 0, 1, 0, 1, 1, 1 ) 88#define MPP9_GPIO MPP( 9, 0x0, 1, 1, 1, 1, 1, 1, 1 )
88#define MPP9_PTP_EVENT_REQ MPP( 9, 0xc, 1, 0, 1, 1, 1, 1 ) 89#define MPP9_TW0_SCK MPP( 9, 0x1, 1, 1, 1, 1, 1, 1, 1 )
89#define MPP9_MII0_CRS MPP( 9, 0xd, 1, 0, 1, 1, 1, 1 ) 90#define MPP9_UART0_CTS MPP( 9, 0x2, 1, 0, 1, 1, 1, 1, 1 )
90 91#define MPP9_UART1_CTS MPP( 9, 0x3, 1, 0, 1, 1, 1, 1, 1 )
91#define MPP10_GPO MPP( 10, 0x0, 0, 1, 1, 1, 1, 1 ) 92#define MPP9_SATA0_PRESENTn MPP( 9, 0x5, 0, 1, 0, 1, 1, 1, 1 )
92#define MPP10_SPI_SCK MPP( 10, 0x2, 0, 1, 1, 1, 1, 1 ) 93#define MPP9_PTP_EVENT_REQ MPP( 9, 0xc, 1, 0, 1, 1, 1, 1, 0 )
93#define MPP10_UART0_TXD MPP( 10, 0X3, 0, 1, 1, 1, 1, 1 ) 94#define MPP9_MII0_CRS MPP( 9, 0xd, 1, 0, 1, 1, 1, 1, 1 )
94#define MPP10_SATA1_ACTn MPP( 10, 0x5, 0, 1, 0, 0, 1, 1 ) 95
95#define MPP10_PTP_TRIG_GEN MPP( 10, 0xc, 0, 1, 1, 1, 1, 1 ) 96#define MPP10_GPO MPP( 10, 0x0, 0, 1, 1, 1, 1, 1, 1 )
96 97#define MPP10_SPI_SCK MPP( 10, 0x2, 0, 1, 1, 1, 1, 1, 1 )
97#define MPP11_GPIO MPP( 11, 0x0, 1, 1, 1, 1, 1, 1 ) 98#define MPP10_UART0_TXD MPP( 10, 0X3, 0, 1, 1, 1, 1, 1, 1 )
98#define MPP11_SPI_MISO MPP( 11, 0x2, 1, 0, 1, 1, 1, 1 ) 99#define MPP10_SATA1_ACTn MPP( 10, 0x5, 0, 1, 0, 0, 1, 1, 1 )
99#define MPP11_UART0_RXD MPP( 11, 0x3, 1, 0, 1, 1, 1, 1 ) 100#define MPP10_PTP_TRIG_GEN MPP( 10, 0xc, 0, 1, 1, 1, 1, 1, 0 )
100#define MPP11_PTP_EVENT_REQ MPP( 11, 0x4, 1, 0, 1, 1, 1, 1 ) 101
101#define MPP11_PTP_TRIG_GEN MPP( 11, 0xc, 0, 1, 1, 1, 1, 1 ) 102#define MPP11_GPIO MPP( 11, 0x0, 1, 1, 1, 1, 1, 1, 1 )
102#define MPP11_PTP_CLK MPP( 11, 0xd, 1, 0, 1, 1, 1, 1 ) 103#define MPP11_SPI_MISO MPP( 11, 0x2, 1, 0, 1, 1, 1, 1, 1 )
103#define MPP11_SATA0_ACTn MPP( 11, 0x5, 0, 1, 0, 1, 1, 1 ) 104#define MPP11_UART0_RXD MPP( 11, 0x3, 1, 0, 1, 1, 1, 1, 1 )
104 105#define MPP11_PTP_EVENT_REQ MPP( 11, 0x4, 1, 0, 1, 1, 1, 1, 0 )
105#define MPP12_GPO MPP( 12, 0x0, 0, 1, 1, 1, 1, 1 ) 106#define MPP11_PTP_TRIG_GEN MPP( 11, 0xc, 0, 1, 1, 1, 1, 1, 0 )
106#define MPP12_SD_CLK MPP( 12, 0x1, 0, 1, 1, 1, 1, 1 ) 107#define MPP11_PTP_CLK MPP( 11, 0xd, 1, 0, 1, 1, 1, 1, 0 )
107 108#define MPP11_SATA0_ACTn MPP( 11, 0x5, 0, 1, 0, 1, 1, 1, 1 )
108#define MPP13_GPIO MPP( 13, 0x0, 1, 1, 1, 1, 1, 1 ) 109
109#define MPP13_SD_CMD MPP( 13, 0x1, 1, 1, 1, 1, 1, 1 ) 110#define MPP12_GPO MPP( 12, 0x0, 0, 1, 1, 1, 1, 1, 1 )
110#define MPP13_UART1_TXD MPP( 13, 0x3, 0, 1, 1, 1, 1, 1 ) 111#define MPP12_SD_CLK MPP( 12, 0x1, 0, 1, 1, 1, 1, 1, 1 )
111 112#define MPP12_AU_SPDIF0 MPP( 12, 0xa, 0, 1, 0, 0, 0, 0, 1 )
112#define MPP14_GPIO MPP( 14, 0x0, 1, 1, 1, 1, 1, 1 ) 113#define MPP12_SPI_MOSI MPP( 12, 0xb, 0, 1, 0, 0, 0, 0, 1 )
113#define MPP14_SD_D0 MPP( 14, 0x1, 1, 1, 1, 1, 1, 1 ) 114#define MPP12_TW1_SDA MPP( 12, 0xd, 1, 0, 0, 0, 0, 0, 1 )
114#define MPP14_UART1_RXD MPP( 14, 0x3, 1, 0, 1, 1, 1, 1 ) 115
115#define MPP14_SATA1_PRESENTn MPP( 14, 0x4, 0, 1, 0, 0, 1, 1 ) 116#define MPP13_GPIO MPP( 13, 0x0, 1, 1, 1, 1, 1, 1, 1 )
116#define MPP14_MII0_COL MPP( 14, 0xd, 1, 0, 1, 1, 1, 1 ) 117#define MPP13_SD_CMD MPP( 13, 0x1, 1, 1, 1, 1, 1, 1, 1 )
117 118#define MPP13_UART1_TXD MPP( 13, 0x3, 0, 1, 1, 1, 1, 1, 1 )
118#define MPP15_GPIO MPP( 15, 0x0, 1, 1, 1, 1, 1, 1 ) 119#define MPP13_AU_SPDIFRMCLK MPP( 13, 0xa, 0, 1, 0, 0, 0, 0, 1 )
119#define MPP15_SD_D1 MPP( 15, 0x1, 1, 1, 1, 1, 1, 1 ) 120#define MPP13_LCDPWM MPP( 13, 0xb, 0, 1, 0, 0, 0, 0, 1 )
120#define MPP15_UART0_RTS MPP( 15, 0x2, 0, 1, 1, 1, 1, 1 ) 121
121#define MPP15_UART1_TXD MPP( 15, 0x3, 0, 1, 1, 1, 1, 1 ) 122#define MPP14_GPIO MPP( 14, 0x0, 1, 1, 1, 1, 1, 1, 1 )
122#define MPP15_SATA0_ACTn MPP( 15, 0x4, 0, 1, 0, 1, 1, 1 ) 123#define MPP14_SD_D0 MPP( 14, 0x1, 1, 1, 1, 1, 1, 1, 1 )
123 124#define MPP14_UART1_RXD MPP( 14, 0x3, 1, 0, 1, 1, 1, 1, 1 )
124#define MPP16_GPIO MPP( 16, 0x0, 1, 1, 1, 1, 1, 1 ) 125#define MPP14_SATA1_PRESENTn MPP( 14, 0x4, 0, 1, 0, 0, 1, 1, 1 )
125#define MPP16_SD_D2 MPP( 16, 0x1, 1, 1, 1, 1, 1, 1 ) 126#define MPP14_AU_SPDIFI MPP( 14, 0xa, 1, 0, 0, 0, 0, 0, 1 )
126#define MPP16_UART0_CTS MPP( 16, 0x2, 1, 0, 1, 1, 1, 1 ) 127#define MPP14_AU_I2SDI MPP( 14, 0xb, 1, 0, 0, 0, 0, 0, 1 )
127#define MPP16_UART1_RXD MPP( 16, 0x3, 1, 0, 1, 1, 1, 1 ) 128#define MPP14_MII0_COL MPP( 14, 0xd, 1, 0, 1, 1, 1, 1, 1 )
128#define MPP16_SATA1_ACTn MPP( 16, 0x4, 0, 1, 0, 0, 1, 1 ) 129
129#define MPP16_MII0_CRS MPP( 16, 0xd, 1, 0, 1, 1, 1, 1 ) 130#define MPP15_GPIO MPP( 15, 0x0, 1, 1, 1, 1, 1, 1, 1 )
130 131#define MPP15_SD_D1 MPP( 15, 0x1, 1, 1, 1, 1, 1, 1, 1 )
131#define MPP17_GPIO MPP( 17, 0x0, 1, 1, 1, 1, 1, 1 ) 132#define MPP15_UART0_RTS MPP( 15, 0x2, 0, 1, 1, 1, 1, 1, 1 )
132#define MPP17_SD_D3 MPP( 17, 0x1, 1, 1, 1, 1, 1, 1 ) 133#define MPP15_UART1_TXD MPP( 15, 0x3, 0, 1, 1, 1, 1, 1, 1 )
133#define MPP17_SATA0_PRESENTn MPP( 17, 0x4, 0, 1, 0, 1, 1, 1 ) 134#define MPP15_SATA0_ACTn MPP( 15, 0x4, 0, 1, 0, 1, 1, 1, 1 )
134 135#define MPP15_SPI_CSn MPP( 15, 0xb, 0, 1, 0, 0, 0, 0, 1 )
135#define MPP18_GPO MPP( 18, 0x0, 0, 1, 1, 1, 1, 1 ) 136
136#define MPP18_NF_IO0 MPP( 18, 0x1, 1, 1, 1, 1, 1, 1 ) 137#define MPP16_GPIO MPP( 16, 0x0, 1, 1, 1, 1, 1, 1, 1 )
137 138#define MPP16_SD_D2 MPP( 16, 0x1, 1, 1, 1, 1, 1, 1, 1 )
138#define MPP19_GPO MPP( 19, 0x0, 0, 1, 1, 1, 1, 1 ) 139#define MPP16_UART0_CTS MPP( 16, 0x2, 1, 0, 1, 1, 1, 1, 1 )
139#define MPP19_NF_IO1 MPP( 19, 0x1, 1, 1, 1, 1, 1, 1 ) 140#define MPP16_UART1_RXD MPP( 16, 0x3, 1, 0, 1, 1, 1, 1, 1 )
140 141#define MPP16_SATA1_ACTn MPP( 16, 0x4, 0, 1, 0, 0, 1, 1, 1 )
141#define MPP20_GPIO MPP( 20, 0x0, 1, 1, 0, 1, 1, 1 ) 142#define MPP16_LCD_EXT_REF_CLK MPP( 16, 0xb, 1, 0, 0, 0, 0, 0, 1 )
142#define MPP20_TSMP0 MPP( 20, 0x1, 1, 1, 0, 0, 1, 1 ) 143#define MPP16_MII0_CRS MPP( 16, 0xd, 1, 0, 1, 1, 1, 1, 1 )
143#define MPP20_TDM_CH0_TX_QL MPP( 20, 0x2, 0, 1, 0, 0, 1, 1 ) 144
144#define MPP20_GE1_0 MPP( 20, 0x3, 0, 0, 0, 1, 1, 1 ) 145#define MPP17_GPIO MPP( 17, 0x0, 1, 1, 1, 1, 1, 1, 1 )
145#define MPP20_AUDIO_SPDIFI MPP( 20, 0x4, 1, 0, 0, 0, 1, 1 ) 146#define MPP17_SD_D3 MPP( 17, 0x1, 1, 1, 1, 1, 1, 1, 1 )
146#define MPP20_SATA1_ACTn MPP( 20, 0x5, 0, 1, 0, 0, 1, 1 ) 147#define MPP17_SATA0_PRESENTn MPP( 17, 0x4, 0, 1, 0, 1, 1, 1, 1 )
147 148#define MPP17_SATA1_ACTn MPP( 17, 0xa, 0, 1, 0, 0, 0, 0, 1 )
148#define MPP21_GPIO MPP( 21, 0x0, 1, 1, 0, 1, 1, 1 ) 149#define MPP17_TW1_SCK MPP( 17, 0xd, 1, 1, 0, 0, 0, 0, 1 )
149#define MPP21_TSMP1 MPP( 21, 0x1, 1, 1, 0, 0, 1, 1 ) 150
150#define MPP21_TDM_CH0_RX_QL MPP( 21, 0x2, 0, 1, 0, 0, 1, 1 ) 151#define MPP18_GPO MPP( 18, 0x0, 0, 1, 1, 1, 1, 1, 1 )
151#define MPP21_GE1_1 MPP( 21, 0x3, 0, 0, 0, 1, 1, 1 ) 152#define MPP18_NF_IO0 MPP( 18, 0x1, 1, 1, 1, 1, 1, 1, 1 )
152#define MPP21_AUDIO_SPDIFO MPP( 21, 0x4, 0, 1, 0, 0, 1, 1 ) 153#define MPP18_PEX0_CLKREQ MPP( 18, 0x2, 0, 1, 0, 0, 0, 0, 1 )
153#define MPP21_SATA0_ACTn MPP( 21, 0x5, 0, 1, 0, 1, 1, 1 ) 154
154 155#define MPP19_GPO MPP( 19, 0x0, 0, 1, 1, 1, 1, 1, 1 )
155#define MPP22_GPIO MPP( 22, 0x0, 1, 1, 0, 1, 1, 1 ) 156#define MPP19_NF_IO1 MPP( 19, 0x1, 1, 1, 1, 1, 1, 1, 1 )
156#define MPP22_TSMP2 MPP( 22, 0x1, 1, 1, 0, 0, 1, 1 ) 157
157#define MPP22_TDM_CH2_TX_QL MPP( 22, 0x2, 0, 1, 0, 0, 1, 1 ) 158#define MPP20_GPIO MPP( 20, 0x0, 1, 1, 0, 1, 1, 1, 1 )
158#define MPP22_GE1_2 MPP( 22, 0x3, 0, 0, 0, 1, 1, 1 ) 159#define MPP20_TSMP0 MPP( 20, 0x1, 1, 1, 0, 0, 1, 1, 1 )
159#define MPP22_AUDIO_SPDIFRMKCLK MPP( 22, 0x4, 0, 1, 0, 0, 1, 1 ) 160#define MPP20_TDM_CH0_TX_QL MPP( 20, 0x2, 0, 1, 0, 0, 1, 1, 1 )
160#define MPP22_SATA1_PRESENTn MPP( 22, 0x5, 0, 1, 0, 0, 1, 1 ) 161#define MPP20_GE1_TXD0 MPP( 20, 0x3, 0, 0, 0, 1, 1, 1, 1 )
161 162#define MPP20_AU_SPDIFI MPP( 20, 0x4, 1, 0, 0, 0, 1, 1, 1 )
162#define MPP23_GPIO MPP( 23, 0x0, 1, 1, 0, 1, 1, 1 ) 163#define MPP20_SATA1_ACTn MPP( 20, 0x5, 0, 1, 0, 0, 1, 1, 1 )
163#define MPP23_TSMP3 MPP( 23, 0x1, 1, 1, 0, 0, 1, 1 ) 164#define MPP20_LCD_D0 MPP( 20, 0xb, 0, 0, 0, 0, 0, 0, 1 )
164#define MPP23_TDM_CH2_RX_QL MPP( 23, 0x2, 1, 0, 0, 0, 1, 1 ) 165
165#define MPP23_GE1_3 MPP( 23, 0x3, 0, 0, 0, 1, 1, 1 ) 166#define MPP21_GPIO MPP( 21, 0x0, 1, 1, 0, 1, 1, 1, 1 )
166#define MPP23_AUDIO_I2SBCLK MPP( 23, 0x4, 0, 1, 0, 0, 1, 1 ) 167#define MPP21_TSMP1 MPP( 21, 0x1, 1, 1, 0, 0, 1, 1, 1 )
167#define MPP23_SATA0_PRESENTn MPP( 23, 0x5, 0, 1, 0, 1, 1, 1 ) 168#define MPP21_TDM_CH0_RX_QL MPP( 21, 0x2, 0, 1, 0, 0, 1, 1, 1 )
168 169#define MPP21_GE1_TXD1 MPP( 21, 0x3, 0, 0, 0, 1, 1, 1, 1 )
169#define MPP24_GPIO MPP( 24, 0x0, 1, 1, 0, 1, 1, 1 ) 170#define MPP21_AU_SPDIFO MPP( 21, 0x4, 0, 1, 0, 0, 1, 1, 1 )
170#define MPP24_TSMP4 MPP( 24, 0x1, 1, 1, 0, 0, 1, 1 ) 171#define MPP21_SATA0_ACTn MPP( 21, 0x5, 0, 1, 0, 1, 1, 1, 1 )
171#define MPP24_TDM_SPI_CS0 DEV( 24, 0x2, 0, 1, 0, 0, 1, 1 ) 172#define MPP21_LCD_D1 MPP( 21, 0xb, 0, 0, 0, 0, 0, 0, 1 )
172#define MPP24_GE1_4 MPP( 24, 0x3, 0, 0, 0, 1, 1, 1 ) 173
173#define MPP24_AUDIO_I2SDO MPP( 24, 0x4, 0, 1, 0, 0, 1, 1 ) 174#define MPP22_GPIO MPP( 22, 0x0, 1, 1, 0, 1, 1, 1, 1 )
174 175#define MPP22_TSMP2 MPP( 22, 0x1, 1, 1, 0, 0, 1, 1, 1 )
175#define MPP25_GPIO MPP( 25, 0x0, 1, 1, 0, 1, 1, 1 ) 176#define MPP22_TDM_CH2_TX_QL MPP( 22, 0x2, 0, 1, 0, 0, 1, 1, 1 )
176#define MPP25_TSMP5 MPP( 25, 0x1, 1, 1, 0, 0, 1, 1 ) 177#define MPP22_GE1_TXD2 MPP( 22, 0x3, 0, 0, 0, 1, 1, 1, 1 )
177#define MPP25_TDM_SPI_SCK MPP( 25, 0x2, 0, 1, 0, 0, 1, 1 ) 178#define MPP22_AU_SPDIFRMKCLK MPP( 22, 0x4, 0, 1, 0, 0, 1, 1, 1 )
178#define MPP25_GE1_5 MPP( 25, 0x3, 0, 0, 0, 1, 1, 1 ) 179#define MPP22_SATA1_PRESENTn MPP( 22, 0x5, 0, 1, 0, 0, 1, 1, 1 )
179#define MPP25_AUDIO_I2SLRCLK MPP( 25, 0x4, 0, 1, 0, 0, 1, 1 ) 180#define MPP22_LCD_D2 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 )
180 181
181#define MPP26_GPIO MPP( 26, 0x0, 1, 1, 0, 1, 1, 1 ) 182#define MPP23_GPIO MPP( 23, 0x0, 1, 1, 0, 1, 1, 1, 1 )
182#define MPP26_TSMP6 MPP( 26, 0x1, 1, 1, 0, 0, 1, 1 ) 183#define MPP23_TSMP3 MPP( 23, 0x1, 1, 1, 0, 0, 1, 1, 1 )
183#define MPP26_TDM_SPI_MISO MPP( 26, 0x2, 1, 0, 0, 0, 1, 1 ) 184#define MPP23_TDM_CH2_RX_QL MPP( 23, 0x2, 1, 0, 0, 0, 1, 1, 1 )
184#define MPP26_GE1_6 MPP( 26, 0x3, 0, 0, 0, 1, 1, 1 ) 185#define MPP23_GE1_TXD3 MPP( 23, 0x3, 0, 0, 0, 1, 1, 1, 1 )
185#define MPP26_AUDIO_I2SMCLK MPP( 26, 0x4, 0, 1, 0, 0, 1, 1 ) 186#define MPP23_AU_I2SBCLK MPP( 23, 0x4, 0, 1, 0, 0, 1, 1, 1 )
186 187#define MPP23_SATA0_PRESENTn MPP( 23, 0x5, 0, 1, 0, 1, 1, 1, 1 )
187#define MPP27_GPIO MPP( 27, 0x0, 1, 1, 0, 1, 1, 1 ) 188#define MPP23_LCD_D3 MPP( 23, 0xb, 0, 0, 0, 0, 0, 0, 1 )
188#define MPP27_TSMP7 MPP( 27, 0x1, 1, 1, 0, 0, 1, 1 ) 189
189#define MPP27_TDM_SPI_MOSI MPP( 27, 0x2, 0, 1, 0, 0, 1, 1 ) 190#define MPP24_GPIO MPP( 24, 0x0, 1, 1, 0, 1, 1, 1, 1 )
190#define MPP27_GE1_7 MPP( 27, 0x3, 0, 0, 0, 1, 1, 1 ) 191#define MPP24_TSMP4 MPP( 24, 0x1, 1, 1, 0, 0, 1, 1, 1 )
191#define MPP27_AUDIO_I2SDI MPP( 27, 0x4, 1, 0, 0, 0, 1, 1 ) 192#define MPP24_TDM_SPI_CS0 MPP( 24, 0x2, 0, 1, 0, 0, 1, 1, 1 )
192 193#define MPP24_GE1_RXD0 MPP( 24, 0x3, 0, 0, 0, 1, 1, 1, 1 )
193#define MPP28_GPIO MPP( 28, 0x0, 1, 1, 0, 1, 1, 1 ) 194#define MPP24_AU_I2SDO MPP( 24, 0x4, 0, 1, 0, 0, 1, 1, 1 )
194#define MPP28_TSMP8 MPP( 28, 0x1, 1, 1, 0, 0, 1, 1 ) 195#define MPP24_LCD_D4 MPP( 24, 0xb, 0, 0, 0, 0, 0, 0, 1 )
195#define MPP28_TDM_CODEC_INTn MPP( 28, 0x2, 0, 0, 0, 0, 1, 1 ) 196
196#define MPP28_GE1_8 MPP( 28, 0x3, 0, 0, 0, 1, 1, 1 ) 197#define MPP25_GPIO MPP( 25, 0x0, 1, 1, 0, 1, 1, 1, 1 )
197#define MPP28_AUDIO_EXTCLK MPP( 28, 0x4, 1, 0, 0, 0, 1, 1 ) 198#define MPP25_TSMP5 MPP( 25, 0x1, 1, 1, 0, 0, 1, 1, 1 )
198 199#define MPP25_TDM_SPI_SCK MPP( 25, 0x2, 0, 1, 0, 0, 1, 1, 1 )
199#define MPP29_GPIO MPP( 29, 0x0, 1, 1, 0, 1, 1, 1 ) 200#define MPP25_GE1_RXD1 MPP( 25, 0x3, 0, 0, 0, 1, 1, 1, 1 )
200#define MPP29_TSMP9 MPP( 29, 0x1, 1, 1, 0, 0, 1, 1 ) 201#define MPP25_AU_I2SLRCLK MPP( 25, 0x4, 0, 1, 0, 0, 1, 1, 1 )
201#define MPP29_TDM_CODEC_RSTn MPP( 29, 0x2, 0, 0, 0, 0, 1, 1 ) 202#define MPP25_LCD_D5 MPP( 25, 0xb, 0, 0, 0, 0, 0, 0, 1 )
202#define MPP29_GE1_9 MPP( 29, 0x3, 0, 0, 0, 1, 1, 1 ) 203
203 204#define MPP26_GPIO MPP( 26, 0x0, 1, 1, 0, 1, 1, 1, 1 )
204#define MPP30_GPIO MPP( 30, 0x0, 1, 1, 0, 1, 1, 1 ) 205#define MPP26_TSMP6 MPP( 26, 0x1, 1, 1, 0, 0, 1, 1, 1 )
205#define MPP30_TSMP10 MPP( 30, 0x1, 1, 1, 0, 0, 1, 1 ) 206#define MPP26_TDM_SPI_MISO MPP( 26, 0x2, 1, 0, 0, 0, 1, 1, 1 )
206#define MPP30_TDM_PCLK MPP( 30, 0x2, 1, 1, 0, 0, 1, 1 ) 207#define MPP26_GE1_RXD2 MPP( 26, 0x3, 0, 0, 0, 1, 1, 1, 1 )
207#define MPP30_GE1_10 MPP( 30, 0x3, 0, 0, 0, 1, 1, 1 ) 208#define MPP26_AU_I2SMCLK MPP( 26, 0x4, 0, 1, 0, 0, 1, 1, 1 )
208 209#define MPP26_LCD_D6 MPP( 26, 0xb, 0, 0, 0, 0, 0, 0, 1 )
209#define MPP31_GPIO MPP( 31, 0x0, 1, 1, 0, 1, 1, 1 ) 210
210#define MPP31_TSMP11 MPP( 31, 0x1, 1, 1, 0, 0, 1, 1 ) 211#define MPP27_GPIO MPP( 27, 0x0, 1, 1, 0, 1, 1, 1, 1 )
211#define MPP31_TDM_FS MPP( 31, 0x2, 1, 1, 0, 0, 1, 1 ) 212#define MPP27_TSMP7 MPP( 27, 0x1, 1, 1, 0, 0, 1, 1, 1 )
212#define MPP31_GE1_11 MPP( 31, 0x3, 0, 0, 0, 1, 1, 1 ) 213#define MPP27_TDM_SPI_MOSI MPP( 27, 0x2, 0, 1, 0, 0, 1, 1, 1 )
213 214#define MPP27_GE1_RXD3 MPP( 27, 0x3, 0, 0, 0, 1, 1, 1, 1 )
214#define MPP32_GPIO MPP( 32, 0x0, 1, 1, 0, 1, 1, 1 ) 215#define MPP27_AU_I2SDI MPP( 27, 0x4, 1, 0, 0, 0, 1, 1, 1 )
215#define MPP32_TSMP12 MPP( 32, 0x1, 1, 1, 0, 0, 1, 1 ) 216#define MPP27_LCD_D7 MPP( 27, 0xb, 0, 0, 0, 0, 0, 0, 1 )
216#define MPP32_TDM_DRX MPP( 32, 0x2, 1, 0, 0, 0, 1, 1 ) 217
217#define MPP32_GE1_12 MPP( 32, 0x3, 0, 0, 0, 1, 1, 1 ) 218#define MPP28_GPIO MPP( 28, 0x0, 1, 1, 0, 1, 1, 1, 1 )
218 219#define MPP28_TSMP8 MPP( 28, 0x1, 1, 1, 0, 0, 1, 1, 1 )
219#define MPP33_GPIO MPP( 33, 0x0, 1, 1, 0, 1, 1, 1 ) 220#define MPP28_TDM_CODEC_INTn MPP( 28, 0x2, 0, 0, 0, 0, 1, 1, 1 )
220#define MPP33_TDM_DTX MPP( 33, 0x2, 0, 1, 0, 0, 1, 1 ) 221#define MPP28_GE1_COL MPP( 28, 0x3, 0, 0, 0, 1, 1, 1, 1 )
221#define MPP33_GE1_13 MPP( 33, 0x3, 0, 0, 0, 1, 1, 1 ) 222#define MPP28_AU_EXTCLK MPP( 28, 0x4, 1, 0, 0, 0, 1, 1, 1 )
222 223#define MPP28_LCD_D8 MPP( 28, 0xb, 0, 0, 0, 0, 0, 0, 1 )
223#define MPP34_GPIO MPP( 34, 0x0, 1, 1, 0, 1, 1, 1 ) 224
224#define MPP34_TDM_SPI_CS1 MPP( 34, 0x2, 0, 1, 0, 0, 1, 1 ) 225#define MPP29_GPIO MPP( 29, 0x0, 1, 1, 0, 1, 1, 1, 1 )
225#define MPP34_GE1_14 MPP( 34, 0x3, 0, 0, 0, 1, 1, 1 ) 226#define MPP29_TSMP9 MPP( 29, 0x1, 1, 1, 0, 0, 1, 1, 1 )
226 227#define MPP29_TDM_CODEC_RSTn MPP( 29, 0x2, 0, 0, 0, 0, 1, 1, 1 )
227#define MPP35_GPIO MPP( 35, 0x0, 1, 1, 1, 1, 1, 1 ) 228#define MPP29_GE1_TCLK MPP( 29, 0x3, 0, 0, 0, 1, 1, 1, 1 )
228#define MPP35_TDM_CH0_TX_QL MPP( 35, 0x2, 0, 1, 0, 0, 1, 1 ) 229#define MPP29_LCD_D9 MPP( 29, 0xb, 0, 0, 0, 0, 0, 0, 1 )
229#define MPP35_GE1_15 MPP( 35, 0x3, 0, 0, 0, 1, 1, 1 ) 230
230#define MPP35_SATA0_ACTn MPP( 35, 0x5, 0, 1, 0, 1, 1, 1 ) 231#define MPP30_GPIO MPP( 30, 0x0, 1, 1, 0, 1, 1, 1, 1 )
231#define MPP35_MII0_RXERR MPP( 35, 0xc, 1, 0, 1, 1, 1, 1 ) 232#define MPP30_TSMP10 MPP( 30, 0x1, 1, 1, 0, 0, 1, 1, 1 )
232 233#define MPP30_TDM_PCLK MPP( 30, 0x2, 1, 1, 0, 0, 1, 1, 1 )
233#define MPP36_GPIO MPP( 36, 0x0, 1, 1, 1, 0, 0, 1 ) 234#define MPP30_GE1_RXCTL MPP( 30, 0x3, 0, 0, 0, 1, 1, 1, 1 )
234#define MPP36_TSMP0 MPP( 36, 0x1, 1, 1, 0, 0, 0, 1 ) 235#define MPP30_LCD_D10 MPP( 30, 0xb, 0, 0, 0, 0, 0, 0, 1 )
235#define MPP36_TDM_SPI_CS1 MPP( 36, 0x2, 0, 1, 0, 0, 0, 1 ) 236
236#define MPP36_AUDIO_SPDIFI MPP( 36, 0x4, 1, 0, 1, 0, 0, 1 ) 237#define MPP31_GPIO MPP( 31, 0x0, 1, 1, 0, 1, 1, 1, 1 )
237 238#define MPP31_TSMP11 MPP( 31, 0x1, 1, 1, 0, 0, 1, 1, 1 )
238#define MPP37_GPIO MPP( 37, 0x0, 1, 1, 1, 0, 0, 1 ) 239#define MPP31_TDM_FS MPP( 31, 0x2, 1, 1, 0, 0, 1, 1, 1 )
239#define MPP37_TSMP1 MPP( 37, 0x1, 1, 1, 0, 0, 0, 1 ) 240#define MPP31_GE1_RXCLK MPP( 31, 0x3, 0, 0, 0, 1, 1, 1, 1 )
240#define MPP37_TDM_CH2_TX_QL MPP( 37, 0x2, 0, 1, 0, 0, 0, 1 ) 241#define MPP31_LCD_D11 MPP( 31, 0xb, 0, 0, 0, 0, 0, 0, 1 )
241#define MPP37_AUDIO_SPDIFO MPP( 37, 0x4, 0, 1, 1, 0, 0, 1 ) 242
242 243#define MPP32_GPIO MPP( 32, 0x0, 1, 1, 0, 1, 1, 1, 1 )
243#define MPP38_GPIO MPP( 38, 0x0, 1, 1, 1, 0, 0, 1 ) 244#define MPP32_TSMP12 MPP( 32, 0x1, 1, 1, 0, 0, 1, 1, 1 )
244#define MPP38_TSMP2 MPP( 38, 0x1, 1, 1, 0, 0, 0, 1 ) 245#define MPP32_TDM_DRX MPP( 32, 0x2, 1, 0, 0, 0, 1, 1, 1 )
245#define MPP38_TDM_CH2_RX_QL MPP( 38, 0x2, 0, 1, 0, 0, 0, 1 ) 246#define MPP32_GE1_TCLKOUT MPP( 32, 0x3, 0, 0, 0, 1, 1, 1, 1 )
246#define MPP38_AUDIO_SPDIFRMLCLK MPP( 38, 0x4, 0, 1, 1, 0, 0, 1 ) 247#define MPP32_LCD_D12 MPP( 32, 0xb, 0, 0, 0, 0, 0, 0, 1 )
247 248
248#define MPP39_GPIO MPP( 39, 0x0, 1, 1, 1, 0, 0, 1 ) 249#define MPP33_GPO MPP( 33, 0x0, 0, 1, 0, 1, 1, 1, 1 )
249#define MPP39_TSMP3 MPP( 39, 0x1, 1, 1, 0, 0, 0, 1 ) 250#define MPP33_TDM_DTX MPP( 33, 0x2, 0, 1, 0, 0, 1, 1, 1 )
250#define MPP39_TDM_SPI_CS0 MPP( 39, 0x2, 0, 1, 0, 0, 0, 1 ) 251#define MPP33_GE1_TXCTL MPP( 33, 0x3, 0, 0, 0, 1, 1, 1, 1 )
251#define MPP39_AUDIO_I2SBCLK MPP( 39, 0x4, 0, 1, 1, 0, 0, 1 ) 252#define MPP33_LCD_D13 MPP( 33, 0xb, 0, 0, 0, 0, 0, 0, 1 )
252 253
253#define MPP40_GPIO MPP( 40, 0x0, 1, 1, 1, 0, 0, 1 ) 254#define MPP34_GPIO MPP( 34, 0x0, 1, 1, 0, 1, 1, 1, 1 )
254#define MPP40_TSMP4 MPP( 40, 0x1, 1, 1, 0, 0, 0, 1 ) 255#define MPP34_TDM_SPI_CS1 MPP( 34, 0x2, 0, 1, 0, 0, 1, 1, 1 )
255#define MPP40_TDM_SPI_SCK MPP( 40, 0x2, 0, 1, 0, 0, 0, 1 ) 256#define MPP34_GE1_TXEN MPP( 34, 0x3, 0, 0, 0, 1, 1, 1, 1 )
256#define MPP40_AUDIO_I2SDO MPP( 40, 0x4, 0, 1, 1, 0, 0, 1 ) 257#define MPP34_SATA1_ACTn MPP( 34, 0x5, 0, 1, 0, 0, 0, 1, 1 )
257 258#define MPP34_LCD_D14 MPP( 34, 0xb, 0, 0, 0, 0, 0, 0, 1 )
258#define MPP41_GPIO MPP( 41, 0x0, 1, 1, 1, 0, 0, 1 ) 259
259#define MPP41_TSMP5 MPP( 41, 0x1, 1, 1, 0, 0, 0, 1 ) 260#define MPP35_GPIO MPP( 35, 0x0, 1, 1, 1, 1, 1, 1, 1 )
260#define MPP41_TDM_SPI_MISO MPP( 41, 0x2, 1, 0, 0, 0, 0, 1 ) 261#define MPP35_TDM_CH0_TX_QL MPP( 35, 0x2, 0, 1, 0, 0, 1, 1, 1 )
261#define MPP41_AUDIO_I2SLRC MPP( 41, 0x4, 0, 1, 1, 0, 0, 1 ) 262#define MPP35_GE1_RXERR MPP( 35, 0x3, 0, 0, 0, 1, 1, 1, 1 )
262 263#define MPP35_SATA0_ACTn MPP( 35, 0x5, 0, 1, 0, 1, 1, 1, 1 )
263#define MPP42_GPIO MPP( 42, 0x0, 1, 1, 1, 0, 0, 1 ) 264#define MPP35_LCD_D15 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 )
264#define MPP42_TSMP6 MPP( 42, 0x1, 1, 1, 0, 0, 0, 1 ) 265#define MPP35_MII0_RXERR MPP( 35, 0xc, 1, 0, 1, 1, 1, 1, 1 )
265#define MPP42_TDM_SPI_MOSI MPP( 42, 0x2, 0, 1, 0, 0, 0, 1 ) 266
266#define MPP42_AUDIO_I2SMCLK MPP( 42, 0x4, 0, 1, 1, 0, 0, 1 ) 267#define MPP36_GPIO MPP( 36, 0x0, 1, 1, 1, 0, 0, 1, 1 )
267 268#define MPP36_TSMP0 MPP( 36, 0x1, 1, 1, 0, 0, 0, 1, 1 )
268#define MPP43_GPIO MPP( 43, 0x0, 1, 1, 1, 0, 0, 1 ) 269#define MPP36_TDM_SPI_CS1 MPP( 36, 0x2, 0, 1, 0, 0, 0, 1, 1 )
269#define MPP43_TSMP7 MPP( 43, 0x1, 1, 1, 0, 0, 0, 1 ) 270#define MPP36_AU_SPDIFI MPP( 36, 0x4, 1, 0, 1, 0, 0, 1, 1 )
270#define MPP43_TDM_CODEC_INTn MPP( 43, 0x2, 0, 0, 0, 0, 0, 1 ) 271#define MPP36_TW1_SDA MPP( 36, 0xb, 1, 1, 0, 0, 0, 0, 1 )
271#define MPP43_AUDIO_I2SDI MPP( 43, 0x4, 1, 0, 1, 0, 0, 1 ) 272
272 273#define MPP37_GPIO MPP( 37, 0x0, 1, 1, 1, 0, 0, 1, 1 )
273#define MPP44_GPIO MPP( 44, 0x0, 1, 1, 1, 0, 0, 1 ) 274#define MPP37_TSMP1 MPP( 37, 0x1, 1, 1, 0, 0, 0, 1, 1 )
274#define MPP44_TSMP8 MPP( 44, 0x1, 1, 1, 0, 0, 0, 1 ) 275#define MPP37_TDM_CH2_TX_QL MPP( 37, 0x2, 0, 1, 0, 0, 0, 1, 1 )
275#define MPP44_TDM_CODEC_RSTn MPP( 44, 0x2, 0, 0, 0, 0, 0, 1 ) 276#define MPP37_AU_SPDIFO MPP( 37, 0x4, 0, 1, 1, 0, 0, 1, 1 )
276#define MPP44_AUDIO_EXTCLK MPP( 44, 0x4, 1, 0, 1, 0, 0, 1 ) 277#define MPP37_TW1_SCK MPP( 37, 0xb, 1, 1, 0, 0, 0, 0, 1 )
277 278
278#define MPP45_GPIO MPP( 45, 0x0, 1, 1, 0, 0, 0, 1 ) 279#define MPP38_GPIO MPP( 38, 0x0, 1, 1, 1, 0, 0, 1, 1 )
279#define MPP45_TSMP9 MPP( 45, 0x1, 1, 1, 0, 0, 0, 1 ) 280#define MPP38_TSMP2 MPP( 38, 0x1, 1, 1, 0, 0, 0, 1, 1 )
280#define MPP45_TDM_PCLK MPP( 45, 0x2, 1, 1, 0, 0, 0, 1 ) 281#define MPP38_TDM_CH2_RX_QL MPP( 38, 0x2, 0, 1, 0, 0, 0, 1, 1 )
281 282#define MPP38_AU_SPDIFRMLCLK MPP( 38, 0x4, 0, 1, 1, 0, 0, 1, 1 )
282#define MPP46_GPIO MPP( 46, 0x0, 1, 1, 0, 0, 0, 1 ) 283#define MPP38_LCD_D18 MPP( 38, 0xb, 0, 0, 0, 0, 0, 0, 1 )
283#define MPP46_TSMP10 MPP( 46, 0x1, 1, 1, 0, 0, 0, 1 ) 284
284#define MPP46_TDM_FS MPP( 46, 0x2, 1, 1, 0, 0, 0, 1 ) 285#define MPP39_GPIO MPP( 39, 0x0, 1, 1, 1, 0, 0, 1, 1 )
285 286#define MPP39_TSMP3 MPP( 39, 0x1, 1, 1, 0, 0, 0, 1, 1 )
286#define MPP47_GPIO MPP( 47, 0x0, 1, 1, 0, 0, 0, 1 ) 287#define MPP39_TDM_SPI_CS0 MPP( 39, 0x2, 0, 1, 0, 0, 0, 1, 1 )
287#define MPP47_TSMP11 MPP( 47, 0x1, 1, 1, 0, 0, 0, 1 ) 288#define MPP39_AU_I2SBCLK MPP( 39, 0x4, 0, 1, 1, 0, 0, 1, 1 )
288#define MPP47_TDM_DRX MPP( 47, 0x2, 1, 0, 0, 0, 0, 1 ) 289#define MPP39_LCD_D19 MPP( 39, 0xb, 0, 0, 0, 0, 0, 0, 1 )
289 290
290#define MPP48_GPIO MPP( 48, 0x0, 1, 1, 0, 0, 0, 1 ) 291#define MPP40_GPIO MPP( 40, 0x0, 1, 1, 1, 0, 0, 1, 1 )
291#define MPP48_TSMP12 MPP( 48, 0x1, 1, 1, 0, 0, 0, 1 ) 292#define MPP40_TSMP4 MPP( 40, 0x1, 1, 1, 0, 0, 0, 1, 1 )
292#define MPP48_TDM_DTX MPP( 48, 0x2, 0, 1, 0, 0, 0, 1 ) 293#define MPP40_TDM_SPI_SCK MPP( 40, 0x2, 0, 1, 0, 0, 0, 1, 1 )
293 294#define MPP40_AU_I2SDO MPP( 40, 0x4, 0, 1, 1, 0, 0, 1, 1 )
294#define MPP49_GPIO MPP( 49, 0x0, 1, 1, 0, 0, 0, 1 ) 295#define MPP40_LCD_D20 MPP( 40, 0xb, 0, 0, 0, 0, 0, 0, 1 )
295#define MPP49_TSMP9 MPP( 49, 0x1, 1, 1, 0, 0, 0, 1 ) 296
296#define MPP49_TDM_CH0_RX_QL MPP( 49, 0x2, 0, 1, 0, 0, 0, 1 ) 297#define MPP41_GPIO MPP( 41, 0x0, 1, 1, 1, 0, 0, 1, 1 )
297#define MPP49_PTP_CLK MPP( 49, 0x5, 1, 0, 0, 0, 0, 1 ) 298#define MPP41_TSMP5 MPP( 41, 0x1, 1, 1, 0, 0, 0, 1, 1 )
299#define MPP41_TDM_SPI_MISO MPP( 41, 0x2, 1, 0, 0, 0, 0, 1, 1 )
300#define MPP41_AU_I2SLRCLK MPP( 41, 0x4, 0, 1, 1, 0, 0, 1, 1 )
301#define MPP41_LCD_D21 MPP( 41, 0xb, 0, 0, 0, 0, 0, 0, 1 )
302
303#define MPP42_GPIO MPP( 42, 0x0, 1, 1, 1, 0, 0, 1, 1 )
304#define MPP42_TSMP6 MPP( 42, 0x1, 1, 1, 0, 0, 0, 1, 1 )
305#define MPP42_TDM_SPI_MOSI MPP( 42, 0x2, 0, 1, 0, 0, 0, 1, 1 )
306#define MPP42_AU_I2SMCLK MPP( 42, 0x4, 0, 1, 1, 0, 0, 1, 1 )
307#define MPP42_LCD_D22 MPP( 42, 0xb, 0, 0, 0, 0, 0, 0, 1 )
308
309#define MPP43_GPIO MPP( 43, 0x0, 1, 1, 1, 0, 0, 1, 1 )
310#define MPP43_TSMP7 MPP( 43, 0x1, 1, 1, 0, 0, 0, 1, 1 )
311#define MPP43_TDM_CODEC_INTn MPP( 43, 0x2, 0, 0, 0, 0, 0, 1, 1 )
312#define MPP43_AU_I2SDI MPP( 43, 0x4, 1, 0, 1, 0, 0, 1, 1 )
313#define MPP43_LCD_D23 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 )
314
315#define MPP44_GPIO MPP( 44, 0x0, 1, 1, 1, 0, 0, 1, 1 )
316#define MPP44_TSMP8 MPP( 44, 0x1, 1, 1, 0, 0, 0, 1, 1 )
317#define MPP44_TDM_CODEC_RSTn MPP( 44, 0x2, 0, 0, 0, 0, 0, 1, 1 )
318#define MPP44_AU_EXTCLK MPP( 44, 0x4, 1, 0, 1, 0, 0, 1, 1 )
319#define MPP44_LCD_CLK MPP( 44, 0xb, 0, 0, 0, 0, 0, 0, 1 )
320
321#define MPP45_GPIO MPP( 45, 0x0, 1, 1, 0, 0, 0, 1, 1 )
322#define MPP45_TSMP9 MPP( 45, 0x1, 1, 1, 0, 0, 0, 1, 1 )
323#define MPP45_TDM_PCLK MPP( 45, 0x2, 1, 1, 0, 0, 0, 1, 1 )
324#define MPP245_LCD_E MPP( 45, 0xb, 0, 0, 0, 0, 0, 0, 1 )
325
326#define MPP46_GPIO MPP( 46, 0x0, 1, 1, 0, 0, 0, 1, 1 )
327#define MPP46_TSMP10 MPP( 46, 0x1, 1, 1, 0, 0, 0, 1, 1 )
328#define MPP46_TDM_FS MPP( 46, 0x2, 1, 1, 0, 0, 0, 1, 1 )
329#define MPP46_LCD_HSYNC MPP( 46, 0xb, 0, 0, 0, 0, 0, 0, 1 )
330
331#define MPP47_GPIO MPP( 47, 0x0, 1, 1, 0, 0, 0, 1, 1 )
332#define MPP47_TSMP11 MPP( 47, 0x1, 1, 1, 0, 0, 0, 1, 1 )
333#define MPP47_TDM_DRX MPP( 47, 0x2, 1, 0, 0, 0, 0, 1, 1 )
334#define MPP47_LCD_VSYNC MPP( 47, 0xb, 0, 0, 0, 0, 0, 0, 1 )
335
336#define MPP48_GPIO MPP( 48, 0x0, 1, 1, 0, 0, 0, 1, 1 )
337#define MPP48_TSMP12 MPP( 48, 0x1, 1, 1, 0, 0, 0, 1, 1 )
338#define MPP48_TDM_DTX MPP( 48, 0x2, 0, 1, 0, 0, 0, 1, 1 )
339#define MPP48_LCD_D16 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 )
340
341#define MPP49_GPIO MPP( 49, 0x0, 1, 1, 0, 0, 0, 1, 0 )
342#define MPP49_GPO MPP( 49, 0x0, 0, 1, 0, 0, 0, 0, 1 )
343#define MPP49_TSMP9 MPP( 49, 0x1, 1, 1, 0, 0, 0, 1, 0 )
344#define MPP49_TDM_CH0_RX_QL MPP( 49, 0x2, 0, 1, 0, 0, 0, 1, 1 )
345#define MPP49_PTP_CLK MPP( 49, 0x5, 1, 0, 0, 0, 0, 1, 0 )
346#define MPP49_PEX0_CLKREQ MPP( 49, 0xa, 0, 1, 0, 0, 0, 0, 1 )
347#define MPP49_LCD_D17 MPP( 49, 0xb, 0, 0, 0, 0, 0, 0, 1 )
298 348
299#define MPP_MAX 49 349#define MPP_MAX 49
300 350
diff --git a/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c b/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
index 5e6f711b1c67..c6b92b42eb4e 100644
--- a/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
+++ b/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
@@ -155,7 +155,7 @@ static void __init mv88f6281gtw_ge_init(void)
155static int __init mv88f6281gtw_ge_pci_init(void) 155static int __init mv88f6281gtw_ge_pci_init(void)
156{ 156{
157 if (machine_is_mv88f6281gtw_ge()) 157 if (machine_is_mv88f6281gtw_ge())
158 kirkwood_pcie_init(); 158 kirkwood_pcie_init(KW_PCIE0);
159 159
160 return 0; 160 return 0;
161} 161}
diff --git a/arch/arm/mach-kirkwood/netspace_v2-setup.c b/arch/arm/mach-kirkwood/netspace_v2-setup.c
index 3ae158d72681..d26bf324738b 100644
--- a/arch/arm/mach-kirkwood/netspace_v2-setup.c
+++ b/arch/arm/mach-kirkwood/netspace_v2-setup.c
@@ -39,6 +39,7 @@
39#include <asm/mach/arch.h> 39#include <asm/mach/arch.h>
40#include <asm/mach/time.h> 40#include <asm/mach/time.h>
41#include <mach/kirkwood.h> 41#include <mach/kirkwood.h>
42#include <mach/leds-ns2.h>
42#include <plat/time.h> 43#include <plat/time.h>
43#include "common.h" 44#include "common.h"
44#include "mpp.h" 45#include "mpp.h"
@@ -126,6 +127,18 @@ static void __init netspace_v2_sata_power_init(void)
126 } 127 }
127 if (err) 128 if (err)
128 pr_err("netspace_v2: failed to setup SATA0 power\n"); 129 pr_err("netspace_v2: failed to setup SATA0 power\n");
130
131 if (machine_is_netspace_max_v2()) {
132 err = gpio_request(NETSPACE_V2_GPIO_SATA1_POWER, "SATA1 power");
133 if (err == 0) {
134 err = gpio_direction_output(
135 NETSPACE_V2_GPIO_SATA1_POWER, 1);
136 if (err)
137 gpio_free(NETSPACE_V2_GPIO_SATA1_POWER);
138 }
139 if (err)
140 pr_err("netspace_v2: failed to setup SATA1 power\n");
141 }
129} 142}
130 143
131/***************************************************************************** 144/*****************************************************************************
@@ -160,36 +173,12 @@ static struct platform_device netspace_v2_gpio_buttons = {
160 * GPIO LEDs 173 * GPIO LEDs
161 ****************************************************************************/ 174 ****************************************************************************/
162 175
163/*
164 * The blue front LED is wired to a CPLD and can blink in relation with the
165 * SATA activity.
166 *
167 * The following array detail the different LED registers and the combination
168 * of their possible values:
169 *
170 * cmd_led | slow_led | /SATA active | LED state
171 * | | |
172 * 1 | 0 | x | off
173 * - | 1 | x | on
174 * 0 | 0 | 1 | on
175 * 0 | 0 | 0 | blink (rate 300ms)
176 */
177
178#define NETSPACE_V2_GPIO_RED_LED 12 176#define NETSPACE_V2_GPIO_RED_LED 12
179#define NETSPACE_V2_GPIO_BLUE_LED_SLOW 29
180#define NETSPACE_V2_GPIO_BLUE_LED_CMD 30
181
182 177
183static struct gpio_led netspace_v2_gpio_led_pins[] = { 178static struct gpio_led netspace_v2_gpio_led_pins[] = {
184 { 179 {
185 .name = "ns_v2:blue:sata", 180 .name = "ns_v2:red:fail",
186 .default_trigger = "default-on", 181 .gpio = NETSPACE_V2_GPIO_RED_LED,
187 .gpio = NETSPACE_V2_GPIO_BLUE_LED_CMD,
188 .active_low = 1,
189 },
190 {
191 .name = "ns_v2:red:fail",
192 .gpio = NETSPACE_V2_GPIO_RED_LED,
193 }, 182 },
194}; 183};
195 184
@@ -206,22 +195,33 @@ static struct platform_device netspace_v2_gpio_leds = {
206 }, 195 },
207}; 196};
208 197
209static void __init netspace_v2_gpio_leds_init(void) 198/*****************************************************************************
210{ 199 * Dual-GPIO CPLD LEDs
211 int err; 200 ****************************************************************************/
212 201
213 /* Configure register slow_led to allow SATA activity LED blinking */ 202#define NETSPACE_V2_GPIO_BLUE_LED_SLOW 29
214 err = gpio_request(NETSPACE_V2_GPIO_BLUE_LED_SLOW, "blue LED slow"); 203#define NETSPACE_V2_GPIO_BLUE_LED_CMD 30
215 if (err == 0) {
216 err = gpio_direction_output(NETSPACE_V2_GPIO_BLUE_LED_SLOW, 0);
217 if (err)
218 gpio_free(NETSPACE_V2_GPIO_BLUE_LED_SLOW);
219 }
220 if (err)
221 pr_err("netspace_v2: failed to configure blue LED slow GPIO\n");
222 204
223 platform_device_register(&netspace_v2_gpio_leds); 205static struct ns2_led netspace_v2_led_pins[] = {
224} 206 {
207 .name = "ns_v2:blue:sata",
208 .cmd = NETSPACE_V2_GPIO_BLUE_LED_CMD,
209 .slow = NETSPACE_V2_GPIO_BLUE_LED_SLOW,
210 },
211};
212
213static struct ns2_led_platform_data netspace_v2_leds_data = {
214 .num_leds = ARRAY_SIZE(netspace_v2_led_pins),
215 .leds = netspace_v2_led_pins,
216};
217
218static struct platform_device netspace_v2_leds = {
219 .name = "leds-ns2",
220 .id = -1,
221 .dev = {
222 .platform_data = &netspace_v2_leds_data,
223 },
224};
225 225
226/***************************************************************************** 226/*****************************************************************************
227 * Timer 227 * Timer
@@ -249,17 +249,21 @@ static unsigned int netspace_v2_mpp_config[] __initdata = {
249 MPP4_NF_IO6, 249 MPP4_NF_IO6,
250 MPP5_NF_IO7, 250 MPP5_NF_IO7,
251 MPP6_SYSRST_OUTn, 251 MPP6_SYSRST_OUTn,
252 MPP8_TW_SDA, 252 MPP7_GPO, /* Fan speed (bit 1) */
253 MPP9_TW_SCK, 253 MPP8_TW0_SDA,
254 MPP9_TW0_SCK,
254 MPP10_UART0_TXD, 255 MPP10_UART0_TXD,
255 MPP11_UART0_RXD, 256 MPP11_UART0_RXD,
256 MPP12_GPO, /* Red led */ 257 MPP12_GPO, /* Red led */
257 MPP14_GPIO, /* USB fuse */ 258 MPP14_GPIO, /* USB fuse */
258 MPP16_GPIO, /* SATA 0 power */ 259 MPP16_GPIO, /* SATA 0 power */
260 MPP17_GPIO, /* SATA 1 power */
259 MPP18_NF_IO0, 261 MPP18_NF_IO0,
260 MPP19_NF_IO1, 262 MPP19_NF_IO1,
261 MPP20_SATA1_ACTn, 263 MPP20_SATA1_ACTn,
262 MPP21_SATA0_ACTn, 264 MPP21_SATA0_ACTn,
265 MPP22_GPIO, /* Fan speed (bit 0) */
266 MPP23_GPIO, /* Fan power */
263 MPP24_GPIO, /* USB mode select */ 267 MPP24_GPIO, /* USB mode select */
264 MPP25_GPIO, /* Fan rotation fail */ 268 MPP25_GPIO, /* Fan rotation fail */
265 MPP26_GPIO, /* USB device vbus */ 269 MPP26_GPIO, /* USB device vbus */
@@ -268,6 +272,7 @@ static unsigned int netspace_v2_mpp_config[] __initdata = {
268 MPP30_GPIO, /* Blue led (command register) */ 272 MPP30_GPIO, /* Blue led (command register) */
269 MPP31_GPIO, /* Board power off */ 273 MPP31_GPIO, /* Board power off */
270 MPP32_GPIO, /* Power button (0 = Released, 1 = Pushed) */ 274 MPP32_GPIO, /* Power button (0 = Released, 1 = Pushed) */
275 MPP33_GPO, /* Fan speed (bit 2) */
271 0 276 0
272}; 277};
273 278
@@ -299,7 +304,8 @@ static void __init netspace_v2_init(void)
299 i2c_register_board_info(0, netspace_v2_i2c_info, 304 i2c_register_board_info(0, netspace_v2_i2c_info,
300 ARRAY_SIZE(netspace_v2_i2c_info)); 305 ARRAY_SIZE(netspace_v2_i2c_info));
301 306
302 netspace_v2_gpio_leds_init(); 307 platform_device_register(&netspace_v2_leds);
308 platform_device_register(&netspace_v2_gpio_leds);
303 platform_device_register(&netspace_v2_gpio_buttons); 309 platform_device_register(&netspace_v2_gpio_buttons);
304 310
305 if (gpio_request(NETSPACE_V2_GPIO_POWER_OFF, "power-off") == 0 && 311 if (gpio_request(NETSPACE_V2_GPIO_POWER_OFF, "power-off") == 0 &&
@@ -332,3 +338,15 @@ MACHINE_START(INETSPACE_V2, "LaCie Internet Space v2")
332 .timer = &netspace_v2_timer, 338 .timer = &netspace_v2_timer,
333MACHINE_END 339MACHINE_END
334#endif 340#endif
341
342#ifdef CONFIG_MACH_NETSPACE_MAX_V2
343MACHINE_START(NETSPACE_MAX_V2, "LaCie Network Space Max v2")
344 .phys_io = KIRKWOOD_REGS_PHYS_BASE,
345 .io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
346 .boot_params = 0x00000100,
347 .init_machine = netspace_v2_init,
348 .map_io = kirkwood_map_io,
349 .init_irq = kirkwood_init_irq,
350 .timer = &netspace_v2_timer,
351MACHINE_END
352#endif
diff --git a/arch/arm/mach-kirkwood/netxbig_v2-setup.c b/arch/arm/mach-kirkwood/netxbig_v2-setup.c
index 8a2bb0228e4f..2bd14c5079de 100644
--- a/arch/arm/mach-kirkwood/netxbig_v2-setup.c
+++ b/arch/arm/mach-kirkwood/netxbig_v2-setup.c
@@ -270,8 +270,8 @@ static unsigned int net2big_v2_mpp_config[] __initdata = {
270 MPP3_SPI_MISO, 270 MPP3_SPI_MISO,
271 MPP6_SYSRST_OUTn, 271 MPP6_SYSRST_OUTn,
272 MPP7_GPO, /* Request power-off */ 272 MPP7_GPO, /* Request power-off */
273 MPP8_TW_SDA, 273 MPP8_TW0_SDA,
274 MPP9_TW_SCK, 274 MPP9_TW0_SCK,
275 MPP10_UART0_TXD, 275 MPP10_UART0_TXD,
276 MPP11_UART0_RXD, 276 MPP11_UART0_RXD,
277 MPP13_GPIO, /* Rear power switch (on|auto) */ 277 MPP13_GPIO, /* Rear power switch (on|auto) */
@@ -306,8 +306,8 @@ static unsigned int net5big_v2_mpp_config[] __initdata = {
306 MPP3_SPI_MISO, 306 MPP3_SPI_MISO,
307 MPP6_SYSRST_OUTn, 307 MPP6_SYSRST_OUTn,
308 MPP7_GPO, /* Request power-off */ 308 MPP7_GPO, /* Request power-off */
309 MPP8_TW_SDA, 309 MPP8_TW0_SDA,
310 MPP9_TW_SCK, 310 MPP9_TW0_SCK,
311 MPP10_UART0_TXD, 311 MPP10_UART0_TXD,
312 MPP11_UART0_RXD, 312 MPP11_UART0_RXD,
313 MPP13_GPIO, /* Rear power switch (on|auto) */ 313 MPP13_GPIO, /* Rear power switch (on|auto) */
@@ -315,20 +315,20 @@ static unsigned int net5big_v2_mpp_config[] __initdata = {
315 MPP15_GPIO, /* Rear power switch (auto|off) */ 315 MPP15_GPIO, /* Rear power switch (auto|off) */
316 MPP16_GPIO, /* SATA HDD1 power */ 316 MPP16_GPIO, /* SATA HDD1 power */
317 MPP17_GPIO, /* SATA HDD2 power */ 317 MPP17_GPIO, /* SATA HDD2 power */
318 MPP20_GE1_0, 318 MPP20_GE1_TXD0,
319 MPP21_GE1_1, 319 MPP21_GE1_TXD1,
320 MPP22_GE1_2, 320 MPP22_GE1_TXD2,
321 MPP23_GE1_3, 321 MPP23_GE1_TXD3,
322 MPP24_GE1_4, 322 MPP24_GE1_RXD0,
323 MPP25_GE1_5, 323 MPP25_GE1_RXD1,
324 MPP26_GE1_6, 324 MPP26_GE1_RXD2,
325 MPP27_GE1_7, 325 MPP27_GE1_RXD3,
326 MPP28_GPIO, /* USB enable host vbus */ 326 MPP28_GPIO, /* USB enable host vbus */
327 MPP29_GPIO, /* CPLD extension ALE */ 327 MPP29_GPIO, /* CPLD extension ALE */
328 MPP30_GE1_10, 328 MPP30_GE1_RXCTL,
329 MPP31_GE1_11, 329 MPP31_GE1_RXCLK,
330 MPP32_GE1_12, 330 MPP32_GE1_TCLKOUT,
331 MPP33_GE1_13, 331 MPP33_GE1_TXCTL,
332 MPP34_GPIO, /* Rear Push button */ 332 MPP34_GPIO, /* Rear Push button */
333 MPP35_GPIO, /* Inhibit switch power-off */ 333 MPP35_GPIO, /* Inhibit switch power-off */
334 MPP36_GPIO, /* SATA HDD1 presence */ 334 MPP36_GPIO, /* SATA HDD1 presence */
diff --git a/arch/arm/mach-kirkwood/openrd-setup.c b/arch/arm/mach-kirkwood/openrd-setup.c
index ad3f1ec33796..fd64cd2b4e0a 100644
--- a/arch/arm/mach-kirkwood/openrd-setup.c
+++ b/arch/arm/mach-kirkwood/openrd-setup.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * arch/arm/mach-kirkwood/openrd-setup.c 2 * arch/arm/mach-kirkwood/openrd-setup.c
3 * 3 *
4 * Marvell OpenRD (Base|Client) Board Setup 4 * Marvell OpenRD (Base|Client|Ultimate) Board Setup
5 * 5 *
6 * This file is licensed under the terms of the GNU General Public 6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any 7 * License version 2. This program is licensed "as is" without any
@@ -73,9 +73,15 @@ static void __init openrd_init(void)
73 73
74 kirkwood_ehci_init(); 74 kirkwood_ehci_init();
75 75
76 if (machine_is_openrd_ultimate()) {
77 openrd_ge00_data.phy_addr = MV643XX_ETH_PHY_ADDR(0);
78 openrd_ge01_data.phy_addr = MV643XX_ETH_PHY_ADDR(1);
79 }
80
76 kirkwood_ge00_init(&openrd_ge00_data); 81 kirkwood_ge00_init(&openrd_ge00_data);
77 if (machine_is_openrd_client()) 82 if (!machine_is_openrd_base())
78 kirkwood_ge01_init(&openrd_ge01_data); 83 kirkwood_ge01_init(&openrd_ge01_data);
84
79 kirkwood_sata_init(&openrd_sata_data); 85 kirkwood_sata_init(&openrd_sata_data);
80 kirkwood_sdio_init(&openrd_mvsdio_data); 86 kirkwood_sdio_init(&openrd_mvsdio_data);
81 87
@@ -84,8 +90,10 @@ static void __init openrd_init(void)
84 90
85static int __init openrd_pci_init(void) 91static int __init openrd_pci_init(void)
86{ 92{
87 if (machine_is_openrd_base() || machine_is_openrd_client()) 93 if (machine_is_openrd_base() ||
88 kirkwood_pcie_init(); 94 machine_is_openrd_client() ||
95 machine_is_openrd_ultimate())
96 kirkwood_pcie_init(KW_PCIE0);
89 97
90 return 0; 98 return 0;
91} 99}
@@ -116,3 +124,16 @@ MACHINE_START(OPENRD_CLIENT, "Marvell OpenRD Client Board")
116 .timer = &kirkwood_timer, 124 .timer = &kirkwood_timer,
117MACHINE_END 125MACHINE_END
118#endif 126#endif
127
128#ifdef CONFIG_MACH_OPENRD_ULTIMATE
129MACHINE_START(OPENRD_ULTIMATE, "Marvell OpenRD Ultimate Board")
130 /* Maintainer: Dhaval Vasa <dhaval.vasa@einfochips.com> */
131 .phys_io = KIRKWOOD_REGS_PHYS_BASE,
132 .io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
133 .boot_params = 0x00000100,
134 .init_machine = openrd_init,
135 .map_io = kirkwood_map_io,
136 .init_irq = kirkwood_init_irq,
137 .timer = &kirkwood_timer,
138MACHINE_END
139#endif
diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c
index dee1eff50d39..55e7f00836b7 100644
--- a/arch/arm/mach-kirkwood/pcie.c
+++ b/arch/arm/mach-kirkwood/pcie.c
@@ -18,29 +18,43 @@
18#include <mach/bridge-regs.h> 18#include <mach/bridge-regs.h>
19#include "common.h" 19#include "common.h"
20 20
21void __init kirkwood_pcie_id(u32 *dev, u32 *rev)
22{
23 *dev = orion_pcie_dev_id((void __iomem *)PCIE_VIRT_BASE);
24 *rev = orion_pcie_rev((void __iomem *)PCIE_VIRT_BASE);
25}
21 26
22#define PCIE_BASE ((void __iomem *)PCIE_VIRT_BASE) 27struct pcie_port {
28 u8 root_bus_nr;
29 void __iomem *base;
30 spinlock_t conf_lock;
31 int irq;
32 struct resource res[2];
33};
23 34
24void __init kirkwood_pcie_id(u32 *dev, u32 *rev) 35static int pcie_port_map[2];
36static int num_pcie_ports;
37
38static inline struct pcie_port *bus_to_port(struct pci_bus *bus)
25{ 39{
26 *dev = orion_pcie_dev_id(PCIE_BASE); 40 struct pci_sys_data *sys = bus->sysdata;
27 *rev = orion_pcie_rev(PCIE_BASE); 41 return sys->private_data;
28} 42}
29 43
30static int pcie_valid_config(int bus, int dev) 44static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
31{ 45{
32 /* 46 /*
33 * Don't go out when trying to access -- 47 * Don't go out when trying to access --
34 * 1. nonexisting device on local bus 48 * 1. nonexisting device on local bus
35 * 2. where there's no device connected (no link) 49 * 2. where there's no device connected (no link)
36 */ 50 */
37 if (bus == 0 && dev == 0) 51 if (bus == pp->root_bus_nr && dev == 0)
38 return 1; 52 return 1;
39 53
40 if (!orion_pcie_link_up(PCIE_BASE)) 54 if (!orion_pcie_link_up(pp->base))
41 return 0; 55 return 0;
42 56
43 if (bus == 0 && dev != 1) 57 if (bus == pp->root_bus_nr && dev != 1)
44 return 0; 58 return 0;
45 59
46 return 1; 60 return 1;
@@ -52,22 +66,22 @@ static int pcie_valid_config(int bus, int dev)
52 * and then reading the PCIE_CONF_DATA register. Need to make sure these 66 * and then reading the PCIE_CONF_DATA register. Need to make sure these
53 * transactions are atomic. 67 * transactions are atomic.
54 */ 68 */
55static DEFINE_SPINLOCK(kirkwood_pcie_lock);
56 69
57static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, 70static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
58 int size, u32 *val) 71 int size, u32 *val)
59{ 72{
73 struct pcie_port *pp = bus_to_port(bus);
60 unsigned long flags; 74 unsigned long flags;
61 int ret; 75 int ret;
62 76
63 if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) { 77 if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) {
64 *val = 0xffffffff; 78 *val = 0xffffffff;
65 return PCIBIOS_DEVICE_NOT_FOUND; 79 return PCIBIOS_DEVICE_NOT_FOUND;
66 } 80 }
67 81
68 spin_lock_irqsave(&kirkwood_pcie_lock, flags); 82 spin_lock_irqsave(&pp->conf_lock, flags);
69 ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val); 83 ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val);
70 spin_unlock_irqrestore(&kirkwood_pcie_lock, flags); 84 spin_unlock_irqrestore(&pp->conf_lock, flags);
71 85
72 return ret; 86 return ret;
73} 87}
@@ -75,15 +89,16 @@ static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
75static int pcie_wr_conf(struct pci_bus *bus, u32 devfn, 89static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
76 int where, int size, u32 val) 90 int where, int size, u32 val)
77{ 91{
92 struct pcie_port *pp = bus_to_port(bus);
78 unsigned long flags; 93 unsigned long flags;
79 int ret; 94 int ret;
80 95
81 if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) 96 if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0)
82 return PCIBIOS_DEVICE_NOT_FOUND; 97 return PCIBIOS_DEVICE_NOT_FOUND;
83 98
84 spin_lock_irqsave(&kirkwood_pcie_lock, flags); 99 spin_lock_irqsave(&pp->conf_lock, flags);
85 ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val); 100 ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val);
86 spin_unlock_irqrestore(&kirkwood_pcie_lock, flags); 101 spin_unlock_irqrestore(&pp->conf_lock, flags);
87 102
88 return ret; 103 return ret;
89} 104}
@@ -93,50 +108,98 @@ static struct pci_ops pcie_ops = {
93 .write = pcie_wr_conf, 108 .write = pcie_wr_conf,
94}; 109};
95 110
96 111static void __init pcie0_ioresources_init(struct pcie_port *pp)
97static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
98{ 112{
99 struct resource *res; 113 pp->base = (void __iomem *)PCIE_VIRT_BASE;
100 extern unsigned int kirkwood_clk_ctrl; 114 pp->irq = IRQ_KIRKWOOD_PCIE;
101 115
102 /* 116 /*
103 * Generic PCIe unit setup. 117 * IORESOURCE_IO
104 */ 118 */
105 orion_pcie_setup(PCIE_BASE, &kirkwood_mbus_dram_info); 119 pp->res[0].name = "PCIe 0 I/O Space";
120 pp->res[0].start = KIRKWOOD_PCIE_IO_PHYS_BASE;
121 pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1;
122 pp->res[0].flags = IORESOURCE_IO;
106 123
107 /* 124 /*
108 * Request resources. 125 * IORESOURCE_MEM
109 */ 126 */
110 res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); 127 pp->res[1].name = "PCIe 0 MEM";
111 if (!res) 128 pp->res[1].start = KIRKWOOD_PCIE_MEM_PHYS_BASE;
112 panic("pcie_setup unable to alloc resources"); 129 pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE_MEM_SIZE - 1;
130 pp->res[1].flags = IORESOURCE_MEM;
131}
132
133static void __init pcie1_ioresources_init(struct pcie_port *pp)
134{
135 pp->base = (void __iomem *)PCIE1_VIRT_BASE;
136 pp->irq = IRQ_KIRKWOOD_PCIE1;
113 137
114 /* 138 /*
115 * IORESOURCE_IO 139 * IORESOURCE_IO
116 */ 140 */
117 res[0].name = "PCIe I/O Space"; 141 pp->res[0].name = "PCIe 1 I/O Space";
118 res[0].flags = IORESOURCE_IO; 142 pp->res[0].start = KIRKWOOD_PCIE1_IO_PHYS_BASE;
119 res[0].start = KIRKWOOD_PCIE_IO_BUS_BASE; 143 pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE1_IO_SIZE - 1;
120 res[0].end = res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1; 144 pp->res[0].flags = IORESOURCE_IO;
121 if (request_resource(&ioport_resource, &res[0]))
122 panic("Request PCIe IO resource failed\n");
123 sys->resource[0] = &res[0];
124 145
125 /* 146 /*
126 * IORESOURCE_MEM 147 * IORESOURCE_MEM
127 */ 148 */
128 res[1].name = "PCIe Memory Space"; 149 pp->res[1].name = "PCIe 1 MEM";
129 res[1].flags = IORESOURCE_MEM; 150 pp->res[1].start = KIRKWOOD_PCIE1_MEM_PHYS_BASE;
130 res[1].start = KIRKWOOD_PCIE_MEM_BUS_BASE; 151 pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE1_MEM_SIZE - 1;
131 res[1].end = res[1].start + KIRKWOOD_PCIE_MEM_SIZE - 1; 152 pp->res[1].flags = IORESOURCE_MEM;
132 if (request_resource(&iomem_resource, &res[1])) 153}
133 panic("Request PCIe Memory resource failed\n"); 154
134 sys->resource[1] = &res[1]; 155static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
156{
157 extern unsigned int kirkwood_clk_ctrl;
158 struct pcie_port *pp;
159 int index;
135 160
161 if (nr >= num_pcie_ports)
162 return 0;
163
164 index = pcie_port_map[nr];
165 printk(KERN_INFO "PCI: bus%d uses PCIe port %d\n", sys->busnr, index);
166
167 pp = kzalloc(sizeof(*pp), GFP_KERNEL);
168 if (!pp)
169 panic("PCIe: failed to allocate pcie_port data");
170 sys->private_data = pp;
171 pp->root_bus_nr = sys->busnr;
172 spin_lock_init(&pp->conf_lock);
173
174 switch (index) {
175 case 0:
176 kirkwood_clk_ctrl |= CGC_PEX0;
177 pcie0_ioresources_init(pp);
178 break;
179 case 1:
180 kirkwood_clk_ctrl |= CGC_PEX1;
181 pcie1_ioresources_init(pp);
182 break;
183 default:
184 panic("PCIe setup: invalid controller %d", index);
185 }
186
187 if (request_resource(&ioport_resource, &pp->res[0]))
188 panic("Request PCIe%d IO resource failed\n", index);
189 if (request_resource(&iomem_resource, &pp->res[1]))
190 panic("Request PCIe%d Memory resource failed\n", index);
191
192 sys->resource[0] = &pp->res[0];
193 sys->resource[1] = &pp->res[1];
136 sys->resource[2] = NULL; 194 sys->resource[2] = NULL;
137 sys->io_offset = 0; 195 sys->io_offset = 0;
138 196
139 kirkwood_clk_ctrl |= CGC_PEX0; 197 /*
198 * Generic PCIe unit setup.
199 */
200 orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
201
202 orion_pcie_setup(pp->base, &kirkwood_mbus_dram_info);
140 203
141 return 1; 204 return 1;
142} 205}
@@ -163,7 +226,7 @@ kirkwood_pcie_scan_bus(int nr, struct pci_sys_data *sys)
163{ 226{
164 struct pci_bus *bus; 227 struct pci_bus *bus;
165 228
166 if (nr == 0) { 229 if (nr < num_pcie_ports) {
167 bus = pci_scan_bus(sys->busnr, &pcie_ops, sys); 230 bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
168 } else { 231 } else {
169 bus = NULL; 232 bus = NULL;
@@ -175,18 +238,37 @@ kirkwood_pcie_scan_bus(int nr, struct pci_sys_data *sys)
175 238
176static int __init kirkwood_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 239static int __init kirkwood_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
177{ 240{
178 return IRQ_KIRKWOOD_PCIE; 241 struct pcie_port *pp = bus_to_port(dev->bus);
242
243 return pp->irq;
179} 244}
180 245
181static struct hw_pci kirkwood_pci __initdata = { 246static struct hw_pci kirkwood_pci __initdata = {
182 .nr_controllers = 1,
183 .swizzle = pci_std_swizzle, 247 .swizzle = pci_std_swizzle,
184 .setup = kirkwood_pcie_setup, 248 .setup = kirkwood_pcie_setup,
185 .scan = kirkwood_pcie_scan_bus, 249 .scan = kirkwood_pcie_scan_bus,
186 .map_irq = kirkwood_pcie_map_irq, 250 .map_irq = kirkwood_pcie_map_irq,
187}; 251};
188 252
189void __init kirkwood_pcie_init(void) 253static void __init add_pcie_port(int index, unsigned long base)
190{ 254{
255 printk(KERN_INFO "Kirkwood PCIe port %d: ", index);
256
257 if (orion_pcie_link_up((void __iomem *)base)) {
258 printk(KERN_INFO "link up\n");
259 pcie_port_map[num_pcie_ports++] = index;
260 } else
261 printk(KERN_INFO "link down, ignoring\n");
262}
263
264void __init kirkwood_pcie_init(unsigned int portmask)
265{
266 if (portmask & KW_PCIE0)
267 add_pcie_port(0, PCIE_VIRT_BASE);
268
269 if (portmask & KW_PCIE1)
270 add_pcie_port(1, PCIE1_VIRT_BASE);
271
272 kirkwood_pci.nr_controllers = num_pcie_ports;
191 pci_common_init(&kirkwood_pci); 273 pci_common_init(&kirkwood_pci);
192} 274}
diff --git a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
index 3bf6304158f6..c34718c2cfe5 100644
--- a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
+++ b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
@@ -71,7 +71,7 @@ static void __init rd88f6192_init(void)
71static int __init rd88f6192_pci_init(void) 71static int __init rd88f6192_pci_init(void)
72{ 72{
73 if (machine_is_rd88f6192_nas()) 73 if (machine_is_rd88f6192_nas())
74 kirkwood_pcie_init(); 74 kirkwood_pcie_init(KW_PCIE0);
75 75
76 return 0; 76 return 0;
77} 77}
diff --git a/arch/arm/mach-kirkwood/rd88f6281-setup.c b/arch/arm/mach-kirkwood/rd88f6281-setup.c
index 31708ddbc83e..3d1477135e12 100644
--- a/arch/arm/mach-kirkwood/rd88f6281-setup.c
+++ b/arch/arm/mach-kirkwood/rd88f6281-setup.c
@@ -107,7 +107,7 @@ static void __init rd88f6281_init(void)
107static int __init rd88f6281_pci_init(void) 107static int __init rd88f6281_pci_init(void)
108{ 108{
109 if (machine_is_rd88f6281()) 109 if (machine_is_rd88f6281())
110 kirkwood_pcie_init(); 110 kirkwood_pcie_init(KW_PCIE0);
111 111
112 return 0; 112 return 0;
113} 113}
diff --git a/arch/arm/mach-kirkwood/t5325-setup.c b/arch/arm/mach-kirkwood/t5325-setup.c
new file mode 100644
index 000000000000..d01bf89cedbe
--- /dev/null
+++ b/arch/arm/mach-kirkwood/t5325-setup.c
@@ -0,0 +1,194 @@
1/*
2 *
3 * HP t5325 Thin Client setup
4 *
5 * Copyright (C) 2010 Martin Michlmayr <tbm@cyrius.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
12
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/platform_device.h>
16#include <linux/mtd/physmap.h>
17#include <linux/spi/flash.h>
18#include <linux/spi/spi.h>
19#include <linux/spi/orion_spi.h>
20#include <linux/i2c.h>
21#include <linux/mv643xx_eth.h>
22#include <linux/ata_platform.h>
23#include <linux/gpio.h>
24#include <linux/gpio_keys.h>
25#include <linux/input.h>
26#include <asm/mach-types.h>
27#include <asm/mach/arch.h>
28#include <mach/kirkwood.h>
29#include "common.h"
30#include "mpp.h"
31
32struct mtd_partition hp_t5325_partitions[] = {
33 {
34 .name = "u-boot env",
35 .size = SZ_64K,
36 .offset = SZ_512K + SZ_256K,
37 },
38 {
39 .name = "permanent u-boot env",
40 .size = SZ_64K,
41 .offset = MTDPART_OFS_APPEND,
42 .mask_flags = MTD_WRITEABLE,
43 },
44 {
45 .name = "HP env",
46 .size = SZ_64K,
47 .offset = MTDPART_OFS_APPEND,
48 },
49 {
50 .name = "u-boot",
51 .size = SZ_512K,
52 .offset = 0,
53 .mask_flags = MTD_WRITEABLE,
54 },
55 {
56 .name = "SSD firmware",
57 .size = SZ_256K,
58 .offset = SZ_512K,
59 },
60};
61
62const struct flash_platform_data hp_t5325_flash = {
63 .type = "mx25l8005",
64 .name = "spi_flash",
65 .parts = hp_t5325_partitions,
66 .nr_parts = ARRAY_SIZE(hp_t5325_partitions),
67};
68
69struct spi_board_info __initdata hp_t5325_spi_slave_info[] = {
70 {
71 .modalias = "m25p80",
72 .platform_data = &hp_t5325_flash,
73 .irq = -1,
74 },
75};
76
77static struct mv643xx_eth_platform_data hp_t5325_ge00_data = {
78 .phy_addr = MV643XX_ETH_PHY_ADDR(8),
79};
80
81static struct mv_sata_platform_data hp_t5325_sata_data = {
82 .n_ports = 2,
83};
84
85static struct gpio_keys_button hp_t5325_buttons[] = {
86 {
87 .code = KEY_POWER,
88 .gpio = 45,
89 .desc = "Power",
90 .active_low = 1,
91 },
92};
93
94static struct gpio_keys_platform_data hp_t5325_button_data = {
95 .buttons = hp_t5325_buttons,
96 .nbuttons = ARRAY_SIZE(hp_t5325_buttons),
97};
98
99static struct platform_device hp_t5325_button_device = {
100 .name = "gpio-keys",
101 .id = -1,
102 .num_resources = 0,
103 .dev = {
104 .platform_data = &hp_t5325_button_data,
105 }
106};
107
108static unsigned int hp_t5325_mpp_config[] __initdata = {
109 MPP0_NF_IO2,
110 MPP1_SPI_MOSI,
111 MPP2_SPI_SCK,
112 MPP3_SPI_MISO,
113 MPP4_NF_IO6,
114 MPP5_NF_IO7,
115 MPP6_SYSRST_OUTn,
116 MPP7_SPI_SCn,
117 MPP8_TW0_SDA,
118 MPP9_TW0_SCK,
119 MPP10_UART0_TXD,
120 MPP11_UART0_RXD,
121 MPP12_SD_CLK,
122 MPP13_GPIO,
123 MPP14_GPIO,
124 MPP15_GPIO,
125 MPP16_GPIO,
126 MPP17_GPIO,
127 MPP18_NF_IO0,
128 MPP19_NF_IO1,
129 MPP20_GPIO,
130 MPP21_GPIO,
131 MPP22_GPIO,
132 MPP23_GPIO,
133 MPP32_GPIO,
134 MPP33_GE1_TXCTL,
135 MPP39_AU_I2SBCLK,
136 MPP40_AU_I2SDO,
137 MPP41_AU_I2SLRCLK,
138 MPP42_AU_I2SMCLK,
139 MPP45_GPIO, /* Power button */
140 MPP48_GPIO, /* Board power off */
141 0
142};
143
144#define HP_T5325_GPIO_POWER_OFF 48
145
146static void hp_t5325_power_off(void)
147{
148 gpio_set_value(HP_T5325_GPIO_POWER_OFF, 1);
149}
150
151static void __init hp_t5325_init(void)
152{
153 /*
154 * Basic setup. Needs to be called early.
155 */
156 kirkwood_init();
157 kirkwood_mpp_conf(hp_t5325_mpp_config);
158
159 kirkwood_uart0_init();
160 spi_register_board_info(hp_t5325_spi_slave_info,
161 ARRAY_SIZE(hp_t5325_spi_slave_info));
162 kirkwood_spi_init();
163 kirkwood_i2c_init();
164 kirkwood_ge00_init(&hp_t5325_ge00_data);
165 kirkwood_sata_init(&hp_t5325_sata_data);
166 kirkwood_ehci_init();
167 platform_device_register(&hp_t5325_button_device);
168
169 if (gpio_request(HP_T5325_GPIO_POWER_OFF, "power-off") == 0 &&
170 gpio_direction_output(HP_T5325_GPIO_POWER_OFF, 0) == 0)
171 pm_power_off = hp_t5325_power_off;
172 else
173 pr_err("t5325: failed to configure power-off GPIO\n");
174}
175
176static int __init hp_t5325_pci_init(void)
177{
178 if (machine_is_t5325())
179 kirkwood_pcie_init(KW_PCIE0);
180
181 return 0;
182}
183subsys_initcall(hp_t5325_pci_init);
184
185MACHINE_START(T5325, "HP t5325 Thin Client")
186 /* Maintainer: Martin Michlmayr <tbm@cyrius.com> */
187 .phys_io = KIRKWOOD_REGS_PHYS_BASE,
188 .io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
189 .boot_params = 0x00000100,
190 .init_machine = hp_t5325_init,
191 .map_io = kirkwood_map_io,
192 .init_irq = kirkwood_init_irq,
193 .timer = &kirkwood_timer,
194MACHINE_END
diff --git a/arch/arm/mach-kirkwood/ts219-setup.c b/arch/arm/mach-kirkwood/ts219-setup.c
index 2830f0fe80e0..a5bd7fde04a9 100644
--- a/arch/arm/mach-kirkwood/ts219-setup.c
+++ b/arch/arm/mach-kirkwood/ts219-setup.c
@@ -74,8 +74,8 @@ static unsigned int qnap_ts219_mpp_config[] __initdata = {
74 MPP3_SPI_MISO, 74 MPP3_SPI_MISO,
75 MPP4_SATA1_ACTn, 75 MPP4_SATA1_ACTn,
76 MPP5_SATA0_ACTn, 76 MPP5_SATA0_ACTn,
77 MPP8_TW_SDA, 77 MPP8_TW0_SDA,
78 MPP9_TW_SCK, 78 MPP9_TW0_SCK,
79 MPP10_UART0_TXD, 79 MPP10_UART0_TXD,
80 MPP11_UART0_RXD, 80 MPP11_UART0_RXD,
81 MPP13_UART1_TXD, /* PIC controller */ 81 MPP13_UART1_TXD, /* PIC controller */
@@ -83,6 +83,7 @@ static unsigned int qnap_ts219_mpp_config[] __initdata = {
83 MPP15_GPIO, /* USB Copy button */ 83 MPP15_GPIO, /* USB Copy button */
84 MPP16_GPIO, /* Reset button */ 84 MPP16_GPIO, /* Reset button */
85 MPP36_GPIO, /* RAM: 0: 256 MB, 1: 512 MB */ 85 MPP36_GPIO, /* RAM: 0: 256 MB, 1: 512 MB */
86 MPP44_GPIO, /* Board ID: 0: TS-11x, 1: TS-21x */
86 0 87 0
87}; 88};
88 89
@@ -110,10 +111,10 @@ static void __init qnap_ts219_init(void)
110 111
111static int __init ts219_pci_init(void) 112static int __init ts219_pci_init(void)
112{ 113{
113 if (machine_is_ts219()) 114 if (machine_is_ts219())
114 kirkwood_pcie_init(); 115 kirkwood_pcie_init(KW_PCIE0);
115 116
116 return 0; 117 return 0;
117} 118}
118subsys_initcall(ts219_pci_init); 119subsys_initcall(ts219_pci_init);
119 120
diff --git a/arch/arm/mach-kirkwood/ts41x-setup.c b/arch/arm/mach-kirkwood/ts41x-setup.c
index de49c2d9e74b..2e14afef07a2 100644
--- a/arch/arm/mach-kirkwood/ts41x-setup.c
+++ b/arch/arm/mach-kirkwood/ts41x-setup.c
@@ -2,7 +2,7 @@
2 * 2 *
3 * QNAP TS-410, TS-410U, TS-419P and TS-419U Turbo NAS Board Setup 3 * QNAP TS-410, TS-410U, TS-419P and TS-419U Turbo NAS Board Setup
4 * 4 *
5 * Copyright (C) 2009 Martin Michlmayr <tbm@cyrius.com> 5 * Copyright (C) 2009-2010 Martin Michlmayr <tbm@cyrius.com>
6 * Copyright (C) 2008 Byron Bradley <byron.bbradley@gmail.com> 6 * Copyright (C) 2008 Byron Bradley <byron.bbradley@gmail.com>
7 * 7 *
8 * This program is free software; you can redistribute it and/or 8 * This program is free software; you can redistribute it and/or
@@ -17,6 +17,7 @@
17#include <linux/i2c.h> 17#include <linux/i2c.h>
18#include <linux/mv643xx_eth.h> 18#include <linux/mv643xx_eth.h>
19#include <linux/ata_platform.h> 19#include <linux/ata_platform.h>
20#include <linux/gpio.h>
20#include <linux/gpio_keys.h> 21#include <linux/gpio_keys.h>
21#include <linux/input.h> 22#include <linux/input.h>
22#include <asm/mach-types.h> 23#include <asm/mach-types.h>
@@ -26,6 +27,8 @@
26#include "mpp.h" 27#include "mpp.h"
27#include "tsx1x-common.h" 28#include "tsx1x-common.h"
28 29
30#define QNAP_TS41X_JUMPER_JP1 45
31
29static struct i2c_board_info __initdata qnap_ts41x_i2c_rtc = { 32static struct i2c_board_info __initdata qnap_ts41x_i2c_rtc = {
30 I2C_BOARD_INFO("s35390a", 0x30), 33 I2C_BOARD_INFO("s35390a", 0x30),
31}; 34};
@@ -78,31 +81,31 @@ static unsigned int qnap_ts41x_mpp_config[] __initdata = {
78 MPP3_SPI_MISO, 81 MPP3_SPI_MISO,
79 MPP6_SYSRST_OUTn, 82 MPP6_SYSRST_OUTn,
80 MPP7_PEX_RST_OUTn, 83 MPP7_PEX_RST_OUTn,
81 MPP8_TW_SDA, 84 MPP8_TW0_SDA,
82 MPP9_TW_SCK, 85 MPP9_TW0_SCK,
83 MPP10_UART0_TXD, 86 MPP10_UART0_TXD,
84 MPP11_UART0_RXD, 87 MPP11_UART0_RXD,
85 MPP13_UART1_TXD, /* PIC controller */ 88 MPP13_UART1_TXD, /* PIC controller */
86 MPP14_UART1_RXD, /* PIC controller */ 89 MPP14_UART1_RXD, /* PIC controller */
87 MPP15_SATA0_ACTn, 90 MPP15_SATA0_ACTn,
88 MPP16_SATA1_ACTn, 91 MPP16_SATA1_ACTn,
89 MPP20_GE1_0, 92 MPP20_GE1_TXD0,
90 MPP21_GE1_1, 93 MPP21_GE1_TXD1,
91 MPP22_GE1_2, 94 MPP22_GE1_TXD2,
92 MPP23_GE1_3, 95 MPP23_GE1_TXD3,
93 MPP24_GE1_4, 96 MPP24_GE1_RXD0,
94 MPP25_GE1_5, 97 MPP25_GE1_RXD1,
95 MPP26_GE1_6, 98 MPP26_GE1_RXD2,
96 MPP27_GE1_7, 99 MPP27_GE1_RXD3,
97 MPP30_GE1_10, 100 MPP30_GE1_RXCTL,
98 MPP31_GE1_11, 101 MPP31_GE1_RXCLK,
99 MPP32_GE1_12, 102 MPP32_GE1_TCLKOUT,
100 MPP33_GE1_13, 103 MPP33_GE1_TXCTL,
101 MPP36_GPIO, /* RAM: 0: 256 MB, 1: 512 MB */ 104 MPP36_GPIO, /* RAM: 0: 256 MB, 1: 512 MB */
102 MPP37_GPIO, /* Reset button */ 105 MPP37_GPIO, /* Reset button */
103 MPP43_GPIO, /* USB Copy button */ 106 MPP43_GPIO, /* USB Copy button */
104 MPP44_GPIO, /* Board ID: 0: TS-419U, 1: TS-419 */ 107 MPP44_GPIO, /* Board ID: 0: TS-419U, 1: TS-419 */
105 MPP45_GPIO, /* JP1: 0: console, 1: LCD */ 108 MPP45_GPIO, /* JP1: 0: LCD, 1: serial console */
106 MPP46_GPIO, /* External SATA HDD1 error indicator */ 109 MPP46_GPIO, /* External SATA HDD1 error indicator */
107 MPP47_GPIO, /* External SATA HDD2 error indicator */ 110 MPP47_GPIO, /* External SATA HDD2 error indicator */
108 MPP48_GPIO, /* External SATA HDD3 error indicator */ 111 MPP48_GPIO, /* External SATA HDD3 error indicator */
@@ -131,12 +134,14 @@ static void __init qnap_ts41x_init(void)
131 134
132 pm_power_off = qnap_tsx1x_power_off; 135 pm_power_off = qnap_tsx1x_power_off;
133 136
137 if (gpio_request(QNAP_TS41X_JUMPER_JP1, "JP1") == 0)
138 gpio_export(QNAP_TS41X_JUMPER_JP1, 0);
134} 139}
135 140
136static int __init ts41x_pci_init(void) 141static int __init ts41x_pci_init(void)
137{ 142{
138 if (machine_is_ts41x()) 143 if (machine_is_ts41x())
139 kirkwood_pcie_init(); 144 kirkwood_pcie_init(KW_PCIE0);
140 145
141 return 0; 146 return 0;
142} 147}
diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index 66677f0acaed..7ff8020d4d24 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -15,7 +15,7 @@ obj-$(CONFIG_ARCH_QSD8X50) += sirc.o
15obj-$(CONFIG_MSM_SMD) += smd.o smd_debug.o 15obj-$(CONFIG_MSM_SMD) += smd.o smd_debug.o
16obj-$(CONFIG_MSM_SMD) += last_radio_log.o 16obj-$(CONFIG_MSM_SMD) += last_radio_log.o
17 17
18obj-$(CONFIG_MACH_TROUT) += board-trout.o devices-msm7x00.o 18obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o devices-msm7x00.o
19obj-$(CONFIG_MACH_HALIBUT) += board-halibut.o devices-msm7x00.o 19obj-$(CONFIG_MACH_HALIBUT) += board-halibut.o devices-msm7x00.o
20obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o 20obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o
21obj-$(CONFIG_ARCH_QSD8X50) += board-qsd8x50.o devices-qsd8x50.o 21obj-$(CONFIG_ARCH_QSD8X50) += board-qsd8x50.o devices-qsd8x50.o
diff --git a/arch/arm/mach-msm/board-trout-gpio.c b/arch/arm/mach-msm/board-trout-gpio.c
new file mode 100644
index 000000000000..523d213bf79e
--- /dev/null
+++ b/arch/arm/mach-msm/board-trout-gpio.c
@@ -0,0 +1,112 @@
1/*
2 * linux/arch/arm/mach-msm/gpio.c
3 *
4 * Copyright (C) 2005 HP Labs
5 * Copyright (C) 2008 Google, Inc.
6 * Copyright (C) 2009 Pavel Machek <pavel@ucw.cz>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/io.h>
17#include <linux/irq.h>
18#include <linux/gpio.h>
19
20#include "board-trout.h"
21
22struct msm_gpio_chip {
23 struct gpio_chip chip;
24 void __iomem *reg; /* Base of register bank */
25 u8 shadow;
26};
27
28#define to_msm_gpio_chip(c) container_of(c, struct msm_gpio_chip, chip)
29
30static int msm_gpiolib_get(struct gpio_chip *chip, unsigned offset)
31{
32 struct msm_gpio_chip *msm_gpio = to_msm_gpio_chip(chip);
33 unsigned mask = 1 << offset;
34
35 return !!(readb(msm_gpio->reg) & mask);
36}
37
38static void msm_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val)
39{
40 struct msm_gpio_chip *msm_gpio = to_msm_gpio_chip(chip);
41 unsigned mask = 1 << offset;
42
43 if (val)
44 msm_gpio->shadow |= mask;
45 else
46 msm_gpio->shadow &= ~mask;
47
48 writeb(msm_gpio->shadow, msm_gpio->reg);
49}
50
51static int msm_gpiolib_direction_input(struct gpio_chip *chip,
52 unsigned offset)
53{
54 msm_gpiolib_set(chip, offset, 0);
55 return 0;
56}
57
58static int msm_gpiolib_direction_output(struct gpio_chip *chip,
59 unsigned offset, int val)
60{
61 msm_gpiolib_set(chip, offset, val);
62 return 0;
63}
64
65#define TROUT_GPIO_BANK(name, reg_num, base_gpio, shadow_val) \
66 { \
67 .chip = { \
68 .label = name, \
69 .direction_input = msm_gpiolib_direction_input,\
70 .direction_output = msm_gpiolib_direction_output, \
71 .get = msm_gpiolib_get, \
72 .set = msm_gpiolib_set, \
73 .base = base_gpio, \
74 .ngpio = 8, \
75 }, \
76 .reg = (void *) reg_num + TROUT_CPLD_BASE, \
77 .shadow = shadow_val, \
78 }
79
80static struct msm_gpio_chip msm_gpio_banks[] = {
81#if defined(CONFIG_MSM_DEBUG_UART1)
82 /* H2W pins <-> UART1 */
83 TROUT_GPIO_BANK("MISC2", 0x00, TROUT_GPIO_MISC2_BASE, 0x40),
84#else
85 /* H2W pins <-> UART3, Bluetooth <-> UART1 */
86 TROUT_GPIO_BANK("MISC2", 0x00, TROUT_GPIO_MISC2_BASE, 0x80),
87#endif
88 /* I2C pull */
89 TROUT_GPIO_BANK("MISC3", 0x02, TROUT_GPIO_MISC3_BASE, 0x04),
90 TROUT_GPIO_BANK("MISC4", 0x04, TROUT_GPIO_MISC4_BASE, 0),
91 /* mmdi 32k en */
92 TROUT_GPIO_BANK("MISC5", 0x06, TROUT_GPIO_MISC5_BASE, 0x04),
93 TROUT_GPIO_BANK("INT2", 0x08, TROUT_GPIO_INT2_BASE, 0),
94 TROUT_GPIO_BANK("MISC1", 0x0a, TROUT_GPIO_MISC1_BASE, 0),
95 TROUT_GPIO_BANK("VIRTUAL", 0x12, TROUT_GPIO_VIRTUAL_BASE, 0),
96};
97
98/*
99 * Called from the processor-specific init to enable GPIO pin support.
100 */
101int __init trout_init_gpio(void)
102{
103 int i;
104
105 for (i = 0; i < ARRAY_SIZE(msm_gpio_banks); i++)
106 gpiochip_add(&msm_gpio_banks[i].chip);
107
108 return 0;
109}
110
111postcore_initcall(trout_init_gpio);
112
diff --git a/arch/arm/mach-msm/board-trout.h b/arch/arm/mach-msm/board-trout.h
index 4f345a5a0a61..651851c3e1dd 100644
--- a/arch/arm/mach-msm/board-trout.h
+++ b/arch/arm/mach-msm/board-trout.h
@@ -1,5 +1,162 @@
1/* linux/arch/arm/mach-msm/board-trout.h
2** Author: Brian Swetland <swetland@google.com>
3*/
4#ifndef __ARCH_ARM_MACH_MSM_BOARD_TROUT_H
5#define __ARCH_ARM_MACH_MSM_BOARD_TROUT_H
6
7#include <mach/board.h>
8
9#define MSM_SMI_BASE 0x00000000
10#define MSM_SMI_SIZE 0x00800000
11
12#define MSM_EBI_BASE 0x10000000
13#define MSM_EBI_SIZE 0x06e00000
14
15#define MSM_PMEM_GPU0_BASE 0x00000000
16#define MSM_PMEM_GPU0_SIZE 0x00700000
17
18#define MSM_PMEM_MDP_BASE 0x02000000
19#define MSM_PMEM_MDP_SIZE 0x00800000
20
21#define MSM_PMEM_ADSP_BASE 0x02800000
22#define MSM_PMEM_ADSP_SIZE 0x00800000
23
24#define MSM_PMEM_CAMERA_BASE 0x03000000
25#define MSM_PMEM_CAMERA_SIZE 0x00800000
26
27#define MSM_FB_BASE 0x03800000
28#define MSM_FB_SIZE 0x00100000
29
30#define MSM_LINUX_BASE MSM_EBI_BASE
31#define MSM_LINUX_SIZE 0x06500000
32
33#define MSM_PMEM_GPU1_SIZE 0x800000
34#define MSM_PMEM_GPU1_BASE (MSM_RAM_CONSOLE_BASE - MSM_PMEM_GPU1_SIZE)
35
36#define MSM_RAM_CONSOLE_BASE (MSM_EBI_BASE + 0x6d00000)
37#define MSM_RAM_CONSOLE_SIZE (128 * SZ_1K)
38
39#if (MSM_FB_BASE + MSM_FB_SIZE) >= (MSM_PMEM_GPU1_BASE)
40#error invalid memory map
41#endif
42
43#define DECLARE_MSM_IOMAP
44#include <mach/msm_iomap.h>
45
46#define TROUT_4_BALL_UP_0 1
47#define TROUT_4_BALL_LEFT_0 18
48#define TROUT_4_BALL_DOWN_0 57
49#define TROUT_4_BALL_RIGHT_0 91
50
51#define TROUT_5_BALL_UP_0 94
52#define TROUT_5_BALL_LEFT_0 18
53#define TROUT_5_BALL_DOWN_0 90
54#define TROUT_5_BALL_RIGHT_0 19
55
56#define TROUT_POWER_KEY 20
57
58#define TROUT_4_TP_LS_EN 19
59#define TROUT_5_TP_LS_EN 1
1 60
2#define TROUT_CPLD_BASE 0xE8100000 61#define TROUT_CPLD_BASE 0xE8100000
3#define TROUT_CPLD_START 0x98000000 62#define TROUT_CPLD_START 0x98000000
4#define TROUT_CPLD_SIZE SZ_4K 63#define TROUT_CPLD_SIZE SZ_4K
5 64
65#define TROUT_GPIO_CABLE_IN1 (83)
66#define TROUT_GPIO_CABLE_IN2 (49)
67
68#define TROUT_GPIO_START (128)
69
70#define TROUT_GPIO_INT_MASK0_REG (0x0c)
71#define TROUT_GPIO_INT_STAT0_REG (0x0e)
72#define TROUT_GPIO_INT_MASK1_REG (0x14)
73#define TROUT_GPIO_INT_STAT1_REG (0x10)
74
75#define TROUT_GPIO_HAPTIC_PWM (28)
76#define TROUT_GPIO_PS_HOLD (25)
77
78#define TROUT_GPIO_MISC2_BASE (TROUT_GPIO_START + 0x00)
79#define TROUT_GPIO_MISC3_BASE (TROUT_GPIO_START + 0x08)
80#define TROUT_GPIO_MISC4_BASE (TROUT_GPIO_START + 0x10)
81#define TROUT_GPIO_MISC5_BASE (TROUT_GPIO_START + 0x18)
82#define TROUT_GPIO_INT2_BASE (TROUT_GPIO_START + 0x20)
83#define TROUT_GPIO_MISC1_BASE (TROUT_GPIO_START + 0x28)
84#define TROUT_GPIO_VIRTUAL_BASE (TROUT_GPIO_START + 0x30)
85#define TROUT_GPIO_INT5_BASE (TROUT_GPIO_START + 0x48)
86
87#define TROUT_GPIO_CHARGER_EN (TROUT_GPIO_MISC2_BASE + 0)
88#define TROUT_GPIO_ISET (TROUT_GPIO_MISC2_BASE + 1)
89#define TROUT_GPIO_H2W_DAT_DIR (TROUT_GPIO_MISC2_BASE + 2)
90#define TROUT_GPIO_H2W_CLK_DIR (TROUT_GPIO_MISC2_BASE + 3)
91#define TROUT_GPIO_H2W_DAT_GPO (TROUT_GPIO_MISC2_BASE + 4)
92#define TROUT_GPIO_H2W_CLK_GPO (TROUT_GPIO_MISC2_BASE + 5)
93#define TROUT_GPIO_H2W_SEL0 (TROUT_GPIO_MISC2_BASE + 6)
94#define TROUT_GPIO_H2W_SEL1 (TROUT_GPIO_MISC2_BASE + 7)
95
96#define TROUT_GPIO_SPOTLIGHT_EN (TROUT_GPIO_MISC3_BASE + 0)
97#define TROUT_GPIO_FLASH_EN (TROUT_GPIO_MISC3_BASE + 1)
98#define TROUT_GPIO_I2C_PULL (TROUT_GPIO_MISC3_BASE + 2)
99#define TROUT_GPIO_TP_I2C_PULL (TROUT_GPIO_MISC3_BASE + 3)
100#define TROUT_GPIO_TP_EN (TROUT_GPIO_MISC3_BASE + 4)
101#define TROUT_GPIO_JOG_EN (TROUT_GPIO_MISC3_BASE + 5)
102#define TROUT_GPIO_UI_LED_EN (TROUT_GPIO_MISC3_BASE + 6)
103#define TROUT_GPIO_QTKEY_LED_EN (TROUT_GPIO_MISC3_BASE + 7)
104
105#define TROUT_GPIO_VCM_PWDN (TROUT_GPIO_MISC4_BASE + 0)
106#define TROUT_GPIO_USB_H2W_SW (TROUT_GPIO_MISC4_BASE + 1)
107#define TROUT_GPIO_COMPASS_RST_N (TROUT_GPIO_MISC4_BASE + 2)
108#define TROUT_GPIO_HAPTIC_EN_UP (TROUT_GPIO_MISC4_BASE + 3)
109#define TROUT_GPIO_HAPTIC_EN_MAIN (TROUT_GPIO_MISC4_BASE + 4)
110#define TROUT_GPIO_USB_PHY_RST_N (TROUT_GPIO_MISC4_BASE + 5)
111#define TROUT_GPIO_WIFI_PA_RESETX (TROUT_GPIO_MISC4_BASE + 6)
112#define TROUT_GPIO_WIFI_EN (TROUT_GPIO_MISC4_BASE + 7)
113
114#define TROUT_GPIO_BT_32K_EN (TROUT_GPIO_MISC5_BASE + 0)
115#define TROUT_GPIO_MAC_32K_EN (TROUT_GPIO_MISC5_BASE + 1)
116#define TROUT_GPIO_MDDI_32K_EN (TROUT_GPIO_MISC5_BASE + 2)
117#define TROUT_GPIO_COMPASS_32K_EN (TROUT_GPIO_MISC5_BASE + 3)
118
119#define TROUT_GPIO_NAVI_ACT_N (TROUT_GPIO_INT2_BASE + 0)
120#define TROUT_GPIO_COMPASS_IRQ (TROUT_GPIO_INT2_BASE + 1)
121#define TROUT_GPIO_SLIDING_DET (TROUT_GPIO_INT2_BASE + 2)
122#define TROUT_GPIO_AUD_HSMIC_DET_N (TROUT_GPIO_INT2_BASE + 3)
123#define TROUT_GPIO_SD_DOOR_N (TROUT_GPIO_INT2_BASE + 4)
124#define TROUT_GPIO_CAM_BTN_STEP1_N (TROUT_GPIO_INT2_BASE + 5)
125#define TROUT_GPIO_CAM_BTN_STEP2_N (TROUT_GPIO_INT2_BASE + 6)
126#define TROUT_GPIO_TP_ATT_N (TROUT_GPIO_INT2_BASE + 7)
127#define TROUT_GPIO_BANK0_FIRST_INT_SOURCE (TROUT_GPIO_NAVI_ACT_N)
128#define TROUT_GPIO_BANK0_LAST_INT_SOURCE (TROUT_GPIO_TP_ATT_N)
129
130#define TROUT_GPIO_H2W_DAT_GPI (TROUT_GPIO_MISC1_BASE + 0)
131#define TROUT_GPIO_H2W_CLK_GPI (TROUT_GPIO_MISC1_BASE + 1)
132#define TROUT_GPIO_CPLD128_VER_0 (TROUT_GPIO_MISC1_BASE + 4)
133#define TROUT_GPIO_CPLD128_VER_1 (TROUT_GPIO_MISC1_BASE + 5)
134#define TROUT_GPIO_CPLD128_VER_2 (TROUT_GPIO_MISC1_BASE + 6)
135#define TROUT_GPIO_CPLD128_VER_3 (TROUT_GPIO_MISC1_BASE + 7)
136
137#define TROUT_GPIO_SDMC_CD_N (TROUT_GPIO_VIRTUAL_BASE + 0)
138#define TROUT_GPIO_END (TROUT_GPIO_SDMC_CD_N)
139#define TROUT_GPIO_BANK1_FIRST_INT_SOURCE (TROUT_GPIO_SDMC_CD_N)
140#define TROUT_GPIO_BANK1_LAST_INT_SOURCE (TROUT_GPIO_SDMC_CD_N)
141
142#define TROUT_GPIO_VIRTUAL_TO_REAL_OFFSET \
143 (TROUT_GPIO_INT5_BASE - TROUT_GPIO_VIRTUAL_BASE)
144
145#define TROUT_INT_START (NR_MSM_IRQS + NR_GPIO_IRQS)
146#define TROUT_INT_BANK0_COUNT (8)
147#define TROUT_INT_BANK1_START (TROUT_INT_START + TROUT_INT_BANK0_COUNT)
148#define TROUT_INT_BANK1_COUNT (1)
149#define TROUT_INT_END (TROUT_INT_START + TROUT_INT_BANK0_COUNT + \
150 TROUT_INT_BANK1_COUNT - 1)
151#define TROUT_GPIO_TO_INT(n) (((n) <= TROUT_GPIO_BANK0_LAST_INT_SOURCE) ? \
152 (TROUT_INT_START - TROUT_GPIO_BANK0_FIRST_INT_SOURCE + (n)) : \
153 (TROUT_INT_BANK1_START - TROUT_GPIO_BANK1_FIRST_INT_SOURCE + (n)))
154
155#define TROUT_INT_TO_BANK(n) ((n - TROUT_INT_START) / TROUT_INT_BANK0_COUNT)
156#define TROUT_INT_TO_MASK(n) (1U << ((n - TROUT_INT_START) & 7))
157#define TROUT_BANK_TO_MASK_REG(bank) \
158 (bank ? TROUT_GPIO_INT_MASK1_REG : TROUT_GPIO_INT_MASK0_REG)
159#define TROUT_BANK_TO_STAT_REG(bank) \
160 (bank ? TROUT_GPIO_INT_STAT1_REG : TROUT_GPIO_INT_STAT0_REG)
161
162#endif /* GUARD */
diff --git a/arch/arm/mach-msm/include/mach/gpio.h b/arch/arm/mach-msm/include/mach/gpio.h
index 262b441b4374..83e47c0d5c2e 100644
--- a/arch/arm/mach-msm/include/mach/gpio.h
+++ b/arch/arm/mach-msm/include/mach/gpio.h
@@ -16,6 +16,13 @@
16#ifndef __ASM_ARCH_MSM_GPIO_H 16#ifndef __ASM_ARCH_MSM_GPIO_H
17#define __ASM_ARCH_MSM_GPIO_H 17#define __ASM_ARCH_MSM_GPIO_H
18 18
19#include <asm-generic/gpio.h>
20
21#define gpio_get_value __gpio_get_value
22#define gpio_set_value __gpio_set_value
23#define gpio_cansleep __gpio_cansleep
24#define gpio_to_irq __gpio_to_irq
25
19/** 26/**
20 * struct msm_gpio - GPIO pin description 27 * struct msm_gpio - GPIO pin description
21 * @gpio_cfg - configuration bitmap, as per gpio_tlmm_config() 28 * @gpio_cfg - configuration bitmap, as per gpio_tlmm_config()
diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig
index 905719a677ae..c897e03e413d 100644
--- a/arch/arm/mach-orion5x/Kconfig
+++ b/arch/arm/mach-orion5x/Kconfig
@@ -26,6 +26,7 @@ config MACH_KUROBOX_PRO
26config MACH_DNS323 26config MACH_DNS323
27 bool "D-Link DNS-323" 27 bool "D-Link DNS-323"
28 select I2C_BOARDINFO 28 select I2C_BOARDINFO
29 select PHYLIB
29 help 30 help
30 Say 'Y' here if you want your kernel to support the 31 Say 'Y' here if you want your kernel to support the
31 D-Link DNS-323 platform. 32 D-Link DNS-323 platform.
diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c
index fe0de1698edc..a47100d46a4e 100644
--- a/arch/arm/mach-orion5x/dns323-setup.c
+++ b/arch/arm/mach-orion5x/dns323-setup.c
@@ -3,6 +3,10 @@
3 * 3 *
4 * Copyright (C) 2007 Herbert Valerio Riedel <hvr@gnu.org> 4 * Copyright (C) 2007 Herbert Valerio Riedel <hvr@gnu.org>
5 * 5 *
6 * Support for HW Rev C1:
7 *
8 * Copyright (C) 2010 Benjamin Herrenschmidt <benh@kernel.crashing.org>
9 *
6 * This program is free software; you can redistribute it and/or modify 10 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU Lesser General Public License as 11 * it under the terms of the GNU Lesser General Public License as
8 * published by the Free Software Foundation; either version 2 of the 12 * published by the Free Software Foundation; either version 2 of the
@@ -23,6 +27,8 @@
23#include <linux/input.h> 27#include <linux/input.h>
24#include <linux/i2c.h> 28#include <linux/i2c.h>
25#include <linux/ata_platform.h> 29#include <linux/ata_platform.h>
30#include <linux/phy.h>
31#include <linux/marvell_phy.h>
26#include <asm/mach-types.h> 32#include <asm/mach-types.h>
27#include <asm/gpio.h> 33#include <asm/gpio.h>
28#include <asm/mach/arch.h> 34#include <asm/mach/arch.h>
@@ -31,6 +37,7 @@
31#include "common.h" 37#include "common.h"
32#include "mpp.h" 38#include "mpp.h"
33 39
40/* Rev A1 and B1 */
34#define DNS323_GPIO_LED_RIGHT_AMBER 1 41#define DNS323_GPIO_LED_RIGHT_AMBER 1
35#define DNS323_GPIO_LED_LEFT_AMBER 2 42#define DNS323_GPIO_LED_LEFT_AMBER 2
36#define DNS323_GPIO_SYSTEM_UP 3 43#define DNS323_GPIO_SYSTEM_UP 3
@@ -42,6 +49,23 @@
42#define DNS323_GPIO_KEY_POWER 9 49#define DNS323_GPIO_KEY_POWER 9
43#define DNS323_GPIO_KEY_RESET 10 50#define DNS323_GPIO_KEY_RESET 10
44 51
52/* Rev C1 */
53#define DNS323C_GPIO_KEY_POWER 1
54#define DNS323C_GPIO_POWER_OFF 2
55#define DNS323C_GPIO_LED_RIGHT_AMBER 8
56#define DNS323C_GPIO_LED_LEFT_AMBER 9
57#define DNS323C_GPIO_LED_POWER 17
58#define DNS323C_GPIO_FAN_BIT1 18
59#define DNS323C_GPIO_FAN_BIT0 19
60
61/* Exposed to userspace, do not change */
62enum {
63 DNS323_REV_A1, /* 0 */
64 DNS323_REV_B1, /* 1 */
65 DNS323_REV_C1, /* 2 */
66};
67
68
45/**************************************************************************** 69/****************************************************************************
46 * PCI setup 70 * PCI setup
47 */ 71 */
@@ -68,21 +92,12 @@ static struct hw_pci dns323_pci __initdata = {
68 .map_irq = dns323_pci_map_irq, 92 .map_irq = dns323_pci_map_irq,
69}; 93};
70 94
71static int __init dns323_dev_id(void)
72{
73 u32 dev, rev;
74
75 orion5x_pcie_id(&dev, &rev);
76
77 return dev;
78}
79
80static int __init dns323_pci_init(void) 95static int __init dns323_pci_init(void)
81{ 96{
82 /* The 5182 doesn't really use its PCI bus, and initialising PCI 97 /* Rev B1 and C1 doesn't really use its PCI bus, and initialising PCI
83 * gets in the way of initialising the SATA controller. 98 * gets in the way of initialising the SATA controller.
84 */ 99 */
85 if (machine_is_dns323() && dns323_dev_id() != MV88F5182_DEV_ID) 100 if (machine_is_dns323() && system_rev == DNS323_REV_A1)
86 pci_common_init(&dns323_pci); 101 pci_common_init(&dns323_pci);
87 102
88 return 0; 103 return 0;
@@ -221,7 +236,7 @@ static int __init dns323_read_mac_addr(void)
221 } 236 }
222 237
223 iounmap(mac_page); 238 iounmap(mac_page);
224 printk("DNS323: Found ethernet MAC address: "); 239 printk("DNS-323: Found ethernet MAC address: ");
225 for (i = 0; i < 6; i++) 240 for (i = 0; i < 6; i++)
226 printk("%.2x%s", addr[i], (i < 5) ? ":" : ".\n"); 241 printk("%.2x%s", addr[i], (i < 5) ? ":" : ".\n");
227 242
@@ -259,12 +274,11 @@ static int dns323_gpio_blink_set(unsigned gpio, int state,
259 return 0; 274 return 0;
260} 275}
261 276
262static struct gpio_led dns323_leds[] = { 277static struct gpio_led dns323ab_leds[] = {
263 { 278 {
264 .name = "power:blue", 279 .name = "power:blue",
265 .gpio = DNS323_GPIO_LED_POWER2, 280 .gpio = DNS323_GPIO_LED_POWER2,
266 .default_trigger = "timer", 281 .default_trigger = "default-on",
267 .active_low = 1,
268 }, { 282 }, {
269 .name = "right:amber", 283 .name = "right:amber",
270 .gpio = DNS323_GPIO_LED_RIGHT_AMBER, 284 .gpio = DNS323_GPIO_LED_RIGHT_AMBER,
@@ -276,9 +290,34 @@ static struct gpio_led dns323_leds[] = {
276 }, 290 },
277}; 291};
278 292
279static struct gpio_led_platform_data dns323_led_data = { 293
280 .num_leds = ARRAY_SIZE(dns323_leds), 294static struct gpio_led dns323c_leds[] = {
281 .leds = dns323_leds, 295 {
296 .name = "power:blue",
297 .gpio = DNS323C_GPIO_LED_POWER,
298 .default_trigger = "timer",
299 .active_low = 1,
300 }, {
301 .name = "right:amber",
302 .gpio = DNS323C_GPIO_LED_RIGHT_AMBER,
303 .active_low = 1,
304 }, {
305 .name = "left:amber",
306 .gpio = DNS323C_GPIO_LED_LEFT_AMBER,
307 .active_low = 1,
308 },
309};
310
311
312static struct gpio_led_platform_data dns323ab_led_data = {
313 .num_leds = ARRAY_SIZE(dns323ab_leds),
314 .leds = dns323ab_leds,
315 .gpio_blink_set = dns323_gpio_blink_set,
316};
317
318static struct gpio_led_platform_data dns323c_led_data = {
319 .num_leds = ARRAY_SIZE(dns323c_leds),
320 .leds = dns323c_leds,
282 .gpio_blink_set = dns323_gpio_blink_set, 321 .gpio_blink_set = dns323_gpio_blink_set,
283}; 322};
284 323
@@ -286,7 +325,7 @@ static struct platform_device dns323_gpio_leds = {
286 .name = "leds-gpio", 325 .name = "leds-gpio",
287 .id = -1, 326 .id = -1,
288 .dev = { 327 .dev = {
289 .platform_data = &dns323_led_data, 328 .platform_data = &dns323ab_led_data,
290 }, 329 },
291}; 330};
292 331
@@ -294,7 +333,7 @@ static struct platform_device dns323_gpio_leds = {
294 * GPIO Attached Keys 333 * GPIO Attached Keys
295 */ 334 */
296 335
297static struct gpio_keys_button dns323_buttons[] = { 336static struct gpio_keys_button dns323ab_buttons[] = {
298 { 337 {
299 .code = KEY_RESTART, 338 .code = KEY_RESTART,
300 .gpio = DNS323_GPIO_KEY_RESET, 339 .gpio = DNS323_GPIO_KEY_RESET,
@@ -308,9 +347,23 @@ static struct gpio_keys_button dns323_buttons[] = {
308 }, 347 },
309}; 348};
310 349
311static struct gpio_keys_platform_data dns323_button_data = { 350static struct gpio_keys_platform_data dns323ab_button_data = {
312 .buttons = dns323_buttons, 351 .buttons = dns323ab_buttons,
313 .nbuttons = ARRAY_SIZE(dns323_buttons), 352 .nbuttons = ARRAY_SIZE(dns323ab_buttons),
353};
354
355static struct gpio_keys_button dns323c_buttons[] = {
356 {
357 .code = KEY_POWER,
358 .gpio = DNS323C_GPIO_KEY_POWER,
359 .desc = "Power Button",
360 .active_low = 1,
361 },
362};
363
364static struct gpio_keys_platform_data dns323c_button_data = {
365 .buttons = dns323c_buttons,
366 .nbuttons = ARRAY_SIZE(dns323c_buttons),
314}; 367};
315 368
316static struct platform_device dns323_button_device = { 369static struct platform_device dns323_button_device = {
@@ -318,7 +371,7 @@ static struct platform_device dns323_button_device = {
318 .id = -1, 371 .id = -1,
319 .num_resources = 0, 372 .num_resources = 0,
320 .dev = { 373 .dev = {
321 .platform_data = &dns323_button_data, 374 .platform_data = &dns323ab_button_data,
322 }, 375 },
323}; 376};
324 377
@@ -332,7 +385,7 @@ static struct mv_sata_platform_data dns323_sata_data = {
332/**************************************************************************** 385/****************************************************************************
333 * General Setup 386 * General Setup
334 */ 387 */
335static struct orion5x_mpp_mode dns323_mv88f5181_mpp_modes[] __initdata = { 388static struct orion5x_mpp_mode dns323a_mpp_modes[] __initdata = {
336 { 0, MPP_PCIE_RST_OUTn }, 389 { 0, MPP_PCIE_RST_OUTn },
337 { 1, MPP_GPIO }, /* right amber LED (sata ch0) */ 390 { 1, MPP_GPIO }, /* right amber LED (sata ch0) */
338 { 2, MPP_GPIO }, /* left amber LED (sata ch1) */ 391 { 2, MPP_GPIO }, /* left amber LED (sata ch1) */
@@ -356,7 +409,7 @@ static struct orion5x_mpp_mode dns323_mv88f5181_mpp_modes[] __initdata = {
356 { -1 }, 409 { -1 },
357}; 410};
358 411
359static struct orion5x_mpp_mode dns323_mv88f5182_mpp_modes[] __initdata = { 412static struct orion5x_mpp_mode dns323b_mpp_modes[] __initdata = {
360 { 0, MPP_UNUSED }, 413 { 0, MPP_UNUSED },
361 { 1, MPP_GPIO }, /* right amber LED (sata ch0) */ 414 { 1, MPP_GPIO }, /* right amber LED (sata ch0) */
362 { 2, MPP_GPIO }, /* left amber LED (sata ch1) */ 415 { 2, MPP_GPIO }, /* left amber LED (sata ch1) */
@@ -380,15 +433,57 @@ static struct orion5x_mpp_mode dns323_mv88f5182_mpp_modes[] __initdata = {
380 { -1 }, 433 { -1 },
381}; 434};
382 435
436static struct orion5x_mpp_mode dns323c_mpp_modes[] __initdata = {
437 { 0, MPP_GPIO }, /* ? input */
438 { 1, MPP_GPIO }, /* input power switch (0 = pressed) */
439 { 2, MPP_GPIO }, /* output power off */
440 { 3, MPP_UNUSED }, /* ? output */
441 { 4, MPP_UNUSED }, /* ? output */
442 { 5, MPP_UNUSED }, /* ? output */
443 { 6, MPP_UNUSED }, /* ? output */
444 { 7, MPP_UNUSED }, /* ? output */
445 { 8, MPP_GPIO }, /* i/o right amber LED */
446 { 9, MPP_GPIO }, /* i/o left amber LED */
447 { 10, MPP_GPIO }, /* input */
448 { 11, MPP_UNUSED },
449 { 12, MPP_SATA_LED },
450 { 13, MPP_SATA_LED },
451 { 14, MPP_SATA_LED },
452 { 15, MPP_SATA_LED },
453 { 16, MPP_UNUSED },
454 { 17, MPP_GPIO }, /* power button LED */
455 { 18, MPP_GPIO }, /* fan speed bit 0 */
456 { 19, MPP_GPIO }, /* fan speed bit 1 */
457 { -1 },
458};
459
460/* Rev C1 Fan speed notes:
461 *
462 * The fan is controlled by 2 GPIOs on this board. The settings
463 * of the bits is as follow:
464 *
465 * GPIO 18 GPIO 19 Fan
466 *
467 * 0 0 stopped
468 * 0 1 low speed
469 * 1 0 high speed
470 * 1 1 don't do that (*)
471 *
472 * (*) I think the two bits control two feed-in resistors into a fixed
473 * PWN circuit, setting both bits will basically go a 'bit' faster
474 * than high speed, but d-link doesn't do it and you may get out of
475 * HW spec so don't do it.
476 */
477
383/* 478/*
384 * On the DNS-323 the following devices are attached via I2C: 479 * On the DNS-323 A1 and B1 the following devices are attached via I2C:
385 * 480 *
386 * i2c addr | chip | description 481 * i2c addr | chip | description
387 * 0x3e | GMT G760Af | fan speed PWM controller 482 * 0x3e | GMT G760Af | fan speed PWM controller
388 * 0x48 | GMT G751-2f | temp. sensor and therm. watchdog (LM75 compatible) 483 * 0x48 | GMT G751-2f | temp. sensor and therm. watchdog (LM75 compatible)
389 * 0x68 | ST M41T80 | RTC w/ alarm 484 * 0x68 | ST M41T80 | RTC w/ alarm
390 */ 485 */
391static struct i2c_board_info __initdata dns323_i2c_devices[] = { 486static struct i2c_board_info __initdata dns323ab_i2c_devices[] = {
392 { 487 {
393 I2C_BOARD_INFO("g760a", 0x3e), 488 I2C_BOARD_INFO("g760a", 0x3e),
394 }, { 489 }, {
@@ -398,36 +493,140 @@ static struct i2c_board_info __initdata dns323_i2c_devices[] = {
398 }, 493 },
399}; 494};
400 495
496/*
497 * On the DNS-323 C1 the following devices are attached via I2C:
498 *
499 * i2c addr | chip | description
500 * 0x48 | GMT G751-2f | temp. sensor and therm. watchdog (LM75 compatible)
501 * 0x68 | ST M41T80 | RTC w/ alarm
502 */
503static struct i2c_board_info __initdata dns323c_i2c_devices[] = {
504 {
505 I2C_BOARD_INFO("lm75", 0x48),
506 }, {
507 I2C_BOARD_INFO("m41t80", 0x68),
508 },
509};
510
401/* DNS-323 rev. A specific power off method */ 511/* DNS-323 rev. A specific power off method */
402static void dns323a_power_off(void) 512static void dns323a_power_off(void)
403{ 513{
404 pr_info("%s: triggering power-off...\n", __func__); 514 pr_info("DNS-323: Triggering power-off...\n");
405 gpio_set_value(DNS323_GPIO_POWER_OFF, 1); 515 gpio_set_value(DNS323_GPIO_POWER_OFF, 1);
406} 516}
407 517
408/* DNS-323 rev B specific power off method */ 518/* DNS-323 rev B specific power off method */
409static void dns323b_power_off(void) 519static void dns323b_power_off(void)
410{ 520{
411 pr_info("%s: triggering power-off...\n", __func__); 521 pr_info("DNS-323: Triggering power-off...\n");
412 /* Pin has to be changed to 1 and back to 0 to do actual power off. */ 522 /* Pin has to be changed to 1 and back to 0 to do actual power off. */
413 gpio_set_value(DNS323_GPIO_POWER_OFF, 1); 523 gpio_set_value(DNS323_GPIO_POWER_OFF, 1);
414 mdelay(100); 524 mdelay(100);
415 gpio_set_value(DNS323_GPIO_POWER_OFF, 0); 525 gpio_set_value(DNS323_GPIO_POWER_OFF, 0);
416} 526}
417 527
528/* DNS-323 rev. C specific power off method */
529static void dns323c_power_off(void)
530{
531 pr_info("DNS-323: Triggering power-off...\n");
532 gpio_set_value(DNS323C_GPIO_POWER_OFF, 1);
533}
534
535static int dns323c_phy_fixup(struct phy_device *phy)
536{
537 phy->dev_flags |= MARVELL_PHY_M1118_DNS323_LEDS;
538
539 return 0;
540}
541
542static int __init dns323_identify_rev(void)
543{
544 u32 dev, rev, i, reg;
545
546 pr_debug("DNS-323: Identifying board ... \n");
547
548 /* Rev A1 has a 5181 */
549 orion5x_pcie_id(&dev, &rev);
550 if (dev == MV88F5181_DEV_ID) {
551 pr_debug("DNS-323: 5181 found, board is A1\n");
552 return DNS323_REV_A1;
553 }
554 pr_debug("DNS-323: 5182 found, board is B1 or C1, checking PHY...\n");
555
556 /* Rev B1 and C1 both have 5182, let's poke at the eth PHY. This is
557 * a bit gross but we want to do that without links into the eth
558 * driver so let's poke at it directly. We default to rev B1 in
559 * case the accesses fail
560 */
561
562#define ETH_SMI_REG (ORION5X_ETH_VIRT_BASE + 0x2000 + 0x004)
563#define SMI_BUSY 0x10000000
564#define SMI_READ_VALID 0x08000000
565#define SMI_OPCODE_READ 0x04000000
566#define SMI_OPCODE_WRITE 0x00000000
567
568 for (i = 0; i < 1000; i++) {
569 reg = readl(ETH_SMI_REG);
570 if (!(reg & SMI_BUSY))
571 break;
572 }
573 if (i >= 1000) {
574 pr_warning("DNS-323: Timeout accessing PHY, assuming rev B1\n");
575 return DNS323_REV_B1;
576 }
577 writel((3 << 21) /* phy ID reg */ |
578 (8 << 16) /* phy addr */ |
579 SMI_OPCODE_READ, ETH_SMI_REG);
580 for (i = 0; i < 1000; i++) {
581 reg = readl(ETH_SMI_REG);
582 if (reg & SMI_READ_VALID)
583 break;
584 }
585 if (i >= 1000) {
586 pr_warning("DNS-323: Timeout reading PHY, assuming rev B1\n");
587 return DNS323_REV_B1;
588 }
589 pr_debug("DNS-323: Ethernet PHY ID 0x%x\n", reg & 0xffff);
590
591 /* Note: the Marvell tools mask the ID with 0x3f0 before comparison
592 * but I don't see that making a difference here, at least with
593 * any known Marvell PHY ID
594 */
595 switch(reg & 0xfff0) {
596 case 0x0cc0: /* MV88E1111 */
597 return DNS323_REV_B1;
598 case 0x0e10: /* MV88E1118 */
599 return DNS323_REV_C1;
600 default:
601 pr_warning("DNS-323: Unknown PHY ID 0x%04x, assuming rev B1\n",
602 reg & 0xffff);
603 }
604 return DNS323_REV_B1;
605}
606
418static void __init dns323_init(void) 607static void __init dns323_init(void)
419{ 608{
420 /* Setup basic Orion functions. Need to be called early. */ 609 /* Setup basic Orion functions. Need to be called early. */
421 orion5x_init(); 610 orion5x_init();
422 611
612 /* Identify revision */
613 system_rev = dns323_identify_rev();
614 pr_info("DNS-323: Identified HW revision %c1\n", 'A' + system_rev);
615
423 /* Just to be tricky, the 5182 has a completely different 616 /* Just to be tricky, the 5182 has a completely different
424 * set of MPP modes to the 5181. 617 * set of MPP modes to the 5181.
425 */ 618 */
426 if (dns323_dev_id() == MV88F5182_DEV_ID) 619 switch(system_rev) {
427 orion5x_mpp_conf(dns323_mv88f5182_mpp_modes); 620 case DNS323_REV_A1:
428 else { 621 orion5x_mpp_conf(dns323a_mpp_modes);
429 orion5x_mpp_conf(dns323_mv88f5181_mpp_modes);
430 writel(0, MPP_DEV_CTRL); /* DEV_D[31:16] */ 622 writel(0, MPP_DEV_CTRL); /* DEV_D[31:16] */
623 break;
624 case DNS323_REV_B1:
625 orion5x_mpp_conf(dns323b_mpp_modes);
626 break;
627 case DNS323_REV_C1:
628 orion5x_mpp_conf(dns323c_mpp_modes);
629 break;
431 } 630 }
432 631
433 /* setup flash mapping 632 /* setup flash mapping
@@ -436,53 +635,96 @@ static void __init dns323_init(void)
436 orion5x_setup_dev_boot_win(DNS323_NOR_BOOT_BASE, DNS323_NOR_BOOT_SIZE); 635 orion5x_setup_dev_boot_win(DNS323_NOR_BOOT_BASE, DNS323_NOR_BOOT_SIZE);
437 platform_device_register(&dns323_nor_flash); 636 platform_device_register(&dns323_nor_flash);
438 637
439 /* The 5181 power LED is active low and requires 638 /* Sort out LEDs, Buttons and i2c devices */
440 * DNS323_GPIO_LED_POWER1 to also be low. 639 switch(system_rev) {
441 */ 640 case DNS323_REV_A1:
442 if (dns323_dev_id() == MV88F5181_DEV_ID) { 641 /* The 5181 power LED is active low and requires
443 dns323_leds[0].active_low = 1; 642 * DNS323_GPIO_LED_POWER1 to also be low.
444 gpio_request(DNS323_GPIO_LED_POWER1, "Power Led Enable"); 643 */
445 gpio_direction_output(DNS323_GPIO_LED_POWER1, 0); 644 dns323ab_leds[0].active_low = 1;
645 gpio_request(DNS323_GPIO_LED_POWER1, "Power Led Enable");
646 gpio_direction_output(DNS323_GPIO_LED_POWER1, 0);
647 /* Fall through */
648 case DNS323_REV_B1:
649 i2c_register_board_info(0, dns323ab_i2c_devices,
650 ARRAY_SIZE(dns323ab_i2c_devices));
651 break;
652 case DNS323_REV_C1:
653 /* Hookup LEDs & Buttons */
654 dns323_gpio_leds.dev.platform_data = &dns323c_led_data;
655 dns323_button_device.dev.platform_data = &dns323c_button_data;
656
657 /* Hookup i2c devices and fan driver */
658 i2c_register_board_info(0, dns323c_i2c_devices,
659 ARRAY_SIZE(dns323c_i2c_devices));
660 platform_device_register_simple("dns323c-fan", 0, NULL, 0);
661
662 /* Register fixup for the PHY LEDs */
663 phy_register_fixup_for_uid(MARVELL_PHY_ID_88E1118,
664 MARVELL_PHY_ID_MASK,
665 dns323c_phy_fixup);
446 } 666 }
447 667
448 platform_device_register(&dns323_gpio_leds); 668 platform_device_register(&dns323_gpio_leds);
449
450 platform_device_register(&dns323_button_device); 669 platform_device_register(&dns323_button_device);
451 670
452 i2c_register_board_info(0, dns323_i2c_devices,
453 ARRAY_SIZE(dns323_i2c_devices));
454
455 /* 671 /*
456 * Configure peripherals. 672 * Configure peripherals.
457 */ 673 */
458 if (dns323_read_mac_addr() < 0) 674 if (dns323_read_mac_addr() < 0)
459 printk("DNS323: Failed to read MAC address\n"); 675 printk("DNS-323: Failed to read MAC address\n");
460
461 orion5x_ehci0_init(); 676 orion5x_ehci0_init();
462 orion5x_eth_init(&dns323_eth_data); 677 orion5x_eth_init(&dns323_eth_data);
463 orion5x_i2c_init(); 678 orion5x_i2c_init();
464 orion5x_uart0_init(); 679 orion5x_uart0_init();
465 680
466 /* The 5182 has its SATA controller on-chip, and needs its own little 681 /* Remaining GPIOs */
467 * init routine. 682 switch(system_rev) {
468 */ 683 case DNS323_REV_A1:
469 if (dns323_dev_id() == MV88F5182_DEV_ID) 684 /* Poweroff GPIO */
685 if (gpio_request(DNS323_GPIO_POWER_OFF, "POWEROFF") != 0 ||
686 gpio_direction_output(DNS323_GPIO_POWER_OFF, 0) != 0)
687 pr_err("DNS-323: failed to setup power-off GPIO\n");
688 pm_power_off = dns323a_power_off;
689 break;
690 case DNS323_REV_B1:
691 /* 5182 built-in SATA init */
470 orion5x_sata_init(&dns323_sata_data); 692 orion5x_sata_init(&dns323_sata_data);
471 693
472 /* The 5182 has flag to indicate the system is up. Without this flag 694 /* The DNS323 rev B1 has flag to indicate the system is up.
473 * set, power LED will flash and cannot be controlled via leds-gpio. 695 * Without this flag set, power LED will flash and cannot be
474 */ 696 * controlled via leds-gpio.
475 if (dns323_dev_id() == MV88F5182_DEV_ID) 697 */
476 gpio_set_value(DNS323_GPIO_SYSTEM_UP, 1); 698 if (gpio_request(DNS323_GPIO_SYSTEM_UP, "SYS_READY") == 0)
477 699 gpio_direction_output(DNS323_GPIO_SYSTEM_UP, 1);
478 /* Register dns323 specific power-off method */ 700
479 if (gpio_request(DNS323_GPIO_POWER_OFF, "POWEROFF") != 0 || 701 /* Poweroff GPIO */
480 gpio_direction_output(DNS323_GPIO_POWER_OFF, 0) != 0) 702 if (gpio_request(DNS323_GPIO_POWER_OFF, "POWEROFF") != 0 ||
481 pr_err("DNS323: failed to setup power-off GPIO\n"); 703 gpio_direction_output(DNS323_GPIO_POWER_OFF, 0) != 0)
482 if (dns323_dev_id() == MV88F5182_DEV_ID) 704 pr_err("DNS-323: failed to setup power-off GPIO\n");
483 pm_power_off = dns323b_power_off; 705 pm_power_off = dns323b_power_off;
484 else 706 break;
485 pm_power_off = dns323a_power_off; 707 case DNS323_REV_C1:
708 /* 5182 built-in SATA init */
709 orion5x_sata_init(&dns323_sata_data);
710
711 /* Poweroff GPIO */
712 if (gpio_request(DNS323C_GPIO_POWER_OFF, "POWEROFF") != 0 ||
713 gpio_direction_output(DNS323C_GPIO_POWER_OFF, 0) != 0)
714 pr_err("DNS-323: failed to setup power-off GPIO\n");
715 pm_power_off = dns323c_power_off;
716
717 /* Now, -this- should theorically be done by the sata_mv driver
718 * once I figure out what's going on there. Maybe the behaviour
719 * of the LEDs should be somewhat passed via the platform_data.
720 * for now, just whack the register and make the LEDs happy
721 *
722 * Note: AFAIK, rev B1 needs the same treatement but I'll let
723 * somebody else test it.
724 */
725 writel(0x5, ORION5X_SATA_VIRT_BASE | 0x2c);
726 break;
727 }
486} 728}
487 729
488/* Warning: D-Link uses a wrong mach-type (=526) in their bootloader */ 730/* Warning: D-Link uses a wrong mach-type (=526) in their bootloader */
diff --git a/arch/arm/mach-orion5x/include/mach/system.h b/arch/arm/mach-orion5x/include/mach/system.h
index 60e734c10458..a1d6e46ab035 100644
--- a/arch/arm/mach-orion5x/include/mach/system.h
+++ b/arch/arm/mach-orion5x/include/mach/system.h
@@ -25,6 +25,8 @@ static inline void arch_reset(char mode, const char *cmd)
25 */ 25 */
26 orion5x_setbits(RSTOUTn_MASK, (1 << 2)); 26 orion5x_setbits(RSTOUTn_MASK, (1 << 2));
27 orion5x_setbits(CPU_SOFT_RESET, 1); 27 orion5x_setbits(CPU_SOFT_RESET, 1);
28 mdelay(200);
29 orion5x_clrbits(CPU_SOFT_RESET, 1);
28} 30}
29 31
30 32
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index f6a999465323..e18c7cedb482 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -495,28 +495,27 @@ static void __init free_unused_memmap_node(int node, struct meminfo *mi)
495 unsigned int i; 495 unsigned int i;
496 496
497 /* 497 /*
498 * [FIXME] This relies on each bank being in address order. This 498 * This relies on each bank being in address order.
499 * may not be the case, especially if the user has provided the 499 * The banks are sorted previously in bootmem_init().
500 * information on the command line.
501 */ 500 */
502 for_each_nodebank(i, mi, node) { 501 for_each_nodebank(i, mi, node) {
503 struct membank *bank = &mi->bank[i]; 502 struct membank *bank = &mi->bank[i];
504 503
505 bank_start = bank_pfn_start(bank); 504 bank_start = bank_pfn_start(bank);
506 if (bank_start < prev_bank_end) {
507 printk(KERN_ERR "MEM: unordered memory banks. "
508 "Not freeing memmap.\n");
509 break;
510 }
511 505
512 /* 506 /*
513 * If we had a previous bank, and there is a space 507 * If we had a previous bank, and there is a space
514 * between the current bank and the previous, free it. 508 * between the current bank and the previous, free it.
515 */ 509 */
516 if (prev_bank_end && prev_bank_end != bank_start) 510 if (prev_bank_end && prev_bank_end < bank_start)
517 free_memmap(node, prev_bank_end, bank_start); 511 free_memmap(node, prev_bank_end, bank_start);
518 512
519 prev_bank_end = bank_pfn_end(bank); 513 /*
514 * Align up here since the VM subsystem insists that the
515 * memmap entries are valid from the bank end aligned to
516 * MAX_ORDER_NR_PAGES.
517 */
518 prev_bank_end = ALIGN(bank_pfn_end(bank), MAX_ORDER_NR_PAGES);
520 } 519 }
521} 520}
522 521
diff --git a/arch/arm/mm/mmap.c b/arch/arm/mm/mmap.c
index f5abc51c5a07..4f5b39687df5 100644
--- a/arch/arm/mm/mmap.c
+++ b/arch/arm/mm/mmap.c
@@ -7,6 +7,7 @@
7#include <linux/shm.h> 7#include <linux/shm.h>
8#include <linux/sched.h> 8#include <linux/sched.h>
9#include <linux/io.h> 9#include <linux/io.h>
10#include <linux/random.h>
10#include <asm/cputype.h> 11#include <asm/cputype.h>
11#include <asm/system.h> 12#include <asm/system.h>
12 13
@@ -80,6 +81,9 @@ arch_get_unmapped_area(struct file *filp, unsigned long addr,
80 start_addr = addr = TASK_UNMAPPED_BASE; 81 start_addr = addr = TASK_UNMAPPED_BASE;
81 mm->cached_hole_size = 0; 82 mm->cached_hole_size = 0;
82 } 83 }
84 /* 8 bits of randomness in 20 address space bits */
85 if (current->flags & PF_RANDOMIZE)
86 addr += (get_random_int() % (1 << 8)) << PAGE_SHIFT;
83 87
84full_search: 88full_search:
85 if (do_align) 89 if (do_align)
diff --git a/arch/arm/plat-orion/pcie.c b/arch/arm/plat-orion/pcie.c
index 54c84a492a0f..779553a1595e 100644
--- a/arch/arm/plat-orion/pcie.c
+++ b/arch/arm/plat-orion/pcie.c
@@ -13,6 +13,7 @@
13#include <linux/mbus.h> 13#include <linux/mbus.h>
14#include <asm/mach/pci.h> 14#include <asm/mach/pci.h>
15#include <plat/pcie.h> 15#include <plat/pcie.h>
16#include <linux/delay.h>
16 17
17/* 18/*
18 * PCIe unit register offsets. 19 * PCIe unit register offsets.
@@ -46,6 +47,8 @@
46#define PCIE_STAT_BUS_OFFS 8 47#define PCIE_STAT_BUS_OFFS 8
47#define PCIE_STAT_BUS_MASK 0xff 48#define PCIE_STAT_BUS_MASK 0xff
48#define PCIE_STAT_LINK_DOWN 1 49#define PCIE_STAT_LINK_DOWN 1
50#define PCIE_DEBUG_CTRL 0x1a60
51#define PCIE_DEBUG_SOFT_RESET (1<<20)
49 52
50 53
51u32 __init orion_pcie_dev_id(void __iomem *base) 54u32 __init orion_pcie_dev_id(void __iomem *base)
@@ -85,6 +88,32 @@ void __init orion_pcie_set_local_bus_nr(void __iomem *base, int nr)
85 writel(stat, base + PCIE_STAT_OFF); 88 writel(stat, base + PCIE_STAT_OFF);
86} 89}
87 90
91void __init orion_pcie_reset(void __iomem *base)
92{
93 u32 reg;
94 int i;
95
96 /*
97 * MV-S104860-U0, Rev. C:
98 * PCI Express Unit Soft Reset
99 * When set, generates an internal reset in the PCI Express unit.
100 * This bit should be cleared after the link is re-established.
101 */
102 reg = readl(base + PCIE_DEBUG_CTRL);
103 reg |= PCIE_DEBUG_SOFT_RESET;
104 writel(reg, base + PCIE_DEBUG_CTRL);
105
106 for (i = 0; i < 20; i++) {
107 mdelay(10);
108
109 if (orion_pcie_link_up(base))
110 break;
111 }
112
113 reg &= ~(PCIE_DEBUG_SOFT_RESET);
114 writel(reg, base + PCIE_DEBUG_CTRL);
115}
116
88/* 117/*
89 * Setup PCIE BARs and Address Decode Wins: 118 * Setup PCIE BARs and Address Decode Wins:
90 * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks 119 * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
@@ -153,6 +182,11 @@ void __init orion_pcie_setup(void __iomem *base,
153 u32 mask; 182 u32 mask;
154 183
155 /* 184 /*
185 * soft reset PCIe unit
186 */
187 orion_pcie_reset(base);
188
189 /*
156 * Point PCIe unit MBUS decode windows to DRAM space. 190 * Point PCIe unit MBUS decode windows to DRAM space.
157 */ 191 */
158 orion_pcie_setup_wins(base, dram); 192 orion_pcie_setup_wins(base, dram);
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-11 02:11:01 -0500