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-rw-r--r--arch/arm/mach-imx/clk-imx27.c4
-rw-r--r--arch/arm/mach-imx/clk-imx31.c4
-rw-r--r--arch/arm/mach-imx/clk-imx51-imx53.c23
-rw-r--r--arch/arm/mach-omap2/Makefile1
-rw-r--r--arch/arm/mach-omap2/clock.h14
-rw-r--r--arch/arm/mach-omap2/clock33xx_data.c1105
-rw-r--r--arch/arm/mach-omap2/clock3xxx_data.c20
-rw-r--r--arch/arm/mach-omap2/clock44xx_data.c72
-rw-r--r--arch/arm/mach-omap2/clock_common_data.c77
-rw-r--r--arch/arm/mach-omap2/io.c2
-rw-r--r--arch/arm/mach-tegra/cpu-tegra.c6
-rw-r--r--arch/arm/mach-tegra/dma.c4
-rw-r--r--arch/arm/mach-tegra/pcie.c6
-rw-r--r--arch/arm/mach-tegra/powergate.c4
-rw-r--r--arch/arm/mach-tegra/tegra2_clocks.c58
-rw-r--r--arch/arm/mach-tegra/tegra30_clocks.c28
-rw-r--r--arch/arm/mach-tegra/timer.c4
-rw-r--r--arch/arm/mach-tegra/usb_phy.c16
-rw-r--r--arch/arm/plat-mxc/devices/platform-spi_imx.c2
-rw-r--r--arch/arm/plat-mxc/time.c3
-rw-r--r--arch/arm/plat-omap/include/plat/clkdev_omap.h1
21 files changed, 1299 insertions, 155 deletions
diff --git a/arch/arm/mach-imx/clk-imx27.c b/arch/arm/mach-imx/clk-imx27.c
index 295cbd7c08dc..7aa6313fb167 100644
--- a/arch/arm/mach-imx/clk-imx27.c
+++ b/arch/arm/mach-imx/clk-imx27.c
@@ -256,7 +256,7 @@ int __init mx27_clocks_init(unsigned long fref)
256 clk_register_clkdev(clk[gpio_ipg_gate], "gpio", NULL); 256 clk_register_clkdev(clk[gpio_ipg_gate], "gpio", NULL);
257 clk_register_clkdev(clk[brom_ahb_gate], "brom", NULL); 257 clk_register_clkdev(clk[brom_ahb_gate], "brom", NULL);
258 clk_register_clkdev(clk[ata_ahb_gate], "ata", NULL); 258 clk_register_clkdev(clk[ata_ahb_gate], "ata", NULL);
259 clk_register_clkdev(clk[rtc_ipg_gate], "rtc", NULL); 259 clk_register_clkdev(clk[rtc_ipg_gate], NULL, "mxc_rtc");
260 clk_register_clkdev(clk[scc_ipg_gate], "scc", NULL); 260 clk_register_clkdev(clk[scc_ipg_gate], "scc", NULL);
261 clk_register_clkdev(clk[cpu_div], "cpu", NULL); 261 clk_register_clkdev(clk[cpu_div], "cpu", NULL);
262 clk_register_clkdev(clk[emi_ahb_gate], "emi_ahb" , NULL); 262 clk_register_clkdev(clk[emi_ahb_gate], "emi_ahb" , NULL);
@@ -267,6 +267,8 @@ int __init mx27_clocks_init(unsigned long fref)
267 267
268 clk_prepare_enable(clk[emi_ahb_gate]); 268 clk_prepare_enable(clk[emi_ahb_gate]);
269 269
270 imx_print_silicon_rev("i.MX27", mx27_revision());
271
270 return 0; 272 return 0;
271} 273}
272 274
diff --git a/arch/arm/mach-imx/clk-imx31.c b/arch/arm/mach-imx/clk-imx31.c
index f87a48fc74e1..8e19e70f90f9 100644
--- a/arch/arm/mach-imx/clk-imx31.c
+++ b/arch/arm/mach-imx/clk-imx31.c
@@ -124,7 +124,7 @@ int __init mx31_clocks_init(unsigned long fref)
124 clk_register_clkdev(clk[cspi3_gate], NULL, "imx31-cspi.2"); 124 clk_register_clkdev(clk[cspi3_gate], NULL, "imx31-cspi.2");
125 clk_register_clkdev(clk[pwm_gate], "pwm", NULL); 125 clk_register_clkdev(clk[pwm_gate], "pwm", NULL);
126 clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0"); 126 clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0");
127 clk_register_clkdev(clk[rtc_gate], "rtc", NULL); 127 clk_register_clkdev(clk[rtc_gate], NULL, "mxc_rtc");
128 clk_register_clkdev(clk[epit1_gate], "epit", NULL); 128 clk_register_clkdev(clk[epit1_gate], "epit", NULL);
129 clk_register_clkdev(clk[epit2_gate], "epit", NULL); 129 clk_register_clkdev(clk[epit2_gate], "epit", NULL);
130 clk_register_clkdev(clk[nfc], NULL, "mxc_nand.0"); 130 clk_register_clkdev(clk[nfc], NULL, "mxc_nand.0");
@@ -166,7 +166,7 @@ int __init mx31_clocks_init(unsigned long fref)
166 clk_register_clkdev(clk[firi_gate], "firi", NULL); 166 clk_register_clkdev(clk[firi_gate], "firi", NULL);
167 clk_register_clkdev(clk[ata_gate], NULL, "pata_imx"); 167 clk_register_clkdev(clk[ata_gate], NULL, "pata_imx");
168 clk_register_clkdev(clk[rtic_gate], "rtic", NULL); 168 clk_register_clkdev(clk[rtic_gate], "rtic", NULL);
169 clk_register_clkdev(clk[rng_gate], "rng", NULL); 169 clk_register_clkdev(clk[rng_gate], NULL, "mxc_rnga");
170 clk_register_clkdev(clk[sdma_gate], NULL, "imx31-sdma"); 170 clk_register_clkdev(clk[sdma_gate], NULL, "imx31-sdma");
171 clk_register_clkdev(clk[iim_gate], "iim", NULL); 171 clk_register_clkdev(clk[iim_gate], "iim", NULL);
172 172
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index 4b89fae14a5a..f6086693ebd2 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -58,7 +58,7 @@ enum imx5_clks {
58 tve_s, uart1_ipg_gate, uart1_per_gate, uart2_ipg_gate, 58 tve_s, uart1_ipg_gate, uart1_per_gate, uart2_ipg_gate,
59 uart2_per_gate, uart3_ipg_gate, uart3_per_gate, i2c1_gate, i2c2_gate, 59 uart2_per_gate, uart3_ipg_gate, uart3_per_gate, i2c1_gate, i2c2_gate,
60 gpt_ipg_gate, pwm1_ipg_gate, pwm1_hf_gate, pwm2_ipg_gate, pwm2_hf_gate, 60 gpt_ipg_gate, pwm1_ipg_gate, pwm1_hf_gate, pwm2_ipg_gate, pwm2_hf_gate,
61 gpt_gate, fec_gate, usboh3_per_gate, esdhc1_ipg_gate, esdhc2_ipg_gate, 61 gpt_hf_gate, fec_gate, usboh3_per_gate, esdhc1_ipg_gate, esdhc2_ipg_gate,
62 esdhc3_ipg_gate, esdhc4_ipg_gate, ssi1_ipg_gate, ssi2_ipg_gate, 62 esdhc3_ipg_gate, esdhc4_ipg_gate, ssi1_ipg_gate, ssi2_ipg_gate,
63 ssi3_ipg_gate, ecspi1_ipg_gate, ecspi1_per_gate, ecspi2_ipg_gate, 63 ssi3_ipg_gate, ecspi1_ipg_gate, ecspi1_per_gate, ecspi2_ipg_gate,
64 ecspi2_per_gate, cspi_ipg_gate, sdma_gate, emi_slow_gate, ipu_s, 64 ecspi2_per_gate, cspi_ipg_gate, sdma_gate, emi_slow_gate, ipu_s,
@@ -81,6 +81,7 @@ enum imx5_clks {
81 ssi1_root_podf, ssi2_root_pred, ssi2_root_podf, ssi_ext1_pred, 81 ssi1_root_podf, ssi2_root_pred, ssi2_root_podf, ssi_ext1_pred,
82 ssi_ext1_podf, ssi_ext2_pred, ssi_ext2_podf, ssi1_root_gate, 82 ssi_ext1_podf, ssi_ext2_pred, ssi_ext2_podf, ssi1_root_gate,
83 ssi2_root_gate, ssi3_root_gate, ssi_ext1_gate, ssi_ext2_gate, 83 ssi2_root_gate, ssi3_root_gate, ssi_ext1_gate, ssi_ext2_gate,
84 epit1_ipg_gate, epit1_hf_gate, epit2_ipg_gate, epit2_hf_gate,
84 clk_max 85 clk_max
85}; 86};
86 87
@@ -167,12 +168,12 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
167 clk[uart3_per_gate] = imx_clk_gate2("uart3_per_gate", "uart_root", MXC_CCM_CCGR1, 16); 168 clk[uart3_per_gate] = imx_clk_gate2("uart3_per_gate", "uart_root", MXC_CCM_CCGR1, 16);
168 clk[i2c1_gate] = imx_clk_gate2("i2c1_gate", "per_root", MXC_CCM_CCGR1, 18); 169 clk[i2c1_gate] = imx_clk_gate2("i2c1_gate", "per_root", MXC_CCM_CCGR1, 18);
169 clk[i2c2_gate] = imx_clk_gate2("i2c2_gate", "per_root", MXC_CCM_CCGR1, 20); 170 clk[i2c2_gate] = imx_clk_gate2("i2c2_gate", "per_root", MXC_CCM_CCGR1, 20);
170 clk[gpt_ipg_gate] = imx_clk_gate2("gpt_ipg_gate", "ipg", MXC_CCM_CCGR2, 20);
171 clk[pwm1_ipg_gate] = imx_clk_gate2("pwm1_ipg_gate", "ipg", MXC_CCM_CCGR2, 10); 171 clk[pwm1_ipg_gate] = imx_clk_gate2("pwm1_ipg_gate", "ipg", MXC_CCM_CCGR2, 10);
172 clk[pwm1_hf_gate] = imx_clk_gate2("pwm1_hf_gate", "ipg", MXC_CCM_CCGR2, 12); 172 clk[pwm1_hf_gate] = imx_clk_gate2("pwm1_hf_gate", "per_root", MXC_CCM_CCGR2, 12);
173 clk[pwm2_ipg_gate] = imx_clk_gate2("pwm2_ipg_gate", "ipg", MXC_CCM_CCGR2, 14); 173 clk[pwm2_ipg_gate] = imx_clk_gate2("pwm2_ipg_gate", "ipg", MXC_CCM_CCGR2, 14);
174 clk[pwm2_hf_gate] = imx_clk_gate2("pwm2_hf_gate", "ipg", MXC_CCM_CCGR2, 16); 174 clk[pwm2_hf_gate] = imx_clk_gate2("pwm2_hf_gate", "per_root", MXC_CCM_CCGR2, 16);
175 clk[gpt_gate] = imx_clk_gate2("gpt_gate", "per_root", MXC_CCM_CCGR2, 18); 175 clk[gpt_ipg_gate] = imx_clk_gate2("gpt_ipg_gate", "ipg", MXC_CCM_CCGR2, 18);
176 clk[gpt_hf_gate] = imx_clk_gate2("gpt_hf_gate", "per_root", MXC_CCM_CCGR2, 20);
176 clk[fec_gate] = imx_clk_gate2("fec_gate", "ipg", MXC_CCM_CCGR2, 24); 177 clk[fec_gate] = imx_clk_gate2("fec_gate", "ipg", MXC_CCM_CCGR2, 24);
177 clk[usboh3_gate] = imx_clk_gate2("usboh3_gate", "ipg", MXC_CCM_CCGR2, 26); 178 clk[usboh3_gate] = imx_clk_gate2("usboh3_gate", "ipg", MXC_CCM_CCGR2, 26);
178 clk[usboh3_per_gate] = imx_clk_gate2("usboh3_per_gate", "usboh3_podf", MXC_CCM_CCGR2, 28); 179 clk[usboh3_per_gate] = imx_clk_gate2("usboh3_per_gate", "usboh3_podf", MXC_CCM_CCGR2, 28);
@@ -226,13 +227,17 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
226 clk[ssi3_root_gate] = imx_clk_gate2("ssi3_root_gate", "ssi3_root_sel", MXC_CCM_CCGR3, 26); 227 clk[ssi3_root_gate] = imx_clk_gate2("ssi3_root_gate", "ssi3_root_sel", MXC_CCM_CCGR3, 26);
227 clk[ssi_ext1_gate] = imx_clk_gate2("ssi_ext1_gate", "ssi_ext1_com_sel", MXC_CCM_CCGR3, 28); 228 clk[ssi_ext1_gate] = imx_clk_gate2("ssi_ext1_gate", "ssi_ext1_com_sel", MXC_CCM_CCGR3, 28);
228 clk[ssi_ext2_gate] = imx_clk_gate2("ssi_ext2_gate", "ssi_ext2_com_sel", MXC_CCM_CCGR3, 30); 229 clk[ssi_ext2_gate] = imx_clk_gate2("ssi_ext2_gate", "ssi_ext2_com_sel", MXC_CCM_CCGR3, 30);
230 clk[epit1_ipg_gate] = imx_clk_gate2("epit1_ipg_gate", "ipg", MXC_CCM_CCGR2, 2);
231 clk[epit1_hf_gate] = imx_clk_gate2("epit1_hf_gate", "per_root", MXC_CCM_CCGR2, 4);
232 clk[epit2_ipg_gate] = imx_clk_gate2("epit2_ipg_gate", "ipg", MXC_CCM_CCGR2, 6);
233 clk[epit2_hf_gate] = imx_clk_gate2("epit2_hf_gate", "per_root", MXC_CCM_CCGR2, 8);
229 234
230 for (i = 0; i < ARRAY_SIZE(clk); i++) 235 for (i = 0; i < ARRAY_SIZE(clk); i++)
231 if (IS_ERR(clk[i])) 236 if (IS_ERR(clk[i]))
232 pr_err("i.MX5 clk %d: register failed with %ld\n", 237 pr_err("i.MX5 clk %d: register failed with %ld\n",
233 i, PTR_ERR(clk[i])); 238 i, PTR_ERR(clk[i]));
234 239
235 clk_register_clkdev(clk[gpt_gate], "per", "imx-gpt.0"); 240 clk_register_clkdev(clk[gpt_hf_gate], "per", "imx-gpt.0");
236 clk_register_clkdev(clk[gpt_ipg_gate], "ipg", "imx-gpt.0"); 241 clk_register_clkdev(clk[gpt_ipg_gate], "ipg", "imx-gpt.0");
237 clk_register_clkdev(clk[uart1_per_gate], "per", "imx21-uart.0"); 242 clk_register_clkdev(clk[uart1_per_gate], "per", "imx21-uart.0");
238 clk_register_clkdev(clk[uart1_ipg_gate], "ipg", "imx21-uart.0"); 243 clk_register_clkdev(clk[uart1_ipg_gate], "ipg", "imx21-uart.0");
@@ -248,7 +253,7 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
248 clk_register_clkdev(clk[ecspi1_ipg_gate], "ipg", "imx51-ecspi.0"); 253 clk_register_clkdev(clk[ecspi1_ipg_gate], "ipg", "imx51-ecspi.0");
249 clk_register_clkdev(clk[ecspi2_per_gate], "per", "imx51-ecspi.1"); 254 clk_register_clkdev(clk[ecspi2_per_gate], "per", "imx51-ecspi.1");
250 clk_register_clkdev(clk[ecspi2_ipg_gate], "ipg", "imx51-ecspi.1"); 255 clk_register_clkdev(clk[ecspi2_ipg_gate], "ipg", "imx51-ecspi.1");
251 clk_register_clkdev(clk[cspi_ipg_gate], NULL, "imx51-cspi.0"); 256 clk_register_clkdev(clk[cspi_ipg_gate], NULL, "imx35-cspi.2");
252 clk_register_clkdev(clk[pwm1_ipg_gate], "pwm", "mxc_pwm.0"); 257 clk_register_clkdev(clk[pwm1_ipg_gate], "pwm", "mxc_pwm.0");
253 clk_register_clkdev(clk[pwm2_ipg_gate], "pwm", "mxc_pwm.1"); 258 clk_register_clkdev(clk[pwm2_ipg_gate], "pwm", "mxc_pwm.1");
254 clk_register_clkdev(clk[i2c1_gate], NULL, "imx-i2c.0"); 259 clk_register_clkdev(clk[i2c1_gate], NULL, "imx-i2c.0");
@@ -280,6 +285,10 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
280 clk_register_clkdev(clk[tve_gate], NULL, "imx-tve.0"); 285 clk_register_clkdev(clk[tve_gate], NULL, "imx-tve.0");
281 clk_register_clkdev(clk[ipu_di1_gate], "di1", "imx-tve.0"); 286 clk_register_clkdev(clk[ipu_di1_gate], "di1", "imx-tve.0");
282 clk_register_clkdev(clk[gpc_dvfs], "gpc_dvfs", NULL); 287 clk_register_clkdev(clk[gpc_dvfs], "gpc_dvfs", NULL);
288 clk_register_clkdev(clk[epit1_ipg_gate], "ipg", "imx-epit.0");
289 clk_register_clkdev(clk[epit1_hf_gate], "per", "imx-epit.0");
290 clk_register_clkdev(clk[epit2_ipg_gate], "ipg", "imx-epit.1");
291 clk_register_clkdev(clk[epit2_hf_gate], "per", "imx-epit.1");
283 292
284 /* Set SDHC parents to be PLL2 */ 293 /* Set SDHC parents to be PLL2 */
285 clk_set_parent(clk[esdhc_a_sel], clk[pll2_sw]); 294 clk_set_parent(clk[esdhc_a_sel], clk[pll2_sw]);
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index b7a4ab65faca..f6a24b3f9c4f 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -172,6 +172,7 @@ obj-$(CONFIG_ARCH_OMAP3) += clkt_iclk.o
172obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) clock44xx_data.o 172obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) clock44xx_data.o
173obj-$(CONFIG_ARCH_OMAP4) += dpll3xxx.o dpll44xx.o 173obj-$(CONFIG_ARCH_OMAP4) += dpll3xxx.o dpll44xx.o
174obj-$(CONFIG_SOC_AM33XX) += $(clock-common) dpll3xxx.o 174obj-$(CONFIG_SOC_AM33XX) += $(clock-common) dpll3xxx.o
175obj-$(CONFIG_SOC_AM33XX) += clock33xx_data.o
175obj-$(CONFIG_SOC_OMAP5) += $(clock-common) 176obj-$(CONFIG_SOC_OMAP5) += $(clock-common)
176obj-$(CONFIG_SOC_OMAP5) += dpll3xxx.o dpll44xx.o 177obj-$(CONFIG_SOC_OMAP5) += dpll3xxx.o dpll44xx.o
177 178
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index a1bb23a23351..35ec5f3d9a73 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -155,4 +155,18 @@ extern const struct clkops clkops_omap3_noncore_dpll_ops;
155extern const struct clkops clkops_omap3_core_dpll_ops; 155extern const struct clkops clkops_omap3_core_dpll_ops;
156extern const struct clkops clkops_omap4_dpllmx_ops; 156extern const struct clkops clkops_omap4_dpllmx_ops;
157 157
158/* clksel_rate blocks shared between OMAP44xx and AM33xx */
159extern const struct clksel_rate div_1_0_rates[];
160extern const struct clksel_rate div_1_1_rates[];
161extern const struct clksel_rate div_1_2_rates[];
162extern const struct clksel_rate div_1_3_rates[];
163extern const struct clksel_rate div_1_4_rates[];
164extern const struct clksel_rate div31_1to31_rates[];
165
166/* clocks shared between various OMAP SoCs */
167extern struct clk virt_19200000_ck;
168extern struct clk virt_26000000_ck;
169
170extern int am33xx_clk_init(void);
171
158#endif 172#endif
diff --git a/arch/arm/mach-omap2/clock33xx_data.c b/arch/arm/mach-omap2/clock33xx_data.c
new file mode 100644
index 000000000000..25bbcc7ca4dc
--- /dev/null
+++ b/arch/arm/mach-omap2/clock33xx_data.c
@@ -0,0 +1,1105 @@
1/*
2 * AM33XX Clock data
3 *
4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
5 * Vaibhav Hiremath <hvaibhav@ti.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
10 *
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/kernel.h>
18#include <linux/list.h>
19#include <linux/clk.h>
20#include <plat/clkdev_omap.h>
21#include <plat/am33xx.h>
22
23#include "iomap.h"
24#include "control.h"
25#include "clock.h"
26#include "cm.h"
27#include "cm33xx.h"
28#include "cm-regbits-33xx.h"
29#include "prm.h"
30
31/* Maximum DPLL multiplier, divider values for AM33XX */
32#define AM33XX_MAX_DPLL_MULT 2047
33#define AM33XX_MAX_DPLL_DIV 128
34
35/* Modulemode control */
36#define AM33XX_MODULEMODE_HWCTRL 0
37#define AM33XX_MODULEMODE_SWCTRL 1
38
39/* TRM ERRATA: Timer 3 & 6 default parent (TCLKIN) may not be always
40 * physically present, in such a case HWMOD enabling of
41 * clock would be failure with default parent. And timer
42 * probe thinks clock is already enabled, this leads to
43 * crash upon accessing timer 3 & 6 registers in probe.
44 * Fix by setting parent of both these timers to master
45 * oscillator clock.
46 */
47static inline void am33xx_init_timer_parent(struct clk *clk)
48{
49 omap2_clksel_set_parent(clk, clk->parent);
50}
51
52/* Root clocks */
53
54/* RTC 32k */
55static struct clk clk_32768_ck = {
56 .name = "clk_32768_ck",
57 .clkdm_name = "l4_rtc_clkdm",
58 .rate = 32768,
59 .ops = &clkops_null,
60};
61
62/* On-Chip 32KHz RC OSC */
63static struct clk clk_rc32k_ck = {
64 .name = "clk_rc32k_ck",
65 .rate = 32000,
66 .ops = &clkops_null,
67};
68
69/* Crystal input clks */
70static struct clk virt_24000000_ck = {
71 .name = "virt_24000000_ck",
72 .rate = 24000000,
73 .ops = &clkops_null,
74};
75
76static struct clk virt_25000000_ck = {
77 .name = "virt_25000000_ck",
78 .rate = 25000000,
79 .ops = &clkops_null,
80};
81
82/* Oscillator clock */
83/* 19.2, 24, 25 or 26 MHz */
84static const struct clksel sys_clkin_sel[] = {
85 { .parent = &virt_19200000_ck, .rates = div_1_0_rates },
86 { .parent = &virt_24000000_ck, .rates = div_1_1_rates },
87 { .parent = &virt_25000000_ck, .rates = div_1_2_rates },
88 { .parent = &virt_26000000_ck, .rates = div_1_3_rates },
89 { .parent = NULL },
90};
91
92/* External clock - 12 MHz */
93static struct clk tclkin_ck = {
94 .name = "tclkin_ck",
95 .rate = 12000000,
96 .ops = &clkops_null,
97};
98
99/*
100 * sys_clk in: input to the dpll and also used as funtional clock for,
101 * adc_tsc, smartreflex0-1, timer1-7, mcasp0-1, dcan0-1, cefuse
102 *
103 */
104static struct clk sys_clkin_ck = {
105 .name = "sys_clkin_ck",
106 .parent = &virt_24000000_ck,
107 .init = &omap2_init_clksel_parent,
108 .clksel_reg = AM33XX_CTRL_REGADDR(AM33XX_CONTROL_STATUS),
109 .clksel_mask = AM33XX_CONTROL_STATUS_SYSBOOT1_MASK,
110 .clksel = sys_clkin_sel,
111 .ops = &clkops_null,
112 .recalc = &omap2_clksel_recalc,
113};
114
115/* DPLL_CORE */
116static struct dpll_data dpll_core_dd = {
117 .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_CORE,
118 .clk_bypass = &sys_clkin_ck,
119 .clk_ref = &sys_clkin_ck,
120 .control_reg = AM33XX_CM_CLKMODE_DPLL_CORE,
121 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
122 .idlest_reg = AM33XX_CM_IDLEST_DPLL_CORE,
123 .mult_mask = AM33XX_DPLL_MULT_MASK,
124 .div1_mask = AM33XX_DPLL_DIV_MASK,
125 .enable_mask = AM33XX_DPLL_EN_MASK,
126 .idlest_mask = AM33XX_ST_DPLL_CLK_MASK,
127 .max_multiplier = AM33XX_MAX_DPLL_MULT,
128 .max_divider = AM33XX_MAX_DPLL_DIV,
129 .min_divider = 1,
130};
131
132/* CLKDCOLDO output */
133static struct clk dpll_core_ck = {
134 .name = "dpll_core_ck",
135 .parent = &sys_clkin_ck,
136 .dpll_data = &dpll_core_dd,
137 .init = &omap2_init_dpll_parent,
138 .ops = &clkops_omap3_core_dpll_ops,
139 .recalc = &omap3_dpll_recalc,
140};
141
142static struct clk dpll_core_x2_ck = {
143 .name = "dpll_core_x2_ck",
144 .parent = &dpll_core_ck,
145 .flags = CLOCK_CLKOUTX2,
146 .ops = &clkops_null,
147 .recalc = &omap3_clkoutx2_recalc,
148};
149
150
151static const struct clksel dpll_core_m4_div[] = {
152 { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
153 { .parent = NULL },
154};
155
156static struct clk dpll_core_m4_ck = {
157 .name = "dpll_core_m4_ck",
158 .parent = &dpll_core_x2_ck,
159 .init = &omap2_init_clksel_parent,
160 .clksel = dpll_core_m4_div,
161 .clksel_reg = AM33XX_CM_DIV_M4_DPLL_CORE,
162 .clksel_mask = AM33XX_HSDIVIDER_CLKOUT1_DIV_MASK,
163 .ops = &clkops_null,
164 .recalc = &omap2_clksel_recalc,
165 .round_rate = &omap2_clksel_round_rate,
166 .set_rate = &omap2_clksel_set_rate,
167};
168
169static const struct clksel dpll_core_m5_div[] = {
170 { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
171 { .parent = NULL },
172};
173
174static struct clk dpll_core_m5_ck = {
175 .name = "dpll_core_m5_ck",
176 .parent = &dpll_core_x2_ck,
177 .init = &omap2_init_clksel_parent,
178 .clksel = dpll_core_m5_div,
179 .clksel_reg = AM33XX_CM_DIV_M5_DPLL_CORE,
180 .clksel_mask = AM33XX_HSDIVIDER_CLKOUT2_DIV_MASK,
181 .ops = &clkops_null,
182 .recalc = &omap2_clksel_recalc,
183 .round_rate = &omap2_clksel_round_rate,
184 .set_rate = &omap2_clksel_set_rate,
185};
186
187static const struct clksel dpll_core_m6_div[] = {
188 { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
189 { .parent = NULL },
190};
191
192static struct clk dpll_core_m6_ck = {
193 .name = "dpll_core_m6_ck",
194 .parent = &dpll_core_x2_ck,
195 .init = &omap2_init_clksel_parent,
196 .clksel = dpll_core_m6_div,
197 .clksel_reg = AM33XX_CM_DIV_M6_DPLL_CORE,
198 .clksel_mask = AM33XX_HSDIVIDER_CLKOUT3_DIV_MASK,
199 .ops = &clkops_null,
200 .recalc = &omap2_clksel_recalc,
201 .round_rate = &omap2_clksel_round_rate,
202 .set_rate = &omap2_clksel_set_rate,
203};
204
205/* DPLL_MPU */
206static struct dpll_data dpll_mpu_dd = {
207 .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_MPU,
208 .clk_bypass = &sys_clkin_ck,
209 .clk_ref = &sys_clkin_ck,
210 .control_reg = AM33XX_CM_CLKMODE_DPLL_MPU,
211 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
212 .idlest_reg = AM33XX_CM_IDLEST_DPLL_MPU,
213 .mult_mask = AM33XX_DPLL_MULT_MASK,
214 .div1_mask = AM33XX_DPLL_DIV_MASK,
215 .enable_mask = AM33XX_DPLL_EN_MASK,
216 .idlest_mask = AM33XX_ST_DPLL_CLK_MASK,
217 .max_multiplier = AM33XX_MAX_DPLL_MULT,
218 .max_divider = AM33XX_MAX_DPLL_DIV,
219 .min_divider = 1,
220};
221
222/* CLKOUT: fdpll/M2 */
223static struct clk dpll_mpu_ck = {
224 .name = "dpll_mpu_ck",
225 .parent = &sys_clkin_ck,
226 .dpll_data = &dpll_mpu_dd,
227 .init = &omap2_init_dpll_parent,
228 .ops = &clkops_omap3_noncore_dpll_ops,
229 .recalc = &omap3_dpll_recalc,
230 .round_rate = &omap2_dpll_round_rate,
231 .set_rate = &omap3_noncore_dpll_set_rate,
232};
233
234/*
235 * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
236 * and ALT_CLK1/2)
237 */
238static const struct clksel dpll_mpu_m2_div[] = {
239 { .parent = &dpll_mpu_ck, .rates = div31_1to31_rates },
240 { .parent = NULL },
241};
242
243static struct clk dpll_mpu_m2_ck = {
244 .name = "dpll_mpu_m2_ck",
245 .clkdm_name = "mpu_clkdm",
246 .parent = &dpll_mpu_ck,
247 .clksel = dpll_mpu_m2_div,
248 .clksel_reg = AM33XX_CM_DIV_M2_DPLL_MPU,
249 .clksel_mask = AM33XX_DPLL_CLKOUT_DIV_MASK,
250 .ops = &clkops_null,
251 .recalc = &omap2_clksel_recalc,
252 .round_rate = &omap2_clksel_round_rate,
253 .set_rate = &omap2_clksel_set_rate,
254};
255
256/* DPLL_DDR */
257static struct dpll_data dpll_ddr_dd = {
258 .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_DDR,
259 .clk_bypass = &sys_clkin_ck,
260 .clk_ref = &sys_clkin_ck,
261 .control_reg = AM33XX_CM_CLKMODE_DPLL_DDR,
262 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
263 .idlest_reg = AM33XX_CM_IDLEST_DPLL_DDR,
264 .mult_mask = AM33XX_DPLL_MULT_MASK,
265 .div1_mask = AM33XX_DPLL_DIV_MASK,
266 .enable_mask = AM33XX_DPLL_EN_MASK,
267 .idlest_mask = AM33XX_ST_DPLL_CLK_MASK,
268 .max_multiplier = AM33XX_MAX_DPLL_MULT,
269 .max_divider = AM33XX_MAX_DPLL_DIV,
270 .min_divider = 1,
271};
272
273/* CLKOUT: fdpll/M2 */
274static struct clk dpll_ddr_ck = {
275 .name = "dpll_ddr_ck",
276 .parent = &sys_clkin_ck,
277 .dpll_data = &dpll_ddr_dd,
278 .init = &omap2_init_dpll_parent,
279 .ops = &clkops_null,
280 .recalc = &omap3_dpll_recalc,
281};
282
283/*
284 * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
285 * and ALT_CLK1/2)
286 */
287static const struct clksel dpll_ddr_m2_div[] = {
288 { .parent = &dpll_ddr_ck, .rates = div31_1to31_rates },
289 { .parent = NULL },
290};
291
292static struct clk dpll_ddr_m2_ck = {
293 .name = "dpll_ddr_m2_ck",
294 .parent = &dpll_ddr_ck,
295 .clksel = dpll_ddr_m2_div,
296 .clksel_reg = AM33XX_CM_DIV_M2_DPLL_DDR,
297 .clksel_mask = AM33XX_DPLL_CLKOUT_DIV_MASK,
298 .ops = &clkops_null,
299 .recalc = &omap2_clksel_recalc,
300 .round_rate = &omap2_clksel_round_rate,
301 .set_rate = &omap2_clksel_set_rate,
302};
303
304/* emif_fck functional clock */
305static struct clk dpll_ddr_m2_div2_ck = {
306 .name = "dpll_ddr_m2_div2_ck",
307 .clkdm_name = "l3_clkdm",
308 .parent = &dpll_ddr_m2_ck,
309 .ops = &clkops_null,
310 .fixed_div = 2,
311 .recalc = &omap_fixed_divisor_recalc,
312};
313
314/* DPLL_DISP */
315static struct dpll_data dpll_disp_dd = {
316 .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_DISP,
317 .clk_bypass = &sys_clkin_ck,
318 .clk_ref = &sys_clkin_ck,
319 .control_reg = AM33XX_CM_CLKMODE_DPLL_DISP,
320 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
321 .idlest_reg = AM33XX_CM_IDLEST_DPLL_DISP,
322 .mult_mask = AM33XX_DPLL_MULT_MASK,
323 .div1_mask = AM33XX_DPLL_DIV_MASK,
324 .enable_mask = AM33XX_DPLL_EN_MASK,
325 .idlest_mask = AM33XX_ST_DPLL_CLK_MASK,
326 .max_multiplier = AM33XX_MAX_DPLL_MULT,
327 .max_divider = AM33XX_MAX_DPLL_DIV,
328 .min_divider = 1,
329};
330
331/* CLKOUT: fdpll/M2 */
332static struct clk dpll_disp_ck = {
333 .name = "dpll_disp_ck",
334 .parent = &sys_clkin_ck,
335 .dpll_data = &dpll_disp_dd,
336 .init = &omap2_init_dpll_parent,
337 .ops = &clkops_null,
338 .recalc = &omap3_dpll_recalc,
339 .round_rate = &omap2_dpll_round_rate,
340 .set_rate = &omap3_noncore_dpll_set_rate,
341};
342
343/*
344 * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
345 * and ALT_CLK1/2)
346 */
347static const struct clksel dpll_disp_m2_div[] = {
348 { .parent = &dpll_disp_ck, .rates = div31_1to31_rates },
349 { .parent = NULL },
350};
351
352static struct clk dpll_disp_m2_ck = {
353 .name = "dpll_disp_m2_ck",
354 .parent = &dpll_disp_ck,
355 .clksel = dpll_disp_m2_div,
356 .clksel_reg = AM33XX_CM_DIV_M2_DPLL_DISP,
357 .clksel_mask = AM33XX_DPLL_CLKOUT_DIV_MASK,
358 .ops = &clkops_null,
359 .recalc = &omap2_clksel_recalc,
360 .round_rate = &omap2_clksel_round_rate,
361 .set_rate = &omap2_clksel_set_rate,
362};
363
364/* DPLL_PER */
365static struct dpll_data dpll_per_dd = {
366 .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_PERIPH,
367 .clk_bypass = &sys_clkin_ck,
368 .clk_ref = &sys_clkin_ck,
369 .control_reg = AM33XX_CM_CLKMODE_DPLL_PER,
370 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
371 .idlest_reg = AM33XX_CM_IDLEST_DPLL_PER,
372 .mult_mask = AM33XX_DPLL_MULT_PERIPH_MASK,
373 .div1_mask = AM33XX_DPLL_PER_DIV_MASK,
374 .enable_mask = AM33XX_DPLL_EN_MASK,
375 .idlest_mask = AM33XX_ST_DPLL_CLK_MASK,
376 .max_multiplier = AM33XX_MAX_DPLL_MULT,
377 .max_divider = AM33XX_MAX_DPLL_DIV,
378 .min_divider = 1,
379 .flags = DPLL_J_TYPE,
380};
381
382/* CLKDCOLDO */
383static struct clk dpll_per_ck = {
384 .name = "dpll_per_ck",
385 .parent = &sys_clkin_ck,
386 .dpll_data = &dpll_per_dd,
387 .init = &omap2_init_dpll_parent,
388 .ops = &clkops_null,
389 .recalc = &omap3_dpll_recalc,
390 .round_rate = &omap2_dpll_round_rate,
391 .set_rate = &omap3_noncore_dpll_set_rate,
392};
393
394/* CLKOUT: fdpll/M2 */
395static const struct clksel dpll_per_m2_div[] = {
396 { .parent = &dpll_per_ck, .rates = div31_1to31_rates },
397 { .parent = NULL },
398};
399
400static struct clk dpll_per_m2_ck = {
401 .name = "dpll_per_m2_ck",
402 .parent = &dpll_per_ck,
403 .clksel = dpll_per_m2_div,
404 .clksel_reg = AM33XX_CM_DIV_M2_DPLL_PER,
405 .clksel_mask = AM33XX_DPLL_CLKOUT_DIV_MASK,
406 .ops = &clkops_null,
407 .recalc = &omap2_clksel_recalc,
408 .round_rate = &omap2_clksel_round_rate,
409 .set_rate = &omap2_clksel_set_rate,
410};
411
412static struct clk dpll_per_m2_div4_wkupdm_ck = {
413 .name = "dpll_per_m2_div4_wkupdm_ck",
414 .clkdm_name = "l4_wkup_clkdm",
415 .parent = &dpll_per_m2_ck,
416 .fixed_div = 4,
417 .ops = &clkops_null,
418 .recalc = &omap_fixed_divisor_recalc,
419};
420
421static struct clk dpll_per_m2_div4_ck = {
422 .name = "dpll_per_m2_div4_ck",
423 .clkdm_name = "l4ls_clkdm",
424 .parent = &dpll_per_m2_ck,
425 .fixed_div = 4,
426 .ops = &clkops_null,
427 .recalc = &omap_fixed_divisor_recalc,
428};
429
430static struct clk l3_gclk = {
431 .name = "l3_gclk",
432 .clkdm_name = "l3_clkdm",
433 .parent = &dpll_core_m4_ck,
434 .ops = &clkops_null,
435 .recalc = &followparent_recalc,
436};
437
438static struct clk dpll_core_m4_div2_ck = {
439 .name = "dpll_core_m4_div2_ck",
440 .clkdm_name = "l4_wkup_clkdm",
441 .parent = &dpll_core_m4_ck,
442 .ops = &clkops_null,
443 .fixed_div = 2,
444 .recalc = &omap_fixed_divisor_recalc,
445};
446
447static struct clk l4_rtc_gclk = {
448 .name = "l4_rtc_gclk",
449 .parent = &dpll_core_m4_ck,
450 .ops = &clkops_null,
451 .fixed_div = 2,
452 .recalc = &omap_fixed_divisor_recalc,
453};
454
455static struct clk clk_24mhz = {
456 .name = "clk_24mhz",
457 .parent = &dpll_per_m2_ck,
458 .fixed_div = 8,
459 .ops = &clkops_null,
460 .recalc = &omap_fixed_divisor_recalc,
461};
462
463/*
464 * Below clock nodes describes clockdomains derived out
465 * of core clock.
466 */
467static struct clk l4hs_gclk = {
468 .name = "l4hs_gclk",
469 .clkdm_name = "l4hs_clkdm",
470 .parent = &dpll_core_m4_ck,
471 .ops = &clkops_null,
472 .recalc = &followparent_recalc,
473};
474
475static struct clk l3s_gclk = {
476 .name = "l3s_gclk",
477 .clkdm_name = "l3s_clkdm",
478 .parent = &dpll_core_m4_div2_ck,
479 .ops = &clkops_null,
480 .recalc = &followparent_recalc,
481};
482
483static struct clk l4fw_gclk = {
484 .name = "l4fw_gclk",
485 .clkdm_name = "l4fw_clkdm",
486 .parent = &dpll_core_m4_div2_ck,
487 .ops = &clkops_null,
488 .recalc = &followparent_recalc,
489};
490
491static struct clk l4ls_gclk = {
492 .name = "l4ls_gclk",
493 .clkdm_name = "l4ls_clkdm",
494 .parent = &dpll_core_m4_div2_ck,
495 .ops = &clkops_null,
496 .recalc = &followparent_recalc,
497};
498
499static struct clk sysclk_div_ck = {
500 .name = "sysclk_div_ck",
501 .parent = &dpll_core_m4_ck,
502 .ops = &clkops_null,
503 .recalc = &followparent_recalc,
504};
505
506/*
507 * In order to match the clock domain with hwmod clockdomain entry,
508 * separate clock nodes is required for the modules which are
509 * directly getting their funtioncal clock from sys_clkin.
510 */
511static struct clk adc_tsc_fck = {
512 .name = "adc_tsc_fck",
513 .clkdm_name = "l4_wkup_clkdm",
514 .parent = &sys_clkin_ck,
515 .ops = &clkops_null,
516 .recalc = &followparent_recalc,
517};
518
519static struct clk dcan0_fck = {
520 .name = "dcan0_fck",
521 .clkdm_name = "l4ls_clkdm",
522 .parent = &sys_clkin_ck,
523 .ops = &clkops_null,
524 .recalc = &followparent_recalc,
525};
526
527static struct clk dcan1_fck = {
528 .name = "dcan1_fck",
529 .clkdm_name = "l4ls_clkdm",
530 .parent = &sys_clkin_ck,
531 .ops = &clkops_null,
532 .recalc = &followparent_recalc,
533};
534
535static struct clk mcasp0_fck = {
536 .name = "mcasp0_fck",
537 .clkdm_name = "l3s_clkdm",
538 .parent = &sys_clkin_ck,
539 .ops = &clkops_null,
540 .recalc = &followparent_recalc,
541};
542
543static struct clk mcasp1_fck = {
544 .name = "mcasp1_fck",
545 .clkdm_name = "l3s_clkdm",
546 .parent = &sys_clkin_ck,
547 .ops = &clkops_null,
548 .recalc = &followparent_recalc,
549};
550
551static struct clk smartreflex0_fck = {
552 .name = "smartreflex0_fck",
553 .clkdm_name = "l4_wkup_clkdm",
554 .parent = &sys_clkin_ck,
555 .ops = &clkops_null,
556 .recalc = &followparent_recalc,
557};
558
559static struct clk smartreflex1_fck = {
560 .name = "smartreflex1_fck",
561 .clkdm_name = "l4_wkup_clkdm",
562 .parent = &sys_clkin_ck,
563 .ops = &clkops_null,
564 .recalc = &followparent_recalc,
565};
566
567/*
568 * Modules clock nodes
569 *
570 * The following clock leaf nodes are added for the moment because:
571 *
572 * - hwmod data is not present for these modules, either hwmod
573 * control is not required or its not populated.
574 * - Driver code is not yet migrated to use hwmod/runtime pm
575 * - Modules outside kernel access (to disable them by default)
576 *
577 * - debugss
578 * - mmu (gfx domain)
579 * - cefuse
580 * - usbotg_fck (its additional clock and not really a modulemode)
581 * - ieee5000
582 */
583static struct clk debugss_ick = {
584 .name = "debugss_ick",
585 .clkdm_name = "l3_aon_clkdm",
586 .parent = &dpll_core_m4_ck,
587 .ops = &clkops_omap2_dflt,
588 .enable_reg = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
589 .enable_bit = AM33XX_MODULEMODE_SWCTRL,
590 .recalc = &followparent_recalc,
591};
592
593static struct clk mmu_fck = {
594 .name = "mmu_fck",
595 .clkdm_name = "gfx_l3_clkdm",
596 .parent = &dpll_core_m4_ck,
597 .ops = &clkops_omap2_dflt,
598 .enable_reg = AM33XX_CM_GFX_MMUDATA_CLKCTRL,
599 .enable_bit = AM33XX_MODULEMODE_SWCTRL,
600 .recalc = &followparent_recalc,
601};
602
603static struct clk cefuse_fck = {
604 .name = "cefuse_fck",
605 .clkdm_name = "l4_cefuse_clkdm",
606 .parent = &sys_clkin_ck,
607 .enable_reg = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL,
608 .enable_bit = AM33XX_MODULEMODE_SWCTRL,
609 .ops = &clkops_omap2_dflt,
610 .recalc = &followparent_recalc,
611};
612
613/*
614 * clkdiv32 is generated from fixed division of 732.4219
615 */
616static struct clk clkdiv32k_ick = {
617 .name = "clkdiv32k_ick",
618 .clkdm_name = "clk_24mhz_clkdm",
619 .rate = 32768,
620 .parent = &clk_24mhz,
621 .enable_reg = AM33XX_CM_PER_CLKDIV32K_CLKCTRL,
622 .enable_bit = AM33XX_MODULEMODE_SWCTRL,
623 .ops = &clkops_omap2_dflt,
624};
625
626static struct clk usbotg_fck = {
627 .name = "usbotg_fck",
628 .clkdm_name = "l3s_clkdm",
629 .parent = &dpll_per_ck,
630 .enable_reg = AM33XX_CM_CLKDCOLDO_DPLL_PER,
631 .enable_bit = AM33XX_ST_DPLL_CLKDCOLDO_SHIFT,
632 .ops = &clkops_omap2_dflt,
633 .recalc = &followparent_recalc,
634};
635
636static struct clk ieee5000_fck = {
637 .name = "ieee5000_fck",
638 .clkdm_name = "l3s_clkdm",
639 .parent = &dpll_core_m4_div2_ck,
640 .enable_reg = AM33XX_CM_PER_IEEE5000_CLKCTRL,
641 .enable_bit = AM33XX_MODULEMODE_SWCTRL,
642 .ops = &clkops_omap2_dflt,
643 .recalc = &followparent_recalc,
644};
645
646/* Timers */
647static const struct clksel timer1_clkmux_sel[] = {
648 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
649 { .parent = &clkdiv32k_ick, .rates = div_1_1_rates },
650 { .parent = &tclkin_ck, .rates = div_1_2_rates },
651 { .parent = &clk_rc32k_ck, .rates = div_1_3_rates },
652 { .parent = &clk_32768_ck, .rates = div_1_4_rates },
653 { .parent = NULL },
654};
655
656static struct clk timer1_fck = {
657 .name = "timer1_fck",
658 .clkdm_name = "l4ls_clkdm",
659 .parent = &sys_clkin_ck,
660 .init = &omap2_init_clksel_parent,
661 .clksel = timer1_clkmux_sel,
662 .clksel_reg = AM33XX_CLKSEL_TIMER1MS_CLK,
663 .clksel_mask = AM33XX_CLKSEL_0_2_MASK,
664 .ops = &clkops_null,
665 .recalc = &omap2_clksel_recalc,
666};
667
668static const struct clksel timer2_to_7_clk_sel[] = {
669 { .parent = &tclkin_ck, .rates = div_1_0_rates },
670 { .parent = &sys_clkin_ck, .rates = div_1_1_rates },
671 { .parent = &clkdiv32k_ick, .rates = div_1_2_rates },
672 { .parent = NULL },
673};
674
675static struct clk timer2_fck = {
676 .name = "timer2_fck",
677 .clkdm_name = "l4ls_clkdm",
678 .parent = &sys_clkin_ck,
679 .init = &omap2_init_clksel_parent,
680 .clksel = timer2_to_7_clk_sel,
681 .clksel_reg = AM33XX_CLKSEL_TIMER2_CLK,
682 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
683 .ops = &clkops_null,
684 .recalc = &omap2_clksel_recalc,
685};
686
687static struct clk timer3_fck = {
688 .name = "timer3_fck",
689 .clkdm_name = "l4ls_clkdm",
690 .parent = &sys_clkin_ck,
691 .init = &am33xx_init_timer_parent,
692 .clksel = timer2_to_7_clk_sel,
693 .clksel_reg = AM33XX_CLKSEL_TIMER3_CLK,
694 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
695 .ops = &clkops_null,
696 .recalc = &omap2_clksel_recalc,
697};
698
699static struct clk timer4_fck = {
700 .name = "timer4_fck",
701 .clkdm_name = "l4ls_clkdm",
702 .parent = &sys_clkin_ck,
703 .init = &omap2_init_clksel_parent,
704 .clksel = timer2_to_7_clk_sel,
705 .clksel_reg = AM33XX_CLKSEL_TIMER4_CLK,
706 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
707 .ops = &clkops_null,
708 .recalc = &omap2_clksel_recalc,
709};
710
711static struct clk timer5_fck = {
712 .name = "timer5_fck",
713 .clkdm_name = "l4ls_clkdm",
714 .parent = &sys_clkin_ck,
715 .init = &omap2_init_clksel_parent,
716 .clksel = timer2_to_7_clk_sel,
717 .clksel_reg = AM33XX_CLKSEL_TIMER5_CLK,
718 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
719 .ops = &clkops_null,
720 .recalc = &omap2_clksel_recalc,
721};
722
723static struct clk timer6_fck = {
724 .name = "timer6_fck",
725 .clkdm_name = "l4ls_clkdm",
726 .parent = &sys_clkin_ck,
727 .init = &am33xx_init_timer_parent,
728 .clksel = timer2_to_7_clk_sel,
729 .clksel_reg = AM33XX_CLKSEL_TIMER6_CLK,
730 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
731 .ops = &clkops_null,
732 .recalc = &omap2_clksel_recalc,
733};
734
735static struct clk timer7_fck = {
736 .name = "timer7_fck",
737 .clkdm_name = "l4ls_clkdm",
738 .parent = &sys_clkin_ck,
739 .init = &omap2_init_clksel_parent,
740 .clksel = timer2_to_7_clk_sel,
741 .clksel_reg = AM33XX_CLKSEL_TIMER7_CLK,
742 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
743 .ops = &clkops_null,
744 .recalc = &omap2_clksel_recalc,
745};
746
747static struct clk cpsw_125mhz_gclk = {
748 .name = "cpsw_125mhz_gclk",
749 .clkdm_name = "cpsw_125mhz_clkdm",
750 .parent = &dpll_core_m5_ck,
751 .ops = &clkops_null,
752 .fixed_div = 2,
753 .recalc = &omap_fixed_divisor_recalc,
754};
755
756static const struct clksel cpsw_cpts_rft_clkmux_sel[] = {
757 { .parent = &dpll_core_m5_ck, .rates = div_1_0_rates },
758 { .parent = &dpll_core_m4_ck, .rates = div_1_1_rates },
759 { .parent = NULL },
760};
761
762static struct clk cpsw_cpts_rft_clk = {
763 .name = "cpsw_cpts_rft_clk",
764 .clkdm_name = "cpsw_125mhz_clkdm",
765 .parent = &dpll_core_m5_ck,
766 .clksel = cpsw_cpts_rft_clkmux_sel,
767 .clksel_reg = AM33XX_CM_CPTS_RFT_CLKSEL,
768 .clksel_mask = AM33XX_CLKSEL_0_0_MASK,
769 .ops = &clkops_null,
770 .recalc = &followparent_recalc,
771};
772
773/* gpio */
774static const struct clksel gpio0_dbclk_mux_sel[] = {
775 { .parent = &clk_rc32k_ck, .rates = div_1_0_rates },
776 { .parent = &clk_32768_ck, .rates = div_1_1_rates },
777 { .parent = &clkdiv32k_ick, .rates = div_1_2_rates },
778 { .parent = NULL },
779};
780
781static struct clk gpio0_dbclk_mux_ck = {
782 .name = "gpio0_dbclk_mux_ck",
783 .clkdm_name = "l4_wkup_clkdm",
784 .parent = &clk_rc32k_ck,
785 .init = &omap2_init_clksel_parent,
786 .clksel = gpio0_dbclk_mux_sel,
787 .clksel_reg = AM33XX_CLKSEL_GPIO0_DBCLK,
788 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
789 .ops = &clkops_null,
790 .recalc = &omap2_clksel_recalc,
791};
792
793static struct clk gpio0_dbclk = {
794 .name = "gpio0_dbclk",
795 .clkdm_name = "l4_wkup_clkdm",
796 .parent = &gpio0_dbclk_mux_ck,
797 .enable_reg = AM33XX_CM_WKUP_GPIO0_CLKCTRL,
798 .enable_bit = AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT,
799 .ops = &clkops_omap2_dflt,
800 .recalc = &followparent_recalc,
801};
802
803static struct clk gpio1_dbclk = {
804 .name = "gpio1_dbclk",
805 .clkdm_name = "l4ls_clkdm",
806 .parent = &clkdiv32k_ick,
807 .enable_reg = AM33XX_CM_PER_GPIO1_CLKCTRL,
808 .enable_bit = AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT,
809 .ops = &clkops_omap2_dflt,
810 .recalc = &followparent_recalc,
811};
812
813static struct clk gpio2_dbclk = {
814 .name = "gpio2_dbclk",
815 .clkdm_name = "l4ls_clkdm",
816 .parent = &clkdiv32k_ick,
817 .enable_reg = AM33XX_CM_PER_GPIO2_CLKCTRL,
818 .enable_bit = AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT,
819 .ops = &clkops_omap2_dflt,
820 .recalc = &followparent_recalc,
821};
822
823static struct clk gpio3_dbclk = {
824 .name = "gpio3_dbclk",
825 .clkdm_name = "l4ls_clkdm",
826 .parent = &clkdiv32k_ick,
827 .enable_reg = AM33XX_CM_PER_GPIO3_CLKCTRL,
828 .enable_bit = AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT,
829 .ops = &clkops_omap2_dflt,
830 .recalc = &followparent_recalc,
831};
832
833static const struct clksel pruss_ocp_clk_mux_sel[] = {
834 { .parent = &l3_gclk, .rates = div_1_0_rates },
835 { .parent = &dpll_disp_m2_ck, .rates = div_1_1_rates },
836 { .parent = NULL },
837};
838
839static struct clk pruss_ocp_gclk = {
840 .name = "pruss_ocp_gclk",
841 .clkdm_name = "pruss_ocp_clkdm",
842 .parent = &l3_gclk,
843 .init = &omap2_init_clksel_parent,
844 .clksel = pruss_ocp_clk_mux_sel,
845 .clksel_reg = AM33XX_CLKSEL_PRUSS_OCP_CLK,
846 .clksel_mask = AM33XX_CLKSEL_0_0_MASK,
847 .ops = &clkops_null,
848 .recalc = &followparent_recalc,
849};
850
851static const struct clksel lcd_clk_mux_sel[] = {
852 { .parent = &dpll_disp_m2_ck, .rates = div_1_0_rates },
853 { .parent = &dpll_core_m5_ck, .rates = div_1_1_rates },
854 { .parent = &dpll_per_m2_ck, .rates = div_1_2_rates },
855 { .parent = NULL },
856};
857
858static struct clk lcd_gclk = {
859 .name = "lcd_gclk",
860 .clkdm_name = "lcdc_clkdm",
861 .parent = &dpll_disp_m2_ck,
862 .init = &omap2_init_clksel_parent,
863 .clksel = lcd_clk_mux_sel,
864 .clksel_reg = AM33XX_CLKSEL_LCDC_PIXEL_CLK,
865 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
866 .ops = &clkops_null,
867 .recalc = &followparent_recalc,
868};
869
870static struct clk mmc_clk = {
871 .name = "mmc_clk",
872 .clkdm_name = "l4ls_clkdm",
873 .parent = &dpll_per_m2_ck,
874 .ops = &clkops_null,
875 .fixed_div = 2,
876 .recalc = &omap_fixed_divisor_recalc,
877};
878
879static struct clk mmc2_fck = {
880 .name = "mmc2_fck",
881 .clkdm_name = "l3s_clkdm",
882 .parent = &mmc_clk,
883 .ops = &clkops_null,
884 .recalc = &followparent_recalc,
885};
886
887static const struct clksel gfx_clksel_sel[] = {
888 { .parent = &dpll_core_m4_ck, .rates = div_1_0_rates },
889 { .parent = &dpll_per_m2_ck, .rates = div_1_1_rates },
890 { .parent = NULL },
891};
892
893static struct clk gfx_fclk_clksel_ck = {
894 .name = "gfx_fclk_clksel_ck",
895 .parent = &dpll_core_m4_ck,
896 .clksel = gfx_clksel_sel,
897 .ops = &clkops_null,
898 .clksel_reg = AM33XX_CLKSEL_GFX_FCLK,
899 .clksel_mask = AM33XX_CLKSEL_GFX_FCLK_MASK,
900 .recalc = &omap2_clksel_recalc,
901};
902
903static const struct clksel_rate div_1_0_2_1_rates[] = {
904 { .div = 1, .val = 0, .flags = RATE_IN_AM33XX },
905 { .div = 2, .val = 1, .flags = RATE_IN_AM33XX },
906 { .div = 0 },
907};
908
909static const struct clksel gfx_div_sel[] = {
910 { .parent = &gfx_fclk_clksel_ck, .rates = div_1_0_2_1_rates },
911 { .parent = NULL },
912};
913
914static struct clk gfx_fck_div_ck = {
915 .name = "gfx_fck_div_ck",
916 .clkdm_name = "gfx_l3_clkdm",
917 .parent = &gfx_fclk_clksel_ck,
918 .init = &omap2_init_clksel_parent,
919 .clksel = gfx_div_sel,
920 .clksel_reg = AM33XX_CLKSEL_GFX_FCLK,
921 .clksel_mask = AM33XX_CLKSEL_0_0_MASK,
922 .recalc = &omap2_clksel_recalc,
923 .round_rate = &omap2_clksel_round_rate,
924 .set_rate = &omap2_clksel_set_rate,
925 .ops = &clkops_null,
926};
927
928static const struct clksel sysclkout_pre_sel[] = {
929 { .parent = &clk_32768_ck, .rates = div_1_0_rates },
930 { .parent = &l3_gclk, .rates = div_1_1_rates },
931 { .parent = &dpll_ddr_m2_ck, .rates = div_1_2_rates },
932 { .parent = &dpll_per_m2_ck, .rates = div_1_3_rates },
933 { .parent = &lcd_gclk, .rates = div_1_4_rates },
934 { .parent = NULL },
935};
936
937static struct clk sysclkout_pre_ck = {
938 .name = "sysclkout_pre_ck",
939 .parent = &clk_32768_ck,
940 .init = &omap2_init_clksel_parent,
941 .clksel = sysclkout_pre_sel,
942 .clksel_reg = AM33XX_CM_CLKOUT_CTRL,
943 .clksel_mask = AM33XX_CLKOUT2SOURCE_MASK,
944 .ops = &clkops_null,
945 .recalc = &omap2_clksel_recalc,
946};
947
948/* Divide by 8 clock rates with default clock is 1/1*/
949static const struct clksel_rate div8_rates[] = {
950 { .div = 1, .val = 0, .flags = RATE_IN_AM33XX },
951 { .div = 2, .val = 1, .flags = RATE_IN_AM33XX },
952 { .div = 3, .val = 2, .flags = RATE_IN_AM33XX },
953 { .div = 4, .val = 3, .flags = RATE_IN_AM33XX },
954 { .div = 5, .val = 4, .flags = RATE_IN_AM33XX },
955 { .div = 6, .val = 5, .flags = RATE_IN_AM33XX },
956 { .div = 7, .val = 6, .flags = RATE_IN_AM33XX },
957 { .div = 8, .val = 7, .flags = RATE_IN_AM33XX },
958 { .div = 0 },
959};
960
961static const struct clksel clkout2_div[] = {
962 { .parent = &sysclkout_pre_ck, .rates = div8_rates },
963 { .parent = NULL },
964};
965
966static struct clk clkout2_ck = {
967 .name = "clkout2_ck",
968 .parent = &sysclkout_pre_ck,
969 .ops = &clkops_omap2_dflt,
970 .clksel = clkout2_div,
971 .clksel_reg = AM33XX_CM_CLKOUT_CTRL,
972 .clksel_mask = AM33XX_CLKOUT2DIV_MASK,
973 .enable_reg = AM33XX_CM_CLKOUT_CTRL,
974 .enable_bit = AM33XX_CLKOUT2EN_SHIFT,
975 .recalc = &omap2_clksel_recalc,
976 .round_rate = &omap2_clksel_round_rate,
977 .set_rate = &omap2_clksel_set_rate,
978};
979
980static const struct clksel wdt_clkmux_sel[] = {
981 { .parent = &clk_rc32k_ck, .rates = div_1_0_rates },
982 { .parent = &clkdiv32k_ick, .rates = div_1_1_rates },
983 { .parent = NULL },
984};
985
986static struct clk wdt1_fck = {
987 .name = "wdt1_fck",
988 .clkdm_name = "l4_wkup_clkdm",
989 .parent = &clk_rc32k_ck,
990 .init = &omap2_init_clksel_parent,
991 .clksel = wdt_clkmux_sel,
992 .clksel_reg = AM33XX_CLKSEL_WDT1_CLK,
993 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
994 .ops = &clkops_null,
995 .recalc = &omap2_clksel_recalc,
996};
997
998/*
999 * clkdev
1000 */
1001static struct omap_clk am33xx_clks[] = {
1002 CLK(NULL, "clk_32768_ck", &clk_32768_ck, CK_AM33XX),
1003 CLK(NULL, "clk_rc32k_ck", &clk_rc32k_ck, CK_AM33XX),
1004 CLK(NULL, "virt_19200000_ck", &virt_19200000_ck, CK_AM33XX),
1005 CLK(NULL, "virt_24000000_ck", &virt_24000000_ck, CK_AM33XX),
1006 CLK(NULL, "virt_25000000_ck", &virt_25000000_ck, CK_AM33XX),
1007 CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_AM33XX),
1008 CLK(NULL, "sys_clkin_ck", &sys_clkin_ck, CK_AM33XX),
1009 CLK(NULL, "tclkin_ck", &tclkin_ck, CK_AM33XX),
1010 CLK(NULL, "dpll_core_ck", &dpll_core_ck, CK_AM33XX),
1011 CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck, CK_AM33XX),
1012 CLK(NULL, "dpll_core_m4_ck", &dpll_core_m4_ck, CK_AM33XX),
1013 CLK(NULL, "dpll_core_m5_ck", &dpll_core_m5_ck, CK_AM33XX),
1014 CLK(NULL, "dpll_core_m6_ck", &dpll_core_m6_ck, CK_AM33XX),
1015 CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_AM33XX),
1016 CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_AM33XX),
1017 CLK(NULL, "dpll_ddr_ck", &dpll_ddr_ck, CK_AM33XX),
1018 CLK(NULL, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck, CK_AM33XX),
1019 CLK(NULL, "dpll_ddr_m2_div2_ck", &dpll_ddr_m2_div2_ck, CK_AM33XX),
1020 CLK(NULL, "dpll_disp_ck", &dpll_disp_ck, CK_AM33XX),
1021 CLK(NULL, "dpll_disp_m2_ck", &dpll_disp_m2_ck, CK_AM33XX),
1022 CLK(NULL, "dpll_per_ck", &dpll_per_ck, CK_AM33XX),
1023 CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck, CK_AM33XX),
1024 CLK(NULL, "dpll_per_m2_div4_wkupdm_ck", &dpll_per_m2_div4_wkupdm_ck, CK_AM33XX),
1025 CLK(NULL, "dpll_per_m2_div4_ck", &dpll_per_m2_div4_ck, CK_AM33XX),
1026 CLK(NULL, "adc_tsc_fck", &adc_tsc_fck, CK_AM33XX),
1027 CLK(NULL, "cefuse_fck", &cefuse_fck, CK_AM33XX),
1028 CLK(NULL, "clkdiv32k_ick", &clkdiv32k_ick, CK_AM33XX),
1029 CLK(NULL, "dcan0_fck", &dcan0_fck, CK_AM33XX),
1030 CLK(NULL, "dcan1_fck", &dcan1_fck, CK_AM33XX),
1031 CLK(NULL, "debugss_ick", &debugss_ick, CK_AM33XX),
1032 CLK(NULL, "pruss_ocp_gclk", &pruss_ocp_gclk, CK_AM33XX),
1033 CLK("davinci-mcasp.0", NULL, &mcasp0_fck, CK_AM33XX),
1034 CLK("davinci-mcasp.1", NULL, &mcasp1_fck, CK_AM33XX),
1035 CLK("NULL", "mmc2_fck", &mmc2_fck, CK_AM33XX),
1036 CLK(NULL, "mmu_fck", &mmu_fck, CK_AM33XX),
1037 CLK(NULL, "smartreflex0_fck", &smartreflex0_fck, CK_AM33XX),
1038 CLK(NULL, "smartreflex1_fck", &smartreflex1_fck, CK_AM33XX),
1039 CLK(NULL, "gpt1_fck", &timer1_fck, CK_AM33XX),
1040 CLK(NULL, "gpt2_fck", &timer2_fck, CK_AM33XX),
1041 CLK(NULL, "gpt3_fck", &timer3_fck, CK_AM33XX),
1042 CLK(NULL, "gpt4_fck", &timer4_fck, CK_AM33XX),
1043 CLK(NULL, "gpt5_fck", &timer5_fck, CK_AM33XX),
1044 CLK(NULL, "gpt6_fck", &timer6_fck, CK_AM33XX),
1045 CLK(NULL, "gpt7_fck", &timer7_fck, CK_AM33XX),
1046 CLK(NULL, "usbotg_fck", &usbotg_fck, CK_AM33XX),
1047 CLK(NULL, "ieee5000_fck", &ieee5000_fck, CK_AM33XX),
1048 CLK(NULL, "wdt1_fck", &wdt1_fck, CK_AM33XX),
1049 CLK(NULL, "l4_rtc_gclk", &l4_rtc_gclk, CK_AM33XX),
1050 CLK(NULL, "l3_gclk", &l3_gclk, CK_AM33XX),
1051 CLK(NULL, "dpll_core_m4_div2_ck", &dpll_core_m4_div2_ck, CK_AM33XX),
1052 CLK(NULL, "l4hs_gclk", &l4hs_gclk, CK_AM33XX),
1053 CLK(NULL, "l3s_gclk", &l3s_gclk, CK_AM33XX),
1054 CLK(NULL, "l4fw_gclk", &l4fw_gclk, CK_AM33XX),
1055 CLK(NULL, "l4ls_gclk", &l4ls_gclk, CK_AM33XX),
1056 CLK(NULL, "clk_24mhz", &clk_24mhz, CK_AM33XX),
1057 CLK(NULL, "sysclk_div_ck", &sysclk_div_ck, CK_AM33XX),
1058 CLK(NULL, "cpsw_125mhz_gclk", &cpsw_125mhz_gclk, CK_AM33XX),
1059 CLK(NULL, "cpsw_cpts_rft_clk", &cpsw_cpts_rft_clk, CK_AM33XX),
1060 CLK(NULL, "gpio0_dbclk_mux_ck", &gpio0_dbclk_mux_ck, CK_AM33XX),
1061 CLK(NULL, "gpio0_dbclk", &gpio0_dbclk, CK_AM33XX),
1062 CLK(NULL, "gpio1_dbclk", &gpio1_dbclk, CK_AM33XX),
1063 CLK(NULL, "gpio2_dbclk", &gpio2_dbclk, CK_AM33XX),
1064 CLK(NULL, "gpio3_dbclk", &gpio3_dbclk, CK_AM33XX),
1065 CLK(NULL, "lcd_gclk", &lcd_gclk, CK_AM33XX),
1066 CLK(NULL, "mmc_clk", &mmc_clk, CK_AM33XX),
1067 CLK(NULL, "gfx_fclk_clksel_ck", &gfx_fclk_clksel_ck, CK_AM33XX),
1068 CLK(NULL, "gfx_fck_div_ck", &gfx_fck_div_ck, CK_AM33XX),
1069 CLK(NULL, "sysclkout_pre_ck", &sysclkout_pre_ck, CK_AM33XX),
1070 CLK(NULL, "clkout2_ck", &clkout2_ck, CK_AM33XX),
1071};
1072
1073int __init am33xx_clk_init(void)
1074{
1075 struct omap_clk *c;
1076 u32 cpu_clkflg;
1077
1078 if (soc_is_am33xx()) {
1079 cpu_mask = RATE_IN_AM33XX;
1080 cpu_clkflg = CK_AM33XX;
1081 }
1082
1083 clk_init(&omap2_clk_functions);
1084
1085 for (c = am33xx_clks; c < am33xx_clks + ARRAY_SIZE(am33xx_clks); c++)
1086 clk_preinit(c->lk.clk);
1087
1088 for (c = am33xx_clks; c < am33xx_clks + ARRAY_SIZE(am33xx_clks); c++) {
1089 if (c->cpu & cpu_clkflg) {
1090 clkdev_add(&c->lk);
1091 clk_register(c->lk.clk);
1092 omap2_init_clk_clkdm(c->lk.clk);
1093 }
1094 }
1095
1096 recalculate_root_clocks();
1097
1098 /*
1099 * Only enable those clocks we will need, let the drivers
1100 * enable other clocks as necessary
1101 */
1102 clk_enable_init_clocks();
1103
1104 return 0;
1105}
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index c3e91d0dd2f2..91b3d5c60bfe 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -93,18 +93,6 @@ static struct clk virt_16_8m_ck = {
93 .rate = 16800000, 93 .rate = 16800000,
94}; 94};
95 95
96static struct clk virt_19_2m_ck = {
97 .name = "virt_19_2m_ck",
98 .ops = &clkops_null,
99 .rate = 19200000,
100};
101
102static struct clk virt_26m_ck = {
103 .name = "virt_26m_ck",
104 .ops = &clkops_null,
105 .rate = 26000000,
106};
107
108static struct clk virt_38_4m_ck = { 96static struct clk virt_38_4m_ck = {
109 .name = "virt_38_4m_ck", 97 .name = "virt_38_4m_ck",
110 .ops = &clkops_null, 98 .ops = &clkops_null,
@@ -145,8 +133,8 @@ static const struct clksel osc_sys_clksel[] = {
145 { .parent = &virt_12m_ck, .rates = osc_sys_12m_rates }, 133 { .parent = &virt_12m_ck, .rates = osc_sys_12m_rates },
146 { .parent = &virt_13m_ck, .rates = osc_sys_13m_rates }, 134 { .parent = &virt_13m_ck, .rates = osc_sys_13m_rates },
147 { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates }, 135 { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
148 { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates }, 136 { .parent = &virt_19200000_ck, .rates = osc_sys_19_2m_rates },
149 { .parent = &virt_26m_ck, .rates = osc_sys_26m_rates }, 137 { .parent = &virt_26000000_ck, .rates = osc_sys_26m_rates },
150 { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates }, 138 { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
151 { .parent = NULL }, 139 { .parent = NULL },
152}; 140};
@@ -3234,8 +3222,8 @@ static struct omap_clk omap3xxx_clks[] = {
3234 CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_3XXX), 3222 CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_3XXX),
3235 CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_3XXX), 3223 CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_3XXX),
3236 CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3224 CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3237 CLK(NULL, "virt_19_2m_ck", &virt_19_2m_ck, CK_3XXX), 3225 CLK(NULL, "virt_19200000_ck", &virt_19200000_ck, CK_3XXX),
3238 CLK(NULL, "virt_26m_ck", &virt_26m_ck, CK_3XXX), 3226 CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_3XXX),
3239 CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck, CK_3XXX), 3227 CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck, CK_3XXX),
3240 CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_3XXX), 3228 CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_3XXX),
3241 CLK(NULL, "sys_ck", &sys_ck, CK_3XXX), 3229 CLK(NULL, "sys_ck", &sys_ck, CK_3XXX),
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index 1b0b049fe445..d7f55e43b761 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -107,18 +107,6 @@ static struct clk virt_16800000_ck = {
107 .rate = 16800000, 107 .rate = 16800000,
108}; 108};
109 109
110static struct clk virt_19200000_ck = {
111 .name = "virt_19200000_ck",
112 .ops = &clkops_null,
113 .rate = 19200000,
114};
115
116static struct clk virt_26000000_ck = {
117 .name = "virt_26000000_ck",
118 .ops = &clkops_null,
119 .rate = 26000000,
120};
121
122static struct clk virt_27000000_ck = { 110static struct clk virt_27000000_ck = {
123 .name = "virt_27000000_ck", 111 .name = "virt_27000000_ck",
124 .ops = &clkops_null, 112 .ops = &clkops_null,
@@ -131,31 +119,6 @@ static struct clk virt_38400000_ck = {
131 .rate = 38400000, 119 .rate = 38400000,
132}; 120};
133 121
134static const struct clksel_rate div_1_0_rates[] = {
135 { .div = 1, .val = 0, .flags = RATE_IN_4430 },
136 { .div = 0 },
137};
138
139static const struct clksel_rate div_1_1_rates[] = {
140 { .div = 1, .val = 1, .flags = RATE_IN_4430 },
141 { .div = 0 },
142};
143
144static const struct clksel_rate div_1_2_rates[] = {
145 { .div = 1, .val = 2, .flags = RATE_IN_4430 },
146 { .div = 0 },
147};
148
149static const struct clksel_rate div_1_3_rates[] = {
150 { .div = 1, .val = 3, .flags = RATE_IN_4430 },
151 { .div = 0 },
152};
153
154static const struct clksel_rate div_1_4_rates[] = {
155 { .div = 1, .val = 4, .flags = RATE_IN_4430 },
156 { .div = 0 },
157};
158
159static const struct clksel_rate div_1_5_rates[] = { 122static const struct clksel_rate div_1_5_rates[] = {
160 { .div = 1, .val = 5, .flags = RATE_IN_4430 }, 123 { .div = 1, .val = 5, .flags = RATE_IN_4430 },
161 { .div = 0 }, 124 { .div = 0 },
@@ -289,41 +252,6 @@ static struct clk dpll_abe_x2_ck = {
289 .recalc = &omap3_clkoutx2_recalc, 252 .recalc = &omap3_clkoutx2_recalc,
290}; 253};
291 254
292static const struct clksel_rate div31_1to31_rates[] = {
293 { .div = 1, .val = 1, .flags = RATE_IN_4430 },
294 { .div = 2, .val = 2, .flags = RATE_IN_4430 },
295 { .div = 3, .val = 3, .flags = RATE_IN_4430 },
296 { .div = 4, .val = 4, .flags = RATE_IN_4430 },
297 { .div = 5, .val = 5, .flags = RATE_IN_4430 },
298 { .div = 6, .val = 6, .flags = RATE_IN_4430 },
299 { .div = 7, .val = 7, .flags = RATE_IN_4430 },
300 { .div = 8, .val = 8, .flags = RATE_IN_4430 },
301 { .div = 9, .val = 9, .flags = RATE_IN_4430 },
302 { .div = 10, .val = 10, .flags = RATE_IN_4430 },
303 { .div = 11, .val = 11, .flags = RATE_IN_4430 },
304 { .div = 12, .val = 12, .flags = RATE_IN_4430 },
305 { .div = 13, .val = 13, .flags = RATE_IN_4430 },
306 { .div = 14, .val = 14, .flags = RATE_IN_4430 },
307 { .div = 15, .val = 15, .flags = RATE_IN_4430 },
308 { .div = 16, .val = 16, .flags = RATE_IN_4430 },
309 { .div = 17, .val = 17, .flags = RATE_IN_4430 },
310 { .div = 18, .val = 18, .flags = RATE_IN_4430 },
311 { .div = 19, .val = 19, .flags = RATE_IN_4430 },
312 { .div = 20, .val = 20, .flags = RATE_IN_4430 },
313 { .div = 21, .val = 21, .flags = RATE_IN_4430 },
314 { .div = 22, .val = 22, .flags = RATE_IN_4430 },
315 { .div = 23, .val = 23, .flags = RATE_IN_4430 },
316 { .div = 24, .val = 24, .flags = RATE_IN_4430 },
317 { .div = 25, .val = 25, .flags = RATE_IN_4430 },
318 { .div = 26, .val = 26, .flags = RATE_IN_4430 },
319 { .div = 27, .val = 27, .flags = RATE_IN_4430 },
320 { .div = 28, .val = 28, .flags = RATE_IN_4430 },
321 { .div = 29, .val = 29, .flags = RATE_IN_4430 },
322 { .div = 30, .val = 30, .flags = RATE_IN_4430 },
323 { .div = 31, .val = 31, .flags = RATE_IN_4430 },
324 { .div = 0 },
325};
326
327static const struct clksel dpll_abe_m2x2_div[] = { 255static const struct clksel dpll_abe_m2x2_div[] = {
328 { .parent = &dpll_abe_x2_ck, .rates = div31_1to31_rates }, 256 { .parent = &dpll_abe_x2_ck, .rates = div31_1to31_rates },
329 { .parent = NULL }, 257 { .parent = NULL },
diff --git a/arch/arm/mach-omap2/clock_common_data.c b/arch/arm/mach-omap2/clock_common_data.c
index 6424d46be14a..b9f3ba68148c 100644
--- a/arch/arm/mach-omap2/clock_common_data.c
+++ b/arch/arm/mach-omap2/clock_common_data.c
@@ -43,3 +43,80 @@ const struct clksel_rate dsp_ick_rates[] = {
43 { .div = 3, .val = 3, .flags = RATE_IN_243X }, 43 { .div = 3, .val = 3, .flags = RATE_IN_243X },
44 { .div = 0 }, 44 { .div = 0 },
45}; 45};
46
47
48/* clksel_rate blocks shared between OMAP44xx and AM33xx */
49
50const struct clksel_rate div_1_0_rates[] = {
51 { .div = 1, .val = 0, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
52 { .div = 0 },
53};
54
55const struct clksel_rate div_1_1_rates[] = {
56 { .div = 1, .val = 1, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
57 { .div = 0 },
58};
59
60const struct clksel_rate div_1_2_rates[] = {
61 { .div = 1, .val = 2, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
62 { .div = 0 },
63};
64
65const struct clksel_rate div_1_3_rates[] = {
66 { .div = 1, .val = 3, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
67 { .div = 0 },
68};
69
70const struct clksel_rate div_1_4_rates[] = {
71 { .div = 1, .val = 4, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
72 { .div = 0 },
73};
74
75const struct clksel_rate div31_1to31_rates[] = {
76 { .div = 1, .val = 1, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
77 { .div = 2, .val = 2, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
78 { .div = 3, .val = 3, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
79 { .div = 4, .val = 4, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
80 { .div = 5, .val = 5, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
81 { .div = 6, .val = 6, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
82 { .div = 7, .val = 7, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
83 { .div = 8, .val = 8, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
84 { .div = 9, .val = 9, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
85 { .div = 10, .val = 10, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
86 { .div = 11, .val = 11, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
87 { .div = 12, .val = 12, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
88 { .div = 13, .val = 13, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
89 { .div = 14, .val = 14, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
90 { .div = 15, .val = 15, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
91 { .div = 16, .val = 16, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
92 { .div = 17, .val = 17, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
93 { .div = 18, .val = 18, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
94 { .div = 19, .val = 19, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
95 { .div = 20, .val = 20, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
96 { .div = 21, .val = 21, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
97 { .div = 22, .val = 22, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
98 { .div = 23, .val = 23, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
99 { .div = 24, .val = 24, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
100 { .div = 25, .val = 25, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
101 { .div = 26, .val = 26, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
102 { .div = 27, .val = 27, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
103 { .div = 28, .val = 28, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
104 { .div = 29, .val = 29, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
105 { .div = 30, .val = 30, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
106 { .div = 31, .val = 31, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
107 { .div = 0 },
108};
109
110/* Clocks shared between various OMAP SoCs */
111
112struct clk virt_19200000_ck = {
113 .name = "virt_19200000_ck",
114 .ops = &clkops_null,
115 .rate = 19200000,
116};
117
118struct clk virt_26000000_ck = {
119 .name = "virt_26000000_ck",
120 .ops = &clkops_null,
121 .rate = 26000000,
122};
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 8976be90c8e8..4d2d981ff5c5 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -38,6 +38,7 @@
38#include "powerdomain.h" 38#include "powerdomain.h"
39#include "clockdomain.h" 39#include "clockdomain.h"
40#include "common.h" 40#include "common.h"
41#include "clock.h"
41#include "clock2xxx.h" 42#include "clock2xxx.h"
42#include "clock3xxx.h" 43#include "clock3xxx.h"
43#include "clock44xx.h" 44#include "clock44xx.h"
@@ -522,6 +523,7 @@ void __init am33xx_init_early(void)
522 am33xx_voltagedomains_init(); 523 am33xx_voltagedomains_init();
523 am33xx_powerdomains_init(); 524 am33xx_powerdomains_init();
524 am33xx_clockdomains_init(); 525 am33xx_clockdomains_init();
526 am33xx_clk_init();
525} 527}
526#endif 528#endif
527 529
diff --git a/arch/arm/mach-tegra/cpu-tegra.c b/arch/arm/mach-tegra/cpu-tegra.c
index 7a065f0cf633..ceb52db1e2f1 100644
--- a/arch/arm/mach-tegra/cpu-tegra.c
+++ b/arch/arm/mach-tegra/cpu-tegra.c
@@ -189,8 +189,8 @@ static int tegra_cpu_init(struct cpufreq_policy *policy)
189 return PTR_ERR(emc_clk); 189 return PTR_ERR(emc_clk);
190 } 190 }
191 191
192 clk_enable(emc_clk); 192 clk_prepare_enable(emc_clk);
193 clk_enable(cpu_clk); 193 clk_prepare_enable(cpu_clk);
194 194
195 cpufreq_frequency_table_cpuinfo(policy, freq_table); 195 cpufreq_frequency_table_cpuinfo(policy, freq_table);
196 cpufreq_frequency_table_get_attr(freq_table, policy->cpu); 196 cpufreq_frequency_table_get_attr(freq_table, policy->cpu);
@@ -212,7 +212,7 @@ static int tegra_cpu_init(struct cpufreq_policy *policy)
212static int tegra_cpu_exit(struct cpufreq_policy *policy) 212static int tegra_cpu_exit(struct cpufreq_policy *policy)
213{ 213{
214 cpufreq_frequency_table_cpuinfo(policy, freq_table); 214 cpufreq_frequency_table_cpuinfo(policy, freq_table);
215 clk_disable(emc_clk); 215 clk_disable_unprepare(emc_clk);
216 clk_put(emc_clk); 216 clk_put(emc_clk);
217 clk_put(cpu_clk); 217 clk_put(cpu_clk);
218 return 0; 218 return 0;
diff --git a/arch/arm/mach-tegra/dma.c b/arch/arm/mach-tegra/dma.c
index abea4f6e2dd5..29c5114d607c 100644
--- a/arch/arm/mach-tegra/dma.c
+++ b/arch/arm/mach-tegra/dma.c
@@ -714,13 +714,13 @@ int __init tegra_dma_init(void)
714 714
715 bitmap_fill(channel_usage, NV_DMA_MAX_CHANNELS); 715 bitmap_fill(channel_usage, NV_DMA_MAX_CHANNELS);
716 716
717 c = clk_get_sys("tegra-dma", NULL); 717 c = clk_get_sys("tegra-apbdma", NULL);
718 if (IS_ERR(c)) { 718 if (IS_ERR(c)) {
719 pr_err("Unable to get clock for APB DMA\n"); 719 pr_err("Unable to get clock for APB DMA\n");
720 ret = PTR_ERR(c); 720 ret = PTR_ERR(c);
721 goto fail; 721 goto fail;
722 } 722 }
723 ret = clk_enable(c); 723 ret = clk_prepare_enable(c);
724 if (ret != 0) { 724 if (ret != 0) {
725 pr_err("Unable to enable clock for APB DMA\n"); 725 pr_err("Unable to enable clock for APB DMA\n");
726 goto fail; 726 goto fail;
diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c
index 0e09137506ec..d3ad5150d660 100644
--- a/arch/arm/mach-tegra/pcie.c
+++ b/arch/arm/mach-tegra/pcie.c
@@ -723,9 +723,9 @@ static int tegra_pcie_power_regate(void)
723 723
724 tegra_pcie_xclk_clamp(false); 724 tegra_pcie_xclk_clamp(false);
725 725
726 clk_enable(tegra_pcie.afi_clk); 726 clk_prepare_enable(tegra_pcie.afi_clk);
727 clk_enable(tegra_pcie.pex_clk); 727 clk_prepare_enable(tegra_pcie.pex_clk);
728 return clk_enable(tegra_pcie.pll_e); 728 return clk_prepare_enable(tegra_pcie.pll_e);
729} 729}
730 730
731static int tegra_pcie_clocks_get(void) 731static int tegra_pcie_clocks_get(void)
diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c
index f5b12fb4ff12..15d506501ccc 100644
--- a/arch/arm/mach-tegra/powergate.c
+++ b/arch/arm/mach-tegra/powergate.c
@@ -146,7 +146,7 @@ int tegra_powergate_sequence_power_up(int id, struct clk *clk)
146 if (ret) 146 if (ret)
147 goto err_power; 147 goto err_power;
148 148
149 ret = clk_enable(clk); 149 ret = clk_prepare_enable(clk);
150 if (ret) 150 if (ret)
151 goto err_clk; 151 goto err_clk;
152 152
@@ -162,7 +162,7 @@ int tegra_powergate_sequence_power_up(int id, struct clk *clk)
162 return 0; 162 return 0;
163 163
164err_clamp: 164err_clamp:
165 clk_disable(clk); 165 clk_disable_unprepare(clk);
166err_clk: 166err_clk:
167 tegra_powergate_power_off(id); 167 tegra_powergate_power_off(id);
168err_power: 168err_power:
diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c
index b59315ce3691..a703844b2061 100644
--- a/arch/arm/mach-tegra/tegra2_clocks.c
+++ b/arch/arm/mach-tegra/tegra2_clocks.c
@@ -69,6 +69,8 @@
69 69
70#define PERIPH_CLK_SOURCE_MASK (3<<30) 70#define PERIPH_CLK_SOURCE_MASK (3<<30)
71#define PERIPH_CLK_SOURCE_SHIFT 30 71#define PERIPH_CLK_SOURCE_SHIFT 30
72#define PERIPH_CLK_SOURCE_PWM_MASK (7<<28)
73#define PERIPH_CLK_SOURCE_PWM_SHIFT 28
72#define PERIPH_CLK_SOURCE_ENABLE (1<<28) 74#define PERIPH_CLK_SOURCE_ENABLE (1<<28)
73#define PERIPH_CLK_SOURCE_DIVU71_MASK 0xFF 75#define PERIPH_CLK_SOURCE_DIVU71_MASK 0xFF
74#define PERIPH_CLK_SOURCE_DIVU16_MASK 0xFFFF 76#define PERIPH_CLK_SOURCE_DIVU16_MASK 0xFFFF
@@ -908,9 +910,20 @@ static void tegra2_periph_clk_init(struct clk *c)
908 u32 val = clk_readl(c->reg); 910 u32 val = clk_readl(c->reg);
909 const struct clk_mux_sel *mux = NULL; 911 const struct clk_mux_sel *mux = NULL;
910 const struct clk_mux_sel *sel; 912 const struct clk_mux_sel *sel;
913 u32 shift;
914 u32 mask;
915
916 if (c->flags & MUX_PWM) {
917 shift = PERIPH_CLK_SOURCE_PWM_SHIFT;
918 mask = PERIPH_CLK_SOURCE_PWM_MASK;
919 } else {
920 shift = PERIPH_CLK_SOURCE_SHIFT;
921 mask = PERIPH_CLK_SOURCE_MASK;
922 }
923
911 if (c->flags & MUX) { 924 if (c->flags & MUX) {
912 for (sel = c->inputs; sel->input != NULL; sel++) { 925 for (sel = c->inputs; sel->input != NULL; sel++) {
913 if (val >> PERIPH_CLK_SOURCE_SHIFT == sel->value) 926 if ((val & mask) >> shift == sel->value)
914 mux = sel; 927 mux = sel;
915 } 928 }
916 BUG_ON(!mux); 929 BUG_ON(!mux);
@@ -1023,12 +1036,23 @@ static int tegra2_periph_clk_set_parent(struct clk *c, struct clk *p)
1023{ 1036{
1024 u32 val; 1037 u32 val;
1025 const struct clk_mux_sel *sel; 1038 const struct clk_mux_sel *sel;
1039 u32 mask, shift;
1040
1026 pr_debug("%s: %s %s\n", __func__, c->name, p->name); 1041 pr_debug("%s: %s %s\n", __func__, c->name, p->name);
1042
1043 if (c->flags & MUX_PWM) {
1044 shift = PERIPH_CLK_SOURCE_PWM_SHIFT;
1045 mask = PERIPH_CLK_SOURCE_PWM_MASK;
1046 } else {
1047 shift = PERIPH_CLK_SOURCE_SHIFT;
1048 mask = PERIPH_CLK_SOURCE_MASK;
1049 }
1050
1027 for (sel = c->inputs; sel->input != NULL; sel++) { 1051 for (sel = c->inputs; sel->input != NULL; sel++) {
1028 if (sel->input == p) { 1052 if (sel->input == p) {
1029 val = clk_readl(c->reg); 1053 val = clk_readl(c->reg);
1030 val &= ~PERIPH_CLK_SOURCE_MASK; 1054 val &= ~mask;
1031 val |= (sel->value) << PERIPH_CLK_SOURCE_SHIFT; 1055 val |= (sel->value) << shift;
1032 1056
1033 if (c->refcnt) 1057 if (c->refcnt)
1034 clk_enable(p); 1058 clk_enable(p);
@@ -2149,14 +2173,14 @@ static struct clk tegra_clk_emc = {
2149 } 2173 }
2150 2174
2151static struct clk tegra_list_clks[] = { 2175static struct clk tegra_list_clks[] = {
2152 PERIPH_CLK("apbdma", "tegra-dma", NULL, 34, 0, 108000000, mux_pclk, 0), 2176 PERIPH_CLK("apbdma", "tegra-apbdma", NULL, 34, 0, 108000000, mux_pclk, 0),
2153 PERIPH_CLK("rtc", "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET), 2177 PERIPH_CLK("rtc", "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET),
2154 PERIPH_CLK("timer", "timer", NULL, 5, 0, 26000000, mux_clk_m, 0), 2178 PERIPH_CLK("timer", "timer", NULL, 5, 0, 26000000, mux_clk_m, 0),
2155 PERIPH_CLK("i2s1", "tegra20-i2s.0", NULL, 11, 0x100, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71), 2179 PERIPH_CLK("i2s1", "tegra20-i2s.0", NULL, 11, 0x100, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71),
2156 PERIPH_CLK("i2s2", "tegra20-i2s.1", NULL, 18, 0x104, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71), 2180 PERIPH_CLK("i2s2", "tegra20-i2s.1", NULL, 18, 0x104, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71),
2157 PERIPH_CLK("spdif_out", "spdif_out", NULL, 10, 0x108, 100000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71), 2181 PERIPH_CLK("spdif_out", "spdif_out", NULL, 10, 0x108, 100000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71),
2158 PERIPH_CLK("spdif_in", "spdif_in", NULL, 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71), 2182 PERIPH_CLK("spdif_in", "spdif_in", NULL, 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71),
2159 PERIPH_CLK("pwm", "pwm", NULL, 17, 0x110, 432000000, mux_pllp_pllc_audio_clkm_clk32, MUX | DIV_U71), 2183 PERIPH_CLK("pwm", "tegra-pwm", NULL, 17, 0x110, 432000000, mux_pllp_pllc_audio_clkm_clk32, MUX | DIV_U71 | MUX_PWM),
2160 PERIPH_CLK("spi", "spi", NULL, 43, 0x114, 40000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), 2184 PERIPH_CLK("spi", "spi", NULL, 43, 0x114, 40000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2161 PERIPH_CLK("xio", "xio", NULL, 45, 0x120, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), 2185 PERIPH_CLK("xio", "xio", NULL, 45, 0x120, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2162 PERIPH_CLK("twc", "twc", NULL, 16, 0x12c, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), 2186 PERIPH_CLK("twc", "twc", NULL, 16, 0x12c, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
@@ -2189,11 +2213,11 @@ static struct clk tegra_list_clks[] = {
2189 PERIPH_CLK("i2c2_i2c", "tegra-i2c.1", "i2c", 0, 0, 72000000, mux_pllp_out3, 0), 2213 PERIPH_CLK("i2c2_i2c", "tegra-i2c.1", "i2c", 0, 0, 72000000, mux_pllp_out3, 0),
2190 PERIPH_CLK("i2c3_i2c", "tegra-i2c.2", "i2c", 0, 0, 72000000, mux_pllp_out3, 0), 2214 PERIPH_CLK("i2c3_i2c", "tegra-i2c.2", "i2c", 0, 0, 72000000, mux_pllp_out3, 0),
2191 PERIPH_CLK("dvc_i2c", "tegra-i2c.3", "i2c", 0, 0, 72000000, mux_pllp_out3, 0), 2215 PERIPH_CLK("dvc_i2c", "tegra-i2c.3", "i2c", 0, 0, 72000000, mux_pllp_out3, 0),
2192 PERIPH_CLK("uarta", "uart.0", NULL, 6, 0x178, 600000000, mux_pllp_pllc_pllm_clkm, MUX), 2216 PERIPH_CLK("uarta", "tegra-uart.0", NULL, 6, 0x178, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
2193 PERIPH_CLK("uartb", "uart.1", NULL, 7, 0x17c, 600000000, mux_pllp_pllc_pllm_clkm, MUX), 2217 PERIPH_CLK("uartb", "tegra-uart.1", NULL, 7, 0x17c, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
2194 PERIPH_CLK("uartc", "uart.2", NULL, 55, 0x1a0, 600000000, mux_pllp_pllc_pllm_clkm, MUX), 2218 PERIPH_CLK("uartc", "tegra-uart.2", NULL, 55, 0x1a0, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
2195 PERIPH_CLK("uartd", "uart.3", NULL, 65, 0x1c0, 600000000, mux_pllp_pllc_pllm_clkm, MUX), 2219 PERIPH_CLK("uartd", "tegra-uart.3", NULL, 65, 0x1c0, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
2196 PERIPH_CLK("uarte", "uart.4", NULL, 66, 0x1c4, 600000000, mux_pllp_pllc_pllm_clkm, MUX), 2220 PERIPH_CLK("uarte", "tegra-uart.4", NULL, 66, 0x1c4, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
2197 PERIPH_CLK("3d", "3d", NULL, 24, 0x158, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_MANUAL_RESET), /* scales with voltage and process_id */ 2221 PERIPH_CLK("3d", "3d", NULL, 24, 0x158, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_MANUAL_RESET), /* scales with voltage and process_id */
2198 PERIPH_CLK("2d", "2d", NULL, 21, 0x15c, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */ 2222 PERIPH_CLK("2d", "2d", NULL, 21, 0x15c, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
2199 PERIPH_CLK("vi", "tegra_camera", "vi", 20, 0x148, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */ 2223 PERIPH_CLK("vi", "tegra_camera", "vi", 20, 0x148, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
@@ -2245,20 +2269,16 @@ static struct clk tegra_list_clks[] = {
2245 * table under two names. 2269 * table under two names.
2246 */ 2270 */
2247static struct clk_duplicate tegra_clk_duplicates[] = { 2271static struct clk_duplicate tegra_clk_duplicates[] = {
2248 CLK_DUPLICATE("uarta", "tegra_uart.0", NULL), 2272 CLK_DUPLICATE("uarta", "serial8250.0", NULL),
2249 CLK_DUPLICATE("uartb", "tegra_uart.1", NULL), 2273 CLK_DUPLICATE("uartb", "serial8250.1", NULL),
2250 CLK_DUPLICATE("uartc", "tegra_uart.2", NULL), 2274 CLK_DUPLICATE("uartc", "serial8250.2", NULL),
2251 CLK_DUPLICATE("uartd", "tegra_uart.3", NULL), 2275 CLK_DUPLICATE("uartd", "serial8250.3", NULL),
2252 CLK_DUPLICATE("uarte", "tegra_uart.4", NULL), 2276 CLK_DUPLICATE("uarte", "serial8250.4", NULL),
2253 CLK_DUPLICATE("usbd", "utmip-pad", NULL), 2277 CLK_DUPLICATE("usbd", "utmip-pad", NULL),
2254 CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL), 2278 CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
2255 CLK_DUPLICATE("usbd", "tegra-otg", NULL), 2279 CLK_DUPLICATE("usbd", "tegra-otg", NULL),
2256 CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"), 2280 CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"),
2257 CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"), 2281 CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"),
2258 CLK_DUPLICATE("pwm", "tegra_pwm.0", NULL),
2259 CLK_DUPLICATE("pwm", "tegra_pwm.1", NULL),
2260 CLK_DUPLICATE("pwm", "tegra_pwm.2", NULL),
2261 CLK_DUPLICATE("pwm", "tegra_pwm.3", NULL),
2262 CLK_DUPLICATE("host1x", "tegra_grhost", "host1x"), 2282 CLK_DUPLICATE("host1x", "tegra_grhost", "host1x"),
2263 CLK_DUPLICATE("2d", "tegra_grhost", "gr2d"), 2283 CLK_DUPLICATE("2d", "tegra_grhost", "gr2d"),
2264 CLK_DUPLICATE("3d", "tegra_grhost", "gr3d"), 2284 CLK_DUPLICATE("3d", "tegra_grhost", "gr3d"),
diff --git a/arch/arm/mach-tegra/tegra30_clocks.c b/arch/arm/mach-tegra/tegra30_clocks.c
index e33fe4b14a2a..6674f100e16f 100644
--- a/arch/arm/mach-tegra/tegra30_clocks.c
+++ b/arch/arm/mach-tegra/tegra30_clocks.c
@@ -2871,7 +2871,7 @@ static struct clk tegra30_clk_twd = {
2871 }, \ 2871 }, \
2872 } 2872 }
2873struct clk tegra_list_clks[] = { 2873struct clk tegra_list_clks[] = {
2874 PERIPH_CLK("apbdma", "tegra-dma", NULL, 34, 0, 26000000, mux_clk_m, 0), 2874 PERIPH_CLK("apbdma", "tegra-apbdma", NULL, 34, 0, 26000000, mux_clk_m, 0),
2875 PERIPH_CLK("rtc", "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB), 2875 PERIPH_CLK("rtc", "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB),
2876 PERIPH_CLK("kbc", "tegra-kbc", NULL, 36, 0, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB), 2876 PERIPH_CLK("kbc", "tegra-kbc", NULL, 36, 0, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB),
2877 PERIPH_CLK("timer", "timer", NULL, 5, 0, 26000000, mux_clk_m, 0), 2877 PERIPH_CLK("timer", "timer", NULL, 5, 0, 26000000, mux_clk_m, 0),
@@ -2886,7 +2886,7 @@ struct clk tegra_list_clks[] = {
2886 PERIPH_CLK("i2s4", "tegra30-i2s.4", NULL, 102, 0x3c0, 26000000, mux_pllaout0_audio4_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB), 2886 PERIPH_CLK("i2s4", "tegra30-i2s.4", NULL, 102, 0x3c0, 26000000, mux_pllaout0_audio4_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2887 PERIPH_CLK("spdif_out", "tegra30-spdif", "spdif_out", 10, 0x108, 100000000, mux_pllaout0_audio_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB), 2887 PERIPH_CLK("spdif_out", "tegra30-spdif", "spdif_out", 10, 0x108, 100000000, mux_pllaout0_audio_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2888 PERIPH_CLK("spdif_in", "tegra30-spdif", "spdif_in", 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71 | PERIPH_ON_APB), 2888 PERIPH_CLK("spdif_in", "tegra30-spdif", "spdif_in", 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71 | PERIPH_ON_APB),
2889 PERIPH_CLK("pwm", "pwm", NULL, 17, 0x110, 432000000, mux_pllp_pllc_clk32_clkm, MUX | MUX_PWM | DIV_U71 | PERIPH_ON_APB), 2889 PERIPH_CLK("pwm", "tegra-pwm", NULL, 17, 0x110, 432000000, mux_pllp_pllc_clk32_clkm, MUX | MUX_PWM | DIV_U71 | PERIPH_ON_APB),
2890 PERIPH_CLK("d_audio", "tegra30-ahub", "d_audio", 106, 0x3d0, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71), 2890 PERIPH_CLK("d_audio", "tegra30-ahub", "d_audio", 106, 0x3d0, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71),
2891 PERIPH_CLK("dam0", "tegra30-dam.0", NULL, 108, 0x3d8, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71), 2891 PERIPH_CLK("dam0", "tegra30-dam.0", NULL, 108, 0x3d8, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71),
2892 PERIPH_CLK("dam1", "tegra30-dam.1", NULL, 109, 0x3dc, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71), 2892 PERIPH_CLK("dam1", "tegra30-dam.1", NULL, 109, 0x3dc, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71),
@@ -2924,16 +2924,11 @@ struct clk tegra_list_clks[] = {
2924 PERIPH_CLK("i2c3", "tegra-i2c.2", NULL, 67, 0x1b8, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB), 2924 PERIPH_CLK("i2c3", "tegra-i2c.2", NULL, 67, 0x1b8, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
2925 PERIPH_CLK("i2c4", "tegra-i2c.3", NULL, 103, 0x3c4, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB), 2925 PERIPH_CLK("i2c4", "tegra-i2c.3", NULL, 103, 0x3c4, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
2926 PERIPH_CLK("i2c5", "tegra-i2c.4", NULL, 47, 0x128, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB), 2926 PERIPH_CLK("i2c5", "tegra-i2c.4", NULL, 47, 0x128, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
2927 PERIPH_CLK("uarta", "tegra_uart.0", NULL, 6, 0x178, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB), 2927 PERIPH_CLK("uarta", "tegra-uart.0", NULL, 6, 0x178, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
2928 PERIPH_CLK("uartb", "tegra_uart.1", NULL, 7, 0x17c, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB), 2928 PERIPH_CLK("uartb", "tegra-uart.1", NULL, 7, 0x17c, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
2929 PERIPH_CLK("uartc", "tegra_uart.2", NULL, 55, 0x1a0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB), 2929 PERIPH_CLK("uartc", "tegra-uart.2", NULL, 55, 0x1a0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
2930 PERIPH_CLK("uartd", "tegra_uart.3", NULL, 65, 0x1c0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB), 2930 PERIPH_CLK("uartd", "tegra-uart.3", NULL, 65, 0x1c0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
2931 PERIPH_CLK("uarte", "tegra_uart.4", NULL, 66, 0x1c4, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB), 2931 PERIPH_CLK("uarte", "tegra-uart.4", NULL, 66, 0x1c4, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
2932 PERIPH_CLK("uarta_dbg", "serial8250.0", "uarta", 6, 0x178, 800000000, mux_pllp_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
2933 PERIPH_CLK("uartb_dbg", "serial8250.0", "uartb", 7, 0x17c, 800000000, mux_pllp_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
2934 PERIPH_CLK("uartc_dbg", "serial8250.0", "uartc", 55, 0x1a0, 800000000, mux_pllp_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
2935 PERIPH_CLK("uartd_dbg", "serial8250.0", "uartd", 65, 0x1c0, 800000000, mux_pllp_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
2936 PERIPH_CLK("uarte_dbg", "serial8250.0", "uarte", 66, 0x1c4, 800000000, mux_pllp_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
2937 PERIPH_CLK_EX("vi", "tegra_camera", "vi", 20, 0x148, 425000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT, &tegra_vi_clk_ops), 2932 PERIPH_CLK_EX("vi", "tegra_camera", "vi", 20, 0x148, 425000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT, &tegra_vi_clk_ops),
2938 PERIPH_CLK("3d", "3d", NULL, 24, 0x158, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET), 2933 PERIPH_CLK("3d", "3d", NULL, 24, 0x158, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET),
2939 PERIPH_CLK("3d2", "3d2", NULL, 98, 0x3b0, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET), 2934 PERIPH_CLK("3d2", "3d2", NULL, 98, 0x3b0, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET),
@@ -2983,6 +2978,11 @@ struct clk tegra_list_clks[] = {
2983 * table under two names. 2978 * table under two names.
2984 */ 2979 */
2985struct clk_duplicate tegra_clk_duplicates[] = { 2980struct clk_duplicate tegra_clk_duplicates[] = {
2981 CLK_DUPLICATE("uarta", "serial8250.0", NULL),
2982 CLK_DUPLICATE("uartb", "serial8250.1", NULL),
2983 CLK_DUPLICATE("uartc", "serial8250.2", NULL),
2984 CLK_DUPLICATE("uartd", "serial8250.3", NULL),
2985 CLK_DUPLICATE("uarte", "serial8250.4", NULL),
2986 CLK_DUPLICATE("usbd", "utmip-pad", NULL), 2986 CLK_DUPLICATE("usbd", "utmip-pad", NULL),
2987 CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL), 2987 CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
2988 CLK_DUPLICATE("usbd", "tegra-otg", NULL), 2988 CLK_DUPLICATE("usbd", "tegra-otg", NULL),
@@ -2990,10 +2990,6 @@ struct clk_duplicate tegra_clk_duplicates[] = {
2990 CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"), 2990 CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"),
2991 CLK_DUPLICATE("dsib", "tegradc.0", "dsib"), 2991 CLK_DUPLICATE("dsib", "tegradc.0", "dsib"),
2992 CLK_DUPLICATE("dsia", "tegradc.1", "dsia"), 2992 CLK_DUPLICATE("dsia", "tegradc.1", "dsia"),
2993 CLK_DUPLICATE("pwm", "tegra_pwm.0", NULL),
2994 CLK_DUPLICATE("pwm", "tegra_pwm.1", NULL),
2995 CLK_DUPLICATE("pwm", "tegra_pwm.2", NULL),
2996 CLK_DUPLICATE("pwm", "tegra_pwm.3", NULL),
2997 CLK_DUPLICATE("bsev", "tegra-avp", "bsev"), 2993 CLK_DUPLICATE("bsev", "tegra-avp", "bsev"),
2998 CLK_DUPLICATE("bsev", "nvavp", "bsev"), 2994 CLK_DUPLICATE("bsev", "nvavp", "bsev"),
2999 CLK_DUPLICATE("vde", "tegra-aes", "vde"), 2995 CLK_DUPLICATE("vde", "tegra-aes", "vde"),
diff --git a/arch/arm/mach-tegra/timer.c b/arch/arm/mach-tegra/timer.c
index 315672c7bd48..57b5bdc13b9b 100644
--- a/arch/arm/mach-tegra/timer.c
+++ b/arch/arm/mach-tegra/timer.c
@@ -189,7 +189,7 @@ static void __init tegra_init_timer(void)
189 " Assuming 12Mhz input clock.\n"); 189 " Assuming 12Mhz input clock.\n");
190 rate = 12000000; 190 rate = 12000000;
191 } else { 191 } else {
192 clk_enable(clk); 192 clk_prepare_enable(clk);
193 rate = clk_get_rate(clk); 193 rate = clk_get_rate(clk);
194 } 194 }
195 195
@@ -201,7 +201,7 @@ static void __init tegra_init_timer(void)
201 if (IS_ERR(clk)) 201 if (IS_ERR(clk))
202 pr_warn("Unable to get rtc-tegra clock\n"); 202 pr_warn("Unable to get rtc-tegra clock\n");
203 else 203 else
204 clk_enable(clk); 204 clk_prepare_enable(clk);
205 205
206 switch (rate) { 206 switch (rate) {
207 case 12000000: 207 case 12000000:
diff --git a/arch/arm/mach-tegra/usb_phy.c b/arch/arm/mach-tegra/usb_phy.c
index 54e353c8e304..022b33a05c3a 100644
--- a/arch/arm/mach-tegra/usb_phy.c
+++ b/arch/arm/mach-tegra/usb_phy.c
@@ -247,7 +247,7 @@ static void utmip_pad_power_on(struct tegra_usb_phy *phy)
247 unsigned long val, flags; 247 unsigned long val, flags;
248 void __iomem *base = phy->pad_regs; 248 void __iomem *base = phy->pad_regs;
249 249
250 clk_enable(phy->pad_clk); 250 clk_prepare_enable(phy->pad_clk);
251 251
252 spin_lock_irqsave(&utmip_pad_lock, flags); 252 spin_lock_irqsave(&utmip_pad_lock, flags);
253 253
@@ -259,7 +259,7 @@ static void utmip_pad_power_on(struct tegra_usb_phy *phy)
259 259
260 spin_unlock_irqrestore(&utmip_pad_lock, flags); 260 spin_unlock_irqrestore(&utmip_pad_lock, flags);
261 261
262 clk_disable(phy->pad_clk); 262 clk_disable_unprepare(phy->pad_clk);
263} 263}
264 264
265static int utmip_pad_power_off(struct tegra_usb_phy *phy) 265static int utmip_pad_power_off(struct tegra_usb_phy *phy)
@@ -272,7 +272,7 @@ static int utmip_pad_power_off(struct tegra_usb_phy *phy)
272 return -EINVAL; 272 return -EINVAL;
273 } 273 }
274 274
275 clk_enable(phy->pad_clk); 275 clk_prepare_enable(phy->pad_clk);
276 276
277 spin_lock_irqsave(&utmip_pad_lock, flags); 277 spin_lock_irqsave(&utmip_pad_lock, flags);
278 278
@@ -284,7 +284,7 @@ static int utmip_pad_power_off(struct tegra_usb_phy *phy)
284 284
285 spin_unlock_irqrestore(&utmip_pad_lock, flags); 285 spin_unlock_irqrestore(&utmip_pad_lock, flags);
286 286
287 clk_disable(phy->pad_clk); 287 clk_disable_unprepare(phy->pad_clk);
288 288
289 return 0; 289 return 0;
290} 290}
@@ -580,7 +580,7 @@ static int ulpi_phy_power_on(struct tegra_usb_phy *phy)
580 msleep(5); 580 msleep(5);
581 gpio_direction_output(config->reset_gpio, 1); 581 gpio_direction_output(config->reset_gpio, 1);
582 582
583 clk_enable(phy->clk); 583 clk_prepare_enable(phy->clk);
584 msleep(1); 584 msleep(1);
585 585
586 val = readl(base + USB_SUSP_CTRL); 586 val = readl(base + USB_SUSP_CTRL);
@@ -689,7 +689,7 @@ struct tegra_usb_phy *tegra_usb_phy_open(struct device *dev, int instance,
689 err = PTR_ERR(phy->pll_u); 689 err = PTR_ERR(phy->pll_u);
690 goto err0; 690 goto err0;
691 } 691 }
692 clk_enable(phy->pll_u); 692 clk_prepare_enable(phy->pll_u);
693 693
694 parent_rate = clk_get_rate(clk_get_parent(phy->pll_u)); 694 parent_rate = clk_get_rate(clk_get_parent(phy->pll_u));
695 for (i = 0; i < ARRAY_SIZE(tegra_freq_table); i++) { 695 for (i = 0; i < ARRAY_SIZE(tegra_freq_table); i++) {
@@ -735,7 +735,7 @@ struct tegra_usb_phy *tegra_usb_phy_open(struct device *dev, int instance,
735 return phy; 735 return phy;
736 736
737err1: 737err1:
738 clk_disable(phy->pll_u); 738 clk_disable_unprepare(phy->pll_u);
739 clk_put(phy->pll_u); 739 clk_put(phy->pll_u);
740err0: 740err0:
741 kfree(phy); 741 kfree(phy);
@@ -810,7 +810,7 @@ void tegra_usb_phy_close(struct tegra_usb_phy *phy)
810 clk_put(phy->clk); 810 clk_put(phy->clk);
811 else 811 else
812 utmip_pad_close(phy); 812 utmip_pad_close(phy);
813 clk_disable(phy->pll_u); 813 clk_disable_unprepare(phy->pll_u);
814 clk_put(phy->pll_u); 814 clk_put(phy->pll_u);
815 kfree(phy); 815 kfree(phy);
816} 816}
diff --git a/arch/arm/plat-mxc/devices/platform-spi_imx.c b/arch/arm/plat-mxc/devices/platform-spi_imx.c
index 9bfae8bd5b8d..9c50c14c8f92 100644
--- a/arch/arm/plat-mxc/devices/platform-spi_imx.c
+++ b/arch/arm/plat-mxc/devices/platform-spi_imx.c
@@ -95,7 +95,7 @@ const struct imx_spi_imx_data imx51_ecspi_data[] __initconst = {
95#ifdef CONFIG_SOC_IMX53 95#ifdef CONFIG_SOC_IMX53
96/* i.mx53 has the i.mx35 type cspi */ 96/* i.mx53 has the i.mx35 type cspi */
97const struct imx_spi_imx_data imx53_cspi_data __initconst = 97const struct imx_spi_imx_data imx53_cspi_data __initconst =
98 imx_spi_imx_data_entry_single(MX53, CSPI, "imx35-cspi", 0, , SZ_4K); 98 imx_spi_imx_data_entry_single(MX53, CSPI, "imx35-cspi", 2, , SZ_4K);
99 99
100/* i.mx53 has the i.mx51 type ecspi */ 100/* i.mx53 has the i.mx51 type ecspi */
101const struct imx_spi_imx_data imx53_ecspi_data[] __initconst = { 101const struct imx_spi_imx_data imx53_ecspi_data[] __initconst = {
diff --git a/arch/arm/plat-mxc/time.c b/arch/arm/plat-mxc/time.c
index 00e8e659e667..a17abcf98325 100644
--- a/arch/arm/plat-mxc/time.c
+++ b/arch/arm/plat-mxc/time.c
@@ -160,7 +160,8 @@ static const char *clock_event_mode_label[] = {
160 [CLOCK_EVT_MODE_PERIODIC] = "CLOCK_EVT_MODE_PERIODIC", 160 [CLOCK_EVT_MODE_PERIODIC] = "CLOCK_EVT_MODE_PERIODIC",
161 [CLOCK_EVT_MODE_ONESHOT] = "CLOCK_EVT_MODE_ONESHOT", 161 [CLOCK_EVT_MODE_ONESHOT] = "CLOCK_EVT_MODE_ONESHOT",
162 [CLOCK_EVT_MODE_SHUTDOWN] = "CLOCK_EVT_MODE_SHUTDOWN", 162 [CLOCK_EVT_MODE_SHUTDOWN] = "CLOCK_EVT_MODE_SHUTDOWN",
163 [CLOCK_EVT_MODE_UNUSED] = "CLOCK_EVT_MODE_UNUSED" 163 [CLOCK_EVT_MODE_UNUSED] = "CLOCK_EVT_MODE_UNUSED",
164 [CLOCK_EVT_MODE_RESUME] = "CLOCK_EVT_MODE_RESUME",
164}; 165};
165#endif /* DEBUG */ 166#endif /* DEBUG */
166 167
diff --git a/arch/arm/plat-omap/include/plat/clkdev_omap.h b/arch/arm/plat-omap/include/plat/clkdev_omap.h
index d0ed8c443a63..025d85a3ee86 100644
--- a/arch/arm/plat-omap/include/plat/clkdev_omap.h
+++ b/arch/arm/plat-omap/include/plat/clkdev_omap.h
@@ -39,6 +39,7 @@ struct omap_clk {
39#define CK_443X (1 << 11) 39#define CK_443X (1 << 11)
40#define CK_TI816X (1 << 12) 40#define CK_TI816X (1 << 12)
41#define CK_446X (1 << 13) 41#define CK_446X (1 << 13)
42#define CK_AM33XX (1 << 14) /* AM33xx specific clocks */
42#define CK_1710 (1 << 15) /* 1710 extra for rate selection */ 43#define CK_1710 (1 << 15) /* 1710 extra for rate selection */
43 44
44 45
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-05 20:30:56 -0500