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-rw-r--r--arch/arm/mach-shmobile/Kconfig6
-rw-r--r--arch/arm/mach-shmobile/Makefile3
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7740.c378
-rw-r--r--arch/arm/mach-shmobile/include/mach/common.h6
-rw-r--r--arch/arm/mach-shmobile/include/mach/r8a7740.h584
-rw-r--r--arch/arm/mach-shmobile/intc-r8a7740.c631
-rw-r--r--arch/arm/mach-shmobile/pfc-r8a7740.c2562
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7740.c352
8 files changed, 4522 insertions, 0 deletions
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 0828fab2b65c..aa63c968f420 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -28,6 +28,12 @@ config ARCH_SH73A0
28 select ARM_GIC 28 select ARM_GIC
29 select I2C 29 select I2C
30 30
31config ARCH_R8A7740
32 bool "R-Mobile A1 (R8A77400)"
33 select CPU_V7
34 select SH_CLK_CPG
35 select ARCH_WANT_OPTIONAL_GPIOLIB
36
31comment "SH-Mobile Board Type" 37comment "SH-Mobile Board Type"
32 38
33config MACH_G3EVM 39config MACH_G3EVM
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index 737bdc631b0d..5ee604dcaf57 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_ARCH_SH7367) += setup-sh7367.o clock-sh7367.o intc-sh7367.o
10obj-$(CONFIG_ARCH_SH7377) += setup-sh7377.o clock-sh7377.o intc-sh7377.o 10obj-$(CONFIG_ARCH_SH7377) += setup-sh7377.o clock-sh7377.o intc-sh7377.o
11obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o clock-sh7372.o intc-sh7372.o 11obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o clock-sh7372.o intc-sh7372.o
12obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o clock-sh73a0.o intc-sh73a0.o 12obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o clock-sh73a0.o intc-sh73a0.o
13obj-$(CONFIG_ARCH_R8A7740) += setup-r8a7740.o clock-r8a7740.o intc-r8a7740.o
13 14
14# SMP objects 15# SMP objects
15smp-y := platsmp.o headsmp.o 16smp-y := platsmp.o headsmp.o
@@ -23,12 +24,14 @@ pfc-$(CONFIG_ARCH_SH7367) += pfc-sh7367.o
23pfc-$(CONFIG_ARCH_SH7377) += pfc-sh7377.o 24pfc-$(CONFIG_ARCH_SH7377) += pfc-sh7377.o
24pfc-$(CONFIG_ARCH_SH7372) += pfc-sh7372.o 25pfc-$(CONFIG_ARCH_SH7372) += pfc-sh7372.o
25pfc-$(CONFIG_ARCH_SH73A0) += pfc-sh73a0.o 26pfc-$(CONFIG_ARCH_SH73A0) += pfc-sh73a0.o
27pfc-$(CONFIG_ARCH_R8A7740) += pfc-r8a7740.o
26 28
27# IRQ objects 29# IRQ objects
28obj-$(CONFIG_ARCH_SH7367) += entry-intc.o 30obj-$(CONFIG_ARCH_SH7367) += entry-intc.o
29obj-$(CONFIG_ARCH_SH7377) += entry-intc.o 31obj-$(CONFIG_ARCH_SH7377) += entry-intc.o
30obj-$(CONFIG_ARCH_SH7372) += entry-intc.o 32obj-$(CONFIG_ARCH_SH7372) += entry-intc.o
31obj-$(CONFIG_ARCH_SH73A0) += entry-gic.o 33obj-$(CONFIG_ARCH_SH73A0) += entry-gic.o
34obj-$(CONFIG_ARCH_R8A7740) += entry-intc.o
32 35
33# PM objects 36# PM objects
34obj-$(CONFIG_SUSPEND) += suspend.o 37obj-$(CONFIG_SUSPEND) += suspend.o
diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c
new file mode 100644
index 000000000000..5bb02f224077
--- /dev/null
+++ b/arch/arm/mach-shmobile/clock-r8a7740.c
@@ -0,0 +1,378 @@
1/*
2 * R8A7740 processor support
3 *
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#include <linux/init.h>
21#include <linux/kernel.h>
22#include <linux/io.h>
23#include <linux/sh_clk.h>
24#include <linux/clkdev.h>
25#include <mach/common.h>
26#include <mach/r8a7740.h>
27
28/*
29 * | MDx | XTAL1/EXTAL1 | System | EXTALR |
30 * Clock |-------+-----------------+ clock | 32.768 | RCLK
31 * Mode | 2/1/0 | src MHz | source | KHz | source
32 * -------+-------+-----------------+-----------+--------+----------
33 * 0 | 0 0 0 | External 20~50 | XTAL1 | O | EXTALR
34 * 1 | 0 0 1 | Crystal 20~30 | XTAL1 | O | EXTALR
35 * 2 | 0 1 0 | External 40~50 | XTAL1 / 2 | O | EXTALR
36 * 3 | 0 1 1 | Crystal 40~50 | XTAL1 / 2 | O | EXTALR
37 * 4 | 1 0 0 | External 20~50 | XTAL1 | x | XTAL1 / 1024
38 * 5 | 1 0 1 | Crystal 20~30 | XTAL1 | x | XTAL1 / 1024
39 * 6 | 1 1 0 | External 40~50 | XTAL1 / 2 | x | XTAL1 / 2048
40 * 7 | 1 1 1 | Crystal 40~50 | XTAL1 / 2 | x | XTAL1 / 2048
41 */
42
43/* CPG registers */
44#define FRQCRA 0xe6150000
45#define FRQCRB 0xe6150004
46#define FRQCRC 0xe61500e0
47#define PLLC01CR 0xe6150028
48
49#define SUBCKCR 0xe6150080
50
51#define MSTPSR0 0xe6150030
52#define MSTPSR1 0xe6150038
53#define MSTPSR2 0xe6150040
54#define MSTPSR3 0xe6150048
55#define MSTPSR4 0xe615004c
56#define SMSTPCR0 0xe6150130
57#define SMSTPCR1 0xe6150134
58#define SMSTPCR2 0xe6150138
59#define SMSTPCR3 0xe615013c
60#define SMSTPCR4 0xe6150140
61
62/* Fixed 32 KHz root clock from EXTALR pin */
63static struct clk extalr_clk = {
64 .rate = 32768,
65};
66
67/*
68 * 25MHz default rate for the EXTAL1 root input clock.
69 * If needed, reset this with clk_set_rate() from the platform code.
70 */
71static struct clk extal1_clk = {
72 .rate = 25000000,
73};
74
75/*
76 * 48MHz default rate for the EXTAL2 root input clock.
77 * If needed, reset this with clk_set_rate() from the platform code.
78 */
79static struct clk extal2_clk = {
80 .rate = 48000000,
81};
82
83/*
84 * 27MHz default rate for the DV_CLKI root input clock.
85 * If needed, reset this with clk_set_rate() from the platform code.
86 */
87static struct clk dv_clk = {
88 .rate = 27000000,
89};
90
91static unsigned long div_recalc(struct clk *clk)
92{
93 return clk->parent->rate / (int)(clk->priv);
94}
95
96static struct clk_ops div_clk_ops = {
97 .recalc = div_recalc,
98};
99
100/* extal1 / 2 */
101static struct clk extal1_div2_clk = {
102 .ops = &div_clk_ops,
103 .priv = (void *)2,
104 .parent = &extal1_clk,
105};
106
107/* extal1 / 1024 */
108static struct clk extal1_div1024_clk = {
109 .ops = &div_clk_ops,
110 .priv = (void *)1024,
111 .parent = &extal1_clk,
112};
113
114/* extal1 / 2 / 1024 */
115static struct clk extal1_div2048_clk = {
116 .ops = &div_clk_ops,
117 .priv = (void *)1024,
118 .parent = &extal1_div2_clk,
119};
120
121/* extal2 / 2 */
122static struct clk extal2_div2_clk = {
123 .ops = &div_clk_ops,
124 .priv = (void *)2,
125 .parent = &extal2_clk,
126};
127
128static struct clk_ops followparent_clk_ops = {
129 .recalc = followparent_recalc,
130};
131
132/* Main clock */
133static struct clk system_clk = {
134 .ops = &followparent_clk_ops,
135};
136
137static struct clk system_div2_clk = {
138 .ops = &div_clk_ops,
139 .priv = (void *)2,
140 .parent = &system_clk,
141};
142
143/* r_clk */
144static struct clk r_clk = {
145 .ops = &followparent_clk_ops,
146};
147
148/* PLLC0/PLLC1 */
149static unsigned long pllc01_recalc(struct clk *clk)
150{
151 unsigned long mult = 1;
152
153 if (__raw_readl(PLLC01CR) & (1 << 14))
154 mult = ((__raw_readl(clk->enable_reg) >> 24) & 0x7f) + 1;
155
156 return clk->parent->rate * mult;
157}
158
159static struct clk_ops pllc01_clk_ops = {
160 .recalc = pllc01_recalc,
161};
162
163static struct clk pllc0_clk = {
164 .ops = &pllc01_clk_ops,
165 .flags = CLK_ENABLE_ON_INIT,
166 .parent = &system_clk,
167 .enable_reg = (void __iomem *)FRQCRC,
168};
169
170static struct clk pllc1_clk = {
171 .ops = &pllc01_clk_ops,
172 .flags = CLK_ENABLE_ON_INIT,
173 .parent = &system_div2_clk,
174 .enable_reg = (void __iomem *)FRQCRA,
175};
176
177/* PLLC1 / 2 */
178static struct clk pllc1_div2_clk = {
179 .ops = &div_clk_ops,
180 .priv = (void *)2,
181 .parent = &pllc1_clk,
182};
183
184struct clk *main_clks[] = {
185 &extalr_clk,
186 &extal1_clk,
187 &extal2_clk,
188 &extal1_div2_clk,
189 &extal1_div1024_clk,
190 &extal1_div2048_clk,
191 &extal2_div2_clk,
192 &dv_clk,
193 &system_clk,
194 &system_div2_clk,
195 &r_clk,
196 &pllc0_clk,
197 &pllc1_clk,
198 &pllc1_div2_clk,
199};
200
201static void div4_kick(struct clk *clk)
202{
203 unsigned long value;
204
205 /* set KICK bit in FRQCRB to update hardware setting */
206 value = __raw_readl(FRQCRB);
207 value |= (1 << 31);
208 __raw_writel(value, FRQCRB);
209}
210
211static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18,
212 24, 32, 36, 48, 0, 72, 96, 0 };
213
214static struct clk_div_mult_table div4_div_mult_table = {
215 .divisors = divisors,
216 .nr_divisors = ARRAY_SIZE(divisors),
217};
218
219static struct clk_div4_table div4_table = {
220 .div_mult_table = &div4_div_mult_table,
221 .kick = div4_kick,
222};
223
224enum {
225 DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_HP,
226 DIV4_HPP, DIV4_S, DIV4_ZB, DIV4_M3, DIV4_CP,
227 DIV4_NR
228};
229
230struct clk div4_clks[DIV4_NR] = {
231 [DIV4_I] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 20, 0x6fff, CLK_ENABLE_ON_INIT),
232 [DIV4_ZG] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 16, 0x6fff, CLK_ENABLE_ON_INIT),
233 [DIV4_B] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 8, 0x6fff, CLK_ENABLE_ON_INIT),
234 [DIV4_M1] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 4, 0x6fff, CLK_ENABLE_ON_INIT),
235 [DIV4_HP] = SH_CLK_DIV4(&pllc1_clk, FRQCRB, 4, 0x6fff, 0),
236 [DIV4_HPP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 20, 0x6fff, 0),
237 [DIV4_S] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 12, 0x6fff, 0),
238 [DIV4_ZB] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 8, 0x6fff, 0),
239 [DIV4_M3] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 4, 0x6fff, 0),
240 [DIV4_CP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 0, 0x6fff, 0),
241};
242
243enum {
244 DIV6_SUB,
245 DIV6_NR
246};
247
248static struct clk div6_clks[DIV6_NR] = {
249 [DIV6_SUB] = SH_CLK_DIV6(&pllc1_div2_clk, SUBCKCR, 0),
250};
251
252enum {
253 MSTP125,
254 MSTP116, MSTP111,
255
256 MSTP230,
257 MSTP222,
258 MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
259
260 MSTP329, MSTP323,
261
262 MSTP_NR
263};
264
265static struct clk mstp_clks[MSTP_NR] = {
266 [MSTP125] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 25, 0), /* TMU0 */
267 [MSTP116] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 16, 0), /* IIC0 */
268 [MSTP111] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 11, 0), /* TMU1 */
269
270 [MSTP230] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 30, 0), /* SCIFA6 */
271 [MSTP222] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 22, 0), /* SCIFA7 */
272 [MSTP207] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */
273 [MSTP206] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */
274 [MSTP204] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 4, 0), /* SCIFA0 */
275 [MSTP203] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 3, 0), /* SCIFA1 */
276 [MSTP202] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 2, 0), /* SCIFA2 */
277 [MSTP201] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 1, 0), /* SCIFA3 */
278 [MSTP200] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */
279
280 [MSTP329] = SH_CLK_MSTP32(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */
281 [MSTP323] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR3, 23, 0), /* IIC1 */
282};
283
284static struct clk_lookup lookups[] = {
285 /* main clocks */
286 CLKDEV_CON_ID("extalr", &extalr_clk),
287 CLKDEV_CON_ID("extal1", &extal1_clk),
288 CLKDEV_CON_ID("extal2", &extal2_clk),
289 CLKDEV_CON_ID("extal1_div2", &extal1_div2_clk),
290 CLKDEV_CON_ID("extal1_div1024", &extal1_div1024_clk),
291 CLKDEV_CON_ID("extal1_div2048", &extal1_div2048_clk),
292 CLKDEV_CON_ID("extal2_div2", &extal2_div2_clk),
293 CLKDEV_CON_ID("dv_clk", &dv_clk),
294 CLKDEV_CON_ID("system_clk", &system_clk),
295 CLKDEV_CON_ID("system_div2_clk", &system_div2_clk),
296 CLKDEV_CON_ID("r_clk", &r_clk),
297 CLKDEV_CON_ID("pllc0_clk", &pllc0_clk),
298 CLKDEV_CON_ID("pllc1_clk", &pllc1_clk),
299 CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk),
300
301 /* DIV4 clocks */
302 CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]),
303 CLKDEV_CON_ID("zg_clk", &div4_clks[DIV4_ZG]),
304 CLKDEV_CON_ID("b_clk", &div4_clks[DIV4_B]),
305 CLKDEV_CON_ID("m1_clk", &div4_clks[DIV4_M1]),
306 CLKDEV_CON_ID("hp_clk", &div4_clks[DIV4_HP]),
307 CLKDEV_CON_ID("hpp_clk", &div4_clks[DIV4_HPP]),
308 CLKDEV_CON_ID("s_clk", &div4_clks[DIV4_S]),
309 CLKDEV_CON_ID("zb_clk", &div4_clks[DIV4_ZB]),
310 CLKDEV_CON_ID("m3_clk", &div4_clks[DIV4_M3]),
311 CLKDEV_CON_ID("cp_clk", &div4_clks[DIV4_CP]),
312
313 /* DIV6 clocks */
314 CLKDEV_CON_ID("sub_clk", &div6_clks[DIV6_SUB]),
315
316 /* MSTP32 clocks */
317 CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP111]),
318 CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]),
319 CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP125]),
320
321 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]),
322 CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]),
323 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]),
324 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
325 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
326 CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP206]),
327 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]),
328
329 CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP222]),
330 CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP230]),
331
332 CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]),
333 CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]),
334};
335
336void __init r8a7740_clock_init(u8 md_ck)
337{
338 int k, ret = 0;
339
340 /* detect system clock parent */
341 if (md_ck & MD_CK1)
342 system_clk.parent = &extal1_div2_clk;
343 else
344 system_clk.parent = &extal1_clk;
345
346 /* detect RCLK parent */
347 switch (md_ck & (MD_CK2 | MD_CK1)) {
348 case MD_CK2 | MD_CK1:
349 r_clk.parent = &extal1_div2048_clk;
350 break;
351 case MD_CK2:
352 r_clk.parent = &extal1_div1024_clk;
353 break;
354 case MD_CK1:
355 default:
356 r_clk.parent = &extalr_clk;
357 break;
358 }
359
360 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
361 ret = clk_register(main_clks[k]);
362
363 if (!ret)
364 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
365
366 if (!ret)
367 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
368
369 if (!ret)
370 ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
371
372 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
373
374 if (!ret)
375 clk_init();
376 else
377 panic("failed to setup r8a7740 clocks\n");
378}
diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h
index 834bd6cd508f..5055a00a83d4 100644
--- a/arch/arm/mach-shmobile/include/mach/common.h
+++ b/arch/arm/mach-shmobile/include/mach/common.h
@@ -53,4 +53,10 @@ extern void sh73a0_secondary_init(unsigned int cpu);
53extern int sh73a0_boot_secondary(unsigned int cpu); 53extern int sh73a0_boot_secondary(unsigned int cpu);
54extern void sh73a0_smp_prepare_cpus(void); 54extern void sh73a0_smp_prepare_cpus(void);
55 55
56extern void r8a7740_init_irq(void);
57extern void r8a7740_add_early_devices(void);
58extern void r8a7740_add_standard_devices(void);
59extern void r8a7740_clock_init(u8 md_ck);
60extern void r8a7740_pinmux_init(void);
61
56#endif /* __ARCH_MACH_COMMON_H */ 62#endif /* __ARCH_MACH_COMMON_H */
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7740.h b/arch/arm/mach-shmobile/include/mach/r8a7740.h
new file mode 100644
index 000000000000..9d447abb969c
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/r8a7740.h
@@ -0,0 +1,584 @@
1/*
2 * Copyright (C) 2011 Renesas Solutions Corp.
3 * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17 */
18
19#ifndef __ASM_R8A7740_H__
20#define __ASM_R8A7740_H__
21
22/*
23 * MD_CKx pin
24 */
25#define MD_CK2 (1 << 2)
26#define MD_CK1 (1 << 1)
27#define MD_CK0 (1 << 0)
28
29/*
30 * Pin Function Controller:
31 * GPIO_FN_xx - GPIO used to select pin function
32 * GPIO_PORTxx - GPIO mapped to real I/O pin on CPU
33 */
34enum {
35 /* PORT */
36 GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4,
37 GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9,
38
39 GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14,
40 GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19,
41
42 GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24,
43 GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29,
44
45 GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34,
46 GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39,
47
48 GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44,
49 GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49,
50
51 GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54,
52 GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59,
53
54 GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64,
55 GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69,
56
57 GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74,
58 GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79,
59
60 GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84,
61 GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89,
62
63 GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94,
64 GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99,
65
66 GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104,
67 GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109,
68
69 GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114,
70 GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118, GPIO_PORT119,
71
72 GPIO_PORT120, GPIO_PORT121, GPIO_PORT122, GPIO_PORT123, GPIO_PORT124,
73 GPIO_PORT125, GPIO_PORT126, GPIO_PORT127, GPIO_PORT128, GPIO_PORT129,
74
75 GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134,
76 GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139,
77
78 GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144,
79 GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149,
80
81 GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154,
82 GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159,
83
84 GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164,
85 GPIO_PORT165, GPIO_PORT166, GPIO_PORT167, GPIO_PORT168, GPIO_PORT169,
86
87 GPIO_PORT170, GPIO_PORT171, GPIO_PORT172, GPIO_PORT173, GPIO_PORT174,
88 GPIO_PORT175, GPIO_PORT176, GPIO_PORT177, GPIO_PORT178, GPIO_PORT179,
89
90 GPIO_PORT180, GPIO_PORT181, GPIO_PORT182, GPIO_PORT183, GPIO_PORT184,
91 GPIO_PORT185, GPIO_PORT186, GPIO_PORT187, GPIO_PORT188, GPIO_PORT189,
92
93 GPIO_PORT190, GPIO_PORT191, GPIO_PORT192, GPIO_PORT193, GPIO_PORT194,
94 GPIO_PORT195, GPIO_PORT196, GPIO_PORT197, GPIO_PORT198, GPIO_PORT199,
95
96 GPIO_PORT200, GPIO_PORT201, GPIO_PORT202, GPIO_PORT203, GPIO_PORT204,
97 GPIO_PORT205, GPIO_PORT206, GPIO_PORT207, GPIO_PORT208, GPIO_PORT209,
98
99 GPIO_PORT210, GPIO_PORT211,
100
101 /* IRQ */
102 GPIO_FN_IRQ0_PORT2, GPIO_FN_IRQ0_PORT13,
103 GPIO_FN_IRQ1,
104 GPIO_FN_IRQ2_PORT11, GPIO_FN_IRQ2_PORT12,
105 GPIO_FN_IRQ3_PORT10, GPIO_FN_IRQ3_PORT14,
106 GPIO_FN_IRQ4_PORT15, GPIO_FN_IRQ4_PORT172,
107 GPIO_FN_IRQ5_PORT0, GPIO_FN_IRQ5_PORT1,
108 GPIO_FN_IRQ6_PORT121, GPIO_FN_IRQ6_PORT173,
109 GPIO_FN_IRQ7_PORT120, GPIO_FN_IRQ7_PORT209,
110 GPIO_FN_IRQ8,
111 GPIO_FN_IRQ9_PORT118, GPIO_FN_IRQ9_PORT210,
112 GPIO_FN_IRQ10,
113 GPIO_FN_IRQ11,
114 GPIO_FN_IRQ12_PORT42, GPIO_FN_IRQ12_PORT97,
115 GPIO_FN_IRQ13_PORT64, GPIO_FN_IRQ13_PORT98,
116 GPIO_FN_IRQ14_PORT63, GPIO_FN_IRQ14_PORT99,
117 GPIO_FN_IRQ15_PORT62, GPIO_FN_IRQ15_PORT100,
118 GPIO_FN_IRQ16_PORT68, GPIO_FN_IRQ16_PORT211,
119 GPIO_FN_IRQ17,
120 GPIO_FN_IRQ18,
121 GPIO_FN_IRQ19,
122 GPIO_FN_IRQ20,
123 GPIO_FN_IRQ21,
124 GPIO_FN_IRQ22,
125 GPIO_FN_IRQ23,
126 GPIO_FN_IRQ24,
127 GPIO_FN_IRQ25,
128 GPIO_FN_IRQ26_PORT58, GPIO_FN_IRQ26_PORT81,
129 GPIO_FN_IRQ27_PORT57, GPIO_FN_IRQ27_PORT168,
130 GPIO_FN_IRQ28_PORT56, GPIO_FN_IRQ28_PORT169,
131 GPIO_FN_IRQ29_PORT50, GPIO_FN_IRQ29_PORT170,
132 GPIO_FN_IRQ30_PORT49, GPIO_FN_IRQ30_PORT171,
133 GPIO_FN_IRQ31_PORT41, GPIO_FN_IRQ31_PORT167,
134
135 /* Function */
136
137 /* DBGT */
138 GPIO_FN_DBGMDT2, GPIO_FN_DBGMDT1, GPIO_FN_DBGMDT0,
139 GPIO_FN_DBGMD10, GPIO_FN_DBGMD11, GPIO_FN_DBGMD20,
140 GPIO_FN_DBGMD21,
141
142 /* FSI */
143 GPIO_FN_FSIAISLD_PORT0, /* FSIAISLD Port 0/5 */
144 GPIO_FN_FSIAISLD_PORT5,
145 GPIO_FN_FSIASPDIF_PORT9, /* FSIASPDIF Port 9/18 */
146 GPIO_FN_FSIASPDIF_PORT18,
147 GPIO_FN_FSIAOSLD1, GPIO_FN_FSIAOSLD2,
148 GPIO_FN_FSIAOLR, GPIO_FN_FSIAOBT,
149 GPIO_FN_FSIAOSLD, GPIO_FN_FSIAOMC,
150 GPIO_FN_FSIACK, GPIO_FN_FSIAILR,
151 GPIO_FN_FSIAIBT,
152
153 /* FMSI */
154 GPIO_FN_FMSISLD_PORT1, /* FMSISLD Port 1/6 */
155 GPIO_FN_FMSISLD_PORT6,
156 GPIO_FN_FMSIILR, GPIO_FN_FMSIIBT,
157 GPIO_FN_FMSIOLR, GPIO_FN_FMSIOBT,
158 GPIO_FN_FMSICK, GPIO_FN_FMSOILR,
159 GPIO_FN_FMSOIBT, GPIO_FN_FMSOOLR,
160 GPIO_FN_FMSOOBT, GPIO_FN_FMSOSLD,
161 GPIO_FN_FMSOCK,
162
163 /* SCIFA0 */
164 GPIO_FN_SCIFA0_SCK, GPIO_FN_SCIFA0_CTS,
165 GPIO_FN_SCIFA0_RTS, GPIO_FN_SCIFA0_RXD,
166 GPIO_FN_SCIFA0_TXD,
167
168 /* SCIFA1 */
169 GPIO_FN_SCIFA1_CTS, GPIO_FN_SCIFA1_SCK,
170 GPIO_FN_SCIFA1_RXD, GPIO_FN_SCIFA1_TXD,
171 GPIO_FN_SCIFA1_RTS,
172
173 /* SCIFA2 */
174 GPIO_FN_SCIFA2_SCK_PORT22, /* SCIFA2_SCK Port 22/199 */
175 GPIO_FN_SCIFA2_SCK_PORT199,
176 GPIO_FN_SCIFA2_RXD, GPIO_FN_SCIFA2_TXD,
177 GPIO_FN_SCIFA2_CTS, GPIO_FN_SCIFA2_RTS,
178
179 /* SCIFA3 */
180 GPIO_FN_SCIFA3_RTS_PORT105, /* MSEL5CR_8_0 */
181 GPIO_FN_SCIFA3_SCK_PORT116,
182 GPIO_FN_SCIFA3_CTS_PORT117,
183 GPIO_FN_SCIFA3_RXD_PORT174,
184 GPIO_FN_SCIFA3_TXD_PORT175,
185
186 GPIO_FN_SCIFA3_RTS_PORT161, /* MSEL5CR_8_1 */
187 GPIO_FN_SCIFA3_SCK_PORT158,
188 GPIO_FN_SCIFA3_CTS_PORT162,
189 GPIO_FN_SCIFA3_RXD_PORT159,
190 GPIO_FN_SCIFA3_TXD_PORT160,
191
192 /* SCIFA4 */
193 GPIO_FN_SCIFA4_RXD_PORT12, /* MSEL5CR[12:11] = 00 */
194 GPIO_FN_SCIFA4_TXD_PORT13,
195
196 GPIO_FN_SCIFA4_RXD_PORT204, /* MSEL5CR[12:11] = 01 */
197 GPIO_FN_SCIFA4_TXD_PORT203,
198
199 GPIO_FN_SCIFA4_RXD_PORT94, /* MSEL5CR[12:11] = 10 */
200 GPIO_FN_SCIFA4_TXD_PORT93,
201
202 GPIO_FN_SCIFA4_SCK_PORT21, /* SCIFA4_SCK Port 21/205 */
203 GPIO_FN_SCIFA4_SCK_PORT205,
204
205 /* SCIFA5 */
206 GPIO_FN_SCIFA5_TXD_PORT20, /* MSEL5CR[15:14] = 00 */
207 GPIO_FN_SCIFA5_RXD_PORT10,
208
209 GPIO_FN_SCIFA5_RXD_PORT207, /* MSEL5CR[15:14] = 01 */
210 GPIO_FN_SCIFA5_TXD_PORT208,
211
212 GPIO_FN_SCIFA5_TXD_PORT91, /* MSEL5CR[15:14] = 10 */
213 GPIO_FN_SCIFA5_RXD_PORT92,
214
215 GPIO_FN_SCIFA5_SCK_PORT23, /* SCIFA5_SCK Port 23/206 */
216 GPIO_FN_SCIFA5_SCK_PORT206,
217
218 /* SCIFA6 */
219 GPIO_FN_SCIFA6_SCK, GPIO_FN_SCIFA6_RXD, GPIO_FN_SCIFA6_TXD,
220
221 /* SCIFA7 */
222 GPIO_FN_SCIFA7_TXD, GPIO_FN_SCIFA7_RXD,
223
224 /* SCIFAB */
225 GPIO_FN_SCIFB_SCK_PORT190, /* MSEL5CR_17_0 */
226 GPIO_FN_SCIFB_RXD_PORT191,
227 GPIO_FN_SCIFB_TXD_PORT192,
228 GPIO_FN_SCIFB_RTS_PORT186,
229 GPIO_FN_SCIFB_CTS_PORT187,
230
231 GPIO_FN_SCIFB_SCK_PORT2, /* MSEL5CR_17_1 */
232 GPIO_FN_SCIFB_RXD_PORT3,
233 GPIO_FN_SCIFB_TXD_PORT4,
234 GPIO_FN_SCIFB_RTS_PORT172,
235 GPIO_FN_SCIFB_CTS_PORT173,
236
237 /* LCD0 */
238 GPIO_FN_LCDC0_SELECT,
239 GPIO_FN_LCD0_D0, GPIO_FN_LCD0_D1, GPIO_FN_LCD0_D2,
240 GPIO_FN_LCD0_D3, GPIO_FN_LCD0_D4, GPIO_FN_LCD0_D5,
241 GPIO_FN_LCD0_D6, GPIO_FN_LCD0_D7, GPIO_FN_LCD0_D8,
242 GPIO_FN_LCD0_D9, GPIO_FN_LCD0_D10, GPIO_FN_LCD0_D11,
243 GPIO_FN_LCD0_D12, GPIO_FN_LCD0_D13, GPIO_FN_LCD0_D14,
244 GPIO_FN_LCD0_D15, GPIO_FN_LCD0_D16, GPIO_FN_LCD0_D17,
245 GPIO_FN_LCD0_DON, GPIO_FN_LCD0_VCPWC, GPIO_FN_LCD0_VEPWC,
246
247 GPIO_FN_LCD0_DCK, GPIO_FN_LCD0_VSYN, /* for RGB */
248 GPIO_FN_LCD0_HSYN, GPIO_FN_LCD0_DISP, /* for RGB */
249
250 GPIO_FN_LCD0_WR, GPIO_FN_LCD0_RD, /* for SYS */
251 GPIO_FN_LCD0_CS, GPIO_FN_LCD0_RS, /* for SYS */
252
253 GPIO_FN_LCD0_D18_PORT163, GPIO_FN_LCD0_D19_PORT162,
254 GPIO_FN_LCD0_D20_PORT161, GPIO_FN_LCD0_D21_PORT158,
255 GPIO_FN_LCD0_D22_PORT160, GPIO_FN_LCD0_D23_PORT159,
256 GPIO_FN_LCD0_LCLK_PORT165, /* MSEL5CR_6_1 */
257
258 GPIO_FN_LCD0_D18_PORT40, GPIO_FN_LCD0_D19_PORT4,
259 GPIO_FN_LCD0_D20_PORT3, GPIO_FN_LCD0_D21_PORT2,
260 GPIO_FN_LCD0_D22_PORT0, GPIO_FN_LCD0_D23_PORT1,
261 GPIO_FN_LCD0_LCLK_PORT102, /* MSEL5CR_6_0 */
262
263 /* LCD1 */
264 GPIO_FN_LCDC1_SELECT,
265 GPIO_FN_LCD1_D0, GPIO_FN_LCD1_D1, GPIO_FN_LCD1_D2,
266 GPIO_FN_LCD1_D3, GPIO_FN_LCD1_D4, GPIO_FN_LCD1_D5,
267 GPIO_FN_LCD1_D6, GPIO_FN_LCD1_D7, GPIO_FN_LCD1_D8,
268 GPIO_FN_LCD1_D9, GPIO_FN_LCD1_D10, GPIO_FN_LCD1_D11,
269 GPIO_FN_LCD1_D12, GPIO_FN_LCD1_D13, GPIO_FN_LCD1_D14,
270 GPIO_FN_LCD1_D15, GPIO_FN_LCD1_D16, GPIO_FN_LCD1_D17,
271 GPIO_FN_LCD1_D18, GPIO_FN_LCD1_D19, GPIO_FN_LCD1_D20,
272 GPIO_FN_LCD1_D21, GPIO_FN_LCD1_D22, GPIO_FN_LCD1_D23,
273 GPIO_FN_LCD1_DON, GPIO_FN_LCD1_VCPWC,
274 GPIO_FN_LCD1_LCLK, GPIO_FN_LCD1_VEPWC,
275
276 GPIO_FN_LCD1_DCK, GPIO_FN_LCD1_VSYN, /* for RGB */
277 GPIO_FN_LCD1_HSYN, GPIO_FN_LCD1_DISP, /* for RGB */
278
279 GPIO_FN_LCD1_WR, GPIO_FN_LCD1_RD, /* for SYS */
280 GPIO_FN_LCD1_CS, GPIO_FN_LCD1_RS, /* for SYS */
281
282 /* RSPI */
283 GPIO_FN_RSPI_SSL0_A, GPIO_FN_RSPI_SSL1_A,
284 GPIO_FN_RSPI_SSL2_A, GPIO_FN_RSPI_SSL3_A,
285 GPIO_FN_RSPI_MOSI_A, GPIO_FN_RSPI_MISO_A,
286 GPIO_FN_RSPI_CK_A,
287
288 /* VIO CKO */
289 GPIO_FN_VIO_CKO1,
290 GPIO_FN_VIO_CKO2,
291 GPIO_FN_VIO_CKO_1,
292 GPIO_FN_VIO_CKO,
293
294 /* VIO0 */
295 GPIO_FN_VIO0_D0, GPIO_FN_VIO0_D1, GPIO_FN_VIO0_D2,
296 GPIO_FN_VIO0_D3, GPIO_FN_VIO0_D4, GPIO_FN_VIO0_D5,
297 GPIO_FN_VIO0_D6, GPIO_FN_VIO0_D7, GPIO_FN_VIO0_D8,
298 GPIO_FN_VIO0_D9, GPIO_FN_VIO0_D10, GPIO_FN_VIO0_D11,
299 GPIO_FN_VIO0_D12, GPIO_FN_VIO0_VD, GPIO_FN_VIO0_HD,
300 GPIO_FN_VIO0_CLK, GPIO_FN_VIO0_FIELD,
301
302 GPIO_FN_VIO0_D13_PORT26, /* MSEL5CR_27_0 */
303 GPIO_FN_VIO0_D14_PORT25,
304 GPIO_FN_VIO0_D15_PORT24,
305
306 GPIO_FN_VIO0_D13_PORT22, /* MSEL5CR_27_1 */
307 GPIO_FN_VIO0_D14_PORT95,
308 GPIO_FN_VIO0_D15_PORT96,
309
310 /* VIO1 */
311 GPIO_FN_VIO1_D0, GPIO_FN_VIO1_D1, GPIO_FN_VIO1_D2,
312 GPIO_FN_VIO1_D3, GPIO_FN_VIO1_D4, GPIO_FN_VIO1_D5,
313 GPIO_FN_VIO1_D6, GPIO_FN_VIO1_D7, GPIO_FN_VIO1_VD,
314 GPIO_FN_VIO1_HD, GPIO_FN_VIO1_CLK, GPIO_FN_VIO1_FIELD,
315
316 /* TPU0 */
317 GPIO_FN_TPU0TO0, GPIO_FN_TPU0TO1,
318 GPIO_FN_TPU0TO3,
319 GPIO_FN_TPU0TO2_PORT66, /* TPU0TO2 Port 66/202 */
320 GPIO_FN_TPU0TO2_PORT202,
321
322 /* SSP1 0 */
323 GPIO_FN_STP0_IPD0, GPIO_FN_STP0_IPD1, GPIO_FN_STP0_IPD2,
324 GPIO_FN_STP0_IPD3, GPIO_FN_STP0_IPD4, GPIO_FN_STP0_IPD5,
325 GPIO_FN_STP0_IPD6, GPIO_FN_STP0_IPD7, GPIO_FN_STP0_IPEN,
326 GPIO_FN_STP0_IPCLK, GPIO_FN_STP0_IPSYNC,
327
328 /* SSP1 1 */
329 GPIO_FN_STP1_IPD1, GPIO_FN_STP1_IPD2, GPIO_FN_STP1_IPD3,
330 GPIO_FN_STP1_IPD4, GPIO_FN_STP1_IPD5, GPIO_FN_STP1_IPD6,
331 GPIO_FN_STP1_IPD7, GPIO_FN_STP1_IPCLK, GPIO_FN_STP1_IPSYNC,
332
333 GPIO_FN_STP1_IPD0_PORT186, /* MSEL5CR_23_0 */
334 GPIO_FN_STP1_IPEN_PORT187,
335
336 GPIO_FN_STP1_IPD0_PORT194, /* MSEL5CR_23_1 */
337 GPIO_FN_STP1_IPEN_PORT193,
338
339 /* SIM */
340 GPIO_FN_SIM_RST, GPIO_FN_SIM_CLK,
341 GPIO_FN_SIM_D_PORT22, /* SIM_D Port 22/199 */
342 GPIO_FN_SIM_D_PORT199,
343
344 /* SDHI0 */
345 GPIO_FN_SDHI0_D0, GPIO_FN_SDHI0_D1, GPIO_FN_SDHI0_D2,
346 GPIO_FN_SDHI0_D3, GPIO_FN_SDHI0_CD, GPIO_FN_SDHI0_WP,
347 GPIO_FN_SDHI0_CMD, GPIO_FN_SDHI0_CLK,
348
349 /* SDHI1 */
350 GPIO_FN_SDHI1_D0, GPIO_FN_SDHI1_D1, GPIO_FN_SDHI1_D2,
351 GPIO_FN_SDHI1_D3, GPIO_FN_SDHI1_CD, GPIO_FN_SDHI1_WP,
352 GPIO_FN_SDHI1_CMD, GPIO_FN_SDHI1_CLK,
353
354 /* SDHI2 */
355 GPIO_FN_SDHI2_D0, GPIO_FN_SDHI2_D1, GPIO_FN_SDHI2_D2,
356 GPIO_FN_SDHI2_D3, GPIO_FN_SDHI2_CLK, GPIO_FN_SDHI2_CMD,
357
358 GPIO_FN_SDHI2_CD_PORT24, /* MSEL5CR_19_0 */
359 GPIO_FN_SDHI2_WP_PORT25,
360
361 GPIO_FN_SDHI2_WP_PORT177, /* MSEL5CR_19_1 */
362 GPIO_FN_SDHI2_CD_PORT202,
363
364 /* MSIOF2 */
365 GPIO_FN_MSIOF2_TXD, GPIO_FN_MSIOF2_RXD, GPIO_FN_MSIOF2_TSCK,
366 GPIO_FN_MSIOF2_SS2, GPIO_FN_MSIOF2_TSYNC, GPIO_FN_MSIOF2_SS1,
367 GPIO_FN_MSIOF2_MCK1, GPIO_FN_MSIOF2_MCK0, GPIO_FN_MSIOF2_RSYNC,
368 GPIO_FN_MSIOF2_RSCK,
369
370 /* KEYSC */
371 GPIO_FN_KEYIN4, GPIO_FN_KEYIN5,
372 GPIO_FN_KEYIN6, GPIO_FN_KEYIN7,
373 GPIO_FN_KEYOUT0, GPIO_FN_KEYOUT1, GPIO_FN_KEYOUT2,
374 GPIO_FN_KEYOUT3, GPIO_FN_KEYOUT4, GPIO_FN_KEYOUT5,
375 GPIO_FN_KEYOUT6, GPIO_FN_KEYOUT7,
376
377 GPIO_FN_KEYIN0_PORT43, /* MSEL4CR_18_0 */
378 GPIO_FN_KEYIN1_PORT44,
379 GPIO_FN_KEYIN2_PORT45,
380 GPIO_FN_KEYIN3_PORT46,
381
382 GPIO_FN_KEYIN0_PORT58, /* MSEL4CR_18_1 */
383 GPIO_FN_KEYIN1_PORT57,
384 GPIO_FN_KEYIN2_PORT56,
385 GPIO_FN_KEYIN3_PORT55,
386
387 /* VOU */
388 GPIO_FN_DV_D0, GPIO_FN_DV_D1, GPIO_FN_DV_D2, GPIO_FN_DV_D3,
389 GPIO_FN_DV_D4, GPIO_FN_DV_D5, GPIO_FN_DV_D6, GPIO_FN_DV_D7,
390 GPIO_FN_DV_D8, GPIO_FN_DV_D9, GPIO_FN_DV_D10, GPIO_FN_DV_D11,
391 GPIO_FN_DV_D12, GPIO_FN_DV_D13, GPIO_FN_DV_D14, GPIO_FN_DV_D15,
392 GPIO_FN_DV_CLK,
393 GPIO_FN_DV_VSYNC,
394 GPIO_FN_DV_HSYNC,
395
396 /* MEMC */
397 GPIO_FN_MEMC_AD0, GPIO_FN_MEMC_AD1, GPIO_FN_MEMC_AD2,
398 GPIO_FN_MEMC_AD3, GPIO_FN_MEMC_AD4, GPIO_FN_MEMC_AD5,
399 GPIO_FN_MEMC_AD6, GPIO_FN_MEMC_AD7, GPIO_FN_MEMC_AD8,
400 GPIO_FN_MEMC_AD9, GPIO_FN_MEMC_AD10, GPIO_FN_MEMC_AD11,
401 GPIO_FN_MEMC_AD12, GPIO_FN_MEMC_AD13, GPIO_FN_MEMC_AD14,
402 GPIO_FN_MEMC_AD15, GPIO_FN_MEMC_CS0, GPIO_FN_MEMC_INT,
403 GPIO_FN_MEMC_NWE, GPIO_FN_MEMC_NOE,
404
405 GPIO_FN_MEMC_CS1, /* MSEL4CR_6_0 */
406 GPIO_FN_MEMC_ADV,
407 GPIO_FN_MEMC_WAIT,
408 GPIO_FN_MEMC_BUSCLK,
409
410 GPIO_FN_MEMC_A1, /* MSEL4CR_6_1 */
411 GPIO_FN_MEMC_DREQ0,
412 GPIO_FN_MEMC_DREQ1,
413 GPIO_FN_MEMC_A0,
414
415 /* MMC */
416 GPIO_FN_MMC0_D0_PORT68, GPIO_FN_MMC0_D1_PORT69,
417 GPIO_FN_MMC0_D2_PORT70, GPIO_FN_MMC0_D3_PORT71,
418 GPIO_FN_MMC0_D4_PORT72, GPIO_FN_MMC0_D5_PORT73,
419 GPIO_FN_MMC0_D6_PORT74, GPIO_FN_MMC0_D7_PORT75,
420 GPIO_FN_MMC0_CLK_PORT66,
421 GPIO_FN_MMC0_CMD_PORT67, /* MSEL4CR_15_0 */
422
423 GPIO_FN_MMC1_D0_PORT149, GPIO_FN_MMC1_D1_PORT148,
424 GPIO_FN_MMC1_D2_PORT147, GPIO_FN_MMC1_D3_PORT146,
425 GPIO_FN_MMC1_D4_PORT145, GPIO_FN_MMC1_D5_PORT144,
426 GPIO_FN_MMC1_D6_PORT143, GPIO_FN_MMC1_D7_PORT142,
427 GPIO_FN_MMC1_CLK_PORT103,
428 GPIO_FN_MMC1_CMD_PORT104, /* MSEL4CR_15_1 */
429
430 /* MSIOF0 */
431 GPIO_FN_MSIOF0_SS1, GPIO_FN_MSIOF0_SS2,
432 GPIO_FN_MSIOF0_RXD, GPIO_FN_MSIOF0_TXD,
433 GPIO_FN_MSIOF0_MCK0, GPIO_FN_MSIOF0_MCK1,
434 GPIO_FN_MSIOF0_RSYNC, GPIO_FN_MSIOF0_RSCK,
435 GPIO_FN_MSIOF0_TSCK, GPIO_FN_MSIOF0_TSYNC,
436
437 /* MSIOF1 */
438 GPIO_FN_MSIOF1_RSCK, GPIO_FN_MSIOF1_RSYNC,
439 GPIO_FN_MSIOF1_MCK0, GPIO_FN_MSIOF1_MCK1,
440
441 GPIO_FN_MSIOF1_SS2_PORT116, GPIO_FN_MSIOF1_SS1_PORT117,
442 GPIO_FN_MSIOF1_RXD_PORT118, GPIO_FN_MSIOF1_TXD_PORT119,
443 GPIO_FN_MSIOF1_TSYNC_PORT120,
444 GPIO_FN_MSIOF1_TSCK_PORT121, /* MSEL4CR_10_0 */
445
446 GPIO_FN_MSIOF1_SS1_PORT67, GPIO_FN_MSIOF1_TSCK_PORT72,
447 GPIO_FN_MSIOF1_TSYNC_PORT73, GPIO_FN_MSIOF1_TXD_PORT74,
448 GPIO_FN_MSIOF1_RXD_PORT75,
449 GPIO_FN_MSIOF1_SS2_PORT202, /* MSEL4CR_10_1 */
450
451 /* GPIO */
452 GPIO_FN_GPO0, GPIO_FN_GPI0,
453 GPIO_FN_GPO1, GPIO_FN_GPI1,
454
455 /* USB0 */
456 GPIO_FN_USB0_OCI, GPIO_FN_USB0_PPON, GPIO_FN_VBUS,
457
458 /* USB1 */
459 GPIO_FN_USB1_OCI, GPIO_FN_USB1_PPON,
460
461 /* BBIF1 */
462 GPIO_FN_BBIF1_RXD, GPIO_FN_BBIF1_TXD, GPIO_FN_BBIF1_TSYNC,
463 GPIO_FN_BBIF1_TSCK, GPIO_FN_BBIF1_RSCK, GPIO_FN_BBIF1_RSYNC,
464 GPIO_FN_BBIF1_FLOW, GPIO_FN_BBIF1_RX_FLOW_N,
465
466 /* BBIF2 */
467 GPIO_FN_BBIF2_TXD2_PORT5, /* MSEL5CR_0_0 */
468 GPIO_FN_BBIF2_RXD2_PORT60,
469 GPIO_FN_BBIF2_TSYNC2_PORT6,
470 GPIO_FN_BBIF2_TSCK2_PORT59,
471
472 GPIO_FN_BBIF2_RXD2_PORT90, /* MSEL5CR_0_1 */
473 GPIO_FN_BBIF2_TXD2_PORT183,
474 GPIO_FN_BBIF2_TSCK2_PORT89,
475 GPIO_FN_BBIF2_TSYNC2_PORT184,
476
477 /* BSC / FLCTL / PCMCIA */
478 GPIO_FN_CS0, GPIO_FN_CS2, GPIO_FN_CS4,
479 GPIO_FN_CS5B, GPIO_FN_CS6A,
480 GPIO_FN_CS5A_PORT105, /* CS5A PORT 19/105 */
481 GPIO_FN_CS5A_PORT19,
482 GPIO_FN_IOIS16, /* ? */
483
484 GPIO_FN_A0, GPIO_FN_A1, GPIO_FN_A2, GPIO_FN_A3,
485 GPIO_FN_A4_FOE, /* share with FLCTL */
486 GPIO_FN_A5_FCDE, /* share with FLCTL */
487 GPIO_FN_A6, GPIO_FN_A7, GPIO_FN_A8, GPIO_FN_A9,
488 GPIO_FN_A10, GPIO_FN_A11, GPIO_FN_A12, GPIO_FN_A13,
489 GPIO_FN_A14, GPIO_FN_A15, GPIO_FN_A16, GPIO_FN_A17,
490 GPIO_FN_A18, GPIO_FN_A19, GPIO_FN_A20, GPIO_FN_A21,
491 GPIO_FN_A22, GPIO_FN_A23, GPIO_FN_A24, GPIO_FN_A25,
492 GPIO_FN_A26,
493
494 GPIO_FN_D0_NAF0, GPIO_FN_D1_NAF1, /* share with FLCTL */
495 GPIO_FN_D2_NAF2, GPIO_FN_D3_NAF3, /* share with FLCTL */
496 GPIO_FN_D4_NAF4, GPIO_FN_D5_NAF5, /* share with FLCTL */
497 GPIO_FN_D6_NAF6, GPIO_FN_D7_NAF7, /* share with FLCTL */
498 GPIO_FN_D8_NAF8, GPIO_FN_D9_NAF9, /* share with FLCTL */
499 GPIO_FN_D10_NAF10, GPIO_FN_D11_NAF11, /* share with FLCTL */
500 GPIO_FN_D12_NAF12, GPIO_FN_D13_NAF13, /* share with FLCTL */
501 GPIO_FN_D14_NAF14, GPIO_FN_D15_NAF15, /* share with FLCTL */
502
503 GPIO_FN_D16, GPIO_FN_D17, GPIO_FN_D18, GPIO_FN_D19,
504 GPIO_FN_D20, GPIO_FN_D21, GPIO_FN_D22, GPIO_FN_D23,
505 GPIO_FN_D24, GPIO_FN_D25, GPIO_FN_D26, GPIO_FN_D27,
506 GPIO_FN_D28, GPIO_FN_D29, GPIO_FN_D30, GPIO_FN_D31,
507
508 GPIO_FN_WE0_FWE, /* share with FLCTL */
509 GPIO_FN_WE1,
510 GPIO_FN_WE2_ICIORD, /* share with PCMCIA */
511 GPIO_FN_WE3_ICIOWR, /* share with PCMCIA */
512 GPIO_FN_CKO, GPIO_FN_BS, GPIO_FN_RDWR,
513 GPIO_FN_RD_FSC, /* share with FLCTL */
514 GPIO_FN_WAIT_PORT177, /* WAIT Port 90/177 */
515 GPIO_FN_WAIT_PORT90,
516
517 GPIO_FN_FCE0, GPIO_FN_FCE1, GPIO_FN_FRB, /* FLCTL */
518
519 /* IRDA */
520 GPIO_FN_IRDA_FIRSEL, GPIO_FN_IRDA_IN, GPIO_FN_IRDA_OUT,
521
522 /* ATAPI */
523 GPIO_FN_IDE_D0, GPIO_FN_IDE_D1, GPIO_FN_IDE_D2,
524 GPIO_FN_IDE_D3, GPIO_FN_IDE_D4, GPIO_FN_IDE_D5,
525 GPIO_FN_IDE_D6, GPIO_FN_IDE_D7, GPIO_FN_IDE_D8,
526 GPIO_FN_IDE_D9, GPIO_FN_IDE_D10, GPIO_FN_IDE_D11,
527 GPIO_FN_IDE_D12, GPIO_FN_IDE_D13, GPIO_FN_IDE_D14,
528 GPIO_FN_IDE_D15, GPIO_FN_IDE_A0, GPIO_FN_IDE_A1,
529 GPIO_FN_IDE_A2, GPIO_FN_IDE_CS0, GPIO_FN_IDE_CS1,
530 GPIO_FN_IDE_IOWR, GPIO_FN_IDE_IORD, GPIO_FN_IDE_IORDY,
531 GPIO_FN_IDE_INT, GPIO_FN_IDE_RST, GPIO_FN_IDE_DIRECTION,
532 GPIO_FN_IDE_EXBUF_ENB, GPIO_FN_IDE_IODACK, GPIO_FN_IDE_IODREQ,
533
534 /* RMII */
535 GPIO_FN_RMII_CRS_DV, GPIO_FN_RMII_RX_ER, GPIO_FN_RMII_RXD0,
536 GPIO_FN_RMII_RXD1, GPIO_FN_RMII_TX_EN, GPIO_FN_RMII_TXD0,
537 GPIO_FN_RMII_MDC, GPIO_FN_RMII_TXD1, GPIO_FN_RMII_MDIO,
538 GPIO_FN_RMII_REF50CK, /* for RMII */
539 GPIO_FN_RMII_REF125CK, /* for GMII */
540
541 /* GEther */
542 GPIO_FN_ET_TX_CLK, GPIO_FN_ET_TX_EN, GPIO_FN_ET_ETXD0,
543 GPIO_FN_ET_ETXD1, GPIO_FN_ET_ETXD2, GPIO_FN_ET_ETXD3,
544 GPIO_FN_ET_ETXD4, GPIO_FN_ET_ETXD5, /* for GEther */
545 GPIO_FN_ET_ETXD6, GPIO_FN_ET_ETXD7, /* for GEther */
546 GPIO_FN_ET_COL, GPIO_FN_ET_TX_ER,
547 GPIO_FN_ET_RX_CLK, GPIO_FN_ET_RX_DV,
548 GPIO_FN_ET_ERXD0, GPIO_FN_ET_ERXD1,
549 GPIO_FN_ET_ERXD2, GPIO_FN_ET_ERXD3,
550 GPIO_FN_ET_ERXD4, GPIO_FN_ET_ERXD5, /* for GEther */
551 GPIO_FN_ET_ERXD6, GPIO_FN_ET_ERXD7, /* for GEther */
552 GPIO_FN_ET_RX_ER, GPIO_FN_ET_CRS,
553 GPIO_FN_ET_MDC, GPIO_FN_ET_MDIO,
554 GPIO_FN_ET_LINK, GPIO_FN_ET_PHY_INT,
555 GPIO_FN_ET_WOL, GPIO_FN_ET_GTX_CLK,
556
557 /* DMA0 */
558 GPIO_FN_DREQ0, GPIO_FN_DACK0,
559
560 /* DMA1 */
561 GPIO_FN_DREQ1, GPIO_FN_DACK1,
562
563 /* SYSC */
564 GPIO_FN_RESETOUTS,
565 GPIO_FN_RESETP_PULLUP,
566 GPIO_FN_RESETP_PLAIN,
567
568 /* SDENC */
569 GPIO_FN_SDENC_CPG,
570 GPIO_FN_SDENC_DV_CLKI,
571
572 /* IRREM */
573 GPIO_FN_IROUT,
574
575 /* DEBUG */
576 GPIO_FN_EDEBGREQ_PULLDOWN,
577 GPIO_FN_EDEBGREQ_PULLUP,
578
579 GPIO_FN_TRACEAUD_FROM_VIO,
580 GPIO_FN_TRACEAUD_FROM_LCDC0,
581 GPIO_FN_TRACEAUD_FROM_MEMC,
582};
583
584#endif /* __ASM_R8A7740_H__ */
diff --git a/arch/arm/mach-shmobile/intc-r8a7740.c b/arch/arm/mach-shmobile/intc-r8a7740.c
new file mode 100644
index 000000000000..272c84c20c83
--- /dev/null
+++ b/arch/arm/mach-shmobile/intc-r8a7740.c
@@ -0,0 +1,631 @@
1/*
2 * R8A7740 processor support
3 *
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <linux/kernel.h>
22#include <linux/init.h>
23#include <linux/interrupt.h>
24#include <linux/irq.h>
25#include <linux/io.h>
26#include <linux/sh_intc.h>
27#include <mach/intc.h>
28#include <asm/mach-types.h>
29#include <asm/mach/arch.h>
30
31/*
32 * INTCA
33 */
34enum {
35 UNUSED_INTCA = 0,
36
37 /* interrupt sources INTCA */
38 DIRC,
39 ATAPI,
40 IIC1_ALI, IIC1_TACKI, IIC1_WAITI, IIC1_DTEI,
41 AP_ARM_COMMTX, AP_ARM_COMMRX,
42 MFI, MFIS,
43 BBIF1, BBIF2,
44 USBHSDMAC,
45 USBF_OUL_SOF, USBF_IXL_INT,
46 SGX540,
47 CMT1_0, CMT1_1, CMT1_2, CMT1_3,
48 CMT2,
49 CMT3,
50 KEYSC,
51 SCIFA0, SCIFA1, SCIFA2, SCIFA3,
52 MSIOF2, MSIOF1,
53 SCIFA4, SCIFA5, SCIFB,
54 FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
55 SDHI0_0, SDHI0_1, SDHI0_2, SDHI0_3,
56 SDHI1_0, SDHI1_1, SDHI1_2, SDHI1_3,
57 AP_ARM_L2CINT,
58 IRDA,
59 TPU0,
60 SCIFA6, SCIFA7,
61 GbEther,
62 ICBS0,
63 DDM,
64 SDHI2_0, SDHI2_1, SDHI2_2, SDHI2_3,
65 RWDT0,
66 DMAC1_1_DEI0, DMAC1_1_DEI1, DMAC1_1_DEI2, DMAC1_1_DEI3,
67 DMAC1_2_DEI4, DMAC1_2_DEI5, DMAC1_2_DADERR,
68 DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3,
69 DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR,
70 DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3,
71 DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR,
72 SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM,
73 USBH_INT, USBH_OHCI, USBH_EHCI, USBH_PME, USBH_BIND,
74 RSPI_OVRF, RSPI_SPTEF, RSPI_SPRF,
75 SPU2_0, SPU2_1,
76 FSI, FMSI,
77 IPMMU,
78 AP_ARM_CTIIRQ, AP_ARM_PMURQ,
79 MFIS2,
80 CPORTR2S,
81 CMT14, CMT15,
82 MMCIF_0, MMCIF_1, MMCIF_2,
83 SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
84 STPRO_0, STPRO_1, STPRO_2, STPRO_3, STPRO_4,
85
86 /* interrupt groups INTCA */
87 DMAC1_1, DMAC1_2,
88 DMAC2_1, DMAC2_2,
89 DMAC3_1, DMAC3_2,
90 AP_ARM1, AP_ARM2,
91 SDHI0, SDHI1, SDHI2,
92 SHWYSTAT,
93 USBF, USBH1, USBH2,
94 RSPI, SPU2, FLCTL, IIC1,
95};
96
97static struct intc_vect intca_vectors[] __initdata = {
98 INTC_VECT(DIRC, 0x0560),
99 INTC_VECT(ATAPI, 0x05E0),
100 INTC_VECT(IIC1_ALI, 0x0780),
101 INTC_VECT(IIC1_TACKI, 0x07A0),
102 INTC_VECT(IIC1_WAITI, 0x07C0),
103 INTC_VECT(IIC1_DTEI, 0x07E0),
104 INTC_VECT(AP_ARM_COMMTX, 0x0840),
105 INTC_VECT(AP_ARM_COMMRX, 0x0860),
106 INTC_VECT(MFI, 0x0900),
107 INTC_VECT(MFIS, 0x0920),
108 INTC_VECT(BBIF1, 0x0940),
109 INTC_VECT(BBIF2, 0x0960),
110 INTC_VECT(USBHSDMAC, 0x0A00),
111 INTC_VECT(USBF_OUL_SOF, 0x0A20),
112 INTC_VECT(USBF_IXL_INT, 0x0A40),
113 INTC_VECT(SGX540, 0x0A60),
114 INTC_VECT(CMT1_0, 0x0B00),
115 INTC_VECT(CMT1_1, 0x0B20),
116 INTC_VECT(CMT1_2, 0x0B40),
117 INTC_VECT(CMT1_3, 0x0B60),
118 INTC_VECT(CMT2, 0x0B80),
119 INTC_VECT(CMT3, 0x0BA0),
120 INTC_VECT(KEYSC, 0x0BE0),
121 INTC_VECT(SCIFA0, 0x0C00),
122 INTC_VECT(SCIFA1, 0x0C20),
123 INTC_VECT(SCIFA2, 0x0C40),
124 INTC_VECT(SCIFA3, 0x0C60),
125 INTC_VECT(MSIOF2, 0x0C80),
126 INTC_VECT(MSIOF1, 0x0D00),
127 INTC_VECT(SCIFA4, 0x0D20),
128 INTC_VECT(SCIFA5, 0x0D40),
129 INTC_VECT(SCIFB, 0x0D60),
130 INTC_VECT(FLCTL_FLSTEI, 0x0D80),
131 INTC_VECT(FLCTL_FLTENDI, 0x0DA0),
132 INTC_VECT(FLCTL_FLTREQ0I, 0x0DC0),
133 INTC_VECT(FLCTL_FLTREQ1I, 0x0DE0),
134 INTC_VECT(SDHI0_0, 0x0E00),
135 INTC_VECT(SDHI0_1, 0x0E20),
136 INTC_VECT(SDHI0_2, 0x0E40),
137 INTC_VECT(SDHI0_3, 0x0E60),
138 INTC_VECT(SDHI1_0, 0x0E80),
139 INTC_VECT(SDHI1_1, 0x0EA0),
140 INTC_VECT(SDHI1_2, 0x0EC0),
141 INTC_VECT(SDHI1_3, 0x0EE0),
142 INTC_VECT(AP_ARM_L2CINT, 0x0FA0),
143 INTC_VECT(IRDA, 0x0480),
144 INTC_VECT(TPU0, 0x04A0),
145 INTC_VECT(SCIFA6, 0x04C0),
146 INTC_VECT(SCIFA7, 0x04E0),
147 INTC_VECT(GbEther, 0x0500),
148 INTC_VECT(ICBS0, 0x0540),
149 INTC_VECT(DDM, 0x1140),
150 INTC_VECT(SDHI2_0, 0x1200),
151 INTC_VECT(SDHI2_1, 0x1220),
152 INTC_VECT(SDHI2_2, 0x1240),
153 INTC_VECT(SDHI2_3, 0x1260),
154 INTC_VECT(RWDT0, 0x1280),
155 INTC_VECT(DMAC1_1_DEI0, 0x2000),
156 INTC_VECT(DMAC1_1_DEI1, 0x2020),
157 INTC_VECT(DMAC1_1_DEI2, 0x2040),
158 INTC_VECT(DMAC1_1_DEI3, 0x2060),
159 INTC_VECT(DMAC1_2_DEI4, 0x2080),
160 INTC_VECT(DMAC1_2_DEI5, 0x20A0),
161 INTC_VECT(DMAC1_2_DADERR, 0x20C0),
162 INTC_VECT(DMAC2_1_DEI0, 0x2100),
163 INTC_VECT(DMAC2_1_DEI1, 0x2120),
164 INTC_VECT(DMAC2_1_DEI2, 0x2140),
165 INTC_VECT(DMAC2_1_DEI3, 0x2160),
166 INTC_VECT(DMAC2_2_DEI4, 0x2180),
167 INTC_VECT(DMAC2_2_DEI5, 0x21A0),
168 INTC_VECT(DMAC2_2_DADERR, 0x21C0),
169 INTC_VECT(DMAC3_1_DEI0, 0x2200),
170 INTC_VECT(DMAC3_1_DEI1, 0x2220),
171 INTC_VECT(DMAC3_1_DEI2, 0x2240),
172 INTC_VECT(DMAC3_1_DEI3, 0x2260),
173 INTC_VECT(DMAC3_2_DEI4, 0x2280),
174 INTC_VECT(DMAC3_2_DEI5, 0x22A0),
175 INTC_VECT(DMAC3_2_DADERR, 0x22C0),
176 INTC_VECT(SHWYSTAT_RT, 0x1300),
177 INTC_VECT(SHWYSTAT_HS, 0x1320),
178 INTC_VECT(SHWYSTAT_COM, 0x1340),
179 INTC_VECT(USBH_INT, 0x1540),
180 INTC_VECT(USBH_OHCI, 0x1560),
181 INTC_VECT(USBH_EHCI, 0x1580),
182 INTC_VECT(USBH_PME, 0x15A0),
183 INTC_VECT(USBH_BIND, 0x15C0),
184 INTC_VECT(RSPI_OVRF, 0x1780),
185 INTC_VECT(RSPI_SPTEF, 0x17A0),
186 INTC_VECT(RSPI_SPRF, 0x17C0),
187 INTC_VECT(SPU2_0, 0x1800),
188 INTC_VECT(SPU2_1, 0x1820),
189 INTC_VECT(FSI, 0x1840),
190 INTC_VECT(FMSI, 0x1860),
191 INTC_VECT(IPMMU, 0x1920),
192 INTC_VECT(AP_ARM_CTIIRQ, 0x1980),
193 INTC_VECT(AP_ARM_PMURQ, 0x19A0),
194 INTC_VECT(MFIS2, 0x1A00),
195 INTC_VECT(CPORTR2S, 0x1A20),
196 INTC_VECT(CMT14, 0x1A40),
197 INTC_VECT(CMT15, 0x1A60),
198 INTC_VECT(MMCIF_0, 0x1AA0),
199 INTC_VECT(MMCIF_1, 0x1AC0),
200 INTC_VECT(MMCIF_2, 0x1AE0),
201 INTC_VECT(SIM_ERI, 0x1C00),
202 INTC_VECT(SIM_RXI, 0x1C20),
203 INTC_VECT(SIM_TXI, 0x1C40),
204 INTC_VECT(SIM_TEI, 0x1C60),
205 INTC_VECT(STPRO_0, 0x1C80),
206 INTC_VECT(STPRO_1, 0x1CA0),
207 INTC_VECT(STPRO_2, 0x1CC0),
208 INTC_VECT(STPRO_3, 0x1CE0),
209 INTC_VECT(STPRO_4, 0x1D00),
210};
211
212static struct intc_group intca_groups[] __initdata = {
213 INTC_GROUP(DMAC1_1,
214 DMAC1_1_DEI0, DMAC1_1_DEI1, DMAC1_1_DEI2, DMAC1_1_DEI3),
215 INTC_GROUP(DMAC1_2,
216 DMAC1_2_DEI4, DMAC1_2_DEI5, DMAC1_2_DADERR),
217 INTC_GROUP(DMAC2_1,
218 DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3),
219 INTC_GROUP(DMAC2_2,
220 DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR),
221 INTC_GROUP(DMAC3_1,
222 DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3),
223 INTC_GROUP(DMAC3_2,
224 DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR),
225 INTC_GROUP(AP_ARM1,
226 AP_ARM_COMMTX, AP_ARM_COMMRX),
227 INTC_GROUP(AP_ARM2,
228 AP_ARM_CTIIRQ, AP_ARM_PMURQ),
229 INTC_GROUP(USBF,
230 USBF_OUL_SOF, USBF_IXL_INT),
231 INTC_GROUP(SDHI0,
232 SDHI0_0, SDHI0_1, SDHI0_2, SDHI0_3),
233 INTC_GROUP(SDHI1,
234 SDHI1_0, SDHI1_1, SDHI1_2, SDHI1_3),
235 INTC_GROUP(SDHI2,
236 SDHI2_0, SDHI2_1, SDHI2_2, SDHI2_3),
237 INTC_GROUP(SHWYSTAT,
238 SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM),
239 INTC_GROUP(USBH1, /* FIXME */
240 USBH_INT, USBH_OHCI),
241 INTC_GROUP(USBH2, /* FIXME */
242 USBH_EHCI,
243 USBH_PME, USBH_BIND),
244 INTC_GROUP(RSPI,
245 RSPI_OVRF, RSPI_SPTEF, RSPI_SPRF),
246 INTC_GROUP(SPU2,
247 SPU2_0, SPU2_1),
248 INTC_GROUP(FLCTL,
249 FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
250 INTC_GROUP(IIC1,
251 IIC1_ALI, IIC1_TACKI, IIC1_WAITI, IIC1_DTEI),
252};
253
254static struct intc_mask_reg intca_mask_registers[] __initdata = {
255 { /* IMR0A / IMCR0A */ 0xe6940080, 0xe69400c0, 8,
256 { DMAC2_1_DEI3, DMAC2_1_DEI2, DMAC2_1_DEI1, DMAC2_1_DEI0,
257 0, 0, AP_ARM_COMMTX, AP_ARM_COMMRX } },
258 { /* IMR1A / IMCR1A */ 0xe6940084, 0xe69400c4, 8,
259 { ATAPI, 0, DIRC, 0,
260 DMAC1_1_DEI3, DMAC1_1_DEI2, DMAC1_1_DEI1, DMAC1_1_DEI0 } },
261 { /* IMR2A / IMCR2A */ 0xe6940088, 0xe69400c8, 8,
262 { 0, 0, 0, 0,
263 BBIF1, BBIF2, MFIS, MFI } },
264 { /* IMR3A / IMCR3A */ 0xe694008c, 0xe69400cc, 8,
265 { DMAC3_1_DEI3, DMAC3_1_DEI2, DMAC3_1_DEI1, DMAC3_1_DEI0,
266 DMAC3_2_DADERR, DMAC3_2_DEI5, DMAC3_2_DEI4, IRDA } },
267 { /* IMR4A / IMCR4A */ 0xe6940090, 0xe69400d0, 8,
268 { DDM, 0, 0, 0,
269 0, 0, 0, 0 } },
270 { /* IMR5A / IMCR5A */ 0xe6940094, 0xe69400d4, 8,
271 { KEYSC, DMAC1_2_DADERR, DMAC1_2_DEI5, DMAC1_2_DEI4,
272 SCIFA3, SCIFA2, SCIFA1, SCIFA0 } },
273 { /* IMR6A / IMCR6A */ 0xe6940098, 0xe69400d8, 8,
274 { SCIFB, SCIFA5, SCIFA4, MSIOF1,
275 0, 0, MSIOF2, 0 } },
276 { /* IMR7A / IMCR7A */ 0xe694009c, 0xe69400dc, 8,
277 { SDHI0_3, SDHI0_2, SDHI0_1, SDHI0_0,
278 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
279 { /* IMR8A / IMCR8A */ 0xe69400a0, 0xe69400e0, 8,
280 { SDHI1_3, SDHI1_2, SDHI1_1, SDHI1_0,
281 0, USBHSDMAC, 0, AP_ARM_L2CINT } },
282 { /* IMR9A / IMCR9A */ 0xe69400a4, 0xe69400e4, 8,
283 { CMT1_3, CMT1_2, CMT1_1, CMT1_0,
284 CMT2, USBF_IXL_INT, USBF_OUL_SOF, SGX540 } },
285 { /* IMR10A / IMCR10A */ 0xe69400a8, 0xe69400e8, 8,
286 { 0, DMAC2_2_DADERR, DMAC2_2_DEI5, DMAC2_2_DEI4,
287 0, 0, 0, 0 } },
288 { /* IMR11A / IMCR11A */ 0xe69400ac, 0xe69400ec, 8,
289 { IIC1_DTEI, IIC1_WAITI, IIC1_TACKI, IIC1_ALI,
290 ICBS0, 0, 0, 0 } },
291 { /* IMR12A / IMCR12A */ 0xe69400b0, 0xe69400f0, 8,
292 { 0, 0, TPU0, SCIFA6,
293 SCIFA7, GbEther, 0, 0 } },
294 { /* IMR13A / IMCR13A */ 0xe69400b4, 0xe69400f4, 8,
295 { SDHI2_3, SDHI2_2, SDHI2_1, SDHI2_0,
296 0, CMT3, 0, RWDT0 } },
297 { /* IMR0A3 / IMCR0A3 */ 0xe6950080, 0xe69500c0, 8,
298 { SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM, 0,
299 0, 0, 0, 0 } },
300 /* IMR1A3 / IMCR1A3 */
301 { /* IMR2A3 / IMCR2A3 */ 0xe6950088, 0xe69500c8, 8,
302 { 0, 0, USBH_INT, USBH_OHCI,
303 USBH_EHCI, USBH_PME, USBH_BIND, 0 } },
304 /* IMR3A3 / IMCR3A3 */
305 { /* IMR4A3 / IMCR4A3 */ 0xe6950090, 0xe69500d0, 8,
306 { 0, 0, 0, 0,
307 RSPI_OVRF, RSPI_SPTEF, RSPI_SPRF, 0 } },
308 { /* IMR5A3 / IMCR5A3 */ 0xe6950094, 0xe69500d4, 8,
309 { SPU2_0, SPU2_1, FSI, FMSI,
310 0, 0, 0, 0 } },
311 { /* IMR6A3 / IMCR6A3 */ 0xe6950098, 0xe69500d8, 8,
312 { 0, IPMMU, 0, 0,
313 AP_ARM_CTIIRQ, AP_ARM_PMURQ, 0, 0 } },
314 { /* IMR7A3 / IMCR7A3 */ 0xe695009c, 0xe69500dc, 8,
315 { MFIS2, CPORTR2S, CMT14, CMT15,
316 0, MMCIF_0, MMCIF_1, MMCIF_2 } },
317 /* IMR8A3 / IMCR8A3 */
318 { /* IMR9A3 / IMCR9A3 */ 0xe69500a4, 0xe69500e4, 8,
319 { SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
320 STPRO_0, STPRO_1, STPRO_2, STPRO_3 } },
321 { /* IMR10A3 / IMCR10A3 */ 0xe69500a8, 0xe69500e8, 8,
322 { STPRO_4, 0, 0, 0,
323 0, 0, 0, 0 } },
324};
325
326static struct intc_prio_reg intca_prio_registers[] __initdata = {
327 { 0xe6940000, 0, 16, 4, /* IPRAA */ { DMAC3_1, DMAC3_2, CMT2, ICBS0 } },
328 { 0xe6940004, 0, 16, 4, /* IPRBA */ { IRDA, 0, BBIF1, BBIF2 } },
329 { 0xe6940008, 0, 16, 4, /* IPRCA */ { ATAPI, 0, CMT1_1, AP_ARM1 } },
330 { 0xe694000c, 0, 16, 4, /* IPRDA */ { 0, 0, CMT1_2, 0 } },
331 { 0xe6940010, 0, 16, 4, /* IPREA */ { DMAC1_1, MFIS, MFI, USBF } },
332 { 0xe6940014, 0, 16, 4, /* IPRFA */ { KEYSC, DMAC1_2,
333 SGX540, CMT1_0 } },
334 { 0xe6940018, 0, 16, 4, /* IPRGA */ { SCIFA0, SCIFA1,
335 SCIFA2, SCIFA3 } },
336 { 0xe694001c, 0, 16, 4, /* IPRGH */ { MSIOF2, USBHSDMAC,
337 FLCTL, SDHI0 } },
338 { 0xe6940020, 0, 16, 4, /* IPRIA */ { MSIOF1, SCIFA4, 0, IIC1 } },
339 { 0xe6940024, 0, 16, 4, /* IPRJA */ { DMAC2_1, DMAC2_2,
340 AP_ARM_L2CINT, 0 } },
341 { 0xe6940028, 0, 16, 4, /* IPRKA */ { 0, CMT1_3, 0, SDHI1 } },
342 { 0xe694002c, 0, 16, 4, /* IPRLA */ { TPU0, SCIFA6,
343 SCIFA7, GbEther } },
344 { 0xe6940030, 0, 16, 4, /* IPRMA */ { 0, CMT3, 0, RWDT0 } },
345 { 0xe6940034, 0, 16, 4, /* IPRNA */ { SCIFB, SCIFA5, 0, DDM } },
346 { 0xe6940038, 0, 16, 4, /* IPROA */ { 0, 0, DIRC, SDHI2 } },
347 { 0xe6950000, 0, 16, 4, /* IPRAA3 */ { SHWYSTAT, 0, 0, 0 } },
348 /* IPRBA3 */
349 /* IPRCA3 */
350 /* IPRDA3 */
351 { 0xe6950010, 0, 16, 4, /* IPREA3 */ { USBH1, 0, 0, 0 } },
352 { 0xe6950014, 0, 16, 4, /* IPRFA3 */ { USBH2, 0, 0, 0 } },
353 /* IPRGA3 */
354 /* IPRHA3 */
355 /* IPRIA3 */
356 { 0xe6950024, 0, 16, 4, /* IPRJA3 */ { RSPI, 0, 0, 0 } },
357 { 0xe6950028, 0, 16, 4, /* IPRKA3 */ { SPU2, 0, FSI, FMSI } },
358 /* IPRLA3 */
359 { 0xe6950030, 0, 16, 4, /* IPRMA3 */ { IPMMU, 0, 0, 0 } },
360 { 0xe6950034, 0, 16, 4, /* IPRNA3 */ { AP_ARM2, 0, 0, 0 } },
361 { 0xe6950038, 0, 16, 4, /* IPROA3 */ { MFIS2, CPORTR2S,
362 CMT14, CMT15 } },
363 { 0xe695003c, 0, 16, 4, /* IPRPA3 */ { 0, MMCIF_0, MMCIF_1, MMCIF_2 } },
364 /* IPRQA3 */
365 /* IPRRA3 */
366 { 0xe6950048, 0, 16, 4, /* IPRSA3 */ { SIM_ERI, SIM_RXI,
367 SIM_TXI, SIM_TEI } },
368 { 0xe695004c, 0, 16, 4, /* IPRTA3 */ { STPRO_0, STPRO_1,
369 STPRO_2, STPRO_3 } },
370 { 0xe6950050, 0, 16, 4, /* IPRUA3 */ { STPRO_4, 0, 0, 0 } },
371};
372
373static DECLARE_INTC_DESC(intca_desc, "r8a7740-intca",
374 intca_vectors, intca_groups,
375 intca_mask_registers, intca_prio_registers,
376 NULL);
377
378INTC_IRQ_PINS_32(intca_irq_pins, 0xe6900000,
379 INTC_VECT, "r8a7740-intca-irq-pins");
380
381
382/*
383 * INTCS
384 */
385enum {
386 UNUSED_INTCS = 0,
387
388 INTCS,
389
390 /* interrupt sources INTCS */
391
392 /* HUDI */
393 /* STPRO */
394 /* RTDMAC(1) */
395 VPU5HA2,
396 _2DG_TRAP, _2DG_GPM_INT, _2DG_CER_INT,
397 /* MFI */
398 /* BBIF2 */
399 VPU5F,
400 _2DG_BRK_INT,
401 /* SGX540 */
402 /* 2DDMAC */
403 /* IPMMU */
404 /* RTDMAC 2 */
405 /* KEYSC */
406 /* MSIOF */
407 IIC0_ALI, IIC0_TACKI, IIC0_WAITI, IIC0_DTEI,
408 TMU0_0, TMU0_1, TMU0_2,
409 CMT0,
410 /* CMT2 */
411 LMB,
412 CTI,
413 VOU,
414 /* RWDT0 */
415 ICB,
416 VIO6C,
417 CEU20, CEU21,
418 JPU,
419 LCDC0,
420 LCRC,
421 /* RTDMAC2(1) */
422 /* RTDMAC2(2) */
423 LCDC1,
424 /* SPU2 */
425 /* FSI */
426 /* FMSI */
427 TMU1_0, TMU1_1, TMU1_2,
428 CMT4,
429 DISP,
430 DSRV,
431 /* MFIS2 */
432 CPORTS2R,
433
434 /* interrupt groups INTCS */
435 _2DG1,
436 IIC0, TMU1,
437};
438
439static struct intc_vect intcs_vectors[] = {
440 /* HUDI */
441 /* STPRO */
442 /* RTDMAC(1) */
443 INTCS_VECT(VPU5HA2, 0x0880),
444 INTCS_VECT(_2DG_TRAP, 0x08A0),
445 INTCS_VECT(_2DG_GPM_INT, 0x08C0),
446 INTCS_VECT(_2DG_CER_INT, 0x08E0),
447 /* MFI */
448 /* BBIF2 */
449 INTCS_VECT(VPU5F, 0x0980),
450 INTCS_VECT(_2DG_BRK_INT, 0x09A0),
451 /* SGX540 */
452 /* 2DDMAC */
453 /* IPMMU */
454 /* RTDMAC(2) */
455 /* KEYSC */
456 /* MSIOF */
457 INTCS_VECT(IIC0_ALI, 0x0E00),
458 INTCS_VECT(IIC0_TACKI, 0x0E20),
459 INTCS_VECT(IIC0_WAITI, 0x0E40),
460 INTCS_VECT(IIC0_DTEI, 0x0E60),
461 INTCS_VECT(TMU0_0, 0x0E80),
462 INTCS_VECT(TMU0_1, 0x0EA0),
463 INTCS_VECT(TMU0_2, 0x0EC0),
464 INTCS_VECT(CMT0, 0x0F00),
465 /* CMT2 */
466 INTCS_VECT(LMB, 0x0F60),
467 INTCS_VECT(CTI, 0x0400),
468 INTCS_VECT(VOU, 0x0420),
469 /* RWDT0 */
470 INTCS_VECT(ICB, 0x0480),
471 INTCS_VECT(VIO6C, 0x04E0),
472 INTCS_VECT(CEU20, 0x0500),
473 INTCS_VECT(CEU21, 0x0520),
474 INTCS_VECT(JPU, 0x0560),
475 INTCS_VECT(LCDC0, 0x0580),
476 INTCS_VECT(LCRC, 0x05A0),
477 /* RTDMAC2(1) */
478 /* RTDMAC2(2) */
479 INTCS_VECT(LCDC1, 0x1780),
480 /* SPU2 */
481 /* FSI */
482 /* FMSI */
483 INTCS_VECT(TMU1_0, 0x1900),
484 INTCS_VECT(TMU1_1, 0x1920),
485 INTCS_VECT(TMU1_2, 0x1940),
486 INTCS_VECT(CMT4, 0x1980),
487 INTCS_VECT(DISP, 0x19A0),
488 INTCS_VECT(DSRV, 0x19C0),
489 /* MFIS2 */
490 INTCS_VECT(CPORTS2R, 0x1A20),
491
492 INTC_VECT(INTCS, 0xf80),
493};
494
495static struct intc_group intcs_groups[] __initdata = {
496 INTC_GROUP(_2DG1, /*FIXME*/
497 _2DG_CER_INT, _2DG_GPM_INT, _2DG_TRAP),
498 INTC_GROUP(IIC0,
499 IIC0_DTEI, IIC0_WAITI, IIC0_TACKI, IIC0_ALI),
500 INTC_GROUP(TMU1,
501 TMU1_0, TMU1_1, TMU1_2),
502};
503
504static struct intc_mask_reg intcs_mask_registers[] = {
505 /* IMR0SA / IMCR0SA */ /* all 0 */
506 { /* IMR1SA / IMCR1SA */ 0xffd20184, 0xffd201c4, 8,
507 { _2DG_CER_INT, _2DG_GPM_INT, _2DG_TRAP, VPU5HA2,
508 0, 0, 0, 0 /*STPRO*/ } },
509 { /* IMR2SA / IMCR2SA */ 0xffd20188, 0xffd201c8, 8,
510 { 0/*STPRO*/, 0, CEU21, VPU5F,
511 0/*BBIF2*/, 0, 0, 0/*MFI*/ } },
512 { /* IMR3SA / IMCR3SA */ 0xffd2018c, 0xffd201cc, 8,
513 { 0, 0, 0, 0, /*2DDMAC*/
514 VIO6C, 0, 0, ICB } },
515 { /* IMR4SA / IMCR4SA */ 0xffd20190, 0xffd201d0, 8,
516 { 0, 0, VOU, CTI,
517 JPU, 0, LCRC, LCDC0 } },
518 /* IMR5SA / IMCR5SA */ /*KEYSC/RTDMAC2/RTDMAC1*/
519 /* IMR6SA / IMCR6SA */ /*MSIOF/SGX540*/
520 { /* IMR7SA / IMCR7SA */ 0xffd2019c, 0xffd201dc, 8,
521 { 0, TMU0_2, TMU0_1, TMU0_0,
522 0, 0, 0, 0 } },
523 { /* IMR8SA / IMCR8SA */ 0xffd201a0, 0xffd201e0, 8,
524 { 0, 0, 0, 0,
525 CEU20, 0, 0, 0 } },
526 { /* IMR9SA / IMCR9SA */ 0xffd201a4, 0xffd201e4, 8,
527 { 0, 0/*RWDT0*/, 0/*CMT2*/, CMT0,
528 0, 0, 0, 0 } },
529 /* IMR10SA / IMCR10SA */ /*IPMMU*/
530 { /* IMR11SA / IMCR11SA */ 0xffd201ac, 0xffd201ec, 8,
531 { IIC0_DTEI, IIC0_WAITI, IIC0_TACKI, IIC0_ALI,
532 0, _2DG_BRK_INT, LMB, 0 } },
533 /* IMR12SA / IMCR12SA */
534 /* IMR13SA / IMCR13SA */
535 /* IMR0SA3 / IMCR0SA3 */ /*RTDMAC2(1)/RTDMAC2(2)*/
536 /* IMR1SA3 / IMCR1SA3 */
537 /* IMR2SA3 / IMCR2SA3 */
538 /* IMR3SA3 / IMCR3SA3 */
539 { /* IMR4SA3 / IMCR4SA3 */ 0xffd50190, 0xffd501d0, 8,
540 { 0, 0, 0, 0,
541 LCDC1, 0, 0, 0 } },
542 /* IMR5SA3 / IMCR5SA3 */ /* SPU2/FSI/FMSI */
543 { /* IMR6SA3 / IMCR6SA3 */ 0xffd50198, 0xffd501d8, 8,
544 { TMU1_0, TMU1_1, TMU1_2, 0,
545 CMT4, DISP, DSRV, 0 } },
546 { /* IMR7SA3 / IMCR7SA3 */ 0xffd5019c, 0xffd501dc, 8,
547 { 0/*MFIS2*/, CPORTS2R, 0, 0,
548 0, 0, 0, 0 } },
549 { /* INTAMASK */ 0xffd20104, 0, 16,
550 { 0, 0, 0, 0, 0, 0, 0, 0,
551 0, 0, 0, 0, 0, 0, 0, INTCS } },
552};
553
554/* Priority is needed for INTCA to receive the INTCS interrupt */
555static struct intc_prio_reg intcs_prio_registers[] = {
556 { 0xffd20000, 0, 16, 4, /* IPRAS */ { CTI, VOU, 0/*2DDMAC*/, ICB } },
557 { 0xffd20004, 0, 16, 4, /* IPRBS */ { JPU, LCDC0, 0, LCRC } },
558 /* IPRCS */ /*BBIF2*/
559 /* IPRDS */
560 { 0xffd20010, 0, 16, 4, /* IPRES */ { 0/*RTDMAC(1)*/, VPU5HA2,
561 0/*MFI*/, VPU5F } },
562 { 0xffd20014, 0, 16, 4, /* IPRFS */ { 0/*KEYSC*/, 0/*RTDMAC(2)*/,
563 0/*CMT2*/, CMT0 } },
564 { 0xffd20018, 0, 16, 4, /* IPRGS */ { TMU0_0, TMU0_1,
565 TMU0_2, _2DG1 } },
566 { 0xffd2001c, 0, 16, 4, /* IPRHS */ { 0, 0/*STPRO*/, 0/*STPRO*/,
567 _2DG_BRK_INT/*FIXME*/ } },
568 { 0xffd20020, 0, 16, 4, /* IPRIS */ { 0, 0/*MSIOF*/, 0, IIC0 } },
569 { 0xffd20024, 0, 16, 4, /* IPRJS */ { CEU20, 0/*SGX540*/, 0, 0 } },
570 { 0xffd20028, 0, 16, 4, /* IPRKS */ { VIO6C, 0, LMB, 0 } },
571 { 0xffd2002c, 0, 16, 4, /* IPRLS */ { 0/*IPMMU*/, 0, CEU21, 0 } },
572 /* IPRMS */ /*RWDT0*/
573 /* IPRAS3 */ /*RTDMAC2(1)*/
574 /* IPRBS3 */ /*RTDMAC2(2)*/
575 /* IPRCS3 */
576 /* IPRDS3 */
577 /* IPRES3 */
578 /* IPRFS3 */
579 /* IPRGS3 */
580 /* IPRHS3 */
581 /* IPRIS3 */
582 { 0xffd50024, 0, 16, 4, /* IPRJS3 */ { LCDC1, 0, 0, 0 } },
583 /* IPRKS3 */ /*SPU2/FSI/FMSi*/
584 /* IPRLS3 */
585 { 0xffd50030, 0, 16, 4, /* IPRMS3 */ { TMU1, 0, 0, 0 } },
586 { 0xffd50034, 0, 16, 4, /* IPRNS3 */ { CMT4, DISP, DSRV, 0 } },
587 { 0xffd50038, 0, 16, 4, /* IPROS3 */ { 0/*MFIS2*/, CPORTS2R, 0, 0 } },
588 /* IPRPS3 */
589};
590
591static struct resource intcs_resources[] __initdata = {
592 [0] = {
593 .start = 0xffd20000,
594 .end = 0xffd201ff,
595 .flags = IORESOURCE_MEM,
596 },
597 [1] = {
598 .start = 0xffd50000,
599 .end = 0xffd501ff,
600 .flags = IORESOURCE_MEM,
601 }
602};
603
604static struct intc_desc intcs_desc __initdata = {
605 .name = "r8a7740-intcs",
606 .resource = intcs_resources,
607 .num_resources = ARRAY_SIZE(intcs_resources),
608 .hw = INTC_HW_DESC(intcs_vectors, intcs_groups, intcs_mask_registers,
609 intcs_prio_registers, NULL, NULL),
610};
611
612static void intcs_demux(unsigned int irq, struct irq_desc *desc)
613{
614 void __iomem *reg = (void *)irq_get_handler_data(irq);
615 unsigned int evtcodeas = ioread32(reg);
616
617 generic_handle_irq(intcs_evt2irq(evtcodeas));
618}
619
620void __init r8a7740_init_irq(void)
621{
622 void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE);
623
624 register_intc_controller(&intca_desc);
625 register_intc_controller(&intca_irq_pins_desc);
626 register_intc_controller(&intcs_desc);
627
628 /* demux using INTEVTSA */
629 irq_set_handler_data(evt2irq(0xf80), (void *)intevtsa);
630 irq_set_chained_handler(evt2irq(0xf80), intcs_demux);
631}
diff --git a/arch/arm/mach-shmobile/pfc-r8a7740.c b/arch/arm/mach-shmobile/pfc-r8a7740.c
new file mode 100644
index 000000000000..a4fff6950b03
--- /dev/null
+++ b/arch/arm/mach-shmobile/pfc-r8a7740.c
@@ -0,0 +1,2562 @@
1/*
2 * R8A7740 processor support
3 *
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; version 2 of the
10 * License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */
21#include <linux/init.h>
22#include <linux/kernel.h>
23#include <linux/gpio.h>
24#include <mach/r8a7740.h>
25
26#define CPU_ALL_PORT(fn, pfx, sfx) \
27 PORT_10(fn, pfx, sfx), PORT_90(fn, pfx, sfx), \
28 PORT_10(fn, pfx##10, sfx), PORT_90(fn, pfx##1, sfx), \
29 PORT_10(fn, pfx##20, sfx), \
30 PORT_1(fn, pfx##210, sfx), PORT_1(fn, pfx##211, sfx)
31
32enum {
33 PINMUX_RESERVED = 0,
34
35 /* PORT0_DATA -> PORT211_DATA */
36 PINMUX_DATA_BEGIN,
37 PORT_ALL(DATA),
38 PINMUX_DATA_END,
39
40 /* PORT0_IN -> PORT211_IN */
41 PINMUX_INPUT_BEGIN,
42 PORT_ALL(IN),
43 PINMUX_INPUT_END,
44
45 /* PORT0_IN_PU -> PORT211_IN_PU */
46 PINMUX_INPUT_PULLUP_BEGIN,
47 PORT_ALL(IN_PU),
48 PINMUX_INPUT_PULLUP_END,
49
50 /* PORT0_IN_PD -> PORT211_IN_PD */
51 PINMUX_INPUT_PULLDOWN_BEGIN,
52 PORT_ALL(IN_PD),
53 PINMUX_INPUT_PULLDOWN_END,
54
55 /* PORT0_OUT -> PORT211_OUT */
56 PINMUX_OUTPUT_BEGIN,
57 PORT_ALL(OUT),
58 PINMUX_OUTPUT_END,
59
60 PINMUX_FUNCTION_BEGIN,
61 PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT211_FN_IN */
62 PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT211_FN_OUT */
63 PORT_ALL(FN0), /* PORT0_FN0 -> PORT211_FN0 */
64 PORT_ALL(FN1), /* PORT0_FN1 -> PORT211_FN1 */
65 PORT_ALL(FN2), /* PORT0_FN2 -> PORT211_FN2 */
66 PORT_ALL(FN3), /* PORT0_FN3 -> PORT211_FN3 */
67 PORT_ALL(FN4), /* PORT0_FN4 -> PORT211_FN4 */
68 PORT_ALL(FN5), /* PORT0_FN5 -> PORT211_FN5 */
69 PORT_ALL(FN6), /* PORT0_FN6 -> PORT211_FN6 */
70 PORT_ALL(FN7), /* PORT0_FN7 -> PORT211_FN7 */
71
72 MSEL1CR_31_0, MSEL1CR_31_1,
73 MSEL1CR_30_0, MSEL1CR_30_1,
74 MSEL1CR_29_0, MSEL1CR_29_1,
75 MSEL1CR_28_0, MSEL1CR_28_1,
76 MSEL1CR_27_0, MSEL1CR_27_1,
77 MSEL1CR_26_0, MSEL1CR_26_1,
78 MSEL1CR_16_0, MSEL1CR_16_1,
79 MSEL1CR_15_0, MSEL1CR_15_1,
80 MSEL1CR_14_0, MSEL1CR_14_1,
81 MSEL1CR_13_0, MSEL1CR_13_1,
82 MSEL1CR_12_0, MSEL1CR_12_1,
83 MSEL1CR_9_0, MSEL1CR_9_1,
84 MSEL1CR_7_0, MSEL1CR_7_1,
85 MSEL1CR_6_0, MSEL1CR_6_1,
86 MSEL1CR_5_0, MSEL1CR_5_1,
87 MSEL1CR_4_0, MSEL1CR_4_1,
88 MSEL1CR_3_0, MSEL1CR_3_1,
89 MSEL1CR_2_0, MSEL1CR_2_1,
90 MSEL1CR_0_0, MSEL1CR_0_1,
91
92 MSEL3CR_15_0, MSEL3CR_15_1, /* Trace / Debug ? */
93 MSEL3CR_6_0, MSEL3CR_6_1,
94
95 MSEL4CR_19_0, MSEL4CR_19_1,
96 MSEL4CR_18_0, MSEL4CR_18_1,
97 MSEL4CR_15_0, MSEL4CR_15_1,
98 MSEL4CR_10_0, MSEL4CR_10_1,
99 MSEL4CR_6_0, MSEL4CR_6_1,
100 MSEL4CR_4_0, MSEL4CR_4_1,
101 MSEL4CR_1_0, MSEL4CR_1_1,
102
103 MSEL5CR_31_0, MSEL5CR_31_1, /* irq/fiq output */
104 MSEL5CR_30_0, MSEL5CR_30_1,
105 MSEL5CR_29_0, MSEL5CR_29_1,
106 MSEL5CR_27_0, MSEL5CR_27_1,
107 MSEL5CR_25_0, MSEL5CR_25_1,
108 MSEL5CR_23_0, MSEL5CR_23_1,
109 MSEL5CR_21_0, MSEL5CR_21_1,
110 MSEL5CR_19_0, MSEL5CR_19_1,
111 MSEL5CR_17_0, MSEL5CR_17_1,
112 MSEL5CR_15_0, MSEL5CR_15_1,
113 MSEL5CR_14_0, MSEL5CR_14_1,
114 MSEL5CR_13_0, MSEL5CR_13_1,
115 MSEL5CR_12_0, MSEL5CR_12_1,
116 MSEL5CR_11_0, MSEL5CR_11_1,
117 MSEL5CR_10_0, MSEL5CR_10_1,
118 MSEL5CR_8_0, MSEL5CR_8_1,
119 MSEL5CR_7_0, MSEL5CR_7_1,
120 MSEL5CR_6_0, MSEL5CR_6_1,
121 MSEL5CR_5_0, MSEL5CR_5_1,
122 MSEL5CR_4_0, MSEL5CR_4_1,
123 MSEL5CR_3_0, MSEL5CR_3_1,
124 MSEL5CR_2_0, MSEL5CR_2_1,
125 MSEL5CR_0_0, MSEL5CR_0_1,
126 PINMUX_FUNCTION_END,
127
128 PINMUX_MARK_BEGIN,
129
130 /* IRQ */
131 IRQ0_PORT2_MARK, IRQ0_PORT13_MARK,
132 IRQ1_MARK,
133 IRQ2_PORT11_MARK, IRQ2_PORT12_MARK,
134 IRQ3_PORT10_MARK, IRQ3_PORT14_MARK,
135 IRQ4_PORT15_MARK, IRQ4_PORT172_MARK,
136 IRQ5_PORT0_MARK, IRQ5_PORT1_MARK,
137 IRQ6_PORT121_MARK, IRQ6_PORT173_MARK,
138 IRQ7_PORT120_MARK, IRQ7_PORT209_MARK,
139 IRQ8_MARK,
140 IRQ9_PORT118_MARK, IRQ9_PORT210_MARK,
141 IRQ10_MARK,
142 IRQ11_MARK,
143 IRQ12_PORT42_MARK, IRQ12_PORT97_MARK,
144 IRQ13_PORT64_MARK, IRQ13_PORT98_MARK,
145 IRQ14_PORT63_MARK, IRQ14_PORT99_MARK,
146 IRQ15_PORT62_MARK, IRQ15_PORT100_MARK,
147 IRQ16_PORT68_MARK, IRQ16_PORT211_MARK,
148 IRQ17_MARK,
149 IRQ18_MARK,
150 IRQ19_MARK,
151 IRQ20_MARK,
152 IRQ21_MARK,
153 IRQ22_MARK,
154 IRQ23_MARK,
155 IRQ24_MARK,
156 IRQ25_MARK,
157 IRQ26_PORT58_MARK, IRQ26_PORT81_MARK,
158 IRQ27_PORT57_MARK, IRQ27_PORT168_MARK,
159 IRQ28_PORT56_MARK, IRQ28_PORT169_MARK,
160 IRQ29_PORT50_MARK, IRQ29_PORT170_MARK,
161 IRQ30_PORT49_MARK, IRQ30_PORT171_MARK,
162 IRQ31_PORT41_MARK, IRQ31_PORT167_MARK,
163
164 /* Function */
165
166 /* DBGT */
167 DBGMDT2_MARK, DBGMDT1_MARK, DBGMDT0_MARK,
168 DBGMD10_MARK, DBGMD11_MARK, DBGMD20_MARK,
169 DBGMD21_MARK,
170
171 /* FSI */
172 FSIAISLD_PORT0_MARK, /* FSIAISLD Port 0/5 */
173 FSIAISLD_PORT5_MARK,
174 FSIASPDIF_PORT9_MARK, /* FSIASPDIF Port 9/18 */
175 FSIASPDIF_PORT18_MARK,
176 FSIAOSLD1_MARK, FSIAOSLD2_MARK, FSIAOLR_MARK,
177 FSIAOBT_MARK, FSIAOSLD_MARK, FSIAOMC_MARK,
178 FSIACK_MARK, FSIAILR_MARK, FSIAIBT_MARK,
179
180 /* FMSI */
181 FMSISLD_PORT1_MARK, /* FMSISLD Port 1/6 */
182 FMSISLD_PORT6_MARK,
183 FMSIILR_MARK, FMSIIBT_MARK, FMSIOLR_MARK, FMSIOBT_MARK,
184 FMSICK_MARK, FMSOILR_MARK, FMSOIBT_MARK, FMSOOLR_MARK,
185 FMSOOBT_MARK, FMSOSLD_MARK, FMSOCK_MARK,
186
187 /* SCIFA0 */
188 SCIFA0_SCK_MARK, SCIFA0_CTS_MARK, SCIFA0_RTS_MARK,
189 SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
190
191 /* SCIFA1 */
192 SCIFA1_CTS_MARK, SCIFA1_SCK_MARK, SCIFA1_RXD_MARK,
193 SCIFA1_TXD_MARK, SCIFA1_RTS_MARK,
194
195 /* SCIFA2 */
196 SCIFA2_SCK_PORT22_MARK, /* SCIFA2_SCK Port 22/199 */
197 SCIFA2_SCK_PORT199_MARK,
198 SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
199 SCIFA2_CTS_MARK, SCIFA2_RTS_MARK,
200
201 /* SCIFA3 */
202 SCIFA3_RTS_PORT105_MARK, /* MSEL5CR_8_0 */
203 SCIFA3_SCK_PORT116_MARK,
204 SCIFA3_CTS_PORT117_MARK,
205 SCIFA3_RXD_PORT174_MARK,
206 SCIFA3_TXD_PORT175_MARK,
207
208 SCIFA3_RTS_PORT161_MARK, /* MSEL5CR_8_1 */
209 SCIFA3_SCK_PORT158_MARK,
210 SCIFA3_CTS_PORT162_MARK,
211 SCIFA3_RXD_PORT159_MARK,
212 SCIFA3_TXD_PORT160_MARK,
213
214 /* SCIFA4 */
215 SCIFA4_RXD_PORT12_MARK, /* MSEL5CR[12:11] = 00 */
216 SCIFA4_TXD_PORT13_MARK,
217
218 SCIFA4_RXD_PORT204_MARK, /* MSEL5CR[12:11] = 01 */
219 SCIFA4_TXD_PORT203_MARK,
220
221 SCIFA4_RXD_PORT94_MARK, /* MSEL5CR[12:11] = 10 */
222 SCIFA4_TXD_PORT93_MARK,
223
224 SCIFA4_SCK_PORT21_MARK, /* SCIFA4_SCK Port 21/205 */
225 SCIFA4_SCK_PORT205_MARK,
226
227 /* SCIFA5 */
228 SCIFA5_TXD_PORT20_MARK, /* MSEL5CR[15:14] = 00 */
229 SCIFA5_RXD_PORT10_MARK,
230
231 SCIFA5_RXD_PORT207_MARK, /* MSEL5CR[15:14] = 01 */
232 SCIFA5_TXD_PORT208_MARK,
233
234 SCIFA5_TXD_PORT91_MARK, /* MSEL5CR[15:14] = 10 */
235 SCIFA5_RXD_PORT92_MARK,
236
237 SCIFA5_SCK_PORT23_MARK, /* SCIFA5_SCK Port 23/206 */
238 SCIFA5_SCK_PORT206_MARK,
239
240 /* SCIFA6 */
241 SCIFA6_SCK_MARK, SCIFA6_RXD_MARK, SCIFA6_TXD_MARK,
242
243 /* SCIFA7 */
244 SCIFA7_TXD_MARK, SCIFA7_RXD_MARK,
245
246 /* SCIFAB */
247 SCIFB_SCK_PORT190_MARK, /* MSEL5CR_17_0 */
248 SCIFB_RXD_PORT191_MARK,
249 SCIFB_TXD_PORT192_MARK,
250 SCIFB_RTS_PORT186_MARK,
251 SCIFB_CTS_PORT187_MARK,
252
253 SCIFB_SCK_PORT2_MARK, /* MSEL5CR_17_1 */
254 SCIFB_RXD_PORT3_MARK,
255 SCIFB_TXD_PORT4_MARK,
256 SCIFB_RTS_PORT172_MARK,
257 SCIFB_CTS_PORT173_MARK,
258
259 /* LCD0 */
260 LCDC0_SELECT_MARK,
261
262 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
263 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
264 LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
265 LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
266 LCD0_D16_MARK, LCD0_D17_MARK,
267 LCD0_DON_MARK, LCD0_VCPWC_MARK, LCD0_VEPWC_MARK,
268 LCD0_DCK_MARK, LCD0_VSYN_MARK, /* for RGB */
269 LCD0_HSYN_MARK, LCD0_DISP_MARK, /* for RGB */
270 LCD0_WR_MARK, LCD0_RD_MARK, /* for SYS */
271 LCD0_CS_MARK, LCD0_RS_MARK, /* for SYS */
272
273 LCD0_D21_PORT158_MARK, LCD0_D23_PORT159_MARK, /* MSEL5CR_6_1 */
274 LCD0_D22_PORT160_MARK, LCD0_D20_PORT161_MARK,
275 LCD0_D19_PORT162_MARK, LCD0_D18_PORT163_MARK,
276 LCD0_LCLK_PORT165_MARK,
277
278 LCD0_D18_PORT40_MARK, LCD0_D22_PORT0_MARK, /* MSEL5CR_6_0 */
279 LCD0_D23_PORT1_MARK, LCD0_D21_PORT2_MARK,
280 LCD0_D20_PORT3_MARK, LCD0_D19_PORT4_MARK,
281 LCD0_LCLK_PORT102_MARK,
282
283 /* LCD1 */
284 LCDC1_SELECT_MARK,
285
286 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
287 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
288 LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
289 LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
290 LCD1_D16_MARK, LCD1_D17_MARK, LCD1_D18_MARK, LCD1_D19_MARK,
291 LCD1_D20_MARK, LCD1_D21_MARK, LCD1_D22_MARK, LCD1_D23_MARK,
292 LCD1_DON_MARK, LCD1_VCPWC_MARK,
293 LCD1_LCLK_MARK, LCD1_VEPWC_MARK,
294
295 LCD1_DCK_MARK, LCD1_VSYN_MARK, /* for RGB */
296 LCD1_HSYN_MARK, LCD1_DISP_MARK, /* for RGB */
297 LCD1_RS_MARK, LCD1_CS_MARK, /* for SYS */
298 LCD1_RD_MARK, LCD1_WR_MARK, /* for SYS */
299
300 /* RSPI */
301 RSPI_SSL0_A_MARK, RSPI_SSL1_A_MARK, RSPI_SSL2_A_MARK,
302 RSPI_SSL3_A_MARK, RSPI_CK_A_MARK, RSPI_MOSI_A_MARK,
303 RSPI_MISO_A_MARK,
304
305 /* VIO CKO */
306 VIO_CKO1_MARK, /* needs fixup */
307 VIO_CKO2_MARK,
308 VIO_CKO_1_MARK,
309 VIO_CKO_MARK,
310
311 /* VIO0 */
312 VIO0_D0_MARK, VIO0_D1_MARK, VIO0_D2_MARK, VIO0_D3_MARK,
313 VIO0_D4_MARK, VIO0_D5_MARK, VIO0_D6_MARK, VIO0_D7_MARK,
314 VIO0_D8_MARK, VIO0_D9_MARK, VIO0_D10_MARK, VIO0_D11_MARK,
315 VIO0_D12_MARK, VIO0_VD_MARK, VIO0_HD_MARK, VIO0_CLK_MARK,
316 VIO0_FIELD_MARK,
317
318 VIO0_D13_PORT26_MARK, /* MSEL5CR_27_0 */
319 VIO0_D14_PORT25_MARK,
320 VIO0_D15_PORT24_MARK,
321
322 VIO0_D13_PORT22_MARK, /* MSEL5CR_27_1 */
323 VIO0_D14_PORT95_MARK,
324 VIO0_D15_PORT96_MARK,
325
326 /* VIO1 */
327 VIO1_D0_MARK, VIO1_D1_MARK, VIO1_D2_MARK, VIO1_D3_MARK,
328 VIO1_D4_MARK, VIO1_D5_MARK, VIO1_D6_MARK, VIO1_D7_MARK,
329 VIO1_VD_MARK, VIO1_HD_MARK, VIO1_CLK_MARK, VIO1_FIELD_MARK,
330
331 /* TPU0 */
332 TPU0TO0_MARK, TPU0TO1_MARK, TPU0TO3_MARK,
333 TPU0TO2_PORT66_MARK, /* TPU0TO2 Port 66/202 */
334 TPU0TO2_PORT202_MARK,
335
336 /* SSP1 0 */
337 STP0_IPD0_MARK, STP0_IPD1_MARK, STP0_IPD2_MARK, STP0_IPD3_MARK,
338 STP0_IPD4_MARK, STP0_IPD5_MARK, STP0_IPD6_MARK, STP0_IPD7_MARK,
339 STP0_IPEN_MARK, STP0_IPCLK_MARK, STP0_IPSYNC_MARK,
340
341 /* SSP1 1 */
342 STP1_IPD1_MARK, STP1_IPD2_MARK, STP1_IPD3_MARK, STP1_IPD4_MARK,
343 STP1_IPD5_MARK, STP1_IPD6_MARK, STP1_IPD7_MARK, STP1_IPCLK_MARK,
344 STP1_IPSYNC_MARK,
345
346 STP1_IPD0_PORT186_MARK, /* MSEL5CR_23_0 */
347 STP1_IPEN_PORT187_MARK,
348
349 STP1_IPD0_PORT194_MARK, /* MSEL5CR_23_1 */
350 STP1_IPEN_PORT193_MARK,
351
352 /* SIM */
353 SIM_RST_MARK, SIM_CLK_MARK,
354 SIM_D_PORT22_MARK, /* SIM_D Port 22/199 */
355 SIM_D_PORT199_MARK,
356
357 /* SDHI0 */
358 SDHI0_D0_MARK, SDHI0_D1_MARK, SDHI0_D2_MARK, SDHI0_D3_MARK,
359 SDHI0_CD_MARK, SDHI0_WP_MARK, SDHI0_CMD_MARK, SDHI0_CLK_MARK,
360
361 /* SDHI1 */
362 SDHI1_D0_MARK, SDHI1_D1_MARK, SDHI1_D2_MARK, SDHI1_D3_MARK,
363 SDHI1_CD_MARK, SDHI1_WP_MARK, SDHI1_CMD_MARK, SDHI1_CLK_MARK,
364
365 /* SDHI2 */
366 SDHI2_D0_MARK, SDHI2_D1_MARK, SDHI2_D2_MARK, SDHI2_D3_MARK,
367 SDHI2_CLK_MARK, SDHI2_CMD_MARK,
368
369 SDHI2_CD_PORT24_MARK, /* MSEL5CR_19_0 */
370 SDHI2_WP_PORT25_MARK,
371
372 SDHI2_WP_PORT177_MARK, /* MSEL5CR_19_1 */
373 SDHI2_CD_PORT202_MARK,
374
375 /* MSIOF2 */
376 MSIOF2_TXD_MARK, MSIOF2_RXD_MARK, MSIOF2_TSCK_MARK,
377 MSIOF2_SS2_MARK, MSIOF2_TSYNC_MARK, MSIOF2_SS1_MARK,
378 MSIOF2_MCK1_MARK, MSIOF2_MCK0_MARK, MSIOF2_RSYNC_MARK,
379 MSIOF2_RSCK_MARK,
380
381 /* KEYSC */
382 KEYIN4_MARK, KEYIN5_MARK, KEYIN6_MARK, KEYIN7_MARK,
383 KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK,
384 KEYOUT4_MARK, KEYOUT5_MARK, KEYOUT6_MARK, KEYOUT7_MARK,
385
386 KEYIN0_PORT43_MARK, /* MSEL4CR_18_0 */
387 KEYIN1_PORT44_MARK,
388 KEYIN2_PORT45_MARK,
389 KEYIN3_PORT46_MARK,
390
391 KEYIN0_PORT58_MARK, /* MSEL4CR_18_1 */
392 KEYIN1_PORT57_MARK,
393 KEYIN2_PORT56_MARK,
394 KEYIN3_PORT55_MARK,
395
396 /* VOU */
397 DV_D0_MARK, DV_D1_MARK, DV_D2_MARK, DV_D3_MARK,
398 DV_D4_MARK, DV_D5_MARK, DV_D6_MARK, DV_D7_MARK,
399 DV_D8_MARK, DV_D9_MARK, DV_D10_MARK, DV_D11_MARK,
400 DV_D12_MARK, DV_D13_MARK, DV_D14_MARK, DV_D15_MARK,
401 DV_CLK_MARK, DV_VSYNC_MARK, DV_HSYNC_MARK,
402
403 /* MEMC */
404 MEMC_AD0_MARK, MEMC_AD1_MARK, MEMC_AD2_MARK, MEMC_AD3_MARK,
405 MEMC_AD4_MARK, MEMC_AD5_MARK, MEMC_AD6_MARK, MEMC_AD7_MARK,
406 MEMC_AD8_MARK, MEMC_AD9_MARK, MEMC_AD10_MARK, MEMC_AD11_MARK,
407 MEMC_AD12_MARK, MEMC_AD13_MARK, MEMC_AD14_MARK, MEMC_AD15_MARK,
408 MEMC_CS0_MARK, MEMC_INT_MARK, MEMC_NWE_MARK, MEMC_NOE_MARK,
409
410 MEMC_CS1_MARK, /* MSEL4CR_6_0 */
411 MEMC_ADV_MARK,
412 MEMC_WAIT_MARK,
413 MEMC_BUSCLK_MARK,
414
415 MEMC_A1_MARK, /* MSEL4CR_6_1 */
416 MEMC_DREQ0_MARK,
417 MEMC_DREQ1_MARK,
418 MEMC_A0_MARK,
419
420 /* MMC */
421 MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK,
422 MMC0_D3_PORT71_MARK, MMC0_D4_PORT72_MARK, MMC0_D5_PORT73_MARK,
423 MMC0_D6_PORT74_MARK, MMC0_D7_PORT75_MARK, MMC0_CLK_PORT66_MARK,
424 MMC0_CMD_PORT67_MARK, /* MSEL4CR_15_0 */
425
426 MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK,
427 MMC1_D3_PORT146_MARK, MMC1_D4_PORT145_MARK, MMC1_D5_PORT144_MARK,
428 MMC1_D6_PORT143_MARK, MMC1_D7_PORT142_MARK, MMC1_CLK_PORT103_MARK,
429 MMC1_CMD_PORT104_MARK, /* MSEL4CR_15_1 */
430
431 /* MSIOF0 */
432 MSIOF0_SS1_MARK, MSIOF0_SS2_MARK, MSIOF0_RXD_MARK,
433 MSIOF0_TXD_MARK, MSIOF0_MCK0_MARK, MSIOF0_MCK1_MARK,
434 MSIOF0_RSYNC_MARK, MSIOF0_RSCK_MARK, MSIOF0_TSCK_MARK,
435 MSIOF0_TSYNC_MARK,
436
437 /* MSIOF1 */
438 MSIOF1_RSCK_MARK, MSIOF1_RSYNC_MARK,
439 MSIOF1_MCK0_MARK, MSIOF1_MCK1_MARK,
440
441 MSIOF1_SS2_PORT116_MARK, MSIOF1_SS1_PORT117_MARK,
442 MSIOF1_RXD_PORT118_MARK, MSIOF1_TXD_PORT119_MARK,
443 MSIOF1_TSYNC_PORT120_MARK,
444 MSIOF1_TSCK_PORT121_MARK, /* MSEL4CR_10_0 */
445
446 MSIOF1_SS1_PORT67_MARK, MSIOF1_TSCK_PORT72_MARK,
447 MSIOF1_TSYNC_PORT73_MARK, MSIOF1_TXD_PORT74_MARK,
448 MSIOF1_RXD_PORT75_MARK,
449 MSIOF1_SS2_PORT202_MARK, /* MSEL4CR_10_1 */
450
451 /* GPIO */
452 GPO0_MARK, GPI0_MARK, GPO1_MARK, GPI1_MARK,
453
454 /* USB0 */
455 USB0_OCI_MARK, USB0_PPON_MARK, VBUS_MARK,
456
457 /* USB1 */
458 USB1_OCI_MARK, USB1_PPON_MARK,
459
460 /* BBIF1 */
461 BBIF1_RXD_MARK, BBIF1_TXD_MARK, BBIF1_TSYNC_MARK,
462 BBIF1_TSCK_MARK, BBIF1_RSCK_MARK, BBIF1_RSYNC_MARK,
463 BBIF1_FLOW_MARK, BBIF1_RX_FLOW_N_MARK,
464
465 /* BBIF2 */
466 BBIF2_TXD2_PORT5_MARK, /* MSEL5CR_0_0 */
467 BBIF2_RXD2_PORT60_MARK,
468 BBIF2_TSYNC2_PORT6_MARK,
469 BBIF2_TSCK2_PORT59_MARK,
470
471 BBIF2_RXD2_PORT90_MARK, /* MSEL5CR_0_1 */
472 BBIF2_TXD2_PORT183_MARK,
473 BBIF2_TSCK2_PORT89_MARK,
474 BBIF2_TSYNC2_PORT184_MARK,
475
476 /* BSC / FLCTL / PCMCIA */
477 CS0_MARK, CS2_MARK, CS4_MARK,
478 CS5B_MARK, CS6A_MARK,
479 CS5A_PORT105_MARK, /* CS5A PORT 19/105 */
480 CS5A_PORT19_MARK,
481 IOIS16_MARK, /* ? */
482
483 A0_MARK, A1_MARK, A2_MARK, A3_MARK,
484 A4_FOE_MARK, /* share with FLCTL */
485 A5_FCDE_MARK, /* share with FLCTL */
486 A6_MARK, A7_MARK, A8_MARK, A9_MARK,
487 A10_MARK, A11_MARK, A12_MARK, A13_MARK,
488 A14_MARK, A15_MARK, A16_MARK, A17_MARK,
489 A18_MARK, A19_MARK, A20_MARK, A21_MARK,
490 A22_MARK, A23_MARK, A24_MARK, A25_MARK,
491 A26_MARK,
492
493 D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, /* share with FLCTL */
494 D3_NAF3_MARK, D4_NAF4_MARK, D5_NAF5_MARK, /* share with FLCTL */
495 D6_NAF6_MARK, D7_NAF7_MARK, D8_NAF8_MARK, /* share with FLCTL */
496 D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK, /* share with FLCTL */
497 D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, /* share with FLCTL */
498 D15_NAF15_MARK, /* share with FLCTL */
499 D16_MARK, D17_MARK, D18_MARK, D19_MARK,
500 D20_MARK, D21_MARK, D22_MARK, D23_MARK,
501 D24_MARK, D25_MARK, D26_MARK, D27_MARK,
502 D28_MARK, D29_MARK, D30_MARK, D31_MARK,
503
504 WE0_FWE_MARK, /* share with FLCTL */
505 WE1_MARK,
506 WE2_ICIORD_MARK, /* share with PCMCIA */
507 WE3_ICIOWR_MARK, /* share with PCMCIA */
508 CKO_MARK, BS_MARK, RDWR_MARK,
509 RD_FSC_MARK, /* share with FLCTL */
510 WAIT_PORT177_MARK, /* WAIT Port 90/177 */
511 WAIT_PORT90_MARK,
512
513 FCE0_MARK, FCE1_MARK, FRB_MARK, /* FLCTL */
514
515 /* IRDA */
516 IRDA_FIRSEL_MARK, IRDA_IN_MARK, IRDA_OUT_MARK,
517
518 /* ATAPI */
519 IDE_D0_MARK, IDE_D1_MARK, IDE_D2_MARK, IDE_D3_MARK,
520 IDE_D4_MARK, IDE_D5_MARK, IDE_D6_MARK, IDE_D7_MARK,
521 IDE_D8_MARK, IDE_D9_MARK, IDE_D10_MARK, IDE_D11_MARK,
522 IDE_D12_MARK, IDE_D13_MARK, IDE_D14_MARK, IDE_D15_MARK,
523 IDE_A0_MARK, IDE_A1_MARK, IDE_A2_MARK, IDE_CS0_MARK,
524 IDE_CS1_MARK, IDE_IOWR_MARK, IDE_IORD_MARK, IDE_IORDY_MARK,
525 IDE_INT_MARK, IDE_RST_MARK, IDE_DIRECTION_MARK,
526 IDE_EXBUF_ENB_MARK, IDE_IODACK_MARK, IDE_IODREQ_MARK,
527
528 /* RMII */
529 RMII_CRS_DV_MARK, RMII_RX_ER_MARK, RMII_RXD0_MARK,
530 RMII_RXD1_MARK, RMII_TX_EN_MARK, RMII_TXD0_MARK,
531 RMII_MDC_MARK, RMII_TXD1_MARK, RMII_MDIO_MARK,
532 RMII_REF50CK_MARK, /* for RMII */
533 RMII_REF125CK_MARK, /* for GMII */
534
535 /* GEther */
536 ET_TX_CLK_MARK, ET_TX_EN_MARK, ET_ETXD0_MARK, ET_ETXD1_MARK,
537 ET_ETXD2_MARK, ET_ETXD3_MARK,
538 ET_ETXD4_MARK, ET_ETXD5_MARK, /* for GEther */
539 ET_ETXD6_MARK, ET_ETXD7_MARK, /* for GEther */
540 ET_COL_MARK, ET_TX_ER_MARK, ET_RX_CLK_MARK, ET_RX_DV_MARK,
541 ET_ERXD0_MARK, ET_ERXD1_MARK, ET_ERXD2_MARK, ET_ERXD3_MARK,
542 ET_ERXD4_MARK, ET_ERXD5_MARK, /* for GEther */
543 ET_ERXD6_MARK, ET_ERXD7_MARK, /* for GEther */
544 ET_RX_ER_MARK, ET_CRS_MARK, ET_MDC_MARK, ET_MDIO_MARK,
545 ET_LINK_MARK, ET_PHY_INT_MARK, ET_WOL_MARK, ET_GTX_CLK_MARK,
546
547 /* DMA0 */
548 DREQ0_MARK, DACK0_MARK,
549
550 /* DMA1 */
551 DREQ1_MARK, DACK1_MARK,
552
553 /* SYSC */
554 RESETOUTS_MARK, RESETP_PULLUP_MARK, RESETP_PLAIN_MARK,
555
556 /* IRREM */
557 IROUT_MARK,
558
559 /* SDENC */
560 SDENC_CPG_MARK, SDENC_DV_CLKI_MARK,
561
562 /* DEBUG */
563 EDEBGREQ_PULLUP_MARK, /* for JTAG */
564 EDEBGREQ_PULLDOWN_MARK,
565
566 TRACEAUD_FROM_VIO_MARK, /* for TRACE/AUD */
567 TRACEAUD_FROM_LCDC0_MARK,
568 TRACEAUD_FROM_MEMC_MARK,
569
570 PINMUX_MARK_END,
571};
572
573static pinmux_enum_t pinmux_data[] = {
574 /* specify valid pin states for each pin in GPIO mode */
575
576 /* I/O and Pull U/D */
577 PORT_DATA_IO_PD(0), PORT_DATA_IO_PD(1),
578 PORT_DATA_IO_PD(2), PORT_DATA_IO_PD(3),
579 PORT_DATA_IO_PD(4), PORT_DATA_IO_PD(5),
580 PORT_DATA_IO_PD(6), PORT_DATA_IO(7),
581 PORT_DATA_IO(8), PORT_DATA_IO(9),
582
583 PORT_DATA_IO_PD(10), PORT_DATA_IO_PD(11),
584 PORT_DATA_IO_PD(12), PORT_DATA_IO_PU_PD(13),
585 PORT_DATA_IO_PD(14), PORT_DATA_IO_PD(15),
586 PORT_DATA_IO_PD(16), PORT_DATA_IO_PD(17),
587 PORT_DATA_IO(18), PORT_DATA_IO_PU(19),
588
589 PORT_DATA_IO_PU_PD(20), PORT_DATA_IO_PD(21),
590 PORT_DATA_IO_PU_PD(22), PORT_DATA_IO(23),
591 PORT_DATA_IO_PU(24), PORT_DATA_IO_PU(25),
592 PORT_DATA_IO_PU(26), PORT_DATA_IO_PU(27),
593 PORT_DATA_IO_PU(28), PORT_DATA_IO_PU(29),
594
595 PORT_DATA_IO_PU(30), PORT_DATA_IO_PD(31),
596 PORT_DATA_IO_PD(32), PORT_DATA_IO_PD(33),
597 PORT_DATA_IO_PD(34), PORT_DATA_IO_PU(35),
598 PORT_DATA_IO_PU(36), PORT_DATA_IO_PD(37),
599 PORT_DATA_IO_PU(38), PORT_DATA_IO_PD(39),
600
601 PORT_DATA_IO_PU_PD(40), PORT_DATA_IO_PD(41),
602 PORT_DATA_IO_PD(42), PORT_DATA_IO_PU_PD(43),
603 PORT_DATA_IO_PU_PD(44), PORT_DATA_IO_PU_PD(45),
604 PORT_DATA_IO_PU_PD(46), PORT_DATA_IO_PU_PD(47),
605 PORT_DATA_IO_PU_PD(48), PORT_DATA_IO_PU_PD(49),
606
607 PORT_DATA_IO_PU_PD(50), PORT_DATA_IO_PD(51),
608 PORT_DATA_IO_PD(52), PORT_DATA_IO_PD(53),
609 PORT_DATA_IO_PD(54), PORT_DATA_IO_PU_PD(55),
610 PORT_DATA_IO_PU_PD(56), PORT_DATA_IO_PU_PD(57),
611 PORT_DATA_IO_PU_PD(58), PORT_DATA_IO_PU_PD(59),
612
613 PORT_DATA_IO_PU_PD(60), PORT_DATA_IO_PD(61),
614 PORT_DATA_IO_PD(62), PORT_DATA_IO_PD(63),
615 PORT_DATA_IO_PD(64), PORT_DATA_IO_PD(65),
616 PORT_DATA_IO_PU_PD(66), PORT_DATA_IO_PU_PD(67),
617 PORT_DATA_IO_PU_PD(68), PORT_DATA_IO_PU_PD(69),
618
619 PORT_DATA_IO_PU_PD(70), PORT_DATA_IO_PU_PD(71),
620 PORT_DATA_IO_PU_PD(72), PORT_DATA_IO_PU_PD(73),
621 PORT_DATA_IO_PU_PD(74), PORT_DATA_IO_PU_PD(75),
622 PORT_DATA_IO_PU_PD(76), PORT_DATA_IO_PU_PD(77),
623 PORT_DATA_IO_PU_PD(78), PORT_DATA_IO_PU_PD(79),
624
625 PORT_DATA_IO_PU_PD(80), PORT_DATA_IO_PU_PD(81),
626 PORT_DATA_IO(82), PORT_DATA_IO_PU_PD(83),
627 PORT_DATA_IO(84), PORT_DATA_IO_PD(85),
628 PORT_DATA_IO_PD(86), PORT_DATA_IO_PD(87),
629 PORT_DATA_IO_PD(88), PORT_DATA_IO_PD(89),
630
631 PORT_DATA_IO_PD(90), PORT_DATA_IO_PU_PD(91),
632 PORT_DATA_IO_PU_PD(92), PORT_DATA_IO_PU_PD(93),
633 PORT_DATA_IO_PU_PD(94), PORT_DATA_IO_PU_PD(95),
634 PORT_DATA_IO_PU_PD(96), PORT_DATA_IO_PU_PD(97),
635 PORT_DATA_IO_PU_PD(98), PORT_DATA_IO_PU_PD(99),
636
637 PORT_DATA_IO_PU_PD(100), PORT_DATA_IO(101),
638 PORT_DATA_IO_PU(102), PORT_DATA_IO_PU_PD(103),
639 PORT_DATA_IO_PU(104), PORT_DATA_IO_PU(105),
640 PORT_DATA_IO_PU_PD(106), PORT_DATA_IO(107),
641 PORT_DATA_IO(108), PORT_DATA_IO(109),
642
643 PORT_DATA_IO(110), PORT_DATA_IO(111),
644 PORT_DATA_IO(112), PORT_DATA_IO(113),
645 PORT_DATA_IO_PU_PD(114), PORT_DATA_IO(115),
646 PORT_DATA_IO_PD(116), PORT_DATA_IO_PD(117),
647 PORT_DATA_IO_PD(118), PORT_DATA_IO_PD(119),
648
649 PORT_DATA_IO_PD(120), PORT_DATA_IO_PD(121),
650 PORT_DATA_IO_PD(122), PORT_DATA_IO_PD(123),
651 PORT_DATA_IO_PD(124), PORT_DATA_IO(125),
652 PORT_DATA_IO(126), PORT_DATA_IO(127),
653 PORT_DATA_IO(128), PORT_DATA_IO(129),
654
655 PORT_DATA_IO(130), PORT_DATA_IO(131),
656 PORT_DATA_IO(132), PORT_DATA_IO(133),
657 PORT_DATA_IO(134), PORT_DATA_IO(135),
658 PORT_DATA_IO(136), PORT_DATA_IO(137),
659 PORT_DATA_IO(138), PORT_DATA_IO(139),
660
661 PORT_DATA_IO(140), PORT_DATA_IO(141),
662 PORT_DATA_IO_PU(142), PORT_DATA_IO_PU(143),
663 PORT_DATA_IO_PU(144), PORT_DATA_IO_PU(145),
664 PORT_DATA_IO_PU(146), PORT_DATA_IO_PU(147),
665 PORT_DATA_IO_PU(148), PORT_DATA_IO_PU(149),
666
667 PORT_DATA_IO_PU(150), PORT_DATA_IO_PU(151),
668 PORT_DATA_IO_PU(152), PORT_DATA_IO_PU(153),
669 PORT_DATA_IO_PU(154), PORT_DATA_IO_PU(155),
670 PORT_DATA_IO_PU(156), PORT_DATA_IO_PU(157),
671 PORT_DATA_IO_PD(158), PORT_DATA_IO_PD(159),
672
673 PORT_DATA_IO_PU_PD(160), PORT_DATA_IO_PD(161),
674 PORT_DATA_IO_PD(162), PORT_DATA_IO_PD(163),
675 PORT_DATA_IO_PD(164), PORT_DATA_IO_PD(165),
676 PORT_DATA_IO_PU(166), PORT_DATA_IO_PU(167),
677 PORT_DATA_IO_PU(168), PORT_DATA_IO_PU(169),
678
679 PORT_DATA_IO_PU(170), PORT_DATA_IO_PU(171),
680 PORT_DATA_IO_PD(172), PORT_DATA_IO_PD(173),
681 PORT_DATA_IO_PD(174), PORT_DATA_IO_PD(175),
682 PORT_DATA_IO_PU(176), PORT_DATA_IO_PU_PD(177),
683 PORT_DATA_IO_PU(178), PORT_DATA_IO_PD(179),
684
685 PORT_DATA_IO_PD(180), PORT_DATA_IO_PU(181),
686 PORT_DATA_IO_PU(182), PORT_DATA_IO(183),
687 PORT_DATA_IO_PD(184), PORT_DATA_IO_PD(185),
688 PORT_DATA_IO_PD(186), PORT_DATA_IO_PD(187),
689 PORT_DATA_IO_PD(188), PORT_DATA_IO_PD(189),
690
691 PORT_DATA_IO_PD(190), PORT_DATA_IO_PD(191),
692 PORT_DATA_IO_PD(192), PORT_DATA_IO_PU_PD(193),
693 PORT_DATA_IO_PU_PD(194), PORT_DATA_IO_PD(195),
694 PORT_DATA_IO_PU_PD(196), PORT_DATA_IO_PD(197),
695 PORT_DATA_IO_PU_PD(198), PORT_DATA_IO_PU_PD(199),
696
697 PORT_DATA_IO_PU_PD(200), PORT_DATA_IO_PU(201),
698 PORT_DATA_IO_PU_PD(202), PORT_DATA_IO(203),
699 PORT_DATA_IO_PU_PD(204), PORT_DATA_IO_PU_PD(205),
700 PORT_DATA_IO_PU_PD(206), PORT_DATA_IO_PU_PD(207),
701 PORT_DATA_IO_PU_PD(208), PORT_DATA_IO_PD(209),
702
703 PORT_DATA_IO_PD(210), PORT_DATA_IO_PD(211),
704
705 /* Port0 */
706 PINMUX_DATA(DBGMDT2_MARK, PORT0_FN1),
707 PINMUX_DATA(FSIAISLD_PORT0_MARK, PORT0_FN2, MSEL5CR_3_0),
708 PINMUX_DATA(FSIAOSLD1_MARK, PORT0_FN3),
709 PINMUX_DATA(LCD0_D22_PORT0_MARK, PORT0_FN4, MSEL5CR_6_0),
710 PINMUX_DATA(SCIFA7_RXD_MARK, PORT0_FN6),
711 PINMUX_DATA(LCD1_D4_MARK, PORT0_FN7),
712 PINMUX_DATA(IRQ5_PORT0_MARK, PORT0_FN0, MSEL1CR_5_0),
713
714 /* Port1 */
715 PINMUX_DATA(DBGMDT1_MARK, PORT1_FN1),
716 PINMUX_DATA(FMSISLD_PORT1_MARK, PORT1_FN2, MSEL5CR_5_0),
717 PINMUX_DATA(FSIAOSLD2_MARK, PORT1_FN3),
718 PINMUX_DATA(LCD0_D23_PORT1_MARK, PORT1_FN4, MSEL5CR_6_0),
719 PINMUX_DATA(SCIFA7_TXD_MARK, PORT1_FN6),
720 PINMUX_DATA(LCD1_D3_MARK, PORT1_FN7),
721 PINMUX_DATA(IRQ5_PORT1_MARK, PORT1_FN0, MSEL1CR_5_1),
722
723 /* Port2 */
724 PINMUX_DATA(DBGMDT0_MARK, PORT2_FN1),
725 PINMUX_DATA(SCIFB_SCK_PORT2_MARK, PORT2_FN2, MSEL5CR_17_1),
726 PINMUX_DATA(LCD0_D21_PORT2_MARK, PORT2_FN4, MSEL5CR_6_0),
727 PINMUX_DATA(LCD1_D2_MARK, PORT2_FN7),
728 PINMUX_DATA(IRQ0_PORT2_MARK, PORT2_FN0, MSEL1CR_0_1),
729
730 /* Port3 */
731 PINMUX_DATA(DBGMD21_MARK, PORT3_FN1),
732 PINMUX_DATA(SCIFB_RXD_PORT3_MARK, PORT3_FN2, MSEL5CR_17_1),
733 PINMUX_DATA(LCD0_D20_PORT3_MARK, PORT3_FN4, MSEL5CR_6_0),
734 PINMUX_DATA(LCD1_D1_MARK, PORT3_FN7),
735
736 /* Port4 */
737 PINMUX_DATA(DBGMD20_MARK, PORT4_FN1),
738 PINMUX_DATA(SCIFB_TXD_PORT4_MARK, PORT4_FN2, MSEL5CR_17_1),
739 PINMUX_DATA(LCD0_D19_PORT4_MARK, PORT4_FN4, MSEL5CR_6_0),
740 PINMUX_DATA(LCD1_D0_MARK, PORT4_FN7),
741
742 /* Port5 */
743 PINMUX_DATA(DBGMD11_MARK, PORT5_FN1),
744 PINMUX_DATA(BBIF2_TXD2_PORT5_MARK, PORT5_FN2, MSEL5CR_0_0),
745 PINMUX_DATA(FSIAISLD_PORT5_MARK, PORT5_FN4, MSEL5CR_3_1),
746 PINMUX_DATA(RSPI_SSL0_A_MARK, PORT5_FN6),
747 PINMUX_DATA(LCD1_VCPWC_MARK, PORT5_FN7),
748
749 /* Port6 */
750 PINMUX_DATA(DBGMD10_MARK, PORT6_FN1),
751 PINMUX_DATA(BBIF2_TSYNC2_PORT6_MARK, PORT6_FN2, MSEL5CR_0_0),
752 PINMUX_DATA(FMSISLD_PORT6_MARK, PORT6_FN4, MSEL5CR_5_1),
753 PINMUX_DATA(RSPI_SSL1_A_MARK, PORT6_FN6),
754 PINMUX_DATA(LCD1_VEPWC_MARK, PORT6_FN7),
755
756 /* Port7 */
757 PINMUX_DATA(FSIAOLR_MARK, PORT7_FN1),
758
759 /* Port8 */
760 PINMUX_DATA(FSIAOBT_MARK, PORT8_FN1),
761
762 /* Port9 */
763 PINMUX_DATA(FSIAOSLD_MARK, PORT9_FN1),
764 PINMUX_DATA(FSIASPDIF_PORT9_MARK, PORT9_FN2, MSEL5CR_4_0),
765
766 /* Port10 */
767 PINMUX_DATA(FSIAOMC_MARK, PORT10_FN1),
768 PINMUX_DATA(SCIFA5_RXD_PORT10_MARK, PORT10_FN3, MSEL5CR_14_0, MSEL5CR_15_0),
769 PINMUX_DATA(IRQ3_PORT10_MARK, PORT10_FN0, MSEL1CR_3_0),
770
771 /* Port11 */
772 PINMUX_DATA(FSIACK_MARK, PORT11_FN1),
773 PINMUX_DATA(IRQ2_PORT11_MARK, PORT11_FN0, MSEL1CR_2_0),
774
775 /* Port12 */
776 PINMUX_DATA(FSIAILR_MARK, PORT12_FN1),
777 PINMUX_DATA(SCIFA4_RXD_PORT12_MARK, PORT12_FN2, MSEL5CR_12_0, MSEL5CR_11_0),
778 PINMUX_DATA(LCD1_RS_MARK, PORT12_FN6),
779 PINMUX_DATA(LCD1_DISP_MARK, PORT12_FN7),
780 PINMUX_DATA(IRQ2_PORT12_MARK, PORT12_FN0, MSEL1CR_2_1),
781
782 /* Port13 */
783 PINMUX_DATA(FSIAIBT_MARK, PORT13_FN1),
784 PINMUX_DATA(SCIFA4_TXD_PORT13_MARK, PORT13_FN2, MSEL5CR_12_0, MSEL5CR_11_0),
785 PINMUX_DATA(LCD1_RD_MARK, PORT13_FN7),
786 PINMUX_DATA(IRQ0_PORT13_MARK, PORT13_FN0, MSEL1CR_0_0),
787
788 /* Port14 */
789 PINMUX_DATA(FMSOILR_MARK, PORT14_FN1),
790 PINMUX_DATA(FMSIILR_MARK, PORT14_FN2),
791 PINMUX_DATA(VIO_CKO1_MARK, PORT14_FN3),
792 PINMUX_DATA(LCD1_D23_MARK, PORT14_FN7),
793 PINMUX_DATA(IRQ3_PORT14_MARK, PORT14_FN0, MSEL1CR_3_1),
794
795 /* Port15 */
796 PINMUX_DATA(FMSOIBT_MARK, PORT15_FN1),
797 PINMUX_DATA(FMSIIBT_MARK, PORT15_FN2),
798 PINMUX_DATA(VIO_CKO2_MARK, PORT15_FN3),
799 PINMUX_DATA(LCD1_D22_MARK, PORT15_FN7),
800 PINMUX_DATA(IRQ4_PORT15_MARK, PORT15_FN0, MSEL1CR_4_0),
801
802 /* Port16 */
803 PINMUX_DATA(FMSOOLR_MARK, PORT16_FN1),
804 PINMUX_DATA(FMSIOLR_MARK, PORT16_FN2),
805
806 /* Port17 */
807 PINMUX_DATA(FMSOOBT_MARK, PORT17_FN1),
808 PINMUX_DATA(FMSIOBT_MARK, PORT17_FN2),
809
810 /* Port18 */
811 PINMUX_DATA(FMSOSLD_MARK, PORT18_FN1),
812 PINMUX_DATA(FSIASPDIF_PORT18_MARK, PORT18_FN2, MSEL5CR_4_1),
813
814 /* Port19 */
815 PINMUX_DATA(FMSICK_MARK, PORT19_FN1),
816 PINMUX_DATA(CS5A_PORT19_MARK, PORT19_FN7, MSEL5CR_2_1),
817 PINMUX_DATA(IRQ10_MARK, PORT19_FN0),
818
819 /* Port20 */
820 PINMUX_DATA(FMSOCK_MARK, PORT20_FN1),
821 PINMUX_DATA(SCIFA5_TXD_PORT20_MARK, PORT20_FN3, MSEL5CR_15_0, MSEL5CR_14_0),
822 PINMUX_DATA(IRQ1_MARK, PORT20_FN0),
823
824 /* Port21 */
825 PINMUX_DATA(SCIFA1_CTS_MARK, PORT21_FN1),
826 PINMUX_DATA(SCIFA4_SCK_PORT21_MARK, PORT21_FN2, MSEL5CR_10_0),
827 PINMUX_DATA(TPU0TO1_MARK, PORT21_FN4),
828 PINMUX_DATA(VIO1_FIELD_MARK, PORT21_FN5),
829 PINMUX_DATA(STP0_IPD5_MARK, PORT21_FN6),
830 PINMUX_DATA(LCD1_D10_MARK, PORT21_FN7),
831
832 /* Port22 */
833 PINMUX_DATA(SCIFA2_SCK_PORT22_MARK, PORT22_FN1, MSEL5CR_7_0),
834 PINMUX_DATA(SIM_D_PORT22_MARK, PORT22_FN4, MSEL5CR_21_0),
835 PINMUX_DATA(VIO0_D13_PORT22_MARK, PORT22_FN7, MSEL5CR_27_1),
836
837 /* Port23 */
838 PINMUX_DATA(SCIFA1_RTS_MARK, PORT23_FN1),
839 PINMUX_DATA(SCIFA5_SCK_PORT23_MARK, PORT23_FN3, MSEL5CR_13_0),
840 PINMUX_DATA(TPU0TO0_MARK, PORT23_FN4),
841 PINMUX_DATA(VIO_CKO_1_MARK, PORT23_FN5),
842 PINMUX_DATA(STP0_IPD2_MARK, PORT23_FN6),
843 PINMUX_DATA(LCD1_D7_MARK, PORT23_FN7),
844
845 /* Port24 */
846 PINMUX_DATA(VIO0_D15_PORT24_MARK, PORT24_FN1, MSEL5CR_27_0),
847 PINMUX_DATA(VIO1_D7_MARK, PORT24_FN5),
848 PINMUX_DATA(SCIFA6_SCK_MARK, PORT24_FN6),
849 PINMUX_DATA(SDHI2_CD_PORT24_MARK, PORT24_FN7, MSEL5CR_19_0),
850
851 /* Port25 */
852 PINMUX_DATA(VIO0_D14_PORT25_MARK, PORT25_FN1, MSEL5CR_27_0),
853 PINMUX_DATA(VIO1_D6_MARK, PORT25_FN5),
854 PINMUX_DATA(SCIFA6_RXD_MARK, PORT25_FN6),
855 PINMUX_DATA(SDHI2_WP_PORT25_MARK, PORT25_FN7, MSEL5CR_19_0),
856
857 /* Port26 */
858 PINMUX_DATA(VIO0_D13_PORT26_MARK, PORT26_FN1, MSEL5CR_27_0),
859 PINMUX_DATA(VIO1_D5_MARK, PORT26_FN5),
860 PINMUX_DATA(SCIFA6_TXD_MARK, PORT26_FN6),
861
862 /* Port27 - Port39 Function */
863 PINMUX_DATA(VIO0_D7_MARK, PORT27_FN1),
864 PINMUX_DATA(VIO0_D6_MARK, PORT28_FN1),
865 PINMUX_DATA(VIO0_D5_MARK, PORT29_FN1),
866 PINMUX_DATA(VIO0_D4_MARK, PORT30_FN1),
867 PINMUX_DATA(VIO0_D3_MARK, PORT31_FN1),
868 PINMUX_DATA(VIO0_D2_MARK, PORT32_FN1),
869 PINMUX_DATA(VIO0_D1_MARK, PORT33_FN1),
870 PINMUX_DATA(VIO0_D0_MARK, PORT34_FN1),
871 PINMUX_DATA(VIO0_CLK_MARK, PORT35_FN1),
872 PINMUX_DATA(VIO_CKO_MARK, PORT36_FN1),
873 PINMUX_DATA(VIO0_HD_MARK, PORT37_FN1),
874 PINMUX_DATA(VIO0_FIELD_MARK, PORT38_FN1),
875 PINMUX_DATA(VIO0_VD_MARK, PORT39_FN1),
876
877 /* Port38 IRQ */
878 PINMUX_DATA(IRQ25_MARK, PORT38_FN0),
879
880 /* Port40 */
881 PINMUX_DATA(LCD0_D18_PORT40_MARK, PORT40_FN4, MSEL5CR_6_0),
882 PINMUX_DATA(RSPI_CK_A_MARK, PORT40_FN6),
883 PINMUX_DATA(LCD1_LCLK_MARK, PORT40_FN7),
884
885 /* Port41 */
886 PINMUX_DATA(LCD0_D17_MARK, PORT41_FN1),
887 PINMUX_DATA(MSIOF2_SS1_MARK, PORT41_FN2),
888 PINMUX_DATA(IRQ31_PORT41_MARK, PORT41_FN0, MSEL1CR_31_1),
889
890 /* Port42 */
891 PINMUX_DATA(LCD0_D16_MARK, PORT42_FN1),
892 PINMUX_DATA(MSIOF2_MCK1_MARK, PORT42_FN2),
893 PINMUX_DATA(IRQ12_PORT42_MARK, PORT42_FN0, MSEL1CR_12_1),
894
895 /* Port43 */
896 PINMUX_DATA(LCD0_D15_MARK, PORT43_FN1),
897 PINMUX_DATA(MSIOF2_MCK0_MARK, PORT43_FN2),
898 PINMUX_DATA(KEYIN0_PORT43_MARK, PORT43_FN3, MSEL4CR_18_0),
899 PINMUX_DATA(DV_D15_MARK, PORT43_FN6),
900
901 /* Port44 */
902 PINMUX_DATA(LCD0_D14_MARK, PORT44_FN1),
903 PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT44_FN2),
904 PINMUX_DATA(KEYIN1_PORT44_MARK, PORT44_FN3, MSEL4CR_18_0),
905 PINMUX_DATA(DV_D14_MARK, PORT44_FN6),
906
907 /* Port45 */
908 PINMUX_DATA(LCD0_D13_MARK, PORT45_FN1),
909 PINMUX_DATA(MSIOF2_RSCK_MARK, PORT45_FN2),
910 PINMUX_DATA(KEYIN2_PORT45_MARK, PORT45_FN3, MSEL4CR_18_0),
911 PINMUX_DATA(DV_D13_MARK, PORT45_FN6),
912
913 /* Port46 */
914 PINMUX_DATA(LCD0_D12_MARK, PORT46_FN1),
915 PINMUX_DATA(KEYIN3_PORT46_MARK, PORT46_FN3, MSEL4CR_18_0),
916 PINMUX_DATA(DV_D12_MARK, PORT46_FN6),
917
918 /* Port47 */
919 PINMUX_DATA(LCD0_D11_MARK, PORT47_FN1),
920 PINMUX_DATA(KEYIN4_MARK, PORT47_FN3),
921 PINMUX_DATA(DV_D11_MARK, PORT47_FN6),
922
923 /* Port48 */
924 PINMUX_DATA(LCD0_D10_MARK, PORT48_FN1),
925 PINMUX_DATA(KEYIN5_MARK, PORT48_FN3),
926 PINMUX_DATA(DV_D10_MARK, PORT48_FN6),
927
928 /* Port49 */
929 PINMUX_DATA(LCD0_D9_MARK, PORT49_FN1),
930 PINMUX_DATA(KEYIN6_MARK, PORT49_FN3),
931 PINMUX_DATA(DV_D9_MARK, PORT49_FN6),
932 PINMUX_DATA(IRQ30_PORT49_MARK, PORT49_FN0, MSEL1CR_30_1),
933
934 /* Port50 */
935 PINMUX_DATA(LCD0_D8_MARK, PORT50_FN1),
936 PINMUX_DATA(KEYIN7_MARK, PORT50_FN3),
937 PINMUX_DATA(DV_D8_MARK, PORT50_FN6),
938 PINMUX_DATA(IRQ29_PORT50_MARK, PORT50_FN0, MSEL1CR_29_1),
939
940 /* Port51 */
941 PINMUX_DATA(LCD0_D7_MARK, PORT51_FN1),
942 PINMUX_DATA(KEYOUT0_MARK, PORT51_FN3),
943 PINMUX_DATA(DV_D7_MARK, PORT51_FN6),
944
945 /* Port52 */
946 PINMUX_DATA(LCD0_D6_MARK, PORT52_FN1),
947 PINMUX_DATA(KEYOUT1_MARK, PORT52_FN3),
948 PINMUX_DATA(DV_D6_MARK, PORT52_FN6),
949
950 /* Port53 */
951 PINMUX_DATA(LCD0_D5_MARK, PORT53_FN1),
952 PINMUX_DATA(KEYOUT2_MARK, PORT53_FN3),
953 PINMUX_DATA(DV_D5_MARK, PORT53_FN6),
954
955 /* Port54 */
956 PINMUX_DATA(LCD0_D4_MARK, PORT54_FN1),
957 PINMUX_DATA(KEYOUT3_MARK, PORT54_FN3),
958 PINMUX_DATA(DV_D4_MARK, PORT54_FN6),
959
960 /* Port55 */
961 PINMUX_DATA(LCD0_D3_MARK, PORT55_FN1),
962 PINMUX_DATA(KEYOUT4_MARK, PORT55_FN3),
963 PINMUX_DATA(KEYIN3_PORT55_MARK, PORT55_FN4, MSEL4CR_18_1),
964 PINMUX_DATA(DV_D3_MARK, PORT55_FN6),
965
966 /* Port56 */
967 PINMUX_DATA(LCD0_D2_MARK, PORT56_FN1),
968 PINMUX_DATA(KEYOUT5_MARK, PORT56_FN3),
969 PINMUX_DATA(KEYIN2_PORT56_MARK, PORT56_FN4, MSEL4CR_18_1),
970 PINMUX_DATA(DV_D2_MARK, PORT56_FN6),
971 PINMUX_DATA(IRQ28_PORT56_MARK, PORT56_FN0, MSEL1CR_28_1),
972
973 /* Port57 */
974 PINMUX_DATA(LCD0_D1_MARK, PORT57_FN1),
975 PINMUX_DATA(KEYOUT6_MARK, PORT57_FN3),
976 PINMUX_DATA(KEYIN1_PORT57_MARK, PORT57_FN4, MSEL4CR_18_1),
977 PINMUX_DATA(DV_D1_MARK, PORT57_FN6),
978 PINMUX_DATA(IRQ27_PORT57_MARK, PORT57_FN0, MSEL1CR_27_1),
979
980 /* Port58 */
981 PINMUX_DATA(LCD0_D0_MARK, PORT58_FN1),
982 PINMUX_DATA(KEYOUT7_MARK, PORT58_FN3),
983 PINMUX_DATA(KEYIN0_PORT58_MARK, PORT58_FN4, MSEL4CR_18_1),
984 PINMUX_DATA(DV_D0_MARK, PORT58_FN6),
985 PINMUX_DATA(IRQ26_PORT58_MARK, PORT58_FN0, MSEL1CR_26_1),
986
987 /* Port59 */
988 PINMUX_DATA(LCD0_VCPWC_MARK, PORT59_FN1),
989 PINMUX_DATA(BBIF2_TSCK2_PORT59_MARK, PORT59_FN2, MSEL5CR_0_0),
990 PINMUX_DATA(RSPI_MOSI_A_MARK, PORT59_FN6),
991
992 /* Port60 */
993 PINMUX_DATA(LCD0_VEPWC_MARK, PORT60_FN1),
994 PINMUX_DATA(BBIF2_RXD2_PORT60_MARK, PORT60_FN2, MSEL5CR_0_0),
995 PINMUX_DATA(RSPI_MISO_A_MARK, PORT60_FN6),
996
997 /* Port61 */
998 PINMUX_DATA(LCD0_DON_MARK, PORT61_FN1),
999 PINMUX_DATA(MSIOF2_TXD_MARK, PORT61_FN2),
1000
1001 /* Port62 */
1002 PINMUX_DATA(LCD0_DCK_MARK, PORT62_FN1),
1003 PINMUX_DATA(LCD0_WR_MARK, PORT62_FN4),
1004 PINMUX_DATA(DV_CLK_MARK, PORT62_FN6),
1005 PINMUX_DATA(IRQ15_PORT62_MARK, PORT62_FN0, MSEL1CR_15_1),
1006
1007 /* Port63 */
1008 PINMUX_DATA(LCD0_VSYN_MARK, PORT63_FN1),
1009 PINMUX_DATA(DV_VSYNC_MARK, PORT63_FN6),
1010 PINMUX_DATA(IRQ14_PORT63_MARK, PORT63_FN0, MSEL1CR_14_1),
1011
1012 /* Port64 */
1013 PINMUX_DATA(LCD0_HSYN_MARK, PORT64_FN1),
1014 PINMUX_DATA(LCD0_CS_MARK, PORT64_FN4),
1015 PINMUX_DATA(DV_HSYNC_MARK, PORT64_FN6),
1016 PINMUX_DATA(IRQ13_PORT64_MARK, PORT64_FN0, MSEL1CR_13_1),
1017
1018 /* Port65 */
1019 PINMUX_DATA(LCD0_DISP_MARK, PORT65_FN1),
1020 PINMUX_DATA(MSIOF2_TSCK_MARK, PORT65_FN2),
1021 PINMUX_DATA(LCD0_RS_MARK, PORT65_FN4),
1022
1023 /* Port66 */
1024 PINMUX_DATA(MEMC_INT_MARK, PORT66_FN1),
1025 PINMUX_DATA(TPU0TO2_PORT66_MARK, PORT66_FN3, MSEL5CR_25_0),
1026 PINMUX_DATA(MMC0_CLK_PORT66_MARK, PORT66_FN4, MSEL4CR_15_0),
1027 PINMUX_DATA(SDHI1_CLK_MARK, PORT66_FN6),
1028
1029 /* Port67 - Port73 Function1 */
1030 PINMUX_DATA(MEMC_CS0_MARK, PORT67_FN1),
1031 PINMUX_DATA(MEMC_AD8_MARK, PORT68_FN1),
1032 PINMUX_DATA(MEMC_AD9_MARK, PORT69_FN1),
1033 PINMUX_DATA(MEMC_AD10_MARK, PORT70_FN1),
1034 PINMUX_DATA(MEMC_AD11_MARK, PORT71_FN1),
1035 PINMUX_DATA(MEMC_AD12_MARK, PORT72_FN1),
1036 PINMUX_DATA(MEMC_AD13_MARK, PORT73_FN1),
1037
1038 /* Port67 - Port73 Function2 */
1039 PINMUX_DATA(MSIOF1_SS1_PORT67_MARK, PORT67_FN2, MSEL4CR_10_1),
1040 PINMUX_DATA(MSIOF1_RSCK_MARK, PORT68_FN2),
1041 PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT69_FN2),
1042 PINMUX_DATA(MSIOF1_MCK0_MARK, PORT70_FN2),
1043 PINMUX_DATA(MSIOF1_MCK1_MARK, PORT71_FN2),
1044 PINMUX_DATA(MSIOF1_TSCK_PORT72_MARK, PORT72_FN2, MSEL4CR_10_1),
1045 PINMUX_DATA(MSIOF1_TSYNC_PORT73_MARK, PORT73_FN2, MSEL4CR_10_1),
1046
1047 /* Port67 - Port73 Function4 */
1048 PINMUX_DATA(MMC0_CMD_PORT67_MARK, PORT67_FN4, MSEL4CR_15_0),
1049 PINMUX_DATA(MMC0_D0_PORT68_MARK, PORT68_FN4, MSEL4CR_15_0),
1050 PINMUX_DATA(MMC0_D1_PORT69_MARK, PORT69_FN4, MSEL4CR_15_0),
1051 PINMUX_DATA(MMC0_D2_PORT70_MARK, PORT70_FN4, MSEL4CR_15_0),
1052 PINMUX_DATA(MMC0_D3_PORT71_MARK, PORT71_FN4, MSEL4CR_15_0),
1053 PINMUX_DATA(MMC0_D4_PORT72_MARK, PORT72_FN4, MSEL4CR_15_0),
1054 PINMUX_DATA(MMC0_D5_PORT73_MARK, PORT73_FN4, MSEL4CR_15_0),
1055
1056 /* Port67 - Port73 Function6 */
1057 PINMUX_DATA(SDHI1_CMD_MARK, PORT67_FN6),
1058 PINMUX_DATA(SDHI1_D0_MARK, PORT68_FN6),
1059 PINMUX_DATA(SDHI1_D1_MARK, PORT69_FN6),
1060 PINMUX_DATA(SDHI1_D2_MARK, PORT70_FN6),
1061 PINMUX_DATA(SDHI1_D3_MARK, PORT71_FN6),
1062 PINMUX_DATA(SDHI1_CD_MARK, PORT72_FN6),
1063 PINMUX_DATA(SDHI1_WP_MARK, PORT73_FN6),
1064
1065 /* Port67 - Port71 IRQ */
1066 PINMUX_DATA(IRQ20_MARK, PORT67_FN0),
1067 PINMUX_DATA(IRQ16_PORT68_MARK, PORT68_FN0, MSEL1CR_16_0),
1068 PINMUX_DATA(IRQ17_MARK, PORT69_FN0),
1069 PINMUX_DATA(IRQ18_MARK, PORT70_FN0),
1070 PINMUX_DATA(IRQ19_MARK, PORT71_FN0),
1071
1072 /* Port74 */
1073 PINMUX_DATA(MEMC_AD14_MARK, PORT74_FN1),
1074 PINMUX_DATA(MSIOF1_TXD_PORT74_MARK, PORT74_FN2, MSEL4CR_10_1),
1075 PINMUX_DATA(MMC0_D6_PORT74_MARK, PORT74_FN4, MSEL4CR_15_0),
1076 PINMUX_DATA(STP1_IPD7_MARK, PORT74_FN6),
1077 PINMUX_DATA(LCD1_D21_MARK, PORT74_FN7),
1078
1079 /* Port75 */
1080 PINMUX_DATA(MEMC_AD15_MARK, PORT75_FN1),
1081 PINMUX_DATA(MSIOF1_RXD_PORT75_MARK, PORT75_FN2, MSEL4CR_10_1),
1082 PINMUX_DATA(MMC0_D7_PORT75_MARK, PORT75_FN4, MSEL4CR_15_0),
1083 PINMUX_DATA(STP1_IPD6_MARK, PORT75_FN6),
1084 PINMUX_DATA(LCD1_D20_MARK, PORT75_FN7),
1085
1086 /* Port76 - Port80 Function */
1087 PINMUX_DATA(SDHI0_CMD_MARK, PORT76_FN1),
1088 PINMUX_DATA(SDHI0_D0_MARK, PORT77_FN1),
1089 PINMUX_DATA(SDHI0_D1_MARK, PORT78_FN1),
1090 PINMUX_DATA(SDHI0_D2_MARK, PORT79_FN1),
1091 PINMUX_DATA(SDHI0_D3_MARK, PORT80_FN1),
1092
1093 /* Port81 */
1094 PINMUX_DATA(SDHI0_CD_MARK, PORT81_FN1),
1095 PINMUX_DATA(IRQ26_PORT81_MARK, PORT81_FN0, MSEL1CR_26_0),
1096
1097 /* Port82 - Port88 Function */
1098 PINMUX_DATA(SDHI0_CLK_MARK, PORT82_FN1),
1099 PINMUX_DATA(SDHI0_WP_MARK, PORT83_FN1),
1100 PINMUX_DATA(RESETOUTS_MARK, PORT84_FN1),
1101 PINMUX_DATA(USB0_PPON_MARK, PORT85_FN1),
1102 PINMUX_DATA(USB0_OCI_MARK, PORT86_FN1),
1103 PINMUX_DATA(USB1_PPON_MARK, PORT87_FN1),
1104 PINMUX_DATA(USB1_OCI_MARK, PORT88_FN1),
1105
1106 /* Port89 */
1107 PINMUX_DATA(DREQ0_MARK, PORT89_FN1),
1108 PINMUX_DATA(BBIF2_TSCK2_PORT89_MARK, PORT89_FN2, MSEL5CR_0_1),
1109 PINMUX_DATA(RSPI_SSL3_A_MARK, PORT89_FN6),
1110
1111 /* Port90 */
1112 PINMUX_DATA(DACK0_MARK, PORT90_FN1),
1113 PINMUX_DATA(BBIF2_RXD2_PORT90_MARK, PORT90_FN2, MSEL5CR_0_1),
1114 PINMUX_DATA(RSPI_SSL2_A_MARK, PORT90_FN6),
1115 PINMUX_DATA(WAIT_PORT90_MARK, PORT90_FN7, MSEL5CR_2_1),
1116
1117 /* Port91 */
1118 PINMUX_DATA(MEMC_AD0_MARK, PORT91_FN1),
1119 PINMUX_DATA(BBIF1_RXD_MARK, PORT91_FN2),
1120 PINMUX_DATA(SCIFA5_TXD_PORT91_MARK, PORT91_FN3, MSEL5CR_15_1, MSEL5CR_14_0),
1121 PINMUX_DATA(LCD1_D5_MARK, PORT91_FN7),
1122
1123 /* Port92 */
1124 PINMUX_DATA(MEMC_AD1_MARK, PORT92_FN1),
1125 PINMUX_DATA(BBIF1_TSYNC_MARK, PORT92_FN2),
1126 PINMUX_DATA(SCIFA5_RXD_PORT92_MARK, PORT92_FN3, MSEL5CR_15_1, MSEL5CR_14_0),
1127 PINMUX_DATA(STP0_IPD1_MARK, PORT92_FN6),
1128 PINMUX_DATA(LCD1_D6_MARK, PORT92_FN7),
1129
1130 /* Port93 */
1131 PINMUX_DATA(MEMC_AD2_MARK, PORT93_FN1),
1132 PINMUX_DATA(BBIF1_TSCK_MARK, PORT93_FN2),
1133 PINMUX_DATA(SCIFA4_TXD_PORT93_MARK, PORT93_FN3, MSEL5CR_12_1, MSEL5CR_11_0),
1134 PINMUX_DATA(STP0_IPD3_MARK, PORT93_FN6),
1135 PINMUX_DATA(LCD1_D8_MARK, PORT93_FN7),
1136
1137 /* Port94 */
1138 PINMUX_DATA(MEMC_AD3_MARK, PORT94_FN1),
1139 PINMUX_DATA(BBIF1_TXD_MARK, PORT94_FN2),
1140 PINMUX_DATA(SCIFA4_RXD_PORT94_MARK, PORT94_FN3, MSEL5CR_12_1, MSEL5CR_11_0),
1141 PINMUX_DATA(STP0_IPD4_MARK, PORT94_FN6),
1142 PINMUX_DATA(LCD1_D9_MARK, PORT94_FN7),
1143
1144 /* Port95 */
1145 PINMUX_DATA(MEMC_CS1_MARK, PORT95_FN1, MSEL4CR_6_0),
1146 PINMUX_DATA(MEMC_A1_MARK, PORT95_FN1, MSEL4CR_6_1),
1147
1148 PINMUX_DATA(SCIFA2_CTS_MARK, PORT95_FN2),
1149 PINMUX_DATA(SIM_RST_MARK, PORT95_FN4),
1150 PINMUX_DATA(VIO0_D14_PORT95_MARK, PORT95_FN7, MSEL5CR_27_1),
1151 PINMUX_DATA(IRQ22_MARK, PORT95_FN0),
1152
1153 /* Port96 */
1154 PINMUX_DATA(MEMC_ADV_MARK, PORT96_FN1, MSEL4CR_6_0),
1155 PINMUX_DATA(MEMC_DREQ0_MARK, PORT96_FN1, MSEL4CR_6_1),
1156
1157 PINMUX_DATA(SCIFA2_RTS_MARK, PORT96_FN2),
1158 PINMUX_DATA(SIM_CLK_MARK, PORT96_FN4),
1159 PINMUX_DATA(VIO0_D15_PORT96_MARK, PORT96_FN7, MSEL5CR_27_1),
1160 PINMUX_DATA(IRQ23_MARK, PORT96_FN0),
1161
1162 /* Port97 */
1163 PINMUX_DATA(MEMC_AD4_MARK, PORT97_FN1),
1164 PINMUX_DATA(BBIF1_RSCK_MARK, PORT97_FN2),
1165 PINMUX_DATA(LCD1_CS_MARK, PORT97_FN6),
1166 PINMUX_DATA(LCD1_HSYN_MARK, PORT97_FN7),
1167 PINMUX_DATA(IRQ12_PORT97_MARK, PORT97_FN0, MSEL1CR_12_0),
1168
1169 /* Port98 */
1170 PINMUX_DATA(MEMC_AD5_MARK, PORT98_FN1),
1171 PINMUX_DATA(BBIF1_RSYNC_MARK, PORT98_FN2),
1172 PINMUX_DATA(LCD1_VSYN_MARK, PORT98_FN7),
1173 PINMUX_DATA(IRQ13_PORT98_MARK, PORT98_FN0, MSEL1CR_13_0),
1174
1175 /* Port99 */
1176 PINMUX_DATA(MEMC_AD6_MARK, PORT99_FN1),
1177 PINMUX_DATA(BBIF1_FLOW_MARK, PORT99_FN2),
1178 PINMUX_DATA(LCD1_WR_MARK, PORT99_FN6),
1179 PINMUX_DATA(LCD1_DCK_MARK, PORT99_FN7),
1180 PINMUX_DATA(IRQ14_PORT99_MARK, PORT99_FN0, MSEL1CR_14_0),
1181
1182 /* Port100 */
1183 PINMUX_DATA(MEMC_AD7_MARK, PORT100_FN1),
1184 PINMUX_DATA(BBIF1_RX_FLOW_N_MARK, PORT100_FN2),
1185 PINMUX_DATA(LCD1_DON_MARK, PORT100_FN7),
1186 PINMUX_DATA(IRQ15_PORT100_MARK, PORT100_FN0, MSEL1CR_15_0),
1187
1188 /* Port101 */
1189 PINMUX_DATA(FCE0_MARK, PORT101_FN1),
1190
1191 /* Port102 */
1192 PINMUX_DATA(FRB_MARK, PORT102_FN1),
1193 PINMUX_DATA(LCD0_LCLK_PORT102_MARK, PORT102_FN4, MSEL5CR_6_0),
1194
1195 /* Port103 */
1196 PINMUX_DATA(CS5B_MARK, PORT103_FN1),
1197 PINMUX_DATA(FCE1_MARK, PORT103_FN2),
1198 PINMUX_DATA(MMC1_CLK_PORT103_MARK, PORT103_FN3, MSEL4CR_15_1),
1199
1200 /* Port104 */
1201 PINMUX_DATA(CS6A_MARK, PORT104_FN1),
1202 PINMUX_DATA(MMC1_CMD_PORT104_MARK, PORT104_FN3, MSEL4CR_15_1),
1203 PINMUX_DATA(IRQ11_MARK, PORT104_FN0),
1204
1205 /* Port105 */
1206 PINMUX_DATA(CS5A_PORT105_MARK, PORT105_FN1, MSEL5CR_2_0),
1207 PINMUX_DATA(SCIFA3_RTS_PORT105_MARK, PORT105_FN4, MSEL5CR_8_0),
1208
1209 /* Port106 */
1210 PINMUX_DATA(IOIS16_MARK, PORT106_FN1),
1211 PINMUX_DATA(IDE_EXBUF_ENB_MARK, PORT106_FN6),
1212
1213 /* Port107 - Port115 Function */
1214 PINMUX_DATA(WE3_ICIOWR_MARK, PORT107_FN1),
1215 PINMUX_DATA(WE2_ICIORD_MARK, PORT108_FN1),
1216 PINMUX_DATA(CS0_MARK, PORT109_FN1),
1217 PINMUX_DATA(CS2_MARK, PORT110_FN1),
1218 PINMUX_DATA(CS4_MARK, PORT111_FN1),
1219 PINMUX_DATA(WE1_MARK, PORT112_FN1),
1220 PINMUX_DATA(WE0_FWE_MARK, PORT113_FN1),
1221 PINMUX_DATA(RDWR_MARK, PORT114_FN1),
1222 PINMUX_DATA(RD_FSC_MARK, PORT115_FN1),
1223
1224 /* Port116 */
1225 PINMUX_DATA(A25_MARK, PORT116_FN1),
1226 PINMUX_DATA(MSIOF0_SS2_MARK, PORT116_FN2),
1227 PINMUX_DATA(MSIOF1_SS2_PORT116_MARK, PORT116_FN3, MSEL4CR_10_0),
1228 PINMUX_DATA(SCIFA3_SCK_PORT116_MARK, PORT116_FN4, MSEL5CR_8_0),
1229 PINMUX_DATA(GPO1_MARK, PORT116_FN5),
1230
1231 /* Port117 */
1232 PINMUX_DATA(A24_MARK, PORT117_FN1),
1233 PINMUX_DATA(MSIOF0_SS1_MARK, PORT117_FN2),
1234 PINMUX_DATA(MSIOF1_SS1_PORT117_MARK, PORT117_FN3, MSEL4CR_10_0),
1235 PINMUX_DATA(SCIFA3_CTS_PORT117_MARK, PORT117_FN4, MSEL5CR_8_0),
1236 PINMUX_DATA(GPO0_MARK, PORT117_FN5),
1237
1238 /* Port118 */
1239 PINMUX_DATA(A23_MARK, PORT118_FN1),
1240 PINMUX_DATA(MSIOF0_MCK1_MARK, PORT118_FN2),
1241 PINMUX_DATA(MSIOF1_RXD_PORT118_MARK, PORT118_FN3, MSEL4CR_10_0),
1242 PINMUX_DATA(GPI1_MARK, PORT118_FN5),
1243 PINMUX_DATA(IRQ9_PORT118_MARK, PORT118_FN0, MSEL1CR_9_0),
1244
1245 /* Port119 */
1246 PINMUX_DATA(A22_MARK, PORT119_FN1),
1247 PINMUX_DATA(MSIOF0_MCK0_MARK, PORT119_FN2),
1248 PINMUX_DATA(MSIOF1_TXD_PORT119_MARK, PORT119_FN3, MSEL4CR_10_0),
1249 PINMUX_DATA(GPI0_MARK, PORT119_FN5),
1250 PINMUX_DATA(IRQ8_MARK, PORT119_FN0),
1251
1252 /* Port120 */
1253 PINMUX_DATA(A21_MARK, PORT120_FN1),
1254 PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT120_FN2),
1255 PINMUX_DATA(MSIOF1_TSYNC_PORT120_MARK, PORT120_FN3, MSEL4CR_10_0),
1256 PINMUX_DATA(IRQ7_PORT120_MARK, PORT120_FN0, MSEL1CR_7_0),
1257
1258 /* Port121 */
1259 PINMUX_DATA(A20_MARK, PORT121_FN1),
1260 PINMUX_DATA(MSIOF0_RSCK_MARK, PORT121_FN2),
1261 PINMUX_DATA(MSIOF1_TSCK_PORT121_MARK, PORT121_FN3, MSEL4CR_10_0),
1262 PINMUX_DATA(IRQ6_PORT121_MARK, PORT121_FN0, MSEL1CR_6_0),
1263
1264 /* Port122 */
1265 PINMUX_DATA(A19_MARK, PORT122_FN1),
1266 PINMUX_DATA(MSIOF0_RXD_MARK, PORT122_FN2),
1267
1268 /* Port123 */
1269 PINMUX_DATA(A18_MARK, PORT123_FN1),
1270 PINMUX_DATA(MSIOF0_TSCK_MARK, PORT123_FN2),
1271
1272 /* Port124 */
1273 PINMUX_DATA(A17_MARK, PORT124_FN1),
1274 PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT124_FN2),
1275
1276 /* Port125 - Port141 Function */
1277 PINMUX_DATA(A16_MARK, PORT125_FN1),
1278 PINMUX_DATA(A15_MARK, PORT126_FN1),
1279 PINMUX_DATA(A14_MARK, PORT127_FN1),
1280 PINMUX_DATA(A13_MARK, PORT128_FN1),
1281 PINMUX_DATA(A12_MARK, PORT129_FN1),
1282 PINMUX_DATA(A11_MARK, PORT130_FN1),
1283 PINMUX_DATA(A10_MARK, PORT131_FN1),
1284 PINMUX_DATA(A9_MARK, PORT132_FN1),
1285 PINMUX_DATA(A8_MARK, PORT133_FN1),
1286 PINMUX_DATA(A7_MARK, PORT134_FN1),
1287 PINMUX_DATA(A6_MARK, PORT135_FN1),
1288 PINMUX_DATA(A5_FCDE_MARK, PORT136_FN1),
1289 PINMUX_DATA(A4_FOE_MARK, PORT137_FN1),
1290 PINMUX_DATA(A3_MARK, PORT138_FN1),
1291 PINMUX_DATA(A2_MARK, PORT139_FN1),
1292 PINMUX_DATA(A1_MARK, PORT140_FN1),
1293 PINMUX_DATA(CKO_MARK, PORT141_FN1),
1294
1295 /* Port142 - Port157 Function1 */
1296 PINMUX_DATA(D15_NAF15_MARK, PORT142_FN1),
1297 PINMUX_DATA(D14_NAF14_MARK, PORT143_FN1),
1298 PINMUX_DATA(D13_NAF13_MARK, PORT144_FN1),
1299 PINMUX_DATA(D12_NAF12_MARK, PORT145_FN1),
1300 PINMUX_DATA(D11_NAF11_MARK, PORT146_FN1),
1301 PINMUX_DATA(D10_NAF10_MARK, PORT147_FN1),
1302 PINMUX_DATA(D9_NAF9_MARK, PORT148_FN1),
1303 PINMUX_DATA(D8_NAF8_MARK, PORT149_FN1),
1304 PINMUX_DATA(D7_NAF7_MARK, PORT150_FN1),
1305 PINMUX_DATA(D6_NAF6_MARK, PORT151_FN1),
1306 PINMUX_DATA(D5_NAF5_MARK, PORT152_FN1),
1307 PINMUX_DATA(D4_NAF4_MARK, PORT153_FN1),
1308 PINMUX_DATA(D3_NAF3_MARK, PORT154_FN1),
1309 PINMUX_DATA(D2_NAF2_MARK, PORT155_FN1),
1310 PINMUX_DATA(D1_NAF1_MARK, PORT156_FN1),
1311 PINMUX_DATA(D0_NAF0_MARK, PORT157_FN1),
1312
1313 /* Port142 - Port149 Function3 */
1314 PINMUX_DATA(MMC1_D7_PORT142_MARK, PORT142_FN3, MSEL4CR_15_1),
1315 PINMUX_DATA(MMC1_D6_PORT143_MARK, PORT143_FN3, MSEL4CR_15_1),
1316 PINMUX_DATA(MMC1_D5_PORT144_MARK, PORT144_FN3, MSEL4CR_15_1),
1317 PINMUX_DATA(MMC1_D4_PORT145_MARK, PORT145_FN3, MSEL4CR_15_1),
1318 PINMUX_DATA(MMC1_D3_PORT146_MARK, PORT146_FN3, MSEL4CR_15_1),
1319 PINMUX_DATA(MMC1_D2_PORT147_MARK, PORT147_FN3, MSEL4CR_15_1),
1320 PINMUX_DATA(MMC1_D1_PORT148_MARK, PORT148_FN3, MSEL4CR_15_1),
1321 PINMUX_DATA(MMC1_D0_PORT149_MARK, PORT149_FN3, MSEL4CR_15_1),
1322
1323 /* Port158 */
1324 PINMUX_DATA(D31_MARK, PORT158_FN1),
1325 PINMUX_DATA(SCIFA3_SCK_PORT158_MARK, PORT158_FN2, MSEL5CR_8_1),
1326 PINMUX_DATA(RMII_REF125CK_MARK, PORT158_FN3),
1327 PINMUX_DATA(LCD0_D21_PORT158_MARK, PORT158_FN4, MSEL5CR_6_1),
1328 PINMUX_DATA(IRDA_FIRSEL_MARK, PORT158_FN5),
1329 PINMUX_DATA(IDE_D15_MARK, PORT158_FN6),
1330
1331 /* Port159 */
1332 PINMUX_DATA(D30_MARK, PORT159_FN1),
1333 PINMUX_DATA(SCIFA3_RXD_PORT159_MARK, PORT159_FN2, MSEL5CR_8_1),
1334 PINMUX_DATA(RMII_REF50CK_MARK, PORT159_FN3),
1335 PINMUX_DATA(LCD0_D23_PORT159_MARK, PORT159_FN4, MSEL5CR_6_1),
1336 PINMUX_DATA(IDE_D14_MARK, PORT159_FN6),
1337
1338 /* Port160 */
1339 PINMUX_DATA(D29_MARK, PORT160_FN1),
1340 PINMUX_DATA(SCIFA3_TXD_PORT160_MARK, PORT160_FN2, MSEL5CR_8_1),
1341 PINMUX_DATA(LCD0_D22_PORT160_MARK, PORT160_FN4, MSEL5CR_6_1),
1342 PINMUX_DATA(VIO1_HD_MARK, PORT160_FN5),
1343 PINMUX_DATA(IDE_D13_MARK, PORT160_FN6),
1344
1345 /* Port161 */
1346 PINMUX_DATA(D28_MARK, PORT161_FN1),
1347 PINMUX_DATA(SCIFA3_RTS_PORT161_MARK, PORT161_FN2, MSEL5CR_8_1),
1348 PINMUX_DATA(ET_RX_DV_MARK, PORT161_FN3),
1349 PINMUX_DATA(LCD0_D20_PORT161_MARK, PORT161_FN4, MSEL5CR_6_1),
1350 PINMUX_DATA(IRDA_IN_MARK, PORT161_FN5),
1351 PINMUX_DATA(IDE_D12_MARK, PORT161_FN6),
1352
1353 /* Port162 */
1354 PINMUX_DATA(D27_MARK, PORT162_FN1),
1355 PINMUX_DATA(SCIFA3_CTS_PORT162_MARK, PORT162_FN2, MSEL5CR_8_1),
1356 PINMUX_DATA(LCD0_D19_PORT162_MARK, PORT162_FN4, MSEL5CR_6_1),
1357 PINMUX_DATA(IRDA_OUT_MARK, PORT162_FN5),
1358 PINMUX_DATA(IDE_D11_MARK, PORT162_FN6),
1359
1360 /* Port163 */
1361 PINMUX_DATA(D26_MARK, PORT163_FN1),
1362 PINMUX_DATA(MSIOF2_SS2_MARK, PORT163_FN2),
1363 PINMUX_DATA(ET_COL_MARK, PORT163_FN3),
1364 PINMUX_DATA(LCD0_D18_PORT163_MARK, PORT163_FN4, MSEL5CR_6_1),
1365 PINMUX_DATA(IROUT_MARK, PORT163_FN5),
1366 PINMUX_DATA(IDE_D10_MARK, PORT163_FN6),
1367
1368 /* Port164 */
1369 PINMUX_DATA(D25_MARK, PORT164_FN1),
1370 PINMUX_DATA(MSIOF2_TSYNC_MARK, PORT164_FN2),
1371 PINMUX_DATA(ET_PHY_INT_MARK, PORT164_FN3),
1372 PINMUX_DATA(LCD0_RD_MARK, PORT164_FN4),
1373 PINMUX_DATA(IDE_D9_MARK, PORT164_FN6),
1374
1375 /* Port165 */
1376 PINMUX_DATA(D24_MARK, PORT165_FN1),
1377 PINMUX_DATA(MSIOF2_RXD_MARK, PORT165_FN2),
1378 PINMUX_DATA(LCD0_LCLK_PORT165_MARK, PORT165_FN4, MSEL5CR_6_1),
1379 PINMUX_DATA(IDE_D8_MARK, PORT165_FN6),
1380
1381 /* Port166 - Port171 Function1 */
1382 PINMUX_DATA(D21_MARK, PORT166_FN1),
1383 PINMUX_DATA(D20_MARK, PORT167_FN1),
1384 PINMUX_DATA(D19_MARK, PORT168_FN1),
1385 PINMUX_DATA(D18_MARK, PORT169_FN1),
1386 PINMUX_DATA(D17_MARK, PORT170_FN1),
1387 PINMUX_DATA(D16_MARK, PORT171_FN1),
1388
1389 /* Port166 - Port171 Function3 */
1390 PINMUX_DATA(ET_ETXD5_MARK, PORT166_FN3),
1391 PINMUX_DATA(ET_ETXD4_MARK, PORT167_FN3),
1392 PINMUX_DATA(ET_ETXD3_MARK, PORT168_FN3),
1393 PINMUX_DATA(ET_ETXD2_MARK, PORT169_FN3),
1394 PINMUX_DATA(ET_ETXD1_MARK, PORT170_FN3),
1395 PINMUX_DATA(ET_ETXD0_MARK, PORT171_FN3),
1396
1397 /* Port166 - Port171 Function6 */
1398 PINMUX_DATA(IDE_D5_MARK, PORT166_FN6),
1399 PINMUX_DATA(IDE_D4_MARK, PORT167_FN6),
1400 PINMUX_DATA(IDE_D3_MARK, PORT168_FN6),
1401 PINMUX_DATA(IDE_D2_MARK, PORT169_FN6),
1402 PINMUX_DATA(IDE_D1_MARK, PORT170_FN6),
1403 PINMUX_DATA(IDE_D0_MARK, PORT171_FN6),
1404
1405 /* Port167 - Port171 IRQ */
1406 PINMUX_DATA(IRQ31_PORT167_MARK, PORT167_FN0, MSEL1CR_31_0),
1407 PINMUX_DATA(IRQ27_PORT168_MARK, PORT168_FN0, MSEL1CR_27_0),
1408 PINMUX_DATA(IRQ28_PORT169_MARK, PORT169_FN0, MSEL1CR_28_0),
1409 PINMUX_DATA(IRQ29_PORT170_MARK, PORT170_FN0, MSEL1CR_29_0),
1410 PINMUX_DATA(IRQ30_PORT171_MARK, PORT171_FN0, MSEL1CR_30_0),
1411
1412 /* Port172 */
1413 PINMUX_DATA(D23_MARK, PORT172_FN1),
1414 PINMUX_DATA(SCIFB_RTS_PORT172_MARK, PORT172_FN2, MSEL5CR_17_1),
1415 PINMUX_DATA(ET_ETXD7_MARK, PORT172_FN3),
1416 PINMUX_DATA(IDE_D7_MARK, PORT172_FN6),
1417 PINMUX_DATA(IRQ4_PORT172_MARK, PORT172_FN0, MSEL1CR_4_1),
1418
1419 /* Port173 */
1420 PINMUX_DATA(D22_MARK, PORT173_FN1),
1421 PINMUX_DATA(SCIFB_CTS_PORT173_MARK, PORT173_FN2, MSEL5CR_17_1),
1422 PINMUX_DATA(ET_ETXD6_MARK, PORT173_FN3),
1423 PINMUX_DATA(IDE_D6_MARK, PORT173_FN6),
1424 PINMUX_DATA(IRQ6_PORT173_MARK, PORT173_FN0, MSEL1CR_6_1),
1425
1426 /* Port174 */
1427 PINMUX_DATA(A26_MARK, PORT174_FN1),
1428 PINMUX_DATA(MSIOF0_TXD_MARK, PORT174_FN2),
1429 PINMUX_DATA(ET_RX_CLK_MARK, PORT174_FN3),
1430 PINMUX_DATA(SCIFA3_RXD_PORT174_MARK, PORT174_FN4, MSEL5CR_8_0),
1431
1432 /* Port175 */
1433 PINMUX_DATA(A0_MARK, PORT175_FN1),
1434 PINMUX_DATA(BS_MARK, PORT175_FN2),
1435 PINMUX_DATA(ET_WOL_MARK, PORT175_FN3),
1436 PINMUX_DATA(SCIFA3_TXD_PORT175_MARK, PORT175_FN4, MSEL5CR_8_0),
1437
1438 /* Port176 */
1439 PINMUX_DATA(ET_GTX_CLK_MARK, PORT176_FN3),
1440
1441 /* Port177 */
1442 PINMUX_DATA(WAIT_PORT177_MARK, PORT177_FN1, MSEL5CR_2_0),
1443 PINMUX_DATA(ET_LINK_MARK, PORT177_FN3),
1444 PINMUX_DATA(IDE_IOWR_MARK, PORT177_FN6),
1445 PINMUX_DATA(SDHI2_WP_PORT177_MARK, PORT177_FN7, MSEL5CR_19_1),
1446
1447 /* Port178 */
1448 PINMUX_DATA(VIO0_D12_MARK, PORT178_FN1),
1449 PINMUX_DATA(VIO1_D4_MARK, PORT178_FN5),
1450 PINMUX_DATA(IDE_IORD_MARK, PORT178_FN6),
1451
1452 /* Port179 */
1453 PINMUX_DATA(VIO0_D11_MARK, PORT179_FN1),
1454 PINMUX_DATA(VIO1_D3_MARK, PORT179_FN5),
1455 PINMUX_DATA(IDE_IORDY_MARK, PORT179_FN6),
1456
1457 /* Port180 */
1458 PINMUX_DATA(VIO0_D10_MARK, PORT180_FN1),
1459 PINMUX_DATA(TPU0TO3_MARK, PORT180_FN4),
1460 PINMUX_DATA(VIO1_D2_MARK, PORT180_FN5),
1461 PINMUX_DATA(IDE_INT_MARK, PORT180_FN6),
1462 PINMUX_DATA(IRQ24_MARK, PORT180_FN0),
1463
1464 /* Port181 */
1465 PINMUX_DATA(VIO0_D9_MARK, PORT181_FN1),
1466 PINMUX_DATA(VIO1_D1_MARK, PORT181_FN5),
1467 PINMUX_DATA(IDE_RST_MARK, PORT181_FN6),
1468
1469 /* Port182 */
1470 PINMUX_DATA(VIO0_D8_MARK, PORT182_FN1),
1471 PINMUX_DATA(VIO1_D0_MARK, PORT182_FN5),
1472 PINMUX_DATA(IDE_DIRECTION_MARK, PORT182_FN6),
1473
1474 /* Port183 */
1475 PINMUX_DATA(DREQ1_MARK, PORT183_FN1),
1476 PINMUX_DATA(BBIF2_TXD2_PORT183_MARK, PORT183_FN2, MSEL5CR_0_1),
1477 PINMUX_DATA(ET_TX_EN_MARK, PORT183_FN3),
1478
1479 /* Port184 */
1480 PINMUX_DATA(DACK1_MARK, PORT184_FN1),
1481 PINMUX_DATA(BBIF2_TSYNC2_PORT184_MARK, PORT184_FN2, MSEL5CR_0_1),
1482 PINMUX_DATA(ET_TX_CLK_MARK, PORT184_FN3),
1483
1484 /* Port185 - Port192 Function1 */
1485 PINMUX_DATA(SCIFA1_SCK_MARK, PORT185_FN1),
1486 PINMUX_DATA(SCIFB_RTS_PORT186_MARK, PORT186_FN1, MSEL5CR_17_0),
1487 PINMUX_DATA(SCIFB_CTS_PORT187_MARK, PORT187_FN1, MSEL5CR_17_0),
1488 PINMUX_DATA(SCIFA0_SCK_MARK, PORT188_FN1),
1489 PINMUX_DATA(SCIFB_SCK_PORT190_MARK, PORT190_FN1, MSEL5CR_17_0),
1490 PINMUX_DATA(SCIFB_RXD_PORT191_MARK, PORT191_FN1, MSEL5CR_17_0),
1491 PINMUX_DATA(SCIFB_TXD_PORT192_MARK, PORT192_FN1, MSEL5CR_17_0),
1492
1493 /* Port185 - Port192 Function3 */
1494 PINMUX_DATA(ET_ERXD0_MARK, PORT185_FN3),
1495 PINMUX_DATA(ET_ERXD1_MARK, PORT186_FN3),
1496 PINMUX_DATA(ET_ERXD2_MARK, PORT187_FN3),
1497 PINMUX_DATA(ET_ERXD3_MARK, PORT188_FN3),
1498 PINMUX_DATA(ET_ERXD4_MARK, PORT189_FN3),
1499 PINMUX_DATA(ET_ERXD5_MARK, PORT190_FN3),
1500 PINMUX_DATA(ET_ERXD6_MARK, PORT191_FN3),
1501 PINMUX_DATA(ET_ERXD7_MARK, PORT192_FN3),
1502
1503 /* Port185 - Port192 Function6 */
1504 PINMUX_DATA(STP1_IPCLK_MARK, PORT185_FN6),
1505 PINMUX_DATA(STP1_IPD0_PORT186_MARK, PORT186_FN6, MSEL5CR_23_0),
1506 PINMUX_DATA(STP1_IPEN_PORT187_MARK, PORT187_FN6, MSEL5CR_23_0),
1507 PINMUX_DATA(STP1_IPSYNC_MARK, PORT188_FN6),
1508 PINMUX_DATA(STP0_IPCLK_MARK, PORT189_FN6),
1509 PINMUX_DATA(STP0_IPD0_MARK, PORT190_FN6),
1510 PINMUX_DATA(STP0_IPEN_MARK, PORT191_FN6),
1511 PINMUX_DATA(STP0_IPSYNC_MARK, PORT192_FN6),
1512
1513 /* Port193 */
1514 PINMUX_DATA(SCIFA0_CTS_MARK, PORT193_FN1),
1515 PINMUX_DATA(RMII_CRS_DV_MARK, PORT193_FN3),
1516 PINMUX_DATA(STP1_IPEN_PORT193_MARK, PORT193_FN6, MSEL5CR_23_1), /* ? */
1517 PINMUX_DATA(LCD1_D17_MARK, PORT193_FN7),
1518
1519 /* Port194 */
1520 PINMUX_DATA(SCIFA0_RTS_MARK, PORT194_FN1),
1521 PINMUX_DATA(RMII_RX_ER_MARK, PORT194_FN3),
1522 PINMUX_DATA(STP1_IPD0_PORT194_MARK, PORT194_FN6, MSEL5CR_23_1), /* ? */
1523 PINMUX_DATA(LCD1_D16_MARK, PORT194_FN7),
1524
1525 /* Port195 */
1526 PINMUX_DATA(SCIFA1_RXD_MARK, PORT195_FN1),
1527 PINMUX_DATA(RMII_RXD0_MARK, PORT195_FN3),
1528 PINMUX_DATA(STP1_IPD3_MARK, PORT195_FN6),
1529 PINMUX_DATA(LCD1_D15_MARK, PORT195_FN7),
1530
1531 /* Port196 */
1532 PINMUX_DATA(SCIFA1_TXD_MARK, PORT196_FN1),
1533 PINMUX_DATA(RMII_RXD1_MARK, PORT196_FN3),
1534 PINMUX_DATA(STP1_IPD2_MARK, PORT196_FN6),
1535 PINMUX_DATA(LCD1_D14_MARK, PORT196_FN7),
1536
1537 /* Port197 */
1538 PINMUX_DATA(SCIFA0_RXD_MARK, PORT197_FN1),
1539 PINMUX_DATA(VIO1_CLK_MARK, PORT197_FN5),
1540 PINMUX_DATA(STP1_IPD5_MARK, PORT197_FN6),
1541 PINMUX_DATA(LCD1_D19_MARK, PORT197_FN7),
1542
1543 /* Port198 */
1544 PINMUX_DATA(SCIFA0_TXD_MARK, PORT198_FN1),
1545 PINMUX_DATA(VIO1_VD_MARK, PORT198_FN5),
1546 PINMUX_DATA(STP1_IPD4_MARK, PORT198_FN6),
1547 PINMUX_DATA(LCD1_D18_MARK, PORT198_FN7),
1548
1549 /* Port199 */
1550 PINMUX_DATA(MEMC_NWE_MARK, PORT199_FN1),
1551 PINMUX_DATA(SCIFA2_SCK_PORT199_MARK, PORT199_FN2, MSEL5CR_7_1),
1552 PINMUX_DATA(RMII_TX_EN_MARK, PORT199_FN3),
1553 PINMUX_DATA(SIM_D_PORT199_MARK, PORT199_FN4, MSEL5CR_21_1),
1554 PINMUX_DATA(STP1_IPD1_MARK, PORT199_FN6),
1555 PINMUX_DATA(LCD1_D13_MARK, PORT199_FN7),
1556
1557 /* Port200 */
1558 PINMUX_DATA(MEMC_NOE_MARK, PORT200_FN1),
1559 PINMUX_DATA(SCIFA2_RXD_MARK, PORT200_FN2),
1560 PINMUX_DATA(RMII_TXD0_MARK, PORT200_FN3),
1561 PINMUX_DATA(STP0_IPD7_MARK, PORT200_FN6),
1562 PINMUX_DATA(LCD1_D12_MARK, PORT200_FN7),
1563
1564 /* Port201 */
1565 PINMUX_DATA(MEMC_WAIT_MARK, PORT201_FN1, MSEL4CR_6_0),
1566 PINMUX_DATA(MEMC_DREQ1_MARK, PORT201_FN1, MSEL4CR_6_1),
1567
1568 PINMUX_DATA(SCIFA2_TXD_MARK, PORT201_FN2),
1569 PINMUX_DATA(RMII_TXD1_MARK, PORT201_FN3),
1570 PINMUX_DATA(STP0_IPD6_MARK, PORT201_FN6),
1571 PINMUX_DATA(LCD1_D11_MARK, PORT201_FN7),
1572
1573 /* Port202 */
1574 PINMUX_DATA(MEMC_BUSCLK_MARK, PORT202_FN1, MSEL4CR_6_0),
1575 PINMUX_DATA(MEMC_A0_MARK, PORT202_FN1, MSEL4CR_6_1),
1576
1577 PINMUX_DATA(MSIOF1_SS2_PORT202_MARK, PORT202_FN2, MSEL4CR_10_1),
1578 PINMUX_DATA(RMII_MDC_MARK, PORT202_FN3),
1579 PINMUX_DATA(TPU0TO2_PORT202_MARK, PORT202_FN4, MSEL5CR_25_1),
1580 PINMUX_DATA(IDE_CS0_MARK, PORT202_FN6),
1581 PINMUX_DATA(SDHI2_CD_PORT202_MARK, PORT202_FN7, MSEL5CR_19_1),
1582 PINMUX_DATA(IRQ21_MARK, PORT202_FN0),
1583
1584 /* Port203 - Port208 Function1 */
1585 PINMUX_DATA(SDHI2_CLK_MARK, PORT203_FN1),
1586 PINMUX_DATA(SDHI2_CMD_MARK, PORT204_FN1),
1587 PINMUX_DATA(SDHI2_D0_MARK, PORT205_FN1),
1588 PINMUX_DATA(SDHI2_D1_MARK, PORT206_FN1),
1589 PINMUX_DATA(SDHI2_D2_MARK, PORT207_FN1),
1590 PINMUX_DATA(SDHI2_D3_MARK, PORT208_FN1),
1591
1592 /* Port203 - Port208 Function3 */
1593 PINMUX_DATA(ET_TX_ER_MARK, PORT203_FN3),
1594 PINMUX_DATA(ET_RX_ER_MARK, PORT204_FN3),
1595 PINMUX_DATA(ET_CRS_MARK, PORT205_FN3),
1596 PINMUX_DATA(ET_MDC_MARK, PORT206_FN3),
1597 PINMUX_DATA(ET_MDIO_MARK, PORT207_FN3),
1598 PINMUX_DATA(RMII_MDIO_MARK, PORT208_FN3),
1599
1600 /* Port203 - Port208 Function6 */
1601 PINMUX_DATA(IDE_A2_MARK, PORT203_FN6),
1602 PINMUX_DATA(IDE_A1_MARK, PORT204_FN6),
1603 PINMUX_DATA(IDE_A0_MARK, PORT205_FN6),
1604 PINMUX_DATA(IDE_IODACK_MARK, PORT206_FN6),
1605 PINMUX_DATA(IDE_IODREQ_MARK, PORT207_FN6),
1606 PINMUX_DATA(IDE_CS1_MARK, PORT208_FN6),
1607
1608 /* Port203 - Port208 Function7 */
1609 PINMUX_DATA(SCIFA4_TXD_PORT203_MARK, PORT203_FN7, MSEL5CR_12_0, MSEL5CR_11_1),
1610 PINMUX_DATA(SCIFA4_RXD_PORT204_MARK, PORT204_FN7, MSEL5CR_12_0, MSEL5CR_11_1),
1611 PINMUX_DATA(SCIFA4_SCK_PORT205_MARK, PORT205_FN7, MSEL5CR_10_1),
1612 PINMUX_DATA(SCIFA5_SCK_PORT206_MARK, PORT206_FN7, MSEL5CR_13_1),
1613 PINMUX_DATA(SCIFA5_RXD_PORT207_MARK, PORT207_FN7, MSEL5CR_15_0, MSEL5CR_14_1),
1614 PINMUX_DATA(SCIFA5_TXD_PORT208_MARK, PORT208_FN7, MSEL5CR_15_0, MSEL5CR_14_1),
1615
1616 /* Port209 */
1617 PINMUX_DATA(VBUS_MARK, PORT209_FN1),
1618 PINMUX_DATA(IRQ7_PORT209_MARK, PORT209_FN0, MSEL1CR_7_1),
1619
1620 /* Port210 */
1621 PINMUX_DATA(IRQ9_PORT210_MARK, PORT210_FN0, MSEL1CR_9_1),
1622
1623 /* Port211 */
1624 PINMUX_DATA(IRQ16_PORT211_MARK, PORT211_FN0, MSEL1CR_16_1),
1625
1626 /* LCDC select */
1627 PINMUX_DATA(LCDC0_SELECT_MARK, MSEL3CR_6_0),
1628 PINMUX_DATA(LCDC1_SELECT_MARK, MSEL3CR_6_1),
1629
1630 /* SDENC */
1631 PINMUX_DATA(SDENC_CPG_MARK, MSEL4CR_19_0),
1632 PINMUX_DATA(SDENC_DV_CLKI_MARK, MSEL4CR_19_1),
1633
1634 /* SYSC */
1635 PINMUX_DATA(RESETP_PULLUP_MARK, MSEL4CR_4_0),
1636 PINMUX_DATA(RESETP_PLAIN_MARK, MSEL4CR_4_1),
1637
1638 /* DEBUG */
1639 PINMUX_DATA(EDEBGREQ_PULLDOWN_MARK, MSEL4CR_1_0),
1640 PINMUX_DATA(EDEBGREQ_PULLUP_MARK, MSEL4CR_1_1),
1641
1642 PINMUX_DATA(TRACEAUD_FROM_VIO_MARK, MSEL5CR_30_0, MSEL5CR_29_0),
1643 PINMUX_DATA(TRACEAUD_FROM_LCDC0_MARK, MSEL5CR_30_0, MSEL5CR_29_1),
1644 PINMUX_DATA(TRACEAUD_FROM_MEMC_MARK, MSEL5CR_30_1, MSEL5CR_29_0),
1645};
1646
1647static struct pinmux_gpio pinmux_gpios[] = {
1648
1649 /* PORT */
1650 GPIO_PORT_ALL(),
1651
1652 /* IRQ */
1653 GPIO_FN(IRQ0_PORT2), GPIO_FN(IRQ0_PORT13),
1654 GPIO_FN(IRQ1),
1655 GPIO_FN(IRQ2_PORT11), GPIO_FN(IRQ2_PORT12),
1656 GPIO_FN(IRQ3_PORT10), GPIO_FN(IRQ3_PORT14),
1657 GPIO_FN(IRQ4_PORT15), GPIO_FN(IRQ4_PORT172),
1658 GPIO_FN(IRQ5_PORT0), GPIO_FN(IRQ5_PORT1),
1659 GPIO_FN(IRQ6_PORT121), GPIO_FN(IRQ6_PORT173),
1660 GPIO_FN(IRQ7_PORT120), GPIO_FN(IRQ7_PORT209),
1661 GPIO_FN(IRQ8),
1662 GPIO_FN(IRQ9_PORT118), GPIO_FN(IRQ9_PORT210),
1663 GPIO_FN(IRQ10),
1664 GPIO_FN(IRQ11),
1665 GPIO_FN(IRQ12_PORT42), GPIO_FN(IRQ12_PORT97),
1666 GPIO_FN(IRQ13_PORT64), GPIO_FN(IRQ13_PORT98),
1667 GPIO_FN(IRQ14_PORT63), GPIO_FN(IRQ14_PORT99),
1668 GPIO_FN(IRQ15_PORT62), GPIO_FN(IRQ15_PORT100),
1669 GPIO_FN(IRQ16_PORT68), GPIO_FN(IRQ16_PORT211),
1670 GPIO_FN(IRQ17),
1671 GPIO_FN(IRQ18),
1672 GPIO_FN(IRQ19),
1673 GPIO_FN(IRQ20),
1674 GPIO_FN(IRQ21),
1675 GPIO_FN(IRQ22),
1676 GPIO_FN(IRQ23),
1677 GPIO_FN(IRQ24),
1678 GPIO_FN(IRQ25),
1679 GPIO_FN(IRQ26_PORT58), GPIO_FN(IRQ26_PORT81),
1680 GPIO_FN(IRQ27_PORT57), GPIO_FN(IRQ27_PORT168),
1681 GPIO_FN(IRQ28_PORT56), GPIO_FN(IRQ28_PORT169),
1682 GPIO_FN(IRQ29_PORT50), GPIO_FN(IRQ29_PORT170),
1683 GPIO_FN(IRQ30_PORT49), GPIO_FN(IRQ30_PORT171),
1684 GPIO_FN(IRQ31_PORT41), GPIO_FN(IRQ31_PORT167),
1685
1686 /* Function */
1687
1688 /* DBGT */
1689 GPIO_FN(DBGMDT2), GPIO_FN(DBGMDT1), GPIO_FN(DBGMDT0),
1690 GPIO_FN(DBGMD10), GPIO_FN(DBGMD11), GPIO_FN(DBGMD20),
1691 GPIO_FN(DBGMD21),
1692
1693 /* FSI */
1694 GPIO_FN(FSIAISLD_PORT0), /* FSIAISLD Port 0/5 */
1695 GPIO_FN(FSIAISLD_PORT5),
1696 GPIO_FN(FSIASPDIF_PORT9), /* FSIASPDIF Port 9/18 */
1697 GPIO_FN(FSIASPDIF_PORT18),
1698 GPIO_FN(FSIAOSLD1), GPIO_FN(FSIAOSLD2), GPIO_FN(FSIAOLR),
1699 GPIO_FN(FSIAOBT), GPIO_FN(FSIAOSLD), GPIO_FN(FSIAOMC),
1700 GPIO_FN(FSIACK), GPIO_FN(FSIAILR), GPIO_FN(FSIAIBT),
1701
1702 /* FMSI */
1703 GPIO_FN(FMSISLD_PORT1), /* FMSISLD Port 1/6 */
1704 GPIO_FN(FMSISLD_PORT6),
1705 GPIO_FN(FMSIILR), GPIO_FN(FMSIIBT), GPIO_FN(FMSIOLR),
1706 GPIO_FN(FMSIOBT), GPIO_FN(FMSICK), GPIO_FN(FMSOILR),
1707 GPIO_FN(FMSOIBT), GPIO_FN(FMSOOLR), GPIO_FN(FMSOOBT),
1708 GPIO_FN(FMSOSLD), GPIO_FN(FMSOCK),
1709
1710 /* SCIFA0 */
1711 GPIO_FN(SCIFA0_SCK), GPIO_FN(SCIFA0_CTS), GPIO_FN(SCIFA0_RTS),
1712 GPIO_FN(SCIFA0_RXD), GPIO_FN(SCIFA0_TXD),
1713
1714 /* SCIFA1 */
1715 GPIO_FN(SCIFA1_CTS), GPIO_FN(SCIFA1_SCK),
1716 GPIO_FN(SCIFA1_RXD), GPIO_FN(SCIFA1_TXD), GPIO_FN(SCIFA1_RTS),
1717
1718 /* SCIFA2 */
1719 GPIO_FN(SCIFA2_SCK_PORT22), /* SCIFA2_SCK Port 22/199 */
1720 GPIO_FN(SCIFA2_SCK_PORT199),
1721 GPIO_FN(SCIFA2_RXD), GPIO_FN(SCIFA2_TXD),
1722 GPIO_FN(SCIFA2_CTS), GPIO_FN(SCIFA2_RTS),
1723
1724 /* SCIFA3 */
1725 GPIO_FN(SCIFA3_RTS_PORT105), /* MSEL5CR_8_0 */
1726 GPIO_FN(SCIFA3_SCK_PORT116),
1727 GPIO_FN(SCIFA3_CTS_PORT117),
1728 GPIO_FN(SCIFA3_RXD_PORT174),
1729 GPIO_FN(SCIFA3_TXD_PORT175),
1730
1731 GPIO_FN(SCIFA3_RTS_PORT161), /* MSEL5CR_8_1 */
1732 GPIO_FN(SCIFA3_SCK_PORT158),
1733 GPIO_FN(SCIFA3_CTS_PORT162),
1734 GPIO_FN(SCIFA3_RXD_PORT159),
1735 GPIO_FN(SCIFA3_TXD_PORT160),
1736
1737 /* SCIFA4 */
1738 GPIO_FN(SCIFA4_RXD_PORT12), /* MSEL5CR[12:11] = 00 */
1739 GPIO_FN(SCIFA4_TXD_PORT13),
1740
1741 GPIO_FN(SCIFA4_RXD_PORT204), /* MSEL5CR[12:11] = 01 */
1742 GPIO_FN(SCIFA4_TXD_PORT203),
1743
1744 GPIO_FN(SCIFA4_RXD_PORT94), /* MSEL5CR[12:11] = 10 */
1745 GPIO_FN(SCIFA4_TXD_PORT93),
1746
1747 GPIO_FN(SCIFA4_SCK_PORT21), /* SCIFA4_SCK Port 21/205 */
1748 GPIO_FN(SCIFA4_SCK_PORT205),
1749
1750 /* SCIFA5 */
1751 GPIO_FN(SCIFA5_TXD_PORT20), /* MSEL5CR[15:14] = 00 */
1752 GPIO_FN(SCIFA5_RXD_PORT10),
1753
1754 GPIO_FN(SCIFA5_RXD_PORT207), /* MSEL5CR[15:14] = 01 */
1755 GPIO_FN(SCIFA5_TXD_PORT208),
1756
1757 GPIO_FN(SCIFA5_TXD_PORT91), /* MSEL5CR[15:14] = 10 */
1758 GPIO_FN(SCIFA5_RXD_PORT92),
1759
1760 GPIO_FN(SCIFA5_SCK_PORT23), /* SCIFA5_SCK Port 23/206 */
1761 GPIO_FN(SCIFA5_SCK_PORT206),
1762
1763 /* SCIFA6 */
1764 GPIO_FN(SCIFA6_SCK), GPIO_FN(SCIFA6_RXD), GPIO_FN(SCIFA6_TXD),
1765
1766 /* SCIFA7 */
1767 GPIO_FN(SCIFA7_TXD), GPIO_FN(SCIFA7_RXD),
1768
1769 /* SCIFAB */
1770 GPIO_FN(SCIFB_SCK_PORT190), /* MSEL5CR_17_0 */
1771 GPIO_FN(SCIFB_RXD_PORT191),
1772 GPIO_FN(SCIFB_TXD_PORT192),
1773 GPIO_FN(SCIFB_RTS_PORT186),
1774 GPIO_FN(SCIFB_CTS_PORT187),
1775
1776 GPIO_FN(SCIFB_SCK_PORT2), /* MSEL5CR_17_1 */
1777 GPIO_FN(SCIFB_RXD_PORT3),
1778 GPIO_FN(SCIFB_TXD_PORT4),
1779 GPIO_FN(SCIFB_RTS_PORT172),
1780 GPIO_FN(SCIFB_CTS_PORT173),
1781
1782 /* LCD0 */
1783 GPIO_FN(LCD0_D0), GPIO_FN(LCD0_D1), GPIO_FN(LCD0_D2),
1784 GPIO_FN(LCD0_D3), GPIO_FN(LCD0_D4), GPIO_FN(LCD0_D5),
1785 GPIO_FN(LCD0_D6), GPIO_FN(LCD0_D7), GPIO_FN(LCD0_D8),
1786 GPIO_FN(LCD0_D9), GPIO_FN(LCD0_D10), GPIO_FN(LCD0_D11),
1787 GPIO_FN(LCD0_D12), GPIO_FN(LCD0_D13), GPIO_FN(LCD0_D14),
1788 GPIO_FN(LCD0_D15), GPIO_FN(LCD0_D16), GPIO_FN(LCD0_D17),
1789 GPIO_FN(LCD0_DON), GPIO_FN(LCD0_VCPWC), GPIO_FN(LCD0_VEPWC),
1790 GPIO_FN(LCD0_DCK), GPIO_FN(LCD0_VSYN),
1791 GPIO_FN(LCD0_HSYN), GPIO_FN(LCD0_DISP),
1792 GPIO_FN(LCD0_WR), GPIO_FN(LCD0_RD),
1793 GPIO_FN(LCD0_CS), GPIO_FN(LCD0_RS),
1794
1795 GPIO_FN(LCD0_D18_PORT163), GPIO_FN(LCD0_D19_PORT162),
1796 GPIO_FN(LCD0_D20_PORT161), GPIO_FN(LCD0_D21_PORT158),
1797 GPIO_FN(LCD0_D22_PORT160), GPIO_FN(LCD0_D23_PORT159),
1798 GPIO_FN(LCD0_LCLK_PORT165), /* MSEL5CR_6_1 */
1799
1800 GPIO_FN(LCD0_D18_PORT40), GPIO_FN(LCD0_D19_PORT4),
1801 GPIO_FN(LCD0_D20_PORT3), GPIO_FN(LCD0_D21_PORT2),
1802 GPIO_FN(LCD0_D22_PORT0), GPIO_FN(LCD0_D23_PORT1),
1803 GPIO_FN(LCD0_LCLK_PORT102), /* MSEL5CR_6_0 */
1804
1805 /* LCD1 */
1806 GPIO_FN(LCD1_D0), GPIO_FN(LCD1_D1), GPIO_FN(LCD1_D2),
1807 GPIO_FN(LCD1_D3), GPIO_FN(LCD1_D4), GPIO_FN(LCD1_D5),
1808 GPIO_FN(LCD1_D6), GPIO_FN(LCD1_D7), GPIO_FN(LCD1_D8),
1809 GPIO_FN(LCD1_D9), GPIO_FN(LCD1_D10), GPIO_FN(LCD1_D11),
1810 GPIO_FN(LCD1_D12), GPIO_FN(LCD1_D13), GPIO_FN(LCD1_D14),
1811 GPIO_FN(LCD1_D15), GPIO_FN(LCD1_D16), GPIO_FN(LCD1_D17),
1812 GPIO_FN(LCD1_D18), GPIO_FN(LCD1_D19), GPIO_FN(LCD1_D20),
1813 GPIO_FN(LCD1_D21), GPIO_FN(LCD1_D22), GPIO_FN(LCD1_D23),
1814 GPIO_FN(LCD1_RS), GPIO_FN(LCD1_RD), GPIO_FN(LCD1_CS),
1815 GPIO_FN(LCD1_WR), GPIO_FN(LCD1_DCK), GPIO_FN(LCD1_DON),
1816 GPIO_FN(LCD1_VCPWC), GPIO_FN(LCD1_LCLK), GPIO_FN(LCD1_HSYN),
1817 GPIO_FN(LCD1_VSYN), GPIO_FN(LCD1_VEPWC), GPIO_FN(LCD1_DISP),
1818
1819 /* RSPI */
1820 GPIO_FN(RSPI_SSL0_A), GPIO_FN(RSPI_SSL1_A), GPIO_FN(RSPI_SSL2_A),
1821 GPIO_FN(RSPI_SSL3_A), GPIO_FN(RSPI_CK_A), GPIO_FN(RSPI_MOSI_A),
1822 GPIO_FN(RSPI_MISO_A),
1823
1824 /* VIO CKO */
1825 GPIO_FN(VIO_CKO1),
1826 GPIO_FN(VIO_CKO2),
1827 GPIO_FN(VIO_CKO_1),
1828 GPIO_FN(VIO_CKO),
1829
1830 /* VIO0 */
1831 GPIO_FN(VIO0_D0), GPIO_FN(VIO0_D1), GPIO_FN(VIO0_D2),
1832 GPIO_FN(VIO0_D3), GPIO_FN(VIO0_D4), GPIO_FN(VIO0_D5),
1833 GPIO_FN(VIO0_D6), GPIO_FN(VIO0_D7), GPIO_FN(VIO0_D8),
1834 GPIO_FN(VIO0_D9), GPIO_FN(VIO0_D10), GPIO_FN(VIO0_D11),
1835 GPIO_FN(VIO0_D12), GPIO_FN(VIO0_VD), GPIO_FN(VIO0_HD),
1836 GPIO_FN(VIO0_CLK), GPIO_FN(VIO0_FIELD),
1837
1838 GPIO_FN(VIO0_D13_PORT26), /* MSEL5CR_27_0 */
1839 GPIO_FN(VIO0_D14_PORT25),
1840 GPIO_FN(VIO0_D15_PORT24),
1841
1842 GPIO_FN(VIO0_D13_PORT22), /* MSEL5CR_27_1 */
1843 GPIO_FN(VIO0_D14_PORT95),
1844 GPIO_FN(VIO0_D15_PORT96),
1845
1846 /* VIO1 */
1847 GPIO_FN(VIO1_D0), GPIO_FN(VIO1_D1), GPIO_FN(VIO1_D2),
1848 GPIO_FN(VIO1_D3), GPIO_FN(VIO1_D4), GPIO_FN(VIO1_D5),
1849 GPIO_FN(VIO1_D6), GPIO_FN(VIO1_D7), GPIO_FN(VIO1_VD),
1850 GPIO_FN(VIO1_HD), GPIO_FN(VIO1_CLK), GPIO_FN(VIO1_FIELD),
1851
1852 /* TPU0 */
1853 GPIO_FN(TPU0TO0), GPIO_FN(TPU0TO1), GPIO_FN(TPU0TO3),
1854 GPIO_FN(TPU0TO2_PORT66), /* TPU0TO2 Port 66/202 */
1855 GPIO_FN(TPU0TO2_PORT202),
1856
1857 /* SSP1 0 */
1858 GPIO_FN(STP0_IPD0), GPIO_FN(STP0_IPD1), GPIO_FN(STP0_IPD2),
1859 GPIO_FN(STP0_IPD3), GPIO_FN(STP0_IPD4), GPIO_FN(STP0_IPD5),
1860 GPIO_FN(STP0_IPD6), GPIO_FN(STP0_IPD7), GPIO_FN(STP0_IPEN),
1861 GPIO_FN(STP0_IPCLK), GPIO_FN(STP0_IPSYNC),
1862
1863 /* SSP1 1 */
1864 GPIO_FN(STP1_IPD1), GPIO_FN(STP1_IPD2), GPIO_FN(STP1_IPD3),
1865 GPIO_FN(STP1_IPD4), GPIO_FN(STP1_IPD5), GPIO_FN(STP1_IPD6),
1866 GPIO_FN(STP1_IPD7), GPIO_FN(STP1_IPCLK), GPIO_FN(STP1_IPSYNC),
1867
1868 GPIO_FN(STP1_IPD0_PORT186), /* MSEL5CR_23_0 */
1869 GPIO_FN(STP1_IPEN_PORT187),
1870
1871 GPIO_FN(STP1_IPD0_PORT194), /* MSEL5CR_23_1 */
1872 GPIO_FN(STP1_IPEN_PORT193),
1873
1874 /* SIM */
1875 GPIO_FN(SIM_RST), GPIO_FN(SIM_CLK),
1876 GPIO_FN(SIM_D_PORT22), /* SIM_D Port 22/199 */
1877 GPIO_FN(SIM_D_PORT199),
1878
1879 /* SDHI0 */
1880 GPIO_FN(SDHI0_D0), GPIO_FN(SDHI0_D1), GPIO_FN(SDHI0_D2),
1881 GPIO_FN(SDHI0_D3), GPIO_FN(SDHI0_CD), GPIO_FN(SDHI0_WP),
1882 GPIO_FN(SDHI0_CMD), GPIO_FN(SDHI0_CLK),
1883
1884 /* SDHI1 */
1885 GPIO_FN(SDHI1_D0), GPIO_FN(SDHI1_D1), GPIO_FN(SDHI1_D2),
1886 GPIO_FN(SDHI1_D3), GPIO_FN(SDHI1_CD), GPIO_FN(SDHI1_WP),
1887 GPIO_FN(SDHI1_CMD), GPIO_FN(SDHI1_CLK),
1888
1889 /* SDHI2 */
1890 GPIO_FN(SDHI2_D0), GPIO_FN(SDHI2_D1), GPIO_FN(SDHI2_D2),
1891 GPIO_FN(SDHI2_D3), GPIO_FN(SDHI2_CLK), GPIO_FN(SDHI2_CMD),
1892
1893 GPIO_FN(SDHI2_CD_PORT24), /* MSEL5CR_19_0 */
1894 GPIO_FN(SDHI2_WP_PORT25),
1895
1896 GPIO_FN(SDHI2_WP_PORT177), /* MSEL5CR_19_1 */
1897 GPIO_FN(SDHI2_CD_PORT202),
1898
1899 /* MSIOF2 */
1900 GPIO_FN(MSIOF2_TXD), GPIO_FN(MSIOF2_RXD), GPIO_FN(MSIOF2_TSCK),
1901 GPIO_FN(MSIOF2_SS2), GPIO_FN(MSIOF2_TSYNC), GPIO_FN(MSIOF2_SS1),
1902 GPIO_FN(MSIOF2_MCK1), GPIO_FN(MSIOF2_MCK0), GPIO_FN(MSIOF2_RSYNC),
1903 GPIO_FN(MSIOF2_RSCK),
1904
1905 /* KEYSC */
1906 GPIO_FN(KEYIN4), GPIO_FN(KEYIN5),
1907 GPIO_FN(KEYIN6), GPIO_FN(KEYIN7),
1908 GPIO_FN(KEYOUT0), GPIO_FN(KEYOUT1), GPIO_FN(KEYOUT2),
1909 GPIO_FN(KEYOUT3), GPIO_FN(KEYOUT4), GPIO_FN(KEYOUT5),
1910 GPIO_FN(KEYOUT6), GPIO_FN(KEYOUT7),
1911
1912 GPIO_FN(KEYIN0_PORT43), /* MSEL4CR_18_0 */
1913 GPIO_FN(KEYIN1_PORT44),
1914 GPIO_FN(KEYIN2_PORT45),
1915 GPIO_FN(KEYIN3_PORT46),
1916
1917 GPIO_FN(KEYIN0_PORT58), /* MSEL4CR_18_1 */
1918 GPIO_FN(KEYIN1_PORT57),
1919 GPIO_FN(KEYIN2_PORT56),
1920 GPIO_FN(KEYIN3_PORT55),
1921
1922 /* VOU */
1923 GPIO_FN(DV_D0), GPIO_FN(DV_D1), GPIO_FN(DV_D2),
1924 GPIO_FN(DV_D3), GPIO_FN(DV_D4), GPIO_FN(DV_D5),
1925 GPIO_FN(DV_D6), GPIO_FN(DV_D7), GPIO_FN(DV_D8),
1926 GPIO_FN(DV_D9), GPIO_FN(DV_D10), GPIO_FN(DV_D11),
1927 GPIO_FN(DV_D12), GPIO_FN(DV_D13), GPIO_FN(DV_D14),
1928 GPIO_FN(DV_D15), GPIO_FN(DV_CLK),
1929 GPIO_FN(DV_VSYNC), GPIO_FN(DV_HSYNC),
1930
1931 /* MEMC */
1932 GPIO_FN(MEMC_AD0), GPIO_FN(MEMC_AD1), GPIO_FN(MEMC_AD2),
1933 GPIO_FN(MEMC_AD3), GPIO_FN(MEMC_AD4), GPIO_FN(MEMC_AD5),
1934 GPIO_FN(MEMC_AD6), GPIO_FN(MEMC_AD7), GPIO_FN(MEMC_AD8),
1935 GPIO_FN(MEMC_AD9), GPIO_FN(MEMC_AD10), GPIO_FN(MEMC_AD11),
1936 GPIO_FN(MEMC_AD12), GPIO_FN(MEMC_AD13), GPIO_FN(MEMC_AD14),
1937 GPIO_FN(MEMC_AD15), GPIO_FN(MEMC_CS0), GPIO_FN(MEMC_INT),
1938 GPIO_FN(MEMC_NWE), GPIO_FN(MEMC_NOE), GPIO_FN(MEMC_CS1),
1939 GPIO_FN(MEMC_A1), GPIO_FN(MEMC_ADV), GPIO_FN(MEMC_DREQ0),
1940 GPIO_FN(MEMC_WAIT), GPIO_FN(MEMC_DREQ1), GPIO_FN(MEMC_BUSCLK),
1941 GPIO_FN(MEMC_A0),
1942
1943 /* MMC */
1944 GPIO_FN(MMC0_D0_PORT68), GPIO_FN(MMC0_D1_PORT69),
1945 GPIO_FN(MMC0_D2_PORT70), GPIO_FN(MMC0_D3_PORT71),
1946 GPIO_FN(MMC0_D4_PORT72), GPIO_FN(MMC0_D5_PORT73),
1947 GPIO_FN(MMC0_D6_PORT74), GPIO_FN(MMC0_D7_PORT75),
1948 GPIO_FN(MMC0_CLK_PORT66),
1949 GPIO_FN(MMC0_CMD_PORT67), /* MSEL4CR_15_0 */
1950
1951 GPIO_FN(MMC1_D0_PORT149), GPIO_FN(MMC1_D1_PORT148),
1952 GPIO_FN(MMC1_D2_PORT147), GPIO_FN(MMC1_D3_PORT146),
1953 GPIO_FN(MMC1_D4_PORT145), GPIO_FN(MMC1_D5_PORT144),
1954 GPIO_FN(MMC1_D6_PORT143), GPIO_FN(MMC1_D7_PORT142),
1955 GPIO_FN(MMC1_CLK_PORT103),
1956 GPIO_FN(MMC1_CMD_PORT104), /* MSEL4CR_15_1 */
1957
1958 /* MSIOF0 */
1959 GPIO_FN(MSIOF0_SS1), GPIO_FN(MSIOF0_SS2), GPIO_FN(MSIOF0_RXD),
1960 GPIO_FN(MSIOF0_TXD), GPIO_FN(MSIOF0_MCK0), GPIO_FN(MSIOF0_MCK1),
1961 GPIO_FN(MSIOF0_RSYNC), GPIO_FN(MSIOF0_RSCK), GPIO_FN(MSIOF0_TSCK),
1962 GPIO_FN(MSIOF0_TSYNC),
1963
1964 /* MSIOF1 */
1965 GPIO_FN(MSIOF1_RSCK), GPIO_FN(MSIOF1_RSYNC),
1966 GPIO_FN(MSIOF1_MCK0), GPIO_FN(MSIOF1_MCK1),
1967
1968 GPIO_FN(MSIOF1_SS2_PORT116), GPIO_FN(MSIOF1_SS1_PORT117),
1969 GPIO_FN(MSIOF1_RXD_PORT118), GPIO_FN(MSIOF1_TXD_PORT119),
1970 GPIO_FN(MSIOF1_TSYNC_PORT120),
1971 GPIO_FN(MSIOF1_TSCK_PORT121), /* MSEL4CR_10_0 */
1972
1973 GPIO_FN(MSIOF1_SS1_PORT67), GPIO_FN(MSIOF1_TSCK_PORT72),
1974 GPIO_FN(MSIOF1_TSYNC_PORT73), GPIO_FN(MSIOF1_TXD_PORT74),
1975 GPIO_FN(MSIOF1_RXD_PORT75),
1976 GPIO_FN(MSIOF1_SS2_PORT202), /* MSEL4CR_10_1 */
1977
1978 /* GPIO */
1979 GPIO_FN(GPO0), GPIO_FN(GPI0),
1980 GPIO_FN(GPO1), GPIO_FN(GPI1),
1981
1982 /* USB0 */
1983 GPIO_FN(USB0_OCI), GPIO_FN(USB0_PPON), GPIO_FN(VBUS),
1984
1985 /* USB1 */
1986 GPIO_FN(USB1_OCI), GPIO_FN(USB1_PPON),
1987
1988 /* BBIF1 */
1989 GPIO_FN(BBIF1_RXD), GPIO_FN(BBIF1_TXD), GPIO_FN(BBIF1_TSYNC),
1990 GPIO_FN(BBIF1_TSCK), GPIO_FN(BBIF1_RSCK), GPIO_FN(BBIF1_RSYNC),
1991 GPIO_FN(BBIF1_FLOW), GPIO_FN(BBIF1_RX_FLOW_N),
1992
1993 /* BBIF2 */
1994 GPIO_FN(BBIF2_TXD2_PORT5), /* MSEL5CR_0_0 */
1995 GPIO_FN(BBIF2_RXD2_PORT60),
1996 GPIO_FN(BBIF2_TSYNC2_PORT6),
1997 GPIO_FN(BBIF2_TSCK2_PORT59),
1998
1999 GPIO_FN(BBIF2_RXD2_PORT90), /* MSEL5CR_0_1 */
2000 GPIO_FN(BBIF2_TXD2_PORT183),
2001 GPIO_FN(BBIF2_TSCK2_PORT89),
2002 GPIO_FN(BBIF2_TSYNC2_PORT184),
2003
2004 /* BSC / FLCTL / PCMCIA */
2005 GPIO_FN(CS0), GPIO_FN(CS2), GPIO_FN(CS4),
2006 GPIO_FN(CS5B), GPIO_FN(CS6A),
2007 GPIO_FN(CS5A_PORT105), /* CS5A PORT 19/105 */
2008 GPIO_FN(CS5A_PORT19),
2009 GPIO_FN(IOIS16), /* ? */
2010
2011 GPIO_FN(A0), GPIO_FN(A1), GPIO_FN(A2), GPIO_FN(A3),
2012 GPIO_FN(A4_FOE), GPIO_FN(A5_FCDE), /* share with FLCTL */
2013 GPIO_FN(A6), GPIO_FN(A7), GPIO_FN(A8), GPIO_FN(A9),
2014 GPIO_FN(A10), GPIO_FN(A11), GPIO_FN(A12), GPIO_FN(A13),
2015 GPIO_FN(A14), GPIO_FN(A15), GPIO_FN(A16), GPIO_FN(A17),
2016 GPIO_FN(A18), GPIO_FN(A19), GPIO_FN(A20), GPIO_FN(A21),
2017 GPIO_FN(A22), GPIO_FN(A23), GPIO_FN(A24), GPIO_FN(A25),
2018 GPIO_FN(A26),
2019
2020 GPIO_FN(D0_NAF0), GPIO_FN(D1_NAF1), /* share with FLCTL */
2021 GPIO_FN(D2_NAF2), GPIO_FN(D3_NAF3), /* share with FLCTL */
2022 GPIO_FN(D4_NAF4), GPIO_FN(D5_NAF5), /* share with FLCTL */
2023 GPIO_FN(D6_NAF6), GPIO_FN(D7_NAF7), /* share with FLCTL */
2024 GPIO_FN(D8_NAF8), GPIO_FN(D9_NAF9), /* share with FLCTL */
2025 GPIO_FN(D10_NAF10), GPIO_FN(D11_NAF11), /* share with FLCTL */
2026 GPIO_FN(D12_NAF12), GPIO_FN(D13_NAF13), /* share with FLCTL */
2027 GPIO_FN(D14_NAF14), GPIO_FN(D15_NAF15), /* share with FLCTL */
2028 GPIO_FN(D16), GPIO_FN(D17), GPIO_FN(D18), GPIO_FN(D19),
2029 GPIO_FN(D20), GPIO_FN(D21), GPIO_FN(D22), GPIO_FN(D23),
2030 GPIO_FN(D24), GPIO_FN(D25), GPIO_FN(D26), GPIO_FN(D27),
2031 GPIO_FN(D28), GPIO_FN(D29), GPIO_FN(D30), GPIO_FN(D31),
2032
2033 GPIO_FN(WE0_FWE), /* share with FLCTL */
2034 GPIO_FN(WE1),
2035 GPIO_FN(WE2_ICIORD), /* share with PCMCIA */
2036 GPIO_FN(WE3_ICIOWR), /* share with PCMCIA */
2037 GPIO_FN(CKO), GPIO_FN(BS), GPIO_FN(RDWR),
2038 GPIO_FN(RD_FSC), /* share with FLCTL */
2039 GPIO_FN(WAIT_PORT177), /* WAIT Port 90/177 */
2040 GPIO_FN(WAIT_PORT90),
2041
2042 GPIO_FN(FCE0), GPIO_FN(FCE1), GPIO_FN(FRB), /* FLCTL */
2043
2044 /* IRDA */
2045 GPIO_FN(IRDA_FIRSEL), GPIO_FN(IRDA_IN), GPIO_FN(IRDA_OUT),
2046
2047 /* ATAPI */
2048 GPIO_FN(IDE_D0), GPIO_FN(IDE_D1), GPIO_FN(IDE_D2),
2049 GPIO_FN(IDE_D3), GPIO_FN(IDE_D4), GPIO_FN(IDE_D5),
2050 GPIO_FN(IDE_D6), GPIO_FN(IDE_D7), GPIO_FN(IDE_D8),
2051 GPIO_FN(IDE_D9), GPIO_FN(IDE_D10), GPIO_FN(IDE_D11),
2052 GPIO_FN(IDE_D12), GPIO_FN(IDE_D13), GPIO_FN(IDE_D14),
2053 GPIO_FN(IDE_D15), GPIO_FN(IDE_A0), GPIO_FN(IDE_A1),
2054 GPIO_FN(IDE_A2), GPIO_FN(IDE_CS0), GPIO_FN(IDE_CS1),
2055 GPIO_FN(IDE_IOWR), GPIO_FN(IDE_IORD), GPIO_FN(IDE_IORDY),
2056 GPIO_FN(IDE_INT), GPIO_FN(IDE_RST), GPIO_FN(IDE_DIRECTION),
2057 GPIO_FN(IDE_EXBUF_ENB), GPIO_FN(IDE_IODACK), GPIO_FN(IDE_IODREQ),
2058
2059 /* RMII */
2060 GPIO_FN(RMII_CRS_DV), GPIO_FN(RMII_RX_ER), GPIO_FN(RMII_RXD0),
2061 GPIO_FN(RMII_RXD1), GPIO_FN(RMII_TX_EN), GPIO_FN(RMII_TXD0),
2062 GPIO_FN(RMII_MDC), GPIO_FN(RMII_TXD1), GPIO_FN(RMII_MDIO),
2063 GPIO_FN(RMII_REF50CK), GPIO_FN(RMII_REF125CK), /* for GMII */
2064
2065 /* GEther */
2066 GPIO_FN(ET_TX_CLK), GPIO_FN(ET_TX_EN), GPIO_FN(ET_ETXD0),
2067 GPIO_FN(ET_ETXD1), GPIO_FN(ET_ETXD2), GPIO_FN(ET_ETXD3),
2068 GPIO_FN(ET_ETXD4), GPIO_FN(ET_ETXD5), /* for GEther */
2069 GPIO_FN(ET_ETXD6), GPIO_FN(ET_ETXD7), /* for GEther */
2070 GPIO_FN(ET_COL), GPIO_FN(ET_TX_ER), GPIO_FN(ET_RX_CLK),
2071 GPIO_FN(ET_RX_DV), GPIO_FN(ET_ERXD0), GPIO_FN(ET_ERXD1),
2072 GPIO_FN(ET_ERXD2), GPIO_FN(ET_ERXD3),
2073 GPIO_FN(ET_ERXD4), GPIO_FN(ET_ERXD5), /* for GEther */
2074 GPIO_FN(ET_ERXD6), GPIO_FN(ET_ERXD7), /* for GEther */
2075 GPIO_FN(ET_RX_ER), GPIO_FN(ET_CRS), GPIO_FN(ET_MDC),
2076 GPIO_FN(ET_MDIO), GPIO_FN(ET_LINK), GPIO_FN(ET_PHY_INT),
2077 GPIO_FN(ET_WOL), GPIO_FN(ET_GTX_CLK),
2078
2079 /* DMA0 */
2080 GPIO_FN(DREQ0), GPIO_FN(DACK0),
2081
2082 /* DMA1 */
2083 GPIO_FN(DREQ1), GPIO_FN(DACK1),
2084
2085 /* SYSC */
2086 GPIO_FN(RESETOUTS),
2087
2088 /* IRREM */
2089 GPIO_FN(IROUT),
2090
2091 /* LCDC */
2092 GPIO_FN(LCDC0_SELECT),
2093 GPIO_FN(LCDC1_SELECT),
2094
2095 /* SDENC */
2096 GPIO_FN(SDENC_CPG),
2097 GPIO_FN(SDENC_DV_CLKI),
2098
2099 /* SYSC */
2100 GPIO_FN(RESETP_PULLUP),
2101 GPIO_FN(RESETP_PLAIN),
2102
2103 /* DEBUG */
2104 GPIO_FN(EDEBGREQ_PULLDOWN),
2105 GPIO_FN(EDEBGREQ_PULLUP),
2106
2107 GPIO_FN(TRACEAUD_FROM_VIO),
2108 GPIO_FN(TRACEAUD_FROM_LCDC0),
2109 GPIO_FN(TRACEAUD_FROM_MEMC),
2110};
2111
2112static struct pinmux_cfg_reg pinmux_config_regs[] = {
2113 PORTCR(0, 0xe6050000), /* PORT0CR */
2114 PORTCR(1, 0xe6050001), /* PORT1CR */
2115 PORTCR(2, 0xe6050002), /* PORT2CR */
2116 PORTCR(3, 0xe6050003), /* PORT3CR */
2117 PORTCR(4, 0xe6050004), /* PORT4CR */
2118 PORTCR(5, 0xe6050005), /* PORT5CR */
2119 PORTCR(6, 0xe6050006), /* PORT6CR */
2120 PORTCR(7, 0xe6050007), /* PORT7CR */
2121 PORTCR(8, 0xe6050008), /* PORT8CR */
2122 PORTCR(9, 0xe6050009), /* PORT9CR */
2123 PORTCR(10, 0xe605000a), /* PORT10CR */
2124 PORTCR(11, 0xe605000b), /* PORT11CR */
2125 PORTCR(12, 0xe605000c), /* PORT12CR */
2126 PORTCR(13, 0xe605000d), /* PORT13CR */
2127 PORTCR(14, 0xe605000e), /* PORT14CR */
2128 PORTCR(15, 0xe605000f), /* PORT15CR */
2129 PORTCR(16, 0xe6050010), /* PORT16CR */
2130 PORTCR(17, 0xe6050011), /* PORT17CR */
2131 PORTCR(18, 0xe6050012), /* PORT18CR */
2132 PORTCR(19, 0xe6050013), /* PORT19CR */
2133 PORTCR(20, 0xe6050014), /* PORT20CR */
2134 PORTCR(21, 0xe6050015), /* PORT21CR */
2135 PORTCR(22, 0xe6050016), /* PORT22CR */
2136 PORTCR(23, 0xe6050017), /* PORT23CR */
2137 PORTCR(24, 0xe6050018), /* PORT24CR */
2138 PORTCR(25, 0xe6050019), /* PORT25CR */
2139 PORTCR(26, 0xe605001a), /* PORT26CR */
2140 PORTCR(27, 0xe605001b), /* PORT27CR */
2141 PORTCR(28, 0xe605001c), /* PORT28CR */
2142 PORTCR(29, 0xe605001d), /* PORT29CR */
2143 PORTCR(30, 0xe605001e), /* PORT30CR */
2144 PORTCR(31, 0xe605001f), /* PORT31CR */
2145 PORTCR(32, 0xe6050020), /* PORT32CR */
2146 PORTCR(33, 0xe6050021), /* PORT33CR */
2147 PORTCR(34, 0xe6050022), /* PORT34CR */
2148 PORTCR(35, 0xe6050023), /* PORT35CR */
2149 PORTCR(36, 0xe6050024), /* PORT36CR */
2150 PORTCR(37, 0xe6050025), /* PORT37CR */
2151 PORTCR(38, 0xe6050026), /* PORT38CR */
2152 PORTCR(39, 0xe6050027), /* PORT39CR */
2153 PORTCR(40, 0xe6050028), /* PORT40CR */
2154 PORTCR(41, 0xe6050029), /* PORT41CR */
2155 PORTCR(42, 0xe605002a), /* PORT42CR */
2156 PORTCR(43, 0xe605002b), /* PORT43CR */
2157 PORTCR(44, 0xe605002c), /* PORT44CR */
2158 PORTCR(45, 0xe605002d), /* PORT45CR */
2159 PORTCR(46, 0xe605002e), /* PORT46CR */
2160 PORTCR(47, 0xe605002f), /* PORT47CR */
2161 PORTCR(48, 0xe6050030), /* PORT48CR */
2162 PORTCR(49, 0xe6050031), /* PORT49CR */
2163 PORTCR(50, 0xe6050032), /* PORT50CR */
2164 PORTCR(51, 0xe6050033), /* PORT51CR */
2165 PORTCR(52, 0xe6050034), /* PORT52CR */
2166 PORTCR(53, 0xe6050035), /* PORT53CR */
2167 PORTCR(54, 0xe6050036), /* PORT54CR */
2168 PORTCR(55, 0xe6050037), /* PORT55CR */
2169 PORTCR(56, 0xe6050038), /* PORT56CR */
2170 PORTCR(57, 0xe6050039), /* PORT57CR */
2171 PORTCR(58, 0xe605003a), /* PORT58CR */
2172 PORTCR(59, 0xe605003b), /* PORT59CR */
2173 PORTCR(60, 0xe605003c), /* PORT60CR */
2174 PORTCR(61, 0xe605003d), /* PORT61CR */
2175 PORTCR(62, 0xe605003e), /* PORT62CR */
2176 PORTCR(63, 0xe605003f), /* PORT63CR */
2177 PORTCR(64, 0xe6050040), /* PORT64CR */
2178 PORTCR(65, 0xe6050041), /* PORT65CR */
2179 PORTCR(66, 0xe6050042), /* PORT66CR */
2180 PORTCR(67, 0xe6050043), /* PORT67CR */
2181 PORTCR(68, 0xe6050044), /* PORT68CR */
2182 PORTCR(69, 0xe6050045), /* PORT69CR */
2183 PORTCR(70, 0xe6050046), /* PORT70CR */
2184 PORTCR(71, 0xe6050047), /* PORT71CR */
2185 PORTCR(72, 0xe6050048), /* PORT72CR */
2186 PORTCR(73, 0xe6050049), /* PORT73CR */
2187 PORTCR(74, 0xe605004a), /* PORT74CR */
2188 PORTCR(75, 0xe605004b), /* PORT75CR */
2189 PORTCR(76, 0xe605004c), /* PORT76CR */
2190 PORTCR(77, 0xe605004d), /* PORT77CR */
2191 PORTCR(78, 0xe605004e), /* PORT78CR */
2192 PORTCR(79, 0xe605004f), /* PORT79CR */
2193 PORTCR(80, 0xe6050050), /* PORT80CR */
2194 PORTCR(81, 0xe6050051), /* PORT81CR */
2195 PORTCR(82, 0xe6050052), /* PORT82CR */
2196 PORTCR(83, 0xe6050053), /* PORT83CR */
2197
2198 PORTCR(84, 0xe6051054), /* PORT84CR */
2199 PORTCR(85, 0xe6051055), /* PORT85CR */
2200 PORTCR(86, 0xe6051056), /* PORT86CR */
2201 PORTCR(87, 0xe6051057), /* PORT87CR */
2202 PORTCR(88, 0xe6051058), /* PORT88CR */
2203 PORTCR(89, 0xe6051059), /* PORT89CR */
2204 PORTCR(90, 0xe605105a), /* PORT90CR */
2205 PORTCR(91, 0xe605105b), /* PORT91CR */
2206 PORTCR(92, 0xe605105c), /* PORT92CR */
2207 PORTCR(93, 0xe605105d), /* PORT93CR */
2208 PORTCR(94, 0xe605105e), /* PORT94CR */
2209 PORTCR(95, 0xe605105f), /* PORT95CR */
2210 PORTCR(96, 0xe6051060), /* PORT96CR */
2211 PORTCR(97, 0xe6051061), /* PORT97CR */
2212 PORTCR(98, 0xe6051062), /* PORT98CR */
2213 PORTCR(99, 0xe6051063), /* PORT99CR */
2214 PORTCR(100, 0xe6051064), /* PORT100CR */
2215 PORTCR(101, 0xe6051065), /* PORT101CR */
2216 PORTCR(102, 0xe6051066), /* PORT102CR */
2217 PORTCR(103, 0xe6051067), /* PORT103CR */
2218 PORTCR(104, 0xe6051068), /* PORT104CR */
2219 PORTCR(105, 0xe6051069), /* PORT105CR */
2220 PORTCR(106, 0xe605106a), /* PORT106CR */
2221 PORTCR(107, 0xe605106b), /* PORT107CR */
2222 PORTCR(108, 0xe605106c), /* PORT108CR */
2223 PORTCR(109, 0xe605106d), /* PORT109CR */
2224 PORTCR(110, 0xe605106e), /* PORT110CR */
2225 PORTCR(111, 0xe605106f), /* PORT111CR */
2226 PORTCR(112, 0xe6051070), /* PORT112CR */
2227 PORTCR(113, 0xe6051071), /* PORT113CR */
2228 PORTCR(114, 0xe6051072), /* PORT114CR */
2229
2230 PORTCR(115, 0xe6052073), /* PORT115CR */
2231 PORTCR(116, 0xe6052074), /* PORT116CR */
2232 PORTCR(117, 0xe6052075), /* PORT117CR */
2233 PORTCR(118, 0xe6052076), /* PORT118CR */
2234 PORTCR(119, 0xe6052077), /* PORT119CR */
2235 PORTCR(120, 0xe6052078), /* PORT120CR */
2236 PORTCR(121, 0xe6052079), /* PORT121CR */
2237 PORTCR(122, 0xe605207a), /* PORT122CR */
2238 PORTCR(123, 0xe605207b), /* PORT123CR */
2239 PORTCR(124, 0xe605207c), /* PORT124CR */
2240 PORTCR(125, 0xe605207d), /* PORT125CR */
2241 PORTCR(126, 0xe605207e), /* PORT126CR */
2242 PORTCR(127, 0xe605207f), /* PORT127CR */
2243 PORTCR(128, 0xe6052080), /* PORT128CR */
2244 PORTCR(129, 0xe6052081), /* PORT129CR */
2245 PORTCR(130, 0xe6052082), /* PORT130CR */
2246 PORTCR(131, 0xe6052083), /* PORT131CR */
2247 PORTCR(132, 0xe6052084), /* PORT132CR */
2248 PORTCR(133, 0xe6052085), /* PORT133CR */
2249 PORTCR(134, 0xe6052086), /* PORT134CR */
2250 PORTCR(135, 0xe6052087), /* PORT135CR */
2251 PORTCR(136, 0xe6052088), /* PORT136CR */
2252 PORTCR(137, 0xe6052089), /* PORT137CR */
2253 PORTCR(138, 0xe605208a), /* PORT138CR */
2254 PORTCR(139, 0xe605208b), /* PORT139CR */
2255 PORTCR(140, 0xe605208c), /* PORT140CR */
2256 PORTCR(141, 0xe605208d), /* PORT141CR */
2257 PORTCR(142, 0xe605208e), /* PORT142CR */
2258 PORTCR(143, 0xe605208f), /* PORT143CR */
2259 PORTCR(144, 0xe6052090), /* PORT144CR */
2260 PORTCR(145, 0xe6052091), /* PORT145CR */
2261 PORTCR(146, 0xe6052092), /* PORT146CR */
2262 PORTCR(147, 0xe6052093), /* PORT147CR */
2263 PORTCR(148, 0xe6052094), /* PORT148CR */
2264 PORTCR(149, 0xe6052095), /* PORT149CR */
2265 PORTCR(150, 0xe6052096), /* PORT150CR */
2266 PORTCR(151, 0xe6052097), /* PORT151CR */
2267 PORTCR(152, 0xe6052098), /* PORT152CR */
2268 PORTCR(153, 0xe6052099), /* PORT153CR */
2269 PORTCR(154, 0xe605209a), /* PORT154CR */
2270 PORTCR(155, 0xe605209b), /* PORT155CR */
2271 PORTCR(156, 0xe605209c), /* PORT156CR */
2272 PORTCR(157, 0xe605209d), /* PORT157CR */
2273 PORTCR(158, 0xe605209e), /* PORT158CR */
2274 PORTCR(159, 0xe605209f), /* PORT159CR */
2275 PORTCR(160, 0xe60520a0), /* PORT160CR */
2276 PORTCR(161, 0xe60520a1), /* PORT161CR */
2277 PORTCR(162, 0xe60520a2), /* PORT162CR */
2278 PORTCR(163, 0xe60520a3), /* PORT163CR */
2279 PORTCR(164, 0xe60520a4), /* PORT164CR */
2280 PORTCR(165, 0xe60520a5), /* PORT165CR */
2281 PORTCR(166, 0xe60520a6), /* PORT166CR */
2282 PORTCR(167, 0xe60520a7), /* PORT167CR */
2283 PORTCR(168, 0xe60520a8), /* PORT168CR */
2284 PORTCR(169, 0xe60520a9), /* PORT169CR */
2285 PORTCR(170, 0xe60520aa), /* PORT170CR */
2286 PORTCR(171, 0xe60520ab), /* PORT171CR */
2287 PORTCR(172, 0xe60520ac), /* PORT172CR */
2288 PORTCR(173, 0xe60520ad), /* PORT173CR */
2289 PORTCR(174, 0xe60520ae), /* PORT174CR */
2290 PORTCR(175, 0xe60520af), /* PORT175CR */
2291 PORTCR(176, 0xe60520b0), /* PORT176CR */
2292 PORTCR(177, 0xe60520b1), /* PORT177CR */
2293 PORTCR(178, 0xe60520b2), /* PORT178CR */
2294 PORTCR(179, 0xe60520b3), /* PORT179CR */
2295 PORTCR(180, 0xe60520b4), /* PORT180CR */
2296 PORTCR(181, 0xe60520b5), /* PORT181CR */
2297 PORTCR(182, 0xe60520b6), /* PORT182CR */
2298 PORTCR(183, 0xe60520b7), /* PORT183CR */
2299 PORTCR(184, 0xe60520b8), /* PORT184CR */
2300 PORTCR(185, 0xe60520b9), /* PORT185CR */
2301 PORTCR(186, 0xe60520ba), /* PORT186CR */
2302 PORTCR(187, 0xe60520bb), /* PORT187CR */
2303 PORTCR(188, 0xe60520bc), /* PORT188CR */
2304 PORTCR(189, 0xe60520bd), /* PORT189CR */
2305 PORTCR(190, 0xe60520be), /* PORT190CR */
2306 PORTCR(191, 0xe60520bf), /* PORT191CR */
2307 PORTCR(192, 0xe60520c0), /* PORT192CR */
2308 PORTCR(193, 0xe60520c1), /* PORT193CR */
2309 PORTCR(194, 0xe60520c2), /* PORT194CR */
2310 PORTCR(195, 0xe60520c3), /* PORT195CR */
2311 PORTCR(196, 0xe60520c4), /* PORT196CR */
2312 PORTCR(197, 0xe60520c5), /* PORT197CR */
2313 PORTCR(198, 0xe60520c6), /* PORT198CR */
2314 PORTCR(199, 0xe60520c7), /* PORT199CR */
2315 PORTCR(200, 0xe60520c8), /* PORT200CR */
2316 PORTCR(201, 0xe60520c9), /* PORT201CR */
2317 PORTCR(202, 0xe60520ca), /* PORT202CR */
2318 PORTCR(203, 0xe60520cb), /* PORT203CR */
2319 PORTCR(204, 0xe60520cc), /* PORT204CR */
2320 PORTCR(205, 0xe60520cd), /* PORT205CR */
2321 PORTCR(206, 0xe60520ce), /* PORT206CR */
2322 PORTCR(207, 0xe60520cf), /* PORT207CR */
2323 PORTCR(208, 0xe60520d0), /* PORT208CR */
2324 PORTCR(209, 0xe60520d1), /* PORT209CR */
2325
2326 PORTCR(210, 0xe60530d2), /* PORT210CR */
2327 PORTCR(211, 0xe60530d3), /* PORT211CR */
2328
2329 { PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1) {
2330 MSEL1CR_31_0, MSEL1CR_31_1,
2331 MSEL1CR_30_0, MSEL1CR_30_1,
2332 MSEL1CR_29_0, MSEL1CR_29_1,
2333 MSEL1CR_28_0, MSEL1CR_28_1,
2334 MSEL1CR_27_0, MSEL1CR_27_1,
2335 MSEL1CR_26_0, MSEL1CR_26_1,
2336 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2337 0, 0, 0, 0, 0, 0, 0, 0,
2338 MSEL1CR_16_0, MSEL1CR_16_1,
2339 MSEL1CR_15_0, MSEL1CR_15_1,
2340 MSEL1CR_14_0, MSEL1CR_14_1,
2341 MSEL1CR_13_0, MSEL1CR_13_1,
2342 MSEL1CR_12_0, MSEL1CR_12_1,
2343 0, 0, 0, 0,
2344 MSEL1CR_9_0, MSEL1CR_9_1,
2345 0, 0,
2346 MSEL1CR_7_0, MSEL1CR_7_1,
2347 MSEL1CR_6_0, MSEL1CR_6_1,
2348 MSEL1CR_5_0, MSEL1CR_5_1,
2349 MSEL1CR_4_0, MSEL1CR_4_1,
2350 MSEL1CR_3_0, MSEL1CR_3_1,
2351 MSEL1CR_2_0, MSEL1CR_2_1,
2352 0, 0,
2353 MSEL1CR_0_0, MSEL1CR_0_1,
2354 }
2355 },
2356 { PINMUX_CFG_REG("MSEL3CR", 0xE6058020, 32, 1) {
2357 0, 0, 0, 0, 0, 0, 0, 0,
2358 0, 0, 0, 0, 0, 0, 0, 0,
2359 0, 0, 0, 0, 0, 0, 0, 0,
2360 0, 0, 0, 0, 0, 0, 0, 0,
2361 MSEL3CR_15_0, MSEL3CR_15_1,
2362 0, 0, 0, 0, 0, 0, 0, 0,
2363 0, 0, 0, 0, 0, 0, 0, 0,
2364 MSEL3CR_6_0, MSEL3CR_6_1,
2365 0, 0, 0, 0, 0, 0, 0, 0,
2366 0, 0, 0, 0,
2367 }
2368 },
2369 { PINMUX_CFG_REG("MSEL4CR", 0xE6058024, 32, 1) {
2370 0, 0, 0, 0, 0, 0, 0, 0,
2371 0, 0, 0, 0, 0, 0, 0, 0,
2372 0, 0, 0, 0, 0, 0, 0, 0,
2373 MSEL4CR_19_0, MSEL4CR_19_1,
2374 MSEL4CR_18_0, MSEL4CR_18_1,
2375 0, 0, 0, 0,
2376 MSEL4CR_15_0, MSEL4CR_15_1,
2377 0, 0, 0, 0, 0, 0, 0, 0,
2378 MSEL4CR_10_0, MSEL4CR_10_1,
2379 0, 0, 0, 0, 0, 0,
2380 MSEL4CR_6_0, MSEL4CR_6_1,
2381 0, 0,
2382 MSEL4CR_4_0, MSEL4CR_4_1,
2383 0, 0, 0, 0,
2384 MSEL4CR_1_0, MSEL4CR_1_1,
2385 0, 0,
2386 }
2387 },
2388 { PINMUX_CFG_REG("MSEL5CR", 0xE6058028, 32, 1) {
2389 MSEL5CR_31_0, MSEL5CR_31_1,
2390 MSEL5CR_30_0, MSEL5CR_30_1,
2391 MSEL5CR_29_0, MSEL5CR_29_1,
2392 0, 0,
2393 MSEL5CR_27_0, MSEL5CR_27_1,
2394 0, 0,
2395 MSEL5CR_25_0, MSEL5CR_25_1,
2396 0, 0,
2397 MSEL5CR_23_0, MSEL5CR_23_1,
2398 0, 0,
2399 MSEL5CR_21_0, MSEL5CR_21_1,
2400 0, 0,
2401 MSEL5CR_19_0, MSEL5CR_19_1,
2402 0, 0,
2403 MSEL5CR_17_0, MSEL5CR_17_1,
2404 0, 0,
2405 MSEL5CR_15_0, MSEL5CR_15_1,
2406 MSEL5CR_14_0, MSEL5CR_14_1,
2407 MSEL5CR_13_0, MSEL5CR_13_1,
2408 MSEL5CR_12_0, MSEL5CR_12_1,
2409 MSEL5CR_11_0, MSEL5CR_11_1,
2410 MSEL5CR_10_0, MSEL5CR_10_1,
2411 0, 0,
2412 MSEL5CR_8_0, MSEL5CR_8_1,
2413 MSEL5CR_7_0, MSEL5CR_7_1,
2414 MSEL5CR_6_0, MSEL5CR_6_1,
2415 MSEL5CR_5_0, MSEL5CR_5_1,
2416 MSEL5CR_4_0, MSEL5CR_4_1,
2417 MSEL5CR_3_0, MSEL5CR_3_1,
2418 MSEL5CR_2_0, MSEL5CR_2_1,
2419 0, 0,
2420 MSEL5CR_0_0, MSEL5CR_0_1,
2421 }
2422 },
2423 { },
2424};
2425
2426static struct pinmux_data_reg pinmux_data_regs[] = {
2427 { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054800, 32) {
2428 PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
2429 PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
2430 PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
2431 PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
2432 PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
2433 PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
2434 PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
2435 PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA }
2436 },
2437 { PINMUX_DATA_REG("PORTL063_032DR", 0xe6054804, 32) {
2438 PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA,
2439 PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA,
2440 PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA,
2441 PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA,
2442 PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA,
2443 PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA,
2444 PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
2445 PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA }
2446 },
2447 { PINMUX_DATA_REG("PORTL095_064DR", 0xe6054808, 32) {
2448 0, 0, 0, 0,
2449 0, 0, 0, 0,
2450 0, 0, 0, 0,
2451 PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
2452 PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
2453 PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
2454 PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
2455 PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA }
2456 },
2457 { PINMUX_DATA_REG("PORTD095_064DR", 0xe6055808, 32) {
2458 PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA,
2459 PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA,
2460 PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA,
2461 0, 0, 0, 0,
2462 0, 0, 0, 0,
2463 0, 0, 0, 0,
2464 0, 0, 0, 0,
2465 0, 0, 0, 0 }
2466 },
2467 { PINMUX_DATA_REG("PORTD127_096DR", 0xe605580c, 32) {
2468 0, 0, 0, 0,
2469 0, 0, 0, 0,
2470 0, 0, 0, 0,
2471 0, PORT114_DATA, PORT113_DATA, PORT112_DATA,
2472 PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
2473 PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
2474 PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
2475 PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA }
2476 },
2477 { PINMUX_DATA_REG("PORTR127_096DR", 0xe605680C, 32) {
2478 PORT127_DATA, PORT126_DATA, PORT125_DATA, PORT124_DATA,
2479 PORT123_DATA, PORT122_DATA, PORT121_DATA, PORT120_DATA,
2480 PORT119_DATA, PORT118_DATA, PORT117_DATA, PORT116_DATA,
2481 PORT115_DATA, 0, 0, 0,
2482 0, 0, 0, 0,
2483 0, 0, 0, 0,
2484 0, 0, 0, 0,
2485 0, 0, 0, 0 }
2486 },
2487 { PINMUX_DATA_REG("PORTR159_128DR", 0xe6056810, 32) {
2488 PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA,
2489 PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA,
2490 PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA,
2491 PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA,
2492 PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA,
2493 PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA,
2494 PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA,
2495 PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA }
2496 },
2497 { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056814, 32) {
2498 PORT191_DATA, PORT190_DATA, PORT189_DATA, PORT188_DATA,
2499 PORT187_DATA, PORT186_DATA, PORT185_DATA, PORT184_DATA,
2500 PORT183_DATA, PORT182_DATA, PORT181_DATA, PORT180_DATA,
2501 PORT179_DATA, PORT178_DATA, PORT177_DATA, PORT176_DATA,
2502 PORT175_DATA, PORT174_DATA, PORT173_DATA, PORT172_DATA,
2503 PORT171_DATA, PORT170_DATA, PORT169_DATA, PORT168_DATA,
2504 PORT167_DATA, PORT166_DATA, PORT165_DATA, PORT164_DATA,
2505 PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA }
2506 },
2507 { PINMUX_DATA_REG("PORTR223_192DR", 0xe6056818, 32) {
2508 0, 0, 0, 0,
2509 0, 0, 0, 0,
2510 0, 0, 0, 0,
2511 0, 0, PORT209_DATA, PORT208_DATA,
2512 PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
2513 PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
2514 PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
2515 PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA }
2516 },
2517 { PINMUX_DATA_REG("PORTU223_192DR", 0xe6057818, 32) {
2518 0, 0, 0, 0,
2519 0, 0, 0, 0,
2520 0, 0, 0, 0,
2521 PORT211_DATA, PORT210_DATA, 0, 0,
2522 0, 0, 0, 0,
2523 0, 0, 0, 0,
2524 0, 0, 0, 0,
2525 0, 0, 0, 0 }
2526 },
2527 { },
2528};
2529
2530static struct pinmux_info r8a7740_pinmux_info = {
2531 .name = "r8a7740_pfc",
2532 .reserved_id = PINMUX_RESERVED,
2533 .data = { PINMUX_DATA_BEGIN,
2534 PINMUX_DATA_END },
2535 .input = { PINMUX_INPUT_BEGIN,
2536 PINMUX_INPUT_END },
2537 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN,
2538 PINMUX_INPUT_PULLUP_END },
2539 .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN,
2540 PINMUX_INPUT_PULLDOWN_END },
2541 .output = { PINMUX_OUTPUT_BEGIN,
2542 PINMUX_OUTPUT_END },
2543 .mark = { PINMUX_MARK_BEGIN,
2544 PINMUX_MARK_END },
2545 .function = { PINMUX_FUNCTION_BEGIN,
2546 PINMUX_FUNCTION_END },
2547
2548 .first_gpio = GPIO_PORT0,
2549 .last_gpio = GPIO_FN_TRACEAUD_FROM_MEMC,
2550
2551 .gpios = pinmux_gpios,
2552 .cfg_regs = pinmux_config_regs,
2553 .data_regs = pinmux_data_regs,
2554
2555 .gpio_data = pinmux_data,
2556 .gpio_data_size = ARRAY_SIZE(pinmux_data),
2557};
2558
2559void r8a7740_pinmux_init(void)
2560{
2561 register_pinmux(&r8a7740_pinmux_info);
2562}
diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c
new file mode 100644
index 000000000000..986dca6b3fad
--- /dev/null
+++ b/arch/arm/mach-shmobile/setup-r8a7740.c
@@ -0,0 +1,352 @@
1/*
2 * R8A7740 processor support
3 *
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20#include <linux/delay.h>
21#include <linux/kernel.h>
22#include <linux/init.h>
23#include <linux/io.h>
24#include <linux/platform_device.h>
25#include <linux/serial_sci.h>
26#include <linux/sh_timer.h>
27#include <mach/r8a7740.h>
28#include <asm/mach-types.h>
29#include <asm/mach/arch.h>
30
31/* SCIFA0 */
32static struct plat_sci_port scif0_platform_data = {
33 .mapbase = 0xe6c40000,
34 .flags = UPF_BOOT_AUTOCONF,
35 .scscr = SCSCR_RE | SCSCR_TE,
36 .scbrr_algo_id = SCBRR_ALGO_4,
37 .type = PORT_SCIFA,
38 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c00)),
39};
40
41static struct platform_device scif0_device = {
42 .name = "sh-sci",
43 .id = 0,
44 .dev = {
45 .platform_data = &scif0_platform_data,
46 },
47};
48
49/* SCIFA1 */
50static struct plat_sci_port scif1_platform_data = {
51 .mapbase = 0xe6c50000,
52 .flags = UPF_BOOT_AUTOCONF,
53 .scscr = SCSCR_RE | SCSCR_TE,
54 .scbrr_algo_id = SCBRR_ALGO_4,
55 .type = PORT_SCIFA,
56 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c20)),
57};
58
59static struct platform_device scif1_device = {
60 .name = "sh-sci",
61 .id = 1,
62 .dev = {
63 .platform_data = &scif1_platform_data,
64 },
65};
66
67/* SCIFA2 */
68static struct plat_sci_port scif2_platform_data = {
69 .mapbase = 0xe6c60000,
70 .flags = UPF_BOOT_AUTOCONF,
71 .scscr = SCSCR_RE | SCSCR_TE,
72 .scbrr_algo_id = SCBRR_ALGO_4,
73 .type = PORT_SCIFA,
74 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c40)),
75};
76
77static struct platform_device scif2_device = {
78 .name = "sh-sci",
79 .id = 2,
80 .dev = {
81 .platform_data = &scif2_platform_data,
82 },
83};
84
85/* SCIFA3 */
86static struct plat_sci_port scif3_platform_data = {
87 .mapbase = 0xe6c70000,
88 .flags = UPF_BOOT_AUTOCONF,
89 .scscr = SCSCR_RE | SCSCR_TE,
90 .scbrr_algo_id = SCBRR_ALGO_4,
91 .type = PORT_SCIFA,
92 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c60)),
93};
94
95static struct platform_device scif3_device = {
96 .name = "sh-sci",
97 .id = 3,
98 .dev = {
99 .platform_data = &scif3_platform_data,
100 },
101};
102
103/* SCIFA4 */
104static struct plat_sci_port scif4_platform_data = {
105 .mapbase = 0xe6c80000,
106 .flags = UPF_BOOT_AUTOCONF,
107 .scscr = SCSCR_RE | SCSCR_TE,
108 .scbrr_algo_id = SCBRR_ALGO_4,
109 .type = PORT_SCIFA,
110 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0d20)),
111};
112
113static struct platform_device scif4_device = {
114 .name = "sh-sci",
115 .id = 4,
116 .dev = {
117 .platform_data = &scif4_platform_data,
118 },
119};
120
121/* SCIFA5 */
122static struct plat_sci_port scif5_platform_data = {
123 .mapbase = 0xe6cb0000,
124 .flags = UPF_BOOT_AUTOCONF,
125 .scscr = SCSCR_RE | SCSCR_TE,
126 .scbrr_algo_id = SCBRR_ALGO_4,
127 .type = PORT_SCIFA,
128 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0d40)),
129};
130
131static struct platform_device scif5_device = {
132 .name = "sh-sci",
133 .id = 5,
134 .dev = {
135 .platform_data = &scif5_platform_data,
136 },
137};
138
139/* SCIFA6 */
140static struct plat_sci_port scif6_platform_data = {
141 .mapbase = 0xe6cc0000,
142 .flags = UPF_BOOT_AUTOCONF,
143 .scscr = SCSCR_RE | SCSCR_TE,
144 .scbrr_algo_id = SCBRR_ALGO_4,
145 .type = PORT_SCIFA,
146 .irqs = SCIx_IRQ_MUXED(evt2irq(0x04c0)),
147};
148
149static struct platform_device scif6_device = {
150 .name = "sh-sci",
151 .id = 6,
152 .dev = {
153 .platform_data = &scif6_platform_data,
154 },
155};
156
157/* SCIFA7 */
158static struct plat_sci_port scif7_platform_data = {
159 .mapbase = 0xe6cd0000,
160 .flags = UPF_BOOT_AUTOCONF,
161 .scscr = SCSCR_RE | SCSCR_TE,
162 .scbrr_algo_id = SCBRR_ALGO_4,
163 .type = PORT_SCIFA,
164 .irqs = SCIx_IRQ_MUXED(evt2irq(0x04e0)),
165};
166
167static struct platform_device scif7_device = {
168 .name = "sh-sci",
169 .id = 7,
170 .dev = {
171 .platform_data = &scif7_platform_data,
172 },
173};
174
175/* SCIFB */
176static struct plat_sci_port scifb_platform_data = {
177 .mapbase = 0xe6c30000,
178 .flags = UPF_BOOT_AUTOCONF,
179 .scscr = SCSCR_RE | SCSCR_TE,
180 .scbrr_algo_id = SCBRR_ALGO_4,
181 .type = PORT_SCIFB,
182 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0d60)),
183};
184
185static struct platform_device scifb_device = {
186 .name = "sh-sci",
187 .id = 8,
188 .dev = {
189 .platform_data = &scifb_platform_data,
190 },
191};
192
193/* CMT */
194static struct sh_timer_config cmt10_platform_data = {
195 .name = "CMT10",
196 .channel_offset = 0x10,
197 .timer_bit = 0,
198 .clockevent_rating = 125,
199 .clocksource_rating = 125,
200};
201
202static struct resource cmt10_resources[] = {
203 [0] = {
204 .name = "CMT10",
205 .start = 0xe6138010,
206 .end = 0xe613801b,
207 .flags = IORESOURCE_MEM,
208 },
209 [1] = {
210 .start = evt2irq(0x0b00),
211 .flags = IORESOURCE_IRQ,
212 },
213};
214
215static struct platform_device cmt10_device = {
216 .name = "sh_cmt",
217 .id = 10,
218 .dev = {
219 .platform_data = &cmt10_platform_data,
220 },
221 .resource = cmt10_resources,
222 .num_resources = ARRAY_SIZE(cmt10_resources),
223};
224
225static struct platform_device *r8a7740_early_devices[] __initdata = {
226 &scif0_device,
227 &scif1_device,
228 &scif2_device,
229 &scif3_device,
230 &scif4_device,
231 &scif5_device,
232 &scif6_device,
233 &scif7_device,
234 &scifb_device,
235 &cmt10_device,
236};
237
238/* I2C */
239static struct resource i2c0_resources[] = {
240 [0] = {
241 .name = "IIC0",
242 .start = 0xfff20000,
243 .end = 0xfff20425 - 1,
244 .flags = IORESOURCE_MEM,
245 },
246 [1] = {
247 .start = intcs_evt2irq(0xe00),
248 .end = intcs_evt2irq(0xe60),
249 .flags = IORESOURCE_IRQ,
250 },
251};
252
253static struct resource i2c1_resources[] = {
254 [0] = {
255 .name = "IIC1",
256 .start = 0xe6c20000,
257 .end = 0xe6c20425 - 1,
258 .flags = IORESOURCE_MEM,
259 },
260 [1] = {
261 .start = evt2irq(0x780), /* IIC1_ALI1 */
262 .end = evt2irq(0x7e0), /* IIC1_DTEI1 */
263 .flags = IORESOURCE_IRQ,
264 },
265};
266
267static struct platform_device i2c0_device = {
268 .name = "i2c-sh_mobile",
269 .id = 0,
270 .resource = i2c0_resources,
271 .num_resources = ARRAY_SIZE(i2c0_resources),
272};
273
274static struct platform_device i2c1_device = {
275 .name = "i2c-sh_mobile",
276 .id = 1,
277 .resource = i2c1_resources,
278 .num_resources = ARRAY_SIZE(i2c1_resources),
279};
280
281static struct platform_device *r8a7740_late_devices[] __initdata = {
282 &i2c0_device,
283 &i2c1_device,
284};
285
286#define ICCR 0x0004
287#define ICSTART 0x0070
288
289#define i2c_read(reg, offset) ioread8(reg + offset)
290#define i2c_write(reg, offset, data) iowrite8(data, reg + offset)
291
292/*
293 * r8a7740 chip has lasting errata on I2C I/O pad reset.
294 * this is work-around for it.
295 */
296static void r8a7740_i2c_workaround(struct platform_device *pdev)
297{
298 struct resource *res;
299 void __iomem *reg;
300
301 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
302 if (unlikely(!res)) {
303 pr_err("r8a7740 i2c workaround fail (cannot find resource)\n");
304 return;
305 }
306
307 reg = ioremap(res->start, resource_size(res));
308 if (unlikely(!reg)) {
309 pr_err("r8a7740 i2c workaround fail (cannot map IO)\n");
310 return;
311 }
312
313 i2c_write(reg, ICCR, i2c_read(reg, ICCR) | 0x80);
314 i2c_read(reg, ICCR); /* dummy read */
315
316 i2c_write(reg, ICSTART, i2c_read(reg, ICSTART) | 0x10);
317 i2c_read(reg, ICSTART); /* dummy read */
318
319 mdelay(100);
320
321 i2c_write(reg, ICCR, 0x01);
322 i2c_read(reg, ICCR);
323 i2c_write(reg, ICSTART, 0x00);
324 i2c_read(reg, ICSTART);
325
326 i2c_write(reg, ICCR, 0x10);
327 mdelay(100);
328 i2c_write(reg, ICCR, 0x00);
329 mdelay(100);
330 i2c_write(reg, ICCR, 0x10);
331 mdelay(100);
332
333 iounmap(reg);
334}
335
336void __init r8a7740_add_standard_devices(void)
337{
338 /* I2C work-around */
339 r8a7740_i2c_workaround(&i2c0_device);
340 r8a7740_i2c_workaround(&i2c1_device);
341
342 platform_add_devices(r8a7740_early_devices,
343 ARRAY_SIZE(r8a7740_early_devices));
344 platform_add_devices(r8a7740_late_devices,
345 ARRAY_SIZE(r8a7740_late_devices));
346}
347
348void __init r8a7740_add_early_devices(void)
349{
350 early_platform_add_devices(r8a7740_early_devices,
351 ARRAY_SIZE(r8a7740_early_devices));
352}
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-14 01:33:09 -0500