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-rw-r--r--arch/arm/mach-omap1/clock.c34
-rw-r--r--arch/arm/mach-omap1/clock.h21
2 files changed, 53 insertions, 2 deletions
diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c
index f625f6dd228a..5d9faa68d2ec 100644
--- a/arch/arm/mach-omap1/clock.c
+++ b/arch/arm/mach-omap1/clock.c
@@ -49,6 +49,15 @@ static void omap1_uart_recalc(struct clk * clk)
49 clk->rate = 12000000; 49 clk->rate = 12000000;
50} 50}
51 51
52static void omap1_sossi_recalc(struct clk *clk)
53{
54 u32 div = omap_readl(MOD_CONF_CTRL_1);
55
56 div = (div >> 17) & 0x7;
57 div++;
58 clk->rate = clk->parent->rate / div;
59}
60
52static int omap1_clk_enable_dsp_domain(struct clk *clk) 61static int omap1_clk_enable_dsp_domain(struct clk *clk)
53{ 62{
54 int retval; 63 int retval;
@@ -396,6 +405,31 @@ static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate)
396 return 0; 405 return 0;
397} 406}
398 407
408static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate)
409{
410 u32 l;
411 int div;
412 unsigned long p_rate;
413
414 p_rate = clk->parent->rate;
415 /* Round towards slower frequency */
416 div = (p_rate + rate - 1) / rate;
417 div--;
418 if (div < 0 || div > 7)
419 return -EINVAL;
420
421 l = omap_readl(MOD_CONF_CTRL_1);
422 l &= ~(7 << 17);
423 l |= div << 17;
424 omap_writel(l, MOD_CONF_CTRL_1);
425
426 clk->rate = p_rate / (div + 1);
427 if (unlikely(clk->flags & RATE_PROPAGATES))
428 propagate_rate(clk);
429
430 return 0;
431}
432
399static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate) 433static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate)
400{ 434{
401 return 96000000 / calc_ext_dsor(rate); 435 return 96000000 / calc_ext_dsor(rate);
diff --git a/arch/arm/mach-omap1/clock.h b/arch/arm/mach-omap1/clock.h
index 4d6060c2facb..6eadf72828d8 100644
--- a/arch/arm/mach-omap1/clock.h
+++ b/arch/arm/mach-omap1/clock.h
@@ -17,6 +17,8 @@ static int omap1_clk_enable_generic(struct clk * clk);
17static void omap1_clk_disable_generic(struct clk * clk); 17static void omap1_clk_disable_generic(struct clk * clk);
18static void omap1_ckctl_recalc(struct clk * clk); 18static void omap1_ckctl_recalc(struct clk * clk);
19static void omap1_watchdog_recalc(struct clk * clk); 19static void omap1_watchdog_recalc(struct clk * clk);
20static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate);
21static void omap1_sossi_recalc(struct clk *clk);
20static void omap1_ckctl_recalc_dsp_domain(struct clk * clk); 22static void omap1_ckctl_recalc_dsp_domain(struct clk * clk);
21static int omap1_clk_enable_dsp_domain(struct clk * clk); 23static int omap1_clk_enable_dsp_domain(struct clk * clk);
22static int omap1_clk_set_rate_dsp_domain(struct clk * clk, unsigned long rate); 24static int omap1_clk_set_rate_dsp_domain(struct clk * clk, unsigned long rate);
@@ -168,9 +170,10 @@ static struct clk ck_dpll1 = {
168 170
169static struct arm_idlect1_clk ck_dpll1out = { 171static struct arm_idlect1_clk ck_dpll1out = {
170 .clk = { 172 .clk = {
171 .name = "ck_dpll1out", 173 .name = "ck_dpll1out",
172 .parent = &ck_dpll1, 174 .parent = &ck_dpll1,
173 .flags = CLOCK_IN_OMAP16XX | CLOCK_IDLE_CONTROL, 175 .flags = CLOCK_IN_OMAP16XX | CLOCK_IDLE_CONTROL |
176 ENABLE_REG_32BIT | RATE_PROPAGATES,
174 .enable_reg = (void __iomem *)ARM_IDLECT2, 177 .enable_reg = (void __iomem *)ARM_IDLECT2,
175 .enable_bit = EN_CKOUT_ARM, 178 .enable_bit = EN_CKOUT_ARM,
176 .recalc = &followparent_recalc, 179 .recalc = &followparent_recalc,
@@ -180,6 +183,19 @@ static struct arm_idlect1_clk ck_dpll1out = {
180 .idlect_shift = 12, 183 .idlect_shift = 12,
181}; 184};
182 185
186static struct clk sossi_ck = {
187 .name = "ck_sossi",
188 .parent = &ck_dpll1out.clk,
189 .flags = CLOCK_IN_OMAP16XX | CLOCK_NO_IDLE_PARENT |
190 ENABLE_REG_32BIT,
191 .enable_reg = (void __iomem *)MOD_CONF_CTRL_1,
192 .enable_bit = 16,
193 .recalc = &omap1_sossi_recalc,
194 .set_rate = &omap1_set_sossi_rate,
195 .enable = &omap1_clk_enable_generic,
196 .disable = &omap1_clk_disable_generic,
197};
198
183static struct clk arm_ck = { 199static struct clk arm_ck = {
184 .name = "arm_ck", 200 .name = "arm_ck",
185 .parent = &ck_dpll1, 201 .parent = &ck_dpll1,
@@ -760,6 +776,7 @@ static struct clk * onchip_clks[] = {
760 &ck_dpll1, 776 &ck_dpll1,
761 /* CK_GEN1 clocks */ 777 /* CK_GEN1 clocks */
762 &ck_dpll1out.clk, 778 &ck_dpll1out.clk,
779 &sossi_ck,
763 &arm_ck, 780 &arm_ck,
764 &armper_ck.clk, 781 &armper_ck.clk,
765 &arm_gpio_ck, 782 &arm_gpio_ck,