aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/boot/dts/am335x-bone.dts8
-rw-r--r--arch/arm/boot/dts/am335x-evm.dts8
-rw-r--r--arch/arm/boot/dts/am33xx.dtsi47
-rw-r--r--arch/arm/boot/dts/imx6q.dtsi5
-rw-r--r--arch/arm/configs/omap2plus_defconfig3
-rw-r--r--arch/arm/mach-at91/Kconfig4
-rw-r--r--arch/arm/mach-at91/board-csb337.c2
-rw-r--r--arch/arm/mach-at91/include/mach/at91rm9200_emac.h138
-rw-r--r--arch/arm/mach-imx/mach-imx6q.c12
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_33xx_data.c31
-rw-r--r--arch/arm/net/bpf_jit_32.c29
-rw-r--r--arch/arm/net/bpf_jit_32.h2
12 files changed, 140 insertions, 149 deletions
diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts
index 2c338889df1b..11b240c5d323 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -128,3 +128,11 @@
128 }; 128 };
129 }; 129 };
130}; 130};
131
132&cpsw_emac0 {
133 phy_id = <&davinci_mdio>, <0>;
134};
135
136&cpsw_emac1 {
137 phy_id = <&davinci_mdio>, <1>;
138};
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index 9f65f17ebdf8..d6496440fcea 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -236,3 +236,11 @@
236 }; 236 };
237 }; 237 };
238}; 238};
239
240&cpsw_emac0 {
241 phy_id = <&davinci_mdio>, <0>;
242};
243
244&cpsw_emac1 {
245 phy_id = <&davinci_mdio>, <1>;
246};
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 20a3f29a6bfe..c2f14e875eb6 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -338,5 +338,52 @@
338 power = <250>; 338 power = <250>;
339 ti,hwmods = "usb_otg_hs"; 339 ti,hwmods = "usb_otg_hs";
340 }; 340 };
341
342 mac: ethernet@4a100000 {
343 compatible = "ti,cpsw";
344 ti,hwmods = "cpgmac0";
345 cpdma_channels = <8>;
346 ale_entries = <1024>;
347 bd_ram_size = <0x2000>;
348 no_bd_ram = <0>;
349 rx_descs = <64>;
350 mac_control = <0x20>;
351 slaves = <2>;
352 cpts_active_slave = <0>;
353 cpts_clock_mult = <0x80000000>;
354 cpts_clock_shift = <29>;
355 reg = <0x4a100000 0x800
356 0x4a101200 0x100>;
357 #address-cells = <1>;
358 #size-cells = <1>;
359 interrupt-parent = <&intc>;
360 /*
361 * c0_rx_thresh_pend
362 * c0_rx_pend
363 * c0_tx_pend
364 * c0_misc_pend
365 */
366 interrupts = <40 41 42 43>;
367 ranges;
368
369 davinci_mdio: mdio@4a101000 {
370 compatible = "ti,davinci_mdio";
371 #address-cells = <1>;
372 #size-cells = <0>;
373 ti,hwmods = "davinci_mdio";
374 bus_freq = <1000000>;
375 reg = <0x4a101000 0x100>;
376 };
377
378 cpsw_emac0: slave@4a100200 {
379 /* Filled in by U-Boot */
380 mac-address = [ 00 00 00 00 00 00 ];
381 };
382
383 cpsw_emac1: slave@4a100300 {
384 /* Filled in by U-Boot */
385 mac-address = [ 00 00 00 00 00 00 ];
386 };
387 };
341 }; 388 };
342}; 389};
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index d907d062e5dd..cce1d874c7a5 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -596,6 +596,7 @@
596 66 0x1b0b0 /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */ 596 66 0x1b0b0 /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */
597 70 0x1b0b0 /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */ 597 70 0x1b0b0 /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */
598 48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */ 598 48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
599 1033 0x4001b0a8 /* MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT*/
599 >; 600 >;
600 }; 601 };
601 602
@@ -849,8 +850,8 @@
849 compatible = "fsl,imx6q-fec"; 850 compatible = "fsl,imx6q-fec";
850 reg = <0x02188000 0x4000>; 851 reg = <0x02188000 0x4000>;
851 interrupts = <0 118 0x04 0 119 0x04>; 852 interrupts = <0 118 0x04 0 119 0x04>;
852 clocks = <&clks 117>, <&clks 117>; 853 clocks = <&clks 117>, <&clks 117>, <&clks 177>;
853 clock-names = "ipg", "ahb"; 854 clock-names = "ipg", "ahb", "ptp";
854 status = "disabled"; 855 status = "disabled";
855 }; 856 };
856 857
diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
index 62303043db9c..a1dc5c071e71 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -240,3 +240,6 @@ CONFIG_CRC_ITU_T=y
240CONFIG_CRC7=y 240CONFIG_CRC7=y
241CONFIG_LIBCRC32C=y 241CONFIG_LIBCRC32C=y
242CONFIG_SOC_OMAP5=y 242CONFIG_SOC_OMAP5=y
243CONFIG_TI_DAVINCI_MDIO=y
244CONFIG_TI_DAVINCI_CPDMA=y
245CONFIG_TI_CPSW=y
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index e34c1bdb804d..958358c91afd 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -39,7 +39,6 @@ config SOC_AT91RM9200
39config SOC_AT91SAM9260 39config SOC_AT91SAM9260
40 bool "AT91SAM9260, AT91SAM9XE or AT91SAM9G20" 40 bool "AT91SAM9260, AT91SAM9XE or AT91SAM9G20"
41 select HAVE_AT91_DBGU0 41 select HAVE_AT91_DBGU0
42 select HAVE_NET_MACB
43 select SOC_AT91SAM9 42 select SOC_AT91SAM9
44 help 43 help
45 Select this if you are using one of Atmel's AT91SAM9260, AT91SAM9XE 44 Select this if you are using one of Atmel's AT91SAM9260, AT91SAM9XE
@@ -57,7 +56,6 @@ config SOC_AT91SAM9263
57 bool "AT91SAM9263" 56 bool "AT91SAM9263"
58 select HAVE_AT91_DBGU1 57 select HAVE_AT91_DBGU1
59 select HAVE_FB_ATMEL 58 select HAVE_FB_ATMEL
60 select HAVE_NET_MACB
61 select SOC_AT91SAM9 59 select SOC_AT91SAM9
62 60
63config SOC_AT91SAM9RL 61config SOC_AT91SAM9RL
@@ -70,7 +68,6 @@ config SOC_AT91SAM9G45
70 bool "AT91SAM9G45 or AT91SAM9M10 families" 68 bool "AT91SAM9G45 or AT91SAM9M10 families"
71 select HAVE_AT91_DBGU1 69 select HAVE_AT91_DBGU1
72 select HAVE_FB_ATMEL 70 select HAVE_FB_ATMEL
73 select HAVE_NET_MACB
74 select SOC_AT91SAM9 71 select SOC_AT91SAM9
75 help 72 help
76 Select this if you are using one of Atmel's AT91SAM9G45 family SoC. 73 Select this if you are using one of Atmel's AT91SAM9G45 family SoC.
@@ -80,7 +77,6 @@ config SOC_AT91SAM9X5
80 bool "AT91SAM9x5 family" 77 bool "AT91SAM9x5 family"
81 select HAVE_AT91_DBGU0 78 select HAVE_AT91_DBGU0
82 select HAVE_FB_ATMEL 79 select HAVE_FB_ATMEL
83 select HAVE_NET_MACB
84 select SOC_AT91SAM9 80 select SOC_AT91SAM9
85 help 81 help
86 Select this if you are using one of Atmel's AT91SAM9x5 family SoC. 82 Select this if you are using one of Atmel's AT91SAM9x5 family SoC.
diff --git a/arch/arm/mach-at91/board-csb337.c b/arch/arm/mach-at91/board-csb337.c
index 78e025074423..48a531e05be3 100644
--- a/arch/arm/mach-at91/board-csb337.c
+++ b/arch/arm/mach-at91/board-csb337.c
@@ -53,6 +53,8 @@ static void __init csb337_init_early(void)
53static struct macb_platform_data __initdata csb337_eth_data = { 53static struct macb_platform_data __initdata csb337_eth_data = {
54 .phy_irq_pin = AT91_PIN_PC2, 54 .phy_irq_pin = AT91_PIN_PC2,
55 .is_rmii = 0, 55 .is_rmii = 0,
56 /* The CSB337 bootloader stores the MAC the wrong-way around */
57 .rev_eth_addr = 1,
56}; 58};
57 59
58static struct at91_usbh_data __initdata csb337_usbh_data = { 60static struct at91_usbh_data __initdata csb337_usbh_data = {
diff --git a/arch/arm/mach-at91/include/mach/at91rm9200_emac.h b/arch/arm/mach-at91/include/mach/at91rm9200_emac.h
deleted file mode 100644
index b8260cd8041c..000000000000
--- a/arch/arm/mach-at91/include/mach/at91rm9200_emac.h
+++ /dev/null
@@ -1,138 +0,0 @@
1/*
2 * arch/arm/mach-at91/include/mach/at91rm9200_emac.h
3 *
4 * Copyright (C) 2005 Ivan Kokshaysky
5 * Copyright (C) SAN People
6 *
7 * Ethernet MAC registers.
8 * Based on AT91RM9200 datasheet revision E.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#ifndef AT91RM9200_EMAC_H
17#define AT91RM9200_EMAC_H
18
19#define AT91_EMAC_CTL 0x00 /* Control Register */
20#define AT91_EMAC_LB (1 << 0) /* Loopback */
21#define AT91_EMAC_LBL (1 << 1) /* Loopback Local */
22#define AT91_EMAC_RE (1 << 2) /* Receive Enable */
23#define AT91_EMAC_TE (1 << 3) /* Transmit Enable */
24#define AT91_EMAC_MPE (1 << 4) /* Management Port Enable */
25#define AT91_EMAC_CSR (1 << 5) /* Clear Statistics Registers */
26#define AT91_EMAC_INCSTAT (1 << 6) /* Increment Statistics Registers */
27#define AT91_EMAC_WES (1 << 7) /* Write Enable for Statistics Registers */
28#define AT91_EMAC_BP (1 << 8) /* Back Pressure */
29
30#define AT91_EMAC_CFG 0x04 /* Configuration Register */
31#define AT91_EMAC_SPD (1 << 0) /* Speed */
32#define AT91_EMAC_FD (1 << 1) /* Full Duplex */
33#define AT91_EMAC_BR (1 << 2) /* Bit Rate */
34#define AT91_EMAC_CAF (1 << 4) /* Copy All Frames */
35#define AT91_EMAC_NBC (1 << 5) /* No Broadcast */
36#define AT91_EMAC_MTI (1 << 6) /* Multicast Hash Enable */
37#define AT91_EMAC_UNI (1 << 7) /* Unicast Hash Enable */
38#define AT91_EMAC_BIG (1 << 8) /* Receive 1522 Bytes */
39#define AT91_EMAC_EAE (1 << 9) /* External Address Match Enable */
40#define AT91_EMAC_CLK (3 << 10) /* MDC Clock Divisor */
41#define AT91_EMAC_CLK_DIV8 (0 << 10)
42#define AT91_EMAC_CLK_DIV16 (1 << 10)
43#define AT91_EMAC_CLK_DIV32 (2 << 10)
44#define AT91_EMAC_CLK_DIV64 (3 << 10)
45#define AT91_EMAC_RTY (1 << 12) /* Retry Test */
46#define AT91_EMAC_RMII (1 << 13) /* Reduce MII (RMII) */
47
48#define AT91_EMAC_SR 0x08 /* Status Register */
49#define AT91_EMAC_SR_LINK (1 << 0) /* Link */
50#define AT91_EMAC_SR_MDIO (1 << 1) /* MDIO pin */
51#define AT91_EMAC_SR_IDLE (1 << 2) /* PHY idle */
52
53#define AT91_EMAC_TAR 0x0c /* Transmit Address Register */
54
55#define AT91_EMAC_TCR 0x10 /* Transmit Control Register */
56#define AT91_EMAC_LEN (0x7ff << 0) /* Transmit Frame Length */
57#define AT91_EMAC_NCRC (1 << 15) /* No CRC */
58
59#define AT91_EMAC_TSR 0x14 /* Transmit Status Register */
60#define AT91_EMAC_TSR_OVR (1 << 0) /* Transmit Buffer Overrun */
61#define AT91_EMAC_TSR_COL (1 << 1) /* Collision Occurred */
62#define AT91_EMAC_TSR_RLE (1 << 2) /* Retry Limit Exceeded */
63#define AT91_EMAC_TSR_IDLE (1 << 3) /* Transmitter Idle */
64#define AT91_EMAC_TSR_BNQ (1 << 4) /* Transmit Buffer not Queued */
65#define AT91_EMAC_TSR_COMP (1 << 5) /* Transmit Complete */
66#define AT91_EMAC_TSR_UND (1 << 6) /* Transmit Underrun */
67
68#define AT91_EMAC_RBQP 0x18 /* Receive Buffer Queue Pointer */
69
70#define AT91_EMAC_RSR 0x20 /* Receive Status Register */
71#define AT91_EMAC_RSR_BNA (1 << 0) /* Buffer Not Available */
72#define AT91_EMAC_RSR_REC (1 << 1) /* Frame Received */
73#define AT91_EMAC_RSR_OVR (1 << 2) /* RX Overrun */
74
75#define AT91_EMAC_ISR 0x24 /* Interrupt Status Register */
76#define AT91_EMAC_DONE (1 << 0) /* Management Done */
77#define AT91_EMAC_RCOM (1 << 1) /* Receive Complete */
78#define AT91_EMAC_RBNA (1 << 2) /* Receive Buffer Not Available */
79#define AT91_EMAC_TOVR (1 << 3) /* Transmit Buffer Overrun */
80#define AT91_EMAC_TUND (1 << 4) /* Transmit Buffer Underrun */
81#define AT91_EMAC_RTRY (1 << 5) /* Retry Limit */
82#define AT91_EMAC_TBRE (1 << 6) /* Transmit Buffer Register Empty */
83#define AT91_EMAC_TCOM (1 << 7) /* Transmit Complete */
84#define AT91_EMAC_TIDLE (1 << 8) /* Transmit Idle */
85#define AT91_EMAC_LINK (1 << 9) /* Link */
86#define AT91_EMAC_ROVR (1 << 10) /* RX Overrun */
87#define AT91_EMAC_ABT (1 << 11) /* Abort */
88
89#define AT91_EMAC_IER 0x28 /* Interrupt Enable Register */
90#define AT91_EMAC_IDR 0x2c /* Interrupt Disable Register */
91#define AT91_EMAC_IMR 0x30 /* Interrupt Mask Register */
92
93#define AT91_EMAC_MAN 0x34 /* PHY Maintenance Register */
94#define AT91_EMAC_DATA (0xffff << 0) /* MDIO Data */
95#define AT91_EMAC_REGA (0x1f << 18) /* MDIO Register */
96#define AT91_EMAC_PHYA (0x1f << 23) /* MDIO PHY Address */
97#define AT91_EMAC_RW (3 << 28) /* Read/Write operation */
98#define AT91_EMAC_RW_W (1 << 28)
99#define AT91_EMAC_RW_R (2 << 28)
100#define AT91_EMAC_MAN_802_3 0x40020000 /* IEEE 802.3 value */
101
102/*
103 * Statistics Registers.
104 */
105#define AT91_EMAC_FRA 0x40 /* Frames Transmitted OK */
106#define AT91_EMAC_SCOL 0x44 /* Single Collision Frame */
107#define AT91_EMAC_MCOL 0x48 /* Multiple Collision Frame */
108#define AT91_EMAC_OK 0x4c /* Frames Received OK */
109#define AT91_EMAC_SEQE 0x50 /* Frame Check Sequence Error */
110#define AT91_EMAC_ALE 0x54 /* Alignmemt Error */
111#define AT91_EMAC_DTE 0x58 /* Deffered Transmission Frame */
112#define AT91_EMAC_LCOL 0x5c /* Late Collision */
113#define AT91_EMAC_ECOL 0x60 /* Excessive Collision */
114#define AT91_EMAC_TUE 0x64 /* Transmit Underrun Error */
115#define AT91_EMAC_CSE 0x68 /* Carrier Sense Error */
116#define AT91_EMAC_DRFC 0x6c /* Discard RX Frame */
117#define AT91_EMAC_ROV 0x70 /* Receive Overrun */
118#define AT91_EMAC_CDE 0x74 /* Code Error */
119#define AT91_EMAC_ELR 0x78 /* Excessive Length Error */
120#define AT91_EMAC_RJB 0x7c /* Receive Jabber */
121#define AT91_EMAC_USF 0x80 /* Undersize Frame */
122#define AT91_EMAC_SQEE 0x84 /* SQE Test Error */
123
124/*
125 * Address Registers.
126 */
127#define AT91_EMAC_HSL 0x90 /* Hash Address Low [31:0] */
128#define AT91_EMAC_HSH 0x94 /* Hash Address High [63:32] */
129#define AT91_EMAC_SA1L 0x98 /* Specific Address 1 Low, bytes 0-3 */
130#define AT91_EMAC_SA1H 0x9c /* Specific Address 1 High, bytes 4-5 */
131#define AT91_EMAC_SA2L 0xa0 /* Specific Address 2 Low, bytes 0-3 */
132#define AT91_EMAC_SA2H 0xa4 /* Specific Address 2 High, bytes 4-5 */
133#define AT91_EMAC_SA3L 0xa8 /* Specific Address 3 Low, bytes 0-3 */
134#define AT91_EMAC_SA3H 0xac /* Specific Address 3 High, bytes 4-5 */
135#define AT91_EMAC_SA4L 0xb0 /* Specific Address 4 Low, bytes 0-3 */
136#define AT91_EMAC_SA4H 0xb4 /* Specific Address 4 High, bytes 4-5 */
137
138#endif
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 978b6dd00de4..cce33e433bd1 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -117,6 +117,17 @@ static void __init imx6q_sabrelite_init(void)
117 imx6q_sabrelite_cko1_setup(); 117 imx6q_sabrelite_cko1_setup();
118} 118}
119 119
120static void __init imx6q_1588_init(void)
121{
122 struct regmap *gpr;
123
124 gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
125 if (!IS_ERR(gpr))
126 regmap_update_bits(gpr, 0x4, 1 << 21, 1 << 21);
127 else
128 pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n");
129
130}
120static void __init imx6q_usb_init(void) 131static void __init imx6q_usb_init(void)
121{ 132{
122 struct regmap *anatop; 133 struct regmap *anatop;
@@ -153,6 +164,7 @@ static void __init imx6q_init_machine(void)
153 164
154 imx6q_pm_init(); 165 imx6q_pm_init();
155 imx6q_usb_init(); 166 imx6q_usb_init();
167 imx6q_1588_init();
156} 168}
157 169
158static struct cpuidle_driver imx6q_cpuidle_driver = { 170static struct cpuidle_driver imx6q_cpuidle_driver = {
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index ad8d43b33273..32820d89f5b4 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -674,6 +674,7 @@ static struct omap_hwmod am33xx_cpgmac0_hwmod = {
674 .name = "cpgmac0", 674 .name = "cpgmac0",
675 .class = &am33xx_cpgmac0_hwmod_class, 675 .class = &am33xx_cpgmac0_hwmod_class,
676 .clkdm_name = "cpsw_125mhz_clkdm", 676 .clkdm_name = "cpsw_125mhz_clkdm",
677 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
677 .mpu_irqs = am33xx_cpgmac0_irqs, 678 .mpu_irqs = am33xx_cpgmac0_irqs,
678 .main_clk = "cpsw_125mhz_gclk", 679 .main_clk = "cpsw_125mhz_gclk",
679 .prcm = { 680 .prcm = {
@@ -685,6 +686,20 @@ static struct omap_hwmod am33xx_cpgmac0_hwmod = {
685}; 686};
686 687
687/* 688/*
689 * mdio class
690 */
691static struct omap_hwmod_class am33xx_mdio_hwmod_class = {
692 .name = "davinci_mdio",
693};
694
695static struct omap_hwmod am33xx_mdio_hwmod = {
696 .name = "davinci_mdio",
697 .class = &am33xx_mdio_hwmod_class,
698 .clkdm_name = "cpsw_125mhz_clkdm",
699 .main_clk = "cpsw_125mhz_gclk",
700};
701
702/*
688 * dcan class 703 * dcan class
689 */ 704 */
690static struct omap_hwmod_class am33xx_dcan_hwmod_class = { 705static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
@@ -2501,6 +2516,21 @@ static struct omap_hwmod_ocp_if am33xx_l4_hs__cpgmac0 = {
2501 .user = OCP_USER_MPU, 2516 .user = OCP_USER_MPU,
2502}; 2517};
2503 2518
2519struct omap_hwmod_addr_space am33xx_mdio_addr_space[] = {
2520 {
2521 .pa_start = 0x4A101000,
2522 .pa_end = 0x4A101000 + SZ_256 - 1,
2523 },
2524 { }
2525};
2526
2527struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio = {
2528 .master = &am33xx_cpgmac0_hwmod,
2529 .slave = &am33xx_mdio_hwmod,
2530 .addr = am33xx_mdio_addr_space,
2531 .user = OCP_USER_MPU,
2532};
2533
2504static struct omap_hwmod_addr_space am33xx_elm_addr_space[] = { 2534static struct omap_hwmod_addr_space am33xx_elm_addr_space[] = {
2505 { 2535 {
2506 .pa_start = 0x48080000, 2536 .pa_start = 0x48080000,
@@ -3371,6 +3401,7 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
3371 &am33xx_l3_main__tptc2, 3401 &am33xx_l3_main__tptc2,
3372 &am33xx_l3_s__usbss, 3402 &am33xx_l3_s__usbss,
3373 &am33xx_l4_hs__cpgmac0, 3403 &am33xx_l4_hs__cpgmac0,
3404 &am33xx_cpgmac0__mdio,
3374 NULL, 3405 NULL,
3375}; 3406};
3376 3407
diff --git a/arch/arm/net/bpf_jit_32.c b/arch/arm/net/bpf_jit_32.c
index b6f305e3b908..a34f1e214116 100644
--- a/arch/arm/net/bpf_jit_32.c
+++ b/arch/arm/net/bpf_jit_32.c
@@ -16,6 +16,7 @@
16#include <linux/netdevice.h> 16#include <linux/netdevice.h>
17#include <linux/string.h> 17#include <linux/string.h>
18#include <linux/slab.h> 18#include <linux/slab.h>
19#include <linux/if_vlan.h>
19#include <asm/cacheflush.h> 20#include <asm/cacheflush.h>
20#include <asm/hwcap.h> 21#include <asm/hwcap.h>
21 22
@@ -168,6 +169,8 @@ static inline bool is_load_to_a(u16 inst)
168 case BPF_S_ANC_MARK: 169 case BPF_S_ANC_MARK:
169 case BPF_S_ANC_PROTOCOL: 170 case BPF_S_ANC_PROTOCOL:
170 case BPF_S_ANC_RXHASH: 171 case BPF_S_ANC_RXHASH:
172 case BPF_S_ANC_VLAN_TAG:
173 case BPF_S_ANC_VLAN_TAG_PRESENT:
171 case BPF_S_ANC_QUEUE: 174 case BPF_S_ANC_QUEUE:
172 return true; 175 return true;
173 default: 176 default:
@@ -646,6 +649,16 @@ load_ind:
646 update_on_xread(ctx); 649 update_on_xread(ctx);
647 emit(ARM_ORR_R(r_A, r_A, r_X), ctx); 650 emit(ARM_ORR_R(r_A, r_A, r_X), ctx);
648 break; 651 break;
652 case BPF_S_ALU_XOR_K:
653 /* A ^= K; */
654 OP_IMM3(ARM_EOR, r_A, r_A, k, ctx);
655 break;
656 case BPF_S_ANC_ALU_XOR_X:
657 case BPF_S_ALU_XOR_X:
658 /* A ^= X */
659 update_on_xread(ctx);
660 emit(ARM_EOR_R(r_A, r_A, r_X), ctx);
661 break;
649 case BPF_S_ALU_AND_K: 662 case BPF_S_ALU_AND_K:
650 /* A &= K */ 663 /* A &= K */
651 OP_IMM3(ARM_AND, r_A, r_A, k, ctx); 664 OP_IMM3(ARM_AND, r_A, r_A, k, ctx);
@@ -762,11 +775,6 @@ b_epilogue:
762 update_on_xread(ctx); 775 update_on_xread(ctx);
763 emit(ARM_MOV_R(r_A, r_X), ctx); 776 emit(ARM_MOV_R(r_A, r_X), ctx);
764 break; 777 break;
765 case BPF_S_ANC_ALU_XOR_X:
766 /* A ^= X */
767 update_on_xread(ctx);
768 emit(ARM_EOR_R(r_A, r_A, r_X), ctx);
769 break;
770 case BPF_S_ANC_PROTOCOL: 778 case BPF_S_ANC_PROTOCOL:
771 /* A = ntohs(skb->protocol) */ 779 /* A = ntohs(skb->protocol) */
772 ctx->seen |= SEEN_SKB; 780 ctx->seen |= SEEN_SKB;
@@ -810,6 +818,17 @@ b_epilogue:
810 off = offsetof(struct sk_buff, rxhash); 818 off = offsetof(struct sk_buff, rxhash);
811 emit(ARM_LDR_I(r_A, r_skb, off), ctx); 819 emit(ARM_LDR_I(r_A, r_skb, off), ctx);
812 break; 820 break;
821 case BPF_S_ANC_VLAN_TAG:
822 case BPF_S_ANC_VLAN_TAG_PRESENT:
823 ctx->seen |= SEEN_SKB;
824 BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, vlan_tci) != 2);
825 off = offsetof(struct sk_buff, vlan_tci);
826 emit(ARM_LDRH_I(r_A, r_skb, off), ctx);
827 if (inst->code == BPF_S_ANC_VLAN_TAG)
828 OP_IMM3(ARM_AND, r_A, r_A, VLAN_VID_MASK, ctx);
829 else
830 OP_IMM3(ARM_AND, r_A, r_A, VLAN_TAG_PRESENT, ctx);
831 break;
813 case BPF_S_ANC_QUEUE: 832 case BPF_S_ANC_QUEUE:
814 ctx->seen |= SEEN_SKB; 833 ctx->seen |= SEEN_SKB;
815 BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, 834 BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff,
diff --git a/arch/arm/net/bpf_jit_32.h b/arch/arm/net/bpf_jit_32.h
index 7fa2f7d3cb90..afb84621ff6f 100644
--- a/arch/arm/net/bpf_jit_32.h
+++ b/arch/arm/net/bpf_jit_32.h
@@ -69,6 +69,7 @@
69#define ARM_INST_CMP_I 0x03500000 69#define ARM_INST_CMP_I 0x03500000
70 70
71#define ARM_INST_EOR_R 0x00200000 71#define ARM_INST_EOR_R 0x00200000
72#define ARM_INST_EOR_I 0x02200000
72 73
73#define ARM_INST_LDRB_I 0x05d00000 74#define ARM_INST_LDRB_I 0x05d00000
74#define ARM_INST_LDRB_R 0x07d00000 75#define ARM_INST_LDRB_R 0x07d00000
@@ -135,6 +136,7 @@
135#define ARM_CMP_I(rn, imm) _AL3_I(ARM_INST_CMP, 0, rn, imm) 136#define ARM_CMP_I(rn, imm) _AL3_I(ARM_INST_CMP, 0, rn, imm)
136 137
137#define ARM_EOR_R(rd, rn, rm) _AL3_R(ARM_INST_EOR, rd, rn, rm) 138#define ARM_EOR_R(rd, rn, rm) _AL3_R(ARM_INST_EOR, rd, rn, rm)
139#define ARM_EOR_I(rd, rn, imm) _AL3_I(ARM_INST_EOR, rd, rn, imm)
138 140
139#define ARM_LDR_I(rt, rn, off) (ARM_INST_LDR_I | (rt) << 12 | (rn) << 16 \ 141#define ARM_LDR_I(rt, rn, off) (ARM_INST_LDR_I | (rt) << 12 | (rn) << 16 \
140 | (off)) 142 | (off))
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-26 23:30:35 -0500