diff options
Diffstat (limited to 'arch/arm')
276 files changed, 5791 insertions, 4883 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index eb91022b90ba..38b5d5dad8e4 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig | |||
| @@ -673,6 +673,7 @@ config ARCH_TEGRA | |||
| 673 | select HAVE_CLK | 673 | select HAVE_CLK |
| 674 | select HAVE_SMP | 674 | select HAVE_SMP |
| 675 | select MIGHT_HAVE_CACHE_L2X0 | 675 | select MIGHT_HAVE_CACHE_L2X0 |
| 676 | select SOC_BUS | ||
| 676 | select SPARSE_IRQ | 677 | select SPARSE_IRQ |
| 677 | select USE_OF | 678 | select USE_OF |
| 678 | help | 679 | help |
| @@ -777,6 +778,7 @@ config ARCH_S3C24XX | |||
| 777 | select HAVE_S3C2410_I2C if I2C | 778 | select HAVE_S3C2410_I2C if I2C |
| 778 | select HAVE_S3C2410_WATCHDOG if WATCHDOG | 779 | select HAVE_S3C2410_WATCHDOG if WATCHDOG |
| 779 | select HAVE_S3C_RTC if RTC_CLASS | 780 | select HAVE_S3C_RTC if RTC_CLASS |
| 781 | select MULTI_IRQ_HANDLER | ||
| 780 | select NEED_MACH_GPIO_H | 782 | select NEED_MACH_GPIO_H |
| 781 | select NEED_MACH_IO_H | 783 | select NEED_MACH_IO_H |
| 782 | help | 784 | help |
| @@ -938,16 +940,8 @@ config ARCH_NOMADIK | |||
| 938 | help | 940 | help |
| 939 | Support for the Nomadik platform by ST-Ericsson | 941 | Support for the Nomadik platform by ST-Ericsson |
| 940 | 942 | ||
| 941 | config PLAT_SPEAR | 943 | config PLAT_SPEAR_SINGLE |
| 942 | bool "ST SPEAr" | 944 | bool "ST SPEAr" |
| 943 | select ARCH_HAS_CPUFREQ | ||
| 944 | select ARCH_REQUIRE_GPIOLIB | ||
| 945 | select ARM_AMBA | ||
| 946 | select CLKDEV_LOOKUP | ||
| 947 | select CLKSRC_MMIO | ||
| 948 | select COMMON_CLK | ||
| 949 | select GENERIC_CLOCKEVENTS | ||
| 950 | select HAVE_CLK | ||
| 951 | help | 945 | help |
| 952 | Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx). | 946 | Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx). |
| 953 | 947 | ||
| @@ -1109,7 +1103,7 @@ source "arch/arm/plat-samsung/Kconfig" | |||
| 1109 | 1103 | ||
| 1110 | source "arch/arm/mach-socfpga/Kconfig" | 1104 | source "arch/arm/mach-socfpga/Kconfig" |
| 1111 | 1105 | ||
| 1112 | source "arch/arm/plat-spear/Kconfig" | 1106 | source "arch/arm/mach-spear/Kconfig" |
| 1113 | 1107 | ||
| 1114 | source "arch/arm/mach-s3c24xx/Kconfig" | 1108 | source "arch/arm/mach-s3c24xx/Kconfig" |
| 1115 | 1109 | ||
| @@ -1178,6 +1172,7 @@ config PLAT_VERSATILE | |||
| 1178 | config ARM_TIMER_SP804 | 1172 | config ARM_TIMER_SP804 |
| 1179 | bool | 1173 | bool |
| 1180 | select CLKSRC_MMIO | 1174 | select CLKSRC_MMIO |
| 1175 | select CLKSRC_OF if OF | ||
| 1181 | select HAVE_SCHED_CLOCK | 1176 | select HAVE_SCHED_CLOCK |
| 1182 | 1177 | ||
| 1183 | source arch/arm/mm/Kconfig | 1178 | source arch/arm/mm/Kconfig |
| @@ -1188,9 +1183,9 @@ config ARM_NR_BANKS | |||
| 1188 | default 8 | 1183 | default 8 |
| 1189 | 1184 | ||
| 1190 | config IWMMXT | 1185 | config IWMMXT |
| 1191 | bool "Enable iWMMXt support" | 1186 | bool "Enable iWMMXt support" if !CPU_PJ4 |
| 1192 | depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 | 1187 | depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 |
| 1193 | default y if PXA27x || PXA3xx || ARCH_MMP | 1188 | default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 |
| 1194 | help | 1189 | help |
| 1195 | Enable support for iWMMXt context switching at run time if | 1190 | Enable support for iWMMXt context switching at run time if |
| 1196 | running on a CPU that supports it. | 1191 | running on a CPU that supports it. |
| @@ -1444,6 +1439,16 @@ config ARM_ERRATA_775420 | |||
| 1444 | to deadlock. This workaround puts DSB before executing ISB if | 1439 | to deadlock. This workaround puts DSB before executing ISB if |
| 1445 | an abort may occur on cache maintenance. | 1440 | an abort may occur on cache maintenance. |
| 1446 | 1441 | ||
| 1442 | config ARM_ERRATA_798181 | ||
| 1443 | bool "ARM errata: TLBI/DSB failure on Cortex-A15" | ||
| 1444 | depends on CPU_V7 && SMP | ||
| 1445 | help | ||
| 1446 | On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not | ||
| 1447 | adequately shooting down all use of the old entries. This | ||
| 1448 | option enables the Linux kernel workaround for this erratum | ||
| 1449 | which sends an IPI to the CPUs that are running the same ASID | ||
| 1450 | as the one being invalidated. | ||
| 1451 | |||
| 1447 | endmenu | 1452 | endmenu |
| 1448 | 1453 | ||
| 1449 | source "arch/arm/common/Kconfig" | 1454 | source "arch/arm/common/Kconfig" |
| @@ -1652,7 +1657,7 @@ config LOCAL_TIMERS | |||
| 1652 | bool "Use local timer interrupts" | 1657 | bool "Use local timer interrupts" |
| 1653 | depends on SMP | 1658 | depends on SMP |
| 1654 | default y | 1659 | default y |
| 1655 | select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT) | 1660 | select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !CLKSRC_EXYNOS_MCT) |
| 1656 | help | 1661 | help |
| 1657 | Enable support for local timers on SMP platforms, rather then the | 1662 | Enable support for local timers on SMP platforms, rather then the |
| 1658 | legacy IPI broadcast method. Local timers allows the system | 1663 | legacy IPI broadcast method. Local timers allows the system |
diff --git a/arch/arm/Makefile b/arch/arm/Makefile index ee4605f400b0..8276536815a8 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile | |||
| @@ -191,9 +191,7 @@ machine-$(CONFIG_ARCH_VT8500) += vt8500 | |||
| 191 | machine-$(CONFIG_ARCH_W90X900) += w90x900 | 191 | machine-$(CONFIG_ARCH_W90X900) += w90x900 |
| 192 | machine-$(CONFIG_FOOTBRIDGE) += footbridge | 192 | machine-$(CONFIG_FOOTBRIDGE) += footbridge |
| 193 | machine-$(CONFIG_ARCH_SOCFPGA) += socfpga | 193 | machine-$(CONFIG_ARCH_SOCFPGA) += socfpga |
| 194 | machine-$(CONFIG_ARCH_SPEAR13XX) += spear13xx | 194 | machine-$(CONFIG_PLAT_SPEAR) += spear |
| 195 | machine-$(CONFIG_ARCH_SPEAR3XX) += spear3xx | ||
| 196 | machine-$(CONFIG_MACH_SPEAR600) += spear6xx | ||
| 197 | machine-$(CONFIG_ARCH_VIRT) += virt | 195 | machine-$(CONFIG_ARCH_VIRT) += virt |
| 198 | machine-$(CONFIG_ARCH_ZYNQ) += zynq | 196 | machine-$(CONFIG_ARCH_ZYNQ) += zynq |
| 199 | machine-$(CONFIG_ARCH_SUNXI) += sunxi | 197 | machine-$(CONFIG_ARCH_SUNXI) += sunxi |
| @@ -207,7 +205,6 @@ plat-$(CONFIG_PLAT_ORION) += orion | |||
| 207 | plat-$(CONFIG_PLAT_PXA) += pxa | 205 | plat-$(CONFIG_PLAT_PXA) += pxa |
| 208 | plat-$(CONFIG_PLAT_S3C24XX) += samsung | 206 | plat-$(CONFIG_PLAT_S3C24XX) += samsung |
| 209 | plat-$(CONFIG_PLAT_S5P) += samsung | 207 | plat-$(CONFIG_PLAT_S5P) += samsung |
| 210 | plat-$(CONFIG_PLAT_SPEAR) += spear | ||
| 211 | plat-$(CONFIG_PLAT_VERSATILE) += versatile | 208 | plat-$(CONFIG_PLAT_VERSATILE) += versatile |
| 212 | 209 | ||
| 213 | ifeq ($(CONFIG_ARCH_EBSA110),y) | 210 | ifeq ($(CONFIG_ARCH_EBSA110),y) |
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 9c6255884cbb..e35b0a7ac77b 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile | |||
| @@ -31,6 +31,11 @@ dtb-$(CONFIG_ARCH_AT91) += at91sam9g25ek.dtb | |||
| 31 | dtb-$(CONFIG_ARCH_AT91) += at91sam9g35ek.dtb | 31 | dtb-$(CONFIG_ARCH_AT91) += at91sam9g35ek.dtb |
| 32 | dtb-$(CONFIG_ARCH_AT91) += at91sam9x25ek.dtb | 32 | dtb-$(CONFIG_ARCH_AT91) += at91sam9x25ek.dtb |
| 33 | dtb-$(CONFIG_ARCH_AT91) += at91sam9x35ek.dtb | 33 | dtb-$(CONFIG_ARCH_AT91) += at91sam9x35ek.dtb |
| 34 | # sama5d3 | ||
| 35 | dtb-$(CONFIG_ARCH_AT91) += sama5d31ek.dtb | ||
| 36 | dtb-$(CONFIG_ARCH_AT91) += sama5d33ek.dtb | ||
| 37 | dtb-$(CONFIG_ARCH_AT91) += sama5d34ek.dtb | ||
| 38 | dtb-$(CONFIG_ARCH_AT91) += sama5d35ek.dtb | ||
| 34 | 39 | ||
| 35 | dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb | 40 | dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb |
| 36 | dtb-$(CONFIG_ARCH_BCM) += bcm11351-brt.dtb | 41 | dtb-$(CONFIG_ARCH_BCM) += bcm11351-brt.dtb |
| @@ -165,6 +170,8 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \ | |||
| 165 | tegra30-cardhu-a04.dtb \ | 170 | tegra30-cardhu-a04.dtb \ |
| 166 | tegra114-dalmore.dtb \ | 171 | tegra114-dalmore.dtb \ |
| 167 | tegra114-pluto.dtb | 172 | tegra114-pluto.dtb |
| 173 | dtb-$(CONFIG_ARCH_VERSATILE) += versatile-ab.dtb \ | ||
| 174 | versatile-pb.dtb | ||
| 168 | dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2p-ca5s.dtb \ | 175 | dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2p-ca5s.dtb \ |
| 169 | vexpress-v2p-ca9.dtb \ | 176 | vexpress-v2p-ca9.dtb \ |
| 170 | vexpress-v2p-ca15-tc1.dtb \ | 177 | vexpress-v2p-ca15-tc1.dtb \ |
diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts index dd0c57dd9f30..3234875824dc 100644 --- a/arch/arm/boot/dts/armada-370-mirabox.dts +++ b/arch/arm/boot/dts/armada-370-mirabox.dts | |||
| @@ -54,7 +54,7 @@ | |||
| 54 | }; | 54 | }; |
| 55 | 55 | ||
| 56 | mvsdio@d00d4000 { | 56 | mvsdio@d00d4000 { |
| 57 | pinctrl-0 = <&sdio_pins2>; | 57 | pinctrl-0 = <&sdio_pins3>; |
| 58 | pinctrl-names = "default"; | 58 | pinctrl-names = "default"; |
| 59 | status = "okay"; | 59 | status = "okay"; |
| 60 | /* | 60 | /* |
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi index 8188d138020e..a195debb67d3 100644 --- a/arch/arm/boot/dts/armada-370.dtsi +++ b/arch/arm/boot/dts/armada-370.dtsi | |||
| @@ -59,6 +59,12 @@ | |||
| 59 | "mpp50", "mpp51", "mpp52"; | 59 | "mpp50", "mpp51", "mpp52"; |
| 60 | marvell,function = "sd0"; | 60 | marvell,function = "sd0"; |
| 61 | }; | 61 | }; |
| 62 | |||
| 63 | sdio_pins3: sdio-pins3 { | ||
| 64 | marvell,pins = "mpp48", "mpp49", "mpp50", | ||
| 65 | "mpp51", "mpp52", "mpp53"; | ||
| 66 | marvell,function = "sd0"; | ||
| 67 | }; | ||
| 62 | }; | 68 | }; |
| 63 | 69 | ||
| 64 | gpio0: gpio@d0018100 { | 70 | gpio0: gpio@d0018100 { |
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi index 6b1d4cab24c2..2b6e30cbc48b 100644 --- a/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/at91sam9g45.dtsi | |||
| @@ -108,6 +108,7 @@ | |||
| 108 | compatible = "atmel,at91sam9g45-dma"; | 108 | compatible = "atmel,at91sam9g45-dma"; |
| 109 | reg = <0xffffec00 0x200>; | 109 | reg = <0xffffec00 0x200>; |
| 110 | interrupts = <21 4 0>; | 110 | interrupts = <21 4 0>; |
| 111 | #dma-cells = <2>; | ||
| 111 | }; | 112 | }; |
| 112 | 113 | ||
| 113 | pinctrl@fffff200 { | 114 | pinctrl@fffff200 { |
| @@ -512,6 +513,8 @@ | |||
| 512 | compatible = "atmel,hsmci"; | 513 | compatible = "atmel,hsmci"; |
| 513 | reg = <0xfff80000 0x600>; | 514 | reg = <0xfff80000 0x600>; |
| 514 | interrupts = <11 4 0>; | 515 | interrupts = <11 4 0>; |
| 516 | dmas = <&dma 1 0>; | ||
| 517 | dma-names = "rxtx"; | ||
| 515 | #address-cells = <1>; | 518 | #address-cells = <1>; |
| 516 | #size-cells = <0>; | 519 | #size-cells = <0>; |
| 517 | status = "disabled"; | 520 | status = "disabled"; |
| @@ -521,6 +524,8 @@ | |||
| 521 | compatible = "atmel,hsmci"; | 524 | compatible = "atmel,hsmci"; |
| 522 | reg = <0xfffd0000 0x600>; | 525 | reg = <0xfffd0000 0x600>; |
| 523 | interrupts = <29 4 0>; | 526 | interrupts = <29 4 0>; |
| 527 | dmas = <&dma 1 13>; | ||
| 528 | dma-names = "rxtx"; | ||
| 524 | #address-cells = <1>; | 529 | #address-cells = <1>; |
| 525 | #size-cells = <0>; | 530 | #size-cells = <0>; |
| 526 | status = "disabled"; | 531 | status = "disabled"; |
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi index 7750f98dd764..b0bd70485f87 100644 --- a/arch/arm/boot/dts/at91sam9n12.dtsi +++ b/arch/arm/boot/dts/at91sam9n12.dtsi | |||
| @@ -89,6 +89,8 @@ | |||
| 89 | compatible = "atmel,hsmci"; | 89 | compatible = "atmel,hsmci"; |
| 90 | reg = <0xf0008000 0x600>; | 90 | reg = <0xf0008000 0x600>; |
| 91 | interrupts = <12 4 0>; | 91 | interrupts = <12 4 0>; |
| 92 | dmas = <&dma 1 0>; | ||
| 93 | dma-names = "rxtx"; | ||
| 92 | #address-cells = <1>; | 94 | #address-cells = <1>; |
| 93 | #size-cells = <0>; | 95 | #size-cells = <0>; |
| 94 | status = "disabled"; | 96 | status = "disabled"; |
| @@ -110,6 +112,7 @@ | |||
| 110 | compatible = "atmel,at91sam9g45-dma"; | 112 | compatible = "atmel,at91sam9g45-dma"; |
| 111 | reg = <0xffffec00 0x200>; | 113 | reg = <0xffffec00 0x200>; |
| 112 | interrupts = <20 4 0>; | 114 | interrupts = <20 4 0>; |
| 115 | #dma-cells = <2>; | ||
| 113 | }; | 116 | }; |
| 114 | 117 | ||
| 115 | pinctrl@fffff400 { | 118 | pinctrl@fffff400 { |
| @@ -360,6 +363,9 @@ | |||
| 360 | compatible = "atmel,at91sam9x5-i2c"; | 363 | compatible = "atmel,at91sam9x5-i2c"; |
| 361 | reg = <0xf8010000 0x100>; | 364 | reg = <0xf8010000 0x100>; |
| 362 | interrupts = <9 4 6>; | 365 | interrupts = <9 4 6>; |
| 366 | dmas = <&dma 1 13>, | ||
| 367 | <&dma 1 14>; | ||
| 368 | dma-names = "tx", "rx"; | ||
| 363 | #address-cells = <1>; | 369 | #address-cells = <1>; |
| 364 | #size-cells = <0>; | 370 | #size-cells = <0>; |
| 365 | status = "disabled"; | 371 | status = "disabled"; |
| @@ -369,6 +375,9 @@ | |||
| 369 | compatible = "atmel,at91sam9x5-i2c"; | 375 | compatible = "atmel,at91sam9x5-i2c"; |
| 370 | reg = <0xf8014000 0x100>; | 376 | reg = <0xf8014000 0x100>; |
| 371 | interrupts = <10 4 6>; | 377 | interrupts = <10 4 6>; |
| 378 | dmas = <&dma 1 15>, | ||
| 379 | <&dma 1 16>; | ||
| 380 | dma-names = "tx", "rx"; | ||
| 372 | #address-cells = <1>; | 381 | #address-cells = <1>; |
| 373 | #size-cells = <0>; | 382 | #size-cells = <0>; |
| 374 | status = "disabled"; | 383 | status = "disabled"; |
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi index a98c0d50fbbe..cbb94732786c 100644 --- a/arch/arm/boot/dts/at91sam9x5.dtsi +++ b/arch/arm/boot/dts/at91sam9x5.dtsi | |||
| @@ -104,12 +104,14 @@ | |||
| 104 | compatible = "atmel,at91sam9g45-dma"; | 104 | compatible = "atmel,at91sam9g45-dma"; |
| 105 | reg = <0xffffec00 0x200>; | 105 | reg = <0xffffec00 0x200>; |
| 106 | interrupts = <20 4 0>; | 106 | interrupts = <20 4 0>; |
| 107 | #dma-cells = <2>; | ||
| 107 | }; | 108 | }; |
| 108 | 109 | ||
| 109 | dma1: dma-controller@ffffee00 { | 110 | dma1: dma-controller@ffffee00 { |
| 110 | compatible = "atmel,at91sam9g45-dma"; | 111 | compatible = "atmel,at91sam9g45-dma"; |
| 111 | reg = <0xffffee00 0x200>; | 112 | reg = <0xffffee00 0x200>; |
| 112 | interrupts = <21 4 0>; | 113 | interrupts = <21 4 0>; |
| 114 | #dma-cells = <2>; | ||
| 113 | }; | 115 | }; |
| 114 | 116 | ||
| 115 | pinctrl@fffff400 { | 117 | pinctrl@fffff400 { |
| @@ -399,6 +401,8 @@ | |||
| 399 | compatible = "atmel,hsmci"; | 401 | compatible = "atmel,hsmci"; |
| 400 | reg = <0xf0008000 0x600>; | 402 | reg = <0xf0008000 0x600>; |
| 401 | interrupts = <12 4 0>; | 403 | interrupts = <12 4 0>; |
| 404 | dmas = <&dma0 1 0>; | ||
| 405 | dma-names = "rxtx"; | ||
| 402 | #address-cells = <1>; | 406 | #address-cells = <1>; |
| 403 | #size-cells = <0>; | 407 | #size-cells = <0>; |
| 404 | status = "disabled"; | 408 | status = "disabled"; |
| @@ -408,6 +412,8 @@ | |||
| 408 | compatible = "atmel,hsmci"; | 412 | compatible = "atmel,hsmci"; |
| 409 | reg = <0xf000c000 0x600>; | 413 | reg = <0xf000c000 0x600>; |
| 410 | interrupts = <26 4 0>; | 414 | interrupts = <26 4 0>; |
| 415 | dmas = <&dma1 1 0>; | ||
| 416 | dma-names = "rxtx"; | ||
| 411 | #address-cells = <1>; | 417 | #address-cells = <1>; |
| 412 | #size-cells = <0>; | 418 | #size-cells = <0>; |
| 413 | status = "disabled"; | 419 | status = "disabled"; |
| @@ -469,6 +475,9 @@ | |||
| 469 | compatible = "atmel,at91sam9x5-i2c"; | 475 | compatible = "atmel,at91sam9x5-i2c"; |
| 470 | reg = <0xf8010000 0x100>; | 476 | reg = <0xf8010000 0x100>; |
| 471 | interrupts = <9 4 6>; | 477 | interrupts = <9 4 6>; |
| 478 | dmas = <&dma0 1 7>, | ||
| 479 | <&dma0 1 8>; | ||
| 480 | dma-names = "tx", "rx"; | ||
| 472 | #address-cells = <1>; | 481 | #address-cells = <1>; |
| 473 | #size-cells = <0>; | 482 | #size-cells = <0>; |
| 474 | status = "disabled"; | 483 | status = "disabled"; |
| @@ -478,6 +487,9 @@ | |||
| 478 | compatible = "atmel,at91sam9x5-i2c"; | 487 | compatible = "atmel,at91sam9x5-i2c"; |
| 479 | reg = <0xf8014000 0x100>; | 488 | reg = <0xf8014000 0x100>; |
| 480 | interrupts = <10 4 6>; | 489 | interrupts = <10 4 6>; |
| 490 | dmas = <&dma1 1 5>, | ||
| 491 | <&dma1 1 6>; | ||
| 492 | dma-names = "tx", "rx"; | ||
| 481 | #address-cells = <1>; | 493 | #address-cells = <1>; |
| 482 | #size-cells = <0>; | 494 | #size-cells = <0>; |
| 483 | status = "disabled"; | 495 | status = "disabled"; |
| @@ -487,6 +499,9 @@ | |||
| 487 | compatible = "atmel,at91sam9x5-i2c"; | 499 | compatible = "atmel,at91sam9x5-i2c"; |
| 488 | reg = <0xf8018000 0x100>; | 500 | reg = <0xf8018000 0x100>; |
| 489 | interrupts = <11 4 6>; | 501 | interrupts = <11 4 6>; |
| 502 | dmas = <&dma0 1 9>, | ||
| 503 | <&dma0 1 10>; | ||
| 504 | dma-names = "tx", "rx"; | ||
| 490 | #address-cells = <1>; | 505 | #address-cells = <1>; |
| 491 | #size-cells = <0>; | 506 | #size-cells = <0>; |
| 492 | status = "disabled"; | 507 | status = "disabled"; |
diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi index 9de93096601a..aaa63d0a8096 100644 --- a/arch/arm/boot/dts/dbx5x0.dtsi +++ b/arch/arm/boot/dts/dbx5x0.dtsi | |||
| @@ -191,8 +191,8 @@ | |||
| 191 | 191 | ||
| 192 | prcmu: prcmu@80157000 { | 192 | prcmu: prcmu@80157000 { |
| 193 | compatible = "stericsson,db8500-prcmu"; | 193 | compatible = "stericsson,db8500-prcmu"; |
| 194 | reg = <0x80157000 0x1000>; | 194 | reg = <0x80157000 0x1000>, <0x801b0000 0x8000>, <0x801b8000 0x1000>; |
| 195 | reg-names = "prcmu"; | 195 | reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm"; |
| 196 | interrupts = <0 47 0x4>; | 196 | interrupts = <0 47 0x4>; |
| 197 | #address-cells = <1>; | 197 | #address-cells = <1>; |
| 198 | #size-cells = <1>; | 198 | #size-cells = <1>; |
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index 2feffc70814c..49a2786e00b9 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi | |||
| @@ -47,6 +47,28 @@ | |||
| 47 | <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>; | 47 | <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>; |
| 48 | }; | 48 | }; |
| 49 | 49 | ||
| 50 | mct@10050000 { | ||
| 51 | compatible = "samsung,exynos4210-mct"; | ||
| 52 | reg = <0x10050000 0x800>; | ||
| 53 | interrupt-controller; | ||
| 54 | #interrups-cells = <2>; | ||
| 55 | interrupt-parent = <&mct_map>; | ||
| 56 | interrupts = <0 0>, <1 0>, <2 0>, <3 0>, | ||
| 57 | <4 0>, <5 0>; | ||
| 58 | |||
| 59 | mct_map: mct-map { | ||
| 60 | #interrupt-cells = <2>; | ||
| 61 | #address-cells = <0>; | ||
| 62 | #size-cells = <0>; | ||
| 63 | interrupt-map = <0x0 0 &gic 0 57 0>, | ||
| 64 | <0x1 0 &gic 0 69 0>, | ||
| 65 | <0x2 0 &combiner 12 6>, | ||
| 66 | <0x3 0 &combiner 12 7>, | ||
| 67 | <0x4 0 &gic 0 42 0>, | ||
| 68 | <0x5 0 &gic 0 48 0>; | ||
| 69 | }; | ||
| 70 | }; | ||
| 71 | |||
| 50 | pinctrl_0: pinctrl@11400000 { | 72 | pinctrl_0: pinctrl@11400000 { |
| 51 | compatible = "samsung,exynos4210-pinctrl"; | 73 | compatible = "samsung,exynos4210-pinctrl"; |
| 52 | reg = <0x11400000 0x1000>; | 74 | reg = <0x11400000 0x1000>; |
diff --git a/arch/arm/boot/dts/exynos4212.dtsi b/arch/arm/boot/dts/exynos4212.dtsi index c6ae2005961f..36d4299789ef 100644 --- a/arch/arm/boot/dts/exynos4212.dtsi +++ b/arch/arm/boot/dts/exynos4212.dtsi | |||
| @@ -25,4 +25,26 @@ | |||
| 25 | gic:interrupt-controller@10490000 { | 25 | gic:interrupt-controller@10490000 { |
| 26 | cpu-offset = <0x8000>; | 26 | cpu-offset = <0x8000>; |
| 27 | }; | 27 | }; |
| 28 | |||
| 29 | mct@10050000 { | ||
| 30 | compatible = "samsung,exynos4412-mct"; | ||
| 31 | reg = <0x10050000 0x800>; | ||
| 32 | interrupt-controller; | ||
| 33 | #interrups-cells = <2>; | ||
| 34 | interrupt-parent = <&mct_map>; | ||
| 35 | interrupts = <0 0>, <1 0>, <2 0>, <3 0>, | ||
| 36 | <4 0>, <5 0>; | ||
| 37 | |||
| 38 | mct_map: mct-map { | ||
| 39 | #interrupt-cells = <2>; | ||
| 40 | #address-cells = <0>; | ||
| 41 | #size-cells = <0>; | ||
| 42 | interrupt-map = <0x0 0 &gic 0 57 0>, | ||
| 43 | <0x1 0 &combiner 12 5>, | ||
| 44 | <0x2 0 &combiner 12 6>, | ||
| 45 | <0x3 0 &combiner 12 7>, | ||
| 46 | <0x4 0 &gic 1 12 0>, | ||
| 47 | <0x5 0 &gic 1 12 0>; | ||
| 48 | }; | ||
| 49 | }; | ||
| 28 | }; | 50 | }; |
diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi index d7dfe312772a..821c9fdd1e3b 100644 --- a/arch/arm/boot/dts/exynos4412.dtsi +++ b/arch/arm/boot/dts/exynos4412.dtsi | |||
| @@ -25,4 +25,28 @@ | |||
| 25 | gic:interrupt-controller@10490000 { | 25 | gic:interrupt-controller@10490000 { |
| 26 | cpu-offset = <0x4000>; | 26 | cpu-offset = <0x4000>; |
| 27 | }; | 27 | }; |
| 28 | |||
| 29 | mct@10050000 { | ||
| 30 | compatible = "samsung,exynos4412-mct"; | ||
| 31 | reg = <0x10050000 0x800>; | ||
| 32 | interrupt-controller; | ||
| 33 | #interrups-cells = <2>; | ||
| 34 | interrupt-parent = <&mct_map>; | ||
| 35 | interrupts = <0 0>, <1 0>, <2 0>, <3 0>, | ||
| 36 | <4 0>, <5 0>, <6 0>, <7 0>; | ||
| 37 | |||
| 38 | mct_map: mct-map { | ||
| 39 | #interrupt-cells = <2>; | ||
| 40 | #address-cells = <0>; | ||
| 41 | #size-cells = <0>; | ||
| 42 | interrupt-map = <0x0 0 &gic 0 57 0>, | ||
| 43 | <0x1 0 &combiner 12 5>, | ||
| 44 | <0x2 0 &combiner 12 6>, | ||
| 45 | <0x3 0 &combiner 12 7>, | ||
| 46 | <0x4 0 &gic 1 12 0>, | ||
| 47 | <0x5 0 &gic 1 12 0>, | ||
| 48 | <0x6 0 &gic 1 12 0>, | ||
| 49 | <0x7 0 &gic 1 12 0>; | ||
| 50 | }; | ||
| 51 | }; | ||
| 28 | }; | 52 | }; |
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index b1ac73e21c80..c60108e0d27e 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi | |||
| @@ -69,6 +69,28 @@ | |||
| 69 | <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>; | 69 | <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>; |
| 70 | }; | 70 | }; |
| 71 | 71 | ||
| 72 | mct@101C0000 { | ||
| 73 | compatible = "samsung,exynos4210-mct"; | ||
| 74 | reg = <0x101C0000 0x800>; | ||
| 75 | interrupt-controller; | ||
| 76 | #interrups-cells = <2>; | ||
| 77 | interrupt-parent = <&mct_map>; | ||
| 78 | interrupts = <0 0>, <1 0>, <2 0>, <3 0>, | ||
| 79 | <4 0>, <5 0>; | ||
| 80 | |||
| 81 | mct_map: mct-map { | ||
| 82 | #interrupt-cells = <2>; | ||
| 83 | #address-cells = <0>; | ||
| 84 | #size-cells = <0>; | ||
| 85 | interrupt-map = <0x0 0 &combiner 23 3>, | ||
| 86 | <0x1 0 &combiner 23 4>, | ||
| 87 | <0x2 0 &combiner 25 2>, | ||
| 88 | <0x3 0 &combiner 25 3>, | ||
| 89 | <0x4 0 &gic 0 120 0>, | ||
| 90 | <0x5 0 &gic 0 121 0>; | ||
| 91 | }; | ||
| 92 | }; | ||
| 93 | |||
| 72 | watchdog { | 94 | watchdog { |
| 73 | compatible = "samsung,s3c2410-wdt"; | 95 | compatible = "samsung,s3c2410-wdt"; |
| 74 | reg = <0x101D0000 0x100>; | 96 | reg = <0x101D0000 0x100>; |
diff --git a/arch/arm/boot/dts/integratorcp.dts b/arch/arm/boot/dts/integratorcp.dts index 8b119399025a..ff1aea0ee043 100644 --- a/arch/arm/boot/dts/integratorcp.dts +++ b/arch/arm/boot/dts/integratorcp.dts | |||
| @@ -24,15 +24,15 @@ | |||
| 24 | }; | 24 | }; |
| 25 | 25 | ||
| 26 | timer0: timer@13000000 { | 26 | timer0: timer@13000000 { |
| 27 | compatible = "arm,sp804", "arm,primecell"; | 27 | compatible = "arm,integrator-cp-timer"; |
| 28 | }; | 28 | }; |
| 29 | 29 | ||
| 30 | timer1: timer@13000100 { | 30 | timer1: timer@13000100 { |
| 31 | compatible = "arm,sp804", "arm,primecell"; | 31 | compatible = "arm,integrator-cp-timer"; |
| 32 | }; | 32 | }; |
| 33 | 33 | ||
| 34 | timer2: timer@13000200 { | 34 | timer2: timer@13000200 { |
| 35 | compatible = "arm,sp804", "arm,primecell"; | 35 | compatible = "arm,integrator-cp-timer"; |
| 36 | }; | 36 | }; |
| 37 | 37 | ||
| 38 | pic: pic@14000000 { | 38 | pic: pic@14000000 { |
diff --git a/arch/arm/boot/dts/kirkwood-goflexnet.dts b/arch/arm/boot/dts/kirkwood-goflexnet.dts index bd83b8fc7c83..c3573be7b92c 100644 --- a/arch/arm/boot/dts/kirkwood-goflexnet.dts +++ b/arch/arm/boot/dts/kirkwood-goflexnet.dts | |||
| @@ -77,6 +77,7 @@ | |||
| 77 | }; | 77 | }; |
| 78 | 78 | ||
| 79 | nand@3000000 { | 79 | nand@3000000 { |
| 80 | chip-delay = <40>; | ||
| 80 | status = "okay"; | 81 | status = "okay"; |
| 81 | 82 | ||
| 82 | partition@0 { | 83 | partition@0 { |
diff --git a/arch/arm/boot/dts/orion5x.dtsi b/arch/arm/boot/dts/orion5x.dtsi index 8aad00f81ed9..f7bec3b1ba32 100644 --- a/arch/arm/boot/dts/orion5x.dtsi +++ b/arch/arm/boot/dts/orion5x.dtsi | |||
| @@ -13,6 +13,9 @@ | |||
| 13 | compatible = "marvell,orion5x"; | 13 | compatible = "marvell,orion5x"; |
| 14 | interrupt-parent = <&intc>; | 14 | interrupt-parent = <&intc>; |
| 15 | 15 | ||
| 16 | aliases { | ||
| 17 | gpio0 = &gpio0; | ||
| 18 | }; | ||
| 16 | intc: interrupt-controller { | 19 | intc: interrupt-controller { |
| 17 | compatible = "marvell,orion-intc", "marvell,intc"; | 20 | compatible = "marvell,orion-intc", "marvell,intc"; |
| 18 | interrupt-controller; | 21 | interrupt-controller; |
| @@ -32,7 +35,9 @@ | |||
| 32 | #gpio-cells = <2>; | 35 | #gpio-cells = <2>; |
| 33 | gpio-controller; | 36 | gpio-controller; |
| 34 | reg = <0x10100 0x40>; | 37 | reg = <0x10100 0x40>; |
| 35 | ngpio = <32>; | 38 | ngpios = <32>; |
| 39 | interrupt-controller; | ||
| 40 | #interrupt-cells = <2>; | ||
| 36 | interrupts = <6>, <7>, <8>, <9>; | 41 | interrupts = <6>, <7>, <8>, <9>; |
| 37 | }; | 42 | }; |
| 38 | 43 | ||
| @@ -91,7 +96,7 @@ | |||
| 91 | reg = <0x90000 0x10000>, | 96 | reg = <0x90000 0x10000>, |
| 92 | <0xf2200000 0x800>; | 97 | <0xf2200000 0x800>; |
| 93 | reg-names = "regs", "sram"; | 98 | reg-names = "regs", "sram"; |
| 94 | interrupts = <22>; | 99 | interrupts = <28>; |
| 95 | status = "okay"; | 100 | status = "okay"; |
| 96 | }; | 101 | }; |
| 97 | }; | 102 | }; |
diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi new file mode 100644 index 000000000000..2e643ea51cce --- /dev/null +++ b/arch/arm/boot/dts/sama5d3.dtsi | |||
| @@ -0,0 +1,1046 @@ | |||
| 1 | /* | ||
| 2 | * sama5d3.dtsi - Device Tree Include file for SAMA5D3 family SoC | ||
| 3 | * applies to SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35 SoC | ||
| 4 | * | ||
| 5 | * Copyright (C) 2013 Atmel, | ||
| 6 | * 2013 Ludovic Desroches <ludovic.desroches@atmel.com> | ||
| 7 | * | ||
| 8 | * Licensed under GPLv2 or later. | ||
| 9 | */ | ||
| 10 | |||
| 11 | /include/ "skeleton.dtsi" | ||
| 12 | |||
| 13 | / { | ||
| 14 | model = "Atmel SAMA5D3 family SoC"; | ||
| 15 | compatible = "atmel,sama5d3", "atmel,sama5"; | ||
| 16 | interrupt-parent = <&aic>; | ||
| 17 | |||
| 18 | aliases { | ||
| 19 | serial0 = &dbgu; | ||
| 20 | serial1 = &usart0; | ||
| 21 | serial2 = &usart1; | ||
| 22 | serial3 = &usart2; | ||
| 23 | serial4 = &usart3; | ||
| 24 | gpio0 = &pioA; | ||
| 25 | gpio1 = &pioB; | ||
| 26 | gpio2 = &pioC; | ||
| 27 | gpio3 = &pioD; | ||
| 28 | gpio4 = &pioE; | ||
| 29 | tcb0 = &tcb0; | ||
| 30 | tcb1 = &tcb1; | ||
| 31 | i2c0 = &i2c0; | ||
| 32 | i2c1 = &i2c1; | ||
| 33 | i2c2 = &i2c2; | ||
| 34 | ssc0 = &ssc0; | ||
| 35 | ssc1 = &ssc1; | ||
| 36 | }; | ||
| 37 | cpus { | ||
| 38 | cpu@0 { | ||
| 39 | compatible = "arm,cortex-a5"; | ||
| 40 | }; | ||
| 41 | }; | ||
| 42 | |||
| 43 | memory { | ||
| 44 | reg = <0x20000000 0x8000000>; | ||
| 45 | }; | ||
| 46 | |||
| 47 | ahb { | ||
| 48 | compatible = "simple-bus"; | ||
| 49 | #address-cells = <1>; | ||
| 50 | #size-cells = <1>; | ||
| 51 | ranges; | ||
| 52 | |||
| 53 | apb { | ||
| 54 | compatible = "simple-bus"; | ||
| 55 | #address-cells = <1>; | ||
| 56 | #size-cells = <1>; | ||
| 57 | ranges; | ||
| 58 | |||
| 59 | mmc0: mmc@f0000000 { | ||
| 60 | compatible = "atmel,hsmci"; | ||
| 61 | reg = <0xf0000000 0x600>; | ||
| 62 | interrupts = <21 4 0>; | ||
| 63 | dmas = <&dma0 2 0>; | ||
| 64 | dma-names = "rxtx"; | ||
| 65 | pinctrl-names = "default"; | ||
| 66 | pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7>; | ||
| 67 | status = "disabled"; | ||
| 68 | #address-cells = <1>; | ||
| 69 | #size-cells = <0>; | ||
| 70 | }; | ||
| 71 | |||
| 72 | spi0: spi@f0004000 { | ||
| 73 | #address-cells = <1>; | ||
| 74 | #size-cells = <0>; | ||
| 75 | compatible = "atmel,at91sam9x5-spi"; | ||
| 76 | reg = <0xf0004000 0x100>; | ||
| 77 | interrupts = <24 4 3>; | ||
| 78 | cs-gpios = <&pioD 13 0 | ||
| 79 | &pioD 14 0 /* conflicts with SCK0 and CANRX0 */ | ||
| 80 | &pioD 15 0 /* conflicts with CTS0 and CANTX0 */ | ||
| 81 | &pioD 16 0 /* conflicts with RTS0 and PWMFI3 */ | ||
| 82 | >; | ||
| 83 | pinctrl-names = "default"; | ||
| 84 | pinctrl-0 = <&pinctrl_spi0>; | ||
| 85 | status = "disabled"; | ||
| 86 | }; | ||
| 87 | |||
| 88 | ssc0: ssc@f0008000 { | ||
| 89 | compatible = "atmel,at91sam9g45-ssc"; | ||
| 90 | reg = <0xf0008000 0x4000>; | ||
| 91 | interrupts = <38 4 4>; | ||
| 92 | pinctrl-names = "default"; | ||
| 93 | pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; | ||
| 94 | status = "disabled"; | ||
| 95 | }; | ||
| 96 | |||
| 97 | can0: can@f000c000 { | ||
| 98 | compatible = "atmel,at91sam9x5-can"; | ||
| 99 | reg = <0xf000c000 0x300>; | ||
| 100 | interrupts = <40 4 3>; | ||
| 101 | pinctrl-names = "default"; | ||
| 102 | pinctrl-0 = <&pinctrl_can0_rx_tx>; | ||
| 103 | status = "disabled"; | ||
| 104 | }; | ||
| 105 | |||
| 106 | tcb0: timer@f0010000 { | ||
| 107 | compatible = "atmel,at91sam9x5-tcb"; | ||
| 108 | reg = <0xf0010000 0x100>; | ||
| 109 | interrupts = <26 4 0>; | ||
| 110 | }; | ||
| 111 | |||
| 112 | i2c0: i2c@f0014000 { | ||
| 113 | compatible = "atmel,at91sam9x5-i2c"; | ||
| 114 | reg = <0xf0014000 0x4000>; | ||
| 115 | interrupts = <18 4 6>; | ||
| 116 | dmas = <&dma0 2 7>, | ||
| 117 | <&dma0 2 8>; | ||
| 118 | dma-names = "tx", "rx"; | ||
| 119 | pinctrl-names = "default"; | ||
| 120 | pinctrl-0 = <&pinctrl_i2c0>; | ||
| 121 | #address-cells = <1>; | ||
| 122 | #size-cells = <0>; | ||
| 123 | status = "disabled"; | ||
| 124 | }; | ||
| 125 | |||
| 126 | i2c1: i2c@f0018000 { | ||
| 127 | compatible = "atmel,at91sam9x5-i2c"; | ||
| 128 | reg = <0xf0018000 0x4000>; | ||
| 129 | interrupts = <19 4 6>; | ||
| 130 | dmas = <&dma0 2 9>, | ||
| 131 | <&dma0 2 10>; | ||
| 132 | dma-names = "tx", "rx"; | ||
| 133 | pinctrl-names = "default"; | ||
| 134 | pinctrl-0 = <&pinctrl_i2c1>; | ||
| 135 | #address-cells = <1>; | ||
| 136 | #size-cells = <0>; | ||
| 137 | status = "disabled"; | ||
| 138 | }; | ||
| 139 | |||
| 140 | usart0: serial@f001c000 { | ||
| 141 | compatible = "atmel,at91sam9260-usart"; | ||
| 142 | reg = <0xf001c000 0x100>; | ||
| 143 | interrupts = <12 4 5>; | ||
| 144 | pinctrl-names = "default"; | ||
| 145 | pinctrl-0 = <&pinctrl_usart0>; | ||
| 146 | status = "disabled"; | ||
| 147 | }; | ||
| 148 | |||
| 149 | usart1: serial@f0020000 { | ||
| 150 | compatible = "atmel,at91sam9260-usart"; | ||
| 151 | reg = <0xf0020000 0x100>; | ||
| 152 | interrupts = <13 4 5>; | ||
| 153 | pinctrl-names = "default"; | ||
| 154 | pinctrl-0 = <&pinctrl_usart1>; | ||
| 155 | status = "disabled"; | ||
| 156 | }; | ||
| 157 | |||
| 158 | macb0: ethernet@f0028000 { | ||
| 159 | compatible = "cnds,pc302-gem", "cdns,gem"; | ||
| 160 | reg = <0xf0028000 0x100>; | ||
| 161 | interrupts = <34 4 3>; | ||
| 162 | pinctrl-names = "default"; | ||
| 163 | pinctrl-0 = <&pinctrl_macb0_data_rgmii &pinctrl_macb0_signal_rgmii>; | ||
| 164 | status = "disabled"; | ||
| 165 | }; | ||
| 166 | |||
| 167 | isi: isi@f0034000 { | ||
| 168 | compatible = "atmel,at91sam9g45-isi"; | ||
| 169 | reg = <0xf0034000 0x4000>; | ||
| 170 | interrupts = <37 4 5>; | ||
| 171 | status = "disabled"; | ||
| 172 | }; | ||
| 173 | |||
| 174 | mmc1: mmc@f8000000 { | ||
| 175 | compatible = "atmel,hsmci"; | ||
| 176 | reg = <0xf8000000 0x600>; | ||
| 177 | interrupts = <22 4 0>; | ||
| 178 | dmas = <&dma1 2 0>; | ||
| 179 | dma-names = "rxtx"; | ||
| 180 | pinctrl-names = "default"; | ||
| 181 | pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>; | ||
| 182 | status = "disabled"; | ||
| 183 | #address-cells = <1>; | ||
| 184 | #size-cells = <0>; | ||
| 185 | }; | ||
| 186 | |||
| 187 | mmc2: mmc@f8004000 { | ||
| 188 | compatible = "atmel,hsmci"; | ||
| 189 | reg = <0xf8004000 0x600>; | ||
| 190 | interrupts = <23 4 0>; | ||
| 191 | dmas = <&dma1 2 1>; | ||
| 192 | dma-names = "rxtx"; | ||
| 193 | pinctrl-names = "default"; | ||
| 194 | pinctrl-0 = <&pinctrl_mmc2_clk_cmd_dat0 &pinctrl_mmc2_dat1_3>; | ||
| 195 | status = "disabled"; | ||
| 196 | #address-cells = <1>; | ||
| 197 | #size-cells = <0>; | ||
| 198 | }; | ||
| 199 | |||
| 200 | spi1: spi@f8008000 { | ||
| 201 | #address-cells = <1>; | ||
| 202 | #size-cells = <0>; | ||
| 203 | compatible = "atmel,at91sam9x5-spi"; | ||
| 204 | reg = <0xf8008000 0x100>; | ||
| 205 | interrupts = <25 4 3>; | ||
| 206 | cs-gpios = <&pioC 25 0 | ||
| 207 | &pioC 26 0 /* conflitcs with TWD1 and ISI_D11 */ | ||
| 208 | &pioC 27 0 /* conflitcs with TWCK1 and ISI_D10 */ | ||
| 209 | &pioC 28 0 /* conflitcs with PWMFI0 and ISI_D9 */ | ||
| 210 | >; | ||
| 211 | pinctrl-names = "default"; | ||
| 212 | pinctrl-0 = <&pinctrl_spi1>; | ||
| 213 | status = "disabled"; | ||
| 214 | }; | ||
| 215 | |||
| 216 | ssc1: ssc@f800c000 { | ||
| 217 | compatible = "atmel,at91sam9g45-ssc"; | ||
| 218 | reg = <0xf800c000 0x4000>; | ||
| 219 | interrupts = <39 4 4>; | ||
| 220 | pinctrl-names = "default"; | ||
| 221 | pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; | ||
| 222 | status = "disabled"; | ||
| 223 | }; | ||
| 224 | |||
| 225 | can1: can@f8010000 { | ||
| 226 | compatible = "atmel,at91sam9x5-can"; | ||
| 227 | reg = <0xf8010000 0x300>; | ||
| 228 | interrupts = <41 4 3>; | ||
| 229 | pinctrl-names = "default"; | ||
| 230 | pinctrl-0 = <&pinctrl_can1_rx_tx>; | ||
| 231 | }; | ||
| 232 | |||
| 233 | tcb1: timer@f8014000 { | ||
| 234 | compatible = "atmel,at91sam9x5-tcb"; | ||
| 235 | reg = <0xf8014000 0x100>; | ||
| 236 | interrupts = <27 4 0>; | ||
| 237 | }; | ||
| 238 | |||
| 239 | adc0: adc@f8018000 { | ||
| 240 | compatible = "atmel,at91sam9260-adc"; | ||
| 241 | reg = <0xf8018000 0x100>; | ||
| 242 | interrupts = <29 4 5>; | ||
| 243 | pinctrl-names = "default"; | ||
| 244 | pinctrl-0 = < | ||
| 245 | &pinctrl_adc0_adtrg | ||
| 246 | &pinctrl_adc0_ad0 | ||
| 247 | &pinctrl_adc0_ad1 | ||
| 248 | &pinctrl_adc0_ad2 | ||
| 249 | &pinctrl_adc0_ad3 | ||
| 250 | &pinctrl_adc0_ad4 | ||
| 251 | &pinctrl_adc0_ad5 | ||
| 252 | &pinctrl_adc0_ad6 | ||
| 253 | &pinctrl_adc0_ad7 | ||
| 254 | &pinctrl_adc0_ad8 | ||
| 255 | &pinctrl_adc0_ad9 | ||
| 256 | &pinctrl_adc0_ad10 | ||
| 257 | &pinctrl_adc0_ad11 | ||
| 258 | >; | ||
| 259 | atmel,adc-channel-base = <0x50>; | ||
| 260 | atmel,adc-channels-used = <0xfff>; | ||
| 261 | atmel,adc-drdy-mask = <0x1000000>; | ||
| 262 | atmel,adc-num-channels = <12>; | ||
| 263 | atmel,adc-startup-time = <40>; | ||
| 264 | atmel,adc-status-register = <0x30>; | ||
| 265 | atmel,adc-trigger-register = <0xc0>; | ||
| 266 | atmel,adc-use-external; | ||
| 267 | atmel,adc-vref = <3000>; | ||
| 268 | atmel,adc-res = <10 12>; | ||
| 269 | atmel,adc-res-names = "lowres", "highres"; | ||
| 270 | status = "disabled"; | ||
| 271 | |||
| 272 | trigger@0 { | ||
| 273 | trigger-name = "external-rising"; | ||
| 274 | trigger-value = <0x1>; | ||
| 275 | trigger-external; | ||
| 276 | }; | ||
| 277 | trigger@1 { | ||
| 278 | trigger-name = "external-falling"; | ||
| 279 | trigger-value = <0x2>; | ||
| 280 | trigger-external; | ||
| 281 | }; | ||
| 282 | trigger@2 { | ||
| 283 | trigger-name = "external-any"; | ||
| 284 | trigger-value = <0x3>; | ||
| 285 | trigger-external; | ||
| 286 | }; | ||
| 287 | trigger@3 { | ||
| 288 | trigger-name = "continuous"; | ||
| 289 | trigger-value = <0x6>; | ||
| 290 | }; | ||
| 291 | }; | ||
| 292 | |||
| 293 | tsadcc: tsadcc@f8018000 { | ||
| 294 | compatible = "atmel,at91sam9x5-tsadcc"; | ||
| 295 | reg = <0xf8018000 0x4000>; | ||
| 296 | interrupts = <29 4 5>; | ||
| 297 | atmel,tsadcc_clock = <300000>; | ||
| 298 | atmel,filtering_average = <0x03>; | ||
| 299 | atmel,pendet_debounce = <0x08>; | ||
| 300 | atmel,pendet_sensitivity = <0x02>; | ||
| 301 | atmel,ts_sample_hold_time = <0x0a>; | ||
| 302 | status = "disabled"; | ||
| 303 | }; | ||
| 304 | |||
| 305 | i2c2: i2c@f801c000 { | ||
| 306 | compatible = "atmel,at91sam9x5-i2c"; | ||
| 307 | reg = <0xf801c000 0x4000>; | ||
| 308 | interrupts = <20 4 6>; | ||
| 309 | dmas = <&dma1 2 11>, | ||
| 310 | <&dma1 2 12>; | ||
| 311 | dma-names = "tx", "rx"; | ||
| 312 | #address-cells = <1>; | ||
| 313 | #size-cells = <0>; | ||
| 314 | status = "disabled"; | ||
| 315 | }; | ||
| 316 | |||
| 317 | usart2: serial@f8020000 { | ||
| 318 | compatible = "atmel,at91sam9260-usart"; | ||
| 319 | reg = <0xf8020000 0x100>; | ||
| 320 | interrupts = <14 4 5>; | ||
| 321 | pinctrl-names = "default"; | ||
| 322 | pinctrl-0 = <&pinctrl_usart2>; | ||
| 323 | status = "disabled"; | ||
| 324 | }; | ||
| 325 | |||
| 326 | usart3: serial@f8024000 { | ||
| 327 | compatible = "atmel,at91sam9260-usart"; | ||
| 328 | reg = <0xf8024000 0x100>; | ||
| 329 | interrupts = <15 4 5>; | ||
| 330 | pinctrl-names = "default"; | ||
| 331 | pinctrl-0 = <&pinctrl_usart3>; | ||
| 332 | status = "disabled"; | ||
| 333 | }; | ||
| 334 | |||
| 335 | macb1: ethernet@f802c000 { | ||
| 336 | compatible = "cdns,at32ap7000-macb", "cdns,macb"; | ||
| 337 | reg = <0xf802c000 0x100>; | ||
| 338 | interrupts = <35 4 3>; | ||
| 339 | pinctrl-names = "default"; | ||
| 340 | pinctrl-0 = <&pinctrl_macb1_rmii>; | ||
| 341 | status = "disabled"; | ||
| 342 | }; | ||
| 343 | |||
| 344 | sha@f8034000 { | ||
| 345 | compatible = "atmel,sam9g46-sha"; | ||
| 346 | reg = <0xf8034000 0x100>; | ||
| 347 | interrupts = <42 4 0>; | ||
| 348 | }; | ||
| 349 | |||
| 350 | aes@f8038000 { | ||
| 351 | compatible = "atmel,sam9g46-aes"; | ||
| 352 | reg = <0xf8038000 0x100>; | ||
| 353 | interrupts = <43 4 0>; | ||
| 354 | }; | ||
| 355 | |||
| 356 | tdes@f803c000 { | ||
| 357 | compatible = "atmel,sam9g46-tdes"; | ||
| 358 | reg = <0xf803c000 0x100>; | ||
| 359 | interrupts = <44 4 0>; | ||
| 360 | }; | ||
| 361 | |||
| 362 | dma0: dma-controller@ffffe600 { | ||
| 363 | compatible = "atmel,at91sam9g45-dma"; | ||
| 364 | reg = <0xffffe600 0x200>; | ||
| 365 | interrupts = <30 4 0>; | ||
| 366 | #dma-cells = <2>; | ||
| 367 | }; | ||
| 368 | |||
| 369 | dma1: dma-controller@ffffe800 { | ||
| 370 | compatible = "atmel,at91sam9g45-dma"; | ||
| 371 | reg = <0xffffe800 0x200>; | ||
| 372 | interrupts = <31 4 0>; | ||
| 373 | #dma-cells = <2>; | ||
| 374 | }; | ||
| 375 | |||
| 376 | ramc0: ramc@ffffea00 { | ||
| 377 | compatible = "atmel,at91sam9g45-ddramc"; | ||
| 378 | reg = <0xffffea00 0x200>; | ||
| 379 | }; | ||
| 380 | |||
| 381 | dbgu: serial@ffffee00 { | ||
| 382 | compatible = "atmel,at91sam9260-usart"; | ||
| 383 | reg = <0xffffee00 0x200>; | ||
| 384 | interrupts = <2 4 7>; | ||
| 385 | pinctrl-names = "default"; | ||
| 386 | pinctrl-0 = <&pinctrl_dbgu>; | ||
| 387 | status = "disabled"; | ||
| 388 | }; | ||
| 389 | |||
| 390 | aic: interrupt-controller@fffff000 { | ||
| 391 | #interrupt-cells = <3>; | ||
| 392 | compatible = "atmel,sama5d3-aic"; | ||
| 393 | interrupt-controller; | ||
| 394 | reg = <0xfffff000 0x200>; | ||
| 395 | atmel,external-irqs = <47>; | ||
| 396 | }; | ||
| 397 | |||
| 398 | pinctrl@fffff200 { | ||
| 399 | #address-cells = <1>; | ||
| 400 | #size-cells = <1>; | ||
| 401 | compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus"; | ||
| 402 | ranges = <0xfffff200 0xfffff200 0xa00>; | ||
| 403 | atmel,mux-mask = < | ||
| 404 | /* A B C */ | ||
| 405 | 0xffffffff 0xc0fc0000 0xc0ff0000 /* pioA */ | ||
| 406 | 0xffffffff 0x0ff8ffff 0x00000000 /* pioB */ | ||
| 407 | 0xffffffff 0xbc00f1ff 0x7c00fc00 /* pioC */ | ||
| 408 | 0xffffffff 0xc001c0e0 0x0001c1e0 /* pioD */ | ||
| 409 | 0xffffffff 0xbf9f8000 0x18000000 /* pioE */ | ||
| 410 | >; | ||
| 411 | |||
| 412 | /* shared pinctrl settings */ | ||
| 413 | adc0 { | ||
| 414 | pinctrl_adc0_adtrg: adc0_adtrg { | ||
| 415 | atmel,pins = | ||
| 416 | <3 19 0x1 0x0>; /* PD19 periph A ADTRG */ | ||
| 417 | }; | ||
| 418 | pinctrl_adc0_ad0: adc0_ad0 { | ||
| 419 | atmel,pins = | ||
| 420 | <3 20 0x1 0x0>; /* PD20 periph A AD0 */ | ||
| 421 | }; | ||
| 422 | pinctrl_adc0_ad1: adc0_ad1 { | ||
| 423 | atmel,pins = | ||
| 424 | <3 21 0x1 0x0>; /* PD21 periph A AD1 */ | ||
| 425 | }; | ||
| 426 | pinctrl_adc0_ad2: adc0_ad2 { | ||
| 427 | atmel,pins = | ||
| 428 | <3 22 0x1 0x0>; /* PD22 periph A AD2 */ | ||
| 429 | }; | ||
| 430 | pinctrl_adc0_ad3: adc0_ad3 { | ||
| 431 | atmel,pins = | ||
| 432 | <3 23 0x1 0x0>; /* PD23 periph A AD3 */ | ||
| 433 | }; | ||
| 434 | pinctrl_adc0_ad4: adc0_ad4 { | ||
| 435 | atmel,pins = | ||
| 436 | <3 24 0x1 0x0>; /* PD24 periph A AD4 */ | ||
| 437 | }; | ||
| 438 | pinctrl_adc0_ad5: adc0_ad5 { | ||
| 439 | atmel,pins = | ||
| 440 | <3 25 0x1 0x0>; /* PD25 periph A AD5 */ | ||
| 441 | }; | ||
| 442 | pinctrl_adc0_ad6: adc0_ad6 { | ||
| 443 | atmel,pins = | ||
| 444 | <3 26 0x1 0x0>; /* PD26 periph A AD6 */ | ||
| 445 | }; | ||
| 446 | pinctrl_adc0_ad7: adc0_ad7 { | ||
| 447 | atmel,pins = | ||
| 448 | <3 27 0x1 0x0>; /* PD27 periph A AD7 */ | ||
| 449 | }; | ||
| 450 | pinctrl_adc0_ad8: adc0_ad8 { | ||
| 451 | atmel,pins = | ||
| 452 | <3 28 0x1 0x0>; /* PD28 periph A AD8 */ | ||
| 453 | }; | ||
| 454 | pinctrl_adc0_ad9: adc0_ad9 { | ||
| 455 | atmel,pins = | ||
| 456 | <3 29 0x1 0x0>; /* PD29 periph A AD9 */ | ||
| 457 | }; | ||
| 458 | pinctrl_adc0_ad10: adc0_ad10 { | ||
| 459 | atmel,pins = | ||
| 460 | <3 30 0x1 0x0>; /* PD30 periph A AD10, conflicts with PCK0 */ | ||
| 461 | }; | ||
| 462 | pinctrl_adc0_ad11: adc0_ad11 { | ||
| 463 | atmel,pins = | ||
| 464 | <3 31 0x1 0x0>; /* PD31 periph A AD11, conflicts with PCK1 */ | ||
| 465 | }; | ||
| 466 | }; | ||
| 467 | |||
| 468 | can0 { | ||
| 469 | pinctrl_can0_rx_tx: can0_rx_tx { | ||
| 470 | atmel,pins = | ||
| 471 | <3 14 0x3 0x0 /* PD14 periph C RX, conflicts with SCK0, SPI0_NPCS1 */ | ||
| 472 | 3 15 0x3 0x0>; /* PD15 periph C TX, conflicts with CTS0, SPI0_NPCS2 */ | ||
| 473 | }; | ||
| 474 | }; | ||
| 475 | |||
| 476 | can1 { | ||
| 477 | pinctrl_can1_rx_tx: can1_rx_tx { | ||
| 478 | atmel,pins = | ||
| 479 | <1 14 0x2 0x0 /* PB14 periph B RX, conflicts with GCRS */ | ||
| 480 | 1 15 0x2 0x0>; /* PB15 periph B TX, conflicts with GCOL */ | ||
| 481 | }; | ||
| 482 | }; | ||
| 483 | |||
| 484 | dbgu { | ||
| 485 | pinctrl_dbgu: dbgu-0 { | ||
| 486 | atmel,pins = | ||
| 487 | <1 30 0x1 0x0 /* PB30 periph A */ | ||
| 488 | 1 31 0x1 0x1>; /* PB31 periph A with pullup */ | ||
| 489 | }; | ||
| 490 | }; | ||
| 491 | |||
| 492 | i2c0 { | ||
| 493 | pinctrl_i2c0: i2c0-0 { | ||
| 494 | atmel,pins = | ||
| 495 | <0 30 0x1 0x0 /* PA30 periph A TWD0 pin, conflicts with URXD1, ISI_VSYNC */ | ||
| 496 | 0 31 0x1 0x0>; /* PA31 periph A TWCK0 pin, conflicts with UTXD1, ISI_HSYNC */ | ||
| 497 | }; | ||
| 498 | }; | ||
| 499 | |||
| 500 | i2c1 { | ||
| 501 | pinctrl_i2c1: i2c1-0 { | ||
| 502 | atmel,pins = | ||
| 503 | <2 26 0x2 0x0 /* PC26 periph B TWD1 pin, conflicts with SPI1_NPCS1, ISI_D11 */ | ||
| 504 | 2 27 0x2 0x0>; /* PC27 periph B TWCK1 pin, conflicts with SPI1_NPCS2, ISI_D10 */ | ||
| 505 | }; | ||
| 506 | }; | ||
| 507 | |||
| 508 | isi { | ||
| 509 | pinctrl_isi: isi-0 { | ||
| 510 | atmel,pins = | ||
| 511 | <0 16 0x3 0x0 /* PA16 periph C ISI_D0, conflicts with LCDDAT16 */ | ||
| 512 | 0 17 0x3 0x0 /* PA17 periph C ISI_D1, conflicts with LCDDAT17 */ | ||
| 513 | 0 18 0x3 0x0 /* PA18 periph C ISI_D2, conflicts with LCDDAT18, TWD2 */ | ||
| 514 | 0 19 0x3 0x0 /* PA19 periph C ISI_D3, conflicts with LCDDAT19, TWCK2 */ | ||
| 515 | 0 20 0x3 0x0 /* PA20 periph C ISI_D4, conflicts with LCDDAT20, PWMH0 */ | ||
| 516 | 0 21 0x3 0x0 /* PA21 periph C ISI_D5, conflicts with LCDDAT21, PWML0 */ | ||
| 517 | 0 22 0x3 0x0 /* PA22 periph C ISI_D6, conflicts with LCDDAT22, PWMH1 */ | ||
| 518 | 0 23 0x3 0x0 /* PA23 periph C ISI_D7, conflicts with LCDDAT23, PWML1 */ | ||
| 519 | 2 30 0x3 0x0 /* PC30 periph C ISI_PCK, conflicts with UTXD0 */ | ||
| 520 | 0 31 0x3 0x0 /* PA31 periph C ISI_HSYNC, conflicts with TWCK0, UTXD1 */ | ||
| 521 | 0 30 0x3 0x0 /* PA30 periph C ISI_VSYNC, conflicts with TWD0, URXD1 */ | ||
| 522 | 2 29 0x3 0x0 /* PC29 periph C ISI_PD8, conflicts with URXD0, PWMFI2 */ | ||
| 523 | 2 28 0x3 0x0>; /* PC28 periph C ISI_PD9, conflicts with SPI1_NPCS3, PWMFI0 */ | ||
| 524 | }; | ||
| 525 | pinctrl_isi_pck_as_mck: isi_pck_as_mck-0 { | ||
| 526 | atmel,pins = | ||
| 527 | <3 31 0x2 0x0>; /* PD31 periph B ISI_MCK */ | ||
| 528 | }; | ||
| 529 | }; | ||
| 530 | |||
| 531 | lcd { | ||
| 532 | pinctrl_lcd: lcd-0 { | ||
| 533 | atmel,pins = | ||
| 534 | <0 24 0x1 0x0 /* PA24 periph A LCDPWM */ | ||
| 535 | 0 26 0x1 0x0 /* PA26 periph A LCDVSYNC */ | ||
| 536 | 0 27 0x1 0x0 /* PA27 periph A LCDHSYNC */ | ||
| 537 | 0 25 0x1 0x0 /* PA25 periph A LCDDISP */ | ||
| 538 | 0 29 0x1 0x0 /* PA29 periph A LCDDEN */ | ||
| 539 | 0 28 0x1 0x0 /* PA28 periph A LCDPCK */ | ||
| 540 | 0 0 0x1 0x0 /* PA0 periph A LCDD0 pin */ | ||
| 541 | 0 1 0x1 0x0 /* PA1 periph A LCDD1 pin */ | ||
| 542 | 0 2 0x1 0x0 /* PA2 periph A LCDD2 pin */ | ||
| 543 | 0 3 0x1 0x0 /* PA3 periph A LCDD3 pin */ | ||
| 544 | 0 4 0x1 0x0 /* PA4 periph A LCDD4 pin */ | ||
| 545 | 0 5 0x1 0x0 /* PA5 periph A LCDD5 pin */ | ||
| 546 | 0 6 0x1 0x0 /* PA6 periph A LCDD6 pin */ | ||
| 547 | 0 7 0x1 0x0 /* PA7 periph A LCDD7 pin */ | ||
| 548 | 0 8 0x1 0x0 /* PA8 periph A LCDD8 pin */ | ||
| 549 | 0 9 0x1 0x0 /* PA9 periph A LCDD9 pin */ | ||
| 550 | 0 10 0x1 0x0 /* PA10 periph A LCDD10 pin */ | ||
| 551 | 0 11 0x1 0x0 /* PA11 periph A LCDD11 pin */ | ||
| 552 | 0 12 0x1 0x0 /* PA12 periph A LCDD12 pin */ | ||
| 553 | 0 13 0x1 0x0 /* PA13 periph A LCDD13 pin */ | ||
| 554 | 0 14 0x1 0x0 /* PA14 periph A LCDD14 pin */ | ||
| 555 | 0 15 0x1 0x0 /* PA15 periph A LCDD15 pin */ | ||
| 556 | 2 14 0x3 0x0 /* PC14 periph C LCDD16 pin */ | ||
| 557 | 2 13 0x3 0x0 /* PC13 periph C LCDD17 pin */ | ||
| 558 | 2 12 0x3 0x0 /* PC12 periph C LCDD18 pin */ | ||
| 559 | 2 11 0x3 0x0 /* PC11 periph C LCDD19 pin */ | ||
| 560 | 2 10 0x3 0x0 /* PC10 periph C LCDD20 pin */ | ||
| 561 | 2 15 0x3 0x0 /* PC15 periph C LCDD21 pin */ | ||
| 562 | 4 27 0x3 0x0 /* PE27 periph C LCDD22 pin */ | ||
| 563 | 4 28 0x3 0x0>; /* PE28 periph C LCDD23 pin */ | ||
| 564 | }; | ||
| 565 | }; | ||
| 566 | |||
| 567 | macb0 { | ||
| 568 | pinctrl_macb0_data_rgmii: macb0_data_rgmii { | ||
| 569 | atmel,pins = | ||
| 570 | <1 0 0x1 0x0 /* PB0 periph A GTX0, conflicts with PWMH0 */ | ||
| 571 | 1 1 0x1 0x0 /* PB1 periph A GTX1, conflicts with PWML0 */ | ||
| 572 | 1 2 0x1 0x0 /* PB2 periph A GTX2, conflicts with TK1 */ | ||
| 573 | 1 3 0x1 0x0 /* PB3 periph A GTX3, conflicts with TF1 */ | ||
| 574 | 1 4 0x1 0x0 /* PB4 periph A GRX0, conflicts with PWMH1 */ | ||
| 575 | 1 5 0x1 0x0 /* PB5 periph A GRX1, conflicts with PWML1 */ | ||
| 576 | 1 6 0x1 0x0 /* PB6 periph A GRX2, conflicts with TD1 */ | ||
| 577 | 1 7 0x1 0x0>; /* PB7 periph A GRX3, conflicts with RK1 */ | ||
| 578 | }; | ||
| 579 | pinctrl_macb0_data_gmii: macb0_data_gmii { | ||
| 580 | atmel,pins = | ||
| 581 | <1 19 0x2 0x0 /* PB19 periph B GTX4, conflicts with MCI1_CDA */ | ||
| 582 | 1 20 0x2 0x0 /* PB20 periph B GTX5, conflicts with MCI1_DA0 */ | ||
| 583 | 1 21 0x2 0x0 /* PB21 periph B GTX6, conflicts with MCI1_DA1 */ | ||
| 584 | 1 22 0x2 0x0 /* PB22 periph B GTX7, conflicts with MCI1_DA2 */ | ||
| 585 | 1 23 0x2 0x0 /* PB23 periph B GRX4, conflicts with MCI1_DA3 */ | ||
| 586 | 1 24 0x2 0x0 /* PB24 periph B GRX5, conflicts with MCI1_CK */ | ||
| 587 | 1 25 0x2 0x0 /* PB25 periph B GRX6, conflicts with SCK1 */ | ||
| 588 | 1 26 0x2 0x0>; /* PB26 periph B GRX7, conflicts with CTS1 */ | ||
| 589 | }; | ||
| 590 | pinctrl_macb0_signal_rgmii: macb0_signal_rgmii { | ||
| 591 | atmel,pins = | ||
| 592 | <1 8 0x1 0x0 /* PB8 periph A GTXCK, conflicts with PWMH2 */ | ||
| 593 | 1 9 0x1 0x0 /* PB9 periph A GTXEN, conflicts with PWML2 */ | ||
| 594 | 1 11 0x1 0x0 /* PB11 periph A GRXCK, conflicts with RD1 */ | ||
| 595 | 1 13 0x1 0x0 /* PB13 periph A GRXER, conflicts with PWML3 */ | ||
| 596 | 1 16 0x1 0x0 /* PB16 periph A GMDC */ | ||
| 597 | 1 17 0x1 0x0 /* PB17 periph A GMDIO */ | ||
| 598 | 1 18 0x1 0x0>; /* PB18 periph A G125CK */ | ||
| 599 | }; | ||
| 600 | pinctrl_macb0_signal_gmii: macb0_signal_gmii { | ||
| 601 | atmel,pins = | ||
| 602 | <1 9 0x1 0x0 /* PB9 periph A GTXEN, conflicts with PWML2 */ | ||
| 603 | 1 10 0x1 0x0 /* PB10 periph A GTXER, conflicts with RF1 */ | ||
| 604 | 1 11 0x1 0x0 /* PB11 periph A GRXCK, conflicts with RD1 */ | ||
| 605 | 1 12 0x1 0x0 /* PB12 periph A GRXDV, conflicts with PWMH3 */ | ||
| 606 | 1 13 0x1 0x0 /* PB13 periph A GRXER, conflicts with PWML3 */ | ||
| 607 | 1 14 0x1 0x0 /* PB14 periph A GCRS, conflicts with CANRX1 */ | ||
| 608 | 1 15 0x1 0x0 /* PB15 periph A GCOL, conflicts with CANTX1 */ | ||
| 609 | 1 16 0x1 0x0 /* PB16 periph A GMDC */ | ||
| 610 | 1 17 0x1 0x0 /* PB17 periph A GMDIO */ | ||
| 611 | 1 27 0x2 0x0>; /* PB27 periph B G125CKO */ | ||
| 612 | }; | ||
| 613 | |||
| 614 | }; | ||
| 615 | |||
| 616 | macb1 { | ||
| 617 | pinctrl_macb1_rmii: macb1_rmii-0 { | ||
| 618 | atmel,pins = | ||
| 619 | <2 0 0x1 0x0 /* PC0 periph A ETX0, conflicts with TIOA3 */ | ||
| 620 | 2 1 0x1 0x0 /* PC1 periph A ETX1, conflicts with TIOB3 */ | ||
| 621 | 2 2 0x1 0x0 /* PC2 periph A ERX0, conflicts with TCLK3 */ | ||
| 622 | 2 3 0x1 0x0 /* PC3 periph A ERX1, conflicts with TIOA4 */ | ||
| 623 | 2 4 0x1 0x0 /* PC4 periph A ETXEN, conflicts with TIOB4 */ | ||
| 624 | 2 5 0x1 0x0 /* PC5 periph A ECRSDV,conflicts with TCLK4 */ | ||
| 625 | 2 6 0x1 0x0 /* PC6 periph A ERXER, conflicts with TIOA5 */ | ||
| 626 | 2 7 0x1 0x0 /* PC7 periph A EREFCK, conflicts with TIOB5 */ | ||
| 627 | 2 8 0x1 0x0 /* PC8 periph A EMDC, conflicts with TCLK5 */ | ||
| 628 | 2 9 0x1 0x0>; /* PC9 periph A EMDIO */ | ||
| 629 | }; | ||
| 630 | }; | ||
| 631 | |||
| 632 | mmc0 { | ||
| 633 | pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 { | ||
| 634 | atmel,pins = | ||
| 635 | <3 9 0x1 0x0 /* PD9 periph A MCI0_CK */ | ||
| 636 | 3 0 0x1 0x1 /* PD0 periph A MCI0_CDA with pullup */ | ||
| 637 | 3 1 0x1 0x1>; /* PD1 periph A MCI0_DA0 with pullup */ | ||
| 638 | }; | ||
| 639 | pinctrl_mmc0_dat1_3: mmc0_dat1_3 { | ||
| 640 | atmel,pins = | ||
| 641 | <3 2 0x1 0x1 /* PD2 periph A MCI0_DA1 with pullup */ | ||
| 642 | 3 3 0x1 0x1 /* PD3 periph A MCI0_DA2 with pullup */ | ||
| 643 | 3 4 0x1 0x1>; /* PD4 periph A MCI0_DA3 with pullup */ | ||
| 644 | }; | ||
| 645 | pinctrl_mmc0_dat4_7: mmc0_dat4_7 { | ||
| 646 | atmel,pins = | ||
| 647 | <3 5 0x1 0x1 /* PD5 periph A MCI0_DA4 with pullup, conflicts with TIOA0, PWMH2 */ | ||
| 648 | 3 6 0x1 0x1 /* PD6 periph A MCI0_DA5 with pullup, conflicts with TIOB0, PWML2 */ | ||
| 649 | 3 7 0x1 0x1 /* PD7 periph A MCI0_DA6 with pullup, conlicts with TCLK0, PWMH3 */ | ||
| 650 | 3 8 0x1 0x1>; /* PD8 periph A MCI0_DA7 with pullup, conflicts with PWML3 */ | ||
| 651 | }; | ||
| 652 | }; | ||
| 653 | |||
| 654 | mmc1 { | ||
| 655 | pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 { | ||
| 656 | atmel,pins = | ||
| 657 | <1 24 0x1 0x0 /* PB24 periph A MCI1_CK, conflicts with GRX5 */ | ||
| 658 | 1 19 0x1 0x1 /* PB19 periph A MCI1_CDA with pullup, conflicts with GTX4 */ | ||
| 659 | 1 20 0x1 0x1>; /* PB20 periph A MCI1_DA0 with pullup, conflicts with GTX5 */ | ||
| 660 | }; | ||
| 661 | pinctrl_mmc1_dat1_3: mmc1_dat1_3 { | ||
| 662 | atmel,pins = | ||
| 663 | <1 21 0x1 0x1 /* PB21 periph A MCI1_DA1 with pullup, conflicts with GTX6 */ | ||
| 664 | 1 22 0x1 0x1 /* PB22 periph A MCI1_DA2 with pullup, conflicts with GTX7 */ | ||
| 665 | 1 23 0x1 0x1>; /* PB23 periph A MCI1_DA3 with pullup, conflicts with GRX4 */ | ||
| 666 | }; | ||
| 667 | }; | ||
| 668 | |||
| 669 | mmc2 { | ||
| 670 | pinctrl_mmc2_clk_cmd_dat0: mmc2_clk_cmd_dat0 { | ||
| 671 | atmel,pins = | ||
| 672 | <2 15 0x1 0x0 /* PC15 periph A MCI2_CK, conflicts with PCK2 */ | ||
| 673 | 2 10 0x1 0x1 /* PC10 periph A MCI2_CDA with pullup */ | ||
| 674 | 2 11 0x1 0x1>; /* PC11 periph A MCI2_DA0 with pullup */ | ||
| 675 | }; | ||
| 676 | pinctrl_mmc2_dat1_3: mmc2_dat1_3 { | ||
| 677 | atmel,pins = | ||
| 678 | <2 12 0x1 0x0 /* PC12 periph A MCI2_DA1 with pullup, conflicts with TIOA1 */ | ||
| 679 | 2 13 0x1 0x0 /* PC13 periph A MCI2_DA2 with pullup, conflicts with TIOB1 */ | ||
| 680 | 2 14 0x1 0x0>; /* PC14 periph A MCI2_DA3 with pullup, conflicts with TCLK1 */ | ||
| 681 | }; | ||
| 682 | }; | ||
| 683 | |||
| 684 | nand0 { | ||
| 685 | pinctrl_nand0_ale_cle: nand0_ale_cle-0 { | ||
| 686 | atmel,pins = | ||
| 687 | <4 21 0x1 0x1 /* PE21 periph A with pullup */ | ||
| 688 | 4 22 0x1 0x1>; /* PE22 periph A with pullup */ | ||
| 689 | }; | ||
| 690 | }; | ||
| 691 | |||
| 692 | pioA: gpio@fffff200 { | ||
| 693 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | ||
| 694 | reg = <0xfffff200 0x100>; | ||
| 695 | interrupts = <6 4 1>; | ||
| 696 | #gpio-cells = <2>; | ||
| 697 | gpio-controller; | ||
| 698 | interrupt-controller; | ||
| 699 | #interrupt-cells = <2>; | ||
| 700 | }; | ||
| 701 | |||
| 702 | pioB: gpio@fffff400 { | ||
| 703 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | ||
| 704 | reg = <0xfffff400 0x100>; | ||
| 705 | interrupts = <7 4 1>; | ||
| 706 | #gpio-cells = <2>; | ||
| 707 | gpio-controller; | ||
| 708 | interrupt-controller; | ||
| 709 | #interrupt-cells = <2>; | ||
| 710 | }; | ||
| 711 | |||
| 712 | pioC: gpio@fffff600 { | ||
| 713 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | ||
| 714 | reg = <0xfffff600 0x100>; | ||
| 715 | interrupts = <8 4 1>; | ||
| 716 | #gpio-cells = <2>; | ||
| 717 | gpio-controller; | ||
| 718 | interrupt-controller; | ||
| 719 | #interrupt-cells = <2>; | ||
| 720 | }; | ||
| 721 | |||
| 722 | pioD: gpio@fffff800 { | ||
| 723 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | ||
| 724 | reg = <0xfffff800 0x100>; | ||
| 725 | interrupts = <9 4 1>; | ||
| 726 | #gpio-cells = <2>; | ||
| 727 | gpio-controller; | ||
| 728 | interrupt-controller; | ||
| 729 | #interrupt-cells = <2>; | ||
| 730 | }; | ||
| 731 | |||
| 732 | pioE: gpio@fffffa00 { | ||
| 733 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | ||
| 734 | reg = <0xfffffa00 0x100>; | ||
| 735 | interrupts = <10 4 1>; | ||
| 736 | #gpio-cells = <2>; | ||
| 737 | gpio-controller; | ||
| 738 | interrupt-controller; | ||
| 739 | #interrupt-cells = <2>; | ||
| 740 | }; | ||
| 741 | |||
| 742 | spi0 { | ||
| 743 | pinctrl_spi0: spi0-0 { | ||
| 744 | atmel,pins = | ||
| 745 | <3 10 0x1 0x0 /* PD10 periph A SPI0_MISO pin */ | ||
| 746 | 3 11 0x1 0x0 /* PD11 periph A SPI0_MOSI pin */ | ||
| 747 | 3 12 0x1 0x0 /* PD12 periph A SPI0_SPCK pin */ | ||
| 748 | 3 13 0x0 0x0>; /* PD13 GPIO SPI0_NPCS0 pin */ | ||
| 749 | }; | ||
| 750 | }; | ||
| 751 | |||
| 752 | spi1 { | ||
| 753 | pinctrl_spi1: spi1-0 { | ||
| 754 | atmel,pins = | ||
| 755 | <2 22 0x1 0x0 /* PC22 periph A SPI1_MISO pin */ | ||
| 756 | 2 23 0x1 0x0 /* PC23 periph A SPI1_MOSI pin */ | ||
| 757 | 2 24 0x1 0x0 /* PC24 periph A SPI1_SPCK pin */ | ||
| 758 | 2 25 0x0 0x0>; /* PC25 GPIO SPI1_NPCS0 pin */ | ||
| 759 | }; | ||
| 760 | }; | ||
| 761 | |||
| 762 | ssc0 { | ||
| 763 | pinctrl_ssc0_tx: ssc0_tx { | ||
| 764 | atmel,pins = | ||
| 765 | <2 16 0x1 0x0 /* PC16 periph A TK0 */ | ||
| 766 | 2 17 0x1 0x0 /* PC17 periph A TF0 */ | ||
| 767 | 2 18 0x1 0x0>; /* PC18 periph A TD0 */ | ||
| 768 | }; | ||
| 769 | |||
| 770 | pinctrl_ssc0_rx: ssc0_rx { | ||
| 771 | atmel,pins = | ||
| 772 | <2 19 0x1 0x0 /* PC19 periph A RK0 */ | ||
| 773 | 2 20 0x1 0x0 /* PC20 periph A RF0 */ | ||
| 774 | 2 21 0x1 0x0>; /* PC21 periph A RD0 */ | ||
| 775 | }; | ||
| 776 | }; | ||
| 777 | |||
| 778 | ssc1 { | ||
| 779 | pinctrl_ssc1_tx: ssc1_tx { | ||
| 780 | atmel,pins = | ||
| 781 | <1 2 0x2 0x0 /* PB2 periph B TK1, conflicts with GTX2 */ | ||
| 782 | 1 3 0x2 0x0 /* PB3 periph B TF1, conflicts with GTX3 */ | ||
| 783 | 1 6 0x2 0x0>; /* PB6 periph B TD1, conflicts with TD1 */ | ||
| 784 | }; | ||
| 785 | |||
| 786 | pinctrl_ssc1_rx: ssc1_rx { | ||
| 787 | atmel,pins = | ||
| 788 | <1 7 0x2 0x0 /* PB7 periph B RK1, conflicts with EREFCK */ | ||
| 789 | 1 10 0x2 0x0 /* PB10 periph B RF1, conflicts with GTXER */ | ||
| 790 | 1 11 0x2 0x0>; /* PB11 periph B RD1, conflicts with GRXCK */ | ||
| 791 | }; | ||
| 792 | }; | ||
| 793 | |||
| 794 | uart0 { | ||
| 795 | pinctrl_uart0: uart0-0 { | ||
| 796 | atmel,pins = | ||
| 797 | <2 29 0x1 0x0 /* PC29 periph A, conflicts with PWMFI2, ISI_D8 */ | ||
| 798 | 2 30 0x1 0x1>; /* PC30 periph A with pullup, conflicts with ISI_PCK */ | ||
| 799 | }; | ||
| 800 | }; | ||
| 801 | |||
| 802 | uart1 { | ||
| 803 | pinctrl_uart1: uart1-0 { | ||
| 804 | atmel,pins = | ||
| 805 | <0 30 0x2 0x0 /* PA30 periph B, conflicts with TWD0, ISI_VSYNC */ | ||
| 806 | 0 31 0x2 0x1>; /* PA31 periph B with pullup, conflicts with TWCK0, ISI_HSYNC */ | ||
| 807 | }; | ||
| 808 | }; | ||
| 809 | |||
| 810 | usart0 { | ||
| 811 | pinctrl_usart0: usart0-0 { | ||
| 812 | atmel,pins = | ||
| 813 | <3 17 0x1 0x0 /* PD17 periph A */ | ||
| 814 | 3 18 0x1 0x1>; /* PD18 periph A with pullup */ | ||
| 815 | }; | ||
| 816 | |||
| 817 | pinctrl_usart0_rts_cts: usart0_rts_cts-0 { | ||
| 818 | atmel,pins = | ||
| 819 | <3 15 0x1 0x0 /* PD15 periph A, conflicts with SPI0_NPCS2, CANTX0 */ | ||
| 820 | 3 16 0x1 0x0>; /* PD16 periph A, conflicts with SPI0_NPCS3, PWMFI3 */ | ||
| 821 | }; | ||
| 822 | }; | ||
| 823 | |||
| 824 | usart1 { | ||
| 825 | pinctrl_usart1: usart1-0 { | ||
| 826 | atmel,pins = | ||
| 827 | <1 28 0x1 0x0 /* PB28 periph A */ | ||
| 828 | 1 29 0x1 0x1>; /* PB29 periph A with pullup */ | ||
| 829 | }; | ||
| 830 | |||
| 831 | pinctrl_usart1_rts_cts: usart1_rts_cts-0 { | ||
| 832 | atmel,pins = | ||
| 833 | <1 26 0x1 0x0 /* PB26 periph A, conflicts with GRX7 */ | ||
| 834 | 1 27 0x1 0x0>; /* PB27 periph A, conflicts with G125CKO */ | ||
| 835 | }; | ||
| 836 | }; | ||
| 837 | |||
| 838 | usart2 { | ||
| 839 | pinctrl_usart2: usart2-0 { | ||
| 840 | atmel,pins = | ||
| 841 | <4 25 0x2 0x0 /* PE25 periph B, conflicts with A25 */ | ||
| 842 | 4 26 0x2 0x1>; /* PE26 periph B with pullup, conflicts NCS0 */ | ||
| 843 | }; | ||
| 844 | |||
| 845 | pinctrl_usart2_rts_cts: usart2_rts_cts-0 { | ||
| 846 | atmel,pins = | ||
| 847 | <4 23 0x2 0x0 /* PE23 periph B, conflicts with A23 */ | ||
| 848 | 4 24 0x2 0x0>; /* PE24 periph B, conflicts with A24 */ | ||
| 849 | }; | ||
| 850 | }; | ||
| 851 | |||
| 852 | usart3 { | ||
| 853 | pinctrl_usart3: usart3-0 { | ||
| 854 | atmel,pins = | ||
| 855 | <4 18 0x2 0x0 /* PE18 periph B, conflicts with A18 */ | ||
| 856 | 4 19 0x2 0x1>; /* PE19 periph B with pullup, conflicts with A19 */ | ||
| 857 | }; | ||
| 858 | |||
| 859 | pinctrl_usart3_rts_cts: usart3_rts_cts-0 { | ||
| 860 | atmel,pins = | ||
| 861 | <4 16 0x2 0x0 /* PE16 periph B, conflicts with A16 */ | ||
| 862 | 4 17 0x2 0x0>; /* PE17 periph B, conflicts with A17 */ | ||
| 863 | }; | ||
| 864 | }; | ||
| 865 | }; | ||
| 866 | |||
| 867 | pmc: pmc@fffffc00 { | ||
| 868 | compatible = "atmel,at91rm9200-pmc"; | ||
| 869 | reg = <0xfffffc00 0x120>; | ||
| 870 | }; | ||
| 871 | |||
| 872 | rstc@fffffe00 { | ||
| 873 | compatible = "atmel,at91sam9g45-rstc"; | ||
| 874 | reg = <0xfffffe00 0x10>; | ||
| 875 | }; | ||
| 876 | |||
| 877 | pit: timer@fffffe30 { | ||
| 878 | compatible = "atmel,at91sam9260-pit"; | ||
| 879 | reg = <0xfffffe30 0xf>; | ||
| 880 | interrupts = <3 4 5>; | ||
| 881 | }; | ||
| 882 | |||
| 883 | watchdog@fffffe40 { | ||
| 884 | compatible = "atmel,at91sam9260-wdt"; | ||
| 885 | reg = <0xfffffe40 0x10>; | ||
| 886 | status = "disabled"; | ||
| 887 | }; | ||
| 888 | |||
| 889 | rtc@fffffeb0 { | ||
| 890 | compatible = "atmel,at91rm9200-rtc"; | ||
| 891 | reg = <0xfffffeb0 0x30>; | ||
| 892 | interrupts = <1 4 7>; | ||
| 893 | }; | ||
| 894 | }; | ||
| 895 | |||
| 896 | usb0: gadget@00500000 { | ||
| 897 | #address-cells = <1>; | ||
| 898 | #size-cells = <0>; | ||
| 899 | compatible = "atmel,at91sam9rl-udc"; | ||
| 900 | reg = <0x00500000 0x100000 | ||
| 901 | 0xf8030000 0x4000>; | ||
| 902 | interrupts = <33 4 2>; | ||
| 903 | status = "disabled"; | ||
| 904 | |||
| 905 | ep0 { | ||
| 906 | reg = <0>; | ||
| 907 | atmel,fifo-size = <64>; | ||
| 908 | atmel,nb-banks = <1>; | ||
| 909 | }; | ||
| 910 | |||
| 911 | ep1 { | ||
| 912 | reg = <1>; | ||
| 913 | atmel,fifo-size = <1024>; | ||
| 914 | atmel,nb-banks = <3>; | ||
| 915 | atmel,can-dma; | ||
| 916 | atmel,can-isoc; | ||
| 917 | }; | ||
| 918 | |||
| 919 | ep2 { | ||
| 920 | reg = <2>; | ||
| 921 | atmel,fifo-size = <1024>; | ||
| 922 | atmel,nb-banks = <3>; | ||
| 923 | atmel,can-dma; | ||
| 924 | atmel,can-isoc; | ||
| 925 | }; | ||
| 926 | |||
| 927 | ep3 { | ||
| 928 | reg = <3>; | ||
| 929 | atmel,fifo-size = <1024>; | ||
| 930 | atmel,nb-banks = <2>; | ||
| 931 | atmel,can-dma; | ||
| 932 | }; | ||
| 933 | |||
| 934 | ep4 { | ||
| 935 | reg = <4>; | ||
| 936 | atmel,fifo-size = <1024>; | ||
| 937 | atmel,nb-banks = <2>; | ||
| 938 | atmel,can-dma; | ||
| 939 | }; | ||
| 940 | |||
| 941 | ep5 { | ||
| 942 | reg = <5>; | ||
| 943 | atmel,fifo-size = <1024>; | ||
| 944 | atmel,nb-banks = <2>; | ||
| 945 | atmel,can-dma; | ||
| 946 | }; | ||
| 947 | |||
| 948 | ep6 { | ||
| 949 | reg = <6>; | ||
| 950 | atmel,fifo-size = <1024>; | ||
| 951 | atmel,nb-banks = <2>; | ||
| 952 | atmel,can-dma; | ||
| 953 | }; | ||
| 954 | |||
| 955 | ep7 { | ||
| 956 | reg = <7>; | ||
| 957 | atmel,fifo-size = <1024>; | ||
| 958 | atmel,nb-banks = <2>; | ||
| 959 | atmel,can-dma; | ||
| 960 | }; | ||
| 961 | |||
| 962 | ep8 { | ||
| 963 | reg = <8>; | ||
| 964 | atmel,fifo-size = <1024>; | ||
| 965 | atmel,nb-banks = <2>; | ||
| 966 | }; | ||
| 967 | |||
| 968 | ep9 { | ||
| 969 | reg = <9>; | ||
| 970 | atmel,fifo-size = <1024>; | ||
| 971 | atmel,nb-banks = <2>; | ||
| 972 | }; | ||
| 973 | |||
| 974 | ep10 { | ||
| 975 | reg = <10>; | ||
| 976 | atmel,fifo-size = <1024>; | ||
| 977 | atmel,nb-banks = <2>; | ||
| 978 | }; | ||
| 979 | |||
| 980 | ep11 { | ||
| 981 | reg = <11>; | ||
| 982 | atmel,fifo-size = <1024>; | ||
| 983 | atmel,nb-banks = <2>; | ||
| 984 | }; | ||
| 985 | |||
| 986 | ep12 { | ||
| 987 | reg = <12>; | ||
| 988 | atmel,fifo-size = <1024>; | ||
| 989 | atmel,nb-banks = <2>; | ||
| 990 | }; | ||
| 991 | |||
| 992 | ep13 { | ||
| 993 | reg = <13>; | ||
| 994 | atmel,fifo-size = <1024>; | ||
| 995 | atmel,nb-banks = <2>; | ||
| 996 | }; | ||
| 997 | |||
| 998 | ep14 { | ||
| 999 | reg = <14>; | ||
| 1000 | atmel,fifo-size = <1024>; | ||
| 1001 | atmel,nb-banks = <2>; | ||
| 1002 | }; | ||
| 1003 | |||
| 1004 | ep15 { | ||
| 1005 | reg = <15>; | ||
| 1006 | atmel,fifo-size = <1024>; | ||
| 1007 | atmel,nb-banks = <2>; | ||
| 1008 | }; | ||
| 1009 | }; | ||
| 1010 | |||
| 1011 | usb1: ohci@00600000 { | ||
| 1012 | compatible = "atmel,at91rm9200-ohci", "usb-ohci"; | ||
| 1013 | reg = <0x00600000 0x100000>; | ||
| 1014 | interrupts = <32 4 2>; | ||
| 1015 | status = "disabled"; | ||
| 1016 | }; | ||
| 1017 | |||
| 1018 | usb2: ehci@00700000 { | ||
| 1019 | compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; | ||
| 1020 | reg = <0x00700000 0x100000>; | ||
| 1021 | interrupts = <32 4 2>; | ||
| 1022 | status = "disabled"; | ||
| 1023 | }; | ||
| 1024 | |||
| 1025 | nand0: nand@60000000 { | ||
| 1026 | compatible = "atmel,at91rm9200-nand"; | ||
| 1027 | #address-cells = <1>; | ||
| 1028 | #size-cells = <1>; | ||
| 1029 | reg = < 0x60000000 0x01000000 /* EBI CS3 */ | ||
| 1030 | 0xffffc070 0x00000490 /* SMC PMECC regs */ | ||
| 1031 | 0xffffc500 0x00000100 /* SMC PMECC Error Location regs */ | ||
| 1032 | 0x00100000 0x00100000 /* ROM code */ | ||
| 1033 | 0x70000000 0x10000000 /* NFC Command Registers */ | ||
| 1034 | 0xffffc000 0x00000070 /* NFC HSMC regs */ | ||
| 1035 | 0x00200000 0x00100000 /* NFC SRAM banks */ | ||
| 1036 | >; | ||
| 1037 | interrupts = <5 4 6>; | ||
| 1038 | atmel,nand-addr-offset = <21>; | ||
| 1039 | atmel,nand-cmd-offset = <22>; | ||
| 1040 | pinctrl-names = "default"; | ||
| 1041 | pinctrl-0 = <&pinctrl_nand0_ale_cle>; | ||
| 1042 | atmel,pmecc-lookup-table-offset = <0x10000 0x18000>; | ||
| 1043 | status = "disabled"; | ||
| 1044 | }; | ||
| 1045 | }; | ||
| 1046 | }; | ||
diff --git a/arch/arm/boot/dts/sama5d31ek.dts b/arch/arm/boot/dts/sama5d31ek.dts new file mode 100644 index 000000000000..fa5d216f1db7 --- /dev/null +++ b/arch/arm/boot/dts/sama5d31ek.dts | |||
| @@ -0,0 +1,51 @@ | |||
| 1 | /* | ||
| 2 | * sama5d31ek.dts - Device Tree file for SAMA5D31-EK board | ||
| 3 | * | ||
| 4 | * Copyright (C) 2013 Atmel, | ||
| 5 | * 2013 Ludovic Desroches <ludovic.desroches@atmel.com> | ||
| 6 | * | ||
| 7 | * Licensed under GPLv2 or later. | ||
| 8 | */ | ||
| 9 | /dts-v1/; | ||
| 10 | /include/ "sama5d3xmb.dtsi" | ||
| 11 | /include/ "sama5d3xdm.dtsi" | ||
| 12 | |||
| 13 | / { | ||
| 14 | model = "Atmel SAMA5D31-EK"; | ||
| 15 | compatible = "atmel,sama5d31ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5"; | ||
| 16 | |||
| 17 | ahb { | ||
| 18 | apb { | ||
| 19 | spi0: spi@f0004000 { | ||
| 20 | status = "okay"; | ||
| 21 | }; | ||
| 22 | |||
| 23 | ssc0: ssc@f0008000 { | ||
| 24 | status = "okay"; | ||
| 25 | }; | ||
| 26 | |||
| 27 | i2c0: i2c@f0014000 { | ||
| 28 | status = "okay"; | ||
| 29 | }; | ||
| 30 | |||
| 31 | i2c1: i2c@f0018000 { | ||
| 32 | status = "okay"; | ||
| 33 | }; | ||
| 34 | |||
| 35 | macb1: ethernet@f802c000 { | ||
| 36 | status = "okay"; | ||
| 37 | }; | ||
| 38 | }; | ||
| 39 | }; | ||
| 40 | |||
| 41 | leds { | ||
| 42 | d3 { | ||
| 43 | label = "d3"; | ||
| 44 | gpios = <&pioE 24 0>; | ||
| 45 | }; | ||
| 46 | }; | ||
| 47 | |||
| 48 | sound { | ||
| 49 | status = "okay"; | ||
| 50 | }; | ||
| 51 | }; | ||
diff --git a/arch/arm/boot/dts/sama5d33ek.dts b/arch/arm/boot/dts/sama5d33ek.dts new file mode 100644 index 000000000000..c38c9433d7a5 --- /dev/null +++ b/arch/arm/boot/dts/sama5d33ek.dts | |||
| @@ -0,0 +1,44 @@ | |||
| 1 | /* | ||
| 2 | * sama5d33ek.dts - Device Tree file for SAMA5D33-EK board | ||
| 3 | * | ||
| 4 | * Copyright (C) 2013 Atmel, | ||
| 5 | * 2013 Ludovic Desroches <ludovic.desroches@atmel.com> | ||
| 6 | * | ||
| 7 | * Licensed under GPLv2 or later. | ||
| 8 | */ | ||
| 9 | /dts-v1/; | ||
| 10 | /include/ "sama5d3xmb.dtsi" | ||
| 11 | /include/ "sama5d3xdm.dtsi" | ||
| 12 | |||
| 13 | / { | ||
| 14 | model = "Atmel SAMA5D33-EK"; | ||
| 15 | compatible = "atmel,sama5d33ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5"; | ||
| 16 | |||
| 17 | ahb { | ||
| 18 | apb { | ||
| 19 | spi0: spi@f0004000 { | ||
| 20 | status = "okay"; | ||
| 21 | }; | ||
| 22 | |||
| 23 | ssc0: ssc@f0008000 { | ||
| 24 | status = "okay"; | ||
| 25 | }; | ||
| 26 | |||
| 27 | i2c0: i2c@f0014000 { | ||
| 28 | status = "okay"; | ||
| 29 | }; | ||
| 30 | |||
| 31 | i2c1: i2c@f0018000 { | ||
| 32 | status = "okay"; | ||
| 33 | }; | ||
| 34 | |||
| 35 | macb0: ethernet@f0028000 { | ||
| 36 | status = "okay"; | ||
| 37 | }; | ||
| 38 | }; | ||
| 39 | }; | ||
| 40 | |||
| 41 | sound { | ||
| 42 | status = "okay"; | ||
| 43 | }; | ||
| 44 | }; | ||
diff --git a/arch/arm/boot/dts/sama5d34ek.dts b/arch/arm/boot/dts/sama5d34ek.dts new file mode 100644 index 000000000000..6bebfcdcb1d1 --- /dev/null +++ b/arch/arm/boot/dts/sama5d34ek.dts | |||
| @@ -0,0 +1,61 @@ | |||
| 1 | /* | ||
| 2 | * sama5d34ek.dts - Device Tree file for SAMA5D34-EK board | ||
| 3 | * | ||
| 4 | * Copyright (C) 2013 Atmel, | ||
| 5 | * 2013 Ludovic Desroches <ludovic.desroches@atmel.com> | ||
| 6 | * | ||
| 7 | * Licensed under GPLv2 or later. | ||
| 8 | */ | ||
| 9 | /dts-v1/; | ||
| 10 | /include/ "sama5d3xmb.dtsi" | ||
| 11 | /include/ "sama5d3xdm.dtsi" | ||
| 12 | |||
| 13 | / { | ||
| 14 | model = "Atmel SAMA5D34-EK"; | ||
| 15 | compatible = "atmel,sama5d34ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5"; | ||
| 16 | |||
| 17 | ahb { | ||
| 18 | apb { | ||
| 19 | spi0: spi@f0004000 { | ||
| 20 | status = "okay"; | ||
| 21 | }; | ||
| 22 | |||
| 23 | ssc0: ssc@f0008000 { | ||
| 24 | status = "okay"; | ||
| 25 | }; | ||
| 26 | |||
| 27 | can0: can@f000c000 { | ||
| 28 | status = "okay"; | ||
| 29 | }; | ||
| 30 | |||
| 31 | i2c0: i2c@f0014000 { | ||
| 32 | status = "okay"; | ||
| 33 | }; | ||
| 34 | |||
| 35 | i2c1: i2c@f0018000 { | ||
| 36 | status = "okay"; | ||
| 37 | |||
| 38 | 24c256@50 { | ||
| 39 | compatible = "24c256"; | ||
| 40 | reg = <0x50>; | ||
| 41 | pagesize = <64>; | ||
| 42 | }; | ||
| 43 | }; | ||
| 44 | |||
| 45 | macb0: ethernet@f0028000 { | ||
| 46 | status = "okay"; | ||
| 47 | }; | ||
| 48 | }; | ||
| 49 | }; | ||
| 50 | |||
| 51 | leds { | ||
| 52 | d3 { | ||
| 53 | label = "d3"; | ||
| 54 | gpios = <&pioE 24 0>; | ||
| 55 | }; | ||
| 56 | }; | ||
| 57 | |||
| 58 | sound { | ||
| 59 | status = "okay"; | ||
| 60 | }; | ||
| 61 | }; | ||
diff --git a/arch/arm/boot/dts/sama5d35ek.dts b/arch/arm/boot/dts/sama5d35ek.dts new file mode 100644 index 000000000000..a488fc4e9777 --- /dev/null +++ b/arch/arm/boot/dts/sama5d35ek.dts | |||
| @@ -0,0 +1,56 @@ | |||
| 1 | /* | ||
| 2 | * sama5d35ek.dts - Device Tree file for SAMA5D35-EK board | ||
| 3 | * | ||
| 4 | * Copyright (C) 2013 Atmel, | ||
| 5 | * 2013 Ludovic Desroches <ludovic.desroches@atmel.com> | ||
| 6 | * | ||
| 7 | * Licensed under GPLv2 or later. | ||
| 8 | */ | ||
| 9 | /dts-v1/; | ||
| 10 | /include/ "sama5d3xmb.dtsi" | ||
| 11 | |||
| 12 | / { | ||
| 13 | model = "Atmel SAMA5D35-EK"; | ||
| 14 | compatible = "atmel,sama5d35ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5"; | ||
| 15 | |||
| 16 | ahb { | ||
| 17 | apb { | ||
| 18 | spi0: spi@f0004000 { | ||
| 19 | status = "okay"; | ||
| 20 | }; | ||
| 21 | |||
| 22 | can0: can@f000c000 { | ||
| 23 | status = "okay"; | ||
| 24 | }; | ||
| 25 | |||
| 26 | i2c1: i2c@f0018000 { | ||
| 27 | status = "okay"; | ||
| 28 | }; | ||
| 29 | |||
| 30 | macb0: ethernet@f0028000 { | ||
| 31 | status = "okay"; | ||
| 32 | }; | ||
| 33 | |||
| 34 | isi: isi@f0034000 { | ||
| 35 | status = "okay"; | ||
| 36 | }; | ||
| 37 | |||
| 38 | macb1: ethernet@f802c000 { | ||
| 39 | status = "okay"; | ||
| 40 | }; | ||
| 41 | }; | ||
| 42 | }; | ||
| 43 | |||
| 44 | gpio_keys { | ||
| 45 | compatible = "gpio-keys"; | ||
| 46 | #address-cells = <1>; | ||
| 47 | #size-cells = <0>; | ||
| 48 | |||
| 49 | pb_user1 { | ||
| 50 | label = "pb_user1"; | ||
| 51 | gpios = <&pioE 27 0>; | ||
| 52 | linux,code = <0x100>; | ||
| 53 | gpio-key,wakeup; | ||
| 54 | }; | ||
| 55 | }; | ||
| 56 | }; | ||
diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi new file mode 100644 index 000000000000..1f8ed404626c --- /dev/null +++ b/arch/arm/boot/dts/sama5d3xcm.dtsi | |||
| @@ -0,0 +1,91 @@ | |||
| 1 | /* | ||
| 2 | * sama5d3xcm.dtsi - Device Tree Include file for SAMA5D3x CPU Module | ||
| 3 | * | ||
| 4 | * Copyright (C) 2013 Atmel, | ||
| 5 | * 2013 Ludovic Desroches <ludovic.desroches@atmel.com> | ||
| 6 | * | ||
| 7 | * Licensed under GPLv2 or later. | ||
| 8 | */ | ||
| 9 | /include/ "sama5d3.dtsi" | ||
| 10 | |||
| 11 | / { | ||
| 12 | compatible = "atmel,samad3xcm", "atmel,sama5d3", "atmel,sama5"; | ||
| 13 | |||
| 14 | chosen { | ||
| 15 | bootargs = "console=ttyS0,115200 rootfstype=ubifs ubi.mtd=5 root=ubi0:rootfs"; | ||
| 16 | }; | ||
| 17 | |||
| 18 | memory { | ||
| 19 | reg = <0x20000000 0x20000000>; | ||
| 20 | }; | ||
| 21 | |||
| 22 | clocks { | ||
| 23 | #address-cells = <1>; | ||
| 24 | #size-cells = <1>; | ||
| 25 | ranges; | ||
| 26 | |||
| 27 | main_clock: clock@0 { | ||
| 28 | compatible = "atmel,osc", "fixed-clock"; | ||
| 29 | clock-frequency = <12000000>; | ||
| 30 | }; | ||
| 31 | }; | ||
| 32 | |||
| 33 | ahb { | ||
| 34 | apb { | ||
| 35 | macb0: ethernet@f0028000 { | ||
| 36 | phy-mode = "rgmii"; | ||
| 37 | }; | ||
| 38 | }; | ||
| 39 | |||
| 40 | nand0: nand@60000000 { | ||
| 41 | nand-bus-width = <8>; | ||
| 42 | nand-ecc-mode = "hw"; | ||
| 43 | atmel,has-pmecc; | ||
| 44 | atmel,pmecc-cap = <4>; | ||
| 45 | atmel,pmecc-sector-size = <512>; | ||
| 46 | atmel,has-nfc; | ||
| 47 | atmel,use-nfc-sram; | ||
| 48 | nand-on-flash-bbt; | ||
| 49 | status = "okay"; | ||
| 50 | |||
| 51 | at91bootstrap@0 { | ||
| 52 | label = "at91bootstrap"; | ||
| 53 | reg = <0x0 0x40000>; | ||
| 54 | }; | ||
| 55 | |||
| 56 | bootloader@40000 { | ||
| 57 | label = "bootloader"; | ||
| 58 | reg = <0x40000 0x80000>; | ||
| 59 | }; | ||
| 60 | |||
| 61 | bootloaderenv@c0000 { | ||
| 62 | label = "bootloader env"; | ||
| 63 | reg = <0xc0000 0xc0000>; | ||
| 64 | }; | ||
| 65 | |||
| 66 | dtb@180000 { | ||
| 67 | label = "device tree"; | ||
| 68 | reg = <0x180000 0x80000>; | ||
| 69 | }; | ||
| 70 | |||
| 71 | kernel@200000 { | ||
| 72 | label = "kernel"; | ||
| 73 | reg = <0x200000 0x600000>; | ||
| 74 | }; | ||
| 75 | |||
| 76 | rootfs@800000 { | ||
| 77 | label = "rootfs"; | ||
| 78 | reg = <0x800000 0x0f800000>; | ||
| 79 | }; | ||
| 80 | }; | ||
| 81 | }; | ||
| 82 | |||
| 83 | leds { | ||
| 84 | compatible = "gpio-leds"; | ||
| 85 | |||
| 86 | d2 { | ||
| 87 | label = "d2"; | ||
| 88 | gpios = <&pioE 25 1>; /* PE25, conflicts with A25, RXD2 */ | ||
| 89 | }; | ||
| 90 | }; | ||
| 91 | }; | ||
diff --git a/arch/arm/boot/dts/sama5d3xdm.dtsi b/arch/arm/boot/dts/sama5d3xdm.dtsi new file mode 100644 index 000000000000..4b8830eb2060 --- /dev/null +++ b/arch/arm/boot/dts/sama5d3xdm.dtsi | |||
| @@ -0,0 +1,42 @@ | |||
| 1 | /* | ||
| 2 | * sama5d3dm.dtsi - Device Tree file for SAMA5 display module | ||
| 3 | * | ||
| 4 | * Copyright (C) 2013 Atmel, | ||
| 5 | * 2013 Ludovic Desroches <ludovic.desroches@atmel.com> | ||
| 6 | * | ||
| 7 | * Licensed under GPLv2 or later. | ||
| 8 | */ | ||
| 9 | |||
| 10 | / { | ||
| 11 | ahb { | ||
| 12 | apb { | ||
| 13 | i2c1: i2c@f0018000 { | ||
| 14 | qt1070: keyboard@1b { | ||
| 15 | compatible = "qt1070"; | ||
| 16 | reg = <0x1b>; | ||
| 17 | interrupt-parent = <&pioE>; | ||
| 18 | interrupts = <31 0x0>; | ||
| 19 | pinctrl-names = "default"; | ||
| 20 | pinctrl-0 = <&pinctrl_qt1070_irq>; | ||
| 21 | }; | ||
| 22 | }; | ||
| 23 | |||
| 24 | adc0: adc@f8018000 { | ||
| 25 | status = "disabled"; | ||
| 26 | }; | ||
| 27 | |||
| 28 | tsadcc: tsadcc@f8018000 { | ||
| 29 | status = "okay"; | ||
| 30 | }; | ||
| 31 | |||
| 32 | pinctrl@fffff200 { | ||
| 33 | board { | ||
| 34 | pinctrl_qt1070_irq: qt1070_irq { | ||
| 35 | atmel,pins = | ||
| 36 | <4 31 0x0 0x5>; /* PE31 GPIO with pull up deglith */ | ||
| 37 | }; | ||
| 38 | }; | ||
| 39 | }; | ||
| 40 | }; | ||
| 41 | }; | ||
| 42 | }; | ||
diff --git a/arch/arm/boot/dts/sama5d3xmb.dtsi b/arch/arm/boot/dts/sama5d3xmb.dtsi new file mode 100644 index 000000000000..661d7ca9c309 --- /dev/null +++ b/arch/arm/boot/dts/sama5d3xmb.dtsi | |||
| @@ -0,0 +1,166 @@ | |||
| 1 | /* | ||
| 2 | * sama5d3xmb.dts - Device Tree file for SAMA5D3x mother board | ||
| 3 | * | ||
| 4 | * Copyright (C) 2013 Atmel, | ||
| 5 | * 2013 Ludovic Desroches <ludovic.desroches@atmel.com> | ||
| 6 | * | ||
| 7 | * Licensed under GPLv2 or later. | ||
| 8 | */ | ||
| 9 | /include/ "sama5d3xcm.dtsi" | ||
| 10 | |||
| 11 | / { | ||
| 12 | compatible = "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5"; | ||
| 13 | |||
| 14 | ahb { | ||
| 15 | apb { | ||
| 16 | mmc0: mmc@f0000000 { | ||
| 17 | pinctrl-names = "default"; | ||
| 18 | pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>; | ||
| 19 | status = "okay"; | ||
| 20 | slot@0 { | ||
| 21 | reg = <0>; | ||
| 22 | bus-width = <4>; | ||
| 23 | cd-gpios = <&pioD 17 0>; | ||
| 24 | }; | ||
| 25 | }; | ||
| 26 | |||
| 27 | spi0: spi@f0004000 { | ||
| 28 | m25p80@0 { | ||
| 29 | compatible = "atmel,at25df321a"; | ||
| 30 | spi-max-frequency = <50000000>; | ||
| 31 | reg = <0>; | ||
| 32 | }; | ||
| 33 | }; | ||
| 34 | |||
| 35 | /* | ||
| 36 | * i2c0 conflicts with ISI: | ||
| 37 | * disable it to allow the use of ISI | ||
| 38 | * can not enable audio when i2c0 disabled | ||
| 39 | */ | ||
| 40 | i2c0: i2c@f0014000 { | ||
| 41 | wm8904: wm8904@1a { | ||
| 42 | compatible = "wm8904"; | ||
| 43 | reg = <0x1a>; | ||
| 44 | }; | ||
| 45 | }; | ||
| 46 | |||
| 47 | usart1: serial@f0020000 { | ||
| 48 | pinctrl-names = "default"; | ||
| 49 | pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts_cts>; | ||
| 50 | status = "okay"; | ||
| 51 | }; | ||
| 52 | |||
| 53 | isi: isi@f0034000 { | ||
| 54 | pinctrl-names = "default"; | ||
| 55 | pinctrl-0 = <&pinctrl_isi &pinctrl_isi_pck_as_mck &pinctrl_isi_power &pinctrl_isi_reset>; | ||
| 56 | }; | ||
| 57 | |||
| 58 | mmc1: mmc@f8000000 { | ||
| 59 | pinctrl-names = "default"; | ||
| 60 | pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>; | ||
| 61 | status = "okay"; | ||
| 62 | slot@0 { | ||
| 63 | reg = <0>; | ||
| 64 | bus-width = <4>; | ||
| 65 | cd-gpios = <&pioD 18 0>; | ||
| 66 | }; | ||
| 67 | }; | ||
| 68 | |||
| 69 | adc0: adc@f8018000 { | ||
| 70 | pinctrl-names = "default"; | ||
| 71 | pinctrl-0 = < | ||
| 72 | &pinctrl_adc0_adtrg | ||
| 73 | &pinctrl_adc0_ad0 | ||
| 74 | &pinctrl_adc0_ad1 | ||
| 75 | &pinctrl_adc0_ad2 | ||
| 76 | &pinctrl_adc0_ad3 | ||
| 77 | &pinctrl_adc0_ad4 | ||
| 78 | >; | ||
| 79 | status = "okay"; | ||
| 80 | }; | ||
| 81 | |||
| 82 | macb1: ethernet@f802c000 { | ||
| 83 | phy-mode = "rmii"; | ||
| 84 | }; | ||
| 85 | |||
| 86 | pinctrl@fffff200 { | ||
| 87 | board { | ||
| 88 | pinctrl_mmc0_cd: mmc0_cd { | ||
| 89 | atmel,pins = | ||
| 90 | <3 17 0x0 0x5>; /* PD17 GPIO with pullup deglitch */ | ||
| 91 | }; | ||
| 92 | |||
| 93 | pinctrl_mmc1_cd: mmc1_cd { | ||
| 94 | atmel,pins = | ||
| 95 | <3 18 0x0 0x5>; /* PD18 GPIO with pullup deglitch */ | ||
| 96 | }; | ||
| 97 | |||
| 98 | pinctrl_pck0_as_audio_mck: pck0_as_audio_mck { | ||
| 99 | atmel,pins = | ||
| 100 | <3 30 0x2 0x0>; /* PD30 periph B */ | ||
| 101 | }; | ||
| 102 | |||
| 103 | pinctrl_isi_reset: isi_reset-0 { | ||
| 104 | atmel,pins = | ||
| 105 | <4 24 0x0 0x0>; /* PE24 gpio */ | ||
| 106 | }; | ||
| 107 | |||
| 108 | pinctrl_isi_power: isi_power-0 { | ||
| 109 | atmel,pins = | ||
| 110 | <4 29 0x0 0x0>; /* PE29 gpio */ | ||
| 111 | }; | ||
| 112 | |||
| 113 | pinctrl_usba_vbus: usba_vbus { | ||
| 114 | atmel,pins = | ||
| 115 | <3 29 0x0 0x4>; /* PD29 GPIO with deglitch */ | ||
| 116 | }; | ||
| 117 | }; | ||
| 118 | }; | ||
| 119 | |||
| 120 | dbgu: serial@ffffee00 { | ||
| 121 | status = "okay"; | ||
| 122 | }; | ||
| 123 | |||
| 124 | watchdog@fffffe40 { | ||
| 125 | status = "okay"; | ||
| 126 | }; | ||
| 127 | }; | ||
| 128 | |||
| 129 | usb0: gadget@00500000 { | ||
| 130 | atmel,vbus-gpio = <&pioD 29 0>; | ||
| 131 | pinctrl-names = "default"; | ||
| 132 | pinctrl-0 = <&pinctrl_usba_vbus>; | ||
| 133 | status = "okay"; | ||
| 134 | }; | ||
| 135 | |||
| 136 | usb1: ohci@00600000 { | ||
| 137 | num-ports = <3>; | ||
| 138 | atmel,vbus-gpio = <&pioD 25 0 | ||
| 139 | &pioD 26 1 | ||
| 140 | &pioD 27 1 | ||
| 141 | >; | ||
| 142 | status = "okay"; | ||
| 143 | }; | ||
| 144 | |||
| 145 | usb2: ehci@00700000 { | ||
| 146 | status = "okay"; | ||
| 147 | }; | ||
| 148 | }; | ||
| 149 | |||
| 150 | sound { | ||
| 151 | compatible = "atmel,sama5d3ek-wm8904"; | ||
| 152 | pinctrl-names = "default"; | ||
| 153 | pinctrl-0 = <&pinctrl_pck0_as_audio_mck>; | ||
| 154 | |||
| 155 | atmel,model = "wm8904 @ SAMA5D3EK"; | ||
| 156 | atmel,audio-routing = | ||
| 157 | "Headphone Jack", "HPOUTL", | ||
| 158 | "Headphone Jack", "HPOUTR", | ||
| 159 | "IN2L", "Line In Jack", | ||
| 160 | "IN2R", "Line In Jack", | ||
| 161 | "IN1L", "Mic"; | ||
| 162 | |||
| 163 | atmel,ssc-controller = <&ssc0>; | ||
| 164 | atmel,audio-codec = <&wm8904>; | ||
| 165 | }; | ||
| 166 | }; | ||
diff --git a/arch/arm/boot/dts/spear1340.dtsi b/arch/arm/boot/dts/spear1340.dtsi index 34da11aa6795..e1786a0b2fcd 100644 --- a/arch/arm/boot/dts/spear1340.dtsi +++ b/arch/arm/boot/dts/spear1340.dtsi | |||
| @@ -113,6 +113,9 @@ | |||
| 113 | reg = <0xb4100000 0x1000>; | 113 | reg = <0xb4100000 0x1000>; |
| 114 | interrupts = <0 105 0x4>; | 114 | interrupts = <0 105 0x4>; |
| 115 | status = "disabled"; | 115 | status = "disabled"; |
| 116 | dmas = <&dwdma0 0x600 0 0 1>, /* 0xC << 11 */ | ||
| 117 | <&dwdma0 0x680 0 1 0>; /* 0xD << 7 */ | ||
| 118 | dma-names = "tx", "rx"; | ||
| 116 | }; | 119 | }; |
| 117 | 120 | ||
| 118 | thermal@e07008c4 { | 121 | thermal@e07008c4 { |
diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi index b4ca60f4eb42..45597fd91050 100644 --- a/arch/arm/boot/dts/spear13xx.dtsi +++ b/arch/arm/boot/dts/spear13xx.dtsi | |||
| @@ -98,13 +98,24 @@ | |||
| 98 | reg = <0xb2800000 0x1000>; | 98 | reg = <0xb2800000 0x1000>; |
| 99 | interrupts = <0 29 0x4>; | 99 | interrupts = <0 29 0x4>; |
| 100 | status = "disabled"; | 100 | status = "disabled"; |
| 101 | dmas = <&dwdma0 0 0 0 0>; | ||
| 102 | dma-names = "data"; | ||
| 101 | }; | 103 | }; |
| 102 | 104 | ||
| 103 | dma@ea800000 { | 105 | dwdma0: dma@ea800000 { |
| 104 | compatible = "snps,dma-spear1340"; | 106 | compatible = "snps,dma-spear1340"; |
| 105 | reg = <0xea800000 0x1000>; | 107 | reg = <0xea800000 0x1000>; |
| 106 | interrupts = <0 19 0x4>; | 108 | interrupts = <0 19 0x4>; |
| 107 | status = "disabled"; | 109 | status = "disabled"; |
| 110 | |||
| 111 | dma-channels = <8>; | ||
| 112 | #dma-cells = <3>; | ||
| 113 | dma-requests = <32>; | ||
| 114 | chan_allocation_order = <1>; | ||
| 115 | chan_priority = <1>; | ||
| 116 | block_size = <0xfff>; | ||
| 117 | dma-masters = <2>; | ||
| 118 | data_width = <3 3 0 0>; | ||
| 108 | }; | 119 | }; |
| 109 | 120 | ||
| 110 | dma@eb000000 { | 121 | dma@eb000000 { |
| @@ -112,6 +123,15 @@ | |||
| 112 | reg = <0xeb000000 0x1000>; | 123 | reg = <0xeb000000 0x1000>; |
| 113 | interrupts = <0 59 0x4>; | 124 | interrupts = <0 59 0x4>; |
| 114 | status = "disabled"; | 125 | status = "disabled"; |
| 126 | |||
| 127 | dma-requests = <32>; | ||
| 128 | dma-channels = <8>; | ||
| 129 | dma-masters = <2>; | ||
| 130 | #dma-cells = <3>; | ||
| 131 | chan_allocation_order = <1>; | ||
| 132 | chan_priority = <1>; | ||
| 133 | block_size = <0xfff>; | ||
| 134 | data_width = <3 3 0 0>; | ||
| 115 | }; | 135 | }; |
| 116 | 136 | ||
| 117 | fsmc: flash@b0000000 { | 137 | fsmc: flash@b0000000 { |
| @@ -261,6 +281,9 @@ | |||
| 261 | #size-cells = <0>; | 281 | #size-cells = <0>; |
| 262 | interrupts = <0 31 0x4>; | 282 | interrupts = <0 31 0x4>; |
| 263 | status = "disabled"; | 283 | status = "disabled"; |
| 284 | dmas = <&dwdma0 0x2000 0 0 0>, /* 0x4 << 11 */ | ||
| 285 | <&dwdma0 0x0280 0 0 0>; /* 0x5 << 7 */ | ||
| 286 | dma-names = "tx", "rx"; | ||
| 264 | }; | 287 | }; |
| 265 | 288 | ||
| 266 | rtc@e0580000 { | 289 | rtc@e0580000 { |
diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts index a30aca62658a..616990dc92db 100644 --- a/arch/arm/boot/dts/tegra114-dalmore.dts +++ b/arch/arm/boot/dts/tegra114-dalmore.dts | |||
| @@ -12,10 +12,22 @@ | |||
| 12 | 12 | ||
| 13 | serial@70006300 { | 13 | serial@70006300 { |
| 14 | status = "okay"; | 14 | status = "okay"; |
| 15 | clock-frequency = <408000000>; | ||
| 16 | }; | 15 | }; |
| 17 | 16 | ||
| 18 | pmc { | 17 | pmc { |
| 19 | nvidia,invert-interrupt; | 18 | nvidia,invert-interrupt; |
| 20 | }; | 19 | }; |
| 20 | |||
| 21 | clocks { | ||
| 22 | compatible = "simple-bus"; | ||
| 23 | #address-cells = <1>; | ||
| 24 | #size-cells = <0>; | ||
| 25 | |||
| 26 | clk32k_in: clock { | ||
| 27 | compatible = "fixed-clock"; | ||
| 28 | reg=<0>; | ||
| 29 | #clock-cells = <0>; | ||
| 30 | clock-frequency = <32768>; | ||
| 31 | }; | ||
| 32 | }; | ||
| 21 | }; | 33 | }; |
diff --git a/arch/arm/boot/dts/tegra114-pluto.dts b/arch/arm/boot/dts/tegra114-pluto.dts index 9bea8f57aa47..6bbc8efae9c0 100644 --- a/arch/arm/boot/dts/tegra114-pluto.dts +++ b/arch/arm/boot/dts/tegra114-pluto.dts | |||
| @@ -12,10 +12,22 @@ | |||
| 12 | 12 | ||
| 13 | serial@70006300 { | 13 | serial@70006300 { |
| 14 | status = "okay"; | 14 | status = "okay"; |
| 15 | clock-frequency = <408000000>; | ||
| 16 | }; | 15 | }; |
| 17 | 16 | ||
| 18 | pmc { | 17 | pmc { |
| 19 | nvidia,invert-interrupt; | 18 | nvidia,invert-interrupt; |
| 20 | }; | 19 | }; |
| 20 | |||
| 21 | clocks { | ||
| 22 | compatible = "simple-bus"; | ||
| 23 | #address-cells = <1>; | ||
| 24 | #size-cells = <0>; | ||
| 25 | |||
| 26 | clk32k_in: clock { | ||
| 27 | compatible = "fixed-clock"; | ||
| 28 | reg=<0>; | ||
| 29 | #clock-cells = <0>; | ||
| 30 | clock-frequency = <32768>; | ||
| 31 | }; | ||
| 32 | }; | ||
| 21 | }; | 33 | }; |
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index 1dfaf2874c57..c1110a9b2a91 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi | |||
| @@ -24,10 +24,11 @@ | |||
| 24 | 0 42 0x04 | 24 | 0 42 0x04 |
| 25 | 0 121 0x04 | 25 | 0 121 0x04 |
| 26 | 0 122 0x04>; | 26 | 0 122 0x04>; |
| 27 | clocks = <&tegra_car 5>; | ||
| 27 | }; | 28 | }; |
| 28 | 29 | ||
| 29 | tegra_car: clock { | 30 | tegra_car: clock { |
| 30 | compatible = "nvidia,tegra114-car, nvidia,tegra30-car"; | 31 | compatible = "nvidia,tegra114-car"; |
| 31 | reg = <0x60006000 0x1000>; | 32 | reg = <0x60006000 0x1000>; |
| 32 | #clock-cells = <1>; | 33 | #clock-cells = <1>; |
| 33 | }; | 34 | }; |
| @@ -66,6 +67,7 @@ | |||
| 66 | reg-shift = <2>; | 67 | reg-shift = <2>; |
| 67 | interrupts = <0 36 0x04>; | 68 | interrupts = <0 36 0x04>; |
| 68 | status = "disabled"; | 69 | status = "disabled"; |
| 70 | clocks = <&tegra_car 6>; | ||
| 69 | }; | 71 | }; |
| 70 | 72 | ||
| 71 | serial@70006040 { | 73 | serial@70006040 { |
| @@ -74,6 +76,7 @@ | |||
| 74 | reg-shift = <2>; | 76 | reg-shift = <2>; |
| 75 | interrupts = <0 37 0x04>; | 77 | interrupts = <0 37 0x04>; |
| 76 | status = "disabled"; | 78 | status = "disabled"; |
| 79 | clocks = <&tegra_car 192>; | ||
| 77 | }; | 80 | }; |
| 78 | 81 | ||
| 79 | serial@70006200 { | 82 | serial@70006200 { |
| @@ -82,6 +85,7 @@ | |||
| 82 | reg-shift = <2>; | 85 | reg-shift = <2>; |
| 83 | interrupts = <0 46 0x04>; | 86 | interrupts = <0 46 0x04>; |
| 84 | status = "disabled"; | 87 | status = "disabled"; |
| 88 | clocks = <&tegra_car 55>; | ||
| 85 | }; | 89 | }; |
| 86 | 90 | ||
| 87 | serial@70006300 { | 91 | serial@70006300 { |
| @@ -90,17 +94,21 @@ | |||
| 90 | reg-shift = <2>; | 94 | reg-shift = <2>; |
| 91 | interrupts = <0 90 0x04>; | 95 | interrupts = <0 90 0x04>; |
| 92 | status = "disabled"; | 96 | status = "disabled"; |
| 97 | clocks = <&tegra_car 65>; | ||
| 93 | }; | 98 | }; |
| 94 | 99 | ||
| 95 | rtc { | 100 | rtc { |
| 96 | compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc"; | 101 | compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc"; |
| 97 | reg = <0x7000e000 0x100>; | 102 | reg = <0x7000e000 0x100>; |
| 98 | interrupts = <0 2 0x04>; | 103 | interrupts = <0 2 0x04>; |
| 104 | clocks = <&tegra_car 4>; | ||
| 99 | }; | 105 | }; |
| 100 | 106 | ||
| 101 | pmc { | 107 | pmc { |
| 102 | compatible = "nvidia,tegra114-pmc", "nvidia,tegra30-pmc"; | 108 | compatible = "nvidia,tegra114-pmc"; |
| 103 | reg = <0x7000e400 0x400>; | 109 | reg = <0x7000e400 0x400>; |
| 110 | clocks = <&tegra_car 261>, <&clk32k_in>; | ||
| 111 | clock-names = "pclk", "clk32k_in"; | ||
| 104 | }; | 112 | }; |
| 105 | 113 | ||
| 106 | iommu { | 114 | iommu { |
diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi b/arch/arm/boot/dts/tegra20-colibri-512.dtsi index 444162090042..4e3afdef28a8 100644 --- a/arch/arm/boot/dts/tegra20-colibri-512.dtsi +++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsi | |||
| @@ -444,7 +444,20 @@ | |||
| 444 | }; | 444 | }; |
| 445 | 445 | ||
| 446 | sdhci@c8000600 { | 446 | sdhci@c8000600 { |
| 447 | cd-gpios = <&gpio 23 0>; /* gpio PC7 */ | 447 | cd-gpios = <&gpio 23 1>; /* gpio PC7 */ |
| 448 | }; | ||
| 449 | |||
| 450 | clocks { | ||
| 451 | compatible = "simple-bus"; | ||
| 452 | #address-cells = <1>; | ||
| 453 | #size-cells = <0>; | ||
| 454 | |||
| 455 | clk32k_in: clock { | ||
| 456 | compatible = "fixed-clock"; | ||
| 457 | reg=<0>; | ||
| 458 | #clock-cells = <0>; | ||
| 459 | clock-frequency = <32768>; | ||
| 460 | }; | ||
| 448 | }; | 461 | }; |
| 449 | 462 | ||
| 450 | sound { | 463 | sound { |
diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts index 61d027f03617..ae9d5a20834e 100644 --- a/arch/arm/boot/dts/tegra20-harmony.dts +++ b/arch/arm/boot/dts/tegra20-harmony.dts | |||
| @@ -437,7 +437,7 @@ | |||
| 437 | 437 | ||
| 438 | sdhci@c8000200 { | 438 | sdhci@c8000200 { |
| 439 | status = "okay"; | 439 | status = "okay"; |
| 440 | cd-gpios = <&gpio 69 0>; /* gpio PI5 */ | 440 | cd-gpios = <&gpio 69 1>; /* gpio PI5 */ |
| 441 | wp-gpios = <&gpio 57 0>; /* gpio PH1 */ | 441 | wp-gpios = <&gpio 57 0>; /* gpio PH1 */ |
| 442 | power-gpios = <&gpio 155 0>; /* gpio PT3 */ | 442 | power-gpios = <&gpio 155 0>; /* gpio PT3 */ |
| 443 | bus-width = <4>; | 443 | bus-width = <4>; |
| @@ -445,12 +445,25 @@ | |||
| 445 | 445 | ||
| 446 | sdhci@c8000600 { | 446 | sdhci@c8000600 { |
| 447 | status = "okay"; | 447 | status = "okay"; |
| 448 | cd-gpios = <&gpio 58 0>; /* gpio PH2 */ | 448 | cd-gpios = <&gpio 58 1>; /* gpio PH2 */ |
| 449 | wp-gpios = <&gpio 59 0>; /* gpio PH3 */ | 449 | wp-gpios = <&gpio 59 0>; /* gpio PH3 */ |
| 450 | power-gpios = <&gpio 70 0>; /* gpio PI6 */ | 450 | power-gpios = <&gpio 70 0>; /* gpio PI6 */ |
| 451 | bus-width = <8>; | 451 | bus-width = <8>; |
| 452 | }; | 452 | }; |
| 453 | 453 | ||
| 454 | clocks { | ||
| 455 | compatible = "simple-bus"; | ||
| 456 | #address-cells = <1>; | ||
| 457 | #size-cells = <0>; | ||
| 458 | |||
| 459 | clk32k_in: clock { | ||
| 460 | compatible = "fixed-clock"; | ||
| 461 | reg=<0>; | ||
| 462 | #clock-cells = <0>; | ||
| 463 | clock-frequency = <32768>; | ||
| 464 | }; | ||
| 465 | }; | ||
| 466 | |||
| 454 | kbc { | 467 | kbc { |
| 455 | status = "okay"; | 468 | status = "okay"; |
| 456 | nvidia,debounce-delay-ms = <2>; | 469 | nvidia,debounce-delay-ms = <2>; |
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index 54d6fce00a59..fd60940e4063 100644 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts | |||
| @@ -436,7 +436,7 @@ | |||
| 436 | 436 | ||
| 437 | sdhci@c8000000 { | 437 | sdhci@c8000000 { |
| 438 | status = "okay"; | 438 | status = "okay"; |
| 439 | cd-gpios = <&gpio 173 0>; /* gpio PV5 */ | 439 | cd-gpios = <&gpio 173 1>; /* gpio PV5 */ |
| 440 | wp-gpios = <&gpio 57 0>; /* gpio PH1 */ | 440 | wp-gpios = <&gpio 57 0>; /* gpio PH1 */ |
| 441 | power-gpios = <&gpio 169 0>; /* gpio PV1 */ | 441 | power-gpios = <&gpio 169 0>; /* gpio PV1 */ |
| 442 | bus-width = <4>; | 442 | bus-width = <4>; |
| @@ -447,6 +447,19 @@ | |||
| 447 | bus-width = <8>; | 447 | bus-width = <8>; |
| 448 | }; | 448 | }; |
| 449 | 449 | ||
| 450 | clocks { | ||
| 451 | compatible = "simple-bus"; | ||
| 452 | #address-cells = <1>; | ||
| 453 | #size-cells = <0>; | ||
| 454 | |||
| 455 | clk32k_in: clock { | ||
| 456 | compatible = "fixed-clock"; | ||
| 457 | reg=<0>; | ||
| 458 | #clock-cells = <0>; | ||
| 459 | clock-frequency = <32768>; | ||
| 460 | }; | ||
| 461 | }; | ||
| 462 | |||
| 450 | gpio-keys { | 463 | gpio-keys { |
| 451 | compatible = "gpio-keys"; | 464 | compatible = "gpio-keys"; |
| 452 | 465 | ||
diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts index 37b3a57ec0f1..4ee700a33ca5 100644 --- a/arch/arm/boot/dts/tegra20-seaboard.dts +++ b/arch/arm/boot/dts/tegra20-seaboard.dts | |||
| @@ -584,7 +584,7 @@ | |||
| 584 | 584 | ||
| 585 | sdhci@c8000400 { | 585 | sdhci@c8000400 { |
| 586 | status = "okay"; | 586 | status = "okay"; |
| 587 | cd-gpios = <&gpio 69 0>; /* gpio PI5 */ | 587 | cd-gpios = <&gpio 69 1>; /* gpio PI5 */ |
| 588 | wp-gpios = <&gpio 57 0>; /* gpio PH1 */ | 588 | wp-gpios = <&gpio 57 0>; /* gpio PH1 */ |
| 589 | power-gpios = <&gpio 70 0>; /* gpio PI6 */ | 589 | power-gpios = <&gpio 70 0>; /* gpio PI6 */ |
| 590 | bus-width = <4>; | 590 | bus-width = <4>; |
| @@ -595,6 +595,19 @@ | |||
| 595 | bus-width = <8>; | 595 | bus-width = <8>; |
| 596 | }; | 596 | }; |
| 597 | 597 | ||
| 598 | clocks { | ||
| 599 | compatible = "simple-bus"; | ||
| 600 | #address-cells = <1>; | ||
| 601 | #size-cells = <0>; | ||
| 602 | |||
| 603 | clk32k_in: clock { | ||
| 604 | compatible = "fixed-clock"; | ||
| 605 | reg=<0>; | ||
| 606 | #clock-cells = <0>; | ||
| 607 | clock-frequency = <32768>; | ||
| 608 | }; | ||
| 609 | }; | ||
| 610 | |||
| 598 | gpio-keys { | 611 | gpio-keys { |
| 599 | compatible = "gpio-keys"; | 612 | compatible = "gpio-keys"; |
| 600 | 613 | ||
diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi index 4766abae7a72..c19025725918 100644 --- a/arch/arm/boot/dts/tegra20-tamonten.dtsi +++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi | |||
| @@ -465,12 +465,25 @@ | |||
| 465 | }; | 465 | }; |
| 466 | 466 | ||
| 467 | sdhci@c8000600 { | 467 | sdhci@c8000600 { |
| 468 | cd-gpios = <&gpio 58 0>; /* gpio PH2 */ | 468 | cd-gpios = <&gpio 58 1>; /* gpio PH2 */ |
| 469 | wp-gpios = <&gpio 59 0>; /* gpio PH3 */ | 469 | wp-gpios = <&gpio 59 0>; /* gpio PH3 */ |
| 470 | bus-width = <4>; | 470 | bus-width = <4>; |
| 471 | status = "okay"; | 471 | status = "okay"; |
| 472 | }; | 472 | }; |
| 473 | 473 | ||
| 474 | clocks { | ||
| 475 | compatible = "simple-bus"; | ||
| 476 | #address-cells = <1>; | ||
| 477 | #size-cells = <0>; | ||
| 478 | |||
| 479 | clk32k_in: clock { | ||
| 480 | compatible = "fixed-clock"; | ||
| 481 | reg=<0>; | ||
| 482 | #clock-cells = <0>; | ||
| 483 | clock-frequency = <32768>; | ||
| 484 | }; | ||
| 485 | }; | ||
| 486 | |||
| 474 | regulators { | 487 | regulators { |
| 475 | compatible = "simple-bus"; | 488 | compatible = "simple-bus"; |
| 476 | 489 | ||
diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts index 5d79e4fc49a6..a9f3f06580f5 100644 --- a/arch/arm/boot/dts/tegra20-trimslice.dts +++ b/arch/arm/boot/dts/tegra20-trimslice.dts | |||
| @@ -325,11 +325,24 @@ | |||
| 325 | 325 | ||
| 326 | sdhci@c8000600 { | 326 | sdhci@c8000600 { |
| 327 | status = "okay"; | 327 | status = "okay"; |
| 328 | cd-gpios = <&gpio 121 0>; /* gpio PP1 */ | 328 | cd-gpios = <&gpio 121 1>; /* gpio PP1 */ |
| 329 | wp-gpios = <&gpio 122 0>; /* gpio PP2 */ | 329 | wp-gpios = <&gpio 122 0>; /* gpio PP2 */ |
| 330 | bus-width = <4>; | 330 | bus-width = <4>; |
| 331 | }; | 331 | }; |
| 332 | 332 | ||
| 333 | clocks { | ||
| 334 | compatible = "simple-bus"; | ||
| 335 | #address-cells = <1>; | ||
| 336 | #size-cells = <0>; | ||
| 337 | |||
| 338 | clk32k_in: clock { | ||
| 339 | compatible = "fixed-clock"; | ||
| 340 | reg=<0>; | ||
| 341 | #clock-cells = <0>; | ||
| 342 | clock-frequency = <32768>; | ||
| 343 | }; | ||
| 344 | }; | ||
| 345 | |||
| 333 | poweroff { | 346 | poweroff { |
| 334 | compatible = "gpio-poweroff"; | 347 | compatible = "gpio-poweroff"; |
| 335 | gpios = <&gpio 191 1>; /* gpio PX7, active low */ | 348 | gpios = <&gpio 191 1>; /* gpio PX7, active low */ |
diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts index 425c89000c20..f544806e9618 100644 --- a/arch/arm/boot/dts/tegra20-ventana.dts +++ b/arch/arm/boot/dts/tegra20-ventana.dts | |||
| @@ -520,7 +520,7 @@ | |||
| 520 | 520 | ||
| 521 | sdhci@c8000400 { | 521 | sdhci@c8000400 { |
| 522 | status = "okay"; | 522 | status = "okay"; |
| 523 | cd-gpios = <&gpio 69 0>; /* gpio PI5 */ | 523 | cd-gpios = <&gpio 69 1>; /* gpio PI5 */ |
| 524 | wp-gpios = <&gpio 57 0>; /* gpio PH1 */ | 524 | wp-gpios = <&gpio 57 0>; /* gpio PH1 */ |
| 525 | power-gpios = <&gpio 70 0>; /* gpio PI6 */ | 525 | power-gpios = <&gpio 70 0>; /* gpio PI6 */ |
| 526 | bus-width = <4>; | 526 | bus-width = <4>; |
| @@ -531,6 +531,19 @@ | |||
| 531 | bus-width = <8>; | 531 | bus-width = <8>; |
| 532 | }; | 532 | }; |
| 533 | 533 | ||
| 534 | clocks { | ||
| 535 | compatible = "simple-bus"; | ||
| 536 | #address-cells = <1>; | ||
| 537 | #size-cells = <0>; | ||
| 538 | |||
| 539 | clk32k_in: clock { | ||
| 540 | compatible = "fixed-clock"; | ||
| 541 | reg=<0>; | ||
| 542 | #clock-cells = <0>; | ||
| 543 | clock-frequency = <32768>; | ||
| 544 | }; | ||
| 545 | }; | ||
| 546 | |||
| 534 | regulators { | 547 | regulators { |
| 535 | compatible = "simple-bus"; | 548 | compatible = "simple-bus"; |
| 536 | #address-cells = <1>; | 549 | #address-cells = <1>; |
diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts index ea57c0f6dcce..258cf945f515 100644 --- a/arch/arm/boot/dts/tegra20-whistler.dts +++ b/arch/arm/boot/dts/tegra20-whistler.dts | |||
| @@ -510,6 +510,7 @@ | |||
| 510 | 510 | ||
| 511 | sdhci@c8000400 { | 511 | sdhci@c8000400 { |
| 512 | status = "okay"; | 512 | status = "okay"; |
| 513 | cd-gpios = <&gpio 69 1>; /* gpio PI5 */ | ||
| 513 | wp-gpios = <&gpio 173 0>; /* gpio PV5 */ | 514 | wp-gpios = <&gpio 173 0>; /* gpio PV5 */ |
| 514 | bus-width = <8>; | 515 | bus-width = <8>; |
| 515 | }; | 516 | }; |
| @@ -519,6 +520,19 @@ | |||
| 519 | bus-width = <8>; | 520 | bus-width = <8>; |
| 520 | }; | 521 | }; |
| 521 | 522 | ||
| 523 | clocks { | ||
| 524 | compatible = "simple-bus"; | ||
| 525 | #address-cells = <1>; | ||
| 526 | #size-cells = <0>; | ||
| 527 | |||
| 528 | clk32k_in: clock { | ||
| 529 | compatible = "fixed-clock"; | ||
| 530 | reg=<0>; | ||
| 531 | #clock-cells = <0>; | ||
| 532 | clock-frequency = <32768>; | ||
| 533 | }; | ||
| 534 | }; | ||
| 535 | |||
| 522 | kbc { | 536 | kbc { |
| 523 | status = "okay"; | 537 | status = "okay"; |
| 524 | nvidia,debounce-delay-ms = <20>; | 538 | nvidia,debounce-delay-ms = <20>; |
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 3d3f64d2111a..fc7febc2b386 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi | |||
| @@ -145,6 +145,7 @@ | |||
| 145 | 0 1 0x04 | 145 | 0 1 0x04 |
| 146 | 0 41 0x04 | 146 | 0 41 0x04 |
| 147 | 0 42 0x04>; | 147 | 0 42 0x04>; |
| 148 | clocks = <&tegra_car 5>; | ||
| 148 | }; | 149 | }; |
| 149 | 150 | ||
| 150 | tegra_car: clock { | 151 | tegra_car: clock { |
| @@ -304,6 +305,7 @@ | |||
| 304 | compatible = "nvidia,tegra20-rtc"; | 305 | compatible = "nvidia,tegra20-rtc"; |
| 305 | reg = <0x7000e000 0x100>; | 306 | reg = <0x7000e000 0x100>; |
| 306 | interrupts = <0 2 0x04>; | 307 | interrupts = <0 2 0x04>; |
| 308 | clocks = <&tegra_car 4>; | ||
| 307 | }; | 309 | }; |
| 308 | 310 | ||
| 309 | i2c@7000c000 { | 311 | i2c@7000c000 { |
| @@ -416,6 +418,8 @@ | |||
| 416 | pmc { | 418 | pmc { |
| 417 | compatible = "nvidia,tegra20-pmc"; | 419 | compatible = "nvidia,tegra20-pmc"; |
| 418 | reg = <0x7000e400 0x400>; | 420 | reg = <0x7000e400 0x400>; |
| 421 | clocks = <&tegra_car 110>, <&clk32k_in>; | ||
| 422 | clock-names = "pclk", "clk32k_in"; | ||
| 419 | }; | 423 | }; |
| 420 | 424 | ||
| 421 | memory-controller@7000f000 { | 425 | memory-controller@7000f000 { |
diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts index 8ff2ff20e4a3..6248b2445b32 100644 --- a/arch/arm/boot/dts/tegra30-beaver.dts +++ b/arch/arm/boot/dts/tegra30-beaver.dts | |||
| @@ -257,7 +257,7 @@ | |||
| 257 | 257 | ||
| 258 | sdhci@78000000 { | 258 | sdhci@78000000 { |
| 259 | status = "okay"; | 259 | status = "okay"; |
| 260 | cd-gpios = <&gpio 69 0>; /* gpio PI5 */ | 260 | cd-gpios = <&gpio 69 1>; /* gpio PI5 */ |
| 261 | wp-gpios = <&gpio 155 0>; /* gpio PT3 */ | 261 | wp-gpios = <&gpio 155 0>; /* gpio PT3 */ |
| 262 | power-gpios = <&gpio 31 0>; /* gpio PD7 */ | 262 | power-gpios = <&gpio 31 0>; /* gpio PD7 */ |
| 263 | bus-width = <4>; | 263 | bus-width = <4>; |
| @@ -268,6 +268,19 @@ | |||
| 268 | bus-width = <8>; | 268 | bus-width = <8>; |
| 269 | }; | 269 | }; |
| 270 | 270 | ||
| 271 | clocks { | ||
| 272 | compatible = "simple-bus"; | ||
| 273 | #address-cells = <1>; | ||
| 274 | #size-cells = <0>; | ||
| 275 | |||
| 276 | clk32k_in: clock { | ||
| 277 | compatible = "fixed-clock"; | ||
| 278 | reg=<0>; | ||
| 279 | #clock-cells = <0>; | ||
| 280 | clock-frequency = <32768>; | ||
| 281 | }; | ||
| 282 | }; | ||
| 283 | |||
| 271 | regulators { | 284 | regulators { |
| 272 | compatible = "simple-bus"; | 285 | compatible = "simple-bus"; |
| 273 | #address-cells = <1>; | 286 | #address-cells = <1>; |
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi index 17499272a4ef..65bf2b63174e 100644 --- a/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi | |||
| @@ -311,7 +311,7 @@ | |||
| 311 | 311 | ||
| 312 | sdhci@78000000 { | 312 | sdhci@78000000 { |
| 313 | status = "okay"; | 313 | status = "okay"; |
| 314 | cd-gpios = <&gpio 69 0>; /* gpio PI5 */ | 314 | cd-gpios = <&gpio 69 1>; /* gpio PI5 */ |
| 315 | wp-gpios = <&gpio 155 0>; /* gpio PT3 */ | 315 | wp-gpios = <&gpio 155 0>; /* gpio PT3 */ |
| 316 | power-gpios = <&gpio 31 0>; /* gpio PD7 */ | 316 | power-gpios = <&gpio 31 0>; /* gpio PD7 */ |
| 317 | bus-width = <4>; | 317 | bus-width = <4>; |
| @@ -322,6 +322,19 @@ | |||
| 322 | bus-width = <8>; | 322 | bus-width = <8>; |
| 323 | }; | 323 | }; |
| 324 | 324 | ||
| 325 | clocks { | ||
| 326 | compatible = "simple-bus"; | ||
| 327 | #address-cells = <1>; | ||
| 328 | #size-cells = <0>; | ||
| 329 | |||
| 330 | clk32k_in: clock { | ||
| 331 | compatible = "fixed-clock"; | ||
| 332 | reg=<0>; | ||
| 333 | #clock-cells = <0>; | ||
| 334 | clock-frequency = <32768>; | ||
| 335 | }; | ||
| 336 | }; | ||
| 337 | |||
| 325 | regulators { | 338 | regulators { |
| 326 | compatible = "simple-bus"; | 339 | compatible = "simple-bus"; |
| 327 | #address-cells = <1>; | 340 | #address-cells = <1>; |
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index dbf46c272562..9fe7a92b4c85 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi | |||
| @@ -148,6 +148,7 @@ | |||
| 148 | 0 42 0x04 | 148 | 0 42 0x04 |
| 149 | 0 121 0x04 | 149 | 0 121 0x04 |
| 150 | 0 122 0x04>; | 150 | 0 122 0x04>; |
| 151 | clocks = <&tegra_car 5>; | ||
| 151 | }; | 152 | }; |
| 152 | 153 | ||
| 153 | tegra_car: clock { | 154 | tegra_car: clock { |
| @@ -291,6 +292,7 @@ | |||
| 291 | compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc"; | 292 | compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc"; |
| 292 | reg = <0x7000e000 0x100>; | 293 | reg = <0x7000e000 0x100>; |
| 293 | interrupts = <0 2 0x04>; | 294 | interrupts = <0 2 0x04>; |
| 295 | clocks = <&tegra_car 4>; | ||
| 294 | }; | 296 | }; |
| 295 | 297 | ||
| 296 | i2c@7000c000 { | 298 | i2c@7000c000 { |
| @@ -423,8 +425,10 @@ | |||
| 423 | }; | 425 | }; |
| 424 | 426 | ||
| 425 | pmc { | 427 | pmc { |
| 426 | compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc"; | 428 | compatible = "nvidia,tegra30-pmc"; |
| 427 | reg = <0x7000e400 0x400>; | 429 | reg = <0x7000e400 0x400>; |
| 430 | clocks = <&tegra_car 218>, <&clk32k_in>; | ||
| 431 | clock-names = "pclk", "clk32k_in"; | ||
| 428 | }; | 432 | }; |
| 429 | 433 | ||
| 430 | memory-controller { | 434 | memory-controller { |
diff --git a/arch/arm/boot/dts/versatile-ab.dts b/arch/arm/boot/dts/versatile-ab.dts index e2fe3195c0d1..dde75ae8b4b1 100644 --- a/arch/arm/boot/dts/versatile-ab.dts +++ b/arch/arm/boot/dts/versatile-ab.dts | |||
| @@ -121,6 +121,18 @@ | |||
| 121 | interrupts = <0>; | 121 | interrupts = <0>; |
| 122 | }; | 122 | }; |
| 123 | 123 | ||
| 124 | timer@101e2000 { | ||
| 125 | compatible = "arm,sp804", "arm,primecell"; | ||
| 126 | reg = <0x101e2000 0x1000>; | ||
| 127 | interrupts = <4>; | ||
| 128 | }; | ||
| 129 | |||
| 130 | timer@101e3000 { | ||
| 131 | compatible = "arm,sp804", "arm,primecell"; | ||
| 132 | reg = <0x101e3000 0x1000>; | ||
| 133 | interrupts = <5>; | ||
| 134 | }; | ||
| 135 | |||
| 124 | gpio0: gpio@101e4000 { | 136 | gpio0: gpio@101e4000 { |
| 125 | compatible = "arm,pl061", "arm,primecell"; | 137 | compatible = "arm,pl061", "arm,primecell"; |
| 126 | reg = <0x101e4000 0x1000>; | 138 | reg = <0x101e4000 0x1000>; |
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca9.dts b/arch/arm/boot/dts/vexpress-v2p-ca9.dts index 1420bb14d95c..62d9b225dcce 100644 --- a/arch/arm/boot/dts/vexpress-v2p-ca9.dts +++ b/arch/arm/boot/dts/vexpress-v2p-ca9.dts | |||
| @@ -98,6 +98,7 @@ | |||
| 98 | <0 49 4>; | 98 | <0 49 4>; |
| 99 | clocks = <&oscclk2>, <&oscclk2>; | 99 | clocks = <&oscclk2>, <&oscclk2>; |
| 100 | clock-names = "timclk", "apb_pclk"; | 100 | clock-names = "timclk", "apb_pclk"; |
| 101 | status = "disabled"; | ||
| 101 | }; | 102 | }; |
| 102 | 103 | ||
| 103 | watchdog@100e5000 { | 104 | watchdog@100e5000 { |
diff --git a/arch/arm/common/timer-sp.c b/arch/arm/common/timer-sp.c index 9d2d3ba339ff..ddc740769601 100644 --- a/arch/arm/common/timer-sp.c +++ b/arch/arm/common/timer-sp.c | |||
| @@ -25,33 +25,29 @@ | |||
| 25 | #include <linux/interrupt.h> | 25 | #include <linux/interrupt.h> |
| 26 | #include <linux/irq.h> | 26 | #include <linux/irq.h> |
| 27 | #include <linux/io.h> | 27 | #include <linux/io.h> |
| 28 | #include <linux/of.h> | ||
| 29 | #include <linux/of_address.h> | ||
| 30 | #include <linux/of_irq.h> | ||
| 28 | 31 | ||
| 29 | #include <asm/sched_clock.h> | 32 | #include <asm/sched_clock.h> |
| 30 | #include <asm/hardware/arm_timer.h> | 33 | #include <asm/hardware/arm_timer.h> |
| 34 | #include <asm/hardware/timer-sp.h> | ||
| 31 | 35 | ||
| 32 | static long __init sp804_get_clock_rate(const char *name) | 36 | static long __init sp804_get_clock_rate(struct clk *clk) |
| 33 | { | 37 | { |
| 34 | struct clk *clk; | ||
| 35 | long rate; | 38 | long rate; |
| 36 | int err; | 39 | int err; |
| 37 | 40 | ||
| 38 | clk = clk_get_sys("sp804", name); | ||
| 39 | if (IS_ERR(clk)) { | ||
| 40 | pr_err("sp804: %s clock not found: %d\n", name, | ||
| 41 | (int)PTR_ERR(clk)); | ||
| 42 | return PTR_ERR(clk); | ||
| 43 | } | ||
| 44 | |||
| 45 | err = clk_prepare(clk); | 41 | err = clk_prepare(clk); |
| 46 | if (err) { | 42 | if (err) { |
| 47 | pr_err("sp804: %s clock failed to prepare: %d\n", name, err); | 43 | pr_err("sp804: clock failed to prepare: %d\n", err); |
| 48 | clk_put(clk); | 44 | clk_put(clk); |
| 49 | return err; | 45 | return err; |
| 50 | } | 46 | } |
| 51 | 47 | ||
| 52 | err = clk_enable(clk); | 48 | err = clk_enable(clk); |
| 53 | if (err) { | 49 | if (err) { |
| 54 | pr_err("sp804: %s clock failed to enable: %d\n", name, err); | 50 | pr_err("sp804: clock failed to enable: %d\n", err); |
| 55 | clk_unprepare(clk); | 51 | clk_unprepare(clk); |
| 56 | clk_put(clk); | 52 | clk_put(clk); |
| 57 | return err; | 53 | return err; |
| @@ -59,7 +55,7 @@ static long __init sp804_get_clock_rate(const char *name) | |||
| 59 | 55 | ||
| 60 | rate = clk_get_rate(clk); | 56 | rate = clk_get_rate(clk); |
| 61 | if (rate < 0) { | 57 | if (rate < 0) { |
| 62 | pr_err("sp804: %s clock failed to get rate: %ld\n", name, rate); | 58 | pr_err("sp804: clock failed to get rate: %ld\n", rate); |
| 63 | clk_disable(clk); | 59 | clk_disable(clk); |
| 64 | clk_unprepare(clk); | 60 | clk_unprepare(clk); |
| 65 | clk_put(clk); | 61 | clk_put(clk); |
| @@ -77,9 +73,21 @@ static u32 sp804_read(void) | |||
| 77 | 73 | ||
| 78 | void __init __sp804_clocksource_and_sched_clock_init(void __iomem *base, | 74 | void __init __sp804_clocksource_and_sched_clock_init(void __iomem *base, |
| 79 | const char *name, | 75 | const char *name, |
| 76 | struct clk *clk, | ||
| 80 | int use_sched_clock) | 77 | int use_sched_clock) |
| 81 | { | 78 | { |
| 82 | long rate = sp804_get_clock_rate(name); | 79 | long rate; |
| 80 | |||
| 81 | if (!clk) { | ||
| 82 | clk = clk_get_sys("sp804", name); | ||
| 83 | if (IS_ERR(clk)) { | ||
| 84 | pr_err("sp804: clock not found: %d\n", | ||
| 85 | (int)PTR_ERR(clk)); | ||
| 86 | return; | ||
| 87 | } | ||
| 88 | } | ||
| 89 | |||
| 90 | rate = sp804_get_clock_rate(clk); | ||
| 83 | 91 | ||
| 84 | if (rate < 0) | 92 | if (rate < 0) |
| 85 | return; | 93 | return; |
| @@ -171,12 +179,20 @@ static struct irqaction sp804_timer_irq = { | |||
| 171 | .dev_id = &sp804_clockevent, | 179 | .dev_id = &sp804_clockevent, |
| 172 | }; | 180 | }; |
| 173 | 181 | ||
| 174 | void __init sp804_clockevents_init(void __iomem *base, unsigned int irq, | 182 | void __init __sp804_clockevents_init(void __iomem *base, unsigned int irq, struct clk *clk, const char *name) |
| 175 | const char *name) | ||
| 176 | { | 183 | { |
| 177 | struct clock_event_device *evt = &sp804_clockevent; | 184 | struct clock_event_device *evt = &sp804_clockevent; |
| 178 | long rate = sp804_get_clock_rate(name); | 185 | long rate; |
| 179 | 186 | ||
| 187 | if (!clk) | ||
| 188 | clk = clk_get_sys("sp804", name); | ||
| 189 | if (IS_ERR(clk)) { | ||
| 190 | pr_err("sp804: %s clock not found: %d\n", name, | ||
| 191 | (int)PTR_ERR(clk)); | ||
| 192 | return; | ||
| 193 | } | ||
| 194 | |||
| 195 | rate = sp804_get_clock_rate(clk); | ||
| 180 | if (rate < 0) | 196 | if (rate < 0) |
| 181 | return; | 197 | return; |
| 182 | 198 | ||
| @@ -186,6 +202,98 @@ void __init sp804_clockevents_init(void __iomem *base, unsigned int irq, | |||
| 186 | evt->irq = irq; | 202 | evt->irq = irq; |
| 187 | evt->cpumask = cpu_possible_mask; | 203 | evt->cpumask = cpu_possible_mask; |
| 188 | 204 | ||
| 205 | writel(0, base + TIMER_CTRL); | ||
| 206 | |||
| 189 | setup_irq(irq, &sp804_timer_irq); | 207 | setup_irq(irq, &sp804_timer_irq); |
| 190 | clockevents_config_and_register(evt, rate, 0xf, 0xffffffff); | 208 | clockevents_config_and_register(evt, rate, 0xf, 0xffffffff); |
| 191 | } | 209 | } |
| 210 | |||
| 211 | static void __init sp804_of_init(struct device_node *np) | ||
| 212 | { | ||
| 213 | static bool initialized = false; | ||
| 214 | void __iomem *base; | ||
| 215 | int irq; | ||
| 216 | u32 irq_num = 0; | ||
| 217 | struct clk *clk1, *clk2; | ||
| 218 | const char *name = of_get_property(np, "compatible", NULL); | ||
| 219 | |||
| 220 | base = of_iomap(np, 0); | ||
| 221 | if (WARN_ON(!base)) | ||
| 222 | return; | ||
| 223 | |||
| 224 | /* Ensure timers are disabled */ | ||
| 225 | writel(0, base + TIMER_CTRL); | ||
| 226 | writel(0, base + TIMER_2_BASE + TIMER_CTRL); | ||
| 227 | |||
| 228 | if (initialized || !of_device_is_available(np)) | ||
| 229 | goto err; | ||
| 230 | |||
| 231 | clk1 = of_clk_get(np, 0); | ||
| 232 | if (IS_ERR(clk1)) | ||
| 233 | clk1 = NULL; | ||
| 234 | |||
| 235 | /* Get the 2nd clock if the timer has 2 timer clocks */ | ||
| 236 | if (of_count_phandle_with_args(np, "clocks", "#clock-cells") == 3) { | ||
| 237 | clk2 = of_clk_get(np, 1); | ||
| 238 | if (IS_ERR(clk2)) { | ||
| 239 | pr_err("sp804: %s clock not found: %d\n", np->name, | ||
| 240 | (int)PTR_ERR(clk2)); | ||
| 241 | goto err; | ||
| 242 | } | ||
| 243 | } else | ||
| 244 | clk2 = clk1; | ||
| 245 | |||
| 246 | irq = irq_of_parse_and_map(np, 0); | ||
| 247 | if (irq <= 0) | ||
| 248 | goto err; | ||
| 249 | |||
| 250 | of_property_read_u32(np, "arm,sp804-has-irq", &irq_num); | ||
| 251 | if (irq_num == 2) { | ||
| 252 | __sp804_clockevents_init(base + TIMER_2_BASE, irq, clk2, name); | ||
| 253 | __sp804_clocksource_and_sched_clock_init(base, name, clk1, 1); | ||
| 254 | } else { | ||
| 255 | __sp804_clockevents_init(base, irq, clk1 , name); | ||
| 256 | __sp804_clocksource_and_sched_clock_init(base + TIMER_2_BASE, | ||
| 257 | name, clk2, 1); | ||
| 258 | } | ||
| 259 | initialized = true; | ||
| 260 | |||
| 261 | return; | ||
| 262 | err: | ||
| 263 | iounmap(base); | ||
| 264 | } | ||
| 265 | CLOCKSOURCE_OF_DECLARE(sp804, "arm,sp804", sp804_of_init); | ||
| 266 | |||
| 267 | static void __init integrator_cp_of_init(struct device_node *np) | ||
| 268 | { | ||
| 269 | static int init_count = 0; | ||
| 270 | void __iomem *base; | ||
| 271 | int irq; | ||
| 272 | const char *name = of_get_property(np, "compatible", NULL); | ||
| 273 | |||
| 274 | base = of_iomap(np, 0); | ||
| 275 | if (WARN_ON(!base)) | ||
| 276 | return; | ||
| 277 | |||
| 278 | /* Ensure timer is disabled */ | ||
| 279 | writel(0, base + TIMER_CTRL); | ||
| 280 | |||
| 281 | if (init_count == 2 || !of_device_is_available(np)) | ||
| 282 | goto err; | ||
| 283 | |||
| 284 | if (!init_count) | ||
| 285 | sp804_clocksource_init(base, name); | ||
| 286 | else { | ||
| 287 | irq = irq_of_parse_and_map(np, 0); | ||
| 288 | if (irq <= 0) | ||
| 289 | goto err; | ||
| 290 | |||
| 291 | sp804_clockevents_init(base, irq, name); | ||
| 292 | } | ||
| 293 | |||
| 294 | init_count++; | ||
| 295 | return; | ||
| 296 | err: | ||
| 297 | iounmap(base); | ||
| 298 | } | ||
| 299 | CLOCKSOURCE_OF_DECLARE(intcp, "arm,integrator-cp-timer", integrator_cp_of_init); | ||
diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig index 1ea959019fcd..047f2a415309 100644 --- a/arch/arm/configs/at91_dt_defconfig +++ b/arch/arm/configs/at91_dt_defconfig | |||
| @@ -20,7 +20,7 @@ CONFIG_SOC_AT91SAM9263=y | |||
| 20 | CONFIG_SOC_AT91SAM9G45=y | 20 | CONFIG_SOC_AT91SAM9G45=y |
| 21 | CONFIG_SOC_AT91SAM9X5=y | 21 | CONFIG_SOC_AT91SAM9X5=y |
| 22 | CONFIG_SOC_AT91SAM9N12=y | 22 | CONFIG_SOC_AT91SAM9N12=y |
| 23 | CONFIG_MACH_AT91SAM_DT=y | 23 | CONFIG_MACH_AT91SAM9_DT=y |
| 24 | CONFIG_AT91_PROGRAMMABLE_CLOCKS=y | 24 | CONFIG_AT91_PROGRAMMABLE_CLOCKS=y |
| 25 | CONFIG_AT91_TIMER_HZ=128 | 25 | CONFIG_AT91_TIMER_HZ=128 |
| 26 | CONFIG_AEABI=y | 26 | CONFIG_AEABI=y |
diff --git a/arch/arm/configs/at91sam9260_defconfig b/arch/arm/configs/at91sam9260_defconfig index 0ea5d2c97fc4..05618eb694f8 100644 --- a/arch/arm/configs/at91sam9260_defconfig +++ b/arch/arm/configs/at91sam9260_defconfig | |||
| @@ -22,7 +22,7 @@ CONFIG_MACH_QIL_A9260=y | |||
| 22 | CONFIG_MACH_CPU9260=y | 22 | CONFIG_MACH_CPU9260=y |
| 23 | CONFIG_MACH_FLEXIBITY=y | 23 | CONFIG_MACH_FLEXIBITY=y |
| 24 | CONFIG_MACH_SNAPPER_9260=y | 24 | CONFIG_MACH_SNAPPER_9260=y |
| 25 | CONFIG_MACH_AT91SAM_DT=y | 25 | CONFIG_MACH_AT91SAM9_DT=y |
| 26 | CONFIG_AT91_PROGRAMMABLE_CLOCKS=y | 26 | CONFIG_AT91_PROGRAMMABLE_CLOCKS=y |
| 27 | # CONFIG_ARM_THUMB is not set | 27 | # CONFIG_ARM_THUMB is not set |
| 28 | CONFIG_ZBOOT_ROM_TEXT=0x0 | 28 | CONFIG_ZBOOT_ROM_TEXT=0x0 |
diff --git a/arch/arm/configs/at91sam9g20_defconfig b/arch/arm/configs/at91sam9g20_defconfig index 3b1881033ad8..892e8287ed73 100644 --- a/arch/arm/configs/at91sam9g20_defconfig +++ b/arch/arm/configs/at91sam9g20_defconfig | |||
| @@ -22,7 +22,7 @@ CONFIG_MACH_PCONTROL_G20=y | |||
| 22 | CONFIG_MACH_GSIA18S=y | 22 | CONFIG_MACH_GSIA18S=y |
| 23 | CONFIG_MACH_USB_A9G20=y | 23 | CONFIG_MACH_USB_A9G20=y |
| 24 | CONFIG_MACH_SNAPPER_9260=y | 24 | CONFIG_MACH_SNAPPER_9260=y |
| 25 | CONFIG_MACH_AT91SAM_DT=y | 25 | CONFIG_MACH_AT91SAM9_DT=y |
| 26 | CONFIG_AT91_PROGRAMMABLE_CLOCKS=y | 26 | CONFIG_AT91_PROGRAMMABLE_CLOCKS=y |
| 27 | # CONFIG_ARM_THUMB is not set | 27 | # CONFIG_ARM_THUMB is not set |
| 28 | CONFIG_AEABI=y | 28 | CONFIG_AEABI=y |
diff --git a/arch/arm/configs/at91sam9g45_defconfig b/arch/arm/configs/at91sam9g45_defconfig index 606d48f3b8f8..5f551b76cb65 100644 --- a/arch/arm/configs/at91sam9g45_defconfig +++ b/arch/arm/configs/at91sam9g45_defconfig | |||
| @@ -18,7 +18,7 @@ CONFIG_MODULE_UNLOAD=y | |||
| 18 | CONFIG_ARCH_AT91=y | 18 | CONFIG_ARCH_AT91=y |
| 19 | CONFIG_ARCH_AT91SAM9G45=y | 19 | CONFIG_ARCH_AT91SAM9G45=y |
| 20 | CONFIG_MACH_AT91SAM9M10G45EK=y | 20 | CONFIG_MACH_AT91SAM9M10G45EK=y |
| 21 | CONFIG_MACH_AT91SAM_DT=y | 21 | CONFIG_MACH_AT91SAM9_DT=y |
| 22 | CONFIG_AT91_PROGRAMMABLE_CLOCKS=y | 22 | CONFIG_AT91_PROGRAMMABLE_CLOCKS=y |
| 23 | CONFIG_AT91_SLOW_CLOCK=y | 23 | CONFIG_AT91_SLOW_CLOCK=y |
| 24 | CONFIG_AEABI=y | 24 | CONFIG_AEABI=y |
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index e31d442343c8..3bf0c543216a 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig | |||
| @@ -10,6 +10,10 @@ CONFIG_ARCH_SUNXI=y | |||
| 10 | # CONFIG_ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA is not set | 10 | # CONFIG_ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA is not set |
| 11 | CONFIG_ARCH_ZYNQ=y | 11 | CONFIG_ARCH_ZYNQ=y |
| 12 | CONFIG_ARM_ERRATA_754322=y | 12 | CONFIG_ARM_ERRATA_754322=y |
| 13 | CONFIG_PLAT_SPEAR=y | ||
| 14 | CONFIG_ARCH_SPEAR13XX=y | ||
| 15 | CONFIG_MACH_SPEAR1310=y | ||
| 16 | CONFIG_MACH_SPEAR1340=y | ||
| 13 | CONFIG_SMP=y | 17 | CONFIG_SMP=y |
| 14 | CONFIG_ARM_ARCH_TIMER=y | 18 | CONFIG_ARM_ARCH_TIMER=y |
| 15 | CONFIG_AEABI=y | 19 | CONFIG_AEABI=y |
| @@ -23,6 +27,7 @@ CONFIG_BLK_DEV_SD=y | |||
| 23 | CONFIG_ATA=y | 27 | CONFIG_ATA=y |
| 24 | CONFIG_SATA_HIGHBANK=y | 28 | CONFIG_SATA_HIGHBANK=y |
| 25 | CONFIG_SATA_MV=y | 29 | CONFIG_SATA_MV=y |
| 30 | CONFIG_SATA_AHCI_PLATFORM=y | ||
| 26 | CONFIG_NETDEVICES=y | 31 | CONFIG_NETDEVICES=y |
| 27 | CONFIG_NET_CALXEDA_XGMAC=y | 32 | CONFIG_NET_CALXEDA_XGMAC=y |
| 28 | CONFIG_SMSC911X=y | 33 | CONFIG_SMSC911X=y |
| @@ -31,6 +36,7 @@ CONFIG_SERIO_AMBAKMI=y | |||
| 31 | CONFIG_SERIAL_8250=y | 36 | CONFIG_SERIAL_8250=y |
| 32 | CONFIG_SERIAL_8250_CONSOLE=y | 37 | CONFIG_SERIAL_8250_CONSOLE=y |
| 33 | CONFIG_SERIAL_8250_DW=y | 38 | CONFIG_SERIAL_8250_DW=y |
| 39 | CONFIG_KEYBOARD_SPEAR=y | ||
| 34 | CONFIG_SERIAL_AMBA_PL011=y | 40 | CONFIG_SERIAL_AMBA_PL011=y |
| 35 | CONFIG_SERIAL_AMBA_PL011_CONSOLE=y | 41 | CONFIG_SERIAL_AMBA_PL011_CONSOLE=y |
| 36 | CONFIG_SERIAL_OF_PLATFORM=y | 42 | CONFIG_SERIAL_OF_PLATFORM=y |
| @@ -40,6 +46,7 @@ CONFIG_I2C=y | |||
| 40 | CONFIG_I2C_DESIGNWARE_PLATFORM=y | 46 | CONFIG_I2C_DESIGNWARE_PLATFORM=y |
| 41 | CONFIG_SPI=y | 47 | CONFIG_SPI=y |
| 42 | CONFIG_SPI_PL022=y | 48 | CONFIG_SPI_PL022=y |
| 49 | CONFIG_GPIO_PL061=y | ||
| 43 | CONFIG_FB=y | 50 | CONFIG_FB=y |
| 44 | CONFIG_FB_ARMCLCD=y | 51 | CONFIG_FB_ARMCLCD=y |
| 45 | CONFIG_FRAMEBUFFER_CONSOLE=y | 52 | CONFIG_FRAMEBUFFER_CONSOLE=y |
| @@ -50,6 +57,7 @@ CONFIG_MMC=y | |||
| 50 | CONFIG_MMC_ARMMMCI=y | 57 | CONFIG_MMC_ARMMMCI=y |
| 51 | CONFIG_MMC_SDHCI=y | 58 | CONFIG_MMC_SDHCI=y |
| 52 | CONFIG_MMC_SDHCI_PLTFM=y | 59 | CONFIG_MMC_SDHCI_PLTFM=y |
| 60 | CONFIG_MMC_SDHCI_SPEAR=y | ||
| 53 | CONFIG_EDAC=y | 61 | CONFIG_EDAC=y |
| 54 | CONFIG_EDAC_MM_EDAC=y | 62 | CONFIG_EDAC_MM_EDAC=y |
| 55 | CONFIG_EDAC_HIGHBANK_MC=y | 63 | CONFIG_EDAC_HIGHBANK_MC=y |
| @@ -58,3 +66,4 @@ CONFIG_RTC_CLASS=y | |||
| 58 | CONFIG_RTC_DRV_PL031=y | 66 | CONFIG_RTC_DRV_PL031=y |
| 59 | CONFIG_DMADEVICES=y | 67 | CONFIG_DMADEVICES=y |
| 60 | CONFIG_PL330_DMA=y | 68 | CONFIG_PL330_DMA=y |
| 69 | CONFIG_DW_DMAC=y | ||
diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig index bd07864f14a0..33903ca0d879 100644 --- a/arch/arm/configs/omap2plus_defconfig +++ b/arch/arm/configs/omap2plus_defconfig | |||
| @@ -93,6 +93,7 @@ CONFIG_BLK_DEV_RAM_SIZE=16384 | |||
| 93 | CONFIG_SENSORS_LIS3LV02D=m | 93 | CONFIG_SENSORS_LIS3LV02D=m |
| 94 | CONFIG_SENSORS_TSL2550=m | 94 | CONFIG_SENSORS_TSL2550=m |
| 95 | CONFIG_SENSORS_LIS3_I2C=m | 95 | CONFIG_SENSORS_LIS3_I2C=m |
| 96 | CONFIG_BMP085_I2C=m | ||
| 96 | CONFIG_SCSI=y | 97 | CONFIG_SCSI=y |
| 97 | CONFIG_BLK_DEV_SD=y | 98 | CONFIG_BLK_DEV_SD=y |
| 98 | CONFIG_SCSI_MULTI_LUN=y | 99 | CONFIG_SCSI_MULTI_LUN=y |
diff --git a/arch/arm/configs/sama5_defconfig b/arch/arm/configs/sama5_defconfig new file mode 100644 index 000000000000..4d0dc3c16063 --- /dev/null +++ b/arch/arm/configs/sama5_defconfig | |||
| @@ -0,0 +1,181 @@ | |||
| 1 | # CONFIG_LOCALVERSION_AUTO is not set | ||
| 2 | # CONFIG_SWAP is not set | ||
| 3 | CONFIG_SYSVIPC=y | ||
| 4 | CONFIG_IRQ_DOMAIN_DEBUG=y | ||
| 5 | CONFIG_LOG_BUF_SHIFT=14 | ||
| 6 | CONFIG_SYSFS_DEPRECATED=y | ||
| 7 | CONFIG_SYSFS_DEPRECATED_V2=y | ||
| 8 | CONFIG_BLK_DEV_INITRD=y | ||
| 9 | CONFIG_EMBEDDED=y | ||
| 10 | CONFIG_SLAB=y | ||
| 11 | CONFIG_MODULES=y | ||
| 12 | CONFIG_MODULE_FORCE_LOAD=y | ||
| 13 | CONFIG_MODULE_UNLOAD=y | ||
| 14 | CONFIG_MODULE_FORCE_UNLOAD=y | ||
| 15 | # CONFIG_LBDAF is not set | ||
| 16 | # CONFIG_BLK_DEV_BSG is not set | ||
| 17 | # CONFIG_IOSCHED_DEADLINE is not set | ||
| 18 | # CONFIG_IOSCHED_CFQ is not set | ||
| 19 | CONFIG_ARCH_AT91=y | ||
| 20 | CONFIG_SOC_SAM_V7=y | ||
| 21 | CONFIG_SOC_SAMA5D3=y | ||
| 22 | CONFIG_MACH_SAMA5_DT=y | ||
| 23 | CONFIG_AT91_PROGRAMMABLE_CLOCKS=y | ||
| 24 | CONFIG_AEABI=y | ||
| 25 | # CONFIG_OABI_COMPAT is not set | ||
| 26 | CONFIG_UACCESS_WITH_MEMCPY=y | ||
| 27 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
| 28 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
| 29 | CONFIG_CMDLINE="console=ttyS0,115200 initrd=0x21100000,25165824 root=/dev/ram0 rw" | ||
| 30 | CONFIG_AUTO_ZRELADDR=y | ||
| 31 | CONFIG_VFP=y | ||
| 32 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set | ||
| 33 | CONFIG_PM_RUNTIME=y | ||
| 34 | CONFIG_PM_DEBUG=y | ||
| 35 | CONFIG_PM_ADVANCED_DEBUG=y | ||
| 36 | CONFIG_NET=y | ||
| 37 | CONFIG_PACKET=y | ||
| 38 | CONFIG_UNIX=y | ||
| 39 | CONFIG_INET=y | ||
| 40 | CONFIG_IP_MULTICAST=y | ||
| 41 | CONFIG_IP_PNP=y | ||
| 42 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set | ||
| 43 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set | ||
| 44 | # CONFIG_INET_XFRM_MODE_BEET is not set | ||
| 45 | # CONFIG_INET_LRO is not set | ||
| 46 | # CONFIG_INET_DIAG is not set | ||
| 47 | CONFIG_IPV6=y | ||
| 48 | # CONFIG_INET6_XFRM_MODE_TRANSPORT is not set | ||
| 49 | # CONFIG_INET6_XFRM_MODE_TUNNEL is not set | ||
| 50 | # CONFIG_INET6_XFRM_MODE_BEET is not set | ||
| 51 | CONFIG_IPV6_SIT_6RD=y | ||
| 52 | CONFIG_CAN=y | ||
| 53 | CONFIG_CAN_AT91=y | ||
| 54 | CONFIG_CFG80211=y | ||
| 55 | CONFIG_MAC80211=y | ||
| 56 | CONFIG_MAC80211_LEDS=y | ||
| 57 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
| 58 | CONFIG_DEVTMPFS=y | ||
| 59 | CONFIG_DEVTMPFS_MOUNT=y | ||
| 60 | # CONFIG_STANDALONE is not set | ||
| 61 | # CONFIG_PREVENT_FIRMWARE_BUILD is not set | ||
| 62 | CONFIG_MTD=y | ||
| 63 | CONFIG_MTD_CMDLINE_PARTS=y | ||
| 64 | CONFIG_MTD_CHAR=y | ||
| 65 | CONFIG_MTD_BLOCK=y | ||
| 66 | CONFIG_MTD_CFI=y | ||
| 67 | CONFIG_MTD_M25P80=y | ||
| 68 | CONFIG_MTD_NAND=y | ||
| 69 | CONFIG_MTD_NAND_ATMEL=y | ||
| 70 | CONFIG_MTD_UBI=y | ||
| 71 | CONFIG_BLK_DEV_LOOP=y | ||
| 72 | CONFIG_BLK_DEV_RAM=y | ||
| 73 | CONFIG_BLK_DEV_RAM_COUNT=4 | ||
| 74 | CONFIG_BLK_DEV_RAM_SIZE=8192 | ||
| 75 | CONFIG_ATMEL_TCLIB=y | ||
| 76 | CONFIG_ATMEL_SSC=y | ||
| 77 | CONFIG_EEPROM_AT24=y | ||
| 78 | CONFIG_SCSI=y | ||
| 79 | CONFIG_BLK_DEV_SD=y | ||
| 80 | CONFIG_SCSI_MULTI_LUN=y | ||
| 81 | # CONFIG_SCSI_LOWLEVEL is not set | ||
| 82 | CONFIG_NETDEVICES=y | ||
| 83 | CONFIG_MII=y | ||
| 84 | CONFIG_MACB=y | ||
| 85 | # CONFIG_NET_VENDOR_BROADCOM is not set | ||
| 86 | # CONFIG_NET_VENDOR_CIRRUS is not set | ||
| 87 | # CONFIG_NET_VENDOR_FARADAY is not set | ||
| 88 | # CONFIG_NET_VENDOR_INTEL is not set | ||
| 89 | # CONFIG_NET_VENDOR_MARVELL is not set | ||
| 90 | # CONFIG_NET_VENDOR_MICREL is not set | ||
| 91 | # CONFIG_NET_VENDOR_MICROCHIP is not set | ||
| 92 | # CONFIG_NET_VENDOR_NATSEMI is not set | ||
| 93 | # CONFIG_NET_VENDOR_SEEQ is not set | ||
| 94 | # CONFIG_NET_VENDOR_SMSC is not set | ||
| 95 | # CONFIG_NET_VENDOR_STMICRO is not set | ||
| 96 | # CONFIG_NET_VENDOR_WIZNET is not set | ||
| 97 | CONFIG_MICREL_PHY=y | ||
| 98 | # CONFIG_WLAN is not set | ||
| 99 | # CONFIG_INPUT_MOUSEDEV is not set | ||
| 100 | CONFIG_INPUT_EVDEV=y | ||
| 101 | # CONFIG_KEYBOARD_ATKBD is not set | ||
| 102 | CONFIG_KEYBOARD_QT1070=y | ||
| 103 | CONFIG_KEYBOARD_GPIO=y | ||
| 104 | # CONFIG_INPUT_MOUSE is not set | ||
| 105 | CONFIG_INPUT_TOUCHSCREEN=y | ||
| 106 | CONFIG_TOUCHSCREEN_ATMEL_MXT=y | ||
| 107 | CONFIG_TOUCHSCREEN_ATMEL_TSADCC=y | ||
| 108 | # CONFIG_SERIO is not set | ||
| 109 | CONFIG_LEGACY_PTY_COUNT=4 | ||
| 110 | CONFIG_SERIAL_ATMEL=y | ||
| 111 | CONFIG_SERIAL_ATMEL_CONSOLE=y | ||
| 112 | CONFIG_HW_RANDOM=y | ||
| 113 | CONFIG_I2C=y | ||
| 114 | CONFIG_I2C_CHARDEV=y | ||
| 115 | CONFIG_I2C_AT91=y | ||
| 116 | CONFIG_I2C_GPIO=y | ||
| 117 | CONFIG_SPI=y | ||
| 118 | CONFIG_SPI_ATMEL=y | ||
| 119 | CONFIG_SPI_GPIO=y | ||
| 120 | CONFIG_GPIO_SYSFS=y | ||
| 121 | # CONFIG_HWMON is not set | ||
| 122 | CONFIG_SSB=m | ||
| 123 | CONFIG_FB=y | ||
| 124 | CONFIG_BACKLIGHT_LCD_SUPPORT=y | ||
| 125 | # CONFIG_LCD_CLASS_DEVICE is not set | ||
| 126 | CONFIG_BACKLIGHT_CLASS_DEVICE=y | ||
| 127 | # CONFIG_BACKLIGHT_GENERIC is not set | ||
| 128 | CONFIG_FRAMEBUFFER_CONSOLE=y | ||
| 129 | # CONFIG_HID_GENERIC is not set | ||
| 130 | CONFIG_USB=y | ||
| 131 | CONFIG_USB_ANNOUNCE_NEW_DEVICES=y | ||
| 132 | CONFIG_USB_EHCI_HCD=y | ||
| 133 | CONFIG_USB_OHCI_HCD=y | ||
| 134 | CONFIG_USB_ACM=y | ||
| 135 | CONFIG_USB_STORAGE=y | ||
| 136 | CONFIG_USB_GADGET=y | ||
| 137 | CONFIG_USB_AT91=y | ||
| 138 | CONFIG_USB_MASS_STORAGE=m | ||
| 139 | CONFIG_MMC=y | ||
| 140 | # CONFIG_MMC_BLOCK_BOUNCE is not set | ||
| 141 | CONFIG_MMC_ATMELMCI=y | ||
| 142 | CONFIG_NEW_LEDS=y | ||
| 143 | CONFIG_LEDS_CLASS=y | ||
| 144 | CONFIG_LEDS_GPIO=y | ||
| 145 | CONFIG_LEDS_TRIGGER_TIMER=y | ||
| 146 | CONFIG_LEDS_TRIGGER_HEARTBEAT=y | ||
| 147 | CONFIG_LEDS_TRIGGER_GPIO=y | ||
| 148 | CONFIG_RTC_CLASS=y | ||
| 149 | CONFIG_RTC_DRV_AT91RM9200=y | ||
| 150 | CONFIG_DMADEVICES=y | ||
| 151 | # CONFIG_IOMMU_SUPPORT is not set | ||
| 152 | CONFIG_IIO=y | ||
| 153 | CONFIG_AT91_ADC=y | ||
| 154 | CONFIG_EXT2_FS=y | ||
| 155 | CONFIG_FANOTIFY=y | ||
| 156 | CONFIG_VFAT_FS=y | ||
| 157 | CONFIG_TMPFS=y | ||
| 158 | CONFIG_JFFS2_FS=y | ||
| 159 | CONFIG_JFFS2_SUMMARY=y | ||
| 160 | CONFIG_UBIFS_FS=y | ||
| 161 | CONFIG_NFS_FS=y | ||
| 162 | CONFIG_ROOT_NFS=y | ||
| 163 | CONFIG_NLS_CODEPAGE_437=y | ||
| 164 | CONFIG_NLS_CODEPAGE_850=y | ||
| 165 | CONFIG_NLS_ISO8859_1=y | ||
| 166 | CONFIG_STRIP_ASM_SYMS=y | ||
| 167 | CONFIG_DEBUG_FS=y | ||
| 168 | # CONFIG_SCHED_DEBUG is not set | ||
| 169 | CONFIG_DEBUG_MEMORY_INIT=y | ||
| 170 | # CONFIG_FTRACE is not set | ||
| 171 | CONFIG_DEBUG_USER=y | ||
| 172 | CONFIG_DEBUG_LL=y | ||
| 173 | CONFIG_EARLY_PRINTK=y | ||
| 174 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | ||
| 175 | CONFIG_CRYPTO_USER_API_HASH=m | ||
| 176 | CONFIG_CRYPTO_USER_API_SKCIPHER=m | ||
| 177 | CONFIG_CRYPTO_DEV_ATMEL_AES=y | ||
| 178 | CONFIG_CRYPTO_DEV_ATMEL_TDES=y | ||
| 179 | CONFIG_CRYPTO_DEV_ATMEL_SHA=y | ||
| 180 | CONFIG_CRC_CCITT=m | ||
| 181 | CONFIG_CRC_ITU_T=m | ||
diff --git a/arch/arm/configs/spear3xx_defconfig b/arch/arm/configs/spear3xx_defconfig index 865980c5f212..7ff23a077f5d 100644 --- a/arch/arm/configs/spear3xx_defconfig +++ b/arch/arm/configs/spear3xx_defconfig | |||
| @@ -6,7 +6,9 @@ CONFIG_MODULES=y | |||
| 6 | CONFIG_MODULE_UNLOAD=y | 6 | CONFIG_MODULE_UNLOAD=y |
| 7 | CONFIG_MODVERSIONS=y | 7 | CONFIG_MODVERSIONS=y |
| 8 | CONFIG_PARTITION_ADVANCED=y | 8 | CONFIG_PARTITION_ADVANCED=y |
| 9 | # CONFIG_ARCH_MULTI_V7 is not set | ||
| 9 | CONFIG_PLAT_SPEAR=y | 10 | CONFIG_PLAT_SPEAR=y |
| 11 | CONFIG_ARCH_SPEAR3XX=y | ||
| 10 | CONFIG_MACH_SPEAR300=y | 12 | CONFIG_MACH_SPEAR300=y |
| 11 | CONFIG_MACH_SPEAR310=y | 13 | CONFIG_MACH_SPEAR310=y |
| 12 | CONFIG_MACH_SPEAR320=y | 14 | CONFIG_MACH_SPEAR320=y |
diff --git a/arch/arm/configs/spear6xx_defconfig b/arch/arm/configs/spear6xx_defconfig index a2a1265f86b6..7822980d7d55 100644 --- a/arch/arm/configs/spear6xx_defconfig +++ b/arch/arm/configs/spear6xx_defconfig | |||
| @@ -6,6 +6,7 @@ CONFIG_MODULES=y | |||
| 6 | CONFIG_MODULE_UNLOAD=y | 6 | CONFIG_MODULE_UNLOAD=y |
| 7 | CONFIG_MODVERSIONS=y | 7 | CONFIG_MODVERSIONS=y |
| 8 | CONFIG_PARTITION_ADVANCED=y | 8 | CONFIG_PARTITION_ADVANCED=y |
| 9 | # CONFIG_ARCH_MULTI_V7 is not set | ||
| 9 | CONFIG_PLAT_SPEAR=y | 10 | CONFIG_PLAT_SPEAR=y |
| 10 | CONFIG_ARCH_SPEAR6XX=y | 11 | CONFIG_ARCH_SPEAR6XX=y |
| 11 | CONFIG_BINFMT_MISC=y | 12 | CONFIG_BINFMT_MISC=y |
diff --git a/arch/arm/include/asm/arch_timer.h b/arch/arm/include/asm/arch_timer.h index 7ade91d8cc6f..7c1bfc0aea0c 100644 --- a/arch/arm/include/asm/arch_timer.h +++ b/arch/arm/include/asm/arch_timer.h | |||
| @@ -10,8 +10,7 @@ | |||
| 10 | #include <clocksource/arm_arch_timer.h> | 10 | #include <clocksource/arm_arch_timer.h> |
| 11 | 11 | ||
| 12 | #ifdef CONFIG_ARM_ARCH_TIMER | 12 | #ifdef CONFIG_ARM_ARCH_TIMER |
| 13 | int arch_timer_of_register(void); | 13 | int arch_timer_arch_init(void); |
| 14 | int arch_timer_sched_clock_init(void); | ||
| 15 | 14 | ||
| 16 | /* | 15 | /* |
| 17 | * These register accessors are marked inline so the compiler can | 16 | * These register accessors are marked inline so the compiler can |
| @@ -110,16 +109,6 @@ static inline void __cpuinit arch_counter_set_user_access(void) | |||
| 110 | 109 | ||
| 111 | asm volatile("mcr p15, 0, %0, c14, c1, 0" : : "r" (cntkctl)); | 110 | asm volatile("mcr p15, 0, %0, c14, c1, 0" : : "r" (cntkctl)); |
| 112 | } | 111 | } |
| 113 | #else | ||
| 114 | static inline int arch_timer_of_register(void) | ||
| 115 | { | ||
| 116 | return -ENXIO; | ||
| 117 | } | ||
| 118 | |||
| 119 | static inline int arch_timer_sched_clock_init(void) | ||
| 120 | { | ||
| 121 | return -ENXIO; | ||
| 122 | } | ||
| 123 | #endif | 112 | #endif |
| 124 | 113 | ||
| 125 | #endif | 114 | #endif |
diff --git a/arch/arm/include/asm/delay.h b/arch/arm/include/asm/delay.h index 720799fd3a81..dff714d886d5 100644 --- a/arch/arm/include/asm/delay.h +++ b/arch/arm/include/asm/delay.h | |||
| @@ -24,7 +24,7 @@ extern struct arm_delay_ops { | |||
| 24 | void (*delay)(unsigned long); | 24 | void (*delay)(unsigned long); |
| 25 | void (*const_udelay)(unsigned long); | 25 | void (*const_udelay)(unsigned long); |
| 26 | void (*udelay)(unsigned long); | 26 | void (*udelay)(unsigned long); |
| 27 | bool const_clock; | 27 | unsigned long ticks_per_jiffy; |
| 28 | } arm_delay_ops; | 28 | } arm_delay_ops; |
| 29 | 29 | ||
| 30 | #define __delay(n) arm_delay_ops.delay(n) | 30 | #define __delay(n) arm_delay_ops.delay(n) |
diff --git a/arch/arm/include/asm/hardware/timer-sp.h b/arch/arm/include/asm/hardware/timer-sp.h index 2dd9d3f83f29..bb28af7c32de 100644 --- a/arch/arm/include/asm/hardware/timer-sp.h +++ b/arch/arm/include/asm/hardware/timer-sp.h | |||
| @@ -1,15 +1,23 @@ | |||
| 1 | struct clk; | ||
| 2 | |||
| 1 | void __sp804_clocksource_and_sched_clock_init(void __iomem *, | 3 | void __sp804_clocksource_and_sched_clock_init(void __iomem *, |
| 2 | const char *, int); | 4 | const char *, struct clk *, int); |
| 5 | void __sp804_clockevents_init(void __iomem *, unsigned int, | ||
| 6 | struct clk *, const char *); | ||
| 3 | 7 | ||
| 4 | static inline void sp804_clocksource_init(void __iomem *base, const char *name) | 8 | static inline void sp804_clocksource_init(void __iomem *base, const char *name) |
| 5 | { | 9 | { |
| 6 | __sp804_clocksource_and_sched_clock_init(base, name, 0); | 10 | __sp804_clocksource_and_sched_clock_init(base, name, NULL, 0); |
| 7 | } | 11 | } |
| 8 | 12 | ||
| 9 | static inline void sp804_clocksource_and_sched_clock_init(void __iomem *base, | 13 | static inline void sp804_clocksource_and_sched_clock_init(void __iomem *base, |
| 10 | const char *name) | 14 | const char *name) |
| 11 | { | 15 | { |
| 12 | __sp804_clocksource_and_sched_clock_init(base, name, 1); | 16 | __sp804_clocksource_and_sched_clock_init(base, name, NULL, 1); |
| 13 | } | 17 | } |
| 14 | 18 | ||
| 15 | void sp804_clockevents_init(void __iomem *, unsigned int, const char *); | 19 | static inline void sp804_clockevents_init(void __iomem *base, unsigned int irq, const char *name) |
| 20 | { | ||
| 21 | __sp804_clockevents_init(base, irq, NULL, name); | ||
| 22 | |||
| 23 | } | ||
diff --git a/arch/arm/include/asm/highmem.h b/arch/arm/include/asm/highmem.h index 8c5e828f484d..91b99abe7a95 100644 --- a/arch/arm/include/asm/highmem.h +++ b/arch/arm/include/asm/highmem.h | |||
| @@ -41,6 +41,13 @@ extern void kunmap_high(struct page *page); | |||
| 41 | #endif | 41 | #endif |
| 42 | #endif | 42 | #endif |
| 43 | 43 | ||
| 44 | /* | ||
| 45 | * Needed to be able to broadcast the TLB invalidation for kmap. | ||
| 46 | */ | ||
| 47 | #ifdef CONFIG_ARM_ERRATA_798181 | ||
| 48 | #undef ARCH_NEEDS_KMAP_HIGH_GET | ||
| 49 | #endif | ||
| 50 | |||
| 44 | #ifdef ARCH_NEEDS_KMAP_HIGH_GET | 51 | #ifdef ARCH_NEEDS_KMAP_HIGH_GET |
| 45 | extern void *kmap_high_get(struct page *page); | 52 | extern void *kmap_high_get(struct page *page); |
| 46 | #else | 53 | #else |
diff --git a/arch/arm/include/asm/mmu_context.h b/arch/arm/include/asm/mmu_context.h index 863a6611323c..a7b85e0d0cc1 100644 --- a/arch/arm/include/asm/mmu_context.h +++ b/arch/arm/include/asm/mmu_context.h | |||
| @@ -27,6 +27,8 @@ void __check_vmalloc_seq(struct mm_struct *mm); | |||
| 27 | void check_and_switch_context(struct mm_struct *mm, struct task_struct *tsk); | 27 | void check_and_switch_context(struct mm_struct *mm, struct task_struct *tsk); |
| 28 | #define init_new_context(tsk,mm) ({ atomic64_set(&mm->context.id, 0); 0; }) | 28 | #define init_new_context(tsk,mm) ({ atomic64_set(&mm->context.id, 0); 0; }) |
| 29 | 29 | ||
| 30 | DECLARE_PER_CPU(atomic64_t, active_asids); | ||
| 31 | |||
| 30 | #else /* !CONFIG_CPU_HAS_ASID */ | 32 | #else /* !CONFIG_CPU_HAS_ASID */ |
| 31 | 33 | ||
| 32 | #ifdef CONFIG_MMU | 34 | #ifdef CONFIG_MMU |
diff --git a/arch/arm/include/asm/sched_clock.h b/arch/arm/include/asm/sched_clock.h index e3f757263438..3d520ddca61b 100644 --- a/arch/arm/include/asm/sched_clock.h +++ b/arch/arm/include/asm/sched_clock.h | |||
| @@ -11,4 +11,6 @@ | |||
| 11 | extern void sched_clock_postinit(void); | 11 | extern void sched_clock_postinit(void); |
| 12 | extern void setup_sched_clock(u32 (*read)(void), int bits, unsigned long rate); | 12 | extern void setup_sched_clock(u32 (*read)(void), int bits, unsigned long rate); |
| 13 | 13 | ||
| 14 | extern unsigned long long (*sched_clock_func)(void); | ||
| 15 | |||
| 14 | #endif | 16 | #endif |
diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h index 4db8c8820f0d..9e9c041358ca 100644 --- a/arch/arm/include/asm/tlbflush.h +++ b/arch/arm/include/asm/tlbflush.h | |||
| @@ -450,6 +450,21 @@ static inline void local_flush_bp_all(void) | |||
| 450 | isb(); | 450 | isb(); |
| 451 | } | 451 | } |
| 452 | 452 | ||
| 453 | #ifdef CONFIG_ARM_ERRATA_798181 | ||
| 454 | static inline void dummy_flush_tlb_a15_erratum(void) | ||
| 455 | { | ||
| 456 | /* | ||
| 457 | * Dummy TLBIMVAIS. Using the unmapped address 0 and ASID 0. | ||
| 458 | */ | ||
| 459 | asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (0)); | ||
| 460 | dsb(); | ||
| 461 | } | ||
| 462 | #else | ||
| 463 | static inline void dummy_flush_tlb_a15_erratum(void) | ||
| 464 | { | ||
| 465 | } | ||
| 466 | #endif | ||
| 467 | |||
| 453 | /* | 468 | /* |
| 454 | * flush_pmd_entry | 469 | * flush_pmd_entry |
| 455 | * | 470 | * |
diff --git a/arch/arm/kernel/arch_timer.c b/arch/arm/kernel/arch_timer.c index d957a51435d8..59dcdced6e30 100644 --- a/arch/arm/kernel/arch_timer.c +++ b/arch/arm/kernel/arch_timer.c | |||
| @@ -22,9 +22,11 @@ static unsigned long arch_timer_read_counter_long(void) | |||
| 22 | return arch_timer_read_counter(); | 22 | return arch_timer_read_counter(); |
| 23 | } | 23 | } |
| 24 | 24 | ||
| 25 | static u32 arch_timer_read_counter_u32(void) | 25 | static u32 sched_clock_mult __read_mostly; |
| 26 | |||
| 27 | static unsigned long long notrace arch_timer_sched_clock(void) | ||
| 26 | { | 28 | { |
| 27 | return arch_timer_read_counter(); | 29 | return arch_timer_read_counter() * sched_clock_mult; |
| 28 | } | 30 | } |
| 29 | 31 | ||
| 30 | static struct delay_timer arch_delay_timer; | 32 | static struct delay_timer arch_delay_timer; |
| @@ -37,25 +39,20 @@ static void __init arch_timer_delay_timer_register(void) | |||
| 37 | register_current_timer_delay(&arch_delay_timer); | 39 | register_current_timer_delay(&arch_delay_timer); |
| 38 | } | 40 | } |
| 39 | 41 | ||
| 40 | int __init arch_timer_of_register(void) | 42 | int __init arch_timer_arch_init(void) |
| 41 | { | 43 | { |
| 42 | int ret; | 44 | u32 arch_timer_rate = arch_timer_get_rate(); |
| 43 | 45 | ||
| 44 | ret = arch_timer_init(); | 46 | if (arch_timer_rate == 0) |
| 45 | if (ret) | 47 | return -ENXIO; |
| 46 | return ret; | ||
| 47 | 48 | ||
| 48 | arch_timer_delay_timer_register(); | 49 | arch_timer_delay_timer_register(); |
| 49 | 50 | ||
| 50 | return 0; | 51 | /* Cache the sched_clock multiplier to save a divide in the hot path. */ |
| 51 | } | 52 | sched_clock_mult = NSEC_PER_SEC / arch_timer_rate; |
| 52 | 53 | sched_clock_func = arch_timer_sched_clock; | |
| 53 | int __init arch_timer_sched_clock_init(void) | 54 | pr_info("sched_clock: ARM arch timer >56 bits at %ukHz, resolution %uns\n", |
| 54 | { | 55 | arch_timer_rate / 1000, sched_clock_mult); |
| 55 | if (arch_timer_get_rate() == 0) | ||
| 56 | return -ENXIO; | ||
| 57 | 56 | ||
| 58 | setup_sched_clock(arch_timer_read_counter_u32, | ||
| 59 | 32, arch_timer_get_rate()); | ||
| 60 | return 0; | 57 | return 0; |
| 61 | } | 58 | } |
diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S index 3248cde504ed..fefd7f971437 100644 --- a/arch/arm/kernel/entry-common.S +++ b/arch/arm/kernel/entry-common.S | |||
| @@ -276,7 +276,13 @@ ENDPROC(ftrace_graph_caller_old) | |||
| 276 | */ | 276 | */ |
| 277 | 277 | ||
| 278 | .macro mcount_enter | 278 | .macro mcount_enter |
| 279 | /* | ||
| 280 | * This pad compensates for the push {lr} at the call site. Note that we are | ||
| 281 | * unable to unwind through a function which does not otherwise save its lr. | ||
| 282 | */ | ||
| 283 | UNWIND(.pad #4) | ||
| 279 | stmdb sp!, {r0-r3, lr} | 284 | stmdb sp!, {r0-r3, lr} |
| 285 | UNWIND(.save {r0-r3, lr}) | ||
| 280 | .endm | 286 | .endm |
| 281 | 287 | ||
| 282 | .macro mcount_get_lr reg | 288 | .macro mcount_get_lr reg |
| @@ -289,6 +295,7 @@ ENDPROC(ftrace_graph_caller_old) | |||
| 289 | .endm | 295 | .endm |
| 290 | 296 | ||
| 291 | ENTRY(__gnu_mcount_nc) | 297 | ENTRY(__gnu_mcount_nc) |
| 298 | UNWIND(.fnstart) | ||
| 292 | #ifdef CONFIG_DYNAMIC_FTRACE | 299 | #ifdef CONFIG_DYNAMIC_FTRACE |
| 293 | mov ip, lr | 300 | mov ip, lr |
| 294 | ldmia sp!, {lr} | 301 | ldmia sp!, {lr} |
| @@ -296,17 +303,22 @@ ENTRY(__gnu_mcount_nc) | |||
| 296 | #else | 303 | #else |
| 297 | __mcount | 304 | __mcount |
| 298 | #endif | 305 | #endif |
| 306 | UNWIND(.fnend) | ||
| 299 | ENDPROC(__gnu_mcount_nc) | 307 | ENDPROC(__gnu_mcount_nc) |
| 300 | 308 | ||
| 301 | #ifdef CONFIG_DYNAMIC_FTRACE | 309 | #ifdef CONFIG_DYNAMIC_FTRACE |
| 302 | ENTRY(ftrace_caller) | 310 | ENTRY(ftrace_caller) |
| 311 | UNWIND(.fnstart) | ||
| 303 | __ftrace_caller | 312 | __ftrace_caller |
| 313 | UNWIND(.fnend) | ||
| 304 | ENDPROC(ftrace_caller) | 314 | ENDPROC(ftrace_caller) |
| 305 | #endif | 315 | #endif |
| 306 | 316 | ||
| 307 | #ifdef CONFIG_FUNCTION_GRAPH_TRACER | 317 | #ifdef CONFIG_FUNCTION_GRAPH_TRACER |
| 308 | ENTRY(ftrace_graph_caller) | 318 | ENTRY(ftrace_graph_caller) |
| 319 | UNWIND(.fnstart) | ||
| 309 | __ftrace_graph_caller | 320 | __ftrace_graph_caller |
| 321 | UNWIND(.fnend) | ||
| 310 | ENDPROC(ftrace_graph_caller) | 322 | ENDPROC(ftrace_graph_caller) |
| 311 | #endif | 323 | #endif |
| 312 | 324 | ||
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S index e0eb9a1cae77..8bac553fe213 100644 --- a/arch/arm/kernel/head.S +++ b/arch/arm/kernel/head.S | |||
| @@ -267,7 +267,7 @@ __create_page_tables: | |||
| 267 | addne r6, r6, #1 << SECTION_SHIFT | 267 | addne r6, r6, #1 << SECTION_SHIFT |
| 268 | strne r6, [r3] | 268 | strne r6, [r3] |
| 269 | 269 | ||
| 270 | #if defined(CONFIG_LPAE) && defined(CONFIG_CPU_ENDIAN_BE8) | 270 | #if defined(CONFIG_ARM_LPAE) && defined(CONFIG_CPU_ENDIAN_BE8) |
| 271 | sub r4, r4, #4 @ Fixup page table pointer | 271 | sub r4, r4, #4 @ Fixup page table pointer |
| 272 | @ for 64-bit descriptors | 272 | @ for 64-bit descriptors |
| 273 | #endif | 273 | #endif |
diff --git a/arch/arm/kernel/hw_breakpoint.c b/arch/arm/kernel/hw_breakpoint.c index 96093b75ab90..5dc1aa6f0f7d 100644 --- a/arch/arm/kernel/hw_breakpoint.c +++ b/arch/arm/kernel/hw_breakpoint.c | |||
| @@ -966,7 +966,7 @@ static void reset_ctrl_regs(void *unused) | |||
| 966 | } | 966 | } |
| 967 | 967 | ||
| 968 | if (err) { | 968 | if (err) { |
| 969 | pr_warning("CPU %d debug is powered down!\n", cpu); | 969 | pr_warn_once("CPU %d debug is powered down!\n", cpu); |
| 970 | cpumask_or(&debug_err_mask, &debug_err_mask, cpumask_of(cpu)); | 970 | cpumask_or(&debug_err_mask, &debug_err_mask, cpumask_of(cpu)); |
| 971 | return; | 971 | return; |
| 972 | } | 972 | } |
| @@ -987,7 +987,7 @@ clear_vcr: | |||
| 987 | isb(); | 987 | isb(); |
| 988 | 988 | ||
| 989 | if (cpumask_intersects(&debug_err_mask, cpumask_of(cpu))) { | 989 | if (cpumask_intersects(&debug_err_mask, cpumask_of(cpu))) { |
| 990 | pr_warning("CPU %d failed to disable vector catch\n", cpu); | 990 | pr_warn_once("CPU %d failed to disable vector catch\n", cpu); |
| 991 | return; | 991 | return; |
| 992 | } | 992 | } |
| 993 | 993 | ||
| @@ -1007,7 +1007,7 @@ clear_vcr: | |||
| 1007 | } | 1007 | } |
| 1008 | 1008 | ||
| 1009 | if (cpumask_intersects(&debug_err_mask, cpumask_of(cpu))) { | 1009 | if (cpumask_intersects(&debug_err_mask, cpumask_of(cpu))) { |
| 1010 | pr_warning("CPU %d failed to clear debug register pairs\n", cpu); | 1010 | pr_warn_once("CPU %d failed to clear debug register pairs\n", cpu); |
| 1011 | return; | 1011 | return; |
| 1012 | } | 1012 | } |
| 1013 | 1013 | ||
diff --git a/arch/arm/kernel/sched_clock.c b/arch/arm/kernel/sched_clock.c index bd6f56b9ec21..880584852fca 100644 --- a/arch/arm/kernel/sched_clock.c +++ b/arch/arm/kernel/sched_clock.c | |||
| @@ -20,6 +20,7 @@ struct clock_data { | |||
| 20 | u64 epoch_ns; | 20 | u64 epoch_ns; |
| 21 | u32 epoch_cyc; | 21 | u32 epoch_cyc; |
| 22 | u32 epoch_cyc_copy; | 22 | u32 epoch_cyc_copy; |
| 23 | unsigned long rate; | ||
| 23 | u32 mult; | 24 | u32 mult; |
| 24 | u32 shift; | 25 | u32 shift; |
| 25 | bool suspended; | 26 | bool suspended; |
| @@ -113,11 +114,14 @@ void __init setup_sched_clock(u32 (*read)(void), int bits, unsigned long rate) | |||
| 113 | u64 res, wrap; | 114 | u64 res, wrap; |
| 114 | char r_unit; | 115 | char r_unit; |
| 115 | 116 | ||
| 117 | if (cd.rate > rate) | ||
| 118 | return; | ||
| 119 | |||
| 116 | BUG_ON(bits > 32); | 120 | BUG_ON(bits > 32); |
| 117 | WARN_ON(!irqs_disabled()); | 121 | WARN_ON(!irqs_disabled()); |
| 118 | WARN_ON(read_sched_clock != jiffy_sched_clock_read); | ||
| 119 | read_sched_clock = read; | 122 | read_sched_clock = read; |
| 120 | sched_clock_mask = (1 << bits) - 1; | 123 | sched_clock_mask = (1 << bits) - 1; |
| 124 | cd.rate = rate; | ||
| 121 | 125 | ||
| 122 | /* calculate the mult/shift to convert counter ticks to ns. */ | 126 | /* calculate the mult/shift to convert counter ticks to ns. */ |
| 123 | clocks_calc_mult_shift(&cd.mult, &cd.shift, rate, NSEC_PER_SEC, 0); | 127 | clocks_calc_mult_shift(&cd.mult, &cd.shift, rate, NSEC_PER_SEC, 0); |
| @@ -161,12 +165,19 @@ void __init setup_sched_clock(u32 (*read)(void), int bits, unsigned long rate) | |||
| 161 | pr_debug("Registered %pF as sched_clock source\n", read); | 165 | pr_debug("Registered %pF as sched_clock source\n", read); |
| 162 | } | 166 | } |
| 163 | 167 | ||
| 164 | unsigned long long notrace sched_clock(void) | 168 | static unsigned long long notrace sched_clock_32(void) |
| 165 | { | 169 | { |
| 166 | u32 cyc = read_sched_clock(); | 170 | u32 cyc = read_sched_clock(); |
| 167 | return cyc_to_sched_clock(cyc, sched_clock_mask); | 171 | return cyc_to_sched_clock(cyc, sched_clock_mask); |
| 168 | } | 172 | } |
| 169 | 173 | ||
| 174 | unsigned long long __read_mostly (*sched_clock_func)(void) = sched_clock_32; | ||
| 175 | |||
| 176 | unsigned long long notrace sched_clock(void) | ||
| 177 | { | ||
| 178 | return sched_clock_func(); | ||
| 179 | } | ||
| 180 | |||
| 170 | void __init sched_clock_postinit(void) | 181 | void __init sched_clock_postinit(void) |
| 171 | { | 182 | { |
| 172 | /* | 183 | /* |
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index 3f6cbb2e3eda..d343a6c3a6d1 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c | |||
| @@ -353,6 +353,23 @@ void __init early_print(const char *str, ...) | |||
| 353 | printk("%s", buf); | 353 | printk("%s", buf); |
| 354 | } | 354 | } |
| 355 | 355 | ||
| 356 | static void __init cpuid_init_hwcaps(void) | ||
| 357 | { | ||
| 358 | unsigned int divide_instrs; | ||
| 359 | |||
| 360 | if (cpu_architecture() < CPU_ARCH_ARMv7) | ||
| 361 | return; | ||
| 362 | |||
| 363 | divide_instrs = (read_cpuid_ext(CPUID_EXT_ISAR0) & 0x0f000000) >> 24; | ||
| 364 | |||
| 365 | switch (divide_instrs) { | ||
| 366 | case 2: | ||
| 367 | elf_hwcap |= HWCAP_IDIVA; | ||
| 368 | case 1: | ||
| 369 | elf_hwcap |= HWCAP_IDIVT; | ||
| 370 | } | ||
| 371 | } | ||
| 372 | |||
| 356 | static void __init feat_v6_fixup(void) | 373 | static void __init feat_v6_fixup(void) |
| 357 | { | 374 | { |
| 358 | int id = read_cpuid_id(); | 375 | int id = read_cpuid_id(); |
| @@ -483,8 +500,11 @@ static void __init setup_processor(void) | |||
| 483 | snprintf(elf_platform, ELF_PLATFORM_SIZE, "%s%c", | 500 | snprintf(elf_platform, ELF_PLATFORM_SIZE, "%s%c", |
| 484 | list->elf_name, ENDIANNESS); | 501 | list->elf_name, ENDIANNESS); |
| 485 | elf_hwcap = list->elf_hwcap; | 502 | elf_hwcap = list->elf_hwcap; |
| 503 | |||
| 504 | cpuid_init_hwcaps(); | ||
| 505 | |||
| 486 | #ifndef CONFIG_ARM_THUMB | 506 | #ifndef CONFIG_ARM_THUMB |
| 487 | elf_hwcap &= ~HWCAP_THUMB; | 507 | elf_hwcap &= ~(HWCAP_THUMB | HWCAP_IDIVT); |
| 488 | #endif | 508 | #endif |
| 489 | 509 | ||
| 490 | feat_v6_fixup(); | 510 | feat_v6_fixup(); |
| @@ -524,7 +544,7 @@ int __init arm_add_memory(phys_addr_t start, phys_addr_t size) | |||
| 524 | size -= start & ~PAGE_MASK; | 544 | size -= start & ~PAGE_MASK; |
| 525 | bank->start = PAGE_ALIGN(start); | 545 | bank->start = PAGE_ALIGN(start); |
| 526 | 546 | ||
| 527 | #ifndef CONFIG_LPAE | 547 | #ifndef CONFIG_ARM_LPAE |
| 528 | if (bank->start + size < bank->start) { | 548 | if (bank->start + size < bank->start) { |
| 529 | printk(KERN_CRIT "Truncating memory at 0x%08llx to fit in " | 549 | printk(KERN_CRIT "Truncating memory at 0x%08llx to fit in " |
| 530 | "32-bit physical address space\n", (long long)start); | 550 | "32-bit physical address space\n", (long long)start); |
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c index 79078edbb9bc..1f2ccccaf009 100644 --- a/arch/arm/kernel/smp.c +++ b/arch/arm/kernel/smp.c | |||
| @@ -673,9 +673,6 @@ static int cpufreq_callback(struct notifier_block *nb, | |||
| 673 | if (freq->flags & CPUFREQ_CONST_LOOPS) | 673 | if (freq->flags & CPUFREQ_CONST_LOOPS) |
| 674 | return NOTIFY_OK; | 674 | return NOTIFY_OK; |
| 675 | 675 | ||
| 676 | if (arm_delay_ops.const_clock) | ||
| 677 | return NOTIFY_OK; | ||
| 678 | |||
| 679 | if (!per_cpu(l_p_j_ref, cpu)) { | 676 | if (!per_cpu(l_p_j_ref, cpu)) { |
| 680 | per_cpu(l_p_j_ref, cpu) = | 677 | per_cpu(l_p_j_ref, cpu) = |
| 681 | per_cpu(cpu_data, cpu).loops_per_jiffy; | 678 | per_cpu(cpu_data, cpu).loops_per_jiffy; |
diff --git a/arch/arm/kernel/smp_tlb.c b/arch/arm/kernel/smp_tlb.c index bd0300531399..e82e1d248772 100644 --- a/arch/arm/kernel/smp_tlb.c +++ b/arch/arm/kernel/smp_tlb.c | |||
| @@ -12,6 +12,7 @@ | |||
| 12 | 12 | ||
| 13 | #include <asm/smp_plat.h> | 13 | #include <asm/smp_plat.h> |
| 14 | #include <asm/tlbflush.h> | 14 | #include <asm/tlbflush.h> |
| 15 | #include <asm/mmu_context.h> | ||
| 15 | 16 | ||
| 16 | /**********************************************************************/ | 17 | /**********************************************************************/ |
| 17 | 18 | ||
| @@ -69,12 +70,72 @@ static inline void ipi_flush_bp_all(void *ignored) | |||
| 69 | local_flush_bp_all(); | 70 | local_flush_bp_all(); |
| 70 | } | 71 | } |
| 71 | 72 | ||
| 73 | #ifdef CONFIG_ARM_ERRATA_798181 | ||
| 74 | static int erratum_a15_798181(void) | ||
| 75 | { | ||
| 76 | unsigned int midr = read_cpuid_id(); | ||
| 77 | |||
| 78 | /* Cortex-A15 r0p0..r3p2 affected */ | ||
| 79 | if ((midr & 0xff0ffff0) != 0x410fc0f0 || midr > 0x413fc0f2) | ||
| 80 | return 0; | ||
| 81 | return 1; | ||
| 82 | } | ||
| 83 | #else | ||
| 84 | static int erratum_a15_798181(void) | ||
| 85 | { | ||
| 86 | return 0; | ||
| 87 | } | ||
| 88 | #endif | ||
| 89 | |||
| 90 | static void ipi_flush_tlb_a15_erratum(void *arg) | ||
| 91 | { | ||
| 92 | dmb(); | ||
| 93 | } | ||
| 94 | |||
| 95 | static void broadcast_tlb_a15_erratum(void) | ||
| 96 | { | ||
| 97 | if (!erratum_a15_798181()) | ||
| 98 | return; | ||
| 99 | |||
| 100 | dummy_flush_tlb_a15_erratum(); | ||
| 101 | smp_call_function_many(cpu_online_mask, ipi_flush_tlb_a15_erratum, | ||
| 102 | NULL, 1); | ||
| 103 | } | ||
| 104 | |||
| 105 | static void broadcast_tlb_mm_a15_erratum(struct mm_struct *mm) | ||
| 106 | { | ||
| 107 | int cpu; | ||
| 108 | cpumask_t mask = { CPU_BITS_NONE }; | ||
| 109 | |||
| 110 | if (!erratum_a15_798181()) | ||
| 111 | return; | ||
| 112 | |||
| 113 | dummy_flush_tlb_a15_erratum(); | ||
| 114 | for_each_online_cpu(cpu) { | ||
| 115 | if (cpu == smp_processor_id()) | ||
| 116 | continue; | ||
| 117 | /* | ||
| 118 | * We only need to send an IPI if the other CPUs are running | ||
| 119 | * the same ASID as the one being invalidated. There is no | ||
| 120 | * need for locking around the active_asids check since the | ||
| 121 | * switch_mm() function has at least one dmb() (as required by | ||
| 122 | * this workaround) in case a context switch happens on | ||
| 123 | * another CPU after the condition below. | ||
| 124 | */ | ||
| 125 | if (atomic64_read(&mm->context.id) == | ||
| 126 | atomic64_read(&per_cpu(active_asids, cpu))) | ||
| 127 | cpumask_set_cpu(cpu, &mask); | ||
| 128 | } | ||
| 129 | smp_call_function_many(&mask, ipi_flush_tlb_a15_erratum, NULL, 1); | ||
| 130 | } | ||
| 131 | |||
| 72 | void flush_tlb_all(void) | 132 | void flush_tlb_all(void) |
| 73 | { | 133 | { |
| 74 | if (tlb_ops_need_broadcast()) | 134 | if (tlb_ops_need_broadcast()) |
| 75 | on_each_cpu(ipi_flush_tlb_all, NULL, 1); | 135 | on_each_cpu(ipi_flush_tlb_all, NULL, 1); |
| 76 | else | 136 | else |
| 77 | local_flush_tlb_all(); | 137 | local_flush_tlb_all(); |
| 138 | broadcast_tlb_a15_erratum(); | ||
| 78 | } | 139 | } |
| 79 | 140 | ||
| 80 | void flush_tlb_mm(struct mm_struct *mm) | 141 | void flush_tlb_mm(struct mm_struct *mm) |
| @@ -83,6 +144,7 @@ void flush_tlb_mm(struct mm_struct *mm) | |||
| 83 | on_each_cpu_mask(mm_cpumask(mm), ipi_flush_tlb_mm, mm, 1); | 144 | on_each_cpu_mask(mm_cpumask(mm), ipi_flush_tlb_mm, mm, 1); |
| 84 | else | 145 | else |
| 85 | local_flush_tlb_mm(mm); | 146 | local_flush_tlb_mm(mm); |
| 147 | broadcast_tlb_mm_a15_erratum(mm); | ||
| 86 | } | 148 | } |
| 87 | 149 | ||
| 88 | void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr) | 150 | void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr) |
| @@ -95,6 +157,7 @@ void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr) | |||
| 95 | &ta, 1); | 157 | &ta, 1); |
| 96 | } else | 158 | } else |
| 97 | local_flush_tlb_page(vma, uaddr); | 159 | local_flush_tlb_page(vma, uaddr); |
| 160 | broadcast_tlb_mm_a15_erratum(vma->vm_mm); | ||
| 98 | } | 161 | } |
| 99 | 162 | ||
| 100 | void flush_tlb_kernel_page(unsigned long kaddr) | 163 | void flush_tlb_kernel_page(unsigned long kaddr) |
| @@ -105,6 +168,7 @@ void flush_tlb_kernel_page(unsigned long kaddr) | |||
| 105 | on_each_cpu(ipi_flush_tlb_kernel_page, &ta, 1); | 168 | on_each_cpu(ipi_flush_tlb_kernel_page, &ta, 1); |
| 106 | } else | 169 | } else |
| 107 | local_flush_tlb_kernel_page(kaddr); | 170 | local_flush_tlb_kernel_page(kaddr); |
| 171 | broadcast_tlb_a15_erratum(); | ||
| 108 | } | 172 | } |
| 109 | 173 | ||
| 110 | void flush_tlb_range(struct vm_area_struct *vma, | 174 | void flush_tlb_range(struct vm_area_struct *vma, |
| @@ -119,6 +183,7 @@ void flush_tlb_range(struct vm_area_struct *vma, | |||
| 119 | &ta, 1); | 183 | &ta, 1); |
| 120 | } else | 184 | } else |
| 121 | local_flush_tlb_range(vma, start, end); | 185 | local_flush_tlb_range(vma, start, end); |
| 186 | broadcast_tlb_mm_a15_erratum(vma->vm_mm); | ||
| 122 | } | 187 | } |
| 123 | 188 | ||
| 124 | void flush_tlb_kernel_range(unsigned long start, unsigned long end) | 189 | void flush_tlb_kernel_range(unsigned long start, unsigned long end) |
| @@ -130,6 +195,7 @@ void flush_tlb_kernel_range(unsigned long start, unsigned long end) | |||
| 130 | on_each_cpu(ipi_flush_tlb_kernel_range, &ta, 1); | 195 | on_each_cpu(ipi_flush_tlb_kernel_range, &ta, 1); |
| 131 | } else | 196 | } else |
| 132 | local_flush_tlb_kernel_range(start, end); | 197 | local_flush_tlb_kernel_range(start, end); |
| 198 | broadcast_tlb_a15_erratum(); | ||
| 133 | } | 199 | } |
| 134 | 200 | ||
| 135 | void flush_bp_all(void) | 201 | void flush_bp_all(void) |
diff --git a/arch/arm/kernel/time.c b/arch/arm/kernel/time.c index 955d92d265e5..abff4e9aaee0 100644 --- a/arch/arm/kernel/time.c +++ b/arch/arm/kernel/time.c | |||
| @@ -22,6 +22,7 @@ | |||
| 22 | #include <linux/errno.h> | 22 | #include <linux/errno.h> |
| 23 | #include <linux/profile.h> | 23 | #include <linux/profile.h> |
| 24 | #include <linux/timer.h> | 24 | #include <linux/timer.h> |
| 25 | #include <linux/clocksource.h> | ||
| 25 | #include <linux/irq.h> | 26 | #include <linux/irq.h> |
| 26 | 27 | ||
| 27 | #include <asm/thread_info.h> | 28 | #include <asm/thread_info.h> |
| @@ -115,6 +116,10 @@ int __init register_persistent_clock(clock_access_fn read_boot, | |||
| 115 | 116 | ||
| 116 | void __init time_init(void) | 117 | void __init time_init(void) |
| 117 | { | 118 | { |
| 118 | machine_desc->init_time(); | 119 | if (machine_desc->init_time) |
| 120 | machine_desc->init_time(); | ||
| 121 | else | ||
| 122 | clocksource_of_init(); | ||
| 123 | |||
| 119 | sched_clock_postinit(); | 124 | sched_clock_postinit(); |
| 120 | } | 125 | } |
diff --git a/arch/arm/kvm/vgic.c b/arch/arm/kvm/vgic.c index c9a17316e9fe..0e4cfe123b38 100644 --- a/arch/arm/kvm/vgic.c +++ b/arch/arm/kvm/vgic.c | |||
| @@ -883,8 +883,7 @@ static bool vgic_queue_irq(struct kvm_vcpu *vcpu, u8 sgi_source_id, int irq) | |||
| 883 | lr, irq, vgic_cpu->vgic_lr[lr]); | 883 | lr, irq, vgic_cpu->vgic_lr[lr]); |
| 884 | BUG_ON(!test_bit(lr, vgic_cpu->lr_used)); | 884 | BUG_ON(!test_bit(lr, vgic_cpu->lr_used)); |
| 885 | vgic_cpu->vgic_lr[lr] |= GICH_LR_PENDING_BIT; | 885 | vgic_cpu->vgic_lr[lr] |= GICH_LR_PENDING_BIT; |
| 886 | 886 | return true; | |
| 887 | goto out; | ||
| 888 | } | 887 | } |
| 889 | 888 | ||
| 890 | /* Try to use another LR for this interrupt */ | 889 | /* Try to use another LR for this interrupt */ |
| @@ -898,7 +897,6 @@ static bool vgic_queue_irq(struct kvm_vcpu *vcpu, u8 sgi_source_id, int irq) | |||
| 898 | vgic_cpu->vgic_irq_lr_map[irq] = lr; | 897 | vgic_cpu->vgic_irq_lr_map[irq] = lr; |
| 899 | set_bit(lr, vgic_cpu->lr_used); | 898 | set_bit(lr, vgic_cpu->lr_used); |
| 900 | 899 | ||
| 901 | out: | ||
| 902 | if (!vgic_irq_is_edge(vcpu, irq)) | 900 | if (!vgic_irq_is_edge(vcpu, irq)) |
| 903 | vgic_cpu->vgic_lr[lr] |= GICH_LR_EOI; | 901 | vgic_cpu->vgic_lr[lr] |= GICH_LR_EOI; |
| 904 | 902 | ||
| @@ -1018,21 +1016,6 @@ static bool vgic_process_maintenance(struct kvm_vcpu *vcpu) | |||
| 1018 | 1016 | ||
| 1019 | kvm_debug("MISR = %08x\n", vgic_cpu->vgic_misr); | 1017 | kvm_debug("MISR = %08x\n", vgic_cpu->vgic_misr); |
| 1020 | 1018 | ||
| 1021 | /* | ||
| 1022 | * We do not need to take the distributor lock here, since the only | ||
| 1023 | * action we perform is clearing the irq_active_bit for an EOIed | ||
| 1024 | * level interrupt. There is a potential race with | ||
| 1025 | * the queuing of an interrupt in __kvm_vgic_flush_hwstate(), where we | ||
| 1026 | * check if the interrupt is already active. Two possibilities: | ||
| 1027 | * | ||
| 1028 | * - The queuing is occurring on the same vcpu: cannot happen, | ||
| 1029 | * as we're already in the context of this vcpu, and | ||
| 1030 | * executing the handler | ||
| 1031 | * - The interrupt has been migrated to another vcpu, and we | ||
| 1032 | * ignore this interrupt for this run. Big deal. It is still | ||
| 1033 | * pending though, and will get considered when this vcpu | ||
| 1034 | * exits. | ||
| 1035 | */ | ||
| 1036 | if (vgic_cpu->vgic_misr & GICH_MISR_EOI) { | 1019 | if (vgic_cpu->vgic_misr & GICH_MISR_EOI) { |
| 1037 | /* | 1020 | /* |
| 1038 | * Some level interrupts have been EOIed. Clear their | 1021 | * Some level interrupts have been EOIed. Clear their |
| @@ -1054,6 +1037,13 @@ static bool vgic_process_maintenance(struct kvm_vcpu *vcpu) | |||
| 1054 | } else { | 1037 | } else { |
| 1055 | vgic_cpu_irq_clear(vcpu, irq); | 1038 | vgic_cpu_irq_clear(vcpu, irq); |
| 1056 | } | 1039 | } |
| 1040 | |||
| 1041 | /* | ||
| 1042 | * Despite being EOIed, the LR may not have | ||
| 1043 | * been marked as empty. | ||
| 1044 | */ | ||
| 1045 | set_bit(lr, (unsigned long *)vgic_cpu->vgic_elrsr); | ||
| 1046 | vgic_cpu->vgic_lr[lr] &= ~GICH_LR_ACTIVE_BIT; | ||
| 1057 | } | 1047 | } |
| 1058 | } | 1048 | } |
| 1059 | 1049 | ||
| @@ -1064,9 +1054,8 @@ static bool vgic_process_maintenance(struct kvm_vcpu *vcpu) | |||
| 1064 | } | 1054 | } |
| 1065 | 1055 | ||
| 1066 | /* | 1056 | /* |
| 1067 | * Sync back the VGIC state after a guest run. We do not really touch | 1057 | * Sync back the VGIC state after a guest run. The distributor lock is |
| 1068 | * the distributor here (the irq_pending_on_cpu bit is safe to set), | 1058 | * needed so we don't get preempted in the middle of the state processing. |
| 1069 | * so there is no need for taking its lock. | ||
| 1070 | */ | 1059 | */ |
| 1071 | static void __kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu) | 1060 | static void __kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu) |
| 1072 | { | 1061 | { |
| @@ -1112,10 +1101,14 @@ void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu) | |||
| 1112 | 1101 | ||
| 1113 | void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu) | 1102 | void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu) |
| 1114 | { | 1103 | { |
| 1104 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | ||
| 1105 | |||
| 1115 | if (!irqchip_in_kernel(vcpu->kvm)) | 1106 | if (!irqchip_in_kernel(vcpu->kvm)) |
| 1116 | return; | 1107 | return; |
| 1117 | 1108 | ||
| 1109 | spin_lock(&dist->lock); | ||
| 1118 | __kvm_vgic_sync_hwstate(vcpu); | 1110 | __kvm_vgic_sync_hwstate(vcpu); |
| 1111 | spin_unlock(&dist->lock); | ||
| 1119 | } | 1112 | } |
| 1120 | 1113 | ||
| 1121 | int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu) | 1114 | int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu) |
diff --git a/arch/arm/lib/delay.c b/arch/arm/lib/delay.c index 6b93f6a1a3c7..64dbfa57204a 100644 --- a/arch/arm/lib/delay.c +++ b/arch/arm/lib/delay.c | |||
| @@ -58,7 +58,7 @@ static void __timer_delay(unsigned long cycles) | |||
| 58 | static void __timer_const_udelay(unsigned long xloops) | 58 | static void __timer_const_udelay(unsigned long xloops) |
| 59 | { | 59 | { |
| 60 | unsigned long long loops = xloops; | 60 | unsigned long long loops = xloops; |
| 61 | loops *= loops_per_jiffy; | 61 | loops *= arm_delay_ops.ticks_per_jiffy; |
| 62 | __timer_delay(loops >> UDELAY_SHIFT); | 62 | __timer_delay(loops >> UDELAY_SHIFT); |
| 63 | } | 63 | } |
| 64 | 64 | ||
| @@ -73,11 +73,13 @@ void __init register_current_timer_delay(const struct delay_timer *timer) | |||
| 73 | pr_info("Switching to timer-based delay loop\n"); | 73 | pr_info("Switching to timer-based delay loop\n"); |
| 74 | delay_timer = timer; | 74 | delay_timer = timer; |
| 75 | lpj_fine = timer->freq / HZ; | 75 | lpj_fine = timer->freq / HZ; |
| 76 | loops_per_jiffy = lpj_fine; | 76 | |
| 77 | /* cpufreq may scale loops_per_jiffy, so keep a private copy */ | ||
| 78 | arm_delay_ops.ticks_per_jiffy = lpj_fine; | ||
| 77 | arm_delay_ops.delay = __timer_delay; | 79 | arm_delay_ops.delay = __timer_delay; |
| 78 | arm_delay_ops.const_udelay = __timer_const_udelay; | 80 | arm_delay_ops.const_udelay = __timer_const_udelay; |
| 79 | arm_delay_ops.udelay = __timer_udelay; | 81 | arm_delay_ops.udelay = __timer_udelay; |
| 80 | arm_delay_ops.const_clock = true; | 82 | |
| 81 | delay_calibrated = true; | 83 | delay_calibrated = true; |
| 82 | } else { | 84 | } else { |
| 83 | pr_info("Ignoring duplicate/late registration of read_current_timer delay\n"); | 85 | pr_info("Ignoring duplicate/late registration of read_current_timer delay\n"); |
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 6071f4c3d654..02802386b894 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig | |||
| @@ -1,14 +1,15 @@ | |||
| 1 | if ARCH_AT91 | 1 | if ARCH_AT91 |
| 2 | 2 | ||
| 3 | config HAVE_AT91_DATAFLASH_CARD | ||
| 4 | bool | ||
| 5 | |||
| 6 | config HAVE_AT91_DBGU0 | 3 | config HAVE_AT91_DBGU0 |
| 7 | bool | 4 | bool |
| 8 | 5 | ||
| 9 | config HAVE_AT91_DBGU1 | 6 | config HAVE_AT91_DBGU1 |
| 10 | bool | 7 | bool |
| 11 | 8 | ||
| 9 | config AT91_PMC_UNIT | ||
| 10 | bool | ||
| 11 | default !ARCH_AT91X40 | ||
| 12 | |||
| 12 | config AT91_SAM9_ALT_RESET | 13 | config AT91_SAM9_ALT_RESET |
| 13 | bool | 14 | bool |
| 14 | default !ARCH_AT91X40 | 15 | default !ARCH_AT91X40 |
| @@ -17,17 +18,59 @@ config AT91_SAM9G45_RESET | |||
| 17 | bool | 18 | bool |
| 18 | default !ARCH_AT91X40 | 19 | default !ARCH_AT91X40 |
| 19 | 20 | ||
| 21 | config AT91_SAM9_TIME | ||
| 22 | bool | ||
| 23 | |||
| 20 | config SOC_AT91SAM9 | 24 | config SOC_AT91SAM9 |
| 21 | bool | 25 | bool |
| 26 | select AT91_SAM9_TIME | ||
| 22 | select CPU_ARM926T | 27 | select CPU_ARM926T |
| 23 | select GENERIC_CLOCKEVENTS | 28 | select GENERIC_CLOCKEVENTS |
| 24 | select MULTI_IRQ_HANDLER | 29 | select MULTI_IRQ_HANDLER |
| 25 | select SPARSE_IRQ | 30 | select SPARSE_IRQ |
| 26 | 31 | ||
| 32 | config SOC_SAMA5 | ||
| 33 | bool | ||
| 34 | select AT91_SAM9_TIME | ||
| 35 | select CPU_V7 | ||
| 36 | select GENERIC_CLOCKEVENTS | ||
| 37 | select MULTI_IRQ_HANDLER | ||
| 38 | select SPARSE_IRQ | ||
| 39 | |||
| 27 | menu "Atmel AT91 System-on-Chip" | 40 | menu "Atmel AT91 System-on-Chip" |
| 28 | 41 | ||
| 42 | choice | ||
| 43 | |||
| 44 | prompt "Core type" | ||
| 45 | |||
| 46 | config SOC_SAM_V4_V5 | ||
| 47 | bool "ARM7/ARM9" | ||
| 48 | help | ||
| 49 | Select this if you are using one of Atmel's AT91SAM9, AT91RM9200 | ||
| 50 | or AT91X40 SoC. | ||
| 51 | |||
| 52 | config SOC_SAM_V7 | ||
| 53 | bool "Cortex A5" | ||
| 54 | help | ||
| 55 | Select this if you are using one of Atmel's SAMA5D3 SoC. | ||
| 56 | |||
| 57 | endchoice | ||
| 58 | |||
| 29 | comment "Atmel AT91 Processor" | 59 | comment "Atmel AT91 Processor" |
| 30 | 60 | ||
| 61 | if SOC_SAM_V7 | ||
| 62 | config SOC_SAMA5D3 | ||
| 63 | bool "SAMA5D3 family" | ||
| 64 | depends on SOC_SAM_V7 | ||
| 65 | select SOC_SAMA5 | ||
| 66 | select HAVE_FB_ATMEL | ||
| 67 | select HAVE_AT91_DBGU1 | ||
| 68 | help | ||
| 69 | Select this if you are using one of Atmel's SAMA5D3 family SoC. | ||
| 70 | This support covers SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35. | ||
| 71 | endif | ||
| 72 | |||
| 73 | if SOC_SAM_V4_V5 | ||
| 31 | config SOC_AT91RM9200 | 74 | config SOC_AT91RM9200 |
| 32 | bool "AT91RM9200" | 75 | bool "AT91RM9200" |
| 33 | select CPU_ARM920T | 76 | select CPU_ARM920T |
| @@ -93,394 +136,10 @@ config SOC_AT91SAM9N12 | |||
| 93 | help | 136 | help |
| 94 | Select this if you are using Atmel's AT91SAM9N12 SoC. | 137 | Select this if you are using Atmel's AT91SAM9N12 SoC. |
| 95 | 138 | ||
| 96 | choice | ||
| 97 | prompt "Atmel AT91 Processor Devices for non DT boards" | ||
| 98 | |||
| 99 | config ARCH_AT91_NONE | ||
| 100 | bool "None" | ||
| 101 | |||
| 102 | config ARCH_AT91RM9200 | ||
| 103 | bool "AT91RM9200" | ||
| 104 | select SOC_AT91RM9200 | ||
| 105 | |||
| 106 | config ARCH_AT91SAM9260 | ||
| 107 | bool "AT91SAM9260 or AT91SAM9XE" | ||
| 108 | select SOC_AT91SAM9260 | ||
| 109 | |||
| 110 | config ARCH_AT91SAM9261 | ||
| 111 | bool "AT91SAM9261" | ||
| 112 | select SOC_AT91SAM9261 | ||
| 113 | |||
| 114 | config ARCH_AT91SAM9G10 | ||
| 115 | bool "AT91SAM9G10" | ||
| 116 | select SOC_AT91SAM9261 | ||
| 117 | |||
| 118 | config ARCH_AT91SAM9263 | ||
| 119 | bool "AT91SAM9263" | ||
| 120 | select SOC_AT91SAM9263 | ||
| 121 | |||
| 122 | config ARCH_AT91SAM9RL | ||
| 123 | bool "AT91SAM9RL" | ||
| 124 | select SOC_AT91SAM9RL | ||
| 125 | |||
| 126 | config ARCH_AT91SAM9G20 | ||
| 127 | bool "AT91SAM9G20" | ||
| 128 | select SOC_AT91SAM9260 | ||
| 129 | |||
| 130 | config ARCH_AT91SAM9G45 | ||
| 131 | bool "AT91SAM9G45" | ||
| 132 | select SOC_AT91SAM9G45 | ||
| 133 | |||
| 134 | config ARCH_AT91X40 | ||
| 135 | bool "AT91x40" | ||
| 136 | depends on !MMU | ||
| 137 | select ARCH_USES_GETTIMEOFFSET | ||
| 138 | select MULTI_IRQ_HANDLER | ||
| 139 | select SPARSE_IRQ | ||
| 140 | |||
| 141 | endchoice | ||
| 142 | |||
| 143 | config AT91_PMC_UNIT | ||
| 144 | bool | ||
| 145 | default !ARCH_AT91X40 | ||
| 146 | |||
| 147 | # ---------------------------------------------------------- | ||
| 148 | |||
| 149 | if ARCH_AT91RM9200 | ||
| 150 | |||
| 151 | comment "AT91RM9200 Board Type" | ||
| 152 | |||
| 153 | config MACH_ONEARM | ||
| 154 | bool "Ajeco 1ARM Single Board Computer" | ||
| 155 | help | ||
| 156 | Select this if you are using Ajeco's 1ARM Single Board Computer. | ||
| 157 | <http://www.ajeco.fi/> | ||
| 158 | |||
| 159 | config ARCH_AT91RM9200DK | ||
| 160 | bool "Atmel AT91RM9200-DK Development board" | ||
| 161 | select HAVE_AT91_DATAFLASH_CARD | ||
| 162 | help | ||
| 163 | Select this if you are using Atmel's AT91RM9200-DK Development board. | ||
| 164 | (Discontinued) | ||
| 165 | |||
| 166 | config MACH_AT91RM9200EK | ||
| 167 | bool "Atmel AT91RM9200-EK Evaluation Kit" | ||
| 168 | select HAVE_AT91_DATAFLASH_CARD | ||
| 169 | help | ||
| 170 | Select this if you are using Atmel's AT91RM9200-EK Evaluation Kit. | ||
| 171 | <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3507> | ||
| 172 | |||
| 173 | config MACH_CSB337 | ||
| 174 | bool "Cogent CSB337" | ||
| 175 | help | ||
| 176 | Select this if you are using Cogent's CSB337 board. | ||
| 177 | <http://www.cogcomp.com/csb_csb337.htm> | ||
| 178 | |||
| 179 | config MACH_CSB637 | ||
| 180 | bool "Cogent CSB637" | ||
| 181 | help | ||
| 182 | Select this if you are using Cogent's CSB637 board. | ||
| 183 | <http://www.cogcomp.com/csb_csb637.htm> | ||
| 184 | |||
| 185 | config MACH_CARMEVA | ||
| 186 | bool "Conitec ARM&EVA" | ||
| 187 | help | ||
| 188 | Select this if you are using Conitec's AT91RM9200-MCU-Module. | ||
| 189 | <http://www.conitec.net/english/linuxboard.php> | ||
| 190 | |||
| 191 | config MACH_ATEB9200 | ||
| 192 | bool "Embest ATEB9200" | ||
| 193 | help | ||
| 194 | Select this if you are using Embest's ATEB9200 board. | ||
| 195 | <http://www.embedinfo.com/english/product/ATEB9200.asp> | ||
| 196 | |||
| 197 | config MACH_KB9200 | ||
| 198 | bool "KwikByte KB920x" | ||
| 199 | help | ||
| 200 | Select this if you are using KwikByte's KB920x board. | ||
| 201 | <http://www.kwikbyte.com/KB9202.html> | ||
| 202 | |||
| 203 | config MACH_PICOTUX2XX | ||
| 204 | bool "picotux 200" | ||
| 205 | help | ||
| 206 | Select this if you are using a picotux 200. | ||
| 207 | <http://www.picotux.com/> | ||
| 208 | |||
| 209 | config MACH_KAFA | ||
| 210 | bool "Sperry-Sun KAFA board" | ||
| 211 | help | ||
| 212 | Select this if you are using Sperry-Sun's KAFA board. | ||
| 213 | |||
| 214 | config MACH_ECBAT91 | ||
| 215 | bool "emQbit ECB_AT91 SBC" | ||
| 216 | select HAVE_AT91_DATAFLASH_CARD | ||
| 217 | help | ||
| 218 | Select this if you are using emQbit's ECB_AT91 board. | ||
| 219 | <http://wiki.emqbit.com/free-ecb-at91> | ||
| 220 | |||
| 221 | config MACH_YL9200 | ||
| 222 | bool "ucDragon YL-9200" | ||
| 223 | help | ||
| 224 | Select this if you are using the ucDragon YL-9200 board. | ||
| 225 | |||
| 226 | config MACH_CPUAT91 | ||
| 227 | bool "Eukrea CPUAT91" | ||
| 228 | help | ||
| 229 | Select this if you are using the Eukrea Electromatique's | ||
| 230 | CPUAT91 board <http://www.eukrea.com/>. | ||
| 231 | |||
| 232 | config MACH_ECO920 | ||
| 233 | bool "eco920" | ||
| 234 | help | ||
| 235 | Select this if you are using the eco920 board | ||
| 236 | |||
| 237 | config MACH_RSI_EWS | ||
| 238 | bool "RSI Embedded Webserver" | ||
| 239 | depends on ARCH_AT91RM9200 | ||
| 240 | help | ||
| 241 | Select this if you are using RSIs EWS board. | ||
| 242 | endif | ||
| 243 | |||
| 244 | # ---------------------------------------------------------- | ||
| 245 | |||
| 246 | if ARCH_AT91SAM9260 | ||
| 247 | |||
| 248 | comment "AT91SAM9260 Variants" | ||
| 249 | |||
| 250 | comment "AT91SAM9260 / AT91SAM9XE Board Type" | ||
| 251 | |||
| 252 | config MACH_AT91SAM9260EK | ||
| 253 | bool "Atmel AT91SAM9260-EK / AT91SAM9XE Evaluation Kit" | ||
| 254 | select HAVE_AT91_DATAFLASH_CARD | ||
| 255 | help | ||
| 256 | Select this if you are using Atmel's AT91SAM9260-EK or AT91SAM9XE Evaluation Kit | ||
| 257 | <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3933> | ||
| 258 | |||
| 259 | config MACH_CAM60 | ||
| 260 | bool "KwikByte KB9260 (CAM60) board" | ||
| 261 | help | ||
| 262 | Select this if you are using KwikByte's KB9260 (CAM60) board based on the Atmel AT91SAM9260. | ||
| 263 | <http://www.kwikbyte.com/KB9260.html> | ||
| 264 | |||
| 265 | config MACH_SAM9_L9260 | ||
| 266 | bool "Olimex SAM9-L9260 board" | ||
| 267 | select HAVE_AT91_DATAFLASH_CARD | ||
| 268 | help | ||
| 269 | Select this if you are using Olimex's SAM9-L9260 board based on the Atmel AT91SAM9260. | ||
| 270 | <http://www.olimex.com/dev/sam9-L9260.html> | ||
| 271 | |||
| 272 | config MACH_AFEB9260 | ||
| 273 | bool "Custom afeb9260 board v1" | ||
| 274 | help | ||
| 275 | Select this if you are using custom afeb9260 board based on | ||
| 276 | open hardware design. Select this for revision 1 of the board. | ||
| 277 | <svn://194.85.238.22/home/users/george/svn/arm9eb> | ||
| 278 | <http://groups.google.com/group/arm9fpga-evolution-board> | ||
| 279 | |||
| 280 | config MACH_USB_A9260 | ||
| 281 | bool "CALAO USB-A9260" | ||
| 282 | help | ||
| 283 | Select this if you are using a Calao Systems USB-A9260. | ||
| 284 | <http://www.calao-systems.com> | ||
| 285 | |||
| 286 | config MACH_QIL_A9260 | ||
| 287 | bool "CALAO QIL-A9260 board" | ||
| 288 | help | ||
| 289 | Select this if you are using a Calao Systems QIL-A9260 Board. | ||
| 290 | <http://www.calao-systems.com> | ||
| 291 | |||
| 292 | config MACH_CPU9260 | ||
| 293 | bool "Eukrea CPU9260 board" | ||
| 294 | help | ||
| 295 | Select this if you are using a Eukrea Electromatique's | ||
| 296 | CPU9260 Board <http://www.eukrea.com/> | ||
| 297 | |||
| 298 | config MACH_FLEXIBITY | ||
| 299 | bool "Flexibity Connect board" | ||
| 300 | help | ||
| 301 | Select this if you are using Flexibity Connect board | ||
| 302 | <http://www.flexibity.com> | ||
| 303 | |||
| 304 | endif | ||
| 305 | |||
| 306 | # ---------------------------------------------------------- | ||
| 307 | |||
| 308 | if ARCH_AT91SAM9261 | ||
| 309 | |||
| 310 | comment "AT91SAM9261 Board Type" | ||
| 311 | |||
| 312 | config MACH_AT91SAM9261EK | ||
| 313 | bool "Atmel AT91SAM9261-EK Evaluation Kit" | ||
| 314 | select HAVE_AT91_DATAFLASH_CARD | ||
| 315 | help | ||
| 316 | Select this if you are using Atmel's AT91SAM9261-EK Evaluation Kit. | ||
| 317 | <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3820> | ||
| 318 | |||
| 319 | endif | ||
| 320 | |||
| 321 | # ---------------------------------------------------------- | ||
| 322 | |||
| 323 | if ARCH_AT91SAM9G10 | ||
| 324 | |||
| 325 | comment "AT91SAM9G10 Board Type" | ||
| 326 | |||
| 327 | config MACH_AT91SAM9G10EK | ||
| 328 | bool "Atmel AT91SAM9G10-EK Evaluation Kit" | ||
| 329 | select HAVE_AT91_DATAFLASH_CARD | ||
| 330 | help | ||
| 331 | Select this if you are using Atmel's AT91SAM9G10-EK Evaluation Kit. | ||
| 332 | <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4588> | ||
| 333 | |||
| 334 | endif | ||
| 335 | |||
| 336 | # ---------------------------------------------------------- | ||
| 337 | |||
| 338 | if ARCH_AT91SAM9263 | ||
| 339 | |||
| 340 | comment "AT91SAM9263 Board Type" | ||
| 341 | |||
| 342 | config MACH_AT91SAM9263EK | ||
| 343 | bool "Atmel AT91SAM9263-EK Evaluation Kit" | ||
| 344 | select HAVE_AT91_DATAFLASH_CARD | ||
| 345 | help | ||
| 346 | Select this if you are using Atmel's AT91SAM9263-EK Evaluation Kit. | ||
| 347 | <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4057> | ||
| 348 | |||
| 349 | config MACH_USB_A9263 | ||
| 350 | bool "CALAO USB-A9263" | ||
| 351 | help | ||
| 352 | Select this if you are using a Calao Systems USB-A9263. | ||
| 353 | <http://www.calao-systems.com> | ||
| 354 | |||
| 355 | endif | ||
| 356 | |||
| 357 | # ---------------------------------------------------------- | ||
| 358 | |||
| 359 | if ARCH_AT91SAM9RL | ||
| 360 | |||
| 361 | comment "AT91SAM9RL Board Type" | ||
| 362 | |||
| 363 | config MACH_AT91SAM9RLEK | ||
| 364 | bool "Atmel AT91SAM9RL-EK Evaluation Kit" | ||
| 365 | help | ||
| 366 | Select this if you are using Atmel's AT91SAM9RL-EK Evaluation Kit. | ||
| 367 | |||
| 368 | endif | ||
| 369 | |||
| 370 | # ---------------------------------------------------------- | 139 | # ---------------------------------------------------------- |
| 371 | 140 | ||
| 372 | if ARCH_AT91SAM9G20 | 141 | source arch/arm/mach-at91/Kconfig.non_dt |
| 373 | 142 | endif # SOC_SAM_V4_V5 | |
| 374 | comment "AT91SAM9G20 Board Type" | ||
| 375 | |||
| 376 | config MACH_AT91SAM9G20EK | ||
| 377 | bool "Atmel AT91SAM9G20-EK Evaluation Kit" | ||
| 378 | select HAVE_AT91_DATAFLASH_CARD | ||
| 379 | help | ||
| 380 | Select this if you are using Atmel's AT91SAM9G20-EK Evaluation Kit | ||
| 381 | that embeds only one SD/MMC slot. | ||
| 382 | |||
| 383 | config MACH_AT91SAM9G20EK_2MMC | ||
| 384 | depends on MACH_AT91SAM9G20EK | ||
| 385 | bool "Atmel AT91SAM9G20-EK Evaluation Kit with 2 SD/MMC Slots" | ||
| 386 | help | ||
| 387 | Select this if you are using an Atmel AT91SAM9G20-EK Evaluation Kit | ||
| 388 | with 2 SD/MMC Slots. This is the case for AT91SAM9G20-EK rev. C and | ||
| 389 | onwards. | ||
| 390 | <http://www.atmel.com/tools/SAM9G20-EK.aspx> | ||
| 391 | |||
| 392 | config MACH_CPU9G20 | ||
| 393 | bool "Eukrea CPU9G20 board" | ||
| 394 | help | ||
| 395 | Select this if you are using a Eukrea Electromatique's | ||
| 396 | CPU9G20 Board <http://www.eukrea.com/> | ||
| 397 | |||
| 398 | config MACH_ACMENETUSFOXG20 | ||
| 399 | bool "Acme Systems srl FOX Board G20" | ||
| 400 | help | ||
| 401 | Select this if you are using Acme Systems | ||
| 402 | FOX Board G20 <http://www.acmesystems.it> | ||
| 403 | |||
| 404 | config MACH_PORTUXG20 | ||
| 405 | bool "taskit PortuxG20" | ||
| 406 | help | ||
| 407 | Select this if you are using taskit's PortuxG20. | ||
| 408 | <http://www.taskit.de/en/> | ||
| 409 | |||
| 410 | config MACH_STAMP9G20 | ||
| 411 | bool "taskit Stamp9G20 CPU module" | ||
| 412 | help | ||
| 413 | Select this if you are using taskit's Stamp9G20 CPU module on its | ||
| 414 | evaluation board. | ||
| 415 | <http://www.taskit.de/en/> | ||
| 416 | |||
| 417 | config MACH_PCONTROL_G20 | ||
| 418 | bool "PControl G20 CPU module" | ||
| 419 | help | ||
| 420 | Select this if you are using taskit's Stamp9G20 CPU module on this | ||
| 421 | carrier board, beeing the decentralized unit of a building automation | ||
| 422 | system; featuring nvram, eth-switch, iso-rs485, display, io | ||
| 423 | |||
| 424 | config MACH_GSIA18S | ||
| 425 | bool "GS_IA18_S board" | ||
| 426 | help | ||
| 427 | This enables support for the GS_IA18_S board | ||
| 428 | produced by GeoSIG Ltd company. This is an internet accelerograph. | ||
| 429 | <http://www.geosig.com> | ||
| 430 | |||
| 431 | config MACH_USB_A9G20 | ||
| 432 | bool "CALAO USB-A9G20" | ||
| 433 | depends on ARCH_AT91SAM9G20 | ||
| 434 | help | ||
| 435 | Select this if you are using a Calao Systems USB-A9G20. | ||
| 436 | <http://www.calao-systems.com> | ||
| 437 | |||
| 438 | endif | ||
| 439 | |||
| 440 | if (ARCH_AT91SAM9260 || ARCH_AT91SAM9G20) | ||
| 441 | comment "AT91SAM9260/AT91SAM9G20 boards" | ||
| 442 | |||
| 443 | config MACH_SNAPPER_9260 | ||
| 444 | bool "Bluewater Systems Snapper 9260/9G20 module" | ||
| 445 | help | ||
| 446 | Select this if you are using the Bluewater Systems Snapper 9260 or | ||
| 447 | Snapper 9G20 modules. | ||
| 448 | <http://www.bluewatersys.com/> | ||
| 449 | endif | ||
| 450 | |||
| 451 | # ---------------------------------------------------------- | ||
| 452 | |||
| 453 | if ARCH_AT91SAM9G45 | ||
| 454 | |||
| 455 | comment "AT91SAM9G45 Board Type" | ||
| 456 | |||
| 457 | config MACH_AT91SAM9M10G45EK | ||
| 458 | bool "Atmel AT91SAM9M10G45-EK Evaluation Kits" | ||
| 459 | help | ||
| 460 | Select this if you are using Atmel's AT91SAM9M10G45-EK Evaluation Kit. | ||
| 461 | Those boards can be populated with any SoC of AT91SAM9G45 or AT91SAM9M10 | ||
| 462 | families: AT91SAM9G45, AT91SAM9G46, AT91SAM9M10 and AT91SAM9M11. | ||
| 463 | <http://www.atmel.com/tools/SAM9M10-G45-EK.aspx> | ||
| 464 | |||
| 465 | endif | ||
| 466 | |||
| 467 | # ---------------------------------------------------------- | ||
| 468 | |||
| 469 | if ARCH_AT91X40 | ||
| 470 | |||
| 471 | comment "AT91X40 Board Type" | ||
| 472 | |||
| 473 | config MACH_AT91EB01 | ||
| 474 | bool "Atmel AT91EB01 Evaluation Kit" | ||
| 475 | help | ||
| 476 | Select this if you are using Atmel's AT91EB01 Evaluation Kit. | ||
| 477 | It is also a popular target for simulators such as GDB's | ||
| 478 | ARM simulator (commonly known as the ARMulator) and the | ||
| 479 | Skyeye simulator. | ||
| 480 | |||
| 481 | endif | ||
| 482 | |||
| 483 | # ---------------------------------------------------------- | ||
| 484 | 143 | ||
| 485 | comment "Generic Board Type" | 144 | comment "Generic Board Type" |
| 486 | 145 | ||
| @@ -492,7 +151,7 @@ config MACH_AT91RM9200_DT | |||
| 492 | Select this if you want to experiment device-tree with | 151 | Select this if you want to experiment device-tree with |
| 493 | an Atmel RM9200 Evaluation Kit. | 152 | an Atmel RM9200 Evaluation Kit. |
| 494 | 153 | ||
| 495 | config MACH_AT91SAM_DT | 154 | config MACH_AT91SAM9_DT |
| 496 | bool "Atmel AT91SAM Evaluation Kits with device-tree support" | 155 | bool "Atmel AT91SAM Evaluation Kits with device-tree support" |
| 497 | depends on SOC_AT91SAM9 | 156 | depends on SOC_AT91SAM9 |
| 498 | select USE_OF | 157 | select USE_OF |
| @@ -500,15 +159,13 @@ config MACH_AT91SAM_DT | |||
| 500 | Select this if you want to experiment device-tree with | 159 | Select this if you want to experiment device-tree with |
| 501 | an Atmel Evaluation Kit. | 160 | an Atmel Evaluation Kit. |
| 502 | 161 | ||
| 503 | # ---------------------------------------------------------- | 162 | config MACH_SAMA5_DT |
| 504 | 163 | bool "Atmel SAMA5 Evaluation Kits with device-tree support" | |
| 505 | comment "AT91 Board Options" | 164 | depends on SOC_SAMA5 |
| 506 | 165 | select USE_OF | |
| 507 | config MTD_AT91_DATAFLASH_CARD | ||
| 508 | bool "Enable DataFlash Card support" | ||
| 509 | depends on HAVE_AT91_DATAFLASH_CARD | ||
| 510 | help | 166 | help |
| 511 | Enable support for the DataFlash card. | 167 | Select this if you want to experiment device-tree with |
| 168 | an Atmel Evaluation Kit. | ||
| 512 | 169 | ||
| 513 | # ---------------------------------------------------------- | 170 | # ---------------------------------------------------------- |
| 514 | 171 | ||
diff --git a/arch/arm/mach-at91/Kconfig.non_dt b/arch/arm/mach-at91/Kconfig.non_dt new file mode 100644 index 000000000000..6c24985515a2 --- /dev/null +++ b/arch/arm/mach-at91/Kconfig.non_dt | |||
| @@ -0,0 +1,399 @@ | |||
| 1 | menu "Atmel Non-DT world" | ||
| 2 | |||
| 3 | config HAVE_AT91_DATAFLASH_CARD | ||
| 4 | bool | ||
| 5 | |||
| 6 | choice | ||
| 7 | prompt "Atmel AT91 Processor Devices for non DT boards" | ||
| 8 | |||
| 9 | config ARCH_AT91_NONE | ||
| 10 | bool "None" | ||
| 11 | |||
| 12 | config ARCH_AT91RM9200 | ||
| 13 | bool "AT91RM9200" | ||
| 14 | select SOC_AT91RM9200 | ||
| 15 | |||
| 16 | config ARCH_AT91SAM9260 | ||
| 17 | bool "AT91SAM9260 or AT91SAM9XE" | ||
| 18 | select SOC_AT91SAM9260 | ||
| 19 | |||
| 20 | config ARCH_AT91SAM9261 | ||
| 21 | bool "AT91SAM9261" | ||
| 22 | select SOC_AT91SAM9261 | ||
| 23 | |||
| 24 | config ARCH_AT91SAM9G10 | ||
| 25 | bool "AT91SAM9G10" | ||
| 26 | select SOC_AT91SAM9261 | ||
| 27 | |||
| 28 | config ARCH_AT91SAM9263 | ||
| 29 | bool "AT91SAM9263" | ||
| 30 | select SOC_AT91SAM9263 | ||
| 31 | |||
| 32 | config ARCH_AT91SAM9RL | ||
| 33 | bool "AT91SAM9RL" | ||
| 34 | select SOC_AT91SAM9RL | ||
| 35 | |||
| 36 | config ARCH_AT91SAM9G20 | ||
| 37 | bool "AT91SAM9G20" | ||
| 38 | select SOC_AT91SAM9260 | ||
| 39 | |||
| 40 | config ARCH_AT91SAM9G45 | ||
| 41 | bool "AT91SAM9G45" | ||
| 42 | select SOC_AT91SAM9G45 | ||
| 43 | |||
| 44 | config ARCH_AT91X40 | ||
| 45 | bool "AT91x40" | ||
| 46 | depends on !MMU | ||
| 47 | select ARCH_USES_GETTIMEOFFSET | ||
| 48 | select MULTI_IRQ_HANDLER | ||
| 49 | select SPARSE_IRQ | ||
| 50 | |||
| 51 | endchoice | ||
| 52 | |||
| 53 | # ---------------------------------------------------------- | ||
| 54 | |||
| 55 | if ARCH_AT91RM9200 | ||
| 56 | |||
| 57 | comment "AT91RM9200 Board Type" | ||
| 58 | |||
| 59 | config MACH_ONEARM | ||
| 60 | bool "Ajeco 1ARM Single Board Computer" | ||
| 61 | help | ||
| 62 | Select this if you are using Ajeco's 1ARM Single Board Computer. | ||
| 63 | <http://www.ajeco.fi/> | ||
| 64 | |||
| 65 | config ARCH_AT91RM9200DK | ||
| 66 | bool "Atmel AT91RM9200-DK Development board" | ||
| 67 | select HAVE_AT91_DATAFLASH_CARD | ||
| 68 | help | ||
| 69 | Select this if you are using Atmel's AT91RM9200-DK Development board. | ||
| 70 | (Discontinued) | ||
| 71 | |||
| 72 | config MACH_AT91RM9200EK | ||
| 73 | bool "Atmel AT91RM9200-EK Evaluation Kit" | ||
| 74 | select HAVE_AT91_DATAFLASH_CARD | ||
| 75 | help | ||
| 76 | Select this if you are using Atmel's AT91RM9200-EK Evaluation Kit. | ||
| 77 | <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3507> | ||
| 78 | |||
| 79 | config MACH_CSB337 | ||
| 80 | bool "Cogent CSB337" | ||
| 81 | help | ||
| 82 | Select this if you are using Cogent's CSB337 board. | ||
| 83 | <http://www.cogcomp.com/csb_csb337.htm> | ||
| 84 | |||
| 85 | config MACH_CSB637 | ||
| 86 | bool "Cogent CSB637" | ||
| 87 | help | ||
| 88 | Select this if you are using Cogent's CSB637 board. | ||
| 89 | <http://www.cogcomp.com/csb_csb637.htm> | ||
| 90 | |||
| 91 | config MACH_CARMEVA | ||
| 92 | bool "Conitec ARM&EVA" | ||
| 93 | help | ||
| 94 | Select this if you are using Conitec's AT91RM9200-MCU-Module. | ||
| 95 | <http://www.conitec.net/english/linuxboard.php> | ||
| 96 | |||
| 97 | config MACH_ATEB9200 | ||
| 98 | bool "Embest ATEB9200" | ||
| 99 | help | ||
| 100 | Select this if you are using Embest's ATEB9200 board. | ||
| 101 | <http://www.embedinfo.com/english/product/ATEB9200.asp> | ||
| 102 | |||
| 103 | config MACH_KB9200 | ||
| 104 | bool "KwikByte KB920x" | ||
| 105 | help | ||
| 106 | Select this if you are using KwikByte's KB920x board. | ||
| 107 | <http://www.kwikbyte.com/KB9202.html> | ||
| 108 | |||
| 109 | config MACH_PICOTUX2XX | ||
| 110 | bool "picotux 200" | ||
| 111 | help | ||
| 112 | Select this if you are using a picotux 200. | ||
| 113 | <http://www.picotux.com/> | ||
| 114 | |||
| 115 | config MACH_KAFA | ||
| 116 | bool "Sperry-Sun KAFA board" | ||
| 117 | help | ||
| 118 | Select this if you are using Sperry-Sun's KAFA board. | ||
| 119 | |||
| 120 | config MACH_ECBAT91 | ||
| 121 | bool "emQbit ECB_AT91 SBC" | ||
| 122 | select HAVE_AT91_DATAFLASH_CARD | ||
| 123 | help | ||
| 124 | Select this if you are using emQbit's ECB_AT91 board. | ||
| 125 | <http://wiki.emqbit.com/free-ecb-at91> | ||
| 126 | |||
| 127 | config MACH_YL9200 | ||
| 128 | bool "ucDragon YL-9200" | ||
| 129 | help | ||
| 130 | Select this if you are using the ucDragon YL-9200 board. | ||
| 131 | |||
| 132 | config MACH_CPUAT91 | ||
| 133 | bool "Eukrea CPUAT91" | ||
| 134 | help | ||
| 135 | Select this if you are using the Eukrea Electromatique's | ||
| 136 | CPUAT91 board <http://www.eukrea.com/>. | ||
| 137 | |||
| 138 | config MACH_ECO920 | ||
| 139 | bool "eco920" | ||
| 140 | help | ||
| 141 | Select this if you are using the eco920 board | ||
| 142 | |||
| 143 | config MACH_RSI_EWS | ||
| 144 | bool "RSI Embedded Webserver" | ||
| 145 | depends on ARCH_AT91RM9200 | ||
| 146 | help | ||
| 147 | Select this if you are using RSIs EWS board. | ||
| 148 | endif | ||
| 149 | |||
| 150 | # ---------------------------------------------------------- | ||
| 151 | |||
| 152 | if ARCH_AT91SAM9260 | ||
| 153 | |||
| 154 | comment "AT91SAM9260 Variants" | ||
| 155 | |||
| 156 | comment "AT91SAM9260 / AT91SAM9XE Board Type" | ||
| 157 | |||
| 158 | config MACH_AT91SAM9260EK | ||
| 159 | bool "Atmel AT91SAM9260-EK / AT91SAM9XE Evaluation Kit" | ||
| 160 | select HAVE_AT91_DATAFLASH_CARD | ||
| 161 | help | ||
| 162 | Select this if you are using Atmel's AT91SAM9260-EK or AT91SAM9XE Evaluation Kit | ||
| 163 | <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3933> | ||
| 164 | |||
| 165 | config MACH_CAM60 | ||
| 166 | bool "KwikByte KB9260 (CAM60) board" | ||
| 167 | help | ||
| 168 | Select this if you are using KwikByte's KB9260 (CAM60) board based on the Atmel AT91SAM9260. | ||
| 169 | <http://www.kwikbyte.com/KB9260.html> | ||
| 170 | |||
| 171 | config MACH_SAM9_L9260 | ||
| 172 | bool "Olimex SAM9-L9260 board" | ||
| 173 | select HAVE_AT91_DATAFLASH_CARD | ||
| 174 | help | ||
| 175 | Select this if you are using Olimex's SAM9-L9260 board based on the Atmel AT91SAM9260. | ||
| 176 | <http://www.olimex.com/dev/sam9-L9260.html> | ||
| 177 | |||
| 178 | config MACH_AFEB9260 | ||
| 179 | bool "Custom afeb9260 board v1" | ||
| 180 | help | ||
| 181 | Select this if you are using custom afeb9260 board based on | ||
| 182 | open hardware design. Select this for revision 1 of the board. | ||
| 183 | <svn://194.85.238.22/home/users/george/svn/arm9eb> | ||
| 184 | <http://groups.google.com/group/arm9fpga-evolution-board> | ||
| 185 | |||
| 186 | config MACH_USB_A9260 | ||
| 187 | bool "CALAO USB-A9260" | ||
| 188 | help | ||
| 189 | Select this if you are using a Calao Systems USB-A9260. | ||
| 190 | <http://www.calao-systems.com> | ||
| 191 | |||
| 192 | config MACH_QIL_A9260 | ||
| 193 | bool "CALAO QIL-A9260 board" | ||
| 194 | help | ||
| 195 | Select this if you are using a Calao Systems QIL-A9260 Board. | ||
| 196 | <http://www.calao-systems.com> | ||
| 197 | |||
| 198 | config MACH_CPU9260 | ||
| 199 | bool "Eukrea CPU9260 board" | ||
| 200 | help | ||
| 201 | Select this if you are using a Eukrea Electromatique's | ||
| 202 | CPU9260 Board <http://www.eukrea.com/> | ||
| 203 | |||
| 204 | config MACH_FLEXIBITY | ||
| 205 | bool "Flexibity Connect board" | ||
| 206 | help | ||
| 207 | Select this if you are using Flexibity Connect board | ||
| 208 | <http://www.flexibity.com> | ||
| 209 | |||
| 210 | endif | ||
| 211 | |||
| 212 | # ---------------------------------------------------------- | ||
| 213 | |||
| 214 | if ARCH_AT91SAM9261 | ||
| 215 | |||
| 216 | comment "AT91SAM9261 Board Type" | ||
| 217 | |||
| 218 | config MACH_AT91SAM9261EK | ||
| 219 | bool "Atmel AT91SAM9261-EK Evaluation Kit" | ||
| 220 | select HAVE_AT91_DATAFLASH_CARD | ||
| 221 | help | ||
| 222 | Select this if you are using Atmel's AT91SAM9261-EK Evaluation Kit. | ||
| 223 | <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3820> | ||
| 224 | |||
| 225 | endif | ||
| 226 | |||
| 227 | # ---------------------------------------------------------- | ||
| 228 | |||
| 229 | if ARCH_AT91SAM9G10 | ||
| 230 | |||
| 231 | comment "AT91SAM9G10 Board Type" | ||
| 232 | |||
| 233 | config MACH_AT91SAM9G10EK | ||
| 234 | bool "Atmel AT91SAM9G10-EK Evaluation Kit" | ||
| 235 | select HAVE_AT91_DATAFLASH_CARD | ||
| 236 | help | ||
| 237 | Select this if you are using Atmel's AT91SAM9G10-EK Evaluation Kit. | ||
| 238 | <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4588> | ||
| 239 | |||
| 240 | endif | ||
| 241 | |||
| 242 | # ---------------------------------------------------------- | ||
| 243 | |||
| 244 | if ARCH_AT91SAM9263 | ||
| 245 | |||
| 246 | comment "AT91SAM9263 Board Type" | ||
| 247 | |||
| 248 | config MACH_AT91SAM9263EK | ||
| 249 | bool "Atmel AT91SAM9263-EK Evaluation Kit" | ||
| 250 | select HAVE_AT91_DATAFLASH_CARD | ||
| 251 | help | ||
| 252 | Select this if you are using Atmel's AT91SAM9263-EK Evaluation Kit. | ||
| 253 | <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4057> | ||
| 254 | |||
| 255 | config MACH_USB_A9263 | ||
| 256 | bool "CALAO USB-A9263" | ||
| 257 | help | ||
| 258 | Select this if you are using a Calao Systems USB-A9263. | ||
| 259 | <http://www.calao-systems.com> | ||
| 260 | |||
| 261 | endif | ||
| 262 | |||
| 263 | # ---------------------------------------------------------- | ||
| 264 | |||
| 265 | if ARCH_AT91SAM9RL | ||
| 266 | |||
| 267 | comment "AT91SAM9RL Board Type" | ||
| 268 | |||
| 269 | config MACH_AT91SAM9RLEK | ||
| 270 | bool "Atmel AT91SAM9RL-EK Evaluation Kit" | ||
| 271 | help | ||
| 272 | Select this if you are using Atmel's AT91SAM9RL-EK Evaluation Kit. | ||
| 273 | |||
| 274 | endif | ||
| 275 | |||
| 276 | # ---------------------------------------------------------- | ||
| 277 | |||
| 278 | if ARCH_AT91SAM9G20 | ||
| 279 | |||
| 280 | comment "AT91SAM9G20 Board Type" | ||
| 281 | |||
| 282 | config MACH_AT91SAM9G20EK | ||
| 283 | bool "Atmel AT91SAM9G20-EK Evaluation Kit" | ||
| 284 | select HAVE_AT91_DATAFLASH_CARD | ||
| 285 | help | ||
| 286 | Select this if you are using Atmel's AT91SAM9G20-EK Evaluation Kit | ||
| 287 | that embeds only one SD/MMC slot. | ||
| 288 | |||
| 289 | config MACH_AT91SAM9G20EK_2MMC | ||
| 290 | depends on MACH_AT91SAM9G20EK | ||
| 291 | bool "Atmel AT91SAM9G20-EK Evaluation Kit with 2 SD/MMC Slots" | ||
| 292 | help | ||
| 293 | Select this if you are using an Atmel AT91SAM9G20-EK Evaluation Kit | ||
| 294 | with 2 SD/MMC Slots. This is the case for AT91SAM9G20-EK rev. C and | ||
| 295 | onwards. | ||
| 296 | <http://www.atmel.com/tools/SAM9G20-EK.aspx> | ||
| 297 | |||
| 298 | config MACH_CPU9G20 | ||
| 299 | bool "Eukrea CPU9G20 board" | ||
| 300 | help | ||
| 301 | Select this if you are using a Eukrea Electromatique's | ||
| 302 | CPU9G20 Board <http://www.eukrea.com/> | ||
| 303 | |||
| 304 | config MACH_ACMENETUSFOXG20 | ||
| 305 | bool "Acme Systems srl FOX Board G20" | ||
| 306 | help | ||
| 307 | Select this if you are using Acme Systems | ||
| 308 | FOX Board G20 <http://www.acmesystems.it> | ||
| 309 | |||
| 310 | config MACH_PORTUXG20 | ||
| 311 | bool "taskit PortuxG20" | ||
| 312 | help | ||
| 313 | Select this if you are using taskit's PortuxG20. | ||
| 314 | <http://www.taskit.de/en/> | ||
| 315 | |||
| 316 | config MACH_STAMP9G20 | ||
| 317 | bool "taskit Stamp9G20 CPU module" | ||
| 318 | help | ||
| 319 | Select this if you are using taskit's Stamp9G20 CPU module on its | ||
| 320 | evaluation board. | ||
| 321 | <http://www.taskit.de/en/> | ||
| 322 | |||
| 323 | config MACH_PCONTROL_G20 | ||
| 324 | bool "PControl G20 CPU module" | ||
| 325 | help | ||
| 326 | Select this if you are using taskit's Stamp9G20 CPU module on this | ||
| 327 | carrier board, beeing the decentralized unit of a building automation | ||
| 328 | system; featuring nvram, eth-switch, iso-rs485, display, io | ||
| 329 | |||
| 330 | config MACH_GSIA18S | ||
| 331 | bool "GS_IA18_S board" | ||
| 332 | help | ||
| 333 | This enables support for the GS_IA18_S board | ||
| 334 | produced by GeoSIG Ltd company. This is an internet accelerograph. | ||
| 335 | <http://www.geosig.com> | ||
| 336 | |||
| 337 | config MACH_USB_A9G20 | ||
| 338 | bool "CALAO USB-A9G20" | ||
| 339 | depends on ARCH_AT91SAM9G20 | ||
| 340 | help | ||
| 341 | Select this if you are using a Calao Systems USB-A9G20. | ||
| 342 | <http://www.calao-systems.com> | ||
| 343 | |||
| 344 | endif | ||
| 345 | |||
| 346 | if (ARCH_AT91SAM9260 || ARCH_AT91SAM9G20) | ||
| 347 | comment "AT91SAM9260/AT91SAM9G20 boards" | ||
| 348 | |||
| 349 | config MACH_SNAPPER_9260 | ||
| 350 | bool "Bluewater Systems Snapper 9260/9G20 module" | ||
| 351 | help | ||
| 352 | Select this if you are using the Bluewater Systems Snapper 9260 or | ||
| 353 | Snapper 9G20 modules. | ||
| 354 | <http://www.bluewatersys.com/> | ||
| 355 | endif | ||
| 356 | |||
| 357 | # ---------------------------------------------------------- | ||
| 358 | |||
| 359 | if ARCH_AT91SAM9G45 | ||
| 360 | |||
| 361 | comment "AT91SAM9G45 Board Type" | ||
| 362 | |||
| 363 | config MACH_AT91SAM9M10G45EK | ||
| 364 | bool "Atmel AT91SAM9M10G45-EK Evaluation Kits" | ||
| 365 | help | ||
| 366 | Select this if you are using Atmel's AT91SAM9M10G45-EK Evaluation Kit. | ||
| 367 | Those boards can be populated with any SoC of AT91SAM9G45 or AT91SAM9M10 | ||
| 368 | families: AT91SAM9G45, AT91SAM9G46, AT91SAM9M10 and AT91SAM9M11. | ||
| 369 | <http://www.atmel.com/tools/SAM9M10-G45-EK.aspx> | ||
| 370 | |||
| 371 | endif | ||
| 372 | |||
| 373 | # ---------------------------------------------------------- | ||
| 374 | |||
| 375 | if ARCH_AT91X40 | ||
| 376 | |||
| 377 | comment "AT91X40 Board Type" | ||
| 378 | |||
| 379 | config MACH_AT91EB01 | ||
| 380 | bool "Atmel AT91EB01 Evaluation Kit" | ||
| 381 | help | ||
| 382 | Select this if you are using Atmel's AT91EB01 Evaluation Kit. | ||
| 383 | It is also a popular target for simulators such as GDB's | ||
| 384 | ARM simulator (commonly known as the ARMulator) and the | ||
| 385 | Skyeye simulator. | ||
| 386 | |||
| 387 | endif | ||
| 388 | |||
| 389 | # ---------------------------------------------------------- | ||
| 390 | |||
| 391 | comment "AT91 Board Options" | ||
| 392 | |||
| 393 | config MTD_AT91_DATAFLASH_CARD | ||
| 394 | bool "Enable DataFlash Card support" | ||
| 395 | depends on HAVE_AT91_DATAFLASH_CARD | ||
| 396 | help | ||
| 397 | Enable support for the DataFlash card. | ||
| 398 | |||
| 399 | endmenu | ||
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index 39218ca6d8e8..788562dccb43 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile | |||
| @@ -10,7 +10,8 @@ obj- := | |||
| 10 | obj-$(CONFIG_AT91_PMC_UNIT) += clock.o | 10 | obj-$(CONFIG_AT91_PMC_UNIT) += clock.o |
| 11 | obj-$(CONFIG_AT91_SAM9_ALT_RESET) += at91sam9_alt_reset.o | 11 | obj-$(CONFIG_AT91_SAM9_ALT_RESET) += at91sam9_alt_reset.o |
| 12 | obj-$(CONFIG_AT91_SAM9G45_RESET) += at91sam9g45_reset.o | 12 | obj-$(CONFIG_AT91_SAM9G45_RESET) += at91sam9g45_reset.o |
| 13 | obj-$(CONFIG_SOC_AT91SAM9) += at91sam926x_time.o sam9_smc.o | 13 | obj-$(CONFIG_AT91_SAM9_TIME) += at91sam926x_time.o |
| 14 | obj-$(CONFIG_SOC_AT91SAM9) += sam9_smc.o | ||
| 14 | 15 | ||
| 15 | # CPU-specific support | 16 | # CPU-specific support |
| 16 | obj-$(CONFIG_SOC_AT91RM9200) += at91rm9200.o at91rm9200_time.o | 17 | obj-$(CONFIG_SOC_AT91RM9200) += at91rm9200.o at91rm9200_time.o |
| @@ -21,6 +22,7 @@ obj-$(CONFIG_SOC_AT91SAM9G45) += at91sam9g45.o | |||
| 21 | obj-$(CONFIG_SOC_AT91SAM9N12) += at91sam9n12.o | 22 | obj-$(CONFIG_SOC_AT91SAM9N12) += at91sam9n12.o |
| 22 | obj-$(CONFIG_SOC_AT91SAM9X5) += at91sam9x5.o | 23 | obj-$(CONFIG_SOC_AT91SAM9X5) += at91sam9x5.o |
| 23 | obj-$(CONFIG_SOC_AT91SAM9RL) += at91sam9rl.o | 24 | obj-$(CONFIG_SOC_AT91SAM9RL) += at91sam9rl.o |
| 25 | obj-$(CONFIG_SOC_SAMA5D3) += sama5d3.o | ||
| 24 | 26 | ||
| 25 | obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200_devices.o | 27 | obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200_devices.o |
| 26 | obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260_devices.o | 28 | obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260_devices.o |
| @@ -87,8 +89,11 @@ obj-$(CONFIG_MACH_SNAPPER_9260) += board-snapper9260.o | |||
| 87 | obj-$(CONFIG_MACH_AT91SAM9M10G45EK) += board-sam9m10g45ek.o | 89 | obj-$(CONFIG_MACH_AT91SAM9M10G45EK) += board-sam9m10g45ek.o |
| 88 | 90 | ||
| 89 | # AT91SAM board with device-tree | 91 | # AT91SAM board with device-tree |
| 90 | obj-$(CONFIG_MACH_AT91RM9200_DT) += board-rm9200-dt.o | 92 | obj-$(CONFIG_MACH_AT91RM9200_DT) += board-dt-rm9200.o |
| 91 | obj-$(CONFIG_MACH_AT91SAM_DT) += board-dt.o | 93 | obj-$(CONFIG_MACH_AT91SAM9_DT) += board-dt-sam9.o |
| 94 | |||
| 95 | # SAMA5 board with device-tree | ||
| 96 | obj-$(CONFIG_MACH_SAMA5_DT) += board-dt-sama5.o | ||
| 92 | 97 | ||
| 93 | # AT91X40 board-specific support | 98 | # AT91X40 board-specific support |
| 94 | obj-$(CONFIG_MACH_AT91EB01) += board-eb01.o | 99 | obj-$(CONFIG_MACH_AT91EB01) += board-eb01.o |
diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c index 9706c000f294..ccce7592dbd3 100644 --- a/arch/arm/mach-at91/at91rm9200.c +++ b/arch/arm/mach-at91/at91rm9200.c | |||
| @@ -384,7 +384,7 @@ static unsigned int at91rm9200_default_irq_priority[NR_AIC_IRQS] __initdata = { | |||
| 384 | 0 /* Advanced Interrupt Controller (IRQ6) */ | 384 | 0 /* Advanced Interrupt Controller (IRQ6) */ |
| 385 | }; | 385 | }; |
| 386 | 386 | ||
| 387 | AT91_SOC_START(rm9200) | 387 | AT91_SOC_START(at91rm9200) |
| 388 | .map_io = at91rm9200_map_io, | 388 | .map_io = at91rm9200_map_io, |
| 389 | .default_irq_priority = at91rm9200_default_irq_priority, | 389 | .default_irq_priority = at91rm9200_default_irq_priority, |
| 390 | .ioremap_registers = at91rm9200_ioremap_registers, | 390 | .ioremap_registers = at91rm9200_ioremap_registers, |
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c index b67cd5374117..1833b4c365df 100644 --- a/arch/arm/mach-at91/at91sam9260.c +++ b/arch/arm/mach-at91/at91sam9260.c | |||
| @@ -395,7 +395,7 @@ static unsigned int at91sam9260_default_irq_priority[NR_AIC_IRQS] __initdata = { | |||
| 395 | 0, /* Advanced Interrupt Controller */ | 395 | 0, /* Advanced Interrupt Controller */ |
| 396 | }; | 396 | }; |
| 397 | 397 | ||
| 398 | AT91_SOC_START(sam9260) | 398 | AT91_SOC_START(at91sam9260) |
| 399 | .map_io = at91sam9260_map_io, | 399 | .map_io = at91sam9260_map_io, |
| 400 | .default_irq_priority = at91sam9260_default_irq_priority, | 400 | .default_irq_priority = at91sam9260_default_irq_priority, |
| 401 | .ioremap_registers = at91sam9260_ioremap_registers, | 401 | .ioremap_registers = at91sam9260_ioremap_registers, |
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c index 0204f4cc9ebf..25efb5ac30f1 100644 --- a/arch/arm/mach-at91/at91sam9261.c +++ b/arch/arm/mach-at91/at91sam9261.c | |||
| @@ -339,7 +339,7 @@ static unsigned int at91sam9261_default_irq_priority[NR_AIC_IRQS] __initdata = { | |||
| 339 | 0, /* Advanced Interrupt Controller */ | 339 | 0, /* Advanced Interrupt Controller */ |
| 340 | }; | 340 | }; |
| 341 | 341 | ||
| 342 | AT91_SOC_START(sam9261) | 342 | AT91_SOC_START(at91sam9261) |
| 343 | .map_io = at91sam9261_map_io, | 343 | .map_io = at91sam9261_map_io, |
| 344 | .default_irq_priority = at91sam9261_default_irq_priority, | 344 | .default_irq_priority = at91sam9261_default_irq_priority, |
| 345 | .ioremap_registers = at91sam9261_ioremap_registers, | 345 | .ioremap_registers = at91sam9261_ioremap_registers, |
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c index 2282fd7ad3e3..f44ffd2105a7 100644 --- a/arch/arm/mach-at91/at91sam9263.c +++ b/arch/arm/mach-at91/at91sam9263.c | |||
| @@ -375,7 +375,7 @@ static unsigned int at91sam9263_default_irq_priority[NR_AIC_IRQS] __initdata = { | |||
| 375 | 0, /* Advanced Interrupt Controller (IRQ1) */ | 375 | 0, /* Advanced Interrupt Controller (IRQ1) */ |
| 376 | }; | 376 | }; |
| 377 | 377 | ||
| 378 | AT91_SOC_START(sam9263) | 378 | AT91_SOC_START(at91sam9263) |
| 379 | .map_io = at91sam9263_map_io, | 379 | .map_io = at91sam9263_map_io, |
| 380 | .default_irq_priority = at91sam9263_default_irq_priority, | 380 | .default_irq_priority = at91sam9263_default_irq_priority, |
| 381 | .ioremap_registers = at91sam9263_ioremap_registers, | 381 | .ioremap_registers = at91sam9263_ioremap_registers, |
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c index c68960d82247..dc49c2c45d49 100644 --- a/arch/arm/mach-at91/at91sam9g45.c +++ b/arch/arm/mach-at91/at91sam9g45.c | |||
| @@ -420,7 +420,7 @@ static unsigned int at91sam9g45_default_irq_priority[NR_AIC_IRQS] __initdata = { | |||
| 420 | 0, /* Advanced Interrupt Controller (IRQ0) */ | 420 | 0, /* Advanced Interrupt Controller (IRQ0) */ |
| 421 | }; | 421 | }; |
| 422 | 422 | ||
| 423 | AT91_SOC_START(sam9g45) | 423 | AT91_SOC_START(at91sam9g45) |
| 424 | .map_io = at91sam9g45_map_io, | 424 | .map_io = at91sam9g45_map_io, |
| 425 | .default_irq_priority = at91sam9g45_default_irq_priority, | 425 | .default_irq_priority = at91sam9g45_default_irq_priority, |
| 426 | .ioremap_registers = at91sam9g45_ioremap_registers, | 426 | .ioremap_registers = at91sam9g45_ioremap_registers, |
diff --git a/arch/arm/mach-at91/at91sam9n12.c b/arch/arm/mach-at91/at91sam9n12.c index 5dfc8fd87103..2c7a2f4a7568 100644 --- a/arch/arm/mach-at91/at91sam9n12.c +++ b/arch/arm/mach-at91/at91sam9n12.c | |||
| @@ -226,7 +226,7 @@ void __init at91sam9n12_initialize(void) | |||
| 226 | at91_extern_irq = (1 << AT91SAM9N12_ID_IRQ0); | 226 | at91_extern_irq = (1 << AT91SAM9N12_ID_IRQ0); |
| 227 | } | 227 | } |
| 228 | 228 | ||
| 229 | AT91_SOC_START(sam9n12) | 229 | AT91_SOC_START(at91sam9n12) |
| 230 | .map_io = at91sam9n12_map_io, | 230 | .map_io = at91sam9n12_map_io, |
| 231 | .register_clocks = at91sam9n12_register_clocks, | 231 | .register_clocks = at91sam9n12_register_clocks, |
| 232 | .init = at91sam9n12_initialize, | 232 | .init = at91sam9n12_initialize, |
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c index 3de3e04d0f81..f77fae5591bc 100644 --- a/arch/arm/mach-at91/at91sam9rl.c +++ b/arch/arm/mach-at91/at91sam9rl.c | |||
| @@ -341,7 +341,7 @@ static unsigned int at91sam9rl_default_irq_priority[NR_AIC_IRQS] __initdata = { | |||
| 341 | 0, /* Advanced Interrupt Controller */ | 341 | 0, /* Advanced Interrupt Controller */ |
| 342 | }; | 342 | }; |
| 343 | 343 | ||
| 344 | AT91_SOC_START(sam9rl) | 344 | AT91_SOC_START(at91sam9rl) |
| 345 | .map_io = at91sam9rl_map_io, | 345 | .map_io = at91sam9rl_map_io, |
| 346 | .default_irq_priority = at91sam9rl_default_irq_priority, | 346 | .default_irq_priority = at91sam9rl_default_irq_priority, |
| 347 | .ioremap_registers = at91sam9rl_ioremap_registers, | 347 | .ioremap_registers = at91sam9rl_ioremap_registers, |
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c index 44a9a62dcc13..3a1a7993c125 100644 --- a/arch/arm/mach-at91/at91sam9x5.c +++ b/arch/arm/mach-at91/at91sam9x5.c | |||
| @@ -320,7 +320,7 @@ static void __init at91sam9x5_map_io(void) | |||
| 320 | * Interrupt initialization | 320 | * Interrupt initialization |
| 321 | * -------------------------------------------------------------------- */ | 321 | * -------------------------------------------------------------------- */ |
| 322 | 322 | ||
| 323 | AT91_SOC_START(sam9x5) | 323 | AT91_SOC_START(at91sam9x5) |
| 324 | .map_io = at91sam9x5_map_io, | 324 | .map_io = at91sam9x5_map_io, |
| 325 | .register_clocks = at91sam9x5_register_clocks, | 325 | .register_clocks = at91sam9x5_register_clocks, |
| 326 | AT91_SOC_END | 326 | AT91_SOC_END |
diff --git a/arch/arm/mach-at91/board-rm9200-dt.c b/arch/arm/mach-at91/board-dt-rm9200.c index 3fcb6623a33e..3fcb6623a33e 100644 --- a/arch/arm/mach-at91/board-rm9200-dt.c +++ b/arch/arm/mach-at91/board-dt-rm9200.c | |||
diff --git a/arch/arm/mach-at91/board-dt.c b/arch/arm/mach-at91/board-dt-sam9.c index 8db30132abed..8db30132abed 100644 --- a/arch/arm/mach-at91/board-dt.c +++ b/arch/arm/mach-at91/board-dt-sam9.c | |||
diff --git a/arch/arm/mach-at91/board-dt-sama5.c b/arch/arm/mach-at91/board-dt-sama5.c new file mode 100644 index 000000000000..705305e62bbc --- /dev/null +++ b/arch/arm/mach-at91/board-dt-sama5.c | |||
| @@ -0,0 +1,86 @@ | |||
| 1 | /* | ||
| 2 | * Setup code for SAMA5 Evaluation Kits with Device Tree support | ||
| 3 | * | ||
| 4 | * Copyright (C) 2013 Atmel, | ||
| 5 | * 2013 Ludovic Desroches <ludovic.desroches@atmel.com> | ||
| 6 | * | ||
| 7 | * Licensed under GPLv2 or later. | ||
| 8 | */ | ||
| 9 | |||
| 10 | #include <linux/types.h> | ||
| 11 | #include <linux/init.h> | ||
| 12 | #include <linux/module.h> | ||
| 13 | #include <linux/gpio.h> | ||
| 14 | #include <linux/micrel_phy.h> | ||
| 15 | #include <linux/of.h> | ||
| 16 | #include <linux/of_irq.h> | ||
| 17 | #include <linux/of_platform.h> | ||
| 18 | #include <linux/phy.h> | ||
| 19 | |||
| 20 | #include <asm/setup.h> | ||
| 21 | #include <asm/irq.h> | ||
| 22 | #include <asm/mach/arch.h> | ||
| 23 | #include <asm/mach/map.h> | ||
| 24 | #include <asm/mach/irq.h> | ||
| 25 | |||
| 26 | #include "at91_aic.h" | ||
| 27 | #include "generic.h" | ||
| 28 | |||
| 29 | |||
| 30 | static const struct of_device_id irq_of_match[] __initconst = { | ||
| 31 | |||
| 32 | { .compatible = "atmel,sama5d3-aic", .data = at91_aic5_of_init }, | ||
| 33 | { /*sentinel*/ } | ||
| 34 | }; | ||
| 35 | |||
| 36 | static void __init at91_dt_init_irq(void) | ||
| 37 | { | ||
| 38 | of_irq_init(irq_of_match); | ||
| 39 | } | ||
| 40 | |||
| 41 | static int ksz9021rn_phy_fixup(struct phy_device *phy) | ||
| 42 | { | ||
| 43 | int value; | ||
| 44 | |||
| 45 | #define GMII_RCCPSR 260 | ||
| 46 | #define GMII_RRDPSR 261 | ||
| 47 | #define GMII_ERCR 11 | ||
| 48 | #define GMII_ERDWR 12 | ||
| 49 | |||
| 50 | /* Set delay values */ | ||
| 51 | value = GMII_RCCPSR | 0x8000; | ||
| 52 | phy_write(phy, GMII_ERCR, value); | ||
| 53 | value = 0xF2F4; | ||
| 54 | phy_write(phy, GMII_ERDWR, value); | ||
| 55 | value = GMII_RRDPSR | 0x8000; | ||
| 56 | phy_write(phy, GMII_ERCR, value); | ||
| 57 | value = 0x2222; | ||
| 58 | phy_write(phy, GMII_ERDWR, value); | ||
| 59 | |||
| 60 | return 0; | ||
| 61 | } | ||
| 62 | |||
| 63 | static void __init sama5_dt_device_init(void) | ||
| 64 | { | ||
| 65 | if (of_machine_is_compatible("atmel,sama5d3xcm")) | ||
| 66 | phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK, | ||
| 67 | ksz9021rn_phy_fixup); | ||
| 68 | |||
| 69 | of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); | ||
| 70 | } | ||
| 71 | |||
| 72 | static const char *sama5_dt_board_compat[] __initdata = { | ||
| 73 | "atmel,sama5", | ||
| 74 | NULL | ||
| 75 | }; | ||
| 76 | |||
| 77 | DT_MACHINE_START(sama5_dt, "Atmel SAMA5 (Device Tree)") | ||
| 78 | /* Maintainer: Atmel */ | ||
| 79 | .init_time = at91sam926x_pit_init, | ||
| 80 | .map_io = at91_map_io, | ||
| 81 | .handle_irq = at91_aic5_handle_irq, | ||
| 82 | .init_early = at91_dt_initialize, | ||
| 83 | .init_irq = at91_dt_init_irq, | ||
| 84 | .init_machine = sama5_dt_device_init, | ||
| 85 | .dt_compat = sama5_dt_board_compat, | ||
| 86 | MACHINE_END | ||
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c index 33361505c0cd..da841885d01c 100644 --- a/arch/arm/mach-at91/clock.c +++ b/arch/arm/mach-at91/clock.c | |||
| @@ -54,7 +54,10 @@ EXPORT_SYMBOL_GPL(at91_pmc_base); | |||
| 54 | */ | 54 | */ |
| 55 | #define cpu_has_utmi() ( cpu_is_at91sam9rl() \ | 55 | #define cpu_has_utmi() ( cpu_is_at91sam9rl() \ |
| 56 | || cpu_is_at91sam9g45() \ | 56 | || cpu_is_at91sam9g45() \ |
| 57 | || cpu_is_at91sam9x5()) | 57 | || cpu_is_at91sam9x5() \ |
| 58 | || cpu_is_sama5d3()) | ||
| 59 | |||
| 60 | #define cpu_has_1056M_plla() (cpu_is_sama5d3()) | ||
| 58 | 61 | ||
| 59 | #define cpu_has_800M_plla() ( cpu_is_at91sam9g20() \ | 62 | #define cpu_has_800M_plla() ( cpu_is_at91sam9g20() \ |
| 60 | || cpu_is_at91sam9g45() \ | 63 | || cpu_is_at91sam9g45() \ |
| @@ -75,7 +78,8 @@ EXPORT_SYMBOL_GPL(at91_pmc_base); | |||
| 75 | || cpu_is_at91sam9n12())) | 78 | || cpu_is_at91sam9n12())) |
| 76 | 79 | ||
| 77 | #define cpu_has_upll() (cpu_is_at91sam9g45() \ | 80 | #define cpu_has_upll() (cpu_is_at91sam9g45() \ |
| 78 | || cpu_is_at91sam9x5()) | 81 | || cpu_is_at91sam9x5() \ |
| 82 | || cpu_is_sama5d3()) | ||
| 79 | 83 | ||
| 80 | /* USB host HS & FS */ | 84 | /* USB host HS & FS */ |
| 81 | #define cpu_has_uhp() (!cpu_is_at91sam9rl()) | 85 | #define cpu_has_uhp() (!cpu_is_at91sam9rl()) |
| @@ -83,18 +87,22 @@ EXPORT_SYMBOL_GPL(at91_pmc_base); | |||
| 83 | /* USB device FS only */ | 87 | /* USB device FS only */ |
| 84 | #define cpu_has_udpfs() (!(cpu_is_at91sam9rl() \ | 88 | #define cpu_has_udpfs() (!(cpu_is_at91sam9rl() \ |
| 85 | || cpu_is_at91sam9g45() \ | 89 | || cpu_is_at91sam9g45() \ |
| 86 | || cpu_is_at91sam9x5())) | 90 | || cpu_is_at91sam9x5() \ |
| 91 | || cpu_is_sama5d3())) | ||
| 87 | 92 | ||
| 88 | #define cpu_has_plladiv2() (cpu_is_at91sam9g45() \ | 93 | #define cpu_has_plladiv2() (cpu_is_at91sam9g45() \ |
| 89 | || cpu_is_at91sam9x5() \ | 94 | || cpu_is_at91sam9x5() \ |
| 90 | || cpu_is_at91sam9n12()) | 95 | || cpu_is_at91sam9n12() \ |
| 96 | || cpu_is_sama5d3()) | ||
| 91 | 97 | ||
| 92 | #define cpu_has_mdiv3() (cpu_is_at91sam9g45() \ | 98 | #define cpu_has_mdiv3() (cpu_is_at91sam9g45() \ |
| 93 | || cpu_is_at91sam9x5() \ | 99 | || cpu_is_at91sam9x5() \ |
| 94 | || cpu_is_at91sam9n12()) | 100 | || cpu_is_at91sam9n12() \ |
| 101 | || cpu_is_sama5d3()) | ||
| 95 | 102 | ||
| 96 | #define cpu_has_alt_prescaler() (cpu_is_at91sam9x5() \ | 103 | #define cpu_has_alt_prescaler() (cpu_is_at91sam9x5() \ |
| 97 | || cpu_is_at91sam9n12()) | 104 | || cpu_is_at91sam9n12() \ |
| 105 | || cpu_is_sama5d3()) | ||
| 98 | 106 | ||
| 99 | static LIST_HEAD(clocks); | 107 | static LIST_HEAD(clocks); |
| 100 | static DEFINE_SPINLOCK(clk_lock); | 108 | static DEFINE_SPINLOCK(clk_lock); |
| @@ -210,10 +218,26 @@ struct clk mck = { | |||
| 210 | 218 | ||
| 211 | static void pmc_periph_mode(struct clk *clk, int is_on) | 219 | static void pmc_periph_mode(struct clk *clk, int is_on) |
| 212 | { | 220 | { |
| 213 | if (is_on) | 221 | u32 regval = 0; |
| 214 | at91_pmc_write(AT91_PMC_PCER, clk->pmc_mask); | 222 | |
| 215 | else | 223 | /* |
| 216 | at91_pmc_write(AT91_PMC_PCDR, clk->pmc_mask); | 224 | * With sama5d3 devices, we are managing clock division so we have to |
| 225 | * use the Peripheral Control Register introduced from at91sam9x5 | ||
| 226 | * devices. | ||
| 227 | */ | ||
| 228 | if (cpu_is_sama5d3()) { | ||
| 229 | regval |= AT91_PMC_PCR_CMD; /* write command */ | ||
| 230 | regval |= clk->pid & AT91_PMC_PCR_PID; /* peripheral selection */ | ||
| 231 | regval |= AT91_PMC_PCR_DIV(clk->div); | ||
| 232 | if (is_on) | ||
| 233 | regval |= AT91_PMC_PCR_EN; /* enable clock */ | ||
| 234 | at91_pmc_write(AT91_PMC_PCR, regval); | ||
| 235 | } else { | ||
| 236 | if (is_on) | ||
| 237 | at91_pmc_write(AT91_PMC_PCER, clk->pmc_mask); | ||
| 238 | else | ||
| 239 | at91_pmc_write(AT91_PMC_PCDR, clk->pmc_mask); | ||
| 240 | } | ||
| 217 | } | 241 | } |
| 218 | 242 | ||
| 219 | static struct clk __init *at91_css_to_clk(unsigned long css) | 243 | static struct clk __init *at91_css_to_clk(unsigned long css) |
| @@ -443,14 +467,18 @@ static void __init init_programmable_clock(struct clk *clk) | |||
| 443 | 467 | ||
| 444 | static int at91_clk_show(struct seq_file *s, void *unused) | 468 | static int at91_clk_show(struct seq_file *s, void *unused) |
| 445 | { | 469 | { |
| 446 | u32 scsr, pcsr, uckr = 0, sr; | 470 | u32 scsr, pcsr, pcsr1 = 0, uckr = 0, sr; |
| 447 | struct clk *clk; | 471 | struct clk *clk; |
| 448 | 472 | ||
| 449 | scsr = at91_pmc_read(AT91_PMC_SCSR); | 473 | scsr = at91_pmc_read(AT91_PMC_SCSR); |
| 450 | pcsr = at91_pmc_read(AT91_PMC_PCSR); | 474 | pcsr = at91_pmc_read(AT91_PMC_PCSR); |
| 475 | if (cpu_is_sama5d3()) | ||
| 476 | pcsr1 = at91_pmc_read(AT91_PMC_PCSR1); | ||
| 451 | sr = at91_pmc_read(AT91_PMC_SR); | 477 | sr = at91_pmc_read(AT91_PMC_SR); |
| 452 | seq_printf(s, "SCSR = %8x\n", scsr); | 478 | seq_printf(s, "SCSR = %8x\n", scsr); |
| 453 | seq_printf(s, "PCSR = %8x\n", pcsr); | 479 | seq_printf(s, "PCSR = %8x\n", pcsr); |
| 480 | if (cpu_is_sama5d3()) | ||
| 481 | seq_printf(s, "PCSR1 = %8x\n", pcsr1); | ||
| 454 | seq_printf(s, "MOR = %8x\n", at91_pmc_read(AT91_CKGR_MOR)); | 482 | seq_printf(s, "MOR = %8x\n", at91_pmc_read(AT91_CKGR_MOR)); |
| 455 | seq_printf(s, "MCFR = %8x\n", at91_pmc_read(AT91_CKGR_MCFR)); | 483 | seq_printf(s, "MCFR = %8x\n", at91_pmc_read(AT91_CKGR_MCFR)); |
| 456 | seq_printf(s, "PLLA = %8x\n", at91_pmc_read(AT91_CKGR_PLLAR)); | 484 | seq_printf(s, "PLLA = %8x\n", at91_pmc_read(AT91_CKGR_PLLAR)); |
| @@ -470,20 +498,30 @@ static int at91_clk_show(struct seq_file *s, void *unused) | |||
| 470 | list_for_each_entry(clk, &clocks, node) { | 498 | list_for_each_entry(clk, &clocks, node) { |
| 471 | char *state; | 499 | char *state; |
| 472 | 500 | ||
| 473 | if (clk->mode == pmc_sys_mode) | 501 | if (clk->mode == pmc_sys_mode) { |
| 474 | state = (scsr & clk->pmc_mask) ? "on" : "off"; | 502 | state = (scsr & clk->pmc_mask) ? "on" : "off"; |
| 475 | else if (clk->mode == pmc_periph_mode) | 503 | } else if (clk->mode == pmc_periph_mode) { |
| 476 | state = (pcsr & clk->pmc_mask) ? "on" : "off"; | 504 | if (cpu_is_sama5d3()) { |
| 477 | else if (clk->mode == pmc_uckr_mode) | 505 | u32 pmc_mask = 1 << (clk->pid % 32); |
| 506 | |||
| 507 | if (clk->pid > 31) | ||
| 508 | state = (pcsr1 & pmc_mask) ? "on" : "off"; | ||
| 509 | else | ||
| 510 | state = (pcsr & pmc_mask) ? "on" : "off"; | ||
| 511 | } else { | ||
| 512 | state = (pcsr & clk->pmc_mask) ? "on" : "off"; | ||
| 513 | } | ||
| 514 | } else if (clk->mode == pmc_uckr_mode) { | ||
| 478 | state = (uckr & clk->pmc_mask) ? "on" : "off"; | 515 | state = (uckr & clk->pmc_mask) ? "on" : "off"; |
| 479 | else if (clk->pmc_mask) | 516 | } else if (clk->pmc_mask) { |
| 480 | state = (sr & clk->pmc_mask) ? "on" : "off"; | 517 | state = (sr & clk->pmc_mask) ? "on" : "off"; |
| 481 | else if (clk == &clk32k || clk == &main_clk) | 518 | } else if (clk == &clk32k || clk == &main_clk) { |
| 482 | state = "on"; | 519 | state = "on"; |
| 483 | else | 520 | } else { |
| 484 | state = ""; | 521 | state = ""; |
| 522 | } | ||
| 485 | 523 | ||
| 486 | seq_printf(s, "%-10s users=%2d %-3s %9ld Hz %s\n", | 524 | seq_printf(s, "%-10s users=%2d %-3s %9lu Hz %s\n", |
| 487 | clk->name, clk->users, state, clk_get_rate(clk), | 525 | clk->name, clk->users, state, clk_get_rate(clk), |
| 488 | clk->parent ? clk->parent->name : ""); | 526 | clk->parent ? clk->parent->name : ""); |
| 489 | } | 527 | } |
| @@ -530,6 +568,9 @@ int __init clk_register(struct clk *clk) | |||
| 530 | if (clk_is_peripheral(clk)) { | 568 | if (clk_is_peripheral(clk)) { |
| 531 | if (!clk->parent) | 569 | if (!clk->parent) |
| 532 | clk->parent = &mck; | 570 | clk->parent = &mck; |
| 571 | if (cpu_is_sama5d3()) | ||
| 572 | clk->rate_hz = DIV_ROUND_UP(clk->parent->rate_hz, | ||
| 573 | 1 << clk->div); | ||
| 533 | clk->mode = pmc_periph_mode; | 574 | clk->mode = pmc_periph_mode; |
| 534 | } | 575 | } |
| 535 | else if (clk_is_sys(clk)) { | 576 | else if (clk_is_sys(clk)) { |
| @@ -555,7 +596,11 @@ static u32 __init at91_pll_rate(struct clk *pll, u32 freq, u32 reg) | |||
| 555 | unsigned mul, div; | 596 | unsigned mul, div; |
| 556 | 597 | ||
| 557 | div = reg & 0xff; | 598 | div = reg & 0xff; |
| 558 | mul = (reg >> 16) & 0x7ff; | 599 | if (cpu_is_sama5d3()) |
| 600 | mul = AT91_PMC3_MUL_GET(reg); | ||
| 601 | else | ||
| 602 | mul = AT91_PMC_MUL_GET(reg); | ||
| 603 | |||
| 559 | if (div && mul) { | 604 | if (div && mul) { |
| 560 | freq /= div; | 605 | freq /= div; |
| 561 | freq *= mul + 1; | 606 | freq *= mul + 1; |
| @@ -706,12 +751,15 @@ static int __init at91_pmc_init(unsigned long main_clock) | |||
| 706 | 751 | ||
| 707 | /* report if PLLA is more than mildly overclocked */ | 752 | /* report if PLLA is more than mildly overclocked */ |
| 708 | plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_pmc_read(AT91_CKGR_PLLAR)); | 753 | plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_pmc_read(AT91_CKGR_PLLAR)); |
| 709 | if (cpu_has_300M_plla()) { | 754 | if (cpu_has_1056M_plla()) { |
| 710 | if (plla.rate_hz > 300000000) | 755 | if (plla.rate_hz > 1056000000) |
| 711 | pll_overclock = true; | 756 | pll_overclock = true; |
| 712 | } else if (cpu_has_800M_plla()) { | 757 | } else if (cpu_has_800M_plla()) { |
| 713 | if (plla.rate_hz > 800000000) | 758 | if (plla.rate_hz > 800000000) |
| 714 | pll_overclock = true; | 759 | pll_overclock = true; |
| 760 | } else if (cpu_has_300M_plla()) { | ||
| 761 | if (plla.rate_hz > 300000000) | ||
| 762 | pll_overclock = true; | ||
| 715 | } else if (cpu_has_240M_plla()) { | 763 | } else if (cpu_has_240M_plla()) { |
| 716 | if (plla.rate_hz > 240000000) | 764 | if (plla.rate_hz > 240000000) |
| 717 | pll_overclock = true; | 765 | pll_overclock = true; |
| @@ -872,6 +920,7 @@ int __init at91_clock_init(unsigned long main_clock) | |||
| 872 | static int __init at91_clock_reset(void) | 920 | static int __init at91_clock_reset(void) |
| 873 | { | 921 | { |
| 874 | unsigned long pcdr = 0; | 922 | unsigned long pcdr = 0; |
| 923 | unsigned long pcdr1 = 0; | ||
| 875 | unsigned long scdr = 0; | 924 | unsigned long scdr = 0; |
| 876 | struct clk *clk; | 925 | struct clk *clk; |
| 877 | 926 | ||
| @@ -879,8 +928,17 @@ static int __init at91_clock_reset(void) | |||
| 879 | if (clk->users > 0) | 928 | if (clk->users > 0) |
| 880 | continue; | 929 | continue; |
| 881 | 930 | ||
| 882 | if (clk->mode == pmc_periph_mode) | 931 | if (clk->mode == pmc_periph_mode) { |
| 883 | pcdr |= clk->pmc_mask; | 932 | if (cpu_is_sama5d3()) { |
| 933 | u32 pmc_mask = 1 << (clk->pid % 32); | ||
| 934 | |||
| 935 | if (clk->pid > 31) | ||
| 936 | pcdr1 |= pmc_mask; | ||
| 937 | else | ||
| 938 | pcdr |= pmc_mask; | ||
| 939 | } else | ||
| 940 | pcdr |= clk->pmc_mask; | ||
| 941 | } | ||
| 884 | 942 | ||
| 885 | if (clk->mode == pmc_sys_mode) | 943 | if (clk->mode == pmc_sys_mode) |
| 886 | scdr |= clk->pmc_mask; | 944 | scdr |= clk->pmc_mask; |
| @@ -888,8 +946,9 @@ static int __init at91_clock_reset(void) | |||
| 888 | pr_debug("Clocks: disable unused %s\n", clk->name); | 946 | pr_debug("Clocks: disable unused %s\n", clk->name); |
| 889 | } | 947 | } |
| 890 | 948 | ||
| 891 | at91_pmc_write(AT91_PMC_PCDR, pcdr); | ||
| 892 | at91_pmc_write(AT91_PMC_SCDR, scdr); | 949 | at91_pmc_write(AT91_PMC_SCDR, scdr); |
| 950 | if (cpu_is_sama5d3()) | ||
| 951 | at91_pmc_write(AT91_PMC_PCDR1, pcdr1); | ||
| 893 | 952 | ||
| 894 | return 0; | 953 | return 0; |
| 895 | } | 954 | } |
diff --git a/arch/arm/mach-at91/clock.h b/arch/arm/mach-at91/clock.h index c2e63e47dcbe..a98a39bbd883 100644 --- a/arch/arm/mach-at91/clock.h +++ b/arch/arm/mach-at91/clock.h | |||
| @@ -20,7 +20,9 @@ struct clk { | |||
| 20 | const char *name; /* unique clock name */ | 20 | const char *name; /* unique clock name */ |
| 21 | struct clk_lookup cl; | 21 | struct clk_lookup cl; |
| 22 | unsigned long rate_hz; | 22 | unsigned long rate_hz; |
| 23 | unsigned div; /* parent clock divider */ | ||
| 23 | struct clk *parent; | 24 | struct clk *parent; |
| 25 | unsigned pid; /* peripheral ID */ | ||
| 24 | u32 pmc_mask; | 26 | u32 pmc_mask; |
| 25 | void (*mode)(struct clk *, int); | 27 | void (*mode)(struct clk *, int); |
| 26 | unsigned id:3; /* PCK0..4, or 32k/main/a/b */ | 28 | unsigned id:3; /* PCK0..4, or 32k/main/a/b */ |
diff --git a/arch/arm/mach-at91/cpuidle.c b/arch/arm/mach-at91/cpuidle.c index 0c6381516a5a..4c6794603780 100644 --- a/arch/arm/mach-at91/cpuidle.c +++ b/arch/arm/mach-at91/cpuidle.c | |||
| @@ -38,6 +38,8 @@ static int at91_enter_idle(struct cpuidle_device *dev, | |||
| 38 | at91rm9200_standby(); | 38 | at91rm9200_standby(); |
| 39 | else if (cpu_is_at91sam9g45()) | 39 | else if (cpu_is_at91sam9g45()) |
| 40 | at91sam9g45_standby(); | 40 | at91sam9g45_standby(); |
| 41 | else if (cpu_is_at91sam9263()) | ||
| 42 | at91sam9263_standby(); | ||
| 41 | else | 43 | else |
| 42 | at91sam9_standby(); | 44 | at91sam9_standby(); |
| 43 | 45 | ||
diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h index ea2c57a86ca6..31df12029c4e 100644 --- a/arch/arm/mach-at91/include/mach/at91_pmc.h +++ b/arch/arm/mach-at91/include/mach/at91_pmc.h | |||
| @@ -75,6 +75,9 @@ extern void __iomem *at91_pmc_base; | |||
| 75 | #define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */ | 75 | #define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */ |
| 76 | #define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */ | 76 | #define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */ |
| 77 | #define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */ | 77 | #define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */ |
| 78 | #define AT91_PMC_MUL_GET(n) ((n) >> 16 & 0x7ff) | ||
| 79 | #define AT91_PMC3_MUL (0x7f << 18) /* PLL Multiplier [SAMA5 only] */ | ||
| 80 | #define AT91_PMC3_MUL_GET(n) ((n) >> 18 & 0x7f) | ||
| 78 | #define AT91_PMC_USBDIV (3 << 28) /* USB Divisor (PLLB only) */ | 81 | #define AT91_PMC_USBDIV (3 << 28) /* USB Divisor (PLLB only) */ |
| 79 | #define AT91_PMC_USBDIV_1 (0 << 28) | 82 | #define AT91_PMC_USBDIV_1 (0 << 28) |
| 80 | #define AT91_PMC_USBDIV_2 (1 << 28) | 83 | #define AT91_PMC_USBDIV_2 (1 << 28) |
| @@ -167,11 +170,18 @@ extern void __iomem *at91_pmc_base; | |||
| 167 | #define AT91_PMC_WPVS (0x1 << 0) /* Write Protect Violation Status */ | 170 | #define AT91_PMC_WPVS (0x1 << 0) /* Write Protect Violation Status */ |
| 168 | #define AT91_PMC_WPVSRC (0xffff << 8) /* Write Protect Violation Source */ | 171 | #define AT91_PMC_WPVSRC (0xffff << 8) /* Write Protect Violation Source */ |
| 169 | 172 | ||
| 170 | #define AT91_PMC_PCR 0x10c /* Peripheral Control Register [some SAM9] */ | 173 | #define AT91_PMC_PCER1 0x100 /* Peripheral Clock Enable Register 1 [SAMA5 only]*/ |
| 174 | #define AT91_PMC_PCDR1 0x104 /* Peripheral Clock Enable Register 1 */ | ||
| 175 | #define AT91_PMC_PCSR1 0x108 /* Peripheral Clock Enable Register 1 */ | ||
| 176 | |||
| 177 | #define AT91_PMC_PCR 0x10c /* Peripheral Control Register [some SAM9 and SAMA5] */ | ||
| 171 | #define AT91_PMC_PCR_PID (0x3f << 0) /* Peripheral ID */ | 178 | #define AT91_PMC_PCR_PID (0x3f << 0) /* Peripheral ID */ |
| 172 | #define AT91_PMC_PCR_CMD (0x1 << 12) /* Command */ | 179 | #define AT91_PMC_PCR_CMD (0x1 << 12) /* Command (read=0, write=1) */ |
| 173 | #define AT91_PMC_PCR_DIV (0x3 << 16) /* Divisor Value */ | 180 | #define AT91_PMC_PCR_DIV(n) ((n) << 16) /* Divisor Value */ |
| 174 | #define AT91_PMC_PCRDIV(n) (((n) << 16) & AT91_PMC_PCR_DIV) | 181 | #define AT91_PMC_PCR_DIV0 0x0 /* Peripheral clock is MCK */ |
| 182 | #define AT91_PMC_PCR_DIV2 0x2 /* Peripheral clock is MCK/2 */ | ||
| 183 | #define AT91_PMC_PCR_DIV4 0x4 /* Peripheral clock is MCK/4 */ | ||
| 184 | #define AT91_PMC_PCR_DIV8 0x8 /* Peripheral clock is MCK/8 */ | ||
| 175 | #define AT91_PMC_PCR_EN (0x1 << 28) /* Enable */ | 185 | #define AT91_PMC_PCR_EN (0x1 << 28) /* Enable */ |
| 176 | 186 | ||
| 177 | #endif | 187 | #endif |
diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h index b6504c19d55c..d3d7b993846b 100644 --- a/arch/arm/mach-at91/include/mach/cpu.h +++ b/arch/arm/mach-at91/include/mach/cpu.h | |||
| @@ -36,6 +36,8 @@ | |||
| 36 | #define ARCH_ID_AT91M40807 0x14080745 | 36 | #define ARCH_ID_AT91M40807 0x14080745 |
| 37 | #define ARCH_ID_AT91R40008 0x44000840 | 37 | #define ARCH_ID_AT91R40008 0x44000840 |
| 38 | 38 | ||
| 39 | #define ARCH_ID_SAMA5D3 0x8A5C07C0 | ||
| 40 | |||
| 39 | #define ARCH_EXID_AT91SAM9M11 0x00000001 | 41 | #define ARCH_EXID_AT91SAM9M11 0x00000001 |
| 40 | #define ARCH_EXID_AT91SAM9M10 0x00000002 | 42 | #define ARCH_EXID_AT91SAM9M10 0x00000002 |
| 41 | #define ARCH_EXID_AT91SAM9G46 0x00000003 | 43 | #define ARCH_EXID_AT91SAM9G46 0x00000003 |
| @@ -47,6 +49,11 @@ | |||
| 47 | #define ARCH_EXID_AT91SAM9G25 0x00000003 | 49 | #define ARCH_EXID_AT91SAM9G25 0x00000003 |
| 48 | #define ARCH_EXID_AT91SAM9X25 0x00000004 | 50 | #define ARCH_EXID_AT91SAM9X25 0x00000004 |
| 49 | 51 | ||
| 52 | #define ARCH_EXID_SAMA5D31 0x00444300 | ||
| 53 | #define ARCH_EXID_SAMA5D33 0x00414300 | ||
| 54 | #define ARCH_EXID_SAMA5D34 0x00414301 | ||
| 55 | #define ARCH_EXID_SAMA5D35 0x00584300 | ||
| 56 | |||
| 50 | #define ARCH_FAMILY_AT91X92 0x09200000 | 57 | #define ARCH_FAMILY_AT91X92 0x09200000 |
| 51 | #define ARCH_FAMILY_AT91SAM9 0x01900000 | 58 | #define ARCH_FAMILY_AT91SAM9 0x01900000 |
| 52 | #define ARCH_FAMILY_AT91SAM9XE 0x02900000 | 59 | #define ARCH_FAMILY_AT91SAM9XE 0x02900000 |
| @@ -75,8 +82,11 @@ enum at91_soc_type { | |||
| 75 | /* SAM9N12 */ | 82 | /* SAM9N12 */ |
| 76 | AT91_SOC_SAM9N12, | 83 | AT91_SOC_SAM9N12, |
| 77 | 84 | ||
| 85 | /* SAMA5D3 */ | ||
| 86 | AT91_SOC_SAMA5D3, | ||
| 87 | |||
| 78 | /* Unknown type */ | 88 | /* Unknown type */ |
| 79 | AT91_SOC_NONE | 89 | AT91_SOC_UNKNOWN, |
| 80 | }; | 90 | }; |
| 81 | 91 | ||
| 82 | enum at91_soc_subtype { | 92 | enum at91_soc_subtype { |
| @@ -93,8 +103,15 @@ enum at91_soc_subtype { | |||
| 93 | AT91_SOC_SAM9G15, AT91_SOC_SAM9G35, AT91_SOC_SAM9X35, | 103 | AT91_SOC_SAM9G15, AT91_SOC_SAM9G35, AT91_SOC_SAM9X35, |
| 94 | AT91_SOC_SAM9G25, AT91_SOC_SAM9X25, | 104 | AT91_SOC_SAM9G25, AT91_SOC_SAM9X25, |
| 95 | 105 | ||
| 106 | /* SAMA5D3 */ | ||
| 107 | AT91_SOC_SAMA5D31, AT91_SOC_SAMA5D33, AT91_SOC_SAMA5D34, | ||
| 108 | AT91_SOC_SAMA5D35, | ||
| 109 | |||
| 110 | /* No subtype for this SoC */ | ||
| 111 | AT91_SOC_SUBTYPE_NONE, | ||
| 112 | |||
| 96 | /* Unknown subtype */ | 113 | /* Unknown subtype */ |
| 97 | AT91_SOC_SUBTYPE_NONE | 114 | AT91_SOC_SUBTYPE_UNKNOWN, |
| 98 | }; | 115 | }; |
| 99 | 116 | ||
| 100 | struct at91_socinfo { | 117 | struct at91_socinfo { |
| @@ -108,7 +125,7 @@ const char *at91_get_soc_subtype(struct at91_socinfo *c); | |||
| 108 | 125 | ||
| 109 | static inline int at91_soc_is_detected(void) | 126 | static inline int at91_soc_is_detected(void) |
| 110 | { | 127 | { |
| 111 | return at91_soc_initdata.type != AT91_SOC_NONE; | 128 | return at91_soc_initdata.type != AT91_SOC_UNKNOWN; |
| 112 | } | 129 | } |
| 113 | 130 | ||
| 114 | #ifdef CONFIG_SOC_AT91RM9200 | 131 | #ifdef CONFIG_SOC_AT91RM9200 |
| @@ -187,6 +204,12 @@ static inline int at91_soc_is_detected(void) | |||
| 187 | #define cpu_is_at91sam9n12() (0) | 204 | #define cpu_is_at91sam9n12() (0) |
| 188 | #endif | 205 | #endif |
| 189 | 206 | ||
| 207 | #ifdef CONFIG_SOC_SAMA5D3 | ||
| 208 | #define cpu_is_sama5d3() (at91_soc_initdata.type == AT91_SOC_SAMA5D3) | ||
| 209 | #else | ||
| 210 | #define cpu_is_sama5d3() (0) | ||
| 211 | #endif | ||
| 212 | |||
| 190 | /* | 213 | /* |
| 191 | * Since this is ARM, we will never run on any AVR32 CPU. But these | 214 | * Since this is ARM, we will never run on any AVR32 CPU. But these |
| 192 | * definitions may reduce clutter in common drivers. | 215 | * definitions may reduce clutter in common drivers. |
diff --git a/arch/arm/mach-at91/include/mach/sama5d3.h b/arch/arm/mach-at91/include/mach/sama5d3.h new file mode 100644 index 000000000000..6dc81ee38048 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/sama5d3.h | |||
| @@ -0,0 +1,73 @@ | |||
| 1 | /* | ||
| 2 | * Chip-specific header file for the SAMA5D3 family | ||
| 3 | * | ||
| 4 | * Copyright (C) 2013 Atmel, | ||
| 5 | * 2013 Ludovic Desroches <ludovic.desroches@atmel.com> | ||
| 6 | * | ||
| 7 | * Common definitions. | ||
| 8 | * Based on SAMA5D3 datasheet. | ||
| 9 | * | ||
| 10 | * Licensed under GPLv2 or later. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef SAMA5D3_H | ||
| 14 | #define SAMA5D3_H | ||
| 15 | |||
| 16 | /* | ||
| 17 | * Peripheral identifiers/interrupts. | ||
| 18 | */ | ||
| 19 | #define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ | ||
| 20 | #define AT91_ID_SYS 1 /* System Peripherals */ | ||
| 21 | #define SAMA5D3_ID_DBGU 2 /* debug Unit (usually no special interrupt line) */ | ||
| 22 | #define AT91_ID_PIT 3 /* PIT */ | ||
| 23 | #define SAMA5D3_ID_WDT 4 /* Watchdog Timer Interrupt */ | ||
| 24 | #define SAMA5D3_ID_HSMC 5 /* Static Memory Controller */ | ||
| 25 | #define SAMA5D3_ID_PIOA 6 /* PIOA */ | ||
| 26 | #define SAMA5D3_ID_PIOB 7 /* PIOB */ | ||
| 27 | #define SAMA5D3_ID_PIOC 8 /* PIOC */ | ||
| 28 | #define SAMA5D3_ID_PIOD 9 /* PIOD */ | ||
| 29 | #define SAMA5D3_ID_PIOE 10 /* PIOE */ | ||
| 30 | #define SAMA5D3_ID_SMD 11 /* SMD Soft Modem */ | ||
| 31 | #define SAMA5D3_ID_USART0 12 /* USART0 */ | ||
| 32 | #define SAMA5D3_ID_USART1 13 /* USART1 */ | ||
| 33 | #define SAMA5D3_ID_USART2 14 /* USART2 */ | ||
| 34 | #define SAMA5D3_ID_USART3 15 /* USART3 */ | ||
| 35 | #define SAMA5D3_ID_UART0 16 /* UART 0 */ | ||
| 36 | #define SAMA5D3_ID_UART1 17 /* UART 1 */ | ||
| 37 | #define SAMA5D3_ID_TWI0 18 /* Two-Wire Interface 0 */ | ||
| 38 | #define SAMA5D3_ID_TWI1 19 /* Two-Wire Interface 1 */ | ||
| 39 | #define SAMA5D3_ID_TWI2 20 /* Two-Wire Interface 2 */ | ||
| 40 | #define SAMA5D3_ID_HSMCI0 21 /* MCI */ | ||
| 41 | #define SAMA5D3_ID_HSMCI1 22 /* MCI */ | ||
| 42 | #define SAMA5D3_ID_HSMCI2 23 /* MCI */ | ||
| 43 | #define SAMA5D3_ID_SPI0 24 /* Serial Peripheral Interface 0 */ | ||
| 44 | #define SAMA5D3_ID_SPI1 25 /* Serial Peripheral Interface 1 */ | ||
| 45 | #define SAMA5D3_ID_TC0 26 /* Timer Counter 0 */ | ||
| 46 | #define SAMA5D3_ID_TC1 27 /* Timer Counter 2 */ | ||
| 47 | #define SAMA5D3_ID_PWM 28 /* Pulse Width Modulation Controller */ | ||
| 48 | #define SAMA5D3_ID_ADC 29 /* Touch Screen ADC Controller */ | ||
| 49 | #define SAMA5D3_ID_DMA0 30 /* DMA Controller 0 */ | ||
| 50 | #define SAMA5D3_ID_DMA1 31 /* DMA Controller 1 */ | ||
| 51 | #define SAMA5D3_ID_UHPHS 32 /* USB Host High Speed */ | ||
| 52 | #define SAMA5D3_ID_UDPHS 33 /* USB Device High Speed */ | ||
| 53 | #define SAMA5D3_ID_GMAC 34 /* Gigabit Ethernet MAC */ | ||
| 54 | #define SAMA5D3_ID_EMAC 35 /* Ethernet MAC */ | ||
| 55 | #define SAMA5D3_ID_LCDC 36 /* LCD Controller */ | ||
| 56 | #define SAMA5D3_ID_ISI 37 /* Image Sensor Interface */ | ||
| 57 | #define SAMA5D3_ID_SSC0 38 /* Synchronous Serial Controller 0 */ | ||
| 58 | #define SAMA5D3_ID_SSC1 39 /* Synchronous Serial Controller 1 */ | ||
| 59 | #define SAMA5D3_ID_CAN0 40 /* CAN Controller 0 */ | ||
| 60 | #define SAMA5D3_ID_CAN1 41 /* CAN Controller 1 */ | ||
| 61 | #define SAMA5D3_ID_SHA 42 /* Secure Hash Algorithm */ | ||
| 62 | #define SAMA5D3_ID_AES 43 /* Advanced Encryption Standard */ | ||
| 63 | #define SAMA5D3_ID_TDES 44 /* Triple Data Encryption Standard */ | ||
| 64 | #define SAMA5D3_ID_TRNG 45 /* True Random Generator Number */ | ||
| 65 | #define SAMA5D3_ID_IRQ0 47 /* Advanced Interrupt Controller (IRQ0) */ | ||
| 66 | |||
| 67 | /* | ||
| 68 | * Internal Memory | ||
| 69 | */ | ||
| 70 | #define SAMA5D3_SRAM_BASE 0x00300000 /* Internal SRAM base address */ | ||
| 71 | #define SAMA5D3_SRAM_SIZE (128 * SZ_1K) /* Internal SRAM size (128Kb) */ | ||
| 72 | |||
| 73 | #endif | ||
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index 73f1f250403a..530db304ec5e 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c | |||
| @@ -270,6 +270,8 @@ static int at91_pm_enter(suspend_state_t state) | |||
| 270 | at91rm9200_standby(); | 270 | at91rm9200_standby(); |
| 271 | else if (cpu_is_at91sam9g45()) | 271 | else if (cpu_is_at91sam9g45()) |
| 272 | at91sam9g45_standby(); | 272 | at91sam9g45_standby(); |
| 273 | else if (cpu_is_at91sam9263()) | ||
| 274 | at91sam9263_standby(); | ||
| 273 | else | 275 | else |
| 274 | at91sam9_standby(); | 276 | at91sam9_standby(); |
| 275 | break; | 277 | break; |
diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h index 38f467c6b710..2f5908f0b8c5 100644 --- a/arch/arm/mach-at91/pm.h +++ b/arch/arm/mach-at91/pm.h | |||
| @@ -70,13 +70,31 @@ static inline void at91sam9g45_standby(void) | |||
| 70 | at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1); | 70 | at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1); |
| 71 | } | 71 | } |
| 72 | 72 | ||
| 73 | #ifdef CONFIG_SOC_AT91SAM9263 | 73 | /* We manage both DDRAM/SDRAM controllers, we need more than one value to |
| 74 | /* | 74 | * remember. |
| 75 | * FIXME either or both the SDRAM controllers (EB0, EB1) might be in use; | ||
| 76 | * handle those cases both here and in the Suspend-To-RAM support. | ||
| 77 | */ | 75 | */ |
| 78 | #warning Assuming EB1 SDRAM controller is *NOT* used | 76 | static inline void at91sam9263_standby(void) |
| 79 | #endif | 77 | { |
| 78 | u32 lpr0, lpr1; | ||
| 79 | u32 saved_lpr0, saved_lpr1; | ||
| 80 | |||
| 81 | saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR); | ||
| 82 | lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB; | ||
| 83 | lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH; | ||
| 84 | |||
| 85 | saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR); | ||
| 86 | lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB; | ||
| 87 | lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH; | ||
| 88 | |||
| 89 | /* self-refresh mode now */ | ||
| 90 | at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0); | ||
| 91 | at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1); | ||
| 92 | |||
| 93 | cpu_do_idle(); | ||
| 94 | |||
| 95 | at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0); | ||
| 96 | at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1); | ||
| 97 | } | ||
| 80 | 98 | ||
| 81 | static inline void at91sam9_standby(void) | 99 | static inline void at91sam9_standby(void) |
| 82 | { | 100 | { |
diff --git a/arch/arm/mach-at91/sama5d3.c b/arch/arm/mach-at91/sama5d3.c new file mode 100644 index 000000000000..401279715ab1 --- /dev/null +++ b/arch/arm/mach-at91/sama5d3.c | |||
| @@ -0,0 +1,377 @@ | |||
| 1 | /* | ||
| 2 | * Chip-specific setup code for the SAMA5D3 family | ||
| 3 | * | ||
| 4 | * Copyright (C) 2013 Atmel, | ||
| 5 | * 2013 Ludovic Desroches <ludovic.desroches@atmel.com> | ||
| 6 | * | ||
| 7 | * Licensed under GPLv2 or later. | ||
| 8 | */ | ||
| 9 | |||
| 10 | #include <linux/module.h> | ||
| 11 | #include <linux/dma-mapping.h> | ||
| 12 | |||
| 13 | #include <asm/irq.h> | ||
| 14 | #include <asm/mach/arch.h> | ||
| 15 | #include <asm/mach/map.h> | ||
| 16 | #include <mach/sama5d3.h> | ||
| 17 | #include <mach/at91_pmc.h> | ||
| 18 | #include <mach/cpu.h> | ||
| 19 | |||
| 20 | #include "soc.h" | ||
| 21 | #include "generic.h" | ||
| 22 | #include "clock.h" | ||
| 23 | #include "sam9_smc.h" | ||
| 24 | |||
| 25 | /* -------------------------------------------------------------------- | ||
| 26 | * Clocks | ||
| 27 | * -------------------------------------------------------------------- */ | ||
| 28 | |||
| 29 | /* | ||
| 30 | * The peripheral clocks. | ||
| 31 | */ | ||
| 32 | |||
| 33 | static struct clk pioA_clk = { | ||
| 34 | .name = "pioA_clk", | ||
| 35 | .pid = SAMA5D3_ID_PIOA, | ||
| 36 | .type = CLK_TYPE_PERIPHERAL, | ||
| 37 | }; | ||
| 38 | static struct clk pioB_clk = { | ||
| 39 | .name = "pioB_clk", | ||
| 40 | .pid = SAMA5D3_ID_PIOB, | ||
| 41 | .type = CLK_TYPE_PERIPHERAL, | ||
| 42 | }; | ||
| 43 | static struct clk pioC_clk = { | ||
| 44 | .name = "pioC_clk", | ||
| 45 | .pid = SAMA5D3_ID_PIOC, | ||
| 46 | .type = CLK_TYPE_PERIPHERAL, | ||
| 47 | }; | ||
| 48 | static struct clk pioD_clk = { | ||
| 49 | .name = "pioD_clk", | ||
| 50 | .pid = SAMA5D3_ID_PIOD, | ||
| 51 | .type = CLK_TYPE_PERIPHERAL, | ||
| 52 | }; | ||
| 53 | static struct clk pioE_clk = { | ||
| 54 | .name = "pioE_clk", | ||
| 55 | .pid = SAMA5D3_ID_PIOE, | ||
| 56 | .type = CLK_TYPE_PERIPHERAL, | ||
| 57 | }; | ||
| 58 | static struct clk usart0_clk = { | ||
| 59 | .name = "usart0_clk", | ||
| 60 | .pid = SAMA5D3_ID_USART0, | ||
| 61 | .type = CLK_TYPE_PERIPHERAL, | ||
| 62 | .div = AT91_PMC_PCR_DIV2, | ||
| 63 | }; | ||
| 64 | static struct clk usart1_clk = { | ||
| 65 | .name = "usart1_clk", | ||
| 66 | .pid = SAMA5D3_ID_USART1, | ||
| 67 | .type = CLK_TYPE_PERIPHERAL, | ||
| 68 | .div = AT91_PMC_PCR_DIV2, | ||
| 69 | }; | ||
| 70 | static struct clk usart2_clk = { | ||
| 71 | .name = "usart2_clk", | ||
| 72 | .pid = SAMA5D3_ID_USART2, | ||
| 73 | .type = CLK_TYPE_PERIPHERAL, | ||
| 74 | .div = AT91_PMC_PCR_DIV2, | ||
| 75 | }; | ||
| 76 | static struct clk usart3_clk = { | ||
| 77 | .name = "usart3_clk", | ||
| 78 | .pid = SAMA5D3_ID_USART3, | ||
| 79 | .type = CLK_TYPE_PERIPHERAL, | ||
| 80 | .div = AT91_PMC_PCR_DIV2, | ||
| 81 | }; | ||
| 82 | static struct clk uart0_clk = { | ||
| 83 | .name = "uart0_clk", | ||
| 84 | .pid = SAMA5D3_ID_UART0, | ||
| 85 | .type = CLK_TYPE_PERIPHERAL, | ||
| 86 | .div = AT91_PMC_PCR_DIV2, | ||
| 87 | }; | ||
| 88 | static struct clk uart1_clk = { | ||
| 89 | .name = "uart1_clk", | ||
| 90 | .pid = SAMA5D3_ID_UART1, | ||
| 91 | .type = CLK_TYPE_PERIPHERAL, | ||
| 92 | .div = AT91_PMC_PCR_DIV2, | ||
| 93 | }; | ||
| 94 | static struct clk twi0_clk = { | ||
| 95 | .name = "twi0_clk", | ||
| 96 | .pid = SAMA5D3_ID_TWI0, | ||
| 97 | .type = CLK_TYPE_PERIPHERAL, | ||
| 98 | .div = AT91_PMC_PCR_DIV2, | ||
| 99 | }; | ||
| 100 | static struct clk twi1_clk = { | ||
| 101 | .name = "twi1_clk", | ||
| 102 | .pid = SAMA5D3_ID_TWI1, | ||
| 103 | .type = CLK_TYPE_PERIPHERAL, | ||
| 104 | .div = AT91_PMC_PCR_DIV2, | ||
| 105 | }; | ||
| 106 | static struct clk twi2_clk = { | ||
| 107 | .name = "twi2_clk", | ||
| 108 | .pid = SAMA5D3_ID_TWI2, | ||
| 109 | .type = CLK_TYPE_PERIPHERAL, | ||
| 110 | .div = AT91_PMC_PCR_DIV2, | ||
| 111 | }; | ||
| 112 | static struct clk mmc0_clk = { | ||
| 113 | .name = "mci0_clk", | ||
| 114 | .pid = SAMA5D3_ID_HSMCI0, | ||
| 115 | .type = CLK_TYPE_PERIPHERAL, | ||
| 116 | }; | ||
| 117 | static struct clk mmc1_clk = { | ||
| 118 | .name = "mci1_clk", | ||
| 119 | .pid = SAMA5D3_ID_HSMCI1, | ||
| 120 | .type = CLK_TYPE_PERIPHERAL, | ||
| 121 | }; | ||
| 122 | static struct clk mmc2_clk = { | ||
| 123 | .name = "mci2_clk", | ||
| 124 | .pid = SAMA5D3_ID_HSMCI2, | ||
| 125 | .type = CLK_TYPE_PERIPHERAL, | ||
| 126 | }; | ||
| 127 | static struct clk spi0_clk = { | ||
| 128 | .name = "spi0_clk", | ||
| 129 | .pid = SAMA5D3_ID_SPI0, | ||
| 130 | .type = CLK_TYPE_PERIPHERAL, | ||
| 131 | }; | ||
| 132 | static struct clk spi1_clk = { | ||
| 133 | .name = "spi1_clk", | ||
| 134 | .pid = SAMA5D3_ID_SPI1, | ||
| 135 | .type = CLK_TYPE_PERIPHERAL, | ||
| 136 | }; | ||
| 137 | static struct clk tcb0_clk = { | ||
| 138 | .name = "tcb0_clk", | ||
| 139 | .pid = SAMA5D3_ID_TC0, | ||
| 140 | .type = CLK_TYPE_PERIPHERAL, | ||
| 141 | .div = AT91_PMC_PCR_DIV2, | ||
| 142 | }; | ||
| 143 | static struct clk tcb1_clk = { | ||
| 144 | .name = "tcb1_clk", | ||
| 145 | .pid = SAMA5D3_ID_TC1, | ||
| 146 | .type = CLK_TYPE_PERIPHERAL, | ||
| 147 | .div = AT91_PMC_PCR_DIV2, | ||
| 148 | }; | ||
| 149 | static struct clk adc_clk = { | ||
| 150 | .name = "adc_clk", | ||
| 151 | .pid = SAMA5D3_ID_ADC, | ||
| 152 | .type = CLK_TYPE_PERIPHERAL, | ||
| 153 | .div = AT91_PMC_PCR_DIV2, | ||
| 154 | }; | ||
| 155 | static struct clk adc_op_clk = { | ||
| 156 | .name = "adc_op_clk", | ||
| 157 | .type = CLK_TYPE_PERIPHERAL, | ||
| 158 | .rate_hz = 5000000, | ||
| 159 | }; | ||
| 160 | static struct clk dma0_clk = { | ||
| 161 | .name = "dma0_clk", | ||
| 162 | .pid = SAMA5D3_ID_DMA0, | ||
| 163 | .type = CLK_TYPE_PERIPHERAL, | ||
| 164 | }; | ||
| 165 | static struct clk dma1_clk = { | ||
| 166 | .name = "dma1_clk", | ||
| 167 | .pid = SAMA5D3_ID_DMA1, | ||
| 168 | .type = CLK_TYPE_PERIPHERAL, | ||
| 169 | }; | ||
| 170 | static struct clk uhphs_clk = { | ||
| 171 | .name = "uhphs", | ||
| 172 | .pid = SAMA5D3_ID_UHPHS, | ||
| 173 | .type = CLK_TYPE_PERIPHERAL, | ||
| 174 | }; | ||
| 175 | static struct clk udphs_clk = { | ||
| 176 | .name = "udphs_clk", | ||
| 177 | .pid = SAMA5D3_ID_UDPHS, | ||
| 178 | .type = CLK_TYPE_PERIPHERAL, | ||
| 179 | }; | ||
| 180 | /* gmac only for sama5d33, sama5d34, sama5d35 */ | ||
| 181 | static struct clk macb0_clk = { | ||
| 182 | .name = "macb0_clk", | ||
| 183 | .pid = SAMA5D3_ID_GMAC, | ||
| 184 | .type = CLK_TYPE_PERIPHERAL, | ||
| 185 | }; | ||
| 186 | /* emac only for sama5d31, sama5d35 */ | ||
| 187 | static struct clk macb1_clk = { | ||
| 188 | .name = "macb1_clk", | ||
| 189 | .pid = SAMA5D3_ID_EMAC, | ||
| 190 | .type = CLK_TYPE_PERIPHERAL, | ||
| 191 | }; | ||
| 192 | /* lcd only for sama5d31, sama5d33, sama5d34 */ | ||
| 193 | static struct clk lcdc_clk = { | ||
| 194 | .name = "lcdc_clk", | ||
| 195 | .pid = SAMA5D3_ID_LCDC, | ||
| 196 | .type = CLK_TYPE_PERIPHERAL, | ||
| 197 | }; | ||
| 198 | /* isi only for sama5d33, sama5d35 */ | ||
| 199 | static struct clk isi_clk = { | ||
| 200 | .name = "isi_clk", | ||
| 201 | .pid = SAMA5D3_ID_ISI, | ||
| 202 | .type = CLK_TYPE_PERIPHERAL, | ||
| 203 | }; | ||
| 204 | static struct clk can0_clk = { | ||
| 205 | .name = "can0_clk", | ||
| 206 | .pid = SAMA5D3_ID_CAN0, | ||
| 207 | .type = CLK_TYPE_PERIPHERAL, | ||
| 208 | .div = AT91_PMC_PCR_DIV2, | ||
| 209 | }; | ||
| 210 | static struct clk can1_clk = { | ||
| 211 | .name = "can1_clk", | ||
| 212 | .pid = SAMA5D3_ID_CAN1, | ||
| 213 | .type = CLK_TYPE_PERIPHERAL, | ||
| 214 | .div = AT91_PMC_PCR_DIV2, | ||
| 215 | }; | ||
| 216 | static struct clk ssc0_clk = { | ||
| 217 | .name = "ssc0_clk", | ||
| 218 | .pid = SAMA5D3_ID_SSC0, | ||
| 219 | .type = CLK_TYPE_PERIPHERAL, | ||
| 220 | .div = AT91_PMC_PCR_DIV2, | ||
| 221 | }; | ||
| 222 | static struct clk ssc1_clk = { | ||
| 223 | .name = "ssc1_clk", | ||
| 224 | .pid = SAMA5D3_ID_SSC1, | ||
| 225 | .type = CLK_TYPE_PERIPHERAL, | ||
| 226 | .div = AT91_PMC_PCR_DIV2, | ||
| 227 | }; | ||
| 228 | static struct clk sha_clk = { | ||
| 229 | .name = "sha_clk", | ||
| 230 | .pid = SAMA5D3_ID_SHA, | ||
| 231 | .type = CLK_TYPE_PERIPHERAL, | ||
| 232 | .div = AT91_PMC_PCR_DIV8, | ||
| 233 | }; | ||
| 234 | static struct clk aes_clk = { | ||
| 235 | .name = "aes_clk", | ||
| 236 | .pid = SAMA5D3_ID_AES, | ||
| 237 | .type = CLK_TYPE_PERIPHERAL, | ||
| 238 | }; | ||
| 239 | static struct clk tdes_clk = { | ||
| 240 | .name = "tdes_clk", | ||
| 241 | .pid = SAMA5D3_ID_TDES, | ||
| 242 | .type = CLK_TYPE_PERIPHERAL, | ||
| 243 | }; | ||
| 244 | |||
| 245 | static struct clk *periph_clocks[] __initdata = { | ||
| 246 | &pioA_clk, | ||
| 247 | &pioB_clk, | ||
| 248 | &pioC_clk, | ||
| 249 | &pioD_clk, | ||
| 250 | &pioE_clk, | ||
| 251 | &usart0_clk, | ||
| 252 | &usart1_clk, | ||
| 253 | &usart2_clk, | ||
| 254 | &usart3_clk, | ||
| 255 | &uart0_clk, | ||
| 256 | &uart1_clk, | ||
| 257 | &twi0_clk, | ||
| 258 | &twi1_clk, | ||
| 259 | &twi2_clk, | ||
| 260 | &mmc0_clk, | ||
| 261 | &mmc1_clk, | ||
| 262 | &mmc2_clk, | ||
| 263 | &spi0_clk, | ||
| 264 | &spi1_clk, | ||
| 265 | &tcb0_clk, | ||
| 266 | &tcb1_clk, | ||
| 267 | &adc_clk, | ||
| 268 | &adc_op_clk, | ||
| 269 | &dma0_clk, | ||
| 270 | &dma1_clk, | ||
| 271 | &uhphs_clk, | ||
| 272 | &udphs_clk, | ||
| 273 | &macb0_clk, | ||
| 274 | &macb1_clk, | ||
| 275 | &lcdc_clk, | ||
| 276 | &isi_clk, | ||
| 277 | &can0_clk, | ||
| 278 | &can1_clk, | ||
| 279 | &ssc0_clk, | ||
| 280 | &ssc1_clk, | ||
| 281 | &sha_clk, | ||
| 282 | &aes_clk, | ||
| 283 | &tdes_clk, | ||
| 284 | }; | ||
| 285 | |||
| 286 | static struct clk pck0 = { | ||
| 287 | .name = "pck0", | ||
| 288 | .pmc_mask = AT91_PMC_PCK0, | ||
| 289 | .type = CLK_TYPE_PROGRAMMABLE, | ||
| 290 | .id = 0, | ||
| 291 | }; | ||
| 292 | |||
| 293 | static struct clk pck1 = { | ||
| 294 | .name = "pck1", | ||
| 295 | .pmc_mask = AT91_PMC_PCK1, | ||
| 296 | .type = CLK_TYPE_PROGRAMMABLE, | ||
| 297 | .id = 1, | ||
| 298 | }; | ||
| 299 | |||
| 300 | static struct clk pck2 = { | ||
| 301 | .name = "pck2", | ||
| 302 | .pmc_mask = AT91_PMC_PCK2, | ||
| 303 | .type = CLK_TYPE_PROGRAMMABLE, | ||
| 304 | .id = 2, | ||
| 305 | }; | ||
| 306 | |||
| 307 | static struct clk_lookup periph_clocks_lookups[] = { | ||
| 308 | /* lookup table for DT entries */ | ||
| 309 | CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck), | ||
| 310 | CLKDEV_CON_DEV_ID(NULL, "fffff200.gpio", &pioA_clk), | ||
| 311 | CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioB_clk), | ||
| 312 | CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioC_clk), | ||
| 313 | CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioD_clk), | ||
| 314 | CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioE_clk), | ||
| 315 | CLKDEV_CON_DEV_ID("usart", "f001c000.serial", &usart0_clk), | ||
| 316 | CLKDEV_CON_DEV_ID("usart", "f0020000.serial", &usart1_clk), | ||
| 317 | CLKDEV_CON_DEV_ID("usart", "f8020000.serial", &usart2_clk), | ||
| 318 | CLKDEV_CON_DEV_ID("usart", "f8024000.serial", &usart3_clk), | ||
| 319 | CLKDEV_CON_DEV_ID(NULL, "f0014000.i2c", &twi0_clk), | ||
| 320 | CLKDEV_CON_DEV_ID(NULL, "f0018000.i2c", &twi1_clk), | ||
| 321 | CLKDEV_CON_DEV_ID(NULL, "f801c000.i2c", &twi2_clk), | ||
| 322 | CLKDEV_CON_DEV_ID("mci_clk", "f0000000.mmc", &mmc0_clk), | ||
| 323 | CLKDEV_CON_DEV_ID("mci_clk", "f8000000.mmc", &mmc1_clk), | ||
| 324 | CLKDEV_CON_DEV_ID("mci_clk", "f8004000.mmc", &mmc2_clk), | ||
| 325 | CLKDEV_CON_DEV_ID("spi_clk", "f0004000.spi", &spi0_clk), | ||
| 326 | CLKDEV_CON_DEV_ID("spi_clk", "f8008000.spi", &spi1_clk), | ||
| 327 | CLKDEV_CON_DEV_ID("t0_clk", "f0010000.timer", &tcb0_clk), | ||
| 328 | CLKDEV_CON_DEV_ID("t0_clk", "f8014000.timer", &tcb1_clk), | ||
| 329 | CLKDEV_CON_DEV_ID("tsc_clk", "f8018000.tsadcc", &adc_clk), | ||
| 330 | CLKDEV_CON_DEV_ID("dma_clk", "ffffe600.dma-controller", &dma0_clk), | ||
| 331 | CLKDEV_CON_DEV_ID("dma_clk", "ffffe800.dma-controller", &dma1_clk), | ||
| 332 | CLKDEV_CON_DEV_ID("hclk", "600000.ohci", &uhphs_clk), | ||
| 333 | CLKDEV_CON_DEV_ID("ohci_clk", "600000.ohci", &uhphs_clk), | ||
| 334 | CLKDEV_CON_DEV_ID("ehci_clk", "700000.ehci", &uhphs_clk), | ||
| 335 | CLKDEV_CON_DEV_ID("pclk", "500000.gadget", &udphs_clk), | ||
| 336 | CLKDEV_CON_DEV_ID("hclk", "500000.gadget", &utmi_clk), | ||
| 337 | CLKDEV_CON_DEV_ID("hclk", "f0028000.ethernet", &macb0_clk), | ||
| 338 | CLKDEV_CON_DEV_ID("pclk", "f0028000.ethernet", &macb0_clk), | ||
| 339 | CLKDEV_CON_DEV_ID("hclk", "f802c000.ethernet", &macb1_clk), | ||
| 340 | CLKDEV_CON_DEV_ID("pclk", "f802c000.ethernet", &macb1_clk), | ||
| 341 | CLKDEV_CON_DEV_ID("pclk", "f0008000.ssc", &ssc0_clk), | ||
| 342 | CLKDEV_CON_DEV_ID("pclk", "f000c000.ssc", &ssc1_clk), | ||
| 343 | CLKDEV_CON_DEV_ID("can_clk", "f000c000.can", &can0_clk), | ||
| 344 | CLKDEV_CON_DEV_ID("can_clk", "f8010000.can", &can1_clk), | ||
| 345 | CLKDEV_CON_DEV_ID("sha_clk", "f8034000.sha", &sha_clk), | ||
| 346 | CLKDEV_CON_DEV_ID("aes_clk", "f8038000.aes", &aes_clk), | ||
| 347 | CLKDEV_CON_DEV_ID("tdes_clk", "f803c000.tdes", &tdes_clk), | ||
| 348 | }; | ||
| 349 | |||
| 350 | static void __init sama5d3_register_clocks(void) | ||
| 351 | { | ||
| 352 | int i; | ||
| 353 | |||
| 354 | for (i = 0; i < ARRAY_SIZE(periph_clocks); i++) | ||
| 355 | clk_register(periph_clocks[i]); | ||
| 356 | |||
| 357 | clkdev_add_table(periph_clocks_lookups, | ||
| 358 | ARRAY_SIZE(periph_clocks_lookups)); | ||
| 359 | |||
| 360 | clk_register(&pck0); | ||
| 361 | clk_register(&pck1); | ||
| 362 | clk_register(&pck2); | ||
| 363 | } | ||
| 364 | |||
| 365 | /* -------------------------------------------------------------------- | ||
| 366 | * AT91SAM9x5 processor initialization | ||
| 367 | * -------------------------------------------------------------------- */ | ||
| 368 | |||
| 369 | static void __init sama5d3_map_io(void) | ||
| 370 | { | ||
| 371 | at91_init_sram(0, SAMA5D3_SRAM_BASE, SAMA5D3_SRAM_SIZE); | ||
| 372 | } | ||
| 373 | |||
| 374 | AT91_SOC_START(sama5d3) | ||
| 375 | .map_io = sama5d3_map_io, | ||
| 376 | .register_clocks = sama5d3_register_clocks, | ||
| 377 | AT91_SOC_END | ||
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c index 4b678478cf95..fd00a09da86b 100644 --- a/arch/arm/mach-at91/setup.c +++ b/arch/arm/mach-at91/setup.c | |||
| @@ -105,28 +105,32 @@ static void __init soc_detect(u32 dbgu_base) | |||
| 105 | switch (socid) { | 105 | switch (socid) { |
| 106 | case ARCH_ID_AT91RM9200: | 106 | case ARCH_ID_AT91RM9200: |
| 107 | at91_soc_initdata.type = AT91_SOC_RM9200; | 107 | at91_soc_initdata.type = AT91_SOC_RM9200; |
| 108 | if (at91_soc_initdata.subtype == AT91_SOC_SUBTYPE_NONE) | 108 | if (at91_soc_initdata.subtype == AT91_SOC_SUBTYPE_UNKNOWN) |
| 109 | at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA; | 109 | at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA; |
| 110 | at91_boot_soc = at91rm9200_soc; | 110 | at91_boot_soc = at91rm9200_soc; |
| 111 | break; | 111 | break; |
| 112 | 112 | ||
| 113 | case ARCH_ID_AT91SAM9260: | 113 | case ARCH_ID_AT91SAM9260: |
| 114 | at91_soc_initdata.type = AT91_SOC_SAM9260; | 114 | at91_soc_initdata.type = AT91_SOC_SAM9260; |
| 115 | at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE; | ||
| 115 | at91_boot_soc = at91sam9260_soc; | 116 | at91_boot_soc = at91sam9260_soc; |
| 116 | break; | 117 | break; |
| 117 | 118 | ||
| 118 | case ARCH_ID_AT91SAM9261: | 119 | case ARCH_ID_AT91SAM9261: |
| 119 | at91_soc_initdata.type = AT91_SOC_SAM9261; | 120 | at91_soc_initdata.type = AT91_SOC_SAM9261; |
| 121 | at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE; | ||
| 120 | at91_boot_soc = at91sam9261_soc; | 122 | at91_boot_soc = at91sam9261_soc; |
| 121 | break; | 123 | break; |
| 122 | 124 | ||
| 123 | case ARCH_ID_AT91SAM9263: | 125 | case ARCH_ID_AT91SAM9263: |
| 124 | at91_soc_initdata.type = AT91_SOC_SAM9263; | 126 | at91_soc_initdata.type = AT91_SOC_SAM9263; |
| 127 | at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE; | ||
| 125 | at91_boot_soc = at91sam9263_soc; | 128 | at91_boot_soc = at91sam9263_soc; |
| 126 | break; | 129 | break; |
| 127 | 130 | ||
| 128 | case ARCH_ID_AT91SAM9G20: | 131 | case ARCH_ID_AT91SAM9G20: |
| 129 | at91_soc_initdata.type = AT91_SOC_SAM9G20; | 132 | at91_soc_initdata.type = AT91_SOC_SAM9G20; |
| 133 | at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE; | ||
| 130 | at91_boot_soc = at91sam9260_soc; | 134 | at91_boot_soc = at91sam9260_soc; |
| 131 | break; | 135 | break; |
| 132 | 136 | ||
| @@ -139,6 +143,7 @@ static void __init soc_detect(u32 dbgu_base) | |||
| 139 | 143 | ||
| 140 | case ARCH_ID_AT91SAM9RL64: | 144 | case ARCH_ID_AT91SAM9RL64: |
| 141 | at91_soc_initdata.type = AT91_SOC_SAM9RL; | 145 | at91_soc_initdata.type = AT91_SOC_SAM9RL; |
| 146 | at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE; | ||
| 142 | at91_boot_soc = at91sam9rl_soc; | 147 | at91_boot_soc = at91sam9rl_soc; |
| 143 | break; | 148 | break; |
| 144 | 149 | ||
| @@ -151,11 +156,17 @@ static void __init soc_detect(u32 dbgu_base) | |||
| 151 | at91_soc_initdata.type = AT91_SOC_SAM9N12; | 156 | at91_soc_initdata.type = AT91_SOC_SAM9N12; |
| 152 | at91_boot_soc = at91sam9n12_soc; | 157 | at91_boot_soc = at91sam9n12_soc; |
| 153 | break; | 158 | break; |
| 159 | |||
| 160 | case ARCH_ID_SAMA5D3: | ||
| 161 | at91_soc_initdata.type = AT91_SOC_SAMA5D3; | ||
| 162 | at91_boot_soc = sama5d3_soc; | ||
| 163 | break; | ||
| 154 | } | 164 | } |
| 155 | 165 | ||
| 156 | /* at91sam9g10 */ | 166 | /* at91sam9g10 */ |
| 157 | if ((socid & ~AT91_CIDR_EXT) == ARCH_ID_AT91SAM9G10) { | 167 | if ((socid & ~AT91_CIDR_EXT) == ARCH_ID_AT91SAM9G10) { |
| 158 | at91_soc_initdata.type = AT91_SOC_SAM9G10; | 168 | at91_soc_initdata.type = AT91_SOC_SAM9G10; |
| 169 | at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE; | ||
| 159 | at91_boot_soc = at91sam9261_soc; | 170 | at91_boot_soc = at91sam9261_soc; |
| 160 | } | 171 | } |
| 161 | /* at91sam9xe */ | 172 | /* at91sam9xe */ |
| @@ -206,6 +217,23 @@ static void __init soc_detect(u32 dbgu_base) | |||
| 206 | break; | 217 | break; |
| 207 | } | 218 | } |
| 208 | } | 219 | } |
| 220 | |||
| 221 | if (at91_soc_initdata.type == AT91_SOC_SAMA5D3) { | ||
| 222 | switch (at91_soc_initdata.exid) { | ||
| 223 | case ARCH_EXID_SAMA5D31: | ||
| 224 | at91_soc_initdata.subtype = AT91_SOC_SAMA5D31; | ||
| 225 | break; | ||
| 226 | case ARCH_EXID_SAMA5D33: | ||
| 227 | at91_soc_initdata.subtype = AT91_SOC_SAMA5D33; | ||
| 228 | break; | ||
| 229 | case ARCH_EXID_SAMA5D34: | ||
| 230 | at91_soc_initdata.subtype = AT91_SOC_SAMA5D34; | ||
| 231 | break; | ||
| 232 | case ARCH_EXID_SAMA5D35: | ||
| 233 | at91_soc_initdata.subtype = AT91_SOC_SAMA5D35; | ||
| 234 | break; | ||
| 235 | } | ||
| 236 | } | ||
| 209 | } | 237 | } |
| 210 | 238 | ||
| 211 | static const char *soc_name[] = { | 239 | static const char *soc_name[] = { |
| @@ -219,7 +247,8 @@ static const char *soc_name[] = { | |||
| 219 | [AT91_SOC_SAM9RL] = "at91sam9rl", | 247 | [AT91_SOC_SAM9RL] = "at91sam9rl", |
| 220 | [AT91_SOC_SAM9X5] = "at91sam9x5", | 248 | [AT91_SOC_SAM9X5] = "at91sam9x5", |
| 221 | [AT91_SOC_SAM9N12] = "at91sam9n12", | 249 | [AT91_SOC_SAM9N12] = "at91sam9n12", |
| 222 | [AT91_SOC_NONE] = "Unknown" | 250 | [AT91_SOC_SAMA5D3] = "sama5d3", |
| 251 | [AT91_SOC_UNKNOWN] = "Unknown", | ||
| 223 | }; | 252 | }; |
| 224 | 253 | ||
| 225 | const char *at91_get_soc_type(struct at91_socinfo *c) | 254 | const char *at91_get_soc_type(struct at91_socinfo *c) |
| @@ -241,7 +270,12 @@ static const char *soc_subtype_name[] = { | |||
| 241 | [AT91_SOC_SAM9X35] = "at91sam9x35", | 270 | [AT91_SOC_SAM9X35] = "at91sam9x35", |
| 242 | [AT91_SOC_SAM9G25] = "at91sam9g25", | 271 | [AT91_SOC_SAM9G25] = "at91sam9g25", |
| 243 | [AT91_SOC_SAM9X25] = "at91sam9x25", | 272 | [AT91_SOC_SAM9X25] = "at91sam9x25", |
| 244 | [AT91_SOC_SUBTYPE_NONE] = "Unknown" | 273 | [AT91_SOC_SAMA5D31] = "sama5d31", |
| 274 | [AT91_SOC_SAMA5D33] = "sama5d33", | ||
| 275 | [AT91_SOC_SAMA5D34] = "sama5d34", | ||
| 276 | [AT91_SOC_SAMA5D35] = "sama5d35", | ||
| 277 | [AT91_SOC_SUBTYPE_NONE] = "None", | ||
| 278 | [AT91_SOC_SUBTYPE_UNKNOWN] = "Unknown", | ||
| 245 | }; | 279 | }; |
| 246 | 280 | ||
| 247 | const char *at91_get_soc_subtype(struct at91_socinfo *c) | 281 | const char *at91_get_soc_subtype(struct at91_socinfo *c) |
| @@ -255,8 +289,8 @@ void __init at91_map_io(void) | |||
| 255 | /* Map peripherals */ | 289 | /* Map peripherals */ |
| 256 | iotable_init(&at91_io_desc, 1); | 290 | iotable_init(&at91_io_desc, 1); |
| 257 | 291 | ||
| 258 | at91_soc_initdata.type = AT91_SOC_NONE; | 292 | at91_soc_initdata.type = AT91_SOC_UNKNOWN; |
| 259 | at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE; | 293 | at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_UNKNOWN; |
| 260 | 294 | ||
| 261 | soc_detect(AT91_BASE_DBGU0); | 295 | soc_detect(AT91_BASE_DBGU0); |
| 262 | if (!at91_soc_is_detected()) | 296 | if (!at91_soc_is_detected()) |
| @@ -267,8 +301,9 @@ void __init at91_map_io(void) | |||
| 267 | 301 | ||
| 268 | pr_info("AT91: Detected soc type: %s\n", | 302 | pr_info("AT91: Detected soc type: %s\n", |
| 269 | at91_get_soc_type(&at91_soc_initdata)); | 303 | at91_get_soc_type(&at91_soc_initdata)); |
| 270 | pr_info("AT91: Detected soc subtype: %s\n", | 304 | if (at91_soc_initdata.subtype != AT91_SOC_SUBTYPE_NONE) |
| 271 | at91_get_soc_subtype(&at91_soc_initdata)); | 305 | pr_info("AT91: Detected soc subtype: %s\n", |
| 306 | at91_get_soc_subtype(&at91_soc_initdata)); | ||
| 272 | 307 | ||
| 273 | if (!at91_soc_is_enabled()) | 308 | if (!at91_soc_is_enabled()) |
| 274 | panic("AT91: Soc not enabled"); | 309 | panic("AT91: Soc not enabled"); |
diff --git a/arch/arm/mach-at91/soc.h b/arch/arm/mach-at91/soc.h index 9c6d3d4f9a23..43a225f9e713 100644 --- a/arch/arm/mach-at91/soc.h +++ b/arch/arm/mach-at91/soc.h | |||
| @@ -22,9 +22,10 @@ extern struct at91_init_soc at91sam9g45_soc; | |||
| 22 | extern struct at91_init_soc at91sam9rl_soc; | 22 | extern struct at91_init_soc at91sam9rl_soc; |
| 23 | extern struct at91_init_soc at91sam9x5_soc; | 23 | extern struct at91_init_soc at91sam9x5_soc; |
| 24 | extern struct at91_init_soc at91sam9n12_soc; | 24 | extern struct at91_init_soc at91sam9n12_soc; |
| 25 | extern struct at91_init_soc sama5d3_soc; | ||
| 25 | 26 | ||
| 26 | #define AT91_SOC_START(_name) \ | 27 | #define AT91_SOC_START(_name) \ |
| 27 | struct at91_init_soc __initdata at91##_name##_soc \ | 28 | struct at91_init_soc __initdata _name##_soc \ |
| 28 | __used \ | 29 | __used \ |
| 29 | = { \ | 30 | = { \ |
| 30 | .builtin = 1, \ | 31 | .builtin = 1, \ |
| @@ -68,3 +69,7 @@ static inline int at91_soc_is_enabled(void) | |||
| 68 | #if !defined(CONFIG_SOC_AT91SAM9N12) | 69 | #if !defined(CONFIG_SOC_AT91SAM9N12) |
| 69 | #define at91sam9n12_soc at91_boot_soc | 70 | #define at91sam9n12_soc at91_boot_soc |
| 70 | #endif | 71 | #endif |
| 72 | |||
| 73 | #if !defined(CONFIG_SOC_SAMA5D3) | ||
| 74 | #define sama5d3_soc at91_boot_soc | ||
| 75 | #endif | ||
diff --git a/arch/arm/mach-cns3xxx/core.c b/arch/arm/mach-cns3xxx/core.c index e698f26cc0cb..52e4bb5cf12d 100644 --- a/arch/arm/mach-cns3xxx/core.c +++ b/arch/arm/mach-cns3xxx/core.c | |||
| @@ -22,19 +22,9 @@ | |||
| 22 | 22 | ||
| 23 | static struct map_desc cns3xxx_io_desc[] __initdata = { | 23 | static struct map_desc cns3xxx_io_desc[] __initdata = { |
| 24 | { | 24 | { |
| 25 | .virtual = CNS3XXX_TC11MP_TWD_BASE_VIRT, | 25 | .virtual = CNS3XXX_TC11MP_SCU_BASE_VIRT, |
| 26 | .pfn = __phys_to_pfn(CNS3XXX_TC11MP_TWD_BASE), | 26 | .pfn = __phys_to_pfn(CNS3XXX_TC11MP_SCU_BASE), |
| 27 | .length = SZ_4K, | 27 | .length = SZ_8K, |
| 28 | .type = MT_DEVICE, | ||
| 29 | }, { | ||
| 30 | .virtual = CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT, | ||
| 31 | .pfn = __phys_to_pfn(CNS3XXX_TC11MP_GIC_CPU_BASE), | ||
| 32 | .length = SZ_4K, | ||
| 33 | .type = MT_DEVICE, | ||
| 34 | }, { | ||
| 35 | .virtual = CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT, | ||
| 36 | .pfn = __phys_to_pfn(CNS3XXX_TC11MP_GIC_DIST_BASE), | ||
| 37 | .length = SZ_4K, | ||
| 38 | .type = MT_DEVICE, | 28 | .type = MT_DEVICE, |
| 39 | }, { | 29 | }, { |
| 40 | .virtual = CNS3XXX_TIMER1_2_3_BASE_VIRT, | 30 | .virtual = CNS3XXX_TIMER1_2_3_BASE_VIRT, |
diff --git a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h b/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h index 191c8e57f289..b1021aafa481 100644 --- a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h +++ b/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h | |||
| @@ -94,10 +94,10 @@ | |||
| 94 | #define RTC_INTR_STS_OFFSET 0x34 | 94 | #define RTC_INTR_STS_OFFSET 0x34 |
| 95 | 95 | ||
| 96 | #define CNS3XXX_MISC_BASE 0x76000000 /* Misc Control */ | 96 | #define CNS3XXX_MISC_BASE 0x76000000 /* Misc Control */ |
| 97 | #define CNS3XXX_MISC_BASE_VIRT 0xFFF07000 /* Misc Control */ | 97 | #define CNS3XXX_MISC_BASE_VIRT 0xFB000000 /* Misc Control */ |
| 98 | 98 | ||
| 99 | #define CNS3XXX_PM_BASE 0x77000000 /* Power Management Control */ | 99 | #define CNS3XXX_PM_BASE 0x77000000 /* Power Management Control */ |
| 100 | #define CNS3XXX_PM_BASE_VIRT 0xFFF08000 | 100 | #define CNS3XXX_PM_BASE_VIRT 0xFB001000 |
| 101 | 101 | ||
| 102 | #define PM_CLK_GATE_OFFSET 0x00 | 102 | #define PM_CLK_GATE_OFFSET 0x00 |
| 103 | #define PM_SOFT_RST_OFFSET 0x04 | 103 | #define PM_SOFT_RST_OFFSET 0x04 |
| @@ -109,7 +109,7 @@ | |||
| 109 | #define PM_PLL_HM_PD_OFFSET 0x1C | 109 | #define PM_PLL_HM_PD_OFFSET 0x1C |
| 110 | 110 | ||
| 111 | #define CNS3XXX_UART0_BASE 0x78000000 /* UART 0 */ | 111 | #define CNS3XXX_UART0_BASE 0x78000000 /* UART 0 */ |
| 112 | #define CNS3XXX_UART0_BASE_VIRT 0xFFF09000 | 112 | #define CNS3XXX_UART0_BASE_VIRT 0xFB002000 |
| 113 | 113 | ||
| 114 | #define CNS3XXX_UART1_BASE 0x78400000 /* UART 1 */ | 114 | #define CNS3XXX_UART1_BASE 0x78400000 /* UART 1 */ |
| 115 | #define CNS3XXX_UART1_BASE_VIRT 0xFFF0A000 | 115 | #define CNS3XXX_UART1_BASE_VIRT 0xFFF0A000 |
| @@ -130,7 +130,7 @@ | |||
| 130 | #define CNS3XXX_I2S_BASE_VIRT 0xFFF10000 | 130 | #define CNS3XXX_I2S_BASE_VIRT 0xFFF10000 |
| 131 | 131 | ||
| 132 | #define CNS3XXX_TIMER1_2_3_BASE 0x7C800000 /* Timer */ | 132 | #define CNS3XXX_TIMER1_2_3_BASE 0x7C800000 /* Timer */ |
| 133 | #define CNS3XXX_TIMER1_2_3_BASE_VIRT 0xFFF10800 | 133 | #define CNS3XXX_TIMER1_2_3_BASE_VIRT 0xFB003000 |
| 134 | 134 | ||
| 135 | #define TIMER1_COUNTER_OFFSET 0x00 | 135 | #define TIMER1_COUNTER_OFFSET 0x00 |
| 136 | #define TIMER1_AUTO_RELOAD_OFFSET 0x04 | 136 | #define TIMER1_AUTO_RELOAD_OFFSET 0x04 |
| @@ -227,16 +227,16 @@ | |||
| 227 | * Testchip peripheral and fpga gic regions | 227 | * Testchip peripheral and fpga gic regions |
| 228 | */ | 228 | */ |
| 229 | #define CNS3XXX_TC11MP_SCU_BASE 0x90000000 /* IRQ, Test chip */ | 229 | #define CNS3XXX_TC11MP_SCU_BASE 0x90000000 /* IRQ, Test chip */ |
| 230 | #define CNS3XXX_TC11MP_SCU_BASE_VIRT 0xFF000000 | 230 | #define CNS3XXX_TC11MP_SCU_BASE_VIRT 0xFB004000 |
| 231 | 231 | ||
| 232 | #define CNS3XXX_TC11MP_GIC_CPU_BASE 0x90000100 /* Test chip interrupt controller CPU interface */ | 232 | #define CNS3XXX_TC11MP_GIC_CPU_BASE 0x90000100 /* Test chip interrupt controller CPU interface */ |
| 233 | #define CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT 0xFF000100 | 233 | #define CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT (CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x100) |
| 234 | 234 | ||
| 235 | #define CNS3XXX_TC11MP_TWD_BASE 0x90000600 | 235 | #define CNS3XXX_TC11MP_TWD_BASE 0x90000600 |
| 236 | #define CNS3XXX_TC11MP_TWD_BASE_VIRT 0xFF000600 | 236 | #define CNS3XXX_TC11MP_TWD_BASE_VIRT (CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x600) |
| 237 | 237 | ||
| 238 | #define CNS3XXX_TC11MP_GIC_DIST_BASE 0x90001000 /* Test chip interrupt controller distributor */ | 238 | #define CNS3XXX_TC11MP_GIC_DIST_BASE 0x90001000 /* Test chip interrupt controller distributor */ |
| 239 | #define CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT 0xFF001000 | 239 | #define CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT (CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x1000) |
| 240 | 240 | ||
| 241 | #define CNS3XXX_TC11MP_L220_BASE 0x92002000 /* L220 registers */ | 241 | #define CNS3XXX_TC11MP_L220_BASE 0x92002000 /* L220 registers */ |
| 242 | #define CNS3XXX_TC11MP_L220_BASE_VIRT 0xFF002000 | 242 | #define CNS3XXX_TC11MP_L220_BASE_VIRT 0xFF002000 |
diff --git a/arch/arm/mach-ep93xx/include/mach/uncompress.h b/arch/arm/mach-ep93xx/include/mach/uncompress.h index d2afb4dd82ab..b5cc77d2380b 100644 --- a/arch/arm/mach-ep93xx/include/mach/uncompress.h +++ b/arch/arm/mach-ep93xx/include/mach/uncompress.h | |||
| @@ -47,9 +47,13 @@ static void __raw_writel(unsigned int value, unsigned int ptr) | |||
| 47 | 47 | ||
| 48 | static inline void putc(int c) | 48 | static inline void putc(int c) |
| 49 | { | 49 | { |
| 50 | /* Transmit fifo not full? */ | 50 | int i; |
| 51 | while (__raw_readb(PHYS_UART_FLAG) & UART_FLAG_TXFF) | 51 | |
| 52 | ; | 52 | for (i = 0; i < 10000; i++) { |
| 53 | /* Transmit fifo not full? */ | ||
| 54 | if (!(__raw_readb(PHYS_UART_FLAG) & UART_FLAG_TXFF)) | ||
| 55 | break; | ||
| 56 | } | ||
| 53 | 57 | ||
| 54 | __raw_writeb(c, PHYS_UART_DATA); | 58 | __raw_writeb(c, PHYS_UART_DATA); |
| 55 | } | 59 | } |
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 2f45906d6ee5..faca4326b46a 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig | |||
| @@ -79,12 +79,6 @@ config SOC_EXYNOS5440 | |||
| 79 | help | 79 | help |
| 80 | Enable EXYNOS5440 SoC support | 80 | Enable EXYNOS5440 SoC support |
| 81 | 81 | ||
| 82 | config EXYNOS4_MCT | ||
| 83 | bool | ||
| 84 | default y | ||
| 85 | help | ||
| 86 | Use MCT (Multi Core Timer) as kernel timers | ||
| 87 | |||
| 88 | config EXYNOS_DEV_DMA | 82 | config EXYNOS_DEV_DMA |
| 89 | bool | 83 | bool |
| 90 | help | 84 | help |
| @@ -406,6 +400,7 @@ config MACH_EXYNOS4_DT | |||
| 406 | bool "Samsung Exynos4 Machine using device tree" | 400 | bool "Samsung Exynos4 Machine using device tree" |
| 407 | depends on ARCH_EXYNOS4 | 401 | depends on ARCH_EXYNOS4 |
| 408 | select ARM_AMBA | 402 | select ARM_AMBA |
| 403 | select CLKSRC_OF | ||
| 409 | select CPU_EXYNOS4210 | 404 | select CPU_EXYNOS4210 |
| 410 | select HAVE_SAMSUNG_KEYPAD if INPUT_KEYBOARD | 405 | select HAVE_SAMSUNG_KEYPAD if INPUT_KEYBOARD |
| 411 | select PINCTRL | 406 | select PINCTRL |
| @@ -422,6 +417,7 @@ config MACH_EXYNOS5_DT | |||
| 422 | default y | 417 | default y |
| 423 | depends on ARCH_EXYNOS5 | 418 | depends on ARCH_EXYNOS5 |
| 424 | select ARM_AMBA | 419 | select ARM_AMBA |
| 420 | select CLKSRC_OF | ||
| 425 | select USE_OF | 421 | select USE_OF |
| 426 | help | 422 | help |
| 427 | Machine support for Samsung EXYNOS5 machine with device tree enabled. | 423 | Machine support for Samsung EXYNOS5 machine with device tree enabled. |
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile index 435757e57bb4..daf289b21486 100644 --- a/arch/arm/mach-exynos/Makefile +++ b/arch/arm/mach-exynos/Makefile | |||
| @@ -26,8 +26,6 @@ obj-$(CONFIG_ARCH_EXYNOS) += pmu.o | |||
| 26 | 26 | ||
| 27 | obj-$(CONFIG_SMP) += platsmp.o headsmp.o | 27 | obj-$(CONFIG_SMP) += platsmp.o headsmp.o |
| 28 | 28 | ||
| 29 | obj-$(CONFIG_EXYNOS4_MCT) += mct.o | ||
| 30 | |||
| 31 | obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o | 29 | obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o |
| 32 | 30 | ||
| 33 | # machine support | 31 | # machine support |
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c index bdd957978d9b..db7dbd0eb6b4 100644 --- a/arch/arm/mach-exynos/common.c +++ b/arch/arm/mach-exynos/common.c | |||
| @@ -257,11 +257,6 @@ static struct map_desc exynos5_iodesc[] __initdata = { | |||
| 257 | .length = SZ_4K, | 257 | .length = SZ_4K, |
| 258 | .type = MT_DEVICE, | 258 | .type = MT_DEVICE, |
| 259 | }, { | 259 | }, { |
| 260 | .virtual = (unsigned long)S5P_VA_SYSTIMER, | ||
| 261 | .pfn = __phys_to_pfn(EXYNOS5_PA_SYSTIMER), | ||
| 262 | .length = SZ_4K, | ||
| 263 | .type = MT_DEVICE, | ||
| 264 | }, { | ||
| 265 | .virtual = (unsigned long)S5P_VA_SYSRAM, | 260 | .virtual = (unsigned long)S5P_VA_SYSRAM, |
| 266 | .pfn = __phys_to_pfn(EXYNOS5_PA_SYSRAM), | 261 | .pfn = __phys_to_pfn(EXYNOS5_PA_SYSRAM), |
| 267 | .length = SZ_4K, | 262 | .length = SZ_4K, |
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h index 9339bb8954be..3b186eaaaa7b 100644 --- a/arch/arm/mach-exynos/common.h +++ b/arch/arm/mach-exynos/common.h | |||
| @@ -12,7 +12,7 @@ | |||
| 12 | #ifndef __ARCH_ARM_MACH_EXYNOS_COMMON_H | 12 | #ifndef __ARCH_ARM_MACH_EXYNOS_COMMON_H |
| 13 | #define __ARCH_ARM_MACH_EXYNOS_COMMON_H | 13 | #define __ARCH_ARM_MACH_EXYNOS_COMMON_H |
| 14 | 14 | ||
| 15 | extern void exynos4_timer_init(void); | 15 | extern void mct_init(void); |
| 16 | 16 | ||
| 17 | struct map_desc; | 17 | struct map_desc; |
| 18 | void exynos_init_io(struct map_desc *mach_desc, int size); | 18 | void exynos_init_io(struct map_desc *mach_desc, int size); |
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h index 1f4dc35cd4b9..c0e75d8dd737 100644 --- a/arch/arm/mach-exynos/include/mach/irqs.h +++ b/arch/arm/mach-exynos/include/mach/irqs.h | |||
| @@ -30,8 +30,6 @@ | |||
| 30 | 30 | ||
| 31 | /* For EXYNOS4 and EXYNOS5 */ | 31 | /* For EXYNOS4 and EXYNOS5 */ |
| 32 | 32 | ||
| 33 | #define EXYNOS_IRQ_MCT_LOCALTIMER IRQ_PPI(12) | ||
| 34 | |||
| 35 | #define EXYNOS_IRQ_EINT16_31 IRQ_SPI(32) | 33 | #define EXYNOS_IRQ_EINT16_31 IRQ_SPI(32) |
| 36 | 34 | ||
| 37 | /* For EXYNOS4 SoCs */ | 35 | /* For EXYNOS4 SoCs */ |
| @@ -323,8 +321,6 @@ | |||
| 323 | #define EXYNOS5_IRQ_CEC IRQ_SPI(114) | 321 | #define EXYNOS5_IRQ_CEC IRQ_SPI(114) |
| 324 | #define EXYNOS5_IRQ_SATA IRQ_SPI(115) | 322 | #define EXYNOS5_IRQ_SATA IRQ_SPI(115) |
| 325 | 323 | ||
| 326 | #define EXYNOS5_IRQ_MCT_L0 IRQ_SPI(120) | ||
| 327 | #define EXYNOS5_IRQ_MCT_L1 IRQ_SPI(121) | ||
| 328 | #define EXYNOS5_IRQ_MMC44 IRQ_SPI(123) | 324 | #define EXYNOS5_IRQ_MMC44 IRQ_SPI(123) |
| 329 | #define EXYNOS5_IRQ_MDMA1 IRQ_SPI(124) | 325 | #define EXYNOS5_IRQ_MDMA1 IRQ_SPI(124) |
| 330 | #define EXYNOS5_IRQ_FIMC_LITE0 IRQ_SPI(125) | 326 | #define EXYNOS5_IRQ_FIMC_LITE0 IRQ_SPI(125) |
| @@ -419,8 +415,6 @@ | |||
| 419 | #define EXYNOS5_IRQ_PMU_CPU1 COMBINER_IRQ(22, 4) | 415 | #define EXYNOS5_IRQ_PMU_CPU1 COMBINER_IRQ(22, 4) |
| 420 | 416 | ||
| 421 | #define EXYNOS5_IRQ_EINT0 COMBINER_IRQ(23, 0) | 417 | #define EXYNOS5_IRQ_EINT0 COMBINER_IRQ(23, 0) |
| 422 | #define EXYNOS5_IRQ_MCT_G0 COMBINER_IRQ(23, 3) | ||
| 423 | #define EXYNOS5_IRQ_MCT_G1 COMBINER_IRQ(23, 4) | ||
| 424 | 418 | ||
| 425 | #define EXYNOS5_IRQ_EINT1 COMBINER_IRQ(24, 0) | 419 | #define EXYNOS5_IRQ_EINT1 COMBINER_IRQ(24, 0) |
| 426 | #define EXYNOS5_IRQ_SYSMMU_LITE1_0 COMBINER_IRQ(24, 1) | 420 | #define EXYNOS5_IRQ_SYSMMU_LITE1_0 COMBINER_IRQ(24, 1) |
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h index 1df6abbf53b8..7f99b7b187d6 100644 --- a/arch/arm/mach-exynos/include/mach/map.h +++ b/arch/arm/mach-exynos/include/mach/map.h | |||
| @@ -65,7 +65,6 @@ | |||
| 65 | #define EXYNOS5_PA_CMU 0x10010000 | 65 | #define EXYNOS5_PA_CMU 0x10010000 |
| 66 | 66 | ||
| 67 | #define EXYNOS4_PA_SYSTIMER 0x10050000 | 67 | #define EXYNOS4_PA_SYSTIMER 0x10050000 |
| 68 | #define EXYNOS5_PA_SYSTIMER 0x101C0000 | ||
| 69 | 68 | ||
| 70 | #define EXYNOS4_PA_WATCHDOG 0x10060000 | 69 | #define EXYNOS4_PA_WATCHDOG 0x10060000 |
| 71 | #define EXYNOS5_PA_WATCHDOG 0x101D0000 | 70 | #define EXYNOS5_PA_WATCHDOG 0x101D0000 |
diff --git a/arch/arm/mach-exynos/include/mach/regs-mct.h b/arch/arm/mach-exynos/include/mach/regs-mct.h deleted file mode 100644 index 80dd02ad6d61..000000000000 --- a/arch/arm/mach-exynos/include/mach/regs-mct.h +++ /dev/null | |||
| @@ -1,53 +0,0 @@ | |||
| 1 | /* arch/arm/mach-exynos4/include/mach/regs-mct.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. | ||
| 4 | * http://www.samsung.com | ||
| 5 | * | ||
| 6 | * EXYNOS4 MCT configutation | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __ASM_ARCH_REGS_MCT_H | ||
| 14 | #define __ASM_ARCH_REGS_MCT_H __FILE__ | ||
| 15 | |||
| 16 | #include <mach/map.h> | ||
| 17 | |||
| 18 | #define EXYNOS4_MCTREG(x) (S5P_VA_SYSTIMER + (x)) | ||
| 19 | |||
| 20 | #define EXYNOS4_MCT_G_CNT_L EXYNOS4_MCTREG(0x100) | ||
| 21 | #define EXYNOS4_MCT_G_CNT_U EXYNOS4_MCTREG(0x104) | ||
| 22 | #define EXYNOS4_MCT_G_CNT_WSTAT EXYNOS4_MCTREG(0x110) | ||
| 23 | |||
| 24 | #define EXYNOS4_MCT_G_COMP0_L EXYNOS4_MCTREG(0x200) | ||
| 25 | #define EXYNOS4_MCT_G_COMP0_U EXYNOS4_MCTREG(0x204) | ||
| 26 | #define EXYNOS4_MCT_G_COMP0_ADD_INCR EXYNOS4_MCTREG(0x208) | ||
| 27 | |||
| 28 | #define EXYNOS4_MCT_G_TCON EXYNOS4_MCTREG(0x240) | ||
| 29 | |||
| 30 | #define EXYNOS4_MCT_G_INT_CSTAT EXYNOS4_MCTREG(0x244) | ||
| 31 | #define EXYNOS4_MCT_G_INT_ENB EXYNOS4_MCTREG(0x248) | ||
| 32 | #define EXYNOS4_MCT_G_WSTAT EXYNOS4_MCTREG(0x24C) | ||
| 33 | |||
| 34 | #define _EXYNOS4_MCT_L_BASE EXYNOS4_MCTREG(0x300) | ||
| 35 | #define EXYNOS4_MCT_L_BASE(x) (_EXYNOS4_MCT_L_BASE + (0x100 * x)) | ||
| 36 | #define EXYNOS4_MCT_L_MASK (0xffffff00) | ||
| 37 | |||
| 38 | #define MCT_L_TCNTB_OFFSET (0x00) | ||
| 39 | #define MCT_L_ICNTB_OFFSET (0x08) | ||
| 40 | #define MCT_L_TCON_OFFSET (0x20) | ||
| 41 | #define MCT_L_INT_CSTAT_OFFSET (0x30) | ||
| 42 | #define MCT_L_INT_ENB_OFFSET (0x34) | ||
| 43 | #define MCT_L_WSTAT_OFFSET (0x40) | ||
| 44 | |||
| 45 | #define MCT_G_TCON_START (1 << 8) | ||
| 46 | #define MCT_G_TCON_COMP0_AUTO_INC (1 << 1) | ||
| 47 | #define MCT_G_TCON_COMP0_ENABLE (1 << 0) | ||
| 48 | |||
| 49 | #define MCT_L_TCON_INTERVAL_MODE (1 << 2) | ||
| 50 | #define MCT_L_TCON_INT_START (1 << 1) | ||
| 51 | #define MCT_L_TCON_TIMER_START (1 << 0) | ||
| 52 | |||
| 53 | #endif /* __ASM_ARCH_REGS_MCT_H */ | ||
diff --git a/arch/arm/mach-exynos/mach-armlex4210.c b/arch/arm/mach-exynos/mach-armlex4210.c index 685f29173afa..3b1a34742679 100644 --- a/arch/arm/mach-exynos/mach-armlex4210.c +++ b/arch/arm/mach-exynos/mach-armlex4210.c | |||
| @@ -202,6 +202,6 @@ MACHINE_START(ARMLEX4210, "ARMLEX4210") | |||
| 202 | .map_io = armlex4210_map_io, | 202 | .map_io = armlex4210_map_io, |
| 203 | .init_machine = armlex4210_machine_init, | 203 | .init_machine = armlex4210_machine_init, |
| 204 | .init_late = exynos_init_late, | 204 | .init_late = exynos_init_late, |
| 205 | .init_time = exynos4_timer_init, | 205 | .init_time = mct_init, |
| 206 | .restart = exynos4_restart, | 206 | .restart = exynos4_restart, |
| 207 | MACHINE_END | 207 | MACHINE_END |
diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c b/arch/arm/mach-exynos/mach-exynos4-dt.c index 3358088c822a..c4ae108e192d 100644 --- a/arch/arm/mach-exynos/mach-exynos4-dt.c +++ b/arch/arm/mach-exynos/mach-exynos4-dt.c | |||
| @@ -13,6 +13,7 @@ | |||
| 13 | 13 | ||
| 14 | #include <linux/of_platform.h> | 14 | #include <linux/of_platform.h> |
| 15 | #include <linux/serial_core.h> | 15 | #include <linux/serial_core.h> |
| 16 | #include <linux/clocksource.h> | ||
| 16 | 17 | ||
| 17 | #include <asm/mach/arch.h> | 18 | #include <asm/mach/arch.h> |
| 18 | #include <mach/map.h> | 19 | #include <mach/map.h> |
| @@ -142,7 +143,7 @@ DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened Device Tree)") | |||
| 142 | .map_io = exynos4_dt_map_io, | 143 | .map_io = exynos4_dt_map_io, |
| 143 | .init_machine = exynos4_dt_machine_init, | 144 | .init_machine = exynos4_dt_machine_init, |
| 144 | .init_late = exynos_init_late, | 145 | .init_late = exynos_init_late, |
| 145 | .init_time = exynos4_timer_init, | 146 | .init_time = clocksource_of_init, |
| 146 | .dt_compat = exynos4_dt_compat, | 147 | .dt_compat = exynos4_dt_compat, |
| 147 | .restart = exynos4_restart, | 148 | .restart = exynos4_restart, |
| 148 | MACHINE_END | 149 | MACHINE_END |
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c index acaeb14db54b..be7eaac0df01 100644 --- a/arch/arm/mach-exynos/mach-exynos5-dt.c +++ b/arch/arm/mach-exynos/mach-exynos5-dt.c | |||
| @@ -14,6 +14,7 @@ | |||
| 14 | #include <linux/serial_core.h> | 14 | #include <linux/serial_core.h> |
| 15 | #include <linux/memblock.h> | 15 | #include <linux/memblock.h> |
| 16 | #include <linux/io.h> | 16 | #include <linux/io.h> |
| 17 | #include <linux/clocksource.h> | ||
| 17 | 18 | ||
| 18 | #include <asm/mach/arch.h> | 19 | #include <asm/mach/arch.h> |
| 19 | #include <mach/map.h> | 20 | #include <mach/map.h> |
| @@ -216,7 +217,6 @@ DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)") | |||
| 216 | .map_io = exynos5_dt_map_io, | 217 | .map_io = exynos5_dt_map_io, |
| 217 | .init_machine = exynos5_dt_machine_init, | 218 | .init_machine = exynos5_dt_machine_init, |
| 218 | .init_late = exynos_init_late, | 219 | .init_late = exynos_init_late, |
| 219 | .init_time = exynos4_timer_init, | ||
| 220 | .dt_compat = exynos5_dt_compat, | 220 | .dt_compat = exynos5_dt_compat, |
| 221 | .restart = exynos5_restart, | 221 | .restart = exynos5_restart, |
| 222 | .reserve = exynos5_reserve, | 222 | .reserve = exynos5_reserve, |
diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c index 1ea79730187f..da3605d15110 100644 --- a/arch/arm/mach-exynos/mach-nuri.c +++ b/arch/arm/mach-exynos/mach-nuri.c | |||
| @@ -1380,7 +1380,7 @@ MACHINE_START(NURI, "NURI") | |||
| 1380 | .map_io = nuri_map_io, | 1380 | .map_io = nuri_map_io, |
| 1381 | .init_machine = nuri_machine_init, | 1381 | .init_machine = nuri_machine_init, |
| 1382 | .init_late = exynos_init_late, | 1382 | .init_late = exynos_init_late, |
| 1383 | .init_time = exynos4_timer_init, | 1383 | .init_time = mct_init, |
| 1384 | .reserve = &nuri_reserve, | 1384 | .reserve = &nuri_reserve, |
| 1385 | .restart = exynos4_restart, | 1385 | .restart = exynos4_restart, |
| 1386 | MACHINE_END | 1386 | MACHINE_END |
diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c index 579d2d171daa..1772cd284f4c 100644 --- a/arch/arm/mach-exynos/mach-origen.c +++ b/arch/arm/mach-exynos/mach-origen.c | |||
| @@ -815,7 +815,7 @@ MACHINE_START(ORIGEN, "ORIGEN") | |||
| 815 | .map_io = origen_map_io, | 815 | .map_io = origen_map_io, |
| 816 | .init_machine = origen_machine_init, | 816 | .init_machine = origen_machine_init, |
| 817 | .init_late = exynos_init_late, | 817 | .init_late = exynos_init_late, |
| 818 | .init_time = exynos4_timer_init, | 818 | .init_time = mct_init, |
| 819 | .reserve = &origen_reserve, | 819 | .reserve = &origen_reserve, |
| 820 | .restart = exynos4_restart, | 820 | .restart = exynos4_restart, |
| 821 | MACHINE_END | 821 | MACHINE_END |
diff --git a/arch/arm/mach-exynos/mach-smdk4x12.c b/arch/arm/mach-exynos/mach-smdk4x12.c index fe6149624b84..34a6356364eb 100644 --- a/arch/arm/mach-exynos/mach-smdk4x12.c +++ b/arch/arm/mach-exynos/mach-smdk4x12.c | |||
| @@ -376,7 +376,7 @@ MACHINE_START(SMDK4212, "SMDK4212") | |||
| 376 | .init_irq = exynos4_init_irq, | 376 | .init_irq = exynos4_init_irq, |
| 377 | .map_io = smdk4x12_map_io, | 377 | .map_io = smdk4x12_map_io, |
| 378 | .init_machine = smdk4x12_machine_init, | 378 | .init_machine = smdk4x12_machine_init, |
| 379 | .init_time = exynos4_timer_init, | 379 | .init_time = mct_init, |
| 380 | .restart = exynos4_restart, | 380 | .restart = exynos4_restart, |
| 381 | .reserve = &smdk4x12_reserve, | 381 | .reserve = &smdk4x12_reserve, |
| 382 | MACHINE_END | 382 | MACHINE_END |
| @@ -390,7 +390,7 @@ MACHINE_START(SMDK4412, "SMDK4412") | |||
| 390 | .map_io = smdk4x12_map_io, | 390 | .map_io = smdk4x12_map_io, |
| 391 | .init_machine = smdk4x12_machine_init, | 391 | .init_machine = smdk4x12_machine_init, |
| 392 | .init_late = exynos_init_late, | 392 | .init_late = exynos_init_late, |
| 393 | .init_time = exynos4_timer_init, | 393 | .init_time = mct_init, |
| 394 | .restart = exynos4_restart, | 394 | .restart = exynos4_restart, |
| 395 | .reserve = &smdk4x12_reserve, | 395 | .reserve = &smdk4x12_reserve, |
| 396 | MACHINE_END | 396 | MACHINE_END |
diff --git a/arch/arm/mach-exynos/mach-smdkv310.c b/arch/arm/mach-exynos/mach-smdkv310.c index d71672922b19..893b14e8c62a 100644 --- a/arch/arm/mach-exynos/mach-smdkv310.c +++ b/arch/arm/mach-exynos/mach-smdkv310.c | |||
| @@ -423,7 +423,7 @@ MACHINE_START(SMDKV310, "SMDKV310") | |||
| 423 | .init_irq = exynos4_init_irq, | 423 | .init_irq = exynos4_init_irq, |
| 424 | .map_io = smdkv310_map_io, | 424 | .map_io = smdkv310_map_io, |
| 425 | .init_machine = smdkv310_machine_init, | 425 | .init_machine = smdkv310_machine_init, |
| 426 | .init_time = exynos4_timer_init, | 426 | .init_time = mct_init, |
| 427 | .reserve = &smdkv310_reserve, | 427 | .reserve = &smdkv310_reserve, |
| 428 | .restart = exynos4_restart, | 428 | .restart = exynos4_restart, |
| 429 | MACHINE_END | 429 | MACHINE_END |
| @@ -436,7 +436,7 @@ MACHINE_START(SMDKC210, "SMDKC210") | |||
| 436 | .map_io = smdkv310_map_io, | 436 | .map_io = smdkv310_map_io, |
| 437 | .init_machine = smdkv310_machine_init, | 437 | .init_machine = smdkv310_machine_init, |
| 438 | .init_late = exynos_init_late, | 438 | .init_late = exynos_init_late, |
| 439 | .init_time = exynos4_timer_init, | 439 | .init_time = mct_init, |
| 440 | .reserve = &smdkv310_reserve, | 440 | .reserve = &smdkv310_reserve, |
| 441 | .restart = exynos4_restart, | 441 | .restart = exynos4_restart, |
| 442 | MACHINE_END | 442 | MACHINE_END |
diff --git a/arch/arm/mach-exynos/mct.c b/arch/arm/mach-exynos/mct.c deleted file mode 100644 index c9d6650f9b5d..000000000000 --- a/arch/arm/mach-exynos/mct.c +++ /dev/null | |||
| @@ -1,485 +0,0 @@ | |||
| 1 | /* linux/arch/arm/mach-exynos4/mct.c | ||
| 2 | * | ||
| 3 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. | ||
| 4 | * http://www.samsung.com | ||
| 5 | * | ||
| 6 | * EXYNOS4 MCT(Multi-Core Timer) support | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #include <linux/sched.h> | ||
| 14 | #include <linux/interrupt.h> | ||
| 15 | #include <linux/irq.h> | ||
| 16 | #include <linux/err.h> | ||
| 17 | #include <linux/clk.h> | ||
| 18 | #include <linux/clockchips.h> | ||
| 19 | #include <linux/platform_device.h> | ||
| 20 | #include <linux/delay.h> | ||
| 21 | #include <linux/percpu.h> | ||
| 22 | #include <linux/of.h> | ||
| 23 | |||
| 24 | #include <asm/arch_timer.h> | ||
| 25 | #include <asm/localtimer.h> | ||
| 26 | |||
| 27 | #include <plat/cpu.h> | ||
| 28 | |||
| 29 | #include <mach/map.h> | ||
| 30 | #include <mach/irqs.h> | ||
| 31 | #include <mach/regs-mct.h> | ||
| 32 | #include <asm/mach/time.h> | ||
| 33 | |||
| 34 | #define TICK_BASE_CNT 1 | ||
| 35 | |||
| 36 | enum { | ||
| 37 | MCT_INT_SPI, | ||
| 38 | MCT_INT_PPI | ||
| 39 | }; | ||
| 40 | |||
| 41 | static unsigned long clk_rate; | ||
| 42 | static unsigned int mct_int_type; | ||
| 43 | |||
| 44 | struct mct_clock_event_device { | ||
| 45 | struct clock_event_device *evt; | ||
| 46 | void __iomem *base; | ||
| 47 | char name[10]; | ||
| 48 | }; | ||
| 49 | |||
| 50 | static void exynos4_mct_write(unsigned int value, void *addr) | ||
| 51 | { | ||
| 52 | void __iomem *stat_addr; | ||
| 53 | u32 mask; | ||
| 54 | u32 i; | ||
| 55 | |||
| 56 | __raw_writel(value, addr); | ||
| 57 | |||
| 58 | if (likely(addr >= EXYNOS4_MCT_L_BASE(0))) { | ||
| 59 | u32 base = (u32) addr & EXYNOS4_MCT_L_MASK; | ||
| 60 | switch ((u32) addr & ~EXYNOS4_MCT_L_MASK) { | ||
| 61 | case (u32) MCT_L_TCON_OFFSET: | ||
| 62 | stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET; | ||
| 63 | mask = 1 << 3; /* L_TCON write status */ | ||
| 64 | break; | ||
| 65 | case (u32) MCT_L_ICNTB_OFFSET: | ||
| 66 | stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET; | ||
| 67 | mask = 1 << 1; /* L_ICNTB write status */ | ||
| 68 | break; | ||
| 69 | case (u32) MCT_L_TCNTB_OFFSET: | ||
| 70 | stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET; | ||
| 71 | mask = 1 << 0; /* L_TCNTB write status */ | ||
| 72 | break; | ||
| 73 | default: | ||
| 74 | return; | ||
| 75 | } | ||
| 76 | } else { | ||
| 77 | switch ((u32) addr) { | ||
| 78 | case (u32) EXYNOS4_MCT_G_TCON: | ||
| 79 | stat_addr = EXYNOS4_MCT_G_WSTAT; | ||
| 80 | mask = 1 << 16; /* G_TCON write status */ | ||
| 81 | break; | ||
| 82 | case (u32) EXYNOS4_MCT_G_COMP0_L: | ||
| 83 | stat_addr = EXYNOS4_MCT_G_WSTAT; | ||
| 84 | mask = 1 << 0; /* G_COMP0_L write status */ | ||
| 85 | break; | ||
| 86 | case (u32) EXYNOS4_MCT_G_COMP0_U: | ||
| 87 | stat_addr = EXYNOS4_MCT_G_WSTAT; | ||
| 88 | mask = 1 << 1; /* G_COMP0_U write status */ | ||
| 89 | break; | ||
| 90 | case (u32) EXYNOS4_MCT_G_COMP0_ADD_INCR: | ||
| 91 | stat_addr = EXYNOS4_MCT_G_WSTAT; | ||
| 92 | mask = 1 << 2; /* G_COMP0_ADD_INCR w status */ | ||
| 93 | break; | ||
| 94 | case (u32) EXYNOS4_MCT_G_CNT_L: | ||
| 95 | stat_addr = EXYNOS4_MCT_G_CNT_WSTAT; | ||
| 96 | mask = 1 << 0; /* G_CNT_L write status */ | ||
| 97 | break; | ||
| 98 | case (u32) EXYNOS4_MCT_G_CNT_U: | ||
| 99 | stat_addr = EXYNOS4_MCT_G_CNT_WSTAT; | ||
| 100 | mask = 1 << 1; /* G_CNT_U write status */ | ||
| 101 | break; | ||
| 102 | default: | ||
| 103 | return; | ||
| 104 | } | ||
| 105 | } | ||
| 106 | |||
| 107 | /* Wait maximum 1 ms until written values are applied */ | ||
| 108 | for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++) | ||
| 109 | if (__raw_readl(stat_addr) & mask) { | ||
| 110 | __raw_writel(mask, stat_addr); | ||
| 111 | return; | ||
| 112 | } | ||
| 113 | |||
| 114 | panic("MCT hangs after writing %d (addr:0x%08x)\n", value, (u32)addr); | ||
| 115 | } | ||
| 116 | |||
| 117 | /* Clocksource handling */ | ||
| 118 | static void exynos4_mct_frc_start(u32 hi, u32 lo) | ||
| 119 | { | ||
| 120 | u32 reg; | ||
| 121 | |||
| 122 | exynos4_mct_write(lo, EXYNOS4_MCT_G_CNT_L); | ||
| 123 | exynos4_mct_write(hi, EXYNOS4_MCT_G_CNT_U); | ||
| 124 | |||
| 125 | reg = __raw_readl(EXYNOS4_MCT_G_TCON); | ||
| 126 | reg |= MCT_G_TCON_START; | ||
| 127 | exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON); | ||
| 128 | } | ||
| 129 | |||
| 130 | static cycle_t exynos4_frc_read(struct clocksource *cs) | ||
| 131 | { | ||
| 132 | unsigned int lo, hi; | ||
| 133 | u32 hi2 = __raw_readl(EXYNOS4_MCT_G_CNT_U); | ||
| 134 | |||
| 135 | do { | ||
| 136 | hi = hi2; | ||
| 137 | lo = __raw_readl(EXYNOS4_MCT_G_CNT_L); | ||
| 138 | hi2 = __raw_readl(EXYNOS4_MCT_G_CNT_U); | ||
| 139 | } while (hi != hi2); | ||
| 140 | |||
| 141 | return ((cycle_t)hi << 32) | lo; | ||
| 142 | } | ||
| 143 | |||
| 144 | static void exynos4_frc_resume(struct clocksource *cs) | ||
| 145 | { | ||
| 146 | exynos4_mct_frc_start(0, 0); | ||
| 147 | } | ||
| 148 | |||
| 149 | struct clocksource mct_frc = { | ||
| 150 | .name = "mct-frc", | ||
| 151 | .rating = 400, | ||
| 152 | .read = exynos4_frc_read, | ||
| 153 | .mask = CLOCKSOURCE_MASK(64), | ||
| 154 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | ||
| 155 | .resume = exynos4_frc_resume, | ||
| 156 | }; | ||
| 157 | |||
| 158 | static void __init exynos4_clocksource_init(void) | ||
| 159 | { | ||
| 160 | exynos4_mct_frc_start(0, 0); | ||
| 161 | |||
| 162 | if (clocksource_register_hz(&mct_frc, clk_rate)) | ||
| 163 | panic("%s: can't register clocksource\n", mct_frc.name); | ||
| 164 | } | ||
| 165 | |||
| 166 | static void exynos4_mct_comp0_stop(void) | ||
| 167 | { | ||
| 168 | unsigned int tcon; | ||
| 169 | |||
| 170 | tcon = __raw_readl(EXYNOS4_MCT_G_TCON); | ||
| 171 | tcon &= ~(MCT_G_TCON_COMP0_ENABLE | MCT_G_TCON_COMP0_AUTO_INC); | ||
| 172 | |||
| 173 | exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON); | ||
| 174 | exynos4_mct_write(0, EXYNOS4_MCT_G_INT_ENB); | ||
| 175 | } | ||
| 176 | |||
| 177 | static void exynos4_mct_comp0_start(enum clock_event_mode mode, | ||
| 178 | unsigned long cycles) | ||
| 179 | { | ||
| 180 | unsigned int tcon; | ||
| 181 | cycle_t comp_cycle; | ||
| 182 | |||
| 183 | tcon = __raw_readl(EXYNOS4_MCT_G_TCON); | ||
| 184 | |||
| 185 | if (mode == CLOCK_EVT_MODE_PERIODIC) { | ||
| 186 | tcon |= MCT_G_TCON_COMP0_AUTO_INC; | ||
| 187 | exynos4_mct_write(cycles, EXYNOS4_MCT_G_COMP0_ADD_INCR); | ||
| 188 | } | ||
| 189 | |||
| 190 | comp_cycle = exynos4_frc_read(&mct_frc) + cycles; | ||
| 191 | exynos4_mct_write((u32)comp_cycle, EXYNOS4_MCT_G_COMP0_L); | ||
| 192 | exynos4_mct_write((u32)(comp_cycle >> 32), EXYNOS4_MCT_G_COMP0_U); | ||
| 193 | |||
| 194 | exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_ENB); | ||
| 195 | |||
| 196 | tcon |= MCT_G_TCON_COMP0_ENABLE; | ||
| 197 | exynos4_mct_write(tcon , EXYNOS4_MCT_G_TCON); | ||
| 198 | } | ||
| 199 | |||
| 200 | static int exynos4_comp_set_next_event(unsigned long cycles, | ||
| 201 | struct clock_event_device *evt) | ||
| 202 | { | ||
| 203 | exynos4_mct_comp0_start(evt->mode, cycles); | ||
| 204 | |||
| 205 | return 0; | ||
| 206 | } | ||
| 207 | |||
| 208 | static void exynos4_comp_set_mode(enum clock_event_mode mode, | ||
| 209 | struct clock_event_device *evt) | ||
| 210 | { | ||
| 211 | unsigned long cycles_per_jiffy; | ||
| 212 | exynos4_mct_comp0_stop(); | ||
| 213 | |||
| 214 | switch (mode) { | ||
| 215 | case CLOCK_EVT_MODE_PERIODIC: | ||
| 216 | cycles_per_jiffy = | ||
| 217 | (((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift); | ||
| 218 | exynos4_mct_comp0_start(mode, cycles_per_jiffy); | ||
| 219 | break; | ||
| 220 | |||
| 221 | case CLOCK_EVT_MODE_ONESHOT: | ||
| 222 | case CLOCK_EVT_MODE_UNUSED: | ||
| 223 | case CLOCK_EVT_MODE_SHUTDOWN: | ||
| 224 | case CLOCK_EVT_MODE_RESUME: | ||
| 225 | break; | ||
| 226 | } | ||
| 227 | } | ||
| 228 | |||
| 229 | static struct clock_event_device mct_comp_device = { | ||
| 230 | .name = "mct-comp", | ||
| 231 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, | ||
| 232 | .rating = 250, | ||
| 233 | .set_next_event = exynos4_comp_set_next_event, | ||
| 234 | .set_mode = exynos4_comp_set_mode, | ||
| 235 | }; | ||
| 236 | |||
| 237 | static irqreturn_t exynos4_mct_comp_isr(int irq, void *dev_id) | ||
| 238 | { | ||
| 239 | struct clock_event_device *evt = dev_id; | ||
| 240 | |||
| 241 | exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_CSTAT); | ||
| 242 | |||
| 243 | evt->event_handler(evt); | ||
| 244 | |||
| 245 | return IRQ_HANDLED; | ||
| 246 | } | ||
| 247 | |||
| 248 | static struct irqaction mct_comp_event_irq = { | ||
| 249 | .name = "mct_comp_irq", | ||
| 250 | .flags = IRQF_TIMER | IRQF_IRQPOLL, | ||
| 251 | .handler = exynos4_mct_comp_isr, | ||
| 252 | .dev_id = &mct_comp_device, | ||
| 253 | }; | ||
| 254 | |||
| 255 | static void exynos4_clockevent_init(void) | ||
| 256 | { | ||
| 257 | mct_comp_device.cpumask = cpumask_of(0); | ||
| 258 | clockevents_config_and_register(&mct_comp_device, clk_rate, | ||
| 259 | 0xf, 0xffffffff); | ||
| 260 | |||
| 261 | if (soc_is_exynos5250()) | ||
| 262 | setup_irq(EXYNOS5_IRQ_MCT_G0, &mct_comp_event_irq); | ||
| 263 | else | ||
| 264 | setup_irq(EXYNOS4_IRQ_MCT_G0, &mct_comp_event_irq); | ||
| 265 | } | ||
| 266 | |||
| 267 | #ifdef CONFIG_LOCAL_TIMERS | ||
| 268 | |||
| 269 | static DEFINE_PER_CPU(struct mct_clock_event_device, percpu_mct_tick); | ||
| 270 | |||
| 271 | /* Clock event handling */ | ||
| 272 | static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt) | ||
| 273 | { | ||
| 274 | unsigned long tmp; | ||
| 275 | unsigned long mask = MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START; | ||
| 276 | void __iomem *addr = mevt->base + MCT_L_TCON_OFFSET; | ||
| 277 | |||
| 278 | tmp = __raw_readl(addr); | ||
| 279 | if (tmp & mask) { | ||
| 280 | tmp &= ~mask; | ||
| 281 | exynos4_mct_write(tmp, addr); | ||
| 282 | } | ||
| 283 | } | ||
| 284 | |||
| 285 | static void exynos4_mct_tick_start(unsigned long cycles, | ||
| 286 | struct mct_clock_event_device *mevt) | ||
| 287 | { | ||
| 288 | unsigned long tmp; | ||
| 289 | |||
| 290 | exynos4_mct_tick_stop(mevt); | ||
| 291 | |||
| 292 | tmp = (1 << 31) | cycles; /* MCT_L_UPDATE_ICNTB */ | ||
| 293 | |||
| 294 | /* update interrupt count buffer */ | ||
| 295 | exynos4_mct_write(tmp, mevt->base + MCT_L_ICNTB_OFFSET); | ||
| 296 | |||
| 297 | /* enable MCT tick interrupt */ | ||
| 298 | exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET); | ||
| 299 | |||
| 300 | tmp = __raw_readl(mevt->base + MCT_L_TCON_OFFSET); | ||
| 301 | tmp |= MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START | | ||
| 302 | MCT_L_TCON_INTERVAL_MODE; | ||
| 303 | exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET); | ||
| 304 | } | ||
| 305 | |||
| 306 | static int exynos4_tick_set_next_event(unsigned long cycles, | ||
| 307 | struct clock_event_device *evt) | ||
| 308 | { | ||
| 309 | struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick); | ||
| 310 | |||
| 311 | exynos4_mct_tick_start(cycles, mevt); | ||
| 312 | |||
| 313 | return 0; | ||
| 314 | } | ||
| 315 | |||
| 316 | static inline void exynos4_tick_set_mode(enum clock_event_mode mode, | ||
| 317 | struct clock_event_device *evt) | ||
| 318 | { | ||
| 319 | struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick); | ||
| 320 | unsigned long cycles_per_jiffy; | ||
| 321 | |||
| 322 | exynos4_mct_tick_stop(mevt); | ||
| 323 | |||
| 324 | switch (mode) { | ||
| 325 | case CLOCK_EVT_MODE_PERIODIC: | ||
| 326 | cycles_per_jiffy = | ||
| 327 | (((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift); | ||
| 328 | exynos4_mct_tick_start(cycles_per_jiffy, mevt); | ||
| 329 | break; | ||
| 330 | |||
| 331 | case CLOCK_EVT_MODE_ONESHOT: | ||
| 332 | case CLOCK_EVT_MODE_UNUSED: | ||
| 333 | case CLOCK_EVT_MODE_SHUTDOWN: | ||
| 334 | case CLOCK_EVT_MODE_RESUME: | ||
| 335 | break; | ||
| 336 | } | ||
| 337 | } | ||
| 338 | |||
| 339 | static int exynos4_mct_tick_clear(struct mct_clock_event_device *mevt) | ||
| 340 | { | ||
| 341 | struct clock_event_device *evt = mevt->evt; | ||
| 342 | |||
| 343 | /* | ||
| 344 | * This is for supporting oneshot mode. | ||
| 345 | * Mct would generate interrupt periodically | ||
| 346 | * without explicit stopping. | ||
| 347 | */ | ||
| 348 | if (evt->mode != CLOCK_EVT_MODE_PERIODIC) | ||
| 349 | exynos4_mct_tick_stop(mevt); | ||
| 350 | |||
| 351 | /* Clear the MCT tick interrupt */ | ||
| 352 | if (__raw_readl(mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) { | ||
| 353 | exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET); | ||
| 354 | return 1; | ||
| 355 | } else { | ||
| 356 | return 0; | ||
| 357 | } | ||
| 358 | } | ||
| 359 | |||
| 360 | static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id) | ||
| 361 | { | ||
| 362 | struct mct_clock_event_device *mevt = dev_id; | ||
| 363 | struct clock_event_device *evt = mevt->evt; | ||
| 364 | |||
| 365 | exynos4_mct_tick_clear(mevt); | ||
| 366 | |||
| 367 | evt->event_handler(evt); | ||
| 368 | |||
| 369 | return IRQ_HANDLED; | ||
| 370 | } | ||
| 371 | |||
| 372 | static struct irqaction mct_tick0_event_irq = { | ||
| 373 | .name = "mct_tick0_irq", | ||
| 374 | .flags = IRQF_TIMER | IRQF_NOBALANCING, | ||
| 375 | .handler = exynos4_mct_tick_isr, | ||
| 376 | }; | ||
| 377 | |||
| 378 | static struct irqaction mct_tick1_event_irq = { | ||
| 379 | .name = "mct_tick1_irq", | ||
| 380 | .flags = IRQF_TIMER | IRQF_NOBALANCING, | ||
| 381 | .handler = exynos4_mct_tick_isr, | ||
| 382 | }; | ||
| 383 | |||
| 384 | static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt) | ||
| 385 | { | ||
| 386 | struct mct_clock_event_device *mevt; | ||
| 387 | unsigned int cpu = smp_processor_id(); | ||
| 388 | int mct_lx_irq; | ||
| 389 | |||
| 390 | mevt = this_cpu_ptr(&percpu_mct_tick); | ||
| 391 | mevt->evt = evt; | ||
| 392 | |||
| 393 | mevt->base = EXYNOS4_MCT_L_BASE(cpu); | ||
| 394 | sprintf(mevt->name, "mct_tick%d", cpu); | ||
| 395 | |||
| 396 | evt->name = mevt->name; | ||
| 397 | evt->cpumask = cpumask_of(cpu); | ||
| 398 | evt->set_next_event = exynos4_tick_set_next_event; | ||
| 399 | evt->set_mode = exynos4_tick_set_mode; | ||
| 400 | evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; | ||
| 401 | evt->rating = 450; | ||
| 402 | clockevents_config_and_register(evt, clk_rate / (TICK_BASE_CNT + 1), | ||
| 403 | 0xf, 0x7fffffff); | ||
| 404 | |||
| 405 | exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET); | ||
| 406 | |||
| 407 | if (mct_int_type == MCT_INT_SPI) { | ||
| 408 | if (cpu == 0) { | ||
| 409 | mct_lx_irq = soc_is_exynos4210() ? EXYNOS4_IRQ_MCT_L0 : | ||
| 410 | EXYNOS5_IRQ_MCT_L0; | ||
| 411 | mct_tick0_event_irq.dev_id = mevt; | ||
| 412 | evt->irq = mct_lx_irq; | ||
| 413 | setup_irq(mct_lx_irq, &mct_tick0_event_irq); | ||
| 414 | } else { | ||
| 415 | mct_lx_irq = soc_is_exynos4210() ? EXYNOS4_IRQ_MCT_L1 : | ||
| 416 | EXYNOS5_IRQ_MCT_L1; | ||
| 417 | mct_tick1_event_irq.dev_id = mevt; | ||
| 418 | evt->irq = mct_lx_irq; | ||
| 419 | setup_irq(mct_lx_irq, &mct_tick1_event_irq); | ||
| 420 | irq_set_affinity(mct_lx_irq, cpumask_of(1)); | ||
| 421 | } | ||
| 422 | } else { | ||
| 423 | enable_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER, 0); | ||
| 424 | } | ||
| 425 | |||
| 426 | return 0; | ||
| 427 | } | ||
| 428 | |||
| 429 | static void exynos4_local_timer_stop(struct clock_event_device *evt) | ||
| 430 | { | ||
| 431 | unsigned int cpu = smp_processor_id(); | ||
| 432 | evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt); | ||
| 433 | if (mct_int_type == MCT_INT_SPI) | ||
| 434 | if (cpu == 0) | ||
| 435 | remove_irq(evt->irq, &mct_tick0_event_irq); | ||
| 436 | else | ||
| 437 | remove_irq(evt->irq, &mct_tick1_event_irq); | ||
| 438 | else | ||
| 439 | disable_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER); | ||
| 440 | } | ||
| 441 | |||
| 442 | static struct local_timer_ops exynos4_mct_tick_ops __cpuinitdata = { | ||
| 443 | .setup = exynos4_local_timer_setup, | ||
| 444 | .stop = exynos4_local_timer_stop, | ||
| 445 | }; | ||
| 446 | #endif /* CONFIG_LOCAL_TIMERS */ | ||
| 447 | |||
| 448 | static void __init exynos4_timer_resources(void) | ||
| 449 | { | ||
| 450 | struct clk *mct_clk; | ||
| 451 | mct_clk = clk_get(NULL, "xtal"); | ||
| 452 | |||
| 453 | clk_rate = clk_get_rate(mct_clk); | ||
| 454 | |||
| 455 | #ifdef CONFIG_LOCAL_TIMERS | ||
| 456 | if (mct_int_type == MCT_INT_PPI) { | ||
| 457 | int err; | ||
| 458 | |||
| 459 | err = request_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER, | ||
| 460 | exynos4_mct_tick_isr, "MCT", | ||
| 461 | &percpu_mct_tick); | ||
| 462 | WARN(err, "MCT: can't request IRQ %d (%d)\n", | ||
| 463 | EXYNOS_IRQ_MCT_LOCALTIMER, err); | ||
| 464 | } | ||
| 465 | |||
| 466 | local_timer_register(&exynos4_mct_tick_ops); | ||
| 467 | #endif /* CONFIG_LOCAL_TIMERS */ | ||
| 468 | } | ||
| 469 | |||
| 470 | void __init exynos4_timer_init(void) | ||
| 471 | { | ||
| 472 | if (soc_is_exynos5440()) { | ||
| 473 | arch_timer_of_register(); | ||
| 474 | return; | ||
| 475 | } | ||
| 476 | |||
| 477 | if ((soc_is_exynos4210()) || (soc_is_exynos5250())) | ||
| 478 | mct_int_type = MCT_INT_SPI; | ||
| 479 | else | ||
| 480 | mct_int_type = MCT_INT_PPI; | ||
| 481 | |||
| 482 | exynos4_timer_resources(); | ||
| 483 | exynos4_clocksource_init(); | ||
| 484 | exynos4_clockevent_init(); | ||
| 485 | } | ||
diff --git a/arch/arm/mach-highbank/highbank.c b/arch/arm/mach-highbank/highbank.c index 76c1170b3528..e7df2dd43a40 100644 --- a/arch/arm/mach-highbank/highbank.c +++ b/arch/arm/mach-highbank/highbank.c | |||
| @@ -15,6 +15,7 @@ | |||
| 15 | */ | 15 | */ |
| 16 | #include <linux/clk.h> | 16 | #include <linux/clk.h> |
| 17 | #include <linux/clkdev.h> | 17 | #include <linux/clkdev.h> |
| 18 | #include <linux/clocksource.h> | ||
| 18 | #include <linux/dma-mapping.h> | 19 | #include <linux/dma-mapping.h> |
| 19 | #include <linux/io.h> | 20 | #include <linux/io.h> |
| 20 | #include <linux/irq.h> | 21 | #include <linux/irq.h> |
| @@ -28,12 +29,9 @@ | |||
| 28 | #include <linux/amba/bus.h> | 29 | #include <linux/amba/bus.h> |
| 29 | #include <linux/clk-provider.h> | 30 | #include <linux/clk-provider.h> |
| 30 | 31 | ||
| 31 | #include <asm/arch_timer.h> | ||
| 32 | #include <asm/cacheflush.h> | 32 | #include <asm/cacheflush.h> |
| 33 | #include <asm/cputype.h> | 33 | #include <asm/cputype.h> |
| 34 | #include <asm/smp_plat.h> | 34 | #include <asm/smp_plat.h> |
| 35 | #include <asm/hardware/arm_timer.h> | ||
| 36 | #include <asm/hardware/timer-sp.h> | ||
| 37 | #include <asm/hardware/cache-l2x0.h> | 35 | #include <asm/hardware/cache-l2x0.h> |
| 38 | #include <asm/mach/arch.h> | 36 | #include <asm/mach/arch.h> |
| 39 | #include <asm/mach/map.h> | 37 | #include <asm/mach/map.h> |
| @@ -90,36 +88,16 @@ static void __init highbank_init_irq(void) | |||
| 90 | #endif | 88 | #endif |
| 91 | } | 89 | } |
| 92 | 90 | ||
| 93 | static struct clk_lookup lookup = { | ||
| 94 | .dev_id = "sp804", | ||
| 95 | .con_id = NULL, | ||
| 96 | }; | ||
| 97 | |||
| 98 | static void __init highbank_timer_init(void) | 91 | static void __init highbank_timer_init(void) |
| 99 | { | 92 | { |
| 100 | int irq; | ||
| 101 | struct device_node *np; | 93 | struct device_node *np; |
| 102 | void __iomem *timer_base; | ||
| 103 | 94 | ||
| 104 | /* Map system registers */ | 95 | /* Map system registers */ |
| 105 | np = of_find_compatible_node(NULL, NULL, "calxeda,hb-sregs"); | 96 | np = of_find_compatible_node(NULL, NULL, "calxeda,hb-sregs"); |
| 106 | sregs_base = of_iomap(np, 0); | 97 | sregs_base = of_iomap(np, 0); |
| 107 | WARN_ON(!sregs_base); | 98 | WARN_ON(!sregs_base); |
| 108 | 99 | ||
| 109 | np = of_find_compatible_node(NULL, NULL, "arm,sp804"); | ||
| 110 | timer_base = of_iomap(np, 0); | ||
| 111 | WARN_ON(!timer_base); | ||
| 112 | irq = irq_of_parse_and_map(np, 0); | ||
| 113 | |||
| 114 | of_clk_init(NULL); | 100 | of_clk_init(NULL); |
| 115 | lookup.clk = of_clk_get(np, 0); | ||
| 116 | clkdev_add(&lookup); | ||
| 117 | |||
| 118 | sp804_clocksource_and_sched_clock_init(timer_base + 0x20, "timer1"); | ||
| 119 | sp804_clockevents_init(timer_base, irq, "timer0"); | ||
| 120 | |||
| 121 | arch_timer_of_register(); | ||
| 122 | arch_timer_sched_clock_init(); | ||
| 123 | 101 | ||
| 124 | clocksource_of_init(); | 102 | clocksource_of_init(); |
| 125 | } | 103 | } |
diff --git a/arch/arm/mach-imx/clk-busy.c b/arch/arm/mach-imx/clk-busy.c index 1ab91b5209e6..85b728cc27ab 100644 --- a/arch/arm/mach-imx/clk-busy.c +++ b/arch/arm/mach-imx/clk-busy.c | |||
| @@ -169,7 +169,7 @@ struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift, | |||
| 169 | 169 | ||
| 170 | busy->mux.reg = reg; | 170 | busy->mux.reg = reg; |
| 171 | busy->mux.shift = shift; | 171 | busy->mux.shift = shift; |
| 172 | busy->mux.width = width; | 172 | busy->mux.mask = BIT(width) - 1; |
| 173 | busy->mux.lock = &imx_ccm_lock; | 173 | busy->mux.lock = &imx_ccm_lock; |
| 174 | busy->mux_ops = &clk_mux_ops; | 174 | busy->mux_ops = &clk_mux_ops; |
| 175 | 175 | ||
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h index 5a800bfcec5b..5bf4a97ab241 100644 --- a/arch/arm/mach-imx/common.h +++ b/arch/arm/mach-imx/common.h | |||
| @@ -110,6 +110,8 @@ void tzic_handle_irq(struct pt_regs *); | |||
| 110 | 110 | ||
| 111 | extern void imx_enable_cpu(int cpu, bool enable); | 111 | extern void imx_enable_cpu(int cpu, bool enable); |
| 112 | extern void imx_set_cpu_jump(int cpu, void *jump_addr); | 112 | extern void imx_set_cpu_jump(int cpu, void *jump_addr); |
| 113 | extern u32 imx_get_cpu_arg(int cpu); | ||
| 114 | extern void imx_set_cpu_arg(int cpu, u32 arg); | ||
| 113 | extern void v7_cpu_resume(void); | 115 | extern void v7_cpu_resume(void); |
| 114 | extern u32 *pl310_get_save_ptr(void); | 116 | extern u32 *pl310_get_save_ptr(void); |
| 115 | #ifdef CONFIG_SMP | 117 | #ifdef CONFIG_SMP |
diff --git a/arch/arm/mach-imx/hotplug.c b/arch/arm/mach-imx/hotplug.c index 7bc5fe15dda2..361a253e2b63 100644 --- a/arch/arm/mach-imx/hotplug.c +++ b/arch/arm/mach-imx/hotplug.c | |||
| @@ -46,11 +46,23 @@ static inline void cpu_enter_lowpower(void) | |||
| 46 | void imx_cpu_die(unsigned int cpu) | 46 | void imx_cpu_die(unsigned int cpu) |
| 47 | { | 47 | { |
| 48 | cpu_enter_lowpower(); | 48 | cpu_enter_lowpower(); |
| 49 | /* | ||
| 50 | * We use the cpu jumping argument register to sync with | ||
| 51 | * imx_cpu_kill() which is running on cpu0 and waiting for | ||
| 52 | * the register being cleared to kill the cpu. | ||
| 53 | */ | ||
| 54 | imx_set_cpu_arg(cpu, ~0); | ||
| 49 | cpu_do_idle(); | 55 | cpu_do_idle(); |
| 50 | } | 56 | } |
| 51 | 57 | ||
| 52 | int imx_cpu_kill(unsigned int cpu) | 58 | int imx_cpu_kill(unsigned int cpu) |
| 53 | { | 59 | { |
| 60 | unsigned long timeout = jiffies + msecs_to_jiffies(50); | ||
| 61 | |||
| 62 | while (imx_get_cpu_arg(cpu) == 0) | ||
| 63 | if (time_after(jiffies, timeout)) | ||
| 64 | return 0; | ||
| 54 | imx_enable_cpu(cpu, false); | 65 | imx_enable_cpu(cpu, false); |
| 66 | imx_set_cpu_arg(cpu, 0); | ||
| 55 | return 1; | 67 | return 1; |
| 56 | } | 68 | } |
diff --git a/arch/arm/mach-imx/src.c b/arch/arm/mach-imx/src.c index e15f1555c59b..09a742f8c7ab 100644 --- a/arch/arm/mach-imx/src.c +++ b/arch/arm/mach-imx/src.c | |||
| @@ -43,6 +43,18 @@ void imx_set_cpu_jump(int cpu, void *jump_addr) | |||
| 43 | src_base + SRC_GPR1 + cpu * 8); | 43 | src_base + SRC_GPR1 + cpu * 8); |
| 44 | } | 44 | } |
| 45 | 45 | ||
| 46 | u32 imx_get_cpu_arg(int cpu) | ||
| 47 | { | ||
| 48 | cpu = cpu_logical_map(cpu); | ||
| 49 | return readl_relaxed(src_base + SRC_GPR1 + cpu * 8 + 4); | ||
| 50 | } | ||
| 51 | |||
| 52 | void imx_set_cpu_arg(int cpu, u32 arg) | ||
| 53 | { | ||
| 54 | cpu = cpu_logical_map(cpu); | ||
| 55 | writel_relaxed(arg, src_base + SRC_GPR1 + cpu * 8 + 4); | ||
| 56 | } | ||
| 57 | |||
| 46 | void imx_src_prepare_restart(void) | 58 | void imx_src_prepare_restart(void) |
| 47 | { | 59 | { |
| 48 | u32 val; | 60 | u32 val; |
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c index da1091be0887..8c60fcb08a98 100644 --- a/arch/arm/mach-integrator/integrator_cp.c +++ b/arch/arm/mach-integrator/integrator_cp.c | |||
| @@ -250,39 +250,6 @@ static void __init intcp_init_early(void) | |||
| 250 | } | 250 | } |
| 251 | 251 | ||
| 252 | #ifdef CONFIG_OF | 252 | #ifdef CONFIG_OF |
| 253 | |||
| 254 | static void __init cp_of_timer_init(void) | ||
| 255 | { | ||
| 256 | struct device_node *node; | ||
| 257 | const char *path; | ||
| 258 | void __iomem *base; | ||
| 259 | int err; | ||
| 260 | int irq; | ||
| 261 | |||
| 262 | err = of_property_read_string(of_aliases, | ||
| 263 | "arm,timer-primary", &path); | ||
| 264 | if (WARN_ON(err)) | ||
| 265 | return; | ||
| 266 | node = of_find_node_by_path(path); | ||
| 267 | base = of_iomap(node, 0); | ||
| 268 | if (WARN_ON(!base)) | ||
| 269 | return; | ||
| 270 | writel(0, base + TIMER_CTRL); | ||
| 271 | sp804_clocksource_init(base, node->name); | ||
| 272 | |||
| 273 | err = of_property_read_string(of_aliases, | ||
| 274 | "arm,timer-secondary", &path); | ||
| 275 | if (WARN_ON(err)) | ||
| 276 | return; | ||
| 277 | node = of_find_node_by_path(path); | ||
| 278 | base = of_iomap(node, 0); | ||
| 279 | if (WARN_ON(!base)) | ||
| 280 | return; | ||
| 281 | irq = irq_of_parse_and_map(node, 0); | ||
| 282 | writel(0, base + TIMER_CTRL); | ||
| 283 | sp804_clockevents_init(base, irq, node->name); | ||
| 284 | } | ||
| 285 | |||
| 286 | static const struct of_device_id fpga_irq_of_match[] __initconst = { | 253 | static const struct of_device_id fpga_irq_of_match[] __initconst = { |
| 287 | { .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, }, | 254 | { .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, }, |
| 288 | { /* Sentinel */ } | 255 | { /* Sentinel */ } |
| @@ -383,7 +350,6 @@ DT_MACHINE_START(INTEGRATOR_CP_DT, "ARM Integrator/CP (Device Tree)") | |||
| 383 | .init_early = intcp_init_early, | 350 | .init_early = intcp_init_early, |
| 384 | .init_irq = intcp_init_irq_of, | 351 | .init_irq = intcp_init_irq_of, |
| 385 | .handle_irq = fpga_handle_irq, | 352 | .handle_irq = fpga_handle_irq, |
| 386 | .init_time = cp_of_timer_init, | ||
| 387 | .init_machine = intcp_init_of, | 353 | .init_machine = intcp_init_of, |
| 388 | .restart = integrator_restart, | 354 | .restart = integrator_restart, |
| 389 | .dt_compat = intcp_dt_board_compat, | 355 | .dt_compat = intcp_dt_board_compat, |
diff --git a/arch/arm/mach-kirkwood/guruplug-setup.c b/arch/arm/mach-kirkwood/guruplug-setup.c index 1c6e736cbbf8..08dd739aa709 100644 --- a/arch/arm/mach-kirkwood/guruplug-setup.c +++ b/arch/arm/mach-kirkwood/guruplug-setup.c | |||
| @@ -53,6 +53,8 @@ static struct mv_sata_platform_data guruplug_sata_data = { | |||
| 53 | 53 | ||
| 54 | static struct mvsdio_platform_data guruplug_mvsdio_data = { | 54 | static struct mvsdio_platform_data guruplug_mvsdio_data = { |
| 55 | /* unfortunately the CD signal has not been connected */ | 55 | /* unfortunately the CD signal has not been connected */ |
| 56 | .gpio_card_detect = -1, | ||
| 57 | .gpio_write_protect = -1, | ||
| 56 | }; | 58 | }; |
| 57 | 59 | ||
| 58 | static struct gpio_led guruplug_led_pins[] = { | 60 | static struct gpio_led guruplug_led_pins[] = { |
diff --git a/arch/arm/mach-kirkwood/openrd-setup.c b/arch/arm/mach-kirkwood/openrd-setup.c index 8ddd69fdc937..6a6eb548307d 100644 --- a/arch/arm/mach-kirkwood/openrd-setup.c +++ b/arch/arm/mach-kirkwood/openrd-setup.c | |||
| @@ -55,6 +55,7 @@ static struct mv_sata_platform_data openrd_sata_data = { | |||
| 55 | 55 | ||
| 56 | static struct mvsdio_platform_data openrd_mvsdio_data = { | 56 | static struct mvsdio_platform_data openrd_mvsdio_data = { |
| 57 | .gpio_card_detect = 29, /* MPP29 used as SD card detect */ | 57 | .gpio_card_detect = 29, /* MPP29 used as SD card detect */ |
| 58 | .gpio_write_protect = -1, | ||
| 58 | }; | 59 | }; |
| 59 | 60 | ||
| 60 | static unsigned int openrd_mpp_config[] __initdata = { | 61 | static unsigned int openrd_mpp_config[] __initdata = { |
diff --git a/arch/arm/mach-kirkwood/rd88f6281-setup.c b/arch/arm/mach-kirkwood/rd88f6281-setup.c index c7d93b48926b..d24223166e06 100644 --- a/arch/arm/mach-kirkwood/rd88f6281-setup.c +++ b/arch/arm/mach-kirkwood/rd88f6281-setup.c | |||
| @@ -69,6 +69,7 @@ static struct mv_sata_platform_data rd88f6281_sata_data = { | |||
| 69 | 69 | ||
| 70 | static struct mvsdio_platform_data rd88f6281_mvsdio_data = { | 70 | static struct mvsdio_platform_data rd88f6281_mvsdio_data = { |
| 71 | .gpio_card_detect = 28, | 71 | .gpio_card_detect = 28, |
| 72 | .gpio_write_protect = -1, | ||
| 72 | }; | 73 | }; |
| 73 | 74 | ||
| 74 | static unsigned int rd88f6281_mpp_config[] __initdata = { | 75 | static unsigned int rd88f6281_mpp_config[] __initdata = { |
diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c index 2969027f02fa..f9fd77e8f1f5 100644 --- a/arch/arm/mach-msm/timer.c +++ b/arch/arm/mach-msm/timer.c | |||
| @@ -62,7 +62,10 @@ static int msm_timer_set_next_event(unsigned long cycles, | |||
| 62 | { | 62 | { |
| 63 | u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE); | 63 | u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE); |
| 64 | 64 | ||
| 65 | writel_relaxed(0, event_base + TIMER_CLEAR); | 65 | ctrl &= ~TIMER_ENABLE_EN; |
| 66 | writel_relaxed(ctrl, event_base + TIMER_ENABLE); | ||
| 67 | |||
| 68 | writel_relaxed(ctrl, event_base + TIMER_CLEAR); | ||
| 66 | writel_relaxed(cycles, event_base + TIMER_MATCH_VAL); | 69 | writel_relaxed(cycles, event_base + TIMER_MATCH_VAL); |
| 67 | writel_relaxed(ctrl | TIMER_ENABLE_EN, event_base + TIMER_ENABLE); | 70 | writel_relaxed(ctrl | TIMER_ENABLE_EN, event_base + TIMER_ENABLE); |
| 68 | return 0; | 71 | return 0; |
diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile index da93bcbc74c1..c3be068f1c96 100644 --- a/arch/arm/mach-mvebu/Makefile +++ b/arch/arm/mach-mvebu/Makefile | |||
| @@ -5,6 +5,6 @@ AFLAGS_coherency_ll.o := -Wa,-march=armv7-a | |||
| 5 | 5 | ||
| 6 | obj-y += system-controller.o | 6 | obj-y += system-controller.o |
| 7 | obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o | 7 | obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o |
| 8 | obj-$(CONFIG_ARCH_MVEBU) += addr-map.o coherency.o coherency_ll.o pmsu.o irq-armada-370-xp.o | 8 | obj-$(CONFIG_ARCH_MVEBU) += addr-map.o coherency.o coherency_ll.o pmsu.o |
| 9 | obj-$(CONFIG_SMP) += platsmp.o headsmp.o | 9 | obj-$(CONFIG_SMP) += platsmp.o headsmp.o |
| 10 | obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o | 10 | obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o |
diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c index a5ea616d6d12..433e8c5343b2 100644 --- a/arch/arm/mach-mvebu/armada-370-xp.c +++ b/arch/arm/mach-mvebu/armada-370-xp.c | |||
| @@ -19,6 +19,8 @@ | |||
| 19 | #include <linux/time-armada-370-xp.h> | 19 | #include <linux/time-armada-370-xp.h> |
| 20 | #include <linux/clk/mvebu.h> | 20 | #include <linux/clk/mvebu.h> |
| 21 | #include <linux/dma-mapping.h> | 21 | #include <linux/dma-mapping.h> |
| 22 | #include <linux/irqchip.h> | ||
| 23 | #include <asm/hardware/cache-l2x0.h> | ||
| 22 | #include <asm/mach/arch.h> | 24 | #include <asm/mach/arch.h> |
| 23 | #include <asm/mach/map.h> | 25 | #include <asm/mach/map.h> |
| 24 | #include <asm/mach/time.h> | 26 | #include <asm/mach/time.h> |
| @@ -54,6 +56,10 @@ void __init armada_370_xp_init_early(void) | |||
| 54 | * to make sure such the allocations won't fail. | 56 | * to make sure such the allocations won't fail. |
| 55 | */ | 57 | */ |
| 56 | init_dma_coherent_pool_size(SZ_1M); | 58 | init_dma_coherent_pool_size(SZ_1M); |
| 59 | |||
| 60 | #ifdef CONFIG_CACHE_L2X0 | ||
| 61 | l2x0_of_init(0, ~0UL); | ||
| 62 | #endif | ||
| 57 | } | 63 | } |
| 58 | 64 | ||
| 59 | static void __init armada_370_xp_dt_init(void) | 65 | static void __init armada_370_xp_dt_init(void) |
| @@ -72,8 +78,7 @@ DT_MACHINE_START(ARMADA_XP_DT, "Marvell Armada 370/XP (Device Tree)") | |||
| 72 | .init_machine = armada_370_xp_dt_init, | 78 | .init_machine = armada_370_xp_dt_init, |
| 73 | .map_io = armada_370_xp_map_io, | 79 | .map_io = armada_370_xp_map_io, |
| 74 | .init_early = armada_370_xp_init_early, | 80 | .init_early = armada_370_xp_init_early, |
| 75 | .init_irq = armada_370_xp_init_irq, | 81 | .init_irq = irqchip_init, |
| 76 | .handle_irq = armada_370_xp_handle_irq, | ||
| 77 | .init_time = armada_370_xp_timer_and_clk_init, | 82 | .init_time = armada_370_xp_timer_and_clk_init, |
| 78 | .restart = mvebu_restart, | 83 | .restart = mvebu_restart, |
| 79 | .dt_compat = armada_370_xp_dt_compat, | 84 | .dt_compat = armada_370_xp_dt_compat, |
diff --git a/arch/arm/mach-mvebu/irq-armada-370-xp.c b/arch/arm/mach-mvebu/irq-armada-370-xp.c deleted file mode 100644 index 274ff58271de..000000000000 --- a/arch/arm/mach-mvebu/irq-armada-370-xp.c +++ /dev/null | |||
| @@ -1,296 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Marvell Armada 370 and Armada XP SoC IRQ handling | ||
| 3 | * | ||
| 4 | * Copyright (C) 2012 Marvell | ||
| 5 | * | ||
| 6 | * Lior Amsalem <alior@marvell.com> | ||
| 7 | * Gregory CLEMENT <gregory.clement@free-electrons.com> | ||
| 8 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | ||
| 9 | * Ben Dooks <ben.dooks@codethink.co.uk> | ||
| 10 | * | ||
| 11 | * This file is licensed under the terms of the GNU General Public | ||
| 12 | * License version 2. This program is licensed "as is" without any | ||
| 13 | * warranty of any kind, whether express or implied. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #include <linux/kernel.h> | ||
| 17 | #include <linux/module.h> | ||
| 18 | #include <linux/init.h> | ||
| 19 | #include <linux/irq.h> | ||
| 20 | #include <linux/interrupt.h> | ||
| 21 | #include <linux/io.h> | ||
| 22 | #include <linux/of_address.h> | ||
| 23 | #include <linux/of_irq.h> | ||
| 24 | #include <linux/irqdomain.h> | ||
| 25 | #include <asm/mach/arch.h> | ||
| 26 | #include <asm/exception.h> | ||
| 27 | #include <asm/smp_plat.h> | ||
| 28 | #include <asm/hardware/cache-l2x0.h> | ||
| 29 | |||
| 30 | /* Interrupt Controller Registers Map */ | ||
| 31 | #define ARMADA_370_XP_INT_SET_MASK_OFFS (0x48) | ||
| 32 | #define ARMADA_370_XP_INT_CLEAR_MASK_OFFS (0x4C) | ||
| 33 | |||
| 34 | #define ARMADA_370_XP_INT_CONTROL (0x00) | ||
| 35 | #define ARMADA_370_XP_INT_SET_ENABLE_OFFS (0x30) | ||
| 36 | #define ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS (0x34) | ||
| 37 | #define ARMADA_370_XP_INT_SOURCE_CTL(irq) (0x100 + irq*4) | ||
| 38 | |||
| 39 | #define ARMADA_370_XP_CPU_INTACK_OFFS (0x44) | ||
| 40 | |||
| 41 | #define ARMADA_370_XP_SW_TRIG_INT_OFFS (0x4) | ||
| 42 | #define ARMADA_370_XP_IN_DRBEL_MSK_OFFS (0xc) | ||
| 43 | #define ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS (0x8) | ||
| 44 | |||
| 45 | #define ARMADA_370_XP_MAX_PER_CPU_IRQS (28) | ||
| 46 | |||
| 47 | #define ACTIVE_DOORBELLS (8) | ||
| 48 | |||
| 49 | static DEFINE_RAW_SPINLOCK(irq_controller_lock); | ||
| 50 | |||
| 51 | static void __iomem *per_cpu_int_base; | ||
| 52 | static void __iomem *main_int_base; | ||
| 53 | static struct irq_domain *armada_370_xp_mpic_domain; | ||
| 54 | |||
| 55 | /* | ||
| 56 | * In SMP mode: | ||
| 57 | * For shared global interrupts, mask/unmask global enable bit | ||
| 58 | * For CPU interrtups, mask/unmask the calling CPU's bit | ||
| 59 | */ | ||
| 60 | static void armada_370_xp_irq_mask(struct irq_data *d) | ||
| 61 | { | ||
| 62 | #ifdef CONFIG_SMP | ||
| 63 | irq_hw_number_t hwirq = irqd_to_hwirq(d); | ||
| 64 | |||
| 65 | if (hwirq > ARMADA_370_XP_MAX_PER_CPU_IRQS) | ||
| 66 | writel(hwirq, main_int_base + | ||
| 67 | ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS); | ||
| 68 | else | ||
| 69 | writel(hwirq, per_cpu_int_base + | ||
| 70 | ARMADA_370_XP_INT_SET_MASK_OFFS); | ||
| 71 | #else | ||
| 72 | writel(irqd_to_hwirq(d), | ||
| 73 | per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS); | ||
| 74 | #endif | ||
| 75 | } | ||
| 76 | |||
| 77 | static void armada_370_xp_irq_unmask(struct irq_data *d) | ||
| 78 | { | ||
| 79 | #ifdef CONFIG_SMP | ||
| 80 | irq_hw_number_t hwirq = irqd_to_hwirq(d); | ||
| 81 | |||
| 82 | if (hwirq > ARMADA_370_XP_MAX_PER_CPU_IRQS) | ||
| 83 | writel(hwirq, main_int_base + | ||
| 84 | ARMADA_370_XP_INT_SET_ENABLE_OFFS); | ||
| 85 | else | ||
| 86 | writel(hwirq, per_cpu_int_base + | ||
| 87 | ARMADA_370_XP_INT_CLEAR_MASK_OFFS); | ||
| 88 | #else | ||
| 89 | writel(irqd_to_hwirq(d), | ||
| 90 | per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); | ||
| 91 | #endif | ||
| 92 | } | ||
| 93 | |||
| 94 | #ifdef CONFIG_SMP | ||
| 95 | static int armada_xp_set_affinity(struct irq_data *d, | ||
| 96 | const struct cpumask *mask_val, bool force) | ||
| 97 | { | ||
| 98 | unsigned long reg; | ||
| 99 | unsigned long new_mask = 0; | ||
| 100 | unsigned long online_mask = 0; | ||
| 101 | unsigned long count = 0; | ||
| 102 | irq_hw_number_t hwirq = irqd_to_hwirq(d); | ||
| 103 | int cpu; | ||
| 104 | |||
| 105 | for_each_cpu(cpu, mask_val) { | ||
| 106 | new_mask |= 1 << cpu_logical_map(cpu); | ||
| 107 | count++; | ||
| 108 | } | ||
| 109 | |||
| 110 | /* | ||
| 111 | * Forbid mutlicore interrupt affinity | ||
| 112 | * This is required since the MPIC HW doesn't limit | ||
| 113 | * several CPUs from acknowledging the same interrupt. | ||
| 114 | */ | ||
| 115 | if (count > 1) | ||
| 116 | return -EINVAL; | ||
| 117 | |||
| 118 | for_each_cpu(cpu, cpu_online_mask) | ||
| 119 | online_mask |= 1 << cpu_logical_map(cpu); | ||
| 120 | |||
| 121 | raw_spin_lock(&irq_controller_lock); | ||
| 122 | |||
| 123 | reg = readl(main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq)); | ||
| 124 | reg = (reg & (~online_mask)) | new_mask; | ||
| 125 | writel(reg, main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq)); | ||
| 126 | |||
| 127 | raw_spin_unlock(&irq_controller_lock); | ||
| 128 | |||
| 129 | return 0; | ||
| 130 | } | ||
| 131 | #endif | ||
| 132 | |||
| 133 | static struct irq_chip armada_370_xp_irq_chip = { | ||
| 134 | .name = "armada_370_xp_irq", | ||
| 135 | .irq_mask = armada_370_xp_irq_mask, | ||
| 136 | .irq_mask_ack = armada_370_xp_irq_mask, | ||
| 137 | .irq_unmask = armada_370_xp_irq_unmask, | ||
| 138 | #ifdef CONFIG_SMP | ||
| 139 | .irq_set_affinity = armada_xp_set_affinity, | ||
| 140 | #endif | ||
| 141 | }; | ||
| 142 | |||
| 143 | static int armada_370_xp_mpic_irq_map(struct irq_domain *h, | ||
| 144 | unsigned int virq, irq_hw_number_t hw) | ||
| 145 | { | ||
| 146 | armada_370_xp_irq_mask(irq_get_irq_data(virq)); | ||
| 147 | writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS); | ||
| 148 | irq_set_status_flags(virq, IRQ_LEVEL); | ||
| 149 | |||
| 150 | if (hw < ARMADA_370_XP_MAX_PER_CPU_IRQS) { | ||
| 151 | irq_set_percpu_devid(virq); | ||
| 152 | irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip, | ||
| 153 | handle_percpu_devid_irq); | ||
| 154 | |||
| 155 | } else { | ||
| 156 | irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip, | ||
| 157 | handle_level_irq); | ||
| 158 | } | ||
| 159 | set_irq_flags(virq, IRQF_VALID | IRQF_PROBE); | ||
| 160 | |||
| 161 | return 0; | ||
| 162 | } | ||
| 163 | |||
| 164 | #ifdef CONFIG_SMP | ||
| 165 | void armada_mpic_send_doorbell(const struct cpumask *mask, unsigned int irq) | ||
| 166 | { | ||
| 167 | int cpu; | ||
| 168 | unsigned long map = 0; | ||
| 169 | |||
| 170 | /* Convert our logical CPU mask into a physical one. */ | ||
| 171 | for_each_cpu(cpu, mask) | ||
| 172 | map |= 1 << cpu_logical_map(cpu); | ||
| 173 | |||
| 174 | /* | ||
| 175 | * Ensure that stores to Normal memory are visible to the | ||
| 176 | * other CPUs before issuing the IPI. | ||
| 177 | */ | ||
| 178 | dsb(); | ||
| 179 | |||
| 180 | /* submit softirq */ | ||
| 181 | writel((map << 8) | irq, main_int_base + | ||
| 182 | ARMADA_370_XP_SW_TRIG_INT_OFFS); | ||
| 183 | } | ||
| 184 | |||
| 185 | void armada_xp_mpic_smp_cpu_init(void) | ||
| 186 | { | ||
| 187 | /* Clear pending IPIs */ | ||
| 188 | writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS); | ||
| 189 | |||
| 190 | /* Enable first 8 IPIs */ | ||
| 191 | writel((1 << ACTIVE_DOORBELLS) - 1, per_cpu_int_base + | ||
| 192 | ARMADA_370_XP_IN_DRBEL_MSK_OFFS); | ||
| 193 | |||
| 194 | /* Unmask IPI interrupt */ | ||
| 195 | writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); | ||
| 196 | } | ||
| 197 | #endif /* CONFIG_SMP */ | ||
| 198 | |||
| 199 | static struct irq_domain_ops armada_370_xp_mpic_irq_ops = { | ||
| 200 | .map = armada_370_xp_mpic_irq_map, | ||
| 201 | .xlate = irq_domain_xlate_onecell, | ||
| 202 | }; | ||
| 203 | |||
| 204 | static int __init armada_370_xp_mpic_of_init(struct device_node *node, | ||
| 205 | struct device_node *parent) | ||
| 206 | { | ||
| 207 | u32 control; | ||
| 208 | |||
| 209 | main_int_base = of_iomap(node, 0); | ||
| 210 | per_cpu_int_base = of_iomap(node, 1); | ||
| 211 | |||
| 212 | BUG_ON(!main_int_base); | ||
| 213 | BUG_ON(!per_cpu_int_base); | ||
| 214 | |||
| 215 | control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL); | ||
| 216 | |||
| 217 | armada_370_xp_mpic_domain = | ||
| 218 | irq_domain_add_linear(node, (control >> 2) & 0x3ff, | ||
| 219 | &armada_370_xp_mpic_irq_ops, NULL); | ||
| 220 | |||
| 221 | if (!armada_370_xp_mpic_domain) | ||
| 222 | panic("Unable to add Armada_370_Xp MPIC irq domain (DT)\n"); | ||
| 223 | |||
| 224 | irq_set_default_host(armada_370_xp_mpic_domain); | ||
| 225 | |||
| 226 | #ifdef CONFIG_SMP | ||
| 227 | armada_xp_mpic_smp_cpu_init(); | ||
| 228 | |||
| 229 | /* | ||
| 230 | * Set the default affinity from all CPUs to the boot cpu. | ||
| 231 | * This is required since the MPIC doesn't limit several CPUs | ||
| 232 | * from acknowledging the same interrupt. | ||
| 233 | */ | ||
| 234 | cpumask_clear(irq_default_affinity); | ||
| 235 | cpumask_set_cpu(smp_processor_id(), irq_default_affinity); | ||
| 236 | |||
| 237 | #endif | ||
| 238 | |||
| 239 | return 0; | ||
| 240 | } | ||
| 241 | |||
| 242 | asmlinkage void __exception_irq_entry armada_370_xp_handle_irq(struct pt_regs | ||
| 243 | *regs) | ||
| 244 | { | ||
| 245 | u32 irqstat, irqnr; | ||
| 246 | |||
| 247 | do { | ||
| 248 | irqstat = readl_relaxed(per_cpu_int_base + | ||
| 249 | ARMADA_370_XP_CPU_INTACK_OFFS); | ||
| 250 | irqnr = irqstat & 0x3FF; | ||
| 251 | |||
| 252 | if (irqnr > 1022) | ||
| 253 | break; | ||
| 254 | |||
| 255 | if (irqnr > 0) { | ||
| 256 | irqnr = irq_find_mapping(armada_370_xp_mpic_domain, | ||
| 257 | irqnr); | ||
| 258 | handle_IRQ(irqnr, regs); | ||
| 259 | continue; | ||
| 260 | } | ||
| 261 | #ifdef CONFIG_SMP | ||
| 262 | /* IPI Handling */ | ||
| 263 | if (irqnr == 0) { | ||
| 264 | u32 ipimask, ipinr; | ||
| 265 | |||
| 266 | ipimask = readl_relaxed(per_cpu_int_base + | ||
| 267 | ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS) | ||
| 268 | & 0xFF; | ||
| 269 | |||
| 270 | writel(0x0, per_cpu_int_base + | ||
| 271 | ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS); | ||
| 272 | |||
| 273 | /* Handle all pending doorbells */ | ||
| 274 | for (ipinr = 0; ipinr < ACTIVE_DOORBELLS; ipinr++) { | ||
| 275 | if (ipimask & (0x1 << ipinr)) | ||
| 276 | handle_IPI(ipinr, regs); | ||
| 277 | } | ||
| 278 | continue; | ||
| 279 | } | ||
| 280 | #endif | ||
| 281 | |||
| 282 | } while (1); | ||
| 283 | } | ||
| 284 | |||
| 285 | static const struct of_device_id mpic_of_match[] __initconst = { | ||
| 286 | {.compatible = "marvell,mpic", .data = armada_370_xp_mpic_of_init}, | ||
| 287 | {}, | ||
| 288 | }; | ||
| 289 | |||
| 290 | void __init armada_370_xp_init_irq(void) | ||
| 291 | { | ||
| 292 | of_irq_init(mpic_of_match); | ||
| 293 | #ifdef CONFIG_CACHE_L2X0 | ||
| 294 | l2x0_of_init(0, ~0UL); | ||
| 295 | #endif | ||
| 296 | } | ||
diff --git a/arch/arm/mach-omap1/clock_data.c b/arch/arm/mach-omap1/clock_data.c index cb7c6ae2e3fc..6c4f766365a2 100644 --- a/arch/arm/mach-omap1/clock_data.c +++ b/arch/arm/mach-omap1/clock_data.c | |||
| @@ -543,15 +543,6 @@ static struct clk usb_dc_ck = { | |||
| 543 | /* Direct from ULPD, no parent */ | 543 | /* Direct from ULPD, no parent */ |
| 544 | .rate = 48000000, | 544 | .rate = 48000000, |
| 545 | .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), | 545 | .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), |
| 546 | .enable_bit = USB_REQ_EN_SHIFT, | ||
| 547 | }; | ||
| 548 | |||
| 549 | static struct clk usb_dc_ck7xx = { | ||
| 550 | .name = "usb_dc_ck", | ||
| 551 | .ops = &clkops_generic, | ||
| 552 | /* Direct from ULPD, no parent */ | ||
| 553 | .rate = 48000000, | ||
| 554 | .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), | ||
| 555 | .enable_bit = SOFT_USB_OTG_DPLL_REQ_SHIFT, | 546 | .enable_bit = SOFT_USB_OTG_DPLL_REQ_SHIFT, |
| 556 | }; | 547 | }; |
| 557 | 548 | ||
| @@ -727,8 +718,7 @@ static struct omap_clk omap_clks[] = { | |||
| 727 | CLK(NULL, "usb_clko", &usb_clko, CK_16XX | CK_1510 | CK_310), | 718 | CLK(NULL, "usb_clko", &usb_clko, CK_16XX | CK_1510 | CK_310), |
| 728 | CLK(NULL, "usb_hhc_ck", &usb_hhc_ck1510, CK_1510 | CK_310), | 719 | CLK(NULL, "usb_hhc_ck", &usb_hhc_ck1510, CK_1510 | CK_310), |
| 729 | CLK(NULL, "usb_hhc_ck", &usb_hhc_ck16xx, CK_16XX), | 720 | CLK(NULL, "usb_hhc_ck", &usb_hhc_ck16xx, CK_16XX), |
| 730 | CLK(NULL, "usb_dc_ck", &usb_dc_ck, CK_16XX), | 721 | CLK(NULL, "usb_dc_ck", &usb_dc_ck, CK_16XX | CK_7XX), |
| 731 | CLK(NULL, "usb_dc_ck", &usb_dc_ck7xx, CK_7XX), | ||
| 732 | CLK(NULL, "mclk", &mclk_1510, CK_1510 | CK_310), | 722 | CLK(NULL, "mclk", &mclk_1510, CK_1510 | CK_310), |
| 733 | CLK(NULL, "mclk", &mclk_16xx, CK_16XX), | 723 | CLK(NULL, "mclk", &mclk_16xx, CK_16XX), |
| 734 | CLK(NULL, "bclk", &bclk_1510, CK_1510 | CK_310), | 724 | CLK(NULL, "bclk", &bclk_1510, CK_1510 | CK_310), |
diff --git a/arch/arm/mach-omap1/include/mach/usb.h b/arch/arm/mach-omap1/include/mach/usb.h index 753cd5ce6949..45e5ac707cbb 100644 --- a/arch/arm/mach-omap1/include/mach/usb.h +++ b/arch/arm/mach-omap1/include/mach/usb.h | |||
| @@ -2,7 +2,7 @@ | |||
| 2 | * FIXME correct answer depends on hmc_mode, | 2 | * FIXME correct answer depends on hmc_mode, |
| 3 | * as does (on omap1) any nonzero value for config->otg port number | 3 | * as does (on omap1) any nonzero value for config->otg port number |
| 4 | */ | 4 | */ |
| 5 | #ifdef CONFIG_USB_GADGET_OMAP | 5 | #if IS_ENABLED(CONFIG_USB_OMAP) |
| 6 | #define is_usb0_device(config) 1 | 6 | #define is_usb0_device(config) 1 |
| 7 | #else | 7 | #else |
| 8 | #define is_usb0_device(config) 0 | 8 | #define is_usb0_device(config) 0 |
diff --git a/arch/arm/mach-omap1/usb.c b/arch/arm/mach-omap1/usb.c index 1a1db5971cd9..4118db50d5e8 100644 --- a/arch/arm/mach-omap1/usb.c +++ b/arch/arm/mach-omap1/usb.c | |||
| @@ -123,7 +123,7 @@ omap_otg_init(struct omap_usb_config *config) | |||
| 123 | syscon = omap_readl(OTG_SYSCON_1); | 123 | syscon = omap_readl(OTG_SYSCON_1); |
| 124 | syscon |= HST_IDLE_EN|DEV_IDLE_EN|OTG_IDLE_EN; | 124 | syscon |= HST_IDLE_EN|DEV_IDLE_EN|OTG_IDLE_EN; |
| 125 | 125 | ||
| 126 | #ifdef CONFIG_USB_GADGET_OMAP | 126 | #if IS_ENABLED(CONFIG_USB_OMAP) |
| 127 | if (config->otg || config->register_dev) { | 127 | if (config->otg || config->register_dev) { |
| 128 | struct platform_device *udc_device = config->udc_device; | 128 | struct platform_device *udc_device = config->udc_device; |
| 129 | int status; | 129 | int status; |
| @@ -169,7 +169,7 @@ omap_otg_init(struct omap_usb_config *config) | |||
| 169 | void omap_otg_init(struct omap_usb_config *config) {} | 169 | void omap_otg_init(struct omap_usb_config *config) {} |
| 170 | #endif | 170 | #endif |
| 171 | 171 | ||
| 172 | #ifdef CONFIG_USB_GADGET_OMAP | 172 | #if IS_ENABLED(CONFIG_USB_OMAP) |
| 173 | 173 | ||
| 174 | static struct resource udc_resources[] = { | 174 | static struct resource udc_resources[] = { |
| 175 | /* order is significant! */ | 175 | /* order is significant! */ |
| @@ -600,7 +600,7 @@ static void __init omap_1510_usb_init(struct omap_usb_config *config) | |||
| 600 | while (!(omap_readw(ULPD_DPLL_CTRL) & DPLL_LOCK)) | 600 | while (!(omap_readw(ULPD_DPLL_CTRL) & DPLL_LOCK)) |
| 601 | cpu_relax(); | 601 | cpu_relax(); |
| 602 | 602 | ||
| 603 | #ifdef CONFIG_USB_GADGET_OMAP | 603 | #if IS_ENABLED(CONFIG_USB_OMAP) |
| 604 | if (config->register_dev) { | 604 | if (config->register_dev) { |
| 605 | int status; | 605 | int status; |
| 606 | 606 | ||
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index b068b7fe99ef..62bb352c2d37 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile | |||
| @@ -229,7 +229,6 @@ obj-$(CONFIG_MACH_DEVKIT8000) += board-devkit8000.o | |||
| 229 | obj-$(CONFIG_MACH_OMAP_LDP) += board-ldp.o | 229 | obj-$(CONFIG_MACH_OMAP_LDP) += board-ldp.o |
| 230 | obj-$(CONFIG_MACH_OMAP3530_LV_SOM) += board-omap3logic.o | 230 | obj-$(CONFIG_MACH_OMAP3530_LV_SOM) += board-omap3logic.o |
| 231 | obj-$(CONFIG_MACH_OMAP3_TORPEDO) += board-omap3logic.o | 231 | obj-$(CONFIG_MACH_OMAP3_TORPEDO) += board-omap3logic.o |
| 232 | obj-$(CONFIG_MACH_ENCORE) += board-omap3encore.o | ||
| 233 | obj-$(CONFIG_MACH_OVERO) += board-overo.o | 232 | obj-$(CONFIG_MACH_OVERO) += board-overo.o |
| 234 | obj-$(CONFIG_MACH_OMAP3EVM) += board-omap3evm.o | 233 | obj-$(CONFIG_MACH_OMAP3EVM) += board-omap3evm.o |
| 235 | obj-$(CONFIG_MACH_OMAP3_PANDORA) += board-omap3pandora.o | 234 | obj-$(CONFIG_MACH_OMAP3_PANDORA) += board-omap3pandora.o |
| @@ -255,8 +254,6 @@ obj-$(CONFIG_MACH_TOUCHBOOK) += board-omap3touchbook.o | |||
| 255 | obj-$(CONFIG_MACH_OMAP_4430SDP) += board-4430sdp.o | 254 | obj-$(CONFIG_MACH_OMAP_4430SDP) += board-4430sdp.o |
| 256 | obj-$(CONFIG_MACH_OMAP4_PANDA) += board-omap4panda.o | 255 | obj-$(CONFIG_MACH_OMAP4_PANDA) += board-omap4panda.o |
| 257 | 256 | ||
| 258 | obj-$(CONFIG_MACH_PCM049) += board-omap4pcm049.o | ||
| 259 | |||
| 260 | obj-$(CONFIG_MACH_OMAP3517EVM) += board-am3517evm.o | 257 | obj-$(CONFIG_MACH_OMAP3517EVM) += board-am3517evm.o |
| 261 | 258 | ||
| 262 | obj-$(CONFIG_MACH_CRANEBOARD) += board-am3517crane.o | 259 | obj-$(CONFIG_MACH_CRANEBOARD) += board-am3517crane.o |
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c index cb0596b631cf..244d8a5aa54b 100644 --- a/arch/arm/mach-omap2/board-2430sdp.c +++ b/arch/arm/mach-omap2/board-2430sdp.c | |||
| @@ -38,7 +38,7 @@ | |||
| 38 | #include "gpmc-smc91x.h" | 38 | #include "gpmc-smc91x.h" |
| 39 | 39 | ||
| 40 | #include <video/omapdss.h> | 40 | #include <video/omapdss.h> |
| 41 | #include <video/omap-panel-generic-dpi.h> | 41 | #include <video/omap-panel-data.h> |
| 42 | 42 | ||
| 43 | #include "mux.h" | 43 | #include "mux.h" |
| 44 | #include "hsmmc.h" | 44 | #include "hsmmc.h" |
| @@ -108,24 +108,13 @@ static struct platform_device *sdp2430_devices[] __initdata = { | |||
| 108 | #define SDP2430_LCD_PANEL_BACKLIGHT_GPIO 91 | 108 | #define SDP2430_LCD_PANEL_BACKLIGHT_GPIO 91 |
| 109 | #define SDP2430_LCD_PANEL_ENABLE_GPIO 154 | 109 | #define SDP2430_LCD_PANEL_ENABLE_GPIO 154 |
| 110 | 110 | ||
| 111 | static int sdp2430_panel_enable_lcd(struct omap_dss_device *dssdev) | ||
| 112 | { | ||
| 113 | gpio_direction_output(SDP2430_LCD_PANEL_ENABLE_GPIO, 1); | ||
| 114 | gpio_direction_output(SDP2430_LCD_PANEL_BACKLIGHT_GPIO, 1); | ||
| 115 | |||
| 116 | return 0; | ||
| 117 | } | ||
| 118 | |||
| 119 | static void sdp2430_panel_disable_lcd(struct omap_dss_device *dssdev) | ||
| 120 | { | ||
| 121 | gpio_direction_output(SDP2430_LCD_PANEL_ENABLE_GPIO, 0); | ||
| 122 | gpio_direction_output(SDP2430_LCD_PANEL_BACKLIGHT_GPIO, 0); | ||
| 123 | } | ||
| 124 | |||
| 125 | static struct panel_generic_dpi_data sdp2430_panel_data = { | 111 | static struct panel_generic_dpi_data sdp2430_panel_data = { |
| 126 | .name = "nec_nl2432dr22-11b", | 112 | .name = "nec_nl2432dr22-11b", |
| 127 | .platform_enable = sdp2430_panel_enable_lcd, | 113 | .num_gpios = 2, |
| 128 | .platform_disable = sdp2430_panel_disable_lcd, | 114 | .gpios = { |
| 115 | SDP2430_LCD_PANEL_ENABLE_GPIO, | ||
| 116 | SDP2430_LCD_PANEL_BACKLIGHT_GPIO, | ||
| 117 | }, | ||
| 129 | }; | 118 | }; |
| 130 | 119 | ||
| 131 | static struct omap_dss_device sdp2430_lcd_device = { | 120 | static struct omap_dss_device sdp2430_lcd_device = { |
| @@ -146,26 +135,6 @@ static struct omap_dss_board_info sdp2430_dss_data = { | |||
| 146 | .default_device = &sdp2430_lcd_device, | 135 | .default_device = &sdp2430_lcd_device, |
| 147 | }; | 136 | }; |
| 148 | 137 | ||
| 149 | static void __init sdp2430_display_init(void) | ||
| 150 | { | ||
| 151 | int r; | ||
| 152 | |||
| 153 | static struct gpio gpios[] __initdata = { | ||
| 154 | { SDP2430_LCD_PANEL_ENABLE_GPIO, GPIOF_OUT_INIT_LOW, | ||
| 155 | "LCD reset" }, | ||
| 156 | { SDP2430_LCD_PANEL_BACKLIGHT_GPIO, GPIOF_OUT_INIT_LOW, | ||
| 157 | "LCD Backlight" }, | ||
| 158 | }; | ||
| 159 | |||
| 160 | r = gpio_request_array(gpios, ARRAY_SIZE(gpios)); | ||
| 161 | if (r) { | ||
| 162 | pr_err("Cannot request LCD GPIOs, error %d\n", r); | ||
| 163 | return; | ||
| 164 | } | ||
| 165 | |||
| 166 | omap_display_init(&sdp2430_dss_data); | ||
| 167 | } | ||
| 168 | |||
| 169 | #if IS_ENABLED(CONFIG_SMC91X) | 138 | #if IS_ENABLED(CONFIG_SMC91X) |
| 170 | 139 | ||
| 171 | static struct omap_smc91x_platform_data board_smc91x_data = { | 140 | static struct omap_smc91x_platform_data board_smc91x_data = { |
| @@ -273,7 +242,7 @@ static void __init omap_2430sdp_init(void) | |||
| 273 | gpio_request_one(SECONDARY_LCD_GPIO, GPIOF_OUT_INIT_LOW, | 242 | gpio_request_one(SECONDARY_LCD_GPIO, GPIOF_OUT_INIT_LOW, |
| 274 | "Secondary LCD backlight"); | 243 | "Secondary LCD backlight"); |
| 275 | 244 | ||
| 276 | sdp2430_display_init(); | 245 | omap_display_init(&sdp2430_dss_data); |
| 277 | } | 246 | } |
| 278 | 247 | ||
| 279 | MACHINE_START(OMAP_2430SDP, "OMAP2430 sdp2430 board") | 248 | MACHINE_START(OMAP_2430SDP, "OMAP2430 sdp2430 board") |
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c index 7eb9651dd0f7..23b004afa3f8 100644 --- a/arch/arm/mach-omap2/board-3430sdp.c +++ b/arch/arm/mach-omap2/board-3430sdp.c | |||
| @@ -35,7 +35,7 @@ | |||
| 35 | #include "common.h" | 35 | #include "common.h" |
| 36 | #include <linux/omap-dma.h> | 36 | #include <linux/omap-dma.h> |
| 37 | #include <video/omapdss.h> | 37 | #include <video/omapdss.h> |
| 38 | #include <video/omap-panel-tfp410.h> | 38 | #include <video/omap-panel-data.h> |
| 39 | 39 | ||
| 40 | #include "gpmc.h" | 40 | #include "gpmc.h" |
| 41 | #include "gpmc-smc91x.h" | 41 | #include "gpmc-smc91x.h" |
| @@ -108,53 +108,38 @@ static struct twl4030_keypad_data sdp3430_kp_data = { | |||
| 108 | #define SDP3430_LCD_PANEL_BACKLIGHT_GPIO 8 | 108 | #define SDP3430_LCD_PANEL_BACKLIGHT_GPIO 8 |
| 109 | #define SDP3430_LCD_PANEL_ENABLE_GPIO 5 | 109 | #define SDP3430_LCD_PANEL_ENABLE_GPIO 5 |
| 110 | 110 | ||
| 111 | static struct gpio sdp3430_dss_gpios[] __initdata = { | ||
| 112 | {SDP3430_LCD_PANEL_ENABLE_GPIO, GPIOF_OUT_INIT_LOW, "LCD reset" }, | ||
| 113 | {SDP3430_LCD_PANEL_BACKLIGHT_GPIO, GPIOF_OUT_INIT_LOW, "LCD Backlight"}, | ||
| 114 | }; | ||
| 115 | |||
| 116 | static void __init sdp3430_display_init(void) | 111 | static void __init sdp3430_display_init(void) |
| 117 | { | 112 | { |
| 118 | int r; | 113 | int r; |
| 119 | 114 | ||
| 120 | r = gpio_request_array(sdp3430_dss_gpios, | 115 | /* |
| 121 | ARRAY_SIZE(sdp3430_dss_gpios)); | 116 | * the backlight GPIO doesn't directly go to the panel, it enables |
| 117 | * an internal circuit on 3430sdp to create the signal V_BKL_28V, | ||
| 118 | * this is connected to LED+ pin of the sharp panel. This GPIO | ||
| 119 | * is left enabled in the board file, and not passed to the panel | ||
| 120 | * as platform_data. | ||
| 121 | */ | ||
| 122 | r = gpio_request_one(SDP3430_LCD_PANEL_BACKLIGHT_GPIO, | ||
| 123 | GPIOF_OUT_INIT_HIGH, "LCD Backlight"); | ||
| 122 | if (r) | 124 | if (r) |
| 123 | printk(KERN_ERR "failed to get LCD control GPIOs\n"); | 125 | pr_err("failed to get LCD Backlight GPIO\n"); |
| 124 | |||
| 125 | } | ||
| 126 | 126 | ||
| 127 | static int sdp3430_panel_enable_lcd(struct omap_dss_device *dssdev) | ||
| 128 | { | ||
| 129 | gpio_direction_output(SDP3430_LCD_PANEL_ENABLE_GPIO, 1); | ||
| 130 | gpio_direction_output(SDP3430_LCD_PANEL_BACKLIGHT_GPIO, 1); | ||
| 131 | |||
| 132 | return 0; | ||
| 133 | } | ||
| 134 | |||
| 135 | static void sdp3430_panel_disable_lcd(struct omap_dss_device *dssdev) | ||
| 136 | { | ||
| 137 | gpio_direction_output(SDP3430_LCD_PANEL_ENABLE_GPIO, 0); | ||
| 138 | gpio_direction_output(SDP3430_LCD_PANEL_BACKLIGHT_GPIO, 0); | ||
| 139 | } | ||
| 140 | |||
| 141 | static int sdp3430_panel_enable_tv(struct omap_dss_device *dssdev) | ||
| 142 | { | ||
| 143 | return 0; | ||
| 144 | } | ||
| 145 | |||
| 146 | static void sdp3430_panel_disable_tv(struct omap_dss_device *dssdev) | ||
| 147 | { | ||
| 148 | } | 127 | } |
| 149 | 128 | ||
| 129 | static struct panel_sharp_ls037v7dw01_data sdp3430_lcd_data = { | ||
| 130 | .resb_gpio = SDP3430_LCD_PANEL_ENABLE_GPIO, | ||
| 131 | .ini_gpio = -1, | ||
| 132 | .mo_gpio = -1, | ||
| 133 | .lr_gpio = -1, | ||
| 134 | .ud_gpio = -1, | ||
| 135 | }; | ||
| 150 | 136 | ||
| 151 | static struct omap_dss_device sdp3430_lcd_device = { | 137 | static struct omap_dss_device sdp3430_lcd_device = { |
| 152 | .name = "lcd", | 138 | .name = "lcd", |
| 153 | .driver_name = "sharp_ls_panel", | 139 | .driver_name = "sharp_ls_panel", |
| 154 | .type = OMAP_DISPLAY_TYPE_DPI, | 140 | .type = OMAP_DISPLAY_TYPE_DPI, |
| 155 | .phy.dpi.data_lines = 16, | 141 | .phy.dpi.data_lines = 16, |
| 156 | .platform_enable = sdp3430_panel_enable_lcd, | 142 | .data = &sdp3430_lcd_data, |
| 157 | .platform_disable = sdp3430_panel_disable_lcd, | ||
| 158 | }; | 143 | }; |
| 159 | 144 | ||
| 160 | static struct tfp410_platform_data dvi_panel = { | 145 | static struct tfp410_platform_data dvi_panel = { |
| @@ -175,8 +160,6 @@ static struct omap_dss_device sdp3430_tv_device = { | |||
| 175 | .driver_name = "venc", | 160 | .driver_name = "venc", |
| 176 | .type = OMAP_DISPLAY_TYPE_VENC, | 161 | .type = OMAP_DISPLAY_TYPE_VENC, |
| 177 | .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO, | 162 | .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO, |
| 178 | .platform_enable = sdp3430_panel_enable_tv, | ||
| 179 | .platform_disable = sdp3430_panel_disable_tv, | ||
| 180 | }; | 163 | }; |
| 181 | 164 | ||
| 182 | 165 | ||
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c index 306df0b40935..56a9a4f855c7 100644 --- a/arch/arm/mach-omap2/board-4430sdp.c +++ b/arch/arm/mach-omap2/board-4430sdp.c | |||
| @@ -291,6 +291,10 @@ static struct platform_device sdp4430_leds_pwm = { | |||
| 291 | }, | 291 | }, |
| 292 | }; | 292 | }; |
| 293 | 293 | ||
| 294 | /* Dummy regulator for pwm-backlight driver */ | ||
| 295 | static struct regulator_consumer_supply backlight_supply = | ||
| 296 | REGULATOR_SUPPLY("enable", "pwm-backlight"); | ||
| 297 | |||
| 294 | static struct platform_pwm_backlight_data sdp4430_backlight_data = { | 298 | static struct platform_pwm_backlight_data sdp4430_backlight_data = { |
| 295 | .max_brightness = 127, | 299 | .max_brightness = 127, |
| 296 | .dft_brightness = 127, | 300 | .dft_brightness = 127, |
| @@ -718,6 +722,8 @@ static void __init omap_4430sdp_init(void) | |||
| 718 | 722 | ||
| 719 | omap4_i2c_init(); | 723 | omap4_i2c_init(); |
| 720 | omap_sfh7741prox_init(); | 724 | omap_sfh7741prox_init(); |
| 725 | regulator_register_always_on(0, "backlight-enable", | ||
| 726 | &backlight_supply, 1, 0); | ||
| 721 | platform_add_devices(sdp4430_devices, ARRAY_SIZE(sdp4430_devices)); | 727 | platform_add_devices(sdp4430_devices, ARRAY_SIZE(sdp4430_devices)); |
| 722 | omap_serial_init(); | 728 | omap_serial_init(); |
| 723 | omap_sdrc_init(NULL, NULL); | 729 | omap_sdrc_init(NULL, NULL); |
diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c index 191f9762ba63..d63f14b534b5 100644 --- a/arch/arm/mach-omap2/board-am3517evm.c +++ b/arch/arm/mach-omap2/board-am3517evm.c | |||
| @@ -35,8 +35,7 @@ | |||
| 35 | 35 | ||
| 36 | #include "common.h" | 36 | #include "common.h" |
| 37 | #include <video/omapdss.h> | 37 | #include <video/omapdss.h> |
| 38 | #include <video/omap-panel-generic-dpi.h> | 38 | #include <video/omap-panel-data.h> |
| 39 | #include <video/omap-panel-tfp410.h> | ||
| 40 | 39 | ||
| 41 | #include "am35xx-emac.h" | 40 | #include "am35xx-emac.h" |
| 42 | #include "mux.h" | 41 | #include "mux.h" |
| @@ -121,63 +120,14 @@ static int __init am3517_evm_i2c_init(void) | |||
| 121 | return 0; | 120 | return 0; |
| 122 | } | 121 | } |
| 123 | 122 | ||
| 124 | static int lcd_enabled; | ||
| 125 | static int dvi_enabled; | ||
| 126 | |||
| 127 | #if defined(CONFIG_PANEL_SHARP_LQ043T1DG01) || \ | ||
| 128 | defined(CONFIG_PANEL_SHARP_LQ043T1DG01_MODULE) | ||
| 129 | static struct gpio am3517_evm_dss_gpios[] __initdata = { | ||
| 130 | /* GPIO 182 = LCD Backlight Power */ | ||
| 131 | { LCD_PANEL_BKLIGHT_PWR, GPIOF_OUT_INIT_HIGH, "lcd_backlight_pwr" }, | ||
| 132 | /* GPIO 181 = LCD Panel PWM */ | ||
| 133 | { LCD_PANEL_PWM, GPIOF_OUT_INIT_HIGH, "lcd bl enable" }, | ||
| 134 | /* GPIO 176 = LCD Panel Power enable pin */ | ||
| 135 | { LCD_PANEL_PWR, GPIOF_OUT_INIT_HIGH, "dvi enable" }, | ||
| 136 | }; | ||
| 137 | |||
| 138 | static void __init am3517_evm_display_init(void) | ||
| 139 | { | ||
| 140 | int r; | ||
| 141 | |||
| 142 | omap_mux_init_gpio(LCD_PANEL_PWR, OMAP_PIN_INPUT_PULLUP); | ||
| 143 | omap_mux_init_gpio(LCD_PANEL_BKLIGHT_PWR, OMAP_PIN_INPUT_PULLDOWN); | ||
| 144 | omap_mux_init_gpio(LCD_PANEL_PWM, OMAP_PIN_INPUT_PULLDOWN); | ||
| 145 | |||
| 146 | r = gpio_request_array(am3517_evm_dss_gpios, | ||
| 147 | ARRAY_SIZE(am3517_evm_dss_gpios)); | ||
| 148 | if (r) { | ||
| 149 | printk(KERN_ERR "failed to get DSS panel control GPIOs\n"); | ||
| 150 | return; | ||
| 151 | } | ||
| 152 | |||
| 153 | printk(KERN_INFO "Display initialized successfully\n"); | ||
| 154 | } | ||
| 155 | #else | ||
| 156 | static void __init am3517_evm_display_init(void) {} | ||
| 157 | #endif | ||
| 158 | |||
| 159 | static int am3517_evm_panel_enable_lcd(struct omap_dss_device *dssdev) | ||
| 160 | { | ||
| 161 | if (dvi_enabled) { | ||
| 162 | printk(KERN_ERR "cannot enable LCD, DVI is enabled\n"); | ||
| 163 | return -EINVAL; | ||
| 164 | } | ||
| 165 | gpio_set_value(LCD_PANEL_PWR, 1); | ||
| 166 | lcd_enabled = 1; | ||
| 167 | |||
| 168 | return 0; | ||
| 169 | } | ||
| 170 | |||
| 171 | static void am3517_evm_panel_disable_lcd(struct omap_dss_device *dssdev) | ||
| 172 | { | ||
| 173 | gpio_set_value(LCD_PANEL_PWR, 0); | ||
| 174 | lcd_enabled = 0; | ||
| 175 | } | ||
| 176 | |||
| 177 | static struct panel_generic_dpi_data lcd_panel = { | 123 | static struct panel_generic_dpi_data lcd_panel = { |
| 178 | .name = "sharp_lq", | 124 | .name = "sharp_lq", |
| 179 | .platform_enable = am3517_evm_panel_enable_lcd, | 125 | .num_gpios = 3, |
| 180 | .platform_disable = am3517_evm_panel_disable_lcd, | 126 | .gpios = { |
| 127 | LCD_PANEL_PWR, | ||
| 128 | LCD_PANEL_BKLIGHT_PWR, | ||
| 129 | LCD_PANEL_PWM, | ||
| 130 | }, | ||
| 181 | }; | 131 | }; |
| 182 | 132 | ||
| 183 | static struct omap_dss_device am3517_evm_lcd_device = { | 133 | static struct omap_dss_device am3517_evm_lcd_device = { |
| @@ -188,22 +138,11 @@ static struct omap_dss_device am3517_evm_lcd_device = { | |||
| 188 | .phy.dpi.data_lines = 16, | 138 | .phy.dpi.data_lines = 16, |
| 189 | }; | 139 | }; |
| 190 | 140 | ||
| 191 | static int am3517_evm_panel_enable_tv(struct omap_dss_device *dssdev) | ||
| 192 | { | ||
| 193 | return 0; | ||
| 194 | } | ||
| 195 | |||
| 196 | static void am3517_evm_panel_disable_tv(struct omap_dss_device *dssdev) | ||
| 197 | { | ||
| 198 | } | ||
| 199 | |||
| 200 | static struct omap_dss_device am3517_evm_tv_device = { | 141 | static struct omap_dss_device am3517_evm_tv_device = { |
| 201 | .type = OMAP_DISPLAY_TYPE_VENC, | 142 | .type = OMAP_DISPLAY_TYPE_VENC, |
| 202 | .name = "tv", | 143 | .name = "tv", |
| 203 | .driver_name = "venc", | 144 | .driver_name = "venc", |
| 204 | .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO, | 145 | .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO, |
| 205 | .platform_enable = am3517_evm_panel_enable_tv, | ||
| 206 | .platform_disable = am3517_evm_panel_disable_tv, | ||
| 207 | }; | 146 | }; |
| 208 | 147 | ||
| 209 | static struct tfp410_platform_data dvi_panel = { | 148 | static struct tfp410_platform_data dvi_panel = { |
| @@ -366,8 +305,6 @@ static void __init am3517_evm_init(void) | |||
| 366 | usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data)); | 305 | usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data)); |
| 367 | usbhs_init(&usbhs_bdata); | 306 | usbhs_init(&usbhs_bdata); |
| 368 | am3517_evm_hecc_init(&am3517_evm_hecc_pdata); | 307 | am3517_evm_hecc_init(&am3517_evm_hecc_pdata); |
| 369 | /* DSS */ | ||
| 370 | am3517_evm_display_init(); | ||
| 371 | 308 | ||
| 372 | /* RTC - S35390A */ | 309 | /* RTC - S35390A */ |
| 373 | am3517_evm_rtc_init(); | 310 | am3517_evm_rtc_init(); |
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c index 7fda3f5f8a7f..ee6218c74807 100644 --- a/arch/arm/mach-omap2/board-cm-t35.c +++ b/arch/arm/mach-omap2/board-cm-t35.c | |||
| @@ -41,8 +41,7 @@ | |||
| 41 | 41 | ||
| 42 | #include <linux/platform_data/mtd-nand-omap2.h> | 42 | #include <linux/platform_data/mtd-nand-omap2.h> |
| 43 | #include <video/omapdss.h> | 43 | #include <video/omapdss.h> |
| 44 | #include <video/omap-panel-generic-dpi.h> | 44 | #include <video/omap-panel-data.h> |
| 45 | #include <video/omap-panel-tfp410.h> | ||
| 46 | #include <linux/platform_data/spi-omap2-mcspi.h> | 45 | #include <linux/platform_data/spi-omap2-mcspi.h> |
| 47 | 46 | ||
| 48 | #include "common.h" | 47 | #include "common.h" |
| @@ -191,45 +190,12 @@ static inline void cm_t35_init_nand(void) {} | |||
| 191 | #define CM_T35_LCD_BL_GPIO 58 | 190 | #define CM_T35_LCD_BL_GPIO 58 |
| 192 | #define CM_T35_DVI_EN_GPIO 54 | 191 | #define CM_T35_DVI_EN_GPIO 54 |
| 193 | 192 | ||
| 194 | static int lcd_enabled; | ||
| 195 | static int dvi_enabled; | ||
| 196 | |||
| 197 | static int cm_t35_panel_enable_lcd(struct omap_dss_device *dssdev) | ||
| 198 | { | ||
| 199 | if (dvi_enabled) { | ||
| 200 | printk(KERN_ERR "cannot enable LCD, DVI is enabled\n"); | ||
| 201 | return -EINVAL; | ||
| 202 | } | ||
| 203 | |||
| 204 | gpio_set_value(CM_T35_LCD_EN_GPIO, 1); | ||
| 205 | gpio_set_value(CM_T35_LCD_BL_GPIO, 1); | ||
| 206 | |||
| 207 | lcd_enabled = 1; | ||
| 208 | |||
| 209 | return 0; | ||
| 210 | } | ||
| 211 | |||
| 212 | static void cm_t35_panel_disable_lcd(struct omap_dss_device *dssdev) | ||
| 213 | { | ||
| 214 | lcd_enabled = 0; | ||
| 215 | |||
| 216 | gpio_set_value(CM_T35_LCD_BL_GPIO, 0); | ||
| 217 | gpio_set_value(CM_T35_LCD_EN_GPIO, 0); | ||
| 218 | } | ||
| 219 | |||
| 220 | static int cm_t35_panel_enable_tv(struct omap_dss_device *dssdev) | ||
| 221 | { | ||
| 222 | return 0; | ||
| 223 | } | ||
| 224 | |||
| 225 | static void cm_t35_panel_disable_tv(struct omap_dss_device *dssdev) | ||
| 226 | { | ||
| 227 | } | ||
| 228 | |||
| 229 | static struct panel_generic_dpi_data lcd_panel = { | 193 | static struct panel_generic_dpi_data lcd_panel = { |
| 230 | .name = "toppoly_tdo35s", | 194 | .name = "toppoly_tdo35s", |
| 231 | .platform_enable = cm_t35_panel_enable_lcd, | 195 | .num_gpios = 1, |
| 232 | .platform_disable = cm_t35_panel_disable_lcd, | 196 | .gpios = { |
| 197 | CM_T35_LCD_BL_GPIO, | ||
| 198 | }, | ||
| 233 | }; | 199 | }; |
| 234 | 200 | ||
| 235 | static struct omap_dss_device cm_t35_lcd_device = { | 201 | static struct omap_dss_device cm_t35_lcd_device = { |
| @@ -258,8 +224,6 @@ static struct omap_dss_device cm_t35_tv_device = { | |||
| 258 | .driver_name = "venc", | 224 | .driver_name = "venc", |
| 259 | .type = OMAP_DISPLAY_TYPE_VENC, | 225 | .type = OMAP_DISPLAY_TYPE_VENC, |
| 260 | .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO, | 226 | .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO, |
| 261 | .platform_enable = cm_t35_panel_enable_tv, | ||
| 262 | .platform_disable = cm_t35_panel_disable_tv, | ||
| 263 | }; | 227 | }; |
| 264 | 228 | ||
| 265 | static struct omap_dss_device *cm_t35_dss_devices[] = { | 229 | static struct omap_dss_device *cm_t35_dss_devices[] = { |
| @@ -293,11 +257,6 @@ static struct spi_board_info cm_t35_lcd_spi_board_info[] __initdata = { | |||
| 293 | }, | 257 | }, |
| 294 | }; | 258 | }; |
| 295 | 259 | ||
| 296 | static struct gpio cm_t35_dss_gpios[] __initdata = { | ||
| 297 | { CM_T35_LCD_EN_GPIO, GPIOF_OUT_INIT_LOW, "lcd enable" }, | ||
| 298 | { CM_T35_LCD_BL_GPIO, GPIOF_OUT_INIT_LOW, "lcd bl enable" }, | ||
| 299 | }; | ||
| 300 | |||
| 301 | static void __init cm_t35_init_display(void) | 260 | static void __init cm_t35_init_display(void) |
| 302 | { | 261 | { |
| 303 | int err; | 262 | int err; |
| @@ -305,23 +264,21 @@ static void __init cm_t35_init_display(void) | |||
| 305 | spi_register_board_info(cm_t35_lcd_spi_board_info, | 264 | spi_register_board_info(cm_t35_lcd_spi_board_info, |
| 306 | ARRAY_SIZE(cm_t35_lcd_spi_board_info)); | 265 | ARRAY_SIZE(cm_t35_lcd_spi_board_info)); |
| 307 | 266 | ||
| 308 | err = gpio_request_array(cm_t35_dss_gpios, | 267 | |
| 309 | ARRAY_SIZE(cm_t35_dss_gpios)); | 268 | err = gpio_request_one(CM_T35_LCD_EN_GPIO, GPIOF_OUT_INIT_LOW, |
| 269 | "lcd bl enable"); | ||
| 310 | if (err) { | 270 | if (err) { |
| 311 | pr_err("CM-T35: failed to request DSS control GPIOs\n"); | 271 | pr_err("CM-T35: failed to request LCD EN GPIO\n"); |
| 312 | return; | 272 | return; |
| 313 | } | 273 | } |
| 314 | 274 | ||
| 315 | gpio_export(CM_T35_LCD_EN_GPIO, 0); | ||
| 316 | gpio_export(CM_T35_LCD_BL_GPIO, 0); | ||
| 317 | |||
| 318 | msleep(50); | 275 | msleep(50); |
| 319 | gpio_set_value(CM_T35_LCD_EN_GPIO, 1); | 276 | gpio_set_value(CM_T35_LCD_EN_GPIO, 1); |
| 320 | 277 | ||
| 321 | err = omap_display_init(&cm_t35_dss_data); | 278 | err = omap_display_init(&cm_t35_dss_data); |
| 322 | if (err) { | 279 | if (err) { |
| 323 | pr_err("CM-T35: failed to register DSS device\n"); | 280 | pr_err("CM-T35: failed to register DSS device\n"); |
| 324 | gpio_free_array(cm_t35_dss_gpios, ARRAY_SIZE(cm_t35_dss_gpios)); | 281 | gpio_free(CM_T35_LCD_EN_GPIO); |
| 325 | } | 282 | } |
| 326 | } | 283 | } |
| 327 | 284 | ||
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c index 42fbf1ef12a9..576420544178 100644 --- a/arch/arm/mach-omap2/board-devkit8000.c +++ b/arch/arm/mach-omap2/board-devkit8000.c | |||
| @@ -43,8 +43,7 @@ | |||
| 43 | #include "gpmc.h" | 43 | #include "gpmc.h" |
| 44 | #include <linux/platform_data/mtd-nand-omap2.h> | 44 | #include <linux/platform_data/mtd-nand-omap2.h> |
| 45 | #include <video/omapdss.h> | 45 | #include <video/omapdss.h> |
| 46 | #include <video/omap-panel-generic-dpi.h> | 46 | #include <video/omap-panel-data.h> |
| 47 | #include <video/omap-panel-tfp410.h> | ||
| 48 | 47 | ||
| 49 | #include <linux/platform_data/spi-omap2-mcspi.h> | 48 | #include <linux/platform_data/spi-omap2-mcspi.h> |
| 50 | #include <linux/input/matrix_keypad.h> | 49 | #include <linux/input/matrix_keypad.h> |
| @@ -104,19 +103,6 @@ static struct omap2_hsmmc_info mmc[] = { | |||
| 104 | {} /* Terminator */ | 103 | {} /* Terminator */ |
| 105 | }; | 104 | }; |
| 106 | 105 | ||
| 107 | static int devkit8000_panel_enable_lcd(struct omap_dss_device *dssdev) | ||
| 108 | { | ||
| 109 | if (gpio_is_valid(dssdev->reset_gpio)) | ||
| 110 | gpio_set_value_cansleep(dssdev->reset_gpio, 1); | ||
| 111 | return 0; | ||
| 112 | } | ||
| 113 | |||
| 114 | static void devkit8000_panel_disable_lcd(struct omap_dss_device *dssdev) | ||
| 115 | { | ||
| 116 | if (gpio_is_valid(dssdev->reset_gpio)) | ||
| 117 | gpio_set_value_cansleep(dssdev->reset_gpio, 0); | ||
| 118 | } | ||
| 119 | |||
| 120 | static struct regulator_consumer_supply devkit8000_vmmc1_supply[] = { | 106 | static struct regulator_consumer_supply devkit8000_vmmc1_supply[] = { |
| 121 | REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"), | 107 | REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"), |
| 122 | }; | 108 | }; |
| @@ -128,8 +114,7 @@ static struct regulator_consumer_supply devkit8000_vio_supply[] = { | |||
| 128 | 114 | ||
| 129 | static struct panel_generic_dpi_data lcd_panel = { | 115 | static struct panel_generic_dpi_data lcd_panel = { |
| 130 | .name = "innolux_at070tn83", | 116 | .name = "innolux_at070tn83", |
| 131 | .platform_enable = devkit8000_panel_enable_lcd, | 117 | /* gpios filled in code */ |
| 132 | .platform_disable = devkit8000_panel_disable_lcd, | ||
| 133 | }; | 118 | }; |
| 134 | 119 | ||
| 135 | static struct omap_dss_device devkit8000_lcd_device = { | 120 | static struct omap_dss_device devkit8000_lcd_device = { |
| @@ -211,8 +196,6 @@ static struct gpio_led gpio_leds[]; | |||
| 211 | static int devkit8000_twl_gpio_setup(struct device *dev, | 196 | static int devkit8000_twl_gpio_setup(struct device *dev, |
| 212 | unsigned gpio, unsigned ngpio) | 197 | unsigned gpio, unsigned ngpio) |
| 213 | { | 198 | { |
| 214 | int ret; | ||
| 215 | |||
| 216 | /* gpio + 0 is "mmc0_cd" (input/IRQ) */ | 199 | /* gpio + 0 is "mmc0_cd" (input/IRQ) */ |
| 217 | mmc[0].gpio_cd = gpio + 0; | 200 | mmc[0].gpio_cd = gpio + 0; |
| 218 | omap_hsmmc_late_init(mmc); | 201 | omap_hsmmc_late_init(mmc); |
| @@ -221,13 +204,8 @@ static int devkit8000_twl_gpio_setup(struct device *dev, | |||
| 221 | gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1; | 204 | gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1; |
| 222 | 205 | ||
| 223 | /* TWL4030_GPIO_MAX + 0 is "LCD_PWREN" (out, active high) */ | 206 | /* TWL4030_GPIO_MAX + 0 is "LCD_PWREN" (out, active high) */ |
| 224 | devkit8000_lcd_device.reset_gpio = gpio + TWL4030_GPIO_MAX + 0; | 207 | lcd_panel.num_gpios = 1; |
| 225 | ret = gpio_request_one(devkit8000_lcd_device.reset_gpio, | 208 | lcd_panel.gpios[0] = gpio + TWL4030_GPIO_MAX + 0; |
| 226 | GPIOF_OUT_INIT_LOW, "LCD_PWREN"); | ||
| 227 | if (ret < 0) { | ||
| 228 | devkit8000_lcd_device.reset_gpio = -EINVAL; | ||
| 229 | printk(KERN_ERR "Failed to request GPIO for LCD_PWRN\n"); | ||
| 230 | } | ||
| 231 | 209 | ||
| 232 | /* gpio + 7 is "DVI_PD" (out, active low) */ | 210 | /* gpio + 7 is "DVI_PD" (out, active low) */ |
| 233 | dvi_panel.power_down_gpio = gpio + 7; | 211 | dvi_panel.power_down_gpio = gpio + 7; |
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c index 5b4ec51c385f..69c0acf5aa63 100644 --- a/arch/arm/mach-omap2/board-h4.c +++ b/arch/arm/mach-omap2/board-h4.c | |||
| @@ -34,7 +34,7 @@ | |||
| 34 | #include <asm/mach/map.h> | 34 | #include <asm/mach/map.h> |
| 35 | 35 | ||
| 36 | #include <video/omapdss.h> | 36 | #include <video/omapdss.h> |
| 37 | #include <video/omap-panel-generic-dpi.h> | 37 | #include <video/omap-panel-data.h> |
| 38 | 38 | ||
| 39 | #include "common.h" | 39 | #include "common.h" |
| 40 | #include "mux.h" | 40 | #include "mux.h" |
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c index 95ccec0eeab9..b54562d1235e 100644 --- a/arch/arm/mach-omap2/board-igep0020.c +++ b/arch/arm/mach-omap2/board-igep0020.c | |||
| @@ -31,7 +31,7 @@ | |||
| 31 | #include <asm/mach/arch.h> | 31 | #include <asm/mach/arch.h> |
| 32 | 32 | ||
| 33 | #include <video/omapdss.h> | 33 | #include <video/omapdss.h> |
| 34 | #include <video/omap-panel-tfp410.h> | 34 | #include <video/omap-panel-data.h> |
| 35 | #include <linux/platform_data/mtd-onenand-omap2.h> | 35 | #include <linux/platform_data/mtd-onenand-omap2.h> |
| 36 | 36 | ||
| 37 | #include "common.h" | 37 | #include "common.h" |
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c index b12fe966a7b9..d0d17bc58d9b 100644 --- a/arch/arm/mach-omap2/board-ldp.c +++ b/arch/arm/mach-omap2/board-ldp.c | |||
| @@ -41,7 +41,7 @@ | |||
| 41 | #include "gpmc-smsc911x.h" | 41 | #include "gpmc-smsc911x.h" |
| 42 | 42 | ||
| 43 | #include <video/omapdss.h> | 43 | #include <video/omapdss.h> |
| 44 | #include <video/omap-panel-generic-dpi.h> | 44 | #include <video/omap-panel-data.h> |
| 45 | 45 | ||
| 46 | #include "board-flash.h" | 46 | #include "board-flash.h" |
| 47 | #include "mux.h" | 47 | #include "mux.h" |
| @@ -181,34 +181,13 @@ static inline void __init ldp_init_smsc911x(void) | |||
| 181 | 181 | ||
| 182 | /* LCD */ | 182 | /* LCD */ |
| 183 | 183 | ||
| 184 | static int ldp_backlight_gpio; | ||
| 185 | static int ldp_lcd_enable_gpio; | ||
| 186 | |||
| 187 | #define LCD_PANEL_RESET_GPIO 55 | 184 | #define LCD_PANEL_RESET_GPIO 55 |
| 188 | #define LCD_PANEL_QVGA_GPIO 56 | 185 | #define LCD_PANEL_QVGA_GPIO 56 |
| 189 | 186 | ||
| 190 | static int ldp_panel_enable_lcd(struct omap_dss_device *dssdev) | ||
| 191 | { | ||
| 192 | if (gpio_is_valid(ldp_lcd_enable_gpio)) | ||
| 193 | gpio_direction_output(ldp_lcd_enable_gpio, 1); | ||
| 194 | if (gpio_is_valid(ldp_backlight_gpio)) | ||
| 195 | gpio_direction_output(ldp_backlight_gpio, 1); | ||
| 196 | |||
| 197 | return 0; | ||
| 198 | } | ||
| 199 | |||
| 200 | static void ldp_panel_disable_lcd(struct omap_dss_device *dssdev) | ||
| 201 | { | ||
| 202 | if (gpio_is_valid(ldp_lcd_enable_gpio)) | ||
| 203 | gpio_direction_output(ldp_lcd_enable_gpio, 0); | ||
| 204 | if (gpio_is_valid(ldp_backlight_gpio)) | ||
| 205 | gpio_direction_output(ldp_backlight_gpio, 0); | ||
| 206 | } | ||
| 207 | |||
| 208 | static struct panel_generic_dpi_data ldp_panel_data = { | 187 | static struct panel_generic_dpi_data ldp_panel_data = { |
| 209 | .name = "nec_nl2432dr22-11b", | 188 | .name = "nec_nl2432dr22-11b", |
| 210 | .platform_enable = ldp_panel_enable_lcd, | 189 | .num_gpios = 4, |
| 211 | .platform_disable = ldp_panel_disable_lcd, | 190 | /* gpios filled in code */ |
| 212 | }; | 191 | }; |
| 213 | 192 | ||
| 214 | static struct omap_dss_device ldp_lcd_device = { | 193 | static struct omap_dss_device ldp_lcd_device = { |
| @@ -231,41 +210,19 @@ static struct omap_dss_board_info ldp_dss_data = { | |||
| 231 | 210 | ||
| 232 | static void __init ldp_display_init(void) | 211 | static void __init ldp_display_init(void) |
| 233 | { | 212 | { |
| 234 | int r; | 213 | ldp_panel_data.gpios[2] = LCD_PANEL_RESET_GPIO; |
| 235 | 214 | ldp_panel_data.gpios[3] = LCD_PANEL_QVGA_GPIO; | |
| 236 | static struct gpio gpios[] __initdata = { | ||
| 237 | {LCD_PANEL_RESET_GPIO, GPIOF_OUT_INIT_HIGH, "LCD RESET"}, | ||
| 238 | {LCD_PANEL_QVGA_GPIO, GPIOF_OUT_INIT_HIGH, "LCD QVGA"}, | ||
| 239 | }; | ||
| 240 | |||
| 241 | r = gpio_request_array(gpios, ARRAY_SIZE(gpios)); | ||
| 242 | if (r) { | ||
| 243 | pr_err("Cannot request LCD GPIOs, error %d\n", r); | ||
| 244 | return; | ||
| 245 | } | ||
| 246 | 215 | ||
| 247 | omap_display_init(&ldp_dss_data); | 216 | omap_display_init(&ldp_dss_data); |
| 248 | } | 217 | } |
| 249 | 218 | ||
| 250 | static int ldp_twl_gpio_setup(struct device *dev, unsigned gpio, unsigned ngpio) | 219 | static int ldp_twl_gpio_setup(struct device *dev, unsigned gpio, unsigned ngpio) |
| 251 | { | 220 | { |
| 252 | int r; | 221 | ldp_panel_data.gpios[0] = gpio + 7; |
| 253 | 222 | ldp_panel_data.gpio_invert[0] = true; | |
| 254 | struct gpio gpios[] = { | 223 | |
| 255 | {gpio + 7 , GPIOF_OUT_INIT_LOW, "LCD ENABLE"}, | 224 | ldp_panel_data.gpios[1] = gpio + 15; |
| 256 | {gpio + 15, GPIOF_OUT_INIT_LOW, "LCD BACKLIGHT"}, | 225 | ldp_panel_data.gpio_invert[1] = true; |
| 257 | }; | ||
| 258 | |||
| 259 | r = gpio_request_array(gpios, ARRAY_SIZE(gpios)); | ||
| 260 | if (r) { | ||
| 261 | pr_err("Cannot request LCD GPIOs, error %d\n", r); | ||
| 262 | ldp_backlight_gpio = -EINVAL; | ||
| 263 | ldp_lcd_enable_gpio = -EINVAL; | ||
| 264 | return r; | ||
| 265 | } | ||
| 266 | |||
| 267 | ldp_backlight_gpio = gpio + 15; | ||
| 268 | ldp_lcd_enable_gpio = gpio + 7; | ||
| 269 | 226 | ||
| 270 | return 0; | 227 | return 0; |
| 271 | } | 228 | } |
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c index 6955a428f534..6de78605c0af 100644 --- a/arch/arm/mach-omap2/board-omap3beagle.c +++ b/arch/arm/mach-omap2/board-omap3beagle.c | |||
| @@ -44,7 +44,7 @@ | |||
| 44 | #include <asm/mach/flash.h> | 44 | #include <asm/mach/flash.h> |
| 45 | 45 | ||
| 46 | #include <video/omapdss.h> | 46 | #include <video/omapdss.h> |
| 47 | #include <video/omap-panel-tfp410.h> | 47 | #include <video/omap-panel-data.h> |
| 48 | #include <linux/platform_data/mtd-nand-omap2.h> | 48 | #include <linux/platform_data/mtd-nand-omap2.h> |
| 49 | 49 | ||
| 50 | #include "common.h" | 50 | #include "common.h" |
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c index 2de92facc8a3..f76d0de7b406 100644 --- a/arch/arm/mach-omap2/board-omap3evm.c +++ b/arch/arm/mach-omap2/board-omap3evm.c | |||
| @@ -51,7 +51,7 @@ | |||
| 51 | #include "common.h" | 51 | #include "common.h" |
| 52 | #include <linux/platform_data/spi-omap2-mcspi.h> | 52 | #include <linux/platform_data/spi-omap2-mcspi.h> |
| 53 | #include <video/omapdss.h> | 53 | #include <video/omapdss.h> |
| 54 | #include <video/omap-panel-tfp410.h> | 54 | #include <video/omap-panel-data.h> |
| 55 | 55 | ||
| 56 | #include "soc.h" | 56 | #include "soc.h" |
| 57 | #include "mux.h" | 57 | #include "mux.h" |
| @@ -155,61 +155,43 @@ static inline void __init omap3evm_init_smsc911x(void) { return; } | |||
| 155 | #define OMAP3EVM_LCD_PANEL_LR 2 | 155 | #define OMAP3EVM_LCD_PANEL_LR 2 |
| 156 | #define OMAP3EVM_LCD_PANEL_UD 3 | 156 | #define OMAP3EVM_LCD_PANEL_UD 3 |
| 157 | #define OMAP3EVM_LCD_PANEL_INI 152 | 157 | #define OMAP3EVM_LCD_PANEL_INI 152 |
| 158 | #define OMAP3EVM_LCD_PANEL_ENVDD 153 | ||
| 159 | #define OMAP3EVM_LCD_PANEL_QVGA 154 | 158 | #define OMAP3EVM_LCD_PANEL_QVGA 154 |
| 160 | #define OMAP3EVM_LCD_PANEL_RESB 155 | 159 | #define OMAP3EVM_LCD_PANEL_RESB 155 |
| 160 | |||
| 161 | #define OMAP3EVM_LCD_PANEL_ENVDD 153 | ||
| 161 | #define OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO 210 | 162 | #define OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO 210 |
| 163 | |||
| 164 | /* | ||
| 165 | * OMAP3EVM DVI control signals | ||
| 166 | */ | ||
| 162 | #define OMAP3EVM_DVI_PANEL_EN_GPIO 199 | 167 | #define OMAP3EVM_DVI_PANEL_EN_GPIO 199 |
| 163 | 168 | ||
| 164 | static struct gpio omap3_evm_dss_gpios[] __initdata = { | 169 | static struct panel_sharp_ls037v7dw01_data omap3_evm_lcd_data = { |
| 165 | { OMAP3EVM_LCD_PANEL_RESB, GPIOF_OUT_INIT_HIGH, "lcd_panel_resb" }, | 170 | .resb_gpio = OMAP3EVM_LCD_PANEL_RESB, |
| 166 | { OMAP3EVM_LCD_PANEL_INI, GPIOF_OUT_INIT_HIGH, "lcd_panel_ini" }, | 171 | .ini_gpio = OMAP3EVM_LCD_PANEL_INI, |
| 167 | { OMAP3EVM_LCD_PANEL_QVGA, GPIOF_OUT_INIT_LOW, "lcd_panel_qvga" }, | 172 | .mo_gpio = OMAP3EVM_LCD_PANEL_QVGA, |
| 168 | { OMAP3EVM_LCD_PANEL_LR, GPIOF_OUT_INIT_HIGH, "lcd_panel_lr" }, | 173 | .lr_gpio = OMAP3EVM_LCD_PANEL_LR, |
| 169 | { OMAP3EVM_LCD_PANEL_UD, GPIOF_OUT_INIT_HIGH, "lcd_panel_ud" }, | 174 | .ud_gpio = OMAP3EVM_LCD_PANEL_UD, |
| 170 | { OMAP3EVM_LCD_PANEL_ENVDD, GPIOF_OUT_INIT_LOW, "lcd_panel_envdd" }, | ||
| 171 | }; | 175 | }; |
| 172 | 176 | ||
| 173 | static int lcd_enabled; | ||
| 174 | static int dvi_enabled; | ||
| 175 | |||
| 176 | static void __init omap3_evm_display_init(void) | 177 | static void __init omap3_evm_display_init(void) |
| 177 | { | 178 | { |
| 178 | int r; | 179 | int r; |
| 179 | 180 | ||
| 180 | r = gpio_request_array(omap3_evm_dss_gpios, | 181 | r = gpio_request_one(OMAP3EVM_LCD_PANEL_ENVDD, GPIOF_OUT_INIT_LOW, |
| 181 | ARRAY_SIZE(omap3_evm_dss_gpios)); | 182 | "lcd_panel_envdd"); |
| 182 | if (r) | 183 | if (r) |
| 183 | printk(KERN_ERR "failed to get lcd_panel_* gpios\n"); | 184 | pr_err("failed to get lcd_panel_envdd GPIO\n"); |
| 184 | } | ||
| 185 | 185 | ||
| 186 | static int omap3_evm_enable_lcd(struct omap_dss_device *dssdev) | 186 | r = gpio_request_one(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, |
| 187 | { | 187 | GPIOF_OUT_INIT_LOW, "lcd_panel_bklight"); |
| 188 | if (dvi_enabled) { | 188 | if (r) |
| 189 | printk(KERN_ERR "cannot enable LCD, DVI is enabled\n"); | 189 | pr_err("failed to get lcd_panel_bklight GPIO\n"); |
| 190 | return -EINVAL; | ||
| 191 | } | ||
| 192 | gpio_set_value(OMAP3EVM_LCD_PANEL_ENVDD, 0); | ||
| 193 | 190 | ||
| 194 | if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2) | 191 | if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2) |
| 195 | gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 0); | 192 | gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 0); |
| 196 | else | 193 | else |
| 197 | gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 1); | 194 | gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 1); |
| 198 | |||
| 199 | lcd_enabled = 1; | ||
| 200 | return 0; | ||
| 201 | } | ||
| 202 | |||
| 203 | static void omap3_evm_disable_lcd(struct omap_dss_device *dssdev) | ||
| 204 | { | ||
| 205 | gpio_set_value(OMAP3EVM_LCD_PANEL_ENVDD, 1); | ||
| 206 | |||
| 207 | if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2) | ||
| 208 | gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 1); | ||
| 209 | else | ||
| 210 | gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 0); | ||
| 211 | |||
| 212 | lcd_enabled = 0; | ||
| 213 | } | 195 | } |
| 214 | 196 | ||
| 215 | static struct omap_dss_device omap3_evm_lcd_device = { | 197 | static struct omap_dss_device omap3_evm_lcd_device = { |
| @@ -217,26 +199,14 @@ static struct omap_dss_device omap3_evm_lcd_device = { | |||
| 217 | .driver_name = "sharp_ls_panel", | 199 | .driver_name = "sharp_ls_panel", |
| 218 | .type = OMAP_DISPLAY_TYPE_DPI, | 200 | .type = OMAP_DISPLAY_TYPE_DPI, |
| 219 | .phy.dpi.data_lines = 18, | 201 | .phy.dpi.data_lines = 18, |
| 220 | .platform_enable = omap3_evm_enable_lcd, | 202 | .data = &omap3_evm_lcd_data, |
| 221 | .platform_disable = omap3_evm_disable_lcd, | ||
| 222 | }; | 203 | }; |
| 223 | 204 | ||
| 224 | static int omap3_evm_enable_tv(struct omap_dss_device *dssdev) | ||
| 225 | { | ||
| 226 | return 0; | ||
| 227 | } | ||
| 228 | |||
| 229 | static void omap3_evm_disable_tv(struct omap_dss_device *dssdev) | ||
| 230 | { | ||
| 231 | } | ||
| 232 | |||
| 233 | static struct omap_dss_device omap3_evm_tv_device = { | 205 | static struct omap_dss_device omap3_evm_tv_device = { |
| 234 | .name = "tv", | 206 | .name = "tv", |
| 235 | .driver_name = "venc", | 207 | .driver_name = "venc", |
| 236 | .type = OMAP_DISPLAY_TYPE_VENC, | 208 | .type = OMAP_DISPLAY_TYPE_VENC, |
| 237 | .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO, | 209 | .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO, |
| 238 | .platform_enable = omap3_evm_enable_tv, | ||
| 239 | .platform_disable = omap3_evm_disable_tv, | ||
| 240 | }; | 210 | }; |
| 241 | 211 | ||
| 242 | static struct tfp410_platform_data dvi_panel = { | 212 | static struct tfp410_platform_data dvi_panel = { |
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c index 1004d2aaa68f..28133d5b4fed 100644 --- a/arch/arm/mach-omap2/board-omap3pandora.c +++ b/arch/arm/mach-omap2/board-omap3pandora.c | |||
| @@ -44,6 +44,7 @@ | |||
| 44 | 44 | ||
| 45 | #include "common.h" | 45 | #include "common.h" |
| 46 | #include <video/omapdss.h> | 46 | #include <video/omapdss.h> |
| 47 | #include <video/omap-panel-data.h> | ||
| 47 | #include <linux/platform_data/mtd-nand-omap2.h> | 48 | #include <linux/platform_data/mtd-nand-omap2.h> |
| 48 | 49 | ||
| 49 | #include "mux.h" | 50 | #include "mux.h" |
| @@ -230,12 +231,16 @@ static struct twl4030_keypad_data pandora_kp_data = { | |||
| 230 | .rep = 1, | 231 | .rep = 1, |
| 231 | }; | 232 | }; |
| 232 | 233 | ||
| 234 | static struct panel_tpo_td043_data lcd_data = { | ||
| 235 | .nreset_gpio = 157, | ||
| 236 | }; | ||
| 237 | |||
| 233 | static struct omap_dss_device pandora_lcd_device = { | 238 | static struct omap_dss_device pandora_lcd_device = { |
| 234 | .name = "lcd", | 239 | .name = "lcd", |
| 235 | .driver_name = "tpo_td043mtea1_panel", | 240 | .driver_name = "tpo_td043mtea1_panel", |
| 236 | .type = OMAP_DISPLAY_TYPE_DPI, | 241 | .type = OMAP_DISPLAY_TYPE_DPI, |
| 237 | .phy.dpi.data_lines = 24, | 242 | .phy.dpi.data_lines = 24, |
| 238 | .reset_gpio = 157, | 243 | .data = &lcd_data, |
| 239 | }; | 244 | }; |
| 240 | 245 | ||
| 241 | static struct omap_dss_device pandora_tv_device = { | 246 | static struct omap_dss_device pandora_tv_device = { |
diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c index bf0956489899..d37e6b187ae4 100644 --- a/arch/arm/mach-omap2/board-omap3stalker.c +++ b/arch/arm/mach-omap2/board-omap3stalker.c | |||
| @@ -44,8 +44,7 @@ | |||
| 44 | #include "gpmc.h" | 44 | #include "gpmc.h" |
| 45 | #include <linux/platform_data/mtd-nand-omap2.h> | 45 | #include <linux/platform_data/mtd-nand-omap2.h> |
| 46 | #include <video/omapdss.h> | 46 | #include <video/omapdss.h> |
| 47 | #include <video/omap-panel-generic-dpi.h> | 47 | #include <video/omap-panel-data.h> |
| 48 | #include <video/omap-panel-tfp410.h> | ||
| 49 | 48 | ||
| 50 | #include <linux/platform_data/spi-omap2-mcspi.h> | 49 | #include <linux/platform_data/spi-omap2-mcspi.h> |
| 51 | 50 | ||
| @@ -95,15 +94,6 @@ static void __init omap3_stalker_display_init(void) | |||
| 95 | return; | 94 | return; |
| 96 | } | 95 | } |
| 97 | 96 | ||
| 98 | static int omap3_stalker_enable_tv(struct omap_dss_device *dssdev) | ||
| 99 | { | ||
| 100 | return 0; | ||
| 101 | } | ||
| 102 | |||
| 103 | static void omap3_stalker_disable_tv(struct omap_dss_device *dssdev) | ||
| 104 | { | ||
| 105 | } | ||
| 106 | |||
| 107 | static struct omap_dss_device omap3_stalker_tv_device = { | 97 | static struct omap_dss_device omap3_stalker_tv_device = { |
| 108 | .name = "tv", | 98 | .name = "tv", |
| 109 | .driver_name = "venc", | 99 | .driver_name = "venc", |
| @@ -113,8 +103,6 @@ static struct omap_dss_device omap3_stalker_tv_device = { | |||
| 113 | #elif defined(CONFIG_OMAP2_VENC_OUT_TYPE_COMPOSITE) | 103 | #elif defined(CONFIG_OMAP2_VENC_OUT_TYPE_COMPOSITE) |
| 114 | .u.venc.type = OMAP_DSS_VENC_TYPE_COMPOSITE, | 104 | .u.venc.type = OMAP_DSS_VENC_TYPE_COMPOSITE, |
| 115 | #endif | 105 | #endif |
| 116 | .platform_enable = omap3_stalker_enable_tv, | ||
| 117 | .platform_disable = omap3_stalker_disable_tv, | ||
| 118 | }; | 106 | }; |
| 119 | 107 | ||
| 120 | static struct tfp410_platform_data dvi_panel = { | 108 | static struct tfp410_platform_data dvi_panel = { |
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c index ab79a4422bcc..4ca6b680aa72 100644 --- a/arch/arm/mach-omap2/board-overo.c +++ b/arch/arm/mach-omap2/board-overo.c | |||
| @@ -47,8 +47,7 @@ | |||
| 47 | #include <asm/mach/map.h> | 47 | #include <asm/mach/map.h> |
| 48 | 48 | ||
| 49 | #include <video/omapdss.h> | 49 | #include <video/omapdss.h> |
| 50 | #include <video/omap-panel-generic-dpi.h> | 50 | #include <video/omap-panel-data.h> |
| 51 | #include <video/omap-panel-tfp410.h> | ||
| 52 | 51 | ||
| 53 | #include "common.h" | 52 | #include "common.h" |
| 54 | #include "mux.h" | 53 | #include "mux.h" |
| @@ -146,28 +145,9 @@ static inline void __init overo_init_smsc911x(void) { return; } | |||
| 146 | #endif | 145 | #endif |
| 147 | 146 | ||
| 148 | /* DSS */ | 147 | /* DSS */ |
| 149 | static int lcd_enabled; | ||
| 150 | static int dvi_enabled; | ||
| 151 | |||
| 152 | #define OVERO_GPIO_LCD_EN 144 | 148 | #define OVERO_GPIO_LCD_EN 144 |
| 153 | #define OVERO_GPIO_LCD_BL 145 | 149 | #define OVERO_GPIO_LCD_BL 145 |
| 154 | 150 | ||
| 155 | static struct gpio overo_dss_gpios[] __initdata = { | ||
| 156 | { OVERO_GPIO_LCD_EN, GPIOF_OUT_INIT_HIGH, "OVERO_GPIO_LCD_EN" }, | ||
| 157 | { OVERO_GPIO_LCD_BL, GPIOF_OUT_INIT_HIGH, "OVERO_GPIO_LCD_BL" }, | ||
| 158 | }; | ||
| 159 | |||
| 160 | static void __init overo_display_init(void) | ||
| 161 | { | ||
| 162 | if (gpio_request_array(overo_dss_gpios, ARRAY_SIZE(overo_dss_gpios))) { | ||
| 163 | printk(KERN_ERR "could not obtain DSS control GPIOs\n"); | ||
| 164 | return; | ||
| 165 | } | ||
| 166 | |||
| 167 | gpio_export(OVERO_GPIO_LCD_EN, 0); | ||
| 168 | gpio_export(OVERO_GPIO_LCD_BL, 0); | ||
| 169 | } | ||
| 170 | |||
| 171 | static struct tfp410_platform_data dvi_panel = { | 151 | static struct tfp410_platform_data dvi_panel = { |
| 172 | .i2c_bus_num = 3, | 152 | .i2c_bus_num = 3, |
| 173 | .power_down_gpio = -1, | 153 | .power_down_gpio = -1, |
| @@ -188,30 +168,13 @@ static struct omap_dss_device overo_tv_device = { | |||
| 188 | .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO, | 168 | .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO, |
| 189 | }; | 169 | }; |
| 190 | 170 | ||
| 191 | static int overo_panel_enable_lcd(struct omap_dss_device *dssdev) | ||
| 192 | { | ||
| 193 | if (dvi_enabled) { | ||
| 194 | printk(KERN_ERR "cannot enable LCD, DVI is enabled\n"); | ||
| 195 | return -EINVAL; | ||
| 196 | } | ||
| 197 | |||
| 198 | gpio_set_value(OVERO_GPIO_LCD_EN, 1); | ||
| 199 | gpio_set_value(OVERO_GPIO_LCD_BL, 1); | ||
| 200 | lcd_enabled = 1; | ||
| 201 | return 0; | ||
| 202 | } | ||
| 203 | |||
| 204 | static void overo_panel_disable_lcd(struct omap_dss_device *dssdev) | ||
| 205 | { | ||
| 206 | gpio_set_value(OVERO_GPIO_LCD_EN, 0); | ||
| 207 | gpio_set_value(OVERO_GPIO_LCD_BL, 0); | ||
| 208 | lcd_enabled = 0; | ||
| 209 | } | ||
| 210 | |||
| 211 | static struct panel_generic_dpi_data lcd43_panel = { | 171 | static struct panel_generic_dpi_data lcd43_panel = { |
| 212 | .name = "samsung_lte430wq_f0c", | 172 | .name = "samsung_lte430wq_f0c", |
| 213 | .platform_enable = overo_panel_enable_lcd, | 173 | .num_gpios = 2, |
| 214 | .platform_disable = overo_panel_disable_lcd, | 174 | .gpios = { |
| 175 | OVERO_GPIO_LCD_EN, | ||
| 176 | OVERO_GPIO_LCD_BL | ||
| 177 | }, | ||
| 215 | }; | 178 | }; |
| 216 | 179 | ||
| 217 | static struct omap_dss_device overo_lcd43_device = { | 180 | static struct omap_dss_device overo_lcd43_device = { |
| @@ -224,13 +187,20 @@ static struct omap_dss_device overo_lcd43_device = { | |||
| 224 | 187 | ||
| 225 | #if defined(CONFIG_PANEL_LGPHILIPS_LB035Q02) || \ | 188 | #if defined(CONFIG_PANEL_LGPHILIPS_LB035Q02) || \ |
| 226 | defined(CONFIG_PANEL_LGPHILIPS_LB035Q02_MODULE) | 189 | defined(CONFIG_PANEL_LGPHILIPS_LB035Q02_MODULE) |
| 190 | static struct panel_generic_dpi_data lcd35_panel = { | ||
| 191 | .num_gpios = 2, | ||
| 192 | .gpios = { | ||
| 193 | OVERO_GPIO_LCD_EN, | ||
| 194 | OVERO_GPIO_LCD_BL | ||
| 195 | }, | ||
| 196 | }; | ||
| 197 | |||
| 227 | static struct omap_dss_device overo_lcd35_device = { | 198 | static struct omap_dss_device overo_lcd35_device = { |
| 228 | .type = OMAP_DISPLAY_TYPE_DPI, | 199 | .type = OMAP_DISPLAY_TYPE_DPI, |
| 229 | .name = "lcd35", | 200 | .name = "lcd35", |
| 230 | .driver_name = "lgphilips_lb035q02_panel", | 201 | .driver_name = "lgphilips_lb035q02_panel", |
| 231 | .phy.dpi.data_lines = 24, | 202 | .phy.dpi.data_lines = 24, |
| 232 | .platform_enable = overo_panel_enable_lcd, | 203 | .data = &lcd35_panel, |
| 233 | .platform_disable = overo_panel_disable_lcd, | ||
| 234 | }; | 204 | }; |
| 235 | #endif | 205 | #endif |
| 236 | 206 | ||
| @@ -509,7 +479,6 @@ static void __init overo_init(void) | |||
| 509 | usbhs_init(&usbhs_bdata); | 479 | usbhs_init(&usbhs_bdata); |
| 510 | overo_spi_init(); | 480 | overo_spi_init(); |
| 511 | overo_init_smsc911x(); | 481 | overo_init_smsc911x(); |
| 512 | overo_display_init(); | ||
| 513 | overo_init_led(); | 482 | overo_init_led(); |
| 514 | overo_init_keys(); | 483 | overo_init_keys(); |
| 515 | omap_twl4030_audio_init("overo", NULL); | 484 | omap_twl4030_audio_init("overo", NULL); |
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c index 3a077df6b8df..1a884670a6c4 100644 --- a/arch/arm/mach-omap2/board-rx51-peripherals.c +++ b/arch/arm/mach-omap2/board-rx51-peripherals.c | |||
| @@ -547,12 +547,16 @@ static struct regulator_consumer_supply rx51_vio_supplies[] = { | |||
| 547 | REGULATOR_SUPPLY("DVDD", "2-0019"), | 547 | REGULATOR_SUPPLY("DVDD", "2-0019"), |
| 548 | /* Si4713 IO supply */ | 548 | /* Si4713 IO supply */ |
| 549 | REGULATOR_SUPPLY("vio", "2-0063"), | 549 | REGULATOR_SUPPLY("vio", "2-0063"), |
| 550 | /* lis3lv02d */ | ||
| 551 | REGULATOR_SUPPLY("Vdd_IO", "3-001d"), | ||
| 550 | }; | 552 | }; |
| 551 | 553 | ||
| 552 | static struct regulator_consumer_supply rx51_vaux1_consumers[] = { | 554 | static struct regulator_consumer_supply rx51_vaux1_consumers[] = { |
| 553 | REGULATOR_SUPPLY("vdds_sdi", "omapdss"), | 555 | REGULATOR_SUPPLY("vdds_sdi", "omapdss"), |
| 554 | /* Si4713 supply */ | 556 | /* Si4713 supply */ |
| 555 | REGULATOR_SUPPLY("vdd", "2-0063"), | 557 | REGULATOR_SUPPLY("vdd", "2-0063"), |
| 558 | /* lis3lv02d */ | ||
| 559 | REGULATOR_SUPPLY("Vdd", "3-001d"), | ||
| 556 | }; | 560 | }; |
| 557 | 561 | ||
| 558 | static struct regulator_init_data rx51_vaux1 = { | 562 | static struct regulator_init_data rx51_vaux1 = { |
diff --git a/arch/arm/mach-omap2/board-rx51-video.c b/arch/arm/mach-omap2/board-rx51-video.c index eb667261df08..bd74f9f6063b 100644 --- a/arch/arm/mach-omap2/board-rx51-video.c +++ b/arch/arm/mach-omap2/board-rx51-video.c | |||
| @@ -16,6 +16,8 @@ | |||
| 16 | #include <linux/mm.h> | 16 | #include <linux/mm.h> |
| 17 | #include <asm/mach-types.h> | 17 | #include <asm/mach-types.h> |
| 18 | #include <video/omapdss.h> | 18 | #include <video/omapdss.h> |
| 19 | #include <video/omap-panel-data.h> | ||
| 20 | |||
| 19 | #include <linux/platform_data/spi-omap2-mcspi.h> | 21 | #include <linux/platform_data/spi-omap2-mcspi.h> |
| 20 | 22 | ||
| 21 | #include "soc.h" | 23 | #include "soc.h" |
| @@ -27,25 +29,16 @@ | |||
| 27 | 29 | ||
| 28 | #if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE) | 30 | #if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE) |
| 29 | 31 | ||
| 30 | static int rx51_lcd_enable(struct omap_dss_device *dssdev) | 32 | static struct panel_acx565akm_data lcd_data = { |
| 31 | { | 33 | .reset_gpio = RX51_LCD_RESET_GPIO, |
| 32 | gpio_set_value(dssdev->reset_gpio, 1); | 34 | }; |
| 33 | return 0; | ||
| 34 | } | ||
| 35 | |||
| 36 | static void rx51_lcd_disable(struct omap_dss_device *dssdev) | ||
| 37 | { | ||
| 38 | gpio_set_value(dssdev->reset_gpio, 0); | ||
| 39 | } | ||
| 40 | 35 | ||
| 41 | static struct omap_dss_device rx51_lcd_device = { | 36 | static struct omap_dss_device rx51_lcd_device = { |
| 42 | .name = "lcd", | 37 | .name = "lcd", |
| 43 | .driver_name = "panel-acx565akm", | 38 | .driver_name = "panel-acx565akm", |
| 44 | .type = OMAP_DISPLAY_TYPE_SDI, | 39 | .type = OMAP_DISPLAY_TYPE_SDI, |
| 45 | .phy.sdi.datapairs = 2, | 40 | .phy.sdi.datapairs = 2, |
| 46 | .reset_gpio = RX51_LCD_RESET_GPIO, | 41 | .data = &lcd_data, |
| 47 | .platform_enable = rx51_lcd_enable, | ||
| 48 | .platform_disable = rx51_lcd_disable, | ||
| 49 | }; | 42 | }; |
| 50 | 43 | ||
| 51 | static struct omap_dss_device rx51_tv_device = { | 44 | static struct omap_dss_device rx51_tv_device = { |
| @@ -76,13 +69,8 @@ static int __init rx51_video_init(void) | |||
| 76 | return 0; | 69 | return 0; |
| 77 | } | 70 | } |
| 78 | 71 | ||
| 79 | if (gpio_request_one(RX51_LCD_RESET_GPIO, GPIOF_OUT_INIT_HIGH, | ||
| 80 | "LCD ACX565AKM reset")) { | ||
| 81 | pr_err("%s failed to get LCD Reset GPIO\n", __func__); | ||
| 82 | return 0; | ||
| 83 | } | ||
| 84 | |||
| 85 | omap_display_init(&rx51_dss_board_info); | 72 | omap_display_init(&rx51_dss_board_info); |
| 73 | |||
| 86 | return 0; | 74 | return 0; |
| 87 | } | 75 | } |
| 88 | 76 | ||
diff --git a/arch/arm/mach-omap2/board-zoom-display.c b/arch/arm/mach-omap2/board-zoom-display.c index 8cef477d6b00..c2a079cb76fc 100644 --- a/arch/arm/mach-omap2/board-zoom-display.c +++ b/arch/arm/mach-omap2/board-zoom-display.c | |||
| @@ -12,12 +12,12 @@ | |||
| 12 | #include <linux/init.h> | 12 | #include <linux/init.h> |
| 13 | #include <linux/platform_device.h> | 13 | #include <linux/platform_device.h> |
| 14 | #include <linux/gpio.h> | 14 | #include <linux/gpio.h> |
| 15 | #include <linux/i2c/twl.h> | ||
| 16 | #include <linux/spi/spi.h> | 15 | #include <linux/spi/spi.h> |
| 17 | #include <linux/platform_data/spi-omap2-mcspi.h> | 16 | #include <linux/platform_data/spi-omap2-mcspi.h> |
| 18 | #include <video/omapdss.h> | 17 | #include <video/omapdss.h> |
| 19 | #include "board-zoom.h" | 18 | #include <video/omap-panel-data.h> |
| 20 | 19 | ||
| 20 | #include "board-zoom.h" | ||
| 21 | #include "soc.h" | 21 | #include "soc.h" |
| 22 | #include "common.h" | 22 | #include "common.h" |
| 23 | 23 | ||
| @@ -25,92 +25,17 @@ | |||
| 25 | #define LCD_PANEL_RESET_GPIO_PILOT 55 | 25 | #define LCD_PANEL_RESET_GPIO_PILOT 55 |
| 26 | #define LCD_PANEL_QVGA_GPIO 56 | 26 | #define LCD_PANEL_QVGA_GPIO 56 |
| 27 | 27 | ||
| 28 | static struct gpio zoom_lcd_gpios[] __initdata = { | 28 | static struct panel_nec_nl8048_data zoom_lcd_data = { |
| 29 | { -EINVAL, GPIOF_OUT_INIT_HIGH, "lcd reset" }, | 29 | /* res_gpio filled in code */ |
| 30 | { LCD_PANEL_QVGA_GPIO, GPIOF_OUT_INIT_HIGH, "lcd qvga" }, | 30 | .qvga_gpio = LCD_PANEL_QVGA_GPIO, |
| 31 | }; | 31 | }; |
| 32 | 32 | ||
| 33 | static void __init zoom_lcd_panel_init(void) | ||
| 34 | { | ||
| 35 | zoom_lcd_gpios[0].gpio = (omap_rev() > OMAP3430_REV_ES3_0) ? | ||
| 36 | LCD_PANEL_RESET_GPIO_PROD : | ||
| 37 | LCD_PANEL_RESET_GPIO_PILOT; | ||
| 38 | |||
| 39 | if (gpio_request_array(zoom_lcd_gpios, ARRAY_SIZE(zoom_lcd_gpios))) | ||
| 40 | pr_err("%s: Failed to get LCD GPIOs.\n", __func__); | ||
| 41 | } | ||
| 42 | |||
| 43 | static int zoom_panel_enable_lcd(struct omap_dss_device *dssdev) | ||
| 44 | { | ||
| 45 | return 0; | ||
| 46 | } | ||
| 47 | |||
| 48 | static void zoom_panel_disable_lcd(struct omap_dss_device *dssdev) | ||
| 49 | { | ||
| 50 | } | ||
| 51 | |||
| 52 | /* Register offsets in TWL4030_MODULE_INTBR */ | ||
| 53 | #define TWL_INTBR_PMBR1 0xD | ||
| 54 | #define TWL_INTBR_GPBR1 0xC | ||
| 55 | |||
| 56 | /* Register offsets in TWL_MODULE_PWM */ | ||
| 57 | #define TWL_LED_PWMON 0x3 | ||
| 58 | #define TWL_LED_PWMOFF 0x4 | ||
| 59 | |||
| 60 | static int zoom_set_bl_intensity(struct omap_dss_device *dssdev, int level) | ||
| 61 | { | ||
| 62 | #ifdef CONFIG_TWL4030_CORE | ||
| 63 | unsigned char c; | ||
| 64 | u8 mux_pwm, enb_pwm; | ||
| 65 | |||
| 66 | if (level > 100) | ||
| 67 | return -1; | ||
| 68 | |||
| 69 | twl_i2c_read_u8(TWL4030_MODULE_INTBR, &mux_pwm, TWL_INTBR_PMBR1); | ||
| 70 | twl_i2c_read_u8(TWL4030_MODULE_INTBR, &enb_pwm, TWL_INTBR_GPBR1); | ||
| 71 | |||
| 72 | if (level == 0) { | ||
| 73 | /* disable pwm1 output and clock */ | ||
| 74 | enb_pwm = enb_pwm & 0xF5; | ||
| 75 | /* change pwm1 pin to gpio pin */ | ||
| 76 | mux_pwm = mux_pwm & 0xCF; | ||
| 77 | twl_i2c_write_u8(TWL4030_MODULE_INTBR, | ||
| 78 | enb_pwm, TWL_INTBR_GPBR1); | ||
| 79 | twl_i2c_write_u8(TWL4030_MODULE_INTBR, | ||
| 80 | mux_pwm, TWL_INTBR_PMBR1); | ||
| 81 | return 0; | ||
| 82 | } | ||
| 83 | |||
| 84 | if (!((enb_pwm & 0xA) && (mux_pwm & 0x30))) { | ||
| 85 | /* change gpio pin to pwm1 pin */ | ||
| 86 | mux_pwm = mux_pwm | 0x30; | ||
| 87 | /* enable pwm1 output and clock*/ | ||
| 88 | enb_pwm = enb_pwm | 0x0A; | ||
| 89 | twl_i2c_write_u8(TWL4030_MODULE_INTBR, | ||
| 90 | mux_pwm, TWL_INTBR_PMBR1); | ||
| 91 | twl_i2c_write_u8(TWL4030_MODULE_INTBR, | ||
| 92 | enb_pwm, TWL_INTBR_GPBR1); | ||
| 93 | } | ||
| 94 | |||
| 95 | c = ((50 * (100 - level)) / 100) + 1; | ||
| 96 | twl_i2c_write_u8(TWL_MODULE_PWM, 0x7F, TWL_LED_PWMOFF); | ||
| 97 | twl_i2c_write_u8(TWL_MODULE_PWM, c, TWL_LED_PWMON); | ||
| 98 | #else | ||
| 99 | pr_warn("Backlight not enabled\n"); | ||
| 100 | #endif | ||
| 101 | |||
| 102 | return 0; | ||
| 103 | } | ||
| 104 | |||
| 105 | static struct omap_dss_device zoom_lcd_device = { | 33 | static struct omap_dss_device zoom_lcd_device = { |
| 106 | .name = "lcd", | 34 | .name = "lcd", |
| 107 | .driver_name = "NEC_8048_panel", | 35 | .driver_name = "NEC_8048_panel", |
| 108 | .type = OMAP_DISPLAY_TYPE_DPI, | 36 | .type = OMAP_DISPLAY_TYPE_DPI, |
| 109 | .phy.dpi.data_lines = 24, | 37 | .phy.dpi.data_lines = 24, |
| 110 | .platform_enable = zoom_panel_enable_lcd, | 38 | .data = &zoom_lcd_data, |
| 111 | .platform_disable = zoom_panel_disable_lcd, | ||
| 112 | .max_backlight_level = 100, | ||
| 113 | .set_backlight = zoom_set_bl_intensity, | ||
| 114 | }; | 39 | }; |
| 115 | 40 | ||
| 116 | static struct omap_dss_device *zoom_dss_devices[] = { | 41 | static struct omap_dss_device *zoom_dss_devices[] = { |
| @@ -123,6 +48,13 @@ static struct omap_dss_board_info zoom_dss_data = { | |||
| 123 | .default_device = &zoom_lcd_device, | 48 | .default_device = &zoom_lcd_device, |
| 124 | }; | 49 | }; |
| 125 | 50 | ||
| 51 | static void __init zoom_lcd_panel_init(void) | ||
| 52 | { | ||
| 53 | zoom_lcd_data.res_gpio = (omap_rev() > OMAP3430_REV_ES3_0) ? | ||
| 54 | LCD_PANEL_RESET_GPIO_PROD : | ||
| 55 | LCD_PANEL_RESET_GPIO_PILOT; | ||
| 56 | } | ||
| 57 | |||
| 126 | static struct omap2_mcspi_device_config dss_lcd_mcspi_config = { | 58 | static struct omap2_mcspi_device_config dss_lcd_mcspi_config = { |
| 127 | .turbo_mode = 1, | 59 | .turbo_mode = 1, |
| 128 | }; | 60 | }; |
diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c index cdc0c1021863..a90375d5b2b6 100644 --- a/arch/arm/mach-omap2/board-zoom-peripherals.c +++ b/arch/arm/mach-omap2/board-zoom-peripherals.c | |||
| @@ -22,6 +22,9 @@ | |||
| 22 | #include <linux/platform_data/gpio-omap.h> | 22 | #include <linux/platform_data/gpio-omap.h> |
| 23 | #include <linux/platform_data/omap-twl4030.h> | 23 | #include <linux/platform_data/omap-twl4030.h> |
| 24 | #include <linux/usb/phy.h> | 24 | #include <linux/usb/phy.h> |
| 25 | #include <linux/pwm.h> | ||
| 26 | #include <linux/leds_pwm.h> | ||
| 27 | #include <linux/pwm_backlight.h> | ||
| 25 | 28 | ||
| 26 | #include <asm/mach-types.h> | 29 | #include <asm/mach-types.h> |
| 27 | #include <asm/mach/arch.h> | 30 | #include <asm/mach/arch.h> |
| @@ -193,6 +196,53 @@ static struct platform_device omap_vwlan_device = { | |||
| 193 | }, | 196 | }, |
| 194 | }; | 197 | }; |
| 195 | 198 | ||
| 199 | static struct pwm_lookup zoom_pwm_lookup[] = { | ||
| 200 | PWM_LOOKUP("twl-pwm", 0, "leds_pwm", "zoom::keypad"), | ||
| 201 | PWM_LOOKUP("twl-pwm", 1, "pwm-backlight", "backlight"), | ||
| 202 | }; | ||
| 203 | |||
| 204 | static struct led_pwm zoom_pwm_leds[] = { | ||
| 205 | { | ||
| 206 | .name = "zoom::keypad", | ||
| 207 | .max_brightness = 127, | ||
| 208 | .pwm_period_ns = 7812500, | ||
| 209 | }, | ||
| 210 | }; | ||
| 211 | |||
| 212 | static struct led_pwm_platform_data zoom_pwm_data = { | ||
| 213 | .num_leds = ARRAY_SIZE(zoom_pwm_leds), | ||
| 214 | .leds = zoom_pwm_leds, | ||
| 215 | }; | ||
| 216 | |||
| 217 | static struct platform_device zoom_leds_pwm = { | ||
| 218 | .name = "leds_pwm", | ||
| 219 | .id = -1, | ||
| 220 | .dev = { | ||
| 221 | .platform_data = &zoom_pwm_data, | ||
| 222 | }, | ||
| 223 | }; | ||
| 224 | |||
| 225 | static struct platform_pwm_backlight_data zoom_backlight_data = { | ||
| 226 | .pwm_id = 1, | ||
| 227 | .max_brightness = 127, | ||
| 228 | .dft_brightness = 127, | ||
| 229 | .pwm_period_ns = 7812500, | ||
| 230 | }; | ||
| 231 | |||
| 232 | static struct platform_device zoom_backlight_pwm = { | ||
| 233 | .name = "pwm-backlight", | ||
| 234 | .id = -1, | ||
| 235 | .dev = { | ||
| 236 | .platform_data = &zoom_backlight_data, | ||
| 237 | }, | ||
| 238 | }; | ||
| 239 | |||
| 240 | static struct platform_device *zoom_devices[] __initdata = { | ||
| 241 | &omap_vwlan_device, | ||
| 242 | &zoom_leds_pwm, | ||
| 243 | &zoom_backlight_pwm, | ||
| 244 | }; | ||
| 245 | |||
| 196 | static struct wl12xx_platform_data omap_zoom_wlan_data __initdata = { | 246 | static struct wl12xx_platform_data omap_zoom_wlan_data __initdata = { |
| 197 | .board_ref_clock = WL12XX_REFCLOCK_26, /* 26 MHz */ | 247 | .board_ref_clock = WL12XX_REFCLOCK_26, /* 26 MHz */ |
| 198 | }; | 248 | }; |
| @@ -301,7 +351,8 @@ void __init zoom_peripherals_init(void) | |||
| 301 | 351 | ||
| 302 | omap_hsmmc_init(mmc); | 352 | omap_hsmmc_init(mmc); |
| 303 | omap_i2c_init(); | 353 | omap_i2c_init(); |
| 304 | platform_device_register(&omap_vwlan_device); | 354 | pwm_add_table(zoom_pwm_lookup, ARRAY_SIZE(zoom_pwm_lookup)); |
| 355 | platform_add_devices(zoom_devices, ARRAY_SIZE(zoom_devices)); | ||
| 305 | usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb"); | 356 | usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb"); |
| 306 | usb_musb_init(NULL); | 357 | usb_musb_init(NULL); |
| 307 | enable_board_wakeup_source(); | 358 | enable_board_wakeup_source(); |
diff --git a/arch/arm/mach-omap2/cclock44xx_data.c b/arch/arm/mach-omap2/cclock44xx_data.c index 3d58f335f173..0c6834ae1fc4 100644 --- a/arch/arm/mach-omap2/cclock44xx_data.c +++ b/arch/arm/mach-omap2/cclock44xx_data.c | |||
| @@ -52,6 +52,13 @@ | |||
| 52 | */ | 52 | */ |
| 53 | #define OMAP4_DPLL_ABE_DEFFREQ 98304000 | 53 | #define OMAP4_DPLL_ABE_DEFFREQ 98304000 |
| 54 | 54 | ||
| 55 | /* | ||
| 56 | * OMAP4 USB DPLL default frequency. In OMAP4430 TRM version V, section | ||
| 57 | * "3.6.3.9.5 DPLL_USB Preferred Settings" shows that the preferred | ||
| 58 | * locked frequency for the USB DPLL is 960MHz. | ||
| 59 | */ | ||
| 60 | #define OMAP4_DPLL_USB_DEFFREQ 960000000 | ||
| 61 | |||
| 55 | /* Root clocks */ | 62 | /* Root clocks */ |
| 56 | 63 | ||
| 57 | DEFINE_CLK_FIXED_RATE(extalt_clkin_ck, CLK_IS_ROOT, 59000000, 0x0); | 64 | DEFINE_CLK_FIXED_RATE(extalt_clkin_ck, CLK_IS_ROOT, 59000000, 0x0); |
| @@ -1011,6 +1018,10 @@ DEFINE_CLK_OMAP_MUX(hsmmc2_fclk, "l3_init_clkdm", hsmmc1_fclk_sel, | |||
| 1011 | OMAP4430_CM_L3INIT_MMC2_CLKCTRL, OMAP4430_CLKSEL_MASK, | 1018 | OMAP4430_CM_L3INIT_MMC2_CLKCTRL, OMAP4430_CLKSEL_MASK, |
| 1012 | hsmmc1_fclk_parents, func_dmic_abe_gfclk_ops); | 1019 | hsmmc1_fclk_parents, func_dmic_abe_gfclk_ops); |
| 1013 | 1020 | ||
| 1021 | DEFINE_CLK_GATE(ocp2scp_usb_phy_phy_48m, "func_48m_fclk", &func_48m_fclk, 0x0, | ||
| 1022 | OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, | ||
| 1023 | OMAP4430_OPTFCLKEN_PHY_48M_SHIFT, 0x0, NULL); | ||
| 1024 | |||
| 1014 | DEFINE_CLK_GATE(sha2md5_fck, "l3_div_ck", &l3_div_ck, 0x0, | 1025 | DEFINE_CLK_GATE(sha2md5_fck, "l3_div_ck", &l3_div_ck, 0x0, |
| 1015 | OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL, | 1026 | OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL, |
| 1016 | OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); | 1027 | OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); |
| @@ -1538,6 +1549,7 @@ static struct omap_clk omap44xx_clks[] = { | |||
| 1538 | CLK(NULL, "per_mcbsp4_gfclk", &per_mcbsp4_gfclk, CK_443X), | 1549 | CLK(NULL, "per_mcbsp4_gfclk", &per_mcbsp4_gfclk, CK_443X), |
| 1539 | CLK(NULL, "hsmmc1_fclk", &hsmmc1_fclk, CK_443X), | 1550 | CLK(NULL, "hsmmc1_fclk", &hsmmc1_fclk, CK_443X), |
| 1540 | CLK(NULL, "hsmmc2_fclk", &hsmmc2_fclk, CK_443X), | 1551 | CLK(NULL, "hsmmc2_fclk", &hsmmc2_fclk, CK_443X), |
| 1552 | CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m, CK_443X), | ||
| 1541 | CLK(NULL, "sha2md5_fck", &sha2md5_fck, CK_443X), | 1553 | CLK(NULL, "sha2md5_fck", &sha2md5_fck, CK_443X), |
| 1542 | CLK(NULL, "slimbus1_fclk_1", &slimbus1_fclk_1, CK_443X), | 1554 | CLK(NULL, "slimbus1_fclk_1", &slimbus1_fclk_1, CK_443X), |
| 1543 | CLK(NULL, "slimbus1_fclk_0", &slimbus1_fclk_0, CK_443X), | 1555 | CLK(NULL, "slimbus1_fclk_0", &slimbus1_fclk_0, CK_443X), |
| @@ -1705,5 +1717,13 @@ int __init omap4xxx_clk_init(void) | |||
| 1705 | if (rc) | 1717 | if (rc) |
| 1706 | pr_err("%s: failed to configure ABE DPLL!\n", __func__); | 1718 | pr_err("%s: failed to configure ABE DPLL!\n", __func__); |
| 1707 | 1719 | ||
| 1720 | /* | ||
| 1721 | * Lock USB DPLL on OMAP4 devices so that the L3INIT power | ||
| 1722 | * domain can transition to retention state when not in use. | ||
| 1723 | */ | ||
| 1724 | rc = clk_set_rate(&dpll_usb_ck, OMAP4_DPLL_USB_DEFFREQ); | ||
| 1725 | if (rc) | ||
| 1726 | pr_err("%s: failed to configure USB DPLL!\n", __func__); | ||
| 1727 | |||
| 1708 | return 0; | 1728 | return 0; |
| 1709 | } | 1729 | } |
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h index bf70e2b57ff8..272490e72ee0 100644 --- a/arch/arm/mach-omap2/common.h +++ b/arch/arm/mach-omap2/common.h | |||
| @@ -292,5 +292,8 @@ extern void omap_reserve(void); | |||
| 292 | struct omap_hwmod; | 292 | struct omap_hwmod; |
| 293 | extern int omap_dss_reset(struct omap_hwmod *); | 293 | extern int omap_dss_reset(struct omap_hwmod *); |
| 294 | 294 | ||
| 295 | /* SoC specific clock initializer */ | ||
| 296 | extern int (*omap_clk_init)(void); | ||
| 297 | |||
| 295 | #endif /* __ASSEMBLER__ */ | 298 | #endif /* __ASSEMBLER__ */ |
| 296 | #endif /* __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H */ | 299 | #endif /* __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H */ |
diff --git a/arch/arm/mach-omap2/dss-common.c b/arch/arm/mach-omap2/dss-common.c index 4be5cfc81ab8..393aeefaebb0 100644 --- a/arch/arm/mach-omap2/dss-common.c +++ b/arch/arm/mach-omap2/dss-common.c | |||
| @@ -27,9 +27,7 @@ | |||
| 27 | #include <linux/gpio.h> | 27 | #include <linux/gpio.h> |
| 28 | 28 | ||
| 29 | #include <video/omapdss.h> | 29 | #include <video/omapdss.h> |
| 30 | #include <video/omap-panel-tfp410.h> | 30 | #include <video/omap-panel-data.h> |
| 31 | #include <video/omap-panel-nokia-dsi.h> | ||
| 32 | #include <video/omap-panel-picodlp.h> | ||
| 33 | 31 | ||
| 34 | #include "soc.h" | 32 | #include "soc.h" |
| 35 | #include "dss-common.h" | 33 | #include "dss-common.h" |
| @@ -54,7 +52,6 @@ static struct omap_dss_device omap4_panda_dvi_device = { | |||
| 54 | .driver_name = "tfp410", | 52 | .driver_name = "tfp410", |
| 55 | .data = &omap4_dvi_panel, | 53 | .data = &omap4_dvi_panel, |
| 56 | .phy.dpi.data_lines = 24, | 54 | .phy.dpi.data_lines = 24, |
| 57 | .reset_gpio = PANDA_DVI_TFP410_POWER_DOWN_GPIO, | ||
| 58 | .channel = OMAP_DSS_CHANNEL_LCD2, | 55 | .channel = OMAP_DSS_CHANNEL_LCD2, |
| 59 | }; | 56 | }; |
| 60 | 57 | ||
| @@ -179,45 +176,12 @@ static struct picodlp_panel_data sdp4430_picodlp_pdata = { | |||
| 179 | .pwrgood_gpio = 45, | 176 | .pwrgood_gpio = 45, |
| 180 | }; | 177 | }; |
| 181 | 178 | ||
| 182 | static void sdp4430_picodlp_init(void) | ||
| 183 | { | ||
| 184 | int r; | ||
| 185 | const struct gpio picodlp_gpios[] = { | ||
| 186 | {DLP_POWER_ON_GPIO, GPIOF_OUT_INIT_LOW, | ||
| 187 | "DLP POWER ON"}, | ||
| 188 | {sdp4430_picodlp_pdata.emu_done_gpio, GPIOF_IN, | ||
| 189 | "DLP EMU DONE"}, | ||
| 190 | {sdp4430_picodlp_pdata.pwrgood_gpio, GPIOF_OUT_INIT_LOW, | ||
| 191 | "DLP PWRGOOD"}, | ||
| 192 | }; | ||
| 193 | |||
| 194 | r = gpio_request_array(picodlp_gpios, ARRAY_SIZE(picodlp_gpios)); | ||
| 195 | if (r) | ||
| 196 | pr_err("Cannot request PicoDLP GPIOs, error %d\n", r); | ||
| 197 | } | ||
| 198 | |||
| 199 | static int sdp4430_panel_enable_picodlp(struct omap_dss_device *dssdev) | ||
| 200 | { | ||
| 201 | gpio_set_value(DISPLAY_SEL_GPIO, 0); | ||
| 202 | gpio_set_value(DLP_POWER_ON_GPIO, 1); | ||
| 203 | |||
| 204 | return 0; | ||
| 205 | } | ||
| 206 | |||
| 207 | static void sdp4430_panel_disable_picodlp(struct omap_dss_device *dssdev) | ||
| 208 | { | ||
| 209 | gpio_set_value(DLP_POWER_ON_GPIO, 0); | ||
| 210 | gpio_set_value(DISPLAY_SEL_GPIO, 1); | ||
| 211 | } | ||
| 212 | |||
| 213 | static struct omap_dss_device sdp4430_picodlp_device = { | 179 | static struct omap_dss_device sdp4430_picodlp_device = { |
| 214 | .name = "picodlp", | 180 | .name = "picodlp", |
| 215 | .driver_name = "picodlp_panel", | 181 | .driver_name = "picodlp_panel", |
| 216 | .type = OMAP_DISPLAY_TYPE_DPI, | 182 | .type = OMAP_DISPLAY_TYPE_DPI, |
| 217 | .phy.dpi.data_lines = 24, | 183 | .phy.dpi.data_lines = 24, |
| 218 | .channel = OMAP_DSS_CHANNEL_LCD2, | 184 | .channel = OMAP_DSS_CHANNEL_LCD2, |
| 219 | .platform_enable = sdp4430_panel_enable_picodlp, | ||
| 220 | .platform_disable = sdp4430_panel_disable_picodlp, | ||
| 221 | .data = &sdp4430_picodlp_pdata, | 185 | .data = &sdp4430_picodlp_pdata, |
| 222 | }; | 186 | }; |
| 223 | 187 | ||
| @@ -234,17 +198,26 @@ static struct omap_dss_board_info sdp4430_dss_data = { | |||
| 234 | .default_device = &sdp4430_lcd_device, | 198 | .default_device = &sdp4430_lcd_device, |
| 235 | }; | 199 | }; |
| 236 | 200 | ||
| 201 | /* | ||
| 202 | * we select LCD2 by default (instead of Pico DLP) by setting DISPLAY_SEL_GPIO. | ||
| 203 | * Setting DLP_POWER_ON gpio enables the VDLP_2V5 VDLP_1V8 and VDLP_1V0 rails | ||
| 204 | * used by picodlp on the 4430sdp platform. Keep this gpio disabled as LCD2 is | ||
| 205 | * selected by default | ||
| 206 | */ | ||
| 237 | void __init omap_4430sdp_display_init(void) | 207 | void __init omap_4430sdp_display_init(void) |
| 238 | { | 208 | { |
| 239 | int r; | 209 | int r; |
| 240 | 210 | ||
| 241 | /* Enable LCD2 by default (instead of Pico DLP) */ | ||
| 242 | r = gpio_request_one(DISPLAY_SEL_GPIO, GPIOF_OUT_INIT_HIGH, | 211 | r = gpio_request_one(DISPLAY_SEL_GPIO, GPIOF_OUT_INIT_HIGH, |
| 243 | "display_sel"); | 212 | "display_sel"); |
| 244 | if (r) | 213 | if (r) |
| 245 | pr_err("%s: Could not get display_sel GPIO\n", __func__); | 214 | pr_err("%s: Could not get display_sel GPIO\n", __func__); |
| 246 | 215 | ||
| 247 | sdp4430_picodlp_init(); | 216 | r = gpio_request_one(DLP_POWER_ON_GPIO, GPIOF_OUT_INIT_LOW, |
| 217 | "DLP POWER ON"); | ||
| 218 | if (r) | ||
| 219 | pr_err("%s: Could not get DLP POWER ON GPIO\n", __func__); | ||
| 220 | |||
| 248 | omap_display_init(&sdp4430_dss_data); | 221 | omap_display_init(&sdp4430_dss_data); |
| 249 | /* | 222 | /* |
| 250 | * OMAP4460SDP/Blaze and OMAP4430 ES2.3 SDP/Blaze boards and | 223 | * OMAP4460SDP/Blaze and OMAP4430 ES2.3 SDP/Blaze boards and |
| @@ -264,12 +237,15 @@ void __init omap_4430sdp_display_init_of(void) | |||
| 264 | { | 237 | { |
| 265 | int r; | 238 | int r; |
| 266 | 239 | ||
| 267 | /* Enable LCD2 by default (instead of Pico DLP) */ | ||
| 268 | r = gpio_request_one(DISPLAY_SEL_GPIO, GPIOF_OUT_INIT_HIGH, | 240 | r = gpio_request_one(DISPLAY_SEL_GPIO, GPIOF_OUT_INIT_HIGH, |
| 269 | "display_sel"); | 241 | "display_sel"); |
| 270 | if (r) | 242 | if (r) |
| 271 | pr_err("%s: Could not get display_sel GPIO\n", __func__); | 243 | pr_err("%s: Could not get display_sel GPIO\n", __func__); |
| 272 | 244 | ||
| 273 | sdp4430_picodlp_init(); | 245 | r = gpio_request_one(DLP_POWER_ON_GPIO, GPIOF_OUT_INIT_LOW, |
| 246 | "DLP POWER ON"); | ||
| 247 | if (r) | ||
| 248 | pr_err("%s: Could not get DLP POWER ON GPIO\n", __func__); | ||
| 249 | |||
| 274 | omap_display_init(&sdp4430_dss_data); | 250 | omap_display_init(&sdp4430_dss_data); |
| 275 | } | 251 | } |
diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c index afc1e8c32d6c..d9c27195caf0 100644 --- a/arch/arm/mach-omap2/gpmc-nand.c +++ b/arch/arm/mach-omap2/gpmc-nand.c | |||
| @@ -74,14 +74,6 @@ static int omap2_nand_gpmc_retime( | |||
| 74 | t.cs_wr_off = gpmc_t->cs_wr_off; | 74 | t.cs_wr_off = gpmc_t->cs_wr_off; |
| 75 | t.wr_cycle = gpmc_t->wr_cycle; | 75 | t.wr_cycle = gpmc_t->wr_cycle; |
| 76 | 76 | ||
| 77 | /* Configure GPMC */ | ||
| 78 | if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16) | ||
| 79 | gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_DEV_SIZE, 1); | ||
| 80 | else | ||
| 81 | gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_DEV_SIZE, 0); | ||
| 82 | gpmc_cs_configure(gpmc_nand_data->cs, | ||
| 83 | GPMC_CONFIG_DEV_TYPE, GPMC_DEVICETYPE_NAND); | ||
| 84 | gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_WP, 0); | ||
| 85 | err = gpmc_cs_set_timings(gpmc_nand_data->cs, &t); | 77 | err = gpmc_cs_set_timings(gpmc_nand_data->cs, &t); |
| 86 | if (err) | 78 | if (err) |
| 87 | return err; | 79 | return err; |
| @@ -115,14 +107,18 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data, | |||
| 115 | struct gpmc_timings *gpmc_t) | 107 | struct gpmc_timings *gpmc_t) |
| 116 | { | 108 | { |
| 117 | int err = 0; | 109 | int err = 0; |
| 110 | struct gpmc_settings s; | ||
| 118 | struct device *dev = &gpmc_nand_device.dev; | 111 | struct device *dev = &gpmc_nand_device.dev; |
| 119 | 112 | ||
| 113 | memset(&s, 0, sizeof(struct gpmc_settings)); | ||
| 114 | |||
| 120 | gpmc_nand_device.dev.platform_data = gpmc_nand_data; | 115 | gpmc_nand_device.dev.platform_data = gpmc_nand_data; |
| 121 | 116 | ||
| 122 | err = gpmc_cs_request(gpmc_nand_data->cs, NAND_IO_SIZE, | 117 | err = gpmc_cs_request(gpmc_nand_data->cs, NAND_IO_SIZE, |
| 123 | (unsigned long *)&gpmc_nand_resource[0].start); | 118 | (unsigned long *)&gpmc_nand_resource[0].start); |
| 124 | if (err < 0) { | 119 | if (err < 0) { |
| 125 | dev_err(dev, "Cannot request GPMC CS\n"); | 120 | dev_err(dev, "Cannot request GPMC CS %d, error %d\n", |
| 121 | gpmc_nand_data->cs, err); | ||
| 126 | return err; | 122 | return err; |
| 127 | } | 123 | } |
| 128 | 124 | ||
| @@ -140,11 +136,31 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data, | |||
| 140 | dev_err(dev, "Unable to set gpmc timings: %d\n", err); | 136 | dev_err(dev, "Unable to set gpmc timings: %d\n", err); |
| 141 | return err; | 137 | return err; |
| 142 | } | 138 | } |
| 143 | } | ||
| 144 | 139 | ||
| 145 | /* Enable RD PIN Monitoring Reg */ | 140 | if (gpmc_nand_data->of_node) { |
| 146 | if (gpmc_nand_data->dev_ready) { | 141 | gpmc_read_settings_dt(gpmc_nand_data->of_node, &s); |
| 147 | gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_RDY_BSY, 1); | 142 | } else { |
| 143 | s.device_nand = true; | ||
| 144 | |||
| 145 | /* Enable RD PIN Monitoring Reg */ | ||
| 146 | if (gpmc_nand_data->dev_ready) { | ||
| 147 | s.wait_on_read = true; | ||
| 148 | s.wait_on_write = true; | ||
| 149 | } | ||
| 150 | } | ||
| 151 | |||
| 152 | if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16) | ||
| 153 | s.device_width = GPMC_DEVWIDTH_16BIT; | ||
| 154 | else | ||
| 155 | s.device_width = GPMC_DEVWIDTH_8BIT; | ||
| 156 | |||
| 157 | err = gpmc_cs_program_settings(gpmc_nand_data->cs, &s); | ||
| 158 | if (err < 0) | ||
| 159 | goto out_free_cs; | ||
| 160 | |||
| 161 | err = gpmc_configure(GPMC_CONFIG_WP, 0); | ||
| 162 | if (err < 0) | ||
| 163 | goto out_free_cs; | ||
| 148 | } | 164 | } |
| 149 | 165 | ||
| 150 | gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs); | 166 | gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs); |
diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c index 0d75889c0a6f..64b5a8346982 100644 --- a/arch/arm/mach-omap2/gpmc-onenand.c +++ b/arch/arm/mach-omap2/gpmc-onenand.c | |||
| @@ -47,11 +47,23 @@ static struct platform_device gpmc_onenand_device = { | |||
| 47 | .resource = &gpmc_onenand_resource, | 47 | .resource = &gpmc_onenand_resource, |
| 48 | }; | 48 | }; |
| 49 | 49 | ||
| 50 | static struct gpmc_timings omap2_onenand_calc_async_timings(void) | 50 | static struct gpmc_settings onenand_async = { |
| 51 | .device_width = GPMC_DEVWIDTH_16BIT, | ||
| 52 | .mux_add_data = GPMC_MUX_AD, | ||
| 53 | }; | ||
| 54 | |||
| 55 | static struct gpmc_settings onenand_sync = { | ||
| 56 | .burst_read = true, | ||
| 57 | .burst_wrap = true, | ||
| 58 | .burst_len = GPMC_BURST_16, | ||
| 59 | .device_width = GPMC_DEVWIDTH_16BIT, | ||
| 60 | .mux_add_data = GPMC_MUX_AD, | ||
| 61 | .wait_pin = 0, | ||
| 62 | }; | ||
| 63 | |||
| 64 | static void omap2_onenand_calc_async_timings(struct gpmc_timings *t) | ||
| 51 | { | 65 | { |
| 52 | struct gpmc_device_timings dev_t; | 66 | struct gpmc_device_timings dev_t; |
| 53 | struct gpmc_timings t; | ||
| 54 | |||
| 55 | const int t_cer = 15; | 67 | const int t_cer = 15; |
| 56 | const int t_avdp = 12; | 68 | const int t_avdp = 12; |
| 57 | const int t_aavdh = 7; | 69 | const int t_aavdh = 7; |
| @@ -64,7 +76,6 @@ static struct gpmc_timings omap2_onenand_calc_async_timings(void) | |||
| 64 | 76 | ||
| 65 | memset(&dev_t, 0, sizeof(dev_t)); | 77 | memset(&dev_t, 0, sizeof(dev_t)); |
| 66 | 78 | ||
| 67 | dev_t.mux = true; | ||
| 68 | dev_t.t_avdp_r = max_t(int, t_avdp, t_cer) * 1000; | 79 | dev_t.t_avdp_r = max_t(int, t_avdp, t_cer) * 1000; |
| 69 | dev_t.t_avdp_w = dev_t.t_avdp_r; | 80 | dev_t.t_avdp_w = dev_t.t_avdp_r; |
| 70 | dev_t.t_aavdh = t_aavdh * 1000; | 81 | dev_t.t_aavdh = t_aavdh * 1000; |
| @@ -76,19 +87,7 @@ static struct gpmc_timings omap2_onenand_calc_async_timings(void) | |||
| 76 | dev_t.t_wpl = t_wpl * 1000; | 87 | dev_t.t_wpl = t_wpl * 1000; |
| 77 | dev_t.t_wph = t_wph * 1000; | 88 | dev_t.t_wph = t_wph * 1000; |
| 78 | 89 | ||
| 79 | gpmc_calc_timings(&t, &dev_t); | 90 | gpmc_calc_timings(t, &onenand_async, &dev_t); |
| 80 | |||
| 81 | return t; | ||
| 82 | } | ||
| 83 | |||
| 84 | static int gpmc_set_async_mode(int cs, struct gpmc_timings *t) | ||
| 85 | { | ||
| 86 | /* Configure GPMC for asynchronous read */ | ||
| 87 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, | ||
| 88 | GPMC_CONFIG1_DEVICESIZE_16 | | ||
| 89 | GPMC_CONFIG1_MUXADDDATA); | ||
| 90 | |||
| 91 | return gpmc_cs_set_timings(cs, t); | ||
| 92 | } | 91 | } |
| 93 | 92 | ||
| 94 | static void omap2_onenand_set_async_mode(void __iomem *onenand_base) | 93 | static void omap2_onenand_set_async_mode(void __iomem *onenand_base) |
| @@ -158,12 +157,11 @@ static int omap2_onenand_get_freq(struct omap_onenand_platform_data *cfg, | |||
| 158 | return freq; | 157 | return freq; |
| 159 | } | 158 | } |
| 160 | 159 | ||
| 161 | static struct gpmc_timings | 160 | static void omap2_onenand_calc_sync_timings(struct gpmc_timings *t, |
| 162 | omap2_onenand_calc_sync_timings(struct omap_onenand_platform_data *cfg, | 161 | unsigned int flags, |
| 163 | int freq) | 162 | int freq) |
| 164 | { | 163 | { |
| 165 | struct gpmc_device_timings dev_t; | 164 | struct gpmc_device_timings dev_t; |
| 166 | struct gpmc_timings t; | ||
| 167 | const int t_cer = 15; | 165 | const int t_cer = 15; |
| 168 | const int t_avdp = 12; | 166 | const int t_avdp = 12; |
| 169 | const int t_cez = 20; /* max of t_cez, t_oez */ | 167 | const int t_cez = 20; /* max of t_cez, t_oez */ |
| @@ -172,9 +170,9 @@ omap2_onenand_calc_sync_timings(struct omap_onenand_platform_data *cfg, | |||
| 172 | int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo; | 170 | int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo; |
| 173 | int div, gpmc_clk_ns; | 171 | int div, gpmc_clk_ns; |
| 174 | 172 | ||
| 175 | if (cfg->flags & ONENAND_SYNC_READ) | 173 | if (flags & ONENAND_SYNC_READ) |
| 176 | onenand_flags = ONENAND_FLAG_SYNCREAD; | 174 | onenand_flags = ONENAND_FLAG_SYNCREAD; |
| 177 | else if (cfg->flags & ONENAND_SYNC_READWRITE) | 175 | else if (flags & ONENAND_SYNC_READWRITE) |
| 178 | onenand_flags = ONENAND_FLAG_SYNCREAD | ONENAND_FLAG_SYNCWRITE; | 176 | onenand_flags = ONENAND_FLAG_SYNCREAD | ONENAND_FLAG_SYNCWRITE; |
| 179 | 177 | ||
| 180 | switch (freq) { | 178 | switch (freq) { |
| @@ -239,10 +237,11 @@ omap2_onenand_calc_sync_timings(struct omap_onenand_platform_data *cfg, | |||
| 239 | /* Set synchronous read timings */ | 237 | /* Set synchronous read timings */ |
| 240 | memset(&dev_t, 0, sizeof(dev_t)); | 238 | memset(&dev_t, 0, sizeof(dev_t)); |
| 241 | 239 | ||
| 242 | dev_t.mux = true; | 240 | if (onenand_flags & ONENAND_FLAG_SYNCREAD) |
| 243 | dev_t.sync_read = true; | 241 | onenand_sync.sync_read = true; |
| 244 | if (onenand_flags & ONENAND_FLAG_SYNCWRITE) { | 242 | if (onenand_flags & ONENAND_FLAG_SYNCWRITE) { |
| 245 | dev_t.sync_write = true; | 243 | onenand_sync.sync_write = true; |
| 244 | onenand_sync.burst_write = true; | ||
| 246 | } else { | 245 | } else { |
| 247 | dev_t.t_avdp_w = max(t_avdp, t_cer) * 1000; | 246 | dev_t.t_avdp_w = max(t_avdp, t_cer) * 1000; |
| 248 | dev_t.t_wpl = t_wpl * 1000; | 247 | dev_t.t_wpl = t_wpl * 1000; |
| @@ -265,32 +264,7 @@ omap2_onenand_calc_sync_timings(struct omap_onenand_platform_data *cfg, | |||
| 265 | dev_t.cyc_aavdh_oe = 1; | 264 | dev_t.cyc_aavdh_oe = 1; |
| 266 | dev_t.t_rdyo = t_rdyo * 1000 + min_gpmc_clk_period; | 265 | dev_t.t_rdyo = t_rdyo * 1000 + min_gpmc_clk_period; |
| 267 | 266 | ||
| 268 | gpmc_calc_timings(&t, &dev_t); | 267 | gpmc_calc_timings(t, &onenand_sync, &dev_t); |
| 269 | |||
| 270 | return t; | ||
| 271 | } | ||
| 272 | |||
| 273 | static int gpmc_set_sync_mode(int cs, struct gpmc_timings *t) | ||
| 274 | { | ||
| 275 | unsigned sync_read = onenand_flags & ONENAND_FLAG_SYNCREAD; | ||
| 276 | unsigned sync_write = onenand_flags & ONENAND_FLAG_SYNCWRITE; | ||
| 277 | |||
| 278 | /* Configure GPMC for synchronous read */ | ||
| 279 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, | ||
| 280 | GPMC_CONFIG1_WRAPBURST_SUPP | | ||
| 281 | GPMC_CONFIG1_READMULTIPLE_SUPP | | ||
| 282 | (sync_read ? GPMC_CONFIG1_READTYPE_SYNC : 0) | | ||
| 283 | (sync_write ? GPMC_CONFIG1_WRITEMULTIPLE_SUPP : 0) | | ||
| 284 | (sync_write ? GPMC_CONFIG1_WRITETYPE_SYNC : 0) | | ||
| 285 | GPMC_CONFIG1_PAGE_LEN(2) | | ||
| 286 | (cpu_is_omap34xx() ? 0 : | ||
| 287 | (GPMC_CONFIG1_WAIT_READ_MON | | ||
| 288 | GPMC_CONFIG1_WAIT_PIN_SEL(0))) | | ||
| 289 | GPMC_CONFIG1_DEVICESIZE_16 | | ||
| 290 | GPMC_CONFIG1_DEVICETYPE_NOR | | ||
| 291 | GPMC_CONFIG1_MUXADDDATA); | ||
| 292 | |||
| 293 | return gpmc_cs_set_timings(cs, t); | ||
| 294 | } | 268 | } |
| 295 | 269 | ||
| 296 | static int omap2_onenand_setup_async(void __iomem *onenand_base) | 270 | static int omap2_onenand_setup_async(void __iomem *onenand_base) |
| @@ -298,11 +272,19 @@ static int omap2_onenand_setup_async(void __iomem *onenand_base) | |||
| 298 | struct gpmc_timings t; | 272 | struct gpmc_timings t; |
| 299 | int ret; | 273 | int ret; |
| 300 | 274 | ||
| 275 | if (gpmc_onenand_data->of_node) | ||
| 276 | gpmc_read_settings_dt(gpmc_onenand_data->of_node, | ||
| 277 | &onenand_async); | ||
| 278 | |||
| 301 | omap2_onenand_set_async_mode(onenand_base); | 279 | omap2_onenand_set_async_mode(onenand_base); |
| 302 | 280 | ||
| 303 | t = omap2_onenand_calc_async_timings(); | 281 | omap2_onenand_calc_async_timings(&t); |
| 282 | |||
| 283 | ret = gpmc_cs_program_settings(gpmc_onenand_data->cs, &onenand_async); | ||
| 284 | if (ret < 0) | ||
| 285 | return ret; | ||
| 304 | 286 | ||
| 305 | ret = gpmc_set_async_mode(gpmc_onenand_data->cs, &t); | 287 | ret = gpmc_cs_set_timings(gpmc_onenand_data->cs, &t); |
| 306 | if (ret < 0) | 288 | if (ret < 0) |
| 307 | return ret; | 289 | return ret; |
| 308 | 290 | ||
| @@ -322,9 +304,25 @@ static int omap2_onenand_setup_sync(void __iomem *onenand_base, int *freq_ptr) | |||
| 322 | set_onenand_cfg(onenand_base); | 304 | set_onenand_cfg(onenand_base); |
| 323 | } | 305 | } |
| 324 | 306 | ||
| 325 | t = omap2_onenand_calc_sync_timings(gpmc_onenand_data, freq); | 307 | if (gpmc_onenand_data->of_node) { |
| 308 | gpmc_read_settings_dt(gpmc_onenand_data->of_node, | ||
| 309 | &onenand_sync); | ||
| 310 | } else { | ||
| 311 | /* | ||
| 312 | * FIXME: Appears to be legacy code from initial ONENAND commit. | ||
| 313 | * Unclear what boards this is for and if this can be removed. | ||
| 314 | */ | ||
| 315 | if (!cpu_is_omap34xx()) | ||
| 316 | onenand_sync.wait_on_read = true; | ||
| 317 | } | ||
| 326 | 318 | ||
| 327 | ret = gpmc_set_sync_mode(gpmc_onenand_data->cs, &t); | 319 | omap2_onenand_calc_sync_timings(&t, gpmc_onenand_data->flags, freq); |
| 320 | |||
| 321 | ret = gpmc_cs_program_settings(gpmc_onenand_data->cs, &onenand_sync); | ||
| 322 | if (ret < 0) | ||
| 323 | return ret; | ||
| 324 | |||
| 325 | ret = gpmc_cs_set_timings(gpmc_onenand_data->cs, &t); | ||
| 328 | if (ret < 0) | 326 | if (ret < 0) |
| 329 | return ret; | 327 | return ret; |
| 330 | 328 | ||
| @@ -359,6 +357,7 @@ static int gpmc_onenand_setup(void __iomem *onenand_base, int *freq_ptr) | |||
| 359 | void gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data) | 357 | void gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data) |
| 360 | { | 358 | { |
| 361 | int err; | 359 | int err; |
| 360 | struct device *dev = &gpmc_onenand_device.dev; | ||
| 362 | 361 | ||
| 363 | gpmc_onenand_data = _onenand_data; | 362 | gpmc_onenand_data = _onenand_data; |
| 364 | gpmc_onenand_data->onenand_setup = gpmc_onenand_setup; | 363 | gpmc_onenand_data->onenand_setup = gpmc_onenand_setup; |
| @@ -366,7 +365,7 @@ void gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data) | |||
| 366 | 365 | ||
| 367 | if (cpu_is_omap24xx() && | 366 | if (cpu_is_omap24xx() && |
| 368 | (gpmc_onenand_data->flags & ONENAND_SYNC_READWRITE)) { | 367 | (gpmc_onenand_data->flags & ONENAND_SYNC_READWRITE)) { |
| 369 | printk(KERN_ERR "Onenand using only SYNC_READ on 24xx\n"); | 368 | dev_warn(dev, "OneNAND using only SYNC_READ on 24xx\n"); |
| 370 | gpmc_onenand_data->flags &= ~ONENAND_SYNC_READWRITE; | 369 | gpmc_onenand_data->flags &= ~ONENAND_SYNC_READWRITE; |
| 371 | gpmc_onenand_data->flags |= ONENAND_SYNC_READ; | 370 | gpmc_onenand_data->flags |= ONENAND_SYNC_READ; |
| 372 | } | 371 | } |
| @@ -379,7 +378,8 @@ void gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data) | |||
| 379 | err = gpmc_cs_request(gpmc_onenand_data->cs, ONENAND_IO_SIZE, | 378 | err = gpmc_cs_request(gpmc_onenand_data->cs, ONENAND_IO_SIZE, |
| 380 | (unsigned long *)&gpmc_onenand_resource.start); | 379 | (unsigned long *)&gpmc_onenand_resource.start); |
| 381 | if (err < 0) { | 380 | if (err < 0) { |
| 382 | pr_err("%s: Cannot request GPMC CS\n", __func__); | 381 | dev_err(dev, "Cannot request GPMC CS %d, error %d\n", |
| 382 | gpmc_onenand_data->cs, err); | ||
| 383 | return; | 383 | return; |
| 384 | } | 384 | } |
| 385 | 385 | ||
| @@ -387,7 +387,7 @@ void gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data) | |||
| 387 | ONENAND_IO_SIZE - 1; | 387 | ONENAND_IO_SIZE - 1; |
| 388 | 388 | ||
| 389 | if (platform_device_register(&gpmc_onenand_device) < 0) { | 389 | if (platform_device_register(&gpmc_onenand_device) < 0) { |
| 390 | pr_err("%s: Unable to register OneNAND device\n", __func__); | 390 | dev_err(dev, "Unable to register OneNAND device\n"); |
| 391 | gpmc_cs_free(gpmc_onenand_data->cs); | 391 | gpmc_cs_free(gpmc_onenand_data->cs); |
| 392 | return; | 392 | return; |
| 393 | } | 393 | } |
diff --git a/arch/arm/mach-omap2/gpmc-smc91x.c b/arch/arm/mach-omap2/gpmc-smc91x.c index 11d0b756f098..61a063595e66 100644 --- a/arch/arm/mach-omap2/gpmc-smc91x.c +++ b/arch/arm/mach-omap2/gpmc-smc91x.c | |||
| @@ -49,6 +49,10 @@ static struct platform_device gpmc_smc91x_device = { | |||
| 49 | .resource = gpmc_smc91x_resources, | 49 | .resource = gpmc_smc91x_resources, |
| 50 | }; | 50 | }; |
| 51 | 51 | ||
| 52 | static struct gpmc_settings smc91x_settings = { | ||
| 53 | .device_width = GPMC_DEVWIDTH_16BIT, | ||
| 54 | }; | ||
| 55 | |||
| 52 | /* | 56 | /* |
| 53 | * Set the gpmc timings for smc91c96. The timings are taken | 57 | * Set the gpmc timings for smc91c96. The timings are taken |
| 54 | * from the data sheet available at: | 58 | * from the data sheet available at: |
| @@ -67,18 +71,6 @@ static int smc91c96_gpmc_retime(void) | |||
| 67 | const int t7 = 5; /* Figure 12.4 write */ | 71 | const int t7 = 5; /* Figure 12.4 write */ |
| 68 | const int t8 = 5; /* Figure 12.4 write */ | 72 | const int t8 = 5; /* Figure 12.4 write */ |
| 69 | const int t20 = 185; /* Figure 12.2 read and 12.4 write */ | 73 | const int t20 = 185; /* Figure 12.2 read and 12.4 write */ |
| 70 | u32 l; | ||
| 71 | |||
| 72 | l = GPMC_CONFIG1_DEVICESIZE_16; | ||
| 73 | if (gpmc_cfg->flags & GPMC_MUX_ADD_DATA) | ||
| 74 | l |= GPMC_CONFIG1_MUXADDDATA; | ||
| 75 | if (gpmc_cfg->flags & GPMC_READ_MON) | ||
| 76 | l |= GPMC_CONFIG1_WAIT_READ_MON; | ||
| 77 | if (gpmc_cfg->flags & GPMC_WRITE_MON) | ||
| 78 | l |= GPMC_CONFIG1_WAIT_WRITE_MON; | ||
| 79 | if (gpmc_cfg->wait_pin) | ||
| 80 | l |= GPMC_CONFIG1_WAIT_PIN_SEL(gpmc_cfg->wait_pin); | ||
| 81 | gpmc_cs_write_reg(gpmc_cfg->cs, GPMC_CS_CONFIG1, l); | ||
| 82 | 74 | ||
| 83 | /* | 75 | /* |
| 84 | * FIXME: Calculate the address and data bus muxed timings. | 76 | * FIXME: Calculate the address and data bus muxed timings. |
| @@ -104,7 +96,7 @@ static int smc91c96_gpmc_retime(void) | |||
| 104 | dev_t.t_cez_w = t4_w * 1000; | 96 | dev_t.t_cez_w = t4_w * 1000; |
| 105 | dev_t.t_wr_cycle = (t20 - t3) * 1000; | 97 | dev_t.t_wr_cycle = (t20 - t3) * 1000; |
| 106 | 98 | ||
| 107 | gpmc_calc_timings(&t, &dev_t); | 99 | gpmc_calc_timings(&t, &smc91x_settings, &dev_t); |
| 108 | 100 | ||
| 109 | return gpmc_cs_set_timings(gpmc_cfg->cs, &t); | 101 | return gpmc_cs_set_timings(gpmc_cfg->cs, &t); |
| 110 | } | 102 | } |
| @@ -133,6 +125,18 @@ void __init gpmc_smc91x_init(struct omap_smc91x_platform_data *board_data) | |||
| 133 | gpmc_smc91x_resources[0].end = cs_mem_base + 0x30f; | 125 | gpmc_smc91x_resources[0].end = cs_mem_base + 0x30f; |
| 134 | gpmc_smc91x_resources[1].flags |= (gpmc_cfg->flags & IRQF_TRIGGER_MASK); | 126 | gpmc_smc91x_resources[1].flags |= (gpmc_cfg->flags & IRQF_TRIGGER_MASK); |
| 135 | 127 | ||
| 128 | if (gpmc_cfg->flags & GPMC_MUX_ADD_DATA) | ||
| 129 | smc91x_settings.mux_add_data = GPMC_MUX_AD; | ||
| 130 | if (gpmc_cfg->flags & GPMC_READ_MON) | ||
| 131 | smc91x_settings.wait_on_read = true; | ||
| 132 | if (gpmc_cfg->flags & GPMC_WRITE_MON) | ||
| 133 | smc91x_settings.wait_on_write = true; | ||
| 134 | if (gpmc_cfg->wait_pin) | ||
| 135 | smc91x_settings.wait_pin = gpmc_cfg->wait_pin; | ||
| 136 | ret = gpmc_cs_program_settings(gpmc_cfg->cs, &smc91x_settings); | ||
| 137 | if (ret < 0) | ||
| 138 | goto free1; | ||
| 139 | |||
| 136 | if (gpmc_cfg->retime) { | 140 | if (gpmc_cfg->retime) { |
| 137 | ret = gpmc_cfg->retime(); | 141 | ret = gpmc_cfg->retime(); |
| 138 | if (ret != 0) | 142 | if (ret != 0) |
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c index 6de31739b45c..ed946df5ad8a 100644 --- a/arch/arm/mach-omap2/gpmc.c +++ b/arch/arm/mach-omap2/gpmc.c | |||
| @@ -26,6 +26,7 @@ | |||
| 26 | #include <linux/interrupt.h> | 26 | #include <linux/interrupt.h> |
| 27 | #include <linux/platform_device.h> | 27 | #include <linux/platform_device.h> |
| 28 | #include <linux/of.h> | 28 | #include <linux/of.h> |
| 29 | #include <linux/of_address.h> | ||
| 29 | #include <linux/of_mtd.h> | 30 | #include <linux/of_mtd.h> |
| 30 | #include <linux/of_device.h> | 31 | #include <linux/of_device.h> |
| 31 | #include <linux/mtd/nand.h> | 32 | #include <linux/mtd/nand.h> |
| @@ -91,9 +92,7 @@ | |||
| 91 | #define GPMC_CS_SIZE 0x30 | 92 | #define GPMC_CS_SIZE 0x30 |
| 92 | #define GPMC_BCH_SIZE 0x10 | 93 | #define GPMC_BCH_SIZE 0x10 |
| 93 | 94 | ||
| 94 | #define GPMC_MEM_START 0x00000000 | ||
| 95 | #define GPMC_MEM_END 0x3FFFFFFF | 95 | #define GPMC_MEM_END 0x3FFFFFFF |
| 96 | #define BOOT_ROM_SPACE 0x100000 /* 1MB */ | ||
| 97 | 96 | ||
| 98 | #define GPMC_CHUNK_SHIFT 24 /* 16 MB */ | 97 | #define GPMC_CHUNK_SHIFT 24 /* 16 MB */ |
| 99 | #define GPMC_SECTION_SHIFT 28 /* 128 MB */ | 98 | #define GPMC_SECTION_SHIFT 28 /* 128 MB */ |
| @@ -107,6 +106,9 @@ | |||
| 107 | 106 | ||
| 108 | #define GPMC_HAS_WR_ACCESS 0x1 | 107 | #define GPMC_HAS_WR_ACCESS 0x1 |
| 109 | #define GPMC_HAS_WR_DATA_MUX_BUS 0x2 | 108 | #define GPMC_HAS_WR_DATA_MUX_BUS 0x2 |
| 109 | #define GPMC_HAS_MUX_AAD 0x4 | ||
| 110 | |||
| 111 | #define GPMC_NR_WAITPINS 4 | ||
| 110 | 112 | ||
| 111 | /* XXX: Only NAND irq has been considered,currently these are the only ones used | 113 | /* XXX: Only NAND irq has been considered,currently these are the only ones used |
| 112 | */ | 114 | */ |
| @@ -153,6 +155,7 @@ static struct resource gpmc_cs_mem[GPMC_CS_NUM]; | |||
| 153 | static DEFINE_SPINLOCK(gpmc_mem_lock); | 155 | static DEFINE_SPINLOCK(gpmc_mem_lock); |
| 154 | /* Define chip-selects as reserved by default until probe completes */ | 156 | /* Define chip-selects as reserved by default until probe completes */ |
| 155 | static unsigned int gpmc_cs_map = ((1 << GPMC_CS_NUM) - 1); | 157 | static unsigned int gpmc_cs_map = ((1 << GPMC_CS_NUM) - 1); |
| 158 | static unsigned int gpmc_nr_waitpins; | ||
| 156 | static struct device *gpmc_dev; | 159 | static struct device *gpmc_dev; |
| 157 | static int gpmc_irq; | 160 | static int gpmc_irq; |
| 158 | static resource_size_t phys_base, mem_size; | 161 | static resource_size_t phys_base, mem_size; |
| @@ -181,7 +184,7 @@ void gpmc_cs_write_reg(int cs, int idx, u32 val) | |||
| 181 | __raw_writel(val, reg_addr); | 184 | __raw_writel(val, reg_addr); |
| 182 | } | 185 | } |
| 183 | 186 | ||
| 184 | u32 gpmc_cs_read_reg(int cs, int idx) | 187 | static u32 gpmc_cs_read_reg(int cs, int idx) |
| 185 | { | 188 | { |
| 186 | void __iomem *reg_addr; | 189 | void __iomem *reg_addr; |
| 187 | 190 | ||
| @@ -190,7 +193,7 @@ u32 gpmc_cs_read_reg(int cs, int idx) | |||
| 190 | } | 193 | } |
| 191 | 194 | ||
| 192 | /* TODO: Add support for gpmc_fck to clock framework and use it */ | 195 | /* TODO: Add support for gpmc_fck to clock framework and use it */ |
| 193 | unsigned long gpmc_get_fclk_period(void) | 196 | static unsigned long gpmc_get_fclk_period(void) |
| 194 | { | 197 | { |
| 195 | unsigned long rate = clk_get_rate(gpmc_l3_clk); | 198 | unsigned long rate = clk_get_rate(gpmc_l3_clk); |
| 196 | 199 | ||
| @@ -205,7 +208,7 @@ unsigned long gpmc_get_fclk_period(void) | |||
| 205 | return rate; | 208 | return rate; |
| 206 | } | 209 | } |
| 207 | 210 | ||
| 208 | unsigned int gpmc_ns_to_ticks(unsigned int time_ns) | 211 | static unsigned int gpmc_ns_to_ticks(unsigned int time_ns) |
| 209 | { | 212 | { |
| 210 | unsigned long tick_ps; | 213 | unsigned long tick_ps; |
| 211 | 214 | ||
| @@ -215,7 +218,7 @@ unsigned int gpmc_ns_to_ticks(unsigned int time_ns) | |||
| 215 | return (time_ns * 1000 + tick_ps - 1) / tick_ps; | 218 | return (time_ns * 1000 + tick_ps - 1) / tick_ps; |
| 216 | } | 219 | } |
| 217 | 220 | ||
| 218 | unsigned int gpmc_ps_to_ticks(unsigned int time_ps) | 221 | static unsigned int gpmc_ps_to_ticks(unsigned int time_ps) |
| 219 | { | 222 | { |
| 220 | unsigned long tick_ps; | 223 | unsigned long tick_ps; |
| 221 | 224 | ||
| @@ -230,13 +233,6 @@ unsigned int gpmc_ticks_to_ns(unsigned int ticks) | |||
| 230 | return ticks * gpmc_get_fclk_period() / 1000; | 233 | return ticks * gpmc_get_fclk_period() / 1000; |
| 231 | } | 234 | } |
| 232 | 235 | ||
| 233 | unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns) | ||
| 234 | { | ||
| 235 | unsigned long ticks = gpmc_ns_to_ticks(time_ns); | ||
| 236 | |||
| 237 | return ticks * gpmc_get_fclk_period() / 1000; | ||
| 238 | } | ||
| 239 | |||
| 240 | static unsigned int gpmc_ticks_to_ps(unsigned int ticks) | 236 | static unsigned int gpmc_ticks_to_ps(unsigned int ticks) |
| 241 | { | 237 | { |
| 242 | return ticks * gpmc_get_fclk_period(); | 238 | return ticks * gpmc_get_fclk_period(); |
| @@ -405,11 +401,18 @@ int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t) | |||
| 405 | return 0; | 401 | return 0; |
| 406 | } | 402 | } |
| 407 | 403 | ||
| 408 | static void gpmc_cs_enable_mem(int cs, u32 base, u32 size) | 404 | static int gpmc_cs_enable_mem(int cs, u32 base, u32 size) |
| 409 | { | 405 | { |
| 410 | u32 l; | 406 | u32 l; |
| 411 | u32 mask; | 407 | u32 mask; |
| 412 | 408 | ||
| 409 | /* | ||
| 410 | * Ensure that base address is aligned on a | ||
| 411 | * boundary equal to or greater than size. | ||
| 412 | */ | ||
| 413 | if (base & (size - 1)) | ||
| 414 | return -EINVAL; | ||
| 415 | |||
| 413 | mask = (1 << GPMC_SECTION_SHIFT) - size; | 416 | mask = (1 << GPMC_SECTION_SHIFT) - size; |
| 414 | l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); | 417 | l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); |
| 415 | l &= ~0x3f; | 418 | l &= ~0x3f; |
| @@ -418,6 +421,8 @@ static void gpmc_cs_enable_mem(int cs, u32 base, u32 size) | |||
| 418 | l |= ((mask >> GPMC_CHUNK_SHIFT) & 0x0f) << 8; | 421 | l |= ((mask >> GPMC_CHUNK_SHIFT) & 0x0f) << 8; |
| 419 | l |= GPMC_CONFIG7_CSVALID; | 422 | l |= GPMC_CONFIG7_CSVALID; |
| 420 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l); | 423 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l); |
| 424 | |||
| 425 | return 0; | ||
| 421 | } | 426 | } |
| 422 | 427 | ||
| 423 | static void gpmc_cs_disable_mem(int cs) | 428 | static void gpmc_cs_disable_mem(int cs) |
| @@ -448,22 +453,14 @@ static int gpmc_cs_mem_enabled(int cs) | |||
| 448 | return l & GPMC_CONFIG7_CSVALID; | 453 | return l & GPMC_CONFIG7_CSVALID; |
| 449 | } | 454 | } |
| 450 | 455 | ||
| 451 | int gpmc_cs_set_reserved(int cs, int reserved) | 456 | static void gpmc_cs_set_reserved(int cs, int reserved) |
| 452 | { | 457 | { |
| 453 | if (cs > GPMC_CS_NUM) | ||
| 454 | return -ENODEV; | ||
| 455 | |||
| 456 | gpmc_cs_map &= ~(1 << cs); | 458 | gpmc_cs_map &= ~(1 << cs); |
| 457 | gpmc_cs_map |= (reserved ? 1 : 0) << cs; | 459 | gpmc_cs_map |= (reserved ? 1 : 0) << cs; |
| 458 | |||
| 459 | return 0; | ||
| 460 | } | 460 | } |
| 461 | 461 | ||
| 462 | int gpmc_cs_reserved(int cs) | 462 | static bool gpmc_cs_reserved(int cs) |
| 463 | { | 463 | { |
| 464 | if (cs > GPMC_CS_NUM) | ||
| 465 | return -ENODEV; | ||
| 466 | |||
| 467 | return gpmc_cs_map & (1 << cs); | 464 | return gpmc_cs_map & (1 << cs); |
| 468 | } | 465 | } |
| 469 | 466 | ||
| @@ -510,6 +507,39 @@ static int gpmc_cs_delete_mem(int cs) | |||
| 510 | return r; | 507 | return r; |
| 511 | } | 508 | } |
| 512 | 509 | ||
| 510 | /** | ||
| 511 | * gpmc_cs_remap - remaps a chip-select physical base address | ||
| 512 | * @cs: chip-select to remap | ||
| 513 | * @base: physical base address to re-map chip-select to | ||
| 514 | * | ||
| 515 | * Re-maps a chip-select to a new physical base address specified by | ||
| 516 | * "base". Returns 0 on success and appropriate negative error code | ||
| 517 | * on failure. | ||
| 518 | */ | ||
| 519 | static int gpmc_cs_remap(int cs, u32 base) | ||
| 520 | { | ||
| 521 | int ret; | ||
| 522 | u32 old_base, size; | ||
| 523 | |||
| 524 | if (cs > GPMC_CS_NUM) | ||
| 525 | return -ENODEV; | ||
| 526 | gpmc_cs_get_memconf(cs, &old_base, &size); | ||
| 527 | if (base == old_base) | ||
| 528 | return 0; | ||
| 529 | gpmc_cs_disable_mem(cs); | ||
| 530 | ret = gpmc_cs_delete_mem(cs); | ||
| 531 | if (ret < 0) | ||
| 532 | return ret; | ||
| 533 | ret = gpmc_cs_insert_mem(cs, base, size); | ||
| 534 | if (ret < 0) | ||
| 535 | return ret; | ||
| 536 | ret = gpmc_cs_enable_mem(cs, base, size); | ||
| 537 | if (ret < 0) | ||
| 538 | return ret; | ||
| 539 | |||
| 540 | return 0; | ||
| 541 | } | ||
| 542 | |||
| 513 | int gpmc_cs_request(int cs, unsigned long size, unsigned long *base) | 543 | int gpmc_cs_request(int cs, unsigned long size, unsigned long *base) |
| 514 | { | 544 | { |
| 515 | struct resource *res = &gpmc_cs_mem[cs]; | 545 | struct resource *res = &gpmc_cs_mem[cs]; |
| @@ -535,7 +565,12 @@ int gpmc_cs_request(int cs, unsigned long size, unsigned long *base) | |||
| 535 | if (r < 0) | 565 | if (r < 0) |
| 536 | goto out; | 566 | goto out; |
| 537 | 567 | ||
| 538 | gpmc_cs_enable_mem(cs, res->start, resource_size(res)); | 568 | r = gpmc_cs_enable_mem(cs, res->start, resource_size(res)); |
| 569 | if (r < 0) { | ||
| 570 | release_resource(res); | ||
| 571 | goto out; | ||
| 572 | } | ||
| 573 | |||
| 539 | *base = res->start; | 574 | *base = res->start; |
| 540 | gpmc_cs_set_reserved(cs, 1); | 575 | gpmc_cs_set_reserved(cs, 1); |
| 541 | out: | 576 | out: |
| @@ -561,16 +596,14 @@ void gpmc_cs_free(int cs) | |||
| 561 | EXPORT_SYMBOL(gpmc_cs_free); | 596 | EXPORT_SYMBOL(gpmc_cs_free); |
| 562 | 597 | ||
| 563 | /** | 598 | /** |
| 564 | * gpmc_cs_configure - write request to configure gpmc | 599 | * gpmc_configure - write request to configure gpmc |
| 565 | * @cs: chip select number | ||
| 566 | * @cmd: command type | 600 | * @cmd: command type |
| 567 | * @wval: value to write | 601 | * @wval: value to write |
| 568 | * @return status of the operation | 602 | * @return status of the operation |
| 569 | */ | 603 | */ |
| 570 | int gpmc_cs_configure(int cs, int cmd, int wval) | 604 | int gpmc_configure(int cmd, int wval) |
| 571 | { | 605 | { |
| 572 | int err = 0; | 606 | u32 regval; |
| 573 | u32 regval = 0; | ||
| 574 | 607 | ||
| 575 | switch (cmd) { | 608 | switch (cmd) { |
| 576 | case GPMC_ENABLE_IRQ: | 609 | case GPMC_ENABLE_IRQ: |
| @@ -590,43 +623,14 @@ int gpmc_cs_configure(int cs, int cmd, int wval) | |||
| 590 | gpmc_write_reg(GPMC_CONFIG, regval); | 623 | gpmc_write_reg(GPMC_CONFIG, regval); |
| 591 | break; | 624 | break; |
| 592 | 625 | ||
| 593 | case GPMC_CONFIG_RDY_BSY: | ||
| 594 | regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); | ||
| 595 | if (wval) | ||
| 596 | regval |= WR_RD_PIN_MONITORING; | ||
| 597 | else | ||
| 598 | regval &= ~WR_RD_PIN_MONITORING; | ||
| 599 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval); | ||
| 600 | break; | ||
| 601 | |||
| 602 | case GPMC_CONFIG_DEV_SIZE: | ||
| 603 | regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); | ||
| 604 | |||
| 605 | /* clear 2 target bits */ | ||
| 606 | regval &= ~GPMC_CONFIG1_DEVICESIZE(3); | ||
| 607 | |||
| 608 | /* set the proper value */ | ||
| 609 | regval |= GPMC_CONFIG1_DEVICESIZE(wval); | ||
| 610 | |||
| 611 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval); | ||
| 612 | break; | ||
| 613 | |||
| 614 | case GPMC_CONFIG_DEV_TYPE: | ||
| 615 | regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); | ||
| 616 | regval |= GPMC_CONFIG1_DEVICETYPE(wval); | ||
| 617 | if (wval == GPMC_DEVICETYPE_NOR) | ||
| 618 | regval |= GPMC_CONFIG1_MUXADDDATA; | ||
| 619 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval); | ||
| 620 | break; | ||
| 621 | |||
| 622 | default: | 626 | default: |
| 623 | printk(KERN_ERR "gpmc_configure_cs: Not supported\n"); | 627 | pr_err("%s: command not supported\n", __func__); |
| 624 | err = -EINVAL; | 628 | return -EINVAL; |
| 625 | } | 629 | } |
| 626 | 630 | ||
| 627 | return err; | 631 | return 0; |
| 628 | } | 632 | } |
| 629 | EXPORT_SYMBOL(gpmc_cs_configure); | 633 | EXPORT_SYMBOL(gpmc_configure); |
| 630 | 634 | ||
| 631 | void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs) | 635 | void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs) |
| 632 | { | 636 | { |
| @@ -781,16 +785,16 @@ static void gpmc_mem_exit(void) | |||
| 781 | 785 | ||
| 782 | } | 786 | } |
| 783 | 787 | ||
| 784 | static int gpmc_mem_init(void) | 788 | static void gpmc_mem_init(void) |
| 785 | { | 789 | { |
| 786 | int cs, rc; | 790 | int cs; |
| 787 | unsigned long boot_rom_space = 0; | ||
| 788 | 791 | ||
| 789 | /* never allocate the first page, to facilitate bug detection; | 792 | /* |
| 790 | * even if we didn't boot from ROM. | 793 | * The first 1MB of GPMC address space is typically mapped to |
| 794 | * the internal ROM. Never allocate the first page, to | ||
| 795 | * facilitate bug detection; even if we didn't boot from ROM. | ||
| 791 | */ | 796 | */ |
| 792 | boot_rom_space = BOOT_ROM_SPACE; | 797 | gpmc_mem_root.start = SZ_1M; |
| 793 | gpmc_mem_root.start = GPMC_MEM_START + boot_rom_space; | ||
| 794 | gpmc_mem_root.end = GPMC_MEM_END; | 798 | gpmc_mem_root.end = GPMC_MEM_END; |
| 795 | 799 | ||
| 796 | /* Reserve all regions that has been set up by bootloader */ | 800 | /* Reserve all regions that has been set up by bootloader */ |
| @@ -800,16 +804,12 @@ static int gpmc_mem_init(void) | |||
| 800 | if (!gpmc_cs_mem_enabled(cs)) | 804 | if (!gpmc_cs_mem_enabled(cs)) |
| 801 | continue; | 805 | continue; |
| 802 | gpmc_cs_get_memconf(cs, &base, &size); | 806 | gpmc_cs_get_memconf(cs, &base, &size); |
| 803 | rc = gpmc_cs_insert_mem(cs, base, size); | 807 | if (gpmc_cs_insert_mem(cs, base, size)) { |
| 804 | if (rc < 0) { | 808 | pr_warn("%s: disabling cs %d mapped at 0x%x-0x%x\n", |
| 805 | while (--cs >= 0) | 809 | __func__, cs, base, base + size); |
| 806 | if (gpmc_cs_mem_enabled(cs)) | 810 | gpmc_cs_disable_mem(cs); |
| 807 | gpmc_cs_delete_mem(cs); | ||
| 808 | return rc; | ||
| 809 | } | 811 | } |
| 810 | } | 812 | } |
| 811 | |||
| 812 | return 0; | ||
| 813 | } | 813 | } |
| 814 | 814 | ||
| 815 | static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk) | 815 | static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk) |
| @@ -825,9 +825,9 @@ static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk) | |||
| 825 | 825 | ||
| 826 | /* XXX: can the cycles be avoided ? */ | 826 | /* XXX: can the cycles be avoided ? */ |
| 827 | static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t, | 827 | static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t, |
| 828 | struct gpmc_device_timings *dev_t) | 828 | struct gpmc_device_timings *dev_t, |
| 829 | bool mux) | ||
| 829 | { | 830 | { |
| 830 | bool mux = dev_t->mux; | ||
| 831 | u32 temp; | 831 | u32 temp; |
| 832 | 832 | ||
| 833 | /* adv_rd_off */ | 833 | /* adv_rd_off */ |
| @@ -880,9 +880,9 @@ static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t, | |||
| 880 | } | 880 | } |
| 881 | 881 | ||
| 882 | static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t, | 882 | static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t, |
| 883 | struct gpmc_device_timings *dev_t) | 883 | struct gpmc_device_timings *dev_t, |
| 884 | bool mux) | ||
| 884 | { | 885 | { |
| 885 | bool mux = dev_t->mux; | ||
| 886 | u32 temp; | 886 | u32 temp; |
| 887 | 887 | ||
| 888 | /* adv_wr_off */ | 888 | /* adv_wr_off */ |
| @@ -942,9 +942,9 @@ static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t, | |||
| 942 | } | 942 | } |
| 943 | 943 | ||
| 944 | static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t, | 944 | static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t, |
| 945 | struct gpmc_device_timings *dev_t) | 945 | struct gpmc_device_timings *dev_t, |
| 946 | bool mux) | ||
| 946 | { | 947 | { |
| 947 | bool mux = dev_t->mux; | ||
| 948 | u32 temp; | 948 | u32 temp; |
| 949 | 949 | ||
| 950 | /* adv_rd_off */ | 950 | /* adv_rd_off */ |
| @@ -982,9 +982,9 @@ static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t, | |||
| 982 | } | 982 | } |
| 983 | 983 | ||
| 984 | static int gpmc_calc_async_write_timings(struct gpmc_timings *gpmc_t, | 984 | static int gpmc_calc_async_write_timings(struct gpmc_timings *gpmc_t, |
| 985 | struct gpmc_device_timings *dev_t) | 985 | struct gpmc_device_timings *dev_t, |
| 986 | bool mux) | ||
| 986 | { | 987 | { |
| 987 | bool mux = dev_t->mux; | ||
| 988 | u32 temp; | 988 | u32 temp; |
| 989 | 989 | ||
| 990 | /* adv_wr_off */ | 990 | /* adv_wr_off */ |
| @@ -1054,7 +1054,8 @@ static int gpmc_calc_sync_common_timings(struct gpmc_timings *gpmc_t, | |||
| 1054 | } | 1054 | } |
| 1055 | 1055 | ||
| 1056 | static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t, | 1056 | static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t, |
| 1057 | struct gpmc_device_timings *dev_t) | 1057 | struct gpmc_device_timings *dev_t, |
| 1058 | bool sync) | ||
| 1058 | { | 1059 | { |
| 1059 | u32 temp; | 1060 | u32 temp; |
| 1060 | 1061 | ||
| @@ -1068,7 +1069,7 @@ static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t, | |||
| 1068 | gpmc_t->cs_on + dev_t->t_ce_avd); | 1069 | gpmc_t->cs_on + dev_t->t_ce_avd); |
| 1069 | gpmc_t->adv_on = gpmc_round_ps_to_ticks(temp); | 1070 | gpmc_t->adv_on = gpmc_round_ps_to_ticks(temp); |
| 1070 | 1071 | ||
| 1071 | if (dev_t->sync_write || dev_t->sync_read) | 1072 | if (sync) |
| 1072 | gpmc_calc_sync_common_timings(gpmc_t, dev_t); | 1073 | gpmc_calc_sync_common_timings(gpmc_t, dev_t); |
| 1073 | 1074 | ||
| 1074 | return 0; | 1075 | return 0; |
| @@ -1103,21 +1104,29 @@ static void gpmc_convert_ps_to_ns(struct gpmc_timings *t) | |||
| 1103 | } | 1104 | } |
| 1104 | 1105 | ||
| 1105 | int gpmc_calc_timings(struct gpmc_timings *gpmc_t, | 1106 | int gpmc_calc_timings(struct gpmc_timings *gpmc_t, |
| 1106 | struct gpmc_device_timings *dev_t) | 1107 | struct gpmc_settings *gpmc_s, |
| 1108 | struct gpmc_device_timings *dev_t) | ||
| 1107 | { | 1109 | { |
| 1110 | bool mux = false, sync = false; | ||
| 1111 | |||
| 1112 | if (gpmc_s) { | ||
| 1113 | mux = gpmc_s->mux_add_data ? true : false; | ||
| 1114 | sync = (gpmc_s->sync_read || gpmc_s->sync_write); | ||
| 1115 | } | ||
| 1116 | |||
| 1108 | memset(gpmc_t, 0, sizeof(*gpmc_t)); | 1117 | memset(gpmc_t, 0, sizeof(*gpmc_t)); |
| 1109 | 1118 | ||
| 1110 | gpmc_calc_common_timings(gpmc_t, dev_t); | 1119 | gpmc_calc_common_timings(gpmc_t, dev_t, sync); |
| 1111 | 1120 | ||
| 1112 | if (dev_t->sync_read) | 1121 | if (gpmc_s && gpmc_s->sync_read) |
| 1113 | gpmc_calc_sync_read_timings(gpmc_t, dev_t); | 1122 | gpmc_calc_sync_read_timings(gpmc_t, dev_t, mux); |
| 1114 | else | 1123 | else |
| 1115 | gpmc_calc_async_read_timings(gpmc_t, dev_t); | 1124 | gpmc_calc_async_read_timings(gpmc_t, dev_t, mux); |
| 1116 | 1125 | ||
| 1117 | if (dev_t->sync_write) | 1126 | if (gpmc_s && gpmc_s->sync_write) |
| 1118 | gpmc_calc_sync_write_timings(gpmc_t, dev_t); | 1127 | gpmc_calc_sync_write_timings(gpmc_t, dev_t, mux); |
| 1119 | else | 1128 | else |
| 1120 | gpmc_calc_async_write_timings(gpmc_t, dev_t); | 1129 | gpmc_calc_async_write_timings(gpmc_t, dev_t, mux); |
| 1121 | 1130 | ||
| 1122 | /* TODO: remove, see function definition */ | 1131 | /* TODO: remove, see function definition */ |
| 1123 | gpmc_convert_ps_to_ns(gpmc_t); | 1132 | gpmc_convert_ps_to_ns(gpmc_t); |
| @@ -1125,6 +1134,90 @@ int gpmc_calc_timings(struct gpmc_timings *gpmc_t, | |||
| 1125 | return 0; | 1134 | return 0; |
| 1126 | } | 1135 | } |
| 1127 | 1136 | ||
| 1137 | /** | ||
| 1138 | * gpmc_cs_program_settings - programs non-timing related settings | ||
| 1139 | * @cs: GPMC chip-select to program | ||
| 1140 | * @p: pointer to GPMC settings structure | ||
| 1141 | * | ||
| 1142 | * Programs non-timing related settings for a GPMC chip-select, such as | ||
| 1143 | * bus-width, burst configuration, etc. Function should be called once | ||
| 1144 | * for each chip-select that is being used and must be called before | ||
| 1145 | * calling gpmc_cs_set_timings() as timing parameters in the CONFIG1 | ||
| 1146 | * register will be initialised to zero by this function. Returns 0 on | ||
| 1147 | * success and appropriate negative error code on failure. | ||
| 1148 | */ | ||
| 1149 | int gpmc_cs_program_settings(int cs, struct gpmc_settings *p) | ||
| 1150 | { | ||
| 1151 | u32 config1; | ||
| 1152 | |||
| 1153 | if ((!p->device_width) || (p->device_width > GPMC_DEVWIDTH_16BIT)) { | ||
| 1154 | pr_err("%s: invalid width %d!", __func__, p->device_width); | ||
| 1155 | return -EINVAL; | ||
| 1156 | } | ||
| 1157 | |||
| 1158 | /* Address-data multiplexing not supported for NAND devices */ | ||
| 1159 | if (p->device_nand && p->mux_add_data) { | ||
| 1160 | pr_err("%s: invalid configuration!\n", __func__); | ||
| 1161 | return -EINVAL; | ||
| 1162 | } | ||
| 1163 | |||
| 1164 | if ((p->mux_add_data > GPMC_MUX_AD) || | ||
| 1165 | ((p->mux_add_data == GPMC_MUX_AAD) && | ||
| 1166 | !(gpmc_capability & GPMC_HAS_MUX_AAD))) { | ||
| 1167 | pr_err("%s: invalid multiplex configuration!\n", __func__); | ||
| 1168 | return -EINVAL; | ||
| 1169 | } | ||
| 1170 | |||
| 1171 | /* Page/burst mode supports lengths of 4, 8 and 16 bytes */ | ||
| 1172 | if (p->burst_read || p->burst_write) { | ||
| 1173 | switch (p->burst_len) { | ||
| 1174 | case GPMC_BURST_4: | ||
| 1175 | case GPMC_BURST_8: | ||
| 1176 | case GPMC_BURST_16: | ||
| 1177 | break; | ||
| 1178 | default: | ||
| 1179 | pr_err("%s: invalid page/burst-length (%d)\n", | ||
| 1180 | __func__, p->burst_len); | ||
| 1181 | return -EINVAL; | ||
| 1182 | } | ||
| 1183 | } | ||
| 1184 | |||
| 1185 | if ((p->wait_on_read || p->wait_on_write) && | ||
| 1186 | (p->wait_pin > gpmc_nr_waitpins)) { | ||
| 1187 | pr_err("%s: invalid wait-pin (%d)\n", __func__, p->wait_pin); | ||
| 1188 | return -EINVAL; | ||
| 1189 | } | ||
| 1190 | |||
| 1191 | config1 = GPMC_CONFIG1_DEVICESIZE((p->device_width - 1)); | ||
| 1192 | |||
| 1193 | if (p->sync_read) | ||
| 1194 | config1 |= GPMC_CONFIG1_READTYPE_SYNC; | ||
| 1195 | if (p->sync_write) | ||
| 1196 | config1 |= GPMC_CONFIG1_WRITETYPE_SYNC; | ||
| 1197 | if (p->wait_on_read) | ||
| 1198 | config1 |= GPMC_CONFIG1_WAIT_READ_MON; | ||
| 1199 | if (p->wait_on_write) | ||
| 1200 | config1 |= GPMC_CONFIG1_WAIT_WRITE_MON; | ||
| 1201 | if (p->wait_on_read || p->wait_on_write) | ||
| 1202 | config1 |= GPMC_CONFIG1_WAIT_PIN_SEL(p->wait_pin); | ||
| 1203 | if (p->device_nand) | ||
| 1204 | config1 |= GPMC_CONFIG1_DEVICETYPE(GPMC_DEVICETYPE_NAND); | ||
| 1205 | if (p->mux_add_data) | ||
| 1206 | config1 |= GPMC_CONFIG1_MUXTYPE(p->mux_add_data); | ||
| 1207 | if (p->burst_read) | ||
| 1208 | config1 |= GPMC_CONFIG1_READMULTIPLE_SUPP; | ||
| 1209 | if (p->burst_write) | ||
| 1210 | config1 |= GPMC_CONFIG1_WRITEMULTIPLE_SUPP; | ||
| 1211 | if (p->burst_read || p->burst_write) { | ||
| 1212 | config1 |= GPMC_CONFIG1_PAGE_LEN(p->burst_len >> 3); | ||
| 1213 | config1 |= p->burst_wrap ? GPMC_CONFIG1_WRAPBURST_SUPP : 0; | ||
| 1214 | } | ||
| 1215 | |||
| 1216 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, config1); | ||
| 1217 | |||
| 1218 | return 0; | ||
| 1219 | } | ||
| 1220 | |||
| 1128 | #ifdef CONFIG_OF | 1221 | #ifdef CONFIG_OF |
| 1129 | static struct of_device_id gpmc_dt_ids[] = { | 1222 | static struct of_device_id gpmc_dt_ids[] = { |
| 1130 | { .compatible = "ti,omap2420-gpmc" }, | 1223 | { .compatible = "ti,omap2420-gpmc" }, |
| @@ -1136,70 +1229,110 @@ static struct of_device_id gpmc_dt_ids[] = { | |||
| 1136 | }; | 1229 | }; |
| 1137 | MODULE_DEVICE_TABLE(of, gpmc_dt_ids); | 1230 | MODULE_DEVICE_TABLE(of, gpmc_dt_ids); |
| 1138 | 1231 | ||
| 1232 | /** | ||
| 1233 | * gpmc_read_settings_dt - read gpmc settings from device-tree | ||
| 1234 | * @np: pointer to device-tree node for a gpmc child device | ||
| 1235 | * @p: pointer to gpmc settings structure | ||
| 1236 | * | ||
| 1237 | * Reads the GPMC settings for a GPMC child device from device-tree and | ||
| 1238 | * stores them in the GPMC settings structure passed. The GPMC settings | ||
| 1239 | * structure is initialised to zero by this function and so any | ||
| 1240 | * previously stored settings will be cleared. | ||
| 1241 | */ | ||
| 1242 | void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p) | ||
| 1243 | { | ||
| 1244 | memset(p, 0, sizeof(struct gpmc_settings)); | ||
| 1245 | |||
| 1246 | p->sync_read = of_property_read_bool(np, "gpmc,sync-read"); | ||
| 1247 | p->sync_write = of_property_read_bool(np, "gpmc,sync-write"); | ||
| 1248 | p->device_nand = of_property_read_bool(np, "gpmc,device-nand"); | ||
| 1249 | of_property_read_u32(np, "gpmc,device-width", &p->device_width); | ||
| 1250 | of_property_read_u32(np, "gpmc,mux-add-data", &p->mux_add_data); | ||
| 1251 | |||
| 1252 | if (!of_property_read_u32(np, "gpmc,burst-length", &p->burst_len)) { | ||
| 1253 | p->burst_wrap = of_property_read_bool(np, "gpmc,burst-wrap"); | ||
| 1254 | p->burst_read = of_property_read_bool(np, "gpmc,burst-read"); | ||
| 1255 | p->burst_write = of_property_read_bool(np, "gpmc,burst-write"); | ||
| 1256 | if (!p->burst_read && !p->burst_write) | ||
| 1257 | pr_warn("%s: page/burst-length set but not used!\n", | ||
| 1258 | __func__); | ||
| 1259 | } | ||
| 1260 | |||
| 1261 | if (!of_property_read_u32(np, "gpmc,wait-pin", &p->wait_pin)) { | ||
| 1262 | p->wait_on_read = of_property_read_bool(np, | ||
| 1263 | "gpmc,wait-on-read"); | ||
| 1264 | p->wait_on_write = of_property_read_bool(np, | ||
| 1265 | "gpmc,wait-on-write"); | ||
| 1266 | if (!p->wait_on_read && !p->wait_on_write) | ||
| 1267 | pr_warn("%s: read/write wait monitoring not enabled!\n", | ||
| 1268 | __func__); | ||
| 1269 | } | ||
| 1270 | } | ||
| 1271 | |||
| 1139 | static void __maybe_unused gpmc_read_timings_dt(struct device_node *np, | 1272 | static void __maybe_unused gpmc_read_timings_dt(struct device_node *np, |
| 1140 | struct gpmc_timings *gpmc_t) | 1273 | struct gpmc_timings *gpmc_t) |
| 1141 | { | 1274 | { |
| 1142 | u32 val; | 1275 | struct gpmc_bool_timings *p; |
| 1276 | |||
| 1277 | if (!np || !gpmc_t) | ||
| 1278 | return; | ||
| 1143 | 1279 | ||
| 1144 | memset(gpmc_t, 0, sizeof(*gpmc_t)); | 1280 | memset(gpmc_t, 0, sizeof(*gpmc_t)); |
| 1145 | 1281 | ||
| 1146 | /* minimum clock period for syncronous mode */ | 1282 | /* minimum clock period for syncronous mode */ |
| 1147 | if (!of_property_read_u32(np, "gpmc,sync-clk", &val)) | 1283 | of_property_read_u32(np, "gpmc,sync-clk-ps", &gpmc_t->sync_clk); |
| 1148 | gpmc_t->sync_clk = val; | ||
| 1149 | 1284 | ||
| 1150 | /* chip select timtings */ | 1285 | /* chip select timtings */ |
| 1151 | if (!of_property_read_u32(np, "gpmc,cs-on", &val)) | 1286 | of_property_read_u32(np, "gpmc,cs-on-ns", &gpmc_t->cs_on); |
| 1152 | gpmc_t->cs_on = val; | 1287 | of_property_read_u32(np, "gpmc,cs-rd-off-ns", &gpmc_t->cs_rd_off); |
| 1153 | 1288 | of_property_read_u32(np, "gpmc,cs-wr-off-ns", &gpmc_t->cs_wr_off); | |
| 1154 | if (!of_property_read_u32(np, "gpmc,cs-rd-off", &val)) | ||
| 1155 | gpmc_t->cs_rd_off = val; | ||
| 1156 | |||
| 1157 | if (!of_property_read_u32(np, "gpmc,cs-wr-off", &val)) | ||
| 1158 | gpmc_t->cs_wr_off = val; | ||
| 1159 | 1289 | ||
| 1160 | /* ADV signal timings */ | 1290 | /* ADV signal timings */ |
| 1161 | if (!of_property_read_u32(np, "gpmc,adv-on", &val)) | 1291 | of_property_read_u32(np, "gpmc,adv-on-ns", &gpmc_t->adv_on); |
| 1162 | gpmc_t->adv_on = val; | 1292 | of_property_read_u32(np, "gpmc,adv-rd-off-ns", &gpmc_t->adv_rd_off); |
| 1163 | 1293 | of_property_read_u32(np, "gpmc,adv-wr-off-ns", &gpmc_t->adv_wr_off); | |
| 1164 | if (!of_property_read_u32(np, "gpmc,adv-rd-off", &val)) | ||
| 1165 | gpmc_t->adv_rd_off = val; | ||
| 1166 | |||
| 1167 | if (!of_property_read_u32(np, "gpmc,adv-wr-off", &val)) | ||
| 1168 | gpmc_t->adv_wr_off = val; | ||
| 1169 | 1294 | ||
| 1170 | /* WE signal timings */ | 1295 | /* WE signal timings */ |
| 1171 | if (!of_property_read_u32(np, "gpmc,we-on", &val)) | 1296 | of_property_read_u32(np, "gpmc,we-on-ns", &gpmc_t->we_on); |
| 1172 | gpmc_t->we_on = val; | 1297 | of_property_read_u32(np, "gpmc,we-off-ns", &gpmc_t->we_off); |
| 1173 | |||
| 1174 | if (!of_property_read_u32(np, "gpmc,we-off", &val)) | ||
| 1175 | gpmc_t->we_off = val; | ||
| 1176 | 1298 | ||
| 1177 | /* OE signal timings */ | 1299 | /* OE signal timings */ |
| 1178 | if (!of_property_read_u32(np, "gpmc,oe-on", &val)) | 1300 | of_property_read_u32(np, "gpmc,oe-on-ns", &gpmc_t->oe_on); |
| 1179 | gpmc_t->oe_on = val; | 1301 | of_property_read_u32(np, "gpmc,oe-off-ns", &gpmc_t->oe_off); |
| 1180 | |||
| 1181 | if (!of_property_read_u32(np, "gpmc,oe-off", &val)) | ||
| 1182 | gpmc_t->oe_off = val; | ||
| 1183 | 1302 | ||
| 1184 | /* access and cycle timings */ | 1303 | /* access and cycle timings */ |
| 1185 | if (!of_property_read_u32(np, "gpmc,page-burst-access", &val)) | 1304 | of_property_read_u32(np, "gpmc,page-burst-access-ns", |
| 1186 | gpmc_t->page_burst_access = val; | 1305 | &gpmc_t->page_burst_access); |
| 1187 | 1306 | of_property_read_u32(np, "gpmc,access-ns", &gpmc_t->access); | |
| 1188 | if (!of_property_read_u32(np, "gpmc,access", &val)) | 1307 | of_property_read_u32(np, "gpmc,rd-cycle-ns", &gpmc_t->rd_cycle); |
| 1189 | gpmc_t->access = val; | 1308 | of_property_read_u32(np, "gpmc,wr-cycle-ns", &gpmc_t->wr_cycle); |
| 1190 | 1309 | of_property_read_u32(np, "gpmc,bus-turnaround-ns", | |
| 1191 | if (!of_property_read_u32(np, "gpmc,rd-cycle", &val)) | 1310 | &gpmc_t->bus_turnaround); |
| 1192 | gpmc_t->rd_cycle = val; | 1311 | of_property_read_u32(np, "gpmc,cycle2cycle-delay-ns", |
| 1193 | 1312 | &gpmc_t->cycle2cycle_delay); | |
| 1194 | if (!of_property_read_u32(np, "gpmc,wr-cycle", &val)) | 1313 | of_property_read_u32(np, "gpmc,wait-monitoring-ns", |
| 1195 | gpmc_t->wr_cycle = val; | 1314 | &gpmc_t->wait_monitoring); |
| 1196 | 1315 | of_property_read_u32(np, "gpmc,clk-activation-ns", | |
| 1197 | /* only for OMAP3430 */ | 1316 | &gpmc_t->clk_activation); |
| 1198 | if (!of_property_read_u32(np, "gpmc,wr-access", &val)) | 1317 | |
| 1199 | gpmc_t->wr_access = val; | 1318 | /* only applicable to OMAP3+ */ |
| 1200 | 1319 | of_property_read_u32(np, "gpmc,wr-access-ns", &gpmc_t->wr_access); | |
| 1201 | if (!of_property_read_u32(np, "gpmc,wr-data-mux-bus", &val)) | 1320 | of_property_read_u32(np, "gpmc,wr-data-mux-bus-ns", |
| 1202 | gpmc_t->wr_data_mux_bus = val; | 1321 | &gpmc_t->wr_data_mux_bus); |
| 1322 | |||
| 1323 | /* bool timing parameters */ | ||
| 1324 | p = &gpmc_t->bool_timings; | ||
| 1325 | |||
| 1326 | p->cycle2cyclediffcsen = | ||
| 1327 | of_property_read_bool(np, "gpmc,cycle2cycle-diffcsen"); | ||
| 1328 | p->cycle2cyclesamecsen = | ||
| 1329 | of_property_read_bool(np, "gpmc,cycle2cycle-samecsen"); | ||
| 1330 | p->we_extra_delay = of_property_read_bool(np, "gpmc,we-extra-delay"); | ||
| 1331 | p->oe_extra_delay = of_property_read_bool(np, "gpmc,oe-extra-delay"); | ||
| 1332 | p->adv_extra_delay = of_property_read_bool(np, "gpmc,adv-extra-delay"); | ||
| 1333 | p->cs_extra_delay = of_property_read_bool(np, "gpmc,cs-extra-delay"); | ||
| 1334 | p->time_para_granularity = | ||
| 1335 | of_property_read_bool(np, "gpmc,time-para-granularity"); | ||
| 1203 | } | 1336 | } |
| 1204 | 1337 | ||
| 1205 | #ifdef CONFIG_MTD_NAND | 1338 | #ifdef CONFIG_MTD_NAND |
| @@ -1295,6 +1428,81 @@ static int gpmc_probe_onenand_child(struct platform_device *pdev, | |||
| 1295 | } | 1428 | } |
| 1296 | #endif | 1429 | #endif |
| 1297 | 1430 | ||
| 1431 | /** | ||
| 1432 | * gpmc_probe_generic_child - configures the gpmc for a child device | ||
| 1433 | * @pdev: pointer to gpmc platform device | ||
| 1434 | * @child: pointer to device-tree node for child device | ||
| 1435 | * | ||
| 1436 | * Allocates and configures a GPMC chip-select for a child device. | ||
| 1437 | * Returns 0 on success and appropriate negative error code on failure. | ||
| 1438 | */ | ||
| 1439 | static int gpmc_probe_generic_child(struct platform_device *pdev, | ||
| 1440 | struct device_node *child) | ||
| 1441 | { | ||
| 1442 | struct gpmc_settings gpmc_s; | ||
| 1443 | struct gpmc_timings gpmc_t; | ||
| 1444 | struct resource res; | ||
| 1445 | unsigned long base; | ||
| 1446 | int ret, cs; | ||
| 1447 | |||
| 1448 | if (of_property_read_u32(child, "reg", &cs) < 0) { | ||
| 1449 | dev_err(&pdev->dev, "%s has no 'reg' property\n", | ||
| 1450 | child->full_name); | ||
| 1451 | return -ENODEV; | ||
| 1452 | } | ||
| 1453 | |||
| 1454 | if (of_address_to_resource(child, 0, &res) < 0) { | ||
| 1455 | dev_err(&pdev->dev, "%s has malformed 'reg' property\n", | ||
| 1456 | child->full_name); | ||
| 1457 | return -ENODEV; | ||
| 1458 | } | ||
| 1459 | |||
| 1460 | ret = gpmc_cs_request(cs, resource_size(&res), &base); | ||
| 1461 | if (ret < 0) { | ||
| 1462 | dev_err(&pdev->dev, "cannot request GPMC CS %d\n", cs); | ||
| 1463 | return ret; | ||
| 1464 | } | ||
| 1465 | |||
| 1466 | /* | ||
| 1467 | * FIXME: gpmc_cs_request() will map the CS to an arbitary | ||
| 1468 | * location in the gpmc address space. When booting with | ||
| 1469 | * device-tree we want the NOR flash to be mapped to the | ||
| 1470 | * location specified in the device-tree blob. So remap the | ||
| 1471 | * CS to this location. Once DT migration is complete should | ||
| 1472 | * just make gpmc_cs_request() map a specific address. | ||
| 1473 | */ | ||
| 1474 | ret = gpmc_cs_remap(cs, res.start); | ||
| 1475 | if (ret < 0) { | ||
| 1476 | dev_err(&pdev->dev, "cannot remap GPMC CS %d to 0x%x\n", | ||
| 1477 | cs, res.start); | ||
| 1478 | goto err; | ||
| 1479 | } | ||
| 1480 | |||
| 1481 | gpmc_read_settings_dt(child, &gpmc_s); | ||
| 1482 | |||
| 1483 | ret = of_property_read_u32(child, "bank-width", &gpmc_s.device_width); | ||
| 1484 | if (ret < 0) | ||
| 1485 | goto err; | ||
| 1486 | |||
| 1487 | ret = gpmc_cs_program_settings(cs, &gpmc_s); | ||
| 1488 | if (ret < 0) | ||
| 1489 | goto err; | ||
| 1490 | |||
| 1491 | gpmc_read_timings_dt(child, &gpmc_t); | ||
| 1492 | gpmc_cs_set_timings(cs, &gpmc_t); | ||
| 1493 | |||
| 1494 | if (of_platform_device_create(child, NULL, &pdev->dev)) | ||
| 1495 | return 0; | ||
| 1496 | |||
| 1497 | dev_err(&pdev->dev, "failed to create gpmc child %s\n", child->name); | ||
| 1498 | ret = -ENODEV; | ||
| 1499 | |||
| 1500 | err: | ||
| 1501 | gpmc_cs_free(cs); | ||
| 1502 | |||
| 1503 | return ret; | ||
| 1504 | } | ||
| 1505 | |||
| 1298 | static int gpmc_probe_dt(struct platform_device *pdev) | 1506 | static int gpmc_probe_dt(struct platform_device *pdev) |
| 1299 | { | 1507 | { |
| 1300 | int ret; | 1508 | int ret; |
| @@ -1305,6 +1513,13 @@ static int gpmc_probe_dt(struct platform_device *pdev) | |||
| 1305 | if (!of_id) | 1513 | if (!of_id) |
| 1306 | return 0; | 1514 | return 0; |
| 1307 | 1515 | ||
| 1516 | ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-waitpins", | ||
| 1517 | &gpmc_nr_waitpins); | ||
| 1518 | if (ret < 0) { | ||
| 1519 | pr_err("%s: number of wait pins not found!\n", __func__); | ||
| 1520 | return ret; | ||
| 1521 | } | ||
| 1522 | |||
| 1308 | for_each_node_by_name(child, "nand") { | 1523 | for_each_node_by_name(child, "nand") { |
| 1309 | ret = gpmc_probe_nand_child(pdev, child); | 1524 | ret = gpmc_probe_nand_child(pdev, child); |
| 1310 | if (ret < 0) { | 1525 | if (ret < 0) { |
| @@ -1320,6 +1535,23 @@ static int gpmc_probe_dt(struct platform_device *pdev) | |||
| 1320 | return ret; | 1535 | return ret; |
| 1321 | } | 1536 | } |
| 1322 | } | 1537 | } |
| 1538 | |||
| 1539 | for_each_node_by_name(child, "nor") { | ||
| 1540 | ret = gpmc_probe_generic_child(pdev, child); | ||
| 1541 | if (ret < 0) { | ||
| 1542 | of_node_put(child); | ||
| 1543 | return ret; | ||
| 1544 | } | ||
| 1545 | } | ||
| 1546 | |||
| 1547 | for_each_node_by_name(child, "ethernet") { | ||
| 1548 | ret = gpmc_probe_generic_child(pdev, child); | ||
| 1549 | if (ret < 0) { | ||
| 1550 | of_node_put(child); | ||
| 1551 | return ret; | ||
| 1552 | } | ||
| 1553 | } | ||
| 1554 | |||
| 1323 | return 0; | 1555 | return 0; |
| 1324 | } | 1556 | } |
| 1325 | #else | 1557 | #else |
| @@ -1364,18 +1596,27 @@ static int gpmc_probe(struct platform_device *pdev) | |||
| 1364 | gpmc_dev = &pdev->dev; | 1596 | gpmc_dev = &pdev->dev; |
| 1365 | 1597 | ||
| 1366 | l = gpmc_read_reg(GPMC_REVISION); | 1598 | l = gpmc_read_reg(GPMC_REVISION); |
| 1599 | |||
| 1600 | /* | ||
| 1601 | * FIXME: Once device-tree migration is complete the below flags | ||
| 1602 | * should be populated based upon the device-tree compatible | ||
| 1603 | * string. For now just use the IP revision. OMAP3+ devices have | ||
| 1604 | * the wr_access and wr_data_mux_bus register fields. OMAP4+ | ||
| 1605 | * devices support the addr-addr-data multiplex protocol. | ||
| 1606 | * | ||
| 1607 | * GPMC IP revisions: | ||
| 1608 | * - OMAP24xx = 2.0 | ||
| 1609 | * - OMAP3xxx = 5.0 | ||
| 1610 | * - OMAP44xx/54xx/AM335x = 6.0 | ||
| 1611 | */ | ||
| 1367 | if (GPMC_REVISION_MAJOR(l) > 0x4) | 1612 | if (GPMC_REVISION_MAJOR(l) > 0x4) |
| 1368 | gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS; | 1613 | gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS; |
| 1614 | if (GPMC_REVISION_MAJOR(l) > 0x5) | ||
| 1615 | gpmc_capability |= GPMC_HAS_MUX_AAD; | ||
| 1369 | dev_info(gpmc_dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l), | 1616 | dev_info(gpmc_dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l), |
| 1370 | GPMC_REVISION_MINOR(l)); | 1617 | GPMC_REVISION_MINOR(l)); |
| 1371 | 1618 | ||
| 1372 | rc = gpmc_mem_init(); | 1619 | gpmc_mem_init(); |
| 1373 | if (rc < 0) { | ||
| 1374 | clk_disable_unprepare(gpmc_l3_clk); | ||
| 1375 | clk_put(gpmc_l3_clk); | ||
| 1376 | dev_err(gpmc_dev, "failed to reserve memory\n"); | ||
| 1377 | return rc; | ||
| 1378 | } | ||
| 1379 | 1620 | ||
| 1380 | if (gpmc_setup_irq() < 0) | 1621 | if (gpmc_setup_irq() < 0) |
| 1381 | dev_warn(gpmc_dev, "gpmc_setup_irq failed\n"); | 1622 | dev_warn(gpmc_dev, "gpmc_setup_irq failed\n"); |
| @@ -1383,6 +1624,9 @@ static int gpmc_probe(struct platform_device *pdev) | |||
| 1383 | /* Now the GPMC is initialised, unreserve the chip-selects */ | 1624 | /* Now the GPMC is initialised, unreserve the chip-selects */ |
| 1384 | gpmc_cs_map = 0; | 1625 | gpmc_cs_map = 0; |
| 1385 | 1626 | ||
| 1627 | if (!pdev->dev.of_node) | ||
| 1628 | gpmc_nr_waitpins = GPMC_NR_WAITPINS; | ||
| 1629 | |||
| 1386 | rc = gpmc_probe_dt(pdev); | 1630 | rc = gpmc_probe_dt(pdev); |
| 1387 | if (rc < 0) { | 1631 | if (rc < 0) { |
| 1388 | clk_disable_unprepare(gpmc_l3_clk); | 1632 | clk_disable_unprepare(gpmc_l3_clk); |
diff --git a/arch/arm/mach-omap2/gpmc.h b/arch/arm/mach-omap2/gpmc.h index fe0a844d5007..707f6d58edd5 100644 --- a/arch/arm/mach-omap2/gpmc.h +++ b/arch/arm/mach-omap2/gpmc.h | |||
| @@ -58,7 +58,7 @@ | |||
| 58 | #define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1) | 58 | #define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1) |
| 59 | #define GPMC_CONFIG1_DEVICETYPE(val) ((val & 3) << 10) | 59 | #define GPMC_CONFIG1_DEVICETYPE(val) ((val & 3) << 10) |
| 60 | #define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0) | 60 | #define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0) |
| 61 | #define GPMC_CONFIG1_MUXADDDATA (1 << 9) | 61 | #define GPMC_CONFIG1_MUXTYPE(val) ((val & 3) << 8) |
| 62 | #define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4) | 62 | #define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4) |
| 63 | #define GPMC_CONFIG1_FCLK_DIV(val) (val & 3) | 63 | #define GPMC_CONFIG1_FCLK_DIV(val) (val & 3) |
| 64 | #define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1)) | 64 | #define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1)) |
| @@ -73,6 +73,13 @@ | |||
| 73 | #define GPMC_IRQ_FIFOEVENTENABLE 0x01 | 73 | #define GPMC_IRQ_FIFOEVENTENABLE 0x01 |
| 74 | #define GPMC_IRQ_COUNT_EVENT 0x02 | 74 | #define GPMC_IRQ_COUNT_EVENT 0x02 |
| 75 | 75 | ||
| 76 | #define GPMC_BURST_4 4 /* 4 word burst */ | ||
| 77 | #define GPMC_BURST_8 8 /* 8 word burst */ | ||
| 78 | #define GPMC_BURST_16 16 /* 16 word burst */ | ||
| 79 | #define GPMC_DEVWIDTH_8BIT 1 /* 8-bit device width */ | ||
| 80 | #define GPMC_DEVWIDTH_16BIT 2 /* 16-bit device width */ | ||
| 81 | #define GPMC_MUX_AAD 1 /* Addr-Addr-Data multiplex */ | ||
| 82 | #define GPMC_MUX_AD 2 /* Addr-Data multiplex */ | ||
| 76 | 83 | ||
| 77 | /* bool type time settings */ | 84 | /* bool type time settings */ |
| 78 | struct gpmc_bool_timings { | 85 | struct gpmc_bool_timings { |
| @@ -178,10 +185,6 @@ struct gpmc_device_timings { | |||
| 178 | u8 cyc_wpl; /* write deassertion time in cycles */ | 185 | u8 cyc_wpl; /* write deassertion time in cycles */ |
| 179 | u32 cyc_iaa; /* initial access time in cycles */ | 186 | u32 cyc_iaa; /* initial access time in cycles */ |
| 180 | 187 | ||
| 181 | bool mux; /* address & data muxed */ | ||
| 182 | bool sync_write;/* synchronous write */ | ||
| 183 | bool sync_read; /* synchronous read */ | ||
| 184 | |||
| 185 | /* extra delays */ | 188 | /* extra delays */ |
| 186 | bool ce_xdelay; | 189 | bool ce_xdelay; |
| 187 | bool avd_xdelay; | 190 | bool avd_xdelay; |
| @@ -189,28 +192,40 @@ struct gpmc_device_timings { | |||
| 189 | bool we_xdelay; | 192 | bool we_xdelay; |
| 190 | }; | 193 | }; |
| 191 | 194 | ||
| 195 | struct gpmc_settings { | ||
| 196 | bool burst_wrap; /* enables wrap bursting */ | ||
| 197 | bool burst_read; /* enables read page/burst mode */ | ||
| 198 | bool burst_write; /* enables write page/burst mode */ | ||
| 199 | bool device_nand; /* device is NAND */ | ||
| 200 | bool sync_read; /* enables synchronous reads */ | ||
| 201 | bool sync_write; /* enables synchronous writes */ | ||
| 202 | bool wait_on_read; /* monitor wait on reads */ | ||
| 203 | bool wait_on_write; /* monitor wait on writes */ | ||
| 204 | u32 burst_len; /* page/burst length */ | ||
| 205 | u32 device_width; /* device bus width (8 or 16 bit) */ | ||
| 206 | u32 mux_add_data; /* multiplex address & data */ | ||
| 207 | u32 wait_pin; /* wait-pin to be used */ | ||
| 208 | }; | ||
| 209 | |||
| 192 | extern int gpmc_calc_timings(struct gpmc_timings *gpmc_t, | 210 | extern int gpmc_calc_timings(struct gpmc_timings *gpmc_t, |
| 193 | struct gpmc_device_timings *dev_t); | 211 | struct gpmc_settings *gpmc_s, |
| 212 | struct gpmc_device_timings *dev_t); | ||
| 194 | 213 | ||
| 195 | extern void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs); | 214 | extern void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs); |
| 196 | extern int gpmc_get_client_irq(unsigned irq_config); | 215 | extern int gpmc_get_client_irq(unsigned irq_config); |
| 197 | 216 | ||
| 198 | extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns); | ||
| 199 | extern unsigned int gpmc_ps_to_ticks(unsigned int time_ps); | ||
| 200 | extern unsigned int gpmc_ticks_to_ns(unsigned int ticks); | 217 | extern unsigned int gpmc_ticks_to_ns(unsigned int ticks); |
| 201 | extern unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns); | ||
| 202 | extern unsigned long gpmc_get_fclk_period(void); | ||
| 203 | 218 | ||
| 204 | extern void gpmc_cs_write_reg(int cs, int idx, u32 val); | 219 | extern void gpmc_cs_write_reg(int cs, int idx, u32 val); |
| 205 | extern u32 gpmc_cs_read_reg(int cs, int idx); | ||
| 206 | extern int gpmc_calc_divider(unsigned int sync_clk); | 220 | extern int gpmc_calc_divider(unsigned int sync_clk); |
| 207 | extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t); | 221 | extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t); |
| 222 | extern int gpmc_cs_program_settings(int cs, struct gpmc_settings *p); | ||
| 208 | extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base); | 223 | extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base); |
| 209 | extern void gpmc_cs_free(int cs); | 224 | extern void gpmc_cs_free(int cs); |
| 210 | extern int gpmc_cs_set_reserved(int cs, int reserved); | ||
| 211 | extern int gpmc_cs_reserved(int cs); | ||
| 212 | extern void omap3_gpmc_save_context(void); | 225 | extern void omap3_gpmc_save_context(void); |
| 213 | extern void omap3_gpmc_restore_context(void); | 226 | extern void omap3_gpmc_restore_context(void); |
| 214 | extern int gpmc_cs_configure(int cs, int cmd, int wval); | 227 | extern int gpmc_configure(int cmd, int wval); |
| 228 | extern void gpmc_read_settings_dt(struct device_node *np, | ||
| 229 | struct gpmc_settings *p); | ||
| 215 | 230 | ||
| 216 | #endif | 231 | #endif |
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 2bef5a7e6af8..e210fa830f8d 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c | |||
| @@ -55,6 +55,12 @@ | |||
| 55 | #include "prm44xx.h" | 55 | #include "prm44xx.h" |
| 56 | 56 | ||
| 57 | /* | 57 | /* |
| 58 | * omap_clk_init: points to a function that does the SoC-specific | ||
| 59 | * clock initializations | ||
| 60 | */ | ||
| 61 | int (*omap_clk_init)(void); | ||
| 62 | |||
| 63 | /* | ||
| 58 | * The machine specific code may provide the extra mapping besides the | 64 | * The machine specific code may provide the extra mapping besides the |
| 59 | * default mapping provided here. | 65 | * default mapping provided here. |
| 60 | */ | 66 | */ |
| @@ -406,7 +412,7 @@ void __init omap2420_init_early(void) | |||
| 406 | omap242x_clockdomains_init(); | 412 | omap242x_clockdomains_init(); |
| 407 | omap2420_hwmod_init(); | 413 | omap2420_hwmod_init(); |
| 408 | omap_hwmod_init_postsetup(); | 414 | omap_hwmod_init_postsetup(); |
| 409 | omap2420_clk_init(); | 415 | omap_clk_init = omap2420_clk_init; |
| 410 | } | 416 | } |
| 411 | 417 | ||
| 412 | void __init omap2420_init_late(void) | 418 | void __init omap2420_init_late(void) |
| @@ -436,7 +442,7 @@ void __init omap2430_init_early(void) | |||
| 436 | omap243x_clockdomains_init(); | 442 | omap243x_clockdomains_init(); |
| 437 | omap2430_hwmod_init(); | 443 | omap2430_hwmod_init(); |
| 438 | omap_hwmod_init_postsetup(); | 444 | omap_hwmod_init_postsetup(); |
| 439 | omap2430_clk_init(); | 445 | omap_clk_init = omap2430_clk_init; |
| 440 | } | 446 | } |
| 441 | 447 | ||
| 442 | void __init omap2430_init_late(void) | 448 | void __init omap2430_init_late(void) |
| @@ -471,7 +477,7 @@ void __init omap3_init_early(void) | |||
| 471 | omap3xxx_clockdomains_init(); | 477 | omap3xxx_clockdomains_init(); |
| 472 | omap3xxx_hwmod_init(); | 478 | omap3xxx_hwmod_init(); |
| 473 | omap_hwmod_init_postsetup(); | 479 | omap_hwmod_init_postsetup(); |
| 474 | omap3xxx_clk_init(); | 480 | omap_clk_init = omap3xxx_clk_init; |
| 475 | } | 481 | } |
| 476 | 482 | ||
| 477 | void __init omap3430_init_early(void) | 483 | void __init omap3430_init_early(void) |
| @@ -509,7 +515,7 @@ void __init ti81xx_init_early(void) | |||
| 509 | omap3xxx_clockdomains_init(); | 515 | omap3xxx_clockdomains_init(); |
| 510 | omap3xxx_hwmod_init(); | 516 | omap3xxx_hwmod_init(); |
| 511 | omap_hwmod_init_postsetup(); | 517 | omap_hwmod_init_postsetup(); |
| 512 | omap3xxx_clk_init(); | 518 | omap_clk_init = omap3xxx_clk_init; |
| 513 | } | 519 | } |
| 514 | 520 | ||
| 515 | void __init omap3_init_late(void) | 521 | void __init omap3_init_late(void) |
| @@ -577,7 +583,7 @@ void __init am33xx_init_early(void) | |||
| 577 | am33xx_clockdomains_init(); | 583 | am33xx_clockdomains_init(); |
| 578 | am33xx_hwmod_init(); | 584 | am33xx_hwmod_init(); |
| 579 | omap_hwmod_init_postsetup(); | 585 | omap_hwmod_init_postsetup(); |
| 580 | am33xx_clk_init(); | 586 | omap_clk_init = am33xx_clk_init; |
| 581 | } | 587 | } |
| 582 | #endif | 588 | #endif |
| 583 | 589 | ||
| @@ -602,7 +608,7 @@ void __init omap4430_init_early(void) | |||
| 602 | omap44xx_clockdomains_init(); | 608 | omap44xx_clockdomains_init(); |
| 603 | omap44xx_hwmod_init(); | 609 | omap44xx_hwmod_init(); |
| 604 | omap_hwmod_init_postsetup(); | 610 | omap_hwmod_init_postsetup(); |
| 605 | omap4xxx_clk_init(); | 611 | omap_clk_init = omap4xxx_clk_init; |
| 606 | } | 612 | } |
| 607 | 613 | ||
| 608 | void __init omap4430_init_late(void) | 614 | void __init omap4430_init_late(void) |
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 2520d46c8508..3f50f680372e 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c | |||
| @@ -1364,7 +1364,9 @@ static void _enable_sysc(struct omap_hwmod *oh) | |||
| 1364 | } | 1364 | } |
| 1365 | 1365 | ||
| 1366 | if (sf & SYSC_HAS_MIDLEMODE) { | 1366 | if (sf & SYSC_HAS_MIDLEMODE) { |
| 1367 | if (oh->flags & HWMOD_SWSUP_MSTANDBY) { | 1367 | if (oh->flags & HWMOD_FORCE_MSTANDBY) { |
| 1368 | idlemode = HWMOD_IDLEMODE_FORCE; | ||
| 1369 | } else if (oh->flags & HWMOD_SWSUP_MSTANDBY) { | ||
| 1368 | idlemode = HWMOD_IDLEMODE_NO; | 1370 | idlemode = HWMOD_IDLEMODE_NO; |
| 1369 | } else { | 1371 | } else { |
| 1370 | if (sf & SYSC_HAS_ENAWAKEUP) | 1372 | if (sf & SYSC_HAS_ENAWAKEUP) |
| @@ -1436,7 +1438,8 @@ static void _idle_sysc(struct omap_hwmod *oh) | |||
| 1436 | } | 1438 | } |
| 1437 | 1439 | ||
| 1438 | if (sf & SYSC_HAS_MIDLEMODE) { | 1440 | if (sf & SYSC_HAS_MIDLEMODE) { |
| 1439 | if (oh->flags & HWMOD_SWSUP_MSTANDBY) { | 1441 | if ((oh->flags & HWMOD_SWSUP_MSTANDBY) || |
| 1442 | (oh->flags & HWMOD_FORCE_MSTANDBY)) { | ||
| 1440 | idlemode = HWMOD_IDLEMODE_FORCE; | 1443 | idlemode = HWMOD_IDLEMODE_FORCE; |
| 1441 | } else { | 1444 | } else { |
| 1442 | if (sf & SYSC_HAS_ENAWAKEUP) | 1445 | if (sf & SYSC_HAS_ENAWAKEUP) |
diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h index 28f4dea0512e..fe5962921f07 100644 --- a/arch/arm/mach-omap2/omap_hwmod.h +++ b/arch/arm/mach-omap2/omap_hwmod.h | |||
| @@ -427,8 +427,8 @@ struct omap_hwmod_omap4_prcm { | |||
| 427 | * | 427 | * |
| 428 | * HWMOD_SWSUP_SIDLE: omap_hwmod code should manually bring module in and out | 428 | * HWMOD_SWSUP_SIDLE: omap_hwmod code should manually bring module in and out |
| 429 | * of idle, rather than relying on module smart-idle | 429 | * of idle, rather than relying on module smart-idle |
| 430 | * HWMOD_SWSUP_MSTDBY: omap_hwmod code should manually bring module in and out | 430 | * HWMOD_SWSUP_MSTANDBY: omap_hwmod code should manually bring module in and |
| 431 | * of standby, rather than relying on module smart-standby | 431 | * out of standby, rather than relying on module smart-standby |
| 432 | * HWMOD_INIT_NO_RESET: don't reset this module at boot - important for | 432 | * HWMOD_INIT_NO_RESET: don't reset this module at boot - important for |
| 433 | * SDRAM controller, etc. XXX probably belongs outside the main hwmod file | 433 | * SDRAM controller, etc. XXX probably belongs outside the main hwmod file |
| 434 | * XXX Should be HWMOD_SETUP_NO_RESET | 434 | * XXX Should be HWMOD_SETUP_NO_RESET |
| @@ -459,6 +459,10 @@ struct omap_hwmod_omap4_prcm { | |||
| 459 | * correctly, or this is being abused to deal with some PM latency | 459 | * correctly, or this is being abused to deal with some PM latency |
| 460 | * issues -- but we're currently suffering from a shortage of | 460 | * issues -- but we're currently suffering from a shortage of |
| 461 | * folks who are able to track these issues down properly. | 461 | * folks who are able to track these issues down properly. |
| 462 | * HWMOD_FORCE_MSTANDBY: Always keep MIDLEMODE bits cleared so that device | ||
| 463 | * is kept in force-standby mode. Failing to do so causes PM problems | ||
| 464 | * with musb on OMAP3630 at least. Note that musb has a dedicated register | ||
| 465 | * to control MSTANDBY signal when MIDLEMODE is set to force-standby. | ||
| 462 | */ | 466 | */ |
| 463 | #define HWMOD_SWSUP_SIDLE (1 << 0) | 467 | #define HWMOD_SWSUP_SIDLE (1 << 0) |
| 464 | #define HWMOD_SWSUP_MSTANDBY (1 << 1) | 468 | #define HWMOD_SWSUP_MSTANDBY (1 << 1) |
| @@ -471,6 +475,7 @@ struct omap_hwmod_omap4_prcm { | |||
| 471 | #define HWMOD_16BIT_REG (1 << 8) | 475 | #define HWMOD_16BIT_REG (1 << 8) |
| 472 | #define HWMOD_EXT_OPT_MAIN_CLK (1 << 9) | 476 | #define HWMOD_EXT_OPT_MAIN_CLK (1 << 9) |
| 473 | #define HWMOD_BLOCK_WFI (1 << 10) | 477 | #define HWMOD_BLOCK_WFI (1 << 10) |
| 478 | #define HWMOD_FORCE_MSTANDBY (1 << 11) | ||
| 474 | 479 | ||
| 475 | /* | 480 | /* |
| 476 | * omap_hwmod._int_flags definitions | 481 | * omap_hwmod._int_flags definitions |
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index ac7e03ec952f..5112d04e7b79 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | |||
| @@ -1707,9 +1707,14 @@ static struct omap_hwmod omap3xxx_usbhsotg_hwmod = { | |||
| 1707 | * Erratum ID: i479 idle_req / idle_ack mechanism potentially | 1707 | * Erratum ID: i479 idle_req / idle_ack mechanism potentially |
| 1708 | * broken when autoidle is enabled | 1708 | * broken when autoidle is enabled |
| 1709 | * workaround is to disable the autoidle bit at module level. | 1709 | * workaround is to disable the autoidle bit at module level. |
| 1710 | * | ||
| 1711 | * Enabling the device in any other MIDLEMODE setting but force-idle | ||
| 1712 | * causes core_pwrdm not enter idle states at least on OMAP3630. | ||
| 1713 | * Note that musb has OTG_FORCESTDBY register that controls MSTANDBY | ||
| 1714 | * signal when MIDLEMODE is set to force-idle. | ||
| 1710 | */ | 1715 | */ |
| 1711 | .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE | 1716 | .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE |
| 1712 | | HWMOD_SWSUP_MSTANDBY, | 1717 | | HWMOD_FORCE_MSTANDBY, |
| 1713 | }; | 1718 | }; |
| 1714 | 1719 | ||
| 1715 | /* usb_otg_hs */ | 1720 | /* usb_otg_hs */ |
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 0e47d2e1687c..9e0576569e07 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c | |||
| @@ -2714,6 +2714,10 @@ static struct omap_ocp2scp_dev ocp2scp_dev_attr[] = { | |||
| 2714 | { } | 2714 | { } |
| 2715 | }; | 2715 | }; |
| 2716 | 2716 | ||
| 2717 | static struct omap_hwmod_opt_clk ocp2scp_usb_phy_opt_clks[] = { | ||
| 2718 | { .role = "48mhz", .clk = "ocp2scp_usb_phy_phy_48m" }, | ||
| 2719 | }; | ||
| 2720 | |||
| 2717 | /* ocp2scp_usb_phy */ | 2721 | /* ocp2scp_usb_phy */ |
| 2718 | static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = { | 2722 | static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = { |
| 2719 | .name = "ocp2scp_usb_phy", | 2723 | .name = "ocp2scp_usb_phy", |
| @@ -2728,6 +2732,8 @@ static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = { | |||
| 2728 | }, | 2732 | }, |
| 2729 | }, | 2733 | }, |
| 2730 | .dev_attr = ocp2scp_dev_attr, | 2734 | .dev_attr = ocp2scp_dev_attr, |
| 2735 | .opt_clks = ocp2scp_usb_phy_opt_clks, | ||
| 2736 | .opt_clks_cnt = ARRAY_SIZE(ocp2scp_usb_phy_opt_clks), | ||
| 2731 | }; | 2737 | }; |
| 2732 | 2738 | ||
| 2733 | /* | 2739 | /* |
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index 31ae76481737..fdf1c039062c 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c | |||
| @@ -46,7 +46,6 @@ | |||
| 46 | #include <asm/smp_twd.h> | 46 | #include <asm/smp_twd.h> |
| 47 | #include <asm/sched_clock.h> | 47 | #include <asm/sched_clock.h> |
| 48 | 48 | ||
| 49 | #include <asm/arch_timer.h> | ||
| 50 | #include "omap_hwmod.h" | 49 | #include "omap_hwmod.h" |
| 51 | #include "omap_device.h" | 50 | #include "omap_device.h" |
| 52 | #include <plat/counter-32k.h> | 51 | #include <plat/counter-32k.h> |
| @@ -626,14 +625,10 @@ void __init omap4_local_timer_init(void) | |||
| 626 | #ifdef CONFIG_SOC_OMAP5 | 625 | #ifdef CONFIG_SOC_OMAP5 |
| 627 | void __init omap5_realtime_timer_init(void) | 626 | void __init omap5_realtime_timer_init(void) |
| 628 | { | 627 | { |
| 629 | int err; | ||
| 630 | |||
| 631 | omap4_sync32k_timer_init(); | 628 | omap4_sync32k_timer_init(); |
| 632 | realtime_counter_init(); | 629 | realtime_counter_init(); |
| 633 | 630 | ||
| 634 | err = arch_timer_of_register(); | 631 | clocksource_of_init(); |
| 635 | if (err) | ||
| 636 | pr_err("%s: arch_timer_register failed %d\n", __func__, err); | ||
| 637 | } | 632 | } |
| 638 | #endif /* CONFIG_SOC_OMAP5 */ | 633 | #endif /* CONFIG_SOC_OMAP5 */ |
| 639 | 634 | ||
diff --git a/arch/arm/mach-omap2/usb-tusb6010.c b/arch/arm/mach-omap2/usb-tusb6010.c index c5a3c6f9504e..e832bc7b8e2d 100644 --- a/arch/arm/mach-omap2/usb-tusb6010.c +++ b/arch/arm/mach-omap2/usb-tusb6010.c | |||
| @@ -8,6 +8,7 @@ | |||
| 8 | * published by the Free Software Foundation. | 8 | * published by the Free Software Foundation. |
| 9 | */ | 9 | */ |
| 10 | 10 | ||
| 11 | #include <linux/err.h> | ||
| 11 | #include <linux/string.h> | 12 | #include <linux/string.h> |
| 12 | #include <linux/types.h> | 13 | #include <linux/types.h> |
| 13 | #include <linux/errno.h> | 14 | #include <linux/errno.h> |
| @@ -26,6 +27,24 @@ | |||
| 26 | static u8 async_cs, sync_cs; | 27 | static u8 async_cs, sync_cs; |
| 27 | static unsigned refclk_psec; | 28 | static unsigned refclk_psec; |
| 28 | 29 | ||
| 30 | static struct gpmc_settings tusb_async = { | ||
| 31 | .wait_on_read = true, | ||
| 32 | .wait_on_write = true, | ||
| 33 | .device_width = GPMC_DEVWIDTH_16BIT, | ||
| 34 | .mux_add_data = GPMC_MUX_AD, | ||
| 35 | }; | ||
| 36 | |||
| 37 | static struct gpmc_settings tusb_sync = { | ||
| 38 | .burst_read = true, | ||
| 39 | .burst_write = true, | ||
| 40 | .sync_read = true, | ||
| 41 | .sync_write = true, | ||
| 42 | .wait_on_read = true, | ||
| 43 | .wait_on_write = true, | ||
| 44 | .burst_len = GPMC_BURST_16, | ||
| 45 | .device_width = GPMC_DEVWIDTH_16BIT, | ||
| 46 | .mux_add_data = GPMC_MUX_AD, | ||
| 47 | }; | ||
| 29 | 48 | ||
| 30 | /* NOTE: timings are from tusb 6010 datasheet Rev 1.8, 12-Sept 2006 */ | 49 | /* NOTE: timings are from tusb 6010 datasheet Rev 1.8, 12-Sept 2006 */ |
| 31 | 50 | ||
| @@ -37,8 +56,6 @@ static int tusb_set_async_mode(unsigned sysclk_ps) | |||
| 37 | 56 | ||
| 38 | memset(&dev_t, 0, sizeof(dev_t)); | 57 | memset(&dev_t, 0, sizeof(dev_t)); |
| 39 | 58 | ||
| 40 | dev_t.mux = true; | ||
| 41 | |||
| 42 | dev_t.t_ceasu = 8 * 1000; | 59 | dev_t.t_ceasu = 8 * 1000; |
| 43 | dev_t.t_avdasu = t_acsnh_advnh - 7000; | 60 | dev_t.t_avdasu = t_acsnh_advnh - 7000; |
| 44 | dev_t.t_ce_avd = 1000; | 61 | dev_t.t_ce_avd = 1000; |
| @@ -52,7 +69,7 @@ static int tusb_set_async_mode(unsigned sysclk_ps) | |||
| 52 | dev_t.t_wpl = 300; | 69 | dev_t.t_wpl = 300; |
| 53 | dev_t.cyc_aavdh_we = 1; | 70 | dev_t.cyc_aavdh_we = 1; |
| 54 | 71 | ||
| 55 | gpmc_calc_timings(&t, &dev_t); | 72 | gpmc_calc_timings(&t, &tusb_async, &dev_t); |
| 56 | 73 | ||
| 57 | return gpmc_cs_set_timings(async_cs, &t); | 74 | return gpmc_cs_set_timings(async_cs, &t); |
| 58 | } | 75 | } |
| @@ -65,10 +82,6 @@ static int tusb_set_sync_mode(unsigned sysclk_ps) | |||
| 65 | 82 | ||
| 66 | memset(&dev_t, 0, sizeof(dev_t)); | 83 | memset(&dev_t, 0, sizeof(dev_t)); |
| 67 | 84 | ||
| 68 | dev_t.mux = true; | ||
| 69 | dev_t.sync_read = true; | ||
| 70 | dev_t.sync_write = true; | ||
| 71 | |||
| 72 | dev_t.clk = 11100; | 85 | dev_t.clk = 11100; |
| 73 | dev_t.t_bacc = 1000; | 86 | dev_t.t_bacc = 1000; |
| 74 | dev_t.t_ces = 1000; | 87 | dev_t.t_ces = 1000; |
| @@ -84,7 +97,7 @@ static int tusb_set_sync_mode(unsigned sysclk_ps) | |||
| 84 | dev_t.cyc_wpl = 6; | 97 | dev_t.cyc_wpl = 6; |
| 85 | dev_t.t_ce_rdyz = 7000; | 98 | dev_t.t_ce_rdyz = 7000; |
| 86 | 99 | ||
| 87 | gpmc_calc_timings(&t, &dev_t); | 100 | gpmc_calc_timings(&t, &tusb_sync, &dev_t); |
| 88 | 101 | ||
| 89 | return gpmc_cs_set_timings(sync_cs, &t); | 102 | return gpmc_cs_set_timings(sync_cs, &t); |
| 90 | } | 103 | } |
| @@ -165,18 +178,12 @@ tusb6010_setup_interface(struct musb_hdrc_platform_data *data, | |||
| 165 | return status; | 178 | return status; |
| 166 | } | 179 | } |
| 167 | tusb_resources[0].end = tusb_resources[0].start + 0x9ff; | 180 | tusb_resources[0].end = tusb_resources[0].start + 0x9ff; |
| 181 | tusb_async.wait_pin = waitpin; | ||
| 168 | async_cs = async; | 182 | async_cs = async; |
| 169 | gpmc_cs_write_reg(async, GPMC_CS_CONFIG1, | ||
| 170 | GPMC_CONFIG1_PAGE_LEN(2) | ||
| 171 | | GPMC_CONFIG1_WAIT_READ_MON | ||
| 172 | | GPMC_CONFIG1_WAIT_WRITE_MON | ||
| 173 | | GPMC_CONFIG1_WAIT_PIN_SEL(waitpin) | ||
| 174 | | GPMC_CONFIG1_READTYPE_ASYNC | ||
| 175 | | GPMC_CONFIG1_WRITETYPE_ASYNC | ||
| 176 | | GPMC_CONFIG1_DEVICESIZE_16 | ||
| 177 | | GPMC_CONFIG1_DEVICETYPE_NOR | ||
| 178 | | GPMC_CONFIG1_MUXADDDATA); | ||
| 179 | 183 | ||
| 184 | status = gpmc_cs_program_settings(async_cs, &tusb_async); | ||
| 185 | if (status < 0) | ||
| 186 | return status; | ||
| 180 | 187 | ||
| 181 | /* SYNC region, primarily for DMA */ | 188 | /* SYNC region, primarily for DMA */ |
| 182 | status = gpmc_cs_request(sync, SZ_16M, (unsigned long *) | 189 | status = gpmc_cs_request(sync, SZ_16M, (unsigned long *) |
| @@ -186,21 +193,12 @@ tusb6010_setup_interface(struct musb_hdrc_platform_data *data, | |||
| 186 | return status; | 193 | return status; |
| 187 | } | 194 | } |
| 188 | tusb_resources[1].end = tusb_resources[1].start + 0x9ff; | 195 | tusb_resources[1].end = tusb_resources[1].start + 0x9ff; |
| 196 | tusb_sync.wait_pin = waitpin; | ||
| 189 | sync_cs = sync; | 197 | sync_cs = sync; |
| 190 | gpmc_cs_write_reg(sync, GPMC_CS_CONFIG1, | 198 | |
| 191 | GPMC_CONFIG1_READMULTIPLE_SUPP | 199 | status = gpmc_cs_program_settings(sync_cs, &tusb_sync); |
| 192 | | GPMC_CONFIG1_READTYPE_SYNC | 200 | if (status < 0) |
| 193 | | GPMC_CONFIG1_WRITEMULTIPLE_SUPP | 201 | return status; |
| 194 | | GPMC_CONFIG1_WRITETYPE_SYNC | ||
| 195 | | GPMC_CONFIG1_PAGE_LEN(2) | ||
| 196 | | GPMC_CONFIG1_WAIT_READ_MON | ||
| 197 | | GPMC_CONFIG1_WAIT_WRITE_MON | ||
| 198 | | GPMC_CONFIG1_WAIT_PIN_SEL(waitpin) | ||
| 199 | | GPMC_CONFIG1_DEVICESIZE_16 | ||
| 200 | | GPMC_CONFIG1_DEVICETYPE_NOR | ||
| 201 | | GPMC_CONFIG1_MUXADDDATA | ||
| 202 | /* fclk divider gets set later */ | ||
| 203 | ); | ||
| 204 | 202 | ||
| 205 | /* IRQ */ | 203 | /* IRQ */ |
| 206 | status = gpio_request_one(irq, GPIOF_IN, "TUSB6010 irq"); | 204 | status = gpio_request_one(irq, GPIOF_IN, "TUSB6010 irq"); |
diff --git a/arch/arm/mach-s3c24xx/Makefile b/arch/arm/mach-s3c24xx/Makefile index be6e4d0e6f1a..6f46ecfc8396 100644 --- a/arch/arm/mach-s3c24xx/Makefile +++ b/arch/arm/mach-s3c24xx/Makefile | |||
| @@ -14,7 +14,7 @@ obj- := | |||
| 14 | 14 | ||
| 15 | # core | 15 | # core |
| 16 | 16 | ||
| 17 | obj-y += common.o irq.o | 17 | obj-y += common.o |
| 18 | 18 | ||
| 19 | obj-$(CONFIG_CPU_S3C2410) += s3c2410.o | 19 | obj-$(CONFIG_CPU_S3C2410) += s3c2410.o |
| 20 | obj-$(CONFIG_S3C2410_CPUFREQ) += cpufreq-s3c2410.o | 20 | obj-$(CONFIG_S3C2410_CPUFREQ) += cpufreq-s3c2410.o |
diff --git a/arch/arm/mach-s3c24xx/common.h b/arch/arm/mach-s3c24xx/common.h index abefeb38bba4..307c3714be55 100644 --- a/arch/arm/mach-s3c24xx/common.h +++ b/arch/arm/mach-s3c24xx/common.h | |||
| @@ -21,6 +21,7 @@ extern void s3c2410_map_io(void); | |||
| 21 | extern void s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no); | 21 | extern void s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no); |
| 22 | extern void s3c2410_init_clocks(int xtal); | 22 | extern void s3c2410_init_clocks(int xtal); |
| 23 | extern void s3c2410_restart(char mode, const char *cmd); | 23 | extern void s3c2410_restart(char mode, const char *cmd); |
| 24 | extern void s3c2410_init_irq(void); | ||
| 24 | #else | 25 | #else |
| 25 | #define s3c2410_init_clocks NULL | 26 | #define s3c2410_init_clocks NULL |
| 26 | #define s3c2410_init_uarts NULL | 27 | #define s3c2410_init_uarts NULL |
diff --git a/arch/arm/mach-s3c24xx/include/mach/entry-macro.S b/arch/arm/mach-s3c24xx/include/mach/entry-macro.S deleted file mode 100644 index 6a21beeba1da..000000000000 --- a/arch/arm/mach-s3c24xx/include/mach/entry-macro.S +++ /dev/null | |||
| @@ -1,70 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-s3c2410/include/mach/entry-macro.S | ||
| 3 | * | ||
| 4 | * Low-level IRQ helper macros for S3C2410-based platforms | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | |||
| 11 | /* We have a problem that the INTOFFSET register does not always | ||
| 12 | * show one interrupt. Occasionally we get two interrupts through | ||
| 13 | * the prioritiser, and this causes the INTOFFSET register to show | ||
| 14 | * what looks like the logical-or of the two interrupt numbers. | ||
| 15 | * | ||
| 16 | * Thanks to Klaus, Shannon, et al for helping to debug this problem | ||
| 17 | */ | ||
| 18 | |||
| 19 | #define INTPND (0x10) | ||
| 20 | #define INTOFFSET (0x14) | ||
| 21 | |||
| 22 | #include <mach/hardware.h> | ||
| 23 | #include <asm/irq.h> | ||
| 24 | |||
| 25 | .macro get_irqnr_preamble, base, tmp | ||
| 26 | .endm | ||
| 27 | |||
| 28 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
| 29 | |||
| 30 | mov \base, #S3C24XX_VA_IRQ | ||
| 31 | |||
| 32 | @@ try the interrupt offset register, since it is there | ||
| 33 | |||
| 34 | ldr \irqstat, [\base, #INTPND ] | ||
| 35 | teq \irqstat, #0 | ||
| 36 | beq 1002f | ||
| 37 | ldr \irqnr, [\base, #INTOFFSET ] | ||
| 38 | mov \tmp, #1 | ||
| 39 | tst \irqstat, \tmp, lsl \irqnr | ||
| 40 | bne 1001f | ||
| 41 | |||
| 42 | @@ the number specified is not a valid irq, so try | ||
| 43 | @@ and work it out for ourselves | ||
| 44 | |||
| 45 | mov \irqnr, #0 @@ start here | ||
| 46 | |||
| 47 | @@ work out which irq (if any) we got | ||
| 48 | |||
| 49 | movs \tmp, \irqstat, lsl#16 | ||
| 50 | addeq \irqnr, \irqnr, #16 | ||
| 51 | moveq \irqstat, \irqstat, lsr#16 | ||
| 52 | tst \irqstat, #0xff | ||
| 53 | addeq \irqnr, \irqnr, #8 | ||
| 54 | moveq \irqstat, \irqstat, lsr#8 | ||
| 55 | tst \irqstat, #0xf | ||
| 56 | addeq \irqnr, \irqnr, #4 | ||
| 57 | moveq \irqstat, \irqstat, lsr#4 | ||
| 58 | tst \irqstat, #0x3 | ||
| 59 | addeq \irqnr, \irqnr, #2 | ||
| 60 | moveq \irqstat, \irqstat, lsr#2 | ||
| 61 | tst \irqstat, #0x1 | ||
| 62 | addeq \irqnr, \irqnr, #1 | ||
| 63 | |||
| 64 | @@ we have the value | ||
| 65 | 1001: | ||
| 66 | adds \irqnr, \irqnr, #IRQ_EINT0 | ||
| 67 | 1002: | ||
| 68 | @@ exit here, Z flag unset if IRQ | ||
| 69 | |||
| 70 | .endm | ||
diff --git a/arch/arm/mach-s3c24xx/irq.c b/arch/arm/mach-s3c24xx/irq.c deleted file mode 100644 index 3f3de7492094..000000000000 --- a/arch/arm/mach-s3c24xx/irq.c +++ /dev/null | |||
| @@ -1,1068 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * S3C24XX IRQ handling | ||
| 3 | * | ||
| 4 | * Copyright (c) 2003-2004 Simtec Electronics | ||
| 5 | * Ben Dooks <ben@simtec.co.uk> | ||
| 6 | * Copyright (c) 2012 Heiko Stuebner <heiko@sntech.de> | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License as published by | ||
| 10 | * the Free Software Foundation; either version 2 of the License, or | ||
| 11 | * (at your option) any later version. | ||
| 12 | * | ||
| 13 | * This program is distributed in the hope that it will be useful, | ||
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 16 | * GNU General Public License for more details. | ||
| 17 | */ | ||
| 18 | |||
| 19 | #include <linux/init.h> | ||
| 20 | #include <linux/slab.h> | ||
| 21 | #include <linux/module.h> | ||
| 22 | #include <linux/io.h> | ||
| 23 | #include <linux/err.h> | ||
| 24 | #include <linux/interrupt.h> | ||
| 25 | #include <linux/ioport.h> | ||
| 26 | #include <linux/device.h> | ||
| 27 | #include <linux/irqdomain.h> | ||
| 28 | |||
| 29 | #include <asm/mach/irq.h> | ||
| 30 | |||
| 31 | #include <mach/regs-irq.h> | ||
| 32 | #include <mach/regs-gpio.h> | ||
| 33 | |||
| 34 | #include <plat/cpu.h> | ||
| 35 | #include <plat/regs-irqtype.h> | ||
| 36 | #include <plat/pm.h> | ||
| 37 | |||
| 38 | #define S3C_IRQTYPE_NONE 0 | ||
| 39 | #define S3C_IRQTYPE_EINT 1 | ||
| 40 | #define S3C_IRQTYPE_EDGE 2 | ||
| 41 | #define S3C_IRQTYPE_LEVEL 3 | ||
| 42 | |||
| 43 | struct s3c_irq_data { | ||
| 44 | unsigned int type; | ||
| 45 | unsigned long parent_irq; | ||
| 46 | |||
| 47 | /* data gets filled during init */ | ||
| 48 | struct s3c_irq_intc *intc; | ||
| 49 | unsigned long sub_bits; | ||
| 50 | struct s3c_irq_intc *sub_intc; | ||
| 51 | }; | ||
| 52 | |||
| 53 | /* | ||
| 54 | * Sructure holding the controller data | ||
| 55 | * @reg_pending register holding pending irqs | ||
| 56 | * @reg_intpnd special register intpnd in main intc | ||
| 57 | * @reg_mask mask register | ||
| 58 | * @domain irq_domain of the controller | ||
| 59 | * @parent parent controller for ext and sub irqs | ||
| 60 | * @irqs irq-data, always s3c_irq_data[32] | ||
| 61 | */ | ||
| 62 | struct s3c_irq_intc { | ||
| 63 | void __iomem *reg_pending; | ||
| 64 | void __iomem *reg_intpnd; | ||
| 65 | void __iomem *reg_mask; | ||
| 66 | struct irq_domain *domain; | ||
| 67 | struct s3c_irq_intc *parent; | ||
| 68 | struct s3c_irq_data *irqs; | ||
| 69 | }; | ||
| 70 | |||
| 71 | static void s3c_irq_mask(struct irq_data *data) | ||
| 72 | { | ||
| 73 | struct s3c_irq_intc *intc = data->domain->host_data; | ||
| 74 | struct s3c_irq_intc *parent_intc = intc->parent; | ||
| 75 | struct s3c_irq_data *irq_data = &intc->irqs[data->hwirq]; | ||
| 76 | struct s3c_irq_data *parent_data; | ||
| 77 | unsigned long mask; | ||
| 78 | unsigned int irqno; | ||
| 79 | |||
| 80 | mask = __raw_readl(intc->reg_mask); | ||
| 81 | mask |= (1UL << data->hwirq); | ||
| 82 | __raw_writel(mask, intc->reg_mask); | ||
| 83 | |||
| 84 | if (parent_intc && irq_data->parent_irq) { | ||
| 85 | parent_data = &parent_intc->irqs[irq_data->parent_irq]; | ||
| 86 | |||
| 87 | /* check to see if we need to mask the parent IRQ */ | ||
| 88 | if ((mask & parent_data->sub_bits) == parent_data->sub_bits) { | ||
| 89 | irqno = irq_find_mapping(parent_intc->domain, | ||
| 90 | irq_data->parent_irq); | ||
| 91 | s3c_irq_mask(irq_get_irq_data(irqno)); | ||
| 92 | } | ||
| 93 | } | ||
| 94 | } | ||
| 95 | |||
| 96 | static void s3c_irq_unmask(struct irq_data *data) | ||
| 97 | { | ||
| 98 | struct s3c_irq_intc *intc = data->domain->host_data; | ||
| 99 | struct s3c_irq_intc *parent_intc = intc->parent; | ||
| 100 | struct s3c_irq_data *irq_data = &intc->irqs[data->hwirq]; | ||
| 101 | unsigned long mask; | ||
| 102 | unsigned int irqno; | ||
| 103 | |||
| 104 | mask = __raw_readl(intc->reg_mask); | ||
| 105 | mask &= ~(1UL << data->hwirq); | ||
| 106 | __raw_writel(mask, intc->reg_mask); | ||
| 107 | |||
| 108 | if (parent_intc && irq_data->parent_irq) { | ||
| 109 | irqno = irq_find_mapping(parent_intc->domain, | ||
| 110 | irq_data->parent_irq); | ||
| 111 | s3c_irq_unmask(irq_get_irq_data(irqno)); | ||
| 112 | } | ||
| 113 | } | ||
| 114 | |||
| 115 | static inline void s3c_irq_ack(struct irq_data *data) | ||
| 116 | { | ||
| 117 | struct s3c_irq_intc *intc = data->domain->host_data; | ||
| 118 | unsigned long bitval = 1UL << data->hwirq; | ||
| 119 | |||
| 120 | __raw_writel(bitval, intc->reg_pending); | ||
| 121 | if (intc->reg_intpnd) | ||
| 122 | __raw_writel(bitval, intc->reg_intpnd); | ||
| 123 | } | ||
| 124 | |||
| 125 | static int s3c_irqext_type_set(void __iomem *gpcon_reg, | ||
| 126 | void __iomem *extint_reg, | ||
| 127 | unsigned long gpcon_offset, | ||
| 128 | unsigned long extint_offset, | ||
| 129 | unsigned int type) | ||
| 130 | { | ||
| 131 | unsigned long newvalue = 0, value; | ||
| 132 | |||
| 133 | /* Set the GPIO to external interrupt mode */ | ||
| 134 | value = __raw_readl(gpcon_reg); | ||
| 135 | value = (value & ~(3 << gpcon_offset)) | (0x02 << gpcon_offset); | ||
| 136 | __raw_writel(value, gpcon_reg); | ||
| 137 | |||
| 138 | /* Set the external interrupt to pointed trigger type */ | ||
| 139 | switch (type) | ||
| 140 | { | ||
| 141 | case IRQ_TYPE_NONE: | ||
| 142 | pr_warn("No edge setting!\n"); | ||
| 143 | break; | ||
| 144 | |||
| 145 | case IRQ_TYPE_EDGE_RISING: | ||
| 146 | newvalue = S3C2410_EXTINT_RISEEDGE; | ||
| 147 | break; | ||
| 148 | |||
| 149 | case IRQ_TYPE_EDGE_FALLING: | ||
| 150 | newvalue = S3C2410_EXTINT_FALLEDGE; | ||
| 151 | break; | ||
| 152 | |||
| 153 | case IRQ_TYPE_EDGE_BOTH: | ||
| 154 | newvalue = S3C2410_EXTINT_BOTHEDGE; | ||
| 155 | break; | ||
| 156 | |||
| 157 | case IRQ_TYPE_LEVEL_LOW: | ||
| 158 | newvalue = S3C2410_EXTINT_LOWLEV; | ||
| 159 | break; | ||
| 160 | |||
| 161 | case IRQ_TYPE_LEVEL_HIGH: | ||
| 162 | newvalue = S3C2410_EXTINT_HILEV; | ||
| 163 | break; | ||
| 164 | |||
| 165 | default: | ||
| 166 | pr_err("No such irq type %d", type); | ||
| 167 | return -EINVAL; | ||
| 168 | } | ||
| 169 | |||
| 170 | value = __raw_readl(extint_reg); | ||
| 171 | value = (value & ~(7 << extint_offset)) | (newvalue << extint_offset); | ||
| 172 | __raw_writel(value, extint_reg); | ||
| 173 | |||
| 174 | return 0; | ||
| 175 | } | ||
| 176 | |||
| 177 | static int s3c_irqext_type(struct irq_data *data, unsigned int type) | ||
| 178 | { | ||
| 179 | void __iomem *extint_reg; | ||
| 180 | void __iomem *gpcon_reg; | ||
| 181 | unsigned long gpcon_offset, extint_offset; | ||
| 182 | |||
| 183 | if ((data->hwirq >= 4) && (data->hwirq <= 7)) { | ||
| 184 | gpcon_reg = S3C2410_GPFCON; | ||
| 185 | extint_reg = S3C24XX_EXTINT0; | ||
| 186 | gpcon_offset = (data->hwirq) * 2; | ||
| 187 | extint_offset = (data->hwirq) * 4; | ||
| 188 | } else if ((data->hwirq >= 8) && (data->hwirq <= 15)) { | ||
| 189 | gpcon_reg = S3C2410_GPGCON; | ||
| 190 | extint_reg = S3C24XX_EXTINT1; | ||
| 191 | gpcon_offset = (data->hwirq - 8) * 2; | ||
| 192 | extint_offset = (data->hwirq - 8) * 4; | ||
| 193 | } else if ((data->hwirq >= 16) && (data->hwirq <= 23)) { | ||
| 194 | gpcon_reg = S3C2410_GPGCON; | ||
| 195 | extint_reg = S3C24XX_EXTINT2; | ||
| 196 | gpcon_offset = (data->hwirq - 8) * 2; | ||
| 197 | extint_offset = (data->hwirq - 16) * 4; | ||
| 198 | } else { | ||
| 199 | return -EINVAL; | ||
| 200 | } | ||
| 201 | |||
| 202 | return s3c_irqext_type_set(gpcon_reg, extint_reg, gpcon_offset, | ||
| 203 | extint_offset, type); | ||
| 204 | } | ||
| 205 | |||
| 206 | static int s3c_irqext0_type(struct irq_data *data, unsigned int type) | ||
| 207 | { | ||
| 208 | void __iomem *extint_reg; | ||
| 209 | void __iomem *gpcon_reg; | ||
| 210 | unsigned long gpcon_offset, extint_offset; | ||
| 211 | |||
| 212 | if ((data->hwirq >= 0) && (data->hwirq <= 3)) { | ||
| 213 | gpcon_reg = S3C2410_GPFCON; | ||
| 214 | extint_reg = S3C24XX_EXTINT0; | ||
| 215 | gpcon_offset = (data->hwirq) * 2; | ||
| 216 | extint_offset = (data->hwirq) * 4; | ||
| 217 | } else { | ||
| 218 | return -EINVAL; | ||
| 219 | } | ||
| 220 | |||
| 221 | return s3c_irqext_type_set(gpcon_reg, extint_reg, gpcon_offset, | ||
| 222 | extint_offset, type); | ||
| 223 | } | ||
| 224 | |||
| 225 | static struct irq_chip s3c_irq_chip = { | ||
| 226 | .name = "s3c", | ||
| 227 | .irq_ack = s3c_irq_ack, | ||
| 228 | .irq_mask = s3c_irq_mask, | ||
| 229 | .irq_unmask = s3c_irq_unmask, | ||
| 230 | .irq_set_wake = s3c_irq_wake | ||
| 231 | }; | ||
| 232 | |||
| 233 | static struct irq_chip s3c_irq_level_chip = { | ||
| 234 | .name = "s3c-level", | ||
| 235 | .irq_mask = s3c_irq_mask, | ||
| 236 | .irq_unmask = s3c_irq_unmask, | ||
| 237 | .irq_ack = s3c_irq_ack, | ||
| 238 | }; | ||
| 239 | |||
| 240 | static struct irq_chip s3c_irqext_chip = { | ||
| 241 | .name = "s3c-ext", | ||
| 242 | .irq_mask = s3c_irq_mask, | ||
| 243 | .irq_unmask = s3c_irq_unmask, | ||
| 244 | .irq_ack = s3c_irq_ack, | ||
| 245 | .irq_set_type = s3c_irqext_type, | ||
| 246 | .irq_set_wake = s3c_irqext_wake | ||
| 247 | }; | ||
| 248 | |||
| 249 | static struct irq_chip s3c_irq_eint0t4 = { | ||
| 250 | .name = "s3c-ext0", | ||
| 251 | .irq_ack = s3c_irq_ack, | ||
| 252 | .irq_mask = s3c_irq_mask, | ||
| 253 | .irq_unmask = s3c_irq_unmask, | ||
| 254 | .irq_set_wake = s3c_irq_wake, | ||
| 255 | .irq_set_type = s3c_irqext0_type, | ||
| 256 | }; | ||
| 257 | |||
| 258 | static void s3c_irq_demux(unsigned int irq, struct irq_desc *desc) | ||
| 259 | { | ||
| 260 | struct irq_chip *chip = irq_desc_get_chip(desc); | ||
| 261 | struct s3c_irq_intc *intc = desc->irq_data.domain->host_data; | ||
| 262 | struct s3c_irq_data *irq_data = &intc->irqs[desc->irq_data.hwirq]; | ||
| 263 | struct s3c_irq_intc *sub_intc = irq_data->sub_intc; | ||
| 264 | unsigned long src; | ||
| 265 | unsigned long msk; | ||
| 266 | unsigned int n; | ||
| 267 | |||
| 268 | chained_irq_enter(chip, desc); | ||
| 269 | |||
| 270 | src = __raw_readl(sub_intc->reg_pending); | ||
| 271 | msk = __raw_readl(sub_intc->reg_mask); | ||
| 272 | |||
| 273 | src &= ~msk; | ||
| 274 | src &= irq_data->sub_bits; | ||
| 275 | |||
| 276 | while (src) { | ||
| 277 | n = __ffs(src); | ||
| 278 | src &= ~(1 << n); | ||
| 279 | generic_handle_irq(irq_find_mapping(sub_intc->domain, n)); | ||
| 280 | } | ||
| 281 | |||
| 282 | chained_irq_exit(chip, desc); | ||
| 283 | } | ||
| 284 | |||
| 285 | #ifdef CONFIG_FIQ | ||
| 286 | /** | ||
| 287 | * s3c24xx_set_fiq - set the FIQ routing | ||
| 288 | * @irq: IRQ number to route to FIQ on processor. | ||
| 289 | * @on: Whether to route @irq to the FIQ, or to remove the FIQ routing. | ||
| 290 | * | ||
| 291 | * Change the state of the IRQ to FIQ routing depending on @irq and @on. If | ||
| 292 | * @on is true, the @irq is checked to see if it can be routed and the | ||
| 293 | * interrupt controller updated to route the IRQ. If @on is false, the FIQ | ||
| 294 | * routing is cleared, regardless of which @irq is specified. | ||
| 295 | */ | ||
| 296 | int s3c24xx_set_fiq(unsigned int irq, bool on) | ||
| 297 | { | ||
| 298 | u32 intmod; | ||
| 299 | unsigned offs; | ||
| 300 | |||
| 301 | if (on) { | ||
| 302 | offs = irq - FIQ_START; | ||
| 303 | if (offs > 31) | ||
| 304 | return -EINVAL; | ||
| 305 | |||
| 306 | intmod = 1 << offs; | ||
| 307 | } else { | ||
| 308 | intmod = 0; | ||
| 309 | } | ||
| 310 | |||
| 311 | __raw_writel(intmod, S3C2410_INTMOD); | ||
| 312 | return 0; | ||
| 313 | } | ||
| 314 | |||
| 315 | EXPORT_SYMBOL_GPL(s3c24xx_set_fiq); | ||
| 316 | #endif | ||
| 317 | |||
| 318 | static int s3c24xx_irq_map(struct irq_domain *h, unsigned int virq, | ||
| 319 | irq_hw_number_t hw) | ||
| 320 | { | ||
| 321 | struct s3c_irq_intc *intc = h->host_data; | ||
| 322 | struct s3c_irq_data *irq_data = &intc->irqs[hw]; | ||
| 323 | struct s3c_irq_intc *parent_intc; | ||
| 324 | struct s3c_irq_data *parent_irq_data; | ||
| 325 | unsigned int irqno; | ||
| 326 | |||
| 327 | if (!intc) { | ||
| 328 | pr_err("irq-s3c24xx: no controller found for hwirq %lu\n", hw); | ||
| 329 | return -EINVAL; | ||
| 330 | } | ||
| 331 | |||
| 332 | if (!irq_data) { | ||
| 333 | pr_err("irq-s3c24xx: no irq data found for hwirq %lu\n", hw); | ||
| 334 | return -EINVAL; | ||
| 335 | } | ||
| 336 | |||
| 337 | /* attach controller pointer to irq_data */ | ||
| 338 | irq_data->intc = intc; | ||
| 339 | |||
| 340 | /* set handler and flags */ | ||
| 341 | switch (irq_data->type) { | ||
| 342 | case S3C_IRQTYPE_NONE: | ||
| 343 | return 0; | ||
| 344 | case S3C_IRQTYPE_EINT: | ||
| 345 | /* On the S3C2412, the EINT0to3 have a parent irq | ||
| 346 | * but need the s3c_irq_eint0t4 chip | ||
| 347 | */ | ||
| 348 | if (irq_data->parent_irq && (!soc_is_s3c2412() || hw >= 4)) | ||
| 349 | irq_set_chip_and_handler(virq, &s3c_irqext_chip, | ||
| 350 | handle_edge_irq); | ||
| 351 | else | ||
| 352 | irq_set_chip_and_handler(virq, &s3c_irq_eint0t4, | ||
| 353 | handle_edge_irq); | ||
| 354 | break; | ||
| 355 | case S3C_IRQTYPE_EDGE: | ||
| 356 | if (irq_data->parent_irq || | ||
| 357 | intc->reg_pending == S3C2416_SRCPND2) | ||
| 358 | irq_set_chip_and_handler(virq, &s3c_irq_level_chip, | ||
| 359 | handle_edge_irq); | ||
| 360 | else | ||
| 361 | irq_set_chip_and_handler(virq, &s3c_irq_chip, | ||
| 362 | handle_edge_irq); | ||
| 363 | break; | ||
| 364 | case S3C_IRQTYPE_LEVEL: | ||
| 365 | if (irq_data->parent_irq) | ||
| 366 | irq_set_chip_and_handler(virq, &s3c_irq_level_chip, | ||
| 367 | handle_level_irq); | ||
| 368 | else | ||
| 369 | irq_set_chip_and_handler(virq, &s3c_irq_chip, | ||
| 370 | handle_level_irq); | ||
| 371 | break; | ||
| 372 | default: | ||
| 373 | pr_err("irq-s3c24xx: unsupported irqtype %d\n", irq_data->type); | ||
| 374 | return -EINVAL; | ||
| 375 | } | ||
| 376 | set_irq_flags(virq, IRQF_VALID); | ||
| 377 | |||
| 378 | if (irq_data->parent_irq) { | ||
| 379 | parent_intc = intc->parent; | ||
| 380 | if (!parent_intc) { | ||
| 381 | pr_err("irq-s3c24xx: no parent controller found for hwirq %lu\n", | ||
| 382 | hw); | ||
| 383 | goto err; | ||
| 384 | } | ||
| 385 | |||
| 386 | parent_irq_data = &parent_intc->irqs[irq_data->parent_irq]; | ||
| 387 | if (!irq_data) { | ||
| 388 | pr_err("irq-s3c24xx: no irq data found for hwirq %lu\n", | ||
| 389 | hw); | ||
| 390 | goto err; | ||
| 391 | } | ||
| 392 | |||
| 393 | parent_irq_data->sub_intc = intc; | ||
| 394 | parent_irq_data->sub_bits |= (1UL << hw); | ||
| 395 | |||
| 396 | /* attach the demuxer to the parent irq */ | ||
| 397 | irqno = irq_find_mapping(parent_intc->domain, | ||
| 398 | irq_data->parent_irq); | ||
| 399 | if (!irqno) { | ||
| 400 | pr_err("irq-s3c24xx: could not find mapping for parent irq %lu\n", | ||
| 401 | irq_data->parent_irq); | ||
| 402 | goto err; | ||
| 403 | } | ||
| 404 | irq_set_chained_handler(irqno, s3c_irq_demux); | ||
| 405 | } | ||
| 406 | |||
| 407 | return 0; | ||
| 408 | |||
| 409 | err: | ||
| 410 | set_irq_flags(virq, 0); | ||
| 411 | |||
| 412 | /* the only error can result from bad mapping data*/ | ||
| 413 | return -EINVAL; | ||
| 414 | } | ||
| 415 | |||
| 416 | static struct irq_domain_ops s3c24xx_irq_ops = { | ||
| 417 | .map = s3c24xx_irq_map, | ||
| 418 | .xlate = irq_domain_xlate_twocell, | ||
| 419 | }; | ||
| 420 | |||
| 421 | static void s3c24xx_clear_intc(struct s3c_irq_intc *intc) | ||
| 422 | { | ||
| 423 | void __iomem *reg_source; | ||
| 424 | unsigned long pend; | ||
| 425 | unsigned long last; | ||
| 426 | int i; | ||
| 427 | |||
| 428 | /* if intpnd is set, read the next pending irq from there */ | ||
| 429 | reg_source = intc->reg_intpnd ? intc->reg_intpnd : intc->reg_pending; | ||
| 430 | |||
| 431 | last = 0; | ||
| 432 | for (i = 0; i < 4; i++) { | ||
| 433 | pend = __raw_readl(reg_source); | ||
| 434 | |||
| 435 | if (pend == 0 || pend == last) | ||
| 436 | break; | ||
| 437 | |||
| 438 | __raw_writel(pend, intc->reg_pending); | ||
| 439 | if (intc->reg_intpnd) | ||
| 440 | __raw_writel(pend, intc->reg_intpnd); | ||
| 441 | |||
| 442 | pr_info("irq: clearing pending status %08x\n", (int)pend); | ||
| 443 | last = pend; | ||
| 444 | } | ||
| 445 | } | ||
| 446 | |||
| 447 | struct s3c_irq_intc *s3c24xx_init_intc(struct device_node *np, | ||
| 448 | struct s3c_irq_data *irq_data, | ||
| 449 | struct s3c_irq_intc *parent, | ||
| 450 | unsigned long address) | ||
| 451 | { | ||
| 452 | struct s3c_irq_intc *intc; | ||
| 453 | void __iomem *base = (void *)0xf6000000; /* static mapping */ | ||
| 454 | int irq_num; | ||
| 455 | int irq_start; | ||
| 456 | int ret; | ||
| 457 | |||
| 458 | intc = kzalloc(sizeof(struct s3c_irq_intc), GFP_KERNEL); | ||
| 459 | if (!intc) | ||
| 460 | return ERR_PTR(-ENOMEM); | ||
| 461 | |||
| 462 | intc->irqs = irq_data; | ||
| 463 | |||
| 464 | if (parent) | ||
| 465 | intc->parent = parent; | ||
| 466 | |||
| 467 | /* select the correct data for the controller. | ||
| 468 | * Need to hard code the irq num start and offset | ||
| 469 | * to preserve the static mapping for now | ||
| 470 | */ | ||
| 471 | switch (address) { | ||
| 472 | case 0x4a000000: | ||
| 473 | pr_debug("irq: found main intc\n"); | ||
| 474 | intc->reg_pending = base; | ||
| 475 | intc->reg_mask = base + 0x08; | ||
| 476 | intc->reg_intpnd = base + 0x10; | ||
| 477 | irq_num = 32; | ||
| 478 | irq_start = S3C2410_IRQ(0); | ||
| 479 | break; | ||
| 480 | case 0x4a000018: | ||
| 481 | pr_debug("irq: found subintc\n"); | ||
| 482 | intc->reg_pending = base + 0x18; | ||
| 483 | intc->reg_mask = base + 0x1c; | ||
| 484 | irq_num = 29; | ||
| 485 | irq_start = S3C2410_IRQSUB(0); | ||
| 486 | break; | ||
| 487 | case 0x4a000040: | ||
| 488 | pr_debug("irq: found intc2\n"); | ||
| 489 | intc->reg_pending = base + 0x40; | ||
| 490 | intc->reg_mask = base + 0x48; | ||
| 491 | intc->reg_intpnd = base + 0x50; | ||
| 492 | irq_num = 8; | ||
| 493 | irq_start = S3C2416_IRQ(0); | ||
| 494 | break; | ||
| 495 | case 0x560000a4: | ||
| 496 | pr_debug("irq: found eintc\n"); | ||
| 497 | base = (void *)0xfd000000; | ||
| 498 | |||
| 499 | intc->reg_mask = base + 0xa4; | ||
| 500 | intc->reg_pending = base + 0x08; | ||
| 501 | irq_num = 24; | ||
| 502 | irq_start = S3C2410_IRQ(32); | ||
| 503 | break; | ||
| 504 | default: | ||
| 505 | pr_err("irq: unsupported controller address\n"); | ||
| 506 | ret = -EINVAL; | ||
| 507 | goto err; | ||
| 508 | } | ||
| 509 | |||
| 510 | /* now that all the data is complete, init the irq-domain */ | ||
| 511 | s3c24xx_clear_intc(intc); | ||
| 512 | intc->domain = irq_domain_add_legacy(np, irq_num, irq_start, | ||
| 513 | 0, &s3c24xx_irq_ops, | ||
| 514 | intc); | ||
| 515 | if (!intc->domain) { | ||
| 516 | pr_err("irq: could not create irq-domain\n"); | ||
| 517 | ret = -EINVAL; | ||
| 518 | goto err; | ||
| 519 | } | ||
| 520 | |||
| 521 | return intc; | ||
| 522 | |||
| 523 | err: | ||
| 524 | kfree(intc); | ||
| 525 | return ERR_PTR(ret); | ||
| 526 | } | ||
| 527 | |||
| 528 | /* s3c24xx_init_irq | ||
| 529 | * | ||
| 530 | * Initialise S3C2410 IRQ system | ||
| 531 | */ | ||
| 532 | |||
| 533 | static struct s3c_irq_data init_base[32] = { | ||
| 534 | { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */ | ||
| 535 | { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */ | ||
| 536 | { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */ | ||
| 537 | { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */ | ||
| 538 | { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */ | ||
| 539 | { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */ | ||
| 540 | { .type = S3C_IRQTYPE_NONE, }, /* reserved */ | ||
| 541 | { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */ | ||
| 542 | { .type = S3C_IRQTYPE_EDGE, }, /* TICK */ | ||
| 543 | { .type = S3C_IRQTYPE_EDGE, }, /* WDT */ | ||
| 544 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */ | ||
| 545 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */ | ||
| 546 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */ | ||
| 547 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */ | ||
| 548 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */ | ||
| 549 | { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */ | ||
| 550 | { .type = S3C_IRQTYPE_EDGE, }, /* LCD */ | ||
| 551 | { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */ | ||
| 552 | { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */ | ||
| 553 | { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */ | ||
| 554 | { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */ | ||
| 555 | { .type = S3C_IRQTYPE_EDGE, }, /* SDI */ | ||
| 556 | { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */ | ||
| 557 | { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */ | ||
| 558 | { .type = S3C_IRQTYPE_NONE, }, /* reserved */ | ||
| 559 | { .type = S3C_IRQTYPE_EDGE, }, /* USBD */ | ||
| 560 | { .type = S3C_IRQTYPE_EDGE, }, /* USBH */ | ||
| 561 | { .type = S3C_IRQTYPE_EDGE, }, /* IIC */ | ||
| 562 | { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */ | ||
| 563 | { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */ | ||
| 564 | { .type = S3C_IRQTYPE_EDGE, }, /* RTC */ | ||
| 565 | { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */ | ||
| 566 | }; | ||
| 567 | |||
| 568 | static struct s3c_irq_data init_eint[32] = { | ||
| 569 | { .type = S3C_IRQTYPE_NONE, }, /* reserved */ | ||
| 570 | { .type = S3C_IRQTYPE_NONE, }, /* reserved */ | ||
| 571 | { .type = S3C_IRQTYPE_NONE, }, /* reserved */ | ||
| 572 | { .type = S3C_IRQTYPE_NONE, }, /* reserved */ | ||
| 573 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT4 */ | ||
| 574 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT5 */ | ||
| 575 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT6 */ | ||
| 576 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT7 */ | ||
| 577 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT8 */ | ||
| 578 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT9 */ | ||
| 579 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT10 */ | ||
| 580 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT11 */ | ||
| 581 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT12 */ | ||
| 582 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT13 */ | ||
| 583 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT14 */ | ||
| 584 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT15 */ | ||
| 585 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT16 */ | ||
| 586 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT17 */ | ||
| 587 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT18 */ | ||
| 588 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT19 */ | ||
| 589 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT20 */ | ||
| 590 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT21 */ | ||
| 591 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT22 */ | ||
| 592 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT23 */ | ||
| 593 | }; | ||
| 594 | |||
| 595 | static struct s3c_irq_data init_subint[32] = { | ||
| 596 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */ | ||
| 597 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */ | ||
| 598 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */ | ||
| 599 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */ | ||
| 600 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */ | ||
| 601 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */ | ||
| 602 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */ | ||
| 603 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */ | ||
| 604 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */ | ||
| 605 | { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */ | ||
| 606 | { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */ | ||
| 607 | }; | ||
| 608 | |||
| 609 | void __init s3c24xx_init_irq(void) | ||
| 610 | { | ||
| 611 | struct s3c_irq_intc *main_intc; | ||
| 612 | |||
| 613 | #ifdef CONFIG_FIQ | ||
| 614 | init_FIQ(FIQ_START); | ||
| 615 | #endif | ||
| 616 | |||
| 617 | main_intc = s3c24xx_init_intc(NULL, &init_base[0], NULL, 0x4a000000); | ||
| 618 | if (IS_ERR(main_intc)) { | ||
| 619 | pr_err("irq: could not create main interrupt controller\n"); | ||
| 620 | return; | ||
| 621 | } | ||
| 622 | |||
| 623 | s3c24xx_init_intc(NULL, &init_subint[0], main_intc, 0x4a000018); | ||
| 624 | s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4); | ||
| 625 | } | ||
| 626 | |||
| 627 | #ifdef CONFIG_CPU_S3C2412 | ||
| 628 | static struct s3c_irq_data init_s3c2412base[32] = { | ||
| 629 | { .type = S3C_IRQTYPE_LEVEL, }, /* EINT0 */ | ||
| 630 | { .type = S3C_IRQTYPE_LEVEL, }, /* EINT1 */ | ||
| 631 | { .type = S3C_IRQTYPE_LEVEL, }, /* EINT2 */ | ||
| 632 | { .type = S3C_IRQTYPE_LEVEL, }, /* EINT3 */ | ||
| 633 | { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */ | ||
| 634 | { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */ | ||
| 635 | { .type = S3C_IRQTYPE_NONE, }, /* reserved */ | ||
| 636 | { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */ | ||
| 637 | { .type = S3C_IRQTYPE_EDGE, }, /* TICK */ | ||
| 638 | { .type = S3C_IRQTYPE_EDGE, }, /* WDT */ | ||
| 639 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */ | ||
| 640 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */ | ||
| 641 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */ | ||
| 642 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */ | ||
| 643 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */ | ||
| 644 | { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */ | ||
| 645 | { .type = S3C_IRQTYPE_EDGE, }, /* LCD */ | ||
| 646 | { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */ | ||
| 647 | { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */ | ||
| 648 | { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */ | ||
| 649 | { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */ | ||
| 650 | { .type = S3C_IRQTYPE_LEVEL, }, /* SDI/CF */ | ||
| 651 | { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */ | ||
| 652 | { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */ | ||
| 653 | { .type = S3C_IRQTYPE_NONE, }, /* reserved */ | ||
| 654 | { .type = S3C_IRQTYPE_EDGE, }, /* USBD */ | ||
| 655 | { .type = S3C_IRQTYPE_EDGE, }, /* USBH */ | ||
| 656 | { .type = S3C_IRQTYPE_EDGE, }, /* IIC */ | ||
| 657 | { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */ | ||
| 658 | { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */ | ||
| 659 | { .type = S3C_IRQTYPE_EDGE, }, /* RTC */ | ||
| 660 | { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */ | ||
| 661 | }; | ||
| 662 | |||
| 663 | static struct s3c_irq_data init_s3c2412eint[32] = { | ||
| 664 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 0 }, /* EINT0 */ | ||
| 665 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 1 }, /* EINT1 */ | ||
| 666 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 2 }, /* EINT2 */ | ||
| 667 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 3 }, /* EINT3 */ | ||
| 668 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT4 */ | ||
| 669 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT5 */ | ||
| 670 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT6 */ | ||
| 671 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT7 */ | ||
| 672 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT8 */ | ||
| 673 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT9 */ | ||
| 674 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT10 */ | ||
| 675 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT11 */ | ||
| 676 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT12 */ | ||
| 677 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT13 */ | ||
| 678 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT14 */ | ||
| 679 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT15 */ | ||
| 680 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT16 */ | ||
| 681 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT17 */ | ||
| 682 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT18 */ | ||
| 683 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT19 */ | ||
| 684 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT20 */ | ||
| 685 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT21 */ | ||
| 686 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT22 */ | ||
| 687 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT23 */ | ||
| 688 | }; | ||
| 689 | |||
| 690 | static struct s3c_irq_data init_s3c2412subint[32] = { | ||
| 691 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */ | ||
| 692 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */ | ||
| 693 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */ | ||
| 694 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */ | ||
| 695 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */ | ||
| 696 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */ | ||
| 697 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */ | ||
| 698 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */ | ||
| 699 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */ | ||
| 700 | { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */ | ||
| 701 | { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */ | ||
| 702 | { .type = S3C_IRQTYPE_NONE, }, | ||
| 703 | { .type = S3C_IRQTYPE_NONE, }, | ||
| 704 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 21 }, /* SDI */ | ||
| 705 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 21 }, /* CF */ | ||
| 706 | }; | ||
| 707 | |||
| 708 | void s3c2412_init_irq(void) | ||
| 709 | { | ||
| 710 | struct s3c_irq_intc *main_intc; | ||
| 711 | |||
| 712 | pr_info("S3C2412: IRQ Support\n"); | ||
| 713 | |||
| 714 | #ifdef CONFIG_FIQ | ||
| 715 | init_FIQ(FIQ_START); | ||
| 716 | #endif | ||
| 717 | |||
| 718 | main_intc = s3c24xx_init_intc(NULL, &init_s3c2412base[0], NULL, 0x4a000000); | ||
| 719 | if (IS_ERR(main_intc)) { | ||
| 720 | pr_err("irq: could not create main interrupt controller\n"); | ||
| 721 | return; | ||
| 722 | } | ||
| 723 | |||
| 724 | s3c24xx_init_intc(NULL, &init_s3c2412eint[0], main_intc, 0x560000a4); | ||
| 725 | s3c24xx_init_intc(NULL, &init_s3c2412subint[0], main_intc, 0x4a000018); | ||
| 726 | } | ||
| 727 | #endif | ||
| 728 | |||
| 729 | #ifdef CONFIG_CPU_S3C2416 | ||
| 730 | static struct s3c_irq_data init_s3c2416base[32] = { | ||
| 731 | { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */ | ||
| 732 | { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */ | ||
| 733 | { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */ | ||
| 734 | { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */ | ||
| 735 | { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */ | ||
| 736 | { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */ | ||
| 737 | { .type = S3C_IRQTYPE_NONE, }, /* reserved */ | ||
| 738 | { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */ | ||
| 739 | { .type = S3C_IRQTYPE_EDGE, }, /* TICK */ | ||
| 740 | { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */ | ||
| 741 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */ | ||
| 742 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */ | ||
| 743 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */ | ||
| 744 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */ | ||
| 745 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */ | ||
| 746 | { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */ | ||
| 747 | { .type = S3C_IRQTYPE_LEVEL, }, /* LCD */ | ||
| 748 | { .type = S3C_IRQTYPE_LEVEL, }, /* DMA */ | ||
| 749 | { .type = S3C_IRQTYPE_LEVEL, }, /* UART3 */ | ||
| 750 | { .type = S3C_IRQTYPE_NONE, }, /* reserved */ | ||
| 751 | { .type = S3C_IRQTYPE_EDGE, }, /* SDI1 */ | ||
| 752 | { .type = S3C_IRQTYPE_EDGE, }, /* SDI0 */ | ||
| 753 | { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */ | ||
| 754 | { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */ | ||
| 755 | { .type = S3C_IRQTYPE_EDGE, }, /* NAND */ | ||
| 756 | { .type = S3C_IRQTYPE_EDGE, }, /* USBD */ | ||
| 757 | { .type = S3C_IRQTYPE_EDGE, }, /* USBH */ | ||
| 758 | { .type = S3C_IRQTYPE_EDGE, }, /* IIC */ | ||
| 759 | { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */ | ||
| 760 | { .type = S3C_IRQTYPE_NONE, }, | ||
| 761 | { .type = S3C_IRQTYPE_EDGE, }, /* RTC */ | ||
| 762 | { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */ | ||
| 763 | }; | ||
| 764 | |||
| 765 | static struct s3c_irq_data init_s3c2416subint[32] = { | ||
| 766 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */ | ||
| 767 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */ | ||
| 768 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */ | ||
| 769 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */ | ||
| 770 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */ | ||
| 771 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */ | ||
| 772 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */ | ||
| 773 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */ | ||
| 774 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */ | ||
| 775 | { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */ | ||
| 776 | { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */ | ||
| 777 | { .type = S3C_IRQTYPE_NONE }, /* reserved */ | ||
| 778 | { .type = S3C_IRQTYPE_NONE }, /* reserved */ | ||
| 779 | { .type = S3C_IRQTYPE_NONE }, /* reserved */ | ||
| 780 | { .type = S3C_IRQTYPE_NONE }, /* reserved */ | ||
| 781 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD2 */ | ||
| 782 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD3 */ | ||
| 783 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD4 */ | ||
| 784 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA0 */ | ||
| 785 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA1 */ | ||
| 786 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA2 */ | ||
| 787 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA3 */ | ||
| 788 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA4 */ | ||
| 789 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA5 */ | ||
| 790 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-RX */ | ||
| 791 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-TX */ | ||
| 792 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-ERR */ | ||
| 793 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */ | ||
| 794 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */ | ||
| 795 | }; | ||
| 796 | |||
| 797 | static struct s3c_irq_data init_s3c2416_second[32] = { | ||
| 798 | { .type = S3C_IRQTYPE_EDGE }, /* 2D */ | ||
| 799 | { .type = S3C_IRQTYPE_EDGE }, /* IIC1 */ | ||
| 800 | { .type = S3C_IRQTYPE_NONE }, /* reserved */ | ||
| 801 | { .type = S3C_IRQTYPE_NONE }, /* reserved */ | ||
| 802 | { .type = S3C_IRQTYPE_EDGE }, /* PCM0 */ | ||
| 803 | { .type = S3C_IRQTYPE_EDGE }, /* PCM1 */ | ||
| 804 | { .type = S3C_IRQTYPE_EDGE }, /* I2S0 */ | ||
| 805 | { .type = S3C_IRQTYPE_EDGE }, /* I2S1 */ | ||
| 806 | }; | ||
| 807 | |||
| 808 | void __init s3c2416_init_irq(void) | ||
| 809 | { | ||
| 810 | struct s3c_irq_intc *main_intc; | ||
| 811 | |||
| 812 | pr_info("S3C2416: IRQ Support\n"); | ||
| 813 | |||
| 814 | #ifdef CONFIG_FIQ | ||
| 815 | init_FIQ(FIQ_START); | ||
| 816 | #endif | ||
| 817 | |||
| 818 | main_intc = s3c24xx_init_intc(NULL, &init_s3c2416base[0], NULL, 0x4a000000); | ||
| 819 | if (IS_ERR(main_intc)) { | ||
| 820 | pr_err("irq: could not create main interrupt controller\n"); | ||
| 821 | return; | ||
| 822 | } | ||
| 823 | |||
| 824 | s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4); | ||
| 825 | s3c24xx_init_intc(NULL, &init_s3c2416subint[0], main_intc, 0x4a000018); | ||
| 826 | |||
| 827 | s3c24xx_init_intc(NULL, &init_s3c2416_second[0], NULL, 0x4a000040); | ||
| 828 | } | ||
| 829 | |||
| 830 | #endif | ||
| 831 | |||
| 832 | #ifdef CONFIG_CPU_S3C2440 | ||
| 833 | static struct s3c_irq_data init_s3c2440base[32] = { | ||
| 834 | { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */ | ||
| 835 | { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */ | ||
| 836 | { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */ | ||
| 837 | { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */ | ||
| 838 | { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */ | ||
| 839 | { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */ | ||
| 840 | { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */ | ||
| 841 | { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */ | ||
| 842 | { .type = S3C_IRQTYPE_EDGE, }, /* TICK */ | ||
| 843 | { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */ | ||
| 844 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */ | ||
| 845 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */ | ||
| 846 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */ | ||
| 847 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */ | ||
| 848 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */ | ||
| 849 | { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */ | ||
| 850 | { .type = S3C_IRQTYPE_EDGE, }, /* LCD */ | ||
| 851 | { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */ | ||
| 852 | { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */ | ||
| 853 | { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */ | ||
| 854 | { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */ | ||
| 855 | { .type = S3C_IRQTYPE_EDGE, }, /* SDI */ | ||
| 856 | { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */ | ||
| 857 | { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */ | ||
| 858 | { .type = S3C_IRQTYPE_LEVEL, }, /* NFCON */ | ||
| 859 | { .type = S3C_IRQTYPE_EDGE, }, /* USBD */ | ||
| 860 | { .type = S3C_IRQTYPE_EDGE, }, /* USBH */ | ||
| 861 | { .type = S3C_IRQTYPE_EDGE, }, /* IIC */ | ||
| 862 | { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */ | ||
| 863 | { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */ | ||
| 864 | { .type = S3C_IRQTYPE_EDGE, }, /* RTC */ | ||
| 865 | { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */ | ||
| 866 | }; | ||
| 867 | |||
| 868 | static struct s3c_irq_data init_s3c2440subint[32] = { | ||
| 869 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */ | ||
| 870 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */ | ||
| 871 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */ | ||
| 872 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */ | ||
| 873 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */ | ||
| 874 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */ | ||
| 875 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */ | ||
| 876 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */ | ||
| 877 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */ | ||
| 878 | { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */ | ||
| 879 | { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */ | ||
| 880 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* TC */ | ||
| 881 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* ADC */ | ||
| 882 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */ | ||
| 883 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */ | ||
| 884 | }; | ||
| 885 | |||
| 886 | void __init s3c2440_init_irq(void) | ||
| 887 | { | ||
| 888 | struct s3c_irq_intc *main_intc; | ||
| 889 | |||
| 890 | pr_info("S3C2440: IRQ Support\n"); | ||
| 891 | |||
| 892 | #ifdef CONFIG_FIQ | ||
| 893 | init_FIQ(FIQ_START); | ||
| 894 | #endif | ||
| 895 | |||
| 896 | main_intc = s3c24xx_init_intc(NULL, &init_s3c2440base[0], NULL, 0x4a000000); | ||
| 897 | if (IS_ERR(main_intc)) { | ||
| 898 | pr_err("irq: could not create main interrupt controller\n"); | ||
| 899 | return; | ||
| 900 | } | ||
| 901 | |||
| 902 | s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4); | ||
| 903 | s3c24xx_init_intc(NULL, &init_s3c2440subint[0], main_intc, 0x4a000018); | ||
| 904 | } | ||
| 905 | #endif | ||
| 906 | |||
| 907 | #ifdef CONFIG_CPU_S3C2442 | ||
| 908 | static struct s3c_irq_data init_s3c2442base[32] = { | ||
| 909 | { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */ | ||
| 910 | { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */ | ||
| 911 | { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */ | ||
| 912 | { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */ | ||
| 913 | { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */ | ||
| 914 | { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */ | ||
| 915 | { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */ | ||
| 916 | { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */ | ||
| 917 | { .type = S3C_IRQTYPE_EDGE, }, /* TICK */ | ||
| 918 | { .type = S3C_IRQTYPE_EDGE, }, /* WDT */ | ||
| 919 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */ | ||
| 920 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */ | ||
| 921 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */ | ||
| 922 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */ | ||
| 923 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */ | ||
| 924 | { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */ | ||
| 925 | { .type = S3C_IRQTYPE_EDGE, }, /* LCD */ | ||
| 926 | { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */ | ||
| 927 | { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */ | ||
| 928 | { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */ | ||
| 929 | { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */ | ||
| 930 | { .type = S3C_IRQTYPE_EDGE, }, /* SDI */ | ||
| 931 | { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */ | ||
| 932 | { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */ | ||
| 933 | { .type = S3C_IRQTYPE_LEVEL, }, /* NFCON */ | ||
| 934 | { .type = S3C_IRQTYPE_EDGE, }, /* USBD */ | ||
| 935 | { .type = S3C_IRQTYPE_EDGE, }, /* USBH */ | ||
| 936 | { .type = S3C_IRQTYPE_EDGE, }, /* IIC */ | ||
| 937 | { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */ | ||
| 938 | { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */ | ||
| 939 | { .type = S3C_IRQTYPE_EDGE, }, /* RTC */ | ||
| 940 | { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */ | ||
| 941 | }; | ||
| 942 | |||
| 943 | static struct s3c_irq_data init_s3c2442subint[32] = { | ||
| 944 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */ | ||
| 945 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */ | ||
| 946 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */ | ||
| 947 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */ | ||
| 948 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */ | ||
| 949 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */ | ||
| 950 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */ | ||
| 951 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */ | ||
| 952 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */ | ||
| 953 | { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */ | ||
| 954 | { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */ | ||
| 955 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* TC */ | ||
| 956 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* ADC */ | ||
| 957 | }; | ||
| 958 | |||
| 959 | void __init s3c2442_init_irq(void) | ||
| 960 | { | ||
| 961 | struct s3c_irq_intc *main_intc; | ||
| 962 | |||
| 963 | pr_info("S3C2442: IRQ Support\n"); | ||
| 964 | |||
| 965 | #ifdef CONFIG_FIQ | ||
| 966 | init_FIQ(FIQ_START); | ||
| 967 | #endif | ||
| 968 | |||
| 969 | main_intc = s3c24xx_init_intc(NULL, &init_s3c2442base[0], NULL, 0x4a000000); | ||
| 970 | if (IS_ERR(main_intc)) { | ||
| 971 | pr_err("irq: could not create main interrupt controller\n"); | ||
| 972 | return; | ||
| 973 | } | ||
| 974 | |||
| 975 | s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4); | ||
| 976 | s3c24xx_init_intc(NULL, &init_s3c2442subint[0], main_intc, 0x4a000018); | ||
| 977 | } | ||
| 978 | #endif | ||
| 979 | |||
| 980 | #ifdef CONFIG_CPU_S3C2443 | ||
| 981 | static struct s3c_irq_data init_s3c2443base[32] = { | ||
| 982 | { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */ | ||
| 983 | { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */ | ||
| 984 | { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */ | ||
| 985 | { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */ | ||
| 986 | { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */ | ||
| 987 | { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */ | ||
| 988 | { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */ | ||
| 989 | { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */ | ||
| 990 | { .type = S3C_IRQTYPE_EDGE, }, /* TICK */ | ||
| 991 | { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */ | ||
| 992 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */ | ||
| 993 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */ | ||
| 994 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */ | ||
| 995 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */ | ||
| 996 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */ | ||
| 997 | { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */ | ||
| 998 | { .type = S3C_IRQTYPE_LEVEL, }, /* LCD */ | ||
| 999 | { .type = S3C_IRQTYPE_LEVEL, }, /* DMA */ | ||
| 1000 | { .type = S3C_IRQTYPE_LEVEL, }, /* UART3 */ | ||
| 1001 | { .type = S3C_IRQTYPE_EDGE, }, /* CFON */ | ||
| 1002 | { .type = S3C_IRQTYPE_EDGE, }, /* SDI1 */ | ||
| 1003 | { .type = S3C_IRQTYPE_EDGE, }, /* SDI0 */ | ||
| 1004 | { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */ | ||
| 1005 | { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */ | ||
| 1006 | { .type = S3C_IRQTYPE_EDGE, }, /* NAND */ | ||
| 1007 | { .type = S3C_IRQTYPE_EDGE, }, /* USBD */ | ||
| 1008 | { .type = S3C_IRQTYPE_EDGE, }, /* USBH */ | ||
| 1009 | { .type = S3C_IRQTYPE_EDGE, }, /* IIC */ | ||
| 1010 | { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */ | ||
| 1011 | { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */ | ||
| 1012 | { .type = S3C_IRQTYPE_EDGE, }, /* RTC */ | ||
| 1013 | { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */ | ||
| 1014 | }; | ||
| 1015 | |||
| 1016 | |||
| 1017 | static struct s3c_irq_data init_s3c2443subint[32] = { | ||
| 1018 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */ | ||
| 1019 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */ | ||
| 1020 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */ | ||
| 1021 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */ | ||
| 1022 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */ | ||
| 1023 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */ | ||
| 1024 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */ | ||
| 1025 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */ | ||
| 1026 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */ | ||
| 1027 | { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */ | ||
| 1028 | { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */ | ||
| 1029 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */ | ||
| 1030 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */ | ||
| 1031 | { .type = S3C_IRQTYPE_NONE }, /* reserved */ | ||
| 1032 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD1 */ | ||
| 1033 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD2 */ | ||
| 1034 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD3 */ | ||
| 1035 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD4 */ | ||
| 1036 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA0 */ | ||
| 1037 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA1 */ | ||
| 1038 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA2 */ | ||
| 1039 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA3 */ | ||
| 1040 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA4 */ | ||
| 1041 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA5 */ | ||
| 1042 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-RX */ | ||
| 1043 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-TX */ | ||
| 1044 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-ERR */ | ||
| 1045 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */ | ||
| 1046 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */ | ||
| 1047 | }; | ||
| 1048 | |||
| 1049 | void __init s3c2443_init_irq(void) | ||
| 1050 | { | ||
| 1051 | struct s3c_irq_intc *main_intc; | ||
| 1052 | |||
| 1053 | pr_info("S3C2443: IRQ Support\n"); | ||
| 1054 | |||
| 1055 | #ifdef CONFIG_FIQ | ||
| 1056 | init_FIQ(FIQ_START); | ||
| 1057 | #endif | ||
| 1058 | |||
| 1059 | main_intc = s3c24xx_init_intc(NULL, &init_s3c2443base[0], NULL, 0x4a000000); | ||
| 1060 | if (IS_ERR(main_intc)) { | ||
| 1061 | pr_err("irq: could not create main interrupt controller\n"); | ||
| 1062 | return; | ||
| 1063 | } | ||
| 1064 | |||
| 1065 | s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4); | ||
| 1066 | s3c24xx_init_intc(NULL, &init_s3c2443subint[0], main_intc, 0x4a000018); | ||
| 1067 | } | ||
| 1068 | #endif | ||
diff --git a/arch/arm/mach-s3c24xx/mach-amlm5900.c b/arch/arm/mach-s3c24xx/mach-amlm5900.c index 432144cb54ae..e27b5c91b3db 100644 --- a/arch/arm/mach-s3c24xx/mach-amlm5900.c +++ b/arch/arm/mach-s3c24xx/mach-amlm5900.c | |||
| @@ -238,7 +238,7 @@ static void __init amlm5900_init(void) | |||
| 238 | MACHINE_START(AML_M5900, "AML_M5900") | 238 | MACHINE_START(AML_M5900, "AML_M5900") |
| 239 | .atag_offset = 0x100, | 239 | .atag_offset = 0x100, |
| 240 | .map_io = amlm5900_map_io, | 240 | .map_io = amlm5900_map_io, |
| 241 | .init_irq = s3c24xx_init_irq, | 241 | .init_irq = s3c2410_init_irq, |
| 242 | .init_machine = amlm5900_init, | 242 | .init_machine = amlm5900_init, |
| 243 | .init_time = samsung_timer_init, | 243 | .init_time = samsung_timer_init, |
| 244 | .restart = s3c2410_restart, | 244 | .restart = s3c2410_restart, |
diff --git a/arch/arm/mach-s3c24xx/mach-bast.c b/arch/arm/mach-s3c24xx/mach-bast.c index eabe2db42ef6..22d6ae926d91 100644 --- a/arch/arm/mach-s3c24xx/mach-bast.c +++ b/arch/arm/mach-s3c24xx/mach-bast.c | |||
| @@ -605,7 +605,7 @@ MACHINE_START(BAST, "Simtec-BAST") | |||
| 605 | /* Maintainer: Ben Dooks <ben@simtec.co.uk> */ | 605 | /* Maintainer: Ben Dooks <ben@simtec.co.uk> */ |
| 606 | .atag_offset = 0x100, | 606 | .atag_offset = 0x100, |
| 607 | .map_io = bast_map_io, | 607 | .map_io = bast_map_io, |
| 608 | .init_irq = s3c24xx_init_irq, | 608 | .init_irq = s3c2410_init_irq, |
| 609 | .init_machine = bast_init, | 609 | .init_machine = bast_init, |
| 610 | .init_time = samsung_timer_init, | 610 | .init_time = samsung_timer_init, |
| 611 | .restart = s3c2410_restart, | 611 | .restart = s3c2410_restart, |
diff --git a/arch/arm/mach-s3c24xx/mach-h1940.c b/arch/arm/mach-s3c24xx/mach-h1940.c index 8dd660102846..af4334d6b4d5 100644 --- a/arch/arm/mach-s3c24xx/mach-h1940.c +++ b/arch/arm/mach-s3c24xx/mach-h1940.c | |||
| @@ -667,11 +667,6 @@ static void __init h1940_reserve(void) | |||
| 667 | memblock_reserve(0x30081000, 0x1000); | 667 | memblock_reserve(0x30081000, 0x1000); |
| 668 | } | 668 | } |
| 669 | 669 | ||
| 670 | static void __init h1940_init_irq(void) | ||
| 671 | { | ||
| 672 | s3c24xx_init_irq(); | ||
| 673 | } | ||
| 674 | |||
| 675 | static void __init h1940_init(void) | 670 | static void __init h1940_init(void) |
| 676 | { | 671 | { |
| 677 | u32 tmp; | 672 | u32 tmp; |
| @@ -740,7 +735,7 @@ MACHINE_START(H1940, "IPAQ-H1940") | |||
| 740 | .atag_offset = 0x100, | 735 | .atag_offset = 0x100, |
| 741 | .map_io = h1940_map_io, | 736 | .map_io = h1940_map_io, |
| 742 | .reserve = h1940_reserve, | 737 | .reserve = h1940_reserve, |
| 743 | .init_irq = h1940_init_irq, | 738 | .init_irq = s3c2410_init_irq, |
| 744 | .init_machine = h1940_init, | 739 | .init_machine = h1940_init, |
| 745 | .init_time = samsung_timer_init, | 740 | .init_time = samsung_timer_init, |
| 746 | .restart = s3c2410_restart, | 741 | .restart = s3c2410_restart, |
diff --git a/arch/arm/mach-s3c24xx/mach-n30.c b/arch/arm/mach-s3c24xx/mach-n30.c index 73a690f431e6..2cb46c37c920 100644 --- a/arch/arm/mach-s3c24xx/mach-n30.c +++ b/arch/arm/mach-s3c24xx/mach-n30.c | |||
| @@ -592,7 +592,7 @@ MACHINE_START(N30, "Acer-N30") | |||
| 592 | .atag_offset = 0x100, | 592 | .atag_offset = 0x100, |
| 593 | .init_time = samsung_timer_init, | 593 | .init_time = samsung_timer_init, |
| 594 | .init_machine = n30_init, | 594 | .init_machine = n30_init, |
| 595 | .init_irq = s3c24xx_init_irq, | 595 | .init_irq = s3c2410_init_irq, |
| 596 | .map_io = n30_map_io, | 596 | .map_io = n30_map_io, |
| 597 | .restart = s3c2410_restart, | 597 | .restart = s3c2410_restart, |
| 598 | MACHINE_END | 598 | MACHINE_END |
| @@ -603,7 +603,7 @@ MACHINE_START(N35, "Acer-N35") | |||
| 603 | .atag_offset = 0x100, | 603 | .atag_offset = 0x100, |
| 604 | .init_time = samsung_timer_init, | 604 | .init_time = samsung_timer_init, |
| 605 | .init_machine = n30_init, | 605 | .init_machine = n30_init, |
| 606 | .init_irq = s3c24xx_init_irq, | 606 | .init_irq = s3c2410_init_irq, |
| 607 | .map_io = n30_map_io, | 607 | .map_io = n30_map_io, |
| 608 | .restart = s3c2410_restart, | 608 | .restart = s3c2410_restart, |
| 609 | MACHINE_END | 609 | MACHINE_END |
diff --git a/arch/arm/mach-s3c24xx/mach-otom.c b/arch/arm/mach-s3c24xx/mach-otom.c index 7b8670746b6a..7e16b0740ec1 100644 --- a/arch/arm/mach-s3c24xx/mach-otom.c +++ b/arch/arm/mach-s3c24xx/mach-otom.c | |||
| @@ -116,7 +116,7 @@ MACHINE_START(OTOM, "Nex Vision - Otom 1.1") | |||
| 116 | .atag_offset = 0x100, | 116 | .atag_offset = 0x100, |
| 117 | .map_io = otom11_map_io, | 117 | .map_io = otom11_map_io, |
| 118 | .init_machine = otom11_init, | 118 | .init_machine = otom11_init, |
| 119 | .init_irq = s3c24xx_init_irq, | 119 | .init_irq = s3c2410_init_irq, |
| 120 | .init_time = samsung_timer_init, | 120 | .init_time = samsung_timer_init, |
| 121 | .restart = s3c2410_restart, | 121 | .restart = s3c2410_restart, |
| 122 | MACHINE_END | 122 | MACHINE_END |
diff --git a/arch/arm/mach-s3c24xx/mach-qt2410.c b/arch/arm/mach-s3c24xx/mach-qt2410.c index 71cf29b12d1f..f8feaeadb55a 100644 --- a/arch/arm/mach-s3c24xx/mach-qt2410.c +++ b/arch/arm/mach-s3c24xx/mach-qt2410.c | |||
| @@ -343,7 +343,7 @@ static void __init qt2410_machine_init(void) | |||
| 343 | MACHINE_START(QT2410, "QT2410") | 343 | MACHINE_START(QT2410, "QT2410") |
| 344 | .atag_offset = 0x100, | 344 | .atag_offset = 0x100, |
| 345 | .map_io = qt2410_map_io, | 345 | .map_io = qt2410_map_io, |
| 346 | .init_irq = s3c24xx_init_irq, | 346 | .init_irq = s3c2410_init_irq, |
| 347 | .init_machine = qt2410_machine_init, | 347 | .init_machine = qt2410_machine_init, |
| 348 | .init_time = samsung_timer_init, | 348 | .init_time = samsung_timer_init, |
| 349 | .restart = s3c2410_restart, | 349 | .restart = s3c2410_restart, |
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2410.c b/arch/arm/mach-s3c24xx/mach-smdk2410.c index fd96f7fc330c..a773789e4f38 100644 --- a/arch/arm/mach-s3c24xx/mach-smdk2410.c +++ b/arch/arm/mach-s3c24xx/mach-smdk2410.c | |||
| @@ -116,7 +116,7 @@ MACHINE_START(SMDK2410, "SMDK2410") /* @TODO: request a new identifier and switc | |||
| 116 | /* Maintainer: Jonas Dietsche */ | 116 | /* Maintainer: Jonas Dietsche */ |
| 117 | .atag_offset = 0x100, | 117 | .atag_offset = 0x100, |
| 118 | .map_io = smdk2410_map_io, | 118 | .map_io = smdk2410_map_io, |
| 119 | .init_irq = s3c24xx_init_irq, | 119 | .init_irq = s3c2410_init_irq, |
| 120 | .init_machine = smdk2410_init, | 120 | .init_machine = smdk2410_init, |
| 121 | .init_time = samsung_timer_init, | 121 | .init_time = samsung_timer_init, |
| 122 | .restart = s3c2410_restart, | 122 | .restart = s3c2410_restart, |
diff --git a/arch/arm/mach-s3c24xx/mach-tct_hammer.c b/arch/arm/mach-s3c24xx/mach-tct_hammer.c index 31dfe589e349..7fad8f055cab 100644 --- a/arch/arm/mach-s3c24xx/mach-tct_hammer.c +++ b/arch/arm/mach-s3c24xx/mach-tct_hammer.c | |||
| @@ -149,7 +149,7 @@ static void __init tct_hammer_init(void) | |||
| 149 | MACHINE_START(TCT_HAMMER, "TCT_HAMMER") | 149 | MACHINE_START(TCT_HAMMER, "TCT_HAMMER") |
| 150 | .atag_offset = 0x100, | 150 | .atag_offset = 0x100, |
| 151 | .map_io = tct_hammer_map_io, | 151 | .map_io = tct_hammer_map_io, |
| 152 | .init_irq = s3c24xx_init_irq, | 152 | .init_irq = s3c2410_init_irq, |
| 153 | .init_machine = tct_hammer_init, | 153 | .init_machine = tct_hammer_init, |
| 154 | .init_time = samsung_timer_init, | 154 | .init_time = samsung_timer_init, |
| 155 | .restart = s3c2410_restart, | 155 | .restart = s3c2410_restart, |
diff --git a/arch/arm/mach-s3c24xx/mach-vr1000.c b/arch/arm/mach-s3c24xx/mach-vr1000.c index deeb8a0a4034..42e7187fed60 100644 --- a/arch/arm/mach-s3c24xx/mach-vr1000.c +++ b/arch/arm/mach-s3c24xx/mach-vr1000.c | |||
| @@ -355,7 +355,7 @@ MACHINE_START(VR1000, "Thorcom-VR1000") | |||
| 355 | .atag_offset = 0x100, | 355 | .atag_offset = 0x100, |
| 356 | .map_io = vr1000_map_io, | 356 | .map_io = vr1000_map_io, |
| 357 | .init_machine = vr1000_init, | 357 | .init_machine = vr1000_init, |
| 358 | .init_irq = s3c24xx_init_irq, | 358 | .init_irq = s3c2410_init_irq, |
| 359 | .init_time = samsung_timer_init, | 359 | .init_time = samsung_timer_init, |
| 360 | .restart = s3c2410_restart, | 360 | .restart = s3c2410_restart, |
| 361 | MACHINE_END | 361 | MACHINE_END |
diff --git a/arch/arm/mach-shmobile/board-kzm9d.c b/arch/arm/mach-shmobile/board-kzm9d.c index c254782aa727..c016ccd92433 100644 --- a/arch/arm/mach-shmobile/board-kzm9d.c +++ b/arch/arm/mach-shmobile/board-kzm9d.c | |||
| @@ -90,6 +90,5 @@ DT_MACHINE_START(KZM9D_DT, "kzm9d") | |||
| 90 | .init_irq = emev2_init_irq, | 90 | .init_irq = emev2_init_irq, |
| 91 | .init_machine = kzm9d_add_standard_devices, | 91 | .init_machine = kzm9d_add_standard_devices, |
| 92 | .init_late = shmobile_init_late, | 92 | .init_late = shmobile_init_late, |
| 93 | .init_time = shmobile_timer_init, | ||
| 94 | .dt_compat = kzm9d_boards_compat_dt, | 93 | .dt_compat = kzm9d_boards_compat_dt, |
| 95 | MACHINE_END | 94 | MACHINE_END |
diff --git a/arch/arm/mach-shmobile/setup-emev2.c b/arch/arm/mach-shmobile/setup-emev2.c index e4545c152722..899a86c31ec9 100644 --- a/arch/arm/mach-shmobile/setup-emev2.c +++ b/arch/arm/mach-shmobile/setup-emev2.c | |||
| @@ -456,7 +456,6 @@ DT_MACHINE_START(EMEV2_DT, "Generic Emma Mobile EV2 (Flattened Device Tree)") | |||
| 456 | .nr_irqs = NR_IRQS_LEGACY, | 456 | .nr_irqs = NR_IRQS_LEGACY, |
| 457 | .init_irq = irqchip_init, | 457 | .init_irq = irqchip_init, |
| 458 | .init_machine = emev2_add_standard_devices_dt, | 458 | .init_machine = emev2_add_standard_devices_dt, |
| 459 | .init_time = shmobile_timer_init, | ||
| 460 | .dt_compat = emev2_boards_compat_dt, | 459 | .dt_compat = emev2_boards_compat_dt, |
| 461 | MACHINE_END | 460 | MACHINE_END |
| 462 | 461 | ||
diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c index 8b85d4d8fab6..104b474a2ccf 100644 --- a/arch/arm/mach-shmobile/setup-r8a7740.c +++ b/arch/arm/mach-shmobile/setup-r8a7740.c | |||
| @@ -906,7 +906,6 @@ DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)") | |||
| 906 | .init_irq = r8a7740_init_irq, | 906 | .init_irq = r8a7740_init_irq, |
| 907 | .handle_irq = shmobile_handle_irq_intc, | 907 | .handle_irq = shmobile_handle_irq_intc, |
| 908 | .init_machine = r8a7740_add_standard_devices_dt, | 908 | .init_machine = r8a7740_add_standard_devices_dt, |
| 909 | .init_time = shmobile_timer_init, | ||
| 910 | .dt_compat = r8a7740_boards_compat_dt, | 909 | .dt_compat = r8a7740_boards_compat_dt, |
| 911 | MACHINE_END | 910 | MACHINE_END |
| 912 | 911 | ||
diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c index 59c7146bf66f..5502d624aca6 100644 --- a/arch/arm/mach-shmobile/setup-sh7372.c +++ b/arch/arm/mach-shmobile/setup-sh7372.c | |||
| @@ -1175,7 +1175,6 @@ DT_MACHINE_START(SH7372_DT, "Generic SH7372 (Flattened Device Tree)") | |||
| 1175 | .init_irq = sh7372_init_irq, | 1175 | .init_irq = sh7372_init_irq, |
| 1176 | .handle_irq = shmobile_handle_irq_intc, | 1176 | .handle_irq = shmobile_handle_irq_intc, |
| 1177 | .init_machine = sh7372_add_standard_devices_dt, | 1177 | .init_machine = sh7372_add_standard_devices_dt, |
| 1178 | .init_time = shmobile_timer_init, | ||
| 1179 | .dt_compat = sh7372_boards_compat_dt, | 1178 | .dt_compat = sh7372_boards_compat_dt, |
| 1180 | MACHINE_END | 1179 | MACHINE_END |
| 1181 | 1180 | ||
diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c index e8cd93a5c550..fdf3894b1cc3 100644 --- a/arch/arm/mach-shmobile/setup-sh73a0.c +++ b/arch/arm/mach-shmobile/setup-sh73a0.c | |||
| @@ -1037,7 +1037,6 @@ DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)") | |||
| 1037 | .nr_irqs = NR_IRQS_LEGACY, | 1037 | .nr_irqs = NR_IRQS_LEGACY, |
| 1038 | .init_irq = irqchip_init, | 1038 | .init_irq = irqchip_init, |
| 1039 | .init_machine = sh73a0_add_standard_devices_dt, | 1039 | .init_machine = sh73a0_add_standard_devices_dt, |
| 1040 | .init_time = shmobile_timer_init, | ||
| 1041 | .dt_compat = sh73a0_boards_compat_dt, | 1040 | .dt_compat = sh73a0_boards_compat_dt, |
| 1042 | MACHINE_END | 1041 | MACHINE_END |
| 1043 | #endif /* CONFIG_USE_OF */ | 1042 | #endif /* CONFIG_USE_OF */ |
diff --git a/arch/arm/mach-shmobile/timer.c b/arch/arm/mach-shmobile/timer.c index 3d16d4dff01b..f321dbeb2379 100644 --- a/arch/arm/mach-shmobile/timer.c +++ b/arch/arm/mach-shmobile/timer.c | |||
| @@ -19,10 +19,8 @@ | |||
| 19 | * | 19 | * |
| 20 | */ | 20 | */ |
| 21 | #include <linux/platform_device.h> | 21 | #include <linux/platform_device.h> |
| 22 | #include <linux/clocksource.h> | ||
| 22 | #include <linux/delay.h> | 23 | #include <linux/delay.h> |
| 23 | #include <asm/arch_timer.h> | ||
| 24 | #include <asm/mach/time.h> | ||
| 25 | #include <asm/smp_twd.h> | ||
| 26 | 24 | ||
| 27 | void __init shmobile_setup_delay(unsigned int max_cpu_core_mhz, | 25 | void __init shmobile_setup_delay(unsigned int max_cpu_core_mhz, |
| 28 | unsigned int mult, unsigned int div) | 26 | unsigned int mult, unsigned int div) |
| @@ -63,6 +61,5 @@ void __init shmobile_earlytimer_init(void) | |||
| 63 | 61 | ||
| 64 | void __init shmobile_timer_init(void) | 62 | void __init shmobile_timer_init(void) |
| 65 | { | 63 | { |
| 66 | arch_timer_of_register(); | 64 | clocksource_of_init(); |
| 67 | arch_timer_sched_clock_init(); | ||
| 68 | } | 65 | } |
diff --git a/arch/arm/mach-spear/Kconfig b/arch/arm/mach-spear/Kconfig new file mode 100644 index 000000000000..5412aeb377ac --- /dev/null +++ b/arch/arm/mach-spear/Kconfig | |||
| @@ -0,0 +1,103 @@ | |||
| 1 | # | ||
| 2 | # SPEAr Platform configuration file | ||
| 3 | # | ||
| 4 | |||
| 5 | menuconfig PLAT_SPEAR | ||
| 6 | bool "ST SPEAr Family" if ARCH_MULTI_V7 || ARCH_MULTI_V5 | ||
| 7 | default PLAT_SPEAR_SINGLE | ||
| 8 | select ARCH_REQUIRE_GPIOLIB | ||
| 9 | select ARM_AMBA | ||
| 10 | select CLKDEV_LOOKUP | ||
| 11 | select CLKSRC_MMIO | ||
| 12 | select COMMON_CLK | ||
| 13 | select GENERIC_CLOCKEVENTS | ||
| 14 | select HAVE_CLK | ||
| 15 | |||
| 16 | if PLAT_SPEAR | ||
| 17 | |||
| 18 | config ARCH_SPEAR13XX | ||
| 19 | bool "ST SPEAr13xx" | ||
| 20 | depends on ARCH_MULTI_V7 || PLAT_SPEAR_SINGLE | ||
| 21 | select ARCH_HAS_CPUFREQ | ||
| 22 | select ARM_GIC | ||
| 23 | select CPU_V7 | ||
| 24 | select GPIO_SPEAR_SPICS | ||
| 25 | select HAVE_SMP | ||
| 26 | select MIGHT_HAVE_CACHE_L2X0 | ||
| 27 | select PINCTRL | ||
| 28 | select USE_OF | ||
| 29 | help | ||
| 30 | Supports for ARM's SPEAR13XX family | ||
| 31 | |||
| 32 | if ARCH_SPEAR13XX | ||
| 33 | |||
| 34 | config MACH_SPEAR1310 | ||
| 35 | bool "SPEAr1310 Machine support with Device Tree" | ||
| 36 | select PINCTRL_SPEAR1310 | ||
| 37 | help | ||
| 38 | Supports ST SPEAr1310 machine configured via the device-tree | ||
| 39 | |||
| 40 | config MACH_SPEAR1340 | ||
| 41 | bool "SPEAr1340 Machine support with Device Tree" | ||
| 42 | select PINCTRL_SPEAR1340 | ||
| 43 | help | ||
| 44 | Supports ST SPEAr1340 machine configured via the device-tree | ||
| 45 | |||
| 46 | endif #ARCH_SPEAR13XX | ||
| 47 | |||
| 48 | config ARCH_SPEAR3XX | ||
| 49 | bool "ST SPEAr3xx" | ||
| 50 | depends on ARCH_MULTI_V5 || PLAT_SPEAR_SINGLE | ||
| 51 | depends on !ARCH_SPEAR13XX | ||
| 52 | select ARM_VIC | ||
| 53 | select CPU_ARM926T | ||
| 54 | select PINCTRL | ||
| 55 | select USE_OF | ||
| 56 | help | ||
| 57 | Supports for ARM's SPEAR3XX family | ||
| 58 | |||
| 59 | if ARCH_SPEAR3XX | ||
| 60 | |||
| 61 | config MACH_SPEAR300 | ||
| 62 | bool "SPEAr300 Machine support with Device Tree" | ||
| 63 | select PINCTRL_SPEAR300 | ||
| 64 | help | ||
| 65 | Supports ST SPEAr300 machine configured via the device-tree | ||
| 66 | |||
| 67 | config MACH_SPEAR310 | ||
| 68 | bool "SPEAr310 Machine support with Device Tree" | ||
| 69 | select PINCTRL_SPEAR310 | ||
| 70 | help | ||
| 71 | Supports ST SPEAr310 machine configured via the device-tree | ||
| 72 | |||
| 73 | config MACH_SPEAR320 | ||
| 74 | bool "SPEAr320 Machine support with Device Tree" | ||
| 75 | select PINCTRL_SPEAR320 | ||
| 76 | help | ||
| 77 | Supports ST SPEAr320 machine configured via the device-tree | ||
| 78 | |||
| 79 | endif | ||
| 80 | |||
| 81 | config ARCH_SPEAR6XX | ||
| 82 | bool "ST SPEAr6XX" | ||
| 83 | depends on ARCH_MULTI_V5 || PLAT_SPEAR_SINGLE | ||
| 84 | depends on !ARCH_SPEAR13XX | ||
| 85 | select ARM_VIC | ||
| 86 | select CPU_ARM926T | ||
| 87 | help | ||
| 88 | Supports for ARM's SPEAR6XX family | ||
| 89 | |||
| 90 | config MACH_SPEAR600 | ||
| 91 | def_bool y | ||
| 92 | depends on ARCH_SPEAR6XX | ||
| 93 | select USE_OF | ||
| 94 | help | ||
| 95 | Supports ST SPEAr600 boards configured via the device-treesource "arch/arm/mach-spear6xx/Kconfig" | ||
| 96 | |||
| 97 | config ARCH_SPEAR_AUTO | ||
| 98 | def_bool PLAT_SPEAR_SINGLE | ||
| 99 | depends on !ARCH_SPEAR13XX && !ARCH_SPEAR6XX | ||
| 100 | select ARCH_SPEAR3XX | ||
| 101 | |||
| 102 | endif | ||
| 103 | |||
diff --git a/arch/arm/mach-spear/Makefile b/arch/arm/mach-spear/Makefile new file mode 100644 index 000000000000..8aaf724e1ea4 --- /dev/null +++ b/arch/arm/mach-spear/Makefile | |||
| @@ -0,0 +1,24 @@ | |||
| 1 | # | ||
| 2 | # SPEAr Platform specific Makefile | ||
| 3 | # | ||
| 4 | |||
| 5 | ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include | ||
| 6 | |||
| 7 | # Common support | ||
| 8 | obj-y := restart.o time.o | ||
| 9 | |||
| 10 | smp-$(CONFIG_SMP) += headsmp.o platsmp.o | ||
| 11 | smp-$(CONFIG_HOTPLUG_CPU) += hotplug.o | ||
| 12 | |||
| 13 | obj-$(CONFIG_ARCH_SPEAR13XX) += spear13xx.o $(smp-y) | ||
| 14 | obj-$(CONFIG_MACH_SPEAR1310) += spear1310.o | ||
| 15 | obj-$(CONFIG_MACH_SPEAR1340) += spear1340.o | ||
| 16 | |||
| 17 | obj-$(CONFIG_ARCH_SPEAR3XX) += spear3xx.o | ||
| 18 | obj-$(CONFIG_ARCH_SPEAR3XX) += pl080.o | ||
| 19 | obj-$(CONFIG_MACH_SPEAR300) += spear300.o | ||
| 20 | obj-$(CONFIG_MACH_SPEAR310) += spear310.o | ||
| 21 | obj-$(CONFIG_MACH_SPEAR320) += spear320.o | ||
| 22 | |||
| 23 | obj-$(CONFIG_ARCH_SPEAR6XX) += spear6xx.o | ||
| 24 | obj-$(CONFIG_ARCH_SPEAR6XX) += pl080.o | ||
diff --git a/arch/arm/mach-spear13xx/Makefile.boot b/arch/arm/mach-spear/Makefile.boot index 4674a4c221db..4674a4c221db 100644 --- a/arch/arm/mach-spear13xx/Makefile.boot +++ b/arch/arm/mach-spear/Makefile.boot | |||
diff --git a/arch/arm/mach-spear13xx/include/mach/generic.h b/arch/arm/mach-spear/generic.h index 633e678e01a3..a9fd45362fee 100644 --- a/arch/arm/mach-spear13xx/include/mach/generic.h +++ b/arch/arm/mach-spear/generic.h | |||
| @@ -1,9 +1,8 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * arch/arm/mach-spear13xx/include/mach/generic.h | 2 | * spear machine family generic header file |
| 3 | * | 3 | * |
| 4 | * spear13xx machine family generic header file | 4 | * Copyright (C) 2009-2012 ST Microelectronics |
| 5 | * | 5 | * Rajeev Kumar <rajeev-dlh.kumar@st.com> |
| 6 | * Copyright (C) 2012 ST Microelectronics | ||
| 7 | * Viresh Kumar <viresh.linux@gmail.com> | 6 | * Viresh Kumar <viresh.linux@gmail.com> |
| 8 | * | 7 | * |
| 9 | * This file is licensed under the terms of the GNU General Public | 8 | * This file is licensed under the terms of the GNU General Public |
| @@ -15,37 +14,41 @@ | |||
| 15 | #define __MACH_GENERIC_H | 14 | #define __MACH_GENERIC_H |
| 16 | 15 | ||
| 17 | #include <linux/dmaengine.h> | 16 | #include <linux/dmaengine.h> |
| 17 | #include <linux/amba/pl08x.h> | ||
| 18 | #include <linux/init.h> | ||
| 18 | #include <asm/mach/time.h> | 19 | #include <asm/mach/time.h> |
| 19 | 20 | ||
| 20 | /* Add spear13xx structure declarations here */ | ||
| 21 | extern void spear13xx_timer_init(void); | 21 | extern void spear13xx_timer_init(void); |
| 22 | extern void spear3xx_timer_init(void); | ||
| 22 | extern struct pl022_ssp_controller pl022_plat_data; | 23 | extern struct pl022_ssp_controller pl022_plat_data; |
| 23 | extern struct dw_dma_platform_data dmac_plat_data; | 24 | extern struct pl08x_platform_data pl080_plat_data; |
| 24 | extern struct dw_dma_slave cf_dma_priv; | ||
| 25 | extern struct dw_dma_slave nand_read_dma_priv; | ||
| 26 | extern struct dw_dma_slave nand_write_dma_priv; | ||
| 27 | 25 | ||
| 28 | /* Add spear13xx family function declarations here */ | ||
| 29 | void __init spear_setup_of_timer(void); | 26 | void __init spear_setup_of_timer(void); |
| 27 | void __init spear3xx_clk_init(void __iomem *misc_base, | ||
| 28 | void __iomem *soc_config_base); | ||
| 29 | void __init spear3xx_map_io(void); | ||
| 30 | void __init spear3xx_dt_init_irq(void); | ||
| 31 | void __init spear6xx_clk_init(void __iomem *misc_base); | ||
| 30 | void __init spear13xx_map_io(void); | 32 | void __init spear13xx_map_io(void); |
| 31 | void __init spear13xx_l2x0_init(void); | 33 | void __init spear13xx_l2x0_init(void); |
| 32 | bool dw_dma_filter(struct dma_chan *chan, void *slave); | 34 | |
| 33 | void spear_restart(char, const char *); | 35 | void spear_restart(char, const char *); |
| 36 | |||
| 34 | void spear13xx_secondary_startup(void); | 37 | void spear13xx_secondary_startup(void); |
| 35 | void __cpuinit spear13xx_cpu_die(unsigned int cpu); | 38 | void __cpuinit spear13xx_cpu_die(unsigned int cpu); |
| 36 | 39 | ||
| 37 | extern struct smp_operations spear13xx_smp_ops; | 40 | extern struct smp_operations spear13xx_smp_ops; |
| 38 | 41 | ||
| 39 | #ifdef CONFIG_MACH_SPEAR1310 | 42 | #ifdef CONFIG_MACH_SPEAR1310 |
| 40 | void __init spear1310_clk_init(void); | 43 | void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base); |
| 41 | #else | 44 | #else |
| 42 | static inline void spear1310_clk_init(void) {} | 45 | static inline void spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base) {} |
| 43 | #endif | 46 | #endif |
| 44 | 47 | ||
| 45 | #ifdef CONFIG_MACH_SPEAR1340 | 48 | #ifdef CONFIG_MACH_SPEAR1340 |
| 46 | void __init spear1340_clk_init(void); | 49 | void __init spear1340_clk_init(void __iomem *misc_base); |
| 47 | #else | 50 | #else |
| 48 | static inline void spear1340_clk_init(void) {} | 51 | static inline void spear1340_clk_init(void __iomem *misc_base) {} |
| 49 | #endif | 52 | #endif |
| 50 | 53 | ||
| 51 | #endif /* __MACH_GENERIC_H */ | 54 | #endif /* __MACH_GENERIC_H */ |
diff --git a/arch/arm/mach-spear13xx/headsmp.S b/arch/arm/mach-spear/headsmp.S index ed85473a047f..ed85473a047f 100644 --- a/arch/arm/mach-spear13xx/headsmp.S +++ b/arch/arm/mach-spear/headsmp.S | |||
diff --git a/arch/arm/mach-spear13xx/hotplug.c b/arch/arm/mach-spear/hotplug.c index a7d2dd11a4f2..a7d2dd11a4f2 100644 --- a/arch/arm/mach-spear13xx/hotplug.c +++ b/arch/arm/mach-spear/hotplug.c | |||
diff --git a/arch/arm/plat-spear/include/plat/debug-macro.S b/arch/arm/mach-spear/include/mach/debug-macro.S index 75b05ad0fbad..75b05ad0fbad 100644 --- a/arch/arm/plat-spear/include/plat/debug-macro.S +++ b/arch/arm/mach-spear/include/mach/debug-macro.S | |||
diff --git a/arch/arm/mach-spear6xx/include/mach/irqs.h b/arch/arm/mach-spear/include/mach/irqs.h index 37a5c411a866..92da0a8c6bce 100644 --- a/arch/arm/mach-spear6xx/include/mach/irqs.h +++ b/arch/arm/mach-spear/include/mach/irqs.h | |||
| @@ -1,10 +1,9 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * arch/arm/mach-spear6xx/include/mach/irqs.h | 2 | * IRQ helper macros for spear machine family |
| 3 | * | 3 | * |
| 4 | * IRQ helper macros for SPEAr6xx machine family | 4 | * Copyright (C) 2009-2012 ST Microelectronics |
| 5 | * | 5 | * Rajeev Kumar <rajeev-dlh.kumar@st.com> |
| 6 | * Copyright (C) 2009 ST Microelectronics | 6 | * Viresh Kumar <viresh.linux@gmail.com> |
| 7 | * Rajeev Kumar<rajeev-dlh.kumar@st.com> | ||
| 8 | * | 7 | * |
| 9 | * This file is licensed under the terms of the GNU General Public | 8 | * This file is licensed under the terms of the GNU General Public |
| 10 | * License version 2. This program is licensed "as is" without any | 9 | * License version 2. This program is licensed "as is" without any |
| @@ -14,6 +13,11 @@ | |||
| 14 | #ifndef __MACH_IRQS_H | 13 | #ifndef __MACH_IRQS_H |
| 15 | #define __MACH_IRQS_H | 14 | #define __MACH_IRQS_H |
| 16 | 15 | ||
| 16 | #ifdef CONFIG_ARCH_SPEAR3XX | ||
| 17 | #define NR_IRQS 256 | ||
| 18 | #endif | ||
| 19 | |||
| 20 | #ifdef CONFIG_ARCH_SPEAR6XX | ||
| 17 | /* IRQ definitions */ | 21 | /* IRQ definitions */ |
| 18 | /* VIC 1 */ | 22 | /* VIC 1 */ |
| 19 | #define IRQ_VIC_END 64 | 23 | #define IRQ_VIC_END 64 |
| @@ -21,5 +25,11 @@ | |||
| 21 | /* GPIO pins virtual irqs */ | 25 | /* GPIO pins virtual irqs */ |
| 22 | #define VIRTUAL_IRQS 24 | 26 | #define VIRTUAL_IRQS 24 |
| 23 | #define NR_IRQS (IRQ_VIC_END + VIRTUAL_IRQS) | 27 | #define NR_IRQS (IRQ_VIC_END + VIRTUAL_IRQS) |
| 28 | #endif | ||
| 29 | |||
| 30 | #ifdef CONFIG_ARCH_SPEAR13XX | ||
| 31 | #define IRQ_GIC_END 160 | ||
| 32 | #define NR_IRQS IRQ_GIC_END | ||
| 33 | #endif | ||
| 24 | 34 | ||
| 25 | #endif /* __MACH_IRQS_H */ | 35 | #endif /* __MACH_IRQS_H */ |
diff --git a/arch/arm/mach-spear3xx/include/mach/misc_regs.h b/arch/arm/mach-spear/include/mach/misc_regs.h index 6309bf68d6f8..935639ce59ba 100644 --- a/arch/arm/mach-spear3xx/include/mach/misc_regs.h +++ b/arch/arm/mach-spear/include/mach/misc_regs.h | |||
| @@ -16,7 +16,7 @@ | |||
| 16 | 16 | ||
| 17 | #include <mach/spear.h> | 17 | #include <mach/spear.h> |
| 18 | 18 | ||
| 19 | #define MISC_BASE IOMEM(VA_SPEAR3XX_ICM3_MISC_REG_BASE) | 19 | #define MISC_BASE (VA_SPEAR_ICM3_MISC_REG_BASE) |
| 20 | #define DMA_CHN_CFG (MISC_BASE + 0x0A0) | 20 | #define DMA_CHN_CFG (MISC_BASE + 0x0A0) |
| 21 | 21 | ||
| 22 | #endif /* __MACH_MISC_REGS_H */ | 22 | #endif /* __MACH_MISC_REGS_H */ |
diff --git a/arch/arm/mach-spear/include/mach/spear.h b/arch/arm/mach-spear/include/mach/spear.h new file mode 100644 index 000000000000..cf3a5369eeca --- /dev/null +++ b/arch/arm/mach-spear/include/mach/spear.h | |||
| @@ -0,0 +1,93 @@ | |||
| 1 | /* | ||
| 2 | * SPEAr3xx/6xx Machine family specific definition | ||
| 3 | * | ||
| 4 | * Copyright (C) 2009,2012 ST Microelectronics | ||
| 5 | * Rajeev Kumar<rajeev-dlh.kumar@st.com> | ||
| 6 | * Viresh Kumar <viresh.linux@gmail.com> | ||
| 7 | * | ||
| 8 | * This file is licensed under the terms of the GNU General Public | ||
| 9 | * License version 2. This program is licensed "as is" without any | ||
| 10 | * warranty of any kind, whether express or implied. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __MACH_SPEAR_H | ||
| 14 | #define __MACH_SPEAR_H | ||
| 15 | |||
| 16 | #include <asm/memory.h> | ||
| 17 | |||
| 18 | #if defined(CONFIG_ARCH_SPEAR3XX) || defined (CONFIG_ARCH_SPEAR6XX) | ||
| 19 | |||
| 20 | /* ICM1 - Low speed connection */ | ||
| 21 | #define SPEAR_ICM1_2_BASE UL(0xD0000000) | ||
| 22 | #define VA_SPEAR_ICM1_2_BASE IOMEM(0xFD000000) | ||
| 23 | #define SPEAR_ICM1_UART_BASE UL(0xD0000000) | ||
| 24 | #define VA_SPEAR_ICM1_UART_BASE (VA_SPEAR_ICM1_2_BASE - SPEAR_ICM1_2_BASE + SPEAR_ICM1_UART_BASE) | ||
| 25 | #define SPEAR3XX_ICM1_SSP_BASE UL(0xD0100000) | ||
| 26 | |||
| 27 | /* ML-1, 2 - Multi Layer CPU Subsystem */ | ||
| 28 | #define SPEAR_ICM3_ML1_2_BASE UL(0xF0000000) | ||
| 29 | #define VA_SPEAR6XX_ML_CPU_BASE IOMEM(0xF0000000) | ||
| 30 | |||
| 31 | /* ICM3 - Basic Subsystem */ | ||
| 32 | #define SPEAR_ICM3_SMI_CTRL_BASE UL(0xFC000000) | ||
| 33 | #define VA_SPEAR_ICM3_SMI_CTRL_BASE IOMEM(0xFC000000) | ||
| 34 | #define SPEAR_ICM3_DMA_BASE UL(0xFC400000) | ||
| 35 | #define SPEAR_ICM3_SYS_CTRL_BASE UL(0xFCA00000) | ||
| 36 | #define VA_SPEAR_ICM3_SYS_CTRL_BASE (VA_SPEAR_ICM3_SMI_CTRL_BASE - SPEAR_ICM3_SMI_CTRL_BASE + SPEAR_ICM3_SYS_CTRL_BASE) | ||
| 37 | #define SPEAR_ICM3_MISC_REG_BASE UL(0xFCA80000) | ||
| 38 | #define VA_SPEAR_ICM3_MISC_REG_BASE (VA_SPEAR_ICM3_SMI_CTRL_BASE - SPEAR_ICM3_SMI_CTRL_BASE + SPEAR_ICM3_MISC_REG_BASE) | ||
| 39 | |||
| 40 | /* Debug uart for linux, will be used for debug and uncompress messages */ | ||
| 41 | #define SPEAR_DBG_UART_BASE SPEAR_ICM1_UART_BASE | ||
| 42 | #define VA_SPEAR_DBG_UART_BASE VA_SPEAR_ICM1_UART_BASE | ||
| 43 | |||
| 44 | /* Sysctl base for spear platform */ | ||
| 45 | #define SPEAR_SYS_CTRL_BASE SPEAR_ICM3_SYS_CTRL_BASE | ||
| 46 | #define VA_SPEAR_SYS_CTRL_BASE VA_SPEAR_ICM3_SYS_CTRL_BASE | ||
| 47 | #endif /* SPEAR3xx || SPEAR6XX */ | ||
| 48 | |||
| 49 | /* SPEAr320 Macros */ | ||
| 50 | #define SPEAR320_SOC_CONFIG_BASE UL(0xB3000000) | ||
| 51 | #define VA_SPEAR320_SOC_CONFIG_BASE IOMEM(0xFE000000) | ||
| 52 | |||
| 53 | #ifdef CONFIG_ARCH_SPEAR13XX | ||
| 54 | |||
| 55 | #define PERIP_GRP2_BASE UL(0xB3000000) | ||
| 56 | #define VA_PERIP_GRP2_BASE IOMEM(0xFE000000) | ||
| 57 | #define MCIF_SDHCI_BASE UL(0xB3000000) | ||
| 58 | #define SYSRAM0_BASE UL(0xB3800000) | ||
| 59 | #define VA_SYSRAM0_BASE IOMEM(0xFE800000) | ||
| 60 | #define SYS_LOCATION (VA_SYSRAM0_BASE + 0x600) | ||
| 61 | |||
| 62 | #define PERIP_GRP1_BASE UL(0xE0000000) | ||
| 63 | #define VA_PERIP_GRP1_BASE IOMEM(0xFD000000) | ||
| 64 | #define UART_BASE UL(0xE0000000) | ||
| 65 | #define VA_UART_BASE IOMEM(0xFD000000) | ||
| 66 | #define SSP_BASE UL(0xE0100000) | ||
| 67 | #define MISC_BASE UL(0xE0700000) | ||
| 68 | #define VA_MISC_BASE IOMEM(0xFD700000) | ||
| 69 | |||
| 70 | #define A9SM_AND_MPMC_BASE UL(0xEC000000) | ||
| 71 | #define VA_A9SM_AND_MPMC_BASE IOMEM(0xFC000000) | ||
| 72 | |||
| 73 | #define SPEAR1310_RAS_BASE UL(0xD8400000) | ||
| 74 | #define VA_SPEAR1310_RAS_BASE IOMEM(UL(0xFA400000)) | ||
| 75 | |||
| 76 | /* A9SM peripheral offsets */ | ||
| 77 | #define A9SM_PERIP_BASE UL(0xEC800000) | ||
| 78 | #define VA_A9SM_PERIP_BASE IOMEM(0xFC800000) | ||
| 79 | #define VA_SCU_BASE (VA_A9SM_PERIP_BASE + 0x00) | ||
| 80 | |||
| 81 | #define L2CC_BASE UL(0xED000000) | ||
| 82 | #define VA_L2CC_BASE IOMEM(UL(0xFB000000)) | ||
| 83 | |||
| 84 | /* others */ | ||
| 85 | #define MCIF_CF_BASE UL(0xB2800000) | ||
| 86 | |||
| 87 | /* Debug uart for linux, will be used for debug and uncompress messages */ | ||
| 88 | #define SPEAR_DBG_UART_BASE UART_BASE | ||
| 89 | #define VA_SPEAR_DBG_UART_BASE VA_UART_BASE | ||
| 90 | |||
| 91 | #endif /* SPEAR13XX */ | ||
| 92 | |||
| 93 | #endif /* __MACH_SPEAR_H */ | ||
diff --git a/arch/arm/plat-spear/include/plat/timex.h b/arch/arm/mach-spear/include/mach/timex.h index ef95e5b780bd..ef95e5b780bd 100644 --- a/arch/arm/plat-spear/include/plat/timex.h +++ b/arch/arm/mach-spear/include/mach/timex.h | |||
diff --git a/arch/arm/plat-spear/include/plat/uncompress.h b/arch/arm/mach-spear/include/mach/uncompress.h index 51b2dc93e4da..51b2dc93e4da 100644 --- a/arch/arm/plat-spear/include/plat/uncompress.h +++ b/arch/arm/mach-spear/include/mach/uncompress.h | |||
diff --git a/arch/arm/plat-spear/pl080.c b/arch/arm/mach-spear/pl080.c index cfa1199d0f4a..cfa1199d0f4a 100644 --- a/arch/arm/plat-spear/pl080.c +++ b/arch/arm/mach-spear/pl080.c | |||
diff --git a/arch/arm/plat-spear/include/plat/pl080.h b/arch/arm/mach-spear/pl080.h index eb6590ded40d..eb6590ded40d 100644 --- a/arch/arm/plat-spear/include/plat/pl080.h +++ b/arch/arm/mach-spear/pl080.h | |||
diff --git a/arch/arm/mach-spear13xx/platsmp.c b/arch/arm/mach-spear/platsmp.c index af4ade61cd95..927979e26b4d 100644 --- a/arch/arm/mach-spear13xx/platsmp.c +++ b/arch/arm/mach-spear/platsmp.c | |||
| @@ -19,7 +19,7 @@ | |||
| 19 | #include <asm/cacheflush.h> | 19 | #include <asm/cacheflush.h> |
| 20 | #include <asm/smp_scu.h> | 20 | #include <asm/smp_scu.h> |
| 21 | #include <mach/spear.h> | 21 | #include <mach/spear.h> |
| 22 | #include <mach/generic.h> | 22 | #include "generic.h" |
| 23 | 23 | ||
| 24 | static DEFINE_SPINLOCK(boot_lock); | 24 | static DEFINE_SPINLOCK(boot_lock); |
| 25 | 25 | ||
diff --git a/arch/arm/plat-spear/restart.c b/arch/arm/mach-spear/restart.c index 7d4616d5df11..2b44500bb718 100644 --- a/arch/arm/plat-spear/restart.c +++ b/arch/arm/mach-spear/restart.c | |||
| @@ -14,7 +14,7 @@ | |||
| 14 | #include <linux/amba/sp810.h> | 14 | #include <linux/amba/sp810.h> |
| 15 | #include <asm/system_misc.h> | 15 | #include <asm/system_misc.h> |
| 16 | #include <mach/spear.h> | 16 | #include <mach/spear.h> |
| 17 | #include <mach/generic.h> | 17 | #include "generic.h" |
| 18 | 18 | ||
| 19 | #define SPEAR13XX_SYS_SW_RES (VA_MISC_BASE + 0x204) | 19 | #define SPEAR13XX_SYS_SW_RES (VA_MISC_BASE + 0x204) |
| 20 | void spear_restart(char mode, const char *cmd) | 20 | void spear_restart(char mode, const char *cmd) |
| @@ -26,7 +26,8 @@ void spear_restart(char mode, const char *cmd) | |||
| 26 | /* hardware reset, Use on-chip reset capability */ | 26 | /* hardware reset, Use on-chip reset capability */ |
| 27 | #ifdef CONFIG_ARCH_SPEAR13XX | 27 | #ifdef CONFIG_ARCH_SPEAR13XX |
| 28 | writel_relaxed(0x01, SPEAR13XX_SYS_SW_RES); | 28 | writel_relaxed(0x01, SPEAR13XX_SYS_SW_RES); |
| 29 | #else | 29 | #endif |
| 30 | #if defined(CONFIG_ARCH_SPEAR3XX) || defined(CONFIG_ARCH_SPEAR6XX) | ||
| 30 | sysctl_soft_reset((void __iomem *)VA_SPEAR_SYS_CTRL_BASE); | 31 | sysctl_soft_reset((void __iomem *)VA_SPEAR_SYS_CTRL_BASE); |
| 31 | #endif | 32 | #endif |
| 32 | } | 33 | } |
diff --git a/arch/arm/mach-spear13xx/spear1310.c b/arch/arm/mach-spear/spear1310.c index 56214d1076ef..9eaac2c881ea 100644 --- a/arch/arm/mach-spear13xx/spear1310.c +++ b/arch/arm/mach-spear/spear1310.c | |||
| @@ -19,46 +19,16 @@ | |||
| 19 | #include <linux/pata_arasan_cf_data.h> | 19 | #include <linux/pata_arasan_cf_data.h> |
| 20 | #include <asm/mach/arch.h> | 20 | #include <asm/mach/arch.h> |
| 21 | #include <asm/mach/map.h> | 21 | #include <asm/mach/map.h> |
| 22 | #include <mach/generic.h> | 22 | #include "generic.h" |
| 23 | #include <mach/spear.h> | 23 | #include <mach/spear.h> |
| 24 | 24 | ||
| 25 | /* Base addresses */ | 25 | /* Base addresses */ |
| 26 | #define SPEAR1310_SSP1_BASE UL(0x5D400000) | ||
| 27 | #define SPEAR1310_SATA0_BASE UL(0xB1000000) | ||
| 28 | #define SPEAR1310_SATA1_BASE UL(0xB1800000) | ||
| 29 | #define SPEAR1310_SATA2_BASE UL(0xB4000000) | ||
| 30 | |||
| 31 | #define SPEAR1310_RAS_GRP1_BASE UL(0xD8000000) | 26 | #define SPEAR1310_RAS_GRP1_BASE UL(0xD8000000) |
| 32 | #define VA_SPEAR1310_RAS_GRP1_BASE UL(0xFA000000) | 27 | #define VA_SPEAR1310_RAS_GRP1_BASE UL(0xFA000000) |
| 33 | #define SPEAR1310_RAS_BASE UL(0xD8400000) | ||
| 34 | #define VA_SPEAR1310_RAS_BASE IOMEM(UL(0xFA400000)) | ||
| 35 | |||
| 36 | static struct arasan_cf_pdata cf_pdata = { | ||
| 37 | .cf_if_clk = CF_IF_CLK_166M, | ||
| 38 | .quirk = CF_BROKEN_UDMA, | ||
| 39 | .dma_priv = &cf_dma_priv, | ||
| 40 | }; | ||
| 41 | |||
| 42 | /* ssp device registration */ | ||
| 43 | static struct pl022_ssp_controller ssp1_plat_data = { | ||
| 44 | .enable_dma = 0, | ||
| 45 | }; | ||
| 46 | |||
| 47 | /* Add SPEAr1310 auxdata to pass platform data */ | ||
| 48 | static struct of_dev_auxdata spear1310_auxdata_lookup[] __initdata = { | ||
| 49 | OF_DEV_AUXDATA("arasan,cf-spear1340", MCIF_CF_BASE, NULL, &cf_pdata), | ||
| 50 | OF_DEV_AUXDATA("snps,dma-spear1340", DMAC0_BASE, NULL, &dmac_plat_data), | ||
| 51 | OF_DEV_AUXDATA("snps,dma-spear1340", DMAC1_BASE, NULL, &dmac_plat_data), | ||
| 52 | OF_DEV_AUXDATA("arm,pl022", SSP_BASE, NULL, &pl022_plat_data), | ||
| 53 | |||
| 54 | OF_DEV_AUXDATA("arm,pl022", SPEAR1310_SSP1_BASE, NULL, &ssp1_plat_data), | ||
| 55 | {} | ||
| 56 | }; | ||
| 57 | 28 | ||
| 58 | static void __init spear1310_dt_init(void) | 29 | static void __init spear1310_dt_init(void) |
| 59 | { | 30 | { |
| 60 | of_platform_populate(NULL, of_default_bus_match_table, | 31 | of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); |
| 61 | spear1310_auxdata_lookup, NULL); | ||
| 62 | } | 32 | } |
| 63 | 33 | ||
| 64 | static const char * const spear1310_dt_board_compat[] = { | 34 | static const char * const spear1310_dt_board_compat[] = { |
diff --git a/arch/arm/mach-spear13xx/spear1340.c b/arch/arm/mach-spear/spear1340.c index 9a28beb2a113..a04a7fe76f71 100644 --- a/arch/arm/mach-spear13xx/spear1340.c +++ b/arch/arm/mach-spear/spear1340.c | |||
| @@ -16,17 +16,16 @@ | |||
| 16 | #include <linux/ahci_platform.h> | 16 | #include <linux/ahci_platform.h> |
| 17 | #include <linux/amba/serial.h> | 17 | #include <linux/amba/serial.h> |
| 18 | #include <linux/delay.h> | 18 | #include <linux/delay.h> |
| 19 | #include <linux/dw_dmac.h> | ||
| 20 | #include <linux/of_platform.h> | 19 | #include <linux/of_platform.h> |
| 21 | #include <linux/irqchip.h> | 20 | #include <linux/irqchip.h> |
| 22 | #include <asm/mach/arch.h> | 21 | #include <asm/mach/arch.h> |
| 23 | #include <mach/dma.h> | 22 | #include "generic.h" |
| 24 | #include <mach/generic.h> | ||
| 25 | #include <mach/spear.h> | 23 | #include <mach/spear.h> |
| 26 | 24 | ||
| 25 | /* FIXME: Move SATA PHY code into a standalone driver */ | ||
| 26 | |||
| 27 | /* Base addresses */ | 27 | /* Base addresses */ |
| 28 | #define SPEAR1340_SATA_BASE UL(0xB1000000) | 28 | #define SPEAR1340_SATA_BASE UL(0xB1000000) |
| 29 | #define SPEAR1340_UART1_BASE UL(0xB4100000) | ||
| 30 | 29 | ||
| 31 | /* Power Management Registers */ | 30 | /* Power Management Registers */ |
| 32 | #define SPEAR1340_PCM_CFG (VA_MISC_BASE + 0x100) | 31 | #define SPEAR1340_PCM_CFG (VA_MISC_BASE + 0x100) |
| @@ -78,28 +77,6 @@ | |||
| 78 | (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \ | 77 | (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \ |
| 79 | SPEAR1340_MIPHY_PLL_RATIO_TOP(25)) | 78 | SPEAR1340_MIPHY_PLL_RATIO_TOP(25)) |
| 80 | 79 | ||
| 81 | static struct dw_dma_slave uart1_dma_param[] = { | ||
| 82 | { | ||
| 83 | /* Tx */ | ||
| 84 | .cfg_hi = DWC_CFGH_DST_PER(SPEAR1340_DMA_REQ_UART1_TX), | ||
| 85 | .cfg_lo = 0, | ||
| 86 | .src_master = DMA_MASTER_MEMORY, | ||
| 87 | .dst_master = SPEAR1340_DMA_MASTER_UART1, | ||
| 88 | }, { | ||
| 89 | /* Rx */ | ||
| 90 | .cfg_hi = DWC_CFGH_SRC_PER(SPEAR1340_DMA_REQ_UART1_RX), | ||
| 91 | .cfg_lo = 0, | ||
| 92 | .src_master = SPEAR1340_DMA_MASTER_UART1, | ||
| 93 | .dst_master = DMA_MASTER_MEMORY, | ||
| 94 | } | ||
| 95 | }; | ||
| 96 | |||
| 97 | static struct amba_pl011_data uart1_data = { | ||
| 98 | .dma_filter = dw_dma_filter, | ||
| 99 | .dma_tx_param = &uart1_dma_param[0], | ||
| 100 | .dma_rx_param = &uart1_dma_param[1], | ||
| 101 | }; | ||
| 102 | |||
| 103 | /* SATA device registration */ | 80 | /* SATA device registration */ |
| 104 | static int sata_miphy_init(struct device *dev, void __iomem *addr) | 81 | static int sata_miphy_init(struct device *dev, void __iomem *addr) |
| 105 | { | 82 | { |
| @@ -158,14 +135,8 @@ static struct ahci_platform_data sata_pdata = { | |||
| 158 | 135 | ||
| 159 | /* Add SPEAr1340 auxdata to pass platform data */ | 136 | /* Add SPEAr1340 auxdata to pass platform data */ |
| 160 | static struct of_dev_auxdata spear1340_auxdata_lookup[] __initdata = { | 137 | static struct of_dev_auxdata spear1340_auxdata_lookup[] __initdata = { |
| 161 | OF_DEV_AUXDATA("arasan,cf-spear1340", MCIF_CF_BASE, NULL, &cf_dma_priv), | ||
| 162 | OF_DEV_AUXDATA("snps,dma-spear1340", DMAC0_BASE, NULL, &dmac_plat_data), | ||
| 163 | OF_DEV_AUXDATA("snps,dma-spear1340", DMAC1_BASE, NULL, &dmac_plat_data), | ||
| 164 | OF_DEV_AUXDATA("arm,pl022", SSP_BASE, NULL, &pl022_plat_data), | ||
| 165 | |||
| 166 | OF_DEV_AUXDATA("snps,spear-ahci", SPEAR1340_SATA_BASE, NULL, | 138 | OF_DEV_AUXDATA("snps,spear-ahci", SPEAR1340_SATA_BASE, NULL, |
| 167 | &sata_pdata), | 139 | &sata_pdata), |
| 168 | OF_DEV_AUXDATA("arm,pl011", SPEAR1340_UART1_BASE, NULL, &uart1_data), | ||
| 169 | {} | 140 | {} |
| 170 | }; | 141 | }; |
| 171 | 142 | ||
diff --git a/arch/arm/mach-spear13xx/spear13xx.c b/arch/arm/mach-spear/spear13xx.c index 25a10191b021..3621599c38ad 100644 --- a/arch/arm/mach-spear13xx/spear13xx.c +++ b/arch/arm/mach-spear/spear13xx.c | |||
| @@ -16,69 +16,12 @@ | |||
| 16 | #include <linux/amba/pl022.h> | 16 | #include <linux/amba/pl022.h> |
| 17 | #include <linux/clk.h> | 17 | #include <linux/clk.h> |
| 18 | #include <linux/clocksource.h> | 18 | #include <linux/clocksource.h> |
| 19 | #include <linux/dw_dmac.h> | ||
| 20 | #include <linux/err.h> | 19 | #include <linux/err.h> |
| 21 | #include <linux/of.h> | 20 | #include <linux/of.h> |
| 22 | #include <asm/hardware/cache-l2x0.h> | 21 | #include <asm/hardware/cache-l2x0.h> |
| 23 | #include <asm/mach/map.h> | 22 | #include <asm/mach/map.h> |
| 24 | #include <mach/dma.h> | ||
| 25 | #include <mach/generic.h> | ||
| 26 | #include <mach/spear.h> | 23 | #include <mach/spear.h> |
| 27 | 24 | #include "generic.h" | |
| 28 | /* common dw_dma filter routine to be used by peripherals */ | ||
| 29 | bool dw_dma_filter(struct dma_chan *chan, void *slave) | ||
| 30 | { | ||
| 31 | struct dw_dma_slave *dws = (struct dw_dma_slave *)slave; | ||
| 32 | |||
| 33 | if (chan->device->dev == dws->dma_dev) { | ||
| 34 | chan->private = slave; | ||
| 35 | return true; | ||
| 36 | } else { | ||
| 37 | return false; | ||
| 38 | } | ||
| 39 | } | ||
| 40 | |||
| 41 | /* ssp device registration */ | ||
| 42 | static struct dw_dma_slave ssp_dma_param[] = { | ||
| 43 | { | ||
| 44 | /* Tx */ | ||
| 45 | .cfg_hi = DWC_CFGH_DST_PER(DMA_REQ_SSP0_TX), | ||
| 46 | .cfg_lo = 0, | ||
| 47 | .src_master = DMA_MASTER_MEMORY, | ||
| 48 | .dst_master = DMA_MASTER_SSP0, | ||
| 49 | }, { | ||
| 50 | /* Rx */ | ||
| 51 | .cfg_hi = DWC_CFGH_SRC_PER(DMA_REQ_SSP0_RX), | ||
| 52 | .cfg_lo = 0, | ||
| 53 | .src_master = DMA_MASTER_SSP0, | ||
| 54 | .dst_master = DMA_MASTER_MEMORY, | ||
| 55 | } | ||
| 56 | }; | ||
| 57 | |||
| 58 | struct pl022_ssp_controller pl022_plat_data = { | ||
| 59 | .enable_dma = 1, | ||
| 60 | .dma_filter = dw_dma_filter, | ||
| 61 | .dma_rx_param = &ssp_dma_param[1], | ||
| 62 | .dma_tx_param = &ssp_dma_param[0], | ||
| 63 | }; | ||
| 64 | |||
| 65 | /* CF device registration */ | ||
| 66 | struct dw_dma_slave cf_dma_priv = { | ||
| 67 | .cfg_hi = 0, | ||
| 68 | .cfg_lo = 0, | ||
| 69 | .src_master = 0, | ||
| 70 | .dst_master = 0, | ||
| 71 | }; | ||
| 72 | |||
| 73 | /* dmac device registeration */ | ||
| 74 | struct dw_dma_platform_data dmac_plat_data = { | ||
| 75 | .nr_channels = 8, | ||
| 76 | .chan_allocation_order = CHAN_ALLOCATION_DESCENDING, | ||
| 77 | .chan_priority = CHAN_PRIORITY_DESCENDING, | ||
| 78 | .block_size = 4095U, | ||
| 79 | .nr_masters = 2, | ||
| 80 | .data_width = { 3, 3, 0, 0 }, | ||
| 81 | }; | ||
| 82 | 25 | ||
| 83 | void __init spear13xx_l2x0_init(void) | 26 | void __init spear13xx_l2x0_init(void) |
| 84 | { | 27 | { |
| @@ -145,9 +88,9 @@ void __init spear13xx_map_io(void) | |||
| 145 | static void __init spear13xx_clk_init(void) | 88 | static void __init spear13xx_clk_init(void) |
| 146 | { | 89 | { |
| 147 | if (of_machine_is_compatible("st,spear1310")) | 90 | if (of_machine_is_compatible("st,spear1310")) |
| 148 | spear1310_clk_init(); | 91 | spear1310_clk_init(VA_MISC_BASE, VA_SPEAR1310_RAS_BASE); |
| 149 | else if (of_machine_is_compatible("st,spear1340")) | 92 | else if (of_machine_is_compatible("st,spear1340")) |
| 150 | spear1340_clk_init(); | 93 | spear1340_clk_init(VA_MISC_BASE); |
| 151 | else | 94 | else |
| 152 | pr_err("%s: Unknown machine\n", __func__); | 95 | pr_err("%s: Unknown machine\n", __func__); |
| 153 | } | 96 | } |
diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear/spear300.c index bbc9b7e9c62c..bac56e845f7a 100644 --- a/arch/arm/mach-spear3xx/spear300.c +++ b/arch/arm/mach-spear/spear300.c | |||
| @@ -17,7 +17,7 @@ | |||
| 17 | #include <linux/irqchip.h> | 17 | #include <linux/irqchip.h> |
| 18 | #include <linux/of_platform.h> | 18 | #include <linux/of_platform.h> |
| 19 | #include <asm/mach/arch.h> | 19 | #include <asm/mach/arch.h> |
| 20 | #include <mach/generic.h> | 20 | #include "generic.h" |
| 21 | #include <mach/spear.h> | 21 | #include <mach/spear.h> |
| 22 | 22 | ||
| 23 | /* DMAC platform data's slave info */ | 23 | /* DMAC platform data's slave info */ |
| @@ -185,7 +185,7 @@ struct pl08x_channel_data spear300_dma_info[] = { | |||
| 185 | static struct of_dev_auxdata spear300_auxdata_lookup[] __initdata = { | 185 | static struct of_dev_auxdata spear300_auxdata_lookup[] __initdata = { |
| 186 | OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL, | 186 | OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL, |
| 187 | &pl022_plat_data), | 187 | &pl022_plat_data), |
| 188 | OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL, | 188 | OF_DEV_AUXDATA("arm,pl080", SPEAR_ICM3_DMA_BASE, NULL, |
| 189 | &pl080_plat_data), | 189 | &pl080_plat_data), |
| 190 | {} | 190 | {} |
| 191 | }; | 191 | }; |
diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear/spear310.c index c13a434a8195..6ffbc63d516d 100644 --- a/arch/arm/mach-spear3xx/spear310.c +++ b/arch/arm/mach-spear/spear310.c | |||
| @@ -18,7 +18,7 @@ | |||
| 18 | #include <linux/irqchip.h> | 18 | #include <linux/irqchip.h> |
| 19 | #include <linux/of_platform.h> | 19 | #include <linux/of_platform.h> |
| 20 | #include <asm/mach/arch.h> | 20 | #include <asm/mach/arch.h> |
| 21 | #include <mach/generic.h> | 21 | #include "generic.h" |
| 22 | #include <mach/spear.h> | 22 | #include <mach/spear.h> |
| 23 | 23 | ||
| 24 | #define SPEAR310_UART1_BASE UL(0xB2000000) | 24 | #define SPEAR310_UART1_BASE UL(0xB2000000) |
| @@ -217,7 +217,7 @@ static struct amba_pl011_data spear310_uart_data[] = { | |||
| 217 | static struct of_dev_auxdata spear310_auxdata_lookup[] __initdata = { | 217 | static struct of_dev_auxdata spear310_auxdata_lookup[] __initdata = { |
| 218 | OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL, | 218 | OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL, |
| 219 | &pl022_plat_data), | 219 | &pl022_plat_data), |
| 220 | OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL, | 220 | OF_DEV_AUXDATA("arm,pl080", SPEAR_ICM3_DMA_BASE, NULL, |
| 221 | &pl080_plat_data), | 221 | &pl080_plat_data), |
| 222 | OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART1_BASE, NULL, | 222 | OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART1_BASE, NULL, |
| 223 | &spear310_uart_data[0]), | 223 | &spear310_uart_data[0]), |
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear/spear320.c index e1c77079a3e5..6eb3eec65f96 100644 --- a/arch/arm/mach-spear3xx/spear320.c +++ b/arch/arm/mach-spear/spear320.c | |||
| @@ -19,7 +19,8 @@ | |||
| 19 | #include <linux/irqchip.h> | 19 | #include <linux/irqchip.h> |
| 20 | #include <linux/of_platform.h> | 20 | #include <linux/of_platform.h> |
| 21 | #include <asm/mach/arch.h> | 21 | #include <asm/mach/arch.h> |
| 22 | #include <mach/generic.h> | 22 | #include <asm/mach/map.h> |
| 23 | #include "generic.h" | ||
| 23 | #include <mach/spear.h> | 24 | #include <mach/spear.h> |
| 24 | 25 | ||
| 25 | #define SPEAR320_UART1_BASE UL(0xA3000000) | 26 | #define SPEAR320_UART1_BASE UL(0xA3000000) |
| @@ -222,7 +223,7 @@ static struct amba_pl011_data spear320_uart_data[] = { | |||
| 222 | static struct of_dev_auxdata spear320_auxdata_lookup[] __initdata = { | 223 | static struct of_dev_auxdata spear320_auxdata_lookup[] __initdata = { |
| 223 | OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL, | 224 | OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL, |
| 224 | &pl022_plat_data), | 225 | &pl022_plat_data), |
| 225 | OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL, | 226 | OF_DEV_AUXDATA("arm,pl080", SPEAR_ICM3_DMA_BASE, NULL, |
| 226 | &pl080_plat_data), | 227 | &pl080_plat_data), |
| 227 | OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP0_BASE, NULL, | 228 | OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP0_BASE, NULL, |
| 228 | &spear320_ssp_data[0]), | 229 | &spear320_ssp_data[0]), |
| @@ -253,7 +254,7 @@ static const char * const spear320_dt_board_compat[] = { | |||
| 253 | 254 | ||
| 254 | struct map_desc spear320_io_desc[] __initdata = { | 255 | struct map_desc spear320_io_desc[] __initdata = { |
| 255 | { | 256 | { |
| 256 | .virtual = VA_SPEAR320_SOC_CONFIG_BASE, | 257 | .virtual = (unsigned long)VA_SPEAR320_SOC_CONFIG_BASE, |
| 257 | .pfn = __phys_to_pfn(SPEAR320_SOC_CONFIG_BASE), | 258 | .pfn = __phys_to_pfn(SPEAR320_SOC_CONFIG_BASE), |
| 258 | .length = SZ_16M, | 259 | .length = SZ_16M, |
| 259 | .type = MT_DEVICE | 260 | .type = MT_DEVICE |
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear/spear3xx.c index d2b3937c4014..0227c97797cd 100644 --- a/arch/arm/mach-spear3xx/spear3xx.c +++ b/arch/arm/mach-spear/spear3xx.c | |||
| @@ -15,10 +15,13 @@ | |||
| 15 | 15 | ||
| 16 | #include <linux/amba/pl022.h> | 16 | #include <linux/amba/pl022.h> |
| 17 | #include <linux/amba/pl080.h> | 17 | #include <linux/amba/pl080.h> |
| 18 | #include <linux/clk.h> | ||
| 18 | #include <linux/io.h> | 19 | #include <linux/io.h> |
| 19 | #include <plat/pl080.h> | 20 | #include <asm/mach/map.h> |
| 20 | #include <mach/generic.h> | 21 | #include "pl080.h" |
| 22 | #include "generic.h" | ||
| 21 | #include <mach/spear.h> | 23 | #include <mach/spear.h> |
| 24 | #include <mach/misc_regs.h> | ||
| 22 | 25 | ||
| 23 | /* ssp device registration */ | 26 | /* ssp device registration */ |
| 24 | struct pl022_ssp_controller pl022_plat_data = { | 27 | struct pl022_ssp_controller pl022_plat_data = { |
| @@ -65,13 +68,13 @@ struct pl08x_platform_data pl080_plat_data = { | |||
| 65 | */ | 68 | */ |
| 66 | struct map_desc spear3xx_io_desc[] __initdata = { | 69 | struct map_desc spear3xx_io_desc[] __initdata = { |
| 67 | { | 70 | { |
| 68 | .virtual = VA_SPEAR3XX_ICM1_2_BASE, | 71 | .virtual = (unsigned long)VA_SPEAR_ICM1_2_BASE, |
| 69 | .pfn = __phys_to_pfn(SPEAR3XX_ICM1_2_BASE), | 72 | .pfn = __phys_to_pfn(SPEAR_ICM1_2_BASE), |
| 70 | .length = SZ_16M, | 73 | .length = SZ_16M, |
| 71 | .type = MT_DEVICE | 74 | .type = MT_DEVICE |
| 72 | }, { | 75 | }, { |
| 73 | .virtual = VA_SPEAR3XX_ICM3_SMI_CTRL_BASE, | 76 | .virtual = (unsigned long)VA_SPEAR_ICM3_SMI_CTRL_BASE, |
| 74 | .pfn = __phys_to_pfn(SPEAR3XX_ICM3_SMI_CTRL_BASE), | 77 | .pfn = __phys_to_pfn(SPEAR_ICM3_SMI_CTRL_BASE), |
| 75 | .length = SZ_16M, | 78 | .length = SZ_16M, |
| 76 | .type = MT_DEVICE | 79 | .type = MT_DEVICE |
| 77 | }, | 80 | }, |
| @@ -88,7 +91,7 @@ void __init spear3xx_timer_init(void) | |||
| 88 | char pclk_name[] = "pll3_clk"; | 91 | char pclk_name[] = "pll3_clk"; |
| 89 | struct clk *gpt_clk, *pclk; | 92 | struct clk *gpt_clk, *pclk; |
| 90 | 93 | ||
| 91 | spear3xx_clk_init(); | 94 | spear3xx_clk_init(MISC_BASE, VA_SPEAR320_SOC_CONFIG_BASE); |
| 92 | 95 | ||
| 93 | /* get the system timer clock */ | 96 | /* get the system timer clock */ |
| 94 | gpt_clk = clk_get_sys("gpt0", NULL); | 97 | gpt_clk = clk_get_sys("gpt0", NULL); |
diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear/spear6xx.c index 8904d8a52d84..ec8eefbbdfad 100644 --- a/arch/arm/mach-spear6xx/spear6xx.c +++ b/arch/arm/mach-spear/spear6xx.c | |||
| @@ -24,9 +24,10 @@ | |||
| 24 | #include <asm/mach/arch.h> | 24 | #include <asm/mach/arch.h> |
| 25 | #include <asm/mach/time.h> | 25 | #include <asm/mach/time.h> |
| 26 | #include <asm/mach/map.h> | 26 | #include <asm/mach/map.h> |
| 27 | #include <plat/pl080.h> | 27 | #include "pl080.h" |
| 28 | #include <mach/generic.h> | 28 | #include "generic.h" |
| 29 | #include <mach/spear.h> | 29 | #include <mach/spear.h> |
| 30 | #include <mach/misc_regs.h> | ||
| 30 | 31 | ||
| 31 | /* dmac device registration */ | 32 | /* dmac device registration */ |
| 32 | static struct pl08x_channel_data spear600_dma_info[] = { | 33 | static struct pl08x_channel_data spear600_dma_info[] = { |
| @@ -321,7 +322,7 @@ static struct pl08x_channel_data spear600_dma_info[] = { | |||
| 321 | }, | 322 | }, |
| 322 | }; | 323 | }; |
| 323 | 324 | ||
| 324 | struct pl08x_platform_data pl080_plat_data = { | 325 | static struct pl08x_platform_data spear6xx_pl080_plat_data = { |
| 325 | .memcpy_channel = { | 326 | .memcpy_channel = { |
| 326 | .bus_id = "memcpy", | 327 | .bus_id = "memcpy", |
| 327 | .cctl_memcpy = | 328 | .cctl_memcpy = |
| @@ -350,18 +351,18 @@ struct pl08x_platform_data pl080_plat_data = { | |||
| 350 | */ | 351 | */ |
| 351 | struct map_desc spear6xx_io_desc[] __initdata = { | 352 | struct map_desc spear6xx_io_desc[] __initdata = { |
| 352 | { | 353 | { |
| 353 | .virtual = VA_SPEAR6XX_ML_CPU_BASE, | 354 | .virtual = (unsigned long)VA_SPEAR6XX_ML_CPU_BASE, |
| 354 | .pfn = __phys_to_pfn(SPEAR6XX_ML_CPU_BASE), | 355 | .pfn = __phys_to_pfn(SPEAR_ICM3_ML1_2_BASE), |
| 355 | .length = 2 * SZ_16M, | 356 | .length = 2 * SZ_16M, |
| 356 | .type = MT_DEVICE | 357 | .type = MT_DEVICE |
| 357 | }, { | 358 | }, { |
| 358 | .virtual = VA_SPEAR6XX_ICM1_BASE, | 359 | .virtual = (unsigned long)VA_SPEAR_ICM1_2_BASE, |
| 359 | .pfn = __phys_to_pfn(SPEAR6XX_ICM1_BASE), | 360 | .pfn = __phys_to_pfn(SPEAR_ICM1_2_BASE), |
| 360 | .length = SZ_16M, | 361 | .length = SZ_16M, |
| 361 | .type = MT_DEVICE | 362 | .type = MT_DEVICE |
| 362 | }, { | 363 | }, { |
| 363 | .virtual = VA_SPEAR6XX_ICM3_SMI_CTRL_BASE, | 364 | .virtual = (unsigned long)VA_SPEAR_ICM3_SMI_CTRL_BASE, |
| 364 | .pfn = __phys_to_pfn(SPEAR6XX_ICM3_SMI_CTRL_BASE), | 365 | .pfn = __phys_to_pfn(SPEAR_ICM3_SMI_CTRL_BASE), |
| 365 | .length = SZ_16M, | 366 | .length = SZ_16M, |
| 366 | .type = MT_DEVICE | 367 | .type = MT_DEVICE |
| 367 | }, | 368 | }, |
| @@ -378,7 +379,7 @@ void __init spear6xx_timer_init(void) | |||
| 378 | char pclk_name[] = "pll3_clk"; | 379 | char pclk_name[] = "pll3_clk"; |
| 379 | struct clk *gpt_clk, *pclk; | 380 | struct clk *gpt_clk, *pclk; |
| 380 | 381 | ||
| 381 | spear6xx_clk_init(); | 382 | spear6xx_clk_init(MISC_BASE); |
| 382 | 383 | ||
| 383 | /* get the system timer clock */ | 384 | /* get the system timer clock */ |
| 384 | gpt_clk = clk_get_sys("gpt0", NULL); | 385 | gpt_clk = clk_get_sys("gpt0", NULL); |
| @@ -404,8 +405,8 @@ void __init spear6xx_timer_init(void) | |||
| 404 | 405 | ||
| 405 | /* Add auxdata to pass platform data */ | 406 | /* Add auxdata to pass platform data */ |
| 406 | struct of_dev_auxdata spear6xx_auxdata_lookup[] __initdata = { | 407 | struct of_dev_auxdata spear6xx_auxdata_lookup[] __initdata = { |
| 407 | OF_DEV_AUXDATA("arm,pl080", SPEAR6XX_ICM3_DMA_BASE, NULL, | 408 | OF_DEV_AUXDATA("arm,pl080", SPEAR_ICM3_DMA_BASE, NULL, |
| 408 | &pl080_plat_data), | 409 | &spear6xx_pl080_plat_data), |
| 409 | {} | 410 | {} |
| 410 | }; | 411 | }; |
| 411 | 412 | ||
diff --git a/arch/arm/plat-spear/time.c b/arch/arm/mach-spear/time.c index bd5c53cd6962..d449673e40f7 100644 --- a/arch/arm/plat-spear/time.c +++ b/arch/arm/mach-spear/time.c | |||
| @@ -23,7 +23,7 @@ | |||
| 23 | #include <linux/time.h> | 23 | #include <linux/time.h> |
| 24 | #include <linux/irq.h> | 24 | #include <linux/irq.h> |
| 25 | #include <asm/mach/time.h> | 25 | #include <asm/mach/time.h> |
| 26 | #include <mach/generic.h> | 26 | #include "generic.h" |
| 27 | 27 | ||
| 28 | /* | 28 | /* |
| 29 | * We would use TIMER0 and TIMER1 as clockevent and clocksource. | 29 | * We would use TIMER0 and TIMER1 as clockevent and clocksource. |
diff --git a/arch/arm/mach-spear13xx/Kconfig b/arch/arm/mach-spear13xx/Kconfig deleted file mode 100644 index eaadc66d96b3..000000000000 --- a/arch/arm/mach-spear13xx/Kconfig +++ /dev/null | |||
| @@ -1,20 +0,0 @@ | |||
| 1 | # | ||
| 2 | # SPEAr13XX Machine configuration file | ||
| 3 | # | ||
| 4 | |||
| 5 | if ARCH_SPEAR13XX | ||
| 6 | |||
| 7 | menu "SPEAr13xx Implementations" | ||
| 8 | config MACH_SPEAR1310 | ||
| 9 | bool "SPEAr1310 Machine support with Device Tree" | ||
| 10 | select PINCTRL_SPEAR1310 | ||
| 11 | help | ||
| 12 | Supports ST SPEAr1310 machine configured via the device-tree | ||
| 13 | |||
| 14 | config MACH_SPEAR1340 | ||
| 15 | bool "SPEAr1340 Machine support with Device Tree" | ||
| 16 | select PINCTRL_SPEAR1340 | ||
| 17 | help | ||
| 18 | Supports ST SPEAr1340 machine configured via the device-tree | ||
| 19 | endmenu | ||
| 20 | endif #ARCH_SPEAR13XX | ||
diff --git a/arch/arm/mach-spear13xx/Makefile b/arch/arm/mach-spear13xx/Makefile deleted file mode 100644 index 3435ea78c15d..000000000000 --- a/arch/arm/mach-spear13xx/Makefile +++ /dev/null | |||
| @@ -1,10 +0,0 @@ | |||
| 1 | # | ||
| 2 | # Makefile for SPEAr13XX machine series | ||
| 3 | # | ||
| 4 | |||
| 5 | obj-$(CONFIG_SMP) += headsmp.o platsmp.o | ||
| 6 | obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o | ||
| 7 | |||
| 8 | obj-$(CONFIG_ARCH_SPEAR13XX) += spear13xx.o | ||
| 9 | obj-$(CONFIG_MACH_SPEAR1310) += spear1310.o | ||
| 10 | obj-$(CONFIG_MACH_SPEAR1340) += spear1340.o | ||
diff --git a/arch/arm/mach-spear13xx/include/mach/debug-macro.S b/arch/arm/mach-spear13xx/include/mach/debug-macro.S deleted file mode 100644 index 9e3ae6bfe50d..000000000000 --- a/arch/arm/mach-spear13xx/include/mach/debug-macro.S +++ /dev/null | |||
| @@ -1,14 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-spear13xx/include/mach/debug-macro.S | ||
| 3 | * | ||
| 4 | * Debugging macro include header spear13xx machine family | ||
| 5 | * | ||
| 6 | * Copyright (C) 2012 ST Microelectronics | ||
| 7 | * Viresh Kumar <viresh.linux@gmail.com> | ||
| 8 | * | ||
| 9 | * This file is licensed under the terms of the GNU General Public | ||
| 10 | * License version 2. This program is licensed "as is" without any | ||
| 11 | * warranty of any kind, whether express or implied. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #include <plat/debug-macro.S> | ||
diff --git a/arch/arm/mach-spear13xx/include/mach/dma.h b/arch/arm/mach-spear13xx/include/mach/dma.h deleted file mode 100644 index d50bdb605925..000000000000 --- a/arch/arm/mach-spear13xx/include/mach/dma.h +++ /dev/null | |||
| @@ -1,128 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-spear13xx/include/mach/dma.h | ||
| 3 | * | ||
| 4 | * DMA information for SPEAr13xx machine family | ||
| 5 | * | ||
| 6 | * Copyright (C) 2012 ST Microelectronics | ||
| 7 | * Viresh Kumar <viresh.linux@gmail.com> | ||
| 8 | * | ||
| 9 | * This file is licensed under the terms of the GNU General Public | ||
| 10 | * License version 2. This program is licensed "as is" without any | ||
| 11 | * warranty of any kind, whether express or implied. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef __MACH_DMA_H | ||
| 15 | #define __MACH_DMA_H | ||
| 16 | |||
| 17 | /* request id of all the peripherals */ | ||
| 18 | enum dma_master_info { | ||
| 19 | /* Accessible from only one master */ | ||
| 20 | DMA_MASTER_MCIF = 0, | ||
| 21 | DMA_MASTER_FSMC = 1, | ||
| 22 | /* Accessible from both 0 & 1 */ | ||
| 23 | DMA_MASTER_MEMORY = 0, | ||
| 24 | DMA_MASTER_ADC = 0, | ||
| 25 | DMA_MASTER_UART0 = 0, | ||
| 26 | DMA_MASTER_SSP0 = 0, | ||
| 27 | DMA_MASTER_I2C0 = 0, | ||
| 28 | |||
| 29 | #ifdef CONFIG_MACH_SPEAR1310 | ||
| 30 | /* Accessible from only one master */ | ||
| 31 | SPEAR1310_DMA_MASTER_JPEG = 1, | ||
| 32 | |||
| 33 | /* Accessible from both 0 & 1 */ | ||
| 34 | SPEAR1310_DMA_MASTER_I2S = 0, | ||
| 35 | SPEAR1310_DMA_MASTER_UART1 = 0, | ||
| 36 | SPEAR1310_DMA_MASTER_UART2 = 0, | ||
| 37 | SPEAR1310_DMA_MASTER_UART3 = 0, | ||
| 38 | SPEAR1310_DMA_MASTER_UART4 = 0, | ||
| 39 | SPEAR1310_DMA_MASTER_UART5 = 0, | ||
| 40 | SPEAR1310_DMA_MASTER_I2C1 = 0, | ||
| 41 | SPEAR1310_DMA_MASTER_I2C2 = 0, | ||
| 42 | SPEAR1310_DMA_MASTER_I2C3 = 0, | ||
| 43 | SPEAR1310_DMA_MASTER_I2C4 = 0, | ||
| 44 | SPEAR1310_DMA_MASTER_I2C5 = 0, | ||
| 45 | SPEAR1310_DMA_MASTER_I2C6 = 0, | ||
| 46 | SPEAR1310_DMA_MASTER_I2C7 = 0, | ||
| 47 | SPEAR1310_DMA_MASTER_SSP1 = 0, | ||
| 48 | #endif | ||
| 49 | |||
| 50 | #ifdef CONFIG_MACH_SPEAR1340 | ||
| 51 | /* Accessible from only one master */ | ||
| 52 | SPEAR1340_DMA_MASTER_I2S_PLAY = 1, | ||
| 53 | SPEAR1340_DMA_MASTER_I2S_REC = 1, | ||
| 54 | SPEAR1340_DMA_MASTER_I2C1 = 1, | ||
| 55 | SPEAR1340_DMA_MASTER_UART1 = 1, | ||
| 56 | |||
| 57 | /* following are accessible from both master 0 & 1 */ | ||
| 58 | SPEAR1340_DMA_MASTER_SPDIF = 0, | ||
| 59 | SPEAR1340_DMA_MASTER_CAM = 1, | ||
| 60 | SPEAR1340_DMA_MASTER_VIDEO_IN = 0, | ||
| 61 | SPEAR1340_DMA_MASTER_MALI = 0, | ||
| 62 | #endif | ||
| 63 | }; | ||
| 64 | |||
| 65 | enum request_id { | ||
| 66 | DMA_REQ_ADC = 0, | ||
| 67 | DMA_REQ_SSP0_TX = 4, | ||
| 68 | DMA_REQ_SSP0_RX = 5, | ||
| 69 | DMA_REQ_UART0_TX = 6, | ||
| 70 | DMA_REQ_UART0_RX = 7, | ||
| 71 | DMA_REQ_I2C0_TX = 8, | ||
| 72 | DMA_REQ_I2C0_RX = 9, | ||
| 73 | |||
| 74 | #ifdef CONFIG_MACH_SPEAR1310 | ||
| 75 | SPEAR1310_DMA_REQ_FROM_JPEG = 2, | ||
| 76 | SPEAR1310_DMA_REQ_TO_JPEG = 3, | ||
| 77 | SPEAR1310_DMA_REQ_I2S_TX = 10, | ||
| 78 | SPEAR1310_DMA_REQ_I2S_RX = 11, | ||
| 79 | |||
| 80 | SPEAR1310_DMA_REQ_I2C1_RX = 0, | ||
| 81 | SPEAR1310_DMA_REQ_I2C1_TX = 1, | ||
| 82 | SPEAR1310_DMA_REQ_I2C2_RX = 2, | ||
| 83 | SPEAR1310_DMA_REQ_I2C2_TX = 3, | ||
| 84 | SPEAR1310_DMA_REQ_I2C3_RX = 4, | ||
| 85 | SPEAR1310_DMA_REQ_I2C3_TX = 5, | ||
| 86 | SPEAR1310_DMA_REQ_I2C4_RX = 6, | ||
| 87 | SPEAR1310_DMA_REQ_I2C4_TX = 7, | ||
| 88 | SPEAR1310_DMA_REQ_I2C5_RX = 8, | ||
| 89 | SPEAR1310_DMA_REQ_I2C5_TX = 9, | ||
| 90 | SPEAR1310_DMA_REQ_I2C6_RX = 10, | ||
| 91 | SPEAR1310_DMA_REQ_I2C6_TX = 11, | ||
| 92 | SPEAR1310_DMA_REQ_UART1_RX = 12, | ||
| 93 | SPEAR1310_DMA_REQ_UART1_TX = 13, | ||
| 94 | SPEAR1310_DMA_REQ_UART2_RX = 14, | ||
| 95 | SPEAR1310_DMA_REQ_UART2_TX = 15, | ||
| 96 | SPEAR1310_DMA_REQ_UART5_RX = 16, | ||
| 97 | SPEAR1310_DMA_REQ_UART5_TX = 17, | ||
| 98 | SPEAR1310_DMA_REQ_SSP1_RX = 18, | ||
| 99 | SPEAR1310_DMA_REQ_SSP1_TX = 19, | ||
| 100 | SPEAR1310_DMA_REQ_I2C7_RX = 20, | ||
| 101 | SPEAR1310_DMA_REQ_I2C7_TX = 21, | ||
| 102 | SPEAR1310_DMA_REQ_UART3_RX = 28, | ||
| 103 | SPEAR1310_DMA_REQ_UART3_TX = 29, | ||
| 104 | SPEAR1310_DMA_REQ_UART4_RX = 30, | ||
| 105 | SPEAR1310_DMA_REQ_UART4_TX = 31, | ||
| 106 | #endif | ||
| 107 | |||
| 108 | #ifdef CONFIG_MACH_SPEAR1340 | ||
| 109 | SPEAR1340_DMA_REQ_SPDIF_TX = 2, | ||
| 110 | SPEAR1340_DMA_REQ_SPDIF_RX = 3, | ||
| 111 | SPEAR1340_DMA_REQ_I2S_TX = 10, | ||
| 112 | SPEAR1340_DMA_REQ_I2S_RX = 11, | ||
| 113 | SPEAR1340_DMA_REQ_UART1_TX = 12, | ||
| 114 | SPEAR1340_DMA_REQ_UART1_RX = 13, | ||
| 115 | SPEAR1340_DMA_REQ_I2C1_TX = 14, | ||
| 116 | SPEAR1340_DMA_REQ_I2C1_RX = 15, | ||
| 117 | SPEAR1340_DMA_REQ_CAM0_EVEN = 0, | ||
| 118 | SPEAR1340_DMA_REQ_CAM0_ODD = 1, | ||
| 119 | SPEAR1340_DMA_REQ_CAM1_EVEN = 2, | ||
| 120 | SPEAR1340_DMA_REQ_CAM1_ODD = 3, | ||
| 121 | SPEAR1340_DMA_REQ_CAM2_EVEN = 4, | ||
| 122 | SPEAR1340_DMA_REQ_CAM2_ODD = 5, | ||
| 123 | SPEAR1340_DMA_REQ_CAM3_EVEN = 6, | ||
| 124 | SPEAR1340_DMA_REQ_CAM3_ODD = 7, | ||
| 125 | #endif | ||
| 126 | }; | ||
| 127 | |||
| 128 | #endif /* __MACH_DMA_H */ | ||
diff --git a/arch/arm/mach-spear13xx/include/mach/hardware.h b/arch/arm/mach-spear13xx/include/mach/hardware.h deleted file mode 100644 index 40a8c178f10d..000000000000 --- a/arch/arm/mach-spear13xx/include/mach/hardware.h +++ /dev/null | |||
| @@ -1 +0,0 @@ | |||
| 1 | /* empty */ | ||
diff --git a/arch/arm/mach-spear13xx/include/mach/irqs.h b/arch/arm/mach-spear13xx/include/mach/irqs.h deleted file mode 100644 index 271a62b4cd31..000000000000 --- a/arch/arm/mach-spear13xx/include/mach/irqs.h +++ /dev/null | |||
| @@ -1,20 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-spear13xx/include/mach/irqs.h | ||
| 3 | * | ||
| 4 | * IRQ helper macros for spear13xx machine family | ||
| 5 | * | ||
| 6 | * Copyright (C) 2012 ST Microelectronics | ||
| 7 | * Viresh Kumar <viresh.linux@gmail.com> | ||
| 8 | * | ||
| 9 | * This file is licensed under the terms of the GNU General Public | ||
| 10 | * License version 2. This program is licensed "as is" without any | ||
| 11 | * warranty of any kind, whether express or implied. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef __MACH_IRQS_H | ||
| 15 | #define __MACH_IRQS_H | ||
| 16 | |||
| 17 | #define IRQ_GIC_END 160 | ||
| 18 | #define NR_IRQS IRQ_GIC_END | ||
| 19 | |||
| 20 | #endif /* __MACH_IRQS_H */ | ||
diff --git a/arch/arm/mach-spear13xx/include/mach/spear.h b/arch/arm/mach-spear13xx/include/mach/spear.h deleted file mode 100644 index 7cfa6818865a..000000000000 --- a/arch/arm/mach-spear13xx/include/mach/spear.h +++ /dev/null | |||
| @@ -1,54 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-spear13xx/include/mach/spear.h | ||
| 3 | * | ||
| 4 | * spear13xx Machine family specific definition | ||
| 5 | * | ||
| 6 | * Copyright (C) 2012 ST Microelectronics | ||
| 7 | * Viresh Kumar <viresh.linux@gmail.com> | ||
| 8 | * | ||
| 9 | * This file is licensed under the terms of the GNU General Public | ||
| 10 | * License version 2. This program is licensed "as is" without any | ||
| 11 | * warranty of any kind, whether express or implied. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef __MACH_SPEAR13XX_H | ||
| 15 | #define __MACH_SPEAR13XX_H | ||
| 16 | |||
| 17 | #include <asm/memory.h> | ||
| 18 | |||
| 19 | #define PERIP_GRP2_BASE UL(0xB3000000) | ||
| 20 | #define VA_PERIP_GRP2_BASE IOMEM(0xFE000000) | ||
| 21 | #define MCIF_SDHCI_BASE UL(0xB3000000) | ||
| 22 | #define SYSRAM0_BASE UL(0xB3800000) | ||
| 23 | #define VA_SYSRAM0_BASE IOMEM(0xFE800000) | ||
| 24 | #define SYS_LOCATION (VA_SYSRAM0_BASE + 0x600) | ||
| 25 | |||
| 26 | #define PERIP_GRP1_BASE UL(0xE0000000) | ||
| 27 | #define VA_PERIP_GRP1_BASE IOMEM(0xFD000000) | ||
| 28 | #define UART_BASE UL(0xE0000000) | ||
| 29 | #define VA_UART_BASE IOMEM(0xFD000000) | ||
| 30 | #define SSP_BASE UL(0xE0100000) | ||
| 31 | #define MISC_BASE UL(0xE0700000) | ||
| 32 | #define VA_MISC_BASE IOMEM(0xFD700000) | ||
| 33 | |||
| 34 | #define A9SM_AND_MPMC_BASE UL(0xEC000000) | ||
| 35 | #define VA_A9SM_AND_MPMC_BASE IOMEM(0xFC000000) | ||
| 36 | |||
| 37 | /* A9SM peripheral offsets */ | ||
| 38 | #define A9SM_PERIP_BASE UL(0xEC800000) | ||
| 39 | #define VA_A9SM_PERIP_BASE IOMEM(0xFC800000) | ||
| 40 | #define VA_SCU_BASE (VA_A9SM_PERIP_BASE + 0x00) | ||
| 41 | |||
| 42 | #define L2CC_BASE UL(0xED000000) | ||
| 43 | #define VA_L2CC_BASE IOMEM(UL(0xFB000000)) | ||
| 44 | |||
| 45 | /* others */ | ||
| 46 | #define DMAC0_BASE UL(0xEA800000) | ||
| 47 | #define DMAC1_BASE UL(0xEB000000) | ||
| 48 | #define MCIF_CF_BASE UL(0xB2800000) | ||
| 49 | |||
| 50 | /* Debug uart for linux, will be used for debug and uncompress messages */ | ||
| 51 | #define SPEAR_DBG_UART_BASE UART_BASE | ||
| 52 | #define VA_SPEAR_DBG_UART_BASE VA_UART_BASE | ||
| 53 | |||
| 54 | #endif /* __MACH_SPEAR13XX_H */ | ||
diff --git a/arch/arm/mach-spear13xx/include/mach/timex.h b/arch/arm/mach-spear13xx/include/mach/timex.h deleted file mode 100644 index 3a58b8284a6a..000000000000 --- a/arch/arm/mach-spear13xx/include/mach/timex.h +++ /dev/null | |||
| @@ -1,19 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-spear3xx/include/mach/timex.h | ||
| 3 | * | ||
| 4 | * SPEAr3XX machine family specific timex definitions | ||
| 5 | * | ||
| 6 | * Copyright (C) 2012 ST Microelectronics | ||
| 7 | * Viresh Kumar <viresh.linux@gmail.com> | ||
| 8 | * | ||
| 9 | * This file is licensed under the terms of the GNU General Public | ||
| 10 | * License version 2. This program is licensed "as is" without any | ||
| 11 | * warranty of any kind, whether express or implied. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef __MACH_TIMEX_H | ||
| 15 | #define __MACH_TIMEX_H | ||
| 16 | |||
| 17 | #include <plat/timex.h> | ||
| 18 | |||
| 19 | #endif /* __MACH_TIMEX_H */ | ||
diff --git a/arch/arm/mach-spear13xx/include/mach/uncompress.h b/arch/arm/mach-spear13xx/include/mach/uncompress.h deleted file mode 100644 index 70fe72f05dea..000000000000 --- a/arch/arm/mach-spear13xx/include/mach/uncompress.h +++ /dev/null | |||
| @@ -1,19 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-spear13xx/include/mach/uncompress.h | ||
| 3 | * | ||
| 4 | * Serial port stubs for kernel decompress status messages | ||
| 5 | * | ||
| 6 | * Copyright (C) 2012 ST Microelectronics | ||
| 7 | * Viresh Kumar <viresh.linux@gmail.com> | ||
| 8 | * | ||
| 9 | * This file is licensed under the terms of the GNU General Public | ||
| 10 | * License version 2. This program is licensed "as is" without any | ||
| 11 | * warranty of any kind, whether express or implied. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef __MACH_UNCOMPRESS_H | ||
| 15 | #define __MACH_UNCOMPRESS_H | ||
| 16 | |||
| 17 | #include <plat/uncompress.h> | ||
| 18 | |||
| 19 | #endif /* __MACH_UNCOMPRESS_H */ | ||
diff --git a/arch/arm/mach-spear3xx/Kconfig b/arch/arm/mach-spear3xx/Kconfig deleted file mode 100644 index 8bd37291fa4f..000000000000 --- a/arch/arm/mach-spear3xx/Kconfig +++ /dev/null | |||
| @@ -1,26 +0,0 @@ | |||
| 1 | # | ||
| 2 | # SPEAr3XX Machine configuration file | ||
| 3 | # | ||
| 4 | |||
| 5 | if ARCH_SPEAR3XX | ||
| 6 | |||
| 7 | menu "SPEAr3xx Implementations" | ||
| 8 | config MACH_SPEAR300 | ||
| 9 | bool "SPEAr300 Machine support with Device Tree" | ||
| 10 | select PINCTRL_SPEAR300 | ||
| 11 | help | ||
| 12 | Supports ST SPEAr300 machine configured via the device-tree | ||
| 13 | |||
| 14 | config MACH_SPEAR310 | ||
| 15 | bool "SPEAr310 Machine support with Device Tree" | ||
| 16 | select PINCTRL_SPEAR310 | ||
| 17 | help | ||
| 18 | Supports ST SPEAr310 machine configured via the device-tree | ||
| 19 | |||
| 20 | config MACH_SPEAR320 | ||
| 21 | bool "SPEAr320 Machine support with Device Tree" | ||
| 22 | select PINCTRL_SPEAR320 | ||
| 23 | help | ||
| 24 | Supports ST SPEAr320 machine configured via the device-tree | ||
| 25 | endmenu | ||
| 26 | endif #ARCH_SPEAR3XX | ||
diff --git a/arch/arm/mach-spear3xx/Makefile b/arch/arm/mach-spear3xx/Makefile deleted file mode 100644 index 8d12faa178fd..000000000000 --- a/arch/arm/mach-spear3xx/Makefile +++ /dev/null | |||
| @@ -1,15 +0,0 @@ | |||
| 1 | # | ||
| 2 | # Makefile for SPEAr3XX machine series | ||
| 3 | # | ||
| 4 | |||
| 5 | # common files | ||
| 6 | obj-$(CONFIG_ARCH_SPEAR3XX) += spear3xx.o | ||
| 7 | |||
| 8 | # spear300 specific files | ||
| 9 | obj-$(CONFIG_MACH_SPEAR300) += spear300.o | ||
| 10 | |||
| 11 | # spear310 specific files | ||
| 12 | obj-$(CONFIG_MACH_SPEAR310) += spear310.o | ||
| 13 | |||
| 14 | # spear320 specific files | ||
| 15 | obj-$(CONFIG_MACH_SPEAR320) += spear320.o | ||
diff --git a/arch/arm/mach-spear3xx/Makefile.boot b/arch/arm/mach-spear3xx/Makefile.boot deleted file mode 100644 index 4674a4c221db..000000000000 --- a/arch/arm/mach-spear3xx/Makefile.boot +++ /dev/null | |||
| @@ -1,3 +0,0 @@ | |||
| 1 | zreladdr-y += 0x00008000 | ||
| 2 | params_phys-y := 0x00000100 | ||
| 3 | initrd_phys-y := 0x00800000 | ||
diff --git a/arch/arm/mach-spear3xx/include/mach/debug-macro.S b/arch/arm/mach-spear3xx/include/mach/debug-macro.S deleted file mode 100644 index 0a6381fad5d9..000000000000 --- a/arch/arm/mach-spear3xx/include/mach/debug-macro.S +++ /dev/null | |||
| @@ -1,14 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-spear3xx/include/mach/debug-macro.S | ||
| 3 | * | ||
| 4 | * Debugging macro include header spear3xx machine family | ||
| 5 | * | ||
| 6 | * Copyright (C) 2009 ST Microelectronics | ||
| 7 | * Viresh Kumar<viresh.linux@gmail.com> | ||
| 8 | * | ||
| 9 | * This file is licensed under the terms of the GNU General Public | ||
| 10 | * License version 2. This program is licensed "as is" without any | ||
| 11 | * warranty of any kind, whether express or implied. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #include <plat/debug-macro.S> | ||
diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h deleted file mode 100644 index df310799e416..000000000000 --- a/arch/arm/mach-spear3xx/include/mach/generic.h +++ /dev/null | |||
| @@ -1,36 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-spear3xx/generic.h | ||
| 3 | * | ||
| 4 | * SPEAr3XX machine family generic header file | ||
| 5 | * | ||
| 6 | * Copyright (C) 2009 ST Microelectronics | ||
| 7 | * Viresh Kumar<viresh.linux@gmail.com> | ||
| 8 | * | ||
| 9 | * This file is licensed under the terms of the GNU General Public | ||
| 10 | * License version 2. This program is licensed "as is" without any | ||
| 11 | * warranty of any kind, whether express or implied. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef __MACH_GENERIC_H | ||
| 15 | #define __MACH_GENERIC_H | ||
| 16 | |||
| 17 | #include <linux/amba/pl08x.h> | ||
| 18 | #include <linux/init.h> | ||
| 19 | #include <linux/platform_device.h> | ||
| 20 | #include <linux/amba/bus.h> | ||
| 21 | #include <asm/mach/time.h> | ||
| 22 | #include <asm/mach/map.h> | ||
| 23 | |||
| 24 | /* Add spear3xx family device structure declarations here */ | ||
| 25 | extern void spear3xx_timer_init(void); | ||
| 26 | extern struct pl022_ssp_controller pl022_plat_data; | ||
| 27 | extern struct pl08x_platform_data pl080_plat_data; | ||
| 28 | |||
| 29 | /* Add spear3xx family function declarations here */ | ||
| 30 | void __init spear_setup_of_timer(void); | ||
| 31 | void __init spear3xx_clk_init(void); | ||
| 32 | void __init spear3xx_map_io(void); | ||
| 33 | |||
| 34 | void spear_restart(char, const char *); | ||
| 35 | |||
| 36 | #endif /* __MACH_GENERIC_H */ | ||
diff --git a/arch/arm/mach-spear3xx/include/mach/hardware.h b/arch/arm/mach-spear3xx/include/mach/hardware.h deleted file mode 100644 index 40a8c178f10d..000000000000 --- a/arch/arm/mach-spear3xx/include/mach/hardware.h +++ /dev/null | |||
| @@ -1 +0,0 @@ | |||
| 1 | /* empty */ | ||
diff --git a/arch/arm/mach-spear3xx/include/mach/irqs.h b/arch/arm/mach-spear3xx/include/mach/irqs.h deleted file mode 100644 index f95e5b2b6686..000000000000 --- a/arch/arm/mach-spear3xx/include/mach/irqs.h +++ /dev/null | |||
| @@ -1,19 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-spear3xx/include/mach/irqs.h | ||
| 3 | * | ||
| 4 | * IRQ helper macros for SPEAr3xx machine family | ||
| 5 | * | ||
| 6 | * Copyright (C) 2009 ST Microelectronics | ||
| 7 | * Viresh Kumar <viresh.linux@gmail.com> | ||
| 8 | * | ||
| 9 | * This file is licensed under the terms of the GNU General Public | ||
| 10 | * License version 2. This program is licensed "as is" without any | ||
| 11 | * warranty of any kind, whether express or implied. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef __MACH_IRQS_H | ||
| 15 | #define __MACH_IRQS_H | ||
| 16 | |||
| 17 | #define NR_IRQS 256 | ||
| 18 | |||
| 19 | #endif /* __MACH_IRQS_H */ | ||
diff --git a/arch/arm/mach-spear3xx/include/mach/spear.h b/arch/arm/mach-spear3xx/include/mach/spear.h deleted file mode 100644 index 8cca95193d4d..000000000000 --- a/arch/arm/mach-spear3xx/include/mach/spear.h +++ /dev/null | |||
| @@ -1,60 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-spear3xx/include/mach/spear.h | ||
| 3 | * | ||
| 4 | * SPEAr3xx Machine family specific definition | ||
| 5 | * | ||
| 6 | * Copyright (C) 2009 ST Microelectronics | ||
| 7 | * Viresh Kumar <viresh.linux@gmail.com> | ||
| 8 | * | ||
| 9 | * This file is licensed under the terms of the GNU General Public | ||
| 10 | * License version 2. This program is licensed "as is" without any | ||
| 11 | * warranty of any kind, whether express or implied. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef __MACH_SPEAR3XX_H | ||
| 15 | #define __MACH_SPEAR3XX_H | ||
| 16 | |||
| 17 | #include <asm/memory.h> | ||
| 18 | |||
| 19 | /* ICM1 - Low speed connection */ | ||
| 20 | #define SPEAR3XX_ICM1_2_BASE UL(0xD0000000) | ||
| 21 | #define VA_SPEAR3XX_ICM1_2_BASE UL(0xFD000000) | ||
| 22 | #define SPEAR3XX_ICM1_UART_BASE UL(0xD0000000) | ||
| 23 | #define VA_SPEAR3XX_ICM1_UART_BASE (VA_SPEAR3XX_ICM1_2_BASE | SPEAR3XX_ICM1_UART_BASE) | ||
| 24 | #define SPEAR3XX_ICM1_SSP_BASE UL(0xD0100000) | ||
| 25 | |||
| 26 | /* ML1 - Multi Layer CPU Subsystem */ | ||
| 27 | #define SPEAR3XX_ICM3_ML1_2_BASE UL(0xF0000000) | ||
| 28 | #define VA_SPEAR6XX_ML_CPU_BASE UL(0xF0000000) | ||
| 29 | |||
| 30 | /* ICM3 - Basic Subsystem */ | ||
| 31 | #define SPEAR3XX_ICM3_SMI_CTRL_BASE UL(0xFC000000) | ||
| 32 | #define VA_SPEAR3XX_ICM3_SMI_CTRL_BASE UL(0xFC000000) | ||
| 33 | #define SPEAR3XX_ICM3_DMA_BASE UL(0xFC400000) | ||
| 34 | #define SPEAR3XX_ICM3_SYS_CTRL_BASE UL(0xFCA00000) | ||
| 35 | #define VA_SPEAR3XX_ICM3_SYS_CTRL_BASE (VA_SPEAR3XX_ICM3_SMI_CTRL_BASE | SPEAR3XX_ICM3_SYS_CTRL_BASE) | ||
| 36 | #define SPEAR3XX_ICM3_MISC_REG_BASE UL(0xFCA80000) | ||
| 37 | #define VA_SPEAR3XX_ICM3_MISC_REG_BASE (VA_SPEAR3XX_ICM3_SMI_CTRL_BASE | SPEAR3XX_ICM3_MISC_REG_BASE) | ||
| 38 | |||
| 39 | /* Debug uart for linux, will be used for debug and uncompress messages */ | ||
| 40 | #define SPEAR_DBG_UART_BASE SPEAR3XX_ICM1_UART_BASE | ||
| 41 | #define VA_SPEAR_DBG_UART_BASE VA_SPEAR3XX_ICM1_UART_BASE | ||
| 42 | |||
| 43 | /* Sysctl base for spear platform */ | ||
| 44 | #define SPEAR_SYS_CTRL_BASE SPEAR3XX_ICM3_SYS_CTRL_BASE | ||
| 45 | #define VA_SPEAR_SYS_CTRL_BASE VA_SPEAR3XX_ICM3_SYS_CTRL_BASE | ||
| 46 | |||
| 47 | /* SPEAr320 Macros */ | ||
| 48 | #define SPEAR320_SOC_CONFIG_BASE UL(0xB3000000) | ||
| 49 | #define VA_SPEAR320_SOC_CONFIG_BASE UL(0xFE000000) | ||
| 50 | #define SPEAR320_CONTROL_REG IOMEM(VA_SPEAR320_SOC_CONFIG_BASE) | ||
| 51 | #define SPEAR320_EXT_CTRL_REG IOMEM(VA_SPEAR320_SOC_CONFIG_BASE + 0x0018) | ||
| 52 | #define SPEAR320_UARTX_PCLK_MASK 0x1 | ||
| 53 | #define SPEAR320_UART2_PCLK_SHIFT 8 | ||
| 54 | #define SPEAR320_UART3_PCLK_SHIFT 9 | ||
| 55 | #define SPEAR320_UART4_PCLK_SHIFT 10 | ||
| 56 | #define SPEAR320_UART5_PCLK_SHIFT 11 | ||
| 57 | #define SPEAR320_UART6_PCLK_SHIFT 12 | ||
| 58 | #define SPEAR320_RS485_PCLK_SHIFT 13 | ||
| 59 | |||
| 60 | #endif /* __MACH_SPEAR3XX_H */ | ||
diff --git a/arch/arm/mach-spear3xx/include/mach/timex.h b/arch/arm/mach-spear3xx/include/mach/timex.h deleted file mode 100644 index 9f5d08bd0c44..000000000000 --- a/arch/arm/mach-spear3xx/include/mach/timex.h +++ /dev/null | |||
| @@ -1,19 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-spear3xx/include/mach/timex.h | ||
| 3 | * | ||
| 4 | * SPEAr3XX machine family specific timex definitions | ||
| 5 | * | ||
| 6 | * Copyright (C) 2009 ST Microelectronics | ||
| 7 | * Viresh Kumar <viresh.linux@gmail.com> | ||
| 8 | * | ||
| 9 | * This file is licensed under the terms of the GNU General Public | ||
| 10 | * License version 2. This program is licensed "as is" without any | ||
| 11 | * warranty of any kind, whether express or implied. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef __MACH_TIMEX_H | ||
| 15 | #define __MACH_TIMEX_H | ||
| 16 | |||
| 17 | #include <plat/timex.h> | ||
| 18 | |||
| 19 | #endif /* __MACH_TIMEX_H */ | ||
diff --git a/arch/arm/mach-spear3xx/include/mach/uncompress.h b/arch/arm/mach-spear3xx/include/mach/uncompress.h deleted file mode 100644 index b909b011f7c8..000000000000 --- a/arch/arm/mach-spear3xx/include/mach/uncompress.h +++ /dev/null | |||
| @@ -1,19 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-spear3xx/include/mach/uncompress.h | ||
| 3 | * | ||
| 4 | * Serial port stubs for kernel decompress status messages | ||
| 5 | * | ||
| 6 | * Copyright (C) 2009 ST Microelectronics | ||
| 7 | * Viresh Kumar <viresh.linux@gmail.com> | ||
| 8 | * | ||
| 9 | * This file is licensed under the terms of the GNU General Public | ||
| 10 | * License version 2. This program is licensed "as is" without any | ||
| 11 | * warranty of any kind, whether express or implied. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef __MACH_UNCOMPRESS_H | ||
| 15 | #define __MACH_UNCOMPRESS_H | ||
| 16 | |||
| 17 | #include <plat/uncompress.h> | ||
| 18 | |||
| 19 | #endif /* __MACH_UNCOMPRESS_H */ | ||
diff --git a/arch/arm/mach-spear6xx/Kconfig b/arch/arm/mach-spear6xx/Kconfig deleted file mode 100644 index 339f397dea70..000000000000 --- a/arch/arm/mach-spear6xx/Kconfig +++ /dev/null | |||
| @@ -1,10 +0,0 @@ | |||
| 1 | # | ||
| 2 | # SPEAr6XX Machine configuration file | ||
| 3 | # | ||
| 4 | |||
| 5 | config MACH_SPEAR600 | ||
| 6 | def_bool y | ||
| 7 | depends on ARCH_SPEAR6XX | ||
| 8 | select USE_OF | ||
| 9 | help | ||
| 10 | Supports ST SPEAr600 boards configured via the device-tree | ||
diff --git a/arch/arm/mach-spear6xx/Makefile b/arch/arm/mach-spear6xx/Makefile deleted file mode 100644 index 898831d93f37..000000000000 --- a/arch/arm/mach-spear6xx/Makefile +++ /dev/null | |||
| @@ -1,6 +0,0 @@ | |||
| 1 | # | ||
| 2 | # Makefile for SPEAr6XX machine series | ||
| 3 | # | ||
| 4 | |||
| 5 | # common files | ||
| 6 | obj-y += spear6xx.o | ||
diff --git a/arch/arm/mach-spear6xx/Makefile.boot b/arch/arm/mach-spear6xx/Makefile.boot deleted file mode 100644 index 4674a4c221db..000000000000 --- a/arch/arm/mach-spear6xx/Makefile.boot +++ /dev/null | |||
| @@ -1,3 +0,0 @@ | |||
| 1 | zreladdr-y += 0x00008000 | ||
| 2 | params_phys-y := 0x00000100 | ||
| 3 | initrd_phys-y := 0x00800000 | ||
diff --git a/arch/arm/mach-spear6xx/include/mach/debug-macro.S b/arch/arm/mach-spear6xx/include/mach/debug-macro.S deleted file mode 100644 index 0f3ea39edd96..000000000000 --- a/arch/arm/mach-spear6xx/include/mach/debug-macro.S +++ /dev/null | |||
| @@ -1,14 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-spear6xx/include/mach/debug-macro.S | ||
| 3 | * | ||
| 4 | * Debugging macro include header for SPEAr6xx machine family | ||
| 5 | * | ||
| 6 | * Copyright (C) 2009 ST Microelectronics | ||
| 7 | * Rajeev Kumar<rajeev-dlh.kumar@st.com> | ||
| 8 | * | ||
| 9 | * This file is licensed under the terms of the GNU General Public | ||
| 10 | * License version 2. This program is licensed "as is" without any | ||
| 11 | * warranty of any kind, whether express or implied. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #include <plat/debug-macro.S> | ||
diff --git a/arch/arm/mach-spear6xx/include/mach/generic.h b/arch/arm/mach-spear6xx/include/mach/generic.h deleted file mode 100644 index 65514b159370..000000000000 --- a/arch/arm/mach-spear6xx/include/mach/generic.h +++ /dev/null | |||
| @@ -1,23 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-spear6xx/include/mach/generic.h | ||
| 3 | * | ||
| 4 | * SPEAr6XX machine family specific generic header file | ||
| 5 | * | ||
| 6 | * Copyright (C) 2009 ST Microelectronics | ||
| 7 | * Rajeev Kumar<rajeev-dlh.kumar@st.com> | ||
| 8 | * | ||
| 9 | * This file is licensed under the terms of the GNU General Public | ||
| 10 | * License version 2. This program is licensed "as is" without any | ||
| 11 | * warranty of any kind, whether express or implied. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef __MACH_GENERIC_H | ||
| 15 | #define __MACH_GENERIC_H | ||
| 16 | |||
| 17 | #include <linux/init.h> | ||
| 18 | |||
| 19 | void __init spear_setup_of_timer(void); | ||
| 20 | void spear_restart(char, const char *); | ||
| 21 | void __init spear6xx_clk_init(void); | ||
| 22 | |||
| 23 | #endif /* __MACH_GENERIC_H */ | ||
diff --git a/arch/arm/mach-spear6xx/include/mach/hardware.h b/arch/arm/mach-spear6xx/include/mach/hardware.h deleted file mode 100644 index 40a8c178f10d..000000000000 --- a/arch/arm/mach-spear6xx/include/mach/hardware.h +++ /dev/null | |||
| @@ -1 +0,0 @@ | |||
| 1 | /* empty */ | ||
diff --git a/arch/arm/mach-spear6xx/include/mach/misc_regs.h b/arch/arm/mach-spear6xx/include/mach/misc_regs.h deleted file mode 100644 index c34acc201d34..000000000000 --- a/arch/arm/mach-spear6xx/include/mach/misc_regs.h +++ /dev/null | |||
| @@ -1,22 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-spear6xx/include/mach/misc_regs.h | ||
| 3 | * | ||
| 4 | * Miscellaneous registers definitions for SPEAr6xx machine family | ||
| 5 | * | ||
| 6 | * Copyright (C) 2009 ST Microelectronics | ||
| 7 | * Viresh Kumar <viresh.linux@gmail.com> | ||
| 8 | * | ||
| 9 | * This file is licensed under the terms of the GNU General Public | ||
| 10 | * License version 2. This program is licensed "as is" without any | ||
| 11 | * warranty of any kind, whether express or implied. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef __MACH_MISC_REGS_H | ||
| 15 | #define __MACH_MISC_REGS_H | ||
| 16 | |||
| 17 | #include <mach/spear.h> | ||
| 18 | |||
| 19 | #define MISC_BASE IOMEM(VA_SPEAR6XX_ICM3_MISC_REG_BASE) | ||
| 20 | #define DMA_CHN_CFG (MISC_BASE + 0x0A0) | ||
| 21 | |||
| 22 | #endif /* __MACH_MISC_REGS_H */ | ||
diff --git a/arch/arm/mach-spear6xx/include/mach/spear.h b/arch/arm/mach-spear6xx/include/mach/spear.h deleted file mode 100644 index cb8ed2f4dc85..000000000000 --- a/arch/arm/mach-spear6xx/include/mach/spear.h +++ /dev/null | |||
| @@ -1,46 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-spear6xx/include/mach/spear.h | ||
| 3 | * | ||
| 4 | * SPEAr6xx Machine family specific definition | ||
| 5 | * | ||
| 6 | * Copyright (C) 2009 ST Microelectronics | ||
| 7 | * Rajeev Kumar<rajeev-dlh.kumar@st.com> | ||
| 8 | * | ||
| 9 | * This file is licensed under the terms of the GNU General Public | ||
| 10 | * License version 2. This program is licensed "as is" without any | ||
| 11 | * warranty of any kind, whether express or implied. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef __MACH_SPEAR6XX_H | ||
| 15 | #define __MACH_SPEAR6XX_H | ||
| 16 | |||
| 17 | #include <asm/memory.h> | ||
| 18 | |||
| 19 | /* ICM1 - Low speed connection */ | ||
| 20 | #define SPEAR6XX_ICM1_BASE UL(0xD0000000) | ||
| 21 | #define VA_SPEAR6XX_ICM1_BASE UL(0xFD000000) | ||
| 22 | #define SPEAR6XX_ICM1_UART0_BASE UL(0xD0000000) | ||
| 23 | #define VA_SPEAR6XX_ICM1_UART0_BASE (VA_SPEAR6XX_ICM1_2_BASE | SPEAR6XX_ICM1_UART0_BASE) | ||
| 24 | |||
| 25 | /* ML-1, 2 - Multi Layer CPU Subsystem */ | ||
| 26 | #define SPEAR6XX_ML_CPU_BASE UL(0xF0000000) | ||
| 27 | #define VA_SPEAR6XX_ML_CPU_BASE UL(0xF0000000) | ||
| 28 | |||
| 29 | /* ICM3 - Basic Subsystem */ | ||
| 30 | #define SPEAR6XX_ICM3_SMI_CTRL_BASE UL(0xFC000000) | ||
| 31 | #define VA_SPEAR6XX_ICM3_SMI_CTRL_BASE UL(0xFC000000) | ||
| 32 | #define SPEAR6XX_ICM3_DMA_BASE UL(0xFC400000) | ||
| 33 | #define SPEAR6XX_ICM3_SYS_CTRL_BASE UL(0xFCA00000) | ||
| 34 | #define VA_SPEAR6XX_ICM3_SYS_CTRL_BASE (VA_SPEAR6XX_ICM3_SMI_CTRL_BASE | SPEAR6XX_ICM3_SYS_CTRL_BASE) | ||
| 35 | #define SPEAR6XX_ICM3_MISC_REG_BASE UL(0xFCA80000) | ||
| 36 | #define VA_SPEAR6XX_ICM3_MISC_REG_BASE (VA_SPEAR6XX_ICM3_SMI_CTRL_BASE | SPEAR6XX_ICM3_MISC_REG_BASE) | ||
| 37 | |||
| 38 | /* Debug uart for linux, will be used for debug and uncompress messages */ | ||
| 39 | #define SPEAR_DBG_UART_BASE SPEAR6XX_ICM1_UART0_BASE | ||
| 40 | #define VA_SPEAR_DBG_UART_BASE VA_SPEAR6XX_ICM1_UART0_BASE | ||
| 41 | |||
| 42 | /* Sysctl base for spear platform */ | ||
| 43 | #define SPEAR_SYS_CTRL_BASE SPEAR6XX_ICM3_SYS_CTRL_BASE | ||
| 44 | #define VA_SPEAR_SYS_CTRL_BASE VA_SPEAR6XX_ICM3_SYS_CTRL_BASE | ||
| 45 | |||
| 46 | #endif /* __MACH_SPEAR6XX_H */ | ||
diff --git a/arch/arm/mach-spear6xx/include/mach/timex.h b/arch/arm/mach-spear6xx/include/mach/timex.h deleted file mode 100644 index ac1c5b005695..000000000000 --- a/arch/arm/mach-spear6xx/include/mach/timex.h +++ /dev/null | |||
| @@ -1,19 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-spear6xx/include/mach/timex.h | ||
| 3 | * | ||
| 4 | * SPEAr6XX machine family specific timex definitions | ||
| 5 | * | ||
| 6 | * Copyright (C) 2009 ST Microelectronics | ||
| 7 | * Rajeev Kumar<rajeev-dlh.kumar@st.com> | ||
| 8 | * | ||
| 9 | * This file is licensed under the terms of the GNU General Public | ||
| 10 | * License version 2. This program is licensed "as is" without any | ||
| 11 | * warranty of any kind, whether express or implied. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef __MACH_TIMEX_H | ||
| 15 | #define __MACH_TIMEX_H | ||
| 16 | |||
| 17 | #include <plat/timex.h> | ||
| 18 | |||
| 19 | #endif /* __MACH_TIMEX_H */ | ||
diff --git a/arch/arm/mach-spear6xx/include/mach/uncompress.h b/arch/arm/mach-spear6xx/include/mach/uncompress.h deleted file mode 100644 index 77f0765e21e1..000000000000 --- a/arch/arm/mach-spear6xx/include/mach/uncompress.h +++ /dev/null | |||
| @@ -1,19 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-spear6xx/include/mach/uncompress.h | ||
| 3 | * | ||
| 4 | * Serial port stubs for kernel decompress status messages | ||
| 5 | * | ||
| 6 | * Copyright (C) 2009 ST Microelectronics | ||
| 7 | * Rajeev Kumar<rajeev-dlh.kumar@st.com> | ||
| 8 | * | ||
| 9 | * This file is licensed under the terms of the GNU General Public | ||
| 10 | * License version 2. This program is licensed "as is" without any | ||
| 11 | * warranty of any kind, whether express or implied. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef __MACH_UNCOMPRESS_H | ||
| 15 | #define __MACH_UNCOMPRESS_H | ||
| 16 | |||
| 17 | #include <plat/uncompress.h> | ||
| 18 | |||
| 19 | #endif /* __MACH_UNCOMPRESS_H */ | ||
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index f6b46ae2b7f8..e40326d0e29f 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile | |||
| @@ -10,6 +10,7 @@ obj-y += pm.o | |||
| 10 | obj-y += reset.o | 10 | obj-y += reset.o |
| 11 | obj-y += reset-handler.o | 11 | obj-y += reset-handler.o |
| 12 | obj-y += sleep.o | 12 | obj-y += sleep.o |
| 13 | obj-y += tegra.o | ||
| 13 | obj-$(CONFIG_CPU_IDLE) += cpuidle.o | 14 | obj-$(CONFIG_CPU_IDLE) += cpuidle.o |
| 14 | obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20_speedo.o | 15 | obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20_speedo.o |
| 15 | obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o | 16 | obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o |
| @@ -27,9 +28,7 @@ obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o | |||
| 27 | obj-$(CONFIG_CPU_FREQ) += cpu-tegra.o | 28 | obj-$(CONFIG_CPU_FREQ) += cpu-tegra.o |
| 28 | obj-$(CONFIG_TEGRA_PCI) += pcie.o | 29 | obj-$(CONFIG_TEGRA_PCI) += pcie.o |
| 29 | 30 | ||
| 30 | obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += board-dt-tegra20.o | 31 | obj-$(CONFIG_ARCH_TEGRA_114_SOC) += tegra114_speedo.o |
| 31 | obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += board-dt-tegra30.o | ||
| 32 | obj-$(CONFIG_ARCH_TEGRA_114_SOC) += board-dt-tegra114.o | ||
| 33 | ifeq ($(CONFIG_CPU_IDLE),y) | 32 | ifeq ($(CONFIG_CPU_IDLE),y) |
| 34 | obj-$(CONFIG_ARCH_TEGRA_114_SOC) += cpuidle-tegra114.o | 33 | obj-$(CONFIG_ARCH_TEGRA_114_SOC) += cpuidle-tegra114.o |
| 35 | endif | 34 | endif |
diff --git a/arch/arm/mach-tegra/board-dt-tegra114.c b/arch/arm/mach-tegra/board-dt-tegra114.c deleted file mode 100644 index 085d63637b62..000000000000 --- a/arch/arm/mach-tegra/board-dt-tegra114.c +++ /dev/null | |||
| @@ -1,46 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * NVIDIA Tegra114 device tree board support | ||
| 3 | * | ||
| 4 | * Copyright (C) 2013 NVIDIA Corporation | ||
| 5 | * | ||
| 6 | * This software is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2, as published by the Free Software Foundation, and | ||
| 8 | * may be copied, distributed, and modified under those terms. | ||
| 9 | * | ||
| 10 | * This program is distributed in the hope that it will be useful, | ||
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 13 | * GNU General Public License for more details. | ||
| 14 | * | ||
| 15 | */ | ||
| 16 | |||
| 17 | #include <linux/of.h> | ||
| 18 | #include <linux/of_platform.h> | ||
| 19 | #include <linux/clocksource.h> | ||
| 20 | |||
| 21 | #include <asm/mach/arch.h> | ||
| 22 | |||
| 23 | #include "board.h" | ||
| 24 | #include "common.h" | ||
| 25 | |||
| 26 | static void __init tegra114_dt_init(void) | ||
| 27 | { | ||
| 28 | of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); | ||
| 29 | } | ||
| 30 | |||
| 31 | static const char * const tegra114_dt_board_compat[] = { | ||
| 32 | "nvidia,tegra114", | ||
| 33 | NULL, | ||
| 34 | }; | ||
| 35 | |||
| 36 | DT_MACHINE_START(TEGRA114_DT, "NVIDIA Tegra114 (Flattened Device Tree)") | ||
| 37 | .smp = smp_ops(tegra_smp_ops), | ||
| 38 | .map_io = tegra_map_common_io, | ||
| 39 | .init_early = tegra114_init_early, | ||
| 40 | .init_irq = tegra_dt_init_irq, | ||
| 41 | .init_time = clocksource_of_init, | ||
| 42 | .init_machine = tegra114_dt_init, | ||
| 43 | .init_late = tegra_init_late, | ||
| 44 | .restart = tegra_assert_system_reset, | ||
| 45 | .dt_compat = tegra114_dt_board_compat, | ||
| 46 | MACHINE_END | ||
diff --git a/arch/arm/mach-tegra/board-dt-tegra30.c b/arch/arm/mach-tegra/board-dt-tegra30.c deleted file mode 100644 index bf68567e549d..000000000000 --- a/arch/arm/mach-tegra/board-dt-tegra30.c +++ /dev/null | |||
| @@ -1,60 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-tegra/board-dt-tegra30.c | ||
| 3 | * | ||
| 4 | * NVIDIA Tegra30 device tree board support | ||
| 5 | * | ||
| 6 | * Copyright (C) 2011 NVIDIA Corporation | ||
| 7 | * | ||
| 8 | * Derived from: | ||
| 9 | * | ||
| 10 | * arch/arm/mach-tegra/board-dt-tegra20.c | ||
| 11 | * | ||
| 12 | * Copyright (C) 2010 Secret Lab Technologies, Ltd. | ||
| 13 | * Copyright (C) 2010 Google, Inc. | ||
| 14 | * | ||
| 15 | * This software is licensed under the terms of the GNU General Public | ||
| 16 | * License version 2, as published by the Free Software Foundation, and | ||
| 17 | * may be copied, distributed, and modified under those terms. | ||
| 18 | * | ||
| 19 | * This program is distributed in the hope that it will be useful, | ||
| 20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 22 | * GNU General Public License for more details. | ||
| 23 | * | ||
| 24 | */ | ||
| 25 | |||
| 26 | #include <linux/clocksource.h> | ||
| 27 | #include <linux/kernel.h> | ||
| 28 | #include <linux/of.h> | ||
| 29 | #include <linux/of_address.h> | ||
| 30 | #include <linux/of_fdt.h> | ||
| 31 | #include <linux/of_irq.h> | ||
| 32 | #include <linux/of_platform.h> | ||
| 33 | |||
| 34 | #include <asm/mach/arch.h> | ||
| 35 | |||
| 36 | #include "board.h" | ||
| 37 | #include "common.h" | ||
| 38 | #include "iomap.h" | ||
| 39 | |||
| 40 | static void __init tegra30_dt_init(void) | ||
| 41 | { | ||
| 42 | of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); | ||
| 43 | } | ||
| 44 | |||
| 45 | static const char *tegra30_dt_board_compat[] = { | ||
| 46 | "nvidia,tegra30", | ||
| 47 | NULL | ||
| 48 | }; | ||
| 49 | |||
| 50 | DT_MACHINE_START(TEGRA30_DT, "NVIDIA Tegra30 (Flattened Device Tree)") | ||
| 51 | .smp = smp_ops(tegra_smp_ops), | ||
| 52 | .map_io = tegra_map_common_io, | ||
| 53 | .init_early = tegra30_init_early, | ||
| 54 | .init_irq = tegra_dt_init_irq, | ||
| 55 | .init_time = clocksource_of_init, | ||
| 56 | .init_machine = tegra30_dt_init, | ||
| 57 | .init_late = tegra_init_late, | ||
| 58 | .restart = tegra_assert_system_reset, | ||
| 59 | .dt_compat = tegra30_dt_board_compat, | ||
| 60 | MACHINE_END | ||
diff --git a/arch/arm/mach-tegra/board-harmony-pcie.c b/arch/arm/mach-tegra/board-harmony-pcie.c index 6d29e6a39540..035b240b9e15 100644 --- a/arch/arm/mach-tegra/board-harmony-pcie.c +++ b/arch/arm/mach-tegra/board-harmony-pcie.c | |||
| @@ -62,7 +62,11 @@ int __init harmony_pcie_init(void) | |||
| 62 | goto err_reg; | 62 | goto err_reg; |
| 63 | } | 63 | } |
| 64 | 64 | ||
| 65 | regulator_enable(regulator); | 65 | err = regulator_enable(regulator); |
| 66 | if (err) { | ||
| 67 | pr_err("%s: regulator_enable failed: %d\n", __func__, err); | ||
| 68 | goto err_en; | ||
| 69 | } | ||
| 66 | 70 | ||
| 67 | err = tegra_pcie_init(true, true); | 71 | err = tegra_pcie_init(true, true); |
| 68 | if (err) { | 72 | if (err) { |
| @@ -74,6 +78,7 @@ int __init harmony_pcie_init(void) | |||
| 74 | 78 | ||
| 75 | err_pcie: | 79 | err_pcie: |
| 76 | regulator_disable(regulator); | 80 | regulator_disable(regulator); |
| 81 | err_en: | ||
| 77 | regulator_put(regulator); | 82 | regulator_put(regulator); |
| 78 | err_reg: | 83 | err_reg: |
| 79 | gpio_free(en_vdd_1v05); | 84 | gpio_free(en_vdd_1v05); |
diff --git a/arch/arm/mach-tegra/board.h b/arch/arm/mach-tegra/board.h index 86851c81a350..60431de585ca 100644 --- a/arch/arm/mach-tegra/board.h +++ b/arch/arm/mach-tegra/board.h | |||
| @@ -26,9 +26,7 @@ | |||
| 26 | 26 | ||
| 27 | void tegra_assert_system_reset(char mode, const char *cmd); | 27 | void tegra_assert_system_reset(char mode, const char *cmd); |
| 28 | 28 | ||
| 29 | void __init tegra20_init_early(void); | 29 | void __init tegra_init_early(void); |
| 30 | void __init tegra30_init_early(void); | ||
| 31 | void __init tegra114_init_early(void); | ||
| 32 | void __init tegra_map_common_io(void); | 30 | void __init tegra_map_common_io(void); |
| 33 | void __init tegra_init_irq(void); | 31 | void __init tegra_init_irq(void); |
| 34 | void __init tegra_dt_init_irq(void); | 32 | void __init tegra_dt_init_irq(void); |
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c index 5449a3f2977b..eb1f3c8c74cc 100644 --- a/arch/arm/mach-tegra/common.c +++ b/arch/arm/mach-tegra/common.c | |||
| @@ -33,6 +33,7 @@ | |||
| 33 | #include "common.h" | 33 | #include "common.h" |
| 34 | #include "fuse.h" | 34 | #include "fuse.h" |
| 35 | #include "iomap.h" | 35 | #include "iomap.h" |
| 36 | #include "irq.h" | ||
| 36 | #include "pmc.h" | 37 | #include "pmc.h" |
| 37 | #include "apbio.h" | 38 | #include "apbio.h" |
| 38 | #include "sleep.h" | 39 | #include "sleep.h" |
| @@ -61,8 +62,10 @@ u32 tegra_uart_config[4] = { | |||
| 61 | void __init tegra_dt_init_irq(void) | 62 | void __init tegra_dt_init_irq(void) |
| 62 | { | 63 | { |
| 63 | tegra_clocks_init(); | 64 | tegra_clocks_init(); |
| 65 | tegra_pmc_init(); | ||
| 64 | tegra_init_irq(); | 66 | tegra_init_irq(); |
| 65 | irqchip_init(); | 67 | irqchip_init(); |
| 68 | tegra_legacy_irq_syscore_init(); | ||
| 66 | } | 69 | } |
| 67 | #endif | 70 | #endif |
| 68 | 71 | ||
| @@ -94,40 +97,18 @@ static void __init tegra_init_cache(void) | |||
| 94 | 97 | ||
| 95 | } | 98 | } |
| 96 | 99 | ||
| 97 | static void __init tegra_init_early(void) | 100 | void __init tegra_init_early(void) |
| 98 | { | 101 | { |
| 99 | tegra_cpu_reset_handler_init(); | 102 | tegra_cpu_reset_handler_init(); |
| 100 | tegra_apb_io_init(); | 103 | tegra_apb_io_init(); |
| 101 | tegra_init_fuse(); | 104 | tegra_init_fuse(); |
| 102 | tegra_init_cache(); | 105 | tegra_init_cache(); |
| 103 | tegra_pmc_init(); | ||
| 104 | tegra_powergate_init(); | 106 | tegra_powergate_init(); |
| 107 | tegra_hotplug_init(); | ||
| 105 | } | 108 | } |
| 106 | 109 | ||
| 107 | #ifdef CONFIG_ARCH_TEGRA_2x_SOC | ||
| 108 | void __init tegra20_init_early(void) | ||
| 109 | { | ||
| 110 | tegra_init_early(); | ||
| 111 | tegra20_hotplug_init(); | ||
| 112 | } | ||
| 113 | #endif | ||
| 114 | |||
| 115 | #ifdef CONFIG_ARCH_TEGRA_3x_SOC | ||
| 116 | void __init tegra30_init_early(void) | ||
| 117 | { | ||
| 118 | tegra_init_early(); | ||
| 119 | tegra30_hotplug_init(); | ||
| 120 | } | ||
| 121 | #endif | ||
| 122 | |||
| 123 | #ifdef CONFIG_ARCH_TEGRA_114_SOC | ||
| 124 | void __init tegra114_init_early(void) | ||
| 125 | { | ||
| 126 | tegra_init_early(); | ||
| 127 | } | ||
| 128 | #endif | ||
| 129 | |||
| 130 | void __init tegra_init_late(void) | 110 | void __init tegra_init_late(void) |
| 131 | { | 111 | { |
| 112 | tegra_init_suspend(); | ||
| 132 | tegra_powergate_debugfs_init(); | 113 | tegra_powergate_debugfs_init(); |
| 133 | } | 114 | } |
diff --git a/arch/arm/mach-tegra/cpuidle-tegra20.c b/arch/arm/mach-tegra/cpuidle-tegra20.c index 825ced4f7a40..8bbbdebed882 100644 --- a/arch/arm/mach-tegra/cpuidle-tegra20.c +++ b/arch/arm/mach-tegra/cpuidle-tegra20.c | |||
| @@ -130,10 +130,6 @@ static bool tegra20_cpu_cluster_power_down(struct cpuidle_device *dev, | |||
| 130 | struct cpuidle_driver *drv, | 130 | struct cpuidle_driver *drv, |
| 131 | int index) | 131 | int index) |
| 132 | { | 132 | { |
| 133 | struct cpuidle_state *state = &drv->states[index]; | ||
| 134 | u32 cpu_on_time = state->exit_latency; | ||
| 135 | u32 cpu_off_time = state->target_residency - state->exit_latency; | ||
| 136 | |||
| 137 | while (tegra20_cpu_is_resettable_soon()) | 133 | while (tegra20_cpu_is_resettable_soon()) |
| 138 | cpu_relax(); | 134 | cpu_relax(); |
| 139 | 135 | ||
| @@ -142,7 +138,7 @@ static bool tegra20_cpu_cluster_power_down(struct cpuidle_device *dev, | |||
| 142 | 138 | ||
| 143 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu); | 139 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu); |
| 144 | 140 | ||
| 145 | tegra_idle_lp2_last(cpu_on_time, cpu_off_time); | 141 | tegra_idle_lp2_last(); |
| 146 | 142 | ||
| 147 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu); | 143 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu); |
| 148 | 144 | ||
diff --git a/arch/arm/mach-tegra/cpuidle-tegra30.c b/arch/arm/mach-tegra/cpuidle-tegra30.c index 8b50cf4ddd6f..c0931c8bb3e5 100644 --- a/arch/arm/mach-tegra/cpuidle-tegra30.c +++ b/arch/arm/mach-tegra/cpuidle-tegra30.c | |||
| @@ -72,10 +72,6 @@ static bool tegra30_cpu_cluster_power_down(struct cpuidle_device *dev, | |||
| 72 | struct cpuidle_driver *drv, | 72 | struct cpuidle_driver *drv, |
| 73 | int index) | 73 | int index) |
| 74 | { | 74 | { |
| 75 | struct cpuidle_state *state = &drv->states[index]; | ||
| 76 | u32 cpu_on_time = state->exit_latency; | ||
| 77 | u32 cpu_off_time = state->target_residency - state->exit_latency; | ||
| 78 | |||
| 79 | /* All CPUs entering LP2 is not working. | 75 | /* All CPUs entering LP2 is not working. |
| 80 | * Don't let CPU0 enter LP2 when any secondary CPU is online. | 76 | * Don't let CPU0 enter LP2 when any secondary CPU is online. |
| 81 | */ | 77 | */ |
| @@ -86,7 +82,7 @@ static bool tegra30_cpu_cluster_power_down(struct cpuidle_device *dev, | |||
| 86 | 82 | ||
| 87 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu); | 83 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu); |
| 88 | 84 | ||
| 89 | tegra_idle_lp2_last(cpu_on_time, cpu_off_time); | 85 | tegra_idle_lp2_last(); |
| 90 | 86 | ||
| 91 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu); | 87 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu); |
| 92 | 88 | ||
| @@ -102,12 +98,8 @@ static bool tegra30_cpu_core_power_down(struct cpuidle_device *dev, | |||
| 102 | 98 | ||
| 103 | smp_wmb(); | 99 | smp_wmb(); |
| 104 | 100 | ||
| 105 | save_cpu_arch_register(); | ||
| 106 | |||
| 107 | cpu_suspend(0, tegra30_sleep_cpu_secondary_finish); | 101 | cpu_suspend(0, tegra30_sleep_cpu_secondary_finish); |
| 108 | 102 | ||
| 109 | restore_cpu_arch_register(); | ||
| 110 | |||
| 111 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu); | 103 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu); |
| 112 | 104 | ||
| 113 | return true; | 105 | return true; |
diff --git a/arch/arm/mach-tegra/fuse.c b/arch/arm/mach-tegra/fuse.c index f7db0782a6b6..e035cd284a6e 100644 --- a/arch/arm/mach-tegra/fuse.c +++ b/arch/arm/mach-tegra/fuse.c | |||
| @@ -2,6 +2,7 @@ | |||
| 2 | * arch/arm/mach-tegra/fuse.c | 2 | * arch/arm/mach-tegra/fuse.c |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2010 Google, Inc. | 4 | * Copyright (C) 2010 Google, Inc. |
| 5 | * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. | ||
| 5 | * | 6 | * |
| 6 | * Author: | 7 | * Author: |
| 7 | * Colin Cross <ccross@android.com> | 8 | * Colin Cross <ccross@android.com> |
| @@ -137,6 +138,9 @@ void tegra_init_fuse(void) | |||
| 137 | tegra_fuse_spare_bit = TEGRA30_FUSE_SPARE_BIT; | 138 | tegra_fuse_spare_bit = TEGRA30_FUSE_SPARE_BIT; |
| 138 | tegra_init_speedo_data = &tegra30_init_speedo_data; | 139 | tegra_init_speedo_data = &tegra30_init_speedo_data; |
| 139 | break; | 140 | break; |
| 141 | case TEGRA114: | ||
| 142 | tegra_init_speedo_data = &tegra114_init_speedo_data; | ||
| 143 | break; | ||
| 140 | default: | 144 | default: |
| 141 | pr_warn("Tegra: unknown chip id %d\n", tegra_chip_id); | 145 | pr_warn("Tegra: unknown chip id %d\n", tegra_chip_id); |
| 142 | tegra_fuse_spare_bit = TEGRA20_FUSE_SPARE_BIT; | 146 | tegra_fuse_spare_bit = TEGRA20_FUSE_SPARE_BIT; |
diff --git a/arch/arm/mach-tegra/fuse.h b/arch/arm/mach-tegra/fuse.h index da78434678c7..aacc00d05980 100644 --- a/arch/arm/mach-tegra/fuse.h +++ b/arch/arm/mach-tegra/fuse.h | |||
| @@ -1,5 +1,6 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * Copyright (C) 2010 Google, Inc. | 2 | * Copyright (C) 2010 Google, Inc. |
| 3 | * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. | ||
| 3 | * | 4 | * |
| 4 | * Author: | 5 | * Author: |
| 5 | * Colin Cross <ccross@android.com> | 6 | * Colin Cross <ccross@android.com> |
| @@ -66,4 +67,10 @@ void tegra30_init_speedo_data(void); | |||
| 66 | static inline void tegra30_init_speedo_data(void) {} | 67 | static inline void tegra30_init_speedo_data(void) {} |
| 67 | #endif | 68 | #endif |
| 68 | 69 | ||
| 70 | #ifdef CONFIG_ARCH_TEGRA_114_SOC | ||
| 71 | void tegra114_init_speedo_data(void); | ||
| 72 | #else | ||
| 73 | static inline void tegra114_init_speedo_data(void) {} | ||
| 74 | #endif | ||
| 75 | |||
| 69 | #endif | 76 | #endif |
diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S index fd473f2b4c3d..045c16f2dd51 100644 --- a/arch/arm/mach-tegra/headsmp.S +++ b/arch/arm/mach-tegra/headsmp.S | |||
| @@ -7,8 +7,5 @@ | |||
| 7 | 7 | ||
| 8 | ENTRY(tegra_secondary_startup) | 8 | ENTRY(tegra_secondary_startup) |
| 9 | bl v7_invalidate_l1 | 9 | bl v7_invalidate_l1 |
| 10 | /* Enable coresight */ | ||
| 11 | mov32 r0, 0xC5ACCE55 | ||
| 12 | mcr p14, 0, r0, c7, c12, 6 | ||
| 13 | b secondary_startup | 10 | b secondary_startup |
| 14 | ENDPROC(tegra_secondary_startup) | 11 | ENDPROC(tegra_secondary_startup) |
diff --git a/arch/arm/mach-tegra/hotplug.c b/arch/arm/mach-tegra/hotplug.c index a599f6e36dea..8da9f78475da 100644 --- a/arch/arm/mach-tegra/hotplug.c +++ b/arch/arm/mach-tegra/hotplug.c | |||
| @@ -1,8 +1,7 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * | ||
| 3 | * Copyright (C) 2002 ARM Ltd. | 2 | * Copyright (C) 2002 ARM Ltd. |
| 4 | * All Rights Reserved | 3 | * All Rights Reserved |
| 5 | * Copyright (c) 2010, 2012 NVIDIA Corporation. All rights reserved. | 4 | * Copyright (c) 2010, 2012-2013, NVIDIA Corporation. All rights reserved. |
| 6 | * | 5 | * |
| 7 | * This program is free software; you can redistribute it and/or modify | 6 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License version 2 as | 7 | * it under the terms of the GNU General Public License version 2 as |
| @@ -15,6 +14,7 @@ | |||
| 15 | #include <asm/cacheflush.h> | 14 | #include <asm/cacheflush.h> |
| 16 | #include <asm/smp_plat.h> | 15 | #include <asm/smp_plat.h> |
| 17 | 16 | ||
| 17 | #include "fuse.h" | ||
| 18 | #include "sleep.h" | 18 | #include "sleep.h" |
| 19 | 19 | ||
| 20 | static void (*tegra_hotplug_shutdown)(void); | 20 | static void (*tegra_hotplug_shutdown)(void); |
| @@ -56,18 +56,13 @@ int tegra_cpu_disable(unsigned int cpu) | |||
| 56 | return cpu == 0 ? -EPERM : 0; | 56 | return cpu == 0 ? -EPERM : 0; |
| 57 | } | 57 | } |
| 58 | 58 | ||
| 59 | #ifdef CONFIG_ARCH_TEGRA_2x_SOC | 59 | void __init tegra_hotplug_init(void) |
| 60 | extern void tegra20_hotplug_shutdown(void); | ||
| 61 | void __init tegra20_hotplug_init(void) | ||
| 62 | { | 60 | { |
| 63 | tegra_hotplug_shutdown = tegra20_hotplug_shutdown; | 61 | if (!IS_ENABLED(CONFIG_HOTPLUG_CPU)) |
| 64 | } | 62 | return; |
| 65 | #endif | ||
| 66 | 63 | ||
| 67 | #ifdef CONFIG_ARCH_TEGRA_3x_SOC | 64 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && tegra_chip_id == TEGRA20) |
| 68 | extern void tegra30_hotplug_shutdown(void); | 65 | tegra_hotplug_shutdown = tegra20_hotplug_shutdown; |
| 69 | void __init tegra30_hotplug_init(void) | 66 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) && tegra_chip_id == TEGRA30) |
| 70 | { | 67 | tegra_hotplug_shutdown = tegra30_hotplug_shutdown; |
| 71 | tegra_hotplug_shutdown = tegra30_hotplug_shutdown; | ||
| 72 | } | 68 | } |
| 73 | #endif | ||
diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c index 1952e82797cc..0de4eed1493d 100644 --- a/arch/arm/mach-tegra/irq.c +++ b/arch/arm/mach-tegra/irq.c | |||
| @@ -4,7 +4,7 @@ | |||
| 4 | * Author: | 4 | * Author: |
| 5 | * Colin Cross <ccross@android.com> | 5 | * Colin Cross <ccross@android.com> |
| 6 | * | 6 | * |
| 7 | * Copyright (C) 2010, NVIDIA Corporation | 7 | * Copyright (C) 2010,2013, NVIDIA Corporation |
| 8 | * | 8 | * |
| 9 | * This software is licensed under the terms of the GNU General Public | 9 | * This software is licensed under the terms of the GNU General Public |
| 10 | * License version 2, as published by the Free Software Foundation, and | 10 | * License version 2, as published by the Free Software Foundation, and |
| @@ -23,6 +23,7 @@ | |||
| 23 | #include <linux/io.h> | 23 | #include <linux/io.h> |
| 24 | #include <linux/of.h> | 24 | #include <linux/of.h> |
| 25 | #include <linux/irqchip/arm-gic.h> | 25 | #include <linux/irqchip/arm-gic.h> |
| 26 | #include <linux/syscore_ops.h> | ||
| 26 | 27 | ||
| 27 | #include "board.h" | 28 | #include "board.h" |
| 28 | #include "iomap.h" | 29 | #include "iomap.h" |
| @@ -43,6 +44,7 @@ | |||
| 43 | #define ICTLR_COP_IEP_CLASS 0x3c | 44 | #define ICTLR_COP_IEP_CLASS 0x3c |
| 44 | 45 | ||
| 45 | #define FIRST_LEGACY_IRQ 32 | 46 | #define FIRST_LEGACY_IRQ 32 |
| 47 | #define TEGRA_MAX_NUM_ICTLRS 5 | ||
| 46 | 48 | ||
| 47 | #define SGI_MASK 0xFFFF | 49 | #define SGI_MASK 0xFFFF |
| 48 | 50 | ||
| @@ -56,6 +58,15 @@ static void __iomem *ictlr_reg_base[] = { | |||
| 56 | IO_ADDRESS(TEGRA_QUINARY_ICTLR_BASE), | 58 | IO_ADDRESS(TEGRA_QUINARY_ICTLR_BASE), |
| 57 | }; | 59 | }; |
| 58 | 60 | ||
| 61 | #ifdef CONFIG_PM_SLEEP | ||
| 62 | static u32 cop_ier[TEGRA_MAX_NUM_ICTLRS]; | ||
| 63 | static u32 cop_iep[TEGRA_MAX_NUM_ICTLRS]; | ||
| 64 | static u32 cpu_ier[TEGRA_MAX_NUM_ICTLRS]; | ||
| 65 | static u32 cpu_iep[TEGRA_MAX_NUM_ICTLRS]; | ||
| 66 | |||
| 67 | static u32 ictlr_wake_mask[TEGRA_MAX_NUM_ICTLRS]; | ||
| 68 | #endif | ||
| 69 | |||
| 59 | bool tegra_pending_sgi(void) | 70 | bool tegra_pending_sgi(void) |
| 60 | { | 71 | { |
| 61 | u32 pending_set; | 72 | u32 pending_set; |
| @@ -125,6 +136,87 @@ static int tegra_retrigger(struct irq_data *d) | |||
| 125 | return 1; | 136 | return 1; |
| 126 | } | 137 | } |
| 127 | 138 | ||
| 139 | #ifdef CONFIG_PM_SLEEP | ||
| 140 | static int tegra_set_wake(struct irq_data *d, unsigned int enable) | ||
| 141 | { | ||
| 142 | u32 irq = d->irq; | ||
| 143 | u32 index, mask; | ||
| 144 | |||
| 145 | if (irq < FIRST_LEGACY_IRQ || | ||
| 146 | irq >= FIRST_LEGACY_IRQ + num_ictlrs * 32) | ||
| 147 | return -EINVAL; | ||
| 148 | |||
| 149 | index = ((irq - FIRST_LEGACY_IRQ) / 32); | ||
| 150 | mask = BIT((irq - FIRST_LEGACY_IRQ) % 32); | ||
| 151 | if (enable) | ||
| 152 | ictlr_wake_mask[index] |= mask; | ||
| 153 | else | ||
| 154 | ictlr_wake_mask[index] &= ~mask; | ||
| 155 | |||
| 156 | return 0; | ||
| 157 | } | ||
| 158 | |||
| 159 | static int tegra_legacy_irq_suspend(void) | ||
| 160 | { | ||
| 161 | unsigned long flags; | ||
| 162 | int i; | ||
| 163 | |||
| 164 | local_irq_save(flags); | ||
| 165 | for (i = 0; i < num_ictlrs; i++) { | ||
| 166 | void __iomem *ictlr = ictlr_reg_base[i]; | ||
| 167 | /* Save interrupt state */ | ||
| 168 | cpu_ier[i] = readl_relaxed(ictlr + ICTLR_CPU_IER); | ||
| 169 | cpu_iep[i] = readl_relaxed(ictlr + ICTLR_CPU_IEP_CLASS); | ||
| 170 | cop_ier[i] = readl_relaxed(ictlr + ICTLR_COP_IER); | ||
| 171 | cop_iep[i] = readl_relaxed(ictlr + ICTLR_COP_IEP_CLASS); | ||
| 172 | |||
| 173 | /* Disable COP interrupts */ | ||
| 174 | writel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR); | ||
| 175 | |||
| 176 | /* Disable CPU interrupts */ | ||
| 177 | writel_relaxed(~0ul, ictlr + ICTLR_CPU_IER_CLR); | ||
| 178 | |||
| 179 | /* Enable the wakeup sources of ictlr */ | ||
| 180 | writel_relaxed(ictlr_wake_mask[i], ictlr + ICTLR_CPU_IER_SET); | ||
| 181 | } | ||
| 182 | local_irq_restore(flags); | ||
| 183 | |||
| 184 | return 0; | ||
| 185 | } | ||
| 186 | |||
| 187 | static void tegra_legacy_irq_resume(void) | ||
| 188 | { | ||
| 189 | unsigned long flags; | ||
| 190 | int i; | ||
| 191 | |||
| 192 | local_irq_save(flags); | ||
| 193 | for (i = 0; i < num_ictlrs; i++) { | ||
| 194 | void __iomem *ictlr = ictlr_reg_base[i]; | ||
| 195 | writel_relaxed(cpu_iep[i], ictlr + ICTLR_CPU_IEP_CLASS); | ||
| 196 | writel_relaxed(~0ul, ictlr + ICTLR_CPU_IER_CLR); | ||
| 197 | writel_relaxed(cpu_ier[i], ictlr + ICTLR_CPU_IER_SET); | ||
| 198 | writel_relaxed(cop_iep[i], ictlr + ICTLR_COP_IEP_CLASS); | ||
| 199 | writel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR); | ||
| 200 | writel_relaxed(cop_ier[i], ictlr + ICTLR_COP_IER_SET); | ||
| 201 | } | ||
| 202 | local_irq_restore(flags); | ||
| 203 | } | ||
| 204 | |||
| 205 | static struct syscore_ops tegra_legacy_irq_syscore_ops = { | ||
| 206 | .suspend = tegra_legacy_irq_suspend, | ||
| 207 | .resume = tegra_legacy_irq_resume, | ||
| 208 | }; | ||
| 209 | |||
| 210 | int tegra_legacy_irq_syscore_init(void) | ||
| 211 | { | ||
| 212 | register_syscore_ops(&tegra_legacy_irq_syscore_ops); | ||
| 213 | |||
| 214 | return 0; | ||
| 215 | } | ||
| 216 | #else | ||
| 217 | #define tegra_set_wake NULL | ||
| 218 | #endif | ||
| 219 | |||
| 128 | void __init tegra_init_irq(void) | 220 | void __init tegra_init_irq(void) |
| 129 | { | 221 | { |
| 130 | int i; | 222 | int i; |
| @@ -150,6 +242,8 @@ void __init tegra_init_irq(void) | |||
| 150 | gic_arch_extn.irq_mask = tegra_mask; | 242 | gic_arch_extn.irq_mask = tegra_mask; |
| 151 | gic_arch_extn.irq_unmask = tegra_unmask; | 243 | gic_arch_extn.irq_unmask = tegra_unmask; |
| 152 | gic_arch_extn.irq_retrigger = tegra_retrigger; | 244 | gic_arch_extn.irq_retrigger = tegra_retrigger; |
| 245 | gic_arch_extn.irq_set_wake = tegra_set_wake; | ||
| 246 | gic_arch_extn.flags = IRQCHIP_MASK_ON_SUSPEND; | ||
| 153 | 247 | ||
| 154 | /* | 248 | /* |
| 155 | * Check if there is a devicetree present, since the GIC will be | 249 | * Check if there is a devicetree present, since the GIC will be |
diff --git a/arch/arm/mach-tegra/irq.h b/arch/arm/mach-tegra/irq.h index 5142649bba05..bc05ce5613fb 100644 --- a/arch/arm/mach-tegra/irq.h +++ b/arch/arm/mach-tegra/irq.h | |||
| @@ -19,4 +19,10 @@ | |||
| 19 | 19 | ||
| 20 | bool tegra_pending_sgi(void); | 20 | bool tegra_pending_sgi(void); |
| 21 | 21 | ||
| 22 | #ifdef CONFIG_PM_SLEEP | ||
| 23 | int tegra_legacy_irq_syscore_init(void); | ||
| 24 | #else | ||
| 25 | static inline int tegra_legacy_irq_syscore_init(void) { return 0; } | ||
| 26 | #endif | ||
| 27 | |||
| 22 | #endif | 28 | #endif |
diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c index 2c6b3d55213b..516aab28fe34 100644 --- a/arch/arm/mach-tegra/platsmp.c +++ b/arch/arm/mach-tegra/platsmp.c | |||
| @@ -26,22 +26,16 @@ | |||
| 26 | #include <asm/smp_scu.h> | 26 | #include <asm/smp_scu.h> |
| 27 | #include <asm/smp_plat.h> | 27 | #include <asm/smp_plat.h> |
| 28 | 28 | ||
| 29 | #include <mach/powergate.h> | ||
| 30 | |||
| 31 | #include "fuse.h" | 29 | #include "fuse.h" |
| 32 | #include "flowctrl.h" | 30 | #include "flowctrl.h" |
| 33 | #include "reset.h" | 31 | #include "reset.h" |
| 32 | #include "pmc.h" | ||
| 34 | 33 | ||
| 35 | #include "common.h" | 34 | #include "common.h" |
| 36 | #include "iomap.h" | 35 | #include "iomap.h" |
| 37 | 36 | ||
| 38 | extern void tegra_secondary_startup(void); | ||
| 39 | |||
| 40 | static cpumask_t tegra_cpu_init_mask; | 37 | static cpumask_t tegra_cpu_init_mask; |
| 41 | 38 | ||
| 42 | #define EVP_CPU_RESET_VECTOR \ | ||
| 43 | (IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE) + 0x100) | ||
| 44 | |||
| 45 | static void __cpuinit tegra_secondary_init(unsigned int cpu) | 39 | static void __cpuinit tegra_secondary_init(unsigned int cpu) |
| 46 | { | 40 | { |
| 47 | /* | 41 | /* |
| @@ -54,25 +48,43 @@ static void __cpuinit tegra_secondary_init(unsigned int cpu) | |||
| 54 | cpumask_set_cpu(cpu, &tegra_cpu_init_mask); | 48 | cpumask_set_cpu(cpu, &tegra_cpu_init_mask); |
| 55 | } | 49 | } |
| 56 | 50 | ||
| 57 | static int tegra20_power_up_cpu(unsigned int cpu) | 51 | |
| 52 | static int tegra20_boot_secondary(unsigned int cpu, struct task_struct *idle) | ||
| 58 | { | 53 | { |
| 59 | /* Enable the CPU clock. */ | 54 | cpu = cpu_logical_map(cpu); |
| 60 | tegra_enable_cpu_clock(cpu); | 55 | |
| 56 | /* | ||
| 57 | * Force the CPU into reset. The CPU must remain in reset when | ||
| 58 | * the flow controller state is cleared (which will cause the | ||
| 59 | * flow controller to stop driving reset if the CPU has been | ||
| 60 | * power-gated via the flow controller). This will have no | ||
| 61 | * effect on first boot of the CPU since it should already be | ||
| 62 | * in reset. | ||
| 63 | */ | ||
| 64 | tegra_put_cpu_in_reset(cpu); | ||
| 61 | 65 | ||
| 62 | /* Clear flow controller CSR. */ | 66 | /* |
| 63 | flowctrl_write_cpu_csr(cpu, 0); | 67 | * Unhalt the CPU. If the flow controller was used to |
| 68 | * power-gate the CPU this will cause the flow controller to | ||
| 69 | * stop driving reset. The CPU will remain in reset because the | ||
| 70 | * clock and reset block is now driving reset. | ||
| 71 | */ | ||
| 72 | flowctrl_write_cpu_halt(cpu, 0); | ||
| 64 | 73 | ||
| 74 | tegra_enable_cpu_clock(cpu); | ||
| 75 | flowctrl_write_cpu_csr(cpu, 0); /* Clear flow controller CSR. */ | ||
| 76 | tegra_cpu_out_of_reset(cpu); | ||
| 65 | return 0; | 77 | return 0; |
| 66 | } | 78 | } |
| 67 | 79 | ||
| 68 | static int tegra30_power_up_cpu(unsigned int cpu) | 80 | static int tegra30_boot_secondary(unsigned int cpu, struct task_struct *idle) |
| 69 | { | 81 | { |
| 70 | int ret, pwrgateid; | 82 | int ret; |
| 71 | unsigned long timeout; | 83 | unsigned long timeout; |
| 72 | 84 | ||
| 73 | pwrgateid = tegra_cpu_powergate_id(cpu); | 85 | cpu = cpu_logical_map(cpu); |
| 74 | if (pwrgateid < 0) | 86 | tegra_put_cpu_in_reset(cpu); |
| 75 | return pwrgateid; | 87 | flowctrl_write_cpu_halt(cpu, 0); |
| 76 | 88 | ||
| 77 | /* | 89 | /* |
| 78 | * The power up sequence of cold boot CPU and warm boot CPU | 90 | * The power up sequence of cold boot CPU and warm boot CPU |
| @@ -85,13 +97,13 @@ static int tegra30_power_up_cpu(unsigned int cpu) | |||
| 85 | * the IO clamps. | 97 | * the IO clamps. |
| 86 | * For cold boot CPU, do not wait. After the cold boot CPU be | 98 | * For cold boot CPU, do not wait. After the cold boot CPU be |
| 87 | * booted, it will run to tegra_secondary_init() and set | 99 | * booted, it will run to tegra_secondary_init() and set |
| 88 | * tegra_cpu_init_mask which influences what tegra30_power_up_cpu() | 100 | * tegra_cpu_init_mask which influences what tegra30_boot_secondary() |
| 89 | * next time around. | 101 | * next time around. |
| 90 | */ | 102 | */ |
| 91 | if (cpumask_test_cpu(cpu, &tegra_cpu_init_mask)) { | 103 | if (cpumask_test_cpu(cpu, &tegra_cpu_init_mask)) { |
| 92 | timeout = jiffies + msecs_to_jiffies(50); | 104 | timeout = jiffies + msecs_to_jiffies(50); |
| 93 | do { | 105 | do { |
| 94 | if (!tegra_powergate_is_powered(pwrgateid)) | 106 | if (tegra_pmc_cpu_is_powered(cpu)) |
| 95 | goto remove_clamps; | 107 | goto remove_clamps; |
| 96 | udelay(10); | 108 | udelay(10); |
| 97 | } while (time_before(jiffies, timeout)); | 109 | } while (time_before(jiffies, timeout)); |
| @@ -103,14 +115,14 @@ static int tegra30_power_up_cpu(unsigned int cpu) | |||
| 103 | * be un-gated by un-toggling the power gate register | 115 | * be un-gated by un-toggling the power gate register |
| 104 | * manually. | 116 | * manually. |
| 105 | */ | 117 | */ |
| 106 | if (!tegra_powergate_is_powered(pwrgateid)) { | 118 | if (!tegra_pmc_cpu_is_powered(cpu)) { |
| 107 | ret = tegra_powergate_power_on(pwrgateid); | 119 | ret = tegra_pmc_cpu_power_on(cpu); |
| 108 | if (ret) | 120 | if (ret) |
| 109 | return ret; | 121 | return ret; |
| 110 | 122 | ||
| 111 | /* Wait for the power to come up. */ | 123 | /* Wait for the power to come up. */ |
| 112 | timeout = jiffies + msecs_to_jiffies(100); | 124 | timeout = jiffies + msecs_to_jiffies(100); |
| 113 | while (tegra_powergate_is_powered(pwrgateid)) { | 125 | while (tegra_pmc_cpu_is_powered(cpu)) { |
| 114 | if (time_after(jiffies, timeout)) | 126 | if (time_after(jiffies, timeout)) |
| 115 | return -ETIMEDOUT; | 127 | return -ETIMEDOUT; |
| 116 | udelay(10); | 128 | udelay(10); |
| @@ -123,57 +135,34 @@ remove_clamps: | |||
| 123 | udelay(10); | 135 | udelay(10); |
| 124 | 136 | ||
| 125 | /* Remove I/O clamps. */ | 137 | /* Remove I/O clamps. */ |
| 126 | ret = tegra_powergate_remove_clamping(pwrgateid); | 138 | ret = tegra_pmc_cpu_remove_clamping(cpu); |
| 127 | udelay(10); | 139 | if (ret) |
| 140 | return ret; | ||
| 128 | 141 | ||
| 129 | /* Clear flow controller CSR. */ | 142 | udelay(10); |
| 130 | flowctrl_write_cpu_csr(cpu, 0); | ||
| 131 | 143 | ||
| 144 | flowctrl_write_cpu_csr(cpu, 0); /* Clear flow controller CSR. */ | ||
| 145 | tegra_cpu_out_of_reset(cpu); | ||
| 132 | return 0; | 146 | return 0; |
| 133 | } | 147 | } |
| 134 | 148 | ||
| 135 | static int __cpuinit tegra_boot_secondary(unsigned int cpu, struct task_struct *idle) | 149 | static int tegra114_boot_secondary(unsigned int cpu, struct task_struct *idle) |
| 136 | { | 150 | { |
| 137 | int status; | ||
| 138 | |||
| 139 | cpu = cpu_logical_map(cpu); | 151 | cpu = cpu_logical_map(cpu); |
| 152 | return tegra_pmc_cpu_power_on(cpu); | ||
| 153 | } | ||
| 140 | 154 | ||
| 141 | /* | 155 | static int __cpuinit tegra_boot_secondary(unsigned int cpu, |
| 142 | * Force the CPU into reset. The CPU must remain in reset when the | 156 | struct task_struct *idle) |
| 143 | * flow controller state is cleared (which will cause the flow | 157 | { |
| 144 | * controller to stop driving reset if the CPU has been power-gated | 158 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && tegra_chip_id == TEGRA20) |
| 145 | * via the flow controller). This will have no effect on first boot | 159 | return tegra20_boot_secondary(cpu, idle); |
| 146 | * of the CPU since it should already be in reset. | 160 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) && tegra_chip_id == TEGRA30) |
| 147 | */ | 161 | return tegra30_boot_secondary(cpu, idle); |
| 148 | tegra_put_cpu_in_reset(cpu); | 162 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) && tegra_chip_id == TEGRA114) |
| 149 | 163 | return tegra114_boot_secondary(cpu, idle); | |
| 150 | /* | 164 | |
| 151 | * Unhalt the CPU. If the flow controller was used to power-gate the | 165 | return -EINVAL; |
| 152 | * CPU this will cause the flow controller to stop driving reset. | ||
| 153 | * The CPU will remain in reset because the clock and reset block | ||
| 154 | * is now driving reset. | ||
| 155 | */ | ||
| 156 | flowctrl_write_cpu_halt(cpu, 0); | ||
| 157 | |||
| 158 | switch (tegra_chip_id) { | ||
| 159 | case TEGRA20: | ||
| 160 | status = tegra20_power_up_cpu(cpu); | ||
| 161 | break; | ||
| 162 | case TEGRA30: | ||
| 163 | status = tegra30_power_up_cpu(cpu); | ||
| 164 | break; | ||
| 165 | default: | ||
| 166 | status = -EINVAL; | ||
| 167 | break; | ||
| 168 | } | ||
| 169 | |||
| 170 | if (status) | ||
| 171 | goto done; | ||
| 172 | |||
| 173 | /* Take the CPU out of reset. */ | ||
| 174 | tegra_cpu_out_of_reset(cpu); | ||
| 175 | done: | ||
| 176 | return status; | ||
| 177 | } | 166 | } |
| 178 | 167 | ||
| 179 | static void __init tegra_smp_prepare_cpus(unsigned int max_cpus) | 168 | static void __init tegra_smp_prepare_cpus(unsigned int max_cpus) |
diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c index 523604de666f..d0b7400e4606 100644 --- a/arch/arm/mach-tegra/pm.c +++ b/arch/arm/mach-tegra/pm.c | |||
| @@ -22,7 +22,7 @@ | |||
| 22 | #include <linux/cpumask.h> | 22 | #include <linux/cpumask.h> |
| 23 | #include <linux/delay.h> | 23 | #include <linux/delay.h> |
| 24 | #include <linux/cpu_pm.h> | 24 | #include <linux/cpu_pm.h> |
| 25 | #include <linux/clk.h> | 25 | #include <linux/suspend.h> |
| 26 | #include <linux/err.h> | 26 | #include <linux/err.h> |
| 27 | #include <linux/clk/tegra.h> | 27 | #include <linux/clk/tegra.h> |
| 28 | 28 | ||
| @@ -37,67 +37,13 @@ | |||
| 37 | #include "reset.h" | 37 | #include "reset.h" |
| 38 | #include "flowctrl.h" | 38 | #include "flowctrl.h" |
| 39 | #include "fuse.h" | 39 | #include "fuse.h" |
| 40 | #include "pmc.h" | ||
| 40 | #include "sleep.h" | 41 | #include "sleep.h" |
| 41 | 42 | ||
| 42 | #define TEGRA_POWER_CPU_PWRREQ_OE (1 << 16) /* CPU pwr req enable */ | ||
| 43 | |||
| 44 | #define PMC_CTRL 0x0 | ||
| 45 | #define PMC_CPUPWRGOOD_TIMER 0xc8 | ||
| 46 | #define PMC_CPUPWROFF_TIMER 0xcc | ||
| 47 | |||
| 48 | #ifdef CONFIG_PM_SLEEP | 43 | #ifdef CONFIG_PM_SLEEP |
| 49 | static unsigned int g_diag_reg; | ||
| 50 | static DEFINE_SPINLOCK(tegra_lp2_lock); | 44 | static DEFINE_SPINLOCK(tegra_lp2_lock); |
| 51 | static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE); | ||
| 52 | static struct clk *tegra_pclk; | ||
| 53 | void (*tegra_tear_down_cpu)(void); | 45 | void (*tegra_tear_down_cpu)(void); |
| 54 | 46 | ||
| 55 | void save_cpu_arch_register(void) | ||
| 56 | { | ||
| 57 | /* read diagnostic register */ | ||
| 58 | asm("mrc p15, 0, %0, c15, c0, 1" : "=r"(g_diag_reg) : : "cc"); | ||
| 59 | return; | ||
| 60 | } | ||
| 61 | |||
| 62 | void restore_cpu_arch_register(void) | ||
| 63 | { | ||
| 64 | /* write diagnostic register */ | ||
| 65 | asm("mcr p15, 0, %0, c15, c0, 1" : : "r"(g_diag_reg) : "cc"); | ||
| 66 | return; | ||
| 67 | } | ||
| 68 | |||
| 69 | static void set_power_timers(unsigned long us_on, unsigned long us_off) | ||
| 70 | { | ||
| 71 | unsigned long long ticks; | ||
| 72 | unsigned long long pclk; | ||
| 73 | unsigned long rate; | ||
| 74 | static unsigned long tegra_last_pclk; | ||
| 75 | |||
| 76 | if (tegra_pclk == NULL) { | ||
| 77 | tegra_pclk = clk_get_sys(NULL, "pclk"); | ||
| 78 | WARN_ON(IS_ERR(tegra_pclk)); | ||
| 79 | } | ||
| 80 | |||
| 81 | rate = clk_get_rate(tegra_pclk); | ||
| 82 | |||
| 83 | if (WARN_ON_ONCE(rate <= 0)) | ||
| 84 | pclk = 100000000; | ||
| 85 | else | ||
| 86 | pclk = rate; | ||
| 87 | |||
| 88 | if ((rate != tegra_last_pclk)) { | ||
| 89 | ticks = (us_on * pclk) + 999999ull; | ||
| 90 | do_div(ticks, 1000000); | ||
| 91 | writel((unsigned long)ticks, pmc + PMC_CPUPWRGOOD_TIMER); | ||
| 92 | |||
| 93 | ticks = (us_off * pclk) + 999999ull; | ||
| 94 | do_div(ticks, 1000000); | ||
| 95 | writel((unsigned long)ticks, pmc + PMC_CPUPWROFF_TIMER); | ||
| 96 | wmb(); | ||
| 97 | } | ||
| 98 | tegra_last_pclk = pclk; | ||
| 99 | } | ||
| 100 | |||
| 101 | /* | 47 | /* |
| 102 | * restore_cpu_complex | 48 | * restore_cpu_complex |
| 103 | * | 49 | * |
| @@ -119,8 +65,6 @@ static void restore_cpu_complex(void) | |||
| 119 | tegra_cpu_clock_resume(); | 65 | tegra_cpu_clock_resume(); |
| 120 | 66 | ||
| 121 | flowctrl_cpu_suspend_exit(cpu); | 67 | flowctrl_cpu_suspend_exit(cpu); |
| 122 | |||
| 123 | restore_cpu_arch_register(); | ||
| 124 | } | 68 | } |
| 125 | 69 | ||
| 126 | /* | 70 | /* |
| @@ -145,8 +89,6 @@ static void suspend_cpu_complex(void) | |||
| 145 | tegra_cpu_clock_suspend(); | 89 | tegra_cpu_clock_suspend(); |
| 146 | 90 | ||
| 147 | flowctrl_cpu_suspend_enter(cpu); | 91 | flowctrl_cpu_suspend_enter(cpu); |
| 148 | |||
| 149 | save_cpu_arch_register(); | ||
| 150 | } | 92 | } |
| 151 | 93 | ||
| 152 | void tegra_clear_cpu_in_lp2(int phy_cpu_id) | 94 | void tegra_clear_cpu_in_lp2(int phy_cpu_id) |
| @@ -197,16 +139,9 @@ static int tegra_sleep_cpu(unsigned long v2p) | |||
| 197 | return 0; | 139 | return 0; |
| 198 | } | 140 | } |
| 199 | 141 | ||
| 200 | void tegra_idle_lp2_last(u32 cpu_on_time, u32 cpu_off_time) | 142 | void tegra_idle_lp2_last(void) |
| 201 | { | 143 | { |
| 202 | u32 mode; | 144 | tegra_pmc_pm_set(TEGRA_SUSPEND_LP2); |
| 203 | |||
| 204 | /* Only the last cpu down does the final suspend steps */ | ||
| 205 | mode = readl(pmc + PMC_CTRL); | ||
| 206 | mode |= TEGRA_POWER_CPU_PWRREQ_OE; | ||
| 207 | writel(mode, pmc + PMC_CTRL); | ||
| 208 | |||
| 209 | set_power_timers(cpu_on_time, cpu_off_time); | ||
| 210 | 145 | ||
| 211 | cpu_cluster_pm_enter(); | 146 | cpu_cluster_pm_enter(); |
| 212 | suspend_cpu_complex(); | 147 | suspend_cpu_complex(); |
| @@ -216,4 +151,81 @@ void tegra_idle_lp2_last(u32 cpu_on_time, u32 cpu_off_time) | |||
| 216 | restore_cpu_complex(); | 151 | restore_cpu_complex(); |
| 217 | cpu_cluster_pm_exit(); | 152 | cpu_cluster_pm_exit(); |
| 218 | } | 153 | } |
| 154 | |||
| 155 | enum tegra_suspend_mode tegra_pm_validate_suspend_mode( | ||
| 156 | enum tegra_suspend_mode mode) | ||
| 157 | { | ||
| 158 | /* Tegra114 didn't support any suspending mode yet. */ | ||
| 159 | if (tegra_chip_id == TEGRA114) | ||
| 160 | return TEGRA_SUSPEND_NONE; | ||
| 161 | |||
| 162 | /* | ||
| 163 | * The Tegra devices only support suspending to LP2 currently. | ||
| 164 | */ | ||
| 165 | if (mode > TEGRA_SUSPEND_LP2) | ||
| 166 | return TEGRA_SUSPEND_LP2; | ||
| 167 | |||
| 168 | return mode; | ||
| 169 | } | ||
| 170 | |||
| 171 | static const char *lp_state[TEGRA_MAX_SUSPEND_MODE] = { | ||
| 172 | [TEGRA_SUSPEND_NONE] = "none", | ||
| 173 | [TEGRA_SUSPEND_LP2] = "LP2", | ||
| 174 | [TEGRA_SUSPEND_LP1] = "LP1", | ||
| 175 | [TEGRA_SUSPEND_LP0] = "LP0", | ||
| 176 | }; | ||
| 177 | |||
| 178 | static int __cpuinit tegra_suspend_enter(suspend_state_t state) | ||
| 179 | { | ||
| 180 | enum tegra_suspend_mode mode = tegra_pmc_get_suspend_mode(); | ||
| 181 | |||
| 182 | if (WARN_ON(mode < TEGRA_SUSPEND_NONE || | ||
| 183 | mode >= TEGRA_MAX_SUSPEND_MODE)) | ||
| 184 | return -EINVAL; | ||
| 185 | |||
| 186 | pr_info("Entering suspend state %s\n", lp_state[mode]); | ||
| 187 | |||
| 188 | tegra_pmc_pm_set(mode); | ||
| 189 | |||
| 190 | local_fiq_disable(); | ||
| 191 | |||
| 192 | suspend_cpu_complex(); | ||
| 193 | switch (mode) { | ||
| 194 | case TEGRA_SUSPEND_LP2: | ||
| 195 | tegra_set_cpu_in_lp2(0); | ||
| 196 | break; | ||
| 197 | default: | ||
| 198 | break; | ||
| 199 | } | ||
| 200 | |||
| 201 | cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, &tegra_sleep_cpu); | ||
| 202 | |||
| 203 | switch (mode) { | ||
| 204 | case TEGRA_SUSPEND_LP2: | ||
| 205 | tegra_clear_cpu_in_lp2(0); | ||
| 206 | break; | ||
| 207 | default: | ||
| 208 | break; | ||
| 209 | } | ||
| 210 | restore_cpu_complex(); | ||
| 211 | |||
| 212 | local_fiq_enable(); | ||
| 213 | |||
| 214 | return 0; | ||
| 215 | } | ||
| 216 | |||
| 217 | static const struct platform_suspend_ops tegra_suspend_ops = { | ||
| 218 | .valid = suspend_valid_only_mem, | ||
| 219 | .enter = tegra_suspend_enter, | ||
| 220 | }; | ||
| 221 | |||
| 222 | void __init tegra_init_suspend(void) | ||
| 223 | { | ||
| 224 | if (tegra_pmc_get_suspend_mode() == TEGRA_SUSPEND_NONE) | ||
| 225 | return; | ||
| 226 | |||
| 227 | tegra_pmc_suspend_init(); | ||
| 228 | |||
| 229 | suspend_set_ops(&tegra_suspend_ops); | ||
| 230 | } | ||
| 219 | #endif | 231 | #endif |
diff --git a/arch/arm/mach-tegra/pm.h b/arch/arm/mach-tegra/pm.h index 787335cc964c..9d2d038bf12e 100644 --- a/arch/arm/mach-tegra/pm.h +++ b/arch/arm/mach-tegra/pm.h | |||
| @@ -21,6 +21,8 @@ | |||
| 21 | #ifndef _MACH_TEGRA_PM_H_ | 21 | #ifndef _MACH_TEGRA_PM_H_ |
| 22 | #define _MACH_TEGRA_PM_H_ | 22 | #define _MACH_TEGRA_PM_H_ |
| 23 | 23 | ||
| 24 | #include "pmc.h" | ||
| 25 | |||
| 24 | extern unsigned long l2x0_saved_regs_addr; | 26 | extern unsigned long l2x0_saved_regs_addr; |
| 25 | 27 | ||
| 26 | void save_cpu_arch_register(void); | 28 | void save_cpu_arch_register(void); |
| @@ -29,7 +31,20 @@ void restore_cpu_arch_register(void); | |||
| 29 | void tegra_clear_cpu_in_lp2(int phy_cpu_id); | 31 | void tegra_clear_cpu_in_lp2(int phy_cpu_id); |
| 30 | bool tegra_set_cpu_in_lp2(int phy_cpu_id); | 32 | bool tegra_set_cpu_in_lp2(int phy_cpu_id); |
| 31 | 33 | ||
| 32 | void tegra_idle_lp2_last(u32 cpu_on_time, u32 cpu_off_time); | 34 | void tegra_idle_lp2_last(void); |
| 33 | extern void (*tegra_tear_down_cpu)(void); | 35 | extern void (*tegra_tear_down_cpu)(void); |
| 34 | 36 | ||
| 37 | #ifdef CONFIG_PM_SLEEP | ||
| 38 | enum tegra_suspend_mode tegra_pm_validate_suspend_mode( | ||
| 39 | enum tegra_suspend_mode mode); | ||
| 40 | void tegra_init_suspend(void); | ||
| 41 | #else | ||
| 42 | enum tegra_suspend_mode tegra_pm_validate_suspend_mode( | ||
| 43 | enum tegra_suspend_mode mode) | ||
| 44 | { | ||
| 45 | return TEGRA_SUSPEND_NONE; | ||
| 46 | } | ||
| 47 | static inline void tegra_init_suspend(void) {} | ||
| 48 | #endif | ||
| 49 | |||
| 35 | #endif /* _MACH_TEGRA_PM_H_ */ | 50 | #endif /* _MACH_TEGRA_PM_H_ */ |
diff --git a/arch/arm/mach-tegra/pmc.c b/arch/arm/mach-tegra/pmc.c index d4fdb5fcec20..32360e540ce6 100644 --- a/arch/arm/mach-tegra/pmc.c +++ b/arch/arm/mach-tegra/pmc.c | |||
| @@ -1,5 +1,5 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (C) 2012,2013 NVIDIA CORPORATION. All rights reserved. |
| 3 | * | 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
| 5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
| @@ -16,59 +16,313 @@ | |||
| 16 | */ | 16 | */ |
| 17 | 17 | ||
| 18 | #include <linux/kernel.h> | 18 | #include <linux/kernel.h> |
| 19 | #include <linux/clk.h> | ||
| 19 | #include <linux/io.h> | 20 | #include <linux/io.h> |
| 20 | #include <linux/of.h> | 21 | #include <linux/of.h> |
| 22 | #include <linux/of_address.h> | ||
| 21 | 23 | ||
| 22 | #include "iomap.h" | 24 | #include "fuse.h" |
| 25 | #include "pm.h" | ||
| 26 | #include "pmc.h" | ||
| 27 | #include "sleep.h" | ||
| 23 | 28 | ||
| 24 | #define PMC_CTRL 0x0 | 29 | #define TEGRA_POWER_EFFECT_LP0 (1 << 14) /* LP0 when CPU pwr gated */ |
| 25 | #define PMC_CTRL_INTR_LOW (1 << 17) | 30 | #define TEGRA_POWER_CPU_PWRREQ_POLARITY (1 << 15) /* CPU pwr req polarity */ |
| 31 | #define TEGRA_POWER_CPU_PWRREQ_OE (1 << 16) /* CPU pwr req enable */ | ||
| 32 | |||
| 33 | #define PMC_CTRL 0x0 | ||
| 34 | #define PMC_CTRL_INTR_LOW (1 << 17) | ||
| 35 | #define PMC_PWRGATE_TOGGLE 0x30 | ||
| 36 | #define PMC_PWRGATE_TOGGLE_START (1 << 8) | ||
| 37 | #define PMC_REMOVE_CLAMPING 0x34 | ||
| 38 | #define PMC_PWRGATE_STATUS 0x38 | ||
| 39 | |||
| 40 | #define PMC_CPUPWRGOOD_TIMER 0xc8 | ||
| 41 | #define PMC_CPUPWROFF_TIMER 0xcc | ||
| 42 | |||
| 43 | #define TEGRA_POWERGATE_PCIE 3 | ||
| 44 | #define TEGRA_POWERGATE_VDEC 4 | ||
| 45 | #define TEGRA_POWERGATE_CPU1 9 | ||
| 46 | #define TEGRA_POWERGATE_CPU2 10 | ||
| 47 | #define TEGRA_POWERGATE_CPU3 11 | ||
| 48 | |||
| 49 | static u8 tegra_cpu_domains[] = { | ||
| 50 | 0xFF, /* not available for CPU0 */ | ||
| 51 | TEGRA_POWERGATE_CPU1, | ||
| 52 | TEGRA_POWERGATE_CPU2, | ||
| 53 | TEGRA_POWERGATE_CPU3, | ||
| 54 | }; | ||
| 55 | static DEFINE_SPINLOCK(tegra_powergate_lock); | ||
| 56 | |||
| 57 | static void __iomem *tegra_pmc_base; | ||
| 58 | static bool tegra_pmc_invert_interrupt; | ||
| 59 | static struct clk *tegra_pclk; | ||
| 60 | |||
| 61 | struct pmc_pm_data { | ||
| 62 | u32 cpu_good_time; /* CPU power good time in uS */ | ||
| 63 | u32 cpu_off_time; /* CPU power off time in uS */ | ||
| 64 | u32 core_osc_time; /* Core power good osc time in uS */ | ||
| 65 | u32 core_pmu_time; /* Core power good pmu time in uS */ | ||
| 66 | u32 core_off_time; /* Core power off time in uS */ | ||
| 67 | bool corereq_high; /* Core power request active-high */ | ||
| 68 | bool sysclkreq_high; /* System clock request active-high */ | ||
| 69 | bool combined_req; /* Combined pwr req for CPU & Core */ | ||
| 70 | bool cpu_pwr_good_en; /* CPU power good signal is enabled */ | ||
| 71 | u32 lp0_vec_phy_addr; /* The phy addr of LP0 warm boot code */ | ||
| 72 | u32 lp0_vec_size; /* The size of LP0 warm boot code */ | ||
| 73 | enum tegra_suspend_mode suspend_mode; | ||
| 74 | }; | ||
| 75 | static struct pmc_pm_data pmc_pm_data; | ||
| 26 | 76 | ||
| 27 | static inline u32 tegra_pmc_readl(u32 reg) | 77 | static inline u32 tegra_pmc_readl(u32 reg) |
| 28 | { | 78 | { |
| 29 | return readl(IO_ADDRESS(TEGRA_PMC_BASE + reg)); | 79 | return readl(tegra_pmc_base + reg); |
| 30 | } | 80 | } |
| 31 | 81 | ||
| 32 | static inline void tegra_pmc_writel(u32 val, u32 reg) | 82 | static inline void tegra_pmc_writel(u32 val, u32 reg) |
| 33 | { | 83 | { |
| 34 | writel(val, IO_ADDRESS(TEGRA_PMC_BASE + reg)); | 84 | writel(val, tegra_pmc_base + reg); |
| 85 | } | ||
| 86 | |||
| 87 | static int tegra_pmc_get_cpu_powerdomain_id(int cpuid) | ||
| 88 | { | ||
| 89 | if (cpuid <= 0 || cpuid >= num_possible_cpus()) | ||
| 90 | return -EINVAL; | ||
| 91 | return tegra_cpu_domains[cpuid]; | ||
| 92 | } | ||
| 93 | |||
| 94 | static bool tegra_pmc_powergate_is_powered(int id) | ||
| 95 | { | ||
| 96 | return (tegra_pmc_readl(PMC_PWRGATE_STATUS) >> id) & 1; | ||
| 97 | } | ||
| 98 | |||
| 99 | static int tegra_pmc_powergate_set(int id, bool new_state) | ||
| 100 | { | ||
| 101 | bool old_state; | ||
| 102 | unsigned long flags; | ||
| 103 | |||
| 104 | spin_lock_irqsave(&tegra_powergate_lock, flags); | ||
| 105 | |||
| 106 | old_state = tegra_pmc_powergate_is_powered(id); | ||
| 107 | WARN_ON(old_state == new_state); | ||
| 108 | |||
| 109 | tegra_pmc_writel(PMC_PWRGATE_TOGGLE_START | id, PMC_PWRGATE_TOGGLE); | ||
| 110 | |||
| 111 | spin_unlock_irqrestore(&tegra_powergate_lock, flags); | ||
| 112 | |||
| 113 | return 0; | ||
| 114 | } | ||
| 115 | |||
| 116 | static int tegra_pmc_powergate_remove_clamping(int id) | ||
| 117 | { | ||
| 118 | u32 mask; | ||
| 119 | |||
| 120 | /* | ||
| 121 | * Tegra has a bug where PCIE and VDE clamping masks are | ||
| 122 | * swapped relatively to the partition ids. | ||
| 123 | */ | ||
| 124 | if (id == TEGRA_POWERGATE_VDEC) | ||
| 125 | mask = (1 << TEGRA_POWERGATE_PCIE); | ||
| 126 | else if (id == TEGRA_POWERGATE_PCIE) | ||
| 127 | mask = (1 << TEGRA_POWERGATE_VDEC); | ||
| 128 | else | ||
| 129 | mask = (1 << id); | ||
| 130 | |||
| 131 | tegra_pmc_writel(mask, PMC_REMOVE_CLAMPING); | ||
| 132 | |||
| 133 | return 0; | ||
| 134 | } | ||
| 135 | |||
| 136 | bool tegra_pmc_cpu_is_powered(int cpuid) | ||
| 137 | { | ||
| 138 | int id; | ||
| 139 | |||
| 140 | id = tegra_pmc_get_cpu_powerdomain_id(cpuid); | ||
| 141 | if (id < 0) | ||
| 142 | return false; | ||
| 143 | return tegra_pmc_powergate_is_powered(id); | ||
| 35 | } | 144 | } |
| 36 | 145 | ||
| 37 | #ifdef CONFIG_OF | 146 | int tegra_pmc_cpu_power_on(int cpuid) |
| 147 | { | ||
| 148 | int id; | ||
| 149 | |||
| 150 | id = tegra_pmc_get_cpu_powerdomain_id(cpuid); | ||
| 151 | if (id < 0) | ||
| 152 | return id; | ||
| 153 | return tegra_pmc_powergate_set(id, true); | ||
| 154 | } | ||
| 155 | |||
| 156 | int tegra_pmc_cpu_remove_clamping(int cpuid) | ||
| 157 | { | ||
| 158 | int id; | ||
| 159 | |||
| 160 | id = tegra_pmc_get_cpu_powerdomain_id(cpuid); | ||
| 161 | if (id < 0) | ||
| 162 | return id; | ||
| 163 | return tegra_pmc_powergate_remove_clamping(id); | ||
| 164 | } | ||
| 165 | |||
| 166 | #ifdef CONFIG_PM_SLEEP | ||
| 167 | static void set_power_timers(u32 us_on, u32 us_off, unsigned long rate) | ||
| 168 | { | ||
| 169 | unsigned long long ticks; | ||
| 170 | unsigned long long pclk; | ||
| 171 | static unsigned long tegra_last_pclk; | ||
| 172 | |||
| 173 | if (WARN_ON_ONCE(rate <= 0)) | ||
| 174 | pclk = 100000000; | ||
| 175 | else | ||
| 176 | pclk = rate; | ||
| 177 | |||
| 178 | if ((rate != tegra_last_pclk)) { | ||
| 179 | ticks = (us_on * pclk) + 999999ull; | ||
| 180 | do_div(ticks, 1000000); | ||
| 181 | tegra_pmc_writel((unsigned long)ticks, PMC_CPUPWRGOOD_TIMER); | ||
| 182 | |||
| 183 | ticks = (us_off * pclk) + 999999ull; | ||
| 184 | do_div(ticks, 1000000); | ||
| 185 | tegra_pmc_writel((unsigned long)ticks, PMC_CPUPWROFF_TIMER); | ||
| 186 | wmb(); | ||
| 187 | } | ||
| 188 | tegra_last_pclk = pclk; | ||
| 189 | } | ||
| 190 | |||
| 191 | enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void) | ||
| 192 | { | ||
| 193 | return pmc_pm_data.suspend_mode; | ||
| 194 | } | ||
| 195 | |||
| 196 | void tegra_pmc_pm_set(enum tegra_suspend_mode mode) | ||
| 197 | { | ||
| 198 | u32 reg; | ||
| 199 | unsigned long rate = 0; | ||
| 200 | |||
| 201 | reg = tegra_pmc_readl(PMC_CTRL); | ||
| 202 | reg |= TEGRA_POWER_CPU_PWRREQ_OE; | ||
| 203 | reg &= ~TEGRA_POWER_EFFECT_LP0; | ||
| 204 | |||
| 205 | switch (mode) { | ||
| 206 | case TEGRA_SUSPEND_LP2: | ||
| 207 | rate = clk_get_rate(tegra_pclk); | ||
| 208 | break; | ||
| 209 | default: | ||
| 210 | break; | ||
| 211 | } | ||
| 212 | |||
| 213 | set_power_timers(pmc_pm_data.cpu_good_time, pmc_pm_data.cpu_off_time, | ||
| 214 | rate); | ||
| 215 | |||
| 216 | tegra_pmc_writel(reg, PMC_CTRL); | ||
| 217 | } | ||
| 218 | |||
| 219 | void tegra_pmc_suspend_init(void) | ||
| 220 | { | ||
| 221 | u32 reg; | ||
| 222 | |||
| 223 | /* Always enable CPU power request */ | ||
| 224 | reg = tegra_pmc_readl(PMC_CTRL); | ||
| 225 | reg |= TEGRA_POWER_CPU_PWRREQ_OE; | ||
| 226 | tegra_pmc_writel(reg, PMC_CTRL); | ||
| 227 | } | ||
| 228 | #endif | ||
| 229 | |||
| 38 | static const struct of_device_id matches[] __initconst = { | 230 | static const struct of_device_id matches[] __initconst = { |
| 231 | { .compatible = "nvidia,tegra114-pmc" }, | ||
| 232 | { .compatible = "nvidia,tegra30-pmc" }, | ||
| 39 | { .compatible = "nvidia,tegra20-pmc" }, | 233 | { .compatible = "nvidia,tegra20-pmc" }, |
| 40 | { } | 234 | { } |
| 41 | }; | 235 | }; |
| 42 | #endif | ||
| 43 | 236 | ||
| 44 | void __init tegra_pmc_init(void) | 237 | static void tegra_pmc_parse_dt(void) |
| 45 | { | 238 | { |
| 46 | /* | 239 | struct device_node *np; |
| 47 | * For now, Harmony is the only board that uses the PMC, and it wants | 240 | u32 prop; |
| 48 | * the signal inverted. Seaboard would too if it used the PMC. | 241 | enum tegra_suspend_mode suspend_mode; |
| 49 | * Hopefully by the time other boards want to use the PMC, everything | 242 | u32 core_good_time[2] = {0, 0}; |
| 50 | * will be device-tree, or they also want it inverted. | 243 | u32 lp0_vec[2] = {0, 0}; |
| 51 | */ | ||
| 52 | bool invert_interrupt = true; | ||
| 53 | u32 val; | ||
| 54 | 244 | ||
| 55 | #ifdef CONFIG_OF | 245 | np = of_find_matching_node(NULL, matches); |
| 56 | if (of_have_populated_dt()) { | 246 | BUG_ON(!np); |
| 57 | struct device_node *np; | ||
| 58 | 247 | ||
| 59 | invert_interrupt = false; | 248 | tegra_pmc_base = of_iomap(np, 0); |
| 60 | 249 | ||
| 61 | np = of_find_matching_node(NULL, matches); | 250 | tegra_pmc_invert_interrupt = of_property_read_bool(np, |
| 62 | if (np) { | 251 | "nvidia,invert-interrupt"); |
| 63 | if (of_find_property(np, "nvidia,invert-interrupt", | 252 | tegra_pclk = of_clk_get_by_name(np, "pclk"); |
| 64 | NULL)) | 253 | WARN_ON(IS_ERR(tegra_pclk)); |
| 65 | invert_interrupt = true; | 254 | |
| 255 | /* Grabbing the power management configurations */ | ||
| 256 | if (of_property_read_u32(np, "nvidia,suspend-mode", &prop)) { | ||
| 257 | suspend_mode = TEGRA_SUSPEND_NONE; | ||
| 258 | } else { | ||
| 259 | switch (prop) { | ||
| 260 | case 0: | ||
| 261 | suspend_mode = TEGRA_SUSPEND_LP0; | ||
| 262 | break; | ||
| 263 | case 1: | ||
| 264 | suspend_mode = TEGRA_SUSPEND_LP1; | ||
| 265 | break; | ||
| 266 | case 2: | ||
| 267 | suspend_mode = TEGRA_SUSPEND_LP2; | ||
| 268 | break; | ||
| 269 | default: | ||
| 270 | suspend_mode = TEGRA_SUSPEND_NONE; | ||
| 271 | break; | ||
| 66 | } | 272 | } |
| 67 | } | 273 | } |
| 68 | #endif | 274 | suspend_mode = tegra_pm_validate_suspend_mode(suspend_mode); |
| 275 | |||
| 276 | if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &prop)) | ||
| 277 | suspend_mode = TEGRA_SUSPEND_NONE; | ||
| 278 | pmc_pm_data.cpu_good_time = prop; | ||
| 279 | |||
| 280 | if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &prop)) | ||
| 281 | suspend_mode = TEGRA_SUSPEND_NONE; | ||
| 282 | pmc_pm_data.cpu_off_time = prop; | ||
| 283 | |||
| 284 | if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time", | ||
| 285 | core_good_time, ARRAY_SIZE(core_good_time))) | ||
| 286 | suspend_mode = TEGRA_SUSPEND_NONE; | ||
| 287 | pmc_pm_data.core_osc_time = core_good_time[0]; | ||
| 288 | pmc_pm_data.core_pmu_time = core_good_time[1]; | ||
| 289 | |||
| 290 | if (of_property_read_u32(np, "nvidia,core-pwr-off-time", | ||
| 291 | &prop)) | ||
| 292 | suspend_mode = TEGRA_SUSPEND_NONE; | ||
| 293 | pmc_pm_data.core_off_time = prop; | ||
| 294 | |||
| 295 | pmc_pm_data.corereq_high = of_property_read_bool(np, | ||
| 296 | "nvidia,core-power-req-active-high"); | ||
| 297 | |||
| 298 | pmc_pm_data.sysclkreq_high = of_property_read_bool(np, | ||
| 299 | "nvidia,sys-clock-req-active-high"); | ||
| 300 | |||
| 301 | pmc_pm_data.combined_req = of_property_read_bool(np, | ||
| 302 | "nvidia,combined-power-req"); | ||
| 303 | |||
| 304 | pmc_pm_data.cpu_pwr_good_en = of_property_read_bool(np, | ||
| 305 | "nvidia,cpu-pwr-good-en"); | ||
| 306 | |||
| 307 | if (of_property_read_u32_array(np, "nvidia,lp0-vec", lp0_vec, | ||
| 308 | ARRAY_SIZE(lp0_vec))) | ||
| 309 | if (suspend_mode == TEGRA_SUSPEND_LP0) | ||
| 310 | suspend_mode = TEGRA_SUSPEND_LP1; | ||
| 311 | |||
| 312 | pmc_pm_data.lp0_vec_phy_addr = lp0_vec[0]; | ||
| 313 | pmc_pm_data.lp0_vec_size = lp0_vec[1]; | ||
| 314 | |||
| 315 | pmc_pm_data.suspend_mode = suspend_mode; | ||
| 316 | } | ||
| 317 | |||
| 318 | void __init tegra_pmc_init(void) | ||
| 319 | { | ||
| 320 | u32 val; | ||
| 321 | |||
| 322 | tegra_pmc_parse_dt(); | ||
| 69 | 323 | ||
| 70 | val = tegra_pmc_readl(PMC_CTRL); | 324 | val = tegra_pmc_readl(PMC_CTRL); |
| 71 | if (invert_interrupt) | 325 | if (tegra_pmc_invert_interrupt) |
| 72 | val |= PMC_CTRL_INTR_LOW; | 326 | val |= PMC_CTRL_INTR_LOW; |
| 73 | else | 327 | else |
| 74 | val &= ~PMC_CTRL_INTR_LOW; | 328 | val &= ~PMC_CTRL_INTR_LOW; |
diff --git a/arch/arm/mach-tegra/pmc.h b/arch/arm/mach-tegra/pmc.h index 8995ee4a8768..e1c2df272f7d 100644 --- a/arch/arm/mach-tegra/pmc.h +++ b/arch/arm/mach-tegra/pmc.h | |||
| @@ -18,6 +18,24 @@ | |||
| 18 | #ifndef __MACH_TEGRA_PMC_H | 18 | #ifndef __MACH_TEGRA_PMC_H |
| 19 | #define __MACH_TEGRA_PMC_H | 19 | #define __MACH_TEGRA_PMC_H |
| 20 | 20 | ||
| 21 | enum tegra_suspend_mode { | ||
| 22 | TEGRA_SUSPEND_NONE = 0, | ||
| 23 | TEGRA_SUSPEND_LP2, /* CPU voltage off */ | ||
| 24 | TEGRA_SUSPEND_LP1, /* CPU voltage off, DRAM self-refresh */ | ||
| 25 | TEGRA_SUSPEND_LP0, /* CPU + core voltage off, DRAM self-refresh */ | ||
| 26 | TEGRA_MAX_SUSPEND_MODE, | ||
| 27 | }; | ||
| 28 | |||
| 29 | #ifdef CONFIG_PM_SLEEP | ||
| 30 | enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void); | ||
| 31 | void tegra_pmc_pm_set(enum tegra_suspend_mode mode); | ||
| 32 | void tegra_pmc_suspend_init(void); | ||
| 33 | #endif | ||
| 34 | |||
| 35 | bool tegra_pmc_cpu_is_powered(int cpuid); | ||
| 36 | int tegra_pmc_cpu_power_on(int cpuid); | ||
| 37 | int tegra_pmc_cpu_remove_clamping(int cpuid); | ||
| 38 | |||
| 21 | void tegra_pmc_init(void); | 39 | void tegra_pmc_init(void); |
| 22 | 40 | ||
| 23 | #endif | 41 | #endif |
diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S index 54382ceade4a..1676aba5e7b8 100644 --- a/arch/arm/mach-tegra/reset-handler.S +++ b/arch/arm/mach-tegra/reset-handler.S | |||
| @@ -41,9 +41,6 @@ | |||
| 41 | */ | 41 | */ |
| 42 | ENTRY(tegra_resume) | 42 | ENTRY(tegra_resume) |
| 43 | bl v7_invalidate_l1 | 43 | bl v7_invalidate_l1 |
| 44 | /* Enable coresight */ | ||
| 45 | mov32 r0, 0xC5ACCE55 | ||
| 46 | mcr p14, 0, r0, c7, c12, 6 | ||
| 47 | 44 | ||
| 48 | cpu_id r0 | 45 | cpu_id r0 |
| 49 | cmp r0, #0 @ CPU0? | 46 | cmp r0, #0 @ CPU0? |
| @@ -99,6 +96,8 @@ ENTRY(__tegra_cpu_reset_handler_start) | |||
| 99 | * | 96 | * |
| 100 | * Register usage within the reset handler: | 97 | * Register usage within the reset handler: |
| 101 | * | 98 | * |
| 99 | * Others: scratch | ||
| 100 | * R6 = SoC ID << 8 | ||
| 102 | * R7 = CPU present (to the OS) mask | 101 | * R7 = CPU present (to the OS) mask |
| 103 | * R8 = CPU in LP1 state mask | 102 | * R8 = CPU in LP1 state mask |
| 104 | * R9 = CPU in LP2 state mask | 103 | * R9 = CPU in LP2 state mask |
| @@ -114,6 +113,40 @@ ENTRY(__tegra_cpu_reset_handler_start) | |||
| 114 | ENTRY(__tegra_cpu_reset_handler) | 113 | ENTRY(__tegra_cpu_reset_handler) |
| 115 | 114 | ||
| 116 | cpsid aif, 0x13 @ SVC mode, interrupts disabled | 115 | cpsid aif, 0x13 @ SVC mode, interrupts disabled |
| 116 | |||
| 117 | mov32 r6, TEGRA_APB_MISC_BASE | ||
| 118 | ldr r6, [r6, #APB_MISC_GP_HIDREV] | ||
| 119 | and r6, r6, #0xff00 | ||
| 120 | #ifdef CONFIG_ARCH_TEGRA_2x_SOC | ||
| 121 | t20_check: | ||
| 122 | cmp r6, #(0x20 << 8) | ||
| 123 | bne after_t20_check | ||
| 124 | t20_errata: | ||
| 125 | # Tegra20 is a Cortex-A9 r1p1 | ||
| 126 | mrc p15, 0, r0, c1, c0, 0 @ read system control register | ||
| 127 | orr r0, r0, #1 << 14 @ erratum 716044 | ||
| 128 | mcr p15, 0, r0, c1, c0, 0 @ write system control register | ||
| 129 | mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register | ||
| 130 | orr r0, r0, #1 << 4 @ erratum 742230 | ||
| 131 | orr r0, r0, #1 << 11 @ erratum 751472 | ||
| 132 | mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register | ||
| 133 | b after_errata | ||
| 134 | after_t20_check: | ||
| 135 | #endif | ||
| 136 | #ifdef CONFIG_ARCH_TEGRA_3x_SOC | ||
| 137 | t30_check: | ||
| 138 | cmp r6, #(0x30 << 8) | ||
| 139 | bne after_t30_check | ||
| 140 | t30_errata: | ||
| 141 | # Tegra30 is a Cortex-A9 r2p9 | ||
| 142 | mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register | ||
| 143 | orr r0, r0, #1 << 6 @ erratum 743622 | ||
| 144 | orr r0, r0, #1 << 11 @ erratum 751472 | ||
| 145 | mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register | ||
| 146 | b after_errata | ||
| 147 | after_t30_check: | ||
| 148 | #endif | ||
| 149 | after_errata: | ||
| 117 | mrc p15, 0, r10, c0, c0, 5 @ MPIDR | 150 | mrc p15, 0, r10, c0, c0, 5 @ MPIDR |
| 118 | and r10, r10, #0x3 @ R10 = CPU number | 151 | and r10, r10, #0x3 @ R10 = CPU number |
| 119 | mov r11, #1 | 152 | mov r11, #1 |
| @@ -129,16 +162,13 @@ ENTRY(__tegra_cpu_reset_handler) | |||
| 129 | 162 | ||
| 130 | #ifdef CONFIG_ARCH_TEGRA_2x_SOC | 163 | #ifdef CONFIG_ARCH_TEGRA_2x_SOC |
| 131 | /* Are we on Tegra20? */ | 164 | /* Are we on Tegra20? */ |
| 132 | mov32 r6, TEGRA_APB_MISC_BASE | 165 | cmp r6, #(0x20 << 8) |
| 133 | ldr r0, [r6, #APB_MISC_GP_HIDREV] | ||
| 134 | and r0, r0, #0xff00 | ||
| 135 | cmp r0, #(0x20 << 8) | ||
| 136 | bne 1f | 166 | bne 1f |
| 137 | /* If not CPU0, don't let CPU0 reset CPU1 now that CPU1 is coming up. */ | 167 | /* If not CPU0, don't let CPU0 reset CPU1 now that CPU1 is coming up. */ |
| 138 | mov32 r6, TEGRA_PMC_BASE | 168 | mov32 r5, TEGRA_PMC_BASE |
| 139 | mov r0, #0 | 169 | mov r0, #0 |
| 140 | cmp r10, #0 | 170 | cmp r10, #0 |
| 141 | strne r0, [r6, #PMC_SCRATCH41] | 171 | strne r0, [r5, #PMC_SCRATCH41] |
| 142 | 1: | 172 | 1: |
| 143 | #endif | 173 | #endif |
| 144 | 174 | ||
diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h index 4ffae541726e..970ebd5138b9 100644 --- a/arch/arm/mach-tegra/sleep.h +++ b/arch/arm/mach-tegra/sleep.h | |||
| @@ -1,5 +1,5 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved. | 2 | * Copyright (c) 2010-2013, NVIDIA Corporation. All rights reserved. |
| 3 | * | 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
| 5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
| @@ -124,11 +124,11 @@ int tegra_sleep_cpu_finish(unsigned long); | |||
| 124 | void tegra_disable_clean_inv_dcache(void); | 124 | void tegra_disable_clean_inv_dcache(void); |
| 125 | 125 | ||
| 126 | #ifdef CONFIG_HOTPLUG_CPU | 126 | #ifdef CONFIG_HOTPLUG_CPU |
| 127 | void tegra20_hotplug_init(void); | 127 | void tegra20_hotplug_shutdown(void); |
| 128 | void tegra30_hotplug_init(void); | 128 | void tegra30_hotplug_shutdown(void); |
| 129 | void tegra_hotplug_init(void); | ||
| 129 | #else | 130 | #else |
| 130 | static inline void tegra20_hotplug_init(void) {} | 131 | static inline void tegra_hotplug_init(void) {} |
| 131 | static inline void tegra30_hotplug_init(void) {} | ||
| 132 | #endif | 132 | #endif |
| 133 | 133 | ||
| 134 | void tegra20_cpu_shutdown(int cpu); | 134 | void tegra20_cpu_shutdown(int cpu); |
diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c b/arch/arm/mach-tegra/tegra.c index a0edf2510280..61749e2d8111 100644 --- a/arch/arm/mach-tegra/board-dt-tegra20.c +++ b/arch/arm/mach-tegra/tegra.c | |||
| @@ -1,6 +1,7 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * nVidia Tegra device tree board support | 2 | * NVIDIA Tegra SoC device tree board support |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2011, 2013, NVIDIA Corporation | ||
| 4 | * Copyright (C) 2010 Secret Lab Technologies, Ltd. | 5 | * Copyright (C) 2010 Secret Lab Technologies, Ltd. |
| 5 | * Copyright (C) 2010 Google, Inc. | 6 | * Copyright (C) 2010 Google, Inc. |
| 6 | * | 7 | * |
| @@ -32,7 +33,10 @@ | |||
| 32 | #include <linux/io.h> | 33 | #include <linux/io.h> |
| 33 | #include <linux/i2c.h> | 34 | #include <linux/i2c.h> |
| 34 | #include <linux/i2c-tegra.h> | 35 | #include <linux/i2c-tegra.h> |
| 36 | #include <linux/slab.h> | ||
| 37 | #include <linux/sys_soc.h> | ||
| 35 | #include <linux/usb/tegra_usb_phy.h> | 38 | #include <linux/usb/tegra_usb_phy.h> |
| 39 | #include <linux/clk/tegra.h> | ||
| 36 | 40 | ||
| 37 | #include <asm/mach-types.h> | 41 | #include <asm/mach-types.h> |
| 38 | #include <asm/mach/arch.h> | 42 | #include <asm/mach/arch.h> |
| @@ -41,6 +45,7 @@ | |||
| 41 | 45 | ||
| 42 | #include "board.h" | 46 | #include "board.h" |
| 43 | #include "common.h" | 47 | #include "common.h" |
| 48 | #include "fuse.h" | ||
| 44 | #include "iomap.h" | 49 | #include "iomap.h" |
| 45 | 50 | ||
| 46 | static struct tegra_ehci_platform_data tegra_ehci1_pdata = { | 51 | static struct tegra_ehci_platform_data tegra_ehci1_pdata = { |
| @@ -79,12 +84,38 @@ static struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = { | |||
| 79 | 84 | ||
| 80 | static void __init tegra_dt_init(void) | 85 | static void __init tegra_dt_init(void) |
| 81 | { | 86 | { |
| 87 | struct soc_device_attribute *soc_dev_attr; | ||
| 88 | struct soc_device *soc_dev; | ||
| 89 | struct device *parent = NULL; | ||
| 90 | |||
| 91 | tegra_clocks_apply_init_table(); | ||
| 92 | |||
| 93 | soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); | ||
| 94 | if (!soc_dev_attr) | ||
| 95 | goto out; | ||
| 96 | |||
| 97 | soc_dev_attr->family = kasprintf(GFP_KERNEL, "Tegra"); | ||
| 98 | soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%d", tegra_revision); | ||
| 99 | soc_dev_attr->soc_id = kasprintf(GFP_KERNEL, "%d", tegra_chip_id); | ||
| 100 | |||
| 101 | soc_dev = soc_device_register(soc_dev_attr); | ||
| 102 | if (IS_ERR(soc_dev)) { | ||
| 103 | kfree(soc_dev_attr->family); | ||
| 104 | kfree(soc_dev_attr->revision); | ||
| 105 | kfree(soc_dev_attr->soc_id); | ||
| 106 | kfree(soc_dev_attr); | ||
| 107 | goto out; | ||
| 108 | } | ||
| 109 | |||
| 110 | parent = soc_device_to_device(soc_dev); | ||
| 111 | |||
| 82 | /* | 112 | /* |
| 83 | * Finished with the static registrations now; fill in the missing | 113 | * Finished with the static registrations now; fill in the missing |
| 84 | * devices | 114 | * devices |
| 85 | */ | 115 | */ |
| 116 | out: | ||
| 86 | of_platform_populate(NULL, of_default_bus_match_table, | 117 | of_platform_populate(NULL, of_default_bus_match_table, |
| 87 | tegra20_auxdata_lookup, NULL); | 118 | tegra20_auxdata_lookup, parent); |
| 88 | } | 119 | } |
| 89 | 120 | ||
| 90 | static void __init trimslice_init(void) | 121 | static void __init trimslice_init(void) |
| @@ -111,7 +142,8 @@ static void __init harmony_init(void) | |||
| 111 | 142 | ||
| 112 | static void __init paz00_init(void) | 143 | static void __init paz00_init(void) |
| 113 | { | 144 | { |
| 114 | tegra_paz00_wifikill_init(); | 145 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC)) |
| 146 | tegra_paz00_wifikill_init(); | ||
| 115 | } | 147 | } |
| 116 | 148 | ||
| 117 | static struct { | 149 | static struct { |
| @@ -137,19 +169,21 @@ static void __init tegra_dt_init_late(void) | |||
| 137 | } | 169 | } |
| 138 | } | 170 | } |
| 139 | 171 | ||
| 140 | static const char *tegra20_dt_board_compat[] = { | 172 | static const char * const tegra_dt_board_compat[] = { |
| 173 | "nvidia,tegra114", | ||
| 174 | "nvidia,tegra30", | ||
| 141 | "nvidia,tegra20", | 175 | "nvidia,tegra20", |
| 142 | NULL | 176 | NULL |
| 143 | }; | 177 | }; |
| 144 | 178 | ||
| 145 | DT_MACHINE_START(TEGRA_DT, "nVidia Tegra20 (Flattened Device Tree)") | 179 | DT_MACHINE_START(TEGRA_DT, "NVIDIA Tegra SoC (Flattened Device Tree)") |
| 146 | .map_io = tegra_map_common_io, | 180 | .map_io = tegra_map_common_io, |
| 147 | .smp = smp_ops(tegra_smp_ops), | 181 | .smp = smp_ops(tegra_smp_ops), |
| 148 | .init_early = tegra20_init_early, | 182 | .init_early = tegra_init_early, |
| 149 | .init_irq = tegra_dt_init_irq, | 183 | .init_irq = tegra_dt_init_irq, |
| 150 | .init_time = clocksource_of_init, | 184 | .init_time = clocksource_of_init, |
| 151 | .init_machine = tegra_dt_init, | 185 | .init_machine = tegra_dt_init, |
| 152 | .init_late = tegra_dt_init_late, | 186 | .init_late = tegra_dt_init_late, |
| 153 | .restart = tegra_assert_system_reset, | 187 | .restart = tegra_assert_system_reset, |
| 154 | .dt_compat = tegra20_dt_board_compat, | 188 | .dt_compat = tegra_dt_board_compat, |
| 155 | MACHINE_END | 189 | MACHINE_END |
diff --git a/arch/arm/mach-tegra/tegra114_speedo.c b/arch/arm/mach-tegra/tegra114_speedo.c new file mode 100644 index 000000000000..5218d4853cd3 --- /dev/null +++ b/arch/arm/mach-tegra/tegra114_speedo.c | |||
| @@ -0,0 +1,104 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify it | ||
| 5 | * under the terms and conditions of the GNU General Public License, | ||
| 6 | * version 2, as published by the Free Software Foundation. | ||
| 7 | * | ||
| 8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
| 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 11 | * more details. | ||
| 12 | * | ||
| 13 | * You should have received a copy of the GNU General Public License | ||
| 14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
| 15 | */ | ||
| 16 | |||
| 17 | #include <linux/kernel.h> | ||
| 18 | #include <linux/bug.h> | ||
| 19 | |||
| 20 | #include "fuse.h" | ||
| 21 | |||
| 22 | #define CORE_PROCESS_CORNERS_NUM 2 | ||
| 23 | #define CPU_PROCESS_CORNERS_NUM 2 | ||
| 24 | |||
| 25 | enum { | ||
| 26 | THRESHOLD_INDEX_0, | ||
| 27 | THRESHOLD_INDEX_1, | ||
| 28 | THRESHOLD_INDEX_COUNT, | ||
| 29 | }; | ||
| 30 | |||
| 31 | static const u32 core_process_speedos[][CORE_PROCESS_CORNERS_NUM] = { | ||
| 32 | {1123, UINT_MAX}, | ||
| 33 | {0, UINT_MAX}, | ||
| 34 | }; | ||
| 35 | |||
| 36 | static const u32 cpu_process_speedos[][CPU_PROCESS_CORNERS_NUM] = { | ||
| 37 | {1695, UINT_MAX}, | ||
| 38 | {0, UINT_MAX}, | ||
| 39 | }; | ||
| 40 | |||
| 41 | static void rev_sku_to_speedo_ids(int rev, int sku, int *threshold) | ||
| 42 | { | ||
| 43 | u32 tmp; | ||
| 44 | |||
| 45 | switch (sku) { | ||
| 46 | case 0x00: | ||
| 47 | case 0x10: | ||
| 48 | case 0x05: | ||
| 49 | case 0x06: | ||
| 50 | tegra_cpu_speedo_id = 1; | ||
| 51 | tegra_soc_speedo_id = 0; | ||
| 52 | *threshold = THRESHOLD_INDEX_0; | ||
| 53 | break; | ||
| 54 | |||
| 55 | case 0x03: | ||
| 56 | case 0x04: | ||
| 57 | tegra_cpu_speedo_id = 2; | ||
| 58 | tegra_soc_speedo_id = 1; | ||
| 59 | *threshold = THRESHOLD_INDEX_1; | ||
| 60 | break; | ||
| 61 | |||
| 62 | default: | ||
| 63 | pr_err("Tegra114 Unknown SKU %d\n", sku); | ||
| 64 | tegra_cpu_speedo_id = 0; | ||
| 65 | tegra_soc_speedo_id = 0; | ||
| 66 | *threshold = THRESHOLD_INDEX_0; | ||
| 67 | break; | ||
| 68 | } | ||
| 69 | |||
| 70 | if (rev == TEGRA_REVISION_A01) { | ||
| 71 | tmp = tegra_fuse_readl(0x270) << 1; | ||
| 72 | tmp |= tegra_fuse_readl(0x26c); | ||
| 73 | if (!tmp) | ||
| 74 | tegra_cpu_speedo_id = 0; | ||
| 75 | } | ||
| 76 | } | ||
| 77 | |||
| 78 | void tegra114_init_speedo_data(void) | ||
| 79 | { | ||
| 80 | u32 cpu_speedo_val; | ||
| 81 | u32 core_speedo_val; | ||
| 82 | int threshold; | ||
| 83 | int i; | ||
| 84 | |||
| 85 | BUILD_BUG_ON(ARRAY_SIZE(cpu_process_speedos) != | ||
| 86 | THRESHOLD_INDEX_COUNT); | ||
| 87 | BUILD_BUG_ON(ARRAY_SIZE(core_process_speedos) != | ||
| 88 | THRESHOLD_INDEX_COUNT); | ||
| 89 | |||
| 90 | rev_sku_to_speedo_ids(tegra_revision, tegra_sku_id, &threshold); | ||
| 91 | |||
| 92 | cpu_speedo_val = tegra_fuse_readl(0x12c) + 1024; | ||
| 93 | core_speedo_val = tegra_fuse_readl(0x134); | ||
| 94 | |||
| 95 | for (i = 0; i < CPU_PROCESS_CORNERS_NUM; i++) | ||
| 96 | if (cpu_speedo_val < cpu_process_speedos[threshold][i]) | ||
| 97 | break; | ||
| 98 | tegra_cpu_process_id = i; | ||
| 99 | |||
| 100 | for (i = 0; i < CORE_PROCESS_CORNERS_NUM; i++) | ||
| 101 | if (core_speedo_val < core_process_speedos[threshold][i]) | ||
| 102 | break; | ||
| 103 | tegra_core_process_id = i; | ||
| 104 | } | ||
diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c index 0a3f30df1eb8..152ae38cd18c 100644 --- a/arch/arm/mach-ux500/board-mop500-pins.c +++ b/arch/arm/mach-ux500/board-mop500-pins.c | |||
| @@ -48,8 +48,12 @@ BIAS(slpm_in_nopull_wkup, PIN_SLEEPMODE_ENABLED| | |||
| 48 | PIN_SLPM_DIR_INPUT|PIN_SLPM_PULL_NONE|PIN_SLPM_WAKEUP_ENABLE); | 48 | PIN_SLPM_DIR_INPUT|PIN_SLPM_PULL_NONE|PIN_SLPM_WAKEUP_ENABLE); |
| 49 | BIAS(slpm_in_wkup_pdis, PIN_SLEEPMODE_ENABLED| | 49 | BIAS(slpm_in_wkup_pdis, PIN_SLEEPMODE_ENABLED| |
| 50 | PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED); | 50 | PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED); |
| 51 | BIAS(slpm_in_wkup_pdis_en, PIN_SLEEPMODE_ENABLED| | ||
| 52 | PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_ENABLED); | ||
| 51 | BIAS(slpm_wkup_pdis, PIN_SLEEPMODE_ENABLED| | 53 | BIAS(slpm_wkup_pdis, PIN_SLEEPMODE_ENABLED| |
| 52 | PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED); | 54 | PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED); |
| 55 | BIAS(slpm_wkup_pdis_en, PIN_SLEEPMODE_ENABLED| | ||
| 56 | PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_ENABLED); | ||
| 53 | BIAS(slpm_out_lo_pdis, PIN_SLEEPMODE_ENABLED| | 57 | BIAS(slpm_out_lo_pdis, PIN_SLEEPMODE_ENABLED| |
| 54 | PIN_SLPM_OUTPUT_LOW|PIN_SLPM_WAKEUP_DISABLE|PIN_SLPM_PDIS_DISABLED); | 58 | PIN_SLPM_OUTPUT_LOW|PIN_SLPM_WAKEUP_DISABLE|PIN_SLPM_PDIS_DISABLED); |
| 55 | BIAS(slpm_out_lo_wkup, PIN_SLEEPMODE_ENABLED| | 59 | BIAS(slpm_out_lo_wkup, PIN_SLEEPMODE_ENABLED| |
| @@ -78,9 +82,6 @@ BIAS(out_wkup_pdis, PIN_SLPM_DIR_OUTPUT|PIN_SLPM_WAKEUP_ENABLE| | |||
| 78 | PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-db8500", group, func) | 82 | PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-db8500", group, func) |
| 79 | #define DB8500_PIN_HOG(pin,conf) \ | 83 | #define DB8500_PIN_HOG(pin,conf) \ |
| 80 | PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-db8500", pin, conf) | 84 | PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-db8500", pin, conf) |
| 81 | #define DB8500_PIN_SLEEP(pin, conf, dev) \ | ||
| 82 | PIN_MAP_CONFIGS_PIN(dev, PINCTRL_STATE_SLEEP, "pinctrl-db8500", \ | ||
| 83 | pin, conf) | ||
| 84 | 85 | ||
| 85 | /* These are default states associated with device and changed runtime */ | 86 | /* These are default states associated with device and changed runtime */ |
| 86 | #define DB8500_MUX(group,func,dev) \ | 87 | #define DB8500_MUX(group,func,dev) \ |
| @@ -309,8 +310,23 @@ static struct pinctrl_map __initdata mop500_family_pinmap[] = { | |||
| 309 | DB8500_PIN_SLEEP("GPIO207_AJ23", slpm_in_wkup_pdis, "sdi4"), /* DAT4 */ | 310 | DB8500_PIN_SLEEP("GPIO207_AJ23", slpm_in_wkup_pdis, "sdi4"), /* DAT4 */ |
| 310 | 311 | ||
| 311 | /* Mux in USB pins, drive STP high */ | 312 | /* Mux in USB pins, drive STP high */ |
| 312 | DB8500_MUX("usb_a_1", "usb", "musb-ux500.0"), | 313 | /* USB default state */ |
| 313 | DB8500_PIN("GPIO257_AE29", out_hi, "musb-ux500.0"), /* STP */ | 314 | DB8500_MUX("usb_a_1", "usb", "ab8500-usb.0"), |
| 315 | DB8500_PIN("GPIO257_AE29", out_hi, "ab8500-usb.0"), /* STP */ | ||
| 316 | /* USB sleep state */ | ||
| 317 | DB8500_PIN_SLEEP("GPIO256_AF28", slpm_wkup_pdis_en, "ab8500-usb.0"), /* NXT */ | ||
| 318 | DB8500_PIN_SLEEP("GPIO257_AE29", slpm_out_hi_wkup_pdis, "ab8500-usb.0"), /* STP */ | ||
| 319 | DB8500_PIN_SLEEP("GPIO258_AD29", slpm_wkup_pdis_en, "ab8500-usb.0"), /* XCLK */ | ||
| 320 | DB8500_PIN_SLEEP("GPIO259_AC29", slpm_wkup_pdis_en, "ab8500-usb.0"), /* DIR */ | ||
| 321 | DB8500_PIN_SLEEP("GPIO260_AD28", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT7 */ | ||
| 322 | DB8500_PIN_SLEEP("GPIO261_AD26", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT6 */ | ||
| 323 | DB8500_PIN_SLEEP("GPIO262_AE26", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT5 */ | ||
| 324 | DB8500_PIN_SLEEP("GPIO263_AG29", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT4 */ | ||
| 325 | DB8500_PIN_SLEEP("GPIO264_AE27", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT3 */ | ||
| 326 | DB8500_PIN_SLEEP("GPIO265_AD27", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT2 */ | ||
| 327 | DB8500_PIN_SLEEP("GPIO266_AC28", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT1 */ | ||
| 328 | DB8500_PIN_SLEEP("GPIO267_AC27", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT0 */ | ||
| 329 | |||
| 314 | /* Mux in SPI2 pins on the "other C1" altfunction */ | 330 | /* Mux in SPI2 pins on the "other C1" altfunction */ |
| 315 | DB8500_MUX("spi2_oc1_2", "spi2", "spi2"), | 331 | DB8500_MUX("spi2_oc1_2", "spi2", "spi2"), |
| 316 | DB8500_PIN("GPIO216_AG12", gpio_out_hi, "spi2"), /* FRM */ | 332 | DB8500_PIN("GPIO216_AG12", gpio_out_hi, "spi2"), /* FRM */ |
| @@ -318,9 +334,9 @@ static struct pinctrl_map __initdata mop500_family_pinmap[] = { | |||
| 318 | DB8500_PIN("GPIO215_AH13", out_lo, "spi2"), /* TXD */ | 334 | DB8500_PIN("GPIO215_AH13", out_lo, "spi2"), /* TXD */ |
| 319 | DB8500_PIN("GPIO217_AH12", out_lo, "spi2"), /* CLK */ | 335 | DB8500_PIN("GPIO217_AH12", out_lo, "spi2"), /* CLK */ |
| 320 | /* SPI2 idle state */ | 336 | /* SPI2 idle state */ |
| 321 | DB8500_PIN_SLEEP("GPIO218_AH11", slpm_in_wkup_pdis, "spi2"), /* RXD */ | 337 | DB8500_PIN_IDLE("GPIO218_AH11", slpm_in_wkup_pdis, "spi2"), /* RXD */ |
| 322 | DB8500_PIN_SLEEP("GPIO215_AH13", slpm_out_lo_wkup_pdis, "spi2"), /* TXD */ | 338 | DB8500_PIN_IDLE("GPIO215_AH13", slpm_out_lo_wkup_pdis, "spi2"), /* TXD */ |
| 323 | DB8500_PIN_SLEEP("GPIO217_AH12", slpm_wkup_pdis, "spi2"), /* CLK */ | 339 | DB8500_PIN_IDLE("GPIO217_AH12", slpm_wkup_pdis, "spi2"), /* CLK */ |
| 324 | /* SPI2 sleep state */ | 340 | /* SPI2 sleep state */ |
| 325 | DB8500_PIN_SLEEP("GPIO216_AG12", slpm_in_wkup_pdis, "spi2"), /* FRM */ | 341 | DB8500_PIN_SLEEP("GPIO216_AG12", slpm_in_wkup_pdis, "spi2"), /* FRM */ |
| 326 | DB8500_PIN_SLEEP("GPIO218_AH11", slpm_in_wkup_pdis, "spi2"), /* RXD */ | 342 | DB8500_PIN_SLEEP("GPIO218_AH11", slpm_in_wkup_pdis, "spi2"), /* RXD */ |
| @@ -747,6 +763,8 @@ static struct pinctrl_map __initdata snowball_pinmap[] = { | |||
| 747 | DB8500_PIN_HOG("GPIO21_AB3", out_hi), | 763 | DB8500_PIN_HOG("GPIO21_AB3", out_hi), |
| 748 | /* Mux in "SM" which is used for the SMSC911x Ethernet adapter */ | 764 | /* Mux in "SM" which is used for the SMSC911x Ethernet adapter */ |
| 749 | DB8500_MUX_HOG("sm_b_1", "sm"), | 765 | DB8500_MUX_HOG("sm_b_1", "sm"), |
| 766 | /* User LED */ | ||
| 767 | DB8500_PIN_HOG("GPIO142_C11", gpio_out_hi), | ||
| 750 | /* Drive RSTn_LAN high */ | 768 | /* Drive RSTn_LAN high */ |
| 751 | DB8500_PIN_HOG("GPIO141_C12", gpio_out_hi), | 769 | DB8500_PIN_HOG("GPIO141_C12", gpio_out_hi), |
| 752 | /* Accelerometer/Magnetometer */ | 770 | /* Accelerometer/Magnetometer */ |
diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c index 051b62c27102..7f2cb6c5e2c1 100644 --- a/arch/arm/mach-ux500/board-mop500-sdi.c +++ b/arch/arm/mach-ux500/board-mop500-sdi.c | |||
| @@ -81,7 +81,6 @@ static struct stedma40_chan_cfg mop500_sdi0_dma_cfg_tx = { | |||
| 81 | #endif | 81 | #endif |
| 82 | 82 | ||
| 83 | struct mmci_platform_data mop500_sdi0_data = { | 83 | struct mmci_platform_data mop500_sdi0_data = { |
| 84 | .ios_handler = mop500_sdi0_ios_handler, | ||
| 85 | .ocr_mask = MMC_VDD_29_30, | 84 | .ocr_mask = MMC_VDD_29_30, |
| 86 | .f_max = 50000000, | 85 | .f_max = 50000000, |
| 87 | .capabilities = MMC_CAP_4_BIT_DATA | | 86 | .capabilities = MMC_CAP_4_BIT_DATA | |
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c index b03457881c4b..87d2d7b38ce9 100644 --- a/arch/arm/mach-ux500/board-mop500.c +++ b/arch/arm/mach-ux500/board-mop500.c | |||
| @@ -12,6 +12,7 @@ | |||
| 12 | #include <linux/init.h> | 12 | #include <linux/init.h> |
| 13 | #include <linux/interrupt.h> | 13 | #include <linux/interrupt.h> |
| 14 | #include <linux/platform_device.h> | 14 | #include <linux/platform_device.h> |
| 15 | #include <linux/clk.h> | ||
| 15 | #include <linux/io.h> | 16 | #include <linux/io.h> |
| 16 | #include <linux/i2c.h> | 17 | #include <linux/i2c.h> |
| 17 | #include <linux/platform_data/i2c-nomadik.h> | 18 | #include <linux/platform_data/i2c-nomadik.h> |
| @@ -439,6 +440,15 @@ static void mop500_prox_deactivate(struct device *dev) | |||
| 439 | regulator_put(prox_regulator); | 440 | regulator_put(prox_regulator); |
| 440 | } | 441 | } |
| 441 | 442 | ||
| 443 | void mop500_snowball_ethernet_clock_enable(void) | ||
| 444 | { | ||
| 445 | struct clk *clk; | ||
| 446 | |||
| 447 | clk = clk_get_sys("fsmc", NULL); | ||
| 448 | if (!IS_ERR(clk)) | ||
| 449 | clk_prepare_enable(clk); | ||
| 450 | } | ||
| 451 | |||
| 442 | static struct cryp_platform_data u8500_cryp1_platform_data = { | 452 | static struct cryp_platform_data u8500_cryp1_platform_data = { |
| 443 | .mem_to_engine = { | 453 | .mem_to_engine = { |
| 444 | .dir = STEDMA40_MEM_TO_PERIPH, | 454 | .dir = STEDMA40_MEM_TO_PERIPH, |
| @@ -683,6 +693,8 @@ static void __init snowball_init_machine(void) | |||
| 683 | mop500_audio_init(parent); | 693 | mop500_audio_init(parent); |
| 684 | mop500_uart_init(parent); | 694 | mop500_uart_init(parent); |
| 685 | 695 | ||
| 696 | mop500_snowball_ethernet_clock_enable(); | ||
| 697 | |||
| 686 | /* This board has full regulator constraints */ | 698 | /* This board has full regulator constraints */ |
| 687 | regulator_has_full_constraints(); | 699 | regulator_has_full_constraints(); |
| 688 | } | 700 | } |
diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h index eaa605f5d90d..d38951be70df 100644 --- a/arch/arm/mach-ux500/board-mop500.h +++ b/arch/arm/mach-ux500/board-mop500.h | |||
| @@ -104,6 +104,7 @@ void __init mop500_pinmaps_init(void); | |||
| 104 | void __init snowball_pinmaps_init(void); | 104 | void __init snowball_pinmaps_init(void); |
| 105 | void __init hrefv60_pinmaps_init(void); | 105 | void __init hrefv60_pinmaps_init(void); |
| 106 | void mop500_audio_init(struct device *parent); | 106 | void mop500_audio_init(struct device *parent); |
| 107 | void mop500_snowball_ethernet_clock_enable(void); | ||
| 107 | 108 | ||
| 108 | int __init mop500_uib_init(void); | 109 | int __init mop500_uib_init(void); |
| 109 | void mop500_uib_i2c_add(int busnum, struct i2c_board_info *info, | 110 | void mop500_uib_i2c_add(int busnum, struct i2c_board_info *info, |
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c index 19235cf7bbe3..f1a581844372 100644 --- a/arch/arm/mach-ux500/cpu-db8500.c +++ b/arch/arm/mach-ux500/cpu-db8500.c | |||
| @@ -312,9 +312,10 @@ static void __init u8500_init_machine(void) | |||
| 312 | /* Pinmaps must be in place before devices register */ | 312 | /* Pinmaps must be in place before devices register */ |
| 313 | if (of_machine_is_compatible("st-ericsson,mop500")) | 313 | if (of_machine_is_compatible("st-ericsson,mop500")) |
| 314 | mop500_pinmaps_init(); | 314 | mop500_pinmaps_init(); |
| 315 | else if (of_machine_is_compatible("calaosystems,snowball-a9500")) | 315 | else if (of_machine_is_compatible("calaosystems,snowball-a9500")) { |
| 316 | snowball_pinmaps_init(); | 316 | snowball_pinmaps_init(); |
| 317 | else if (of_machine_is_compatible("st-ericsson,hrefv60+")) | 317 | mop500_snowball_ethernet_clock_enable(); |
| 318 | } else if (of_machine_is_compatible("st-ericsson,hrefv60+")) | ||
| 318 | hrefv60_pinmaps_init(); | 319 | hrefv60_pinmaps_init(); |
| 319 | else if (of_machine_is_compatible("st-ericsson,ccu9540")) {} | 320 | else if (of_machine_is_compatible("st-ericsson,ccu9540")) {} |
| 320 | /* TODO: Add pinmaps for ccu9540 board. */ | 321 | /* TODO: Add pinmaps for ccu9540 board. */ |
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c index 25160aeaa3b7..54bb80b012ac 100644 --- a/arch/arm/mach-versatile/core.c +++ b/arch/arm/mach-versatile/core.c | |||
| @@ -749,12 +749,25 @@ void versatile_restart(char mode, const char *cmd) | |||
| 749 | /* Early initializations */ | 749 | /* Early initializations */ |
| 750 | void __init versatile_init_early(void) | 750 | void __init versatile_init_early(void) |
| 751 | { | 751 | { |
| 752 | u32 val; | ||
| 752 | void __iomem *sys = __io_address(VERSATILE_SYS_BASE); | 753 | void __iomem *sys = __io_address(VERSATILE_SYS_BASE); |
| 753 | 754 | ||
| 754 | osc4_clk.vcoreg = sys + VERSATILE_SYS_OSCCLCD_OFFSET; | 755 | osc4_clk.vcoreg = sys + VERSATILE_SYS_OSCCLCD_OFFSET; |
| 755 | clkdev_add_table(lookups, ARRAY_SIZE(lookups)); | 756 | clkdev_add_table(lookups, ARRAY_SIZE(lookups)); |
| 756 | 757 | ||
| 757 | versatile_sched_clock_init(sys + VERSATILE_SYS_24MHz_OFFSET, 24000000); | 758 | versatile_sched_clock_init(sys + VERSATILE_SYS_24MHz_OFFSET, 24000000); |
| 759 | |||
| 760 | /* | ||
| 761 | * set clock frequency: | ||
| 762 | * VERSATILE_REFCLK is 32KHz | ||
| 763 | * VERSATILE_TIMCLK is 1MHz | ||
| 764 | */ | ||
| 765 | val = readl(__io_address(VERSATILE_SCTL_BASE)); | ||
| 766 | writel((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) | | ||
| 767 | (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) | | ||
| 768 | (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) | | ||
| 769 | (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel) | val, | ||
| 770 | __io_address(VERSATILE_SCTL_BASE)); | ||
| 758 | } | 771 | } |
| 759 | 772 | ||
| 760 | void __init versatile_init(void) | 773 | void __init versatile_init(void) |
| @@ -785,19 +798,6 @@ void __init versatile_init(void) | |||
| 785 | */ | 798 | */ |
| 786 | void __init versatile_timer_init(void) | 799 | void __init versatile_timer_init(void) |
| 787 | { | 800 | { |
| 788 | u32 val; | ||
| 789 | |||
| 790 | /* | ||
| 791 | * set clock frequency: | ||
| 792 | * VERSATILE_REFCLK is 32KHz | ||
| 793 | * VERSATILE_TIMCLK is 1MHz | ||
| 794 | */ | ||
| 795 | val = readl(__io_address(VERSATILE_SCTL_BASE)); | ||
| 796 | writel((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) | | ||
| 797 | (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) | | ||
| 798 | (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) | | ||
| 799 | (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel) | val, | ||
| 800 | __io_address(VERSATILE_SCTL_BASE)); | ||
| 801 | 801 | ||
| 802 | /* | 802 | /* |
| 803 | * Initialise to a known state (all timers off) | 803 | * Initialise to a known state (all timers off) |
diff --git a/arch/arm/mach-versatile/versatile_dt.c b/arch/arm/mach-versatile/versatile_dt.c index 2558f2e957c3..3621b000a0f6 100644 --- a/arch/arm/mach-versatile/versatile_dt.c +++ b/arch/arm/mach-versatile/versatile_dt.c | |||
| @@ -45,7 +45,6 @@ DT_MACHINE_START(VERSATILE_PB, "ARM-Versatile (Device Tree Support)") | |||
| 45 | .map_io = versatile_map_io, | 45 | .map_io = versatile_map_io, |
| 46 | .init_early = versatile_init_early, | 46 | .init_early = versatile_init_early, |
| 47 | .init_irq = versatile_init_irq, | 47 | .init_irq = versatile_init_irq, |
| 48 | .init_time = versatile_timer_init, | ||
| 49 | .init_machine = versatile_dt_init, | 48 | .init_machine = versatile_dt_init, |
| 50 | .dt_compat = versatile_dt_match, | 49 | .dt_compat = versatile_dt_match, |
| 51 | .restart = versatile_restart, | 50 | .restart = versatile_restart, |
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c index d0ad78998cb6..09e571ddc984 100644 --- a/arch/arm/mach-vexpress/v2m.c +++ b/arch/arm/mach-vexpress/v2m.c | |||
| @@ -1,6 +1,7 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * Versatile Express V2M Motherboard Support | 2 | * Versatile Express V2M Motherboard Support |
| 3 | */ | 3 | */ |
| 4 | #include <linux/clocksource.h> | ||
| 4 | #include <linux/device.h> | 5 | #include <linux/device.h> |
| 5 | #include <linux/amba/bus.h> | 6 | #include <linux/amba/bus.h> |
| 6 | #include <linux/amba/mmci.h> | 7 | #include <linux/amba/mmci.h> |
| @@ -23,7 +24,6 @@ | |||
| 23 | #include <linux/regulator/machine.h> | 24 | #include <linux/regulator/machine.h> |
| 24 | #include <linux/vexpress.h> | 25 | #include <linux/vexpress.h> |
| 25 | 26 | ||
| 26 | #include <asm/arch_timer.h> | ||
| 27 | #include <asm/mach-types.h> | 27 | #include <asm/mach-types.h> |
| 28 | #include <asm/sizes.h> | 28 | #include <asm/sizes.h> |
| 29 | #include <asm/mach/arch.h> | 29 | #include <asm/mach/arch.h> |
| @@ -61,9 +61,6 @@ static void __init v2m_sp804_init(void __iomem *base, unsigned int irq) | |||
| 61 | if (WARN_ON(!base || irq == NO_IRQ)) | 61 | if (WARN_ON(!base || irq == NO_IRQ)) |
| 62 | return; | 62 | return; |
| 63 | 63 | ||
| 64 | writel(0, base + TIMER_1_BASE + TIMER_CTRL); | ||
| 65 | writel(0, base + TIMER_2_BASE + TIMER_CTRL); | ||
| 66 | |||
| 67 | sp804_clocksource_init(base + TIMER_2_BASE, "v2m-timer1"); | 64 | sp804_clocksource_init(base + TIMER_2_BASE, "v2m-timer1"); |
| 68 | sp804_clockevents_init(base + TIMER_1_BASE, irq, "v2m-timer0"); | 65 | sp804_clockevents_init(base + TIMER_1_BASE, irq, "v2m-timer0"); |
| 69 | } | 66 | } |
| @@ -431,25 +428,11 @@ void __init v2m_dt_init_early(void) | |||
| 431 | 428 | ||
| 432 | static void __init v2m_dt_timer_init(void) | 429 | static void __init v2m_dt_timer_init(void) |
| 433 | { | 430 | { |
| 434 | struct device_node *node = NULL; | ||
| 435 | |||
| 436 | vexpress_clk_of_init(); | 431 | vexpress_clk_of_init(); |
| 437 | 432 | ||
| 438 | clocksource_of_init(); | 433 | clocksource_of_init(); |
| 439 | do { | ||
| 440 | node = of_find_compatible_node(node, NULL, "arm,sp804"); | ||
| 441 | } while (node && vexpress_get_site_by_node(node) != VEXPRESS_SITE_MB); | ||
| 442 | if (node) { | ||
| 443 | pr_info("Using SP804 '%s' as a clock & events source\n", | ||
| 444 | node->full_name); | ||
| 445 | v2m_sp804_init(of_iomap(node, 0), | ||
| 446 | irq_of_parse_and_map(node, 0)); | ||
| 447 | } | ||
| 448 | |||
| 449 | arch_timer_of_register(); | ||
| 450 | 434 | ||
| 451 | if (arch_timer_sched_clock_init() != 0) | 435 | versatile_sched_clock_init(vexpress_get_24mhz_clock_base(), |
| 452 | versatile_sched_clock_init(vexpress_get_24mhz_clock_base(), | ||
| 453 | 24000000); | 436 | 24000000); |
| 454 | } | 437 | } |
| 455 | 438 | ||
diff --git a/arch/arm/mach-virt/virt.c b/arch/arm/mach-virt/virt.c index 31666f6b4373..adc0945255ae 100644 --- a/arch/arm/mach-virt/virt.c +++ b/arch/arm/mach-virt/virt.c | |||
| @@ -23,21 +23,13 @@ | |||
| 23 | #include <linux/of_platform.h> | 23 | #include <linux/of_platform.h> |
| 24 | #include <linux/smp.h> | 24 | #include <linux/smp.h> |
| 25 | 25 | ||
| 26 | #include <asm/arch_timer.h> | ||
| 27 | #include <asm/mach/arch.h> | 26 | #include <asm/mach/arch.h> |
| 28 | #include <asm/mach/time.h> | ||
| 29 | 27 | ||
| 30 | static void __init virt_init(void) | 28 | static void __init virt_init(void) |
| 31 | { | 29 | { |
| 32 | of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); | 30 | of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); |
| 33 | } | 31 | } |
| 34 | 32 | ||
| 35 | static void __init virt_timer_init(void) | ||
| 36 | { | ||
| 37 | WARN_ON(arch_timer_of_register() != 0); | ||
| 38 | WARN_ON(arch_timer_sched_clock_init() != 0); | ||
| 39 | } | ||
| 40 | |||
| 41 | static const char *virt_dt_match[] = { | 33 | static const char *virt_dt_match[] = { |
| 42 | "linux,dummy-virt", | 34 | "linux,dummy-virt", |
| 43 | NULL | 35 | NULL |
| @@ -47,7 +39,6 @@ extern struct smp_operations virt_smp_ops; | |||
| 47 | 39 | ||
| 48 | DT_MACHINE_START(VIRT, "Dummy Virtual Machine") | 40 | DT_MACHINE_START(VIRT, "Dummy Virtual Machine") |
| 49 | .init_irq = irqchip_init, | 41 | .init_irq = irqchip_init, |
| 50 | .init_time = virt_timer_init, | ||
| 51 | .init_machine = virt_init, | 42 | .init_machine = virt_init, |
| 52 | .smp = smp_ops(virt_smp_ops), | 43 | .smp = smp_ops(virt_smp_ops), |
| 53 | .dt_compat = virt_dt_match, | 44 | .dt_compat = virt_dt_match, |
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index c2f37390308a..c465faca51b0 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c | |||
| @@ -299,7 +299,7 @@ static void l2x0_unlock(u32 cache_id) | |||
| 299 | int lockregs; | 299 | int lockregs; |
| 300 | int i; | 300 | int i; |
| 301 | 301 | ||
| 302 | switch (cache_id) { | 302 | switch (cache_id & L2X0_CACHE_ID_PART_MASK) { |
| 303 | case L2X0_CACHE_ID_PART_L310: | 303 | case L2X0_CACHE_ID_PART_L310: |
| 304 | lockregs = 8; | 304 | lockregs = 8; |
| 305 | break; | 305 | break; |
| @@ -333,15 +333,14 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask) | |||
| 333 | if (cache_id_part_number_from_dt) | 333 | if (cache_id_part_number_from_dt) |
| 334 | cache_id = cache_id_part_number_from_dt; | 334 | cache_id = cache_id_part_number_from_dt; |
| 335 | else | 335 | else |
| 336 | cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID) | 336 | cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID); |
| 337 | & L2X0_CACHE_ID_PART_MASK; | ||
| 338 | aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL); | 337 | aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL); |
| 339 | 338 | ||
| 340 | aux &= aux_mask; | 339 | aux &= aux_mask; |
| 341 | aux |= aux_val; | 340 | aux |= aux_val; |
| 342 | 341 | ||
| 343 | /* Determine the number of ways */ | 342 | /* Determine the number of ways */ |
| 344 | switch (cache_id) { | 343 | switch (cache_id & L2X0_CACHE_ID_PART_MASK) { |
| 345 | case L2X0_CACHE_ID_PART_L310: | 344 | case L2X0_CACHE_ID_PART_L310: |
| 346 | if (aux & (1 << 16)) | 345 | if (aux & (1 << 16)) |
| 347 | ways = 16; | 346 | ways = 16; |
| @@ -725,7 +724,6 @@ static const struct l2x0_of_data pl310_data = { | |||
| 725 | .flush_all = l2x0_flush_all, | 724 | .flush_all = l2x0_flush_all, |
| 726 | .inv_all = l2x0_inv_all, | 725 | .inv_all = l2x0_inv_all, |
| 727 | .disable = l2x0_disable, | 726 | .disable = l2x0_disable, |
| 728 | .set_debug = pl310_set_debug, | ||
| 729 | }, | 727 | }, |
| 730 | }; | 728 | }; |
| 731 | 729 | ||
| @@ -814,9 +812,8 @@ int __init l2x0_of_init(u32 aux_val, u32 aux_mask) | |||
| 814 | data->save(); | 812 | data->save(); |
| 815 | 813 | ||
| 816 | of_init = true; | 814 | of_init = true; |
| 817 | l2x0_init(l2x0_base, aux_val, aux_mask); | ||
| 818 | |||
| 819 | memcpy(&outer_cache, &data->outer_cache, sizeof(outer_cache)); | 815 | memcpy(&outer_cache, &data->outer_cache, sizeof(outer_cache)); |
| 816 | l2x0_init(l2x0_base, aux_val, aux_mask); | ||
| 820 | 817 | ||
| 821 | return 0; | 818 | return 0; |
| 822 | } | 819 | } |
diff --git a/arch/arm/mm/context.c b/arch/arm/mm/context.c index a5a4b2bc42ba..2ac37372ef52 100644 --- a/arch/arm/mm/context.c +++ b/arch/arm/mm/context.c | |||
| @@ -48,7 +48,7 @@ static DEFINE_RAW_SPINLOCK(cpu_asid_lock); | |||
| 48 | static atomic64_t asid_generation = ATOMIC64_INIT(ASID_FIRST_VERSION); | 48 | static atomic64_t asid_generation = ATOMIC64_INIT(ASID_FIRST_VERSION); |
| 49 | static DECLARE_BITMAP(asid_map, NUM_USER_ASIDS); | 49 | static DECLARE_BITMAP(asid_map, NUM_USER_ASIDS); |
| 50 | 50 | ||
| 51 | static DEFINE_PER_CPU(atomic64_t, active_asids); | 51 | DEFINE_PER_CPU(atomic64_t, active_asids); |
| 52 | static DEFINE_PER_CPU(u64, reserved_asids); | 52 | static DEFINE_PER_CPU(u64, reserved_asids); |
| 53 | static cpumask_t tlb_flush_pending; | 53 | static cpumask_t tlb_flush_pending; |
| 54 | 54 | ||
| @@ -215,6 +215,7 @@ void check_and_switch_context(struct mm_struct *mm, struct task_struct *tsk) | |||
| 215 | if (cpumask_test_and_clear_cpu(cpu, &tlb_flush_pending)) { | 215 | if (cpumask_test_and_clear_cpu(cpu, &tlb_flush_pending)) { |
| 216 | local_flush_bp_all(); | 216 | local_flush_bp_all(); |
| 217 | local_flush_tlb_all(); | 217 | local_flush_tlb_all(); |
| 218 | dummy_flush_tlb_a15_erratum(); | ||
| 218 | } | 219 | } |
| 219 | 220 | ||
| 220 | atomic64_set(&per_cpu(active_asids, cpu), asid); | 221 | atomic64_set(&per_cpu(active_asids, cpu), asid); |
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c index e95a996ab78f..78978945492a 100644 --- a/arch/arm/mm/mmu.c +++ b/arch/arm/mm/mmu.c | |||
| @@ -598,39 +598,60 @@ static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr, | |||
| 598 | } while (pte++, addr += PAGE_SIZE, addr != end); | 598 | } while (pte++, addr += PAGE_SIZE, addr != end); |
| 599 | } | 599 | } |
| 600 | 600 | ||
| 601 | static void __init alloc_init_section(pud_t *pud, unsigned long addr, | 601 | static void __init map_init_section(pmd_t *pmd, unsigned long addr, |
| 602 | unsigned long end, phys_addr_t phys, | 602 | unsigned long end, phys_addr_t phys, |
| 603 | const struct mem_type *type) | 603 | const struct mem_type *type) |
| 604 | { | 604 | { |
| 605 | pmd_t *pmd = pmd_offset(pud, addr); | 605 | #ifndef CONFIG_ARM_LPAE |
| 606 | |||
| 607 | /* | 606 | /* |
| 608 | * Try a section mapping - end, addr and phys must all be aligned | 607 | * In classic MMU format, puds and pmds are folded in to |
| 609 | * to a section boundary. Note that PMDs refer to the individual | 608 | * the pgds. pmd_offset gives the PGD entry. PGDs refer to a |
| 610 | * L1 entries, whereas PGDs refer to a group of L1 entries making | 609 | * group of L1 entries making up one logical pointer to |
| 611 | * up one logical pointer to an L2 table. | 610 | * an L2 table (2MB), where as PMDs refer to the individual |
| 611 | * L1 entries (1MB). Hence increment to get the correct | ||
| 612 | * offset for odd 1MB sections. | ||
| 613 | * (See arch/arm/include/asm/pgtable-2level.h) | ||
| 612 | */ | 614 | */ |
| 613 | if (type->prot_sect && ((addr | end | phys) & ~SECTION_MASK) == 0) { | 615 | if (addr & SECTION_SIZE) |
| 614 | pmd_t *p = pmd; | 616 | pmd++; |
| 615 | |||
| 616 | #ifndef CONFIG_ARM_LPAE | ||
| 617 | if (addr & SECTION_SIZE) | ||
| 618 | pmd++; | ||
| 619 | #endif | 617 | #endif |
| 618 | do { | ||
| 619 | *pmd = __pmd(phys | type->prot_sect); | ||
| 620 | phys += SECTION_SIZE; | ||
| 621 | } while (pmd++, addr += SECTION_SIZE, addr != end); | ||
| 620 | 622 | ||
| 621 | do { | 623 | flush_pmd_entry(pmd); |
| 622 | *pmd = __pmd(phys | type->prot_sect); | 624 | } |
| 623 | phys += SECTION_SIZE; | ||
| 624 | } while (pmd++, addr += SECTION_SIZE, addr != end); | ||
| 625 | 625 | ||
| 626 | flush_pmd_entry(p); | 626 | static void __init alloc_init_pmd(pud_t *pud, unsigned long addr, |
| 627 | } else { | 627 | unsigned long end, phys_addr_t phys, |
| 628 | const struct mem_type *type) | ||
| 629 | { | ||
| 630 | pmd_t *pmd = pmd_offset(pud, addr); | ||
| 631 | unsigned long next; | ||
| 632 | |||
| 633 | do { | ||
| 628 | /* | 634 | /* |
| 629 | * No need to loop; pte's aren't interested in the | 635 | * With LPAE, we must loop over to map |
| 630 | * individual L1 entries. | 636 | * all the pmds for the given range. |
| 631 | */ | 637 | */ |
| 632 | alloc_init_pte(pmd, addr, end, __phys_to_pfn(phys), type); | 638 | next = pmd_addr_end(addr, end); |
| 633 | } | 639 | |
| 640 | /* | ||
| 641 | * Try a section mapping - addr, next and phys must all be | ||
| 642 | * aligned to a section boundary. | ||
| 643 | */ | ||
| 644 | if (type->prot_sect && | ||
| 645 | ((addr | next | phys) & ~SECTION_MASK) == 0) { | ||
| 646 | map_init_section(pmd, addr, next, phys, type); | ||
| 647 | } else { | ||
| 648 | alloc_init_pte(pmd, addr, next, | ||
| 649 | __phys_to_pfn(phys), type); | ||
| 650 | } | ||
| 651 | |||
| 652 | phys += next - addr; | ||
| 653 | |||
| 654 | } while (pmd++, addr = next, addr != end); | ||
| 634 | } | 655 | } |
| 635 | 656 | ||
| 636 | static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr, | 657 | static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr, |
| @@ -641,7 +662,7 @@ static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr, | |||
| 641 | 662 | ||
| 642 | do { | 663 | do { |
| 643 | next = pud_addr_end(addr, end); | 664 | next = pud_addr_end(addr, end); |
| 644 | alloc_init_section(pud, addr, next, phys, type); | 665 | alloc_init_pmd(pud, addr, next, phys, type); |
| 645 | phys += next - addr; | 666 | phys += next - addr; |
| 646 | } while (pud++, addr = next, addr != end); | 667 | } while (pud++, addr = next, addr != end); |
| 647 | } | 668 | } |
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 3a3c015f8d5c..f584d3f5b37c 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S | |||
| @@ -420,7 +420,7 @@ __v7_pj4b_proc_info: | |||
| 420 | __v7_ca7mp_proc_info: | 420 | __v7_ca7mp_proc_info: |
| 421 | .long 0x410fc070 | 421 | .long 0x410fc070 |
| 422 | .long 0xff0ffff0 | 422 | .long 0xff0ffff0 |
| 423 | __v7_proc __v7_ca7mp_setup, hwcaps = HWCAP_IDIV | 423 | __v7_proc __v7_ca7mp_setup |
| 424 | .size __v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info | 424 | .size __v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info |
| 425 | 425 | ||
| 426 | /* | 426 | /* |
| @@ -430,10 +430,25 @@ __v7_ca7mp_proc_info: | |||
| 430 | __v7_ca15mp_proc_info: | 430 | __v7_ca15mp_proc_info: |
| 431 | .long 0x410fc0f0 | 431 | .long 0x410fc0f0 |
| 432 | .long 0xff0ffff0 | 432 | .long 0xff0ffff0 |
| 433 | __v7_proc __v7_ca15mp_setup, hwcaps = HWCAP_IDIV | 433 | __v7_proc __v7_ca15mp_setup |
| 434 | .size __v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info | 434 | .size __v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info |
| 435 | 435 | ||
| 436 | /* | 436 | /* |
| 437 | * Qualcomm Inc. Krait processors. | ||
| 438 | */ | ||
| 439 | .type __krait_proc_info, #object | ||
| 440 | __krait_proc_info: | ||
| 441 | .long 0x510f0400 @ Required ID value | ||
| 442 | .long 0xff0ffc00 @ Mask for ID | ||
| 443 | /* | ||
| 444 | * Some Krait processors don't indicate support for SDIV and UDIV | ||
| 445 | * instructions in the ARM instruction set, even though they actually | ||
| 446 | * do support them. | ||
| 447 | */ | ||
| 448 | __v7_proc __v7_setup, hwcaps = HWCAP_IDIV | ||
| 449 | .size __krait_proc_info, . - __krait_proc_info | ||
| 450 | |||
| 451 | /* | ||
| 437 | * Match any ARMv7 processor core. | 452 | * Match any ARMv7 processor core. |
| 438 | */ | 453 | */ |
| 439 | .type __v7_proc_info, #object | 454 | .type __v7_proc_info, #object |
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h index 0f6c47a6475b..989fefe18be6 100644 --- a/arch/arm/plat-samsung/include/plat/cpu.h +++ b/arch/arm/plat-samsung/include/plat/cpu.h | |||
| @@ -183,7 +183,6 @@ extern void s3c_init_cpu(unsigned long idcode, | |||
| 183 | 183 | ||
| 184 | /* core initialisation functions */ | 184 | /* core initialisation functions */ |
| 185 | 185 | ||
| 186 | extern void s3c24xx_init_irq(void); | ||
| 187 | extern void s5p_init_irq(u32 *vic, u32 num_vic); | 186 | extern void s5p_init_irq(u32 *vic, u32 num_vic); |
| 188 | 187 | ||
| 189 | extern void s3c24xx_init_io(struct map_desc *mach_desc, int size); | 188 | extern void s3c24xx_init_io(struct map_desc *mach_desc, int size); |
diff --git a/arch/arm/plat-spear/Kconfig b/arch/arm/plat-spear/Kconfig deleted file mode 100644 index 8a08c31b5e20..000000000000 --- a/arch/arm/plat-spear/Kconfig +++ /dev/null | |||
| @@ -1,47 +0,0 @@ | |||
| 1 | # | ||
| 2 | # SPEAr Platform configuration file | ||
| 3 | # | ||
| 4 | |||
| 5 | if PLAT_SPEAR | ||
| 6 | |||
| 7 | choice | ||
| 8 | prompt "ST SPEAr Family" | ||
| 9 | default ARCH_SPEAR3XX | ||
| 10 | |||
| 11 | config ARCH_SPEAR13XX | ||
| 12 | bool "ST SPEAr13xx with Device Tree" | ||
| 13 | select ARCH_HAS_CPUFREQ | ||
| 14 | select ARM_GIC | ||
| 15 | select CPU_V7 | ||
| 16 | select GPIO_SPEAR_SPICS | ||
| 17 | select HAVE_SMP | ||
| 18 | select MIGHT_HAVE_CACHE_L2X0 | ||
| 19 | select PINCTRL | ||
| 20 | select USE_OF | ||
| 21 | help | ||
| 22 | Supports for ARM's SPEAR13XX family | ||
| 23 | |||
| 24 | config ARCH_SPEAR3XX | ||
| 25 | bool "ST SPEAr3xx with Device Tree" | ||
| 26 | select ARM_VIC | ||
| 27 | select CPU_ARM926T | ||
| 28 | select PINCTRL | ||
| 29 | select USE_OF | ||
| 30 | help | ||
| 31 | Supports for ARM's SPEAR3XX family | ||
| 32 | |||
| 33 | config ARCH_SPEAR6XX | ||
| 34 | bool "SPEAr6XX" | ||
| 35 | select ARM_VIC | ||
| 36 | select CPU_ARM926T | ||
| 37 | help | ||
| 38 | Supports for ARM's SPEAR6XX family | ||
| 39 | |||
| 40 | endchoice | ||
| 41 | |||
| 42 | # Adding SPEAr machine specific configuration files | ||
| 43 | source "arch/arm/mach-spear13xx/Kconfig" | ||
| 44 | source "arch/arm/mach-spear3xx/Kconfig" | ||
| 45 | source "arch/arm/mach-spear6xx/Kconfig" | ||
| 46 | |||
| 47 | endif | ||
diff --git a/arch/arm/plat-spear/Makefile b/arch/arm/plat-spear/Makefile deleted file mode 100644 index 01e88532a5db..000000000000 --- a/arch/arm/plat-spear/Makefile +++ /dev/null | |||
| @@ -1,9 +0,0 @@ | |||
| 1 | # | ||
| 2 | # SPEAr Platform specific Makefile | ||
| 3 | # | ||
| 4 | |||
| 5 | # Common support | ||
| 6 | obj-y := restart.o time.o | ||
| 7 | |||
| 8 | obj-$(CONFIG_ARCH_SPEAR3XX) += pl080.o | ||
| 9 | obj-$(CONFIG_ARCH_SPEAR6XX) += pl080.o | ||