381 files changed, 5264 insertions, 4297 deletions
diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/omap2.dtsi
new file mode 100644
index 000000000000..f2ab4ea7cc0e
--- /dev/null
+++ b/arch/arm/boot/dts/omap2.dtsi
@@ -0,0 +1,67 @@
+/*
+ * Device Tree Source for OMAP2 SoC
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+/include/ "skeleton.dtsi"
+/ {
+        compatible = "ti,omap2430", "ti,omap2420", "ti,omap2";
+        aliases {
+                serial0 = &uart1;
+                serial1 = &uart2;
+                serial2 = &uart3;
+        };
+        cpus {
+                cpu@0 {
+                        compatible = "arm,arm1136jf-s";
+                };
+        };
+        soc {
+                compatible = "ti,omap-infra";
+                mpu {
+                        compatible = "ti,omap2-mpu";
+                        ti,hwmods = "mpu";
+                };
+        };
+        ocp {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                ti,hwmods = "l3_main";
+                intc: interrupt-controller@1 {
+                        compatible = "ti,omap2-intc";
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                };
+                uart1: serial@4806a000 {
+                        compatible = "ti,omap2-uart";
+                        ti,hwmods = "uart1";
+                        clock-frequency = <48000000>;
+                };
+                uart2: serial@4806c000 {
+                        compatible = "ti,omap2-uart";
+                        ti,hwmods = "uart2";
+                        clock-frequency = <48000000>;
+                };
+                uart3: serial@4806e000 {
+                        compatible = "ti,omap2-uart";
+                        ti,hwmods = "uart3";
+                        clock-frequency = <48000000>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index d202bb5ec7ef..216c3317461d 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -13,6 +13,13 @@
 / {
        compatible = "ti,omap3430", "ti,omap3";
+        aliases {
+                serial0 = &uart1;
+                serial1 = &uart2;
+                serial2 = &uart3;
+                serial3 = &uart4;
+        };
        cpus {
                cpu@0 {
                        compatible = "arm,cortex-a8";
@@ -59,5 +66,29 @@
                        interrupt-controller;
                        #interrupt-cells = <1>;
                };
+                uart1: serial@0x4806a000 {
+                        compatible = "ti,omap3-uart";
+                        ti,hwmods = "uart1";
+                        clock-frequency = <48000000>;
+                };
+                uart2: serial@0x4806c000 {
+                        compatible = "ti,omap3-uart";
+                        ti,hwmods = "uart2";
+                        clock-frequency = <48000000>;
+                };
+                uart3: serial@0x49020000 {
+                        compatible = "ti,omap3-uart";
+                        ti,hwmods = "uart3";
+                        clock-frequency = <48000000>;
+                };
+                uart4: serial@0x49042000 {
+                        compatible = "ti,omap3-uart";
+                        ti,hwmods = "uart4";
+                        clock-frequency = <48000000>;
+                };
        };
 };
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 4c61c829043a..e8fe75fac7c5 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -21,6 +21,10 @@
        interrupt-parent = <&gic>;
        aliases {
+                serial0 = &uart1;
+                serial1 = &uart2;
+                serial2 = &uart3;
+                serial3 = &uart4;
        };
        cpus {
@@ -99,5 +103,29 @@
                        reg = <0x48241000 0x1000>,
                              <0x48240100 0x0100>;
                };
+                uart1: serial@0x4806a000 {
+                        compatible = "ti,omap4-uart";
+                        ti,hwmods = "uart1";
+                        clock-frequency = <48000000>;
+                };
+                uart2: serial@0x4806c000 {
+                        compatible = "ti,omap4-uart";
+                        ti,hwmods = "uart2";
+                        clock-frequency = <48000000>;
+                };
+                uart3: serial@0x48020000 {
+                        compatible = "ti,omap4-uart";
+                        ti,hwmods = "uart3";
+                        clock-frequency = <48000000>;
+                };
+                uart4: serial@0x4806e000 {
+                        compatible = "ti,omap4-uart";
+                        ti,hwmods = "uart4";
+                        clock-frequency = <48000000>;
+                };
        };
 };
diff --git a/arch/arm/common/Kconfig b/arch/arm/common/Kconfig
index 74df9ca2be31..81a933eb0903 100644
--- a/arch/arm/common/Kconfig
+++ b/arch/arm/common/Kconfig
@@ -1,8 +1,14 @@
 config ARM_GIC
        select IRQ_DOMAIN
+        select MULTI_IRQ_HANDLER
+        bool
+config GIC_NON_BANKED
        bool
 config ARM_VIC
+        select IRQ_DOMAIN
+        select MULTI_IRQ_HANDLER
        bool
 config ARM_VIC_NR
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index 410a546060a2..b2dc2dd7f1df 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -40,13 +40,36 @@
 #include <linux/slab.h>
 #include <asm/irq.h>
+#include <asm/exception.h>
 #include <asm/mach/irq.h>
 #include <asm/hardware/gic.h>
-static DEFINE_RAW_SPINLOCK(irq_controller_lock);
+union gic_base {
+        void __iomem *common_base;
+        void __percpu __iomem **percpu_base;
+};
-/* Address of GIC 0 CPU interface */
+struct gic_chip_data {
-void __iomem *gic_cpu_base_addr __read_mostly;
+        unsigned int irq_offset;
+        union gic_base dist_base;
+        union gic_base cpu_base;
+#ifdef CONFIG_CPU_PM
+        u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)];
+        u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)];
+        u32 saved_spi_target[DIV_ROUND_UP(1020, 4)];
+        u32 __percpu *saved_ppi_enable;
+        u32 __percpu *saved_ppi_conf;
+#endif
+#ifdef CONFIG_IRQ_DOMAIN
+        struct irq_domain domain;
+#endif
+        unsigned int gic_irqs;
+#ifdef CONFIG_GIC_NON_BANKED
+        void __iomem *(*get_base)(union gic_base *);
+#endif
+};
+static DEFINE_RAW_SPINLOCK(irq_controller_lock);
 /*
 * Supported arch specific GIC irq extension.
@@ -67,16 +90,48 @@ struct irq_chip gic_arch_extn = {
 static struct gic_chip_data gic_data[MAX_GIC_NR] __read_mostly;
+#ifdef CONFIG_GIC_NON_BANKED
+static void __iomem *gic_get_percpu_base(union gic_base *base)
+{
+        return *__this_cpu_ptr(base->percpu_base);
+}
+static void __iomem *gic_get_common_base(union gic_base *base)
+{
+        return base->common_base;
+}
+static inline void __iomem *gic_data_dist_base(struct gic_chip_data *data)
+{
+        return data->get_base(&data->dist_base);
+}
+static inline void __iomem *gic_data_cpu_base(struct gic_chip_data *data)
+{
+        return data->get_base(&data->cpu_base);
+}
+static inline void gic_set_base_accessor(struct gic_chip_data *data,
+                                         void __iomem *(*f)(union gic_base *))
+{
+        data->get_base = f;
+}
+#else
+#define gic_data_dist_base(d)   ((d)->dist_base.common_base)
+#define gic_data_cpu_base(d)    ((d)->cpu_base.common_base)
+#define gic_set_base_accessor(d,f)
+#endif
 static inline void __iomem *gic_dist_base(struct irq_data *d)
 {
        struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
-        return gic_data->dist_base;
+        return gic_data_dist_base(gic_data);
 }
 static inline void __iomem *gic_cpu_base(struct irq_data *d)
 {
        struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
-        return gic_data->cpu_base;
+        return gic_data_cpu_base(gic_data);
 }
 static inline unsigned int gic_irq(struct irq_data *d)
@@ -215,6 +270,32 @@ static int gic_set_wake(struct irq_data *d, unsigned int on)
 #define gic_set_wake    NULL
 #endif
+asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
+{
+        u32 irqstat, irqnr;
+        struct gic_chip_data *gic = &gic_data[0];
+        void __iomem *cpu_base = gic_data_cpu_base(gic);
+        do {
+                irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK);
+                irqnr = irqstat & ~0x1c00;
+                if (likely(irqnr > 15 && irqnr < 1021)) {
+                        irqnr = irq_domain_to_irq(&gic->domain, irqnr);
+                        handle_IRQ(irqnr, regs);
+                        continue;
+                }
+                if (irqnr < 16) {
+                        writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
+#ifdef CONFIG_SMP
+                        handle_IPI(irqnr, regs);
+#endif
+                        continue;
+                }
+                break;
+        } while (1);
+}
 static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
 {
        struct gic_chip_data *chip_data = irq_get_handler_data(irq);
@@ -225,7 +306,7 @@ static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
        chained_irq_enter(chip, desc);
        raw_spin_lock(&irq_controller_lock);
-        status = readl_relaxed(chip_data->cpu_base + GIC_CPU_INTACK);
+        status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK);
        raw_spin_unlock(&irq_controller_lock);
        gic_irq = (status & 0x3ff);
@@ -270,7 +351,7 @@ static void __init gic_dist_init(struct gic_chip_data *gic)
        u32 cpumask;
        unsigned int gic_irqs = gic->gic_irqs;
        struct irq_domain *domain = &gic->domain;
-        void __iomem *base = gic->dist_base;
+        void __iomem *base = gic_data_dist_base(gic);
        u32 cpu = 0;
 #ifdef CONFIG_SMP
@@ -330,8 +411,8 @@ static void __init gic_dist_init(struct gic_chip_data *gic)
 static void __cpuinit gic_cpu_init(struct gic_chip_data *gic)
 {
-        void __iomem *dist_base = gic->dist_base;
+        void __iomem *dist_base = gic_data_dist_base(gic);
-        void __iomem *base = gic->cpu_base;
+        void __iomem *base = gic_data_cpu_base(gic);
        int i;
        /*
@@ -368,7 +449,7 @@ static void gic_dist_save(unsigned int gic_nr)
                BUG();
        gic_irqs = gic_data[gic_nr].gic_irqs;
-        dist_base = gic_data[gic_nr].dist_base;
+        dist_base = gic_data_dist_base(&gic_data[gic_nr]);
        if (!dist_base)
                return;
@@ -403,7 +484,7 @@ static void gic_dist_restore(unsigned int gic_nr)
                BUG();
        gic_irqs = gic_data[gic_nr].gic_irqs;
-        dist_base = gic_data[gic_nr].dist_base;
+        dist_base = gic_data_dist_base(&gic_data[gic_nr]);
        if (!dist_base)
                return;
@@ -439,8 +520,8 @@ static void gic_cpu_save(unsigned int gic_nr)
        if (gic_nr >= MAX_GIC_NR)
                BUG();
-        dist_base = gic_data[gic_nr].dist_base;
+        dist_base = gic_data_dist_base(&gic_data[gic_nr]);
-        cpu_base = gic_data[gic_nr].cpu_base;
+        cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
        if (!dist_base || !cpu_base)
                return;
@@ -465,8 +546,8 @@ static void gic_cpu_restore(unsigned int gic_nr)
        if (gic_nr >= MAX_GIC_NR)
                BUG();
-        dist_base = gic_data[gic_nr].dist_base;
+        dist_base = gic_data_dist_base(&gic_data[gic_nr]);
-        cpu_base = gic_data[gic_nr].cpu_base;
+        cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
        if (!dist_base || !cpu_base)
                return;
@@ -491,6 +572,11 @@ static int gic_notifier(struct notifier_block *self, unsigned long cmd,	void *v)
        int i;
        for (i = 0; i < MAX_GIC_NR; i++) {
+#ifdef CONFIG_GIC_NON_BANKED
+                /* Skip over unused GICs */
+                if (!gic_data[i].get_base)
+                        continue;
+#endif
                switch (cmd) {
                case CPU_PM_ENTER:
                        gic_cpu_save(i);
@@ -564,8 +650,9 @@ const struct irq_domain_ops gic_irq_domain_ops = {
 #endif
 };
-void __init gic_init(unsigned int gic_nr, int irq_start,
+void __init gic_init_bases(unsigned int gic_nr, int irq_start,
-        void __iomem *dist_base, void __iomem *cpu_base)
+                           void __iomem *dist_base, void __iomem *cpu_base,
+                           u32 percpu_offset)
 {
        struct gic_chip_data *gic;
        struct irq_domain *domain;
@@ -575,8 +662,36 @@ void __init gic_init(unsigned int gic_nr, int irq_start,
        gic = &gic_data[gic_nr];
        domain = &gic->domain;
-        gic->dist_base = dist_base;
+#ifdef CONFIG_GIC_NON_BANKED
-        gic->cpu_base = cpu_base;
+        if (percpu_offset) { /* Frankein-GIC without banked registers... */
+                unsigned int cpu;
+                gic->dist_base.percpu_base = alloc_percpu(void __iomem *);
+                gic->cpu_base.percpu_base = alloc_percpu(void __iomem *);
+                if (WARN_ON(!gic->dist_base.percpu_base ||
+                            !gic->cpu_base.percpu_base)) {
+                        free_percpu(gic->dist_base.percpu_base);
+                        free_percpu(gic->cpu_base.percpu_base);
+                        return;
+                }
+                for_each_possible_cpu(cpu) {
+                        unsigned long offset = percpu_offset * cpu_logical_map(cpu);
+                        *per_cpu_ptr(gic->dist_base.percpu_base, cpu) = dist_base + offset;
+                        *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) = cpu_base + offset;
+                }
+                gic_set_base_accessor(gic, gic_get_percpu_base);
+        } else
+#endif
+        {                       /* Normal, sane GIC... */
+                WARN(percpu_offset,
+                     "GIC_NON_BANKED not enabled, ignoring %08x offset!",
+                     percpu_offset);
+                gic->dist_base.common_base = dist_base;
+                gic->cpu_base.common_base = cpu_base;
+                gic_set_base_accessor(gic, gic_get_common_base);
+        }
        /*
         * For primary GICs, skip over SGIs.
@@ -584,8 +699,6 @@ void __init gic_init(unsigned int gic_nr, int irq_start,
         */
        domain->hwirq_base = 32;
        if (gic_nr == 0) {
-                gic_cpu_base_addr = cpu_base;
                if ((irq_start & 31) > 0) {
                        domain->hwirq_base = 16;
                        if (irq_start != -1)
@@ -597,7 +710,7 @@ void __init gic_init(unsigned int gic_nr, int irq_start,
         * Find out how many interrupts are supported.
         * The GIC only supports up to 1020 interrupt sources.
         */
-        gic_irqs = readl_relaxed(dist_base + GIC_DIST_CTR) & 0x1f;
+        gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f;
        gic_irqs = (gic_irqs + 1) * 32;
        if (gic_irqs > 1020)
                gic_irqs = 1020;
@@ -645,7 +758,7 @@ void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
        dsb();
        /* this always happens on GIC0 */
-        writel_relaxed(map << 16 | irq, gic_data[0].dist_base + GIC_DIST_SOFTINT);
+        writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
 }
 #endif
@@ -656,6 +769,7 @@ int __init gic_of_init(struct device_node *node, struct device_node *parent)
 {
        void __iomem *cpu_base;
        void __iomem *dist_base;
+        u32 percpu_offset;
        int irq;
        struct irq_domain *domain = &gic_data[gic_cnt].domain;
@@ -668,9 +782,12 @@ int __init gic_of_init(struct device_node *node, struct device_node *parent)
        cpu_base = of_iomap(node, 1);
        WARN(!cpu_base, "unable to map gic cpu registers\n");
+        if (of_property_read_u32(node, "cpu-offset", &percpu_offset))
+                percpu_offset = 0;
        domain->of_node = of_node_get(node);
-        gic_init(gic_cnt, -1, dist_base, cpu_base);
+        gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset);
        if (parent) {
                irq = irq_of_parse_and_map(node, 0);
diff --git a/arch/arm/common/vic.c b/arch/arm/common/vic.c
index 01f18a421b17..6ed41ec2bbf5 100644
--- a/arch/arm/common/vic.c
+++ b/arch/arm/common/vic.c
@@ -19,17 +19,22 @@
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
+#include <linux/export.h>
 #include <linux/init.h>
 #include <linux/list.h>
 #include <linux/io.h>
+#include <linux/irqdomain.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
 #include <linux/syscore_ops.h>
 #include <linux/device.h>
 #include <linux/amba/bus.h>
+#include <asm/exception.h>
 #include <asm/mach/irq.h>
 #include <asm/hardware/vic.h>
-#ifdef CONFIG_PM
 /**
 * struct vic_device - VIC PM device
 * @irq: The IRQ number for the base of the VIC.
@@ -40,6 +45,7 @@
 * @int_enable: Save for VIC_INT_ENABLE.
 * @soft_int: Save for VIC_INT_SOFT.
 * @protect: Save for VIC_PROTECT.
+ * @domain: The IRQ domain for the VIC.
 */
 struct vic_device {
        void __iomem    *base;
@@ -50,13 +56,13 @@ struct vic_device {
        u32             int_enable;
        u32             soft_int;
        u32             protect;
+        struct irq_domain domain;
 };
 /* we cannot allocate memory when VICs are initially registered */
 static struct vic_device vic_devices[CONFIG_ARM_VIC_NR];
 static int vic_id;
-#endif /* CONFIG_PM */
 /**
 * vic_init2 - common initialisation code
@@ -156,39 +162,50 @@ static int __init vic_pm_init(void)
        return 0;
 }
 late_initcall(vic_pm_init);
+#endif /* CONFIG_PM */
 /**
- * vic_pm_register - Register a VIC for later power management control
+ * vic_register() - Register a VIC.
 * @base: The base address of the VIC.
 * @irq: The base IRQ for the VIC.
 * @resume_sources: bitmask of interrupts allowed for resume sources.
+ * @node: The device tree node associated with the VIC.
 *
 * Register the VIC with the system device tree so that it can be notified
 * of suspend and resume requests and ensure that the correct actions are
 * taken to re-instate the settings on resume.
+ *
+ * This also configures the IRQ domain for the VIC.
 */
-static void __init vic_pm_register(void __iomem *base, unsigned int irq, u32 resume_sources)
+static void __init vic_register(void __iomem *base, unsigned int irq,
+                                u32 resume_sources, struct device_node *node)
 {
        struct vic_device *v;
-        if (vic_id >= ARRAY_SIZE(vic_devices))
+        if (vic_id >= ARRAY_SIZE(vic_devices)) {
                printk(KERN_ERR "%s: too few VICs, increase CONFIG_ARM_VIC_NR\n", __func__);
-        else {
+                return;
-                v = &vic_devices[vic_id];
-                v->base = base;
-                v->resume_sources = resume_sources;
-                v->irq = irq;
-                vic_id++;
        }
+        v = &vic_devices[vic_id];
+        v->base = base;
+        v->resume_sources = resume_sources;
+        v->irq = irq;
+        vic_id++;
+        v->domain.irq_base = irq;
+        v->domain.nr_irq = 32;
+#ifdef CONFIG_OF_IRQ
+        v->domain.of_node = of_node_get(node);
+        v->domain.ops = &irq_domain_simple_ops;
+#endif /* CONFIG_OF */
+        irq_domain_add(&v->domain);
 }
-#else
-static inline void vic_pm_register(void __iomem *base, unsigned int irq, u32 arg1) { }
-#endif /* CONFIG_PM */
 static void vic_ack_irq(struct irq_data *d)
 {
        void __iomem *base = irq_data_get_irq_chip_data(d);
-        unsigned int irq = d->irq & 31;
+        unsigned int irq = d->hwirq;
        writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
        /* moreover, clear the soft-triggered, in case it was the reason */
        writel(1 << irq, base + VIC_INT_SOFT_CLEAR);
@@ -197,14 +214,14 @@ static void vic_ack_irq(struct irq_data *d)
 static void vic_mask_irq(struct irq_data *d)
 {
        void __iomem *base = irq_data_get_irq_chip_data(d);
-        unsigned int irq = d->irq & 31;
+        unsigned int irq = d->hwirq;
        writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
 }
 static void vic_unmask_irq(struct irq_data *d)
 {
        void __iomem *base = irq_data_get_irq_chip_data(d);
-        unsigned int irq = d->irq & 31;
+        unsigned int irq = d->hwirq;
        writel(1 << irq, base + VIC_INT_ENABLE);
 }
@@ -226,7 +243,7 @@ static struct vic_device *vic_from_irq(unsigned int irq)
 static int vic_set_wake(struct irq_data *d, unsigned int on)
 {
        struct vic_device *v = vic_from_irq(d->irq);
-        unsigned int off = d->irq & 31;
+        unsigned int off = d->hwirq;
        u32 bit = 1 << off;
        if (!v)
@@ -330,15 +347,9 @@ static void __init vic_init_st(void __iomem *base, unsigned int irq_start,
        vic_set_irq_sources(base, irq_start, vic_sources);
 }
-/**
+static void __init __vic_init(void __iomem *base, unsigned int irq_start,
- * vic_init - initialise a vectored interrupt controller
+                              u32 vic_sources, u32 resume_sources,
- * @base: iomem base address
+                              struct device_node *node)
- * @irq_start: starting interrupt number, must be muliple of 32
- * @vic_sources: bitmask of interrupt sources to allow
- * @resume_sources: bitmask of interrupt sources to allow for resume
- */
-void __init vic_init(void __iomem *base, unsigned int irq_start,
-                     u32 vic_sources, u32 resume_sources)
 {
        unsigned int i;
        u32 cellid = 0;
@@ -375,5 +386,81 @@ void __init vic_init(void __iomem *base, unsigned int irq_start,
        vic_set_irq_sources(base, irq_start, vic_sources);
-        vic_pm_register(base, irq_start, resume_sources);
+        vic_register(base, irq_start, resume_sources, node);
+}
+/**
+ * vic_init() - initialise a vectored interrupt controller
+ * @base: iomem base address
+ * @irq_start: starting interrupt number, must be muliple of 32
+ * @vic_sources: bitmask of interrupt sources to allow
+ * @resume_sources: bitmask of interrupt sources to allow for resume
+ */
+void __init vic_init(void __iomem *base, unsigned int irq_start,
+                     u32 vic_sources, u32 resume_sources)
+{
+        __vic_init(base, irq_start, vic_sources, resume_sources, NULL);
+}
+#ifdef CONFIG_OF
+int __init vic_of_init(struct device_node *node, struct device_node *parent)
+{
+        void __iomem *regs;
+        int irq_base;
+        if (WARN(parent, "non-root VICs are not supported"))
+                return -EINVAL;
+        regs = of_iomap(node, 0);
+        if (WARN_ON(!regs))
+                return -EIO;
+        irq_base = irq_alloc_descs(-1, 0, 32, numa_node_id());
+        if (WARN_ON(irq_base < 0))
+                goto out_unmap;
+        __vic_init(regs, irq_base, ~0, ~0, node);
+        return 0;
+ out_unmap:
+        iounmap(regs);
+        return -EIO;
+}
+#endif /* CONFIG OF */
+/*
+ * Handle each interrupt in a single VIC.  Returns non-zero if we've
+ * handled at least one interrupt.  This does a single read of the
+ * status register and handles all interrupts in order from LSB first.
+ */
+static int handle_one_vic(struct vic_device *vic, struct pt_regs *regs)
+{
+        u32 stat, irq;
+        int handled = 0;
+        stat = readl_relaxed(vic->base + VIC_IRQ_STATUS);
+        while (stat) {
+                irq = ffs(stat) - 1;
+                handle_IRQ(irq_domain_to_irq(&vic->domain, irq), regs);
+                stat &= ~(1 << irq);
+                handled = 1;
+        }
+        return handled;
+}
+/*
+ * Keep iterating over all registered VIC's until there are no pending
+ * interrupts.
+ */
+asmlinkage void __exception_irq_entry vic_handle_irq(struct pt_regs *regs)
+{
+        int i, handled;
+        do {
+                for (i = 0, handled = 0; i < vic_id; ++i)
+                        handled |= handle_one_vic(&vic_devices[i], regs);
+        } while (handled);
 }
diff --git a/arch/arm/include/asm/cti.h b/arch/arm/include/asm/cti.h
new file mode 100644
index 000000000000..a0ada3ea4358
--- /dev/null
+++ b/arch/arm/include/asm/cti.h
@@ -0,0 +1,179 @@
+#ifndef __ASMARM_CTI_H
+#define __ASMARM_CTI_H
+#include        <asm/io.h>
+/* The registers' definition is from section 3.2 of
+ * Embedded Cross Trigger Revision: r0p0
+ */
+#define         CTICONTROL              0x000
+#define         CTISTATUS               0x004
+#define         CTILOCK                 0x008
+#define         CTIPROTECTION           0x00C
+#define         CTIINTACK               0x010
+#define         CTIAPPSET               0x014
+#define         CTIAPPCLEAR             0x018
+#define         CTIAPPPULSE             0x01c
+#define         CTIINEN                 0x020
+#define         CTIOUTEN                0x0A0
+#define         CTITRIGINSTATUS         0x130
+#define         CTITRIGOUTSTATUS        0x134
+#define         CTICHINSTATUS           0x138
+#define         CTICHOUTSTATUS          0x13c
+#define         CTIPERIPHID0            0xFE0
+#define         CTIPERIPHID1            0xFE4
+#define         CTIPERIPHID2            0xFE8
+#define         CTIPERIPHID3            0xFEC
+#define         CTIPCELLID0             0xFF0
+#define         CTIPCELLID1             0xFF4
+#define         CTIPCELLID2             0xFF8
+#define         CTIPCELLID3             0xFFC
+/* The below are from section 3.6.4 of
+ * CoreSight v1.0 Architecture Specification
+ */
+#define         LOCKACCESS              0xFB0
+#define         LOCKSTATUS              0xFB4
+/* write this value to LOCKACCESS will unlock the module, and
+ * other value will lock the module
+ */
+#define         LOCKCODE                0xC5ACCE55
+/**
+ * struct cti - cross trigger interface struct
+ * @base: mapped virtual address for the cti base
+ * @irq: irq number for the cti
+ * @trig_out_for_irq: triger out number which will cause
+ *      the @irq happen
+ *
+ * cti struct used to operate cti registers.
+ */
+struct cti {
+        void __iomem *base;
+        int irq;
+        int trig_out_for_irq;
+};
+/**
+ * cti_init - initialize the cti instance
+ * @cti: cti instance
+ * @base: mapped virtual address for the cti base
+ * @irq: irq number for the cti
+ * @trig_out: triger out number which will cause
+ *      the @irq happen
+ *
+ * called by machine code to pass the board dependent
+ * @base, @irq and @trig_out to cti.
+ */
+static inline void cti_init(struct cti *cti,
+        void __iomem *base, int irq, int trig_out)
+{
+        cti->base = base;
+        cti->irq  = irq;
+        cti->trig_out_for_irq = trig_out;
+}
+/**
+ * cti_map_trigger - use the @chan to map @trig_in to @trig_out
+ * @cti: cti instance
+ * @trig_in: trigger in number
+ * @trig_out: trigger out number
+ * @channel: channel number
+ *
+ * This function maps one trigger in of @trig_in to one trigger
+ * out of @trig_out using the channel @chan.
+ */
+static inline void cti_map_trigger(struct cti *cti,
+        int trig_in, int trig_out, int chan)
+{
+        void __iomem *base = cti->base;
+        unsigned long val;
+        val = __raw_readl(base + CTIINEN + trig_in * 4);
+        val |= BIT(chan);
+        __raw_writel(val, base + CTIINEN + trig_in * 4);
+        val = __raw_readl(base + CTIOUTEN + trig_out * 4);
+        val |= BIT(chan);
+        __raw_writel(val, base + CTIOUTEN + trig_out * 4);
+}
+/**
+ * cti_enable - enable the cti module
+ * @cti: cti instance
+ *
+ * enable the cti module
+ */
+static inline void cti_enable(struct cti *cti)
+{
+        __raw_writel(0x1, cti->base + CTICONTROL);
+}
+/**
+ * cti_disable - disable the cti module
+ * @cti: cti instance
+ *
+ * enable the cti module
+ */
+static inline void cti_disable(struct cti *cti)
+{
+        __raw_writel(0, cti->base + CTICONTROL);
+}
+/**
+ * cti_irq_ack - clear the cti irq
+ * @cti: cti instance
+ *
+ * clear the cti irq
+ */
+static inline void cti_irq_ack(struct cti *cti)
+{
+        void __iomem *base = cti->base;
+        unsigned long val;
+        val = __raw_readl(base + CTIINTACK);
+        val |= BIT(cti->trig_out_for_irq);
+        __raw_writel(val, base + CTIINTACK);
+}
+/**
+ * cti_unlock - unlock cti module
+ * @cti: cti instance
+ *
+ * unlock the cti module, or else any writes to the cti
+ * module is not allowed.
+ */
+static inline void cti_unlock(struct cti *cti)
+{
+        void __iomem *base = cti->base;
+        unsigned long val;
+        val = __raw_readl(base + LOCKSTATUS);
+        if (val & 1) {
+                val = LOCKCODE;
+                __raw_writel(val, base + LOCKACCESS);
+        }
+}
+/**
+ * cti_lock - lock cti module
+ * @cti: cti instance
+ *
+ * lock the cti module, so any writes to the cti
+ * module will be not allowed.
+ */
+static inline void cti_lock(struct cti *cti)
+{
+        void __iomem *base = cti->base;
+        unsigned long val;
+        val = __raw_readl(base + LOCKSTATUS);
+        if (!(val & 1)) {
+                val = ~LOCKCODE;
+                __raw_writel(val, base + LOCKACCESS);
+        }
+}
+#endif
diff --git a/arch/arm/include/asm/entry-macro-vic2.S b/arch/arm/include/asm/entry-macro-vic2.S
deleted file mode 100644
index 3ceb85e43850..000000000000
--- a/arch/arm/include/asm/entry-macro-vic2.S
+++ /dev/null
@@ -1,57 +0,0 @@
-/* arch/arm/include/asm/entry-macro-vic2.S
- *
- * Originally arch/arm/mach-s3c6400/include/mach/entry-macro.S
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- *      http://armlinux.simtec.co.uk/
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * Low-level IRQ helper macros for a device with two VICs
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
-*/
-/* This should be included from <mach/entry-macro.S> with the necessary
- * defines for virtual addresses and IRQ bases for the two vics.
- *
- * The code needs the following defined:
- *      IRQ_VIC0_BASE   IRQ number of VIC0's first IRQ
- *      IRQ_VIC1_BASE   IRQ number of VIC1's first IRQ
- *      VA_VIC0         Virtual address of VIC0
- *      VA_VIC1         Virtual address of VIC1
- *
- * Note, code assumes VIC0's virtual address is an ARM immediate constant
- * away from VIC1.
-*/
-#include <asm/hardware/vic.h>
-        .macro  disable_fiq
-        .endm
-        .macro  get_irqnr_preamble, base, tmp
-        ldr     \base, =VA_VIC0
-        .endm
-        .macro  arch_ret_to_user, tmp1, tmp2
-        .endm
-        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-        @ check the vic0
-        mov     \irqnr, #IRQ_VIC0_BASE + 31
-        ldr     \irqstat, [ \base, # VIC_IRQ_STATUS ]
-        teq     \irqstat, #0
-        @ otherwise try vic1
-        addeq   \tmp, \base, #(VA_VIC1 - VA_VIC0)
-        addeq   \irqnr, \irqnr, #(IRQ_VIC1_BASE - IRQ_VIC0_BASE)
-        ldreq   \irqstat, [ \tmp, # VIC_IRQ_STATUS ]
-        teqeq   \irqstat, #0
-        clzne   \irqstat, \irqstat
-        subne   \irqnr, \irqnr, \irqstat
-        .endm
diff --git a/arch/arm/include/asm/hardware/entry-macro-gic.S b/arch/arm/include/asm/hardware/entry-macro-gic.S
deleted file mode 100644
index 74ebc803904d..000000000000
--- a/arch/arm/include/asm/hardware/entry-macro-gic.S
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * arch/arm/include/asm/hardware/entry-macro-gic.S
- *
- * Low-level IRQ helper macros for GIC
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <asm/hardware/gic.h>
-#ifndef HAVE_GET_IRQNR_PREAMBLE
-        .macro  get_irqnr_preamble, base, tmp
-        ldr     \base, =gic_cpu_base_addr
-        ldr     \base, [\base]
-        .endm
-#endif
-/*
- * The interrupt numbering scheme is defined in the
- * interrupt controller spec.  To wit:
- *
- * Interrupts 0-15 are IPI
- * 16-31 are local.  We allow 30 to be used for the watchdog.
- * 32-1020 are global
- * 1021-1022 are reserved
- * 1023 is "spurious" (no interrupt)
- *
- * A simple read from the controller will tell us the number of the highest
- * priority enabled interrupt.  We then just need to check whether it is in the
- * valid range for an IRQ (30-1020 inclusive).
- */
-        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-        ldr     \irqstat, [\base, #GIC_CPU_INTACK]
-        /* bits 12-10 = src CPU, 9-0 = int # */
-        ldr     \tmp, =1021
-        bic     \irqnr, \irqstat, #0x1c00
-        cmp     \irqnr, #15
-        cmpcc   \irqnr, \irqnr
-        cmpne   \irqnr, \tmp
-        cmpcs   \irqnr, \irqnr
-        .endm
-/* We assume that irqstat (the raw value of the IRQ acknowledge
- * register) is preserved from the macro above.
- * If there is an IPI, we immediately signal end of interrupt on the
- * controller, since this requires the original irqstat value which
- * we won't easily be able to recreate later.
- */
-        .macro test_for_ipi, irqnr, irqstat, base, tmp
-        bic     \irqnr, \irqstat, #0x1c00
-        cmp     \irqnr, #16
-        strcc   \irqstat, [\base, #GIC_CPU_EOI]
-        cmpcs   \irqnr, \irqnr
-        .endm
diff --git a/arch/arm/include/asm/hardware/gic.h b/arch/arm/include/asm/hardware/gic.h
index 3e91f22046f5..4bdfe0018696 100644
--- a/arch/arm/include/asm/hardware/gic.h
+++ b/arch/arm/include/asm/hardware/gic.h
@@ -36,30 +36,22 @@
 #include <linux/irqdomain.h>
 struct device_node;
-extern void __iomem *gic_cpu_base_addr;
 extern struct irq_chip gic_arch_extn;
-void gic_init(unsigned int, int, void __iomem *, void __iomem *);
+void gic_init_bases(unsigned int, int, void __iomem *, void __iomem *,
+                    u32 offset);
 int gic_of_init(struct device_node *node, struct device_node *parent);
 void gic_secondary_init(unsigned int);
+void gic_handle_irq(struct pt_regs *regs);
 void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
 void gic_raise_softirq(const struct cpumask *mask, unsigned int irq);
-struct gic_chip_data {
+static inline void gic_init(unsigned int nr, int start,
-        void __iomem *dist_base;
+                            void __iomem *dist , void __iomem *cpu)
-        void __iomem *cpu_base;
+{
-#ifdef CONFIG_CPU_PM
+        gic_init_bases(nr, start, dist, cpu, 0);
-        u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)];
+}
-        u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)];
-        u32 saved_spi_target[DIV_ROUND_UP(1020, 4)];
-        u32 __percpu *saved_ppi_enable;
-        u32 __percpu *saved_ppi_conf;
-#endif
-#ifdef CONFIG_IRQ_DOMAIN
-        struct irq_domain domain;
-#endif
-        unsigned int gic_irqs;
-};
 #endif
 #endif
diff --git a/arch/arm/include/asm/hardware/vic.h b/arch/arm/include/asm/hardware/vic.h
index 5d72550a8097..f42ebd619590 100644
--- a/arch/arm/include/asm/hardware/vic.h
+++ b/arch/arm/include/asm/hardware/vic.h
@@ -41,7 +41,15 @@
 #define VIC_PL192_VECT_ADDR             0xF00
 #ifndef __ASSEMBLY__
+#include <linux/compiler.h>
+#include <linux/types.h>
+struct device_node;
+struct pt_regs;
 void vic_init(void __iomem *base, unsigned int irq_start, u32 vic_sources, u32 resume_sources);
-#endif
+int vic_of_init(struct device_node *node, struct device_node *parent);
+void vic_handle_irq(struct pt_regs *regs);
+#endif /* __ASSEMBLY__ */
 #endif
diff --git a/arch/arm/include/asm/mach/arch.h b/arch/arm/include/asm/mach/arch.h
index 2b0efc3104ac..bcb0c883e21e 100644
--- a/arch/arm/include/asm/mach/arch.h
+++ b/arch/arm/include/asm/mach/arch.h
@@ -31,10 +31,10 @@ struct machine_desc {
        unsigned int            video_start;    /* start of video RAM   */
        unsigned int            video_end;      /* end of video RAM     */
-        unsigned int            reserve_lp0 :1; /* never has lp0        */
+        unsigned char           reserve_lp0 :1; /* never has lp0        */
-        unsigned int            reserve_lp1 :1; /* never has lp1        */
+        unsigned char           reserve_lp1 :1; /* never has lp1        */
-        unsigned int            reserve_lp2 :1; /* never has lp2        */
+        unsigned char           reserve_lp2 :1; /* never has lp2        */
-        unsigned int            soft_reboot :1; /* soft reboot          */
+        char                    restart_mode;   /* default restart mode */
        void                    (*fixup)(struct tag *, char **,
                                         struct meminfo *);
        void                    (*reserve)(void);/* reserve mem blocks  */
@@ -46,6 +46,7 @@ struct machine_desc {
 #ifdef CONFIG_MULTI_IRQ_HANDLER
        void                    (*handle_irq)(struct pt_regs *);
 #endif
+        void                    (*restart)(char, const char *);
 };
 /*
diff --git a/arch/arm/include/asm/perf_event.h b/arch/arm/include/asm/perf_event.h
index 0f8e3827a89b..99cfe3607989 100644
--- a/arch/arm/include/asm/perf_event.h
+++ b/arch/arm/include/asm/perf_event.h
@@ -32,7 +32,4 @@ enum arm_perf_pmu_ids {
 extern enum arm_perf_pmu_ids
 armpmu_get_pmu_id(void);
-extern int
-armpmu_get_max_events(void);
 #endif /* __ARM_PERF_EVENT_H__ */
diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h
index 9451dce3a553..bcae9b81a6d0 100644
--- a/arch/arm/include/asm/pgtable.h
+++ b/arch/arm/include/asm/pgtable.h
@@ -21,7 +21,6 @@
 #else
 #include <asm/memory.h>
-#include <mach/vmalloc.h>
 #include <asm/pgtable-hwdef.h>
 #include <asm/pgtable-2level.h>
@@ -33,14 +32,16 @@
 * any out-of-bounds memory accesses will hopefully be caught.
 * The vmalloc() routines leaves a hole of 4kB between each vmalloced
 * area for the same reason. ;)
- *
- * Note that platforms may override VMALLOC_START, but they must provide
- * VMALLOC_END.  VMALLOC_END defines the (exclusive) limit of this space,
- * which may not overlap IO space.
 */
-#ifndef VMALLOC_START
 #define VMALLOC_OFFSET          (8*1024*1024)
 #define VMALLOC_START           (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
+#define VMALLOC_END             0xff000000UL
+/* This is a temporary hack until shmobile's DMA area size is sorted out */
+#ifdef CONFIG_ARCH_SHMOBILE
+#warning "SH-Mobile's consistent DMA size conflicts with VMALLOC_END by 144MB"
+#undef VMALLOC_END
+#define VMALLOC_END             0xF6000000UL
 #endif
 #define LIBRARY_TEXT_START      0x0c000000
diff --git a/arch/arm/include/asm/pmu.h b/arch/arm/include/asm/pmu.h
index 0bda22c094a6..b5a5be2536c1 100644
--- a/arch/arm/include/asm/pmu.h
+++ b/arch/arm/include/asm/pmu.h
@@ -27,13 +27,22 @@ enum arm_pmu_type {
 /*
 * struct arm_pmu_platdata - ARM PMU platform data
 *
- * @handle_irq: an optional handler which will be called from the interrupt and
+ * @handle_irq: an optional handler which will be called from the
- * passed the address of the low level handler, and can be used to implement
+ *      interrupt and passed the address of the low level handler,
- * any platform specific handling before or after calling it.
+ *      and can be used to implement any platform specific handling
+ *      before or after calling it.
+ * @enable_irq: an optional handler which will be called after
+ *      request_irq and be used to handle some platform specific
+ *      irq enablement
+ * @disable_irq: an optional handler which will be called before
+ *      free_irq and be used to handle some platform specific
+ *      irq disablement
 */
 struct arm_pmu_platdata {
        irqreturn_t (*handle_irq)(int irq, void *dev,
                                  irq_handler_t pmu_handler);
+        void (*enable_irq)(int irq);
+        void (*disable_irq)(int irq);
 };
 #ifdef CONFIG_CPU_HAS_PMU
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 984014b92647..fe7de7571bac 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -101,6 +101,7 @@ extern int __pure cpu_architecture(void);
 extern void cpu_init(void);
 void arm_machine_restart(char mode, const char *cmd);
+void soft_restart(unsigned long);
 extern void (*arm_pm_restart)(char str, const char *cmd);
 #define UDBG_UNDEFINED  (1 << 0)
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index b145f16c91bc..3a456c6c7005 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -36,12 +36,11 @@
 #ifdef CONFIG_MULTI_IRQ_HANDLER
        ldr     r1, =handle_arch_irq
        mov     r0, sp
-        ldr     r1, [r1]
        adr     lr, BSYM(9997f)
-        teq     r1, #0
+        ldr     pc, [r1]
-        movne   pc, r1
+#else
-#endif
        arch_irq_handler_default
+#endif
 9997:
        .endm
diff --git a/arch/arm/kernel/machine_kexec.c b/arch/arm/kernel/machine_kexec.c
index e59bbd496c39..29620b632ed9 100644
--- a/arch/arm/kernel/machine_kexec.c
+++ b/arch/arm/kernel/machine_kexec.c
@@ -16,7 +16,7 @@
 extern const unsigned char relocate_new_kernel[];
 extern const unsigned int relocate_new_kernel_size;
-extern void setup_mm_for_reboot(char mode);
+extern void setup_mm_for_reboot(void);
 extern unsigned long kexec_start_address;
 extern unsigned long kexec_indirection_page;
@@ -113,7 +113,7 @@ void machine_kexec(struct kimage *image)
                kexec_reinit();
        local_irq_disable();
        local_fiq_disable();
-        setup_mm_for_reboot(0); /* mode is not used, so just pass 0*/
+        setup_mm_for_reboot();
        flush_cache_all();
        outer_flush_all();
        outer_disable();
diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
index 88b0941ce51e..5bb91bf3d47f 100644
--- a/arch/arm/kernel/perf_event.c
+++ b/arch/arm/kernel/perf_event.c
@@ -59,8 +59,7 @@ armpmu_get_pmu_id(void)
 }
 EXPORT_SYMBOL_GPL(armpmu_get_pmu_id);
-int
+int perf_num_counters(void)
-armpmu_get_max_events(void)
 {
        int max_events = 0;
@@ -69,12 +68,6 @@ armpmu_get_max_events(void)
        return max_events;
 }
-EXPORT_SYMBOL_GPL(armpmu_get_max_events);
-int perf_num_counters(void)
-{
-        return armpmu_get_max_events();
-}
 EXPORT_SYMBOL_GPL(perf_num_counters);
 #define HW_OP_UNSUPPORTED               0xFFFF
@@ -380,6 +373,8 @@ armpmu_release_hardware(struct arm_pmu *armpmu)
 {
        int i, irq, irqs;
        struct platform_device *pmu_device = armpmu->plat_device;
+        struct arm_pmu_platdata *plat =
+                dev_get_platdata(&pmu_device->dev);
        irqs = min(pmu_device->num_resources, num_possible_cpus());
@@ -387,8 +382,11 @@ armpmu_release_hardware(struct arm_pmu *armpmu)
                if (!cpumask_test_and_clear_cpu(i, &armpmu->active_irqs))
                        continue;
                irq = platform_get_irq(pmu_device, i);
-                if (irq >= 0)
+                if (irq >= 0) {
+                        if (plat && plat->disable_irq)
+                                plat->disable_irq(irq);
                        free_irq(irq, armpmu);
+                }
        }
        release_pmu(armpmu->type);
@@ -448,7 +446,8 @@ armpmu_reserve_hardware(struct arm_pmu *armpmu)
                                irq);
                        armpmu_release_hardware(armpmu);
                        return err;
-                }
+                } else if (plat && plat->enable_irq)
+                        plat->enable_irq(irq);
                cpumask_set_cpu(i, &armpmu->active_irqs);
        }
diff --git a/arch/arm/kernel/perf_event_v6.c b/arch/arm/kernel/perf_event_v6.c
index e63d8115c01b..533be9930ec2 100644
--- a/arch/arm/kernel/perf_event_v6.c
+++ b/arch/arm/kernel/perf_event_v6.c
@@ -65,13 +65,15 @@ enum armv6_counters {
 * accesses/misses in hardware.
 */
 static const unsigned armv6_perf_map[PERF_COUNT_HW_MAX] = {
-        [PERF_COUNT_HW_CPU_CYCLES]          = ARMV6_PERFCTR_CPU_CYCLES,
+        [PERF_COUNT_HW_CPU_CYCLES]              = ARMV6_PERFCTR_CPU_CYCLES,
-        [PERF_COUNT_HW_INSTRUCTIONS]        = ARMV6_PERFCTR_INSTR_EXEC,
+        [PERF_COUNT_HW_INSTRUCTIONS]            = ARMV6_PERFCTR_INSTR_EXEC,
-        [PERF_COUNT_HW_CACHE_REFERENCES]    = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_CACHE_REFERENCES]        = HW_OP_UNSUPPORTED,
-        [PERF_COUNT_HW_CACHE_MISSES]        = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_CACHE_MISSES]            = HW_OP_UNSUPPORTED,
-        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV6_PERFCTR_BR_EXEC,
+        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]     = ARMV6_PERFCTR_BR_EXEC,
-        [PERF_COUNT_HW_BRANCH_MISSES]       = ARMV6_PERFCTR_BR_MISPREDICT,
+        [PERF_COUNT_HW_BRANCH_MISSES]           = ARMV6_PERFCTR_BR_MISPREDICT,
-        [PERF_COUNT_HW_BUS_CYCLES]          = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_BUS_CYCLES]              = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV6_PERFCTR_IBUF_STALL,
+        [PERF_COUNT_HW_STALLED_CYCLES_BACKEND]  = ARMV6_PERFCTR_LSU_FULL_STALL,
 };
 static const unsigned armv6_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
@@ -218,13 +220,15 @@ enum armv6mpcore_perf_types {
 * accesses/misses in hardware.
 */
 static const unsigned armv6mpcore_perf_map[PERF_COUNT_HW_MAX] = {
-        [PERF_COUNT_HW_CPU_CYCLES]          = ARMV6MPCORE_PERFCTR_CPU_CYCLES,
+        [PERF_COUNT_HW_CPU_CYCLES]              = ARMV6MPCORE_PERFCTR_CPU_CYCLES,
-        [PERF_COUNT_HW_INSTRUCTIONS]        = ARMV6MPCORE_PERFCTR_INSTR_EXEC,
+        [PERF_COUNT_HW_INSTRUCTIONS]            = ARMV6MPCORE_PERFCTR_INSTR_EXEC,
-        [PERF_COUNT_HW_CACHE_REFERENCES]    = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_CACHE_REFERENCES]        = HW_OP_UNSUPPORTED,
-        [PERF_COUNT_HW_CACHE_MISSES]        = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_CACHE_MISSES]            = HW_OP_UNSUPPORTED,
-        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV6MPCORE_PERFCTR_BR_EXEC,
+        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]     = ARMV6MPCORE_PERFCTR_BR_EXEC,
-        [PERF_COUNT_HW_BRANCH_MISSES]       = ARMV6MPCORE_PERFCTR_BR_MISPREDICT,
+        [PERF_COUNT_HW_BRANCH_MISSES]           = ARMV6MPCORE_PERFCTR_BR_MISPREDICT,
-        [PERF_COUNT_HW_BUS_CYCLES]          = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_BUS_CYCLES]              = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV6MPCORE_PERFCTR_IBUF_STALL,
+        [PERF_COUNT_HW_STALLED_CYCLES_BACKEND]  = ARMV6MPCORE_PERFCTR_LSU_FULL_STALL,
 };
 static const unsigned armv6mpcore_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c
index 1ef6d0034b85..460bbbb6b885 100644
--- a/arch/arm/kernel/perf_event_v7.c
+++ b/arch/arm/kernel/perf_event_v7.c
@@ -28,165 +28,87 @@ static struct arm_pmu armv7pmu;
 * they are not available.
 */
 enum armv7_perf_types {
-        ARMV7_PERFCTR_PMNC_SW_INCR              = 0x00,
+        ARMV7_PERFCTR_PMNC_SW_INCR                      = 0x00,
-        ARMV7_PERFCTR_IFETCH_MISS               = 0x01,
+        ARMV7_PERFCTR_L1_ICACHE_REFILL                  = 0x01,
-        ARMV7_PERFCTR_ITLB_MISS                 = 0x02,
+        ARMV7_PERFCTR_ITLB_REFILL                       = 0x02,
-        ARMV7_PERFCTR_DCACHE_REFILL             = 0x03, /* L1 */
+        ARMV7_PERFCTR_L1_DCACHE_REFILL                  = 0x03,
-        ARMV7_PERFCTR_DCACHE_ACCESS             = 0x04, /* L1 */
+        ARMV7_PERFCTR_L1_DCACHE_ACCESS                  = 0x04,
-        ARMV7_PERFCTR_DTLB_REFILL               = 0x05,
+        ARMV7_PERFCTR_DTLB_REFILL                       = 0x05,
-        ARMV7_PERFCTR_DREAD                     = 0x06,
+        ARMV7_PERFCTR_MEM_READ                          = 0x06,
-        ARMV7_PERFCTR_DWRITE                    = 0x07,
+        ARMV7_PERFCTR_MEM_WRITE                         = 0x07,
-        ARMV7_PERFCTR_INSTR_EXECUTED            = 0x08,
+        ARMV7_PERFCTR_INSTR_EXECUTED                    = 0x08,
-        ARMV7_PERFCTR_EXC_TAKEN                 = 0x09,
+        ARMV7_PERFCTR_EXC_TAKEN                         = 0x09,
-        ARMV7_PERFCTR_EXC_EXECUTED              = 0x0A,
+        ARMV7_PERFCTR_EXC_EXECUTED                      = 0x0A,
-        ARMV7_PERFCTR_CID_WRITE                 = 0x0B,
+        ARMV7_PERFCTR_CID_WRITE                         = 0x0B,
-        /* ARMV7_PERFCTR_PC_WRITE is equivalent to HW_BRANCH_INSTRUCTIONS.
+        /*
+         * ARMV7_PERFCTR_PC_WRITE is equivalent to HW_BRANCH_INSTRUCTIONS.
         * It counts:
-         *  - all branch instructions,
+         *  - all (taken) branch instructions,
         *  - instructions that explicitly write the PC,
         *  - exception generating instructions.
         */
-        ARMV7_PERFCTR_PC_WRITE                  = 0x0C,
+        ARMV7_PERFCTR_PC_WRITE                          = 0x0C,
-        ARMV7_PERFCTR_PC_IMM_BRANCH             = 0x0D,
+        ARMV7_PERFCTR_PC_IMM_BRANCH                     = 0x0D,
-        ARMV7_PERFCTR_PC_PROC_RETURN            = 0x0E,
+        ARMV7_PERFCTR_PC_PROC_RETURN                    = 0x0E,
-        ARMV7_PERFCTR_UNALIGNED_ACCESS          = 0x0F,
+        ARMV7_PERFCTR_MEM_UNALIGNED_ACCESS              = 0x0F,
+        ARMV7_PERFCTR_PC_BRANCH_MIS_PRED                = 0x10,
+        ARMV7_PERFCTR_CLOCK_CYCLES                      = 0x11,
+        ARMV7_PERFCTR_PC_BRANCH_PRED                    = 0x12,
        /* These events are defined by the PMUv2 supplement (ARM DDI 0457A). */
-        ARMV7_PERFCTR_PC_BRANCH_MIS_PRED        = 0x10,
+        ARMV7_PERFCTR_MEM_ACCESS                        = 0x13,
-        ARMV7_PERFCTR_CLOCK_CYCLES              = 0x11,
+        ARMV7_PERFCTR_L1_ICACHE_ACCESS                  = 0x14,
-        ARMV7_PERFCTR_PC_BRANCH_PRED            = 0x12,
+        ARMV7_PERFCTR_L1_DCACHE_WB                      = 0x15,
-        ARMV7_PERFCTR_MEM_ACCESS                = 0x13,
+        ARMV7_PERFCTR_L2_CACHE_ACCESS                   = 0x16,
-        ARMV7_PERFCTR_L1_ICACHE_ACCESS          = 0x14,
+        ARMV7_PERFCTR_L2_CACHE_REFILL                   = 0x17,
-        ARMV7_PERFCTR_L1_DCACHE_WB              = 0x15,
+        ARMV7_PERFCTR_L2_CACHE_WB                       = 0x18,
-        ARMV7_PERFCTR_L2_DCACHE_ACCESS          = 0x16,
+        ARMV7_PERFCTR_BUS_ACCESS                        = 0x19,
-        ARMV7_PERFCTR_L2_DCACHE_REFILL          = 0x17,
+        ARMV7_PERFCTR_MEM_ERROR                         = 0x1A,
-        ARMV7_PERFCTR_L2_DCACHE_WB              = 0x18,
+        ARMV7_PERFCTR_INSTR_SPEC                        = 0x1B,
-        ARMV7_PERFCTR_BUS_ACCESS                = 0x19,
+        ARMV7_PERFCTR_TTBR_WRITE                        = 0x1C,
-        ARMV7_PERFCTR_MEMORY_ERROR              = 0x1A,
+        ARMV7_PERFCTR_BUS_CYCLES                        = 0x1D,
-        ARMV7_PERFCTR_INSTR_SPEC                = 0x1B,
-        ARMV7_PERFCTR_TTBR_WRITE                = 0x1C,
+        ARMV7_PERFCTR_CPU_CYCLES                        = 0xFF
-        ARMV7_PERFCTR_BUS_CYCLES                = 0x1D,
-        ARMV7_PERFCTR_CPU_CYCLES                = 0xFF
 };
 /* ARMv7 Cortex-A8 specific event types */
 enum armv7_a8_perf_types {
-        ARMV7_PERFCTR_WRITE_BUFFER_FULL         = 0x40,
+        ARMV7_A8_PERFCTR_L2_CACHE_ACCESS                = 0x43,
-        ARMV7_PERFCTR_L2_STORE_MERGED           = 0x41,
+        ARMV7_A8_PERFCTR_L2_CACHE_REFILL                = 0x44,
-        ARMV7_PERFCTR_L2_STORE_BUFF             = 0x42,
+        ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS               = 0x50,
-        ARMV7_PERFCTR_L2_ACCESS                 = 0x43,
+        ARMV7_A8_PERFCTR_STALL_ISIDE                    = 0x56,
-        ARMV7_PERFCTR_L2_CACH_MISS              = 0x44,
-        ARMV7_PERFCTR_AXI_READ_CYCLES           = 0x45,
-        ARMV7_PERFCTR_AXI_WRITE_CYCLES          = 0x46,
-        ARMV7_PERFCTR_MEMORY_REPLAY             = 0x47,
-        ARMV7_PERFCTR_UNALIGNED_ACCESS_REPLAY   = 0x48,
-        ARMV7_PERFCTR_L1_DATA_MISS              = 0x49,
-        ARMV7_PERFCTR_L1_INST_MISS              = 0x4A,
-        ARMV7_PERFCTR_L1_DATA_COLORING          = 0x4B,
-        ARMV7_PERFCTR_L1_NEON_DATA              = 0x4C,
-        ARMV7_PERFCTR_L1_NEON_CACH_DATA         = 0x4D,
-        ARMV7_PERFCTR_L2_NEON                   = 0x4E,
-        ARMV7_PERFCTR_L2_NEON_HIT               = 0x4F,
-        ARMV7_PERFCTR_L1_INST                   = 0x50,
-        ARMV7_PERFCTR_PC_RETURN_MIS_PRED        = 0x51,
-        ARMV7_PERFCTR_PC_BRANCH_FAILED          = 0x52,
-        ARMV7_PERFCTR_PC_BRANCH_TAKEN           = 0x53,
-        ARMV7_PERFCTR_PC_BRANCH_EXECUTED        = 0x54,
-        ARMV7_PERFCTR_OP_EXECUTED               = 0x55,
-        ARMV7_PERFCTR_CYCLES_INST_STALL         = 0x56,
-        ARMV7_PERFCTR_CYCLES_INST               = 0x57,
-        ARMV7_PERFCTR_CYCLES_NEON_DATA_STALL    = 0x58,
-        ARMV7_PERFCTR_CYCLES_NEON_INST_STALL    = 0x59,
-        ARMV7_PERFCTR_NEON_CYCLES               = 0x5A,
-        ARMV7_PERFCTR_PMU0_EVENTS               = 0x70,
-        ARMV7_PERFCTR_PMU1_EVENTS               = 0x71,
-        ARMV7_PERFCTR_PMU_EVENTS                = 0x72,
 };
 /* ARMv7 Cortex-A9 specific event types */
 enum armv7_a9_perf_types {
-        ARMV7_PERFCTR_JAVA_HW_BYTECODE_EXEC     = 0x40,
+        ARMV7_A9_PERFCTR_INSTR_CORE_RENAME              = 0x68,
-        ARMV7_PERFCTR_JAVA_SW_BYTECODE_EXEC     = 0x41,
+        ARMV7_A9_PERFCTR_STALL_ICACHE                   = 0x60,
-        ARMV7_PERFCTR_JAZELLE_BRANCH_EXEC       = 0x42,
+        ARMV7_A9_PERFCTR_STALL_DISPATCH                 = 0x66,
-        ARMV7_PERFCTR_COHERENT_LINE_MISS        = 0x50,
-        ARMV7_PERFCTR_COHERENT_LINE_HIT         = 0x51,
-        ARMV7_PERFCTR_ICACHE_DEP_STALL_CYCLES   = 0x60,
-        ARMV7_PERFCTR_DCACHE_DEP_STALL_CYCLES   = 0x61,
-        ARMV7_PERFCTR_TLB_MISS_DEP_STALL_CYCLES = 0x62,
-        ARMV7_PERFCTR_STREX_EXECUTED_PASSED     = 0x63,
-        ARMV7_PERFCTR_STREX_EXECUTED_FAILED     = 0x64,
-        ARMV7_PERFCTR_DATA_EVICTION             = 0x65,
-        ARMV7_PERFCTR_ISSUE_STAGE_NO_INST       = 0x66,
-        ARMV7_PERFCTR_ISSUE_STAGE_EMPTY         = 0x67,
-        ARMV7_PERFCTR_INST_OUT_OF_RENAME_STAGE  = 0x68,
-        ARMV7_PERFCTR_PREDICTABLE_FUNCT_RETURNS = 0x6E,
-        ARMV7_PERFCTR_MAIN_UNIT_EXECUTED_INST   = 0x70,
-        ARMV7_PERFCTR_SECOND_UNIT_EXECUTED_INST = 0x71,
-        ARMV7_PERFCTR_LD_ST_UNIT_EXECUTED_INST  = 0x72,
-        ARMV7_PERFCTR_FP_EXECUTED_INST          = 0x73,
-        ARMV7_PERFCTR_NEON_EXECUTED_INST        = 0x74,
-        ARMV7_PERFCTR_PLD_FULL_DEP_STALL_CYCLES = 0x80,
-        ARMV7_PERFCTR_DATA_WR_DEP_STALL_CYCLES  = 0x81,
-        ARMV7_PERFCTR_ITLB_MISS_DEP_STALL_CYCLES        = 0x82,
-        ARMV7_PERFCTR_DTLB_MISS_DEP_STALL_CYCLES        = 0x83,
-        ARMV7_PERFCTR_MICRO_ITLB_MISS_DEP_STALL_CYCLES  = 0x84,
-        ARMV7_PERFCTR_MICRO_DTLB_MISS_DEP_STALL_CYCLES  = 0x85,
-        ARMV7_PERFCTR_DMB_DEP_STALL_CYCLES      = 0x86,
-        ARMV7_PERFCTR_INTGR_CLK_ENABLED_CYCLES  = 0x8A,
-        ARMV7_PERFCTR_DATA_ENGINE_CLK_EN_CYCLES = 0x8B,
-        ARMV7_PERFCTR_ISB_INST                  = 0x90,
-        ARMV7_PERFCTR_DSB_INST                  = 0x91,
-        ARMV7_PERFCTR_DMB_INST                  = 0x92,
-        ARMV7_PERFCTR_EXT_INTERRUPTS            = 0x93,
-        ARMV7_PERFCTR_PLE_CACHE_LINE_RQST_COMPLETED     = 0xA0,
-        ARMV7_PERFCTR_PLE_CACHE_LINE_RQST_SKIPPED       = 0xA1,
-        ARMV7_PERFCTR_PLE_FIFO_FLUSH            = 0xA2,
-        ARMV7_PERFCTR_PLE_RQST_COMPLETED        = 0xA3,
-        ARMV7_PERFCTR_PLE_FIFO_OVERFLOW         = 0xA4,
-        ARMV7_PERFCTR_PLE_RQST_PROG             = 0xA5
 };
 /* ARMv7 Cortex-A5 specific event types */
 enum armv7_a5_perf_types {
-        ARMV7_PERFCTR_IRQ_TAKEN                 = 0x86,
+        ARMV7_A5_PERFCTR_PREFETCH_LINEFILL              = 0xc2,
-        ARMV7_PERFCTR_FIQ_TAKEN                 = 0x87,
+        ARMV7_A5_PERFCTR_PREFETCH_LINEFILL_DROP         = 0xc3,
-        ARMV7_PERFCTR_EXT_MEM_RQST              = 0xc0,
-        ARMV7_PERFCTR_NC_EXT_MEM_RQST           = 0xc1,
-        ARMV7_PERFCTR_PREFETCH_LINEFILL         = 0xc2,
-        ARMV7_PERFCTR_PREFETCH_LINEFILL_DROP    = 0xc3,
-        ARMV7_PERFCTR_ENTER_READ_ALLOC          = 0xc4,
-        ARMV7_PERFCTR_READ_ALLOC                = 0xc5,
-        ARMV7_PERFCTR_STALL_SB_FULL             = 0xc9,
 };
 /* ARMv7 Cortex-A15 specific event types */
 enum armv7_a15_perf_types {
-        ARMV7_PERFCTR_L1_DCACHE_READ_ACCESS     = 0x40,
+        ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_READ         = 0x40,
-        ARMV7_PERFCTR_L1_DCACHE_WRITE_ACCESS    = 0x41,
+        ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_WRITE        = 0x41,
-        ARMV7_PERFCTR_L1_DCACHE_READ_REFILL     = 0x42,
+        ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_READ         = 0x42,
-        ARMV7_PERFCTR_L1_DCACHE_WRITE_REFILL    = 0x43,
+        ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_WRITE        = 0x43,
-        ARMV7_PERFCTR_L1_DTLB_READ_REFILL       = 0x4C,
+        ARMV7_A15_PERFCTR_DTLB_REFILL_L1_READ           = 0x4C,
-        ARMV7_PERFCTR_L1_DTLB_WRITE_REFILL      = 0x4D,
+        ARMV7_A15_PERFCTR_DTLB_REFILL_L1_WRITE          = 0x4D,
-        ARMV7_PERFCTR_L2_DCACHE_READ_ACCESS     = 0x50,
+        ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_READ          = 0x50,
-        ARMV7_PERFCTR_L2_DCACHE_WRITE_ACCESS    = 0x51,
+        ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_WRITE         = 0x51,
-        ARMV7_PERFCTR_L2_DCACHE_READ_REFILL     = 0x52,
+        ARMV7_A15_PERFCTR_L2_CACHE_REFILL_READ          = 0x52,
-        ARMV7_PERFCTR_L2_DCACHE_WRITE_REFILL    = 0x53,
+        ARMV7_A15_PERFCTR_L2_CACHE_REFILL_WRITE         = 0x53,
-        ARMV7_PERFCTR_SPEC_PC_WRITE             = 0x76,
+        ARMV7_A15_PERFCTR_PC_WRITE_SPEC                 = 0x76,
 };
 /*
@@ -197,13 +119,15 @@ enum armv7_a15_perf_types {
 * accesses/misses in hardware.
 */
 static const unsigned armv7_a8_perf_map[PERF_COUNT_HW_MAX] = {
-        [PERF_COUNT_HW_CPU_CYCLES]          = ARMV7_PERFCTR_CPU_CYCLES,
+        [PERF_COUNT_HW_CPU_CYCLES]              = ARMV7_PERFCTR_CPU_CYCLES,
-        [PERF_COUNT_HW_INSTRUCTIONS]        = ARMV7_PERFCTR_INSTR_EXECUTED,
+        [PERF_COUNT_HW_INSTRUCTIONS]            = ARMV7_PERFCTR_INSTR_EXECUTED,
-        [PERF_COUNT_HW_CACHE_REFERENCES]    = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_CACHE_REFERENCES]        = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
-        [PERF_COUNT_HW_CACHE_MISSES]        = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_CACHE_MISSES]            = ARMV7_PERFCTR_L1_DCACHE_REFILL,
-        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
+        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]     = ARMV7_PERFCTR_PC_WRITE,
-        [PERF_COUNT_HW_BRANCH_MISSES]       = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
+        [PERF_COUNT_HW_BRANCH_MISSES]           = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
-        [PERF_COUNT_HW_BUS_CYCLES]          = ARMV7_PERFCTR_CLOCK_CYCLES,
+        [PERF_COUNT_HW_BUS_CYCLES]              = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV7_A8_PERFCTR_STALL_ISIDE,
+        [PERF_COUNT_HW_STALLED_CYCLES_BACKEND]  = HW_OP_UNSUPPORTED,
 };
 static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
@@ -217,12 +141,12 @@ static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
                 * combined.
                 */
                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_DCACHE_ACCESS,
+                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_DCACHE_REFILL,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_DCACHE_REFILL,
                },
                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_DCACHE_ACCESS,
+                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_DCACHE_REFILL,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_DCACHE_REFILL,
                },
                [C(OP_PREFETCH)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
@@ -231,12 +155,12 @@ static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
        },
        [C(L1I)] = {
                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_L1_INST,
+                        [C(RESULT_ACCESS)]      = ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_INST_MISS,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_ICACHE_REFILL,
                },
                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_L1_INST,
+                        [C(RESULT_ACCESS)]      = ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_INST_MISS,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_ICACHE_REFILL,
                },
                [C(OP_PREFETCH)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
@@ -245,12 +169,12 @@ static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
        },
        [C(LL)] = {
                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_L2_ACCESS,
+                        [C(RESULT_ACCESS)]      = ARMV7_A8_PERFCTR_L2_CACHE_ACCESS,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L2_CACH_MISS,
+                        [C(RESULT_MISS)]        = ARMV7_A8_PERFCTR_L2_CACHE_REFILL,
                },
                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_L2_ACCESS,
+                        [C(RESULT_ACCESS)]      = ARMV7_A8_PERFCTR_L2_CACHE_ACCESS,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L2_CACH_MISS,
+                        [C(RESULT_MISS)]        = ARMV7_A8_PERFCTR_L2_CACHE_REFILL,
                },
                [C(OP_PREFETCH)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
@@ -274,11 +198,11 @@ static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
        [C(ITLB)] = {
                [C(OP_READ)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_ITLB_MISS,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_ITLB_REFILL,
                },
                [C(OP_WRITE)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_ITLB_MISS,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_ITLB_REFILL,
                },
                [C(OP_PREFETCH)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
@@ -287,14 +211,12 @@ static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
        },
        [C(BPU)] = {
                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_PC_WRITE,
+                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_PC_BRANCH_PRED,
-                        [C(RESULT_MISS)]
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
-                                        = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
                },
                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_PC_WRITE,
+                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_PC_BRANCH_PRED,
-                        [C(RESULT_MISS)]
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
-                                        = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
                },
                [C(OP_PREFETCH)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
@@ -321,14 +243,15 @@ static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
 * Cortex-A9 HW events mapping
 */
 static const unsigned armv7_a9_perf_map[PERF_COUNT_HW_MAX] = {
-        [PERF_COUNT_HW_CPU_CYCLES]          = ARMV7_PERFCTR_CPU_CYCLES,
+        [PERF_COUNT_HW_CPU_CYCLES]              = ARMV7_PERFCTR_CPU_CYCLES,
-        [PERF_COUNT_HW_INSTRUCTIONS]        =
+        [PERF_COUNT_HW_INSTRUCTIONS]            = ARMV7_A9_PERFCTR_INSTR_CORE_RENAME,
-                                        ARMV7_PERFCTR_INST_OUT_OF_RENAME_STAGE,
+        [PERF_COUNT_HW_CACHE_REFERENCES]        = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
-        [PERF_COUNT_HW_CACHE_REFERENCES]    = ARMV7_PERFCTR_DCACHE_ACCESS,
+        [PERF_COUNT_HW_CACHE_MISSES]            = ARMV7_PERFCTR_L1_DCACHE_REFILL,
-        [PERF_COUNT_HW_CACHE_MISSES]        = ARMV7_PERFCTR_DCACHE_REFILL,
+        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]     = ARMV7_PERFCTR_PC_WRITE,
-        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
+        [PERF_COUNT_HW_BRANCH_MISSES]           = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
-        [PERF_COUNT_HW_BRANCH_MISSES]       = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
+        [PERF_COUNT_HW_BUS_CYCLES]              = HW_OP_UNSUPPORTED,
-        [PERF_COUNT_HW_BUS_CYCLES]          = ARMV7_PERFCTR_CLOCK_CYCLES,
+        [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV7_A9_PERFCTR_STALL_ICACHE,
+        [PERF_COUNT_HW_STALLED_CYCLES_BACKEND]  = ARMV7_A9_PERFCTR_STALL_DISPATCH,
 };
 static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
@@ -342,12 +265,12 @@ static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
                 * combined.
                 */
                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_DCACHE_ACCESS,
+                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_DCACHE_REFILL,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_DCACHE_REFILL,
                },
                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_DCACHE_ACCESS,
+                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_DCACHE_REFILL,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_DCACHE_REFILL,
                },
                [C(OP_PREFETCH)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
@@ -357,11 +280,11 @@ static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
        [C(L1I)] = {
                [C(OP_READ)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_IFETCH_MISS,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_ICACHE_REFILL,
                },
                [C(OP_WRITE)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_IFETCH_MISS,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_ICACHE_REFILL,
                },
                [C(OP_PREFETCH)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
@@ -399,11 +322,11 @@ static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
        [C(ITLB)] = {
                [C(OP_READ)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_ITLB_MISS,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_ITLB_REFILL,
                },
                [C(OP_WRITE)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_ITLB_MISS,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_ITLB_REFILL,
                },
                [C(OP_PREFETCH)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
@@ -412,14 +335,12 @@ static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
        },
        [C(BPU)] = {
                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_PC_WRITE,
+                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_PC_BRANCH_PRED,
-                        [C(RESULT_MISS)]
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
-                                        = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
                },
                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_PC_WRITE,
+                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_PC_BRANCH_PRED,
-                        [C(RESULT_MISS)]
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
-                                        = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
                },
                [C(OP_PREFETCH)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
@@ -446,13 +367,15 @@ static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
 * Cortex-A5 HW events mapping
 */
 static const unsigned armv7_a5_perf_map[PERF_COUNT_HW_MAX] = {
-        [PERF_COUNT_HW_CPU_CYCLES]          = ARMV7_PERFCTR_CPU_CYCLES,
+        [PERF_COUNT_HW_CPU_CYCLES]              = ARMV7_PERFCTR_CPU_CYCLES,
-        [PERF_COUNT_HW_INSTRUCTIONS]        = ARMV7_PERFCTR_INSTR_EXECUTED,
+        [PERF_COUNT_HW_INSTRUCTIONS]            = ARMV7_PERFCTR_INSTR_EXECUTED,
-        [PERF_COUNT_HW_CACHE_REFERENCES]    = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_CACHE_REFERENCES]        = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
-        [PERF_COUNT_HW_CACHE_MISSES]        = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_CACHE_MISSES]            = ARMV7_PERFCTR_L1_DCACHE_REFILL,
-        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
+        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]     = ARMV7_PERFCTR_PC_WRITE,
-        [PERF_COUNT_HW_BRANCH_MISSES]       = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
+        [PERF_COUNT_HW_BRANCH_MISSES]           = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
-        [PERF_COUNT_HW_BUS_CYCLES]          = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_BUS_CYCLES]              = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_STALLED_CYCLES_BACKEND]  = HW_OP_UNSUPPORTED,
 };
 static const unsigned armv7_a5_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
@@ -460,42 +383,34 @@ static const unsigned armv7_a5_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
                                        [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
        [C(L1D)] = {
                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]
+                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
-                                        = ARMV7_PERFCTR_DCACHE_ACCESS,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_DCACHE_REFILL,
-                        [C(RESULT_MISS)]
-                                        = ARMV7_PERFCTR_DCACHE_REFILL,
                },
                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]
+                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
-                                        = ARMV7_PERFCTR_DCACHE_ACCESS,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_DCACHE_REFILL,
-                        [C(RESULT_MISS)]
-                                        = ARMV7_PERFCTR_DCACHE_REFILL,
                },
                [C(OP_PREFETCH)] = {
-                        [C(RESULT_ACCESS)]
+                        [C(RESULT_ACCESS)]      = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL,
-                                        = ARMV7_PERFCTR_PREFETCH_LINEFILL,
+                        [C(RESULT_MISS)]        = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL_DROP,
-                        [C(RESULT_MISS)]
-                                        = ARMV7_PERFCTR_PREFETCH_LINEFILL_DROP,
                },
        },
        [C(L1I)] = {
                [C(OP_READ)] = {
                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_L1_ICACHE_ACCESS,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_IFETCH_MISS,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_ICACHE_REFILL,
                },
                [C(OP_WRITE)] = {
                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_L1_ICACHE_ACCESS,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_IFETCH_MISS,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_ICACHE_REFILL,
                },
                /*
                 * The prefetch counters don't differentiate between the I
                 * side and the D side.
                 */
                [C(OP_PREFETCH)] = {
-                        [C(RESULT_ACCESS)]
+                        [C(RESULT_ACCESS)]      = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL,
-                                        = ARMV7_PERFCTR_PREFETCH_LINEFILL,
+                        [C(RESULT_MISS)]        = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL_DROP,
-                        [C(RESULT_MISS)]
-                                        = ARMV7_PERFCTR_PREFETCH_LINEFILL_DROP,
                },
        },
        [C(LL)] = {
@@ -529,11 +444,11 @@ static const unsigned armv7_a5_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
        [C(ITLB)] = {
                [C(OP_READ)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_ITLB_MISS,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_ITLB_REFILL,
                },
                [C(OP_WRITE)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_ITLB_MISS,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_ITLB_REFILL,
                },
                [C(OP_PREFETCH)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
@@ -543,13 +458,11 @@ static const unsigned armv7_a5_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
        [C(BPU)] = {
                [C(OP_READ)] = {
                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_PC_BRANCH_PRED,
-                        [C(RESULT_MISS)]
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
-                                        = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
                },
                [C(OP_WRITE)] = {
                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_PC_BRANCH_PRED,
-                        [C(RESULT_MISS)]
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
-                                        = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
                },
                [C(OP_PREFETCH)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
@@ -562,13 +475,15 @@ static const unsigned armv7_a5_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
 * Cortex-A15 HW events mapping
 */
 static const unsigned armv7_a15_perf_map[PERF_COUNT_HW_MAX] = {
-        [PERF_COUNT_HW_CPU_CYCLES]          = ARMV7_PERFCTR_CPU_CYCLES,
+        [PERF_COUNT_HW_CPU_CYCLES]              = ARMV7_PERFCTR_CPU_CYCLES,
-        [PERF_COUNT_HW_INSTRUCTIONS]        = ARMV7_PERFCTR_INSTR_EXECUTED,
+        [PERF_COUNT_HW_INSTRUCTIONS]            = ARMV7_PERFCTR_INSTR_EXECUTED,
-        [PERF_COUNT_HW_CACHE_REFERENCES]    = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_CACHE_REFERENCES]        = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
-        [PERF_COUNT_HW_CACHE_MISSES]        = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_CACHE_MISSES]            = ARMV7_PERFCTR_L1_DCACHE_REFILL,
-        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_SPEC_PC_WRITE,
+        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]     = ARMV7_A15_PERFCTR_PC_WRITE_SPEC,
-        [PERF_COUNT_HW_BRANCH_MISSES]       = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
+        [PERF_COUNT_HW_BRANCH_MISSES]           = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
-        [PERF_COUNT_HW_BUS_CYCLES]          = ARMV7_PERFCTR_BUS_CYCLES,
+        [PERF_COUNT_HW_BUS_CYCLES]              = ARMV7_PERFCTR_BUS_CYCLES,
+        [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_STALLED_CYCLES_BACKEND]  = HW_OP_UNSUPPORTED,
 };
 static const unsigned armv7_a15_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
@@ -576,16 +491,12 @@ static const unsigned armv7_a15_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
                                        [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
        [C(L1D)] = {
                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]
+                        [C(RESULT_ACCESS)]      = ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_READ,
-                                        = ARMV7_PERFCTR_L1_DCACHE_READ_ACCESS,
+                        [C(RESULT_MISS)]        = ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_READ,
-                        [C(RESULT_MISS)]
-                                        = ARMV7_PERFCTR_L1_DCACHE_READ_REFILL,
                },
                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]
+                        [C(RESULT_ACCESS)]      = ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_WRITE,
-                                        = ARMV7_PERFCTR_L1_DCACHE_WRITE_ACCESS,
+                        [C(RESULT_MISS)]        = ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_WRITE,
-                        [C(RESULT_MISS)]
-                                        = ARMV7_PERFCTR_L1_DCACHE_WRITE_REFILL,
                },
                [C(OP_PREFETCH)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
@@ -601,11 +512,11 @@ static const unsigned armv7_a15_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
                 */
                [C(OP_READ)] = {
                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_L1_ICACHE_ACCESS,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_IFETCH_MISS,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_ICACHE_REFILL,
                },
                [C(OP_WRITE)] = {
                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_L1_ICACHE_ACCESS,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_IFETCH_MISS,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_ICACHE_REFILL,
                },
                [C(OP_PREFETCH)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
@@ -614,16 +525,12 @@ static const unsigned armv7_a15_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
        },
        [C(LL)] = {
                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]
+                        [C(RESULT_ACCESS)]      = ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_READ,
-                                        = ARMV7_PERFCTR_L2_DCACHE_READ_ACCESS,
+                        [C(RESULT_MISS)]        = ARMV7_A15_PERFCTR_L2_CACHE_REFILL_READ,
-                        [C(RESULT_MISS)]
-                                        = ARMV7_PERFCTR_L2_DCACHE_READ_REFILL,
                },
                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]
+                        [C(RESULT_ACCESS)]      = ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_WRITE,
-                                        = ARMV7_PERFCTR_L2_DCACHE_WRITE_ACCESS,
+                        [C(RESULT_MISS)]        = ARMV7_A15_PERFCTR_L2_CACHE_REFILL_WRITE,
-                        [C(RESULT_MISS)]
-                                        = ARMV7_PERFCTR_L2_DCACHE_WRITE_REFILL,
                },
                [C(OP_PREFETCH)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
@@ -633,13 +540,11 @@ static const unsigned armv7_a15_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
        [C(DTLB)] = {
                [C(OP_READ)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]
+                        [C(RESULT_MISS)]        = ARMV7_A15_PERFCTR_DTLB_REFILL_L1_READ,
-                                        = ARMV7_PERFCTR_L1_DTLB_READ_REFILL,
                },
                [C(OP_WRITE)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]
+                        [C(RESULT_MISS)]        = ARMV7_A15_PERFCTR_DTLB_REFILL_L1_WRITE,
-                                        = ARMV7_PERFCTR_L1_DTLB_WRITE_REFILL,
                },
                [C(OP_PREFETCH)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
@@ -649,11 +554,11 @@ static const unsigned armv7_a15_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
        [C(ITLB)] = {
                [C(OP_READ)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_ITLB_MISS,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_ITLB_REFILL,
                },
                [C(OP_WRITE)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_ITLB_MISS,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_ITLB_REFILL,
                },
                [C(OP_PREFETCH)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
@@ -663,13 +568,11 @@ static const unsigned armv7_a15_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
        [C(BPU)] = {
                [C(OP_READ)] = {
                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_PC_BRANCH_PRED,
-                        [C(RESULT_MISS)]
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
-                                        = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
                },
                [C(OP_WRITE)] = {
                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_PC_BRANCH_PRED,
-                        [C(RESULT_MISS)]
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
-                                        = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
                },
                [C(OP_PREFETCH)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
diff --git a/arch/arm/kernel/perf_event_xscale.c b/arch/arm/kernel/perf_event_xscale.c
index e0cca10a8411..3b99d8269829 100644
--- a/arch/arm/kernel/perf_event_xscale.c
+++ b/arch/arm/kernel/perf_event_xscale.c
@@ -48,13 +48,15 @@ enum xscale_counters {
 };
 static const unsigned xscale_perf_map[PERF_COUNT_HW_MAX] = {
-        [PERF_COUNT_HW_CPU_CYCLES]          = XSCALE_PERFCTR_CCNT,
+        [PERF_COUNT_HW_CPU_CYCLES]              = XSCALE_PERFCTR_CCNT,
-        [PERF_COUNT_HW_INSTRUCTIONS]        = XSCALE_PERFCTR_INSTRUCTION,
+        [PERF_COUNT_HW_INSTRUCTIONS]            = XSCALE_PERFCTR_INSTRUCTION,
-        [PERF_COUNT_HW_CACHE_REFERENCES]    = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_CACHE_REFERENCES]        = HW_OP_UNSUPPORTED,
-        [PERF_COUNT_HW_CACHE_MISSES]        = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_CACHE_MISSES]            = HW_OP_UNSUPPORTED,
-        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = XSCALE_PERFCTR_BRANCH,
+        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]     = XSCALE_PERFCTR_BRANCH,
-        [PERF_COUNT_HW_BRANCH_MISSES]       = XSCALE_PERFCTR_BRANCH_MISS,
+        [PERF_COUNT_HW_BRANCH_MISSES]           = XSCALE_PERFCTR_BRANCH_MISS,
-        [PERF_COUNT_HW_BUS_CYCLES]          = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_BUS_CYCLES]              = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = XSCALE_PERFCTR_ICACHE_NO_DELIVER,
+        [PERF_COUNT_HW_STALLED_CYCLES_BACKEND]  = HW_OP_UNSUPPORTED,
 };
 static const unsigned xscale_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index 3d0c6fb74ae4..eeb3e16c6046 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -57,7 +57,7 @@ static const char *isa_modes[] = {
  "ARM" , "Thumb" , "Jazelle", "ThumbEE"
 };
-extern void setup_mm_for_reboot(char mode);
+extern void setup_mm_for_reboot(void);
 static volatile int hlt_counter;
@@ -92,7 +92,7 @@ static int __init hlt_setup(char *__unused)
 __setup("nohlt", nohlt_setup);
 __setup("hlt", hlt_setup);
-void arm_machine_restart(char mode, const char *cmd)
+void soft_restart(unsigned long addr)
 {
        /* Disable interrupts first */
        local_irq_disable();
@@ -103,7 +103,7 @@ void arm_machine_restart(char mode, const char *cmd)
         * we may need it to insert some 1:1 mappings so that
         * soft boot works.
         */
-        setup_mm_for_reboot(mode);
+        setup_mm_for_reboot();
        /* Clean and invalidate caches */
        flush_cache_all();
@@ -114,18 +114,17 @@ void arm_machine_restart(char mode, const char *cmd)
        /* Push out any further dirty data, and ensure cache is empty */
        flush_cache_all();
-        /*
+        cpu_reset(addr);
-         * Now call the architecture specific reboot code.
+}
-         */
-        arch_reset(mode, cmd);
-        /*
+void arm_machine_restart(char mode, const char *cmd)
-         * Whoops - the architecture was unable to reboot.
+{
-         * Tell the user!
+        /* Disable interrupts first */
-         */
+        local_irq_disable();
-        mdelay(1000);
+        local_fiq_disable();
-        printk("Reboot failed -- System halted\n");
-        while (1);
+        /* Call the architecture specific reboot code. */
+        arch_reset(mode, cmd);
 }
 /*
@@ -253,7 +252,15 @@ void machine_power_off(void)
 void machine_restart(char *cmd)
 {
        machine_shutdown();
        arm_pm_restart(reboot_mode, cmd);
+        /* Give a grace period for failure to restart of 1s */
+        mdelay(1000);
+        /* Whoops - the platform was unable to reboot. Tell the user! */
+        printk("Reboot failed -- System halted\n");
+        while (1);
 }
 void __show_regs(struct pt_regs *regs)
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 8fc2c8fcbdc6..095d6611c84e 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -31,6 +31,7 @@
 #include <linux/memblock.h>
 #include <linux/bug.h>
 #include <linux/compiler.h>
+#include <linux/sort.h>
 #include <asm/unified.h>
 #include <asm/cpu.h>
@@ -890,6 +891,12 @@ static struct machine_desc * __init setup_machine_tags(unsigned int nr)
        return mdesc;
 }
+static int __init meminfo_cmp(const void *_a, const void *_b)
+{
+        const struct membank *a = _a, *b = _b;
+        long cmp = bank_pfn_start(a) - bank_pfn_start(b);
+        return cmp < 0 ? -1 : cmp > 0 ? 1 : 0;
+}
 void __init setup_arch(char **cmdline_p)
 {
@@ -908,8 +915,8 @@ void __init setup_arch(char **cmdline_p)
                arm_dma_zone_size = mdesc->dma_zone_size;
        }
 #endif
-        if (mdesc->soft_reboot)
+        if (mdesc->restart_mode)
-                reboot_setup("s");
+                reboot_setup(&mdesc->restart_mode);
        init_mm.start_code = (unsigned long) _text;
        init_mm.end_code   = (unsigned long) _etext;
@@ -922,12 +929,16 @@ void __init setup_arch(char **cmdline_p)
        parse_early_param();
+        sort(&meminfo.bank, meminfo.nr_banks, sizeof(meminfo.bank[0]), meminfo_cmp, NULL);
        sanity_check_meminfo();
        arm_memblock_init(&meminfo, mdesc);
        paging_init(mdesc);
        request_standard_resources(mdesc);
+        if (mdesc->restart)
+                arm_pm_restart = mdesc->restart;
        unflatten_device_tree();
 #ifdef CONFIG_SMP
diff --git a/arch/arm/mach-at91/include/mach/io.h b/arch/arm/mach-at91/include/mach/io.h
index 4298e7806c76..4ca09ef7ca29 100644
--- a/arch/arm/mach-at91/include/mach/io.h
+++ b/arch/arm/mach-at91/include/mach/io.h
@@ -30,14 +30,6 @@
 #ifndef __ASSEMBLY__
-#ifndef CONFIG_ARCH_AT91X40
-#define __arch_ioremap  at91_ioremap
-#define __arch_iounmap  at91_iounmap
-#endif
-void __iomem *at91_ioremap(unsigned long phys, size_t size, unsigned int type);
-void at91_iounmap(volatile void __iomem *addr);
 static inline unsigned int at91_sys_read(unsigned int reg_offset)
 {
        void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS;
diff --git a/arch/arm/mach-at91/include/mach/vmalloc.h b/arch/arm/mach-at91/include/mach/vmalloc.h
deleted file mode 100644
index 8e4a1bd0ab1d..000000000000
--- a/arch/arm/mach-at91/include/mach/vmalloc.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * arch/arm/mach-at91/include/mach/vmalloc.h
- *
- *  Copyright (C) 2003 SAN People
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_VMALLOC_H
-#define __ASM_ARCH_VMALLOC_H
-#include <mach/hardware.h>
-#define VMALLOC_END             (AT91_VIRT_BASE & PGDIR_MASK)
-#endif
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index aa64294c7db3..cf98a8f94dc5 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -73,24 +73,6 @@ static struct map_desc at91_io_desc __initdata = {
        .type           = MT_DEVICE,
 };
-void __iomem *at91_ioremap(unsigned long p, size_t size, unsigned int type)
-{
-        if (p >= AT91_BASE_SYS && p <= (AT91_BASE_SYS + SZ_16K - 1))
-                return (void __iomem *)AT91_IO_P2V(p);
-        return __arm_ioremap_caller(p, size, type, __builtin_return_address(0));
-}
-EXPORT_SYMBOL(at91_ioremap);
-void at91_iounmap(volatile void __iomem *addr)
-{
-        unsigned long virt = (unsigned long)addr;
-        if (virt >= VMALLOC_START && virt < VMALLOC_END)
-                __iounmap(addr);
-}
-EXPORT_SYMBOL(at91_iounmap);
 #define AT91_DBGU0      0xfffff200
 #define AT91_DBGU1      0xffffee00
diff --git a/arch/arm/mach-bcmring/dma.c b/arch/arm/mach-bcmring/dma.c
index f4d4d6d174d0..1a1a27dd5654 100644
--- a/arch/arm/mach-bcmring/dma.c
+++ b/arch/arm/mach-bcmring/dma.c
@@ -1615,7 +1615,7 @@ DMA_MemType_t dma_mem_type(void *addr)
 {
        unsigned long addrVal = (unsigned long)addr;
-        if (addrVal >= VMALLOC_END) {
+        if (addrVal >= CONSISTENT_BASE) {
                /* NOTE: DMA virtual memory space starts at 0xFFxxxxxx */
                /* dma_alloc_xxx pages are physically and virtually contiguous */
diff --git a/arch/arm/mach-bcmring/include/mach/vmalloc.h b/arch/arm/mach-bcmring/include/mach/vmalloc.h
deleted file mode 100644
index 7397bd7817d9..000000000000
--- a/arch/arm/mach-bcmring/include/mach/vmalloc.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- *
- *  Copyright (C) 2000 Russell King.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-/*
- * Move VMALLOC_END to 0xf0000000 so that the vm space can range from
- * 0xe0000000 to 0xefffffff. This gives us 256 MB of vm space and handles
- * larger physical memory designs better.
- */
-#define VMALLOC_END       0xf0000000UL
diff --git a/arch/arm/mach-clps711x/Makefile b/arch/arm/mach-clps711x/Makefile
index 4a197315f0cf..f2f0256232e3 100644
--- a/arch/arm/mach-clps711x/Makefile
+++ b/arch/arm/mach-clps711x/Makefile
@@ -4,7 +4,7 @@
 # Object file lists.
-obj-y                   := irq.o mm.o time.o
+obj-y                   := common.o
 obj-m                   :=
 obj-n                   :=
 obj-                    :=
diff --git a/arch/arm/mach-clps711x/irq.c b/arch/arm/mach-clps711x/common.c
index c2eceee645e3..ced2a4e406f4 100644
--- a/arch/arm/mach-clps711x/irq.c
+++ b/arch/arm/mach-clps711x/common.c
@@ -1,7 +1,9 @@
 /*
- *  linux/arch/arm/mach-clps711x/irq.c
+ *  linux/arch/arm/mach-clps711x/core.c
 *
- *  Copyright (C) 2000 Deep Blue Solutions Ltd.
+ *  Core support for the CLPS711x-based machines.
+ *
+ *  Copyright (C) 2001,2011 Deep Blue Solutions Ltd
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
@@ -17,16 +19,42 @@
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
+#include <linux/kernel.h>
+#include <linux/mm.h>
 #include <linux/init.h>
-#include <linux/list.h>
+#include <linux/interrupt.h>
 #include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/sched.h>
+#include <linux/timex.h>
-#include <asm/mach/irq.h>
+#include <asm/sizes.h>
 #include <mach/hardware.h>
 #include <asm/irq.h>
+#include <asm/leds.h>
+#include <asm/pgtable.h>
+#include <asm/page.h>
+#include <asm/mach/map.h>
+#include <asm/mach/time.h>
 #include <asm/hardware/clps7111.h>
+/*
+ * This maps the generic CLPS711x registers
+ */
+static struct map_desc clps711x_io_desc[] __initdata = {
+        {
+                .virtual        = CLPS7111_VIRT_BASE,
+                .pfn            = __phys_to_pfn(CLPS7111_PHYS_BASE),
+                .length         = SZ_1M,
+                .type           = MT_DEVICE
+        }
+};
+void __init clps711x_map_io(void)
+{
+        iotable_init(clps711x_io_desc, ARRAY_SIZE(clps711x_io_desc));
+}
 static void int1_mask(struct irq_data *d)
 {
        u32 intmr1;
@@ -112,15 +140,15 @@ void __init clps711x_init_irq(void)
        for (i = 0; i < NR_IRQS; i++) {
                if (INT1_IRQS & (1 << i)) {
-                        irq_set_chip_and_handler(i, &int1_chip,
+                        irq_set_chip_and_handler(i, &int1_chip,
                                                 handle_level_irq);
-                        set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
+                        set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
                }
                if (INT2_IRQS & (1 << i)) {
                        irq_set_chip_and_handler(i, &int2_chip,
                                                 handle_level_irq);
                        set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
-                }                       
+                }
        }
        /*
@@ -141,3 +169,54 @@ void __init clps711x_init_irq(void)
        clps_writel(0, SYNCIO);
        clps_writel(0, KBDEOI);
 }
+/*
+ * gettimeoffset() returns time since last timer tick, in usecs.
+ *
+ * 'LATCH' is hwclock ticks (see CLOCK_TICK_RATE in timex.h) per jiffy.
+ * 'tick' is usecs per jiffy.
+ */
+static unsigned long clps711x_gettimeoffset(void)
+{
+        unsigned long hwticks;
+        hwticks = LATCH - (clps_readl(TC2D) & 0xffff);  /* since last underflow */
+        return (hwticks * (tick_nsec / 1000)) / LATCH;
+}
+/*
+ * IRQ handler for the timer
+ */
+static irqreturn_t p720t_timer_interrupt(int irq, void *dev_id)
+{
+        timer_tick();
+        return IRQ_HANDLED;
+}
+static struct irqaction clps711x_timer_irq = {
+        .name           = "CLPS711x Timer Tick",
+        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+        .handler        = p720t_timer_interrupt,
+};
+static void __init clps711x_timer_init(void)
+{
+        struct timespec tv;
+        unsigned int syscon;
+        syscon = clps_readl(SYSCON1);
+        syscon |= SYSCON1_TC2S | SYSCON1_TC2M;
+        clps_writel(syscon, SYSCON1);
+        clps_writel(LATCH-1, TC2D); /* 512kHz / 100Hz - 1 */
+        setup_irq(IRQ_TC2OI, &clps711x_timer_irq);
+        tv.tv_nsec = 0;
+        tv.tv_sec = clps_readl(RTCDR);
+        do_settimeofday(&tv);
+}
+struct sys_timer clps711x_timer = {
+        .init           = clps711x_timer_init,
+        .offset         = clps711x_gettimeoffset,
+};
diff --git a/arch/arm/mach-clps711x/include/mach/system.h b/arch/arm/mach-clps711x/include/mach/system.h
index f916cd7a477d..6c119937d398 100644
--- a/arch/arm/mach-clps711x/include/mach/system.h
+++ b/arch/arm/mach-clps711x/include/mach/system.h
@@ -34,7 +34,7 @@ static inline void arch_idle(void)
 static inline void arch_reset(char mode, const char *cmd)
 {
-        cpu_reset(0);
+        soft_restart(0);
 }
 #endif
diff --git a/arch/arm/mach-clps711x/include/mach/vmalloc.h b/arch/arm/mach-clps711x/include/mach/vmalloc.h
deleted file mode 100644
index 467b96137e47..000000000000
--- a/arch/arm/mach-clps711x/include/mach/vmalloc.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- *  arch/arm/mach-clps711x/include/mach/vmalloc.h
- *
- *  Copyright (C) 2000 Deep Blue Solutions Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#define VMALLOC_END       0xd0000000UL
diff --git a/arch/arm/mach-clps711x/mm.c b/arch/arm/mach-clps711x/mm.c
deleted file mode 100644
index 986592176767..000000000000
--- a/arch/arm/mach-clps711x/mm.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- *  linux/arch/arm/mach-clps711x/mm.c
- *
- *  Generic MM setup for the CLPS711x-based machines.
- *
- *  Copyright (C) 2001 Deep Blue Solutions Ltd
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/kernel.h>
-#include <linux/mm.h>
-#include <linux/init.h>
-#include <asm/sizes.h>
-#include <mach/hardware.h>
-#include <asm/pgtable.h>
-#include <asm/page.h>
-#include <asm/mach/map.h>
-#include <asm/hardware/clps7111.h>
-/*
- * This maps the generic CLPS711x registers
- */
-static struct map_desc clps711x_io_desc[] __initdata = {
-        {
-                .virtual        = CLPS7111_VIRT_BASE,
-                .pfn            = __phys_to_pfn(CLPS7111_PHYS_BASE),
-                .length         = SZ_1M,
-                .type           = MT_DEVICE
-        }
-};
-void __init clps711x_map_io(void)
-{
-        iotable_init(clps711x_io_desc, ARRAY_SIZE(clps711x_io_desc));
-}
diff --git a/arch/arm/mach-clps711x/time.c b/arch/arm/mach-clps711x/time.c
deleted file mode 100644
index d581ef0bcd24..000000000000
--- a/arch/arm/mach-clps711x/time.c
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- *  linux/arch/arm/mach-clps711x/time.c
- *
- *  Copyright (C) 2001 Deep Blue Solutions Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/timex.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/sched.h>
-#include <linux/io.h>
-#include <mach/hardware.h>
-#include <asm/irq.h>
-#include <asm/leds.h>
-#include <asm/hardware/clps7111.h>
-#include <asm/mach/time.h>
-/*
- * gettimeoffset() returns time since last timer tick, in usecs.
- *
- * 'LATCH' is hwclock ticks (see CLOCK_TICK_RATE in timex.h) per jiffy.
- * 'tick' is usecs per jiffy.
- */
-static unsigned long clps711x_gettimeoffset(void)
-{
-        unsigned long hwticks;
-        hwticks = LATCH - (clps_readl(TC2D) & 0xffff);  /* since last underflow */
-        return (hwticks * (tick_nsec / 1000)) / LATCH;
-}
-/*
- * IRQ handler for the timer
- */
-static irqreturn_t
-p720t_timer_interrupt(int irq, void *dev_id)
-{
-        timer_tick();
-        return IRQ_HANDLED;
-}
-static struct irqaction clps711x_timer_irq = {
-        .name           = "CLPS711x Timer Tick",
-        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
-        .handler        = p720t_timer_interrupt,
-};
-static void __init clps711x_timer_init(void)
-{
-        struct timespec tv;
-        unsigned int syscon;
-        syscon = clps_readl(SYSCON1);
-        syscon |= SYSCON1_TC2S | SYSCON1_TC2M;
-        clps_writel(syscon, SYSCON1);
-        clps_writel(LATCH-1, TC2D); /* 512kHz / 100Hz - 1 */
-        setup_irq(IRQ_TC2OI, &clps711x_timer_irq);
-        tv.tv_nsec = 0;
-        tv.tv_sec = clps_readl(RTCDR);
-        do_settimeofday(&tv);
-}
-struct sys_timer clps711x_timer = {
-        .init           = clps711x_timer_init,
-        .offset         = clps711x_gettimeoffset,
-};
diff --git a/arch/arm/mach-cns3xxx/cns3420vb.c b/arch/arm/mach-cns3xxx/cns3420vb.c
index 55f7b4b08ab9..594852fe24cc 100644
--- a/arch/arm/mach-cns3xxx/cns3420vb.c
+++ b/arch/arm/mach-cns3xxx/cns3420vb.c
@@ -26,6 +26,7 @@
 #include <linux/mtd/partitions.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
+#include <asm/hardware/gic.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
@@ -201,5 +202,6 @@ MACHINE_START(CNS3420VB, "Cavium Networks CNS3420 Validation Board")
        .map_io         = cns3420_map_io,
        .init_irq       = cns3xxx_init_irq,
        .timer          = &cns3xxx_timer,
+        .handle_irq     = gic_handle_irq,
        .init_machine   = cns3420_init,
 MACHINE_END
diff --git a/arch/arm/mach-cns3xxx/include/mach/entry-macro.S b/arch/arm/mach-cns3xxx/include/mach/entry-macro.S
index d87bfc397d39..01c57df5f716 100644
--- a/arch/arm/mach-cns3xxx/include/mach/entry-macro.S
+++ b/arch/arm/mach-cns3xxx/include/mach/entry-macro.S
@@ -8,8 +8,6 @@
 * published by the Free Software Foundation.
 */
-#include <asm/hardware/entry-macro-gic.S>
                .macro  disable_fiq
                .endm
diff --git a/arch/arm/mach-cns3xxx/include/mach/vmalloc.h b/arch/arm/mach-cns3xxx/include/mach/vmalloc.h
deleted file mode 100644
index 1dd231d2f772..000000000000
--- a/arch/arm/mach-cns3xxx/include/mach/vmalloc.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/*
- * Copyright 2000 Russell King.
- * Copyright 2003 ARM Limited
- * Copyright 2008 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- */
-#define VMALLOC_END             0xd8000000UL
diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile
index 495e31306fc0..2db78bd5c835 100644
--- a/arch/arm/mach-davinci/Makefile
+++ b/arch/arm/mach-davinci/Makefile
@@ -4,7 +4,7 @@
 #
 # Common objects
-obj-y                   := time.o clock.o serial.o io.o psc.o \
+obj-y                   := time.o clock.o serial.o psc.o \
                           dma.o usb.o common.o sram.o aemif.o
 obj-$(CONFIG_DAVINCI_MUX)               += mux.o
diff --git a/arch/arm/mach-davinci/include/mach/io.h b/arch/arm/mach-davinci/include/mach/io.h
index d1b954955c12..b2267d1e1a71 100644
--- a/arch/arm/mach-davinci/include/mach/io.h
+++ b/arch/arm/mach-davinci/include/mach/io.h
@@ -21,12 +21,4 @@
 #define __mem_pci(a)            (a)
 #define __mem_isa(a)            (a)
-#ifndef __ASSEMBLER__
-#define __arch_ioremap          davinci_ioremap
-#define __arch_iounmap          davinci_iounmap
-void __iomem *davinci_ioremap(unsigned long phys, size_t size,
-                              unsigned int type);
-void davinci_iounmap(volatile void __iomem *addr);
-#endif
 #endif /* __ASM_ARCH_IO_H */
diff --git a/arch/arm/mach-davinci/include/mach/vmalloc.h b/arch/arm/mach-davinci/include/mach/vmalloc.h
deleted file mode 100644
index d49646a8e206..000000000000
--- a/arch/arm/mach-davinci/include/mach/vmalloc.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * DaVinci vmalloc definitions
- *
- * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
- *
- * 2007 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#include <mach/hardware.h>
-/* Allow vmalloc range until the IO virtual range minus a 2M "hole" */
-#define VMALLOC_END       (IO_VIRT - (2<<20))
diff --git a/arch/arm/mach-davinci/io.c b/arch/arm/mach-davinci/io.c
deleted file mode 100644
index 8ea60a8b2495..000000000000
--- a/arch/arm/mach-davinci/io.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * DaVinci I/O mapping code
- *
- * Copyright (C) 2005-2006 Texas Instruments
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/module.h>
-#include <linux/io.h>
-#include <asm/tlb.h>
-#include <asm/mach/map.h>
-#include <mach/common.h>
-/*
- * Intercept ioremap() requests for addresses in our fixed mapping regions.
- */
-void __iomem *davinci_ioremap(unsigned long p, size_t size, unsigned int type)
-{
-        struct map_desc *desc = davinci_soc_info.io_desc;
-        int desc_num = davinci_soc_info.io_desc_num;
-        int i;
-        for (i = 0; i < desc_num; i++, desc++) {
-                unsigned long iophys = __pfn_to_phys(desc->pfn);
-                unsigned long iosize = desc->length;
-                if (p >= iophys && (p + size) <= (iophys + iosize))
-                        return __io(desc->virtual + p - iophys);
-        }
-        return __arm_ioremap_caller(p, size, type,
-                                        __builtin_return_address(0));
-}
-EXPORT_SYMBOL(davinci_ioremap);
-void davinci_iounmap(volatile void __iomem *addr)
-{
-        unsigned long virt = (unsigned long)addr;
-        if (virt >= VMALLOC_START && virt < VMALLOC_END)
-                __iounmap(addr);
-}
-EXPORT_SYMBOL(davinci_iounmap);
diff --git a/arch/arm/mach-dove/include/mach/dove.h b/arch/arm/mach-dove/include/mach/dove.h
index b20ec9af7882..ad1165d488c1 100644
--- a/arch/arm/mach-dove/include/mach/dove.h
+++ b/arch/arm/mach-dove/include/mach/dove.h
@@ -11,8 +11,6 @@
 #ifndef __ASM_ARCH_DOVE_H
 #define __ASM_ARCH_DOVE_H
-#include <mach/vmalloc.h>
 /*
 * Marvell Dove address maps.
 *
diff --git a/arch/arm/mach-dove/include/mach/vmalloc.h b/arch/arm/mach-dove/include/mach/vmalloc.h
deleted file mode 100644
index a28792cf761e..000000000000
--- a/arch/arm/mach-dove/include/mach/vmalloc.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/*
- * arch/arm/mach-dove/include/mach/vmalloc.h
- */
-#define VMALLOC_END     0xfd800000UL
diff --git a/arch/arm/mach-ebsa110/core.c b/arch/arm/mach-ebsa110/core.c
index d0ce8abdd4b6..ce3ed244c4b0 100644
--- a/arch/arm/mach-ebsa110/core.c
+++ b/arch/arm/mach-ebsa110/core.c
@@ -283,7 +283,7 @@ MACHINE_START(EBSA110, "EBSA110")
        .atag_offset    = 0x400,
        .reserve_lp0    = 1,
        .reserve_lp2    = 1,
-        .soft_reboot    = 1,
+        .restart_mode   = 's',
        .map_io         = ebsa110_map_io,
        .init_irq       = ebsa110_init_irq,
        .timer          = &ebsa110_timer,
diff --git a/arch/arm/mach-ebsa110/include/mach/system.h b/arch/arm/mach-ebsa110/include/mach/system.h
index 9a26245bf1fc..0d5df72a03f6 100644
--- a/arch/arm/mach-ebsa110/include/mach/system.h
+++ b/arch/arm/mach-ebsa110/include/mach/system.h
@@ -34,6 +34,6 @@ static inline void arch_idle(void)
        asm volatile ("mcr p15, 0, ip, c15, c1, 2" : : : "cc");
 }
-#define arch_reset(mode, cmd)   cpu_reset(0x80000000)
+#define arch_reset(mode, cmd)   soft_restart(0x80000000)
 #endif
diff --git a/arch/arm/mach-ebsa110/include/mach/vmalloc.h b/arch/arm/mach-ebsa110/include/mach/vmalloc.h
deleted file mode 100644
index ea141b7a3e03..000000000000
--- a/arch/arm/mach-ebsa110/include/mach/vmalloc.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/*
- *  arch/arm/mach-ebsa110/include/mach/vmalloc.h
- *
- *  Copyright (C) 1998 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#define VMALLOC_END       0xdf000000UL
diff --git a/arch/arm/mach-ep93xx/adssphere.c b/arch/arm/mach-ep93xx/adssphere.c
index 0713448206a5..d9b0ea2ba4d8 100644
--- a/arch/arm/mach-ep93xx/adssphere.c
+++ b/arch/arm/mach-ep93xx/adssphere.c
@@ -16,6 +16,7 @@
 #include <mach/hardware.h>
+#include <asm/hardware/vic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -36,6 +37,7 @@ MACHINE_START(ADSSPHERE, "ADS Sphere board")
        .atag_offset    = 0x100,
        .map_io         = ep93xx_map_io,
        .init_irq       = ep93xx_init_irq,
+        .handle_irq     = vic_handle_irq,
        .timer          = &ep93xx_timer,
        .init_machine   = adssphere_init_machine,
 MACHINE_END
diff --git a/arch/arm/mach-ep93xx/edb93xx.c b/arch/arm/mach-ep93xx/edb93xx.c
index 70ef8c527d27..9bbae0835f27 100644
--- a/arch/arm/mach-ep93xx/edb93xx.c
+++ b/arch/arm/mach-ep93xx/edb93xx.c
@@ -39,6 +39,7 @@
 #include <mach/ep93xx_spi.h>
 #include <mach/gpio-ep93xx.h>
+#include <asm/hardware/vic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -250,6 +251,7 @@ MACHINE_START(EDB9301, "Cirrus Logic EDB9301 Evaluation Board")
        .atag_offset    = 0x100,
        .map_io         = ep93xx_map_io,
        .init_irq       = ep93xx_init_irq,
+        .handle_irq     = vic_handle_irq,
        .timer          = &ep93xx_timer,
        .init_machine   = edb93xx_init_machine,
 MACHINE_END
@@ -261,6 +263,7 @@ MACHINE_START(EDB9302, "Cirrus Logic EDB9302 Evaluation Board")
        .atag_offset    = 0x100,
        .map_io         = ep93xx_map_io,
        .init_irq       = ep93xx_init_irq,
+        .handle_irq     = vic_handle_irq,
        .timer          = &ep93xx_timer,
        .init_machine   = edb93xx_init_machine,
 MACHINE_END
@@ -272,6 +275,7 @@ MACHINE_START(EDB9302A, "Cirrus Logic EDB9302A Evaluation Board")
        .atag_offset    = 0x100,
        .map_io         = ep93xx_map_io,
        .init_irq       = ep93xx_init_irq,
+        .handle_irq     = vic_handle_irq,
        .timer          = &ep93xx_timer,
        .init_machine   = edb93xx_init_machine,
 MACHINE_END
@@ -283,6 +287,7 @@ MACHINE_START(EDB9307, "Cirrus Logic EDB9307 Evaluation Board")
        .atag_offset    = 0x100,
        .map_io         = ep93xx_map_io,
        .init_irq       = ep93xx_init_irq,
+        .handle_irq     = vic_handle_irq,
        .timer          = &ep93xx_timer,
        .init_machine   = edb93xx_init_machine,
 MACHINE_END
@@ -294,6 +299,7 @@ MACHINE_START(EDB9307A, "Cirrus Logic EDB9307A Evaluation Board")
        .atag_offset    = 0x100,
        .map_io         = ep93xx_map_io,
        .init_irq       = ep93xx_init_irq,
+        .handle_irq     = vic_handle_irq,
        .timer          = &ep93xx_timer,
        .init_machine   = edb93xx_init_machine,
 MACHINE_END
@@ -305,6 +311,7 @@ MACHINE_START(EDB9312, "Cirrus Logic EDB9312 Evaluation Board")
        .atag_offset    = 0x100,
        .map_io         = ep93xx_map_io,
        .init_irq       = ep93xx_init_irq,
+        .handle_irq     = vic_handle_irq,
        .timer          = &ep93xx_timer,
        .init_machine   = edb93xx_init_machine,
 MACHINE_END
@@ -316,6 +323,7 @@ MACHINE_START(EDB9315, "Cirrus Logic EDB9315 Evaluation Board")
        .atag_offset    = 0x100,
        .map_io         = ep93xx_map_io,
        .init_irq       = ep93xx_init_irq,
+        .handle_irq     = vic_handle_irq,
        .timer          = &ep93xx_timer,
        .init_machine   = edb93xx_init_machine,
 MACHINE_END
@@ -327,6 +335,7 @@ MACHINE_START(EDB9315A, "Cirrus Logic EDB9315A Evaluation Board")
        .atag_offset    = 0x100,
        .map_io         = ep93xx_map_io,
        .init_irq       = ep93xx_init_irq,
+        .handle_irq     = vic_handle_irq,
        .timer          = &ep93xx_timer,
        .init_machine   = edb93xx_init_machine,
 MACHINE_END
diff --git a/arch/arm/mach-ep93xx/gesbc9312.c b/arch/arm/mach-ep93xx/gesbc9312.c
index 45ee205856f8..1dd32a7c5f15 100644
--- a/arch/arm/mach-ep93xx/gesbc9312.c
+++ b/arch/arm/mach-ep93xx/gesbc9312.c
@@ -16,6 +16,7 @@
 #include <mach/hardware.h>
+#include <asm/hardware/vic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -36,6 +37,7 @@ MACHINE_START(GESBC9312, "Glomation GESBC-9312-sx")
        .atag_offset    = 0x100,
        .map_io         = ep93xx_map_io,
        .init_irq       = ep93xx_init_irq,
+        .handle_irq     = vic_handle_irq,
        .timer          = &ep93xx_timer,
        .init_machine   = gesbc9312_init_machine,
 MACHINE_END
diff --git a/arch/arm/mach-ep93xx/include/mach/entry-macro.S b/arch/arm/mach-ep93xx/include/mach/entry-macro.S
index 96b85e2c2c0b..9be6edcf9045 100644
--- a/arch/arm/mach-ep93xx/include/mach/entry-macro.S
+++ b/arch/arm/mach-ep93xx/include/mach/entry-macro.S
@@ -9,51 +9,9 @@
 * the Free Software Foundation; either version 2 of the License, or (at
 * your option) any later version.
 */
-#include <mach/ep93xx-regs.h>
                .macro  disable_fiq
                .endm
-                .macro  get_irqnr_preamble, base, tmp
-                .endm
                .macro  arch_ret_to_user, tmp1, tmp2
                .endm
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-                ldr     \base, =(EP93XX_AHB_VIRT_BASE)
-                orr     \base, \base, #0x000b0000
-                mov     \irqnr, #0
-                ldr     \irqstat, [\base]               @ lower 32 interrupts
-                cmp     \irqstat, #0
-                bne     1001f
-                eor     \base, \base, #0x00070000
-                ldr     \irqstat, [\base]               @ upper 32 interrupts
-                cmp     \irqstat, #0
-                beq     1002f
-                mov     \irqnr, #0x20
-1001:
-                movs    \tmp, \irqstat, lsl #16
-                movne   \irqstat, \tmp
-                addeq   \irqnr, \irqnr, #16
-                movs    \tmp, \irqstat, lsl #8
-                movne   \irqstat, \tmp
-                addeq   \irqnr, \irqnr, #8
-                movs    \tmp, \irqstat, lsl #4
-                movne   \irqstat, \tmp
-                addeq   \irqnr, \irqnr, #4
-                movs    \tmp, \irqstat, lsl #2
-                movne   \irqstat, \tmp
-                addeq   \irqnr, \irqnr, #2
-                movs    \tmp, \irqstat, lsl #1
-                addeq   \irqnr, \irqnr, #1
-                orrs    \base, \base, #1
-1002:
-                .endm
diff --git a/arch/arm/mach-ep93xx/include/mach/system.h b/arch/arm/mach-ep93xx/include/mach/system.h
index 6d661fe9d66c..bdf6c4f1feef 100644
--- a/arch/arm/mach-ep93xx/include/mach/system.h
+++ b/arch/arm/mach-ep93xx/include/mach/system.h
@@ -11,8 +11,6 @@ static inline void arch_idle(void)
 static inline void arch_reset(char mode, const char *cmd)
 {
-        local_irq_disable();
        /*
         * Set then clear the SWRST bit to initiate a software reset
         */
diff --git a/arch/arm/mach-ep93xx/include/mach/vmalloc.h b/arch/arm/mach-ep93xx/include/mach/vmalloc.h
deleted file mode 100644
index 1b3f25d03d39..000000000000
--- a/arch/arm/mach-ep93xx/include/mach/vmalloc.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/*
- * arch/arm/mach-ep93xx/include/mach/vmalloc.h
- */
-#define VMALLOC_END     0xfe800000UL
diff --git a/arch/arm/mach-ep93xx/micro9.c b/arch/arm/mach-ep93xx/micro9.c
index e72f7368876e..a6dae6c2e3c1 100644
--- a/arch/arm/mach-ep93xx/micro9.c
+++ b/arch/arm/mach-ep93xx/micro9.c
@@ -18,6 +18,7 @@
 #include <mach/hardware.h>
+#include <asm/hardware/vic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -80,6 +81,7 @@ MACHINE_START(MICRO9, "Contec Micro9-High")
        .atag_offset    = 0x100,
        .map_io         = ep93xx_map_io,
        .init_irq       = ep93xx_init_irq,
+        .handle_irq     = vic_handle_irq,
        .timer          = &ep93xx_timer,
        .init_machine   = micro9_init_machine,
 MACHINE_END
@@ -91,6 +93,7 @@ MACHINE_START(MICRO9M, "Contec Micro9-Mid")
        .atag_offset    = 0x100,
        .map_io         = ep93xx_map_io,
        .init_irq       = ep93xx_init_irq,
+        .handle_irq     = vic_handle_irq,
        .timer          = &ep93xx_timer,
        .init_machine   = micro9_init_machine,
 MACHINE_END
@@ -102,6 +105,7 @@ MACHINE_START(MICRO9L, "Contec Micro9-Lite")
        .atag_offset    = 0x100,
        .map_io         = ep93xx_map_io,
        .init_irq       = ep93xx_init_irq,
+        .handle_irq     = vic_handle_irq,
        .timer          = &ep93xx_timer,
        .init_machine   = micro9_init_machine,
 MACHINE_END
@@ -113,6 +117,7 @@ MACHINE_START(MICRO9S, "Contec Micro9-Slim")
        .atag_offset    = 0x100,
        .map_io         = ep93xx_map_io,
        .init_irq       = ep93xx_init_irq,
+        .handle_irq     = vic_handle_irq,
        .timer          = &ep93xx_timer,
        .init_machine   = micro9_init_machine,
 MACHINE_END
diff --git a/arch/arm/mach-ep93xx/simone.c b/arch/arm/mach-ep93xx/simone.c
index 52e090dc9d27..40121ba8e711 100644
--- a/arch/arm/mach-ep93xx/simone.c
+++ b/arch/arm/mach-ep93xx/simone.c
@@ -25,6 +25,7 @@
 #include <mach/fb.h>
 #include <mach/gpio-ep93xx.h>
+#include <asm/hardware/vic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -80,6 +81,7 @@ MACHINE_START(SIM_ONE, "Simplemachines Sim.One Board")
        .atag_offset    = 0x100,
        .map_io         = ep93xx_map_io,
        .init_irq       = ep93xx_init_irq,
+        .handle_irq     = vic_handle_irq,
        .timer          = &ep93xx_timer,
        .init_machine   = simone_init_machine,
 MACHINE_END
diff --git a/arch/arm/mach-ep93xx/snappercl15.c b/arch/arm/mach-ep93xx/snappercl15.c
index 8121e3aedc0a..ec7c63ff01e2 100644
--- a/arch/arm/mach-ep93xx/snappercl15.c
+++ b/arch/arm/mach-ep93xx/snappercl15.c
@@ -31,6 +31,7 @@
 #include <mach/fb.h>
 #include <mach/gpio-ep93xx.h>
+#include <asm/hardware/vic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -177,6 +178,7 @@ MACHINE_START(SNAPPER_CL15, "Bluewater Systems Snapper CL15")
        .atag_offset    = 0x100,
        .map_io         = ep93xx_map_io,
        .init_irq       = ep93xx_init_irq,
+        .handle_irq     = vic_handle_irq,
        .timer          = &ep93xx_timer,
        .init_machine   = snappercl15_init_machine,
 MACHINE_END
diff --git a/arch/arm/mach-ep93xx/ts72xx.c b/arch/arm/mach-ep93xx/ts72xx.c
index 8b2f1435bcac..760384e6407d 100644
--- a/arch/arm/mach-ep93xx/ts72xx.c
+++ b/arch/arm/mach-ep93xx/ts72xx.c
@@ -23,6 +23,7 @@
 #include <mach/hardware.h>
 #include <mach/ts72xx.h>
+#include <asm/hardware/vic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/map.h>
 #include <asm/mach/arch.h>
@@ -247,6 +248,7 @@ MACHINE_START(TS72XX, "Technologic Systems TS-72xx SBC")
        .atag_offset    = 0x100,
        .map_io         = ts72xx_map_io,
        .init_irq       = ep93xx_init_irq,
+        .handle_irq     = vic_handle_irq,
        .timer          = &ep93xx_timer,
        .init_machine   = ts72xx_init_machine,
 MACHINE_END
diff --git a/arch/arm/mach-exynos/cpu.c b/arch/arm/mach-exynos/cpu.c
index 90ec247f3b37..22316cb31a8c 100644
--- a/arch/arm/mach-exynos/cpu.c
+++ b/arch/arm/mach-exynos/cpu.c
@@ -15,6 +15,7 @@
 #include <asm/mach/irq.h>
 #include <asm/proc-fns.h>
+#include <asm/exception.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/hardware/gic.h>
@@ -33,8 +34,6 @@
 #include <mach/regs-irq.h>
 #include <mach/regs-pmu.h>
-unsigned int gic_bank_offset __read_mostly;
 extern int combiner_init(unsigned int combiner_nr, void __iomem *base,
                         unsigned int irq_start);
 extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq);
@@ -207,27 +206,14 @@ void __init exynos4_init_clocks(int xtal)
        exynos4_setup_clocks();
 }
-static void exynos4_gic_irq_fix_base(struct irq_data *d)
-{
-        struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
-        gic_data->cpu_base = S5P_VA_GIC_CPU +
-                            (gic_bank_offset * smp_processor_id());
-        gic_data->dist_base = S5P_VA_GIC_DIST +
-                            (gic_bank_offset * smp_processor_id());
-}
 void __init exynos4_init_irq(void)
 {
        int irq;
+        unsigned int gic_bank_offset;
        gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
-        gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
+        gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset);
-        gic_arch_extn.irq_eoi = exynos4_gic_irq_fix_base;
-        gic_arch_extn.irq_unmask = exynos4_gic_irq_fix_base;
-        gic_arch_extn.irq_mask = exynos4_gic_irq_fix_base;
        for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
diff --git a/arch/arm/mach-exynos/include/mach/entry-macro.S b/arch/arm/mach-exynos/include/mach/entry-macro.S
index f5e9fd8e37b4..3ba4f547534b 100644
--- a/arch/arm/mach-exynos/include/mach/entry-macro.S
+++ b/arch/arm/mach-exynos/include/mach/entry-macro.S
@@ -9,83 +9,8 @@
 * warranty of any kind, whether express or implied.
 */
-#include <mach/hardware.h>
-#include <mach/map.h>
-#include <asm/hardware/gic.h>
                .macro  disable_fiq
                .endm
-                .macro  get_irqnr_preamble, base, tmp
-                mov     \tmp, #0
-                mrc     p15, 0, \base, c0, c0, 5
-                and     \base, \base, #3
-                cmp     \base, #0
-                beq     1f
-                ldr     \tmp, =gic_bank_offset
-                ldr     \tmp, [\tmp]
-                cmp     \base, #1
-                beq     1f
-                cmp     \base, #2
-                addeq   \tmp, \tmp, \tmp
-                addne   \tmp, \tmp, \tmp, LSL #1
-1:              ldr     \base, =gic_cpu_base_addr
-                ldr     \base, [\base]
-                add     \base, \base, \tmp
-                .endm
                .macro  arch_ret_to_user, tmp1, tmp2
                .endm
-                /*
-                 * The interrupt numbering scheme is defined in the
-                 * interrupt controller spec.  To wit:
-                 *
-                 * Interrupts 0-15 are IPI
-                 * 16-28 are reserved
-                 * 29-31 are local.  We allow 30 to be used for the watchdog.
-                 * 32-1020 are global
-                 * 1021-1022 are reserved
-                 * 1023 is "spurious" (no interrupt)
-                 *
-                 * For now, we ignore all local interrupts so only return an interrupt if it's
-                 * between 30 and 1020.  The test_for_ipi routine below will pick up on IPIs.
-                 *
-                 * A simple read from the controller will tell us the number of the highest
-                 * priority enabled interrupt.  We then just need to check whether it is in the
-                 * valid range for an IRQ (30-1020 inclusive).
-                 */
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-                ldr     \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */
-                ldr     \tmp, =1021
-                bic     \irqnr, \irqstat, #0x1c00
-                cmp     \irqnr, #15
-                cmpcc   \irqnr, \irqnr
-                cmpne   \irqnr, \tmp
-                cmpcs   \irqnr, \irqnr
-                addne   \irqnr, \irqnr, #32
-                .endm
-                /* We assume that irqstat (the raw value of the IRQ acknowledge
-                 * register) is preserved from the macro above.
-                 * If there is an IPI, we immediately signal end of interrupt on the
-                 * controller, since this requires the original irqstat value which
-                 * we won't easily be able to recreate later.
-                 */
-                .macro test_for_ipi, irqnr, irqstat, base, tmp
-                bic     \irqnr, \irqstat, #0x1c00
-                cmp     \irqnr, #16
-                strcc   \irqstat, [\base, #GIC_CPU_EOI]
-                cmpcs   \irqnr, \irqnr
-                .endm
diff --git a/arch/arm/mach-exynos/include/mach/vmalloc.h b/arch/arm/mach-exynos/include/mach/vmalloc.h
deleted file mode 100644
index 284330e571d2..000000000000
--- a/arch/arm/mach-exynos/include/mach/vmalloc.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* linux/arch/arm/mach-exynos4/include/mach/vmalloc.h
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * Copyright 2010 Ben Dooks <ben-linux@fluff.org>
- *
- * Based on arch/arm/mach-s5p6440/include/mach/vmalloc.h
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * EXYNOS4 vmalloc definition
-*/
-#ifndef __ASM_ARCH_VMALLOC_H
-#define __ASM_ARCH_VMALLOC_H __FILE__
-#define VMALLOC_END     0xF6000000UL
-#endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/mach-exynos/mach-armlex4210.c b/arch/arm/mach-exynos/mach-armlex4210.c
index f0ca6c157d29..49da3089249a 100644
--- a/arch/arm/mach-exynos/mach-armlex4210.c
+++ b/arch/arm/mach-exynos/mach-armlex4210.c
@@ -16,6 +16,7 @@
 #include <linux/smsc911x.h>
 #include <asm/mach/arch.h>
+#include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 #include <plat/cpu.h>
@@ -210,6 +211,7 @@ MACHINE_START(ARMLEX4210, "ARMLEX4210")
        .atag_offset    = 0x100,
        .init_irq       = exynos4_init_irq,
        .map_io         = armlex4210_map_io,
+        .handle_irq     = gic_handle_irq,
        .init_machine   = armlex4210_machine_init,
        .timer          = &exynos4_timer,
 MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c
index 236bbe187163..5acec11821a4 100644
--- a/arch/arm/mach-exynos/mach-nuri.c
+++ b/arch/arm/mach-exynos/mach-nuri.c
@@ -32,6 +32,7 @@
 #include <media/v4l2-mediabus.h>
 #include <asm/mach/arch.h>
+#include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 #include <plat/adc.h>
@@ -1333,6 +1334,7 @@ MACHINE_START(NURI, "NURI")
        .atag_offset    = 0x100,
        .init_irq       = exynos4_init_irq,
        .map_io         = nuri_map_io,
+        .handle_irq     = gic_handle_irq,
        .init_machine   = nuri_machine_init,
        .timer          = &exynos4_timer,
        .reserve        = &nuri_reserve,
diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c
index f80b563f2be7..5561b06c38ec 100644
--- a/arch/arm/mach-exynos/mach-origen.c
+++ b/arch/arm/mach-exynos/mach-origen.c
@@ -22,6 +22,7 @@
 #include <linux/lcd.h>
 #include <asm/mach/arch.h>
+#include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 #include <video/platform_lcd.h>
@@ -694,6 +695,7 @@ MACHINE_START(ORIGEN, "ORIGEN")
        .atag_offset    = 0x100,
        .init_irq       = exynos4_init_irq,
        .map_io         = origen_map_io,
+        .handle_irq     = gic_handle_irq,
        .init_machine   = origen_machine_init,
        .timer          = &exynos4_timer,
        .reserve        = &origen_reserve,
diff --git a/arch/arm/mach-exynos/mach-smdk4x12.c b/arch/arm/mach-exynos/mach-smdk4x12.c
index fcf2e0e23d53..722d82d7f217 100644
--- a/arch/arm/mach-exynos/mach-smdk4x12.c
+++ b/arch/arm/mach-exynos/mach-smdk4x12.c
@@ -21,6 +21,7 @@
 #include <linux/serial_core.h>
 #include <asm/mach/arch.h>
+#include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 #include <plat/backlight.h>
@@ -287,6 +288,7 @@ MACHINE_START(SMDK4212, "SMDK4212")
        .atag_offset    = 0x100,
        .init_irq       = exynos4_init_irq,
        .map_io         = smdk4x12_map_io,
+        .handle_irq     = gic_handle_irq,
        .init_machine   = smdk4x12_machine_init,
        .timer          = &exynos4_timer,
 MACHINE_END
@@ -297,6 +299,7 @@ MACHINE_START(SMDK4412, "SMDK4412")
        .atag_offset    = 0x100,
        .init_irq       = exynos4_init_irq,
        .map_io         = smdk4x12_map_io,
+        .handle_irq     = gic_handle_irq,
        .init_machine   = smdk4x12_machine_init,
        .timer          = &exynos4_timer,
 MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-smdkv310.c b/arch/arm/mach-exynos/mach-smdkv310.c
index cec2afabe7b4..edc60b6108ed 100644
--- a/arch/arm/mach-exynos/mach-smdkv310.c
+++ b/arch/arm/mach-exynos/mach-smdkv310.c
@@ -21,6 +21,7 @@
 #include <linux/pwm_backlight.h>
 #include <asm/mach/arch.h>
+#include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 #include <video/platform_lcd.h>
@@ -375,6 +376,7 @@ MACHINE_START(SMDKV310, "SMDKV310")
        .atag_offset    = 0x100,
        .init_irq       = exynos4_init_irq,
        .map_io         = smdkv310_map_io,
+        .handle_irq     = gic_handle_irq,
        .init_machine   = smdkv310_machine_init,
        .timer          = &exynos4_timer,
        .reserve        = &smdkv310_reserve,
@@ -385,6 +387,7 @@ MACHINE_START(SMDKC210, "SMDKC210")
        .atag_offset    = 0x100,
        .init_irq       = exynos4_init_irq,
        .map_io         = smdkv310_map_io,
+        .handle_irq     = gic_handle_irq,
        .init_machine   = smdkv310_machine_init,
        .timer          = &exynos4_timer,
 MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c
index a2a177ff4b44..cfc7d5076f5a 100644
--- a/arch/arm/mach-exynos/mach-universal_c210.c
+++ b/arch/arm/mach-exynos/mach-universal_c210.c
@@ -24,6 +24,7 @@
 #include <linux/i2c/atmel_mxt_ts.h>
 #include <asm/mach/arch.h>
+#include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 #include <plat/regs-serial.h>
@@ -1058,6 +1059,7 @@ MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
        .atag_offset    = 0x100,
        .init_irq       = exynos4_init_irq,
        .map_io         = universal_map_io,
+        .handle_irq     = gic_handle_irq,
        .init_machine   = universal_machine_init,
        .timer          = &exynos4_timer,
        .reserve        = &universal_reserve,
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 69ffb2fb3875..60bc45e3e709 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -32,7 +32,6 @@
 #include <plat/cpu.h>
-extern unsigned int gic_bank_offset;
 extern void exynos4_secondary_startup(void);
 #define CPU1_BOOT_REG           (samsung_rev() == EXYNOS4210_REV_1_1 ? \
@@ -65,31 +64,6 @@ static void __iomem *scu_base_addr(void)
 static DEFINE_SPINLOCK(boot_lock);
-static void __cpuinit exynos4_gic_secondary_init(void)
-{
-        void __iomem *dist_base = S5P_VA_GIC_DIST +
-                                (gic_bank_offset * smp_processor_id());
-        void __iomem *cpu_base = S5P_VA_GIC_CPU +
-                                (gic_bank_offset * smp_processor_id());
-        int i;
-        /*
-         * Deal with the banked PPI and SGI interrupts - disable all
-         * PPI interrupts, ensure all SGI interrupts are enabled.
-         */
-        __raw_writel(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR);
-        __raw_writel(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET);
-        /*
-         * Set priority on PPI and SGI interrupts
-         */
-        for (i = 0; i < 32; i += 4)
-                __raw_writel(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4);
-        __raw_writel(0xf0, cpu_base + GIC_CPU_PRIMASK);
-        __raw_writel(1, cpu_base + GIC_CPU_CTRL);
-}
 void __cpuinit platform_secondary_init(unsigned int cpu)
 {
        /*
@@ -97,7 +71,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
         * core (e.g. timer irq), then they will not have been enabled
         * for us: do so
         */
-        exynos4_gic_secondary_init();
+        gic_secondary_init(0);
        /*
         * let the primary processor know we're out of the
diff --git a/arch/arm/mach-footbridge/cats-hw.c b/arch/arm/mach-footbridge/cats-hw.c
index d5f178540928..60b6774e1eaa 100644
--- a/arch/arm/mach-footbridge/cats-hw.c
+++ b/arch/arm/mach-footbridge/cats-hw.c
@@ -86,7 +86,7 @@ fixup_cats(struct tag *tags, char **cmdline, struct meminfo *mi)
 MACHINE_START(CATS, "Chalice-CATS")
        /* Maintainer: Philip Blundell */
        .atag_offset    = 0x100,
-        .soft_reboot    = 1,
+        .restart_mode   = 's',
        .fixup          = fixup_cats,
        .map_io         = footbridge_map_io,
        .init_irq       = footbridge_init_irq,
diff --git a/arch/arm/mach-footbridge/include/mach/system.h b/arch/arm/mach-footbridge/include/mach/system.h
index 0b2931566209..249f895910fb 100644
--- a/arch/arm/mach-footbridge/include/mach/system.h
+++ b/arch/arm/mach-footbridge/include/mach/system.h
@@ -24,7 +24,7 @@ static inline void arch_reset(char mode, const char *cmd)
                /*
                 * Jump into the ROM
                 */
-                cpu_reset(0x41000000);
+                soft_restart(0x41000000);
        } else {
                if (machine_is_netwinder()) {
                        /* open up the SuperIO chip
diff --git a/arch/arm/mach-footbridge/include/mach/vmalloc.h b/arch/arm/mach-footbridge/include/mach/vmalloc.h
deleted file mode 100644
index 40ba78e5782b..000000000000
--- a/arch/arm/mach-footbridge/include/mach/vmalloc.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/*
- *  arch/arm/mach-footbridge/include/mach/vmalloc.h
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#define VMALLOC_END       0xf0000000UL
diff --git a/arch/arm/mach-gemini/include/mach/vmalloc.h b/arch/arm/mach-gemini/include/mach/vmalloc.h
deleted file mode 100644
index 45371eb86fcb..000000000000
--- a/arch/arm/mach-gemini/include/mach/vmalloc.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/*
- *  Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-#define VMALLOC_END     0xf0000000UL
diff --git a/arch/arm/mach-h720x/include/mach/vmalloc.h b/arch/arm/mach-h720x/include/mach/vmalloc.h
deleted file mode 100644
index 8520b4a4d4e6..000000000000
--- a/arch/arm/mach-h720x/include/mach/vmalloc.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/*
- * arch/arm/mach-h720x/include/mach/vmalloc.h
- */
-#ifndef __ARCH_ARM_VMALLOC_H
-#define __ARCH_ARM_VMALLOC_H
-#define VMALLOC_END       0xd0000000UL
-#endif
diff --git a/arch/arm/mach-highbank/highbank.c b/arch/arm/mach-highbank/highbank.c
index 88660d500f5b..7266dd510f1a 100644
--- a/arch/arm/mach-highbank/highbank.c
+++ b/arch/arm/mach-highbank/highbank.c
@@ -144,6 +144,7 @@ DT_MACHINE_START(HIGHBANK, "Highbank")
        .map_io         = highbank_map_io,
        .init_irq       = highbank_init_irq,
        .timer          = &highbank_timer,
+        .handle_irq     = gic_handle_irq,
        .init_machine   = highbank_init,
        .dt_compat      = highbank_match,
 MACHINE_END
diff --git a/arch/arm/mach-highbank/include/mach/entry-macro.S b/arch/arm/mach-highbank/include/mach/entry-macro.S
index 73c11297509e..a14f9e62ca92 100644
--- a/arch/arm/mach-highbank/include/mach/entry-macro.S
+++ b/arch/arm/mach-highbank/include/mach/entry-macro.S
@@ -1,5 +1,3 @@
-#include <asm/hardware/entry-macro-gic.S>
        .macro  disable_fiq
        .endm
diff --git a/arch/arm/mach-highbank/include/mach/vmalloc.h b/arch/arm/mach-highbank/include/mach/vmalloc.h
deleted file mode 100644
index 1969e954277a..000000000000
--- a/arch/arm/mach-highbank/include/mach/vmalloc.h
+++ /dev/null
@@ -1 +0,0 @@
-#define VMALLOC_END             0xFEE00000UL
diff --git a/arch/arm/mach-integrator/include/mach/vmalloc.h b/arch/arm/mach-integrator/include/mach/vmalloc.h
deleted file mode 100644
index 2f5a2bafb11f..000000000000
--- a/arch/arm/mach-integrator/include/mach/vmalloc.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- *  arch/arm/mach-integrator/include/mach/vmalloc.h
- *
- *  Copyright (C) 2000 Russell King.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#define VMALLOC_END       0xd0000000UL
diff --git a/arch/arm/mach-iop13xx/include/mach/vmalloc.h b/arch/arm/mach-iop13xx/include/mach/vmalloc.h
deleted file mode 100644
index c53456740345..000000000000
--- a/arch/arm/mach-iop13xx/include/mach/vmalloc.h
+++ /dev/null
@@ -1,4 +0,0 @@
-#ifndef _VMALLOC_H_
-#define _VMALLOC_H_
-#define VMALLOC_END     0xfa000000UL
-#endif
diff --git a/arch/arm/mach-iop32x/include/mach/io.h b/arch/arm/mach-iop32x/include/mach/io.h
index 059c783ce0b2..2d88264b9863 100644
--- a/arch/arm/mach-iop32x/include/mach/io.h
+++ b/arch/arm/mach-iop32x/include/mach/io.h
@@ -13,15 +13,8 @@
 #include <asm/hardware/iop3xx.h>
-extern void __iomem *__iop3xx_ioremap(unsigned long cookie, size_t size,
-        unsigned int mtype);
-extern void __iop3xx_iounmap(void __iomem *addr);
 #define IO_SPACE_LIMIT          0xffffffff
 #define __io(p)         ((void __iomem *)IOP3XX_PCI_IO_PHYS_TO_VIRT(p))
 #define __mem_pci(a)            (a)
-#define __arch_ioremap  __iop3xx_ioremap
-#define __arch_iounmap  __iop3xx_iounmap
 #endif
diff --git a/arch/arm/mach-iop32x/include/mach/system.h b/arch/arm/mach-iop32x/include/mach/system.h
index a4b808fe0d81..b4f83e5973b2 100644
--- a/arch/arm/mach-iop32x/include/mach/system.h
+++ b/arch/arm/mach-iop32x/include/mach/system.h
@@ -18,8 +18,6 @@ static inline void arch_idle(void)
 static inline void arch_reset(char mode, const char *cmd)
 {
-        local_irq_disable();
        if (machine_is_n2100()) {
                gpio_line_set(N2100_HARDWARE_RESET, GPIO_LOW);
                gpio_line_config(N2100_HARDWARE_RESET, GPIO_OUT);
@@ -30,5 +28,5 @@ static inline void arch_reset(char mode, const char *cmd)
        *IOP3XX_PCSR = 0x30;
        /* Jump into ROM at address 0 */
-        cpu_reset(0);
+        soft_restart(0);
 }
diff --git a/arch/arm/mach-iop32x/include/mach/vmalloc.h b/arch/arm/mach-iop32x/include/mach/vmalloc.h
deleted file mode 100644
index c4862d48e583..000000000000
--- a/arch/arm/mach-iop32x/include/mach/vmalloc.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/*
- * arch/arm/mach-iop32x/include/mach/vmalloc.h
- */
-#define VMALLOC_END     0xfe000000UL
diff --git a/arch/arm/mach-iop33x/include/mach/io.h b/arch/arm/mach-iop33x/include/mach/io.h
index 39e893e97c21..a8a66fc8fbdb 100644
--- a/arch/arm/mach-iop33x/include/mach/io.h
+++ b/arch/arm/mach-iop33x/include/mach/io.h
@@ -13,15 +13,8 @@
 #include <asm/hardware/iop3xx.h>
-extern void __iomem *__iop3xx_ioremap(unsigned long cookie, size_t size,
-        unsigned int mtype);
-extern void __iop3xx_iounmap(void __iomem *addr);
 #define IO_SPACE_LIMIT          0xffffffff
 #define __io(p)         ((void __iomem *)IOP3XX_PCI_IO_PHYS_TO_VIRT(p))
 #define __mem_pci(a)            (a)
-#define __arch_ioremap  __iop3xx_ioremap
-#define __arch_iounmap  __iop3xx_iounmap
 #endif
diff --git a/arch/arm/mach-iop33x/include/mach/system.h b/arch/arm/mach-iop33x/include/mach/system.h
index f192a34be073..86d1b20dd692 100644
--- a/arch/arm/mach-iop33x/include/mach/system.h
+++ b/arch/arm/mach-iop33x/include/mach/system.h
@@ -19,5 +19,5 @@ static inline void arch_reset(char mode, const char *cmd)
        *IOP3XX_PCSR = 0x30;
        /* Jump into ROM at address 0 */
-        cpu_reset(0);
+        soft_restart(0);
 }
diff --git a/arch/arm/mach-iop33x/include/mach/vmalloc.h b/arch/arm/mach-iop33x/include/mach/vmalloc.h
deleted file mode 100644
index 48331dc23704..000000000000
--- a/arch/arm/mach-iop33x/include/mach/vmalloc.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/*
- * arch/arm/mach-iop33x/include/mach/vmalloc.h
- */
-#define VMALLOC_END     0xfe000000UL
diff --git a/arch/arm/mach-ixp2000/include/mach/system.h b/arch/arm/mach-ixp2000/include/mach/system.h
index de370992c848..810df7b93982 100644
--- a/arch/arm/mach-ixp2000/include/mach/system.h
+++ b/arch/arm/mach-ixp2000/include/mach/system.h
@@ -19,8 +19,6 @@ static inline void arch_idle(void)
 static inline void arch_reset(char mode, const char *cmd)
 {
-        local_irq_disable();
        /*
         * Reset flash banking register so that we are pointing at
         * RedBoot bank.
diff --git a/arch/arm/mach-ixp2000/include/mach/vmalloc.h b/arch/arm/mach-ixp2000/include/mach/vmalloc.h
deleted file mode 100644
index 61c8dae24f95..000000000000
--- a/arch/arm/mach-ixp2000/include/mach/vmalloc.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * arch/arm/mach-ixp2000/include/mach/vmalloc.h
- *
- * Author: Naeem Afzal <naeem.m.afzal@intel.com>
- *
- * Copyright 2002 Intel Corp.
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- * Just any arbitrary offset to the start of the vmalloc VM area: the
- * current 8MB value just means that there will be a 8MB "hole" after the
- * physical memory until the kernel virtual memory starts.  That means that
- * any out-of-bounds memory accesses will hopefully be caught.
- * The vmalloc() routines leaves a hole of 4kB between each vmalloced
- * area for the same reason. ;)
- */
-#define VMALLOC_END         0xfb000000UL
diff --git a/arch/arm/mach-ixp23xx/include/mach/io.h b/arch/arm/mach-ixp23xx/include/mach/io.h
index a1749d0fd896..4ce4353b9f72 100644
--- a/arch/arm/mach-ixp23xx/include/mach/io.h
+++ b/arch/arm/mach-ixp23xx/include/mach/io.h
@@ -20,33 +20,4 @@
 #define __io(p)         ((void __iomem*)((p) + IXP23XX_PCI_IO_VIRT))
 #define __mem_pci(a)    (a)
-static inline void __iomem *
-ixp23xx_ioremap(unsigned long addr, unsigned long size, unsigned int mtype)
-{
-        if (addr >= IXP23XX_PCI_MEM_START &&
-                addr <= IXP23XX_PCI_MEM_START + IXP23XX_PCI_MEM_SIZE) {
-                if (addr + size > IXP23XX_PCI_MEM_START + IXP23XX_PCI_MEM_SIZE)
-                        return NULL;
-                return (void __iomem *)
-                        ((addr - IXP23XX_PCI_MEM_START) + IXP23XX_PCI_MEM_VIRT);
-        }
-        return __arm_ioremap(addr, size, mtype);
-}
-static inline void
-ixp23xx_iounmap(void __iomem *addr)
-{
-        if ((((u32)addr) >= IXP23XX_PCI_MEM_VIRT) &&
-            (((u32)addr) < IXP23XX_PCI_MEM_VIRT + IXP23XX_PCI_MEM_SIZE))
-                return;
-        __iounmap(addr);
-}
-#define __arch_ioremap  ixp23xx_ioremap
-#define __arch_iounmap  ixp23xx_iounmap
 #endif
diff --git a/arch/arm/mach-ixp23xx/include/mach/vmalloc.h b/arch/arm/mach-ixp23xx/include/mach/vmalloc.h
deleted file mode 100644
index 896c56a1c00e..000000000000
--- a/arch/arm/mach-ixp23xx/include/mach/vmalloc.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/*
- * arch/arm/mach-ixp23xx/include/mach/vmalloc.h
- *
- * Copyright (c) 2005 MontaVista Software, Inc.
- *
- * NPU mappings end at 0xf0000000 and we allocate 64MB for board
- * specific static I/O.
- */
-#define VMALLOC_END     (0xec000000UL)
diff --git a/arch/arm/mach-ixp4xx/include/mach/system.h b/arch/arm/mach-ixp4xx/include/mach/system.h
index 54c0af7fa2d4..24337d9d275b 100644
--- a/arch/arm/mach-ixp4xx/include/mach/system.h
+++ b/arch/arm/mach-ixp4xx/include/mach/system.h
@@ -26,7 +26,7 @@ static inline void arch_reset(char mode, const char *cmd)
 {
        if ( 1 && mode == 's') {
                /* Jump into ROM at address 0 */
-                cpu_reset(0);
+                soft_restart(0);
        } else {
                /* Use on-chip reset capability */
diff --git a/arch/arm/mach-ixp4xx/include/mach/vmalloc.h b/arch/arm/mach-ixp4xx/include/mach/vmalloc.h
deleted file mode 100644
index 9bcd64d59854..000000000000
--- a/arch/arm/mach-ixp4xx/include/mach/vmalloc.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/*
- * arch/arm/mach-ixp4xx/include/mach/vmalloc.h
- */
-#define VMALLOC_END       (0xff000000UL)
diff --git a/arch/arm/mach-kirkwood/include/mach/io.h b/arch/arm/mach-kirkwood/include/mach/io.h
index 1aaddc364f2e..49dd0cb5e166 100644
--- a/arch/arm/mach-kirkwood/include/mach/io.h
+++ b/arch/arm/mach-kirkwood/include/mach/io.h
@@ -19,31 +19,6 @@ static inline void __iomem *__io(unsigned long addr)
                                        + KIRKWOOD_PCIE_IO_VIRT_BASE);
 }
-static inline void __iomem *
-__arch_ioremap(unsigned long paddr, size_t size, unsigned int mtype)
-{
-        void __iomem *retval;
-        unsigned long offs = paddr - KIRKWOOD_REGS_PHYS_BASE;
-        if (mtype == MT_DEVICE && size && offs < KIRKWOOD_REGS_SIZE &&
-            size <= KIRKWOOD_REGS_SIZE && offs + size <= KIRKWOOD_REGS_SIZE) {
-                retval = (void __iomem *)KIRKWOOD_REGS_VIRT_BASE + offs;
-        } else {
-                retval = __arm_ioremap(paddr, size, mtype);
-        }
-        return retval;
-}
-static inline void
-__arch_iounmap(void __iomem *addr)
-{
-        if (addr < (void __iomem *)KIRKWOOD_REGS_VIRT_BASE ||
-            addr >= (void __iomem *)(KIRKWOOD_REGS_VIRT_BASE + KIRKWOOD_REGS_SIZE))
-                __iounmap(addr);
-}
-#define __arch_ioremap          __arch_ioremap
-#define __arch_iounmap          __arch_iounmap
 #define __io(a)                 __io(a)
 #define __mem_pci(a)            (a)
diff --git a/arch/arm/mach-kirkwood/include/mach/vmalloc.h b/arch/arm/mach-kirkwood/include/mach/vmalloc.h
deleted file mode 100644
index bf162ca3d2c1..000000000000
--- a/arch/arm/mach-kirkwood/include/mach/vmalloc.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/*
- * arch/arm/mach-kirkwood/include/mach/vmalloc.h
- */
-#define VMALLOC_END     0xfe800000UL
diff --git a/arch/arm/mach-ks8695/include/mach/system.h b/arch/arm/mach-ks8695/include/mach/system.h
index fb1dda9be2d0..ceb19c90aa52 100644
--- a/arch/arm/mach-ks8695/include/mach/system.h
+++ b/arch/arm/mach-ks8695/include/mach/system.h
@@ -32,7 +32,7 @@ static void arch_reset(char mode, const char *cmd)
        unsigned int reg;
        if (mode == 's')
-                cpu_reset(0);
+                soft_restart(0);
        /* disable timer0 */
        reg = __raw_readl(KS8695_TMR_VA + KS8695_TMCON);
diff --git a/arch/arm/mach-ks8695/include/mach/vmalloc.h b/arch/arm/mach-ks8695/include/mach/vmalloc.h
deleted file mode 100644
index 744ac66be3a2..000000000000
--- a/arch/arm/mach-ks8695/include/mach/vmalloc.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * arch/arm/mach-ks8695/include/mach/vmalloc.h
- *
- * Copyright (C) 2006 Ben Dooks
- * Copyright (C) 2006 Simtec Electronics <linux@simtec.co.uk>
- *
- * KS8695 vmalloc definition
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __ASM_ARCH_VMALLOC_H
-#define __ASM_ARCH_VMALLOC_H
-#define VMALLOC_END       (KS8695_IO_VA & PGDIR_MASK)
-#endif
diff --git a/arch/arm/mach-lpc32xx/include/mach/system.h b/arch/arm/mach-lpc32xx/include/mach/system.h
index df3b0dea4d7b..d47f3b1c24b8 100644
--- a/arch/arm/mach-lpc32xx/include/mach/system.h
+++ b/arch/arm/mach-lpc32xx/include/mach/system.h
@@ -33,9 +33,6 @@ static inline void arch_reset(char mode, const char *cmd)
        case 'h':
                printk(KERN_CRIT "RESET: Rebooting system\n");
-                /* Disable interrupts */
-                local_irq_disable();
                lpc32xx_watchdog_reset();
                break;
diff --git a/arch/arm/mach-lpc32xx/include/mach/vmalloc.h b/arch/arm/mach-lpc32xx/include/mach/vmalloc.h
deleted file mode 100644
index 720fa43a60bf..000000000000
--- a/arch/arm/mach-lpc32xx/include/mach/vmalloc.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * arch/arm/mach-lpc32xx/include/mach/vmalloc.h
- *
- * Author: Kevin Wells <kevin.wells@nxp.com>
- *
- * Copyright (C) 2010 NXP Semiconductors
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#ifndef __ASM_ARCH_VMALLOC_H
-#define __ASM_ARCH_VMALLOC_H
-#define VMALLOC_END     0xF0000000UL
-#endif
diff --git a/arch/arm/mach-mmp/include/mach/system.h b/arch/arm/mach-mmp/include/mach/system.h
index 1a8a25edb1b4..cb0637933a85 100644
--- a/arch/arm/mach-mmp/include/mach/system.h
+++ b/arch/arm/mach-mmp/include/mach/system.h
@@ -19,8 +19,8 @@ static inline void arch_idle(void)
 static inline void arch_reset(char mode, const char *cmd)
 {
        if (cpu_is_pxa168())
-                cpu_reset(0xffff0000);
+                soft_restart(0xffff0000);
        else
-                cpu_reset(0);
+                soft_restart(0);
 }
 #endif /* __ASM_MACH_SYSTEM_H */
diff --git a/arch/arm/mach-mmp/include/mach/vmalloc.h b/arch/arm/mach-mmp/include/mach/vmalloc.h
deleted file mode 100644
index 1d0bac003ad0..000000000000
--- a/arch/arm/mach-mmp/include/mach/vmalloc.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/*
- * linux/arch/arm/mach-mmp/include/mach/vmalloc.h
- */
-#define VMALLOC_END     0xfe000000UL
diff --git a/arch/arm/mach-msm/board-msm8960.c b/arch/arm/mach-msm/board-msm8960.c
index 6dc1cbd2a595..ed3598128530 100644
--- a/arch/arm/mach-msm/board-msm8960.c
+++ b/arch/arm/mach-msm/board-msm8960.c
@@ -99,6 +99,7 @@ MACHINE_START(MSM8960_SIM, "QCT MSM8960 SIMULATOR")
        .map_io = msm8960_map_io,
        .init_irq = msm8960_init_irq,
        .timer = &msm_timer,
+        .handle_irq = gic_handle_irq,
        .init_machine = msm8960_sim_init,
 MACHINE_END
@@ -108,6 +109,7 @@ MACHINE_START(MSM8960_RUMI3, "QCT MSM8960 RUMI3")
        .map_io = msm8960_map_io,
        .init_irq = msm8960_init_irq,
        .timer = &msm_timer,
+        .handle_irq = gic_handle_irq,
        .init_machine = msm8960_rumi3_init,
 MACHINE_END
diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c
index 44bf71688373..0a113424632c 100644
--- a/arch/arm/mach-msm/board-msm8x60.c
+++ b/arch/arm/mach-msm/board-msm8x60.c
@@ -108,6 +108,7 @@ MACHINE_START(MSM8X60_RUMI3, "QCT MSM8X60 RUMI3")
        .reserve = msm8x60_reserve,
        .map_io = msm8x60_map_io,
        .init_irq = msm8x60_init_irq,
+        .handle_irq = gic_handle_irq,
        .init_machine = msm8x60_init,
        .timer = &msm_timer,
 MACHINE_END
@@ -117,6 +118,7 @@ MACHINE_START(MSM8X60_SURF, "QCT MSM8X60 SURF")
        .reserve = msm8x60_reserve,
        .map_io = msm8x60_map_io,
        .init_irq = msm8x60_init_irq,
+        .handle_irq = gic_handle_irq,
        .init_machine = msm8x60_init,
        .timer = &msm_timer,
 MACHINE_END
@@ -126,6 +128,7 @@ MACHINE_START(MSM8X60_SIM, "QCT MSM8X60 SIMULATOR")
        .reserve = msm8x60_reserve,
        .map_io = msm8x60_map_io,
        .init_irq = msm8x60_init_irq,
+        .handle_irq = gic_handle_irq,
        .init_machine = msm8x60_init,
        .timer = &msm_timer,
 MACHINE_END
@@ -135,6 +138,7 @@ MACHINE_START(MSM8X60_FFA, "QCT MSM8X60 FFA")
        .reserve = msm8x60_reserve,
        .map_io = msm8x60_map_io,
        .init_irq = msm8x60_init_irq,
+        .handle_irq = gic_handle_irq,
        .init_machine = msm8x60_init,
        .timer = &msm_timer,
 MACHINE_END
diff --git a/arch/arm/mach-msm/include/mach/entry-macro-qgic.S b/arch/arm/mach-msm/include/mach/entry-macro-qgic.S
deleted file mode 100644
index 717076f3ca73..000000000000
--- a/arch/arm/mach-msm/include/mach/entry-macro-qgic.S
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * Low-level IRQ helper macros
- *
- * Copyright (c) 2010, Code Aurora Forum. All rights reserved.
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <asm/hardware/entry-macro-gic.S>
-        .macro  disable_fiq
-        .endm
-        .macro  arch_ret_to_user, tmp1, tmp2
-        .endm
diff --git a/arch/arm/mach-msm/include/mach/entry-macro-vic.S b/arch/arm/mach-msm/include/mach/entry-macro-vic.S
deleted file mode 100644
index 70563ed11b36..000000000000
--- a/arch/arm/mach-msm/include/mach/entry-macro-vic.S
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * Copyright (C) 2007 Google, Inc.
- * Author: Brian Swetland <swetland@google.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#include <mach/msm_iomap.h>
-        .macro  disable_fiq
-        .endm
-        .macro  get_irqnr_preamble, base, tmp
-        @ enable imprecise aborts
-        cpsie   a
-        mov     \base, #MSM_VIC_BASE
-        .endm
-        .macro  arch_ret_to_user, tmp1, tmp2
-        .endm
-        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-        @ 0xD0 has irq# or old irq# if the irq has been handled
-        @ 0xD4 has irq# or -1 if none pending *but* if you just
-        @ read 0xD4 you never get the first irq for some reason
-        ldr     \irqnr, [\base, #0xD0]
-        ldr     \irqnr, [\base, #0xD4]
-        cmp     \irqnr, #0xffffffff
-        .endm
diff --git a/arch/arm/mach-msm/include/mach/entry-macro.S b/arch/arm/mach-msm/include/mach/entry-macro.S
index b16f082eeb6f..41f7003ef34f 100644
--- a/arch/arm/mach-msm/include/mach/entry-macro.S
+++ b/arch/arm/mach-msm/include/mach/entry-macro.S
@@ -16,8 +16,27 @@
 *
 */
-#if defined(CONFIG_ARM_GIC)
+        .macro  disable_fiq
-#include <mach/entry-macro-qgic.S>
+        .endm
-#else
-#include <mach/entry-macro-vic.S>
+        .macro  arch_ret_to_user, tmp1, tmp2
+        .endm
+#if !defined(CONFIG_ARM_GIC)
+#include <mach/msm_iomap.h>
+        .macro  get_irqnr_preamble, base, tmp
+        @ enable imprecise aborts
+        cpsie   a
+        mov     \base, #MSM_VIC_BASE
+        .endm
+        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+        @ 0xD0 has irq# or old irq# if the irq has been handled
+        @ 0xD4 has irq# or -1 if none pending *but* if you just
+        @ read 0xD4 you never get the first irq for some reason
+        ldr     \irqnr, [\base, #0xD0]
+        ldr     \irqnr, [\base, #0xD4]
+        cmp     \irqnr, #0xffffffff
+        .endm
 #endif
diff --git a/arch/arm/mach-msm/include/mach/vmalloc.h b/arch/arm/mach-msm/include/mach/vmalloc.h
deleted file mode 100644
index d138448eff16..000000000000
--- a/arch/arm/mach-msm/include/mach/vmalloc.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* arch/arm/mach-msm/include/mach/vmalloc.h
- *
- * Copyright (C) 2007 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#ifndef __ASM_ARCH_MSM_VMALLOC_H
-#define __ASM_ARCH_MSM_VMALLOC_H
-#define VMALLOC_END       0xd0000000UL
-#endif
diff --git a/arch/arm/mach-mv78xx0/include/mach/vmalloc.h b/arch/arm/mach-mv78xx0/include/mach/vmalloc.h
deleted file mode 100644
index ba26fe98e640..000000000000
--- a/arch/arm/mach-mv78xx0/include/mach/vmalloc.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/*
- * arch/arm/mach-mv78xx0/include/mach/vmalloc.h
- */
-#define VMALLOC_END     0xfe000000UL
diff --git a/arch/arm/mach-mxs/include/mach/vmalloc.h b/arch/arm/mach-mxs/include/mach/vmalloc.h
deleted file mode 100644
index 103b0165ed0b..000000000000
--- a/arch/arm/mach-mxs/include/mach/vmalloc.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- *  Copyright (C) 2000 Russell King.
- *  Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#ifndef __MACH_MXS_VMALLOC_H__
-#define __MACH_MXS_VMALLOC_H__
-/* vmalloc ending address */
-#define VMALLOC_END       0xf4000000UL
-#endif /* __MACH_MXS_VMALLOC_H__ */
diff --git a/arch/arm/mach-mxs/system.c b/arch/arm/mach-mxs/system.c
index 20ec3bddf7cd..cab88364e7c1 100644
--- a/arch/arm/mach-mxs/system.c
+++ b/arch/arm/mach-mxs/system.c
@@ -53,7 +53,7 @@ void arch_reset(char mode, const char *cmd)
        mdelay(50);
        /* We'll take a jump through zero as a poor second */
-        cpu_reset(0);
+        soft_restart(0);
 }
 static int __init mxs_arch_reset_init(void)
diff --git a/arch/arm/mach-netx/include/mach/entry-macro.S b/arch/arm/mach-netx/include/mach/entry-macro.S
index 844f1f9acbdf..6e9f1cbe1634 100644
--- a/arch/arm/mach-netx/include/mach/entry-macro.S
+++ b/arch/arm/mach-netx/include/mach/entry-macro.S
@@ -18,22 +18,9 @@
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
-#include <mach/hardware.h>
                .macro  disable_fiq
                .endm
-                .macro  get_irqnr_preamble, base, tmp
-                ldr     \base, =io_p2v(0x001ff000)
-                .endm
                .macro  arch_ret_to_user, tmp1, tmp2
                .endm
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-                ldr     \irqstat, [\base, #0]
-                clz     \irqnr, \irqstat
-                rsb     \irqnr, \irqnr, #31
-                cmp     \irqstat, #0
-                .endm
diff --git a/arch/arm/mach-netx/nxdb500.c b/arch/arm/mach-netx/nxdb500.c
index 90903dd44cbc..ef8cf3574a02 100644
--- a/arch/arm/mach-netx/nxdb500.c
+++ b/arch/arm/mach-netx/nxdb500.c
@@ -28,6 +28,7 @@
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
+#include <asm/hardware/vic.h>
 #include <mach/netx-regs.h>
 #include <mach/eth.h>
@@ -203,6 +204,7 @@ MACHINE_START(NXDB500, "Hilscher nxdb500")
        .atag_offset    = 0x100,
        .map_io         = netx_map_io,
        .init_irq       = netx_init_irq,
+        .handle_irq     = vic_handle_irq,
        .timer          = &netx_timer,
        .init_machine   = nxdb500_init,
 MACHINE_END
diff --git a/arch/arm/mach-netx/nxdkn.c b/arch/arm/mach-netx/nxdkn.c
index c63384aba500..588558bdd800 100644
--- a/arch/arm/mach-netx/nxdkn.c
+++ b/arch/arm/mach-netx/nxdkn.c
@@ -28,6 +28,7 @@
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
+#include <asm/hardware/vic.h>
 #include <mach/netx-regs.h>
 #include <mach/eth.h>
@@ -96,6 +97,7 @@ MACHINE_START(NXDKN, "Hilscher nxdkn")
        .atag_offset    = 0x100,
        .map_io         = netx_map_io,
        .init_irq       = netx_init_irq,
+        .handle_irq     = vic_handle_irq,
        .timer          = &netx_timer,
        .init_machine   = nxdkn_init,
 MACHINE_END
diff --git a/arch/arm/mach-netx/nxeb500hmi.c b/arch/arm/mach-netx/nxeb500hmi.c
index 8f548ec83ad2..cfcbb5038648 100644
--- a/arch/arm/mach-netx/nxeb500hmi.c
+++ b/arch/arm/mach-netx/nxeb500hmi.c
@@ -28,6 +28,7 @@
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
+#include <asm/hardware/vic.h>
 #include <mach/netx-regs.h>
 #include <mach/eth.h>
@@ -180,6 +181,7 @@ MACHINE_START(NXEB500HMI, "Hilscher nxeb500hmi")
        .atag_offset    = 0x100,
        .map_io         = netx_map_io,
        .init_irq       = netx_init_irq,
+        .handle_irq     = vic_handle_irq,
        .timer          = &netx_timer,
        .init_machine   = nxeb500hmi_init,
 MACHINE_END
diff --git a/arch/arm/mach-nomadik/board-nhk8815.c b/arch/arm/mach-nomadik/board-nhk8815.c
index 0cbb74c96ef7..f98259c050ee 100644
--- a/arch/arm/mach-nomadik/board-nhk8815.c
+++ b/arch/arm/mach-nomadik/board-nhk8815.c
@@ -21,6 +21,7 @@
 #include <linux/mtd/onenand.h>
 #include <linux/mtd/partitions.h>
 #include <linux/io.h>
+#include <asm/hardware/vic.h>
 #include <asm/sizes.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -280,6 +281,7 @@ MACHINE_START(NOMADIK, "NHK8815")
        .atag_offset    = 0x100,
        .map_io         = cpu8815_map_io,
        .init_irq       = cpu8815_init_irq,
+        .handle_irq     = vic_handle_irq,
        .timer          = &nomadik_timer,
        .init_machine   = nhk8815_platform_init,
 MACHINE_END
diff --git a/arch/arm/mach-nomadik/include/mach/entry-macro.S b/arch/arm/mach-nomadik/include/mach/entry-macro.S
index 49f1aa3bb420..98ea1c1fbbab 100644
--- a/arch/arm/mach-nomadik/include/mach/entry-macro.S
+++ b/arch/arm/mach-nomadik/include/mach/entry-macro.S
@@ -6,38 +6,8 @@
 * warranty of any kind, whether express or implied.
 */
-#include <mach/hardware.h>
-#include <mach/irqs.h>
        .macro  disable_fiq
        .endm
-        .macro  get_irqnr_preamble, base, tmp
-        ldr     \base, =IO_ADDRESS(NOMADIK_IC_BASE)
-        .endm
        .macro  arch_ret_to_user, tmp1, tmp2
        .endm
-        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-        /* This stanza gets the irq mask from one of two status registers */
-        mov     \irqnr, #0
-        ldr     \irqstat, [\base, #VIC_REG_IRQSR0]      @ get masked status
-        cmp     \irqstat, #0
-        bne     1001f
-        add     \irqnr, \irqnr, #32
-        ldr     \irqstat, [\base, #VIC_REG_IRQSR1]      @ get masked status
-1001:   tst     \irqstat, #15
-        bne     1002f
-        add     \irqnr, \irqnr, #4
-        movs    \irqstat, \irqstat, lsr #4
-        bne     1001b
-1002:   tst     \irqstat, #1
-        bne     1003f
-        add     \irqnr, \irqnr, #1
-        movs    \irqstat, \irqstat, lsr #1
-        bne     1002b
-1003:   /* EQ will be set if no irqs pending */
-        .endm
diff --git a/arch/arm/mach-nomadik/include/mach/vmalloc.h b/arch/arm/mach-nomadik/include/mach/vmalloc.h
deleted file mode 100644
index f83d574d9445..000000000000
--- a/arch/arm/mach-nomadik/include/mach/vmalloc.h
+++ /dev/null
@@ -1,2 +0,0 @@
-#define VMALLOC_END       0xe8000000UL
diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c
index b0f15d234a12..af7911963c0d 100644
--- a/arch/arm/mach-omap1/board-ams-delta.c
+++ b/arch/arm/mach-omap1/board-ams-delta.c
@@ -35,7 +35,7 @@
 #include <plat/mux.h>
 #include <plat/usb.h>
 #include <plat/board.h>
-#include <plat/common.h>
+#include "common.h"
 #include <mach/camera.h>
 #include <mach/ams-delta-fiq.h>
diff --git a/arch/arm/mach-omap1/board-fsample.c b/arch/arm/mach-omap1/board-fsample.c
index 23178275f96b..b9c4c0f933ee 100644
--- a/arch/arm/mach-omap1/board-fsample.c
+++ b/arch/arm/mach-omap1/board-fsample.c
@@ -32,7 +32,7 @@
 #include <plat/flash.h>
 #include <plat/fpga.h>
 #include <plat/keypad.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/board.h>
 /* fsample is pretty close to p2-sample */
diff --git a/arch/arm/mach-omap1/board-generic.c b/arch/arm/mach-omap1/board-generic.c
index dc5b75de531c..7f41d7a504a5 100644
--- a/arch/arm/mach-omap1/board-generic.c
+++ b/arch/arm/mach-omap1/board-generic.c
@@ -25,7 +25,7 @@
 #include <plat/mux.h>
 #include <plat/usb.h>
 #include <plat/board.h>
-#include <plat/common.h>
+#include "common.h"
 /* assume no Mini-AB port */
diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c
index b334b1481678..7933b97698f8 100644
--- a/arch/arm/mach-omap1/board-h2.c
+++ b/arch/arm/mach-omap1/board-h2.c
@@ -43,7 +43,7 @@
 #include <plat/irda.h>
 #include <plat/usb.h>
 #include <plat/keypad.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/flash.h>
 #include "board-h2.h"
diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c
index 74ebe72c9848..04be2f83ca09 100644
--- a/arch/arm/mach-omap1/board-h3.c
+++ b/arch/arm/mach-omap1/board-h3.c
@@ -45,7 +45,7 @@
 #include <plat/usb.h>
 #include <plat/keypad.h>
 #include <plat/dma.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/flash.h>
 #include "board-h3.h"
diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c
index 3e91baab1a89..46fcfeb1f11e 100644
--- a/arch/arm/mach-omap1/board-htcherald.c
+++ b/arch/arm/mach-omap1/board-htcherald.c
@@ -41,7 +41,7 @@
 #include <asm/mach/arch.h>
 #include <plat/omap7xx.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/board.h>
 #include <plat/keypad.h>
 #include <plat/usb.h>
diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c
index 273153dba15b..f99d11de1531 100644
--- a/arch/arm/mach-omap1/board-innovator.c
+++ b/arch/arm/mach-omap1/board-innovator.c
@@ -37,7 +37,7 @@
 #include <plat/tc.h>
 #include <plat/usb.h>
 #include <plat/keypad.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/mmc.h>
 /* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */
diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c
index 6798b8488315..c64342388ec3 100644
--- a/arch/arm/mach-omap1/board-nokia770.c
+++ b/arch/arm/mach-omap1/board-nokia770.c
@@ -30,7 +30,7 @@
 #include <plat/usb.h>
 #include <plat/board.h>
 #include <plat/keypad.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/hwa742.h>
 #include <plat/lcd_mipid.h>
 #include <plat/mmc.h>
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c
index c3859278d257..a409dfcc5b18 100644
--- a/arch/arm/mach-omap1/board-osk.c
+++ b/arch/arm/mach-omap1/board-osk.c
@@ -51,7 +51,7 @@
 #include <plat/usb.h>
 #include <plat/mux.h>
 #include <plat/tc.h>
-#include <plat/common.h>
+#include "common.h"
 /* At OMAP5912 OSK the Ethernet is directly connected to CS1 */
 #define OMAP_OSK_ETHR_START             0x04800300
diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c
index f9c44cb15b47..105292d39484 100644
--- a/arch/arm/mach-omap1/board-palmte.c
+++ b/arch/arm/mach-omap1/board-palmte.c
@@ -41,7 +41,7 @@
 #include <plat/board.h>
 #include <plat/irda.h>
 #include <plat/keypad.h>
-#include <plat/common.h>
+#include "common.h"
 #define PALMTE_USBDETECT_GPIO   0
 #define PALMTE_USB_OR_DC_GPIO   1
diff --git a/arch/arm/mach-omap1/board-palmtt.c b/arch/arm/mach-omap1/board-palmtt.c
index 11a98539f7bb..387a9006358d 100644
--- a/arch/arm/mach-omap1/board-palmtt.c
+++ b/arch/arm/mach-omap1/board-palmtt.c
@@ -39,7 +39,7 @@
 #include <plat/board.h>
 #include <plat/irda.h>
 #include <plat/keypad.h>
-#include <plat/common.h>
+#include "common.h"
 #include <linux/spi/spi.h>
 #include <linux/spi/ads7846.h>
diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c
index 42061573e380..df6d15e68aad 100644
--- a/arch/arm/mach-omap1/board-palmz71.c
+++ b/arch/arm/mach-omap1/board-palmz71.c
@@ -41,7 +41,7 @@
 #include <plat/board.h>
 #include <plat/irda.h>
 #include <plat/keypad.h>
-#include <plat/common.h>
+#include "common.h"
 #include <linux/spi/spi.h>
 #include <linux/spi/ads7846.h>
diff --git a/arch/arm/mach-omap1/board-perseus2.c b/arch/arm/mach-omap1/board-perseus2.c
index 203ae07550db..57ecd7e09831 100644
--- a/arch/arm/mach-omap1/board-perseus2.c
+++ b/arch/arm/mach-omap1/board-perseus2.c
@@ -32,7 +32,7 @@
 #include <plat/fpga.h>
 #include <plat/flash.h>
 #include <plat/keypad.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/board.h>
 static const unsigned int p2_keymap[] = {
diff --git a/arch/arm/mach-omap1/board-sx1.c b/arch/arm/mach-omap1/board-sx1.c
index 092a4c046407..774ae39fd636 100644
--- a/arch/arm/mach-omap1/board-sx1.c
+++ b/arch/arm/mach-omap1/board-sx1.c
@@ -40,7 +40,7 @@
 #include <plat/usb.h>
 #include <plat/tc.h>
 #include <plat/board.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/keypad.h>
 #include <plat/board-sx1.h>
diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c
index 61ed6cdab2bd..7721c146d8d6 100644
--- a/arch/arm/mach-omap1/board-voiceblue.c
+++ b/arch/arm/mach-omap1/board-voiceblue.c
@@ -34,7 +34,7 @@
 #include <asm/mach/map.h>
 #include <plat/board-voiceblue.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/flash.h>
 #include <plat/mux.h>
 #include <plat/tc.h>
diff --git a/arch/arm/mach-omap1/common.h b/arch/arm/mach-omap1/common.h
new file mode 100644
index 000000000000..52c4eda97fa8
--- /dev/null
+++ b/arch/arm/mach-omap1/common.h
@@ -0,0 +1,61 @@
+/*
+ *
+ * Header for code common to all OMAP1 machines.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the  GNU General Public License along
+ * with this program; if not, write  to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#ifndef __ARCH_ARM_MACH_OMAP1_COMMON_H
+#define __ARCH_ARM_MACH_OMAP1_COMMON_H
+#include <plat/common.h>
+#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
+void omap7xx_map_io(void);
+#else
+static inline void omap7xx_map_io(void)
+{
+}
+#endif
+#ifdef CONFIG_ARCH_OMAP15XX
+void omap15xx_map_io(void);
+#else
+static inline void omap15xx_map_io(void)
+{
+}
+#endif
+#ifdef CONFIG_ARCH_OMAP16XX
+void omap16xx_map_io(void);
+#else
+static inline void omap16xx_map_io(void)
+{
+}
+#endif
+void omap1_init_early(void);
+void omap1_init_irq(void);
+extern struct sys_timer omap1_timer;
+extern bool omap_32k_timer_init(void);
+#endif /* __ARCH_ARM_MACH_OMAP1_COMMON_H */
diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c
index 475cb2f50d87..1d76a63c0983 100644
--- a/arch/arm/mach-omap1/devices.c
+++ b/arch/arm/mach-omap1/devices.c
@@ -22,7 +22,7 @@
 #include <mach/hardware.h>
 #include <asm/mach/map.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/tc.h>
 #include <plat/board.h>
 #include <plat/mux.h>
diff --git a/arch/arm/mach-omap1/include/mach/vmalloc.h b/arch/arm/mach-omap1/include/mach/vmalloc.h
deleted file mode 100644
index 22ec4a479577..000000000000
--- a/arch/arm/mach-omap1/include/mach/vmalloc.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- *  arch/arm/mach-omap1/include/mach/vmalloc.h
- *
- *  Copyright (C) 2000 Russell King.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#define VMALLOC_END     0xd8000000UL
diff --git a/arch/arm/mach-omap1/io.c b/arch/arm/mach-omap1/io.c
index 7969cfda4454..8e55b6fb3478 100644
--- a/arch/arm/mach-omap1/io.c
+++ b/arch/arm/mach-omap1/io.c
@@ -121,7 +121,6 @@ void __init omap16xx_map_io(void)
 void omap1_init_early(void)
 {
        omap_check_revision();
-        omap_ioremap_init();
        /* REVISIT: Refer to OMAP5910 Errata, Advisory SYS_1: "Timeout Abort
         * on a Posted Write in the TIPB Bridge".
diff --git a/arch/arm/mach-omap1/time.c b/arch/arm/mach-omap1/time.c
index a1837771e031..485a21d31004 100644
--- a/arch/arm/mach-omap1/time.c
+++ b/arch/arm/mach-omap1/time.c
@@ -54,7 +54,7 @@
 #include <asm/mach/irq.h>
 #include <asm/mach/time.h>
-#include <plat/common.h>
+#include "common.h"
 #ifdef CONFIG_OMAP_MPU_TIMER
diff --git a/arch/arm/mach-omap1/timer32k.c b/arch/arm/mach-omap1/timer32k.c
index 96604a50c4fe..9a54ef4dcf5e 100644
--- a/arch/arm/mach-omap1/timer32k.c
+++ b/arch/arm/mach-omap1/timer32k.c
@@ -52,7 +52,7 @@
 #include <asm/irq.h>
 #include <asm/mach/irq.h>
 #include <asm/mach/time.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/dmtimer.h>
 /*
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index e1293aa513d3..a34d0f7d1bfa 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -25,6 +25,7 @@ config ARCH_OMAP2
        depends on ARCH_OMAP2PLUS
        default y
        select CPU_V6
+        select MULTI_IRQ_HANDLER
 config ARCH_OMAP3
        bool "TI OMAP3"
@@ -36,6 +37,7 @@ config ARCH_OMAP3
        select ARCH_HAS_OPP
        select PM_OPP if PM
        select ARM_CPU_SUSPEND if PM
+        select MULTI_IRQ_HANDLER
 config ARCH_OMAP4
        bool "TI OMAP4"
@@ -74,8 +76,13 @@ config SOC_OMAP3430
        default y
        select ARCH_OMAP_OTG
-config SOC_OMAPTI816X
+config SOC_OMAPTI81XX
-        bool "TI816X support"
+        bool "TI81XX support"
+        depends on ARCH_OMAP3
+        default y
+config SOC_OMAPAM33XX
+        bool "AM33XX support"
        depends on ARCH_OMAP3
        default y
@@ -312,7 +319,7 @@ config MACH_OMAP_3630SDP
 config MACH_TI8168EVM
        bool "TI8168 Evaluation Module"
-        depends on SOC_OMAPTI816X
+        depends on SOC_OMAPTI81XX
        default y
 config MACH_OMAP_4430SDP
@@ -351,6 +358,27 @@ config OMAP3_SDRC_AC_TIMING
          wish to say no.  Selecting yes without understanding what is
          going on could result in system crashes;
+config OMAP4_ERRATA_I688
+        bool "OMAP4 errata: Async Bridge Corruption"
+        depends on ARCH_OMAP4
+        select ARCH_HAS_BARRIERS
+        help
+          If a data is stalled inside asynchronous bridge because of back
+          pressure, it may be accepted multiple times, creating pointer
+          misalignment that will corrupt next transfers on that data path
+          until next reset of the system (No recovery procedure once the
+          issue is hit, the path remains consistently broken). Async bridge
+          can be found on path between MPU to EMIF and MPU to L3 interconnect.
+          This situation can happen only when the idle is initiated by a
+          Master Request Disconnection (which is trigged by software when
+          executing WFI on CPU).
+          The work-around for this errata needs all the initiators connected
+          through async bridge must ensure that data path is properly drained
+          before issuing WFI. This condition will be met if one Strongly ordered
+          access is performed to the target right before executing the WFI.
+          In MPU case, L3 T2ASYNC FIFO and DDR T2ASYNC FIFO needs to be drained.
+          IO barrier ensure that there is no synchronisation loss on initiators
+          operating on both interconnect port simultaneously.
 endmenu
 endif
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index b009f17dee56..63a5efad70e8 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -11,10 +11,11 @@ hwmod-common				= omap_hwmod.o \
                                          omap_hwmod_common_data.o
 clock-common                            = clock.o clock_common_data.o \
                                          clkt_dpll.o clkt_clksel.o
+secure-common                          = omap-smc.o omap-secure.o
-obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common)
+obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common) $(secure-common)
-obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common)
+obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common)
-obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common)
+obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common)
 obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
@@ -24,11 +25,13 @@ obj-$(CONFIG_TWL4030_CORE) += omap_twl.o
 obj-$(CONFIG_SMP)                       += omap-smp.o omap-headsmp.o
 obj-$(CONFIG_LOCAL_TIMERS)              += timer-mpu.o
 obj-$(CONFIG_HOTPLUG_CPU)               += omap-hotplug.o
-obj-$(CONFIG_ARCH_OMAP4)                += omap44xx-smc.o omap4-common.o
+obj-$(CONFIG_ARCH_OMAP4)                += omap4-common.o omap-wakeupgen.o \
+                                           sleep44xx.o
 plus_sec := $(call as-instr,.arch_extension sec,+sec)
 AFLAGS_omap-headsmp.o                   :=-Wa,-march=armv7-a$(plus_sec)
-AFLAGS_omap44xx-smc.o                   :=-Wa,-march=armv7-a$(plus_sec)
+AFLAGS_omap-smc.o                       :=-Wa,-march=armv7-a$(plus_sec)
+AFLAGS_sleep44xx.o                      :=-Wa,-march=armv7-a$(plus_sec)
 # Functions loaded to SRAM
 obj-$(CONFIG_SOC_OMAP2420)              += sram242x.o
@@ -62,7 +65,8 @@ obj-$(CONFIG_ARCH_OMAP2)		+= pm24xx.o
 obj-$(CONFIG_ARCH_OMAP2)                += sleep24xx.o
 obj-$(CONFIG_ARCH_OMAP3)                += pm34xx.o sleep34xx.o \
                                           cpuidle34xx.o
-obj-$(CONFIG_ARCH_OMAP4)                += pm44xx.o
+obj-$(CONFIG_ARCH_OMAP4)                += pm44xx.o omap-mpuss-lowpower.o \
+                                           cpuidle44xx.o
 obj-$(CONFIG_PM_DEBUG)                  += pm-debug.o
 obj-$(CONFIG_OMAP_SMARTREFLEX)          += sr_device.o smartreflex.o
 obj-$(CONFIG_OMAP_SMARTREFLEX_CLASS3)   += smartreflex-class3.o
@@ -77,6 +81,7 @@ endif
 endif
 # PRCM
+obj-y                                   += prm_common.o
 obj-$(CONFIG_ARCH_OMAP2)                += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o
 obj-$(CONFIG_ARCH_OMAP3)                += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o \
                                           vc3xxx_data.o vp3xxx_data.o
@@ -86,7 +91,7 @@ obj-$(CONFIG_ARCH_OMAP3)		+= prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o \
 obj-$(CONFIG_ARCH_OMAP4)                += prcm.o cm2xxx_3xxx.o cminst44xx.o \
                                           cm44xx.o prcm_mpu44xx.o \
                                           prminst44xx.o vc44xx_data.o \
-                                           vp44xx_data.o
+                                           vp44xx_data.o prm44xx.o
 # OMAP voltage domains
 voltagedomain-common                    := voltage.o vc.o vp.o
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index d704f0ac328d..d88143faca59 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -34,7 +34,7 @@
 #include <asm/mach/map.h>
 #include <plat/board.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/gpmc.h>
 #include <plat/usb.h>
 #include <plat/gpmc-smc91x.h>
@@ -301,6 +301,7 @@ MACHINE_START(OMAP_2430SDP, "OMAP2430 sdp2430 board")
        .map_io         = omap243x_map_io,
        .init_early     = omap2430_init_early,
        .init_irq       = omap2_init_irq,
+        .handle_irq     = omap2_intc_handle_irq,
        .init_machine   = omap_2430sdp_init,
        .timer          = &omap2_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index 77142c13fa13..109b434159f5 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -33,7 +33,7 @@
 #include <plat/mcspi.h>
 #include <plat/board.h>
 #include <plat/usb.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/dma.h>
 #include <plat/gpmc.h>
 #include <video/omapdss.h>
@@ -475,106 +475,8 @@ static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
 static struct omap_board_mux board_mux[] __initdata = {
        { .reg_offset = OMAP_MUX_TERMINATOR },
 };
-static struct omap_device_pad serial1_pads[] __initdata = {
-        /*
-         * Note that off output enable is an active low
-         * signal. So setting this means pin is a
-         * input enabled in off mode
-         */
-        OMAP_MUX_STATIC("uart1_cts.uart1_cts",
-                         OMAP_PIN_INPUT |
-                         OMAP_PIN_OFF_INPUT_PULLDOWN |
-                         OMAP_OFFOUT_EN |
-                         OMAP_MUX_MODE0),
-        OMAP_MUX_STATIC("uart1_rts.uart1_rts",
-                         OMAP_PIN_OUTPUT |
-                         OMAP_OFF_EN |
-                         OMAP_MUX_MODE0),
-        OMAP_MUX_STATIC("uart1_rx.uart1_rx",
-                         OMAP_PIN_INPUT |
-                         OMAP_PIN_OFF_INPUT_PULLDOWN |
-                         OMAP_OFFOUT_EN |
-                         OMAP_MUX_MODE0),
-        OMAP_MUX_STATIC("uart1_tx.uart1_tx",
-                         OMAP_PIN_OUTPUT |
-                         OMAP_OFF_EN |
-                         OMAP_MUX_MODE0),
-};
-static struct omap_device_pad serial2_pads[] __initdata = {
-        OMAP_MUX_STATIC("uart2_cts.uart2_cts",
-                         OMAP_PIN_INPUT_PULLUP |
-                         OMAP_PIN_OFF_INPUT_PULLDOWN |
-                         OMAP_OFFOUT_EN |
-                         OMAP_MUX_MODE0),
-        OMAP_MUX_STATIC("uart2_rts.uart2_rts",
-                         OMAP_PIN_OUTPUT |
-                         OMAP_OFF_EN |
-                         OMAP_MUX_MODE0),
-        OMAP_MUX_STATIC("uart2_rx.uart2_rx",
-                         OMAP_PIN_INPUT |
-                         OMAP_PIN_OFF_INPUT_PULLDOWN |
-                         OMAP_OFFOUT_EN |
-                         OMAP_MUX_MODE0),
-        OMAP_MUX_STATIC("uart2_tx.uart2_tx",
-                         OMAP_PIN_OUTPUT |
-                         OMAP_OFF_EN |
-                         OMAP_MUX_MODE0),
-};
-static struct omap_device_pad serial3_pads[] __initdata = {
-        OMAP_MUX_STATIC("uart3_cts_rctx.uart3_cts_rctx",
-                         OMAP_PIN_INPUT_PULLDOWN |
-                         OMAP_PIN_OFF_INPUT_PULLDOWN |
-                         OMAP_OFFOUT_EN |
-                         OMAP_MUX_MODE0),
-        OMAP_MUX_STATIC("uart3_rts_sd.uart3_rts_sd",
-                         OMAP_PIN_OUTPUT |
-                         OMAP_OFF_EN |
-                         OMAP_MUX_MODE0),
-        OMAP_MUX_STATIC("uart3_rx_irrx.uart3_rx_irrx",
-                         OMAP_PIN_INPUT |
-                         OMAP_PIN_OFF_INPUT_PULLDOWN |
-                         OMAP_OFFOUT_EN |
-                         OMAP_MUX_MODE0),
-        OMAP_MUX_STATIC("uart3_tx_irtx.uart3_tx_irtx",
-                         OMAP_PIN_OUTPUT |
-                         OMAP_OFF_EN |
-                         OMAP_MUX_MODE0),
-};
-static struct omap_board_data serial1_data __initdata = {
-        .id             = 0,
-        .pads           = serial1_pads,
-        .pads_cnt       = ARRAY_SIZE(serial1_pads),
-};
-static struct omap_board_data serial2_data __initdata = {
-        .id             = 1,
-        .pads           = serial2_pads,
-        .pads_cnt       = ARRAY_SIZE(serial2_pads),
-};
-static struct omap_board_data serial3_data __initdata = {
-        .id             = 2,
-        .pads           = serial3_pads,
-        .pads_cnt       = ARRAY_SIZE(serial3_pads),
-};
-static inline void board_serial_init(void)
-{
-        omap_serial_init_port(&serial1_data);
-        omap_serial_init_port(&serial2_data);
-        omap_serial_init_port(&serial3_data);
-}
 #else
 #define board_mux       NULL
-static inline void board_serial_init(void)
-{
-        omap_serial_init();
-}
 #endif
 /*
@@ -711,7 +613,7 @@ static void __init omap_3430sdp_init(void)
        else
                gpio_pendown = SDP3430_TS_GPIO_IRQ_SDPV1;
        omap_ads7846_init(1, gpio_pendown, 310, NULL);
-        board_serial_init();
+        omap_serial_init();
        omap_sdrc_init(hyb18m512160af6_sdrc_params, NULL);
        usb_musb_init(NULL);
        board_smc91x_init();
@@ -728,6 +630,7 @@ MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board")
        .map_io         = omap3_map_io,
        .init_early     = omap3430_init_early,
        .init_irq       = omap3_init_irq,
+        .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = omap_3430sdp_init,
        .timer          = &omap3_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c
index f552305162fc..7969dd904bd3 100644
--- a/arch/arm/mach-omap2/board-3630sdp.c
+++ b/arch/arm/mach-omap2/board-3630sdp.c
@@ -16,7 +16,7 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/board.h>
 #include <plat/gpmc-smc91x.h>
 #include <plat/usb.h>
@@ -215,6 +215,7 @@ MACHINE_START(OMAP_3630SDP, "OMAP 3630SDP board")
        .map_io         = omap3_map_io,
        .init_early     = omap3630_init_early,
        .init_irq       = omap3_init_irq,
+        .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = omap_sdp_init,
        .timer          = &omap3_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index 515646886b59..5f264fad69bc 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -27,13 +27,13 @@
 #include <linux/leds_pwm.h>
 #include <mach/hardware.h>
-#include <mach/omap4-common.h>
+#include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <plat/board.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/usb.h>
 #include <plat/mmc.h>
 #include <plat/omap4-keypad.h>
@@ -837,74 +837,8 @@ static struct omap_board_mux board_mux[] __initdata = {
        { .reg_offset = OMAP_MUX_TERMINATOR },
 };
-static struct omap_device_pad serial2_pads[] __initdata = {
-        OMAP_MUX_STATIC("uart2_cts.uart2_cts",
-                         OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
-        OMAP_MUX_STATIC("uart2_rts.uart2_rts",
-                         OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
-        OMAP_MUX_STATIC("uart2_rx.uart2_rx",
-                         OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
-        OMAP_MUX_STATIC("uart2_tx.uart2_tx",
-                         OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
-};
-static struct omap_device_pad serial3_pads[] __initdata = {
-        OMAP_MUX_STATIC("uart3_cts_rctx.uart3_cts_rctx",
-                         OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
-        OMAP_MUX_STATIC("uart3_rts_sd.uart3_rts_sd",
-                         OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
-        OMAP_MUX_STATIC("uart3_rx_irrx.uart3_rx_irrx",
-                         OMAP_PIN_INPUT | OMAP_MUX_MODE0),
-        OMAP_MUX_STATIC("uart3_tx_irtx.uart3_tx_irtx",
-                         OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
-};
-static struct omap_device_pad serial4_pads[] __initdata = {
-        OMAP_MUX_STATIC("uart4_rx.uart4_rx",
-                         OMAP_PIN_INPUT | OMAP_MUX_MODE0),
-        OMAP_MUX_STATIC("uart4_tx.uart4_tx",
-                         OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
-};
-static struct omap_board_data serial2_data __initdata = {
-        .id             = 1,
-        .pads           = serial2_pads,
-        .pads_cnt       = ARRAY_SIZE(serial2_pads),
-};
-static struct omap_board_data serial3_data __initdata = {
-        .id             = 2,
-        .pads           = serial3_pads,
-        .pads_cnt       = ARRAY_SIZE(serial3_pads),
-};
-static struct omap_board_data serial4_data __initdata = {
-        .id             = 3,
-        .pads           = serial4_pads,
-        .pads_cnt       = ARRAY_SIZE(serial4_pads),
-};
-static inline void board_serial_init(void)
-{
-        struct omap_board_data bdata;
-        bdata.flags     = 0;
-        bdata.pads      = NULL;
-        bdata.pads_cnt  = 0;
-        bdata.id        = 0;
-        /* pass dummy data for UART1 */
-        omap_serial_init_port(&bdata);
-        omap_serial_init_port(&serial2_data);
-        omap_serial_init_port(&serial3_data);
-        omap_serial_init_port(&serial4_data);
-}
 #else
 #define board_mux       NULL
-static inline void board_serial_init(void)
-{
-        omap_serial_init();
-}
 #endif
 static void omap4_sdp4430_wifi_mux_init(void)
@@ -954,7 +888,7 @@ static void __init omap_4430sdp_init(void)
        omap4_i2c_init();
        omap_sfh7741prox_init();
        platform_add_devices(sdp4430_devices, ARRAY_SIZE(sdp4430_devices));
-        board_serial_init();
+        omap_serial_init();
        omap_sdrc_init(NULL, NULL);
        omap4_sdp4430_wifi_init();
        omap4_twl6030_hsmmc_init(mmc);
@@ -984,6 +918,7 @@ MACHINE_START(OMAP_4430SDP, "OMAP4430 4430SDP board")
        .map_io         = omap4_map_io,
        .init_early     = omap4430_init_early,
        .init_irq       = gic_init_irq,
+        .handle_irq     = gic_handle_irq,
        .init_machine   = omap_4430sdp_init,
        .timer          = &omap4_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-am3517crane.c b/arch/arm/mach-omap2/board-am3517crane.c
index 7834536ab416..7e90f93263db 100644
--- a/arch/arm/mach-omap2/board-am3517crane.c
+++ b/arch/arm/mach-omap2/board-am3517crane.c
@@ -27,7 +27,7 @@
 #include <asm/mach/map.h>
 #include <plat/board.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/usb.h>
 #include "mux.h"
@@ -98,6 +98,7 @@ MACHINE_START(CRANEBOARD, "AM3517/05 CRANEBOARD")
        .map_io         = omap3_map_io,
        .init_early     = am35xx_init_early,
        .init_irq       = omap3_init_irq,
+        .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = am3517_crane_init,
        .timer          = &omap3_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
index d314f033c9df..551cae8d9b8a 100644
--- a/arch/arm/mach-omap2/board-am3517evm.c
+++ b/arch/arm/mach-omap2/board-am3517evm.c
@@ -32,7 +32,7 @@
 #include <asm/mach/map.h>
 #include <plat/board.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/usb.h>
 #include <video/omapdss.h>
 #include <video/omap-panel-generic-dpi.h>
@@ -491,6 +491,7 @@ MACHINE_START(OMAP3517EVM, "OMAP3517/AM3517 EVM")
        .map_io         = omap3_map_io,
        .init_early     = am35xx_init_early,
        .init_irq       = omap3_init_irq,
+        .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = am3517_evm_init,
        .timer          = &omap3_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index de8134b7f580..5a66480feed0 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -37,7 +37,7 @@
 #include <plat/led.h>
 #include <plat/usb.h>
 #include <plat/board.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/gpmc.h>
 #include <video/omapdss.h>
@@ -354,6 +354,7 @@ MACHINE_START(OMAP_APOLLON, "OMAP24xx Apollon")
        .map_io         = omap242x_map_io,
        .init_early     = omap2420_init_early,
        .init_irq       = omap2_init_irq,
+        .handle_irq     = omap2_intc_handle_irq,
        .init_machine   = omap_apollon_init,
        .timer          = &omap2_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index bd1bcacb40f9..510b6a2ff0fa 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -37,7 +37,7 @@
 #include <asm/mach/map.h>
 #include <plat/board.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/nand.h>
 #include <plat/gpmc.h>
 #include <plat/usb.h>
@@ -634,6 +634,7 @@ MACHINE_START(CM_T35, "Compulab CM-T35")
        .map_io         = omap3_map_io,
        .init_early     = omap35xx_init_early,
        .init_irq       = omap3_init_irq,
+        .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = cm_t35_init,
        .timer          = &omap3_timer,
 MACHINE_END
@@ -644,6 +645,7 @@ MACHINE_START(CM_T3730, "Compulab CM-T3730")
        .map_io         = omap3_map_io,
        .init_early     = omap3630_init_early,
        .init_irq       = omap3_init_irq,
+        .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = cm_t3730_init,
        .timer          = &omap3_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c
index 3f4dc6626845..efc5cedb1fbb 100644
--- a/arch/arm/mach-omap2/board-cm-t3517.c
+++ b/arch/arm/mach-omap2/board-cm-t3517.c
@@ -39,7 +39,7 @@
 #include <asm/mach/map.h>
 #include <plat/board.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/usb.h>
 #include <plat/nand.h>
 #include <plat/gpmc.h>
@@ -299,6 +299,7 @@ MACHINE_START(CM_T3517, "Compulab CM-T3517")
        .map_io         = omap3_map_io,
        .init_early     = am35xx_init_early,
        .init_irq       = omap3_init_irq,
+        .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = cm_t3517_init,
        .timer          = &omap3_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index 90154e411da0..d81ea7fa75ef 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -41,7 +41,7 @@
 #include <asm/mach/flash.h>
 #include <plat/board.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/gpmc.h>
 #include <plat/nand.h>
 #include <plat/usb.h>
@@ -660,6 +660,7 @@ MACHINE_START(DEVKIT8000, "OMAP3 Devkit8000")
        .map_io         = omap3_map_io,
        .init_early     = omap35xx_init_early,
        .init_irq       = omap3_init_irq,
+        .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = devkit8000_init,
        .timer          = &omap3_secure_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index fb55fa3dad5a..a508ed5cc890 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -20,8 +20,7 @@
 #include <asm/mach/arch.h>
 #include <plat/board.h>
-#include <plat/common.h>
+#include "common.h"
-#include <mach/omap4-common.h>
 #include "common-board-devices.h"
 /*
@@ -70,7 +69,6 @@ static void __init omap_generic_init(void)
        if (node)
                irq_domain_add_simple(node, 0);
-        omap_serial_init();
        omap_sdrc_init(NULL, NULL);
        of_platform_populate(NULL, omap_dt_match_table, NULL, NULL);
@@ -122,6 +120,7 @@ DT_MACHINE_START(OMAP243X_DT, "Generic OMAP2430 (Flattened Device Tree)")
        .map_io         = omap243x_map_io,
        .init_early     = omap2430_init_early,
        .init_irq       = omap2_init_irq,
+        .handle_irq     = omap2_intc_handle_irq,
        .init_machine   = omap_generic_init,
        .timer          = &omap2_timer,
        .dt_compat      = omap243x_boards_compat,
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index 8b351d92a1cc..ec4018362e8e 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -34,7 +34,7 @@
 #include <plat/usb.h>
 #include <plat/board.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/menelaus.h>
 #include <plat/dma.h>
 #include <plat/gpmc.h>
@@ -396,6 +396,7 @@ MACHINE_START(OMAP_H4, "OMAP2420 H4 board")
        .map_io         = omap242x_map_io,
        .init_early     = omap2420_init_early,
        .init_irq       = omap2_init_irq,
+        .handle_irq     = omap2_intc_handle_irq,
        .init_machine   = omap_h4_init,
        .timer          = &omap2_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index d0a3f78a9b69..5949f6ae3edf 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -28,7 +28,7 @@
 #include <asm/mach/arch.h>
 #include <plat/board.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/gpmc.h>
 #include <plat/usb.h>
 #include <video/omapdss.h>
@@ -672,6 +672,7 @@ MACHINE_START(IGEP0020, "IGEP v2 board")
        .map_io         = omap3_map_io,
        .init_early     = omap35xx_init_early,
        .init_irq       = omap3_init_irq,
+        .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = igep_init,
        .timer          = &omap3_timer,
 MACHINE_END
@@ -682,6 +683,7 @@ MACHINE_START(IGEP0030, "IGEP OMAP3 module")
        .map_io         = omap3_map_io,
        .init_early     = omap35xx_init_early,
        .init_irq       = omap3_init_irq,
+        .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = igep_init,
        .timer          = &omap3_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index e179da0c4da5..13bde0e66934 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -36,7 +36,7 @@
 #include <plat/mcspi.h>
 #include <plat/board.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/gpmc.h>
 #include <mach/board-zoom.h>
@@ -434,6 +434,7 @@ MACHINE_START(OMAP_LDP, "OMAP LDP board")
        .map_io         = omap3_map_io,
        .init_early     = omap3430_init_early,
        .init_irq       = omap3_init_irq,
+        .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = omap_ldp_init,
        .timer          = &omap3_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
index e9d5f4a3d064..118f38c4b37d 100644
--- a/arch/arm/mach-omap2/board-n8x0.c
+++ b/arch/arm/mach-omap2/board-n8x0.c
@@ -26,7 +26,7 @@
 #include <asm/mach-types.h>
 #include <plat/board.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/menelaus.h>
 #include <mach/irqs.h>
 #include <plat/mcspi.h>
@@ -644,15 +644,15 @@ static inline void board_serial_init(void)
        bdata.pads_cnt = 0;
        bdata.id = 0;
-        omap_serial_init_port(&bdata);
+        omap_serial_init_port(&bdata, NULL);
        bdata.id = 1;
-        omap_serial_init_port(&bdata);
+        omap_serial_init_port(&bdata, NULL);
        bdata.id = 2;
        bdata.pads = serial2_pads;
        bdata.pads_cnt = ARRAY_SIZE(serial2_pads);
-        omap_serial_init_port(&bdata);
+        omap_serial_init_port(&bdata, NULL);
 }
 #else
@@ -689,6 +689,7 @@ MACHINE_START(NOKIA_N800, "Nokia N800")
        .map_io         = omap242x_map_io,
        .init_early     = omap2420_init_early,
        .init_irq       = omap2_init_irq,
+        .handle_irq     = omap2_intc_handle_irq,
        .init_machine   = n8x0_init_machine,
        .timer          = &omap2_timer,
 MACHINE_END
@@ -699,6 +700,7 @@ MACHINE_START(NOKIA_N810, "Nokia N810")
        .map_io         = omap242x_map_io,
        .init_early     = omap2420_init_early,
        .init_irq       = omap2_init_irq,
+        .handle_irq     = omap2_intc_handle_irq,
        .init_machine   = n8x0_init_machine,
        .timer          = &omap2_timer,
 MACHINE_END
@@ -709,6 +711,7 @@ MACHINE_START(NOKIA_N810_WIMAX, "Nokia N810 WiMAX")
        .map_io         = omap242x_map_io,
        .init_early     = omap2420_init_early,
        .init_irq       = omap2_init_irq,
+        .handle_irq     = omap2_intc_handle_irq,
        .init_machine   = n8x0_init_machine,
        .timer          = &omap2_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index 4a71cb7e42d4..c34f56588284 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -40,7 +40,7 @@
 #include <asm/mach/flash.h>
 #include <plat/board.h>
-#include <plat/common.h>
+#include "common.h"
 #include <video/omapdss.h>
 #include <video/omap-panel-dvi.h>
 #include <plat/gpmc.h>
@@ -559,6 +559,7 @@ MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board")
        .map_io         = omap3_map_io,
        .init_early     = omap3_init_early,
        .init_irq       = omap3_init_irq,
+        .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = omap3_beagle_init,
        .timer          = &omap3_secure_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index ec00b2ec7022..f11bc444e7be 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -43,7 +43,7 @@
 #include <plat/board.h>
 #include <plat/usb.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/mcspi.h>
 #include <video/omapdss.h>
 #include <video/omap-panel-dvi.h>
@@ -681,6 +681,7 @@ MACHINE_START(OMAP3EVM, "OMAP3 EVM")
        .map_io         = omap3_map_io,
        .init_early     = omap35xx_init_early,
        .init_irq       = omap3_init_irq,
+        .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = omap3_evm_init,
        .timer          = &omap3_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c
index 7c0f193f246d..5fa6bad9574e 100644
--- a/arch/arm/mach-omap2/board-omap3logic.c
+++ b/arch/arm/mach-omap2/board-omap3logic.c
@@ -40,7 +40,7 @@
 #include <plat/mux.h>
 #include <plat/board.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/gpmc-smsc911x.h>
 #include <plat/gpmc.h>
 #include <plat/sdrc.h>
@@ -208,6 +208,7 @@ MACHINE_START(OMAP3_TORPEDO, "Logic OMAP3 Torpedo board")
        .map_io         = omap3_map_io,
        .init_early     = omap35xx_init_early,
        .init_irq       = omap3_init_irq,
+        .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = omap3logic_init,
        .timer          = &omap3_timer,
 MACHINE_END
@@ -217,6 +218,7 @@ MACHINE_START(OMAP3530_LV_SOM, "OMAP Logic 3530 LV SOM board")
        .map_io         = omap3_map_io,
        .init_early     = omap35xx_init_early,
        .init_irq       = omap3_init_irq,
+        .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = omap3logic_init,
        .timer          = &omap3_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
index f7811f4cfc3d..ef315c585b75 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -41,7 +41,7 @@
 #include <asm/mach/map.h>
 #include <plat/board.h>
-#include <plat/common.h>
+#include "common.h"
 #include <mach/hardware.h>
 #include <plat/mcspi.h>
 #include <plat/usb.h>
@@ -606,6 +606,7 @@ MACHINE_START(OMAP3_PANDORA, "Pandora Handheld Console")
        .map_io         = omap3_map_io,
        .init_early     = omap35xx_init_early,
        .init_irq       = omap3_init_irq,
+        .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = omap3pandora_init,
        .timer          = &omap3_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
index ddb7d6663c6d..b21d70a2e4a7 100644
--- a/arch/arm/mach-omap2/board-omap3stalker.c
+++ b/arch/arm/mach-omap2/board-omap3stalker.c
@@ -35,7 +35,7 @@
 #include <asm/mach/flash.h>
 #include <plat/board.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/gpmc.h>
 #include <plat/nand.h>
 #include <plat/usb.h>
@@ -454,6 +454,7 @@ MACHINE_START(SBC3530, "OMAP3 STALKER")
        .map_io                 = omap3_map_io,
        .init_early             = omap35xx_init_early,
        .init_irq               = omap3_init_irq,
+        .handle_irq             = omap3_intc_handle_irq,
        .init_machine           = omap3_stalker_init,
        .timer                  = &omap3_secure_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c
index a2d0d1971e27..18cd340f9b7b 100644
--- a/arch/arm/mach-omap2/board-omap3touchbook.c
+++ b/arch/arm/mach-omap2/board-omap3touchbook.c
@@ -44,7 +44,7 @@
 #include <asm/mach/flash.h>
 #include <plat/board.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/gpmc.h>
 #include <plat/nand.h>
 #include <plat/usb.h>
@@ -381,6 +381,7 @@ MACHINE_START(TOUCHBOOK, "OMAP3 touchbook Board")
        .map_io         = omap3_map_io,
        .init_early     = omap3430_init_early,
        .init_irq       = omap3_init_irq,
+        .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = omap3_touchbook_init,
        .timer          = &omap3_secure_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index a8c2c4263e38..ea45f5835103 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -30,14 +30,14 @@
 #include <linux/wl12xx.h>
 #include <mach/hardware.h>
-#include <mach/omap4-common.h>
+#include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <video/omapdss.h>
 #include <plat/board.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/usb.h>
 #include <plat/mmc.h>
 #include <video/omap-panel-dvi.h>
@@ -364,74 +364,8 @@ static struct omap_board_mux board_mux[] __initdata = {
        { .reg_offset = OMAP_MUX_TERMINATOR },
 };
-static struct omap_device_pad serial2_pads[] __initdata = {
-        OMAP_MUX_STATIC("uart2_cts.uart2_cts",
-                         OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
-        OMAP_MUX_STATIC("uart2_rts.uart2_rts",
-                         OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
-        OMAP_MUX_STATIC("uart2_rx.uart2_rx",
-                         OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
-        OMAP_MUX_STATIC("uart2_tx.uart2_tx",
-                         OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
-};
-static struct omap_device_pad serial3_pads[] __initdata = {
-        OMAP_MUX_STATIC("uart3_cts_rctx.uart3_cts_rctx",
-                         OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
-        OMAP_MUX_STATIC("uart3_rts_sd.uart3_rts_sd",
-                         OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
-        OMAP_MUX_STATIC("uart3_rx_irrx.uart3_rx_irrx",
-                         OMAP_PIN_INPUT | OMAP_MUX_MODE0),
-        OMAP_MUX_STATIC("uart3_tx_irtx.uart3_tx_irtx",
-                         OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
-};
-static struct omap_device_pad serial4_pads[] __initdata = {
-        OMAP_MUX_STATIC("uart4_rx.uart4_rx",
-                         OMAP_PIN_INPUT | OMAP_MUX_MODE0),
-        OMAP_MUX_STATIC("uart4_tx.uart4_tx",
-                         OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
-};
-static struct omap_board_data serial2_data __initdata = {
-        .id             = 1,
-        .pads           = serial2_pads,
-        .pads_cnt       = ARRAY_SIZE(serial2_pads),
-};
-static struct omap_board_data serial3_data __initdata = {
-        .id             = 2,
-        .pads           = serial3_pads,
-        .pads_cnt       = ARRAY_SIZE(serial3_pads),
-};
-static struct omap_board_data serial4_data __initdata = {
-        .id             = 3,
-        .pads           = serial4_pads,
-        .pads_cnt       = ARRAY_SIZE(serial4_pads),
-};
-static inline void board_serial_init(void)
-{
-        struct omap_board_data bdata;
-        bdata.flags     = 0;
-        bdata.pads      = NULL;
-        bdata.pads_cnt  = 0;
-        bdata.id        = 0;
-        /* pass dummy data for UART1 */
-        omap_serial_init_port(&bdata);
-        omap_serial_init_port(&serial2_data);
-        omap_serial_init_port(&serial3_data);
-        omap_serial_init_port(&serial4_data);
-}
 #else
 #define board_mux       NULL
-static inline void board_serial_init(void)
-{
-        omap_serial_init();
-}
 #endif
 /* Display DVI */
@@ -562,7 +496,7 @@ static void __init omap4_panda_init(void)
        omap4_panda_i2c_init();
        platform_add_devices(panda_devices, ARRAY_SIZE(panda_devices));
        platform_device_register(&omap_vwlan_device);
-        board_serial_init();
+        omap_serial_init();
        omap_sdrc_init(NULL, NULL);
        omap4_twl6030_hsmmc_init(mmc);
        omap4_ehci_init();
@@ -577,6 +511,7 @@ MACHINE_START(OMAP4_PANDA, "OMAP4 Panda board")
        .map_io         = omap4_map_io,
        .init_early     = omap4430_init_early,
        .init_irq       = gic_init_irq,
+        .handle_irq     = gic_handle_irq,
        .init_machine   = omap4_panda_init,
        .timer          = &omap4_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index 4cf7aeabab86..60a61ea759bf 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -43,7 +43,7 @@
 #include <asm/mach/map.h>
 #include <plat/board.h>
-#include <plat/common.h>
+#include "common.h"
 #include <video/omapdss.h>
 #include <video/omap-panel-generic-dpi.h>
 #include <video/omap-panel-dvi.h>
@@ -562,6 +562,7 @@ MACHINE_START(OVERO, "Gumstix Overo")
        .map_io         = omap3_map_io,
        .init_early     = omap35xx_init_early,
        .init_irq       = omap3_init_irq,
+        .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = overo_init,
        .timer          = &omap3_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-rm680.c b/arch/arm/mach-omap2/board-rm680.c
index 616fb39763b0..a79d49e3fe09 100644
--- a/arch/arm/mach-omap2/board-rm680.c
+++ b/arch/arm/mach-omap2/board-rm680.c
@@ -25,7 +25,7 @@
 #include <plat/mmc.h>
 #include <plat/usb.h>
 #include <plat/gpmc.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/onenand.h>
 #include "mux.h"
@@ -149,6 +149,7 @@ MACHINE_START(NOKIA_RM680, "Nokia RM-680 board")
        .map_io         = omap3_map_io,
        .init_early     = omap3630_init_early,
        .init_irq       = omap3_init_irq,
+        .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = rm680_init,
        .timer          = &omap3_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index c15c5c9c9085..108fee6146fc 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -27,7 +27,7 @@
 #include <plat/mcspi.h>
 #include <plat/board.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/dma.h>
 #include <plat/gpmc.h>
 #include <plat/onenand.h>
diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c
index 4af7c4b2881a..4e3c0965edf3 100644
--- a/arch/arm/mach-omap2/board-rx51.c
+++ b/arch/arm/mach-omap2/board-rx51.c
@@ -25,7 +25,7 @@
 #include <plat/mcspi.h>
 #include <plat/board.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/dma.h>
 #include <plat/gpmc.h>
 #include <plat/usb.h>
@@ -127,6 +127,7 @@ MACHINE_START(NOKIA_RX51, "Nokia RX-51 board")
        .map_io         = omap3_map_io,
        .init_early     = omap3430_init_early,
        .init_irq       = omap3_init_irq,
+        .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = rx51_init,
        .timer          = &omap3_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-ti8168evm.c b/arch/arm/mach-omap2/board-ti8168evm.c
index e6ee8842285c..b236fcc023ac 100644
--- a/arch/arm/mach-omap2/board-ti8168evm.c
+++ b/arch/arm/mach-omap2/board-ti8168evm.c
@@ -22,7 +22,7 @@
 #include <plat/irqs.h>
 #include <plat/board.h>
-#include <plat/common.h>
+#include "common.h"
 static struct omap_board_config_kernel ti8168_evm_config[] __initdata = {
 };
@@ -35,17 +35,12 @@ static void __init ti8168_evm_init(void)
        omap_board_config_size = ARRAY_SIZE(ti8168_evm_config);
 }
-static void __init ti8168_evm_map_io(void)
-{
-        omapti816x_map_common_io();
-}
 MACHINE_START(TI8168EVM, "ti8168evm")
        /* Maintainer: Texas Instruments */
        .atag_offset    = 0x100,
-        .map_io         = ti8168_evm_map_io,
+        .map_io         = ti81xx_map_io,
-        .init_early     = ti816x_init_early,
+        .init_early     = ti81xx_init_early,
-        .init_irq       = ti816x_init_irq,
+        .init_irq       = ti81xx_init_irq,
        .timer          = &omap3_timer,
        .init_machine   = ti8168_evm_init,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c
index 6d0aa4fcb7c3..8d7ce11cfeaf 100644
--- a/arch/arm/mach-omap2/board-zoom-peripherals.c
+++ b/arch/arm/mach-omap2/board-zoom-peripherals.c
@@ -24,7 +24,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/usb.h>
 #include <mach/board-zoom.h>
diff --git a/arch/arm/mach-omap2/board-zoom.c b/arch/arm/mach-omap2/board-zoom.c
index be6684dc4f55..70e5b54a2115 100644
--- a/arch/arm/mach-omap2/board-zoom.c
+++ b/arch/arm/mach-omap2/board-zoom.c
@@ -21,7 +21,7 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/board.h>
 #include <plat/usb.h>
@@ -135,6 +135,7 @@ MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board")
        .map_io         = omap3_map_io,
        .init_early     = omap3430_init_early,
        .init_irq       = omap3_init_irq,
+        .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = omap_zoom_init,
        .timer          = &omap3_timer,
 MACHINE_END
@@ -145,6 +146,7 @@ MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board")
        .map_io         = omap3_map_io,
        .init_early     = omap3630_init_early,
        .init_irq       = omap3_init_irq,
+        .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = omap_zoom_init,
        .timer          = &omap3_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 1f3481f8d695..f57ed5baeccf 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -35,7 +35,7 @@
 #include "cm-regbits-24xx.h"
 #include "cm-regbits-34xx.h"
-u8 cpu_mask;
+u16 cpu_mask;
 /*
 * clkdm_control: if true, then when a clock is enabled in the
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 2311bc217226..b8c2a686481c 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -132,7 +132,7 @@ void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
                               const char *core_ck_name,
                               const char *mpu_ck_name);
-extern u8 cpu_mask;
+extern u16 cpu_mask;
 extern const struct clkops clkops_omap2_dflt_wait;
 extern const struct clkops clkops_dummy;
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index 5d0064a4fb5a..60424f41156b 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -3517,6 +3517,10 @@ int __init omap3xxx_clk_init(void)
        } else if (cpu_is_ti816x()) {
                cpu_mask = RATE_IN_TI816X;
                cpu_clkflg = CK_TI816X;
+        } else if (cpu_is_am33xx()) {
+                cpu_mask = RATE_IN_AM33XX;
+        } else if (cpu_is_ti814x()) {
+                cpu_mask = RATE_IN_TI814X;
        } else if (cpu_is_omap34xx()) {
                if (omap_rev() == OMAP3430_REV_ES1_0) {
                        cpu_mask = RATE_IN_3430ES1;
@@ -3600,7 +3604,7 @@ int __init omap3xxx_clk_init(void)
         * Lock DPLL5 -- here only until other device init code can
         * handle this
         */
-        if (!cpu_is_ti816x() && (omap_rev() >= OMAP3430_REV_ES2_0))
+        if (!cpu_is_ti81xx() && (omap_rev() >= OMAP3430_REV_ES2_0))
                omap3_clk_lock_dpll5();
        /* Avoid sleeping during omap3_core_dpll_m2_set_rate() */
diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.c b/arch/arm/mach-omap2/cm2xxx_3xxx.c
index 38830d8d4783..04d39cdd2112 100644
--- a/arch/arm/mach-omap2/cm2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/cm2xxx_3xxx.c
@@ -18,7 +18,7 @@
 #include <linux/err.h>
 #include <linux/io.h>
-#include <plat/common.h>
+#include "common.h"
 #include "cm.h"
 #include "cm2xxx_3xxx.h"
diff --git a/arch/arm/mach-omap2/cm44xx.c b/arch/arm/mach-omap2/cm44xx.c
index e96f53ea01a1..6a836303252c 100644
--- a/arch/arm/mach-omap2/cm44xx.c
+++ b/arch/arm/mach-omap2/cm44xx.c
@@ -18,7 +18,7 @@
 #include <linux/err.h>
 #include <linux/io.h>
-#include <plat/common.h>
+#include "common.h"
 #include "cm.h"
 #include "cm1_44xx.h"
diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c
index eb2a472bbf46..6204deaf85b1 100644
--- a/arch/arm/mach-omap2/cminst44xx.c
+++ b/arch/arm/mach-omap2/cminst44xx.c
@@ -20,7 +20,7 @@
 #include <linux/err.h>
 #include <linux/io.h>
-#include <plat/common.h>
+#include "common.h"
 #include "cm.h"
 #include "cm1_44xx.h"
diff --git a/arch/arm/mach-omap2/common.c b/arch/arm/mach-omap2/common.c
index 110e5b9db145..aaf421178c91 100644
--- a/arch/arm/mach-omap2/common.c
+++ b/arch/arm/mach-omap2/common.c
@@ -17,7 +17,7 @@
 #include <linux/clk.h>
 #include <linux/io.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/board.h>
 #include <plat/mux.h>
@@ -110,23 +110,49 @@ void __init omap3_map_io(void)
 /*
 * Adjust TAP register base such that omap3_check_revision accesses the correct
- * TI816X register for checking device ID (it adds 0x204 to tap base while
+ * TI81XX register for checking device ID (it adds 0x204 to tap base while
- * TI816X DEVICE ID register is at offset 0x600 from control base).
+ * TI81XX DEVICE ID register is at offset 0x600 from control base).
 */
-#define TI816X_TAP_BASE         (TI816X_CTRL_BASE + \
+#define TI81XX_TAP_BASE         (TI81XX_CTRL_BASE + \
-                                TI816X_CONTROL_DEVICE_ID - 0x204)
+                                TI81XX_CONTROL_DEVICE_ID - 0x204)
-static struct omap_globals ti816x_globals = {
+static struct omap_globals ti81xx_globals = {
        .class  = OMAP343X_CLASS,
-        .tap    = OMAP2_L4_IO_ADDRESS(TI816X_TAP_BASE),
+        .tap    = OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE),
-        .ctrl   = OMAP2_L4_IO_ADDRESS(TI816X_CTRL_BASE),
+        .ctrl   = OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE),
-        .prm    = OMAP2_L4_IO_ADDRESS(TI816X_PRCM_BASE),
+        .prm    = OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE),
-        .cm     = OMAP2_L4_IO_ADDRESS(TI816X_PRCM_BASE),
+        .cm     = OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE),
 };
-void __init omap2_set_globals_ti816x(void)
+void __init omap2_set_globals_ti81xx(void)
 {
-        __omap2_set_globals(&ti816x_globals);
+        __omap2_set_globals(&ti81xx_globals);
+}
+void __init ti81xx_map_io(void)
+{
+        omapti81xx_map_common_io();
+}
+#define AM33XX_TAP_BASE         (AM33XX_CTRL_BASE + \
+                                TI81XX_CONTROL_DEVICE_ID - 0x204)
+static struct omap_globals am33xx_globals = {
+        .class  = AM335X_CLASS,
+        .tap    = AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE),
+        .ctrl   = AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE),
+        .prm    = AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE),
+        .cm     = AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE),
+};
+void __init omap2_set_globals_am33xx(void)
+{
+        __omap2_set_globals(&am33xx_globals);
+}
+void __init am33xx_map_io(void)
+{
+        omapam33xx_map_common_io();
 }
 #endif
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
new file mode 100644
index 000000000000..90bd2ae85596
--- /dev/null
+++ b/arch/arm/mach-omap2/common.h
@@ -0,0 +1,238 @@
+/*
+ * Header for code common to all OMAP2+ machines.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the  GNU General Public License along
+ * with this program; if not, write  to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#ifndef __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H
+#define __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H
+#ifndef __ASSEMBLER__
+#include <linux/delay.h>
+#include <plat/common.h>
+#include <asm/proc-fns.h>
+#ifdef CONFIG_SOC_OMAP2420
+extern void omap242x_map_common_io(void);
+#else
+static inline void omap242x_map_common_io(void)
+{
+}
+#endif
+#ifdef CONFIG_SOC_OMAP2430
+extern void omap243x_map_common_io(void);
+#else
+static inline void omap243x_map_common_io(void)
+{
+}
+#endif
+#ifdef CONFIG_ARCH_OMAP3
+extern void omap34xx_map_common_io(void);
+#else
+static inline void omap34xx_map_common_io(void)
+{
+}
+#endif
+#ifdef CONFIG_SOC_OMAPTI81XX
+extern void omapti81xx_map_common_io(void);
+#else
+static inline void omapti81xx_map_common_io(void)
+{
+}
+#endif
+#ifdef CONFIG_SOC_OMAPAM33XX
+extern void omapam33xx_map_common_io(void);
+#else
+static inline void omapam33xx_map_common_io(void)
+{
+}
+#endif
+#ifdef CONFIG_ARCH_OMAP4
+extern void omap44xx_map_common_io(void);
+#else
+static inline void omap44xx_map_common_io(void)
+{
+}
+#endif
+extern void omap2_init_common_infrastructure(void);
+extern struct sys_timer omap2_timer;
+extern struct sys_timer omap3_timer;
+extern struct sys_timer omap3_secure_timer;
+extern struct sys_timer omap4_timer;
+void omap2420_init_early(void);
+void omap2430_init_early(void);
+void omap3430_init_early(void);
+void omap35xx_init_early(void);
+void omap3630_init_early(void);
+void omap3_init_early(void);    /* Do not use this one */
+void am35xx_init_early(void);
+void ti81xx_init_early(void);
+void omap4430_init_early(void);
+/*
+ * IO bases for various OMAP processors
+ * Except the tap base, rest all the io bases
+ * listed are physical addresses.
+ */
+struct omap_globals {
+        u32             class;          /* OMAP class to detect */
+        void __iomem    *tap;           /* Control module ID code */
+        void __iomem    *sdrc;           /* SDRAM Controller */
+        void __iomem    *sms;            /* SDRAM Memory Scheduler */
+        void __iomem    *ctrl;           /* System Control Module */
+        void __iomem    *ctrl_pad;      /* PAD Control Module */
+        void __iomem    *prm;            /* Power and Reset Management */
+        void __iomem    *cm;             /* Clock Management */
+        void __iomem    *cm2;
+};
+void omap2_set_globals_242x(void);
+void omap2_set_globals_243x(void);
+void omap2_set_globals_3xxx(void);
+void omap2_set_globals_443x(void);
+void omap2_set_globals_ti81xx(void);
+void omap2_set_globals_am33xx(void);
+/* These get called from omap2_set_globals_xxxx(), do not call these */
+void omap2_set_globals_tap(struct omap_globals *);
+void omap2_set_globals_sdrc(struct omap_globals *);
+void omap2_set_globals_control(struct omap_globals *);
+void omap2_set_globals_prcm(struct omap_globals *);
+void omap242x_map_io(void);
+void omap243x_map_io(void);
+void omap3_map_io(void);
+void am33xx_map_io(void);
+void omap4_map_io(void);
+void ti81xx_map_io(void);
+/**
+ * omap_test_timeout - busy-loop, testing a condition
+ * @cond: condition to test until it evaluates to true
+ * @timeout: maximum number of microseconds in the timeout
+ * @index: loop index (integer)
+ *
+ * Loop waiting for @cond to become true or until at least @timeout
+ * microseconds have passed.  To use, define some integer @index in the
+ * calling code.  After running, if @index == @timeout, then the loop has
+ * timed out.
+ */
+#define omap_test_timeout(cond, timeout, index)                 \
+({                                                              \
+        for (index = 0; index < timeout; index++) {             \
+                if (cond)                                       \
+                        break;                                  \
+                udelay(1);                                      \
+        }                                                       \
+})
+extern struct device *omap2_get_mpuss_device(void);
+extern struct device *omap2_get_iva_device(void);
+extern struct device *omap2_get_l3_device(void);
+extern struct device *omap4_get_dsp_device(void);
+void omap2_init_irq(void);
+void omap3_init_irq(void);
+void ti81xx_init_irq(void);
+extern int omap_irq_pending(void);
+void omap_intc_save_context(void);
+void omap_intc_restore_context(void);
+void omap3_intc_suspend(void);
+void omap3_intc_prepare_idle(void);
+void omap3_intc_resume_idle(void);
+void omap2_intc_handle_irq(struct pt_regs *regs);
+void omap3_intc_handle_irq(struct pt_regs *regs);
+#ifdef CONFIG_CACHE_L2X0
+extern void __iomem *omap4_get_l2cache_base(void);
+#endif
+#ifdef CONFIG_SMP
+extern void __iomem *omap4_get_scu_base(void);
+#else
+static inline void __iomem *omap4_get_scu_base(void)
+{
+        return NULL;
+}
+#endif
+extern void __init gic_init_irq(void);
+extern void omap_smc1(u32 fn, u32 arg);
+extern void __iomem *omap4_get_sar_ram_base(void);
+extern void omap_do_wfi(void);
+#ifdef CONFIG_SMP
+/* Needed for secondary core boot */
+extern void omap_secondary_startup(void);
+extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
+extern void omap_auxcoreboot_addr(u32 cpu_addr);
+extern u32 omap_read_auxcoreboot0(void);
+#endif
+#if defined(CONFIG_SMP) && defined(CONFIG_PM)
+extern int omap4_mpuss_init(void);
+extern int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state);
+extern int omap4_finish_suspend(unsigned long cpu_state);
+extern void omap4_cpu_resume(void);
+extern int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state);
+extern u32 omap4_mpuss_read_prev_context_state(void);
+#else
+static inline int omap4_enter_lowpower(unsigned int cpu,
+                                        unsigned int power_state)
+{
+        cpu_do_idle();
+        return 0;
+}
+static inline int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
+{
+        cpu_do_idle();
+        return 0;
+}
+static inline int omap4_mpuss_init(void)
+{
+        return 0;
+}
+static inline int omap4_finish_suspend(unsigned long cpu_state)
+{
+        return 0;
+}
+static inline void omap4_cpu_resume(void)
+{}
+static inline u32 omap4_mpuss_read_prev_context_state(void)
+{
+        return 0;
+}
+#endif
+#endif /* __ASSEMBLER__ */
+#endif /* __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H */
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index e34d27f8c49c..114c037e433c 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -15,7 +15,7 @@
 #include <linux/kernel.h>
 #include <linux/io.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/sdrc.h>
 #include "cm-regbits-34xx.h"
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index d4ef75d5a382..0ba68d3764bc 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -52,8 +52,8 @@
 #define OMAP343X_CONTROL_PADCONFS_WKUP  0xa00
 #define OMAP343X_CONTROL_GENERAL_WKUP   0xa60
-/* TI816X spefic control submodules */
+/* TI81XX spefic control submodules */
-#define TI816X_CONTROL_DEVCONF          0x600
+#define TI81XX_CONTROL_DEVCONF          0x600
 /* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */
@@ -244,8 +244,8 @@
 #define OMAP3_PADCONF_SAD2D_MSTANDBY   0x250
 #define OMAP3_PADCONF_SAD2D_IDLEACK    0x254
-/* TI816X CONTROL_DEVCONF register offsets */
+/* TI81XX CONTROL_DEVCONF register offsets */
-#define TI816X_CONTROL_DEVICE_ID        (TI816X_CONTROL_DEVCONF + 0x000)
+#define TI81XX_CONTROL_DEVICE_ID        (TI81XX_CONTROL_DEVCONF + 0x000)
 /*
 * REVISIT: This list of registers is not comprehensive - there are more
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
index 942bb4f19f9f..464cffde58fe 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -25,15 +25,16 @@
 #include <linux/sched.h>
 #include <linux/cpuidle.h>
 #include <linux/export.h>
+#include <linux/cpu_pm.h>
 #include <plat/prcm.h>
 #include <plat/irqs.h>
 #include "powerdomain.h"
 #include "clockdomain.h"
-#include <plat/serial.h>
 #include "pm.h"
 #include "control.h"
+#include "common.h"
 #ifdef CONFIG_CPU_IDLE
@@ -123,9 +124,23 @@ static int omap3_enter_idle(struct cpuidle_device *dev,
                pwrdm_for_each_clkdm(core_pd, _cpuidle_deny_idle);
        }
+        /*
+         * Call idle CPU PM enter notifier chain so that
+         * VFP context is saved.
+         */
+        if (mpu_state == PWRDM_POWER_OFF)
+                cpu_pm_enter();
        /* Execute ARM wfi */
        omap_sram_idle();
+        /*
+         * Call idle CPU PM enter notifier chain to restore
+         * VFP context.
+         */
+        if (pwrdm_read_prev_pwrst(mpu_pd) == PWRDM_POWER_OFF)
+                cpu_pm_exit();
        /* Re-allow idle for C1 */
        if (index == 0) {
                pwrdm_for_each_clkdm(mpu_pd, _cpuidle_allow_idle);
@@ -244,11 +259,6 @@ static int omap3_enter_idle_bm(struct cpuidle_device *dev,
        struct omap3_idle_statedata *cx;
        int ret;
-        if (!omap3_can_sleep()) {
-                new_state_idx = drv->safe_state_index;
-                goto select_state;
-        }
        /*
         * Prevent idle completely if CAM is active.
         * CAM does not have wakeup capability in OMAP3.
diff --git a/arch/arm/mach-omap2/cpuidle44xx.c b/arch/arm/mach-omap2/cpuidle44xx.c
new file mode 100644
index 000000000000..cfdbb86bc84e
--- /dev/null
+++ b/arch/arm/mach-omap2/cpuidle44xx.c
@@ -0,0 +1,245 @@
+/*
+ * OMAP4 CPU idle Routines
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc.
+ * Santosh Shilimkar <santosh.shilimkar@ti.com>
+ * Rajendra Nayak <rnayak@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/sched.h>
+#include <linux/cpuidle.h>
+#include <linux/cpu_pm.h>
+#include <linux/export.h>
+#include <linux/clockchips.h>
+#include <asm/proc-fns.h>
+#include "common.h"
+#include "pm.h"
+#include "prm.h"
+#ifdef CONFIG_CPU_IDLE
+/* Machine specific information to be recorded in the C-state driver_data */
+struct omap4_idle_statedata {
+        u32 cpu_state;
+        u32 mpu_logic_state;
+        u32 mpu_state;
+        u8 valid;
+};
+static struct cpuidle_params cpuidle_params_table[] = {
+        /* C1 - CPU0 ON + CPU1 ON + MPU ON */
+        {.exit_latency = 2 + 2 , .target_residency = 5, .valid = 1},
+        /* C2- CPU0 OFF + CPU1 OFF + MPU CSWR */
+        {.exit_latency = 328 + 440 , .target_residency = 960, .valid = 1},
+        /* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */
+        {.exit_latency = 460 + 518 , .target_residency = 1100, .valid = 1},
+};
+#define OMAP4_NUM_STATES ARRAY_SIZE(cpuidle_params_table)
+struct omap4_idle_statedata omap4_idle_data[OMAP4_NUM_STATES];
+static struct powerdomain *mpu_pd, *cpu0_pd, *cpu1_pd;
+/**
+ * omap4_enter_idle - Programs OMAP4 to enter the specified state
+ * @dev: cpuidle device
+ * @drv: cpuidle driver
+ * @index: the index of state to be entered
+ *
+ * Called from the CPUidle framework to program the device to the
+ * specified low power state selected by the governor.
+ * Returns the amount of time spent in the low power state.
+ */
+static int omap4_enter_idle(struct cpuidle_device *dev,
+                        struct cpuidle_driver *drv,
+                        int index)
+{
+        struct omap4_idle_statedata *cx =
+                        cpuidle_get_statedata(&dev->states_usage[index]);
+        struct timespec ts_preidle, ts_postidle, ts_idle;
+        u32 cpu1_state;
+        int idle_time;
+        int new_state_idx;
+        int cpu_id = smp_processor_id();
+        /* Used to keep track of the total time in idle */
+        getnstimeofday(&ts_preidle);
+        local_irq_disable();
+        local_fiq_disable();
+        /*
+         * CPU0 has to stay ON (i.e in C1) until CPU1 is OFF state.
+         * This is necessary to honour hardware recommondation
+         * of triggeing all the possible low power modes once CPU1 is
+         * out of coherency and in OFF mode.
+         * Update dev->last_state so that governor stats reflects right
+         * data.
+         */
+        cpu1_state = pwrdm_read_pwrst(cpu1_pd);
+        if (cpu1_state != PWRDM_POWER_OFF) {
+                new_state_idx = drv->safe_state_index;
+                cx = cpuidle_get_statedata(&dev->states_usage[new_state_idx]);
+        }
+        if (index > 0)
+                clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu_id);
+        /*
+         * Call idle CPU PM enter notifier chain so that
+         * VFP and per CPU interrupt context is saved.
+         */
+        if (cx->cpu_state == PWRDM_POWER_OFF)
+                cpu_pm_enter();
+        pwrdm_set_logic_retst(mpu_pd, cx->mpu_logic_state);
+        omap_set_pwrdm_state(mpu_pd, cx->mpu_state);
+        /*
+         * Call idle CPU cluster PM enter notifier chain
+         * to save GIC and wakeupgen context.
+         */
+        if ((cx->mpu_state == PWRDM_POWER_RET) &&
+                (cx->mpu_logic_state == PWRDM_POWER_OFF))
+                        cpu_cluster_pm_enter();
+        omap4_enter_lowpower(dev->cpu, cx->cpu_state);
+        /*
+         * Call idle CPU PM exit notifier chain to restore
+         * VFP and per CPU IRQ context. Only CPU0 state is
+         * considered since CPU1 is managed by CPU hotplug.
+         */
+        if (pwrdm_read_prev_pwrst(cpu0_pd) == PWRDM_POWER_OFF)
+                cpu_pm_exit();
+        /*
+         * Call idle CPU cluster PM exit notifier chain
+         * to restore GIC and wakeupgen context.
+         */
+        if (omap4_mpuss_read_prev_context_state())
+                cpu_cluster_pm_exit();
+        if (index > 0)
+                clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu_id);
+        getnstimeofday(&ts_postidle);
+        ts_idle = timespec_sub(ts_postidle, ts_preidle);
+        local_irq_enable();
+        local_fiq_enable();
+        idle_time = ts_idle.tv_nsec / NSEC_PER_USEC + ts_idle.tv_sec * \
+                                                                USEC_PER_SEC;
+        /* Update cpuidle counters */
+        dev->last_residency = idle_time;
+        return index;
+}
+DEFINE_PER_CPU(struct cpuidle_device, omap4_idle_dev);
+struct cpuidle_driver omap4_idle_driver = {
+        .name =         "omap4_idle",
+        .owner =        THIS_MODULE,
+};
+static inline void _fill_cstate(struct cpuidle_driver *drv,
+                                        int idx, const char *descr)
+{
+        struct cpuidle_state *state = &drv->states[idx];
+        state->exit_latency     = cpuidle_params_table[idx].exit_latency;
+        state->target_residency = cpuidle_params_table[idx].target_residency;
+        state->flags            = CPUIDLE_FLAG_TIME_VALID;
+        state->enter            = omap4_enter_idle;
+        sprintf(state->name, "C%d", idx + 1);
+        strncpy(state->desc, descr, CPUIDLE_DESC_LEN);
+}
+static inline struct omap4_idle_statedata *_fill_cstate_usage(
+                                        struct cpuidle_device *dev,
+                                        int idx)
+{
+        struct omap4_idle_statedata *cx = &omap4_idle_data[idx];
+        struct cpuidle_state_usage *state_usage = &dev->states_usage[idx];
+        cx->valid               = cpuidle_params_table[idx].valid;
+        cpuidle_set_statedata(state_usage, cx);
+        return cx;
+}
+/**
+ * omap4_idle_init - Init routine for OMAP4 idle
+ *
+ * Registers the OMAP4 specific cpuidle driver to the cpuidle
+ * framework with the valid set of states.
+ */
+int __init omap4_idle_init(void)
+{
+        struct omap4_idle_statedata *cx;
+        struct cpuidle_device *dev;
+        struct cpuidle_driver *drv = &omap4_idle_driver;
+        unsigned int cpu_id = 0;
+        mpu_pd = pwrdm_lookup("mpu_pwrdm");
+        cpu0_pd = pwrdm_lookup("cpu0_pwrdm");
+        cpu1_pd = pwrdm_lookup("cpu1_pwrdm");
+        if ((!mpu_pd) || (!cpu0_pd) || (!cpu1_pd))
+                return -ENODEV;
+        drv->safe_state_index = -1;
+        dev = &per_cpu(omap4_idle_dev, cpu_id);
+        dev->cpu = cpu_id;
+        /* C1 - CPU0 ON + CPU1 ON + MPU ON */
+        _fill_cstate(drv, 0, "MPUSS ON");
+        drv->safe_state_index = 0;
+        cx = _fill_cstate_usage(dev, 0);
+        cx->valid = 1;  /* C1 is always valid */
+        cx->cpu_state = PWRDM_POWER_ON;
+        cx->mpu_state = PWRDM_POWER_ON;
+        cx->mpu_logic_state = PWRDM_POWER_RET;
+        /* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */
+        _fill_cstate(drv, 1, "MPUSS CSWR");
+        cx = _fill_cstate_usage(dev, 1);
+        cx->cpu_state = PWRDM_POWER_OFF;
+        cx->mpu_state = PWRDM_POWER_RET;
+        cx->mpu_logic_state = PWRDM_POWER_RET;
+        /* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */
+        _fill_cstate(drv, 2, "MPUSS OSWR");
+        cx = _fill_cstate_usage(dev, 2);
+        cx->cpu_state = PWRDM_POWER_OFF;
+        cx->mpu_state = PWRDM_POWER_RET;
+        cx->mpu_logic_state = PWRDM_POWER_OFF;
+        drv->state_count = OMAP4_NUM_STATES;
+        cpuidle_register_driver(&omap4_idle_driver);
+        dev->state_count = OMAP4_NUM_STATES;
+        if (cpuidle_register_device(dev)) {
+                pr_err("%s: CPUidle register device failed\n", __func__);
+                        return -EIO;
+                }
+        return 0;
+}
+#else
+int __init omap4_idle_init(void)
+{
+        return 0;
+}
+#endif /* CONFIG_CPU_IDLE */
diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c
index dce9905d64bb..bc6cf863a563 100644
--- a/arch/arm/mach-omap2/display.c
+++ b/arch/arm/mach-omap2/display.c
@@ -22,12 +22,13 @@
 #include <linux/io.h>
 #include <linux/clk.h>
 #include <linux/err.h>
+#include <linux/delay.h>
 #include <video/omapdss.h>
 #include <plat/omap_hwmod.h>
 #include <plat/omap_device.h>
 #include <plat/omap-pm.h>
-#include <plat/common.h>
+#include "common.h"
 #include "control.h"
 #include "display.h"
diff --git a/arch/arm/mach-omap2/i2c.c b/arch/arm/mach-omap2/i2c.c
index ace99944e96f..a12e224eb97d 100644
--- a/arch/arm/mach-omap2/i2c.c
+++ b/arch/arm/mach-omap2/i2c.c
@@ -21,7 +21,7 @@
 #include <plat/cpu.h>
 #include <plat/i2c.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/omap_hwmod.h>
 #include "mux.h"
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 7f47092a193f..6c5826605eae 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -21,7 +21,7 @@
 #include <asm/cputype.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/cpu.h>
 #include <mach/id.h>
@@ -226,7 +226,7 @@ static void __init omap4_check_features(void)
        }
 }
-static void __init ti816x_check_features(void)
+static void __init ti81xx_check_features(void)
 {
        omap_features = OMAP3_HAS_NEON;
 }
@@ -340,6 +340,29 @@ static void __init omap3_check_revision(const char **cpu_rev)
                        break;
                }
                break;
+        case 0xb944:
+                omap_revision = AM335X_REV_ES1_0;
+                *cpu_rev = "1.0";
+        case 0xb8f2:
+                switch (rev) {
+                case 0:
+                /* FALLTHROUGH */
+                case 1:
+                        omap_revision = TI8148_REV_ES1_0;
+                        *cpu_rev = "1.0";
+                        break;
+                case 2:
+                        omap_revision = TI8148_REV_ES2_0;
+                        *cpu_rev = "2.0";
+                        break;
+                case 3:
+                /* FALLTHROUGH */
+                default:
+                        omap_revision = TI8148_REV_ES2_1;
+                        *cpu_rev = "2.1";
+                        break;
+                }
+                break;
        default:
                /* Unknown default to latest silicon rev as default */
                omap_revision = OMAP3630_REV_ES1_2;
@@ -367,7 +390,7 @@ static void __init omap4_check_revision(void)
         * Few initial 4430 ES2.0 samples IDCODE is same as ES1.0
         * Use ARM register to detect the correct ES version
         */
-        if (!rev && (hawkeye != 0xb94e)) {
+        if (!rev && (hawkeye != 0xb94e) && (hawkeye != 0xb975)) {
                idcode = read_cpuid(CPUID_ID);
                rev = (idcode & 0xf) - 1;
        }
@@ -389,8 +412,11 @@ static void __init omap4_check_revision(void)
                        omap_revision = OMAP4430_REV_ES2_1;
                        break;
                case 4:
-                default:
                        omap_revision = OMAP4430_REV_ES2_2;
+                        break;
+                case 6:
+                default:
+                        omap_revision = OMAP4430_REV_ES2_3;
                }
                break;
        case 0xb94e:
@@ -401,9 +427,17 @@ static void __init omap4_check_revision(void)
                        break;
                }
                break;
+        case 0xb975:
+                switch (rev) {
+                case 0:
+                default:
+                        omap_revision = OMAP4470_REV_ES1_0;
+                        break;
+                }
+                break;
        default:
                /* Unknown default to latest silicon rev as default */
-                omap_revision = OMAP4430_REV_ES2_2;
+                omap_revision = OMAP4430_REV_ES2_3;
        }
        pr_info("OMAP%04x ES%d.%d\n", omap_rev() >> 16,
@@ -432,6 +466,10 @@ static void __init omap3_cpuinfo(const char *cpu_rev)
                cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505";
        } else if (cpu_is_ti816x()) {
                cpu_name = "TI816X";
+        } else if (cpu_is_am335x()) {
+                cpu_name =  "AM335X";
+        } else if (cpu_is_ti814x()) {
+                cpu_name = "TI814X";
        } else if (omap3_has_iva() && omap3_has_sgx()) {
                /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
                cpu_name = "OMAP3430/3530";
@@ -472,11 +510,11 @@ void __init omap2_check_revision(void)
        } else if (cpu_is_omap34xx()) {
                omap3_check_revision(&cpu_rev);
-                /* TI816X doesn't have feature register */
+                /* TI81XX doesn't have feature register */
-                if (!cpu_is_ti816x())
+                if (!cpu_is_ti81xx())
                        omap3_check_features();
                else
-                        ti816x_check_features();
+                        ti81xx_check_features();
                omap3_cpuinfo(cpu_rev);
                return;
diff --git a/arch/arm/mach-netx/include/mach/vmalloc.h b/arch/arm/mach-omap2/include/mach/barriers.h
index 871f1ef7bff5..4fa72c7cc7cd 100644
--- a/arch/arm/mach-netx/include/mach/vmalloc.h
+++ b/arch/arm/mach-omap2/include/mach/barriers.h
@@ -1,11 +1,13 @@
 /*
- *  arch/arm/mach-netx/include/mach/vmalloc.h
+ * OMAP memory barrier header.
 *
- * Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
+ * Copyright (C) 2011 Texas Instruments, Inc.
+ *  Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *  Richard Woodruff <r-woodruff2@ti.com>
 *
 * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2
+ * it under the terms of the GNU General Public License version 2 as
- * as published by the Free Software Foundation.
+ * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
@@ -14,6 +16,16 @@
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 */
-#define VMALLOC_END       0xd0000000UL
+#ifndef __MACH_BARRIERS_H
+#define __MACH_BARRIERS_H
+extern void omap_bus_sync(void);
+#define rmb()           dsb()
+#define wmb()           do { dsb(); outer_sync(); omap_bus_sync(); } while (0)
+#define mb()            wmb()
+#endif  /* __MACH_BARRIERS_H */
diff --git a/arch/arm/mach-omap2/include/mach/debug-macro.S b/arch/arm/mach-omap2/include/mach/debug-macro.S
index 13f98e59cfef..cdfc2a1f0e75 100644
--- a/arch/arm/mach-omap2/include/mach/debug-macro.S
+++ b/arch/arm/mach-omap2/include/mach/debug-macro.S
@@ -66,11 +66,11 @@ omap_uart_lsr:	.word	0
                beq     34f                     @ configure OMAP3UART4
                cmp     \rp, #OMAP4UART4        @ only on 44xx
                beq     44f                     @ configure OMAP4UART4
-                cmp     \rp, #TI816XUART1       @ ti816x UART offsets different
+                cmp     \rp, #TI81XXUART1       @ ti81Xx UART offsets different
                beq     81f                     @ configure UART1
-                cmp     \rp, #TI816XUART2       @ ti816x UART offsets different
+                cmp     \rp, #TI81XXUART2       @ ti81Xx UART offsets different
                beq     82f                     @ configure UART2
-                cmp     \rp, #TI816XUART3       @ ti816x UART offsets different
+                cmp     \rp, #TI81XXUART3       @ ti81Xx UART offsets different
                beq     83f                     @ configure UART3
                cmp     \rp, #ZOOM_UART         @ only on zoom2/3
                beq     95f                     @ configure ZOOM_UART
@@ -94,11 +94,11 @@ omap_uart_lsr:	.word	0
                b       98f
 44:             mov     \rp, #UART_OFFSET(OMAP4_UART4_BASE)
                b       98f
-81:             mov     \rp, #UART_OFFSET(TI816X_UART1_BASE)
+81:             mov     \rp, #UART_OFFSET(TI81XX_UART1_BASE)
                b       98f
-82:             mov     \rp, #UART_OFFSET(TI816X_UART2_BASE)
+82:             mov     \rp, #UART_OFFSET(TI81XX_UART2_BASE)
                b       98f
-83:             mov     \rp, #UART_OFFSET(TI816X_UART3_BASE)
+83:             mov     \rp, #UART_OFFSET(TI81XX_UART3_BASE)
                b       98f
 95:             ldr     \rp, =ZOOM_UART_BASE
diff --git a/arch/arm/mach-omap2/include/mach/entry-macro.S b/arch/arm/mach-omap2/include/mach/entry-macro.S
index feb90a10945a..56964a0c4c7e 100644
--- a/arch/arm/mach-omap2/include/mach/entry-macro.S
+++ b/arch/arm/mach-omap2/include/mach/entry-macro.S
@@ -10,146 +10,9 @@
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */
-#include <mach/hardware.h>
-#include <mach/io.h>
-#include <mach/irqs.h>
-#include <asm/hardware/gic.h>
-#include <plat/omap24xx.h>
-#include <plat/omap34xx.h>
-#include <plat/omap44xx.h>
-#include <plat/multi.h>
-#define OMAP2_IRQ_BASE          OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE)
-#define OMAP3_IRQ_BASE          OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE)
-#define OMAP4_IRQ_BASE          OMAP2_L4_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE)
-#define INTCPS_SIR_IRQ_OFFSET   0x0040  /* omap2/3 active interrupt offset */
-#define ACTIVEIRQ_MASK          0x7f    /* omap2/3 active interrupt bits */
                .macro  disable_fiq
                .endm
                .macro  arch_ret_to_user, tmp1, tmp2
                .endm
-/*
- * Unoptimized irq functions for multi-omap2, 3 and 4
- */
-#ifdef MULTI_OMAP2
-                /*
-                 * Configure the interrupt base on the first interrupt.
-                 * See also omap_irq_base_init for setting omap_irq_base.
-                 */
-                .macro  get_irqnr_preamble, base, tmp
-                ldr     \base, =omap_irq_base   @ irq base address
-                ldr     \base, [\base, #0]      @ irq base value
-                .endm
-                /* Check the pending interrupts. Note that base already set */
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-                tst     \base, #0x100           @ gic address?
-                bne     4401f                   @ found gic
-                /* Handle omap2 and omap3 */
-                ldr     \irqnr, [\base, #0x98] /* IRQ pending reg 1 */
-                cmp     \irqnr, #0x0
-                bne     9998f
-                ldr     \irqnr, [\base, #0xb8] /* IRQ pending reg 2 */
-                cmp     \irqnr, #0x0
-                bne     9998f
-                ldr     \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */
-                cmp     \irqnr, #0x0
-                bne     9998f
-                /*
-                 * ti816x has additional IRQ pending register. Checking this
-                 * register on omap2 & omap3 has no effect (read as 0).
-                 */
-                ldr     \irqnr, [\base, #0xf8] /* IRQ pending reg 4 */
-                cmp     \irqnr, #0x0
-9998:
-                ldrne   \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET]
-                and     \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */
-                b       9999f
-                /* Handle omap4 */
-4401:           ldr     \irqstat, [\base, #GIC_CPU_INTACK]
-                ldr     \tmp, =1021
-                bic     \irqnr, \irqstat, #0x1c00
-                cmp     \irqnr, #15
-                cmpcc   \irqnr, \irqnr
-                cmpne   \irqnr, \tmp
-                cmpcs   \irqnr, \irqnr
-9999:
-                .endm
-#ifdef CONFIG_SMP
-                /* We assume that irqstat (the raw value of the IRQ acknowledge
-                 * register) is preserved from the macro above.
-                 * If there is an IPI, we immediately signal end of interrupt
-                 * on the controller, since this requires the original irqstat
-                 * value which we won't easily be able to recreate later.
-                 */
-                .macro test_for_ipi, irqnr, irqstat, base, tmp
-                bic     \irqnr, \irqstat, #0x1c00
-                cmp     \irqnr, #16
-                it      cc
-                strcc   \irqstat, [\base, #GIC_CPU_EOI]
-                it      cs
-                cmpcs   \irqnr, \irqnr
-                .endm
-#endif  /* CONFIG_SMP */
-#else   /* MULTI_OMAP2 */
-/*
- * Optimized irq functions for omap2, 3 and 4
- */
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
-                .macro  get_irqnr_preamble, base, tmp
-#ifdef CONFIG_ARCH_OMAP2
-                ldr     \base, =OMAP2_IRQ_BASE
-#else
-                ldr     \base, =OMAP3_IRQ_BASE
-#endif
-                .endm
-                /* Check the pending interrupts. Note that base already set */
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-                ldr     \irqnr, [\base, #0x98] /* IRQ pending reg 1 */
-                cmp     \irqnr, #0x0
-                bne     9999f
-                ldr     \irqnr, [\base, #0xb8] /* IRQ pending reg 2 */
-                cmp     \irqnr, #0x0
-                bne     9999f
-                ldr     \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */
-                cmp     \irqnr, #0x0
-#ifdef CONFIG_SOC_OMAPTI816X
-                bne     9999f
-                ldr     \irqnr, [\base, #0xf8] /* IRQ pending reg 4 */
-                cmp     \irqnr, #0x0
-#endif
-9999:
-                ldrne   \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET]
-                and     \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */
-                .endm
-#endif
-#ifdef CONFIG_ARCH_OMAP4
-#define HAVE_GET_IRQNR_PREAMBLE
-#include <asm/hardware/entry-macro-gic.S>
-                .macro  get_irqnr_preamble, base, tmp
-                ldr     \base, =OMAP4_IRQ_BASE
-                .endm
-#endif
-#endif  /* MULTI_OMAP2 */
diff --git a/arch/arm/mach-omap2/include/mach/omap-secure.h b/arch/arm/mach-omap2/include/mach/omap-secure.h
new file mode 100644
index 000000000000..c90a43589abe
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/omap-secure.h
@@ -0,0 +1,57 @@
+/*
+ * omap-secure.h: OMAP Secure infrastructure header.
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc.
+ *      Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef OMAP_ARCH_OMAP_SECURE_H
+#define OMAP_ARCH_OMAP_SECURE_H
+/* Monitor error code */
+#define  API_HAL_RET_VALUE_NS2S_CONVERSION_ERROR        0xFFFFFFFE
+#define  API_HAL_RET_VALUE_SERVICE_UNKNWON              0xFFFFFFFF
+/* HAL API error codes */
+#define  API_HAL_RET_VALUE_OK           0x00
+#define  API_HAL_RET_VALUE_FAIL         0x01
+/* Secure HAL API flags */
+#define FLAG_START_CRITICAL             0x4
+#define FLAG_IRQFIQ_MASK                0x3
+#define FLAG_IRQ_ENABLE                 0x2
+#define FLAG_FIQ_ENABLE                 0x1
+#define NO_FLAG                         0x0
+/* Maximum Secure memory storage size */
+#define OMAP_SECURE_RAM_STORAGE (88 * SZ_1K)
+/* Secure low power HAL API index */
+#define OMAP4_HAL_SAVESECURERAM_INDEX   0x1a
+#define OMAP4_HAL_SAVEHW_INDEX          0x1b
+#define OMAP4_HAL_SAVEALL_INDEX         0x1c
+#define OMAP4_HAL_SAVEGIC_INDEX         0x1d
+/* Secure Monitor mode APIs */
+#define OMAP4_MON_SCU_PWR_INDEX         0x108
+#define OMAP4_MON_L2X0_DBG_CTRL_INDEX   0x100
+#define OMAP4_MON_L2X0_CTRL_INDEX       0x102
+#define OMAP4_MON_L2X0_AUXCTRL_INDEX    0x109
+#define OMAP4_MON_L2X0_PREFETCH_INDEX   0x113
+/* Secure PPA(Primary Protected Application) APIs */
+#define OMAP4_PPA_L2_POR_INDEX          0x23
+#define OMAP4_PPA_CPU_ACTRL_SMP_INDEX   0x25
+#ifndef __ASSEMBLER__
+extern u32 omap_secure_dispatcher(u32 idx, u32 flag, u32 nargs,
+                                u32 arg1, u32 arg2, u32 arg3, u32 arg4);
+extern u32 omap_smc2(u32 id, u32 falg, u32 pargs);
+extern phys_addr_t omap_secure_ram_mempool_base(void);
+#endif /* __ASSEMBLER__ */
+#endif /* OMAP_ARCH_OMAP_SECURE_H */
diff --git a/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h b/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h
new file mode 100644
index 000000000000..d79321b0f2a2
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h
@@ -0,0 +1,39 @@
+/*
+ * OMAP WakeupGen header file
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc.
+ *      Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef OMAP_ARCH_WAKEUPGEN_H
+#define OMAP_ARCH_WAKEUPGEN_H
+#define OMAP_WKG_CONTROL_0                      0x00
+#define OMAP_WKG_ENB_A_0                        0x10
+#define OMAP_WKG_ENB_B_0                        0x14
+#define OMAP_WKG_ENB_C_0                        0x18
+#define OMAP_WKG_ENB_D_0                        0x1c
+#define OMAP_WKG_ENB_SECURE_A_0                 0x20
+#define OMAP_WKG_ENB_SECURE_B_0                 0x24
+#define OMAP_WKG_ENB_SECURE_C_0                 0x28
+#define OMAP_WKG_ENB_SECURE_D_0                 0x2c
+#define OMAP_WKG_ENB_A_1                        0x410
+#define OMAP_WKG_ENB_B_1                        0x414
+#define OMAP_WKG_ENB_C_1                        0x418
+#define OMAP_WKG_ENB_D_1                        0x41c
+#define OMAP_WKG_ENB_SECURE_A_1                 0x420
+#define OMAP_WKG_ENB_SECURE_B_1                 0x424
+#define OMAP_WKG_ENB_SECURE_C_1                 0x428
+#define OMAP_WKG_ENB_SECURE_D_1                 0x42c
+#define OMAP_AUX_CORE_BOOT_0                    0x800
+#define OMAP_AUX_CORE_BOOT_1                    0x804
+#define OMAP_PTMSYNCREQ_MASK                    0xc00
+#define OMAP_PTMSYNCREQ_EN                      0xc04
+#define OMAP_TIMESTAMPCYCLELO                   0xc08
+#define OMAP_TIMESTAMPCYCLEHI                   0xc0c
+extern int __init omap_wakeupgen_init(void);
+#endif
diff --git a/arch/arm/mach-omap2/include/mach/omap4-common.h b/arch/arm/mach-omap2/include/mach/omap4-common.h
deleted file mode 100644
index e4bd87619734..000000000000
--- a/arch/arm/mach-omap2/include/mach/omap4-common.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * omap4-common.h: OMAP4 specific common header file
- *
- * Copyright (C) 2010 Texas Instruments, Inc.
- *
- * Author:
- *      Santosh Shilimkar <santosh.shilimkar@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef OMAP_ARCH_OMAP4_COMMON_H
-#define OMAP_ARCH_OMAP4_COMMON_H
-/*
- * wfi used in low power code. Directly opcode is used instead
- * of instruction to avoid mulit-omap build break
- */
-#ifdef CONFIG_THUMB2_KERNEL
-#define do_wfi() __asm__ __volatile__ ("wfi" : : : "memory")
-#else
-#define do_wfi()                        \
-                __asm__ __volatile__ (".word    0xe320f003" : : : "memory")
-#endif
-#ifdef CONFIG_CACHE_L2X0
-extern void __iomem *l2cache_base;
-#endif
-extern void __iomem *gic_dist_base_addr;
-extern void __init gic_init_irq(void);
-extern void omap_smc1(u32 fn, u32 arg);
-#ifdef CONFIG_SMP
-/* Needed for secondary core boot */
-extern void omap_secondary_startup(void);
-extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
-extern void omap_auxcoreboot_addr(u32 cpu_addr);
-extern u32 omap_read_auxcoreboot0(void);
-#endif
-#endif
diff --git a/arch/arm/mach-omap2/include/mach/vmalloc.h b/arch/arm/mach-omap2/include/mach/vmalloc.h
deleted file mode 100644
index 866319947760..000000000000
--- a/arch/arm/mach-omap2/include/mach/vmalloc.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- *  arch/arm/plat-omap/include/mach/vmalloc.h
- *
- *  Copyright (C) 2000 Russell King.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#define VMALLOC_END       0xf8000000UL
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 25d20ced03e1..3f174d51f67f 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -35,7 +35,7 @@
 #include "clock3xxx.h"
 #include "clock44xx.h"
-#include <plat/common.h>
+#include "common.h"
 #include <plat/omap-pm.h>
 #include "voltage.h"
 #include "powerdomain.h"
@@ -43,7 +43,7 @@
 #include "clockdomain.h"
 #include <plat/omap_hwmod.h>
 #include <plat/multi.h>
-#include <plat/common.h>
+#include "common.h"
 /*
 * The machine specific code may provide the extra mapping besides the
@@ -176,14 +176,31 @@ static struct map_desc omap34xx_io_desc[] __initdata = {
 };
 #endif
-#ifdef CONFIG_SOC_OMAPTI816X
+#ifdef CONFIG_SOC_OMAPTI81XX
-static struct map_desc omapti816x_io_desc[] __initdata = {
+static struct map_desc omapti81xx_io_desc[] __initdata = {
+        {
+                .virtual        = L4_34XX_VIRT,
+                .pfn            = __phys_to_pfn(L4_34XX_PHYS),
+                .length         = L4_34XX_SIZE,
+                .type           = MT_DEVICE
+        }
+};
+#endif
+#ifdef CONFIG_SOC_OMAPAM33XX
+static struct map_desc omapam33xx_io_desc[] __initdata = {
        {
                .virtual        = L4_34XX_VIRT,
                .pfn            = __phys_to_pfn(L4_34XX_PHYS),
                .length         = L4_34XX_SIZE,
                .type           = MT_DEVICE
        },
+        {
+                .virtual        = L4_WK_AM33XX_VIRT,
+                .pfn            = __phys_to_pfn(L4_WK_AM33XX_PHYS),
+                .length         = L4_WK_AM33XX_SIZE,
+                .type           = MT_DEVICE
+        }
 };
 #endif
@@ -237,6 +254,15 @@ static struct map_desc omap44xx_io_desc[] __initdata = {
                .length         = L4_EMU_44XX_SIZE,
                .type           = MT_DEVICE,
        },
+#ifdef CONFIG_OMAP4_ERRATA_I688
+        {
+                .virtual        = OMAP4_SRAM_VA,
+                .pfn            = __phys_to_pfn(OMAP4_SRAM_PA),
+                .length         = PAGE_SIZE,
+                .type           = MT_MEMORY_SO,
+        },
+#endif
 };
 #endif
@@ -263,10 +289,17 @@ void __init omap34xx_map_common_io(void)
 }
 #endif
-#ifdef CONFIG_SOC_OMAPTI816X
+#ifdef CONFIG_SOC_OMAPTI81XX
-void __init omapti816x_map_common_io(void)
+void __init omapti81xx_map_common_io(void)
 {
-        iotable_init(omapti816x_io_desc, ARRAY_SIZE(omapti816x_io_desc));
+        iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc));
+}
+#endif
+#ifdef CONFIG_SOC_OMAPAM33XX
+void __init omapam33xx_map_common_io(void)
+{
+        iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
 }
 #endif
@@ -316,13 +349,9 @@ static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
        return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
 }
-/* See irq.c, omap4-common.c and entry-macro.S */
-void __iomem *omap_irq_base;
 static void __init omap_common_init_early(void)
 {
        omap2_check_revision();
-        omap_ioremap_init();
        omap_init_consistent_dma_size();
 }
@@ -422,9 +451,9 @@ void __init am35xx_init_early(void)
        omap3_init_early();
 }
-void __init ti816x_init_early(void)
+void __init ti81xx_init_early(void)
 {
-        omap2_set_globals_ti816x();
+        omap2_set_globals_ti81xx();
        omap_common_init_early();
        omap3xxx_voltagedomains_init();
        omap3xxx_powerdomains_init();
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index 65f1be6a182c..1fef061f7927 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -15,6 +15,7 @@
 #include <linux/interrupt.h>
 #include <linux/io.h>
 #include <mach/hardware.h>
+#include <asm/exception.h>
 #include <asm/mach/irq.h>
@@ -35,6 +36,11 @@
 /* Number of IRQ state bits in each MIR register */
 #define IRQ_BITS_PER_REG        32
+#define OMAP2_IRQ_BASE          OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE)
+#define OMAP3_IRQ_BASE          OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE)
+#define INTCPS_SIR_IRQ_OFFSET   0x0040  /* omap2/3 active interrupt offset */
+#define ACTIVEIRQ_MASK          0x7f    /* omap2/3 active interrupt bits */
 /*
 * OMAP2 has a number of different interrupt controllers, each interrupt
 * controller is identified as its own "bank". Register definitions are
@@ -143,6 +149,7 @@ omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
 static void __init omap_init_irq(u32 base, int nr_irqs)
 {
+        void __iomem *omap_irq_base;
        unsigned long nr_of_irqs = 0;
        unsigned int nr_banks = 0;
        int i, j;
@@ -186,11 +193,49 @@ void __init omap3_init_irq(void)
        omap_init_irq(OMAP34XX_IC_BASE, 96);
 }
-void __init ti816x_init_irq(void)
+void __init ti81xx_init_irq(void)
 {
        omap_init_irq(OMAP34XX_IC_BASE, 128);
 }
+static inline void omap_intc_handle_irq(void __iomem *base_addr, struct pt_regs *regs)
+{
+        u32 irqnr;
+        do {
+                irqnr = readl_relaxed(base_addr + 0x98);
+                if (irqnr)
+                        goto out;
+                irqnr = readl_relaxed(base_addr + 0xb8);
+                if (irqnr)
+                        goto out;
+                irqnr = readl_relaxed(base_addr + 0xd8);
+#ifdef CONFIG_SOC_OMAPTI816X
+                if (irqnr)
+                        goto out;
+                irqnr = readl_relaxed(base_addr + 0xf8);
+#endif
+out:
+                if (!irqnr)
+                        break;
+                irqnr = readl_relaxed(base_addr + INTCPS_SIR_IRQ_OFFSET);
+                irqnr &= ACTIVEIRQ_MASK;
+                if (irqnr)
+                        handle_IRQ(irqnr, regs);
+        } while (irqnr);
+}
+asmlinkage void __exception_irq_entry omap2_intc_handle_irq(struct pt_regs *regs)
+{
+        void __iomem *base_addr = OMAP2_IRQ_BASE;
+        omap_intc_handle_irq(base_addr, regs);
+}
 #ifdef CONFIG_ARCH_OMAP3
 static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)];
@@ -263,4 +308,10 @@ void omap3_intc_resume_idle(void)
        /* Re-enable autoidle */
        intc_bank_write_reg(1, &irq_banks[0], INTC_SYSCONFIG);
 }
+asmlinkage void __exception_irq_entry omap3_intc_handle_irq(struct pt_regs *regs)
+{
+        void __iomem *base_addr = OMAP3_IRQ_BASE;
+        omap_intc_handle_irq(base_addr, regs);
+}
 #endif /* CONFIG_ARCH_OMAP3 */
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 655e9480eb98..e1cc75d1a57a 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -32,6 +32,8 @@
 #include <linux/debugfs.h>
 #include <linux/seq_file.h>
 #include <linux/uaccess.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
 #include <asm/system.h>
@@ -39,6 +41,7 @@
 #include "control.h"
 #include "mux.h"
+#include "prm.h"
 #define OMAP_MUX_BASE_OFFSET            0x30    /* Offset from CTRL_BASE */
 #define OMAP_MUX_BASE_SZ                0x5ca
@@ -306,7 +309,8 @@ omap_hwmod_mux_init(struct omap_device_pad *bpads, int nr_pads)
                pad->idle = bpad->idle;
                pad->off = bpad->off;
-                if (pad->flags & OMAP_DEVICE_PAD_REMUX)
+                if (pad->flags &
+                    (OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP))
                        nr_pads_dynamic++;
                pr_debug("%s: Initialized %s\n", __func__, pad->name);
@@ -331,7 +335,8 @@ omap_hwmod_mux_init(struct omap_device_pad *bpads, int nr_pads)
        for (i = 0; i < hmux->nr_pads; i++) {
                struct omap_device_pad *pad = &hmux->pads[i];
-                if (pad->flags & OMAP_DEVICE_PAD_REMUX) {
+                if (pad->flags &
+                    (OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP)) {
                        pr_debug("%s: pad %s tagged dynamic\n",
                                        __func__, pad->name);
                        hmux->pads_dynamic[nr_pads_dynamic] = pad;
@@ -351,6 +356,78 @@ err1:
        return NULL;
 }
+/**
+ * omap_hwmod_mux_scan_wakeups - omap hwmod scan wakeup pads
+ * @hmux: Pads for a hwmod
+ * @mpu_irqs: MPU irq array for a hwmod
+ *
+ * Scans the wakeup status of pads for a single hwmod.  If an irq
+ * array is defined for this mux, the parser will call the registered
+ * ISRs for corresponding pads, otherwise the parser will stop at the
+ * first wakeup active pad and return.  Returns true if there is a
+ * pending and non-served wakeup event for the mux, otherwise false.
+ */
+static bool omap_hwmod_mux_scan_wakeups(struct omap_hwmod_mux_info *hmux,
+                struct omap_hwmod_irq_info *mpu_irqs)
+{
+        int i, irq;
+        unsigned int val;
+        u32 handled_irqs = 0;
+        for (i = 0; i < hmux->nr_pads_dynamic; i++) {
+                struct omap_device_pad *pad = hmux->pads_dynamic[i];
+                if (!(pad->flags & OMAP_DEVICE_PAD_WAKEUP) ||
+                    !(pad->idle & OMAP_WAKEUP_EN))
+                        continue;
+                val = omap_mux_read(pad->partition, pad->mux->reg_offset);
+                if (!(val & OMAP_WAKEUP_EVENT))
+                        continue;
+                if (!hmux->irqs)
+                        return true;
+                irq = hmux->irqs[i];
+                /* make sure we only handle each irq once */
+                if (handled_irqs & 1 << irq)
+                        continue;
+                handled_irqs |= 1 << irq;
+                generic_handle_irq(mpu_irqs[irq].irq);
+        }
+        return false;
+}
+/**
+ * _omap_hwmod_mux_handle_irq - Process wakeup events for a single hwmod
+ *
+ * Checks a single hwmod for every wakeup capable pad to see if there is an
+ * active wakeup event. If this is the case, call the corresponding ISR.
+ */
+static int _omap_hwmod_mux_handle_irq(struct omap_hwmod *oh, void *data)
+{
+        if (!oh->mux || !oh->mux->enabled)
+                return 0;
+        if (omap_hwmod_mux_scan_wakeups(oh->mux, oh->mpu_irqs))
+                generic_handle_irq(oh->mpu_irqs[0].irq);
+        return 0;
+}
+/**
+ * omap_hwmod_mux_handle_irq - Process pad wakeup irqs.
+ *
+ * Calls a function for each registered omap_hwmod to check
+ * pad wakeup statuses.
+ */
+static irqreturn_t omap_hwmod_mux_handle_irq(int irq, void *unused)
+{
+        omap_hwmod_for_each(_omap_hwmod_mux_handle_irq, NULL);
+        return IRQ_HANDLED;
+}
 /* Assumes the calling function takes care of locking */
 void omap_hwmod_mux(struct omap_hwmod_mux_info *hmux, u8 state)
 {
@@ -715,6 +792,7 @@ static void __init omap_mux_free_names(struct omap_mux *m)
 static int __init omap_mux_late_init(void)
 {
        struct omap_mux_partition *partition;
+        int ret;
        list_for_each_entry(partition, &mux_partitions, node) {
                struct omap_mux_entry *e, *tmp;
@@ -735,6 +813,13 @@ static int __init omap_mux_late_init(void)
                }
        }
+        ret = request_irq(omap_prcm_event_to_irq("io"),
+                omap_hwmod_mux_handle_irq, IRQF_SHARED | IRQF_NO_SUSPEND,
+                        "hwmod_io", omap_mux_late_init);
+        if (ret)
+                pr_warning("mux: Failed to setup hwmod io irq %d\n", ret);
        omap_mux_dbg_init();
        return 0;
diff --git a/arch/arm/mach-omap2/omap-headsmp.S b/arch/arm/mach-omap2/omap-headsmp.S
index 4ee6aeca885a..b13ef7ef5ef4 100644
--- a/arch/arm/mach-omap2/omap-headsmp.S
+++ b/arch/arm/mach-omap2/omap-headsmp.S
@@ -18,11 +18,6 @@
 #include <linux/linkage.h>
 #include <linux/init.h>
-/* Physical address needed since MMU not enabled yet on secondary core */
-#define OMAP4_AUX_CORE_BOOT1_PA                 0x48281804
-        __INIT
 /*
 * OMAP4 specific entry point for secondary CPU to jump from ROM
 * code.  This routine also provides a holding flag into which
diff --git a/arch/arm/mach-omap2/omap-hotplug.c b/arch/arm/mach-omap2/omap-hotplug.c
index 4976b9393e49..adbe4d8c7caf 100644
--- a/arch/arm/mach-omap2/omap-hotplug.c
+++ b/arch/arm/mach-omap2/omap-hotplug.c
@@ -19,7 +19,10 @@
 #include <linux/smp.h>
 #include <asm/cacheflush.h>
-#include <mach/omap4-common.h>
+#include "common.h"
+#include "powerdomain.h"
 int platform_cpu_kill(unsigned int cpu)
 {
@@ -32,6 +35,8 @@ int platform_cpu_kill(unsigned int cpu)
 */
 void platform_cpu_die(unsigned int cpu)
 {
+        unsigned int this_cpu;
        flush_cache_all();
        dsb();
@@ -39,15 +44,15 @@ void platform_cpu_die(unsigned int cpu)
         * we're ready for shutdown now, so do it
         */
        if (omap_modify_auxcoreboot0(0x0, 0x200) != 0x0)
-                printk(KERN_CRIT "Secure clear status failed\n");
+                pr_err("Secure clear status failed\n");
        for (;;) {
                /*
-                 * Execute WFI
+                 * Enter into low power state
                 */
-                do_wfi();
+                omap4_hotplug_cpu(cpu, PWRDM_POWER_OFF);
+                this_cpu = smp_processor_id();
-                if (omap_read_auxcoreboot0() == cpu) {
+                if (omap_read_auxcoreboot0() == this_cpu) {
                        /*
                         * OK, proper wakeup, we're done
                         */
diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
new file mode 100644
index 000000000000..1d5d01056558
--- /dev/null
+++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
@@ -0,0 +1,398 @@
+/*
+ * OMAP MPUSS low power code
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc.
+ *      Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ * OMAP4430 MPUSS mainly consists of dual Cortex-A9 with per-CPU
+ * Local timer and Watchdog, GIC, SCU, PL310 L2 cache controller,
+ * CPU0 and CPU1 LPRM modules.
+ * CPU0, CPU1 and MPUSS each have there own power domain and
+ * hence multiple low power combinations of MPUSS are possible.
+ *
+ * The CPU0 and CPU1 can't support Closed switch Retention (CSWR)
+ * because the mode is not supported by hw constraints of dormant
+ * mode. While waking up from the dormant mode, a reset  signal
+ * to the Cortex-A9 processor must be asserted by the external
+ * power controller.
+ *
+ * With architectural inputs and hardware recommendations, only
+ * below modes are supported from power gain vs latency point of view.
+ *
+ *      CPU0            CPU1            MPUSS
+ *      ----------------------------------------------
+ *      ON              ON              ON
+ *      ON(Inactive)    OFF             ON(Inactive)
+ *      OFF             OFF             CSWR
+ *      OFF             OFF             OSWR
+ *      OFF             OFF             OFF(Device OFF *TBD)
+ *      ----------------------------------------------
+ *
+ * Note: CPU0 is the master core and it is the last CPU to go down
+ * and first to wake-up when MPUSS low power states are excercised
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/errno.h>
+#include <linux/linkage.h>
+#include <linux/smp.h>
+#include <asm/cacheflush.h>
+#include <asm/tlbflush.h>
+#include <asm/smp_scu.h>
+#include <asm/system.h>
+#include <asm/pgalloc.h>
+#include <asm/suspend.h>
+#include <asm/hardware/cache-l2x0.h>
+#include <plat/omap44xx.h>
+#include "common.h"
+#include "omap4-sar-layout.h"
+#include "pm.h"
+#include "prcm_mpu44xx.h"
+#include "prminst44xx.h"
+#include "prcm44xx.h"
+#include "prm44xx.h"
+#include "prm-regbits-44xx.h"
+#ifdef CONFIG_SMP
+struct omap4_cpu_pm_info {
+        struct powerdomain *pwrdm;
+        void __iomem *scu_sar_addr;
+        void __iomem *wkup_sar_addr;
+        void __iomem *l2x0_sar_addr;
+};
+static DEFINE_PER_CPU(struct omap4_cpu_pm_info, omap4_pm_info);
+static struct powerdomain *mpuss_pd;
+static void __iomem *sar_base;
+/*
+ * Program the wakeup routine address for the CPU0 and CPU1
+ * used for OFF or DORMANT wakeup.
+ */
+static inline void set_cpu_wakeup_addr(unsigned int cpu_id, u32 addr)
+{
+        struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
+        __raw_writel(addr, pm_info->wkup_sar_addr);
+}
+/*
+ * Set the CPUx powerdomain's previous power state
+ */
+static inline void set_cpu_next_pwrst(unsigned int cpu_id,
+                                unsigned int power_state)
+{
+        struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
+        pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);
+}
+/*
+ * Read CPU's previous power state
+ */
+static inline unsigned int read_cpu_prev_pwrst(unsigned int cpu_id)
+{
+        struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
+        return pwrdm_read_prev_pwrst(pm_info->pwrdm);
+}
+/*
+ * Clear the CPUx powerdomain's previous power state
+ */
+static inline void clear_cpu_prev_pwrst(unsigned int cpu_id)
+{
+        struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
+        pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
+}
+/*
+ * Store the SCU power status value to scratchpad memory
+ */
+static void scu_pwrst_prepare(unsigned int cpu_id, unsigned int cpu_state)
+{
+        struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
+        u32 scu_pwr_st;
+        switch (cpu_state) {
+        case PWRDM_POWER_RET:
+                scu_pwr_st = SCU_PM_DORMANT;
+                break;
+        case PWRDM_POWER_OFF:
+                scu_pwr_st = SCU_PM_POWEROFF;
+                break;
+        case PWRDM_POWER_ON:
+        case PWRDM_POWER_INACTIVE:
+        default:
+                scu_pwr_st = SCU_PM_NORMAL;
+                break;
+        }
+        __raw_writel(scu_pwr_st, pm_info->scu_sar_addr);
+}
+/* Helper functions for MPUSS OSWR */
+static inline void mpuss_clear_prev_logic_pwrst(void)
+{
+        u32 reg;
+        reg = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
+                OMAP4430_PRM_MPU_INST, OMAP4_RM_MPU_MPU_CONTEXT_OFFSET);
+        omap4_prminst_write_inst_reg(reg, OMAP4430_PRM_PARTITION,
+                OMAP4430_PRM_MPU_INST, OMAP4_RM_MPU_MPU_CONTEXT_OFFSET);
+}
+static inline void cpu_clear_prev_logic_pwrst(unsigned int cpu_id)
+{
+        u32 reg;
+        if (cpu_id) {
+                reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU1_INST,
+                                        OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET);
+                omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU1_INST,
+                                        OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET);
+        } else {
+                reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU0_INST,
+                                        OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET);
+                omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU0_INST,
+                                        OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET);
+        }
+}
+/**
+ * omap4_mpuss_read_prev_context_state:
+ * Function returns the MPUSS previous context state
+ */
+u32 omap4_mpuss_read_prev_context_state(void)
+{
+        u32 reg;
+        reg = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
+                OMAP4430_PRM_MPU_INST, OMAP4_RM_MPU_MPU_CONTEXT_OFFSET);
+        reg &= OMAP4430_LOSTCONTEXT_DFF_MASK;
+        return reg;
+}
+/*
+ * Store the CPU cluster state for L2X0 low power operations.
+ */
+static void l2x0_pwrst_prepare(unsigned int cpu_id, unsigned int save_state)
+{
+        struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
+        __raw_writel(save_state, pm_info->l2x0_sar_addr);
+}
+/*
+ * Save the L2X0 AUXCTRL and POR value to SAR memory. Its used to
+ * in every restore MPUSS OFF path.
+ */
+#ifdef CONFIG_CACHE_L2X0
+static void save_l2x0_context(void)
+{
+        u32 val;
+        void __iomem *l2x0_base = omap4_get_l2cache_base();
+        val = __raw_readl(l2x0_base + L2X0_AUX_CTRL);
+        __raw_writel(val, sar_base + L2X0_AUXCTRL_OFFSET);
+        val = __raw_readl(l2x0_base + L2X0_PREFETCH_CTRL);
+        __raw_writel(val, sar_base + L2X0_PREFETCH_CTRL_OFFSET);
+}
+#else
+static void save_l2x0_context(void)
+{}
+#endif
+/**
+ * omap4_enter_lowpower: OMAP4 MPUSS Low Power Entry Function
+ * The purpose of this function is to manage low power programming
+ * of OMAP4 MPUSS subsystem
+ * @cpu : CPU ID
+ * @power_state: Low power state.
+ *
+ * MPUSS states for the context save:
+ * save_state =
+ *      0 - Nothing lost and no need to save: MPUSS INACTIVE
+ *      1 - CPUx L1 and logic lost: MPUSS CSWR
+ *      2 - CPUx L1 and logic lost + GIC lost: MPUSS OSWR
+ *      3 - CPUx L1 and logic lost + GIC + L2 lost: DEVICE OFF
+ */
+int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
+{
+        unsigned int save_state = 0;
+        unsigned int wakeup_cpu;
+        if (omap_rev() == OMAP4430_REV_ES1_0)
+                return -ENXIO;
+        switch (power_state) {
+        case PWRDM_POWER_ON:
+        case PWRDM_POWER_INACTIVE:
+                save_state = 0;
+                break;
+        case PWRDM_POWER_OFF:
+                save_state = 1;
+                break;
+        case PWRDM_POWER_RET:
+        default:
+                /*
+                 * CPUx CSWR is invalid hardware state. Also CPUx OSWR
+                 * doesn't make much scense, since logic is lost and $L1
+                 * needs to be cleaned because of coherency. This makes
+                 * CPUx OSWR equivalent to CPUX OFF and hence not supported
+                 */
+                WARN_ON(1);
+                return -ENXIO;
+        }
+        pwrdm_pre_transition();
+        /*
+         * Check MPUSS next state and save interrupt controller if needed.
+         * In MPUSS OSWR or device OFF, interrupt controller  contest is lost.
+         */
+        mpuss_clear_prev_logic_pwrst();
+        pwrdm_clear_all_prev_pwrst(mpuss_pd);
+        if ((pwrdm_read_next_pwrst(mpuss_pd) == PWRDM_POWER_RET) &&
+                (pwrdm_read_logic_retst(mpuss_pd) == PWRDM_POWER_OFF))
+                save_state = 2;
+        clear_cpu_prev_pwrst(cpu);
+        cpu_clear_prev_logic_pwrst(cpu);
+        set_cpu_next_pwrst(cpu, power_state);
+        set_cpu_wakeup_addr(cpu, virt_to_phys(omap4_cpu_resume));
+        scu_pwrst_prepare(cpu, power_state);
+        l2x0_pwrst_prepare(cpu, save_state);
+        /*
+         * Call low level function  with targeted low power state.
+         */
+        cpu_suspend(save_state, omap4_finish_suspend);
+        /*
+         * Restore the CPUx power state to ON otherwise CPUx
+         * power domain can transitions to programmed low power
+         * state while doing WFI outside the low powe code. On
+         * secure devices, CPUx does WFI which can result in
+         * domain transition
+         */
+        wakeup_cpu = smp_processor_id();
+        set_cpu_next_pwrst(wakeup_cpu, PWRDM_POWER_ON);
+        pwrdm_post_transition();
+        return 0;
+}
+/**
+ * omap4_hotplug_cpu: OMAP4 CPU hotplug entry
+ * @cpu : CPU ID
+ * @power_state: CPU low power state.
+ */
+int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
+{
+        unsigned int cpu_state = 0;
+        if (omap_rev() == OMAP4430_REV_ES1_0)
+                return -ENXIO;
+        if (power_state == PWRDM_POWER_OFF)
+                cpu_state = 1;
+        clear_cpu_prev_pwrst(cpu);
+        set_cpu_next_pwrst(cpu, power_state);
+        set_cpu_wakeup_addr(cpu, virt_to_phys(omap_secondary_startup));
+        scu_pwrst_prepare(cpu, power_state);
+        /*
+         * CPU never retuns back if targetted power state is OFF mode.
+         * CPU ONLINE follows normal CPU ONLINE ptah via
+         * omap_secondary_startup().
+         */
+        omap4_finish_suspend(cpu_state);
+        set_cpu_next_pwrst(cpu, PWRDM_POWER_ON);
+        return 0;
+}
+/*
+ * Initialise OMAP4 MPUSS
+ */
+int __init omap4_mpuss_init(void)
+{
+        struct omap4_cpu_pm_info *pm_info;
+        if (omap_rev() == OMAP4430_REV_ES1_0) {
+                WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
+                return -ENODEV;
+        }
+        sar_base = omap4_get_sar_ram_base();
+        /* Initilaise per CPU PM information */
+        pm_info = &per_cpu(omap4_pm_info, 0x0);
+        pm_info->scu_sar_addr = sar_base + SCU_OFFSET0;
+        pm_info->wkup_sar_addr = sar_base + CPU0_WAKEUP_NS_PA_ADDR_OFFSET;
+        pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET0;
+        pm_info->pwrdm = pwrdm_lookup("cpu0_pwrdm");
+        if (!pm_info->pwrdm) {
+                pr_err("Lookup failed for CPU0 pwrdm\n");
+                return -ENODEV;
+        }
+        /* Clear CPU previous power domain state */
+        pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
+        cpu_clear_prev_logic_pwrst(0);
+        /* Initialise CPU0 power domain state to ON */
+        pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
+        pm_info = &per_cpu(omap4_pm_info, 0x1);
+        pm_info->scu_sar_addr = sar_base + SCU_OFFSET1;
+        pm_info->wkup_sar_addr = sar_base + CPU1_WAKEUP_NS_PA_ADDR_OFFSET;
+        pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET1;
+        pm_info->pwrdm = pwrdm_lookup("cpu1_pwrdm");
+        if (!pm_info->pwrdm) {
+                pr_err("Lookup failed for CPU1 pwrdm\n");
+                return -ENODEV;
+        }
+        /* Clear CPU previous power domain state */
+        pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
+        cpu_clear_prev_logic_pwrst(1);
+        /* Initialise CPU1 power domain state to ON */
+        pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
+        mpuss_pd = pwrdm_lookup("mpu_pwrdm");
+        if (!mpuss_pd) {
+                pr_err("Failed to lookup MPUSS power domain\n");
+                return -ENODEV;
+        }
+        pwrdm_clear_all_prev_pwrst(mpuss_pd);
+        mpuss_clear_prev_logic_pwrst();
+        /* Save device type on scratchpad for low level code to use */
+        if (omap_type() != OMAP2_DEVICE_TYPE_GP)
+                __raw_writel(1, sar_base + OMAP_TYPE_OFFSET);
+        else
+                __raw_writel(0, sar_base + OMAP_TYPE_OFFSET);
+        save_l2x0_context();
+        return 0;
+}
+#endif
diff --git a/arch/arm/mach-omap2/omap-secure.c b/arch/arm/mach-omap2/omap-secure.c
new file mode 100644
index 000000000000..69f3c72d959b
--- /dev/null
+++ b/arch/arm/mach-omap2/omap-secure.c
@@ -0,0 +1,81 @@
+/*
+ * OMAP Secure API infrastructure.
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc.
+ *      Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ *
+ * This program is free software,you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/memblock.h>
+#include <asm/cacheflush.h>
+#include <mach/omap-secure.h>
+static phys_addr_t omap_secure_memblock_base;
+/**
+ * omap_sec_dispatcher: Routine to dispatch low power secure
+ * service routines
+ * @idx: The HAL API index
+ * @flag: The flag indicating criticality of operation
+ * @nargs: Number of valid arguments out of four.
+ * @arg1, arg2, arg3 args4: Parameters passed to secure API
+ *
+ * Return the non-zero error value on failure.
+ */
+u32 omap_secure_dispatcher(u32 idx, u32 flag, u32 nargs, u32 arg1, u32 arg2,
+                                                         u32 arg3, u32 arg4)
+{
+        u32 ret;
+        u32 param[5];
+        param[0] = nargs;
+        param[1] = arg1;
+        param[2] = arg2;
+        param[3] = arg3;
+        param[4] = arg4;
+        /*
+         * Secure API needs physical address
+         * pointer for the parameters
+         */
+        flush_cache_all();
+        outer_clean_range(__pa(param), __pa(param + 5));
+        ret = omap_smc2(idx, flag, __pa(param));
+        return ret;
+}
+/* Allocate the memory to save secure ram */
+int __init omap_secure_ram_reserve_memblock(void)
+{
+        phys_addr_t paddr;
+        u32 size = OMAP_SECURE_RAM_STORAGE;
+        size = ALIGN(size, SZ_1M);
+        paddr = memblock_alloc(size, SZ_1M);
+        if (!paddr) {
+                pr_err("%s: failed to reserve %x bytes\n",
+                                __func__, size);
+                return -ENOMEM;
+        }
+        memblock_free(paddr, size);
+        memblock_remove(paddr, size);
+        omap_secure_memblock_base = paddr;
+        return 0;
+}
+phys_addr_t omap_secure_ram_mempool_base(void)
+{
+        return omap_secure_memblock_base;
+}
diff --git a/arch/arm/mach-omap2/omap44xx-smc.S b/arch/arm/mach-omap2/omap-smc.S
index e69d37d95204..f6441c13cd8c 100644
--- a/arch/arm/mach-omap2/omap44xx-smc.S
+++ b/arch/arm/mach-omap2/omap-smc.S
@@ -31,6 +31,29 @@ ENTRY(omap_smc1)
        ldmfd   sp!, {r2-r12, pc}
 ENDPROC(omap_smc1)
+/**
+ * u32 omap_smc2(u32 id, u32 falg, u32 pargs)
+ * Low level common routine for secure HAL and PPA APIs.
+ * @id: Application ID of HAL APIs
+ * @flag: Flag to indicate the criticality of operation
+ * @pargs: Physical address of parameter list starting
+ *          with number of parametrs
+ */
+ENTRY(omap_smc2)
+        stmfd   sp!, {r4-r12, lr}
+        mov     r3, r2
+        mov     r2, r1
+        mov     r1, #0x0        @ Process ID
+        mov     r6, #0xff
+        mov     r12, #0x00      @ Secure Service ID
+        mov     r7, #0
+        mcr     p15, 0, r7, c7, c5, 6
+        dsb
+        dmb
+        smc     #0
+        ldmfd   sp!, {r4-r12, pc}
+ENDPROC(omap_smc2)
 ENTRY(omap_modify_auxcoreboot0)
        stmfd   sp!, {r1-r12, lr}
        ldr     r12, =0x104
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index 4412ddb7b3f6..c1bf3ef0ba02 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -24,16 +24,37 @@
 #include <asm/hardware/gic.h>
 #include <asm/smp_scu.h>
 #include <mach/hardware.h>
-#include <mach/omap4-common.h>
+#include <mach/omap-secure.h>
+#include "common.h"
+#include "clockdomain.h"
 /* SCU base address */
 static void __iomem *scu_base;
 static DEFINE_SPINLOCK(boot_lock);
+void __iomem *omap4_get_scu_base(void)
+{
+        return scu_base;
+}
 void __cpuinit platform_secondary_init(unsigned int cpu)
 {
        /*
+         * Configure ACTRL and enable NS SMP bit access on CPU1 on HS device.
+         * OMAP44XX EMU/HS devices - CPU0 SMP bit access is enabled in PPA
+         * init and for CPU1, a secure PPA API provided. CPU0 must be ON
+         * while executing NS_SMP API on CPU1 and PPA version must be 1.4.0+.
+         * OMAP443X GP devices- SMP bit isn't accessible.
+         * OMAP446X GP devices - SMP bit access is enabled on both CPUs.
+         */
+        if (cpu_is_omap443x() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
+                omap_secure_dispatcher(OMAP4_PPA_CPU_ACTRL_SMP_INDEX,
+                                                        4, 0, 0, 0, 0, 0);
+        /*
         * If any interrupts are already enabled for the primary
         * core (e.g. timer irq), then they will not have been enabled
         * for us: do so
@@ -49,6 +70,8 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
 int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
+        static struct clockdomain *cpu1_clkdm;
+        static bool booted;
        /*
         * Set synchronisation state between this boot processor
         * and the secondary one
@@ -64,6 +87,29 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
        omap_modify_auxcoreboot0(0x200, 0xfffffdff);
        flush_cache_all();
        smp_wmb();
+        if (!cpu1_clkdm)
+                cpu1_clkdm = clkdm_lookup("mpu1_clkdm");
+        /*
+         * The SGI(Software Generated Interrupts) are not wakeup capable
+         * from low power states. This is known limitation on OMAP4 and
+         * needs to be worked around by using software forced clockdomain
+         * wake-up. To wakeup CPU1, CPU0 forces the CPU1 clockdomain to
+         * software force wakeup. The clockdomain is then put back to
+         * hardware supervised mode.
+         * More details can be found in OMAP4430 TRM - Version J
+         * Section :
+         *      4.3.4.2 Power States of CPU0 and CPU1
+         */
+        if (booted) {
+                clkdm_wakeup(cpu1_clkdm);
+                clkdm_allow_idle(cpu1_clkdm);
+        } else {
+                dsb_sev();
+                booted = true;
+        }
        gic_raise_softirq(cpumask_of(cpu), 1);
        /*
diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c b/arch/arm/mach-omap2/omap-wakeupgen.c
new file mode 100644
index 000000000000..d3d8971d7f30
--- /dev/null
+++ b/arch/arm/mach-omap2/omap-wakeupgen.c
@@ -0,0 +1,389 @@
+/*
+ * OMAP WakeupGen Source file
+ *
+ * OMAP WakeupGen is the interrupt controller extension used along
+ * with ARM GIC to wake the CPU out from low power states on
+ * external interrupts. It is responsible for generating wakeup
+ * event from the incoming interrupts and enable bits. It is
+ * implemented in MPU always ON power domain. During normal operation,
+ * WakeupGen delivers external interrupts directly to the GIC.
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc.
+ *      Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/platform_device.h>
+#include <linux/cpu.h>
+#include <linux/notifier.h>
+#include <linux/cpu_pm.h>
+#include <asm/hardware/gic.h>
+#include <mach/omap-wakeupgen.h>
+#include <mach/omap-secure.h>
+#include "omap4-sar-layout.h"
+#include "common.h"
+#define NR_REG_BANKS            4
+#define MAX_IRQS                128
+#define WKG_MASK_ALL            0x00000000
+#define WKG_UNMASK_ALL          0xffffffff
+#define CPU_ENA_OFFSET          0x400
+#define CPU0_ID                 0x0
+#define CPU1_ID                 0x1
+static void __iomem *wakeupgen_base;
+static void __iomem *sar_base;
+static DEFINE_PER_CPU(u32 [NR_REG_BANKS], irqmasks);
+static DEFINE_SPINLOCK(wakeupgen_lock);
+static unsigned int irq_target_cpu[NR_IRQS];
+/*
+ * Static helper functions.
+ */
+static inline u32 wakeupgen_readl(u8 idx, u32 cpu)
+{
+        return __raw_readl(wakeupgen_base + OMAP_WKG_ENB_A_0 +
+                                (cpu * CPU_ENA_OFFSET) + (idx * 4));
+}
+static inline void wakeupgen_writel(u32 val, u8 idx, u32 cpu)
+{
+        __raw_writel(val, wakeupgen_base + OMAP_WKG_ENB_A_0 +
+                                (cpu * CPU_ENA_OFFSET) + (idx * 4));
+}
+static inline void sar_writel(u32 val, u32 offset, u8 idx)
+{
+        __raw_writel(val, sar_base + offset + (idx * 4));
+}
+static void _wakeupgen_set_all(unsigned int cpu, unsigned int reg)
+{
+        u8 i;
+        for (i = 0; i < NR_REG_BANKS; i++)
+                wakeupgen_writel(reg, i, cpu);
+}
+static inline int _wakeupgen_get_irq_info(u32 irq, u32 *bit_posn, u8 *reg_index)
+{
+        unsigned int spi_irq;
+        /*
+         * PPIs and SGIs are not supported.
+         */
+        if (irq < OMAP44XX_IRQ_GIC_START)
+                return -EINVAL;
+        /*
+         * Subtract the GIC offset.
+         */
+        spi_irq = irq - OMAP44XX_IRQ_GIC_START;
+        if (spi_irq > MAX_IRQS) {
+                pr_err("omap wakeupGen: Invalid IRQ%d\n", irq);
+                return -EINVAL;
+        }
+        /*
+         * Each WakeupGen register controls 32 interrupt.
+         * i.e. 1 bit per SPI IRQ
+         */
+        *reg_index = spi_irq >> 5;
+        *bit_posn = spi_irq %= 32;
+        return 0;
+}
+static void _wakeupgen_clear(unsigned int irq, unsigned int cpu)
+{
+        u32 val, bit_number;
+        u8 i;
+        if (_wakeupgen_get_irq_info(irq, &bit_number, &i))
+                return;
+        val = wakeupgen_readl(i, cpu);
+        val &= ~BIT(bit_number);
+        wakeupgen_writel(val, i, cpu);
+}
+static void _wakeupgen_set(unsigned int irq, unsigned int cpu)
+{
+        u32 val, bit_number;
+        u8 i;
+        if (_wakeupgen_get_irq_info(irq, &bit_number, &i))
+                return;
+        val = wakeupgen_readl(i, cpu);
+        val |= BIT(bit_number);
+        wakeupgen_writel(val, i, cpu);
+}
+static void _wakeupgen_save_masks(unsigned int cpu)
+{
+        u8 i;
+        for (i = 0; i < NR_REG_BANKS; i++)
+                per_cpu(irqmasks, cpu)[i] = wakeupgen_readl(i, cpu);
+}
+static void _wakeupgen_restore_masks(unsigned int cpu)
+{
+        u8 i;
+        for (i = 0; i < NR_REG_BANKS; i++)
+                wakeupgen_writel(per_cpu(irqmasks, cpu)[i], i, cpu);
+}
+/*
+ * Architecture specific Mask extension
+ */
+static void wakeupgen_mask(struct irq_data *d)
+{
+        unsigned long flags;
+        spin_lock_irqsave(&wakeupgen_lock, flags);
+        _wakeupgen_clear(d->irq, irq_target_cpu[d->irq]);
+        spin_unlock_irqrestore(&wakeupgen_lock, flags);
+}
+/*
+ * Architecture specific Unmask extension
+ */
+static void wakeupgen_unmask(struct irq_data *d)
+{
+        unsigned long flags;
+        spin_lock_irqsave(&wakeupgen_lock, flags);
+        _wakeupgen_set(d->irq, irq_target_cpu[d->irq]);
+        spin_unlock_irqrestore(&wakeupgen_lock, flags);
+}
+/*
+ * Mask or unmask all interrupts on given CPU.
+ *      0 = Mask all interrupts on the 'cpu'
+ *      1 = Unmask all interrupts on the 'cpu'
+ * Ensure that the initial mask is maintained. This is faster than
+ * iterating through GIC registers to arrive at the correct masks.
+ */
+static void wakeupgen_irqmask_all(unsigned int cpu, unsigned int set)
+{
+        unsigned long flags;
+        spin_lock_irqsave(&wakeupgen_lock, flags);
+        if (set) {
+                _wakeupgen_save_masks(cpu);
+                _wakeupgen_set_all(cpu, WKG_MASK_ALL);
+        } else {
+                _wakeupgen_set_all(cpu, WKG_UNMASK_ALL);
+                _wakeupgen_restore_masks(cpu);
+        }
+        spin_unlock_irqrestore(&wakeupgen_lock, flags);
+}
+#ifdef CONFIG_CPU_PM
+/*
+ * Save WakeupGen interrupt context in SAR BANK3. Restore is done by
+ * ROM code. WakeupGen IP is integrated along with GIC to manage the
+ * interrupt wakeups from CPU low power states. It manages
+ * masking/unmasking of Shared peripheral interrupts(SPI). So the
+ * interrupt enable/disable control should be in sync and consistent
+ * at WakeupGen and GIC so that interrupts are not lost.
+ */
+static void irq_save_context(void)
+{
+        u32 i, val;
+        if (omap_rev() == OMAP4430_REV_ES1_0)
+                return;
+        if (!sar_base)
+                sar_base = omap4_get_sar_ram_base();
+        for (i = 0; i < NR_REG_BANKS; i++) {
+                /* Save the CPUx interrupt mask for IRQ 0 to 127 */
+                val = wakeupgen_readl(i, 0);
+                sar_writel(val, WAKEUPGENENB_OFFSET_CPU0, i);
+                val = wakeupgen_readl(i, 1);
+                sar_writel(val, WAKEUPGENENB_OFFSET_CPU1, i);
+                /*
+                 * Disable the secure interrupts for CPUx. The restore
+                 * code blindly restores secure and non-secure interrupt
+                 * masks from SAR RAM. Secure interrupts are not suppose
+                 * to be enabled from HLOS. So overwrite the SAR location
+                 * so that the secure interrupt remains disabled.
+                 */
+                sar_writel(0x0, WAKEUPGENENB_SECURE_OFFSET_CPU0, i);
+                sar_writel(0x0, WAKEUPGENENB_SECURE_OFFSET_CPU1, i);
+        }
+        /* Save AuxBoot* registers */
+        val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
+        __raw_writel(val, sar_base + AUXCOREBOOT0_OFFSET);
+        val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
+        __raw_writel(val, sar_base + AUXCOREBOOT1_OFFSET);
+        /* Save SyncReq generation logic */
+        val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
+        __raw_writel(val, sar_base + AUXCOREBOOT0_OFFSET);
+        val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
+        __raw_writel(val, sar_base + AUXCOREBOOT1_OFFSET);
+        /* Save SyncReq generation logic */
+        val = __raw_readl(wakeupgen_base + OMAP_PTMSYNCREQ_MASK);
+        __raw_writel(val, sar_base + PTMSYNCREQ_MASK_OFFSET);
+        val = __raw_readl(wakeupgen_base + OMAP_PTMSYNCREQ_EN);
+        __raw_writel(val, sar_base + PTMSYNCREQ_EN_OFFSET);
+        /* Set the Backup Bit Mask status */
+        val = __raw_readl(sar_base + SAR_BACKUP_STATUS_OFFSET);
+        val |= SAR_BACKUP_STATUS_WAKEUPGEN;
+        __raw_writel(val, sar_base + SAR_BACKUP_STATUS_OFFSET);
+}
+/*
+ * Clear WakeupGen SAR backup status.
+ */
+void irq_sar_clear(void)
+{
+        u32 val;
+        val = __raw_readl(sar_base + SAR_BACKUP_STATUS_OFFSET);
+        val &= ~SAR_BACKUP_STATUS_WAKEUPGEN;
+        __raw_writel(val, sar_base + SAR_BACKUP_STATUS_OFFSET);
+}
+/*
+ * Save GIC and Wakeupgen interrupt context using secure API
+ * for HS/EMU devices.
+ */
+static void irq_save_secure_context(void)
+{
+        u32 ret;
+        ret = omap_secure_dispatcher(OMAP4_HAL_SAVEGIC_INDEX,
+                                FLAG_START_CRITICAL,
+                                0, 0, 0, 0, 0);
+        if (ret != API_HAL_RET_VALUE_OK)
+                pr_err("GIC and Wakeupgen context save failed\n");
+}
+#endif
+#ifdef CONFIG_HOTPLUG_CPU
+static int __cpuinit irq_cpu_hotplug_notify(struct notifier_block *self,
+                                         unsigned long action, void *hcpu)
+{
+        unsigned int cpu = (unsigned int)hcpu;
+        switch (action) {
+        case CPU_ONLINE:
+                wakeupgen_irqmask_all(cpu, 0);
+                break;
+        case CPU_DEAD:
+                wakeupgen_irqmask_all(cpu, 1);
+                break;
+        }
+        return NOTIFY_OK;
+}
+static struct notifier_block __refdata irq_hotplug_notifier = {
+        .notifier_call = irq_cpu_hotplug_notify,
+};
+static void __init irq_hotplug_init(void)
+{
+        register_hotcpu_notifier(&irq_hotplug_notifier);
+}
+#else
+static void __init irq_hotplug_init(void)
+{}
+#endif
+#ifdef CONFIG_CPU_PM
+static int irq_notifier(struct notifier_block *self, unsigned long cmd, void *v)
+{
+        switch (cmd) {
+        case CPU_CLUSTER_PM_ENTER:
+                if (omap_type() == OMAP2_DEVICE_TYPE_GP)
+                        irq_save_context();
+                else
+                        irq_save_secure_context();
+                break;
+        case CPU_CLUSTER_PM_EXIT:
+                if (omap_type() == OMAP2_DEVICE_TYPE_GP)
+                        irq_sar_clear();
+                break;
+        }
+        return NOTIFY_OK;
+}
+static struct notifier_block irq_notifier_block = {
+        .notifier_call = irq_notifier,
+};
+static void __init irq_pm_init(void)
+{
+        cpu_pm_register_notifier(&irq_notifier_block);
+}
+#else
+static void __init irq_pm_init(void)
+{}
+#endif
+/*
+ * Initialise the wakeupgen module.
+ */
+int __init omap_wakeupgen_init(void)
+{
+        int i;
+        unsigned int boot_cpu = smp_processor_id();
+        /* Not supported on OMAP4 ES1.0 silicon */
+        if (omap_rev() == OMAP4430_REV_ES1_0) {
+                WARN(1, "WakeupGen: Not supported on OMAP4430 ES1.0\n");
+                return -EPERM;
+        }
+        /* Static mapping, never released */
+        wakeupgen_base = ioremap(OMAP44XX_WKUPGEN_BASE, SZ_4K);
+        if (WARN_ON(!wakeupgen_base))
+                return -ENOMEM;
+        /* Clear all IRQ bitmasks at wakeupGen level */
+        for (i = 0; i < NR_REG_BANKS; i++) {
+                wakeupgen_writel(0, i, CPU0_ID);
+                wakeupgen_writel(0, i, CPU1_ID);
+        }
+        /*
+         * Override GIC architecture specific functions to add
+         * OMAP WakeupGen interrupt controller along with GIC
+         */
+        gic_arch_extn.irq_mask = wakeupgen_mask;
+        gic_arch_extn.irq_unmask = wakeupgen_unmask;
+        gic_arch_extn.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE;
+        /*
+         * FIXME: Add support to set_smp_affinity() once the core
+         * GIC code has necessary hooks in place.
+         */
+        /* Associate all the IRQs to boot CPU like GIC init does. */
+        for (i = 0; i < NR_IRQS; i++)
+                irq_target_cpu[i] = boot_cpu;
+        irq_hotplug_init();
+        irq_pm_init();
+        return 0;
+}
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index 35ac3e5f6e94..bc16c818c6b7 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -15,24 +15,80 @@
 #include <linux/init.h>
 #include <linux/io.h>
 #include <linux/platform_device.h>
+#include <linux/memblock.h>
 #include <asm/hardware/gic.h>
 #include <asm/hardware/cache-l2x0.h>
+#include <asm/mach/map.h>
 #include <plat/irqs.h>
+#include <plat/sram.h>
 #include <mach/hardware.h>
-#include <mach/omap4-common.h>
+#include <mach/omap-wakeupgen.h>
+#include "common.h"
+#include "omap4-sar-layout.h"
 #ifdef CONFIG_CACHE_L2X0
-void __iomem *l2cache_base;
+static void __iomem *l2cache_base;
 #endif
-void __iomem *gic_dist_base_addr;
+static void __iomem *sar_ram_base;
+#ifdef CONFIG_OMAP4_ERRATA_I688
+/* Used to implement memory barrier on DRAM path */
+#define OMAP4_DRAM_BARRIER_VA                   0xfe600000
+void __iomem *dram_sync, *sram_sync;
+void omap_bus_sync(void)
+{
+        if (dram_sync && sram_sync) {
+                writel_relaxed(readl_relaxed(dram_sync), dram_sync);
+                writel_relaxed(readl_relaxed(sram_sync), sram_sync);
+                isb();
+        }
+}
+static int __init omap_barriers_init(void)
+{
+        struct map_desc dram_io_desc[1];
+        phys_addr_t paddr;
+        u32 size;
+        if (!cpu_is_omap44xx())
+                return -ENODEV;
+        size = ALIGN(PAGE_SIZE, SZ_1M);
+        paddr = memblock_alloc(size, SZ_1M);
+        if (!paddr) {
+                pr_err("%s: failed to reserve 4 Kbytes\n", __func__);
+                return -ENOMEM;
+        }
+        memblock_free(paddr, size);
+        memblock_remove(paddr, size);
+        dram_io_desc[0].virtual = OMAP4_DRAM_BARRIER_VA;
+        dram_io_desc[0].pfn = __phys_to_pfn(paddr);
+        dram_io_desc[0].length = size;
+        dram_io_desc[0].type = MT_MEMORY_SO;
+        iotable_init(dram_io_desc, ARRAY_SIZE(dram_io_desc));
+        dram_sync = (void __iomem *) dram_io_desc[0].virtual;
+        sram_sync = (void __iomem *) OMAP4_SRAM_VA;
+        pr_info("OMAP4: Map 0x%08llx to 0x%08lx for dram barrier\n",
+                (long long) paddr, dram_io_desc[0].virtual);
+        return 0;
+}
+core_initcall(omap_barriers_init);
+#endif
 void __init gic_init_irq(void)
 {
+        void __iomem *omap_irq_base;
+        void __iomem *gic_dist_base_addr;
        /* Static mapping, never released */
        gic_dist_base_addr = ioremap(OMAP44XX_GIC_DIST_BASE, SZ_4K);
        BUG_ON(!gic_dist_base_addr);
@@ -41,11 +97,18 @@ void __init gic_init_irq(void)
        omap_irq_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
        BUG_ON(!omap_irq_base);
+        omap_wakeupgen_init();
        gic_init(0, 29, gic_dist_base_addr, omap_irq_base);
 }
 #ifdef CONFIG_CACHE_L2X0
+void __iomem *omap4_get_l2cache_base(void)
+{
+        return l2cache_base;
+}
 static void omap4_l2x0_disable(void)
 {
        /* Disable PL310 L2 Cache controller */
@@ -71,7 +134,8 @@ static int __init omap_l2_cache_init(void)
        /* Static mapping, never released */
        l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
-        BUG_ON(!l2cache_base);
+        if (WARN_ON(!l2cache_base))
+                return -ENOMEM;
        /*
         * 16-way associativity, parity disabled
@@ -111,3 +175,30 @@ static int __init omap_l2_cache_init(void)
 }
 early_initcall(omap_l2_cache_init);
 #endif
+void __iomem *omap4_get_sar_ram_base(void)
+{
+        return sar_ram_base;
+}
+/*
+ * SAR RAM used to save and restore the HW
+ * context in low power modes
+ */
+static int __init omap4_sar_ram_init(void)
+{
+        /*
+         * To avoid code running on other OMAPs in
+         * multi-omap builds
+         */
+        if (!cpu_is_omap44xx())
+                return -ENOMEM;
+        /* Static mapping, never released */
+        sar_ram_base = ioremap(OMAP44XX_SAR_RAM_BASE, SZ_16K);
+        if (WARN_ON(!sar_ram_base))
+                return -ENOMEM;
+        return 0;
+}
+early_initcall(omap4_sar_ram_init);
diff --git a/arch/arm/mach-omap2/omap4-sar-layout.h b/arch/arm/mach-omap2/omap4-sar-layout.h
new file mode 100644
index 000000000000..fe5b545ad443
--- /dev/null
+++ b/arch/arm/mach-omap2/omap4-sar-layout.h
@@ -0,0 +1,50 @@
+/*
+ * omap4-sar-layout.h: OMAP4 SAR RAM layout header file
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc.
+ *      Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef OMAP_ARCH_OMAP4_SAR_LAYOUT_H
+#define OMAP_ARCH_OMAP4_SAR_LAYOUT_H
+/*
+ * SAR BANK offsets from base address OMAP44XX_SAR_RAM_BASE
+ */
+#define SAR_BANK1_OFFSET                0x0000
+#define SAR_BANK2_OFFSET                0x1000
+#define SAR_BANK3_OFFSET                0x2000
+#define SAR_BANK4_OFFSET                0x3000
+/* Scratch pad memory offsets from SAR_BANK1 */
+#define SCU_OFFSET0                             0xd00
+#define SCU_OFFSET1                             0xd04
+#define OMAP_TYPE_OFFSET                        0xd10
+#define L2X0_SAVE_OFFSET0                       0xd14
+#define L2X0_SAVE_OFFSET1                       0xd18
+#define L2X0_AUXCTRL_OFFSET                     0xd1c
+#define L2X0_PREFETCH_CTRL_OFFSET               0xd20
+/* CPUx Wakeup Non-Secure Physical Address offsets in SAR_BANK3 */
+#define CPU0_WAKEUP_NS_PA_ADDR_OFFSET           0xa04
+#define CPU1_WAKEUP_NS_PA_ADDR_OFFSET           0xa08
+#define SAR_BACKUP_STATUS_OFFSET                (SAR_BANK3_OFFSET + 0x500)
+#define SAR_SECURE_RAM_SIZE_OFFSET              (SAR_BANK3_OFFSET + 0x504)
+#define SAR_SECRAM_SAVED_AT_OFFSET              (SAR_BANK3_OFFSET + 0x508)
+/* WakeUpGen save restore offset from OMAP44XX_SAR_RAM_BASE */
+#define WAKEUPGENENB_OFFSET_CPU0                (SAR_BANK3_OFFSET + 0x684)
+#define WAKEUPGENENB_SECURE_OFFSET_CPU0         (SAR_BANK3_OFFSET + 0x694)
+#define WAKEUPGENENB_OFFSET_CPU1                (SAR_BANK3_OFFSET + 0x6a4)
+#define WAKEUPGENENB_SECURE_OFFSET_CPU1         (SAR_BANK3_OFFSET + 0x6b4)
+#define AUXCOREBOOT0_OFFSET                     (SAR_BANK3_OFFSET + 0x6c4)
+#define AUXCOREBOOT1_OFFSET                     (SAR_BANK3_OFFSET + 0x6c8)
+#define PTMSYNCREQ_MASK_OFFSET                  (SAR_BANK3_OFFSET + 0x6cc)
+#define PTMSYNCREQ_EN_OFFSET                    (SAR_BANK3_OFFSET + 0x6d0)
+#define SAR_BACKUP_STATUS_WAKEUPGEN             0x10
+#endif
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 207a2ff9a8c4..ee9416bcc3e6 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -136,8 +136,9 @@
 #include <linux/list.h>
 #include <linux/mutex.h>
 #include <linux/spinlock.h>
+#include <linux/slab.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/cpu.h>
 #include "clockdomain.h"
 #include "powerdomain.h"
@@ -381,6 +382,51 @@ static int _set_module_autoidle(struct omap_hwmod *oh, u8 autoidle,
 }
 /**
+ * _set_idle_ioring_wakeup - enable/disable IO pad wakeup on hwmod idle for mux
+ * @oh: struct omap_hwmod *
+ * @set_wake: bool value indicating to set (true) or clear (false) wakeup enable
+ *
+ * Set or clear the I/O pad wakeup flag in the mux entries for the
+ * hwmod @oh.  This function changes the @oh->mux->pads_dynamic array
+ * in memory.  If the hwmod is currently idled, and the new idle
+ * values don't match the previous ones, this function will also
+ * update the SCM PADCTRL registers.  Otherwise, if the hwmod is not
+ * currently idled, this function won't touch the hardware: the new
+ * mux settings are written to the SCM PADCTRL registers when the
+ * hwmod is idled.  No return value.
+ */
+static void _set_idle_ioring_wakeup(struct omap_hwmod *oh, bool set_wake)
+{
+        struct omap_device_pad *pad;
+        bool change = false;
+        u16 prev_idle;
+        int j;
+        if (!oh->mux || !oh->mux->enabled)
+                return;
+        for (j = 0; j < oh->mux->nr_pads_dynamic; j++) {
+                pad = oh->mux->pads_dynamic[j];
+                if (!(pad->flags & OMAP_DEVICE_PAD_WAKEUP))
+                        continue;
+                prev_idle = pad->idle;
+                if (set_wake)
+                        pad->idle |= OMAP_WAKEUP_EN;
+                else
+                        pad->idle &= ~OMAP_WAKEUP_EN;
+                if (prev_idle != pad->idle)
+                        change = true;
+        }
+        if (change && oh->_state == _HWMOD_STATE_IDLE)
+                omap_hwmod_mux(oh->mux, _HWMOD_STATE_IDLE);
+}
+/**
 * _enable_wakeup: set OCP_SYSCONFIG.ENAWAKEUP bit in the hardware
 * @oh: struct omap_hwmod *
 *
@@ -1441,6 +1487,25 @@ static int _enable(struct omap_hwmod *oh)
        pr_debug("omap_hwmod: %s: enabling\n", oh->name);
+        /*
+         * hwmods with HWMOD_INIT_NO_IDLE flag set are left
+         * in enabled state at init.
+         * Now that someone is really trying to enable them,
+         * just ensure that the hwmod mux is set.
+         */
+        if (oh->_int_flags & _HWMOD_SKIP_ENABLE) {
+                /*
+                 * If the caller has mux data populated, do the mux'ing
+                 * which wouldn't have been done as part of the _enable()
+                 * done during setup.
+                 */
+                if (oh->mux)
+                        omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED);
+                oh->_int_flags &= ~_HWMOD_SKIP_ENABLE;
+                return 0;
+        }
        if (oh->_state != _HWMOD_STATE_INITIALIZED &&
            oh->_state != _HWMOD_STATE_IDLE &&
            oh->_state != _HWMOD_STATE_DISABLED) {
@@ -1744,8 +1809,10 @@ static int _setup(struct omap_hwmod *oh, void *data)
         * it should be set by the core code as a runtime flag during startup
         */
        if ((oh->flags & HWMOD_INIT_NO_IDLE) &&
-            (postsetup_state == _HWMOD_STATE_IDLE))
+            (postsetup_state == _HWMOD_STATE_IDLE)) {
+                oh->_int_flags |= _HWMOD_SKIP_ENABLE;
                postsetup_state = _HWMOD_STATE_ENABLED;
+        }
        if (postsetup_state == _HWMOD_STATE_IDLE)
                _idle(oh);
@@ -2416,6 +2483,7 @@ int omap_hwmod_enable_wakeup(struct omap_hwmod *oh)
        v = oh->_sysc_cache;
        _enable_wakeup(oh, &v);
        _write_sysconfig(v, oh);
+        _set_idle_ioring_wakeup(oh, true);
        spin_unlock_irqrestore(&oh->_lock, flags);
        return 0;
@@ -2446,6 +2514,7 @@ int omap_hwmod_disable_wakeup(struct omap_hwmod *oh)
        v = oh->_sysc_cache;
        _disable_wakeup(oh, &v);
        _write_sysconfig(v, oh);
+        _set_idle_ioring_wakeup(oh, false);
        spin_unlock_irqrestore(&oh->_lock, flags);
        return 0;
@@ -2662,3 +2731,57 @@ int omap_hwmod_no_setup_reset(struct omap_hwmod *oh)
        return 0;
 }
+/**
+ * omap_hwmod_pad_route_irq - route an I/O pad wakeup to a particular MPU IRQ
+ * @oh: struct omap_hwmod * containing hwmod mux entries
+ * @pad_idx: array index in oh->mux of the hwmod mux entry to route wakeup
+ * @irq_idx: the hwmod mpu_irqs array index of the IRQ to trigger on wakeup
+ *
+ * When an I/O pad wakeup arrives for the dynamic or wakeup hwmod mux
+ * entry number @pad_idx for the hwmod @oh, trigger the interrupt
+ * service routine for the hwmod's mpu_irqs array index @irq_idx.  If
+ * this function is not called for a given pad_idx, then the ISR
+ * associated with @oh's first MPU IRQ will be triggered when an I/O
+ * pad wakeup occurs on that pad.  Note that @pad_idx is the index of
+ * the _dynamic or wakeup_ entry: if there are other entries not
+ * marked with OMAP_DEVICE_PAD_WAKEUP or OMAP_DEVICE_PAD_REMUX, these
+ * entries are NOT COUNTED in the dynamic pad index.  This function
+ * must be called separately for each pad that requires its interrupt
+ * to be re-routed this way.  Returns -EINVAL if there is an argument
+ * problem or if @oh does not have hwmod mux entries or MPU IRQs;
+ * returns -ENOMEM if memory cannot be allocated; or 0 upon success.
+ *
+ * XXX This function interface is fragile.  Rather than using array
+ * indexes, which are subject to unpredictable change, it should be
+ * using hwmod IRQ names, and some other stable key for the hwmod mux
+ * pad records.
+ */
+int omap_hwmod_pad_route_irq(struct omap_hwmod *oh, int pad_idx, int irq_idx)
+{
+        int nr_irqs;
+        might_sleep();
+        if (!oh || !oh->mux || !oh->mpu_irqs || pad_idx < 0 ||
+            pad_idx >= oh->mux->nr_pads_dynamic)
+                return -EINVAL;
+        /* Check the number of available mpu_irqs */
+        for (nr_irqs = 0; oh->mpu_irqs[nr_irqs].irq >= 0; nr_irqs++)
+                ;
+        if (irq_idx >= nr_irqs)
+                return -EINVAL;
+        if (!oh->mux->irqs) {
+                /* XXX What frees this? */
+                oh->mux->irqs = kzalloc(sizeof(int) * oh->mux->nr_pads_dynamic,
+                        GFP_KERNEL);
+                if (!oh->mux->irqs)
+                        return -ENOMEM;
+        }
+        oh->mux->irqs[pad_idx] = irq_idx;
+        return 0;
+}
diff --git a/arch/arm/mach-omap2/opp2xxx.h b/arch/arm/mach-omap2/opp2xxx.h
index 8affc66a92c2..8fae534eb157 100644
--- a/arch/arm/mach-omap2/opp2xxx.h
+++ b/arch/arm/mach-omap2/opp2xxx.h
@@ -51,7 +51,7 @@ struct prcm_config {
        unsigned long cm_clksel2_pll;   /* dpllx1 or x2 out */
        unsigned long cm_clksel_mdm;    /* modem dividers 2430 only */
        unsigned long base_sdrc_rfr;    /* base refresh timing for a set */
-        unsigned char flags;
+        unsigned short flags;
 };
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 00bff46ca48b..1881fe915149 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -18,7 +18,7 @@
 #include <plat/omap-pm.h>
 #include <plat/omap_device.h>
-#include <plat/common.h>
+#include "common.h"
 #include "voltage.h"
 #include "powerdomain.h"
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 4e166add2f35..b737b11e4499 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -21,6 +21,7 @@ extern void omap_sram_idle(void);
 extern int omap3_can_sleep(void);
 extern int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state);
 extern int omap3_idle_init(void);
+extern int omap4_idle_init(void);
 #if defined(CONFIG_PM_OPP)
 extern int omap3_opp_init(void);
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index cf0c216132ab..b8822f8b2891 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -30,7 +30,6 @@
 #include <linux/irq.h>
 #include <linux/time.h>
 #include <linux/gpio.h>
-#include <linux/console.h>
 #include <asm/mach/time.h>
 #include <asm/mach/irq.h>
@@ -42,6 +41,7 @@
 #include <plat/dma.h>
 #include <plat/board.h>
+#include "common.h"
 #include "prm2xxx_3xxx.h"
 #include "prm-regbits-24xx.h"
 #include "cm2xxx_3xxx.h"
@@ -126,27 +126,11 @@ static void omap2_enter_full_retention(void)
        if (omap_irq_pending())
                goto no_sleep;
-        /* Block console output in case it is on one of the OMAP UARTs */
-        if (!is_suspending())
-                if (!console_trylock())
-                        goto no_sleep;
-        omap_uart_prepare_idle(0);
-        omap_uart_prepare_idle(1);
-        omap_uart_prepare_idle(2);
        /* Jump to SRAM suspend code */
        omap2_sram_suspend(sdrc_read_reg(SDRC_DLLA_CTRL),
                           OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL),
                           OMAP_SDRC_REGADDR(SDRC_POWER));
-        omap_uart_resume_idle(2);
-        omap_uart_resume_idle(1);
-        omap_uart_resume_idle(0);
-        if (!is_suspending())
-                console_unlock();
 no_sleep:
        omap2_gpio_resume_after_idle();
@@ -238,8 +222,6 @@ static int omap2_can_sleep(void)
 {
        if (omap2_fclks_active())
                return 0;
-        if (!omap_uart_can_sleep())
-                return 0;
        if (osc_ck->usecount > 1)
                return 0;
        if (omap_dma_running())
@@ -290,7 +272,6 @@ static int omap2_pm_suspend(void)
        mir1 = omap_readl(0x480fe0a4);
        omap_writel(1 << 5, 0x480fe0ac);
-        omap_uart_prepare_suspend();
        omap2_enter_full_retention();
        omap_writel(mir1, 0x480fe0a4);
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index efa66494c1e3..fc6987578920 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -28,7 +28,6 @@
 #include <linux/clk.h>
 #include <linux/delay.h>
 #include <linux/slab.h>
-#include <linux/console.h>
 #include <trace/events/power.h>
 #include <asm/suspend.h>
@@ -36,12 +35,12 @@
 #include <plat/sram.h>
 #include "clockdomain.h"
 #include "powerdomain.h"
-#include <plat/serial.h>
 #include <plat/sdrc.h>
 #include <plat/prcm.h>
 #include <plat/gpmc.h>
 #include <plat/dma.h>
+#include "common.h"
 #include "cm2xxx_3xxx.h"
 #include "cm-regbits-34xx.h"
 #include "prm-regbits-34xx.h"
@@ -53,15 +52,6 @@
 #ifdef CONFIG_SUSPEND
 static suspend_state_t suspend_state = PM_SUSPEND_ON;
-static inline bool is_suspending(void)
-{
-        return (suspend_state != PM_SUSPEND_ON) && console_suspend_enabled;
-}
-#else
-static inline bool is_suspending(void)
-{
-        return false;
-}
 #endif
 /* pm34xx errata defined in pm.h */
@@ -194,7 +184,7 @@ static void omap3_save_secure_ram_context(void)
 * that any peripheral wake-up events occurring while attempting to
 * clear the PM_WKST_x are detected and cleared.
 */
-static int prcm_clear_mod_irqs(s16 module, u8 regs)
+static int prcm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits)
 {
        u32 wkst, fclk, iclk, clken;
        u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
@@ -206,6 +196,7 @@ static int prcm_clear_mod_irqs(s16 module, u8 regs)
        wkst = omap2_prm_read_mod_reg(module, wkst_off);
        wkst &= omap2_prm_read_mod_reg(module, grpsel_off);
+        wkst &= ~ignore_bits;
        if (wkst) {
                iclk = omap2_cm_read_mod_reg(module, iclk_off);
                fclk = omap2_cm_read_mod_reg(module, fclk_off);
@@ -221,6 +212,7 @@ static int prcm_clear_mod_irqs(s16 module, u8 regs)
                        omap2_cm_set_mod_reg_bits(clken, module, fclk_off);
                        omap2_prm_write_mod_reg(wkst, module, wkst_off);
                        wkst = omap2_prm_read_mod_reg(module, wkst_off);
+                        wkst &= ~ignore_bits;
                        c++;
                }
                omap2_cm_write_mod_reg(iclk, module, iclk_off);
@@ -230,76 +222,35 @@ static int prcm_clear_mod_irqs(s16 module, u8 regs)
        return c;
 }
-static int _prcm_int_handle_wakeup(void)
+static irqreturn_t _prcm_int_handle_io(int irq, void *unused)
 {
        int c;
-        c = prcm_clear_mod_irqs(WKUP_MOD, 1);
+        c = prcm_clear_mod_irqs(WKUP_MOD, 1,
-        c += prcm_clear_mod_irqs(CORE_MOD, 1);
+                ~(OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK));
-        c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1);
-        if (omap_rev() > OMAP3430_REV_ES1_0) {
-                c += prcm_clear_mod_irqs(CORE_MOD, 3);
-                c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1);
-        }
-        return c;
+        return c ? IRQ_HANDLED : IRQ_NONE;
 }
-/*
+static irqreturn_t _prcm_int_handle_wakeup(int irq, void *unused)
- * PRCM Interrupt Handler
- *
- * The PRM_IRQSTATUS_MPU register indicates if there are any pending
- * interrupts from the PRCM for the MPU. These bits must be cleared in
- * order to clear the PRCM interrupt. The PRCM interrupt handler is
- * implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear
- * the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU
- * register indicates that a wake-up event is pending for the MPU and
- * this bit can only be cleared if the all the wake-up events latched
- * in the various PM_WKST_x registers have been cleared. The interrupt
- * handler is implemented using a do-while loop so that if a wake-up
- * event occurred during the processing of the prcm interrupt handler
- * (setting a bit in the corresponding PM_WKST_x register and thus
- * preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register)
- * this would be handled.
- */
-static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
 {
-        u32 irqenable_mpu, irqstatus_mpu;
+        int c;
-        int c = 0;
-        irqenable_mpu = omap2_prm_read_mod_reg(OCP_MOD,
-                                         OMAP3_PRM_IRQENABLE_MPU_OFFSET);
-        irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD,
-                                         OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
-        irqstatus_mpu &= irqenable_mpu;
-        do {
-                if (irqstatus_mpu & (OMAP3430_WKUP_ST_MASK |
-                                     OMAP3430_IO_ST_MASK)) {
-                        c = _prcm_int_handle_wakeup();
-                        /*
-                         * Is the MPU PRCM interrupt handler racing with the
-                         * IVA2 PRCM interrupt handler ?
-                         */
-                        WARN(c == 0, "prcm: WARNING: PRCM indicated MPU wakeup "
-                             "but no wakeup sources are marked\n");
-                } else {
-                        /* XXX we need to expand our PRCM interrupt handler */
-                        WARN(1, "prcm: WARNING: PRCM interrupt received, but "
-                             "no code to handle it (%08x)\n", irqstatus_mpu);
-                }
-                omap2_prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
-                                        OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
-                irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD,
-                                        OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
-                irqstatus_mpu &= irqenable_mpu;
-        } while (irqstatus_mpu);
+        /*
+         * Clear all except ST_IO and ST_IO_CHAIN for wkup module,
+         * these are handled in a separate handler to avoid acking
+         * IO events before parsing in mux code
+         */
+        c = prcm_clear_mod_irqs(WKUP_MOD, 1,
+                OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK);
+        c += prcm_clear_mod_irqs(CORE_MOD, 1, 0);
+        c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1, 0);
+        if (omap_rev() > OMAP3430_REV_ES1_0) {
+                c += prcm_clear_mod_irqs(CORE_MOD, 3, 0);
+                c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, 0);
+        }
-        return IRQ_HANDLED;
+        return c ? IRQ_HANDLED : IRQ_NONE;
 }
 static void omap34xx_save_context(u32 *save)
@@ -375,20 +326,11 @@ void omap_sram_idle(void)
                        omap3_enable_io_chain();
        }
-        /* Block console output in case it is on one of the OMAP UARTs */
-        if (!is_suspending())
-                if (per_next_state < PWRDM_POWER_ON ||
-                    core_next_state < PWRDM_POWER_ON)
-                        if (!console_trylock())
-                                goto console_still_active;
        pwrdm_pre_transition();
        /* PER */
        if (per_next_state < PWRDM_POWER_ON) {
                per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0;
-                omap_uart_prepare_idle(2);
-                omap_uart_prepare_idle(3);
                omap2_gpio_prepare_for_idle(per_going_off);
                if (per_next_state == PWRDM_POWER_OFF)
                                omap3_per_save_context();
@@ -396,8 +338,6 @@ void omap_sram_idle(void)
        /* CORE */
        if (core_next_state < PWRDM_POWER_ON) {
-                omap_uart_prepare_idle(0);
-                omap_uart_prepare_idle(1);
                if (core_next_state == PWRDM_POWER_OFF) {
                        omap3_core_save_context();
                        omap3_cm_save_context();
@@ -446,8 +386,6 @@ void omap_sram_idle(void)
                        omap3_sram_restore_context();
                        omap2_sms_restore_context();
                }
-                omap_uart_resume_idle(0);
-                omap_uart_resume_idle(1);
                if (core_next_state == PWRDM_POWER_OFF)
                        omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
                                               OMAP3430_GR_MOD,
@@ -463,14 +401,8 @@ void omap_sram_idle(void)
                omap2_gpio_resume_after_idle();
                if (per_prev_state == PWRDM_POWER_OFF)
                        omap3_per_restore_context();
-                omap_uart_resume_idle(2);
-                omap_uart_resume_idle(3);
        }
-        if (!is_suspending())
-                console_unlock();
-console_still_active:
        /* Disable IO-PAD and IO-CHAIN wakeup */
        if (omap3_has_io_wakeup() &&
            (per_next_state < PWRDM_POWER_ON ||
@@ -484,21 +416,11 @@ console_still_active:
        clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]);
 }
-int omap3_can_sleep(void)
-{
-        if (!omap_uart_can_sleep())
-                return 0;
-        return 1;
-}
 static void omap3_pm_idle(void)
 {
        local_irq_disable();
        local_fiq_disable();
-        if (!omap3_can_sleep())
-                goto out;
        if (omap_irq_pending() || need_resched())
                goto out;
@@ -532,7 +454,6 @@ static int omap3_pm_suspend(void)
                        goto restore;
        }
-        omap_uart_prepare_suspend();
        omap3_intc_suspend();
        omap_sram_idle();
@@ -579,22 +500,27 @@ static int omap3_pm_begin(suspend_state_t state)
 {
        disable_hlt();
        suspend_state = state;
-        omap_uart_enable_irqs(0);
+        omap_prcm_irq_prepare();
        return 0;
 }
 static void omap3_pm_end(void)
 {
        suspend_state = PM_SUSPEND_ON;
-        omap_uart_enable_irqs(1);
        enable_hlt();
        return;
 }
+static void omap3_pm_finish(void)
+{
+        omap_prcm_irq_complete();
+}
 static const struct platform_suspend_ops omap_pm_ops = {
        .begin          = omap3_pm_begin,
        .end            = omap3_pm_end,
        .enter          = omap3_pm_enter,
+        .finish         = omap3_pm_finish,
        .valid          = suspend_valid_only_mem,
 };
 #endif /* CONFIG_SUSPEND */
@@ -700,10 +626,6 @@ static void __init prcm_setup_regs(void)
                          OMAP3430_GRPSEL_GPT1_MASK |
                          OMAP3430_GRPSEL_GPT12_MASK,
                          WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
-        /* For some reason IO doesn't generate wakeup event even if
-         * it is selected to mpu wakeup goup */
-        omap2_prm_write_mod_reg(OMAP3430_IO_EN_MASK | OMAP3430_WKUP_EN_MASK,
-                          OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
        /* Enable PM_WKEN to support DSS LPR */
        omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
@@ -880,12 +802,21 @@ static int __init omap3_pm_init(void)
         * supervised mode for powerdomains */
        prcm_setup_regs();
-        ret = request_irq(INT_34XX_PRCM_MPU_IRQ,
+        ret = request_irq(omap_prcm_event_to_irq("wkup"),
-                          (irq_handler_t)prcm_interrupt_handler,
+                _prcm_int_handle_wakeup, IRQF_NO_SUSPEND, "pm_wkup", NULL);
-                          IRQF_DISABLED, "prcm", NULL);
+        if (ret) {
+                pr_err("pm: Failed to request pm_wkup irq\n");
+                goto err1;
+        }
+        /* IO interrupt is shared with mux code */
+        ret = request_irq(omap_prcm_event_to_irq("io"),
+                _prcm_int_handle_io, IRQF_SHARED | IRQF_NO_SUSPEND, "pm_io",
+                omap3_pm_init);
        if (ret) {
-                printk(KERN_ERR "request_irq failed to register for 0x%x\n",
+                pr_err("pm: Failed to request pm_io irq\n");
-                       INT_34XX_PRCM_MPU_IRQ);
                goto err1;
        }
diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
index 59a870be8390..c264ef7219c1 100644
--- a/arch/arm/mach-omap2/pm44xx.c
+++ b/arch/arm/mach-omap2/pm44xx.c
@@ -1,8 +1,9 @@
 /*
 * OMAP4 Power Management Routines
 *
- * Copyright (C) 2010 Texas Instruments, Inc.
+ * Copyright (C) 2010-2011 Texas Instruments, Inc.
 * Rajendra Nayak <rnayak@ti.com>
+ * Santosh Shilimkar <santosh.shilimkar@ti.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
@@ -16,14 +17,17 @@
 #include <linux/err.h>
 #include <linux/slab.h>
+#include "common.h"
+#include "clockdomain.h"
 #include "powerdomain.h"
-#include <mach/omap4-common.h>
+#include "pm.h"
 struct power_state {
        struct powerdomain *pwrdm;
        u32 next_state;
 #ifdef CONFIG_SUSPEND
        u32 saved_state;
+        u32 saved_logic_state;
 #endif
        struct list_head node;
 };
@@ -33,7 +37,50 @@ static LIST_HEAD(pwrst_list);
 #ifdef CONFIG_SUSPEND
 static int omap4_pm_suspend(void)
 {
-        do_wfi();
+        struct power_state *pwrst;
+        int state, ret = 0;
+        u32 cpu_id = smp_processor_id();
+        /* Save current powerdomain state */
+        list_for_each_entry(pwrst, &pwrst_list, node) {
+                pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
+                pwrst->saved_logic_state = pwrdm_read_logic_retst(pwrst->pwrdm);
+        }
+        /* Set targeted power domain states by suspend */
+        list_for_each_entry(pwrst, &pwrst_list, node) {
+                omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
+                pwrdm_set_logic_retst(pwrst->pwrdm, PWRDM_POWER_OFF);
+        }
+        /*
+         * For MPUSS to hit power domain retention(CSWR or OSWR),
+         * CPU0 and CPU1 power domains need to be in OFF or DORMANT state,
+         * since CPU power domain CSWR is not supported by hardware
+         * Only master CPU follows suspend path. All other CPUs follow
+         * CPU hotplug path in system wide suspend. On OMAP4, CPU power
+         * domain CSWR is not supported by hardware.
+         * More details can be found in OMAP4430 TRM section 4.3.4.2.
+         */
+        omap4_enter_lowpower(cpu_id, PWRDM_POWER_OFF);
+        /* Restore next powerdomain state */
+        list_for_each_entry(pwrst, &pwrst_list, node) {
+                state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
+                if (state > pwrst->next_state) {
+                        pr_info("Powerdomain (%s) didn't enter "
+                               "target state %d\n",
+                               pwrst->pwrdm->name, pwrst->next_state);
+                        ret = -1;
+                }
+                omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
+                pwrdm_set_logic_retst(pwrst->pwrdm, pwrst->saved_logic_state);
+        }
+        if (ret)
+                pr_crit("Could not enter target state in pm_suspend\n");
+        else
+                pr_info("Successfully put all powerdomains to target state\n");
        return 0;
 }
@@ -73,6 +120,22 @@ static const struct platform_suspend_ops omap_pm_ops = {
 };
 #endif /* CONFIG_SUSPEND */
+/*
+ * Enable hardware supervised mode for all clockdomains if it's
+ * supported. Initiate sleep transition for other clockdomains, if
+ * they are not used
+ */
+static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
+{
+        if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
+                clkdm_allow_idle(clkdm);
+        else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
+                        atomic_read(&clkdm->usecount) == 0)
+                clkdm_sleep(clkdm);
+        return 0;
+}
 static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
 {
        struct power_state *pwrst;
@@ -80,14 +143,48 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
        if (!pwrdm->pwrsts)
                return 0;
+        /*
+         * Skip CPU0 and CPU1 power domains. CPU1 is programmed
+         * through hotplug path and CPU0 explicitly programmed
+         * further down in the code path
+         */
+        if (!strncmp(pwrdm->name, "cpu", 3))
+                return 0;
+        /*
+         * FIXME: Remove this check when core retention is supported
+         * Only MPUSS power domain is added in the list.
+         */
+        if (strcmp(pwrdm->name, "mpu_pwrdm"))
+                return 0;
        pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
        if (!pwrst)
                return -ENOMEM;
        pwrst->pwrdm = pwrdm;
-        pwrst->next_state = PWRDM_POWER_ON;
+        pwrst->next_state = PWRDM_POWER_RET;
        list_add(&pwrst->node, &pwrst_list);
-        return pwrdm_set_next_pwrst(pwrst->pwrdm, pwrst->next_state);
+        return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
+}
+/**
+ * omap_default_idle - OMAP4 default ilde routine.'
+ *
+ * Implements OMAP4 memory, IO ordering requirements which can't be addressed
+ * with default arch_idle() hook. Used by all CPUs with !CONFIG_CPUIDLE and
+ * by secondary CPU with CONFIG_CPUIDLE.
+ */
+static void omap_default_idle(void)
+{
+        local_irq_disable();
+        local_fiq_disable();
+        omap_do_wfi();
+        local_fiq_enable();
+        local_irq_enable();
 }
 /**
@@ -99,10 +196,17 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
 static int __init omap4_pm_init(void)
 {
        int ret;
+        struct clockdomain *emif_clkdm, *mpuss_clkdm, *l3_1_clkdm;
+        struct clockdomain *ducati_clkdm, *l3_2_clkdm, *l4_per_clkdm;
        if (!cpu_is_omap44xx())
                return -ENODEV;
+        if (omap_rev() == OMAP4430_REV_ES1_0) {
+                WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
+                return -ENODEV;
+        }
        pr_err("Power Management for TI OMAP4.\n");
        ret = pwrdm_for_each(pwrdms_setup, NULL);
@@ -111,10 +215,51 @@ static int __init omap4_pm_init(void)
                goto err2;
        }
+        /*
+         * The dynamic dependency between MPUSS -> MEMIF and
+         * MPUSS -> L4_PER/L3_* and DUCATI -> L3_* doesn't work as
+         * expected. The hardware recommendation is to enable static
+         * dependencies for these to avoid system lock ups or random crashes.
+         */
+        mpuss_clkdm = clkdm_lookup("mpuss_clkdm");
+        emif_clkdm = clkdm_lookup("l3_emif_clkdm");
+        l3_1_clkdm = clkdm_lookup("l3_1_clkdm");
+        l3_2_clkdm = clkdm_lookup("l3_2_clkdm");
+        l4_per_clkdm = clkdm_lookup("l4_per_clkdm");
+        ducati_clkdm = clkdm_lookup("ducati_clkdm");
+        if ((!mpuss_clkdm) || (!emif_clkdm) || (!l3_1_clkdm) ||
+                (!l3_2_clkdm) || (!ducati_clkdm) || (!l4_per_clkdm))
+                goto err2;
+        ret = clkdm_add_wkdep(mpuss_clkdm, emif_clkdm);
+        ret |= clkdm_add_wkdep(mpuss_clkdm, l3_1_clkdm);
+        ret |= clkdm_add_wkdep(mpuss_clkdm, l3_2_clkdm);
+        ret |= clkdm_add_wkdep(mpuss_clkdm, l4_per_clkdm);
+        ret |= clkdm_add_wkdep(ducati_clkdm, l3_1_clkdm);
+        ret |= clkdm_add_wkdep(ducati_clkdm, l3_2_clkdm);
+        if (ret) {
+                pr_err("Failed to add MPUSS -> L3/EMIF/L4PER, DUCATI -> L3 "
+                                "wakeup dependency\n");
+                goto err2;
+        }
+        ret = omap4_mpuss_init();
+        if (ret) {
+                pr_err("Failed to initialise OMAP4 MPUSS\n");
+                goto err2;
+        }
+        (void) clkdm_for_each(clkdms_setup, NULL);
 #ifdef CONFIG_SUSPEND
        suspend_set_ops(&omap_pm_ops);
 #endif /* CONFIG_SUSPEND */
+        /* Overwrite the default arch_idle() */
+        pm_idle = omap_default_idle;
+        omap4_idle_init();
 err2:
        return ret;
 }
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index 0363dcb0ef93..0f69d8fc5628 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -4,7 +4,7 @@
 /*
 * OMAP2/3 PRCM base and module definitions
 *
- * Copyright (C) 2007-2009 Texas Instruments, Inc.
+ * Copyright (C) 2007-2009, 2011 Texas Instruments, Inc.
 * Copyright (C) 2007-2009 Nokia Corporation
 *
 * Written by Paul Walmsley
@@ -408,6 +408,79 @@
 extern void __iomem *prm_base;
 extern void __iomem *cm_base;
 extern void __iomem *cm2_base;
+/**
+ * struct omap_prcm_irq - describes a PRCM interrupt bit
+ * @name: a short name describing the interrupt type, e.g. "wkup" or "io"
+ * @offset: the bit shift of the interrupt inside the IRQ{ENABLE,STATUS} regs
+ * @priority: should this interrupt be handled before @priority=false IRQs?
+ *
+ * Describes interrupt bits inside the PRM_IRQ{ENABLE,STATUS}_MPU* registers.
+ * On systems with multiple PRM MPU IRQ registers, the bitfields read from
+ * the registers are concatenated, so @offset could be > 31 on these systems -
+ * see omap_prm_irq_handler() for more details.  I/O ring interrupts should
+ * have @priority set to true.
+ */
+struct omap_prcm_irq {
+        const char *name;
+        unsigned int offset;
+        bool priority;
+};
+/**
+ * struct omap_prcm_irq_setup - PRCM interrupt controller details
+ * @ack: PRM register offset for the first PRM_IRQSTATUS_MPU register
+ * @mask: PRM register offset for the first PRM_IRQENABLE_MPU register
+ * @nr_regs: number of PRM_IRQ{STATUS,ENABLE}_MPU* registers
+ * @nr_irqs: number of entries in the @irqs array
+ * @irqs: ptr to an array of PRCM interrupt bits (see @nr_irqs)
+ * @irq: MPU IRQ asserted when a PRCM interrupt arrives
+ * @read_pending_irqs: fn ptr to determine if any PRCM IRQs are pending
+ * @ocp_barrier: fn ptr to force buffered PRM writes to complete
+ * @save_and_clear_irqen: fn ptr to save and clear IRQENABLE regs
+ * @restore_irqen: fn ptr to save and clear IRQENABLE regs
+ * @saved_mask: IRQENABLE regs are saved here during suspend
+ * @priority_mask: 1 bit per IRQ, set to 1 if omap_prcm_irq.priority = true
+ * @base_irq: base dynamic IRQ number, returned from irq_alloc_descs() in init
+ * @suspended: set to true after Linux suspend code has called our ->prepare()
+ * @suspend_save_flag: set to true after IRQ masks have been saved and disabled
+ *
+ * @saved_mask, @priority_mask, @base_irq, @suspended, and
+ * @suspend_save_flag are populated dynamically, and are not to be
+ * specified in static initializers.
+ */
+struct omap_prcm_irq_setup {
+        u16 ack;
+        u16 mask;
+        u8 nr_regs;
+        u8 nr_irqs;
+        const struct omap_prcm_irq *irqs;
+        int irq;
+        void (*read_pending_irqs)(unsigned long *events);
+        void (*ocp_barrier)(void);
+        void (*save_and_clear_irqen)(u32 *saved_mask);
+        void (*restore_irqen)(u32 *saved_mask);
+        u32 *saved_mask;
+        u32 *priority_mask;
+        int base_irq;
+        bool suspended;
+        bool suspend_save_flag;
+};
+/* OMAP_PRCM_IRQ: convenience macro for creating struct omap_prcm_irq records */
+#define OMAP_PRCM_IRQ(_name, _offset, _priority) {      \
+        .name = _name,                                  \
+        .offset = _offset,                              \
+        .priority = _priority                           \
+        }
+extern void omap_prcm_irq_cleanup(void);
+extern int omap_prcm_register_chain_handler(
+        struct omap_prcm_irq_setup *irq_setup);
+extern int omap_prcm_event_to_irq(const char *event);
+extern void omap_prcm_irq_prepare(void);
+extern void omap_prcm_irq_complete(void);
 # endif
 #endif
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index 597e2da831b3..c35e5cea9f8f 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -26,7 +26,7 @@
 #include <linux/export.h>
 #include <mach/system.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/prcm.h>
 #include <plat/irqs.h>
diff --git a/arch/arm/mach-omap2/prcm_mpu44xx.c b/arch/arm/mach-omap2/prcm_mpu44xx.c
index 171fe171a749..ca669b50f390 100644
--- a/arch/arm/mach-omap2/prcm_mpu44xx.c
+++ b/arch/arm/mach-omap2/prcm_mpu44xx.c
@@ -15,7 +15,7 @@
 #include <linux/err.h>
 #include <linux/io.h>
-#include <plat/common.h>
+#include "common.h"
 #include "prcm_mpu44xx.h"
 #include "cm-regbits-44xx.h"
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c
index f02d87f68e54..c1c4d86a79a8 100644
--- a/arch/arm/mach-omap2/prm2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c
@@ -1,7 +1,7 @@
 /*
 * OMAP2/3 PRM module functions
 *
- * Copyright (C) 2010 Texas Instruments, Inc.
+ * Copyright (C) 2010-2011 Texas Instruments, Inc.
 * Copyright (C) 2010 Nokia Corporation
 * Benoît Cousson
 * Paul Walmsley
@@ -16,7 +16,7 @@
 #include <linux/err.h>
 #include <linux/io.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/cpu.h>
 #include <plat/prcm.h>
@@ -27,6 +27,24 @@
 #include "prm-regbits-24xx.h"
 #include "prm-regbits-34xx.h"
+static const struct omap_prcm_irq omap3_prcm_irqs[] = {
+        OMAP_PRCM_IRQ("wkup",   0,      0),
+        OMAP_PRCM_IRQ("io",     9,      1),
+};
+static struct omap_prcm_irq_setup omap3_prcm_irq_setup = {
+        .ack                    = OMAP3_PRM_IRQSTATUS_MPU_OFFSET,
+        .mask                   = OMAP3_PRM_IRQENABLE_MPU_OFFSET,
+        .nr_regs                = 1,
+        .irqs                   = omap3_prcm_irqs,
+        .nr_irqs                = ARRAY_SIZE(omap3_prcm_irqs),
+        .irq                    = INT_34XX_PRCM_MPU_IRQ,
+        .read_pending_irqs      = &omap3xxx_prm_read_pending_irqs,
+        .ocp_barrier            = &omap3xxx_prm_ocp_barrier,
+        .save_and_clear_irqen   = &omap3xxx_prm_save_and_clear_irqen,
+        .restore_irqen          = &omap3xxx_prm_restore_irqen,
+};
 u32 omap2_prm_read_mod_reg(s16 module, u16 idx)
 {
        return __raw_readl(prm_base + module + idx);
@@ -212,3 +230,80 @@ u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset)
 {
        return omap2_prm_rmw_mod_reg_bits(mask, bits, OMAP3430_GR_MOD, offset);
 }
+/**
+ * omap3xxx_prm_read_pending_irqs - read pending PRM MPU IRQs into @events
+ * @events: ptr to a u32, preallocated by caller
+ *
+ * Read PRM_IRQSTATUS_MPU bits, AND'ed with the currently-enabled PRM
+ * MPU IRQs, and store the result into the u32 pointed to by @events.
+ * No return value.
+ */
+void omap3xxx_prm_read_pending_irqs(unsigned long *events)
+{
+        u32 mask, st;
+        /* XXX Can the mask read be avoided (e.g., can it come from RAM?) */
+        mask = omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
+        st = omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
+        events[0] = mask & st;
+}
+/**
+ * omap3xxx_prm_ocp_barrier - force buffered MPU writes to the PRM to complete
+ *
+ * Force any buffered writes to the PRM IP block to complete.  Needed
+ * by the PRM IRQ handler, which reads and writes directly to the IP
+ * block, to avoid race conditions after acknowledging or clearing IRQ
+ * bits.  No return value.
+ */
+void omap3xxx_prm_ocp_barrier(void)
+{
+        omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_REVISION_OFFSET);
+}
+/**
+ * omap3xxx_prm_save_and_clear_irqen - save/clear PRM_IRQENABLE_MPU reg
+ * @saved_mask: ptr to a u32 array to save IRQENABLE bits
+ *
+ * Save the PRM_IRQENABLE_MPU register to @saved_mask.  @saved_mask
+ * must be allocated by the caller.  Intended to be used in the PRM
+ * interrupt handler suspend callback.  The OCP barrier is needed to
+ * ensure the write to disable PRM interrupts reaches the PRM before
+ * returning; otherwise, spurious interrupts might occur.  No return
+ * value.
+ */
+void omap3xxx_prm_save_and_clear_irqen(u32 *saved_mask)
+{
+        saved_mask[0] = omap2_prm_read_mod_reg(OCP_MOD,
+                                               OMAP3_PRM_IRQENABLE_MPU_OFFSET);
+        omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
+        /* OCP barrier */
+        omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_REVISION_OFFSET);
+}
+/**
+ * omap3xxx_prm_restore_irqen - set PRM_IRQENABLE_MPU register from args
+ * @saved_mask: ptr to a u32 array of IRQENABLE bits saved previously
+ *
+ * Restore the PRM_IRQENABLE_MPU register from @saved_mask.  Intended
+ * to be used in the PRM interrupt handler resume callback to restore
+ * values saved by omap3xxx_prm_save_and_clear_irqen().  No OCP
+ * barrier should be needed here; any pending PRM interrupts will fire
+ * once the writes reach the PRM.  No return value.
+ */
+void omap3xxx_prm_restore_irqen(u32 *saved_mask)
+{
+        omap2_prm_write_mod_reg(saved_mask[0], OCP_MOD,
+                                OMAP3_PRM_IRQENABLE_MPU_OFFSET);
+}
+static int __init omap3xxx_prcm_init(void)
+{
+        if (cpu_is_omap34xx())
+                return omap_prcm_register_chain_handler(&omap3_prcm_irq_setup);
+        return 0;
+}
+subsys_initcall(omap3xxx_prcm_init);
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.h b/arch/arm/mach-omap2/prm2xxx_3xxx.h
index cef533df0861..70ac2a19dc5f 100644
--- a/arch/arm/mach-omap2/prm2xxx_3xxx.h
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.h
@@ -1,7 +1,7 @@
 /*
 * OMAP2/3 Power/Reset Management (PRM) register definitions
 *
- * Copyright (C) 2007-2009 Texas Instruments, Inc.
+ * Copyright (C) 2007-2009, 2011 Texas Instruments, Inc.
 * Copyright (C) 2008-2010 Nokia Corporation
 * Paul Walmsley
 *
@@ -314,6 +314,13 @@ void omap3_prm_vp_clear_txdone(u8 vp_id);
 extern u32 omap3_prm_vcvp_read(u8 offset);
 extern void omap3_prm_vcvp_write(u32 val, u8 offset);
 extern u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
+/* PRM interrupt-related functions */
+extern void omap3xxx_prm_read_pending_irqs(unsigned long *events);
+extern void omap3xxx_prm_ocp_barrier(void);
+extern void omap3xxx_prm_save_and_clear_irqen(u32 *saved_mask);
+extern void omap3xxx_prm_restore_irqen(u32 *saved_mask);
 #endif  /* CONFIG_ARCH_OMAP4 */
 #endif
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index 495a31a7e8a7..33dd655e6aab 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -17,7 +17,7 @@
 #include <linux/err.h>
 #include <linux/io.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/cpu.h>
 #include <plat/prcm.h>
@@ -27,6 +27,24 @@
 #include "prcm44xx.h"
 #include "prminst44xx.h"
+static const struct omap_prcm_irq omap4_prcm_irqs[] = {
+        OMAP_PRCM_IRQ("wkup",   0,      0),
+        OMAP_PRCM_IRQ("io",     9,      1),
+};
+static struct omap_prcm_irq_setup omap4_prcm_irq_setup = {
+        .ack                    = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
+        .mask                   = OMAP4_PRM_IRQENABLE_MPU_OFFSET,
+        .nr_regs                = 2,
+        .irqs                   = omap4_prcm_irqs,
+        .nr_irqs                = ARRAY_SIZE(omap4_prcm_irqs),
+        .irq                    = OMAP44XX_IRQ_PRCM,
+        .read_pending_irqs      = &omap44xx_prm_read_pending_irqs,
+        .ocp_barrier            = &omap44xx_prm_ocp_barrier,
+        .save_and_clear_irqen   = &omap44xx_prm_save_and_clear_irqen,
+        .restore_irqen          = &omap44xx_prm_restore_irqen,
+};
 /* PRM low-level functions */
 /* Read a register in a CM/PRM instance in the PRM module */
@@ -121,3 +139,101 @@ u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset)
                                               OMAP4430_PRM_DEVICE_INST,
                                               offset);
 }
+static inline u32 _read_pending_irq_reg(u16 irqen_offs, u16 irqst_offs)
+{
+        u32 mask, st;
+        /* XXX read mask from RAM? */
+        mask = omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST, irqen_offs);
+        st = omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST, irqst_offs);
+        return mask & st;
+}
+/**
+ * omap44xx_prm_read_pending_irqs - read pending PRM MPU IRQs into @events
+ * @events: ptr to two consecutive u32s, preallocated by caller
+ *
+ * Read PRM_IRQSTATUS_MPU* bits, AND'ed with the currently-enabled PRM
+ * MPU IRQs, and store the result into the two u32s pointed to by @events.
+ * No return value.
+ */
+void omap44xx_prm_read_pending_irqs(unsigned long *events)
+{
+        events[0] = _read_pending_irq_reg(OMAP4_PRM_IRQENABLE_MPU_OFFSET,
+                                          OMAP4_PRM_IRQSTATUS_MPU_OFFSET);
+        events[1] = _read_pending_irq_reg(OMAP4_PRM_IRQENABLE_MPU_2_OFFSET,
+                                          OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET);
+}
+/**
+ * omap44xx_prm_ocp_barrier - force buffered MPU writes to the PRM to complete
+ *
+ * Force any buffered writes to the PRM IP block to complete.  Needed
+ * by the PRM IRQ handler, which reads and writes directly to the IP
+ * block, to avoid race conditions after acknowledging or clearing IRQ
+ * bits.  No return value.
+ */
+void omap44xx_prm_ocp_barrier(void)
+{
+        omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
+                                OMAP4_REVISION_PRM_OFFSET);
+}
+/**
+ * omap44xx_prm_save_and_clear_irqen - save/clear PRM_IRQENABLE_MPU* regs
+ * @saved_mask: ptr to a u32 array to save IRQENABLE bits
+ *
+ * Save the PRM_IRQENABLE_MPU and PRM_IRQENABLE_MPU_2 registers to
+ * @saved_mask.  @saved_mask must be allocated by the caller.
+ * Intended to be used in the PRM interrupt handler suspend callback.
+ * The OCP barrier is needed to ensure the write to disable PRM
+ * interrupts reaches the PRM before returning; otherwise, spurious
+ * interrupts might occur.  No return value.
+ */
+void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask)
+{
+        saved_mask[0] =
+                omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
+                                        OMAP4_PRM_IRQSTATUS_MPU_OFFSET);
+        saved_mask[1] =
+                omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
+                                        OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET);
+        omap4_prm_write_inst_reg(0, OMAP4430_PRM_DEVICE_INST,
+                                 OMAP4_PRM_IRQENABLE_MPU_OFFSET);
+        omap4_prm_write_inst_reg(0, OMAP4430_PRM_DEVICE_INST,
+                                 OMAP4_PRM_IRQENABLE_MPU_2_OFFSET);
+        /* OCP barrier */
+        omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
+                                OMAP4_REVISION_PRM_OFFSET);
+}
+/**
+ * omap44xx_prm_restore_irqen - set PRM_IRQENABLE_MPU* registers from args
+ * @saved_mask: ptr to a u32 array of IRQENABLE bits saved previously
+ *
+ * Restore the PRM_IRQENABLE_MPU and PRM_IRQENABLE_MPU_2 registers from
+ * @saved_mask.  Intended to be used in the PRM interrupt handler resume
+ * callback to restore values saved by omap44xx_prm_save_and_clear_irqen().
+ * No OCP barrier should be needed here; any pending PRM interrupts will fire
+ * once the writes reach the PRM.  No return value.
+ */
+void omap44xx_prm_restore_irqen(u32 *saved_mask)
+{
+        omap4_prm_write_inst_reg(saved_mask[0], OMAP4430_PRM_DEVICE_INST,
+                                 OMAP4_PRM_IRQENABLE_MPU_OFFSET);
+        omap4_prm_write_inst_reg(saved_mask[1], OMAP4430_PRM_DEVICE_INST,
+                                 OMAP4_PRM_IRQENABLE_MPU_2_OFFSET);
+}
+static int __init omap4xxx_prcm_init(void)
+{
+        if (cpu_is_omap44xx())
+                return omap_prcm_register_chain_handler(&omap4_prcm_irq_setup);
+        return 0;
+}
+subsys_initcall(omap4xxx_prcm_init);
diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h
index 3d66ccd849d2..7978092946db 100644
--- a/arch/arm/mach-omap2/prm44xx.h
+++ b/arch/arm/mach-omap2/prm44xx.h
@@ -1,7 +1,7 @@
 /*
 * OMAP44xx PRM instance offset macros
 *
- * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ * Copyright (C) 2009-2011 Texas Instruments, Inc.
 * Copyright (C) 2009-2010 Nokia Corporation
 *
 * Paul Walmsley (paul@pwsan.com)
@@ -763,6 +763,12 @@ extern u32 omap4_prm_vcvp_read(u8 offset);
 extern void omap4_prm_vcvp_write(u32 val, u8 offset);
 extern u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
+/* PRM interrupt-related functions */
+extern void omap44xx_prm_read_pending_irqs(unsigned long *events);
+extern void omap44xx_prm_ocp_barrier(void);
+extern void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask);
+extern void omap44xx_prm_restore_irqen(u32 *saved_mask);
 # endif
 #endif
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
new file mode 100644
index 000000000000..860118ab43e2
--- /dev/null
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -0,0 +1,320 @@
+/*
+ * OMAP2+ common Power & Reset Management (PRM) IP block functions
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc.
+ * Tero Kristo <t-kristo@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *
+ * For historical purposes, the API used to configure the PRM
+ * interrupt handler refers to it as the "PRCM interrupt."  The
+ * underlying registers are located in the PRM on OMAP3/4.
+ *
+ * XXX This code should eventually be moved to a PRM driver.
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/slab.h>
+#include <mach/system.h>
+#include <plat/common.h>
+#include <plat/prcm.h>
+#include <plat/irqs.h>
+#include "prm2xxx_3xxx.h"
+#include "prm44xx.h"
+/*
+ * OMAP_PRCM_MAX_NR_PENDING_REG: maximum number of PRM_IRQ*_MPU regs
+ * XXX this is technically not needed, since
+ * omap_prcm_register_chain_handler() could allocate this based on the
+ * actual amount of memory needed for the SoC
+ */
+#define OMAP_PRCM_MAX_NR_PENDING_REG            2
+/*
+ * prcm_irq_chips: an array of all of the "generic IRQ chips" in use
+ * by the PRCM interrupt handler code.  There will be one 'chip' per
+ * PRM_{IRQSTATUS,IRQENABLE}_MPU register pair.  (So OMAP3 will have
+ * one "chip" and OMAP4 will have two.)
+ */
+static struct irq_chip_generic **prcm_irq_chips;
+/*
+ * prcm_irq_setup: the PRCM IRQ parameters for the hardware the code
+ * is currently running on.  Defined and passed by initialization code
+ * that calls omap_prcm_register_chain_handler().
+ */
+static struct omap_prcm_irq_setup *prcm_irq_setup;
+/* Private functions */
+/*
+ * Move priority events from events to priority_events array
+ */
+static void omap_prcm_events_filter_priority(unsigned long *events,
+        unsigned long *priority_events)
+{
+        int i;
+        for (i = 0; i < prcm_irq_setup->nr_regs; i++) {
+                priority_events[i] =
+                        events[i] & prcm_irq_setup->priority_mask[i];
+                events[i] ^= priority_events[i];
+        }
+}
+/*
+ * PRCM Interrupt Handler
+ *
+ * This is a common handler for the OMAP PRCM interrupts. Pending
+ * interrupts are detected by a call to prcm_pending_events and
+ * dispatched accordingly. Clearing of the wakeup events should be
+ * done by the SoC specific individual handlers.
+ */
+static void omap_prcm_irq_handler(unsigned int irq, struct irq_desc *desc)
+{
+        unsigned long pending[OMAP_PRCM_MAX_NR_PENDING_REG];
+        unsigned long priority_pending[OMAP_PRCM_MAX_NR_PENDING_REG];
+        struct irq_chip *chip = irq_desc_get_chip(desc);
+        unsigned int virtirq;
+        int nr_irqs = prcm_irq_setup->nr_regs * 32;
+        /*
+         * If we are suspended, mask all interrupts from PRCM level,
+         * this does not ack them, and they will be pending until we
+         * re-enable the interrupts, at which point the
+         * omap_prcm_irq_handler will be executed again.  The
+         * _save_and_clear_irqen() function must ensure that the PRM
+         * write to disable all IRQs has reached the PRM before
+         * returning, or spurious PRCM interrupts may occur during
+         * suspend.
+         */
+        if (prcm_irq_setup->suspended) {
+                prcm_irq_setup->save_and_clear_irqen(prcm_irq_setup->saved_mask);
+                prcm_irq_setup->suspend_save_flag = true;
+        }
+        /*
+         * Loop until all pending irqs are handled, since
+         * generic_handle_irq() can cause new irqs to come
+         */
+        while (!prcm_irq_setup->suspended) {
+                prcm_irq_setup->read_pending_irqs(pending);
+                /* No bit set, then all IRQs are handled */
+                if (find_first_bit(pending, nr_irqs) >= nr_irqs)
+                        break;
+                omap_prcm_events_filter_priority(pending, priority_pending);
+                /*
+                 * Loop on all currently pending irqs so that new irqs
+                 * cannot starve previously pending irqs
+                 */
+                /* Serve priority events first */
+                for_each_set_bit(virtirq, priority_pending, nr_irqs)
+                        generic_handle_irq(prcm_irq_setup->base_irq + virtirq);
+                /* Serve normal events next */
+                for_each_set_bit(virtirq, pending, nr_irqs)
+                        generic_handle_irq(prcm_irq_setup->base_irq + virtirq);
+        }
+        if (chip->irq_ack)
+                chip->irq_ack(&desc->irq_data);
+        if (chip->irq_eoi)
+                chip->irq_eoi(&desc->irq_data);
+        chip->irq_unmask(&desc->irq_data);
+        prcm_irq_setup->ocp_barrier(); /* avoid spurious IRQs */
+}
+/* Public functions */
+/**
+ * omap_prcm_event_to_irq - given a PRCM event name, returns the
+ * corresponding IRQ on which the handler should be registered
+ * @name: name of the PRCM interrupt bit to look up - see struct omap_prcm_irq
+ *
+ * Returns the Linux internal IRQ ID corresponding to @name upon success,
+ * or -ENOENT upon failure.
+ */
+int omap_prcm_event_to_irq(const char *name)
+{
+        int i;
+        if (!prcm_irq_setup || !name)
+                return -ENOENT;
+        for (i = 0; i < prcm_irq_setup->nr_irqs; i++)
+                if (!strcmp(prcm_irq_setup->irqs[i].name, name))
+                        return prcm_irq_setup->base_irq +
+                                prcm_irq_setup->irqs[i].offset;
+        return -ENOENT;
+}
+/**
+ * omap_prcm_irq_cleanup - reverses memory allocated and other steps
+ * done by omap_prcm_register_chain_handler()
+ *
+ * No return value.
+ */
+void omap_prcm_irq_cleanup(void)
+{
+        int i;
+        if (!prcm_irq_setup) {
+                pr_err("PRCM: IRQ handler not initialized; cannot cleanup\n");
+                return;
+        }
+        if (prcm_irq_chips) {
+                for (i = 0; i < prcm_irq_setup->nr_regs; i++) {
+                        if (prcm_irq_chips[i])
+                                irq_remove_generic_chip(prcm_irq_chips[i],
+                                        0xffffffff, 0, 0);
+                        prcm_irq_chips[i] = NULL;
+                }
+                kfree(prcm_irq_chips);
+                prcm_irq_chips = NULL;
+        }
+        kfree(prcm_irq_setup->saved_mask);
+        prcm_irq_setup->saved_mask = NULL;
+        kfree(prcm_irq_setup->priority_mask);
+        prcm_irq_setup->priority_mask = NULL;
+        irq_set_chained_handler(prcm_irq_setup->irq, NULL);
+        if (prcm_irq_setup->base_irq > 0)
+                irq_free_descs(prcm_irq_setup->base_irq,
+                        prcm_irq_setup->nr_regs * 32);
+        prcm_irq_setup->base_irq = 0;
+}
+void omap_prcm_irq_prepare(void)
+{
+        prcm_irq_setup->suspended = true;
+}
+void omap_prcm_irq_complete(void)
+{
+        prcm_irq_setup->suspended = false;
+        /* If we have not saved the masks, do not attempt to restore */
+        if (!prcm_irq_setup->suspend_save_flag)
+                return;
+        prcm_irq_setup->suspend_save_flag = false;
+        /*
+         * Re-enable all masked PRCM irq sources, this causes the PRCM
+         * interrupt to fire immediately if the events were masked
+         * previously in the chain handler
+         */
+        prcm_irq_setup->restore_irqen(prcm_irq_setup->saved_mask);
+}
+/**
+ * omap_prcm_register_chain_handler - initializes the prcm chained interrupt
+ * handler based on provided parameters
+ * @irq_setup: hardware data about the underlying PRM/PRCM
+ *
+ * Set up the PRCM chained interrupt handler on the PRCM IRQ.  Sets up
+ * one generic IRQ chip per PRM interrupt status/enable register pair.
+ * Returns 0 upon success, -EINVAL if called twice or if invalid
+ * arguments are passed, or -ENOMEM on any other error.
+ */
+int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup)
+{
+        int nr_regs = irq_setup->nr_regs;
+        u32 mask[OMAP_PRCM_MAX_NR_PENDING_REG];
+        int offset, i;
+        struct irq_chip_generic *gc;
+        struct irq_chip_type *ct;
+        if (!irq_setup)
+                return -EINVAL;
+        if (prcm_irq_setup) {
+                pr_err("PRCM: already initialized; won't reinitialize\n");
+                return -EINVAL;
+        }
+        if (nr_regs > OMAP_PRCM_MAX_NR_PENDING_REG) {
+                pr_err("PRCM: nr_regs too large\n");
+                return -EINVAL;
+        }
+        prcm_irq_setup = irq_setup;
+        prcm_irq_chips = kzalloc(sizeof(void *) * nr_regs, GFP_KERNEL);
+        prcm_irq_setup->saved_mask = kzalloc(sizeof(u32) * nr_regs, GFP_KERNEL);
+        prcm_irq_setup->priority_mask = kzalloc(sizeof(u32) * nr_regs,
+                GFP_KERNEL);
+        if (!prcm_irq_chips || !prcm_irq_setup->saved_mask ||
+            !prcm_irq_setup->priority_mask) {
+                pr_err("PRCM: kzalloc failed\n");
+                goto err;
+        }
+        memset(mask, 0, sizeof(mask));
+        for (i = 0; i < irq_setup->nr_irqs; i++) {
+                offset = irq_setup->irqs[i].offset;
+                mask[offset >> 5] |= 1 << (offset & 0x1f);
+                if (irq_setup->irqs[i].priority)
+                        irq_setup->priority_mask[offset >> 5] |=
+                                1 << (offset & 0x1f);
+        }
+        irq_set_chained_handler(irq_setup->irq, omap_prcm_irq_handler);
+        irq_setup->base_irq = irq_alloc_descs(-1, 0, irq_setup->nr_regs * 32,
+                0);
+        if (irq_setup->base_irq < 0) {
+                pr_err("PRCM: failed to allocate irq descs: %d\n",
+                        irq_setup->base_irq);
+                goto err;
+        }
+        for (i = 0; i <= irq_setup->nr_regs; i++) {
+                gc = irq_alloc_generic_chip("PRCM", 1,
+                        irq_setup->base_irq + i * 32, prm_base,
+                        handle_level_irq);
+                if (!gc) {
+                        pr_err("PRCM: failed to allocate generic chip\n");
+                        goto err;
+                }
+                ct = gc->chip_types;
+                ct->chip.irq_ack = irq_gc_ack_set_bit;
+                ct->chip.irq_mask = irq_gc_mask_clr_bit;
+                ct->chip.irq_unmask = irq_gc_mask_set_bit;
+                ct->regs.ack = irq_setup->ack + i * 4;
+                ct->regs.mask = irq_setup->mask + i * 4;
+                irq_setup_generic_chip(gc, mask[i], 0, IRQ_NOREQUEST, 0);
+                prcm_irq_chips[i] = gc;
+        }
+        return 0;
+err:
+        omap_prcm_irq_cleanup();
+        return -ENOMEM;
+}
diff --git a/arch/arm/mach-omap2/prminst44xx.c b/arch/arm/mach-omap2/prminst44xx.c
index 3a7bab16edd5..f6de5bc6b12a 100644
--- a/arch/arm/mach-omap2/prminst44xx.c
+++ b/arch/arm/mach-omap2/prminst44xx.c
@@ -16,7 +16,7 @@
 #include <linux/err.h>
 #include <linux/io.h>
-#include <plat/common.h>
+#include "common.h"
 #include "prm44xx.h"
 #include "prminst44xx.h"
diff --git a/arch/arm/mach-omap2/sdram-nokia.c b/arch/arm/mach-omap2/sdram-nokia.c
index 14caa228bc0d..ee3a8ad304cb 100644
--- a/arch/arm/mach-omap2/sdram-nokia.c
+++ b/arch/arm/mach-omap2/sdram-nokia.c
@@ -18,7 +18,7 @@
 #include <linux/io.h>
 #include <plat/io.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/clock.h>
 #include <plat/sdrc.h>
diff --git a/arch/arm/mach-omap2/sdrc.c b/arch/arm/mach-omap2/sdrc.c
index 8f2782874771..e3d345f46409 100644
--- a/arch/arm/mach-omap2/sdrc.c
+++ b/arch/arm/mach-omap2/sdrc.c
@@ -23,7 +23,7 @@
 #include <linux/clk.h>
 #include <linux/io.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/clock.h>
 #include <plat/sram.h>
diff --git a/arch/arm/mach-omap2/sdrc2xxx.c b/arch/arm/mach-omap2/sdrc2xxx.c
index ccdb010f169d..791a63cdceb2 100644
--- a/arch/arm/mach-omap2/sdrc2xxx.c
+++ b/arch/arm/mach-omap2/sdrc2xxx.c
@@ -24,7 +24,7 @@
 #include <linux/clk.h>
 #include <linux/io.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/clock.h>
 #include <plat/sram.h>
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index 9992dbfdfdb3..247d89478f24 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -19,26 +19,21 @@
 */
 #include <linux/kernel.h>
 #include <linux/init.h>
-#include <linux/serial_reg.h>
 #include <linux/clk.h>
 #include <linux/io.h>
 #include <linux/delay.h>
 #include <linux/platform_device.h>
 #include <linux/slab.h>
-#include <linux/serial_8250.h>
 #include <linux/pm_runtime.h>
 #include <linux/console.h>
-#ifdef CONFIG_SERIAL_OMAP
 #include <plat/omap-serial.h>
-#endif
+#include "common.h"
-#include <plat/common.h>
 #include <plat/board.h>
-#include <plat/clock.h>
 #include <plat/dma.h>
 #include <plat/omap_hwmod.h>
 #include <plat/omap_device.h>
+#include <plat/omap-pm.h>
 #include "prm2xxx_3xxx.h"
 #include "pm.h"
@@ -47,603 +42,226 @@
 #include "control.h"
 #include "mux.h"
-#define UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV     0x52
-#define UART_OMAP_WER           0x17    /* Wake-up enable register */
-#define UART_ERRATA_FIFO_FULL_ABORT     (0x1 << 0)
-#define UART_ERRATA_i202_MDR1_ACCESS    (0x1 << 1)
 /*
- * NOTE: By default the serial timeout is disabled as it causes lost characters
+ * NOTE: By default the serial auto_suspend timeout is disabled as it causes
- * over the serial ports. This means that the UART clocks will stay on until
+ * lost characters over the serial ports. This means that the UART clocks will
- * disabled via sysfs. This also causes that any deeper omap sleep states are
+ * stay on until power/autosuspend_delay is set for the uart from sysfs.
- * blocked. 
+ * This also causes that any deeper omap sleep states are blocked.
 */
-#define DEFAULT_TIMEOUT 0
+#define DEFAULT_AUTOSUSPEND_DELAY       -1
 #define MAX_UART_HWMOD_NAME_LEN         16
 struct omap_uart_state {
        int num;
        int can_sleep;
-        struct timer_list timer;
-        u32 timeout;
-        void __iomem *wk_st;
-        void __iomem *wk_en;
-        u32 wk_mask;
-        u32 padconf;
-        u32 dma_enabled;
-        struct clk *ick;
-        struct clk *fck;
-        int clocked;
-        int irq;
-        int regshift;
-        int irqflags;
-        void __iomem *membase;
-        resource_size_t mapbase;
        struct list_head node;
        struct omap_hwmod *oh;
        struct platform_device *pdev;
-        u32 errata;
-#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
-        int context_valid;
-        /* Registers to be saved/restored for OFF-mode */
-        u16 dll;
-        u16 dlh;
-        u16 ier;
-        u16 sysc;
-        u16 scr;
-        u16 wer;
-        u16 mcr;
-#endif
 };
 static LIST_HEAD(uart_list);
 static u8 num_uarts;
+static u8 console_uart_id = -1;
+static u8 no_console_suspend;
+static u8 uart_debug;
+#define DEFAULT_RXDMA_POLLRATE          1       /* RX DMA polling rate (us) */
+#define DEFAULT_RXDMA_BUFSIZE           4096    /* RX DMA buffer size */
+#define DEFAULT_RXDMA_TIMEOUT           (3 * HZ)/* RX DMA timeout (jiffies) */
+static struct omap_uart_port_info omap_serial_default_info[] __initdata = {
+        {
+                .dma_enabled    = false,
+                .dma_rx_buf_size = DEFAULT_RXDMA_BUFSIZE,
+                .dma_rx_poll_rate = DEFAULT_RXDMA_POLLRATE,
+                .dma_rx_timeout = DEFAULT_RXDMA_TIMEOUT,
+                .autosuspend_timeout = DEFAULT_AUTOSUSPEND_DELAY,
+        },
+};
-static inline unsigned int __serial_read_reg(struct uart_port *up,
+#ifdef CONFIG_PM
-                                             int offset)
+static void omap_uart_enable_wakeup(struct platform_device *pdev, bool enable)
-{
-        offset <<= up->regshift;
-        return (unsigned int)__raw_readb(up->membase + offset);
-}
-static inline unsigned int serial_read_reg(struct omap_uart_state *uart,
-                                           int offset)
 {
-        offset <<= uart->regshift;
+        struct omap_device *od = to_omap_device(pdev);
-        return (unsigned int)__raw_readb(uart->membase + offset);
-}
-static inline void __serial_write_reg(struct uart_port *up, int offset,
+        if (!od)
-                int value)
+                return;
-{
-        offset <<= up->regshift;
-        __raw_writeb(value, up->membase + offset);
-}
-static inline void serial_write_reg(struct omap_uart_state *uart, int offset,
+        if (enable)
-                                    int value)
+                omap_hwmod_enable_wakeup(od->hwmods[0]);
-{
+        else
-        offset <<= uart->regshift;
+                omap_hwmod_disable_wakeup(od->hwmods[0]);
-        __raw_writeb(value, uart->membase + offset);
 }
 /*
- * Internal UARTs need to be initialized for the 8250 autoconfig to work
+ * Errata i291: [UART]:Cannot Acknowledge Idle Requests
- * properly. Note that the TX watermark initialization may not be needed
+ * in Smartidle Mode When Configured for DMA Operations.
- * once the 8250.c watermark handling code is merged.
+ * WA: configure uart in force idle mode.
 */
+static void omap_uart_set_noidle(struct platform_device *pdev)
-static inline void __init omap_uart_reset(struct omap_uart_state *uart)
 {
-        serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
+        struct omap_device *od = to_omap_device(pdev);
-        serial_write_reg(uart, UART_OMAP_SCR, 0x08);
-        serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_16X_MODE);
-}
-#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
-/*
+        omap_hwmod_set_slave_idlemode(od->hwmods[0], HWMOD_IDLEMODE_NO);
- * Work Around for Errata i202 (3430 - 1.12, 3630 - 1.6)
- * The access to uart register after MDR1 Access
- * causes UART to corrupt data.
- *
- * Need a delay =
- * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
- * give 10 times as much
- */
-static void omap_uart_mdr1_errataset(struct omap_uart_state *uart, u8 mdr1_val,
-                u8 fcr_val)
-{
-        u8 timeout = 255;
-        serial_write_reg(uart, UART_OMAP_MDR1, mdr1_val);
-        udelay(2);
-        serial_write_reg(uart, UART_FCR, fcr_val | UART_FCR_CLEAR_XMIT |
-                        UART_FCR_CLEAR_RCVR);
-        /*
-         * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
-         * TX_FIFO_E bit is 1.
-         */
-        while (UART_LSR_THRE != (serial_read_reg(uart, UART_LSR) &
-                                (UART_LSR_THRE | UART_LSR_DR))) {
-                timeout--;
-                if (!timeout) {
-                        /* Should *never* happen. we warn and carry on */
-                        dev_crit(&uart->pdev->dev, "Errata i202: timedout %x\n",
-                        serial_read_reg(uart, UART_LSR));
-                        break;
-                }
-                udelay(1);
-        }
 }
-static void omap_uart_save_context(struct omap_uart_state *uart)
+static void omap_uart_set_forceidle(struct platform_device *pdev)
 {
-        u16 lcr = 0;
+        struct omap_device *od = to_omap_device(pdev);
-        if (!enable_off_mode)
+        omap_hwmod_set_slave_idlemode(od->hwmods[0], HWMOD_IDLEMODE_FORCE);
-                return;
-        lcr = serial_read_reg(uart, UART_LCR);
-        serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
-        uart->dll = serial_read_reg(uart, UART_DLL);
-        uart->dlh = serial_read_reg(uart, UART_DLM);
-        serial_write_reg(uart, UART_LCR, lcr);
-        uart->ier = serial_read_reg(uart, UART_IER);
-        uart->sysc = serial_read_reg(uart, UART_OMAP_SYSC);
-        uart->scr = serial_read_reg(uart, UART_OMAP_SCR);
-        uart->wer = serial_read_reg(uart, UART_OMAP_WER);
-        serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_A);
-        uart->mcr = serial_read_reg(uart, UART_MCR);
-        serial_write_reg(uart, UART_LCR, lcr);
-        uart->context_valid = 1;
 }
-static void omap_uart_restore_context(struct omap_uart_state *uart)
-{
-        u16 efr = 0;
-        if (!enable_off_mode)
-                return;
-        if (!uart->context_valid)
-                return;
-        uart->context_valid = 0;
-        if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS)
-                omap_uart_mdr1_errataset(uart, UART_OMAP_MDR1_DISABLE, 0xA0);
-        else
-                serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
-        serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
-        efr = serial_read_reg(uart, UART_EFR);
-        serial_write_reg(uart, UART_EFR, UART_EFR_ECB);
-        serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */
-        serial_write_reg(uart, UART_IER, 0x0);
-        serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
-        serial_write_reg(uart, UART_DLL, uart->dll);
-        serial_write_reg(uart, UART_DLM, uart->dlh);
-        serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */
-        serial_write_reg(uart, UART_IER, uart->ier);
-        serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_A);
-        serial_write_reg(uart, UART_MCR, uart->mcr);
-        serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
-        serial_write_reg(uart, UART_EFR, efr);
-        serial_write_reg(uart, UART_LCR, UART_LCR_WLEN8);
-        serial_write_reg(uart, UART_OMAP_SCR, uart->scr);
-        serial_write_reg(uart, UART_OMAP_WER, uart->wer);
-        serial_write_reg(uart, UART_OMAP_SYSC, uart->sysc);
-        if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS)
-                omap_uart_mdr1_errataset(uart, UART_OMAP_MDR1_16X_MODE, 0xA1);
-        else
-                /* UART 16x mode */
-                serial_write_reg(uart, UART_OMAP_MDR1,
-                                UART_OMAP_MDR1_16X_MODE);
-}
 #else
-static inline void omap_uart_save_context(struct omap_uart_state *uart) {}
+static void omap_uart_enable_wakeup(struct platform_device *pdev, bool enable)
-static inline void omap_uart_restore_context(struct omap_uart_state *uart) {}
+{}
-#endif /* CONFIG_PM && CONFIG_ARCH_OMAP3 */
+static void omap_uart_set_noidle(struct platform_device *pdev) {}
+static void omap_uart_set_forceidle(struct platform_device *pdev) {}
-static inline void omap_uart_enable_clocks(struct omap_uart_state *uart)
+#endif /* CONFIG_PM */
-{
-        if (uart->clocked)
-                return;
-        omap_device_enable(uart->pdev);
-        uart->clocked = 1;
-        omap_uart_restore_context(uart);
-}
-#ifdef CONFIG_PM
-static inline void omap_uart_disable_clocks(struct omap_uart_state *uart)
-{
-        if (!uart->clocked)
-                return;
-        omap_uart_save_context(uart);
-        uart->clocked = 0;
-        omap_device_idle(uart->pdev);
-}
-static void omap_uart_enable_wakeup(struct omap_uart_state *uart)
-{
-        /* Set wake-enable bit */
-        if (uart->wk_en && uart->wk_mask) {
-                u32 v = __raw_readl(uart->wk_en);
-                v |= uart->wk_mask;
-                __raw_writel(v, uart->wk_en);
-        }
-        /* Ensure IOPAD wake-enables are set */
-        if (cpu_is_omap34xx() && uart->padconf) {
-                u16 v = omap_ctrl_readw(uart->padconf);
-                v |= OMAP3_PADCONF_WAKEUPENABLE0;
-                omap_ctrl_writew(v, uart->padconf);
-        }
-}
-static void omap_uart_disable_wakeup(struct omap_uart_state *uart)
-{
-        /* Clear wake-enable bit */
-        if (uart->wk_en && uart->wk_mask) {
-                u32 v = __raw_readl(uart->wk_en);
-                v &= ~uart->wk_mask;
-                __raw_writel(v, uart->wk_en);
-        }
-        /* Ensure IOPAD wake-enables are cleared */
-        if (cpu_is_omap34xx() && uart->padconf) {
-                u16 v = omap_ctrl_readw(uart->padconf);
-                v &= ~OMAP3_PADCONF_WAKEUPENABLE0;
-                omap_ctrl_writew(v, uart->padconf);
-        }
-}
-static void omap_uart_smart_idle_enable(struct omap_uart_state *uart,
-                                               int enable)
-{
-        u8 idlemode;
-        if (enable) {
-                /**
-                 * Errata 2.15: [UART]:Cannot Acknowledge Idle Requests
-                 * in Smartidle Mode When Configured for DMA Operations.
-                 */
-                if (uart->dma_enabled)
-                        idlemode = HWMOD_IDLEMODE_FORCE;
-                else
-                        idlemode = HWMOD_IDLEMODE_SMART;
-        } else {
-                idlemode = HWMOD_IDLEMODE_NO;
-        }
-        omap_hwmod_set_slave_idlemode(uart->oh, idlemode);
-}
-static void omap_uart_block_sleep(struct omap_uart_state *uart)
-{
-        omap_uart_enable_clocks(uart);
-        omap_uart_smart_idle_enable(uart, 0);
-        uart->can_sleep = 0;
-        if (uart->timeout)
-                mod_timer(&uart->timer, jiffies + uart->timeout);
-        else
-                del_timer(&uart->timer);
-}
-static void omap_uart_allow_sleep(struct omap_uart_state *uart)
-{
-        if (device_may_wakeup(&uart->pdev->dev))
-                omap_uart_enable_wakeup(uart);
-        else
-                omap_uart_disable_wakeup(uart);
-        if (!uart->clocked)
-                return;
-        omap_uart_smart_idle_enable(uart, 1);
-        uart->can_sleep = 1;
-        del_timer(&uart->timer);
-}
-static void omap_uart_idle_timer(unsigned long data)
-{
-        struct omap_uart_state *uart = (struct omap_uart_state *)data;
-        omap_uart_allow_sleep(uart);
-}
-void omap_uart_prepare_idle(int num)
-{
-        struct omap_uart_state *uart;
-        list_for_each_entry(uart, &uart_list, node) {
-                if (num == uart->num && uart->can_sleep) {
-                        omap_uart_disable_clocks(uart);
-                        return;
-                }
-        }
-}
-void omap_uart_resume_idle(int num)
-{
-        struct omap_uart_state *uart;
-        list_for_each_entry(uart, &uart_list, node) {
-                if (num == uart->num && uart->can_sleep) {
-                        omap_uart_enable_clocks(uart);
-                        /* Check for IO pad wakeup */
-                        if (cpu_is_omap34xx() && uart->padconf) {
-                                u16 p = omap_ctrl_readw(uart->padconf);
-                                if (p & OMAP3_PADCONF_WAKEUPEVENT0)
-                                        omap_uart_block_sleep(uart);
-                        }
-                        /* Check for normal UART wakeup */
-                        if (__raw_readl(uart->wk_st) & uart->wk_mask)
-                                omap_uart_block_sleep(uart);
-                        return;
-                }
-        }
-}
-void omap_uart_prepare_suspend(void)
-{
-        struct omap_uart_state *uart;
-        list_for_each_entry(uart, &uart_list, node) {
-                omap_uart_allow_sleep(uart);
-        }
-}
-int omap_uart_can_sleep(void)
-{
-        struct omap_uart_state *uart;
-        int can_sleep = 1;
-        list_for_each_entry(uart, &uart_list, node) {
-                if (!uart->clocked)
-                        continue;
-                if (!uart->can_sleep) {
-                        can_sleep = 0;
-                        continue;
-                }
-                /* This UART can now safely sleep. */
-                omap_uart_allow_sleep(uart);
-        }
-        return can_sleep;
-}
-/**
+#ifdef CONFIG_OMAP_MUX
- * omap_uart_interrupt()
+static struct omap_device_pad default_uart1_pads[] __initdata = {
- *
+        {
- * This handler is used only to detect that *any* UART interrupt has
+                .name   = "uart1_cts.uart1_cts",
- * occurred.  It does _nothing_ to handle the interrupt.  Rather,
+                .enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
- * any UART interrupt will trigger the inactivity timer so the
+        },
- * UART will not idle or sleep for its timeout period.
+        {
- *
+                .name   = "uart1_rts.uart1_rts",
- **/
+                .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
-/* static int first_interrupt; */
+        },
-static irqreturn_t omap_uart_interrupt(int irq, void *dev_id)
+        {
-{
+                .name   = "uart1_tx.uart1_tx",
-        struct omap_uart_state *uart = dev_id;
+                .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
+        },
+        {
+                .name   = "uart1_rx.uart1_rx",
+                .flags  = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
+                .enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
+                .idle   = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
+        },
+};
-        omap_uart_block_sleep(uart);
+static struct omap_device_pad default_uart2_pads[] __initdata = {
+        {
+                .name   = "uart2_cts.uart2_cts",
+                .enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
+        },
+        {
+                .name   = "uart2_rts.uart2_rts",
+                .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
+        },
+        {
+                .name   = "uart2_tx.uart2_tx",
+                .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
+        },
+        {
+                .name   = "uart2_rx.uart2_rx",
+                .flags  = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
+                .enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
+                .idle   = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
+        },
+};
-        return IRQ_NONE;
+static struct omap_device_pad default_uart3_pads[] __initdata = {
-}
+        {
+                .name   = "uart3_cts_rctx.uart3_cts_rctx",
+                .enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
+        },
+        {
+                .name   = "uart3_rts_sd.uart3_rts_sd",
+                .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
+        },
+        {
+                .name   = "uart3_tx_irtx.uart3_tx_irtx",
+                .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
+        },
+        {
+                .name   = "uart3_rx_irrx.uart3_rx_irrx",
+                .flags  = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
+                .enable = OMAP_PIN_INPUT | OMAP_MUX_MODE0,
+                .idle   = OMAP_PIN_INPUT | OMAP_MUX_MODE0,
+        },
+};
-static void omap_uart_idle_init(struct omap_uart_state *uart)
+static struct omap_device_pad default_omap36xx_uart4_pads[] __initdata = {
-{
+        {
-        int ret;
+                .name   = "gpmc_wait2.uart4_tx",
+                .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
-        uart->can_sleep = 0;
+        },
-        uart->timeout = DEFAULT_TIMEOUT;
+        {
-        setup_timer(&uart->timer, omap_uart_idle_timer,
+                .name   = "gpmc_wait3.uart4_rx",
-                    (unsigned long) uart);
+                .flags  = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
-        if (uart->timeout)
+                .enable = OMAP_PIN_INPUT | OMAP_MUX_MODE2,
-                mod_timer(&uart->timer, jiffies + uart->timeout);
+                .idle   = OMAP_PIN_INPUT | OMAP_MUX_MODE2,
-        omap_uart_smart_idle_enable(uart, 0);
+        },
+};
-        if (cpu_is_omap34xx() && !cpu_is_ti816x()) {
-                u32 mod = (uart->num > 1) ? OMAP3430_PER_MOD : CORE_MOD;
-                u32 wk_mask = 0;
-                u32 padconf = 0;
-                /* XXX These PRM accesses do not belong here */
-                uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1);
-                uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1);
-                switch (uart->num) {
-                case 0:
-                        wk_mask = OMAP3430_ST_UART1_MASK;
-                        padconf = 0x182;
-                        break;
-                case 1:
-                        wk_mask = OMAP3430_ST_UART2_MASK;
-                        padconf = 0x17a;
-                        break;
-                case 2:
-                        wk_mask = OMAP3430_ST_UART3_MASK;
-                        padconf = 0x19e;
-                        break;
-                case 3:
-                        wk_mask = OMAP3630_ST_UART4_MASK;
-                        padconf = 0x0d2;
-                        break;
-                }
-                uart->wk_mask = wk_mask;
-                uart->padconf = padconf;
-        } else if (cpu_is_omap24xx()) {
-                u32 wk_mask = 0;
-                u32 wk_en = PM_WKEN1, wk_st = PM_WKST1;
-                switch (uart->num) {
-                case 0:
-                        wk_mask = OMAP24XX_ST_UART1_MASK;
-                        break;
-                case 1:
-                        wk_mask = OMAP24XX_ST_UART2_MASK;
-                        break;
-                case 2:
-                        wk_en = OMAP24XX_PM_WKEN2;
-                        wk_st = OMAP24XX_PM_WKST2;
-                        wk_mask = OMAP24XX_ST_UART3_MASK;
-                        break;
-                }
-                uart->wk_mask = wk_mask;
-                if (cpu_is_omap2430()) {
-                        uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, wk_en);
-                        uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, wk_st);
-                } else if (cpu_is_omap2420()) {
-                        uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, wk_en);
-                        uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, wk_st);
-                }
-        } else {
-                uart->wk_en = NULL;
-                uart->wk_st = NULL;
-                uart->wk_mask = 0;
-                uart->padconf = 0;
-        }
-        uart->irqflags |= IRQF_SHARED;
+static struct omap_device_pad default_omap4_uart4_pads[] __initdata = {
-        ret = request_threaded_irq(uart->irq, NULL, omap_uart_interrupt,
+        {
-                                   IRQF_SHARED, "serial idle", (void *)uart);
+                .name   = "uart4_tx.uart4_tx",
-        WARN_ON(ret);
+                .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
-}
+        },
+        {
+                .name   = "uart4_rx.uart4_rx",
+                .flags  = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
+                .enable = OMAP_PIN_INPUT | OMAP_MUX_MODE0,
+                .idle   = OMAP_PIN_INPUT | OMAP_MUX_MODE0,
+        },
+};
-void omap_uart_enable_irqs(int enable)
+static void omap_serial_fill_default_pads(struct omap_board_data *bdata)
 {
-        int ret;
+        switch (bdata->id) {
-        struct omap_uart_state *uart;
+        case 0:
+                bdata->pads = default_uart1_pads;
-        list_for_each_entry(uart, &uart_list, node) {
+                bdata->pads_cnt = ARRAY_SIZE(default_uart1_pads);
-                if (enable) {
+                break;
-                        pm_runtime_put_sync(&uart->pdev->dev);
+        case 1:
-                        ret = request_threaded_irq(uart->irq, NULL,
+                bdata->pads = default_uart2_pads;
-                                                   omap_uart_interrupt,
+                bdata->pads_cnt = ARRAY_SIZE(default_uart2_pads);
-                                                   IRQF_SHARED,
+                break;
-                                                   "serial idle",
+        case 2:
-                                                   (void *)uart);
+                bdata->pads = default_uart3_pads;
-                } else {
+                bdata->pads_cnt = ARRAY_SIZE(default_uart3_pads);
-                        pm_runtime_get_noresume(&uart->pdev->dev);
+                break;
-                        free_irq(uart->irq, (void *)uart);
+        case 3:
+                if (cpu_is_omap44xx()) {
+                        bdata->pads = default_omap4_uart4_pads;
+                        bdata->pads_cnt =
+                                ARRAY_SIZE(default_omap4_uart4_pads);
+                } else if (cpu_is_omap3630()) {
+                        bdata->pads = default_omap36xx_uart4_pads;
+                        bdata->pads_cnt =
+                                ARRAY_SIZE(default_omap36xx_uart4_pads);
                }
+                break;
+        default:
+                break;
        }
 }
-static ssize_t sleep_timeout_show(struct device *dev,
-                                  struct device_attribute *attr,
-                                  char *buf)
-{
-        struct platform_device *pdev = to_platform_device(dev);
-        struct omap_device *odev = to_omap_device(pdev);
-        struct omap_uart_state *uart = odev->hwmods[0]->dev_attr;
-        return sprintf(buf, "%u\n", uart->timeout / HZ);
-}
-static ssize_t sleep_timeout_store(struct device *dev,
-                                   struct device_attribute *attr,
-                                   const char *buf, size_t n)
-{
-        struct platform_device *pdev = to_platform_device(dev);
-        struct omap_device *odev = to_omap_device(pdev);
-        struct omap_uart_state *uart = odev->hwmods[0]->dev_attr;
-        unsigned int value;
-        if (sscanf(buf, "%u", &value) != 1) {
-                dev_err(dev, "sleep_timeout_store: Invalid value\n");
-                return -EINVAL;
-        }
-        uart->timeout = value * HZ;
-        if (uart->timeout)
-                mod_timer(&uart->timer, jiffies + uart->timeout);
-        else
-                /* A zero value means disable timeout feature */
-                omap_uart_block_sleep(uart);
-        return n;
-}
-static DEVICE_ATTR(sleep_timeout, 0644, sleep_timeout_show,
-                sleep_timeout_store);
-#define DEV_CREATE_FILE(dev, attr) WARN_ON(device_create_file(dev, attr))
 #else
-static inline void omap_uart_idle_init(struct omap_uart_state *uart) {}
+static void omap_serial_fill_default_pads(struct omap_board_data *bdata) {}
-static void omap_uart_block_sleep(struct omap_uart_state *uart)
+#endif
-{
-        /* Needed to enable UART clocks when built without CONFIG_PM */
-        omap_uart_enable_clocks(uart);
-}
-#define DEV_CREATE_FILE(dev, attr)
-#endif /* CONFIG_PM */
-#ifndef CONFIG_SERIAL_OMAP
-/*
- * Override the default 8250 read handler: mem_serial_in()
- * Empty RX fifo read causes an abort on omap3630 and omap4
- * This function makes sure that an empty rx fifo is not read on these silicons
- * (OMAP1/2/3430 are not affected)
- */
-static unsigned int serial_in_override(struct uart_port *up, int offset)
-{
-        if (UART_RX == offset) {
-                unsigned int lsr;
-                lsr = __serial_read_reg(up, UART_LSR);
-                if (!(lsr & UART_LSR_DR))
-                        return -EPERM;
-        }
-        return __serial_read_reg(up, offset);
-}
-static void serial_out_override(struct uart_port *up, int offset, int value)
+char *cmdline_find_option(char *str)
 {
-        unsigned int status, tmout = 10000;
+        extern char *saved_command_line;
-        status = __serial_read_reg(up, UART_LSR);
+        return strstr(saved_command_line, str);
-        while (!(status & UART_LSR_THRE)) {
-                /* Wait up to 10ms for the character(s) to be sent. */
-                if (--tmout == 0)
-                        break;
-                udelay(1);
-                status = __serial_read_reg(up, UART_LSR);
-        }
-        __serial_write_reg(up, offset, value);
 }
-#endif
 static int __init omap_serial_early_init(void)
 {
-        int i = 0;
        do {
                char oh_name[MAX_UART_HWMOD_NAME_LEN];
                struct omap_hwmod *oh;
                struct omap_uart_state *uart;
+                char uart_name[MAX_UART_HWMOD_NAME_LEN];
                snprintf(oh_name, MAX_UART_HWMOD_NAME_LEN,
-                         "uart%d", i + 1);
+                         "uart%d", num_uarts + 1);
                oh = omap_hwmod_lookup(oh_name);
                if (!oh)
                        break;
@@ -653,21 +271,35 @@ static int __init omap_serial_early_init(void)
                        return -ENODEV;
                uart->oh = oh;
-                uart->num = i++;
+                uart->num = num_uarts++;
                list_add_tail(&uart->node, &uart_list);
-                num_uarts++;
+                snprintf(uart_name, MAX_UART_HWMOD_NAME_LEN,
+                                "%s%d", OMAP_SERIAL_NAME, uart->num);
-                /*
-                 * NOTE: omap_hwmod_setup*() has not yet been called,
+                if (cmdline_find_option(uart_name)) {
-                 *       so no hwmod functions will work yet.
+                        console_uart_id = uart->num;
-                 */
+                        if (console_loglevel >= 10) {
-                /*
+                                uart_debug = true;
-                 * During UART early init, device need to be probed
+                                pr_info("%s used as console in debug mode"
-                 * to determine SoC specific init before omap_device
+                                                " uart%d clocks will not be"
-                 * is ready.  Therefore, don't allow idle here
+                                                " gated", uart_name, uart->num);
-                 */
+                        }
-                uart->oh->flags |= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET;
+                        if (cmdline_find_option("no_console_suspend"))
+                                no_console_suspend = true;
+                        /*
+                         * omap-uart can be used for earlyprintk logs
+                         * So if omap-uart is used as console then prevent
+                         * uart reset and idle to get logs from omap-uart
+                         * until uart console driver is available to take
+                         * care for console messages.
+                         * Idling or resetting omap-uart while printing logs
+                         * early boot logs can stall the boot-up.
+                         */
+                        oh->flags |= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET;
+                }
        } while (1);
        return 0;
@@ -677,6 +309,7 @@ core_initcall(omap_serial_early_init);
 /**
 * omap_serial_init_port() - initialize single serial port
 * @bdata: port specific board data pointer
+ * @info: platform specific data pointer
 *
 * This function initialies serial driver for given port only.
 * Platforms can call this function instead of omap_serial_init()
@@ -685,7 +318,8 @@ core_initcall(omap_serial_early_init);
 * Don't mix calls to omap_serial_init_port() and omap_serial_init(),
 * use only one of the two.
 */
-void __init omap_serial_init_port(struct omap_board_data *bdata)
+void __init omap_serial_init_port(struct omap_board_data *bdata,
+                        struct omap_uart_port_info *info)
 {
        struct omap_uart_state *uart;
        struct omap_hwmod *oh;
@@ -693,15 +327,7 @@ void __init omap_serial_init_port(struct omap_board_data *bdata)
        void *pdata = NULL;
        u32 pdata_size = 0;
        char *name;
-#ifndef CONFIG_SERIAL_OMAP
-        struct plat_serial8250_port ports[2] = {
-                {},
-                {.flags = 0},
-        };
-        struct plat_serial8250_port *p = &ports[0];
-#else
        struct omap_uart_port_info omap_up;
-#endif
        if (WARN_ON(!bdata))
                return;
@@ -713,66 +339,34 @@ void __init omap_serial_init_port(struct omap_board_data *bdata)
        list_for_each_entry(uart, &uart_list, node)
                if (bdata->id == uart->num)
                        break;
+        if (!info)
+                info = omap_serial_default_info;
        oh = uart->oh;
-        uart->dma_enabled = 0;
-#ifndef CONFIG_SERIAL_OMAP
-        name = "serial8250";
-        /*
-         * !! 8250 driver does not use standard IORESOURCE* It
-         * has it's own custom pdata that can be taken from
-         * the hwmod resource data.  But, this needs to be
-         * done after the build.
-         *
-         * ?? does it have to be done before the register ??
-         * YES, because platform_device_data_add() copies
-         * pdata, it does not use a pointer.
-         */
-        p->flags = UPF_BOOT_AUTOCONF;
-        p->iotype = UPIO_MEM;
-        p->regshift = 2;
-        p->uartclk = OMAP24XX_BASE_BAUD * 16;
-        p->irq = oh->mpu_irqs[0].irq;
-        p->mapbase = oh->slaves[0]->addr->pa_start;
-        p->membase = omap_hwmod_get_mpu_rt_va(oh);
-        p->irqflags = IRQF_SHARED;
-        p->private_data = uart;
-        /*
-         * omap44xx, ti816x: Never read empty UART fifo
-         * omap3xxx: Never read empty UART fifo on UARTs
-         * with IP rev >=0x52
-         */
-        uart->regshift = p->regshift;
-        uart->membase = p->membase;
-        if (cpu_is_omap44xx() || cpu_is_ti816x())
-                uart->errata |= UART_ERRATA_FIFO_FULL_ABORT;
-        else if ((serial_read_reg(uart, UART_OMAP_MVER) & 0xFF)
-                        >= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV)
-                uart->errata |= UART_ERRATA_FIFO_FULL_ABORT;
-        if (uart->errata & UART_ERRATA_FIFO_FULL_ABORT) {
-                p->serial_in = serial_in_override;
-                p->serial_out = serial_out_override;
-        }
-        pdata = &ports[0];
-        pdata_size = 2 * sizeof(struct plat_serial8250_port);
-#else
        name = DRIVER_NAME;
-        omap_up.dma_enabled = uart->dma_enabled;
+        omap_up.dma_enabled = info->dma_enabled;
        omap_up.uartclk = OMAP24XX_BASE_BAUD * 16;
-        omap_up.mapbase = oh->slaves[0]->addr->pa_start;
+        omap_up.flags = UPF_BOOT_AUTOCONF;
-        omap_up.membase = omap_hwmod_get_mpu_rt_va(oh);
+        omap_up.get_context_loss_count = omap_pm_get_dev_context_loss_count;
-        omap_up.irqflags = IRQF_SHARED;
+        omap_up.set_forceidle = omap_uart_set_forceidle;
-        omap_up.flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
+        omap_up.set_noidle = omap_uart_set_noidle;
+        omap_up.enable_wakeup = omap_uart_enable_wakeup;
+        omap_up.dma_rx_buf_size = info->dma_rx_buf_size;
+        omap_up.dma_rx_timeout = info->dma_rx_timeout;
+        omap_up.dma_rx_poll_rate = info->dma_rx_poll_rate;
+        omap_up.autosuspend_timeout = info->autosuspend_timeout;
+        /* Enable the MDR1 Errata i202 for OMAP2430/3xxx/44xx */
+        if (!cpu_is_omap2420() && !cpu_is_ti816x())
+                omap_up.errata |= UART_ERRATA_i202_MDR1_ACCESS;
+        /* Enable DMA Mode Force Idle Errata i291 for omap34xx/3630 */
+        if (cpu_is_omap34xx() || cpu_is_omap3630())
+                omap_up.errata |= UART_ERRATA_i291_DMA_FORCEIDLE;
        pdata = &omap_up;
        pdata_size = sizeof(struct omap_uart_port_info);
-#endif
        if (WARN_ON(!oh))
                return;
@@ -782,64 +376,29 @@ void __init omap_serial_init_port(struct omap_board_data *bdata)
        WARN(IS_ERR(pdev), "Could not build omap_device for %s: %s.\n",
             name, oh->name);
-        omap_device_disable_idle_on_suspend(pdev);
+        if ((console_uart_id == bdata->id) && no_console_suspend)
+                omap_device_disable_idle_on_suspend(pdev);
        oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt);
-        uart->irq = oh->mpu_irqs[0].irq;
-        uart->regshift = 2;
-        uart->mapbase = oh->slaves[0]->addr->pa_start;
-        uart->membase = omap_hwmod_get_mpu_rt_va(oh);
        uart->pdev = pdev;
        oh->dev_attr = uart;
-        console_lock(); /* in case the earlycon is on the UART */
+        if (((cpu_is_omap34xx() || cpu_is_omap44xx()) && bdata->pads)
+                        && !uart_debug)
-        /*
-         * Because of early UART probing, UART did not get idled
-         * on init.  Now that omap_device is ready, ensure full idle
-         * before doing omap_device_enable().
-         */
-        omap_hwmod_idle(uart->oh);
-        omap_device_enable(uart->pdev);
-        omap_uart_idle_init(uart);
-        omap_uart_reset(uart);
-        omap_hwmod_enable_wakeup(uart->oh);
-        omap_device_idle(uart->pdev);
-        /*
-         * Need to block sleep long enough for interrupt driven
-         * driver to start.  Console driver is in polling mode
-         * so device needs to be kept enabled while polling driver
-         * is in use.
-         */
-        if (uart->timeout)
-                uart->timeout = (30 * HZ);
-        omap_uart_block_sleep(uart);
-        uart->timeout = DEFAULT_TIMEOUT;
-        console_unlock();
-        if ((cpu_is_omap34xx() && uart->padconf) ||
-            (uart->wk_en && uart->wk_mask)) {
                device_init_wakeup(&pdev->dev, true);
-                DEV_CREATE_FILE(&pdev->dev, &dev_attr_sleep_timeout);
-        }
-        /* Enable the MDR1 errata for OMAP3 */
-        if (cpu_is_omap34xx() && !cpu_is_ti816x())
-                uart->errata |= UART_ERRATA_i202_MDR1_ACCESS;
 }
 /**
- * omap_serial_init() - initialize all supported serial ports
+ * omap_serial_board_init() - initialize all supported serial ports
+ * @info: platform specific data pointer
 *
 * Initializes all available UARTs as serial ports. Platforms
 * can call this function when they want to have default behaviour
 * for serial ports (e.g initialize them all as serial ports).
 */
-void __init omap_serial_init(void)
+void __init omap_serial_board_init(struct omap_uart_port_info *info)
 {
        struct omap_uart_state *uart;
        struct omap_board_data bdata;
@@ -849,7 +408,25 @@ void __init omap_serial_init(void)
                bdata.flags = 0;
                bdata.pads = NULL;
                bdata.pads_cnt = 0;
-                omap_serial_init_port(&bdata);
+                if (cpu_is_omap44xx() || cpu_is_omap34xx())
+                        omap_serial_fill_default_pads(&bdata);
+                if (!info)
+                        omap_serial_init_port(&bdata, NULL);
+                else
+                        omap_serial_init_port(&bdata, &info[uart->num]);
        }
 }
+/**
+ * omap_serial_init() - initialize all supported serial ports
+ *
+ * Initializes all available UARTs.
+ * Platforms can call this function when they want to have default behaviour
+ * for serial ports (e.g initialize them all as serial ports).
+ */
+void __init omap_serial_init(void)
+{
+        omap_serial_board_init(NULL);
+}
diff --git a/arch/arm/mach-omap2/sleep44xx.S b/arch/arm/mach-omap2/sleep44xx.S
new file mode 100644
index 000000000000..abd283400490
--- /dev/null
+++ b/arch/arm/mach-omap2/sleep44xx.S
@@ -0,0 +1,379 @@
+/*
+ * OMAP44xx sleep code.
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc.
+ *      Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ * This program is free software,you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/linkage.h>
+#include <asm/system.h>
+#include <asm/smp_scu.h>
+#include <asm/memory.h>
+#include <asm/hardware/cache-l2x0.h>
+#include <plat/omap44xx.h>
+#include <mach/omap-secure.h>
+#include "common.h"
+#include "omap4-sar-layout.h"
+#if defined(CONFIG_SMP) && defined(CONFIG_PM)
+.macro  DO_SMC
+        dsb
+        smc     #0
+        dsb
+.endm
+ppa_zero_params:
+        .word           0x0
+ppa_por_params:
+        .word           1, 0
+/*
+ * =============================
+ * == CPU suspend finisher ==
+ * =============================
+ *
+ * void omap4_finish_suspend(unsigned long cpu_state)
+ *
+ * This function code saves the CPU context and performs the CPU
+ * power down sequence. Calling WFI effectively changes the CPU
+ * power domains states to the desired target power state.
+ *
+ * @cpu_state : contains context save state (r0)
+ *      0 - No context lost
+ *      1 - CPUx L1 and logic lost: MPUSS CSWR
+ *      2 - CPUx L1 and logic lost + GIC lost: MPUSS OSWR
+ *      3 - CPUx L1 and logic lost + GIC + L2 lost: MPUSS OFF
+ * @return: This function never returns for CPU OFF and DORMANT power states.
+ * Post WFI, CPU transitions to DORMANT or OFF power state and on wake-up
+ * from this follows a full CPU reset path via ROM code to CPU restore code.
+ * The restore function pointer is stored at CPUx_WAKEUP_NS_PA_ADDR_OFFSET.
+ * It returns to the caller for CPU INACTIVE and ON power states or in case
+ * CPU failed to transition to targeted OFF/DORMANT state.
+ */
+ENTRY(omap4_finish_suspend)
+        stmfd   sp!, {lr}
+        cmp     r0, #0x0
+        beq     do_WFI                          @ No lowpower state, jump to WFI
+        /*
+         * Flush all data from the L1 data cache before disabling
+         * SCTLR.C bit.
+         */
+        bl      omap4_get_sar_ram_base
+        ldr     r9, [r0, #OMAP_TYPE_OFFSET]
+        cmp     r9, #0x1                        @ Check for HS device
+        bne     skip_secure_l1_clean
+        mov     r0, #SCU_PM_NORMAL
+        mov     r1, #0xFF                       @ clean seucre L1
+        stmfd   r13!, {r4-r12, r14}
+        ldr     r12, =OMAP4_MON_SCU_PWR_INDEX
+        DO_SMC
+        ldmfd   r13!, {r4-r12, r14}
+skip_secure_l1_clean:
+        bl      v7_flush_dcache_all
+        /*
+         * Clear the SCTLR.C bit to prevent further data cache
+         * allocation. Clearing SCTLR.C would make all the data accesses
+         * strongly ordered and would not hit the cache.
+         */
+        mrc     p15, 0, r0, c1, c0, 0
+        bic     r0, r0, #(1 << 2)               @ Disable the C bit
+        mcr     p15, 0, r0, c1, c0, 0
+        isb
+        /*
+         * Invalidate L1 data cache. Even though only invalidate is
+         * necessary exported flush API is used here. Doing clean
+         * on already clean cache would be almost NOP.
+         */
+        bl      v7_flush_dcache_all
+        /*
+         * Switch the CPU from Symmetric Multiprocessing (SMP) mode
+         * to AsymmetricMultiprocessing (AMP) mode by programming
+         * the SCU power status to DORMANT or OFF mode.
+         * This enables the CPU to be taken out of coherency by
+         * preventing the CPU from receiving cache, TLB, or BTB
+         * maintenance operations broadcast by other CPUs in the cluster.
+         */
+        bl      omap4_get_sar_ram_base
+        mov     r8, r0
+        ldr     r9, [r8, #OMAP_TYPE_OFFSET]
+        cmp     r9, #0x1                        @ Check for HS device
+        bne     scu_gp_set
+        mrc     p15, 0, r0, c0, c0, 5           @ Read MPIDR
+        ands    r0, r0, #0x0f
+        ldreq   r0, [r8, #SCU_OFFSET0]
+        ldrne   r0, [r8, #SCU_OFFSET1]
+        mov     r1, #0x00
+        stmfd   r13!, {r4-r12, r14}
+        ldr     r12, =OMAP4_MON_SCU_PWR_INDEX
+        DO_SMC
+        ldmfd   r13!, {r4-r12, r14}
+        b       skip_scu_gp_set
+scu_gp_set:
+        mrc     p15, 0, r0, c0, c0, 5           @ Read MPIDR
+        ands    r0, r0, #0x0f
+        ldreq   r1, [r8, #SCU_OFFSET0]
+        ldrne   r1, [r8, #SCU_OFFSET1]
+        bl      omap4_get_scu_base
+        bl      scu_power_mode
+skip_scu_gp_set:
+        mrc     p15, 0, r0, c1, c1, 2           @ Read NSACR data
+        tst     r0, #(1 << 18)
+        mrcne   p15, 0, r0, c1, c0, 1
+        bicne   r0, r0, #(1 << 6)               @ Disable SMP bit
+        mcrne   p15, 0, r0, c1, c0, 1
+        isb
+        dsb
+#ifdef CONFIG_CACHE_L2X0
+        /*
+         * Clean and invalidate the L2 cache.
+         * Common cache-l2x0.c functions can't be used here since it
+         * uses spinlocks. We are out of coherency here with data cache
+         * disabled. The spinlock implementation uses exclusive load/store
+         * instruction which can fail without data cache being enabled.
+         * OMAP4 hardware doesn't support exclusive monitor which can
+         * overcome exclusive access issue. Because of this, CPU can
+         * lead to deadlock.
+         */
+        bl      omap4_get_sar_ram_base
+        mov     r8, r0
+        mrc     p15, 0, r5, c0, c0, 5           @ Read MPIDR
+        ands    r5, r5, #0x0f
+        ldreq   r0, [r8, #L2X0_SAVE_OFFSET0]    @ Retrieve L2 state from SAR
+        ldrne   r0, [r8, #L2X0_SAVE_OFFSET1]    @ memory.
+        cmp     r0, #3
+        bne     do_WFI
+#ifdef CONFIG_PL310_ERRATA_727915
+        mov     r0, #0x03
+        mov     r12, #OMAP4_MON_L2X0_DBG_CTRL_INDEX
+        DO_SMC
+#endif
+        bl      omap4_get_l2cache_base
+        mov     r2, r0
+        ldr     r0, =0xffff
+        str     r0, [r2, #L2X0_CLEAN_INV_WAY]
+wait:
+        ldr     r0, [r2, #L2X0_CLEAN_INV_WAY]
+        ldr     r1, =0xffff
+        ands    r0, r0, r1
+        bne     wait
+#ifdef CONFIG_PL310_ERRATA_727915
+        mov     r0, #0x00
+        mov     r12, #OMAP4_MON_L2X0_DBG_CTRL_INDEX
+        DO_SMC
+#endif
+l2x_sync:
+        bl      omap4_get_l2cache_base
+        mov     r2, r0
+        mov     r0, #0x0
+        str     r0, [r2, #L2X0_CACHE_SYNC]
+sync:
+        ldr     r0, [r2, #L2X0_CACHE_SYNC]
+        ands    r0, r0, #0x1
+        bne     sync
+#endif
+do_WFI:
+        bl      omap_do_wfi
+        /*
+         * CPU is here when it failed to enter OFF/DORMANT or
+         * no low power state was attempted.
+         */
+        mrc     p15, 0, r0, c1, c0, 0
+        tst     r0, #(1 << 2)                   @ Check C bit enabled?
+        orreq   r0, r0, #(1 << 2)               @ Enable the C bit
+        mcreq   p15, 0, r0, c1, c0, 0
+        isb
+        /*
+         * Ensure the CPU power state is set to NORMAL in
+         * SCU power state so that CPU is back in coherency.
+         * In non-coherent mode CPU can lock-up and lead to
+         * system deadlock.
+         */
+        mrc     p15, 0, r0, c1, c0, 1
+        tst     r0, #(1 << 6)                   @ Check SMP bit enabled?
+        orreq   r0, r0, #(1 << 6)
+        mcreq   p15, 0, r0, c1, c0, 1
+        isb
+        bl      omap4_get_sar_ram_base
+        mov     r8, r0
+        ldr     r9, [r8, #OMAP_TYPE_OFFSET]
+        cmp     r9, #0x1                        @ Check for HS device
+        bne     scu_gp_clear
+        mov     r0, #SCU_PM_NORMAL
+        mov     r1, #0x00
+        stmfd   r13!, {r4-r12, r14}
+        ldr     r12, =OMAP4_MON_SCU_PWR_INDEX
+        DO_SMC
+        ldmfd   r13!, {r4-r12, r14}
+        b       skip_scu_gp_clear
+scu_gp_clear:
+        bl      omap4_get_scu_base
+        mov     r1, #SCU_PM_NORMAL
+        bl      scu_power_mode
+skip_scu_gp_clear:
+        isb
+        dsb
+        ldmfd   sp!, {pc}
+ENDPROC(omap4_finish_suspend)
+/*
+ * ============================
+ * == CPU resume entry point ==
+ * ============================
+ *
+ * void omap4_cpu_resume(void)
+ *
+ * ROM code jumps to this function while waking up from CPU
+ * OFF or DORMANT state. Physical address of the function is
+ * stored in the SAR RAM while entering to OFF or DORMANT mode.
+ * The restore function pointer is stored at CPUx_WAKEUP_NS_PA_ADDR_OFFSET.
+ */
+ENTRY(omap4_cpu_resume)
+        /*
+         * Configure ACTRL and enable NS SMP bit access on CPU1 on HS device.
+         * OMAP44XX EMU/HS devices - CPU0 SMP bit access is enabled in PPA
+         * init and for CPU1, a secure PPA API provided. CPU0 must be ON
+         * while executing NS_SMP API on CPU1 and PPA version must be 1.4.0+.
+         * OMAP443X GP devices- SMP bit isn't accessible.
+         * OMAP446X GP devices - SMP bit access is enabled on both CPUs.
+         */
+        ldr     r8, =OMAP44XX_SAR_RAM_BASE
+        ldr     r9, [r8, #OMAP_TYPE_OFFSET]
+        cmp     r9, #0x1                        @ Skip if GP device
+        bne     skip_ns_smp_enable
+        mrc     p15, 0, r0, c0, c0, 5
+        ands    r0, r0, #0x0f
+        beq     skip_ns_smp_enable
+ppa_actrl_retry:
+        mov     r0, #OMAP4_PPA_CPU_ACTRL_SMP_INDEX
+        adr     r3, ppa_zero_params             @ Pointer to parameters
+        mov     r1, #0x0                        @ Process ID
+        mov     r2, #0x4                        @ Flag
+        mov     r6, #0xff
+        mov     r12, #0x00                      @ Secure Service ID
+        DO_SMC
+        cmp     r0, #0x0                        @ API returns 0 on success.
+        beq     enable_smp_bit
+        b       ppa_actrl_retry
+enable_smp_bit:
+        mrc     p15, 0, r0, c1, c0, 1
+        tst     r0, #(1 << 6)                   @ Check SMP bit enabled?
+        orreq   r0, r0, #(1 << 6)
+        mcreq   p15, 0, r0, c1, c0, 1
+        isb
+skip_ns_smp_enable:
+#ifdef CONFIG_CACHE_L2X0
+        /*
+         * Restore the L2 AUXCTRL and enable the L2 cache.
+         * OMAP4_MON_L2X0_AUXCTRL_INDEX =  Program the L2X0 AUXCTRL
+         * OMAP4_MON_L2X0_CTRL_INDEX =  Enable the L2 using L2X0 CTRL
+         * register r0 contains value to be programmed.
+         * L2 cache is already invalidate by ROM code as part
+         * of MPUSS OFF wakeup path.
+         */
+        ldr     r2, =OMAP44XX_L2CACHE_BASE
+        ldr     r0, [r2, #L2X0_CTRL]
+        and     r0, #0x0f
+        cmp     r0, #1
+        beq     skip_l2en                       @ Skip if already enabled
+        ldr     r3, =OMAP44XX_SAR_RAM_BASE
+        ldr     r1, [r3, #OMAP_TYPE_OFFSET]
+        cmp     r1, #0x1                        @ Check for HS device
+        bne     set_gp_por
+        ldr     r0, =OMAP4_PPA_L2_POR_INDEX
+        ldr     r1, =OMAP44XX_SAR_RAM_BASE
+        ldr     r4, [r1, #L2X0_PREFETCH_CTRL_OFFSET]
+        adr     r3, ppa_por_params
+        str     r4, [r3, #0x04]
+        mov     r1, #0x0                        @ Process ID
+        mov     r2, #0x4                        @ Flag
+        mov     r6, #0xff
+        mov     r12, #0x00                      @ Secure Service ID
+        DO_SMC
+        b       set_aux_ctrl
+set_gp_por:
+        ldr     r1, =OMAP44XX_SAR_RAM_BASE
+        ldr     r0, [r1, #L2X0_PREFETCH_CTRL_OFFSET]
+        ldr     r12, =OMAP4_MON_L2X0_PREFETCH_INDEX     @ Setup L2 PREFETCH
+        DO_SMC
+set_aux_ctrl:
+        ldr     r1, =OMAP44XX_SAR_RAM_BASE
+        ldr     r0, [r1, #L2X0_AUXCTRL_OFFSET]
+        ldr     r12, =OMAP4_MON_L2X0_AUXCTRL_INDEX      @ Setup L2 AUXCTRL
+        DO_SMC
+        mov     r0, #0x1
+        ldr     r12, =OMAP4_MON_L2X0_CTRL_INDEX         @ Enable L2 cache
+        DO_SMC
+skip_l2en:
+#endif
+        b       cpu_resume                      @ Jump to generic resume
+ENDPROC(omap4_cpu_resume)
+#endif
+#ifndef CONFIG_OMAP4_ERRATA_I688
+ENTRY(omap_bus_sync)
+        mov     pc, lr
+ENDPROC(omap_bus_sync)
+#endif
+ENTRY(omap_do_wfi)
+        stmfd   sp!, {lr}
+        /* Drain interconnect write buffers. */
+        bl omap_bus_sync
+        /*
+         * Execute an ISB instruction to ensure that all of the
+         * CP15 register changes have been committed.
+         */
+        isb
+        /*
+         * Execute a barrier instruction to ensure that all cache,
+         * TLB and branch predictor maintenance operations issued
+         * by any CPU in the cluster have completed.
+         */
+        dsb
+        dmb
+        /*
+         * Execute a WFI instruction and wait until the
+         * STANDBYWFI output is asserted to indicate that the
+         * CPU is in idle and low power state. CPU can specualatively
+         * prefetch the instructions so add NOPs after WFI. Sixteen
+         * NOPs as per Cortex-A9 pipeline.
+         */
+        wfi                                     @ Wait For Interrupt
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        ldmfd   sp!, {pc}
+ENDPROC(omap_do_wfi)
diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
index cf246b39bac7..9dd93453e563 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -26,7 +26,7 @@
 #include <linux/slab.h>
 #include <linux/pm_runtime.h>
-#include <plat/common.h>
+#include "common.h"
 #include "pm.h"
 #include "smartreflex.h"
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 037b0d7d4e05..9edcd520510f 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -41,7 +41,7 @@
 #include <plat/dmtimer.h>
 #include <asm/localtimer.h>
 #include <asm/sched_clock.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/omap_hwmod.h>
 #include <plat/omap_device.h>
 #include <plat/omap-pm.h>
diff --git a/arch/arm/mach-omap2/vc3xxx_data.c b/arch/arm/mach-omap2/vc3xxx_data.c
index cfe348e1af0e..a5ec7f8f2ea8 100644
--- a/arch/arm/mach-omap2/vc3xxx_data.c
+++ b/arch/arm/mach-omap2/vc3xxx_data.c
@@ -18,7 +18,7 @@
 #include <linux/err.h>
 #include <linux/init.h>
-#include <plat/common.h>
+#include "common.h"
 #include "prm-regbits-34xx.h"
 #include "voltage.h"
diff --git a/arch/arm/mach-omap2/vc44xx_data.c b/arch/arm/mach-omap2/vc44xx_data.c
index 2740a968145e..d70b930f2739 100644
--- a/arch/arm/mach-omap2/vc44xx_data.c
+++ b/arch/arm/mach-omap2/vc44xx_data.c
@@ -18,7 +18,7 @@
 #include <linux/err.h>
 #include <linux/init.h>
-#include <plat/common.h>
+#include "common.h"
 #include "prm44xx.h"
 #include "prm-regbits-44xx.h"
diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c
index 1f8fdf736e63..8a36342e60d2 100644
--- a/arch/arm/mach-omap2/voltage.c
+++ b/arch/arm/mach-omap2/voltage.c
@@ -27,7 +27,7 @@
 #include <linux/slab.h>
 #include <linux/clk.h>
-#include <plat/common.h>
+#include "common.h"
 #include "prm-regbits-34xx.h"
 #include "prm-regbits-44xx.h"
diff --git a/arch/arm/mach-omap2/voltagedomains3xxx_data.c b/arch/arm/mach-omap2/voltagedomains3xxx_data.c
index 071101debbbc..474559d5b072 100644
--- a/arch/arm/mach-omap2/voltagedomains3xxx_data.c
+++ b/arch/arm/mach-omap2/voltagedomains3xxx_data.c
@@ -18,7 +18,7 @@
 #include <linux/err.h>
 #include <linux/init.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/cpu.h>
 #include "prm-regbits-34xx.h"
diff --git a/arch/arm/mach-omap2/voltagedomains44xx_data.c b/arch/arm/mach-omap2/voltagedomains44xx_data.c
index c4584e9ac717..4e11d022595d 100644
--- a/arch/arm/mach-omap2/voltagedomains44xx_data.c
+++ b/arch/arm/mach-omap2/voltagedomains44xx_data.c
@@ -21,7 +21,7 @@
 #include <linux/err.h>
 #include <linux/init.h>
-#include <plat/common.h>
+#include "common.h"
 #include "prm-regbits-44xx.h"
 #include "prm44xx.h"
diff --git a/arch/arm/mach-omap2/vp.c b/arch/arm/mach-omap2/vp.c
index 66bd700a2b98..807391d84a9d 100644
--- a/arch/arm/mach-omap2/vp.c
+++ b/arch/arm/mach-omap2/vp.c
@@ -1,7 +1,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
-#include <plat/common.h>
+#include "common.h"
 #include "voltage.h"
 #include "vp.h"
diff --git a/arch/arm/mach-omap2/vp3xxx_data.c b/arch/arm/mach-omap2/vp3xxx_data.c
index 260c554b1547..bd89f80089f5 100644
--- a/arch/arm/mach-omap2/vp3xxx_data.c
+++ b/arch/arm/mach-omap2/vp3xxx_data.c
@@ -19,7 +19,7 @@
 #include <linux/err.h>
 #include <linux/init.h>
-#include <plat/common.h>
+#include "common.h"
 #include "prm-regbits-34xx.h"
 #include "voltage.h"
diff --git a/arch/arm/mach-omap2/vp44xx_data.c b/arch/arm/mach-omap2/vp44xx_data.c
index b4e77044891e..8c031d16879e 100644
--- a/arch/arm/mach-omap2/vp44xx_data.c
+++ b/arch/arm/mach-omap2/vp44xx_data.c
@@ -19,7 +19,7 @@
 #include <linux/err.h>
 #include <linux/init.h>
-#include <plat/common.h>
+#include "common.h"
 #include "prm44xx.h"
 #include "prm-regbits-44xx.h"
diff --git a/arch/arm/mach-orion5x/include/mach/io.h b/arch/arm/mach-orion5x/include/mach/io.h
index c5196101a237..e9d9afdc2659 100644
--- a/arch/arm/mach-orion5x/include/mach/io.h
+++ b/arch/arm/mach-orion5x/include/mach/io.h
@@ -15,31 +15,6 @@
 #define IO_SPACE_LIMIT          0xffffffff
-static inline void __iomem *
-__arch_ioremap(unsigned long paddr, size_t size, unsigned int mtype)
-{
-        void __iomem *retval;
-        unsigned long offs = paddr - ORION5X_REGS_PHYS_BASE;
-        if (mtype == MT_DEVICE && size && offs < ORION5X_REGS_SIZE &&
-            size <= ORION5X_REGS_SIZE && offs + size <= ORION5X_REGS_SIZE) {
-                retval = (void __iomem *)ORION5X_REGS_VIRT_BASE + offs;
-        } else {
-                retval = __arm_ioremap(paddr, size, mtype);
-        }
-        return retval;
-}
-static inline void
-__arch_iounmap(void __iomem *addr)
-{
-        if (addr < (void __iomem *)ORION5X_REGS_VIRT_BASE ||
-            addr >= (void __iomem *)(ORION5X_REGS_VIRT_BASE + ORION5X_REGS_SIZE))
-                __iounmap(addr);
-}
-#define __arch_ioremap          __arch_ioremap
-#define __arch_iounmap          __arch_iounmap
 #define __io(a)                 __typesafe_io(a)
 #define __mem_pci(a)            (a)
diff --git a/arch/arm/mach-orion5x/include/mach/vmalloc.h b/arch/arm/mach-orion5x/include/mach/vmalloc.h
deleted file mode 100644
index 06b50aeff7b9..000000000000
--- a/arch/arm/mach-orion5x/include/mach/vmalloc.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/*
- * arch/arm/mach-orion5x/include/mach/vmalloc.h
- */
-#define VMALLOC_END       0xfd800000UL
diff --git a/arch/arm/mach-picoxcell/common.c b/arch/arm/mach-picoxcell/common.c
index 34d08347be5f..ad871bd7b1ab 100644
--- a/arch/arm/mach-picoxcell/common.c
+++ b/arch/arm/mach-picoxcell/common.c
@@ -11,6 +11,7 @@
 #include <linux/irqdomain.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
+#include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <asm/mach/arch.h>
@@ -33,22 +34,20 @@ static const char *picoxcell_dt_match[] = {
 };
 static const struct of_device_id vic_of_match[] __initconst = {
-        { .compatible = "arm,pl192-vic" },
+        { .compatible = "arm,pl192-vic", .data = vic_of_init, },
        { /* Sentinel */ }
 };
 static void __init picoxcell_init_irq(void)
 {
-        vic_init(IO_ADDRESS(PICOXCELL_VIC0_BASE), 0, ~0, 0);
+        of_irq_init(vic_of_match);
-        vic_init(IO_ADDRESS(PICOXCELL_VIC1_BASE), 32, ~0, 0);
-        irq_domain_generate_simple(vic_of_match, PICOXCELL_VIC0_BASE, 0);
-        irq_domain_generate_simple(vic_of_match, PICOXCELL_VIC1_BASE, 32);
 }
 DT_MACHINE_START(PICOXCELL, "Picochip picoXcell")
        .map_io         = picoxcell_map_io,
        .nr_irqs        = ARCH_NR_IRQS,
        .init_irq       = picoxcell_init_irq,
+        .handle_irq     = vic_handle_irq,
        .timer          = &picoxcell_timer,
        .init_machine   = picoxcell_init_machine,
        .dt_compat      = picoxcell_dt_match,
diff --git a/arch/arm/mach-picoxcell/include/mach/entry-macro.S b/arch/arm/mach-picoxcell/include/mach/entry-macro.S
index a6b09f75d9df..9b505ac00be9 100644
--- a/arch/arm/mach-picoxcell/include/mach/entry-macro.S
+++ b/arch/arm/mach-picoxcell/include/mach/entry-macro.S
@@ -9,11 +9,8 @@
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */
-#include <mach/hardware.h>
+        .macro  disable_fiq
-#include <mach/irqs.h>
+        .endm
-#include <mach/map.h>
-#define VA_VIC0         IO_ADDRESS(PICOXCELL_VIC0_BASE)
+        .macro  arch_ret_to_user, tmp1, tmp2
-#define VA_VIC1         IO_ADDRESS(PICOXCELL_VIC1_BASE)
+        .endm
-#include <asm/entry-macro-vic2.S>
diff --git a/arch/arm/mach-picoxcell/include/mach/vmalloc.h b/arch/arm/mach-picoxcell/include/mach/vmalloc.h
deleted file mode 100644
index 0216cc4b1f0b..000000000000
--- a/arch/arm/mach-picoxcell/include/mach/vmalloc.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * Copyright (c) 2011 Picochip Ltd., Jamie Iles
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#define VMALLOC_END     0xfe000000UL
diff --git a/arch/arm/mach-pnx4008/include/mach/system.h b/arch/arm/mach-pnx4008/include/mach/system.h
index 5dda2bb55f8d..5d6384a6128c 100644
--- a/arch/arm/mach-pnx4008/include/mach/system.h
+++ b/arch/arm/mach-pnx4008/include/mach/system.h
@@ -32,7 +32,7 @@ static void arch_idle(void)
 static inline void arch_reset(char mode, const char *cmd)
 {
-        cpu_reset(0);
+        soft_restart(0);
 }
 #endif
diff --git a/arch/arm/mach-pnx4008/include/mach/vmalloc.h b/arch/arm/mach-pnx4008/include/mach/vmalloc.h
deleted file mode 100644
index 184913c71141..000000000000
--- a/arch/arm/mach-pnx4008/include/mach/vmalloc.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/include/mach/vmalloc.h
- *
- * Author: Vitaly Wool <source@mvista.com>
- *
- * 2006 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-/*
- * Just any arbitrary offset to the start of the vmalloc VM area: the
- * current 8MB value just means that there will be a 8MB "hole" after the
- * physical memory until the kernel virtual memory starts.  That means that
- * any out-of-bounds memory accesses will hopefully be caught.
- * The vmalloc() routines leaves a hole of 4kB between each vmalloced
- * area for the same reason. ;)
- */
-#define VMALLOC_END       0xd0000000UL
diff --git a/arch/arm/mach-prima2/include/mach/map.h b/arch/arm/mach-prima2/include/mach/map.h
index 66b1ae2e553f..6f243532570c 100644
--- a/arch/arm/mach-prima2/include/mach/map.h
+++ b/arch/arm/mach-prima2/include/mach/map.h
@@ -9,8 +9,10 @@
 #ifndef __MACH_PRIMA2_MAP_H__
 #define __MACH_PRIMA2_MAP_H__
-#include <mach/vmalloc.h>
+#include <linux/const.h>
-#define SIRFSOC_VA(x)                   (VMALLOC_END + ((x) & 0x00FFF000))
+#define SIRFSOC_VA_BASE         _AC(0xFEC00000, UL)
+#define SIRFSOC_VA(x)           (SIRFSOC_VA_BASE + ((x) & 0x00FFF000))
 #endif
diff --git a/arch/arm/mach-prima2/include/mach/vmalloc.h b/arch/arm/mach-prima2/include/mach/vmalloc.h
deleted file mode 100644
index c9f90fec78e3..000000000000
--- a/arch/arm/mach-prima2/include/mach/vmalloc.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * arch/arm/ach-prima2/include/mach/vmalloc.h
- *
- * Copyright (c) 2010 – 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
- *
- * Licensed under GPLv2 or later.
- */
-#ifndef __MACH_VMALLOC_H
-#define __MACH_VMALLOC_H
-#include <linux/const.h>
-#define VMALLOC_END    _AC(0xFEC00000, UL)
-#endif
diff --git a/arch/arm/mach-pxa/include/mach/entry-macro.S b/arch/arm/mach-pxa/include/mach/entry-macro.S
index a73bc86a3c26..260c0c17692a 100644
--- a/arch/arm/mach-pxa/include/mach/entry-macro.S
+++ b/arch/arm/mach-pxa/include/mach/entry-macro.S
@@ -7,45 +7,9 @@
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */
-#include <mach/hardware.h>
-#include <mach/irqs.h>
                .macro  disable_fiq
                .endm
-                .macro  get_irqnr_preamble, base, tmp
-                .endm
                .macro  arch_ret_to_user, tmp1, tmp2
                .endm
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-                mrc     p15, 0, \tmp, c0, c0, 0         @ CPUID
-                mov     \tmp, \tmp, lsr #13
-                and     \tmp, \tmp, #0x7                @ Core G
-                cmp     \tmp, #1
-                bhi     1002f
-                @ Core Generation 1 (PXA25x)
-                mov     \base, #io_p2v(0x40000000)      @ IIR Ctl = 0x40d00000
-                add     \base, \base, #0x00d00000
-                ldr     \irqstat, [\base, #0]           @ ICIP
-                ldr     \irqnr, [\base, #4]             @ ICMR
-                ands    \irqnr, \irqstat, \irqnr
-                beq     1001f
-                rsb     \irqstat, \irqnr, #0
-                and     \irqstat, \irqstat, \irqnr
-                clz     \irqnr, \irqstat
-                rsb     \irqnr, \irqnr, #(31 + PXA_IRQ(0))
-                b       1001f
-1002:
-                @ Core Generation 2 (PXA27x) or Core Generation 3 (PXA3xx)
-                mrc     p6, 0, \irqstat, c5, c0, 0      @ ICHP
-                tst     \irqstat, #0x80000000
-                beq     1001f
-                bic     \irqstat, \irqstat, #0x80000000
-                mov     \irqnr, \irqstat, lsr #16
-                add     \irqnr, \irqnr, #(PXA_IRQ(0))
-1001:
-                .endm
diff --git a/arch/arm/mach-pxa/include/mach/vmalloc.h b/arch/arm/mach-pxa/include/mach/vmalloc.h
deleted file mode 100644
index bfecfbf5f460..000000000000
--- a/arch/arm/mach-pxa/include/mach/vmalloc.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/*
- * arch/arm/mach-pxa/include/mach/vmalloc.h
- *
- * Author:      Nicolas Pitre
- * Copyright:   (C) 2001 MontaVista Software Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#define VMALLOC_END       (0xe8000000UL)
diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c
index b938fc2c316a..4f47a760398f 100644
--- a/arch/arm/mach-pxa/mioa701.c
+++ b/arch/arm/mach-pxa/mioa701.c
@@ -752,6 +752,7 @@ static void mioa701_machine_exit(void)
 MACHINE_START(MIOA701, "MIO A701")
        .atag_offset    = 0x100,
+        .restart_mode   = 's',
        .map_io         = &pxa27x_map_io,
        .init_irq       = &pxa27x_init_irq,
        .handle_irq     = &pxa27x_handle_irq,
diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c
index 50c833177866..afcb48a5792c 100644
--- a/arch/arm/mach-pxa/poodle.c
+++ b/arch/arm/mach-pxa/poodle.c
@@ -420,17 +420,11 @@ static void poodle_poweroff(void)
        arm_machine_restart('h', NULL);
 }
-static void poodle_restart(char mode, const char *cmd)
-{
-        arm_machine_restart('h', cmd);
-}
 static void __init poodle_init(void)
 {
        int ret = 0;
        pm_power_off = poodle_poweroff;
-        arm_pm_restart = poodle_restart;
        PCFR |= PCFR_OPDE;
diff --git a/arch/arm/mach-pxa/reset.c b/arch/arm/mach-pxa/reset.c
index 01e9d643394a..b8bcda15da81 100644
--- a/arch/arm/mach-pxa/reset.c
+++ b/arch/arm/mach-pxa/reset.c
@@ -88,7 +88,7 @@ void arch_reset(char mode, const char *cmd)
        switch (mode) {
        case 's':
                /* Jump into ROM at address 0 */
-                cpu_reset(0);
+                soft_restart(0);
                break;
        case 'g':
                do_gpio_reset();
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
index 953a9195f9e5..2f57d94de727 100644
--- a/arch/arm/mach-pxa/spitz.c
+++ b/arch/arm/mach-pxa/spitz.c
@@ -982,6 +982,7 @@ static void __init spitz_fixup(struct tag *tags, char **cmdline,
 #ifdef CONFIG_MACH_SPITZ
 MACHINE_START(SPITZ, "SHARP Spitz")
+        .restart_mode   = 'g',
        .fixup          = spitz_fixup,
        .map_io         = pxa27x_map_io,
        .init_irq       = pxa27x_init_irq,
@@ -993,6 +994,7 @@ MACHINE_END
 #ifdef CONFIG_MACH_BORZOI
 MACHINE_START(BORZOI, "SHARP Borzoi")
+        .restart_mode   = 'g',
        .fixup          = spitz_fixup,
        .map_io         = pxa27x_map_io,
        .init_irq       = pxa27x_init_irq,
@@ -1004,6 +1006,7 @@ MACHINE_END
 #ifdef CONFIG_MACH_AKITA
 MACHINE_START(AKITA, "SHARP Akita")
+        .restart_mode   = 'g',
        .fixup          = spitz_fixup,
        .map_io         = pxa27x_map_io,
        .init_irq       = pxa27x_init_irq,
diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c
index 402b0c96613b..ef6453041cf1 100644
--- a/arch/arm/mach-pxa/tosa.c
+++ b/arch/arm/mach-pxa/tosa.c
@@ -970,6 +970,7 @@ static void __init fixup_tosa(struct tag *tags, char **cmdline,
 }
 MACHINE_START(TOSA, "SHARP Tosa")
+        .restart_mode   = 'g',
        .fixup          = fixup_tosa,
        .map_io         = pxa25x_map_io,
        .nr_irqs        = TOSA_NR_IRQS,
diff --git a/arch/arm/mach-realview/include/mach/entry-macro.S b/arch/arm/mach-realview/include/mach/entry-macro.S
index 4071164aebaa..e8a5179c2653 100644
--- a/arch/arm/mach-realview/include/mach/entry-macro.S
+++ b/arch/arm/mach-realview/include/mach/entry-macro.S
@@ -7,8 +7,6 @@
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */
-#include <mach/hardware.h>
-#include <asm/hardware/entry-macro-gic.S>
                .macro  disable_fiq
                .endm
diff --git a/arch/arm/mach-realview/include/mach/vmalloc.h b/arch/arm/mach-realview/include/mach/vmalloc.h
deleted file mode 100644
index a2a4c6861407..000000000000
--- a/arch/arm/mach-realview/include/mach/vmalloc.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- *  arch/arm/mach-realview/include/mach/vmalloc.h
- *
- *  Copyright (C) 2003 ARM Limited
- *  Copyright (C) 2000 Russell King.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#define VMALLOC_END             0xf8000000UL
diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c
index 026c66ad7ec2..1ca944aea7f8 100644
--- a/arch/arm/mach-realview/realview_eb.c
+++ b/arch/arm/mach-realview/realview_eb.c
@@ -91,8 +91,8 @@ static struct map_desc realview_eb_io_desc[] __initdata = {
 static struct map_desc realview_eb11mp_io_desc[] __initdata = {
        {
-                .virtual        = IO_ADDRESS(REALVIEW_EB11MP_GIC_CPU_BASE),
+                .virtual        = IO_ADDRESS(REALVIEW_EB11MP_SCU_BASE),
-                .pfn            = __phys_to_pfn(REALVIEW_EB11MP_GIC_CPU_BASE),
+                .pfn            = __phys_to_pfn(REALVIEW_EB11MP_SCU_BASE),
                .length         = SZ_4K,
                .type           = MT_DEVICE,
        }, {
@@ -469,6 +469,7 @@ MACHINE_START(REALVIEW_EB, "ARM-RealView EB")
        .init_early     = realview_init_early,
        .init_irq       = gic_init_irq,
        .timer          = &realview_eb_timer,
+        .handle_irq     = gic_handle_irq,
        .init_machine   = realview_eb_init,
 #ifdef CONFIG_ZONE_DMA
        .dma_zone_size  = SZ_256M,
diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c
index c057540ec776..bd8fec8b20d9 100644
--- a/arch/arm/mach-realview/realview_pb1176.c
+++ b/arch/arm/mach-realview/realview_pb1176.c
@@ -392,6 +392,7 @@ MACHINE_START(REALVIEW_PB1176, "ARM-RealView PB1176")
        .init_early     = realview_init_early,
        .init_irq       = gic_init_irq,
        .timer          = &realview_pb1176_timer,
+        .handle_irq     = gic_handle_irq,
        .init_machine   = realview_pb1176_init,
 #ifdef CONFIG_ZONE_DMA
        .dma_zone_size  = SZ_256M,
diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c
index 671ad6d6ff00..fa73ba81a449 100644
--- a/arch/arm/mach-realview/realview_pb11mp.c
+++ b/arch/arm/mach-realview/realview_pb11mp.c
@@ -366,6 +366,7 @@ MACHINE_START(REALVIEW_PB11MP, "ARM-RealView PB11MPCore")
        .init_early     = realview_init_early,
        .init_irq       = gic_init_irq,
        .timer          = &realview_pb11mp_timer,
+        .handle_irq     = gic_handle_irq,
        .init_machine   = realview_pb11mp_init,
 #ifdef CONFIG_ZONE_DMA
        .dma_zone_size  = SZ_256M,
diff --git a/arch/arm/mach-realview/realview_pba8.c b/arch/arm/mach-realview/realview_pba8.c
index cbf22df4ad5b..6e5f2b9ddb7e 100644
--- a/arch/arm/mach-realview/realview_pba8.c
+++ b/arch/arm/mach-realview/realview_pba8.c
@@ -316,6 +316,7 @@ MACHINE_START(REALVIEW_PBA8, "ARM-RealView PB-A8")
        .init_early     = realview_init_early,
        .init_irq       = gic_init_irq,
        .timer          = &realview_pba8_timer,
+        .handle_irq     = gic_handle_irq,
        .init_machine   = realview_pba8_init,
 #ifdef CONFIG_ZONE_DMA
        .dma_zone_size  = SZ_256M,
diff --git a/arch/arm/mach-realview/realview_pbx.c b/arch/arm/mach-realview/realview_pbx.c
index 63c4114afae9..7aabc21af01c 100644
--- a/arch/arm/mach-realview/realview_pbx.c
+++ b/arch/arm/mach-realview/realview_pbx.c
@@ -98,8 +98,8 @@ static struct map_desc realview_pbx_io_desc[] __initdata = {
 static struct map_desc realview_local_io_desc[] __initdata = {
        {
-                .virtual        = IO_ADDRESS(REALVIEW_PBX_TILE_GIC_CPU_BASE),
+                .virtual        = IO_ADDRESS(REALVIEW_PBX_TILE_SCU_BASE),
-                .pfn            = __phys_to_pfn(REALVIEW_PBX_TILE_GIC_CPU_BASE),
+                .pfn            = __phys_to_pfn(REALVIEW_PBX_TILE_SCU_BASE),
                .length         = SZ_4K,
                .type           = MT_DEVICE,
        }, {
@@ -399,6 +399,7 @@ MACHINE_START(REALVIEW_PBX, "ARM-RealView PBX")
        .init_early     = realview_init_early,
        .init_irq       = gic_init_irq,
        .timer          = &realview_pbx_timer,
+        .handle_irq     = gic_handle_irq,
        .init_machine   = realview_pbx_init,
 #ifdef CONFIG_ZONE_DMA
        .dma_zone_size  = SZ_256M,
diff --git a/arch/arm/mach-rpc/include/mach/system.h b/arch/arm/mach-rpc/include/mach/system.h
index 45c7b935dc45..a354f4d092c8 100644
--- a/arch/arm/mach-rpc/include/mach/system.h
+++ b/arch/arm/mach-rpc/include/mach/system.h
@@ -23,5 +23,5 @@ static inline void arch_reset(char mode, const char *cmd)
        /*
         * Jump into the ROM
         */
-        cpu_reset(0);
+        soft_restart(0);
 }
diff --git a/arch/arm/mach-rpc/include/mach/vmalloc.h b/arch/arm/mach-rpc/include/mach/vmalloc.h
deleted file mode 100644
index fb700228637a..000000000000
--- a/arch/arm/mach-rpc/include/mach/vmalloc.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/*
- *  arch/arm/mach-rpc/include/mach/vmalloc.h
- *
- *  Copyright (C) 1997 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#define VMALLOC_END       0xdc000000UL
diff --git a/arch/arm/mach-s3c2410/include/mach/system-reset.h b/arch/arm/mach-s3c2410/include/mach/system-reset.h
index 6faadcee7729..913893d44650 100644
--- a/arch/arm/mach-s3c2410/include/mach/system-reset.h
+++ b/arch/arm/mach-s3c2410/include/mach/system-reset.h
@@ -19,7 +19,7 @@ static void
 arch_reset(char mode, const char *cmd)
 {
        if (mode == 's') {
-                cpu_reset(0);
+                soft_restart(0);
        }
        if (s3c24xx_reset_hook)
@@ -28,5 +28,5 @@ arch_reset(char mode, const char *cmd)
        arch_wdt_reset();
        /* we'll take a jump through zero as a poor second */
-        cpu_reset(0);
+        soft_restart(0);
 }
diff --git a/arch/arm/mach-s3c2410/include/mach/vmalloc.h b/arch/arm/mach-s3c2410/include/mach/vmalloc.h
deleted file mode 100644
index 7a311e8dddba..000000000000
--- a/arch/arm/mach-s3c2410/include/mach/vmalloc.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/vmalloc.h
- *
- * from arch/arm/mach-iop3xx/include/mach/vmalloc.h
- *
- * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
- *                    http://www.simtec.co.uk/products/SWLINUX/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2410 vmalloc definition
-*/
-#ifndef __ASM_ARCH_VMALLOC_H
-#define __ASM_ARCH_VMALLOC_H
-#define VMALLOC_END     0xF6000000UL
-#endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/mach-s3c64xx/include/mach/entry-macro.S b/arch/arm/mach-s3c64xx/include/mach/entry-macro.S
index dd362604dcce..dc2bc15142ce 100644
--- a/arch/arm/mach-s3c64xx/include/mach/entry-macro.S
+++ b/arch/arm/mach-s3c64xx/include/mach/entry-macro.S
@@ -12,7 +12,8 @@
 * warranty of any kind, whether express or implied.
 */
-#include <mach/map.h>
+                .macro  disable_fiq
-#include <mach/irqs.h>
+                .endm
-#include <asm/entry-macro-vic2.S>
+                .macro  arch_ret_to_user, tmp1, tmp2
+                .endm
diff --git a/arch/arm/mach-s3c64xx/include/mach/system.h b/arch/arm/mach-s3c64xx/include/mach/system.h
index 2e58cb7a7147..d8ca5786ba25 100644
--- a/arch/arm/mach-s3c64xx/include/mach/system.h
+++ b/arch/arm/mach-s3c64xx/include/mach/system.h
@@ -24,7 +24,7 @@ static void arch_reset(char mode, const char *cmd)
                arch_wdt_reset();
        /* if all else fails, or mode was for soft, jump to 0 */
-        cpu_reset(0);
+        soft_restart(0);
 }
 #endif /* __ASM_ARCH_IRQ_H */
diff --git a/arch/arm/mach-s3c64xx/include/mach/vmalloc.h b/arch/arm/mach-s3c64xx/include/mach/vmalloc.h
deleted file mode 100644
index 23f75e556a30..000000000000
--- a/arch/arm/mach-s3c64xx/include/mach/vmalloc.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* arch/arm/mach-s3c64xx/include/mach/vmalloc.h
- *
- * from arch/arm/mach-iop3xx/include/mach/vmalloc.h
- *
- * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
- *                    http://www.simtec.co.uk/products/SWLINUX/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C6400 vmalloc definition
-*/
-#ifndef __ASM_ARCH_VMALLOC_H
-#define __ASM_ARCH_VMALLOC_H
-#define VMALLOC_END     0xF6000000UL
-#endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/mach-s3c64xx/mach-anw6410.c b/arch/arm/mach-s3c64xx/mach-anw6410.c
index 8eba88e7209e..2bbc14d93428 100644
--- a/arch/arm/mach-s3c64xx/mach-anw6410.c
+++ b/arch/arm/mach-s3c64xx/mach-anw6410.c
@@ -30,6 +30,7 @@
 #include <video/platform_lcd.h>
+#include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
@@ -236,6 +237,7 @@ MACHINE_START(ANW6410, "A&W6410")
        .atag_offset    = 0x100,
        .init_irq       = s3c6410_init_irq,
+        .handle_irq     = vic_handle_irq,
        .map_io         = anw6410_map_io,
        .init_machine   = anw6410_machine_init,
        .timer          = &s3c24xx_timer,
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c
index d04b65448510..988ac2e48f08 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410.c
@@ -37,6 +37,7 @@
 #include <linux/mfd/wm831x/irq.h>
 #include <linux/mfd/wm831x/gpio.h>
+#include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
@@ -711,6 +712,7 @@ MACHINE_START(WLF_CRAGG_6410, "Wolfson Cragganmore 6410")
        /* Maintainer: Mark Brown <broonie@opensource.wolfsonmicro.com> */
        .atag_offset    = 0x100,
        .init_irq       = s3c6410_init_irq,
+        .handle_irq     = vic_handle_irq,
        .map_io         = crag6410_map_io,
        .init_machine   = crag6410_machine_init,
        .timer          = &s3c24xx_timer,
diff --git a/arch/arm/mach-s3c64xx/mach-hmt.c b/arch/arm/mach-s3c64xx/mach-hmt.c
index 952f75ff5deb..c5955f301709 100644
--- a/arch/arm/mach-s3c64xx/mach-hmt.c
+++ b/arch/arm/mach-s3c64xx/mach-hmt.c
@@ -29,6 +29,7 @@
 #include <mach/hardware.h>
 #include <mach/map.h>
+#include <asm/hardware/vic.h>
 #include <asm/irq.h>
 #include <asm/mach-types.h>
@@ -267,6 +268,7 @@ MACHINE_START(HMT, "Airgoo-HMT")
        /* Maintainer: Peter Korsgaard <jacmet@sunsite.dk> */
        .atag_offset    = 0x100,
        .init_irq       = s3c6410_init_irq,
+        .handle_irq     = vic_handle_irq,
        .map_io         = hmt_map_io,
        .init_machine   = hmt_machine_init,
        .timer          = &s3c24xx_timer,
diff --git a/arch/arm/mach-s3c64xx/mach-mini6410.c b/arch/arm/mach-s3c64xx/mach-mini6410.c
index 1bc85c359498..4415c85e3f6f 100644
--- a/arch/arm/mach-s3c64xx/mach-mini6410.c
+++ b/arch/arm/mach-s3c64xx/mach-mini6410.c
@@ -24,6 +24,7 @@
 #include <linux/serial_core.h>
 #include <linux/types.h>
+#include <asm/hardware/vic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -345,6 +346,7 @@ MACHINE_START(MINI6410, "MINI6410")
        /* Maintainer: Darius Augulis <augulis.darius@gmail.com> */
        .atag_offset    = 0x100,
        .init_irq       = s3c6410_init_irq,
+        .handle_irq     = vic_handle_irq,
        .map_io         = mini6410_map_io,
        .init_machine   = mini6410_machine_init,
        .timer          = &s3c24xx_timer,
diff --git a/arch/arm/mach-s3c64xx/mach-ncp.c b/arch/arm/mach-s3c64xx/mach-ncp.c
index cb13cba98b3d..9b2c610eac2a 100644
--- a/arch/arm/mach-s3c64xx/mach-ncp.c
+++ b/arch/arm/mach-s3c64xx/mach-ncp.c
@@ -25,6 +25,7 @@
 #include <video/platform_lcd.h>
+#include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
@@ -99,6 +100,7 @@ MACHINE_START(NCP, "NCP")
        /* Maintainer: Samsung Electronics */
        .atag_offset    = 0x100,
        .init_irq       = s3c6410_init_irq,
+        .handle_irq     = vic_handle_irq,
        .map_io         = ncp_map_io,
        .init_machine   = ncp_machine_init,
        .timer          = &s3c24xx_timer,
diff --git a/arch/arm/mach-s3c64xx/mach-real6410.c b/arch/arm/mach-s3c64xx/mach-real6410.c
index 87281e4b8471..dbab49f2713e 100644
--- a/arch/arm/mach-s3c64xx/mach-real6410.c
+++ b/arch/arm/mach-s3c64xx/mach-real6410.c
@@ -25,6 +25,7 @@
 #include <linux/serial_core.h>
 #include <linux/types.h>
+#include <asm/hardware/vic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -326,6 +327,7 @@ MACHINE_START(REAL6410, "REAL6410")
        .atag_offset    = 0x100,
        .init_irq       = s3c6410_init_irq,
+        .handle_irq     = vic_handle_irq,
        .map_io         = real6410_map_io,
        .init_machine   = real6410_machine_init,
        .timer          = &s3c24xx_timer,
diff --git a/arch/arm/mach-s3c64xx/mach-smartq5.c b/arch/arm/mach-s3c64xx/mach-smartq5.c
index 94c831d88365..053945282652 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq5.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq5.c
@@ -17,6 +17,7 @@
 #include <linux/leds.h>
 #include <linux/platform_device.h>
+#include <asm/hardware/vic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -148,6 +149,7 @@ MACHINE_START(SMARTQ5, "SmartQ 5")
        /* Maintainer: Maurus Cuelenaere <mcuelenaere AT gmail DOT com> */
        .atag_offset    = 0x100,
        .init_irq       = s3c6410_init_irq,
+        .handle_irq     = vic_handle_irq,
        .map_io         = smartq_map_io,
        .init_machine   = smartq5_machine_init,
        .timer          = &s3c24xx_timer,
diff --git a/arch/arm/mach-s3c64xx/mach-smartq7.c b/arch/arm/mach-s3c64xx/mach-smartq7.c
index f112547ce80a..a58d1ba5cba2 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq7.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq7.c
@@ -17,6 +17,7 @@
 #include <linux/leds.h>
 #include <linux/platform_device.h>
+#include <asm/hardware/vic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -164,6 +165,7 @@ MACHINE_START(SMARTQ7, "SmartQ 7")
        /* Maintainer: Maurus Cuelenaere <mcuelenaere AT gmail DOT com> */
        .atag_offset    = 0x100,
        .init_irq       = s3c6410_init_irq,
+        .handle_irq     = vic_handle_irq,
        .map_io         = smartq_map_io,
        .init_machine   = smartq7_machine_init,
        .timer          = &s3c24xx_timer,
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6400.c b/arch/arm/mach-s3c64xx/mach-smdk6400.c
index 73450c2b530a..be28a59e3f57 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6400.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6400.c
@@ -22,6 +22,7 @@
 #include <asm/mach-types.h>
+#include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
@@ -88,6 +89,7 @@ MACHINE_START(SMDK6400, "SMDK6400")
        .atag_offset    = 0x100,
        .init_irq       = s3c6400_init_irq,
+        .handle_irq     = vic_handle_irq,
        .map_io         = smdk6400_map_io,
        .init_machine   = smdk6400_machine_init,
        .timer          = &s3c24xx_timer,
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c
index 8bc8edd85e5a..08309155d087 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
@@ -43,6 +43,7 @@
 #include <video/platform_lcd.h>
+#include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
@@ -700,6 +701,7 @@ MACHINE_START(SMDK6410, "SMDK6410")
        .atag_offset    = 0x100,
        .init_irq       = s3c6410_init_irq,
+        .handle_irq     = vic_handle_irq,
        .map_io         = smdk6410_map_io,
        .init_machine   = smdk6410_machine_init,
        .timer          = &s3c24xx_timer,
diff --git a/arch/arm/mach-s5p64x0/include/mach/entry-macro.S b/arch/arm/mach-s5p64x0/include/mach/entry-macro.S
index 10b62b4f8211..fbb246d0a3df 100644
--- a/arch/arm/mach-s5p64x0/include/mach/entry-macro.S
+++ b/arch/arm/mach-s5p64x0/include/mach/entry-macro.S
@@ -10,7 +10,8 @@
 * published by the Free Software Foundation.
 */
-#include <mach/map.h>
+                .macro  disable_fiq
-#include <plat/irqs.h>
+                .endm
-#include <asm/entry-macro-vic2.S>
+                .macro  arch_ret_to_user, tmp1, tmp2
+                .endm
diff --git a/arch/arm/mach-s5p64x0/include/mach/vmalloc.h b/arch/arm/mach-s5p64x0/include/mach/vmalloc.h
deleted file mode 100644
index 38dcc71a03cc..000000000000
--- a/arch/arm/mach-s5p64x0/include/mach/vmalloc.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* linux/arch/arm/mach-s5p64x0/include/mach/vmalloc.h
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * Copyright 2010 Ben Dooks <ben-linux@fluff.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C6400 vmalloc definition
-*/
-#ifndef __ASM_ARCH_VMALLOC_H
-#define __ASM_ARCH_VMALLOC_H
-#define VMALLOC_END     0xF6000000UL
-#endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6440.c b/arch/arm/mach-s5p64x0/mach-smdk6440.c
index 4a1250cd1356..c272c3f7d6de 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6440.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6440.c
@@ -27,6 +27,7 @@
 #include <video/platform_lcd.h>
+#include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/irq.h>
@@ -242,6 +243,7 @@ MACHINE_START(SMDK6440, "SMDK6440")
        .atag_offset    = 0x100,
        .init_irq       = s5p6440_init_irq,
+        .handle_irq     = vic_handle_irq,
        .map_io         = smdk6440_map_io,
        .init_machine   = smdk6440_machine_init,
        .timer          = &s5p_timer,
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6450.c b/arch/arm/mach-s5p64x0/mach-smdk6450.c
index 0ab129ecf009..7a4700959616 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6450.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6450.c
@@ -27,6 +27,7 @@
 #include <video/platform_lcd.h>
+#include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/irq.h>
@@ -262,6 +263,7 @@ MACHINE_START(SMDK6450, "SMDK6450")
        .atag_offset    = 0x100,
        .init_irq       = s5p6450_init_irq,
+        .handle_irq     = vic_handle_irq,
        .map_io         = smdk6450_map_io,
        .init_machine   = smdk6450_machine_init,
        .timer          = &s5p_timer,
diff --git a/arch/arm/mach-s5pc100/include/mach/entry-macro.S b/arch/arm/mach-s5pc100/include/mach/entry-macro.S
index ba76af052c81..b8c242edfa22 100644
--- a/arch/arm/mach-s5pc100/include/mach/entry-macro.S
+++ b/arch/arm/mach-s5pc100/include/mach/entry-macro.S
@@ -12,39 +12,14 @@
 * warranty of any kind, whether express or implied.
 */
-#include <asm/hardware/vic.h>
-#include <mach/map.h>
-#include <plat/irqs.h>
        .macro  disable_fiq
        .endm
        .macro  get_irqnr_preamble, base, tmp
-        ldr     \base, =VA_VIC0
        .endm
        .macro  arch_ret_to_user, tmp1, tmp2
        .endm
        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-        @ check the vic0
-        mov     \irqnr, # S5P_IRQ_OFFSET + 31
-        ldr     \irqstat, [ \base, # VIC_IRQ_STATUS ]
-        teq     \irqstat, #0
-        @ otherwise try vic1
-        addeq   \tmp, \base, #(VA_VIC1 - VA_VIC0)
-        addeq   \irqnr, \irqnr, #32
-        ldreq   \irqstat, [ \tmp, # VIC_IRQ_STATUS ]
-        teqeq   \irqstat, #0
-        @ otherwise try vic2
-        addeq   \tmp, \base, #(VA_VIC2 - VA_VIC0)
-        addeq   \irqnr, \irqnr, #32
-        ldreq   \irqstat, [ \tmp, # VIC_IRQ_STATUS ]
-        teqeq   \irqstat, #0
-        clzne   \irqstat, \irqstat
-        subne   \irqnr, \irqnr, \irqstat
        .endm
diff --git a/arch/arm/mach-s5pc100/include/mach/vmalloc.h b/arch/arm/mach-s5pc100/include/mach/vmalloc.h
deleted file mode 100644
index 44c8e5726d9d..000000000000
--- a/arch/arm/mach-s5pc100/include/mach/vmalloc.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* arch/arm/mach-s5pc100/include/mach/vmalloc.h
- *
- * Copyright 2010 Ben Dooks <ben-linux@fluff.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C6400 vmalloc definition
-*/
-#ifndef __ASM_ARCH_VMALLOC_H
-#define __ASM_ARCH_VMALLOC_H
-#define VMALLOC_END     0xF6000000UL
-#endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c
index 26f5c91c9427..93ebe3a92d10 100644
--- a/arch/arm/mach-s5pc100/mach-smdkc100.c
+++ b/arch/arm/mach-s5pc100/mach-smdkc100.c
@@ -25,6 +25,7 @@
 #include <linux/input.h>
 #include <linux/pwm_backlight.h>
+#include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -250,6 +251,7 @@ MACHINE_START(SMDKC100, "SMDKC100")
        /* Maintainer: Byungho Min <bhmin@samsung.com> */
        .atag_offset    = 0x100,
        .init_irq       = s5pc100_init_irq,
+        .handle_irq     = vic_handle_irq,
        .map_io         = smdkc100_map_io,
        .init_machine   = smdkc100_machine_init,
        .timer          = &s3c24xx_timer,
diff --git a/arch/arm/mach-s5pv210/include/mach/entry-macro.S b/arch/arm/mach-s5pv210/include/mach/entry-macro.S
index 3aa41ac59f07..bebca1b5d0b1 100644
--- a/arch/arm/mach-s5pv210/include/mach/entry-macro.S
+++ b/arch/arm/mach-s5pv210/include/mach/entry-macro.S
@@ -10,45 +10,8 @@
 * published by the Free Software Foundation.
 */
-#include <asm/hardware/vic.h>
-#include <mach/map.h>
-#include <plat/irqs.h>
        .macro  disable_fiq
        .endm
-        .macro  get_irqnr_preamble, base, tmp
-        ldr     \base, =VA_VIC0
-        .endm
        .macro  arch_ret_to_user, tmp1, tmp2
        .endm
-        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-        @ check the vic0
-        mov     \irqnr, # S5P_IRQ_OFFSET + 31
-        ldr     \irqstat, [ \base, # VIC_IRQ_STATUS ]
-        teq     \irqstat, #0
-        @ otherwise try vic1
-        addeq   \tmp, \base, #(VA_VIC1 - VA_VIC0)
-        addeq   \irqnr, \irqnr, #32
-        ldreq   \irqstat, [ \tmp, # VIC_IRQ_STATUS ]
-        teqeq   \irqstat, #0
-        @ otherwise try vic2
-        addeq   \tmp, \base, #(VA_VIC2 - VA_VIC0)
-        addeq   \irqnr, \irqnr, #32
-        ldreq   \irqstat, [ \tmp, # VIC_IRQ_STATUS ]
-        teqeq   \irqstat, #0
-        @ otherwise try vic3
-        addeq   \tmp, \base, #(VA_VIC3 - VA_VIC0)
-        addeq   \irqnr, \irqnr, #32
-        ldreq   \irqstat, [ \tmp, # VIC_IRQ_STATUS ]
-        teqeq   \irqstat, #0
-        clzne   \irqstat, \irqstat
-        subne   \irqnr, \irqnr, \irqstat
-        .endm
diff --git a/arch/arm/mach-s5pv210/include/mach/vmalloc.h b/arch/arm/mach-s5pv210/include/mach/vmalloc.h
deleted file mode 100644
index a6c659d68a5d..000000000000
--- a/arch/arm/mach-s5pv210/include/mach/vmalloc.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* linux/arch/arm/mach-s5p6442/include/mach/vmalloc.h
- *
- * Copyright 2010 Ben Dooks <ben-linux@fluff.org>
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * Based on arch/arm/mach-s5p6442/include/mach/vmalloc.h
- *
- * S5PV210 vmalloc definition
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#ifndef __ASM_ARCH_VMALLOC_H
-#define __ASM_ARCH_VMALLOC_H __FILE__
-#define VMALLOC_END     0xF6000000UL
-#endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c
index 5811a96125f0..71ca95604d63 100644
--- a/arch/arm/mach-s5pv210/mach-aquila.c
+++ b/arch/arm/mach-s5pv210/mach-aquila.c
@@ -22,6 +22,7 @@
 #include <linux/input.h>
 #include <linux/gpio.h>
+#include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/setup.h>
@@ -680,6 +681,7 @@ MACHINE_START(AQUILA, "Aquila")
           Kyungmin Park <kyungmin.park@samsung.com> */
        .atag_offset    = 0x100,
        .init_irq       = s5pv210_init_irq,
+        .handle_irq     = vic_handle_irq,
        .map_io         = aquila_map_io,
        .init_machine   = aquila_machine_init,
        .timer          = &s5p_timer,
diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c
index 15edcae448b9..448fd9ea96f2 100644
--- a/arch/arm/mach-s5pv210/mach-goni.c
+++ b/arch/arm/mach-s5pv210/mach-goni.c
@@ -27,6 +27,7 @@
 #include <linux/gpio.h>
 #include <linux/interrupt.h>
+#include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/setup.h>
@@ -956,6 +957,7 @@ MACHINE_START(GONI, "GONI")
        /* Maintainers: Kyungmin Park <kyungmin.park@samsung.com> */
        .atag_offset    = 0x100,
        .init_irq       = s5pv210_init_irq,
+        .handle_irq     = vic_handle_irq,
        .map_io         = goni_map_io,
        .init_machine   = goni_machine_init,
        .timer          = &s5p_timer,
diff --git a/arch/arm/mach-s5pv210/mach-smdkc110.c b/arch/arm/mach-s5pv210/mach-smdkc110.c
index f7266bb0cac8..c2531ffc720b 100644
--- a/arch/arm/mach-s5pv210/mach-smdkc110.c
+++ b/arch/arm/mach-s5pv210/mach-smdkc110.c
@@ -15,6 +15,7 @@
 #include <linux/i2c.h>
 #include <linux/sysdev.h>
+#include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/setup.h>
@@ -138,6 +139,7 @@ MACHINE_START(SMDKC110, "SMDKC110")
        /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
        .atag_offset    = 0x100,
        .init_irq       = s5pv210_init_irq,
+        .handle_irq     = vic_handle_irq,
        .map_io         = smdkc110_map_io,
        .init_machine   = smdkc110_machine_init,
        .timer          = &s5p_timer,
diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c
index 8662ef6e5681..3ac9e57d9705 100644
--- a/arch/arm/mach-s5pv210/mach-smdkv210.c
+++ b/arch/arm/mach-s5pv210/mach-smdkv210.c
@@ -20,6 +20,7 @@
 #include <linux/delay.h>
 #include <linux/pwm_backlight.h>
+#include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/setup.h>
@@ -316,6 +317,7 @@ MACHINE_START(SMDKV210, "SMDKV210")
        /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
        .atag_offset    = 0x100,
        .init_irq       = s5pv210_init_irq,
+        .handle_irq     = vic_handle_irq,
        .map_io         = smdkv210_map_io,
        .init_machine   = smdkv210_machine_init,
        .timer          = &s5p_timer,
diff --git a/arch/arm/mach-s5pv210/mach-torbreck.c b/arch/arm/mach-s5pv210/mach-torbreck.c
index 97cc066c5369..df70fcb34516 100644
--- a/arch/arm/mach-s5pv210/mach-torbreck.c
+++ b/arch/arm/mach-s5pv210/mach-torbreck.c
@@ -14,6 +14,7 @@
 #include <linux/init.h>
 #include <linux/serial_core.h>
+#include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/setup.h>
@@ -127,6 +128,7 @@ MACHINE_START(TORBRECK, "TORBRECK")
        /* Maintainer: Hyunchul Ko <ghcstop@gmail.com> */
        .atag_offset    = 0x100,
        .init_irq       = s5pv210_init_irq,
+        .handle_irq     = vic_handle_irq,
        .map_io         = torbreck_map_io,
        .init_machine   = torbreck_machine_init,
        .timer          = &s5p_timer,
diff --git a/arch/arm/mach-sa1100/include/mach/system.h b/arch/arm/mach-sa1100/include/mach/system.h
index ba9da9f7f183..345d35b7450c 100644
--- a/arch/arm/mach-sa1100/include/mach/system.h
+++ b/arch/arm/mach-sa1100/include/mach/system.h
@@ -14,7 +14,7 @@ static inline void arch_reset(char mode, const char *cmd)
 {
        if (mode == 's') {
                /* Jump into ROM at address 0 */
-                cpu_reset(0);
+                soft_restart(0);
        } else {
                /* Use on-chip reset capability */
                RSRR = RSRR_SWR;
diff --git a/arch/arm/mach-sa1100/include/mach/vmalloc.h b/arch/arm/mach-sa1100/include/mach/vmalloc.h
deleted file mode 100644
index b3d002398480..000000000000
--- a/arch/arm/mach-sa1100/include/mach/vmalloc.h
+++ /dev/null
@@ -1,4 +0,0 @@
-/*
- * arch/arm/mach-sa1100/include/mach/vmalloc.h
- */
-#define VMALLOC_END       (0xe8000000UL)
diff --git a/arch/arm/mach-shark/core.c b/arch/arm/mach-shark/core.c
index feda3ca7fc95..f4b25d875f3d 100644
--- a/arch/arm/mach-shark/core.c
+++ b/arch/arm/mach-shark/core.c
@@ -29,7 +29,6 @@
 void arch_reset(char mode, const char *cmd)
 {
        short temp;
-        local_irq_disable();
        /* Reset the Machine via pc[3] of the sequoia chipset */
        outw(0x09,0x24);
        temp=inw(0x26);
diff --git a/arch/arm/mach-shark/include/mach/vmalloc.h b/arch/arm/mach-shark/include/mach/vmalloc.h
deleted file mode 100644
index b10df988526d..000000000000
--- a/arch/arm/mach-shark/include/mach/vmalloc.h
+++ /dev/null
@@ -1,4 +0,0 @@
-/*
- * arch/arm/mach-shark/include/mach/vmalloc.h
- */
-#define VMALLOC_END       0xd0000000UL
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index 737bdc631b0d..5ca1f9d66995 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -28,7 +28,6 @@ pfc-$(CONFIG_ARCH_SH73A0)	+= pfc-sh73a0.o
 obj-$(CONFIG_ARCH_SH7367)       += entry-intc.o
 obj-$(CONFIG_ARCH_SH7377)       += entry-intc.o
 obj-$(CONFIG_ARCH_SH7372)       += entry-intc.o
-obj-$(CONFIG_ARCH_SH73A0)       += entry-gic.o
 # PM objects
 obj-$(CONFIG_SUSPEND)           += suspend.o
diff --git a/arch/arm/mach-shmobile/board-ag5evm.c b/arch/arm/mach-shmobile/board-ag5evm.c
index 7119b87cbfa0..f71fa3c13c8c 100644
--- a/arch/arm/mach-shmobile/board-ag5evm.c
+++ b/arch/arm/mach-shmobile/board-ag5evm.c
@@ -609,7 +609,7 @@ MACHINE_START(AG5EVM, "ag5evm")
        .map_io         = ag5evm_map_io,
        .nr_irqs        = NR_IRQS_LEGACY,
        .init_irq       = sh73a0_init_irq,
-        .handle_irq     = shmobile_handle_irq_gic,
+        .handle_irq     = gic_handle_irq,
        .init_machine   = ag5evm_init,
        .timer          = &ag5evm_timer,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-kota2.c b/arch/arm/mach-shmobile/board-kota2.c
index f44150b5ae46..857ceeec1bb0 100644
--- a/arch/arm/mach-shmobile/board-kota2.c
+++ b/arch/arm/mach-shmobile/board-kota2.c
@@ -551,7 +551,7 @@ MACHINE_START(KOTA2, "kota2")
        .map_io         = kota2_map_io,
        .nr_irqs        = NR_IRQS_LEGACY,
        .init_irq       = sh73a0_init_irq,
-        .handle_irq     = shmobile_handle_irq_gic,
+        .handle_irq     = gic_handle_irq,
        .init_machine   = kota2_init,
        .timer          = &kota2_timer,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/entry-gic.S b/arch/arm/mach-shmobile/entry-gic.S
deleted file mode 100644
index e20239b08c83..000000000000
--- a/arch/arm/mach-shmobile/entry-gic.S
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * ARM Interrupt demux handler using GIC
- *
- * Copyright (C) 2010 Magnus Damm
- * Copyright (C) 2011 Paul Mundt
- * Copyright (C) 2010 - 2011 Renesas Solutions Corp.
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <asm/assembler.h>
-#include <asm/entry-macro-multi.S>
-#include <asm/hardware/gic.h>
-#include <asm/hardware/entry-macro-gic.S>
-        arch_irq_handler shmobile_handle_irq_gic
diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h
index 834bd6cd508f..4bf82c156771 100644
--- a/arch/arm/mach-shmobile/include/mach/common.h
+++ b/arch/arm/mach-shmobile/include/mach/common.h
@@ -7,7 +7,6 @@ extern void shmobile_secondary_vector(void);
 struct clk;
 extern int clk_init(void);
 extern void shmobile_handle_irq_intc(struct pt_regs *);
-extern void shmobile_handle_irq_gic(struct pt_regs *);
 extern struct platform_suspend_ops shmobile_suspend_ops;
 struct cpuidle_driver;
 extern void (*shmobile_cpuidle_modes[])(void);
diff --git a/arch/arm/mach-shmobile/include/mach/entry-macro.S b/arch/arm/mach-shmobile/include/mach/entry-macro.S
index 8d4a416d4285..2a57b2964ee9 100644
--- a/arch/arm/mach-shmobile/include/mach/entry-macro.S
+++ b/arch/arm/mach-shmobile/include/mach/entry-macro.S
@@ -18,14 +18,5 @@
        .macro  disable_fiq
        .endm
-        .macro  get_irqnr_preamble, base, tmp
-        .endm
-        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-        .endm
-        .macro  test_for_ipi, irqnr, irqstat, base, tmp
-        .endm
        .macro  arch_ret_to_user, tmp1, tmp2
        .endm
diff --git a/arch/arm/mach-shmobile/include/mach/system.h b/arch/arm/mach-shmobile/include/mach/system.h
index 76a687eeaa22..956ac18ddbf9 100644
--- a/arch/arm/mach-shmobile/include/mach/system.h
+++ b/arch/arm/mach-shmobile/include/mach/system.h
@@ -8,7 +8,7 @@ static inline void arch_idle(void)
 static inline void arch_reset(char mode, const char *cmd)
 {
-        cpu_reset(0);
+        soft_restart(0);
 }
 #endif
diff --git a/arch/arm/mach-shmobile/include/mach/vmalloc.h b/arch/arm/mach-shmobile/include/mach/vmalloc.h
deleted file mode 100644
index 2b8fd8b942fe..000000000000
--- a/arch/arm/mach-shmobile/include/mach/vmalloc.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __ASM_MACH_VMALLOC_H
-#define __ASM_MACH_VMALLOC_H
-/* Vmalloc at ... - 0xe5ffffff */
-#define VMALLOC_END 0xe6000000UL
-#endif /* __ASM_MACH_VMALLOC_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/entry-macro.S b/arch/arm/mach-spear3xx/include/mach/entry-macro.S
index 53da4224ba3d..de3bb41c8e9e 100644
--- a/arch/arm/mach-spear3xx/include/mach/entry-macro.S
+++ b/arch/arm/mach-spear3xx/include/mach/entry-macro.S
@@ -11,35 +11,8 @@
 * warranty of any kind, whether express or implied.
 */
-#include <asm/hardware/vic.h>
-#include <mach/hardware.h>
                .macro  disable_fiq
                .endm
-                .macro  get_irqnr_preamble, base, tmp
-                .endm
                .macro  arch_ret_to_user, tmp1, tmp2
                .endm
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-                ldr     \base, =VA_SPEAR3XX_ML1_VIC_BASE
-                ldr     \irqstat, [\base, #VIC_IRQ_STATUS]      @ get status
-                teq     \irqstat, #0
-                beq     1001f                           @ this will set/reset
-                                                        @ zero register
-                /*
-                 * Following code will find bit position of least significang
-                 * bit set in irqstat, using following equation
-                 * least significant bit set in n = (n & ~(n-1))
-                 */
-                sub     \tmp, \irqstat, #1              @ tmp = irqstat - 1
-                mvn     \tmp, \tmp                      @ tmp = ~tmp
-                and     \irqstat, \irqstat, \tmp        @ irqstat &= tmp
-                /* Now, irqstat is = bit no. of 1st bit set in vic irq status */
-                clz     \tmp, \irqstat                  @ tmp = leading zeros
-                rsb     \irqnr, \tmp, #0x1F             @ irqnr = 32 - tmp - 1
-1001:           /* EQ will be set if no irqs pending */
-                .endm
diff --git a/arch/arm/mach-spear3xx/include/mach/vmalloc.h b/arch/arm/mach-spear3xx/include/mach/vmalloc.h
deleted file mode 100644
index df977b3c9a63..000000000000
--- a/arch/arm/mach-spear3xx/include/mach/vmalloc.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/include/mach/vmalloc.h
- *
- * Defining Vmalloc area for SPEAr3xx machine family
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#ifndef __MACH_VMALLOC_H
-#define __MACH_VMALLOC_H
-#include <plat/vmalloc.h>
-#endif /* __MACH_VMALLOC_H */
diff --git a/arch/arm/mach-spear3xx/spear300_evb.c b/arch/arm/mach-spear3xx/spear300_evb.c
index a5ff98eed1db..61068ba67923 100644
--- a/arch/arm/mach-spear3xx/spear300_evb.c
+++ b/arch/arm/mach-spear3xx/spear300_evb.c
@@ -11,6 +11,7 @@
 * warranty of any kind, whether express or implied.
 */
+#include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 #include <mach/generic.h>
@@ -67,6 +68,7 @@ MACHINE_START(SPEAR300, "ST-SPEAR300-EVB")
        .atag_offset    =       0x100,
        .map_io         =       spear3xx_map_io,
        .init_irq       =       spear3xx_init_irq,
+        .handle_irq     =       vic_handle_irq,
        .timer          =       &spear3xx_timer,
        .init_machine   =       spear300_evb_init,
 MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear310_evb.c b/arch/arm/mach-spear3xx/spear310_evb.c
index 45d180d59362..7903abe92bf6 100644
--- a/arch/arm/mach-spear3xx/spear310_evb.c
+++ b/arch/arm/mach-spear3xx/spear310_evb.c
@@ -11,6 +11,7 @@
 * warranty of any kind, whether express or implied.
 */
+#include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 #include <mach/generic.h>
@@ -73,6 +74,7 @@ MACHINE_START(SPEAR310, "ST-SPEAR310-EVB")
        .atag_offset    =       0x100,
        .map_io         =       spear3xx_map_io,
        .init_irq       =       spear3xx_init_irq,
+        .handle_irq     =       vic_handle_irq,
        .timer          =       &spear3xx_timer,
        .init_machine   =       spear310_evb_init,
 MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear320_evb.c b/arch/arm/mach-spear3xx/spear320_evb.c
index 22879848d73a..e9751f970933 100644
--- a/arch/arm/mach-spear3xx/spear320_evb.c
+++ b/arch/arm/mach-spear3xx/spear320_evb.c
@@ -11,6 +11,7 @@
 * warranty of any kind, whether express or implied.
 */
+#include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 #include <mach/generic.h>
@@ -71,6 +72,7 @@ MACHINE_START(SPEAR320, "ST-SPEAR320-EVB")
        .atag_offset    =       0x100,
        .map_io         =       spear3xx_map_io,
        .init_irq       =       spear3xx_init_irq,
+        .handle_irq     =       vic_handle_irq,
        .timer          =       &spear3xx_timer,
        .init_machine   =       spear320_evb_init,
 MACHINE_END
diff --git a/arch/arm/mach-spear6xx/include/mach/entry-macro.S b/arch/arm/mach-spear6xx/include/mach/entry-macro.S
index 8a0b0ed7b203..d490a910d925 100644
--- a/arch/arm/mach-spear6xx/include/mach/entry-macro.S
+++ b/arch/arm/mach-spear6xx/include/mach/entry-macro.S
@@ -11,44 +11,8 @@
 * warranty of any kind, whether express or implied.
 */
-#include <asm/hardware/vic.h>
-#include <mach/hardware.h>
                .macro  disable_fiq
                .endm
-                .macro  get_irqnr_preamble, base, tmp
-                .endm
                .macro  arch_ret_to_user, tmp1, tmp2
                .endm
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-                ldr     \base, =VA_SPEAR6XX_CPU_VIC_PRI_BASE
-                ldr     \irqstat, [\base, #VIC_IRQ_STATUS]      @ get status
-                mov     \irqnr, #0
-                teq     \irqstat, #0
-                bne     1001f
-                ldr     \base, =VA_SPEAR6XX_CPU_VIC_SEC_BASE
-                ldr     \irqstat, [\base, #VIC_IRQ_STATUS]      @ get status
-                teq     \irqstat, #0
-                beq     1002f                           @ this will set/reset
-                                                        @ zero register
-                mov     \irqnr, #32
-1001:
-                /*
-                 * Following code will find bit position of least significang
-                 * bit set in irqstat, using following equation
-                 * least significant bit set in n = (n & ~(n-1))
-                 */
-                sub     \tmp, \irqstat, #1              @ tmp = irqstat - 1
-                mvn     \tmp, \tmp                      @ tmp = ~tmp
-                and     \irqstat, \irqstat, \tmp        @ irqstat &= tmp
-                /* Now, irqstat is = bit no. of 1st bit set in vic irq status */
-                clz     \tmp, \irqstat                  @ tmp = leading zeros
-                rsb     \tmp, \tmp, #0x1F               @ tmp = 32 - tmp - 1
-                add     \irqnr, \irqnr, \tmp
-1002:           /* EQ will be set if no irqs pending */
-                .endm
diff --git a/arch/arm/mach-spear6xx/include/mach/vmalloc.h b/arch/arm/mach-spear6xx/include/mach/vmalloc.h
deleted file mode 100644
index 4a0b56cb2a91..000000000000
--- a/arch/arm/mach-spear6xx/include/mach/vmalloc.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * arch/arm/mach-spear6xx/include/mach/vmalloc.h
- *
- * Defining Vmalloc area for SPEAr6xx machine family
- *
- * Copyright (C) 2009 ST Microelectronics
- * Rajeev Kumar<rajeev-dlh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#ifndef __MACH_VMALLOC_H
-#define __MACH_VMALLOC_H
-#include <plat/vmalloc.h>
-#endif  /* __MACH_VMALLOC_H */
diff --git a/arch/arm/mach-spear6xx/spear600_evb.c b/arch/arm/mach-spear6xx/spear600_evb.c
index 8238fe38e713..ff139ed0a61e 100644
--- a/arch/arm/mach-spear6xx/spear600_evb.c
+++ b/arch/arm/mach-spear6xx/spear600_evb.c
@@ -11,6 +11,7 @@
 * warranty of any kind, whether express or implied.
 */
+#include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 #include <mach/generic.h>
@@ -46,6 +47,7 @@ MACHINE_START(SPEAR600, "ST-SPEAR600-EVB")
        .atag_offset    =       0x100,
        .map_io         =       spear6xx_map_io,
        .init_irq       =       spear6xx_init_irq,
+        .handle_irq     =       vic_handle_irq,
        .timer          =       &spear6xx_timer,
        .init_machine   =       spear600_evb_init,
 MACHINE_END
diff --git a/arch/arm/mach-tegra/board-dt.c b/arch/arm/mach-tegra/board-dt.c
index 74743ad3d2d3..f6f03ce340fc 100644
--- a/arch/arm/mach-tegra/board-dt.c
+++ b/arch/arm/mach-tegra/board-dt.c
@@ -32,6 +32,7 @@
 #include <linux/i2c.h>
 #include <linux/i2c-tegra.h>
+#include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
@@ -130,6 +131,7 @@ DT_MACHINE_START(TEGRA_DT, "nVidia Tegra (Flattened Device Tree)")
        .map_io         = tegra_map_common_io,
        .init_early     = tegra_init_early,
        .init_irq       = tegra_init_irq,
+        .handle_irq     = gic_handle_irq,
        .timer          = &tegra_timer,
        .init_machine   = tegra_dt_init,
        .dt_compat      = tegra_dt_board_compat,
diff --git a/arch/arm/mach-tegra/board-harmony.c b/arch/arm/mach-tegra/board-harmony.c
index f0bdc5e3fe52..fd190a8dc665 100644
--- a/arch/arm/mach-tegra/board-harmony.c
+++ b/arch/arm/mach-tegra/board-harmony.c
@@ -31,6 +31,7 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
+#include <asm/hardware/gic.h>
 #include <asm/setup.h>
 #include <mach/tegra_wm8903_pdata.h>
@@ -187,6 +188,7 @@ MACHINE_START(HARMONY, "harmony")
        .map_io         = tegra_map_common_io,
        .init_early     = tegra_init_early,
        .init_irq       = tegra_init_irq,
+        .handle_irq     = gic_handle_irq,
        .timer          = &tegra_timer,
        .init_machine   = tegra_harmony_init,
 MACHINE_END
diff --git a/arch/arm/mach-tegra/board-paz00.c b/arch/arm/mach-tegra/board-paz00.c
index 55c55ba89f1e..0b7e1cfee70d 100644
--- a/arch/arm/mach-tegra/board-paz00.c
+++ b/arch/arm/mach-tegra/board-paz00.c
@@ -29,6 +29,7 @@
 #include <linux/gpio.h>
 #include <linux/rfkill-gpio.h>
+#include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
@@ -190,6 +191,7 @@ MACHINE_START(PAZ00, "Toshiba AC100 / Dynabook AZ")
        .map_io         = tegra_map_common_io,
        .init_early     = tegra_init_early,
        .init_irq       = tegra_init_irq,
+        .handle_irq     = gic_handle_irq,
        .timer          = &tegra_timer,
        .init_machine   = tegra_paz00_init,
 MACHINE_END
diff --git a/arch/arm/mach-tegra/board-seaboard.c b/arch/arm/mach-tegra/board-seaboard.c
index bf13ea355efc..7328379b1356 100644
--- a/arch/arm/mach-tegra/board-seaboard.c
+++ b/arch/arm/mach-tegra/board-seaboard.c
@@ -34,6 +34,7 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
+#include <asm/hardware/gic.h>
 #include "board.h"
 #include "board-seaboard.h"
@@ -284,6 +285,7 @@ MACHINE_START(SEABOARD, "seaboard")
        .map_io         = tegra_map_common_io,
        .init_early     = tegra_init_early,
        .init_irq       = tegra_init_irq,
+        .handle_irq     = gic_handle_irq,
        .timer          = &tegra_timer,
        .init_machine   = tegra_seaboard_init,
 MACHINE_END
@@ -293,6 +295,7 @@ MACHINE_START(KAEN, "kaen")
        .map_io         = tegra_map_common_io,
        .init_early     = tegra_init_early,
        .init_irq       = tegra_init_irq,
+        .handle_irq     = gic_handle_irq,
        .timer          = &tegra_timer,
        .init_machine   = tegra_kaen_init,
 MACHINE_END
@@ -302,6 +305,7 @@ MACHINE_START(WARIO, "wario")
        .map_io         = tegra_map_common_io,
        .init_early     = tegra_init_early,
        .init_irq       = tegra_init_irq,
+        .handle_irq     = gic_handle_irq,
        .timer          = &tegra_timer,
        .init_machine   = tegra_wario_init,
 MACHINE_END
diff --git a/arch/arm/mach-tegra/board-trimslice.c b/arch/arm/mach-tegra/board-trimslice.c
index 1a6617b7806f..60a36a2e0be1 100644
--- a/arch/arm/mach-tegra/board-trimslice.c
+++ b/arch/arm/mach-tegra/board-trimslice.c
@@ -26,6 +26,7 @@
 #include <linux/i2c.h>
 #include <linux/gpio.h>
+#include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/setup.h>
@@ -176,6 +177,7 @@ MACHINE_START(TRIMSLICE, "trimslice")
        .map_io         = tegra_map_common_io,
        .init_early     = tegra_init_early,
        .init_irq       = tegra_init_irq,
+        .handle_irq     = gic_handle_irq,
        .timer          = &tegra_timer,
        .init_machine   = tegra_trimslice_init,
 MACHINE_END
diff --git a/arch/arm/mach-tegra/include/mach/entry-macro.S b/arch/arm/mach-tegra/include/mach/entry-macro.S
index dd165c53889d..ac11262149c7 100644
--- a/arch/arm/mach-tegra/include/mach/entry-macro.S
+++ b/arch/arm/mach-tegra/include/mach/entry-macro.S
@@ -12,30 +12,15 @@
 * GNU General Public License for more details.
 *
 */
-#include <mach/iomap.h>
-#include <mach/io.h>
-#if defined(CONFIG_ARM_GIC)
-#define HAVE_GET_IRQNR_PREAMBLE
-#include <asm/hardware/entry-macro-gic.S>
-        /* Uses the GIC interrupt controller built into the cpu */
-#define ICTRL_BASE (IO_CPU_VIRT + 0x100)
        .macro  disable_fiq
        .endm
-        .macro  get_irqnr_preamble, base, tmp
+        .macro  arch_ret_to_user, tmp1, tmp2
-        movw \base, #(ICTRL_BASE & 0x0000ffff)
-        movt \base, #((ICTRL_BASE & 0xffff0000) >> 16)
        .endm
-        .macro  arch_ret_to_user, tmp1, tmp2
+#if !defined(CONFIG_ARM_GIC)
-        .endm
-#else
        /* legacy interrupt controller for AP16 */
-        .macro  disable_fiq
-        .endm
        .macro  get_irqnr_preamble, base, tmp
        @ enable imprecise aborts
@@ -46,9 +31,6 @@
        orr \base, #0x0000f000
        .endm
-        .macro  arch_ret_to_user, tmp1, tmp2
-        .endm
        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
        ldr \irqnr, [\base, #0x20]      @ EVT_IRQ_STS
        cmp \irqnr, #0x80
diff --git a/arch/arm/mach-tegra/include/mach/io.h b/arch/arm/mach-tegra/include/mach/io.h
index 35a011fbc42d..f15defffb5d2 100644
--- a/arch/arm/mach-tegra/include/mach/io.h
+++ b/arch/arm/mach-tegra/include/mach/io.h
@@ -71,12 +71,6 @@
 #ifndef __ASSEMBLER__
-#define __arch_ioremap          tegra_ioremap
-#define __arch_iounmap          tegra_iounmap
-void __iomem *tegra_ioremap(unsigned long phys, size_t size, unsigned int type);
-void tegra_iounmap(volatile void __iomem *addr);
 #define IO_ADDRESS(n) (IO_TO_VIRT(n))
 #ifdef CONFIG_TEGRA_PCI
diff --git a/arch/arm/mach-tegra/include/mach/vmalloc.h b/arch/arm/mach-tegra/include/mach/vmalloc.h
deleted file mode 100644
index fd6aa65b2dc6..000000000000
--- a/arch/arm/mach-tegra/include/mach/vmalloc.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * arch/arm/mach-tegra/include/mach/vmalloc.h
- *
- * Copyright (C) 2010 Google, Inc.
- *
- * Author:
- *      Colin Cross <ccross@google.com>
- *      Erik Gilling <konkers@google.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#ifndef __MACH_TEGRA_VMALLOC_H
-#define __MACH_TEGRA_VMALLOC_H
-#include <asm/sizes.h>
-#define VMALLOC_END        0xFE000000UL
-#endif
diff --git a/arch/arm/mach-tegra/io.c b/arch/arm/mach-tegra/io.c
index 5489f8b5d6ad..d23ee2db2827 100644
--- a/arch/arm/mach-tegra/io.c
+++ b/arch/arm/mach-tegra/io.c
@@ -60,24 +60,3 @@ void __init tegra_map_common_io(void)
 {
        iotable_init(tegra_io_desc, ARRAY_SIZE(tegra_io_desc));
 }
-/*
- * Intercept ioremap() requests for addresses in our fixed mapping regions.
- */
-void __iomem *tegra_ioremap(unsigned long p, size_t size, unsigned int type)
-{
-        void __iomem *v = IO_ADDRESS(p);
-        if (v == NULL)
-                v = __arm_ioremap(p, size, type);
-        return v;
-}
-EXPORT_SYMBOL(tegra_ioremap);
-void tegra_iounmap(volatile void __iomem *addr)
-{
-        unsigned long virt = (unsigned long)addr;
-        if (virt >= VMALLOC_START && virt < VMALLOC_END)
-                __iounmap(addr);
-}
-EXPORT_SYMBOL(tegra_iounmap);
diff --git a/arch/arm/mach-u300/include/mach/entry-macro.S b/arch/arm/mach-u300/include/mach/entry-macro.S
index 20731ae39d38..7181d6ac6651 100644
--- a/arch/arm/mach-u300/include/mach/entry-macro.S
+++ b/arch/arm/mach-u300/include/mach/entry-macro.S
@@ -8,33 +8,9 @@
 * Low-level IRQ helper macros for ST-Ericsson U300
 * Author: Linus Walleij <linus.walleij@stericsson.com>
 */
-#include <mach/hardware.h>
-#include <asm/hardware/vic.h>
        .macro  disable_fiq
        .endm
-        .macro  get_irqnr_preamble, base, tmp
-        .endm
        .macro  arch_ret_to_user, tmp1, tmp2
        .endm
-        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-        ldr     \base, = U300_AHB_PER_VIRT_BASE-U300_AHB_PER_PHYS_BASE+U300_INTCON0_BASE
-        ldr     \irqstat, [\base, #VIC_IRQ_STATUS] @ get masked status
-        mov     \irqnr, #0
-        teq     \irqstat, #0
-        bne     1002f
-1001:   ldr     \base, = U300_AHB_PER_VIRT_BASE-U300_AHB_PER_PHYS_BASE+U300_INTCON1_BASE
-        ldr     \irqstat, [\base, #VIC_IRQ_STATUS] @ get masked status
-        mov     \irqnr, #32
-        teq     \irqstat, #0
-        beq     1003f
-1002:   tst     \irqstat, #1
-        bne     1003f
-        add     \irqnr, \irqnr, #1
-        movs    \irqstat, \irqstat, lsr #1
-        bne     1002b
-1003:           /* EQ will be set if no irqs pending */
-        .endm
diff --git a/arch/arm/mach-u300/include/mach/system.h b/arch/arm/mach-u300/include/mach/system.h
index 8daf13634ce0..6b6fef7a438c 100644
--- a/arch/arm/mach-u300/include/mach/system.h
+++ b/arch/arm/mach-u300/include/mach/system.h
@@ -27,8 +27,6 @@ static void arch_reset(char mode, const char *cmd)
        case 's':
        case 'h':
                printk(KERN_CRIT "RESET: shutting down/rebooting system\n");
-                /* Disable interrupts */
-                local_irq_disable();
 #ifdef CONFIG_COH901327_WATCHDOG
                coh901327_watchdog_reset();
 #endif
diff --git a/arch/arm/mach-u300/include/mach/vmalloc.h b/arch/arm/mach-u300/include/mach/vmalloc.h
deleted file mode 100644
index ec423b92b81d..000000000000
--- a/arch/arm/mach-u300/include/mach/vmalloc.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/*
- *
- * arch/arm/mach-u300/include/mach/vmalloc.h
- *
- *
- * Copyright (C) 2006-2009 ST-Ericsson AB
- * License terms: GNU General Public License (GPL) version 2
- * Virtual memory allocations
- * End must be above the I/O registers and on an even 2MiB boundary.
- * Author: Linus Walleij <linus.walleij@stericsson.com>
- */
-#define VMALLOC_END     0xfe800000UL
diff --git a/arch/arm/mach-u300/u300.c b/arch/arm/mach-u300/u300.c
index 89422ee7f3a8..4a4fd334eb6e 100644
--- a/arch/arm/mach-u300/u300.c
+++ b/arch/arm/mach-u300/u300.c
@@ -19,6 +19,7 @@
 #include <linux/io.h>
 #include <mach/hardware.h>
 #include <mach/platform.h>
+#include <asm/hardware/vic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/memory.h>
@@ -49,6 +50,7 @@ MACHINE_START(U300, MACH_U300_STRING)
        .atag_offset    = BOOT_PARAMS_OFFSET,
        .map_io         = u300_map_io,
        .init_irq       = u300_init_irq,
+        .handle_irq     = vic_handle_irq,
        .timer          = &u300_timer,
        .init_machine   = u300_init_machine,
 MACHINE_END
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index bdd7b80dd7ad..de1f5f8f7330 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -33,6 +33,7 @@
 #include <linux/leds.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
+#include <asm/hardware/gic.h>
 #include <plat/i2c.h>
 #include <plat/ste_dma40.h>
@@ -695,6 +696,7 @@ MACHINE_START(U8500, "ST-Ericsson MOP500 platform")
        .init_irq       = ux500_init_irq,
        /* we re-use nomadik timer here */
        .timer          = &ux500_timer,
+        .handle_irq     = gic_handle_irq,
        .init_machine   = mop500_init_machine,
 MACHINE_END
@@ -703,6 +705,7 @@ MACHINE_START(HREFV60, "ST-Ericsson U8500 Platform HREFv60+")
        .map_io         = u8500_map_io,
        .init_irq       = ux500_init_irq,
        .timer          = &ux500_timer,
+        .handle_irq     = gic_handle_irq,
        .init_machine   = hrefv60_init_machine,
 MACHINE_END
@@ -712,5 +715,6 @@ MACHINE_START(SNOWBALL, "Calao Systems Snowball platform")
        .init_irq       = ux500_init_irq,
        /* we re-use nomadik timer here */
        .timer          = &ux500_timer,
+        .handle_irq     = gic_handle_irq,
        .init_machine   = snowball_init_machine,
 MACHINE_END
diff --git a/arch/arm/mach-ux500/board-u5500.c b/arch/arm/mach-ux500/board-u5500.c
index 82025ba70c03..fe1569b67c91 100644
--- a/arch/arm/mach-ux500/board-u5500.c
+++ b/arch/arm/mach-ux500/board-u5500.c
@@ -12,6 +12,7 @@
 #include <linux/i2c.h>
 #include <linux/mfd/ab5500/ab5500.h>
+#include <asm/hardware/gic.h>
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
@@ -149,5 +150,6 @@ MACHINE_START(U5500, "ST-Ericsson U5500 Platform")
        .map_io         = u5500_map_io,
        .init_irq       = ux500_init_irq,
        .timer          = &ux500_timer,
+        .handle_irq     = gic_handle_irq,
        .init_machine   = u5500_init_machine,
 MACHINE_END
diff --git a/arch/arm/mach-ux500/include/mach/entry-macro.S b/arch/arm/mach-ux500/include/mach/entry-macro.S
index 071bba94f727..e16299e1020a 100644
--- a/arch/arm/mach-ux500/include/mach/entry-macro.S
+++ b/arch/arm/mach-ux500/include/mach/entry-macro.S
@@ -10,8 +10,6 @@
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */
-#include <mach/hardware.h>
-#include <asm/hardware/entry-macro-gic.S>
                .macro  disable_fiq
                .endm
diff --git a/arch/arm/mach-ux500/include/mach/vmalloc.h b/arch/arm/mach-ux500/include/mach/vmalloc.h
deleted file mode 100644
index a4945cb41172..000000000000
--- a/arch/arm/mach-ux500/include/mach/vmalloc.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- *  Copyright (C) 2009 ST-Ericsson
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#define VMALLOC_END     0xf0000000UL
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index e340a54251df..4d8dfc15f3e6 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -141,11 +141,6 @@ static struct map_desc versatile_io_desc[] __initdata = {
        },
 #ifdef CONFIG_MACH_VERSATILE_AB
        {
-                .virtual        =  IO_ADDRESS(VERSATILE_GPIO0_BASE),
-                .pfn            = __phys_to_pfn(VERSATILE_GPIO0_BASE),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE
-        }, {
                .virtual        =  IO_ADDRESS(VERSATILE_IB2_BASE),
                .pfn            = __phys_to_pfn(VERSATILE_IB2_BASE),
                .length         = SZ_64M,
diff --git a/arch/arm/mach-versatile/include/mach/entry-macro.S b/arch/arm/mach-versatile/include/mach/entry-macro.S
index e6f7c1663160..b6f0dbf122ee 100644
--- a/arch/arm/mach-versatile/include/mach/entry-macro.S
+++ b/arch/arm/mach-versatile/include/mach/entry-macro.S
@@ -7,39 +7,9 @@
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */
-#include <mach/hardware.h>
-#include <mach/platform.h>
-#include <asm/hardware/vic.h>
                .macro  disable_fiq
                .endm
-                .macro  get_irqnr_preamble, base, tmp
-                ldr     \base, =IO_ADDRESS(VERSATILE_VIC_BASE)
-                .endm
                .macro  arch_ret_to_user, tmp1, tmp2
                .endm
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-                ldr     \irqstat, [\base, #VIC_IRQ_STATUS]      @ get masked status
-                mov     \irqnr, #0
-                teq     \irqstat, #0
-                beq     1003f
-1001:           tst     \irqstat, #15
-                bne     1002f
-                add     \irqnr, \irqnr, #4
-                movs    \irqstat, \irqstat, lsr #4
-                bne     1001b
-1002:           tst     \irqstat, #1
-                bne     1003f
-                add     \irqnr, \irqnr, #1
-                movs    \irqstat, \irqstat, lsr #1
-                bne     1002b
-1003:           /* EQ will be set if no irqs pending */
-@               clz     \irqnr, \irqstat
-@1003:          /* EQ will be set if we reach MAXIRQNUM */
-                .endm
diff --git a/arch/arm/mach-versatile/include/mach/vmalloc.h b/arch/arm/mach-versatile/include/mach/vmalloc.h
deleted file mode 100644
index 7d8e069ad51b..000000000000
--- a/arch/arm/mach-versatile/include/mach/vmalloc.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- *  arch/arm/mach-versatile/include/mach/vmalloc.h
- *
- *  Copyright (C) 2003 ARM Limited
- *  Copyright (C) 2000 Russell King.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#define VMALLOC_END             0xd8000000UL
diff --git a/arch/arm/mach-versatile/versatile_ab.c b/arch/arm/mach-versatile/versatile_ab.c
index fda4866703cd..c83a1f379f7a 100644
--- a/arch/arm/mach-versatile/versatile_ab.c
+++ b/arch/arm/mach-versatile/versatile_ab.c
@@ -27,6 +27,7 @@
 #include <mach/hardware.h>
 #include <asm/irq.h>
+#include <asm/hardware/vic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -39,6 +40,7 @@ MACHINE_START(VERSATILE_AB, "ARM-Versatile AB")
        .map_io         = versatile_map_io,
        .init_early     = versatile_init_early,
        .init_irq       = versatile_init_irq,
+        .handle_irq     = vic_handle_irq,
        .timer          = &versatile_timer,
        .init_machine   = versatile_init,
 MACHINE_END
diff --git a/arch/arm/mach-versatile/versatile_dt.c b/arch/arm/mach-versatile/versatile_dt.c
index 54e037c090f5..f4d1e0f072c8 100644
--- a/arch/arm/mach-versatile/versatile_dt.c
+++ b/arch/arm/mach-versatile/versatile_dt.c
@@ -24,6 +24,7 @@
 #include <linux/init.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
+#include <asm/hardware/vic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -45,6 +46,7 @@ DT_MACHINE_START(VERSATILE_PB, "ARM-Versatile (Device Tree Support)")
        .map_io         = versatile_map_io,
        .init_early     = versatile_init_early,
        .init_irq       = versatile_init_irq,
+        .handle_irq     = vic_handle_irq,
        .timer          = &versatile_timer,
        .init_machine   = versatile_dt_init,
        .dt_compat      = versatile_dt_match,
diff --git a/arch/arm/mach-versatile/versatile_pb.c b/arch/arm/mach-versatile/versatile_pb.c
index feaf9cbe60f6..4d31eeb6c101 100644
--- a/arch/arm/mach-versatile/versatile_pb.c
+++ b/arch/arm/mach-versatile/versatile_pb.c
@@ -28,6 +28,7 @@
 #include <linux/io.h>
 #include <mach/hardware.h>
+#include <asm/hardware/vic.h>
 #include <asm/irq.h>
 #include <asm/mach-types.h>
@@ -107,6 +108,7 @@ MACHINE_START(VERSATILE_PB, "ARM-Versatile PB")
        .map_io         = versatile_map_io,
        .init_early     = versatile_init_early,
        .init_irq       = versatile_init_irq,
+        .handle_irq     = vic_handle_irq,
        .timer          = &versatile_timer,
        .init_machine   = versatile_pb_init,
 MACHINE_END
diff --git a/arch/arm/mach-vexpress/include/mach/entry-macro.S b/arch/arm/mach-vexpress/include/mach/entry-macro.S
index 73c11297509e..a14f9e62ca92 100644
--- a/arch/arm/mach-vexpress/include/mach/entry-macro.S
+++ b/arch/arm/mach-vexpress/include/mach/entry-macro.S
@@ -1,5 +1,3 @@
-#include <asm/hardware/entry-macro-gic.S>
        .macro  disable_fiq
        .endm
diff --git a/arch/arm/mach-vexpress/include/mach/vmalloc.h b/arch/arm/mach-vexpress/include/mach/vmalloc.h
deleted file mode 100644
index f43a36ef678b..000000000000
--- a/arch/arm/mach-vexpress/include/mach/vmalloc.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- *  arch/arm/mach-vexpress/include/mach/vmalloc.h
- *
- *  Copyright (C) 2003 ARM Limited
- *  Copyright (C) 2000 Russell King.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#define VMALLOC_END             0xf8000000UL
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
index 1fafc3244607..7aa07a8ce232 100644
--- a/arch/arm/mach-vexpress/v2m.c
+++ b/arch/arm/mach-vexpress/v2m.c
@@ -23,6 +23,7 @@
 #include <asm/hardware/arm_timer.h>
 #include <asm/hardware/timer-sp.h>
 #include <asm/hardware/sp810.h>
+#include <asm/hardware/gic.h>
 #include <mach/ct-ca9x4.h>
 #include <mach/motherboard.h>
@@ -448,5 +449,6 @@ MACHINE_START(VEXPRESS, "ARM-Versatile Express")
        .init_early     = v2m_init_early,
        .init_irq       = v2m_init_irq,
        .timer          = &v2m_timer,
+        .handle_irq     = gic_handle_irq,
        .init_machine   = v2m_init,
 MACHINE_END
diff --git a/arch/arm/mach-vt8500/include/mach/vmalloc.h b/arch/arm/mach-vt8500/include/mach/vmalloc.h
deleted file mode 100644
index 4642290ce416..000000000000
--- a/arch/arm/mach-vt8500/include/mach/vmalloc.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- *  arch/arm/mach-vt8500/include/mach/vmalloc.h
- *
- *  Copyright (C) 2000 Russell King.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#define VMALLOC_END     0xd0000000UL
diff --git a/arch/arm/mach-w90x900/include/mach/system.h b/arch/arm/mach-w90x900/include/mach/system.h
index ce228bdc66dd..68875a1c16be 100644
--- a/arch/arm/mach-w90x900/include/mach/system.h
+++ b/arch/arm/mach-w90x900/include/mach/system.h
@@ -33,7 +33,7 @@ static void arch_reset(char mode, const char *cmd)
 {
        if (mode == 's') {
                /* Jump into ROM at address 0 */
-                cpu_reset(0);
+                soft_restart(0);
        } else {
                __raw_writel(WTE | WTRE | WTCLK, WTCR);
        }
diff --git a/arch/arm/mach-w90x900/include/mach/vmalloc.h b/arch/arm/mach-w90x900/include/mach/vmalloc.h
deleted file mode 100644
index b067e44500a4..000000000000
--- a/arch/arm/mach-w90x900/include/mach/vmalloc.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * arch/arm/mach-w90x900/include/mach/vmalloc.h
- *
- * Copyright (c) 2008 Nuvoton technology corporation
- * All rights reserved.
- *
- * Wan ZongShun <mcuos.com@gmail.com>
- *
- * Based on arch/arm/mach-s3c2410/include/mach/vmalloc.h
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- */
-#ifndef __ASM_ARCH_VMALLOC_H
-#define __ASM_ARCH_VMALLOC_H
-#define VMALLOC_END       (0xe0000000UL)
-#endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/mach-w90x900/irq.c b/arch/arm/mach-w90x900/irq.c
index 7bf143c443f1..b466e2450ba3 100644
--- a/arch/arm/mach-w90x900/irq.c
+++ b/arch/arm/mach-w90x900/irq.c
@@ -28,6 +28,8 @@
 #include <mach/hardware.h>
 #include <mach/regs-irq.h>
+#include "nuc9xx.h"
 struct group_irq {
        unsigned long           gpen;
        unsigned int            enabled;
diff --git a/arch/arm/mach-w90x900/nuc910.h b/arch/arm/mach-w90x900/nuc910.h
index 83e9ba5fc26c..b14c71a9e683 100644
--- a/arch/arm/mach-w90x900/nuc910.h
+++ b/arch/arm/mach-w90x900/nuc910.h
@@ -12,14 +12,7 @@
 * published by the Free Software Foundation.
 *
 */
+#include "nuc9xx.h"
-struct map_desc;
-struct sys_timer;
-/* core initialisation functions */
-extern void nuc900_init_irq(void);
-extern struct sys_timer nuc900_timer;
 /* extern file from nuc910.c */
diff --git a/arch/arm/mach-w90x900/nuc950.h b/arch/arm/mach-w90x900/nuc950.h
index 98a1148bc5ae..6e9de3051cd4 100644
--- a/arch/arm/mach-w90x900/nuc950.h
+++ b/arch/arm/mach-w90x900/nuc950.h
@@ -12,14 +12,7 @@
 * published by the Free Software Foundation.
 *
 */
+#include "nuc9xx.h"
-struct map_desc;
-struct sys_timer;
-/* core initialisation functions */
-extern void nuc900_init_irq(void);
-extern struct sys_timer nuc900_timer;
 /* extern file from nuc950.c */
diff --git a/arch/arm/mach-w90x900/nuc960.h b/arch/arm/mach-w90x900/nuc960.h
index f0c07cbe3a82..9f6df9a00286 100644
--- a/arch/arm/mach-w90x900/nuc960.h
+++ b/arch/arm/mach-w90x900/nuc960.h
@@ -12,14 +12,7 @@
 * published by the Free Software Foundation.
 *
 */
+#include "nuc9xx.h"
-struct map_desc;
-struct sys_timer;
-/* core initialisation functions */
-extern void nuc900_init_irq(void);
-extern struct sys_timer nuc900_timer;
 /* extern file from nuc960.c */
diff --git a/arch/arm/mach-w90x900/nuc9xx.h b/arch/arm/mach-w90x900/nuc9xx.h
new file mode 100644
index 000000000000..847c4f3e0440
--- /dev/null
+++ b/arch/arm/mach-w90x900/nuc9xx.h
@@ -0,0 +1,23 @@
+/*
+ * arch/arm/mach-w90x900/nuc9xx.h
+ *
+ * Copied from nuc910.h, which had:
+ *
+ * Copyright (c) 2008 Nuvoton corporation
+ *
+ * Header file for NUC900 CPU support
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+struct map_desc;
+struct sys_timer;
+/* core initialisation functions */
+extern void nuc900_init_irq(void);
+extern struct sys_timer nuc900_timer;
diff --git a/arch/arm/mach-w90x900/time.c b/arch/arm/mach-w90x900/time.c
index a2c4e2d0a0d4..fa27c498ac09 100644
--- a/arch/arm/mach-w90x900/time.c
+++ b/arch/arm/mach-w90x900/time.c
@@ -33,6 +33,8 @@
 #include <mach/map.h>
 #include <mach/regs-timer.h>
+#include "nuc9xx.h"
 #define RESETINT        0x1f
 #define PERIOD          (0x01 << 27)
 #define ONESHOT         (0x00 << 27)
diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c
index 73e93687b81a..ab5cfddc0d7b 100644
--- a/arch/arm/mach-zynq/common.c
+++ b/arch/arm/mach-zynq/common.c
@@ -112,6 +112,7 @@ static const char *xilinx_dt_match[] = {
 MACHINE_START(XILINX_EP107, "Xilinx Zynq Platform")
        .map_io         = xilinx_map_io,
        .init_irq       = xilinx_irq_init,
+        .handle_irq     = gic_handle_irq,
        .init_machine   = xilinx_init_machine,
        .timer          = &xttcpss_sys_timer,
        .dt_compat      = xilinx_dt_match,
diff --git a/arch/arm/mach-zynq/include/mach/entry-macro.S b/arch/arm/mach-zynq/include/mach/entry-macro.S
index 3cfc01b37461..d621fb732569 100644
--- a/arch/arm/mach-zynq/include/mach/entry-macro.S
+++ b/arch/arm/mach-zynq/include/mach/entry-macro.S
@@ -20,9 +20,6 @@
 * GNU General Public License for more details.
 */
-#include <mach/hardware.h>
-#include <asm/hardware/entry-macro-gic.S>
                .macro  disable_fiq
                .endm
diff --git a/arch/arm/mach-zynq/include/mach/vmalloc.h b/arch/arm/mach-zynq/include/mach/vmalloc.h
deleted file mode 100644
index 2398eff1e8b8..000000000000
--- a/arch/arm/mach-zynq/include/mach/vmalloc.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* arch/arm/mach-zynq/include/mach/vmalloc.h
- *
- *  Copyright (C) 2011 Xilinx
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#ifndef __MACH_VMALLOC_H__
-#define __MACH_VMALLOC_H__
-#define VMALLOC_END       0xE0000000UL
-#endif
diff --git a/arch/arm/mm/idmap.c b/arch/arm/mm/idmap.c
index 2be9139a4ef3..296ad2eaddb0 100644
--- a/arch/arm/mm/idmap.c
+++ b/arch/arm/mm/idmap.c
@@ -78,7 +78,7 @@ void identity_mapping_del(pgd_t *pgd, unsigned long addr, unsigned long end)
 * the user-mode pages.  This will then ensure that we have predictable
 * results when turning the mmu off
 */
-void setup_mm_for_reboot(char mode)
+void setup_mm_for_reboot(void)
 {
        /*
         * We need to access to user-mode page tables here. For kernel threads
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index fbdd12ea3a58..786adddf1a86 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -20,7 +20,6 @@
 #include <linux/highmem.h>
 #include <linux/gfp.h>
 #include <linux/memblock.h>
-#include <linux/sort.h>
 #include <asm/mach-types.h>
 #include <asm/prom.h>
@@ -134,30 +133,18 @@ void show_mem(unsigned int filter)
 }
 static void __init find_limits(unsigned long *min, unsigned long *max_low,
-        unsigned long *max_high)
+                               unsigned long *max_high)
 {
        struct meminfo *mi = &meminfo;
        int i;
-        *min = -1UL;
+        /* This assumes the meminfo array is properly sorted */
-        *max_low = *max_high = 0;
+        *min = bank_pfn_start(&mi->bank[0]);
+        for_each_bank (i, mi)
-        for_each_bank (i, mi) {
+                if (mi->bank[i].highmem)
-                struct membank *bank = &mi->bank[i];
+                                break;
-                unsigned long start, end;
+        *max_low = bank_pfn_end(&mi->bank[i - 1]);
+        *max_high = bank_pfn_end(&mi->bank[mi->nr_banks - 1]);
-                start = bank_pfn_start(bank);
-                end = bank_pfn_end(bank);
-                if (*min > start)
-                        *min = start;
-                if (*max_high < end)
-                        *max_high = end;
-                if (bank->highmem)
-                        continue;
-                if (*max_low < end)
-                        *max_low = end;
-        }
 }
 static void __init arm_bootmem_init(unsigned long start_pfn,
@@ -319,19 +306,10 @@ static void arm_memory_present(void)
 }
 #endif
-static int __init meminfo_cmp(const void *_a, const void *_b)
-{
-        const struct membank *a = _a, *b = _b;
-        long cmp = bank_pfn_start(a) - bank_pfn_start(b);
-        return cmp < 0 ? -1 : cmp > 0 ? 1 : 0;
-}
 void __init arm_memblock_init(struct meminfo *mi, struct machine_desc *mdesc)
 {
        int i;
-        sort(&meminfo.bank, meminfo.nr_banks, sizeof(meminfo.bank[0]), meminfo_cmp, NULL);
        memblock_init();
        for (i = 0; i < mi->nr_banks; i++)
                memblock_add(mi->bank[i].start, mi->bank[i].size);
@@ -403,8 +381,6 @@ void __init bootmem_init(void)
         */
        arm_bootmem_free(min, max_low, max_high);
-        high_memory = __va(((phys_addr_t)max_low << PAGE_SHIFT) - 1) + 1;
        /*
         * This doesn't seem to be used by the Linux memory manager any
         * more, but is used by ll_rw_block.  If we can get rid of it, we
diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c
index bdb248c4f55c..12c7ad215ce7 100644
--- a/arch/arm/mm/ioremap.c
+++ b/arch/arm/mm/ioremap.c
@@ -36,12 +36,6 @@
 #include <asm/mach/map.h>
 #include "mm.h"
-/*
- * Used by ioremap() and iounmap() code to mark (super)section-mapped
- * I/O regions in vm_struct->flags field.
- */
-#define VM_ARM_SECTION_MAPPING  0x80000000
 int ioremap_page(unsigned long virt, unsigned long phys,
                 const struct mem_type *mtype)
 {
@@ -201,12 +195,6 @@ void __iomem * __arm_ioremap_pfn_caller(unsigned long pfn,
        if (pfn >= 0x100000 && (__pfn_to_phys(pfn) & ~SUPERSECTION_MASK))
                return NULL;
-        /*
-         * Don't allow RAM to be mapped - this causes problems with ARMv6+
-         */
-        if (WARN_ON(pfn_valid(pfn)))
-                return NULL;
        type = get_mem_type(mtype);
        if (!type)
                return NULL;
@@ -216,6 +204,34 @@ void __iomem * __arm_ioremap_pfn_caller(unsigned long pfn,
         */
        size = PAGE_ALIGN(offset + size);
+        /*
+         * Try to reuse one of the static mapping whenever possible.
+         */
+        read_lock(&vmlist_lock);
+        for (area = vmlist; area; area = area->next) {
+                if (!size || (sizeof(phys_addr_t) == 4 && pfn >= 0x100000))
+                        break;
+                if (!(area->flags & VM_ARM_STATIC_MAPPING))
+                        continue;
+                if ((area->flags & VM_ARM_MTYPE_MASK) != VM_ARM_MTYPE(mtype))
+                        continue;
+                if (__phys_to_pfn(area->phys_addr) > pfn ||
+                    __pfn_to_phys(pfn) + size-1 > area->phys_addr + area->size-1)
+                        continue;
+                /* we can drop the lock here as we know *area is static */
+                read_unlock(&vmlist_lock);
+                addr = (unsigned long)area->addr;
+                addr += __pfn_to_phys(pfn) - area->phys_addr;
+                return (void __iomem *) (offset + addr);
+        }
+        read_unlock(&vmlist_lock);
+        /*
+         * Don't allow RAM to be mapped - this causes problems with ARMv6+
+         */
+        if (WARN_ON(pfn_valid(pfn)))
+                return NULL;
        area = get_vm_area_caller(size, VM_IOREMAP, caller);
        if (!area)
                return NULL;
@@ -313,28 +329,34 @@ __arm_ioremap_exec(unsigned long phys_addr, size_t size, bool cached)
 void __iounmap(volatile void __iomem *io_addr)
 {
        void *addr = (void *)(PAGE_MASK & (unsigned long)io_addr);
-#ifndef CONFIG_SMP
+        struct vm_struct *vm;
-        struct vm_struct **p, *tmp;
-        /*
+        read_lock(&vmlist_lock);
-         * If this is a section based mapping we need to handle it
+        for (vm = vmlist; vm; vm = vm->next) {
-         * specially as the VM subsystem does not know how to handle
+                if (vm->addr > addr)
-         * such a beast. We need the lock here b/c we need to clear
+                        break;
-         * all the mappings before the area can be reclaimed
+                if (!(vm->flags & VM_IOREMAP))
-         * by someone else.
+                        continue;
-         */
+                /* If this is a static mapping we must leave it alone */
-        write_lock(&vmlist_lock);
+                if ((vm->flags & VM_ARM_STATIC_MAPPING) &&
-        for (p = &vmlist ; (tmp = *p) ; p = &tmp->next) {
+                    (vm->addr <= addr) && (vm->addr + vm->size > addr)) {
-                if ((tmp->flags & VM_IOREMAP) && (tmp->addr == addr)) {
+                        read_unlock(&vmlist_lock);
-                        if (tmp->flags & VM_ARM_SECTION_MAPPING) {
+                        return;
-                                unmap_area_sections((unsigned long)tmp->addr,
+                }
-                                                    tmp->size);
+#ifndef CONFIG_SMP
-                        }
+                /*
+                 * If this is a section based mapping we need to handle it
+                 * specially as the VM subsystem does not know how to handle
+                 * such a beast.
+                 */
+                if ((vm->addr == addr) &&
+                    (vm->flags & VM_ARM_SECTION_MAPPING)) {
+                        unmap_area_sections((unsigned long)vm->addr, vm->size);
                        break;
                }
-        }
-        write_unlock(&vmlist_lock);
 #endif
+        }
+        read_unlock(&vmlist_lock);
        vunmap(addr);
 }
diff --git a/arch/arm/mm/mm.h b/arch/arm/mm/mm.h
index ad7cce3bc431..70f6d3ea4834 100644
--- a/arch/arm/mm/mm.h
+++ b/arch/arm/mm/mm.h
@@ -21,6 +21,20 @@ const struct mem_type *get_mem_type(unsigned int type);
 extern void __flush_dcache_page(struct address_space *mapping, struct page *page);
+/*
+ * ARM specific vm_struct->flags bits.
+ */
+/* (super)section-mapped I/O regions used by ioremap()/iounmap() */
+#define VM_ARM_SECTION_MAPPING  0x80000000
+/* permanent static mappings from iotable_init() */
+#define VM_ARM_STATIC_MAPPING   0x40000000
+/* mapping type (attributes) for permanent static mappings */
+#define VM_ARM_MTYPE(mt)                ((mt) << 20)
+#define VM_ARM_MTYPE_MASK       (0x1f << 20)
 #endif
 #ifdef CONFIG_ZONE_DMA
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index dc8c550e6cbd..27e366af67f9 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -15,6 +15,7 @@
 #include <linux/nodemask.h>
 #include <linux/memblock.h>
 #include <linux/fs.h>
+#include <linux/vmalloc.h>
 #include <asm/cputype.h>
 #include <asm/sections.h>
@@ -529,13 +530,18 @@ EXPORT_SYMBOL(phys_mem_access_prot);
 #define vectors_base()  (vectors_high() ? 0xffff0000 : 0)
-static void __init *early_alloc(unsigned long sz)
+static void __init *early_alloc_aligned(unsigned long sz, unsigned long align)
 {
-        void *ptr = __va(memblock_alloc(sz, sz));
+        void *ptr = __va(memblock_alloc(sz, align));
        memset(ptr, 0, sz);
        return ptr;
 }
+static void __init *early_alloc(unsigned long sz)
+{
+        return early_alloc_aligned(sz, sz);
+}
 static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr, unsigned long prot)
 {
        if (pmd_none(*pmd)) {
@@ -685,9 +691,10 @@ static void __init create_mapping(struct map_desc *md)
        }
        if ((md->type == MT_DEVICE || md->type == MT_ROM) &&
-            md->virtual >= PAGE_OFFSET && md->virtual < VMALLOC_END) {
+            md->virtual >= PAGE_OFFSET &&
+            (md->virtual < VMALLOC_START || md->virtual >= VMALLOC_END)) {
                printk(KERN_WARNING "BUG: mapping for 0x%08llx"
-                       " at 0x%08lx overlaps vmalloc space\n",
+                       " at 0x%08lx out of vmalloc space\n",
                       (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
        }
@@ -729,18 +736,33 @@ static void __init create_mapping(struct map_desc *md)
 */
 void __init iotable_init(struct map_desc *io_desc, int nr)
 {
-        int i;
+        struct map_desc *md;
+        struct vm_struct *vm;
+        if (!nr)
+                return;
-        for (i = 0; i < nr; i++)
+        vm = early_alloc_aligned(sizeof(*vm) * nr, __alignof__(*vm));
-                create_mapping(io_desc + i);
+        for (md = io_desc; nr; md++, nr--) {
+                create_mapping(md);
+                vm->addr = (void *)(md->virtual & PAGE_MASK);
+                vm->size = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
+                vm->phys_addr = __pfn_to_phys(md->pfn); 
+                vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING; 
+                vm->flags |= VM_ARM_MTYPE(md->type);
+                vm->caller = iotable_init;
+                vm_area_add_early(vm++);
+        }
 }
-static void * __initdata vmalloc_min = (void *)(VMALLOC_END - SZ_128M);
+static void * __initdata vmalloc_min =
+        (void *)(VMALLOC_END - (240 << 20) - VMALLOC_OFFSET);
 /*
 * vmalloc=size forces the vmalloc area to be exactly 'size'
 * bytes. This can be used to increase (or decrease) the vmalloc
- * area - the default is 128m.
+ * area - the default is 240m.
 */
 static int __init early_vmalloc(char *arg)
 {
@@ -860,6 +882,7 @@ void __init sanity_check_meminfo(void)
        }
 #endif
        meminfo.nr_banks = j;
+        high_memory = __va(lowmem_limit - 1) + 1;
        memblock_set_current_limit(lowmem_limit);
 }
@@ -890,10 +913,10 @@ static inline void prepare_page_table(void)
        /*
         * Clear out all the kernel space mappings, except for the first
-         * memory bank, up to the end of the vmalloc region.
+         * memory bank, up to the vmalloc region.
         */
        for (addr = __phys_to_virt(end);
-             addr < VMALLOC_END; addr += PMD_SIZE)
+             addr < VMALLOC_START; addr += PMD_SIZE)
                pmd_clear(pmd_off_k(addr));
 }
@@ -920,8 +943,8 @@ void __init arm_mm_memblock_reserve(void)
 }
 /*
- * Set up device the mappings.  Since we clear out the page tables for all
+ * Set up the device mappings.  Since we clear out the page tables for all
- * mappings above VMALLOC_END, we will remove any debug device mappings.
+ * mappings above VMALLOC_START, we will remove any debug device mappings.
 * This means you have to be careful how you debug this function, or any
 * called function.  This means you can't use any function or debugging
 * method which may touch any device, otherwise the kernel _will_ crash.
@@ -936,7 +959,7 @@ static void __init devicemaps_init(struct machine_desc *mdesc)
         */
        vectors_page = early_alloc(PAGE_SIZE);
-        for (addr = VMALLOC_END; addr; addr += PMD_SIZE)
+        for (addr = VMALLOC_START; addr; addr += PMD_SIZE)
                pmd_clear(pmd_off_k(addr));
        /*
diff --git a/arch/arm/mm/nommu.c b/arch/arm/mm/nommu.c
index 941a98c9e8aa..4fc6794cca4b 100644
--- a/arch/arm/mm/nommu.c
+++ b/arch/arm/mm/nommu.c
@@ -29,6 +29,8 @@ void __init arm_mm_memblock_reserve(void)
 void __init sanity_check_meminfo(void)
 {
+        phys_addr_t end = bank_phys_end(&meminfo.bank[meminfo.nr_banks - 1]);
+        high_memory = __va(end - 1) + 1;
 }
 /*
@@ -43,7 +45,7 @@ void __init paging_init(struct machine_desc *mdesc)
 /*
 * We don't need to do anything here for nommu machines.
 */
-void setup_mm_for_reboot(char mode)
+void setup_mm_for_reboot(void)
 {
 }
diff --git a/arch/arm/plat-iop/Makefile b/arch/arm/plat-iop/Makefile
index 69b09c1cec8b..90f7153a8d78 100644
--- a/arch/arm/plat-iop/Makefile
+++ b/arch/arm/plat-iop/Makefile
@@ -10,7 +10,6 @@ obj-$(CONFIG_ARCH_IOP32X) += i2c.o
 obj-$(CONFIG_ARCH_IOP32X) += pci.o
 obj-$(CONFIG_ARCH_IOP32X) += setup.o
 obj-$(CONFIG_ARCH_IOP32X) += time.o
-obj-$(CONFIG_ARCH_IOP32X) += io.o
 obj-$(CONFIG_ARCH_IOP32X) += cp6.o
 obj-$(CONFIG_ARCH_IOP32X) += adma.o
 obj-$(CONFIG_ARCH_IOP32X) += pmu.o
@@ -21,7 +20,6 @@ obj-$(CONFIG_ARCH_IOP33X) += i2c.o
 obj-$(CONFIG_ARCH_IOP33X) += pci.o
 obj-$(CONFIG_ARCH_IOP33X) += setup.o
 obj-$(CONFIG_ARCH_IOP33X) += time.o
-obj-$(CONFIG_ARCH_IOP33X) += io.o
 obj-$(CONFIG_ARCH_IOP33X) += cp6.o
 obj-$(CONFIG_ARCH_IOP33X) += adma.o
 obj-$(CONFIG_ARCH_IOP33X) += pmu.o
diff --git a/arch/arm/plat-iop/io.c b/arch/arm/plat-iop/io.c
deleted file mode 100644
index e15bc17db90b..000000000000
--- a/arch/arm/plat-iop/io.c
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * iop3xx custom ioremap implementation
- * Copyright (c) 2006, Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
- * Place - Suite 330, Boston, MA 02111-1307 USA.
- *
- */
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/io.h>
-#include <mach/hardware.h>
-void * __iomem __iop3xx_ioremap(unsigned long cookie, size_t size,
-        unsigned int mtype)
-{
-        void __iomem * retval;
-        switch (cookie) {
-        case IOP3XX_PCI_LOWER_IO_PA ... IOP3XX_PCI_UPPER_IO_PA:
-                retval = (void *) IOP3XX_PCI_IO_PHYS_TO_VIRT(cookie);
-                break;
-        case IOP3XX_PERIPHERAL_PHYS_BASE ... IOP3XX_PERIPHERAL_UPPER_PA:
-                retval = (void *) IOP3XX_PMMR_PHYS_TO_VIRT(cookie);
-                break;
-        default:
-                retval = __arm_ioremap_caller(cookie, size, mtype,
-                                __builtin_return_address(0));
-        }
-        return retval;
-}
-EXPORT_SYMBOL(__iop3xx_ioremap);
-void __iop3xx_iounmap(void __iomem *addr)
-{
-        extern void __iounmap(volatile void __iomem *addr);
-        switch ((u32) addr) {
-        case IOP3XX_PCI_LOWER_IO_VA ... IOP3XX_PCI_UPPER_IO_VA:
-        case IOP3XX_PERIPHERAL_VIRT_BASE ... IOP3XX_PERIPHERAL_UPPER_VA:
-                goto skip;
-        }
-        __iounmap(addr);
-skip:
-        return;
-}
-EXPORT_SYMBOL(__iop3xx_iounmap);
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
index b9f0f5f499a4..076db84f3e31 100644
--- a/arch/arm/plat-mxc/Makefile
+++ b/arch/arm/plat-mxc/Makefile
@@ -5,7 +5,6 @@
 # Common support
 obj-y := clock.o time.o devices.o cpu.o system.o irq-common.o
-obj-$(CONFIG_ARM_GIC) += gic.o
 obj-$(CONFIG_MXC_TZIC) += tzic.o
 obj-$(CONFIG_MXC_AVIC) += avic.o
diff --git a/arch/arm/plat-mxc/gic.c b/arch/arm/plat-mxc/gic.c
deleted file mode 100644
index 12f8f8109010..000000000000
--- a/arch/arm/plat-mxc/gic.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- * Copyright 2011 Linaro Ltd.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#include <linux/io.h>
-#include <asm/exception.h>
-#include <asm/localtimer.h>
-#include <asm/hardware/gic.h>
-#ifdef CONFIG_SMP
-#include <asm/smp.h>
-#endif
-asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
-{
-        u32 irqstat, irqnr;
-        do {
-                irqstat = readl_relaxed(gic_cpu_base_addr + GIC_CPU_INTACK);
-                irqnr = irqstat & 0x3ff;
-                if (irqnr == 1023)
-                        break;
-                if (irqnr > 15 && irqnr < 1021)
-                        handle_IRQ(irqnr, regs);
-#ifdef CONFIG_SMP
-                else {
-                        writel_relaxed(irqstat, gic_cpu_base_addr +
-                                                GIC_CPU_EOI);
-                        handle_IPI(irqnr, regs);
-                }
-#endif
-        } while (1);
-}
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index f4ebdb817abf..3846c53f5b5d 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -89,7 +89,6 @@ extern void imx_print_silicon_rev(const char *cpu, int srev);
 void avic_handle_irq(struct pt_regs *);
 void tzic_handle_irq(struct pt_regs *);
-void gic_handle_irq(struct pt_regs *);
 #define imx1_handle_irq avic_handle_irq
 #define imx21_handle_irq avic_handle_irq
diff --git a/arch/arm/plat-mxc/include/mach/entry-macro.S b/arch/arm/plat-mxc/include/mach/entry-macro.S
index ca5cf26a04b1..def5d30cb67e 100644
--- a/arch/arm/plat-mxc/include/mach/entry-macro.S
+++ b/arch/arm/plat-mxc/include/mach/entry-macro.S
@@ -9,19 +9,8 @@
 * published by the Free Software Foundation.
 */
-/* Unused, we use CONFIG_MULTI_IRQ_HANDLER */
        .macro  disable_fiq
        .endm
-        .macro  get_irqnr_preamble, base, tmp
-        .endm
        .macro  arch_ret_to_user, tmp1, tmp2
        .endm
-        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-        .endm
-        .macro test_for_ipi, irqnr, irqstat, base, tmp
-        .endm
diff --git a/arch/arm/plat-mxc/include/mach/mx1.h b/arch/arm/plat-mxc/include/mach/mx1.h
index 97b19e7800bc..2b7c08d13e89 100644
--- a/arch/arm/plat-mxc/include/mach/mx1.h
+++ b/arch/arm/plat-mxc/include/mach/mx1.h
@@ -12,8 +12,6 @@
 #ifndef __MACH_MX1_H__
 #define __MACH_MX1_H__
-#include <mach/vmalloc.h>
 /*
 * Memory map
 */
diff --git a/arch/arm/plat-mxc/include/mach/vmalloc.h b/arch/arm/plat-mxc/include/mach/vmalloc.h
deleted file mode 100644
index ef6379c474be..000000000000
--- a/arch/arm/plat-mxc/include/mach/vmalloc.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- *  Copyright (C) 2000 Russell King.
- *  Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#ifndef __ASM_ARCH_MXC_VMALLOC_H__
-#define __ASM_ARCH_MXC_VMALLOC_H__
-/* vmalloc ending address */
-#define VMALLOC_END       0xf4000000UL
-#endif /* __ASM_ARCH_MXC_VMALLOC_H__ */
diff --git a/arch/arm/plat-mxc/system.c b/arch/arm/plat-mxc/system.c
index d65fb31a55ca..7e5c76ea4466 100644
--- a/arch/arm/plat-mxc/system.c
+++ b/arch/arm/plat-mxc/system.c
@@ -71,7 +71,7 @@ void arch_reset(char mode, const char *cmd)
        mdelay(50);
        /* we'll take a jump through zero as a poor second */
-        cpu_reset(0);
+        soft_restart(0);
 }
 void mxc_arch_reset_init(void __iomem *base)
diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
index 985262242f25..9a584614e7e6 100644
--- a/arch/arm/plat-omap/Makefile
+++ b/arch/arm/plat-omap/Makefile
@@ -4,7 +4,7 @@
 # Common support
 obj-y := common.o sram.o clock.o devices.o dma.o mux.o \
-         usb.o fb.o io.o counter_32k.o
+         usb.o fb.o counter_32k.o
 obj-m :=
 obj-n :=
 obj-  :=
@@ -19,7 +19,6 @@ obj-$(CONFIG_ARCH_OMAP4) += omap_device.o
 obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
-obj-$(CONFIG_CPU_FREQ) += cpu-omap.o
 obj-$(CONFIG_OMAP_DM_TIMER) += dmtimer.o
 obj-$(CONFIG_OMAP_DEBUG_DEVICES) += debug-devices.o
 obj-$(CONFIG_OMAP_DEBUG_LEDS) += debug-leds.o
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
index d9f10a31e604..06383b51e655 100644
--- a/arch/arm/plat-omap/common.c
+++ b/arch/arm/plat-omap/common.c
@@ -14,6 +14,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/io.h>
+#include <linux/dma-mapping.h>
 #include <linux/omapfb.h>
 #include <plat/common.h>
@@ -21,6 +22,8 @@
 #include <plat/vram.h>
 #include <plat/dsp.h>
+#include <plat/omap-secure.h>
 #define NO_LENGTH_CHECK 0xffffffff
@@ -65,4 +68,12 @@ void __init omap_reserve(void)
        omapfb_reserve_sdram_memblock();
        omap_vram_reserve_sdram_memblock();
        omap_dsp_reserve_sdram_memblock();
+        omap_secure_ram_reserve_memblock();
+}
+void __init omap_init_consistent_dma_size(void)
+{
+#ifdef CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE
+        init_consistent_dma_size(CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE << 20);
+#endif
 }
diff --git a/arch/arm/plat-omap/include/plat/am33xx.h b/arch/arm/plat-omap/include/plat/am33xx.h
new file mode 100644
index 000000000000..06c19bb7bca6
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/am33xx.h
@@ -0,0 +1,25 @@
+/*
+ * This file contains the address info for various AM33XX modules.
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef __ASM_ARCH_AM33XX_H
+#define __ASM_ARCH_AM33XX_H
+#define L4_SLOW_AM33XX_BASE     0x48000000
+#define AM33XX_SCM_BASE         0x44E10000
+#define AM33XX_CTRL_BASE        AM33XX_SCM_BASE
+#define AM33XX_PRCM_BASE        0x44E00000
+#endif /* __ASM_ARCH_AM33XX_H */
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index eb73ab40e955..240a7b9fd946 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -59,6 +59,8 @@ struct clkops {
 #define RATE_IN_4430            (1 << 5)
 #define RATE_IN_TI816X          (1 << 6)
 #define RATE_IN_4460            (1 << 7)
+#define RATE_IN_AM33XX          (1 << 8)
+#define RATE_IN_TI814X          (1 << 9)
 #define RATE_IN_24XX            (RATE_IN_242X | RATE_IN_243X)
 #define RATE_IN_34XX            (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS)
@@ -84,7 +86,7 @@ struct clkops {
 struct clksel_rate {
        u32                     val;
        u8                      div;
-        u8                      flags;
+        u16                     flags;
 };
 /**
diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h
index 3ff3e36580f2..257f9770b2da 100644
--- a/arch/arm/plat-omap/include/plat/common.h
+++ b/arch/arm/plat-omap/include/plat/common.h
@@ -27,97 +27,15 @@
 #ifndef __ARCH_ARM_MACH_OMAP_COMMON_H
 #define __ARCH_ARM_MACH_OMAP_COMMON_H
-#include <linux/delay.h>
 #include <plat/i2c.h>
 #include <plat/omap_hwmod.h>
-struct sys_timer;
-extern void omap_map_common_io(void);
-extern struct sys_timer omap1_timer;
-extern struct sys_timer omap2_timer;
-extern struct sys_timer omap3_timer;
-extern struct sys_timer omap3_secure_timer;
-extern struct sys_timer omap4_timer;
-extern bool omap_32k_timer_init(void);
 extern int __init omap_init_clocksource_32k(void);
 extern unsigned long long notrace omap_32k_sched_clock(void);
 extern void omap_reserve(void);
-void omap2420_init_early(void);
-void omap2430_init_early(void);
-void omap3430_init_early(void);
-void omap35xx_init_early(void);
-void omap3630_init_early(void);
-void omap3_init_early(void);    /* Do not use this one */
-void am35xx_init_early(void);
-void ti816x_init_early(void);
-void omap4430_init_early(void);
 extern int omap_dss_reset(struct omap_hwmod *);
 void omap_sram_init(void);
-/*
- * IO bases for various OMAP processors
- * Except the tap base, rest all the io bases
- * listed are physical addresses.
- */
-struct omap_globals {
-        u32             class;          /* OMAP class to detect */
-        void __iomem    *tap;           /* Control module ID code */
-        void __iomem    *sdrc;           /* SDRAM Controller */
-        void __iomem    *sms;            /* SDRAM Memory Scheduler */
-        void __iomem    *ctrl;           /* System Control Module */
-        void __iomem    *ctrl_pad;      /* PAD Control Module */
-        void __iomem    *prm;            /* Power and Reset Management */
-        void __iomem    *cm;             /* Clock Management */
-        void __iomem    *cm2;
-};
-void omap2_set_globals_242x(void);
-void omap2_set_globals_243x(void);
-void omap2_set_globals_3xxx(void);
-void omap2_set_globals_443x(void);
-void omap2_set_globals_ti816x(void);
-/* These get called from omap2_set_globals_xxxx(), do not call these */
-void omap2_set_globals_tap(struct omap_globals *);
-void omap2_set_globals_sdrc(struct omap_globals *);
-void omap2_set_globals_control(struct omap_globals *);
-void omap2_set_globals_prcm(struct omap_globals *);
-void omap242x_map_io(void);
-void omap243x_map_io(void);
-void omap3_map_io(void);
-void omap4_map_io(void);
-/**
- * omap_test_timeout - busy-loop, testing a condition
- * @cond: condition to test until it evaluates to true
- * @timeout: maximum number of microseconds in the timeout
- * @index: loop index (integer)
- *
- * Loop waiting for @cond to become true or until at least @timeout
- * microseconds have passed.  To use, define some integer @index in the
- * calling code.  After running, if @index == @timeout, then the loop has
- * timed out.
- */
-#define omap_test_timeout(cond, timeout, index)                 \
-({                                                              \
-        for (index = 0; index < timeout; index++) {             \
-                if (cond)                                       \
-                        break;                                  \
-                udelay(1);                                      \
-        }                                                       \
-})
-extern struct device *omap2_get_mpuss_device(void);
-extern struct device *omap2_get_iva_device(void);
-extern struct device *omap2_get_l3_device(void);
-extern struct device *omap4_get_dsp_device(void);
 #endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index 408a12f79205..6b51086fce18 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -69,6 +69,7 @@ unsigned int omap_rev(void);
 * cpu_is_omap343x():   True for OMAP3430
 * cpu_is_omap443x():   True for OMAP4430
 * cpu_is_omap446x():   True for OMAP4460
+ * cpu_is_omap447x():   True for OMAP4470
 */
 #define GET_OMAP_CLASS  (omap_rev() & 0xff)
@@ -78,6 +79,22 @@ static inline int is_omap ##class (void)		\
        return (GET_OMAP_CLASS == (id)) ? 1 : 0;        \
 }
+#define GET_AM_CLASS    ((omap_rev() >> 24) & 0xff)
+#define IS_AM_CLASS(class, id)                          \
+static inline int is_am ##class (void)                  \
+{                                                       \
+        return (GET_AM_CLASS == (id)) ? 1 : 0;          \
+}
+#define GET_TI_CLASS    ((omap_rev() >> 24) & 0xff)
+#define IS_TI_CLASS(class, id)                  \
+static inline int is_ti ##class (void)          \
+{                                                       \
+        return (GET_TI_CLASS == (id)) ? 1 : 0;  \
+}
 #define GET_OMAP_SUBCLASS       ((omap_rev() >> 20) & 0x0fff)
 #define IS_OMAP_SUBCLASS(subclass, id)                  \
@@ -92,12 +109,21 @@ static inline int is_ti ##subclass (void)		\
        return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0;     \
 }
+#define IS_AM_SUBCLASS(subclass, id)                    \
+static inline int is_am ##subclass (void)               \
+{                                                       \
+        return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0;     \
+}
 IS_OMAP_CLASS(7xx, 0x07)
 IS_OMAP_CLASS(15xx, 0x15)
 IS_OMAP_CLASS(16xx, 0x16)
 IS_OMAP_CLASS(24xx, 0x24)
 IS_OMAP_CLASS(34xx, 0x34)
 IS_OMAP_CLASS(44xx, 0x44)
+IS_AM_CLASS(33xx, 0x33)
+IS_TI_CLASS(81xx, 0x81)
 IS_OMAP_SUBCLASS(242x, 0x242)
 IS_OMAP_SUBCLASS(243x, 0x243)
@@ -105,8 +131,11 @@ IS_OMAP_SUBCLASS(343x, 0x343)
 IS_OMAP_SUBCLASS(363x, 0x363)
 IS_OMAP_SUBCLASS(443x, 0x443)
 IS_OMAP_SUBCLASS(446x, 0x446)
+IS_OMAP_SUBCLASS(447x, 0x447)
 IS_TI_SUBCLASS(816x, 0x816)
+IS_TI_SUBCLASS(814x, 0x814)
+IS_AM_SUBCLASS(335x, 0x335)
 #define cpu_is_omap7xx()                0
 #define cpu_is_omap15xx()               0
@@ -116,10 +145,15 @@ IS_TI_SUBCLASS(816x, 0x816)
 #define cpu_is_omap243x()               0
 #define cpu_is_omap34xx()               0
 #define cpu_is_omap343x()               0
+#define cpu_is_ti81xx()                 0
 #define cpu_is_ti816x()                 0
+#define cpu_is_ti814x()                 0
+#define cpu_is_am33xx()                 0
+#define cpu_is_am335x()                 0
 #define cpu_is_omap44xx()               0
 #define cpu_is_omap443x()               0
 #define cpu_is_omap446x()               0
+#define cpu_is_omap447x()               0
 #if defined(MULTI_OMAP1)
 # if defined(CONFIG_ARCH_OMAP730)
@@ -322,7 +356,11 @@ IS_OMAP_TYPE(3517, 0x3517)
 # undef cpu_is_omap3530
 # undef cpu_is_omap3505
 # undef cpu_is_omap3517
+# undef cpu_is_ti81xx
 # undef cpu_is_ti816x
+# undef cpu_is_ti814x
+# undef cpu_is_am33xx
+# undef cpu_is_am335x
 # define cpu_is_omap3430()              is_omap3430()
 # define cpu_is_omap3503()              (cpu_is_omap3430() &&           \
                                                (!omap3_has_iva()) &&   \
@@ -339,16 +377,22 @@ IS_OMAP_TYPE(3517, 0x3517)
                                                !omap3_has_sgx())
 # undef cpu_is_omap3630
 # define cpu_is_omap3630()              is_omap363x()
+# define cpu_is_ti81xx()                is_ti81xx()
 # define cpu_is_ti816x()                is_ti816x()
+# define cpu_is_ti814x()                is_ti814x()
+# define cpu_is_am33xx()                is_am33xx()
+# define cpu_is_am335x()                is_am335x()
 #endif
 # if defined(CONFIG_ARCH_OMAP4)
 # undef cpu_is_omap44xx
 # undef cpu_is_omap443x
 # undef cpu_is_omap446x
+# undef cpu_is_omap447x
 # define cpu_is_omap44xx()              is_omap44xx()
 # define cpu_is_omap443x()              is_omap443x()
 # define cpu_is_omap446x()              is_omap446x()
+# define cpu_is_omap447x()              is_omap447x()
 # endif
 /* Macros to detect if we have OMAP1 or OMAP2 */
@@ -386,15 +430,27 @@ IS_OMAP_TYPE(3517, 0x3517)
 #define TI8168_REV_ES1_0        TI816X_CLASS
 #define TI8168_REV_ES1_1        (TI816X_CLASS | (0x1 << 8))
+#define TI814X_CLASS            0x81400034
+#define TI8148_REV_ES1_0        TI814X_CLASS
+#define TI8148_REV_ES2_0        (TI814X_CLASS | (0x1 << 8))
+#define TI8148_REV_ES2_1        (TI814X_CLASS | (0x2 << 8))
+#define AM335X_CLASS            0x33500034
+#define AM335X_REV_ES1_0        AM335X_CLASS
 #define OMAP443X_CLASS          0x44300044
 #define OMAP4430_REV_ES1_0      (OMAP443X_CLASS | (0x10 << 8))
 #define OMAP4430_REV_ES2_0      (OMAP443X_CLASS | (0x20 << 8))
 #define OMAP4430_REV_ES2_1      (OMAP443X_CLASS | (0x21 << 8))
 #define OMAP4430_REV_ES2_2      (OMAP443X_CLASS | (0x22 << 8))
+#define OMAP4430_REV_ES2_3      (OMAP443X_CLASS | (0x23 << 8))
 #define OMAP446X_CLASS          0x44600044
 #define OMAP4460_REV_ES1_0      (OMAP446X_CLASS | (0x10 << 8))
+#define OMAP447X_CLASS          0x44700044
+#define OMAP4470_REV_ES1_0      (OMAP447X_CLASS | (0x10 << 8))
 void omap2_check_revision(void);
 /*
diff --git a/arch/arm/plat-omap/include/plat/hardware.h b/arch/arm/plat-omap/include/plat/hardware.h
index e87efe1499b8..e897978371c2 100644
--- a/arch/arm/plat-omap/include/plat/hardware.h
+++ b/arch/arm/plat-omap/include/plat/hardware.h
@@ -286,6 +286,7 @@
 #include <plat/omap24xx.h>
 #include <plat/omap34xx.h>
 #include <plat/omap44xx.h>
-#include <plat/ti816x.h>
+#include <plat/ti81xx.h>
+#include <plat/am33xx.h>
 #endif  /* __ASM_ARCH_OMAP_HARDWARE_H */
diff --git a/arch/arm/plat-omap/include/plat/io.h b/arch/arm/plat-omap/include/plat/io.h
index 7f2969eadb85..0696bae1818b 100644
--- a/arch/arm/plat-omap/include/plat/io.h
+++ b/arch/arm/plat-omap/include/plat/io.h
@@ -73,6 +73,9 @@
 #define OMAP4_L3_IO_OFFSET      0xb4000000
 #define OMAP4_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_IO_OFFSET) /* L3 */
+#define AM33XX_L4_WK_IO_OFFSET  0xb5000000
+#define AM33XX_L4_WK_IO_ADDRESS(pa)     IOMEM((pa) + AM33XX_L4_WK_IO_OFFSET)
 #define OMAP4_L3_PER_IO_OFFSET  0xb1100000
 #define OMAP4_L3_PER_IO_ADDRESS(pa)     IOMEM((pa) + OMAP4_L3_PER_IO_OFFSET)
@@ -154,6 +157,15 @@
 #define L4_34XX_SIZE            SZ_4M   /* 1MB of 128MB used, want 1MB sect */
 /*
+ * ----------------------------------------------------------------------------
+ * AM33XX specific IO mapping
+ * ----------------------------------------------------------------------------
+ */
+#define L4_WK_AM33XX_PHYS       L4_WK_AM33XX_BASE
+#define L4_WK_AM33XX_VIRT       (L4_WK_AM33XX_PHYS + AM33XX_L4_WK_IO_OFFSET)
+#define L4_WK_AM33XX_SIZE       SZ_4M   /* 1MB of 128MB used, want 1MB sect */
+/*
 * Need to look at the Size 4M for L4.
 * VPOM3430 was not working for Int controller
 */
@@ -247,8 +259,6 @@
 * NOTE: Please use ioremap + __raw_read/write where possible instead of these
 */
-void omap_ioremap_init(void);
 extern u8 omap_readb(u32 pa);
 extern u16 omap_readw(u32 pa);
 extern u32 omap_readl(u32 pa);
@@ -257,83 +267,9 @@ extern void omap_writew(u16 v, u32 pa);
 extern void omap_writel(u32 v, u32 pa);
 struct omap_sdrc_params;
-#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
-void omap7xx_map_io(void);
-#else
-static inline void omap_map_io(void)
-{
-}
-#endif
-#ifdef CONFIG_ARCH_OMAP15XX
-void omap15xx_map_io(void);
-#else
-static inline void omap15xx_map_io(void)
-{
-}
-#endif
-#ifdef CONFIG_ARCH_OMAP16XX
-void omap16xx_map_io(void);
-#else
-static inline void omap16xx_map_io(void)
-{
-}
-#endif
-void omap1_init_early(void);
-#ifdef CONFIG_SOC_OMAP2420
-extern void omap242x_map_common_io(void);
-#else
-static inline void omap242x_map_common_io(void)
-{
-}
-#endif
-#ifdef CONFIG_SOC_OMAP2430
-extern void omap243x_map_common_io(void);
-#else
-static inline void omap243x_map_common_io(void)
-{
-}
-#endif
-#ifdef CONFIG_ARCH_OMAP3
-extern void omap34xx_map_common_io(void);
-#else
-static inline void omap34xx_map_common_io(void)
-{
-}
-#endif
-#ifdef CONFIG_SOC_OMAPTI816X
-extern void omapti816x_map_common_io(void);
-#else
-static inline void omapti816x_map_common_io(void)
-{
-}
-#endif
-#ifdef CONFIG_ARCH_OMAP4
-extern void omap44xx_map_common_io(void);
-#else
-static inline void omap44xx_map_common_io(void)
-{
-}
-#endif
-extern void omap2_init_common_infrastructure(void);
 extern void omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
                                      struct omap_sdrc_params *sdrc_cs1);
-#define __arch_ioremap  omap_ioremap
-#define __arch_iounmap  omap_iounmap
-void __iomem *omap_ioremap(unsigned long phys, size_t size, unsigned int type);
-void omap_iounmap(volatile void __iomem *addr);
 extern void __init omap_init_consistent_dma_size(void);
 #endif
diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h
index 30e10719b774..ebda7382c65b 100644
--- a/arch/arm/plat-omap/include/plat/irqs.h
+++ b/arch/arm/plat-omap/include/plat/irqs.h
@@ -436,20 +436,6 @@
 #define INTCPS_NR_MIR_REGS      3
 #define INTCPS_NR_IRQS          96
-#ifndef __ASSEMBLY__
-extern void __iomem *omap_irq_base;
-void omap1_init_irq(void);
-void omap2_init_irq(void);
-void omap3_init_irq(void);
-void ti816x_init_irq(void);
-extern int omap_irq_pending(void);
-void omap_intc_save_context(void);
-void omap_intc_restore_context(void);
-void omap3_intc_suspend(void);
-void omap3_intc_prepare_idle(void);
-void omap3_intc_resume_idle(void);
-#endif
 #include <mach/hardware.h>
 #ifdef CONFIG_FIQ
diff --git a/arch/arm/plat-omap/include/plat/omap-secure.h b/arch/arm/plat-omap/include/plat/omap-secure.h
new file mode 100644
index 000000000000..64f9d1c7f1bb
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/omap-secure.h
@@ -0,0 +1,13 @@
+#ifndef __OMAP_SECURE_H__
+#define __OMAP_SECURE_H__
+#include <linux/types.h>
+#ifdef CONFIG_ARCH_OMAP2PLUS
+extern int omap_secure_ram_reserve_memblock(void);
+#else
+static inline void omap_secure_ram_reserve_memblock(void)
+{ }
+#endif
+#endif /* __OMAP_SECURE_H__ */
diff --git a/arch/arm/plat-omap/include/plat/omap-serial.h b/arch/arm/plat-omap/include/plat/omap-serial.h
index 2682043f5a5b..9ff444469f3d 100644
--- a/arch/arm/plat-omap/include/plat/omap-serial.h
+++ b/arch/arm/plat-omap/include/plat/omap-serial.h
@@ -19,6 +19,7 @@
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
+#include <linux/pm_qos.h>
 #include <plat/mux.h>
@@ -33,6 +34,8 @@
 #define OMAP_MODE13X_SPEED      230400
+#define OMAP_UART_SCR_TX_EMPTY  0x08
 /* WER = 0x7F
 * Enable module level wakeup in WER reg
 */
@@ -51,18 +54,27 @@
 #define OMAP_UART_DMA_CH_FREE   -1
-#define RX_TIMEOUT              (3 * HZ)
 #define OMAP_MAX_HSUART_PORTS   4
 #define MSR_SAVE_FLAGS          UART_MSR_ANY_DELTA
+#define UART_ERRATA_i202_MDR1_ACCESS    BIT(0)
+#define UART_ERRATA_i291_DMA_FORCEIDLE  BIT(1)
 struct omap_uart_port_info {
        bool                    dma_enabled;    /* To specify DMA Mode */
        unsigned int            uartclk;        /* UART clock rate */
-        void __iomem            *membase;       /* ioremap cookie or NULL */
-        resource_size_t         mapbase;        /* resource base */
-        unsigned long           irqflags;       /* request_irq flags */
        upf_t                   flags;          /* UPF_* flags */
+        u32                     errata;
+        unsigned int            dma_rx_buf_size;
+        unsigned int            dma_rx_timeout;
+        unsigned int            autosuspend_timeout;
+        unsigned int            dma_rx_poll_rate;
+        int (*get_context_loss_count)(struct device *);
+        void (*set_forceidle)(struct platform_device *);
+        void (*set_noidle)(struct platform_device *);
+        void (*enable_wakeup)(struct platform_device *, bool);
 };
 struct uart_omap_dma {
@@ -86,8 +98,9 @@ struct uart_omap_dma {
        spinlock_t              rx_lock;
        /* timer to poll activity on rx dma */
        struct timer_list       rx_timer;
-        int                     rx_buf_size;
+        unsigned int            rx_buf_size;
-        int                     rx_timeout;
+        unsigned int            rx_poll_rate;
+        unsigned int            rx_timeout;
 };
 struct uart_omap_port {
@@ -100,6 +113,10 @@ struct uart_omap_port {
        unsigned char           mcr;
        unsigned char           fcr;
        unsigned char           efr;
+        unsigned char           dll;
+        unsigned char           dlh;
+        unsigned char           mdr1;
+        unsigned char           scr;
        int                     use_dma;
        /*
@@ -111,6 +128,14 @@ struct uart_omap_port {
        unsigned char           msr_saved_flags;
        char                    name[20];
        unsigned long           port_activity;
+        u32                     context_loss_cnt;
+        u32                     errata;
+        u8                      wakeups_enabled;
+        struct pm_qos_request   pm_qos_request;
+        u32                     latency;
+        u32                     calc_latency;
+        struct work_struct      qos_work;
 };
 #endif /* __OMAP_SERIAL_H__ */
diff --git a/arch/arm/plat-omap/include/plat/omap34xx.h b/arch/arm/plat-omap/include/plat/omap34xx.h
index b9e85886b9d6..0d818acf3917 100644
--- a/arch/arm/plat-omap/include/plat/omap34xx.h
+++ b/arch/arm/plat-omap/include/plat/omap34xx.h
@@ -35,6 +35,8 @@
 #define L4_EMU_34XX_BASE        0x54000000
 #define L3_34XX_BASE            0x68000000
+#define L4_WK_AM33XX_BASE       0x44C00000
 #define OMAP3430_32KSYNCT_BASE  0x48320000
 #define OMAP3430_CM_BASE        0x48004800
 #define OMAP3430_PRM_BASE       0x48306800
diff --git a/arch/arm/plat-omap/include/plat/omap44xx.h b/arch/arm/plat-omap/include/plat/omap44xx.h
index ea2b8a6306e7..c0d478e55c84 100644
--- a/arch/arm/plat-omap/include/plat/omap44xx.h
+++ b/arch/arm/plat-omap/include/plat/omap44xx.h
@@ -45,6 +45,7 @@
 #define OMAP44XX_WKUPGEN_BASE           0x48281000
 #define OMAP44XX_MCPDM_BASE             0x40132000
 #define OMAP44XX_MCPDM_L3_BASE          0x49032000
+#define OMAP44XX_SAR_RAM_BASE           0x4a326000
 #define OMAP44XX_MAILBOX_BASE           (L4_44XX_BASE + 0xF4000)
 #define OMAP44XX_HSUSB_OTG_BASE         (L4_44XX_BASE + 0xAB000)
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index 8b372ede17c1..647010109afa 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -97,6 +97,7 @@ struct omap_hwmod_mux_info {
        struct omap_device_pad          *pads;
        int                             nr_pads_dynamic;
        struct omap_device_pad          **pads_dynamic;
+        int                             *irqs;
        bool                            enabled;
 };
@@ -416,10 +417,13 @@ struct omap_hwmod_omap4_prcm {
 * _HWMOD_NO_MPU_PORT: no path exists for the MPU to write to this module
 * _HWMOD_WAKEUP_ENABLED: set when the omap_hwmod code has enabled ENAWAKEUP
 * _HWMOD_SYSCONFIG_LOADED: set when the OCP_SYSCONFIG value has been cached
+ * _HWMOD_SKIP_ENABLE: set if hwmod enabled during init (HWMOD_INIT_NO_IDLE) -
+ *     causes the first call to _enable() to only update the pinmux
 */
 #define _HWMOD_NO_MPU_PORT                      (1 << 0)
 #define _HWMOD_WAKEUP_ENABLED                   (1 << 1)
 #define _HWMOD_SYSCONFIG_LOADED                 (1 << 2)
+#define _HWMOD_SKIP_ENABLE                      (1 << 3)
 /*
 * omap_hwmod._state definitions
@@ -604,6 +608,8 @@ int omap_hwmod_get_context_loss_count(struct omap_hwmod *oh);
 int omap_hwmod_no_setup_reset(struct omap_hwmod *oh);
+int omap_hwmod_pad_route_irq(struct omap_hwmod *oh, int pad_idx, int irq_idx);
 /*
 * Chip variant-specific hwmod init routines - XXX should be converted
 * to use initcalls once the initial boot ordering is straightened out
diff --git a/arch/arm/plat-omap/include/plat/serial.h b/arch/arm/plat-omap/include/plat/serial.h
index 1ab9fd6abe6d..38b3e38df2a0 100644
--- a/arch/arm/plat-omap/include/plat/serial.h
+++ b/arch/arm/plat-omap/include/plat/serial.h
@@ -51,10 +51,10 @@
 #define OMAP4_UART3_BASE        0x48020000
 #define OMAP4_UART4_BASE        0x4806e000
-/* TI816X serial ports */
+/* TI81XX serial ports */
-#define TI816X_UART1_BASE       0x48020000
+#define TI81XX_UART1_BASE       0x48020000
-#define TI816X_UART2_BASE       0x48022000
+#define TI81XX_UART2_BASE       0x48022000
-#define TI816X_UART3_BASE       0x48024000
+#define TI81XX_UART3_BASE       0x48024000
 /* AM3505/3517 UART4 */
 #define AM35XX_UART4_BASE       0x4809E000      /* Only on AM3505/3517 */
@@ -89,9 +89,9 @@
 #define OMAP4UART2              OMAP2UART2
 #define OMAP4UART3              43
 #define OMAP4UART4              44
-#define TI816XUART1             81
+#define TI81XXUART1             81
-#define TI816XUART2             82
+#define TI81XXUART2             82
-#define TI816XUART3             83
+#define TI81XXUART3             83
 #define ZOOM_UART               95              /* Only on zoom2/3 */
 /* This is only used by 8250.c for omap1510 */
@@ -106,15 +106,13 @@
 #ifndef __ASSEMBLER__
 struct omap_board_data;
+struct omap_uart_port_info;
 extern void omap_serial_init(void);
-extern void omap_serial_init_port(struct omap_board_data *bdata);
 extern int omap_uart_can_sleep(void);
-extern void omap_uart_check_wakeup(void);
+extern void omap_serial_board_init(struct omap_uart_port_info *platform_data);
-extern void omap_uart_prepare_suspend(void);
+extern void omap_serial_init_port(struct omap_board_data *bdata,
-extern void omap_uart_prepare_idle(int num);
+                struct omap_uart_port_info *platform_data);
-extern void omap_uart_resume_idle(int num);
-extern void omap_uart_enable_irqs(int enable);
 #endif
 #endif
diff --git a/arch/arm/plat-omap/include/plat/sram.h b/arch/arm/plat-omap/include/plat/sram.h
index f500fc34d065..75aa1b2bef51 100644
--- a/arch/arm/plat-omap/include/plat/sram.h
+++ b/arch/arm/plat-omap/include/plat/sram.h
@@ -95,6 +95,10 @@ static inline void omap_push_sram_idle(void) {}
 */
 #define OMAP2_SRAM_PA           0x40200000
 #define OMAP3_SRAM_PA           0x40200000
+#ifdef CONFIG_OMAP4_ERRATA_I688
+#define OMAP4_SRAM_PA           0x40304000
+#define OMAP4_SRAM_VA           0xfe404000
+#else
 #define OMAP4_SRAM_PA           0x40300000
+#endif
 #endif
diff --git a/arch/arm/plat-omap/include/plat/ti816x.h b/arch/arm/plat-omap/include/plat/ti81xx.h
index 50510f5dda1e..8f9843f78422 100644
--- a/arch/arm/plat-omap/include/plat/ti816x.h
+++ b/arch/arm/plat-omap/include/plat/ti81xx.h
@@ -1,5 +1,5 @@
 /*
- * This file contains the address data for various TI816X modules.
+ * This file contains the address data for various TI81XX modules.
 *
 * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
 *
@@ -13,15 +13,15 @@
 * GNU General Public License for more details.
 */
-#ifndef __ASM_ARCH_TI816X_H
+#ifndef __ASM_ARCH_TI81XX_H
-#define __ASM_ARCH_TI816X_H
+#define __ASM_ARCH_TI81XX_H
-#define L4_SLOW_TI816X_BASE     0x48000000
+#define L4_SLOW_TI81XX_BASE     0x48000000
-#define TI816X_SCM_BASE         0x48140000
+#define TI81XX_SCM_BASE         0x48140000
-#define TI816X_CTRL_BASE        TI816X_SCM_BASE
+#define TI81XX_CTRL_BASE        TI81XX_SCM_BASE
-#define TI816X_PRCM_BASE        0x48180000
+#define TI81XX_PRCM_BASE        0x48180000
-#define TI816X_ARM_INTC_BASE    0x48200000
+#define TI81XX_ARM_INTC_BASE    0x48200000
-#endif /* __ASM_ARCH_TI816X_H */
+#endif /* __ASM_ARCH_TI81XX_H */
diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h
index 2f472e989ec6..7fbc361946b5 100644
--- a/arch/arm/plat-omap/include/plat/uncompress.h
+++ b/arch/arm/plat-omap/include/plat/uncompress.h
@@ -99,9 +99,9 @@ static inline void flush(void)
 #define DEBUG_LL_ZOOM(mach)                                             \
        _DEBUG_LL_ENTRY(mach, ZOOM_UART_BASE, ZOOM_PORT_SHIFT, ZOOM_UART)
-#define DEBUG_LL_TI816X(p, mach)                                        \
+#define DEBUG_LL_TI81XX(p, mach)                                        \
-        _DEBUG_LL_ENTRY(mach, TI816X_UART##p##_BASE, OMAP_PORT_SHIFT,   \
+        _DEBUG_LL_ENTRY(mach, TI81XX_UART##p##_BASE, OMAP_PORT_SHIFT,   \
-                TI816XUART##p)
+                TI81XXUART##p)
 static inline void __arch_decomp_setup(unsigned long arch_id)
 {
@@ -177,7 +177,7 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
                DEBUG_LL_ZOOM(omap_zoom3);
                /* TI8168 base boards using UART3 */
-                DEBUG_LL_TI816X(3, ti8168evm);
+                DEBUG_LL_TI81XX(3, ti8168evm);
        } while (0);
 }
diff --git a/arch/arm/plat-omap/io.c b/arch/arm/plat-omap/io.c
deleted file mode 100644
index 333871f59995..000000000000
--- a/arch/arm/plat-omap/io.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/*
- * Common io.c file
- * This file is created by Russell King <rmk+kernel@arm.linux.org.uk>
- *
- * Copyright (C) 2009 Texas Instruments
- * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/module.h>
-#include <linux/io.h>
-#include <linux/mm.h>
-#include <linux/dma-mapping.h>
-#include <plat/omap7xx.h>
-#include <plat/omap1510.h>
-#include <plat/omap16xx.h>
-#include <plat/omap24xx.h>
-#include <plat/omap34xx.h>
-#include <plat/omap44xx.h>
-#define BETWEEN(p,st,sz)        ((p) >= (st) && (p) < ((st) + (sz)))
-#define XLATE(p,pst,vst)        ((void __iomem *)((p) - (pst) + (vst)))
-static int initialized;
-/*
- * Intercept ioremap() requests for addresses in our fixed mapping regions.
- */
-void __iomem *omap_ioremap(unsigned long p, size_t size, unsigned int type)
-{
-        WARN(!initialized, "Do not use ioremap before init_early\n");
-#ifdef CONFIG_ARCH_OMAP1
-        if (cpu_class_is_omap1()) {
-                if (BETWEEN(p, OMAP1_IO_PHYS, OMAP1_IO_SIZE))
-                        return XLATE(p, OMAP1_IO_PHYS, OMAP1_IO_VIRT);
-        }
-        if (cpu_is_omap7xx()) {
-                if (BETWEEN(p, OMAP7XX_DSP_BASE, OMAP7XX_DSP_SIZE))
-                        return XLATE(p, OMAP7XX_DSP_BASE, OMAP7XX_DSP_START);
-                if (BETWEEN(p, OMAP7XX_DSPREG_BASE, OMAP7XX_DSPREG_SIZE))
-                        return XLATE(p, OMAP7XX_DSPREG_BASE,
-                                        OMAP7XX_DSPREG_START);
-        }
-        if (cpu_is_omap15xx()) {
-                if (BETWEEN(p, OMAP1510_DSP_BASE, OMAP1510_DSP_SIZE))
-                        return XLATE(p, OMAP1510_DSP_BASE, OMAP1510_DSP_START);
-                if (BETWEEN(p, OMAP1510_DSPREG_BASE, OMAP1510_DSPREG_SIZE))
-                        return XLATE(p, OMAP1510_DSPREG_BASE,
-                                        OMAP1510_DSPREG_START);
-        }
-        if (cpu_is_omap16xx()) {
-                if (BETWEEN(p, OMAP16XX_DSP_BASE, OMAP16XX_DSP_SIZE))
-                        return XLATE(p, OMAP16XX_DSP_BASE, OMAP16XX_DSP_START);
-                if (BETWEEN(p, OMAP16XX_DSPREG_BASE, OMAP16XX_DSPREG_SIZE))
-                        return XLATE(p, OMAP16XX_DSPREG_BASE,
-                                        OMAP16XX_DSPREG_START);
-        }
-#endif
-#ifdef CONFIG_ARCH_OMAP2
-        if (cpu_is_omap24xx()) {
-                if (BETWEEN(p, L3_24XX_PHYS, L3_24XX_SIZE))
-                        return XLATE(p, L3_24XX_PHYS, L3_24XX_VIRT);
-                if (BETWEEN(p, L4_24XX_PHYS, L4_24XX_SIZE))
-                        return XLATE(p, L4_24XX_PHYS, L4_24XX_VIRT);
-        }
-        if (cpu_is_omap2420()) {
-                if (BETWEEN(p, DSP_MEM_2420_PHYS, DSP_MEM_2420_SIZE))
-                        return XLATE(p, DSP_MEM_2420_PHYS, DSP_MEM_2420_VIRT);
-                if (BETWEEN(p, DSP_IPI_2420_PHYS, DSP_IPI_2420_SIZE))
-                        return XLATE(p, DSP_IPI_2420_PHYS, DSP_IPI_2420_SIZE);
-                if (BETWEEN(p, DSP_MMU_2420_PHYS, DSP_MMU_2420_SIZE))
-                        return XLATE(p, DSP_MMU_2420_PHYS, DSP_MMU_2420_VIRT);
-        }
-        if (cpu_is_omap2430()) {
-                if (BETWEEN(p, L4_WK_243X_PHYS, L4_WK_243X_SIZE))
-                        return XLATE(p, L4_WK_243X_PHYS, L4_WK_243X_VIRT);
-                if (BETWEEN(p, OMAP243X_GPMC_PHYS, OMAP243X_GPMC_SIZE))
-                        return XLATE(p, OMAP243X_GPMC_PHYS, OMAP243X_GPMC_VIRT);
-                if (BETWEEN(p, OMAP243X_SDRC_PHYS, OMAP243X_SDRC_SIZE))
-                        return XLATE(p, OMAP243X_SDRC_PHYS, OMAP243X_SDRC_VIRT);
-                if (BETWEEN(p, OMAP243X_SMS_PHYS, OMAP243X_SMS_SIZE))
-                        return XLATE(p, OMAP243X_SMS_PHYS, OMAP243X_SMS_VIRT);
-        }
-#endif
-#ifdef CONFIG_ARCH_OMAP3
-        if (cpu_is_ti816x()) {
-                if (BETWEEN(p, L4_34XX_PHYS, L4_34XX_SIZE))
-                        return XLATE(p, L4_34XX_PHYS, L4_34XX_VIRT);
-        } else if (cpu_is_omap34xx()) {
-                if (BETWEEN(p, L3_34XX_PHYS, L3_34XX_SIZE))
-                        return XLATE(p, L3_34XX_PHYS, L3_34XX_VIRT);
-                if (BETWEEN(p, L4_34XX_PHYS, L4_34XX_SIZE))
-                        return XLATE(p, L4_34XX_PHYS, L4_34XX_VIRT);
-                if (BETWEEN(p, OMAP34XX_GPMC_PHYS, OMAP34XX_GPMC_SIZE))
-                        return XLATE(p, OMAP34XX_GPMC_PHYS, OMAP34XX_GPMC_VIRT);
-                if (BETWEEN(p, OMAP343X_SMS_PHYS, OMAP343X_SMS_SIZE))
-                        return XLATE(p, OMAP343X_SMS_PHYS, OMAP343X_SMS_VIRT);
-                if (BETWEEN(p, OMAP343X_SDRC_PHYS, OMAP343X_SDRC_SIZE))
-                        return XLATE(p, OMAP343X_SDRC_PHYS, OMAP343X_SDRC_VIRT);
-                if (BETWEEN(p, L4_PER_34XX_PHYS, L4_PER_34XX_SIZE))
-                        return XLATE(p, L4_PER_34XX_PHYS, L4_PER_34XX_VIRT);
-                if (BETWEEN(p, L4_EMU_34XX_PHYS, L4_EMU_34XX_SIZE))
-                        return XLATE(p, L4_EMU_34XX_PHYS, L4_EMU_34XX_VIRT);
-        }
-#endif
-#ifdef CONFIG_ARCH_OMAP4
-        if (cpu_is_omap44xx()) {
-                if (BETWEEN(p, L3_44XX_PHYS, L3_44XX_SIZE))
-                        return XLATE(p, L3_44XX_PHYS, L3_44XX_VIRT);
-                if (BETWEEN(p, L4_44XX_PHYS, L4_44XX_SIZE))
-                        return XLATE(p, L4_44XX_PHYS, L4_44XX_VIRT);
-                if (BETWEEN(p, OMAP44XX_GPMC_PHYS, OMAP44XX_GPMC_SIZE))
-                        return XLATE(p, OMAP44XX_GPMC_PHYS, OMAP44XX_GPMC_VIRT);
-                if (BETWEEN(p, OMAP44XX_EMIF1_PHYS, OMAP44XX_EMIF1_SIZE))
-                        return XLATE(p, OMAP44XX_EMIF1_PHYS,            \
-                                                        OMAP44XX_EMIF1_VIRT);
-                if (BETWEEN(p, OMAP44XX_EMIF2_PHYS, OMAP44XX_EMIF2_SIZE))
-                        return XLATE(p, OMAP44XX_EMIF2_PHYS,            \
-                                                        OMAP44XX_EMIF2_VIRT);
-                if (BETWEEN(p, OMAP44XX_DMM_PHYS, OMAP44XX_DMM_SIZE))
-                        return XLATE(p, OMAP44XX_DMM_PHYS, OMAP44XX_DMM_VIRT);
-                if (BETWEEN(p, L4_PER_44XX_PHYS, L4_PER_44XX_SIZE))
-                        return XLATE(p, L4_PER_44XX_PHYS, L4_PER_44XX_VIRT);
-                if (BETWEEN(p, L4_EMU_44XX_PHYS, L4_EMU_44XX_SIZE))
-                        return XLATE(p, L4_EMU_44XX_PHYS, L4_EMU_44XX_VIRT);
-        }
-#endif
-        return __arm_ioremap_caller(p, size, type, __builtin_return_address(0));
-}
-EXPORT_SYMBOL(omap_ioremap);
-void omap_iounmap(volatile void __iomem *addr)
-{
-        unsigned long virt = (unsigned long)addr;
-        if (virt >= VMALLOC_START && virt < VMALLOC_END)
-                __iounmap(addr);
-}
-EXPORT_SYMBOL(omap_iounmap);
-void __init omap_init_consistent_dma_size(void)
-{
-#ifdef CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE
-        init_consistent_dma_size(CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE << 20);
-#endif
-}
-void __init omap_ioremap_init(void)
-{
-        initialized++;
-}
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index 8b28664d1c62..ad6a71a00cef 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -40,7 +40,11 @@
 #define OMAP1_SRAM_PA           0x20000000
 #define OMAP2_SRAM_PUB_PA       (OMAP2_SRAM_PA + 0xf800)
 #define OMAP3_SRAM_PUB_PA       (OMAP3_SRAM_PA + 0x8000)
+#ifdef CONFIG_OMAP4_ERRATA_I688
+#define OMAP4_SRAM_PUB_PA       OMAP4_SRAM_PA
+#else
 #define OMAP4_SRAM_PUB_PA       (OMAP4_SRAM_PA + 0x4000)
+#endif
 #if defined(CONFIG_ARCH_OMAP2PLUS)
 #define SRAM_BOOTLOADER_SZ      0x00
@@ -163,6 +167,10 @@ static void __init omap_map_sram(void)
        if (omap_sram_size == 0)
                return;
+#ifdef CONFIG_OMAP4_ERRATA_I688
+                omap_sram_start += PAGE_SIZE;
+                omap_sram_size -= SZ_16K;
+#endif
        if (cpu_is_omap34xx()) {
                /*
                 * SRAM must be marked as non-cached on OMAP3 since the
diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig
index 9b9968fa8695..8167ce66188c 100644
--- a/arch/arm/plat-s5p/Kconfig
+++ b/arch/arm/plat-s5p/Kconfig
@@ -11,6 +11,7 @@ config PLAT_S5P
        default y
        select ARM_VIC if !ARCH_EXYNOS4
        select ARM_GIC if ARCH_EXYNOS4
+        select GIC_NON_BANKED if ARCH_EXYNOS4
        select NO_IOPORT
        select ARCH_REQUIRE_GPIOLIB
        select S3C_GPIO_TRACK
diff --git a/arch/arm/plat-spear/include/plat/system.h b/arch/arm/plat-spear/include/plat/system.h
index a235fa0ca777..1171f228d718 100644
--- a/arch/arm/plat-spear/include/plat/system.h
+++ b/arch/arm/plat-spear/include/plat/system.h
@@ -31,7 +31,7 @@ static inline void arch_reset(char mode, const char *cmd)
 {
        if (mode == 's') {
                /* software reset, Jump into ROM at address 0 */
-                cpu_reset(0);
+                soft_restart(0);
        } else {
                /* hardware reset, Use on-chip reset capability */
                sysctl_soft_reset((void __iomem *)VA_SPEAR_SYS_CTRL_BASE);
diff --git a/arch/arm/plat-spear/include/plat/vmalloc.h b/arch/arm/plat-spear/include/plat/vmalloc.h
deleted file mode 100644
index 8c8b24d07046..000000000000
--- a/arch/arm/plat-spear/include/plat/vmalloc.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * arch/arm/plat-spear/include/plat/vmalloc.h
- *
- * Defining Vmalloc area for SPEAr platform
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#ifndef __PLAT_VMALLOC_H
-#define __PLAT_VMALLOC_H
-#define VMALLOC_END             0xF0000000UL
-#endif /* __PLAT_VMALLOC_H */
diff --git a/arch/arm/plat-tcc/include/mach/vmalloc.h b/arch/arm/plat-tcc/include/mach/vmalloc.h
deleted file mode 100644
index 99414d9c2b94..000000000000
--- a/arch/arm/plat-tcc/include/mach/vmalloc.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/*
- * Author: <linux@telechips.com>
- * Created: June 10, 2008
- *
- * Copyright (C) 2000 Russell King.
- * Copyright (C) 2008-2009 Telechips
- *
- * Licensed under the terms of the GPL v2.
- */
-#define VMALLOC_END     0xf0000000UL