149 files changed, 3306 insertions, 2702 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 5ebc5d922ea1..3269576dbfa8 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1271,6 +1271,18 @@ config ARM_ERRATA_754327
          This workaround defines cpu_relax() as smp_mb(), preventing correctly
          written polling loops from denying visibility of updates to memory.
+config ARM_ERRATA_364296
+        bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
+        depends on CPU_V6 && !SMP
+        help
+          This options enables the workaround for the 364296 ARM1136
+          r0p2 erratum (possible cache data corruption with
+          hit-under-miss enabled). It sets the undocumented bit 31 in
+          the auxiliary control register and the FI bit in the control
+          register, thus disabling hit-under-miss without putting the
+          processor into full low interrupt latency mode. ARM11MPCore
+          is not affected.
 endmenu
 source "arch/arm/common/Kconfig"
diff --git a/arch/arm/boot/compressed/mmcif-sh7372.c b/arch/arm/boot/compressed/mmcif-sh7372.c
index b6f61d9a5a1b..672ae95db5c3 100644
--- a/arch/arm/boot/compressed/mmcif-sh7372.c
+++ b/arch/arm/boot/compressed/mmcif-sh7372.c
@@ -82,7 +82,7 @@ asmlinkage void mmc_loader(unsigned char *buf, unsigned long len)
        /* Disable clock to MMC hardware block */
-        __raw_writel(__raw_readl(SMSTPCR3) & (1 << 12), SMSTPCR3);
+        __raw_writel(__raw_readl(SMSTPCR3) | (1 << 12), SMSTPCR3);
        mmc_update_progress(MMC_PROGRESS_DONE);
 }
diff --git a/arch/arm/boot/compressed/sdhi-sh7372.c b/arch/arm/boot/compressed/sdhi-sh7372.c
index d403a8b24d7f..d279294f2381 100644
--- a/arch/arm/boot/compressed/sdhi-sh7372.c
+++ b/arch/arm/boot/compressed/sdhi-sh7372.c
@@ -85,7 +85,7 @@ asmlinkage void mmc_loader(unsigned short *buf, unsigned long len)
                goto err;
        /* Disable clock to SDHI1 hardware block */
-        __raw_writel(__raw_readl(SMSTPCR3) & (1 << 13), SMSTPCR3);
+        __raw_writel(__raw_readl(SMSTPCR3) | (1 << 13), SMSTPCR3);
        mmc_update_progress(MMC_PROGRESS_DONE);
diff --git a/arch/arm/boot/dts/tegra-harmony.dts b/arch/arm/boot/dts/tegra-harmony.dts
index 4c053340ce33..e5818668d091 100644
--- a/arch/arm/boot/dts/tegra-harmony.dts
+++ b/arch/arm/boot/dts/tegra-harmony.dts
@@ -57,14 +57,14 @@
        };
        sdhci@c8000200 {
-                gpios = <&gpio 69 0>, /* cd, gpio PI5 */
+                cd-gpios = <&gpio 69 0>; /* gpio PI5 */
-                        <&gpio 57 0>, /* wp, gpio PH1 */
+                wp-gpios = <&gpio 57 0>; /* gpio PH1 */
-                        <&gpio 155 0>; /* power, gpio PT3 */
+                power-gpios = <&gpio 155 0>; /* gpio PT3 */
        };
        sdhci@c8000600 {
-                gpios = <&gpio 58 0>, /* cd, gpio PH2 */
+                cd-gpios = <&gpio 58 0>; /* gpio PH2 */
-                        <&gpio 59 0>, /* wp, gpio PH3 */
+                wp-gpios = <&gpio 59 0>; /* gpio PH3 */
-                        <&gpio 70 0>; /* power, gpio PI6 */
+                power-gpios = <&gpio 70 0>; /* gpio PI6 */
        };
 };
diff --git a/arch/arm/boot/dts/tegra-seaboard.dts b/arch/arm/boot/dts/tegra-seaboard.dts
index 1940cae00748..64cedca6fc79 100644
--- a/arch/arm/boot/dts/tegra-seaboard.dts
+++ b/arch/arm/boot/dts/tegra-seaboard.dts
@@ -21,8 +21,8 @@
        };
        sdhci@c8000400 {
-                gpios = <&gpio 69 0>, /* cd, gpio PI5 */
+                cd-gpios = <&gpio 69 0>; /* gpio PI5 */
-                        <&gpio 57 0>, /* wp, gpio PH1 */
+                wp-gpios = <&gpio 57 0>; /* gpio PH1 */
-                        <&gpio 70 0>; /* power, gpio PI6 */
+                power-gpios = <&gpio 70 0>; /* gpio PI6 */
        };
 };
diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h
index 16bd48031583..99a6ed7e1bfd 100644
--- a/arch/arm/include/asm/hardware/cache-l2x0.h
+++ b/arch/arm/include/asm/hardware/cache-l2x0.h
@@ -45,8 +45,13 @@
 #define L2X0_CLEAN_INV_LINE_PA          0x7F0
 #define L2X0_CLEAN_INV_LINE_IDX         0x7F8
 #define L2X0_CLEAN_INV_WAY              0x7FC
-#define L2X0_LOCKDOWN_WAY_D             0x900
+/*
-#define L2X0_LOCKDOWN_WAY_I             0x904
+ * The lockdown registers repeat 8 times for L310, the L210 has only one
+ * D and one I lockdown register at 0x0900 and 0x0904.
+ */
+#define L2X0_LOCKDOWN_WAY_D_BASE        0x900
+#define L2X0_LOCKDOWN_WAY_I_BASE        0x904
+#define L2X0_LOCKDOWN_STRIDE            0x08
 #define L2X0_TEST_OPERATION             0xF00
 #define L2X0_LINE_DATA                  0xF10
 #define L2X0_LINE_TAG                   0xF30
@@ -64,7 +69,7 @@
 #define L2X0_AUX_CTRL_MASK                      0xc0000fff
 #define L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT       16
 #define L2X0_AUX_CTRL_WAY_SIZE_SHIFT            17
-#define L2X0_AUX_CTRL_WAY_SIZE_MASK             (0x3 << 17)
+#define L2X0_AUX_CTRL_WAY_SIZE_MASK             (0x7 << 17)
 #define L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT      22
 #define L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT         26
 #define L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT         27
diff --git a/arch/arm/include/asm/pmu.h b/arch/arm/include/asm/pmu.h
index 67c70a31a1be..b7e82c4aced6 100644
--- a/arch/arm/include/asm/pmu.h
+++ b/arch/arm/include/asm/pmu.h
@@ -41,7 +41,7 @@ struct arm_pmu_platdata {
 * encoded error on failure.
 */
 extern struct platform_device *
-reserve_pmu(enum arm_pmu_type device);
+reserve_pmu(enum arm_pmu_type type);
 /**
 * release_pmu() - Relinquish control of the performance counters
@@ -62,26 +62,26 @@ release_pmu(enum arm_pmu_type type);
 * the actual hardware initialisation.
 */
 extern int
-init_pmu(enum arm_pmu_type device);
+init_pmu(enum arm_pmu_type type);
 #else /* CONFIG_CPU_HAS_PMU */
 #include <linux/err.h>
 static inline struct platform_device *
-reserve_pmu(enum arm_pmu_type device)
+reserve_pmu(enum arm_pmu_type type)
 {
        return ERR_PTR(-ENODEV);
 }
 static inline int
-release_pmu(struct platform_device *pdev)
+release_pmu(enum arm_pmu_type type)
 {
        return -ENODEV;
 }
 static inline int
-init_pmu(enum arm_pmu_type device)
+init_pmu(enum arm_pmu_type type)
 {
        return -ENODEV;
 }
diff --git a/arch/arm/kernel/pmu.c b/arch/arm/kernel/pmu.c
index 2b70709376c3..c53474fe84df 100644
--- a/arch/arm/kernel/pmu.c
+++ b/arch/arm/kernel/pmu.c
@@ -31,7 +31,7 @@ static int __devinit pmu_register(struct platform_device *pdev,
 {
        if (type < 0 || type >= ARM_NUM_PMU_DEVICES) {
                pr_warning("received registration request for unknown "
-                                "device %d\n", type);
+                                "PMU device type %d\n", type);
                return -EINVAL;
        }
@@ -112,17 +112,17 @@ static int __init register_pmu_driver(void)
 device_initcall(register_pmu_driver);
 struct platform_device *
-reserve_pmu(enum arm_pmu_type device)
+reserve_pmu(enum arm_pmu_type type)
 {
        struct platform_device *pdev;
-        if (test_and_set_bit_lock(device, &pmu_lock)) {
+        if (test_and_set_bit_lock(type, &pmu_lock)) {
                pdev = ERR_PTR(-EBUSY);
-        } else if (pmu_devices[device] == NULL) {
+        } else if (pmu_devices[type] == NULL) {
-                clear_bit_unlock(device, &pmu_lock);
+                clear_bit_unlock(type, &pmu_lock);
                pdev = ERR_PTR(-ENODEV);
        } else {
-                pdev = pmu_devices[device];
+                pdev = pmu_devices[type];
        }
        return pdev;
@@ -130,11 +130,11 @@ reserve_pmu(enum arm_pmu_type device)
 EXPORT_SYMBOL_GPL(reserve_pmu);
 int
-release_pmu(enum arm_pmu_type device)
+release_pmu(enum arm_pmu_type type)
 {
-        if (WARN_ON(!pmu_devices[device]))
+        if (WARN_ON(!pmu_devices[type]))
                return -EINVAL;
-        clear_bit_unlock(device, &pmu_lock);
+        clear_bit_unlock(type, &pmu_lock);
        return 0;
 }
 EXPORT_SYMBOL_GPL(release_pmu);
@@ -182,17 +182,17 @@ init_cpu_pmu(void)
 }
 int
-init_pmu(enum arm_pmu_type device)
+init_pmu(enum arm_pmu_type type)
 {
        int err = 0;
-        switch (device) {
+        switch (type) {
        case ARM_PMU_DEVICE_CPU:
                err = init_cpu_pmu();
                break;
        default:
-                pr_warning("attempt to initialise unknown device %d\n",
+                pr_warning("attempt to initialise PMU of unknown "
-                                device);
+                           "type %d\n", type);
                err = -EINVAL;
        }
diff --git a/arch/arm/kernel/relocate_kernel.S b/arch/arm/kernel/relocate_kernel.S
index 9cf4cbf8f95b..d0cdedf4864d 100644
--- a/arch/arm/kernel/relocate_kernel.S
+++ b/arch/arm/kernel/relocate_kernel.S
@@ -57,7 +57,8 @@ relocate_new_kernel:
        mov r0,#0
        ldr r1,kexec_mach_type
        ldr r2,kexec_boot_atags
-        mov pc,lr
+ ARM(   mov pc, lr      )
+ THUMB( bx lr           )
        .align
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 70bca649e925..e514c76043b4 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -280,18 +280,19 @@ static void __init cacheid_init(void)
        if (arch >= CPU_ARCH_ARMv6) {
                if ((cachetype & (7 << 29)) == 4 << 29) {
                        /* ARMv7 register format */
+                        arch = CPU_ARCH_ARMv7;
                        cacheid = CACHEID_VIPT_NONALIASING;
                        if ((cachetype & (3 << 14)) == 1 << 14)
                                cacheid |= CACHEID_ASID_TAGGED;
-                        else if (cpu_has_aliasing_icache(CPU_ARCH_ARMv7))
-                                cacheid |= CACHEID_VIPT_I_ALIASING;
-                } else if (cachetype & (1 << 23)) {
-                        cacheid = CACHEID_VIPT_ALIASING;
                } else {
-                        cacheid = CACHEID_VIPT_NONALIASING;
+                        arch = CPU_ARCH_ARMv6;
-                        if (cpu_has_aliasing_icache(CPU_ARCH_ARMv6))
+                        if (cachetype & (1 << 23))
-                                cacheid |= CACHEID_VIPT_I_ALIASING;
+                                cacheid = CACHEID_VIPT_ALIASING;
+                        else
+                                cacheid = CACHEID_VIPT_NONALIASING;
                }
+                if (cpu_has_aliasing_icache(arch))
+                        cacheid |= CACHEID_VIPT_I_ALIASING;
        } else {
                cacheid = CACHEID_VIVT;
        }
diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c
index 2c277d40cee6..01c186222f3b 100644
--- a/arch/arm/kernel/smp_twd.c
+++ b/arch/arm/kernel/smp_twd.c
@@ -137,8 +137,8 @@ void __cpuinit twd_timer_setup(struct clock_event_device *clk)
        clk->max_delta_ns = clockevent_delta2ns(0xffffffff, clk);
        clk->min_delta_ns = clockevent_delta2ns(0xf, clk);
+        clockevents_register_device(clk);
        /* Make sure our local interrupt controller has this enabled */
        gic_enable_ppi(clk->irq);
-        clockevents_register_device(clk);
 }
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index d522b47e30b5..6c8e3b5f669f 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -157,7 +157,7 @@ static struct clk_lookup periph_clocks_lookups[] = {
        CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
        CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
        CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
-        CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc1_clk),
+        CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
        CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
        CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
        CLKDEV_CON_DEV_ID("pclk", "ssc.2", &ssc2_clk),
diff --git a/arch/arm/mach-cns3xxx/include/mach/entry-macro.S b/arch/arm/mach-cns3xxx/include/mach/entry-macro.S
index 6bd83ed90afe..d87bfc397d39 100644
--- a/arch/arm/mach-cns3xxx/include/mach/entry-macro.S
+++ b/arch/arm/mach-cns3xxx/include/mach/entry-macro.S
@@ -8,7 +8,6 @@
 * published by the Free Software Foundation.
 */
-#include <mach/hardware.h>
 #include <asm/hardware/entry-macro-gic.S>
                .macro  disable_fiq
diff --git a/arch/arm/mach-cns3xxx/include/mach/system.h b/arch/arm/mach-cns3xxx/include/mach/system.h
index 58bb03ae3cf4..4f16c9b79f78 100644
--- a/arch/arm/mach-cns3xxx/include/mach/system.h
+++ b/arch/arm/mach-cns3xxx/include/mach/system.h
@@ -13,7 +13,6 @@
 #include <linux/io.h>
 #include <asm/proc-fns.h>
-#include <mach/hardware.h>
 static inline void arch_idle(void)
 {
diff --git a/arch/arm/mach-cns3xxx/include/mach/uncompress.h b/arch/arm/mach-cns3xxx/include/mach/uncompress.h
index de8ead9b91f7..a91b6058ab4f 100644
--- a/arch/arm/mach-cns3xxx/include/mach/uncompress.h
+++ b/arch/arm/mach-cns3xxx/include/mach/uncompress.h
@@ -8,7 +8,6 @@
 */
 #include <asm/mach-types.h>
-#include <mach/hardware.h>
 #include <mach/cns3xxx.h>
 #define AMBA_UART_DR(base)      (*(volatile unsigned char *)((base) + 0x00))
diff --git a/arch/arm/mach-cns3xxx/pcie.c b/arch/arm/mach-cns3xxx/pcie.c
index 06fd25d70aec..0f8fca48a5ed 100644
--- a/arch/arm/mach-cns3xxx/pcie.c
+++ b/arch/arm/mach-cns3xxx/pcie.c
@@ -49,7 +49,7 @@ static struct cns3xxx_pcie *sysdata_to_cnspci(void *sysdata)
        return &cns3xxx_pcie[root->domain];
 }
-static struct cns3xxx_pcie *pdev_to_cnspci(struct pci_dev *dev)
+static struct cns3xxx_pcie *pdev_to_cnspci(const struct pci_dev *dev)
 {
        return sysdata_to_cnspci(dev->sysdata);
 }
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index bd5394537c88..008d51407cd7 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -115,6 +115,32 @@ static struct spi_board_info da850evm_spi_info[] = {
        },
 };
+#ifdef CONFIG_MTD
+static void da850_evm_m25p80_notify_add(struct mtd_info *mtd)
+{
+        char *mac_addr = davinci_soc_info.emac_pdata->mac_addr;
+        size_t retlen;
+        if (!strcmp(mtd->name, "MAC-Address")) {
+                mtd->read(mtd, 0, ETH_ALEN, &retlen, mac_addr);
+                if (retlen == ETH_ALEN)
+                        pr_info("Read MAC addr from SPI Flash: %pM\n",
+                                mac_addr);
+        }
+}
+static struct mtd_notifier da850evm_spi_notifier = {
+        .add    = da850_evm_m25p80_notify_add,
+};
+static void da850_evm_setup_mac_addr(void)
+{
+        register_mtd_user(&da850evm_spi_notifier);
+}
+#else
+static void da850_evm_setup_mac_addr(void) { }
+#endif
 static struct mtd_partition da850_evm_norflash_partition[] = {
        {
                .name           = "bootloaders + env",
@@ -1244,6 +1270,8 @@ static __init void da850_evm_init(void)
        if (ret)
                pr_warning("da850_evm_init: sata registration failed: %d\n",
                                ret);
+        da850_evm_setup_mac_addr();
 }
 #ifdef CONFIG_SERIAL_8250_CONSOLE
diff --git a/arch/arm/mach-davinci/include/mach/psc.h b/arch/arm/mach-davinci/include/mach/psc.h
index 47fd0bc3d3e7..fa59c097223d 100644
--- a/arch/arm/mach-davinci/include/mach/psc.h
+++ b/arch/arm/mach-davinci/include/mach/psc.h
@@ -243,7 +243,7 @@
 #define PSC_STATE_DISABLE       2
 #define PSC_STATE_ENABLE        3
-#define MDSTAT_STATE_MASK       0x1f
+#define MDSTAT_STATE_MASK       0x3f
 #define MDCTL_FORCE             BIT(31)
 #ifndef __ASSEMBLER__
diff --git a/arch/arm/mach-davinci/sleep.S b/arch/arm/mach-davinci/sleep.S
index fb5e72b532b0..5f1e045a3ad1 100644
--- a/arch/arm/mach-davinci/sleep.S
+++ b/arch/arm/mach-davinci/sleep.S
@@ -217,7 +217,11 @@ ddr2clk_stop_done:
 ENDPROC(davinci_ddr_psc_config)
 CACHE_FLUSH:
-        .word   arm926_flush_kern_cache_all
+#ifdef CONFIG_CPU_V6
+        .word   v6_flush_kern_cache_all
+#else
+        .word   arm926_flush_kern_cache_all
+#endif
 ENTRY(davinci_cpu_suspend_sz)
        .word   . - davinci_cpu_suspend
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index 83dce859886d..a9e0dae86a26 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -158,7 +158,7 @@ void __init dove_spi0_init(void)
 void __init dove_spi1_init(void)
 {
-        orion_spi_init(DOVE_SPI1_PHYS_BASE, get_tclk());
+        orion_spi_1_init(DOVE_SPI1_PHYS_BASE, get_tclk());
 }
 /*****************************************************************************
diff --git a/arch/arm/mach-ep93xx/include/mach/ts72xx.h b/arch/arm/mach-ep93xx/include/mach/ts72xx.h
index 0eabec62cd9d..f1397a13e76b 100644
--- a/arch/arm/mach-ep93xx/include/mach/ts72xx.h
+++ b/arch/arm/mach-ep93xx/include/mach/ts72xx.h
@@ -6,7 +6,7 @@
 * TS72xx memory map:
 *
 * virt         phys            size
- * febff000     22000000        4K      model number register
+ * febff000     22000000        4K      model number register (bits 0-2)
 * febfe000     22400000        4K      options register
 * febfd000     22800000        4K      options register #2
 * febf9000     10800000        4K      TS-5620 RTC index register
@@ -20,6 +20,9 @@
 #define TS72XX_MODEL_TS7200             0x00
 #define TS72XX_MODEL_TS7250             0x01
 #define TS72XX_MODEL_TS7260             0x02
+#define TS72XX_MODEL_TS7300             0x03
+#define TS72XX_MODEL_TS7400             0x04
+#define TS72XX_MODEL_MASK               0x07
 #define TS72XX_OPTIONS_PHYS_BASE        0x22400000
@@ -51,19 +54,34 @@
 #ifndef __ASSEMBLY__
+static inline int ts72xx_model(void)
+{
+        return __raw_readb(TS72XX_MODEL_VIRT_BASE) & TS72XX_MODEL_MASK;
+}
 static inline int board_is_ts7200(void)
 {
-        return __raw_readb(TS72XX_MODEL_VIRT_BASE) == TS72XX_MODEL_TS7200;
+        return ts72xx_model() == TS72XX_MODEL_TS7200;
 }
 static inline int board_is_ts7250(void)
 {
-        return __raw_readb(TS72XX_MODEL_VIRT_BASE) == TS72XX_MODEL_TS7250;
+        return ts72xx_model() == TS72XX_MODEL_TS7250;
 }
 static inline int board_is_ts7260(void)
 {
-        return __raw_readb(TS72XX_MODEL_VIRT_BASE) == TS72XX_MODEL_TS7260;
+        return ts72xx_model() == TS72XX_MODEL_TS7260;
+}
+static inline int board_is_ts7300(void)
+{
+        return ts72xx_model()  == TS72XX_MODEL_TS7300;
+}
+static inline int board_is_ts7400(void)
+{
+        return ts72xx_model() == TS72XX_MODEL_TS7400;
 }
 static inline int is_max197_installed(void)
diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c
index 851dea018578..79d6cd0c8e7b 100644
--- a/arch/arm/mach-exynos4/clock.c
+++ b/arch/arm/mach-exynos4/clock.c
@@ -520,7 +520,7 @@ static struct clk init_clocks_off[] = {
                .ctrlbit        = (1 << 21),
        }, {
                .name           = "ac97",
-                .id             = -1,
+                .devname        = "samsung-ac97",
                .enable         = exynos4_clk_ip_peril_ctrl,
                .ctrlbit        = (1 << 27),
        }, {
@@ -1160,7 +1160,7 @@ void __init_or_cpufreq exynos4_setup_clocks(void)
        vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
        vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
-                                __raw_readl(S5P_VPLL_CON1), pll_4650);
+                                __raw_readl(S5P_VPLL_CON1), pll_4650c);
        clk_fout_apll.ops = &exynos4_fout_apll_ops;
        clk_fout_mpll.rate = mpll;
diff --git a/arch/arm/mach-exynos4/cpu.c b/arch/arm/mach-exynos4/cpu.c
index 2d8a40c9e6e5..746d6fc6d397 100644
--- a/arch/arm/mach-exynos4/cpu.c
+++ b/arch/arm/mach-exynos4/cpu.c
@@ -24,12 +24,13 @@
 #include <plat/exynos4.h>
 #include <plat/adc-core.h>
 #include <plat/sdhci.h>
-#include <plat/devs.h>
 #include <plat/fb-core.h>
 #include <plat/fimc-core.h>
 #include <plat/iic-core.h>
+#include <plat/reset.h>
 #include <mach/regs-irq.h>
+#include <mach/regs-pmu.h>
 extern int combiner_init(unsigned int combiner_nr, void __iomem *base,
                         unsigned int irq_start);
@@ -128,6 +129,11 @@ static void exynos4_idle(void)
        local_irq_enable();
 }
+static void exynos4_sw_reset(void)
+{
+        __raw_writel(0x1, S5P_SWRESET);
+}
 /*
 * exynos4_map_io
 *
@@ -241,5 +247,8 @@ int __init exynos4_init(void)
        /* set idle function */
        pm_idle = exynos4_idle;
+        /* set sw_reset function */
+        s5p_reset_hook = exynos4_sw_reset;
        return sysdev_register(&exynos4_sysdev);
 }
diff --git a/arch/arm/mach-exynos4/include/mach/irqs.h b/arch/arm/mach-exynos4/include/mach/irqs.h
index 934d2a493982..f8952f8f3757 100644
--- a/arch/arm/mach-exynos4/include/mach/irqs.h
+++ b/arch/arm/mach-exynos4/include/mach/irqs.h
@@ -80,9 +80,8 @@
 #define IRQ_HSMMC3              IRQ_SPI(76)
 #define IRQ_DWMCI               IRQ_SPI(77)
-#define IRQ_MIPICSI0            IRQ_SPI(78)
+#define IRQ_MIPI_CSIS0          IRQ_SPI(78)
+#define IRQ_MIPI_CSIS1          IRQ_SPI(80)
-#define IRQ_MIPICSI1            IRQ_SPI(80)
 #define IRQ_ONENAND_AUDI        IRQ_SPI(82)
 #define IRQ_ROTATOR             IRQ_SPI(83)
diff --git a/arch/arm/mach-exynos4/include/mach/regs-pmu.h b/arch/arm/mach-exynos4/include/mach/regs-pmu.h
index fa49bbb8e7b0..cdf9b47c303c 100644
--- a/arch/arm/mach-exynos4/include/mach/regs-pmu.h
+++ b/arch/arm/mach-exynos4/include/mach/regs-pmu.h
@@ -29,6 +29,8 @@
 #define S5P_USE_STANDBY_WFE1                    (1 << 25)
 #define S5P_USE_MASK                            ((0x3 << 16) | (0x3 << 24))
+#define S5P_SWRESET                             S5P_PMUREG(0x0400)
 #define S5P_WAKEUP_STAT                         S5P_PMUREG(0x0600)
 #define S5P_EINT_WAKEUP_MASK                    S5P_PMUREG(0x0604)
 #define S5P_WAKEUP_MASK                         S5P_PMUREG(0x0608)
diff --git a/arch/arm/mach-exynos4/irq-eint.c b/arch/arm/mach-exynos4/irq-eint.c
index 9d87d2ac7f68..badb8c66fc9b 100644
--- a/arch/arm/mach-exynos4/irq-eint.c
+++ b/arch/arm/mach-exynos4/irq-eint.c
@@ -23,6 +23,8 @@
 #include <mach/regs-gpio.h>
+#include <asm/mach/irq.h>
 static DEFINE_SPINLOCK(eint_lock);
 static unsigned int eint0_15_data[16];
@@ -184,8 +186,11 @@ static inline void exynos4_irq_demux_eint(unsigned int start)
 static void exynos4_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
 {
+        struct irq_chip *chip = irq_get_chip(irq);
+        chained_irq_enter(chip, desc);
        exynos4_irq_demux_eint(IRQ_EINT(16));
        exynos4_irq_demux_eint(IRQ_EINT(24));
+        chained_irq_exit(chip, desc);
 }
 static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
@@ -193,6 +198,7 @@ static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
        u32 *irq_data = irq_get_handler_data(irq);
        struct irq_chip *chip = irq_get_chip(irq);
+        chained_irq_enter(chip, desc);
        chip->irq_mask(&desc->irq_data);
        if (chip->irq_ack)
@@ -201,6 +207,7 @@ static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
        generic_handle_irq(*irq_data);
        chip->irq_unmask(&desc->irq_data);
+        chained_irq_exit(chip, desc);
 }
 int __init exynos4_init_irq_eint(void)
diff --git a/arch/arm/mach-exynos4/mach-universal_c210.c b/arch/arm/mach-exynos4/mach-universal_c210.c
index 0e280d12301e..b3b5d8911004 100644
--- a/arch/arm/mach-exynos4/mach-universal_c210.c
+++ b/arch/arm/mach-exynos4/mach-universal_c210.c
@@ -79,7 +79,7 @@ static struct s3c2410_uartcfg universal_uartcfgs[] __initdata = {
 };
 static struct regulator_consumer_supply max8952_consumer =
-        REGULATOR_SUPPLY("vddarm", NULL);
+        REGULATOR_SUPPLY("vdd_arm", NULL);
 static struct max8952_platform_data universal_max8952_pdata __initdata = {
        .gpio_vid0      = EXYNOS4_GPX0(3),
@@ -105,7 +105,7 @@ static struct max8952_platform_data universal_max8952_pdata __initdata = {
 };
 static struct regulator_consumer_supply lp3974_buck1_consumer =
-        REGULATOR_SUPPLY("vddint", NULL);
+        REGULATOR_SUPPLY("vdd_int", NULL);
 static struct regulator_consumer_supply lp3974_buck2_consumer =
        REGULATOR_SUPPLY("vddg3d", NULL);
diff --git a/arch/arm/mach-exynos4/mct.c b/arch/arm/mach-exynos4/mct.c
index 1ae059b7ad7b..ddd86864fb83 100644
--- a/arch/arm/mach-exynos4/mct.c
+++ b/arch/arm/mach-exynos4/mct.c
@@ -132,12 +132,18 @@ static cycle_t exynos4_frc_read(struct clocksource *cs)
        return ((cycle_t)hi << 32) | lo;
 }
+static void exynos4_frc_resume(struct clocksource *cs)
+{
+        exynos4_mct_frc_start(0, 0);
+}
 struct clocksource mct_frc = {
        .name           = "mct-frc",
        .rating         = 400,
        .read           = exynos4_frc_read,
        .mask           = CLOCKSOURCE_MASK(64),
        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
+        .resume         = exynos4_frc_resume,
 };
 static void __init exynos4_clocksource_init(void)
@@ -389,9 +395,11 @@ static void exynos4_mct_tick_init(struct clock_event_device *evt)
 }
 /* Setup the local clock events for a CPU */
-void __cpuinit local_timer_setup(struct clock_event_device *evt)
+int __cpuinit local_timer_setup(struct clock_event_device *evt)
 {
        exynos4_mct_tick_init(evt);
+        return 0;
 }
 int local_timer_ack(void)
diff --git a/arch/arm/mach-exynos4/platsmp.c b/arch/arm/mach-exynos4/platsmp.c
index 7c2282c6ba81..df6ef1b2f98b 100644
--- a/arch/arm/mach-exynos4/platsmp.c
+++ b/arch/arm/mach-exynos4/platsmp.c
@@ -106,6 +106,8 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
         */
        spin_lock(&boot_lock);
        spin_unlock(&boot_lock);
+        set_cpu_online(cpu, true);
 }
 int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
diff --git a/arch/arm/mach-exynos4/setup-keypad.c b/arch/arm/mach-exynos4/setup-keypad.c
index 1ee0ebff111f..7862bfb5933d 100644
--- a/arch/arm/mach-exynos4/setup-keypad.c
+++ b/arch/arm/mach-exynos4/setup-keypad.c
@@ -19,15 +19,16 @@ void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols)
        if (rows > 8) {
                /* Set all the necessary GPX2 pins: KP_ROW[0~7] */
-                s3c_gpio_cfgrange_nopull(EXYNOS4_GPX2(0), 8, S3C_GPIO_SFN(3));
+                s3c_gpio_cfgall_range(EXYNOS4_GPX2(0), 8, S3C_GPIO_SFN(3),
+                                        S3C_GPIO_PULL_UP);
                /* Set all the necessary GPX3 pins: KP_ROW[8~] */
-                s3c_gpio_cfgrange_nopull(EXYNOS4_GPX3(0), (rows - 8),
+                s3c_gpio_cfgall_range(EXYNOS4_GPX3(0), (rows - 8),
-                                         S3C_GPIO_SFN(3));
+                                         S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
        } else {
                /* Set all the necessary GPX2 pins: KP_ROW[x] */
-                s3c_gpio_cfgrange_nopull(EXYNOS4_GPX2(0), rows,
+                s3c_gpio_cfgall_range(EXYNOS4_GPX2(0), rows, S3C_GPIO_SFN(3),
-                                         S3C_GPIO_SFN(3));
+                                        S3C_GPIO_PULL_UP);
        }
        /* Set all the necessary GPX1 pins to special-function 3: KP_COL[x] */
diff --git a/arch/arm/mach-exynos4/setup-usb-phy.c b/arch/arm/mach-exynos4/setup-usb-phy.c
index 0883c1b824b9..39aca045f660 100644
--- a/arch/arm/mach-exynos4/setup-usb-phy.c
+++ b/arch/arm/mach-exynos4/setup-usb-phy.c
@@ -82,7 +82,7 @@ static int exynos4_usb_phy1_init(struct platform_device *pdev)
        rstcon &= ~(HOST_LINK_PORT_SWRST_MASK | PHY1_SWRST_MASK);
        writel(rstcon, EXYNOS4_RSTCON);
-        udelay(50);
+        udelay(80);
        clk_disable(otg_clk);
        clk_put(otg_clk);
diff --git a/arch/arm/mach-footbridge/Kconfig b/arch/arm/mach-footbridge/Kconfig
index dc26fff22cf0..c8e7afcf14ec 100644
--- a/arch/arm/mach-footbridge/Kconfig
+++ b/arch/arm/mach-footbridge/Kconfig
@@ -62,6 +62,7 @@ config ARCH_EBSA285_HOST
 config ARCH_NETWINDER
        bool "NetWinder"
        select CLKSRC_I8253
+        select CLKEVT_I8253
        select FOOTBRIDGE_HOST
        select ISA
        select ISA_DMA
diff --git a/arch/arm/mach-footbridge/dc21285.c b/arch/arm/mach-footbridge/dc21285.c
index 1331fff51ae2..18c32a5541d9 100644
--- a/arch/arm/mach-footbridge/dc21285.c
+++ b/arch/arm/mach-footbridge/dc21285.c
@@ -18,6 +18,7 @@
 #include <linux/irq.h>
 #include <linux/io.h>
 #include <linux/spinlock.h>
+#include <video/vga.h>
 #include <asm/irq.h>
 #include <asm/system.h>
diff --git a/arch/arm/mach-imx/mach-cpuimx27.c b/arch/arm/mach-imx/mach-cpuimx27.c
index 87887ac5806b..f851fe903687 100644
--- a/arch/arm/mach-imx/mach-cpuimx27.c
+++ b/arch/arm/mach-imx/mach-cpuimx27.c
@@ -310,7 +310,7 @@ static struct sys_timer eukrea_cpuimx27_timer = {
        .init = eukrea_cpuimx27_timer_init,
 };
-MACHINE_START(CPUIMX27, "EUKREA CPUIMX27")
+MACHINE_START(EUKREA_CPUIMX27, "EUKREA CPUIMX27")
        .boot_params = MX27_PHYS_OFFSET + 0x100,
        .map_io = mx27_map_io,
        .init_early = imx27_init_early,
diff --git a/arch/arm/mach-imx/mach-cpuimx35.c b/arch/arm/mach-imx/mach-cpuimx35.c
index f39a478ba1a6..4bd083ba9af2 100644
--- a/arch/arm/mach-imx/mach-cpuimx35.c
+++ b/arch/arm/mach-imx/mach-cpuimx35.c
@@ -192,7 +192,7 @@ struct sys_timer eukrea_cpuimx35_timer = {
        .init   = eukrea_cpuimx35_timer_init,
 };
-MACHINE_START(EUKREA_CPUIMX35, "Eukrea CPUIMX35")
+MACHINE_START(EUKREA_CPUIMX35SD, "Eukrea CPUIMX35")
        /* Maintainer: Eukrea Electromatique */
        .boot_params = MX3x_PHYS_OFFSET + 0x100,
        .map_io = mx35_map_io,
diff --git a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
index da36da52969d..2442d5da883d 100644
--- a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
+++ b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
@@ -161,7 +161,7 @@ static struct sys_timer eukrea_cpuimx25_timer = {
        .init   = eukrea_cpuimx25_timer_init,
 };
-MACHINE_START(EUKREA_CPUIMX25, "Eukrea CPUIMX25")
+MACHINE_START(EUKREA_CPUIMX25SD, "Eukrea CPUIMX25")
        /* Maintainer: Eukrea Electromatique */
        .boot_params = MX25_PHYS_OFFSET + 0x100,
        .map_io = mx25_map_io,
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
index 2fbbdd5eac35..8cdc730dcb3a 100644
--- a/arch/arm/mach-integrator/integrator_ap.c
+++ b/arch/arm/mach-integrator/integrator_ap.c
@@ -32,6 +32,7 @@
 #include <linux/interrupt.h>
 #include <linux/io.h>
 #include <linux/mtd/physmap.h>
+#include <video/vga.h>
 #include <mach/hardware.h>
 #include <mach/platform.h>
@@ -154,6 +155,7 @@ static struct map_desc ap_io_desc[] __initdata = {
 static void __init ap_map_io(void)
 {
        iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc));
+        vga_base = PCI_MEMORY_VADDR;
 }
 #define INTEGRATOR_SC_VALID_INT 0x003fffff
@@ -337,15 +339,15 @@ static unsigned long timer_reload;
 static void integrator_clocksource_init(u32 khz)
 {
        void __iomem *base = (void __iomem *)TIMER2_VA_BASE;
-        u32 ctrl = TIMER_CTRL_ENABLE;
+        u32 ctrl = TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC;
        if (khz >= 1500) {
                khz /= 16;
-                ctrl = TIMER_CTRL_DIV16;
+                ctrl |= TIMER_CTRL_DIV16;
        }
-        writel(ctrl, base + TIMER_CTRL);
        writel(0xffff, base + TIMER_LOAD);
+        writel(ctrl, base + TIMER_CTRL);
        clocksource_mmio_init(base + TIMER_VALUE, "timer2",
                khz * 1000, 200, 16, clocksource_mmio_readl_down);
diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c
index dd56bfb351e3..11b86e5b71c2 100644
--- a/arch/arm/mach-integrator/pci_v3.c
+++ b/arch/arm/mach-integrator/pci_v3.c
@@ -27,7 +27,6 @@
 #include <linux/spinlock.h>
 #include <linux/init.h>
 #include <linux/io.h>
-#include <video/vga.h>
 #include <mach/hardware.h>
 #include <mach/platform.h>
@@ -505,7 +504,6 @@ void __init pci_v3_preinit(void)
        pcibios_min_io = 0x6000;
        pcibios_min_mem = 0x00100000;
-        vga_base = PCI_MEMORY_VADDR;
        /*
         * Hook in our fault handler for PCI errors
diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile
index 5b114d1558c8..11c85cd2731a 100644
--- a/arch/arm/mach-omap1/Makefile
+++ b/arch/arm/mach-omap1/Makefile
@@ -4,7 +4,7 @@
 # Common support
 obj-y := io.o id.o sram.o time.o irq.o mux.o flash.o serial.o devices.o dma.o
-obj-y += clock.o clock_data.o opp_data.o reset.o pm_bus.o
+obj-y += clock.o clock_data.o opp_data.o reset.o pm_bus.o timer.o
 obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
diff --git a/arch/arm/mach-omap1/timer.c b/arch/arm/mach-omap1/timer.c
new file mode 100644
index 000000000000..6e90665a7c47
--- /dev/null
+++ b/arch/arm/mach-omap1/timer.c
@@ -0,0 +1,173 @@
+/**
+ * OMAP1 Dual-Mode Timers - platform device registration
+ *
+ * Contains first level initialization routines which internally
+ * generates timer device information and registers with linux
+ * device model. It also has low level function to chnage the timer
+ * input clock source.
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Tarun Kanti DebBarma <tarun.kanti@ti.com>
+ * Thara Gopinath <thara@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+#include <mach/irqs.h>
+#include <plat/dmtimer.h>
+#define OMAP1610_GPTIMER1_BASE          0xfffb1400
+#define OMAP1610_GPTIMER2_BASE          0xfffb1c00
+#define OMAP1610_GPTIMER3_BASE          0xfffb2400
+#define OMAP1610_GPTIMER4_BASE          0xfffb2c00
+#define OMAP1610_GPTIMER5_BASE          0xfffb3400
+#define OMAP1610_GPTIMER6_BASE          0xfffb3c00
+#define OMAP1610_GPTIMER7_BASE          0xfffb7400
+#define OMAP1610_GPTIMER8_BASE          0xfffbd400
+#define OMAP1_DM_TIMER_COUNT            8
+static int omap1_dm_timer_set_src(struct platform_device *pdev,
+                                int source)
+{
+        int n = (pdev->id - 1) << 1;
+        u32 l;
+        l = __raw_readl(MOD_CONF_CTRL_1) & ~(0x03 << n);
+        l |= source << n;
+        __raw_writel(l, MOD_CONF_CTRL_1);
+        return 0;
+}
+int __init omap1_dm_timer_init(void)
+{
+        int i;
+        int ret;
+        struct dmtimer_platform_data *pdata;
+        struct platform_device *pdev;
+        if (!cpu_is_omap16xx())
+                return 0;
+        for (i = 1; i <= OMAP1_DM_TIMER_COUNT; i++) {
+                struct resource res[2];
+                u32 base, irq;
+                switch (i) {
+                case 1:
+                        base = OMAP1610_GPTIMER1_BASE;
+                        irq = INT_1610_GPTIMER1;
+                        break;
+                case 2:
+                        base = OMAP1610_GPTIMER2_BASE;
+                        irq = INT_1610_GPTIMER2;
+                        break;
+                case 3:
+                        base = OMAP1610_GPTIMER3_BASE;
+                        irq = INT_1610_GPTIMER3;
+                        break;
+                case 4:
+                        base = OMAP1610_GPTIMER4_BASE;
+                        irq = INT_1610_GPTIMER4;
+                        break;
+                case 5:
+                        base = OMAP1610_GPTIMER5_BASE;
+                        irq = INT_1610_GPTIMER5;
+                        break;
+                case 6:
+                        base = OMAP1610_GPTIMER6_BASE;
+                        irq = INT_1610_GPTIMER6;
+                        break;
+                case 7:
+                        base = OMAP1610_GPTIMER7_BASE;
+                        irq = INT_1610_GPTIMER7;
+                        break;
+                case 8:
+                        base = OMAP1610_GPTIMER8_BASE;
+                        irq = INT_1610_GPTIMER8;
+                        break;
+                default:
+                        /*
+                         * not supposed to reach here.
+                         * this is to remove warning.
+                         */
+                        return -EINVAL;
+                }
+                pdev = platform_device_alloc("omap_timer", i);
+                if (!pdev) {
+                        pr_err("%s: Failed to device alloc for dmtimer%d\n",
+                                __func__, i);
+                        return -ENOMEM;
+                }
+                memset(res, 0, 2 * sizeof(struct resource));
+                res[0].start = base;
+                res[0].end = base + 0x46;
+                res[0].flags = IORESOURCE_MEM;
+                res[1].start = irq;
+                res[1].end = irq;
+                res[1].flags = IORESOURCE_IRQ;
+                ret = platform_device_add_resources(pdev, res,
+                                ARRAY_SIZE(res));
+                if (ret) {
+                        dev_err(&pdev->dev, "%s: Failed to add resources.\n",
+                                __func__);
+                        goto err_free_pdev;
+                }
+                pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
+                if (!pdata) {
+                        dev_err(&pdev->dev, "%s: Failed to allocate pdata.\n",
+                                __func__);
+                        ret = -ENOMEM;
+                        goto err_free_pdata;
+                }
+                pdata->set_timer_src = omap1_dm_timer_set_src;
+                pdata->needs_manual_reset = 1;
+                ret = platform_device_add_data(pdev, pdata, sizeof(*pdata));
+                if (ret) {
+                        dev_err(&pdev->dev, "%s: Failed to add platform data.\n",
+                                __func__);
+                        goto err_free_pdata;
+                }
+                ret = platform_device_add(pdev);
+                if (ret) {
+                        dev_err(&pdev->dev, "%s: Failed to add platform device.\n",
+                                __func__);
+                        goto err_free_pdata;
+                }
+                dev_dbg(&pdev->dev, " Registered.\n");
+        }
+        return 0;
+err_free_pdata:
+        kfree(pdata);
+err_free_pdev:
+        platform_device_unregister(pdev);
+        return ret;
+}
+arch_initcall(omap1_dm_timer_init);
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index f34336560437..cd45c045ab8c 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -116,9 +116,12 @@ obj-$(CONFIG_ARCH_OMAP4)		+= $(powerdomain-common) \
 obj-$(CONFIG_ARCH_OMAP2)                += clockdomain.o \
                                           clockdomain2xxx_3xxx.o \
                                           clockdomains2xxx_3xxx_data.o
+obj-$(CONFIG_SOC_OMAP2420)              += clockdomains2420_data.o
+obj-$(CONFIG_SOC_OMAP2430)              += clockdomains2430_data.o
 obj-$(CONFIG_ARCH_OMAP3)                += clockdomain.o \
                                           clockdomain2xxx_3xxx.o \
-                                           clockdomains2xxx_3xxx_data.o
+                                           clockdomains2xxx_3xxx_data.o \
+                                           clockdomains3xxx_data.o
 obj-$(CONFIG_ARCH_OMAP4)                += clockdomain.o \
                                           clockdomain44xx.o \
                                           clockdomains44xx_data.o
@@ -185,78 +188,66 @@ endif
 # Specific board support
 obj-$(CONFIG_MACH_OMAP_GENERIC)         += board-generic.o
 obj-$(CONFIG_MACH_OMAP_H4)              += board-h4.o
-obj-$(CONFIG_MACH_OMAP_2430SDP)         += board-2430sdp.o \
+obj-$(CONFIG_MACH_OMAP_2430SDP)         += board-2430sdp.o
-                                           hsmmc.o
 obj-$(CONFIG_MACH_OMAP_APOLLON)         += board-apollon.o
-obj-$(CONFIG_MACH_OMAP3_BEAGLE)         += board-omap3beagle.o \
+obj-$(CONFIG_MACH_OMAP3_BEAGLE)         += board-omap3beagle.o
-                                           hsmmc.o
+obj-$(CONFIG_MACH_DEVKIT8000)           += board-devkit8000.o
-obj-$(CONFIG_MACH_DEVKIT8000)           += board-devkit8000.o \
+obj-$(CONFIG_MACH_OMAP_LDP)             += board-ldp.o
-                                           hsmmc.o
+obj-$(CONFIG_MACH_OMAP3530_LV_SOM)      += board-omap3logic.o
-obj-$(CONFIG_MACH_OMAP_LDP)             += board-ldp.o \
+obj-$(CONFIG_MACH_OMAP3_TORPEDO)        += board-omap3logic.o
-                                           board-flash.o \
+obj-$(CONFIG_MACH_ENCORE)               += board-omap3encore.o
-                                           hsmmc.o
+obj-$(CONFIG_MACH_OVERO)                += board-overo.o
-obj-$(CONFIG_MACH_OMAP3530_LV_SOM)      += board-omap3logic.o \
+obj-$(CONFIG_MACH_OMAP3EVM)             += board-omap3evm.o
-                                           hsmmc.o
+obj-$(CONFIG_MACH_OMAP3_PANDORA)        += board-omap3pandora.o
-obj-$(CONFIG_MACH_OMAP3_TORPEDO)        += board-omap3logic.o \
+obj-$(CONFIG_MACH_OMAP_3430SDP)         += board-3430sdp.o
-                                           hsmmc.o
-obj-$(CONFIG_MACH_OVERO)                += board-overo.o \
-                                           hsmmc.o
-obj-$(CONFIG_MACH_OMAP3EVM)             += board-omap3evm.o \
-                                           hsmmc.o
-obj-$(CONFIG_MACH_OMAP3_PANDORA)        += board-omap3pandora.o \
-                                           hsmmc.o
-obj-$(CONFIG_MACH_OMAP_3430SDP)         += board-3430sdp.o \
-                                           hsmmc.o \
-                                           board-flash.o
 obj-$(CONFIG_MACH_NOKIA_N8X0)           += board-n8x0.o
 obj-$(CONFIG_MACH_NOKIA_RM680)          += board-rm680.o \
-                                           sdram-nokia.o \
+                                           sdram-nokia.o
-                                           hsmmc.o
 obj-$(CONFIG_MACH_NOKIA_RX51)           += board-rx51.o \
                                           sdram-nokia.o \
                                           board-rx51-peripherals.o \
-                                           board-rx51-video.o \
+                                           board-rx51-video.o
-                                           hsmmc.o
 obj-$(CONFIG_MACH_OMAP_ZOOM2)           += board-zoom.o \
                                           board-zoom-peripherals.o \
                                           board-zoom-display.o \
-                                           board-flash.o \
-                                           hsmmc.o \
                                           board-zoom-debugboard.o
 obj-$(CONFIG_MACH_OMAP_ZOOM3)           += board-zoom.o \
                                           board-zoom-peripherals.o \
                                           board-zoom-display.o \
-                                           board-flash.o \
-                                           hsmmc.o \
                                           board-zoom-debugboard.o
 obj-$(CONFIG_MACH_OMAP_3630SDP)         += board-3630sdp.o \
                                           board-zoom-peripherals.o \
-                                           board-zoom-display.o \
+                                           board-zoom-display.o
-                                           board-flash.o \
+obj-$(CONFIG_MACH_CM_T35)               += board-cm-t35.o
-                                           hsmmc.o
-obj-$(CONFIG_MACH_CM_T35)               += board-cm-t35.o \
-                                           hsmmc.o
 obj-$(CONFIG_MACH_CM_T3517)             += board-cm-t3517.o
-obj-$(CONFIG_MACH_IGEP0020)             += board-igep0020.o \
+obj-$(CONFIG_MACH_IGEP0020)             += board-igep0020.o
-                                           hsmmc.o
+obj-$(CONFIG_MACH_OMAP3_TOUCHBOOK)      += board-omap3touchbook.o
-obj-$(CONFIG_MACH_OMAP3_TOUCHBOOK)      += board-omap3touchbook.o \
-                                           hsmmc.o
 obj-$(CONFIG_MACH_OMAP_4430SDP)         += board-4430sdp.o \
-                                           hsmmc.o \
                                           omap_phy_internal.o
 obj-$(CONFIG_MACH_OMAP4_PANDA)          += board-omap4panda.o \
-                                           hsmmc.o \
+                                           omap_phy_internal.o
+obj-$(CONFIG_MACH_PCM049)               += board-omap4pcm049.o \
                                           omap_phy_internal.o
 obj-$(CONFIG_MACH_OMAP3517EVM)          += board-am3517evm.o \
-                                           omap_phy_internal.o \
+                                           omap_phy_internal.o
 obj-$(CONFIG_MACH_CRANEBOARD)           += board-am3517crane.o
-obj-$(CONFIG_MACH_SBC3530)              += board-omap3stalker.o \
+obj-$(CONFIG_MACH_SBC3530)              += board-omap3stalker.o
-                                           hsmmc.o
 obj-$(CONFIG_MACH_TI8168EVM)            += board-ti8168evm.o
 # Platform specific device init code
+omap-flash-$(CONFIG_MTD_NAND_OMAP2)     := board-flash.o
+omap-flash-$(CONFIG_MTD_ONENAND_OMAP2)  := board-flash.o
+obj-y                                   += $(omap-flash-y) $(omap-flash-m)
+omap-hsmmc-$(CONFIG_MMC_OMAP_HS)        := hsmmc.o
+obj-y                                   += $(omap-hsmmc-m) $(omap-hsmmc-y)
 usbfs-$(CONFIG_ARCH_OMAP_OTG)           := usb-fs.o
 obj-y                                   += $(usbfs-m) $(usbfs-y)
 obj-y                                   += usb-musb.o
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index 2028464cf5b9..618216c8f742 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -141,12 +141,6 @@ static struct omap_board_config_kernel sdp2430_config[] __initdata = {
        {OMAP_TAG_LCD, &sdp2430_lcd_config},
 };
-static void __init omap_2430sdp_init_early(void)
-{
-        omap2_init_common_infrastructure();
-        omap2_init_common_devices(NULL, NULL);
-}
 static struct regulator_consumer_supply sdp2430_vmmc1_supplies[] = {
        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
 };
@@ -235,6 +229,7 @@ static void __init omap_2430sdp_init(void)
        platform_add_devices(sdp2430_devices, ARRAY_SIZE(sdp2430_devices));
        omap_serial_init();
+        omap_sdrc_init(NULL, NULL);
        omap2_hsmmc_init(mmc);
        omap2_usbfs_init(&sdp2430_usb_config);
@@ -259,7 +254,7 @@ MACHINE_START(OMAP_2430SDP, "OMAP2430 sdp2430 board")
        .boot_params    = 0x80000100,
        .reserve        = omap_reserve,
        .map_io         = omap_2430sdp_map_io,
-        .init_early     = omap_2430sdp_init_early,
+        .init_early     = omap2430_init_early,
        .init_irq       = omap2_init_irq,
        .init_machine   = omap_2430sdp_init,
        .timer          = &omap2_timer,
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index bd600cfb7f80..9bb48eaa4381 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -225,12 +225,6 @@ static struct omap_dss_board_info sdp3430_dss_data = {
 static struct omap_board_config_kernel sdp3430_config[] __initdata = {
 };
-static void __init omap_3430sdp_init_early(void)
-{
-        omap2_init_common_infrastructure();
-        omap2_init_common_devices(hyb18m512160af6_sdrc_params, NULL);
-}
 static struct omap2_hsmmc_info mmc[] = {
        {
                .mmc            = 1,
@@ -719,6 +713,7 @@ static void __init omap_3430sdp_init(void)
                gpio_pendown = SDP3430_TS_GPIO_IRQ_SDPV1;
        omap_ads7846_init(1, gpio_pendown, 310, NULL);
        board_serial_init();
+        omap_sdrc_init(hyb18m512160af6_sdrc_params, NULL);
        usb_musb_init(NULL);
        board_smc91x_init();
        board_flash_init(sdp_flash_partitions, chip_sel_3430, 0);
@@ -732,7 +727,7 @@ MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board")
        .boot_params    = 0x80000100,
        .reserve        = omap_reserve,
        .map_io         = omap3_map_io,
-        .init_early     = omap_3430sdp_init_early,
+        .init_early     = omap3430_init_early,
        .init_irq       = omap3_init_irq,
        .init_machine   = omap_3430sdp_init,
        .timer          = &omap3_timer,
diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c
index e4f37b57a0c4..94febc85d805 100644
--- a/arch/arm/mach-omap2/board-3630sdp.c
+++ b/arch/arm/mach-omap2/board-3630sdp.c
@@ -70,13 +70,6 @@ static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
 static struct omap_board_config_kernel sdp_config[] __initdata = {
 };
-static void __init omap_sdp_init_early(void)
-{
-        omap2_init_common_infrastructure();
-        omap2_init_common_devices(h8mbx00u0mer0em_sdrc_params,
-                                  h8mbx00u0mer0em_sdrc_params);
-}
 #ifdef CONFIG_OMAP_MUX
 static struct omap_board_mux board_mux[] __initdata = {
        { .reg_offset = OMAP_MUX_TERMINATOR },
@@ -207,6 +200,8 @@ static void __init omap_sdp_init(void)
        omap_board_config = sdp_config;
        omap_board_config_size = ARRAY_SIZE(sdp_config);
        zoom_peripherals_init();
+        omap_sdrc_init(h8mbx00u0mer0em_sdrc_params,
+                                  h8mbx00u0mer0em_sdrc_params);
        zoom_display_init();
        board_smc91x_init();
        board_flash_init(sdp_flash_partitions, chip_sel_sdp, NAND_BUSWIDTH_16);
@@ -218,7 +213,7 @@ MACHINE_START(OMAP_3630SDP, "OMAP 3630SDP board")
        .boot_params    = 0x80000100,
        .reserve        = omap_reserve,
        .map_io         = omap3_map_io,
-        .init_early     = omap_sdp_init_early,
+        .init_early     = omap3630_init_early,
        .init_irq       = omap3_init_irq,
        .init_machine   = omap_sdp_init,
        .timer          = &omap3_timer,
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index c7cef44c75d4..ab19d305f61e 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -389,12 +389,6 @@ static struct omap_board_config_kernel sdp4430_config[] __initdata = {
        { OMAP_TAG_LCD,         &sdp4430_lcd_config },
 };
-static void __init omap_4430sdp_init_early(void)
-{
-        omap2_init_common_infrastructure();
-        omap2_init_common_devices(NULL, NULL);
-}
 static struct omap_musb_board_data musb_board_data = {
        .interface_type         = MUSB_INTERFACE_UTMI,
        .mode                   = MUSB_OTG,
@@ -809,6 +803,7 @@ static void __init omap_4430sdp_init(void)
        omap_sfh7741prox_init();
        platform_add_devices(sdp4430_devices, ARRAY_SIZE(sdp4430_devices));
        board_serial_init();
+        omap_sdrc_init(NULL, NULL);
        omap4_sdp4430_wifi_init();
        omap4_twl6030_hsmmc_init(mmc);
@@ -841,7 +836,7 @@ MACHINE_START(OMAP_4430SDP, "OMAP4430 4430SDP board")
        .boot_params    = 0x80000100,
        .reserve        = omap_reserve,
        .map_io         = omap_4430sdp_map_io,
-        .init_early     = omap_4430sdp_init_early,
+        .init_early     = omap4430_init_early,
        .init_irq       = gic_init_irq,
        .init_machine   = omap_4430sdp_init,
        .timer          = &omap4_timer,
diff --git a/arch/arm/mach-omap2/board-am3517crane.c b/arch/arm/mach-omap2/board-am3517crane.c
index 933e9353cb37..9e1b2c248328 100644
--- a/arch/arm/mach-omap2/board-am3517crane.c
+++ b/arch/arm/mach-omap2/board-am3517crane.c
@@ -47,12 +47,6 @@ static struct omap_board_mux board_mux[] __initdata = {
 };
 #endif
-static void __init am3517_crane_init_early(void)
-{
-        omap2_init_common_infrastructure();
-        omap2_init_common_devices(NULL, NULL);
-}
 static struct usbhs_omap_board_data usbhs_bdata __initdata = {
        .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
        .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
@@ -70,6 +64,7 @@ static void __init am3517_crane_init(void)
        omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
        omap_serial_init();
+        omap_sdrc_init(NULL, NULL);
        omap_board_config = am3517_crane_config;
        omap_board_config_size = ARRAY_SIZE(am3517_crane_config);
@@ -101,7 +96,7 @@ MACHINE_START(CRANEBOARD, "AM3517/05 CRANEBOARD")
        .boot_params    = 0x80000100,
        .reserve        = omap_reserve,
        .map_io         = omap3_map_io,
-        .init_early     = am3517_crane_init_early,
+        .init_early     = am35xx_init_early,
        .init_irq       = omap3_init_irq,
        .init_machine   = am3517_crane_init,
        .timer          = &omap3_timer,
diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
index f3006c304150..7d842940c252 100644
--- a/arch/arm/mach-omap2/board-am3517evm.c
+++ b/arch/arm/mach-omap2/board-am3517evm.c
@@ -362,11 +362,6 @@ static struct omap_dss_board_info am3517_evm_dss_data = {
 /*
 * Board initialization
 */
-static void __init am3517_evm_init_early(void)
-{
-        omap2_init_common_infrastructure();
-        omap2_init_common_devices(NULL, NULL);
-}
 static struct omap_musb_board_data musb_board_data = {
        .interface_type         = MUSB_INTERFACE_ULPI,
@@ -469,6 +464,7 @@ static void __init am3517_evm_init(void)
        am3517_evm_i2c_init();
        omap_display_init(&am3517_evm_dss_data);
        omap_serial_init();
+        omap_sdrc_init(NULL, NULL);
        /* Configure GPIO for EHCI port */
        omap_mux_init_gpio(57, OMAP_PIN_OUTPUT);
@@ -493,7 +489,7 @@ MACHINE_START(OMAP3517EVM, "OMAP3517/AM3517 EVM")
        .boot_params    = 0x80000100,
        .reserve        = omap_reserve,
        .map_io         = omap3_map_io,
-        .init_early     = am3517_evm_init_early,
+        .init_early     = am35xx_init_early,
        .init_irq       = omap3_init_irq,
        .init_machine   = am3517_evm_init,
        .timer          = &omap3_timer,
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index 70211703ff9f..cf546f86014e 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -273,12 +273,6 @@ static struct omap_board_config_kernel apollon_config[] __initdata = {
        { OMAP_TAG_LCD,         &apollon_lcd_config },
 };
-static void __init omap_apollon_init_early(void)
-{
-        omap2_init_common_infrastructure();
-        omap2_init_common_devices(NULL, NULL);
-}
 static struct gpio apollon_gpio_leds[] __initdata = {
        { LED0_GPIO13, GPIOF_OUT_INIT_LOW, "LED0" }, /* LED0 - AA10 */
        { LED1_GPIO14, GPIOF_OUT_INIT_LOW, "LED1" }, /* LED1 - AA6  */
@@ -340,6 +334,7 @@ static void __init omap_apollon_init(void)
         */
        platform_add_devices(apollon_devices, ARRAY_SIZE(apollon_devices));
        omap_serial_init();
+        omap_sdrc_init(NULL, NULL);
 }
 static void __init omap_apollon_map_io(void)
@@ -353,7 +348,7 @@ MACHINE_START(OMAP_APOLLON, "OMAP24xx Apollon")
        .boot_params    = 0x80000100,
        .reserve        = omap_reserve,
        .map_io         = omap_apollon_map_io,
-        .init_early     = omap_apollon_init_early,
+        .init_early     = omap2420_init_early,
        .init_irq       = omap2_init_irq,
        .init_machine   = omap_apollon_init,
        .timer          = &omap2_timer,
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index 3af8aab435b5..e15d39bffe79 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -471,13 +471,6 @@ static void __init cm_t35_init_i2c(void)
        omap3_pmic_init("tps65930", &cm_t35_twldata);
 }
-static void __init cm_t35_init_early(void)
-{
-        omap2_init_common_infrastructure();
-        omap2_init_common_devices(mt46h32m32lf6_sdrc_params,
-                             mt46h32m32lf6_sdrc_params);
-}
 #ifdef CONFIG_OMAP_MUX
 static struct omap_board_mux board_mux[] __initdata = {
        /* nCS and IRQ for CM-T35 ethernet */
@@ -610,6 +603,8 @@ static void __init cm_t3x_common_init(void)
        omap_board_config_size = ARRAY_SIZE(cm_t35_config);
        omap3_mux_init(board_mux, OMAP_PACKAGE_CUS);
        omap_serial_init();
+        omap_sdrc_init(mt46h32m32lf6_sdrc_params,
+                             mt46h32m32lf6_sdrc_params);
        cm_t35_init_i2c();
        omap_ads7846_init(1, CM_T35_GPIO_PENDOWN, 0, NULL);
        cm_t35_init_ethernet();
@@ -637,7 +632,7 @@ MACHINE_START(CM_T35, "Compulab CM-T35")
        .boot_params    = 0x80000100,
        .reserve        = omap_reserve,
        .map_io         = omap3_map_io,
-        .init_early     = cm_t35_init_early,
+        .init_early     = omap35xx_init_early,
        .init_irq       = omap3_init_irq,
        .init_machine   = cm_t35_init,
        .timer          = &omap3_timer,
@@ -647,7 +642,7 @@ MACHINE_START(CM_T3730, "Compulab CM-T3730")
        .boot_params    = 0x80000100,
        .reserve        = omap_reserve,
        .map_io         = omap3_map_io,
-        .init_early     = cm_t35_init_early,
+        .init_early     = omap3630_init_early,
        .init_irq       = omap3_init_irq,
        .init_machine   = cm_t3730_init,
        .timer          = &omap3_timer,
diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c
index 05c72f4c1b57..867bf671719c 100644
--- a/arch/arm/mach-omap2/board-cm-t3517.c
+++ b/arch/arm/mach-omap2/board-cm-t3517.c
@@ -251,12 +251,6 @@ static inline void cm_t3517_init_nand(void) {}
 static struct omap_board_config_kernel cm_t3517_config[] __initdata = {
 };
-static void __init cm_t3517_init_early(void)
-{
-        omap2_init_common_infrastructure();
-        omap2_init_common_devices(NULL, NULL);
-}
 #ifdef CONFIG_OMAP_MUX
 static struct omap_board_mux board_mux[] __initdata = {
        /* GPIO186 - Green LED */
@@ -289,6 +283,7 @@ static void __init cm_t3517_init(void)
 {
        omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
        omap_serial_init();
+        omap_sdrc_init(NULL, NULL);
        omap_board_config = cm_t3517_config;
        omap_board_config_size = ARRAY_SIZE(cm_t3517_config);
        cm_t3517_init_leds();
@@ -302,7 +297,7 @@ MACHINE_START(CM_T3517, "Compulab CM-T3517")
        .boot_params    = 0x80000100,
        .reserve        = omap_reserve,
        .map_io         = omap3_map_io,
-        .init_early     = cm_t3517_init_early,
+        .init_early     = am35xx_init_early,
        .init_irq       = omap3_init_irq,
        .init_machine   = cm_t3517_init,
        .timer          = &omap3_timer,
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index b6002ec31c6a..4b1f6c68c358 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -397,14 +397,6 @@ static struct platform_device keys_gpio = {
        },
 };
-static void __init devkit8000_init_early(void)
-{
-        omap2_init_common_infrastructure();
-        omap2_init_common_devices(mt46h32m32lf6_sdrc_params,
-                                  mt46h32m32lf6_sdrc_params);
-}
 static void __init devkit8000_init_irq(void)
 {
        omap3_init_irq();
@@ -645,6 +637,8 @@ static void __init devkit8000_init(void)
 {
        omap3_mux_init(board_mux, OMAP_PACKAGE_CUS);
        omap_serial_init();
+        omap_sdrc_init(mt46h32m32lf6_sdrc_params,
+                                  mt46h32m32lf6_sdrc_params);
        omap_dm9000_init();
@@ -670,7 +664,7 @@ MACHINE_START(DEVKIT8000, "OMAP3 Devkit8000")
        .boot_params    = 0x80000100,
        .reserve        = omap_reserve,
        .map_io         = omap3_map_io,
-        .init_early     = devkit8000_init_early,
+        .init_early     = omap35xx_init_early,
        .init_irq       = devkit8000_init_irq,
        .init_machine   = devkit8000_init,
        .timer          = &omap3_secure_timer,
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 54db41a84a9b..5223898f50e4 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -36,12 +36,12 @@ static struct omap_board_config_kernel generic_config[] = {
 static void __init omap_generic_init_early(void)
 {
        omap2_init_common_infrastructure();
-        omap2_init_common_devices(NULL, NULL);
 }
 static void __init omap_generic_init(void)
 {
        omap_serial_init();
+        omap_sdrc_init(NULL, NULL);
        omap_board_config = generic_config;
        omap_board_config_size = ARRAY_SIZE(generic_config);
 }
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index 45de2b319ec9..948fde010c69 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -290,12 +290,6 @@ static struct omap_board_config_kernel h4_config[] __initdata = {
        { OMAP_TAG_LCD,         &h4_lcd_config },
 };
-static void __init omap_h4_init_early(void)
-{
-        omap2_init_common_infrastructure();
-        omap2_init_common_devices(NULL, NULL);
-}
 static void __init omap_h4_init_irq(void)
 {
        omap2_init_irq();
@@ -371,6 +365,7 @@ static void __init omap_h4_init(void)
        platform_add_devices(h4_devices, ARRAY_SIZE(h4_devices));
        omap2_usbfs_init(&h4_usb_config);
        omap_serial_init();
+        omap_sdrc_init(NULL, NULL);
        h4_init_flash();
 }
@@ -385,7 +380,7 @@ MACHINE_START(OMAP_H4, "OMAP2420 H4 board")
        .boot_params    = 0x80000100,
        .reserve        = omap_reserve,
        .map_io         = omap_h4_map_io,
-        .init_early     = omap_h4_init_early,
+        .init_early     = omap2420_init_early,
        .init_irq       = omap_h4_init_irq,
        .init_machine   = omap_h4_init,
        .timer          = &omap2_timer,
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index 35be778caf1b..7b66338e451b 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -491,13 +491,6 @@ static struct platform_device *igep_devices[] __initdata = {
        &igep_vwlan_device,
 };
-static void __init igep_init_early(void)
-{
-        omap2_init_common_infrastructure();
-        omap2_init_common_devices(m65kxxxxam_sdrc_params,
-                                  m65kxxxxam_sdrc_params);
-}
 static int igep2_keymap[] = {
        KEY(0, 0, KEY_LEFT),
        KEY(0, 1, KEY_RIGHT),
@@ -650,6 +643,8 @@ static void __init igep_init(void)
        igep_i2c_init();
        platform_add_devices(igep_devices, ARRAY_SIZE(igep_devices));
        omap_serial_init();
+        omap_sdrc_init(m65kxxxxam_sdrc_params,
+                                  m65kxxxxam_sdrc_params);
        usb_musb_init(NULL);
        igep_flash_init();
@@ -675,7 +670,7 @@ MACHINE_START(IGEP0020, "IGEP v2 board")
        .boot_params    = 0x80000100,
        .reserve        = omap_reserve,
        .map_io         = omap3_map_io,
-        .init_early     = igep_init_early,
+        .init_early     = omap35xx_init_early,
        .init_irq       = omap3_init_irq,
        .init_machine   = igep_init,
        .timer          = &omap3_timer,
@@ -685,7 +680,7 @@ MACHINE_START(IGEP0030, "IGEP OMAP3 module")
        .boot_params    = 0x80000100,
        .reserve        = omap_reserve,
        .map_io         = omap3_map_io,
-        .init_early     = igep_init_early,
+        .init_early     = omap35xx_init_early,
        .init_irq       = omap3_init_irq,
        .init_machine   = igep_init,
        .timer          = &omap3_timer,
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index 218764c9377e..401b9449f722 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -193,12 +193,6 @@ static struct omap_board_config_kernel ldp_config[] __initdata = {
        { OMAP_TAG_LCD,         &ldp_lcd_config },
 };
-static void __init omap_ldp_init_early(void)
-{
-        omap2_init_common_infrastructure();
-        omap2_init_common_devices(NULL, NULL);
-}
 static struct twl4030_gpio_platform_data ldp_gpio_data = {
        .gpio_base      = OMAP_MAX_GPIO_LINES,
        .irq_base       = TWL4030_GPIO_IRQ_BASE,
@@ -325,6 +319,7 @@ static void __init omap_ldp_init(void)
        platform_add_devices(ldp_devices, ARRAY_SIZE(ldp_devices));
        omap_ads7846_init(1, 54, 310, NULL);
        omap_serial_init();
+        omap_sdrc_init(NULL, NULL);
        usb_musb_init(NULL);
        board_nand_init(ldp_nand_partitions,
                ARRAY_SIZE(ldp_nand_partitions), ZOOM_NAND_CS, 0);
@@ -336,7 +331,7 @@ MACHINE_START(OMAP_LDP, "OMAP LDP board")
        .boot_params    = 0x80000100,
        .reserve        = omap_reserve,
        .map_io         = omap3_map_io,
-        .init_early     = omap_ldp_init_early,
+        .init_early     = omap3430_init_early,
        .init_irq       = omap3_init_irq,
        .init_machine   = omap_ldp_init,
        .timer          = &omap3_timer,
diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
index e11f0c5d608a..77a4e19222e2 100644
--- a/arch/arm/mach-omap2/board-n8x0.c
+++ b/arch/arm/mach-omap2/board-n8x0.c
@@ -622,12 +622,6 @@ static void __init n8x0_map_io(void)
        omap242x_map_common_io();
 }
-static void __init n8x0_init_early(void)
-{
-        omap2_init_common_infrastructure();
-        omap2_init_common_devices(NULL, NULL);
-}
 #ifdef CONFIG_OMAP_MUX
 static struct omap_board_mux board_mux[] __initdata = {
        /* I2S codec port pins for McBSP block */
@@ -689,6 +683,7 @@ static void __init n8x0_init_machine(void)
                i2c_register_board_info(2, n810_i2c_board_info_2,
                                        ARRAY_SIZE(n810_i2c_board_info_2));
        board_serial_init();
+        omap_sdrc_init(NULL, NULL);
        gpmc_onenand_init(board_onenand_data);
        n8x0_mmc_init();
        n8x0_usb_init();
@@ -698,7 +693,7 @@ MACHINE_START(NOKIA_N800, "Nokia N800")
        .boot_params    = 0x80000100,
        .reserve        = omap_reserve,
        .map_io         = n8x0_map_io,
-        .init_early     = n8x0_init_early,
+        .init_early     = omap2420_init_early,
        .init_irq       = omap2_init_irq,
        .init_machine   = n8x0_init_machine,
        .timer          = &omap2_timer,
@@ -708,7 +703,7 @@ MACHINE_START(NOKIA_N810, "Nokia N810")
        .boot_params    = 0x80000100,
        .reserve        = omap_reserve,
        .map_io         = n8x0_map_io,
-        .init_early     = n8x0_init_early,
+        .init_early     = omap2420_init_early,
        .init_irq       = omap2_init_irq,
        .init_machine   = n8x0_init_machine,
        .timer          = &omap2_timer,
@@ -718,7 +713,7 @@ MACHINE_START(NOKIA_N810_WIMAX, "Nokia N810 WiMAX")
        .boot_params    = 0x80000100,
        .reserve        = omap_reserve,
        .map_io         = n8x0_map_io,
-        .init_early     = n8x0_init_early,
+        .init_early     = omap2420_init_early,
        .init_irq       = omap2_init_irq,
        .init_machine   = n8x0_init_machine,
        .timer          = &omap2_timer,
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index 3ae16b4e3f52..ce3234d6a344 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -447,8 +447,6 @@ static struct platform_device keys_gpio = {
 static void __init omap3_beagle_init_early(void)
 {
        omap2_init_common_infrastructure();
-        omap2_init_common_devices(mt46h32m32lf6_sdrc_params,
-                                  mt46h32m32lf6_sdrc_params);
 }
 static void __init omap3_beagle_init_irq(void)
@@ -534,6 +532,8 @@ static void __init omap3_beagle_init(void)
                        ARRAY_SIZE(omap3_beagle_devices));
        omap_display_init(&beagle_dss_data);
        omap_serial_init();
+        omap_sdrc_init(mt46h32m32lf6_sdrc_params,
+                                  mt46h32m32lf6_sdrc_params);
        omap_mux_init_gpio(170, OMAP_PIN_INPUT);
        /* REVISIT leave DVI powered down until it's needed ... */
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index c452b3f3331a..a1184b347aeb 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -520,12 +520,6 @@ static int __init omap3_evm_i2c_init(void)
 static struct omap_board_config_kernel omap3_evm_config[] __initdata = {
 };
-static void __init omap3_evm_init_early(void)
-{
-        omap2_init_common_infrastructure();
-        omap2_init_common_devices(mt46h32m32lf6_sdrc_params, NULL);
-}
 static struct usbhs_omap_board_data usbhs_bdata __initdata = {
        .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
@@ -640,6 +634,7 @@ static void __init omap3_evm_init(void)
        omap_display_init(&omap3_evm_dss_data);
        omap_serial_init();
+        omap_sdrc_init(mt46h32m32lf6_sdrc_params, NULL);
        /* OMAP3EVM uses ISP1504 phy and so register nop transceiver */
        usb_nop_xceiv_register();
@@ -684,7 +679,7 @@ MACHINE_START(OMAP3EVM, "OMAP3 EVM")
        .boot_params    = 0x80000100,
        .reserve        = omap_reserve,
        .map_io         = omap3_map_io,
-        .init_early     = omap3_evm_init_early,
+        .init_early     = omap35xx_init_early,
        .init_irq       = omap3_init_irq,
        .init_machine   = omap3_evm_init,
        .timer          = &omap3_timer,
diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c
index 703aeb5b8fd4..3a1dd84faca0 100644
--- a/arch/arm/mach-omap2/board-omap3logic.c
+++ b/arch/arm/mach-omap2/board-omap3logic.c
@@ -182,12 +182,6 @@ static inline void __init board_smsc911x_init(void)
        gpmc_smsc911x_init(&board_smsc911x_data);
 }
-static void __init omap3logic_init_early(void)
-{
-        omap2_init_common_infrastructure();
-        omap2_init_common_devices(NULL, NULL);
-}
 #ifdef CONFIG_OMAP_MUX
 static struct omap_board_mux board_mux[] __initdata = {
        { .reg_offset = OMAP_MUX_TERMINATOR },
@@ -200,6 +194,7 @@ static void __init omap3logic_init(void)
        omap3torpedo_fix_pbias_voltage();
        omap3logic_i2c_init();
        omap_serial_init();
+        omap_sdrc_init(NULL, NULL);
        board_mmc_init();
        board_smsc911x_init();
@@ -211,7 +206,7 @@ static void __init omap3logic_init(void)
 MACHINE_START(OMAP3_TORPEDO, "Logic OMAP3 Torpedo board")
        .boot_params    = 0x80000100,
        .map_io         = omap3_map_io,
-        .init_early     = omap3logic_init_early,
+        .init_early     = omap35xx_init_early,
        .init_irq       = omap3_init_irq,
        .init_machine   = omap3logic_init,
        .timer          = &omap3_timer,
@@ -220,7 +215,7 @@ MACHINE_END
 MACHINE_START(OMAP3530_LV_SOM, "OMAP Logic 3530 LV SOM board")
        .boot_params    = 0x80000100,
        .map_io         = omap3_map_io,
-        .init_early     = omap3logic_init_early,
+        .init_early     = omap35xx_init_early,
        .init_irq       = omap3_init_irq,
        .init_machine   = omap3logic_init,
        .timer          = &omap3_timer,
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
index 080d7bd6795e..e46bf5249559 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -525,13 +525,6 @@ static struct spi_board_info omap3pandora_spi_board_info[] __initdata = {
        }
 };
-static void __init omap3pandora_init_early(void)
-{
-        omap2_init_common_infrastructure();
-        omap2_init_common_devices(mt46h32m32lf6_sdrc_params,
-                                  mt46h32m32lf6_sdrc_params);
-}
 static void __init pandora_wl1251_init(void)
 {
        struct wl12xx_platform_data pandora_wl1251_pdata;
@@ -593,6 +586,8 @@ static void __init omap3pandora_init(void)
                        ARRAY_SIZE(omap3pandora_devices));
        omap_display_init(&pandora_dss_data);
        omap_serial_init();
+        omap_sdrc_init(mt46h32m32lf6_sdrc_params,
+                                  mt46h32m32lf6_sdrc_params);
        spi_register_board_info(omap3pandora_spi_board_info,
                        ARRAY_SIZE(omap3pandora_spi_board_info));
        omap_ads7846_init(1, OMAP3_PANDORA_TS_GPIO, 0, NULL);
@@ -609,7 +604,7 @@ MACHINE_START(OMAP3_PANDORA, "Pandora Handheld Console")
        .boot_params    = 0x80000100,
        .reserve        = omap_reserve,
        .map_io         = omap3_map_io,
-        .init_early     = omap3pandora_init_early,
+        .init_early     = omap35xx_init_early,
        .init_irq       = omap3_init_irq,
        .init_machine   = omap3pandora_init,
        .timer          = &omap3_timer,
diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
index 8e104980ea26..807c27406792 100644
--- a/arch/arm/mach-omap2/board-omap3stalker.c
+++ b/arch/arm/mach-omap2/board-omap3stalker.c
@@ -428,12 +428,6 @@ static int __init omap3_stalker_i2c_init(void)
 static struct omap_board_config_kernel omap3_stalker_config[] __initdata = {
 };
-static void __init omap3_stalker_init_early(void)
-{
-        omap2_init_common_infrastructure();
-        omap2_init_common_devices(mt46h32m32lf6_sdrc_params, NULL);
-}
 static void __init omap3_stalker_init_irq(void)
 {
        omap3_init_irq();
@@ -478,6 +472,7 @@ static void __init omap3_stalker_init(void)
        omap_display_init(&omap3_stalker_dss_data);
        omap_serial_init();
+        omap_sdrc_init(mt46h32m32lf6_sdrc_params, NULL);
        usb_musb_init(NULL);
        usbhs_init(&usbhs_bdata);
        omap_ads7846_init(1, OMAP3_STALKER_TS_GPIO, 310, NULL);
@@ -496,7 +491,7 @@ MACHINE_START(SBC3530, "OMAP3 STALKER")
        /* Maintainer: Jason Lam -lzg@ema-tech.com */
        .boot_params            = 0x80000100,
        .map_io                 = omap3_map_io,
-        .init_early             = omap3_stalker_init_early,
+        .init_early             = omap35xx_init_early,
        .init_irq               = omap3_stalker_init_irq,
        .init_machine           = omap3_stalker_init,
        .timer                  = &omap3_secure_timer,
diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c
index 852ea0464057..f7f18092f36d 100644
--- a/arch/arm/mach-omap2/board-omap3touchbook.c
+++ b/arch/arm/mach-omap2/board-omap3touchbook.c
@@ -326,13 +326,6 @@ static struct omap_board_mux board_mux[] __initdata = {
 };
 #endif
-static void __init omap3_touchbook_init_early(void)
-{
-        omap2_init_common_infrastructure();
-        omap2_init_common_devices(mt46h32m32lf6_sdrc_params,
-                                  mt46h32m32lf6_sdrc_params);
-}
 static void __init omap3_touchbook_init_irq(void)
 {
        omap3_init_irq();
@@ -385,6 +378,8 @@ static void __init omap3_touchbook_init(void)
        platform_add_devices(omap3_touchbook_devices,
                        ARRAY_SIZE(omap3_touchbook_devices));
        omap_serial_init();
+        omap_sdrc_init(mt46h32m32lf6_sdrc_params,
+                                  mt46h32m32lf6_sdrc_params);
        omap_mux_init_gpio(170, OMAP_PIN_INPUT);
        /* REVISIT leave DVI powered down until it's needed ... */
@@ -407,7 +402,7 @@ MACHINE_START(TOUCHBOOK, "OMAP3 touchbook Board")
        .boot_params    = 0x80000100,
        .reserve        = omap_reserve,
        .map_io         = omap3_map_io,
-        .init_early     = omap3_touchbook_init_early,
+        .init_early     = omap3430_init_early,
        .init_irq       = omap3_touchbook_init_irq,
        .init_machine   = omap3_touchbook_init,
        .timer          = &omap3_secure_timer,
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index 9aaa96057666..1bce76589784 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -95,12 +95,6 @@ static struct platform_device *panda_devices[] __initdata = {
        &wl1271_device,
 };
-static void __init omap4_panda_init_early(void)
-{
-        omap2_init_common_infrastructure();
-        omap2_init_common_devices(NULL, NULL);
-}
 static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
        .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
        .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
@@ -569,6 +563,7 @@ static void __init omap4_panda_init(void)
        platform_add_devices(panda_devices, ARRAY_SIZE(panda_devices));
        platform_device_register(&omap_vwlan_device);
        board_serial_init();
+        omap_sdrc_init(NULL, NULL);
        omap4_twl6030_hsmmc_init(mmc);
        omap4_ehci_init();
        usb_musb_init(&musb_board_data);
@@ -586,7 +581,7 @@ MACHINE_START(OMAP4_PANDA, "OMAP4 Panda board")
        .boot_params    = 0x80000100,
        .reserve        = omap_reserve,
        .map_io         = omap4_panda_map_io,
-        .init_early     = omap4_panda_init_early,
+        .init_early     = omap4430_init_early,
        .init_irq       = gic_init_irq,
        .init_machine   = omap4_panda_init,
        .timer          = &omap4_timer,
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index f949a9954d76..7228ae50802d 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -478,13 +478,6 @@ static int __init overo_spi_init(void)
        return 0;
 }
-static void __init overo_init_early(void)
-{
-        omap2_init_common_infrastructure();
-        omap2_init_common_devices(mt46h32m32lf6_sdrc_params,
-                                  mt46h32m32lf6_sdrc_params);
-}
 static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
        .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
        .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
@@ -514,6 +507,8 @@ static void __init overo_init(void)
        overo_i2c_init();
        omap_display_init(&overo_dss_data);
        omap_serial_init();
+        omap_sdrc_init(mt46h32m32lf6_sdrc_params,
+                                  mt46h32m32lf6_sdrc_params);
        omap_nand_flash_init(0, overo_nand_partitions,
                             ARRAY_SIZE(overo_nand_partitions));
        usb_musb_init(NULL);
@@ -564,7 +559,7 @@ MACHINE_START(OVERO, "Gumstix Overo")
        .boot_params    = 0x80000100,
        .reserve        = omap_reserve,
        .map_io         = omap3_map_io,
-        .init_early     = overo_init_early,
+        .init_early     = omap35xx_init_early,
        .init_irq       = omap3_init_irq,
        .init_machine   = overo_init,
        .timer          = &omap3_timer,
diff --git a/arch/arm/mach-omap2/board-rm680.c b/arch/arm/mach-omap2/board-rm680.c
index 7dfed24ee12e..a3182e846b14 100644
--- a/arch/arm/mach-omap2/board-rm680.c
+++ b/arch/arm/mach-omap2/board-rm680.c
@@ -123,15 +123,6 @@ static void __init rm680_peripherals_init(void)
        omap2_hsmmc_init(mmc);
 }
-static void __init rm680_init_early(void)
-{
-        struct omap_sdrc_params *sdrc_params;
-        omap2_init_common_infrastructure();
-        sdrc_params = nokia_get_sdram_timings();
-        omap2_init_common_devices(sdrc_params, sdrc_params);
-}
 #ifdef CONFIG_OMAP_MUX
 static struct omap_board_mux board_mux[] __initdata = {
        { .reg_offset = OMAP_MUX_TERMINATOR },
@@ -140,8 +131,14 @@ static struct omap_board_mux board_mux[] __initdata = {
 static void __init rm680_init(void)
 {
+        struct omap_sdrc_params *sdrc_params;
        omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
        omap_serial_init();
+        sdrc_params = nokia_get_sdram_timings();
+        omap_sdrc_init(sdrc_params, sdrc_params);
        usb_musb_init(NULL);
        rm680_peripherals_init();
 }
@@ -156,7 +153,7 @@ MACHINE_START(NOKIA_RM680, "Nokia RM-680 board")
        .boot_params    = 0x80000100,
        .reserve        = omap_reserve,
        .map_io         = rm680_map_io,
-        .init_early     = rm680_init_early,
+        .init_early     = omap3630_init_early,
        .init_irq       = omap3_init_irq,
        .init_machine   = rm680_init,
        .timer          = &omap3_timer,
diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c
index 5ea142f9bc97..32a79e28379c 100644
--- a/arch/arm/mach-omap2/board-rx51.c
+++ b/arch/arm/mach-omap2/board-rx51.c
@@ -102,15 +102,6 @@ static struct omap_board_config_kernel rx51_config[] = {
        { OMAP_TAG_LCD,         &rx51_lcd_config },
 };
-static void __init rx51_init_early(void)
-{
-        struct omap_sdrc_params *sdrc_params;
-        omap2_init_common_infrastructure();
-        sdrc_params = nokia_get_sdram_timings();
-        omap2_init_common_devices(sdrc_params, sdrc_params);
-}
 extern void __init rx51_peripherals_init(void);
 #ifdef CONFIG_OMAP_MUX
@@ -127,11 +118,17 @@ static struct omap_musb_board_data musb_board_data = {
 static void __init rx51_init(void)
 {
+        struct omap_sdrc_params *sdrc_params;
        omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
        omap_board_config = rx51_config;
        omap_board_config_size = ARRAY_SIZE(rx51_config);
        omap3_pm_init_cpuidle(rx51_cpuidle_params);
        omap_serial_init();
+        sdrc_params = nokia_get_sdram_timings();
+        omap_sdrc_init(sdrc_params, sdrc_params);
        usb_musb_init(&musb_board_data);
        rx51_peripherals_init();
@@ -159,7 +156,7 @@ MACHINE_START(NOKIA_RX51, "Nokia RX-51 board")
        .boot_params    = 0x80000100,
        .reserve        = rx51_reserve,
        .map_io         = rx51_map_io,
-        .init_early     = rx51_init_early,
+        .init_early     = omap3430_init_early,
        .init_irq       = omap3_init_irq,
        .init_machine   = rx51_init,
        .timer          = &omap3_timer,
diff --git a/arch/arm/mach-omap2/board-ti8168evm.c b/arch/arm/mach-omap2/board-ti8168evm.c
index a85d5b0b11da..981ca00d6e29 100644
--- a/arch/arm/mach-omap2/board-ti8168evm.c
+++ b/arch/arm/mach-omap2/board-ti8168evm.c
@@ -27,15 +27,10 @@
 static struct omap_board_config_kernel ti8168_evm_config[] __initdata = {
 };
-static void __init ti8168_init_early(void)
-{
-        omap2_init_common_infrastructure();
-        omap2_init_common_devices(NULL, NULL);
-}
 static void __init ti8168_evm_init(void)
 {
        omap_serial_init();
+        omap_sdrc_init(NULL, NULL);
        omap_board_config = ti8168_evm_config;
        omap_board_config_size = ARRAY_SIZE(ti8168_evm_config);
 }
@@ -50,7 +45,7 @@ MACHINE_START(TI8168EVM, "ti8168evm")
        /* Maintainer: Texas Instruments */
        .boot_params    = 0x80000100,
        .map_io         = ti8168_evm_map_io,
-        .init_early     = ti8168_init_early,
+        .init_early     = ti816x_init_early,
        .init_irq       = ti816x_init_irq,
        .timer          = &omap3_timer,
        .init_machine   = ti8168_evm_init,
diff --git a/arch/arm/mach-omap2/board-zoom.c b/arch/arm/mach-omap2/board-zoom.c
index 8a98c3c303fc..d56c79661038 100644
--- a/arch/arm/mach-omap2/board-zoom.c
+++ b/arch/arm/mach-omap2/board-zoom.c
@@ -34,17 +34,6 @@
 #define ZOOM3_EHCI_RESET_GPIO           64
-static void __init omap_zoom_init_early(void)
-{
-        omap2_init_common_infrastructure();
-        if (machine_is_omap_zoom2())
-                omap2_init_common_devices(mt46h32m32lf6_sdrc_params,
-                                          mt46h32m32lf6_sdrc_params);
-        else if (machine_is_omap_zoom3())
-                omap2_init_common_devices(h8mbx00u0mer0em_sdrc_params,
-                                          h8mbx00u0mer0em_sdrc_params);
-}
 #ifdef CONFIG_OMAP_MUX
 static struct omap_board_mux board_mux[] __initdata = {
        /* WLAN IRQ - GPIO 162 */
@@ -129,6 +118,14 @@ static void __init omap_zoom_init(void)
                                                ZOOM_NAND_CS, NAND_BUSWIDTH_16);
        zoom_debugboard_init();
        zoom_peripherals_init();
+        if (machine_is_omap_zoom2())
+                omap_sdrc_init(mt46h32m32lf6_sdrc_params,
+                                          mt46h32m32lf6_sdrc_params);
+        else if (machine_is_omap_zoom3())
+                omap_sdrc_init(h8mbx00u0mer0em_sdrc_params,
+                                          h8mbx00u0mer0em_sdrc_params);
        zoom_display_init();
 }
@@ -136,7 +133,7 @@ MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board")
        .boot_params    = 0x80000100,
        .reserve        = omap_reserve,
        .map_io         = omap3_map_io,
-        .init_early     = omap_zoom_init_early,
+        .init_early     = omap3430_init_early,
        .init_irq       = omap3_init_irq,
        .init_machine   = omap_zoom_init,
        .timer          = &omap3_timer,
@@ -146,7 +143,7 @@ MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board")
        .boot_params    = 0x80000100,
        .reserve        = omap_reserve,
        .map_io         = omap3_map_io,
-        .init_early     = omap_zoom_init_early,
+        .init_early     = omap3630_init_early,
        .init_irq       = omap3_init_irq,
        .init_machine   = omap_zoom_init,
        .timer          = &omap3_timer,
diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c
index debc040872f1..14a6277dd184 100644
--- a/arch/arm/mach-omap2/clock2420_data.c
+++ b/arch/arm/mach-omap2/clock2420_data.c
@@ -1898,6 +1898,54 @@ static struct omap_clk omap2420_clks[] = {
        CLK(NULL,       "pka_ick",      &pka_ick,       CK_242X),
        CLK(NULL,       "usb_fck",      &usb_fck,       CK_242X),
        CLK("musb-hdrc",        "fck",  &osc_ck,        CK_242X),
+        CLK("omap_timer.1",     "fck",  &gpt1_fck,      CK_242X),
+        CLK("omap_timer.2",     "fck",  &gpt2_fck,      CK_242X),
+        CLK("omap_timer.3",     "fck",  &gpt3_fck,      CK_242X),
+        CLK("omap_timer.4",     "fck",  &gpt4_fck,      CK_242X),
+        CLK("omap_timer.5",     "fck",  &gpt5_fck,      CK_242X),
+        CLK("omap_timer.6",     "fck",  &gpt6_fck,      CK_242X),
+        CLK("omap_timer.7",     "fck",  &gpt7_fck,      CK_242X),
+        CLK("omap_timer.8",     "fck",  &gpt8_fck,      CK_242X),
+        CLK("omap_timer.9",     "fck",  &gpt9_fck,      CK_242X),
+        CLK("omap_timer.10",    "fck",  &gpt10_fck,     CK_242X),
+        CLK("omap_timer.11",    "fck",  &gpt11_fck,     CK_242X),
+        CLK("omap_timer.12",    "fck",  &gpt12_fck,     CK_242X),
+        CLK("omap_timer.1",     "32k_ck",       &func_32k_ck,   CK_243X),
+        CLK("omap_timer.2",     "32k_ck",       &func_32k_ck,   CK_243X),
+        CLK("omap_timer.3",     "32k_ck",       &func_32k_ck,   CK_243X),
+        CLK("omap_timer.4",     "32k_ck",       &func_32k_ck,   CK_243X),
+        CLK("omap_timer.5",     "32k_ck",       &func_32k_ck,   CK_243X),
+        CLK("omap_timer.6",     "32k_ck",       &func_32k_ck,   CK_243X),
+        CLK("omap_timer.7",     "32k_ck",       &func_32k_ck,   CK_243X),
+        CLK("omap_timer.8",     "32k_ck",       &func_32k_ck,   CK_243X),
+        CLK("omap_timer.9",     "32k_ck",       &func_32k_ck,   CK_243X),
+        CLK("omap_timer.10",    "32k_ck",       &func_32k_ck,   CK_243X),
+        CLK("omap_timer.11",    "32k_ck",       &func_32k_ck,   CK_243X),
+        CLK("omap_timer.12",    "32k_ck",       &func_32k_ck,   CK_243X),
+        CLK("omap_timer.1",     "sys_ck",       &sys_ck,        CK_243X),
+        CLK("omap_timer.2",     "sys_ck",       &sys_ck,        CK_243X),
+        CLK("omap_timer.3",     "sys_ck",       &sys_ck,        CK_243X),
+        CLK("omap_timer.4",     "sys_ck",       &sys_ck,        CK_243X),
+        CLK("omap_timer.5",     "sys_ck",       &sys_ck,        CK_243X),
+        CLK("omap_timer.6",     "sys_ck",       &sys_ck,        CK_243X),
+        CLK("omap_timer.7",     "sys_ck",       &sys_ck,        CK_243X),
+        CLK("omap_timer.8",     "sys_ck",       &sys_ck,        CK_243X),
+        CLK("omap_timer.9",     "sys_ck",       &sys_ck,        CK_243X),
+        CLK("omap_timer.10",    "sys_ck",       &sys_ck,        CK_243X),
+        CLK("omap_timer.11",    "sys_ck",       &sys_ck,        CK_243X),
+        CLK("omap_timer.12",    "sys_ck",       &sys_ck,        CK_243X),
+        CLK("omap_timer.1",     "alt_ck",       &alt_ck,        CK_243X),
+        CLK("omap_timer.2",     "alt_ck",       &alt_ck,        CK_243X),
+        CLK("omap_timer.3",     "alt_ck",       &alt_ck,        CK_243X),
+        CLK("omap_timer.4",     "alt_ck",       &alt_ck,        CK_243X),
+        CLK("omap_timer.5",     "alt_ck",       &alt_ck,        CK_243X),
+        CLK("omap_timer.6",     "alt_ck",       &alt_ck,        CK_243X),
+        CLK("omap_timer.7",     "alt_ck",       &alt_ck,        CK_243X),
+        CLK("omap_timer.8",     "alt_ck",       &alt_ck,        CK_243X),
+        CLK("omap_timer.9",     "alt_ck",       &alt_ck,        CK_243X),
+        CLK("omap_timer.10",    "alt_ck",       &alt_ck,        CK_243X),
+        CLK("omap_timer.11",    "alt_ck",       &alt_ck,        CK_243X),
+        CLK("omap_timer.12",    "alt_ck",       &alt_ck,        CK_243X),
 };
 /*
diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c
index 96a942e42db1..ea6717cfa3c8 100644
--- a/arch/arm/mach-omap2/clock2430_data.c
+++ b/arch/arm/mach-omap2/clock2430_data.c
@@ -1998,6 +1998,54 @@ static struct omap_clk omap2430_clks[] = {
        CLK(NULL,       "mdm_intc_ick", &mdm_intc_ick,  CK_243X),
        CLK("omap_hsmmc.0", "mmchsdb_fck",      &mmchsdb1_fck,  CK_243X),
        CLK("omap_hsmmc.1", "mmchsdb_fck",      &mmchsdb2_fck,  CK_243X),
+        CLK("omap_timer.1",     "fck",  &gpt1_fck,      CK_243X),
+        CLK("omap_timer.2",     "fck",  &gpt2_fck,      CK_243X),
+        CLK("omap_timer.3",     "fck",  &gpt3_fck,      CK_243X),
+        CLK("omap_timer.4",     "fck",  &gpt4_fck,      CK_243X),
+        CLK("omap_timer.5",     "fck",  &gpt5_fck,      CK_243X),
+        CLK("omap_timer.6",     "fck",  &gpt6_fck,      CK_243X),
+        CLK("omap_timer.7",     "fck",  &gpt7_fck,      CK_243X),
+        CLK("omap_timer.8",     "fck",  &gpt8_fck,      CK_243X),
+        CLK("omap_timer.9",     "fck",  &gpt9_fck,      CK_243X),
+        CLK("omap_timer.10",    "fck",  &gpt10_fck,     CK_243X),
+        CLK("omap_timer.11",    "fck",  &gpt11_fck,     CK_243X),
+        CLK("omap_timer.12",    "fck",  &gpt12_fck,     CK_243X),
+        CLK("omap_timer.1",     "32k_ck",  &func_32k_ck,   CK_243X),
+        CLK("omap_timer.2",     "32k_ck",  &func_32k_ck,   CK_243X),
+        CLK("omap_timer.3",     "32k_ck",  &func_32k_ck,   CK_243X),
+        CLK("omap_timer.4",     "32k_ck",  &func_32k_ck,   CK_243X),
+        CLK("omap_timer.5",     "32k_ck",  &func_32k_ck,   CK_243X),
+        CLK("omap_timer.6",     "32k_ck",  &func_32k_ck,   CK_243X),
+        CLK("omap_timer.7",     "32k_ck",  &func_32k_ck,   CK_243X),
+        CLK("omap_timer.8",     "32k_ck",  &func_32k_ck,   CK_243X),
+        CLK("omap_timer.9",     "32k_ck",  &func_32k_ck,   CK_243X),
+        CLK("omap_timer.10",    "32k_ck",  &func_32k_ck,   CK_243X),
+        CLK("omap_timer.11",    "32k_ck",  &func_32k_ck,   CK_243X),
+        CLK("omap_timer.12",    "32k_ck",  &func_32k_ck,   CK_243X),
+        CLK("omap_timer.1",     "sys_ck",       &sys_ck,        CK_243X),
+        CLK("omap_timer.2",     "sys_ck",       &sys_ck,        CK_243X),
+        CLK("omap_timer.3",     "sys_ck",       &sys_ck,        CK_243X),
+        CLK("omap_timer.4",     "sys_ck",       &sys_ck,        CK_243X),
+        CLK("omap_timer.5",     "sys_ck",       &sys_ck,        CK_243X),
+        CLK("omap_timer.6",     "sys_ck",       &sys_ck,        CK_243X),
+        CLK("omap_timer.7",     "sys_ck",       &sys_ck,        CK_243X),
+        CLK("omap_timer.8",     "sys_ck",       &sys_ck,        CK_243X),
+        CLK("omap_timer.9",     "sys_ck",       &sys_ck,        CK_243X),
+        CLK("omap_timer.10",    "sys_ck",       &sys_ck,        CK_243X),
+        CLK("omap_timer.11",    "sys_ck",       &sys_ck,        CK_243X),
+        CLK("omap_timer.12",    "sys_ck",       &sys_ck,        CK_243X),
+        CLK("omap_timer.1",     "alt_ck",       &alt_ck,        CK_243X),
+        CLK("omap_timer.2",     "alt_ck",       &alt_ck,        CK_243X),
+        CLK("omap_timer.3",     "alt_ck",       &alt_ck,        CK_243X),
+        CLK("omap_timer.4",     "alt_ck",       &alt_ck,        CK_243X),
+        CLK("omap_timer.5",     "alt_ck",       &alt_ck,        CK_243X),
+        CLK("omap_timer.6",     "alt_ck",       &alt_ck,        CK_243X),
+        CLK("omap_timer.7",     "alt_ck",       &alt_ck,        CK_243X),
+        CLK("omap_timer.8",     "alt_ck",       &alt_ck,        CK_243X),
+        CLK("omap_timer.9",     "alt_ck",       &alt_ck,        CK_243X),
+        CLK("omap_timer.10",    "alt_ck",       &alt_ck,        CK_243X),
+        CLK("omap_timer.11",    "alt_ck",       &alt_ck,        CK_243X),
+        CLK("omap_timer.12",    "alt_ck",       &alt_ck,        CK_243X),
 };
 /*
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index ffd55b1c4396..65dd363163bc 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -3078,6 +3078,7 @@ static struct clk gpt12_fck = {
        .name           = "gpt12_fck",
        .ops            = &clkops_null,
        .parent         = &secure_32k_fck,
+        .clkdm_name     = "wkup_clkdm",
        .recalc         = &followparent_recalc,
 };
@@ -3085,6 +3086,7 @@ static struct clk wdt1_fck = {
        .name           = "wdt1_fck",
        .ops            = &clkops_null,
        .parent         = &secure_32k_fck,
+        .clkdm_name     = "wkup_clkdm",
        .recalc         = &followparent_recalc,
 };
@@ -3462,6 +3464,42 @@ static struct omap_clk omap3xxx_clks[] = {
        CLK("musb-am35x",       "fck",          &hsotgusb_fck_am35xx,   CK_AM35XX),
        CLK(NULL,       "hecc_ck",      &hecc_ck,       CK_AM35XX),
        CLK(NULL,       "uart4_ick",    &uart4_ick_am35xx,      CK_AM35XX),
+        CLK("omap_timer.1",     "fck",  &gpt1_fck,      CK_3XXX),
+        CLK("omap_timer.2",     "fck",  &gpt2_fck,      CK_3XXX),
+        CLK("omap_timer.3",     "fck",  &gpt3_fck,      CK_3XXX),
+        CLK("omap_timer.4",     "fck",  &gpt4_fck,      CK_3XXX),
+        CLK("omap_timer.5",     "fck",  &gpt5_fck,      CK_3XXX),
+        CLK("omap_timer.6",     "fck",  &gpt6_fck,      CK_3XXX),
+        CLK("omap_timer.7",     "fck",  &gpt7_fck,      CK_3XXX),
+        CLK("omap_timer.8",     "fck",  &gpt8_fck,      CK_3XXX),
+        CLK("omap_timer.9",     "fck",  &gpt9_fck,      CK_3XXX),
+        CLK("omap_timer.10",    "fck",  &gpt10_fck,     CK_3XXX),
+        CLK("omap_timer.11",    "fck",  &gpt11_fck,     CK_3XXX),
+        CLK("omap_timer.12",    "fck",  &gpt12_fck,     CK_3XXX),
+        CLK("omap_timer.1",     "32k_ck",       &omap_32k_fck,  CK_3XXX),
+        CLK("omap_timer.2",     "32k_ck",       &omap_32k_fck,  CK_3XXX),
+        CLK("omap_timer.3",     "32k_ck",       &omap_32k_fck,  CK_3XXX),
+        CLK("omap_timer.4",     "32k_ck",       &omap_32k_fck,  CK_3XXX),
+        CLK("omap_timer.5",     "32k_ck",       &omap_32k_fck,  CK_3XXX),
+        CLK("omap_timer.6",     "32k_ck",       &omap_32k_fck,  CK_3XXX),
+        CLK("omap_timer.7",     "32k_ck",       &omap_32k_fck,  CK_3XXX),
+        CLK("omap_timer.8",     "32k_ck",       &omap_32k_fck,  CK_3XXX),
+        CLK("omap_timer.9",     "32k_ck",       &omap_32k_fck,  CK_3XXX),
+        CLK("omap_timer.10",    "32k_ck",       &omap_32k_fck,  CK_3XXX),
+        CLK("omap_timer.11",    "32k_ck",       &omap_32k_fck,  CK_3XXX),
+        CLK("omap_timer.12",    "32k_ck",       &omap_32k_fck,  CK_3XXX),
+        CLK("omap_timer.1",     "sys_ck",       &sys_ck,        CK_3XXX),
+        CLK("omap_timer.2",     "sys_ck",       &sys_ck,        CK_3XXX),
+        CLK("omap_timer.3",     "sys_ck",       &sys_ck,        CK_3XXX),
+        CLK("omap_timer.4",     "sys_ck",       &sys_ck,        CK_3XXX),
+        CLK("omap_timer.5",     "sys_ck",       &sys_ck,        CK_3XXX),
+        CLK("omap_timer.6",     "sys_ck",       &sys_ck,        CK_3XXX),
+        CLK("omap_timer.7",     "sys_ck",       &sys_ck,        CK_3XXX),
+        CLK("omap_timer.8",     "sys_ck",       &sys_ck,        CK_3XXX),
+        CLK("omap_timer.9",     "sys_ck",       &sys_ck,        CK_3XXX),
+        CLK("omap_timer.10",    "sys_ck",       &sys_ck,        CK_3XXX),
+        CLK("omap_timer.11",    "sys_ck",       &sys_ck,        CK_3XXX),
+        CLK("omap_timer.12",    "sys_ck",       &sys_ck,        CK_3XXX),
 };
@@ -3470,7 +3508,16 @@ int __init omap3xxx_clk_init(void)
        struct omap_clk *c;
        u32 cpu_clkflg = 0;
-        if (cpu_is_omap3517()) {
+        /*
+         * 3505 must be tested before 3517, since 3517 returns true
+         * for both AM3517 chips and AM3517 family chips, which
+         * includes 3505.  Unfortunately there's no obvious family
+         * test for 3517/3505 :-(
+         */
+        if (cpu_is_omap3505()) {
+                cpu_mask = RATE_IN_34XX;
+                cpu_clkflg = CK_3505;
+        } else if (cpu_is_omap3517()) {
                cpu_mask = RATE_IN_34XX;
                cpu_clkflg = CK_3517;
        } else if (cpu_is_omap3505()) {
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index 2af0e3f00ce1..946bf04a956d 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -3363,6 +3363,39 @@ static struct omap_clk omap44xx_clks[] = {
        CLK("usbhs-omap.0",     "usbhost_ick",          &dummy_ck,              CK_443X),
        CLK("usbhs-omap.0",     "usbtll_fck",           &dummy_ck,      CK_443X),
        CLK("omap_wdt", "ick",                          &dummy_ck,      CK_443X),
+        CLK("omap_timer.1",     "fck",                  &timer1_fck,    CK_443X),
+        CLK("omap_timer.2",     "fck",                  &timer2_fck,    CK_443X),
+        CLK("omap_timer.3",     "fck",                  &timer3_fck,    CK_443X),
+        CLK("omap_timer.4",     "fck",                  &timer4_fck,    CK_443X),
+        CLK("omap_timer.5",     "fck",                  &timer5_fck,    CK_443X),
+        CLK("omap_timer.6",     "fck",                  &timer6_fck,    CK_443X),
+        CLK("omap_timer.7",     "fck",                  &timer7_fck,    CK_443X),
+        CLK("omap_timer.8",     "fck",                  &timer8_fck,    CK_443X),
+        CLK("omap_timer.9",     "fck",                  &timer9_fck,    CK_443X),
+        CLK("omap_timer.10",    "fck",                  &timer10_fck,   CK_443X),
+        CLK("omap_timer.11",    "fck",                  &timer11_fck,   CK_443X),
+        CLK("omap_timer.1",     "32k_ck",       &sys_32k_ck,    CK_443X),
+        CLK("omap_timer.2",     "32k_ck",       &sys_32k_ck,    CK_443X),
+        CLK("omap_timer.3",     "32k_ck",       &sys_32k_ck,    CK_443X),
+        CLK("omap_timer.4",     "32k_ck",       &sys_32k_ck,    CK_443X),
+        CLK("omap_timer.5",     "32k_ck",       &sys_32k_ck,    CK_443X),
+        CLK("omap_timer.6",     "32k_ck",       &sys_32k_ck,    CK_443X),
+        CLK("omap_timer.7",     "32k_ck",       &sys_32k_ck,    CK_443X),
+        CLK("omap_timer.8",     "32k_ck",       &sys_32k_ck,    CK_443X),
+        CLK("omap_timer.9",     "32k_ck",       &sys_32k_ck,    CK_443X),
+        CLK("omap_timer.10",    "32k_ck",       &sys_32k_ck,    CK_443X),
+        CLK("omap_timer.11",    "32k_ck",       &sys_32k_ck,    CK_443X),
+        CLK("omap_timer.1",     "sys_ck",       &sys_clkin_ck,  CK_443X),
+        CLK("omap_timer.2",     "sys_ck",       &sys_clkin_ck,  CK_443X),
+        CLK("omap_timer.3",     "sys_ck",       &sys_clkin_ck,  CK_443X),
+        CLK("omap_timer.4",     "sys_ck",       &sys_clkin_ck,  CK_443X),
+        CLK("omap_timer.9",     "sys_ck",       &sys_clkin_ck,  CK_443X),
+        CLK("omap_timer.10",    "sys_ck",       &sys_clkin_ck,  CK_443X),
+        CLK("omap_timer.11",    "sys_ck",       &sys_clkin_ck,  CK_443X),
+        CLK("omap_timer.5",     "sys_ck",       &syc_clk_div_ck,        CK_443X),
+        CLK("omap_timer.6",     "sys_ck",       &syc_clk_div_ck,        CK_443X),
+        CLK("omap_timer.7",     "sys_ck",       &syc_clk_div_ck,        CK_443X),
+        CLK("omap_timer.8",     "sys_ck",       &syc_clk_div_ck,        CK_443X),
 };
 int __init omap4xxx_clk_init(void)
@@ -3376,10 +3409,18 @@ int __init omap4xxx_clk_init(void)
        } else if (cpu_is_omap446x()) {
                cpu_mask = RATE_IN_4460;
                cpu_clkflg = CK_446X;
+        } else {
+                return 0;
        }
        clk_init(&omap2_clk_functions);
-        omap2_clk_disable_clkdm_control();
+        /*
+         * Must stay commented until all OMAP SoC drivers are
+         * converted to runtime PM, or drivers may start crashing
+         *
+         * omap2_clk_disable_clkdm_control();
+         */
        for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks);
                                                                          c++)
diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
index ab7db083f97f..8480ee4344ea 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -73,9 +73,6 @@ static int _clkdm_register(struct clockdomain *clkdm)
        if (!clkdm || !clkdm->name)
                return -EINVAL;
-        if (!omap_chip_is(clkdm->omap_chip))
-                return -EINVAL;
        pwrdm = pwrdm_lookup(clkdm->pwrdm.name);
        if (!pwrdm) {
                pr_err("clockdomain: %s: powerdomain %s does not exist\n",
@@ -105,13 +102,10 @@ static struct clkdm_dep *_clkdm_deps_lookup(struct clockdomain *clkdm,
 {
        struct clkdm_dep *cd;
-        if (!clkdm || !deps || !omap_chip_is(clkdm->omap_chip))
+        if (!clkdm || !deps)
                return ERR_PTR(-EINVAL);
        for (cd = deps; cd->clkdm_name; cd++) {
-                if (!omap_chip_is(cd->omap_chip))
-                        continue;
                if (!cd->clkdm && cd->clkdm_name)
                        cd->clkdm = _clkdm_lookup(cd->clkdm_name);
@@ -148,9 +142,6 @@ static void _autodep_lookup(struct clkdm_autodep *autodep)
        if (!autodep)
                return;
-        if (!omap_chip_is(autodep->omap_chip))
-                return;
        clkdm = clkdm_lookup(autodep->clkdm.name);
        if (!clkdm) {
                pr_err("clockdomain: autodeps: clockdomain %s does not exist\n",
@@ -182,9 +173,6 @@ void _clkdm_add_autodeps(struct clockdomain *clkdm)
                if (IS_ERR(autodep->clkdm.ptr))
                        continue;
-                if (!omap_chip_is(autodep->omap_chip))
-                        continue;
                pr_debug("clockdomain: adding %s sleepdep/wkdep for "
                         "clkdm %s\n", autodep->clkdm.ptr->name,
                         clkdm->name);
@@ -216,9 +204,6 @@ void _clkdm_del_autodeps(struct clockdomain *clkdm)
                if (IS_ERR(autodep->clkdm.ptr))
                        continue;
-                if (!omap_chip_is(autodep->omap_chip))
-                        continue;
                pr_debug("clockdomain: removing %s sleepdep/wkdep for "
                         "clkdm %s\n", autodep->clkdm.ptr->name,
                         clkdm->name);
@@ -243,8 +228,6 @@ static void _resolve_clkdm_deps(struct clockdomain *clkdm,
        struct clkdm_dep *cd;
        for (cd = clkdm_deps; cd && cd->clkdm_name; cd++) {
-                if (!omap_chip_is(cd->omap_chip))
-                        continue;
                if (cd->clkdm)
                        continue;
                cd->clkdm = _clkdm_lookup(cd->clkdm_name);
@@ -257,43 +240,113 @@ static void _resolve_clkdm_deps(struct clockdomain *clkdm,
 /* Public functions */
 /**
- * clkdm_init - set up the clockdomain layer
+ * clkdm_register_platform_funcs - register clockdomain implementation fns
- * @clkdms: optional pointer to an array of clockdomains to register
+ * @co: func pointers for arch specific implementations
- * @init_autodeps: optional pointer to an array of autodeps to register
+ *
- * @custom_funcs: func pointers for arch specific implementations
+ * Register the list of function pointers used to implement the
- *
+ * clockdomain functions on different OMAP SoCs.  Should be called
- * Set up internal state.  If a pointer to an array of clockdomains
+ * before any other clkdm_register*() function.  Returns -EINVAL if
- * @clkdms was supplied, loop through the list of clockdomains,
+ * @co is null, -EEXIST if platform functions have already been
- * register all that are available on the current platform. Similarly,
+ * registered, or 0 upon success.
- * if a pointer to an array of clockdomain autodependencies
+ */
- * @init_autodeps was provided, register those.  No return value.
+int clkdm_register_platform_funcs(struct clkdm_ops *co)
+{
+        if (!co)
+                return -EINVAL;
+        if (arch_clkdm)
+                return -EEXIST;
+        arch_clkdm = co;
+        return 0;
+};
+/**
+ * clkdm_register_clkdms - register SoC clockdomains
+ * @cs: pointer to an array of struct clockdomain to register
+ *
+ * Register the clockdomains available on a particular OMAP SoC.  Must
+ * be called after clkdm_register_platform_funcs().  May be called
+ * multiple times.  Returns -EACCES if called before
+ * clkdm_register_platform_funcs(); -EINVAL if the argument @cs is
+ * null; or 0 upon success.
 */
-void clkdm_init(struct clockdomain **clkdms,
+int clkdm_register_clkdms(struct clockdomain **cs)
-                struct clkdm_autodep *init_autodeps,
-                struct clkdm_ops *custom_funcs)
 {
        struct clockdomain **c = NULL;
-        struct clockdomain *clkdm;
-        struct clkdm_autodep *autodep = NULL;
-        if (!custom_funcs)
+        if (!arch_clkdm)
-                WARN(1, "No custom clkdm functions registered\n");
+                return -EACCES;
-        else
-                arch_clkdm = custom_funcs;
+        if (!cs)
+                return -EINVAL;
+        for (c = cs; *c; c++)
+                _clkdm_register(*c);
+        return 0;
+}
+/**
+ * clkdm_register_autodeps - register autodeps (if required)
+ * @ia: pointer to a static array of struct clkdm_autodep to register
+ *
+ * Register clockdomain "automatic dependencies."  These are
+ * clockdomain wakeup and sleep dependencies that are automatically
+ * added whenever the first clock inside a clockdomain is enabled, and
+ * removed whenever the last clock inside a clockdomain is disabled.
+ * These are currently only used on OMAP3 devices, and are deprecated,
+ * since they waste energy.  However, until the OMAP2/3 IP block
+ * enable/disable sequence can be converted to match the OMAP4
+ * sequence, they are needed.
+ *
+ * Must be called only after all of the SoC clockdomains are
+ * registered, since the function will resolve autodep clockdomain
+ * names into clockdomain pointers.
+ *
+ * The struct clkdm_autodep @ia array must be static, as this function
+ * does not copy the array elements.
+ *
+ * Returns -EACCES if called before any clockdomains have been
+ * registered, -EINVAL if called with a null @ia argument, -EEXIST if
+ * autodeps have already been registered, or 0 upon success.
+ */
+int clkdm_register_autodeps(struct clkdm_autodep *ia)
+{
+        struct clkdm_autodep *a = NULL;
-        if (clkdms)
+        if (list_empty(&clkdm_list))
-                for (c = clkdms; *c; c++)
+                return -EACCES;
-                        _clkdm_register(*c);
+        if (!ia)
+                return -EINVAL;
-        autodeps = init_autodeps;
        if (autodeps)
-                for (autodep = autodeps; autodep->clkdm.ptr; autodep++)
+                return -EEXIST;
-                        _autodep_lookup(autodep);
+        autodeps = ia;
+        for (a = autodeps; a->clkdm.ptr; a++)
+                _autodep_lookup(a);
+        return 0;
+}
+/**
+ * clkdm_complete_init - set up the clockdomain layer
+ *
+ * Put all clockdomains into software-supervised mode; PM code should
+ * later enable hardware-supervised mode as appropriate.  Must be
+ * called after clkdm_register_clkdms().  Returns -EACCES if called
+ * before clkdm_register_clkdms(), or 0 upon success.
+ */
+int clkdm_complete_init(void)
+{
+        struct clockdomain *clkdm;
+        if (list_empty(&clkdm_list))
+                return -EACCES;
-        /*
-         * Put all clockdomains into software-supervised mode; PM code
-         * should later enable hardware-supervised mode as appropriate
-         */
        list_for_each_entry(clkdm, &clkdm_list, node) {
                if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
                        clkdm_wakeup(clkdm);
@@ -306,6 +359,8 @@ void clkdm_init(struct clockdomain **clkdms,
                _resolve_clkdm_deps(clkdm, clkdm->sleepdep_srcs);
                clkdm_clear_all_sleepdeps(clkdm);
        }
+        return 0;
 }
 /**
@@ -747,6 +802,7 @@ int clkdm_wakeup(struct clockdomain *clkdm)
        spin_lock_irqsave(&clkdm->lock, flags);
        clkdm->_flags &= ~_CLKDM_FLAG_HWSUP_ENABLED;
        ret = arch_clkdm->clkdm_wakeup(clkdm);
+        ret |= pwrdm_state_switch(clkdm->pwrdm.ptr);
        spin_unlock_irqrestore(&clkdm->lock, flags);
        return ret;
 }
@@ -818,6 +874,7 @@ void clkdm_deny_idle(struct clockdomain *clkdm)
        spin_lock_irqsave(&clkdm->lock, flags);
        clkdm->_flags &= ~_CLKDM_FLAG_HWSUP_ENABLED;
        arch_clkdm->clkdm_deny_idle(clkdm);
+        pwrdm_state_switch(clkdm->pwrdm.ptr);
        spin_unlock_irqrestore(&clkdm->lock, flags);
 }
diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h
index 1e50c88b8a07..f7b58609bad8 100644
--- a/arch/arm/mach-omap2/clockdomain.h
+++ b/arch/arm/mach-omap2/clockdomain.h
@@ -45,7 +45,6 @@
 /**
 * struct clkdm_autodep - clkdm deps to add when entering/exiting hwsup mode
 * @clkdm: clockdomain to add wkdep+sleepdep on - set name member only
- * @omap_chip: OMAP chip types that this autodep is valid on
 *
 * A clockdomain that should have wkdeps and sleepdeps added when a
 * clockdomain should stay active in hwsup mode; and conversely,
@@ -60,14 +59,12 @@ struct clkdm_autodep {
                const char *name;
                struct clockdomain *ptr;
        } clkdm;
-        const struct omap_chip_id omap_chip;
 };
 /**
 * struct clkdm_dep - encode dependencies between clockdomains
 * @clkdm_name: clockdomain name
 * @clkdm: pointer to the struct clockdomain of @clkdm_name
- * @omap_chip: OMAP chip types that this dependency is valid on
 * @wkdep_usecount: Number of wakeup dependencies causing this clkdm to wake
 * @sleepdep_usecount: Number of sleep deps that could prevent clkdm from idle
 *
@@ -81,7 +78,6 @@ struct clkdm_dep {
        struct clockdomain *clkdm;
        atomic_t wkdep_usecount;
        atomic_t sleepdep_usecount;
-        const struct omap_chip_id omap_chip;
 };
 /* Possible flags for struct clockdomain._flags */
@@ -101,7 +97,6 @@ struct clkdm_dep {
 * @clkdm_offs: (OMAP4 only) CM clockdomain register offset
 * @wkdep_srcs: Clockdomains that can be told to wake this powerdomain up
 * @sleepdep_srcs: Clockdomains that can be told to keep this clkdm from inact
- * @omap_chip: OMAP chip types that this clockdomain is valid on
 * @usecount: Usecount tracking
 * @node: list_head to link all clockdomains together
 *
@@ -126,7 +121,6 @@ struct clockdomain {
        const u16 clkdm_offs;
        struct clkdm_dep *wkdep_srcs;
        struct clkdm_dep *sleepdep_srcs;
-        const struct omap_chip_id omap_chip;
        atomic_t usecount;
        struct list_head node;
        spinlock_t lock;
@@ -166,8 +160,11 @@ struct clkdm_ops {
        int     (*clkdm_clk_disable)(struct clockdomain *clkdm);
 };
-void clkdm_init(struct clockdomain **clkdms, struct clkdm_autodep *autodeps,
+int clkdm_register_platform_funcs(struct clkdm_ops *co);
-                        struct clkdm_ops *custom_funcs);
+int clkdm_register_autodeps(struct clkdm_autodep *ia);
+int clkdm_register_clkdms(struct clockdomain **c);
+int clkdm_complete_init(void);
 struct clockdomain *clkdm_lookup(const char *name);
 int clkdm_for_each(int (*fn)(struct clockdomain *clkdm, void *user),
@@ -195,7 +192,8 @@ int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk);
 int clkdm_hwmod_enable(struct clockdomain *clkdm, struct omap_hwmod *oh);
 int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh);
-extern void __init omap2xxx_clockdomains_init(void);
+extern void __init omap242x_clockdomains_init(void);
+extern void __init omap243x_clockdomains_init(void);
 extern void __init omap3xxx_clockdomains_init(void);
 extern void __init omap44xx_clockdomains_init(void);
 extern void _clkdm_add_autodeps(struct clockdomain *clkdm);
@@ -205,4 +203,10 @@ extern struct clkdm_ops omap2_clkdm_operations;
 extern struct clkdm_ops omap3_clkdm_operations;
 extern struct clkdm_ops omap4_clkdm_operations;
+extern struct clkdm_dep gfx_24xx_wkdeps[];
+extern struct clkdm_dep dsp_24xx_wkdeps[];
+extern struct clockdomain wkup_common_clkdm;
+extern struct clockdomain prm_common_clkdm;
+extern struct clockdomain cm_common_clkdm;
 #endif
diff --git a/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c b/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
index f740edb111f4..a0d68dbecfa3 100644
--- a/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
@@ -52,8 +52,6 @@ static int omap2_clkdm_clear_all_wkdeps(struct clockdomain *clkdm)
        u32 mask = 0;
        for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) {
-                if (!omap_chip_is(cd->omap_chip))
-                        continue;
                if (!cd->clkdm)
                        continue; /* only happens if data is erroneous */
@@ -98,8 +96,6 @@ static int omap3_clkdm_clear_all_sleepdeps(struct clockdomain *clkdm)
        u32 mask = 0;
        for (cd = clkdm->sleepdep_srcs; cd && cd->clkdm_name; cd++) {
-                if (!omap_chip_is(cd->omap_chip))
-                        continue;
                if (!cd->clkdm)
                        continue; /* only happens if data is erroneous */
diff --git a/arch/arm/mach-omap2/clockdomain44xx.c b/arch/arm/mach-omap2/clockdomain44xx.c
index b43706aa08bd..935c7f03dab9 100644
--- a/arch/arm/mach-omap2/clockdomain44xx.c
+++ b/arch/arm/mach-omap2/clockdomain44xx.c
@@ -52,8 +52,6 @@ static int omap4_clkdm_clear_all_wkup_sleep_deps(struct clockdomain *clkdm)
        u32 mask = 0;
        for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) {
-                if (!omap_chip_is(cd->omap_chip))
-                        continue;
                if (!cd->clkdm)
                        continue; /* only happens if data is erroneous */
diff --git a/arch/arm/mach-omap2/clockdomains2420_data.c b/arch/arm/mach-omap2/clockdomains2420_data.c
new file mode 100644
index 000000000000..0ab8e46d5b2b
--- /dev/null
+++ b/arch/arm/mach-omap2/clockdomains2420_data.c
@@ -0,0 +1,154 @@
+/*
+ * OMAP2420 clockdomains
+ *
+ * Copyright (C) 2008-2011 Texas Instruments, Inc.
+ * Copyright (C) 2008-2010 Nokia Corporation
+ *
+ * Paul Walmsley, Jouni Högander
+ *
+ * This file contains clockdomains and clockdomain wakeup dependencies
+ * for OMAP2420 chips.  Some notes:
+ *
+ * A useful validation rule for struct clockdomain: Any clockdomain
+ * referenced by a wkdep_srcs must have a dep_bit assigned.  So
+ * wkdep_srcs are really just software-controllable dependencies.
+ * Non-software-controllable dependencies do exist, but they are not
+ * encoded below (yet).
+ *
+ * 24xx does not support programmable sleep dependencies (SLEEPDEP)
+ *
+ * The overly-specific dep_bit names are due to a bit name collision
+ * with CM_FCLKEN_{DSP,IVA2}.  The DSP/IVA2 PM_WKDEP and CM_SLEEPDEP shift
+ * value are the same for all powerdomains: 2
+ *
+ * XXX should dep_bit be a mask, so we can test to see if it is 0 as a
+ * sanity check?
+ * XXX encode hardware fixed wakeup dependencies -- esp. for 3430 CORE
+ */
+/*
+ * To-Do List
+ * -> Port the Sleep/Wakeup dependencies for the domains
+ *    from the Power domain framework
+ */
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include "clockdomain.h"
+#include "prm2xxx_3xxx.h"
+#include "cm2xxx_3xxx.h"
+#include "cm-regbits-24xx.h"
+#include "prm-regbits-24xx.h"
+/*
+ * Clockdomain dependencies for wkdeps
+ *
+ * XXX Hardware dependencies (e.g., dependencies that cannot be
+ * changed in software) are not included here yet, but should be.
+ */
+/* Wakeup dependency source arrays */
+/* 2420-specific possible wakeup dependencies */
+/* 2420 PM_WKDEP_MPU: CORE, DSP, WKUP */
+static struct clkdm_dep mpu_2420_wkdeps[] = {
+        { .clkdm_name = "core_l3_clkdm" },
+        { .clkdm_name = "core_l4_clkdm" },
+        { .clkdm_name = "dsp_clkdm" },
+        { .clkdm_name = "wkup_clkdm" },
+        { NULL },
+};
+/* 2420 PM_WKDEP_CORE: DSP, GFX, MPU, WKUP */
+static struct clkdm_dep core_2420_wkdeps[] = {
+        { .clkdm_name = "dsp_clkdm" },
+        { .clkdm_name = "gfx_clkdm" },
+        { .clkdm_name = "mpu_clkdm" },
+        { .clkdm_name = "wkup_clkdm" },
+        { NULL },
+};
+/*
+ * 2420-only clockdomains
+ */
+static struct clockdomain mpu_2420_clkdm = {
+        .name           = "mpu_clkdm",
+        .pwrdm          = { .name = "mpu_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP,
+        .wkdep_srcs     = mpu_2420_wkdeps,
+        .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
+};
+static struct clockdomain iva1_2420_clkdm = {
+        .name           = "iva1_clkdm",
+        .pwrdm          = { .name = "dsp_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP_SWSUP,
+        .dep_bit        = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT,
+        .wkdep_srcs     = dsp_24xx_wkdeps,
+        .clktrctrl_mask = OMAP2420_AUTOSTATE_IVA_MASK,
+};
+static struct clockdomain dsp_2420_clkdm = {
+        .name           = "dsp_clkdm",
+        .pwrdm          = { .name = "dsp_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP_SWSUP,
+        .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
+};
+static struct clockdomain gfx_2420_clkdm = {
+        .name           = "gfx_clkdm",
+        .pwrdm          = { .name = "gfx_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP_SWSUP,
+        .wkdep_srcs     = gfx_24xx_wkdeps,
+        .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
+};
+static struct clockdomain core_l3_2420_clkdm = {
+        .name           = "core_l3_clkdm",
+        .pwrdm          = { .name = "core_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP,
+        .wkdep_srcs     = core_2420_wkdeps,
+        .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
+};
+static struct clockdomain core_l4_2420_clkdm = {
+        .name           = "core_l4_clkdm",
+        .pwrdm          = { .name = "core_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP,
+        .wkdep_srcs     = core_2420_wkdeps,
+        .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
+};
+static struct clockdomain dss_2420_clkdm = {
+        .name           = "dss_clkdm",
+        .pwrdm          = { .name = "core_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP,
+        .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
+};
+static struct clockdomain *clockdomains_omap242x[] __initdata = {
+        &wkup_common_clkdm,
+        &cm_common_clkdm,
+        &prm_common_clkdm,
+        &mpu_2420_clkdm,
+        &iva1_2420_clkdm,
+        &dsp_2420_clkdm,
+        &gfx_2420_clkdm,
+        &core_l3_2420_clkdm,
+        &core_l4_2420_clkdm,
+        &dss_2420_clkdm,
+        NULL,
+};
+void __init omap242x_clockdomains_init(void)
+{
+        if (!cpu_is_omap242x())
+                return;
+        clkdm_register_platform_funcs(&omap2_clkdm_operations);
+        clkdm_register_clkdms(clockdomains_omap242x);
+        clkdm_complete_init();
+}
diff --git a/arch/arm/mach-omap2/clockdomains2430_data.c b/arch/arm/mach-omap2/clockdomains2430_data.c
new file mode 100644
index 000000000000..3645ed044890
--- /dev/null
+++ b/arch/arm/mach-omap2/clockdomains2430_data.c
@@ -0,0 +1,181 @@
+/*
+ * OMAP2xxx clockdomains
+ *
+ * Copyright (C) 2008-2009 Texas Instruments, Inc.
+ * Copyright (C) 2008-2010 Nokia Corporation
+ *
+ * Paul Walmsley, Jouni Högander
+ *
+ * This file contains clockdomains and clockdomain wakeup dependencies
+ * for OMAP2xxx chips.  Some notes:
+ *
+ * A useful validation rule for struct clockdomain: Any clockdomain
+ * referenced by a wkdep_srcs must have a dep_bit assigned.  So
+ * wkdep_srcs are really just software-controllable dependencies.
+ * Non-software-controllable dependencies do exist, but they are not
+ * encoded below (yet).
+ *
+ * 24xx does not support programmable sleep dependencies (SLEEPDEP)
+ *
+ * The overly-specific dep_bit names are due to a bit name collision
+ * with CM_FCLKEN_{DSP,IVA2}.  The DSP/IVA2 PM_WKDEP and CM_SLEEPDEP shift
+ * value are the same for all powerdomains: 2
+ *
+ * XXX should dep_bit be a mask, so we can test to see if it is 0 as a
+ * sanity check?
+ * XXX encode hardware fixed wakeup dependencies -- esp. for 3430 CORE
+ */
+/*
+ * To-Do List
+ * -> Port the Sleep/Wakeup dependencies for the domains
+ *    from the Power domain framework
+ */
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include "clockdomain.h"
+#include "prm2xxx_3xxx.h"
+#include "cm2xxx_3xxx.h"
+#include "cm-regbits-24xx.h"
+#include "prm-regbits-24xx.h"
+/*
+ * Clockdomain dependencies for wkdeps
+ *
+ * XXX Hardware dependencies (e.g., dependencies that cannot be
+ * changed in software) are not included here yet, but should be.
+ */
+/* Wakeup dependency source arrays */
+/* 2430-specific possible wakeup dependencies */
+/* 2430 PM_WKDEP_CORE: DSP, GFX, MPU, WKUP, MDM */
+static struct clkdm_dep core_2430_wkdeps[] = {
+        { .clkdm_name = "dsp_clkdm" },
+        { .clkdm_name = "gfx_clkdm" },
+        { .clkdm_name = "mpu_clkdm" },
+        { .clkdm_name = "wkup_clkdm" },
+        { .clkdm_name = "mdm_clkdm" },
+        { NULL },
+};
+/* 2430 PM_WKDEP_MPU: CORE, DSP, WKUP, MDM */
+static struct clkdm_dep mpu_2430_wkdeps[] = {
+        { .clkdm_name = "core_l3_clkdm" },
+        { .clkdm_name = "core_l4_clkdm" },
+        { .clkdm_name = "dsp_clkdm" },
+        { .clkdm_name = "wkup_clkdm" },
+        { .clkdm_name = "mdm_clkdm" },
+        { NULL },
+};
+/* 2430 PM_WKDEP_MDM: CORE, MPU, WKUP */
+static struct clkdm_dep mdm_2430_wkdeps[] = {
+        { .clkdm_name = "core_l3_clkdm" },
+        { .clkdm_name = "core_l4_clkdm" },
+        { .clkdm_name = "mpu_clkdm" },
+        { .clkdm_name = "wkup_clkdm" },
+        { NULL },
+};
+/*
+ * 2430-only clockdomains
+ */
+static struct clockdomain mpu_2430_clkdm = {
+        .name           = "mpu_clkdm",
+        .pwrdm          = { .name = "mpu_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP_SWSUP,
+        .wkdep_srcs     = mpu_2430_wkdeps,
+        .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
+};
+/* Another case of bit name collisions between several registers: EN_MDM */
+static struct clockdomain mdm_clkdm = {
+        .name           = "mdm_clkdm",
+        .pwrdm          = { .name = "mdm_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP_SWSUP,
+        .dep_bit        = OMAP2430_PM_WKDEP_MPU_EN_MDM_SHIFT,
+        .wkdep_srcs     = mdm_2430_wkdeps,
+        .clktrctrl_mask = OMAP2430_AUTOSTATE_MDM_MASK,
+};
+static struct clockdomain dsp_2430_clkdm = {
+        .name           = "dsp_clkdm",
+        .pwrdm          = { .name = "dsp_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP_SWSUP,
+        .dep_bit        = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT,
+        .wkdep_srcs     = dsp_24xx_wkdeps,
+        .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
+};
+static struct clockdomain gfx_2430_clkdm = {
+        .name           = "gfx_clkdm",
+        .pwrdm          = { .name = "gfx_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP_SWSUP,
+        .wkdep_srcs     = gfx_24xx_wkdeps,
+        .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
+};
+/*
+ * XXX add usecounting for clkdm dependencies, otherwise the presence
+ * of a single dep bit for core_l3_24xx_clkdm and core_l4_24xx_clkdm
+ * could cause trouble
+ */
+static struct clockdomain core_l3_2430_clkdm = {
+        .name           = "core_l3_clkdm",
+        .pwrdm          = { .name = "core_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP,
+        .dep_bit        = OMAP24XX_EN_CORE_SHIFT,
+        .wkdep_srcs     = core_2430_wkdeps,
+        .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
+};
+/*
+ * XXX add usecounting for clkdm dependencies, otherwise the presence
+ * of a single dep bit for core_l3_24xx_clkdm and core_l4_24xx_clkdm
+ * could cause trouble
+ */
+static struct clockdomain core_l4_2430_clkdm = {
+        .name           = "core_l4_clkdm",
+        .pwrdm          = { .name = "core_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP,
+        .dep_bit        = OMAP24XX_EN_CORE_SHIFT,
+        .wkdep_srcs     = core_2430_wkdeps,
+        .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
+};
+static struct clockdomain dss_2430_clkdm = {
+        .name           = "dss_clkdm",
+        .pwrdm          = { .name = "core_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP,
+        .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
+};
+static struct clockdomain *clockdomains_omap243x[] __initdata = {
+        &wkup_common_clkdm,
+        &cm_common_clkdm,
+        &prm_common_clkdm,
+        &mpu_2430_clkdm,
+        &mdm_clkdm,
+        &dsp_2430_clkdm,
+        &gfx_2430_clkdm,
+        &core_l3_2430_clkdm,
+        &core_l4_2430_clkdm,
+        &dss_2430_clkdm,
+        NULL,
+};
+void __init omap243x_clockdomains_init(void)
+{
+        if (!cpu_is_omap243x())
+                return;
+        clkdm_register_platform_funcs(&omap2_clkdm_operations);
+        clkdm_register_clkdms(clockdomains_omap243x);
+        clkdm_complete_init();
+}
diff --git a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
index 13bde95b6790..0a6a04897d89 100644
--- a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
+++ b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
@@ -1,7 +1,7 @@
 /*
- * OMAP2/3 clockdomains
+ * OMAP2/3 clockdomain common data
 *
- * Copyright (C) 2008-2009 Texas Instruments, Inc.
+ * Copyright (C) 2008-2011 Texas Instruments, Inc.
 * Copyright (C) 2008-2010 Nokia Corporation
 *
 * Paul Walmsley, Jouni Högander
@@ -51,374 +51,28 @@
 * changed in software) are not included here yet, but should be.
 */
-/* OMAP2/3-common wakeup dependencies */
-/*
- * 2420/2430 PM_WKDEP_GFX: CORE, MPU, WKUP
- * 3430ES1 PM_WKDEP_GFX: adds IVA2, removes CORE
- * 3430ES2 PM_WKDEP_SGX: adds IVA2, removes CORE
- * These can share data since they will never be present simultaneously
- * on the same device.
- */
-static struct clkdm_dep gfx_sgx_wkdeps[] = {
-        {
-                .clkdm_name = "core_l3_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
-        },
-        {
-                .clkdm_name = "core_l4_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
-        },
-        {
-                .clkdm_name = "iva2_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm_name = "mpu_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX |
-                                            CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm_name = "wkup_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX |
-                                            CHIP_IS_OMAP3430)
-        },
-        { NULL },
-};
-/* 24XX-specific possible dependencies */
-#ifdef CONFIG_ARCH_OMAP2
 /* Wakeup dependency source arrays */
-/* 2420/2430 PM_WKDEP_DSP: CORE, MPU, WKUP */
+/* 2xxx-specific possible dependencies */
-static struct clkdm_dep dsp_24xx_wkdeps[] = {
-        {
-                .clkdm_name = "core_l3_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
-        },
-        {
-                .clkdm_name = "core_l4_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
-        },
-        {
-                .clkdm_name = "mpu_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
-        },
-        {
-                .clkdm_name = "wkup_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
-        },
-        { NULL },
-};
-/*
- * 2420 PM_WKDEP_MPU: CORE, DSP, WKUP
- * 2430 adds MDM
- */
-static struct clkdm_dep mpu_24xx_wkdeps[] = {
-        {
-                .clkdm_name = "core_l3_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
-        },
-        {
-                .clkdm_name = "core_l4_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
-        },
-        {
-                .clkdm_name = "dsp_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
-        },
-        {
-                .clkdm_name = "wkup_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
-        },
-        {
-                .clkdm_name = "mdm_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
-        },
-        { NULL },
-};
-/*
- * 2420 PM_WKDEP_CORE: DSP, GFX, MPU, WKUP
- * 2430 adds MDM
- */
-static struct clkdm_dep core_24xx_wkdeps[] = {
-        {
-                .clkdm_name = "dsp_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
-        },
-        {
-                .clkdm_name = "gfx_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
-        },
-        {
-                .clkdm_name = "mpu_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
-        },
-        {
-                .clkdm_name = "wkup_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
-        },
-        {
-                .clkdm_name = "mdm_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
-        },
-        { NULL },
-};
-#endif /* CONFIG_ARCH_OMAP2 */
-/* 2430-specific possible wakeup dependencies */
-#ifdef CONFIG_SOC_OMAP2430
+/* 2xxx PM_WKDEP_GFX: CORE, MPU, WKUP */
+struct clkdm_dep gfx_24xx_wkdeps[] = {
-/* 2430 PM_WKDEP_MDM: CORE, MPU, WKUP */
+        { .clkdm_name = "core_l3_clkdm" },
-static struct clkdm_dep mdm_2430_wkdeps[] = {
+        { .clkdm_name = "core_l4_clkdm" },
-        {
+        { .clkdm_name = "mpu_clkdm" },
-                .clkdm_name = "core_l3_clkdm",
+        { .clkdm_name = "wkup_clkdm" },
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
-        },
-        {
-                .clkdm_name = "core_l4_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
-        },
-        {
-                .clkdm_name = "mpu_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
-        },
-        {
-                .clkdm_name = "wkup_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
-        },
-        { NULL },
-};
-#endif /* CONFIG_SOC_OMAP2430 */
-/* OMAP3-specific possible dependencies */
-#ifdef CONFIG_ARCH_OMAP3
-/* 3430: PM_WKDEP_PER: CORE, IVA2, MPU, WKUP */
-static struct clkdm_dep per_wkdeps[] = {
-        {
-                .clkdm_name = "core_l3_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm_name = "core_l4_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm_name = "iva2_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm_name = "mpu_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm_name = "wkup_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        { NULL },
-};
-/* 3430ES2: PM_WKDEP_USBHOST: CORE, IVA2, MPU, WKUP */
-static struct clkdm_dep usbhost_wkdeps[] = {
-        {
-                .clkdm_name = "core_l3_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm_name = "core_l4_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm_name = "iva2_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm_name = "mpu_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm_name = "wkup_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
        { NULL },
 };
-/* 3430 PM_WKDEP_MPU: CORE, IVA2, DSS, PER */
+/* 2xxx PM_WKDEP_DSP: CORE, MPU, WKUP */
-static struct clkdm_dep mpu_3xxx_wkdeps[] = {
+struct clkdm_dep dsp_24xx_wkdeps[] = {
-        {
+        { .clkdm_name = "core_l3_clkdm" },
-                .clkdm_name = "core_l3_clkdm",
+        { .clkdm_name = "core_l4_clkdm" },
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+        { .clkdm_name = "mpu_clkdm" },
-        },
+        { .clkdm_name = "wkup_clkdm" },
-        {
-                .clkdm_name = "core_l4_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm_name = "iva2_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm_name = "dss_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm_name = "per_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
        { NULL },
 };
-/* 3430 PM_WKDEP_IVA2: CORE, MPU, WKUP, DSS, PER */
-static struct clkdm_dep iva2_wkdeps[] = {
-        {
-                .clkdm_name = "core_l3_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm_name = "core_l4_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm_name = "mpu_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm_name = "wkup_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm_name = "dss_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm_name = "per_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        { NULL },
-};
-/* 3430 PM_WKDEP_CAM: IVA2, MPU, WKUP */
-static struct clkdm_dep cam_wkdeps[] = {
-        {
-                .clkdm_name = "iva2_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm_name = "mpu_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm_name = "wkup_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        { NULL },
-};
-/* 3430 PM_WKDEP_DSS: IVA2, MPU, WKUP */
-static struct clkdm_dep dss_wkdeps[] = {
-        {
-                .clkdm_name = "iva2_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm_name = "mpu_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm_name = "wkup_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        { NULL },
-};
-/* 3430: PM_WKDEP_NEON: MPU */
-static struct clkdm_dep neon_wkdeps[] = {
-        {
-                .clkdm_name = "mpu_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        { NULL },
-};
-/* Sleep dependency source arrays for OMAP3-specific clkdms */
-/* 3430: CM_SLEEPDEP_DSS: MPU, IVA */
-static struct clkdm_dep dss_sleepdeps[] = {
-        {
-                .clkdm_name = "mpu_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm_name = "iva2_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        { NULL },
-};
-/* 3430: CM_SLEEPDEP_PER: MPU, IVA */
-static struct clkdm_dep per_sleepdeps[] = {
-        {
-                .clkdm_name = "mpu_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm_name = "iva2_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        { NULL },
-};
-/* 3430ES2: CM_SLEEPDEP_USBHOST: MPU, IVA */
-static struct clkdm_dep usbhost_sleepdeps[] = {
-        {
-                .clkdm_name = "mpu_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm_name = "iva2_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        { NULL },
-};
-/* 3430: CM_SLEEPDEP_CAM: MPU */
-static struct clkdm_dep cam_sleepdeps[] = {
-        {
-                .clkdm_name = "mpu_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        { NULL },
-};
-/*
- * 3430ES1: CM_SLEEPDEP_GFX: MPU
- * 3430ES2: CM_SLEEPDEP_SGX: MPU
- * These can share data since they will never be present simultaneously
- * on the same device.
- */
-static struct clkdm_dep gfx_sgx_sleepdeps[] = {
-        {
-                .clkdm_name = "mpu_clkdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        { NULL },
-};
-#endif /* CONFIG_ARCH_OMAP3 */
 /*
 * OMAP2/3-common clockdomains
@@ -430,439 +84,18 @@ static struct clkdm_dep gfx_sgx_sleepdeps[] = {
 */
 /* This is an implicit clockdomain - it is never defined as such in TRM */
-static struct clockdomain wkup_clkdm = {
+struct clockdomain wkup_common_clkdm = {
        .name           = "wkup_clkdm",
        .pwrdm          = { .name = "wkup_pwrdm" },
        .dep_bit        = OMAP_EN_WKUP_SHIFT,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
 };
-static struct clockdomain prm_clkdm = {
+struct clockdomain prm_common_clkdm = {
        .name           = "prm_clkdm",
        .pwrdm          = { .name = "wkup_pwrdm" },
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
 };
-static struct clockdomain cm_clkdm = {
+struct clockdomain cm_common_clkdm = {
        .name           = "cm_clkdm",
        .pwrdm          = { .name = "core_pwrdm" },
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
 };
-/*
- * 2420-only clockdomains
- */
-#if defined(CONFIG_SOC_OMAP2420)
-static struct clockdomain mpu_2420_clkdm = {
-        .name           = "mpu_clkdm",
-        .pwrdm          = { .name = "mpu_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP,
-        .wkdep_srcs     = mpu_24xx_wkdeps,
-        .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
-};
-static struct clockdomain iva1_2420_clkdm = {
-        .name           = "iva1_clkdm",
-        .pwrdm          = { .name = "dsp_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .dep_bit        = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT,
-        .wkdep_srcs     = dsp_24xx_wkdeps,
-        .clktrctrl_mask = OMAP2420_AUTOSTATE_IVA_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
-};
-static struct clockdomain dsp_2420_clkdm = {
-        .name           = "dsp_clkdm",
-        .pwrdm          = { .name = "dsp_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
-};
-static struct clockdomain gfx_2420_clkdm = {
-        .name           = "gfx_clkdm",
-        .pwrdm          = { .name = "gfx_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .wkdep_srcs     = gfx_sgx_wkdeps,
-        .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
-};
-static struct clockdomain core_l3_2420_clkdm = {
-        .name           = "core_l3_clkdm",
-        .pwrdm          = { .name = "core_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP,
-        .wkdep_srcs     = core_24xx_wkdeps,
-        .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
-};
-static struct clockdomain core_l4_2420_clkdm = {
-        .name           = "core_l4_clkdm",
-        .pwrdm          = { .name = "core_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP,
-        .wkdep_srcs     = core_24xx_wkdeps,
-        .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
-};
-static struct clockdomain dss_2420_clkdm = {
-        .name           = "dss_clkdm",
-        .pwrdm          = { .name = "core_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP,
-        .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
-};
-#endif   /* CONFIG_SOC_OMAP2420 */
-/*
- * 2430-only clockdomains
- */
-#if defined(CONFIG_SOC_OMAP2430)
-static struct clockdomain mpu_2430_clkdm = {
-        .name           = "mpu_clkdm",
-        .pwrdm          = { .name = "mpu_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .wkdep_srcs     = mpu_24xx_wkdeps,
-        .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
-};
-/* Another case of bit name collisions between several registers: EN_MDM */
-static struct clockdomain mdm_clkdm = {
-        .name           = "mdm_clkdm",
-        .pwrdm          = { .name = "mdm_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .dep_bit        = OMAP2430_PM_WKDEP_MPU_EN_MDM_SHIFT,
-        .wkdep_srcs     = mdm_2430_wkdeps,
-        .clktrctrl_mask = OMAP2430_AUTOSTATE_MDM_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
-};
-static struct clockdomain dsp_2430_clkdm = {
-        .name           = "dsp_clkdm",
-        .pwrdm          = { .name = "dsp_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .dep_bit        = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT,
-        .wkdep_srcs     = dsp_24xx_wkdeps,
-        .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
-};
-static struct clockdomain gfx_2430_clkdm = {
-        .name           = "gfx_clkdm",
-        .pwrdm          = { .name = "gfx_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .wkdep_srcs     = gfx_sgx_wkdeps,
-        .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
-};
-/*
- * XXX add usecounting for clkdm dependencies, otherwise the presence
- * of a single dep bit for core_l3_24xx_clkdm and core_l4_24xx_clkdm
- * could cause trouble
- */
-static struct clockdomain core_l3_2430_clkdm = {
-        .name           = "core_l3_clkdm",
-        .pwrdm          = { .name = "core_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP,
-        .dep_bit        = OMAP24XX_EN_CORE_SHIFT,
-        .wkdep_srcs     = core_24xx_wkdeps,
-        .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
-};
-/*
- * XXX add usecounting for clkdm dependencies, otherwise the presence
- * of a single dep bit for core_l3_24xx_clkdm and core_l4_24xx_clkdm
- * could cause trouble
- */
-static struct clockdomain core_l4_2430_clkdm = {
-        .name           = "core_l4_clkdm",
-        .pwrdm          = { .name = "core_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP,
-        .dep_bit        = OMAP24XX_EN_CORE_SHIFT,
-        .wkdep_srcs     = core_24xx_wkdeps,
-        .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
-};
-static struct clockdomain dss_2430_clkdm = {
-        .name           = "dss_clkdm",
-        .pwrdm          = { .name = "core_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP,
-        .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
-};
-#endif    /* CONFIG_SOC_OMAP2430 */
-/*
- * OMAP3 clockdomains
- */
-#if defined(CONFIG_ARCH_OMAP3)
-static struct clockdomain mpu_3xxx_clkdm = {
-        .name           = "mpu_clkdm",
-        .pwrdm          = { .name = "mpu_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP | CLKDM_CAN_FORCE_WAKEUP,
-        .dep_bit        = OMAP3430_EN_MPU_SHIFT,
-        .wkdep_srcs     = mpu_3xxx_wkdeps,
-        .clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
-};
-static struct clockdomain neon_clkdm = {
-        .name           = "neon_clkdm",
-        .pwrdm          = { .name = "neon_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .wkdep_srcs     = neon_wkdeps,
-        .clktrctrl_mask = OMAP3430_CLKTRCTRL_NEON_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
-};
-static struct clockdomain iva2_clkdm = {
-        .name           = "iva2_clkdm",
-        .pwrdm          = { .name = "iva2_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .dep_bit        = OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT,
-        .wkdep_srcs     = iva2_wkdeps,
-        .clktrctrl_mask = OMAP3430_CLKTRCTRL_IVA2_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
-};
-static struct clockdomain gfx_3430es1_clkdm = {
-        .name           = "gfx_clkdm",
-        .pwrdm          = { .name = "gfx_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .wkdep_srcs     = gfx_sgx_wkdeps,
-        .sleepdep_srcs  = gfx_sgx_sleepdeps,
-        .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_GFX_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
-};
-static struct clockdomain sgx_clkdm = {
-        .name           = "sgx_clkdm",
-        .pwrdm          = { .name = "sgx_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .wkdep_srcs     = gfx_sgx_wkdeps,
-        .sleepdep_srcs  = gfx_sgx_sleepdeps,
-        .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
-};
-/*
- * The die-to-die clockdomain was documented in the 34xx ES1 TRM, but
- * then that information was removed from the 34xx ES2+ TRM.  It is
- * unclear whether the core is still there, but the clockdomain logic
- * is there, and must be programmed to an appropriate state if the
- * CORE clockdomain is to become inactive.
- */
-static struct clockdomain d2d_clkdm = {
-        .name           = "d2d_clkdm",
-        .pwrdm          = { .name = "core_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_D2D_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
-};
-/*
- * XXX add usecounting for clkdm dependencies, otherwise the presence
- * of a single dep bit for core_l3_3xxx_clkdm and core_l4_3xxx_clkdm
- * could cause trouble
- */
-static struct clockdomain core_l3_3xxx_clkdm = {
-        .name           = "core_l3_clkdm",
-        .pwrdm          = { .name = "core_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP,
-        .dep_bit        = OMAP3430_EN_CORE_SHIFT,
-        .clktrctrl_mask = OMAP3430_CLKTRCTRL_L3_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
-};
-/*
- * XXX add usecounting for clkdm dependencies, otherwise the presence
- * of a single dep bit for core_l3_3xxx_clkdm and core_l4_3xxx_clkdm
- * could cause trouble
- */
-static struct clockdomain core_l4_3xxx_clkdm = {
-        .name           = "core_l4_clkdm",
-        .pwrdm          = { .name = "core_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP,
-        .dep_bit        = OMAP3430_EN_CORE_SHIFT,
-        .clktrctrl_mask = OMAP3430_CLKTRCTRL_L4_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
-};
-/* Another case of bit name collisions between several registers: EN_DSS */
-static struct clockdomain dss_3xxx_clkdm = {
-        .name           = "dss_clkdm",
-        .pwrdm          = { .name = "dss_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .dep_bit        = OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT,
-        .wkdep_srcs     = dss_wkdeps,
-        .sleepdep_srcs  = dss_sleepdeps,
-        .clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
-};
-static struct clockdomain cam_clkdm = {
-        .name           = "cam_clkdm",
-        .pwrdm          = { .name = "cam_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .wkdep_srcs     = cam_wkdeps,
-        .sleepdep_srcs  = cam_sleepdeps,
-        .clktrctrl_mask = OMAP3430_CLKTRCTRL_CAM_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
-};
-static struct clockdomain usbhost_clkdm = {
-        .name           = "usbhost_clkdm",
-        .pwrdm          = { .name = "usbhost_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .wkdep_srcs     = usbhost_wkdeps,
-        .sleepdep_srcs  = usbhost_sleepdeps,
-        .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
-};
-static struct clockdomain per_clkdm = {
-        .name           = "per_clkdm",
-        .pwrdm          = { .name = "per_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .dep_bit        = OMAP3430_EN_PER_SHIFT,
-        .wkdep_srcs     = per_wkdeps,
-        .sleepdep_srcs  = per_sleepdeps,
-        .clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
-};
-/*
- * Disable hw supervised mode for emu_clkdm, because emu_pwrdm is
- * switched of even if sdti is in use
- */
-static struct clockdomain emu_clkdm = {
-        .name           = "emu_clkdm",
-        .pwrdm          = { .name = "emu_pwrdm" },
-        .flags          = /* CLKDM_CAN_ENABLE_AUTO |  */CLKDM_CAN_SWSUP,
-        .clktrctrl_mask = OMAP3430_CLKTRCTRL_EMU_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
-};
-static struct clockdomain dpll1_clkdm = {
-        .name           = "dpll1_clkdm",
-        .pwrdm          = { .name = "dpll1_pwrdm" },
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
-};
-static struct clockdomain dpll2_clkdm = {
-        .name           = "dpll2_clkdm",
-        .pwrdm          = { .name = "dpll2_pwrdm" },
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
-};
-static struct clockdomain dpll3_clkdm = {
-        .name           = "dpll3_clkdm",
-        .pwrdm          = { .name = "dpll3_pwrdm" },
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
-};
-static struct clockdomain dpll4_clkdm = {
-        .name           = "dpll4_clkdm",
-        .pwrdm          = { .name = "dpll4_pwrdm" },
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
-};
-static struct clockdomain dpll5_clkdm = {
-        .name           = "dpll5_clkdm",
-        .pwrdm          = { .name = "dpll5_pwrdm" },
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
-};
-#endif   /* CONFIG_ARCH_OMAP3 */
-/*
- * Clockdomain hwsup dependencies (OMAP3 only)
- */
-static struct clkdm_autodep clkdm_autodeps[] = {
-        {
-                .clkdm     = { .name = "mpu_clkdm" },
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm     = { .name = "iva2_clkdm" },
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .clkdm     = { .name = NULL },
-        }
-};
-static struct clockdomain *clockdomains_omap2[] __initdata = {
-        &wkup_clkdm,
-        &cm_clkdm,
-        &prm_clkdm,
-#ifdef CONFIG_SOC_OMAP2420
-        &mpu_2420_clkdm,
-        &iva1_2420_clkdm,
-        &dsp_2420_clkdm,
-        &gfx_2420_clkdm,
-        &core_l3_2420_clkdm,
-        &core_l4_2420_clkdm,
-        &dss_2420_clkdm,
-#endif
-#ifdef CONFIG_SOC_OMAP2430
-        &mpu_2430_clkdm,
-        &mdm_clkdm,
-        &dsp_2430_clkdm,
-        &gfx_2430_clkdm,
-        &core_l3_2430_clkdm,
-        &core_l4_2430_clkdm,
-        &dss_2430_clkdm,
-#endif
-#ifdef CONFIG_ARCH_OMAP3
-        &mpu_3xxx_clkdm,
-        &neon_clkdm,
-        &iva2_clkdm,
-        &gfx_3430es1_clkdm,
-        &sgx_clkdm,
-        &d2d_clkdm,
-        &core_l3_3xxx_clkdm,
-        &core_l4_3xxx_clkdm,
-        &dss_3xxx_clkdm,
-        &cam_clkdm,
-        &usbhost_clkdm,
-        &per_clkdm,
-        &emu_clkdm,
-        &dpll1_clkdm,
-        &dpll2_clkdm,
-        &dpll3_clkdm,
-        &dpll4_clkdm,
-        &dpll5_clkdm,
-#endif
-        NULL,
-};
-void __init omap2xxx_clockdomains_init(void)
-{
-        clkdm_init(clockdomains_omap2, clkdm_autodeps, &omap2_clkdm_operations);
-}
-void __init omap3xxx_clockdomains_init(void)
-{
-        clkdm_init(clockdomains_omap2, clkdm_autodeps, &omap3_clkdm_operations);
-}
diff --git a/arch/arm/mach-omap2/clockdomains3xxx_data.c b/arch/arm/mach-omap2/clockdomains3xxx_data.c
new file mode 100644
index 000000000000..b84e138d99c8
--- /dev/null
+++ b/arch/arm/mach-omap2/clockdomains3xxx_data.c
@@ -0,0 +1,398 @@
+/*
+ * OMAP3xxx clockdomains
+ *
+ * Copyright (C) 2008-2011 Texas Instruments, Inc.
+ * Copyright (C) 2008-2010 Nokia Corporation
+ *
+ * Paul Walmsley, Jouni Högander
+ *
+ * This file contains clockdomains and clockdomain wakeup/sleep
+ * dependencies for the OMAP3xxx chips.  Some notes:
+ *
+ * A useful validation rule for struct clockdomain: Any clockdomain
+ * referenced by a wkdep_srcs or sleepdep_srcs array must have a
+ * dep_bit assigned.  So wkdep_srcs/sleepdep_srcs are really just
+ * software-controllable dependencies.  Non-software-controllable
+ * dependencies do exist, but they are not encoded below (yet).
+ *
+ * The overly-specific dep_bit names are due to a bit name collision
+ * with CM_FCLKEN_{DSP,IVA2}.  The DSP/IVA2 PM_WKDEP and CM_SLEEPDEP shift
+ * value are the same for all powerdomains: 2
+ *
+ * XXX should dep_bit be a mask, so we can test to see if it is 0 as a
+ * sanity check?
+ * XXX encode hardware fixed wakeup dependencies -- esp. for 3430 CORE
+ */
+/*
+ * To-Do List
+ * -> Port the Sleep/Wakeup dependencies for the domains
+ *    from the Power domain framework
+ */
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include "clockdomain.h"
+#include "prm2xxx_3xxx.h"
+#include "cm2xxx_3xxx.h"
+#include "cm-regbits-34xx.h"
+#include "prm-regbits-34xx.h"
+/*
+ * Clockdomain dependencies for wkdeps/sleepdeps
+ *
+ * XXX Hardware dependencies (e.g., dependencies that cannot be
+ * changed in software) are not included here yet, but should be.
+ */
+/* OMAP3-specific possible dependencies */
+/*
+ * 3430ES1 PM_WKDEP_GFX: adds IVA2, removes CORE
+ * 3430ES2 PM_WKDEP_SGX: adds IVA2, removes CORE
+ */
+static struct clkdm_dep gfx_sgx_3xxx_wkdeps[] = {
+        { .clkdm_name = "iva2_clkdm", },
+        { .clkdm_name = "mpu_clkdm", },
+        { .clkdm_name = "wkup_clkdm", },
+        { NULL },
+};
+/* 3430: PM_WKDEP_PER: CORE, IVA2, MPU, WKUP */
+static struct clkdm_dep per_wkdeps[] = {
+        { .clkdm_name = "core_l3_clkdm" },
+        { .clkdm_name = "core_l4_clkdm" },
+        { .clkdm_name = "iva2_clkdm" },
+        { .clkdm_name = "mpu_clkdm" },
+        { .clkdm_name = "wkup_clkdm" },
+        { NULL },
+};
+/* 3430ES2: PM_WKDEP_USBHOST: CORE, IVA2, MPU, WKUP */
+static struct clkdm_dep usbhost_wkdeps[] = {
+        { .clkdm_name = "core_l3_clkdm" },
+        { .clkdm_name = "core_l4_clkdm" },
+        { .clkdm_name = "iva2_clkdm" },
+        { .clkdm_name = "mpu_clkdm" },
+        { .clkdm_name = "wkup_clkdm" },
+        { NULL },
+};
+/* 3430 PM_WKDEP_MPU: CORE, IVA2, DSS, PER */
+static struct clkdm_dep mpu_3xxx_wkdeps[] = {
+        { .clkdm_name = "core_l3_clkdm" },
+        { .clkdm_name = "core_l4_clkdm" },
+        { .clkdm_name = "iva2_clkdm" },
+        { .clkdm_name = "dss_clkdm" },
+        { .clkdm_name = "per_clkdm" },
+        { NULL },
+};
+/* 3430 PM_WKDEP_IVA2: CORE, MPU, WKUP, DSS, PER */
+static struct clkdm_dep iva2_wkdeps[] = {
+        { .clkdm_name = "core_l3_clkdm" },
+        { .clkdm_name = "core_l4_clkdm" },
+        { .clkdm_name = "mpu_clkdm" },
+        { .clkdm_name = "wkup_clkdm" },
+        { .clkdm_name = "dss_clkdm" },
+        { .clkdm_name = "per_clkdm" },
+        { NULL },
+};
+/* 3430 PM_WKDEP_CAM: IVA2, MPU, WKUP */
+static struct clkdm_dep cam_wkdeps[] = {
+        { .clkdm_name = "iva2_clkdm" },
+        { .clkdm_name = "mpu_clkdm" },
+        { .clkdm_name = "wkup_clkdm" },
+        { NULL },
+};
+/* 3430 PM_WKDEP_DSS: IVA2, MPU, WKUP */
+static struct clkdm_dep dss_wkdeps[] = {
+        { .clkdm_name = "iva2_clkdm" },
+        { .clkdm_name = "mpu_clkdm" },
+        { .clkdm_name = "wkup_clkdm" },
+        { NULL },
+};
+/* 3430: PM_WKDEP_NEON: MPU */
+static struct clkdm_dep neon_wkdeps[] = {
+        { .clkdm_name = "mpu_clkdm" },
+        { NULL },
+};
+/* Sleep dependency source arrays for OMAP3-specific clkdms */
+/* 3430: CM_SLEEPDEP_DSS: MPU, IVA */
+static struct clkdm_dep dss_sleepdeps[] = {
+        { .clkdm_name = "mpu_clkdm" },
+        { .clkdm_name = "iva2_clkdm" },
+        { NULL },
+};
+/* 3430: CM_SLEEPDEP_PER: MPU, IVA */
+static struct clkdm_dep per_sleepdeps[] = {
+        { .clkdm_name = "mpu_clkdm" },
+        { .clkdm_name = "iva2_clkdm" },
+        { NULL },
+};
+/* 3430ES2: CM_SLEEPDEP_USBHOST: MPU, IVA */
+static struct clkdm_dep usbhost_sleepdeps[] = {
+        { .clkdm_name = "mpu_clkdm" },
+        { .clkdm_name = "iva2_clkdm" },
+        { NULL },
+};
+/* 3430: CM_SLEEPDEP_CAM: MPU */
+static struct clkdm_dep cam_sleepdeps[] = {
+        { .clkdm_name = "mpu_clkdm" },
+        { NULL },
+};
+/*
+ * 3430ES1: CM_SLEEPDEP_GFX: MPU
+ * 3430ES2: CM_SLEEPDEP_SGX: MPU
+ * These can share data since they will never be present simultaneously
+ * on the same device.
+ */
+static struct clkdm_dep gfx_sgx_sleepdeps[] = {
+        { .clkdm_name = "mpu_clkdm" },
+        { NULL },
+};
+/*
+ * OMAP3 clockdomains
+ */
+static struct clockdomain mpu_3xxx_clkdm = {
+        .name           = "mpu_clkdm",
+        .pwrdm          = { .name = "mpu_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP | CLKDM_CAN_FORCE_WAKEUP,
+        .dep_bit        = OMAP3430_EN_MPU_SHIFT,
+        .wkdep_srcs     = mpu_3xxx_wkdeps,
+        .clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK,
+};
+static struct clockdomain neon_clkdm = {
+        .name           = "neon_clkdm",
+        .pwrdm          = { .name = "neon_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP_SWSUP,
+        .wkdep_srcs     = neon_wkdeps,
+        .clktrctrl_mask = OMAP3430_CLKTRCTRL_NEON_MASK,
+};
+static struct clockdomain iva2_clkdm = {
+        .name           = "iva2_clkdm",
+        .pwrdm          = { .name = "iva2_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP_SWSUP,
+        .dep_bit        = OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT,
+        .wkdep_srcs     = iva2_wkdeps,
+        .clktrctrl_mask = OMAP3430_CLKTRCTRL_IVA2_MASK,
+};
+static struct clockdomain gfx_3430es1_clkdm = {
+        .name           = "gfx_clkdm",
+        .pwrdm          = { .name = "gfx_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP_SWSUP,
+        .wkdep_srcs     = gfx_sgx_3xxx_wkdeps,
+        .sleepdep_srcs  = gfx_sgx_sleepdeps,
+        .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_GFX_MASK,
+};
+static struct clockdomain sgx_clkdm = {
+        .name           = "sgx_clkdm",
+        .pwrdm          = { .name = "sgx_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP_SWSUP,
+        .wkdep_srcs     = gfx_sgx_3xxx_wkdeps,
+        .sleepdep_srcs  = gfx_sgx_sleepdeps,
+        .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK,
+};
+/*
+ * The die-to-die clockdomain was documented in the 34xx ES1 TRM, but
+ * then that information was removed from the 34xx ES2+ TRM.  It is
+ * unclear whether the core is still there, but the clockdomain logic
+ * is there, and must be programmed to an appropriate state if the
+ * CORE clockdomain is to become inactive.
+ */
+static struct clockdomain d2d_clkdm = {
+        .name           = "d2d_clkdm",
+        .pwrdm          = { .name = "core_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP_SWSUP,
+        .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_D2D_MASK,
+};
+/*
+ * XXX add usecounting for clkdm dependencies, otherwise the presence
+ * of a single dep bit for core_l3_3xxx_clkdm and core_l4_3xxx_clkdm
+ * could cause trouble
+ */
+static struct clockdomain core_l3_3xxx_clkdm = {
+        .name           = "core_l3_clkdm",
+        .pwrdm          = { .name = "core_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP,
+        .dep_bit        = OMAP3430_EN_CORE_SHIFT,
+        .clktrctrl_mask = OMAP3430_CLKTRCTRL_L3_MASK,
+};
+/*
+ * XXX add usecounting for clkdm dependencies, otherwise the presence
+ * of a single dep bit for core_l3_3xxx_clkdm and core_l4_3xxx_clkdm
+ * could cause trouble
+ */
+static struct clockdomain core_l4_3xxx_clkdm = {
+        .name           = "core_l4_clkdm",
+        .pwrdm          = { .name = "core_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP,
+        .dep_bit        = OMAP3430_EN_CORE_SHIFT,
+        .clktrctrl_mask = OMAP3430_CLKTRCTRL_L4_MASK,
+};
+/* Another case of bit name collisions between several registers: EN_DSS */
+static struct clockdomain dss_3xxx_clkdm = {
+        .name           = "dss_clkdm",
+        .pwrdm          = { .name = "dss_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP_SWSUP,
+        .dep_bit        = OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT,
+        .wkdep_srcs     = dss_wkdeps,
+        .sleepdep_srcs  = dss_sleepdeps,
+        .clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK,
+};
+static struct clockdomain cam_clkdm = {
+        .name           = "cam_clkdm",
+        .pwrdm          = { .name = "cam_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP_SWSUP,
+        .wkdep_srcs     = cam_wkdeps,
+        .sleepdep_srcs  = cam_sleepdeps,
+        .clktrctrl_mask = OMAP3430_CLKTRCTRL_CAM_MASK,
+};
+static struct clockdomain usbhost_clkdm = {
+        .name           = "usbhost_clkdm",
+        .pwrdm          = { .name = "usbhost_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP_SWSUP,
+        .wkdep_srcs     = usbhost_wkdeps,
+        .sleepdep_srcs  = usbhost_sleepdeps,
+        .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK,
+};
+static struct clockdomain per_clkdm = {
+        .name           = "per_clkdm",
+        .pwrdm          = { .name = "per_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP_SWSUP,
+        .dep_bit        = OMAP3430_EN_PER_SHIFT,
+        .wkdep_srcs     = per_wkdeps,
+        .sleepdep_srcs  = per_sleepdeps,
+        .clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK,
+};
+/*
+ * Disable hw supervised mode for emu_clkdm, because emu_pwrdm is
+ * switched of even if sdti is in use
+ */
+static struct clockdomain emu_clkdm = {
+        .name           = "emu_clkdm",
+        .pwrdm          = { .name = "emu_pwrdm" },
+        .flags          = /* CLKDM_CAN_ENABLE_AUTO |  */CLKDM_CAN_SWSUP,
+        .clktrctrl_mask = OMAP3430_CLKTRCTRL_EMU_MASK,
+};
+static struct clockdomain dpll1_clkdm = {
+        .name           = "dpll1_clkdm",
+        .pwrdm          = { .name = "dpll1_pwrdm" },
+};
+static struct clockdomain dpll2_clkdm = {
+        .name           = "dpll2_clkdm",
+        .pwrdm          = { .name = "dpll2_pwrdm" },
+};
+static struct clockdomain dpll3_clkdm = {
+        .name           = "dpll3_clkdm",
+        .pwrdm          = { .name = "dpll3_pwrdm" },
+};
+static struct clockdomain dpll4_clkdm = {
+        .name           = "dpll4_clkdm",
+        .pwrdm          = { .name = "dpll4_pwrdm" },
+};
+static struct clockdomain dpll5_clkdm = {
+        .name           = "dpll5_clkdm",
+        .pwrdm          = { .name = "dpll5_pwrdm" },
+};
+/*
+ * Clockdomain hwsup dependencies
+ */
+static struct clkdm_autodep clkdm_autodeps[] = {
+        {
+                .clkdm = { .name = "mpu_clkdm" },
+        },
+        {
+                .clkdm = { .name = "iva2_clkdm" },
+        },
+        {
+                .clkdm = { .name = NULL },
+        }
+};
+/*
+ *
+ */
+static struct clockdomain *clockdomains_omap3430_common[] __initdata = {
+        &wkup_common_clkdm,
+        &cm_common_clkdm,
+        &prm_common_clkdm,
+        &mpu_3xxx_clkdm,
+        &neon_clkdm,
+        &iva2_clkdm,
+        &d2d_clkdm,
+        &core_l3_3xxx_clkdm,
+        &core_l4_3xxx_clkdm,
+        &dss_3xxx_clkdm,
+        &cam_clkdm,
+        &per_clkdm,
+        &emu_clkdm,
+        &dpll1_clkdm,
+        &dpll2_clkdm,
+        &dpll3_clkdm,
+        &dpll4_clkdm,
+        NULL
+};
+static struct clockdomain *clockdomains_omap3430es1[] __initdata = {
+        &gfx_3430es1_clkdm,
+        NULL,
+};
+static struct clockdomain *clockdomains_omap3430es2plus[] __initdata = {
+        &sgx_clkdm,
+        &dpll5_clkdm,
+        &usbhost_clkdm,
+        NULL,
+};
+void __init omap3xxx_clockdomains_init(void)
+{
+        struct clockdomain **sc;
+        if (!cpu_is_omap34xx())
+                return;
+        clkdm_register_platform_funcs(&omap3_clkdm_operations);
+        clkdm_register_clkdms(clockdomains_omap3430_common);
+        sc = (omap_rev() == OMAP3430_REV_ES1_0) ? clockdomains_omap3430es1 :
+                clockdomains_omap3430es2plus;
+        clkdm_register_clkdms(sc);
+        clkdm_register_autodeps(clkdm_autodeps);
+        clkdm_complete_init();
+}
diff --git a/arch/arm/mach-omap2/clockdomains44xx_data.c b/arch/arm/mach-omap2/clockdomains44xx_data.c
index dccc651fa0d0..9299ac291d28 100644
--- a/arch/arm/mach-omap2/clockdomains44xx_data.c
+++ b/arch/arm/mach-omap2/clockdomains44xx_data.c
@@ -34,350 +34,122 @@
 /* Static Dependencies for OMAP4 Clock Domains */
 static struct clkdm_dep d2d_wkup_sleep_deps[] = {
-        {
+        { .clkdm_name = "abe_clkdm" },
-                .clkdm_name      = "abe_clkdm",
+        { .clkdm_name = "ivahd_clkdm" },
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        { .clkdm_name = "l3_1_clkdm" },
-        },
+        { .clkdm_name = "l3_2_clkdm" },
-        {
+        { .clkdm_name = "l3_emif_clkdm" },
-                .clkdm_name      = "ivahd_clkdm",
+        { .clkdm_name = "l3_init_clkdm" },
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        { .clkdm_name = "l4_cfg_clkdm" },
-        },
+        { .clkdm_name = "l4_per_clkdm" },
-        {
-                .clkdm_name      = "l3_1_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l3_2_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l3_emif_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l3_init_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l4_cfg_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l4_per_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
        { NULL },
 };
 static struct clkdm_dep ducati_wkup_sleep_deps[] = {
-        {
+        { .clkdm_name = "abe_clkdm" },
-                .clkdm_name      = "abe_clkdm",
+        { .clkdm_name = "ivahd_clkdm" },
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        { .clkdm_name = "l3_1_clkdm" },
-        },
+        { .clkdm_name = "l3_2_clkdm" },
-        {
+        { .clkdm_name = "l3_dss_clkdm" },
-                .clkdm_name      = "ivahd_clkdm",
+        { .clkdm_name = "l3_emif_clkdm" },
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        { .clkdm_name = "l3_gfx_clkdm" },
-        },
+        { .clkdm_name = "l3_init_clkdm" },
-        {
+        { .clkdm_name = "l4_cfg_clkdm" },
-                .clkdm_name      = "l3_1_clkdm",
+        { .clkdm_name = "l4_per_clkdm" },
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        { .clkdm_name = "l4_secure_clkdm" },
-        },
+        { .clkdm_name = "l4_wkup_clkdm" },
-        {
+        { .clkdm_name = "tesla_clkdm" },
-                .clkdm_name      = "l3_2_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l3_dss_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l3_emif_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l3_gfx_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l3_init_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l4_cfg_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l4_per_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l4_secure_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l4_wkup_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "tesla_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
        { NULL },
 };
 static struct clkdm_dep iss_wkup_sleep_deps[] = {
-        {
+        { .clkdm_name = "ivahd_clkdm" },
-                .clkdm_name      = "ivahd_clkdm",
+        { .clkdm_name = "l3_1_clkdm" },
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        { .clkdm_name = "l3_emif_clkdm" },
-        },
-        {
-                .clkdm_name      = "l3_1_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l3_emif_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
        { NULL },
 };
 static struct clkdm_dep ivahd_wkup_sleep_deps[] = {
-        {
+        { .clkdm_name = "l3_1_clkdm" },
-                .clkdm_name      = "l3_1_clkdm",
+        { .clkdm_name = "l3_emif_clkdm" },
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l3_emif_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
        { NULL },
 };
 static struct clkdm_dep l3_dma_wkup_sleep_deps[] = {
-        {
+        { .clkdm_name = "abe_clkdm" },
-                .clkdm_name      = "abe_clkdm",
+        { .clkdm_name = "ducati_clkdm" },
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        { .clkdm_name = "ivahd_clkdm" },
-        },
+        { .clkdm_name = "l3_1_clkdm" },
-        {
+        { .clkdm_name = "l3_dss_clkdm" },
-                .clkdm_name      = "ducati_clkdm",
+        { .clkdm_name = "l3_emif_clkdm" },
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        { .clkdm_name = "l3_init_clkdm" },
-        },
+        { .clkdm_name = "l4_cfg_clkdm" },
-        {
+        { .clkdm_name = "l4_per_clkdm" },
-                .clkdm_name      = "ivahd_clkdm",
+        { .clkdm_name = "l4_secure_clkdm" },
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        { .clkdm_name = "l4_wkup_clkdm" },
-        },
-        {
-                .clkdm_name      = "l3_1_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l3_dss_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l3_emif_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l3_init_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l4_cfg_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l4_per_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l4_secure_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l4_wkup_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
        { NULL },
 };
 static struct clkdm_dep l3_dss_wkup_sleep_deps[] = {
-        {
+        { .clkdm_name = "ivahd_clkdm" },
-                .clkdm_name      = "ivahd_clkdm",
+        { .clkdm_name = "l3_2_clkdm" },
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        { .clkdm_name = "l3_emif_clkdm" },
-        },
-        {
-                .clkdm_name      = "l3_2_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l3_emif_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
        { NULL },
 };
 static struct clkdm_dep l3_gfx_wkup_sleep_deps[] = {
-        {
+        { .clkdm_name = "ivahd_clkdm" },
-                .clkdm_name      = "ivahd_clkdm",
+        { .clkdm_name = "l3_1_clkdm" },
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        { .clkdm_name = "l3_emif_clkdm" },
-        },
-        {
-                .clkdm_name      = "l3_1_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l3_emif_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
        { NULL },
 };
 static struct clkdm_dep l3_init_wkup_sleep_deps[] = {
-        {
+        { .clkdm_name = "abe_clkdm" },
-                .clkdm_name      = "abe_clkdm",
+        { .clkdm_name = "ivahd_clkdm" },
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        { .clkdm_name = "l3_emif_clkdm" },
-        },
+        { .clkdm_name = "l4_cfg_clkdm" },
-        {
+        { .clkdm_name = "l4_per_clkdm" },
-                .clkdm_name      = "ivahd_clkdm",
+        { .clkdm_name = "l4_secure_clkdm" },
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        { .clkdm_name = "l4_wkup_clkdm" },
-        },
-        {
-                .clkdm_name      = "l3_emif_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l4_cfg_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l4_per_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l4_secure_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l4_wkup_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
        { NULL },
 };
 static struct clkdm_dep l4_secure_wkup_sleep_deps[] = {
-        {
+        { .clkdm_name = "l3_1_clkdm" },
-                .clkdm_name      = "l3_1_clkdm",
+        { .clkdm_name = "l3_emif_clkdm" },
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        { .clkdm_name = "l4_per_clkdm" },
-        },
-        {
-                .clkdm_name      = "l3_emif_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l4_per_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
        { NULL },
 };
 static struct clkdm_dep mpu_wkup_sleep_deps[] = {
-        {
+        { .clkdm_name = "abe_clkdm" },
-                .clkdm_name      = "abe_clkdm",
+        { .clkdm_name = "ducati_clkdm" },
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        { .clkdm_name = "ivahd_clkdm" },
-        },
+        { .clkdm_name = "l3_1_clkdm" },
-        {
+        { .clkdm_name = "l3_2_clkdm" },
-                .clkdm_name      = "ducati_clkdm",
+        { .clkdm_name = "l3_dss_clkdm" },
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        { .clkdm_name = "l3_emif_clkdm" },
-        },
+        { .clkdm_name = "l3_gfx_clkdm" },
-        {
+        { .clkdm_name = "l3_init_clkdm" },
-                .clkdm_name      = "ivahd_clkdm",
+        { .clkdm_name = "l4_cfg_clkdm" },
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        { .clkdm_name = "l4_per_clkdm" },
-        },
+        { .clkdm_name = "l4_secure_clkdm" },
-        {
+        { .clkdm_name = "l4_wkup_clkdm" },
-                .clkdm_name      = "l3_1_clkdm",
+        { .clkdm_name = "tesla_clkdm" },
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l3_2_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l3_dss_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l3_emif_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l3_gfx_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l3_init_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l4_cfg_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l4_per_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l4_secure_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l4_wkup_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "tesla_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
        { NULL },
 };
 static struct clkdm_dep tesla_wkup_sleep_deps[] = {
-        {
+        { .clkdm_name = "abe_clkdm" },
-                .clkdm_name      = "abe_clkdm",
+        { .clkdm_name = "ivahd_clkdm" },
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        { .clkdm_name = "l3_1_clkdm" },
-        },
+        { .clkdm_name = "l3_2_clkdm" },
-        {
+        { .clkdm_name = "l3_emif_clkdm" },
-                .clkdm_name      = "ivahd_clkdm",
+        { .clkdm_name = "l3_init_clkdm" },
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        { .clkdm_name = "l4_cfg_clkdm" },
-        },
+        { .clkdm_name = "l4_per_clkdm" },
-        {
+        { .clkdm_name = "l4_wkup_clkdm" },
-                .clkdm_name      = "l3_1_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l3_2_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l3_emif_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l3_init_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l4_cfg_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l4_per_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
-        {
-                .clkdm_name      = "l4_wkup_clkdm",
-                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
-        },
        { NULL },
 };
@@ -388,7 +160,6 @@ static struct clockdomain l4_cefuse_44xx_clkdm = {
        .cm_inst          = OMAP4430_CM2_CEFUSE_INST,
        .clkdm_offs       = OMAP4430_CM2_CEFUSE_CEFUSE_CDOFFS,
        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 static struct clockdomain l4_cfg_44xx_clkdm = {
@@ -399,7 +170,6 @@ static struct clockdomain l4_cfg_44xx_clkdm = {
        .clkdm_offs       = OMAP4430_CM2_CORE_L4CFG_CDOFFS,
        .dep_bit          = OMAP4430_L4CFG_STATDEP_SHIFT,
        .flags            = CLKDM_CAN_HWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 static struct clockdomain tesla_44xx_clkdm = {
@@ -412,7 +182,6 @@ static struct clockdomain tesla_44xx_clkdm = {
        .wkdep_srcs       = tesla_wkup_sleep_deps,
        .sleepdep_srcs    = tesla_wkup_sleep_deps,
        .flags            = CLKDM_CAN_HWSUP_SWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 static struct clockdomain l3_gfx_44xx_clkdm = {
@@ -425,7 +194,6 @@ static struct clockdomain l3_gfx_44xx_clkdm = {
        .wkdep_srcs       = l3_gfx_wkup_sleep_deps,
        .sleepdep_srcs    = l3_gfx_wkup_sleep_deps,
        .flags            = CLKDM_CAN_HWSUP_SWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 static struct clockdomain ivahd_44xx_clkdm = {
@@ -438,7 +206,6 @@ static struct clockdomain ivahd_44xx_clkdm = {
        .wkdep_srcs       = ivahd_wkup_sleep_deps,
        .sleepdep_srcs    = ivahd_wkup_sleep_deps,
        .flags            = CLKDM_CAN_HWSUP_SWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 static struct clockdomain l4_secure_44xx_clkdm = {
@@ -451,7 +218,6 @@ static struct clockdomain l4_secure_44xx_clkdm = {
        .wkdep_srcs       = l4_secure_wkup_sleep_deps,
        .sleepdep_srcs    = l4_secure_wkup_sleep_deps,
        .flags            = CLKDM_CAN_HWSUP_SWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 static struct clockdomain l4_per_44xx_clkdm = {
@@ -462,7 +228,6 @@ static struct clockdomain l4_per_44xx_clkdm = {
        .clkdm_offs       = OMAP4430_CM2_L4PER_L4PER_CDOFFS,
        .dep_bit          = OMAP4430_L4PER_STATDEP_SHIFT,
        .flags            = CLKDM_CAN_HWSUP_SWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 static struct clockdomain abe_44xx_clkdm = {
@@ -473,7 +238,6 @@ static struct clockdomain abe_44xx_clkdm = {
        .clkdm_offs       = OMAP4430_CM1_ABE_ABE_CDOFFS,
        .dep_bit          = OMAP4430_ABE_STATDEP_SHIFT,
        .flags            = CLKDM_CAN_HWSUP_SWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 static struct clockdomain l3_instr_44xx_clkdm = {
@@ -482,7 +246,6 @@ static struct clockdomain l3_instr_44xx_clkdm = {
        .prcm_partition   = OMAP4430_CM2_PARTITION,
        .cm_inst          = OMAP4430_CM2_CORE_INST,
        .clkdm_offs       = OMAP4430_CM2_CORE_L3INSTR_CDOFFS,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 static struct clockdomain l3_init_44xx_clkdm = {
@@ -495,7 +258,6 @@ static struct clockdomain l3_init_44xx_clkdm = {
        .wkdep_srcs       = l3_init_wkup_sleep_deps,
        .sleepdep_srcs    = l3_init_wkup_sleep_deps,
        .flags            = CLKDM_CAN_HWSUP_SWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 static struct clockdomain d2d_44xx_clkdm = {
@@ -507,7 +269,6 @@ static struct clockdomain d2d_44xx_clkdm = {
        .wkdep_srcs       = d2d_wkup_sleep_deps,
        .sleepdep_srcs    = d2d_wkup_sleep_deps,
        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 static struct clockdomain mpu0_44xx_clkdm = {
@@ -517,7 +278,6 @@ static struct clockdomain mpu0_44xx_clkdm = {
        .cm_inst          = OMAP4430_PRCM_MPU_CPU0_INST,
        .clkdm_offs       = OMAP4430_PRCM_MPU_CPU0_CPU0_CDOFFS,
        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 static struct clockdomain mpu1_44xx_clkdm = {
@@ -527,7 +287,6 @@ static struct clockdomain mpu1_44xx_clkdm = {
        .cm_inst          = OMAP4430_PRCM_MPU_CPU1_INST,
        .clkdm_offs       = OMAP4430_PRCM_MPU_CPU1_CPU1_CDOFFS,
        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 static struct clockdomain l3_emif_44xx_clkdm = {
@@ -538,7 +297,6 @@ static struct clockdomain l3_emif_44xx_clkdm = {
        .clkdm_offs       = OMAP4430_CM2_CORE_MEMIF_CDOFFS,
        .dep_bit          = OMAP4430_MEMIF_STATDEP_SHIFT,
        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 static struct clockdomain l4_ao_44xx_clkdm = {
@@ -548,7 +306,6 @@ static struct clockdomain l4_ao_44xx_clkdm = {
        .cm_inst          = OMAP4430_CM2_ALWAYS_ON_INST,
        .clkdm_offs       = OMAP4430_CM2_ALWAYS_ON_ALWON_CDOFFS,
        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 static struct clockdomain ducati_44xx_clkdm = {
@@ -561,7 +318,6 @@ static struct clockdomain ducati_44xx_clkdm = {
        .wkdep_srcs       = ducati_wkup_sleep_deps,
        .sleepdep_srcs    = ducati_wkup_sleep_deps,
        .flags            = CLKDM_CAN_HWSUP_SWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 static struct clockdomain mpu_44xx_clkdm = {
@@ -573,7 +329,6 @@ static struct clockdomain mpu_44xx_clkdm = {
        .wkdep_srcs       = mpu_wkup_sleep_deps,
        .sleepdep_srcs    = mpu_wkup_sleep_deps,
        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 static struct clockdomain l3_2_44xx_clkdm = {
@@ -584,7 +339,6 @@ static struct clockdomain l3_2_44xx_clkdm = {
        .clkdm_offs       = OMAP4430_CM2_CORE_L3_2_CDOFFS,
        .dep_bit          = OMAP4430_L3_2_STATDEP_SHIFT,
        .flags            = CLKDM_CAN_HWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 static struct clockdomain l3_1_44xx_clkdm = {
@@ -595,7 +349,6 @@ static struct clockdomain l3_1_44xx_clkdm = {
        .clkdm_offs       = OMAP4430_CM2_CORE_L3_1_CDOFFS,
        .dep_bit          = OMAP4430_L3_1_STATDEP_SHIFT,
        .flags            = CLKDM_CAN_HWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 static struct clockdomain iss_44xx_clkdm = {
@@ -607,7 +360,6 @@ static struct clockdomain iss_44xx_clkdm = {
        .wkdep_srcs       = iss_wkup_sleep_deps,
        .sleepdep_srcs    = iss_wkup_sleep_deps,
        .flags            = CLKDM_CAN_HWSUP_SWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 static struct clockdomain l3_dss_44xx_clkdm = {
@@ -620,7 +372,6 @@ static struct clockdomain l3_dss_44xx_clkdm = {
        .wkdep_srcs       = l3_dss_wkup_sleep_deps,
        .sleepdep_srcs    = l3_dss_wkup_sleep_deps,
        .flags            = CLKDM_CAN_HWSUP_SWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 static struct clockdomain l4_wkup_44xx_clkdm = {
@@ -631,7 +382,6 @@ static struct clockdomain l4_wkup_44xx_clkdm = {
        .clkdm_offs       = OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS,
        .dep_bit          = OMAP4430_L4WKUP_STATDEP_SHIFT,
        .flags            = CLKDM_CAN_HWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 static struct clockdomain emu_sys_44xx_clkdm = {
@@ -641,7 +391,6 @@ static struct clockdomain emu_sys_44xx_clkdm = {
        .cm_inst          = OMAP4430_PRM_EMU_CM_INST,
        .clkdm_offs       = OMAP4430_PRM_EMU_CM_EMU_CDOFFS,
        .flags            = CLKDM_CAN_HWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 static struct clockdomain l3_dma_44xx_clkdm = {
@@ -653,7 +402,6 @@ static struct clockdomain l3_dma_44xx_clkdm = {
        .wkdep_srcs       = l3_dma_wkup_sleep_deps,
        .sleepdep_srcs    = l3_dma_wkup_sleep_deps,
        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* As clockdomains are added or removed above, this list must also be changed */
@@ -685,7 +433,10 @@ static struct clockdomain *clockdomains_omap44xx[] __initdata = {
        NULL
 };
 void __init omap44xx_clockdomains_init(void)
 {
-        clkdm_init(clockdomains_omap44xx, NULL, &omap4_clkdm_operations);
+        clkdm_register_platform_funcs(&omap4_clkdm_operations);
+        clkdm_register_clkdms(clockdomains_omap44xx);
+        clkdm_complete_init();
 }
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 37efb8696927..d27daf921c7e 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -28,7 +28,6 @@
 #include "control.h"
-static struct omap_chip_id omap_chip;
 static unsigned int omap_revision;
 u32 omap_features;
@@ -39,19 +38,6 @@ unsigned int omap_rev(void)
 }
 EXPORT_SYMBOL(omap_rev);
-/**
- * omap_chip_is - test whether currently running OMAP matches a chip type
- * @oc: omap_chip_t to test against
- *
- * Test whether the currently-running OMAP chip matches the supplied
- * chip type 'oc'.  Returns 1 upon a match; 0 upon failure.
- */
-int omap_chip_is(struct omap_chip_id oci)
-{
-        return (oci.oc & omap_chip.oc) ? 1 : 0;
-}
-EXPORT_SYMBOL(omap_chip_is);
 int omap_type(void)
 {
        u32 val = 0;
@@ -242,14 +228,12 @@ static void __init ti816x_check_features(void)
        omap_features = OMAP3_HAS_NEON;
 }
-static void __init omap3_check_revision(void)
+static void __init omap3_check_revision(const char **cpu_rev)
 {
        u32 cpuid, idcode;
        u16 hawkeye;
        u8 rev;
-        omap_chip.oc = CHIP_IS_OMAP3430;
        /*
         * We cannot access revision registers on ES1.0.
         * If the processor type is Cortex-A8 and the revision is 0x0
@@ -258,7 +242,7 @@ static void __init omap3_check_revision(void)
        cpuid = read_cpuid(CPUID_ID);
        if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) {
                omap_revision = OMAP3430_REV_ES1_0;
-                omap_chip.oc |= CHIP_IS_OMAP3430ES1;
+                *cpu_rev = "1.0";
                return;
        }
@@ -279,77 +263,85 @@ static void __init omap3_check_revision(void)
                case 0: /* Take care of early samples */
                case 1:
                        omap_revision = OMAP3430_REV_ES2_0;
-                        omap_chip.oc |= CHIP_IS_OMAP3430ES2;
+                        *cpu_rev = "2.0";
                        break;
                case 2:
                        omap_revision = OMAP3430_REV_ES2_1;
-                        omap_chip.oc |= CHIP_IS_OMAP3430ES2;
+                        *cpu_rev = "2.1";
                        break;
                case 3:
                        omap_revision = OMAP3430_REV_ES3_0;
-                        omap_chip.oc |= CHIP_IS_OMAP3430ES3_0;
+                        *cpu_rev = "3.0";
                        break;
                case 4:
                        omap_revision = OMAP3430_REV_ES3_1;
-                        omap_chip.oc |= CHIP_IS_OMAP3430ES3_1;
+                        *cpu_rev = "3.1";
                        break;
                case 7:
                /* FALLTHROUGH */
                default:
                        /* Use the latest known revision as default */
                        omap_revision = OMAP3430_REV_ES3_1_2;
+                        *cpu_rev = "3.1.2";
-                        /* REVISIT: Add CHIP_IS_OMAP3430ES3_1_2? */
-                        omap_chip.oc |= CHIP_IS_OMAP3430ES3_1;
                }
                break;
        case 0xb868:
-                /* Handle OMAP35xx/AM35xx devices
+                /*
+                 * Handle OMAP/AM 3505/3517 devices
                 *
-                 * Set the device to be OMAP3505 here. Actual device
+                 * Set the device to be OMAP3517 here. Actual device
                 * is identified later based on the features.
-                 *
-                 * REVISIT: AM3505/AM3517 should have their own CHIP_IS
                 */
-                omap_revision = OMAP3505_REV(rev);
+                switch (rev) {
-                omap_chip.oc |= CHIP_IS_OMAP3430ES3_1;
+                case 0:
+                        omap_revision = OMAP3517_REV_ES1_0;
+                        *cpu_rev = "1.0";
+                        break;
+                case 1:
+                /* FALLTHROUGH */
+                default:
+                        omap_revision = OMAP3517_REV_ES1_1;
+                        *cpu_rev = "1.1";
+                }
                break;
        case 0xb891:
                /* Handle 36xx devices */
-                omap_chip.oc |= CHIP_IS_OMAP3630ES1;
                switch(rev) {
                case 0: /* Take care of early samples */
                        omap_revision = OMAP3630_REV_ES1_0;
+                        *cpu_rev = "1.0";
                        break;
                case 1:
                        omap_revision = OMAP3630_REV_ES1_1;
-                        omap_chip.oc |= CHIP_IS_OMAP3630ES1_1;
+                        *cpu_rev = "1.1";
                        break;
                case 2:
+                /* FALLTHROUGH */
                default:
-                        omap_revision =  OMAP3630_REV_ES1_2;
+                        omap_revision = OMAP3630_REV_ES1_2;
-                        omap_chip.oc |= CHIP_IS_OMAP3630ES1_2;
+                        *cpu_rev = "1.2";
                }
                break;
        case 0xb81e:
-                omap_chip.oc = CHIP_IS_TI816X;
                switch (rev) {
                case 0:
                        omap_revision = TI8168_REV_ES1_0;
+                        *cpu_rev = "1.0";
                        break;
                case 1:
+                /* FALLTHROUGH */
+                default:
                        omap_revision = TI8168_REV_ES1_1;
+                        *cpu_rev = "1.1";
                        break;
-                default:
-                        omap_revision =  TI8168_REV_ES1_1;
                }
                break;
        default:
-                /* Unknown default to latest silicon rev as default*/
+                /* Unknown default to latest silicon rev as default */
-                omap_revision =  OMAP3630_REV_ES1_2;
+                omap_revision = OMAP3630_REV_ES1_2;
-                omap_chip.oc |= CHIP_IS_OMAP3630ES1_2;
+                *cpu_rev = "1.2";
+                pr_warn("Warning: unknown chip type; assuming OMAP3630ES1.2\n");
        }
 }
@@ -382,24 +374,20 @@ static void __init omap4_check_revision(void)
                switch (rev) {
                case 0:
                        omap_revision = OMAP4430_REV_ES1_0;
-                        omap_chip.oc |= CHIP_IS_OMAP4430ES1;
                        break;
                case 1:
                default:
                        omap_revision = OMAP4430_REV_ES2_0;
-                        omap_chip.oc |= CHIP_IS_OMAP4430ES2;
                }
                break;
        case 0xb95c:
                switch (rev) {
                case 3:
                        omap_revision = OMAP4430_REV_ES2_1;
-                        omap_chip.oc |= CHIP_IS_OMAP4430ES2_1;
                        break;
                case 4:
                default:
                        omap_revision = OMAP4430_REV_ES2_2;
-                        omap_chip.oc |= CHIP_IS_OMAP4430ES2_2;
                }
                break;
        case 0xb94e:
@@ -407,14 +395,12 @@ static void __init omap4_check_revision(void)
                case 0:
                default:
                        omap_revision = OMAP4460_REV_ES1_0;
-                        omap_chip.oc |= CHIP_IS_OMAP4460ES1_0;
                        break;
                }
                break;
        default:
                /* Unknown default to latest silicon rev as default */
                omap_revision = OMAP4430_REV_ES2_2;
-                omap_chip.oc |= CHIP_IS_OMAP4430ES2_2;
        }
        pr_info("OMAP%04x ES%d.%d\n", omap_rev() >> 16,
@@ -425,94 +411,33 @@ static void __init omap4_check_revision(void)
        if (omap3_has_ ##feat())                \
                printk(#feat" ");
-static void __init omap3_cpuinfo(void)
+static void __init omap3_cpuinfo(const char *cpu_rev)
 {
-        u8 rev = GET_OMAP_REVISION();
+        const char *cpu_name;
-        char cpu_name[16], cpu_rev[16];
-        /* OMAP3430 and OMAP3530 are assumed to be same.
+        /*
+         * OMAP3430 and OMAP3530 are assumed to be same.
         *
         * OMAP3525, OMAP3515 and OMAP3503 can be detected only based
         * on available features. Upon detection, update the CPU id
         * and CPU class bits.
         */
        if (cpu_is_omap3630()) {
-                strcpy(cpu_name, "OMAP3630");
+                cpu_name = "OMAP3630";
-        } else if (cpu_is_omap3505()) {
+        } else if (cpu_is_omap3517()) {
-                /*
+                /* AM35xx devices */
-                 * AM35xx devices
+                cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505";
-                 */
-                if (omap3_has_sgx()) {
-                        omap_revision = OMAP3517_REV(rev);
-                        strcpy(cpu_name, "AM3517");
-                } else {
-                        /* Already set in omap3_check_revision() */
-                        strcpy(cpu_name, "AM3505");
-                }
        } else if (cpu_is_ti816x()) {
-                strcpy(cpu_name, "TI816X");
+                cpu_name = "TI816X";
        } else if (omap3_has_iva() && omap3_has_sgx()) {
                /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
-                strcpy(cpu_name, "OMAP3430/3530");
+                cpu_name = "OMAP3430/3530";
        } else if (omap3_has_iva()) {
-                omap_revision = OMAP3525_REV(rev);
+                cpu_name = "OMAP3525";
-                strcpy(cpu_name, "OMAP3525");
        } else if (omap3_has_sgx()) {
-                omap_revision = OMAP3515_REV(rev);
+                cpu_name = "OMAP3515";
-                strcpy(cpu_name, "OMAP3515");
        } else {
-                omap_revision = OMAP3503_REV(rev);
+                cpu_name = "OMAP3503";
-                strcpy(cpu_name, "OMAP3503");
-        }
-        if (cpu_is_omap3630() || cpu_is_ti816x()) {
-                switch (rev) {
-                case OMAP_REVBITS_00:
-                        strcpy(cpu_rev, "1.0");
-                        break;
-                case OMAP_REVBITS_01:
-                        strcpy(cpu_rev, "1.1");
-                        break;
-                case OMAP_REVBITS_02:
-                        /* FALLTHROUGH */
-                default:
-                        /* Use the latest known revision as default */
-                        strcpy(cpu_rev, "1.2");
-                }
-        } else if (cpu_is_omap3505() || cpu_is_omap3517()) {
-                switch (rev) {
-                case OMAP_REVBITS_00:
-                        strcpy(cpu_rev, "1.0");
-                        break;
-                case OMAP_REVBITS_01:
-                        /* FALLTHROUGH */
-                default:
-                        /* Use the latest known revision as default */
-                        strcpy(cpu_rev, "1.1");
-                }
-        } else {
-                switch (rev) {
-                case OMAP_REVBITS_00:
-                        strcpy(cpu_rev, "1.0");
-                        break;
-                case OMAP_REVBITS_01:
-                        strcpy(cpu_rev, "2.0");
-                        break;
-                case OMAP_REVBITS_02:
-                        strcpy(cpu_rev, "2.1");
-                        break;
-                case OMAP_REVBITS_03:
-                        strcpy(cpu_rev, "3.0");
-                        break;
-                case OMAP_REVBITS_04:
-                        strcpy(cpu_rev, "3.1");
-                        break;
-                case OMAP_REVBITS_05:
-                        /* FALLTHROUGH */
-                default:
-                        /* Use the latest known revision as default */
-                        strcpy(cpu_rev, "3.1.2");
-                }
        }
        /* Print verbose information */
@@ -533,6 +458,8 @@ static void __init omap3_cpuinfo(void)
 */
 void __init omap2_check_revision(void)
 {
+        const char *cpu_rev;
        /*
         * At this point we have an idea about the processor revision set
         * earlier with omap2_set_globals_tap().
@@ -540,7 +467,7 @@ void __init omap2_check_revision(void)
        if (cpu_is_omap24xx()) {
                omap24xx_check_revision();
        } else if (cpu_is_omap34xx()) {
-                omap3_check_revision();
+                omap3_check_revision(&cpu_rev);
                /* TI816X doesn't have feature register */
                if (!cpu_is_ti816x())
@@ -548,7 +475,7 @@ void __init omap2_check_revision(void)
                else
                        ti816x_check_features();
-                omap3_cpuinfo();
+                omap3_cpuinfo(cpu_rev);
                return;
        } else if (cpu_is_omap44xx()) {
                omap4_check_revision();
@@ -557,22 +484,6 @@ void __init omap2_check_revision(void)
        } else {
                pr_err("OMAP revision unknown, please fix!\n");
        }
-        /*
-         * OK, now we know the exact revision. Initialize omap_chip bits
-         * for powerdowmain and clockdomain code.
-         */
-        if (cpu_is_omap243x()) {
-                /* Currently only supports 2430ES2.1 and 2430-all */
-                omap_chip.oc |= CHIP_IS_OMAP2430;
-                return;
-        } else if (cpu_is_omap242x()) {
-                /* Currently only supports 2420ES2.1.1 and 2420-all */
-                omap_chip.oc |= CHIP_IS_OMAP2420;
-                return;
-        }
-        pr_err("Uninitialized omap_chip, please fix!\n");
 }
 /*
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 2ce1ce6fb4db..1a13b7916554 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -341,12 +341,12 @@ void __init omap2_init_common_infrastructure(void)
        u8 postsetup_state;
        if (cpu_is_omap242x()) {
-                omap2xxx_powerdomains_init();
+                omap242x_powerdomains_init();
-                omap2xxx_clockdomains_init();
+                omap242x_clockdomains_init();
                omap2420_hwmod_init();
        } else if (cpu_is_omap243x()) {
-                omap2xxx_powerdomains_init();
+                omap243x_powerdomains_init();
-                omap2xxx_clockdomains_init();
+                omap243x_clockdomains_init();
                omap2430_hwmod_init();
        } else if (cpu_is_omap34xx()) {
                omap3xxx_powerdomains_init();
@@ -376,7 +376,7 @@ void __init omap2_init_common_infrastructure(void)
         * omap_hwmod_late_init(), so boards that desire full watchdog
         * coverage of kernel initialization can reprogram the
         * postsetup_state between the calls to
-         * omap2_init_common_infra() and omap2_init_common_devices().
+         * omap2_init_common_infra() and omap_sdrc_init().
         *
         * XXX ideally we could detect whether the MPU WDT was currently
         * enabled here and make this conditional
@@ -400,7 +400,47 @@ void __init omap2_init_common_infrastructure(void)
                pr_err("Could not init clock framework - unknown SoC\n");
 }
-void __init omap2_init_common_devices(struct omap_sdrc_params *sdrc_cs0,
+void __init omap2420_init_early(void)
+{
+        omap2_init_common_infrastructure();
+}
+void __init omap2430_init_early(void)
+{
+        omap2_init_common_infrastructure();
+}
+void __init omap3430_init_early(void)
+{
+        omap2_init_common_infrastructure();
+}
+void __init omap35xx_init_early(void)
+{
+        omap2_init_common_infrastructure();
+}
+void __init omap3630_init_early(void)
+{
+        omap2_init_common_infrastructure();
+}
+void __init am35xx_init_early(void)
+{
+        omap2_init_common_infrastructure();
+}
+void __init ti816x_init_early(void)
+{
+        omap2_init_common_infrastructure();
+}
+void __init omap4430_init_early(void)
+{
+        omap2_init_common_infrastructure();
+}
+void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
                                      struct omap_sdrc_params *sdrc_cs1)
 {
        if (cpu_is_omap24xx() || omap3_has_sdrc()) {
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 84cc0bdda3ae..d71380705080 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -1954,9 +1954,6 @@ int __init omap_hwmod_register(struct omap_hwmod **ohs)
        i = 0;
        do {
-                if (!omap_chip_is(ohs[i]->omap_chip))
-                        continue;
                r = _register(ohs[i]);
                WARN(r, "omap_hwmod: %s: _register returned %d\n", ohs[i]->name,
                     r);
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index a015c69068f6..6d7206213525 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -100,7 +100,6 @@ static struct omap_hwmod omap2420_l3_main_hwmod = {
        .masters_cnt    = ARRAY_SIZE(omap2420_l3_main_masters),
        .slaves         = omap2420_l3_main_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2420_l3_main_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
        .flags          = HWMOD_NO_IDLEST,
 };
@@ -206,7 +205,6 @@ static struct omap_hwmod omap2420_l4_core_hwmod = {
        .masters_cnt    = ARRAY_SIZE(omap2420_l4_core_masters),
        .slaves         = omap2420_l4_core_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2420_l4_core_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
        .flags          = HWMOD_NO_IDLEST,
 };
@@ -227,7 +225,6 @@ static struct omap_hwmod omap2420_l4_wkup_hwmod = {
        .masters_cnt    = ARRAY_SIZE(omap2420_l4_wkup_masters),
        .slaves         = omap2420_l4_wkup_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2420_l4_wkup_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
        .flags          = HWMOD_NO_IDLEST,
 };
@@ -243,7 +240,6 @@ static struct omap_hwmod omap2420_mpu_hwmod = {
        .main_clk       = "mpu_ck",
        .masters        = omap2420_mpu_masters,
        .masters_cnt    = ARRAY_SIZE(omap2420_mpu_masters),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 };
 /*
@@ -271,7 +267,16 @@ static struct omap_hwmod omap2420_iva_hwmod = {
        .class          = &iva_hwmod_class,
        .masters        = omap2420_iva_masters,
        .masters_cnt    = ARRAY_SIZE(omap2420_iva_masters),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
+};
+/* always-on timers dev attribute */
+static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
+        .timer_capability       = OMAP_TIMER_ALWON,
+};
+/* pwm timers dev attribute */
+static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
+        .timer_capability       = OMAP_TIMER_HAS_PWM,
 };
 /* timer1 */
@@ -314,10 +319,10 @@ static struct omap_hwmod omap2420_timer1_hwmod = {
                        .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
                },
        },
+        .dev_attr       = &capability_alwon_dev_attr,
        .slaves         = omap2420_timer1_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2420_timer1_slaves),
        .class          = &omap2xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 };
 /* timer2 */
@@ -351,10 +356,10 @@ static struct omap_hwmod omap2420_timer2_hwmod = {
                        .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
                },
        },
+        .dev_attr       = &capability_alwon_dev_attr,
        .slaves         = omap2420_timer2_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2420_timer2_slaves),
        .class          = &omap2xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 };
 /* timer3 */
@@ -388,10 +393,10 @@ static struct omap_hwmod omap2420_timer3_hwmod = {
                        .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
                },
        },
+        .dev_attr       = &capability_alwon_dev_attr,
        .slaves         = omap2420_timer3_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2420_timer3_slaves),
        .class          = &omap2xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 };
 /* timer4 */
@@ -425,10 +430,10 @@ static struct omap_hwmod omap2420_timer4_hwmod = {
                        .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
                },
        },
+        .dev_attr       = &capability_alwon_dev_attr,
        .slaves         = omap2420_timer4_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2420_timer4_slaves),
        .class          = &omap2xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 };
 /* timer5 */
@@ -462,10 +467,10 @@ static struct omap_hwmod omap2420_timer5_hwmod = {
                        .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
                },
        },
+        .dev_attr       = &capability_alwon_dev_attr,
        .slaves         = omap2420_timer5_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2420_timer5_slaves),
        .class          = &omap2xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 };
@@ -500,10 +505,10 @@ static struct omap_hwmod omap2420_timer6_hwmod = {
                        .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
                },
        },
+        .dev_attr       = &capability_alwon_dev_attr,
        .slaves         = omap2420_timer6_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2420_timer6_slaves),
        .class          = &omap2xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 };
 /* timer7 */
@@ -537,10 +542,10 @@ static struct omap_hwmod omap2420_timer7_hwmod = {
                        .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
                },
        },
+        .dev_attr       = &capability_alwon_dev_attr,
        .slaves         = omap2420_timer7_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2420_timer7_slaves),
        .class          = &omap2xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 };
 /* timer8 */
@@ -574,10 +579,10 @@ static struct omap_hwmod omap2420_timer8_hwmod = {
                        .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
                },
        },
+        .dev_attr       = &capability_alwon_dev_attr,
        .slaves         = omap2420_timer8_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2420_timer8_slaves),
        .class          = &omap2xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 };
 /* timer9 */
@@ -611,10 +616,10 @@ static struct omap_hwmod omap2420_timer9_hwmod = {
                        .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
                },
        },
+        .dev_attr       = &capability_pwm_dev_attr,
        .slaves         = omap2420_timer9_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2420_timer9_slaves),
        .class          = &omap2xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 };
 /* timer10 */
@@ -648,10 +653,10 @@ static struct omap_hwmod omap2420_timer10_hwmod = {
                        .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
                },
        },
+        .dev_attr       = &capability_pwm_dev_attr,
        .slaves         = omap2420_timer10_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2420_timer10_slaves),
        .class          = &omap2xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 };
 /* timer11 */
@@ -685,10 +690,10 @@ static struct omap_hwmod omap2420_timer11_hwmod = {
                        .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
                },
        },
+        .dev_attr       = &capability_pwm_dev_attr,
        .slaves         = omap2420_timer11_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2420_timer11_slaves),
        .class          = &omap2xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 };
 /* timer12 */
@@ -722,10 +727,10 @@ static struct omap_hwmod omap2420_timer12_hwmod = {
                        .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
                },
        },
+        .dev_attr       = &capability_pwm_dev_attr,
        .slaves         = omap2420_timer12_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2420_timer12_slaves),
        .class          = &omap2xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 };
 /* l4_wkup -> wd_timer2 */
@@ -766,7 +771,6 @@ static struct omap_hwmod omap2420_wd_timer2_hwmod = {
        },
        .slaves         = omap2420_wd_timer2_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2420_wd_timer2_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 };
 /* UART1 */
@@ -792,7 +796,6 @@ static struct omap_hwmod omap2420_uart1_hwmod = {
        .slaves         = omap2420_uart1_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2420_uart1_slaves),
        .class          = &omap2_uart_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 };
 /* UART2 */
@@ -818,7 +821,6 @@ static struct omap_hwmod omap2420_uart2_hwmod = {
        .slaves         = omap2420_uart2_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2420_uart2_slaves),
        .class          = &omap2_uart_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 };
 /* UART3 */
@@ -844,7 +846,6 @@ static struct omap_hwmod omap2420_uart3_hwmod = {
        .slaves         = omap2420_uart3_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2420_uart3_slaves),
        .class          = &omap2_uart_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 };
 /* dss */
@@ -898,7 +899,6 @@ static struct omap_hwmod omap2420_dss_core_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap2420_dss_slaves),
        .masters        = omap2420_dss_masters,
        .masters_cnt    = ARRAY_SIZE(omap2420_dss_masters),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
        .flags          = HWMOD_NO_IDLEST,
 };
@@ -938,7 +938,6 @@ static struct omap_hwmod omap2420_dss_dispc_hwmod = {
        },
        .slaves         = omap2420_dss_dispc_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2420_dss_dispc_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
        .flags          = HWMOD_NO_IDLEST,
 };
@@ -975,7 +974,6 @@ static struct omap_hwmod omap2420_dss_rfbi_hwmod = {
        },
        .slaves         = omap2420_dss_rfbi_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2420_dss_rfbi_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
        .flags          = HWMOD_NO_IDLEST,
 };
@@ -1013,7 +1011,6 @@ static struct omap_hwmod omap2420_dss_venc_hwmod = {
        },
        .slaves         = omap2420_dss_venc_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2420_dss_venc_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
        .flags          = HWMOD_NO_IDLEST,
 };
@@ -1064,7 +1061,6 @@ static struct omap_hwmod omap2420_i2c1_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap2420_i2c1_slaves),
        .class          = &i2c_class,
        .dev_attr       = &i2c_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
        .flags          = HWMOD_16BIT_REG,
 };
@@ -1092,7 +1088,6 @@ static struct omap_hwmod omap2420_i2c2_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap2420_i2c2_slaves),
        .class          = &i2c_class,
        .dev_attr       = &i2c_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
        .flags          = HWMOD_16BIT_REG,
 };
@@ -1197,7 +1192,6 @@ static struct omap_hwmod omap2420_gpio1_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap2420_gpio1_slaves),
        .class          = &omap2xxx_gpio_hwmod_class,
        .dev_attr       = &gpio_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 };
 /* gpio2 */
@@ -1223,7 +1217,6 @@ static struct omap_hwmod omap2420_gpio2_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap2420_gpio2_slaves),
        .class          = &omap2xxx_gpio_hwmod_class,
        .dev_attr       = &gpio_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 };
 /* gpio3 */
@@ -1249,7 +1242,6 @@ static struct omap_hwmod omap2420_gpio3_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap2420_gpio3_slaves),
        .class          = &omap2xxx_gpio_hwmod_class,
        .dev_attr       = &gpio_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 };
 /* gpio4 */
@@ -1275,7 +1267,6 @@ static struct omap_hwmod omap2420_gpio4_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap2420_gpio4_slaves),
        .class          = &omap2xxx_gpio_hwmod_class,
        .dev_attr       = &gpio_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 };
 /* dma attributes */
@@ -1322,7 +1313,6 @@ static struct omap_hwmod omap2420_dma_system_hwmod = {
        .masters        = omap2420_dma_system_masters,
        .masters_cnt    = ARRAY_SIZE(omap2420_dma_system_masters),
        .dev_attr       = &dma_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
        .flags          = HWMOD_NO_IDLEST,
 };
@@ -1363,7 +1353,6 @@ static struct omap_hwmod omap2420_mailbox_hwmod = {
        },
        .slaves         = omap2420_mailbox_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2420_mailbox_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 };
 /* mcspi1 */
@@ -1393,7 +1382,6 @@ static struct omap_hwmod omap2420_mcspi1_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap2420_mcspi1_slaves),
        .class          = &omap2xxx_mcspi_class,
        .dev_attr       = &omap_mcspi1_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 };
 /* mcspi2 */
@@ -1423,7 +1411,6 @@ static struct omap_hwmod omap2420_mcspi2_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap2420_mcspi2_slaves),
        .class          = &omap2xxx_mcspi_class,
        .dev_attr       = &omap_mcspi2_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 };
 /*
@@ -1473,7 +1460,6 @@ static struct omap_hwmod omap2420_mcbsp1_hwmod = {
        },
        .slaves         = omap2420_mcbsp1_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2420_mcbsp1_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 };
 /* mcbsp2 */
@@ -1514,7 +1500,6 @@ static struct omap_hwmod omap2420_mcbsp2_hwmod = {
        },
        .slaves         = omap2420_mcbsp2_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2420_mcbsp2_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 };
 static __initdata struct omap_hwmod *omap2420_hwmods[] = {
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index 16743c7d6e8e..a2580d01c3ff 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -110,7 +110,6 @@ static struct omap_hwmod omap2430_l3_main_hwmod = {
        .masters_cnt    = ARRAY_SIZE(omap2430_l3_main_masters),
        .slaves         = omap2430_l3_main_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2430_l3_main_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
        .flags          = HWMOD_NO_IDLEST,
 };
@@ -192,6 +191,7 @@ static struct omap_hwmod_addr_space omap2430_usbhsotg_addrs[] = {
                .pa_end         = OMAP243X_HS_BASE + SZ_4K - 1,
                .flags          = ADDR_TYPE_RT
        },
+        { }
 };
 /*  l4_core ->usbhsotg  interface */
@@ -249,7 +249,6 @@ static struct omap_hwmod omap2430_l4_core_hwmod = {
        .masters_cnt    = ARRAY_SIZE(omap2430_l4_core_masters),
        .slaves         = omap2430_l4_core_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2430_l4_core_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
        .flags          = HWMOD_NO_IDLEST,
 };
@@ -300,7 +299,6 @@ static struct omap_hwmod omap2430_l4_wkup_hwmod = {
        .masters_cnt    = ARRAY_SIZE(omap2430_l4_wkup_masters),
        .slaves         = omap2430_l4_wkup_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2430_l4_wkup_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
        .flags          = HWMOD_NO_IDLEST,
 };
@@ -316,7 +314,6 @@ static struct omap_hwmod omap2430_mpu_hwmod = {
        .main_clk       = "mpu_ck",
        .masters        = omap2430_mpu_masters,
        .masters_cnt    = ARRAY_SIZE(omap2430_mpu_masters),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 /*
@@ -344,7 +341,16 @@ static struct omap_hwmod omap2430_iva_hwmod = {
        .class          = &iva_hwmod_class,
        .masters        = omap2430_iva_masters,
        .masters_cnt    = ARRAY_SIZE(omap2430_iva_masters),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+};
+/* always-on timers dev attribute */
+static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
+        .timer_capability       = OMAP_TIMER_ALWON,
+};
+/* pwm timers dev attribute */
+static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
+        .timer_capability       = OMAP_TIMER_HAS_PWM,
 };
 /* timer1 */
@@ -387,10 +393,10 @@ static struct omap_hwmod omap2430_timer1_hwmod = {
                        .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
                },
        },
+        .dev_attr       = &capability_alwon_dev_attr,
        .slaves         = omap2430_timer1_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2430_timer1_slaves),
        .class          = &omap2xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 };
 /* timer2 */
@@ -424,10 +430,10 @@ static struct omap_hwmod omap2430_timer2_hwmod = {
                        .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
                },
        },
+        .dev_attr       = &capability_alwon_dev_attr,
        .slaves         = omap2430_timer2_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2430_timer2_slaves),
        .class          = &omap2xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 };
 /* timer3 */
@@ -461,10 +467,10 @@ static struct omap_hwmod omap2430_timer3_hwmod = {
                        .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
                },
        },
+        .dev_attr       = &capability_alwon_dev_attr,
        .slaves         = omap2430_timer3_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2430_timer3_slaves),
        .class          = &omap2xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 };
 /* timer4 */
@@ -498,10 +504,10 @@ static struct omap_hwmod omap2430_timer4_hwmod = {
                        .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
                },
        },
+        .dev_attr       = &capability_alwon_dev_attr,
        .slaves         = omap2430_timer4_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2430_timer4_slaves),
        .class          = &omap2xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 };
 /* timer5 */
@@ -535,10 +541,10 @@ static struct omap_hwmod omap2430_timer5_hwmod = {
                        .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
                },
        },
+        .dev_attr       = &capability_alwon_dev_attr,
        .slaves         = omap2430_timer5_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2430_timer5_slaves),
        .class          = &omap2xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 };
 /* timer6 */
@@ -572,10 +578,10 @@ static struct omap_hwmod omap2430_timer6_hwmod = {
                        .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
                },
        },
+        .dev_attr       = &capability_alwon_dev_attr,
        .slaves         = omap2430_timer6_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2430_timer6_slaves),
        .class          = &omap2xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 };
 /* timer7 */
@@ -609,10 +615,10 @@ static struct omap_hwmod omap2430_timer7_hwmod = {
                        .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
                },
        },
+        .dev_attr       = &capability_alwon_dev_attr,
        .slaves         = omap2430_timer7_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2430_timer7_slaves),
        .class          = &omap2xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 };
 /* timer8 */
@@ -646,10 +652,10 @@ static struct omap_hwmod omap2430_timer8_hwmod = {
                        .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
                },
        },
+        .dev_attr       = &capability_alwon_dev_attr,
        .slaves         = omap2430_timer8_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2430_timer8_slaves),
        .class          = &omap2xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 };
 /* timer9 */
@@ -683,10 +689,10 @@ static struct omap_hwmod omap2430_timer9_hwmod = {
                        .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
                },
        },
+        .dev_attr       = &capability_pwm_dev_attr,
        .slaves         = omap2430_timer9_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2430_timer9_slaves),
        .class          = &omap2xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 };
 /* timer10 */
@@ -720,10 +726,10 @@ static struct omap_hwmod omap2430_timer10_hwmod = {
                        .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
                },
        },
+        .dev_attr       = &capability_pwm_dev_attr,
        .slaves         = omap2430_timer10_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2430_timer10_slaves),
        .class          = &omap2xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 };
 /* timer11 */
@@ -757,10 +763,10 @@ static struct omap_hwmod omap2430_timer11_hwmod = {
                        .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
                },
        },
+        .dev_attr       = &capability_pwm_dev_attr,
        .slaves         = omap2430_timer11_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2430_timer11_slaves),
        .class          = &omap2xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 };
 /* timer12 */
@@ -794,10 +800,10 @@ static struct omap_hwmod omap2430_timer12_hwmod = {
                        .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
                },
        },
+        .dev_attr       = &capability_pwm_dev_attr,
        .slaves         = omap2430_timer12_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2430_timer12_slaves),
        .class          = &omap2xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 };
 /* l4_wkup -> wd_timer2 */
@@ -838,7 +844,6 @@ static struct omap_hwmod omap2430_wd_timer2_hwmod = {
        },
        .slaves         = omap2430_wd_timer2_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2430_wd_timer2_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 /* UART1 */
@@ -864,7 +869,6 @@ static struct omap_hwmod omap2430_uart1_hwmod = {
        .slaves         = omap2430_uart1_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2430_uart1_slaves),
        .class          = &omap2_uart_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 /* UART2 */
@@ -890,7 +894,6 @@ static struct omap_hwmod omap2430_uart2_hwmod = {
        .slaves         = omap2430_uart2_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2430_uart2_slaves),
        .class          = &omap2_uart_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 /* UART3 */
@@ -916,7 +919,6 @@ static struct omap_hwmod omap2430_uart3_hwmod = {
        .slaves         = omap2430_uart3_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2430_uart3_slaves),
        .class          = &omap2_uart_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 /* dss */
@@ -964,7 +966,6 @@ static struct omap_hwmod omap2430_dss_core_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap2430_dss_slaves),
        .masters        = omap2430_dss_masters,
        .masters_cnt    = ARRAY_SIZE(omap2430_dss_masters),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
        .flags          = HWMOD_NO_IDLEST,
 };
@@ -998,7 +999,6 @@ static struct omap_hwmod omap2430_dss_dispc_hwmod = {
        },
        .slaves         = omap2430_dss_dispc_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2430_dss_dispc_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
        .flags          = HWMOD_NO_IDLEST,
 };
@@ -1029,7 +1029,6 @@ static struct omap_hwmod omap2430_dss_rfbi_hwmod = {
        },
        .slaves         = omap2430_dss_rfbi_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2430_dss_rfbi_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
        .flags          = HWMOD_NO_IDLEST,
 };
@@ -1061,7 +1060,6 @@ static struct omap_hwmod omap2430_dss_venc_hwmod = {
        },
        .slaves         = omap2430_dss_venc_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2430_dss_venc_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
        .flags          = HWMOD_NO_IDLEST,
 };
@@ -1122,7 +1120,6 @@ static struct omap_hwmod omap2430_i2c1_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap2430_i2c1_slaves),
        .class          = &i2c_class,
        .dev_attr       = &i2c_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 /* I2C2 */
@@ -1150,7 +1147,6 @@ static struct omap_hwmod omap2430_i2c2_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap2430_i2c2_slaves),
        .class          = &i2c_class,
        .dev_attr       = &i2c_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 /* l4_wkup -> gpio1 */
@@ -1272,7 +1268,6 @@ static struct omap_hwmod omap2430_gpio1_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap2430_gpio1_slaves),
        .class          = &omap2xxx_gpio_hwmod_class,
        .dev_attr       = &gpio_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 /* gpio2 */
@@ -1298,7 +1293,6 @@ static struct omap_hwmod omap2430_gpio2_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap2430_gpio2_slaves),
        .class          = &omap2xxx_gpio_hwmod_class,
        .dev_attr       = &gpio_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 /* gpio3 */
@@ -1324,7 +1318,6 @@ static struct omap_hwmod omap2430_gpio3_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap2430_gpio3_slaves),
        .class          = &omap2xxx_gpio_hwmod_class,
        .dev_attr       = &gpio_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 /* gpio4 */
@@ -1350,7 +1343,6 @@ static struct omap_hwmod omap2430_gpio4_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap2430_gpio4_slaves),
        .class          = &omap2xxx_gpio_hwmod_class,
        .dev_attr       = &gpio_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 /* gpio5 */
@@ -1381,7 +1373,6 @@ static struct omap_hwmod omap2430_gpio5_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap2430_gpio5_slaves),
        .class          = &omap2xxx_gpio_hwmod_class,
        .dev_attr       = &gpio_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 /* dma attributes */
@@ -1428,7 +1419,6 @@ static struct omap_hwmod omap2430_dma_system_hwmod = {
        .masters        = omap2430_dma_system_masters,
        .masters_cnt    = ARRAY_SIZE(omap2430_dma_system_masters),
        .dev_attr       = &dma_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
        .flags          = HWMOD_NO_IDLEST,
 };
@@ -1468,7 +1458,6 @@ static struct omap_hwmod omap2430_mailbox_hwmod = {
        },
        .slaves         = omap2430_mailbox_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2430_mailbox_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 /* mcspi1 */
@@ -1498,7 +1487,6 @@ static struct omap_hwmod omap2430_mcspi1_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap2430_mcspi1_slaves),
        .class          = &omap2xxx_mcspi_class,
        .dev_attr       = &omap_mcspi1_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 /* mcspi2 */
@@ -1528,7 +1516,6 @@ static struct omap_hwmod omap2430_mcspi2_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap2430_mcspi2_slaves),
        .class          = &omap2xxx_mcspi_class,
        .dev_attr       = &omap_mcspi2_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 /* mcspi3 */
@@ -1571,7 +1558,6 @@ static struct omap_hwmod omap2430_mcspi3_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap2430_mcspi3_slaves),
        .class          = &omap2xxx_mcspi_class,
        .dev_attr       = &omap_mcspi3_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 /*
@@ -1627,7 +1613,6 @@ static struct omap_hwmod omap2430_usbhsotg_hwmod = {
         */
        .flags          = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
                                | HWMOD_SWSUP_MSTANDBY,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 };
 /*
@@ -1688,7 +1673,6 @@ static struct omap_hwmod omap2430_mcbsp1_hwmod = {
        },
        .slaves         = omap2430_mcbsp1_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp1_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 /* mcbsp2 */
@@ -1730,7 +1714,6 @@ static struct omap_hwmod omap2430_mcbsp2_hwmod = {
        },
        .slaves         = omap2430_mcbsp2_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp2_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 /* mcbsp3 */
@@ -1782,7 +1765,6 @@ static struct omap_hwmod omap2430_mcbsp3_hwmod = {
        },
        .slaves         = omap2430_mcbsp3_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp3_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 /* mcbsp4 */
@@ -1840,7 +1822,6 @@ static struct omap_hwmod omap2430_mcbsp4_hwmod = {
        },
        .slaves         = omap2430_mcbsp4_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp4_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 /* mcbsp5 */
@@ -1898,7 +1879,6 @@ static struct omap_hwmod omap2430_mcbsp5_hwmod = {
        },
        .slaves         = omap2430_mcbsp5_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp5_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 /* MMC/SD/SDIO common */
@@ -1965,7 +1945,6 @@ static struct omap_hwmod omap2430_mmc1_hwmod = {
        .slaves         = omap2430_mmc1_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2430_mmc1_slaves),
        .class          = &omap2430_mmc_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 /* MMC/SD/SDIO2 */
@@ -2009,7 +1988,6 @@ static struct omap_hwmod omap2430_mmc2_hwmod = {
        .slaves         = omap2430_mmc2_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2430_mmc2_slaves),
        .class          = &omap2430_mmc_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 static __initdata struct omap_hwmod *omap2430_hwmods[] = {
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 25bf43b5a4ec..2e4852d9574f 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -156,7 +156,6 @@ static struct omap_hwmod omap3xxx_l3_main_hwmod = {
        .masters_cnt    = ARRAY_SIZE(omap3xxx_l3_main_masters),
        .slaves         = omap3xxx_l3_main_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_l3_main_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
        .flags          = HWMOD_NO_IDLEST,
 };
@@ -459,7 +458,6 @@ static struct omap_hwmod omap3xxx_l4_core_hwmod = {
        .class          = &l4_hwmod_class,
        .slaves         = omap3xxx_l4_core_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_core_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
        .flags          = HWMOD_NO_IDLEST,
 };
@@ -474,7 +472,6 @@ static struct omap_hwmod omap3xxx_l4_per_hwmod = {
        .class          = &l4_hwmod_class,
        .slaves         = omap3xxx_l4_per_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_per_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
        .flags          = HWMOD_NO_IDLEST,
 };
@@ -489,7 +486,6 @@ static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
        .class          = &l4_hwmod_class,
        .slaves         = omap3xxx_l4_wkup_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_wkup_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
        .flags          = HWMOD_NO_IDLEST,
 };
@@ -505,7 +501,6 @@ static struct omap_hwmod omap3xxx_mpu_hwmod = {
        .main_clk       = "arm_fck",
        .masters        = omap3xxx_mpu_masters,
        .masters_cnt    = ARRAY_SIZE(omap3xxx_mpu_masters),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 /*
@@ -533,7 +528,6 @@ static struct omap_hwmod omap3xxx_iva_hwmod = {
        .class          = &iva_hwmod_class,
        .masters        = omap3xxx_iva_masters,
        .masters_cnt    = ARRAY_SIZE(omap3xxx_iva_masters),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 };
 /* timer class */
@@ -570,6 +564,21 @@ static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
        .rev =  OMAP_TIMER_IP_VERSION_1,
 };
+/* secure timers dev attribute */
+static struct omap_timer_capability_dev_attr capability_secure_dev_attr = {
+        .timer_capability       = OMAP_TIMER_SECURE,
+};
+/* always-on timers dev attribute */
+static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
+        .timer_capability       = OMAP_TIMER_ALWON,
+};
+/* pwm timers dev attribute */
+static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
+        .timer_capability       = OMAP_TIMER_HAS_PWM,
+};
 /* timer1 */
 static struct omap_hwmod omap3xxx_timer1_hwmod;
@@ -610,10 +619,10 @@ static struct omap_hwmod omap3xxx_timer1_hwmod = {
                        .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
                },
        },
+        .dev_attr       = &capability_alwon_dev_attr,
        .slaves         = omap3xxx_timer1_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer1_slaves),
        .class          = &omap3xxx_timer_1ms_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 };
 /* timer2 */
@@ -656,10 +665,10 @@ static struct omap_hwmod omap3xxx_timer2_hwmod = {
                        .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
                },
        },
+        .dev_attr       = &capability_alwon_dev_attr,
        .slaves         = omap3xxx_timer2_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer2_slaves),
        .class          = &omap3xxx_timer_1ms_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 };
 /* timer3 */
@@ -702,10 +711,10 @@ static struct omap_hwmod omap3xxx_timer3_hwmod = {
                        .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
                },
        },
+        .dev_attr       = &capability_alwon_dev_attr,
        .slaves         = omap3xxx_timer3_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer3_slaves),
        .class          = &omap3xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 };
 /* timer4 */
@@ -748,10 +757,10 @@ static struct omap_hwmod omap3xxx_timer4_hwmod = {
                        .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
                },
        },
+        .dev_attr       = &capability_alwon_dev_attr,
        .slaves         = omap3xxx_timer4_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer4_slaves),
        .class          = &omap3xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 };
 /* timer5 */
@@ -794,10 +803,10 @@ static struct omap_hwmod omap3xxx_timer5_hwmod = {
                        .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
                },
        },
+        .dev_attr       = &capability_alwon_dev_attr,
        .slaves         = omap3xxx_timer5_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer5_slaves),
        .class          = &omap3xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 };
 /* timer6 */
@@ -840,10 +849,10 @@ static struct omap_hwmod omap3xxx_timer6_hwmod = {
                        .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
                },
        },
+        .dev_attr       = &capability_alwon_dev_attr,
        .slaves         = omap3xxx_timer6_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer6_slaves),
        .class          = &omap3xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 };
 /* timer7 */
@@ -886,10 +895,10 @@ static struct omap_hwmod omap3xxx_timer7_hwmod = {
                        .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
                },
        },
+        .dev_attr       = &capability_alwon_dev_attr,
        .slaves         = omap3xxx_timer7_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer7_slaves),
        .class          = &omap3xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 };
 /* timer8 */
@@ -932,10 +941,10 @@ static struct omap_hwmod omap3xxx_timer8_hwmod = {
                        .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
                },
        },
+        .dev_attr       = &capability_pwm_dev_attr,
        .slaves         = omap3xxx_timer8_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer8_slaves),
        .class          = &omap3xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 };
 /* timer9 */
@@ -978,10 +987,10 @@ static struct omap_hwmod omap3xxx_timer9_hwmod = {
                        .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
                },
        },
+        .dev_attr       = &capability_pwm_dev_attr,
        .slaves         = omap3xxx_timer9_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer9_slaves),
        .class          = &omap3xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 };
 /* timer10 */
@@ -1015,10 +1024,10 @@ static struct omap_hwmod omap3xxx_timer10_hwmod = {
                        .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
                },
        },
+        .dev_attr       = &capability_pwm_dev_attr,
        .slaves         = omap3xxx_timer10_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer10_slaves),
        .class          = &omap3xxx_timer_1ms_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 };
 /* timer11 */
@@ -1052,10 +1061,10 @@ static struct omap_hwmod omap3xxx_timer11_hwmod = {
                        .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
                },
        },
+        .dev_attr       = &capability_pwm_dev_attr,
        .slaves         = omap3xxx_timer11_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer11_slaves),
        .class          = &omap3xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 };
 /* timer12*/
@@ -1102,10 +1111,10 @@ static struct omap_hwmod omap3xxx_timer12_hwmod = {
                        .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
                },
        },
+        .dev_attr       = &capability_secure_dev_attr,
        .slaves         = omap3xxx_timer12_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer12_slaves),
        .class          = &omap3xxx_timer_hwmod_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 };
 /* l4_wkup -> wd_timer2 */
@@ -1182,7 +1191,6 @@ static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
        },
        .slaves         = omap3xxx_wd_timer2_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_wd_timer2_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
        /*
         * XXX: Use software supervised mode, HW supervised smartidle seems to
         * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
@@ -1213,7 +1221,6 @@ static struct omap_hwmod omap3xxx_uart1_hwmod = {
        .slaves         = omap3xxx_uart1_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart1_slaves),
        .class          = &omap2_uart_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 /* UART2 */
@@ -1239,7 +1246,6 @@ static struct omap_hwmod omap3xxx_uart2_hwmod = {
        .slaves         = omap3xxx_uart2_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart2_slaves),
        .class          = &omap2_uart_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 /* UART3 */
@@ -1265,7 +1271,6 @@ static struct omap_hwmod omap3xxx_uart3_hwmod = {
        .slaves         = omap3xxx_uart3_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart3_slaves),
        .class          = &omap2_uart_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 /* UART4 */
@@ -1302,7 +1307,6 @@ static struct omap_hwmod omap3xxx_uart4_hwmod = {
        .slaves         = omap3xxx_uart4_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart4_slaves),
        .class          = &omap2_uart_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
 };
 static struct omap_hwmod_class i2c_class = {
@@ -1390,7 +1394,6 @@ static struct omap_hwmod omap3430es1_dss_core_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap3430es1_dss_slaves),
        .masters        = omap3xxx_dss_masters,
        .masters_cnt    = ARRAY_SIZE(omap3xxx_dss_masters),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
        .flags          = HWMOD_NO_IDLEST,
 };
@@ -1415,8 +1418,6 @@ static struct omap_hwmod omap3xxx_dss_core_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_slaves),
        .masters        = omap3xxx_dss_masters,
        .masters_cnt    = ARRAY_SIZE(omap3xxx_dss_masters),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2 |
-                                CHIP_IS_OMAP3630ES1 | CHIP_GE_OMAP3630ES1_1),
 };
 /* l4_core -> dss_dispc */
@@ -1454,9 +1455,6 @@ static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
        },
        .slaves         = omap3xxx_dss_dispc_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_dispc_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
-                                CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
-                                CHIP_GE_OMAP3630ES1_1),
        .flags          = HWMOD_NO_IDLEST,
 };
@@ -1518,9 +1516,6 @@ static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
        },
        .slaves         = omap3xxx_dss_dsi1_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_dsi1_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
-                                CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
-                                CHIP_GE_OMAP3630ES1_1),
        .flags          = HWMOD_NO_IDLEST,
 };
@@ -1558,9 +1553,6 @@ static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
        },
        .slaves         = omap3xxx_dss_rfbi_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_rfbi_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
-                                CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
-                                CHIP_GE_OMAP3630ES1_1),
        .flags          = HWMOD_NO_IDLEST,
 };
@@ -1599,9 +1591,6 @@ static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
        },
        .slaves         = omap3xxx_dss_venc_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_venc_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
-                                CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
-                                CHIP_GE_OMAP3630ES1_1),
        .flags          = HWMOD_NO_IDLEST,
 };
@@ -1637,7 +1626,6 @@ static struct omap_hwmod omap3xxx_i2c1_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c1_slaves),
        .class          = &i2c_class,
        .dev_attr       = &i2c1_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 /* I2C2 */
@@ -1672,7 +1660,6 @@ static struct omap_hwmod omap3xxx_i2c2_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c2_slaves),
        .class          = &i2c_class,
        .dev_attr       = &i2c2_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 /* I2C3 */
@@ -1718,7 +1705,6 @@ static struct omap_hwmod omap3xxx_i2c3_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c3_slaves),
        .class          = &i2c_class,
        .dev_attr       = &i2c3_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 /* l4_wkup -> gpio1 */
@@ -1880,7 +1866,6 @@ static struct omap_hwmod omap3xxx_gpio1_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio1_slaves),
        .class          = &omap3xxx_gpio_hwmod_class,
        .dev_attr       = &gpio_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 /* gpio2 */
@@ -1912,7 +1897,6 @@ static struct omap_hwmod omap3xxx_gpio2_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio2_slaves),
        .class          = &omap3xxx_gpio_hwmod_class,
        .dev_attr       = &gpio_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 /* gpio3 */
@@ -1944,7 +1928,6 @@ static struct omap_hwmod omap3xxx_gpio3_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio3_slaves),
        .class          = &omap3xxx_gpio_hwmod_class,
        .dev_attr       = &gpio_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 /* gpio4 */
@@ -1976,7 +1959,6 @@ static struct omap_hwmod omap3xxx_gpio4_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio4_slaves),
        .class          = &omap3xxx_gpio_hwmod_class,
        .dev_attr       = &gpio_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 /* gpio5 */
@@ -2013,7 +1995,6 @@ static struct omap_hwmod omap3xxx_gpio5_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio5_slaves),
        .class          = &omap3xxx_gpio_hwmod_class,
        .dev_attr       = &gpio_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 /* gpio6 */
@@ -2050,7 +2031,6 @@ static struct omap_hwmod omap3xxx_gpio6_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio6_slaves),
        .class          = &omap3xxx_gpio_hwmod_class,
        .dev_attr       = &gpio_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 /* dma_system -> L3 */
@@ -2134,7 +2114,6 @@ static struct omap_hwmod omap3xxx_dma_system_hwmod = {
        .masters        = omap3xxx_dma_system_masters,
        .masters_cnt    = ARRAY_SIZE(omap3xxx_dma_system_masters),
        .dev_attr       = &dma_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
        .flags          = HWMOD_NO_IDLEST,
 };
@@ -2207,7 +2186,6 @@ static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
        },
        .slaves         = omap3xxx_mcbsp1_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp1_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 /* mcbsp2 */
@@ -2264,7 +2242,6 @@ static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
        .slaves         = omap3xxx_mcbsp2_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp2_slaves),
        .dev_attr       = &omap34xx_mcbsp2_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 /* mcbsp3 */
@@ -2321,7 +2298,6 @@ static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
        .slaves         = omap3xxx_mcbsp3_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp3_slaves),
        .dev_attr       = &omap34xx_mcbsp3_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 /* mcbsp4 */
@@ -2379,7 +2355,6 @@ static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
        },
        .slaves         = omap3xxx_mcbsp4_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp4_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 /* mcbsp5 */
@@ -2437,7 +2412,6 @@ static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
        },
        .slaves         = omap3xxx_mcbsp5_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp5_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 /* 'mcbsp sidetone' class */
@@ -2498,7 +2472,6 @@ static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
        },
        .slaves         = omap3xxx_mcbsp2_sidetone_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 /* mcbsp3_sidetone */
@@ -2547,7 +2520,6 @@ static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
        },
        .slaves         = omap3xxx_mcbsp3_sidetone_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
@@ -2609,9 +2581,6 @@ static struct omap_hwmod omap34xx_sr1_hwmod = {
        },
        .slaves         = omap3_sr1_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3_sr1_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |
-                                        CHIP_IS_OMAP3430ES3_0 |
-                                        CHIP_IS_OMAP3430ES3_1),
        .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 };
@@ -2631,7 +2600,6 @@ static struct omap_hwmod omap36xx_sr1_hwmod = {
        },
        .slaves         = omap3_sr1_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3_sr1_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
 };
 /* SR2 */
@@ -2655,9 +2623,6 @@ static struct omap_hwmod omap34xx_sr2_hwmod = {
        },
        .slaves         = omap3_sr2_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3_sr2_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |
-                                        CHIP_IS_OMAP3430ES3_0 |
-                                        CHIP_IS_OMAP3430ES3_1),
        .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 };
@@ -2677,7 +2642,6 @@ static struct omap_hwmod omap36xx_sr2_hwmod = {
        },
        .slaves         = omap3_sr2_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3_sr2_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
 };
 /*
@@ -2745,7 +2709,6 @@ static struct omap_hwmod omap3xxx_mailbox_hwmod = {
        },
        .slaves         = omap3xxx_mailbox_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_mailbox_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 /* l4 core -> mcspi1 interface */
@@ -2843,7 +2806,6 @@ static struct omap_hwmod omap34xx_mcspi1 = {
        .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi1_slaves),
        .class          = &omap34xx_mcspi_class,
        .dev_attr       = &omap_mcspi1_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 /* mcspi2 */
@@ -2873,7 +2835,6 @@ static struct omap_hwmod omap34xx_mcspi2 = {
        .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi2_slaves),
        .class          = &omap34xx_mcspi_class,
        .dev_attr       = &omap_mcspi2_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 /* mcspi3 */
@@ -2916,7 +2877,6 @@ static struct omap_hwmod omap34xx_mcspi3 = {
        .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi3_slaves),
        .class          = &omap34xx_mcspi_class,
        .dev_attr       = &omap_mcspi3_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 /* SPI4 */
@@ -2957,7 +2917,6 @@ static struct omap_hwmod omap34xx_mcspi4 = {
        .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi4_slaves),
        .class          = &omap34xx_mcspi_class,
        .dev_attr       = &omap_mcspi4_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 /*
@@ -3014,7 +2973,6 @@ static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
         */
        .flags          = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
                                | HWMOD_SWSUP_MSTANDBY,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 };
 /* usb_otg_hs */
@@ -3042,7 +3000,6 @@ static struct omap_hwmod am35xx_usbhsotg_hwmod = {
        .slaves         = am35xx_usbhsotg_slaves,
        .slaves_cnt     = ARRAY_SIZE(am35xx_usbhsotg_slaves),
        .class          = &am35xx_usbotg_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES3_1)
 };
 /* MMC/SD/SDIO common */
@@ -3108,7 +3065,6 @@ static struct omap_hwmod omap3xxx_mmc1_hwmod = {
        .slaves         = omap3xxx_mmc1_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc1_slaves),
        .class          = &omap34xx_mmc_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 /* MMC/SD/SDIO2 */
@@ -3151,7 +3107,6 @@ static struct omap_hwmod omap3xxx_mmc2_hwmod = {
        .slaves         = omap3xxx_mmc2_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc2_slaves),
        .class          = &omap34xx_mmc_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 /* MMC/SD/SDIO3 */
@@ -3193,7 +3148,6 @@ static struct omap_hwmod omap3xxx_mmc3_hwmod = {
        .slaves         = omap3xxx_mmc3_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc3_slaves),
        .class          = &omap34xx_mmc_class,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
@@ -3224,10 +3178,7 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
        &omap3xxx_uart1_hwmod,
        &omap3xxx_uart2_hwmod,
        &omap3xxx_uart3_hwmod,
-        &omap3xxx_uart4_hwmod,
        /* dss class */
-        &omap3430es1_dss_core_hwmod,
-        &omap3xxx_dss_core_hwmod,
        &omap3xxx_dss_dispc_hwmod,
        &omap3xxx_dss_dsi1_hwmod,
        &omap3xxx_dss_rfbi_hwmod,
@@ -3239,9 +3190,6 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
        &omap3xxx_i2c3_hwmod,
        &omap34xx_sr1_hwmod,
        &omap34xx_sr2_hwmod,
-        &omap36xx_sr1_hwmod,
-        &omap36xx_sr2_hwmod,
        /* gpio class */
        &omap3xxx_gpio1_hwmod,
@@ -3272,16 +3220,96 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
        &omap34xx_mcspi3,
        &omap34xx_mcspi4,
-        /* usbotg class */
+        NULL,
+};
+/* 3430ES1-only hwmods */
+static __initdata struct omap_hwmod *omap3430es1_hwmods[] = {
+        &omap3430es1_dss_core_hwmod,
+        NULL
+};
+/* 3430ES2+-only hwmods */
+static __initdata struct omap_hwmod *omap3430es2plus_hwmods[] = {
+        &omap3xxx_dss_core_hwmod,
        &omap3xxx_usbhsotg_hwmod,
+        NULL
+};
-        /* usbotg for am35x */
+/* 34xx-only hwmods (all ES revisions) */
-        &am35xx_usbhsotg_hwmod,
+static __initdata struct omap_hwmod *omap34xx_hwmods[] = {
+        &omap34xx_sr1_hwmod,
+        &omap34xx_sr2_hwmod,
+        NULL
+};
-        NULL,
+/* 36xx-only hwmods (all ES revisions) */
+static __initdata struct omap_hwmod *omap36xx_hwmods[] = {
+        &omap3xxx_uart4_hwmod,
+        &omap3xxx_dss_core_hwmod,
+        &omap36xx_sr1_hwmod,
+        &omap36xx_sr2_hwmod,
+        &omap3xxx_usbhsotg_hwmod,
+        NULL
+};
+static __initdata struct omap_hwmod *am35xx_hwmods[] = {
+        &omap3xxx_dss_core_hwmod, /* XXX ??? */
+        &am35xx_usbhsotg_hwmod,
+        NULL
 };
 int __init omap3xxx_hwmod_init(void)
 {
-        return omap_hwmod_register(omap3xxx_hwmods);
+        int r;
+        struct omap_hwmod **h = NULL;
+        unsigned int rev;
+        /* Register hwmods common to all OMAP3 */
+        r = omap_hwmod_register(omap3xxx_hwmods);
+        if (!r)
+                return r;
+        rev = omap_rev();
+        /*
+         * Register hwmods common to individual OMAP3 families, all
+         * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx)
+         * All possible revisions should be included in this conditional.
+         */
+        if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
+            rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
+            rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
+                h = omap34xx_hwmods;
+        } else if (rev == OMAP3517_REV_ES1_0 || rev == OMAP3517_REV_ES1_1) {
+                h = am35xx_hwmods;
+        } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
+                   rev == OMAP3630_REV_ES1_2) {
+                h = omap36xx_hwmods;
+        } else {
+                WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
+                return -EINVAL;
+        };
+        r = omap_hwmod_register(h);
+        if (!r)
+                return r;
+        /*
+         * Register hwmods specific to certain ES levels of a
+         * particular family of silicon (e.g., 34xx ES1.0)
+         */
+        h = NULL;
+        if (rev == OMAP3430_REV_ES1_0) {
+                h = omap3430es1_hwmods;
+        } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
+                   rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
+                   rev == OMAP3430_REV_ES3_1_2) {
+                h = omap3430es2plus_hwmods;
+        };
+        if (h)
+                r = omap_hwmod_register(h);
+        return r;
 }
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 6201422c0606..393afac9caf6 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -29,6 +29,7 @@
 #include <plat/mcbsp.h>
 #include <plat/mmc.h>
 #include <plat/i2c.h>
+#include <plat/dmtimer.h>
 #include "omap_hwmod_common_data.h"
@@ -133,7 +134,6 @@ static struct omap_hwmod omap44xx_dmm_hwmod = {
        .slaves         = omap44xx_dmm_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_dmm_slaves),
        .mpu_irqs       = omap44xx_dmm_irqs,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /*
@@ -189,7 +189,6 @@ static struct omap_hwmod omap44xx_emif_fw_hwmod = {
        },
        .slaves         = omap44xx_emif_fw_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_emif_fw_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /*
@@ -236,7 +235,6 @@ static struct omap_hwmod omap44xx_l3_instr_hwmod = {
        },
        .slaves         = omap44xx_l3_instr_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_instr_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* l3_main_1 */
@@ -336,7 +334,6 @@ static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
        },
        .slaves         = omap44xx_l3_main_1_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* l3_main_2 */
@@ -438,7 +435,6 @@ static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
        },
        .slaves         = omap44xx_l3_main_2_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_2_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* l3_main_3 */
@@ -496,7 +492,6 @@ static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
        },
        .slaves         = omap44xx_l3_main_3_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_3_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /*
@@ -559,7 +554,6 @@ static struct omap_hwmod omap44xx_l4_abe_hwmod = {
        },
        .slaves         = omap44xx_l4_abe_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_abe_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* l4_cfg */
@@ -588,7 +582,6 @@ static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
        },
        .slaves         = omap44xx_l4_cfg_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_cfg_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* l4_per */
@@ -617,7 +610,6 @@ static struct omap_hwmod omap44xx_l4_per_hwmod = {
        },
        .slaves         = omap44xx_l4_per_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_per_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* l4_wkup */
@@ -646,7 +638,6 @@ static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
        },
        .slaves         = omap44xx_l4_wkup_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_wkup_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /*
@@ -677,7 +668,6 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = {
        .clkdm_name     = "mpuss_clkdm",
        .slaves         = omap44xx_mpu_private_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_mpu_private_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /*
@@ -828,7 +818,6 @@ static struct omap_hwmod omap44xx_aess_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap44xx_aess_slaves),
        .masters        = omap44xx_aess_masters,
        .masters_cnt    = ARRAY_SIZE(omap44xx_aess_masters),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /*
@@ -856,7 +845,6 @@ static struct omap_hwmod omap44xx_bandgap_hwmod = {
        },
        .opt_clks       = bandgap_opt_clks,
        .opt_clks_cnt   = ARRAY_SIZE(bandgap_opt_clks),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /*
@@ -917,7 +905,6 @@ static struct omap_hwmod omap44xx_counter_32k_hwmod = {
        },
        .slaves         = omap44xx_counter_32k_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_counter_32k_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /*
@@ -1005,7 +992,6 @@ static struct omap_hwmod omap44xx_dma_system_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap44xx_dma_system_slaves),
        .masters        = omap44xx_dma_system_masters,
        .masters_cnt    = ARRAY_SIZE(omap44xx_dma_system_masters),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /*
@@ -1098,7 +1084,6 @@ static struct omap_hwmod omap44xx_dmic_hwmod = {
        },
        .slaves         = omap44xx_dmic_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_dmic_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /*
@@ -1164,7 +1149,6 @@ static struct omap_hwmod omap44xx_dsp_c0_hwmod = {
                        .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
                },
        },
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 static struct omap_hwmod omap44xx_dsp_hwmod = {
@@ -1187,7 +1171,6 @@ static struct omap_hwmod omap44xx_dsp_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap44xx_dsp_slaves),
        .masters        = omap44xx_dsp_masters,
        .masters_cnt    = ARRAY_SIZE(omap44xx_dsp_masters),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /*
@@ -1278,7 +1261,6 @@ static struct omap_hwmod omap44xx_dss_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_slaves),
        .masters        = omap44xx_dss_masters,
        .masters_cnt    = ARRAY_SIZE(omap44xx_dss_masters),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /*
@@ -1381,7 +1363,6 @@ static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
        .opt_clks_cnt   = ARRAY_SIZE(dss_dispc_opt_clks),
        .slaves         = omap44xx_dss_dispc_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dispc_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /*
@@ -1480,7 +1461,6 @@ static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
        .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
        .slaves         = omap44xx_dss_dsi1_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dsi1_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* dss_dsi2 */
@@ -1558,7 +1538,6 @@ static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
        .opt_clks_cnt   = ARRAY_SIZE(dss_dsi2_opt_clks),
        .slaves         = omap44xx_dss_dsi2_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dsi2_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /*
@@ -1656,7 +1635,6 @@ static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
        .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
        .slaves         = omap44xx_dss_hdmi_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_hdmi_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /*
@@ -1748,7 +1726,6 @@ static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
        .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
        .slaves         = omap44xx_dss_rfbi_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_rfbi_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /*
@@ -1817,7 +1794,6 @@ static struct omap_hwmod omap44xx_dss_venc_hwmod = {
        },
        .slaves         = omap44xx_dss_venc_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_venc_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /*
@@ -1901,7 +1877,6 @@ static struct omap_hwmod omap44xx_gpio1_hwmod = {
        .dev_attr       = &gpio_dev_attr,
        .slaves         = omap44xx_gpio1_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio1_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* gpio2 */
@@ -1957,7 +1932,6 @@ static struct omap_hwmod omap44xx_gpio2_hwmod = {
        .dev_attr       = &gpio_dev_attr,
        .slaves         = omap44xx_gpio2_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio2_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* gpio3 */
@@ -2013,7 +1987,6 @@ static struct omap_hwmod omap44xx_gpio3_hwmod = {
        .dev_attr       = &gpio_dev_attr,
        .slaves         = omap44xx_gpio3_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio3_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* gpio4 */
@@ -2069,7 +2042,6 @@ static struct omap_hwmod omap44xx_gpio4_hwmod = {
        .dev_attr       = &gpio_dev_attr,
        .slaves         = omap44xx_gpio4_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio4_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* gpio5 */
@@ -2125,7 +2097,6 @@ static struct omap_hwmod omap44xx_gpio5_hwmod = {
        .dev_attr       = &gpio_dev_attr,
        .slaves         = omap44xx_gpio5_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio5_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* gpio6 */
@@ -2181,7 +2152,6 @@ static struct omap_hwmod omap44xx_gpio6_hwmod = {
        .dev_attr       = &gpio_dev_attr,
        .slaves         = omap44xx_gpio6_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio6_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /*
@@ -2261,7 +2231,6 @@ static struct omap_hwmod omap44xx_hsi_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap44xx_hsi_slaves),
        .masters        = omap44xx_hsi_masters,
        .masters_cnt    = ARRAY_SIZE(omap44xx_hsi_masters),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /*
@@ -2345,7 +2314,6 @@ static struct omap_hwmod omap44xx_i2c1_hwmod = {
        .slaves         = omap44xx_i2c1_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c1_slaves),
        .dev_attr       = &i2c_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* i2c2 */
@@ -2402,7 +2370,6 @@ static struct omap_hwmod omap44xx_i2c2_hwmod = {
        .slaves         = omap44xx_i2c2_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c2_slaves),
        .dev_attr       = &i2c_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* i2c3 */
@@ -2459,7 +2426,6 @@ static struct omap_hwmod omap44xx_i2c3_hwmod = {
        .slaves         = omap44xx_i2c3_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c3_slaves),
        .dev_attr       = &i2c_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* i2c4 */
@@ -2516,7 +2482,6 @@ static struct omap_hwmod omap44xx_i2c4_hwmod = {
        .slaves         = omap44xx_i2c4_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c4_slaves),
        .dev_attr       = &i2c_dev_attr,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /*
@@ -2577,7 +2542,6 @@ static struct omap_hwmod omap44xx_ipu_c0_hwmod = {
                        .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
                },
        },
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* Pseudo hwmod for reset control purpose only */
@@ -2593,7 +2557,6 @@ static struct omap_hwmod omap44xx_ipu_c1_hwmod = {
                        .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
                },
        },
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 static struct omap_hwmod omap44xx_ipu_hwmod = {
@@ -2616,7 +2579,6 @@ static struct omap_hwmod omap44xx_ipu_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap44xx_ipu_slaves),
        .masters        = omap44xx_ipu_masters,
        .masters_cnt    = ARRAY_SIZE(omap44xx_ipu_masters),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /*
@@ -2706,7 +2668,6 @@ static struct omap_hwmod omap44xx_iss_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap44xx_iss_slaves),
        .masters        = omap44xx_iss_masters,
        .masters_cnt    = ARRAY_SIZE(omap44xx_iss_masters),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /*
@@ -2781,7 +2742,6 @@ static struct omap_hwmod omap44xx_iva_seq0_hwmod = {
                        .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
                },
        },
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* Pseudo hwmod for reset control purpose only */
@@ -2797,7 +2757,6 @@ static struct omap_hwmod omap44xx_iva_seq1_hwmod = {
                        .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
                },
        },
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 static struct omap_hwmod omap44xx_iva_hwmod = {
@@ -2820,7 +2779,6 @@ static struct omap_hwmod omap44xx_iva_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap44xx_iva_slaves),
        .masters        = omap44xx_iva_masters,
        .masters_cnt    = ARRAY_SIZE(omap44xx_iva_masters),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /*
@@ -2890,7 +2848,6 @@ static struct omap_hwmod omap44xx_kbd_hwmod = {
        },
        .slaves         = omap44xx_kbd_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_kbd_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /*
@@ -2956,7 +2913,6 @@ static struct omap_hwmod omap44xx_mailbox_hwmod = {
        },
        .slaves         = omap44xx_mailbox_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_mailbox_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /*
@@ -3051,7 +3007,6 @@ static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
        },
        .slaves         = omap44xx_mcbsp1_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp1_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* mcbsp2 */
@@ -3127,7 +3082,6 @@ static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
        },
        .slaves         = omap44xx_mcbsp2_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp2_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* mcbsp3 */
@@ -3203,7 +3157,6 @@ static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
        },
        .slaves         = omap44xx_mcbsp3_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp3_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* mcbsp4 */
@@ -3258,7 +3211,6 @@ static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
        },
        .slaves         = omap44xx_mcbsp4_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp4_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /*
@@ -3353,7 +3305,6 @@ static struct omap_hwmod omap44xx_mcpdm_hwmod = {
        },
        .slaves         = omap44xx_mcpdm_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_mcpdm_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /*
@@ -3442,7 +3393,6 @@ static struct omap_hwmod omap44xx_mcspi1_hwmod = {
        .dev_attr       = &mcspi1_dev_attr,
        .slaves         = omap44xx_mcspi1_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi1_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* mcspi2 */
@@ -3505,7 +3455,6 @@ static struct omap_hwmod omap44xx_mcspi2_hwmod = {
        .dev_attr       = &mcspi2_dev_attr,
        .slaves         = omap44xx_mcspi2_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi2_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* mcspi3 */
@@ -3568,7 +3517,6 @@ static struct omap_hwmod omap44xx_mcspi3_hwmod = {
        .dev_attr       = &mcspi3_dev_attr,
        .slaves         = omap44xx_mcspi3_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi3_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* mcspi4 */
@@ -3629,7 +3577,6 @@ static struct omap_hwmod omap44xx_mcspi4_hwmod = {
        .dev_attr       = &mcspi4_dev_attr,
        .slaves         = omap44xx_mcspi4_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi4_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /*
@@ -3718,7 +3665,6 @@ static struct omap_hwmod omap44xx_mmc1_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc1_slaves),
        .masters        = omap44xx_mmc1_masters,
        .masters_cnt    = ARRAY_SIZE(omap44xx_mmc1_masters),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* mmc2 */
@@ -3779,7 +3725,6 @@ static struct omap_hwmod omap44xx_mmc2_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc2_slaves),
        .masters        = omap44xx_mmc2_masters,
        .masters_cnt    = ARRAY_SIZE(omap44xx_mmc2_masters),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* mmc3 */
@@ -3834,7 +3779,6 @@ static struct omap_hwmod omap44xx_mmc3_hwmod = {
        },
        .slaves         = omap44xx_mmc3_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc3_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* mmc4 */
@@ -3890,7 +3834,6 @@ static struct omap_hwmod omap44xx_mmc4_hwmod = {
        },
        .slaves         = omap44xx_mmc4_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc4_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* mmc5 */
@@ -3945,7 +3888,6 @@ static struct omap_hwmod omap44xx_mmc5_hwmod = {
        },
        .slaves         = omap44xx_mmc5_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc5_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /*
@@ -3987,7 +3929,6 @@ static struct omap_hwmod omap44xx_mpu_hwmod = {
        },
        .masters        = omap44xx_mpu_masters,
        .masters_cnt    = ARRAY_SIZE(omap44xx_mpu_masters),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /*
@@ -4063,7 +4004,6 @@ static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
        },
        .slaves         = omap44xx_smartreflex_core_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_core_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* smartreflex_iva */
@@ -4112,7 +4052,6 @@ static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
        },
        .slaves         = omap44xx_smartreflex_iva_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_iva_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* smartreflex_mpu */
@@ -4161,7 +4100,6 @@ static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
        },
        .slaves         = omap44xx_smartreflex_mpu_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /*
@@ -4224,7 +4162,6 @@ static struct omap_hwmod omap44xx_spinlock_hwmod = {
        },
        .slaves         = omap44xx_spinlock_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_spinlock_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /*
@@ -4265,6 +4202,16 @@ static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
        .sysc   = &omap44xx_timer_sysc,
 };
+/* always-on timers dev attribute */
+static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
+        .timer_capability       = OMAP_TIMER_ALWON,
+};
+/* pwm timers dev attribute */
+static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
+        .timer_capability       = OMAP_TIMER_HAS_PWM,
+};
 /* timer1 */
 static struct omap_hwmod omap44xx_timer1_hwmod;
 static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
@@ -4308,9 +4255,9 @@ static struct omap_hwmod omap44xx_timer1_hwmod = {
                        .modulemode   = MODULEMODE_SWCTRL,
                },
        },
+        .dev_attr       = &capability_alwon_dev_attr,
        .slaves         = omap44xx_timer1_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_timer1_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* timer2 */
@@ -4356,9 +4303,9 @@ static struct omap_hwmod omap44xx_timer2_hwmod = {
                        .modulemode   = MODULEMODE_SWCTRL,
                },
        },
+        .dev_attr       = &capability_alwon_dev_attr,
        .slaves         = omap44xx_timer2_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_timer2_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* timer3 */
@@ -4404,9 +4351,9 @@ static struct omap_hwmod omap44xx_timer3_hwmod = {
                        .modulemode   = MODULEMODE_SWCTRL,
                },
        },
+        .dev_attr       = &capability_alwon_dev_attr,
        .slaves         = omap44xx_timer3_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_timer3_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* timer4 */
@@ -4452,9 +4399,9 @@ static struct omap_hwmod omap44xx_timer4_hwmod = {
                        .modulemode   = MODULEMODE_SWCTRL,
                },
        },
+        .dev_attr       = &capability_alwon_dev_attr,
        .slaves         = omap44xx_timer4_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_timer4_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* timer5 */
@@ -4519,9 +4466,9 @@ static struct omap_hwmod omap44xx_timer5_hwmod = {
                        .modulemode   = MODULEMODE_SWCTRL,
                },
        },
+        .dev_attr       = &capability_alwon_dev_attr,
        .slaves         = omap44xx_timer5_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_timer5_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* timer6 */
@@ -4587,9 +4534,9 @@ static struct omap_hwmod omap44xx_timer6_hwmod = {
                        .modulemode   = MODULEMODE_SWCTRL,
                },
        },
+        .dev_attr       = &capability_alwon_dev_attr,
        .slaves         = omap44xx_timer6_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_timer6_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* timer7 */
@@ -4654,9 +4601,9 @@ static struct omap_hwmod omap44xx_timer7_hwmod = {
                        .modulemode   = MODULEMODE_SWCTRL,
                },
        },
+        .dev_attr       = &capability_alwon_dev_attr,
        .slaves         = omap44xx_timer7_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_timer7_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* timer8 */
@@ -4721,9 +4668,9 @@ static struct omap_hwmod omap44xx_timer8_hwmod = {
                        .modulemode   = MODULEMODE_SWCTRL,
                },
        },
+        .dev_attr       = &capability_pwm_dev_attr,
        .slaves         = omap44xx_timer8_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_timer8_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* timer9 */
@@ -4769,9 +4716,9 @@ static struct omap_hwmod omap44xx_timer9_hwmod = {
                        .modulemode   = MODULEMODE_SWCTRL,
                },
        },
+        .dev_attr       = &capability_pwm_dev_attr,
        .slaves         = omap44xx_timer9_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_timer9_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* timer10 */
@@ -4817,9 +4764,9 @@ static struct omap_hwmod omap44xx_timer10_hwmod = {
                        .modulemode   = MODULEMODE_SWCTRL,
                },
        },
+        .dev_attr       = &capability_pwm_dev_attr,
        .slaves         = omap44xx_timer10_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_timer10_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* timer11 */
@@ -4865,9 +4812,9 @@ static struct omap_hwmod omap44xx_timer11_hwmod = {
                        .modulemode   = MODULEMODE_SWCTRL,
                },
        },
+        .dev_attr       = &capability_pwm_dev_attr,
        .slaves         = omap44xx_timer11_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_timer11_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /*
@@ -4944,7 +4891,6 @@ static struct omap_hwmod omap44xx_uart1_hwmod = {
        },
        .slaves         = omap44xx_uart1_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_uart1_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* uart2 */
@@ -4999,7 +4945,6 @@ static struct omap_hwmod omap44xx_uart2_hwmod = {
        },
        .slaves         = omap44xx_uart2_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_uart2_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* uart3 */
@@ -5055,7 +5000,6 @@ static struct omap_hwmod omap44xx_uart3_hwmod = {
        },
        .slaves         = omap44xx_uart3_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_uart3_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* uart4 */
@@ -5110,7 +5054,6 @@ static struct omap_hwmod omap44xx_uart4_hwmod = {
        },
        .slaves         = omap44xx_uart4_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_uart4_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /*
@@ -5195,7 +5138,6 @@ static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap44xx_usb_otg_hs_slaves),
        .masters        = omap44xx_usb_otg_hs_masters,
        .masters_cnt    = ARRAY_SIZE(omap44xx_usb_otg_hs_masters),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /*
@@ -5266,7 +5208,6 @@ static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
        },
        .slaves         = omap44xx_wd_timer2_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_wd_timer2_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 /* wd_timer3 */
@@ -5333,7 +5274,6 @@ static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
        },
        .slaves         = omap44xx_wd_timer3_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap44xx_wd_timer3_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 3feb35911a32..472bf22d5e84 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -130,7 +130,6 @@ int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
                } else {
                        hwsup = clkdm_in_hwsup(pwrdm->pwrdm_clkdms[0]);
                        clkdm_wakeup(pwrdm->pwrdm_clkdms[0]);
-                        pwrdm_wait_transition(pwrdm);
                        sleep_switch = FORCEWAKEUP_SWITCH;
                }
        }
@@ -156,7 +155,6 @@ int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
                return ret;
        }
-        pwrdm_wait_transition(pwrdm);
        pwrdm_state_switch(pwrdm);
 err:
        return ret;
diff --git a/arch/arm/mach-omap2/powerdomain-common.c b/arch/arm/mach-omap2/powerdomain-common.c
index 171fccd208c7..f97afff68d6d 100644
--- a/arch/arm/mach-omap2/powerdomain-common.c
+++ b/arch/arm/mach-omap2/powerdomain-common.c
@@ -1,9 +1,8 @@
 /*
- *  linux/arch/arm/mach-omap2/powerdomain-common.c
+ * Common powerdomain framework functions
- *  Contains common powerdomain framework functions
 *
- *  Copyright (C) 2010 Texas Instruments, Inc.
+ * Copyright (C) 2010-2011 Texas Instruments, Inc.
- *  Copyright (C) 2010 Nokia Corporation
+ * Copyright (C) 2010 Nokia Corporation
 *
 * Derived from mach-omap2/powerdomain.c written by Paul Walmsley
 *
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index 9af08473bf10..896cb4c5eb1a 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -1,7 +1,7 @@
 /*
 * OMAP powerdomain control
 *
- * Copyright (C) 2007-2008 Texas Instruments, Inc.
+ * Copyright (C) 2007-2008, 2011 Texas Instruments, Inc.
 * Copyright (C) 2007-2011 Nokia Corporation
 *
 * Written by Paul Walmsley
@@ -81,9 +81,6 @@ static int _pwrdm_register(struct powerdomain *pwrdm)
        if (!pwrdm || !pwrdm->name)
                return -EINVAL;
-        if (!omap_chip_is(pwrdm->omap_chip))
-                return -EINVAL;
        if (cpu_is_omap44xx() &&
            pwrdm->prcm_partition == OMAP4430_INVALID_PRCM_PARTITION) {
                pr_err("powerdomain: %s: missing OMAP4 PRCM partition ID\n",
@@ -194,29 +191,76 @@ static int _pwrdm_post_transition_cb(struct powerdomain *pwrdm, void *unused)
 /* Public functions */
 /**
- * pwrdm_init - set up the powerdomain layer
+ * pwrdm_register_platform_funcs - register powerdomain implementation fns
- * @pwrdm_list: array of struct powerdomain pointers to register
+ * @po: func pointers for arch specific implementations
- * @custom_funcs: func pointers for arch specific implementations
 *
- * Loop through the array of powerdomains @pwrdm_list, registering all
+ * Register the list of function pointers used to implement the
- * that are available on the current CPU. If pwrdm_list is supplied
+ * powerdomain functions on different OMAP SoCs.  Should be called
- * and not null, all of the referenced powerdomains will be
+ * before any other pwrdm_register*() function.  Returns -EINVAL if
- * registered.  No return value.  XXX pwrdm_list is not really a
+ * @po is null, -EEXIST if platform functions have already been
- * "list"; it is an array.  Rename appropriately.
+ * registered, or 0 upon success.
 */
-void pwrdm_init(struct powerdomain **pwrdm_list, struct pwrdm_ops *custom_funcs)
+int pwrdm_register_platform_funcs(struct pwrdm_ops *po)
+{
+        if (!po)
+                return -EINVAL;
+        if (arch_pwrdm)
+                return -EEXIST;
+        arch_pwrdm = po;
+        return 0;
+}
+/**
+ * pwrdm_register_pwrdms - register SoC powerdomains
+ * @ps: pointer to an array of struct powerdomain to register
+ *
+ * Register the powerdomains available on a particular OMAP SoC.  Must
+ * be called after pwrdm_register_platform_funcs().  May be called
+ * multiple times.  Returns -EACCES if called before
+ * pwrdm_register_platform_funcs(); -EINVAL if the argument @ps is
+ * null; or 0 upon success.
+ */
+int pwrdm_register_pwrdms(struct powerdomain **ps)
 {
        struct powerdomain **p = NULL;
-        if (!custom_funcs)
+        if (!arch_pwrdm)
-                WARN(1, "powerdomain: No custom pwrdm functions registered\n");
+                return -EEXIST;
-        else
-                arch_pwrdm = custom_funcs;
+        if (!ps)
+                return -EINVAL;
+        for (p = ps; *p; p++)
+                _pwrdm_register(*p);
-        if (pwrdm_list) {
+        return 0;
-                for (p = pwrdm_list; *p; p++)
+}
-                        _pwrdm_register(*p);
-        }
+/**
+ * pwrdm_complete_init - set up the powerdomain layer
+ *
+ * Do whatever is necessary to initialize registered powerdomains and
+ * powerdomain code.  Currently, this programs the next power state
+ * for each powerdomain to ON.  This prevents powerdomains from
+ * unexpectedly losing context or entering high wakeup latency modes
+ * with non-power-management-enabled kernels.  Must be called after
+ * pwrdm_register_pwrdms().  Returns -EACCES if called before
+ * pwrdm_register_pwrdms(), or 0 upon success.
+ */
+int pwrdm_complete_init(void)
+{
+        struct powerdomain *temp_p;
+        if (list_empty(&pwrdm_list))
+                return -EACCES;
+        list_for_each_entry(temp_p, &pwrdm_list, node)
+                pwrdm_set_next_pwrst(temp_p, PWRDM_POWER_ON);
+        return 0;
 }
 /**
diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h
index d23d979b9c34..8febd84e5e31 100644
--- a/arch/arm/mach-omap2/powerdomain.h
+++ b/arch/arm/mach-omap2/powerdomain.h
@@ -78,7 +78,6 @@ struct powerdomain;
 /**
 * struct powerdomain - OMAP powerdomain
 * @name: Powerdomain name
- * @omap_chip: represents the OMAP chip types containing this pwrdm
 * @prcm_offs: the address offset from CM_BASE/PRM_BASE
 * @prcm_partition: (OMAP4 only) the PRCM partition ID containing @prcm_offs
 * @pwrsts: Possible powerdomain power states
@@ -98,7 +97,6 @@ struct powerdomain;
 */
 struct powerdomain {
        const char *name;
-        const struct omap_chip_id omap_chip;
        const s16 prcm_offs;
        const u8 pwrsts;
        const u8 pwrsts_logic_ret;
@@ -162,7 +160,9 @@ struct pwrdm_ops {
        int     (*pwrdm_wait_transition)(struct powerdomain *pwrdm);
 };
-void pwrdm_init(struct powerdomain **pwrdm_list, struct pwrdm_ops *custom_funcs);
+int pwrdm_register_platform_funcs(struct pwrdm_ops *custom_funcs);
+int pwrdm_register_pwrdms(struct powerdomain **pwrdm_list);
+int pwrdm_complete_init(void);
 struct powerdomain *pwrdm_lookup(const char *name);
@@ -210,7 +210,8 @@ int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm);
 u32 pwrdm_get_context_loss_count(struct powerdomain *pwrdm);
 bool pwrdm_can_ever_lose_context(struct powerdomain *pwrdm);
-extern void omap2xxx_powerdomains_init(void);
+extern void omap242x_powerdomains_init(void);
+extern void omap243x_powerdomains_init(void);
 extern void omap3xxx_powerdomains_init(void);
 extern void omap44xx_powerdomains_init(void);
diff --git a/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c b/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c
index 4210c3399769..bf30483d5cb0 100644
--- a/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c
+++ b/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c
@@ -1,7 +1,7 @@
 /*
 * OMAP2/3 common powerdomain definitions
 *
- * Copyright (C) 2007-2008 Texas Instruments, Inc.
+ * Copyright (C) 2007-2008, 2011 Texas Instruments, Inc.
 * Copyright (C) 2007-2011 Nokia Corporation
 *
 * Paul Walmsley, Jouni Högander
@@ -12,20 +12,6 @@
 */
 /*
- * To Do List
- * -> Move the Sleep/Wakeup dependencies from Power Domain framework to
- *    Clock Domain Framework
- */
-/*
- * This file contains all of the powerdomains that have some element
- * of software control for the OMAP24xx and OMAP34xx chips.
- *
- * This is not an exhaustive listing of powerdomains on the chips; only
- * powerdomains that can be controlled in software.
- */
-/*
 * The names for the DSP/IVA2 powerdomains are confusing.
 *
 * Most OMAP chips have an on-board DSP.
@@ -59,8 +45,6 @@
 struct powerdomain gfx_omap2_pwrdm = {
        .name             = "gfx_pwrdm",
        .prcm_offs        = GFX_MOD,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX |
-                                           CHIP_IS_OMAP3430ES1),
        .pwrsts           = PWRSTS_OFF_RET_ON,
        .pwrsts_logic_ret = PWRSTS_RET,
        .banks            = 1,
@@ -75,6 +59,5 @@ struct powerdomain gfx_omap2_pwrdm = {
 struct powerdomain wkup_omap2_pwrdm = {
        .name           = "wkup_pwrdm",
        .prcm_offs      = WKUP_MOD,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
        .pwrsts         = PWRSTS_ON,
 };
diff --git a/arch/arm/mach-omap2/powerdomains2xxx_data.c b/arch/arm/mach-omap2/powerdomains2xxx_data.c
index cc389fb2005d..bb4394e3b621 100644
--- a/arch/arm/mach-omap2/powerdomains2xxx_data.c
+++ b/arch/arm/mach-omap2/powerdomains2xxx_data.c
@@ -1,7 +1,7 @@
 /*
 * OMAP2XXX powerdomain definitions
 *
- * Copyright (C) 2007-2008 Texas Instruments, Inc.
+ * Copyright (C) 2007-2008, 2011 Texas Instruments, Inc.
 * Copyright (C) 2007-2011 Nokia Corporation
 *
 * Paul Walmsley, Jouni Högander
@@ -28,7 +28,6 @@
 static struct powerdomain dsp_pwrdm = {
        .name             = "dsp_pwrdm",
        .prcm_offs        = OMAP24XX_DSP_MOD,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
        .pwrsts           = PWRSTS_OFF_RET_ON,
        .pwrsts_logic_ret = PWRSTS_RET,
        .banks            = 1,
@@ -43,7 +42,6 @@ static struct powerdomain dsp_pwrdm = {
 static struct powerdomain mpu_24xx_pwrdm = {
        .name             = "mpu_pwrdm",
        .prcm_offs        = MPU_MOD,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
        .pwrsts           = PWRSTS_OFF_RET_ON,
        .pwrsts_logic_ret = PWRSTS_OFF_RET,
        .banks            = 1,
@@ -58,7 +56,6 @@ static struct powerdomain mpu_24xx_pwrdm = {
 static struct powerdomain core_24xx_pwrdm = {
        .name             = "core_pwrdm",
        .prcm_offs        = CORE_MOD,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
        .pwrsts           = PWRSTS_OFF_RET_ON,
        .banks            = 3,
        .pwrsts_mem_ret   = {
@@ -78,14 +75,11 @@ static struct powerdomain core_24xx_pwrdm = {
 * 2430-specific powerdomains
 */
-#ifdef CONFIG_SOC_OMAP2430
 /* XXX 2430 KILLDOMAINWKUP bit?  No current users apparently */
 static struct powerdomain mdm_pwrdm = {
        .name             = "mdm_pwrdm",
        .prcm_offs        = OMAP2430_MDM_MOD,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
        .pwrsts           = PWRSTS_OFF_RET_ON,
        .pwrsts_logic_ret = PWRSTS_RET,
        .banks            = 1,
@@ -97,27 +91,41 @@ static struct powerdomain mdm_pwrdm = {
        },
 };
-#endif     /* CONFIG_SOC_OMAP2430 */
+/*
+ *
-/* As powerdomains are added or removed above, this list must also be changed */
+ */
-static struct powerdomain *powerdomains_omap2xxx[] __initdata = {
+static struct powerdomain *powerdomains_omap24xx[] __initdata = {
        &wkup_omap2_pwrdm,
        &gfx_omap2_pwrdm,
-#ifdef CONFIG_ARCH_OMAP2
        &dsp_pwrdm,
        &mpu_24xx_pwrdm,
        &core_24xx_pwrdm,
-#endif
+        NULL
+};
-#ifdef CONFIG_SOC_OMAP2430
+static struct powerdomain *powerdomains_omap2430[] __initdata = {
        &mdm_pwrdm,
-#endif
        NULL
 };
-void __init omap2xxx_powerdomains_init(void)
+void __init omap242x_powerdomains_init(void)
+{
+        if (!cpu_is_omap2420())
+                return;
+        pwrdm_register_platform_funcs(&omap2_pwrdm_operations);
+        pwrdm_register_pwrdms(powerdomains_omap24xx);
+        pwrdm_complete_init();
+}
+void __init omap243x_powerdomains_init(void)
 {
-        pwrdm_init(powerdomains_omap2xxx, &omap2_pwrdm_operations);
+        if (!cpu_is_omap2430())
+                return;
+        pwrdm_register_platform_funcs(&omap2_pwrdm_operations);
+        pwrdm_register_pwrdms(powerdomains_omap24xx);
+        pwrdm_register_pwrdms(powerdomains_omap2430);
+        pwrdm_complete_init();
 }
diff --git a/arch/arm/mach-omap2/powerdomains3xxx_data.c b/arch/arm/mach-omap2/powerdomains3xxx_data.c
index 469a920a74dc..e4f3a7d6ecfc 100644
--- a/arch/arm/mach-omap2/powerdomains3xxx_data.c
+++ b/arch/arm/mach-omap2/powerdomains3xxx_data.c
@@ -1,7 +1,7 @@
 /*
 * OMAP3 powerdomain definitions
 *
- * Copyright (C) 2007-2008 Texas Instruments, Inc.
+ * Copyright (C) 2007-2008, 2011 Texas Instruments, Inc.
 * Copyright (C) 2007-2011 Nokia Corporation
 *
 * Paul Walmsley, Jouni Högander
@@ -14,6 +14,8 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <plat/cpu.h>
 #include "powerdomain.h"
 #include "powerdomains2xxx_3xxx_data.h"
@@ -27,8 +29,6 @@
 * 34XX-specific powerdomains, dependencies
 */
-#ifdef CONFIG_ARCH_OMAP3
 /*
 * Powerdomains
 */
@@ -36,7 +36,6 @@
 static struct powerdomain iva2_pwrdm = {
        .name             = "iva2_pwrdm",
        .prcm_offs        = OMAP3430_IVA2_MOD,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
        .pwrsts           = PWRSTS_OFF_RET_ON,
        .pwrsts_logic_ret = PWRSTS_OFF_RET,
        .banks            = 4,
@@ -57,7 +56,6 @@ static struct powerdomain iva2_pwrdm = {
 static struct powerdomain mpu_3xxx_pwrdm = {
        .name             = "mpu_pwrdm",
        .prcm_offs        = MPU_MOD,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
        .pwrsts           = PWRSTS_OFF_RET_ON,
        .pwrsts_logic_ret = PWRSTS_OFF_RET,
        .flags            = PWRDM_HAS_MPU_QUIRK,
@@ -83,10 +81,6 @@ static struct powerdomain mpu_3xxx_pwrdm = {
 static struct powerdomain core_3xxx_pre_es3_1_pwrdm = {
        .name             = "core_pwrdm",
        .prcm_offs        = CORE_MOD,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
-                                           CHIP_IS_OMAP3430ES2 |
-                                           CHIP_IS_OMAP3430ES3_0 |
-                                           CHIP_IS_OMAP3630ES1),
        .pwrsts           = PWRSTS_OFF_RET_ON,
        .pwrsts_logic_ret = PWRSTS_OFF_RET,
        .banks            = 2,
@@ -103,8 +97,6 @@ static struct powerdomain core_3xxx_pre_es3_1_pwrdm = {
 static struct powerdomain core_3xxx_es3_1_pwrdm = {
        .name             = "core_pwrdm",
        .prcm_offs        = CORE_MOD,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES3_1 |
-                                          CHIP_GE_OMAP3630ES1_1),
        .pwrsts           = PWRSTS_OFF_RET_ON,
        .pwrsts_logic_ret = PWRSTS_OFF_RET,
        /*
@@ -125,7 +117,6 @@ static struct powerdomain core_3xxx_es3_1_pwrdm = {
 static struct powerdomain dss_pwrdm = {
        .name             = "dss_pwrdm",
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
        .prcm_offs        = OMAP3430_DSS_MOD,
        .pwrsts           = PWRSTS_OFF_RET_ON,
        .pwrsts_logic_ret = PWRSTS_RET,
@@ -146,7 +137,6 @@ static struct powerdomain dss_pwrdm = {
 static struct powerdomain sgx_pwrdm = {
        .name             = "sgx_pwrdm",
        .prcm_offs        = OMAP3430ES2_SGX_MOD,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
        /* XXX This is accurate for 3430 SGX, but what about GFX? */
        .pwrsts           = PWRSTS_OFF_ON,
        .pwrsts_logic_ret = PWRSTS_RET,
@@ -161,7 +151,6 @@ static struct powerdomain sgx_pwrdm = {
 static struct powerdomain cam_pwrdm = {
        .name             = "cam_pwrdm",
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
        .prcm_offs        = OMAP3430_CAM_MOD,
        .pwrsts           = PWRSTS_OFF_RET_ON,
        .pwrsts_logic_ret = PWRSTS_RET,
@@ -177,7 +166,6 @@ static struct powerdomain cam_pwrdm = {
 static struct powerdomain per_pwrdm = {
        .name             = "per_pwrdm",
        .prcm_offs        = OMAP3430_PER_MOD,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
        .pwrsts           = PWRSTS_OFF_RET_ON,
        .pwrsts_logic_ret = PWRSTS_OFF_RET,
        .banks            = 1,
@@ -192,13 +180,11 @@ static struct powerdomain per_pwrdm = {
 static struct powerdomain emu_pwrdm = {
        .name           = "emu_pwrdm",
        .prcm_offs      = OMAP3430_EMU_MOD,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 static struct powerdomain neon_pwrdm = {
        .name             = "neon_pwrdm",
        .prcm_offs        = OMAP3430_NEON_MOD,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
        .pwrsts           = PWRSTS_OFF_RET_ON,
        .pwrsts_logic_ret = PWRSTS_RET,
 };
@@ -206,7 +192,6 @@ static struct powerdomain neon_pwrdm = {
 static struct powerdomain usbhost_pwrdm = {
        .name             = "usbhost_pwrdm",
        .prcm_offs        = OMAP3430ES2_USBHOST_MOD,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
        .pwrsts           = PWRSTS_OFF_RET_ON,
        .pwrsts_logic_ret = PWRSTS_RET,
        /*
@@ -228,60 +213,92 @@ static struct powerdomain usbhost_pwrdm = {
 static struct powerdomain dpll1_pwrdm = {
        .name           = "dpll1_pwrdm",
        .prcm_offs      = MPU_MOD,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 static struct powerdomain dpll2_pwrdm = {
        .name           = "dpll2_pwrdm",
        .prcm_offs      = OMAP3430_IVA2_MOD,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 static struct powerdomain dpll3_pwrdm = {
        .name           = "dpll3_pwrdm",
        .prcm_offs      = PLL_MOD,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 static struct powerdomain dpll4_pwrdm = {
        .name           = "dpll4_pwrdm",
        .prcm_offs      = PLL_MOD,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 static struct powerdomain dpll5_pwrdm = {
        .name           = "dpll5_pwrdm",
        .prcm_offs      = PLL_MOD,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
 };
 /* As powerdomains are added or removed above, this list must also be changed */
-static struct powerdomain *powerdomains_omap3xxx[] __initdata = {
+static struct powerdomain *powerdomains_omap3430_common[] __initdata = {
        &wkup_omap2_pwrdm,
-        &gfx_omap2_pwrdm,
        &iva2_pwrdm,
        &mpu_3xxx_pwrdm,
        &neon_pwrdm,
-        &core_3xxx_pre_es3_1_pwrdm,
-        &core_3xxx_es3_1_pwrdm,
        &cam_pwrdm,
        &dss_pwrdm,
        &per_pwrdm,
        &emu_pwrdm,
-        &sgx_pwrdm,
-        &usbhost_pwrdm,
        &dpll1_pwrdm,
        &dpll2_pwrdm,
        &dpll3_pwrdm,
        &dpll4_pwrdm,
+        NULL
+};
+static struct powerdomain *powerdomains_omap3430es1[] __initdata = {
+        &gfx_omap2_pwrdm,
+        &core_3xxx_pre_es3_1_pwrdm,
+        NULL
+};
+/* also includes 3630ES1.0 */
+static struct powerdomain *powerdomains_omap3430es2_es3_0[] __initdata = {
+        &core_3xxx_pre_es3_1_pwrdm,
+        &sgx_pwrdm,
+        &usbhost_pwrdm,
        &dpll5_pwrdm,
-#endif
        NULL
 };
+/* also includes 3630ES1.1+ */
+static struct powerdomain *powerdomains_omap3430es3_1plus[] __initdata = {
+        &core_3xxx_es3_1_pwrdm,
+        &sgx_pwrdm,
+        &usbhost_pwrdm,
+        &dpll5_pwrdm,
+        NULL
+};
 void __init omap3xxx_powerdomains_init(void)
 {
-        pwrdm_init(powerdomains_omap3xxx, &omap3_pwrdm_operations);
+        unsigned int rev;
+        if (!cpu_is_omap34xx())
+                return;
+        pwrdm_register_platform_funcs(&omap3_pwrdm_operations);
+        pwrdm_register_pwrdms(powerdomains_omap3430_common);
+        rev = omap_rev();
+        if (rev == OMAP3430_REV_ES1_0)
+                pwrdm_register_pwrdms(powerdomains_omap3430es1);
+        else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
+                 rev == OMAP3430_REV_ES3_0 || rev == OMAP3630_REV_ES1_0)
+                pwrdm_register_pwrdms(powerdomains_omap3430es2_es3_0);
+        else if (rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2 ||
+                 rev == OMAP3517_REV_ES1_0 || rev == OMAP3517_REV_ES1_1 ||
+                 rev == OMAP3630_REV_ES1_1 || rev == OMAP3630_REV_ES1_2)
+                pwrdm_register_pwrdms(powerdomains_omap3430es3_1plus);
+        else
+                WARN(1, "OMAP3 powerdomain init: unknown chip type\n");
+        pwrdm_complete_init();
 }
diff --git a/arch/arm/mach-omap2/powerdomains44xx_data.c b/arch/arm/mach-omap2/powerdomains44xx_data.c
index 247e79495115..cbce0c9069cd 100644
--- a/arch/arm/mach-omap2/powerdomains44xx_data.c
+++ b/arch/arm/mach-omap2/powerdomains44xx_data.c
@@ -35,7 +35,6 @@ static struct powerdomain core_44xx_pwrdm = {
        .name             = "core_pwrdm",
        .prcm_offs        = OMAP4430_PRM_CORE_INST,
        .prcm_partition   = OMAP4430_PRM_PARTITION,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
        .pwrsts           = PWRSTS_RET_ON,
        .pwrsts_logic_ret = PWRSTS_OFF_RET,
        .banks            = 5,
@@ -61,7 +60,6 @@ static struct powerdomain gfx_44xx_pwrdm = {
        .name             = "gfx_pwrdm",
        .prcm_offs        = OMAP4430_PRM_GFX_INST,
        .prcm_partition   = OMAP4430_PRM_PARTITION,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
        .pwrsts           = PWRSTS_OFF_ON,
        .banks            = 1,
        .pwrsts_mem_ret = {
@@ -78,7 +76,6 @@ static struct powerdomain abe_44xx_pwrdm = {
        .name             = "abe_pwrdm",
        .prcm_offs        = OMAP4430_PRM_ABE_INST,
        .prcm_partition   = OMAP4430_PRM_PARTITION,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
        .pwrsts           = PWRSTS_OFF_RET_ON,
        .pwrsts_logic_ret = PWRSTS_OFF,
        .banks            = 2,
@@ -98,7 +95,6 @@ static struct powerdomain dss_44xx_pwrdm = {
        .name             = "dss_pwrdm",
        .prcm_offs        = OMAP4430_PRM_DSS_INST,
        .prcm_partition   = OMAP4430_PRM_PARTITION,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
        .pwrsts           = PWRSTS_OFF_RET_ON,
        .pwrsts_logic_ret = PWRSTS_OFF,
        .banks            = 1,
@@ -116,7 +112,6 @@ static struct powerdomain tesla_44xx_pwrdm = {
        .name             = "tesla_pwrdm",
        .prcm_offs        = OMAP4430_PRM_TESLA_INST,
        .prcm_partition   = OMAP4430_PRM_PARTITION,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
        .pwrsts           = PWRSTS_OFF_RET_ON,
        .pwrsts_logic_ret = PWRSTS_OFF_RET,
        .banks            = 3,
@@ -138,7 +133,6 @@ static struct powerdomain wkup_44xx_pwrdm = {
        .name             = "wkup_pwrdm",
        .prcm_offs        = OMAP4430_PRM_WKUP_INST,
        .prcm_partition   = OMAP4430_PRM_PARTITION,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
        .pwrsts           = PWRSTS_ON,
        .banks            = 1,
        .pwrsts_mem_ret = {
@@ -154,7 +148,6 @@ static struct powerdomain cpu0_44xx_pwrdm = {
        .name             = "cpu0_pwrdm",
        .prcm_offs        = OMAP4430_PRCM_MPU_CPU0_INST,
        .prcm_partition   = OMAP4430_PRCM_MPU_PARTITION,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
        .pwrsts           = PWRSTS_OFF_RET_ON,
        .pwrsts_logic_ret = PWRSTS_OFF_RET,
        .banks            = 1,
@@ -171,7 +164,6 @@ static struct powerdomain cpu1_44xx_pwrdm = {
        .name             = "cpu1_pwrdm",
        .prcm_offs        = OMAP4430_PRCM_MPU_CPU1_INST,
        .prcm_partition   = OMAP4430_PRCM_MPU_PARTITION,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
        .pwrsts           = PWRSTS_OFF_RET_ON,
        .pwrsts_logic_ret = PWRSTS_OFF_RET,
        .banks            = 1,
@@ -188,7 +180,6 @@ static struct powerdomain emu_44xx_pwrdm = {
        .name             = "emu_pwrdm",
        .prcm_offs        = OMAP4430_PRM_EMU_INST,
        .prcm_partition   = OMAP4430_PRM_PARTITION,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
        .pwrsts           = PWRSTS_OFF_ON,
        .banks            = 1,
        .pwrsts_mem_ret = {
@@ -204,7 +195,6 @@ static struct powerdomain mpu_44xx_pwrdm = {
        .name             = "mpu_pwrdm",
        .prcm_offs        = OMAP4430_PRM_MPU_INST,
        .prcm_partition   = OMAP4430_PRM_PARTITION,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
        .pwrsts           = PWRSTS_RET_ON,
        .pwrsts_logic_ret = PWRSTS_OFF_RET,
        .banks            = 3,
@@ -225,7 +215,6 @@ static struct powerdomain ivahd_44xx_pwrdm = {
        .name             = "ivahd_pwrdm",
        .prcm_offs        = OMAP4430_PRM_IVAHD_INST,
        .prcm_partition   = OMAP4430_PRM_PARTITION,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
        .pwrsts           = PWRSTS_OFF_RET_ON,
        .pwrsts_logic_ret = PWRSTS_OFF,
        .banks            = 4,
@@ -249,7 +238,6 @@ static struct powerdomain cam_44xx_pwrdm = {
        .name             = "cam_pwrdm",
        .prcm_offs        = OMAP4430_PRM_CAM_INST,
        .prcm_partition   = OMAP4430_PRM_PARTITION,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
        .pwrsts           = PWRSTS_OFF_ON,
        .banks            = 1,
        .pwrsts_mem_ret = {
@@ -266,7 +254,6 @@ static struct powerdomain l3init_44xx_pwrdm = {
        .name             = "l3init_pwrdm",
        .prcm_offs        = OMAP4430_PRM_L3INIT_INST,
        .prcm_partition   = OMAP4430_PRM_PARTITION,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
        .pwrsts           = PWRSTS_RET_ON,
        .pwrsts_logic_ret = PWRSTS_OFF_RET,
        .banks            = 1,
@@ -284,7 +271,6 @@ static struct powerdomain l4per_44xx_pwrdm = {
        .name             = "l4per_pwrdm",
        .prcm_offs        = OMAP4430_PRM_L4PER_INST,
        .prcm_partition   = OMAP4430_PRM_PARTITION,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
        .pwrsts           = PWRSTS_RET_ON,
        .pwrsts_logic_ret = PWRSTS_OFF_RET,
        .banks            = 2,
@@ -307,7 +293,6 @@ static struct powerdomain always_on_core_44xx_pwrdm = {
        .name             = "always_on_core_pwrdm",
        .prcm_offs        = OMAP4430_PRM_ALWAYS_ON_INST,
        .prcm_partition   = OMAP4430_PRM_PARTITION,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
        .pwrsts           = PWRSTS_ON,
 };
@@ -316,7 +301,6 @@ static struct powerdomain cefuse_44xx_pwrdm = {
        .name             = "cefuse_pwrdm",
        .prcm_offs        = OMAP4430_PRM_CEFUSE_INST,
        .prcm_partition   = OMAP4430_PRM_PARTITION,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
        .pwrsts           = PWRSTS_OFF_ON,
        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
 };
@@ -352,5 +336,7 @@ static struct powerdomain *powerdomains_omap44xx[] __initdata = {
 void __init omap44xx_powerdomains_init(void)
 {
-        pwrdm_init(powerdomains_omap44xx, &omap4_pwrdm_operations);
+        pwrdm_register_platform_funcs(&omap4_pwrdm_operations);
+        pwrdm_register_pwrdms(powerdomains_omap44xx);
+        pwrdm_complete_init();
 }
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index cf1de7d2630d..1140e98c9773 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -35,6 +35,7 @@
 #include <linux/irq.h>
 #include <linux/clocksource.h>
 #include <linux/clockchips.h>
+#include <linux/slab.h>
 #include <asm/mach/time.h>
 #include <plat/dmtimer.h>
@@ -42,6 +43,10 @@
 #include <asm/sched_clock.h>
 #include <plat/common.h>
 #include <plat/omap_hwmod.h>
+#include <plat/omap_device.h>
+#include <plat/omap-pm.h>
+#include "powerdomain.h"
 /* Parent clocks, eventually these will come from the clock framework */
@@ -67,7 +72,7 @@
 /* MAX_GPTIMER_ID: number of GPTIMERs on the chip */
 #define MAX_GPTIMER_ID          12
-u32 sys_timer_reserved;
+static u32 sys_timer_reserved;
 /* Clockevent code */
@@ -78,7 +83,7 @@ static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
 {
        struct clock_event_device *evt = &clockevent_gpt;
-        __omap_dm_timer_write_status(clkev.io_base, OMAP_TIMER_INT_OVERFLOW);
+        __omap_dm_timer_write_status(&clkev, OMAP_TIMER_INT_OVERFLOW);
        evt->event_handler(evt);
        return IRQ_HANDLED;
@@ -93,7 +98,7 @@ static struct irqaction omap2_gp_timer_irq = {
 static int omap2_gp_timer_set_next_event(unsigned long cycles,
                                         struct clock_event_device *evt)
 {
-        __omap_dm_timer_load_start(clkev.io_base, OMAP_TIMER_CTRL_ST,
+        __omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST,
                                                0xffffffff - cycles, 1);
        return 0;
@@ -104,16 +109,16 @@ static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
 {
        u32 period;
-        __omap_dm_timer_stop(clkev.io_base, 1, clkev.rate);
+        __omap_dm_timer_stop(&clkev, 1, clkev.rate);
        switch (mode) {
        case CLOCK_EVT_MODE_PERIODIC:
                period = clkev.rate / HZ;
                period -= 1;
                /* Looks like we need to first set the load value separately */
-                __omap_dm_timer_write(clkev.io_base, OMAP_TIMER_LOAD_REG,
+                __omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG,
                                        0xffffffff - period, 1);
-                __omap_dm_timer_load_start(clkev.io_base,
+                __omap_dm_timer_load_start(&clkev,
                                        OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST,
                                                0xffffffff - period, 1);
                break;
@@ -189,7 +194,8 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
                        clk_put(src);
                }
        }
-        __omap_dm_timer_reset(timer->io_base, 1, 1);
+        __omap_dm_timer_init_regs(timer);
+        __omap_dm_timer_reset(timer, 1, 1);
        timer->posted = 1;
        timer->rate = clk_get_rate(timer->fclk);
@@ -210,7 +216,7 @@ static void __init omap2_gp_clockevent_init(int gptimer_id,
        omap2_gp_timer_irq.dev_id = (void *)&clkev;
        setup_irq(clkev.irq, &omap2_gp_timer_irq);
-        __omap_dm_timer_int_enable(clkev.io_base, OMAP_TIMER_INT_OVERFLOW);
+        __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW);
        clockevent_gpt.mult = div_sc(clkev.rate, NSEC_PER_SEC,
                                     clockevent_gpt.shift);
@@ -251,7 +257,7 @@ static struct omap_dm_timer clksrc;
 static DEFINE_CLOCK_DATA(cd);
 static cycle_t clocksource_read_cycles(struct clocksource *cs)
 {
-        return (cycle_t)__omap_dm_timer_read_counter(clksrc.io_base, 1);
+        return (cycle_t)__omap_dm_timer_read_counter(&clksrc, 1);
 }
 static struct clocksource clocksource_gpt = {
@@ -266,7 +272,7 @@ static void notrace dmtimer_update_sched_clock(void)
 {
        u32 cyc;
-        cyc = __omap_dm_timer_read_counter(clksrc.io_base, 1);
+        cyc = __omap_dm_timer_read_counter(&clksrc, 1);
        update_sched_clock(&cd, cyc, (u32)~0);
 }
@@ -276,7 +282,7 @@ unsigned long long notrace sched_clock(void)
        u32 cyc = 0;
        if (clksrc.reserved)
-                cyc = __omap_dm_timer_read_counter(clksrc.io_base, 1);
+                cyc = __omap_dm_timer_read_counter(&clksrc, 1);
        return cyc_to_sched_clock(&cd, cyc, (u32)~0);
 }
@@ -293,7 +299,7 @@ static void __init omap2_gp_clocksource_init(int gptimer_id,
        pr_info("OMAP clocksource: GPTIMER%d at %lu Hz\n",
                gptimer_id, clksrc.rate);
-        __omap_dm_timer_load_start(clksrc.io_base,
+        __omap_dm_timer_load_start(&clksrc,
                        OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0, 1);
        init_sched_clock(&cd, dmtimer_update_sched_clock, 32, clksrc.rate);
@@ -341,3 +347,167 @@ static void __init omap4_timer_init(void)
 }
 OMAP_SYS_TIMER(4)
 #endif
+/**
+ * omap2_dm_timer_set_src - change the timer input clock source
+ * @pdev:       timer platform device pointer
+ * @source:     array index of parent clock source
+ */
+static int omap2_dm_timer_set_src(struct platform_device *pdev, int source)
+{
+        int ret;
+        struct dmtimer_platform_data *pdata = pdev->dev.platform_data;
+        struct clk *fclk, *parent;
+        char *parent_name = NULL;
+        fclk = clk_get(&pdev->dev, "fck");
+        if (IS_ERR_OR_NULL(fclk)) {
+                dev_err(&pdev->dev, "%s: %d: clk_get() FAILED\n",
+                                __func__, __LINE__);
+                return -EINVAL;
+        }
+        switch (source) {
+        case OMAP_TIMER_SRC_SYS_CLK:
+                parent_name = "sys_ck";
+                break;
+        case OMAP_TIMER_SRC_32_KHZ:
+                parent_name = "32k_ck";
+                break;
+        case OMAP_TIMER_SRC_EXT_CLK:
+                if (pdata->timer_ip_version == OMAP_TIMER_IP_VERSION_1) {
+                        parent_name = "alt_ck";
+                        break;
+                }
+                dev_err(&pdev->dev, "%s: %d: invalid clk src.\n",
+                        __func__, __LINE__);
+                clk_put(fclk);
+                return -EINVAL;
+        }
+        parent = clk_get(&pdev->dev, parent_name);
+        if (IS_ERR_OR_NULL(parent)) {
+                dev_err(&pdev->dev, "%s: %d: clk_get() %s FAILED\n",
+                        __func__, __LINE__, parent_name);
+                clk_put(fclk);
+                return -EINVAL;
+        }
+        ret = clk_set_parent(fclk, parent);
+        if (IS_ERR_VALUE(ret)) {
+                dev_err(&pdev->dev, "%s: clk_set_parent() to %s FAILED\n",
+                        __func__, parent_name);
+                ret = -EINVAL;
+        }
+        clk_put(parent);
+        clk_put(fclk);
+        return ret;
+}
+struct omap_device_pm_latency omap2_dmtimer_latency[] = {
+        {
+                .deactivate_func = omap_device_idle_hwmods,
+                .activate_func   = omap_device_enable_hwmods,
+                .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
+        },
+};
+/**
+ * omap_timer_init - build and register timer device with an
+ * associated timer hwmod
+ * @oh: timer hwmod pointer to be used to build timer device
+ * @user:       parameter that can be passed from calling hwmod API
+ *
+ * Called by omap_hwmod_for_each_by_class to register each of the timer
+ * devices present in the system. The number of timer devices is known
+ * by parsing through the hwmod database for a given class name. At the
+ * end of function call memory is allocated for timer device and it is
+ * registered to the framework ready to be proved by the driver.
+ */
+static int __init omap_timer_init(struct omap_hwmod *oh, void *unused)
+{
+        int id;
+        int ret = 0;
+        char *name = "omap_timer";
+        struct dmtimer_platform_data *pdata;
+        struct omap_device *od;
+        struct omap_timer_capability_dev_attr *timer_dev_attr;
+        struct powerdomain *pwrdm;
+        pr_debug("%s: %s\n", __func__, oh->name);
+        /* on secure device, do not register secure timer */
+        timer_dev_attr = oh->dev_attr;
+        if (omap_type() != OMAP2_DEVICE_TYPE_GP && timer_dev_attr)
+                if (timer_dev_attr->timer_capability == OMAP_TIMER_SECURE)
+                        return ret;
+        pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
+        if (!pdata) {
+                pr_err("%s: No memory for [%s]\n", __func__, oh->name);
+                return -ENOMEM;
+        }
+        /*
+         * Extract the IDs from name field in hwmod database
+         * and use the same for constructing ids' for the
+         * timer devices. In a way, we are avoiding usage of
+         * static variable witin the function to do the same.
+         * CAUTION: We have to be careful and make sure the
+         * name in hwmod database does not change in which case
+         * we might either make corresponding change here or
+         * switch back static variable mechanism.
+         */
+        sscanf(oh->name, "timer%2d", &id);
+        pdata->set_timer_src = omap2_dm_timer_set_src;
+        pdata->timer_ip_version = oh->class->rev;
+        /* Mark clocksource and clockevent timers as reserved */
+        if ((sys_timer_reserved >> (id - 1)) & 0x1)
+                pdata->reserved = 1;
+        pwrdm = omap_hwmod_get_pwrdm(oh);
+        pdata->loses_context = pwrdm_can_ever_lose_context(pwrdm);
+#ifdef CONFIG_PM
+        pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count;
+#endif
+        od = omap_device_build(name, id, oh, pdata, sizeof(*pdata),
+                        omap2_dmtimer_latency,
+                        ARRAY_SIZE(omap2_dmtimer_latency),
+                        0);
+        if (IS_ERR(od)) {
+                pr_err("%s: Can't build omap_device for %s: %s.\n",
+                        __func__, name, oh->name);
+                ret = -EINVAL;
+        }
+        kfree(pdata);
+        return ret;
+}
+/**
+ * omap2_dm_timer_init - top level regular device initialization
+ *
+ * Uses dedicated hwmod api to parse through hwmod database for
+ * given class name and then build and register the timer device.
+ */
+static int __init omap2_dm_timer_init(void)
+{
+        int ret;
+        ret = omap_hwmod_for_each_by_class("timer", omap_timer_init, NULL);
+        if (unlikely(ret)) {
+                pr_err("%s: device registration failed.\n", __func__);
+                return -EINVAL;
+        }
+        return 0;
+}
+arch_initcall(omap2_dm_timer_init);
diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c
index a6eddae82a0b..c105556a0ee1 100644
--- a/arch/arm/mach-orion5x/dns323-setup.c
+++ b/arch/arm/mach-orion5x/dns323-setup.c
@@ -77,7 +77,7 @@ static int __init dns323_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
        /*
         * Check for devices with hard-wired IRQs.
         */
-        irq = orion5x_pci_map_irq(const dev, slot, pin);
+        irq = orion5x_pci_map_irq(dev, slot, pin);
        if (irq != -1)
                return irq;
diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c
index 28b8760ab9fa..bc4a920e26ee 100644
--- a/arch/arm/mach-orion5x/pci.c
+++ b/arch/arm/mach-orion5x/pci.c
@@ -14,6 +14,7 @@
 #include <linux/pci.h>
 #include <linux/slab.h>
 #include <linux/mbus.h>
+#include <video/vga.h>
 #include <asm/irq.h>
 #include <asm/mach/pci.h>
 #include <plat/pcie.h>
diff --git a/arch/arm/mach-prima2/clock.c b/arch/arm/mach-prima2/clock.c
index f9a2aaf63f71..615a4e75ceab 100644
--- a/arch/arm/mach-prima2/clock.c
+++ b/arch/arm/mach-prima2/clock.c
@@ -481,6 +481,7 @@ static void __init sirfsoc_clk_init(void)
 static struct of_device_id clkc_ids[] = {
        { .compatible = "sirf,prima2-clkc" },
+        {},
 };
 void __init sirfsoc_of_clk_init(void)
diff --git a/arch/arm/mach-prima2/irq.c b/arch/arm/mach-prima2/irq.c
index c3404cbb6ff7..7af254d046ba 100644
--- a/arch/arm/mach-prima2/irq.c
+++ b/arch/arm/mach-prima2/irq.c
@@ -51,6 +51,7 @@ static __init void sirfsoc_irq_init(void)
 static struct of_device_id intc_ids[]  = {
        { .compatible = "sirf,prima2-intc" },
+        {},
 };
 void __init sirfsoc_of_irq_init(void)
diff --git a/arch/arm/mach-prima2/rstc.c b/arch/arm/mach-prima2/rstc.c
index d074786e83d4..492cfa8d2610 100644
--- a/arch/arm/mach-prima2/rstc.c
+++ b/arch/arm/mach-prima2/rstc.c
@@ -19,6 +19,7 @@ static DEFINE_MUTEX(rstc_lock);
 static struct of_device_id rstc_ids[]  = {
        { .compatible = "sirf,prima2-rstc" },
+        {},
 };
 static int __init sirfsoc_of_rstc_init(void)
diff --git a/arch/arm/mach-prima2/timer.c b/arch/arm/mach-prima2/timer.c
index 44027f34a88a..ed7ec48d11da 100644
--- a/arch/arm/mach-prima2/timer.c
+++ b/arch/arm/mach-prima2/timer.c
@@ -190,6 +190,7 @@ static void __init sirfsoc_timer_init(void)
 static struct of_device_id timer_ids[] = {
        { .compatible = "sirf,prima2-tick" },
+        {},
 };
 static void __init sirfsoc_of_timer_map(void)
diff --git a/arch/arm/mach-realview/include/mach/system.h b/arch/arm/mach-realview/include/mach/system.h
index a30f2e3ec178..6657ff231161 100644
--- a/arch/arm/mach-realview/include/mach/system.h
+++ b/arch/arm/mach-realview/include/mach/system.h
@@ -44,6 +44,7 @@ static inline void arch_reset(char mode, const char *cmd)
         */
        if (realview_reset)
                realview_reset(mode);
+        dsb();
 }
 #endif
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c
index ecbea92bf83b..a9f3183e0290 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
@@ -262,45 +262,6 @@ static struct samsung_keypad_platdata smdk6410_keypad_data __initdata = {
        .cols           = 8,
 };
-static int smdk6410_backlight_init(struct device *dev)
-{
-        int ret;
-        ret = gpio_request(S3C64XX_GPF(15), "Backlight");
-        if (ret) {
-                printk(KERN_ERR "failed to request GPF for PWM-OUT1\n");
-                return ret;
-        }
-        /* Configure GPIO pin with S3C64XX_GPF15_PWM_TOUT1 */
-        s3c_gpio_cfgpin(S3C64XX_GPF(15), S3C_GPIO_SFN(2));
-        return 0;
-}
-static void smdk6410_backlight_exit(struct device *dev)
-{
-        s3c_gpio_cfgpin(S3C64XX_GPF(15), S3C_GPIO_OUTPUT);
-        gpio_free(S3C64XX_GPF(15));
-}
-static struct platform_pwm_backlight_data smdk6410_backlight_data = {
-        .pwm_id         = 1,
-        .max_brightness = 255,
-        .dft_brightness = 255,
-        .pwm_period_ns  = 78770,
-        .init           = smdk6410_backlight_init,
-        .exit           = smdk6410_backlight_exit,
-};
-static struct platform_device smdk6410_backlight_device = {
-        .name           = "pwm-backlight",
-        .dev            = {
-                .parent         = &s3c_device_timer[1].dev,
-                .platform_data  = &smdk6410_backlight_data,
-        },
-};
 static struct map_desc smdk6410_iodesc[] = {};
 static struct platform_device *smdk6410_devices[] __initdata = {
diff --git a/arch/arm/mach-s3c64xx/pm.c b/arch/arm/mach-s3c64xx/pm.c
index 8bad64370689..055e2858b0dd 100644
--- a/arch/arm/mach-s3c64xx/pm.c
+++ b/arch/arm/mach-s3c64xx/pm.c
@@ -16,6 +16,7 @@
 #include <linux/suspend.h>
 #include <linux/serial_core.h>
 #include <linux/io.h>
+#include <linux/gpio.h>
 #include <mach/map.h>
 #include <mach/irqs.h>
diff --git a/arch/arm/mach-s5p64x0/irq-eint.c b/arch/arm/mach-s5p64x0/irq-eint.c
index 69ed4545112b..fe7380f5c3cd 100644
--- a/arch/arm/mach-s5p64x0/irq-eint.c
+++ b/arch/arm/mach-s5p64x0/irq-eint.c
@@ -129,7 +129,7 @@ static int s5p64x0_alloc_gc(void)
        }
        ct = gc->chip_types;
-        ct->chip.irq_ack = irq_gc_ack;
+        ct->chip.irq_ack = irq_gc_ack_set_bit;
        ct->chip.irq_mask = irq_gc_mask_set_bit;
        ct->chip.irq_unmask = irq_gc_mask_clr_bit;
        ct->chip.irq_set_type = s5p64x0_irq_eint_set_type;
diff --git a/arch/arm/mach-s5pv210/pm.c b/arch/arm/mach-s5pv210/pm.c
index 309e388a8a83..f149d278377b 100644
--- a/arch/arm/mach-s5pv210/pm.c
+++ b/arch/arm/mach-s5pv210/pm.c
@@ -88,7 +88,7 @@ static struct sleep_save s5pv210_core_save[] = {
        SAVE_ITEM(S3C2410_TCNTO(0)),
 };
-void s5pv210_cpu_suspend(unsigned long arg)
+static int s5pv210_cpu_suspend(unsigned long arg)
 {
        unsigned long tmp;
diff --git a/arch/arm/mach-shmobile/board-ag5evm.c b/arch/arm/mach-shmobile/board-ag5evm.c
index ce5c2513c6ce..cdfdd624d21d 100644
--- a/arch/arm/mach-shmobile/board-ag5evm.c
+++ b/arch/arm/mach-shmobile/board-ag5evm.c
@@ -341,6 +341,7 @@ static struct platform_device mipidsi0_device = {
 static struct sh_mobile_sdhi_info sdhi0_info = {
        .dma_slave_tx   = SHDMA_SLAVE_SDHI0_TX,
        .dma_slave_rx   = SHDMA_SLAVE_SDHI0_RX,
+        .tmio_flags     = TMIO_MMC_HAS_IDLE_WAIT,
        .tmio_caps      = MMC_CAP_SD_HIGHSPEED,
        .tmio_ocr_mask  = MMC_VDD_27_28 | MMC_VDD_28_29,
 };
@@ -382,7 +383,7 @@ void ag5evm_sdhi1_set_pwr(struct platform_device *pdev, int state)
 }
 static struct sh_mobile_sdhi_info sh_sdhi1_info = {
-        .tmio_flags     = TMIO_MMC_WRPROTECT_DISABLE,
+        .tmio_flags     = TMIO_MMC_WRPROTECT_DISABLE | TMIO_MMC_HAS_IDLE_WAIT,
        .tmio_caps      = MMC_CAP_NONREMOVABLE | MMC_CAP_SDIO_IRQ,
        .tmio_ocr_mask  = MMC_VDD_32_33 | MMC_VDD_33_34,
        .set_pwr        = ag5evm_sdhi1_set_pwr,
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index 0ea71f8d4b89..17c19dc25604 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -641,6 +641,8 @@ static struct usbhs_private usbhs0_private = {
                },
                .driver_param = {
                        .buswait_bwait  = 4,
+                        .d0_tx_id       = SHDMA_SLAVE_USB0_TX,
+                        .d1_rx_id       = SHDMA_SLAVE_USB0_RX,
                },
        },
 };
@@ -810,6 +812,8 @@ static struct usbhs_private usbhs1_private = {
                        .buswait_bwait  = 4,
                        .pipe_type      = usbhs1_pipe_cfg,
                        .pipe_size      = ARRAY_SIZE(usbhs1_pipe_cfg),
+                        .d0_tx_id       = SHDMA_SLAVE_USB1_TX,
+                        .d1_rx_id       = SHDMA_SLAVE_USB1_RX,
                },
        },
 };
diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c
index e6e11e4e2d43..66975921e646 100644
--- a/arch/arm/mach-shmobile/clock-sh7372.c
+++ b/arch/arm/mach-shmobile/clock-sh7372.c
@@ -503,16 +503,17 @@ static struct clk *late_main_clks[] = {
        &sh7372_fsidivb_clk,
 };
-enum { MSTP001,
+enum { MSTP001, MSTP000,
       MSTP131, MSTP130,
       MSTP129, MSTP128, MSTP127, MSTP126, MSTP125,
       MSTP118, MSTP117, MSTP116, MSTP113,
       MSTP106, MSTP101, MSTP100,
       MSTP223,
-       MSTP218, MSTP217, MSTP216,
+       MSTP218, MSTP217, MSTP216, MSTP214, MSTP208, MSTP207,
-       MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
+       MSTP206, MSTP205, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
-       MSTP329, MSTP328, MSTP323, MSTP322, MSTP314, MSTP313, MSTP312,
+       MSTP328, MSTP323, MSTP322, MSTP314, MSTP313, MSTP312,
-       MSTP423, MSTP415, MSTP413, MSTP411, MSTP410, MSTP406, MSTP403,
+       MSTP423, MSTP415, MSTP413, MSTP411, MSTP410, MSTP407, MSTP406,
+       MSTP405, MSTP404, MSTP403, MSTP400,
       MSTP_NR };
 #define MSTP(_parent, _reg, _bit, _flags) \
@@ -520,6 +521,7 @@ enum { MSTP001,
 static struct clk mstp_clks[MSTP_NR] = {
        [MSTP001] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR0, 1, 0), /* IIC2 */
+        [MSTP000] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR0, 0, 0), /* MSIOF0 */
        [MSTP131] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 31, 0), /* VEU3 */
        [MSTP130] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 30, 0), /* VEU2 */
        [MSTP129] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 29, 0), /* VEU1 */
@@ -538,14 +540,16 @@ static struct clk mstp_clks[MSTP_NR] = {
        [MSTP218] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 18, 0), /* DMAC1 */
        [MSTP217] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 17, 0), /* DMAC2 */
        [MSTP216] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 16, 0), /* DMAC3 */
+        [MSTP214] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 14, 0), /* USBDMAC */
+        [MSTP208] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 8, 0), /* MSIOF1 */
        [MSTP207] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */
        [MSTP206] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */
+        [MSTP205] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 5, 0), /* MSIOF2 */
        [MSTP204] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 4, 0), /* SCIFA0 */
        [MSTP203] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 3, 0), /* SCIFA1 */
        [MSTP202] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 2, 0), /* SCIFA2 */
        [MSTP201] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 1, 0), /* SCIFA3 */
        [MSTP200] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */
-        [MSTP329] = MSTP(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */
        [MSTP328] = MSTP(&div6_clks[DIV6_SPU], SMSTPCR3, 28, 0), /* FSI2 */
        [MSTP323] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 23, 0), /* IIC1 */
        [MSTP322] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 22, 0), /* USB0 */
@@ -557,8 +561,12 @@ static struct clk mstp_clks[MSTP_NR] = {
        [MSTP413] = MSTP(&pllc1_div2_clk, SMSTPCR4, 13, 0), /* HDMI */
        [MSTP411] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 11, 0), /* IIC3 */
        [MSTP410] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 10, 0), /* IIC4 */
+        [MSTP407] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 7, 0), /* USB-DMAC1 */
        [MSTP406] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 6, 0), /* USB1 */
+        [MSTP405] = MSTP(&r_clk, SMSTPCR4, 5, 0), /* CMT4 */
+        [MSTP404] = MSTP(&r_clk, SMSTPCR4, 4, 0), /* CMT3 */
        [MSTP403] = MSTP(&r_clk, SMSTPCR4, 3, 0), /* KEYSC */
+        [MSTP400] = MSTP(&r_clk, SMSTPCR4, 0, 0), /* CMT2 */
 };
 static struct clk_lookup lookups[] = {
@@ -609,6 +617,7 @@ static struct clk_lookup lookups[] = {
        /* MSTP32 clocks */
        CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* IIC2 */
+        CLKDEV_DEV_ID("spi_sh_msiof.0", &mstp_clks[MSTP000]), /* MSIOF0 */
        CLKDEV_DEV_ID("uio_pdrv_genirq.4", &mstp_clks[MSTP131]), /* VEU3 */
        CLKDEV_DEV_ID("uio_pdrv_genirq.3", &mstp_clks[MSTP130]), /* VEU2 */
        CLKDEV_DEV_ID("uio_pdrv_genirq.2", &mstp_clks[MSTP129]), /* VEU1 */
@@ -629,14 +638,16 @@ static struct clk_lookup lookups[] = {
        CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]), /* DMAC1 */
        CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[MSTP217]), /* DMAC2 */
        CLKDEV_DEV_ID("sh-dma-engine.2", &mstp_clks[MSTP216]), /* DMAC3 */
+        CLKDEV_DEV_ID("sh-dma-engine.3", &mstp_clks[MSTP214]), /* USB-DMAC0 */
+        CLKDEV_DEV_ID("spi_sh_msiof.1", &mstp_clks[MSTP208]), /* MSIOF1 */
        CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */
        CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP206]), /* SCIFB */
+        CLKDEV_DEV_ID("spi_sh_msiof.2", &mstp_clks[MSTP205]), /* MSIOF2 */
        CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */
        CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */
        CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]), /* SCIFA2 */
        CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]), /* SCIFA3 */
        CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), /* SCIFA4 */
-        CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), /* CMT10 */
        CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]), /* FSI2 */
        CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* IIC1 */
        CLKDEV_DEV_ID("r8a66597_hcd.0", &mstp_clks[MSTP322]), /* USB0 */
@@ -650,10 +661,14 @@ static struct clk_lookup lookups[] = {
        CLKDEV_DEV_ID("sh-mobile-hdmi", &mstp_clks[MSTP413]), /* HDMI */
        CLKDEV_DEV_ID("i2c-sh_mobile.3", &mstp_clks[MSTP411]), /* IIC3 */
        CLKDEV_DEV_ID("i2c-sh_mobile.4", &mstp_clks[MSTP410]), /* IIC4 */
+        CLKDEV_DEV_ID("sh-dma-engine.4", &mstp_clks[MSTP407]), /* USB-DMAC1 */
        CLKDEV_DEV_ID("r8a66597_hcd.1", &mstp_clks[MSTP406]), /* USB1 */
        CLKDEV_DEV_ID("r8a66597_udc.1", &mstp_clks[MSTP406]), /* USB1 */
        CLKDEV_DEV_ID("renesas_usbhs.1", &mstp_clks[MSTP406]), /* USB1 */
+        CLKDEV_DEV_ID("sh_cmt.4", &mstp_clks[MSTP405]), /* CMT4 */
+        CLKDEV_DEV_ID("sh_cmt.3", &mstp_clks[MSTP404]), /* CMT3 */
        CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */
+        CLKDEV_DEV_ID("sh_cmt.2", &mstp_clks[MSTP400]), /* CMT2 */
        CLKDEV_ICK_ID("hdmi", "sh_mobile_lcdc_fb.1",
                      &div6_reparent_clks[DIV6_HDMI]),
diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c
index 6db2ccabc2bf..61a846bb30f2 100644
--- a/arch/arm/mach-shmobile/clock-sh73a0.c
+++ b/arch/arm/mach-shmobile/clock-sh73a0.c
@@ -365,7 +365,7 @@ void __init sh73a0_clock_init(void)
        __raw_writel(0x108, SD2CKCR);
        /* detect main clock parent */
-        switch ((__raw_readl(CKSCR) >> 24) & 0x03) {
+        switch ((__raw_readl(CKSCR) >> 28) & 0x03) {
        case 0:
                main_clk.parent = &sh73a0_extal1_clk;
                break;
diff --git a/arch/arm/mach-shmobile/include/mach/sh7372.h b/arch/arm/mach-shmobile/include/mach/sh7372.h
index ce595cee86cd..24e63a85e669 100644
--- a/arch/arm/mach-shmobile/include/mach/sh7372.h
+++ b/arch/arm/mach-shmobile/include/mach/sh7372.h
@@ -459,6 +459,10 @@ enum {
        SHDMA_SLAVE_SDHI2_TX,
        SHDMA_SLAVE_MMCIF_RX,
        SHDMA_SLAVE_MMCIF_TX,
+        SHDMA_SLAVE_USB0_TX,
+        SHDMA_SLAVE_USB0_RX,
+        SHDMA_SLAVE_USB1_TX,
+        SHDMA_SLAVE_USB1_RX,
 };
 extern struct clk sh7372_extal1_clk;
diff --git a/arch/arm/mach-shmobile/intc-sh7372.c b/arch/arm/mach-shmobile/intc-sh7372.c
index 3b28743c77eb..739315e30eb9 100644
--- a/arch/arm/mach-shmobile/intc-sh7372.c
+++ b/arch/arm/mach-shmobile/intc-sh7372.c
@@ -379,7 +379,7 @@ enum {
        /* BBIF2 */
        VPU,
        TSIF1,
-        _3DG_SGX530,
+        /* 3DG */
        _2DDMAC,
        IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2,
        IPMMU_IPMMUR, IPMMU_IPMMUR2,
@@ -436,7 +436,7 @@ static struct intc_vect intcs_vectors[] = {
        /* BBIF2 */
        INTCS_VECT(VPU, 0x980),
        INTCS_VECT(TSIF1, 0x9a0),
-        INTCS_VECT(_3DG_SGX530, 0x9e0),
+        /* 3DG */
        INTCS_VECT(_2DDMAC, 0xa00),
        INTCS_VECT(IIC2_ALI2, 0xa80), INTCS_VECT(IIC2_TACKI2, 0xaa0),
        INTCS_VECT(IIC2_WAITI2, 0xac0), INTCS_VECT(IIC2_DTEI2, 0xae0),
@@ -521,7 +521,7 @@ static struct intc_mask_reg intcs_mask_registers[] = {
            RTDMAC_1_DEI3, RTDMAC_1_DEI2, RTDMAC_1_DEI1, RTDMAC_1_DEI0 } },
        { 0xffd20198, 0xffd201d8, 8, /* IMR6SA / IMCR6SA */
          { 0, 0, MSIOF, 0,
-            _3DG_SGX530, 0, 0, 0 } },
+            0, 0, 0, 0 } },
        { 0xffd2019c, 0xffd201dc, 8, /* IMR7SA / IMCR7SA */
          { 0, TMU_TUNI2, TMU_TUNI1, TMU_TUNI0,
            0, 0, 0, 0 } },
@@ -561,7 +561,6 @@ static struct intc_prio_reg intcs_prio_registers[] = {
                                              TMU_TUNI2, TSIF1 } },
        { 0xffd2001c, 0, 16, 4, /* IPRHS */ { 0, 0, VEU, BEU } },
        { 0xffd20020, 0, 16, 4, /* IPRIS */ { 0, MSIOF, TSIF0, IIC0 } },
-        { 0xffd20024, 0, 16, 4, /* IPRJS */ { 0, _3DG_SGX530, 0, 0 } },
        { 0xffd20028, 0, 16, 4, /* IPRKS */ { 0, 0, LMB, 0 } },
        { 0xffd2002c, 0, 16, 4, /* IPRLS */ { IPMMU, 0, 0, 0 } },
        { 0xffd20030, 0, 16, 4, /* IPRMS */ { IIC2, 0, 0, 0 } },
diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c
index 79f0413d8725..2d9b1b1a2538 100644
--- a/arch/arm/mach-shmobile/setup-sh7372.c
+++ b/arch/arm/mach-shmobile/setup-sh7372.c
@@ -169,35 +169,35 @@ static struct platform_device scif6_device = {
 };
 /* CMT */
-static struct sh_timer_config cmt10_platform_data = {
+static struct sh_timer_config cmt2_platform_data = {
-        .name = "CMT10",
+        .name = "CMT2",
-        .channel_offset = 0x10,
+        .channel_offset = 0x40,
-        .timer_bit = 0,
+        .timer_bit = 5,
        .clockevent_rating = 125,
        .clocksource_rating = 125,
 };
-static struct resource cmt10_resources[] = {
+static struct resource cmt2_resources[] = {
        [0] = {
-                .name   = "CMT10",
+                .name   = "CMT2",
-                .start  = 0xe6138010,
+                .start  = 0xe6130040,
-                .end    = 0xe613801b,
+                .end    = 0xe613004b,
                .flags  = IORESOURCE_MEM,
        },
        [1] = {
-                .start  = evt2irq(0x0b00), /* CMT1_CMT10 */
+                .start  = evt2irq(0x0b80), /* CMT2 */
                .flags  = IORESOURCE_IRQ,
        },
 };
-static struct platform_device cmt10_device = {
+static struct platform_device cmt2_device = {
        .name           = "sh_cmt",
-        .id             = 10,
+        .id             = 2,
        .dev = {
-                .platform_data  = &cmt10_platform_data,
+                .platform_data  = &cmt2_platform_data,
        },
-        .resource       = cmt10_resources,
+        .resource       = cmt2_resources,
-        .num_resources  = ARRAY_SIZE(cmt10_resources),
+        .num_resources  = ARRAY_SIZE(cmt2_resources),
 };
 /* TMU */
@@ -602,6 +602,150 @@ static struct platform_device dma2_device = {
        },
 };
+/*
+ * USB-DMAC
+ */
+unsigned int usbts_shift[] = {3, 4, 5};
+enum {
+        XMIT_SZ_8BYTE           = 0,
+        XMIT_SZ_16BYTE          = 1,
+        XMIT_SZ_32BYTE          = 2,
+};
+#define USBTS_INDEX2VAL(i) (((i) & 3) << 6)
+static const struct sh_dmae_channel sh7372_usb_dmae_channels[] = {
+        {
+                .offset = 0,
+        }, {
+                .offset = 0x20,
+        },
+};
+/* USB DMAC0 */
+static const struct sh_dmae_slave_config sh7372_usb_dmae0_slaves[] = {
+        {
+                .slave_id       = SHDMA_SLAVE_USB0_TX,
+                .chcr           = USBTS_INDEX2VAL(XMIT_SZ_8BYTE),
+        }, {
+                .slave_id       = SHDMA_SLAVE_USB0_RX,
+                .chcr           = USBTS_INDEX2VAL(XMIT_SZ_8BYTE),
+        },
+};
+static struct sh_dmae_pdata usb_dma0_platform_data = {
+        .slave          = sh7372_usb_dmae0_slaves,
+        .slave_num      = ARRAY_SIZE(sh7372_usb_dmae0_slaves),
+        .channel        = sh7372_usb_dmae_channels,
+        .channel_num    = ARRAY_SIZE(sh7372_usb_dmae_channels),
+        .ts_low_shift   = 6,
+        .ts_low_mask    = 0xc0,
+        .ts_high_shift  = 0,
+        .ts_high_mask   = 0,
+        .ts_shift       = usbts_shift,
+        .ts_shift_num   = ARRAY_SIZE(usbts_shift),
+        .dmaor_init     = DMAOR_DME,
+        .chcr_offset    = 0x14,
+        .chcr_ie_bit    = 1 << 5,
+        .dmaor_is_32bit = 1,
+        .needs_tend_set = 1,
+        .no_dmars       = 1,
+};
+static struct resource sh7372_usb_dmae0_resources[] = {
+        {
+                /* Channel registers and DMAOR */
+                .start  = 0xe68a0020,
+                .end    = 0xe68a0064 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                /* VCR/SWR/DMICR */
+                .start  = 0xe68a0000,
+                .end    = 0xe68a0014 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                /* IRQ for channels */
+                .start  = evt2irq(0x0a00),
+                .end    = evt2irq(0x0a00),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device usb_dma0_device = {
+        .name           = "sh-dma-engine",
+        .id             = 3,
+        .resource       = sh7372_usb_dmae0_resources,
+        .num_resources  = ARRAY_SIZE(sh7372_usb_dmae0_resources),
+        .dev            = {
+                .platform_data  = &usb_dma0_platform_data,
+        },
+};
+/* USB DMAC1 */
+static const struct sh_dmae_slave_config sh7372_usb_dmae1_slaves[] = {
+        {
+                .slave_id       = SHDMA_SLAVE_USB1_TX,
+                .chcr           = USBTS_INDEX2VAL(XMIT_SZ_8BYTE),
+        }, {
+                .slave_id       = SHDMA_SLAVE_USB1_RX,
+                .chcr           = USBTS_INDEX2VAL(XMIT_SZ_8BYTE),
+        },
+};
+static struct sh_dmae_pdata usb_dma1_platform_data = {
+        .slave          = sh7372_usb_dmae1_slaves,
+        .slave_num      = ARRAY_SIZE(sh7372_usb_dmae1_slaves),
+        .channel        = sh7372_usb_dmae_channels,
+        .channel_num    = ARRAY_SIZE(sh7372_usb_dmae_channels),
+        .ts_low_shift   = 6,
+        .ts_low_mask    = 0xc0,
+        .ts_high_shift  = 0,
+        .ts_high_mask   = 0,
+        .ts_shift       = usbts_shift,
+        .ts_shift_num   = ARRAY_SIZE(usbts_shift),
+        .dmaor_init     = DMAOR_DME,
+        .chcr_offset    = 0x14,
+        .chcr_ie_bit    = 1 << 5,
+        .dmaor_is_32bit = 1,
+        .needs_tend_set = 1,
+        .no_dmars       = 1,
+};
+static struct resource sh7372_usb_dmae1_resources[] = {
+        {
+                /* Channel registers and DMAOR */
+                .start  = 0xe68c0020,
+                .end    = 0xe68c0064 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                /* VCR/SWR/DMICR */
+                .start  = 0xe68c0000,
+                .end    = 0xe68c0014 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                /* IRQ for channels */
+                .start  = evt2irq(0x1d00),
+                .end    = evt2irq(0x1d00),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device usb_dma1_device = {
+        .name           = "sh-dma-engine",
+        .id             = 4,
+        .resource       = sh7372_usb_dmae1_resources,
+        .num_resources  = ARRAY_SIZE(sh7372_usb_dmae1_resources),
+        .dev            = {
+                .platform_data  = &usb_dma1_platform_data,
+        },
+};
 /* VPU */
 static struct uio_info vpu_platform_data = {
        .name = "VPU5HG",
@@ -818,7 +962,7 @@ static struct platform_device *sh7372_early_devices[] __initdata = {
        &scif4_device,
        &scif5_device,
        &scif6_device,
-        &cmt10_device,
+        &cmt2_device,
        &tmu00_device,
        &tmu01_device,
 };
@@ -829,6 +973,8 @@ static struct platform_device *sh7372_late_devices[] __initdata = {
        &dma0_device,
        &dma1_device,
        &dma2_device,
+        &usb_dma0_device,
+        &usb_dma1_device,
        &vpu_device,
        &veu0_device,
        &veu1_device,
diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile
index 9fd00a6d4248..6bd2f451c185 100644
--- a/arch/arm/mach-ux500/Makefile
+++ b/arch/arm/mach-ux500/Makefile
@@ -3,7 +3,7 @@
 #
 obj-y                           := clock.o cpu.o devices.o devices-common.o \
-                                   id.o usb.o
+                                   id.o usb.o timer.o
 obj-$(CONFIG_CACHE_L2X0)        += cache-l2x0.o
 obj-$(CONFIG_UX500_SOC_DB5500)  += cpu-db5500.o dma-db5500.o
 obj-$(CONFIG_UX500_SOC_DB8500)  += cpu-db8500.o devices-db8500.o
diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c
index 252e8b3c5706..1405d0eb7edb 100644
--- a/arch/arm/mach-ux500/cpu.c
+++ b/arch/arm/mach-ux500/cpu.c
@@ -10,12 +10,12 @@
 #include <linux/clk.h>
 #include <linux/mfd/db8500-prcmu.h>
 #include <linux/mfd/db5500-prcmu.h>
+#include <linux/clksrc-dbx500-prcmu.h>
 #include <asm/hardware/gic.h>
 #include <asm/mach/map.h>
 #include <asm/localtimer.h>
-#include <plat/mtu.h>
 #include <mach/hardware.h>
 #include <mach/setup.h>
 #include <mach/devices.h>
@@ -50,30 +50,3 @@ void __init ux500_init_irq(void)
                prcmu_early_init();
        clk_init();
 }
-static void __init ux500_timer_init(void)
-{
-#ifdef CONFIG_LOCAL_TIMERS
-        /* Setup the local timer base */
-        if (cpu_is_u5500())
-                twd_base = __io_address(U5500_TWD_BASE);
-        else if (cpu_is_u8500())
-                twd_base = __io_address(U8500_TWD_BASE);
-        else
-                ux500_unknown_soc();
-#endif
-        if (cpu_is_u5500())
-                mtu_base = __io_address(U5500_MTU0_BASE);
-        else if (cpu_is_u8500ed())
-                mtu_base = __io_address(U8500_MTU0_BASE_ED);
-        else if (cpu_is_u8500())
-                mtu_base = __io_address(U8500_MTU0_BASE);
-        else
-                ux500_unknown_soc();
-        nmdk_timer_init();
-}
-struct sys_timer ux500_timer = {
-        .init   = ux500_timer_init,
-};
diff --git a/arch/arm/mach-ux500/include/mach/db5500-regs.h b/arch/arm/mach-ux500/include/mach/db5500-regs.h
index 6ad983294103..994b5fe6f85a 100644
--- a/arch/arm/mach-ux500/include/mach/db5500-regs.h
+++ b/arch/arm/mach-ux500/include/mach/db5500-regs.h
@@ -61,6 +61,8 @@
 #define U5500_SCR_BASE          (U5500_PER4_BASE + 0x5000)
 #define U5500_DMC_BASE          (U5500_PER4_BASE + 0x6000)
 #define U5500_PRCMU_BASE        (U5500_PER4_BASE + 0x7000)
+#define U5500_PRCMU_TIMER_3_BASE (U5500_PER4_BASE + 0x07338)
+#define U5500_PRCMU_TIMER_4_BASE (U5500_PER4_BASE + 0x07450)
 #define U5500_MSP1_BASE         (U5500_PER4_BASE + 0x9000)
 #define U5500_GPIO2_BASE        (U5500_PER4_BASE + 0xA000)
 #define U5500_CDETECT_BASE      (U5500_PER4_BASE + 0xF000)
diff --git a/arch/arm/mach-ux500/include/mach/db8500-regs.h b/arch/arm/mach-ux500/include/mach/db8500-regs.h
index 049997109cf9..751b0e6938d4 100644
--- a/arch/arm/mach-ux500/include/mach/db8500-regs.h
+++ b/arch/arm/mach-ux500/include/mach/db8500-regs.h
@@ -102,10 +102,13 @@
 #define U8500_SCR_BASE          (U8500_PER4_BASE + 0x05000)
 #define U8500_DMC_BASE          (U8500_PER4_BASE + 0x06000)
 #define U8500_PRCMU_BASE        (U8500_PER4_BASE + 0x07000)
+#define U8500_PRCMU_TIMER_3_BASE (U8500_PER4_BASE + 0x07338)
+#define U8500_PRCMU_TIMER_4_BASE (U8500_PER4_BASE + 0x07450)
 #define U8500_PRCMU_TCDM_BASE_V1 (U8500_PER4_BASE + 0x0f000)
 #define U8500_PRCMU_TCDM_BASE   (U8500_PER4_BASE + 0x68000)
 #define U8500_PRCMU_TCPM_BASE   (U8500_PER4_BASE + 0x60000)
 /* per3 base addresses */
 #define U8500_FSMC_BASE         (U8500_PER3_BASE + 0x0000)
 #define U8500_SSP0_BASE         (U8500_PER3_BASE + 0x2000)
diff --git a/arch/arm/mach-ux500/timer.c b/arch/arm/mach-ux500/timer.c
new file mode 100644
index 000000000000..aea467d04ff7
--- /dev/null
+++ b/arch/arm/mach-ux500/timer.c
@@ -0,0 +1,68 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2011
+ *
+ * License Terms: GNU General Public License v2
+ * Author: Mattias Wallin <mattias.wallin@stericsson.com> for ST-Ericsson
+ */
+#include <linux/io.h>
+#include <linux/errno.h>
+#include <linux/clksrc-dbx500-prcmu.h>
+#include <asm/localtimer.h>
+#include <plat/mtu.h>
+#include <mach/setup.h>
+#include <mach/hardware.h>
+static void __init ux500_timer_init(void)
+{
+        void __iomem *prcmu_timer_base;
+        if (cpu_is_u5500()) {
+#ifdef CONFIG_LOCAL_TIMERS
+                twd_base = __io_address(U5500_TWD_BASE);
+#endif
+                mtu_base = __io_address(U5500_MTU0_BASE);
+                prcmu_timer_base = __io_address(U5500_PRCMU_TIMER_3_BASE);
+        } else if (cpu_is_u8500()) {
+#ifdef CONFIG_LOCAL_TIMERS
+                twd_base = __io_address(U8500_TWD_BASE);
+#endif
+                mtu_base = __io_address(U8500_MTU0_BASE);
+                prcmu_timer_base = __io_address(U8500_PRCMU_TIMER_4_BASE);
+        } else {
+                ux500_unknown_soc();
+        }
+        /*
+         * Here we register the timerblocks active in the system.
+         * Localtimers (twd) is started when both cpu is up and running.
+         * MTU register a clocksource, clockevent and sched_clock.
+         * Since the MTU is located in the VAPE power domain
+         * it will be cleared in sleep which makes it unsuitable.
+         * We however need it as a timer tick (clockevent)
+         * during boot to calibrate delay until twd is started.
+         * RTC-RTT have problems as timer tick during boot since it is
+         * depending on delay which is not yet calibrated. RTC-RTT is in the
+         * always-on powerdomain and is used as clockevent instead of twd when
+         * sleeping.
+         * The PRCMU timer 4(3 for DB5500) register a clocksource and
+         * sched_clock with higher rating then MTU since is always-on.
+         *
+         */
+        nmdk_timer_init();
+        clksrc_dbx500_prcmu_init(prcmu_timer_base);
+}
+static void ux500_timer_reset(void)
+{
+        nmdk_clkevt_reset();
+        nmdk_clksrc_reset();
+}
+struct sys_timer ux500_timer = {
+        .init           = ux500_timer_init,
+        .resume         = ux500_timer_reset,
+};
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
index 9e6b93b1a043..d0d267a8d3f9 100644
--- a/arch/arm/mach-vexpress/v2m.c
+++ b/arch/arm/mach-vexpress/v2m.c
@@ -318,6 +318,10 @@ static struct clk v2m_sp804_clk = {
        .rate   = 1000000,
 };
+static struct clk v2m_ref_clk = {
+        .rate   = 32768,
+};
 static struct clk dummy_apb_pclk;
 static struct clk_lookup v2m_lookups[] = {
@@ -348,6 +352,9 @@ static struct clk_lookup v2m_lookups[] = {
        }, {    /* CLCD */
                .dev_id         = "mb:clcd",
                .clk            = &osc1_clk,
+        }, {    /* SP805 WDT */
+                .dev_id         = "mb:wdt",
+                .clk            = &v2m_ref_clk,
        }, {    /* SP804 timers */
                .dev_id         = "sp804",
                .con_id         = "v2m-timer0",
diff --git a/arch/arm/mm/abort-macro.S b/arch/arm/mm/abort-macro.S
index 52162d59407a..2cbf68ef0e83 100644
--- a/arch/arm/mm/abort-macro.S
+++ b/arch/arm/mm/abort-macro.S
@@ -17,7 +17,7 @@
        cmp     \tmp, # 0x5600                  @ Is it ldrsb?
        orreq   \tmp, \tmp, #1 << 11            @ Set L-bit if yes
        tst     \tmp, #1 << 11                  @ L = 0 -> write
-        orreq   \psr, \psr, #1 << 11            @ yes.
+        orreq   \fsr, \fsr, #1 << 11            @ yes.
        b       do_DataAbort
 not_thumb:
        .endm
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 44c086710d2b..9ecfdb511951 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -277,6 +277,25 @@ static void l2x0_disable(void)
        spin_unlock_irqrestore(&l2x0_lock, flags);
 }
+static void __init l2x0_unlock(__u32 cache_id)
+{
+        int lockregs;
+        int i;
+        if (cache_id == L2X0_CACHE_ID_PART_L310)
+                lockregs = 8;
+        else
+                /* L210 and unknown types */
+                lockregs = 1;
+        for (i = 0; i < lockregs; i++) {
+                writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_D_BASE +
+                               i * L2X0_LOCKDOWN_STRIDE);
+                writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_I_BASE +
+                               i * L2X0_LOCKDOWN_STRIDE);
+        }
+}
 void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
 {
        __u32 aux;
@@ -328,6 +347,8 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
         * accessing the below registers will fault.
         */
        if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {
+                /* Make sure that I&D is not locked down when starting */
+                l2x0_unlock(cache_id);
                /* l2x0 controller is disabled */
                writel_relaxed(aux, l2x0_base + L2X0_AUX_CTRL);
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 91bca355cd31..cc7e2d8be9aa 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -298,7 +298,7 @@ static void __init arm_bootmem_free(unsigned long min, unsigned long max_low,
 #ifdef CONFIG_HAVE_ARCH_PFN_VALID
 int pfn_valid(unsigned long pfn)
 {
-        return memblock_is_memory(pfn << PAGE_SHIFT);
+        return memblock_is_memory(__pfn_to_phys(pfn));
 }
 EXPORT_SYMBOL(pfn_valid);
 #endif
diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S
index 92bd102e3982..2e6849b41f66 100644
--- a/arch/arm/mm/proc-arm920.S
+++ b/arch/arm/mm/proc-arm920.S
@@ -379,7 +379,7 @@ ENTRY(cpu_arm920_set_pte_ext)
 /* Suspend/resume support: taken from arch/arm/plat-s3c24xx/sleep.S */
 .globl  cpu_arm920_suspend_size
-.equ    cpu_arm920_suspend_size, 4 * 3
+.equ    cpu_arm920_suspend_size, 4 * 4
 #ifdef CONFIG_PM_SLEEP
 ENTRY(cpu_arm920_do_suspend)
        stmfd   sp!, {r4 - r7, lr}
diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S
index 2bbcf053dffd..cd8f79c3a282 100644
--- a/arch/arm/mm/proc-arm926.S
+++ b/arch/arm/mm/proc-arm926.S
@@ -394,7 +394,7 @@ ENTRY(cpu_arm926_set_pte_ext)
 /* Suspend/resume support: taken from arch/arm/plat-s3c24xx/sleep.S */
 .globl  cpu_arm926_suspend_size
-.equ    cpu_arm926_suspend_size, 4 * 3
+.equ    cpu_arm926_suspend_size, 4 * 4
 #ifdef CONFIG_PM_SLEEP
 ENTRY(cpu_arm926_do_suspend)
        stmfd   sp!, {r4 - r7, lr}
diff --git a/arch/arm/mm/proc-sa1100.S b/arch/arm/mm/proc-sa1100.S
index 07219c2ae114..69e7f2ef7384 100644
--- a/arch/arm/mm/proc-sa1100.S
+++ b/arch/arm/mm/proc-sa1100.S
@@ -182,11 +182,11 @@ ENDPROC(cpu_sa1100_do_suspend)
 ENTRY(cpu_sa1100_do_resume)
        ldmia   r0, {r4 - r7}                   @ load cp regs
-        mov     r1, #0
+        mov     ip, #0
-        mcr     p15, 0, r1, c8, c7, 0           @ flush I+D TLBs
+        mcr     p15, 0, ip, c8, c7, 0           @ flush I+D TLBs
-        mcr     p15, 0, r1, c7, c7, 0           @ flush I&D cache
+        mcr     p15, 0, ip, c7, c7, 0           @ flush I&D cache
-        mcr     p15, 0, r1, c9, c0, 0           @ invalidate RB
+        mcr     p15, 0, ip, c9, c0, 0           @ invalidate RB
-        mcr     p15, 0, r1, c9, c0, 5           @ allow user space to use RB
+        mcr     p15, 0, ip, c9, c0, 5           @ allow user space to use RB
        mcr     p15, 0, r4, c3, c0, 0           @ domain ID
        mcr     p15, 0, r5, c2, c0, 0           @ translation table base addr
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 219138d2f158..a923aa0fd00d 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -223,6 +223,22 @@ __v6_setup:
        mrc     p15, 0, r0, c1, c0, 0           @ read control register
        bic     r0, r0, r5                      @ clear bits them
        orr     r0, r0, r6                      @ set them
+#ifdef CONFIG_ARM_ERRATA_364296
+        /*
+         * Workaround for the 364296 ARM1136 r0p2 erratum (possible cache data
+         * corruption with hit-under-miss enabled). The conditional code below
+         * (setting the undocumented bit 31 in the auxiliary control register
+         * and the FI bit in the control register) disables hit-under-miss
+         * without putting the processor into full low interrupt latency mode.
+         */
+        ldr     r6, =0x4107b362                 @ id for ARM1136 r0p2
+        mrc     p15, 0, r5, c0, c0, 0           @ get processor id
+        teq     r5, r6                          @ check for the faulty core
+        mrceq   p15, 0, r5, c1, c0, 1           @ load aux control reg
+        orreq   r5, r5, #(1 << 31)              @ set the undocumented bit 31
+        mcreq   p15, 0, r5, c1, c0, 1           @ write aux control reg
+        orreq   r0, r0, #(1 << 21)              @ low interrupt latency configuration
+#endif
        mov     pc, lr                          @ return to head.S:__ret
        /*
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index a30e78542ccf..9049c0764db2 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -66,6 +66,7 @@ ENDPROC(cpu_v7_proc_fin)
 ENTRY(cpu_v7_reset)
        mrc     p15, 0, r1, c1, c0, 0           @ ctrl register
        bic     r1, r1, #0x1                    @ ...............m
+ THUMB( bic     r1, r1, #1 << 30 )              @ SCTLR.TE (Thumb exceptions)
        mcr     p15, 0, r1, c1, c0, 0           @ disable MMU
        isb
        mov     pc, r0
@@ -247,13 +248,16 @@ ENTRY(cpu_v7_do_resume)
        mcr     p15, 0, r7, c2, c0, 0   @ TTB 0
        mcr     p15, 0, r8, c2, c0, 1   @ TTB 1
        mcr     p15, 0, ip, c2, c0, 2   @ TTB control register
-        mcr     p15, 0, r10, c1, c0, 1  @ Auxiliary control register
+        mrc     p15, 0, r4, c1, c0, 1   @ Read Auxiliary control register
+        teq     r4, r10                 @ Is it already set?
+        mcrne   p15, 0, r10, c1, c0, 1  @ No, so write it
        mcr     p15, 0, r11, c1, c0, 2  @ Co-processor access control
        ldr     r4, =PRRR               @ PRRR
        ldr     r5, =NMRR               @ NMRR
        mcr     p15, 0, r4, c10, c2, 0  @ write PRRR
        mcr     p15, 0, r5, c10, c2, 1  @ write NMRR
        isb
+        dsb
        mov     r0, r9                  @ control register
        mov     r2, r7, lsr #14         @ get TTB0 base
        mov     r2, r2, lsl #14
diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S
index 28c72a2006a1..755e1bf22681 100644
--- a/arch/arm/mm/proc-xsc3.S
+++ b/arch/arm/mm/proc-xsc3.S
@@ -406,7 +406,7 @@ ENTRY(cpu_xsc3_set_pte_ext)
        .align
 .globl  cpu_xsc3_suspend_size
-.equ    cpu_xsc3_suspend_size, 4 * 8
+.equ    cpu_xsc3_suspend_size, 4 * 7
 #ifdef CONFIG_PM_SLEEP
 ENTRY(cpu_xsc3_do_suspend)
        stmfd   sp!, {r4 - r10, lr}
@@ -418,12 +418,12 @@ ENTRY(cpu_xsc3_do_suspend)
        mrc     p15, 0, r9, c1, c0, 1   @ auxiliary control reg
        mrc     p15, 0, r10, c1, c0, 0  @ control reg
        bic     r4, r4, #2              @ clear frequency change bit
-        stmia   r0, {r1, r4 - r10}      @ store v:p offset + cp regs
+        stmia   r0, {r4 - r10}          @ store cp regs
        ldmia   sp!, {r4 - r10, pc}
 ENDPROC(cpu_xsc3_do_suspend)
 ENTRY(cpu_xsc3_do_resume)
-        ldmia   r0, {r1, r4 - r10}      @ load v:p offset + cp regs
+        ldmia   r0, {r4 - r10}          @ load cp regs
        mov     ip, #0
        mcr     p15, 0, ip, c7, c7, 0   @ invalidate I & D caches, BTB
        mcr     p15, 0, ip, c7, c10, 4  @ drain write (&fill) buffer
diff --git a/arch/arm/plat-nomadik/Kconfig b/arch/arm/plat-nomadik/Kconfig
index ce659015535e..bca4914b4b9d 100644
--- a/arch/arm/plat-nomadik/Kconfig
+++ b/arch/arm/plat-nomadik/Kconfig
@@ -15,10 +15,16 @@ if PLAT_NOMADIK
 config HAS_MTU
        bool
-        select HAVE_SCHED_CLOCK
        help
          Support for Multi Timer Unit. MTU provides access
          to multiple interrupt generating programmable
          32-bit free running decrementing counters.
+config NOMADIK_MTU_SCHED_CLOCK
+        bool
+        depends on HAS_MTU
+        select HAVE_SCHED_CLOCK
+        help
+          Use the Multi Timer Unit as the sched_clock.
 endif
diff --git a/arch/arm/plat-nomadik/include/plat/mtu.h b/arch/arm/plat-nomadik/include/plat/mtu.h
index 65704a3d4241..6508e7694a4b 100644
--- a/arch/arm/plat-nomadik/include/plat/mtu.h
+++ b/arch/arm/plat-nomadik/include/plat/mtu.h
@@ -1,54 +1,11 @@
 #ifndef __PLAT_MTU_H
 #define __PLAT_MTU_H
-/*
- * Guaranteed runtime conversion range in seconds for
- * the clocksource and clockevent.
- */
-#define MTU_MIN_RANGE 4
 /* should be set by the platform code */
 extern void __iomem *mtu_base;
-/*
+void nmdk_clkevt_reset(void);
- * The MTU device hosts four different counters, with 4 set of
+void nmdk_clksrc_reset(void);
- * registers. These are register names.
- */
-#define MTU_IMSC        0x00    /* Interrupt mask set/clear */
-#define MTU_RIS         0x04    /* Raw interrupt status */
-#define MTU_MIS         0x08    /* Masked interrupt status */
-#define MTU_ICR         0x0C    /* Interrupt clear register */
-/* per-timer registers take 0..3 as argument */
-#define MTU_LR(x)       (0x10 + 0x10 * (x) + 0x00)      /* Load value */
-#define MTU_VAL(x)      (0x10 + 0x10 * (x) + 0x04)      /* Current value */
-#define MTU_CR(x)       (0x10 + 0x10 * (x) + 0x08)      /* Control reg */
-#define MTU_BGLR(x)     (0x10 + 0x10 * (x) + 0x0c)      /* At next overflow */
-/* bits for the control register */
-#define MTU_CRn_ENA             0x80
-#define MTU_CRn_PERIODIC        0x40    /* if 0 = free-running */
-#define MTU_CRn_PRESCALE_MASK   0x0c
-#define MTU_CRn_PRESCALE_1              0x00
-#define MTU_CRn_PRESCALE_16             0x04
-#define MTU_CRn_PRESCALE_256            0x08
-#define MTU_CRn_32BITS          0x02
-#define MTU_CRn_ONESHOT         0x01    /* if 0 = wraps reloading from BGLR*/
-/* Other registers are usual amba/primecell registers, currently not used */
-#define MTU_ITCR        0xff0
-#define MTU_ITOP        0xff4
-#define MTU_PERIPH_ID0  0xfe0
-#define MTU_PERIPH_ID1  0xfe4
-#define MTU_PERIPH_ID2  0xfe8
-#define MTU_PERIPH_ID3  0xfeC
-#define MTU_PCELL0      0xff0
-#define MTU_PCELL1      0xff4
-#define MTU_PCELL2      0xff8
-#define MTU_PCELL3      0xffC
 #endif /* __PLAT_MTU_H */
diff --git a/arch/arm/plat-nomadik/timer.c b/arch/arm/plat-nomadik/timer.c
index ef74e157a9d5..30b6433d910d 100644
--- a/arch/arm/plat-nomadik/timer.c
+++ b/arch/arm/plat-nomadik/timer.c
@@ -21,10 +21,59 @@
 #include <asm/mach/time.h>
 #include <asm/sched_clock.h>
-#include <plat/mtu.h>
+/*
+ * Guaranteed runtime conversion range in seconds for
+ * the clocksource and clockevent.
+ */
+#define MTU_MIN_RANGE 4
+/*
+ * The MTU device hosts four different counters, with 4 set of
+ * registers. These are register names.
+ */
+#define MTU_IMSC        0x00    /* Interrupt mask set/clear */
+#define MTU_RIS         0x04    /* Raw interrupt status */
+#define MTU_MIS         0x08    /* Masked interrupt status */
+#define MTU_ICR         0x0C    /* Interrupt clear register */
+/* per-timer registers take 0..3 as argument */
+#define MTU_LR(x)       (0x10 + 0x10 * (x) + 0x00)      /* Load value */
+#define MTU_VAL(x)      (0x10 + 0x10 * (x) + 0x04)      /* Current value */
+#define MTU_CR(x)       (0x10 + 0x10 * (x) + 0x08)      /* Control reg */
+#define MTU_BGLR(x)     (0x10 + 0x10 * (x) + 0x0c)      /* At next overflow */
+/* bits for the control register */
+#define MTU_CRn_ENA             0x80
+#define MTU_CRn_PERIODIC        0x40    /* if 0 = free-running */
+#define MTU_CRn_PRESCALE_MASK   0x0c
+#define MTU_CRn_PRESCALE_1              0x00
+#define MTU_CRn_PRESCALE_16             0x04
+#define MTU_CRn_PRESCALE_256            0x08
+#define MTU_CRn_32BITS          0x02
+#define MTU_CRn_ONESHOT         0x01    /* if 0 = wraps reloading from BGLR*/
+/* Other registers are usual amba/primecell registers, currently not used */
+#define MTU_ITCR        0xff0
+#define MTU_ITOP        0xff4
+#define MTU_PERIPH_ID0  0xfe0
+#define MTU_PERIPH_ID1  0xfe4
+#define MTU_PERIPH_ID2  0xfe8
+#define MTU_PERIPH_ID3  0xfeC
+#define MTU_PCELL0      0xff0
+#define MTU_PCELL1      0xff4
+#define MTU_PCELL2      0xff8
+#define MTU_PCELL3      0xffC
+static bool clkevt_periodic;
+static u32 clk_prescale;
+static u32 nmdk_cycle;          /* write-once */
 void __iomem *mtu_base; /* Assigned by machine code */
+#ifdef CONFIG_NOMADIK_MTU_SCHED_CLOCK
 /*
 * Override the global weak sched_clock symbol with this
 * local implementation which uses the clocksource to get some
@@ -48,32 +97,56 @@ static void notrace nomadik_update_sched_clock(void)
        u32 cyc = -readl(mtu_base + MTU_VAL(0));
        update_sched_clock(&cd, cyc, (u32)~0);
 }
+#endif
 /* Clockevent device: use one-shot mode */
+static int nmdk_clkevt_next(unsigned long evt, struct clock_event_device *ev)
+{
+        writel(1 << 1, mtu_base + MTU_IMSC);
+        writel(evt, mtu_base + MTU_LR(1));
+        /* Load highest value, enable device, enable interrupts */
+        writel(MTU_CRn_ONESHOT | clk_prescale |
+               MTU_CRn_32BITS | MTU_CRn_ENA,
+               mtu_base + MTU_CR(1));
+        return 0;
+}
+void nmdk_clkevt_reset(void)
+{
+        if (clkevt_periodic) {
+                /* Timer: configure load and background-load, and fire it up */
+                writel(nmdk_cycle, mtu_base + MTU_LR(1));
+                writel(nmdk_cycle, mtu_base + MTU_BGLR(1));
+                writel(MTU_CRn_PERIODIC | clk_prescale |
+                       MTU_CRn_32BITS | MTU_CRn_ENA,
+                       mtu_base + MTU_CR(1));
+                writel(1 << 1, mtu_base + MTU_IMSC);
+        } else {
+                /* Generate an interrupt to start the clockevent again */
+                (void) nmdk_clkevt_next(nmdk_cycle, NULL);
+        }
+}
 static void nmdk_clkevt_mode(enum clock_event_mode mode,
                             struct clock_event_device *dev)
 {
-        u32 cr;
        switch (mode) {
        case CLOCK_EVT_MODE_PERIODIC:
-                pr_err("%s: periodic mode not supported\n", __func__);
+                clkevt_periodic = true;
+                nmdk_clkevt_reset();
                break;
        case CLOCK_EVT_MODE_ONESHOT:
-                /* Load highest value, enable device, enable interrupts */
+                clkevt_periodic = false;
-                cr = readl(mtu_base + MTU_CR(1));
-                writel(0, mtu_base + MTU_LR(1));
-                writel(cr | MTU_CRn_ENA, mtu_base + MTU_CR(1));
-                writel(1 << 1, mtu_base + MTU_IMSC);
                break;
        case CLOCK_EVT_MODE_SHUTDOWN:
        case CLOCK_EVT_MODE_UNUSED:
-                /* disable irq */
                writel(0, mtu_base + MTU_IMSC);
                /* disable timer */
-                cr = readl(mtu_base + MTU_CR(1));
+                writel(0, mtu_base + MTU_CR(1));
-                cr &= ~MTU_CRn_ENA;
-                writel(cr, mtu_base + MTU_CR(1));
                /* load some high default value */
                writel(0xffffffff, mtu_base + MTU_LR(1));
                break;
@@ -82,16 +155,9 @@ static void nmdk_clkevt_mode(enum clock_event_mode mode,
        }
 }
-static int nmdk_clkevt_next(unsigned long evt, struct clock_event_device *ev)
-{
-        /* writing the value has immediate effect */
-        writel(evt, mtu_base + MTU_LR(1));
-        return 0;
-}
 static struct clock_event_device nmdk_clkevt = {
        .name           = "mtu_1",
-        .features       = CLOCK_EVT_FEAT_ONESHOT,
+        .features       = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
        .rating         = 200,
        .set_mode       = nmdk_clkevt_mode,
        .set_next_event = nmdk_clkevt_next,
@@ -116,11 +182,23 @@ static struct irqaction nmdk_timer_irq = {
        .dev_id         = &nmdk_clkevt,
 };
+void nmdk_clksrc_reset(void)
+{
+        /* Disable */
+        writel(0, mtu_base + MTU_CR(0));
+        /* ClockSource: configure load and background-load, and fire it up */
+        writel(nmdk_cycle, mtu_base + MTU_LR(0));
+        writel(nmdk_cycle, mtu_base + MTU_BGLR(0));
+        writel(clk_prescale | MTU_CRn_32BITS | MTU_CRn_ENA,
+               mtu_base + MTU_CR(0));
+}
 void __init nmdk_timer_init(void)
 {
        unsigned long rate;
        struct clk *clk0;
-        u32 cr = MTU_CRn_32BITS;
        clk0 = clk_get_sys("mtu0", NULL);
        BUG_ON(IS_ERR(clk0));
@@ -138,30 +216,28 @@ void __init nmdk_timer_init(void)
        rate = clk_get_rate(clk0);
        if (rate > 32000000) {
                rate /= 16;
-                cr |= MTU_CRn_PRESCALE_16;
+                clk_prescale = MTU_CRn_PRESCALE_16;
        } else {
-                cr |= MTU_CRn_PRESCALE_1;
+                clk_prescale = MTU_CRn_PRESCALE_1;
        }
+        nmdk_cycle = (rate + HZ/2) / HZ;
        /* Timer 0 is the free running clocksource */
-        writel(cr, mtu_base + MTU_CR(0));
+        nmdk_clksrc_reset();
-        writel(0, mtu_base + MTU_LR(0));
-        writel(0, mtu_base + MTU_BGLR(0));
-        writel(cr | MTU_CRn_ENA, mtu_base + MTU_CR(0));
        if (clocksource_mmio_init(mtu_base + MTU_VAL(0), "mtu_0",
                        rate, 200, 32, clocksource_mmio_readl_down))
                pr_err("timer: failed to initialize clock source %s\n",
                       "mtu_0");
+#ifdef CONFIG_NOMADIK_MTU_SCHED_CLOCK
        init_sched_clock(&cd, nomadik_update_sched_clock, 32, rate);
+#endif
        /* Timer 1 is used for events */
        clockevents_calc_mult_shift(&nmdk_clkevt, rate, MTU_MIN_RANGE);
-        writel(cr | MTU_CRn_ONESHOT, mtu_base + MTU_CR(1)); /* off, currently */
        nmdk_clkevt.max_delta_ns =
                clockevent_delta2ns(0xffffffff, &nmdk_clkevt);
        nmdk_clkevt.min_delta_ns =
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 75a847dd776a..2def4e1990ed 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -3,6 +3,12 @@
 *
 * OMAP Dual-Mode Timers
 *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ * Tarun Kanti DebBarma <tarun.kanti@ti.com>
+ * Thara Gopinath <thara@ti.com>
+ *
+ * dmtimer adaptation to platform_driver.
+ *
 * Copyright (C) 2005 Nokia Corporation
 * OMAP2 support by Juha Yrjola
 * API improvements and OMAP2 clock framework support by Timo Teras
@@ -29,168 +35,80 @@
 * 675 Mass Ave, Cambridge, MA 02139, USA.
 */
-#include <linux/init.h>
-#include <linux/spinlock.h>
-#include <linux/errno.h>
-#include <linux/list.h>
-#include <linux/clk.h>
-#include <linux/delay.h>
 #include <linux/io.h>
-#include <linux/module.h>
+#include <linux/slab.h>
-#include <mach/hardware.h>
+#include <linux/err.h>
-#include <plat/dmtimer.h>
+#include <linux/pm_runtime.h>
-#include <mach/irqs.h>
-static int dm_timer_count;
-#ifdef CONFIG_ARCH_OMAP1
-static struct omap_dm_timer omap1_dm_timers[] = {
-        { .phys_base = 0xfffb1400, .irq = INT_1610_GPTIMER1 },
-        { .phys_base = 0xfffb1c00, .irq = INT_1610_GPTIMER2 },
-        { .phys_base = 0xfffb2400, .irq = INT_1610_GPTIMER3 },
-        { .phys_base = 0xfffb2c00, .irq = INT_1610_GPTIMER4 },
-        { .phys_base = 0xfffb3400, .irq = INT_1610_GPTIMER5 },
-        { .phys_base = 0xfffb3c00, .irq = INT_1610_GPTIMER6 },
-        { .phys_base = 0xfffb7400, .irq = INT_1610_GPTIMER7 },
-        { .phys_base = 0xfffbd400, .irq = INT_1610_GPTIMER8 },
-};
-static const int omap1_dm_timer_count = ARRAY_SIZE(omap1_dm_timers);
-#else
-#define omap1_dm_timers                 NULL
-#define omap1_dm_timer_count            0
-#endif  /* CONFIG_ARCH_OMAP1 */
-#ifdef CONFIG_ARCH_OMAP2
-static struct omap_dm_timer omap2_dm_timers[] = {
-        { .phys_base = 0x48028000, .irq = INT_24XX_GPTIMER1 },
-        { .phys_base = 0x4802a000, .irq = INT_24XX_GPTIMER2 },
-        { .phys_base = 0x48078000, .irq = INT_24XX_GPTIMER3 },
-        { .phys_base = 0x4807a000, .irq = INT_24XX_GPTIMER4 },
-        { .phys_base = 0x4807c000, .irq = INT_24XX_GPTIMER5 },
-        { .phys_base = 0x4807e000, .irq = INT_24XX_GPTIMER6 },
-        { .phys_base = 0x48080000, .irq = INT_24XX_GPTIMER7 },
-        { .phys_base = 0x48082000, .irq = INT_24XX_GPTIMER8 },
-        { .phys_base = 0x48084000, .irq = INT_24XX_GPTIMER9 },
-        { .phys_base = 0x48086000, .irq = INT_24XX_GPTIMER10 },
-        { .phys_base = 0x48088000, .irq = INT_24XX_GPTIMER11 },
-        { .phys_base = 0x4808a000, .irq = INT_24XX_GPTIMER12 },
-};
-static const char *omap2_dm_source_names[] __initdata = {
-        "sys_ck",
-        "func_32k_ck",
-        "alt_ck",
-        NULL
-};
-static struct clk *omap2_dm_source_clocks[3];
-static const int omap2_dm_timer_count = ARRAY_SIZE(omap2_dm_timers);
-#else
-#define omap2_dm_timers                 NULL
-#define omap2_dm_timer_count            0
-#define omap2_dm_source_names           NULL
-#define omap2_dm_source_clocks          NULL
-#endif  /* CONFIG_ARCH_OMAP2 */
-#ifdef CONFIG_ARCH_OMAP3
-static struct omap_dm_timer omap3_dm_timers[] = {
-        { .phys_base = 0x48318000, .irq = INT_24XX_GPTIMER1 },
-        { .phys_base = 0x49032000, .irq = INT_24XX_GPTIMER2 },
-        { .phys_base = 0x49034000, .irq = INT_24XX_GPTIMER3 },
-        { .phys_base = 0x49036000, .irq = INT_24XX_GPTIMER4 },
-        { .phys_base = 0x49038000, .irq = INT_24XX_GPTIMER5 },
-        { .phys_base = 0x4903A000, .irq = INT_24XX_GPTIMER6 },
-        { .phys_base = 0x4903C000, .irq = INT_24XX_GPTIMER7 },
-        { .phys_base = 0x4903E000, .irq = INT_24XX_GPTIMER8 },
-        { .phys_base = 0x49040000, .irq = INT_24XX_GPTIMER9 },
-        { .phys_base = 0x48086000, .irq = INT_24XX_GPTIMER10 },
-        { .phys_base = 0x48088000, .irq = INT_24XX_GPTIMER11 },
-        { .phys_base = 0x48304000, .irq = INT_34XX_GPT12_IRQ },
-};
-static const char *omap3_dm_source_names[] __initdata = {
-        "sys_ck",
-        "omap_32k_fck",
-        NULL
-};
-static struct clk *omap3_dm_source_clocks[2];
-static const int omap3_dm_timer_count = ARRAY_SIZE(omap3_dm_timers);
-#else
+#include <plat/dmtimer.h>
-#define omap3_dm_timers                 NULL
-#define omap3_dm_timer_count            0
-#define omap3_dm_source_names           NULL
-#define omap3_dm_source_clocks          NULL
-#endif  /* CONFIG_ARCH_OMAP3 */
-#ifdef CONFIG_ARCH_OMAP4
-static struct omap_dm_timer omap4_dm_timers[] = {
-        { .phys_base = 0x4a318000, .irq = OMAP44XX_IRQ_GPT1 },
-        { .phys_base = 0x48032000, .irq = OMAP44XX_IRQ_GPT2 },
-        { .phys_base = 0x48034000, .irq = OMAP44XX_IRQ_GPT3 },
-        { .phys_base = 0x48036000, .irq = OMAP44XX_IRQ_GPT4 },
-        { .phys_base = 0x40138000, .irq = OMAP44XX_IRQ_GPT5 },
-        { .phys_base = 0x4013a000, .irq = OMAP44XX_IRQ_GPT6 },
-        { .phys_base = 0x4013a000, .irq = OMAP44XX_IRQ_GPT7 },
-        { .phys_base = 0x4013e000, .irq = OMAP44XX_IRQ_GPT8 },
-        { .phys_base = 0x4803e000, .irq = OMAP44XX_IRQ_GPT9 },
-        { .phys_base = 0x48086000, .irq = OMAP44XX_IRQ_GPT10 },
-        { .phys_base = 0x48088000, .irq = OMAP44XX_IRQ_GPT11 },
-        { .phys_base = 0x4a320000, .irq = OMAP44XX_IRQ_GPT12 },
-};
-static const char *omap4_dm_source_names[] __initdata = {
-        "sys_clkin_ck",
-        "sys_32k_ck",
-        NULL
-};
-static struct clk *omap4_dm_source_clocks[2];
-static const int omap4_dm_timer_count = ARRAY_SIZE(omap4_dm_timers);
-#else
-#define omap4_dm_timers                 NULL
-#define omap4_dm_timer_count            0
-#define omap4_dm_source_names           NULL
-#define omap4_dm_source_clocks          NULL
-#endif  /* CONFIG_ARCH_OMAP4 */
-static struct omap_dm_timer *dm_timers;
-static const char **dm_source_names;
-static struct clk **dm_source_clocks;
-static spinlock_t dm_timer_lock;
+static LIST_HEAD(omap_timer_list);
+static DEFINE_SPINLOCK(dm_timer_lock);
-/*
+/**
- * Reads timer registers in posted and non-posted mode. The posted mode bit
+ * omap_dm_timer_read_reg - read timer registers in posted and non-posted mode
- * is encoded in reg. Note that in posted mode write pending bit must be
+ * @timer:      timer pointer over which read operation to perform
- * checked. Otherwise a read of a non completed write will produce an error.
+ * @reg:        lowest byte holds the register offset
+ *
+ * The posted mode bit is encoded in reg. Note that in posted mode write
+ * pending bit must be checked. Otherwise a read of a non completed write
+ * will produce an error.
 */
 static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, u32 reg)
 {
-        return __omap_dm_timer_read(timer->io_base, reg, timer->posted);
+        WARN_ON((reg & 0xff) < _OMAP_TIMER_WAKEUP_EN_OFFSET);
+        return __omap_dm_timer_read(timer, reg, timer->posted);
 }
-/*
+/**
- * Writes timer registers in posted and non-posted mode. The posted mode bit
+ * omap_dm_timer_write_reg - write timer registers in posted and non-posted mode
- * is encoded in reg. Note that in posted mode the write pending bit must be
+ * @timer:      timer pointer over which write operation is to perform
- * checked. Otherwise a write on a register which has a pending write will be
+ * @reg:        lowest byte holds the register offset
- * lost.
+ * @value:      data to write into the register
+ *
+ * The posted mode bit is encoded in reg. Note that in posted mode the write
+ * pending bit must be checked. Otherwise a write on a register which has a
+ * pending write will be lost.
 */
 static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg,
                                                u32 value)
 {
-        __omap_dm_timer_write(timer->io_base, reg, value, timer->posted);
+        WARN_ON((reg & 0xff) < _OMAP_TIMER_WAKEUP_EN_OFFSET);
+        __omap_dm_timer_write(timer, reg, value, timer->posted);
+}
+static void omap_timer_restore_context(struct omap_dm_timer *timer)
+{
+        omap_dm_timer_write_reg(timer, OMAP_TIMER_OCP_CFG_OFFSET,
+                                timer->context.tiocp_cfg);
+        if (timer->revision > 1)
+                __raw_writel(timer->context.tistat, timer->sys_stat);
+        __raw_writel(timer->context.tisr, timer->irq_stat);
+        omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG,
+                                timer->context.twer);
+        omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG,
+                                timer->context.tcrr);
+        omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG,
+                                timer->context.tldr);
+        omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG,
+                                timer->context.tmar);
+        omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG,
+                                timer->context.tsicr);
+        __raw_writel(timer->context.tier, timer->irq_ena);
+        omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG,
+                                timer->context.tclr);
 }
 static void omap_dm_timer_wait_for_reset(struct omap_dm_timer *timer)
 {
        int c;
+        if (!timer->sys_stat)
+                return;
        c = 0;
-        while (!(omap_dm_timer_read_reg(timer, OMAP_TIMER_SYS_STAT_REG) & 1)) {
+        while (!(__raw_readl(timer->sys_stat) & 1)) {
                c++;
                if (c > 100000) {
                        printk(KERN_ERR "Timer failed to reset\n");
@@ -201,53 +119,65 @@ static void omap_dm_timer_wait_for_reset(struct omap_dm_timer *timer)
 static void omap_dm_timer_reset(struct omap_dm_timer *timer)
 {
-        int autoidle = 0, wakeup = 0;
+        omap_dm_timer_enable(timer);
+        if (timer->pdev->id != 1) {
-        if (!cpu_class_is_omap2() || timer != &dm_timers[0]) {
                omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06);
                omap_dm_timer_wait_for_reset(timer);
        }
-        omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ);
-        /* Enable autoidle on OMAP2+ */
-        if (cpu_class_is_omap2())
-                autoidle = 1;
-        /*
-         * Enable wake-up on OMAP2 CPUs.
-         */
-        if (cpu_class_is_omap2())
-                wakeup = 1;
-        __omap_dm_timer_reset(timer->io_base, autoidle, wakeup);
+        __omap_dm_timer_reset(timer, 0, 0);
+        omap_dm_timer_disable(timer);
        timer->posted = 1;
 }
-void omap_dm_timer_prepare(struct omap_dm_timer *timer)
+int omap_dm_timer_prepare(struct omap_dm_timer *timer)
 {
-        omap_dm_timer_enable(timer);
+        struct dmtimer_platform_data *pdata = timer->pdev->dev.platform_data;
-        omap_dm_timer_reset(timer);
+        int ret;
+        timer->fclk = clk_get(&timer->pdev->dev, "fck");
+        if (WARN_ON_ONCE(IS_ERR_OR_NULL(timer->fclk))) {
+                timer->fclk = NULL;
+                dev_err(&timer->pdev->dev, ": No fclk handle.\n");
+                return -EINVAL;
+        }
+        if (pdata->needs_manual_reset)
+                omap_dm_timer_reset(timer);
+        ret = omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ);
+        timer->posted = 1;
+        return ret;
 }
 struct omap_dm_timer *omap_dm_timer_request(void)
 {
-        struct omap_dm_timer *timer = NULL;
+        struct omap_dm_timer *timer = NULL, *t;
        unsigned long flags;
-        int i;
+        int ret = 0;
        spin_lock_irqsave(&dm_timer_lock, flags);
-        for (i = 0; i < dm_timer_count; i++) {
+        list_for_each_entry(t, &omap_timer_list, node) {
-                if (dm_timers[i].reserved)
+                if (t->reserved)
                        continue;
-                timer = &dm_timers[i];
+                timer = t;
                timer->reserved = 1;
                break;
        }
+        if (timer) {
+                ret = omap_dm_timer_prepare(timer);
+                if (ret) {
+                        timer->reserved = 0;
+                        timer = NULL;
+                }
+        }
        spin_unlock_irqrestore(&dm_timer_lock, flags);
-        if (timer != NULL)
+        if (!timer)
-                omap_dm_timer_prepare(timer);
+                pr_debug("%s: timer request failed!\n", __func__);
        return timer;
 }
@@ -255,74 +185,65 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_request);
 struct omap_dm_timer *omap_dm_timer_request_specific(int id)
 {
-        struct omap_dm_timer *timer;
+        struct omap_dm_timer *timer = NULL, *t;
        unsigned long flags;
+        int ret = 0;
        spin_lock_irqsave(&dm_timer_lock, flags);
-        if (id <= 0 || id > dm_timer_count || dm_timers[id-1].reserved) {
+        list_for_each_entry(t, &omap_timer_list, node) {
-                spin_unlock_irqrestore(&dm_timer_lock, flags);
+                if (t->pdev->id == id && !t->reserved) {
-                printk("BUG: warning at %s:%d/%s(): unable to get timer %d\n",
+                        timer = t;
-                       __FILE__, __LINE__, __func__, id);
+                        timer->reserved = 1;
-                dump_stack();
+                        break;
-                return NULL;
+                }
        }
-        timer = &dm_timers[id-1];
+        if (timer) {
-        timer->reserved = 1;
+                ret = omap_dm_timer_prepare(timer);
+                if (ret) {
+                        timer->reserved = 0;
+                        timer = NULL;
+                }
+        }
        spin_unlock_irqrestore(&dm_timer_lock, flags);
-        omap_dm_timer_prepare(timer);
+        if (!timer)
+                pr_debug("%s: timer%d request failed!\n", __func__, id);
        return timer;
 }
 EXPORT_SYMBOL_GPL(omap_dm_timer_request_specific);
-void omap_dm_timer_free(struct omap_dm_timer *timer)
+int omap_dm_timer_free(struct omap_dm_timer *timer)
 {
-        omap_dm_timer_enable(timer);
+        if (unlikely(!timer))
-        omap_dm_timer_reset(timer);
+                return -EINVAL;
-        omap_dm_timer_disable(timer);
+        clk_put(timer->fclk);
        WARN_ON(!timer->reserved);
        timer->reserved = 0;
+        return 0;
 }
 EXPORT_SYMBOL_GPL(omap_dm_timer_free);
 void omap_dm_timer_enable(struct omap_dm_timer *timer)
 {
-        if (timer->enabled)
+        pm_runtime_get_sync(&timer->pdev->dev);
-                return;
-#ifdef CONFIG_ARCH_OMAP2PLUS
-        if (cpu_class_is_omap2()) {
-                clk_enable(timer->fclk);
-                clk_enable(timer->iclk);
-        }
-#endif
-        timer->enabled = 1;
 }
 EXPORT_SYMBOL_GPL(omap_dm_timer_enable);
 void omap_dm_timer_disable(struct omap_dm_timer *timer)
 {
-        if (!timer->enabled)
+        pm_runtime_put(&timer->pdev->dev);
-                return;
-#ifdef CONFIG_ARCH_OMAP2PLUS
-        if (cpu_class_is_omap2()) {
-                clk_disable(timer->iclk);
-                clk_disable(timer->fclk);
-        }
-#endif
-        timer->enabled = 0;
 }
 EXPORT_SYMBOL_GPL(omap_dm_timer_disable);
 int omap_dm_timer_get_irq(struct omap_dm_timer *timer)
 {
-        return timer->irq;
+        if (timer)
+                return timer->irq;
+        return -EINVAL;
 }
 EXPORT_SYMBOL_GPL(omap_dm_timer_get_irq);
@@ -334,24 +255,29 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_get_irq);
 */
 __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
 {
-        int i;
+        int i = 0;
+        struct omap_dm_timer *timer = NULL;
+        unsigned long flags;
        /* If ARMXOR cannot be idled this function call is unnecessary */
        if (!(inputmask & (1 << 1)))
                return inputmask;
        /* If any active timer is using ARMXOR return modified mask */
-        for (i = 0; i < dm_timer_count; i++) {
+        spin_lock_irqsave(&dm_timer_lock, flags);
+        list_for_each_entry(timer, &omap_timer_list, node) {
                u32 l;
-                l = omap_dm_timer_read_reg(&dm_timers[i], OMAP_TIMER_CTRL_REG);
+                l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
                if (l & OMAP_TIMER_CTRL_ST) {
                        if (((omap_readl(MOD_CONF_CTRL_1) >> (i * 2)) & 0x03) == 0)
                                inputmask &= ~(1 << 1);
                        else
                                inputmask &= ~(1 << 2);
                }
+                i++;
        }
+        spin_unlock_irqrestore(&dm_timer_lock, flags);
        return inputmask;
 }
@@ -361,7 +287,9 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_modify_idlect_mask);
 struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer)
 {
-        return timer->fclk;
+        if (timer)
+                return timer->fclk;
+        return NULL;
 }
 EXPORT_SYMBOL_GPL(omap_dm_timer_get_fclk);
@@ -375,70 +303,91 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_modify_idlect_mask);
 #endif
-void omap_dm_timer_trigger(struct omap_dm_timer *timer)
+int omap_dm_timer_trigger(struct omap_dm_timer *timer)
 {
+        if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) {
+                pr_err("%s: timer not available or enabled.\n", __func__);
+                return -EINVAL;
+        }
        omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
+        return 0;
 }
 EXPORT_SYMBOL_GPL(omap_dm_timer_trigger);
-void omap_dm_timer_start(struct omap_dm_timer *timer)
+int omap_dm_timer_start(struct omap_dm_timer *timer)
 {
        u32 l;
+        if (unlikely(!timer))
+                return -EINVAL;
+        omap_dm_timer_enable(timer);
+        if (timer->loses_context) {
+                u32 ctx_loss_cnt_after =
+                        timer->get_context_loss_count(&timer->pdev->dev);
+                if (ctx_loss_cnt_after != timer->ctx_loss_count)
+                        omap_timer_restore_context(timer);
+        }
        l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
        if (!(l & OMAP_TIMER_CTRL_ST)) {
                l |= OMAP_TIMER_CTRL_ST;
                omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
        }
+        /* Save the context */
+        timer->context.tclr = l;
+        return 0;
 }
 EXPORT_SYMBOL_GPL(omap_dm_timer_start);
-void omap_dm_timer_stop(struct omap_dm_timer *timer)
+int omap_dm_timer_stop(struct omap_dm_timer *timer)
 {
        unsigned long rate = 0;
+        struct dmtimer_platform_data *pdata = timer->pdev->dev.platform_data;
-#ifdef CONFIG_ARCH_OMAP2PLUS
+        if (unlikely(!timer))
-        rate = clk_get_rate(timer->fclk);
+                return -EINVAL;
-#endif
-        __omap_dm_timer_stop(timer->io_base, timer->posted, rate);
+        if (!pdata->needs_manual_reset)
+                rate = clk_get_rate(timer->fclk);
+        __omap_dm_timer_stop(timer, timer->posted, rate);
+        return 0;
 }
 EXPORT_SYMBOL_GPL(omap_dm_timer_stop);
-#ifdef CONFIG_ARCH_OMAP1
 int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
 {
-        int n = (timer - dm_timers) << 1;
+        int ret;
-        u32 l;
+        struct dmtimer_platform_data *pdata;
-        l = omap_readl(MOD_CONF_CTRL_1) & ~(0x03 << n);
-        l |= source << n;
-        omap_writel(l, MOD_CONF_CTRL_1);
-        return 0;
+        if (unlikely(!timer))
-}
+                return -EINVAL;
-EXPORT_SYMBOL_GPL(omap_dm_timer_set_source);
-#else
+        pdata = timer->pdev->dev.platform_data;
-int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
-{
        if (source < 0 || source >= 3)
                return -EINVAL;
-        return __omap_dm_timer_set_source(timer->fclk,
+        ret = pdata->set_timer_src(timer->pdev, source);
-                                                dm_source_clocks[source]);
+        return ret;
 }
 EXPORT_SYMBOL_GPL(omap_dm_timer_set_source);
-#endif
+int omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload,
-void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload,
                            unsigned int load)
 {
        u32 l;
+        if (unlikely(!timer))
+                return -EINVAL;
+        omap_dm_timer_enable(timer);
        l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
        if (autoreload)
                l |= OMAP_TIMER_CTRL_AR;
@@ -448,15 +397,32 @@ void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload,
        omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load);
        omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
+        /* Save the context */
+        timer->context.tclr = l;
+        timer->context.tldr = load;
+        omap_dm_timer_disable(timer);
+        return 0;
 }
 EXPORT_SYMBOL_GPL(omap_dm_timer_set_load);
 /* Optimized set_load which removes costly spin wait in timer_start */
-void omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload,
+int omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload,
                            unsigned int load)
 {
        u32 l;
+        if (unlikely(!timer))
+                return -EINVAL;
+        omap_dm_timer_enable(timer);
+        if (timer->loses_context) {
+                u32 ctx_loss_cnt_after =
+                        timer->get_context_loss_count(&timer->pdev->dev);
+                if (ctx_loss_cnt_after != timer->ctx_loss_count)
+                        omap_timer_restore_context(timer);
+        }
        l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
        if (autoreload) {
                l |= OMAP_TIMER_CTRL_AR;
@@ -466,15 +432,25 @@ void omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload,
        }
        l |= OMAP_TIMER_CTRL_ST;
-        __omap_dm_timer_load_start(timer->io_base, l, load, timer->posted);
+        __omap_dm_timer_load_start(timer, l, load, timer->posted);
+        /* Save the context */
+        timer->context.tclr = l;
+        timer->context.tldr = load;
+        timer->context.tcrr = load;
+        return 0;
 }
 EXPORT_SYMBOL_GPL(omap_dm_timer_set_load_start);
-void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable,
+int omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable,
                             unsigned int match)
 {
        u32 l;
+        if (unlikely(!timer))
+                return -EINVAL;
+        omap_dm_timer_enable(timer);
        l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
        if (enable)
                l |= OMAP_TIMER_CTRL_CE;
@@ -482,14 +458,24 @@ void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable,
                l &= ~OMAP_TIMER_CTRL_CE;
        omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
        omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match);
+        /* Save the context */
+        timer->context.tclr = l;
+        timer->context.tmar = match;
+        omap_dm_timer_disable(timer);
+        return 0;
 }
 EXPORT_SYMBOL_GPL(omap_dm_timer_set_match);
-void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on,
+int omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on,
                           int toggle, int trigger)
 {
        u32 l;
+        if (unlikely(!timer))
+                return -EINVAL;
+        omap_dm_timer_enable(timer);
        l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
        l &= ~(OMAP_TIMER_CTRL_GPOCFG | OMAP_TIMER_CTRL_SCPWM |
               OMAP_TIMER_CTRL_PT | (0x03 << 10));
@@ -499,13 +485,22 @@ void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on,
                l |= OMAP_TIMER_CTRL_PT;
        l |= trigger << 10;
        omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
+        /* Save the context */
+        timer->context.tclr = l;
+        omap_dm_timer_disable(timer);
+        return 0;
 }
 EXPORT_SYMBOL_GPL(omap_dm_timer_set_pwm);
-void omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler)
+int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler)
 {
        u32 l;
+        if (unlikely(!timer))
+                return -EINVAL;
+        omap_dm_timer_enable(timer);
        l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
        l &= ~(OMAP_TIMER_CTRL_PRE | (0x07 << 2));
        if (prescaler >= 0x00 && prescaler <= 0x07) {
@@ -513,13 +508,28 @@ void omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler)
                l |= prescaler << 2;
        }
        omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
+        /* Save the context */
+        timer->context.tclr = l;
+        omap_dm_timer_disable(timer);
+        return 0;
 }
 EXPORT_SYMBOL_GPL(omap_dm_timer_set_prescaler);
-void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer,
+int omap_dm_timer_set_int_enable(struct omap_dm_timer *timer,
                                  unsigned int value)
 {
-        __omap_dm_timer_int_enable(timer->io_base, value);
+        if (unlikely(!timer))
+                return -EINVAL;
+        omap_dm_timer_enable(timer);
+        __omap_dm_timer_int_enable(timer, value);
+        /* Save the context */
+        timer->context.tier = value;
+        timer->context.twer = value;
+        omap_dm_timer_disable(timer);
+        return 0;
 }
 EXPORT_SYMBOL_GPL(omap_dm_timer_set_int_enable);
@@ -527,40 +537,61 @@ unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer)
 {
        unsigned int l;
-        l = omap_dm_timer_read_reg(timer, OMAP_TIMER_STAT_REG);
+        if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) {
+                pr_err("%s: timer not available or enabled.\n", __func__);
+                return 0;
+        }
+        l = __raw_readl(timer->irq_stat);
        return l;
 }
 EXPORT_SYMBOL_GPL(omap_dm_timer_read_status);
-void omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value)
+int omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value)
 {
-        __omap_dm_timer_write_status(timer->io_base, value);
+        if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev)))
+                return -EINVAL;
+        __omap_dm_timer_write_status(timer, value);
+        /* Save the context */
+        timer->context.tisr = value;
+        return 0;
 }
 EXPORT_SYMBOL_GPL(omap_dm_timer_write_status);
 unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer)
 {
-        return __omap_dm_timer_read_counter(timer->io_base, timer->posted);
+        if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) {
+                pr_err("%s: timer not iavailable or enabled.\n", __func__);
+                return 0;
+        }
+        return __omap_dm_timer_read_counter(timer, timer->posted);
 }
 EXPORT_SYMBOL_GPL(omap_dm_timer_read_counter);
-void omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value)
+int omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value)
 {
+        if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) {
+                pr_err("%s: timer not available or enabled.\n", __func__);
+                return -EINVAL;
+        }
        omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, value);
+        /* Save the context */
+        timer->context.tcrr = value;
+        return 0;
 }
 EXPORT_SYMBOL_GPL(omap_dm_timer_write_counter);
 int omap_dm_timers_active(void)
 {
-        int i;
+        struct omap_dm_timer *timer;
-        for (i = 0; i < dm_timer_count; i++) {
-                struct omap_dm_timer *timer;
-                timer = &dm_timers[i];
-                if (!timer->enabled)
+        list_for_each_entry(timer, &omap_timer_list, node) {
+                if (!timer->reserved)
                        continue;
                if (omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG) &
@@ -572,69 +603,147 @@ int omap_dm_timers_active(void)
 }
 EXPORT_SYMBOL_GPL(omap_dm_timers_active);
-static int __init omap_dm_timer_init(void)
+/**
+ * omap_dm_timer_probe - probe function called for every registered device
+ * @pdev:       pointer to current timer platform device
+ *
+ * Called by driver framework at the end of device registration for all
+ * timer devices.
+ */
+static int __devinit omap_dm_timer_probe(struct platform_device *pdev)
 {
+        int ret;
+        unsigned long flags;
        struct omap_dm_timer *timer;
-        int i, map_size = SZ_8K;        /* Module 4KB + L4 4KB except on omap1 */
+        struct resource *mem, *irq, *ioarea;
+        struct dmtimer_platform_data *pdata = pdev->dev.platform_data;
-        if (!(cpu_is_omap16xx() || cpu_class_is_omap2()))
+        if (!pdata) {
+                dev_err(&pdev->dev, "%s: no platform data.\n", __func__);
                return -ENODEV;
+        }
-        spin_lock_init(&dm_timer_lock);
+        irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+        if (unlikely(!irq)) {
-        if (cpu_class_is_omap1()) {
+                dev_err(&pdev->dev, "%s: no IRQ resource.\n", __func__);
-                dm_timers = omap1_dm_timers;
+                return -ENODEV;
-                dm_timer_count = omap1_dm_timer_count;
-                map_size = SZ_2K;
-        } else if (cpu_is_omap24xx()) {
-                dm_timers = omap2_dm_timers;
-                dm_timer_count = omap2_dm_timer_count;
-                dm_source_names = omap2_dm_source_names;
-                dm_source_clocks = omap2_dm_source_clocks;
-        } else if (cpu_is_omap34xx()) {
-                dm_timers = omap3_dm_timers;
-                dm_timer_count = omap3_dm_timer_count;
-                dm_source_names = omap3_dm_source_names;
-                dm_source_clocks = omap3_dm_source_clocks;
-        } else if (cpu_is_omap44xx()) {
-                dm_timers = omap4_dm_timers;
-                dm_timer_count = omap4_dm_timer_count;
-                dm_source_names = omap4_dm_source_names;
-                dm_source_clocks = omap4_dm_source_clocks;
        }
-        if (cpu_class_is_omap2())
+        mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-                for (i = 0; dm_source_names[i] != NULL; i++)
+        if (unlikely(!mem)) {
-                        dm_source_clocks[i] = clk_get(NULL, dm_source_names[i]);
+                dev_err(&pdev->dev, "%s: no memory resource.\n", __func__);
+                return -ENODEV;
+        }
-        if (cpu_is_omap243x())
+        ioarea = request_mem_region(mem->start, resource_size(mem),
-                dm_timers[0].phys_base = 0x49018000;
+                        pdev->name);
+        if (!ioarea) {
+                dev_err(&pdev->dev, "%s: region already claimed.\n", __func__);
+                return -EBUSY;
+        }
-        for (i = 0; i < dm_timer_count; i++) {
+        timer = kzalloc(sizeof(struct omap_dm_timer), GFP_KERNEL);
-                timer = &dm_timers[i];
+        if (!timer) {
+                dev_err(&pdev->dev, "%s: no memory for omap_dm_timer.\n",
+                        __func__);
+                ret = -ENOMEM;
+                goto err_free_ioregion;
+        }
-                /* Static mapping, never released */
+        timer->io_base = ioremap(mem->start, resource_size(mem));
-                timer->io_base = ioremap(timer->phys_base, map_size);
+        if (!timer->io_base) {
-                BUG_ON(!timer->io_base);
+                dev_err(&pdev->dev, "%s: ioremap failed.\n", __func__);
+                ret = -ENOMEM;
+                goto err_free_mem;
+        }
-#ifdef CONFIG_ARCH_OMAP2PLUS
+        timer->id = pdev->id;
-                if (cpu_class_is_omap2()) {
+        timer->irq = irq->start;
-                        char clk_name[16];
+        timer->reserved = pdata->reserved;
-                        sprintf(clk_name, "gpt%d_ick", i + 1);
+        timer->pdev = pdev;
-                        timer->iclk = clk_get(NULL, clk_name);
+        timer->loses_context = pdata->loses_context;
-                        sprintf(clk_name, "gpt%d_fck", i + 1);
+        timer->get_context_loss_count = pdata->get_context_loss_count;
-                        timer->fclk = clk_get(NULL, clk_name);
-                }
+        /* Skip pm_runtime_enable for OMAP1 */
+        if (!pdata->needs_manual_reset) {
+                pm_runtime_enable(&pdev->dev);
+                pm_runtime_irq_safe(&pdev->dev);
+        }
-                /* One or two timers may be set up early for sys_timer */
+        if (!timer->reserved) {
-                if (sys_timer_reserved & (1  << i)) {
+                pm_runtime_get_sync(&pdev->dev);
-                        timer->reserved = 1;
+                __omap_dm_timer_init_regs(timer);
-                        timer->posted = 1;
+                pm_runtime_put(&pdev->dev);
-                }
-#endif
        }
+        /* add the timer element to the list */
+        spin_lock_irqsave(&dm_timer_lock, flags);
+        list_add_tail(&timer->node, &omap_timer_list);
+        spin_unlock_irqrestore(&dm_timer_lock, flags);
+        dev_dbg(&pdev->dev, "Device Probed.\n");
        return 0;
+err_free_mem:
+        kfree(timer);
+err_free_ioregion:
+        release_mem_region(mem->start, resource_size(mem));
+        return ret;
 }
-arch_initcall(omap_dm_timer_init);
+/**
+ * omap_dm_timer_remove - cleanup a registered timer device
+ * @pdev:       pointer to current timer platform device
+ *
+ * Called by driver framework whenever a timer device is unregistered.
+ * In addition to freeing platform resources it also deletes the timer
+ * entry from the local list.
+ */
+static int __devexit omap_dm_timer_remove(struct platform_device *pdev)
+{
+        struct omap_dm_timer *timer;
+        unsigned long flags;
+        int ret = -EINVAL;
+        spin_lock_irqsave(&dm_timer_lock, flags);
+        list_for_each_entry(timer, &omap_timer_list, node)
+                if (timer->pdev->id == pdev->id) {
+                        list_del(&timer->node);
+                        kfree(timer);
+                        ret = 0;
+                        break;
+                }
+        spin_unlock_irqrestore(&dm_timer_lock, flags);
+        return ret;
+}
+static struct platform_driver omap_dm_timer_driver = {
+        .probe  = omap_dm_timer_probe,
+        .remove = __devexit_p(omap_dm_timer_remove),
+        .driver = {
+                .name   = "omap_timer",
+        },
+};
+static int __init omap_dm_timer_driver_init(void)
+{
+        return platform_driver_register(&omap_dm_timer_driver);
+}
+static void __exit omap_dm_timer_driver_exit(void)
+{
+        platform_driver_unregister(&omap_dm_timer_driver);
+}
+early_platform_init("earlytimer", &omap_dm_timer_driver);
+module_init(omap_dm_timer_driver_init);
+module_exit(omap_dm_timer_driver_exit);
+MODULE_DESCRIPTION("OMAP Dual-Mode Timer Driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:" DRIVER_NAME);
+MODULE_AUTHOR("Texas Instruments Inc");
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index df4b9683f17f..197ca03c3f7d 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -80,8 +80,6 @@ struct clkops {
 *
 * @div is the divisor that should be applied to the parent clock's rate
 * to produce the current clock's rate.
- *
- * XXX @flags probably should be replaced with an struct omap_chip.
 */
 struct clksel_rate {
        u32                     val;
diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h
index 4564cc697d7f..5cac97e36079 100644
--- a/arch/arm/plat-omap/include/plat/common.h
+++ b/arch/arm/plat-omap/include/plat/common.h
@@ -45,6 +45,15 @@ extern unsigned long long notrace omap_32k_sched_clock(void);
 extern void omap_reserve(void);
+void omap2420_init_early(void);
+void omap2430_init_early(void);
+void omap3430_init_early(void);
+void omap35xx_init_early(void);
+void omap3630_init_early(void);
+void am35xx_init_early(void);
+void ti816x_init_early(void);
+void omap4430_init_early(void);
 /*
 * IO bases for various OMAP processors
 * Except the tap base, rest all the io bases
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index 67b3d75884cd..2f9026942229 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -44,13 +44,6 @@
 int omap_type(void);
-struct omap_chip_id {
-        u16 oc;
-        u8 type;
-};
-#define OMAP_CHIP_INIT(x)       { .oc = x }
 /*
 * omap_rev bits:
 * CPU id bits  (0730, 1510, 1710, 2422...)     [31:16]
@@ -60,19 +53,6 @@ struct omap_chip_id {
 unsigned int omap_rev(void);
 /*
- * Define CPU revision bits
- *
- * Verbose meaning of the revision bits may be different for a silicon
- * family. This difference can be handled separately.
- */
-#define OMAP_REVBITS_00         0x00
-#define OMAP_REVBITS_01         0x01
-#define OMAP_REVBITS_02         0x02
-#define OMAP_REVBITS_03         0x03
-#define OMAP_REVBITS_04         0x04
-#define OMAP_REVBITS_05         0x05
-/*
 * Get the CPU revision for OMAP devices
 */
 #define GET_OMAP_REVISION()     ((omap_rev() >> 8) & 0xff)
@@ -262,7 +242,7 @@ IS_OMAP_TYPE(2422, 0x2422)
 IS_OMAP_TYPE(2423, 0x2423)
 IS_OMAP_TYPE(2430, 0x2430)
 IS_OMAP_TYPE(3430, 0x3430)
-IS_OMAP_TYPE(3505, 0x3505)
+IS_OMAP_TYPE(3505, 0x3517)
 IS_OMAP_TYPE(3517, 0x3517)
 #define cpu_is_omap310()                0
@@ -354,8 +334,9 @@ IS_OMAP_TYPE(3517, 0x3517)
                                                (!omap3_has_sgx()) &&   \
                                                (omap3_has_iva()))
 # define cpu_is_omap3530()              (cpu_is_omap3430())
-# define cpu_is_omap3505()              is_omap3505()
 # define cpu_is_omap3517()              is_omap3517()
+# define cpu_is_omap3505()              (cpu_is_omap3517() &&           \
+                                                !omap3_has_sgx())
 # undef cpu_is_omap3630
 # define cpu_is_omap3630()              is_omap363x()
 # define cpu_is_ti816x()                is_ti816x()
@@ -379,35 +360,31 @@ IS_OMAP_TYPE(3517, 0x3517)
 /* Various silicon revisions for omap2 */
 #define OMAP242X_CLASS          0x24200024
 #define OMAP2420_REV_ES1_0      OMAP242X_CLASS
-#define OMAP2420_REV_ES2_0      (OMAP242X_CLASS | (OMAP_REVBITS_01 << 8))
+#define OMAP2420_REV_ES2_0      (OMAP242X_CLASS | (0x1 << 8))
 #define OMAP243X_CLASS          0x24300024
 #define OMAP2430_REV_ES1_0      OMAP243X_CLASS
 #define OMAP343X_CLASS          0x34300034
 #define OMAP3430_REV_ES1_0      OMAP343X_CLASS
-#define OMAP3430_REV_ES2_0      (OMAP343X_CLASS | (OMAP_REVBITS_01 << 8))
+#define OMAP3430_REV_ES2_0      (OMAP343X_CLASS | (0x1 << 8))
-#define OMAP3430_REV_ES2_1      (OMAP343X_CLASS | (OMAP_REVBITS_02 << 8))
+#define OMAP3430_REV_ES2_1      (OMAP343X_CLASS | (0x2 << 8))
-#define OMAP3430_REV_ES3_0      (OMAP343X_CLASS | (OMAP_REVBITS_03 << 8))
+#define OMAP3430_REV_ES3_0      (OMAP343X_CLASS | (0x3 << 8))
-#define OMAP3430_REV_ES3_1      (OMAP343X_CLASS | (OMAP_REVBITS_04 << 8))
+#define OMAP3430_REV_ES3_1      (OMAP343X_CLASS | (0x4 << 8))
-#define OMAP3430_REV_ES3_1_2    (OMAP343X_CLASS | (OMAP_REVBITS_05 << 8))
+#define OMAP3430_REV_ES3_1_2    (OMAP343X_CLASS | (0x5 << 8))
 #define OMAP363X_CLASS          0x36300034
 #define OMAP3630_REV_ES1_0      OMAP363X_CLASS
-#define OMAP3630_REV_ES1_1      (OMAP363X_CLASS | (OMAP_REVBITS_01 << 8))
+#define OMAP3630_REV_ES1_1      (OMAP363X_CLASS | (0x1 << 8))
-#define OMAP3630_REV_ES1_2      (OMAP363X_CLASS | (OMAP_REVBITS_02 << 8))
+#define OMAP3630_REV_ES1_2      (OMAP363X_CLASS | (0x2 << 8))
-#define OMAP35XX_CLASS          0x35000034
+#define OMAP3517_CLASS          0x35170034
-#define OMAP3503_REV(v)         (OMAP35XX_CLASS | (0x3503 << 16) | (v << 8))
+#define OMAP3517_REV_ES1_0      OMAP3517_CLASS
-#define OMAP3515_REV(v)         (OMAP35XX_CLASS | (0x3515 << 16) | (v << 8))
+#define OMAP3517_REV_ES1_1      (OMAP3517_CLASS | (0x1 << 8))
-#define OMAP3525_REV(v)         (OMAP35XX_CLASS | (0x3525 << 16) | (v << 8))
-#define OMAP3530_REV(v)         (OMAP35XX_CLASS | (0x3530 << 16) | (v << 8))
-#define OMAP3505_REV(v)         (OMAP35XX_CLASS | (0x3505 << 16) | (v << 8))
-#define OMAP3517_REV(v)         (OMAP35XX_CLASS | (0x3517 << 16) | (v << 8))
 #define TI816X_CLASS            0x81600034
 #define TI8168_REV_ES1_0        TI816X_CLASS
-#define TI8168_REV_ES1_1        (TI816X_CLASS | (OMAP_REVBITS_01 << 8))
+#define TI8168_REV_ES1_1        (TI816X_CLASS | (0x1 << 8))
 #define OMAP443X_CLASS          0x44300044
 #define OMAP4430_REV_ES1_0      (OMAP443X_CLASS | (0x10 << 8))
@@ -418,61 +395,6 @@ IS_OMAP_TYPE(3517, 0x3517)
 #define OMAP446X_CLASS          0x44600044
 #define OMAP4460_REV_ES1_0      (OMAP446X_CLASS | (0x10 << 8))
-/*
- * omap_chip bits
- *
- * CHIP_IS_OMAP{2420,2430,3430} indicate that a particular structure is
- * valid on all chips of that type.  CHIP_IS_OMAP3430ES{1,2} indicates
- * something that is only valid on that particular ES revision.
- *
- * These bits may be ORed together to indicate structures that are
- * available on multiple chip types.
- *
- * To test whether a particular structure matches the current OMAP chip type,
- * use omap_chip_is().
- *
- */
-#define CHIP_IS_OMAP2420                (1 << 0)
-#define CHIP_IS_OMAP2430                (1 << 1)
-#define CHIP_IS_OMAP3430                (1 << 2)
-#define CHIP_IS_OMAP3430ES1             (1 << 3)
-#define CHIP_IS_OMAP3430ES2             (1 << 4)
-#define CHIP_IS_OMAP3430ES3_0           (1 << 5)
-#define CHIP_IS_OMAP3430ES3_1           (1 << 6)
-#define CHIP_IS_OMAP3630ES1             (1 << 7)
-#define CHIP_IS_OMAP4430ES1             (1 << 8)
-#define CHIP_IS_OMAP3630ES1_1           (1 << 9)
-#define CHIP_IS_OMAP3630ES1_2           (1 << 10)
-#define CHIP_IS_OMAP4430ES2             (1 << 11)
-#define CHIP_IS_OMAP4430ES2_1           (1 << 12)
-#define CHIP_IS_OMAP4430ES2_2           (1 << 13)
-#define CHIP_IS_TI816X                  (1 << 14)
-#define CHIP_IS_OMAP4460ES1_0           (1 << 15)
-#define CHIP_IS_OMAP24XX                (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430)
-#define CHIP_IS_OMAP4430                (CHIP_IS_OMAP4430ES1 |          \
-                                         CHIP_IS_OMAP4430ES2 |          \
-                                         CHIP_IS_OMAP4430ES2_1 |        \
-                                         CHIP_IS_OMAP4430ES2_2 |        \
-                                         CHIP_IS_OMAP4460ES1_0)
-/*
- * "GE" here represents "greater than or equal to" in terms of ES
- * levels.  So CHIP_GE_OMAP3430ES2 is intended to match all OMAP3430
- * chips at ES2 and beyond, but not, for example, any OMAP lines after
- * OMAP3.
- */
-#define CHIP_GE_OMAP3430ES2             (CHIP_IS_OMAP3430ES2 | \
-                                         CHIP_IS_OMAP3430ES3_0 | \
-                                         CHIP_GE_OMAP3430ES3_1)
-#define CHIP_GE_OMAP3430ES3_1           (CHIP_IS_OMAP3430ES3_1 | \
-                                         CHIP_IS_OMAP3630ES1 | \
-                                         CHIP_GE_OMAP3630ES1_1)
-#define CHIP_GE_OMAP3630ES1_1           (CHIP_IS_OMAP3630ES1_1 | \
-                                         CHIP_IS_OMAP3630ES1_2)
-int omap_chip_is(struct omap_chip_id oci);
 void omap2_check_revision(void);
 /*
diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
index eb5d16c60cd9..d11025e6e7a4 100644
--- a/arch/arm/plat-omap/include/plat/dmtimer.h
+++ b/arch/arm/plat-omap/include/plat/dmtimer.h
@@ -1,5 +1,5 @@
 /*
- * arch/arm/plat-omap/include/mach/dmtimer.h
+ * arch/arm/plat-omap/include/plat/dmtimer.h
 *
 * OMAP Dual-Mode Timers
 *
@@ -35,6 +35,7 @@
 #include <linux/clk.h>
 #include <linux/delay.h>
 #include <linux/io.h>
+#include <linux/platform_device.h>
 #ifndef __ASM_ARCH_DMTIMER_H
 #define __ASM_ARCH_DMTIMER_H
@@ -59,12 +60,56 @@
 * in OMAP4 can be distinguished.
 */
 #define OMAP_TIMER_IP_VERSION_1                        0x1
+/* timer capabilities used in hwmod database */
+#define OMAP_TIMER_SECURE                               0x80000000
+#define OMAP_TIMER_ALWON                                0x40000000
+#define OMAP_TIMER_HAS_PWM                              0x20000000
+struct omap_timer_capability_dev_attr {
+        u32 timer_capability;
+};
 struct omap_dm_timer;
 struct clk;
+struct timer_regs {
+        u32 tidr;
+        u32 tiocp_cfg;
+        u32 tistat;
+        u32 tisr;
+        u32 tier;
+        u32 twer;
+        u32 tclr;
+        u32 tcrr;
+        u32 tldr;
+        u32 ttrg;
+        u32 twps;
+        u32 tmar;
+        u32 tcar1;
+        u32 tsicr;
+        u32 tcar2;
+        u32 tpir;
+        u32 tnir;
+        u32 tcvr;
+        u32 tocr;
+        u32 towr;
+};
+struct dmtimer_platform_data {
+        int (*set_timer_src)(struct platform_device *pdev, int source);
+        int timer_ip_version;
+        u32 needs_manual_reset:1;
+        bool reserved;
+        bool loses_context;
+        u32 (*get_context_loss_count)(struct device *dev);
+};
 struct omap_dm_timer *omap_dm_timer_request(void);
 struct omap_dm_timer *omap_dm_timer_request_specific(int timer_id);
-void omap_dm_timer_free(struct omap_dm_timer *timer);
+int omap_dm_timer_free(struct omap_dm_timer *timer);
 void omap_dm_timer_enable(struct omap_dm_timer *timer);
 void omap_dm_timer_disable(struct omap_dm_timer *timer);
@@ -73,23 +118,23 @@ int omap_dm_timer_get_irq(struct omap_dm_timer *timer);
 u32 omap_dm_timer_modify_idlect_mask(u32 inputmask);
 struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer);
-void omap_dm_timer_trigger(struct omap_dm_timer *timer);
+int omap_dm_timer_trigger(struct omap_dm_timer *timer);
-void omap_dm_timer_start(struct omap_dm_timer *timer);
+int omap_dm_timer_start(struct omap_dm_timer *timer);
-void omap_dm_timer_stop(struct omap_dm_timer *timer);
+int omap_dm_timer_stop(struct omap_dm_timer *timer);
 int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source);
-void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, unsigned int value);
+int omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, unsigned int value);
-void omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, unsigned int value);
+int omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, unsigned int value);
-void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, unsigned int match);
+int omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, unsigned int match);
-void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, int toggle, int trigger);
+int omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, int toggle, int trigger);
-void omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler);
+int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler);
-void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, unsigned int value);
+int omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, unsigned int value);
 unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer);
-void omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value);
+int omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value);
 unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer);
-void omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value);
+int omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value);
 int omap_dm_timers_active(void);
@@ -98,12 +143,30 @@ int omap_dm_timers_active(void);
 * used by dmtimer.c and sys_timer related code.
 */
-/* register offsets */
+/*
-#define _OMAP_TIMER_ID_OFFSET           0x00
+ * The interrupt registers are different between v1 and v2 ip.
-#define _OMAP_TIMER_OCP_CFG_OFFSET      0x10
+ * These registers are offsets from timer->iobase.
-#define _OMAP_TIMER_SYS_STAT_OFFSET     0x14
+ */
-#define _OMAP_TIMER_STAT_OFFSET         0x18
+#define OMAP_TIMER_ID_OFFSET            0x00
-#define _OMAP_TIMER_INT_EN_OFFSET       0x1c
+#define OMAP_TIMER_OCP_CFG_OFFSET       0x10
+#define OMAP_TIMER_V1_SYS_STAT_OFFSET   0x14
+#define OMAP_TIMER_V1_STAT_OFFSET       0x18
+#define OMAP_TIMER_V1_INT_EN_OFFSET     0x1c
+#define OMAP_TIMER_V2_IRQSTATUS_RAW     0x24
+#define OMAP_TIMER_V2_IRQSTATUS         0x28
+#define OMAP_TIMER_V2_IRQENABLE_SET     0x2c
+#define OMAP_TIMER_V2_IRQENABLE_CLR     0x30
+/*
+ * The functional registers have a different base on v1 and v2 ip.
+ * These registers are offsets from timer->func_base. The func_base
+ * is samae as io_base for v1 and io_base + 0x14 for v2 ip.
+ *
+ */
+#define OMAP_TIMER_V2_FUNC_OFFSET               0x14
 #define _OMAP_TIMER_WAKEUP_EN_OFFSET    0x20
 #define _OMAP_TIMER_CTRL_OFFSET         0x24
 #define         OMAP_TIMER_CTRL_GPOCFG          (1 << 14)
@@ -147,21 +210,6 @@ int omap_dm_timers_active(void);
 /* register offsets with the write pending bit encoded */
 #define WPSHIFT                                 16
-#define OMAP_TIMER_ID_REG                       (_OMAP_TIMER_ID_OFFSET \
-                                                        | (WP_NONE << WPSHIFT))
-#define OMAP_TIMER_OCP_CFG_REG                  (_OMAP_TIMER_OCP_CFG_OFFSET \
-                                                        | (WP_NONE << WPSHIFT))
-#define OMAP_TIMER_SYS_STAT_REG                 (_OMAP_TIMER_SYS_STAT_OFFSET \
-                                                        | (WP_NONE << WPSHIFT))
-#define OMAP_TIMER_STAT_REG                     (_OMAP_TIMER_STAT_OFFSET \
-                                                        | (WP_NONE << WPSHIFT))
-#define OMAP_TIMER_INT_EN_REG                   (_OMAP_TIMER_INT_EN_OFFSET \
-                                                        | (WP_NONE << WPSHIFT))
 #define OMAP_TIMER_WAKEUP_EN_REG                (_OMAP_TIMER_WAKEUP_EN_OFFSET \
                                                        | (WP_NONE << WPSHIFT))
@@ -209,49 +257,88 @@ int omap_dm_timers_active(void);
 struct omap_dm_timer {
        unsigned long phys_base;
+        int id;
        int irq;
-#ifdef CONFIG_ARCH_OMAP2PLUS
        struct clk *iclk, *fclk;
-#endif
-        void __iomem *io_base;
+        void __iomem    *io_base;
+        void __iomem    *sys_stat;      /* TISTAT timer status */
+        void __iomem    *irq_stat;      /* TISR/IRQSTATUS interrupt status */
+        void __iomem    *irq_ena;       /* irq enable */
+        void __iomem    *irq_dis;       /* irq disable, only on v2 ip */
+        void __iomem    *pend;          /* write pending */
+        void __iomem    *func_base;     /* function register base */
        unsigned long rate;
        unsigned reserved:1;
-        unsigned enabled:1;
        unsigned posted:1;
+        struct timer_regs context;
+        bool loses_context;
+        int ctx_loss_count;
+        int revision;
+        struct platform_device *pdev;
+        struct list_head node;
+        u32 (*get_context_loss_count)(struct device *dev);
 };
-extern u32 sys_timer_reserved;
+int omap_dm_timer_prepare(struct omap_dm_timer *timer);
-void omap_dm_timer_prepare(struct omap_dm_timer *timer);
-static inline u32 __omap_dm_timer_read(void __iomem *base, u32 reg,
+static inline u32 __omap_dm_timer_read(struct omap_dm_timer *timer, u32 reg,
                                                int posted)
 {
        if (posted)
-                while (__raw_readl(base + (OMAP_TIMER_WRITE_PEND_REG & 0xff))
+                while (__raw_readl(timer->pend) & (reg >> WPSHIFT))
-                                & (reg >> WPSHIFT))
                        cpu_relax();
-        return __raw_readl(base + (reg & 0xff));
+        return __raw_readl(timer->func_base + (reg & 0xff));
 }
-static inline void __omap_dm_timer_write(void __iomem *base, u32 reg, u32 val,
+static inline void __omap_dm_timer_write(struct omap_dm_timer *timer,
-                                                int posted)
+                                        u32 reg, u32 val, int posted)
 {
        if (posted)
-                while (__raw_readl(base + (OMAP_TIMER_WRITE_PEND_REG & 0xff))
+                while (__raw_readl(timer->pend) & (reg >> WPSHIFT))
-                                & (reg >> WPSHIFT))
                        cpu_relax();
-        __raw_writel(val, base + (reg & 0xff));
+        __raw_writel(val, timer->func_base + (reg & 0xff));
+}
+static inline void __omap_dm_timer_init_regs(struct omap_dm_timer *timer)
+{
+        u32 tidr;
+        /* Assume v1 ip if bits [31:16] are zero */
+        tidr = __raw_readl(timer->io_base);
+        if (!(tidr >> 16)) {
+                timer->revision = 1;
+                timer->sys_stat = timer->io_base +
+                                OMAP_TIMER_V1_SYS_STAT_OFFSET;
+                timer->irq_stat = timer->io_base + OMAP_TIMER_V1_STAT_OFFSET;
+                timer->irq_ena = timer->io_base + OMAP_TIMER_V1_INT_EN_OFFSET;
+                timer->irq_dis = 0;
+                timer->pend = timer->io_base + _OMAP_TIMER_WRITE_PEND_OFFSET;
+                timer->func_base = timer->io_base;
+        } else {
+                timer->revision = 2;
+                timer->sys_stat = 0;
+                timer->irq_stat = timer->io_base + OMAP_TIMER_V2_IRQSTATUS;
+                timer->irq_ena = timer->io_base + OMAP_TIMER_V2_IRQENABLE_SET;
+                timer->irq_dis = timer->io_base + OMAP_TIMER_V2_IRQENABLE_CLR;
+                timer->pend = timer->io_base +
+                        _OMAP_TIMER_WRITE_PEND_OFFSET +
+                                OMAP_TIMER_V2_FUNC_OFFSET;
+                timer->func_base = timer->io_base + OMAP_TIMER_V2_FUNC_OFFSET;
+        }
 }
 /* Assumes the source clock has been set by caller */
-static inline void __omap_dm_timer_reset(void __iomem *base, int autoidle,
+static inline void __omap_dm_timer_reset(struct omap_dm_timer *timer,
-                                                int wakeup)
+                                        int autoidle, int wakeup)
 {
        u32 l;
-        l = __omap_dm_timer_read(base, OMAP_TIMER_OCP_CFG_REG, 0);
+        l = __raw_readl(timer->io_base + OMAP_TIMER_OCP_CFG_OFFSET);
        l |= 0x02 << 3;  /* Set to smart-idle mode */
        l |= 0x2 << 8;   /* Set clock activity to perserve f-clock on idle */
@@ -261,10 +348,10 @@ static inline void __omap_dm_timer_reset(void __iomem *base, int autoidle,
        if (wakeup)
                l |= 1 << 2;
-        __omap_dm_timer_write(base, OMAP_TIMER_OCP_CFG_REG, l, 0);
+        __raw_writel(l, timer->io_base + OMAP_TIMER_OCP_CFG_OFFSET);
        /* Match hardware reset default of posted mode */
-        __omap_dm_timer_write(base, OMAP_TIMER_IF_CTRL_REG,
+        __omap_dm_timer_write(timer, OMAP_TIMER_IF_CTRL_REG,
                                        OMAP_TIMER_CTRL_POSTED, 0);
 }
@@ -286,18 +373,18 @@ static inline int __omap_dm_timer_set_source(struct clk *timer_fck,
        return ret;
 }
-static inline void __omap_dm_timer_stop(void __iomem *base, int posted,
+static inline void __omap_dm_timer_stop(struct omap_dm_timer *timer,
-                                                unsigned long rate)
+                                        int posted, unsigned long rate)
 {
        u32 l;
-        l = __omap_dm_timer_read(base, OMAP_TIMER_CTRL_REG, posted);
+        l = __omap_dm_timer_read(timer, OMAP_TIMER_CTRL_REG, posted);
        if (l & OMAP_TIMER_CTRL_ST) {
                l &= ~0x1;
-                __omap_dm_timer_write(base, OMAP_TIMER_CTRL_REG, l, posted);
+                __omap_dm_timer_write(timer, OMAP_TIMER_CTRL_REG, l, posted);
 #ifdef CONFIG_ARCH_OMAP2PLUS
                /* Readback to make sure write has completed */
-                __omap_dm_timer_read(base, OMAP_TIMER_CTRL_REG, posted);
+                __omap_dm_timer_read(timer, OMAP_TIMER_CTRL_REG, posted);
                /*
                 * Wait for functional clock period x 3.5 to make sure that
                 * timer is stopped
@@ -307,34 +394,34 @@ static inline void __omap_dm_timer_stop(void __iomem *base, int posted,
        }
        /* Ack possibly pending interrupt */
-        __omap_dm_timer_write(base, OMAP_TIMER_STAT_REG,
+        __raw_writel(OMAP_TIMER_INT_OVERFLOW, timer->irq_stat);
-                                        OMAP_TIMER_INT_OVERFLOW, 0);
 }
-static inline void __omap_dm_timer_load_start(void __iomem *base, u32 ctrl,
+static inline void __omap_dm_timer_load_start(struct omap_dm_timer *timer,
-                                                unsigned int load, int posted)
+                                                u32 ctrl, unsigned int load,
+                                                int posted)
 {
-        __omap_dm_timer_write(base, OMAP_TIMER_COUNTER_REG, load, posted);
+        __omap_dm_timer_write(timer, OMAP_TIMER_COUNTER_REG, load, posted);
-        __omap_dm_timer_write(base, OMAP_TIMER_CTRL_REG, ctrl, posted);
+        __omap_dm_timer_write(timer, OMAP_TIMER_CTRL_REG, ctrl, posted);
 }
-static inline void __omap_dm_timer_int_enable(void __iomem *base,
+static inline void __omap_dm_timer_int_enable(struct omap_dm_timer *timer,
                                                unsigned int value)
 {
-        __omap_dm_timer_write(base, OMAP_TIMER_INT_EN_REG, value, 0);
+        __raw_writel(value, timer->irq_ena);
-        __omap_dm_timer_write(base, OMAP_TIMER_WAKEUP_EN_REG, value, 0);
+        __omap_dm_timer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, value, 0);
 }
-static inline unsigned int __omap_dm_timer_read_counter(void __iomem *base,
+static inline unsigned int
-                                                        int posted)
+__omap_dm_timer_read_counter(struct omap_dm_timer *timer, int posted)
 {
-        return __omap_dm_timer_read(base, OMAP_TIMER_COUNTER_REG, posted);
+        return __omap_dm_timer_read(timer, OMAP_TIMER_COUNTER_REG, posted);
 }
-static inline void __omap_dm_timer_write_status(void __iomem *base,
+static inline void __omap_dm_timer_write_status(struct omap_dm_timer *timer,
                                                unsigned int value)
 {
-        __omap_dm_timer_write(base, OMAP_TIMER_STAT_REG, value, 0);
+        __raw_writel(value, timer->irq_stat);
 }
 #endif /* __ASM_ARCH_DMTIMER_H */
diff --git a/arch/arm/plat-omap/include/plat/io.h b/arch/arm/plat-omap/include/plat/io.h
index d72ec85c97e6..75311fc9c018 100644
--- a/arch/arm/plat-omap/include/plat/io.h
+++ b/arch/arm/plat-omap/include/plat/io.h
@@ -300,7 +300,7 @@ static inline void omap44xx_map_common_io(void)
 #endif
 extern void omap2_init_common_infrastructure(void);
-extern void omap2_init_common_devices(struct omap_sdrc_params *sdrc_cs0,
+extern void omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
                                      struct omap_sdrc_params *sdrc_cs1);
 #define __arch_ioremap  omap_ioremap
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index 0e329ca88a70..9115aedd2124 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -496,7 +496,6 @@ struct omap_hwmod_class {
 * @_state: internal-use hwmod state
 * @_postsetup_state: internal-use state to leave the hwmod in after _setup()
 * @flags: hwmod flags (documented below)
- * @omap_chip: OMAP chips this hwmod is present on
 * @_lock: spinlock serializing operations on this hwmod
 * @node: list node for hwmod list (internal use)
 *
@@ -545,7 +544,6 @@ struct omap_hwmod {
        u8                              _int_flags;
        u8                              _state;
        u8                              _postsetup_state;
-        const struct omap_chip_id       omap_chip;
 };
 int omap_hwmod_register(struct omap_hwmod **ohs);
diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
index 9a6a53854911..02609eee0562 100644
--- a/arch/arm/plat-omap/omap_device.c
+++ b/arch/arm/plat-omap/omap_device.c
@@ -615,6 +615,9 @@ static int _od_resume_noirq(struct device *dev)
        return pm_generic_resume_noirq(dev);
 }
+#else
+#define _od_suspend_noirq NULL
+#define _od_resume_noirq NULL
 #endif
 static struct dev_pm_domain omap_device_pm_domain = {
diff --git a/arch/arm/plat-s5p/clock.c b/arch/arm/plat-s5p/clock.c
index 02af235298e2..5f84a3f13ef9 100644
--- a/arch/arm/plat-s5p/clock.c
+++ b/arch/arm/plat-s5p/clock.c
@@ -192,7 +192,7 @@ unsigned long s5p_spdif_get_rate(struct clk *clk)
        if (IS_ERR(pclk))
                return -EINVAL;
-        rate = pclk->ops->get_rate(clk);
+        rate = pclk->ops->get_rate(pclk);
        clk_put(pclk);
        return rate;
diff --git a/arch/arm/plat-s5p/irq-gpioint.c b/arch/arm/plat-s5p/irq-gpioint.c
index 327ab9f662e8..f71078ef6bb5 100644
--- a/arch/arm/plat-s5p/irq-gpioint.c
+++ b/arch/arm/plat-s5p/irq-gpioint.c
@@ -23,6 +23,8 @@
 #include <plat/gpio-core.h>
 #include <plat/gpio-cfg.h>
+#include <asm/mach/irq.h>
 #define GPIO_BASE(chip)         (((unsigned long)(chip)->base) & 0xFFFFF000u)
 #define CON_OFFSET              0x700
@@ -81,6 +83,9 @@ static void s5p_gpioint_handler(unsigned int irq, struct irq_desc *desc)
        int group, pend_offset, mask_offset;
        unsigned int pend, mask;
+        struct irq_chip *chip = irq_get_chip(irq);
+        chained_irq_enter(chip, desc);
        for (group = 0; group < bank->nr_groups; group++) {
                struct s3c_gpio_chip *chip = bank->chips[group];
                if (!chip)
@@ -102,6 +107,7 @@ static void s5p_gpioint_handler(unsigned int irq, struct irq_desc *desc)
                        pend &= ~BIT(offset);
                }
        }
+        chained_irq_exit(chip, desc);
 }
 static __init int s5p_gpioint_add(struct s3c_gpio_chip *chip)
diff --git a/arch/arm/plat-samsung/clock.c b/arch/arm/plat-samsung/clock.c
index 302c42670bd1..3b4451979d1b 100644
--- a/arch/arm/plat-samsung/clock.c
+++ b/arch/arm/plat-samsung/clock.c
@@ -64,6 +64,17 @@ static LIST_HEAD(clocks);
 */
 DEFINE_SPINLOCK(clocks_lock);
+/* Global watchdog clock used by arch_wtd_reset() callback */
+struct clk *s3c2410_wdtclk;
+static int __init s3c_wdt_reset_init(void)
+{
+        s3c2410_wdtclk = clk_get(NULL, "watchdog");
+        if (IS_ERR(s3c2410_wdtclk))
+                printk(KERN_WARNING "%s: warning: cannot get watchdog clock\n", __func__);
+        return 0;
+}
+arch_initcall(s3c_wdt_reset_init);
 /* enable and disable calls for use with the clk struct */
 static int clk_null_enable(struct clk *clk, int enable)
diff --git a/arch/arm/plat-samsung/include/plat/backlight.h b/arch/arm/plat-samsung/include/plat/backlight.h
index 51d8da846a62..ad530c78fe8c 100644
--- a/arch/arm/plat-samsung/include/plat/backlight.h
+++ b/arch/arm/plat-samsung/include/plat/backlight.h
@@ -20,7 +20,7 @@ struct samsung_bl_gpio_info {
        int func;
 };
-extern void samsung_bl_set(struct samsung_bl_gpio_info *gpio_info,
+extern void __init samsung_bl_set(struct samsung_bl_gpio_info *gpio_info,
        struct platform_pwm_backlight_data *bl_data);
 #endif /* __ASM_PLAT_BACKLIGHT_H */
diff --git a/arch/arm/plat-samsung/include/plat/clock.h b/arch/arm/plat-samsung/include/plat/clock.h
index 87d5b38a86fb..73c66d4d10fa 100644
--- a/arch/arm/plat-samsung/include/plat/clock.h
+++ b/arch/arm/plat-samsung/include/plat/clock.h
@@ -9,6 +9,9 @@
 * published by the Free Software Foundation.
 */
+#ifndef __ASM_PLAT_CLOCK_H
+#define __ASM_PLAT_CLOCK_H __FILE__
 #include <linux/spinlock.h>
 #include <linux/clkdev.h>
@@ -121,3 +124,8 @@ extern int s3c64xx_sclk_ctrl(struct clk *clk, int enable);
 extern void s3c_pwmclk_init(void);
+/* Global watchdog clock used by arch_wtd_reset() callback */
+extern struct clk *s3c2410_wdtclk;
+#endif /* __ASM_PLAT_CLOCK_H */
diff --git a/arch/arm/plat-samsung/include/plat/watchdog-reset.h b/arch/arm/plat-samsung/include/plat/watchdog-reset.h
index 54b762acb5a0..40dbb2b0ae22 100644
--- a/arch/arm/plat-samsung/include/plat/watchdog-reset.h
+++ b/arch/arm/plat-samsung/include/plat/watchdog-reset.h
@@ -10,6 +10,7 @@
 * published by the Free Software Foundation.
 */
+#include <plat/clock.h>
 #include <plat/regs-watchdog.h>
 #include <mach/map.h>
@@ -19,17 +20,12 @@
 static inline void arch_wdt_reset(void)
 {
-        struct clk *wdtclk;
        printk("arch_reset: attempting watchdog reset\n");
        __raw_writel(0, S3C2410_WTCON);   /* disable watchdog, to be safe  */
-        wdtclk = clk_get(NULL, "watchdog");
+        if (s3c2410_wdtclk)
-        if (!IS_ERR(wdtclk)) {
+                clk_enable(s3c2410_wdtclk);
-                clk_enable(wdtclk);
-        } else
-                printk(KERN_WARNING "%s: warning: cannot get watchdog clock\n", __func__);
        /* put initial values into count and data */
        __raw_writel(0x80, S3C2410_WTCNT);
diff --git a/arch/arm/plat-samsung/irq-vic-timer.c b/arch/arm/plat-samsung/irq-vic-timer.c
index f714d060370d..51583cd30164 100644
--- a/arch/arm/plat-samsung/irq-vic-timer.c
+++ b/arch/arm/plat-samsung/irq-vic-timer.c
@@ -22,9 +22,14 @@
 #include <plat/irq-vic-timer.h>
 #include <plat/regs-timer.h>
+#include <asm/mach/irq.h>
 static void s3c_irq_demux_vic_timer(unsigned int irq, struct irq_desc *desc)
 {
+        struct irq_chip *chip = irq_get_chip(irq);
+        chained_irq_enter(chip, desc);
        generic_handle_irq((int)desc->irq_data.handler_data);
+        chained_irq_exit(chip, desc);
 }
 /* We assume the IRQ_TIMER0..IRQ_TIMER4 range is continuous. */
diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types
index fff68d0d521b..62cc8f981171 100644
--- a/arch/arm/tools/mach-types
+++ b/arch/arm/tools/mach-types
@@ -351,7 +351,7 @@ centro			MACH_CENTRO		CENTRO			1944
 nokia_rx51              MACH_NOKIA_RX51         NOKIA_RX51              1955
 omap_zoom2              MACH_OMAP_ZOOM2         OMAP_ZOOM2              1967
 cpuat9260               MACH_CPUAT9260          CPUAT9260               1973
-eukrea_cpuimx27         MACH_CPUIMX27           CPUIMX27                1975
+eukrea_cpuimx27         MACH_EUKREA_CPUIMX27    EUKREA_CPUIMX27         1975
 acs5k                   MACH_ACS5K              ACS5K                   1982
 snapper_9260            MACH_SNAPPER_9260       SNAPPER_9260            1987
 dsm320                  MACH_DSM320             DSM320                  1988
@@ -476,8 +476,8 @@ cns3420vb		MACH_CNS3420VB		CNS3420VB		2776
 omap4_panda             MACH_OMAP4_PANDA        OMAP4_PANDA             2791
 ti8168evm               MACH_TI8168EVM          TI8168EVM               2800
 teton_bga               MACH_TETON_BGA          TETON_BGA               2816
-eukrea_cpuimx25sd       MACH_EUKREA_CPUIMX25    EUKREA_CPUIMX25         2820
+eukrea_cpuimx25sd       MACH_EUKREA_CPUIMX25SD  EUKREA_CPUIMX25SD       2820
-eukrea_cpuimx35sd       MACH_EUKREA_CPUIMX35    EUKREA_CPUIMX35         2821
+eukrea_cpuimx35sd       MACH_EUKREA_CPUIMX35SD  EUKREA_CPUIMX35SD       2821
 eukrea_cpuimx51sd       MACH_EUKREA_CPUIMX51SD  EUKREA_CPUIMX51SD       2822
 eukrea_cpuimx51         MACH_EUKREA_CPUIMX51    EUKREA_CPUIMX51         2823
 smdkc210                MACH_SMDKC210           SMDKC210                2838