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-rw-r--r--arch/arm/mach-s5p6440/include/mach/irqs.h111
-rw-r--r--arch/arm/mach-s5p6440/include/mach/regs-irq.h19
-rw-r--r--arch/arm/plat-s5p/include/plat/irqs.h83
-rw-r--r--arch/arm/plat-s5p/irq.c73
4 files changed, 286 insertions, 0 deletions
diff --git a/arch/arm/mach-s5p6440/include/mach/irqs.h b/arch/arm/mach-s5p6440/include/mach/irqs.h
new file mode 100644
index 000000000000..a4b9b40d18f2
--- /dev/null
+++ b/arch/arm/mach-s5p6440/include/mach/irqs.h
@@ -0,0 +1,111 @@
1/* linux/arch/arm/mach-s5p6440/include/mach/irqs.h
2 *
3 * Copyright 2009 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5P6440 - IRQ definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_S5P_IRQS_H
14#define __ASM_ARCH_S5P_IRQS_H __FILE__
15
16#include <plat/irqs.h>
17
18/* VIC0 */
19
20#define IRQ_EINT0_3 S5P_IRQ_VIC0(0)
21#define IRQ_EINT4_11 S5P_IRQ_VIC0(1)
22#define IRQ_RTC_TIC S5P_IRQ_VIC0(2)
23#define IRQ_IIC1 S5P_IRQ_VIC0(5)
24#define IRQ_I2SV40 S5P_IRQ_VIC0(6)
25#define IRQ_GPS S5P_IRQ_VIC0(7)
26#define IRQ_POST0 S5P_IRQ_VIC0(9)
27#define IRQ_2D S5P_IRQ_VIC0(11)
28#define IRQ_TIMER0_VIC S5P_IRQ_VIC0(23)
29#define IRQ_TIMER1_VIC S5P_IRQ_VIC0(24)
30#define IRQ_TIMER2_VIC S5P_IRQ_VIC0(25)
31#define IRQ_WDT S5P_IRQ_VIC0(26)
32#define IRQ_TIMER3_VIC S5P_IRQ_VIC0(27)
33#define IRQ_TIMER4_VIC S5P_IRQ_VIC0(28)
34#define IRQ_DISPCON0 S5P_IRQ_VIC0(29)
35#define IRQ_DISPCON1 S5P_IRQ_VIC0(30)
36#define IRQ_DISPCON2 S5P_IRQ_VIC0(31)
37
38/* VIC1 */
39
40#define IRQ_EINT12_15 S5P_IRQ_VIC1(0)
41#define IRQ_PCM0 S5P_IRQ_VIC1(2)
42#define IRQ_UART0 S5P_IRQ_VIC1(5)
43#define IRQ_UART1 S5P_IRQ_VIC1(6)
44#define IRQ_UART2 S5P_IRQ_VIC1(7)
45#define IRQ_UART3 S5P_IRQ_VIC1(8)
46#define IRQ_DMA0 S5P_IRQ_VIC1(9)
47#define IRQ_NFC S5P_IRQ_VIC1(13)
48#define IRQ_SPI0 S5P_IRQ_VIC1(16)
49#define IRQ_SPI1 S5P_IRQ_VIC1(17)
50#define IRQ_IIC S5P_IRQ_VIC1(18)
51#define IRQ_DISPCON3 S5P_IRQ_VIC1(19)
52#define IRQ_FIMGVG S5P_IRQ_VIC1(20)
53#define IRQ_EINT_GROUPS S5P_IRQ_VIC1(21)
54#define IRQ_PMUIRQ S5P_IRQ_VIC1(23)
55#define IRQ_HSMMC0 S5P_IRQ_VIC1(24)
56#define IRQ_HSMMC1 S5P_IRQ_VIC1(25)
57#define IRQ_HSMMC2 IRQ_SPI1 /* shared with SPI1 */
58#define IRQ_OTG S5P_IRQ_VIC1(26)
59#define IRQ_DSI S5P_IRQ_VIC1(27)
60#define IRQ_RTC_ALARM S5P_IRQ_VIC1(28)
61#define IRQ_TSI S5P_IRQ_VIC1(29)
62#define IRQ_PENDN S5P_IRQ_VIC1(30)
63#define IRQ_TC IRQ_PENDN
64#define IRQ_ADC S5P_IRQ_VIC1(31)
65
66/*
67 * Since the IRQ_EINT(x) are a linear mapping on s5p6440 we just defined
68 * them as an IRQ_EINT(x) macro from S5P_IRQ_EINT_BASE which we place
69 * after the pair of VICs.
70 */
71
72#define S5P_IRQ_EINT_BASE (S5P_IRQ_VIC1(31) + 6)
73
74#define S5P_EINT(x) ((x) + S5P_IRQ_EINT_BASE)
75#define IRQ_EINT(x) S5P_EINT(x)
76
77/*
78 * Next the external interrupt groups. These are similar to the IRQ_EINT(x)
79 * that they are sourced from the GPIO pins but with a different scheme for
80 * priority and source indication.
81 *
82 * The IRQ_EINT(x) can be thought of as 'group 0' of the available GPIO
83 * interrupts, but for historical reasons they are kept apart from these
84 * next interrupts.
85 *
86 * Use IRQ_EINT_GROUP(group, offset) to get the number for use in the
87 * machine specific support files.
88 */
89
90/* Actually, #6 and #7 are missing in the EINT_GROUP1 */
91#define IRQ_EINT_GROUP1_NR (15)
92#define IRQ_EINT_GROUP2_NR (8)
93#define IRQ_EINT_GROUP5_NR (7)
94#define IRQ_EINT_GROUP6_NR (10)
95/* Actually, #0, #1 and #2 are missing in the EINT_GROUP8 */
96#define IRQ_EINT_GROUP8_NR (11)
97
98#define IRQ_EINT_GROUP_BASE S5P_EINT(16)
99#define IRQ_EINT_GROUP1_BASE (IRQ_EINT_GROUP_BASE + 0)
100#define IRQ_EINT_GROUP2_BASE (IRQ_EINT_GROUP1_BASE + IRQ_EINT_GROUP1_NR)
101#define IRQ_EINT_GROUP5_BASE (IRQ_EINT_GROUP2_BASE + IRQ_EINT_GROUP2_NR)
102#define IRQ_EINT_GROUP6_BASE (IRQ_EINT_GROUP5_BASE + IRQ_EINT_GROUP5_NR)
103#define IRQ_EINT_GROUP8_BASE (IRQ_EINT_GROUP6_BASE + IRQ_EINT_GROUP6_NR)
104
105#define IRQ_EINT_GROUP(grp, x) (IRQ_EINT_GROUP##grp##_BASE + (x))
106
107/* Set the default NR_IRQS */
108
109#define NR_IRQS (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR + 1)
110
111#endif /* __ASM_ARCH_S5P_IRQS_H */
diff --git a/arch/arm/mach-s5p6440/include/mach/regs-irq.h b/arch/arm/mach-s5p6440/include/mach/regs-irq.h
new file mode 100644
index 000000000000..a961f4beeb0c
--- /dev/null
+++ b/arch/arm/mach-s5p6440/include/mach/regs-irq.h
@@ -0,0 +1,19 @@
1/* linux/arch/arm/mach-s5p6440/include/mach/regs-irq.h
2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5P6440 - IRQ register definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_REGS_IRQ_H
14#define __ASM_ARCH_REGS_IRQ_H __FILE__
15
16#include <asm/hardware/vic.h>
17#include <mach/map.h>
18
19#endif /* __ASM_ARCH_REGS_IRQ_H */
diff --git a/arch/arm/plat-s5p/include/plat/irqs.h b/arch/arm/plat-s5p/include/plat/irqs.h
new file mode 100644
index 000000000000..5d7937dddad2
--- /dev/null
+++ b/arch/arm/plat-s5p/include/plat/irqs.h
@@ -0,0 +1,83 @@
1/* linux/arch/arm/plat-s5p/include/plat/irqs.h
2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5P Common IRQ support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_PLAT_S5P_IRQS_H
14#define __ASM_PLAT_S5P_IRQS_H __FILE__
15
16/* we keep the first set of CPU IRQs out of the range of
17 * the ISA space, so that the PC104 has them to itself
18 * and we don't end up having to do horrible things to the
19 * standard ISA drivers....
20 *
21 * note, since we're using the VICs, our start must be a
22 * mulitple of 32 to allow the common code to work
23 */
24
25#define S5P_IRQ_OFFSET (32)
26
27#define S5P_IRQ(x) ((x) + S5P_IRQ_OFFSET)
28
29#define S5P_VIC0_BASE S5P_IRQ(0)
30#define S5P_VIC1_BASE S5P_IRQ(32)
31
32#define IRQ_VIC0_BASE S5P_VIC0_BASE
33#define IRQ_VIC1_BASE S5P_VIC1_BASE
34
35/* UART interrupts, each UART has 4 intterupts per channel so
36 * use the space between the ISA and S3C main interrupts. Note, these
37 * are not in the same order as the S3C24XX series! */
38
39#define IRQ_S5P_UART_BASE0 (16)
40#define IRQ_S5P_UART_BASE1 (20)
41#define IRQ_S5P_UART_BASE2 (24)
42#define IRQ_S5P_UART_BASE3 (28)
43
44#define UART_IRQ_RXD (0)
45#define UART_IRQ_ERR (1)
46#define UART_IRQ_TXD (2)
47
48#define IRQ_S5P_UART_RX0 (IRQ_S5P_UART_BASE0 + UART_IRQ_RXD)
49#define IRQ_S5P_UART_TX0 (IRQ_S5P_UART_BASE0 + UART_IRQ_TXD)
50#define IRQ_S5P_UART_ERR0 (IRQ_S5P_UART_BASE0 + UART_IRQ_ERR)
51
52#define IRQ_S5P_UART_RX1 (IRQ_S5P_UART_BASE1 + UART_IRQ_RXD)
53#define IRQ_S5P_UART_TX1 (IRQ_S5P_UART_BASE1 + UART_IRQ_TXD)
54#define IRQ_S5P_UART_ERR1 (IRQ_S5P_UART_BASE1 + UART_IRQ_ERR)
55
56#define IRQ_S5P_UART_RX2 (IRQ_S5P_UART_BASE2 + UART_IRQ_RXD)
57#define IRQ_S5P_UART_TX2 (IRQ_S5P_UART_BASE2 + UART_IRQ_TXD)
58#define IRQ_S5P_UART_ERR2 (IRQ_S5P_UART_BASE2 + UART_IRQ_ERR)
59
60#define IRQ_S5P_UART_RX3 (IRQ_S5P_UART_BASE3 + UART_IRQ_RXD)
61#define IRQ_S5P_UART_TX3 (IRQ_S5P_UART_BASE3 + UART_IRQ_TXD)
62#define IRQ_S5P_UART_ERR3 (IRQ_S5P_UART_BASE3 + UART_IRQ_ERR)
63
64/* S3C compatibilty defines */
65#define IRQ_S3CUART_RX0 IRQ_S5P_UART_RX0
66#define IRQ_S3CUART_RX1 IRQ_S5P_UART_RX1
67#define IRQ_S3CUART_RX2 IRQ_S5P_UART_RX2
68#define IRQ_S3CUART_RX3 IRQ_S5P_UART_RX3
69
70/* VIC based IRQs */
71
72#define S5P_IRQ_VIC0(x) (S5P_VIC0_BASE + (x))
73#define S5P_IRQ_VIC1(x) (S5P_VIC1_BASE + (x))
74
75#define S5P_TIMER_IRQ(x) S5P_IRQ(64 + (x))
76
77#define IRQ_TIMER0 S5P_TIMER_IRQ(0)
78#define IRQ_TIMER1 S5P_TIMER_IRQ(1)
79#define IRQ_TIMER2 S5P_TIMER_IRQ(2)
80#define IRQ_TIMER3 S5P_TIMER_IRQ(3)
81#define IRQ_TIMER4 S5P_TIMER_IRQ(4)
82
83#endif /* __ASM_PLAT_S5P_IRQS_H */
diff --git a/arch/arm/plat-s5p/irq.c b/arch/arm/plat-s5p/irq.c
new file mode 100644
index 000000000000..eada40d0847d
--- /dev/null
+++ b/arch/arm/plat-s5p/irq.c
@@ -0,0 +1,73 @@
1/* arch/arm/plat-s5p/irq.c
2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5P - Interrupt handling
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/interrupt.h>
15#include <linux/irq.h>
16#include <linux/io.h>
17
18#include <asm/hardware/vic.h>
19
20#include <linux/serial_core.h>
21#include <mach/map.h>
22#include <plat/regs-timer.h>
23#include <plat/regs-serial.h>
24#include <plat/cpu.h>
25#include <plat/irq-vic-timer.h>
26#include <plat/irq-uart.h>
27
28#define VIC_VAADDR(no) (S5P_VA_VIC0 + ((no)*0x10000))
29#define VIC_BASE(no) (S5P_VIC0_BASE + ((no)*32))
30
31/*
32 * Note, we make use of the fact that the parent IRQs, IRQ_UART[0..3]
33 * are consecutive when looking up the interrupt in the demux routines.
34 */
35static struct s3c_uart_irq uart_irqs[] = {
36 [0] = {
37 .regs = S5P_VA_UART0,
38 .base_irq = IRQ_S5P_UART_BASE0,
39 .parent_irq = IRQ_UART0,
40 },
41 [1] = {
42 .regs = S5P_VA_UART1,
43 .base_irq = IRQ_S5P_UART_BASE1,
44 .parent_irq = IRQ_UART1,
45 },
46 [2] = {
47 .regs = S5P_VA_UART2,
48 .base_irq = IRQ_S5P_UART_BASE2,
49 .parent_irq = IRQ_UART2,
50 },
51 [3] = {
52 .regs = S5P_VA_UART3,
53 .base_irq = IRQ_S5P_UART_BASE3,
54 .parent_irq = IRQ_UART3,
55 },
56};
57
58void __init s5p_init_irq(u32 *vic, u32 num_vic)
59{
60 int irq;
61
62 /* initialize the VICs */
63 for (irq = 0; irq < num_vic; irq++)
64 vic_init(VIC_VAADDR(irq), VIC_BASE(irq), vic[irq], 0);
65
66 s3c_init_vic_timer_irq(IRQ_TIMER0_VIC, IRQ_TIMER0);
67 s3c_init_vic_timer_irq(IRQ_TIMER1_VIC, IRQ_TIMER1);
68 s3c_init_vic_timer_irq(IRQ_TIMER2_VIC, IRQ_TIMER2);
69 s3c_init_vic_timer_irq(IRQ_TIMER3_VIC, IRQ_TIMER3);
70 s3c_init_vic_timer_irq(IRQ_TIMER4_VIC, IRQ_TIMER4);
71
72 s3c_init_uart_irqs(uart_irqs, ARRAY_SIZE(uart_irqs));
73}
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-30 11:26:25 -0400