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-rw-r--r--arch/arm/mach-exynos/common.c2
-rw-r--r--arch/arm/mach-exynos/cpuidle.c3
-rw-r--r--arch/arm/mach-exynos/hotplug.c45
-rw-r--r--arch/arm/mach-exynos/pm.c7
-rw-r--r--arch/arm/mach-omap1/board-h2.c2
-rw-r--r--arch/arm/mach-omap1/board-h3.c2
-rw-r--r--arch/arm/mach-omap1/board-palmte.c2
-rw-r--r--arch/arm/mach-omap1/board-palmtt.c2
-rw-r--r--arch/arm/mach-omap1/board-palmz71.c2
-rw-r--r--arch/arm/mach-omap1/board-sx1.c2
-rw-r--r--arch/arm/mach-omap1/dma.c2
-rw-r--r--arch/arm/mach-omap1/io.c2
-rw-r--r--arch/arm/mach-omap1/lcd_dma.c2
-rw-r--r--arch/arm/mach-omap1/mcbsp.c2
-rw-r--r--arch/arm/mach-omap1/pm.c2
-rw-r--r--arch/arm/mach-omap2/Kconfig5
-rw-r--r--arch/arm/mach-omap2/Makefile10
-rw-r--r--arch/arm/mach-omap2/board-3430sdp.c2
-rw-r--r--arch/arm/mach-omap2/board-h4.c2
-rw-r--r--arch/arm/mach-omap2/board-rx51-peripherals.c2
-rw-r--r--arch/arm/mach-omap2/board-rx51.c2
-rw-r--r--arch/arm/mach-omap2/cclock2420_data.c1950
-rw-r--r--arch/arm/mach-omap2/cclock2430_data.c2065
-rw-r--r--arch/arm/mach-omap2/cclock33xx_data.c961
-rw-r--r--arch/arm/mach-omap2/cclock3xxx_data.c3595
-rw-r--r--arch/arm/mach-omap2/cclock44xx_data.c1987
-rw-r--r--arch/arm/mach-omap2/clkt2xxx_apll.c62
-rw-r--r--arch/arm/mach-omap2/clkt2xxx_dpll.c8
-rw-r--r--arch/arm/mach-omap2/clkt2xxx_dpllcore.c13
-rw-r--r--arch/arm/mach-omap2/clkt2xxx_osc.c13
-rw-r--r--arch/arm/mach-omap2/clkt2xxx_sys.c7
-rw-r--r--arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c9
-rw-r--r--arch/arm/mach-omap2/clkt34xx_dpll3m2.c8
-rw-r--r--arch/arm/mach-omap2/clkt_clksel.c194
-rw-r--r--arch/arm/mach-omap2/clkt_dpll.c28
-rw-r--r--arch/arm/mach-omap2/clkt_iclk.c30
-rw-r--r--arch/arm/mach-omap2/clock.c910
-rw-r--r--arch/arm/mach-omap2/clock.h329
-rw-r--r--arch/arm/mach-omap2/clock2420_data.c1972
-rw-r--r--arch/arm/mach-omap2/clock2430.c8
-rw-r--r--arch/arm/mach-omap2/clock2430_data.c2071
-rw-r--r--arch/arm/mach-omap2/clock2xxx.c1
-rw-r--r--arch/arm/mach-omap2/clock2xxx.h41
-rw-r--r--arch/arm/mach-omap2/clock33xx_data.c1109
-rw-r--r--arch/arm/mach-omap2/clock34xx.c51
-rw-r--r--arch/arm/mach-omap2/clock3517.c24
-rw-r--r--arch/arm/mach-omap2/clock36xx.c22
-rw-r--r--arch/arm/mach-omap2/clock36xx.h2
-rw-r--r--arch/arm/mach-omap2/clock3xxx.c6
-rw-r--r--arch/arm/mach-omap2/clock3xxx.h6
-rw-r--r--arch/arm/mach-omap2/clock3xxx_data.c3613
-rw-r--r--arch/arm/mach-omap2/clock44xx_data.c3398
-rw-r--r--arch/arm/mach-omap2/clock_common_data.c22
-rw-r--r--arch/arm/mach-omap2/clockdomain.c89
-rw-r--r--arch/arm/mach-omap2/cm-regbits-24xx.h5
-rw-r--r--arch/arm/mach-omap2/cm-regbits-34xx.h31
-rw-r--r--arch/arm/mach-omap2/cm2xxx_3xxx.h1
-rw-r--r--arch/arm/mach-omap2/control.h1
-rw-r--r--arch/arm/mach-omap2/devices.c2
-rw-r--r--arch/arm/mach-omap2/dma.c2
-rw-r--r--arch/arm/mach-omap2/dpll3xxx.c183
-rw-r--r--arch/arm/mach-omap2/dpll44xx.c21
-rw-r--r--arch/arm/mach-omap2/io.c18
-rw-r--r--arch/arm/mach-omap2/mcbsp.c2
-rw-r--r--arch/arm/mach-omap2/omap_device.c87
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.c145
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.h12
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2420_data.c4
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2430_data.c4
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c3
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c2
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_3xxx_data.c2
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_44xx_data.c3
-rw-r--r--arch/arm/mach-omap2/omap_opp_data.h9
-rw-r--r--arch/arm/mach-omap2/omap_phy_internal.c32
-rw-r--r--arch/arm/mach-omap2/omap_twl.c73
-rw-r--r--arch/arm/mach-omap2/opp4xxx_data.c98
-rw-r--r--arch/arm/mach-omap2/pm.c32
-rw-r--r--arch/arm/mach-omap2/pm.h10
-rw-r--r--arch/arm/mach-omap2/pm24xx.c6
-rw-r--r--arch/arm/mach-omap2/pm34xx.c3
-rw-r--r--arch/arm/mach-omap2/pm44xx.c7
-rw-r--r--arch/arm/mach-omap2/prm-regbits-24xx.h2
-rw-r--r--arch/arm/mach-omap2/prm-regbits-34xx.h1
-rw-r--r--arch/arm/mach-omap2/prm.h11
-rw-r--r--arch/arm/mach-omap2/prm2xxx.c3
-rw-r--r--arch/arm/mach-omap2/prm2xxx.h3
-rw-r--r--arch/arm/mach-omap2/prm2xxx_3xxx.h1
-rw-r--r--arch/arm/mach-omap2/prm3xxx.c17
-rw-r--r--arch/arm/mach-omap2/prm3xxx.h1
-rw-r--r--arch/arm/mach-omap2/prm44xx.c49
-rw-r--r--arch/arm/mach-omap2/prm44xx.h1
-rw-r--r--arch/arm/mach-omap2/prm_common.c45
-rw-r--r--arch/arm/mach-omap2/scrm44xx.h2
-rw-r--r--arch/arm/mach-omap2/serial.c2
-rw-r--r--arch/arm/mach-omap2/sr_device.c13
-rw-r--r--arch/arm/mach-omap2/vc.c453
-rw-r--r--arch/arm/mach-omap2/vc.h8
-rw-r--r--arch/arm/mach-omap2/vc3xxx_data.c22
-rw-r--r--arch/arm/mach-omap2/vc44xx_data.c28
-rw-r--r--arch/arm/mach-omap2/voltage.h44
-rw-r--r--arch/arm/mach-omap2/voltagedomains3xxx_data.c5
-rw-r--r--arch/arm/mach-omap2/voltagedomains44xx_data.c25
-rw-r--r--arch/arm/mach-omap2/vp.c19
-rw-r--r--arch/arm/mach-omap2/vp.h7
-rw-r--r--arch/arm/mach-omap2/vp3xxx_data.c10
-rw-r--r--arch/arm/mach-omap2/vp44xx_data.c15
-rw-r--r--arch/arm/plat-omap/dma.c2
-rw-r--r--arch/arm/plat-omap/include/plat-omap/dma-omap.h377
-rw-r--r--arch/arm/plat-samsung/include/plat/pm.h2
110 files changed, 12599 insertions, 14073 deletions
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 3f257e76bfde..ddd4b72c6f9a 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -680,6 +680,8 @@ void __init exynos5_init_irq(void)
680 * uses GIC instead of VIC. 680 * uses GIC instead of VIC.
681 */ 681 */
682 s5p_init_irq(NULL, 0); 682 s5p_init_irq(NULL, 0);
683
684 gic_arch_extn.irq_set_wake = s3c_irq_wake;
683} 685}
684 686
685struct bus_type exynos_subsys = { 687struct bus_type exynos_subsys = {
diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index cff0595d0d35..8e4ec21ef2cf 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -116,7 +116,8 @@ static int exynos4_enter_core0_aftr(struct cpuidle_device *dev,
116 cpu_suspend(0, idle_finisher); 116 cpu_suspend(0, idle_finisher);
117 117
118#ifdef CONFIG_SMP 118#ifdef CONFIG_SMP
119 scu_enable(S5P_VA_SCU); 119 if (!soc_is_exynos5250())
120 scu_enable(S5P_VA_SCU);
120#endif 121#endif
121 cpu_pm_exit(); 122 cpu_pm_exit();
122 123
diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c
index f4d7dd20cdac..c3f825b27947 100644
--- a/arch/arm/mach-exynos/hotplug.c
+++ b/arch/arm/mach-exynos/hotplug.c
@@ -20,10 +20,11 @@
20#include <asm/smp_plat.h> 20#include <asm/smp_plat.h>
21 21
22#include <mach/regs-pmu.h> 22#include <mach/regs-pmu.h>
23#include <plat/cpu.h>
23 24
24#include "common.h" 25#include "common.h"
25 26
26static inline void cpu_enter_lowpower(void) 27static inline void cpu_enter_lowpower_a9(void)
27{ 28{
28 unsigned int v; 29 unsigned int v;
29 30
@@ -45,6 +46,35 @@ static inline void cpu_enter_lowpower(void)
45 : "cc"); 46 : "cc");
46} 47}
47 48
49static inline void cpu_enter_lowpower_a15(void)
50{
51 unsigned int v;
52
53 asm volatile(
54 " mrc p15, 0, %0, c1, c0, 0\n"
55 " bic %0, %0, %1\n"
56 " mcr p15, 0, %0, c1, c0, 0\n"
57 : "=&r" (v)
58 : "Ir" (CR_C)
59 : "cc");
60
61 flush_cache_louis();
62
63 asm volatile(
64 /*
65 * Turn off coherency
66 */
67 " mrc p15, 0, %0, c1, c0, 1\n"
68 " bic %0, %0, %1\n"
69 " mcr p15, 0, %0, c1, c0, 1\n"
70 : "=&r" (v)
71 : "Ir" (0x40)
72 : "cc");
73
74 isb();
75 dsb();
76}
77
48static inline void cpu_leave_lowpower(void) 78static inline void cpu_leave_lowpower(void)
49{ 79{
50 unsigned int v; 80 unsigned int v;
@@ -103,11 +133,20 @@ static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
103void __ref exynos_cpu_die(unsigned int cpu) 133void __ref exynos_cpu_die(unsigned int cpu)
104{ 134{
105 int spurious = 0; 135 int spurious = 0;
136 int primary_part = 0;
106 137
107 /* 138 /*
108 * we're ready for shutdown now, so do it 139 * we're ready for shutdown now, so do it.
140 * Exynos4 is A9 based while Exynos5 is A15; check the CPU part
141 * number by reading the Main ID register and then perform the
142 * appropriate sequence for entering low power.
109 */ 143 */
110 cpu_enter_lowpower(); 144 asm("mrc p15, 0, %0, c0, c0, 0" : "=r"(primary_part) : : "cc");
145 if ((primary_part & 0xfff0) == 0xc0f0)
146 cpu_enter_lowpower_a15();
147 else
148 cpu_enter_lowpower_a9();
149
111 platform_do_lowpower(cpu, &spurious); 150 platform_do_lowpower(cpu, &spurious);
112 151
113 /* 152 /*
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index c06c992943a1..8df6ec547f78 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -81,6 +81,9 @@ static int exynos_cpu_suspend(unsigned long arg)
81 outer_flush_all(); 81 outer_flush_all();
82#endif 82#endif
83 83
84 if (soc_is_exynos5250())
85 flush_cache_all();
86
84 /* issue the standby signal into the pm unit. */ 87 /* issue the standby signal into the pm unit. */
85 cpu_do_idle(); 88 cpu_do_idle();
86 89
@@ -312,6 +315,10 @@ static void exynos_pm_resume(void)
312 } 315 }
313 316
314early_wakeup: 317early_wakeup:
318
319 /* Clear SLEEP mode set in INFORM1 */
320 __raw_writel(0x0, S5P_INFORM1);
321
315 return; 322 return;
316} 323}
317 324
diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c
index 4953cf7a5123..2274bd677efc 100644
--- a/arch/arm/mach-omap1/board-h2.c
+++ b/arch/arm/mach-omap1/board-h2.c
@@ -39,7 +39,7 @@
39#include <asm/mach/map.h> 39#include <asm/mach/map.h>
40 40
41#include <mach/mux.h> 41#include <mach/mux.h>
42#include <plat-omap/dma-omap.h> 42#include <linux/omap-dma.h>
43#include <mach/tc.h> 43#include <mach/tc.h>
44#include <mach/irda.h> 44#include <mach/irda.h>
45#include <linux/platform_data/keypad-omap.h> 45#include <linux/platform_data/keypad-omap.h>
diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c
index 563ba167bb16..1051935f0aac 100644
--- a/arch/arm/mach-omap1/board-h3.c
+++ b/arch/arm/mach-omap1/board-h3.c
@@ -43,7 +43,7 @@
43#include <mach/mux.h> 43#include <mach/mux.h>
44#include <mach/tc.h> 44#include <mach/tc.h>
45#include <linux/platform_data/keypad-omap.h> 45#include <linux/platform_data/keypad-omap.h>
46#include <plat-omap/dma-omap.h> 46#include <linux/omap-dma.h>
47#include <mach/flash.h> 47#include <mach/flash.h>
48 48
49#include <mach/hardware.h> 49#include <mach/hardware.h>
diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c
index 584b6fab894b..c33dceb46607 100644
--- a/arch/arm/mach-omap1/board-palmte.c
+++ b/arch/arm/mach-omap1/board-palmte.c
@@ -37,7 +37,7 @@
37#include <mach/flash.h> 37#include <mach/flash.h>
38#include <mach/mux.h> 38#include <mach/mux.h>
39#include <mach/tc.h> 39#include <mach/tc.h>
40#include <plat-omap/dma-omap.h> 40#include <linux/omap-dma.h>
41#include <mach/irda.h> 41#include <mach/irda.h>
42#include <linux/platform_data/keypad-omap.h> 42#include <linux/platform_data/keypad-omap.h>
43 43
diff --git a/arch/arm/mach-omap1/board-palmtt.c b/arch/arm/mach-omap1/board-palmtt.c
index fbc986bfe69e..2948b0ee4be8 100644
--- a/arch/arm/mach-omap1/board-palmtt.c
+++ b/arch/arm/mach-omap1/board-palmtt.c
@@ -36,7 +36,7 @@
36 36
37#include <mach/flash.h> 37#include <mach/flash.h>
38#include <mach/mux.h> 38#include <mach/mux.h>
39#include <plat-omap/dma-omap.h> 39#include <linux/omap-dma.h>
40#include <mach/tc.h> 40#include <mach/tc.h>
41#include <mach/irda.h> 41#include <mach/irda.h>
42#include <linux/platform_data/keypad-omap.h> 42#include <linux/platform_data/keypad-omap.h>
diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c
index 60d917a93763..7a05895c0be3 100644
--- a/arch/arm/mach-omap1/board-palmz71.c
+++ b/arch/arm/mach-omap1/board-palmz71.c
@@ -38,7 +38,7 @@
38 38
39#include <mach/flash.h> 39#include <mach/flash.h>
40#include <mach/mux.h> 40#include <mach/mux.h>
41#include <plat-omap/dma-omap.h> 41#include <linux/omap-dma.h>
42#include <mach/tc.h> 42#include <mach/tc.h>
43#include <mach/irda.h> 43#include <mach/irda.h>
44#include <linux/platform_data/keypad-omap.h> 44#include <linux/platform_data/keypad-omap.h>
diff --git a/arch/arm/mach-omap1/board-sx1.c b/arch/arm/mach-omap1/board-sx1.c
index 1ebc7e08d6e5..20ed52ae1714 100644
--- a/arch/arm/mach-omap1/board-sx1.c
+++ b/arch/arm/mach-omap1/board-sx1.c
@@ -36,7 +36,7 @@
36 36
37#include <mach/flash.h> 37#include <mach/flash.h>
38#include <mach/mux.h> 38#include <mach/mux.h>
39#include <plat-omap/dma-omap.h> 39#include <linux/omap-dma.h>
40#include <mach/irda.h> 40#include <mach/irda.h>
41#include <mach/tc.h> 41#include <mach/tc.h>
42#include <mach/board-sx1.h> 42#include <mach/board-sx1.h>
diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c
index 978aed85d328..e190611e4b46 100644
--- a/arch/arm/mach-omap1/dma.c
+++ b/arch/arm/mach-omap1/dma.c
@@ -25,7 +25,7 @@
25#include <linux/device.h> 25#include <linux/device.h>
26#include <linux/io.h> 26#include <linux/io.h>
27 27
28#include <plat-omap/dma-omap.h> 28#include <linux/omap-dma.h>
29#include <mach/tc.h> 29#include <mach/tc.h>
30 30
31#include <mach/irqs.h> 31#include <mach/irqs.h>
diff --git a/arch/arm/mach-omap1/io.c b/arch/arm/mach-omap1/io.c
index 5a3b80617a11..499b8accb83d 100644
--- a/arch/arm/mach-omap1/io.c
+++ b/arch/arm/mach-omap1/io.c
@@ -18,7 +18,7 @@
18 18
19#include <mach/mux.h> 19#include <mach/mux.h>
20#include <mach/tc.h> 20#include <mach/tc.h>
21#include <plat-omap/dma-omap.h> 21#include <linux/omap-dma.h>
22 22
23#include "iomap.h" 23#include "iomap.h"
24#include "common.h" 24#include "common.h"
diff --git a/arch/arm/mach-omap1/lcd_dma.c b/arch/arm/mach-omap1/lcd_dma.c
index 7ed8c1857d56..77924be37d41 100644
--- a/arch/arm/mach-omap1/lcd_dma.c
+++ b/arch/arm/mach-omap1/lcd_dma.c
@@ -27,7 +27,7 @@
27#include <linux/interrupt.h> 27#include <linux/interrupt.h>
28#include <linux/io.h> 28#include <linux/io.h>
29 29
30#include <plat-omap/dma-omap.h> 30#include <linux/omap-dma.h>
31 31
32#include <mach/hardware.h> 32#include <mach/hardware.h>
33#include <mach/lcdc.h> 33#include <mach/lcdc.h>
diff --git a/arch/arm/mach-omap1/mcbsp.c b/arch/arm/mach-omap1/mcbsp.c
index c6d8fdf92e9c..b0d4723c9a90 100644
--- a/arch/arm/mach-omap1/mcbsp.c
+++ b/arch/arm/mach-omap1/mcbsp.c
@@ -19,7 +19,7 @@
19#include <linux/platform_device.h> 19#include <linux/platform_device.h>
20#include <linux/slab.h> 20#include <linux/slab.h>
21 21
22#include <plat-omap/dma-omap.h> 22#include <linux/omap-dma.h>
23#include <mach/mux.h> 23#include <mach/mux.h>
24#include "soc.h" 24#include "soc.h"
25#include <linux/platform_data/asoc-ti-mcbsp.h> 25#include <linux/platform_data/asoc-ti-mcbsp.h>
diff --git a/arch/arm/mach-omap1/pm.c b/arch/arm/mach-omap1/pm.c
index 66d663a6ef3a..7a7690ab6cb8 100644
--- a/arch/arm/mach-omap1/pm.c
+++ b/arch/arm/mach-omap1/pm.c
@@ -52,7 +52,7 @@
52 52
53#include <mach/tc.h> 53#include <mach/tc.h>
54#include <mach/mux.h> 54#include <mach/mux.h>
55#include <plat-omap/dma-omap.h> 55#include <linux/omap-dma.h>
56#include <plat/dmtimer.h> 56#include <plat/dmtimer.h>
57 57
58#include <mach/irqs.h> 58#include <mach/irqs.h>
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 2265e5826883..be0f62bf9037 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -34,6 +34,7 @@ config ARCH_OMAP2
34 select CPU_V6 34 select CPU_V6
35 select MULTI_IRQ_HANDLER 35 select MULTI_IRQ_HANDLER
36 select SOC_HAS_OMAP2_SDRC 36 select SOC_HAS_OMAP2_SDRC
37 select COMMON_CLK
37 38
38config ARCH_OMAP3 39config ARCH_OMAP3
39 bool "TI OMAP3" 40 bool "TI OMAP3"
@@ -47,6 +48,7 @@ config ARCH_OMAP3
47 select PM_OPP if PM 48 select PM_OPP if PM
48 select PM_RUNTIME if CPU_IDLE 49 select PM_RUNTIME if CPU_IDLE
49 select SOC_HAS_OMAP2_SDRC 50 select SOC_HAS_OMAP2_SDRC
51 select COMMON_CLK
50 select USB_ARCH_HAS_EHCI if USB_SUPPORT 52 select USB_ARCH_HAS_EHCI if USB_SUPPORT
51 53
52config ARCH_OMAP4 54config ARCH_OMAP4
@@ -68,6 +70,7 @@ config ARCH_OMAP4
68 select PM_OPP if PM 70 select PM_OPP if PM
69 select PM_RUNTIME if CPU_IDLE 71 select PM_RUNTIME if CPU_IDLE
70 select USB_ARCH_HAS_EHCI if USB_SUPPORT 72 select USB_ARCH_HAS_EHCI if USB_SUPPORT
73 select COMMON_CLK
71 74
72config SOC_OMAP5 75config SOC_OMAP5
73 bool "TI OMAP5" 76 bool "TI OMAP5"
@@ -77,6 +80,7 @@ config SOC_OMAP5
77 select CPU_V7 80 select CPU_V7
78 select HAVE_SMP 81 select HAVE_SMP
79 select SOC_HAS_REALTIME_COUNTER 82 select SOC_HAS_REALTIME_COUNTER
83 select COMMON_CLK
80 84
81comment "OMAP Core Type" 85comment "OMAP Core Type"
82 depends on ARCH_OMAP2 86 depends on ARCH_OMAP2
@@ -111,6 +115,7 @@ config SOC_AM33XX
111 select ARM_CPU_SUSPEND if PM 115 select ARM_CPU_SUSPEND if PM
112 select CPU_V7 116 select CPU_V7
113 select MULTI_IRQ_HANDLER 117 select MULTI_IRQ_HANDLER
118 select COMMON_CLK
114 119
115config OMAP_PACKAGE_ZAF 120config OMAP_PACKAGE_ZAF
116 bool 121 bool
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index b455ffc12ebe..a8004f33b7e2 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -160,17 +160,17 @@ obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpllcore.o
160obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_virt_prcm_set.o 160obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_virt_prcm_set.o
161obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_apll.o clkt2xxx_osc.o 161obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_apll.o clkt2xxx_osc.o
162obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpll.o clkt_iclk.o 162obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpll.o clkt_iclk.o
163obj-$(CONFIG_SOC_OMAP2420) += clock2420_data.o 163obj-$(CONFIG_SOC_OMAP2420) += cclock2420_data.o
164obj-$(CONFIG_SOC_OMAP2430) += clock2430.o clock2430_data.o 164obj-$(CONFIG_SOC_OMAP2430) += clock2430.o cclock2430_data.o
165obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) clock3xxx.o 165obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) clock3xxx.o
166obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o clkt34xx_dpll3m2.o 166obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o clkt34xx_dpll3m2.o
167obj-$(CONFIG_ARCH_OMAP3) += clock3517.o clock36xx.o 167obj-$(CONFIG_ARCH_OMAP3) += clock3517.o clock36xx.o
168obj-$(CONFIG_ARCH_OMAP3) += dpll3xxx.o clock3xxx_data.o 168obj-$(CONFIG_ARCH_OMAP3) += dpll3xxx.o cclock3xxx_data.o
169obj-$(CONFIG_ARCH_OMAP3) += clkt_iclk.o 169obj-$(CONFIG_ARCH_OMAP3) += clkt_iclk.o
170obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) clock44xx_data.o 170obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) cclock44xx_data.o
171obj-$(CONFIG_ARCH_OMAP4) += dpll3xxx.o dpll44xx.o 171obj-$(CONFIG_ARCH_OMAP4) += dpll3xxx.o dpll44xx.o
172obj-$(CONFIG_SOC_AM33XX) += $(clock-common) dpll3xxx.o 172obj-$(CONFIG_SOC_AM33XX) += $(clock-common) dpll3xxx.o
173obj-$(CONFIG_SOC_AM33XX) += clock33xx_data.o 173obj-$(CONFIG_SOC_AM33XX) += cclock33xx_data.o
174obj-$(CONFIG_SOC_OMAP5) += $(clock-common) 174obj-$(CONFIG_SOC_OMAP5) += $(clock-common)
175obj-$(CONFIG_SOC_OMAP5) += dpll3xxx.o dpll44xx.o 175obj-$(CONFIG_SOC_OMAP5) += dpll3xxx.o dpll44xx.o
176 176
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index 6601754f9512..7b201546834d 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -31,7 +31,7 @@
31#include <asm/mach/map.h> 31#include <asm/mach/map.h>
32 32
33#include "common.h" 33#include "common.h"
34#include <plat-omap/dma-omap.h> 34#include <linux/omap-dma.h>
35#include <video/omapdss.h> 35#include <video/omapdss.h>
36#include <video/omap-panel-tfp410.h> 36#include <video/omap-panel-tfp410.h>
37 37
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index b626dbe6f7bc..9a3878ec2256 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -32,7 +32,7 @@
32#include <asm/mach/arch.h> 32#include <asm/mach/arch.h>
33#include <asm/mach/map.h> 33#include <asm/mach/map.h>
34 34
35#include <plat-omap/dma-omap.h> 35#include <linux/omap-dma.h>
36#include <plat/debug-devices.h> 36#include <plat/debug-devices.h>
37 37
38#include <video/omapdss.h> 38#include <video/omapdss.h>
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index 07005fe40a2a..60529e0b3d67 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -31,7 +31,7 @@
31#include <asm/system_info.h> 31#include <asm/system_info.h>
32 32
33#include "common.h" 33#include "common.h"
34#include <plat-omap/dma-omap.h> 34#include <linux/omap-dma.h>
35#include "gpmc-smc91x.h" 35#include "gpmc-smc91x.h"
36 36
37#include "board-rx51.h" 37#include "board-rx51.h"
diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c
index b67fe11d0d94..f1d6efe079ca 100644
--- a/arch/arm/mach-omap2/board-rx51.c
+++ b/arch/arm/mach-omap2/board-rx51.c
@@ -24,7 +24,7 @@
24#include <asm/mach/arch.h> 24#include <asm/mach/arch.h>
25#include <asm/mach/map.h> 25#include <asm/mach/map.h>
26 26
27#include <plat-omap/dma-omap.h> 27#include <linux/omap-dma.h>
28 28
29#include "common.h" 29#include "common.h"
30#include "mux.h" 30#include "mux.h"
diff --git a/arch/arm/mach-omap2/cclock2420_data.c b/arch/arm/mach-omap2/cclock2420_data.c
new file mode 100644
index 000000000000..7e5febe456d9
--- /dev/null
+++ b/arch/arm/mach-omap2/cclock2420_data.c
@@ -0,0 +1,1950 @@
1/*
2 * OMAP2420 clock data
3 *
4 * Copyright (C) 2005-2012 Texas Instruments, Inc.
5 * Copyright (C) 2004-2011 Nokia Corporation
6 *
7 * Contacts:
8 * Richard Woodruff <r-woodruff2@ti.com>
9 * Paul Walmsley
10 * Updated to COMMON clk format by Rajendra Nayak <rnayak@ti.com>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17#include <linux/kernel.h>
18#include <linux/io.h>
19#include <linux/clk.h>
20#include <linux/clk-private.h>
21#include <linux/list.h>
22
23#include "soc.h"
24#include "iomap.h"
25#include "clock.h"
26#include "clock2xxx.h"
27#include "opp2xxx.h"
28#include "cm2xxx.h"
29#include "prm2xxx.h"
30#include "prm-regbits-24xx.h"
31#include "cm-regbits-24xx.h"
32#include "sdrc.h"
33#include "control.h"
34
35#define OMAP_CM_REGADDR OMAP2420_CM_REGADDR
36
37/*
38 * 2420 clock tree.
39 *
40 * NOTE:In many cases here we are assigning a 'default' parent. In
41 * many cases the parent is selectable. The set parent calls will
42 * also switch sources.
43 *
44 * Several sources are given initial rates which may be wrong, this will
45 * be fixed up in the init func.
46 *
47 * Things are broadly separated below by clock domains. It is
48 * noteworthy that most peripherals have dependencies on multiple clock
49 * domains. Many get their interface clocks from the L4 domain, but get
50 * functional clocks from fixed sources or other core domain derived
51 * clocks.
52 */
53
54DEFINE_CLK_FIXED_RATE(alt_ck, CLK_IS_ROOT, 54000000, 0x0);
55
56DEFINE_CLK_FIXED_RATE(func_32k_ck, CLK_IS_ROOT, 32768, 0x0);
57
58DEFINE_CLK_FIXED_RATE(mcbsp_clks, CLK_IS_ROOT, 0x0, 0x0);
59
60static struct clk osc_ck;
61
62static const struct clk_ops osc_ck_ops = {
63 .recalc_rate = &omap2_osc_clk_recalc,
64};
65
66static struct clk_hw_omap osc_ck_hw = {
67 .hw = {
68 .clk = &osc_ck,
69 },
70};
71
72static struct clk osc_ck = {
73 .name = "osc_ck",
74 .ops = &osc_ck_ops,
75 .hw = &osc_ck_hw.hw,
76 .flags = CLK_IS_ROOT,
77};
78
79DEFINE_CLK_FIXED_RATE(secure_32k_ck, CLK_IS_ROOT, 32768, 0x0);
80
81static struct clk sys_ck;
82
83static const char *sys_ck_parent_names[] = {
84 "osc_ck",
85};
86
87static const struct clk_ops sys_ck_ops = {
88 .init = &omap2_init_clk_clkdm,
89 .recalc_rate = &omap2xxx_sys_clk_recalc,
90};
91
92DEFINE_STRUCT_CLK_HW_OMAP(sys_ck, "wkup_clkdm");
93DEFINE_STRUCT_CLK(sys_ck, sys_ck_parent_names, sys_ck_ops);
94
95static struct dpll_data dpll_dd = {
96 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
97 .mult_mask = OMAP24XX_DPLL_MULT_MASK,
98 .div1_mask = OMAP24XX_DPLL_DIV_MASK,
99 .clk_bypass = &sys_ck,
100 .clk_ref = &sys_ck,
101 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
102 .enable_mask = OMAP24XX_EN_DPLL_MASK,
103 .max_multiplier = 1023,
104 .min_divider = 1,
105 .max_divider = 16,
106};
107
108static struct clk dpll_ck;
109
110static const char *dpll_ck_parent_names[] = {
111 "sys_ck",
112};
113
114static const struct clk_ops dpll_ck_ops = {
115 .init = &omap2_init_clk_clkdm,
116 .get_parent = &omap2_init_dpll_parent,
117 .recalc_rate = &omap2_dpllcore_recalc,
118 .round_rate = &omap2_dpll_round_rate,
119 .set_rate = &omap2_reprogram_dpllcore,
120};
121
122static struct clk_hw_omap dpll_ck_hw = {
123 .hw = {
124 .clk = &dpll_ck,
125 },
126 .ops = &clkhwops_omap2xxx_dpll,
127 .dpll_data = &dpll_dd,
128 .clkdm_name = "wkup_clkdm",
129};
130
131DEFINE_STRUCT_CLK(dpll_ck, dpll_ck_parent_names, dpll_ck_ops);
132
133static struct clk core_ck;
134
135static const char *core_ck_parent_names[] = {
136 "dpll_ck",
137};
138
139static const struct clk_ops core_ck_ops = {
140 .init = &omap2_init_clk_clkdm,
141};
142
143DEFINE_STRUCT_CLK_HW_OMAP(core_ck, "wkup_clkdm");
144DEFINE_STRUCT_CLK(core_ck, core_ck_parent_names, core_ck_ops);
145
146DEFINE_CLK_DIVIDER(core_l3_ck, "core_ck", &core_ck, 0x0,
147 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
148 OMAP24XX_CLKSEL_L3_SHIFT, OMAP24XX_CLKSEL_L3_WIDTH,
149 CLK_DIVIDER_ONE_BASED, NULL);
150
151DEFINE_CLK_DIVIDER(l4_ck, "core_l3_ck", &core_l3_ck, 0x0,
152 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
153 OMAP24XX_CLKSEL_L4_SHIFT, OMAP24XX_CLKSEL_L4_WIDTH,
154 CLK_DIVIDER_ONE_BASED, NULL);
155
156static struct clk aes_ick;
157
158static const char *aes_ick_parent_names[] = {
159 "l4_ck",
160};
161
162static const struct clk_ops aes_ick_ops = {
163 .init = &omap2_init_clk_clkdm,
164 .enable = &omap2_dflt_clk_enable,
165 .disable = &omap2_dflt_clk_disable,
166 .is_enabled = &omap2_dflt_clk_is_enabled,
167};
168
169static struct clk_hw_omap aes_ick_hw = {
170 .hw = {
171 .clk = &aes_ick,
172 },
173 .ops = &clkhwops_iclk_wait,
174 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
175 .enable_bit = OMAP24XX_EN_AES_SHIFT,
176 .clkdm_name = "core_l4_clkdm",
177};
178
179DEFINE_STRUCT_CLK(aes_ick, aes_ick_parent_names, aes_ick_ops);
180
181static struct clk apll54_ck;
182
183static const struct clk_ops apll54_ck_ops = {
184 .init = &omap2_init_clk_clkdm,
185 .enable = &omap2_clk_apll54_enable,
186 .disable = &omap2_clk_apll54_disable,
187 .recalc_rate = &omap2_clk_apll54_recalc,
188};
189
190static struct clk_hw_omap apll54_ck_hw = {
191 .hw = {
192 .clk = &apll54_ck,
193 },
194 .ops = &clkhwops_apll54,
195 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
196 .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT,
197 .flags = ENABLE_ON_INIT,
198 .clkdm_name = "wkup_clkdm",
199};
200
201DEFINE_STRUCT_CLK(apll54_ck, dpll_ck_parent_names, apll54_ck_ops);
202
203static struct clk apll96_ck;
204
205static const struct clk_ops apll96_ck_ops = {
206 .init = &omap2_init_clk_clkdm,
207 .enable = &omap2_clk_apll96_enable,
208 .disable = &omap2_clk_apll96_disable,
209 .recalc_rate = &omap2_clk_apll96_recalc,
210};
211
212static struct clk_hw_omap apll96_ck_hw = {
213 .hw = {
214 .clk = &apll96_ck,
215 },
216 .ops = &clkhwops_apll96,
217 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
218 .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT,
219 .flags = ENABLE_ON_INIT,
220 .clkdm_name = "wkup_clkdm",
221};
222
223DEFINE_STRUCT_CLK(apll96_ck, dpll_ck_parent_names, apll96_ck_ops);
224
225static struct clk func_96m_ck;
226
227static const char *func_96m_ck_parent_names[] = {
228 "apll96_ck",
229};
230
231DEFINE_STRUCT_CLK_HW_OMAP(func_96m_ck, "wkup_clkdm");
232DEFINE_STRUCT_CLK(func_96m_ck, func_96m_ck_parent_names, core_ck_ops);
233
234static struct clk cam_fck;
235
236static const char *cam_fck_parent_names[] = {
237 "func_96m_ck",
238};
239
240static struct clk_hw_omap cam_fck_hw = {
241 .hw = {
242 .clk = &cam_fck,
243 },
244 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
245 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
246 .clkdm_name = "core_l3_clkdm",
247};
248
249DEFINE_STRUCT_CLK(cam_fck, cam_fck_parent_names, aes_ick_ops);
250
251static struct clk cam_ick;
252
253static struct clk_hw_omap cam_ick_hw = {
254 .hw = {
255 .clk = &cam_ick,
256 },
257 .ops = &clkhwops_iclk,
258 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
259 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
260 .clkdm_name = "core_l4_clkdm",
261};
262
263DEFINE_STRUCT_CLK(cam_ick, aes_ick_parent_names, aes_ick_ops);
264
265static struct clk des_ick;
266
267static struct clk_hw_omap des_ick_hw = {
268 .hw = {
269 .clk = &des_ick,
270 },
271 .ops = &clkhwops_iclk_wait,
272 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
273 .enable_bit = OMAP24XX_EN_DES_SHIFT,
274 .clkdm_name = "core_l4_clkdm",
275};
276
277DEFINE_STRUCT_CLK(des_ick, aes_ick_parent_names, aes_ick_ops);
278
279static const struct clksel_rate dsp_fck_core_rates[] = {
280 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
281 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
282 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
283 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
284 { .div = 6, .val = 6, .flags = RATE_IN_242X },
285 { .div = 8, .val = 8, .flags = RATE_IN_242X },
286 { .div = 12, .val = 12, .flags = RATE_IN_242X },
287 { .div = 0 }
288};
289
290static const struct clksel dsp_fck_clksel[] = {
291 { .parent = &core_ck, .rates = dsp_fck_core_rates },
292 { .parent = NULL },
293};
294
295static const char *dsp_fck_parent_names[] = {
296 "core_ck",
297};
298
299static const struct clk_ops dsp_fck_ops = {
300 .init = &omap2_init_clk_clkdm,
301 .enable = &omap2_dflt_clk_enable,
302 .disable = &omap2_dflt_clk_disable,
303 .is_enabled = &omap2_dflt_clk_is_enabled,
304 .recalc_rate = &omap2_clksel_recalc,
305 .set_rate = &omap2_clksel_set_rate,
306 .round_rate = &omap2_clksel_round_rate,
307};
308
309DEFINE_CLK_OMAP_MUX_GATE(dsp_fck, "dsp_clkdm", dsp_fck_clksel,
310 OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
311 OMAP24XX_CLKSEL_DSP_MASK,
312 OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
313 OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, &clkhwops_wait,
314 dsp_fck_parent_names, dsp_fck_ops);
315
316static const struct clksel dsp_ick_clksel[] = {
317 { .parent = &dsp_fck, .rates = dsp_ick_rates },
318 { .parent = NULL },
319};
320
321static const char *dsp_ick_parent_names[] = {
322 "dsp_fck",
323};
324
325DEFINE_CLK_OMAP_MUX_GATE(dsp_ick, "dsp_clkdm", dsp_ick_clksel,
326 OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
327 OMAP24XX_CLKSEL_DSP_IF_MASK,
328 OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
329 OMAP2420_EN_DSP_IPI_SHIFT, &clkhwops_iclk_wait,
330 dsp_ick_parent_names, dsp_fck_ops);
331
332static const struct clksel_rate dss1_fck_sys_rates[] = {
333 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
334 { .div = 0 }
335};
336
337static const struct clksel_rate dss1_fck_core_rates[] = {
338 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
339 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
340 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
341 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
342 { .div = 5, .val = 5, .flags = RATE_IN_24XX },
343 { .div = 6, .val = 6, .flags = RATE_IN_24XX },
344 { .div = 8, .val = 8, .flags = RATE_IN_24XX },
345 { .div = 9, .val = 9, .flags = RATE_IN_24XX },
346 { .div = 12, .val = 12, .flags = RATE_IN_24XX },
347 { .div = 16, .val = 16, .flags = RATE_IN_24XX },
348 { .div = 0 }
349};
350
351static const struct clksel dss1_fck_clksel[] = {
352 { .parent = &sys_ck, .rates = dss1_fck_sys_rates },
353 { .parent = &core_ck, .rates = dss1_fck_core_rates },
354 { .parent = NULL },
355};
356
357static const char *dss1_fck_parent_names[] = {
358 "sys_ck", "core_ck",
359};
360
361static struct clk dss1_fck;
362
363static const struct clk_ops dss1_fck_ops = {
364 .init = &omap2_init_clk_clkdm,
365 .enable = &omap2_dflt_clk_enable,
366 .disable = &omap2_dflt_clk_disable,
367 .is_enabled = &omap2_dflt_clk_is_enabled,
368 .recalc_rate = &omap2_clksel_recalc,
369 .get_parent = &omap2_clksel_find_parent_index,
370 .set_parent = &omap2_clksel_set_parent,
371};
372
373DEFINE_CLK_OMAP_MUX_GATE(dss1_fck, "dss_clkdm", dss1_fck_clksel,
374 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
375 OMAP24XX_CLKSEL_DSS1_MASK,
376 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
377 OMAP24XX_EN_DSS1_SHIFT, NULL,
378 dss1_fck_parent_names, dss1_fck_ops);
379
380static const struct clksel_rate dss2_fck_sys_rates[] = {
381 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
382 { .div = 0 }
383};
384
385static const struct clksel_rate dss2_fck_48m_rates[] = {
386 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
387 { .div = 0 }
388};
389
390static const struct clksel_rate func_48m_apll96_rates[] = {
391 { .div = 2, .val = 0, .flags = RATE_IN_24XX },
392 { .div = 0 }
393};
394
395static const struct clksel_rate func_48m_alt_rates[] = {
396 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
397 { .div = 0 }
398};
399
400static const struct clksel func_48m_clksel[] = {
401 { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
402 { .parent = &alt_ck, .rates = func_48m_alt_rates },
403 { .parent = NULL },
404};
405
406static const char *func_48m_ck_parent_names[] = {
407 "apll96_ck", "alt_ck",
408};
409
410static struct clk func_48m_ck;
411
412static const struct clk_ops func_48m_ck_ops = {
413 .init = &omap2_init_clk_clkdm,
414 .recalc_rate = &omap2_clksel_recalc,
415 .set_rate = &omap2_clksel_set_rate,
416 .round_rate = &omap2_clksel_round_rate,
417 .get_parent = &omap2_clksel_find_parent_index,
418 .set_parent = &omap2_clksel_set_parent,
419};
420
421static struct clk_hw_omap func_48m_ck_hw = {
422 .hw = {
423 .clk = &func_48m_ck,
424 },
425 .clksel = func_48m_clksel,
426 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
427 .clksel_mask = OMAP24XX_48M_SOURCE_MASK,
428 .clkdm_name = "wkup_clkdm",
429};
430
431DEFINE_STRUCT_CLK(func_48m_ck, func_48m_ck_parent_names, func_48m_ck_ops);
432
433static const struct clksel dss2_fck_clksel[] = {
434 { .parent = &sys_ck, .rates = dss2_fck_sys_rates },
435 { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
436 { .parent = NULL },
437};
438
439static const char *dss2_fck_parent_names[] = {
440 "sys_ck", "func_48m_ck",
441};
442
443DEFINE_CLK_OMAP_MUX_GATE(dss2_fck, "dss_clkdm", dss2_fck_clksel,
444 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
445 OMAP24XX_CLKSEL_DSS2_MASK,
446 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
447 OMAP24XX_EN_DSS2_SHIFT, NULL,
448 dss2_fck_parent_names, dss1_fck_ops);
449
450static const char *func_54m_ck_parent_names[] = {
451 "apll54_ck", "alt_ck",
452};
453
454DEFINE_CLK_MUX(func_54m_ck, func_54m_ck_parent_names, NULL, 0x0,
455 OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
456 OMAP24XX_54M_SOURCE_SHIFT, OMAP24XX_54M_SOURCE_WIDTH,
457 0x0, NULL);
458
459static struct clk dss_54m_fck;
460
461static const char *dss_54m_fck_parent_names[] = {
462 "func_54m_ck",
463};
464
465static struct clk_hw_omap dss_54m_fck_hw = {
466 .hw = {
467 .clk = &dss_54m_fck,
468 },
469 .ops = &clkhwops_wait,
470 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
471 .enable_bit = OMAP24XX_EN_TV_SHIFT,
472 .clkdm_name = "dss_clkdm",
473};
474
475DEFINE_STRUCT_CLK(dss_54m_fck, dss_54m_fck_parent_names, aes_ick_ops);
476
477static struct clk dss_ick;
478
479static struct clk_hw_omap dss_ick_hw = {
480 .hw = {
481 .clk = &dss_ick,
482 },
483 .ops = &clkhwops_iclk,
484 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
485 .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
486 .clkdm_name = "dss_clkdm",
487};
488
489DEFINE_STRUCT_CLK(dss_ick, aes_ick_parent_names, aes_ick_ops);
490
491static struct clk eac_fck;
492
493static struct clk_hw_omap eac_fck_hw = {
494 .hw = {
495 .clk = &eac_fck,
496 },
497 .ops = &clkhwops_wait,
498 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
499 .enable_bit = OMAP2420_EN_EAC_SHIFT,
500 .clkdm_name = "core_l4_clkdm",
501};
502
503DEFINE_STRUCT_CLK(eac_fck, cam_fck_parent_names, aes_ick_ops);
504
505static struct clk eac_ick;
506
507static struct clk_hw_omap eac_ick_hw = {
508 .hw = {
509 .clk = &eac_ick,
510 },
511 .ops = &clkhwops_iclk_wait,
512 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
513 .enable_bit = OMAP2420_EN_EAC_SHIFT,
514 .clkdm_name = "core_l4_clkdm",
515};
516
517DEFINE_STRUCT_CLK(eac_ick, aes_ick_parent_names, aes_ick_ops);
518
519static struct clk emul_ck;
520
521static struct clk_hw_omap emul_ck_hw = {
522 .hw = {
523 .clk = &emul_ck,
524 },
525 .enable_reg = OMAP2420_PRCM_CLKEMUL_CTRL,
526 .enable_bit = OMAP24XX_EMULATION_EN_SHIFT,
527 .clkdm_name = "wkup_clkdm",
528};
529
530DEFINE_STRUCT_CLK(emul_ck, dss_54m_fck_parent_names, aes_ick_ops);
531
532DEFINE_CLK_FIXED_FACTOR(func_12m_ck, "func_48m_ck", &func_48m_ck, 0x0, 1, 4);
533
534static struct clk fac_fck;
535
536static const char *fac_fck_parent_names[] = {
537 "func_12m_ck",
538};
539
540static struct clk_hw_omap fac_fck_hw = {
541 .hw = {
542 .clk = &fac_fck,
543 },
544 .ops = &clkhwops_wait,
545 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
546 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
547 .clkdm_name = "core_l4_clkdm",
548};
549
550DEFINE_STRUCT_CLK(fac_fck, fac_fck_parent_names, aes_ick_ops);
551
552static struct clk fac_ick;
553
554static struct clk_hw_omap fac_ick_hw = {
555 .hw = {
556 .clk = &fac_ick,
557 },
558 .ops = &clkhwops_iclk_wait,
559 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
560 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
561 .clkdm_name = "core_l4_clkdm",
562};
563
564DEFINE_STRUCT_CLK(fac_ick, aes_ick_parent_names, aes_ick_ops);
565
566static const struct clksel gfx_fck_clksel[] = {
567 { .parent = &core_l3_ck, .rates = gfx_l3_rates },
568 { .parent = NULL },
569};
570
571static const char *gfx_2d_fck_parent_names[] = {
572 "core_l3_ck",
573};
574
575DEFINE_CLK_OMAP_MUX_GATE(gfx_2d_fck, "gfx_clkdm", gfx_fck_clksel,
576 OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
577 OMAP_CLKSEL_GFX_MASK,
578 OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
579 OMAP24XX_EN_2D_SHIFT, &clkhwops_wait,
580 gfx_2d_fck_parent_names, dsp_fck_ops);
581
582DEFINE_CLK_OMAP_MUX_GATE(gfx_3d_fck, "gfx_clkdm", gfx_fck_clksel,
583 OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
584 OMAP_CLKSEL_GFX_MASK,
585 OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
586 OMAP24XX_EN_3D_SHIFT, &clkhwops_wait,
587 gfx_2d_fck_parent_names, dsp_fck_ops);
588
589static struct clk gfx_ick;
590
591static const char *gfx_ick_parent_names[] = {
592 "core_l3_ck",
593};
594
595static struct clk_hw_omap gfx_ick_hw = {
596 .hw = {
597 .clk = &gfx_ick,
598 },
599 .ops = &clkhwops_wait,
600 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
601 .enable_bit = OMAP_EN_GFX_SHIFT,
602 .clkdm_name = "gfx_clkdm",
603};
604
605DEFINE_STRUCT_CLK(gfx_ick, gfx_ick_parent_names, aes_ick_ops);
606
607static struct clk gpios_fck;
608
609static const char *gpios_fck_parent_names[] = {
610 "func_32k_ck",
611};
612
613static struct clk_hw_omap gpios_fck_hw = {
614 .hw = {
615 .clk = &gpios_fck,
616 },
617 .ops = &clkhwops_wait,
618 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
619 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
620 .clkdm_name = "wkup_clkdm",
621};
622
623DEFINE_STRUCT_CLK(gpios_fck, gpios_fck_parent_names, aes_ick_ops);
624
625static struct clk wu_l4_ick;
626
627DEFINE_STRUCT_CLK_HW_OMAP(wu_l4_ick, "wkup_clkdm");
628DEFINE_STRUCT_CLK(wu_l4_ick, dpll_ck_parent_names, core_ck_ops);
629
630static struct clk gpios_ick;
631
632static const char *gpios_ick_parent_names[] = {
633 "wu_l4_ick",
634};
635
636static struct clk_hw_omap gpios_ick_hw = {
637 .hw = {
638 .clk = &gpios_ick,
639 },
640 .ops = &clkhwops_iclk_wait,
641 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
642 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
643 .clkdm_name = "wkup_clkdm",
644};
645
646DEFINE_STRUCT_CLK(gpios_ick, gpios_ick_parent_names, aes_ick_ops);
647
648static struct clk gpmc_fck;
649
650static struct clk_hw_omap gpmc_fck_hw = {
651 .hw = {
652 .clk = &gpmc_fck,
653 },
654 .ops = &clkhwops_iclk,
655 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
656 .enable_bit = OMAP24XX_AUTO_GPMC_SHIFT,
657 .flags = ENABLE_ON_INIT,
658 .clkdm_name = "core_l3_clkdm",
659};
660
661DEFINE_STRUCT_CLK(gpmc_fck, gfx_ick_parent_names, core_ck_ops);
662
663static const struct clksel_rate gpt_alt_rates[] = {
664 { .div = 1, .val = 2, .flags = RATE_IN_24XX },
665 { .div = 0 }
666};
667
668static const struct clksel omap24xx_gpt_clksel[] = {
669 { .parent = &func_32k_ck, .rates = gpt_32k_rates },
670 { .parent = &sys_ck, .rates = gpt_sys_rates },
671 { .parent = &alt_ck, .rates = gpt_alt_rates },
672 { .parent = NULL },
673};
674
675static const char *gpt10_fck_parent_names[] = {
676 "func_32k_ck", "sys_ck", "alt_ck",
677};
678
679DEFINE_CLK_OMAP_MUX_GATE(gpt10_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
680 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
681 OMAP24XX_CLKSEL_GPT10_MASK,
682 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
683 OMAP24XX_EN_GPT10_SHIFT, &clkhwops_wait,
684 gpt10_fck_parent_names, dss1_fck_ops);
685
686static struct clk gpt10_ick;
687
688static struct clk_hw_omap gpt10_ick_hw = {
689 .hw = {
690 .clk = &gpt10_ick,
691 },
692 .ops = &clkhwops_iclk_wait,
693 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
694 .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
695 .clkdm_name = "core_l4_clkdm",
696};
697
698DEFINE_STRUCT_CLK(gpt10_ick, aes_ick_parent_names, aes_ick_ops);
699
700DEFINE_CLK_OMAP_MUX_GATE(gpt11_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
701 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
702 OMAP24XX_CLKSEL_GPT11_MASK,
703 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
704 OMAP24XX_EN_GPT11_SHIFT, &clkhwops_wait,
705 gpt10_fck_parent_names, dss1_fck_ops);
706
707static struct clk gpt11_ick;
708
709static struct clk_hw_omap gpt11_ick_hw = {
710 .hw = {
711 .clk = &gpt11_ick,
712 },
713 .ops = &clkhwops_iclk_wait,
714 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
715 .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
716 .clkdm_name = "core_l4_clkdm",
717};
718
719DEFINE_STRUCT_CLK(gpt11_ick, aes_ick_parent_names, aes_ick_ops);
720
721DEFINE_CLK_OMAP_MUX_GATE(gpt12_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
722 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
723 OMAP24XX_CLKSEL_GPT12_MASK,
724 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
725 OMAP24XX_EN_GPT12_SHIFT, &clkhwops_wait,
726 gpt10_fck_parent_names, dss1_fck_ops);
727
728static struct clk gpt12_ick;
729
730static struct clk_hw_omap gpt12_ick_hw = {
731 .hw = {
732 .clk = &gpt12_ick,
733 },
734 .ops = &clkhwops_iclk_wait,
735 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
736 .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
737 .clkdm_name = "core_l4_clkdm",
738};
739
740DEFINE_STRUCT_CLK(gpt12_ick, aes_ick_parent_names, aes_ick_ops);
741
742static const struct clk_ops gpt1_fck_ops = {
743 .init = &omap2_init_clk_clkdm,
744 .enable = &omap2_dflt_clk_enable,
745 .disable = &omap2_dflt_clk_disable,
746 .is_enabled = &omap2_dflt_clk_is_enabled,
747 .recalc_rate = &omap2_clksel_recalc,
748 .set_rate = &omap2_clksel_set_rate,
749 .round_rate = &omap2_clksel_round_rate,
750 .get_parent = &omap2_clksel_find_parent_index,
751 .set_parent = &omap2_clksel_set_parent,
752};
753
754DEFINE_CLK_OMAP_MUX_GATE(gpt1_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
755 OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1),
756 OMAP24XX_CLKSEL_GPT1_MASK,
757 OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
758 OMAP24XX_EN_GPT1_SHIFT, &clkhwops_wait,
759 gpt10_fck_parent_names, gpt1_fck_ops);
760
761static struct clk gpt1_ick;
762
763static struct clk_hw_omap gpt1_ick_hw = {
764 .hw = {
765 .clk = &gpt1_ick,
766 },
767 .ops = &clkhwops_iclk_wait,
768 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
769 .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
770 .clkdm_name = "wkup_clkdm",
771};
772
773DEFINE_STRUCT_CLK(gpt1_ick, gpios_ick_parent_names, aes_ick_ops);
774
775DEFINE_CLK_OMAP_MUX_GATE(gpt2_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
776 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
777 OMAP24XX_CLKSEL_GPT2_MASK,
778 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
779 OMAP24XX_EN_GPT2_SHIFT, &clkhwops_wait,
780 gpt10_fck_parent_names, dss1_fck_ops);
781
782static struct clk gpt2_ick;
783
784static struct clk_hw_omap gpt2_ick_hw = {
785 .hw = {
786 .clk = &gpt2_ick,
787 },
788 .ops = &clkhwops_iclk_wait,
789 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
790 .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
791 .clkdm_name = "core_l4_clkdm",
792};
793
794DEFINE_STRUCT_CLK(gpt2_ick, aes_ick_parent_names, aes_ick_ops);
795
796DEFINE_CLK_OMAP_MUX_GATE(gpt3_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
797 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
798 OMAP24XX_CLKSEL_GPT3_MASK,
799 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
800 OMAP24XX_EN_GPT3_SHIFT, &clkhwops_wait,
801 gpt10_fck_parent_names, dss1_fck_ops);
802
803static struct clk gpt3_ick;
804
805static struct clk_hw_omap gpt3_ick_hw = {
806 .hw = {
807 .clk = &gpt3_ick,
808 },
809 .ops = &clkhwops_iclk_wait,
810 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
811 .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
812 .clkdm_name = "core_l4_clkdm",
813};
814
815DEFINE_STRUCT_CLK(gpt3_ick, aes_ick_parent_names, aes_ick_ops);
816
817DEFINE_CLK_OMAP_MUX_GATE(gpt4_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
818 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
819 OMAP24XX_CLKSEL_GPT4_MASK,
820 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
821 OMAP24XX_EN_GPT4_SHIFT, &clkhwops_wait,
822 gpt10_fck_parent_names, dss1_fck_ops);
823
824static struct clk gpt4_ick;
825
826static struct clk_hw_omap gpt4_ick_hw = {
827 .hw = {
828 .clk = &gpt4_ick,
829 },
830 .ops = &clkhwops_iclk_wait,
831 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
832 .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
833 .clkdm_name = "core_l4_clkdm",
834};
835
836DEFINE_STRUCT_CLK(gpt4_ick, aes_ick_parent_names, aes_ick_ops);
837
838DEFINE_CLK_OMAP_MUX_GATE(gpt5_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
839 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
840 OMAP24XX_CLKSEL_GPT5_MASK,
841 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
842 OMAP24XX_EN_GPT5_SHIFT, &clkhwops_wait,
843 gpt10_fck_parent_names, dss1_fck_ops);
844
845static struct clk gpt5_ick;
846
847static struct clk_hw_omap gpt5_ick_hw = {
848 .hw = {
849 .clk = &gpt5_ick,
850 },
851 .ops = &clkhwops_iclk_wait,
852 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
853 .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
854 .clkdm_name = "core_l4_clkdm",
855};
856
857DEFINE_STRUCT_CLK(gpt5_ick, aes_ick_parent_names, aes_ick_ops);
858
859DEFINE_CLK_OMAP_MUX_GATE(gpt6_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
860 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
861 OMAP24XX_CLKSEL_GPT6_MASK,
862 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
863 OMAP24XX_EN_GPT6_SHIFT, &clkhwops_wait,
864 gpt10_fck_parent_names, dss1_fck_ops);
865
866static struct clk gpt6_ick;
867
868static struct clk_hw_omap gpt6_ick_hw = {
869 .hw = {
870 .clk = &gpt6_ick,
871 },
872 .ops = &clkhwops_iclk_wait,
873 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
874 .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
875 .clkdm_name = "core_l4_clkdm",
876};
877
878DEFINE_STRUCT_CLK(gpt6_ick, aes_ick_parent_names, aes_ick_ops);
879
880DEFINE_CLK_OMAP_MUX_GATE(gpt7_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
881 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
882 OMAP24XX_CLKSEL_GPT7_MASK,
883 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
884 OMAP24XX_EN_GPT7_SHIFT, &clkhwops_wait,
885 gpt10_fck_parent_names, dss1_fck_ops);
886
887static struct clk gpt7_ick;
888
889static struct clk_hw_omap gpt7_ick_hw = {
890 .hw = {
891 .clk = &gpt7_ick,
892 },
893 .ops = &clkhwops_iclk_wait,
894 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
895 .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
896 .clkdm_name = "core_l4_clkdm",
897};
898
899DEFINE_STRUCT_CLK(gpt7_ick, aes_ick_parent_names, aes_ick_ops);
900
901DEFINE_CLK_OMAP_MUX_GATE(gpt8_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
902 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
903 OMAP24XX_CLKSEL_GPT8_MASK,
904 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
905 OMAP24XX_EN_GPT8_SHIFT, &clkhwops_wait,
906 gpt10_fck_parent_names, dss1_fck_ops);
907
908static struct clk gpt8_ick;
909
910static struct clk_hw_omap gpt8_ick_hw = {
911 .hw = {
912 .clk = &gpt8_ick,
913 },
914 .ops = &clkhwops_iclk_wait,
915 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
916 .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
917 .clkdm_name = "core_l4_clkdm",
918};
919
920DEFINE_STRUCT_CLK(gpt8_ick, aes_ick_parent_names, aes_ick_ops);
921
922DEFINE_CLK_OMAP_MUX_GATE(gpt9_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
923 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
924 OMAP24XX_CLKSEL_GPT9_MASK,
925 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
926 OMAP24XX_EN_GPT9_SHIFT, &clkhwops_wait,
927 gpt10_fck_parent_names, dss1_fck_ops);
928
929static struct clk gpt9_ick;
930
931static struct clk_hw_omap gpt9_ick_hw = {
932 .hw = {
933 .clk = &gpt9_ick,
934 },
935 .ops = &clkhwops_iclk_wait,
936 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
937 .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
938 .clkdm_name = "core_l4_clkdm",
939};
940
941DEFINE_STRUCT_CLK(gpt9_ick, aes_ick_parent_names, aes_ick_ops);
942
943static struct clk hdq_fck;
944
945static struct clk_hw_omap hdq_fck_hw = {
946 .hw = {
947 .clk = &hdq_fck,
948 },
949 .ops = &clkhwops_wait,
950 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
951 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
952 .clkdm_name = "core_l4_clkdm",
953};
954
955DEFINE_STRUCT_CLK(hdq_fck, fac_fck_parent_names, aes_ick_ops);
956
957static struct clk hdq_ick;
958
959static struct clk_hw_omap hdq_ick_hw = {
960 .hw = {
961 .clk = &hdq_ick,
962 },
963 .ops = &clkhwops_iclk_wait,
964 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
965 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
966 .clkdm_name = "core_l4_clkdm",
967};
968
969DEFINE_STRUCT_CLK(hdq_ick, aes_ick_parent_names, aes_ick_ops);
970
971static struct clk i2c1_fck;
972
973static struct clk_hw_omap i2c1_fck_hw = {
974 .hw = {
975 .clk = &i2c1_fck,
976 },
977 .ops = &clkhwops_wait,
978 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
979 .enable_bit = OMAP2420_EN_I2C1_SHIFT,
980 .clkdm_name = "core_l4_clkdm",
981};
982
983DEFINE_STRUCT_CLK(i2c1_fck, fac_fck_parent_names, aes_ick_ops);
984
985static struct clk i2c1_ick;
986
987static struct clk_hw_omap i2c1_ick_hw = {
988 .hw = {
989 .clk = &i2c1_ick,
990 },
991 .ops = &clkhwops_iclk_wait,
992 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
993 .enable_bit = OMAP2420_EN_I2C1_SHIFT,
994 .clkdm_name = "core_l4_clkdm",
995};
996
997DEFINE_STRUCT_CLK(i2c1_ick, aes_ick_parent_names, aes_ick_ops);
998
999static struct clk i2c2_fck;
1000
1001static struct clk_hw_omap i2c2_fck_hw = {
1002 .hw = {
1003 .clk = &i2c2_fck,
1004 },
1005 .ops = &clkhwops_wait,
1006 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1007 .enable_bit = OMAP2420_EN_I2C2_SHIFT,
1008 .clkdm_name = "core_l4_clkdm",
1009};
1010
1011DEFINE_STRUCT_CLK(i2c2_fck, fac_fck_parent_names, aes_ick_ops);
1012
1013static struct clk i2c2_ick;
1014
1015static struct clk_hw_omap i2c2_ick_hw = {
1016 .hw = {
1017 .clk = &i2c2_ick,
1018 },
1019 .ops = &clkhwops_iclk_wait,
1020 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1021 .enable_bit = OMAP2420_EN_I2C2_SHIFT,
1022 .clkdm_name = "core_l4_clkdm",
1023};
1024
1025DEFINE_STRUCT_CLK(i2c2_ick, aes_ick_parent_names, aes_ick_ops);
1026
1027DEFINE_CLK_OMAP_MUX_GATE(iva1_ifck, "iva1_clkdm", dsp_fck_clksel,
1028 OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1029 OMAP2420_CLKSEL_IVA_MASK,
1030 OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1031 OMAP2420_EN_IVA_COP_SHIFT, &clkhwops_wait,
1032 dsp_fck_parent_names, dsp_fck_ops);
1033
1034static struct clk iva1_mpu_int_ifck;
1035
1036static const char *iva1_mpu_int_ifck_parent_names[] = {
1037 "iva1_ifck",
1038};
1039
1040static const struct clk_ops iva1_mpu_int_ifck_ops = {
1041 .init = &omap2_init_clk_clkdm,
1042 .enable = &omap2_dflt_clk_enable,
1043 .disable = &omap2_dflt_clk_disable,
1044 .is_enabled = &omap2_dflt_clk_is_enabled,
1045 .recalc_rate = &omap_fixed_divisor_recalc,
1046};
1047
1048static struct clk_hw_omap iva1_mpu_int_ifck_hw = {
1049 .hw = {
1050 .clk = &iva1_mpu_int_ifck,
1051 },
1052 .ops = &clkhwops_wait,
1053 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1054 .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT,
1055 .clkdm_name = "iva1_clkdm",
1056 .fixed_div = 2,
1057};
1058
1059DEFINE_STRUCT_CLK(iva1_mpu_int_ifck, iva1_mpu_int_ifck_parent_names,
1060 iva1_mpu_int_ifck_ops);
1061
1062static struct clk mailboxes_ick;
1063
1064static struct clk_hw_omap mailboxes_ick_hw = {
1065 .hw = {
1066 .clk = &mailboxes_ick,
1067 },
1068 .ops = &clkhwops_iclk_wait,
1069 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1070 .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
1071 .clkdm_name = "core_l4_clkdm",
1072};
1073
1074DEFINE_STRUCT_CLK(mailboxes_ick, aes_ick_parent_names, aes_ick_ops);
1075
1076static const struct clksel_rate common_mcbsp_96m_rates[] = {
1077 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
1078 { .div = 0 }
1079};
1080
1081static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1082 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1083 { .div = 0 }
1084};
1085
1086static const struct clksel mcbsp_fck_clksel[] = {
1087 { .parent = &func_96m_ck, .rates = common_mcbsp_96m_rates },
1088 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
1089 { .parent = NULL },
1090};
1091
1092static const char *mcbsp1_fck_parent_names[] = {
1093 "func_96m_ck", "mcbsp_clks",
1094};
1095
1096DEFINE_CLK_OMAP_MUX_GATE(mcbsp1_fck, "core_l4_clkdm", mcbsp_fck_clksel,
1097 OMAP242X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1098 OMAP2_MCBSP1_CLKS_MASK,
1099 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1100 OMAP24XX_EN_MCBSP1_SHIFT, &clkhwops_wait,
1101 mcbsp1_fck_parent_names, dss1_fck_ops);
1102
1103static struct clk mcbsp1_ick;
1104
1105static struct clk_hw_omap mcbsp1_ick_hw = {
1106 .hw = {
1107 .clk = &mcbsp1_ick,
1108 },
1109 .ops = &clkhwops_iclk_wait,
1110 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1111 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1112 .clkdm_name = "core_l4_clkdm",
1113};
1114
1115DEFINE_STRUCT_CLK(mcbsp1_ick, aes_ick_parent_names, aes_ick_ops);
1116
1117DEFINE_CLK_OMAP_MUX_GATE(mcbsp2_fck, "core_l4_clkdm", mcbsp_fck_clksel,
1118 OMAP242X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1119 OMAP2_MCBSP2_CLKS_MASK,
1120 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1121 OMAP24XX_EN_MCBSP2_SHIFT, &clkhwops_wait,
1122 mcbsp1_fck_parent_names, dss1_fck_ops);
1123
1124static struct clk mcbsp2_ick;
1125
1126static struct clk_hw_omap mcbsp2_ick_hw = {
1127 .hw = {
1128 .clk = &mcbsp2_ick,
1129 },
1130 .ops = &clkhwops_iclk_wait,
1131 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1132 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1133 .clkdm_name = "core_l4_clkdm",
1134};
1135
1136DEFINE_STRUCT_CLK(mcbsp2_ick, aes_ick_parent_names, aes_ick_ops);
1137
1138static struct clk mcspi1_fck;
1139
1140static const char *mcspi1_fck_parent_names[] = {
1141 "func_48m_ck",
1142};
1143
1144static struct clk_hw_omap mcspi1_fck_hw = {
1145 .hw = {
1146 .clk = &mcspi1_fck,
1147 },
1148 .ops = &clkhwops_wait,
1149 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1150 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1151 .clkdm_name = "core_l4_clkdm",
1152};
1153
1154DEFINE_STRUCT_CLK(mcspi1_fck, mcspi1_fck_parent_names, aes_ick_ops);
1155
1156static struct clk mcspi1_ick;
1157
1158static struct clk_hw_omap mcspi1_ick_hw = {
1159 .hw = {
1160 .clk = &mcspi1_ick,
1161 },
1162 .ops = &clkhwops_iclk_wait,
1163 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1164 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1165 .clkdm_name = "core_l4_clkdm",
1166};
1167
1168DEFINE_STRUCT_CLK(mcspi1_ick, aes_ick_parent_names, aes_ick_ops);
1169
1170static struct clk mcspi2_fck;
1171
1172static struct clk_hw_omap mcspi2_fck_hw = {
1173 .hw = {
1174 .clk = &mcspi2_fck,
1175 },
1176 .ops = &clkhwops_wait,
1177 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1178 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1179 .clkdm_name = "core_l4_clkdm",
1180};
1181
1182DEFINE_STRUCT_CLK(mcspi2_fck, mcspi1_fck_parent_names, aes_ick_ops);
1183
1184static struct clk mcspi2_ick;
1185
1186static struct clk_hw_omap mcspi2_ick_hw = {
1187 .hw = {
1188 .clk = &mcspi2_ick,
1189 },
1190 .ops = &clkhwops_iclk_wait,
1191 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1192 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1193 .clkdm_name = "core_l4_clkdm",
1194};
1195
1196DEFINE_STRUCT_CLK(mcspi2_ick, aes_ick_parent_names, aes_ick_ops);
1197
1198static struct clk mmc_fck;
1199
1200static struct clk_hw_omap mmc_fck_hw = {
1201 .hw = {
1202 .clk = &mmc_fck,
1203 },
1204 .ops = &clkhwops_wait,
1205 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1206 .enable_bit = OMAP2420_EN_MMC_SHIFT,
1207 .clkdm_name = "core_l4_clkdm",
1208};
1209
1210DEFINE_STRUCT_CLK(mmc_fck, cam_fck_parent_names, aes_ick_ops);
1211
1212static struct clk mmc_ick;
1213
1214static struct clk_hw_omap mmc_ick_hw = {
1215 .hw = {
1216 .clk = &mmc_ick,
1217 },
1218 .ops = &clkhwops_iclk_wait,
1219 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1220 .enable_bit = OMAP2420_EN_MMC_SHIFT,
1221 .clkdm_name = "core_l4_clkdm",
1222};
1223
1224DEFINE_STRUCT_CLK(mmc_ick, aes_ick_parent_names, aes_ick_ops);
1225
1226DEFINE_CLK_DIVIDER(mpu_ck, "core_ck", &core_ck, 0x0,
1227 OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
1228 OMAP24XX_CLKSEL_MPU_SHIFT, OMAP24XX_CLKSEL_MPU_WIDTH,
1229 CLK_DIVIDER_ONE_BASED, NULL);
1230
1231static struct clk mpu_wdt_fck;
1232
1233static struct clk_hw_omap mpu_wdt_fck_hw = {
1234 .hw = {
1235 .clk = &mpu_wdt_fck,
1236 },
1237 .ops = &clkhwops_wait,
1238 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1239 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
1240 .clkdm_name = "wkup_clkdm",
1241};
1242
1243DEFINE_STRUCT_CLK(mpu_wdt_fck, gpios_fck_parent_names, aes_ick_ops);
1244
1245static struct clk mpu_wdt_ick;
1246
1247static struct clk_hw_omap mpu_wdt_ick_hw = {
1248 .hw = {
1249 .clk = &mpu_wdt_ick,
1250 },
1251 .ops = &clkhwops_iclk_wait,
1252 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1253 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
1254 .clkdm_name = "wkup_clkdm",
1255};
1256
1257DEFINE_STRUCT_CLK(mpu_wdt_ick, gpios_ick_parent_names, aes_ick_ops);
1258
1259static struct clk mspro_fck;
1260
1261static struct clk_hw_omap mspro_fck_hw = {
1262 .hw = {
1263 .clk = &mspro_fck,
1264 },
1265 .ops = &clkhwops_wait,
1266 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1267 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
1268 .clkdm_name = "core_l4_clkdm",
1269};
1270
1271DEFINE_STRUCT_CLK(mspro_fck, cam_fck_parent_names, aes_ick_ops);
1272
1273static struct clk mspro_ick;
1274
1275static struct clk_hw_omap mspro_ick_hw = {
1276 .hw = {
1277 .clk = &mspro_ick,
1278 },
1279 .ops = &clkhwops_iclk_wait,
1280 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1281 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
1282 .clkdm_name = "core_l4_clkdm",
1283};
1284
1285DEFINE_STRUCT_CLK(mspro_ick, aes_ick_parent_names, aes_ick_ops);
1286
1287static struct clk omapctrl_ick;
1288
1289static struct clk_hw_omap omapctrl_ick_hw = {
1290 .hw = {
1291 .clk = &omapctrl_ick,
1292 },
1293 .ops = &clkhwops_iclk_wait,
1294 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1295 .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT,
1296 .flags = ENABLE_ON_INIT,
1297 .clkdm_name = "wkup_clkdm",
1298};
1299
1300DEFINE_STRUCT_CLK(omapctrl_ick, gpios_ick_parent_names, aes_ick_ops);
1301
1302static struct clk pka_ick;
1303
1304static struct clk_hw_omap pka_ick_hw = {
1305 .hw = {
1306 .clk = &pka_ick,
1307 },
1308 .ops = &clkhwops_iclk_wait,
1309 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1310 .enable_bit = OMAP24XX_EN_PKA_SHIFT,
1311 .clkdm_name = "core_l4_clkdm",
1312};
1313
1314DEFINE_STRUCT_CLK(pka_ick, aes_ick_parent_names, aes_ick_ops);
1315
1316static struct clk rng_ick;
1317
1318static struct clk_hw_omap rng_ick_hw = {
1319 .hw = {
1320 .clk = &rng_ick,
1321 },
1322 .ops = &clkhwops_iclk_wait,
1323 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1324 .enable_bit = OMAP24XX_EN_RNG_SHIFT,
1325 .clkdm_name = "core_l4_clkdm",
1326};
1327
1328DEFINE_STRUCT_CLK(rng_ick, aes_ick_parent_names, aes_ick_ops);
1329
1330static struct clk sdma_fck;
1331
1332DEFINE_STRUCT_CLK_HW_OMAP(sdma_fck, "core_l3_clkdm");
1333DEFINE_STRUCT_CLK(sdma_fck, gfx_ick_parent_names, core_ck_ops);
1334
1335static struct clk sdma_ick;
1336
1337static struct clk_hw_omap sdma_ick_hw = {
1338 .hw = {
1339 .clk = &sdma_ick,
1340 },
1341 .ops = &clkhwops_iclk,
1342 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1343 .enable_bit = OMAP24XX_AUTO_SDMA_SHIFT,
1344 .clkdm_name = "core_l3_clkdm",
1345};
1346
1347DEFINE_STRUCT_CLK(sdma_ick, gfx_ick_parent_names, core_ck_ops);
1348
1349static struct clk sdrc_ick;
1350
1351static struct clk_hw_omap sdrc_ick_hw = {
1352 .hw = {
1353 .clk = &sdrc_ick,
1354 },
1355 .ops = &clkhwops_iclk,
1356 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1357 .enable_bit = OMAP24XX_AUTO_SDRC_SHIFT,
1358 .flags = ENABLE_ON_INIT,
1359 .clkdm_name = "core_l3_clkdm",
1360};
1361
1362DEFINE_STRUCT_CLK(sdrc_ick, gfx_ick_parent_names, core_ck_ops);
1363
1364static struct clk sha_ick;
1365
1366static struct clk_hw_omap sha_ick_hw = {
1367 .hw = {
1368 .clk = &sha_ick,
1369 },
1370 .ops = &clkhwops_iclk_wait,
1371 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1372 .enable_bit = OMAP24XX_EN_SHA_SHIFT,
1373 .clkdm_name = "core_l4_clkdm",
1374};
1375
1376DEFINE_STRUCT_CLK(sha_ick, aes_ick_parent_names, aes_ick_ops);
1377
1378static struct clk ssi_l4_ick;
1379
1380static struct clk_hw_omap ssi_l4_ick_hw = {
1381 .hw = {
1382 .clk = &ssi_l4_ick,
1383 },
1384 .ops = &clkhwops_iclk_wait,
1385 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1386 .enable_bit = OMAP24XX_EN_SSI_SHIFT,
1387 .clkdm_name = "core_l4_clkdm",
1388};
1389
1390DEFINE_STRUCT_CLK(ssi_l4_ick, aes_ick_parent_names, aes_ick_ops);
1391
1392static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
1393 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1394 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1395 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1396 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1397 { .div = 6, .val = 6, .flags = RATE_IN_242X },
1398 { .div = 8, .val = 8, .flags = RATE_IN_242X },
1399 { .div = 0 }
1400};
1401
1402static const struct clksel ssi_ssr_sst_fck_clksel[] = {
1403 { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
1404 { .parent = NULL },
1405};
1406
1407static const char *ssi_ssr_sst_fck_parent_names[] = {
1408 "core_ck",
1409};
1410
1411DEFINE_CLK_OMAP_MUX_GATE(ssi_ssr_sst_fck, "core_l3_clkdm",
1412 ssi_ssr_sst_fck_clksel,
1413 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1414 OMAP24XX_CLKSEL_SSI_MASK,
1415 OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1416 OMAP24XX_EN_SSI_SHIFT, &clkhwops_wait,
1417 ssi_ssr_sst_fck_parent_names, dsp_fck_ops);
1418
1419static struct clk sync_32k_ick;
1420
1421static struct clk_hw_omap sync_32k_ick_hw = {
1422 .hw = {
1423 .clk = &sync_32k_ick,
1424 },
1425 .ops = &clkhwops_iclk_wait,
1426 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1427 .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT,
1428 .flags = ENABLE_ON_INIT,
1429 .clkdm_name = "wkup_clkdm",
1430};
1431
1432DEFINE_STRUCT_CLK(sync_32k_ick, gpios_ick_parent_names, aes_ick_ops);
1433
1434static const struct clksel_rate common_clkout_src_core_rates[] = {
1435 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
1436 { .div = 0 }
1437};
1438
1439static const struct clksel_rate common_clkout_src_sys_rates[] = {
1440 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1441 { .div = 0 }
1442};
1443
1444static const struct clksel_rate common_clkout_src_96m_rates[] = {
1445 { .div = 1, .val = 2, .flags = RATE_IN_24XX },
1446 { .div = 0 }
1447};
1448
1449static const struct clksel_rate common_clkout_src_54m_rates[] = {
1450 { .div = 1, .val = 3, .flags = RATE_IN_24XX },
1451 { .div = 0 }
1452};
1453
1454static const struct clksel common_clkout_src_clksel[] = {
1455 { .parent = &core_ck, .rates = common_clkout_src_core_rates },
1456 { .parent = &sys_ck, .rates = common_clkout_src_sys_rates },
1457 { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
1458 { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
1459 { .parent = NULL },
1460};
1461
1462static const char *sys_clkout_src_parent_names[] = {
1463 "core_ck", "sys_ck", "func_96m_ck", "func_54m_ck",
1464};
1465
1466DEFINE_CLK_OMAP_MUX_GATE(sys_clkout_src, "wkup_clkdm", common_clkout_src_clksel,
1467 OMAP2420_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_SOURCE_MASK,
1468 OMAP2420_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_EN_SHIFT,
1469 NULL, sys_clkout_src_parent_names, gpt1_fck_ops);
1470
1471DEFINE_CLK_DIVIDER(sys_clkout, "sys_clkout_src", &sys_clkout_src, 0x0,
1472 OMAP2420_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_DIV_SHIFT,
1473 OMAP24XX_CLKOUT_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
1474
1475DEFINE_CLK_OMAP_MUX_GATE(sys_clkout2_src, "wkup_clkdm",
1476 common_clkout_src_clksel, OMAP2420_PRCM_CLKOUT_CTRL,
1477 OMAP2420_CLKOUT2_SOURCE_MASK,
1478 OMAP2420_PRCM_CLKOUT_CTRL, OMAP2420_CLKOUT2_EN_SHIFT,
1479 NULL, sys_clkout_src_parent_names, gpt1_fck_ops);
1480
1481DEFINE_CLK_DIVIDER(sys_clkout2, "sys_clkout2_src", &sys_clkout2_src, 0x0,
1482 OMAP2420_PRCM_CLKOUT_CTRL, OMAP2420_CLKOUT2_DIV_SHIFT,
1483 OMAP2420_CLKOUT2_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
1484
1485static struct clk uart1_fck;
1486
1487static struct clk_hw_omap uart1_fck_hw = {
1488 .hw = {
1489 .clk = &uart1_fck,
1490 },
1491 .ops = &clkhwops_wait,
1492 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1493 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
1494 .clkdm_name = "core_l4_clkdm",
1495};
1496
1497DEFINE_STRUCT_CLK(uart1_fck, mcspi1_fck_parent_names, aes_ick_ops);
1498
1499static struct clk uart1_ick;
1500
1501static struct clk_hw_omap uart1_ick_hw = {
1502 .hw = {
1503 .clk = &uart1_ick,
1504 },
1505 .ops = &clkhwops_iclk_wait,
1506 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1507 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
1508 .clkdm_name = "core_l4_clkdm",
1509};
1510
1511DEFINE_STRUCT_CLK(uart1_ick, aes_ick_parent_names, aes_ick_ops);
1512
1513static struct clk uart2_fck;
1514
1515static struct clk_hw_omap uart2_fck_hw = {
1516 .hw = {
1517 .clk = &uart2_fck,
1518 },
1519 .ops = &clkhwops_wait,
1520 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1521 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
1522 .clkdm_name = "core_l4_clkdm",
1523};
1524
1525DEFINE_STRUCT_CLK(uart2_fck, mcspi1_fck_parent_names, aes_ick_ops);
1526
1527static struct clk uart2_ick;
1528
1529static struct clk_hw_omap uart2_ick_hw = {
1530 .hw = {
1531 .clk = &uart2_ick,
1532 },
1533 .ops = &clkhwops_iclk_wait,
1534 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1535 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
1536 .clkdm_name = "core_l4_clkdm",
1537};
1538
1539DEFINE_STRUCT_CLK(uart2_ick, aes_ick_parent_names, aes_ick_ops);
1540
1541static struct clk uart3_fck;
1542
1543static struct clk_hw_omap uart3_fck_hw = {
1544 .hw = {
1545 .clk = &uart3_fck,
1546 },
1547 .ops = &clkhwops_wait,
1548 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1549 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
1550 .clkdm_name = "core_l4_clkdm",
1551};
1552
1553DEFINE_STRUCT_CLK(uart3_fck, mcspi1_fck_parent_names, aes_ick_ops);
1554
1555static struct clk uart3_ick;
1556
1557static struct clk_hw_omap uart3_ick_hw = {
1558 .hw = {
1559 .clk = &uart3_ick,
1560 },
1561 .ops = &clkhwops_iclk_wait,
1562 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1563 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
1564 .clkdm_name = "core_l4_clkdm",
1565};
1566
1567DEFINE_STRUCT_CLK(uart3_ick, aes_ick_parent_names, aes_ick_ops);
1568
1569static struct clk usb_fck;
1570
1571static struct clk_hw_omap usb_fck_hw = {
1572 .hw = {
1573 .clk = &usb_fck,
1574 },
1575 .ops = &clkhwops_wait,
1576 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1577 .enable_bit = OMAP24XX_EN_USB_SHIFT,
1578 .clkdm_name = "core_l3_clkdm",
1579};
1580
1581DEFINE_STRUCT_CLK(usb_fck, mcspi1_fck_parent_names, aes_ick_ops);
1582
1583static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
1584 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1585 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1586 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1587 { .div = 0 }
1588};
1589
1590static const struct clksel usb_l4_ick_clksel[] = {
1591 { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
1592 { .parent = NULL },
1593};
1594
1595static const char *usb_l4_ick_parent_names[] = {
1596 "core_l3_ck",
1597};
1598
1599DEFINE_CLK_OMAP_MUX_GATE(usb_l4_ick, "core_l4_clkdm", usb_l4_ick_clksel,
1600 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1601 OMAP24XX_CLKSEL_USB_MASK,
1602 OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1603 OMAP24XX_EN_USB_SHIFT, &clkhwops_iclk_wait,
1604 usb_l4_ick_parent_names, dsp_fck_ops);
1605
1606static struct clk virt_prcm_set;
1607
1608static const char *virt_prcm_set_parent_names[] = {
1609 "mpu_ck",
1610};
1611
1612static const struct clk_ops virt_prcm_set_ops = {
1613 .recalc_rate = &omap2_table_mpu_recalc,
1614 .set_rate = &omap2_select_table_rate,
1615 .round_rate = &omap2_round_to_table_rate,
1616};
1617
1618DEFINE_STRUCT_CLK_HW_OMAP(virt_prcm_set, NULL);
1619DEFINE_STRUCT_CLK(virt_prcm_set, virt_prcm_set_parent_names, virt_prcm_set_ops);
1620
1621static const struct clksel_rate vlynq_fck_96m_rates[] = {
1622 { .div = 1, .val = 0, .flags = RATE_IN_242X },
1623 { .div = 0 }
1624};
1625
1626static const struct clksel_rate vlynq_fck_core_rates[] = {
1627 { .div = 1, .val = 1, .flags = RATE_IN_242X },
1628 { .div = 2, .val = 2, .flags = RATE_IN_242X },
1629 { .div = 3, .val = 3, .flags = RATE_IN_242X },
1630 { .div = 4, .val = 4, .flags = RATE_IN_242X },
1631 { .div = 6, .val = 6, .flags = RATE_IN_242X },
1632 { .div = 8, .val = 8, .flags = RATE_IN_242X },
1633 { .div = 9, .val = 9, .flags = RATE_IN_242X },
1634 { .div = 12, .val = 12, .flags = RATE_IN_242X },
1635 { .div = 16, .val = 16, .flags = RATE_IN_242X },
1636 { .div = 18, .val = 18, .flags = RATE_IN_242X },
1637 { .div = 0 }
1638};
1639
1640static const struct clksel vlynq_fck_clksel[] = {
1641 { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates },
1642 { .parent = &core_ck, .rates = vlynq_fck_core_rates },
1643 { .parent = NULL },
1644};
1645
1646static const char *vlynq_fck_parent_names[] = {
1647 "func_96m_ck", "core_ck",
1648};
1649
1650DEFINE_CLK_OMAP_MUX_GATE(vlynq_fck, "core_l3_clkdm", vlynq_fck_clksel,
1651 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1652 OMAP2420_CLKSEL_VLYNQ_MASK,
1653 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1654 OMAP2420_EN_VLYNQ_SHIFT, &clkhwops_wait,
1655 vlynq_fck_parent_names, dss1_fck_ops);
1656
1657static struct clk vlynq_ick;
1658
1659static struct clk_hw_omap vlynq_ick_hw = {
1660 .hw = {
1661 .clk = &vlynq_ick,
1662 },
1663 .ops = &clkhwops_iclk_wait,
1664 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1665 .enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
1666 .clkdm_name = "core_l3_clkdm",
1667};
1668
1669DEFINE_STRUCT_CLK(vlynq_ick, gfx_ick_parent_names, aes_ick_ops);
1670
1671static struct clk wdt1_ick;
1672
1673static struct clk_hw_omap wdt1_ick_hw = {
1674 .hw = {
1675 .clk = &wdt1_ick,
1676 },
1677 .ops = &clkhwops_iclk_wait,
1678 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1679 .enable_bit = OMAP24XX_EN_WDT1_SHIFT,
1680 .clkdm_name = "wkup_clkdm",
1681};
1682
1683DEFINE_STRUCT_CLK(wdt1_ick, gpios_ick_parent_names, aes_ick_ops);
1684
1685static struct clk wdt1_osc_ck;
1686
1687static const struct clk_ops wdt1_osc_ck_ops = {};
1688
1689DEFINE_STRUCT_CLK_HW_OMAP(wdt1_osc_ck, NULL);
1690DEFINE_STRUCT_CLK(wdt1_osc_ck, sys_ck_parent_names, wdt1_osc_ck_ops);
1691
1692static struct clk wdt3_fck;
1693
1694static struct clk_hw_omap wdt3_fck_hw = {
1695 .hw = {
1696 .clk = &wdt3_fck,
1697 },
1698 .ops = &clkhwops_wait,
1699 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1700 .enable_bit = OMAP2420_EN_WDT3_SHIFT,
1701 .clkdm_name = "core_l4_clkdm",
1702};
1703
1704DEFINE_STRUCT_CLK(wdt3_fck, gpios_fck_parent_names, aes_ick_ops);
1705
1706static struct clk wdt3_ick;
1707
1708static struct clk_hw_omap wdt3_ick_hw = {
1709 .hw = {
1710 .clk = &wdt3_ick,
1711 },
1712 .ops = &clkhwops_iclk_wait,
1713 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1714 .enable_bit = OMAP2420_EN_WDT3_SHIFT,
1715 .clkdm_name = "core_l4_clkdm",
1716};
1717
1718DEFINE_STRUCT_CLK(wdt3_ick, aes_ick_parent_names, aes_ick_ops);
1719
1720static struct clk wdt4_fck;
1721
1722static struct clk_hw_omap wdt4_fck_hw = {
1723 .hw = {
1724 .clk = &wdt4_fck,
1725 },
1726 .ops = &clkhwops_wait,
1727 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1728 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
1729 .clkdm_name = "core_l4_clkdm",
1730};
1731
1732DEFINE_STRUCT_CLK(wdt4_fck, gpios_fck_parent_names, aes_ick_ops);
1733
1734static struct clk wdt4_ick;
1735
1736static struct clk_hw_omap wdt4_ick_hw = {
1737 .hw = {
1738 .clk = &wdt4_ick,
1739 },
1740 .ops = &clkhwops_iclk_wait,
1741 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1742 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
1743 .clkdm_name = "core_l4_clkdm",
1744};
1745
1746DEFINE_STRUCT_CLK(wdt4_ick, aes_ick_parent_names, aes_ick_ops);
1747
1748/*
1749 * clkdev integration
1750 */
1751
1752static struct omap_clk omap2420_clks[] = {
1753 /* external root sources */
1754 CLK(NULL, "func_32k_ck", &func_32k_ck, CK_242X),
1755 CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_242X),
1756 CLK(NULL, "osc_ck", &osc_ck, CK_242X),
1757 CLK(NULL, "sys_ck", &sys_ck, CK_242X),
1758 CLK(NULL, "alt_ck", &alt_ck, CK_242X),
1759 CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_242X),
1760 /* internal analog sources */
1761 CLK(NULL, "dpll_ck", &dpll_ck, CK_242X),
1762 CLK(NULL, "apll96_ck", &apll96_ck, CK_242X),
1763 CLK(NULL, "apll54_ck", &apll54_ck, CK_242X),
1764 /* internal prcm root sources */
1765 CLK(NULL, "func_54m_ck", &func_54m_ck, CK_242X),
1766 CLK(NULL, "core_ck", &core_ck, CK_242X),
1767 CLK(NULL, "func_96m_ck", &func_96m_ck, CK_242X),
1768 CLK(NULL, "func_48m_ck", &func_48m_ck, CK_242X),
1769 CLK(NULL, "func_12m_ck", &func_12m_ck, CK_242X),
1770 CLK(NULL, "ck_wdt1_osc", &wdt1_osc_ck, CK_242X),
1771 CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_242X),
1772 CLK(NULL, "sys_clkout", &sys_clkout, CK_242X),
1773 CLK(NULL, "sys_clkout2_src", &sys_clkout2_src, CK_242X),
1774 CLK(NULL, "sys_clkout2", &sys_clkout2, CK_242X),
1775 CLK(NULL, "emul_ck", &emul_ck, CK_242X),
1776 /* mpu domain clocks */
1777 CLK(NULL, "mpu_ck", &mpu_ck, CK_242X),
1778 /* dsp domain clocks */
1779 CLK(NULL, "dsp_fck", &dsp_fck, CK_242X),
1780 CLK(NULL, "dsp_ick", &dsp_ick, CK_242X),
1781 CLK(NULL, "iva1_ifck", &iva1_ifck, CK_242X),
1782 CLK(NULL, "iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X),
1783 /* GFX domain clocks */
1784 CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_242X),
1785 CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_242X),
1786 CLK(NULL, "gfx_ick", &gfx_ick, CK_242X),
1787 /* DSS domain clocks */
1788 CLK("omapdss_dss", "ick", &dss_ick, CK_242X),
1789 CLK(NULL, "dss_ick", &dss_ick, CK_242X),
1790 CLK(NULL, "dss1_fck", &dss1_fck, CK_242X),
1791 CLK(NULL, "dss2_fck", &dss2_fck, CK_242X),
1792 CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_242X),
1793 /* L3 domain clocks */
1794 CLK(NULL, "core_l3_ck", &core_l3_ck, CK_242X),
1795 CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_242X),
1796 CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_242X),
1797 /* L4 domain clocks */
1798 CLK(NULL, "l4_ck", &l4_ck, CK_242X),
1799 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_242X),
1800 CLK(NULL, "wu_l4_ick", &wu_l4_ick, CK_242X),
1801 /* virtual meta-group clock */
1802 CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_242X),
1803 /* general l4 interface ck, multi-parent functional clk */
1804 CLK(NULL, "gpt1_ick", &gpt1_ick, CK_242X),
1805 CLK(NULL, "gpt1_fck", &gpt1_fck, CK_242X),
1806 CLK(NULL, "gpt2_ick", &gpt2_ick, CK_242X),
1807 CLK(NULL, "gpt2_fck", &gpt2_fck, CK_242X),
1808 CLK(NULL, "gpt3_ick", &gpt3_ick, CK_242X),
1809 CLK(NULL, "gpt3_fck", &gpt3_fck, CK_242X),
1810 CLK(NULL, "gpt4_ick", &gpt4_ick, CK_242X),
1811 CLK(NULL, "gpt4_fck", &gpt4_fck, CK_242X),
1812 CLK(NULL, "gpt5_ick", &gpt5_ick, CK_242X),
1813 CLK(NULL, "gpt5_fck", &gpt5_fck, CK_242X),
1814 CLK(NULL, "gpt6_ick", &gpt6_ick, CK_242X),
1815 CLK(NULL, "gpt6_fck", &gpt6_fck, CK_242X),
1816 CLK(NULL, "gpt7_ick", &gpt7_ick, CK_242X),
1817 CLK(NULL, "gpt7_fck", &gpt7_fck, CK_242X),
1818 CLK(NULL, "gpt8_ick", &gpt8_ick, CK_242X),
1819 CLK(NULL, "gpt8_fck", &gpt8_fck, CK_242X),
1820 CLK(NULL, "gpt9_ick", &gpt9_ick, CK_242X),
1821 CLK(NULL, "gpt9_fck", &gpt9_fck, CK_242X),
1822 CLK(NULL, "gpt10_ick", &gpt10_ick, CK_242X),
1823 CLK(NULL, "gpt10_fck", &gpt10_fck, CK_242X),
1824 CLK(NULL, "gpt11_ick", &gpt11_ick, CK_242X),
1825 CLK(NULL, "gpt11_fck", &gpt11_fck, CK_242X),
1826 CLK(NULL, "gpt12_ick", &gpt12_ick, CK_242X),
1827 CLK(NULL, "gpt12_fck", &gpt12_fck, CK_242X),
1828 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_242X),
1829 CLK(NULL, "mcbsp1_ick", &mcbsp1_ick, CK_242X),
1830 CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_242X),
1831 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_242X),
1832 CLK(NULL, "mcbsp2_ick", &mcbsp2_ick, CK_242X),
1833 CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_242X),
1834 CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_242X),
1835 CLK(NULL, "mcspi1_ick", &mcspi1_ick, CK_242X),
1836 CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_242X),
1837 CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_242X),
1838 CLK(NULL, "mcspi2_ick", &mcspi2_ick, CK_242X),
1839 CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_242X),
1840 CLK(NULL, "uart1_ick", &uart1_ick, CK_242X),
1841 CLK(NULL, "uart1_fck", &uart1_fck, CK_242X),
1842 CLK(NULL, "uart2_ick", &uart2_ick, CK_242X),
1843 CLK(NULL, "uart2_fck", &uart2_fck, CK_242X),
1844 CLK(NULL, "uart3_ick", &uart3_ick, CK_242X),
1845 CLK(NULL, "uart3_fck", &uart3_fck, CK_242X),
1846 CLK(NULL, "gpios_ick", &gpios_ick, CK_242X),
1847 CLK(NULL, "gpios_fck", &gpios_fck, CK_242X),
1848 CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_242X),
1849 CLK(NULL, "mpu_wdt_ick", &mpu_wdt_ick, CK_242X),
1850 CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck, CK_242X),
1851 CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_242X),
1852 CLK(NULL, "wdt1_ick", &wdt1_ick, CK_242X),
1853 CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_242X),
1854 CLK("omap24xxcam", "fck", &cam_fck, CK_242X),
1855 CLK(NULL, "cam_fck", &cam_fck, CK_242X),
1856 CLK("omap24xxcam", "ick", &cam_ick, CK_242X),
1857 CLK(NULL, "cam_ick", &cam_ick, CK_242X),
1858 CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_242X),
1859 CLK(NULL, "wdt4_ick", &wdt4_ick, CK_242X),
1860 CLK(NULL, "wdt4_fck", &wdt4_fck, CK_242X),
1861 CLK(NULL, "wdt3_ick", &wdt3_ick, CK_242X),
1862 CLK(NULL, "wdt3_fck", &wdt3_fck, CK_242X),
1863 CLK(NULL, "mspro_ick", &mspro_ick, CK_242X),
1864 CLK(NULL, "mspro_fck", &mspro_fck, CK_242X),
1865 CLK("mmci-omap.0", "ick", &mmc_ick, CK_242X),
1866 CLK(NULL, "mmc_ick", &mmc_ick, CK_242X),
1867 CLK("mmci-omap.0", "fck", &mmc_fck, CK_242X),
1868 CLK(NULL, "mmc_fck", &mmc_fck, CK_242X),
1869 CLK(NULL, "fac_ick", &fac_ick, CK_242X),
1870 CLK(NULL, "fac_fck", &fac_fck, CK_242X),
1871 CLK(NULL, "eac_ick", &eac_ick, CK_242X),
1872 CLK(NULL, "eac_fck", &eac_fck, CK_242X),
1873 CLK("omap_hdq.0", "ick", &hdq_ick, CK_242X),
1874 CLK(NULL, "hdq_ick", &hdq_ick, CK_242X),
1875 CLK("omap_hdq.0", "fck", &hdq_fck, CK_242X),
1876 CLK(NULL, "hdq_fck", &hdq_fck, CK_242X),
1877 CLK("omap_i2c.1", "ick", &i2c1_ick, CK_242X),
1878 CLK(NULL, "i2c1_ick", &i2c1_ick, CK_242X),
1879 CLK(NULL, "i2c1_fck", &i2c1_fck, CK_242X),
1880 CLK("omap_i2c.2", "ick", &i2c2_ick, CK_242X),
1881 CLK(NULL, "i2c2_ick", &i2c2_ick, CK_242X),
1882 CLK(NULL, "i2c2_fck", &i2c2_fck, CK_242X),
1883 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_242X),
1884 CLK(NULL, "sdma_fck", &sdma_fck, CK_242X),
1885 CLK(NULL, "sdma_ick", &sdma_ick, CK_242X),
1886 CLK(NULL, "sdrc_ick", &sdrc_ick, CK_242X),
1887 CLK(NULL, "vlynq_ick", &vlynq_ick, CK_242X),
1888 CLK(NULL, "vlynq_fck", &vlynq_fck, CK_242X),
1889 CLK(NULL, "des_ick", &des_ick, CK_242X),
1890 CLK("omap-sham", "ick", &sha_ick, CK_242X),
1891 CLK(NULL, "sha_ick", &sha_ick, CK_242X),
1892 CLK("omap_rng", "ick", &rng_ick, CK_242X),
1893 CLK(NULL, "rng_ick", &rng_ick, CK_242X),
1894 CLK("omap-aes", "ick", &aes_ick, CK_242X),
1895 CLK(NULL, "aes_ick", &aes_ick, CK_242X),
1896 CLK(NULL, "pka_ick", &pka_ick, CK_242X),
1897 CLK(NULL, "usb_fck", &usb_fck, CK_242X),
1898 CLK("musb-hdrc", "fck", &osc_ck, CK_242X),
1899 CLK(NULL, "timer_32k_ck", &func_32k_ck, CK_242X),
1900 CLK(NULL, "timer_sys_ck", &sys_ck, CK_242X),
1901 CLK(NULL, "timer_ext_ck", &alt_ck, CK_242X),
1902 CLK(NULL, "cpufreq_ck", &virt_prcm_set, CK_242X),
1903};
1904
1905
1906static const char *enable_init_clks[] = {
1907 "apll96_ck",
1908 "apll54_ck",
1909 "sync_32k_ick",
1910 "omapctrl_ick",
1911 "gpmc_fck",
1912 "sdrc_ick",
1913};
1914
1915/*
1916 * init code
1917 */
1918
1919int __init omap2420_clk_init(void)
1920{
1921 struct omap_clk *c;
1922
1923 prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL;
1924 cpu_mask = RATE_IN_242X;
1925 rate_table = omap2420_rate_table;
1926
1927 omap2xxx_clkt_dpllcore_init(&dpll_ck_hw.hw);
1928
1929 omap2xxx_clkt_vps_check_bootloader_rates();
1930
1931 for (c = omap2420_clks; c < omap2420_clks + ARRAY_SIZE(omap2420_clks);
1932 c++) {
1933 clkdev_add(&c->lk);
1934 if (!__clk_init(NULL, c->lk.clk))
1935 omap2_init_clk_hw_omap_clocks(c->lk.clk);
1936 }
1937
1938 omap2_clk_disable_autoidle_all();
1939
1940 omap2_clk_enable_init_clocks(enable_init_clks,
1941 ARRAY_SIZE(enable_init_clks));
1942
1943 pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n",
1944 (clk_get_rate(&sys_ck) / 1000000),
1945 (clk_get_rate(&sys_ck) / 100000) % 10,
1946 (clk_get_rate(&dpll_ck) / 1000000),
1947 (clk_get_rate(&mpu_ck) / 1000000));
1948
1949 return 0;
1950}
diff --git a/arch/arm/mach-omap2/cclock2430_data.c b/arch/arm/mach-omap2/cclock2430_data.c
new file mode 100644
index 000000000000..eda079b96c6a
--- /dev/null
+++ b/arch/arm/mach-omap2/cclock2430_data.c
@@ -0,0 +1,2065 @@
1/*
2 * OMAP2430 clock data
3 *
4 * Copyright (C) 2005-2009, 2012 Texas Instruments, Inc.
5 * Copyright (C) 2004-2011 Nokia Corporation
6 *
7 * Contacts:
8 * Richard Woodruff <r-woodruff2@ti.com>
9 * Paul Walmsley
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#include <linux/kernel.h>
17#include <linux/clk.h>
18#include <linux/clk-private.h>
19#include <linux/list.h>
20
21#include "soc.h"
22#include "iomap.h"
23#include "clock.h"
24#include "clock2xxx.h"
25#include "opp2xxx.h"
26#include "cm2xxx.h"
27#include "prm2xxx.h"
28#include "prm-regbits-24xx.h"
29#include "cm-regbits-24xx.h"
30#include "sdrc.h"
31#include "control.h"
32
33#define OMAP_CM_REGADDR OMAP2430_CM_REGADDR
34
35/*
36 * 2430 clock tree.
37 *
38 * NOTE:In many cases here we are assigning a 'default' parent. In
39 * many cases the parent is selectable. The set parent calls will
40 * also switch sources.
41 *
42 * Several sources are given initial rates which may be wrong, this will
43 * be fixed up in the init func.
44 *
45 * Things are broadly separated below by clock domains. It is
46 * noteworthy that most peripherals have dependencies on multiple clock
47 * domains. Many get their interface clocks from the L4 domain, but get
48 * functional clocks from fixed sources or other core domain derived
49 * clocks.
50 */
51
52DEFINE_CLK_FIXED_RATE(alt_ck, CLK_IS_ROOT, 54000000, 0x0);
53
54DEFINE_CLK_FIXED_RATE(func_32k_ck, CLK_IS_ROOT, 32768, 0x0);
55
56DEFINE_CLK_FIXED_RATE(mcbsp_clks, CLK_IS_ROOT, 0x0, 0x0);
57
58static struct clk osc_ck;
59
60static const struct clk_ops osc_ck_ops = {
61 .enable = &omap2_enable_osc_ck,
62 .disable = omap2_disable_osc_ck,
63 .recalc_rate = &omap2_osc_clk_recalc,
64};
65
66static struct clk_hw_omap osc_ck_hw = {
67 .hw = {
68 .clk = &osc_ck,
69 },
70};
71
72static struct clk osc_ck = {
73 .name = "osc_ck",
74 .ops = &osc_ck_ops,
75 .hw = &osc_ck_hw.hw,
76 .flags = CLK_IS_ROOT,
77};
78
79DEFINE_CLK_FIXED_RATE(secure_32k_ck, CLK_IS_ROOT, 32768, 0x0);
80
81static struct clk sys_ck;
82
83static const char *sys_ck_parent_names[] = {
84 "osc_ck",
85};
86
87static const struct clk_ops sys_ck_ops = {
88 .init = &omap2_init_clk_clkdm,
89 .recalc_rate = &omap2xxx_sys_clk_recalc,
90};
91
92DEFINE_STRUCT_CLK_HW_OMAP(sys_ck, "wkup_clkdm");
93DEFINE_STRUCT_CLK(sys_ck, sys_ck_parent_names, sys_ck_ops);
94
95static struct dpll_data dpll_dd = {
96 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
97 .mult_mask = OMAP24XX_DPLL_MULT_MASK,
98 .div1_mask = OMAP24XX_DPLL_DIV_MASK,
99 .clk_bypass = &sys_ck,
100 .clk_ref = &sys_ck,
101 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
102 .enable_mask = OMAP24XX_EN_DPLL_MASK,
103 .max_multiplier = 1023,
104 .min_divider = 1,
105 .max_divider = 16,
106};
107
108static struct clk dpll_ck;
109
110static const char *dpll_ck_parent_names[] = {
111 "sys_ck",
112};
113
114static const struct clk_ops dpll_ck_ops = {
115 .init = &omap2_init_clk_clkdm,
116 .get_parent = &omap2_init_dpll_parent,
117 .recalc_rate = &omap2_dpllcore_recalc,
118 .round_rate = &omap2_dpll_round_rate,
119 .set_rate = &omap2_reprogram_dpllcore,
120};
121
122static struct clk_hw_omap dpll_ck_hw = {
123 .hw = {
124 .clk = &dpll_ck,
125 },
126 .ops = &clkhwops_omap2xxx_dpll,
127 .dpll_data = &dpll_dd,
128 .clkdm_name = "wkup_clkdm",
129};
130
131DEFINE_STRUCT_CLK(dpll_ck, dpll_ck_parent_names, dpll_ck_ops);
132
133static struct clk core_ck;
134
135static const char *core_ck_parent_names[] = {
136 "dpll_ck",
137};
138
139static const struct clk_ops core_ck_ops = {
140 .init = &omap2_init_clk_clkdm,
141};
142
143DEFINE_STRUCT_CLK_HW_OMAP(core_ck, "wkup_clkdm");
144DEFINE_STRUCT_CLK(core_ck, core_ck_parent_names, core_ck_ops);
145
146DEFINE_CLK_DIVIDER(core_l3_ck, "core_ck", &core_ck, 0x0,
147 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
148 OMAP24XX_CLKSEL_L3_SHIFT, OMAP24XX_CLKSEL_L3_WIDTH,
149 CLK_DIVIDER_ONE_BASED, NULL);
150
151DEFINE_CLK_DIVIDER(l4_ck, "core_l3_ck", &core_l3_ck, 0x0,
152 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
153 OMAP24XX_CLKSEL_L4_SHIFT, OMAP24XX_CLKSEL_L4_WIDTH,
154 CLK_DIVIDER_ONE_BASED, NULL);
155
156static struct clk aes_ick;
157
158static const char *aes_ick_parent_names[] = {
159 "l4_ck",
160};
161
162static const struct clk_ops aes_ick_ops = {
163 .init = &omap2_init_clk_clkdm,
164 .enable = &omap2_dflt_clk_enable,
165 .disable = &omap2_dflt_clk_disable,
166 .is_enabled = &omap2_dflt_clk_is_enabled,
167};
168
169static struct clk_hw_omap aes_ick_hw = {
170 .hw = {
171 .clk = &aes_ick,
172 },
173 .ops = &clkhwops_iclk_wait,
174 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
175 .enable_bit = OMAP24XX_EN_AES_SHIFT,
176 .clkdm_name = "core_l4_clkdm",
177};
178
179DEFINE_STRUCT_CLK(aes_ick, aes_ick_parent_names, aes_ick_ops);
180
181static struct clk apll54_ck;
182
183static const struct clk_ops apll54_ck_ops = {
184 .init = &omap2_init_clk_clkdm,
185 .enable = &omap2_clk_apll54_enable,
186 .disable = &omap2_clk_apll54_disable,
187 .recalc_rate = &omap2_clk_apll54_recalc,
188};
189
190static struct clk_hw_omap apll54_ck_hw = {
191 .hw = {
192 .clk = &apll54_ck,
193 },
194 .ops = &clkhwops_apll54,
195 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
196 .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT,
197 .flags = ENABLE_ON_INIT,
198 .clkdm_name = "wkup_clkdm",
199};
200
201DEFINE_STRUCT_CLK(apll54_ck, dpll_ck_parent_names, apll54_ck_ops);
202
203static struct clk apll96_ck;
204
205static const struct clk_ops apll96_ck_ops = {
206 .init = &omap2_init_clk_clkdm,
207 .enable = &omap2_clk_apll96_enable,
208 .disable = &omap2_clk_apll96_disable,
209 .recalc_rate = &omap2_clk_apll96_recalc,
210};
211
212static struct clk_hw_omap apll96_ck_hw = {
213 .hw = {
214 .clk = &apll96_ck,
215 },
216 .ops = &clkhwops_apll96,
217 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
218 .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT,
219 .flags = ENABLE_ON_INIT,
220 .clkdm_name = "wkup_clkdm",
221};
222
223DEFINE_STRUCT_CLK(apll96_ck, dpll_ck_parent_names, apll96_ck_ops);
224
225static const char *func_96m_ck_parent_names[] = {
226 "apll96_ck", "alt_ck",
227};
228
229DEFINE_CLK_MUX(func_96m_ck, func_96m_ck_parent_names, NULL, 0x0,
230 OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), OMAP2430_96M_SOURCE_SHIFT,
231 OMAP2430_96M_SOURCE_WIDTH, 0x0, NULL);
232
233static struct clk cam_fck;
234
235static const char *cam_fck_parent_names[] = {
236 "func_96m_ck",
237};
238
239static struct clk_hw_omap cam_fck_hw = {
240 .hw = {
241 .clk = &cam_fck,
242 },
243 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
244 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
245 .clkdm_name = "core_l3_clkdm",
246};
247
248DEFINE_STRUCT_CLK(cam_fck, cam_fck_parent_names, aes_ick_ops);
249
250static struct clk cam_ick;
251
252static struct clk_hw_omap cam_ick_hw = {
253 .hw = {
254 .clk = &cam_ick,
255 },
256 .ops = &clkhwops_iclk,
257 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
258 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
259 .clkdm_name = "core_l4_clkdm",
260};
261
262DEFINE_STRUCT_CLK(cam_ick, aes_ick_parent_names, aes_ick_ops);
263
264static struct clk des_ick;
265
266static struct clk_hw_omap des_ick_hw = {
267 .hw = {
268 .clk = &des_ick,
269 },
270 .ops = &clkhwops_iclk_wait,
271 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
272 .enable_bit = OMAP24XX_EN_DES_SHIFT,
273 .clkdm_name = "core_l4_clkdm",
274};
275
276DEFINE_STRUCT_CLK(des_ick, aes_ick_parent_names, aes_ick_ops);
277
278static const struct clksel_rate dsp_fck_core_rates[] = {
279 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
280 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
281 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
282 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
283 { .div = 0 }
284};
285
286static const struct clksel dsp_fck_clksel[] = {
287 { .parent = &core_ck, .rates = dsp_fck_core_rates },
288 { .parent = NULL },
289};
290
291static const char *dsp_fck_parent_names[] = {
292 "core_ck",
293};
294
295static struct clk dsp_fck;
296
297static const struct clk_ops dsp_fck_ops = {
298 .init = &omap2_init_clk_clkdm,
299 .enable = &omap2_dflt_clk_enable,
300 .disable = &omap2_dflt_clk_disable,
301 .is_enabled = &omap2_dflt_clk_is_enabled,
302 .recalc_rate = &omap2_clksel_recalc,
303 .set_rate = &omap2_clksel_set_rate,
304 .round_rate = &omap2_clksel_round_rate,
305};
306
307DEFINE_CLK_OMAP_MUX_GATE(dsp_fck, "dsp_clkdm", dsp_fck_clksel,
308 OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
309 OMAP24XX_CLKSEL_DSP_MASK,
310 OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
311 OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, &clkhwops_wait,
312 dsp_fck_parent_names, dsp_fck_ops);
313
314static const struct clksel_rate dss1_fck_sys_rates[] = {
315 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
316 { .div = 0 }
317};
318
319static const struct clksel_rate dss1_fck_core_rates[] = {
320 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
321 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
322 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
323 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
324 { .div = 5, .val = 5, .flags = RATE_IN_24XX },
325 { .div = 6, .val = 6, .flags = RATE_IN_24XX },
326 { .div = 8, .val = 8, .flags = RATE_IN_24XX },
327 { .div = 9, .val = 9, .flags = RATE_IN_24XX },
328 { .div = 12, .val = 12, .flags = RATE_IN_24XX },
329 { .div = 16, .val = 16, .flags = RATE_IN_24XX },
330 { .div = 0 }
331};
332
333static const struct clksel dss1_fck_clksel[] = {
334 { .parent = &sys_ck, .rates = dss1_fck_sys_rates },
335 { .parent = &core_ck, .rates = dss1_fck_core_rates },
336 { .parent = NULL },
337};
338
339static const char *dss1_fck_parent_names[] = {
340 "sys_ck", "core_ck",
341};
342
343static const struct clk_ops dss1_fck_ops = {
344 .init = &omap2_init_clk_clkdm,
345 .enable = &omap2_dflt_clk_enable,
346 .disable = &omap2_dflt_clk_disable,
347 .is_enabled = &omap2_dflt_clk_is_enabled,
348 .recalc_rate = &omap2_clksel_recalc,
349 .get_parent = &omap2_clksel_find_parent_index,
350 .set_parent = &omap2_clksel_set_parent,
351};
352
353DEFINE_CLK_OMAP_MUX_GATE(dss1_fck, "dss_clkdm", dss1_fck_clksel,
354 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
355 OMAP24XX_CLKSEL_DSS1_MASK,
356 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
357 OMAP24XX_EN_DSS1_SHIFT, NULL,
358 dss1_fck_parent_names, dss1_fck_ops);
359
360static const struct clksel_rate dss2_fck_sys_rates[] = {
361 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
362 { .div = 0 }
363};
364
365static const struct clksel_rate dss2_fck_48m_rates[] = {
366 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
367 { .div = 0 }
368};
369
370static const struct clksel_rate func_48m_apll96_rates[] = {
371 { .div = 2, .val = 0, .flags = RATE_IN_24XX },
372 { .div = 0 }
373};
374
375static const struct clksel_rate func_48m_alt_rates[] = {
376 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
377 { .div = 0 }
378};
379
380static const struct clksel func_48m_clksel[] = {
381 { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
382 { .parent = &alt_ck, .rates = func_48m_alt_rates },
383 { .parent = NULL },
384};
385
386static const char *func_48m_ck_parent_names[] = {
387 "apll96_ck", "alt_ck",
388};
389
390static struct clk func_48m_ck;
391
392static const struct clk_ops func_48m_ck_ops = {
393 .init = &omap2_init_clk_clkdm,
394 .recalc_rate = &omap2_clksel_recalc,
395 .set_rate = &omap2_clksel_set_rate,
396 .round_rate = &omap2_clksel_round_rate,
397 .get_parent = &omap2_clksel_find_parent_index,
398 .set_parent = &omap2_clksel_set_parent,
399};
400
401static struct clk_hw_omap func_48m_ck_hw = {
402 .hw = {
403 .clk = &func_48m_ck,
404 },
405 .clksel = func_48m_clksel,
406 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
407 .clksel_mask = OMAP24XX_48M_SOURCE_MASK,
408 .clkdm_name = "wkup_clkdm",
409};
410
411DEFINE_STRUCT_CLK(func_48m_ck, func_48m_ck_parent_names, func_48m_ck_ops);
412
413static const struct clksel dss2_fck_clksel[] = {
414 { .parent = &sys_ck, .rates = dss2_fck_sys_rates },
415 { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
416 { .parent = NULL },
417};
418
419static const char *dss2_fck_parent_names[] = {
420 "sys_ck", "func_48m_ck",
421};
422
423DEFINE_CLK_OMAP_MUX_GATE(dss2_fck, "dss_clkdm", dss2_fck_clksel,
424 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
425 OMAP24XX_CLKSEL_DSS2_MASK,
426 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
427 OMAP24XX_EN_DSS2_SHIFT, NULL,
428 dss2_fck_parent_names, dss1_fck_ops);
429
430static const char *func_54m_ck_parent_names[] = {
431 "apll54_ck", "alt_ck",
432};
433
434DEFINE_CLK_MUX(func_54m_ck, func_54m_ck_parent_names, NULL, 0x0,
435 OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
436 OMAP24XX_54M_SOURCE_SHIFT, OMAP24XX_54M_SOURCE_WIDTH, 0x0, NULL);
437
438static struct clk dss_54m_fck;
439
440static const char *dss_54m_fck_parent_names[] = {
441 "func_54m_ck",
442};
443
444static struct clk_hw_omap dss_54m_fck_hw = {
445 .hw = {
446 .clk = &dss_54m_fck,
447 },
448 .ops = &clkhwops_wait,
449 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
450 .enable_bit = OMAP24XX_EN_TV_SHIFT,
451 .clkdm_name = "dss_clkdm",
452};
453
454DEFINE_STRUCT_CLK(dss_54m_fck, dss_54m_fck_parent_names, aes_ick_ops);
455
456static struct clk dss_ick;
457
458static struct clk_hw_omap dss_ick_hw = {
459 .hw = {
460 .clk = &dss_ick,
461 },
462 .ops = &clkhwops_iclk,
463 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
464 .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
465 .clkdm_name = "dss_clkdm",
466};
467
468DEFINE_STRUCT_CLK(dss_ick, aes_ick_parent_names, aes_ick_ops);
469
470static struct clk emul_ck;
471
472static struct clk_hw_omap emul_ck_hw = {
473 .hw = {
474 .clk = &emul_ck,
475 },
476 .enable_reg = OMAP2430_PRCM_CLKEMUL_CTRL,
477 .enable_bit = OMAP24XX_EMULATION_EN_SHIFT,
478 .clkdm_name = "wkup_clkdm",
479};
480
481DEFINE_STRUCT_CLK(emul_ck, dss_54m_fck_parent_names, aes_ick_ops);
482
483DEFINE_CLK_FIXED_FACTOR(func_12m_ck, "func_48m_ck", &func_48m_ck, 0x0, 1, 4);
484
485static struct clk fac_fck;
486
487static const char *fac_fck_parent_names[] = {
488 "func_12m_ck",
489};
490
491static struct clk_hw_omap fac_fck_hw = {
492 .hw = {
493 .clk = &fac_fck,
494 },
495 .ops = &clkhwops_wait,
496 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
497 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
498 .clkdm_name = "core_l4_clkdm",
499};
500
501DEFINE_STRUCT_CLK(fac_fck, fac_fck_parent_names, aes_ick_ops);
502
503static struct clk fac_ick;
504
505static struct clk_hw_omap fac_ick_hw = {
506 .hw = {
507 .clk = &fac_ick,
508 },
509 .ops = &clkhwops_iclk_wait,
510 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
511 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
512 .clkdm_name = "core_l4_clkdm",
513};
514
515DEFINE_STRUCT_CLK(fac_ick, aes_ick_parent_names, aes_ick_ops);
516
517static const struct clksel gfx_fck_clksel[] = {
518 { .parent = &core_l3_ck, .rates = gfx_l3_rates },
519 { .parent = NULL },
520};
521
522static const char *gfx_2d_fck_parent_names[] = {
523 "core_l3_ck",
524};
525
526DEFINE_CLK_OMAP_MUX_GATE(gfx_2d_fck, "gfx_clkdm", gfx_fck_clksel,
527 OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
528 OMAP_CLKSEL_GFX_MASK,
529 OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
530 OMAP24XX_EN_2D_SHIFT, &clkhwops_wait,
531 gfx_2d_fck_parent_names, dsp_fck_ops);
532
533DEFINE_CLK_OMAP_MUX_GATE(gfx_3d_fck, "gfx_clkdm", gfx_fck_clksel,
534 OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
535 OMAP_CLKSEL_GFX_MASK,
536 OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
537 OMAP24XX_EN_3D_SHIFT, &clkhwops_wait,
538 gfx_2d_fck_parent_names, dsp_fck_ops);
539
540static struct clk gfx_ick;
541
542static const char *gfx_ick_parent_names[] = {
543 "core_l3_ck",
544};
545
546static struct clk_hw_omap gfx_ick_hw = {
547 .hw = {
548 .clk = &gfx_ick,
549 },
550 .ops = &clkhwops_wait,
551 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
552 .enable_bit = OMAP_EN_GFX_SHIFT,
553 .clkdm_name = "gfx_clkdm",
554};
555
556DEFINE_STRUCT_CLK(gfx_ick, gfx_ick_parent_names, aes_ick_ops);
557
558static struct clk gpio5_fck;
559
560static const char *gpio5_fck_parent_names[] = {
561 "func_32k_ck",
562};
563
564static struct clk_hw_omap gpio5_fck_hw = {
565 .hw = {
566 .clk = &gpio5_fck,
567 },
568 .ops = &clkhwops_wait,
569 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
570 .enable_bit = OMAP2430_EN_GPIO5_SHIFT,
571 .clkdm_name = "core_l4_clkdm",
572};
573
574DEFINE_STRUCT_CLK(gpio5_fck, gpio5_fck_parent_names, aes_ick_ops);
575
576static struct clk gpio5_ick;
577
578static struct clk_hw_omap gpio5_ick_hw = {
579 .hw = {
580 .clk = &gpio5_ick,
581 },
582 .ops = &clkhwops_iclk_wait,
583 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
584 .enable_bit = OMAP2430_EN_GPIO5_SHIFT,
585 .clkdm_name = "core_l4_clkdm",
586};
587
588DEFINE_STRUCT_CLK(gpio5_ick, aes_ick_parent_names, aes_ick_ops);
589
590static struct clk gpios_fck;
591
592static struct clk_hw_omap gpios_fck_hw = {
593 .hw = {
594 .clk = &gpios_fck,
595 },
596 .ops = &clkhwops_wait,
597 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
598 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
599 .clkdm_name = "wkup_clkdm",
600};
601
602DEFINE_STRUCT_CLK(gpios_fck, gpio5_fck_parent_names, aes_ick_ops);
603
604static struct clk wu_l4_ick;
605
606DEFINE_STRUCT_CLK_HW_OMAP(wu_l4_ick, "wkup_clkdm");
607DEFINE_STRUCT_CLK(wu_l4_ick, dpll_ck_parent_names, core_ck_ops);
608
609static struct clk gpios_ick;
610
611static const char *gpios_ick_parent_names[] = {
612 "wu_l4_ick",
613};
614
615static struct clk_hw_omap gpios_ick_hw = {
616 .hw = {
617 .clk = &gpios_ick,
618 },
619 .ops = &clkhwops_iclk_wait,
620 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
621 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
622 .clkdm_name = "wkup_clkdm",
623};
624
625DEFINE_STRUCT_CLK(gpios_ick, gpios_ick_parent_names, aes_ick_ops);
626
627static struct clk gpmc_fck;
628
629static struct clk_hw_omap gpmc_fck_hw = {
630 .hw = {
631 .clk = &gpmc_fck,
632 },
633 .ops = &clkhwops_iclk,
634 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
635 .enable_bit = OMAP24XX_AUTO_GPMC_SHIFT,
636 .flags = ENABLE_ON_INIT,
637 .clkdm_name = "core_l3_clkdm",
638};
639
640DEFINE_STRUCT_CLK(gpmc_fck, gfx_ick_parent_names, core_ck_ops);
641
642static const struct clksel_rate gpt_alt_rates[] = {
643 { .div = 1, .val = 2, .flags = RATE_IN_24XX },
644 { .div = 0 }
645};
646
647static const struct clksel omap24xx_gpt_clksel[] = {
648 { .parent = &func_32k_ck, .rates = gpt_32k_rates },
649 { .parent = &sys_ck, .rates = gpt_sys_rates },
650 { .parent = &alt_ck, .rates = gpt_alt_rates },
651 { .parent = NULL },
652};
653
654static const char *gpt10_fck_parent_names[] = {
655 "func_32k_ck", "sys_ck", "alt_ck",
656};
657
658DEFINE_CLK_OMAP_MUX_GATE(gpt10_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
659 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
660 OMAP24XX_CLKSEL_GPT10_MASK,
661 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
662 OMAP24XX_EN_GPT10_SHIFT, &clkhwops_wait,
663 gpt10_fck_parent_names, dss1_fck_ops);
664
665static struct clk gpt10_ick;
666
667static struct clk_hw_omap gpt10_ick_hw = {
668 .hw = {
669 .clk = &gpt10_ick,
670 },
671 .ops = &clkhwops_iclk_wait,
672 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
673 .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
674 .clkdm_name = "core_l4_clkdm",
675};
676
677DEFINE_STRUCT_CLK(gpt10_ick, aes_ick_parent_names, aes_ick_ops);
678
679DEFINE_CLK_OMAP_MUX_GATE(gpt11_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
680 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
681 OMAP24XX_CLKSEL_GPT11_MASK,
682 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
683 OMAP24XX_EN_GPT11_SHIFT, &clkhwops_wait,
684 gpt10_fck_parent_names, dss1_fck_ops);
685
686static struct clk gpt11_ick;
687
688static struct clk_hw_omap gpt11_ick_hw = {
689 .hw = {
690 .clk = &gpt11_ick,
691 },
692 .ops = &clkhwops_iclk_wait,
693 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
694 .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
695 .clkdm_name = "core_l4_clkdm",
696};
697
698DEFINE_STRUCT_CLK(gpt11_ick, aes_ick_parent_names, aes_ick_ops);
699
700DEFINE_CLK_OMAP_MUX_GATE(gpt12_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
701 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
702 OMAP24XX_CLKSEL_GPT12_MASK,
703 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
704 OMAP24XX_EN_GPT12_SHIFT, &clkhwops_wait,
705 gpt10_fck_parent_names, dss1_fck_ops);
706
707static struct clk gpt12_ick;
708
709static struct clk_hw_omap gpt12_ick_hw = {
710 .hw = {
711 .clk = &gpt12_ick,
712 },
713 .ops = &clkhwops_iclk_wait,
714 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
715 .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
716 .clkdm_name = "core_l4_clkdm",
717};
718
719DEFINE_STRUCT_CLK(gpt12_ick, aes_ick_parent_names, aes_ick_ops);
720
721static const struct clk_ops gpt1_fck_ops = {
722 .init = &omap2_init_clk_clkdm,
723 .enable = &omap2_dflt_clk_enable,
724 .disable = &omap2_dflt_clk_disable,
725 .is_enabled = &omap2_dflt_clk_is_enabled,
726 .recalc_rate = &omap2_clksel_recalc,
727 .set_rate = &omap2_clksel_set_rate,
728 .round_rate = &omap2_clksel_round_rate,
729 .get_parent = &omap2_clksel_find_parent_index,
730 .set_parent = &omap2_clksel_set_parent,
731};
732
733DEFINE_CLK_OMAP_MUX_GATE(gpt1_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
734 OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1),
735 OMAP24XX_CLKSEL_GPT1_MASK,
736 OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
737 OMAP24XX_EN_GPT1_SHIFT, &clkhwops_wait,
738 gpt10_fck_parent_names, gpt1_fck_ops);
739
740static struct clk gpt1_ick;
741
742static struct clk_hw_omap gpt1_ick_hw = {
743 .hw = {
744 .clk = &gpt1_ick,
745 },
746 .ops = &clkhwops_iclk_wait,
747 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
748 .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
749 .clkdm_name = "wkup_clkdm",
750};
751
752DEFINE_STRUCT_CLK(gpt1_ick, gpios_ick_parent_names, aes_ick_ops);
753
754DEFINE_CLK_OMAP_MUX_GATE(gpt2_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
755 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
756 OMAP24XX_CLKSEL_GPT2_MASK,
757 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
758 OMAP24XX_EN_GPT2_SHIFT, &clkhwops_wait,
759 gpt10_fck_parent_names, dss1_fck_ops);
760
761static struct clk gpt2_ick;
762
763static struct clk_hw_omap gpt2_ick_hw = {
764 .hw = {
765 .clk = &gpt2_ick,
766 },
767 .ops = &clkhwops_iclk_wait,
768 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
769 .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
770 .clkdm_name = "core_l4_clkdm",
771};
772
773DEFINE_STRUCT_CLK(gpt2_ick, aes_ick_parent_names, aes_ick_ops);
774
775DEFINE_CLK_OMAP_MUX_GATE(gpt3_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
776 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
777 OMAP24XX_CLKSEL_GPT3_MASK,
778 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
779 OMAP24XX_EN_GPT3_SHIFT, &clkhwops_wait,
780 gpt10_fck_parent_names, dss1_fck_ops);
781
782static struct clk gpt3_ick;
783
784static struct clk_hw_omap gpt3_ick_hw = {
785 .hw = {
786 .clk = &gpt3_ick,
787 },
788 .ops = &clkhwops_iclk_wait,
789 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
790 .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
791 .clkdm_name = "core_l4_clkdm",
792};
793
794DEFINE_STRUCT_CLK(gpt3_ick, aes_ick_parent_names, aes_ick_ops);
795
796DEFINE_CLK_OMAP_MUX_GATE(gpt4_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
797 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
798 OMAP24XX_CLKSEL_GPT4_MASK,
799 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
800 OMAP24XX_EN_GPT4_SHIFT, &clkhwops_wait,
801 gpt10_fck_parent_names, dss1_fck_ops);
802
803static struct clk gpt4_ick;
804
805static struct clk_hw_omap gpt4_ick_hw = {
806 .hw = {
807 .clk = &gpt4_ick,
808 },
809 .ops = &clkhwops_iclk_wait,
810 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
811 .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
812 .clkdm_name = "core_l4_clkdm",
813};
814
815DEFINE_STRUCT_CLK(gpt4_ick, aes_ick_parent_names, aes_ick_ops);
816
817DEFINE_CLK_OMAP_MUX_GATE(gpt5_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
818 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
819 OMAP24XX_CLKSEL_GPT5_MASK,
820 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
821 OMAP24XX_EN_GPT5_SHIFT, &clkhwops_wait,
822 gpt10_fck_parent_names, dss1_fck_ops);
823
824static struct clk gpt5_ick;
825
826static struct clk_hw_omap gpt5_ick_hw = {
827 .hw = {
828 .clk = &gpt5_ick,
829 },
830 .ops = &clkhwops_iclk_wait,
831 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
832 .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
833 .clkdm_name = "core_l4_clkdm",
834};
835
836DEFINE_STRUCT_CLK(gpt5_ick, aes_ick_parent_names, aes_ick_ops);
837
838DEFINE_CLK_OMAP_MUX_GATE(gpt6_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
839 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
840 OMAP24XX_CLKSEL_GPT6_MASK,
841 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
842 OMAP24XX_EN_GPT6_SHIFT, &clkhwops_wait,
843 gpt10_fck_parent_names, dss1_fck_ops);
844
845static struct clk gpt6_ick;
846
847static struct clk_hw_omap gpt6_ick_hw = {
848 .hw = {
849 .clk = &gpt6_ick,
850 },
851 .ops = &clkhwops_iclk_wait,
852 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
853 .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
854 .clkdm_name = "core_l4_clkdm",
855};
856
857DEFINE_STRUCT_CLK(gpt6_ick, aes_ick_parent_names, aes_ick_ops);
858
859DEFINE_CLK_OMAP_MUX_GATE(gpt7_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
860 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
861 OMAP24XX_CLKSEL_GPT7_MASK,
862 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
863 OMAP24XX_EN_GPT7_SHIFT, &clkhwops_wait,
864 gpt10_fck_parent_names, dss1_fck_ops);
865
866static struct clk gpt7_ick;
867
868static struct clk_hw_omap gpt7_ick_hw = {
869 .hw = {
870 .clk = &gpt7_ick,
871 },
872 .ops = &clkhwops_iclk_wait,
873 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
874 .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
875 .clkdm_name = "core_l4_clkdm",
876};
877
878DEFINE_STRUCT_CLK(gpt7_ick, aes_ick_parent_names, aes_ick_ops);
879
880static struct clk gpt8_fck;
881
882DEFINE_CLK_OMAP_MUX_GATE(gpt8_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
883 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
884 OMAP24XX_CLKSEL_GPT8_MASK,
885 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
886 OMAP24XX_EN_GPT8_SHIFT, &clkhwops_wait,
887 gpt10_fck_parent_names, dss1_fck_ops);
888
889static struct clk gpt8_ick;
890
891static struct clk_hw_omap gpt8_ick_hw = {
892 .hw = {
893 .clk = &gpt8_ick,
894 },
895 .ops = &clkhwops_iclk_wait,
896 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
897 .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
898 .clkdm_name = "core_l4_clkdm",
899};
900
901DEFINE_STRUCT_CLK(gpt8_ick, aes_ick_parent_names, aes_ick_ops);
902
903DEFINE_CLK_OMAP_MUX_GATE(gpt9_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
904 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
905 OMAP24XX_CLKSEL_GPT9_MASK,
906 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
907 OMAP24XX_EN_GPT9_SHIFT, &clkhwops_wait,
908 gpt10_fck_parent_names, dss1_fck_ops);
909
910static struct clk gpt9_ick;
911
912static struct clk_hw_omap gpt9_ick_hw = {
913 .hw = {
914 .clk = &gpt9_ick,
915 },
916 .ops = &clkhwops_iclk_wait,
917 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
918 .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
919 .clkdm_name = "core_l4_clkdm",
920};
921
922DEFINE_STRUCT_CLK(gpt9_ick, aes_ick_parent_names, aes_ick_ops);
923
924static struct clk hdq_fck;
925
926static struct clk_hw_omap hdq_fck_hw = {
927 .hw = {
928 .clk = &hdq_fck,
929 },
930 .ops = &clkhwops_wait,
931 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
932 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
933 .clkdm_name = "core_l4_clkdm",
934};
935
936DEFINE_STRUCT_CLK(hdq_fck, fac_fck_parent_names, aes_ick_ops);
937
938static struct clk hdq_ick;
939
940static struct clk_hw_omap hdq_ick_hw = {
941 .hw = {
942 .clk = &hdq_ick,
943 },
944 .ops = &clkhwops_iclk_wait,
945 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
946 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
947 .clkdm_name = "core_l4_clkdm",
948};
949
950DEFINE_STRUCT_CLK(hdq_ick, aes_ick_parent_names, aes_ick_ops);
951
952static struct clk i2c1_ick;
953
954static struct clk_hw_omap i2c1_ick_hw = {
955 .hw = {
956 .clk = &i2c1_ick,
957 },
958 .ops = &clkhwops_iclk_wait,
959 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
960 .enable_bit = OMAP2420_EN_I2C1_SHIFT,
961 .clkdm_name = "core_l4_clkdm",
962};
963
964DEFINE_STRUCT_CLK(i2c1_ick, aes_ick_parent_names, aes_ick_ops);
965
966static struct clk i2c2_ick;
967
968static struct clk_hw_omap i2c2_ick_hw = {
969 .hw = {
970 .clk = &i2c2_ick,
971 },
972 .ops = &clkhwops_iclk_wait,
973 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
974 .enable_bit = OMAP2420_EN_I2C2_SHIFT,
975 .clkdm_name = "core_l4_clkdm",
976};
977
978DEFINE_STRUCT_CLK(i2c2_ick, aes_ick_parent_names, aes_ick_ops);
979
980static struct clk i2chs1_fck;
981
982static struct clk_hw_omap i2chs1_fck_hw = {
983 .hw = {
984 .clk = &i2chs1_fck,
985 },
986 .ops = &clkhwops_omap2430_i2chs_wait,
987 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
988 .enable_bit = OMAP2430_EN_I2CHS1_SHIFT,
989 .clkdm_name = "core_l4_clkdm",
990};
991
992DEFINE_STRUCT_CLK(i2chs1_fck, cam_fck_parent_names, aes_ick_ops);
993
994static struct clk i2chs2_fck;
995
996static struct clk_hw_omap i2chs2_fck_hw = {
997 .hw = {
998 .clk = &i2chs2_fck,
999 },
1000 .ops = &clkhwops_omap2430_i2chs_wait,
1001 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1002 .enable_bit = OMAP2430_EN_I2CHS2_SHIFT,
1003 .clkdm_name = "core_l4_clkdm",
1004};
1005
1006DEFINE_STRUCT_CLK(i2chs2_fck, cam_fck_parent_names, aes_ick_ops);
1007
1008static struct clk icr_ick;
1009
1010static struct clk_hw_omap icr_ick_hw = {
1011 .hw = {
1012 .clk = &icr_ick,
1013 },
1014 .ops = &clkhwops_iclk_wait,
1015 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1016 .enable_bit = OMAP2430_EN_ICR_SHIFT,
1017 .clkdm_name = "wkup_clkdm",
1018};
1019
1020DEFINE_STRUCT_CLK(icr_ick, gpios_ick_parent_names, aes_ick_ops);
1021
1022static const struct clksel dsp_ick_clksel[] = {
1023 { .parent = &dsp_fck, .rates = dsp_ick_rates },
1024 { .parent = NULL },
1025};
1026
1027static const char *iva2_1_ick_parent_names[] = {
1028 "dsp_fck",
1029};
1030
1031DEFINE_CLK_OMAP_MUX_GATE(iva2_1_ick, "dsp_clkdm", dsp_ick_clksel,
1032 OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1033 OMAP24XX_CLKSEL_DSP_IF_MASK,
1034 OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1035 OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, &clkhwops_wait,
1036 iva2_1_ick_parent_names, dsp_fck_ops);
1037
1038static struct clk mailboxes_ick;
1039
1040static struct clk_hw_omap mailboxes_ick_hw = {
1041 .hw = {
1042 .clk = &mailboxes_ick,
1043 },
1044 .ops = &clkhwops_iclk_wait,
1045 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1046 .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
1047 .clkdm_name = "core_l4_clkdm",
1048};
1049
1050DEFINE_STRUCT_CLK(mailboxes_ick, aes_ick_parent_names, aes_ick_ops);
1051
1052static const struct clksel_rate common_mcbsp_96m_rates[] = {
1053 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
1054 { .div = 0 }
1055};
1056
1057static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1058 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1059 { .div = 0 }
1060};
1061
1062static const struct clksel mcbsp_fck_clksel[] = {
1063 { .parent = &func_96m_ck, .rates = common_mcbsp_96m_rates },
1064 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
1065 { .parent = NULL },
1066};
1067
1068static const char *mcbsp1_fck_parent_names[] = {
1069 "func_96m_ck", "mcbsp_clks",
1070};
1071
1072DEFINE_CLK_OMAP_MUX_GATE(mcbsp1_fck, "core_l4_clkdm", mcbsp_fck_clksel,
1073 OMAP243X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1074 OMAP2_MCBSP1_CLKS_MASK,
1075 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1076 OMAP24XX_EN_MCBSP1_SHIFT, &clkhwops_wait,
1077 mcbsp1_fck_parent_names, dss1_fck_ops);
1078
1079static struct clk mcbsp1_ick;
1080
1081static struct clk_hw_omap mcbsp1_ick_hw = {
1082 .hw = {
1083 .clk = &mcbsp1_ick,
1084 },
1085 .ops = &clkhwops_iclk_wait,
1086 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1087 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1088 .clkdm_name = "core_l4_clkdm",
1089};
1090
1091DEFINE_STRUCT_CLK(mcbsp1_ick, aes_ick_parent_names, aes_ick_ops);
1092
1093DEFINE_CLK_OMAP_MUX_GATE(mcbsp2_fck, "core_l4_clkdm", mcbsp_fck_clksel,
1094 OMAP243X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1095 OMAP2_MCBSP2_CLKS_MASK,
1096 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1097 OMAP24XX_EN_MCBSP2_SHIFT, &clkhwops_wait,
1098 mcbsp1_fck_parent_names, dss1_fck_ops);
1099
1100static struct clk mcbsp2_ick;
1101
1102static struct clk_hw_omap mcbsp2_ick_hw = {
1103 .hw = {
1104 .clk = &mcbsp2_ick,
1105 },
1106 .ops = &clkhwops_iclk_wait,
1107 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1108 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1109 .clkdm_name = "core_l4_clkdm",
1110};
1111
1112DEFINE_STRUCT_CLK(mcbsp2_ick, aes_ick_parent_names, aes_ick_ops);
1113
1114DEFINE_CLK_OMAP_MUX_GATE(mcbsp3_fck, "core_l4_clkdm", mcbsp_fck_clksel,
1115 OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1),
1116 OMAP2_MCBSP3_CLKS_MASK,
1117 OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1118 OMAP2430_EN_MCBSP3_SHIFT, &clkhwops_wait,
1119 mcbsp1_fck_parent_names, dss1_fck_ops);
1120
1121static struct clk mcbsp3_ick;
1122
1123static struct clk_hw_omap mcbsp3_ick_hw = {
1124 .hw = {
1125 .clk = &mcbsp3_ick,
1126 },
1127 .ops = &clkhwops_iclk_wait,
1128 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1129 .enable_bit = OMAP2430_EN_MCBSP3_SHIFT,
1130 .clkdm_name = "core_l4_clkdm",
1131};
1132
1133DEFINE_STRUCT_CLK(mcbsp3_ick, aes_ick_parent_names, aes_ick_ops);
1134
1135DEFINE_CLK_OMAP_MUX_GATE(mcbsp4_fck, "core_l4_clkdm", mcbsp_fck_clksel,
1136 OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1),
1137 OMAP2_MCBSP4_CLKS_MASK,
1138 OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1139 OMAP2430_EN_MCBSP4_SHIFT, &clkhwops_wait,
1140 mcbsp1_fck_parent_names, dss1_fck_ops);
1141
1142static struct clk mcbsp4_ick;
1143
1144static struct clk_hw_omap mcbsp4_ick_hw = {
1145 .hw = {
1146 .clk = &mcbsp4_ick,
1147 },
1148 .ops = &clkhwops_iclk_wait,
1149 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1150 .enable_bit = OMAP2430_EN_MCBSP4_SHIFT,
1151 .clkdm_name = "core_l4_clkdm",
1152};
1153
1154DEFINE_STRUCT_CLK(mcbsp4_ick, aes_ick_parent_names, aes_ick_ops);
1155
1156DEFINE_CLK_OMAP_MUX_GATE(mcbsp5_fck, "core_l4_clkdm", mcbsp_fck_clksel,
1157 OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1),
1158 OMAP2_MCBSP5_CLKS_MASK,
1159 OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1160 OMAP2430_EN_MCBSP5_SHIFT, &clkhwops_wait,
1161 mcbsp1_fck_parent_names, dss1_fck_ops);
1162
1163static struct clk mcbsp5_ick;
1164
1165static struct clk_hw_omap mcbsp5_ick_hw = {
1166 .hw = {
1167 .clk = &mcbsp5_ick,
1168 },
1169 .ops = &clkhwops_iclk_wait,
1170 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1171 .enable_bit = OMAP2430_EN_MCBSP5_SHIFT,
1172 .clkdm_name = "core_l4_clkdm",
1173};
1174
1175DEFINE_STRUCT_CLK(mcbsp5_ick, aes_ick_parent_names, aes_ick_ops);
1176
1177static struct clk mcspi1_fck;
1178
1179static const char *mcspi1_fck_parent_names[] = {
1180 "func_48m_ck",
1181};
1182
1183static struct clk_hw_omap mcspi1_fck_hw = {
1184 .hw = {
1185 .clk = &mcspi1_fck,
1186 },
1187 .ops = &clkhwops_wait,
1188 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1189 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1190 .clkdm_name = "core_l4_clkdm",
1191};
1192
1193DEFINE_STRUCT_CLK(mcspi1_fck, mcspi1_fck_parent_names, aes_ick_ops);
1194
1195static struct clk mcspi1_ick;
1196
1197static struct clk_hw_omap mcspi1_ick_hw = {
1198 .hw = {
1199 .clk = &mcspi1_ick,
1200 },
1201 .ops = &clkhwops_iclk_wait,
1202 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1203 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1204 .clkdm_name = "core_l4_clkdm",
1205};
1206
1207DEFINE_STRUCT_CLK(mcspi1_ick, aes_ick_parent_names, aes_ick_ops);
1208
1209static struct clk mcspi2_fck;
1210
1211static struct clk_hw_omap mcspi2_fck_hw = {
1212 .hw = {
1213 .clk = &mcspi2_fck,
1214 },
1215 .ops = &clkhwops_wait,
1216 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1217 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1218 .clkdm_name = "core_l4_clkdm",
1219};
1220
1221DEFINE_STRUCT_CLK(mcspi2_fck, mcspi1_fck_parent_names, aes_ick_ops);
1222
1223static struct clk mcspi2_ick;
1224
1225static struct clk_hw_omap mcspi2_ick_hw = {
1226 .hw = {
1227 .clk = &mcspi2_ick,
1228 },
1229 .ops = &clkhwops_iclk_wait,
1230 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1231 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1232 .clkdm_name = "core_l4_clkdm",
1233};
1234
1235DEFINE_STRUCT_CLK(mcspi2_ick, aes_ick_parent_names, aes_ick_ops);
1236
1237static struct clk mcspi3_fck;
1238
1239static struct clk_hw_omap mcspi3_fck_hw = {
1240 .hw = {
1241 .clk = &mcspi3_fck,
1242 },
1243 .ops = &clkhwops_wait,
1244 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1245 .enable_bit = OMAP2430_EN_MCSPI3_SHIFT,
1246 .clkdm_name = "core_l4_clkdm",
1247};
1248
1249DEFINE_STRUCT_CLK(mcspi3_fck, mcspi1_fck_parent_names, aes_ick_ops);
1250
1251static struct clk mcspi3_ick;
1252
1253static struct clk_hw_omap mcspi3_ick_hw = {
1254 .hw = {
1255 .clk = &mcspi3_ick,
1256 },
1257 .ops = &clkhwops_iclk_wait,
1258 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1259 .enable_bit = OMAP2430_EN_MCSPI3_SHIFT,
1260 .clkdm_name = "core_l4_clkdm",
1261};
1262
1263DEFINE_STRUCT_CLK(mcspi3_ick, aes_ick_parent_names, aes_ick_ops);
1264
1265static const struct clksel_rate mdm_ick_core_rates[] = {
1266 { .div = 1, .val = 1, .flags = RATE_IN_243X },
1267 { .div = 4, .val = 4, .flags = RATE_IN_243X },
1268 { .div = 6, .val = 6, .flags = RATE_IN_243X },
1269 { .div = 9, .val = 9, .flags = RATE_IN_243X },
1270 { .div = 0 }
1271};
1272
1273static const struct clksel mdm_ick_clksel[] = {
1274 { .parent = &core_ck, .rates = mdm_ick_core_rates },
1275 { .parent = NULL },
1276};
1277
1278static const char *mdm_ick_parent_names[] = {
1279 "core_ck",
1280};
1281
1282DEFINE_CLK_OMAP_MUX_GATE(mdm_ick, "mdm_clkdm", mdm_ick_clksel,
1283 OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL),
1284 OMAP2430_CLKSEL_MDM_MASK,
1285 OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
1286 OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
1287 &clkhwops_iclk_wait, mdm_ick_parent_names,
1288 dsp_fck_ops);
1289
1290static struct clk mdm_intc_ick;
1291
1292static struct clk_hw_omap mdm_intc_ick_hw = {
1293 .hw = {
1294 .clk = &mdm_intc_ick,
1295 },
1296 .ops = &clkhwops_iclk_wait,
1297 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1298 .enable_bit = OMAP2430_EN_MDM_INTC_SHIFT,
1299 .clkdm_name = "core_l4_clkdm",
1300};
1301
1302DEFINE_STRUCT_CLK(mdm_intc_ick, aes_ick_parent_names, aes_ick_ops);
1303
1304static struct clk mdm_osc_ck;
1305
1306static struct clk_hw_omap mdm_osc_ck_hw = {
1307 .hw = {
1308 .clk = &mdm_osc_ck,
1309 },
1310 .ops = &clkhwops_iclk_wait,
1311 .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN),
1312 .enable_bit = OMAP2430_EN_OSC_SHIFT,
1313 .clkdm_name = "mdm_clkdm",
1314};
1315
1316DEFINE_STRUCT_CLK(mdm_osc_ck, sys_ck_parent_names, aes_ick_ops);
1317
1318static struct clk mmchs1_fck;
1319
1320static struct clk_hw_omap mmchs1_fck_hw = {
1321 .hw = {
1322 .clk = &mmchs1_fck,
1323 },
1324 .ops = &clkhwops_wait,
1325 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1326 .enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
1327 .clkdm_name = "core_l4_clkdm",
1328};
1329
1330DEFINE_STRUCT_CLK(mmchs1_fck, cam_fck_parent_names, aes_ick_ops);
1331
1332static struct clk mmchs1_ick;
1333
1334static struct clk_hw_omap mmchs1_ick_hw = {
1335 .hw = {
1336 .clk = &mmchs1_ick,
1337 },
1338 .ops = &clkhwops_iclk_wait,
1339 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1340 .enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
1341 .clkdm_name = "core_l4_clkdm",
1342};
1343
1344DEFINE_STRUCT_CLK(mmchs1_ick, aes_ick_parent_names, aes_ick_ops);
1345
1346static struct clk mmchs2_fck;
1347
1348static struct clk_hw_omap mmchs2_fck_hw = {
1349 .hw = {
1350 .clk = &mmchs2_fck,
1351 },
1352 .ops = &clkhwops_wait,
1353 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1354 .enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
1355 .clkdm_name = "core_l4_clkdm",
1356};
1357
1358DEFINE_STRUCT_CLK(mmchs2_fck, cam_fck_parent_names, aes_ick_ops);
1359
1360static struct clk mmchs2_ick;
1361
1362static struct clk_hw_omap mmchs2_ick_hw = {
1363 .hw = {
1364 .clk = &mmchs2_ick,
1365 },
1366 .ops = &clkhwops_iclk_wait,
1367 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1368 .enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
1369 .clkdm_name = "core_l4_clkdm",
1370};
1371
1372DEFINE_STRUCT_CLK(mmchs2_ick, aes_ick_parent_names, aes_ick_ops);
1373
1374static struct clk mmchsdb1_fck;
1375
1376static struct clk_hw_omap mmchsdb1_fck_hw = {
1377 .hw = {
1378 .clk = &mmchsdb1_fck,
1379 },
1380 .ops = &clkhwops_wait,
1381 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1382 .enable_bit = OMAP2430_EN_MMCHSDB1_SHIFT,
1383 .clkdm_name = "core_l4_clkdm",
1384};
1385
1386DEFINE_STRUCT_CLK(mmchsdb1_fck, gpio5_fck_parent_names, aes_ick_ops);
1387
1388static struct clk mmchsdb2_fck;
1389
1390static struct clk_hw_omap mmchsdb2_fck_hw = {
1391 .hw = {
1392 .clk = &mmchsdb2_fck,
1393 },
1394 .ops = &clkhwops_wait,
1395 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1396 .enable_bit = OMAP2430_EN_MMCHSDB2_SHIFT,
1397 .clkdm_name = "core_l4_clkdm",
1398};
1399
1400DEFINE_STRUCT_CLK(mmchsdb2_fck, gpio5_fck_parent_names, aes_ick_ops);
1401
1402DEFINE_CLK_DIVIDER(mpu_ck, "core_ck", &core_ck, 0x0,
1403 OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
1404 OMAP24XX_CLKSEL_MPU_SHIFT, OMAP24XX_CLKSEL_MPU_WIDTH,
1405 CLK_DIVIDER_ONE_BASED, NULL);
1406
1407static struct clk mpu_wdt_fck;
1408
1409static struct clk_hw_omap mpu_wdt_fck_hw = {
1410 .hw = {
1411 .clk = &mpu_wdt_fck,
1412 },
1413 .ops = &clkhwops_wait,
1414 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1415 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
1416 .clkdm_name = "wkup_clkdm",
1417};
1418
1419DEFINE_STRUCT_CLK(mpu_wdt_fck, gpio5_fck_parent_names, aes_ick_ops);
1420
1421static struct clk mpu_wdt_ick;
1422
1423static struct clk_hw_omap mpu_wdt_ick_hw = {
1424 .hw = {
1425 .clk = &mpu_wdt_ick,
1426 },
1427 .ops = &clkhwops_iclk_wait,
1428 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1429 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
1430 .clkdm_name = "wkup_clkdm",
1431};
1432
1433DEFINE_STRUCT_CLK(mpu_wdt_ick, gpios_ick_parent_names, aes_ick_ops);
1434
1435static struct clk mspro_fck;
1436
1437static struct clk_hw_omap mspro_fck_hw = {
1438 .hw = {
1439 .clk = &mspro_fck,
1440 },
1441 .ops = &clkhwops_wait,
1442 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1443 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
1444 .clkdm_name = "core_l4_clkdm",
1445};
1446
1447DEFINE_STRUCT_CLK(mspro_fck, cam_fck_parent_names, aes_ick_ops);
1448
1449static struct clk mspro_ick;
1450
1451static struct clk_hw_omap mspro_ick_hw = {
1452 .hw = {
1453 .clk = &mspro_ick,
1454 },
1455 .ops = &clkhwops_iclk_wait,
1456 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1457 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
1458 .clkdm_name = "core_l4_clkdm",
1459};
1460
1461DEFINE_STRUCT_CLK(mspro_ick, aes_ick_parent_names, aes_ick_ops);
1462
1463static struct clk omapctrl_ick;
1464
1465static struct clk_hw_omap omapctrl_ick_hw = {
1466 .hw = {
1467 .clk = &omapctrl_ick,
1468 },
1469 .ops = &clkhwops_iclk_wait,
1470 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1471 .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT,
1472 .flags = ENABLE_ON_INIT,
1473 .clkdm_name = "wkup_clkdm",
1474};
1475
1476DEFINE_STRUCT_CLK(omapctrl_ick, gpios_ick_parent_names, aes_ick_ops);
1477
1478static struct clk pka_ick;
1479
1480static struct clk_hw_omap pka_ick_hw = {
1481 .hw = {
1482 .clk = &pka_ick,
1483 },
1484 .ops = &clkhwops_iclk_wait,
1485 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1486 .enable_bit = OMAP24XX_EN_PKA_SHIFT,
1487 .clkdm_name = "core_l4_clkdm",
1488};
1489
1490DEFINE_STRUCT_CLK(pka_ick, aes_ick_parent_names, aes_ick_ops);
1491
1492static struct clk rng_ick;
1493
1494static struct clk_hw_omap rng_ick_hw = {
1495 .hw = {
1496 .clk = &rng_ick,
1497 },
1498 .ops = &clkhwops_iclk_wait,
1499 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1500 .enable_bit = OMAP24XX_EN_RNG_SHIFT,
1501 .clkdm_name = "core_l4_clkdm",
1502};
1503
1504DEFINE_STRUCT_CLK(rng_ick, aes_ick_parent_names, aes_ick_ops);
1505
1506static struct clk sdma_fck;
1507
1508DEFINE_STRUCT_CLK_HW_OMAP(sdma_fck, "core_l3_clkdm");
1509DEFINE_STRUCT_CLK(sdma_fck, gfx_ick_parent_names, core_ck_ops);
1510
1511static struct clk sdma_ick;
1512
1513static struct clk_hw_omap sdma_ick_hw = {
1514 .hw = {
1515 .clk = &sdma_ick,
1516 },
1517 .ops = &clkhwops_iclk,
1518 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1519 .enable_bit = OMAP24XX_AUTO_SDMA_SHIFT,
1520 .clkdm_name = "core_l3_clkdm",
1521};
1522
1523DEFINE_STRUCT_CLK(sdma_ick, gfx_ick_parent_names, core_ck_ops);
1524
1525static struct clk sdrc_ick;
1526
1527static struct clk_hw_omap sdrc_ick_hw = {
1528 .hw = {
1529 .clk = &sdrc_ick,
1530 },
1531 .ops = &clkhwops_iclk,
1532 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1533 .enable_bit = OMAP2430_EN_SDRC_SHIFT,
1534 .flags = ENABLE_ON_INIT,
1535 .clkdm_name = "core_l3_clkdm",
1536};
1537
1538DEFINE_STRUCT_CLK(sdrc_ick, gfx_ick_parent_names, core_ck_ops);
1539
1540static struct clk sha_ick;
1541
1542static struct clk_hw_omap sha_ick_hw = {
1543 .hw = {
1544 .clk = &sha_ick,
1545 },
1546 .ops = &clkhwops_iclk_wait,
1547 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1548 .enable_bit = OMAP24XX_EN_SHA_SHIFT,
1549 .clkdm_name = "core_l4_clkdm",
1550};
1551
1552DEFINE_STRUCT_CLK(sha_ick, aes_ick_parent_names, aes_ick_ops);
1553
1554static struct clk ssi_l4_ick;
1555
1556static struct clk_hw_omap ssi_l4_ick_hw = {
1557 .hw = {
1558 .clk = &ssi_l4_ick,
1559 },
1560 .ops = &clkhwops_iclk_wait,
1561 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1562 .enable_bit = OMAP24XX_EN_SSI_SHIFT,
1563 .clkdm_name = "core_l4_clkdm",
1564};
1565
1566DEFINE_STRUCT_CLK(ssi_l4_ick, aes_ick_parent_names, aes_ick_ops);
1567
1568static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
1569 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1570 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1571 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1572 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1573 { .div = 5, .val = 5, .flags = RATE_IN_243X },
1574 { .div = 0 }
1575};
1576
1577static const struct clksel ssi_ssr_sst_fck_clksel[] = {
1578 { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
1579 { .parent = NULL },
1580};
1581
1582static const char *ssi_ssr_sst_fck_parent_names[] = {
1583 "core_ck",
1584};
1585
1586DEFINE_CLK_OMAP_MUX_GATE(ssi_ssr_sst_fck, "core_l3_clkdm",
1587 ssi_ssr_sst_fck_clksel,
1588 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1589 OMAP24XX_CLKSEL_SSI_MASK,
1590 OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1591 OMAP24XX_EN_SSI_SHIFT, &clkhwops_wait,
1592 ssi_ssr_sst_fck_parent_names, dsp_fck_ops);
1593
1594static struct clk sync_32k_ick;
1595
1596static struct clk_hw_omap sync_32k_ick_hw = {
1597 .hw = {
1598 .clk = &sync_32k_ick,
1599 },
1600 .ops = &clkhwops_iclk_wait,
1601 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1602 .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT,
1603 .flags = ENABLE_ON_INIT,
1604 .clkdm_name = "wkup_clkdm",
1605};
1606
1607DEFINE_STRUCT_CLK(sync_32k_ick, gpios_ick_parent_names, aes_ick_ops);
1608
1609static const struct clksel_rate common_clkout_src_core_rates[] = {
1610 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
1611 { .div = 0 }
1612};
1613
1614static const struct clksel_rate common_clkout_src_sys_rates[] = {
1615 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1616 { .div = 0 }
1617};
1618
1619static const struct clksel_rate common_clkout_src_96m_rates[] = {
1620 { .div = 1, .val = 2, .flags = RATE_IN_24XX },
1621 { .div = 0 }
1622};
1623
1624static const struct clksel_rate common_clkout_src_54m_rates[] = {
1625 { .div = 1, .val = 3, .flags = RATE_IN_24XX },
1626 { .div = 0 }
1627};
1628
1629static const struct clksel common_clkout_src_clksel[] = {
1630 { .parent = &core_ck, .rates = common_clkout_src_core_rates },
1631 { .parent = &sys_ck, .rates = common_clkout_src_sys_rates },
1632 { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
1633 { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
1634 { .parent = NULL },
1635};
1636
1637static const char *sys_clkout_src_parent_names[] = {
1638 "core_ck", "sys_ck", "func_96m_ck", "func_54m_ck",
1639};
1640
1641DEFINE_CLK_OMAP_MUX_GATE(sys_clkout_src, "wkup_clkdm", common_clkout_src_clksel,
1642 OMAP2430_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_SOURCE_MASK,
1643 OMAP2430_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_EN_SHIFT,
1644 NULL, sys_clkout_src_parent_names, gpt1_fck_ops);
1645
1646DEFINE_CLK_DIVIDER(sys_clkout, "sys_clkout_src", &sys_clkout_src, 0x0,
1647 OMAP2430_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_DIV_SHIFT,
1648 OMAP24XX_CLKOUT_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
1649
1650static struct clk uart1_fck;
1651
1652static struct clk_hw_omap uart1_fck_hw = {
1653 .hw = {
1654 .clk = &uart1_fck,
1655 },
1656 .ops = &clkhwops_wait,
1657 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1658 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
1659 .clkdm_name = "core_l4_clkdm",
1660};
1661
1662DEFINE_STRUCT_CLK(uart1_fck, mcspi1_fck_parent_names, aes_ick_ops);
1663
1664static struct clk uart1_ick;
1665
1666static struct clk_hw_omap uart1_ick_hw = {
1667 .hw = {
1668 .clk = &uart1_ick,
1669 },
1670 .ops = &clkhwops_iclk_wait,
1671 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1672 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
1673 .clkdm_name = "core_l4_clkdm",
1674};
1675
1676DEFINE_STRUCT_CLK(uart1_ick, aes_ick_parent_names, aes_ick_ops);
1677
1678static struct clk uart2_fck;
1679
1680static struct clk_hw_omap uart2_fck_hw = {
1681 .hw = {
1682 .clk = &uart2_fck,
1683 },
1684 .ops = &clkhwops_wait,
1685 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1686 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
1687 .clkdm_name = "core_l4_clkdm",
1688};
1689
1690DEFINE_STRUCT_CLK(uart2_fck, mcspi1_fck_parent_names, aes_ick_ops);
1691
1692static struct clk uart2_ick;
1693
1694static struct clk_hw_omap uart2_ick_hw = {
1695 .hw = {
1696 .clk = &uart2_ick,
1697 },
1698 .ops = &clkhwops_iclk_wait,
1699 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1700 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
1701 .clkdm_name = "core_l4_clkdm",
1702};
1703
1704DEFINE_STRUCT_CLK(uart2_ick, aes_ick_parent_names, aes_ick_ops);
1705
1706static struct clk uart3_fck;
1707
1708static struct clk_hw_omap uart3_fck_hw = {
1709 .hw = {
1710 .clk = &uart3_fck,
1711 },
1712 .ops = &clkhwops_wait,
1713 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1714 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
1715 .clkdm_name = "core_l4_clkdm",
1716};
1717
1718DEFINE_STRUCT_CLK(uart3_fck, mcspi1_fck_parent_names, aes_ick_ops);
1719
1720static struct clk uart3_ick;
1721
1722static struct clk_hw_omap uart3_ick_hw = {
1723 .hw = {
1724 .clk = &uart3_ick,
1725 },
1726 .ops = &clkhwops_iclk_wait,
1727 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1728 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
1729 .clkdm_name = "core_l4_clkdm",
1730};
1731
1732DEFINE_STRUCT_CLK(uart3_ick, aes_ick_parent_names, aes_ick_ops);
1733
1734static struct clk usb_fck;
1735
1736static struct clk_hw_omap usb_fck_hw = {
1737 .hw = {
1738 .clk = &usb_fck,
1739 },
1740 .ops = &clkhwops_wait,
1741 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1742 .enable_bit = OMAP24XX_EN_USB_SHIFT,
1743 .clkdm_name = "core_l3_clkdm",
1744};
1745
1746DEFINE_STRUCT_CLK(usb_fck, mcspi1_fck_parent_names, aes_ick_ops);
1747
1748static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
1749 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1750 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1751 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1752 { .div = 0 }
1753};
1754
1755static const struct clksel usb_l4_ick_clksel[] = {
1756 { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
1757 { .parent = NULL },
1758};
1759
1760static const char *usb_l4_ick_parent_names[] = {
1761 "core_l3_ck",
1762};
1763
1764DEFINE_CLK_OMAP_MUX_GATE(usb_l4_ick, "core_l4_clkdm", usb_l4_ick_clksel,
1765 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1766 OMAP24XX_CLKSEL_USB_MASK,
1767 OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1768 OMAP24XX_EN_USB_SHIFT, &clkhwops_iclk_wait,
1769 usb_l4_ick_parent_names, dsp_fck_ops);
1770
1771static struct clk usbhs_ick;
1772
1773static struct clk_hw_omap usbhs_ick_hw = {
1774 .hw = {
1775 .clk = &usbhs_ick,
1776 },
1777 .ops = &clkhwops_iclk_wait,
1778 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1779 .enable_bit = OMAP2430_EN_USBHS_SHIFT,
1780 .clkdm_name = "core_l3_clkdm",
1781};
1782
1783DEFINE_STRUCT_CLK(usbhs_ick, gfx_ick_parent_names, aes_ick_ops);
1784
1785static struct clk virt_prcm_set;
1786
1787static const char *virt_prcm_set_parent_names[] = {
1788 "mpu_ck",
1789};
1790
1791static const struct clk_ops virt_prcm_set_ops = {
1792 .recalc_rate = &omap2_table_mpu_recalc,
1793 .set_rate = &omap2_select_table_rate,
1794 .round_rate = &omap2_round_to_table_rate,
1795};
1796
1797DEFINE_STRUCT_CLK_HW_OMAP(virt_prcm_set, NULL);
1798DEFINE_STRUCT_CLK(virt_prcm_set, virt_prcm_set_parent_names, virt_prcm_set_ops);
1799
1800static struct clk wdt1_ick;
1801
1802static struct clk_hw_omap wdt1_ick_hw = {
1803 .hw = {
1804 .clk = &wdt1_ick,
1805 },
1806 .ops = &clkhwops_iclk_wait,
1807 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1808 .enable_bit = OMAP24XX_EN_WDT1_SHIFT,
1809 .clkdm_name = "wkup_clkdm",
1810};
1811
1812DEFINE_STRUCT_CLK(wdt1_ick, gpios_ick_parent_names, aes_ick_ops);
1813
1814static struct clk wdt1_osc_ck;
1815
1816static const struct clk_ops wdt1_osc_ck_ops = {};
1817
1818DEFINE_STRUCT_CLK_HW_OMAP(wdt1_osc_ck, NULL);
1819DEFINE_STRUCT_CLK(wdt1_osc_ck, sys_ck_parent_names, wdt1_osc_ck_ops);
1820
1821static struct clk wdt4_fck;
1822
1823static struct clk_hw_omap wdt4_fck_hw = {
1824 .hw = {
1825 .clk = &wdt4_fck,
1826 },
1827 .ops = &clkhwops_wait,
1828 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1829 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
1830 .clkdm_name = "core_l4_clkdm",
1831};
1832
1833DEFINE_STRUCT_CLK(wdt4_fck, gpio5_fck_parent_names, aes_ick_ops);
1834
1835static struct clk wdt4_ick;
1836
1837static struct clk_hw_omap wdt4_ick_hw = {
1838 .hw = {
1839 .clk = &wdt4_ick,
1840 },
1841 .ops = &clkhwops_iclk_wait,
1842 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1843 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
1844 .clkdm_name = "core_l4_clkdm",
1845};
1846
1847DEFINE_STRUCT_CLK(wdt4_ick, aes_ick_parent_names, aes_ick_ops);
1848
1849/*
1850 * clkdev integration
1851 */
1852
1853static struct omap_clk omap2430_clks[] = {
1854 /* external root sources */
1855 CLK(NULL, "func_32k_ck", &func_32k_ck, CK_243X),
1856 CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_243X),
1857 CLK(NULL, "osc_ck", &osc_ck, CK_243X),
1858 CLK("twl", "fck", &osc_ck, CK_243X),
1859 CLK(NULL, "sys_ck", &sys_ck, CK_243X),
1860 CLK(NULL, "alt_ck", &alt_ck, CK_243X),
1861 CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_243X),
1862 /* internal analog sources */
1863 CLK(NULL, "dpll_ck", &dpll_ck, CK_243X),
1864 CLK(NULL, "apll96_ck", &apll96_ck, CK_243X),
1865 CLK(NULL, "apll54_ck", &apll54_ck, CK_243X),
1866 /* internal prcm root sources */
1867 CLK(NULL, "func_54m_ck", &func_54m_ck, CK_243X),
1868 CLK(NULL, "core_ck", &core_ck, CK_243X),
1869 CLK(NULL, "func_96m_ck", &func_96m_ck, CK_243X),
1870 CLK(NULL, "func_48m_ck", &func_48m_ck, CK_243X),
1871 CLK(NULL, "func_12m_ck", &func_12m_ck, CK_243X),
1872 CLK(NULL, "ck_wdt1_osc", &wdt1_osc_ck, CK_243X),
1873 CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_243X),
1874 CLK(NULL, "sys_clkout", &sys_clkout, CK_243X),
1875 CLK(NULL, "emul_ck", &emul_ck, CK_243X),
1876 /* mpu domain clocks */
1877 CLK(NULL, "mpu_ck", &mpu_ck, CK_243X),
1878 /* dsp domain clocks */
1879 CLK(NULL, "dsp_fck", &dsp_fck, CK_243X),
1880 CLK(NULL, "iva2_1_ick", &iva2_1_ick, CK_243X),
1881 /* GFX domain clocks */
1882 CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_243X),
1883 CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_243X),
1884 CLK(NULL, "gfx_ick", &gfx_ick, CK_243X),
1885 /* Modem domain clocks */
1886 CLK(NULL, "mdm_ick", &mdm_ick, CK_243X),
1887 CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X),
1888 /* DSS domain clocks */
1889 CLK("omapdss_dss", "ick", &dss_ick, CK_243X),
1890 CLK(NULL, "dss_ick", &dss_ick, CK_243X),
1891 CLK(NULL, "dss1_fck", &dss1_fck, CK_243X),
1892 CLK(NULL, "dss2_fck", &dss2_fck, CK_243X),
1893 CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_243X),
1894 /* L3 domain clocks */
1895 CLK(NULL, "core_l3_ck", &core_l3_ck, CK_243X),
1896 CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_243X),
1897 CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_243X),
1898 /* L4 domain clocks */
1899 CLK(NULL, "l4_ck", &l4_ck, CK_243X),
1900 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_243X),
1901 CLK(NULL, "wu_l4_ick", &wu_l4_ick, CK_243X),
1902 /* virtual meta-group clock */
1903 CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_243X),
1904 /* general l4 interface ck, multi-parent functional clk */
1905 CLK(NULL, "gpt1_ick", &gpt1_ick, CK_243X),
1906 CLK(NULL, "gpt1_fck", &gpt1_fck, CK_243X),
1907 CLK(NULL, "gpt2_ick", &gpt2_ick, CK_243X),
1908 CLK(NULL, "gpt2_fck", &gpt2_fck, CK_243X),
1909 CLK(NULL, "gpt3_ick", &gpt3_ick, CK_243X),
1910 CLK(NULL, "gpt3_fck", &gpt3_fck, CK_243X),
1911 CLK(NULL, "gpt4_ick", &gpt4_ick, CK_243X),
1912 CLK(NULL, "gpt4_fck", &gpt4_fck, CK_243X),
1913 CLK(NULL, "gpt5_ick", &gpt5_ick, CK_243X),
1914 CLK(NULL, "gpt5_fck", &gpt5_fck, CK_243X),
1915 CLK(NULL, "gpt6_ick", &gpt6_ick, CK_243X),
1916 CLK(NULL, "gpt6_fck", &gpt6_fck, CK_243X),
1917 CLK(NULL, "gpt7_ick", &gpt7_ick, CK_243X),
1918 CLK(NULL, "gpt7_fck", &gpt7_fck, CK_243X),
1919 CLK(NULL, "gpt8_ick", &gpt8_ick, CK_243X),
1920 CLK(NULL, "gpt8_fck", &gpt8_fck, CK_243X),
1921 CLK(NULL, "gpt9_ick", &gpt9_ick, CK_243X),
1922 CLK(NULL, "gpt9_fck", &gpt9_fck, CK_243X),
1923 CLK(NULL, "gpt10_ick", &gpt10_ick, CK_243X),
1924 CLK(NULL, "gpt10_fck", &gpt10_fck, CK_243X),
1925 CLK(NULL, "gpt11_ick", &gpt11_ick, CK_243X),
1926 CLK(NULL, "gpt11_fck", &gpt11_fck, CK_243X),
1927 CLK(NULL, "gpt12_ick", &gpt12_ick, CK_243X),
1928 CLK(NULL, "gpt12_fck", &gpt12_fck, CK_243X),
1929 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_243X),
1930 CLK(NULL, "mcbsp1_ick", &mcbsp1_ick, CK_243X),
1931 CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_243X),
1932 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_243X),
1933 CLK(NULL, "mcbsp2_ick", &mcbsp2_ick, CK_243X),
1934 CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_243X),
1935 CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_243X),
1936 CLK(NULL, "mcbsp3_ick", &mcbsp3_ick, CK_243X),
1937 CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_243X),
1938 CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_243X),
1939 CLK(NULL, "mcbsp4_ick", &mcbsp4_ick, CK_243X),
1940 CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_243X),
1941 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_243X),
1942 CLK(NULL, "mcbsp5_ick", &mcbsp5_ick, CK_243X),
1943 CLK(NULL, "mcbsp5_fck", &mcbsp5_fck, CK_243X),
1944 CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_243X),
1945 CLK(NULL, "mcspi1_ick", &mcspi1_ick, CK_243X),
1946 CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_243X),
1947 CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_243X),
1948 CLK(NULL, "mcspi2_ick", &mcspi2_ick, CK_243X),
1949 CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_243X),
1950 CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_243X),
1951 CLK(NULL, "mcspi3_ick", &mcspi3_ick, CK_243X),
1952 CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_243X),
1953 CLK(NULL, "uart1_ick", &uart1_ick, CK_243X),
1954 CLK(NULL, "uart1_fck", &uart1_fck, CK_243X),
1955 CLK(NULL, "uart2_ick", &uart2_ick, CK_243X),
1956 CLK(NULL, "uart2_fck", &uart2_fck, CK_243X),
1957 CLK(NULL, "uart3_ick", &uart3_ick, CK_243X),
1958 CLK(NULL, "uart3_fck", &uart3_fck, CK_243X),
1959 CLK(NULL, "gpios_ick", &gpios_ick, CK_243X),
1960 CLK(NULL, "gpios_fck", &gpios_fck, CK_243X),
1961 CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_243X),
1962 CLK(NULL, "mpu_wdt_ick", &mpu_wdt_ick, CK_243X),
1963 CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck, CK_243X),
1964 CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_243X),
1965 CLK(NULL, "wdt1_ick", &wdt1_ick, CK_243X),
1966 CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_243X),
1967 CLK(NULL, "icr_ick", &icr_ick, CK_243X),
1968 CLK("omap24xxcam", "fck", &cam_fck, CK_243X),
1969 CLK(NULL, "cam_fck", &cam_fck, CK_243X),
1970 CLK("omap24xxcam", "ick", &cam_ick, CK_243X),
1971 CLK(NULL, "cam_ick", &cam_ick, CK_243X),
1972 CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_243X),
1973 CLK(NULL, "wdt4_ick", &wdt4_ick, CK_243X),
1974 CLK(NULL, "wdt4_fck", &wdt4_fck, CK_243X),
1975 CLK(NULL, "mspro_ick", &mspro_ick, CK_243X),
1976 CLK(NULL, "mspro_fck", &mspro_fck, CK_243X),
1977 CLK(NULL, "fac_ick", &fac_ick, CK_243X),
1978 CLK(NULL, "fac_fck", &fac_fck, CK_243X),
1979 CLK("omap_hdq.0", "ick", &hdq_ick, CK_243X),
1980 CLK(NULL, "hdq_ick", &hdq_ick, CK_243X),
1981 CLK("omap_hdq.1", "fck", &hdq_fck, CK_243X),
1982 CLK(NULL, "hdq_fck", &hdq_fck, CK_243X),
1983 CLK("omap_i2c.1", "ick", &i2c1_ick, CK_243X),
1984 CLK(NULL, "i2c1_ick", &i2c1_ick, CK_243X),
1985 CLK(NULL, "i2chs1_fck", &i2chs1_fck, CK_243X),
1986 CLK("omap_i2c.2", "ick", &i2c2_ick, CK_243X),
1987 CLK(NULL, "i2c2_ick", &i2c2_ick, CK_243X),
1988 CLK(NULL, "i2chs2_fck", &i2chs2_fck, CK_243X),
1989 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_243X),
1990 CLK(NULL, "sdma_fck", &sdma_fck, CK_243X),
1991 CLK(NULL, "sdma_ick", &sdma_ick, CK_243X),
1992 CLK(NULL, "sdrc_ick", &sdrc_ick, CK_243X),
1993 CLK(NULL, "des_ick", &des_ick, CK_243X),
1994 CLK("omap-sham", "ick", &sha_ick, CK_243X),
1995 CLK("omap_rng", "ick", &rng_ick, CK_243X),
1996 CLK(NULL, "rng_ick", &rng_ick, CK_243X),
1997 CLK("omap-aes", "ick", &aes_ick, CK_243X),
1998 CLK(NULL, "pka_ick", &pka_ick, CK_243X),
1999 CLK(NULL, "usb_fck", &usb_fck, CK_243X),
2000 CLK("musb-omap2430", "ick", &usbhs_ick, CK_243X),
2001 CLK(NULL, "usbhs_ick", &usbhs_ick, CK_243X),
2002 CLK("omap_hsmmc.0", "ick", &mmchs1_ick, CK_243X),
2003 CLK(NULL, "mmchs1_ick", &mmchs1_ick, CK_243X),
2004 CLK(NULL, "mmchs1_fck", &mmchs1_fck, CK_243X),
2005 CLK("omap_hsmmc.1", "ick", &mmchs2_ick, CK_243X),
2006 CLK(NULL, "mmchs2_ick", &mmchs2_ick, CK_243X),
2007 CLK(NULL, "mmchs2_fck", &mmchs2_fck, CK_243X),
2008 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_243X),
2009 CLK(NULL, "gpio5_fck", &gpio5_fck, CK_243X),
2010 CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X),
2011 CLK("omap_hsmmc.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X),
2012 CLK(NULL, "mmchsdb1_fck", &mmchsdb1_fck, CK_243X),
2013 CLK("omap_hsmmc.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X),
2014 CLK(NULL, "mmchsdb2_fck", &mmchsdb2_fck, CK_243X),
2015 CLK(NULL, "timer_32k_ck", &func_32k_ck, CK_243X),
2016 CLK(NULL, "timer_sys_ck", &sys_ck, CK_243X),
2017 CLK(NULL, "timer_ext_ck", &alt_ck, CK_243X),
2018 CLK(NULL, "cpufreq_ck", &virt_prcm_set, CK_243X),
2019};
2020
2021static const char *enable_init_clks[] = {
2022 "apll96_ck",
2023 "apll54_ck",
2024 "sync_32k_ick",
2025 "omapctrl_ick",
2026 "gpmc_fck",
2027 "sdrc_ick",
2028};
2029
2030/*
2031 * init code
2032 */
2033
2034int __init omap2430_clk_init(void)
2035{
2036 struct omap_clk *c;
2037
2038 prcm_clksrc_ctrl = OMAP2430_PRCM_CLKSRC_CTRL;
2039 cpu_mask = RATE_IN_243X;
2040 rate_table = omap2430_rate_table;
2041
2042 omap2xxx_clkt_dpllcore_init(&dpll_ck_hw.hw);
2043
2044 omap2xxx_clkt_vps_check_bootloader_rates();
2045
2046 for (c = omap2430_clks; c < omap2430_clks + ARRAY_SIZE(omap2430_clks);
2047 c++) {
2048 clkdev_add(&c->lk);
2049 if (!__clk_init(NULL, c->lk.clk))
2050 omap2_init_clk_hw_omap_clocks(c->lk.clk);
2051 }
2052
2053 omap2_clk_disable_autoidle_all();
2054
2055 omap2_clk_enable_init_clocks(enable_init_clks,
2056 ARRAY_SIZE(enable_init_clks));
2057
2058 pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n",
2059 (clk_get_rate(&sys_ck) / 1000000),
2060 (clk_get_rate(&sys_ck) / 100000) % 10,
2061 (clk_get_rate(&dpll_ck) / 1000000),
2062 (clk_get_rate(&mpu_ck) / 1000000));
2063
2064 return 0;
2065}
diff --git a/arch/arm/mach-omap2/cclock33xx_data.c b/arch/arm/mach-omap2/cclock33xx_data.c
new file mode 100644
index 000000000000..ea64ad606759
--- /dev/null
+++ b/arch/arm/mach-omap2/cclock33xx_data.c
@@ -0,0 +1,961 @@
1/*
2 * AM33XX Clock data
3 *
4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
5 * Vaibhav Hiremath <hvaibhav@ti.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
10 *
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/kernel.h>
18#include <linux/list.h>
19#include <linux/clk-private.h>
20#include <linux/clkdev.h>
21#include <linux/io.h>
22
23#include "am33xx.h"
24#include "soc.h"
25#include "iomap.h"
26#include "clock.h"
27#include "control.h"
28#include "cm.h"
29#include "cm33xx.h"
30#include "cm-regbits-33xx.h"
31#include "prm.h"
32
33/* Modulemode control */
34#define AM33XX_MODULEMODE_HWCTRL_SHIFT 0
35#define AM33XX_MODULEMODE_SWCTRL_SHIFT 1
36
37/*LIST_HEAD(clocks);*/
38
39/* Root clocks */
40
41/* RTC 32k */
42DEFINE_CLK_FIXED_RATE(clk_32768_ck, CLK_IS_ROOT, 32768, 0x0);
43
44/* On-Chip 32KHz RC OSC */
45DEFINE_CLK_FIXED_RATE(clk_rc32k_ck, CLK_IS_ROOT, 32000, 0x0);
46
47/* Crystal input clks */
48DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0);
49
50DEFINE_CLK_FIXED_RATE(virt_24000000_ck, CLK_IS_ROOT, 24000000, 0x0);
51
52DEFINE_CLK_FIXED_RATE(virt_25000000_ck, CLK_IS_ROOT, 25000000, 0x0);
53
54DEFINE_CLK_FIXED_RATE(virt_26000000_ck, CLK_IS_ROOT, 26000000, 0x0);
55
56/* Oscillator clock */
57/* 19.2, 24, 25 or 26 MHz */
58static const char *sys_clkin_ck_parents[] = {
59 "virt_19200000_ck", "virt_24000000_ck", "virt_25000000_ck",
60 "virt_26000000_ck",
61};
62
63/*
64 * sys_clk in: input to the dpll and also used as funtional clock for,
65 * adc_tsc, smartreflex0-1, timer1-7, mcasp0-1, dcan0-1, cefuse
66 *
67 */
68DEFINE_CLK_MUX(sys_clkin_ck, sys_clkin_ck_parents, NULL, 0x0,
69 AM33XX_CTRL_REGADDR(AM33XX_CONTROL_STATUS),
70 AM33XX_CONTROL_STATUS_SYSBOOT1_SHIFT,
71 AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH,
72 0, NULL);
73
74/* External clock - 12 MHz */
75DEFINE_CLK_FIXED_RATE(tclkin_ck, CLK_IS_ROOT, 12000000, 0x0);
76
77/* Module clocks and DPLL outputs */
78
79/* DPLL_CORE */
80static struct dpll_data dpll_core_dd = {
81 .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_CORE,
82 .clk_bypass = &sys_clkin_ck,
83 .clk_ref = &sys_clkin_ck,
84 .control_reg = AM33XX_CM_CLKMODE_DPLL_CORE,
85 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
86 .idlest_reg = AM33XX_CM_IDLEST_DPLL_CORE,
87 .mult_mask = AM33XX_DPLL_MULT_MASK,
88 .div1_mask = AM33XX_DPLL_DIV_MASK,
89 .enable_mask = AM33XX_DPLL_EN_MASK,
90 .idlest_mask = AM33XX_ST_DPLL_CLK_MASK,
91 .max_multiplier = 2047,
92 .max_divider = 128,
93 .min_divider = 1,
94};
95
96/* CLKDCOLDO output */
97static const char *dpll_core_ck_parents[] = {
98 "sys_clkin_ck",
99};
100
101static struct clk dpll_core_ck;
102
103static const struct clk_ops dpll_core_ck_ops = {
104 .recalc_rate = &omap3_dpll_recalc,
105 .get_parent = &omap2_init_dpll_parent,
106};
107
108static struct clk_hw_omap dpll_core_ck_hw = {
109 .hw = {
110 .clk = &dpll_core_ck,
111 },
112 .dpll_data = &dpll_core_dd,
113 .ops = &clkhwops_omap3_dpll,
114};
115
116DEFINE_STRUCT_CLK(dpll_core_ck, dpll_core_ck_parents, dpll_core_ck_ops);
117
118static const char *dpll_core_x2_ck_parents[] = {
119 "dpll_core_ck",
120};
121
122static struct clk dpll_core_x2_ck;
123
124static const struct clk_ops dpll_x2_ck_ops = {
125 .recalc_rate = &omap3_clkoutx2_recalc,
126};
127
128static struct clk_hw_omap dpll_core_x2_ck_hw = {
129 .hw = {
130 .clk = &dpll_core_x2_ck,
131 },
132 .flags = CLOCK_CLKOUTX2,
133};
134
135DEFINE_STRUCT_CLK(dpll_core_x2_ck, dpll_core_x2_ck_parents, dpll_x2_ck_ops);
136
137DEFINE_CLK_DIVIDER(dpll_core_m4_ck, "dpll_core_x2_ck", &dpll_core_x2_ck,
138 0x0, AM33XX_CM_DIV_M4_DPLL_CORE,
139 AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT,
140 AM33XX_HSDIVIDER_CLKOUT1_DIV_WIDTH, CLK_DIVIDER_ONE_BASED,
141 NULL);
142
143DEFINE_CLK_DIVIDER(dpll_core_m5_ck, "dpll_core_x2_ck", &dpll_core_x2_ck,
144 0x0, AM33XX_CM_DIV_M5_DPLL_CORE,
145 AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT,
146 AM33XX_HSDIVIDER_CLKOUT2_DIV_WIDTH,
147 CLK_DIVIDER_ONE_BASED, NULL);
148
149DEFINE_CLK_DIVIDER(dpll_core_m6_ck, "dpll_core_x2_ck", &dpll_core_x2_ck,
150 0x0, AM33XX_CM_DIV_M6_DPLL_CORE,
151 AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT,
152 AM33XX_HSDIVIDER_CLKOUT3_DIV_WIDTH,
153 CLK_DIVIDER_ONE_BASED, NULL);
154
155
156/* DPLL_MPU */
157static struct dpll_data dpll_mpu_dd = {
158 .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_MPU,
159 .clk_bypass = &sys_clkin_ck,
160 .clk_ref = &sys_clkin_ck,
161 .control_reg = AM33XX_CM_CLKMODE_DPLL_MPU,
162 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
163 .idlest_reg = AM33XX_CM_IDLEST_DPLL_MPU,
164 .mult_mask = AM33XX_DPLL_MULT_MASK,
165 .div1_mask = AM33XX_DPLL_DIV_MASK,
166 .enable_mask = AM33XX_DPLL_EN_MASK,
167 .idlest_mask = AM33XX_ST_DPLL_CLK_MASK,
168 .max_multiplier = 2047,
169 .max_divider = 128,
170 .min_divider = 1,
171};
172
173/* CLKOUT: fdpll/M2 */
174static struct clk dpll_mpu_ck;
175
176static const struct clk_ops dpll_mpu_ck_ops = {
177 .enable = &omap3_noncore_dpll_enable,
178 .disable = &omap3_noncore_dpll_disable,
179 .recalc_rate = &omap3_dpll_recalc,
180 .round_rate = &omap2_dpll_round_rate,
181 .set_rate = &omap3_noncore_dpll_set_rate,
182 .get_parent = &omap2_init_dpll_parent,
183};
184
185static struct clk_hw_omap dpll_mpu_ck_hw = {
186 .hw = {
187 .clk = &dpll_mpu_ck,
188 },
189 .dpll_data = &dpll_mpu_dd,
190 .ops = &clkhwops_omap3_dpll,
191};
192
193DEFINE_STRUCT_CLK(dpll_mpu_ck, dpll_core_ck_parents, dpll_mpu_ck_ops);
194
195/*
196 * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
197 * and ALT_CLK1/2)
198 */
199DEFINE_CLK_DIVIDER(dpll_mpu_m2_ck, "dpll_mpu_ck", &dpll_mpu_ck,
200 0x0, AM33XX_CM_DIV_M2_DPLL_MPU, AM33XX_DPLL_CLKOUT_DIV_SHIFT,
201 AM33XX_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
202
203/* DPLL_DDR */
204static struct dpll_data dpll_ddr_dd = {
205 .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_DDR,
206 .clk_bypass = &sys_clkin_ck,
207 .clk_ref = &sys_clkin_ck,
208 .control_reg = AM33XX_CM_CLKMODE_DPLL_DDR,
209 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
210 .idlest_reg = AM33XX_CM_IDLEST_DPLL_DDR,
211 .mult_mask = AM33XX_DPLL_MULT_MASK,
212 .div1_mask = AM33XX_DPLL_DIV_MASK,
213 .enable_mask = AM33XX_DPLL_EN_MASK,
214 .idlest_mask = AM33XX_ST_DPLL_CLK_MASK,
215 .max_multiplier = 2047,
216 .max_divider = 128,
217 .min_divider = 1,
218};
219
220/* CLKOUT: fdpll/M2 */
221static struct clk dpll_ddr_ck;
222
223static const struct clk_ops dpll_ddr_ck_ops = {
224 .recalc_rate = &omap3_dpll_recalc,
225 .get_parent = &omap2_init_dpll_parent,
226 .round_rate = &omap2_dpll_round_rate,
227 .set_rate = &omap3_noncore_dpll_set_rate,
228};
229
230static struct clk_hw_omap dpll_ddr_ck_hw = {
231 .hw = {
232 .clk = &dpll_ddr_ck,
233 },
234 .dpll_data = &dpll_ddr_dd,
235 .ops = &clkhwops_omap3_dpll,
236};
237
238DEFINE_STRUCT_CLK(dpll_ddr_ck, dpll_core_ck_parents, dpll_ddr_ck_ops);
239
240/*
241 * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
242 * and ALT_CLK1/2)
243 */
244DEFINE_CLK_DIVIDER(dpll_ddr_m2_ck, "dpll_ddr_ck", &dpll_ddr_ck,
245 0x0, AM33XX_CM_DIV_M2_DPLL_DDR,
246 AM33XX_DPLL_CLKOUT_DIV_SHIFT, AM33XX_DPLL_CLKOUT_DIV_WIDTH,
247 CLK_DIVIDER_ONE_BASED, NULL);
248
249/* emif_fck functional clock */
250DEFINE_CLK_FIXED_FACTOR(dpll_ddr_m2_div2_ck, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck,
251 0x0, 1, 2);
252
253/* DPLL_DISP */
254static struct dpll_data dpll_disp_dd = {
255 .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_DISP,
256 .clk_bypass = &sys_clkin_ck,
257 .clk_ref = &sys_clkin_ck,
258 .control_reg = AM33XX_CM_CLKMODE_DPLL_DISP,
259 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
260 .idlest_reg = AM33XX_CM_IDLEST_DPLL_DISP,
261 .mult_mask = AM33XX_DPLL_MULT_MASK,
262 .div1_mask = AM33XX_DPLL_DIV_MASK,
263 .enable_mask = AM33XX_DPLL_EN_MASK,
264 .idlest_mask = AM33XX_ST_DPLL_CLK_MASK,
265 .max_multiplier = 2047,
266 .max_divider = 128,
267 .min_divider = 1,
268};
269
270/* CLKOUT: fdpll/M2 */
271static struct clk dpll_disp_ck;
272
273static struct clk_hw_omap dpll_disp_ck_hw = {
274 .hw = {
275 .clk = &dpll_disp_ck,
276 },
277 .dpll_data = &dpll_disp_dd,
278 .ops = &clkhwops_omap3_dpll,
279};
280
281DEFINE_STRUCT_CLK(dpll_disp_ck, dpll_core_ck_parents, dpll_ddr_ck_ops);
282
283/*
284 * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
285 * and ALT_CLK1/2)
286 */
287DEFINE_CLK_DIVIDER(dpll_disp_m2_ck, "dpll_disp_ck", &dpll_disp_ck, 0x0,
288 AM33XX_CM_DIV_M2_DPLL_DISP, AM33XX_DPLL_CLKOUT_DIV_SHIFT,
289 AM33XX_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
290
291/* DPLL_PER */
292static struct dpll_data dpll_per_dd = {
293 .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_PERIPH,
294 .clk_bypass = &sys_clkin_ck,
295 .clk_ref = &sys_clkin_ck,
296 .control_reg = AM33XX_CM_CLKMODE_DPLL_PER,
297 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
298 .idlest_reg = AM33XX_CM_IDLEST_DPLL_PER,
299 .mult_mask = AM33XX_DPLL_MULT_PERIPH_MASK,
300 .div1_mask = AM33XX_DPLL_PER_DIV_MASK,
301 .enable_mask = AM33XX_DPLL_EN_MASK,
302 .idlest_mask = AM33XX_ST_DPLL_CLK_MASK,
303 .max_multiplier = 2047,
304 .max_divider = 128,
305 .min_divider = 1,
306 .flags = DPLL_J_TYPE,
307};
308
309/* CLKDCOLDO */
310static struct clk dpll_per_ck;
311
312static struct clk_hw_omap dpll_per_ck_hw = {
313 .hw = {
314 .clk = &dpll_per_ck,
315 },
316 .dpll_data = &dpll_per_dd,
317 .ops = &clkhwops_omap3_dpll,
318};
319
320DEFINE_STRUCT_CLK(dpll_per_ck, dpll_core_ck_parents, dpll_ddr_ck_ops);
321
322/* CLKOUT: fdpll/M2 */
323DEFINE_CLK_DIVIDER(dpll_per_m2_ck, "dpll_per_ck", &dpll_per_ck, 0x0,
324 AM33XX_CM_DIV_M2_DPLL_PER, AM33XX_DPLL_CLKOUT_DIV_SHIFT,
325 AM33XX_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED,
326 NULL);
327
328DEFINE_CLK_FIXED_FACTOR(dpll_per_m2_div4_wkupdm_ck, "dpll_per_m2_ck",
329 &dpll_per_m2_ck, 0x0, 1, 4);
330
331DEFINE_CLK_FIXED_FACTOR(dpll_per_m2_div4_ck, "dpll_per_m2_ck",
332 &dpll_per_m2_ck, 0x0, 1, 4);
333
334DEFINE_CLK_FIXED_FACTOR(dpll_core_m4_div2_ck, "dpll_core_m4_ck",
335 &dpll_core_m4_ck, 0x0, 1, 2);
336
337DEFINE_CLK_FIXED_FACTOR(l4_rtc_gclk, "dpll_core_m4_ck", &dpll_core_m4_ck, 0x0,
338 1, 2);
339
340DEFINE_CLK_FIXED_FACTOR(clk_24mhz, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0, 1,
341 8);
342
343/*
344 * Below clock nodes describes clockdomains derived out
345 * of core clock.
346 */
347static const struct clk_ops clk_ops_null = {
348};
349
350static const char *l3_gclk_parents[] = {
351 "dpll_core_m4_ck"
352};
353
354static struct clk l3_gclk;
355DEFINE_STRUCT_CLK_HW_OMAP(l3_gclk, NULL);
356DEFINE_STRUCT_CLK(l3_gclk, l3_gclk_parents, clk_ops_null);
357
358static struct clk l4hs_gclk;
359DEFINE_STRUCT_CLK_HW_OMAP(l4hs_gclk, NULL);
360DEFINE_STRUCT_CLK(l4hs_gclk, l3_gclk_parents, clk_ops_null);
361
362static const char *l3s_gclk_parents[] = {
363 "dpll_core_m4_div2_ck"
364};
365
366static struct clk l3s_gclk;
367DEFINE_STRUCT_CLK_HW_OMAP(l3s_gclk, NULL);
368DEFINE_STRUCT_CLK(l3s_gclk, l3s_gclk_parents, clk_ops_null);
369
370static struct clk l4fw_gclk;
371DEFINE_STRUCT_CLK_HW_OMAP(l4fw_gclk, NULL);
372DEFINE_STRUCT_CLK(l4fw_gclk, l3s_gclk_parents, clk_ops_null);
373
374static struct clk l4ls_gclk;
375DEFINE_STRUCT_CLK_HW_OMAP(l4ls_gclk, NULL);
376DEFINE_STRUCT_CLK(l4ls_gclk, l3s_gclk_parents, clk_ops_null);
377
378static struct clk sysclk_div_ck;
379DEFINE_STRUCT_CLK_HW_OMAP(sysclk_div_ck, NULL);
380DEFINE_STRUCT_CLK(sysclk_div_ck, l3_gclk_parents, clk_ops_null);
381
382/*
383 * In order to match the clock domain with hwmod clockdomain entry,
384 * separate clock nodes is required for the modules which are
385 * directly getting their funtioncal clock from sys_clkin.
386 */
387static struct clk adc_tsc_fck;
388DEFINE_STRUCT_CLK_HW_OMAP(adc_tsc_fck, NULL);
389DEFINE_STRUCT_CLK(adc_tsc_fck, dpll_core_ck_parents, clk_ops_null);
390
391static struct clk dcan0_fck;
392DEFINE_STRUCT_CLK_HW_OMAP(dcan0_fck, NULL);
393DEFINE_STRUCT_CLK(dcan0_fck, dpll_core_ck_parents, clk_ops_null);
394
395static struct clk dcan1_fck;
396DEFINE_STRUCT_CLK_HW_OMAP(dcan1_fck, NULL);
397DEFINE_STRUCT_CLK(dcan1_fck, dpll_core_ck_parents, clk_ops_null);
398
399static struct clk mcasp0_fck;
400DEFINE_STRUCT_CLK_HW_OMAP(mcasp0_fck, NULL);
401DEFINE_STRUCT_CLK(mcasp0_fck, dpll_core_ck_parents, clk_ops_null);
402
403static struct clk mcasp1_fck;
404DEFINE_STRUCT_CLK_HW_OMAP(mcasp1_fck, NULL);
405DEFINE_STRUCT_CLK(mcasp1_fck, dpll_core_ck_parents, clk_ops_null);
406
407static struct clk smartreflex0_fck;
408DEFINE_STRUCT_CLK_HW_OMAP(smartreflex0_fck, NULL);
409DEFINE_STRUCT_CLK(smartreflex0_fck, dpll_core_ck_parents, clk_ops_null);
410
411static struct clk smartreflex1_fck;
412DEFINE_STRUCT_CLK_HW_OMAP(smartreflex1_fck, NULL);
413DEFINE_STRUCT_CLK(smartreflex1_fck, dpll_core_ck_parents, clk_ops_null);
414
415/*
416 * Modules clock nodes
417 *
418 * The following clock leaf nodes are added for the moment because:
419 *
420 * - hwmod data is not present for these modules, either hwmod
421 * control is not required or its not populated.
422 * - Driver code is not yet migrated to use hwmod/runtime pm
423 * - Modules outside kernel access (to disable them by default)
424 *
425 * - debugss
426 * - mmu (gfx domain)
427 * - cefuse
428 * - usbotg_fck (its additional clock and not really a modulemode)
429 * - ieee5000
430 */
431DEFINE_CLK_GATE(debugss_ick, "dpll_core_m4_ck", &dpll_core_m4_ck, 0x0,
432 AM33XX_CM_WKUP_DEBUGSS_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT,
433 0x0, NULL);
434
435DEFINE_CLK_GATE(mmu_fck, "dpll_core_m4_ck", &dpll_core_m4_ck, 0x0,
436 AM33XX_CM_GFX_MMUDATA_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT,
437 0x0, NULL);
438
439DEFINE_CLK_GATE(cefuse_fck, "sys_clkin_ck", &sys_clkin_ck, 0x0,
440 AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT,
441 0x0, NULL);
442
443/*
444 * clkdiv32 is generated from fixed division of 732.4219
445 */
446DEFINE_CLK_FIXED_FACTOR(clkdiv32k_ck, "clk_24mhz", &clk_24mhz, 0x0, 1, 732);
447
448DEFINE_CLK_GATE(clkdiv32k_ick, "clkdiv32k_ck", &clkdiv32k_ck, 0x0,
449 AM33XX_CM_PER_CLKDIV32K_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT,
450 0x0, NULL);
451
452/* "usbotg_fck" is an additional clock and not really a modulemode */
453DEFINE_CLK_GATE(usbotg_fck, "dpll_per_ck", &dpll_per_ck, 0x0,
454 AM33XX_CM_CLKDCOLDO_DPLL_PER, AM33XX_ST_DPLL_CLKDCOLDO_SHIFT,
455 0x0, NULL);
456
457DEFINE_CLK_GATE(ieee5000_fck, "dpll_core_m4_div2_ck", &dpll_core_m4_div2_ck,
458 0x0, AM33XX_CM_PER_IEEE5000_CLKCTRL,
459 AM33XX_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
460
461/* Timers */
462static const struct clksel timer1_clkmux_sel[] = {
463 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
464 { .parent = &clkdiv32k_ick, .rates = div_1_1_rates },
465 { .parent = &tclkin_ck, .rates = div_1_2_rates },
466 { .parent = &clk_rc32k_ck, .rates = div_1_3_rates },
467 { .parent = &clk_32768_ck, .rates = div_1_4_rates },
468 { .parent = NULL },
469};
470
471static const char *timer1_ck_parents[] = {
472 "sys_clkin_ck", "clkdiv32k_ick", "tclkin_ck", "clk_rc32k_ck",
473 "clk_32768_ck",
474};
475
476static struct clk timer1_fck;
477
478static const struct clk_ops timer1_fck_ops = {
479 .recalc_rate = &omap2_clksel_recalc,
480 .get_parent = &omap2_clksel_find_parent_index,
481 .set_parent = &omap2_clksel_set_parent,
482 .init = &omap2_init_clk_clkdm,
483};
484
485static struct clk_hw_omap timer1_fck_hw = {
486 .hw = {
487 .clk = &timer1_fck,
488 },
489 .clkdm_name = "l4ls_clkdm",
490 .clksel = timer1_clkmux_sel,
491 .clksel_reg = AM33XX_CLKSEL_TIMER1MS_CLK,
492 .clksel_mask = AM33XX_CLKSEL_0_2_MASK,
493};
494
495DEFINE_STRUCT_CLK(timer1_fck, timer1_ck_parents, timer1_fck_ops);
496
497static const struct clksel timer2_to_7_clk_sel[] = {
498 { .parent = &tclkin_ck, .rates = div_1_0_rates },
499 { .parent = &sys_clkin_ck, .rates = div_1_1_rates },
500 { .parent = &clkdiv32k_ick, .rates = div_1_2_rates },
501 { .parent = NULL },
502};
503
504static const char *timer2_to_7_ck_parents[] = {
505 "tclkin_ck", "sys_clkin_ck", "clkdiv32k_ick",
506};
507
508static struct clk timer2_fck;
509
510static struct clk_hw_omap timer2_fck_hw = {
511 .hw = {
512 .clk = &timer2_fck,
513 },
514 .clkdm_name = "l4ls_clkdm",
515 .clksel = timer2_to_7_clk_sel,
516 .clksel_reg = AM33XX_CLKSEL_TIMER2_CLK,
517 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
518};
519
520DEFINE_STRUCT_CLK(timer2_fck, timer2_to_7_ck_parents, timer1_fck_ops);
521
522static struct clk timer3_fck;
523
524static struct clk_hw_omap timer3_fck_hw = {
525 .hw = {
526 .clk = &timer3_fck,
527 },
528 .clkdm_name = "l4ls_clkdm",
529 .clksel = timer2_to_7_clk_sel,
530 .clksel_reg = AM33XX_CLKSEL_TIMER3_CLK,
531 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
532};
533
534DEFINE_STRUCT_CLK(timer3_fck, timer2_to_7_ck_parents, timer1_fck_ops);
535
536static struct clk timer4_fck;
537
538static struct clk_hw_omap timer4_fck_hw = {
539 .hw = {
540 .clk = &timer4_fck,
541 },
542 .clkdm_name = "l4ls_clkdm",
543 .clksel = timer2_to_7_clk_sel,
544 .clksel_reg = AM33XX_CLKSEL_TIMER4_CLK,
545 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
546};
547
548DEFINE_STRUCT_CLK(timer4_fck, timer2_to_7_ck_parents, timer1_fck_ops);
549
550static struct clk timer5_fck;
551
552static struct clk_hw_omap timer5_fck_hw = {
553 .hw = {
554 .clk = &timer5_fck,
555 },
556 .clkdm_name = "l4ls_clkdm",
557 .clksel = timer2_to_7_clk_sel,
558 .clksel_reg = AM33XX_CLKSEL_TIMER5_CLK,
559 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
560};
561
562DEFINE_STRUCT_CLK(timer5_fck, timer2_to_7_ck_parents, timer1_fck_ops);
563
564static struct clk timer6_fck;
565
566static struct clk_hw_omap timer6_fck_hw = {
567 .hw = {
568 .clk = &timer6_fck,
569 },
570 .clkdm_name = "l4ls_clkdm",
571 .clksel = timer2_to_7_clk_sel,
572 .clksel_reg = AM33XX_CLKSEL_TIMER6_CLK,
573 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
574};
575
576DEFINE_STRUCT_CLK(timer6_fck, timer2_to_7_ck_parents, timer1_fck_ops);
577
578static struct clk timer7_fck;
579
580static struct clk_hw_omap timer7_fck_hw = {
581 .hw = {
582 .clk = &timer7_fck,
583 },
584 .clkdm_name = "l4ls_clkdm",
585 .clksel = timer2_to_7_clk_sel,
586 .clksel_reg = AM33XX_CLKSEL_TIMER7_CLK,
587 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
588};
589
590DEFINE_STRUCT_CLK(timer7_fck, timer2_to_7_ck_parents, timer1_fck_ops);
591
592DEFINE_CLK_FIXED_FACTOR(cpsw_125mhz_gclk,
593 "dpll_core_m5_ck",
594 &dpll_core_m5_ck,
595 0x0,
596 1, 2);
597
598static const struct clk_ops cpsw_fck_ops = {
599 .recalc_rate = &omap2_clksel_recalc,
600 .get_parent = &omap2_clksel_find_parent_index,
601 .set_parent = &omap2_clksel_set_parent,
602};
603
604static const struct clksel cpsw_cpts_rft_clkmux_sel[] = {
605 { .parent = &dpll_core_m5_ck, .rates = div_1_0_rates },
606 { .parent = &dpll_core_m4_ck, .rates = div_1_1_rates },
607 { .parent = NULL },
608};
609
610static const char *cpsw_cpts_rft_ck_parents[] = {
611 "dpll_core_m5_ck", "dpll_core_m4_ck",
612};
613
614static struct clk cpsw_cpts_rft_clk;
615
616static struct clk_hw_omap cpsw_cpts_rft_clk_hw = {
617 .hw = {
618 .clk = &cpsw_cpts_rft_clk,
619 },
620 .clkdm_name = "cpsw_125mhz_clkdm",
621 .clksel = cpsw_cpts_rft_clkmux_sel,
622 .clksel_reg = AM33XX_CM_CPTS_RFT_CLKSEL,
623 .clksel_mask = AM33XX_CLKSEL_0_0_MASK,
624};
625
626DEFINE_STRUCT_CLK(cpsw_cpts_rft_clk, cpsw_cpts_rft_ck_parents, cpsw_fck_ops);
627
628
629/* gpio */
630static const char *gpio0_ck_parents[] = {
631 "clk_rc32k_ck", "clk_32768_ck", "clkdiv32k_ick",
632};
633
634static const struct clksel gpio0_dbclk_mux_sel[] = {
635 { .parent = &clk_rc32k_ck, .rates = div_1_0_rates },
636 { .parent = &clk_32768_ck, .rates = div_1_1_rates },
637 { .parent = &clkdiv32k_ick, .rates = div_1_2_rates },
638 { .parent = NULL },
639};
640
641static const struct clk_ops gpio_fck_ops = {
642 .recalc_rate = &omap2_clksel_recalc,
643 .get_parent = &omap2_clksel_find_parent_index,
644 .set_parent = &omap2_clksel_set_parent,
645 .init = &omap2_init_clk_clkdm,
646};
647
648static struct clk gpio0_dbclk_mux_ck;
649
650static struct clk_hw_omap gpio0_dbclk_mux_ck_hw = {
651 .hw = {
652 .clk = &gpio0_dbclk_mux_ck,
653 },
654 .clkdm_name = "l4_wkup_clkdm",
655 .clksel = gpio0_dbclk_mux_sel,
656 .clksel_reg = AM33XX_CLKSEL_GPIO0_DBCLK,
657 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
658};
659
660DEFINE_STRUCT_CLK(gpio0_dbclk_mux_ck, gpio0_ck_parents, gpio_fck_ops);
661
662DEFINE_CLK_GATE(gpio0_dbclk, "gpio0_dbclk_mux_ck", &gpio0_dbclk_mux_ck, 0x0,
663 AM33XX_CM_WKUP_GPIO0_CLKCTRL,
664 AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT, 0x0, NULL);
665
666DEFINE_CLK_GATE(gpio1_dbclk, "clkdiv32k_ick", &clkdiv32k_ick, 0x0,
667 AM33XX_CM_PER_GPIO1_CLKCTRL,
668 AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT, 0x0, NULL);
669
670DEFINE_CLK_GATE(gpio2_dbclk, "clkdiv32k_ick", &clkdiv32k_ick, 0x0,
671 AM33XX_CM_PER_GPIO2_CLKCTRL,
672 AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT, 0x0, NULL);
673
674DEFINE_CLK_GATE(gpio3_dbclk, "clkdiv32k_ick", &clkdiv32k_ick, 0x0,
675 AM33XX_CM_PER_GPIO3_CLKCTRL,
676 AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT, 0x0, NULL);
677
678
679static const char *pruss_ck_parents[] = {
680 "l3_gclk", "dpll_disp_m2_ck",
681};
682
683static const struct clksel pruss_ocp_clk_mux_sel[] = {
684 { .parent = &l3_gclk, .rates = div_1_0_rates },
685 { .parent = &dpll_disp_m2_ck, .rates = div_1_1_rates },
686 { .parent = NULL },
687};
688
689static struct clk pruss_ocp_gclk;
690
691static struct clk_hw_omap pruss_ocp_gclk_hw = {
692 .hw = {
693 .clk = &pruss_ocp_gclk,
694 },
695 .clkdm_name = "pruss_ocp_clkdm",
696 .clksel = pruss_ocp_clk_mux_sel,
697 .clksel_reg = AM33XX_CLKSEL_PRUSS_OCP_CLK,
698 .clksel_mask = AM33XX_CLKSEL_0_0_MASK,
699};
700
701DEFINE_STRUCT_CLK(pruss_ocp_gclk, pruss_ck_parents, gpio_fck_ops);
702
703static const char *lcd_ck_parents[] = {
704 "dpll_disp_m2_ck", "dpll_core_m5_ck", "dpll_per_m2_ck",
705};
706
707static const struct clksel lcd_clk_mux_sel[] = {
708 { .parent = &dpll_disp_m2_ck, .rates = div_1_0_rates },
709 { .parent = &dpll_core_m5_ck, .rates = div_1_1_rates },
710 { .parent = &dpll_per_m2_ck, .rates = div_1_2_rates },
711 { .parent = NULL },
712};
713
714static struct clk lcd_gclk;
715
716static struct clk_hw_omap lcd_gclk_hw = {
717 .hw = {
718 .clk = &lcd_gclk,
719 },
720 .clkdm_name = "lcdc_clkdm",
721 .clksel = lcd_clk_mux_sel,
722 .clksel_reg = AM33XX_CLKSEL_LCDC_PIXEL_CLK,
723 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
724};
725
726DEFINE_STRUCT_CLK(lcd_gclk, lcd_ck_parents, gpio_fck_ops);
727
728DEFINE_CLK_FIXED_FACTOR(mmc_clk, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0, 1, 2);
729
730static const char *gfx_ck_parents[] = {
731 "dpll_core_m4_ck", "dpll_per_m2_ck",
732};
733
734static const struct clksel gfx_clksel_sel[] = {
735 { .parent = &dpll_core_m4_ck, .rates = div_1_0_rates },
736 { .parent = &dpll_per_m2_ck, .rates = div_1_1_rates },
737 { .parent = NULL },
738};
739
740static struct clk gfx_fclk_clksel_ck;
741
742static struct clk_hw_omap gfx_fclk_clksel_ck_hw = {
743 .hw = {
744 .clk = &gfx_fclk_clksel_ck,
745 },
746 .clksel = gfx_clksel_sel,
747 .clksel_reg = AM33XX_CLKSEL_GFX_FCLK,
748 .clksel_mask = AM33XX_CLKSEL_GFX_FCLK_MASK,
749};
750
751DEFINE_STRUCT_CLK(gfx_fclk_clksel_ck, gfx_ck_parents, gpio_fck_ops);
752
753static const struct clk_div_table div_1_0_2_1_rates[] = {
754 { .div = 1, .val = 0, },
755 { .div = 2, .val = 1, },
756 { .div = 0 },
757};
758
759DEFINE_CLK_DIVIDER_TABLE(gfx_fck_div_ck, "gfx_fclk_clksel_ck",
760 &gfx_fclk_clksel_ck, 0x0, AM33XX_CLKSEL_GFX_FCLK,
761 AM33XX_CLKSEL_0_0_SHIFT, AM33XX_CLKSEL_0_0_WIDTH,
762 0x0, div_1_0_2_1_rates, NULL);
763
764static const char *sysclkout_ck_parents[] = {
765 "clk_32768_ck", "l3_gclk", "dpll_ddr_m2_ck", "dpll_per_m2_ck",
766 "lcd_gclk",
767};
768
769static const struct clksel sysclkout_pre_sel[] = {
770 { .parent = &clk_32768_ck, .rates = div_1_0_rates },
771 { .parent = &l3_gclk, .rates = div_1_1_rates },
772 { .parent = &dpll_ddr_m2_ck, .rates = div_1_2_rates },
773 { .parent = &dpll_per_m2_ck, .rates = div_1_3_rates },
774 { .parent = &lcd_gclk, .rates = div_1_4_rates },
775 { .parent = NULL },
776};
777
778static struct clk sysclkout_pre_ck;
779
780static struct clk_hw_omap sysclkout_pre_ck_hw = {
781 .hw = {
782 .clk = &sysclkout_pre_ck,
783 },
784 .clksel = sysclkout_pre_sel,
785 .clksel_reg = AM33XX_CM_CLKOUT_CTRL,
786 .clksel_mask = AM33XX_CLKOUT2SOURCE_MASK,
787};
788
789DEFINE_STRUCT_CLK(sysclkout_pre_ck, sysclkout_ck_parents, gpio_fck_ops);
790
791/* Divide by 8 clock rates with default clock is 1/1*/
792static const struct clk_div_table div8_rates[] = {
793 { .div = 1, .val = 0, },
794 { .div = 2, .val = 1, },
795 { .div = 3, .val = 2, },
796 { .div = 4, .val = 3, },
797 { .div = 5, .val = 4, },
798 { .div = 6, .val = 5, },
799 { .div = 7, .val = 6, },
800 { .div = 8, .val = 7, },
801 { .div = 0 },
802};
803
804DEFINE_CLK_DIVIDER_TABLE(clkout2_div_ck, "sysclkout_pre_ck", &sysclkout_pre_ck,
805 0x0, AM33XX_CM_CLKOUT_CTRL, AM33XX_CLKOUT2DIV_SHIFT,
806 AM33XX_CLKOUT2DIV_WIDTH, 0x0, div8_rates, NULL);
807
808DEFINE_CLK_GATE(clkout2_ck, "clkout2_div_ck", &clkout2_div_ck, 0x0,
809 AM33XX_CM_CLKOUT_CTRL, AM33XX_CLKOUT2EN_SHIFT, 0x0, NULL);
810
811static const char *wdt_ck_parents[] = {
812 "clk_rc32k_ck", "clkdiv32k_ick",
813};
814
815static const struct clksel wdt_clkmux_sel[] = {
816 { .parent = &clk_rc32k_ck, .rates = div_1_0_rates },
817 { .parent = &clkdiv32k_ick, .rates = div_1_1_rates },
818 { .parent = NULL },
819};
820
821static struct clk wdt1_fck;
822
823static struct clk_hw_omap wdt1_fck_hw = {
824 .hw = {
825 .clk = &wdt1_fck,
826 },
827 .clkdm_name = "l4_wkup_clkdm",
828 .clksel = wdt_clkmux_sel,
829 .clksel_reg = AM33XX_CLKSEL_WDT1_CLK,
830 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
831};
832
833DEFINE_STRUCT_CLK(wdt1_fck, wdt_ck_parents, gpio_fck_ops);
834
835/*
836 * clkdev
837 */
838static struct omap_clk am33xx_clks[] = {
839 CLK(NULL, "clk_32768_ck", &clk_32768_ck, CK_AM33XX),
840 CLK(NULL, "clk_rc32k_ck", &clk_rc32k_ck, CK_AM33XX),
841 CLK(NULL, "virt_19200000_ck", &virt_19200000_ck, CK_AM33XX),
842 CLK(NULL, "virt_24000000_ck", &virt_24000000_ck, CK_AM33XX),
843 CLK(NULL, "virt_25000000_ck", &virt_25000000_ck, CK_AM33XX),
844 CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_AM33XX),
845 CLK(NULL, "sys_clkin_ck", &sys_clkin_ck, CK_AM33XX),
846 CLK(NULL, "tclkin_ck", &tclkin_ck, CK_AM33XX),
847 CLK(NULL, "dpll_core_ck", &dpll_core_ck, CK_AM33XX),
848 CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck, CK_AM33XX),
849 CLK(NULL, "dpll_core_m4_ck", &dpll_core_m4_ck, CK_AM33XX),
850 CLK(NULL, "dpll_core_m5_ck", &dpll_core_m5_ck, CK_AM33XX),
851 CLK(NULL, "dpll_core_m6_ck", &dpll_core_m6_ck, CK_AM33XX),
852 CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_AM33XX),
853 CLK("cpu0", NULL, &dpll_mpu_ck, CK_AM33XX),
854 CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_AM33XX),
855 CLK(NULL, "dpll_ddr_ck", &dpll_ddr_ck, CK_AM33XX),
856 CLK(NULL, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck, CK_AM33XX),
857 CLK(NULL, "dpll_ddr_m2_div2_ck", &dpll_ddr_m2_div2_ck, CK_AM33XX),
858 CLK(NULL, "dpll_disp_ck", &dpll_disp_ck, CK_AM33XX),
859 CLK(NULL, "dpll_disp_m2_ck", &dpll_disp_m2_ck, CK_AM33XX),
860 CLK(NULL, "dpll_per_ck", &dpll_per_ck, CK_AM33XX),
861 CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck, CK_AM33XX),
862 CLK(NULL, "dpll_per_m2_div4_wkupdm_ck", &dpll_per_m2_div4_wkupdm_ck, CK_AM33XX),
863 CLK(NULL, "dpll_per_m2_div4_ck", &dpll_per_m2_div4_ck, CK_AM33XX),
864 CLK(NULL, "adc_tsc_fck", &adc_tsc_fck, CK_AM33XX),
865 CLK(NULL, "cefuse_fck", &cefuse_fck, CK_AM33XX),
866 CLK(NULL, "clkdiv32k_ck", &clkdiv32k_ck, CK_AM33XX),
867 CLK(NULL, "clkdiv32k_ick", &clkdiv32k_ick, CK_AM33XX),
868 CLK(NULL, "dcan0_fck", &dcan0_fck, CK_AM33XX),
869 CLK("481cc000.d_can", NULL, &dcan0_fck, CK_AM33XX),
870 CLK(NULL, "dcan1_fck", &dcan1_fck, CK_AM33XX),
871 CLK("481d0000.d_can", NULL, &dcan1_fck, CK_AM33XX),
872 CLK(NULL, "debugss_ick", &debugss_ick, CK_AM33XX),
873 CLK(NULL, "pruss_ocp_gclk", &pruss_ocp_gclk, CK_AM33XX),
874 CLK(NULL, "mcasp0_fck", &mcasp0_fck, CK_AM33XX),
875 CLK(NULL, "mcasp1_fck", &mcasp1_fck, CK_AM33XX),
876 CLK(NULL, "mmu_fck", &mmu_fck, CK_AM33XX),
877 CLK(NULL, "smartreflex0_fck", &smartreflex0_fck, CK_AM33XX),
878 CLK(NULL, "smartreflex1_fck", &smartreflex1_fck, CK_AM33XX),
879 CLK(NULL, "timer1_fck", &timer1_fck, CK_AM33XX),
880 CLK(NULL, "timer2_fck", &timer2_fck, CK_AM33XX),
881 CLK(NULL, "timer3_fck", &timer3_fck, CK_AM33XX),
882 CLK(NULL, "timer4_fck", &timer4_fck, CK_AM33XX),
883 CLK(NULL, "timer5_fck", &timer5_fck, CK_AM33XX),
884 CLK(NULL, "timer6_fck", &timer6_fck, CK_AM33XX),
885 CLK(NULL, "timer7_fck", &timer7_fck, CK_AM33XX),
886 CLK(NULL, "usbotg_fck", &usbotg_fck, CK_AM33XX),
887 CLK(NULL, "ieee5000_fck", &ieee5000_fck, CK_AM33XX),
888 CLK(NULL, "wdt1_fck", &wdt1_fck, CK_AM33XX),
889 CLK(NULL, "l4_rtc_gclk", &l4_rtc_gclk, CK_AM33XX),
890 CLK(NULL, "l3_gclk", &l3_gclk, CK_AM33XX),
891 CLK(NULL, "dpll_core_m4_div2_ck", &dpll_core_m4_div2_ck, CK_AM33XX),
892 CLK(NULL, "l4hs_gclk", &l4hs_gclk, CK_AM33XX),
893 CLK(NULL, "l3s_gclk", &l3s_gclk, CK_AM33XX),
894 CLK(NULL, "l4fw_gclk", &l4fw_gclk, CK_AM33XX),
895 CLK(NULL, "l4ls_gclk", &l4ls_gclk, CK_AM33XX),
896 CLK(NULL, "clk_24mhz", &clk_24mhz, CK_AM33XX),
897 CLK(NULL, "sysclk_div_ck", &sysclk_div_ck, CK_AM33XX),
898 CLK(NULL, "cpsw_125mhz_gclk", &cpsw_125mhz_gclk, CK_AM33XX),
899 CLK(NULL, "cpsw_cpts_rft_clk", &cpsw_cpts_rft_clk, CK_AM33XX),
900 CLK(NULL, "gpio0_dbclk_mux_ck", &gpio0_dbclk_mux_ck, CK_AM33XX),
901 CLK(NULL, "gpio0_dbclk", &gpio0_dbclk, CK_AM33XX),
902 CLK(NULL, "gpio1_dbclk", &gpio1_dbclk, CK_AM33XX),
903 CLK(NULL, "gpio2_dbclk", &gpio2_dbclk, CK_AM33XX),
904 CLK(NULL, "gpio3_dbclk", &gpio3_dbclk, CK_AM33XX),
905 CLK(NULL, "lcd_gclk", &lcd_gclk, CK_AM33XX),
906 CLK(NULL, "mmc_clk", &mmc_clk, CK_AM33XX),
907 CLK(NULL, "gfx_fclk_clksel_ck", &gfx_fclk_clksel_ck, CK_AM33XX),
908 CLK(NULL, "gfx_fck_div_ck", &gfx_fck_div_ck, CK_AM33XX),
909 CLK(NULL, "sysclkout_pre_ck", &sysclkout_pre_ck, CK_AM33XX),
910 CLK(NULL, "clkout2_div_ck", &clkout2_div_ck, CK_AM33XX),
911 CLK(NULL, "timer_32k_ck", &clkdiv32k_ick, CK_AM33XX),
912 CLK(NULL, "timer_sys_ck", &sys_clkin_ck, CK_AM33XX),
913};
914
915
916static const char *enable_init_clks[] = {
917 "dpll_ddr_m2_ck",
918 "dpll_mpu_m2_ck",
919 "l3_gclk",
920 "l4hs_gclk",
921 "l4fw_gclk",
922 "l4ls_gclk",
923};
924
925int __init am33xx_clk_init(void)
926{
927 struct omap_clk *c;
928 u32 cpu_clkflg;
929
930 if (soc_is_am33xx()) {
931 cpu_mask = RATE_IN_AM33XX;
932 cpu_clkflg = CK_AM33XX;
933 }
934
935 for (c = am33xx_clks; c < am33xx_clks + ARRAY_SIZE(am33xx_clks); c++) {
936 if (c->cpu & cpu_clkflg) {
937 clkdev_add(&c->lk);
938 if (!__clk_init(NULL, c->lk.clk))
939 omap2_init_clk_hw_omap_clocks(c->lk.clk);
940 }
941 }
942
943 omap2_clk_disable_autoidle_all();
944
945 omap2_clk_enable_init_clocks(enable_init_clks,
946 ARRAY_SIZE(enable_init_clks));
947
948 /* TRM ERRATA: Timer 3 & 6 default parent (TCLKIN) may not be always
949 * physically present, in such a case HWMOD enabling of
950 * clock would be failure with default parent. And timer
951 * probe thinks clock is already enabled, this leads to
952 * crash upon accessing timer 3 & 6 registers in probe.
953 * Fix by setting parent of both these timers to master
954 * oscillator clock.
955 */
956
957 clk_set_parent(&timer3_fck, &sys_clkin_ck);
958 clk_set_parent(&timer6_fck, &sys_clkin_ck);
959
960 return 0;
961}
diff --git a/arch/arm/mach-omap2/cclock3xxx_data.c b/arch/arm/mach-omap2/cclock3xxx_data.c
new file mode 100644
index 000000000000..bdf39481fbd6
--- /dev/null
+++ b/arch/arm/mach-omap2/cclock3xxx_data.c
@@ -0,0 +1,3595 @@
1/*
2 * OMAP3 clock data
3 *
4 * Copyright (C) 2007-2012 Texas Instruments, Inc.
5 * Copyright (C) 2007-2011 Nokia Corporation
6 *
7 * Written by Paul Walmsley
8 * Updated to COMMON clk data format by Rajendra Nayak <rnayak@ti.com>
9 * With many device clock fixes by Kevin Hilman and Jouni Högander
10 * DPLL bypass clock support added by Roman Tereshonkov
11 *
12 */
13
14/*
15 * Virtual clocks are introduced as convenient tools.
16 * They are sources for other clocks and not supposed
17 * to be requested from drivers directly.
18 */
19
20#include <linux/kernel.h>
21#include <linux/clk.h>
22#include <linux/clk-private.h>
23#include <linux/list.h>
24#include <linux/io.h>
25
26#include "soc.h"
27#include "iomap.h"
28#include "clock.h"
29#include "clock3xxx.h"
30#include "clock34xx.h"
31#include "clock36xx.h"
32#include "clock3517.h"
33#include "cm3xxx.h"
34#include "cm-regbits-34xx.h"
35#include "prm3xxx.h"
36#include "prm-regbits-34xx.h"
37#include "control.h"
38
39/*
40 * clocks
41 */
42
43#define OMAP_CM_REGADDR OMAP34XX_CM_REGADDR
44
45/* Maximum DPLL multiplier, divider values for OMAP3 */
46#define OMAP3_MAX_DPLL_MULT 2047
47#define OMAP3630_MAX_JTYPE_DPLL_MULT 4095
48#define OMAP3_MAX_DPLL_DIV 128
49
50DEFINE_CLK_FIXED_RATE(dummy_apb_pclk, CLK_IS_ROOT, 0x0, 0x0);
51
52DEFINE_CLK_FIXED_RATE(mcbsp_clks, CLK_IS_ROOT, 0x0, 0x0);
53
54DEFINE_CLK_FIXED_RATE(omap_32k_fck, CLK_IS_ROOT, 32768, 0x0);
55
56DEFINE_CLK_FIXED_RATE(pclk_ck, CLK_IS_ROOT, 27000000, 0x0);
57
58DEFINE_CLK_FIXED_RATE(rmii_ck, CLK_IS_ROOT, 50000000, 0x0);
59
60DEFINE_CLK_FIXED_RATE(secure_32k_fck, CLK_IS_ROOT, 32768, 0x0);
61
62DEFINE_CLK_FIXED_RATE(sys_altclk, CLK_IS_ROOT, 0x0, 0x0);
63
64DEFINE_CLK_FIXED_RATE(virt_12m_ck, CLK_IS_ROOT, 12000000, 0x0);
65
66DEFINE_CLK_FIXED_RATE(virt_13m_ck, CLK_IS_ROOT, 13000000, 0x0);
67
68DEFINE_CLK_FIXED_RATE(virt_16_8m_ck, CLK_IS_ROOT, 16800000, 0x0);
69
70DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0);
71
72DEFINE_CLK_FIXED_RATE(virt_26000000_ck, CLK_IS_ROOT, 26000000, 0x0);
73
74DEFINE_CLK_FIXED_RATE(virt_38_4m_ck, CLK_IS_ROOT, 38400000, 0x0);
75
76static const char *osc_sys_ck_parent_names[] = {
77 "virt_12m_ck", "virt_13m_ck", "virt_19200000_ck", "virt_26000000_ck",
78 "virt_38_4m_ck", "virt_16_8m_ck",
79};
80
81DEFINE_CLK_MUX(osc_sys_ck, osc_sys_ck_parent_names, NULL, 0x0,
82 OMAP3430_PRM_CLKSEL, OMAP3430_SYS_CLKIN_SEL_SHIFT,
83 OMAP3430_SYS_CLKIN_SEL_WIDTH, 0x0, NULL);
84
85DEFINE_CLK_DIVIDER(sys_ck, "osc_sys_ck", &osc_sys_ck, 0x0,
86 OMAP3430_PRM_CLKSRC_CTRL, OMAP_SYSCLKDIV_SHIFT,
87 OMAP_SYSCLKDIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
88
89static struct dpll_data dpll3_dd = {
90 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
91 .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK,
92 .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK,
93 .clk_bypass = &sys_ck,
94 .clk_ref = &sys_ck,
95 .freqsel_mask = OMAP3430_CORE_DPLL_FREQSEL_MASK,
96 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
97 .enable_mask = OMAP3430_EN_CORE_DPLL_MASK,
98 .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
99 .recal_en_bit = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
100 .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT,
101 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
102 .autoidle_mask = OMAP3430_AUTO_CORE_DPLL_MASK,
103 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
104 .idlest_mask = OMAP3430_ST_CORE_CLK_MASK,
105 .max_multiplier = OMAP3_MAX_DPLL_MULT,
106 .min_divider = 1,
107 .max_divider = OMAP3_MAX_DPLL_DIV,
108};
109
110static struct clk dpll3_ck;
111
112static const char *dpll3_ck_parent_names[] = {
113 "sys_ck",
114};
115
116static const struct clk_ops dpll3_ck_ops = {
117 .init = &omap2_init_clk_clkdm,
118 .get_parent = &omap2_init_dpll_parent,
119 .recalc_rate = &omap3_dpll_recalc,
120 .round_rate = &omap2_dpll_round_rate,
121};
122
123static struct clk_hw_omap dpll3_ck_hw = {
124 .hw = {
125 .clk = &dpll3_ck,
126 },
127 .ops = &clkhwops_omap3_dpll,
128 .dpll_data = &dpll3_dd,
129 .clkdm_name = "dpll3_clkdm",
130};
131
132DEFINE_STRUCT_CLK(dpll3_ck, dpll3_ck_parent_names, dpll3_ck_ops);
133
134DEFINE_CLK_DIVIDER(dpll3_m2_ck, "dpll3_ck", &dpll3_ck, 0x0,
135 OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
136 OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT,
137 OMAP3430_CORE_DPLL_CLKOUT_DIV_WIDTH,
138 CLK_DIVIDER_ONE_BASED, NULL);
139
140static struct clk core_ck;
141
142static const char *core_ck_parent_names[] = {
143 "dpll3_m2_ck",
144};
145
146static const struct clk_ops core_ck_ops = {};
147
148DEFINE_STRUCT_CLK_HW_OMAP(core_ck, NULL);
149DEFINE_STRUCT_CLK(core_ck, core_ck_parent_names, core_ck_ops);
150
151DEFINE_CLK_DIVIDER(l3_ick, "core_ck", &core_ck, 0x0,
152 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
153 OMAP3430_CLKSEL_L3_SHIFT, OMAP3430_CLKSEL_L3_WIDTH,
154 CLK_DIVIDER_ONE_BASED, NULL);
155
156DEFINE_CLK_DIVIDER(l4_ick, "l3_ick", &l3_ick, 0x0,
157 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
158 OMAP3430_CLKSEL_L4_SHIFT, OMAP3430_CLKSEL_L4_WIDTH,
159 CLK_DIVIDER_ONE_BASED, NULL);
160
161static struct clk security_l4_ick2;
162
163static const char *security_l4_ick2_parent_names[] = {
164 "l4_ick",
165};
166
167DEFINE_STRUCT_CLK_HW_OMAP(security_l4_ick2, NULL);
168DEFINE_STRUCT_CLK(security_l4_ick2, security_l4_ick2_parent_names, core_ck_ops);
169
170static struct clk aes1_ick;
171
172static const char *aes1_ick_parent_names[] = {
173 "security_l4_ick2",
174};
175
176static const struct clk_ops aes1_ick_ops = {
177 .enable = &omap2_dflt_clk_enable,
178 .disable = &omap2_dflt_clk_disable,
179 .is_enabled = &omap2_dflt_clk_is_enabled,
180};
181
182static struct clk_hw_omap aes1_ick_hw = {
183 .hw = {
184 .clk = &aes1_ick,
185 },
186 .ops = &clkhwops_iclk_wait,
187 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
188 .enable_bit = OMAP3430_EN_AES1_SHIFT,
189};
190
191DEFINE_STRUCT_CLK(aes1_ick, aes1_ick_parent_names, aes1_ick_ops);
192
193static struct clk core_l4_ick;
194
195static const struct clk_ops core_l4_ick_ops = {
196 .init = &omap2_init_clk_clkdm,
197};
198
199DEFINE_STRUCT_CLK_HW_OMAP(core_l4_ick, "core_l4_clkdm");
200DEFINE_STRUCT_CLK(core_l4_ick, security_l4_ick2_parent_names, core_l4_ick_ops);
201
202static struct clk aes2_ick;
203
204static const char *aes2_ick_parent_names[] = {
205 "core_l4_ick",
206};
207
208static const struct clk_ops aes2_ick_ops = {
209 .init = &omap2_init_clk_clkdm,
210 .enable = &omap2_dflt_clk_enable,
211 .disable = &omap2_dflt_clk_disable,
212 .is_enabled = &omap2_dflt_clk_is_enabled,
213};
214
215static struct clk_hw_omap aes2_ick_hw = {
216 .hw = {
217 .clk = &aes2_ick,
218 },
219 .ops = &clkhwops_iclk_wait,
220 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
221 .enable_bit = OMAP3430_EN_AES2_SHIFT,
222 .clkdm_name = "core_l4_clkdm",
223};
224
225DEFINE_STRUCT_CLK(aes2_ick, aes2_ick_parent_names, aes2_ick_ops);
226
227static struct clk dpll1_fck;
228
229static struct dpll_data dpll1_dd = {
230 .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
231 .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK,
232 .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK,
233 .clk_bypass = &dpll1_fck,
234 .clk_ref = &sys_ck,
235 .freqsel_mask = OMAP3430_MPU_DPLL_FREQSEL_MASK,
236 .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
237 .enable_mask = OMAP3430_EN_MPU_DPLL_MASK,
238 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
239 .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
240 .recal_en_bit = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
241 .recal_st_bit = OMAP3430_MPU_DPLL_ST_SHIFT,
242 .autoidle_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
243 .autoidle_mask = OMAP3430_AUTO_MPU_DPLL_MASK,
244 .idlest_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
245 .idlest_mask = OMAP3430_ST_MPU_CLK_MASK,
246 .max_multiplier = OMAP3_MAX_DPLL_MULT,
247 .min_divider = 1,
248 .max_divider = OMAP3_MAX_DPLL_DIV,
249};
250
251static struct clk dpll1_ck;
252
253static const struct clk_ops dpll1_ck_ops = {
254 .init = &omap2_init_clk_clkdm,
255 .enable = &omap3_noncore_dpll_enable,
256 .disable = &omap3_noncore_dpll_disable,
257 .get_parent = &omap2_init_dpll_parent,
258 .recalc_rate = &omap3_dpll_recalc,
259 .set_rate = &omap3_noncore_dpll_set_rate,
260 .round_rate = &omap2_dpll_round_rate,
261};
262
263static struct clk_hw_omap dpll1_ck_hw = {
264 .hw = {
265 .clk = &dpll1_ck,
266 },
267 .ops = &clkhwops_omap3_dpll,
268 .dpll_data = &dpll1_dd,
269 .clkdm_name = "dpll1_clkdm",
270};
271
272DEFINE_STRUCT_CLK(dpll1_ck, dpll3_ck_parent_names, dpll1_ck_ops);
273
274DEFINE_CLK_FIXED_FACTOR(dpll1_x2_ck, "dpll1_ck", &dpll1_ck, 0x0, 2, 1);
275
276DEFINE_CLK_DIVIDER(dpll1_x2m2_ck, "dpll1_x2_ck", &dpll1_x2_ck, 0x0,
277 OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
278 OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT,
279 OMAP3430_MPU_DPLL_CLKOUT_DIV_WIDTH,
280 CLK_DIVIDER_ONE_BASED, NULL);
281
282static struct clk mpu_ck;
283
284static const char *mpu_ck_parent_names[] = {
285 "dpll1_x2m2_ck",
286};
287
288DEFINE_STRUCT_CLK_HW_OMAP(mpu_ck, "mpu_clkdm");
289DEFINE_STRUCT_CLK(mpu_ck, mpu_ck_parent_names, core_l4_ick_ops);
290
291DEFINE_CLK_DIVIDER(arm_fck, "mpu_ck", &mpu_ck, 0x0,
292 OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
293 OMAP3430_ST_MPU_CLK_SHIFT, OMAP3430_ST_MPU_CLK_WIDTH,
294 0x0, NULL);
295
296static struct clk cam_ick;
297
298static struct clk_hw_omap cam_ick_hw = {
299 .hw = {
300 .clk = &cam_ick,
301 },
302 .ops = &clkhwops_iclk,
303 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
304 .enable_bit = OMAP3430_EN_CAM_SHIFT,
305 .clkdm_name = "cam_clkdm",
306};
307
308DEFINE_STRUCT_CLK(cam_ick, security_l4_ick2_parent_names, aes2_ick_ops);
309
310/* DPLL4 */
311/* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
312/* Type: DPLL */
313static struct dpll_data dpll4_dd;
314
315static struct dpll_data dpll4_dd_34xx __initdata = {
316 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
317 .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK,
318 .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK,
319 .clk_bypass = &sys_ck,
320 .clk_ref = &sys_ck,
321 .freqsel_mask = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
322 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
323 .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK,
324 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
325 .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
326 .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
327 .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT,
328 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
329 .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK,
330 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
331 .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK,
332 .max_multiplier = OMAP3_MAX_DPLL_MULT,
333 .min_divider = 1,
334 .max_divider = OMAP3_MAX_DPLL_DIV,
335};
336
337static struct dpll_data dpll4_dd_3630 __initdata = {
338 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
339 .mult_mask = OMAP3630_PERIPH_DPLL_MULT_MASK,
340 .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK,
341 .clk_bypass = &sys_ck,
342 .clk_ref = &sys_ck,
343 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
344 .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK,
345 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
346 .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
347 .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
348 .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT,
349 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
350 .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK,
351 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
352 .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK,
353 .dco_mask = OMAP3630_PERIPH_DPLL_DCO_SEL_MASK,
354 .sddiv_mask = OMAP3630_PERIPH_DPLL_SD_DIV_MASK,
355 .max_multiplier = OMAP3630_MAX_JTYPE_DPLL_MULT,
356 .min_divider = 1,
357 .max_divider = OMAP3_MAX_DPLL_DIV,
358 .flags = DPLL_J_TYPE
359};
360
361static struct clk dpll4_ck;
362
363static const struct clk_ops dpll4_ck_ops = {
364 .init = &omap2_init_clk_clkdm,
365 .enable = &omap3_noncore_dpll_enable,
366 .disable = &omap3_noncore_dpll_disable,
367 .get_parent = &omap2_init_dpll_parent,
368 .recalc_rate = &omap3_dpll_recalc,
369 .set_rate = &omap3_dpll4_set_rate,
370 .round_rate = &omap2_dpll_round_rate,
371};
372
373static struct clk_hw_omap dpll4_ck_hw = {
374 .hw = {
375 .clk = &dpll4_ck,
376 },
377 .dpll_data = &dpll4_dd,
378 .ops = &clkhwops_omap3_dpll,
379 .clkdm_name = "dpll4_clkdm",
380};
381
382DEFINE_STRUCT_CLK(dpll4_ck, dpll3_ck_parent_names, dpll4_ck_ops);
383
384DEFINE_CLK_DIVIDER(dpll4_m5_ck, "dpll4_ck", &dpll4_ck, 0x0,
385 OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
386 OMAP3430_CLKSEL_CAM_SHIFT, OMAP3630_CLKSEL_CAM_WIDTH,
387 CLK_DIVIDER_ONE_BASED, NULL);
388
389static struct clk dpll4_m5x2_ck;
390
391static const char *dpll4_m5x2_ck_parent_names[] = {
392 "dpll4_m5_ck",
393};
394
395static const struct clk_ops dpll4_m5x2_ck_ops = {
396 .init = &omap2_init_clk_clkdm,
397 .enable = &omap2_dflt_clk_enable,
398 .disable = &omap2_dflt_clk_disable,
399 .is_enabled = &omap2_dflt_clk_is_enabled,
400 .recalc_rate = &omap3_clkoutx2_recalc,
401};
402
403static const struct clk_ops dpll4_m5x2_ck_3630_ops = {
404 .init = &omap2_init_clk_clkdm,
405 .enable = &omap36xx_pwrdn_clk_enable_with_hsdiv_restore,
406 .disable = &omap2_dflt_clk_disable,
407 .recalc_rate = &omap3_clkoutx2_recalc,
408};
409
410static struct clk_hw_omap dpll4_m5x2_ck_hw = {
411 .hw = {
412 .clk = &dpll4_m5x2_ck,
413 },
414 .ops = &clkhwops_wait,
415 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
416 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
417 .flags = INVERT_ENABLE,
418 .clkdm_name = "dpll4_clkdm",
419};
420
421DEFINE_STRUCT_CLK(dpll4_m5x2_ck, dpll4_m5x2_ck_parent_names, dpll4_m5x2_ck_ops);
422
423static struct clk dpll4_m5x2_ck_3630 = {
424 .name = "dpll4_m5x2_ck",
425 .hw = &dpll4_m5x2_ck_hw.hw,
426 .parent_names = dpll4_m5x2_ck_parent_names,
427 .num_parents = ARRAY_SIZE(dpll4_m5x2_ck_parent_names),
428 .ops = &dpll4_m5x2_ck_3630_ops,
429};
430
431static struct clk cam_mclk;
432
433static const char *cam_mclk_parent_names[] = {
434 "dpll4_m5x2_ck",
435};
436
437static struct clk_hw_omap cam_mclk_hw = {
438 .hw = {
439 .clk = &cam_mclk,
440 },
441 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
442 .enable_bit = OMAP3430_EN_CAM_SHIFT,
443 .clkdm_name = "cam_clkdm",
444};
445
446DEFINE_STRUCT_CLK(cam_mclk, cam_mclk_parent_names, aes2_ick_ops);
447
448static const struct clksel_rate clkout2_src_core_rates[] = {
449 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
450 { .div = 0 }
451};
452
453static const struct clksel_rate clkout2_src_sys_rates[] = {
454 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
455 { .div = 0 }
456};
457
458static const struct clksel_rate clkout2_src_96m_rates[] = {
459 { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
460 { .div = 0 }
461};
462
463DEFINE_CLK_DIVIDER(dpll4_m2_ck, "dpll4_ck", &dpll4_ck, 0x0,
464 OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
465 OMAP3430_DIV_96M_SHIFT, OMAP3630_DIV_96M_WIDTH,
466 CLK_DIVIDER_ONE_BASED, NULL);
467
468static struct clk dpll4_m2x2_ck;
469
470static const char *dpll4_m2x2_ck_parent_names[] = {
471 "dpll4_m2_ck",
472};
473
474static struct clk_hw_omap dpll4_m2x2_ck_hw = {
475 .hw = {
476 .clk = &dpll4_m2x2_ck,
477 },
478 .ops = &clkhwops_wait,
479 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
480 .enable_bit = OMAP3430_PWRDN_96M_SHIFT,
481 .flags = INVERT_ENABLE,
482 .clkdm_name = "dpll4_clkdm",
483};
484
485DEFINE_STRUCT_CLK(dpll4_m2x2_ck, dpll4_m2x2_ck_parent_names, dpll4_m5x2_ck_ops);
486
487static struct clk dpll4_m2x2_ck_3630 = {
488 .name = "dpll4_m2x2_ck",
489 .hw = &dpll4_m2x2_ck_hw.hw,
490 .parent_names = dpll4_m2x2_ck_parent_names,
491 .num_parents = ARRAY_SIZE(dpll4_m2x2_ck_parent_names),
492 .ops = &dpll4_m5x2_ck_3630_ops,
493};
494
495static struct clk omap_96m_alwon_fck;
496
497static const char *omap_96m_alwon_fck_parent_names[] = {
498 "dpll4_m2x2_ck",
499};
500
501DEFINE_STRUCT_CLK_HW_OMAP(omap_96m_alwon_fck, NULL);
502DEFINE_STRUCT_CLK(omap_96m_alwon_fck, omap_96m_alwon_fck_parent_names,
503 core_ck_ops);
504
505static struct clk cm_96m_fck;
506
507static const char *cm_96m_fck_parent_names[] = {
508 "omap_96m_alwon_fck",
509};
510
511DEFINE_STRUCT_CLK_HW_OMAP(cm_96m_fck, NULL);
512DEFINE_STRUCT_CLK(cm_96m_fck, cm_96m_fck_parent_names, core_ck_ops);
513
514static const struct clksel_rate clkout2_src_54m_rates[] = {
515 { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
516 { .div = 0 }
517};
518
519DEFINE_CLK_DIVIDER(dpll4_m3_ck, "dpll4_ck", &dpll4_ck, 0x0,
520 OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
521 OMAP3430_CLKSEL_TV_SHIFT, OMAP3630_CLKSEL_TV_WIDTH,
522 CLK_DIVIDER_ONE_BASED, NULL);
523
524static struct clk dpll4_m3x2_ck;
525
526static const char *dpll4_m3x2_ck_parent_names[] = {
527 "dpll4_m3_ck",
528};
529
530static struct clk_hw_omap dpll4_m3x2_ck_hw = {
531 .hw = {
532 .clk = &dpll4_m3x2_ck,
533 },
534 .ops = &clkhwops_wait,
535 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
536 .enable_bit = OMAP3430_PWRDN_TV_SHIFT,
537 .flags = INVERT_ENABLE,
538 .clkdm_name = "dpll4_clkdm",
539};
540
541DEFINE_STRUCT_CLK(dpll4_m3x2_ck, dpll4_m3x2_ck_parent_names, dpll4_m5x2_ck_ops);
542
543static struct clk dpll4_m3x2_ck_3630 = {
544 .name = "dpll4_m3x2_ck",
545 .hw = &dpll4_m3x2_ck_hw.hw,
546 .parent_names = dpll4_m3x2_ck_parent_names,
547 .num_parents = ARRAY_SIZE(dpll4_m3x2_ck_parent_names),
548 .ops = &dpll4_m5x2_ck_3630_ops,
549};
550
551static const char *omap_54m_fck_parent_names[] = {
552 "dpll4_m3x2_ck", "sys_altclk",
553};
554
555DEFINE_CLK_MUX(omap_54m_fck, omap_54m_fck_parent_names, NULL, 0x0,
556 OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), OMAP3430_SOURCE_54M_SHIFT,
557 OMAP3430_SOURCE_54M_WIDTH, 0x0, NULL);
558
559static const struct clksel clkout2_src_clksel[] = {
560 { .parent = &core_ck, .rates = clkout2_src_core_rates },
561 { .parent = &sys_ck, .rates = clkout2_src_sys_rates },
562 { .parent = &cm_96m_fck, .rates = clkout2_src_96m_rates },
563 { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates },
564 { .parent = NULL },
565};
566
567static const char *clkout2_src_ck_parent_names[] = {
568 "core_ck", "sys_ck", "cm_96m_fck", "omap_54m_fck",
569};
570
571static const struct clk_ops clkout2_src_ck_ops = {
572 .init = &omap2_init_clk_clkdm,
573 .enable = &omap2_dflt_clk_enable,
574 .disable = &omap2_dflt_clk_disable,
575 .is_enabled = &omap2_dflt_clk_is_enabled,
576 .recalc_rate = &omap2_clksel_recalc,
577 .get_parent = &omap2_clksel_find_parent_index,
578 .set_parent = &omap2_clksel_set_parent,
579};
580
581DEFINE_CLK_OMAP_MUX_GATE(clkout2_src_ck, "core_clkdm",
582 clkout2_src_clksel, OMAP3430_CM_CLKOUT_CTRL,
583 OMAP3430_CLKOUT2SOURCE_MASK,
584 OMAP3430_CM_CLKOUT_CTRL, OMAP3430_CLKOUT2_EN_SHIFT,
585 NULL, clkout2_src_ck_parent_names, clkout2_src_ck_ops);
586
587static const struct clksel_rate omap_48m_cm96m_rates[] = {
588 { .div = 2, .val = 0, .flags = RATE_IN_3XXX },
589 { .div = 0 }
590};
591
592static const struct clksel_rate omap_48m_alt_rates[] = {
593 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
594 { .div = 0 }
595};
596
597static const struct clksel omap_48m_clksel[] = {
598 { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
599 { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
600 { .parent = NULL },
601};
602
603static const char *omap_48m_fck_parent_names[] = {
604 "cm_96m_fck", "sys_altclk",
605};
606
607static struct clk omap_48m_fck;
608
609static const struct clk_ops omap_48m_fck_ops = {
610 .recalc_rate = &omap2_clksel_recalc,
611 .get_parent = &omap2_clksel_find_parent_index,
612 .set_parent = &omap2_clksel_set_parent,
613};
614
615static struct clk_hw_omap omap_48m_fck_hw = {
616 .hw = {
617 .clk = &omap_48m_fck,
618 },
619 .clksel = omap_48m_clksel,
620 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
621 .clksel_mask = OMAP3430_SOURCE_48M_MASK,
622};
623
624DEFINE_STRUCT_CLK(omap_48m_fck, omap_48m_fck_parent_names, omap_48m_fck_ops);
625
626DEFINE_CLK_FIXED_FACTOR(omap_12m_fck, "omap_48m_fck", &omap_48m_fck, 0x0, 1, 4);
627
628static struct clk core_12m_fck;
629
630static const char *core_12m_fck_parent_names[] = {
631 "omap_12m_fck",
632};
633
634DEFINE_STRUCT_CLK_HW_OMAP(core_12m_fck, "core_l4_clkdm");
635DEFINE_STRUCT_CLK(core_12m_fck, core_12m_fck_parent_names, core_l4_ick_ops);
636
637static struct clk core_48m_fck;
638
639static const char *core_48m_fck_parent_names[] = {
640 "omap_48m_fck",
641};
642
643DEFINE_STRUCT_CLK_HW_OMAP(core_48m_fck, "core_l4_clkdm");
644DEFINE_STRUCT_CLK(core_48m_fck, core_48m_fck_parent_names, core_l4_ick_ops);
645
646static const char *omap_96m_fck_parent_names[] = {
647 "cm_96m_fck", "sys_ck",
648};
649
650DEFINE_CLK_MUX(omap_96m_fck, omap_96m_fck_parent_names, NULL, 0x0,
651 OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
652 OMAP3430_SOURCE_96M_SHIFT, OMAP3430_SOURCE_96M_WIDTH, 0x0, NULL);
653
654static struct clk core_96m_fck;
655
656static const char *core_96m_fck_parent_names[] = {
657 "omap_96m_fck",
658};
659
660DEFINE_STRUCT_CLK_HW_OMAP(core_96m_fck, "core_l4_clkdm");
661DEFINE_STRUCT_CLK(core_96m_fck, core_96m_fck_parent_names, core_l4_ick_ops);
662
663static struct clk core_l3_ick;
664
665static const char *core_l3_ick_parent_names[] = {
666 "l3_ick",
667};
668
669DEFINE_STRUCT_CLK_HW_OMAP(core_l3_ick, "core_l3_clkdm");
670DEFINE_STRUCT_CLK(core_l3_ick, core_l3_ick_parent_names, core_l4_ick_ops);
671
672DEFINE_CLK_FIXED_FACTOR(dpll3_m2x2_ck, "dpll3_m2_ck", &dpll3_m2_ck, 0x0, 2, 1);
673
674static struct clk corex2_fck;
675
676static const char *corex2_fck_parent_names[] = {
677 "dpll3_m2x2_ck",
678};
679
680DEFINE_STRUCT_CLK_HW_OMAP(corex2_fck, NULL);
681DEFINE_STRUCT_CLK(corex2_fck, corex2_fck_parent_names, core_ck_ops);
682
683static struct clk cpefuse_fck;
684
685static struct clk_hw_omap cpefuse_fck_hw = {
686 .hw = {
687 .clk = &cpefuse_fck,
688 },
689 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
690 .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT,
691 .clkdm_name = "core_l4_clkdm",
692};
693
694DEFINE_STRUCT_CLK(cpefuse_fck, dpll3_ck_parent_names, aes2_ick_ops);
695
696static struct clk csi2_96m_fck;
697
698static const char *csi2_96m_fck_parent_names[] = {
699 "core_96m_fck",
700};
701
702static struct clk_hw_omap csi2_96m_fck_hw = {
703 .hw = {
704 .clk = &csi2_96m_fck,
705 },
706 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
707 .enable_bit = OMAP3430_EN_CSI2_SHIFT,
708 .clkdm_name = "cam_clkdm",
709};
710
711DEFINE_STRUCT_CLK(csi2_96m_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
712
713static struct clk d2d_26m_fck;
714
715static struct clk_hw_omap d2d_26m_fck_hw = {
716 .hw = {
717 .clk = &d2d_26m_fck,
718 },
719 .ops = &clkhwops_wait,
720 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
721 .enable_bit = OMAP3430ES1_EN_D2D_SHIFT,
722 .clkdm_name = "d2d_clkdm",
723};
724
725DEFINE_STRUCT_CLK(d2d_26m_fck, dpll3_ck_parent_names, aes2_ick_ops);
726
727static struct clk des1_ick;
728
729static struct clk_hw_omap des1_ick_hw = {
730 .hw = {
731 .clk = &des1_ick,
732 },
733 .ops = &clkhwops_iclk_wait,
734 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
735 .enable_bit = OMAP3430_EN_DES1_SHIFT,
736};
737
738DEFINE_STRUCT_CLK(des1_ick, aes1_ick_parent_names, aes1_ick_ops);
739
740static struct clk des2_ick;
741
742static struct clk_hw_omap des2_ick_hw = {
743 .hw = {
744 .clk = &des2_ick,
745 },
746 .ops = &clkhwops_iclk_wait,
747 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
748 .enable_bit = OMAP3430_EN_DES2_SHIFT,
749 .clkdm_name = "core_l4_clkdm",
750};
751
752DEFINE_STRUCT_CLK(des2_ick, aes2_ick_parent_names, aes2_ick_ops);
753
754DEFINE_CLK_DIVIDER(dpll1_fck, "core_ck", &core_ck, 0x0,
755 OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
756 OMAP3430_MPU_CLK_SRC_SHIFT, OMAP3430_MPU_CLK_SRC_WIDTH,
757 CLK_DIVIDER_ONE_BASED, NULL);
758
759static struct clk dpll2_fck;
760
761static struct dpll_data dpll2_dd = {
762 .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
763 .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK,
764 .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK,
765 .clk_bypass = &dpll2_fck,
766 .clk_ref = &sys_ck,
767 .freqsel_mask = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
768 .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
769 .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK,
770 .modes = ((1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
771 (1 << DPLL_LOW_POWER_BYPASS)),
772 .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
773 .recal_en_bit = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
774 .recal_st_bit = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
775 .autoidle_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
776 .autoidle_mask = OMAP3430_AUTO_IVA2_DPLL_MASK,
777 .idlest_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
778 .idlest_mask = OMAP3430_ST_IVA2_CLK_MASK,
779 .max_multiplier = OMAP3_MAX_DPLL_MULT,
780 .min_divider = 1,
781 .max_divider = OMAP3_MAX_DPLL_DIV,
782};
783
784static struct clk dpll2_ck;
785
786static struct clk_hw_omap dpll2_ck_hw = {
787 .hw = {
788 .clk = &dpll2_ck,
789 },
790 .ops = &clkhwops_omap3_dpll,
791 .dpll_data = &dpll2_dd,
792 .clkdm_name = "dpll2_clkdm",
793};
794
795DEFINE_STRUCT_CLK(dpll2_ck, dpll3_ck_parent_names, dpll1_ck_ops);
796
797DEFINE_CLK_DIVIDER(dpll2_fck, "core_ck", &core_ck, 0x0,
798 OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
799 OMAP3430_IVA2_CLK_SRC_SHIFT, OMAP3430_IVA2_CLK_SRC_WIDTH,
800 CLK_DIVIDER_ONE_BASED, NULL);
801
802DEFINE_CLK_DIVIDER(dpll2_m2_ck, "dpll2_ck", &dpll2_ck, 0x0,
803 OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL2_PLL),
804 OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT,
805 OMAP3430_IVA2_DPLL_CLKOUT_DIV_WIDTH,
806 CLK_DIVIDER_ONE_BASED, NULL);
807
808DEFINE_CLK_DIVIDER(dpll3_m3_ck, "dpll3_ck", &dpll3_ck, 0x0,
809 OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
810 OMAP3430_DIV_DPLL3_SHIFT, OMAP3430_DIV_DPLL3_WIDTH,
811 CLK_DIVIDER_ONE_BASED, NULL);
812
813static struct clk dpll3_m3x2_ck;
814
815static const char *dpll3_m3x2_ck_parent_names[] = {
816 "dpll3_m3_ck",
817};
818
819static struct clk_hw_omap dpll3_m3x2_ck_hw = {
820 .hw = {
821 .clk = &dpll3_m3x2_ck,
822 },
823 .ops = &clkhwops_wait,
824 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
825 .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT,
826 .flags = INVERT_ENABLE,
827 .clkdm_name = "dpll3_clkdm",
828};
829
830DEFINE_STRUCT_CLK(dpll3_m3x2_ck, dpll3_m3x2_ck_parent_names, dpll4_m5x2_ck_ops);
831
832static struct clk dpll3_m3x2_ck_3630 = {
833 .name = "dpll3_m3x2_ck",
834 .hw = &dpll3_m3x2_ck_hw.hw,
835 .parent_names = dpll3_m3x2_ck_parent_names,
836 .num_parents = ARRAY_SIZE(dpll3_m3x2_ck_parent_names),
837 .ops = &dpll4_m5x2_ck_3630_ops,
838};
839
840DEFINE_CLK_FIXED_FACTOR(dpll3_x2_ck, "dpll3_ck", &dpll3_ck, 0x0, 2, 1);
841
842DEFINE_CLK_DIVIDER(dpll4_m4_ck, "dpll4_ck", &dpll4_ck, 0x0,
843 OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
844 OMAP3430_CLKSEL_DSS1_SHIFT, OMAP3630_CLKSEL_DSS1_WIDTH,
845 CLK_DIVIDER_ONE_BASED, NULL);
846
847static struct clk dpll4_m4x2_ck;
848
849static const char *dpll4_m4x2_ck_parent_names[] = {
850 "dpll4_m4_ck",
851};
852
853static struct clk_hw_omap dpll4_m4x2_ck_hw = {
854 .hw = {
855 .clk = &dpll4_m4x2_ck,
856 },
857 .ops = &clkhwops_wait,
858 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
859 .enable_bit = OMAP3430_PWRDN_DSS1_SHIFT,
860 .flags = INVERT_ENABLE,
861 .clkdm_name = "dpll4_clkdm",
862};
863
864DEFINE_STRUCT_CLK(dpll4_m4x2_ck, dpll4_m4x2_ck_parent_names, dpll4_m5x2_ck_ops);
865
866static struct clk dpll4_m4x2_ck_3630 = {
867 .name = "dpll4_m4x2_ck",
868 .hw = &dpll4_m4x2_ck_hw.hw,
869 .parent_names = dpll4_m4x2_ck_parent_names,
870 .num_parents = ARRAY_SIZE(dpll4_m4x2_ck_parent_names),
871 .ops = &dpll4_m5x2_ck_3630_ops,
872};
873
874DEFINE_CLK_DIVIDER(dpll4_m6_ck, "dpll4_ck", &dpll4_ck, 0x0,
875 OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
876 OMAP3430_DIV_DPLL4_SHIFT, OMAP3630_DIV_DPLL4_WIDTH,
877 CLK_DIVIDER_ONE_BASED, NULL);
878
879static struct clk dpll4_m6x2_ck;
880
881static const char *dpll4_m6x2_ck_parent_names[] = {
882 "dpll4_m6_ck",
883};
884
885static struct clk_hw_omap dpll4_m6x2_ck_hw = {
886 .hw = {
887 .clk = &dpll4_m6x2_ck,
888 },
889 .ops = &clkhwops_wait,
890 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
891 .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
892 .flags = INVERT_ENABLE,
893 .clkdm_name = "dpll4_clkdm",
894};
895
896DEFINE_STRUCT_CLK(dpll4_m6x2_ck, dpll4_m6x2_ck_parent_names, dpll4_m5x2_ck_ops);
897
898static struct clk dpll4_m6x2_ck_3630 = {
899 .name = "dpll4_m6x2_ck",
900 .hw = &dpll4_m6x2_ck_hw.hw,
901 .parent_names = dpll4_m6x2_ck_parent_names,
902 .num_parents = ARRAY_SIZE(dpll4_m6x2_ck_parent_names),
903 .ops = &dpll4_m5x2_ck_3630_ops,
904};
905
906DEFINE_CLK_FIXED_FACTOR(dpll4_x2_ck, "dpll4_ck", &dpll4_ck, 0x0, 2, 1);
907
908static struct dpll_data dpll5_dd = {
909 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
910 .mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
911 .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
912 .clk_bypass = &sys_ck,
913 .clk_ref = &sys_ck,
914 .freqsel_mask = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
915 .control_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
916 .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
917 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
918 .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
919 .recal_en_bit = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
920 .recal_st_bit = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
921 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
922 .autoidle_mask = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
923 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
924 .idlest_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
925 .max_multiplier = OMAP3_MAX_DPLL_MULT,
926 .min_divider = 1,
927 .max_divider = OMAP3_MAX_DPLL_DIV,
928};
929
930static struct clk dpll5_ck;
931
932static struct clk_hw_omap dpll5_ck_hw = {
933 .hw = {
934 .clk = &dpll5_ck,
935 },
936 .ops = &clkhwops_omap3_dpll,
937 .dpll_data = &dpll5_dd,
938 .clkdm_name = "dpll5_clkdm",
939};
940
941DEFINE_STRUCT_CLK(dpll5_ck, dpll3_ck_parent_names, dpll1_ck_ops);
942
943DEFINE_CLK_DIVIDER(dpll5_m2_ck, "dpll5_ck", &dpll5_ck, 0x0,
944 OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
945 OMAP3430ES2_DIV_120M_SHIFT, OMAP3430ES2_DIV_120M_WIDTH,
946 CLK_DIVIDER_ONE_BASED, NULL);
947
948static struct clk dss1_alwon_fck_3430es1;
949
950static const char *dss1_alwon_fck_3430es1_parent_names[] = {
951 "dpll4_m4x2_ck",
952};
953
954static struct clk_hw_omap dss1_alwon_fck_3430es1_hw = {
955 .hw = {
956 .clk = &dss1_alwon_fck_3430es1,
957 },
958 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
959 .enable_bit = OMAP3430_EN_DSS1_SHIFT,
960 .clkdm_name = "dss_clkdm",
961};
962
963DEFINE_STRUCT_CLK(dss1_alwon_fck_3430es1, dss1_alwon_fck_3430es1_parent_names,
964 aes2_ick_ops);
965
966static struct clk dss1_alwon_fck_3430es2;
967
968static struct clk_hw_omap dss1_alwon_fck_3430es2_hw = {
969 .hw = {
970 .clk = &dss1_alwon_fck_3430es2,
971 },
972 .ops = &clkhwops_omap3430es2_dss_usbhost_wait,
973 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
974 .enable_bit = OMAP3430_EN_DSS1_SHIFT,
975 .clkdm_name = "dss_clkdm",
976};
977
978DEFINE_STRUCT_CLK(dss1_alwon_fck_3430es2, dss1_alwon_fck_3430es1_parent_names,
979 aes2_ick_ops);
980
981static struct clk dss2_alwon_fck;
982
983static struct clk_hw_omap dss2_alwon_fck_hw = {
984 .hw = {
985 .clk = &dss2_alwon_fck,
986 },
987 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
988 .enable_bit = OMAP3430_EN_DSS2_SHIFT,
989 .clkdm_name = "dss_clkdm",
990};
991
992DEFINE_STRUCT_CLK(dss2_alwon_fck, dpll3_ck_parent_names, aes2_ick_ops);
993
994static struct clk dss_96m_fck;
995
996static struct clk_hw_omap dss_96m_fck_hw = {
997 .hw = {
998 .clk = &dss_96m_fck,
999 },
1000 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1001 .enable_bit = OMAP3430_EN_TV_SHIFT,
1002 .clkdm_name = "dss_clkdm",
1003};
1004
1005DEFINE_STRUCT_CLK(dss_96m_fck, core_96m_fck_parent_names, aes2_ick_ops);
1006
1007static struct clk dss_ick_3430es1;
1008
1009static struct clk_hw_omap dss_ick_3430es1_hw = {
1010 .hw = {
1011 .clk = &dss_ick_3430es1,
1012 },
1013 .ops = &clkhwops_iclk,
1014 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
1015 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
1016 .clkdm_name = "dss_clkdm",
1017};
1018
1019DEFINE_STRUCT_CLK(dss_ick_3430es1, security_l4_ick2_parent_names, aes2_ick_ops);
1020
1021static struct clk dss_ick_3430es2;
1022
1023static struct clk_hw_omap dss_ick_3430es2_hw = {
1024 .hw = {
1025 .clk = &dss_ick_3430es2,
1026 },
1027 .ops = &clkhwops_omap3430es2_iclk_dss_usbhost_wait,
1028 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
1029 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
1030 .clkdm_name = "dss_clkdm",
1031};
1032
1033DEFINE_STRUCT_CLK(dss_ick_3430es2, security_l4_ick2_parent_names, aes2_ick_ops);
1034
1035static struct clk dss_tv_fck;
1036
1037static const char *dss_tv_fck_parent_names[] = {
1038 "omap_54m_fck",
1039};
1040
1041static struct clk_hw_omap dss_tv_fck_hw = {
1042 .hw = {
1043 .clk = &dss_tv_fck,
1044 },
1045 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1046 .enable_bit = OMAP3430_EN_TV_SHIFT,
1047 .clkdm_name = "dss_clkdm",
1048};
1049
1050DEFINE_STRUCT_CLK(dss_tv_fck, dss_tv_fck_parent_names, aes2_ick_ops);
1051
1052static struct clk emac_fck;
1053
1054static const char *emac_fck_parent_names[] = {
1055 "rmii_ck",
1056};
1057
1058static struct clk_hw_omap emac_fck_hw = {
1059 .hw = {
1060 .clk = &emac_fck,
1061 },
1062 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
1063 .enable_bit = AM35XX_CPGMAC_FCLK_SHIFT,
1064};
1065
1066DEFINE_STRUCT_CLK(emac_fck, emac_fck_parent_names, aes1_ick_ops);
1067
1068static struct clk ipss_ick;
1069
1070static const char *ipss_ick_parent_names[] = {
1071 "core_l3_ick",
1072};
1073
1074static struct clk_hw_omap ipss_ick_hw = {
1075 .hw = {
1076 .clk = &ipss_ick,
1077 },
1078 .ops = &clkhwops_am35xx_ipss_wait,
1079 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1080 .enable_bit = AM35XX_EN_IPSS_SHIFT,
1081 .clkdm_name = "core_l3_clkdm",
1082};
1083
1084DEFINE_STRUCT_CLK(ipss_ick, ipss_ick_parent_names, aes2_ick_ops);
1085
1086static struct clk emac_ick;
1087
1088static const char *emac_ick_parent_names[] = {
1089 "ipss_ick",
1090};
1091
1092static struct clk_hw_omap emac_ick_hw = {
1093 .hw = {
1094 .clk = &emac_ick,
1095 },
1096 .ops = &clkhwops_am35xx_ipss_module_wait,
1097 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
1098 .enable_bit = AM35XX_CPGMAC_VBUSP_CLK_SHIFT,
1099 .clkdm_name = "core_l3_clkdm",
1100};
1101
1102DEFINE_STRUCT_CLK(emac_ick, emac_ick_parent_names, aes2_ick_ops);
1103
1104static struct clk emu_core_alwon_ck;
1105
1106static const char *emu_core_alwon_ck_parent_names[] = {
1107 "dpll3_m3x2_ck",
1108};
1109
1110DEFINE_STRUCT_CLK_HW_OMAP(emu_core_alwon_ck, "dpll3_clkdm");
1111DEFINE_STRUCT_CLK(emu_core_alwon_ck, emu_core_alwon_ck_parent_names,
1112 core_l4_ick_ops);
1113
1114static struct clk emu_mpu_alwon_ck;
1115
1116static const char *emu_mpu_alwon_ck_parent_names[] = {
1117 "mpu_ck",
1118};
1119
1120DEFINE_STRUCT_CLK_HW_OMAP(emu_mpu_alwon_ck, NULL);
1121DEFINE_STRUCT_CLK(emu_mpu_alwon_ck, emu_mpu_alwon_ck_parent_names, core_ck_ops);
1122
1123static struct clk emu_per_alwon_ck;
1124
1125static const char *emu_per_alwon_ck_parent_names[] = {
1126 "dpll4_m6x2_ck",
1127};
1128
1129DEFINE_STRUCT_CLK_HW_OMAP(emu_per_alwon_ck, "dpll4_clkdm");
1130DEFINE_STRUCT_CLK(emu_per_alwon_ck, emu_per_alwon_ck_parent_names,
1131 core_l4_ick_ops);
1132
1133static const char *emu_src_ck_parent_names[] = {
1134 "sys_ck", "emu_core_alwon_ck", "emu_per_alwon_ck", "emu_mpu_alwon_ck",
1135};
1136
1137static const struct clksel_rate emu_src_sys_rates[] = {
1138 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
1139 { .div = 0 },
1140};
1141
1142static const struct clksel_rate emu_src_core_rates[] = {
1143 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
1144 { .div = 0 },
1145};
1146
1147static const struct clksel_rate emu_src_per_rates[] = {
1148 { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
1149 { .div = 0 },
1150};
1151
1152static const struct clksel_rate emu_src_mpu_rates[] = {
1153 { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
1154 { .div = 0 },
1155};
1156
1157static const struct clksel emu_src_clksel[] = {
1158 { .parent = &sys_ck, .rates = emu_src_sys_rates },
1159 { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
1160 { .parent = &emu_per_alwon_ck, .rates = emu_src_per_rates },
1161 { .parent = &emu_mpu_alwon_ck, .rates = emu_src_mpu_rates },
1162 { .parent = NULL },
1163};
1164
1165static const struct clk_ops emu_src_ck_ops = {
1166 .init = &omap2_init_clk_clkdm,
1167 .recalc_rate = &omap2_clksel_recalc,
1168 .get_parent = &omap2_clksel_find_parent_index,
1169 .set_parent = &omap2_clksel_set_parent,
1170};
1171
1172static struct clk emu_src_ck;
1173
1174static struct clk_hw_omap emu_src_ck_hw = {
1175 .hw = {
1176 .clk = &emu_src_ck,
1177 },
1178 .clksel = emu_src_clksel,
1179 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
1180 .clksel_mask = OMAP3430_MUX_CTRL_MASK,
1181 .clkdm_name = "emu_clkdm",
1182};
1183
1184DEFINE_STRUCT_CLK(emu_src_ck, emu_src_ck_parent_names, emu_src_ck_ops);
1185
1186DEFINE_CLK_DIVIDER(atclk_fck, "emu_src_ck", &emu_src_ck, 0x0,
1187 OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
1188 OMAP3430_CLKSEL_ATCLK_SHIFT, OMAP3430_CLKSEL_ATCLK_WIDTH,
1189 CLK_DIVIDER_ONE_BASED, NULL);
1190
1191static struct clk fac_ick;
1192
1193static struct clk_hw_omap fac_ick_hw = {
1194 .hw = {
1195 .clk = &fac_ick,
1196 },
1197 .ops = &clkhwops_iclk_wait,
1198 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1199 .enable_bit = OMAP3430ES1_EN_FAC_SHIFT,
1200 .clkdm_name = "core_l4_clkdm",
1201};
1202
1203DEFINE_STRUCT_CLK(fac_ick, aes2_ick_parent_names, aes2_ick_ops);
1204
1205static struct clk fshostusb_fck;
1206
1207static const char *fshostusb_fck_parent_names[] = {
1208 "core_48m_fck",
1209};
1210
1211static struct clk_hw_omap fshostusb_fck_hw = {
1212 .hw = {
1213 .clk = &fshostusb_fck,
1214 },
1215 .ops = &clkhwops_wait,
1216 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1217 .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1218 .clkdm_name = "core_l4_clkdm",
1219};
1220
1221DEFINE_STRUCT_CLK(fshostusb_fck, fshostusb_fck_parent_names, aes2_ick_ops);
1222
1223static struct clk gfx_l3_ck;
1224
1225static struct clk_hw_omap gfx_l3_ck_hw = {
1226 .hw = {
1227 .clk = &gfx_l3_ck,
1228 },
1229 .ops = &clkhwops_wait,
1230 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1231 .enable_bit = OMAP_EN_GFX_SHIFT,
1232 .clkdm_name = "gfx_3430es1_clkdm",
1233};
1234
1235DEFINE_STRUCT_CLK(gfx_l3_ck, core_l3_ick_parent_names, aes1_ick_ops);
1236
1237DEFINE_CLK_DIVIDER(gfx_l3_fck, "l3_ick", &l3_ick, 0x0,
1238 OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1239 OMAP_CLKSEL_GFX_SHIFT, OMAP_CLKSEL_GFX_WIDTH,
1240 CLK_DIVIDER_ONE_BASED, NULL);
1241
1242static struct clk gfx_cg1_ck;
1243
1244static const char *gfx_cg1_ck_parent_names[] = {
1245 "gfx_l3_fck",
1246};
1247
1248static struct clk_hw_omap gfx_cg1_ck_hw = {
1249 .hw = {
1250 .clk = &gfx_cg1_ck,
1251 },
1252 .ops = &clkhwops_wait,
1253 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1254 .enable_bit = OMAP3430ES1_EN_2D_SHIFT,
1255 .clkdm_name = "gfx_3430es1_clkdm",
1256};
1257
1258DEFINE_STRUCT_CLK(gfx_cg1_ck, gfx_cg1_ck_parent_names, aes2_ick_ops);
1259
1260static struct clk gfx_cg2_ck;
1261
1262static struct clk_hw_omap gfx_cg2_ck_hw = {
1263 .hw = {
1264 .clk = &gfx_cg2_ck,
1265 },
1266 .ops = &clkhwops_wait,
1267 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1268 .enable_bit = OMAP3430ES1_EN_3D_SHIFT,
1269 .clkdm_name = "gfx_3430es1_clkdm",
1270};
1271
1272DEFINE_STRUCT_CLK(gfx_cg2_ck, gfx_cg1_ck_parent_names, aes2_ick_ops);
1273
1274static struct clk gfx_l3_ick;
1275
1276static const char *gfx_l3_ick_parent_names[] = {
1277 "gfx_l3_ck",
1278};
1279
1280DEFINE_STRUCT_CLK_HW_OMAP(gfx_l3_ick, "gfx_3430es1_clkdm");
1281DEFINE_STRUCT_CLK(gfx_l3_ick, gfx_l3_ick_parent_names, core_l4_ick_ops);
1282
1283static struct clk wkup_32k_fck;
1284
1285static const char *wkup_32k_fck_parent_names[] = {
1286 "omap_32k_fck",
1287};
1288
1289DEFINE_STRUCT_CLK_HW_OMAP(wkup_32k_fck, "wkup_clkdm");
1290DEFINE_STRUCT_CLK(wkup_32k_fck, wkup_32k_fck_parent_names, core_l4_ick_ops);
1291
1292static struct clk gpio1_dbck;
1293
1294static const char *gpio1_dbck_parent_names[] = {
1295 "wkup_32k_fck",
1296};
1297
1298static struct clk_hw_omap gpio1_dbck_hw = {
1299 .hw = {
1300 .clk = &gpio1_dbck,
1301 },
1302 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1303 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
1304 .clkdm_name = "wkup_clkdm",
1305};
1306
1307DEFINE_STRUCT_CLK(gpio1_dbck, gpio1_dbck_parent_names, aes2_ick_ops);
1308
1309static struct clk wkup_l4_ick;
1310
1311DEFINE_STRUCT_CLK_HW_OMAP(wkup_l4_ick, "wkup_clkdm");
1312DEFINE_STRUCT_CLK(wkup_l4_ick, dpll3_ck_parent_names, core_l4_ick_ops);
1313
1314static struct clk gpio1_ick;
1315
1316static const char *gpio1_ick_parent_names[] = {
1317 "wkup_l4_ick",
1318};
1319
1320static struct clk_hw_omap gpio1_ick_hw = {
1321 .hw = {
1322 .clk = &gpio1_ick,
1323 },
1324 .ops = &clkhwops_iclk_wait,
1325 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1326 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
1327 .clkdm_name = "wkup_clkdm",
1328};
1329
1330DEFINE_STRUCT_CLK(gpio1_ick, gpio1_ick_parent_names, aes2_ick_ops);
1331
1332static struct clk per_32k_alwon_fck;
1333
1334DEFINE_STRUCT_CLK_HW_OMAP(per_32k_alwon_fck, "per_clkdm");
1335DEFINE_STRUCT_CLK(per_32k_alwon_fck, wkup_32k_fck_parent_names,
1336 core_l4_ick_ops);
1337
1338static struct clk gpio2_dbck;
1339
1340static const char *gpio2_dbck_parent_names[] = {
1341 "per_32k_alwon_fck",
1342};
1343
1344static struct clk_hw_omap gpio2_dbck_hw = {
1345 .hw = {
1346 .clk = &gpio2_dbck,
1347 },
1348 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1349 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
1350 .clkdm_name = "per_clkdm",
1351};
1352
1353DEFINE_STRUCT_CLK(gpio2_dbck, gpio2_dbck_parent_names, aes2_ick_ops);
1354
1355static struct clk per_l4_ick;
1356
1357DEFINE_STRUCT_CLK_HW_OMAP(per_l4_ick, "per_clkdm");
1358DEFINE_STRUCT_CLK(per_l4_ick, security_l4_ick2_parent_names, core_l4_ick_ops);
1359
1360static struct clk gpio2_ick;
1361
1362static const char *gpio2_ick_parent_names[] = {
1363 "per_l4_ick",
1364};
1365
1366static struct clk_hw_omap gpio2_ick_hw = {
1367 .hw = {
1368 .clk = &gpio2_ick,
1369 },
1370 .ops = &clkhwops_iclk_wait,
1371 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1372 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
1373 .clkdm_name = "per_clkdm",
1374};
1375
1376DEFINE_STRUCT_CLK(gpio2_ick, gpio2_ick_parent_names, aes2_ick_ops);
1377
1378static struct clk gpio3_dbck;
1379
1380static struct clk_hw_omap gpio3_dbck_hw = {
1381 .hw = {
1382 .clk = &gpio3_dbck,
1383 },
1384 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1385 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
1386 .clkdm_name = "per_clkdm",
1387};
1388
1389DEFINE_STRUCT_CLK(gpio3_dbck, gpio2_dbck_parent_names, aes2_ick_ops);
1390
1391static struct clk gpio3_ick;
1392
1393static struct clk_hw_omap gpio3_ick_hw = {
1394 .hw = {
1395 .clk = &gpio3_ick,
1396 },
1397 .ops = &clkhwops_iclk_wait,
1398 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1399 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
1400 .clkdm_name = "per_clkdm",
1401};
1402
1403DEFINE_STRUCT_CLK(gpio3_ick, gpio2_ick_parent_names, aes2_ick_ops);
1404
1405static struct clk gpio4_dbck;
1406
1407static struct clk_hw_omap gpio4_dbck_hw = {
1408 .hw = {
1409 .clk = &gpio4_dbck,
1410 },
1411 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1412 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
1413 .clkdm_name = "per_clkdm",
1414};
1415
1416DEFINE_STRUCT_CLK(gpio4_dbck, gpio2_dbck_parent_names, aes2_ick_ops);
1417
1418static struct clk gpio4_ick;
1419
1420static struct clk_hw_omap gpio4_ick_hw = {
1421 .hw = {
1422 .clk = &gpio4_ick,
1423 },
1424 .ops = &clkhwops_iclk_wait,
1425 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1426 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
1427 .clkdm_name = "per_clkdm",
1428};
1429
1430DEFINE_STRUCT_CLK(gpio4_ick, gpio2_ick_parent_names, aes2_ick_ops);
1431
1432static struct clk gpio5_dbck;
1433
1434static struct clk_hw_omap gpio5_dbck_hw = {
1435 .hw = {
1436 .clk = &gpio5_dbck,
1437 },
1438 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1439 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
1440 .clkdm_name = "per_clkdm",
1441};
1442
1443DEFINE_STRUCT_CLK(gpio5_dbck, gpio2_dbck_parent_names, aes2_ick_ops);
1444
1445static struct clk gpio5_ick;
1446
1447static struct clk_hw_omap gpio5_ick_hw = {
1448 .hw = {
1449 .clk = &gpio5_ick,
1450 },
1451 .ops = &clkhwops_iclk_wait,
1452 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1453 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
1454 .clkdm_name = "per_clkdm",
1455};
1456
1457DEFINE_STRUCT_CLK(gpio5_ick, gpio2_ick_parent_names, aes2_ick_ops);
1458
1459static struct clk gpio6_dbck;
1460
1461static struct clk_hw_omap gpio6_dbck_hw = {
1462 .hw = {
1463 .clk = &gpio6_dbck,
1464 },
1465 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1466 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
1467 .clkdm_name = "per_clkdm",
1468};
1469
1470DEFINE_STRUCT_CLK(gpio6_dbck, gpio2_dbck_parent_names, aes2_ick_ops);
1471
1472static struct clk gpio6_ick;
1473
1474static struct clk_hw_omap gpio6_ick_hw = {
1475 .hw = {
1476 .clk = &gpio6_ick,
1477 },
1478 .ops = &clkhwops_iclk_wait,
1479 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1480 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
1481 .clkdm_name = "per_clkdm",
1482};
1483
1484DEFINE_STRUCT_CLK(gpio6_ick, gpio2_ick_parent_names, aes2_ick_ops);
1485
1486static struct clk gpmc_fck;
1487
1488static struct clk_hw_omap gpmc_fck_hw = {
1489 .hw = {
1490 .clk = &gpmc_fck,
1491 },
1492 .flags = ENABLE_ON_INIT,
1493 .clkdm_name = "core_l3_clkdm",
1494};
1495
1496DEFINE_STRUCT_CLK(gpmc_fck, ipss_ick_parent_names, core_l4_ick_ops);
1497
1498static const struct clksel omap343x_gpt_clksel[] = {
1499 { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1500 { .parent = &sys_ck, .rates = gpt_sys_rates },
1501 { .parent = NULL },
1502};
1503
1504static const char *gpt10_fck_parent_names[] = {
1505 "omap_32k_fck", "sys_ck",
1506};
1507
1508DEFINE_CLK_OMAP_MUX_GATE(gpt10_fck, "core_l4_clkdm", omap343x_gpt_clksel,
1509 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1510 OMAP3430_CLKSEL_GPT10_MASK,
1511 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1512 OMAP3430_EN_GPT10_SHIFT, &clkhwops_wait,
1513 gpt10_fck_parent_names, clkout2_src_ck_ops);
1514
1515static struct clk gpt10_ick;
1516
1517static struct clk_hw_omap gpt10_ick_hw = {
1518 .hw = {
1519 .clk = &gpt10_ick,
1520 },
1521 .ops = &clkhwops_iclk_wait,
1522 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1523 .enable_bit = OMAP3430_EN_GPT10_SHIFT,
1524 .clkdm_name = "core_l4_clkdm",
1525};
1526
1527DEFINE_STRUCT_CLK(gpt10_ick, aes2_ick_parent_names, aes2_ick_ops);
1528
1529DEFINE_CLK_OMAP_MUX_GATE(gpt11_fck, "core_l4_clkdm", omap343x_gpt_clksel,
1530 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1531 OMAP3430_CLKSEL_GPT11_MASK,
1532 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1533 OMAP3430_EN_GPT11_SHIFT, &clkhwops_wait,
1534 gpt10_fck_parent_names, clkout2_src_ck_ops);
1535
1536static struct clk gpt11_ick;
1537
1538static struct clk_hw_omap gpt11_ick_hw = {
1539 .hw = {
1540 .clk = &gpt11_ick,
1541 },
1542 .ops = &clkhwops_iclk_wait,
1543 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1544 .enable_bit = OMAP3430_EN_GPT11_SHIFT,
1545 .clkdm_name = "core_l4_clkdm",
1546};
1547
1548DEFINE_STRUCT_CLK(gpt11_ick, aes2_ick_parent_names, aes2_ick_ops);
1549
1550static struct clk gpt12_fck;
1551
1552static const char *gpt12_fck_parent_names[] = {
1553 "secure_32k_fck",
1554};
1555
1556DEFINE_STRUCT_CLK_HW_OMAP(gpt12_fck, "wkup_clkdm");
1557DEFINE_STRUCT_CLK(gpt12_fck, gpt12_fck_parent_names, core_l4_ick_ops);
1558
1559static struct clk gpt12_ick;
1560
1561static struct clk_hw_omap gpt12_ick_hw = {
1562 .hw = {
1563 .clk = &gpt12_ick,
1564 },
1565 .ops = &clkhwops_iclk_wait,
1566 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1567 .enable_bit = OMAP3430_EN_GPT12_SHIFT,
1568 .clkdm_name = "wkup_clkdm",
1569};
1570
1571DEFINE_STRUCT_CLK(gpt12_ick, gpio1_ick_parent_names, aes2_ick_ops);
1572
1573DEFINE_CLK_OMAP_MUX_GATE(gpt1_fck, "wkup_clkdm", omap343x_gpt_clksel,
1574 OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1575 OMAP3430_CLKSEL_GPT1_MASK,
1576 OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1577 OMAP3430_EN_GPT1_SHIFT, &clkhwops_wait,
1578 gpt10_fck_parent_names, clkout2_src_ck_ops);
1579
1580static struct clk gpt1_ick;
1581
1582static struct clk_hw_omap gpt1_ick_hw = {
1583 .hw = {
1584 .clk = &gpt1_ick,
1585 },
1586 .ops = &clkhwops_iclk_wait,
1587 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1588 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
1589 .clkdm_name = "wkup_clkdm",
1590};
1591
1592DEFINE_STRUCT_CLK(gpt1_ick, gpio1_ick_parent_names, aes2_ick_ops);
1593
1594DEFINE_CLK_OMAP_MUX_GATE(gpt2_fck, "per_clkdm", omap343x_gpt_clksel,
1595 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1596 OMAP3430_CLKSEL_GPT2_MASK,
1597 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1598 OMAP3430_EN_GPT2_SHIFT, &clkhwops_wait,
1599 gpt10_fck_parent_names, clkout2_src_ck_ops);
1600
1601static struct clk gpt2_ick;
1602
1603static struct clk_hw_omap gpt2_ick_hw = {
1604 .hw = {
1605 .clk = &gpt2_ick,
1606 },
1607 .ops = &clkhwops_iclk_wait,
1608 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1609 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
1610 .clkdm_name = "per_clkdm",
1611};
1612
1613DEFINE_STRUCT_CLK(gpt2_ick, gpio2_ick_parent_names, aes2_ick_ops);
1614
1615DEFINE_CLK_OMAP_MUX_GATE(gpt3_fck, "per_clkdm", omap343x_gpt_clksel,
1616 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1617 OMAP3430_CLKSEL_GPT3_MASK,
1618 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1619 OMAP3430_EN_GPT3_SHIFT, &clkhwops_wait,
1620 gpt10_fck_parent_names, clkout2_src_ck_ops);
1621
1622static struct clk gpt3_ick;
1623
1624static struct clk_hw_omap gpt3_ick_hw = {
1625 .hw = {
1626 .clk = &gpt3_ick,
1627 },
1628 .ops = &clkhwops_iclk_wait,
1629 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1630 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
1631 .clkdm_name = "per_clkdm",
1632};
1633
1634DEFINE_STRUCT_CLK(gpt3_ick, gpio2_ick_parent_names, aes2_ick_ops);
1635
1636DEFINE_CLK_OMAP_MUX_GATE(gpt4_fck, "per_clkdm", omap343x_gpt_clksel,
1637 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1638 OMAP3430_CLKSEL_GPT4_MASK,
1639 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1640 OMAP3430_EN_GPT4_SHIFT, &clkhwops_wait,
1641 gpt10_fck_parent_names, clkout2_src_ck_ops);
1642
1643static struct clk gpt4_ick;
1644
1645static struct clk_hw_omap gpt4_ick_hw = {
1646 .hw = {
1647 .clk = &gpt4_ick,
1648 },
1649 .ops = &clkhwops_iclk_wait,
1650 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1651 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
1652 .clkdm_name = "per_clkdm",
1653};
1654
1655DEFINE_STRUCT_CLK(gpt4_ick, gpio2_ick_parent_names, aes2_ick_ops);
1656
1657DEFINE_CLK_OMAP_MUX_GATE(gpt5_fck, "per_clkdm", omap343x_gpt_clksel,
1658 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1659 OMAP3430_CLKSEL_GPT5_MASK,
1660 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1661 OMAP3430_EN_GPT5_SHIFT, &clkhwops_wait,
1662 gpt10_fck_parent_names, clkout2_src_ck_ops);
1663
1664static struct clk gpt5_ick;
1665
1666static struct clk_hw_omap gpt5_ick_hw = {
1667 .hw = {
1668 .clk = &gpt5_ick,
1669 },
1670 .ops = &clkhwops_iclk_wait,
1671 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1672 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
1673 .clkdm_name = "per_clkdm",
1674};
1675
1676DEFINE_STRUCT_CLK(gpt5_ick, gpio2_ick_parent_names, aes2_ick_ops);
1677
1678DEFINE_CLK_OMAP_MUX_GATE(gpt6_fck, "per_clkdm", omap343x_gpt_clksel,
1679 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1680 OMAP3430_CLKSEL_GPT6_MASK,
1681 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1682 OMAP3430_EN_GPT6_SHIFT, &clkhwops_wait,
1683 gpt10_fck_parent_names, clkout2_src_ck_ops);
1684
1685static struct clk gpt6_ick;
1686
1687static struct clk_hw_omap gpt6_ick_hw = {
1688 .hw = {
1689 .clk = &gpt6_ick,
1690 },
1691 .ops = &clkhwops_iclk_wait,
1692 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1693 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
1694 .clkdm_name = "per_clkdm",
1695};
1696
1697DEFINE_STRUCT_CLK(gpt6_ick, gpio2_ick_parent_names, aes2_ick_ops);
1698
1699DEFINE_CLK_OMAP_MUX_GATE(gpt7_fck, "per_clkdm", omap343x_gpt_clksel,
1700 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1701 OMAP3430_CLKSEL_GPT7_MASK,
1702 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1703 OMAP3430_EN_GPT7_SHIFT, &clkhwops_wait,
1704 gpt10_fck_parent_names, clkout2_src_ck_ops);
1705
1706static struct clk gpt7_ick;
1707
1708static struct clk_hw_omap gpt7_ick_hw = {
1709 .hw = {
1710 .clk = &gpt7_ick,
1711 },
1712 .ops = &clkhwops_iclk_wait,
1713 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1714 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
1715 .clkdm_name = "per_clkdm",
1716};
1717
1718DEFINE_STRUCT_CLK(gpt7_ick, gpio2_ick_parent_names, aes2_ick_ops);
1719
1720DEFINE_CLK_OMAP_MUX_GATE(gpt8_fck, "per_clkdm", omap343x_gpt_clksel,
1721 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1722 OMAP3430_CLKSEL_GPT8_MASK,
1723 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1724 OMAP3430_EN_GPT8_SHIFT, &clkhwops_wait,
1725 gpt10_fck_parent_names, clkout2_src_ck_ops);
1726
1727static struct clk gpt8_ick;
1728
1729static struct clk_hw_omap gpt8_ick_hw = {
1730 .hw = {
1731 .clk = &gpt8_ick,
1732 },
1733 .ops = &clkhwops_iclk_wait,
1734 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1735 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
1736 .clkdm_name = "per_clkdm",
1737};
1738
1739DEFINE_STRUCT_CLK(gpt8_ick, gpio2_ick_parent_names, aes2_ick_ops);
1740
1741DEFINE_CLK_OMAP_MUX_GATE(gpt9_fck, "per_clkdm", omap343x_gpt_clksel,
1742 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1743 OMAP3430_CLKSEL_GPT9_MASK,
1744 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1745 OMAP3430_EN_GPT9_SHIFT, &clkhwops_wait,
1746 gpt10_fck_parent_names, clkout2_src_ck_ops);
1747
1748static struct clk gpt9_ick;
1749
1750static struct clk_hw_omap gpt9_ick_hw = {
1751 .hw = {
1752 .clk = &gpt9_ick,
1753 },
1754 .ops = &clkhwops_iclk_wait,
1755 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1756 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
1757 .clkdm_name = "per_clkdm",
1758};
1759
1760DEFINE_STRUCT_CLK(gpt9_ick, gpio2_ick_parent_names, aes2_ick_ops);
1761
1762static struct clk hdq_fck;
1763
1764static const char *hdq_fck_parent_names[] = {
1765 "core_12m_fck",
1766};
1767
1768static struct clk_hw_omap hdq_fck_hw = {
1769 .hw = {
1770 .clk = &hdq_fck,
1771 },
1772 .ops = &clkhwops_wait,
1773 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1774 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1775 .clkdm_name = "core_l4_clkdm",
1776};
1777
1778DEFINE_STRUCT_CLK(hdq_fck, hdq_fck_parent_names, aes2_ick_ops);
1779
1780static struct clk hdq_ick;
1781
1782static struct clk_hw_omap hdq_ick_hw = {
1783 .hw = {
1784 .clk = &hdq_ick,
1785 },
1786 .ops = &clkhwops_iclk_wait,
1787 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1788 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1789 .clkdm_name = "core_l4_clkdm",
1790};
1791
1792DEFINE_STRUCT_CLK(hdq_ick, aes2_ick_parent_names, aes2_ick_ops);
1793
1794static struct clk hecc_ck;
1795
1796static struct clk_hw_omap hecc_ck_hw = {
1797 .hw = {
1798 .clk = &hecc_ck,
1799 },
1800 .ops = &clkhwops_am35xx_ipss_module_wait,
1801 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
1802 .enable_bit = AM35XX_HECC_VBUSP_CLK_SHIFT,
1803 .clkdm_name = "core_l3_clkdm",
1804};
1805
1806DEFINE_STRUCT_CLK(hecc_ck, dpll3_ck_parent_names, aes2_ick_ops);
1807
1808static struct clk hsotgusb_fck_am35xx;
1809
1810static struct clk_hw_omap hsotgusb_fck_am35xx_hw = {
1811 .hw = {
1812 .clk = &hsotgusb_fck_am35xx,
1813 },
1814 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
1815 .enable_bit = AM35XX_USBOTG_FCLK_SHIFT,
1816 .clkdm_name = "core_l3_clkdm",
1817};
1818
1819DEFINE_STRUCT_CLK(hsotgusb_fck_am35xx, dpll3_ck_parent_names, aes2_ick_ops);
1820
1821static struct clk hsotgusb_ick_3430es1;
1822
1823static struct clk_hw_omap hsotgusb_ick_3430es1_hw = {
1824 .hw = {
1825 .clk = &hsotgusb_ick_3430es1,
1826 },
1827 .ops = &clkhwops_iclk,
1828 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1829 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1830 .clkdm_name = "core_l3_clkdm",
1831};
1832
1833DEFINE_STRUCT_CLK(hsotgusb_ick_3430es1, ipss_ick_parent_names, aes2_ick_ops);
1834
1835static struct clk hsotgusb_ick_3430es2;
1836
1837static struct clk_hw_omap hsotgusb_ick_3430es2_hw = {
1838 .hw = {
1839 .clk = &hsotgusb_ick_3430es2,
1840 },
1841 .ops = &clkhwops_omap3430es2_iclk_hsotgusb_wait,
1842 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1843 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1844 .clkdm_name = "core_l3_clkdm",
1845};
1846
1847DEFINE_STRUCT_CLK(hsotgusb_ick_3430es2, ipss_ick_parent_names, aes2_ick_ops);
1848
1849static struct clk hsotgusb_ick_am35xx;
1850
1851static struct clk_hw_omap hsotgusb_ick_am35xx_hw = {
1852 .hw = {
1853 .clk = &hsotgusb_ick_am35xx,
1854 },
1855 .ops = &clkhwops_am35xx_ipss_module_wait,
1856 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
1857 .enable_bit = AM35XX_USBOTG_VBUSP_CLK_SHIFT,
1858 .clkdm_name = "core_l3_clkdm",
1859};
1860
1861DEFINE_STRUCT_CLK(hsotgusb_ick_am35xx, emac_ick_parent_names, aes2_ick_ops);
1862
1863static struct clk i2c1_fck;
1864
1865static struct clk_hw_omap i2c1_fck_hw = {
1866 .hw = {
1867 .clk = &i2c1_fck,
1868 },
1869 .ops = &clkhwops_wait,
1870 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1871 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
1872 .clkdm_name = "core_l4_clkdm",
1873};
1874
1875DEFINE_STRUCT_CLK(i2c1_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
1876
1877static struct clk i2c1_ick;
1878
1879static struct clk_hw_omap i2c1_ick_hw = {
1880 .hw = {
1881 .clk = &i2c1_ick,
1882 },
1883 .ops = &clkhwops_iclk_wait,
1884 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1885 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
1886 .clkdm_name = "core_l4_clkdm",
1887};
1888
1889DEFINE_STRUCT_CLK(i2c1_ick, aes2_ick_parent_names, aes2_ick_ops);
1890
1891static struct clk i2c2_fck;
1892
1893static struct clk_hw_omap i2c2_fck_hw = {
1894 .hw = {
1895 .clk = &i2c2_fck,
1896 },
1897 .ops = &clkhwops_wait,
1898 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1899 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
1900 .clkdm_name = "core_l4_clkdm",
1901};
1902
1903DEFINE_STRUCT_CLK(i2c2_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
1904
1905static struct clk i2c2_ick;
1906
1907static struct clk_hw_omap i2c2_ick_hw = {
1908 .hw = {
1909 .clk = &i2c2_ick,
1910 },
1911 .ops = &clkhwops_iclk_wait,
1912 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1913 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
1914 .clkdm_name = "core_l4_clkdm",
1915};
1916
1917DEFINE_STRUCT_CLK(i2c2_ick, aes2_ick_parent_names, aes2_ick_ops);
1918
1919static struct clk i2c3_fck;
1920
1921static struct clk_hw_omap i2c3_fck_hw = {
1922 .hw = {
1923 .clk = &i2c3_fck,
1924 },
1925 .ops = &clkhwops_wait,
1926 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1927 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
1928 .clkdm_name = "core_l4_clkdm",
1929};
1930
1931DEFINE_STRUCT_CLK(i2c3_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
1932
1933static struct clk i2c3_ick;
1934
1935static struct clk_hw_omap i2c3_ick_hw = {
1936 .hw = {
1937 .clk = &i2c3_ick,
1938 },
1939 .ops = &clkhwops_iclk_wait,
1940 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1941 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
1942 .clkdm_name = "core_l4_clkdm",
1943};
1944
1945DEFINE_STRUCT_CLK(i2c3_ick, aes2_ick_parent_names, aes2_ick_ops);
1946
1947static struct clk icr_ick;
1948
1949static struct clk_hw_omap icr_ick_hw = {
1950 .hw = {
1951 .clk = &icr_ick,
1952 },
1953 .ops = &clkhwops_iclk_wait,
1954 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1955 .enable_bit = OMAP3430_EN_ICR_SHIFT,
1956 .clkdm_name = "core_l4_clkdm",
1957};
1958
1959DEFINE_STRUCT_CLK(icr_ick, aes2_ick_parent_names, aes2_ick_ops);
1960
1961static struct clk iva2_ck;
1962
1963static const char *iva2_ck_parent_names[] = {
1964 "dpll2_m2_ck",
1965};
1966
1967static struct clk_hw_omap iva2_ck_hw = {
1968 .hw = {
1969 .clk = &iva2_ck,
1970 },
1971 .ops = &clkhwops_wait,
1972 .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
1973 .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1974 .clkdm_name = "iva2_clkdm",
1975};
1976
1977DEFINE_STRUCT_CLK(iva2_ck, iva2_ck_parent_names, aes2_ick_ops);
1978
1979static struct clk mad2d_ick;
1980
1981static struct clk_hw_omap mad2d_ick_hw = {
1982 .hw = {
1983 .clk = &mad2d_ick,
1984 },
1985 .ops = &clkhwops_iclk_wait,
1986 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1987 .enable_bit = OMAP3430_EN_MAD2D_SHIFT,
1988 .clkdm_name = "d2d_clkdm",
1989};
1990
1991DEFINE_STRUCT_CLK(mad2d_ick, core_l3_ick_parent_names, aes2_ick_ops);
1992
1993static struct clk mailboxes_ick;
1994
1995static struct clk_hw_omap mailboxes_ick_hw = {
1996 .hw = {
1997 .clk = &mailboxes_ick,
1998 },
1999 .ops = &clkhwops_iclk_wait,
2000 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2001 .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT,
2002 .clkdm_name = "core_l4_clkdm",
2003};
2004
2005DEFINE_STRUCT_CLK(mailboxes_ick, aes2_ick_parent_names, aes2_ick_ops);
2006
2007static const struct clksel_rate common_mcbsp_96m_rates[] = {
2008 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
2009 { .div = 0 }
2010};
2011
2012static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
2013 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
2014 { .div = 0 }
2015};
2016
2017static const struct clksel mcbsp_15_clksel[] = {
2018 { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
2019 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
2020 { .parent = NULL },
2021};
2022
2023static const char *mcbsp1_fck_parent_names[] = {
2024 "core_96m_fck", "mcbsp_clks",
2025};
2026
2027DEFINE_CLK_OMAP_MUX_GATE(mcbsp1_fck, "core_l4_clkdm", mcbsp_15_clksel,
2028 OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2029 OMAP2_MCBSP1_CLKS_MASK,
2030 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2031 OMAP3430_EN_MCBSP1_SHIFT, &clkhwops_wait,
2032 mcbsp1_fck_parent_names, clkout2_src_ck_ops);
2033
2034static struct clk mcbsp1_ick;
2035
2036static struct clk_hw_omap mcbsp1_ick_hw = {
2037 .hw = {
2038 .clk = &mcbsp1_ick,
2039 },
2040 .ops = &clkhwops_iclk_wait,
2041 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2042 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
2043 .clkdm_name = "core_l4_clkdm",
2044};
2045
2046DEFINE_STRUCT_CLK(mcbsp1_ick, aes2_ick_parent_names, aes2_ick_ops);
2047
2048static struct clk per_96m_fck;
2049
2050DEFINE_STRUCT_CLK_HW_OMAP(per_96m_fck, "per_clkdm");
2051DEFINE_STRUCT_CLK(per_96m_fck, cm_96m_fck_parent_names, core_l4_ick_ops);
2052
2053static const struct clksel mcbsp_234_clksel[] = {
2054 { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates },
2055 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
2056 { .parent = NULL },
2057};
2058
2059static const char *mcbsp2_fck_parent_names[] = {
2060 "per_96m_fck", "mcbsp_clks",
2061};
2062
2063DEFINE_CLK_OMAP_MUX_GATE(mcbsp2_fck, "per_clkdm", mcbsp_234_clksel,
2064 OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2065 OMAP2_MCBSP2_CLKS_MASK,
2066 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2067 OMAP3430_EN_MCBSP2_SHIFT, &clkhwops_wait,
2068 mcbsp2_fck_parent_names, clkout2_src_ck_ops);
2069
2070static struct clk mcbsp2_ick;
2071
2072static struct clk_hw_omap mcbsp2_ick_hw = {
2073 .hw = {
2074 .clk = &mcbsp2_ick,
2075 },
2076 .ops = &clkhwops_iclk_wait,
2077 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2078 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
2079 .clkdm_name = "per_clkdm",
2080};
2081
2082DEFINE_STRUCT_CLK(mcbsp2_ick, gpio2_ick_parent_names, aes2_ick_ops);
2083
2084DEFINE_CLK_OMAP_MUX_GATE(mcbsp3_fck, "per_clkdm", mcbsp_234_clksel,
2085 OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2086 OMAP2_MCBSP3_CLKS_MASK,
2087 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2088 OMAP3430_EN_MCBSP3_SHIFT, &clkhwops_wait,
2089 mcbsp2_fck_parent_names, clkout2_src_ck_ops);
2090
2091static struct clk mcbsp3_ick;
2092
2093static struct clk_hw_omap mcbsp3_ick_hw = {
2094 .hw = {
2095 .clk = &mcbsp3_ick,
2096 },
2097 .ops = &clkhwops_iclk_wait,
2098 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2099 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
2100 .clkdm_name = "per_clkdm",
2101};
2102
2103DEFINE_STRUCT_CLK(mcbsp3_ick, gpio2_ick_parent_names, aes2_ick_ops);
2104
2105DEFINE_CLK_OMAP_MUX_GATE(mcbsp4_fck, "per_clkdm", mcbsp_234_clksel,
2106 OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2107 OMAP2_MCBSP4_CLKS_MASK,
2108 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2109 OMAP3430_EN_MCBSP4_SHIFT, &clkhwops_wait,
2110 mcbsp2_fck_parent_names, clkout2_src_ck_ops);
2111
2112static struct clk mcbsp4_ick;
2113
2114static struct clk_hw_omap mcbsp4_ick_hw = {
2115 .hw = {
2116 .clk = &mcbsp4_ick,
2117 },
2118 .ops = &clkhwops_iclk_wait,
2119 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2120 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
2121 .clkdm_name = "per_clkdm",
2122};
2123
2124DEFINE_STRUCT_CLK(mcbsp4_ick, gpio2_ick_parent_names, aes2_ick_ops);
2125
2126DEFINE_CLK_OMAP_MUX_GATE(mcbsp5_fck, "core_l4_clkdm", mcbsp_15_clksel,
2127 OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2128 OMAP2_MCBSP5_CLKS_MASK,
2129 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2130 OMAP3430_EN_MCBSP5_SHIFT, &clkhwops_wait,
2131 mcbsp1_fck_parent_names, clkout2_src_ck_ops);
2132
2133static struct clk mcbsp5_ick;
2134
2135static struct clk_hw_omap mcbsp5_ick_hw = {
2136 .hw = {
2137 .clk = &mcbsp5_ick,
2138 },
2139 .ops = &clkhwops_iclk_wait,
2140 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2141 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
2142 .clkdm_name = "core_l4_clkdm",
2143};
2144
2145DEFINE_STRUCT_CLK(mcbsp5_ick, aes2_ick_parent_names, aes2_ick_ops);
2146
2147static struct clk mcspi1_fck;
2148
2149static struct clk_hw_omap mcspi1_fck_hw = {
2150 .hw = {
2151 .clk = &mcspi1_fck,
2152 },
2153 .ops = &clkhwops_wait,
2154 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2155 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
2156 .clkdm_name = "core_l4_clkdm",
2157};
2158
2159DEFINE_STRUCT_CLK(mcspi1_fck, fshostusb_fck_parent_names, aes2_ick_ops);
2160
2161static struct clk mcspi1_ick;
2162
2163static struct clk_hw_omap mcspi1_ick_hw = {
2164 .hw = {
2165 .clk = &mcspi1_ick,
2166 },
2167 .ops = &clkhwops_iclk_wait,
2168 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2169 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
2170 .clkdm_name = "core_l4_clkdm",
2171};
2172
2173DEFINE_STRUCT_CLK(mcspi1_ick, aes2_ick_parent_names, aes2_ick_ops);
2174
2175static struct clk mcspi2_fck;
2176
2177static struct clk_hw_omap mcspi2_fck_hw = {
2178 .hw = {
2179 .clk = &mcspi2_fck,
2180 },
2181 .ops = &clkhwops_wait,
2182 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2183 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
2184 .clkdm_name = "core_l4_clkdm",
2185};
2186
2187DEFINE_STRUCT_CLK(mcspi2_fck, fshostusb_fck_parent_names, aes2_ick_ops);
2188
2189static struct clk mcspi2_ick;
2190
2191static struct clk_hw_omap mcspi2_ick_hw = {
2192 .hw = {
2193 .clk = &mcspi2_ick,
2194 },
2195 .ops = &clkhwops_iclk_wait,
2196 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2197 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
2198 .clkdm_name = "core_l4_clkdm",
2199};
2200
2201DEFINE_STRUCT_CLK(mcspi2_ick, aes2_ick_parent_names, aes2_ick_ops);
2202
2203static struct clk mcspi3_fck;
2204
2205static struct clk_hw_omap mcspi3_fck_hw = {
2206 .hw = {
2207 .clk = &mcspi3_fck,
2208 },
2209 .ops = &clkhwops_wait,
2210 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2211 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
2212 .clkdm_name = "core_l4_clkdm",
2213};
2214
2215DEFINE_STRUCT_CLK(mcspi3_fck, fshostusb_fck_parent_names, aes2_ick_ops);
2216
2217static struct clk mcspi3_ick;
2218
2219static struct clk_hw_omap mcspi3_ick_hw = {
2220 .hw = {
2221 .clk = &mcspi3_ick,
2222 },
2223 .ops = &clkhwops_iclk_wait,
2224 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2225 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
2226 .clkdm_name = "core_l4_clkdm",
2227};
2228
2229DEFINE_STRUCT_CLK(mcspi3_ick, aes2_ick_parent_names, aes2_ick_ops);
2230
2231static struct clk mcspi4_fck;
2232
2233static struct clk_hw_omap mcspi4_fck_hw = {
2234 .hw = {
2235 .clk = &mcspi4_fck,
2236 },
2237 .ops = &clkhwops_wait,
2238 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2239 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
2240 .clkdm_name = "core_l4_clkdm",
2241};
2242
2243DEFINE_STRUCT_CLK(mcspi4_fck, fshostusb_fck_parent_names, aes2_ick_ops);
2244
2245static struct clk mcspi4_ick;
2246
2247static struct clk_hw_omap mcspi4_ick_hw = {
2248 .hw = {
2249 .clk = &mcspi4_ick,
2250 },
2251 .ops = &clkhwops_iclk_wait,
2252 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2253 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
2254 .clkdm_name = "core_l4_clkdm",
2255};
2256
2257DEFINE_STRUCT_CLK(mcspi4_ick, aes2_ick_parent_names, aes2_ick_ops);
2258
2259static struct clk mmchs1_fck;
2260
2261static struct clk_hw_omap mmchs1_fck_hw = {
2262 .hw = {
2263 .clk = &mmchs1_fck,
2264 },
2265 .ops = &clkhwops_wait,
2266 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2267 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
2268 .clkdm_name = "core_l4_clkdm",
2269};
2270
2271DEFINE_STRUCT_CLK(mmchs1_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
2272
2273static struct clk mmchs1_ick;
2274
2275static struct clk_hw_omap mmchs1_ick_hw = {
2276 .hw = {
2277 .clk = &mmchs1_ick,
2278 },
2279 .ops = &clkhwops_iclk_wait,
2280 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2281 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
2282 .clkdm_name = "core_l4_clkdm",
2283};
2284
2285DEFINE_STRUCT_CLK(mmchs1_ick, aes2_ick_parent_names, aes2_ick_ops);
2286
2287static struct clk mmchs2_fck;
2288
2289static struct clk_hw_omap mmchs2_fck_hw = {
2290 .hw = {
2291 .clk = &mmchs2_fck,
2292 },
2293 .ops = &clkhwops_wait,
2294 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2295 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
2296 .clkdm_name = "core_l4_clkdm",
2297};
2298
2299DEFINE_STRUCT_CLK(mmchs2_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
2300
2301static struct clk mmchs2_ick;
2302
2303static struct clk_hw_omap mmchs2_ick_hw = {
2304 .hw = {
2305 .clk = &mmchs2_ick,
2306 },
2307 .ops = &clkhwops_iclk_wait,
2308 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2309 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
2310 .clkdm_name = "core_l4_clkdm",
2311};
2312
2313DEFINE_STRUCT_CLK(mmchs2_ick, aes2_ick_parent_names, aes2_ick_ops);
2314
2315static struct clk mmchs3_fck;
2316
2317static struct clk_hw_omap mmchs3_fck_hw = {
2318 .hw = {
2319 .clk = &mmchs3_fck,
2320 },
2321 .ops = &clkhwops_wait,
2322 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2323 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
2324 .clkdm_name = "core_l4_clkdm",
2325};
2326
2327DEFINE_STRUCT_CLK(mmchs3_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
2328
2329static struct clk mmchs3_ick;
2330
2331static struct clk_hw_omap mmchs3_ick_hw = {
2332 .hw = {
2333 .clk = &mmchs3_ick,
2334 },
2335 .ops = &clkhwops_iclk_wait,
2336 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2337 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
2338 .clkdm_name = "core_l4_clkdm",
2339};
2340
2341DEFINE_STRUCT_CLK(mmchs3_ick, aes2_ick_parent_names, aes2_ick_ops);
2342
2343static struct clk modem_fck;
2344
2345static struct clk_hw_omap modem_fck_hw = {
2346 .hw = {
2347 .clk = &modem_fck,
2348 },
2349 .ops = &clkhwops_iclk_wait,
2350 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2351 .enable_bit = OMAP3430_EN_MODEM_SHIFT,
2352 .clkdm_name = "d2d_clkdm",
2353};
2354
2355DEFINE_STRUCT_CLK(modem_fck, dpll3_ck_parent_names, aes2_ick_ops);
2356
2357static struct clk mspro_fck;
2358
2359static struct clk_hw_omap mspro_fck_hw = {
2360 .hw = {
2361 .clk = &mspro_fck,
2362 },
2363 .ops = &clkhwops_wait,
2364 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2365 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
2366 .clkdm_name = "core_l4_clkdm",
2367};
2368
2369DEFINE_STRUCT_CLK(mspro_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
2370
2371static struct clk mspro_ick;
2372
2373static struct clk_hw_omap mspro_ick_hw = {
2374 .hw = {
2375 .clk = &mspro_ick,
2376 },
2377 .ops = &clkhwops_iclk_wait,
2378 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2379 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
2380 .clkdm_name = "core_l4_clkdm",
2381};
2382
2383DEFINE_STRUCT_CLK(mspro_ick, aes2_ick_parent_names, aes2_ick_ops);
2384
2385static struct clk omap_192m_alwon_fck;
2386
2387DEFINE_STRUCT_CLK_HW_OMAP(omap_192m_alwon_fck, NULL);
2388DEFINE_STRUCT_CLK(omap_192m_alwon_fck, omap_96m_alwon_fck_parent_names,
2389 core_ck_ops);
2390
2391static struct clk omap_32ksync_ick;
2392
2393static struct clk_hw_omap omap_32ksync_ick_hw = {
2394 .hw = {
2395 .clk = &omap_32ksync_ick,
2396 },
2397 .ops = &clkhwops_iclk_wait,
2398 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2399 .enable_bit = OMAP3430_EN_32KSYNC_SHIFT,
2400 .clkdm_name = "wkup_clkdm",
2401};
2402
2403DEFINE_STRUCT_CLK(omap_32ksync_ick, gpio1_ick_parent_names, aes2_ick_ops);
2404
2405static const struct clksel_rate omap_96m_alwon_fck_rates[] = {
2406 { .div = 1, .val = 1, .flags = RATE_IN_36XX },
2407 { .div = 2, .val = 2, .flags = RATE_IN_36XX },
2408 { .div = 0 }
2409};
2410
2411static const struct clksel omap_96m_alwon_fck_clksel[] = {
2412 { .parent = &omap_192m_alwon_fck, .rates = omap_96m_alwon_fck_rates },
2413 { .parent = NULL }
2414};
2415
2416static struct clk omap_96m_alwon_fck_3630;
2417
2418static const char *omap_96m_alwon_fck_3630_parent_names[] = {
2419 "omap_192m_alwon_fck",
2420};
2421
2422static const struct clk_ops omap_96m_alwon_fck_3630_ops = {
2423 .set_rate = &omap2_clksel_set_rate,
2424 .recalc_rate = &omap2_clksel_recalc,
2425 .round_rate = &omap2_clksel_round_rate,
2426};
2427
2428static struct clk_hw_omap omap_96m_alwon_fck_3630_hw = {
2429 .hw = {
2430 .clk = &omap_96m_alwon_fck_3630,
2431 },
2432 .clksel = omap_96m_alwon_fck_clksel,
2433 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2434 .clksel_mask = OMAP3630_CLKSEL_96M_MASK,
2435};
2436
2437static struct clk omap_96m_alwon_fck_3630 = {
2438 .name = "omap_96m_alwon_fck",
2439 .hw = &omap_96m_alwon_fck_3630_hw.hw,
2440 .parent_names = omap_96m_alwon_fck_3630_parent_names,
2441 .num_parents = ARRAY_SIZE(omap_96m_alwon_fck_3630_parent_names),
2442 .ops = &omap_96m_alwon_fck_3630_ops,
2443};
2444
2445static struct clk omapctrl_ick;
2446
2447static struct clk_hw_omap omapctrl_ick_hw = {
2448 .hw = {
2449 .clk = &omapctrl_ick,
2450 },
2451 .ops = &clkhwops_iclk_wait,
2452 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2453 .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT,
2454 .flags = ENABLE_ON_INIT,
2455 .clkdm_name = "core_l4_clkdm",
2456};
2457
2458DEFINE_STRUCT_CLK(omapctrl_ick, aes2_ick_parent_names, aes2_ick_ops);
2459
2460DEFINE_CLK_DIVIDER(pclk_fck, "emu_src_ck", &emu_src_ck, 0x0,
2461 OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2462 OMAP3430_CLKSEL_PCLK_SHIFT, OMAP3430_CLKSEL_PCLK_WIDTH,
2463 CLK_DIVIDER_ONE_BASED, NULL);
2464
2465DEFINE_CLK_DIVIDER(pclkx2_fck, "emu_src_ck", &emu_src_ck, 0x0,
2466 OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2467 OMAP3430_CLKSEL_PCLKX2_SHIFT, OMAP3430_CLKSEL_PCLKX2_WIDTH,
2468 CLK_DIVIDER_ONE_BASED, NULL);
2469
2470static struct clk per_48m_fck;
2471
2472DEFINE_STRUCT_CLK_HW_OMAP(per_48m_fck, "per_clkdm");
2473DEFINE_STRUCT_CLK(per_48m_fck, core_48m_fck_parent_names, core_l4_ick_ops);
2474
2475static struct clk security_l3_ick;
2476
2477DEFINE_STRUCT_CLK_HW_OMAP(security_l3_ick, NULL);
2478DEFINE_STRUCT_CLK(security_l3_ick, core_l3_ick_parent_names, core_ck_ops);
2479
2480static struct clk pka_ick;
2481
2482static const char *pka_ick_parent_names[] = {
2483 "security_l3_ick",
2484};
2485
2486static struct clk_hw_omap pka_ick_hw = {
2487 .hw = {
2488 .clk = &pka_ick,
2489 },
2490 .ops = &clkhwops_iclk_wait,
2491 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2492 .enable_bit = OMAP3430_EN_PKA_SHIFT,
2493};
2494
2495DEFINE_STRUCT_CLK(pka_ick, pka_ick_parent_names, aes1_ick_ops);
2496
2497DEFINE_CLK_DIVIDER(rm_ick, "l4_ick", &l4_ick, 0x0,
2498 OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2499 OMAP3430_CLKSEL_RM_SHIFT, OMAP3430_CLKSEL_RM_WIDTH,
2500 CLK_DIVIDER_ONE_BASED, NULL);
2501
2502static struct clk rng_ick;
2503
2504static struct clk_hw_omap rng_ick_hw = {
2505 .hw = {
2506 .clk = &rng_ick,
2507 },
2508 .ops = &clkhwops_iclk_wait,
2509 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2510 .enable_bit = OMAP3430_EN_RNG_SHIFT,
2511};
2512
2513DEFINE_STRUCT_CLK(rng_ick, aes1_ick_parent_names, aes1_ick_ops);
2514
2515static struct clk sad2d_ick;
2516
2517static struct clk_hw_omap sad2d_ick_hw = {
2518 .hw = {
2519 .clk = &sad2d_ick,
2520 },
2521 .ops = &clkhwops_iclk_wait,
2522 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2523 .enable_bit = OMAP3430_EN_SAD2D_SHIFT,
2524 .clkdm_name = "d2d_clkdm",
2525};
2526
2527DEFINE_STRUCT_CLK(sad2d_ick, core_l3_ick_parent_names, aes2_ick_ops);
2528
2529static struct clk sdrc_ick;
2530
2531static struct clk_hw_omap sdrc_ick_hw = {
2532 .hw = {
2533 .clk = &sdrc_ick,
2534 },
2535 .ops = &clkhwops_wait,
2536 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2537 .enable_bit = OMAP3430_EN_SDRC_SHIFT,
2538 .flags = ENABLE_ON_INIT,
2539 .clkdm_name = "core_l3_clkdm",
2540};
2541
2542DEFINE_STRUCT_CLK(sdrc_ick, ipss_ick_parent_names, aes2_ick_ops);
2543
2544static const struct clksel_rate sgx_core_rates[] = {
2545 { .div = 2, .val = 5, .flags = RATE_IN_36XX },
2546 { .div = 3, .val = 0, .flags = RATE_IN_3XXX },
2547 { .div = 4, .val = 1, .flags = RATE_IN_3XXX },
2548 { .div = 6, .val = 2, .flags = RATE_IN_3XXX },
2549 { .div = 0 }
2550};
2551
2552static const struct clksel_rate sgx_96m_rates[] = {
2553 { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
2554 { .div = 0 }
2555};
2556
2557static const struct clksel_rate sgx_192m_rates[] = {
2558 { .div = 1, .val = 4, .flags = RATE_IN_36XX },
2559 { .div = 0 }
2560};
2561
2562static const struct clksel_rate sgx_corex2_rates[] = {
2563 { .div = 3, .val = 6, .flags = RATE_IN_36XX },
2564 { .div = 5, .val = 7, .flags = RATE_IN_36XX },
2565 { .div = 0 }
2566};
2567
2568static const struct clksel sgx_clksel[] = {
2569 { .parent = &core_ck, .rates = sgx_core_rates },
2570 { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
2571 { .parent = &omap_192m_alwon_fck, .rates = sgx_192m_rates },
2572 { .parent = &corex2_fck, .rates = sgx_corex2_rates },
2573 { .parent = NULL },
2574};
2575
2576static const char *sgx_fck_parent_names[] = {
2577 "core_ck", "cm_96m_fck", "omap_192m_alwon_fck", "corex2_fck",
2578};
2579
2580static struct clk sgx_fck;
2581
2582static const struct clk_ops sgx_fck_ops = {
2583 .init = &omap2_init_clk_clkdm,
2584 .enable = &omap2_dflt_clk_enable,
2585 .disable = &omap2_dflt_clk_disable,
2586 .is_enabled = &omap2_dflt_clk_is_enabled,
2587 .recalc_rate = &omap2_clksel_recalc,
2588 .set_rate = &omap2_clksel_set_rate,
2589 .round_rate = &omap2_clksel_round_rate,
2590 .get_parent = &omap2_clksel_find_parent_index,
2591 .set_parent = &omap2_clksel_set_parent,
2592};
2593
2594DEFINE_CLK_OMAP_MUX_GATE(sgx_fck, "sgx_clkdm", sgx_clksel,
2595 OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
2596 OMAP3430ES2_CLKSEL_SGX_MASK,
2597 OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
2598 OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
2599 &clkhwops_wait, sgx_fck_parent_names, sgx_fck_ops);
2600
2601static struct clk sgx_ick;
2602
2603static struct clk_hw_omap sgx_ick_hw = {
2604 .hw = {
2605 .clk = &sgx_ick,
2606 },
2607 .ops = &clkhwops_wait,
2608 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
2609 .enable_bit = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
2610 .clkdm_name = "sgx_clkdm",
2611};
2612
2613DEFINE_STRUCT_CLK(sgx_ick, core_l3_ick_parent_names, aes2_ick_ops);
2614
2615static struct clk sha11_ick;
2616
2617static struct clk_hw_omap sha11_ick_hw = {
2618 .hw = {
2619 .clk = &sha11_ick,
2620 },
2621 .ops = &clkhwops_iclk_wait,
2622 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2623 .enable_bit = OMAP3430_EN_SHA11_SHIFT,
2624};
2625
2626DEFINE_STRUCT_CLK(sha11_ick, aes1_ick_parent_names, aes1_ick_ops);
2627
2628static struct clk sha12_ick;
2629
2630static struct clk_hw_omap sha12_ick_hw = {
2631 .hw = {
2632 .clk = &sha12_ick,
2633 },
2634 .ops = &clkhwops_iclk_wait,
2635 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2636 .enable_bit = OMAP3430_EN_SHA12_SHIFT,
2637 .clkdm_name = "core_l4_clkdm",
2638};
2639
2640DEFINE_STRUCT_CLK(sha12_ick, aes2_ick_parent_names, aes2_ick_ops);
2641
2642static struct clk sr1_fck;
2643
2644static struct clk_hw_omap sr1_fck_hw = {
2645 .hw = {
2646 .clk = &sr1_fck,
2647 },
2648 .ops = &clkhwops_wait,
2649 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2650 .enable_bit = OMAP3430_EN_SR1_SHIFT,
2651 .clkdm_name = "wkup_clkdm",
2652};
2653
2654DEFINE_STRUCT_CLK(sr1_fck, dpll3_ck_parent_names, aes2_ick_ops);
2655
2656static struct clk sr2_fck;
2657
2658static struct clk_hw_omap sr2_fck_hw = {
2659 .hw = {
2660 .clk = &sr2_fck,
2661 },
2662 .ops = &clkhwops_wait,
2663 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2664 .enable_bit = OMAP3430_EN_SR2_SHIFT,
2665 .clkdm_name = "wkup_clkdm",
2666};
2667
2668DEFINE_STRUCT_CLK(sr2_fck, dpll3_ck_parent_names, aes2_ick_ops);
2669
2670static struct clk sr_l4_ick;
2671
2672DEFINE_STRUCT_CLK_HW_OMAP(sr_l4_ick, "core_l4_clkdm");
2673DEFINE_STRUCT_CLK(sr_l4_ick, security_l4_ick2_parent_names, core_l4_ick_ops);
2674
2675static struct clk ssi_l4_ick;
2676
2677DEFINE_STRUCT_CLK_HW_OMAP(ssi_l4_ick, "core_l4_clkdm");
2678DEFINE_STRUCT_CLK(ssi_l4_ick, security_l4_ick2_parent_names, core_l4_ick_ops);
2679
2680static struct clk ssi_ick_3430es1;
2681
2682static const char *ssi_ick_3430es1_parent_names[] = {
2683 "ssi_l4_ick",
2684};
2685
2686static struct clk_hw_omap ssi_ick_3430es1_hw = {
2687 .hw = {
2688 .clk = &ssi_ick_3430es1,
2689 },
2690 .ops = &clkhwops_iclk,
2691 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2692 .enable_bit = OMAP3430_EN_SSI_SHIFT,
2693 .clkdm_name = "core_l4_clkdm",
2694};
2695
2696DEFINE_STRUCT_CLK(ssi_ick_3430es1, ssi_ick_3430es1_parent_names, aes2_ick_ops);
2697
2698static struct clk ssi_ick_3430es2;
2699
2700static struct clk_hw_omap ssi_ick_3430es2_hw = {
2701 .hw = {
2702 .clk = &ssi_ick_3430es2,
2703 },
2704 .ops = &clkhwops_omap3430es2_iclk_ssi_wait,
2705 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2706 .enable_bit = OMAP3430_EN_SSI_SHIFT,
2707 .clkdm_name = "core_l4_clkdm",
2708};
2709
2710DEFINE_STRUCT_CLK(ssi_ick_3430es2, ssi_ick_3430es1_parent_names, aes2_ick_ops);
2711
2712static const struct clksel_rate ssi_ssr_corex2_rates[] = {
2713 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
2714 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
2715 { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
2716 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
2717 { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
2718 { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
2719 { .div = 0 }
2720};
2721
2722static const struct clksel ssi_ssr_clksel[] = {
2723 { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
2724 { .parent = NULL },
2725};
2726
2727static const char *ssi_ssr_fck_3430es1_parent_names[] = {
2728 "corex2_fck",
2729};
2730
2731static const struct clk_ops ssi_ssr_fck_3430es1_ops = {
2732 .init = &omap2_init_clk_clkdm,
2733 .enable = &omap2_dflt_clk_enable,
2734 .disable = &omap2_dflt_clk_disable,
2735 .is_enabled = &omap2_dflt_clk_is_enabled,
2736 .recalc_rate = &omap2_clksel_recalc,
2737 .set_rate = &omap2_clksel_set_rate,
2738 .round_rate = &omap2_clksel_round_rate,
2739};
2740
2741DEFINE_CLK_OMAP_MUX_GATE(ssi_ssr_fck_3430es1, "core_l4_clkdm",
2742 ssi_ssr_clksel, OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2743 OMAP3430_CLKSEL_SSI_MASK,
2744 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2745 OMAP3430_EN_SSI_SHIFT,
2746 NULL, ssi_ssr_fck_3430es1_parent_names,
2747 ssi_ssr_fck_3430es1_ops);
2748
2749DEFINE_CLK_OMAP_MUX_GATE(ssi_ssr_fck_3430es2, "core_l4_clkdm",
2750 ssi_ssr_clksel, OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2751 OMAP3430_CLKSEL_SSI_MASK,
2752 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2753 OMAP3430_EN_SSI_SHIFT,
2754 NULL, ssi_ssr_fck_3430es1_parent_names,
2755 ssi_ssr_fck_3430es1_ops);
2756
2757DEFINE_CLK_FIXED_FACTOR(ssi_sst_fck_3430es1, "ssi_ssr_fck_3430es1",
2758 &ssi_ssr_fck_3430es1, 0x0, 1, 2);
2759
2760DEFINE_CLK_FIXED_FACTOR(ssi_sst_fck_3430es2, "ssi_ssr_fck_3430es2",
2761 &ssi_ssr_fck_3430es2, 0x0, 1, 2);
2762
2763static struct clk sys_clkout1;
2764
2765static const char *sys_clkout1_parent_names[] = {
2766 "osc_sys_ck",
2767};
2768
2769static struct clk_hw_omap sys_clkout1_hw = {
2770 .hw = {
2771 .clk = &sys_clkout1,
2772 },
2773 .enable_reg = OMAP3430_PRM_CLKOUT_CTRL,
2774 .enable_bit = OMAP3430_CLKOUT_EN_SHIFT,
2775};
2776
2777DEFINE_STRUCT_CLK(sys_clkout1, sys_clkout1_parent_names, aes1_ick_ops);
2778
2779DEFINE_CLK_DIVIDER(sys_clkout2, "clkout2_src_ck", &clkout2_src_ck, 0x0,
2780 OMAP3430_CM_CLKOUT_CTRL, OMAP3430_CLKOUT2_DIV_SHIFT,
2781 OMAP3430_CLKOUT2_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
2782
2783DEFINE_CLK_MUX(traceclk_src_fck, emu_src_ck_parent_names, NULL, 0x0,
2784 OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2785 OMAP3430_TRACE_MUX_CTRL_SHIFT, OMAP3430_TRACE_MUX_CTRL_WIDTH,
2786 0x0, NULL);
2787
2788DEFINE_CLK_DIVIDER(traceclk_fck, "traceclk_src_fck", &traceclk_src_fck, 0x0,
2789 OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2790 OMAP3430_CLKSEL_TRACECLK_SHIFT,
2791 OMAP3430_CLKSEL_TRACECLK_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
2792
2793static struct clk ts_fck;
2794
2795static struct clk_hw_omap ts_fck_hw = {
2796 .hw = {
2797 .clk = &ts_fck,
2798 },
2799 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
2800 .enable_bit = OMAP3430ES2_EN_TS_SHIFT,
2801 .clkdm_name = "core_l4_clkdm",
2802};
2803
2804DEFINE_STRUCT_CLK(ts_fck, wkup_32k_fck_parent_names, aes2_ick_ops);
2805
2806static struct clk uart1_fck;
2807
2808static struct clk_hw_omap uart1_fck_hw = {
2809 .hw = {
2810 .clk = &uart1_fck,
2811 },
2812 .ops = &clkhwops_wait,
2813 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2814 .enable_bit = OMAP3430_EN_UART1_SHIFT,
2815 .clkdm_name = "core_l4_clkdm",
2816};
2817
2818DEFINE_STRUCT_CLK(uart1_fck, fshostusb_fck_parent_names, aes2_ick_ops);
2819
2820static struct clk uart1_ick;
2821
2822static struct clk_hw_omap uart1_ick_hw = {
2823 .hw = {
2824 .clk = &uart1_ick,
2825 },
2826 .ops = &clkhwops_iclk_wait,
2827 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2828 .enable_bit = OMAP3430_EN_UART1_SHIFT,
2829 .clkdm_name = "core_l4_clkdm",
2830};
2831
2832DEFINE_STRUCT_CLK(uart1_ick, aes2_ick_parent_names, aes2_ick_ops);
2833
2834static struct clk uart2_fck;
2835
2836static struct clk_hw_omap uart2_fck_hw = {
2837 .hw = {
2838 .clk = &uart2_fck,
2839 },
2840 .ops = &clkhwops_wait,
2841 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2842 .enable_bit = OMAP3430_EN_UART2_SHIFT,
2843 .clkdm_name = "core_l4_clkdm",
2844};
2845
2846DEFINE_STRUCT_CLK(uart2_fck, fshostusb_fck_parent_names, aes2_ick_ops);
2847
2848static struct clk uart2_ick;
2849
2850static struct clk_hw_omap uart2_ick_hw = {
2851 .hw = {
2852 .clk = &uart2_ick,
2853 },
2854 .ops = &clkhwops_iclk_wait,
2855 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2856 .enable_bit = OMAP3430_EN_UART2_SHIFT,
2857 .clkdm_name = "core_l4_clkdm",
2858};
2859
2860DEFINE_STRUCT_CLK(uart2_ick, aes2_ick_parent_names, aes2_ick_ops);
2861
2862static struct clk uart3_fck;
2863
2864static const char *uart3_fck_parent_names[] = {
2865 "per_48m_fck",
2866};
2867
2868static struct clk_hw_omap uart3_fck_hw = {
2869 .hw = {
2870 .clk = &uart3_fck,
2871 },
2872 .ops = &clkhwops_wait,
2873 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2874 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2875 .clkdm_name = "per_clkdm",
2876};
2877
2878DEFINE_STRUCT_CLK(uart3_fck, uart3_fck_parent_names, aes2_ick_ops);
2879
2880static struct clk uart3_ick;
2881
2882static struct clk_hw_omap uart3_ick_hw = {
2883 .hw = {
2884 .clk = &uart3_ick,
2885 },
2886 .ops = &clkhwops_iclk_wait,
2887 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2888 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2889 .clkdm_name = "per_clkdm",
2890};
2891
2892DEFINE_STRUCT_CLK(uart3_ick, gpio2_ick_parent_names, aes2_ick_ops);
2893
2894static struct clk uart4_fck;
2895
2896static struct clk_hw_omap uart4_fck_hw = {
2897 .hw = {
2898 .clk = &uart4_fck,
2899 },
2900 .ops = &clkhwops_wait,
2901 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2902 .enable_bit = OMAP3630_EN_UART4_SHIFT,
2903 .clkdm_name = "per_clkdm",
2904};
2905
2906DEFINE_STRUCT_CLK(uart4_fck, uart3_fck_parent_names, aes2_ick_ops);
2907
2908static struct clk uart4_fck_am35xx;
2909
2910static struct clk_hw_omap uart4_fck_am35xx_hw = {
2911 .hw = {
2912 .clk = &uart4_fck_am35xx,
2913 },
2914 .ops = &clkhwops_wait,
2915 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2916 .enable_bit = AM35XX_EN_UART4_SHIFT,
2917 .clkdm_name = "core_l4_clkdm",
2918};
2919
2920DEFINE_STRUCT_CLK(uart4_fck_am35xx, fshostusb_fck_parent_names, aes2_ick_ops);
2921
2922static struct clk uart4_ick;
2923
2924static struct clk_hw_omap uart4_ick_hw = {
2925 .hw = {
2926 .clk = &uart4_ick,
2927 },
2928 .ops = &clkhwops_iclk_wait,
2929 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2930 .enable_bit = OMAP3630_EN_UART4_SHIFT,
2931 .clkdm_name = "per_clkdm",
2932};
2933
2934DEFINE_STRUCT_CLK(uart4_ick, gpio2_ick_parent_names, aes2_ick_ops);
2935
2936static struct clk uart4_ick_am35xx;
2937
2938static struct clk_hw_omap uart4_ick_am35xx_hw = {
2939 .hw = {
2940 .clk = &uart4_ick_am35xx,
2941 },
2942 .ops = &clkhwops_iclk_wait,
2943 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2944 .enable_bit = AM35XX_EN_UART4_SHIFT,
2945 .clkdm_name = "core_l4_clkdm",
2946};
2947
2948DEFINE_STRUCT_CLK(uart4_ick_am35xx, aes2_ick_parent_names, aes2_ick_ops);
2949
2950static const struct clksel_rate div2_rates[] = {
2951 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
2952 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
2953 { .div = 0 }
2954};
2955
2956static const struct clksel usb_l4_clksel[] = {
2957 { .parent = &l4_ick, .rates = div2_rates },
2958 { .parent = NULL },
2959};
2960
2961static const char *usb_l4_ick_parent_names[] = {
2962 "l4_ick",
2963};
2964
2965DEFINE_CLK_OMAP_MUX_GATE(usb_l4_ick, "core_l4_clkdm", usb_l4_clksel,
2966 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2967 OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
2968 OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2969 OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
2970 &clkhwops_iclk_wait, usb_l4_ick_parent_names,
2971 ssi_ssr_fck_3430es1_ops);
2972
2973static struct clk usbhost_120m_fck;
2974
2975static const char *usbhost_120m_fck_parent_names[] = {
2976 "dpll5_m2_ck",
2977};
2978
2979static struct clk_hw_omap usbhost_120m_fck_hw = {
2980 .hw = {
2981 .clk = &usbhost_120m_fck,
2982 },
2983 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2984 .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT,
2985 .clkdm_name = "usbhost_clkdm",
2986};
2987
2988DEFINE_STRUCT_CLK(usbhost_120m_fck, usbhost_120m_fck_parent_names,
2989 aes2_ick_ops);
2990
2991static struct clk usbhost_48m_fck;
2992
2993static struct clk_hw_omap usbhost_48m_fck_hw = {
2994 .hw = {
2995 .clk = &usbhost_48m_fck,
2996 },
2997 .ops = &clkhwops_omap3430es2_dss_usbhost_wait,
2998 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2999 .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
3000 .clkdm_name = "usbhost_clkdm",
3001};
3002
3003DEFINE_STRUCT_CLK(usbhost_48m_fck, core_48m_fck_parent_names, aes2_ick_ops);
3004
3005static struct clk usbhost_ick;
3006
3007static struct clk_hw_omap usbhost_ick_hw = {
3008 .hw = {
3009 .clk = &usbhost_ick,
3010 },
3011 .ops = &clkhwops_omap3430es2_iclk_dss_usbhost_wait,
3012 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
3013 .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT,
3014 .clkdm_name = "usbhost_clkdm",
3015};
3016
3017DEFINE_STRUCT_CLK(usbhost_ick, security_l4_ick2_parent_names, aes2_ick_ops);
3018
3019static struct clk usbtll_fck;
3020
3021static struct clk_hw_omap usbtll_fck_hw = {
3022 .hw = {
3023 .clk = &usbtll_fck,
3024 },
3025 .ops = &clkhwops_wait,
3026 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
3027 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
3028 .clkdm_name = "core_l4_clkdm",
3029};
3030
3031DEFINE_STRUCT_CLK(usbtll_fck, usbhost_120m_fck_parent_names, aes2_ick_ops);
3032
3033static struct clk usbtll_ick;
3034
3035static struct clk_hw_omap usbtll_ick_hw = {
3036 .hw = {
3037 .clk = &usbtll_ick,
3038 },
3039 .ops = &clkhwops_iclk_wait,
3040 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
3041 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
3042 .clkdm_name = "core_l4_clkdm",
3043};
3044
3045DEFINE_STRUCT_CLK(usbtll_ick, aes2_ick_parent_names, aes2_ick_ops);
3046
3047static const struct clksel_rate usim_96m_rates[] = {
3048 { .div = 2, .val = 3, .flags = RATE_IN_3XXX },
3049 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
3050 { .div = 8, .val = 5, .flags = RATE_IN_3XXX },
3051 { .div = 10, .val = 6, .flags = RATE_IN_3XXX },
3052 { .div = 0 }
3053};
3054
3055static const struct clksel_rate usim_120m_rates[] = {
3056 { .div = 4, .val = 7, .flags = RATE_IN_3XXX },
3057 { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
3058 { .div = 16, .val = 9, .flags = RATE_IN_3XXX },
3059 { .div = 20, .val = 10, .flags = RATE_IN_3XXX },
3060 { .div = 0 }
3061};
3062
3063static const struct clksel usim_clksel[] = {
3064 { .parent = &omap_96m_fck, .rates = usim_96m_rates },
3065 { .parent = &dpll5_m2_ck, .rates = usim_120m_rates },
3066 { .parent = &sys_ck, .rates = div2_rates },
3067 { .parent = NULL },
3068};
3069
3070static const char *usim_fck_parent_names[] = {
3071 "omap_96m_fck", "dpll5_m2_ck", "sys_ck",
3072};
3073
3074static struct clk usim_fck;
3075
3076static const struct clk_ops usim_fck_ops = {
3077 .enable = &omap2_dflt_clk_enable,
3078 .disable = &omap2_dflt_clk_disable,
3079 .is_enabled = &omap2_dflt_clk_is_enabled,
3080 .recalc_rate = &omap2_clksel_recalc,
3081 .get_parent = &omap2_clksel_find_parent_index,
3082 .set_parent = &omap2_clksel_set_parent,
3083};
3084
3085DEFINE_CLK_OMAP_MUX_GATE(usim_fck, NULL, usim_clksel,
3086 OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
3087 OMAP3430ES2_CLKSEL_USIMOCP_MASK,
3088 OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3089 OMAP3430ES2_EN_USIMOCP_SHIFT, &clkhwops_wait,
3090 usim_fck_parent_names, usim_fck_ops);
3091
3092static struct clk usim_ick;
3093
3094static struct clk_hw_omap usim_ick_hw = {
3095 .hw = {
3096 .clk = &usim_ick,
3097 },
3098 .ops = &clkhwops_iclk_wait,
3099 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
3100 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
3101 .clkdm_name = "wkup_clkdm",
3102};
3103
3104DEFINE_STRUCT_CLK(usim_ick, gpio1_ick_parent_names, aes2_ick_ops);
3105
3106static struct clk vpfe_fck;
3107
3108static const char *vpfe_fck_parent_names[] = {
3109 "pclk_ck",
3110};
3111
3112static struct clk_hw_omap vpfe_fck_hw = {
3113 .hw = {
3114 .clk = &vpfe_fck,
3115 },
3116 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3117 .enable_bit = AM35XX_VPFE_FCLK_SHIFT,
3118};
3119
3120DEFINE_STRUCT_CLK(vpfe_fck, vpfe_fck_parent_names, aes1_ick_ops);
3121
3122static struct clk vpfe_ick;
3123
3124static struct clk_hw_omap vpfe_ick_hw = {
3125 .hw = {
3126 .clk = &vpfe_ick,
3127 },
3128 .ops = &clkhwops_am35xx_ipss_module_wait,
3129 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3130 .enable_bit = AM35XX_VPFE_VBUSP_CLK_SHIFT,
3131 .clkdm_name = "core_l3_clkdm",
3132};
3133
3134DEFINE_STRUCT_CLK(vpfe_ick, emac_ick_parent_names, aes2_ick_ops);
3135
3136static struct clk wdt1_fck;
3137
3138DEFINE_STRUCT_CLK_HW_OMAP(wdt1_fck, "wkup_clkdm");
3139DEFINE_STRUCT_CLK(wdt1_fck, gpt12_fck_parent_names, core_l4_ick_ops);
3140
3141static struct clk wdt1_ick;
3142
3143static struct clk_hw_omap wdt1_ick_hw = {
3144 .hw = {
3145 .clk = &wdt1_ick,
3146 },
3147 .ops = &clkhwops_iclk_wait,
3148 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
3149 .enable_bit = OMAP3430_EN_WDT1_SHIFT,
3150 .clkdm_name = "wkup_clkdm",
3151};
3152
3153DEFINE_STRUCT_CLK(wdt1_ick, gpio1_ick_parent_names, aes2_ick_ops);
3154
3155static struct clk wdt2_fck;
3156
3157static struct clk_hw_omap wdt2_fck_hw = {
3158 .hw = {
3159 .clk = &wdt2_fck,
3160 },
3161 .ops = &clkhwops_wait,
3162 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3163 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
3164 .clkdm_name = "wkup_clkdm",
3165};
3166
3167DEFINE_STRUCT_CLK(wdt2_fck, gpio1_dbck_parent_names, aes2_ick_ops);
3168
3169static struct clk wdt2_ick;
3170
3171static struct clk_hw_omap wdt2_ick_hw = {
3172 .hw = {
3173 .clk = &wdt2_ick,
3174 },
3175 .ops = &clkhwops_iclk_wait,
3176 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
3177 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
3178 .clkdm_name = "wkup_clkdm",
3179};
3180
3181DEFINE_STRUCT_CLK(wdt2_ick, gpio1_ick_parent_names, aes2_ick_ops);
3182
3183static struct clk wdt3_fck;
3184
3185static struct clk_hw_omap wdt3_fck_hw = {
3186 .hw = {
3187 .clk = &wdt3_fck,
3188 },
3189 .ops = &clkhwops_wait,
3190 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
3191 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
3192 .clkdm_name = "per_clkdm",
3193};
3194
3195DEFINE_STRUCT_CLK(wdt3_fck, gpio2_dbck_parent_names, aes2_ick_ops);
3196
3197static struct clk wdt3_ick;
3198
3199static struct clk_hw_omap wdt3_ick_hw = {
3200 .hw = {
3201 .clk = &wdt3_ick,
3202 },
3203 .ops = &clkhwops_iclk_wait,
3204 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
3205 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
3206 .clkdm_name = "per_clkdm",
3207};
3208
3209DEFINE_STRUCT_CLK(wdt3_ick, gpio2_ick_parent_names, aes2_ick_ops);
3210
3211/*
3212 * clkdev
3213 */
3214static struct omap_clk omap3xxx_clks[] = {
3215 CLK(NULL, "apb_pclk", &dummy_apb_pclk, CK_3XXX),
3216 CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_3XXX),
3217 CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_3XXX),
3218 CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_3XXX),
3219 CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3220 CLK(NULL, "virt_19200000_ck", &virt_19200000_ck, CK_3XXX),
3221 CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_3XXX),
3222 CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck, CK_3XXX),
3223 CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_3XXX),
3224 CLK("twl", "fck", &osc_sys_ck, CK_3XXX),
3225 CLK(NULL, "sys_ck", &sys_ck, CK_3XXX),
3226 CLK(NULL, "sys_altclk", &sys_altclk, CK_3XXX),
3227 CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_3XXX),
3228 CLK(NULL, "sys_clkout1", &sys_clkout1, CK_3XXX),
3229 CLK(NULL, "dpll1_ck", &dpll1_ck, CK_3XXX),
3230 CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck, CK_3XXX),
3231 CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_3XXX),
3232 CLK(NULL, "dpll2_ck", &dpll2_ck, CK_34XX | CK_36XX),
3233 CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck, CK_34XX | CK_36XX),
3234 CLK(NULL, "dpll3_ck", &dpll3_ck, CK_3XXX),
3235 CLK(NULL, "core_ck", &core_ck, CK_3XXX),
3236 CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck, CK_3XXX),
3237 CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck, CK_3XXX),
3238 CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_3XXX),
3239 CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck, CK_3XXX),
3240 CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_3XXX),
3241 CLK("etb", "emu_core_alwon_ck", &emu_core_alwon_ck, CK_3XXX),
3242 CLK(NULL, "dpll4_ck", &dpll4_ck, CK_3XXX),
3243 CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck, CK_3XXX),
3244 CLK(NULL, "omap_192m_alwon_fck", &omap_192m_alwon_fck, CK_36XX),
3245 CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_3XXX),
3246 CLK(NULL, "omap_96m_fck", &omap_96m_fck, CK_3XXX),
3247 CLK(NULL, "cm_96m_fck", &cm_96m_fck, CK_3XXX),
3248 CLK(NULL, "omap_54m_fck", &omap_54m_fck, CK_3XXX),
3249 CLK(NULL, "omap_48m_fck", &omap_48m_fck, CK_3XXX),
3250 CLK(NULL, "omap_12m_fck", &omap_12m_fck, CK_3XXX),
3251 CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck, CK_3XXX),
3252 CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_3XXX),
3253 CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck, CK_3XXX),
3254 CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_3XXX),
3255 CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck, CK_3XXX),
3256 CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_3XXX),
3257 CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck, CK_3XXX),
3258 CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_3XXX),
3259 CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck, CK_3XXX),
3260 CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_3XXX),
3261 CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX),
3262 CLK(NULL, "dpll5_ck", &dpll5_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3263 CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3264 CLK(NULL, "clkout2_src_ck", &clkout2_src_ck, CK_3XXX),
3265 CLK(NULL, "sys_clkout2", &sys_clkout2, CK_3XXX),
3266 CLK(NULL, "corex2_fck", &corex2_fck, CK_3XXX),
3267 CLK(NULL, "dpll1_fck", &dpll1_fck, CK_3XXX),
3268 CLK(NULL, "mpu_ck", &mpu_ck, CK_3XXX),
3269 CLK(NULL, "arm_fck", &arm_fck, CK_3XXX),
3270 CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX),
3271 CLK(NULL, "dpll2_fck", &dpll2_fck, CK_34XX | CK_36XX),
3272 CLK(NULL, "iva2_ck", &iva2_ck, CK_34XX | CK_36XX),
3273 CLK(NULL, "l3_ick", &l3_ick, CK_3XXX),
3274 CLK(NULL, "l4_ick", &l4_ick, CK_3XXX),
3275 CLK(NULL, "rm_ick", &rm_ick, CK_3XXX),
3276 CLK(NULL, "gfx_l3_ck", &gfx_l3_ck, CK_3430ES1),
3277 CLK(NULL, "gfx_l3_fck", &gfx_l3_fck, CK_3430ES1),
3278 CLK(NULL, "gfx_l3_ick", &gfx_l3_ick, CK_3430ES1),
3279 CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck, CK_3430ES1),
3280 CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck, CK_3430ES1),
3281 CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3282 CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3283 CLK(NULL, "d2d_26m_fck", &d2d_26m_fck, CK_3430ES1),
3284 CLK(NULL, "modem_fck", &modem_fck, CK_34XX | CK_36XX),
3285 CLK(NULL, "sad2d_ick", &sad2d_ick, CK_34XX | CK_36XX),
3286 CLK(NULL, "mad2d_ick", &mad2d_ick, CK_34XX | CK_36XX),
3287 CLK(NULL, "gpt10_fck", &gpt10_fck, CK_3XXX),
3288 CLK(NULL, "gpt11_fck", &gpt11_fck, CK_3XXX),
3289 CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3290 CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3291 CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3292 CLK("usbhs_omap", "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3293 CLK("usbhs_tll", "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3294 CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX),
3295 CLK(NULL, "mmchs3_fck", &mmchs3_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3296 CLK(NULL, "mmchs2_fck", &mmchs2_fck, CK_3XXX),
3297 CLK(NULL, "mspro_fck", &mspro_fck, CK_34XX | CK_36XX),
3298 CLK(NULL, "mmchs1_fck", &mmchs1_fck, CK_3XXX),
3299 CLK(NULL, "i2c3_fck", &i2c3_fck, CK_3XXX),
3300 CLK(NULL, "i2c2_fck", &i2c2_fck, CK_3XXX),
3301 CLK(NULL, "i2c1_fck", &i2c1_fck, CK_3XXX),
3302 CLK(NULL, "mcbsp5_fck", &mcbsp5_fck, CK_3XXX),
3303 CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_3XXX),
3304 CLK(NULL, "core_48m_fck", &core_48m_fck, CK_3XXX),
3305 CLK(NULL, "mcspi4_fck", &mcspi4_fck, CK_3XXX),
3306 CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_3XXX),
3307 CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_3XXX),
3308 CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_3XXX),
3309 CLK(NULL, "uart2_fck", &uart2_fck, CK_3XXX),
3310 CLK(NULL, "uart1_fck", &uart1_fck, CK_3XXX),
3311 CLK(NULL, "fshostusb_fck", &fshostusb_fck, CK_3430ES1),
3312 CLK(NULL, "core_12m_fck", &core_12m_fck, CK_3XXX),
3313 CLK("omap_hdq.0", "fck", &hdq_fck, CK_3XXX),
3314 CLK(NULL, "hdq_fck", &hdq_fck, CK_3XXX),
3315 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1, CK_3430ES1),
3316 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2, CK_3430ES2PLUS | CK_36XX),
3317 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1, CK_3430ES1),
3318 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es2, CK_3430ES2PLUS | CK_36XX),
3319 CLK(NULL, "core_l3_ick", &core_l3_ick, CK_3XXX),
3320 CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es1, CK_3430ES1),
3321 CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es2, CK_3430ES2PLUS | CK_36XX),
3322 CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_3430es1, CK_3430ES1),
3323 CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_3430es2, CK_3430ES2PLUS | CK_36XX),
3324 CLK(NULL, "sdrc_ick", &sdrc_ick, CK_3XXX),
3325 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_3XXX),
3326 CLK(NULL, "security_l3_ick", &security_l3_ick, CK_34XX | CK_36XX),
3327 CLK(NULL, "pka_ick", &pka_ick, CK_34XX | CK_36XX),
3328 CLK(NULL, "core_l4_ick", &core_l4_ick, CK_3XXX),
3329 CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3330 CLK("usbhs_omap", "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3331 CLK("usbhs_tll", "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3332 CLK("omap_hsmmc.2", "ick", &mmchs3_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3333 CLK(NULL, "mmchs3_ick", &mmchs3_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3334 CLK(NULL, "icr_ick", &icr_ick, CK_34XX | CK_36XX),
3335 CLK("omap-aes", "ick", &aes2_ick, CK_34XX | CK_36XX),
3336 CLK("omap-sham", "ick", &sha12_ick, CK_34XX | CK_36XX),
3337 CLK(NULL, "des2_ick", &des2_ick, CK_34XX | CK_36XX),
3338 CLK("omap_hsmmc.1", "ick", &mmchs2_ick, CK_3XXX),
3339 CLK("omap_hsmmc.0", "ick", &mmchs1_ick, CK_3XXX),
3340 CLK(NULL, "mmchs2_ick", &mmchs2_ick, CK_3XXX),
3341 CLK(NULL, "mmchs1_ick", &mmchs1_ick, CK_3XXX),
3342 CLK(NULL, "mspro_ick", &mspro_ick, CK_34XX | CK_36XX),
3343 CLK("omap_hdq.0", "ick", &hdq_ick, CK_3XXX),
3344 CLK(NULL, "hdq_ick", &hdq_ick, CK_3XXX),
3345 CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_3XXX),
3346 CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_3XXX),
3347 CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_3XXX),
3348 CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_3XXX),
3349 CLK(NULL, "mcspi4_ick", &mcspi4_ick, CK_3XXX),
3350 CLK(NULL, "mcspi3_ick", &mcspi3_ick, CK_3XXX),
3351 CLK(NULL, "mcspi2_ick", &mcspi2_ick, CK_3XXX),
3352 CLK(NULL, "mcspi1_ick", &mcspi1_ick, CK_3XXX),
3353 CLK("omap_i2c.3", "ick", &i2c3_ick, CK_3XXX),
3354 CLK("omap_i2c.2", "ick", &i2c2_ick, CK_3XXX),
3355 CLK("omap_i2c.1", "ick", &i2c1_ick, CK_3XXX),
3356 CLK(NULL, "i2c3_ick", &i2c3_ick, CK_3XXX),
3357 CLK(NULL, "i2c2_ick", &i2c2_ick, CK_3XXX),
3358 CLK(NULL, "i2c1_ick", &i2c1_ick, CK_3XXX),
3359 CLK(NULL, "uart2_ick", &uart2_ick, CK_3XXX),
3360 CLK(NULL, "uart1_ick", &uart1_ick, CK_3XXX),
3361 CLK(NULL, "gpt11_ick", &gpt11_ick, CK_3XXX),
3362 CLK(NULL, "gpt10_ick", &gpt10_ick, CK_3XXX),
3363 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_3XXX),
3364 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_3XXX),
3365 CLK(NULL, "mcbsp5_ick", &mcbsp5_ick, CK_3XXX),
3366 CLK(NULL, "mcbsp1_ick", &mcbsp1_ick, CK_3XXX),
3367 CLK(NULL, "fac_ick", &fac_ick, CK_3430ES1),
3368 CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_34XX | CK_36XX),
3369 CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_3XXX),
3370 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_34XX | CK_36XX),
3371 CLK(NULL, "ssi_ick", &ssi_ick_3430es1, CK_3430ES1),
3372 CLK(NULL, "ssi_ick", &ssi_ick_3430es2, CK_3430ES2PLUS | CK_36XX),
3373 CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_3430ES1),
3374 CLK(NULL, "security_l4_ick2", &security_l4_ick2, CK_34XX | CK_36XX),
3375 CLK(NULL, "aes1_ick", &aes1_ick, CK_34XX | CK_36XX),
3376 CLK("omap_rng", "ick", &rng_ick, CK_34XX | CK_36XX),
3377 CLK(NULL, "sha11_ick", &sha11_ick, CK_34XX | CK_36XX),
3378 CLK(NULL, "des1_ick", &des1_ick, CK_34XX | CK_36XX),
3379 CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es1, CK_3430ES1),
3380 CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3381 CLK(NULL, "dss_tv_fck", &dss_tv_fck, CK_3XXX),
3382 CLK(NULL, "dss_96m_fck", &dss_96m_fck, CK_3XXX),
3383 CLK(NULL, "dss2_alwon_fck", &dss2_alwon_fck, CK_3XXX),
3384 CLK("omapdss_dss", "ick", &dss_ick_3430es1, CK_3430ES1),
3385 CLK(NULL, "dss_ick", &dss_ick_3430es1, CK_3430ES1),
3386 CLK("omapdss_dss", "ick", &dss_ick_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3387 CLK(NULL, "dss_ick", &dss_ick_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3388 CLK(NULL, "cam_mclk", &cam_mclk, CK_34XX | CK_36XX),
3389 CLK(NULL, "cam_ick", &cam_ick, CK_34XX | CK_36XX),
3390 CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_34XX | CK_36XX),
3391 CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3392 CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3393 CLK(NULL, "usbhost_ick", &usbhost_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3394 CLK("usbhs_omap", "usbhost_ick", &usbhost_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3395 CLK(NULL, "utmi_p1_gfclk", &dummy_ck, CK_3XXX),
3396 CLK(NULL, "utmi_p2_gfclk", &dummy_ck, CK_3XXX),
3397 CLK(NULL, "xclk60mhsp1_ck", &dummy_ck, CK_3XXX),
3398 CLK(NULL, "xclk60mhsp2_ck", &dummy_ck, CK_3XXX),
3399 CLK(NULL, "usb_host_hs_utmi_p1_clk", &dummy_ck, CK_3XXX),
3400 CLK(NULL, "usb_host_hs_utmi_p2_clk", &dummy_ck, CK_3XXX),
3401 CLK("usbhs_omap", "usb_tll_hs_usb_ch0_clk", &dummy_ck, CK_3XXX),
3402 CLK("usbhs_omap", "usb_tll_hs_usb_ch1_clk", &dummy_ck, CK_3XXX),
3403 CLK("usbhs_tll", "usb_tll_hs_usb_ch0_clk", &dummy_ck, CK_3XXX),
3404 CLK("usbhs_tll", "usb_tll_hs_usb_ch1_clk", &dummy_ck, CK_3XXX),
3405 CLK(NULL, "init_60m_fclk", &dummy_ck, CK_3XXX),
3406 CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2PLUS | CK_36XX),
3407 CLK(NULL, "gpt1_fck", &gpt1_fck, CK_3XXX),
3408 CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_3XXX),
3409 CLK(NULL, "gpio1_dbck", &gpio1_dbck, CK_3XXX),
3410 CLK(NULL, "wdt2_fck", &wdt2_fck, CK_3XXX),
3411 CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_34XX | CK_36XX),
3412 CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2PLUS | CK_36XX),
3413 CLK("omap_wdt", "ick", &wdt2_ick, CK_3XXX),
3414 CLK(NULL, "wdt2_ick", &wdt2_ick, CK_3XXX),
3415 CLK(NULL, "wdt1_ick", &wdt1_ick, CK_3XXX),
3416 CLK(NULL, "gpio1_ick", &gpio1_ick, CK_3XXX),
3417 CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX),
3418 CLK(NULL, "gpt12_ick", &gpt12_ick, CK_3XXX),
3419 CLK(NULL, "gpt1_ick", &gpt1_ick, CK_3XXX),
3420 CLK(NULL, "per_96m_fck", &per_96m_fck, CK_3XXX),
3421 CLK(NULL, "per_48m_fck", &per_48m_fck, CK_3XXX),
3422 CLK(NULL, "uart3_fck", &uart3_fck, CK_3XXX),
3423 CLK(NULL, "uart4_fck", &uart4_fck, CK_36XX),
3424 CLK(NULL, "uart4_fck", &uart4_fck_am35xx, CK_AM35XX),
3425 CLK(NULL, "gpt2_fck", &gpt2_fck, CK_3XXX),
3426 CLK(NULL, "gpt3_fck", &gpt3_fck, CK_3XXX),
3427 CLK(NULL, "gpt4_fck", &gpt4_fck, CK_3XXX),
3428 CLK(NULL, "gpt5_fck", &gpt5_fck, CK_3XXX),
3429 CLK(NULL, "gpt6_fck", &gpt6_fck, CK_3XXX),
3430 CLK(NULL, "gpt7_fck", &gpt7_fck, CK_3XXX),
3431 CLK(NULL, "gpt8_fck", &gpt8_fck, CK_3XXX),
3432 CLK(NULL, "gpt9_fck", &gpt9_fck, CK_3XXX),
3433 CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck, CK_3XXX),
3434 CLK(NULL, "gpio6_dbck", &gpio6_dbck, CK_3XXX),
3435 CLK(NULL, "gpio5_dbck", &gpio5_dbck, CK_3XXX),
3436 CLK(NULL, "gpio4_dbck", &gpio4_dbck, CK_3XXX),
3437 CLK(NULL, "gpio3_dbck", &gpio3_dbck, CK_3XXX),
3438 CLK(NULL, "gpio2_dbck", &gpio2_dbck, CK_3XXX),
3439 CLK(NULL, "wdt3_fck", &wdt3_fck, CK_3XXX),
3440 CLK(NULL, "per_l4_ick", &per_l4_ick, CK_3XXX),
3441 CLK(NULL, "gpio6_ick", &gpio6_ick, CK_3XXX),
3442 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_3XXX),
3443 CLK(NULL, "gpio4_ick", &gpio4_ick, CK_3XXX),
3444 CLK(NULL, "gpio3_ick", &gpio3_ick, CK_3XXX),
3445 CLK(NULL, "gpio2_ick", &gpio2_ick, CK_3XXX),
3446 CLK(NULL, "wdt3_ick", &wdt3_ick, CK_3XXX),
3447 CLK(NULL, "uart3_ick", &uart3_ick, CK_3XXX),
3448 CLK(NULL, "uart4_ick", &uart4_ick, CK_36XX),
3449 CLK(NULL, "gpt9_ick", &gpt9_ick, CK_3XXX),
3450 CLK(NULL, "gpt8_ick", &gpt8_ick, CK_3XXX),
3451 CLK(NULL, "gpt7_ick", &gpt7_ick, CK_3XXX),
3452 CLK(NULL, "gpt6_ick", &gpt6_ick, CK_3XXX),
3453 CLK(NULL, "gpt5_ick", &gpt5_ick, CK_3XXX),
3454 CLK(NULL, "gpt4_ick", &gpt4_ick, CK_3XXX),
3455 CLK(NULL, "gpt3_ick", &gpt3_ick, CK_3XXX),
3456 CLK(NULL, "gpt2_ick", &gpt2_ick, CK_3XXX),
3457 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_3XXX),
3458 CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_3XXX),
3459 CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_3XXX),
3460 CLK(NULL, "mcbsp4_ick", &mcbsp2_ick, CK_3XXX),
3461 CLK(NULL, "mcbsp3_ick", &mcbsp3_ick, CK_3XXX),
3462 CLK(NULL, "mcbsp2_ick", &mcbsp4_ick, CK_3XXX),
3463 CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_3XXX),
3464 CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_3XXX),
3465 CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_3XXX),
3466 CLK("etb", "emu_src_ck", &emu_src_ck, CK_3XXX),
3467 CLK(NULL, "emu_src_ck", &emu_src_ck, CK_3XXX),
3468 CLK(NULL, "pclk_fck", &pclk_fck, CK_3XXX),
3469 CLK(NULL, "pclkx2_fck", &pclkx2_fck, CK_3XXX),
3470 CLK(NULL, "atclk_fck", &atclk_fck, CK_3XXX),
3471 CLK(NULL, "traceclk_src_fck", &traceclk_src_fck, CK_3XXX),
3472 CLK(NULL, "traceclk_fck", &traceclk_fck, CK_3XXX),
3473 CLK(NULL, "sr1_fck", &sr1_fck, CK_34XX | CK_36XX),
3474 CLK(NULL, "sr2_fck", &sr2_fck, CK_34XX | CK_36XX),
3475 CLK(NULL, "sr_l4_ick", &sr_l4_ick, CK_34XX | CK_36XX),
3476 CLK(NULL, "secure_32k_fck", &secure_32k_fck, CK_3XXX),
3477 CLK(NULL, "gpt12_fck", &gpt12_fck, CK_3XXX),
3478 CLK(NULL, "wdt1_fck", &wdt1_fck, CK_3XXX),
3479 CLK(NULL, "ipss_ick", &ipss_ick, CK_AM35XX),
3480 CLK(NULL, "rmii_ck", &rmii_ck, CK_AM35XX),
3481 CLK(NULL, "pclk_ck", &pclk_ck, CK_AM35XX),
3482 CLK(NULL, "emac_ick", &emac_ick, CK_AM35XX),
3483 CLK(NULL, "emac_fck", &emac_fck, CK_AM35XX),
3484 CLK("davinci_emac.0", NULL, &emac_ick, CK_AM35XX),
3485 CLK("davinci_mdio.0", NULL, &emac_fck, CK_AM35XX),
3486 CLK("vpfe-capture", "master", &vpfe_ick, CK_AM35XX),
3487 CLK("vpfe-capture", "slave", &vpfe_fck, CK_AM35XX),
3488 CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_am35xx, CK_AM35XX),
3489 CLK(NULL, "hsotgusb_fck", &hsotgusb_fck_am35xx, CK_AM35XX),
3490 CLK(NULL, "hecc_ck", &hecc_ck, CK_AM35XX),
3491 CLK(NULL, "uart4_ick", &uart4_ick_am35xx, CK_AM35XX),
3492 CLK(NULL, "timer_32k_ck", &omap_32k_fck, CK_3XXX),
3493 CLK(NULL, "timer_sys_ck", &sys_ck, CK_3XXX),
3494 CLK(NULL, "cpufreq_ck", &dpll1_ck, CK_3XXX),
3495};
3496
3497static const char *enable_init_clks[] = {
3498 "sdrc_ick",
3499 "gpmc_fck",
3500 "omapctrl_ick",
3501};
3502
3503int __init omap3xxx_clk_init(void)
3504{
3505 struct omap_clk *c;
3506 u32 cpu_clkflg = 0;
3507
3508 /*
3509 * 3505 must be tested before 3517, since 3517 returns true
3510 * for both AM3517 chips and AM3517 family chips, which
3511 * includes 3505. Unfortunately there's no obvious family
3512 * test for 3517/3505 :-(
3513 */
3514 if (soc_is_am35xx()) {
3515 cpu_mask = RATE_IN_34XX;
3516 cpu_clkflg = CK_AM35XX;
3517 } else if (cpu_is_omap3630()) {
3518 cpu_mask = (RATE_IN_34XX | RATE_IN_36XX);
3519 cpu_clkflg = CK_36XX;
3520 } else if (cpu_is_ti816x()) {
3521 cpu_mask = RATE_IN_TI816X;
3522 cpu_clkflg = CK_TI816X;
3523 } else if (soc_is_am33xx()) {
3524 cpu_mask = RATE_IN_AM33XX;
3525 } else if (cpu_is_ti814x()) {
3526 cpu_mask = RATE_IN_TI814X;
3527 } else if (cpu_is_omap34xx()) {
3528 if (omap_rev() == OMAP3430_REV_ES1_0) {
3529 cpu_mask = RATE_IN_3430ES1;
3530 cpu_clkflg = CK_3430ES1;
3531 } else {
3532 /*
3533 * Assume that anything that we haven't matched yet
3534 * has 3430ES2-type clocks.
3535 */
3536 cpu_mask = RATE_IN_3430ES2PLUS;
3537 cpu_clkflg = CK_3430ES2PLUS;
3538 }
3539 } else {
3540 WARN(1, "clock: could not identify OMAP3 variant\n");
3541 }
3542
3543 if (omap3_has_192mhz_clk())
3544 omap_96m_alwon_fck = omap_96m_alwon_fck_3630;
3545
3546 if (cpu_is_omap3630()) {
3547 dpll3_m3x2_ck = dpll3_m3x2_ck_3630;
3548 dpll4_m2x2_ck = dpll4_m2x2_ck_3630;
3549 dpll4_m3x2_ck = dpll4_m3x2_ck_3630;
3550 dpll4_m4x2_ck = dpll4_m4x2_ck_3630;
3551 dpll4_m5x2_ck = dpll4_m5x2_ck_3630;
3552 dpll4_m6x2_ck = dpll4_m6x2_ck_3630;
3553 }
3554
3555 /*
3556 * XXX This type of dynamic rewriting of the clock tree is
3557 * deprecated and should be revised soon.
3558 */
3559 if (cpu_is_omap3630())
3560 dpll4_dd = dpll4_dd_3630;
3561 else
3562 dpll4_dd = dpll4_dd_34xx;
3563
3564 for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks);
3565 c++)
3566 if (c->cpu & cpu_clkflg) {
3567 clkdev_add(&c->lk);
3568 if (!__clk_init(NULL, c->lk.clk))
3569 omap2_init_clk_hw_omap_clocks(c->lk.clk);
3570 }
3571
3572 omap2_clk_disable_autoidle_all();
3573
3574 omap2_clk_enable_init_clocks(enable_init_clks,
3575 ARRAY_SIZE(enable_init_clks));
3576
3577 pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
3578 (clk_get_rate(&osc_sys_ck) / 1000000),
3579 (clk_get_rate(&osc_sys_ck) / 100000) % 10,
3580 (clk_get_rate(&core_ck) / 1000000),
3581 (clk_get_rate(&arm_fck) / 1000000));
3582
3583 /*
3584 * Lock DPLL5 -- here only until other device init code can
3585 * handle this
3586 */
3587 if (!cpu_is_ti81xx() && (omap_rev() >= OMAP3430_REV_ES2_0))
3588 omap3_clk_lock_dpll5();
3589
3590 /* Avoid sleeping during omap3_core_dpll_m2_set_rate() */
3591 sdrc_ick_p = clk_get(NULL, "sdrc_ick");
3592 arm_fck_p = clk_get(NULL, "arm_fck");
3593
3594 return 0;
3595}
diff --git a/arch/arm/mach-omap2/cclock44xx_data.c b/arch/arm/mach-omap2/cclock44xx_data.c
new file mode 100644
index 000000000000..aa56c3e5bb34
--- /dev/null
+++ b/arch/arm/mach-omap2/cclock44xx_data.c
@@ -0,0 +1,1987 @@
1/*
2 * OMAP4 Clock data
3 *
4 * Copyright (C) 2009-2012 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation
6 *
7 * Paul Walmsley (paul@pwsan.com)
8 * Rajendra Nayak (rnayak@ti.com)
9 * Benoit Cousson (b-cousson@ti.com)
10 * Mike Turquette (mturquette@ti.com)
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 *
16 * XXX Some of the ES1 clocks have been removed/changed; once support
17 * is added for discriminating clocks by ES level, these should be added back
18 * in.
19 */
20
21#include <linux/kernel.h>
22#include <linux/list.h>
23#include <linux/clk-private.h>
24#include <linux/clkdev.h>
25#include <linux/io.h>
26
27#include "soc.h"
28#include "iomap.h"
29#include "clock.h"
30#include "clock44xx.h"
31#include "cm1_44xx.h"
32#include "cm2_44xx.h"
33#include "cm-regbits-44xx.h"
34#include "prm44xx.h"
35#include "prm-regbits-44xx.h"
36#include "control.h"
37#include "scrm44xx.h"
38
39/* OMAP4 modulemode control */
40#define OMAP4430_MODULEMODE_HWCTRL_SHIFT 0
41#define OMAP4430_MODULEMODE_SWCTRL_SHIFT 1
42
43/* Root clocks */
44
45DEFINE_CLK_FIXED_RATE(extalt_clkin_ck, CLK_IS_ROOT, 59000000, 0x0);
46
47DEFINE_CLK_FIXED_RATE(pad_clks_src_ck, CLK_IS_ROOT, 12000000, 0x0);
48
49DEFINE_CLK_GATE(pad_clks_ck, "pad_clks_src_ck", &pad_clks_src_ck, 0x0,
50 OMAP4430_CM_CLKSEL_ABE, OMAP4430_PAD_CLKS_GATE_SHIFT,
51 0x0, NULL);
52
53DEFINE_CLK_FIXED_RATE(pad_slimbus_core_clks_ck, CLK_IS_ROOT, 12000000, 0x0);
54
55DEFINE_CLK_FIXED_RATE(secure_32k_clk_src_ck, CLK_IS_ROOT, 32768, 0x0);
56
57DEFINE_CLK_FIXED_RATE(slimbus_src_clk, CLK_IS_ROOT, 12000000, 0x0);
58
59DEFINE_CLK_GATE(slimbus_clk, "slimbus_src_clk", &slimbus_src_clk, 0x0,
60 OMAP4430_CM_CLKSEL_ABE, OMAP4430_SLIMBUS_CLK_GATE_SHIFT,
61 0x0, NULL);
62
63DEFINE_CLK_FIXED_RATE(sys_32k_ck, CLK_IS_ROOT, 32768, 0x0);
64
65DEFINE_CLK_FIXED_RATE(virt_12000000_ck, CLK_IS_ROOT, 12000000, 0x0);
66
67DEFINE_CLK_FIXED_RATE(virt_13000000_ck, CLK_IS_ROOT, 13000000, 0x0);
68
69DEFINE_CLK_FIXED_RATE(virt_16800000_ck, CLK_IS_ROOT, 16800000, 0x0);
70
71DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0);
72
73DEFINE_CLK_FIXED_RATE(virt_26000000_ck, CLK_IS_ROOT, 26000000, 0x0);
74
75DEFINE_CLK_FIXED_RATE(virt_27000000_ck, CLK_IS_ROOT, 27000000, 0x0);
76
77DEFINE_CLK_FIXED_RATE(virt_38400000_ck, CLK_IS_ROOT, 38400000, 0x0);
78
79static const char *sys_clkin_ck_parents[] = {
80 "virt_12000000_ck", "virt_13000000_ck", "virt_16800000_ck",
81 "virt_19200000_ck", "virt_26000000_ck", "virt_27000000_ck",
82 "virt_38400000_ck",
83};
84
85DEFINE_CLK_MUX(sys_clkin_ck, sys_clkin_ck_parents, NULL, 0x0,
86 OMAP4430_CM_SYS_CLKSEL, OMAP4430_SYS_CLKSEL_SHIFT,
87 OMAP4430_SYS_CLKSEL_WIDTH, CLK_MUX_INDEX_ONE, NULL);
88
89DEFINE_CLK_FIXED_RATE(tie_low_clock_ck, CLK_IS_ROOT, 0, 0x0);
90
91DEFINE_CLK_FIXED_RATE(utmi_phy_clkout_ck, CLK_IS_ROOT, 60000000, 0x0);
92
93DEFINE_CLK_FIXED_RATE(xclk60mhsp1_ck, CLK_IS_ROOT, 60000000, 0x0);
94
95DEFINE_CLK_FIXED_RATE(xclk60mhsp2_ck, CLK_IS_ROOT, 60000000, 0x0);
96
97DEFINE_CLK_FIXED_RATE(xclk60motg_ck, CLK_IS_ROOT, 60000000, 0x0);
98
99/* Module clocks and DPLL outputs */
100
101static const char *abe_dpll_bypass_clk_mux_ck_parents[] = {
102 "sys_clkin_ck", "sys_32k_ck",
103};
104
105DEFINE_CLK_MUX(abe_dpll_bypass_clk_mux_ck, abe_dpll_bypass_clk_mux_ck_parents,
106 NULL, 0x0, OMAP4430_CM_L4_WKUP_CLKSEL, OMAP4430_CLKSEL_SHIFT,
107 OMAP4430_CLKSEL_WIDTH, 0x0, NULL);
108
109DEFINE_CLK_MUX(abe_dpll_refclk_mux_ck, abe_dpll_bypass_clk_mux_ck_parents, NULL,
110 0x0, OMAP4430_CM_ABE_PLL_REF_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT,
111 OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL);
112
113/* DPLL_ABE */
114static struct dpll_data dpll_abe_dd = {
115 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_ABE,
116 .clk_bypass = &abe_dpll_bypass_clk_mux_ck,
117 .clk_ref = &abe_dpll_refclk_mux_ck,
118 .control_reg = OMAP4430_CM_CLKMODE_DPLL_ABE,
119 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
120 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_ABE,
121 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_ABE,
122 .mult_mask = OMAP4430_DPLL_MULT_MASK,
123 .div1_mask = OMAP4430_DPLL_DIV_MASK,
124 .enable_mask = OMAP4430_DPLL_EN_MASK,
125 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
126 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
127 .max_multiplier = 2047,
128 .max_divider = 128,
129 .min_divider = 1,
130};
131
132
133static const char *dpll_abe_ck_parents[] = {
134 "abe_dpll_refclk_mux_ck",
135};
136
137static struct clk dpll_abe_ck;
138
139static const struct clk_ops dpll_abe_ck_ops = {
140 .enable = &omap3_noncore_dpll_enable,
141 .disable = &omap3_noncore_dpll_disable,
142 .recalc_rate = &omap4_dpll_regm4xen_recalc,
143 .round_rate = &omap4_dpll_regm4xen_round_rate,
144 .set_rate = &omap3_noncore_dpll_set_rate,
145 .get_parent = &omap2_init_dpll_parent,
146};
147
148static struct clk_hw_omap dpll_abe_ck_hw = {
149 .hw = {
150 .clk = &dpll_abe_ck,
151 },
152 .dpll_data = &dpll_abe_dd,
153 .ops = &clkhwops_omap3_dpll,
154};
155
156DEFINE_STRUCT_CLK(dpll_abe_ck, dpll_abe_ck_parents, dpll_abe_ck_ops);
157
158static const char *dpll_abe_x2_ck_parents[] = {
159 "dpll_abe_ck",
160};
161
162static struct clk dpll_abe_x2_ck;
163
164static const struct clk_ops dpll_abe_x2_ck_ops = {
165 .recalc_rate = &omap3_clkoutx2_recalc,
166};
167
168static struct clk_hw_omap dpll_abe_x2_ck_hw = {
169 .hw = {
170 .clk = &dpll_abe_x2_ck,
171 },
172 .flags = CLOCK_CLKOUTX2,
173 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE,
174 .ops = &clkhwops_omap4_dpllmx,
175};
176
177DEFINE_STRUCT_CLK(dpll_abe_x2_ck, dpll_abe_x2_ck_parents, dpll_abe_x2_ck_ops);
178
179static const struct clk_ops omap_hsdivider_ops = {
180 .set_rate = &omap2_clksel_set_rate,
181 .recalc_rate = &omap2_clksel_recalc,
182 .round_rate = &omap2_clksel_round_rate,
183};
184
185DEFINE_CLK_OMAP_HSDIVIDER(dpll_abe_m2x2_ck, "dpll_abe_x2_ck", &dpll_abe_x2_ck,
186 0x0, OMAP4430_CM_DIV_M2_DPLL_ABE,
187 OMAP4430_DPLL_CLKOUT_DIV_MASK);
188
189DEFINE_CLK_FIXED_FACTOR(abe_24m_fclk, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck,
190 0x0, 1, 8);
191
192DEFINE_CLK_DIVIDER(abe_clk, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, 0x0,
193 OMAP4430_CM_CLKSEL_ABE, OMAP4430_CLKSEL_OPP_SHIFT,
194 OMAP4430_CLKSEL_OPP_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
195
196DEFINE_CLK_DIVIDER(aess_fclk, "abe_clk", &abe_clk, 0x0,
197 OMAP4430_CM1_ABE_AESS_CLKCTRL,
198 OMAP4430_CLKSEL_AESS_FCLK_SHIFT,
199 OMAP4430_CLKSEL_AESS_FCLK_WIDTH,
200 0x0, NULL);
201
202DEFINE_CLK_OMAP_HSDIVIDER(dpll_abe_m3x2_ck, "dpll_abe_x2_ck", &dpll_abe_x2_ck,
203 0x0, OMAP4430_CM_DIV_M3_DPLL_ABE,
204 OMAP4430_DPLL_CLKOUTHIF_DIV_MASK);
205
206static const char *core_hsd_byp_clk_mux_ck_parents[] = {
207 "sys_clkin_ck", "dpll_abe_m3x2_ck",
208};
209
210DEFINE_CLK_MUX(core_hsd_byp_clk_mux_ck, core_hsd_byp_clk_mux_ck_parents, NULL,
211 0x0, OMAP4430_CM_CLKSEL_DPLL_CORE,
212 OMAP4430_DPLL_BYP_CLKSEL_SHIFT, OMAP4430_DPLL_BYP_CLKSEL_WIDTH,
213 0x0, NULL);
214
215/* DPLL_CORE */
216static struct dpll_data dpll_core_dd = {
217 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_CORE,
218 .clk_bypass = &core_hsd_byp_clk_mux_ck,
219 .clk_ref = &sys_clkin_ck,
220 .control_reg = OMAP4430_CM_CLKMODE_DPLL_CORE,
221 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
222 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_CORE,
223 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_CORE,
224 .mult_mask = OMAP4430_DPLL_MULT_MASK,
225 .div1_mask = OMAP4430_DPLL_DIV_MASK,
226 .enable_mask = OMAP4430_DPLL_EN_MASK,
227 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
228 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
229 .max_multiplier = 2047,
230 .max_divider = 128,
231 .min_divider = 1,
232};
233
234
235static const char *dpll_core_ck_parents[] = {
236 "sys_clkin_ck",
237};
238
239static struct clk dpll_core_ck;
240
241static const struct clk_ops dpll_core_ck_ops = {
242 .recalc_rate = &omap3_dpll_recalc,
243 .get_parent = &omap2_init_dpll_parent,
244};
245
246static struct clk_hw_omap dpll_core_ck_hw = {
247 .hw = {
248 .clk = &dpll_core_ck,
249 },
250 .dpll_data = &dpll_core_dd,
251 .ops = &clkhwops_omap3_dpll,
252};
253
254DEFINE_STRUCT_CLK(dpll_core_ck, dpll_core_ck_parents, dpll_core_ck_ops);
255
256static const char *dpll_core_x2_ck_parents[] = {
257 "dpll_core_ck",
258};
259
260static struct clk dpll_core_x2_ck;
261
262static struct clk_hw_omap dpll_core_x2_ck_hw = {
263 .hw = {
264 .clk = &dpll_core_x2_ck,
265 },
266};
267
268DEFINE_STRUCT_CLK(dpll_core_x2_ck, dpll_core_x2_ck_parents, dpll_abe_x2_ck_ops);
269
270DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m6x2_ck, "dpll_core_x2_ck",
271 &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M6_DPLL_CORE,
272 OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK);
273
274DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m2_ck, "dpll_core_ck", &dpll_core_ck, 0x0,
275 OMAP4430_CM_DIV_M2_DPLL_CORE,
276 OMAP4430_DPLL_CLKOUT_DIV_MASK);
277
278DEFINE_CLK_FIXED_FACTOR(ddrphy_ck, "dpll_core_m2_ck", &dpll_core_m2_ck, 0x0, 1,
279 2);
280
281DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m5x2_ck, "dpll_core_x2_ck",
282 &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M5_DPLL_CORE,
283 OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK);
284
285DEFINE_CLK_DIVIDER(div_core_ck, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, 0x0,
286 OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_CORE_SHIFT,
287 OMAP4430_CLKSEL_CORE_WIDTH, 0x0, NULL);
288
289DEFINE_CLK_OMAP_HSDIVIDER(div_iva_hs_clk, "dpll_core_m5x2_ck",
290 &dpll_core_m5x2_ck, 0x0, OMAP4430_CM_BYPCLK_DPLL_IVA,
291 OMAP4430_CLKSEL_0_1_MASK);
292
293DEFINE_CLK_DIVIDER(div_mpu_hs_clk, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck,
294 0x0, OMAP4430_CM_BYPCLK_DPLL_MPU, OMAP4430_CLKSEL_0_1_SHIFT,
295 OMAP4430_CLKSEL_0_1_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
296
297DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m4x2_ck, "dpll_core_x2_ck",
298 &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M4_DPLL_CORE,
299 OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK);
300
301DEFINE_CLK_FIXED_FACTOR(dll_clk_div_ck, "dpll_core_m4x2_ck", &dpll_core_m4x2_ck,
302 0x0, 1, 2);
303
304DEFINE_CLK_DIVIDER(dpll_abe_m2_ck, "dpll_abe_ck", &dpll_abe_ck, 0x0,
305 OMAP4430_CM_DIV_M2_DPLL_ABE, OMAP4430_DPLL_CLKOUT_DIV_SHIFT,
306 OMAP4430_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
307
308static const struct clk_ops dmic_fck_ops = {
309 .enable = &omap2_dflt_clk_enable,
310 .disable = &omap2_dflt_clk_disable,
311 .is_enabled = &omap2_dflt_clk_is_enabled,
312 .recalc_rate = &omap2_clksel_recalc,
313 .get_parent = &omap2_clksel_find_parent_index,
314 .set_parent = &omap2_clksel_set_parent,
315 .init = &omap2_init_clk_clkdm,
316};
317
318static const char *dpll_core_m3x2_ck_parents[] = {
319 "dpll_core_x2_ck",
320};
321
322static const struct clksel dpll_core_m3x2_div[] = {
323 { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
324 { .parent = NULL },
325};
326
327/* XXX Missing round_rate, set_rate in ops */
328DEFINE_CLK_OMAP_MUX_GATE(dpll_core_m3x2_ck, NULL, dpll_core_m3x2_div,
329 OMAP4430_CM_DIV_M3_DPLL_CORE,
330 OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
331 OMAP4430_CM_DIV_M3_DPLL_CORE,
332 OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, NULL,
333 dpll_core_m3x2_ck_parents, dmic_fck_ops);
334
335DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m7x2_ck, "dpll_core_x2_ck",
336 &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M7_DPLL_CORE,
337 OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK);
338
339static const char *iva_hsd_byp_clk_mux_ck_parents[] = {
340 "sys_clkin_ck", "div_iva_hs_clk",
341};
342
343DEFINE_CLK_MUX(iva_hsd_byp_clk_mux_ck, iva_hsd_byp_clk_mux_ck_parents, NULL,
344 0x0, OMAP4430_CM_CLKSEL_DPLL_IVA, OMAP4430_DPLL_BYP_CLKSEL_SHIFT,
345 OMAP4430_DPLL_BYP_CLKSEL_WIDTH, 0x0, NULL);
346
347/* DPLL_IVA */
348static struct dpll_data dpll_iva_dd = {
349 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_IVA,
350 .clk_bypass = &iva_hsd_byp_clk_mux_ck,
351 .clk_ref = &sys_clkin_ck,
352 .control_reg = OMAP4430_CM_CLKMODE_DPLL_IVA,
353 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
354 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_IVA,
355 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_IVA,
356 .mult_mask = OMAP4430_DPLL_MULT_MASK,
357 .div1_mask = OMAP4430_DPLL_DIV_MASK,
358 .enable_mask = OMAP4430_DPLL_EN_MASK,
359 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
360 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
361 .max_multiplier = 2047,
362 .max_divider = 128,
363 .min_divider = 1,
364};
365
366static struct clk dpll_iva_ck;
367
368static struct clk_hw_omap dpll_iva_ck_hw = {
369 .hw = {
370 .clk = &dpll_iva_ck,
371 },
372 .dpll_data = &dpll_iva_dd,
373 .ops = &clkhwops_omap3_dpll,
374};
375
376DEFINE_STRUCT_CLK(dpll_iva_ck, dpll_core_ck_parents, dpll_abe_ck_ops);
377
378static const char *dpll_iva_x2_ck_parents[] = {
379 "dpll_iva_ck",
380};
381
382static struct clk dpll_iva_x2_ck;
383
384static struct clk_hw_omap dpll_iva_x2_ck_hw = {
385 .hw = {
386 .clk = &dpll_iva_x2_ck,
387 },
388};
389
390DEFINE_STRUCT_CLK(dpll_iva_x2_ck, dpll_iva_x2_ck_parents, dpll_abe_x2_ck_ops);
391
392DEFINE_CLK_OMAP_HSDIVIDER(dpll_iva_m4x2_ck, "dpll_iva_x2_ck", &dpll_iva_x2_ck,
393 0x0, OMAP4430_CM_DIV_M4_DPLL_IVA,
394 OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK);
395
396DEFINE_CLK_OMAP_HSDIVIDER(dpll_iva_m5x2_ck, "dpll_iva_x2_ck", &dpll_iva_x2_ck,
397 0x0, OMAP4430_CM_DIV_M5_DPLL_IVA,
398 OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK);
399
400/* DPLL_MPU */
401static struct dpll_data dpll_mpu_dd = {
402 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_MPU,
403 .clk_bypass = &div_mpu_hs_clk,
404 .clk_ref = &sys_clkin_ck,
405 .control_reg = OMAP4430_CM_CLKMODE_DPLL_MPU,
406 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
407 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_MPU,
408 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_MPU,
409 .mult_mask = OMAP4430_DPLL_MULT_MASK,
410 .div1_mask = OMAP4430_DPLL_DIV_MASK,
411 .enable_mask = OMAP4430_DPLL_EN_MASK,
412 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
413 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
414 .max_multiplier = 2047,
415 .max_divider = 128,
416 .min_divider = 1,
417};
418
419static struct clk dpll_mpu_ck;
420
421static struct clk_hw_omap dpll_mpu_ck_hw = {
422 .hw = {
423 .clk = &dpll_mpu_ck,
424 },
425 .dpll_data = &dpll_mpu_dd,
426 .ops = &clkhwops_omap3_dpll,
427};
428
429DEFINE_STRUCT_CLK(dpll_mpu_ck, dpll_core_ck_parents, dpll_abe_ck_ops);
430
431DEFINE_CLK_FIXED_FACTOR(mpu_periphclk, "dpll_mpu_ck", &dpll_mpu_ck, 0x0, 1, 2);
432
433DEFINE_CLK_OMAP_HSDIVIDER(dpll_mpu_m2_ck, "dpll_mpu_ck", &dpll_mpu_ck, 0x0,
434 OMAP4430_CM_DIV_M2_DPLL_MPU,
435 OMAP4430_DPLL_CLKOUT_DIV_MASK);
436
437DEFINE_CLK_FIXED_FACTOR(per_hs_clk_div_ck, "dpll_abe_m3x2_ck",
438 &dpll_abe_m3x2_ck, 0x0, 1, 2);
439
440static const char *per_hsd_byp_clk_mux_ck_parents[] = {
441 "sys_clkin_ck", "per_hs_clk_div_ck",
442};
443
444DEFINE_CLK_MUX(per_hsd_byp_clk_mux_ck, per_hsd_byp_clk_mux_ck_parents, NULL,
445 0x0, OMAP4430_CM_CLKSEL_DPLL_PER, OMAP4430_DPLL_BYP_CLKSEL_SHIFT,
446 OMAP4430_DPLL_BYP_CLKSEL_WIDTH, 0x0, NULL);
447
448/* DPLL_PER */
449static struct dpll_data dpll_per_dd = {
450 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_PER,
451 .clk_bypass = &per_hsd_byp_clk_mux_ck,
452 .clk_ref = &sys_clkin_ck,
453 .control_reg = OMAP4430_CM_CLKMODE_DPLL_PER,
454 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
455 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_PER,
456 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_PER,
457 .mult_mask = OMAP4430_DPLL_MULT_MASK,
458 .div1_mask = OMAP4430_DPLL_DIV_MASK,
459 .enable_mask = OMAP4430_DPLL_EN_MASK,
460 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
461 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
462 .max_multiplier = 2047,
463 .max_divider = 128,
464 .min_divider = 1,
465};
466
467
468static struct clk dpll_per_ck;
469
470static struct clk_hw_omap dpll_per_ck_hw = {
471 .hw = {
472 .clk = &dpll_per_ck,
473 },
474 .dpll_data = &dpll_per_dd,
475 .ops = &clkhwops_omap3_dpll,
476};
477
478DEFINE_STRUCT_CLK(dpll_per_ck, dpll_core_ck_parents, dpll_abe_ck_ops);
479
480DEFINE_CLK_DIVIDER(dpll_per_m2_ck, "dpll_per_ck", &dpll_per_ck, 0x0,
481 OMAP4430_CM_DIV_M2_DPLL_PER, OMAP4430_DPLL_CLKOUT_DIV_SHIFT,
482 OMAP4430_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
483
484static const char *dpll_per_x2_ck_parents[] = {
485 "dpll_per_ck",
486};
487
488static struct clk dpll_per_x2_ck;
489
490static struct clk_hw_omap dpll_per_x2_ck_hw = {
491 .hw = {
492 .clk = &dpll_per_x2_ck,
493 },
494 .flags = CLOCK_CLKOUTX2,
495 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER,
496 .ops = &clkhwops_omap4_dpllmx,
497};
498
499DEFINE_STRUCT_CLK(dpll_per_x2_ck, dpll_per_x2_ck_parents, dpll_abe_x2_ck_ops);
500
501DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m2x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
502 0x0, OMAP4430_CM_DIV_M2_DPLL_PER,
503 OMAP4430_DPLL_CLKOUT_DIV_MASK);
504
505static const char *dpll_per_m3x2_ck_parents[] = {
506 "dpll_per_x2_ck",
507};
508
509static const struct clksel dpll_per_m3x2_div[] = {
510 { .parent = &dpll_per_x2_ck, .rates = div31_1to31_rates },
511 { .parent = NULL },
512};
513
514/* XXX Missing round_rate, set_rate in ops */
515DEFINE_CLK_OMAP_MUX_GATE(dpll_per_m3x2_ck, NULL, dpll_per_m3x2_div,
516 OMAP4430_CM_DIV_M3_DPLL_PER,
517 OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
518 OMAP4430_CM_DIV_M3_DPLL_PER,
519 OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, NULL,
520 dpll_per_m3x2_ck_parents, dmic_fck_ops);
521
522DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m4x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
523 0x0, OMAP4430_CM_DIV_M4_DPLL_PER,
524 OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK);
525
526DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m5x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
527 0x0, OMAP4430_CM_DIV_M5_DPLL_PER,
528 OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK);
529
530DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m6x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
531 0x0, OMAP4430_CM_DIV_M6_DPLL_PER,
532 OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK);
533
534DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m7x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
535 0x0, OMAP4430_CM_DIV_M7_DPLL_PER,
536 OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK);
537
538DEFINE_CLK_FIXED_FACTOR(usb_hs_clk_div_ck, "dpll_abe_m3x2_ck",
539 &dpll_abe_m3x2_ck, 0x0, 1, 3);
540
541/* DPLL_USB */
542static struct dpll_data dpll_usb_dd = {
543 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_USB,
544 .clk_bypass = &usb_hs_clk_div_ck,
545 .flags = DPLL_J_TYPE,
546 .clk_ref = &sys_clkin_ck,
547 .control_reg = OMAP4430_CM_CLKMODE_DPLL_USB,
548 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
549 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_USB,
550 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_USB,
551 .mult_mask = OMAP4430_DPLL_MULT_USB_MASK,
552 .div1_mask = OMAP4430_DPLL_DIV_0_7_MASK,
553 .enable_mask = OMAP4430_DPLL_EN_MASK,
554 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
555 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
556 .sddiv_mask = OMAP4430_DPLL_SD_DIV_MASK,
557 .max_multiplier = 4095,
558 .max_divider = 256,
559 .min_divider = 1,
560};
561
562static struct clk dpll_usb_ck;
563
564static struct clk_hw_omap dpll_usb_ck_hw = {
565 .hw = {
566 .clk = &dpll_usb_ck,
567 },
568 .dpll_data = &dpll_usb_dd,
569 .ops = &clkhwops_omap3_dpll,
570};
571
572DEFINE_STRUCT_CLK(dpll_usb_ck, dpll_core_ck_parents, dpll_abe_ck_ops);
573
574static const char *dpll_usb_clkdcoldo_ck_parents[] = {
575 "dpll_usb_ck",
576};
577
578static struct clk dpll_usb_clkdcoldo_ck;
579
580static const struct clk_ops dpll_usb_clkdcoldo_ck_ops = {
581};
582
583static struct clk_hw_omap dpll_usb_clkdcoldo_ck_hw = {
584 .hw = {
585 .clk = &dpll_usb_clkdcoldo_ck,
586 },
587 .clksel_reg = OMAP4430_CM_CLKDCOLDO_DPLL_USB,
588 .ops = &clkhwops_omap4_dpllmx,
589};
590
591DEFINE_STRUCT_CLK(dpll_usb_clkdcoldo_ck, dpll_usb_clkdcoldo_ck_parents,
592 dpll_usb_clkdcoldo_ck_ops);
593
594DEFINE_CLK_OMAP_HSDIVIDER(dpll_usb_m2_ck, "dpll_usb_ck", &dpll_usb_ck, 0x0,
595 OMAP4430_CM_DIV_M2_DPLL_USB,
596 OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK);
597
598static const char *ducati_clk_mux_ck_parents[] = {
599 "div_core_ck", "dpll_per_m6x2_ck",
600};
601
602DEFINE_CLK_MUX(ducati_clk_mux_ck, ducati_clk_mux_ck_parents, NULL, 0x0,
603 OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT, OMAP4430_CLKSEL_0_0_SHIFT,
604 OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL);
605
606DEFINE_CLK_FIXED_FACTOR(func_12m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
607 0x0, 1, 16);
608
609DEFINE_CLK_FIXED_FACTOR(func_24m_clk, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0,
610 1, 4);
611
612DEFINE_CLK_FIXED_FACTOR(func_24mc_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
613 0x0, 1, 8);
614
615static const struct clk_div_table func_48m_fclk_rates[] = {
616 { .div = 4, .val = 0 },
617 { .div = 8, .val = 1 },
618 { .div = 0 },
619};
620DEFINE_CLK_DIVIDER_TABLE(func_48m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
621 0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT,
622 OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_48m_fclk_rates,
623 NULL);
624
625DEFINE_CLK_FIXED_FACTOR(func_48mc_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
626 0x0, 1, 4);
627
628static const struct clk_div_table func_64m_fclk_rates[] = {
629 { .div = 2, .val = 0 },
630 { .div = 4, .val = 1 },
631 { .div = 0 },
632};
633DEFINE_CLK_DIVIDER_TABLE(func_64m_fclk, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck,
634 0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT,
635 OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_64m_fclk_rates,
636 NULL);
637
638static const struct clk_div_table func_96m_fclk_rates[] = {
639 { .div = 2, .val = 0 },
640 { .div = 4, .val = 1 },
641 { .div = 0 },
642};
643DEFINE_CLK_DIVIDER_TABLE(func_96m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
644 0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT,
645 OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_96m_fclk_rates,
646 NULL);
647
648static const struct clk_div_table init_60m_fclk_rates[] = {
649 { .div = 1, .val = 0 },
650 { .div = 8, .val = 1 },
651 { .div = 0 },
652};
653DEFINE_CLK_DIVIDER_TABLE(init_60m_fclk, "dpll_usb_m2_ck", &dpll_usb_m2_ck,
654 0x0, OMAP4430_CM_CLKSEL_USB_60MHZ,
655 OMAP4430_CLKSEL_0_0_SHIFT, OMAP4430_CLKSEL_0_0_WIDTH,
656 0x0, init_60m_fclk_rates, NULL);
657
658DEFINE_CLK_DIVIDER(l3_div_ck, "div_core_ck", &div_core_ck, 0x0,
659 OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_L3_SHIFT,
660 OMAP4430_CLKSEL_L3_WIDTH, 0x0, NULL);
661
662DEFINE_CLK_DIVIDER(l4_div_ck, "l3_div_ck", &l3_div_ck, 0x0,
663 OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_L4_SHIFT,
664 OMAP4430_CLKSEL_L4_WIDTH, 0x0, NULL);
665
666DEFINE_CLK_FIXED_FACTOR(lp_clk_div_ck, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck,
667 0x0, 1, 16);
668
669static const char *l4_wkup_clk_mux_ck_parents[] = {
670 "sys_clkin_ck", "lp_clk_div_ck",
671};
672
673DEFINE_CLK_MUX(l4_wkup_clk_mux_ck, l4_wkup_clk_mux_ck_parents, NULL, 0x0,
674 OMAP4430_CM_L4_WKUP_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT,
675 OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL);
676
677static const struct clk_div_table ocp_abe_iclk_rates[] = {
678 { .div = 2, .val = 0 },
679 { .div = 1, .val = 1 },
680 { .div = 0 },
681};
682DEFINE_CLK_DIVIDER_TABLE(ocp_abe_iclk, "aess_fclk", &aess_fclk, 0x0,
683 OMAP4430_CM1_ABE_AESS_CLKCTRL,
684 OMAP4430_CLKSEL_AESS_FCLK_SHIFT,
685 OMAP4430_CLKSEL_AESS_FCLK_WIDTH,
686 0x0, ocp_abe_iclk_rates, NULL);
687
688DEFINE_CLK_FIXED_FACTOR(per_abe_24m_fclk, "dpll_abe_m2_ck", &dpll_abe_m2_ck,
689 0x0, 1, 4);
690
691DEFINE_CLK_DIVIDER(per_abe_nc_fclk, "dpll_abe_m2_ck", &dpll_abe_m2_ck, 0x0,
692 OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT,
693 OMAP4430_SCALE_FCLK_WIDTH, 0x0, NULL);
694
695DEFINE_CLK_DIVIDER(syc_clk_div_ck, "sys_clkin_ck", &sys_clkin_ck, 0x0,
696 OMAP4430_CM_ABE_DSS_SYS_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT,
697 OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL);
698
699static struct clk dbgclk_mux_ck;
700DEFINE_STRUCT_CLK_HW_OMAP(dbgclk_mux_ck, NULL);
701DEFINE_STRUCT_CLK(dbgclk_mux_ck, dpll_core_ck_parents,
702 dpll_usb_clkdcoldo_ck_ops);
703
704/* Leaf clocks controlled by modules */
705
706DEFINE_CLK_GATE(aes1_fck, "l3_div_ck", &l3_div_ck, 0x0,
707 OMAP4430_CM_L4SEC_AES1_CLKCTRL,
708 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
709
710DEFINE_CLK_GATE(aes2_fck, "l3_div_ck", &l3_div_ck, 0x0,
711 OMAP4430_CM_L4SEC_AES2_CLKCTRL,
712 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
713
714DEFINE_CLK_GATE(aess_fck, "aess_fclk", &aess_fclk, 0x0,
715 OMAP4430_CM1_ABE_AESS_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
716 0x0, NULL);
717
718DEFINE_CLK_GATE(bandgap_fclk, "sys_32k_ck", &sys_32k_ck, 0x0,
719 OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
720 OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT, 0x0, NULL);
721
722static const struct clk_div_table div_ts_ck_rates[] = {
723 { .div = 8, .val = 0 },
724 { .div = 16, .val = 1 },
725 { .div = 32, .val = 2 },
726 { .div = 0 },
727};
728DEFINE_CLK_DIVIDER_TABLE(div_ts_ck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
729 0x0, OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
730 OMAP4430_CLKSEL_24_25_SHIFT,
731 OMAP4430_CLKSEL_24_25_WIDTH, 0x0, div_ts_ck_rates,
732 NULL);
733
734DEFINE_CLK_GATE(bandgap_ts_fclk, "div_ts_ck", &div_ts_ck, 0x0,
735 OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
736 OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT,
737 0x0, NULL);
738
739DEFINE_CLK_GATE(des3des_fck, "l4_div_ck", &l4_div_ck, 0x0,
740 OMAP4430_CM_L4SEC_DES3DES_CLKCTRL,
741 OMAP4430_MODULEMODE_SWCTRL_SHIFT,
742 0x0, NULL);
743
744static const char *dmic_sync_mux_ck_parents[] = {
745 "abe_24m_fclk", "syc_clk_div_ck", "func_24m_clk",
746};
747
748DEFINE_CLK_MUX(dmic_sync_mux_ck, dmic_sync_mux_ck_parents, NULL,
749 0x0, OMAP4430_CM1_ABE_DMIC_CLKCTRL,
750 OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
751 OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
752
753static const struct clksel func_dmic_abe_gfclk_sel[] = {
754 { .parent = &dmic_sync_mux_ck, .rates = div_1_0_rates },
755 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
756 { .parent = &slimbus_clk, .rates = div_1_2_rates },
757 { .parent = NULL },
758};
759
760static const char *dmic_fck_parents[] = {
761 "dmic_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
762};
763
764/* Merged func_dmic_abe_gfclk into dmic */
765static struct clk dmic_fck;
766
767DEFINE_CLK_OMAP_MUX_GATE(dmic_fck, "abe_clkdm", func_dmic_abe_gfclk_sel,
768 OMAP4430_CM1_ABE_DMIC_CLKCTRL,
769 OMAP4430_CLKSEL_SOURCE_MASK,
770 OMAP4430_CM1_ABE_DMIC_CLKCTRL,
771 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
772 dmic_fck_parents, dmic_fck_ops);
773
774DEFINE_CLK_GATE(dsp_fck, "dpll_iva_m4x2_ck", &dpll_iva_m4x2_ck, 0x0,
775 OMAP4430_CM_TESLA_TESLA_CLKCTRL,
776 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
777
778DEFINE_CLK_GATE(dss_sys_clk, "syc_clk_div_ck", &syc_clk_div_ck, 0x0,
779 OMAP4430_CM_DSS_DSS_CLKCTRL,
780 OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT, 0x0, NULL);
781
782DEFINE_CLK_GATE(dss_tv_clk, "extalt_clkin_ck", &extalt_clkin_ck, 0x0,
783 OMAP4430_CM_DSS_DSS_CLKCTRL,
784 OMAP4430_OPTFCLKEN_TV_CLK_SHIFT, 0x0, NULL);
785
786DEFINE_CLK_GATE(dss_dss_clk, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, 0x0,
787 OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_OPTFCLKEN_DSSCLK_SHIFT,
788 0x0, NULL);
789
790DEFINE_CLK_GATE(dss_48mhz_clk, "func_48mc_fclk", &func_48mc_fclk, 0x0,
791 OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT,
792 0x0, NULL);
793
794DEFINE_CLK_GATE(dss_fck, "l3_div_ck", &l3_div_ck, 0x0,
795 OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
796 0x0, NULL);
797
798DEFINE_CLK_GATE(efuse_ctrl_cust_fck, "sys_clkin_ck", &sys_clkin_ck, 0x0,
799 OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL,
800 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
801
802DEFINE_CLK_GATE(emif1_fck, "ddrphy_ck", &ddrphy_ck, 0x0,
803 OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL,
804 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
805
806DEFINE_CLK_GATE(emif2_fck, "ddrphy_ck", &ddrphy_ck, 0x0,
807 OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL,
808 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
809
810DEFINE_CLK_DIVIDER(fdif_fck, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, 0x0,
811 OMAP4430_CM_CAM_FDIF_CLKCTRL, OMAP4430_CLKSEL_FCLK_SHIFT,
812 OMAP4430_CLKSEL_FCLK_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
813
814DEFINE_CLK_GATE(fpka_fck, "l4_div_ck", &l4_div_ck, 0x0,
815 OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL,
816 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
817
818DEFINE_CLK_GATE(gpio1_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
819 OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
820 OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL);
821
822DEFINE_CLK_GATE(gpio1_ick, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, 0x0,
823 OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
824 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
825
826DEFINE_CLK_GATE(gpio2_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
827 OMAP4430_CM_L4PER_GPIO2_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
828 0x0, NULL);
829
830DEFINE_CLK_GATE(gpio2_ick, "l4_div_ck", &l4_div_ck, 0x0,
831 OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
832 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
833
834DEFINE_CLK_GATE(gpio3_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
835 OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
836 OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL);
837
838DEFINE_CLK_GATE(gpio3_ick, "l4_div_ck", &l4_div_ck, 0x0,
839 OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
840 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
841
842DEFINE_CLK_GATE(gpio4_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
843 OMAP4430_CM_L4PER_GPIO4_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
844 0x0, NULL);
845
846DEFINE_CLK_GATE(gpio4_ick, "l4_div_ck", &l4_div_ck, 0x0,
847 OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
848 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
849
850DEFINE_CLK_GATE(gpio5_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
851 OMAP4430_CM_L4PER_GPIO5_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
852 0x0, NULL);
853
854DEFINE_CLK_GATE(gpio5_ick, "l4_div_ck", &l4_div_ck, 0x0,
855 OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
856 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
857
858DEFINE_CLK_GATE(gpio6_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
859 OMAP4430_CM_L4PER_GPIO6_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
860 0x0, NULL);
861
862DEFINE_CLK_GATE(gpio6_ick, "l4_div_ck", &l4_div_ck, 0x0,
863 OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
864 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
865
866DEFINE_CLK_GATE(gpmc_ick, "l3_div_ck", &l3_div_ck, 0x0,
867 OMAP4430_CM_L3_2_GPMC_CLKCTRL, OMAP4430_MODULEMODE_HWCTRL_SHIFT,
868 0x0, NULL);
869
870static const struct clksel sgx_clk_mux_sel[] = {
871 { .parent = &dpll_core_m7x2_ck, .rates = div_1_0_rates },
872 { .parent = &dpll_per_m7x2_ck, .rates = div_1_1_rates },
873 { .parent = NULL },
874};
875
876static const char *gpu_fck_parents[] = {
877 "dpll_core_m7x2_ck", "dpll_per_m7x2_ck",
878};
879
880/* Merged sgx_clk_mux into gpu */
881DEFINE_CLK_OMAP_MUX_GATE(gpu_fck, "l3_gfx_clkdm", sgx_clk_mux_sel,
882 OMAP4430_CM_GFX_GFX_CLKCTRL,
883 OMAP4430_CLKSEL_SGX_FCLK_MASK,
884 OMAP4430_CM_GFX_GFX_CLKCTRL,
885 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
886 gpu_fck_parents, dmic_fck_ops);
887
888DEFINE_CLK_GATE(hdq1w_fck, "func_12m_fclk", &func_12m_fclk, 0x0,
889 OMAP4430_CM_L4PER_HDQ1W_CLKCTRL,
890 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
891
892DEFINE_CLK_DIVIDER(hsi_fck, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, 0x0,
893 OMAP4430_CM_L3INIT_HSI_CLKCTRL, OMAP4430_CLKSEL_24_25_SHIFT,
894 OMAP4430_CLKSEL_24_25_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
895 NULL);
896
897DEFINE_CLK_GATE(i2c1_fck, "func_96m_fclk", &func_96m_fclk, 0x0,
898 OMAP4430_CM_L4PER_I2C1_CLKCTRL,
899 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
900
901DEFINE_CLK_GATE(i2c2_fck, "func_96m_fclk", &func_96m_fclk, 0x0,
902 OMAP4430_CM_L4PER_I2C2_CLKCTRL,
903 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
904
905DEFINE_CLK_GATE(i2c3_fck, "func_96m_fclk", &func_96m_fclk, 0x0,
906 OMAP4430_CM_L4PER_I2C3_CLKCTRL,
907 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
908
909DEFINE_CLK_GATE(i2c4_fck, "func_96m_fclk", &func_96m_fclk, 0x0,
910 OMAP4430_CM_L4PER_I2C4_CLKCTRL,
911 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
912
913DEFINE_CLK_GATE(ipu_fck, "ducati_clk_mux_ck", &ducati_clk_mux_ck, 0x0,
914 OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
915 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
916
917DEFINE_CLK_GATE(iss_ctrlclk, "func_96m_fclk", &func_96m_fclk, 0x0,
918 OMAP4430_CM_CAM_ISS_CLKCTRL, OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT,
919 0x0, NULL);
920
921DEFINE_CLK_GATE(iss_fck, "ducati_clk_mux_ck", &ducati_clk_mux_ck, 0x0,
922 OMAP4430_CM_CAM_ISS_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
923 0x0, NULL);
924
925DEFINE_CLK_GATE(iva_fck, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck, 0x0,
926 OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
927 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
928
929DEFINE_CLK_GATE(kbd_fck, "sys_32k_ck", &sys_32k_ck, 0x0,
930 OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
931 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
932
933static struct clk l3_instr_ick;
934
935static const char *l3_instr_ick_parent_names[] = {
936 "l3_div_ck",
937};
938
939static const struct clk_ops l3_instr_ick_ops = {
940 .enable = &omap2_dflt_clk_enable,
941 .disable = &omap2_dflt_clk_disable,
942 .is_enabled = &omap2_dflt_clk_is_enabled,
943 .init = &omap2_init_clk_clkdm,
944};
945
946static struct clk_hw_omap l3_instr_ick_hw = {
947 .hw = {
948 .clk = &l3_instr_ick,
949 },
950 .enable_reg = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL,
951 .enable_bit = OMAP4430_MODULEMODE_HWCTRL_SHIFT,
952 .clkdm_name = "l3_instr_clkdm",
953};
954
955DEFINE_STRUCT_CLK(l3_instr_ick, l3_instr_ick_parent_names, l3_instr_ick_ops);
956
957static struct clk l3_main_3_ick;
958static struct clk_hw_omap l3_main_3_ick_hw = {
959 .hw = {
960 .clk = &l3_main_3_ick,
961 },
962 .enable_reg = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL,
963 .enable_bit = OMAP4430_MODULEMODE_HWCTRL_SHIFT,
964 .clkdm_name = "l3_instr_clkdm",
965};
966
967DEFINE_STRUCT_CLK(l3_main_3_ick, l3_instr_ick_parent_names, l3_instr_ick_ops);
968
969DEFINE_CLK_MUX(mcasp_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
970 OMAP4430_CM1_ABE_MCASP_CLKCTRL,
971 OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
972 OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
973
974static const struct clksel func_mcasp_abe_gfclk_sel[] = {
975 { .parent = &mcasp_sync_mux_ck, .rates = div_1_0_rates },
976 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
977 { .parent = &slimbus_clk, .rates = div_1_2_rates },
978 { .parent = NULL },
979};
980
981static const char *mcasp_fck_parents[] = {
982 "mcasp_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
983};
984
985/* Merged func_mcasp_abe_gfclk into mcasp */
986DEFINE_CLK_OMAP_MUX_GATE(mcasp_fck, "abe_clkdm", func_mcasp_abe_gfclk_sel,
987 OMAP4430_CM1_ABE_MCASP_CLKCTRL,
988 OMAP4430_CLKSEL_SOURCE_MASK,
989 OMAP4430_CM1_ABE_MCASP_CLKCTRL,
990 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
991 mcasp_fck_parents, dmic_fck_ops);
992
993DEFINE_CLK_MUX(mcbsp1_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
994 OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
995 OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
996 OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
997
998static const struct clksel func_mcbsp1_gfclk_sel[] = {
999 { .parent = &mcbsp1_sync_mux_ck, .rates = div_1_0_rates },
1000 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1001 { .parent = &slimbus_clk, .rates = div_1_2_rates },
1002 { .parent = NULL },
1003};
1004
1005static const char *mcbsp1_fck_parents[] = {
1006 "mcbsp1_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
1007};
1008
1009/* Merged func_mcbsp1_gfclk into mcbsp1 */
1010DEFINE_CLK_OMAP_MUX_GATE(mcbsp1_fck, "abe_clkdm", func_mcbsp1_gfclk_sel,
1011 OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1012 OMAP4430_CLKSEL_SOURCE_MASK,
1013 OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1014 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1015 mcbsp1_fck_parents, dmic_fck_ops);
1016
1017DEFINE_CLK_MUX(mcbsp2_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
1018 OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1019 OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
1020 OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
1021
1022static const struct clksel func_mcbsp2_gfclk_sel[] = {
1023 { .parent = &mcbsp2_sync_mux_ck, .rates = div_1_0_rates },
1024 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1025 { .parent = &slimbus_clk, .rates = div_1_2_rates },
1026 { .parent = NULL },
1027};
1028
1029static const char *mcbsp2_fck_parents[] = {
1030 "mcbsp2_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
1031};
1032
1033/* Merged func_mcbsp2_gfclk into mcbsp2 */
1034DEFINE_CLK_OMAP_MUX_GATE(mcbsp2_fck, "abe_clkdm", func_mcbsp2_gfclk_sel,
1035 OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1036 OMAP4430_CLKSEL_SOURCE_MASK,
1037 OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1038 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1039 mcbsp2_fck_parents, dmic_fck_ops);
1040
1041DEFINE_CLK_MUX(mcbsp3_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
1042 OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
1043 OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
1044 OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
1045
1046static const struct clksel func_mcbsp3_gfclk_sel[] = {
1047 { .parent = &mcbsp3_sync_mux_ck, .rates = div_1_0_rates },
1048 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1049 { .parent = &slimbus_clk, .rates = div_1_2_rates },
1050 { .parent = NULL },
1051};
1052
1053static const char *mcbsp3_fck_parents[] = {
1054 "mcbsp3_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
1055};
1056
1057/* Merged func_mcbsp3_gfclk into mcbsp3 */
1058DEFINE_CLK_OMAP_MUX_GATE(mcbsp3_fck, "abe_clkdm", func_mcbsp3_gfclk_sel,
1059 OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
1060 OMAP4430_CLKSEL_SOURCE_MASK,
1061 OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
1062 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1063 mcbsp3_fck_parents, dmic_fck_ops);
1064
1065static const char *mcbsp4_sync_mux_ck_parents[] = {
1066 "func_96m_fclk", "per_abe_nc_fclk",
1067};
1068
1069DEFINE_CLK_MUX(mcbsp4_sync_mux_ck, mcbsp4_sync_mux_ck_parents, NULL, 0x0,
1070 OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
1071 OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
1072 OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
1073
1074static const struct clksel per_mcbsp4_gfclk_sel[] = {
1075 { .parent = &mcbsp4_sync_mux_ck, .rates = div_1_0_rates },
1076 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1077 { .parent = NULL },
1078};
1079
1080static const char *mcbsp4_fck_parents[] = {
1081 "mcbsp4_sync_mux_ck", "pad_clks_ck",
1082};
1083
1084/* Merged per_mcbsp4_gfclk into mcbsp4 */
1085DEFINE_CLK_OMAP_MUX_GATE(mcbsp4_fck, "l4_per_clkdm", per_mcbsp4_gfclk_sel,
1086 OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
1087 OMAP4430_CLKSEL_SOURCE_24_24_MASK,
1088 OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
1089 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1090 mcbsp4_fck_parents, dmic_fck_ops);
1091
1092DEFINE_CLK_GATE(mcpdm_fck, "pad_clks_ck", &pad_clks_ck, 0x0,
1093 OMAP4430_CM1_ABE_PDM_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
1094 0x0, NULL);
1095
1096DEFINE_CLK_GATE(mcspi1_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
1097 OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
1098 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1099
1100DEFINE_CLK_GATE(mcspi2_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
1101 OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
1102 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1103
1104DEFINE_CLK_GATE(mcspi3_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
1105 OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
1106 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1107
1108DEFINE_CLK_GATE(mcspi4_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
1109 OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
1110 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1111
1112static const struct clksel hsmmc1_fclk_sel[] = {
1113 { .parent = &func_64m_fclk, .rates = div_1_0_rates },
1114 { .parent = &func_96m_fclk, .rates = div_1_1_rates },
1115 { .parent = NULL },
1116};
1117
1118static const char *mmc1_fck_parents[] = {
1119 "func_64m_fclk", "func_96m_fclk",
1120};
1121
1122/* Merged hsmmc1_fclk into mmc1 */
1123DEFINE_CLK_OMAP_MUX_GATE(mmc1_fck, "l3_init_clkdm", hsmmc1_fclk_sel,
1124 OMAP4430_CM_L3INIT_MMC1_CLKCTRL, OMAP4430_CLKSEL_MASK,
1125 OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
1126 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1127 mmc1_fck_parents, dmic_fck_ops);
1128
1129/* Merged hsmmc2_fclk into mmc2 */
1130DEFINE_CLK_OMAP_MUX_GATE(mmc2_fck, "l3_init_clkdm", hsmmc1_fclk_sel,
1131 OMAP4430_CM_L3INIT_MMC2_CLKCTRL, OMAP4430_CLKSEL_MASK,
1132 OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
1133 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1134 mmc1_fck_parents, dmic_fck_ops);
1135
1136DEFINE_CLK_GATE(mmc3_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
1137 OMAP4430_CM_L4PER_MMCSD3_CLKCTRL,
1138 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1139
1140DEFINE_CLK_GATE(mmc4_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
1141 OMAP4430_CM_L4PER_MMCSD4_CLKCTRL,
1142 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1143
1144DEFINE_CLK_GATE(mmc5_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
1145 OMAP4430_CM_L4PER_MMCSD5_CLKCTRL,
1146 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1147
1148DEFINE_CLK_GATE(ocp2scp_usb_phy_phy_48m, "func_48m_fclk", &func_48m_fclk, 0x0,
1149 OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
1150 OMAP4430_OPTFCLKEN_PHY_48M_SHIFT, 0x0, NULL);
1151
1152DEFINE_CLK_GATE(ocp2scp_usb_phy_ick, "l4_div_ck", &l4_div_ck, 0x0,
1153 OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
1154 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
1155
1156static struct clk ocp_wp_noc_ick;
1157
1158static struct clk_hw_omap ocp_wp_noc_ick_hw = {
1159 .hw = {
1160 .clk = &ocp_wp_noc_ick,
1161 },
1162 .enable_reg = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL,
1163 .enable_bit = OMAP4430_MODULEMODE_HWCTRL_SHIFT,
1164 .clkdm_name = "l3_instr_clkdm",
1165};
1166
1167DEFINE_STRUCT_CLK(ocp_wp_noc_ick, l3_instr_ick_parent_names, l3_instr_ick_ops);
1168
1169DEFINE_CLK_GATE(rng_ick, "l4_div_ck", &l4_div_ck, 0x0,
1170 OMAP4430_CM_L4SEC_RNG_CLKCTRL, OMAP4430_MODULEMODE_HWCTRL_SHIFT,
1171 0x0, NULL);
1172
1173DEFINE_CLK_GATE(sha2md5_fck, "l3_div_ck", &l3_div_ck, 0x0,
1174 OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL,
1175 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1176
1177DEFINE_CLK_GATE(sl2if_ick, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck, 0x0,
1178 OMAP4430_CM_IVAHD_SL2_CLKCTRL, OMAP4430_MODULEMODE_HWCTRL_SHIFT,
1179 0x0, NULL);
1180
1181DEFINE_CLK_GATE(slimbus1_fclk_1, "func_24m_clk", &func_24m_clk, 0x0,
1182 OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
1183 OMAP4430_OPTFCLKEN_FCLK1_SHIFT, 0x0, NULL);
1184
1185DEFINE_CLK_GATE(slimbus1_fclk_0, "abe_24m_fclk", &abe_24m_fclk, 0x0,
1186 OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
1187 OMAP4430_OPTFCLKEN_FCLK0_SHIFT, 0x0, NULL);
1188
1189DEFINE_CLK_GATE(slimbus1_fclk_2, "pad_clks_ck", &pad_clks_ck, 0x0,
1190 OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
1191 OMAP4430_OPTFCLKEN_FCLK2_SHIFT, 0x0, NULL);
1192
1193DEFINE_CLK_GATE(slimbus1_slimbus_clk, "slimbus_clk", &slimbus_clk, 0x0,
1194 OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
1195 OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT, 0x0, NULL);
1196
1197DEFINE_CLK_GATE(slimbus1_fck, "ocp_abe_iclk", &ocp_abe_iclk, 0x0,
1198 OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
1199 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1200
1201DEFINE_CLK_GATE(slimbus2_fclk_1, "per_abe_24m_fclk", &per_abe_24m_fclk, 0x0,
1202 OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
1203 OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT, 0x0, NULL);
1204
1205DEFINE_CLK_GATE(slimbus2_fclk_0, "func_24mc_fclk", &func_24mc_fclk, 0x0,
1206 OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
1207 OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT, 0x0, NULL);
1208
1209DEFINE_CLK_GATE(slimbus2_slimbus_clk, "pad_slimbus_core_clks_ck",
1210 &pad_slimbus_core_clks_ck, 0x0,
1211 OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
1212 OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT, 0x0, NULL);
1213
1214DEFINE_CLK_GATE(slimbus2_fck, "l4_div_ck", &l4_div_ck, 0x0,
1215 OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
1216 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1217
1218DEFINE_CLK_GATE(smartreflex_core_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
1219 0x0, OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
1220 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1221
1222DEFINE_CLK_GATE(smartreflex_iva_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
1223 0x0, OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
1224 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1225
1226DEFINE_CLK_GATE(smartreflex_mpu_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
1227 0x0, OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
1228 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1229
1230static const struct clksel dmt1_clk_mux_sel[] = {
1231 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
1232 { .parent = &sys_32k_ck, .rates = div_1_1_rates },
1233 { .parent = NULL },
1234};
1235
1236/* Merged dmt1_clk_mux into timer1 */
1237DEFINE_CLK_OMAP_MUX_GATE(timer1_fck, "l4_wkup_clkdm", dmt1_clk_mux_sel,
1238 OMAP4430_CM_WKUP_TIMER1_CLKCTRL, OMAP4430_CLKSEL_MASK,
1239 OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
1240 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1241 abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops);
1242
1243/* Merged cm2_dm10_mux into timer10 */
1244DEFINE_CLK_OMAP_MUX_GATE(timer10_fck, "l4_per_clkdm", dmt1_clk_mux_sel,
1245 OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
1246 OMAP4430_CLKSEL_MASK,
1247 OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
1248 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1249 abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops);
1250
1251/* Merged cm2_dm11_mux into timer11 */
1252DEFINE_CLK_OMAP_MUX_GATE(timer11_fck, "l4_per_clkdm", dmt1_clk_mux_sel,
1253 OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
1254 OMAP4430_CLKSEL_MASK,
1255 OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
1256 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1257 abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops);
1258
1259/* Merged cm2_dm2_mux into timer2 */
1260DEFINE_CLK_OMAP_MUX_GATE(timer2_fck, "l4_per_clkdm", dmt1_clk_mux_sel,
1261 OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
1262 OMAP4430_CLKSEL_MASK,
1263 OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
1264 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1265 abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops);
1266
1267/* Merged cm2_dm3_mux into timer3 */
1268DEFINE_CLK_OMAP_MUX_GATE(timer3_fck, "l4_per_clkdm", dmt1_clk_mux_sel,
1269 OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
1270 OMAP4430_CLKSEL_MASK,
1271 OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
1272 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1273 abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops);
1274
1275/* Merged cm2_dm4_mux into timer4 */
1276DEFINE_CLK_OMAP_MUX_GATE(timer4_fck, "l4_per_clkdm", dmt1_clk_mux_sel,
1277 OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
1278 OMAP4430_CLKSEL_MASK,
1279 OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
1280 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1281 abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops);
1282
1283static const struct clksel timer5_sync_mux_sel[] = {
1284 { .parent = &syc_clk_div_ck, .rates = div_1_0_rates },
1285 { .parent = &sys_32k_ck, .rates = div_1_1_rates },
1286 { .parent = NULL },
1287};
1288
1289static const char *timer5_fck_parents[] = {
1290 "syc_clk_div_ck", "sys_32k_ck",
1291};
1292
1293/* Merged timer5_sync_mux into timer5 */
1294DEFINE_CLK_OMAP_MUX_GATE(timer5_fck, "abe_clkdm", timer5_sync_mux_sel,
1295 OMAP4430_CM1_ABE_TIMER5_CLKCTRL, OMAP4430_CLKSEL_MASK,
1296 OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
1297 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1298 timer5_fck_parents, dmic_fck_ops);
1299
1300/* Merged timer6_sync_mux into timer6 */
1301DEFINE_CLK_OMAP_MUX_GATE(timer6_fck, "abe_clkdm", timer5_sync_mux_sel,
1302 OMAP4430_CM1_ABE_TIMER6_CLKCTRL, OMAP4430_CLKSEL_MASK,
1303 OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
1304 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1305 timer5_fck_parents, dmic_fck_ops);
1306
1307/* Merged timer7_sync_mux into timer7 */
1308DEFINE_CLK_OMAP_MUX_GATE(timer7_fck, "abe_clkdm", timer5_sync_mux_sel,
1309 OMAP4430_CM1_ABE_TIMER7_CLKCTRL, OMAP4430_CLKSEL_MASK,
1310 OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
1311 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1312 timer5_fck_parents, dmic_fck_ops);
1313
1314/* Merged timer8_sync_mux into timer8 */
1315DEFINE_CLK_OMAP_MUX_GATE(timer8_fck, "abe_clkdm", timer5_sync_mux_sel,
1316 OMAP4430_CM1_ABE_TIMER8_CLKCTRL, OMAP4430_CLKSEL_MASK,
1317 OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
1318 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1319 timer5_fck_parents, dmic_fck_ops);
1320
1321/* Merged cm2_dm9_mux into timer9 */
1322DEFINE_CLK_OMAP_MUX_GATE(timer9_fck, "l4_per_clkdm", dmt1_clk_mux_sel,
1323 OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
1324 OMAP4430_CLKSEL_MASK,
1325 OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
1326 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1327 abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops);
1328
1329DEFINE_CLK_GATE(uart1_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
1330 OMAP4430_CM_L4PER_UART1_CLKCTRL,
1331 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1332
1333DEFINE_CLK_GATE(uart2_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
1334 OMAP4430_CM_L4PER_UART2_CLKCTRL,
1335 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1336
1337DEFINE_CLK_GATE(uart3_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
1338 OMAP4430_CM_L4PER_UART3_CLKCTRL,
1339 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1340
1341DEFINE_CLK_GATE(uart4_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
1342 OMAP4430_CM_L4PER_UART4_CLKCTRL,
1343 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1344
1345static struct clk usb_host_fs_fck;
1346
1347static const char *usb_host_fs_fck_parent_names[] = {
1348 "func_48mc_fclk",
1349};
1350
1351static const struct clk_ops usb_host_fs_fck_ops = {
1352 .enable = &omap2_dflt_clk_enable,
1353 .disable = &omap2_dflt_clk_disable,
1354 .is_enabled = &omap2_dflt_clk_is_enabled,
1355};
1356
1357static struct clk_hw_omap usb_host_fs_fck_hw = {
1358 .hw = {
1359 .clk = &usb_host_fs_fck,
1360 },
1361 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL,
1362 .enable_bit = OMAP4430_MODULEMODE_SWCTRL_SHIFT,
1363 .clkdm_name = "l3_init_clkdm",
1364};
1365
1366DEFINE_STRUCT_CLK(usb_host_fs_fck, usb_host_fs_fck_parent_names,
1367 usb_host_fs_fck_ops);
1368
1369static const char *utmi_p1_gfclk_parents[] = {
1370 "init_60m_fclk", "xclk60mhsp1_ck",
1371};
1372
1373DEFINE_CLK_MUX(utmi_p1_gfclk, utmi_p1_gfclk_parents, NULL, 0x0,
1374 OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
1375 OMAP4430_CLKSEL_UTMI_P1_SHIFT, OMAP4430_CLKSEL_UTMI_P1_WIDTH,
1376 0x0, NULL);
1377
1378DEFINE_CLK_GATE(usb_host_hs_utmi_p1_clk, "utmi_p1_gfclk", &utmi_p1_gfclk, 0x0,
1379 OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
1380 OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT, 0x0, NULL);
1381
1382static const char *utmi_p2_gfclk_parents[] = {
1383 "init_60m_fclk", "xclk60mhsp2_ck",
1384};
1385
1386DEFINE_CLK_MUX(utmi_p2_gfclk, utmi_p2_gfclk_parents, NULL, 0x0,
1387 OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
1388 OMAP4430_CLKSEL_UTMI_P2_SHIFT, OMAP4430_CLKSEL_UTMI_P2_WIDTH,
1389 0x0, NULL);
1390
1391DEFINE_CLK_GATE(usb_host_hs_utmi_p2_clk, "utmi_p2_gfclk", &utmi_p2_gfclk, 0x0,
1392 OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
1393 OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT, 0x0, NULL);
1394
1395DEFINE_CLK_GATE(usb_host_hs_utmi_p3_clk, "init_60m_fclk", &init_60m_fclk, 0x0,
1396 OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
1397 OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT, 0x0, NULL);
1398
1399DEFINE_CLK_GATE(usb_host_hs_hsic480m_p1_clk, "dpll_usb_m2_ck",
1400 &dpll_usb_m2_ck, 0x0,
1401 OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
1402 OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT, 0x0, NULL);
1403
1404DEFINE_CLK_GATE(usb_host_hs_hsic60m_p1_clk, "init_60m_fclk",
1405 &init_60m_fclk, 0x0,
1406 OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
1407 OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT, 0x0, NULL);
1408
1409DEFINE_CLK_GATE(usb_host_hs_hsic60m_p2_clk, "init_60m_fclk",
1410 &init_60m_fclk, 0x0,
1411 OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
1412 OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT, 0x0, NULL);
1413
1414DEFINE_CLK_GATE(usb_host_hs_hsic480m_p2_clk, "dpll_usb_m2_ck",
1415 &dpll_usb_m2_ck, 0x0,
1416 OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
1417 OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT, 0x0, NULL);
1418
1419DEFINE_CLK_GATE(usb_host_hs_func48mclk, "func_48mc_fclk", &func_48mc_fclk, 0x0,
1420 OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
1421 OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT, 0x0, NULL);
1422
1423DEFINE_CLK_GATE(usb_host_hs_fck, "init_60m_fclk", &init_60m_fclk, 0x0,
1424 OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
1425 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1426
1427static const char *otg_60m_gfclk_parents[] = {
1428 "utmi_phy_clkout_ck", "xclk60motg_ck",
1429};
1430
1431DEFINE_CLK_MUX(otg_60m_gfclk, otg_60m_gfclk_parents, NULL, 0x0,
1432 OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, OMAP4430_CLKSEL_60M_SHIFT,
1433 OMAP4430_CLKSEL_60M_WIDTH, 0x0, NULL);
1434
1435DEFINE_CLK_GATE(usb_otg_hs_xclk, "otg_60m_gfclk", &otg_60m_gfclk, 0x0,
1436 OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
1437 OMAP4430_OPTFCLKEN_XCLK_SHIFT, 0x0, NULL);
1438
1439DEFINE_CLK_GATE(usb_otg_hs_ick, "l3_div_ck", &l3_div_ck, 0x0,
1440 OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
1441 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
1442
1443DEFINE_CLK_GATE(usb_phy_cm_clk32k, "sys_32k_ck", &sys_32k_ck, 0x0,
1444 OMAP4430_CM_ALWON_USBPHY_CLKCTRL,
1445 OMAP4430_OPTFCLKEN_CLK32K_SHIFT, 0x0, NULL);
1446
1447DEFINE_CLK_GATE(usb_tll_hs_usb_ch2_clk, "init_60m_fclk", &init_60m_fclk, 0x0,
1448 OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
1449 OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT, 0x0, NULL);
1450
1451DEFINE_CLK_GATE(usb_tll_hs_usb_ch0_clk, "init_60m_fclk", &init_60m_fclk, 0x0,
1452 OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
1453 OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT, 0x0, NULL);
1454
1455DEFINE_CLK_GATE(usb_tll_hs_usb_ch1_clk, "init_60m_fclk", &init_60m_fclk, 0x0,
1456 OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
1457 OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT, 0x0, NULL);
1458
1459DEFINE_CLK_GATE(usb_tll_hs_ick, "l4_div_ck", &l4_div_ck, 0x0,
1460 OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
1461 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
1462
1463static const struct clk_div_table usim_ck_rates[] = {
1464 { .div = 14, .val = 0 },
1465 { .div = 18, .val = 1 },
1466 { .div = 0 },
1467};
1468DEFINE_CLK_DIVIDER_TABLE(usim_ck, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, 0x0,
1469 OMAP4430_CM_WKUP_USIM_CLKCTRL,
1470 OMAP4430_CLKSEL_DIV_SHIFT, OMAP4430_CLKSEL_DIV_WIDTH,
1471 0x0, usim_ck_rates, NULL);
1472
1473DEFINE_CLK_GATE(usim_fclk, "usim_ck", &usim_ck, 0x0,
1474 OMAP4430_CM_WKUP_USIM_CLKCTRL, OMAP4430_OPTFCLKEN_FCLK_SHIFT,
1475 0x0, NULL);
1476
1477DEFINE_CLK_GATE(usim_fck, "sys_32k_ck", &sys_32k_ck, 0x0,
1478 OMAP4430_CM_WKUP_USIM_CLKCTRL, OMAP4430_MODULEMODE_HWCTRL_SHIFT,
1479 0x0, NULL);
1480
1481DEFINE_CLK_GATE(wd_timer2_fck, "sys_32k_ck", &sys_32k_ck, 0x0,
1482 OMAP4430_CM_WKUP_WDT2_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
1483 0x0, NULL);
1484
1485DEFINE_CLK_GATE(wd_timer3_fck, "sys_32k_ck", &sys_32k_ck, 0x0,
1486 OMAP4430_CM1_ABE_WDT3_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
1487 0x0, NULL);
1488
1489/* Remaining optional clocks */
1490static const char *pmd_stm_clock_mux_ck_parents[] = {
1491 "sys_clkin_ck", "dpll_core_m6x2_ck", "tie_low_clock_ck",
1492};
1493
1494DEFINE_CLK_MUX(pmd_stm_clock_mux_ck, pmd_stm_clock_mux_ck_parents, NULL, 0x0,
1495 OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, OMAP4430_PMD_STM_MUX_CTRL_SHIFT,
1496 OMAP4430_PMD_STM_MUX_CTRL_WIDTH, 0x0, NULL);
1497
1498DEFINE_CLK_MUX(pmd_trace_clk_mux_ck, pmd_stm_clock_mux_ck_parents, NULL, 0x0,
1499 OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
1500 OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT,
1501 OMAP4430_PMD_TRACE_MUX_CTRL_WIDTH, 0x0, NULL);
1502
1503DEFINE_CLK_DIVIDER(stm_clk_div_ck, "pmd_stm_clock_mux_ck",
1504 &pmd_stm_clock_mux_ck, 0x0, OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
1505 OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT,
1506 OMAP4430_CLKSEL_PMD_STM_CLK_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
1507 NULL);
1508
1509static const char *trace_clk_div_ck_parents[] = {
1510 "pmd_trace_clk_mux_ck",
1511};
1512
1513static const struct clksel trace_clk_div_div[] = {
1514 { .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates },
1515 { .parent = NULL },
1516};
1517
1518static struct clk trace_clk_div_ck;
1519
1520static const struct clk_ops trace_clk_div_ck_ops = {
1521 .recalc_rate = &omap2_clksel_recalc,
1522 .set_rate = &omap2_clksel_set_rate,
1523 .round_rate = &omap2_clksel_round_rate,
1524 .init = &omap2_init_clk_clkdm,
1525 .enable = &omap2_clkops_enable_clkdm,
1526 .disable = &omap2_clkops_disable_clkdm,
1527};
1528
1529static struct clk_hw_omap trace_clk_div_ck_hw = {
1530 .hw = {
1531 .clk = &trace_clk_div_ck,
1532 },
1533 .clkdm_name = "emu_sys_clkdm",
1534 .clksel = trace_clk_div_div,
1535 .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
1536 .clksel_mask = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK,
1537};
1538
1539DEFINE_STRUCT_CLK(trace_clk_div_ck, trace_clk_div_ck_parents,
1540 trace_clk_div_ck_ops);
1541
1542/* SCRM aux clk nodes */
1543
1544static const struct clksel auxclk_src_sel[] = {
1545 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
1546 { .parent = &dpll_core_m3x2_ck, .rates = div_1_1_rates },
1547 { .parent = &dpll_per_m3x2_ck, .rates = div_1_2_rates },
1548 { .parent = NULL },
1549};
1550
1551static const char *auxclk_src_ck_parents[] = {
1552 "sys_clkin_ck", "dpll_core_m3x2_ck", "dpll_per_m3x2_ck",
1553};
1554
1555static const struct clk_ops auxclk_src_ck_ops = {
1556 .enable = &omap2_dflt_clk_enable,
1557 .disable = &omap2_dflt_clk_disable,
1558 .is_enabled = &omap2_dflt_clk_is_enabled,
1559 .recalc_rate = &omap2_clksel_recalc,
1560 .get_parent = &omap2_clksel_find_parent_index,
1561};
1562
1563DEFINE_CLK_OMAP_MUX_GATE(auxclk0_src_ck, NULL, auxclk_src_sel,
1564 OMAP4_SCRM_AUXCLK0, OMAP4_SRCSELECT_MASK,
1565 OMAP4_SCRM_AUXCLK0, OMAP4_ENABLE_SHIFT, NULL,
1566 auxclk_src_ck_parents, auxclk_src_ck_ops);
1567
1568DEFINE_CLK_DIVIDER(auxclk0_ck, "auxclk0_src_ck", &auxclk0_src_ck, 0x0,
1569 OMAP4_SCRM_AUXCLK0, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
1570 0x0, NULL);
1571
1572DEFINE_CLK_OMAP_MUX_GATE(auxclk1_src_ck, NULL, auxclk_src_sel,
1573 OMAP4_SCRM_AUXCLK1, OMAP4_SRCSELECT_MASK,
1574 OMAP4_SCRM_AUXCLK1, OMAP4_ENABLE_SHIFT, NULL,
1575 auxclk_src_ck_parents, auxclk_src_ck_ops);
1576
1577DEFINE_CLK_DIVIDER(auxclk1_ck, "auxclk1_src_ck", &auxclk1_src_ck, 0x0,
1578 OMAP4_SCRM_AUXCLK1, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
1579 0x0, NULL);
1580
1581DEFINE_CLK_OMAP_MUX_GATE(auxclk2_src_ck, NULL, auxclk_src_sel,
1582 OMAP4_SCRM_AUXCLK2, OMAP4_SRCSELECT_MASK,
1583 OMAP4_SCRM_AUXCLK2, OMAP4_ENABLE_SHIFT, NULL,
1584 auxclk_src_ck_parents, auxclk_src_ck_ops);
1585
1586DEFINE_CLK_DIVIDER(auxclk2_ck, "auxclk2_src_ck", &auxclk2_src_ck, 0x0,
1587 OMAP4_SCRM_AUXCLK2, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
1588 0x0, NULL);
1589
1590DEFINE_CLK_OMAP_MUX_GATE(auxclk3_src_ck, NULL, auxclk_src_sel,
1591 OMAP4_SCRM_AUXCLK3, OMAP4_SRCSELECT_MASK,
1592 OMAP4_SCRM_AUXCLK3, OMAP4_ENABLE_SHIFT, NULL,
1593 auxclk_src_ck_parents, auxclk_src_ck_ops);
1594
1595DEFINE_CLK_DIVIDER(auxclk3_ck, "auxclk3_src_ck", &auxclk3_src_ck, 0x0,
1596 OMAP4_SCRM_AUXCLK3, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
1597 0x0, NULL);
1598
1599DEFINE_CLK_OMAP_MUX_GATE(auxclk4_src_ck, NULL, auxclk_src_sel,
1600 OMAP4_SCRM_AUXCLK4, OMAP4_SRCSELECT_MASK,
1601 OMAP4_SCRM_AUXCLK4, OMAP4_ENABLE_SHIFT, NULL,
1602 auxclk_src_ck_parents, auxclk_src_ck_ops);
1603
1604DEFINE_CLK_DIVIDER(auxclk4_ck, "auxclk4_src_ck", &auxclk4_src_ck, 0x0,
1605 OMAP4_SCRM_AUXCLK4, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
1606 0x0, NULL);
1607
1608DEFINE_CLK_OMAP_MUX_GATE(auxclk5_src_ck, NULL, auxclk_src_sel,
1609 OMAP4_SCRM_AUXCLK5, OMAP4_SRCSELECT_MASK,
1610 OMAP4_SCRM_AUXCLK5, OMAP4_ENABLE_SHIFT, NULL,
1611 auxclk_src_ck_parents, auxclk_src_ck_ops);
1612
1613DEFINE_CLK_DIVIDER(auxclk5_ck, "auxclk5_src_ck", &auxclk5_src_ck, 0x0,
1614 OMAP4_SCRM_AUXCLK5, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
1615 0x0, NULL);
1616
1617static const char *auxclkreq_ck_parents[] = {
1618 "auxclk0_ck", "auxclk1_ck", "auxclk2_ck", "auxclk3_ck", "auxclk4_ck",
1619 "auxclk5_ck",
1620};
1621
1622DEFINE_CLK_MUX(auxclkreq0_ck, auxclkreq_ck_parents, NULL, 0x0,
1623 OMAP4_SCRM_AUXCLKREQ0, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
1624 0x0, NULL);
1625
1626DEFINE_CLK_MUX(auxclkreq1_ck, auxclkreq_ck_parents, NULL, 0x0,
1627 OMAP4_SCRM_AUXCLKREQ1, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
1628 0x0, NULL);
1629
1630DEFINE_CLK_MUX(auxclkreq2_ck, auxclkreq_ck_parents, NULL, 0x0,
1631 OMAP4_SCRM_AUXCLKREQ2, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
1632 0x0, NULL);
1633
1634DEFINE_CLK_MUX(auxclkreq3_ck, auxclkreq_ck_parents, NULL, 0x0,
1635 OMAP4_SCRM_AUXCLKREQ3, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
1636 0x0, NULL);
1637
1638DEFINE_CLK_MUX(auxclkreq4_ck, auxclkreq_ck_parents, NULL, 0x0,
1639 OMAP4_SCRM_AUXCLKREQ4, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
1640 0x0, NULL);
1641
1642DEFINE_CLK_MUX(auxclkreq5_ck, auxclkreq_ck_parents, NULL, 0x0,
1643 OMAP4_SCRM_AUXCLKREQ5, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
1644 0x0, NULL);
1645
1646/*
1647 * clkdev
1648 */
1649
1650static struct omap_clk omap44xx_clks[] = {
1651 CLK(NULL, "extalt_clkin_ck", &extalt_clkin_ck, CK_443X),
1652 CLK(NULL, "pad_clks_src_ck", &pad_clks_src_ck, CK_443X),
1653 CLK(NULL, "pad_clks_ck", &pad_clks_ck, CK_443X),
1654 CLK(NULL, "pad_slimbus_core_clks_ck", &pad_slimbus_core_clks_ck, CK_443X),
1655 CLK(NULL, "secure_32k_clk_src_ck", &secure_32k_clk_src_ck, CK_443X),
1656 CLK(NULL, "slimbus_src_clk", &slimbus_src_clk, CK_443X),
1657 CLK(NULL, "slimbus_clk", &slimbus_clk, CK_443X),
1658 CLK(NULL, "sys_32k_ck", &sys_32k_ck, CK_443X),
1659 CLK(NULL, "virt_12000000_ck", &virt_12000000_ck, CK_443X),
1660 CLK(NULL, "virt_13000000_ck", &virt_13000000_ck, CK_443X),
1661 CLK(NULL, "virt_16800000_ck", &virt_16800000_ck, CK_443X),
1662 CLK(NULL, "virt_19200000_ck", &virt_19200000_ck, CK_443X),
1663 CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_443X),
1664 CLK(NULL, "virt_27000000_ck", &virt_27000000_ck, CK_443X),
1665 CLK(NULL, "virt_38400000_ck", &virt_38400000_ck, CK_443X),
1666 CLK(NULL, "sys_clkin_ck", &sys_clkin_ck, CK_443X),
1667 CLK(NULL, "tie_low_clock_ck", &tie_low_clock_ck, CK_443X),
1668 CLK(NULL, "utmi_phy_clkout_ck", &utmi_phy_clkout_ck, CK_443X),
1669 CLK(NULL, "xclk60mhsp1_ck", &xclk60mhsp1_ck, CK_443X),
1670 CLK(NULL, "xclk60mhsp2_ck", &xclk60mhsp2_ck, CK_443X),
1671 CLK(NULL, "xclk60motg_ck", &xclk60motg_ck, CK_443X),
1672 CLK(NULL, "abe_dpll_bypass_clk_mux_ck", &abe_dpll_bypass_clk_mux_ck, CK_443X),
1673 CLK(NULL, "abe_dpll_refclk_mux_ck", &abe_dpll_refclk_mux_ck, CK_443X),
1674 CLK(NULL, "dpll_abe_ck", &dpll_abe_ck, CK_443X),
1675 CLK(NULL, "dpll_abe_x2_ck", &dpll_abe_x2_ck, CK_443X),
1676 CLK(NULL, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, CK_443X),
1677 CLK(NULL, "abe_24m_fclk", &abe_24m_fclk, CK_443X),
1678 CLK(NULL, "abe_clk", &abe_clk, CK_443X),
1679 CLK(NULL, "aess_fclk", &aess_fclk, CK_443X),
1680 CLK(NULL, "dpll_abe_m3x2_ck", &dpll_abe_m3x2_ck, CK_443X),
1681 CLK(NULL, "core_hsd_byp_clk_mux_ck", &core_hsd_byp_clk_mux_ck, CK_443X),
1682 CLK(NULL, "dpll_core_ck", &dpll_core_ck, CK_443X),
1683 CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck, CK_443X),
1684 CLK(NULL, "dpll_core_m6x2_ck", &dpll_core_m6x2_ck, CK_443X),
1685 CLK(NULL, "dbgclk_mux_ck", &dbgclk_mux_ck, CK_443X),
1686 CLK(NULL, "dpll_core_m2_ck", &dpll_core_m2_ck, CK_443X),
1687 CLK(NULL, "ddrphy_ck", &ddrphy_ck, CK_443X),
1688 CLK(NULL, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, CK_443X),
1689 CLK(NULL, "div_core_ck", &div_core_ck, CK_443X),
1690 CLK(NULL, "div_iva_hs_clk", &div_iva_hs_clk, CK_443X),
1691 CLK(NULL, "div_mpu_hs_clk", &div_mpu_hs_clk, CK_443X),
1692 CLK(NULL, "dpll_core_m4x2_ck", &dpll_core_m4x2_ck, CK_443X),
1693 CLK(NULL, "dll_clk_div_ck", &dll_clk_div_ck, CK_443X),
1694 CLK(NULL, "dpll_abe_m2_ck", &dpll_abe_m2_ck, CK_443X),
1695 CLK(NULL, "dpll_core_m3x2_ck", &dpll_core_m3x2_ck, CK_443X),
1696 CLK(NULL, "dpll_core_m7x2_ck", &dpll_core_m7x2_ck, CK_443X),
1697 CLK(NULL, "iva_hsd_byp_clk_mux_ck", &iva_hsd_byp_clk_mux_ck, CK_443X),
1698 CLK(NULL, "dpll_iva_ck", &dpll_iva_ck, CK_443X),
1699 CLK(NULL, "dpll_iva_x2_ck", &dpll_iva_x2_ck, CK_443X),
1700 CLK(NULL, "dpll_iva_m4x2_ck", &dpll_iva_m4x2_ck, CK_443X),
1701 CLK(NULL, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck, CK_443X),
1702 CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_443X),
1703 CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_443X),
1704 CLK(NULL, "per_hs_clk_div_ck", &per_hs_clk_div_ck, CK_443X),
1705 CLK(NULL, "per_hsd_byp_clk_mux_ck", &per_hsd_byp_clk_mux_ck, CK_443X),
1706 CLK(NULL, "dpll_per_ck", &dpll_per_ck, CK_443X),
1707 CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck, CK_443X),
1708 CLK(NULL, "dpll_per_x2_ck", &dpll_per_x2_ck, CK_443X),
1709 CLK(NULL, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, CK_443X),
1710 CLK(NULL, "dpll_per_m3x2_ck", &dpll_per_m3x2_ck, CK_443X),
1711 CLK(NULL, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, CK_443X),
1712 CLK(NULL, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, CK_443X),
1713 CLK(NULL, "dpll_per_m6x2_ck", &dpll_per_m6x2_ck, CK_443X),
1714 CLK(NULL, "dpll_per_m7x2_ck", &dpll_per_m7x2_ck, CK_443X),
1715 CLK(NULL, "usb_hs_clk_div_ck", &usb_hs_clk_div_ck, CK_443X),
1716 CLK(NULL, "dpll_usb_ck", &dpll_usb_ck, CK_443X),
1717 CLK(NULL, "dpll_usb_clkdcoldo_ck", &dpll_usb_clkdcoldo_ck, CK_443X),
1718 CLK(NULL, "dpll_usb_m2_ck", &dpll_usb_m2_ck, CK_443X),
1719 CLK(NULL, "ducati_clk_mux_ck", &ducati_clk_mux_ck, CK_443X),
1720 CLK(NULL, "func_12m_fclk", &func_12m_fclk, CK_443X),
1721 CLK(NULL, "func_24m_clk", &func_24m_clk, CK_443X),
1722 CLK(NULL, "func_24mc_fclk", &func_24mc_fclk, CK_443X),
1723 CLK(NULL, "func_48m_fclk", &func_48m_fclk, CK_443X),
1724 CLK(NULL, "func_48mc_fclk", &func_48mc_fclk, CK_443X),
1725 CLK(NULL, "func_64m_fclk", &func_64m_fclk, CK_443X),
1726 CLK(NULL, "func_96m_fclk", &func_96m_fclk, CK_443X),
1727 CLK(NULL, "init_60m_fclk", &init_60m_fclk, CK_443X),
1728 CLK(NULL, "l3_div_ck", &l3_div_ck, CK_443X),
1729 CLK(NULL, "l4_div_ck", &l4_div_ck, CK_443X),
1730 CLK(NULL, "lp_clk_div_ck", &lp_clk_div_ck, CK_443X),
1731 CLK(NULL, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, CK_443X),
1732 CLK("smp_twd", NULL, &mpu_periphclk, CK_443X),
1733 CLK(NULL, "ocp_abe_iclk", &ocp_abe_iclk, CK_443X),
1734 CLK(NULL, "per_abe_24m_fclk", &per_abe_24m_fclk, CK_443X),
1735 CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk, CK_443X),
1736 CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck, CK_443X),
1737 CLK(NULL, "aes1_fck", &aes1_fck, CK_443X),
1738 CLK(NULL, "aes2_fck", &aes2_fck, CK_443X),
1739 CLK(NULL, "aess_fck", &aess_fck, CK_443X),
1740 CLK(NULL, "bandgap_fclk", &bandgap_fclk, CK_443X),
1741 CLK(NULL, "div_ts_ck", &div_ts_ck, CK_446X),
1742 CLK(NULL, "bandgap_ts_fclk", &bandgap_ts_fclk, CK_446X),
1743 CLK(NULL, "des3des_fck", &des3des_fck, CK_443X),
1744 CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X),
1745 CLK(NULL, "dmic_fck", &dmic_fck, CK_443X),
1746 CLK(NULL, "dsp_fck", &dsp_fck, CK_443X),
1747 CLK(NULL, "dss_sys_clk", &dss_sys_clk, CK_443X),
1748 CLK(NULL, "dss_tv_clk", &dss_tv_clk, CK_443X),
1749 CLK(NULL, "dss_dss_clk", &dss_dss_clk, CK_443X),
1750 CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk, CK_443X),
1751 CLK(NULL, "dss_fck", &dss_fck, CK_443X),
1752 CLK("omapdss_dss", "ick", &dss_fck, CK_443X),
1753 CLK(NULL, "efuse_ctrl_cust_fck", &efuse_ctrl_cust_fck, CK_443X),
1754 CLK(NULL, "emif1_fck", &emif1_fck, CK_443X),
1755 CLK(NULL, "emif2_fck", &emif2_fck, CK_443X),
1756 CLK(NULL, "fdif_fck", &fdif_fck, CK_443X),
1757 CLK(NULL, "fpka_fck", &fpka_fck, CK_443X),
1758 CLK(NULL, "gpio1_dbclk", &gpio1_dbclk, CK_443X),
1759 CLK(NULL, "gpio1_ick", &gpio1_ick, CK_443X),
1760 CLK(NULL, "gpio2_dbclk", &gpio2_dbclk, CK_443X),
1761 CLK(NULL, "gpio2_ick", &gpio2_ick, CK_443X),
1762 CLK(NULL, "gpio3_dbclk", &gpio3_dbclk, CK_443X),
1763 CLK(NULL, "gpio3_ick", &gpio3_ick, CK_443X),
1764 CLK(NULL, "gpio4_dbclk", &gpio4_dbclk, CK_443X),
1765 CLK(NULL, "gpio4_ick", &gpio4_ick, CK_443X),
1766 CLK(NULL, "gpio5_dbclk", &gpio5_dbclk, CK_443X),
1767 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_443X),
1768 CLK(NULL, "gpio6_dbclk", &gpio6_dbclk, CK_443X),
1769 CLK(NULL, "gpio6_ick", &gpio6_ick, CK_443X),
1770 CLK(NULL, "gpmc_ick", &gpmc_ick, CK_443X),
1771 CLK(NULL, "gpu_fck", &gpu_fck, CK_443X),
1772 CLK(NULL, "hdq1w_fck", &hdq1w_fck, CK_443X),
1773 CLK(NULL, "hsi_fck", &hsi_fck, CK_443X),
1774 CLK(NULL, "i2c1_fck", &i2c1_fck, CK_443X),
1775 CLK(NULL, "i2c2_fck", &i2c2_fck, CK_443X),
1776 CLK(NULL, "i2c3_fck", &i2c3_fck, CK_443X),
1777 CLK(NULL, "i2c4_fck", &i2c4_fck, CK_443X),
1778 CLK(NULL, "ipu_fck", &ipu_fck, CK_443X),
1779 CLK(NULL, "iss_ctrlclk", &iss_ctrlclk, CK_443X),
1780 CLK(NULL, "iss_fck", &iss_fck, CK_443X),
1781 CLK(NULL, "iva_fck", &iva_fck, CK_443X),
1782 CLK(NULL, "kbd_fck", &kbd_fck, CK_443X),
1783 CLK(NULL, "l3_instr_ick", &l3_instr_ick, CK_443X),
1784 CLK(NULL, "l3_main_3_ick", &l3_main_3_ick, CK_443X),
1785 CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck, CK_443X),
1786 CLK(NULL, "mcasp_fck", &mcasp_fck, CK_443X),
1787 CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck, CK_443X),
1788 CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_443X),
1789 CLK(NULL, "mcbsp2_sync_mux_ck", &mcbsp2_sync_mux_ck, CK_443X),
1790 CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_443X),
1791 CLK(NULL, "mcbsp3_sync_mux_ck", &mcbsp3_sync_mux_ck, CK_443X),
1792 CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_443X),
1793 CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck, CK_443X),
1794 CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_443X),
1795 CLK(NULL, "mcpdm_fck", &mcpdm_fck, CK_443X),
1796 CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_443X),
1797 CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_443X),
1798 CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_443X),
1799 CLK(NULL, "mcspi4_fck", &mcspi4_fck, CK_443X),
1800 CLK(NULL, "mmc1_fck", &mmc1_fck, CK_443X),
1801 CLK(NULL, "mmc2_fck", &mmc2_fck, CK_443X),
1802 CLK(NULL, "mmc3_fck", &mmc3_fck, CK_443X),
1803 CLK(NULL, "mmc4_fck", &mmc4_fck, CK_443X),
1804 CLK(NULL, "mmc5_fck", &mmc5_fck, CK_443X),
1805 CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m, CK_443X),
1806 CLK(NULL, "ocp2scp_usb_phy_ick", &ocp2scp_usb_phy_ick, CK_443X),
1807 CLK(NULL, "ocp_wp_noc_ick", &ocp_wp_noc_ick, CK_443X),
1808 CLK(NULL, "rng_ick", &rng_ick, CK_443X),
1809 CLK("omap_rng", "ick", &rng_ick, CK_443X),
1810 CLK(NULL, "sha2md5_fck", &sha2md5_fck, CK_443X),
1811 CLK(NULL, "sl2if_ick", &sl2if_ick, CK_443X),
1812 CLK(NULL, "slimbus1_fclk_1", &slimbus1_fclk_1, CK_443X),
1813 CLK(NULL, "slimbus1_fclk_0", &slimbus1_fclk_0, CK_443X),
1814 CLK(NULL, "slimbus1_fclk_2", &slimbus1_fclk_2, CK_443X),
1815 CLK(NULL, "slimbus1_slimbus_clk", &slimbus1_slimbus_clk, CK_443X),
1816 CLK(NULL, "slimbus1_fck", &slimbus1_fck, CK_443X),
1817 CLK(NULL, "slimbus2_fclk_1", &slimbus2_fclk_1, CK_443X),
1818 CLK(NULL, "slimbus2_fclk_0", &slimbus2_fclk_0, CK_443X),
1819 CLK(NULL, "slimbus2_slimbus_clk", &slimbus2_slimbus_clk, CK_443X),
1820 CLK(NULL, "slimbus2_fck", &slimbus2_fck, CK_443X),
1821 CLK(NULL, "smartreflex_core_fck", &smartreflex_core_fck, CK_443X),
1822 CLK(NULL, "smartreflex_iva_fck", &smartreflex_iva_fck, CK_443X),
1823 CLK(NULL, "smartreflex_mpu_fck", &smartreflex_mpu_fck, CK_443X),
1824 CLK(NULL, "timer1_fck", &timer1_fck, CK_443X),
1825 CLK(NULL, "timer10_fck", &timer10_fck, CK_443X),
1826 CLK(NULL, "timer11_fck", &timer11_fck, CK_443X),
1827 CLK(NULL, "timer2_fck", &timer2_fck, CK_443X),
1828 CLK(NULL, "timer3_fck", &timer3_fck, CK_443X),
1829 CLK(NULL, "timer4_fck", &timer4_fck, CK_443X),
1830 CLK(NULL, "timer5_fck", &timer5_fck, CK_443X),
1831 CLK(NULL, "timer6_fck", &timer6_fck, CK_443X),
1832 CLK(NULL, "timer7_fck", &timer7_fck, CK_443X),
1833 CLK(NULL, "timer8_fck", &timer8_fck, CK_443X),
1834 CLK(NULL, "timer9_fck", &timer9_fck, CK_443X),
1835 CLK(NULL, "uart1_fck", &uart1_fck, CK_443X),
1836 CLK(NULL, "uart2_fck", &uart2_fck, CK_443X),
1837 CLK(NULL, "uart3_fck", &uart3_fck, CK_443X),
1838 CLK(NULL, "uart4_fck", &uart4_fck, CK_443X),
1839 CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X),
1840 CLK("usbhs_omap", "fs_fck", &usb_host_fs_fck, CK_443X),
1841 CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_443X),
1842 CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk, CK_443X),
1843 CLK(NULL, "utmi_p2_gfclk", &utmi_p2_gfclk, CK_443X),
1844 CLK(NULL, "usb_host_hs_utmi_p2_clk", &usb_host_hs_utmi_p2_clk, CK_443X),
1845 CLK(NULL, "usb_host_hs_utmi_p3_clk", &usb_host_hs_utmi_p3_clk, CK_443X),
1846 CLK(NULL, "usb_host_hs_hsic480m_p1_clk", &usb_host_hs_hsic480m_p1_clk, CK_443X),
1847 CLK(NULL, "usb_host_hs_hsic60m_p1_clk", &usb_host_hs_hsic60m_p1_clk, CK_443X),
1848 CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk, CK_443X),
1849 CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk, CK_443X),
1850 CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk, CK_443X),
1851 CLK(NULL, "usb_host_hs_fck", &usb_host_hs_fck, CK_443X),
1852 CLK("usbhs_omap", "hs_fck", &usb_host_hs_fck, CK_443X),
1853 CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk, CK_443X),
1854 CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk, CK_443X),
1855 CLK(NULL, "usb_otg_hs_ick", &usb_otg_hs_ick, CK_443X),
1856 CLK("musb-omap2430", "ick", &usb_otg_hs_ick, CK_443X),
1857 CLK(NULL, "usb_phy_cm_clk32k", &usb_phy_cm_clk32k, CK_443X),
1858 CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk, CK_443X),
1859 CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk, CK_443X),
1860 CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk, CK_443X),
1861 CLK(NULL, "usb_tll_hs_ick", &usb_tll_hs_ick, CK_443X),
1862 CLK("usbhs_omap", "usbtll_ick", &usb_tll_hs_ick, CK_443X),
1863 CLK("usbhs_tll", "usbtll_ick", &usb_tll_hs_ick, CK_443X),
1864 CLK(NULL, "usim_ck", &usim_ck, CK_443X),
1865 CLK(NULL, "usim_fclk", &usim_fclk, CK_443X),
1866 CLK(NULL, "usim_fck", &usim_fck, CK_443X),
1867 CLK(NULL, "wd_timer2_fck", &wd_timer2_fck, CK_443X),
1868 CLK(NULL, "wd_timer3_fck", &wd_timer3_fck, CK_443X),
1869 CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck, CK_443X),
1870 CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck, CK_443X),
1871 CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X),
1872 CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X),
1873 CLK(NULL, "auxclk0_src_ck", &auxclk0_src_ck, CK_443X),
1874 CLK(NULL, "auxclk0_ck", &auxclk0_ck, CK_443X),
1875 CLK(NULL, "auxclkreq0_ck", &auxclkreq0_ck, CK_443X),
1876 CLK(NULL, "auxclk1_src_ck", &auxclk1_src_ck, CK_443X),
1877 CLK(NULL, "auxclk1_ck", &auxclk1_ck, CK_443X),
1878 CLK(NULL, "auxclkreq1_ck", &auxclkreq1_ck, CK_443X),
1879 CLK(NULL, "auxclk2_src_ck", &auxclk2_src_ck, CK_443X),
1880 CLK(NULL, "auxclk2_ck", &auxclk2_ck, CK_443X),
1881 CLK(NULL, "auxclkreq2_ck", &auxclkreq2_ck, CK_443X),
1882 CLK(NULL, "auxclk3_src_ck", &auxclk3_src_ck, CK_443X),
1883 CLK(NULL, "auxclk3_ck", &auxclk3_ck, CK_443X),
1884 CLK(NULL, "auxclkreq3_ck", &auxclkreq3_ck, CK_443X),
1885 CLK(NULL, "auxclk4_src_ck", &auxclk4_src_ck, CK_443X),
1886 CLK(NULL, "auxclk4_ck", &auxclk4_ck, CK_443X),
1887 CLK(NULL, "auxclkreq4_ck", &auxclkreq4_ck, CK_443X),
1888 CLK(NULL, "auxclk5_src_ck", &auxclk5_src_ck, CK_443X),
1889 CLK(NULL, "auxclk5_ck", &auxclk5_ck, CK_443X),
1890 CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck, CK_443X),
1891 CLK("omap-gpmc", "fck", &dummy_ck, CK_443X),
1892 CLK("omap_i2c.1", "ick", &dummy_ck, CK_443X),
1893 CLK("omap_i2c.2", "ick", &dummy_ck, CK_443X),
1894 CLK("omap_i2c.3", "ick", &dummy_ck, CK_443X),
1895 CLK("omap_i2c.4", "ick", &dummy_ck, CK_443X),
1896 CLK(NULL, "mailboxes_ick", &dummy_ck, CK_443X),
1897 CLK("omap_hsmmc.0", "ick", &dummy_ck, CK_443X),
1898 CLK("omap_hsmmc.1", "ick", &dummy_ck, CK_443X),
1899 CLK("omap_hsmmc.2", "ick", &dummy_ck, CK_443X),
1900 CLK("omap_hsmmc.3", "ick", &dummy_ck, CK_443X),
1901 CLK("omap_hsmmc.4", "ick", &dummy_ck, CK_443X),
1902 CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_443X),
1903 CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_443X),
1904 CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_443X),
1905 CLK("omap-mcbsp.4", "ick", &dummy_ck, CK_443X),
1906 CLK("omap2_mcspi.1", "ick", &dummy_ck, CK_443X),
1907 CLK("omap2_mcspi.2", "ick", &dummy_ck, CK_443X),
1908 CLK("omap2_mcspi.3", "ick", &dummy_ck, CK_443X),
1909 CLK("omap2_mcspi.4", "ick", &dummy_ck, CK_443X),
1910 CLK(NULL, "uart1_ick", &dummy_ck, CK_443X),
1911 CLK(NULL, "uart2_ick", &dummy_ck, CK_443X),
1912 CLK(NULL, "uart3_ick", &dummy_ck, CK_443X),
1913 CLK(NULL, "uart4_ick", &dummy_ck, CK_443X),
1914 CLK("usbhs_omap", "usbhost_ick", &dummy_ck, CK_443X),
1915 CLK("usbhs_omap", "usbtll_fck", &dummy_ck, CK_443X),
1916 CLK("usbhs_tll", "usbtll_fck", &dummy_ck, CK_443X),
1917 CLK("omap_wdt", "ick", &dummy_ck, CK_443X),
1918 CLK(NULL, "timer_32k_ck", &sys_32k_ck, CK_443X),
1919 /* TODO: Remove "omap_timer.X" aliases once DT migration is complete */
1920 CLK("omap_timer.1", "timer_sys_ck", &sys_clkin_ck, CK_443X),
1921 CLK("omap_timer.2", "timer_sys_ck", &sys_clkin_ck, CK_443X),
1922 CLK("omap_timer.3", "timer_sys_ck", &sys_clkin_ck, CK_443X),
1923 CLK("omap_timer.4", "timer_sys_ck", &sys_clkin_ck, CK_443X),
1924 CLK("omap_timer.9", "timer_sys_ck", &sys_clkin_ck, CK_443X),
1925 CLK("omap_timer.10", "timer_sys_ck", &sys_clkin_ck, CK_443X),
1926 CLK("omap_timer.11", "timer_sys_ck", &sys_clkin_ck, CK_443X),
1927 CLK("omap_timer.5", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
1928 CLK("omap_timer.6", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
1929 CLK("omap_timer.7", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
1930 CLK("omap_timer.8", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
1931 CLK("4a318000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X),
1932 CLK("48032000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X),
1933 CLK("48034000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X),
1934 CLK("48036000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X),
1935 CLK("4803e000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X),
1936 CLK("48086000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X),
1937 CLK("48088000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X),
1938 CLK("49038000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
1939 CLK("4903a000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
1940 CLK("4903c000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
1941 CLK("4903e000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
1942 CLK(NULL, "cpufreq_ck", &dpll_mpu_ck, CK_443X),
1943};
1944
1945static const char *enable_init_clks[] = {
1946 "emif1_fck",
1947 "emif2_fck",
1948 "gpmc_ick",
1949 "l3_instr_ick",
1950 "l3_main_3_ick",
1951 "ocp_wp_noc_ick",
1952};
1953
1954int __init omap4xxx_clk_init(void)
1955{
1956 u32 cpu_clkflg;
1957 struct omap_clk *c;
1958
1959 if (cpu_is_omap443x()) {
1960 cpu_mask = RATE_IN_4430;
1961 cpu_clkflg = CK_443X;
1962 } else if (cpu_is_omap446x() || cpu_is_omap447x()) {
1963 cpu_mask = RATE_IN_4460 | RATE_IN_4430;
1964 cpu_clkflg = CK_446X | CK_443X;
1965
1966 if (cpu_is_omap447x())
1967 pr_warn("WARNING: OMAP4470 clock data incomplete!\n");
1968 } else {
1969 return 0;
1970 }
1971
1972 for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks);
1973 c++) {
1974 if (c->cpu & cpu_clkflg) {
1975 clkdev_add(&c->lk);
1976 if (!__clk_init(NULL, c->lk.clk))
1977 omap2_init_clk_hw_omap_clocks(c->lk.clk);
1978 }
1979 }
1980
1981 omap2_clk_disable_autoidle_all();
1982
1983 omap2_clk_enable_init_clocks(enable_init_clks,
1984 ARRAY_SIZE(enable_init_clks));
1985
1986 return 0;
1987}
diff --git a/arch/arm/mach-omap2/clkt2xxx_apll.c b/arch/arm/mach-omap2/clkt2xxx_apll.c
index 8c5b13e7ee61..25b1feed480d 100644
--- a/arch/arm/mach-omap2/clkt2xxx_apll.c
+++ b/arch/arm/mach-omap2/clkt2xxx_apll.c
@@ -38,62 +38,88 @@
38 38
39/* Private functions */ 39/* Private functions */
40 40
41static int _apll96_enable(struct clk *clk) 41/**
42 * omap2xxx_clk_apll_locked - is the APLL locked?
43 * @hw: struct clk_hw * of the APLL to check
44 *
45 * If the APLL IP block referred to by @hw indicates that it's locked,
46 * return true; otherwise, return false.
47 */
48static bool omap2xxx_clk_apll_locked(struct clk_hw *hw)
49{
50 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
51 u32 r, apll_mask;
52
53 apll_mask = EN_APLL_LOCKED << clk->enable_bit;
54
55 r = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
56
57 return ((r & apll_mask) == apll_mask) ? true : false;
58}
59
60int omap2_clk_apll96_enable(struct clk_hw *hw)
42{ 61{
43 return omap2xxx_cm_apll96_enable(); 62 return omap2xxx_cm_apll96_enable();
44} 63}
45 64
46static int _apll54_enable(struct clk *clk) 65int omap2_clk_apll54_enable(struct clk_hw *hw)
47{ 66{
48 return omap2xxx_cm_apll54_enable(); 67 return omap2xxx_cm_apll54_enable();
49} 68}
50 69
51static void _apll96_allow_idle(struct clk *clk) 70static void _apll96_allow_idle(struct clk_hw_omap *clk)
52{ 71{
53 omap2xxx_cm_set_apll96_auto_low_power_stop(); 72 omap2xxx_cm_set_apll96_auto_low_power_stop();
54} 73}
55 74
56static void _apll96_deny_idle(struct clk *clk) 75static void _apll96_deny_idle(struct clk_hw_omap *clk)
57{ 76{
58 omap2xxx_cm_set_apll96_disable_autoidle(); 77 omap2xxx_cm_set_apll96_disable_autoidle();
59} 78}
60 79
61static void _apll54_allow_idle(struct clk *clk) 80static void _apll54_allow_idle(struct clk_hw_omap *clk)
62{ 81{
63 omap2xxx_cm_set_apll54_auto_low_power_stop(); 82 omap2xxx_cm_set_apll54_auto_low_power_stop();
64} 83}
65 84
66static void _apll54_deny_idle(struct clk *clk) 85static void _apll54_deny_idle(struct clk_hw_omap *clk)
67{ 86{
68 omap2xxx_cm_set_apll54_disable_autoidle(); 87 omap2xxx_cm_set_apll54_disable_autoidle();
69} 88}
70 89
71static void _apll96_disable(struct clk *clk) 90void omap2_clk_apll96_disable(struct clk_hw *hw)
72{ 91{
73 omap2xxx_cm_apll96_disable(); 92 omap2xxx_cm_apll96_disable();
74} 93}
75 94
76static void _apll54_disable(struct clk *clk) 95void omap2_clk_apll54_disable(struct clk_hw *hw)
77{ 96{
78 omap2xxx_cm_apll54_disable(); 97 omap2xxx_cm_apll54_disable();
79} 98}
80 99
81/* Public data */ 100unsigned long omap2_clk_apll54_recalc(struct clk_hw *hw,
101 unsigned long parent_rate)
102{
103 return (omap2xxx_clk_apll_locked(hw)) ? 54000000 : 0;
104}
82 105
83const struct clkops clkops_apll96 = { 106unsigned long omap2_clk_apll96_recalc(struct clk_hw *hw,
84 .enable = _apll96_enable, 107 unsigned long parent_rate)
85 .disable = _apll96_disable, 108{
86 .allow_idle = _apll96_allow_idle, 109 return (omap2xxx_clk_apll_locked(hw)) ? 96000000 : 0;
87 .deny_idle = _apll96_deny_idle, 110}
88};
89 111
90const struct clkops clkops_apll54 = { 112/* Public data */
91 .enable = _apll54_enable, 113const struct clk_hw_omap_ops clkhwops_apll54 = {
92 .disable = _apll54_disable,
93 .allow_idle = _apll54_allow_idle, 114 .allow_idle = _apll54_allow_idle,
94 .deny_idle = _apll54_deny_idle, 115 .deny_idle = _apll54_deny_idle,
95}; 116};
96 117
118const struct clk_hw_omap_ops clkhwops_apll96 = {
119 .allow_idle = _apll96_allow_idle,
120 .deny_idle = _apll96_deny_idle,
121};
122
97/* Public functions */ 123/* Public functions */
98 124
99u32 omap2xxx_get_apll_clkin(void) 125u32 omap2xxx_get_apll_clkin(void)
diff --git a/arch/arm/mach-omap2/clkt2xxx_dpll.c b/arch/arm/mach-omap2/clkt2xxx_dpll.c
index 399534c7843b..82572e277b97 100644
--- a/arch/arm/mach-omap2/clkt2xxx_dpll.c
+++ b/arch/arm/mach-omap2/clkt2xxx_dpll.c
@@ -29,7 +29,7 @@
29 * REVISIT: DPLL can optionally enter low-power bypass by writing 0x1 29 * REVISIT: DPLL can optionally enter low-power bypass by writing 0x1
30 * instead. Add some mechanism to optionally enter this mode. 30 * instead. Add some mechanism to optionally enter this mode.
31 */ 31 */
32static void _allow_idle(struct clk *clk) 32static void _allow_idle(struct clk_hw_omap *clk)
33{ 33{
34 if (!clk || !clk->dpll_data) 34 if (!clk || !clk->dpll_data)
35 return; 35 return;
@@ -43,7 +43,7 @@ static void _allow_idle(struct clk *clk)
43 * 43 *
44 * Disable DPLL automatic idle control. No return value. 44 * Disable DPLL automatic idle control. No return value.
45 */ 45 */
46static void _deny_idle(struct clk *clk) 46static void _deny_idle(struct clk_hw_omap *clk)
47{ 47{
48 if (!clk || !clk->dpll_data) 48 if (!clk || !clk->dpll_data)
49 return; 49 return;
@@ -53,9 +53,7 @@ static void _deny_idle(struct clk *clk)
53 53
54 54
55/* Public data */ 55/* Public data */
56 56const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll = {
57const struct clkops clkops_omap2xxx_dpll_ops = {
58 .allow_idle = _allow_idle, 57 .allow_idle = _allow_idle,
59 .deny_idle = _deny_idle, 58 .deny_idle = _deny_idle,
60}; 59};
61
diff --git a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c
index 825e44cdf1cf..d8620105c42a 100644
--- a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c
+++ b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c
@@ -40,7 +40,7 @@
40 * (currently defined as "dpll_ck" in the OMAP2xxx clock tree). Set 40 * (currently defined as "dpll_ck" in the OMAP2xxx clock tree). Set
41 * during dpll_ck init and used later by omap2xxx_clk_get_core_rate(). 41 * during dpll_ck init and used later by omap2xxx_clk_get_core_rate().
42 */ 42 */
43static struct clk *dpll_core_ck; 43static struct clk_hw_omap *dpll_core_ck;
44 44
45/** 45/**
46 * omap2xxx_clk_get_core_rate - return the CORE_CLK rate 46 * omap2xxx_clk_get_core_rate - return the CORE_CLK rate
@@ -104,13 +104,16 @@ static long omap2_dpllcore_round_rate(unsigned long target_rate)
104 104
105} 105}
106 106
107unsigned long omap2_dpllcore_recalc(struct clk *clk) 107unsigned long omap2_dpllcore_recalc(struct clk_hw *hw,
108 unsigned long parent_rate)
108{ 109{
109 return omap2xxx_clk_get_core_rate(); 110 return omap2xxx_clk_get_core_rate();
110} 111}
111 112
112int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate) 113int omap2_reprogram_dpllcore(struct clk_hw *hw, unsigned long rate,
114 unsigned long parent_rate)
113{ 115{
116 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
114 u32 cur_rate, low, mult, div, valid_rate, done_rate; 117 u32 cur_rate, low, mult, div, valid_rate, done_rate;
115 u32 bypass = 0; 118 u32 bypass = 0;
116 struct prcm_config tmpset; 119 struct prcm_config tmpset;
@@ -188,8 +191,8 @@ int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
188 * statically defined, this code may need to change to increment some 191 * statically defined, this code may need to change to increment some
189 * kind of use count on dpll_ck. 192 * kind of use count on dpll_ck.
190 */ 193 */
191void omap2xxx_clkt_dpllcore_init(struct clk *clk) 194void omap2xxx_clkt_dpllcore_init(struct clk_hw *hw)
192{ 195{
193 WARN(dpll_core_ck, "dpll_core_ck already set - should never happen"); 196 WARN(dpll_core_ck, "dpll_core_ck already set - should never happen");
194 dpll_core_ck = clk; 197 dpll_core_ck = to_clk_hw_omap(hw);
195} 198}
diff --git a/arch/arm/mach-omap2/clkt2xxx_osc.c b/arch/arm/mach-omap2/clkt2xxx_osc.c
index e1777371bb5e..19f54d433490 100644
--- a/arch/arm/mach-omap2/clkt2xxx_osc.c
+++ b/arch/arm/mach-omap2/clkt2xxx_osc.c
@@ -35,7 +35,7 @@
35 * clk_enable/clk_disable()-based usecounting for osc_ck should be 35 * clk_enable/clk_disable()-based usecounting for osc_ck should be
36 * replaced with autoidle-based usecounting. 36 * replaced with autoidle-based usecounting.
37 */ 37 */
38static int omap2_enable_osc_ck(struct clk *clk) 38int omap2_enable_osc_ck(struct clk_hw *clk)
39{ 39{
40 u32 pcc; 40 u32 pcc;
41 41
@@ -53,7 +53,7 @@ static int omap2_enable_osc_ck(struct clk *clk)
53 * clk_enable/clk_disable()-based usecounting for osc_ck should be 53 * clk_enable/clk_disable()-based usecounting for osc_ck should be
54 * replaced with autoidle-based usecounting. 54 * replaced with autoidle-based usecounting.
55 */ 55 */
56static void omap2_disable_osc_ck(struct clk *clk) 56void omap2_disable_osc_ck(struct clk_hw *clk)
57{ 57{
58 u32 pcc; 58 u32 pcc;
59 59
@@ -62,13 +62,8 @@ static void omap2_disable_osc_ck(struct clk *clk)
62 __raw_writel(pcc | OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl); 62 __raw_writel(pcc | OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl);
63} 63}
64 64
65const struct clkops clkops_oscck = { 65unsigned long omap2_osc_clk_recalc(struct clk_hw *clk,
66 .enable = omap2_enable_osc_ck, 66 unsigned long parent_rate)
67 .disable = omap2_disable_osc_ck,
68};
69
70unsigned long omap2_osc_clk_recalc(struct clk *clk)
71{ 67{
72 return omap2xxx_get_apll_clkin() * omap2xxx_get_sysclkdiv(); 68 return omap2xxx_get_apll_clkin() * omap2xxx_get_sysclkdiv();
73} 69}
74
diff --git a/arch/arm/mach-omap2/clkt2xxx_sys.c b/arch/arm/mach-omap2/clkt2xxx_sys.c
index 46683b3c2461..f467d072cd02 100644
--- a/arch/arm/mach-omap2/clkt2xxx_sys.c
+++ b/arch/arm/mach-omap2/clkt2xxx_sys.c
@@ -40,9 +40,8 @@ u32 omap2xxx_get_sysclkdiv(void)
40 return div; 40 return div;
41} 41}
42 42
43unsigned long omap2xxx_sys_clk_recalc(struct clk *clk) 43unsigned long omap2xxx_sys_clk_recalc(struct clk_hw *clk,
44 unsigned long parent_rate)
44{ 45{
45 return clk->parent->rate / omap2xxx_get_sysclkdiv(); 46 return parent_rate / omap2xxx_get_sysclkdiv();
46} 47}
47
48
diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
index 1c2041fbd718..ae2b35e76dc8 100644
--- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
+++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
@@ -58,7 +58,8 @@ static unsigned long sys_ck_rate;
58 * 58 *
59 * Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set. 59 * Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set.
60 */ 60 */
61unsigned long omap2_table_mpu_recalc(struct clk *clk) 61unsigned long omap2_table_mpu_recalc(struct clk_hw *clk,
62 unsigned long parent_rate)
62{ 63{
63 return curr_prcm_set->mpu_speed; 64 return curr_prcm_set->mpu_speed;
64} 65}
@@ -70,7 +71,8 @@ unsigned long omap2_table_mpu_recalc(struct clk *clk)
70 * Some might argue L3-DDR, others ARM, others IVA. This code is simple and 71 * Some might argue L3-DDR, others ARM, others IVA. This code is simple and
71 * just uses the ARM rates. 72 * just uses the ARM rates.
72 */ 73 */
73long omap2_round_to_table_rate(struct clk *clk, unsigned long rate) 74long omap2_round_to_table_rate(struct clk_hw *hw, unsigned long rate,
75 unsigned long *parent_rate)
74{ 76{
75 const struct prcm_config *ptr; 77 const struct prcm_config *ptr;
76 long highest_rate; 78 long highest_rate;
@@ -93,7 +95,8 @@ long omap2_round_to_table_rate(struct clk *clk, unsigned long rate)
93} 95}
94 96
95/* Sets basic clocks based on the specified rate */ 97/* Sets basic clocks based on the specified rate */
96int omap2_select_table_rate(struct clk *clk, unsigned long rate) 98int omap2_select_table_rate(struct clk_hw *hw, unsigned long rate,
99 unsigned long parent_rate)
97{ 100{
98 u32 cur_rate, done_rate, bypass = 0, tmp; 101 u32 cur_rate, done_rate, bypass = 0, tmp;
99 const struct prcm_config *prcm; 102 const struct prcm_config *prcm;
diff --git a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
index 6cf298e262f6..eb69acf21014 100644
--- a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
+++ b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
@@ -44,8 +44,10 @@
44 * Program the DPLL M2 divider with the rounded target rate. Returns 44 * Program the DPLL M2 divider with the rounded target rate. Returns
45 * -EINVAL upon error, or 0 upon success. 45 * -EINVAL upon error, or 0 upon success.
46 */ 46 */
47int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) 47int omap3_core_dpll_m2_set_rate(struct clk_hw *hw, unsigned long rate,
48 unsigned long parent_rate)
48{ 49{
50 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
49 u32 new_div = 0; 51 u32 new_div = 0;
50 u32 unlock_dll = 0; 52 u32 unlock_dll = 0;
51 u32 c; 53 u32 c;
@@ -63,7 +65,7 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
63 return -EINVAL; 65 return -EINVAL;
64 66
65 sdrcrate = __clk_get_rate(sdrc_ick_p); 67 sdrcrate = __clk_get_rate(sdrc_ick_p);
66 clkrate = __clk_get_rate(clk); 68 clkrate = __clk_get_rate(hw->clk);
67 if (rate > clkrate) 69 if (rate > clkrate)
68 sdrcrate <<= ((rate / clkrate) >> 1); 70 sdrcrate <<= ((rate / clkrate) >> 1);
69 else 71 else
@@ -112,8 +114,6 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
112 sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla, 114 sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
113 sdrc_cs0->actim_ctrlb, sdrc_cs0->mr, 115 sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
114 0, 0, 0, 0); 116 0, 0, 0, 0);
115 clk->rate = rate;
116
117 return 0; 117 return 0;
118} 118}
119 119
diff --git a/arch/arm/mach-omap2/clkt_clksel.c b/arch/arm/mach-omap2/clkt_clksel.c
index 53646facda45..0ec9f6fdf046 100644
--- a/arch/arm/mach-omap2/clkt_clksel.c
+++ b/arch/arm/mach-omap2/clkt_clksel.c
@@ -41,7 +41,7 @@
41 41
42#include <linux/kernel.h> 42#include <linux/kernel.h>
43#include <linux/errno.h> 43#include <linux/errno.h>
44#include <linux/clk.h> 44#include <linux/clk-provider.h>
45#include <linux/io.h> 45#include <linux/io.h>
46#include <linux/bug.h> 46#include <linux/bug.h>
47 47
@@ -58,11 +58,14 @@
58 * the element associated with the supplied parent clock address. 58 * the element associated with the supplied parent clock address.
59 * Returns a pointer to the struct clksel on success or NULL on error. 59 * Returns a pointer to the struct clksel on success or NULL on error.
60 */ 60 */
61static const struct clksel *_get_clksel_by_parent(struct clk *clk, 61static const struct clksel *_get_clksel_by_parent(struct clk_hw_omap *clk,
62 struct clk *src_clk) 62 struct clk *src_clk)
63{ 63{
64 const struct clksel *clks; 64 const struct clksel *clks;
65 65
66 if (!src_clk)
67 return NULL;
68
66 for (clks = clk->clksel; clks->parent; clks++) 69 for (clks = clk->clksel; clks->parent; clks++)
67 if (clks->parent == src_clk) 70 if (clks->parent == src_clk)
68 break; /* Found the requested parent */ 71 break; /* Found the requested parent */
@@ -70,7 +73,7 @@ static const struct clksel *_get_clksel_by_parent(struct clk *clk,
70 if (!clks->parent) { 73 if (!clks->parent) {
71 /* This indicates a data problem */ 74 /* This indicates a data problem */
72 WARN(1, "clock: %s: could not find parent clock %s in clksel array\n", 75 WARN(1, "clock: %s: could not find parent clock %s in clksel array\n",
73 __clk_get_name(clk), __clk_get_name(src_clk)); 76 __clk_get_name(clk->hw.clk), __clk_get_name(src_clk));
74 return NULL; 77 return NULL;
75 } 78 }
76 79
@@ -78,64 +81,6 @@ static const struct clksel *_get_clksel_by_parent(struct clk *clk,
78} 81}
79 82
80/** 83/**
81 * _get_div_and_fieldval() - find the new clksel divisor and field value to use
82 * @src_clk: planned new parent struct clk *
83 * @clk: struct clk * that is being reparented
84 * @field_val: pointer to a u32 to contain the register data for the divisor
85 *
86 * Given an intended new parent struct clk * @src_clk, and the struct
87 * clk * @clk to the clock that is being reparented, find the
88 * appropriate rate divisor for the new clock (returned as the return
89 * value), and the corresponding register bitfield data to program to
90 * reach that divisor (returned in the u32 pointed to by @field_val).
91 * Returns 0 on error, or returns the newly-selected divisor upon
92 * success (in this latter case, the corresponding register bitfield
93 * value is passed back in the variable pointed to by @field_val)
94 */
95static u8 _get_div_and_fieldval(struct clk *src_clk, struct clk *clk,
96 u32 *field_val)
97{
98 const struct clksel *clks;
99 const struct clksel_rate *clkr, *max_clkr = NULL;
100 u8 max_div = 0;
101
102 clks = _get_clksel_by_parent(clk, src_clk);
103 if (!clks)
104 return 0;
105
106 /*
107 * Find the highest divisor (e.g., the one resulting in the
108 * lowest rate) to use as the default. This should avoid
109 * clock rates that are too high for the device. XXX A better
110 * solution here would be to try to determine if there is a
111 * divisor matching the original clock rate before the parent
112 * switch, and if it cannot be found, to fall back to the
113 * highest divisor.
114 */
115 for (clkr = clks->rates; clkr->div; clkr++) {
116 if (!(clkr->flags & cpu_mask))
117 continue;
118
119 if (clkr->div > max_div) {
120 max_div = clkr->div;
121 max_clkr = clkr;
122 }
123 }
124
125 if (max_div == 0) {
126 /* This indicates an error in the clksel data */
127 WARN(1, "clock: %s: could not find divisor for parent %s\n",
128 __clk_get_name(clk),
129 __clk_get_name(__clk_get_parent(src_clk)));
130 return 0;
131 }
132
133 *field_val = max_clkr->val;
134
135 return max_div;
136}
137
138/**
139 * _write_clksel_reg() - program a clock's clksel register in hardware 84 * _write_clksel_reg() - program a clock's clksel register in hardware
140 * @clk: struct clk * to program 85 * @clk: struct clk * to program
141 * @v: clksel bitfield value to program (with LSB at bit 0) 86 * @v: clksel bitfield value to program (with LSB at bit 0)
@@ -148,7 +93,7 @@ static u8 _get_div_and_fieldval(struct clk *src_clk, struct clk *clk,
148 * take into account any time the hardware might take to switch the 93 * take into account any time the hardware might take to switch the
149 * clock source. 94 * clock source.
150 */ 95 */
151static void _write_clksel_reg(struct clk *clk, u32 field_val) 96static void _write_clksel_reg(struct clk_hw_omap *clk, u32 field_val)
152{ 97{
153 u32 v; 98 u32 v;
154 99
@@ -171,13 +116,14 @@ static void _write_clksel_reg(struct clk *clk, u32 field_val)
171 * before calling. Returns 0 on error or returns the actual integer divisor 116 * before calling. Returns 0 on error or returns the actual integer divisor
172 * upon success. 117 * upon success.
173 */ 118 */
174static u32 _clksel_to_divisor(struct clk *clk, u32 field_val) 119static u32 _clksel_to_divisor(struct clk_hw_omap *clk, u32 field_val)
175{ 120{
176 const struct clksel *clks; 121 const struct clksel *clks;
177 const struct clksel_rate *clkr; 122 const struct clksel_rate *clkr;
178 struct clk *parent; 123 struct clk *parent;
179 124
180 parent = __clk_get_parent(clk); 125 parent = __clk_get_parent(clk->hw.clk);
126
181 clks = _get_clksel_by_parent(clk, parent); 127 clks = _get_clksel_by_parent(clk, parent);
182 if (!clks) 128 if (!clks)
183 return 0; 129 return 0;
@@ -193,7 +139,8 @@ static u32 _clksel_to_divisor(struct clk *clk, u32 field_val)
193 if (!clkr->div) { 139 if (!clkr->div) {
194 /* This indicates a data error */ 140 /* This indicates a data error */
195 WARN(1, "clock: %s: could not find fieldval %d for parent %s\n", 141 WARN(1, "clock: %s: could not find fieldval %d for parent %s\n",
196 __clk_get_name(clk), field_val, __clk_get_name(parent)); 142 __clk_get_name(clk->hw.clk), field_val,
143 __clk_get_name(parent));
197 return 0; 144 return 0;
198 } 145 }
199 146
@@ -210,7 +157,7 @@ static u32 _clksel_to_divisor(struct clk *clk, u32 field_val)
210 * register field value _before_ left-shifting (i.e., LSB is at bit 157 * register field value _before_ left-shifting (i.e., LSB is at bit
211 * 0); or returns 0xFFFFFFFF (~0) upon error. 158 * 0); or returns 0xFFFFFFFF (~0) upon error.
212 */ 159 */
213static u32 _divisor_to_clksel(struct clk *clk, u32 div) 160static u32 _divisor_to_clksel(struct clk_hw_omap *clk, u32 div)
214{ 161{
215 const struct clksel *clks; 162 const struct clksel *clks;
216 const struct clksel_rate *clkr; 163 const struct clksel_rate *clkr;
@@ -219,7 +166,7 @@ static u32 _divisor_to_clksel(struct clk *clk, u32 div)
219 /* should never happen */ 166 /* should never happen */
220 WARN_ON(div == 0); 167 WARN_ON(div == 0);
221 168
222 parent = __clk_get_parent(clk); 169 parent = __clk_get_parent(clk->hw.clk);
223 clks = _get_clksel_by_parent(clk, parent); 170 clks = _get_clksel_by_parent(clk, parent);
224 if (!clks) 171 if (!clks)
225 return ~0; 172 return ~0;
@@ -234,7 +181,8 @@ static u32 _divisor_to_clksel(struct clk *clk, u32 div)
234 181
235 if (!clkr->div) { 182 if (!clkr->div) {
236 pr_err("clock: %s: could not find divisor %d for parent %s\n", 183 pr_err("clock: %s: could not find divisor %d for parent %s\n",
237 __clk_get_name(clk), div, __clk_get_name(parent)); 184 __clk_get_name(clk->hw.clk), div,
185 __clk_get_name(parent));
238 return ~0; 186 return ~0;
239 } 187 }
240 188
@@ -249,7 +197,7 @@ static u32 _divisor_to_clksel(struct clk *clk, u32 div)
249 * into the hardware, convert it into the actual divisor value, and 197 * into the hardware, convert it into the actual divisor value, and
250 * return it; or return 0 on error. 198 * return it; or return 0 on error.
251 */ 199 */
252static u32 _read_divisor(struct clk *clk) 200static u32 _read_divisor(struct clk_hw_omap *clk)
253{ 201{
254 u32 v; 202 u32 v;
255 203
@@ -277,7 +225,8 @@ static u32 _read_divisor(struct clk *clk)
277 * 225 *
278 * Returns the rounded clock rate or returns 0xffffffff on error. 226 * Returns the rounded clock rate or returns 0xffffffff on error.
279 */ 227 */
280u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, 228u32 omap2_clksel_round_rate_div(struct clk_hw_omap *clk,
229 unsigned long target_rate,
281 u32 *new_div) 230 u32 *new_div)
282{ 231{
283 unsigned long test_rate; 232 unsigned long test_rate;
@@ -288,9 +237,9 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
288 unsigned long parent_rate; 237 unsigned long parent_rate;
289 const char *clk_name; 238 const char *clk_name;
290 239
291 parent = __clk_get_parent(clk); 240 parent = __clk_get_parent(clk->hw.clk);
241 clk_name = __clk_get_name(clk->hw.clk);
292 parent_rate = __clk_get_rate(parent); 242 parent_rate = __clk_get_rate(parent);
293 clk_name = __clk_get_name(clk);
294 243
295 if (!clk->clksel || !clk->clksel_mask) 244 if (!clk->clksel || !clk->clksel_mask)
296 return ~0; 245 return ~0;
@@ -341,27 +290,35 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
341 */ 290 */
342 291
343/** 292/**
344 * omap2_init_clksel_parent() - set a clksel clk's parent field from the hdwr 293 * omap2_clksel_find_parent_index() - return the array index of the current
345 * @clk: OMAP clock struct ptr to use 294 * hardware parent of @hw
295 * @hw: struct clk_hw * to find the current hardware parent of
346 * 296 *
347 * Given a pointer @clk to a source-selectable struct clk, read the 297 * Given a struct clk_hw pointer @hw to the 'hw' member of a struct
348 * hardware register and determine what its parent is currently set 298 * clk_hw_omap record representing a source-selectable hardware clock,
349 * to. Update @clk's .parent field with the appropriate clk ptr. No 299 * read the hardware register and determine what its parent is
350 * return value. 300 * currently set to. Intended to be called only by the common clock
301 * framework struct clk_hw_ops.get_parent function pointer. Return
302 * the array index of this parent clock upon success -- there is no
303 * way to return an error, so if we encounter an error, just WARN()
304 * and pretend that we know that we're doing.
351 */ 305 */
352void omap2_init_clksel_parent(struct clk *clk) 306u8 omap2_clksel_find_parent_index(struct clk_hw *hw)
353{ 307{
308 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
354 const struct clksel *clks; 309 const struct clksel *clks;
355 const struct clksel_rate *clkr; 310 const struct clksel_rate *clkr;
356 u32 r, found = 0; 311 u32 r, found = 0;
357 struct clk *parent; 312 struct clk *parent;
358 const char *clk_name; 313 const char *clk_name;
314 int ret = 0, f = 0;
359 315
360 if (!clk->clksel || !clk->clksel_mask) 316 parent = __clk_get_parent(hw->clk);
361 return; 317 clk_name = __clk_get_name(hw->clk);
362 318
363 parent = __clk_get_parent(clk); 319 /* XXX should be able to return an error */
364 clk_name = __clk_get_name(clk); 320 WARN((!clk->clksel || !clk->clksel_mask),
321 "clock: %s: attempt to call on a non-clksel clock", clk_name);
365 322
366 r = __raw_readl(clk->clksel_reg) & clk->clksel_mask; 323 r = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
367 r >>= __ffs(clk->clksel_mask); 324 r >>= __ffs(clk->clksel_mask);
@@ -372,27 +329,21 @@ void omap2_init_clksel_parent(struct clk *clk)
372 continue; 329 continue;
373 330
374 if (clkr->val == r) { 331 if (clkr->val == r) {
375 if (parent != clks->parent) {
376 pr_debug("clock: %s: inited parent to %s (was %s)\n",
377 clk_name,
378 __clk_get_name(clks->parent),
379 ((parent) ?
380 __clk_get_name(parent) :
381 "NULL"));
382 clk_reparent(clk, clks->parent);
383 }
384 found = 1; 332 found = 1;
333 ret = f;
385 } 334 }
386 } 335 }
336 f++;
387 } 337 }
388 338
389 /* This indicates a data error */ 339 /* This indicates a data error */
390 WARN(!found, "clock: %s: init parent: could not find regval %0x\n", 340 WARN(!found, "clock: %s: init parent: could not find regval %0x\n",
391 clk_name, r); 341 clk_name, r);
392 342
393 return; 343 return ret;
394} 344}
395 345
346
396/** 347/**
397 * omap2_clksel_recalc() - function ptr to pass via struct clk .recalc field 348 * omap2_clksel_recalc() - function ptr to pass via struct clk .recalc field
398 * @clk: struct clk * 349 * @clk: struct clk *
@@ -402,21 +353,23 @@ void omap2_init_clksel_parent(struct clk *clk)
402 * function. Returns the clock's current rate, based on its parent's rate 353 * function. Returns the clock's current rate, based on its parent's rate
403 * and its current divisor setting in the hardware. 354 * and its current divisor setting in the hardware.
404 */ 355 */
405unsigned long omap2_clksel_recalc(struct clk *clk) 356unsigned long omap2_clksel_recalc(struct clk_hw *hw, unsigned long parent_rate)
406{ 357{
407 unsigned long rate; 358 unsigned long rate;
408 u32 div = 0; 359 u32 div = 0;
409 struct clk *parent; 360 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
410 361
411 div = _read_divisor(clk); 362 if (!parent_rate)
412 if (div == 0) 363 return 0;
413 return __clk_get_rate(clk);
414 364
415 parent = __clk_get_parent(clk); 365 div = _read_divisor(clk);
416 rate = __clk_get_rate(parent) / div; 366 if (!div)
367 rate = parent_rate;
368 else
369 rate = parent_rate / div;
417 370
418 pr_debug("clock: %s: recalc'd rate is %ld (div %d)\n", 371 pr_debug("%s: recalc'd %s's rate to %lu (div %d)\n", __func__,
419 __clk_get_name(clk), rate, div); 372 __clk_get_name(hw->clk), rate, div);
420 373
421 return rate; 374 return rate;
422} 375}
@@ -432,8 +385,10 @@ unsigned long omap2_clksel_recalc(struct clk *clk)
432 * 385 *
433 * Returns the rounded clock rate or returns 0xffffffff on error. 386 * Returns the rounded clock rate or returns 0xffffffff on error.
434 */ 387 */
435long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate) 388long omap2_clksel_round_rate(struct clk_hw *hw, unsigned long target_rate,
389 unsigned long *parent_rate)
436{ 390{
391 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
437 u32 new_div; 392 u32 new_div;
438 393
439 return omap2_clksel_round_rate_div(clk, target_rate, &new_div); 394 return omap2_clksel_round_rate_div(clk, target_rate, &new_div);
@@ -454,8 +409,10 @@ long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate)
454 * is changed, they will all be affected without any notification. 409 * is changed, they will all be affected without any notification.
455 * Returns -EINVAL upon error, or 0 upon success. 410 * Returns -EINVAL upon error, or 0 upon success.
456 */ 411 */
457int omap2_clksel_set_rate(struct clk *clk, unsigned long rate) 412int omap2_clksel_set_rate(struct clk_hw *hw, unsigned long rate,
413 unsigned long parent_rate)
458{ 414{
415 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
459 u32 field_val, validrate, new_div = 0; 416 u32 field_val, validrate, new_div = 0;
460 417
461 if (!clk->clksel || !clk->clksel_mask) 418 if (!clk->clksel || !clk->clksel_mask)
@@ -471,10 +428,8 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
471 428
472 _write_clksel_reg(clk, field_val); 429 _write_clksel_reg(clk, field_val);
473 430
474 clk->rate = __clk_get_rate(__clk_get_parent(clk)) / new_div; 431 pr_debug("clock: %s: set rate to %ld\n", __clk_get_name(hw->clk),
475 432 __clk_get_rate(hw->clk));
476 pr_debug("clock: %s: set rate to %ld\n", __clk_get_name(clk),
477 __clk_get_rate(clk));
478 433
479 return 0; 434 return 0;
480} 435}
@@ -499,32 +454,13 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
499 * affected without any notification. Returns -EINVAL upon error, or 454 * affected without any notification. Returns -EINVAL upon error, or
500 * 0 upon success. 455 * 0 upon success.
501 */ 456 */
502int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent) 457int omap2_clksel_set_parent(struct clk_hw *hw, u8 field_val)
503{ 458{
504 u32 field_val = 0; 459 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
505 u32 parent_div;
506 460
507 if (!clk->clksel || !clk->clksel_mask) 461 if (!clk->clksel || !clk->clksel_mask)
508 return -EINVAL; 462 return -EINVAL;
509 463
510 parent_div = _get_div_and_fieldval(new_parent, clk, &field_val);
511 if (!parent_div)
512 return -EINVAL;
513
514 _write_clksel_reg(clk, field_val); 464 _write_clksel_reg(clk, field_val);
515
516 clk_reparent(clk, new_parent);
517
518 /* CLKSEL clocks follow their parents' rates, divided by a divisor */
519 clk->rate = __clk_get_rate(new_parent);
520
521 if (parent_div > 0)
522 __clk_get_rate(clk) /= parent_div;
523
524 pr_debug("clock: %s: set parent to %s (new rate %ld)\n",
525 __clk_get_name(clk),
526 __clk_get_name(__clk_get_parent(clk)),
527 __clk_get_rate(clk));
528
529 return 0; 465 return 0;
530} 466}
diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c
index 8463cc356245..924c230f8948 100644
--- a/arch/arm/mach-omap2/clkt_dpll.c
+++ b/arch/arm/mach-omap2/clkt_dpll.c
@@ -16,7 +16,7 @@
16 16
17#include <linux/kernel.h> 17#include <linux/kernel.h>
18#include <linux/errno.h> 18#include <linux/errno.h>
19#include <linux/clk.h> 19#include <linux/clk-provider.h>
20#include <linux/io.h> 20#include <linux/io.h>
21 21
22#include <asm/div64.h> 22#include <asm/div64.h>
@@ -76,7 +76,7 @@
76 * (assuming that it is counting N upwards), or -2 if the enclosing loop 76 * (assuming that it is counting N upwards), or -2 if the enclosing loop
77 * should skip to the next iteration (again assuming N is increasing). 77 * should skip to the next iteration (again assuming N is increasing).
78 */ 78 */
79static int _dpll_test_fint(struct clk *clk, u8 n) 79static int _dpll_test_fint(struct clk_hw_omap *clk, u8 n)
80{ 80{
81 struct dpll_data *dd; 81 struct dpll_data *dd;
82 long fint, fint_min, fint_max; 82 long fint, fint_min, fint_max;
@@ -85,7 +85,7 @@ static int _dpll_test_fint(struct clk *clk, u8 n)
85 dd = clk->dpll_data; 85 dd = clk->dpll_data;
86 86
87 /* DPLL divider must result in a valid jitter correction val */ 87 /* DPLL divider must result in a valid jitter correction val */
88 fint = __clk_get_rate(__clk_get_parent(clk)) / n; 88 fint = __clk_get_rate(__clk_get_parent(clk->hw.clk)) / n;
89 89
90 if (cpu_is_omap24xx()) { 90 if (cpu_is_omap24xx()) {
91 /* Should not be called for OMAP2, so warn if it is called */ 91 /* Should not be called for OMAP2, so warn if it is called */
@@ -186,15 +186,15 @@ static int _dpll_test_mult(int *m, int n, unsigned long *new_rate,
186} 186}
187 187
188/* Public functions */ 188/* Public functions */
189 189u8 omap2_init_dpll_parent(struct clk_hw *hw)
190void omap2_init_dpll_parent(struct clk *clk)
191{ 190{
191 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
192 u32 v; 192 u32 v;
193 struct dpll_data *dd; 193 struct dpll_data *dd;
194 194
195 dd = clk->dpll_data; 195 dd = clk->dpll_data;
196 if (!dd) 196 if (!dd)
197 return; 197 return -EINVAL;
198 198
199 v = __raw_readl(dd->control_reg); 199 v = __raw_readl(dd->control_reg);
200 v &= dd->enable_mask; 200 v &= dd->enable_mask;
@@ -204,18 +204,18 @@ void omap2_init_dpll_parent(struct clk *clk)
204 if (cpu_is_omap24xx()) { 204 if (cpu_is_omap24xx()) {
205 if (v == OMAP2XXX_EN_DPLL_LPBYPASS || 205 if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
206 v == OMAP2XXX_EN_DPLL_FRBYPASS) 206 v == OMAP2XXX_EN_DPLL_FRBYPASS)
207 clk_reparent(clk, dd->clk_bypass); 207 return 1;
208 } else if (cpu_is_omap34xx()) { 208 } else if (cpu_is_omap34xx()) {
209 if (v == OMAP3XXX_EN_DPLL_LPBYPASS || 209 if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
210 v == OMAP3XXX_EN_DPLL_FRBYPASS) 210 v == OMAP3XXX_EN_DPLL_FRBYPASS)
211 clk_reparent(clk, dd->clk_bypass); 211 return 1;
212 } else if (soc_is_am33xx() || cpu_is_omap44xx()) { 212 } else if (soc_is_am33xx() || cpu_is_omap44xx()) {
213 if (v == OMAP4XXX_EN_DPLL_LPBYPASS || 213 if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
214 v == OMAP4XXX_EN_DPLL_FRBYPASS || 214 v == OMAP4XXX_EN_DPLL_FRBYPASS ||
215 v == OMAP4XXX_EN_DPLL_MNBYPASS) 215 v == OMAP4XXX_EN_DPLL_MNBYPASS)
216 clk_reparent(clk, dd->clk_bypass); 216 return 1;
217 } 217 }
218 return; 218 return 0;
219} 219}
220 220
221/** 221/**
@@ -232,7 +232,7 @@ void omap2_init_dpll_parent(struct clk *clk)
232 * locked, or the appropriate bypass rate if the DPLL is bypassed, or 0 232 * locked, or the appropriate bypass rate if the DPLL is bypassed, or 0
233 * if the clock @clk is not a DPLL. 233 * if the clock @clk is not a DPLL.
234 */ 234 */
235u32 omap2_get_dpll_rate(struct clk *clk) 235unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk)
236{ 236{
237 long long dpll_clk; 237 long long dpll_clk;
238 u32 dpll_mult, dpll_div, v; 238 u32 dpll_mult, dpll_div, v;
@@ -288,8 +288,10 @@ u32 omap2_get_dpll_rate(struct clk *clk)
288 * (expensive) function again. Returns ~0 if the target rate cannot 288 * (expensive) function again. Returns ~0 if the target rate cannot
289 * be rounded, or the rounded rate upon success. 289 * be rounded, or the rounded rate upon success.
290 */ 290 */
291long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate) 291long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
292 unsigned long *parent_rate)
292{ 293{
294 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
293 int m, n, r, scaled_max_m; 295 int m, n, r, scaled_max_m;
294 unsigned long scaled_rt_rp; 296 unsigned long scaled_rt_rp;
295 unsigned long new_rate = 0; 297 unsigned long new_rate = 0;
@@ -303,7 +305,7 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
303 dd = clk->dpll_data; 305 dd = clk->dpll_data;
304 306
305 ref_rate = __clk_get_rate(dd->clk_ref); 307 ref_rate = __clk_get_rate(dd->clk_ref);
306 clk_name = __clk_get_name(clk); 308 clk_name = __clk_get_name(hw->clk);
307 pr_debug("clock: %s: starting DPLL round_rate, target rate %ld\n", 309 pr_debug("clock: %s: starting DPLL round_rate, target rate %ld\n",
308 clk_name, target_rate); 310 clk_name, target_rate);
309 311
diff --git a/arch/arm/mach-omap2/clkt_iclk.c b/arch/arm/mach-omap2/clkt_iclk.c
index fe774a09dd0c..f10eb03ce3e2 100644
--- a/arch/arm/mach-omap2/clkt_iclk.c
+++ b/arch/arm/mach-omap2/clkt_iclk.c
@@ -11,7 +11,7 @@
11#undef DEBUG 11#undef DEBUG
12 12
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/clk.h> 14#include <linux/clk-provider.h>
15#include <linux/io.h> 15#include <linux/io.h>
16 16
17 17
@@ -23,7 +23,7 @@
23/* Private functions */ 23/* Private functions */
24 24
25/* XXX */ 25/* XXX */
26void omap2_clkt_iclk_allow_idle(struct clk *clk) 26void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk)
27{ 27{
28 u32 v, r; 28 u32 v, r;
29 29
@@ -35,7 +35,7 @@ void omap2_clkt_iclk_allow_idle(struct clk *clk)
35} 35}
36 36
37/* XXX */ 37/* XXX */
38void omap2_clkt_iclk_deny_idle(struct clk *clk) 38void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk)
39{ 39{
40 u32 v, r; 40 u32 v, r;
41 41
@@ -48,33 +48,17 @@ void omap2_clkt_iclk_deny_idle(struct clk *clk)
48 48
49/* Public data */ 49/* Public data */
50 50
51const struct clkops clkops_omap2_iclk_dflt_wait = { 51const struct clk_hw_omap_ops clkhwops_iclk = {
52 .enable = omap2_dflt_clk_enable,
53 .disable = omap2_dflt_clk_disable,
54 .find_companion = omap2_clk_dflt_find_companion,
55 .find_idlest = omap2_clk_dflt_find_idlest,
56 .allow_idle = omap2_clkt_iclk_allow_idle, 52 .allow_idle = omap2_clkt_iclk_allow_idle,
57 .deny_idle = omap2_clkt_iclk_deny_idle, 53 .deny_idle = omap2_clkt_iclk_deny_idle,
58}; 54};
59 55
60const struct clkops clkops_omap2_iclk_dflt = { 56const struct clk_hw_omap_ops clkhwops_iclk_wait = {
61 .enable = omap2_dflt_clk_enable,
62 .disable = omap2_dflt_clk_disable,
63 .allow_idle = omap2_clkt_iclk_allow_idle, 57 .allow_idle = omap2_clkt_iclk_allow_idle,
64 .deny_idle = omap2_clkt_iclk_deny_idle, 58 .deny_idle = omap2_clkt_iclk_deny_idle,
59 .find_idlest = omap2_clk_dflt_find_idlest,
60 .find_companion = omap2_clk_dflt_find_companion,
65}; 61};
66 62
67const struct clkops clkops_omap2_iclk_idle_only = {
68 .allow_idle = omap2_clkt_iclk_allow_idle,
69 .deny_idle = omap2_clkt_iclk_deny_idle,
70};
71 63
72const struct clkops clkops_omap2_mdmclk_dflt_wait = {
73 .enable = omap2_dflt_clk_enable,
74 .disable = omap2_dflt_clk_disable,
75 .find_companion = omap2_clk_dflt_find_companion,
76 .find_idlest = omap2_clk_dflt_find_idlest,
77 .allow_idle = omap2_clkt_iclk_allow_idle,
78 .deny_idle = omap2_clkt_iclk_deny_idle,
79};
80 64
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index e381d991092c..e4ec3a69ee2e 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -20,7 +20,7 @@
20#include <linux/errno.h> 20#include <linux/errno.h>
21#include <linux/err.h> 21#include <linux/err.h>
22#include <linux/delay.h> 22#include <linux/delay.h>
23#include <linux/clk.h> 23#include <linux/clk-provider.h>
24#include <linux/io.h> 24#include <linux/io.h>
25#include <linux/bitops.h> 25#include <linux/bitops.h>
26 26
@@ -55,9 +55,28 @@ u16 cpu_mask;
55 */ 55 */
56static bool clkdm_control = true; 56static bool clkdm_control = true;
57 57
58static LIST_HEAD(clocks); 58static LIST_HEAD(clk_hw_omap_clocks);
59static DEFINE_MUTEX(clocks_mutex); 59
60static DEFINE_SPINLOCK(clockfw_lock); 60/*
61 * Used for clocks that have the same value as the parent clock,
62 * divided by some factor
63 */
64unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw,
65 unsigned long parent_rate)
66{
67 struct clk_hw_omap *oclk;
68
69 if (!hw) {
70 pr_warn("%s: hw is NULL\n", __func__);
71 return -EINVAL;
72 }
73
74 oclk = to_clk_hw_omap(hw);
75
76 WARN_ON(!oclk->fixed_div);
77
78 return parent_rate / oclk->fixed_div;
79}
61 80
62/* 81/*
63 * OMAP2+ specific clock functions 82 * OMAP2+ specific clock functions
@@ -109,7 +128,7 @@ static int _wait_idlest_generic(void __iomem *reg, u32 mask, u8 idlest,
109 * belong in the clock code and will be moved in the medium term to 128 * belong in the clock code and will be moved in the medium term to
110 * module-dependent code. No return value. 129 * module-dependent code. No return value.
111 */ 130 */
112static void _omap2_module_wait_ready(struct clk *clk) 131static void _omap2_module_wait_ready(struct clk_hw_omap *clk)
113{ 132{
114 void __iomem *companion_reg, *idlest_reg; 133 void __iomem *companion_reg, *idlest_reg;
115 u8 other_bit, idlest_bit, idlest_val, idlest_reg_id; 134 u8 other_bit, idlest_bit, idlest_val, idlest_reg_id;
@@ -124,12 +143,11 @@ static void _omap2_module_wait_ready(struct clk *clk)
124 } 143 }
125 144
126 clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit, &idlest_val); 145 clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit, &idlest_val);
127
128 r = cm_split_idlest_reg(idlest_reg, &prcm_mod, &idlest_reg_id); 146 r = cm_split_idlest_reg(idlest_reg, &prcm_mod, &idlest_reg_id);
129 if (r) { 147 if (r) {
130 /* IDLEST register not in the CM module */ 148 /* IDLEST register not in the CM module */
131 _wait_idlest_generic(idlest_reg, (1 << idlest_bit), idlest_val, 149 _wait_idlest_generic(idlest_reg, (1 << idlest_bit), idlest_val,
132 clk->name); 150 __clk_get_name(clk->hw.clk));
133 } else { 151 } else {
134 cm_wait_module_ready(prcm_mod, idlest_reg_id, idlest_bit); 152 cm_wait_module_ready(prcm_mod, idlest_reg_id, idlest_bit);
135 }; 153 };
@@ -145,15 +163,16 @@ static void _omap2_module_wait_ready(struct clk *clk)
145 * clockdomain pointer, and save it into the struct clk. Intended to be 163 * clockdomain pointer, and save it into the struct clk. Intended to be
146 * called during clk_register(). No return value. 164 * called during clk_register(). No return value.
147 */ 165 */
148void omap2_init_clk_clkdm(struct clk *clk) 166void omap2_init_clk_clkdm(struct clk_hw *hw)
149{ 167{
168 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
150 struct clockdomain *clkdm; 169 struct clockdomain *clkdm;
151 const char *clk_name; 170 const char *clk_name;
152 171
153 if (!clk->clkdm_name) 172 if (!clk->clkdm_name)
154 return; 173 return;
155 174
156 clk_name = __clk_get_name(clk); 175 clk_name = __clk_get_name(hw->clk);
157 176
158 clkdm = clkdm_lookup(clk->clkdm_name); 177 clkdm = clkdm_lookup(clk->clkdm_name);
159 if (clkdm) { 178 if (clkdm) {
@@ -200,8 +219,8 @@ void __init omap2_clk_disable_clkdm_control(void)
200 * associate this type of code with per-module data structures to 219 * associate this type of code with per-module data structures to
201 * avoid this issue, and remove the casts. No return value. 220 * avoid this issue, and remove the casts. No return value.
202 */ 221 */
203void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg, 222void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk,
204 u8 *other_bit) 223 void __iomem **other_reg, u8 *other_bit)
205{ 224{
206 u32 r; 225 u32 r;
207 226
@@ -229,8 +248,8 @@ void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg,
229 * register address ID (e.g., that CM_FCLKEN2 corresponds to 248 * register address ID (e.g., that CM_FCLKEN2 corresponds to
230 * CM_IDLEST2). This is not true for all modules. No return value. 249 * CM_IDLEST2). This is not true for all modules. No return value.
231 */ 250 */
232void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg, 251void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
233 u8 *idlest_bit, u8 *idlest_val) 252 void __iomem **idlest_reg, u8 *idlest_bit, u8 *idlest_val)
234{ 253{
235 u32 r; 254 u32 r;
236 255
@@ -252,16 +271,44 @@ void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg,
252 271
253} 272}
254 273
255int omap2_dflt_clk_enable(struct clk *clk) 274/**
275 * omap2_dflt_clk_enable - enable a clock in the hardware
276 * @hw: struct clk_hw * of the clock to enable
277 *
278 * Enable the clock @hw in the hardware. We first call into the OMAP
279 * clockdomain code to "enable" the corresponding clockdomain if this
280 * is the first enabled user of the clockdomain. Then program the
281 * hardware to enable the clock. Then wait for the IP block that uses
282 * this clock to leave idle (if applicable). Returns the error value
283 * from clkdm_clk_enable() if it terminated with an error, or -EINVAL
284 * if @hw has a null clock enable_reg, or zero upon success.
285 */
286int omap2_dflt_clk_enable(struct clk_hw *hw)
256{ 287{
288 struct clk_hw_omap *clk;
257 u32 v; 289 u32 v;
290 int ret = 0;
291
292 clk = to_clk_hw_omap(hw);
293
294 if (clkdm_control && clk->clkdm) {
295 ret = clkdm_clk_enable(clk->clkdm, hw->clk);
296 if (ret) {
297 WARN(1, "%s: could not enable %s's clockdomain %s: %d\n",
298 __func__, __clk_get_name(hw->clk),
299 clk->clkdm->name, ret);
300 return ret;
301 }
302 }
258 303
259 if (unlikely(clk->enable_reg == NULL)) { 304 if (unlikely(clk->enable_reg == NULL)) {
260 pr_err("clock.c: Enable for %s without enable code\n", 305 pr_err("%s: %s missing enable_reg\n", __func__,
261 clk->name); 306 __clk_get_name(hw->clk));
262 return 0; /* REVISIT: -EINVAL */ 307 ret = -EINVAL;
308 goto err;
263 } 309 }
264 310
311 /* FIXME should not have INVERT_ENABLE bit here */
265 v = __raw_readl(clk->enable_reg); 312 v = __raw_readl(clk->enable_reg);
266 if (clk->flags & INVERT_ENABLE) 313 if (clk->flags & INVERT_ENABLE)
267 v &= ~(1 << clk->enable_bit); 314 v &= ~(1 << clk->enable_bit);
@@ -270,22 +317,39 @@ int omap2_dflt_clk_enable(struct clk *clk)
270 __raw_writel(v, clk->enable_reg); 317 __raw_writel(v, clk->enable_reg);
271 v = __raw_readl(clk->enable_reg); /* OCP barrier */ 318 v = __raw_readl(clk->enable_reg); /* OCP barrier */
272 319
273 if (clk->ops->find_idlest) 320 if (clk->ops && clk->ops->find_idlest)
274 _omap2_module_wait_ready(clk); 321 _omap2_module_wait_ready(clk);
275 322
276 return 0; 323 return 0;
324
325err:
326 if (clkdm_control && clk->clkdm)
327 clkdm_clk_disable(clk->clkdm, hw->clk);
328 return ret;
277} 329}
278 330
279void omap2_dflt_clk_disable(struct clk *clk) 331/**
332 * omap2_dflt_clk_disable - disable a clock in the hardware
333 * @hw: struct clk_hw * of the clock to disable
334 *
335 * Disable the clock @hw in the hardware, and call into the OMAP
336 * clockdomain code to "disable" the corresponding clockdomain if all
337 * clocks/hwmods in that clockdomain are now disabled. No return
338 * value.
339 */
340void omap2_dflt_clk_disable(struct clk_hw *hw)
280{ 341{
342 struct clk_hw_omap *clk;
281 u32 v; 343 u32 v;
282 344
345 clk = to_clk_hw_omap(hw);
283 if (!clk->enable_reg) { 346 if (!clk->enable_reg) {
284 /* 347 /*
285 * 'Independent' here refers to a clock which is not 348 * 'independent' here refers to a clock which is not
286 * controlled by its parent. 349 * controlled by its parent.
287 */ 350 */
288 pr_err("clock: clk_disable called on independent clock %s which has no enable_reg\n", clk->name); 351 pr_err("%s: independent clock %s has no enable_reg\n",
352 __func__, __clk_get_name(hw->clk));
289 return; 353 return;
290 } 354 }
291 355
@@ -296,191 +360,213 @@ void omap2_dflt_clk_disable(struct clk *clk)
296 v &= ~(1 << clk->enable_bit); 360 v &= ~(1 << clk->enable_bit);
297 __raw_writel(v, clk->enable_reg); 361 __raw_writel(v, clk->enable_reg);
298 /* No OCP barrier needed here since it is a disable operation */ 362 /* No OCP barrier needed here since it is a disable operation */
299}
300
301const struct clkops clkops_omap2_dflt_wait = {
302 .enable = omap2_dflt_clk_enable,
303 .disable = omap2_dflt_clk_disable,
304 .find_companion = omap2_clk_dflt_find_companion,
305 .find_idlest = omap2_clk_dflt_find_idlest,
306};
307 363
308const struct clkops clkops_omap2_dflt = { 364 if (clkdm_control && clk->clkdm)
309 .enable = omap2_dflt_clk_enable, 365 clkdm_clk_disable(clk->clkdm, hw->clk);
310 .disable = omap2_dflt_clk_disable, 366}
311};
312 367
313/** 368/**
314 * omap2_clk_disable - disable a clock, if the system is not using it 369 * omap2_clkops_enable_clkdm - increment usecount on clkdm of @hw
315 * @clk: struct clk * to disable 370 * @hw: struct clk_hw * of the clock being enabled
316 * 371 *
317 * Decrements the usecount on struct clk @clk. If there are no users 372 * Increment the usecount of the clockdomain of the clock pointed to
318 * left, call the clkops-specific clock disable function to disable it 373 * by @hw; if the usecount is 1, the clockdomain will be "enabled."
319 * in hardware. If the clock is part of a clockdomain (which they all 374 * Only needed for clocks that don't use omap2_dflt_clk_enable() as
320 * should be), request that the clockdomain be disabled. (It too has 375 * their enable function pointer. Passes along the return value of
321 * a usecount, and so will not be disabled in the hardware until it no 376 * clkdm_clk_enable(), -EINVAL if @hw is not associated with a
322 * longer has any users.) If the clock has a parent clock (most of 377 * clockdomain, or 0 if clock framework-based clockdomain control is
323 * them do), then call ourselves, recursing on the parent clock. This 378 * not implemented.
324 * can cause an entire branch of the clock tree to be powered off by
325 * simply disabling one clock. Intended to be called with the clockfw_lock
326 * spinlock held. No return value.
327 */ 379 */
328void omap2_clk_disable(struct clk *clk) 380int omap2_clkops_enable_clkdm(struct clk_hw *hw)
329{ 381{
330 if (clk->usecount == 0) { 382 struct clk_hw_omap *clk;
331 WARN(1, "clock: %s: omap2_clk_disable() called, but usecount already 0?", clk->name); 383 int ret = 0;
332 return;
333 }
334
335 pr_debug("clock: %s: decrementing usecount\n", clk->name);
336 384
337 clk->usecount--; 385 clk = to_clk_hw_omap(hw);
338 386
339 if (clk->usecount > 0) 387 if (unlikely(!clk->clkdm)) {
340 return; 388 pr_err("%s: %s: no clkdm set ?!\n", __func__,
389 __clk_get_name(hw->clk));
390 return -EINVAL;
391 }
341 392
342 pr_debug("clock: %s: disabling in hardware\n", clk->name); 393 if (unlikely(clk->enable_reg))
394 pr_err("%s: %s: should use dflt_clk_enable ?!\n", __func__,
395 __clk_get_name(hw->clk));
343 396
344 if (clk->ops && clk->ops->disable) { 397 if (!clkdm_control) {
345 trace_clock_disable(clk->name, 0, smp_processor_id()); 398 pr_err("%s: %s: clkfw-based clockdomain control disabled ?!\n",
346 clk->ops->disable(clk); 399 __func__, __clk_get_name(hw->clk));
400 return 0;
347 } 401 }
348 402
349 if (clkdm_control && clk->clkdm) 403 ret = clkdm_clk_enable(clk->clkdm, hw->clk);
350 clkdm_clk_disable(clk->clkdm, clk); 404 WARN(ret, "%s: could not enable %s's clockdomain %s: %d\n",
405 __func__, __clk_get_name(hw->clk), clk->clkdm->name, ret);
351 406
352 if (clk->parent) 407 return ret;
353 omap2_clk_disable(clk->parent);
354} 408}
355 409
356/** 410/**
357 * omap2_clk_enable - request that the system enable a clock 411 * omap2_clkops_disable_clkdm - decrement usecount on clkdm of @hw
358 * @clk: struct clk * to enable 412 * @hw: struct clk_hw * of the clock being disabled
359 * 413 *
360 * Increments the usecount on struct clk @clk. If there were no users 414 * Decrement the usecount of the clockdomain of the clock pointed to
361 * previously, then recurse up the clock tree, enabling all of the 415 * by @hw; if the usecount is 0, the clockdomain will be "disabled."
362 * clock's parents and all of the parent clockdomains, and finally, 416 * Only needed for clocks that don't use omap2_dflt_clk_disable() as their
363 * enabling @clk's clockdomain, and @clk itself. Intended to be 417 * disable function pointer. No return value.
364 * called with the clockfw_lock spinlock held. Returns 0 upon success
365 * or a negative error code upon failure.
366 */ 418 */
367int omap2_clk_enable(struct clk *clk) 419void omap2_clkops_disable_clkdm(struct clk_hw *hw)
368{ 420{
369 int ret; 421 struct clk_hw_omap *clk;
370 422
371 pr_debug("clock: %s: incrementing usecount\n", clk->name); 423 clk = to_clk_hw_omap(hw);
372 424
373 clk->usecount++; 425 if (unlikely(!clk->clkdm)) {
374 426 pr_err("%s: %s: no clkdm set ?!\n", __func__,
375 if (clk->usecount > 1) 427 __clk_get_name(hw->clk));
376 return 0; 428 return;
377
378 pr_debug("clock: %s: enabling in hardware\n", clk->name);
379
380 if (clk->parent) {
381 ret = omap2_clk_enable(clk->parent);
382 if (ret) {
383 WARN(1, "clock: %s: could not enable parent %s: %d\n",
384 clk->name, clk->parent->name, ret);
385 goto oce_err1;
386 }
387 } 429 }
388 430
389 if (clkdm_control && clk->clkdm) { 431 if (unlikely(clk->enable_reg))
390 ret = clkdm_clk_enable(clk->clkdm, clk); 432 pr_err("%s: %s: should use dflt_clk_disable ?!\n", __func__,
391 if (ret) { 433 __clk_get_name(hw->clk));
392 WARN(1, "clock: %s: could not enable clockdomain %s: %d\n",
393 clk->name, clk->clkdm->name, ret);
394 goto oce_err2;
395 }
396 }
397 434
398 if (clk->ops && clk->ops->enable) { 435 if (!clkdm_control) {
399 trace_clock_enable(clk->name, 1, smp_processor_id()); 436 pr_err("%s: %s: clkfw-based clockdomain control disabled ?!\n",
400 ret = clk->ops->enable(clk); 437 __func__, __clk_get_name(hw->clk));
401 if (ret) { 438 return;
402 WARN(1, "clock: %s: could not enable: %d\n",
403 clk->name, ret);
404 goto oce_err3;
405 }
406 } 439 }
407 440
408 return 0; 441 clkdm_clk_disable(clk->clkdm, hw->clk);
409
410oce_err3:
411 if (clkdm_control && clk->clkdm)
412 clkdm_clk_disable(clk->clkdm, clk);
413oce_err2:
414 if (clk->parent)
415 omap2_clk_disable(clk->parent);
416oce_err1:
417 clk->usecount--;
418
419 return ret;
420} 442}
421 443
422/* Given a clock and a rate apply a clock specific rounding function */ 444/**
423long omap2_clk_round_rate(struct clk *clk, unsigned long rate) 445 * omap2_dflt_clk_is_enabled - is clock enabled in the hardware?
446 * @hw: struct clk_hw * to check
447 *
448 * Return 1 if the clock represented by @hw is enabled in the
449 * hardware, or 0 otherwise. Intended for use in the struct
450 * clk_ops.is_enabled function pointer.
451 */
452int omap2_dflt_clk_is_enabled(struct clk_hw *hw)
424{ 453{
425 if (clk->round_rate) 454 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
426 return clk->round_rate(clk, rate); 455 u32 v;
427 456
428 return clk->rate; 457 v = __raw_readl(clk->enable_reg);
458
459 if (clk->flags & INVERT_ENABLE)
460 v ^= BIT(clk->enable_bit);
461
462 v &= BIT(clk->enable_bit);
463
464 return v ? 1 : 0;
429} 465}
430 466
431/* Set the clock rate for a clock source */ 467static int __initdata mpurate;
432int omap2_clk_set_rate(struct clk *clk, unsigned long rate) 468
469/*
470 * By default we use the rate set by the bootloader.
471 * You can override this with mpurate= cmdline option.
472 */
473static int __init omap_clk_setup(char *str)
433{ 474{
434 int ret = -EINVAL; 475 get_option(&str, &mpurate);
435 476
436 pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate); 477 if (!mpurate)
478 return 1;
437 479
438 /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */ 480 if (mpurate < 1000)
439 if (clk->set_rate) { 481 mpurate *= 1000000;
440 trace_clock_set_rate(clk->name, rate, smp_processor_id());
441 ret = clk->set_rate(clk, rate);
442 }
443 482
444 return ret; 483 return 1;
445} 484}
485__setup("mpurate=", omap_clk_setup);
446 486
447int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent) 487/**
488 * omap2_init_clk_hw_omap_clocks - initialize an OMAP clock
489 * @clk: struct clk * to initialize
490 *
491 * Add an OMAP clock @clk to the internal list of OMAP clocks. Used
492 * temporarily for autoidle handling, until this support can be
493 * integrated into the common clock framework code in some way. No
494 * return value.
495 */
496void omap2_init_clk_hw_omap_clocks(struct clk *clk)
448{ 497{
449 if (!clk->clksel) 498 struct clk_hw_omap *c;
450 return -EINVAL;
451 499
452 if (clk->parent == new_parent) 500 if (__clk_get_flags(clk) & CLK_IS_BASIC)
453 return 0; 501 return;
454 502
455 return omap2_clksel_set_parent(clk, new_parent); 503 c = to_clk_hw_omap(__clk_get_hw(clk));
504 list_add(&c->node, &clk_hw_omap_clocks);
456} 505}
457 506
458/* 507/**
459 * OMAP2+ clock reset and init functions 508 * omap2_clk_enable_autoidle_all - enable autoidle on all OMAP clocks that
509 * support it
510 *
511 * Enable clock autoidle on all OMAP clocks that have allow_idle
512 * function pointers associated with them. This function is intended
513 * to be temporary until support for this is added to the common clock
514 * code. Returns 0.
460 */ 515 */
516int omap2_clk_enable_autoidle_all(void)
517{
518 struct clk_hw_omap *c;
461 519
462#ifdef CONFIG_OMAP_RESET_CLOCKS 520 list_for_each_entry(c, &clk_hw_omap_clocks, node)
463void omap2_clk_disable_unused(struct clk *clk) 521 if (c->ops && c->ops->allow_idle)
522 c->ops->allow_idle(c);
523 return 0;
524}
525
526/**
527 * omap2_clk_disable_autoidle_all - disable autoidle on all OMAP clocks that
528 * support it
529 *
530 * Disable clock autoidle on all OMAP clocks that have allow_idle
531 * function pointers associated with them. This function is intended
532 * to be temporary until support for this is added to the common clock
533 * code. Returns 0.
534 */
535int omap2_clk_disable_autoidle_all(void)
464{ 536{
465 u32 regval32, v; 537 struct clk_hw_omap *c;
466 538
467 v = (clk->flags & INVERT_ENABLE) ? (1 << clk->enable_bit) : 0; 539 list_for_each_entry(c, &clk_hw_omap_clocks, node)
540 if (c->ops && c->ops->deny_idle)
541 c->ops->deny_idle(c);
542 return 0;
543}
468 544
469 regval32 = __raw_readl(clk->enable_reg); 545/**
470 if ((regval32 & (1 << clk->enable_bit)) == v) 546 * omap2_clk_enable_init_clocks - prepare & enable a list of clocks
471 return; 547 * @clk_names: ptr to an array of strings of clock names to enable
548 * @num_clocks: number of clock names in @clk_names
549 *
550 * Prepare and enable a list of clocks, named by @clk_names. No
551 * return value. XXX Deprecated; only needed until these clocks are
552 * properly claimed and enabled by the drivers or core code that uses
553 * them. XXX What code disables & calls clk_put on these clocks?
554 */
555void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks)
556{
557 struct clk *init_clk;
558 int i;
472 559
473 pr_debug("Disabling unused clock \"%s\"\n", clk->name); 560 for (i = 0; i < num_clocks; i++) {
474 if (cpu_is_omap34xx()) { 561 init_clk = clk_get(NULL, clk_names[i]);
475 omap2_clk_enable(clk); 562 clk_prepare_enable(init_clk);
476 omap2_clk_disable(clk);
477 } else {
478 clk->ops->disable(clk);
479 } 563 }
480 if (clk->clkdm != NULL)
481 pwrdm_state_switch(clk->clkdm->pwrdm.ptr);
482} 564}
483#endif 565
566const struct clk_hw_omap_ops clkhwops_wait = {
567 .find_idlest = omap2_clk_dflt_find_idlest,
568 .find_companion = omap2_clk_dflt_find_companion,
569};
484 570
485/** 571/**
486 * omap2_clk_switch_mpurate_at_boot - switch ARM MPU rate by boot-time argument 572 * omap2_clk_switch_mpurate_at_boot - switch ARM MPU rate by boot-time argument
@@ -512,14 +598,12 @@ int __init omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name)
512 r = clk_set_rate(mpurate_ck, mpurate); 598 r = clk_set_rate(mpurate_ck, mpurate);
513 if (IS_ERR_VALUE(r)) { 599 if (IS_ERR_VALUE(r)) {
514 WARN(1, "clock: %s: unable to set MPU rate to %d: %d\n", 600 WARN(1, "clock: %s: unable to set MPU rate to %d: %d\n",
515 mpurate_ck->name, mpurate, r); 601 mpurate_ck_name, mpurate, r);
516 clk_put(mpurate_ck); 602 clk_put(mpurate_ck);
517 return -EINVAL; 603 return -EINVAL;
518 } 604 }
519 605
520 calibrate_delay(); 606 calibrate_delay();
521 recalculate_root_clocks();
522
523 clk_put(mpurate_ck); 607 clk_put(mpurate_ck);
524 608
525 return 0; 609 return 0;
@@ -563,513 +647,3 @@ void __init omap2_clk_print_new_rates(const char *hfclkin_ck_name,
563 (clk_get_rate(core_ck) / 1000000), 647 (clk_get_rate(core_ck) / 1000000),
564 (clk_get_rate(mpu_ck) / 1000000)); 648 (clk_get_rate(mpu_ck) / 1000000));
565} 649}
566
567/* Common data */
568
569int clk_enable(struct clk *clk)
570{
571 unsigned long flags;
572 int ret;
573
574 if (clk == NULL || IS_ERR(clk))
575 return -EINVAL;
576
577 spin_lock_irqsave(&clockfw_lock, flags);
578 ret = omap2_clk_enable(clk);
579 spin_unlock_irqrestore(&clockfw_lock, flags);
580
581 return ret;
582}
583EXPORT_SYMBOL(clk_enable);
584
585void clk_disable(struct clk *clk)
586{
587 unsigned long flags;
588
589 if (clk == NULL || IS_ERR(clk))
590 return;
591
592 spin_lock_irqsave(&clockfw_lock, flags);
593 if (clk->usecount == 0) {
594 pr_err("Trying disable clock %s with 0 usecount\n",
595 clk->name);
596 WARN_ON(1);
597 goto out;
598 }
599
600 omap2_clk_disable(clk);
601
602out:
603 spin_unlock_irqrestore(&clockfw_lock, flags);
604}
605EXPORT_SYMBOL(clk_disable);
606
607unsigned long clk_get_rate(struct clk *clk)
608{
609 unsigned long flags;
610 unsigned long ret;
611
612 if (clk == NULL || IS_ERR(clk))
613 return 0;
614
615 spin_lock_irqsave(&clockfw_lock, flags);
616 ret = clk->rate;
617 spin_unlock_irqrestore(&clockfw_lock, flags);
618
619 return ret;
620}
621EXPORT_SYMBOL(clk_get_rate);
622
623/*
624 * Optional clock functions defined in include/linux/clk.h
625 */
626
627long clk_round_rate(struct clk *clk, unsigned long rate)
628{
629 unsigned long flags;
630 long ret;
631
632 if (clk == NULL || IS_ERR(clk))
633 return 0;
634
635 spin_lock_irqsave(&clockfw_lock, flags);
636 ret = omap2_clk_round_rate(clk, rate);
637 spin_unlock_irqrestore(&clockfw_lock, flags);
638
639 return ret;
640}
641EXPORT_SYMBOL(clk_round_rate);
642
643int clk_set_rate(struct clk *clk, unsigned long rate)
644{
645 unsigned long flags;
646 int ret = -EINVAL;
647
648 if (clk == NULL || IS_ERR(clk))
649 return ret;
650
651 spin_lock_irqsave(&clockfw_lock, flags);
652 ret = omap2_clk_set_rate(clk, rate);
653 if (ret == 0)
654 propagate_rate(clk);
655 spin_unlock_irqrestore(&clockfw_lock, flags);
656
657 return ret;
658}
659EXPORT_SYMBOL(clk_set_rate);
660
661int clk_set_parent(struct clk *clk, struct clk *parent)
662{
663 unsigned long flags;
664 int ret = -EINVAL;
665
666 if (clk == NULL || IS_ERR(clk) || parent == NULL || IS_ERR(parent))
667 return ret;
668
669 spin_lock_irqsave(&clockfw_lock, flags);
670 if (clk->usecount == 0) {
671 ret = omap2_clk_set_parent(clk, parent);
672 if (ret == 0)
673 propagate_rate(clk);
674 } else {
675 ret = -EBUSY;
676 }
677 spin_unlock_irqrestore(&clockfw_lock, flags);
678
679 return ret;
680}
681EXPORT_SYMBOL(clk_set_parent);
682
683struct clk *clk_get_parent(struct clk *clk)
684{
685 return clk->parent;
686}
687EXPORT_SYMBOL(clk_get_parent);
688
689/*
690 * OMAP specific clock functions shared between omap1 and omap2
691 */
692
693int __initdata mpurate;
694
695/*
696 * By default we use the rate set by the bootloader.
697 * You can override this with mpurate= cmdline option.
698 */
699static int __init omap_clk_setup(char *str)
700{
701 get_option(&str, &mpurate);
702
703 if (!mpurate)
704 return 1;
705
706 if (mpurate < 1000)
707 mpurate *= 1000000;
708
709 return 1;
710}
711__setup("mpurate=", omap_clk_setup);
712
713/* Used for clocks that always have same value as the parent clock */
714unsigned long followparent_recalc(struct clk *clk)
715{
716 return clk->parent->rate;
717}
718
719/*
720 * Used for clocks that have the same value as the parent clock,
721 * divided by some factor
722 */
723unsigned long omap_fixed_divisor_recalc(struct clk *clk)
724{
725 WARN_ON(!clk->fixed_div);
726
727 return clk->parent->rate / clk->fixed_div;
728}
729
730void clk_reparent(struct clk *child, struct clk *parent)
731{
732 list_del_init(&child->sibling);
733 if (parent)
734 list_add(&child->sibling, &parent->children);
735 child->parent = parent;
736
737 /* now do the debugfs renaming to reattach the child
738 to the proper parent */
739}
740
741/* Propagate rate to children */
742void propagate_rate(struct clk *tclk)
743{
744 struct clk *clkp;
745
746 list_for_each_entry(clkp, &tclk->children, sibling) {
747 if (clkp->recalc)
748 clkp->rate = clkp->recalc(clkp);
749 propagate_rate(clkp);
750 }
751}
752
753static LIST_HEAD(root_clks);
754
755/**
756 * recalculate_root_clocks - recalculate and propagate all root clocks
757 *
758 * Recalculates all root clocks (clocks with no parent), which if the
759 * clock's .recalc is set correctly, should also propagate their rates.
760 * Called at init.
761 */
762void recalculate_root_clocks(void)
763{
764 struct clk *clkp;
765
766 list_for_each_entry(clkp, &root_clks, sibling) {
767 if (clkp->recalc)
768 clkp->rate = clkp->recalc(clkp);
769 propagate_rate(clkp);
770 }
771}
772
773/**
774 * clk_preinit - initialize any fields in the struct clk before clk init
775 * @clk: struct clk * to initialize
776 *
777 * Initialize any struct clk fields needed before normal clk initialization
778 * can run. No return value.
779 */
780void clk_preinit(struct clk *clk)
781{
782 INIT_LIST_HEAD(&clk->children);
783}
784
785int clk_register(struct clk *clk)
786{
787 if (clk == NULL || IS_ERR(clk))
788 return -EINVAL;
789
790 /*
791 * trap out already registered clocks
792 */
793 if (clk->node.next || clk->node.prev)
794 return 0;
795
796 mutex_lock(&clocks_mutex);
797 if (clk->parent)
798 list_add(&clk->sibling, &clk->parent->children);
799 else
800 list_add(&clk->sibling, &root_clks);
801
802 list_add(&clk->node, &clocks);
803 if (clk->init)
804 clk->init(clk);
805 mutex_unlock(&clocks_mutex);
806
807 return 0;
808}
809EXPORT_SYMBOL(clk_register);
810
811void clk_unregister(struct clk *clk)
812{
813 if (clk == NULL || IS_ERR(clk))
814 return;
815
816 mutex_lock(&clocks_mutex);
817 list_del(&clk->sibling);
818 list_del(&clk->node);
819 mutex_unlock(&clocks_mutex);
820}
821EXPORT_SYMBOL(clk_unregister);
822
823void clk_enable_init_clocks(void)
824{
825 struct clk *clkp;
826
827 list_for_each_entry(clkp, &clocks, node)
828 if (clkp->flags & ENABLE_ON_INIT)
829 clk_enable(clkp);
830}
831
832/**
833 * omap_clk_get_by_name - locate OMAP struct clk by its name
834 * @name: name of the struct clk to locate
835 *
836 * Locate an OMAP struct clk by its name. Assumes that struct clk
837 * names are unique. Returns NULL if not found or a pointer to the
838 * struct clk if found.
839 */
840struct clk *omap_clk_get_by_name(const char *name)
841{
842 struct clk *c;
843 struct clk *ret = NULL;
844
845 mutex_lock(&clocks_mutex);
846
847 list_for_each_entry(c, &clocks, node) {
848 if (!strcmp(c->name, name)) {
849 ret = c;
850 break;
851 }
852 }
853
854 mutex_unlock(&clocks_mutex);
855
856 return ret;
857}
858
859int omap_clk_enable_autoidle_all(void)
860{
861 struct clk *c;
862 unsigned long flags;
863
864 spin_lock_irqsave(&clockfw_lock, flags);
865
866 list_for_each_entry(c, &clocks, node)
867 if (c->ops->allow_idle)
868 c->ops->allow_idle(c);
869
870 spin_unlock_irqrestore(&clockfw_lock, flags);
871
872 return 0;
873}
874
875int omap_clk_disable_autoidle_all(void)
876{
877 struct clk *c;
878 unsigned long flags;
879
880 spin_lock_irqsave(&clockfw_lock, flags);
881
882 list_for_each_entry(c, &clocks, node)
883 if (c->ops->deny_idle)
884 c->ops->deny_idle(c);
885
886 spin_unlock_irqrestore(&clockfw_lock, flags);
887
888 return 0;
889}
890
891/*
892 * Low level helpers
893 */
894static int clkll_enable_null(struct clk *clk)
895{
896 return 0;
897}
898
899static void clkll_disable_null(struct clk *clk)
900{
901}
902
903const struct clkops clkops_null = {
904 .enable = clkll_enable_null,
905 .disable = clkll_disable_null,
906};
907
908/*
909 * Dummy clock
910 *
911 * Used for clock aliases that are needed on some OMAPs, but not others
912 */
913struct clk dummy_ck = {
914 .name = "dummy",
915 .ops = &clkops_null,
916};
917
918/*
919 *
920 */
921
922#ifdef CONFIG_OMAP_RESET_CLOCKS
923/*
924 * Disable any unused clocks left on by the bootloader
925 */
926static int __init clk_disable_unused(void)
927{
928 struct clk *ck;
929 unsigned long flags;
930
931 pr_info("clock: disabling unused clocks to save power\n");
932
933 spin_lock_irqsave(&clockfw_lock, flags);
934 list_for_each_entry(ck, &clocks, node) {
935 if (ck->ops == &clkops_null)
936 continue;
937
938 if (ck->usecount > 0 || !ck->enable_reg)
939 continue;
940
941 omap2_clk_disable_unused(ck);
942 }
943 spin_unlock_irqrestore(&clockfw_lock, flags);
944
945 return 0;
946}
947late_initcall(clk_disable_unused);
948late_initcall(omap_clk_enable_autoidle_all);
949#endif
950
951#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
952/*
953 * debugfs support to trace clock tree hierarchy and attributes
954 */
955
956#include <linux/debugfs.h>
957#include <linux/seq_file.h>
958
959static struct dentry *clk_debugfs_root;
960
961static int clk_dbg_show_summary(struct seq_file *s, void *unused)
962{
963 struct clk *c;
964 struct clk *pa;
965
966 mutex_lock(&clocks_mutex);
967 seq_printf(s, "%-30s %-30s %-10s %s\n",
968 "clock-name", "parent-name", "rate", "use-count");
969
970 list_for_each_entry(c, &clocks, node) {
971 pa = c->parent;
972 seq_printf(s, "%-30s %-30s %-10lu %d\n",
973 c->name, pa ? pa->name : "none", c->rate,
974 c->usecount);
975 }
976 mutex_unlock(&clocks_mutex);
977
978 return 0;
979}
980
981static int clk_dbg_open(struct inode *inode, struct file *file)
982{
983 return single_open(file, clk_dbg_show_summary, inode->i_private);
984}
985
986static const struct file_operations debug_clock_fops = {
987 .open = clk_dbg_open,
988 .read = seq_read,
989 .llseek = seq_lseek,
990 .release = single_release,
991};
992
993static int clk_debugfs_register_one(struct clk *c)
994{
995 int err;
996 struct dentry *d;
997 struct clk *pa = c->parent;
998
999 d = debugfs_create_dir(c->name, pa ? pa->dent : clk_debugfs_root);
1000 if (!d)
1001 return -ENOMEM;
1002 c->dent = d;
1003
1004 d = debugfs_create_u8("usecount", S_IRUGO, c->dent, (u8 *)&c->usecount);
1005 if (!d) {
1006 err = -ENOMEM;
1007 goto err_out;
1008 }
1009 d = debugfs_create_u32("rate", S_IRUGO, c->dent, (u32 *)&c->rate);
1010 if (!d) {
1011 err = -ENOMEM;
1012 goto err_out;
1013 }
1014 d = debugfs_create_x32("flags", S_IRUGO, c->dent, (u32 *)&c->flags);
1015 if (!d) {
1016 err = -ENOMEM;
1017 goto err_out;
1018 }
1019 return 0;
1020
1021err_out:
1022 debugfs_remove_recursive(c->dent);
1023 return err;
1024}
1025
1026static int clk_debugfs_register(struct clk *c)
1027{
1028 int err;
1029 struct clk *pa = c->parent;
1030
1031 if (pa && !pa->dent) {
1032 err = clk_debugfs_register(pa);
1033 if (err)
1034 return err;
1035 }
1036
1037 if (!c->dent) {
1038 err = clk_debugfs_register_one(c);
1039 if (err)
1040 return err;
1041 }
1042 return 0;
1043}
1044
1045static int __init clk_debugfs_init(void)
1046{
1047 struct clk *c;
1048 struct dentry *d;
1049 int err;
1050
1051 d = debugfs_create_dir("clock", NULL);
1052 if (!d)
1053 return -ENOMEM;
1054 clk_debugfs_root = d;
1055
1056 list_for_each_entry(c, &clocks, node) {
1057 err = clk_debugfs_register(c);
1058 if (err)
1059 goto err_out;
1060 }
1061
1062 d = debugfs_create_file("summary", S_IRUGO,
1063 d, NULL, &debug_clock_fops);
1064 if (!d)
1065 return -ENOMEM;
1066
1067 return 0;
1068err_out:
1069 debugfs_remove_recursive(clk_debugfs_root);
1070 return err;
1071}
1072late_initcall(clk_debugfs_init);
1073
1074#endif /* defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) */
1075
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index ff9789bc0fd1..9917f793c3b6 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -20,6 +20,7 @@
20#include <linux/list.h> 20#include <linux/list.h>
21 21
22#include <linux/clkdev.h> 22#include <linux/clkdev.h>
23#include <linux/clk-provider.h>
23 24
24struct omap_clk { 25struct omap_clk {
25 u16 cpu; 26 u16 cpu;
@@ -52,43 +53,84 @@ struct omap_clk {
52#define CK_34XX (CK_3430ES1 | CK_3430ES2PLUS) 53#define CK_34XX (CK_3430ES1 | CK_3430ES2PLUS)
53#define CK_3XXX (CK_34XX | CK_AM35XX | CK_36XX) 54#define CK_3XXX (CK_34XX | CK_AM35XX | CK_36XX)
54 55
55struct module;
56struct clk;
57struct clockdomain; 56struct clockdomain;
58 57#define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw)
59/* Temporary, needed during the common clock framework conversion */ 58
60#define __clk_get_name(clk) (clk->name) 59#define DEFINE_STRUCT_CLK(_name, _parent_array_name, _clkops_name) \
61#define __clk_get_parent(clk) (clk->parent) 60 static struct clk _name = { \
62#define __clk_get_rate(clk) (clk->rate) 61 .name = #_name, \
63 62 .hw = &_name##_hw.hw, \
64/** 63 .parent_names = _parent_array_name, \
65 * struct clkops - some clock function pointers 64 .num_parents = ARRAY_SIZE(_parent_array_name), \
66 * @enable: fn ptr that enables the current clock in hardware 65 .ops = &_clkops_name, \
67 * @disable: fn ptr that enables the current clock in hardware 66 };
68 * @find_idlest: function returning the IDLEST register for the clock's IP blk 67
69 * @find_companion: function returning the "companion" clk reg for the clock 68#define DEFINE_STRUCT_CLK_HW_OMAP(_name, _clkdm_name) \
70 * @allow_idle: fn ptr that enables autoidle for the current clock in hardware 69 static struct clk_hw_omap _name##_hw = { \
71 * @deny_idle: fn ptr that disables autoidle for the current clock in hardware 70 .hw = { \
72 * 71 .clk = &_name, \
73 * A "companion" clk is an accompanying clock to the one being queried 72 }, \
74 * that must be enabled for the IP module connected to the clock to 73 .clkdm_name = _clkdm_name, \
75 * become accessible by the hardware. Neither @find_idlest nor 74 };
76 * @find_companion should be needed; that information is IP 75
77 * block-specific; the hwmod code has been created to handle this, but 76#define DEFINE_CLK_OMAP_MUX(_name, _clkdm_name, _clksel, \
78 * until hwmod data is ready and drivers have been converted to use PM 77 _clksel_reg, _clksel_mask, \
79 * runtime calls in place of clk_enable()/clk_disable(), @find_idlest and 78 _parent_names, _ops) \
80 * @find_companion must, unfortunately, remain. 79 static struct clk _name; \
81 */ 80 static struct clk_hw_omap _name##_hw = { \
82struct clkops { 81 .hw = { \
83 int (*enable)(struct clk *); 82 .clk = &_name, \
84 void (*disable)(struct clk *); 83 }, \
85 void (*find_idlest)(struct clk *, void __iomem **, 84 .clksel = _clksel, \
86 u8 *, u8 *); 85 .clksel_reg = _clksel_reg, \
87 void (*find_companion)(struct clk *, void __iomem **, 86 .clksel_mask = _clksel_mask, \
88 u8 *); 87 .clkdm_name = _clkdm_name, \
89 void (*allow_idle)(struct clk *); 88 }; \
90 void (*deny_idle)(struct clk *); 89 DEFINE_STRUCT_CLK(_name, _parent_names, _ops);
91}; 90
91#define DEFINE_CLK_OMAP_MUX_GATE(_name, _clkdm_name, _clksel, \
92 _clksel_reg, _clksel_mask, \
93 _enable_reg, _enable_bit, \
94 _hwops, _parent_names, _ops) \
95 static struct clk _name; \
96 static struct clk_hw_omap _name##_hw = { \
97 .hw = { \
98 .clk = &_name, \
99 }, \
100 .ops = _hwops, \
101 .enable_reg = _enable_reg, \
102 .enable_bit = _enable_bit, \
103 .clksel = _clksel, \
104 .clksel_reg = _clksel_reg, \
105 .clksel_mask = _clksel_mask, \
106 .clkdm_name = _clkdm_name, \
107 }; \
108 DEFINE_STRUCT_CLK(_name, _parent_names, _ops);
109
110#define DEFINE_CLK_OMAP_HSDIVIDER(_name, _parent_name, \
111 _parent_ptr, _flags, \
112 _clksel_reg, _clksel_mask) \
113 static const struct clksel _name##_div[] = { \
114 { \
115 .parent = _parent_ptr, \
116 .rates = div31_1to31_rates \
117 }, \
118 { .parent = NULL }, \
119 }; \
120 static struct clk _name; \
121 static const char *_name##_parent_names[] = { \
122 _parent_name, \
123 }; \
124 static struct clk_hw_omap _name##_hw = { \
125 .hw = { \
126 .clk = &_name, \
127 }, \
128 .clksel = _name##_div, \
129 .clksel_reg = _clksel_reg, \
130 .clksel_mask = _clksel_mask, \
131 .ops = &clkhwops_omap4_dpllmx, \
132 }; \
133 DEFINE_STRUCT_CLK(_name, _name##_parent_names, omap_hsdivider_ops);
92 134
93/* struct clksel_rate.flags possibilities */ 135/* struct clksel_rate.flags possibilities */
94#define RATE_IN_242X (1 << 0) 136#define RATE_IN_242X (1 << 0)
@@ -229,22 +271,10 @@ struct dpll_data {
229#define CLOCK_CLKOUTX2 (1 << 5) 271#define CLOCK_CLKOUTX2 (1 << 5)
230 272
231/** 273/**
232 * struct clk - OMAP struct clk 274 * struct clk_hw_omap - OMAP struct clk
233 * @node: list_head connecting this clock into the full clock list 275 * @node: list_head connecting this clock into the full clock list
234 * @ops: struct clkops * for this clock
235 * @name: the name of the clock in the hardware (used in hwmod data and debug)
236 * @parent: pointer to this clock's parent struct clk
237 * @children: list_head connecting to the child clks' @sibling list_heads
238 * @sibling: list_head connecting this clk to its parent clk's @children
239 * @rate: current clock rate
240 * @enable_reg: register to write to enable the clock (see @enable_bit) 276 * @enable_reg: register to write to enable the clock (see @enable_bit)
241 * @recalc: fn ptr that returns the clock's current rate
242 * @set_rate: fn ptr that can change the clock's current rate
243 * @round_rate: fn ptr that can round the clock's current rate
244 * @init: fn ptr to do clock-specific initialization
245 * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg) 277 * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
246 * @usecount: number of users that have requested this clock to be enabled
247 * @fixed_div: when > 0, this clock's rate is its parent's rate / @fixed_div
248 * @flags: see "struct clk.flags possibilities" above 278 * @flags: see "struct clk.flags possibilities" above
249 * @clksel_reg: for clksel clks, register va containing src/divisor select 279 * @clksel_reg: for clksel clks, register va containing src/divisor select
250 * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector 280 * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector
@@ -258,39 +288,17 @@ struct dpll_data {
258 * XXX @rate_offset, @src_offset should probably be removed and OMAP1 288 * XXX @rate_offset, @src_offset should probably be removed and OMAP1
259 * clock code converted to use clksel. 289 * clock code converted to use clksel.
260 * 290 *
261 * XXX @usecount is poorly named. It should be "enable_count" or
262 * something similar. "users" in the description refers to kernel
263 * code (core code or drivers) that have called clk_enable() and not
264 * yet called clk_disable(); the usecount of parent clocks is also
265 * incremented by the clock code when clk_enable() is called on child
266 * clocks and decremented by the clock code when clk_disable() is
267 * called on child clocks.
268 *
269 * XXX @clkdm, @usecount, @children, @sibling should be marked for
270 * internal use only.
271 *
272 * @children and @sibling are used to optimize parent-to-child clock
273 * tree traversals. (child-to-parent traversals use @parent.)
274 *
275 * XXX The notion of the clock's current rate probably needs to be
276 * separated from the clock's target rate.
277 */ 291 */
278struct clk { 292
293struct clk_hw_omap_ops;
294
295struct clk_hw_omap {
296 struct clk_hw hw;
279 struct list_head node; 297 struct list_head node;
280 const struct clkops *ops; 298 unsigned long fixed_rate;
281 const char *name; 299 u8 fixed_div;
282 struct clk *parent;
283 struct list_head children;
284 struct list_head sibling; /* node for children */
285 unsigned long rate;
286 void __iomem *enable_reg; 300 void __iomem *enable_reg;
287 unsigned long (*recalc)(struct clk *);
288 int (*set_rate)(struct clk *, unsigned long);
289 long (*round_rate)(struct clk *, unsigned long);
290 void (*init)(struct clk *);
291 u8 enable_bit; 301 u8 enable_bit;
292 s8 usecount;
293 u8 fixed_div;
294 u8 flags; 302 u8 flags;
295 void __iomem *clksel_reg; 303 void __iomem *clksel_reg;
296 u32 clksel_mask; 304 u32 clksel_mask;
@@ -298,42 +306,22 @@ struct clk {
298 struct dpll_data *dpll_data; 306 struct dpll_data *dpll_data;
299 const char *clkdm_name; 307 const char *clkdm_name;
300 struct clockdomain *clkdm; 308 struct clockdomain *clkdm;
301#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) 309 const struct clk_hw_omap_ops *ops;
302 struct dentry *dent; /* For visible tree hierarchy */
303#endif
304}; 310};
305 311
306struct clk_functions { 312struct clk_hw_omap_ops {
307 int (*clk_enable)(struct clk *clk); 313 void (*find_idlest)(struct clk_hw_omap *oclk,
308 void (*clk_disable)(struct clk *clk); 314 void __iomem **idlest_reg,
309 long (*clk_round_rate)(struct clk *clk, unsigned long rate); 315 u8 *idlest_bit, u8 *idlest_val);
310 int (*clk_set_rate)(struct clk *clk, unsigned long rate); 316 void (*find_companion)(struct clk_hw_omap *oclk,
311 int (*clk_set_parent)(struct clk *clk, struct clk *parent); 317 void __iomem **other_reg,
312 void (*clk_allow_idle)(struct clk *clk); 318 u8 *other_bit);
313 void (*clk_deny_idle)(struct clk *clk); 319 void (*allow_idle)(struct clk_hw_omap *oclk);
314 void (*clk_disable_unused)(struct clk *clk); 320 void (*deny_idle)(struct clk_hw_omap *oclk);
315}; 321};
316 322
317extern int mpurate; 323unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw,
318 324 unsigned long parent_rate);
319extern int clk_init(struct clk_functions *custom_clocks);
320extern void clk_preinit(struct clk *clk);
321extern int clk_register(struct clk *clk);
322extern void clk_reparent(struct clk *child, struct clk *parent);
323extern void clk_unregister(struct clk *clk);
324extern void propagate_rate(struct clk *clk);
325extern void recalculate_root_clocks(void);
326extern unsigned long followparent_recalc(struct clk *clk);
327extern void clk_enable_init_clocks(void);
328unsigned long omap_fixed_divisor_recalc(struct clk *clk);
329extern struct clk *omap_clk_get_by_name(const char *name);
330extern int omap_clk_enable_autoidle_all(void);
331extern int omap_clk_disable_autoidle_all(void);
332
333extern const struct clkops clkops_null;
334
335extern struct clk dummy_ck;
336
337 325
338/* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */ 326/* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */
339#define CORE_CLK_SRC_32K 0x0 327#define CORE_CLK_SRC_32K 0x0
@@ -364,57 +352,62 @@ extern struct clk dummy_ck;
364/* DPLL Type and DCO Selection Flags */ 352/* DPLL Type and DCO Selection Flags */
365#define DPLL_J_TYPE 0x1 353#define DPLL_J_TYPE 0x1
366 354
367int omap2_clk_enable(struct clk *clk); 355long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
368void omap2_clk_disable(struct clk *clk); 356 unsigned long *parent_rate);
369long omap2_clk_round_rate(struct clk *clk, unsigned long rate); 357unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate);
370int omap2_clk_set_rate(struct clk *clk, unsigned long rate); 358int omap3_noncore_dpll_enable(struct clk_hw *hw);
371int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent); 359void omap3_noncore_dpll_disable(struct clk_hw *hw);
372long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate); 360int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
373unsigned long omap3_dpll_recalc(struct clk *clk); 361 unsigned long parent_rate);
374unsigned long omap3_clkoutx2_recalc(struct clk *clk); 362u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk);
375void omap3_dpll_allow_idle(struct clk *clk); 363void omap3_dpll_allow_idle(struct clk_hw_omap *clk);
376void omap3_dpll_deny_idle(struct clk *clk); 364void omap3_dpll_deny_idle(struct clk_hw_omap *clk);
377u32 omap3_dpll_autoidle_read(struct clk *clk); 365unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
378int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate); 366 unsigned long parent_rate);
379int omap3_noncore_dpll_enable(struct clk *clk); 367int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk);
380void omap3_noncore_dpll_disable(struct clk *clk); 368void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk);
381int omap4_dpllmx_gatectrl_read(struct clk *clk); 369void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk);
382void omap4_dpllmx_allow_gatectrl(struct clk *clk); 370unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
383void omap4_dpllmx_deny_gatectrl(struct clk *clk); 371 unsigned long parent_rate);
384long omap4_dpll_regm4xen_round_rate(struct clk *clk, unsigned long target_rate); 372long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
385unsigned long omap4_dpll_regm4xen_recalc(struct clk *clk); 373 unsigned long target_rate,
386 374 unsigned long *parent_rate);
387#ifdef CONFIG_OMAP_RESET_CLOCKS 375
388void omap2_clk_disable_unused(struct clk *clk); 376void omap2_init_clk_clkdm(struct clk_hw *clk);
389#else
390#define omap2_clk_disable_unused NULL
391#endif
392
393void omap2_init_clk_clkdm(struct clk *clk);
394void __init omap2_clk_disable_clkdm_control(void); 377void __init omap2_clk_disable_clkdm_control(void);
395 378
396/* clkt_clksel.c public functions */ 379/* clkt_clksel.c public functions */
397u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, 380u32 omap2_clksel_round_rate_div(struct clk_hw_omap *clk,
381 unsigned long target_rate,
398 u32 *new_div); 382 u32 *new_div);
399void omap2_init_clksel_parent(struct clk *clk); 383u8 omap2_clksel_find_parent_index(struct clk_hw *hw);
400unsigned long omap2_clksel_recalc(struct clk *clk); 384unsigned long omap2_clksel_recalc(struct clk_hw *hw, unsigned long parent_rate);
401long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate); 385long omap2_clksel_round_rate(struct clk_hw *hw, unsigned long target_rate,
402int omap2_clksel_set_rate(struct clk *clk, unsigned long rate); 386 unsigned long *parent_rate);
403int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent); 387int omap2_clksel_set_rate(struct clk_hw *hw, unsigned long rate,
388 unsigned long parent_rate);
389int omap2_clksel_set_parent(struct clk_hw *hw, u8 field_val);
404 390
405/* clkt_iclk.c public functions */ 391/* clkt_iclk.c public functions */
406extern void omap2_clkt_iclk_allow_idle(struct clk *clk); 392extern void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk);
407extern void omap2_clkt_iclk_deny_idle(struct clk *clk); 393extern void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk);
408 394
409u32 omap2_get_dpll_rate(struct clk *clk); 395u8 omap2_init_dpll_parent(struct clk_hw *hw);
410void omap2_init_dpll_parent(struct clk *clk); 396unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk);
411 397
412int omap2_dflt_clk_enable(struct clk *clk); 398int omap2_dflt_clk_enable(struct clk_hw *hw);
413void omap2_dflt_clk_disable(struct clk *clk); 399void omap2_dflt_clk_disable(struct clk_hw *hw);
414void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg, 400int omap2_dflt_clk_is_enabled(struct clk_hw *hw);
401void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk,
402 void __iomem **other_reg,
415 u8 *other_bit); 403 u8 *other_bit);
416void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg, 404void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
405 void __iomem **idlest_reg,
417 u8 *idlest_bit, u8 *idlest_val); 406 u8 *idlest_bit, u8 *idlest_val);
407void omap2_init_clk_hw_omap_clocks(struct clk *clk);
408int omap2_clk_enable_autoidle_all(void);
409int omap2_clk_disable_autoidle_all(void);
410void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
418int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name); 411int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name);
419void omap2_clk_print_new_rates(const char *hfclkin_ck_name, 412void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
420 const char *core_ck_name, 413 const char *core_ck_name,
@@ -432,28 +425,38 @@ extern const struct clksel_rate gpt_32k_rates[];
432extern const struct clksel_rate gpt_sys_rates[]; 425extern const struct clksel_rate gpt_sys_rates[];
433extern const struct clksel_rate gfx_l3_rates[]; 426extern const struct clksel_rate gfx_l3_rates[];
434extern const struct clksel_rate dsp_ick_rates[]; 427extern const struct clksel_rate dsp_ick_rates[];
428extern struct clk dummy_ck;
435 429
436extern const struct clkops clkops_omap2_iclk_dflt_wait; 430extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
437extern const struct clkops clkops_omap2_iclk_dflt; 431extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
438extern const struct clkops clkops_omap2_iclk_idle_only; 432extern const struct clk_hw_omap_ops clkhwops_wait;
439extern const struct clkops clkops_omap2_mdmclk_dflt_wait; 433extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
440extern const struct clkops clkops_omap2xxx_dpll_ops; 434extern const struct clk_hw_omap_ops clkhwops_iclk;
441extern const struct clkops clkops_omap3_noncore_dpll_ops; 435extern const struct clk_hw_omap_ops clkhwops_omap3430es2_ssi_wait;
442extern const struct clkops clkops_omap3_core_dpll_ops; 436extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait;
443extern const struct clkops clkops_omap4_dpllmx_ops; 437extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait;
438extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait;
439extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait;
440extern const struct clk_hw_omap_ops clkhwops_omap3430es2_hsotgusb_wait;
441extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait;
442extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait;
443extern const struct clk_hw_omap_ops clkhwops_apll54;
444extern const struct clk_hw_omap_ops clkhwops_apll96;
445extern const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll;
446extern const struct clk_hw_omap_ops clkhwops_omap2430_i2chs_wait;
444 447
445/* clksel_rate blocks shared between OMAP44xx and AM33xx */ 448/* clksel_rate blocks shared between OMAP44xx and AM33xx */
446extern const struct clksel_rate div_1_0_rates[]; 449extern const struct clksel_rate div_1_0_rates[];
450extern const struct clksel_rate div3_1to4_rates[];
447extern const struct clksel_rate div_1_1_rates[]; 451extern const struct clksel_rate div_1_1_rates[];
448extern const struct clksel_rate div_1_2_rates[]; 452extern const struct clksel_rate div_1_2_rates[];
449extern const struct clksel_rate div_1_3_rates[]; 453extern const struct clksel_rate div_1_3_rates[];
450extern const struct clksel_rate div_1_4_rates[]; 454extern const struct clksel_rate div_1_4_rates[];
451extern const struct clksel_rate div31_1to31_rates[]; 455extern const struct clksel_rate div31_1to31_rates[];
452 456
453/* clocks shared between various OMAP SoCs */
454extern struct clk virt_19200000_ck;
455extern struct clk virt_26000000_ck;
456
457extern int am33xx_clk_init(void); 457extern int am33xx_clk_init(void);
458 458
459extern int omap2_clkops_enable_clkdm(struct clk_hw *hw);
460extern void omap2_clkops_disable_clkdm(struct clk_hw *hw);
461
459#endif 462#endif
diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c
deleted file mode 100644
index 608874b651e8..000000000000
--- a/arch/arm/mach-omap2/clock2420_data.c
+++ /dev/null
@@ -1,1972 +0,0 @@
1/*
2 * OMAP2420 clock data
3 *
4 * Copyright (C) 2005-2009, 2012 Texas Instruments, Inc.
5 * Copyright (C) 2004-2011 Nokia Corporation
6 *
7 * Contacts:
8 * Richard Woodruff <r-woodruff2@ti.com>
9 * Paul Walmsley
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#include <linux/kernel.h>
17#include <linux/io.h>
18#include <linux/clk.h>
19#include <linux/list.h>
20
21#include "soc.h"
22#include "iomap.h"
23#include "clock.h"
24#include "clock2xxx.h"
25#include "opp2xxx.h"
26#include "cm2xxx.h"
27#include "prm2xxx_3xxx.h"
28#include "prm-regbits-24xx.h"
29#include "cm-regbits-24xx.h"
30#include "sdrc.h"
31#include "control.h"
32
33#define OMAP_CM_REGADDR OMAP2420_CM_REGADDR
34
35/*
36 * 2420 clock tree.
37 *
38 * NOTE:In many cases here we are assigning a 'default' parent. In
39 * many cases the parent is selectable. The set parent calls will
40 * also switch sources.
41 *
42 * Several sources are given initial rates which may be wrong, this will
43 * be fixed up in the init func.
44 *
45 * Things are broadly separated below by clock domains. It is
46 * noteworthy that most peripherals have dependencies on multiple clock
47 * domains. Many get their interface clocks from the L4 domain, but get
48 * functional clocks from fixed sources or other core domain derived
49 * clocks.
50 */
51
52/* Base external input clocks */
53static struct clk func_32k_ck = {
54 .name = "func_32k_ck",
55 .ops = &clkops_null,
56 .rate = 32768,
57 .clkdm_name = "wkup_clkdm",
58};
59
60static struct clk secure_32k_ck = {
61 .name = "secure_32k_ck",
62 .ops = &clkops_null,
63 .rate = 32768,
64 .clkdm_name = "wkup_clkdm",
65};
66
67/* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
68static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */
69 .name = "osc_ck",
70 .ops = &clkops_oscck,
71 .clkdm_name = "wkup_clkdm",
72 .recalc = &omap2_osc_clk_recalc,
73};
74
75/* Without modem likely 12MHz, with modem likely 13MHz */
76static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */
77 .name = "sys_ck", /* ~ ref_clk also */
78 .ops = &clkops_null,
79 .parent = &osc_ck,
80 .clkdm_name = "wkup_clkdm",
81 .recalc = &omap2xxx_sys_clk_recalc,
82};
83
84static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */
85 .name = "alt_ck",
86 .ops = &clkops_null,
87 .rate = 54000000,
88 .clkdm_name = "wkup_clkdm",
89};
90
91/* Optional external clock input for McBSP CLKS */
92static struct clk mcbsp_clks = {
93 .name = "mcbsp_clks",
94 .ops = &clkops_null,
95};
96
97/*
98 * Analog domain root source clocks
99 */
100
101/* dpll_ck, is broken out in to special cases through clksel */
102/* REVISIT: Rate changes on dpll_ck trigger a full set change. ...
103 * deal with this
104 */
105
106static struct dpll_data dpll_dd = {
107 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
108 .mult_mask = OMAP24XX_DPLL_MULT_MASK,
109 .div1_mask = OMAP24XX_DPLL_DIV_MASK,
110 .clk_bypass = &sys_ck,
111 .clk_ref = &sys_ck,
112 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
113 .enable_mask = OMAP24XX_EN_DPLL_MASK,
114 .max_multiplier = 1023,
115 .min_divider = 1,
116 .max_divider = 16,
117};
118
119/*
120 * XXX Cannot add round_rate here yet, as this is still a composite clock,
121 * not just a DPLL
122 */
123static struct clk dpll_ck = {
124 .name = "dpll_ck",
125 .ops = &clkops_omap2xxx_dpll_ops,
126 .parent = &sys_ck, /* Can be func_32k also */
127 .init = &omap2xxx_clkt_dpllcore_init,
128 .dpll_data = &dpll_dd,
129 .clkdm_name = "wkup_clkdm",
130 .recalc = &omap2_dpllcore_recalc,
131 .set_rate = &omap2_reprogram_dpllcore,
132};
133
134static struct clk apll96_ck = {
135 .name = "apll96_ck",
136 .ops = &clkops_apll96,
137 .parent = &sys_ck,
138 .rate = 96000000,
139 .flags = ENABLE_ON_INIT,
140 .clkdm_name = "wkup_clkdm",
141 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
142 .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT,
143};
144
145static struct clk apll54_ck = {
146 .name = "apll54_ck",
147 .ops = &clkops_apll54,
148 .parent = &sys_ck,
149 .rate = 54000000,
150 .flags = ENABLE_ON_INIT,
151 .clkdm_name = "wkup_clkdm",
152 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
153 .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT,
154};
155
156/*
157 * PRCM digital base sources
158 */
159
160/* func_54m_ck */
161
162static const struct clksel_rate func_54m_apll54_rates[] = {
163 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
164 { .div = 0 },
165};
166
167static const struct clksel_rate func_54m_alt_rates[] = {
168 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
169 { .div = 0 },
170};
171
172static const struct clksel func_54m_clksel[] = {
173 { .parent = &apll54_ck, .rates = func_54m_apll54_rates, },
174 { .parent = &alt_ck, .rates = func_54m_alt_rates, },
175 { .parent = NULL },
176};
177
178static struct clk func_54m_ck = {
179 .name = "func_54m_ck",
180 .ops = &clkops_null,
181 .parent = &apll54_ck, /* can also be alt_clk */
182 .clkdm_name = "wkup_clkdm",
183 .init = &omap2_init_clksel_parent,
184 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
185 .clksel_mask = OMAP24XX_54M_SOURCE_MASK,
186 .clksel = func_54m_clksel,
187 .recalc = &omap2_clksel_recalc,
188};
189
190static struct clk core_ck = {
191 .name = "core_ck",
192 .ops = &clkops_null,
193 .parent = &dpll_ck, /* can also be 32k */
194 .clkdm_name = "wkup_clkdm",
195 .recalc = &followparent_recalc,
196};
197
198static struct clk func_96m_ck = {
199 .name = "func_96m_ck",
200 .ops = &clkops_null,
201 .parent = &apll96_ck,
202 .clkdm_name = "wkup_clkdm",
203 .recalc = &followparent_recalc,
204};
205
206/* func_48m_ck */
207
208static const struct clksel_rate func_48m_apll96_rates[] = {
209 { .div = 2, .val = 0, .flags = RATE_IN_24XX },
210 { .div = 0 },
211};
212
213static const struct clksel_rate func_48m_alt_rates[] = {
214 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
215 { .div = 0 },
216};
217
218static const struct clksel func_48m_clksel[] = {
219 { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
220 { .parent = &alt_ck, .rates = func_48m_alt_rates },
221 { .parent = NULL }
222};
223
224static struct clk func_48m_ck = {
225 .name = "func_48m_ck",
226 .ops = &clkops_null,
227 .parent = &apll96_ck, /* 96M or Alt */
228 .clkdm_name = "wkup_clkdm",
229 .init = &omap2_init_clksel_parent,
230 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
231 .clksel_mask = OMAP24XX_48M_SOURCE_MASK,
232 .clksel = func_48m_clksel,
233 .recalc = &omap2_clksel_recalc,
234 .round_rate = &omap2_clksel_round_rate,
235 .set_rate = &omap2_clksel_set_rate
236};
237
238static struct clk func_12m_ck = {
239 .name = "func_12m_ck",
240 .ops = &clkops_null,
241 .parent = &func_48m_ck,
242 .fixed_div = 4,
243 .clkdm_name = "wkup_clkdm",
244 .recalc = &omap_fixed_divisor_recalc,
245};
246
247/* Secure timer, only available in secure mode */
248static struct clk wdt1_osc_ck = {
249 .name = "ck_wdt1_osc",
250 .ops = &clkops_null, /* RMK: missing? */
251 .parent = &osc_ck,
252 .recalc = &followparent_recalc,
253};
254
255/*
256 * The common_clkout* clksel_rate structs are common to
257 * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src.
258 * sys_clkout2_* are 2420-only, so the
259 * clksel_rate flags fields are inaccurate for those clocks. This is
260 * harmless since access to those clocks are gated by the struct clk
261 * flags fields, which mark them as 2420-only.
262 */
263static const struct clksel_rate common_clkout_src_core_rates[] = {
264 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
265 { .div = 0 }
266};
267
268static const struct clksel_rate common_clkout_src_sys_rates[] = {
269 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
270 { .div = 0 }
271};
272
273static const struct clksel_rate common_clkout_src_96m_rates[] = {
274 { .div = 1, .val = 2, .flags = RATE_IN_24XX },
275 { .div = 0 }
276};
277
278static const struct clksel_rate common_clkout_src_54m_rates[] = {
279 { .div = 1, .val = 3, .flags = RATE_IN_24XX },
280 { .div = 0 }
281};
282
283static const struct clksel common_clkout_src_clksel[] = {
284 { .parent = &core_ck, .rates = common_clkout_src_core_rates },
285 { .parent = &sys_ck, .rates = common_clkout_src_sys_rates },
286 { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
287 { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
288 { .parent = NULL }
289};
290
291static struct clk sys_clkout_src = {
292 .name = "sys_clkout_src",
293 .ops = &clkops_omap2_dflt,
294 .parent = &func_54m_ck,
295 .clkdm_name = "wkup_clkdm",
296 .enable_reg = OMAP2420_PRCM_CLKOUT_CTRL,
297 .enable_bit = OMAP24XX_CLKOUT_EN_SHIFT,
298 .init = &omap2_init_clksel_parent,
299 .clksel_reg = OMAP2420_PRCM_CLKOUT_CTRL,
300 .clksel_mask = OMAP24XX_CLKOUT_SOURCE_MASK,
301 .clksel = common_clkout_src_clksel,
302 .recalc = &omap2_clksel_recalc,
303 .round_rate = &omap2_clksel_round_rate,
304 .set_rate = &omap2_clksel_set_rate
305};
306
307static const struct clksel_rate common_clkout_rates[] = {
308 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
309 { .div = 2, .val = 1, .flags = RATE_IN_24XX },
310 { .div = 4, .val = 2, .flags = RATE_IN_24XX },
311 { .div = 8, .val = 3, .flags = RATE_IN_24XX },
312 { .div = 16, .val = 4, .flags = RATE_IN_24XX },
313 { .div = 0 },
314};
315
316static const struct clksel sys_clkout_clksel[] = {
317 { .parent = &sys_clkout_src, .rates = common_clkout_rates },
318 { .parent = NULL }
319};
320
321static struct clk sys_clkout = {
322 .name = "sys_clkout",
323 .ops = &clkops_null,
324 .parent = &sys_clkout_src,
325 .clkdm_name = "wkup_clkdm",
326 .clksel_reg = OMAP2420_PRCM_CLKOUT_CTRL,
327 .clksel_mask = OMAP24XX_CLKOUT_DIV_MASK,
328 .clksel = sys_clkout_clksel,
329 .recalc = &omap2_clksel_recalc,
330 .round_rate = &omap2_clksel_round_rate,
331 .set_rate = &omap2_clksel_set_rate
332};
333
334/* In 2430, new in 2420 ES2 */
335static struct clk sys_clkout2_src = {
336 .name = "sys_clkout2_src",
337 .ops = &clkops_omap2_dflt,
338 .parent = &func_54m_ck,
339 .clkdm_name = "wkup_clkdm",
340 .enable_reg = OMAP2420_PRCM_CLKOUT_CTRL,
341 .enable_bit = OMAP2420_CLKOUT2_EN_SHIFT,
342 .init = &omap2_init_clksel_parent,
343 .clksel_reg = OMAP2420_PRCM_CLKOUT_CTRL,
344 .clksel_mask = OMAP2420_CLKOUT2_SOURCE_MASK,
345 .clksel = common_clkout_src_clksel,
346 .recalc = &omap2_clksel_recalc,
347 .round_rate = &omap2_clksel_round_rate,
348 .set_rate = &omap2_clksel_set_rate
349};
350
351static const struct clksel sys_clkout2_clksel[] = {
352 { .parent = &sys_clkout2_src, .rates = common_clkout_rates },
353 { .parent = NULL }
354};
355
356/* In 2430, new in 2420 ES2 */
357static struct clk sys_clkout2 = {
358 .name = "sys_clkout2",
359 .ops = &clkops_null,
360 .parent = &sys_clkout2_src,
361 .clkdm_name = "wkup_clkdm",
362 .clksel_reg = OMAP2420_PRCM_CLKOUT_CTRL,
363 .clksel_mask = OMAP2420_CLKOUT2_DIV_MASK,
364 .clksel = sys_clkout2_clksel,
365 .recalc = &omap2_clksel_recalc,
366 .round_rate = &omap2_clksel_round_rate,
367 .set_rate = &omap2_clksel_set_rate
368};
369
370static struct clk emul_ck = {
371 .name = "emul_ck",
372 .ops = &clkops_omap2_dflt,
373 .parent = &func_54m_ck,
374 .clkdm_name = "wkup_clkdm",
375 .enable_reg = OMAP2420_PRCM_CLKEMUL_CTRL,
376 .enable_bit = OMAP24XX_EMULATION_EN_SHIFT,
377 .recalc = &followparent_recalc,
378
379};
380
381/*
382 * MPU clock domain
383 * Clocks:
384 * MPU_FCLK, MPU_ICLK
385 * INT_M_FCLK, INT_M_I_CLK
386 *
387 * - Individual clocks are hardware managed.
388 * - Base divider comes from: CM_CLKSEL_MPU
389 *
390 */
391static const struct clksel_rate mpu_core_rates[] = {
392 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
393 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
394 { .div = 4, .val = 4, .flags = RATE_IN_242X },
395 { .div = 6, .val = 6, .flags = RATE_IN_242X },
396 { .div = 8, .val = 8, .flags = RATE_IN_242X },
397 { .div = 0 },
398};
399
400static const struct clksel mpu_clksel[] = {
401 { .parent = &core_ck, .rates = mpu_core_rates },
402 { .parent = NULL }
403};
404
405static struct clk mpu_ck = { /* Control cpu */
406 .name = "mpu_ck",
407 .ops = &clkops_null,
408 .parent = &core_ck,
409 .clkdm_name = "mpu_clkdm",
410 .init = &omap2_init_clksel_parent,
411 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
412 .clksel_mask = OMAP24XX_CLKSEL_MPU_MASK,
413 .clksel = mpu_clksel,
414 .recalc = &omap2_clksel_recalc,
415};
416
417/*
418 * DSP (2420-UMA+IVA1) clock domain
419 * Clocks:
420 * 2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP
421 *
422 * Won't be too specific here. The core clock comes into this block
423 * it is divided then tee'ed. One branch goes directly to xyz enable
424 * controls. The other branch gets further divided by 2 then possibly
425 * routed into a synchronizer and out of clocks abc.
426 */
427static const struct clksel_rate dsp_fck_core_rates[] = {
428 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
429 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
430 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
431 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
432 { .div = 6, .val = 6, .flags = RATE_IN_242X },
433 { .div = 8, .val = 8, .flags = RATE_IN_242X },
434 { .div = 12, .val = 12, .flags = RATE_IN_242X },
435 { .div = 0 },
436};
437
438static const struct clksel dsp_fck_clksel[] = {
439 { .parent = &core_ck, .rates = dsp_fck_core_rates },
440 { .parent = NULL }
441};
442
443static struct clk dsp_fck = {
444 .name = "dsp_fck",
445 .ops = &clkops_omap2_dflt_wait,
446 .parent = &core_ck,
447 .clkdm_name = "dsp_clkdm",
448 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
449 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
450 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
451 .clksel_mask = OMAP24XX_CLKSEL_DSP_MASK,
452 .clksel = dsp_fck_clksel,
453 .recalc = &omap2_clksel_recalc,
454};
455
456static const struct clksel dsp_ick_clksel[] = {
457 { .parent = &dsp_fck, .rates = dsp_ick_rates },
458 { .parent = NULL }
459};
460
461static struct clk dsp_ick = {
462 .name = "dsp_ick", /* apparently ipi and isp */
463 .ops = &clkops_omap2_iclk_dflt_wait,
464 .parent = &dsp_fck,
465 .clkdm_name = "dsp_clkdm",
466 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
467 .enable_bit = OMAP2420_EN_DSP_IPI_SHIFT, /* for ipi */
468 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
469 .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK,
470 .clksel = dsp_ick_clksel,
471 .recalc = &omap2_clksel_recalc,
472};
473
474/*
475 * The IVA1 is an ARM7 core on the 2420 that has nothing to do with
476 * the C54x, but which is contained in the DSP powerdomain. Does not
477 * exist on later OMAPs.
478 */
479static struct clk iva1_ifck = {
480 .name = "iva1_ifck",
481 .ops = &clkops_omap2_dflt_wait,
482 .parent = &core_ck,
483 .clkdm_name = "iva1_clkdm",
484 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
485 .enable_bit = OMAP2420_EN_IVA_COP_SHIFT,
486 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
487 .clksel_mask = OMAP2420_CLKSEL_IVA_MASK,
488 .clksel = dsp_fck_clksel,
489 .recalc = &omap2_clksel_recalc,
490};
491
492/* IVA1 mpu/int/i/f clocks are /2 of parent */
493static struct clk iva1_mpu_int_ifck = {
494 .name = "iva1_mpu_int_ifck",
495 .ops = &clkops_omap2_dflt_wait,
496 .parent = &iva1_ifck,
497 .clkdm_name = "iva1_clkdm",
498 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
499 .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT,
500 .fixed_div = 2,
501 .recalc = &omap_fixed_divisor_recalc,
502};
503
504/*
505 * L3 clock domain
506 * L3 clocks are used for both interface and functional clocks to
507 * multiple entities. Some of these clocks are completely managed
508 * by hardware, and some others allow software control. Hardware
509 * managed ones general are based on directly CLK_REQ signals and
510 * various auto idle settings. The functional spec sets many of these
511 * as 'tie-high' for their enables.
512 *
513 * I-CLOCKS:
514 * L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
515 * CAM, HS-USB.
516 * F-CLOCK
517 * SSI.
518 *
519 * GPMC memories and SDRC have timing and clock sensitive registers which
520 * may very well need notification when the clock changes. Currently for low
521 * operating points, these are taken care of in sleep.S.
522 */
523static const struct clksel_rate core_l3_core_rates[] = {
524 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
525 { .div = 2, .val = 2, .flags = RATE_IN_242X },
526 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
527 { .div = 6, .val = 6, .flags = RATE_IN_24XX },
528 { .div = 8, .val = 8, .flags = RATE_IN_242X },
529 { .div = 12, .val = 12, .flags = RATE_IN_242X },
530 { .div = 16, .val = 16, .flags = RATE_IN_242X },
531 { .div = 0 }
532};
533
534static const struct clksel core_l3_clksel[] = {
535 { .parent = &core_ck, .rates = core_l3_core_rates },
536 { .parent = NULL }
537};
538
539static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */
540 .name = "core_l3_ck",
541 .ops = &clkops_null,
542 .parent = &core_ck,
543 .clkdm_name = "core_l3_clkdm",
544 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
545 .clksel_mask = OMAP24XX_CLKSEL_L3_MASK,
546 .clksel = core_l3_clksel,
547 .recalc = &omap2_clksel_recalc,
548};
549
550/* usb_l4_ick */
551static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
552 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
553 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
554 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
555 { .div = 0 }
556};
557
558static const struct clksel usb_l4_ick_clksel[] = {
559 { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
560 { .parent = NULL },
561};
562
563/* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */
564static struct clk usb_l4_ick = { /* FS-USB interface clock */
565 .name = "usb_l4_ick",
566 .ops = &clkops_omap2_iclk_dflt_wait,
567 .parent = &core_l3_ck,
568 .clkdm_name = "core_l4_clkdm",
569 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
570 .enable_bit = OMAP24XX_EN_USB_SHIFT,
571 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
572 .clksel_mask = OMAP24XX_CLKSEL_USB_MASK,
573 .clksel = usb_l4_ick_clksel,
574 .recalc = &omap2_clksel_recalc,
575};
576
577/*
578 * L4 clock management domain
579 *
580 * This domain contains lots of interface clocks from the L4 interface, some
581 * functional clocks. Fixed APLL functional source clocks are managed in
582 * this domain.
583 */
584static const struct clksel_rate l4_core_l3_rates[] = {
585 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
586 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
587 { .div = 0 }
588};
589
590static const struct clksel l4_clksel[] = {
591 { .parent = &core_l3_ck, .rates = l4_core_l3_rates },
592 { .parent = NULL }
593};
594
595static struct clk l4_ck = { /* used both as an ick and fck */
596 .name = "l4_ck",
597 .ops = &clkops_null,
598 .parent = &core_l3_ck,
599 .clkdm_name = "core_l4_clkdm",
600 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
601 .clksel_mask = OMAP24XX_CLKSEL_L4_MASK,
602 .clksel = l4_clksel,
603 .recalc = &omap2_clksel_recalc,
604};
605
606/*
607 * SSI is in L3 management domain, its direct parent is core not l3,
608 * many core power domain entities are grouped into the L3 clock
609 * domain.
610 * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_ICLK
611 *
612 * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
613 */
614static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
615 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
616 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
617 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
618 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
619 { .div = 6, .val = 6, .flags = RATE_IN_242X },
620 { .div = 8, .val = 8, .flags = RATE_IN_242X },
621 { .div = 0 }
622};
623
624static const struct clksel ssi_ssr_sst_fck_clksel[] = {
625 { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
626 { .parent = NULL }
627};
628
629static struct clk ssi_ssr_sst_fck = {
630 .name = "ssi_fck",
631 .ops = &clkops_omap2_dflt_wait,
632 .parent = &core_ck,
633 .clkdm_name = "core_l3_clkdm",
634 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
635 .enable_bit = OMAP24XX_EN_SSI_SHIFT,
636 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
637 .clksel_mask = OMAP24XX_CLKSEL_SSI_MASK,
638 .clksel = ssi_ssr_sst_fck_clksel,
639 .recalc = &omap2_clksel_recalc,
640};
641
642/*
643 * Presumably this is the same as SSI_ICLK.
644 * TRM contradicts itself on what clockdomain SSI_ICLK is in
645 */
646static struct clk ssi_l4_ick = {
647 .name = "ssi_l4_ick",
648 .ops = &clkops_omap2_iclk_dflt_wait,
649 .parent = &l4_ck,
650 .clkdm_name = "core_l4_clkdm",
651 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
652 .enable_bit = OMAP24XX_EN_SSI_SHIFT,
653 .recalc = &followparent_recalc,
654};
655
656
657/*
658 * GFX clock domain
659 * Clocks:
660 * GFX_FCLK, GFX_ICLK
661 * GFX_CG1(2d), GFX_CG2(3d)
662 *
663 * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
664 * The 2d and 3d clocks run at a hardware determined
665 * divided value of fclk.
666 *
667 */
668
669/* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */
670static const struct clksel gfx_fck_clksel[] = {
671 { .parent = &core_l3_ck, .rates = gfx_l3_rates },
672 { .parent = NULL },
673};
674
675static struct clk gfx_3d_fck = {
676 .name = "gfx_3d_fck",
677 .ops = &clkops_omap2_dflt_wait,
678 .parent = &core_l3_ck,
679 .clkdm_name = "gfx_clkdm",
680 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
681 .enable_bit = OMAP24XX_EN_3D_SHIFT,
682 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
683 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
684 .clksel = gfx_fck_clksel,
685 .recalc = &omap2_clksel_recalc,
686 .round_rate = &omap2_clksel_round_rate,
687 .set_rate = &omap2_clksel_set_rate
688};
689
690static struct clk gfx_2d_fck = {
691 .name = "gfx_2d_fck",
692 .ops = &clkops_omap2_dflt_wait,
693 .parent = &core_l3_ck,
694 .clkdm_name = "gfx_clkdm",
695 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
696 .enable_bit = OMAP24XX_EN_2D_SHIFT,
697 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
698 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
699 .clksel = gfx_fck_clksel,
700 .recalc = &omap2_clksel_recalc,
701};
702
703/* This interface clock does not have a CM_AUTOIDLE bit */
704static struct clk gfx_ick = {
705 .name = "gfx_ick", /* From l3 */
706 .ops = &clkops_omap2_dflt_wait,
707 .parent = &core_l3_ck,
708 .clkdm_name = "gfx_clkdm",
709 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
710 .enable_bit = OMAP_EN_GFX_SHIFT,
711 .recalc = &followparent_recalc,
712};
713
714/*
715 * DSS clock domain
716 * CLOCKs:
717 * DSS_L4_ICLK, DSS_L3_ICLK,
718 * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
719 *
720 * DSS is both initiator and target.
721 */
722/* XXX Add RATE_NOT_VALIDATED */
723
724static const struct clksel_rate dss1_fck_sys_rates[] = {
725 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
726 { .div = 0 }
727};
728
729static const struct clksel_rate dss1_fck_core_rates[] = {
730 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
731 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
732 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
733 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
734 { .div = 5, .val = 5, .flags = RATE_IN_24XX },
735 { .div = 6, .val = 6, .flags = RATE_IN_24XX },
736 { .div = 8, .val = 8, .flags = RATE_IN_24XX },
737 { .div = 9, .val = 9, .flags = RATE_IN_24XX },
738 { .div = 12, .val = 12, .flags = RATE_IN_24XX },
739 { .div = 16, .val = 16, .flags = RATE_IN_24XX },
740 { .div = 0 }
741};
742
743static const struct clksel dss1_fck_clksel[] = {
744 { .parent = &sys_ck, .rates = dss1_fck_sys_rates },
745 { .parent = &core_ck, .rates = dss1_fck_core_rates },
746 { .parent = NULL },
747};
748
749static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */
750 .name = "dss_ick",
751 .ops = &clkops_omap2_iclk_dflt,
752 .parent = &l4_ck, /* really both l3 and l4 */
753 .clkdm_name = "dss_clkdm",
754 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
755 .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
756 .recalc = &followparent_recalc,
757};
758
759static struct clk dss1_fck = {
760 .name = "dss1_fck",
761 .ops = &clkops_omap2_dflt,
762 .parent = &core_ck, /* Core or sys */
763 .clkdm_name = "dss_clkdm",
764 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
765 .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
766 .init = &omap2_init_clksel_parent,
767 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
768 .clksel_mask = OMAP24XX_CLKSEL_DSS1_MASK,
769 .clksel = dss1_fck_clksel,
770 .recalc = &omap2_clksel_recalc,
771};
772
773static const struct clksel_rate dss2_fck_sys_rates[] = {
774 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
775 { .div = 0 }
776};
777
778static const struct clksel_rate dss2_fck_48m_rates[] = {
779 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
780 { .div = 0 }
781};
782
783static const struct clksel dss2_fck_clksel[] = {
784 { .parent = &sys_ck, .rates = dss2_fck_sys_rates },
785 { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
786 { .parent = NULL }
787};
788
789static struct clk dss2_fck = { /* Alt clk used in power management */
790 .name = "dss2_fck",
791 .ops = &clkops_omap2_dflt,
792 .parent = &sys_ck, /* fixed at sys_ck or 48MHz */
793 .clkdm_name = "dss_clkdm",
794 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
795 .enable_bit = OMAP24XX_EN_DSS2_SHIFT,
796 .init = &omap2_init_clksel_parent,
797 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
798 .clksel_mask = OMAP24XX_CLKSEL_DSS2_MASK,
799 .clksel = dss2_fck_clksel,
800 .recalc = &omap2_clksel_recalc,
801};
802
803static struct clk dss_54m_fck = { /* Alt clk used in power management */
804 .name = "dss_54m_fck", /* 54m tv clk */
805 .ops = &clkops_omap2_dflt_wait,
806 .parent = &func_54m_ck,
807 .clkdm_name = "dss_clkdm",
808 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
809 .enable_bit = OMAP24XX_EN_TV_SHIFT,
810 .recalc = &followparent_recalc,
811};
812
813static struct clk wu_l4_ick = {
814 .name = "wu_l4_ick",
815 .ops = &clkops_null,
816 .parent = &sys_ck,
817 .clkdm_name = "wkup_clkdm",
818 .recalc = &followparent_recalc,
819};
820
821/*
822 * CORE power domain ICLK & FCLK defines.
823 * Many of the these can have more than one possible parent. Entries
824 * here will likely have an L4 interface parent, and may have multiple
825 * functional clock parents.
826 */
827static const struct clksel_rate gpt_alt_rates[] = {
828 { .div = 1, .val = 2, .flags = RATE_IN_24XX },
829 { .div = 0 }
830};
831
832static const struct clksel omap24xx_gpt_clksel[] = {
833 { .parent = &func_32k_ck, .rates = gpt_32k_rates },
834 { .parent = &sys_ck, .rates = gpt_sys_rates },
835 { .parent = &alt_ck, .rates = gpt_alt_rates },
836 { .parent = NULL },
837};
838
839static struct clk gpt1_ick = {
840 .name = "gpt1_ick",
841 .ops = &clkops_omap2_iclk_dflt_wait,
842 .parent = &wu_l4_ick,
843 .clkdm_name = "wkup_clkdm",
844 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
845 .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
846 .recalc = &followparent_recalc,
847};
848
849static struct clk gpt1_fck = {
850 .name = "gpt1_fck",
851 .ops = &clkops_omap2_dflt_wait,
852 .parent = &func_32k_ck,
853 .clkdm_name = "core_l4_clkdm",
854 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
855 .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
856 .init = &omap2_init_clksel_parent,
857 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1),
858 .clksel_mask = OMAP24XX_CLKSEL_GPT1_MASK,
859 .clksel = omap24xx_gpt_clksel,
860 .recalc = &omap2_clksel_recalc,
861 .round_rate = &omap2_clksel_round_rate,
862 .set_rate = &omap2_clksel_set_rate
863};
864
865static struct clk gpt2_ick = {
866 .name = "gpt2_ick",
867 .ops = &clkops_omap2_iclk_dflt_wait,
868 .parent = &l4_ck,
869 .clkdm_name = "core_l4_clkdm",
870 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
871 .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
872 .recalc = &followparent_recalc,
873};
874
875static struct clk gpt2_fck = {
876 .name = "gpt2_fck",
877 .ops = &clkops_omap2_dflt_wait,
878 .parent = &func_32k_ck,
879 .clkdm_name = "core_l4_clkdm",
880 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
881 .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
882 .init = &omap2_init_clksel_parent,
883 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
884 .clksel_mask = OMAP24XX_CLKSEL_GPT2_MASK,
885 .clksel = omap24xx_gpt_clksel,
886 .recalc = &omap2_clksel_recalc,
887};
888
889static struct clk gpt3_ick = {
890 .name = "gpt3_ick",
891 .ops = &clkops_omap2_iclk_dflt_wait,
892 .parent = &l4_ck,
893 .clkdm_name = "core_l4_clkdm",
894 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
895 .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
896 .recalc = &followparent_recalc,
897};
898
899static struct clk gpt3_fck = {
900 .name = "gpt3_fck",
901 .ops = &clkops_omap2_dflt_wait,
902 .parent = &func_32k_ck,
903 .clkdm_name = "core_l4_clkdm",
904 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
905 .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
906 .init = &omap2_init_clksel_parent,
907 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
908 .clksel_mask = OMAP24XX_CLKSEL_GPT3_MASK,
909 .clksel = omap24xx_gpt_clksel,
910 .recalc = &omap2_clksel_recalc,
911};
912
913static struct clk gpt4_ick = {
914 .name = "gpt4_ick",
915 .ops = &clkops_omap2_iclk_dflt_wait,
916 .parent = &l4_ck,
917 .clkdm_name = "core_l4_clkdm",
918 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
919 .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
920 .recalc = &followparent_recalc,
921};
922
923static struct clk gpt4_fck = {
924 .name = "gpt4_fck",
925 .ops = &clkops_omap2_dflt_wait,
926 .parent = &func_32k_ck,
927 .clkdm_name = "core_l4_clkdm",
928 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
929 .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
930 .init = &omap2_init_clksel_parent,
931 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
932 .clksel_mask = OMAP24XX_CLKSEL_GPT4_MASK,
933 .clksel = omap24xx_gpt_clksel,
934 .recalc = &omap2_clksel_recalc,
935};
936
937static struct clk gpt5_ick = {
938 .name = "gpt5_ick",
939 .ops = &clkops_omap2_iclk_dflt_wait,
940 .parent = &l4_ck,
941 .clkdm_name = "core_l4_clkdm",
942 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
943 .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
944 .recalc = &followparent_recalc,
945};
946
947static struct clk gpt5_fck = {
948 .name = "gpt5_fck",
949 .ops = &clkops_omap2_dflt_wait,
950 .parent = &func_32k_ck,
951 .clkdm_name = "core_l4_clkdm",
952 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
953 .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
954 .init = &omap2_init_clksel_parent,
955 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
956 .clksel_mask = OMAP24XX_CLKSEL_GPT5_MASK,
957 .clksel = omap24xx_gpt_clksel,
958 .recalc = &omap2_clksel_recalc,
959};
960
961static struct clk gpt6_ick = {
962 .name = "gpt6_ick",
963 .ops = &clkops_omap2_iclk_dflt_wait,
964 .parent = &l4_ck,
965 .clkdm_name = "core_l4_clkdm",
966 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
967 .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
968 .recalc = &followparent_recalc,
969};
970
971static struct clk gpt6_fck = {
972 .name = "gpt6_fck",
973 .ops = &clkops_omap2_dflt_wait,
974 .parent = &func_32k_ck,
975 .clkdm_name = "core_l4_clkdm",
976 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
977 .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
978 .init = &omap2_init_clksel_parent,
979 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
980 .clksel_mask = OMAP24XX_CLKSEL_GPT6_MASK,
981 .clksel = omap24xx_gpt_clksel,
982 .recalc = &omap2_clksel_recalc,
983};
984
985static struct clk gpt7_ick = {
986 .name = "gpt7_ick",
987 .ops = &clkops_omap2_iclk_dflt_wait,
988 .parent = &l4_ck,
989 .clkdm_name = "core_l4_clkdm",
990 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
991 .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
992 .recalc = &followparent_recalc,
993};
994
995static struct clk gpt7_fck = {
996 .name = "gpt7_fck",
997 .ops = &clkops_omap2_dflt_wait,
998 .parent = &func_32k_ck,
999 .clkdm_name = "core_l4_clkdm",
1000 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1001 .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
1002 .init = &omap2_init_clksel_parent,
1003 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1004 .clksel_mask = OMAP24XX_CLKSEL_GPT7_MASK,
1005 .clksel = omap24xx_gpt_clksel,
1006 .recalc = &omap2_clksel_recalc,
1007};
1008
1009static struct clk gpt8_ick = {
1010 .name = "gpt8_ick",
1011 .ops = &clkops_omap2_iclk_dflt_wait,
1012 .parent = &l4_ck,
1013 .clkdm_name = "core_l4_clkdm",
1014 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1015 .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
1016 .recalc = &followparent_recalc,
1017};
1018
1019static struct clk gpt8_fck = {
1020 .name = "gpt8_fck",
1021 .ops = &clkops_omap2_dflt_wait,
1022 .parent = &func_32k_ck,
1023 .clkdm_name = "core_l4_clkdm",
1024 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1025 .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
1026 .init = &omap2_init_clksel_parent,
1027 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1028 .clksel_mask = OMAP24XX_CLKSEL_GPT8_MASK,
1029 .clksel = omap24xx_gpt_clksel,
1030 .recalc = &omap2_clksel_recalc,
1031};
1032
1033static struct clk gpt9_ick = {
1034 .name = "gpt9_ick",
1035 .ops = &clkops_omap2_iclk_dflt_wait,
1036 .parent = &l4_ck,
1037 .clkdm_name = "core_l4_clkdm",
1038 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1039 .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
1040 .recalc = &followparent_recalc,
1041};
1042
1043static struct clk gpt9_fck = {
1044 .name = "gpt9_fck",
1045 .ops = &clkops_omap2_dflt_wait,
1046 .parent = &func_32k_ck,
1047 .clkdm_name = "core_l4_clkdm",
1048 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1049 .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
1050 .init = &omap2_init_clksel_parent,
1051 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1052 .clksel_mask = OMAP24XX_CLKSEL_GPT9_MASK,
1053 .clksel = omap24xx_gpt_clksel,
1054 .recalc = &omap2_clksel_recalc,
1055};
1056
1057static struct clk gpt10_ick = {
1058 .name = "gpt10_ick",
1059 .ops = &clkops_omap2_iclk_dflt_wait,
1060 .parent = &l4_ck,
1061 .clkdm_name = "core_l4_clkdm",
1062 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1063 .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
1064 .recalc = &followparent_recalc,
1065};
1066
1067static struct clk gpt10_fck = {
1068 .name = "gpt10_fck",
1069 .ops = &clkops_omap2_dflt_wait,
1070 .parent = &func_32k_ck,
1071 .clkdm_name = "core_l4_clkdm",
1072 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1073 .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
1074 .init = &omap2_init_clksel_parent,
1075 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1076 .clksel_mask = OMAP24XX_CLKSEL_GPT10_MASK,
1077 .clksel = omap24xx_gpt_clksel,
1078 .recalc = &omap2_clksel_recalc,
1079};
1080
1081static struct clk gpt11_ick = {
1082 .name = "gpt11_ick",
1083 .ops = &clkops_omap2_iclk_dflt_wait,
1084 .parent = &l4_ck,
1085 .clkdm_name = "core_l4_clkdm",
1086 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1087 .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
1088 .recalc = &followparent_recalc,
1089};
1090
1091static struct clk gpt11_fck = {
1092 .name = "gpt11_fck",
1093 .ops = &clkops_omap2_dflt_wait,
1094 .parent = &func_32k_ck,
1095 .clkdm_name = "core_l4_clkdm",
1096 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1097 .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
1098 .init = &omap2_init_clksel_parent,
1099 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1100 .clksel_mask = OMAP24XX_CLKSEL_GPT11_MASK,
1101 .clksel = omap24xx_gpt_clksel,
1102 .recalc = &omap2_clksel_recalc,
1103};
1104
1105static struct clk gpt12_ick = {
1106 .name = "gpt12_ick",
1107 .ops = &clkops_omap2_iclk_dflt_wait,
1108 .parent = &l4_ck,
1109 .clkdm_name = "core_l4_clkdm",
1110 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1111 .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
1112 .recalc = &followparent_recalc,
1113};
1114
1115static struct clk gpt12_fck = {
1116 .name = "gpt12_fck",
1117 .ops = &clkops_omap2_dflt_wait,
1118 .parent = &secure_32k_ck,
1119 .clkdm_name = "core_l4_clkdm",
1120 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1121 .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
1122 .init = &omap2_init_clksel_parent,
1123 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1124 .clksel_mask = OMAP24XX_CLKSEL_GPT12_MASK,
1125 .clksel = omap24xx_gpt_clksel,
1126 .recalc = &omap2_clksel_recalc,
1127};
1128
1129static struct clk mcbsp1_ick = {
1130 .name = "mcbsp1_ick",
1131 .ops = &clkops_omap2_iclk_dflt_wait,
1132 .parent = &l4_ck,
1133 .clkdm_name = "core_l4_clkdm",
1134 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1135 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1136 .recalc = &followparent_recalc,
1137};
1138
1139static const struct clksel_rate common_mcbsp_96m_rates[] = {
1140 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
1141 { .div = 0 }
1142};
1143
1144static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1145 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1146 { .div = 0 }
1147};
1148
1149static const struct clksel mcbsp_fck_clksel[] = {
1150 { .parent = &func_96m_ck, .rates = common_mcbsp_96m_rates },
1151 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
1152 { .parent = NULL }
1153};
1154
1155static struct clk mcbsp1_fck = {
1156 .name = "mcbsp1_fck",
1157 .ops = &clkops_omap2_dflt_wait,
1158 .parent = &func_96m_ck,
1159 .init = &omap2_init_clksel_parent,
1160 .clkdm_name = "core_l4_clkdm",
1161 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1162 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1163 .clksel_reg = OMAP242X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1164 .clksel_mask = OMAP2_MCBSP1_CLKS_MASK,
1165 .clksel = mcbsp_fck_clksel,
1166 .recalc = &omap2_clksel_recalc,
1167};
1168
1169static struct clk mcbsp2_ick = {
1170 .name = "mcbsp2_ick",
1171 .ops = &clkops_omap2_iclk_dflt_wait,
1172 .parent = &l4_ck,
1173 .clkdm_name = "core_l4_clkdm",
1174 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1175 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1176 .recalc = &followparent_recalc,
1177};
1178
1179static struct clk mcbsp2_fck = {
1180 .name = "mcbsp2_fck",
1181 .ops = &clkops_omap2_dflt_wait,
1182 .parent = &func_96m_ck,
1183 .init = &omap2_init_clksel_parent,
1184 .clkdm_name = "core_l4_clkdm",
1185 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1186 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1187 .clksel_reg = OMAP242X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1188 .clksel_mask = OMAP2_MCBSP2_CLKS_MASK,
1189 .clksel = mcbsp_fck_clksel,
1190 .recalc = &omap2_clksel_recalc,
1191};
1192
1193static struct clk mcspi1_ick = {
1194 .name = "mcspi1_ick",
1195 .ops = &clkops_omap2_iclk_dflt_wait,
1196 .parent = &l4_ck,
1197 .clkdm_name = "core_l4_clkdm",
1198 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1199 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1200 .recalc = &followparent_recalc,
1201};
1202
1203static struct clk mcspi1_fck = {
1204 .name = "mcspi1_fck",
1205 .ops = &clkops_omap2_dflt_wait,
1206 .parent = &func_48m_ck,
1207 .clkdm_name = "core_l4_clkdm",
1208 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1209 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1210 .recalc = &followparent_recalc,
1211};
1212
1213static struct clk mcspi2_ick = {
1214 .name = "mcspi2_ick",
1215 .ops = &clkops_omap2_iclk_dflt_wait,
1216 .parent = &l4_ck,
1217 .clkdm_name = "core_l4_clkdm",
1218 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1219 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1220 .recalc = &followparent_recalc,
1221};
1222
1223static struct clk mcspi2_fck = {
1224 .name = "mcspi2_fck",
1225 .ops = &clkops_omap2_dflt_wait,
1226 .parent = &func_48m_ck,
1227 .clkdm_name = "core_l4_clkdm",
1228 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1229 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1230 .recalc = &followparent_recalc,
1231};
1232
1233static struct clk uart1_ick = {
1234 .name = "uart1_ick",
1235 .ops = &clkops_omap2_iclk_dflt_wait,
1236 .parent = &l4_ck,
1237 .clkdm_name = "core_l4_clkdm",
1238 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1239 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
1240 .recalc = &followparent_recalc,
1241};
1242
1243static struct clk uart1_fck = {
1244 .name = "uart1_fck",
1245 .ops = &clkops_omap2_dflt_wait,
1246 .parent = &func_48m_ck,
1247 .clkdm_name = "core_l4_clkdm",
1248 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1249 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
1250 .recalc = &followparent_recalc,
1251};
1252
1253static struct clk uart2_ick = {
1254 .name = "uart2_ick",
1255 .ops = &clkops_omap2_iclk_dflt_wait,
1256 .parent = &l4_ck,
1257 .clkdm_name = "core_l4_clkdm",
1258 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1259 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
1260 .recalc = &followparent_recalc,
1261};
1262
1263static struct clk uart2_fck = {
1264 .name = "uart2_fck",
1265 .ops = &clkops_omap2_dflt_wait,
1266 .parent = &func_48m_ck,
1267 .clkdm_name = "core_l4_clkdm",
1268 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1269 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
1270 .recalc = &followparent_recalc,
1271};
1272
1273static struct clk uart3_ick = {
1274 .name = "uart3_ick",
1275 .ops = &clkops_omap2_iclk_dflt_wait,
1276 .parent = &l4_ck,
1277 .clkdm_name = "core_l4_clkdm",
1278 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1279 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
1280 .recalc = &followparent_recalc,
1281};
1282
1283static struct clk uart3_fck = {
1284 .name = "uart3_fck",
1285 .ops = &clkops_omap2_dflt_wait,
1286 .parent = &func_48m_ck,
1287 .clkdm_name = "core_l4_clkdm",
1288 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1289 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
1290 .recalc = &followparent_recalc,
1291};
1292
1293static struct clk gpios_ick = {
1294 .name = "gpios_ick",
1295 .ops = &clkops_omap2_iclk_dflt_wait,
1296 .parent = &wu_l4_ick,
1297 .clkdm_name = "wkup_clkdm",
1298 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1299 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
1300 .recalc = &followparent_recalc,
1301};
1302
1303static struct clk gpios_fck = {
1304 .name = "gpios_fck",
1305 .ops = &clkops_omap2_dflt_wait,
1306 .parent = &func_32k_ck,
1307 .clkdm_name = "wkup_clkdm",
1308 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1309 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
1310 .recalc = &followparent_recalc,
1311};
1312
1313static struct clk mpu_wdt_ick = {
1314 .name = "mpu_wdt_ick",
1315 .ops = &clkops_omap2_iclk_dflt_wait,
1316 .parent = &wu_l4_ick,
1317 .clkdm_name = "wkup_clkdm",
1318 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1319 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
1320 .recalc = &followparent_recalc,
1321};
1322
1323static struct clk mpu_wdt_fck = {
1324 .name = "mpu_wdt_fck",
1325 .ops = &clkops_omap2_dflt_wait,
1326 .parent = &func_32k_ck,
1327 .clkdm_name = "wkup_clkdm",
1328 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1329 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
1330 .recalc = &followparent_recalc,
1331};
1332
1333static struct clk sync_32k_ick = {
1334 .name = "sync_32k_ick",
1335 .ops = &clkops_omap2_iclk_dflt_wait,
1336 .parent = &wu_l4_ick,
1337 .clkdm_name = "wkup_clkdm",
1338 .flags = ENABLE_ON_INIT,
1339 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1340 .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT,
1341 .recalc = &followparent_recalc,
1342};
1343
1344static struct clk wdt1_ick = {
1345 .name = "wdt1_ick",
1346 .ops = &clkops_omap2_iclk_dflt_wait,
1347 .parent = &wu_l4_ick,
1348 .clkdm_name = "wkup_clkdm",
1349 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1350 .enable_bit = OMAP24XX_EN_WDT1_SHIFT,
1351 .recalc = &followparent_recalc,
1352};
1353
1354static struct clk omapctrl_ick = {
1355 .name = "omapctrl_ick",
1356 .ops = &clkops_omap2_iclk_dflt_wait,
1357 .parent = &wu_l4_ick,
1358 .clkdm_name = "wkup_clkdm",
1359 .flags = ENABLE_ON_INIT,
1360 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1361 .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT,
1362 .recalc = &followparent_recalc,
1363};
1364
1365static struct clk cam_ick = {
1366 .name = "cam_ick",
1367 .ops = &clkops_omap2_iclk_dflt,
1368 .parent = &l4_ck,
1369 .clkdm_name = "core_l4_clkdm",
1370 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1371 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
1372 .recalc = &followparent_recalc,
1373};
1374
1375/*
1376 * cam_fck controls both CAM_MCLK and CAM_FCLK. It should probably be
1377 * split into two separate clocks, since the parent clocks are different
1378 * and the clockdomains are also different.
1379 */
1380static struct clk cam_fck = {
1381 .name = "cam_fck",
1382 .ops = &clkops_omap2_dflt,
1383 .parent = &func_96m_ck,
1384 .clkdm_name = "core_l3_clkdm",
1385 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1386 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
1387 .recalc = &followparent_recalc,
1388};
1389
1390static struct clk mailboxes_ick = {
1391 .name = "mailboxes_ick",
1392 .ops = &clkops_omap2_iclk_dflt_wait,
1393 .parent = &l4_ck,
1394 .clkdm_name = "core_l4_clkdm",
1395 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1396 .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
1397 .recalc = &followparent_recalc,
1398};
1399
1400static struct clk wdt4_ick = {
1401 .name = "wdt4_ick",
1402 .ops = &clkops_omap2_iclk_dflt_wait,
1403 .parent = &l4_ck,
1404 .clkdm_name = "core_l4_clkdm",
1405 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1406 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
1407 .recalc = &followparent_recalc,
1408};
1409
1410static struct clk wdt4_fck = {
1411 .name = "wdt4_fck",
1412 .ops = &clkops_omap2_dflt_wait,
1413 .parent = &func_32k_ck,
1414 .clkdm_name = "core_l4_clkdm",
1415 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1416 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
1417 .recalc = &followparent_recalc,
1418};
1419
1420static struct clk wdt3_ick = {
1421 .name = "wdt3_ick",
1422 .ops = &clkops_omap2_iclk_dflt_wait,
1423 .parent = &l4_ck,
1424 .clkdm_name = "core_l4_clkdm",
1425 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1426 .enable_bit = OMAP2420_EN_WDT3_SHIFT,
1427 .recalc = &followparent_recalc,
1428};
1429
1430static struct clk wdt3_fck = {
1431 .name = "wdt3_fck",
1432 .ops = &clkops_omap2_dflt_wait,
1433 .parent = &func_32k_ck,
1434 .clkdm_name = "core_l4_clkdm",
1435 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1436 .enable_bit = OMAP2420_EN_WDT3_SHIFT,
1437 .recalc = &followparent_recalc,
1438};
1439
1440static struct clk mspro_ick = {
1441 .name = "mspro_ick",
1442 .ops = &clkops_omap2_iclk_dflt_wait,
1443 .parent = &l4_ck,
1444 .clkdm_name = "core_l4_clkdm",
1445 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1446 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
1447 .recalc = &followparent_recalc,
1448};
1449
1450static struct clk mspro_fck = {
1451 .name = "mspro_fck",
1452 .ops = &clkops_omap2_dflt_wait,
1453 .parent = &func_96m_ck,
1454 .clkdm_name = "core_l4_clkdm",
1455 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1456 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
1457 .recalc = &followparent_recalc,
1458};
1459
1460static struct clk mmc_ick = {
1461 .name = "mmc_ick",
1462 .ops = &clkops_omap2_iclk_dflt_wait,
1463 .parent = &l4_ck,
1464 .clkdm_name = "core_l4_clkdm",
1465 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1466 .enable_bit = OMAP2420_EN_MMC_SHIFT,
1467 .recalc = &followparent_recalc,
1468};
1469
1470static struct clk mmc_fck = {
1471 .name = "mmc_fck",
1472 .ops = &clkops_omap2_dflt_wait,
1473 .parent = &func_96m_ck,
1474 .clkdm_name = "core_l4_clkdm",
1475 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1476 .enable_bit = OMAP2420_EN_MMC_SHIFT,
1477 .recalc = &followparent_recalc,
1478};
1479
1480static struct clk fac_ick = {
1481 .name = "fac_ick",
1482 .ops = &clkops_omap2_iclk_dflt_wait,
1483 .parent = &l4_ck,
1484 .clkdm_name = "core_l4_clkdm",
1485 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1486 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
1487 .recalc = &followparent_recalc,
1488};
1489
1490static struct clk fac_fck = {
1491 .name = "fac_fck",
1492 .ops = &clkops_omap2_dflt_wait,
1493 .parent = &func_12m_ck,
1494 .clkdm_name = "core_l4_clkdm",
1495 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1496 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
1497 .recalc = &followparent_recalc,
1498};
1499
1500static struct clk eac_ick = {
1501 .name = "eac_ick",
1502 .ops = &clkops_omap2_iclk_dflt_wait,
1503 .parent = &l4_ck,
1504 .clkdm_name = "core_l4_clkdm",
1505 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1506 .enable_bit = OMAP2420_EN_EAC_SHIFT,
1507 .recalc = &followparent_recalc,
1508};
1509
1510static struct clk eac_fck = {
1511 .name = "eac_fck",
1512 .ops = &clkops_omap2_dflt_wait,
1513 .parent = &func_96m_ck,
1514 .clkdm_name = "core_l4_clkdm",
1515 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1516 .enable_bit = OMAP2420_EN_EAC_SHIFT,
1517 .recalc = &followparent_recalc,
1518};
1519
1520static struct clk hdq_ick = {
1521 .name = "hdq_ick",
1522 .ops = &clkops_omap2_iclk_dflt_wait,
1523 .parent = &l4_ck,
1524 .clkdm_name = "core_l4_clkdm",
1525 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1526 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
1527 .recalc = &followparent_recalc,
1528};
1529
1530static struct clk hdq_fck = {
1531 .name = "hdq_fck",
1532 .ops = &clkops_omap2_dflt_wait,
1533 .parent = &func_12m_ck,
1534 .clkdm_name = "core_l4_clkdm",
1535 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1536 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
1537 .recalc = &followparent_recalc,
1538};
1539
1540static struct clk i2c2_ick = {
1541 .name = "i2c2_ick",
1542 .ops = &clkops_omap2_iclk_dflt_wait,
1543 .parent = &l4_ck,
1544 .clkdm_name = "core_l4_clkdm",
1545 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1546 .enable_bit = OMAP2420_EN_I2C2_SHIFT,
1547 .recalc = &followparent_recalc,
1548};
1549
1550static struct clk i2c2_fck = {
1551 .name = "i2c2_fck",
1552 .ops = &clkops_omap2_dflt_wait,
1553 .parent = &func_12m_ck,
1554 .clkdm_name = "core_l4_clkdm",
1555 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1556 .enable_bit = OMAP2420_EN_I2C2_SHIFT,
1557 .recalc = &followparent_recalc,
1558};
1559
1560static struct clk i2c1_ick = {
1561 .name = "i2c1_ick",
1562 .ops = &clkops_omap2_iclk_dflt_wait,
1563 .parent = &l4_ck,
1564 .clkdm_name = "core_l4_clkdm",
1565 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1566 .enable_bit = OMAP2420_EN_I2C1_SHIFT,
1567 .recalc = &followparent_recalc,
1568};
1569
1570static struct clk i2c1_fck = {
1571 .name = "i2c1_fck",
1572 .ops = &clkops_omap2_dflt_wait,
1573 .parent = &func_12m_ck,
1574 .clkdm_name = "core_l4_clkdm",
1575 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1576 .enable_bit = OMAP2420_EN_I2C1_SHIFT,
1577 .recalc = &followparent_recalc,
1578};
1579
1580/*
1581 * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
1582 * accesses derived from this data.
1583 */
1584static struct clk gpmc_fck = {
1585 .name = "gpmc_fck",
1586 .ops = &clkops_omap2_iclk_idle_only,
1587 .parent = &core_l3_ck,
1588 .flags = ENABLE_ON_INIT,
1589 .clkdm_name = "core_l3_clkdm",
1590 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1591 .enable_bit = OMAP24XX_AUTO_GPMC_SHIFT,
1592 .recalc = &followparent_recalc,
1593};
1594
1595static struct clk sdma_fck = {
1596 .name = "sdma_fck",
1597 .ops = &clkops_null, /* RMK: missing? */
1598 .parent = &core_l3_ck,
1599 .clkdm_name = "core_l3_clkdm",
1600 .recalc = &followparent_recalc,
1601};
1602
1603/*
1604 * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
1605 * accesses derived from this data.
1606 */
1607static struct clk sdma_ick = {
1608 .name = "sdma_ick",
1609 .ops = &clkops_omap2_iclk_idle_only,
1610 .parent = &core_l3_ck,
1611 .clkdm_name = "core_l3_clkdm",
1612 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1613 .enable_bit = OMAP24XX_AUTO_SDMA_SHIFT,
1614 .recalc = &followparent_recalc,
1615};
1616
1617/*
1618 * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
1619 * accesses derived from this data.
1620 */
1621static struct clk sdrc_ick = {
1622 .name = "sdrc_ick",
1623 .ops = &clkops_omap2_iclk_idle_only,
1624 .parent = &core_l3_ck,
1625 .flags = ENABLE_ON_INIT,
1626 .clkdm_name = "core_l3_clkdm",
1627 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1628 .enable_bit = OMAP24XX_AUTO_SDRC_SHIFT,
1629 .recalc = &followparent_recalc,
1630};
1631
1632static struct clk vlynq_ick = {
1633 .name = "vlynq_ick",
1634 .ops = &clkops_omap2_iclk_dflt_wait,
1635 .parent = &core_l3_ck,
1636 .clkdm_name = "core_l3_clkdm",
1637 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1638 .enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
1639 .recalc = &followparent_recalc,
1640};
1641
1642static const struct clksel_rate vlynq_fck_96m_rates[] = {
1643 { .div = 1, .val = 0, .flags = RATE_IN_242X },
1644 { .div = 0 }
1645};
1646
1647static const struct clksel_rate vlynq_fck_core_rates[] = {
1648 { .div = 1, .val = 1, .flags = RATE_IN_242X },
1649 { .div = 2, .val = 2, .flags = RATE_IN_242X },
1650 { .div = 3, .val = 3, .flags = RATE_IN_242X },
1651 { .div = 4, .val = 4, .flags = RATE_IN_242X },
1652 { .div = 6, .val = 6, .flags = RATE_IN_242X },
1653 { .div = 8, .val = 8, .flags = RATE_IN_242X },
1654 { .div = 9, .val = 9, .flags = RATE_IN_242X },
1655 { .div = 12, .val = 12, .flags = RATE_IN_242X },
1656 { .div = 16, .val = 16, .flags = RATE_IN_242X },
1657 { .div = 18, .val = 18, .flags = RATE_IN_242X },
1658 { .div = 0 }
1659};
1660
1661static const struct clksel vlynq_fck_clksel[] = {
1662 { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates },
1663 { .parent = &core_ck, .rates = vlynq_fck_core_rates },
1664 { .parent = NULL }
1665};
1666
1667static struct clk vlynq_fck = {
1668 .name = "vlynq_fck",
1669 .ops = &clkops_omap2_dflt_wait,
1670 .parent = &func_96m_ck,
1671 .clkdm_name = "core_l3_clkdm",
1672 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1673 .enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
1674 .init = &omap2_init_clksel_parent,
1675 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1676 .clksel_mask = OMAP2420_CLKSEL_VLYNQ_MASK,
1677 .clksel = vlynq_fck_clksel,
1678 .recalc = &omap2_clksel_recalc,
1679};
1680
1681static struct clk des_ick = {
1682 .name = "des_ick",
1683 .ops = &clkops_omap2_iclk_dflt_wait,
1684 .parent = &l4_ck,
1685 .clkdm_name = "core_l4_clkdm",
1686 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1687 .enable_bit = OMAP24XX_EN_DES_SHIFT,
1688 .recalc = &followparent_recalc,
1689};
1690
1691static struct clk sha_ick = {
1692 .name = "sha_ick",
1693 .ops = &clkops_omap2_iclk_dflt_wait,
1694 .parent = &l4_ck,
1695 .clkdm_name = "core_l4_clkdm",
1696 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1697 .enable_bit = OMAP24XX_EN_SHA_SHIFT,
1698 .recalc = &followparent_recalc,
1699};
1700
1701static struct clk rng_ick = {
1702 .name = "rng_ick",
1703 .ops = &clkops_omap2_iclk_dflt_wait,
1704 .parent = &l4_ck,
1705 .clkdm_name = "core_l4_clkdm",
1706 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1707 .enable_bit = OMAP24XX_EN_RNG_SHIFT,
1708 .recalc = &followparent_recalc,
1709};
1710
1711static struct clk aes_ick = {
1712 .name = "aes_ick",
1713 .ops = &clkops_omap2_iclk_dflt_wait,
1714 .parent = &l4_ck,
1715 .clkdm_name = "core_l4_clkdm",
1716 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1717 .enable_bit = OMAP24XX_EN_AES_SHIFT,
1718 .recalc = &followparent_recalc,
1719};
1720
1721static struct clk pka_ick = {
1722 .name = "pka_ick",
1723 .ops = &clkops_omap2_iclk_dflt_wait,
1724 .parent = &l4_ck,
1725 .clkdm_name = "core_l4_clkdm",
1726 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1727 .enable_bit = OMAP24XX_EN_PKA_SHIFT,
1728 .recalc = &followparent_recalc,
1729};
1730
1731static struct clk usb_fck = {
1732 .name = "usb_fck",
1733 .ops = &clkops_omap2_dflt_wait,
1734 .parent = &func_48m_ck,
1735 .clkdm_name = "core_l3_clkdm",
1736 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1737 .enable_bit = OMAP24XX_EN_USB_SHIFT,
1738 .recalc = &followparent_recalc,
1739};
1740
1741/*
1742 * This clock is a composite clock which does entire set changes then
1743 * forces a rebalance. It keys on the MPU speed, but it really could
1744 * be any key speed part of a set in the rate table.
1745 *
1746 * to really change a set, you need memory table sets which get changed
1747 * in sram, pre-notifiers & post notifiers, changing the top set, without
1748 * having low level display recalc's won't work... this is why dpm notifiers
1749 * work, isr's off, walk a list of clocks already _off_ and not messing with
1750 * the bus.
1751 *
1752 * This clock should have no parent. It embodies the entire upper level
1753 * active set. A parent will mess up some of the init also.
1754 */
1755static struct clk virt_prcm_set = {
1756 .name = "virt_prcm_set",
1757 .ops = &clkops_null,
1758 .parent = &mpu_ck, /* Indexed by mpu speed, no parent */
1759 .recalc = &omap2_table_mpu_recalc, /* sets are keyed on mpu rate */
1760 .set_rate = &omap2_select_table_rate,
1761 .round_rate = &omap2_round_to_table_rate,
1762};
1763
1764
1765/*
1766 * clkdev integration
1767 */
1768
1769static struct omap_clk omap2420_clks[] = {
1770 /* external root sources */
1771 CLK(NULL, "func_32k_ck", &func_32k_ck, CK_242X),
1772 CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_242X),
1773 CLK(NULL, "osc_ck", &osc_ck, CK_242X),
1774 CLK(NULL, "sys_ck", &sys_ck, CK_242X),
1775 CLK(NULL, "alt_ck", &alt_ck, CK_242X),
1776 CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_242X),
1777 /* internal analog sources */
1778 CLK(NULL, "dpll_ck", &dpll_ck, CK_242X),
1779 CLK(NULL, "apll96_ck", &apll96_ck, CK_242X),
1780 CLK(NULL, "apll54_ck", &apll54_ck, CK_242X),
1781 /* internal prcm root sources */
1782 CLK(NULL, "func_54m_ck", &func_54m_ck, CK_242X),
1783 CLK(NULL, "core_ck", &core_ck, CK_242X),
1784 CLK(NULL, "func_96m_ck", &func_96m_ck, CK_242X),
1785 CLK(NULL, "func_48m_ck", &func_48m_ck, CK_242X),
1786 CLK(NULL, "func_12m_ck", &func_12m_ck, CK_242X),
1787 CLK(NULL, "ck_wdt1_osc", &wdt1_osc_ck, CK_242X),
1788 CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_242X),
1789 CLK(NULL, "sys_clkout", &sys_clkout, CK_242X),
1790 CLK(NULL, "sys_clkout2_src", &sys_clkout2_src, CK_242X),
1791 CLK(NULL, "sys_clkout2", &sys_clkout2, CK_242X),
1792 CLK(NULL, "emul_ck", &emul_ck, CK_242X),
1793 /* mpu domain clocks */
1794 CLK(NULL, "mpu_ck", &mpu_ck, CK_242X),
1795 /* dsp domain clocks */
1796 CLK(NULL, "dsp_fck", &dsp_fck, CK_242X),
1797 CLK(NULL, "dsp_ick", &dsp_ick, CK_242X),
1798 CLK(NULL, "iva1_ifck", &iva1_ifck, CK_242X),
1799 CLK(NULL, "iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X),
1800 /* GFX domain clocks */
1801 CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_242X),
1802 CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_242X),
1803 CLK(NULL, "gfx_ick", &gfx_ick, CK_242X),
1804 /* DSS domain clocks */
1805 CLK("omapdss_dss", "ick", &dss_ick, CK_242X),
1806 CLK(NULL, "dss_ick", &dss_ick, CK_242X),
1807 CLK(NULL, "dss1_fck", &dss1_fck, CK_242X),
1808 CLK(NULL, "dss2_fck", &dss2_fck, CK_242X),
1809 CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_242X),
1810 /* L3 domain clocks */
1811 CLK(NULL, "core_l3_ck", &core_l3_ck, CK_242X),
1812 CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_242X),
1813 CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_242X),
1814 /* L4 domain clocks */
1815 CLK(NULL, "l4_ck", &l4_ck, CK_242X),
1816 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_242X),
1817 CLK(NULL, "wu_l4_ick", &wu_l4_ick, CK_242X),
1818 /* virtual meta-group clock */
1819 CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_242X),
1820 /* general l4 interface ck, multi-parent functional clk */
1821 CLK(NULL, "gpt1_ick", &gpt1_ick, CK_242X),
1822 CLK(NULL, "gpt1_fck", &gpt1_fck, CK_242X),
1823 CLK(NULL, "gpt2_ick", &gpt2_ick, CK_242X),
1824 CLK(NULL, "gpt2_fck", &gpt2_fck, CK_242X),
1825 CLK(NULL, "gpt3_ick", &gpt3_ick, CK_242X),
1826 CLK(NULL, "gpt3_fck", &gpt3_fck, CK_242X),
1827 CLK(NULL, "gpt4_ick", &gpt4_ick, CK_242X),
1828 CLK(NULL, "gpt4_fck", &gpt4_fck, CK_242X),
1829 CLK(NULL, "gpt5_ick", &gpt5_ick, CK_242X),
1830 CLK(NULL, "gpt5_fck", &gpt5_fck, CK_242X),
1831 CLK(NULL, "gpt6_ick", &gpt6_ick, CK_242X),
1832 CLK(NULL, "gpt6_fck", &gpt6_fck, CK_242X),
1833 CLK(NULL, "gpt7_ick", &gpt7_ick, CK_242X),
1834 CLK(NULL, "gpt7_fck", &gpt7_fck, CK_242X),
1835 CLK(NULL, "gpt8_ick", &gpt8_ick, CK_242X),
1836 CLK(NULL, "gpt8_fck", &gpt8_fck, CK_242X),
1837 CLK(NULL, "gpt9_ick", &gpt9_ick, CK_242X),
1838 CLK(NULL, "gpt9_fck", &gpt9_fck, CK_242X),
1839 CLK(NULL, "gpt10_ick", &gpt10_ick, CK_242X),
1840 CLK(NULL, "gpt10_fck", &gpt10_fck, CK_242X),
1841 CLK(NULL, "gpt11_ick", &gpt11_ick, CK_242X),
1842 CLK(NULL, "gpt11_fck", &gpt11_fck, CK_242X),
1843 CLK(NULL, "gpt12_ick", &gpt12_ick, CK_242X),
1844 CLK(NULL, "gpt12_fck", &gpt12_fck, CK_242X),
1845 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_242X),
1846 CLK(NULL, "mcbsp1_ick", &mcbsp1_ick, CK_242X),
1847 CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_242X),
1848 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_242X),
1849 CLK(NULL, "mcbsp2_ick", &mcbsp2_ick, CK_242X),
1850 CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_242X),
1851 CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_242X),
1852 CLK(NULL, "mcspi1_ick", &mcspi1_ick, CK_242X),
1853 CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_242X),
1854 CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_242X),
1855 CLK(NULL, "mcspi2_ick", &mcspi2_ick, CK_242X),
1856 CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_242X),
1857 CLK(NULL, "uart1_ick", &uart1_ick, CK_242X),
1858 CLK(NULL, "uart1_fck", &uart1_fck, CK_242X),
1859 CLK(NULL, "uart2_ick", &uart2_ick, CK_242X),
1860 CLK(NULL, "uart2_fck", &uart2_fck, CK_242X),
1861 CLK(NULL, "uart3_ick", &uart3_ick, CK_242X),
1862 CLK(NULL, "uart3_fck", &uart3_fck, CK_242X),
1863 CLK(NULL, "gpios_ick", &gpios_ick, CK_242X),
1864 CLK(NULL, "gpios_fck", &gpios_fck, CK_242X),
1865 CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_242X),
1866 CLK(NULL, "mpu_wdt_ick", &mpu_wdt_ick, CK_242X),
1867 CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck, CK_242X),
1868 CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_242X),
1869 CLK(NULL, "wdt1_ick", &wdt1_ick, CK_242X),
1870 CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_242X),
1871 CLK("omap24xxcam", "fck", &cam_fck, CK_242X),
1872 CLK(NULL, "cam_fck", &cam_fck, CK_242X),
1873 CLK("omap24xxcam", "ick", &cam_ick, CK_242X),
1874 CLK(NULL, "cam_ick", &cam_ick, CK_242X),
1875 CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_242X),
1876 CLK(NULL, "wdt4_ick", &wdt4_ick, CK_242X),
1877 CLK(NULL, "wdt4_fck", &wdt4_fck, CK_242X),
1878 CLK(NULL, "wdt3_ick", &wdt3_ick, CK_242X),
1879 CLK(NULL, "wdt3_fck", &wdt3_fck, CK_242X),
1880 CLK(NULL, "mspro_ick", &mspro_ick, CK_242X),
1881 CLK(NULL, "mspro_fck", &mspro_fck, CK_242X),
1882 CLK("mmci-omap.0", "ick", &mmc_ick, CK_242X),
1883 CLK(NULL, "mmc_ick", &mmc_ick, CK_242X),
1884 CLK("mmci-omap.0", "fck", &mmc_fck, CK_242X),
1885 CLK(NULL, "mmc_fck", &mmc_fck, CK_242X),
1886 CLK(NULL, "fac_ick", &fac_ick, CK_242X),
1887 CLK(NULL, "fac_fck", &fac_fck, CK_242X),
1888 CLK(NULL, "eac_ick", &eac_ick, CK_242X),
1889 CLK(NULL, "eac_fck", &eac_fck, CK_242X),
1890 CLK("omap_hdq.0", "ick", &hdq_ick, CK_242X),
1891 CLK(NULL, "hdq_ick", &hdq_ick, CK_242X),
1892 CLK("omap_hdq.0", "fck", &hdq_fck, CK_242X),
1893 CLK(NULL, "hdq_fck", &hdq_fck, CK_242X),
1894 CLK("omap_i2c.1", "ick", &i2c1_ick, CK_242X),
1895 CLK(NULL, "i2c1_ick", &i2c1_ick, CK_242X),
1896 CLK(NULL, "i2c1_fck", &i2c1_fck, CK_242X),
1897 CLK("omap_i2c.2", "ick", &i2c2_ick, CK_242X),
1898 CLK(NULL, "i2c2_ick", &i2c2_ick, CK_242X),
1899 CLK(NULL, "i2c2_fck", &i2c2_fck, CK_242X),
1900 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_242X),
1901 CLK(NULL, "sdma_fck", &sdma_fck, CK_242X),
1902 CLK(NULL, "sdma_ick", &sdma_ick, CK_242X),
1903 CLK(NULL, "sdrc_ick", &sdrc_ick, CK_242X),
1904 CLK(NULL, "vlynq_ick", &vlynq_ick, CK_242X),
1905 CLK(NULL, "vlynq_fck", &vlynq_fck, CK_242X),
1906 CLK(NULL, "des_ick", &des_ick, CK_242X),
1907 CLK("omap-sham", "ick", &sha_ick, CK_242X),
1908 CLK(NULL, "sha_ick", &sha_ick, CK_242X),
1909 CLK("omap_rng", "ick", &rng_ick, CK_242X),
1910 CLK(NULL, "rng_ick", &rng_ick, CK_242X),
1911 CLK("omap-aes", "ick", &aes_ick, CK_242X),
1912 CLK(NULL, "aes_ick", &aes_ick, CK_242X),
1913 CLK(NULL, "pka_ick", &pka_ick, CK_242X),
1914 CLK(NULL, "usb_fck", &usb_fck, CK_242X),
1915 CLK("musb-hdrc", "fck", &osc_ck, CK_242X),
1916 CLK(NULL, "timer_32k_ck", &func_32k_ck, CK_242X),
1917 CLK(NULL, "timer_sys_ck", &sys_ck, CK_242X),
1918 CLK(NULL, "timer_ext_ck", &alt_ck, CK_242X),
1919 CLK(NULL, "cpufreq_ck", &virt_prcm_set, CK_242X),
1920};
1921
1922/*
1923 * init code
1924 */
1925
1926int __init omap2420_clk_init(void)
1927{
1928 struct omap_clk *c;
1929
1930 prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL;
1931 cpu_mask = RATE_IN_242X;
1932 rate_table = omap2420_rate_table;
1933
1934 for (c = omap2420_clks; c < omap2420_clks + ARRAY_SIZE(omap2420_clks);
1935 c++)
1936 clk_preinit(c->lk.clk);
1937
1938 osc_ck.rate = omap2_osc_clk_recalc(&osc_ck);
1939 propagate_rate(&osc_ck);
1940 sys_ck.rate = omap2xxx_sys_clk_recalc(&sys_ck);
1941 propagate_rate(&sys_ck);
1942
1943 for (c = omap2420_clks; c < omap2420_clks + ARRAY_SIZE(omap2420_clks);
1944 c++) {
1945 clkdev_add(&c->lk);
1946 clk_register(c->lk.clk);
1947 omap2_init_clk_clkdm(c->lk.clk);
1948 }
1949
1950 omap2xxx_clkt_vps_late_init();
1951
1952 /* Disable autoidle on all clocks; let the PM code enable it later */
1953 omap_clk_disable_autoidle_all();
1954
1955 /* XXX Can this be done from the virt_prcm_set clk init function? */
1956 omap2xxx_clkt_vps_check_bootloader_rates();
1957
1958 recalculate_root_clocks();
1959
1960 pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n",
1961 (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
1962 (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
1963
1964 /*
1965 * Only enable those clocks we will need, let the drivers
1966 * enable other clocks as necessary
1967 */
1968 clk_enable_init_clocks();
1969
1970 return 0;
1971}
1972
diff --git a/arch/arm/mach-omap2/clock2430.c b/arch/arm/mach-omap2/clock2430.c
index e37df538bcd3..cef0c8d1de52 100644
--- a/arch/arm/mach-omap2/clock2430.c
+++ b/arch/arm/mach-omap2/clock2430.c
@@ -40,7 +40,7 @@
40 * passes back the correct CM_IDLEST register address for I2CHS 40 * passes back the correct CM_IDLEST register address for I2CHS
41 * modules. No return value. 41 * modules. No return value.
42 */ 42 */
43static void omap2430_clk_i2chs_find_idlest(struct clk *clk, 43static void omap2430_clk_i2chs_find_idlest(struct clk_hw_omap *clk,
44 void __iomem **idlest_reg, 44 void __iomem **idlest_reg,
45 u8 *idlest_bit, 45 u8 *idlest_bit,
46 u8 *idlest_val) 46 u8 *idlest_val)
@@ -51,9 +51,7 @@ static void omap2430_clk_i2chs_find_idlest(struct clk *clk,
51} 51}
52 52
53/* 2430 I2CHS has non-standard IDLEST register */ 53/* 2430 I2CHS has non-standard IDLEST register */
54const struct clkops clkops_omap2430_i2chs_wait = { 54const struct clk_hw_omap_ops clkhwops_omap2430_i2chs_wait = {
55 .enable = omap2_dflt_clk_enable,
56 .disable = omap2_dflt_clk_disable,
57 .find_idlest = omap2430_clk_i2chs_find_idlest, 55 .find_idlest = omap2430_clk_i2chs_find_idlest,
58 .find_companion = omap2_clk_dflt_find_companion, 56 .find_companion = omap2_clk_dflt_find_companion,
59}; 57};
diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c
deleted file mode 100644
index b179b6ef4329..000000000000
--- a/arch/arm/mach-omap2/clock2430_data.c
+++ /dev/null
@@ -1,2071 +0,0 @@
1/*
2 * OMAP2430 clock data
3 *
4 * Copyright (C) 2005-2009, 2012 Texas Instruments, Inc.
5 * Copyright (C) 2004-2011 Nokia Corporation
6 *
7 * Contacts:
8 * Richard Woodruff <r-woodruff2@ti.com>
9 * Paul Walmsley
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#include <linux/kernel.h>
17#include <linux/clk.h>
18#include <linux/list.h>
19
20#include "soc.h"
21#include "iomap.h"
22#include "clock.h"
23#include "clock2xxx.h"
24#include "opp2xxx.h"
25#include "cm2xxx.h"
26#include "prm2xxx_3xxx.h"
27#include "prm-regbits-24xx.h"
28#include "cm-regbits-24xx.h"
29#include "sdrc.h"
30#include "control.h"
31
32#define OMAP_CM_REGADDR OMAP2430_CM_REGADDR
33
34/*
35 * 2430 clock tree.
36 *
37 * NOTE:In many cases here we are assigning a 'default' parent. In
38 * many cases the parent is selectable. The set parent calls will
39 * also switch sources.
40 *
41 * Several sources are given initial rates which may be wrong, this will
42 * be fixed up in the init func.
43 *
44 * Things are broadly separated below by clock domains. It is
45 * noteworthy that most peripherals have dependencies on multiple clock
46 * domains. Many get their interface clocks from the L4 domain, but get
47 * functional clocks from fixed sources or other core domain derived
48 * clocks.
49 */
50
51/* Base external input clocks */
52static struct clk func_32k_ck = {
53 .name = "func_32k_ck",
54 .ops = &clkops_null,
55 .rate = 32768,
56 .clkdm_name = "wkup_clkdm",
57};
58
59static struct clk secure_32k_ck = {
60 .name = "secure_32k_ck",
61 .ops = &clkops_null,
62 .rate = 32768,
63 .clkdm_name = "wkup_clkdm",
64};
65
66/* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
67static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */
68 .name = "osc_ck",
69 .ops = &clkops_oscck,
70 .clkdm_name = "wkup_clkdm",
71 .recalc = &omap2_osc_clk_recalc,
72};
73
74/* Without modem likely 12MHz, with modem likely 13MHz */
75static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */
76 .name = "sys_ck", /* ~ ref_clk also */
77 .ops = &clkops_null,
78 .parent = &osc_ck,
79 .clkdm_name = "wkup_clkdm",
80 .recalc = &omap2xxx_sys_clk_recalc,
81};
82
83static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */
84 .name = "alt_ck",
85 .ops = &clkops_null,
86 .rate = 54000000,
87 .clkdm_name = "wkup_clkdm",
88};
89
90/* Optional external clock input for McBSP CLKS */
91static struct clk mcbsp_clks = {
92 .name = "mcbsp_clks",
93 .ops = &clkops_null,
94};
95
96/*
97 * Analog domain root source clocks
98 */
99
100/* dpll_ck, is broken out in to special cases through clksel */
101/* REVISIT: Rate changes on dpll_ck trigger a full set change. ...
102 * deal with this
103 */
104
105static struct dpll_data dpll_dd = {
106 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
107 .mult_mask = OMAP24XX_DPLL_MULT_MASK,
108 .div1_mask = OMAP24XX_DPLL_DIV_MASK,
109 .clk_bypass = &sys_ck,
110 .clk_ref = &sys_ck,
111 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
112 .enable_mask = OMAP24XX_EN_DPLL_MASK,
113 .max_multiplier = 1023,
114 .min_divider = 1,
115 .max_divider = 16,
116};
117
118/*
119 * XXX Cannot add round_rate here yet, as this is still a composite clock,
120 * not just a DPLL
121 */
122static struct clk dpll_ck = {
123 .name = "dpll_ck",
124 .ops = &clkops_omap2xxx_dpll_ops,
125 .parent = &sys_ck, /* Can be func_32k also */
126 .init = &omap2xxx_clkt_dpllcore_init,
127 .dpll_data = &dpll_dd,
128 .clkdm_name = "wkup_clkdm",
129 .recalc = &omap2_dpllcore_recalc,
130 .set_rate = &omap2_reprogram_dpllcore,
131};
132
133static struct clk apll96_ck = {
134 .name = "apll96_ck",
135 .ops = &clkops_apll96,
136 .parent = &sys_ck,
137 .rate = 96000000,
138 .flags = ENABLE_ON_INIT,
139 .clkdm_name = "wkup_clkdm",
140 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
141 .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT,
142};
143
144static struct clk apll54_ck = {
145 .name = "apll54_ck",
146 .ops = &clkops_apll54,
147 .parent = &sys_ck,
148 .rate = 54000000,
149 .flags = ENABLE_ON_INIT,
150 .clkdm_name = "wkup_clkdm",
151 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
152 .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT,
153};
154
155/*
156 * PRCM digital base sources
157 */
158
159/* func_54m_ck */
160
161static const struct clksel_rate func_54m_apll54_rates[] = {
162 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
163 { .div = 0 },
164};
165
166static const struct clksel_rate func_54m_alt_rates[] = {
167 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
168 { .div = 0 },
169};
170
171static const struct clksel func_54m_clksel[] = {
172 { .parent = &apll54_ck, .rates = func_54m_apll54_rates, },
173 { .parent = &alt_ck, .rates = func_54m_alt_rates, },
174 { .parent = NULL },
175};
176
177static struct clk func_54m_ck = {
178 .name = "func_54m_ck",
179 .ops = &clkops_null,
180 .parent = &apll54_ck, /* can also be alt_clk */
181 .clkdm_name = "wkup_clkdm",
182 .init = &omap2_init_clksel_parent,
183 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
184 .clksel_mask = OMAP24XX_54M_SOURCE_MASK,
185 .clksel = func_54m_clksel,
186 .recalc = &omap2_clksel_recalc,
187};
188
189static struct clk core_ck = {
190 .name = "core_ck",
191 .ops = &clkops_null,
192 .parent = &dpll_ck, /* can also be 32k */
193 .clkdm_name = "wkup_clkdm",
194 .recalc = &followparent_recalc,
195};
196
197/* func_96m_ck */
198static const struct clksel_rate func_96m_apll96_rates[] = {
199 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
200 { .div = 0 },
201};
202
203static const struct clksel_rate func_96m_alt_rates[] = {
204 { .div = 1, .val = 1, .flags = RATE_IN_243X },
205 { .div = 0 },
206};
207
208static const struct clksel func_96m_clksel[] = {
209 { .parent = &apll96_ck, .rates = func_96m_apll96_rates },
210 { .parent = &alt_ck, .rates = func_96m_alt_rates },
211 { .parent = NULL }
212};
213
214static struct clk func_96m_ck = {
215 .name = "func_96m_ck",
216 .ops = &clkops_null,
217 .parent = &apll96_ck,
218 .clkdm_name = "wkup_clkdm",
219 .init = &omap2_init_clksel_parent,
220 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
221 .clksel_mask = OMAP2430_96M_SOURCE_MASK,
222 .clksel = func_96m_clksel,
223 .recalc = &omap2_clksel_recalc,
224};
225
226/* func_48m_ck */
227
228static const struct clksel_rate func_48m_apll96_rates[] = {
229 { .div = 2, .val = 0, .flags = RATE_IN_24XX },
230 { .div = 0 },
231};
232
233static const struct clksel_rate func_48m_alt_rates[] = {
234 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
235 { .div = 0 },
236};
237
238static const struct clksel func_48m_clksel[] = {
239 { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
240 { .parent = &alt_ck, .rates = func_48m_alt_rates },
241 { .parent = NULL }
242};
243
244static struct clk func_48m_ck = {
245 .name = "func_48m_ck",
246 .ops = &clkops_null,
247 .parent = &apll96_ck, /* 96M or Alt */
248 .clkdm_name = "wkup_clkdm",
249 .init = &omap2_init_clksel_parent,
250 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
251 .clksel_mask = OMAP24XX_48M_SOURCE_MASK,
252 .clksel = func_48m_clksel,
253 .recalc = &omap2_clksel_recalc,
254 .round_rate = &omap2_clksel_round_rate,
255 .set_rate = &omap2_clksel_set_rate
256};
257
258static struct clk func_12m_ck = {
259 .name = "func_12m_ck",
260 .ops = &clkops_null,
261 .parent = &func_48m_ck,
262 .fixed_div = 4,
263 .clkdm_name = "wkup_clkdm",
264 .recalc = &omap_fixed_divisor_recalc,
265};
266
267/* Secure timer, only available in secure mode */
268static struct clk wdt1_osc_ck = {
269 .name = "ck_wdt1_osc",
270 .ops = &clkops_null, /* RMK: missing? */
271 .parent = &osc_ck,
272 .recalc = &followparent_recalc,
273};
274
275/*
276 * The common_clkout* clksel_rate structs are common to
277 * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src.
278 * sys_clkout2_* are 2420-only, so the
279 * clksel_rate flags fields are inaccurate for those clocks. This is
280 * harmless since access to those clocks are gated by the struct clk
281 * flags fields, which mark them as 2420-only.
282 */
283static const struct clksel_rate common_clkout_src_core_rates[] = {
284 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
285 { .div = 0 }
286};
287
288static const struct clksel_rate common_clkout_src_sys_rates[] = {
289 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
290 { .div = 0 }
291};
292
293static const struct clksel_rate common_clkout_src_96m_rates[] = {
294 { .div = 1, .val = 2, .flags = RATE_IN_24XX },
295 { .div = 0 }
296};
297
298static const struct clksel_rate common_clkout_src_54m_rates[] = {
299 { .div = 1, .val = 3, .flags = RATE_IN_24XX },
300 { .div = 0 }
301};
302
303static const struct clksel common_clkout_src_clksel[] = {
304 { .parent = &core_ck, .rates = common_clkout_src_core_rates },
305 { .parent = &sys_ck, .rates = common_clkout_src_sys_rates },
306 { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
307 { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
308 { .parent = NULL }
309};
310
311static struct clk sys_clkout_src = {
312 .name = "sys_clkout_src",
313 .ops = &clkops_omap2_dflt,
314 .parent = &func_54m_ck,
315 .clkdm_name = "wkup_clkdm",
316 .enable_reg = OMAP2430_PRCM_CLKOUT_CTRL,
317 .enable_bit = OMAP24XX_CLKOUT_EN_SHIFT,
318 .init = &omap2_init_clksel_parent,
319 .clksel_reg = OMAP2430_PRCM_CLKOUT_CTRL,
320 .clksel_mask = OMAP24XX_CLKOUT_SOURCE_MASK,
321 .clksel = common_clkout_src_clksel,
322 .recalc = &omap2_clksel_recalc,
323 .round_rate = &omap2_clksel_round_rate,
324 .set_rate = &omap2_clksel_set_rate
325};
326
327static const struct clksel_rate common_clkout_rates[] = {
328 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
329 { .div = 2, .val = 1, .flags = RATE_IN_24XX },
330 { .div = 4, .val = 2, .flags = RATE_IN_24XX },
331 { .div = 8, .val = 3, .flags = RATE_IN_24XX },
332 { .div = 16, .val = 4, .flags = RATE_IN_24XX },
333 { .div = 0 },
334};
335
336static const struct clksel sys_clkout_clksel[] = {
337 { .parent = &sys_clkout_src, .rates = common_clkout_rates },
338 { .parent = NULL }
339};
340
341static struct clk sys_clkout = {
342 .name = "sys_clkout",
343 .ops = &clkops_null,
344 .parent = &sys_clkout_src,
345 .clkdm_name = "wkup_clkdm",
346 .clksel_reg = OMAP2430_PRCM_CLKOUT_CTRL,
347 .clksel_mask = OMAP24XX_CLKOUT_DIV_MASK,
348 .clksel = sys_clkout_clksel,
349 .recalc = &omap2_clksel_recalc,
350 .round_rate = &omap2_clksel_round_rate,
351 .set_rate = &omap2_clksel_set_rate
352};
353
354static struct clk emul_ck = {
355 .name = "emul_ck",
356 .ops = &clkops_omap2_dflt,
357 .parent = &func_54m_ck,
358 .clkdm_name = "wkup_clkdm",
359 .enable_reg = OMAP2430_PRCM_CLKEMUL_CTRL,
360 .enable_bit = OMAP24XX_EMULATION_EN_SHIFT,
361 .recalc = &followparent_recalc,
362
363};
364
365/*
366 * MPU clock domain
367 * Clocks:
368 * MPU_FCLK, MPU_ICLK
369 * INT_M_FCLK, INT_M_I_CLK
370 *
371 * - Individual clocks are hardware managed.
372 * - Base divider comes from: CM_CLKSEL_MPU
373 *
374 */
375static const struct clksel_rate mpu_core_rates[] = {
376 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
377 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
378 { .div = 0 },
379};
380
381static const struct clksel mpu_clksel[] = {
382 { .parent = &core_ck, .rates = mpu_core_rates },
383 { .parent = NULL }
384};
385
386static struct clk mpu_ck = { /* Control cpu */
387 .name = "mpu_ck",
388 .ops = &clkops_null,
389 .parent = &core_ck,
390 .clkdm_name = "mpu_clkdm",
391 .init = &omap2_init_clksel_parent,
392 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
393 .clksel_mask = OMAP24XX_CLKSEL_MPU_MASK,
394 .clksel = mpu_clksel,
395 .recalc = &omap2_clksel_recalc,
396};
397
398/*
399 * DSP (2430-IVA2.1) clock domain
400 * Clocks:
401 * 2430: IVA2.1_FCLK (really just DSP_FCLK), IVA2.1_ICLK
402 *
403 * Won't be too specific here. The core clock comes into this block
404 * it is divided then tee'ed. One branch goes directly to xyz enable
405 * controls. The other branch gets further divided by 2 then possibly
406 * routed into a synchronizer and out of clocks abc.
407 */
408static const struct clksel_rate dsp_fck_core_rates[] = {
409 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
410 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
411 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
412 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
413 { .div = 0 },
414};
415
416static const struct clksel dsp_fck_clksel[] = {
417 { .parent = &core_ck, .rates = dsp_fck_core_rates },
418 { .parent = NULL }
419};
420
421static struct clk dsp_fck = {
422 .name = "dsp_fck",
423 .ops = &clkops_omap2_dflt_wait,
424 .parent = &core_ck,
425 .clkdm_name = "dsp_clkdm",
426 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
427 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
428 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
429 .clksel_mask = OMAP24XX_CLKSEL_DSP_MASK,
430 .clksel = dsp_fck_clksel,
431 .recalc = &omap2_clksel_recalc,
432};
433
434static const struct clksel dsp_ick_clksel[] = {
435 { .parent = &dsp_fck, .rates = dsp_ick_rates },
436 { .parent = NULL }
437};
438
439/* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */
440static struct clk iva2_1_ick = {
441 .name = "iva2_1_ick",
442 .ops = &clkops_omap2_dflt_wait,
443 .parent = &dsp_fck,
444 .clkdm_name = "dsp_clkdm",
445 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
446 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
447 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
448 .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK,
449 .clksel = dsp_ick_clksel,
450 .recalc = &omap2_clksel_recalc,
451};
452
453/*
454 * L3 clock domain
455 * L3 clocks are used for both interface and functional clocks to
456 * multiple entities. Some of these clocks are completely managed
457 * by hardware, and some others allow software control. Hardware
458 * managed ones general are based on directly CLK_REQ signals and
459 * various auto idle settings. The functional spec sets many of these
460 * as 'tie-high' for their enables.
461 *
462 * I-CLOCKS:
463 * L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
464 * CAM, HS-USB.
465 * F-CLOCK
466 * SSI.
467 *
468 * GPMC memories and SDRC have timing and clock sensitive registers which
469 * may very well need notification when the clock changes. Currently for low
470 * operating points, these are taken care of in sleep.S.
471 */
472static const struct clksel_rate core_l3_core_rates[] = {
473 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
474 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
475 { .div = 6, .val = 6, .flags = RATE_IN_24XX },
476 { .div = 0 }
477};
478
479static const struct clksel core_l3_clksel[] = {
480 { .parent = &core_ck, .rates = core_l3_core_rates },
481 { .parent = NULL }
482};
483
484static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */
485 .name = "core_l3_ck",
486 .ops = &clkops_null,
487 .parent = &core_ck,
488 .clkdm_name = "core_l3_clkdm",
489 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
490 .clksel_mask = OMAP24XX_CLKSEL_L3_MASK,
491 .clksel = core_l3_clksel,
492 .recalc = &omap2_clksel_recalc,
493};
494
495/* usb_l4_ick */
496static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
497 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
498 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
499 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
500 { .div = 0 }
501};
502
503static const struct clksel usb_l4_ick_clksel[] = {
504 { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
505 { .parent = NULL },
506};
507
508/* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */
509static struct clk usb_l4_ick = { /* FS-USB interface clock */
510 .name = "usb_l4_ick",
511 .ops = &clkops_omap2_iclk_dflt_wait,
512 .parent = &core_l3_ck,
513 .clkdm_name = "core_l4_clkdm",
514 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
515 .enable_bit = OMAP24XX_EN_USB_SHIFT,
516 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
517 .clksel_mask = OMAP24XX_CLKSEL_USB_MASK,
518 .clksel = usb_l4_ick_clksel,
519 .recalc = &omap2_clksel_recalc,
520};
521
522/*
523 * L4 clock management domain
524 *
525 * This domain contains lots of interface clocks from the L4 interface, some
526 * functional clocks. Fixed APLL functional source clocks are managed in
527 * this domain.
528 */
529static const struct clksel_rate l4_core_l3_rates[] = {
530 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
531 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
532 { .div = 0 }
533};
534
535static const struct clksel l4_clksel[] = {
536 { .parent = &core_l3_ck, .rates = l4_core_l3_rates },
537 { .parent = NULL }
538};
539
540static struct clk l4_ck = { /* used both as an ick and fck */
541 .name = "l4_ck",
542 .ops = &clkops_null,
543 .parent = &core_l3_ck,
544 .clkdm_name = "core_l4_clkdm",
545 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
546 .clksel_mask = OMAP24XX_CLKSEL_L4_MASK,
547 .clksel = l4_clksel,
548 .recalc = &omap2_clksel_recalc,
549};
550
551/*
552 * SSI is in L3 management domain, its direct parent is core not l3,
553 * many core power domain entities are grouped into the L3 clock
554 * domain.
555 * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_ICLK
556 *
557 * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
558 */
559static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
560 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
561 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
562 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
563 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
564 { .div = 5, .val = 5, .flags = RATE_IN_243X },
565 { .div = 0 }
566};
567
568static const struct clksel ssi_ssr_sst_fck_clksel[] = {
569 { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
570 { .parent = NULL }
571};
572
573static struct clk ssi_ssr_sst_fck = {
574 .name = "ssi_fck",
575 .ops = &clkops_omap2_dflt_wait,
576 .parent = &core_ck,
577 .clkdm_name = "core_l3_clkdm",
578 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
579 .enable_bit = OMAP24XX_EN_SSI_SHIFT,
580 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
581 .clksel_mask = OMAP24XX_CLKSEL_SSI_MASK,
582 .clksel = ssi_ssr_sst_fck_clksel,
583 .recalc = &omap2_clksel_recalc,
584};
585
586/*
587 * Presumably this is the same as SSI_ICLK.
588 * TRM contradicts itself on what clockdomain SSI_ICLK is in
589 */
590static struct clk ssi_l4_ick = {
591 .name = "ssi_l4_ick",
592 .ops = &clkops_omap2_iclk_dflt_wait,
593 .parent = &l4_ck,
594 .clkdm_name = "core_l4_clkdm",
595 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
596 .enable_bit = OMAP24XX_EN_SSI_SHIFT,
597 .recalc = &followparent_recalc,
598};
599
600
601/*
602 * GFX clock domain
603 * Clocks:
604 * GFX_FCLK, GFX_ICLK
605 * GFX_CG1(2d), GFX_CG2(3d)
606 *
607 * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
608 * The 2d and 3d clocks run at a hardware determined
609 * divided value of fclk.
610 *
611 */
612
613/* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */
614static const struct clksel gfx_fck_clksel[] = {
615 { .parent = &core_l3_ck, .rates = gfx_l3_rates },
616 { .parent = NULL },
617};
618
619static struct clk gfx_3d_fck = {
620 .name = "gfx_3d_fck",
621 .ops = &clkops_omap2_dflt_wait,
622 .parent = &core_l3_ck,
623 .clkdm_name = "gfx_clkdm",
624 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
625 .enable_bit = OMAP24XX_EN_3D_SHIFT,
626 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
627 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
628 .clksel = gfx_fck_clksel,
629 .recalc = &omap2_clksel_recalc,
630 .round_rate = &omap2_clksel_round_rate,
631 .set_rate = &omap2_clksel_set_rate
632};
633
634static struct clk gfx_2d_fck = {
635 .name = "gfx_2d_fck",
636 .ops = &clkops_omap2_dflt_wait,
637 .parent = &core_l3_ck,
638 .clkdm_name = "gfx_clkdm",
639 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
640 .enable_bit = OMAP24XX_EN_2D_SHIFT,
641 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
642 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
643 .clksel = gfx_fck_clksel,
644 .recalc = &omap2_clksel_recalc,
645};
646
647/* This interface clock does not have a CM_AUTOIDLE bit */
648static struct clk gfx_ick = {
649 .name = "gfx_ick", /* From l3 */
650 .ops = &clkops_omap2_dflt_wait,
651 .parent = &core_l3_ck,
652 .clkdm_name = "gfx_clkdm",
653 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
654 .enable_bit = OMAP_EN_GFX_SHIFT,
655 .recalc = &followparent_recalc,
656};
657
658/*
659 * Modem clock domain (2430)
660 * CLOCKS:
661 * MDM_OSC_CLK
662 * MDM_ICLK
663 * These clocks are usable in chassis mode only.
664 */
665static const struct clksel_rate mdm_ick_core_rates[] = {
666 { .div = 1, .val = 1, .flags = RATE_IN_243X },
667 { .div = 4, .val = 4, .flags = RATE_IN_243X },
668 { .div = 6, .val = 6, .flags = RATE_IN_243X },
669 { .div = 9, .val = 9, .flags = RATE_IN_243X },
670 { .div = 0 }
671};
672
673static const struct clksel mdm_ick_clksel[] = {
674 { .parent = &core_ck, .rates = mdm_ick_core_rates },
675 { .parent = NULL }
676};
677
678static struct clk mdm_ick = { /* used both as a ick and fck */
679 .name = "mdm_ick",
680 .ops = &clkops_omap2_iclk_dflt_wait,
681 .parent = &core_ck,
682 .clkdm_name = "mdm_clkdm",
683 .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
684 .enable_bit = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
685 .clksel_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL),
686 .clksel_mask = OMAP2430_CLKSEL_MDM_MASK,
687 .clksel = mdm_ick_clksel,
688 .recalc = &omap2_clksel_recalc,
689};
690
691static struct clk mdm_osc_ck = {
692 .name = "mdm_osc_ck",
693 .ops = &clkops_omap2_mdmclk_dflt_wait,
694 .parent = &osc_ck,
695 .clkdm_name = "mdm_clkdm",
696 .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN),
697 .enable_bit = OMAP2430_EN_OSC_SHIFT,
698 .recalc = &followparent_recalc,
699};
700
701/*
702 * DSS clock domain
703 * CLOCKs:
704 * DSS_L4_ICLK, DSS_L3_ICLK,
705 * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
706 *
707 * DSS is both initiator and target.
708 */
709/* XXX Add RATE_NOT_VALIDATED */
710
711static const struct clksel_rate dss1_fck_sys_rates[] = {
712 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
713 { .div = 0 }
714};
715
716static const struct clksel_rate dss1_fck_core_rates[] = {
717 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
718 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
719 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
720 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
721 { .div = 5, .val = 5, .flags = RATE_IN_24XX },
722 { .div = 6, .val = 6, .flags = RATE_IN_24XX },
723 { .div = 8, .val = 8, .flags = RATE_IN_24XX },
724 { .div = 9, .val = 9, .flags = RATE_IN_24XX },
725 { .div = 12, .val = 12, .flags = RATE_IN_24XX },
726 { .div = 16, .val = 16, .flags = RATE_IN_24XX },
727 { .div = 0 }
728};
729
730static const struct clksel dss1_fck_clksel[] = {
731 { .parent = &sys_ck, .rates = dss1_fck_sys_rates },
732 { .parent = &core_ck, .rates = dss1_fck_core_rates },
733 { .parent = NULL },
734};
735
736static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */
737 .name = "dss_ick",
738 .ops = &clkops_omap2_iclk_dflt,
739 .parent = &l4_ck, /* really both l3 and l4 */
740 .clkdm_name = "dss_clkdm",
741 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
742 .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
743 .recalc = &followparent_recalc,
744};
745
746static struct clk dss1_fck = {
747 .name = "dss1_fck",
748 .ops = &clkops_omap2_dflt,
749 .parent = &core_ck, /* Core or sys */
750 .clkdm_name = "dss_clkdm",
751 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
752 .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
753 .init = &omap2_init_clksel_parent,
754 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
755 .clksel_mask = OMAP24XX_CLKSEL_DSS1_MASK,
756 .clksel = dss1_fck_clksel,
757 .recalc = &omap2_clksel_recalc,
758};
759
760static const struct clksel_rate dss2_fck_sys_rates[] = {
761 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
762 { .div = 0 }
763};
764
765static const struct clksel_rate dss2_fck_48m_rates[] = {
766 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
767 { .div = 0 }
768};
769
770static const struct clksel dss2_fck_clksel[] = {
771 { .parent = &sys_ck, .rates = dss2_fck_sys_rates },
772 { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
773 { .parent = NULL }
774};
775
776static struct clk dss2_fck = { /* Alt clk used in power management */
777 .name = "dss2_fck",
778 .ops = &clkops_omap2_dflt,
779 .parent = &sys_ck, /* fixed at sys_ck or 48MHz */
780 .clkdm_name = "dss_clkdm",
781 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
782 .enable_bit = OMAP24XX_EN_DSS2_SHIFT,
783 .init = &omap2_init_clksel_parent,
784 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
785 .clksel_mask = OMAP24XX_CLKSEL_DSS2_MASK,
786 .clksel = dss2_fck_clksel,
787 .recalc = &omap2_clksel_recalc,
788};
789
790static struct clk dss_54m_fck = { /* Alt clk used in power management */
791 .name = "dss_54m_fck", /* 54m tv clk */
792 .ops = &clkops_omap2_dflt_wait,
793 .parent = &func_54m_ck,
794 .clkdm_name = "dss_clkdm",
795 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
796 .enable_bit = OMAP24XX_EN_TV_SHIFT,
797 .recalc = &followparent_recalc,
798};
799
800static struct clk wu_l4_ick = {
801 .name = "wu_l4_ick",
802 .ops = &clkops_null,
803 .parent = &sys_ck,
804 .clkdm_name = "wkup_clkdm",
805 .recalc = &followparent_recalc,
806};
807
808/*
809 * CORE power domain ICLK & FCLK defines.
810 * Many of the these can have more than one possible parent. Entries
811 * here will likely have an L4 interface parent, and may have multiple
812 * functional clock parents.
813 */
814static const struct clksel_rate gpt_alt_rates[] = {
815 { .div = 1, .val = 2, .flags = RATE_IN_24XX },
816 { .div = 0 }
817};
818
819static const struct clksel omap24xx_gpt_clksel[] = {
820 { .parent = &func_32k_ck, .rates = gpt_32k_rates },
821 { .parent = &sys_ck, .rates = gpt_sys_rates },
822 { .parent = &alt_ck, .rates = gpt_alt_rates },
823 { .parent = NULL },
824};
825
826static struct clk gpt1_ick = {
827 .name = "gpt1_ick",
828 .ops = &clkops_omap2_iclk_dflt_wait,
829 .parent = &wu_l4_ick,
830 .clkdm_name = "wkup_clkdm",
831 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
832 .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
833 .recalc = &followparent_recalc,
834};
835
836static struct clk gpt1_fck = {
837 .name = "gpt1_fck",
838 .ops = &clkops_omap2_dflt_wait,
839 .parent = &func_32k_ck,
840 .clkdm_name = "core_l4_clkdm",
841 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
842 .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
843 .init = &omap2_init_clksel_parent,
844 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1),
845 .clksel_mask = OMAP24XX_CLKSEL_GPT1_MASK,
846 .clksel = omap24xx_gpt_clksel,
847 .recalc = &omap2_clksel_recalc,
848 .round_rate = &omap2_clksel_round_rate,
849 .set_rate = &omap2_clksel_set_rate
850};
851
852static struct clk gpt2_ick = {
853 .name = "gpt2_ick",
854 .ops = &clkops_omap2_iclk_dflt_wait,
855 .parent = &l4_ck,
856 .clkdm_name = "core_l4_clkdm",
857 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
858 .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
859 .recalc = &followparent_recalc,
860};
861
862static struct clk gpt2_fck = {
863 .name = "gpt2_fck",
864 .ops = &clkops_omap2_dflt_wait,
865 .parent = &func_32k_ck,
866 .clkdm_name = "core_l4_clkdm",
867 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
868 .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
869 .init = &omap2_init_clksel_parent,
870 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
871 .clksel_mask = OMAP24XX_CLKSEL_GPT2_MASK,
872 .clksel = omap24xx_gpt_clksel,
873 .recalc = &omap2_clksel_recalc,
874};
875
876static struct clk gpt3_ick = {
877 .name = "gpt3_ick",
878 .ops = &clkops_omap2_iclk_dflt_wait,
879 .parent = &l4_ck,
880 .clkdm_name = "core_l4_clkdm",
881 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
882 .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
883 .recalc = &followparent_recalc,
884};
885
886static struct clk gpt3_fck = {
887 .name = "gpt3_fck",
888 .ops = &clkops_omap2_dflt_wait,
889 .parent = &func_32k_ck,
890 .clkdm_name = "core_l4_clkdm",
891 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
892 .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
893 .init = &omap2_init_clksel_parent,
894 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
895 .clksel_mask = OMAP24XX_CLKSEL_GPT3_MASK,
896 .clksel = omap24xx_gpt_clksel,
897 .recalc = &omap2_clksel_recalc,
898};
899
900static struct clk gpt4_ick = {
901 .name = "gpt4_ick",
902 .ops = &clkops_omap2_iclk_dflt_wait,
903 .parent = &l4_ck,
904 .clkdm_name = "core_l4_clkdm",
905 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
906 .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
907 .recalc = &followparent_recalc,
908};
909
910static struct clk gpt4_fck = {
911 .name = "gpt4_fck",
912 .ops = &clkops_omap2_dflt_wait,
913 .parent = &func_32k_ck,
914 .clkdm_name = "core_l4_clkdm",
915 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
916 .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
917 .init = &omap2_init_clksel_parent,
918 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
919 .clksel_mask = OMAP24XX_CLKSEL_GPT4_MASK,
920 .clksel = omap24xx_gpt_clksel,
921 .recalc = &omap2_clksel_recalc,
922};
923
924static struct clk gpt5_ick = {
925 .name = "gpt5_ick",
926 .ops = &clkops_omap2_iclk_dflt_wait,
927 .parent = &l4_ck,
928 .clkdm_name = "core_l4_clkdm",
929 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
930 .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
931 .recalc = &followparent_recalc,
932};
933
934static struct clk gpt5_fck = {
935 .name = "gpt5_fck",
936 .ops = &clkops_omap2_dflt_wait,
937 .parent = &func_32k_ck,
938 .clkdm_name = "core_l4_clkdm",
939 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
940 .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
941 .init = &omap2_init_clksel_parent,
942 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
943 .clksel_mask = OMAP24XX_CLKSEL_GPT5_MASK,
944 .clksel = omap24xx_gpt_clksel,
945 .recalc = &omap2_clksel_recalc,
946};
947
948static struct clk gpt6_ick = {
949 .name = "gpt6_ick",
950 .ops = &clkops_omap2_iclk_dflt_wait,
951 .parent = &l4_ck,
952 .clkdm_name = "core_l4_clkdm",
953 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
954 .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
955 .recalc = &followparent_recalc,
956};
957
958static struct clk gpt6_fck = {
959 .name = "gpt6_fck",
960 .ops = &clkops_omap2_dflt_wait,
961 .parent = &func_32k_ck,
962 .clkdm_name = "core_l4_clkdm",
963 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
964 .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
965 .init = &omap2_init_clksel_parent,
966 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
967 .clksel_mask = OMAP24XX_CLKSEL_GPT6_MASK,
968 .clksel = omap24xx_gpt_clksel,
969 .recalc = &omap2_clksel_recalc,
970};
971
972static struct clk gpt7_ick = {
973 .name = "gpt7_ick",
974 .ops = &clkops_omap2_iclk_dflt_wait,
975 .parent = &l4_ck,
976 .clkdm_name = "core_l4_clkdm",
977 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
978 .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
979 .recalc = &followparent_recalc,
980};
981
982static struct clk gpt7_fck = {
983 .name = "gpt7_fck",
984 .ops = &clkops_omap2_dflt_wait,
985 .parent = &func_32k_ck,
986 .clkdm_name = "core_l4_clkdm",
987 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
988 .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
989 .init = &omap2_init_clksel_parent,
990 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
991 .clksel_mask = OMAP24XX_CLKSEL_GPT7_MASK,
992 .clksel = omap24xx_gpt_clksel,
993 .recalc = &omap2_clksel_recalc,
994};
995
996static struct clk gpt8_ick = {
997 .name = "gpt8_ick",
998 .ops = &clkops_omap2_iclk_dflt_wait,
999 .parent = &l4_ck,
1000 .clkdm_name = "core_l4_clkdm",
1001 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1002 .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
1003 .recalc = &followparent_recalc,
1004};
1005
1006static struct clk gpt8_fck = {
1007 .name = "gpt8_fck",
1008 .ops = &clkops_omap2_dflt_wait,
1009 .parent = &func_32k_ck,
1010 .clkdm_name = "core_l4_clkdm",
1011 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1012 .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
1013 .init = &omap2_init_clksel_parent,
1014 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1015 .clksel_mask = OMAP24XX_CLKSEL_GPT8_MASK,
1016 .clksel = omap24xx_gpt_clksel,
1017 .recalc = &omap2_clksel_recalc,
1018};
1019
1020static struct clk gpt9_ick = {
1021 .name = "gpt9_ick",
1022 .ops = &clkops_omap2_iclk_dflt_wait,
1023 .parent = &l4_ck,
1024 .clkdm_name = "core_l4_clkdm",
1025 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1026 .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
1027 .recalc = &followparent_recalc,
1028};
1029
1030static struct clk gpt9_fck = {
1031 .name = "gpt9_fck",
1032 .ops = &clkops_omap2_dflt_wait,
1033 .parent = &func_32k_ck,
1034 .clkdm_name = "core_l4_clkdm",
1035 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1036 .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
1037 .init = &omap2_init_clksel_parent,
1038 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1039 .clksel_mask = OMAP24XX_CLKSEL_GPT9_MASK,
1040 .clksel = omap24xx_gpt_clksel,
1041 .recalc = &omap2_clksel_recalc,
1042};
1043
1044static struct clk gpt10_ick = {
1045 .name = "gpt10_ick",
1046 .ops = &clkops_omap2_iclk_dflt_wait,
1047 .parent = &l4_ck,
1048 .clkdm_name = "core_l4_clkdm",
1049 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1050 .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
1051 .recalc = &followparent_recalc,
1052};
1053
1054static struct clk gpt10_fck = {
1055 .name = "gpt10_fck",
1056 .ops = &clkops_omap2_dflt_wait,
1057 .parent = &func_32k_ck,
1058 .clkdm_name = "core_l4_clkdm",
1059 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1060 .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
1061 .init = &omap2_init_clksel_parent,
1062 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1063 .clksel_mask = OMAP24XX_CLKSEL_GPT10_MASK,
1064 .clksel = omap24xx_gpt_clksel,
1065 .recalc = &omap2_clksel_recalc,
1066};
1067
1068static struct clk gpt11_ick = {
1069 .name = "gpt11_ick",
1070 .ops = &clkops_omap2_iclk_dflt_wait,
1071 .parent = &l4_ck,
1072 .clkdm_name = "core_l4_clkdm",
1073 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1074 .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
1075 .recalc = &followparent_recalc,
1076};
1077
1078static struct clk gpt11_fck = {
1079 .name = "gpt11_fck",
1080 .ops = &clkops_omap2_dflt_wait,
1081 .parent = &func_32k_ck,
1082 .clkdm_name = "core_l4_clkdm",
1083 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1084 .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
1085 .init = &omap2_init_clksel_parent,
1086 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1087 .clksel_mask = OMAP24XX_CLKSEL_GPT11_MASK,
1088 .clksel = omap24xx_gpt_clksel,
1089 .recalc = &omap2_clksel_recalc,
1090};
1091
1092static struct clk gpt12_ick = {
1093 .name = "gpt12_ick",
1094 .ops = &clkops_omap2_iclk_dflt_wait,
1095 .parent = &l4_ck,
1096 .clkdm_name = "core_l4_clkdm",
1097 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1098 .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
1099 .recalc = &followparent_recalc,
1100};
1101
1102static struct clk gpt12_fck = {
1103 .name = "gpt12_fck",
1104 .ops = &clkops_omap2_dflt_wait,
1105 .parent = &secure_32k_ck,
1106 .clkdm_name = "core_l4_clkdm",
1107 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1108 .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
1109 .init = &omap2_init_clksel_parent,
1110 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1111 .clksel_mask = OMAP24XX_CLKSEL_GPT12_MASK,
1112 .clksel = omap24xx_gpt_clksel,
1113 .recalc = &omap2_clksel_recalc,
1114};
1115
1116static struct clk mcbsp1_ick = {
1117 .name = "mcbsp1_ick",
1118 .ops = &clkops_omap2_iclk_dflt_wait,
1119 .parent = &l4_ck,
1120 .clkdm_name = "core_l4_clkdm",
1121 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1122 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1123 .recalc = &followparent_recalc,
1124};
1125
1126static const struct clksel_rate common_mcbsp_96m_rates[] = {
1127 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
1128 { .div = 0 }
1129};
1130
1131static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1132 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1133 { .div = 0 }
1134};
1135
1136static const struct clksel mcbsp_fck_clksel[] = {
1137 { .parent = &func_96m_ck, .rates = common_mcbsp_96m_rates },
1138 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
1139 { .parent = NULL }
1140};
1141
1142static struct clk mcbsp1_fck = {
1143 .name = "mcbsp1_fck",
1144 .ops = &clkops_omap2_dflt_wait,
1145 .parent = &func_96m_ck,
1146 .init = &omap2_init_clksel_parent,
1147 .clkdm_name = "core_l4_clkdm",
1148 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1149 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1150 .clksel_reg = OMAP243X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1151 .clksel_mask = OMAP2_MCBSP1_CLKS_MASK,
1152 .clksel = mcbsp_fck_clksel,
1153 .recalc = &omap2_clksel_recalc,
1154};
1155
1156static struct clk mcbsp2_ick = {
1157 .name = "mcbsp2_ick",
1158 .ops = &clkops_omap2_iclk_dflt_wait,
1159 .parent = &l4_ck,
1160 .clkdm_name = "core_l4_clkdm",
1161 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1162 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1163 .recalc = &followparent_recalc,
1164};
1165
1166static struct clk mcbsp2_fck = {
1167 .name = "mcbsp2_fck",
1168 .ops = &clkops_omap2_dflt_wait,
1169 .parent = &func_96m_ck,
1170 .init = &omap2_init_clksel_parent,
1171 .clkdm_name = "core_l4_clkdm",
1172 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1173 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1174 .clksel_reg = OMAP243X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1175 .clksel_mask = OMAP2_MCBSP2_CLKS_MASK,
1176 .clksel = mcbsp_fck_clksel,
1177 .recalc = &omap2_clksel_recalc,
1178};
1179
1180static struct clk mcbsp3_ick = {
1181 .name = "mcbsp3_ick",
1182 .ops = &clkops_omap2_iclk_dflt_wait,
1183 .parent = &l4_ck,
1184 .clkdm_name = "core_l4_clkdm",
1185 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1186 .enable_bit = OMAP2430_EN_MCBSP3_SHIFT,
1187 .recalc = &followparent_recalc,
1188};
1189
1190static struct clk mcbsp3_fck = {
1191 .name = "mcbsp3_fck",
1192 .ops = &clkops_omap2_dflt_wait,
1193 .parent = &func_96m_ck,
1194 .init = &omap2_init_clksel_parent,
1195 .clkdm_name = "core_l4_clkdm",
1196 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1197 .enable_bit = OMAP2430_EN_MCBSP3_SHIFT,
1198 .clksel_reg = OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1),
1199 .clksel_mask = OMAP2_MCBSP3_CLKS_MASK,
1200 .clksel = mcbsp_fck_clksel,
1201 .recalc = &omap2_clksel_recalc,
1202};
1203
1204static struct clk mcbsp4_ick = {
1205 .name = "mcbsp4_ick",
1206 .ops = &clkops_omap2_iclk_dflt_wait,
1207 .parent = &l4_ck,
1208 .clkdm_name = "core_l4_clkdm",
1209 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1210 .enable_bit = OMAP2430_EN_MCBSP4_SHIFT,
1211 .recalc = &followparent_recalc,
1212};
1213
1214static struct clk mcbsp4_fck = {
1215 .name = "mcbsp4_fck",
1216 .ops = &clkops_omap2_dflt_wait,
1217 .parent = &func_96m_ck,
1218 .init = &omap2_init_clksel_parent,
1219 .clkdm_name = "core_l4_clkdm",
1220 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1221 .enable_bit = OMAP2430_EN_MCBSP4_SHIFT,
1222 .clksel_reg = OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1),
1223 .clksel_mask = OMAP2_MCBSP4_CLKS_MASK,
1224 .clksel = mcbsp_fck_clksel,
1225 .recalc = &omap2_clksel_recalc,
1226};
1227
1228static struct clk mcbsp5_ick = {
1229 .name = "mcbsp5_ick",
1230 .ops = &clkops_omap2_iclk_dflt_wait,
1231 .parent = &l4_ck,
1232 .clkdm_name = "core_l4_clkdm",
1233 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1234 .enable_bit = OMAP2430_EN_MCBSP5_SHIFT,
1235 .recalc = &followparent_recalc,
1236};
1237
1238static struct clk mcbsp5_fck = {
1239 .name = "mcbsp5_fck",
1240 .ops = &clkops_omap2_dflt_wait,
1241 .parent = &func_96m_ck,
1242 .init = &omap2_init_clksel_parent,
1243 .clkdm_name = "core_l4_clkdm",
1244 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1245 .enable_bit = OMAP2430_EN_MCBSP5_SHIFT,
1246 .clksel_reg = OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1),
1247 .clksel_mask = OMAP2_MCBSP5_CLKS_MASK,
1248 .clksel = mcbsp_fck_clksel,
1249 .recalc = &omap2_clksel_recalc,
1250};
1251
1252static struct clk mcspi1_ick = {
1253 .name = "mcspi1_ick",
1254 .ops = &clkops_omap2_iclk_dflt_wait,
1255 .parent = &l4_ck,
1256 .clkdm_name = "core_l4_clkdm",
1257 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1258 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1259 .recalc = &followparent_recalc,
1260};
1261
1262static struct clk mcspi1_fck = {
1263 .name = "mcspi1_fck",
1264 .ops = &clkops_omap2_dflt_wait,
1265 .parent = &func_48m_ck,
1266 .clkdm_name = "core_l4_clkdm",
1267 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1268 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1269 .recalc = &followparent_recalc,
1270};
1271
1272static struct clk mcspi2_ick = {
1273 .name = "mcspi2_ick",
1274 .ops = &clkops_omap2_iclk_dflt_wait,
1275 .parent = &l4_ck,
1276 .clkdm_name = "core_l4_clkdm",
1277 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1278 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1279 .recalc = &followparent_recalc,
1280};
1281
1282static struct clk mcspi2_fck = {
1283 .name = "mcspi2_fck",
1284 .ops = &clkops_omap2_dflt_wait,
1285 .parent = &func_48m_ck,
1286 .clkdm_name = "core_l4_clkdm",
1287 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1288 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1289 .recalc = &followparent_recalc,
1290};
1291
1292static struct clk mcspi3_ick = {
1293 .name = "mcspi3_ick",
1294 .ops = &clkops_omap2_iclk_dflt_wait,
1295 .parent = &l4_ck,
1296 .clkdm_name = "core_l4_clkdm",
1297 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1298 .enable_bit = OMAP2430_EN_MCSPI3_SHIFT,
1299 .recalc = &followparent_recalc,
1300};
1301
1302static struct clk mcspi3_fck = {
1303 .name = "mcspi3_fck",
1304 .ops = &clkops_omap2_dflt_wait,
1305 .parent = &func_48m_ck,
1306 .clkdm_name = "core_l4_clkdm",
1307 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1308 .enable_bit = OMAP2430_EN_MCSPI3_SHIFT,
1309 .recalc = &followparent_recalc,
1310};
1311
1312static struct clk uart1_ick = {
1313 .name = "uart1_ick",
1314 .ops = &clkops_omap2_iclk_dflt_wait,
1315 .parent = &l4_ck,
1316 .clkdm_name = "core_l4_clkdm",
1317 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1318 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
1319 .recalc = &followparent_recalc,
1320};
1321
1322static struct clk uart1_fck = {
1323 .name = "uart1_fck",
1324 .ops = &clkops_omap2_dflt_wait,
1325 .parent = &func_48m_ck,
1326 .clkdm_name = "core_l4_clkdm",
1327 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1328 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
1329 .recalc = &followparent_recalc,
1330};
1331
1332static struct clk uart2_ick = {
1333 .name = "uart2_ick",
1334 .ops = &clkops_omap2_iclk_dflt_wait,
1335 .parent = &l4_ck,
1336 .clkdm_name = "core_l4_clkdm",
1337 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1338 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
1339 .recalc = &followparent_recalc,
1340};
1341
1342static struct clk uart2_fck = {
1343 .name = "uart2_fck",
1344 .ops = &clkops_omap2_dflt_wait,
1345 .parent = &func_48m_ck,
1346 .clkdm_name = "core_l4_clkdm",
1347 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1348 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
1349 .recalc = &followparent_recalc,
1350};
1351
1352static struct clk uart3_ick = {
1353 .name = "uart3_ick",
1354 .ops = &clkops_omap2_iclk_dflt_wait,
1355 .parent = &l4_ck,
1356 .clkdm_name = "core_l4_clkdm",
1357 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1358 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
1359 .recalc = &followparent_recalc,
1360};
1361
1362static struct clk uart3_fck = {
1363 .name = "uart3_fck",
1364 .ops = &clkops_omap2_dflt_wait,
1365 .parent = &func_48m_ck,
1366 .clkdm_name = "core_l4_clkdm",
1367 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1368 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
1369 .recalc = &followparent_recalc,
1370};
1371
1372static struct clk gpios_ick = {
1373 .name = "gpios_ick",
1374 .ops = &clkops_omap2_iclk_dflt_wait,
1375 .parent = &wu_l4_ick,
1376 .clkdm_name = "wkup_clkdm",
1377 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1378 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
1379 .recalc = &followparent_recalc,
1380};
1381
1382static struct clk gpios_fck = {
1383 .name = "gpios_fck",
1384 .ops = &clkops_omap2_dflt_wait,
1385 .parent = &func_32k_ck,
1386 .clkdm_name = "wkup_clkdm",
1387 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1388 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
1389 .recalc = &followparent_recalc,
1390};
1391
1392static struct clk mpu_wdt_ick = {
1393 .name = "mpu_wdt_ick",
1394 .ops = &clkops_omap2_iclk_dflt_wait,
1395 .parent = &wu_l4_ick,
1396 .clkdm_name = "wkup_clkdm",
1397 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1398 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
1399 .recalc = &followparent_recalc,
1400};
1401
1402static struct clk mpu_wdt_fck = {
1403 .name = "mpu_wdt_fck",
1404 .ops = &clkops_omap2_dflt_wait,
1405 .parent = &func_32k_ck,
1406 .clkdm_name = "wkup_clkdm",
1407 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1408 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
1409 .recalc = &followparent_recalc,
1410};
1411
1412static struct clk sync_32k_ick = {
1413 .name = "sync_32k_ick",
1414 .ops = &clkops_omap2_iclk_dflt_wait,
1415 .flags = ENABLE_ON_INIT,
1416 .parent = &wu_l4_ick,
1417 .clkdm_name = "wkup_clkdm",
1418 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1419 .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT,
1420 .recalc = &followparent_recalc,
1421};
1422
1423static struct clk wdt1_ick = {
1424 .name = "wdt1_ick",
1425 .ops = &clkops_omap2_iclk_dflt_wait,
1426 .parent = &wu_l4_ick,
1427 .clkdm_name = "wkup_clkdm",
1428 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1429 .enable_bit = OMAP24XX_EN_WDT1_SHIFT,
1430 .recalc = &followparent_recalc,
1431};
1432
1433static struct clk omapctrl_ick = {
1434 .name = "omapctrl_ick",
1435 .ops = &clkops_omap2_iclk_dflt_wait,
1436 .flags = ENABLE_ON_INIT,
1437 .parent = &wu_l4_ick,
1438 .clkdm_name = "wkup_clkdm",
1439 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1440 .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT,
1441 .recalc = &followparent_recalc,
1442};
1443
1444static struct clk icr_ick = {
1445 .name = "icr_ick",
1446 .ops = &clkops_omap2_iclk_dflt_wait,
1447 .parent = &wu_l4_ick,
1448 .clkdm_name = "wkup_clkdm",
1449 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1450 .enable_bit = OMAP2430_EN_ICR_SHIFT,
1451 .recalc = &followparent_recalc,
1452};
1453
1454static struct clk cam_ick = {
1455 .name = "cam_ick",
1456 .ops = &clkops_omap2_iclk_dflt,
1457 .parent = &l4_ck,
1458 .clkdm_name = "core_l4_clkdm",
1459 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1460 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
1461 .recalc = &followparent_recalc,
1462};
1463
1464/*
1465 * cam_fck controls both CAM_MCLK and CAM_FCLK. It should probably be
1466 * split into two separate clocks, since the parent clocks are different
1467 * and the clockdomains are also different.
1468 */
1469static struct clk cam_fck = {
1470 .name = "cam_fck",
1471 .ops = &clkops_omap2_dflt,
1472 .parent = &func_96m_ck,
1473 .clkdm_name = "core_l3_clkdm",
1474 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1475 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
1476 .recalc = &followparent_recalc,
1477};
1478
1479static struct clk mailboxes_ick = {
1480 .name = "mailboxes_ick",
1481 .ops = &clkops_omap2_iclk_dflt_wait,
1482 .parent = &l4_ck,
1483 .clkdm_name = "core_l4_clkdm",
1484 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1485 .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
1486 .recalc = &followparent_recalc,
1487};
1488
1489static struct clk wdt4_ick = {
1490 .name = "wdt4_ick",
1491 .ops = &clkops_omap2_iclk_dflt_wait,
1492 .parent = &l4_ck,
1493 .clkdm_name = "core_l4_clkdm",
1494 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1495 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
1496 .recalc = &followparent_recalc,
1497};
1498
1499static struct clk wdt4_fck = {
1500 .name = "wdt4_fck",
1501 .ops = &clkops_omap2_dflt_wait,
1502 .parent = &func_32k_ck,
1503 .clkdm_name = "core_l4_clkdm",
1504 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1505 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
1506 .recalc = &followparent_recalc,
1507};
1508
1509static struct clk mspro_ick = {
1510 .name = "mspro_ick",
1511 .ops = &clkops_omap2_iclk_dflt_wait,
1512 .parent = &l4_ck,
1513 .clkdm_name = "core_l4_clkdm",
1514 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1515 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
1516 .recalc = &followparent_recalc,
1517};
1518
1519static struct clk mspro_fck = {
1520 .name = "mspro_fck",
1521 .ops = &clkops_omap2_dflt_wait,
1522 .parent = &func_96m_ck,
1523 .clkdm_name = "core_l4_clkdm",
1524 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1525 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
1526 .recalc = &followparent_recalc,
1527};
1528
1529static struct clk fac_ick = {
1530 .name = "fac_ick",
1531 .ops = &clkops_omap2_iclk_dflt_wait,
1532 .parent = &l4_ck,
1533 .clkdm_name = "core_l4_clkdm",
1534 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1535 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
1536 .recalc = &followparent_recalc,
1537};
1538
1539static struct clk fac_fck = {
1540 .name = "fac_fck",
1541 .ops = &clkops_omap2_dflt_wait,
1542 .parent = &func_12m_ck,
1543 .clkdm_name = "core_l4_clkdm",
1544 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1545 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
1546 .recalc = &followparent_recalc,
1547};
1548
1549static struct clk hdq_ick = {
1550 .name = "hdq_ick",
1551 .ops = &clkops_omap2_iclk_dflt_wait,
1552 .parent = &l4_ck,
1553 .clkdm_name = "core_l4_clkdm",
1554 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1555 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
1556 .recalc = &followparent_recalc,
1557};
1558
1559static struct clk hdq_fck = {
1560 .name = "hdq_fck",
1561 .ops = &clkops_omap2_dflt_wait,
1562 .parent = &func_12m_ck,
1563 .clkdm_name = "core_l4_clkdm",
1564 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1565 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
1566 .recalc = &followparent_recalc,
1567};
1568
1569/*
1570 * XXX This is marked as a 2420-only define, but it claims to be present
1571 * on 2430 also. Double-check.
1572 */
1573static struct clk i2c2_ick = {
1574 .name = "i2c2_ick",
1575 .ops = &clkops_omap2_iclk_dflt_wait,
1576 .parent = &l4_ck,
1577 .clkdm_name = "core_l4_clkdm",
1578 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1579 .enable_bit = OMAP2420_EN_I2C2_SHIFT,
1580 .recalc = &followparent_recalc,
1581};
1582
1583static struct clk i2chs2_fck = {
1584 .name = "i2chs2_fck",
1585 .ops = &clkops_omap2430_i2chs_wait,
1586 .parent = &func_96m_ck,
1587 .clkdm_name = "core_l4_clkdm",
1588 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1589 .enable_bit = OMAP2430_EN_I2CHS2_SHIFT,
1590 .recalc = &followparent_recalc,
1591};
1592
1593/*
1594 * XXX This is marked as a 2420-only define, but it claims to be present
1595 * on 2430 also. Double-check.
1596 */
1597static struct clk i2c1_ick = {
1598 .name = "i2c1_ick",
1599 .ops = &clkops_omap2_iclk_dflt_wait,
1600 .parent = &l4_ck,
1601 .clkdm_name = "core_l4_clkdm",
1602 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1603 .enable_bit = OMAP2420_EN_I2C1_SHIFT,
1604 .recalc = &followparent_recalc,
1605};
1606
1607static struct clk i2chs1_fck = {
1608 .name = "i2chs1_fck",
1609 .ops = &clkops_omap2430_i2chs_wait,
1610 .parent = &func_96m_ck,
1611 .clkdm_name = "core_l4_clkdm",
1612 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1613 .enable_bit = OMAP2430_EN_I2CHS1_SHIFT,
1614 .recalc = &followparent_recalc,
1615};
1616
1617/*
1618 * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
1619 * accesses derived from this data.
1620 */
1621static struct clk gpmc_fck = {
1622 .name = "gpmc_fck",
1623 .ops = &clkops_omap2_iclk_idle_only,
1624 .parent = &core_l3_ck,
1625 .flags = ENABLE_ON_INIT,
1626 .clkdm_name = "core_l3_clkdm",
1627 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1628 .enable_bit = OMAP24XX_AUTO_GPMC_SHIFT,
1629 .recalc = &followparent_recalc,
1630};
1631
1632static struct clk sdma_fck = {
1633 .name = "sdma_fck",
1634 .ops = &clkops_null, /* RMK: missing? */
1635 .parent = &core_l3_ck,
1636 .clkdm_name = "core_l3_clkdm",
1637 .recalc = &followparent_recalc,
1638};
1639
1640/*
1641 * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
1642 * accesses derived from this data.
1643 */
1644static struct clk sdma_ick = {
1645 .name = "sdma_ick",
1646 .ops = &clkops_omap2_iclk_idle_only,
1647 .parent = &core_l3_ck,
1648 .clkdm_name = "core_l3_clkdm",
1649 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1650 .enable_bit = OMAP24XX_AUTO_SDMA_SHIFT,
1651 .recalc = &followparent_recalc,
1652};
1653
1654static struct clk sdrc_ick = {
1655 .name = "sdrc_ick",
1656 .ops = &clkops_omap2_iclk_idle_only,
1657 .parent = &core_l3_ck,
1658 .flags = ENABLE_ON_INIT,
1659 .clkdm_name = "core_l3_clkdm",
1660 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1661 .enable_bit = OMAP2430_EN_SDRC_SHIFT,
1662 .recalc = &followparent_recalc,
1663};
1664
1665static struct clk des_ick = {
1666 .name = "des_ick",
1667 .ops = &clkops_omap2_iclk_dflt_wait,
1668 .parent = &l4_ck,
1669 .clkdm_name = "core_l4_clkdm",
1670 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1671 .enable_bit = OMAP24XX_EN_DES_SHIFT,
1672 .recalc = &followparent_recalc,
1673};
1674
1675static struct clk sha_ick = {
1676 .name = "sha_ick",
1677 .ops = &clkops_omap2_iclk_dflt_wait,
1678 .parent = &l4_ck,
1679 .clkdm_name = "core_l4_clkdm",
1680 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1681 .enable_bit = OMAP24XX_EN_SHA_SHIFT,
1682 .recalc = &followparent_recalc,
1683};
1684
1685static struct clk rng_ick = {
1686 .name = "rng_ick",
1687 .ops = &clkops_omap2_iclk_dflt_wait,
1688 .parent = &l4_ck,
1689 .clkdm_name = "core_l4_clkdm",
1690 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1691 .enable_bit = OMAP24XX_EN_RNG_SHIFT,
1692 .recalc = &followparent_recalc,
1693};
1694
1695static struct clk aes_ick = {
1696 .name = "aes_ick",
1697 .ops = &clkops_omap2_iclk_dflt_wait,
1698 .parent = &l4_ck,
1699 .clkdm_name = "core_l4_clkdm",
1700 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1701 .enable_bit = OMAP24XX_EN_AES_SHIFT,
1702 .recalc = &followparent_recalc,
1703};
1704
1705static struct clk pka_ick = {
1706 .name = "pka_ick",
1707 .ops = &clkops_omap2_iclk_dflt_wait,
1708 .parent = &l4_ck,
1709 .clkdm_name = "core_l4_clkdm",
1710 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1711 .enable_bit = OMAP24XX_EN_PKA_SHIFT,
1712 .recalc = &followparent_recalc,
1713};
1714
1715static struct clk usb_fck = {
1716 .name = "usb_fck",
1717 .ops = &clkops_omap2_dflt_wait,
1718 .parent = &func_48m_ck,
1719 .clkdm_name = "core_l3_clkdm",
1720 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1721 .enable_bit = OMAP24XX_EN_USB_SHIFT,
1722 .recalc = &followparent_recalc,
1723};
1724
1725static struct clk usbhs_ick = {
1726 .name = "usbhs_ick",
1727 .ops = &clkops_omap2_iclk_dflt_wait,
1728 .parent = &core_l3_ck,
1729 .clkdm_name = "core_l3_clkdm",
1730 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1731 .enable_bit = OMAP2430_EN_USBHS_SHIFT,
1732 .recalc = &followparent_recalc,
1733};
1734
1735static struct clk mmchs1_ick = {
1736 .name = "mmchs1_ick",
1737 .ops = &clkops_omap2_iclk_dflt_wait,
1738 .parent = &l4_ck,
1739 .clkdm_name = "core_l4_clkdm",
1740 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1741 .enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
1742 .recalc = &followparent_recalc,
1743};
1744
1745static struct clk mmchs1_fck = {
1746 .name = "mmchs1_fck",
1747 .ops = &clkops_omap2_dflt_wait,
1748 .parent = &func_96m_ck,
1749 .clkdm_name = "core_l4_clkdm",
1750 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1751 .enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
1752 .recalc = &followparent_recalc,
1753};
1754
1755static struct clk mmchs2_ick = {
1756 .name = "mmchs2_ick",
1757 .ops = &clkops_omap2_iclk_dflt_wait,
1758 .parent = &l4_ck,
1759 .clkdm_name = "core_l4_clkdm",
1760 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1761 .enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
1762 .recalc = &followparent_recalc,
1763};
1764
1765static struct clk mmchs2_fck = {
1766 .name = "mmchs2_fck",
1767 .ops = &clkops_omap2_dflt_wait,
1768 .parent = &func_96m_ck,
1769 .clkdm_name = "core_l4_clkdm",
1770 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1771 .enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
1772 .recalc = &followparent_recalc,
1773};
1774
1775static struct clk gpio5_ick = {
1776 .name = "gpio5_ick",
1777 .ops = &clkops_omap2_iclk_dflt_wait,
1778 .parent = &l4_ck,
1779 .clkdm_name = "core_l4_clkdm",
1780 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1781 .enable_bit = OMAP2430_EN_GPIO5_SHIFT,
1782 .recalc = &followparent_recalc,
1783};
1784
1785static struct clk gpio5_fck = {
1786 .name = "gpio5_fck",
1787 .ops = &clkops_omap2_dflt_wait,
1788 .parent = &func_32k_ck,
1789 .clkdm_name = "core_l4_clkdm",
1790 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1791 .enable_bit = OMAP2430_EN_GPIO5_SHIFT,
1792 .recalc = &followparent_recalc,
1793};
1794
1795static struct clk mdm_intc_ick = {
1796 .name = "mdm_intc_ick",
1797 .ops = &clkops_omap2_iclk_dflt_wait,
1798 .parent = &l4_ck,
1799 .clkdm_name = "core_l4_clkdm",
1800 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1801 .enable_bit = OMAP2430_EN_MDM_INTC_SHIFT,
1802 .recalc = &followparent_recalc,
1803};
1804
1805static struct clk mmchsdb1_fck = {
1806 .name = "mmchsdb1_fck",
1807 .ops = &clkops_omap2_dflt_wait,
1808 .parent = &func_32k_ck,
1809 .clkdm_name = "core_l4_clkdm",
1810 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1811 .enable_bit = OMAP2430_EN_MMCHSDB1_SHIFT,
1812 .recalc = &followparent_recalc,
1813};
1814
1815static struct clk mmchsdb2_fck = {
1816 .name = "mmchsdb2_fck",
1817 .ops = &clkops_omap2_dflt_wait,
1818 .parent = &func_32k_ck,
1819 .clkdm_name = "core_l4_clkdm",
1820 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1821 .enable_bit = OMAP2430_EN_MMCHSDB2_SHIFT,
1822 .recalc = &followparent_recalc,
1823};
1824
1825/*
1826 * This clock is a composite clock which does entire set changes then
1827 * forces a rebalance. It keys on the MPU speed, but it really could
1828 * be any key speed part of a set in the rate table.
1829 *
1830 * to really change a set, you need memory table sets which get changed
1831 * in sram, pre-notifiers & post notifiers, changing the top set, without
1832 * having low level display recalc's won't work... this is why dpm notifiers
1833 * work, isr's off, walk a list of clocks already _off_ and not messing with
1834 * the bus.
1835 *
1836 * This clock should have no parent. It embodies the entire upper level
1837 * active set. A parent will mess up some of the init also.
1838 */
1839static struct clk virt_prcm_set = {
1840 .name = "virt_prcm_set",
1841 .ops = &clkops_null,
1842 .parent = &mpu_ck, /* Indexed by mpu speed, no parent */
1843 .recalc = &omap2_table_mpu_recalc, /* sets are keyed on mpu rate */
1844 .set_rate = &omap2_select_table_rate,
1845 .round_rate = &omap2_round_to_table_rate,
1846};
1847
1848
1849/*
1850 * clkdev integration
1851 */
1852
1853static struct omap_clk omap2430_clks[] = {
1854 /* external root sources */
1855 CLK(NULL, "func_32k_ck", &func_32k_ck, CK_243X),
1856 CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_243X),
1857 CLK(NULL, "osc_ck", &osc_ck, CK_243X),
1858 CLK("twl", "fck", &osc_ck, CK_243X),
1859 CLK(NULL, "sys_ck", &sys_ck, CK_243X),
1860 CLK(NULL, "alt_ck", &alt_ck, CK_243X),
1861 CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_243X),
1862 /* internal analog sources */
1863 CLK(NULL, "dpll_ck", &dpll_ck, CK_243X),
1864 CLK(NULL, "apll96_ck", &apll96_ck, CK_243X),
1865 CLK(NULL, "apll54_ck", &apll54_ck, CK_243X),
1866 /* internal prcm root sources */
1867 CLK(NULL, "func_54m_ck", &func_54m_ck, CK_243X),
1868 CLK(NULL, "core_ck", &core_ck, CK_243X),
1869 CLK(NULL, "func_96m_ck", &func_96m_ck, CK_243X),
1870 CLK(NULL, "func_48m_ck", &func_48m_ck, CK_243X),
1871 CLK(NULL, "func_12m_ck", &func_12m_ck, CK_243X),
1872 CLK(NULL, "ck_wdt1_osc", &wdt1_osc_ck, CK_243X),
1873 CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_243X),
1874 CLK(NULL, "sys_clkout", &sys_clkout, CK_243X),
1875 CLK(NULL, "emul_ck", &emul_ck, CK_243X),
1876 /* mpu domain clocks */
1877 CLK(NULL, "mpu_ck", &mpu_ck, CK_243X),
1878 /* dsp domain clocks */
1879 CLK(NULL, "dsp_fck", &dsp_fck, CK_243X),
1880 CLK(NULL, "iva2_1_ick", &iva2_1_ick, CK_243X),
1881 /* GFX domain clocks */
1882 CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_243X),
1883 CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_243X),
1884 CLK(NULL, "gfx_ick", &gfx_ick, CK_243X),
1885 /* Modem domain clocks */
1886 CLK(NULL, "mdm_ick", &mdm_ick, CK_243X),
1887 CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X),
1888 /* DSS domain clocks */
1889 CLK("omapdss_dss", "ick", &dss_ick, CK_243X),
1890 CLK(NULL, "dss_ick", &dss_ick, CK_243X),
1891 CLK(NULL, "dss1_fck", &dss1_fck, CK_243X),
1892 CLK(NULL, "dss2_fck", &dss2_fck, CK_243X),
1893 CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_243X),
1894 /* L3 domain clocks */
1895 CLK(NULL, "core_l3_ck", &core_l3_ck, CK_243X),
1896 CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_243X),
1897 CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_243X),
1898 /* L4 domain clocks */
1899 CLK(NULL, "l4_ck", &l4_ck, CK_243X),
1900 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_243X),
1901 CLK(NULL, "wu_l4_ick", &wu_l4_ick, CK_243X),
1902 /* virtual meta-group clock */
1903 CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_243X),
1904 /* general l4 interface ck, multi-parent functional clk */
1905 CLK(NULL, "gpt1_ick", &gpt1_ick, CK_243X),
1906 CLK(NULL, "gpt1_fck", &gpt1_fck, CK_243X),
1907 CLK(NULL, "gpt2_ick", &gpt2_ick, CK_243X),
1908 CLK(NULL, "gpt2_fck", &gpt2_fck, CK_243X),
1909 CLK(NULL, "gpt3_ick", &gpt3_ick, CK_243X),
1910 CLK(NULL, "gpt3_fck", &gpt3_fck, CK_243X),
1911 CLK(NULL, "gpt4_ick", &gpt4_ick, CK_243X),
1912 CLK(NULL, "gpt4_fck", &gpt4_fck, CK_243X),
1913 CLK(NULL, "gpt5_ick", &gpt5_ick, CK_243X),
1914 CLK(NULL, "gpt5_fck", &gpt5_fck, CK_243X),
1915 CLK(NULL, "gpt6_ick", &gpt6_ick, CK_243X),
1916 CLK(NULL, "gpt6_fck", &gpt6_fck, CK_243X),
1917 CLK(NULL, "gpt7_ick", &gpt7_ick, CK_243X),
1918 CLK(NULL, "gpt7_fck", &gpt7_fck, CK_243X),
1919 CLK(NULL, "gpt8_ick", &gpt8_ick, CK_243X),
1920 CLK(NULL, "gpt8_fck", &gpt8_fck, CK_243X),
1921 CLK(NULL, "gpt9_ick", &gpt9_ick, CK_243X),
1922 CLK(NULL, "gpt9_fck", &gpt9_fck, CK_243X),
1923 CLK(NULL, "gpt10_ick", &gpt10_ick, CK_243X),
1924 CLK(NULL, "gpt10_fck", &gpt10_fck, CK_243X),
1925 CLK(NULL, "gpt11_ick", &gpt11_ick, CK_243X),
1926 CLK(NULL, "gpt11_fck", &gpt11_fck, CK_243X),
1927 CLK(NULL, "gpt12_ick", &gpt12_ick, CK_243X),
1928 CLK(NULL, "gpt12_fck", &gpt12_fck, CK_243X),
1929 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_243X),
1930 CLK(NULL, "mcbsp1_ick", &mcbsp1_ick, CK_243X),
1931 CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_243X),
1932 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_243X),
1933 CLK(NULL, "mcbsp2_ick", &mcbsp2_ick, CK_243X),
1934 CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_243X),
1935 CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_243X),
1936 CLK(NULL, "mcbsp3_ick", &mcbsp3_ick, CK_243X),
1937 CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_243X),
1938 CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_243X),
1939 CLK(NULL, "mcbsp4_ick", &mcbsp4_ick, CK_243X),
1940 CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_243X),
1941 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_243X),
1942 CLK(NULL, "mcbsp5_ick", &mcbsp5_ick, CK_243X),
1943 CLK(NULL, "mcbsp5_fck", &mcbsp5_fck, CK_243X),
1944 CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_243X),
1945 CLK(NULL, "mcspi1_ick", &mcspi1_ick, CK_243X),
1946 CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_243X),
1947 CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_243X),
1948 CLK(NULL, "mcspi2_ick", &mcspi2_ick, CK_243X),
1949 CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_243X),
1950 CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_243X),
1951 CLK(NULL, "mcspi3_ick", &mcspi3_ick, CK_243X),
1952 CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_243X),
1953 CLK(NULL, "uart1_ick", &uart1_ick, CK_243X),
1954 CLK(NULL, "uart1_fck", &uart1_fck, CK_243X),
1955 CLK(NULL, "uart2_ick", &uart2_ick, CK_243X),
1956 CLK(NULL, "uart2_fck", &uart2_fck, CK_243X),
1957 CLK(NULL, "uart3_ick", &uart3_ick, CK_243X),
1958 CLK(NULL, "uart3_fck", &uart3_fck, CK_243X),
1959 CLK(NULL, "gpios_ick", &gpios_ick, CK_243X),
1960 CLK(NULL, "gpios_fck", &gpios_fck, CK_243X),
1961 CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_243X),
1962 CLK(NULL, "mpu_wdt_ick", &mpu_wdt_ick, CK_243X),
1963 CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck, CK_243X),
1964 CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_243X),
1965 CLK(NULL, "wdt1_ick", &wdt1_ick, CK_243X),
1966 CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_243X),
1967 CLK(NULL, "icr_ick", &icr_ick, CK_243X),
1968 CLK("omap24xxcam", "fck", &cam_fck, CK_243X),
1969 CLK(NULL, "cam_fck", &cam_fck, CK_243X),
1970 CLK("omap24xxcam", "ick", &cam_ick, CK_243X),
1971 CLK(NULL, "cam_ick", &cam_ick, CK_243X),
1972 CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_243X),
1973 CLK(NULL, "wdt4_ick", &wdt4_ick, CK_243X),
1974 CLK(NULL, "wdt4_fck", &wdt4_fck, CK_243X),
1975 CLK(NULL, "mspro_ick", &mspro_ick, CK_243X),
1976 CLK(NULL, "mspro_fck", &mspro_fck, CK_243X),
1977 CLK(NULL, "fac_ick", &fac_ick, CK_243X),
1978 CLK(NULL, "fac_fck", &fac_fck, CK_243X),
1979 CLK("omap_hdq.0", "ick", &hdq_ick, CK_243X),
1980 CLK(NULL, "hdq_ick", &hdq_ick, CK_243X),
1981 CLK("omap_hdq.1", "fck", &hdq_fck, CK_243X),
1982 CLK(NULL, "hdq_fck", &hdq_fck, CK_243X),
1983 CLK("omap_i2c.1", "ick", &i2c1_ick, CK_243X),
1984 CLK(NULL, "i2c1_ick", &i2c1_ick, CK_243X),
1985 CLK(NULL, "i2chs1_fck", &i2chs1_fck, CK_243X),
1986 CLK("omap_i2c.2", "ick", &i2c2_ick, CK_243X),
1987 CLK(NULL, "i2c2_ick", &i2c2_ick, CK_243X),
1988 CLK(NULL, "i2chs2_fck", &i2chs2_fck, CK_243X),
1989 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_243X),
1990 CLK(NULL, "sdma_fck", &sdma_fck, CK_243X),
1991 CLK(NULL, "sdma_ick", &sdma_ick, CK_243X),
1992 CLK(NULL, "sdrc_ick", &sdrc_ick, CK_243X),
1993 CLK(NULL, "des_ick", &des_ick, CK_243X),
1994 CLK("omap-sham", "ick", &sha_ick, CK_243X),
1995 CLK("omap_rng", "ick", &rng_ick, CK_243X),
1996 CLK(NULL, "rng_ick", &rng_ick, CK_243X),
1997 CLK("omap-aes", "ick", &aes_ick, CK_243X),
1998 CLK(NULL, "pka_ick", &pka_ick, CK_243X),
1999 CLK(NULL, "usb_fck", &usb_fck, CK_243X),
2000 CLK("musb-omap2430", "ick", &usbhs_ick, CK_243X),
2001 CLK(NULL, "usbhs_ick", &usbhs_ick, CK_243X),
2002 CLK("omap_hsmmc.0", "ick", &mmchs1_ick, CK_243X),
2003 CLK(NULL, "mmchs1_ick", &mmchs1_ick, CK_243X),
2004 CLK(NULL, "mmchs1_fck", &mmchs1_fck, CK_243X),
2005 CLK("omap_hsmmc.1", "ick", &mmchs2_ick, CK_243X),
2006 CLK(NULL, "mmchs2_ick", &mmchs2_ick, CK_243X),
2007 CLK(NULL, "mmchs2_fck", &mmchs2_fck, CK_243X),
2008 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_243X),
2009 CLK(NULL, "gpio5_fck", &gpio5_fck, CK_243X),
2010 CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X),
2011 CLK("omap_hsmmc.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X),
2012 CLK(NULL, "mmchsdb1_fck", &mmchsdb1_fck, CK_243X),
2013 CLK("omap_hsmmc.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X),
2014 CLK(NULL, "mmchsdb2_fck", &mmchsdb2_fck, CK_243X),
2015 CLK(NULL, "timer_32k_ck", &func_32k_ck, CK_243X),
2016 CLK(NULL, "timer_sys_ck", &sys_ck, CK_243X),
2017 CLK(NULL, "timer_ext_ck", &alt_ck, CK_243X),
2018 CLK(NULL, "cpufreq_ck", &virt_prcm_set, CK_243X),
2019};
2020
2021/*
2022 * init code
2023 */
2024
2025int __init omap2430_clk_init(void)
2026{
2027 struct omap_clk *c;
2028
2029 prcm_clksrc_ctrl = OMAP2430_PRCM_CLKSRC_CTRL;
2030 cpu_mask = RATE_IN_243X;
2031 rate_table = omap2430_rate_table;
2032
2033 for (c = omap2430_clks; c < omap2430_clks + ARRAY_SIZE(omap2430_clks);
2034 c++)
2035 clk_preinit(c->lk.clk);
2036
2037 osc_ck.rate = omap2_osc_clk_recalc(&osc_ck);
2038 propagate_rate(&osc_ck);
2039 sys_ck.rate = omap2xxx_sys_clk_recalc(&sys_ck);
2040 propagate_rate(&sys_ck);
2041
2042 for (c = omap2430_clks; c < omap2430_clks + ARRAY_SIZE(omap2430_clks);
2043 c++) {
2044 clkdev_add(&c->lk);
2045 clk_register(c->lk.clk);
2046 omap2_init_clk_clkdm(c->lk.clk);
2047 }
2048
2049 omap2xxx_clkt_vps_late_init();
2050
2051 /* Disable autoidle on all clocks; let the PM code enable it later */
2052 omap_clk_disable_autoidle_all();
2053
2054 /* XXX Can this be done from the virt_prcm_set clk init function? */
2055 omap2xxx_clkt_vps_check_bootloader_rates();
2056
2057 recalculate_root_clocks();
2058
2059 pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n",
2060 (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
2061 (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
2062
2063 /*
2064 * Only enable those clocks we will need, let the drivers
2065 * enable other clocks as necessary
2066 */
2067 clk_enable_init_clocks();
2068
2069 return 0;
2070}
2071
diff --git a/arch/arm/mach-omap2/clock2xxx.c b/arch/arm/mach-omap2/clock2xxx.c
index 5f7faeb4c19b..1ff646908627 100644
--- a/arch/arm/mach-omap2/clock2xxx.c
+++ b/arch/arm/mach-omap2/clock2xxx.c
@@ -28,6 +28,7 @@
28#include "cm.h" 28#include "cm.h"
29#include "cm-regbits-24xx.h" 29#include "cm-regbits-24xx.h"
30 30
31struct clk_hw *dclk_hw;
31/* 32/*
32 * Omap24xx specific clock functions 33 * Omap24xx specific clock functions
33 */ 34 */
diff --git a/arch/arm/mach-omap2/clock2xxx.h b/arch/arm/mach-omap2/clock2xxx.h
index ce809c913b6f..539dc08afbba 100644
--- a/arch/arm/mach-omap2/clock2xxx.h
+++ b/arch/arm/mach-omap2/clock2xxx.h
@@ -8,18 +8,32 @@
8#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK2XXX_H 8#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK2XXX_H
9#define __ARCH_ARM_MACH_OMAP2_CLOCK2XXX_H 9#define __ARCH_ARM_MACH_OMAP2_CLOCK2XXX_H
10 10
11unsigned long omap2_table_mpu_recalc(struct clk *clk); 11#include <linux/clk-provider.h>
12int omap2_select_table_rate(struct clk *clk, unsigned long rate); 12#include "clock.h"
13long omap2_round_to_table_rate(struct clk *clk, unsigned long rate); 13
14unsigned long omap2xxx_sys_clk_recalc(struct clk *clk); 14unsigned long omap2_table_mpu_recalc(struct clk_hw *clk,
15unsigned long omap2_osc_clk_recalc(struct clk *clk); 15 unsigned long parent_rate);
16unsigned long omap2_dpllcore_recalc(struct clk *clk); 16int omap2_select_table_rate(struct clk_hw *hw, unsigned long rate,
17int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate); 17 unsigned long parent_rate);
18long omap2_round_to_table_rate(struct clk_hw *hw, unsigned long rate,
19 unsigned long *parent_rate);
20unsigned long omap2xxx_sys_clk_recalc(struct clk_hw *clk,
21 unsigned long parent_rate);
22unsigned long omap2_osc_clk_recalc(struct clk_hw *clk,
23 unsigned long parent_rate);
24unsigned long omap2_dpllcore_recalc(struct clk_hw *hw,
25 unsigned long parent_rate);
26int omap2_reprogram_dpllcore(struct clk_hw *clk, unsigned long rate,
27 unsigned long parent_rate);
28void omap2xxx_clkt_dpllcore_init(struct clk_hw *hw);
29unsigned long omap2_clk_apll54_recalc(struct clk_hw *hw,
30 unsigned long parent_rate);
31unsigned long omap2_clk_apll96_recalc(struct clk_hw *hw,
32 unsigned long parent_rate);
18unsigned long omap2xxx_clk_get_core_rate(void); 33unsigned long omap2xxx_clk_get_core_rate(void);
19u32 omap2xxx_get_apll_clkin(void); 34u32 omap2xxx_get_apll_clkin(void);
20u32 omap2xxx_get_sysclkdiv(void); 35u32 omap2xxx_get_sysclkdiv(void);
21void omap2xxx_clk_prepare_for_reboot(void); 36void omap2xxx_clk_prepare_for_reboot(void);
22void omap2xxx_clkt_dpllcore_init(struct clk *clk);
23void omap2xxx_clkt_vps_check_bootloader_rates(void); 37void omap2xxx_clkt_vps_check_bootloader_rates(void);
24void omap2xxx_clkt_vps_late_init(void); 38void omap2xxx_clkt_vps_late_init(void);
25 39
@@ -37,9 +51,12 @@ int omap2430_clk_init(void);
37 51
38extern void __iomem *prcm_clksrc_ctrl; 52extern void __iomem *prcm_clksrc_ctrl;
39 53
40extern const struct clkops clkops_omap2430_i2chs_wait; 54extern struct clk_hw *dclk_hw;
41extern const struct clkops clkops_oscck; 55int omap2_enable_osc_ck(struct clk_hw *hw);
42extern const struct clkops clkops_apll96; 56void omap2_disable_osc_ck(struct clk_hw *hw);
43extern const struct clkops clkops_apll54; 57int omap2_clk_apll96_enable(struct clk_hw *hw);
58int omap2_clk_apll54_enable(struct clk_hw *hw);
59void omap2_clk_apll96_disable(struct clk_hw *hw);
60void omap2_clk_apll54_disable(struct clk_hw *hw);
44 61
45#endif 62#endif
diff --git a/arch/arm/mach-omap2/clock33xx_data.c b/arch/arm/mach-omap2/clock33xx_data.c
deleted file mode 100644
index 17e3de51bcba..000000000000
--- a/arch/arm/mach-omap2/clock33xx_data.c
+++ /dev/null
@@ -1,1109 +0,0 @@
1/*
2 * AM33XX Clock data
3 *
4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
5 * Vaibhav Hiremath <hvaibhav@ti.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
10 *
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/kernel.h>
18#include <linux/list.h>
19#include <linux/clk.h>
20
21#include "soc.h"
22#include "iomap.h"
23#include "control.h"
24#include "clock.h"
25#include "cm.h"
26#include "cm33xx.h"
27#include "cm-regbits-33xx.h"
28#include "prm.h"
29
30/* Maximum DPLL multiplier, divider values for AM33XX */
31#define AM33XX_MAX_DPLL_MULT 2047
32#define AM33XX_MAX_DPLL_DIV 128
33
34/* Modulemode control */
35#define AM33XX_MODULEMODE_HWCTRL 0
36#define AM33XX_MODULEMODE_SWCTRL 1
37
38/* TRM ERRATA: Timer 3 & 6 default parent (TCLKIN) may not be always
39 * physically present, in such a case HWMOD enabling of
40 * clock would be failure with default parent. And timer
41 * probe thinks clock is already enabled, this leads to
42 * crash upon accessing timer 3 & 6 registers in probe.
43 * Fix by setting parent of both these timers to master
44 * oscillator clock.
45 */
46static inline void am33xx_init_timer_parent(struct clk *clk)
47{
48 omap2_clksel_set_parent(clk, clk->parent);
49}
50
51/* Root clocks */
52
53/* RTC 32k */
54static struct clk clk_32768_ck = {
55 .name = "clk_32768_ck",
56 .clkdm_name = "l4_rtc_clkdm",
57 .rate = 32768,
58 .ops = &clkops_null,
59};
60
61/* On-Chip 32KHz RC OSC */
62static struct clk clk_rc32k_ck = {
63 .name = "clk_rc32k_ck",
64 .rate = 32000,
65 .ops = &clkops_null,
66};
67
68/* Crystal input clks */
69static struct clk virt_24000000_ck = {
70 .name = "virt_24000000_ck",
71 .rate = 24000000,
72 .ops = &clkops_null,
73};
74
75static struct clk virt_25000000_ck = {
76 .name = "virt_25000000_ck",
77 .rate = 25000000,
78 .ops = &clkops_null,
79};
80
81/* Oscillator clock */
82/* 19.2, 24, 25 or 26 MHz */
83static const struct clksel sys_clkin_sel[] = {
84 { .parent = &virt_19200000_ck, .rates = div_1_0_rates },
85 { .parent = &virt_24000000_ck, .rates = div_1_1_rates },
86 { .parent = &virt_25000000_ck, .rates = div_1_2_rates },
87 { .parent = &virt_26000000_ck, .rates = div_1_3_rates },
88 { .parent = NULL },
89};
90
91/* External clock - 12 MHz */
92static struct clk tclkin_ck = {
93 .name = "tclkin_ck",
94 .rate = 12000000,
95 .ops = &clkops_null,
96};
97
98/*
99 * sys_clk in: input to the dpll and also used as funtional clock for,
100 * adc_tsc, smartreflex0-1, timer1-7, mcasp0-1, dcan0-1, cefuse
101 *
102 */
103static struct clk sys_clkin_ck = {
104 .name = "sys_clkin_ck",
105 .parent = &virt_24000000_ck,
106 .init = &omap2_init_clksel_parent,
107 .clksel_reg = AM33XX_CTRL_REGADDR(AM33XX_CONTROL_STATUS),
108 .clksel_mask = AM33XX_CONTROL_STATUS_SYSBOOT1_MASK,
109 .clksel = sys_clkin_sel,
110 .ops = &clkops_null,
111 .recalc = &omap2_clksel_recalc,
112};
113
114/* DPLL_CORE */
115static struct dpll_data dpll_core_dd = {
116 .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_CORE,
117 .clk_bypass = &sys_clkin_ck,
118 .clk_ref = &sys_clkin_ck,
119 .control_reg = AM33XX_CM_CLKMODE_DPLL_CORE,
120 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
121 .idlest_reg = AM33XX_CM_IDLEST_DPLL_CORE,
122 .mult_mask = AM33XX_DPLL_MULT_MASK,
123 .div1_mask = AM33XX_DPLL_DIV_MASK,
124 .enable_mask = AM33XX_DPLL_EN_MASK,
125 .idlest_mask = AM33XX_ST_DPLL_CLK_MASK,
126 .max_multiplier = AM33XX_MAX_DPLL_MULT,
127 .max_divider = AM33XX_MAX_DPLL_DIV,
128 .min_divider = 1,
129};
130
131/* CLKDCOLDO output */
132static struct clk dpll_core_ck = {
133 .name = "dpll_core_ck",
134 .parent = &sys_clkin_ck,
135 .dpll_data = &dpll_core_dd,
136 .init = &omap2_init_dpll_parent,
137 .ops = &clkops_omap3_core_dpll_ops,
138 .recalc = &omap3_dpll_recalc,
139};
140
141static struct clk dpll_core_x2_ck = {
142 .name = "dpll_core_x2_ck",
143 .parent = &dpll_core_ck,
144 .flags = CLOCK_CLKOUTX2,
145 .ops = &clkops_null,
146 .recalc = &omap3_clkoutx2_recalc,
147};
148
149
150static const struct clksel dpll_core_m4_div[] = {
151 { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
152 { .parent = NULL },
153};
154
155static struct clk dpll_core_m4_ck = {
156 .name = "dpll_core_m4_ck",
157 .parent = &dpll_core_x2_ck,
158 .init = &omap2_init_clksel_parent,
159 .clksel = dpll_core_m4_div,
160 .clksel_reg = AM33XX_CM_DIV_M4_DPLL_CORE,
161 .clksel_mask = AM33XX_HSDIVIDER_CLKOUT1_DIV_MASK,
162 .ops = &clkops_null,
163 .recalc = &omap2_clksel_recalc,
164 .round_rate = &omap2_clksel_round_rate,
165 .set_rate = &omap2_clksel_set_rate,
166};
167
168static const struct clksel dpll_core_m5_div[] = {
169 { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
170 { .parent = NULL },
171};
172
173static struct clk dpll_core_m5_ck = {
174 .name = "dpll_core_m5_ck",
175 .parent = &dpll_core_x2_ck,
176 .init = &omap2_init_clksel_parent,
177 .clksel = dpll_core_m5_div,
178 .clksel_reg = AM33XX_CM_DIV_M5_DPLL_CORE,
179 .clksel_mask = AM33XX_HSDIVIDER_CLKOUT2_DIV_MASK,
180 .ops = &clkops_null,
181 .recalc = &omap2_clksel_recalc,
182 .round_rate = &omap2_clksel_round_rate,
183 .set_rate = &omap2_clksel_set_rate,
184};
185
186static const struct clksel dpll_core_m6_div[] = {
187 { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
188 { .parent = NULL },
189};
190
191static struct clk dpll_core_m6_ck = {
192 .name = "dpll_core_m6_ck",
193 .parent = &dpll_core_x2_ck,
194 .init = &omap2_init_clksel_parent,
195 .clksel = dpll_core_m6_div,
196 .clksel_reg = AM33XX_CM_DIV_M6_DPLL_CORE,
197 .clksel_mask = AM33XX_HSDIVIDER_CLKOUT3_DIV_MASK,
198 .ops = &clkops_null,
199 .recalc = &omap2_clksel_recalc,
200 .round_rate = &omap2_clksel_round_rate,
201 .set_rate = &omap2_clksel_set_rate,
202};
203
204/* DPLL_MPU */
205static struct dpll_data dpll_mpu_dd = {
206 .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_MPU,
207 .clk_bypass = &sys_clkin_ck,
208 .clk_ref = &sys_clkin_ck,
209 .control_reg = AM33XX_CM_CLKMODE_DPLL_MPU,
210 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
211 .idlest_reg = AM33XX_CM_IDLEST_DPLL_MPU,
212 .mult_mask = AM33XX_DPLL_MULT_MASK,
213 .div1_mask = AM33XX_DPLL_DIV_MASK,
214 .enable_mask = AM33XX_DPLL_EN_MASK,
215 .idlest_mask = AM33XX_ST_DPLL_CLK_MASK,
216 .max_multiplier = AM33XX_MAX_DPLL_MULT,
217 .max_divider = AM33XX_MAX_DPLL_DIV,
218 .min_divider = 1,
219};
220
221/* CLKOUT: fdpll/M2 */
222static struct clk dpll_mpu_ck = {
223 .name = "dpll_mpu_ck",
224 .parent = &sys_clkin_ck,
225 .dpll_data = &dpll_mpu_dd,
226 .init = &omap2_init_dpll_parent,
227 .ops = &clkops_omap3_noncore_dpll_ops,
228 .recalc = &omap3_dpll_recalc,
229 .round_rate = &omap2_dpll_round_rate,
230 .set_rate = &omap3_noncore_dpll_set_rate,
231};
232
233/*
234 * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
235 * and ALT_CLK1/2)
236 */
237static const struct clksel dpll_mpu_m2_div[] = {
238 { .parent = &dpll_mpu_ck, .rates = div31_1to31_rates },
239 { .parent = NULL },
240};
241
242static struct clk dpll_mpu_m2_ck = {
243 .name = "dpll_mpu_m2_ck",
244 .clkdm_name = "mpu_clkdm",
245 .parent = &dpll_mpu_ck,
246 .clksel = dpll_mpu_m2_div,
247 .clksel_reg = AM33XX_CM_DIV_M2_DPLL_MPU,
248 .clksel_mask = AM33XX_DPLL_CLKOUT_DIV_MASK,
249 .ops = &clkops_null,
250 .recalc = &omap2_clksel_recalc,
251 .round_rate = &omap2_clksel_round_rate,
252 .set_rate = &omap2_clksel_set_rate,
253};
254
255/* DPLL_DDR */
256static struct dpll_data dpll_ddr_dd = {
257 .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_DDR,
258 .clk_bypass = &sys_clkin_ck,
259 .clk_ref = &sys_clkin_ck,
260 .control_reg = AM33XX_CM_CLKMODE_DPLL_DDR,
261 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
262 .idlest_reg = AM33XX_CM_IDLEST_DPLL_DDR,
263 .mult_mask = AM33XX_DPLL_MULT_MASK,
264 .div1_mask = AM33XX_DPLL_DIV_MASK,
265 .enable_mask = AM33XX_DPLL_EN_MASK,
266 .idlest_mask = AM33XX_ST_DPLL_CLK_MASK,
267 .max_multiplier = AM33XX_MAX_DPLL_MULT,
268 .max_divider = AM33XX_MAX_DPLL_DIV,
269 .min_divider = 1,
270};
271
272/* CLKOUT: fdpll/M2 */
273static struct clk dpll_ddr_ck = {
274 .name = "dpll_ddr_ck",
275 .parent = &sys_clkin_ck,
276 .dpll_data = &dpll_ddr_dd,
277 .init = &omap2_init_dpll_parent,
278 .ops = &clkops_null,
279 .recalc = &omap3_dpll_recalc,
280};
281
282/*
283 * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
284 * and ALT_CLK1/2)
285 */
286static const struct clksel dpll_ddr_m2_div[] = {
287 { .parent = &dpll_ddr_ck, .rates = div31_1to31_rates },
288 { .parent = NULL },
289};
290
291static struct clk dpll_ddr_m2_ck = {
292 .name = "dpll_ddr_m2_ck",
293 .parent = &dpll_ddr_ck,
294 .clksel = dpll_ddr_m2_div,
295 .clksel_reg = AM33XX_CM_DIV_M2_DPLL_DDR,
296 .clksel_mask = AM33XX_DPLL_CLKOUT_DIV_MASK,
297 .ops = &clkops_null,
298 .recalc = &omap2_clksel_recalc,
299 .round_rate = &omap2_clksel_round_rate,
300 .set_rate = &omap2_clksel_set_rate,
301};
302
303/* emif_fck functional clock */
304static struct clk dpll_ddr_m2_div2_ck = {
305 .name = "dpll_ddr_m2_div2_ck",
306 .clkdm_name = "l3_clkdm",
307 .parent = &dpll_ddr_m2_ck,
308 .ops = &clkops_null,
309 .fixed_div = 2,
310 .recalc = &omap_fixed_divisor_recalc,
311};
312
313/* DPLL_DISP */
314static struct dpll_data dpll_disp_dd = {
315 .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_DISP,
316 .clk_bypass = &sys_clkin_ck,
317 .clk_ref = &sys_clkin_ck,
318 .control_reg = AM33XX_CM_CLKMODE_DPLL_DISP,
319 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
320 .idlest_reg = AM33XX_CM_IDLEST_DPLL_DISP,
321 .mult_mask = AM33XX_DPLL_MULT_MASK,
322 .div1_mask = AM33XX_DPLL_DIV_MASK,
323 .enable_mask = AM33XX_DPLL_EN_MASK,
324 .idlest_mask = AM33XX_ST_DPLL_CLK_MASK,
325 .max_multiplier = AM33XX_MAX_DPLL_MULT,
326 .max_divider = AM33XX_MAX_DPLL_DIV,
327 .min_divider = 1,
328};
329
330/* CLKOUT: fdpll/M2 */
331static struct clk dpll_disp_ck = {
332 .name = "dpll_disp_ck",
333 .parent = &sys_clkin_ck,
334 .dpll_data = &dpll_disp_dd,
335 .init = &omap2_init_dpll_parent,
336 .ops = &clkops_null,
337 .recalc = &omap3_dpll_recalc,
338 .round_rate = &omap2_dpll_round_rate,
339 .set_rate = &omap3_noncore_dpll_set_rate,
340};
341
342/*
343 * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
344 * and ALT_CLK1/2)
345 */
346static const struct clksel dpll_disp_m2_div[] = {
347 { .parent = &dpll_disp_ck, .rates = div31_1to31_rates },
348 { .parent = NULL },
349};
350
351static struct clk dpll_disp_m2_ck = {
352 .name = "dpll_disp_m2_ck",
353 .parent = &dpll_disp_ck,
354 .clksel = dpll_disp_m2_div,
355 .clksel_reg = AM33XX_CM_DIV_M2_DPLL_DISP,
356 .clksel_mask = AM33XX_DPLL_CLKOUT_DIV_MASK,
357 .ops = &clkops_null,
358 .recalc = &omap2_clksel_recalc,
359 .round_rate = &omap2_clksel_round_rate,
360 .set_rate = &omap2_clksel_set_rate,
361};
362
363/* DPLL_PER */
364static struct dpll_data dpll_per_dd = {
365 .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_PERIPH,
366 .clk_bypass = &sys_clkin_ck,
367 .clk_ref = &sys_clkin_ck,
368 .control_reg = AM33XX_CM_CLKMODE_DPLL_PER,
369 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
370 .idlest_reg = AM33XX_CM_IDLEST_DPLL_PER,
371 .mult_mask = AM33XX_DPLL_MULT_PERIPH_MASK,
372 .div1_mask = AM33XX_DPLL_PER_DIV_MASK,
373 .enable_mask = AM33XX_DPLL_EN_MASK,
374 .idlest_mask = AM33XX_ST_DPLL_CLK_MASK,
375 .max_multiplier = AM33XX_MAX_DPLL_MULT,
376 .max_divider = AM33XX_MAX_DPLL_DIV,
377 .min_divider = 1,
378 .flags = DPLL_J_TYPE,
379};
380
381/* CLKDCOLDO */
382static struct clk dpll_per_ck = {
383 .name = "dpll_per_ck",
384 .parent = &sys_clkin_ck,
385 .dpll_data = &dpll_per_dd,
386 .init = &omap2_init_dpll_parent,
387 .ops = &clkops_null,
388 .recalc = &omap3_dpll_recalc,
389 .round_rate = &omap2_dpll_round_rate,
390 .set_rate = &omap3_noncore_dpll_set_rate,
391};
392
393/* CLKOUT: fdpll/M2 */
394static const struct clksel dpll_per_m2_div[] = {
395 { .parent = &dpll_per_ck, .rates = div31_1to31_rates },
396 { .parent = NULL },
397};
398
399static struct clk dpll_per_m2_ck = {
400 .name = "dpll_per_m2_ck",
401 .parent = &dpll_per_ck,
402 .clksel = dpll_per_m2_div,
403 .clksel_reg = AM33XX_CM_DIV_M2_DPLL_PER,
404 .clksel_mask = AM33XX_DPLL_CLKOUT_DIV_MASK,
405 .ops = &clkops_null,
406 .recalc = &omap2_clksel_recalc,
407 .round_rate = &omap2_clksel_round_rate,
408 .set_rate = &omap2_clksel_set_rate,
409};
410
411static struct clk dpll_per_m2_div4_wkupdm_ck = {
412 .name = "dpll_per_m2_div4_wkupdm_ck",
413 .clkdm_name = "l4_wkup_clkdm",
414 .parent = &dpll_per_m2_ck,
415 .fixed_div = 4,
416 .ops = &clkops_null,
417 .recalc = &omap_fixed_divisor_recalc,
418};
419
420static struct clk dpll_per_m2_div4_ck = {
421 .name = "dpll_per_m2_div4_ck",
422 .clkdm_name = "l4ls_clkdm",
423 .parent = &dpll_per_m2_ck,
424 .fixed_div = 4,
425 .ops = &clkops_null,
426 .recalc = &omap_fixed_divisor_recalc,
427};
428
429static struct clk l3_gclk = {
430 .name = "l3_gclk",
431 .clkdm_name = "l3_clkdm",
432 .parent = &dpll_core_m4_ck,
433 .ops = &clkops_null,
434 .recalc = &followparent_recalc,
435};
436
437static struct clk dpll_core_m4_div2_ck = {
438 .name = "dpll_core_m4_div2_ck",
439 .clkdm_name = "l4_wkup_clkdm",
440 .parent = &dpll_core_m4_ck,
441 .ops = &clkops_null,
442 .fixed_div = 2,
443 .recalc = &omap_fixed_divisor_recalc,
444};
445
446static struct clk l4_rtc_gclk = {
447 .name = "l4_rtc_gclk",
448 .parent = &dpll_core_m4_ck,
449 .ops = &clkops_null,
450 .fixed_div = 2,
451 .recalc = &omap_fixed_divisor_recalc,
452};
453
454static struct clk clk_24mhz = {
455 .name = "clk_24mhz",
456 .parent = &dpll_per_m2_ck,
457 .fixed_div = 8,
458 .ops = &clkops_null,
459 .recalc = &omap_fixed_divisor_recalc,
460};
461
462/*
463 * Below clock nodes describes clockdomains derived out
464 * of core clock.
465 */
466static struct clk l4hs_gclk = {
467 .name = "l4hs_gclk",
468 .clkdm_name = "l4hs_clkdm",
469 .parent = &dpll_core_m4_ck,
470 .ops = &clkops_null,
471 .recalc = &followparent_recalc,
472};
473
474static struct clk l3s_gclk = {
475 .name = "l3s_gclk",
476 .clkdm_name = "l3s_clkdm",
477 .parent = &dpll_core_m4_div2_ck,
478 .ops = &clkops_null,
479 .recalc = &followparent_recalc,
480};
481
482static struct clk l4fw_gclk = {
483 .name = "l4fw_gclk",
484 .clkdm_name = "l4fw_clkdm",
485 .parent = &dpll_core_m4_div2_ck,
486 .ops = &clkops_null,
487 .recalc = &followparent_recalc,
488};
489
490static struct clk l4ls_gclk = {
491 .name = "l4ls_gclk",
492 .clkdm_name = "l4ls_clkdm",
493 .parent = &dpll_core_m4_div2_ck,
494 .ops = &clkops_null,
495 .recalc = &followparent_recalc,
496};
497
498static struct clk sysclk_div_ck = {
499 .name = "sysclk_div_ck",
500 .parent = &dpll_core_m4_ck,
501 .ops = &clkops_null,
502 .recalc = &followparent_recalc,
503};
504
505/*
506 * In order to match the clock domain with hwmod clockdomain entry,
507 * separate clock nodes is required for the modules which are
508 * directly getting their funtioncal clock from sys_clkin.
509 */
510static struct clk adc_tsc_fck = {
511 .name = "adc_tsc_fck",
512 .clkdm_name = "l4_wkup_clkdm",
513 .parent = &sys_clkin_ck,
514 .ops = &clkops_null,
515 .recalc = &followparent_recalc,
516};
517
518static struct clk dcan0_fck = {
519 .name = "dcan0_fck",
520 .clkdm_name = "l4ls_clkdm",
521 .parent = &sys_clkin_ck,
522 .ops = &clkops_null,
523 .recalc = &followparent_recalc,
524};
525
526static struct clk dcan1_fck = {
527 .name = "dcan1_fck",
528 .clkdm_name = "l4ls_clkdm",
529 .parent = &sys_clkin_ck,
530 .ops = &clkops_null,
531 .recalc = &followparent_recalc,
532};
533
534static struct clk mcasp0_fck = {
535 .name = "mcasp0_fck",
536 .clkdm_name = "l3s_clkdm",
537 .parent = &sys_clkin_ck,
538 .ops = &clkops_null,
539 .recalc = &followparent_recalc,
540};
541
542static struct clk mcasp1_fck = {
543 .name = "mcasp1_fck",
544 .clkdm_name = "l3s_clkdm",
545 .parent = &sys_clkin_ck,
546 .ops = &clkops_null,
547 .recalc = &followparent_recalc,
548};
549
550static struct clk smartreflex0_fck = {
551 .name = "smartreflex0_fck",
552 .clkdm_name = "l4_wkup_clkdm",
553 .parent = &sys_clkin_ck,
554 .ops = &clkops_null,
555 .recalc = &followparent_recalc,
556};
557
558static struct clk smartreflex1_fck = {
559 .name = "smartreflex1_fck",
560 .clkdm_name = "l4_wkup_clkdm",
561 .parent = &sys_clkin_ck,
562 .ops = &clkops_null,
563 .recalc = &followparent_recalc,
564};
565
566/*
567 * Modules clock nodes
568 *
569 * The following clock leaf nodes are added for the moment because:
570 *
571 * - hwmod data is not present for these modules, either hwmod
572 * control is not required or its not populated.
573 * - Driver code is not yet migrated to use hwmod/runtime pm
574 * - Modules outside kernel access (to disable them by default)
575 *
576 * - debugss
577 * - mmu (gfx domain)
578 * - cefuse
579 * - usbotg_fck (its additional clock and not really a modulemode)
580 * - ieee5000
581 */
582static struct clk debugss_ick = {
583 .name = "debugss_ick",
584 .clkdm_name = "l3_aon_clkdm",
585 .parent = &dpll_core_m4_ck,
586 .ops = &clkops_omap2_dflt,
587 .enable_reg = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
588 .enable_bit = AM33XX_MODULEMODE_SWCTRL,
589 .recalc = &followparent_recalc,
590};
591
592static struct clk mmu_fck = {
593 .name = "mmu_fck",
594 .clkdm_name = "gfx_l3_clkdm",
595 .parent = &dpll_core_m4_ck,
596 .ops = &clkops_omap2_dflt,
597 .enable_reg = AM33XX_CM_GFX_MMUDATA_CLKCTRL,
598 .enable_bit = AM33XX_MODULEMODE_SWCTRL,
599 .recalc = &followparent_recalc,
600};
601
602static struct clk cefuse_fck = {
603 .name = "cefuse_fck",
604 .clkdm_name = "l4_cefuse_clkdm",
605 .parent = &sys_clkin_ck,
606 .enable_reg = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL,
607 .enable_bit = AM33XX_MODULEMODE_SWCTRL,
608 .ops = &clkops_omap2_dflt,
609 .recalc = &followparent_recalc,
610};
611
612/*
613 * clkdiv32 is generated from fixed division of 732.4219
614 */
615static struct clk clkdiv32k_ick = {
616 .name = "clkdiv32k_ick",
617 .clkdm_name = "clk_24mhz_clkdm",
618 .rate = 32768,
619 .parent = &clk_24mhz,
620 .enable_reg = AM33XX_CM_PER_CLKDIV32K_CLKCTRL,
621 .enable_bit = AM33XX_MODULEMODE_SWCTRL,
622 .ops = &clkops_omap2_dflt,
623};
624
625static struct clk usbotg_fck = {
626 .name = "usbotg_fck",
627 .clkdm_name = "l3s_clkdm",
628 .parent = &dpll_per_ck,
629 .enable_reg = AM33XX_CM_CLKDCOLDO_DPLL_PER,
630 .enable_bit = AM33XX_ST_DPLL_CLKDCOLDO_SHIFT,
631 .ops = &clkops_omap2_dflt,
632 .recalc = &followparent_recalc,
633};
634
635static struct clk ieee5000_fck = {
636 .name = "ieee5000_fck",
637 .clkdm_name = "l3s_clkdm",
638 .parent = &dpll_core_m4_div2_ck,
639 .enable_reg = AM33XX_CM_PER_IEEE5000_CLKCTRL,
640 .enable_bit = AM33XX_MODULEMODE_SWCTRL,
641 .ops = &clkops_omap2_dflt,
642 .recalc = &followparent_recalc,
643};
644
645/* Timers */
646static const struct clksel timer1_clkmux_sel[] = {
647 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
648 { .parent = &clkdiv32k_ick, .rates = div_1_1_rates },
649 { .parent = &tclkin_ck, .rates = div_1_2_rates },
650 { .parent = &clk_rc32k_ck, .rates = div_1_3_rates },
651 { .parent = &clk_32768_ck, .rates = div_1_4_rates },
652 { .parent = NULL },
653};
654
655static struct clk timer1_fck = {
656 .name = "timer1_fck",
657 .clkdm_name = "l4ls_clkdm",
658 .parent = &sys_clkin_ck,
659 .init = &omap2_init_clksel_parent,
660 .clksel = timer1_clkmux_sel,
661 .clksel_reg = AM33XX_CLKSEL_TIMER1MS_CLK,
662 .clksel_mask = AM33XX_CLKSEL_0_2_MASK,
663 .ops = &clkops_null,
664 .recalc = &omap2_clksel_recalc,
665};
666
667static const struct clksel timer2_to_7_clk_sel[] = {
668 { .parent = &tclkin_ck, .rates = div_1_0_rates },
669 { .parent = &sys_clkin_ck, .rates = div_1_1_rates },
670 { .parent = &clkdiv32k_ick, .rates = div_1_2_rates },
671 { .parent = NULL },
672};
673
674static struct clk timer2_fck = {
675 .name = "timer2_fck",
676 .clkdm_name = "l4ls_clkdm",
677 .parent = &sys_clkin_ck,
678 .init = &omap2_init_clksel_parent,
679 .clksel = timer2_to_7_clk_sel,
680 .clksel_reg = AM33XX_CLKSEL_TIMER2_CLK,
681 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
682 .ops = &clkops_null,
683 .recalc = &omap2_clksel_recalc,
684};
685
686static struct clk timer3_fck = {
687 .name = "timer3_fck",
688 .clkdm_name = "l4ls_clkdm",
689 .parent = &sys_clkin_ck,
690 .init = &am33xx_init_timer_parent,
691 .clksel = timer2_to_7_clk_sel,
692 .clksel_reg = AM33XX_CLKSEL_TIMER3_CLK,
693 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
694 .ops = &clkops_null,
695 .recalc = &omap2_clksel_recalc,
696};
697
698static struct clk timer4_fck = {
699 .name = "timer4_fck",
700 .clkdm_name = "l4ls_clkdm",
701 .parent = &sys_clkin_ck,
702 .init = &omap2_init_clksel_parent,
703 .clksel = timer2_to_7_clk_sel,
704 .clksel_reg = AM33XX_CLKSEL_TIMER4_CLK,
705 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
706 .ops = &clkops_null,
707 .recalc = &omap2_clksel_recalc,
708};
709
710static struct clk timer5_fck = {
711 .name = "timer5_fck",
712 .clkdm_name = "l4ls_clkdm",
713 .parent = &sys_clkin_ck,
714 .init = &omap2_init_clksel_parent,
715 .clksel = timer2_to_7_clk_sel,
716 .clksel_reg = AM33XX_CLKSEL_TIMER5_CLK,
717 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
718 .ops = &clkops_null,
719 .recalc = &omap2_clksel_recalc,
720};
721
722static struct clk timer6_fck = {
723 .name = "timer6_fck",
724 .clkdm_name = "l4ls_clkdm",
725 .parent = &sys_clkin_ck,
726 .init = &am33xx_init_timer_parent,
727 .clksel = timer2_to_7_clk_sel,
728 .clksel_reg = AM33XX_CLKSEL_TIMER6_CLK,
729 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
730 .ops = &clkops_null,
731 .recalc = &omap2_clksel_recalc,
732};
733
734static struct clk timer7_fck = {
735 .name = "timer7_fck",
736 .clkdm_name = "l4ls_clkdm",
737 .parent = &sys_clkin_ck,
738 .init = &omap2_init_clksel_parent,
739 .clksel = timer2_to_7_clk_sel,
740 .clksel_reg = AM33XX_CLKSEL_TIMER7_CLK,
741 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
742 .ops = &clkops_null,
743 .recalc = &omap2_clksel_recalc,
744};
745
746static struct clk cpsw_125mhz_gclk = {
747 .name = "cpsw_125mhz_gclk",
748 .clkdm_name = "cpsw_125mhz_clkdm",
749 .parent = &dpll_core_m5_ck,
750 .ops = &clkops_null,
751 .fixed_div = 2,
752 .recalc = &omap_fixed_divisor_recalc,
753};
754
755static const struct clksel cpsw_cpts_rft_clkmux_sel[] = {
756 { .parent = &dpll_core_m5_ck, .rates = div_1_0_rates },
757 { .parent = &dpll_core_m4_ck, .rates = div_1_1_rates },
758 { .parent = NULL },
759};
760
761static struct clk cpsw_cpts_rft_clk = {
762 .name = "cpsw_cpts_rft_clk",
763 .clkdm_name = "cpsw_125mhz_clkdm",
764 .parent = &dpll_core_m5_ck,
765 .clksel = cpsw_cpts_rft_clkmux_sel,
766 .clksel_reg = AM33XX_CM_CPTS_RFT_CLKSEL,
767 .clksel_mask = AM33XX_CLKSEL_0_0_MASK,
768 .ops = &clkops_null,
769 .recalc = &followparent_recalc,
770};
771
772/* gpio */
773static const struct clksel gpio0_dbclk_mux_sel[] = {
774 { .parent = &clk_rc32k_ck, .rates = div_1_0_rates },
775 { .parent = &clk_32768_ck, .rates = div_1_1_rates },
776 { .parent = &clkdiv32k_ick, .rates = div_1_2_rates },
777 { .parent = NULL },
778};
779
780static struct clk gpio0_dbclk_mux_ck = {
781 .name = "gpio0_dbclk_mux_ck",
782 .clkdm_name = "l4_wkup_clkdm",
783 .parent = &clk_rc32k_ck,
784 .init = &omap2_init_clksel_parent,
785 .clksel = gpio0_dbclk_mux_sel,
786 .clksel_reg = AM33XX_CLKSEL_GPIO0_DBCLK,
787 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
788 .ops = &clkops_null,
789 .recalc = &omap2_clksel_recalc,
790};
791
792static struct clk gpio0_dbclk = {
793 .name = "gpio0_dbclk",
794 .clkdm_name = "l4_wkup_clkdm",
795 .parent = &gpio0_dbclk_mux_ck,
796 .enable_reg = AM33XX_CM_WKUP_GPIO0_CLKCTRL,
797 .enable_bit = AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT,
798 .ops = &clkops_omap2_dflt,
799 .recalc = &followparent_recalc,
800};
801
802static struct clk gpio1_dbclk = {
803 .name = "gpio1_dbclk",
804 .clkdm_name = "l4ls_clkdm",
805 .parent = &clkdiv32k_ick,
806 .enable_reg = AM33XX_CM_PER_GPIO1_CLKCTRL,
807 .enable_bit = AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT,
808 .ops = &clkops_omap2_dflt,
809 .recalc = &followparent_recalc,
810};
811
812static struct clk gpio2_dbclk = {
813 .name = "gpio2_dbclk",
814 .clkdm_name = "l4ls_clkdm",
815 .parent = &clkdiv32k_ick,
816 .enable_reg = AM33XX_CM_PER_GPIO2_CLKCTRL,
817 .enable_bit = AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT,
818 .ops = &clkops_omap2_dflt,
819 .recalc = &followparent_recalc,
820};
821
822static struct clk gpio3_dbclk = {
823 .name = "gpio3_dbclk",
824 .clkdm_name = "l4ls_clkdm",
825 .parent = &clkdiv32k_ick,
826 .enable_reg = AM33XX_CM_PER_GPIO3_CLKCTRL,
827 .enable_bit = AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT,
828 .ops = &clkops_omap2_dflt,
829 .recalc = &followparent_recalc,
830};
831
832static const struct clksel pruss_ocp_clk_mux_sel[] = {
833 { .parent = &l3_gclk, .rates = div_1_0_rates },
834 { .parent = &dpll_disp_m2_ck, .rates = div_1_1_rates },
835 { .parent = NULL },
836};
837
838static struct clk pruss_ocp_gclk = {
839 .name = "pruss_ocp_gclk",
840 .clkdm_name = "pruss_ocp_clkdm",
841 .parent = &l3_gclk,
842 .init = &omap2_init_clksel_parent,
843 .clksel = pruss_ocp_clk_mux_sel,
844 .clksel_reg = AM33XX_CLKSEL_PRUSS_OCP_CLK,
845 .clksel_mask = AM33XX_CLKSEL_0_0_MASK,
846 .ops = &clkops_null,
847 .recalc = &followparent_recalc,
848};
849
850static const struct clksel lcd_clk_mux_sel[] = {
851 { .parent = &dpll_disp_m2_ck, .rates = div_1_0_rates },
852 { .parent = &dpll_core_m5_ck, .rates = div_1_1_rates },
853 { .parent = &dpll_per_m2_ck, .rates = div_1_2_rates },
854 { .parent = NULL },
855};
856
857static struct clk lcd_gclk = {
858 .name = "lcd_gclk",
859 .clkdm_name = "lcdc_clkdm",
860 .parent = &dpll_disp_m2_ck,
861 .init = &omap2_init_clksel_parent,
862 .clksel = lcd_clk_mux_sel,
863 .clksel_reg = AM33XX_CLKSEL_LCDC_PIXEL_CLK,
864 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
865 .ops = &clkops_null,
866 .recalc = &followparent_recalc,
867};
868
869static struct clk mmc_clk = {
870 .name = "mmc_clk",
871 .clkdm_name = "l4ls_clkdm",
872 .parent = &dpll_per_m2_ck,
873 .ops = &clkops_null,
874 .fixed_div = 2,
875 .recalc = &omap_fixed_divisor_recalc,
876};
877
878static struct clk mmc2_fck = {
879 .name = "mmc2_fck",
880 .clkdm_name = "l3s_clkdm",
881 .parent = &mmc_clk,
882 .ops = &clkops_null,
883 .recalc = &followparent_recalc,
884};
885
886static const struct clksel gfx_clksel_sel[] = {
887 { .parent = &dpll_core_m4_ck, .rates = div_1_0_rates },
888 { .parent = &dpll_per_m2_ck, .rates = div_1_1_rates },
889 { .parent = NULL },
890};
891
892static struct clk gfx_fclk_clksel_ck = {
893 .name = "gfx_fclk_clksel_ck",
894 .parent = &dpll_core_m4_ck,
895 .clksel = gfx_clksel_sel,
896 .ops = &clkops_null,
897 .clksel_reg = AM33XX_CLKSEL_GFX_FCLK,
898 .clksel_mask = AM33XX_CLKSEL_GFX_FCLK_MASK,
899 .recalc = &omap2_clksel_recalc,
900};
901
902static const struct clksel_rate div_1_0_2_1_rates[] = {
903 { .div = 1, .val = 0, .flags = RATE_IN_AM33XX },
904 { .div = 2, .val = 1, .flags = RATE_IN_AM33XX },
905 { .div = 0 },
906};
907
908static const struct clksel gfx_div_sel[] = {
909 { .parent = &gfx_fclk_clksel_ck, .rates = div_1_0_2_1_rates },
910 { .parent = NULL },
911};
912
913static struct clk gfx_fck_div_ck = {
914 .name = "gfx_fck_div_ck",
915 .clkdm_name = "gfx_l3_clkdm",
916 .parent = &gfx_fclk_clksel_ck,
917 .init = &omap2_init_clksel_parent,
918 .clksel = gfx_div_sel,
919 .clksel_reg = AM33XX_CLKSEL_GFX_FCLK,
920 .clksel_mask = AM33XX_CLKSEL_0_0_MASK,
921 .recalc = &omap2_clksel_recalc,
922 .round_rate = &omap2_clksel_round_rate,
923 .set_rate = &omap2_clksel_set_rate,
924 .ops = &clkops_null,
925};
926
927static const struct clksel sysclkout_pre_sel[] = {
928 { .parent = &clk_32768_ck, .rates = div_1_0_rates },
929 { .parent = &l3_gclk, .rates = div_1_1_rates },
930 { .parent = &dpll_ddr_m2_ck, .rates = div_1_2_rates },
931 { .parent = &dpll_per_m2_ck, .rates = div_1_3_rates },
932 { .parent = &lcd_gclk, .rates = div_1_4_rates },
933 { .parent = NULL },
934};
935
936static struct clk sysclkout_pre_ck = {
937 .name = "sysclkout_pre_ck",
938 .parent = &clk_32768_ck,
939 .init = &omap2_init_clksel_parent,
940 .clksel = sysclkout_pre_sel,
941 .clksel_reg = AM33XX_CM_CLKOUT_CTRL,
942 .clksel_mask = AM33XX_CLKOUT2SOURCE_MASK,
943 .ops = &clkops_null,
944 .recalc = &omap2_clksel_recalc,
945};
946
947/* Divide by 8 clock rates with default clock is 1/1*/
948static const struct clksel_rate div8_rates[] = {
949 { .div = 1, .val = 0, .flags = RATE_IN_AM33XX },
950 { .div = 2, .val = 1, .flags = RATE_IN_AM33XX },
951 { .div = 3, .val = 2, .flags = RATE_IN_AM33XX },
952 { .div = 4, .val = 3, .flags = RATE_IN_AM33XX },
953 { .div = 5, .val = 4, .flags = RATE_IN_AM33XX },
954 { .div = 6, .val = 5, .flags = RATE_IN_AM33XX },
955 { .div = 7, .val = 6, .flags = RATE_IN_AM33XX },
956 { .div = 8, .val = 7, .flags = RATE_IN_AM33XX },
957 { .div = 0 },
958};
959
960static const struct clksel clkout2_div[] = {
961 { .parent = &sysclkout_pre_ck, .rates = div8_rates },
962 { .parent = NULL },
963};
964
965static struct clk clkout2_ck = {
966 .name = "clkout2_ck",
967 .parent = &sysclkout_pre_ck,
968 .ops = &clkops_omap2_dflt,
969 .clksel = clkout2_div,
970 .clksel_reg = AM33XX_CM_CLKOUT_CTRL,
971 .clksel_mask = AM33XX_CLKOUT2DIV_MASK,
972 .enable_reg = AM33XX_CM_CLKOUT_CTRL,
973 .enable_bit = AM33XX_CLKOUT2EN_SHIFT,
974 .recalc = &omap2_clksel_recalc,
975 .round_rate = &omap2_clksel_round_rate,
976 .set_rate = &omap2_clksel_set_rate,
977};
978
979static const struct clksel wdt_clkmux_sel[] = {
980 { .parent = &clk_rc32k_ck, .rates = div_1_0_rates },
981 { .parent = &clkdiv32k_ick, .rates = div_1_1_rates },
982 { .parent = NULL },
983};
984
985static struct clk wdt1_fck = {
986 .name = "wdt1_fck",
987 .clkdm_name = "l4_wkup_clkdm",
988 .parent = &clk_rc32k_ck,
989 .init = &omap2_init_clksel_parent,
990 .clksel = wdt_clkmux_sel,
991 .clksel_reg = AM33XX_CLKSEL_WDT1_CLK,
992 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
993 .ops = &clkops_null,
994 .recalc = &omap2_clksel_recalc,
995};
996
997/*
998 * clkdev
999 */
1000static struct omap_clk am33xx_clks[] = {
1001 CLK(NULL, "clk_32768_ck", &clk_32768_ck, CK_AM33XX),
1002 CLK(NULL, "clk_rc32k_ck", &clk_rc32k_ck, CK_AM33XX),
1003 CLK(NULL, "virt_19200000_ck", &virt_19200000_ck, CK_AM33XX),
1004 CLK(NULL, "virt_24000000_ck", &virt_24000000_ck, CK_AM33XX),
1005 CLK(NULL, "virt_25000000_ck", &virt_25000000_ck, CK_AM33XX),
1006 CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_AM33XX),
1007 CLK(NULL, "sys_clkin_ck", &sys_clkin_ck, CK_AM33XX),
1008 CLK(NULL, "tclkin_ck", &tclkin_ck, CK_AM33XX),
1009 CLK(NULL, "dpll_core_ck", &dpll_core_ck, CK_AM33XX),
1010 CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck, CK_AM33XX),
1011 CLK(NULL, "dpll_core_m4_ck", &dpll_core_m4_ck, CK_AM33XX),
1012 CLK(NULL, "dpll_core_m5_ck", &dpll_core_m5_ck, CK_AM33XX),
1013 CLK(NULL, "dpll_core_m6_ck", &dpll_core_m6_ck, CK_AM33XX),
1014 CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_AM33XX),
1015 CLK("cpu0", NULL, &dpll_mpu_ck, CK_AM33XX),
1016 CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_AM33XX),
1017 CLK(NULL, "dpll_ddr_ck", &dpll_ddr_ck, CK_AM33XX),
1018 CLK(NULL, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck, CK_AM33XX),
1019 CLK(NULL, "dpll_ddr_m2_div2_ck", &dpll_ddr_m2_div2_ck, CK_AM33XX),
1020 CLK(NULL, "dpll_disp_ck", &dpll_disp_ck, CK_AM33XX),
1021 CLK(NULL, "dpll_disp_m2_ck", &dpll_disp_m2_ck, CK_AM33XX),
1022 CLK(NULL, "dpll_per_ck", &dpll_per_ck, CK_AM33XX),
1023 CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck, CK_AM33XX),
1024 CLK(NULL, "dpll_per_m2_div4_wkupdm_ck", &dpll_per_m2_div4_wkupdm_ck, CK_AM33XX),
1025 CLK(NULL, "dpll_per_m2_div4_ck", &dpll_per_m2_div4_ck, CK_AM33XX),
1026 CLK(NULL, "adc_tsc_fck", &adc_tsc_fck, CK_AM33XX),
1027 CLK(NULL, "cefuse_fck", &cefuse_fck, CK_AM33XX),
1028 CLK(NULL, "clkdiv32k_ick", &clkdiv32k_ick, CK_AM33XX),
1029 CLK(NULL, "dcan0_fck", &dcan0_fck, CK_AM33XX),
1030 CLK("481cc000.d_can", NULL, &dcan0_fck, CK_AM33XX),
1031 CLK(NULL, "dcan1_fck", &dcan1_fck, CK_AM33XX),
1032 CLK("481d0000.d_can", NULL, &dcan1_fck, CK_AM33XX),
1033 CLK(NULL, "debugss_ick", &debugss_ick, CK_AM33XX),
1034 CLK(NULL, "pruss_ocp_gclk", &pruss_ocp_gclk, CK_AM33XX),
1035 CLK("davinci-mcasp.0", NULL, &mcasp0_fck, CK_AM33XX),
1036 CLK("davinci-mcasp.1", NULL, &mcasp1_fck, CK_AM33XX),
1037 CLK(NULL, "mcasp0_fck", &mcasp0_fck, CK_AM33XX),
1038 CLK(NULL, "mcasp1_fck", &mcasp1_fck, CK_AM33XX),
1039 CLK("NULL", "mmc2_fck", &mmc2_fck, CK_AM33XX),
1040 CLK(NULL, "mmu_fck", &mmu_fck, CK_AM33XX),
1041 CLK(NULL, "smartreflex0_fck", &smartreflex0_fck, CK_AM33XX),
1042 CLK(NULL, "smartreflex1_fck", &smartreflex1_fck, CK_AM33XX),
1043 CLK(NULL, "timer1_fck", &timer1_fck, CK_AM33XX),
1044 CLK(NULL, "timer2_fck", &timer2_fck, CK_AM33XX),
1045 CLK(NULL, "timer3_fck", &timer3_fck, CK_AM33XX),
1046 CLK(NULL, "timer4_fck", &timer4_fck, CK_AM33XX),
1047 CLK(NULL, "timer5_fck", &timer5_fck, CK_AM33XX),
1048 CLK(NULL, "timer6_fck", &timer6_fck, CK_AM33XX),
1049 CLK(NULL, "timer7_fck", &timer7_fck, CK_AM33XX),
1050 CLK(NULL, "usbotg_fck", &usbotg_fck, CK_AM33XX),
1051 CLK(NULL, "ieee5000_fck", &ieee5000_fck, CK_AM33XX),
1052 CLK(NULL, "wdt1_fck", &wdt1_fck, CK_AM33XX),
1053 CLK(NULL, "l4_rtc_gclk", &l4_rtc_gclk, CK_AM33XX),
1054 CLK(NULL, "l3_gclk", &l3_gclk, CK_AM33XX),
1055 CLK(NULL, "dpll_core_m4_div2_ck", &dpll_core_m4_div2_ck, CK_AM33XX),
1056 CLK(NULL, "l4hs_gclk", &l4hs_gclk, CK_AM33XX),
1057 CLK(NULL, "l3s_gclk", &l3s_gclk, CK_AM33XX),
1058 CLK(NULL, "l4fw_gclk", &l4fw_gclk, CK_AM33XX),
1059 CLK(NULL, "l4ls_gclk", &l4ls_gclk, CK_AM33XX),
1060 CLK(NULL, "clk_24mhz", &clk_24mhz, CK_AM33XX),
1061 CLK(NULL, "sysclk_div_ck", &sysclk_div_ck, CK_AM33XX),
1062 CLK(NULL, "cpsw_125mhz_gclk", &cpsw_125mhz_gclk, CK_AM33XX),
1063 CLK(NULL, "cpsw_cpts_rft_clk", &cpsw_cpts_rft_clk, CK_AM33XX),
1064 CLK(NULL, "gpio0_dbclk_mux_ck", &gpio0_dbclk_mux_ck, CK_AM33XX),
1065 CLK(NULL, "gpio0_dbclk", &gpio0_dbclk, CK_AM33XX),
1066 CLK(NULL, "gpio1_dbclk", &gpio1_dbclk, CK_AM33XX),
1067 CLK(NULL, "gpio2_dbclk", &gpio2_dbclk, CK_AM33XX),
1068 CLK(NULL, "gpio3_dbclk", &gpio3_dbclk, CK_AM33XX),
1069 CLK(NULL, "lcd_gclk", &lcd_gclk, CK_AM33XX),
1070 CLK(NULL, "mmc_clk", &mmc_clk, CK_AM33XX),
1071 CLK(NULL, "gfx_fclk_clksel_ck", &gfx_fclk_clksel_ck, CK_AM33XX),
1072 CLK(NULL, "gfx_fck_div_ck", &gfx_fck_div_ck, CK_AM33XX),
1073 CLK(NULL, "sysclkout_pre_ck", &sysclkout_pre_ck, CK_AM33XX),
1074 CLK(NULL, "clkout2_ck", &clkout2_ck, CK_AM33XX),
1075 CLK(NULL, "timer_32k_ck", &clkdiv32k_ick, CK_AM33XX),
1076 CLK(NULL, "timer_sys_ck", &sys_clkin_ck, CK_AM33XX),
1077};
1078
1079int __init am33xx_clk_init(void)
1080{
1081 struct omap_clk *c;
1082 u32 cpu_clkflg;
1083
1084 if (soc_is_am33xx()) {
1085 cpu_mask = RATE_IN_AM33XX;
1086 cpu_clkflg = CK_AM33XX;
1087 }
1088
1089 for (c = am33xx_clks; c < am33xx_clks + ARRAY_SIZE(am33xx_clks); c++)
1090 clk_preinit(c->lk.clk);
1091
1092 for (c = am33xx_clks; c < am33xx_clks + ARRAY_SIZE(am33xx_clks); c++) {
1093 if (c->cpu & cpu_clkflg) {
1094 clkdev_add(&c->lk);
1095 clk_register(c->lk.clk);
1096 omap2_init_clk_clkdm(c->lk.clk);
1097 }
1098 }
1099
1100 recalculate_root_clocks();
1101
1102 /*
1103 * Only enable those clocks we will need, let the drivers
1104 * enable other clocks as necessary
1105 */
1106 clk_enable_init_clocks();
1107
1108 return 0;
1109}
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index e41819ba7482..4596468e50ab 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -37,7 +37,7 @@
37 * from the CM_{I,F}CLKEN bit. Pass back the correct info via 37 * from the CM_{I,F}CLKEN bit. Pass back the correct info via
38 * @idlest_reg and @idlest_bit. No return value. 38 * @idlest_reg and @idlest_bit. No return value.
39 */ 39 */
40static void omap3430es2_clk_ssi_find_idlest(struct clk *clk, 40static void omap3430es2_clk_ssi_find_idlest(struct clk_hw_omap *clk,
41 void __iomem **idlest_reg, 41 void __iomem **idlest_reg,
42 u8 *idlest_bit, 42 u8 *idlest_bit,
43 u8 *idlest_val) 43 u8 *idlest_val)
@@ -49,21 +49,16 @@ static void omap3430es2_clk_ssi_find_idlest(struct clk *clk,
49 *idlest_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT; 49 *idlest_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT;
50 *idlest_val = OMAP34XX_CM_IDLEST_VAL; 50 *idlest_val = OMAP34XX_CM_IDLEST_VAL;
51} 51}
52 52const struct clk_hw_omap_ops clkhwops_omap3430es2_ssi_wait = {
53const struct clkops clkops_omap3430es2_ssi_wait = {
54 .enable = omap2_dflt_clk_enable,
55 .disable = omap2_dflt_clk_disable,
56 .find_idlest = omap3430es2_clk_ssi_find_idlest, 53 .find_idlest = omap3430es2_clk_ssi_find_idlest,
57 .find_companion = omap2_clk_dflt_find_companion, 54 .find_companion = omap2_clk_dflt_find_companion,
58}; 55};
59 56
60const struct clkops clkops_omap3430es2_iclk_ssi_wait = { 57const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait = {
61 .enable = omap2_dflt_clk_enable,
62 .disable = omap2_dflt_clk_disable,
63 .find_idlest = omap3430es2_clk_ssi_find_idlest,
64 .find_companion = omap2_clk_dflt_find_companion,
65 .allow_idle = omap2_clkt_iclk_allow_idle, 58 .allow_idle = omap2_clkt_iclk_allow_idle,
66 .deny_idle = omap2_clkt_iclk_deny_idle, 59 .deny_idle = omap2_clkt_iclk_deny_idle,
60 .find_idlest = omap3430es2_clk_ssi_find_idlest,
61 .find_companion = omap2_clk_dflt_find_companion,
67}; 62};
68 63
69/** 64/**
@@ -80,7 +75,7 @@ const struct clkops clkops_omap3430es2_iclk_ssi_wait = {
80 * default find_idlest code assumes that they are at the same 75 * default find_idlest code assumes that they are at the same
81 * position.) No return value. 76 * position.) No return value.
82 */ 77 */
83static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk *clk, 78static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk_hw_omap *clk,
84 void __iomem **idlest_reg, 79 void __iomem **idlest_reg,
85 u8 *idlest_bit, 80 u8 *idlest_bit,
86 u8 *idlest_val) 81 u8 *idlest_val)
@@ -94,20 +89,16 @@ static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk *clk,
94 *idlest_val = OMAP34XX_CM_IDLEST_VAL; 89 *idlest_val = OMAP34XX_CM_IDLEST_VAL;
95} 90}
96 91
97const struct clkops clkops_omap3430es2_dss_usbhost_wait = { 92const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait = {
98 .enable = omap2_dflt_clk_enable,
99 .disable = omap2_dflt_clk_disable,
100 .find_idlest = omap3430es2_clk_dss_usbhost_find_idlest, 93 .find_idlest = omap3430es2_clk_dss_usbhost_find_idlest,
101 .find_companion = omap2_clk_dflt_find_companion, 94 .find_companion = omap2_clk_dflt_find_companion,
102}; 95};
103 96
104const struct clkops clkops_omap3430es2_iclk_dss_usbhost_wait = { 97const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait = {
105 .enable = omap2_dflt_clk_enable,
106 .disable = omap2_dflt_clk_disable,
107 .find_idlest = omap3430es2_clk_dss_usbhost_find_idlest,
108 .find_companion = omap2_clk_dflt_find_companion,
109 .allow_idle = omap2_clkt_iclk_allow_idle, 98 .allow_idle = omap2_clkt_iclk_allow_idle,
110 .deny_idle = omap2_clkt_iclk_deny_idle, 99 .deny_idle = omap2_clkt_iclk_deny_idle,
100 .find_idlest = omap3430es2_clk_dss_usbhost_find_idlest,
101 .find_companion = omap2_clk_dflt_find_companion,
111}; 102};
112 103
113/** 104/**
@@ -121,7 +112,7 @@ const struct clkops clkops_omap3430es2_iclk_dss_usbhost_wait = {
121 * shift from the CM_{I,F}CLKEN bit. Pass back the correct info via 112 * shift from the CM_{I,F}CLKEN bit. Pass back the correct info via
122 * @idlest_reg and @idlest_bit. No return value. 113 * @idlest_reg and @idlest_bit. No return value.
123 */ 114 */
124static void omap3430es2_clk_hsotgusb_find_idlest(struct clk *clk, 115static void omap3430es2_clk_hsotgusb_find_idlest(struct clk_hw_omap *clk,
125 void __iomem **idlest_reg, 116 void __iomem **idlest_reg,
126 u8 *idlest_bit, 117 u8 *idlest_bit,
127 u8 *idlest_val) 118 u8 *idlest_val)
@@ -134,18 +125,14 @@ static void omap3430es2_clk_hsotgusb_find_idlest(struct clk *clk,
134 *idlest_val = OMAP34XX_CM_IDLEST_VAL; 125 *idlest_val = OMAP34XX_CM_IDLEST_VAL;
135} 126}
136 127
137const struct clkops clkops_omap3430es2_hsotgusb_wait = { 128const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait = {
138 .enable = omap2_dflt_clk_enable, 129 .allow_idle = omap2_clkt_iclk_allow_idle,
139 .disable = omap2_dflt_clk_disable, 130 .deny_idle = omap2_clkt_iclk_deny_idle,
140 .find_idlest = omap3430es2_clk_hsotgusb_find_idlest, 131 .find_idlest = omap3430es2_clk_hsotgusb_find_idlest,
141 .find_companion = omap2_clk_dflt_find_companion, 132 .find_companion = omap2_clk_dflt_find_companion,
142}; 133};
143 134
144const struct clkops clkops_omap3430es2_iclk_hsotgusb_wait = { 135const struct clk_hw_omap_ops clkhwops_omap3430es2_hsotgusb_wait = {
145 .enable = omap2_dflt_clk_enable,
146 .disable = omap2_dflt_clk_disable,
147 .find_idlest = omap3430es2_clk_hsotgusb_find_idlest, 136 .find_idlest = omap3430es2_clk_hsotgusb_find_idlest,
148 .find_companion = omap2_clk_dflt_find_companion, 137 .find_companion = omap2_clk_dflt_find_companion,
149 .allow_idle = omap2_clkt_iclk_allow_idle,
150 .deny_idle = omap2_clkt_iclk_deny_idle,
151}; 138};
diff --git a/arch/arm/mach-omap2/clock3517.c b/arch/arm/mach-omap2/clock3517.c
index 622ea0502610..4d79ae2c0241 100644
--- a/arch/arm/mach-omap2/clock3517.c
+++ b/arch/arm/mach-omap2/clock3517.c
@@ -47,7 +47,7 @@
47 * in the enable register itsel at a bit offset of 4 from the enable 47 * in the enable register itsel at a bit offset of 4 from the enable
48 * bit. A value of 1 indicates that clock is enabled. 48 * bit. A value of 1 indicates that clock is enabled.
49 */ 49 */
50static void am35xx_clk_find_idlest(struct clk *clk, 50static void am35xx_clk_find_idlest(struct clk_hw_omap *clk,
51 void __iomem **idlest_reg, 51 void __iomem **idlest_reg,
52 u8 *idlest_bit, 52 u8 *idlest_bit,
53 u8 *idlest_val) 53 u8 *idlest_val)
@@ -71,8 +71,9 @@ static void am35xx_clk_find_idlest(struct clk *clk,
71 * associate this type of code with per-module data structures to 71 * associate this type of code with per-module data structures to
72 * avoid this issue, and remove the casts. No return value. 72 * avoid this issue, and remove the casts. No return value.
73 */ 73 */
74static void am35xx_clk_find_companion(struct clk *clk, void __iomem **other_reg, 74static void am35xx_clk_find_companion(struct clk_hw_omap *clk,
75 u8 *other_bit) 75 void __iomem **other_reg,
76 u8 *other_bit)
76{ 77{
77 *other_reg = (__force void __iomem *)(clk->enable_reg); 78 *other_reg = (__force void __iomem *)(clk->enable_reg);
78 if (clk->enable_bit & AM35XX_IPSS_ICK_MASK) 79 if (clk->enable_bit & AM35XX_IPSS_ICK_MASK)
@@ -80,10 +81,7 @@ static void am35xx_clk_find_companion(struct clk *clk, void __iomem **other_reg,
80 else 81 else
81 *other_bit = clk->enable_bit - AM35XX_IPSS_ICK_FCK_OFFSET; 82 *other_bit = clk->enable_bit - AM35XX_IPSS_ICK_FCK_OFFSET;
82} 83}
83 84const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait = {
84const struct clkops clkops_am35xx_ipss_module_wait = {
85 .enable = omap2_dflt_clk_enable,
86 .disable = omap2_dflt_clk_disable,
87 .find_idlest = am35xx_clk_find_idlest, 85 .find_idlest = am35xx_clk_find_idlest,
88 .find_companion = am35xx_clk_find_companion, 86 .find_companion = am35xx_clk_find_companion,
89}; 87};
@@ -99,7 +97,7 @@ const struct clkops clkops_am35xx_ipss_module_wait = {
99 * CM_{I,F}CLKEN bit. Pass back the correct info via @idlest_reg 97 * CM_{I,F}CLKEN bit. Pass back the correct info via @idlest_reg
100 * and @idlest_bit. No return value. 98 * and @idlest_bit. No return value.
101 */ 99 */
102static void am35xx_clk_ipss_find_idlest(struct clk *clk, 100static void am35xx_clk_ipss_find_idlest(struct clk_hw_omap *clk,
103 void __iomem **idlest_reg, 101 void __iomem **idlest_reg,
104 u8 *idlest_bit, 102 u8 *idlest_bit,
105 u8 *idlest_val) 103 u8 *idlest_val)
@@ -112,13 +110,9 @@ static void am35xx_clk_ipss_find_idlest(struct clk *clk,
112 *idlest_val = OMAP34XX_CM_IDLEST_VAL; 110 *idlest_val = OMAP34XX_CM_IDLEST_VAL;
113} 111}
114 112
115const struct clkops clkops_am35xx_ipss_wait = { 113const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait = {
116 .enable = omap2_dflt_clk_enable,
117 .disable = omap2_dflt_clk_disable,
118 .find_idlest = am35xx_clk_ipss_find_idlest,
119 .find_companion = omap2_clk_dflt_find_companion,
120 .allow_idle = omap2_clkt_iclk_allow_idle, 114 .allow_idle = omap2_clkt_iclk_allow_idle,
121 .deny_idle = omap2_clkt_iclk_deny_idle, 115 .deny_idle = omap2_clkt_iclk_deny_idle,
116 .find_idlest = am35xx_clk_ipss_find_idlest,
117 .find_companion = omap2_clk_dflt_find_companion,
122}; 118};
123
124
diff --git a/arch/arm/mach-omap2/clock36xx.c b/arch/arm/mach-omap2/clock36xx.c
index 0e1e9e4e2fa4..8f3bf4e50908 100644
--- a/arch/arm/mach-omap2/clock36xx.c
+++ b/arch/arm/mach-omap2/clock36xx.c
@@ -37,34 +37,32 @@
37 * (Any other value different from the Read value) to the 37 * (Any other value different from the Read value) to the
38 * corresponding CM_CLKSEL register will refresh the dividers. 38 * corresponding CM_CLKSEL register will refresh the dividers.
39 */ 39 */
40static int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk *clk) 40int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk_hw *clk)
41{ 41{
42 struct clk_hw_omap *parent;
43 struct clk_hw *parent_hw;
42 u32 dummy_v, orig_v, clksel_shift; 44 u32 dummy_v, orig_v, clksel_shift;
43 int ret; 45 int ret;
44 46
45 /* Clear PWRDN bit of HSDIVIDER */ 47 /* Clear PWRDN bit of HSDIVIDER */
46 ret = omap2_dflt_clk_enable(clk); 48 ret = omap2_dflt_clk_enable(clk);
47 49
50 parent_hw = __clk_get_hw(__clk_get_parent(clk->clk));
51 parent = to_clk_hw_omap(parent_hw);
52
48 /* Restore the dividers */ 53 /* Restore the dividers */
49 if (!ret) { 54 if (!ret) {
50 clksel_shift = __ffs(clk->parent->clksel_mask); 55 clksel_shift = __ffs(parent->clksel_mask);
51 orig_v = __raw_readl(clk->parent->clksel_reg); 56 orig_v = __raw_readl(parent->clksel_reg);
52 dummy_v = orig_v; 57 dummy_v = orig_v;
53 58
54 /* Write any other value different from the Read value */ 59 /* Write any other value different from the Read value */
55 dummy_v ^= (1 << clksel_shift); 60 dummy_v ^= (1 << clksel_shift);
56 __raw_writel(dummy_v, clk->parent->clksel_reg); 61 __raw_writel(dummy_v, parent->clksel_reg);
57 62
58 /* Write the original divider */ 63 /* Write the original divider */
59 __raw_writel(orig_v, clk->parent->clksel_reg); 64 __raw_writel(orig_v, parent->clksel_reg);
60 } 65 }
61 66
62 return ret; 67 return ret;
63} 68}
64
65const struct clkops clkops_omap36xx_pwrdn_with_hsdiv_wait_restore = {
66 .enable = omap36xx_pwrdn_clk_enable_with_hsdiv_restore,
67 .disable = omap2_dflt_clk_disable,
68 .find_companion = omap2_clk_dflt_find_companion,
69 .find_idlest = omap2_clk_dflt_find_idlest,
70};
diff --git a/arch/arm/mach-omap2/clock36xx.h b/arch/arm/mach-omap2/clock36xx.h
index a7dee5bc6364..945bb7f083e9 100644
--- a/arch/arm/mach-omap2/clock36xx.h
+++ b/arch/arm/mach-omap2/clock36xx.h
@@ -8,6 +8,6 @@
8#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK36XX_H 8#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK36XX_H
9#define __ARCH_ARM_MACH_OMAP2_CLOCK36XX_H 9#define __ARCH_ARM_MACH_OMAP2_CLOCK36XX_H
10 10
11extern const struct clkops clkops_omap36xx_pwrdn_with_hsdiv_wait_restore; 11extern int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk_hw *hw);
12 12
13#endif 13#endif
diff --git a/arch/arm/mach-omap2/clock3xxx.c b/arch/arm/mach-omap2/clock3xxx.c
index 3e8aca2b1b61..4eacab8f1176 100644
--- a/arch/arm/mach-omap2/clock3xxx.c
+++ b/arch/arm/mach-omap2/clock3xxx.c
@@ -38,8 +38,8 @@
38 38
39/* needed by omap3_core_dpll_m2_set_rate() */ 39/* needed by omap3_core_dpll_m2_set_rate() */
40struct clk *sdrc_ick_p, *arm_fck_p; 40struct clk *sdrc_ick_p, *arm_fck_p;
41 41int omap3_dpll4_set_rate(struct clk_hw *hw, unsigned long rate,
42int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate) 42 unsigned long parent_rate)
43{ 43{
44 /* 44 /*
45 * According to the 12-5 CDP code from TI, "Limitation 2.5" 45 * According to the 12-5 CDP code from TI, "Limitation 2.5"
@@ -51,7 +51,7 @@ int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate)
51 return -EINVAL; 51 return -EINVAL;
52 } 52 }
53 53
54 return omap3_noncore_dpll_set_rate(clk, rate); 54 return omap3_noncore_dpll_set_rate(hw, rate, parent_rate);
55} 55}
56 56
57void __init omap3_clk_lock_dpll5(void) 57void __init omap3_clk_lock_dpll5(void)
diff --git a/arch/arm/mach-omap2/clock3xxx.h b/arch/arm/mach-omap2/clock3xxx.h
index 8bbeeaf399e2..8cd4b0a882ae 100644
--- a/arch/arm/mach-omap2/clock3xxx.h
+++ b/arch/arm/mach-omap2/clock3xxx.h
@@ -9,8 +9,10 @@
9#define __ARCH_ARM_MACH_OMAP2_CLOCK3XXX_H 9#define __ARCH_ARM_MACH_OMAP2_CLOCK3XXX_H
10 10
11int omap3xxx_clk_init(void); 11int omap3xxx_clk_init(void);
12int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate); 12int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
13int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate); 13 unsigned long parent_rate);
14int omap3_core_dpll_m2_set_rate(struct clk_hw *clk, unsigned long rate,
15 unsigned long parent_rate);
14void omap3_clk_lock_dpll5(void); 16void omap3_clk_lock_dpll5(void);
15 17
16extern struct clk *sdrc_ick_p; 18extern struct clk *sdrc_ick_p;
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
deleted file mode 100644
index 6cca19953950..000000000000
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ /dev/null
@@ -1,3613 +0,0 @@
1/*
2 * OMAP3 clock data
3 *
4 * Copyright (C) 2007-2010, 2012 Texas Instruments, Inc.
5 * Copyright (C) 2007-2011 Nokia Corporation
6 *
7 * Written by Paul Walmsley
8 * With many device clock fixes by Kevin Hilman and Jouni Högander
9 * DPLL bypass clock support added by Roman Tereshonkov
10 *
11 */
12
13/*
14 * Virtual clocks are introduced as convenient tools.
15 * They are sources for other clocks and not supposed
16 * to be requested from drivers directly.
17 */
18
19#include <linux/kernel.h>
20#include <linux/clk.h>
21#include <linux/list.h>
22#include <linux/io.h>
23
24#include "soc.h"
25#include "iomap.h"
26#include "clock.h"
27#include "clock3xxx.h"
28#include "clock34xx.h"
29#include "clock36xx.h"
30#include "clock3517.h"
31#include "cm3xxx.h"
32#include "cm-regbits-34xx.h"
33#include "prm2xxx_3xxx.h"
34#include "prm-regbits-34xx.h"
35#include "control.h"
36
37/*
38 * clocks
39 */
40
41#define OMAP_CM_REGADDR OMAP34XX_CM_REGADDR
42
43/* Maximum DPLL multiplier, divider values for OMAP3 */
44#define OMAP3_MAX_DPLL_MULT 2047
45#define OMAP3630_MAX_JTYPE_DPLL_MULT 4095
46#define OMAP3_MAX_DPLL_DIV 128
47
48/*
49 * DPLL1 supplies clock to the MPU.
50 * DPLL2 supplies clock to the IVA2.
51 * DPLL3 supplies CORE domain clocks.
52 * DPLL4 supplies peripheral clocks.
53 * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
54 */
55
56/* Forward declarations for DPLL bypass clocks */
57static struct clk dpll1_fck;
58static struct clk dpll2_fck;
59
60/* PRM CLOCKS */
61
62/* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
63static struct clk omap_32k_fck = {
64 .name = "omap_32k_fck",
65 .ops = &clkops_null,
66 .rate = 32768,
67};
68
69static struct clk secure_32k_fck = {
70 .name = "secure_32k_fck",
71 .ops = &clkops_null,
72 .rate = 32768,
73};
74
75/* Virtual source clocks for osc_sys_ck */
76static struct clk virt_12m_ck = {
77 .name = "virt_12m_ck",
78 .ops = &clkops_null,
79 .rate = 12000000,
80};
81
82static struct clk virt_13m_ck = {
83 .name = "virt_13m_ck",
84 .ops = &clkops_null,
85 .rate = 13000000,
86};
87
88static struct clk virt_16_8m_ck = {
89 .name = "virt_16_8m_ck",
90 .ops = &clkops_null,
91 .rate = 16800000,
92};
93
94static struct clk virt_38_4m_ck = {
95 .name = "virt_38_4m_ck",
96 .ops = &clkops_null,
97 .rate = 38400000,
98};
99
100static const struct clksel_rate osc_sys_12m_rates[] = {
101 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
102 { .div = 0 }
103};
104
105static const struct clksel_rate osc_sys_13m_rates[] = {
106 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
107 { .div = 0 }
108};
109
110static const struct clksel_rate osc_sys_16_8m_rates[] = {
111 { .div = 1, .val = 5, .flags = RATE_IN_3430ES2PLUS_36XX },
112 { .div = 0 }
113};
114
115static const struct clksel_rate osc_sys_19_2m_rates[] = {
116 { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
117 { .div = 0 }
118};
119
120static const struct clksel_rate osc_sys_26m_rates[] = {
121 { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
122 { .div = 0 }
123};
124
125static const struct clksel_rate osc_sys_38_4m_rates[] = {
126 { .div = 1, .val = 4, .flags = RATE_IN_3XXX },
127 { .div = 0 }
128};
129
130static const struct clksel osc_sys_clksel[] = {
131 { .parent = &virt_12m_ck, .rates = osc_sys_12m_rates },
132 { .parent = &virt_13m_ck, .rates = osc_sys_13m_rates },
133 { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
134 { .parent = &virt_19200000_ck, .rates = osc_sys_19_2m_rates },
135 { .parent = &virt_26000000_ck, .rates = osc_sys_26m_rates },
136 { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
137 { .parent = NULL },
138};
139
140/* Oscillator clock */
141/* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
142static struct clk osc_sys_ck = {
143 .name = "osc_sys_ck",
144 .ops = &clkops_null,
145 .init = &omap2_init_clksel_parent,
146 .clksel_reg = OMAP3430_PRM_CLKSEL,
147 .clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK,
148 .clksel = osc_sys_clksel,
149 /* REVISIT: deal with autoextclkmode? */
150 .recalc = &omap2_clksel_recalc,
151};
152
153static const struct clksel_rate div2_rates[] = {
154 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
155 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
156 { .div = 0 }
157};
158
159static const struct clksel sys_clksel[] = {
160 { .parent = &osc_sys_ck, .rates = div2_rates },
161 { .parent = NULL }
162};
163
164/* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
165/* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
166static struct clk sys_ck = {
167 .name = "sys_ck",
168 .ops = &clkops_null,
169 .parent = &osc_sys_ck,
170 .init = &omap2_init_clksel_parent,
171 .clksel_reg = OMAP3430_PRM_CLKSRC_CTRL,
172 .clksel_mask = OMAP_SYSCLKDIV_MASK,
173 .clksel = sys_clksel,
174 .recalc = &omap2_clksel_recalc,
175};
176
177static struct clk sys_altclk = {
178 .name = "sys_altclk",
179 .ops = &clkops_null,
180};
181
182/* Optional external clock input for some McBSPs */
183static struct clk mcbsp_clks = {
184 .name = "mcbsp_clks",
185 .ops = &clkops_null,
186};
187
188/* PRM EXTERNAL CLOCK OUTPUT */
189
190static struct clk sys_clkout1 = {
191 .name = "sys_clkout1",
192 .ops = &clkops_omap2_dflt,
193 .parent = &osc_sys_ck,
194 .enable_reg = OMAP3430_PRM_CLKOUT_CTRL,
195 .enable_bit = OMAP3430_CLKOUT_EN_SHIFT,
196 .recalc = &followparent_recalc,
197};
198
199/* DPLLS */
200
201/* CM CLOCKS */
202
203static const struct clksel_rate div16_dpll_rates[] = {
204 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
205 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
206 { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
207 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
208 { .div = 5, .val = 5, .flags = RATE_IN_3XXX },
209 { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
210 { .div = 7, .val = 7, .flags = RATE_IN_3XXX },
211 { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
212 { .div = 9, .val = 9, .flags = RATE_IN_3XXX },
213 { .div = 10, .val = 10, .flags = RATE_IN_3XXX },
214 { .div = 11, .val = 11, .flags = RATE_IN_3XXX },
215 { .div = 12, .val = 12, .flags = RATE_IN_3XXX },
216 { .div = 13, .val = 13, .flags = RATE_IN_3XXX },
217 { .div = 14, .val = 14, .flags = RATE_IN_3XXX },
218 { .div = 15, .val = 15, .flags = RATE_IN_3XXX },
219 { .div = 16, .val = 16, .flags = RATE_IN_3XXX },
220 { .div = 0 }
221};
222
223static const struct clksel_rate dpll4_rates[] = {
224 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
225 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
226 { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
227 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
228 { .div = 5, .val = 5, .flags = RATE_IN_3XXX },
229 { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
230 { .div = 7, .val = 7, .flags = RATE_IN_3XXX },
231 { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
232 { .div = 9, .val = 9, .flags = RATE_IN_3XXX },
233 { .div = 10, .val = 10, .flags = RATE_IN_3XXX },
234 { .div = 11, .val = 11, .flags = RATE_IN_3XXX },
235 { .div = 12, .val = 12, .flags = RATE_IN_3XXX },
236 { .div = 13, .val = 13, .flags = RATE_IN_3XXX },
237 { .div = 14, .val = 14, .flags = RATE_IN_3XXX },
238 { .div = 15, .val = 15, .flags = RATE_IN_3XXX },
239 { .div = 16, .val = 16, .flags = RATE_IN_3XXX },
240 { .div = 17, .val = 17, .flags = RATE_IN_36XX },
241 { .div = 18, .val = 18, .flags = RATE_IN_36XX },
242 { .div = 19, .val = 19, .flags = RATE_IN_36XX },
243 { .div = 20, .val = 20, .flags = RATE_IN_36XX },
244 { .div = 21, .val = 21, .flags = RATE_IN_36XX },
245 { .div = 22, .val = 22, .flags = RATE_IN_36XX },
246 { .div = 23, .val = 23, .flags = RATE_IN_36XX },
247 { .div = 24, .val = 24, .flags = RATE_IN_36XX },
248 { .div = 25, .val = 25, .flags = RATE_IN_36XX },
249 { .div = 26, .val = 26, .flags = RATE_IN_36XX },
250 { .div = 27, .val = 27, .flags = RATE_IN_36XX },
251 { .div = 28, .val = 28, .flags = RATE_IN_36XX },
252 { .div = 29, .val = 29, .flags = RATE_IN_36XX },
253 { .div = 30, .val = 30, .flags = RATE_IN_36XX },
254 { .div = 31, .val = 31, .flags = RATE_IN_36XX },
255 { .div = 32, .val = 32, .flags = RATE_IN_36XX },
256 { .div = 0 }
257};
258
259/* DPLL1 */
260/* MPU clock source */
261/* Type: DPLL */
262static struct dpll_data dpll1_dd = {
263 .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
264 .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK,
265 .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK,
266 .clk_bypass = &dpll1_fck,
267 .clk_ref = &sys_ck,
268 .freqsel_mask = OMAP3430_MPU_DPLL_FREQSEL_MASK,
269 .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
270 .enable_mask = OMAP3430_EN_MPU_DPLL_MASK,
271 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
272 .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
273 .recal_en_bit = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
274 .recal_st_bit = OMAP3430_MPU_DPLL_ST_SHIFT,
275 .autoidle_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
276 .autoidle_mask = OMAP3430_AUTO_MPU_DPLL_MASK,
277 .idlest_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
278 .idlest_mask = OMAP3430_ST_MPU_CLK_MASK,
279 .max_multiplier = OMAP3_MAX_DPLL_MULT,
280 .min_divider = 1,
281 .max_divider = OMAP3_MAX_DPLL_DIV,
282};
283
284static struct clk dpll1_ck = {
285 .name = "dpll1_ck",
286 .ops = &clkops_omap3_noncore_dpll_ops,
287 .parent = &sys_ck,
288 .dpll_data = &dpll1_dd,
289 .round_rate = &omap2_dpll_round_rate,
290 .set_rate = &omap3_noncore_dpll_set_rate,
291 .clkdm_name = "dpll1_clkdm",
292 .recalc = &omap3_dpll_recalc,
293};
294
295/*
296 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
297 * DPLL isn't bypassed.
298 */
299static struct clk dpll1_x2_ck = {
300 .name = "dpll1_x2_ck",
301 .ops = &clkops_null,
302 .parent = &dpll1_ck,
303 .clkdm_name = "dpll1_clkdm",
304 .recalc = &omap3_clkoutx2_recalc,
305};
306
307/* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
308static const struct clksel div16_dpll1_x2m2_clksel[] = {
309 { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
310 { .parent = NULL }
311};
312
313/*
314 * Does not exist in the TRM - needed to separate the M2 divider from
315 * bypass selection in mpu_ck
316 */
317static struct clk dpll1_x2m2_ck = {
318 .name = "dpll1_x2m2_ck",
319 .ops = &clkops_null,
320 .parent = &dpll1_x2_ck,
321 .init = &omap2_init_clksel_parent,
322 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
323 .clksel_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
324 .clksel = div16_dpll1_x2m2_clksel,
325 .clkdm_name = "dpll1_clkdm",
326 .recalc = &omap2_clksel_recalc,
327};
328
329/* DPLL2 */
330/* IVA2 clock source */
331/* Type: DPLL */
332
333static struct dpll_data dpll2_dd = {
334 .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
335 .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK,
336 .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK,
337 .clk_bypass = &dpll2_fck,
338 .clk_ref = &sys_ck,
339 .freqsel_mask = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
340 .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
341 .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK,
342 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
343 (1 << DPLL_LOW_POWER_BYPASS),
344 .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
345 .recal_en_bit = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
346 .recal_st_bit = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
347 .autoidle_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
348 .autoidle_mask = OMAP3430_AUTO_IVA2_DPLL_MASK,
349 .idlest_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
350 .idlest_mask = OMAP3430_ST_IVA2_CLK_MASK,
351 .max_multiplier = OMAP3_MAX_DPLL_MULT,
352 .min_divider = 1,
353 .max_divider = OMAP3_MAX_DPLL_DIV,
354};
355
356static struct clk dpll2_ck = {
357 .name = "dpll2_ck",
358 .ops = &clkops_omap3_noncore_dpll_ops,
359 .parent = &sys_ck,
360 .dpll_data = &dpll2_dd,
361 .round_rate = &omap2_dpll_round_rate,
362 .set_rate = &omap3_noncore_dpll_set_rate,
363 .clkdm_name = "dpll2_clkdm",
364 .recalc = &omap3_dpll_recalc,
365};
366
367static const struct clksel div16_dpll2_m2x2_clksel[] = {
368 { .parent = &dpll2_ck, .rates = div16_dpll_rates },
369 { .parent = NULL }
370};
371
372/*
373 * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
374 * or CLKOUTX2. CLKOUT seems most plausible.
375 */
376static struct clk dpll2_m2_ck = {
377 .name = "dpll2_m2_ck",
378 .ops = &clkops_null,
379 .parent = &dpll2_ck,
380 .init = &omap2_init_clksel_parent,
381 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
382 OMAP3430_CM_CLKSEL2_PLL),
383 .clksel_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
384 .clksel = div16_dpll2_m2x2_clksel,
385 .clkdm_name = "dpll2_clkdm",
386 .recalc = &omap2_clksel_recalc,
387};
388
389/*
390 * DPLL3
391 * Source clock for all interfaces and for some device fclks
392 * REVISIT: Also supports fast relock bypass - not included below
393 */
394static struct dpll_data dpll3_dd = {
395 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
396 .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK,
397 .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK,
398 .clk_bypass = &sys_ck,
399 .clk_ref = &sys_ck,
400 .freqsel_mask = OMAP3430_CORE_DPLL_FREQSEL_MASK,
401 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
402 .enable_mask = OMAP3430_EN_CORE_DPLL_MASK,
403 .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
404 .recal_en_bit = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
405 .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT,
406 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
407 .autoidle_mask = OMAP3430_AUTO_CORE_DPLL_MASK,
408 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
409 .idlest_mask = OMAP3430_ST_CORE_CLK_MASK,
410 .max_multiplier = OMAP3_MAX_DPLL_MULT,
411 .min_divider = 1,
412 .max_divider = OMAP3_MAX_DPLL_DIV,
413};
414
415static struct clk dpll3_ck = {
416 .name = "dpll3_ck",
417 .ops = &clkops_omap3_core_dpll_ops,
418 .parent = &sys_ck,
419 .dpll_data = &dpll3_dd,
420 .round_rate = &omap2_dpll_round_rate,
421 .clkdm_name = "dpll3_clkdm",
422 .recalc = &omap3_dpll_recalc,
423};
424
425/*
426 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
427 * DPLL isn't bypassed
428 */
429static struct clk dpll3_x2_ck = {
430 .name = "dpll3_x2_ck",
431 .ops = &clkops_null,
432 .parent = &dpll3_ck,
433 .clkdm_name = "dpll3_clkdm",
434 .recalc = &omap3_clkoutx2_recalc,
435};
436
437static const struct clksel_rate div31_dpll3_rates[] = {
438 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
439 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
440 { .div = 3, .val = 3, .flags = RATE_IN_3430ES2PLUS_36XX },
441 { .div = 4, .val = 4, .flags = RATE_IN_3430ES2PLUS_36XX },
442 { .div = 5, .val = 5, .flags = RATE_IN_3430ES2PLUS_36XX },
443 { .div = 6, .val = 6, .flags = RATE_IN_3430ES2PLUS_36XX },
444 { .div = 7, .val = 7, .flags = RATE_IN_3430ES2PLUS_36XX },
445 { .div = 8, .val = 8, .flags = RATE_IN_3430ES2PLUS_36XX },
446 { .div = 9, .val = 9, .flags = RATE_IN_3430ES2PLUS_36XX },
447 { .div = 10, .val = 10, .flags = RATE_IN_3430ES2PLUS_36XX },
448 { .div = 11, .val = 11, .flags = RATE_IN_3430ES2PLUS_36XX },
449 { .div = 12, .val = 12, .flags = RATE_IN_3430ES2PLUS_36XX },
450 { .div = 13, .val = 13, .flags = RATE_IN_3430ES2PLUS_36XX },
451 { .div = 14, .val = 14, .flags = RATE_IN_3430ES2PLUS_36XX },
452 { .div = 15, .val = 15, .flags = RATE_IN_3430ES2PLUS_36XX },
453 { .div = 16, .val = 16, .flags = RATE_IN_3430ES2PLUS_36XX },
454 { .div = 17, .val = 17, .flags = RATE_IN_3430ES2PLUS_36XX },
455 { .div = 18, .val = 18, .flags = RATE_IN_3430ES2PLUS_36XX },
456 { .div = 19, .val = 19, .flags = RATE_IN_3430ES2PLUS_36XX },
457 { .div = 20, .val = 20, .flags = RATE_IN_3430ES2PLUS_36XX },
458 { .div = 21, .val = 21, .flags = RATE_IN_3430ES2PLUS_36XX },
459 { .div = 22, .val = 22, .flags = RATE_IN_3430ES2PLUS_36XX },
460 { .div = 23, .val = 23, .flags = RATE_IN_3430ES2PLUS_36XX },
461 { .div = 24, .val = 24, .flags = RATE_IN_3430ES2PLUS_36XX },
462 { .div = 25, .val = 25, .flags = RATE_IN_3430ES2PLUS_36XX },
463 { .div = 26, .val = 26, .flags = RATE_IN_3430ES2PLUS_36XX },
464 { .div = 27, .val = 27, .flags = RATE_IN_3430ES2PLUS_36XX },
465 { .div = 28, .val = 28, .flags = RATE_IN_3430ES2PLUS_36XX },
466 { .div = 29, .val = 29, .flags = RATE_IN_3430ES2PLUS_36XX },
467 { .div = 30, .val = 30, .flags = RATE_IN_3430ES2PLUS_36XX },
468 { .div = 31, .val = 31, .flags = RATE_IN_3430ES2PLUS_36XX },
469 { .div = 0 },
470};
471
472static const struct clksel div31_dpll3m2_clksel[] = {
473 { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
474 { .parent = NULL }
475};
476
477/* DPLL3 output M2 - primary control point for CORE speed */
478static struct clk dpll3_m2_ck = {
479 .name = "dpll3_m2_ck",
480 .ops = &clkops_null,
481 .parent = &dpll3_ck,
482 .init = &omap2_init_clksel_parent,
483 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
484 .clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
485 .clksel = div31_dpll3m2_clksel,
486 .clkdm_name = "dpll3_clkdm",
487 .round_rate = &omap2_clksel_round_rate,
488 .set_rate = &omap3_core_dpll_m2_set_rate,
489 .recalc = &omap2_clksel_recalc,
490};
491
492static struct clk core_ck = {
493 .name = "core_ck",
494 .ops = &clkops_null,
495 .parent = &dpll3_m2_ck,
496 .recalc = &followparent_recalc,
497};
498
499static struct clk dpll3_m2x2_ck = {
500 .name = "dpll3_m2x2_ck",
501 .ops = &clkops_null,
502 .parent = &dpll3_m2_ck,
503 .clkdm_name = "dpll3_clkdm",
504 .recalc = &omap3_clkoutx2_recalc,
505};
506
507/* The PWRDN bit is apparently only available on 3430ES2 and above */
508static const struct clksel div16_dpll3_clksel[] = {
509 { .parent = &dpll3_ck, .rates = div16_dpll_rates },
510 { .parent = NULL }
511};
512
513/* This virtual clock is the source for dpll3_m3x2_ck */
514static struct clk dpll3_m3_ck = {
515 .name = "dpll3_m3_ck",
516 .ops = &clkops_null,
517 .parent = &dpll3_ck,
518 .init = &omap2_init_clksel_parent,
519 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
520 .clksel_mask = OMAP3430_DIV_DPLL3_MASK,
521 .clksel = div16_dpll3_clksel,
522 .clkdm_name = "dpll3_clkdm",
523 .recalc = &omap2_clksel_recalc,
524};
525
526/* The PWRDN bit is apparently only available on 3430ES2 and above */
527static struct clk dpll3_m3x2_ck = {
528 .name = "dpll3_m3x2_ck",
529 .ops = &clkops_omap2_dflt_wait,
530 .parent = &dpll3_m3_ck,
531 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
532 .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT,
533 .flags = INVERT_ENABLE,
534 .clkdm_name = "dpll3_clkdm",
535 .recalc = &omap3_clkoutx2_recalc,
536};
537
538static struct clk emu_core_alwon_ck = {
539 .name = "emu_core_alwon_ck",
540 .ops = &clkops_null,
541 .parent = &dpll3_m3x2_ck,
542 .clkdm_name = "dpll3_clkdm",
543 .recalc = &followparent_recalc,
544};
545
546/* DPLL4 */
547/* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
548/* Type: DPLL */
549static struct dpll_data dpll4_dd;
550
551static struct dpll_data dpll4_dd_34xx __initdata = {
552 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
553 .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK,
554 .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK,
555 .clk_bypass = &sys_ck,
556 .clk_ref = &sys_ck,
557 .freqsel_mask = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
558 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
559 .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK,
560 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
561 .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
562 .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
563 .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT,
564 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
565 .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK,
566 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
567 .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK,
568 .max_multiplier = OMAP3_MAX_DPLL_MULT,
569 .min_divider = 1,
570 .max_divider = OMAP3_MAX_DPLL_DIV,
571};
572
573static struct dpll_data dpll4_dd_3630 __initdata = {
574 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
575 .mult_mask = OMAP3630_PERIPH_DPLL_MULT_MASK,
576 .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK,
577 .clk_bypass = &sys_ck,
578 .clk_ref = &sys_ck,
579 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
580 .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK,
581 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
582 .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
583 .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
584 .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT,
585 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
586 .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK,
587 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
588 .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK,
589 .dco_mask = OMAP3630_PERIPH_DPLL_DCO_SEL_MASK,
590 .sddiv_mask = OMAP3630_PERIPH_DPLL_SD_DIV_MASK,
591 .max_multiplier = OMAP3630_MAX_JTYPE_DPLL_MULT,
592 .min_divider = 1,
593 .max_divider = OMAP3_MAX_DPLL_DIV,
594 .flags = DPLL_J_TYPE
595};
596
597static struct clk dpll4_ck = {
598 .name = "dpll4_ck",
599 .ops = &clkops_omap3_noncore_dpll_ops,
600 .parent = &sys_ck,
601 .dpll_data = &dpll4_dd,
602 .round_rate = &omap2_dpll_round_rate,
603 .set_rate = &omap3_dpll4_set_rate,
604 .clkdm_name = "dpll4_clkdm",
605 .recalc = &omap3_dpll_recalc,
606};
607
608/*
609 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
610 * DPLL isn't bypassed --
611 * XXX does this serve any downstream clocks?
612 */
613static struct clk dpll4_x2_ck = {
614 .name = "dpll4_x2_ck",
615 .ops = &clkops_null,
616 .parent = &dpll4_ck,
617 .clkdm_name = "dpll4_clkdm",
618 .recalc = &omap3_clkoutx2_recalc,
619};
620
621static const struct clksel dpll4_clksel[] = {
622 { .parent = &dpll4_ck, .rates = dpll4_rates },
623 { .parent = NULL }
624};
625
626/* This virtual clock is the source for dpll4_m2x2_ck */
627static struct clk dpll4_m2_ck = {
628 .name = "dpll4_m2_ck",
629 .ops = &clkops_null,
630 .parent = &dpll4_ck,
631 .init = &omap2_init_clksel_parent,
632 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
633 .clksel_mask = OMAP3630_DIV_96M_MASK,
634 .clksel = dpll4_clksel,
635 .clkdm_name = "dpll4_clkdm",
636 .recalc = &omap2_clksel_recalc,
637};
638
639/* The PWRDN bit is apparently only available on 3430ES2 and above */
640static struct clk dpll4_m2x2_ck = {
641 .name = "dpll4_m2x2_ck",
642 .ops = &clkops_omap2_dflt_wait,
643 .parent = &dpll4_m2_ck,
644 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
645 .enable_bit = OMAP3430_PWRDN_96M_SHIFT,
646 .flags = INVERT_ENABLE,
647 .clkdm_name = "dpll4_clkdm",
648 .recalc = &omap3_clkoutx2_recalc,
649};
650
651/*
652 * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
653 * PRM_96M_ALWON_(F)CLK. Two clocks then emerge from the PRM:
654 * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
655 * CM_96K_(F)CLK.
656 */
657
658/* Adding 192MHz Clock node needed by SGX */
659static struct clk omap_192m_alwon_fck = {
660 .name = "omap_192m_alwon_fck",
661 .ops = &clkops_null,
662 .parent = &dpll4_m2x2_ck,
663 .recalc = &followparent_recalc,
664};
665
666static const struct clksel_rate omap_96m_alwon_fck_rates[] = {
667 { .div = 1, .val = 1, .flags = RATE_IN_36XX },
668 { .div = 2, .val = 2, .flags = RATE_IN_36XX },
669 { .div = 0 }
670};
671
672static const struct clksel omap_96m_alwon_fck_clksel[] = {
673 { .parent = &omap_192m_alwon_fck, .rates = omap_96m_alwon_fck_rates },
674 { .parent = NULL }
675};
676
677static const struct clksel_rate omap_96m_dpll_rates[] = {
678 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
679 { .div = 0 }
680};
681
682static const struct clksel_rate omap_96m_sys_rates[] = {
683 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
684 { .div = 0 }
685};
686
687static struct clk omap_96m_alwon_fck = {
688 .name = "omap_96m_alwon_fck",
689 .ops = &clkops_null,
690 .parent = &dpll4_m2x2_ck,
691 .recalc = &followparent_recalc,
692};
693
694static struct clk omap_96m_alwon_fck_3630 = {
695 .name = "omap_96m_alwon_fck",
696 .parent = &omap_192m_alwon_fck,
697 .init = &omap2_init_clksel_parent,
698 .ops = &clkops_null,
699 .recalc = &omap2_clksel_recalc,
700 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
701 .clksel_mask = OMAP3630_CLKSEL_96M_MASK,
702 .clksel = omap_96m_alwon_fck_clksel
703};
704
705static struct clk cm_96m_fck = {
706 .name = "cm_96m_fck",
707 .ops = &clkops_null,
708 .parent = &omap_96m_alwon_fck,
709 .recalc = &followparent_recalc,
710};
711
712static const struct clksel omap_96m_fck_clksel[] = {
713 { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates },
714 { .parent = &sys_ck, .rates = omap_96m_sys_rates },
715 { .parent = NULL }
716};
717
718static struct clk omap_96m_fck = {
719 .name = "omap_96m_fck",
720 .ops = &clkops_null,
721 .parent = &sys_ck,
722 .init = &omap2_init_clksel_parent,
723 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
724 .clksel_mask = OMAP3430_SOURCE_96M_MASK,
725 .clksel = omap_96m_fck_clksel,
726 .recalc = &omap2_clksel_recalc,
727};
728
729/* This virtual clock is the source for dpll4_m3x2_ck */
730static struct clk dpll4_m3_ck = {
731 .name = "dpll4_m3_ck",
732 .ops = &clkops_null,
733 .parent = &dpll4_ck,
734 .init = &omap2_init_clksel_parent,
735 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
736 .clksel_mask = OMAP3630_CLKSEL_TV_MASK,
737 .clksel = dpll4_clksel,
738 .clkdm_name = "dpll4_clkdm",
739 .recalc = &omap2_clksel_recalc,
740};
741
742/* The PWRDN bit is apparently only available on 3430ES2 and above */
743static struct clk dpll4_m3x2_ck = {
744 .name = "dpll4_m3x2_ck",
745 .ops = &clkops_omap2_dflt_wait,
746 .parent = &dpll4_m3_ck,
747 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
748 .enable_bit = OMAP3430_PWRDN_TV_SHIFT,
749 .flags = INVERT_ENABLE,
750 .clkdm_name = "dpll4_clkdm",
751 .recalc = &omap3_clkoutx2_recalc,
752};
753
754static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
755 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
756 { .div = 0 }
757};
758
759static const struct clksel_rate omap_54m_alt_rates[] = {
760 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
761 { .div = 0 }
762};
763
764static const struct clksel omap_54m_clksel[] = {
765 { .parent = &dpll4_m3x2_ck, .rates = omap_54m_d4m3x2_rates },
766 { .parent = &sys_altclk, .rates = omap_54m_alt_rates },
767 { .parent = NULL }
768};
769
770static struct clk omap_54m_fck = {
771 .name = "omap_54m_fck",
772 .ops = &clkops_null,
773 .init = &omap2_init_clksel_parent,
774 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
775 .clksel_mask = OMAP3430_SOURCE_54M_MASK,
776 .clksel = omap_54m_clksel,
777 .recalc = &omap2_clksel_recalc,
778};
779
780static const struct clksel_rate omap_48m_cm96m_rates[] = {
781 { .div = 2, .val = 0, .flags = RATE_IN_3XXX },
782 { .div = 0 }
783};
784
785static const struct clksel_rate omap_48m_alt_rates[] = {
786 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
787 { .div = 0 }
788};
789
790static const struct clksel omap_48m_clksel[] = {
791 { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
792 { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
793 { .parent = NULL }
794};
795
796static struct clk omap_48m_fck = {
797 .name = "omap_48m_fck",
798 .ops = &clkops_null,
799 .init = &omap2_init_clksel_parent,
800 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
801 .clksel_mask = OMAP3430_SOURCE_48M_MASK,
802 .clksel = omap_48m_clksel,
803 .recalc = &omap2_clksel_recalc,
804};
805
806static struct clk omap_12m_fck = {
807 .name = "omap_12m_fck",
808 .ops = &clkops_null,
809 .parent = &omap_48m_fck,
810 .fixed_div = 4,
811 .recalc = &omap_fixed_divisor_recalc,
812};
813
814/* This virtual clock is the source for dpll4_m4x2_ck */
815static struct clk dpll4_m4_ck = {
816 .name = "dpll4_m4_ck",
817 .ops = &clkops_null,
818 .parent = &dpll4_ck,
819 .init = &omap2_init_clksel_parent,
820 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
821 .clksel_mask = OMAP3630_CLKSEL_DSS1_MASK,
822 .clksel = dpll4_clksel,
823 .clkdm_name = "dpll4_clkdm",
824 .recalc = &omap2_clksel_recalc,
825 .set_rate = &omap2_clksel_set_rate,
826 .round_rate = &omap2_clksel_round_rate,
827};
828
829/* The PWRDN bit is apparently only available on 3430ES2 and above */
830static struct clk dpll4_m4x2_ck = {
831 .name = "dpll4_m4x2_ck",
832 .ops = &clkops_omap2_dflt_wait,
833 .parent = &dpll4_m4_ck,
834 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
835 .enable_bit = OMAP3430_PWRDN_DSS1_SHIFT,
836 .flags = INVERT_ENABLE,
837 .clkdm_name = "dpll4_clkdm",
838 .recalc = &omap3_clkoutx2_recalc,
839};
840
841/* This virtual clock is the source for dpll4_m5x2_ck */
842static struct clk dpll4_m5_ck = {
843 .name = "dpll4_m5_ck",
844 .ops = &clkops_null,
845 .parent = &dpll4_ck,
846 .init = &omap2_init_clksel_parent,
847 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
848 .clksel_mask = OMAP3630_CLKSEL_CAM_MASK,
849 .clksel = dpll4_clksel,
850 .clkdm_name = "dpll4_clkdm",
851 .set_rate = &omap2_clksel_set_rate,
852 .round_rate = &omap2_clksel_round_rate,
853 .recalc = &omap2_clksel_recalc,
854};
855
856/* The PWRDN bit is apparently only available on 3430ES2 and above */
857static struct clk dpll4_m5x2_ck = {
858 .name = "dpll4_m5x2_ck",
859 .ops = &clkops_omap2_dflt_wait,
860 .parent = &dpll4_m5_ck,
861 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
862 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
863 .flags = INVERT_ENABLE,
864 .clkdm_name = "dpll4_clkdm",
865 .recalc = &omap3_clkoutx2_recalc,
866};
867
868/* This virtual clock is the source for dpll4_m6x2_ck */
869static struct clk dpll4_m6_ck = {
870 .name = "dpll4_m6_ck",
871 .ops = &clkops_null,
872 .parent = &dpll4_ck,
873 .init = &omap2_init_clksel_parent,
874 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
875 .clksel_mask = OMAP3630_DIV_DPLL4_MASK,
876 .clksel = dpll4_clksel,
877 .clkdm_name = "dpll4_clkdm",
878 .recalc = &omap2_clksel_recalc,
879};
880
881/* The PWRDN bit is apparently only available on 3430ES2 and above */
882static struct clk dpll4_m6x2_ck = {
883 .name = "dpll4_m6x2_ck",
884 .ops = &clkops_omap2_dflt_wait,
885 .parent = &dpll4_m6_ck,
886 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
887 .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
888 .flags = INVERT_ENABLE,
889 .clkdm_name = "dpll4_clkdm",
890 .recalc = &omap3_clkoutx2_recalc,
891};
892
893static struct clk emu_per_alwon_ck = {
894 .name = "emu_per_alwon_ck",
895 .ops = &clkops_null,
896 .parent = &dpll4_m6x2_ck,
897 .clkdm_name = "dpll4_clkdm",
898 .recalc = &followparent_recalc,
899};
900
901/* DPLL5 */
902/* Supplies 120MHz clock, USIM source clock */
903/* Type: DPLL */
904/* 3430ES2 only */
905static struct dpll_data dpll5_dd = {
906 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
907 .mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
908 .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
909 .clk_bypass = &sys_ck,
910 .clk_ref = &sys_ck,
911 .freqsel_mask = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
912 .control_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
913 .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
914 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
915 .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
916 .recal_en_bit = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
917 .recal_st_bit = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
918 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
919 .autoidle_mask = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
920 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
921 .idlest_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
922 .max_multiplier = OMAP3_MAX_DPLL_MULT,
923 .min_divider = 1,
924 .max_divider = OMAP3_MAX_DPLL_DIV,
925};
926
927static struct clk dpll5_ck = {
928 .name = "dpll5_ck",
929 .ops = &clkops_omap3_noncore_dpll_ops,
930 .parent = &sys_ck,
931 .dpll_data = &dpll5_dd,
932 .round_rate = &omap2_dpll_round_rate,
933 .set_rate = &omap3_noncore_dpll_set_rate,
934 .clkdm_name = "dpll5_clkdm",
935 .recalc = &omap3_dpll_recalc,
936};
937
938static const struct clksel div16_dpll5_clksel[] = {
939 { .parent = &dpll5_ck, .rates = div16_dpll_rates },
940 { .parent = NULL }
941};
942
943static struct clk dpll5_m2_ck = {
944 .name = "dpll5_m2_ck",
945 .ops = &clkops_null,
946 .parent = &dpll5_ck,
947 .init = &omap2_init_clksel_parent,
948 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
949 .clksel_mask = OMAP3430ES2_DIV_120M_MASK,
950 .clksel = div16_dpll5_clksel,
951 .clkdm_name = "dpll5_clkdm",
952 .recalc = &omap2_clksel_recalc,
953};
954
955/* CM EXTERNAL CLOCK OUTPUTS */
956
957static const struct clksel_rate clkout2_src_core_rates[] = {
958 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
959 { .div = 0 }
960};
961
962static const struct clksel_rate clkout2_src_sys_rates[] = {
963 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
964 { .div = 0 }
965};
966
967static const struct clksel_rate clkout2_src_96m_rates[] = {
968 { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
969 { .div = 0 }
970};
971
972static const struct clksel_rate clkout2_src_54m_rates[] = {
973 { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
974 { .div = 0 }
975};
976
977static const struct clksel clkout2_src_clksel[] = {
978 { .parent = &core_ck, .rates = clkout2_src_core_rates },
979 { .parent = &sys_ck, .rates = clkout2_src_sys_rates },
980 { .parent = &cm_96m_fck, .rates = clkout2_src_96m_rates },
981 { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates },
982 { .parent = NULL }
983};
984
985static struct clk clkout2_src_ck = {
986 .name = "clkout2_src_ck",
987 .ops = &clkops_omap2_dflt,
988 .init = &omap2_init_clksel_parent,
989 .enable_reg = OMAP3430_CM_CLKOUT_CTRL,
990 .enable_bit = OMAP3430_CLKOUT2_EN_SHIFT,
991 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL,
992 .clksel_mask = OMAP3430_CLKOUT2SOURCE_MASK,
993 .clksel = clkout2_src_clksel,
994 .clkdm_name = "core_clkdm",
995 .recalc = &omap2_clksel_recalc,
996};
997
998static const struct clksel_rate sys_clkout2_rates[] = {
999 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
1000 { .div = 2, .val = 1, .flags = RATE_IN_3XXX },
1001 { .div = 4, .val = 2, .flags = RATE_IN_3XXX },
1002 { .div = 8, .val = 3, .flags = RATE_IN_3XXX },
1003 { .div = 16, .val = 4, .flags = RATE_IN_3XXX },
1004 { .div = 0 },
1005};
1006
1007static const struct clksel sys_clkout2_clksel[] = {
1008 { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
1009 { .parent = NULL },
1010};
1011
1012static struct clk sys_clkout2 = {
1013 .name = "sys_clkout2",
1014 .ops = &clkops_null,
1015 .init = &omap2_init_clksel_parent,
1016 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL,
1017 .clksel_mask = OMAP3430_CLKOUT2_DIV_MASK,
1018 .clksel = sys_clkout2_clksel,
1019 .recalc = &omap2_clksel_recalc,
1020 .round_rate = &omap2_clksel_round_rate,
1021 .set_rate = &omap2_clksel_set_rate
1022};
1023
1024/* CM OUTPUT CLOCKS */
1025
1026static struct clk corex2_fck = {
1027 .name = "corex2_fck",
1028 .ops = &clkops_null,
1029 .parent = &dpll3_m2x2_ck,
1030 .recalc = &followparent_recalc,
1031};
1032
1033/* DPLL power domain clock controls */
1034
1035static const struct clksel_rate div4_rates[] = {
1036 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
1037 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
1038 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
1039 { .div = 0 }
1040};
1041
1042static const struct clksel div4_core_clksel[] = {
1043 { .parent = &core_ck, .rates = div4_rates },
1044 { .parent = NULL }
1045};
1046
1047/*
1048 * REVISIT: Are these in DPLL power domain or CM power domain? docs
1049 * may be inconsistent here?
1050 */
1051static struct clk dpll1_fck = {
1052 .name = "dpll1_fck",
1053 .ops = &clkops_null,
1054 .parent = &core_ck,
1055 .init = &omap2_init_clksel_parent,
1056 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
1057 .clksel_mask = OMAP3430_MPU_CLK_SRC_MASK,
1058 .clksel = div4_core_clksel,
1059 .recalc = &omap2_clksel_recalc,
1060};
1061
1062static struct clk mpu_ck = {
1063 .name = "mpu_ck",
1064 .ops = &clkops_null,
1065 .parent = &dpll1_x2m2_ck,
1066 .clkdm_name = "mpu_clkdm",
1067 .recalc = &followparent_recalc,
1068};
1069
1070/* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
1071static const struct clksel_rate arm_fck_rates[] = {
1072 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
1073 { .div = 2, .val = 1, .flags = RATE_IN_3XXX },
1074 { .div = 0 },
1075};
1076
1077static const struct clksel arm_fck_clksel[] = {
1078 { .parent = &mpu_ck, .rates = arm_fck_rates },
1079 { .parent = NULL }
1080};
1081
1082static struct clk arm_fck = {
1083 .name = "arm_fck",
1084 .ops = &clkops_null,
1085 .parent = &mpu_ck,
1086 .init = &omap2_init_clksel_parent,
1087 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1088 .clksel_mask = OMAP3430_ST_MPU_CLK_MASK,
1089 .clksel = arm_fck_clksel,
1090 .clkdm_name = "mpu_clkdm",
1091 .recalc = &omap2_clksel_recalc,
1092};
1093
1094/* XXX What about neon_clkdm ? */
1095
1096/*
1097 * REVISIT: This clock is never specifically defined in the 3430 TRM,
1098 * although it is referenced - so this is a guess
1099 */
1100static struct clk emu_mpu_alwon_ck = {
1101 .name = "emu_mpu_alwon_ck",
1102 .ops = &clkops_null,
1103 .parent = &mpu_ck,
1104 .recalc = &followparent_recalc,
1105};
1106
1107static struct clk dpll2_fck = {
1108 .name = "dpll2_fck",
1109 .ops = &clkops_null,
1110 .parent = &core_ck,
1111 .init = &omap2_init_clksel_parent,
1112 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
1113 .clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK,
1114 .clksel = div4_core_clksel,
1115 .recalc = &omap2_clksel_recalc,
1116};
1117
1118static struct clk iva2_ck = {
1119 .name = "iva2_ck",
1120 .ops = &clkops_omap2_dflt_wait,
1121 .parent = &dpll2_m2_ck,
1122 .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
1123 .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1124 .clkdm_name = "iva2_clkdm",
1125 .recalc = &followparent_recalc,
1126};
1127
1128/* Common interface clocks */
1129
1130static const struct clksel div2_core_clksel[] = {
1131 { .parent = &core_ck, .rates = div2_rates },
1132 { .parent = NULL }
1133};
1134
1135static struct clk l3_ick = {
1136 .name = "l3_ick",
1137 .ops = &clkops_null,
1138 .parent = &core_ck,
1139 .init = &omap2_init_clksel_parent,
1140 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1141 .clksel_mask = OMAP3430_CLKSEL_L3_MASK,
1142 .clksel = div2_core_clksel,
1143 .clkdm_name = "core_l3_clkdm",
1144 .recalc = &omap2_clksel_recalc,
1145};
1146
1147static const struct clksel div2_l3_clksel[] = {
1148 { .parent = &l3_ick, .rates = div2_rates },
1149 { .parent = NULL }
1150};
1151
1152static struct clk l4_ick = {
1153 .name = "l4_ick",
1154 .ops = &clkops_null,
1155 .parent = &l3_ick,
1156 .init = &omap2_init_clksel_parent,
1157 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1158 .clksel_mask = OMAP3430_CLKSEL_L4_MASK,
1159 .clksel = div2_l3_clksel,
1160 .clkdm_name = "core_l4_clkdm",
1161 .recalc = &omap2_clksel_recalc,
1162
1163};
1164
1165static const struct clksel div2_l4_clksel[] = {
1166 { .parent = &l4_ick, .rates = div2_rates },
1167 { .parent = NULL }
1168};
1169
1170static struct clk rm_ick = {
1171 .name = "rm_ick",
1172 .ops = &clkops_null,
1173 .parent = &l4_ick,
1174 .init = &omap2_init_clksel_parent,
1175 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1176 .clksel_mask = OMAP3430_CLKSEL_RM_MASK,
1177 .clksel = div2_l4_clksel,
1178 .recalc = &omap2_clksel_recalc,
1179};
1180
1181/* GFX power domain */
1182
1183/* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
1184
1185static const struct clksel gfx_l3_clksel[] = {
1186 { .parent = &l3_ick, .rates = gfx_l3_rates },
1187 { .parent = NULL }
1188};
1189
1190/*
1191 * Virtual parent clock for gfx_l3_ick and gfx_l3_fck
1192 * This interface clock does not have a CM_AUTOIDLE bit
1193 */
1194static struct clk gfx_l3_ck = {
1195 .name = "gfx_l3_ck",
1196 .ops = &clkops_omap2_dflt_wait,
1197 .parent = &l3_ick,
1198 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1199 .enable_bit = OMAP_EN_GFX_SHIFT,
1200 .recalc = &followparent_recalc,
1201};
1202
1203static struct clk gfx_l3_fck = {
1204 .name = "gfx_l3_fck",
1205 .ops = &clkops_null,
1206 .parent = &gfx_l3_ck,
1207 .init = &omap2_init_clksel_parent,
1208 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1209 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
1210 .clksel = gfx_l3_clksel,
1211 .clkdm_name = "gfx_3430es1_clkdm",
1212 .recalc = &omap2_clksel_recalc,
1213};
1214
1215static struct clk gfx_l3_ick = {
1216 .name = "gfx_l3_ick",
1217 .ops = &clkops_null,
1218 .parent = &gfx_l3_ck,
1219 .clkdm_name = "gfx_3430es1_clkdm",
1220 .recalc = &followparent_recalc,
1221};
1222
1223static struct clk gfx_cg1_ck = {
1224 .name = "gfx_cg1_ck",
1225 .ops = &clkops_omap2_dflt_wait,
1226 .parent = &gfx_l3_fck, /* REVISIT: correct? */
1227 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1228 .enable_bit = OMAP3430ES1_EN_2D_SHIFT,
1229 .clkdm_name = "gfx_3430es1_clkdm",
1230 .recalc = &followparent_recalc,
1231};
1232
1233static struct clk gfx_cg2_ck = {
1234 .name = "gfx_cg2_ck",
1235 .ops = &clkops_omap2_dflt_wait,
1236 .parent = &gfx_l3_fck, /* REVISIT: correct? */
1237 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1238 .enable_bit = OMAP3430ES1_EN_3D_SHIFT,
1239 .clkdm_name = "gfx_3430es1_clkdm",
1240 .recalc = &followparent_recalc,
1241};
1242
1243/* SGX power domain - 3430ES2 only */
1244
1245static const struct clksel_rate sgx_core_rates[] = {
1246 { .div = 2, .val = 5, .flags = RATE_IN_36XX },
1247 { .div = 3, .val = 0, .flags = RATE_IN_3XXX },
1248 { .div = 4, .val = 1, .flags = RATE_IN_3XXX },
1249 { .div = 6, .val = 2, .flags = RATE_IN_3XXX },
1250 { .div = 0 },
1251};
1252
1253static const struct clksel_rate sgx_192m_rates[] = {
1254 { .div = 1, .val = 4, .flags = RATE_IN_36XX },
1255 { .div = 0 },
1256};
1257
1258static const struct clksel_rate sgx_corex2_rates[] = {
1259 { .div = 3, .val = 6, .flags = RATE_IN_36XX },
1260 { .div = 5, .val = 7, .flags = RATE_IN_36XX },
1261 { .div = 0 },
1262};
1263
1264static const struct clksel_rate sgx_96m_rates[] = {
1265 { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
1266 { .div = 0 },
1267};
1268
1269static const struct clksel sgx_clksel[] = {
1270 { .parent = &core_ck, .rates = sgx_core_rates },
1271 { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
1272 { .parent = &omap_192m_alwon_fck, .rates = sgx_192m_rates },
1273 { .parent = &corex2_fck, .rates = sgx_corex2_rates },
1274 { .parent = NULL }
1275};
1276
1277static struct clk sgx_fck = {
1278 .name = "sgx_fck",
1279 .ops = &clkops_omap2_dflt_wait,
1280 .init = &omap2_init_clksel_parent,
1281 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
1282 .enable_bit = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
1283 .clksel_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
1284 .clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK,
1285 .clksel = sgx_clksel,
1286 .clkdm_name = "sgx_clkdm",
1287 .recalc = &omap2_clksel_recalc,
1288 .set_rate = &omap2_clksel_set_rate,
1289 .round_rate = &omap2_clksel_round_rate
1290};
1291
1292/* This interface clock does not have a CM_AUTOIDLE bit */
1293static struct clk sgx_ick = {
1294 .name = "sgx_ick",
1295 .ops = &clkops_omap2_dflt_wait,
1296 .parent = &l3_ick,
1297 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
1298 .enable_bit = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
1299 .clkdm_name = "sgx_clkdm",
1300 .recalc = &followparent_recalc,
1301};
1302
1303/* CORE power domain */
1304
1305static struct clk d2d_26m_fck = {
1306 .name = "d2d_26m_fck",
1307 .ops = &clkops_omap2_dflt_wait,
1308 .parent = &sys_ck,
1309 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1310 .enable_bit = OMAP3430ES1_EN_D2D_SHIFT,
1311 .clkdm_name = "d2d_clkdm",
1312 .recalc = &followparent_recalc,
1313};
1314
1315static struct clk modem_fck = {
1316 .name = "modem_fck",
1317 .ops = &clkops_omap2_mdmclk_dflt_wait,
1318 .parent = &sys_ck,
1319 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1320 .enable_bit = OMAP3430_EN_MODEM_SHIFT,
1321 .clkdm_name = "d2d_clkdm",
1322 .recalc = &followparent_recalc,
1323};
1324
1325static struct clk sad2d_ick = {
1326 .name = "sad2d_ick",
1327 .ops = &clkops_omap2_iclk_dflt_wait,
1328 .parent = &l3_ick,
1329 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1330 .enable_bit = OMAP3430_EN_SAD2D_SHIFT,
1331 .clkdm_name = "d2d_clkdm",
1332 .recalc = &followparent_recalc,
1333};
1334
1335static struct clk mad2d_ick = {
1336 .name = "mad2d_ick",
1337 .ops = &clkops_omap2_iclk_dflt_wait,
1338 .parent = &l3_ick,
1339 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1340 .enable_bit = OMAP3430_EN_MAD2D_SHIFT,
1341 .clkdm_name = "d2d_clkdm",
1342 .recalc = &followparent_recalc,
1343};
1344
1345static const struct clksel omap343x_gpt_clksel[] = {
1346 { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1347 { .parent = &sys_ck, .rates = gpt_sys_rates },
1348 { .parent = NULL}
1349};
1350
1351static struct clk gpt10_fck = {
1352 .name = "gpt10_fck",
1353 .ops = &clkops_omap2_dflt_wait,
1354 .parent = &sys_ck,
1355 .init = &omap2_init_clksel_parent,
1356 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1357 .enable_bit = OMAP3430_EN_GPT10_SHIFT,
1358 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1359 .clksel_mask = OMAP3430_CLKSEL_GPT10_MASK,
1360 .clksel = omap343x_gpt_clksel,
1361 .clkdm_name = "core_l4_clkdm",
1362 .recalc = &omap2_clksel_recalc,
1363};
1364
1365static struct clk gpt11_fck = {
1366 .name = "gpt11_fck",
1367 .ops = &clkops_omap2_dflt_wait,
1368 .parent = &sys_ck,
1369 .init = &omap2_init_clksel_parent,
1370 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1371 .enable_bit = OMAP3430_EN_GPT11_SHIFT,
1372 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1373 .clksel_mask = OMAP3430_CLKSEL_GPT11_MASK,
1374 .clksel = omap343x_gpt_clksel,
1375 .clkdm_name = "core_l4_clkdm",
1376 .recalc = &omap2_clksel_recalc,
1377};
1378
1379static struct clk cpefuse_fck = {
1380 .name = "cpefuse_fck",
1381 .ops = &clkops_omap2_dflt,
1382 .parent = &sys_ck,
1383 .clkdm_name = "core_l4_clkdm",
1384 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1385 .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT,
1386 .recalc = &followparent_recalc,
1387};
1388
1389static struct clk ts_fck = {
1390 .name = "ts_fck",
1391 .ops = &clkops_omap2_dflt,
1392 .parent = &omap_32k_fck,
1393 .clkdm_name = "core_l4_clkdm",
1394 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1395 .enable_bit = OMAP3430ES2_EN_TS_SHIFT,
1396 .recalc = &followparent_recalc,
1397};
1398
1399static struct clk usbtll_fck = {
1400 .name = "usbtll_fck",
1401 .ops = &clkops_omap2_dflt_wait,
1402 .parent = &dpll5_m2_ck,
1403 .clkdm_name = "core_l4_clkdm",
1404 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1405 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1406 .recalc = &followparent_recalc,
1407};
1408
1409/* CORE 96M FCLK-derived clocks */
1410
1411static struct clk core_96m_fck = {
1412 .name = "core_96m_fck",
1413 .ops = &clkops_null,
1414 .parent = &omap_96m_fck,
1415 .clkdm_name = "core_l4_clkdm",
1416 .recalc = &followparent_recalc,
1417};
1418
1419static struct clk mmchs3_fck = {
1420 .name = "mmchs3_fck",
1421 .ops = &clkops_omap2_dflt_wait,
1422 .parent = &core_96m_fck,
1423 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1424 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
1425 .clkdm_name = "core_l4_clkdm",
1426 .recalc = &followparent_recalc,
1427};
1428
1429static struct clk mmchs2_fck = {
1430 .name = "mmchs2_fck",
1431 .ops = &clkops_omap2_dflt_wait,
1432 .parent = &core_96m_fck,
1433 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1434 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
1435 .clkdm_name = "core_l4_clkdm",
1436 .recalc = &followparent_recalc,
1437};
1438
1439static struct clk mspro_fck = {
1440 .name = "mspro_fck",
1441 .ops = &clkops_omap2_dflt_wait,
1442 .parent = &core_96m_fck,
1443 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1444 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
1445 .clkdm_name = "core_l4_clkdm",
1446 .recalc = &followparent_recalc,
1447};
1448
1449static struct clk mmchs1_fck = {
1450 .name = "mmchs1_fck",
1451 .ops = &clkops_omap2_dflt_wait,
1452 .parent = &core_96m_fck,
1453 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1454 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
1455 .clkdm_name = "core_l4_clkdm",
1456 .recalc = &followparent_recalc,
1457};
1458
1459static struct clk i2c3_fck = {
1460 .name = "i2c3_fck",
1461 .ops = &clkops_omap2_dflt_wait,
1462 .parent = &core_96m_fck,
1463 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1464 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
1465 .clkdm_name = "core_l4_clkdm",
1466 .recalc = &followparent_recalc,
1467};
1468
1469static struct clk i2c2_fck = {
1470 .name = "i2c2_fck",
1471 .ops = &clkops_omap2_dflt_wait,
1472 .parent = &core_96m_fck,
1473 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1474 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
1475 .clkdm_name = "core_l4_clkdm",
1476 .recalc = &followparent_recalc,
1477};
1478
1479static struct clk i2c1_fck = {
1480 .name = "i2c1_fck",
1481 .ops = &clkops_omap2_dflt_wait,
1482 .parent = &core_96m_fck,
1483 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1484 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
1485 .clkdm_name = "core_l4_clkdm",
1486 .recalc = &followparent_recalc,
1487};
1488
1489/*
1490 * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1491 * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1492 */
1493static const struct clksel_rate common_mcbsp_96m_rates[] = {
1494 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
1495 { .div = 0 }
1496};
1497
1498static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1499 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
1500 { .div = 0 }
1501};
1502
1503static const struct clksel mcbsp_15_clksel[] = {
1504 { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
1505 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
1506 { .parent = NULL }
1507};
1508
1509static struct clk mcbsp5_fck = {
1510 .name = "mcbsp5_fck",
1511 .ops = &clkops_omap2_dflt_wait,
1512 .init = &omap2_init_clksel_parent,
1513 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1514 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
1515 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
1516 .clksel_mask = OMAP2_MCBSP5_CLKS_MASK,
1517 .clksel = mcbsp_15_clksel,
1518 .clkdm_name = "core_l4_clkdm",
1519 .recalc = &omap2_clksel_recalc,
1520};
1521
1522static struct clk mcbsp1_fck = {
1523 .name = "mcbsp1_fck",
1524 .ops = &clkops_omap2_dflt_wait,
1525 .init = &omap2_init_clksel_parent,
1526 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1527 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
1528 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1529 .clksel_mask = OMAP2_MCBSP1_CLKS_MASK,
1530 .clksel = mcbsp_15_clksel,
1531 .clkdm_name = "core_l4_clkdm",
1532 .recalc = &omap2_clksel_recalc,
1533};
1534
1535/* CORE_48M_FCK-derived clocks */
1536
1537static struct clk core_48m_fck = {
1538 .name = "core_48m_fck",
1539 .ops = &clkops_null,
1540 .parent = &omap_48m_fck,
1541 .clkdm_name = "core_l4_clkdm",
1542 .recalc = &followparent_recalc,
1543};
1544
1545static struct clk mcspi4_fck = {
1546 .name = "mcspi4_fck",
1547 .ops = &clkops_omap2_dflt_wait,
1548 .parent = &core_48m_fck,
1549 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1550 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
1551 .recalc = &followparent_recalc,
1552 .clkdm_name = "core_l4_clkdm",
1553};
1554
1555static struct clk mcspi3_fck = {
1556 .name = "mcspi3_fck",
1557 .ops = &clkops_omap2_dflt_wait,
1558 .parent = &core_48m_fck,
1559 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1560 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
1561 .recalc = &followparent_recalc,
1562 .clkdm_name = "core_l4_clkdm",
1563};
1564
1565static struct clk mcspi2_fck = {
1566 .name = "mcspi2_fck",
1567 .ops = &clkops_omap2_dflt_wait,
1568 .parent = &core_48m_fck,
1569 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1570 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
1571 .recalc = &followparent_recalc,
1572 .clkdm_name = "core_l4_clkdm",
1573};
1574
1575static struct clk mcspi1_fck = {
1576 .name = "mcspi1_fck",
1577 .ops = &clkops_omap2_dflt_wait,
1578 .parent = &core_48m_fck,
1579 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1580 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
1581 .recalc = &followparent_recalc,
1582 .clkdm_name = "core_l4_clkdm",
1583};
1584
1585static struct clk uart2_fck = {
1586 .name = "uart2_fck",
1587 .ops = &clkops_omap2_dflt_wait,
1588 .parent = &core_48m_fck,
1589 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1590 .enable_bit = OMAP3430_EN_UART2_SHIFT,
1591 .clkdm_name = "core_l4_clkdm",
1592 .recalc = &followparent_recalc,
1593};
1594
1595static struct clk uart1_fck = {
1596 .name = "uart1_fck",
1597 .ops = &clkops_omap2_dflt_wait,
1598 .parent = &core_48m_fck,
1599 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1600 .enable_bit = OMAP3430_EN_UART1_SHIFT,
1601 .clkdm_name = "core_l4_clkdm",
1602 .recalc = &followparent_recalc,
1603};
1604
1605static struct clk fshostusb_fck = {
1606 .name = "fshostusb_fck",
1607 .ops = &clkops_omap2_dflt_wait,
1608 .parent = &core_48m_fck,
1609 .clkdm_name = "core_l4_clkdm",
1610 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1611 .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1612 .recalc = &followparent_recalc,
1613};
1614
1615/* CORE_12M_FCK based clocks */
1616
1617static struct clk core_12m_fck = {
1618 .name = "core_12m_fck",
1619 .ops = &clkops_null,
1620 .parent = &omap_12m_fck,
1621 .clkdm_name = "core_l4_clkdm",
1622 .recalc = &followparent_recalc,
1623};
1624
1625static struct clk hdq_fck = {
1626 .name = "hdq_fck",
1627 .ops = &clkops_omap2_dflt_wait,
1628 .parent = &core_12m_fck,
1629 .clkdm_name = "core_l4_clkdm",
1630 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1631 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1632 .recalc = &followparent_recalc,
1633};
1634
1635/* DPLL3-derived clock */
1636
1637static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1638 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
1639 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
1640 { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
1641 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
1642 { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
1643 { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
1644 { .div = 0 }
1645};
1646
1647static const struct clksel ssi_ssr_clksel[] = {
1648 { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1649 { .parent = NULL }
1650};
1651
1652static struct clk ssi_ssr_fck_3430es1 = {
1653 .name = "ssi_ssr_fck",
1654 .ops = &clkops_omap2_dflt,
1655 .init = &omap2_init_clksel_parent,
1656 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1657 .enable_bit = OMAP3430_EN_SSI_SHIFT,
1658 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1659 .clksel_mask = OMAP3430_CLKSEL_SSI_MASK,
1660 .clksel = ssi_ssr_clksel,
1661 .clkdm_name = "core_l4_clkdm",
1662 .recalc = &omap2_clksel_recalc,
1663};
1664
1665static struct clk ssi_ssr_fck_3430es2 = {
1666 .name = "ssi_ssr_fck",
1667 .ops = &clkops_omap3430es2_ssi_wait,
1668 .init = &omap2_init_clksel_parent,
1669 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1670 .enable_bit = OMAP3430_EN_SSI_SHIFT,
1671 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1672 .clksel_mask = OMAP3430_CLKSEL_SSI_MASK,
1673 .clksel = ssi_ssr_clksel,
1674 .clkdm_name = "core_l4_clkdm",
1675 .recalc = &omap2_clksel_recalc,
1676};
1677
1678static struct clk ssi_sst_fck_3430es1 = {
1679 .name = "ssi_sst_fck",
1680 .ops = &clkops_null,
1681 .parent = &ssi_ssr_fck_3430es1,
1682 .fixed_div = 2,
1683 .recalc = &omap_fixed_divisor_recalc,
1684};
1685
1686static struct clk ssi_sst_fck_3430es2 = {
1687 .name = "ssi_sst_fck",
1688 .ops = &clkops_null,
1689 .parent = &ssi_ssr_fck_3430es2,
1690 .fixed_div = 2,
1691 .recalc = &omap_fixed_divisor_recalc,
1692};
1693
1694
1695
1696/* CORE_L3_ICK based clocks */
1697
1698/*
1699 * XXX must add clk_enable/clk_disable for these if standard code won't
1700 * handle it
1701 */
1702static struct clk core_l3_ick = {
1703 .name = "core_l3_ick",
1704 .ops = &clkops_null,
1705 .parent = &l3_ick,
1706 .clkdm_name = "core_l3_clkdm",
1707 .recalc = &followparent_recalc,
1708};
1709
1710static struct clk hsotgusb_ick_3430es1 = {
1711 .name = "hsotgusb_ick",
1712 .ops = &clkops_omap2_iclk_dflt,
1713 .parent = &core_l3_ick,
1714 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1715 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1716 .clkdm_name = "core_l3_clkdm",
1717 .recalc = &followparent_recalc,
1718};
1719
1720static struct clk hsotgusb_ick_3430es2 = {
1721 .name = "hsotgusb_ick",
1722 .ops = &clkops_omap3430es2_iclk_hsotgusb_wait,
1723 .parent = &core_l3_ick,
1724 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1725 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1726 .clkdm_name = "core_l3_clkdm",
1727 .recalc = &followparent_recalc,
1728};
1729
1730/* This interface clock does not have a CM_AUTOIDLE bit */
1731static struct clk sdrc_ick = {
1732 .name = "sdrc_ick",
1733 .ops = &clkops_omap2_dflt_wait,
1734 .parent = &core_l3_ick,
1735 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1736 .enable_bit = OMAP3430_EN_SDRC_SHIFT,
1737 .flags = ENABLE_ON_INIT,
1738 .clkdm_name = "core_l3_clkdm",
1739 .recalc = &followparent_recalc,
1740};
1741
1742static struct clk gpmc_fck = {
1743 .name = "gpmc_fck",
1744 .ops = &clkops_null,
1745 .parent = &core_l3_ick,
1746 .flags = ENABLE_ON_INIT, /* huh? */
1747 .clkdm_name = "core_l3_clkdm",
1748 .recalc = &followparent_recalc,
1749};
1750
1751/* SECURITY_L3_ICK based clocks */
1752
1753static struct clk security_l3_ick = {
1754 .name = "security_l3_ick",
1755 .ops = &clkops_null,
1756 .parent = &l3_ick,
1757 .recalc = &followparent_recalc,
1758};
1759
1760static struct clk pka_ick = {
1761 .name = "pka_ick",
1762 .ops = &clkops_omap2_iclk_dflt_wait,
1763 .parent = &security_l3_ick,
1764 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1765 .enable_bit = OMAP3430_EN_PKA_SHIFT,
1766 .recalc = &followparent_recalc,
1767};
1768
1769/* CORE_L4_ICK based clocks */
1770
1771static struct clk core_l4_ick = {
1772 .name = "core_l4_ick",
1773 .ops = &clkops_null,
1774 .parent = &l4_ick,
1775 .clkdm_name = "core_l4_clkdm",
1776 .recalc = &followparent_recalc,
1777};
1778
1779static struct clk usbtll_ick = {
1780 .name = "usbtll_ick",
1781 .ops = &clkops_omap2_iclk_dflt_wait,
1782 .parent = &core_l4_ick,
1783 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1784 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1785 .clkdm_name = "core_l4_clkdm",
1786 .recalc = &followparent_recalc,
1787};
1788
1789static struct clk mmchs3_ick = {
1790 .name = "mmchs3_ick",
1791 .ops = &clkops_omap2_iclk_dflt_wait,
1792 .parent = &core_l4_ick,
1793 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1794 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
1795 .clkdm_name = "core_l4_clkdm",
1796 .recalc = &followparent_recalc,
1797};
1798
1799/* Intersystem Communication Registers - chassis mode only */
1800static struct clk icr_ick = {
1801 .name = "icr_ick",
1802 .ops = &clkops_omap2_iclk_dflt_wait,
1803 .parent = &core_l4_ick,
1804 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1805 .enable_bit = OMAP3430_EN_ICR_SHIFT,
1806 .clkdm_name = "core_l4_clkdm",
1807 .recalc = &followparent_recalc,
1808};
1809
1810static struct clk aes2_ick = {
1811 .name = "aes2_ick",
1812 .ops = &clkops_omap2_iclk_dflt_wait,
1813 .parent = &core_l4_ick,
1814 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1815 .enable_bit = OMAP3430_EN_AES2_SHIFT,
1816 .clkdm_name = "core_l4_clkdm",
1817 .recalc = &followparent_recalc,
1818};
1819
1820static struct clk sha12_ick = {
1821 .name = "sha12_ick",
1822 .ops = &clkops_omap2_iclk_dflt_wait,
1823 .parent = &core_l4_ick,
1824 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1825 .enable_bit = OMAP3430_EN_SHA12_SHIFT,
1826 .clkdm_name = "core_l4_clkdm",
1827 .recalc = &followparent_recalc,
1828};
1829
1830static struct clk des2_ick = {
1831 .name = "des2_ick",
1832 .ops = &clkops_omap2_iclk_dflt_wait,
1833 .parent = &core_l4_ick,
1834 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1835 .enable_bit = OMAP3430_EN_DES2_SHIFT,
1836 .clkdm_name = "core_l4_clkdm",
1837 .recalc = &followparent_recalc,
1838};
1839
1840static struct clk mmchs2_ick = {
1841 .name = "mmchs2_ick",
1842 .ops = &clkops_omap2_iclk_dflt_wait,
1843 .parent = &core_l4_ick,
1844 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1845 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
1846 .clkdm_name = "core_l4_clkdm",
1847 .recalc = &followparent_recalc,
1848};
1849
1850static struct clk mmchs1_ick = {
1851 .name = "mmchs1_ick",
1852 .ops = &clkops_omap2_iclk_dflt_wait,
1853 .parent = &core_l4_ick,
1854 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1855 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
1856 .clkdm_name = "core_l4_clkdm",
1857 .recalc = &followparent_recalc,
1858};
1859
1860static struct clk mspro_ick = {
1861 .name = "mspro_ick",
1862 .ops = &clkops_omap2_iclk_dflt_wait,
1863 .parent = &core_l4_ick,
1864 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1865 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
1866 .clkdm_name = "core_l4_clkdm",
1867 .recalc = &followparent_recalc,
1868};
1869
1870static struct clk hdq_ick = {
1871 .name = "hdq_ick",
1872 .ops = &clkops_omap2_iclk_dflt_wait,
1873 .parent = &core_l4_ick,
1874 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1875 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1876 .clkdm_name = "core_l4_clkdm",
1877 .recalc = &followparent_recalc,
1878};
1879
1880static struct clk mcspi4_ick = {
1881 .name = "mcspi4_ick",
1882 .ops = &clkops_omap2_iclk_dflt_wait,
1883 .parent = &core_l4_ick,
1884 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1885 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
1886 .clkdm_name = "core_l4_clkdm",
1887 .recalc = &followparent_recalc,
1888};
1889
1890static struct clk mcspi3_ick = {
1891 .name = "mcspi3_ick",
1892 .ops = &clkops_omap2_iclk_dflt_wait,
1893 .parent = &core_l4_ick,
1894 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1895 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
1896 .clkdm_name = "core_l4_clkdm",
1897 .recalc = &followparent_recalc,
1898};
1899
1900static struct clk mcspi2_ick = {
1901 .name = "mcspi2_ick",
1902 .ops = &clkops_omap2_iclk_dflt_wait,
1903 .parent = &core_l4_ick,
1904 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1905 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
1906 .clkdm_name = "core_l4_clkdm",
1907 .recalc = &followparent_recalc,
1908};
1909
1910static struct clk mcspi1_ick = {
1911 .name = "mcspi1_ick",
1912 .ops = &clkops_omap2_iclk_dflt_wait,
1913 .parent = &core_l4_ick,
1914 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1915 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
1916 .clkdm_name = "core_l4_clkdm",
1917 .recalc = &followparent_recalc,
1918};
1919
1920static struct clk i2c3_ick = {
1921 .name = "i2c3_ick",
1922 .ops = &clkops_omap2_iclk_dflt_wait,
1923 .parent = &core_l4_ick,
1924 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1925 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
1926 .clkdm_name = "core_l4_clkdm",
1927 .recalc = &followparent_recalc,
1928};
1929
1930static struct clk i2c2_ick = {
1931 .name = "i2c2_ick",
1932 .ops = &clkops_omap2_iclk_dflt_wait,
1933 .parent = &core_l4_ick,
1934 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1935 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
1936 .clkdm_name = "core_l4_clkdm",
1937 .recalc = &followparent_recalc,
1938};
1939
1940static struct clk i2c1_ick = {
1941 .name = "i2c1_ick",
1942 .ops = &clkops_omap2_iclk_dflt_wait,
1943 .parent = &core_l4_ick,
1944 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1945 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
1946 .clkdm_name = "core_l4_clkdm",
1947 .recalc = &followparent_recalc,
1948};
1949
1950static struct clk uart2_ick = {
1951 .name = "uart2_ick",
1952 .ops = &clkops_omap2_iclk_dflt_wait,
1953 .parent = &core_l4_ick,
1954 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1955 .enable_bit = OMAP3430_EN_UART2_SHIFT,
1956 .clkdm_name = "core_l4_clkdm",
1957 .recalc = &followparent_recalc,
1958};
1959
1960static struct clk uart1_ick = {
1961 .name = "uart1_ick",
1962 .ops = &clkops_omap2_iclk_dflt_wait,
1963 .parent = &core_l4_ick,
1964 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1965 .enable_bit = OMAP3430_EN_UART1_SHIFT,
1966 .clkdm_name = "core_l4_clkdm",
1967 .recalc = &followparent_recalc,
1968};
1969
1970static struct clk gpt11_ick = {
1971 .name = "gpt11_ick",
1972 .ops = &clkops_omap2_iclk_dflt_wait,
1973 .parent = &core_l4_ick,
1974 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1975 .enable_bit = OMAP3430_EN_GPT11_SHIFT,
1976 .clkdm_name = "core_l4_clkdm",
1977 .recalc = &followparent_recalc,
1978};
1979
1980static struct clk gpt10_ick = {
1981 .name = "gpt10_ick",
1982 .ops = &clkops_omap2_iclk_dflt_wait,
1983 .parent = &core_l4_ick,
1984 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1985 .enable_bit = OMAP3430_EN_GPT10_SHIFT,
1986 .clkdm_name = "core_l4_clkdm",
1987 .recalc = &followparent_recalc,
1988};
1989
1990static struct clk mcbsp5_ick = {
1991 .name = "mcbsp5_ick",
1992 .ops = &clkops_omap2_iclk_dflt_wait,
1993 .parent = &core_l4_ick,
1994 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1995 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
1996 .clkdm_name = "core_l4_clkdm",
1997 .recalc = &followparent_recalc,
1998};
1999
2000static struct clk mcbsp1_ick = {
2001 .name = "mcbsp1_ick",
2002 .ops = &clkops_omap2_iclk_dflt_wait,
2003 .parent = &core_l4_ick,
2004 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2005 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
2006 .clkdm_name = "core_l4_clkdm",
2007 .recalc = &followparent_recalc,
2008};
2009
2010static struct clk fac_ick = {
2011 .name = "fac_ick",
2012 .ops = &clkops_omap2_iclk_dflt_wait,
2013 .parent = &core_l4_ick,
2014 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2015 .enable_bit = OMAP3430ES1_EN_FAC_SHIFT,
2016 .clkdm_name = "core_l4_clkdm",
2017 .recalc = &followparent_recalc,
2018};
2019
2020static struct clk mailboxes_ick = {
2021 .name = "mailboxes_ick",
2022 .ops = &clkops_omap2_iclk_dflt_wait,
2023 .parent = &core_l4_ick,
2024 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2025 .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT,
2026 .clkdm_name = "core_l4_clkdm",
2027 .recalc = &followparent_recalc,
2028};
2029
2030static struct clk omapctrl_ick = {
2031 .name = "omapctrl_ick",
2032 .ops = &clkops_omap2_iclk_dflt_wait,
2033 .parent = &core_l4_ick,
2034 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2035 .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT,
2036 .flags = ENABLE_ON_INIT,
2037 .clkdm_name = "core_l4_clkdm",
2038 .recalc = &followparent_recalc,
2039};
2040
2041/* SSI_L4_ICK based clocks */
2042
2043static struct clk ssi_l4_ick = {
2044 .name = "ssi_l4_ick",
2045 .ops = &clkops_null,
2046 .parent = &l4_ick,
2047 .clkdm_name = "core_l4_clkdm",
2048 .recalc = &followparent_recalc,
2049};
2050
2051static struct clk ssi_ick_3430es1 = {
2052 .name = "ssi_ick",
2053 .ops = &clkops_omap2_iclk_dflt,
2054 .parent = &ssi_l4_ick,
2055 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2056 .enable_bit = OMAP3430_EN_SSI_SHIFT,
2057 .clkdm_name = "core_l4_clkdm",
2058 .recalc = &followparent_recalc,
2059};
2060
2061static struct clk ssi_ick_3430es2 = {
2062 .name = "ssi_ick",
2063 .ops = &clkops_omap3430es2_iclk_ssi_wait,
2064 .parent = &ssi_l4_ick,
2065 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2066 .enable_bit = OMAP3430_EN_SSI_SHIFT,
2067 .clkdm_name = "core_l4_clkdm",
2068 .recalc = &followparent_recalc,
2069};
2070
2071/* REVISIT: Technically the TRM claims that this is CORE_CLK based,
2072 * but l4_ick makes more sense to me */
2073
2074static const struct clksel usb_l4_clksel[] = {
2075 { .parent = &l4_ick, .rates = div2_rates },
2076 { .parent = NULL },
2077};
2078
2079static struct clk usb_l4_ick = {
2080 .name = "usb_l4_ick",
2081 .ops = &clkops_omap2_iclk_dflt_wait,
2082 .parent = &l4_ick,
2083 .init = &omap2_init_clksel_parent,
2084 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2085 .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
2086 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2087 .clksel_mask = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
2088 .clksel = usb_l4_clksel,
2089 .clkdm_name = "core_l4_clkdm",
2090 .recalc = &omap2_clksel_recalc,
2091};
2092
2093/* SECURITY_L4_ICK2 based clocks */
2094
2095static struct clk security_l4_ick2 = {
2096 .name = "security_l4_ick2",
2097 .ops = &clkops_null,
2098 .parent = &l4_ick,
2099 .recalc = &followparent_recalc,
2100};
2101
2102static struct clk aes1_ick = {
2103 .name = "aes1_ick",
2104 .ops = &clkops_omap2_iclk_dflt_wait,
2105 .parent = &security_l4_ick2,
2106 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2107 .enable_bit = OMAP3430_EN_AES1_SHIFT,
2108 .recalc = &followparent_recalc,
2109};
2110
2111static struct clk rng_ick = {
2112 .name = "rng_ick",
2113 .ops = &clkops_omap2_iclk_dflt_wait,
2114 .parent = &security_l4_ick2,
2115 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2116 .enable_bit = OMAP3430_EN_RNG_SHIFT,
2117 .recalc = &followparent_recalc,
2118};
2119
2120static struct clk sha11_ick = {
2121 .name = "sha11_ick",
2122 .ops = &clkops_omap2_iclk_dflt_wait,
2123 .parent = &security_l4_ick2,
2124 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2125 .enable_bit = OMAP3430_EN_SHA11_SHIFT,
2126 .recalc = &followparent_recalc,
2127};
2128
2129static struct clk des1_ick = {
2130 .name = "des1_ick",
2131 .ops = &clkops_omap2_iclk_dflt_wait,
2132 .parent = &security_l4_ick2,
2133 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2134 .enable_bit = OMAP3430_EN_DES1_SHIFT,
2135 .recalc = &followparent_recalc,
2136};
2137
2138/* DSS */
2139static struct clk dss1_alwon_fck_3430es1 = {
2140 .name = "dss1_alwon_fck",
2141 .ops = &clkops_omap2_dflt,
2142 .parent = &dpll4_m4x2_ck,
2143 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2144 .enable_bit = OMAP3430_EN_DSS1_SHIFT,
2145 .clkdm_name = "dss_clkdm",
2146 .recalc = &followparent_recalc,
2147};
2148
2149static struct clk dss1_alwon_fck_3430es2 = {
2150 .name = "dss1_alwon_fck",
2151 .ops = &clkops_omap3430es2_dss_usbhost_wait,
2152 .parent = &dpll4_m4x2_ck,
2153 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2154 .enable_bit = OMAP3430_EN_DSS1_SHIFT,
2155 .clkdm_name = "dss_clkdm",
2156 .recalc = &followparent_recalc,
2157};
2158
2159static struct clk dss_tv_fck = {
2160 .name = "dss_tv_fck",
2161 .ops = &clkops_omap2_dflt,
2162 .parent = &omap_54m_fck,
2163 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2164 .enable_bit = OMAP3430_EN_TV_SHIFT,
2165 .clkdm_name = "dss_clkdm",
2166 .recalc = &followparent_recalc,
2167};
2168
2169static struct clk dss_96m_fck = {
2170 .name = "dss_96m_fck",
2171 .ops = &clkops_omap2_dflt,
2172 .parent = &omap_96m_fck,
2173 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2174 .enable_bit = OMAP3430_EN_TV_SHIFT,
2175 .clkdm_name = "dss_clkdm",
2176 .recalc = &followparent_recalc,
2177};
2178
2179static struct clk dss2_alwon_fck = {
2180 .name = "dss2_alwon_fck",
2181 .ops = &clkops_omap2_dflt,
2182 .parent = &sys_ck,
2183 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2184 .enable_bit = OMAP3430_EN_DSS2_SHIFT,
2185 .clkdm_name = "dss_clkdm",
2186 .recalc = &followparent_recalc,
2187};
2188
2189static struct clk dss_ick_3430es1 = {
2190 /* Handles both L3 and L4 clocks */
2191 .name = "dss_ick",
2192 .ops = &clkops_omap2_iclk_dflt,
2193 .parent = &l4_ick,
2194 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2195 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2196 .clkdm_name = "dss_clkdm",
2197 .recalc = &followparent_recalc,
2198};
2199
2200static struct clk dss_ick_3430es2 = {
2201 /* Handles both L3 and L4 clocks */
2202 .name = "dss_ick",
2203 .ops = &clkops_omap3430es2_iclk_dss_usbhost_wait,
2204 .parent = &l4_ick,
2205 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2206 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2207 .clkdm_name = "dss_clkdm",
2208 .recalc = &followparent_recalc,
2209};
2210
2211/* CAM */
2212
2213static struct clk cam_mclk = {
2214 .name = "cam_mclk",
2215 .ops = &clkops_omap2_dflt,
2216 .parent = &dpll4_m5x2_ck,
2217 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2218 .enable_bit = OMAP3430_EN_CAM_SHIFT,
2219 .clkdm_name = "cam_clkdm",
2220 .recalc = &followparent_recalc,
2221};
2222
2223static struct clk cam_ick = {
2224 /* Handles both L3 and L4 clocks */
2225 .name = "cam_ick",
2226 .ops = &clkops_omap2_iclk_dflt,
2227 .parent = &l4_ick,
2228 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2229 .enable_bit = OMAP3430_EN_CAM_SHIFT,
2230 .clkdm_name = "cam_clkdm",
2231 .recalc = &followparent_recalc,
2232};
2233
2234static struct clk csi2_96m_fck = {
2235 .name = "csi2_96m_fck",
2236 .ops = &clkops_omap2_dflt,
2237 .parent = &core_96m_fck,
2238 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2239 .enable_bit = OMAP3430_EN_CSI2_SHIFT,
2240 .clkdm_name = "cam_clkdm",
2241 .recalc = &followparent_recalc,
2242};
2243
2244/* USBHOST - 3430ES2 only */
2245
2246static struct clk usbhost_120m_fck = {
2247 .name = "usbhost_120m_fck",
2248 .ops = &clkops_omap2_dflt,
2249 .parent = &dpll5_m2_ck,
2250 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2251 .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT,
2252 .clkdm_name = "usbhost_clkdm",
2253 .recalc = &followparent_recalc,
2254};
2255
2256static struct clk usbhost_48m_fck = {
2257 .name = "usbhost_48m_fck",
2258 .ops = &clkops_omap3430es2_dss_usbhost_wait,
2259 .parent = &omap_48m_fck,
2260 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2261 .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
2262 .clkdm_name = "usbhost_clkdm",
2263 .recalc = &followparent_recalc,
2264};
2265
2266static struct clk usbhost_ick = {
2267 /* Handles both L3 and L4 clocks */
2268 .name = "usbhost_ick",
2269 .ops = &clkops_omap3430es2_iclk_dss_usbhost_wait,
2270 .parent = &l4_ick,
2271 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2272 .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT,
2273 .clkdm_name = "usbhost_clkdm",
2274 .recalc = &followparent_recalc,
2275};
2276
2277/* WKUP */
2278
2279static const struct clksel_rate usim_96m_rates[] = {
2280 { .div = 2, .val = 3, .flags = RATE_IN_3XXX },
2281 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
2282 { .div = 8, .val = 5, .flags = RATE_IN_3XXX },
2283 { .div = 10, .val = 6, .flags = RATE_IN_3XXX },
2284 { .div = 0 },
2285};
2286
2287static const struct clksel_rate usim_120m_rates[] = {
2288 { .div = 4, .val = 7, .flags = RATE_IN_3XXX },
2289 { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
2290 { .div = 16, .val = 9, .flags = RATE_IN_3XXX },
2291 { .div = 20, .val = 10, .flags = RATE_IN_3XXX },
2292 { .div = 0 },
2293};
2294
2295static const struct clksel usim_clksel[] = {
2296 { .parent = &omap_96m_fck, .rates = usim_96m_rates },
2297 { .parent = &dpll5_m2_ck, .rates = usim_120m_rates },
2298 { .parent = &sys_ck, .rates = div2_rates },
2299 { .parent = NULL },
2300};
2301
2302/* 3430ES2 only */
2303static struct clk usim_fck = {
2304 .name = "usim_fck",
2305 .ops = &clkops_omap2_dflt_wait,
2306 .init = &omap2_init_clksel_parent,
2307 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2308 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
2309 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2310 .clksel_mask = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
2311 .clksel = usim_clksel,
2312 .recalc = &omap2_clksel_recalc,
2313};
2314
2315/* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
2316static struct clk gpt1_fck = {
2317 .name = "gpt1_fck",
2318 .ops = &clkops_omap2_dflt_wait,
2319 .init = &omap2_init_clksel_parent,
2320 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2321 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
2322 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2323 .clksel_mask = OMAP3430_CLKSEL_GPT1_MASK,
2324 .clksel = omap343x_gpt_clksel,
2325 .clkdm_name = "wkup_clkdm",
2326 .recalc = &omap2_clksel_recalc,
2327};
2328
2329static struct clk wkup_32k_fck = {
2330 .name = "wkup_32k_fck",
2331 .ops = &clkops_null,
2332 .parent = &omap_32k_fck,
2333 .clkdm_name = "wkup_clkdm",
2334 .recalc = &followparent_recalc,
2335};
2336
2337static struct clk gpio1_dbck = {
2338 .name = "gpio1_dbck",
2339 .ops = &clkops_omap2_dflt,
2340 .parent = &wkup_32k_fck,
2341 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2342 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
2343 .clkdm_name = "wkup_clkdm",
2344 .recalc = &followparent_recalc,
2345};
2346
2347static struct clk wdt2_fck = {
2348 .name = "wdt2_fck",
2349 .ops = &clkops_omap2_dflt_wait,
2350 .parent = &wkup_32k_fck,
2351 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2352 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
2353 .clkdm_name = "wkup_clkdm",
2354 .recalc = &followparent_recalc,
2355};
2356
2357static struct clk wkup_l4_ick = {
2358 .name = "wkup_l4_ick",
2359 .ops = &clkops_null,
2360 .parent = &sys_ck,
2361 .clkdm_name = "wkup_clkdm",
2362 .recalc = &followparent_recalc,
2363};
2364
2365/* 3430ES2 only */
2366/* Never specifically named in the TRM, so we have to infer a likely name */
2367static struct clk usim_ick = {
2368 .name = "usim_ick",
2369 .ops = &clkops_omap2_iclk_dflt_wait,
2370 .parent = &wkup_l4_ick,
2371 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2372 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
2373 .clkdm_name = "wkup_clkdm",
2374 .recalc = &followparent_recalc,
2375};
2376
2377static struct clk wdt2_ick = {
2378 .name = "wdt2_ick",
2379 .ops = &clkops_omap2_iclk_dflt_wait,
2380 .parent = &wkup_l4_ick,
2381 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2382 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
2383 .clkdm_name = "wkup_clkdm",
2384 .recalc = &followparent_recalc,
2385};
2386
2387static struct clk wdt1_ick = {
2388 .name = "wdt1_ick",
2389 .ops = &clkops_omap2_iclk_dflt_wait,
2390 .parent = &wkup_l4_ick,
2391 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2392 .enable_bit = OMAP3430_EN_WDT1_SHIFT,
2393 .clkdm_name = "wkup_clkdm",
2394 .recalc = &followparent_recalc,
2395};
2396
2397static struct clk gpio1_ick = {
2398 .name = "gpio1_ick",
2399 .ops = &clkops_omap2_iclk_dflt_wait,
2400 .parent = &wkup_l4_ick,
2401 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2402 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
2403 .clkdm_name = "wkup_clkdm",
2404 .recalc = &followparent_recalc,
2405};
2406
2407static struct clk omap_32ksync_ick = {
2408 .name = "omap_32ksync_ick",
2409 .ops = &clkops_omap2_iclk_dflt_wait,
2410 .parent = &wkup_l4_ick,
2411 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2412 .enable_bit = OMAP3430_EN_32KSYNC_SHIFT,
2413 .clkdm_name = "wkup_clkdm",
2414 .recalc = &followparent_recalc,
2415};
2416
2417/* XXX This clock no longer exists in 3430 TRM rev F */
2418static struct clk gpt12_ick = {
2419 .name = "gpt12_ick",
2420 .ops = &clkops_omap2_iclk_dflt_wait,
2421 .parent = &wkup_l4_ick,
2422 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2423 .enable_bit = OMAP3430_EN_GPT12_SHIFT,
2424 .clkdm_name = "wkup_clkdm",
2425 .recalc = &followparent_recalc,
2426};
2427
2428static struct clk gpt1_ick = {
2429 .name = "gpt1_ick",
2430 .ops = &clkops_omap2_iclk_dflt_wait,
2431 .parent = &wkup_l4_ick,
2432 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2433 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
2434 .clkdm_name = "wkup_clkdm",
2435 .recalc = &followparent_recalc,
2436};
2437
2438
2439
2440/* PER clock domain */
2441
2442static struct clk per_96m_fck = {
2443 .name = "per_96m_fck",
2444 .ops = &clkops_null,
2445 .parent = &omap_96m_alwon_fck,
2446 .clkdm_name = "per_clkdm",
2447 .recalc = &followparent_recalc,
2448};
2449
2450static struct clk per_48m_fck = {
2451 .name = "per_48m_fck",
2452 .ops = &clkops_null,
2453 .parent = &omap_48m_fck,
2454 .clkdm_name = "per_clkdm",
2455 .recalc = &followparent_recalc,
2456};
2457
2458static struct clk uart3_fck = {
2459 .name = "uart3_fck",
2460 .ops = &clkops_omap2_dflt_wait,
2461 .parent = &per_48m_fck,
2462 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2463 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2464 .clkdm_name = "per_clkdm",
2465 .recalc = &followparent_recalc,
2466};
2467
2468static struct clk uart4_fck = {
2469 .name = "uart4_fck",
2470 .ops = &clkops_omap2_dflt_wait,
2471 .parent = &per_48m_fck,
2472 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2473 .enable_bit = OMAP3630_EN_UART4_SHIFT,
2474 .clkdm_name = "per_clkdm",
2475 .recalc = &followparent_recalc,
2476};
2477
2478static struct clk uart4_fck_am35xx = {
2479 .name = "uart4_fck",
2480 .ops = &clkops_omap2_dflt_wait,
2481 .parent = &core_48m_fck,
2482 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2483 .enable_bit = AM35XX_EN_UART4_SHIFT,
2484 .clkdm_name = "core_l4_clkdm",
2485 .recalc = &followparent_recalc,
2486};
2487
2488static struct clk gpt2_fck = {
2489 .name = "gpt2_fck",
2490 .ops = &clkops_omap2_dflt_wait,
2491 .init = &omap2_init_clksel_parent,
2492 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2493 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
2494 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2495 .clksel_mask = OMAP3430_CLKSEL_GPT2_MASK,
2496 .clksel = omap343x_gpt_clksel,
2497 .clkdm_name = "per_clkdm",
2498 .recalc = &omap2_clksel_recalc,
2499};
2500
2501static struct clk gpt3_fck = {
2502 .name = "gpt3_fck",
2503 .ops = &clkops_omap2_dflt_wait,
2504 .init = &omap2_init_clksel_parent,
2505 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2506 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
2507 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2508 .clksel_mask = OMAP3430_CLKSEL_GPT3_MASK,
2509 .clksel = omap343x_gpt_clksel,
2510 .clkdm_name = "per_clkdm",
2511 .recalc = &omap2_clksel_recalc,
2512};
2513
2514static struct clk gpt4_fck = {
2515 .name = "gpt4_fck",
2516 .ops = &clkops_omap2_dflt_wait,
2517 .init = &omap2_init_clksel_parent,
2518 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2519 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
2520 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2521 .clksel_mask = OMAP3430_CLKSEL_GPT4_MASK,
2522 .clksel = omap343x_gpt_clksel,
2523 .clkdm_name = "per_clkdm",
2524 .recalc = &omap2_clksel_recalc,
2525};
2526
2527static struct clk gpt5_fck = {
2528 .name = "gpt5_fck",
2529 .ops = &clkops_omap2_dflt_wait,
2530 .init = &omap2_init_clksel_parent,
2531 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2532 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
2533 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2534 .clksel_mask = OMAP3430_CLKSEL_GPT5_MASK,
2535 .clksel = omap343x_gpt_clksel,
2536 .clkdm_name = "per_clkdm",
2537 .recalc = &omap2_clksel_recalc,
2538};
2539
2540static struct clk gpt6_fck = {
2541 .name = "gpt6_fck",
2542 .ops = &clkops_omap2_dflt_wait,
2543 .init = &omap2_init_clksel_parent,
2544 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2545 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
2546 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2547 .clksel_mask = OMAP3430_CLKSEL_GPT6_MASK,
2548 .clksel = omap343x_gpt_clksel,
2549 .clkdm_name = "per_clkdm",
2550 .recalc = &omap2_clksel_recalc,
2551};
2552
2553static struct clk gpt7_fck = {
2554 .name = "gpt7_fck",
2555 .ops = &clkops_omap2_dflt_wait,
2556 .init = &omap2_init_clksel_parent,
2557 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2558 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
2559 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2560 .clksel_mask = OMAP3430_CLKSEL_GPT7_MASK,
2561 .clksel = omap343x_gpt_clksel,
2562 .clkdm_name = "per_clkdm",
2563 .recalc = &omap2_clksel_recalc,
2564};
2565
2566static struct clk gpt8_fck = {
2567 .name = "gpt8_fck",
2568 .ops = &clkops_omap2_dflt_wait,
2569 .init = &omap2_init_clksel_parent,
2570 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2571 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
2572 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2573 .clksel_mask = OMAP3430_CLKSEL_GPT8_MASK,
2574 .clksel = omap343x_gpt_clksel,
2575 .clkdm_name = "per_clkdm",
2576 .recalc = &omap2_clksel_recalc,
2577};
2578
2579static struct clk gpt9_fck = {
2580 .name = "gpt9_fck",
2581 .ops = &clkops_omap2_dflt_wait,
2582 .init = &omap2_init_clksel_parent,
2583 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2584 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
2585 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2586 .clksel_mask = OMAP3430_CLKSEL_GPT9_MASK,
2587 .clksel = omap343x_gpt_clksel,
2588 .clkdm_name = "per_clkdm",
2589 .recalc = &omap2_clksel_recalc,
2590};
2591
2592static struct clk per_32k_alwon_fck = {
2593 .name = "per_32k_alwon_fck",
2594 .ops = &clkops_null,
2595 .parent = &omap_32k_fck,
2596 .clkdm_name = "per_clkdm",
2597 .recalc = &followparent_recalc,
2598};
2599
2600static struct clk gpio6_dbck = {
2601 .name = "gpio6_dbck",
2602 .ops = &clkops_omap2_dflt,
2603 .parent = &per_32k_alwon_fck,
2604 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2605 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
2606 .clkdm_name = "per_clkdm",
2607 .recalc = &followparent_recalc,
2608};
2609
2610static struct clk gpio5_dbck = {
2611 .name = "gpio5_dbck",
2612 .ops = &clkops_omap2_dflt,
2613 .parent = &per_32k_alwon_fck,
2614 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2615 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
2616 .clkdm_name = "per_clkdm",
2617 .recalc = &followparent_recalc,
2618};
2619
2620static struct clk gpio4_dbck = {
2621 .name = "gpio4_dbck",
2622 .ops = &clkops_omap2_dflt,
2623 .parent = &per_32k_alwon_fck,
2624 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2625 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
2626 .clkdm_name = "per_clkdm",
2627 .recalc = &followparent_recalc,
2628};
2629
2630static struct clk gpio3_dbck = {
2631 .name = "gpio3_dbck",
2632 .ops = &clkops_omap2_dflt,
2633 .parent = &per_32k_alwon_fck,
2634 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2635 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
2636 .clkdm_name = "per_clkdm",
2637 .recalc = &followparent_recalc,
2638};
2639
2640static struct clk gpio2_dbck = {
2641 .name = "gpio2_dbck",
2642 .ops = &clkops_omap2_dflt,
2643 .parent = &per_32k_alwon_fck,
2644 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2645 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
2646 .clkdm_name = "per_clkdm",
2647 .recalc = &followparent_recalc,
2648};
2649
2650static struct clk wdt3_fck = {
2651 .name = "wdt3_fck",
2652 .ops = &clkops_omap2_dflt_wait,
2653 .parent = &per_32k_alwon_fck,
2654 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2655 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
2656 .clkdm_name = "per_clkdm",
2657 .recalc = &followparent_recalc,
2658};
2659
2660static struct clk per_l4_ick = {
2661 .name = "per_l4_ick",
2662 .ops = &clkops_null,
2663 .parent = &l4_ick,
2664 .clkdm_name = "per_clkdm",
2665 .recalc = &followparent_recalc,
2666};
2667
2668static struct clk gpio6_ick = {
2669 .name = "gpio6_ick",
2670 .ops = &clkops_omap2_iclk_dflt_wait,
2671 .parent = &per_l4_ick,
2672 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2673 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
2674 .clkdm_name = "per_clkdm",
2675 .recalc = &followparent_recalc,
2676};
2677
2678static struct clk gpio5_ick = {
2679 .name = "gpio5_ick",
2680 .ops = &clkops_omap2_iclk_dflt_wait,
2681 .parent = &per_l4_ick,
2682 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2683 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
2684 .clkdm_name = "per_clkdm",
2685 .recalc = &followparent_recalc,
2686};
2687
2688static struct clk gpio4_ick = {
2689 .name = "gpio4_ick",
2690 .ops = &clkops_omap2_iclk_dflt_wait,
2691 .parent = &per_l4_ick,
2692 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2693 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
2694 .clkdm_name = "per_clkdm",
2695 .recalc = &followparent_recalc,
2696};
2697
2698static struct clk gpio3_ick = {
2699 .name = "gpio3_ick",
2700 .ops = &clkops_omap2_iclk_dflt_wait,
2701 .parent = &per_l4_ick,
2702 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2703 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
2704 .clkdm_name = "per_clkdm",
2705 .recalc = &followparent_recalc,
2706};
2707
2708static struct clk gpio2_ick = {
2709 .name = "gpio2_ick",
2710 .ops = &clkops_omap2_iclk_dflt_wait,
2711 .parent = &per_l4_ick,
2712 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2713 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
2714 .clkdm_name = "per_clkdm",
2715 .recalc = &followparent_recalc,
2716};
2717
2718static struct clk wdt3_ick = {
2719 .name = "wdt3_ick",
2720 .ops = &clkops_omap2_iclk_dflt_wait,
2721 .parent = &per_l4_ick,
2722 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2723 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
2724 .clkdm_name = "per_clkdm",
2725 .recalc = &followparent_recalc,
2726};
2727
2728static struct clk uart3_ick = {
2729 .name = "uart3_ick",
2730 .ops = &clkops_omap2_iclk_dflt_wait,
2731 .parent = &per_l4_ick,
2732 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2733 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2734 .clkdm_name = "per_clkdm",
2735 .recalc = &followparent_recalc,
2736};
2737
2738static struct clk uart4_ick = {
2739 .name = "uart4_ick",
2740 .ops = &clkops_omap2_iclk_dflt_wait,
2741 .parent = &per_l4_ick,
2742 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2743 .enable_bit = OMAP3630_EN_UART4_SHIFT,
2744 .clkdm_name = "per_clkdm",
2745 .recalc = &followparent_recalc,
2746};
2747
2748static struct clk gpt9_ick = {
2749 .name = "gpt9_ick",
2750 .ops = &clkops_omap2_iclk_dflt_wait,
2751 .parent = &per_l4_ick,
2752 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2753 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
2754 .clkdm_name = "per_clkdm",
2755 .recalc = &followparent_recalc,
2756};
2757
2758static struct clk gpt8_ick = {
2759 .name = "gpt8_ick",
2760 .ops = &clkops_omap2_iclk_dflt_wait,
2761 .parent = &per_l4_ick,
2762 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2763 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
2764 .clkdm_name = "per_clkdm",
2765 .recalc = &followparent_recalc,
2766};
2767
2768static struct clk gpt7_ick = {
2769 .name = "gpt7_ick",
2770 .ops = &clkops_omap2_iclk_dflt_wait,
2771 .parent = &per_l4_ick,
2772 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2773 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
2774 .clkdm_name = "per_clkdm",
2775 .recalc = &followparent_recalc,
2776};
2777
2778static struct clk gpt6_ick = {
2779 .name = "gpt6_ick",
2780 .ops = &clkops_omap2_iclk_dflt_wait,
2781 .parent = &per_l4_ick,
2782 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2783 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
2784 .clkdm_name = "per_clkdm",
2785 .recalc = &followparent_recalc,
2786};
2787
2788static struct clk gpt5_ick = {
2789 .name = "gpt5_ick",
2790 .ops = &clkops_omap2_iclk_dflt_wait,
2791 .parent = &per_l4_ick,
2792 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2793 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
2794 .clkdm_name = "per_clkdm",
2795 .recalc = &followparent_recalc,
2796};
2797
2798static struct clk gpt4_ick = {
2799 .name = "gpt4_ick",
2800 .ops = &clkops_omap2_iclk_dflt_wait,
2801 .parent = &per_l4_ick,
2802 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2803 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
2804 .clkdm_name = "per_clkdm",
2805 .recalc = &followparent_recalc,
2806};
2807
2808static struct clk gpt3_ick = {
2809 .name = "gpt3_ick",
2810 .ops = &clkops_omap2_iclk_dflt_wait,
2811 .parent = &per_l4_ick,
2812 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2813 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
2814 .clkdm_name = "per_clkdm",
2815 .recalc = &followparent_recalc,
2816};
2817
2818static struct clk gpt2_ick = {
2819 .name = "gpt2_ick",
2820 .ops = &clkops_omap2_iclk_dflt_wait,
2821 .parent = &per_l4_ick,
2822 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2823 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
2824 .clkdm_name = "per_clkdm",
2825 .recalc = &followparent_recalc,
2826};
2827
2828static struct clk mcbsp2_ick = {
2829 .name = "mcbsp2_ick",
2830 .ops = &clkops_omap2_iclk_dflt_wait,
2831 .parent = &per_l4_ick,
2832 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2833 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
2834 .clkdm_name = "per_clkdm",
2835 .recalc = &followparent_recalc,
2836};
2837
2838static struct clk mcbsp3_ick = {
2839 .name = "mcbsp3_ick",
2840 .ops = &clkops_omap2_iclk_dflt_wait,
2841 .parent = &per_l4_ick,
2842 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2843 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
2844 .clkdm_name = "per_clkdm",
2845 .recalc = &followparent_recalc,
2846};
2847
2848static struct clk mcbsp4_ick = {
2849 .name = "mcbsp4_ick",
2850 .ops = &clkops_omap2_iclk_dflt_wait,
2851 .parent = &per_l4_ick,
2852 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2853 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
2854 .clkdm_name = "per_clkdm",
2855 .recalc = &followparent_recalc,
2856};
2857
2858static const struct clksel mcbsp_234_clksel[] = {
2859 { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates },
2860 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
2861 { .parent = NULL }
2862};
2863
2864static struct clk mcbsp2_fck = {
2865 .name = "mcbsp2_fck",
2866 .ops = &clkops_omap2_dflt_wait,
2867 .init = &omap2_init_clksel_parent,
2868 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2869 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
2870 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2871 .clksel_mask = OMAP2_MCBSP2_CLKS_MASK,
2872 .clksel = mcbsp_234_clksel,
2873 .clkdm_name = "per_clkdm",
2874 .recalc = &omap2_clksel_recalc,
2875};
2876
2877static struct clk mcbsp3_fck = {
2878 .name = "mcbsp3_fck",
2879 .ops = &clkops_omap2_dflt_wait,
2880 .init = &omap2_init_clksel_parent,
2881 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2882 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
2883 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2884 .clksel_mask = OMAP2_MCBSP3_CLKS_MASK,
2885 .clksel = mcbsp_234_clksel,
2886 .clkdm_name = "per_clkdm",
2887 .recalc = &omap2_clksel_recalc,
2888};
2889
2890static struct clk mcbsp4_fck = {
2891 .name = "mcbsp4_fck",
2892 .ops = &clkops_omap2_dflt_wait,
2893 .init = &omap2_init_clksel_parent,
2894 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2895 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
2896 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2897 .clksel_mask = OMAP2_MCBSP4_CLKS_MASK,
2898 .clksel = mcbsp_234_clksel,
2899 .clkdm_name = "per_clkdm",
2900 .recalc = &omap2_clksel_recalc,
2901};
2902
2903/* EMU clocks */
2904
2905/* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
2906
2907static const struct clksel_rate emu_src_sys_rates[] = {
2908 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
2909 { .div = 0 },
2910};
2911
2912static const struct clksel_rate emu_src_core_rates[] = {
2913 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
2914 { .div = 0 },
2915};
2916
2917static const struct clksel_rate emu_src_per_rates[] = {
2918 { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
2919 { .div = 0 },
2920};
2921
2922static const struct clksel_rate emu_src_mpu_rates[] = {
2923 { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
2924 { .div = 0 },
2925};
2926
2927static const struct clksel emu_src_clksel[] = {
2928 { .parent = &sys_ck, .rates = emu_src_sys_rates },
2929 { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
2930 { .parent = &emu_per_alwon_ck, .rates = emu_src_per_rates },
2931 { .parent = &emu_mpu_alwon_ck, .rates = emu_src_mpu_rates },
2932 { .parent = NULL },
2933};
2934
2935/*
2936 * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
2937 * to switch the source of some of the EMU clocks.
2938 * XXX Are there CLKEN bits for these EMU clks?
2939 */
2940static struct clk emu_src_ck = {
2941 .name = "emu_src_ck",
2942 .ops = &clkops_null,
2943 .init = &omap2_init_clksel_parent,
2944 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2945 .clksel_mask = OMAP3430_MUX_CTRL_MASK,
2946 .clksel = emu_src_clksel,
2947 .clkdm_name = "emu_clkdm",
2948 .recalc = &omap2_clksel_recalc,
2949};
2950
2951static const struct clksel_rate pclk_emu_rates[] = {
2952 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
2953 { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
2954 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
2955 { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
2956 { .div = 0 },
2957};
2958
2959static const struct clksel pclk_emu_clksel[] = {
2960 { .parent = &emu_src_ck, .rates = pclk_emu_rates },
2961 { .parent = NULL },
2962};
2963
2964static struct clk pclk_fck = {
2965 .name = "pclk_fck",
2966 .ops = &clkops_null,
2967 .init = &omap2_init_clksel_parent,
2968 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2969 .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK,
2970 .clksel = pclk_emu_clksel,
2971 .clkdm_name = "emu_clkdm",
2972 .recalc = &omap2_clksel_recalc,
2973};
2974
2975static const struct clksel_rate pclkx2_emu_rates[] = {
2976 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
2977 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
2978 { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
2979 { .div = 0 },
2980};
2981
2982static const struct clksel pclkx2_emu_clksel[] = {
2983 { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
2984 { .parent = NULL },
2985};
2986
2987static struct clk pclkx2_fck = {
2988 .name = "pclkx2_fck",
2989 .ops = &clkops_null,
2990 .init = &omap2_init_clksel_parent,
2991 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2992 .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK,
2993 .clksel = pclkx2_emu_clksel,
2994 .clkdm_name = "emu_clkdm",
2995 .recalc = &omap2_clksel_recalc,
2996};
2997
2998static const struct clksel atclk_emu_clksel[] = {
2999 { .parent = &emu_src_ck, .rates = div2_rates },
3000 { .parent = NULL },
3001};
3002
3003static struct clk atclk_fck = {
3004 .name = "atclk_fck",
3005 .ops = &clkops_null,
3006 .init = &omap2_init_clksel_parent,
3007 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3008 .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK,
3009 .clksel = atclk_emu_clksel,
3010 .clkdm_name = "emu_clkdm",
3011 .recalc = &omap2_clksel_recalc,
3012};
3013
3014static struct clk traceclk_src_fck = {
3015 .name = "traceclk_src_fck",
3016 .ops = &clkops_null,
3017 .init = &omap2_init_clksel_parent,
3018 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3019 .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK,
3020 .clksel = emu_src_clksel,
3021 .clkdm_name = "emu_clkdm",
3022 .recalc = &omap2_clksel_recalc,
3023};
3024
3025static const struct clksel_rate traceclk_rates[] = {
3026 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
3027 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
3028 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
3029 { .div = 0 },
3030};
3031
3032static const struct clksel traceclk_clksel[] = {
3033 { .parent = &traceclk_src_fck, .rates = traceclk_rates },
3034 { .parent = NULL },
3035};
3036
3037static struct clk traceclk_fck = {
3038 .name = "traceclk_fck",
3039 .ops = &clkops_null,
3040 .init = &omap2_init_clksel_parent,
3041 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3042 .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK,
3043 .clksel = traceclk_clksel,
3044 .clkdm_name = "emu_clkdm",
3045 .recalc = &omap2_clksel_recalc,
3046};
3047
3048/* SR clocks */
3049
3050/* SmartReflex fclk (VDD1) */
3051static struct clk sr1_fck = {
3052 .name = "sr1_fck",
3053 .ops = &clkops_omap2_dflt_wait,
3054 .parent = &sys_ck,
3055 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3056 .enable_bit = OMAP3430_EN_SR1_SHIFT,
3057 .clkdm_name = "wkup_clkdm",
3058 .recalc = &followparent_recalc,
3059};
3060
3061/* SmartReflex fclk (VDD2) */
3062static struct clk sr2_fck = {
3063 .name = "sr2_fck",
3064 .ops = &clkops_omap2_dflt_wait,
3065 .parent = &sys_ck,
3066 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3067 .enable_bit = OMAP3430_EN_SR2_SHIFT,
3068 .clkdm_name = "wkup_clkdm",
3069 .recalc = &followparent_recalc,
3070};
3071
3072static struct clk sr_l4_ick = {
3073 .name = "sr_l4_ick",
3074 .ops = &clkops_null, /* RMK: missing? */
3075 .parent = &l4_ick,
3076 .clkdm_name = "core_l4_clkdm",
3077 .recalc = &followparent_recalc,
3078};
3079
3080/* SECURE_32K_FCK clocks */
3081
3082static struct clk gpt12_fck = {
3083 .name = "gpt12_fck",
3084 .ops = &clkops_null,
3085 .parent = &secure_32k_fck,
3086 .clkdm_name = "wkup_clkdm",
3087 .recalc = &followparent_recalc,
3088};
3089
3090static struct clk wdt1_fck = {
3091 .name = "wdt1_fck",
3092 .ops = &clkops_null,
3093 .parent = &secure_32k_fck,
3094 .clkdm_name = "wkup_clkdm",
3095 .recalc = &followparent_recalc,
3096};
3097
3098/* Clocks for AM35XX */
3099static struct clk ipss_ick = {
3100 .name = "ipss_ick",
3101 .ops = &clkops_am35xx_ipss_wait,
3102 .parent = &core_l3_ick,
3103 .clkdm_name = "core_l3_clkdm",
3104 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
3105 .enable_bit = AM35XX_EN_IPSS_SHIFT,
3106 .recalc = &followparent_recalc,
3107};
3108
3109static struct clk emac_ick = {
3110 .name = "emac_ick",
3111 .ops = &clkops_am35xx_ipss_module_wait,
3112 .parent = &ipss_ick,
3113 .clkdm_name = "core_l3_clkdm",
3114 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3115 .enable_bit = AM35XX_CPGMAC_VBUSP_CLK_SHIFT,
3116 .recalc = &followparent_recalc,
3117};
3118
3119static struct clk rmii_ck = {
3120 .name = "rmii_ck",
3121 .ops = &clkops_null,
3122 .rate = 50000000,
3123};
3124
3125static struct clk emac_fck = {
3126 .name = "emac_fck",
3127 .ops = &clkops_omap2_dflt,
3128 .parent = &rmii_ck,
3129 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3130 .enable_bit = AM35XX_CPGMAC_FCLK_SHIFT,
3131 .recalc = &followparent_recalc,
3132};
3133
3134static struct clk hsotgusb_ick_am35xx = {
3135 .name = "hsotgusb_ick",
3136 .ops = &clkops_am35xx_ipss_module_wait,
3137 .parent = &ipss_ick,
3138 .clkdm_name = "core_l3_clkdm",
3139 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3140 .enable_bit = AM35XX_USBOTG_VBUSP_CLK_SHIFT,
3141 .recalc = &followparent_recalc,
3142};
3143
3144static struct clk hsotgusb_fck_am35xx = {
3145 .name = "hsotgusb_fck",
3146 .ops = &clkops_omap2_dflt,
3147 .parent = &sys_ck,
3148 .clkdm_name = "core_l3_clkdm",
3149 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3150 .enable_bit = AM35XX_USBOTG_FCLK_SHIFT,
3151 .recalc = &followparent_recalc,
3152};
3153
3154static struct clk hecc_ck = {
3155 .name = "hecc_ck",
3156 .ops = &clkops_am35xx_ipss_module_wait,
3157 .parent = &sys_ck,
3158 .clkdm_name = "core_l3_clkdm",
3159 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3160 .enable_bit = AM35XX_HECC_VBUSP_CLK_SHIFT,
3161 .recalc = &followparent_recalc,
3162};
3163
3164static struct clk vpfe_ick = {
3165 .name = "vpfe_ick",
3166 .ops = &clkops_am35xx_ipss_module_wait,
3167 .parent = &ipss_ick,
3168 .clkdm_name = "core_l3_clkdm",
3169 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3170 .enable_bit = AM35XX_VPFE_VBUSP_CLK_SHIFT,
3171 .recalc = &followparent_recalc,
3172};
3173
3174static struct clk pclk_ck = {
3175 .name = "pclk_ck",
3176 .ops = &clkops_null,
3177 .rate = 27000000,
3178};
3179
3180static struct clk vpfe_fck = {
3181 .name = "vpfe_fck",
3182 .ops = &clkops_omap2_dflt,
3183 .parent = &pclk_ck,
3184 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3185 .enable_bit = AM35XX_VPFE_FCLK_SHIFT,
3186 .recalc = &followparent_recalc,
3187};
3188
3189/*
3190 * The UART1/2 functional clock acts as the functional clock for
3191 * UART4. No separate fclk control available. XXX Well now we have a
3192 * uart4_fck that is apparently used as the UART4 functional clock,
3193 * but it also seems that uart1_fck or uart2_fck are still needed, at
3194 * least for UART4 softresets to complete. This really needs
3195 * clarification.
3196 */
3197static struct clk uart4_ick_am35xx = {
3198 .name = "uart4_ick",
3199 .ops = &clkops_omap2_iclk_dflt_wait,
3200 .parent = &core_l4_ick,
3201 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
3202 .enable_bit = AM35XX_EN_UART4_SHIFT,
3203 .clkdm_name = "core_l4_clkdm",
3204 .recalc = &followparent_recalc,
3205};
3206
3207static struct clk dummy_apb_pclk = {
3208 .name = "apb_pclk",
3209 .ops = &clkops_null,
3210};
3211
3212/*
3213 * clkdev
3214 */
3215
3216static struct omap_clk omap3xxx_clks[] = {
3217 CLK(NULL, "apb_pclk", &dummy_apb_pclk, CK_3XXX),
3218 CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_3XXX),
3219 CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_3XXX),
3220 CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_3XXX),
3221 CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3222 CLK(NULL, "virt_19200000_ck", &virt_19200000_ck, CK_3XXX),
3223 CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_3XXX),
3224 CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck, CK_3XXX),
3225 CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_3XXX),
3226 CLK("twl", "fck", &osc_sys_ck, CK_3XXX),
3227 CLK(NULL, "sys_ck", &sys_ck, CK_3XXX),
3228 CLK(NULL, "sys_altclk", &sys_altclk, CK_3XXX),
3229 CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_3XXX),
3230 CLK(NULL, "sys_clkout1", &sys_clkout1, CK_3XXX),
3231 CLK(NULL, "dpll1_ck", &dpll1_ck, CK_3XXX),
3232 CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck, CK_3XXX),
3233 CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_3XXX),
3234 CLK(NULL, "dpll2_ck", &dpll2_ck, CK_34XX | CK_36XX),
3235 CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck, CK_34XX | CK_36XX),
3236 CLK(NULL, "dpll3_ck", &dpll3_ck, CK_3XXX),
3237 CLK(NULL, "core_ck", &core_ck, CK_3XXX),
3238 CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck, CK_3XXX),
3239 CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck, CK_3XXX),
3240 CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_3XXX),
3241 CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck, CK_3XXX),
3242 CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_3XXX),
3243 CLK(NULL, "emu_core_alwon_ck", &emu_core_alwon_ck, CK_3XXX),
3244 CLK("etb", "emu_core_alwon_ck", &emu_core_alwon_ck, CK_3XXX),
3245 CLK(NULL, "dpll4_ck", &dpll4_ck, CK_3XXX),
3246 CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck, CK_3XXX),
3247 CLK(NULL, "omap_192m_alwon_fck", &omap_192m_alwon_fck, CK_36XX),
3248 CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_3XXX),
3249 CLK(NULL, "omap_96m_alwon_fck_3630", &omap_96m_alwon_fck_3630, CK_36XX),
3250 CLK(NULL, "omap_96m_fck", &omap_96m_fck, CK_3XXX),
3251 CLK(NULL, "cm_96m_fck", &cm_96m_fck, CK_3XXX),
3252 CLK(NULL, "omap_54m_fck", &omap_54m_fck, CK_3XXX),
3253 CLK(NULL, "omap_48m_fck", &omap_48m_fck, CK_3XXX),
3254 CLK(NULL, "omap_12m_fck", &omap_12m_fck, CK_3XXX),
3255 CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck, CK_3XXX),
3256 CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_3XXX),
3257 CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck, CK_3XXX),
3258 CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_3XXX),
3259 CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck, CK_3XXX),
3260 CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_3XXX),
3261 CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck, CK_3XXX),
3262 CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_3XXX),
3263 CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck, CK_3XXX),
3264 CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_3XXX),
3265 CLK(NULL, "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX),
3266 CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX),
3267 CLK(NULL, "dpll5_ck", &dpll5_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3268 CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3269 CLK(NULL, "clkout2_src_ck", &clkout2_src_ck, CK_3XXX),
3270 CLK(NULL, "sys_clkout2", &sys_clkout2, CK_3XXX),
3271 CLK(NULL, "corex2_fck", &corex2_fck, CK_3XXX),
3272 CLK(NULL, "dpll1_fck", &dpll1_fck, CK_3XXX),
3273 CLK(NULL, "mpu_ck", &mpu_ck, CK_3XXX),
3274 CLK(NULL, "arm_fck", &arm_fck, CK_3XXX),
3275 CLK(NULL, "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX),
3276 CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX),
3277 CLK(NULL, "dpll2_fck", &dpll2_fck, CK_34XX | CK_36XX),
3278 CLK(NULL, "iva2_ck", &iva2_ck, CK_34XX | CK_36XX),
3279 CLK(NULL, "l3_ick", &l3_ick, CK_3XXX),
3280 CLK(NULL, "l4_ick", &l4_ick, CK_3XXX),
3281 CLK(NULL, "rm_ick", &rm_ick, CK_3XXX),
3282 CLK(NULL, "gfx_l3_ck", &gfx_l3_ck, CK_3430ES1),
3283 CLK(NULL, "gfx_l3_fck", &gfx_l3_fck, CK_3430ES1),
3284 CLK(NULL, "gfx_l3_ick", &gfx_l3_ick, CK_3430ES1),
3285 CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck, CK_3430ES1),
3286 CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck, CK_3430ES1),
3287 CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3288 CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3289 CLK(NULL, "d2d_26m_fck", &d2d_26m_fck, CK_3430ES1),
3290 CLK(NULL, "modem_fck", &modem_fck, CK_34XX | CK_36XX),
3291 CLK(NULL, "sad2d_ick", &sad2d_ick, CK_34XX | CK_36XX),
3292 CLK(NULL, "mad2d_ick", &mad2d_ick, CK_34XX | CK_36XX),
3293 CLK(NULL, "gpt10_fck", &gpt10_fck, CK_3XXX),
3294 CLK(NULL, "gpt11_fck", &gpt11_fck, CK_3XXX),
3295 CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3296 CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3297 CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3298 CLK("usbhs_omap", "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3299 CLK("usbhs_tll", "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3300 CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX),
3301 CLK(NULL, "mmchs3_fck", &mmchs3_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3302 CLK(NULL, "mmchs2_fck", &mmchs2_fck, CK_3XXX),
3303 CLK(NULL, "mspro_fck", &mspro_fck, CK_34XX | CK_36XX),
3304 CLK(NULL, "mmchs1_fck", &mmchs1_fck, CK_3XXX),
3305 CLK(NULL, "i2c3_fck", &i2c3_fck, CK_3XXX),
3306 CLK(NULL, "i2c2_fck", &i2c2_fck, CK_3XXX),
3307 CLK(NULL, "i2c1_fck", &i2c1_fck, CK_3XXX),
3308 CLK(NULL, "mcbsp5_fck", &mcbsp5_fck, CK_3XXX),
3309 CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_3XXX),
3310 CLK(NULL, "core_48m_fck", &core_48m_fck, CK_3XXX),
3311 CLK(NULL, "mcspi4_fck", &mcspi4_fck, CK_3XXX),
3312 CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_3XXX),
3313 CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_3XXX),
3314 CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_3XXX),
3315 CLK(NULL, "uart2_fck", &uart2_fck, CK_3XXX),
3316 CLK(NULL, "uart1_fck", &uart1_fck, CK_3XXX),
3317 CLK(NULL, "fshostusb_fck", &fshostusb_fck, CK_3430ES1),
3318 CLK(NULL, "core_12m_fck", &core_12m_fck, CK_3XXX),
3319 CLK("omap_hdq.0", "fck", &hdq_fck, CK_3XXX),
3320 CLK(NULL, "hdq_fck", &hdq_fck, CK_3XXX),
3321 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1, CK_3430ES1),
3322 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2, CK_3430ES2PLUS | CK_36XX),
3323 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1, CK_3430ES1),
3324 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es2, CK_3430ES2PLUS | CK_36XX),
3325 CLK(NULL, "core_l3_ick", &core_l3_ick, CK_3XXX),
3326 CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es1, CK_3430ES1),
3327 CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es2, CK_3430ES2PLUS | CK_36XX),
3328 CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_3430es1, CK_3430ES1),
3329 CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_3430es2, CK_3430ES2PLUS | CK_36XX),
3330 CLK(NULL, "sdrc_ick", &sdrc_ick, CK_3XXX),
3331 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_3XXX),
3332 CLK(NULL, "security_l3_ick", &security_l3_ick, CK_34XX | CK_36XX),
3333 CLK(NULL, "pka_ick", &pka_ick, CK_34XX | CK_36XX),
3334 CLK(NULL, "core_l4_ick", &core_l4_ick, CK_3XXX),
3335 CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3336 CLK("usbhs_omap", "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3337 CLK("usbhs_tll", "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3338 CLK("omap_hsmmc.2", "ick", &mmchs3_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3339 CLK(NULL, "mmchs3_ick", &mmchs3_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3340 CLK(NULL, "icr_ick", &icr_ick, CK_34XX | CK_36XX),
3341 CLK("omap-aes", "ick", &aes2_ick, CK_34XX | CK_36XX),
3342 CLK("omap-sham", "ick", &sha12_ick, CK_34XX | CK_36XX),
3343 CLK(NULL, "des2_ick", &des2_ick, CK_34XX | CK_36XX),
3344 CLK("omap_hsmmc.1", "ick", &mmchs2_ick, CK_3XXX),
3345 CLK("omap_hsmmc.0", "ick", &mmchs1_ick, CK_3XXX),
3346 CLK(NULL, "mmchs2_ick", &mmchs2_ick, CK_3XXX),
3347 CLK(NULL, "mmchs1_ick", &mmchs1_ick, CK_3XXX),
3348 CLK(NULL, "mspro_ick", &mspro_ick, CK_34XX | CK_36XX),
3349 CLK("omap_hdq.0", "ick", &hdq_ick, CK_3XXX),
3350 CLK(NULL, "hdq_ick", &hdq_ick, CK_3XXX),
3351 CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_3XXX),
3352 CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_3XXX),
3353 CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_3XXX),
3354 CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_3XXX),
3355 CLK(NULL, "mcspi4_ick", &mcspi4_ick, CK_3XXX),
3356 CLK(NULL, "mcspi3_ick", &mcspi3_ick, CK_3XXX),
3357 CLK(NULL, "mcspi2_ick", &mcspi2_ick, CK_3XXX),
3358 CLK(NULL, "mcspi1_ick", &mcspi1_ick, CK_3XXX),
3359 CLK("omap_i2c.3", "ick", &i2c3_ick, CK_3XXX),
3360 CLK("omap_i2c.2", "ick", &i2c2_ick, CK_3XXX),
3361 CLK("omap_i2c.1", "ick", &i2c1_ick, CK_3XXX),
3362 CLK(NULL, "i2c3_ick", &i2c3_ick, CK_3XXX),
3363 CLK(NULL, "i2c2_ick", &i2c2_ick, CK_3XXX),
3364 CLK(NULL, "i2c1_ick", &i2c1_ick, CK_3XXX),
3365 CLK(NULL, "uart2_ick", &uart2_ick, CK_3XXX),
3366 CLK(NULL, "uart1_ick", &uart1_ick, CK_3XXX),
3367 CLK(NULL, "gpt11_ick", &gpt11_ick, CK_3XXX),
3368 CLK(NULL, "gpt10_ick", &gpt10_ick, CK_3XXX),
3369 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_3XXX),
3370 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_3XXX),
3371 CLK(NULL, "mcbsp5_ick", &mcbsp5_ick, CK_3XXX),
3372 CLK(NULL, "mcbsp1_ick", &mcbsp1_ick, CK_3XXX),
3373 CLK(NULL, "fac_ick", &fac_ick, CK_3430ES1),
3374 CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_34XX | CK_36XX),
3375 CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_3XXX),
3376 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_34XX | CK_36XX),
3377 CLK(NULL, "ssi_ick", &ssi_ick_3430es1, CK_3430ES1),
3378 CLK(NULL, "ssi_ick", &ssi_ick_3430es2, CK_3430ES2PLUS | CK_36XX),
3379 CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_3430ES1),
3380 CLK(NULL, "security_l4_ick2", &security_l4_ick2, CK_34XX | CK_36XX),
3381 CLK(NULL, "aes1_ick", &aes1_ick, CK_34XX | CK_36XX),
3382 CLK("omap_rng", "ick", &rng_ick, CK_34XX | CK_36XX),
3383 CLK(NULL, "sha11_ick", &sha11_ick, CK_34XX | CK_36XX),
3384 CLK(NULL, "des1_ick", &des1_ick, CK_34XX | CK_36XX),
3385 CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es1, CK_3430ES1),
3386 CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3387 CLK(NULL, "dss_tv_fck", &dss_tv_fck, CK_3XXX),
3388 CLK(NULL, "dss_96m_fck", &dss_96m_fck, CK_3XXX),
3389 CLK(NULL, "dss2_alwon_fck", &dss2_alwon_fck, CK_3XXX),
3390 CLK("omapdss_dss", "ick", &dss_ick_3430es1, CK_3430ES1),
3391 CLK(NULL, "dss_ick", &dss_ick_3430es1, CK_3430ES1),
3392 CLK("omapdss_dss", "ick", &dss_ick_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3393 CLK(NULL, "dss_ick", &dss_ick_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3394 CLK(NULL, "cam_mclk", &cam_mclk, CK_34XX | CK_36XX),
3395 CLK(NULL, "cam_ick", &cam_ick, CK_34XX | CK_36XX),
3396 CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_34XX | CK_36XX),
3397 CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3398 CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3399 CLK(NULL, "usbhost_ick", &usbhost_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3400 CLK("usbhs_omap", "usbhost_ick", &usbhost_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3401 CLK(NULL, "utmi_p1_gfclk", &dummy_ck, CK_3XXX),
3402 CLK(NULL, "utmi_p2_gfclk", &dummy_ck, CK_3XXX),
3403 CLK(NULL, "xclk60mhsp1_ck", &dummy_ck, CK_3XXX),
3404 CLK(NULL, "xclk60mhsp2_ck", &dummy_ck, CK_3XXX),
3405 CLK(NULL, "usb_host_hs_utmi_p1_clk", &dummy_ck, CK_3XXX),
3406 CLK(NULL, "usb_host_hs_utmi_p2_clk", &dummy_ck, CK_3XXX),
3407 CLK("usbhs_omap", "usb_tll_hs_usb_ch0_clk", &dummy_ck, CK_3XXX),
3408 CLK("usbhs_omap", "usb_tll_hs_usb_ch1_clk", &dummy_ck, CK_3XXX),
3409 CLK("usbhs_tll", "usb_tll_hs_usb_ch0_clk", &dummy_ck, CK_3XXX),
3410 CLK("usbhs_tll", "usb_tll_hs_usb_ch1_clk", &dummy_ck, CK_3XXX),
3411 CLK(NULL, "init_60m_fclk", &dummy_ck, CK_3XXX),
3412 CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2PLUS | CK_36XX),
3413 CLK(NULL, "gpt1_fck", &gpt1_fck, CK_3XXX),
3414 CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_3XXX),
3415 CLK(NULL, "gpio1_dbck", &gpio1_dbck, CK_3XXX),
3416 CLK(NULL, "wdt2_fck", &wdt2_fck, CK_3XXX),
3417 CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_34XX | CK_36XX),
3418 CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2PLUS | CK_36XX),
3419 CLK("omap_wdt", "ick", &wdt2_ick, CK_3XXX),
3420 CLK(NULL, "wdt2_ick", &wdt2_ick, CK_3XXX),
3421 CLK(NULL, "wdt1_ick", &wdt1_ick, CK_3XXX),
3422 CLK(NULL, "gpio1_ick", &gpio1_ick, CK_3XXX),
3423 CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX),
3424 CLK(NULL, "gpt12_ick", &gpt12_ick, CK_3XXX),
3425 CLK(NULL, "gpt1_ick", &gpt1_ick, CK_3XXX),
3426 CLK(NULL, "per_96m_fck", &per_96m_fck, CK_3XXX),
3427 CLK(NULL, "per_48m_fck", &per_48m_fck, CK_3XXX),
3428 CLK(NULL, "uart3_fck", &uart3_fck, CK_3XXX),
3429 CLK(NULL, "uart4_fck", &uart4_fck, CK_36XX),
3430 CLK(NULL, "uart4_fck", &uart4_fck_am35xx, CK_AM35XX),
3431 CLK(NULL, "gpt2_fck", &gpt2_fck, CK_3XXX),
3432 CLK(NULL, "gpt3_fck", &gpt3_fck, CK_3XXX),
3433 CLK(NULL, "gpt4_fck", &gpt4_fck, CK_3XXX),
3434 CLK(NULL, "gpt5_fck", &gpt5_fck, CK_3XXX),
3435 CLK(NULL, "gpt6_fck", &gpt6_fck, CK_3XXX),
3436 CLK(NULL, "gpt7_fck", &gpt7_fck, CK_3XXX),
3437 CLK(NULL, "gpt8_fck", &gpt8_fck, CK_3XXX),
3438 CLK(NULL, "gpt9_fck", &gpt9_fck, CK_3XXX),
3439 CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck, CK_3XXX),
3440 CLK(NULL, "gpio6_dbck", &gpio6_dbck, CK_3XXX),
3441 CLK(NULL, "gpio5_dbck", &gpio5_dbck, CK_3XXX),
3442 CLK(NULL, "gpio4_dbck", &gpio4_dbck, CK_3XXX),
3443 CLK(NULL, "gpio3_dbck", &gpio3_dbck, CK_3XXX),
3444 CLK(NULL, "gpio2_dbck", &gpio2_dbck, CK_3XXX),
3445 CLK(NULL, "wdt3_fck", &wdt3_fck, CK_3XXX),
3446 CLK(NULL, "per_l4_ick", &per_l4_ick, CK_3XXX),
3447 CLK(NULL, "gpio6_ick", &gpio6_ick, CK_3XXX),
3448 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_3XXX),
3449 CLK(NULL, "gpio4_ick", &gpio4_ick, CK_3XXX),
3450 CLK(NULL, "gpio3_ick", &gpio3_ick, CK_3XXX),
3451 CLK(NULL, "gpio2_ick", &gpio2_ick, CK_3XXX),
3452 CLK(NULL, "wdt3_ick", &wdt3_ick, CK_3XXX),
3453 CLK(NULL, "uart3_ick", &uart3_ick, CK_3XXX),
3454 CLK(NULL, "uart4_ick", &uart4_ick, CK_36XX),
3455 CLK(NULL, "gpt9_ick", &gpt9_ick, CK_3XXX),
3456 CLK(NULL, "gpt8_ick", &gpt8_ick, CK_3XXX),
3457 CLK(NULL, "gpt7_ick", &gpt7_ick, CK_3XXX),
3458 CLK(NULL, "gpt6_ick", &gpt6_ick, CK_3XXX),
3459 CLK(NULL, "gpt5_ick", &gpt5_ick, CK_3XXX),
3460 CLK(NULL, "gpt4_ick", &gpt4_ick, CK_3XXX),
3461 CLK(NULL, "gpt3_ick", &gpt3_ick, CK_3XXX),
3462 CLK(NULL, "gpt2_ick", &gpt2_ick, CK_3XXX),
3463 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_3XXX),
3464 CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_3XXX),
3465 CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_3XXX),
3466 CLK(NULL, "mcbsp4_ick", &mcbsp2_ick, CK_3XXX),
3467 CLK(NULL, "mcbsp3_ick", &mcbsp3_ick, CK_3XXX),
3468 CLK(NULL, "mcbsp2_ick", &mcbsp4_ick, CK_3XXX),
3469 CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_3XXX),
3470 CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_3XXX),
3471 CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_3XXX),
3472 CLK(NULL, "emu_src_ck", &emu_src_ck, CK_3XXX),
3473 CLK("etb", "emu_src_ck", &emu_src_ck, CK_3XXX),
3474 CLK(NULL, "pclk_fck", &pclk_fck, CK_3XXX),
3475 CLK(NULL, "pclkx2_fck", &pclkx2_fck, CK_3XXX),
3476 CLK(NULL, "atclk_fck", &atclk_fck, CK_3XXX),
3477 CLK(NULL, "traceclk_src_fck", &traceclk_src_fck, CK_3XXX),
3478 CLK(NULL, "traceclk_fck", &traceclk_fck, CK_3XXX),
3479 CLK(NULL, "sr1_fck", &sr1_fck, CK_34XX | CK_36XX),
3480 CLK(NULL, "sr2_fck", &sr2_fck, CK_34XX | CK_36XX),
3481 CLK(NULL, "sr_l4_ick", &sr_l4_ick, CK_34XX | CK_36XX),
3482 CLK(NULL, "secure_32k_fck", &secure_32k_fck, CK_3XXX),
3483 CLK(NULL, "gpt12_fck", &gpt12_fck, CK_3XXX),
3484 CLK(NULL, "wdt1_fck", &wdt1_fck, CK_3XXX),
3485 CLK(NULL, "ipss_ick", &ipss_ick, CK_AM35XX),
3486 CLK(NULL, "rmii_ck", &rmii_ck, CK_AM35XX),
3487 CLK(NULL, "pclk_ck", &pclk_ck, CK_AM35XX),
3488 CLK(NULL, "emac_ick", &emac_ick, CK_AM35XX),
3489 CLK(NULL, "emac_fck", &emac_fck, CK_AM35XX),
3490 CLK("davinci_emac.0", NULL, &emac_ick, CK_AM35XX),
3491 CLK("davinci_mdio.0", NULL, &emac_fck, CK_AM35XX),
3492 CLK(NULL, "vpfe_ick", &emac_ick, CK_AM35XX),
3493 CLK(NULL, "vpfe_fck", &emac_fck, CK_AM35XX),
3494 CLK("vpfe-capture", "master", &vpfe_ick, CK_AM35XX),
3495 CLK("vpfe-capture", "slave", &vpfe_fck, CK_AM35XX),
3496 CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_am35xx, CK_AM35XX),
3497 CLK(NULL, "hsotgusb_fck", &hsotgusb_fck_am35xx, CK_AM35XX),
3498 CLK(NULL, "hecc_ck", &hecc_ck, CK_AM35XX),
3499 CLK(NULL, "uart4_ick", &uart4_ick_am35xx, CK_AM35XX),
3500 CLK(NULL, "timer_32k_ck", &omap_32k_fck, CK_3XXX),
3501 CLK(NULL, "timer_sys_ck", &sys_ck, CK_3XXX),
3502 CLK(NULL, "cpufreq_ck", &dpll1_ck, CK_3XXX),
3503};
3504
3505
3506int __init omap3xxx_clk_init(void)
3507{
3508 struct omap_clk *c;
3509 u32 cpu_clkflg = 0;
3510
3511 if (soc_is_am35xx()) {
3512 cpu_mask = RATE_IN_34XX;
3513 cpu_clkflg = CK_AM35XX;
3514 } else if (cpu_is_omap3630()) {
3515 cpu_mask = (RATE_IN_34XX | RATE_IN_36XX);
3516 cpu_clkflg = CK_36XX;
3517 } else if (cpu_is_ti816x()) {
3518 cpu_mask = RATE_IN_TI816X;
3519 cpu_clkflg = CK_TI816X;
3520 } else if (soc_is_am33xx()) {
3521 cpu_mask = RATE_IN_AM33XX;
3522 } else if (cpu_is_ti814x()) {
3523 cpu_mask = RATE_IN_TI814X;
3524 } else if (cpu_is_omap34xx()) {
3525 if (omap_rev() == OMAP3430_REV_ES1_0) {
3526 cpu_mask = RATE_IN_3430ES1;
3527 cpu_clkflg = CK_3430ES1;
3528 } else {
3529 /*
3530 * Assume that anything that we haven't matched yet
3531 * has 3430ES2-type clocks.
3532 */
3533 cpu_mask = RATE_IN_3430ES2PLUS;
3534 cpu_clkflg = CK_3430ES2PLUS;
3535 }
3536 } else {
3537 WARN(1, "clock: could not identify OMAP3 variant\n");
3538 }
3539
3540 if (omap3_has_192mhz_clk())
3541 omap_96m_alwon_fck = omap_96m_alwon_fck_3630;
3542
3543 if (cpu_is_omap3630()) {
3544 /*
3545 * XXX This type of dynamic rewriting of the clock tree is
3546 * deprecated and should be revised soon.
3547 *
3548 * For 3630: override clkops_omap2_dflt_wait for the
3549 * clocks affected from PWRDN reset Limitation
3550 */
3551 dpll3_m3x2_ck.ops =
3552 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3553 dpll4_m2x2_ck.ops =
3554 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3555 dpll4_m3x2_ck.ops =
3556 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3557 dpll4_m4x2_ck.ops =
3558 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3559 dpll4_m5x2_ck.ops =
3560 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3561 dpll4_m6x2_ck.ops =
3562 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3563 }
3564
3565 /*
3566 * XXX This type of dynamic rewriting of the clock tree is
3567 * deprecated and should be revised soon.
3568 */
3569 if (cpu_is_omap3630())
3570 dpll4_dd = dpll4_dd_3630;
3571 else
3572 dpll4_dd = dpll4_dd_34xx;
3573
3574 for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks);
3575 c++)
3576 clk_preinit(c->lk.clk);
3577
3578 for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks);
3579 c++)
3580 if (c->cpu & cpu_clkflg) {
3581 clkdev_add(&c->lk);
3582 clk_register(c->lk.clk);
3583 omap2_init_clk_clkdm(c->lk.clk);
3584 }
3585
3586 /* Disable autoidle on all clocks; let the PM code enable it later */
3587 omap_clk_disable_autoidle_all();
3588
3589 recalculate_root_clocks();
3590
3591 pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
3592 (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
3593 (core_ck.rate / 1000000), (arm_fck.rate / 1000000));
3594
3595 /*
3596 * Only enable those clocks we will need, let the drivers
3597 * enable other clocks as necessary
3598 */
3599 clk_enable_init_clocks();
3600
3601 /*
3602 * Lock DPLL5 -- here only until other device init code can
3603 * handle this
3604 */
3605 if (!cpu_is_ti81xx() && (omap_rev() >= OMAP3430_REV_ES2_0))
3606 omap3_clk_lock_dpll5();
3607
3608 /* Avoid sleeping during omap3_core_dpll_m2_set_rate() */
3609 sdrc_ick_p = clk_get(NULL, "sdrc_ick");
3610 arm_fck_p = clk_get(NULL, "arm_fck");
3611
3612 return 0;
3613}
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
deleted file mode 100644
index 2a450c9b9a7b..000000000000
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ /dev/null
@@ -1,3398 +0,0 @@
1/*
2 * OMAP4 Clock data
3 *
4 * Copyright (C) 2009-2010 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation
6 *
7 * Paul Walmsley (paul@pwsan.com)
8 * Rajendra Nayak (rnayak@ti.com)
9 * Benoit Cousson (b-cousson@ti.com)
10 *
11 * This file is automatically generated from the OMAP hardware databases.
12 * We respectfully ask that any modifications to this file be coordinated
13 * with the public linux-omap@vger.kernel.org mailing list and the
14 * authors above to ensure that the autogeneration scripts are kept
15 * up-to-date with the file contents.
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
20 *
21 * XXX Some of the ES1 clocks have been removed/changed; once support
22 * is added for discriminating clocks by ES level, these should be added back
23 * in.
24 */
25
26#include <linux/kernel.h>
27#include <linux/list.h>
28#include <linux/clk.h>
29#include <linux/io.h>
30
31#include "soc.h"
32#include "iomap.h"
33#include "clock.h"
34#include "clock44xx.h"
35#include "cm1_44xx.h"
36#include "cm2_44xx.h"
37#include "cm-regbits-44xx.h"
38#include "prm44xx.h"
39#include "prm-regbits-44xx.h"
40#include "control.h"
41#include "scrm44xx.h"
42
43/* OMAP4 modulemode control */
44#define OMAP4430_MODULEMODE_HWCTRL 0
45#define OMAP4430_MODULEMODE_SWCTRL 1
46
47/* Root clocks */
48
49static struct clk extalt_clkin_ck = {
50 .name = "extalt_clkin_ck",
51 .rate = 59000000,
52 .ops = &clkops_null,
53};
54
55static struct clk pad_clks_ck = {
56 .name = "pad_clks_ck",
57 .rate = 12000000,
58 .ops = &clkops_omap2_dflt,
59 .enable_reg = OMAP4430_CM_CLKSEL_ABE,
60 .enable_bit = OMAP4430_PAD_CLKS_GATE_SHIFT,
61};
62
63static struct clk pad_slimbus_core_clks_ck = {
64 .name = "pad_slimbus_core_clks_ck",
65 .rate = 12000000,
66 .ops = &clkops_null,
67};
68
69static struct clk secure_32k_clk_src_ck = {
70 .name = "secure_32k_clk_src_ck",
71 .rate = 32768,
72 .ops = &clkops_null,
73};
74
75static struct clk slimbus_clk = {
76 .name = "slimbus_clk",
77 .rate = 12000000,
78 .ops = &clkops_omap2_dflt,
79 .enable_reg = OMAP4430_CM_CLKSEL_ABE,
80 .enable_bit = OMAP4430_SLIMBUS_CLK_GATE_SHIFT,
81};
82
83static struct clk sys_32k_ck = {
84 .name = "sys_32k_ck",
85 .clkdm_name = "prm_clkdm",
86 .rate = 32768,
87 .ops = &clkops_null,
88};
89
90static struct clk virt_12000000_ck = {
91 .name = "virt_12000000_ck",
92 .ops = &clkops_null,
93 .rate = 12000000,
94};
95
96static struct clk virt_13000000_ck = {
97 .name = "virt_13000000_ck",
98 .ops = &clkops_null,
99 .rate = 13000000,
100};
101
102static struct clk virt_16800000_ck = {
103 .name = "virt_16800000_ck",
104 .ops = &clkops_null,
105 .rate = 16800000,
106};
107
108static struct clk virt_27000000_ck = {
109 .name = "virt_27000000_ck",
110 .ops = &clkops_null,
111 .rate = 27000000,
112};
113
114static struct clk virt_38400000_ck = {
115 .name = "virt_38400000_ck",
116 .ops = &clkops_null,
117 .rate = 38400000,
118};
119
120static const struct clksel_rate div_1_5_rates[] = {
121 { .div = 1, .val = 5, .flags = RATE_IN_4430 },
122 { .div = 0 },
123};
124
125static const struct clksel_rate div_1_6_rates[] = {
126 { .div = 1, .val = 6, .flags = RATE_IN_4430 },
127 { .div = 0 },
128};
129
130static const struct clksel_rate div_1_7_rates[] = {
131 { .div = 1, .val = 7, .flags = RATE_IN_4430 },
132 { .div = 0 },
133};
134
135static const struct clksel sys_clkin_sel[] = {
136 { .parent = &virt_12000000_ck, .rates = div_1_1_rates },
137 { .parent = &virt_13000000_ck, .rates = div_1_2_rates },
138 { .parent = &virt_16800000_ck, .rates = div_1_3_rates },
139 { .parent = &virt_19200000_ck, .rates = div_1_4_rates },
140 { .parent = &virt_26000000_ck, .rates = div_1_5_rates },
141 { .parent = &virt_27000000_ck, .rates = div_1_6_rates },
142 { .parent = &virt_38400000_ck, .rates = div_1_7_rates },
143 { .parent = NULL },
144};
145
146static struct clk sys_clkin_ck = {
147 .name = "sys_clkin_ck",
148 .rate = 38400000,
149 .clksel = sys_clkin_sel,
150 .init = &omap2_init_clksel_parent,
151 .clksel_reg = OMAP4430_CM_SYS_CLKSEL,
152 .clksel_mask = OMAP4430_SYS_CLKSEL_MASK,
153 .ops = &clkops_null,
154 .recalc = &omap2_clksel_recalc,
155};
156
157static struct clk tie_low_clock_ck = {
158 .name = "tie_low_clock_ck",
159 .rate = 0,
160 .ops = &clkops_null,
161};
162
163static struct clk utmi_phy_clkout_ck = {
164 .name = "utmi_phy_clkout_ck",
165 .rate = 60000000,
166 .ops = &clkops_null,
167};
168
169static struct clk xclk60mhsp1_ck = {
170 .name = "xclk60mhsp1_ck",
171 .rate = 60000000,
172 .ops = &clkops_null,
173};
174
175static struct clk xclk60mhsp2_ck = {
176 .name = "xclk60mhsp2_ck",
177 .rate = 60000000,
178 .ops = &clkops_null,
179};
180
181static struct clk xclk60motg_ck = {
182 .name = "xclk60motg_ck",
183 .rate = 60000000,
184 .ops = &clkops_null,
185};
186
187/* Module clocks and DPLL outputs */
188
189static const struct clksel abe_dpll_bypass_clk_mux_sel[] = {
190 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
191 { .parent = &sys_32k_ck, .rates = div_1_1_rates },
192 { .parent = NULL },
193};
194
195static struct clk abe_dpll_bypass_clk_mux_ck = {
196 .name = "abe_dpll_bypass_clk_mux_ck",
197 .parent = &sys_clkin_ck,
198 .ops = &clkops_null,
199 .recalc = &followparent_recalc,
200};
201
202static struct clk abe_dpll_refclk_mux_ck = {
203 .name = "abe_dpll_refclk_mux_ck",
204 .parent = &sys_clkin_ck,
205 .clksel = abe_dpll_bypass_clk_mux_sel,
206 .init = &omap2_init_clksel_parent,
207 .clksel_reg = OMAP4430_CM_ABE_PLL_REF_CLKSEL,
208 .clksel_mask = OMAP4430_CLKSEL_0_0_MASK,
209 .ops = &clkops_null,
210 .recalc = &omap2_clksel_recalc,
211};
212
213/* DPLL_ABE */
214static struct dpll_data dpll_abe_dd = {
215 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_ABE,
216 .clk_bypass = &abe_dpll_bypass_clk_mux_ck,
217 .clk_ref = &abe_dpll_refclk_mux_ck,
218 .control_reg = OMAP4430_CM_CLKMODE_DPLL_ABE,
219 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
220 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_ABE,
221 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_ABE,
222 .mult_mask = OMAP4430_DPLL_MULT_MASK,
223 .div1_mask = OMAP4430_DPLL_DIV_MASK,
224 .enable_mask = OMAP4430_DPLL_EN_MASK,
225 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
226 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
227 .max_multiplier = 2047,
228 .max_divider = 128,
229 .min_divider = 1,
230};
231
232
233static struct clk dpll_abe_ck = {
234 .name = "dpll_abe_ck",
235 .parent = &abe_dpll_refclk_mux_ck,
236 .dpll_data = &dpll_abe_dd,
237 .init = &omap2_init_dpll_parent,
238 .ops = &clkops_omap3_noncore_dpll_ops,
239 .recalc = &omap4_dpll_regm4xen_recalc,
240 .round_rate = &omap4_dpll_regm4xen_round_rate,
241 .set_rate = &omap3_noncore_dpll_set_rate,
242};
243
244static struct clk dpll_abe_x2_ck = {
245 .name = "dpll_abe_x2_ck",
246 .parent = &dpll_abe_ck,
247 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE,
248 .flags = CLOCK_CLKOUTX2,
249 .ops = &clkops_omap4_dpllmx_ops,
250 .recalc = &omap3_clkoutx2_recalc,
251};
252
253static const struct clksel dpll_abe_m2x2_div[] = {
254 { .parent = &dpll_abe_x2_ck, .rates = div31_1to31_rates },
255 { .parent = NULL },
256};
257
258static struct clk dpll_abe_m2x2_ck = {
259 .name = "dpll_abe_m2x2_ck",
260 .parent = &dpll_abe_x2_ck,
261 .clksel = dpll_abe_m2x2_div,
262 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE,
263 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
264 .ops = &clkops_omap4_dpllmx_ops,
265 .recalc = &omap2_clksel_recalc,
266 .round_rate = &omap2_clksel_round_rate,
267 .set_rate = &omap2_clksel_set_rate,
268};
269
270static struct clk abe_24m_fclk = {
271 .name = "abe_24m_fclk",
272 .parent = &dpll_abe_m2x2_ck,
273 .ops = &clkops_null,
274 .fixed_div = 8,
275 .recalc = &omap_fixed_divisor_recalc,
276};
277
278static const struct clksel_rate div3_1to4_rates[] = {
279 { .div = 1, .val = 0, .flags = RATE_IN_4430 },
280 { .div = 2, .val = 1, .flags = RATE_IN_4430 },
281 { .div = 4, .val = 2, .flags = RATE_IN_4430 },
282 { .div = 0 },
283};
284
285static const struct clksel abe_clk_div[] = {
286 { .parent = &dpll_abe_m2x2_ck, .rates = div3_1to4_rates },
287 { .parent = NULL },
288};
289
290static struct clk abe_clk = {
291 .name = "abe_clk",
292 .parent = &dpll_abe_m2x2_ck,
293 .clksel = abe_clk_div,
294 .clksel_reg = OMAP4430_CM_CLKSEL_ABE,
295 .clksel_mask = OMAP4430_CLKSEL_OPP_MASK,
296 .ops = &clkops_null,
297 .recalc = &omap2_clksel_recalc,
298 .round_rate = &omap2_clksel_round_rate,
299 .set_rate = &omap2_clksel_set_rate,
300};
301
302static const struct clksel_rate div2_1to2_rates[] = {
303 { .div = 1, .val = 0, .flags = RATE_IN_4430 },
304 { .div = 2, .val = 1, .flags = RATE_IN_4430 },
305 { .div = 0 },
306};
307
308static const struct clksel aess_fclk_div[] = {
309 { .parent = &abe_clk, .rates = div2_1to2_rates },
310 { .parent = NULL },
311};
312
313static struct clk aess_fclk = {
314 .name = "aess_fclk",
315 .parent = &abe_clk,
316 .clksel = aess_fclk_div,
317 .clksel_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL,
318 .clksel_mask = OMAP4430_CLKSEL_AESS_FCLK_MASK,
319 .ops = &clkops_null,
320 .recalc = &omap2_clksel_recalc,
321 .round_rate = &omap2_clksel_round_rate,
322 .set_rate = &omap2_clksel_set_rate,
323};
324
325static struct clk dpll_abe_m3x2_ck = {
326 .name = "dpll_abe_m3x2_ck",
327 .parent = &dpll_abe_x2_ck,
328 .clksel = dpll_abe_m2x2_div,
329 .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_ABE,
330 .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
331 .ops = &clkops_omap4_dpllmx_ops,
332 .recalc = &omap2_clksel_recalc,
333 .round_rate = &omap2_clksel_round_rate,
334 .set_rate = &omap2_clksel_set_rate,
335};
336
337static const struct clksel core_hsd_byp_clk_mux_sel[] = {
338 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
339 { .parent = &dpll_abe_m3x2_ck, .rates = div_1_1_rates },
340 { .parent = NULL },
341};
342
343static struct clk core_hsd_byp_clk_mux_ck = {
344 .name = "core_hsd_byp_clk_mux_ck",
345 .parent = &sys_clkin_ck,
346 .clksel = core_hsd_byp_clk_mux_sel,
347 .init = &omap2_init_clksel_parent,
348 .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_CORE,
349 .clksel_mask = OMAP4430_DPLL_BYP_CLKSEL_MASK,
350 .ops = &clkops_null,
351 .recalc = &omap2_clksel_recalc,
352};
353
354/* DPLL_CORE */
355static struct dpll_data dpll_core_dd = {
356 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_CORE,
357 .clk_bypass = &core_hsd_byp_clk_mux_ck,
358 .clk_ref = &sys_clkin_ck,
359 .control_reg = OMAP4430_CM_CLKMODE_DPLL_CORE,
360 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
361 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_CORE,
362 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_CORE,
363 .mult_mask = OMAP4430_DPLL_MULT_MASK,
364 .div1_mask = OMAP4430_DPLL_DIV_MASK,
365 .enable_mask = OMAP4430_DPLL_EN_MASK,
366 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
367 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
368 .max_multiplier = 2047,
369 .max_divider = 128,
370 .min_divider = 1,
371};
372
373
374static struct clk dpll_core_ck = {
375 .name = "dpll_core_ck",
376 .parent = &sys_clkin_ck,
377 .dpll_data = &dpll_core_dd,
378 .init = &omap2_init_dpll_parent,
379 .ops = &clkops_omap3_core_dpll_ops,
380 .recalc = &omap3_dpll_recalc,
381};
382
383static struct clk dpll_core_x2_ck = {
384 .name = "dpll_core_x2_ck",
385 .parent = &dpll_core_ck,
386 .flags = CLOCK_CLKOUTX2,
387 .ops = &clkops_null,
388 .recalc = &omap3_clkoutx2_recalc,
389};
390
391static const struct clksel dpll_core_m6x2_div[] = {
392 { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
393 { .parent = NULL },
394};
395
396static struct clk dpll_core_m6x2_ck = {
397 .name = "dpll_core_m6x2_ck",
398 .parent = &dpll_core_x2_ck,
399 .clksel = dpll_core_m6x2_div,
400 .clksel_reg = OMAP4430_CM_DIV_M6_DPLL_CORE,
401 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
402 .ops = &clkops_omap4_dpllmx_ops,
403 .recalc = &omap2_clksel_recalc,
404 .round_rate = &omap2_clksel_round_rate,
405 .set_rate = &omap2_clksel_set_rate,
406};
407
408static const struct clksel dbgclk_mux_sel[] = {
409 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
410 { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates },
411 { .parent = NULL },
412};
413
414static struct clk dbgclk_mux_ck = {
415 .name = "dbgclk_mux_ck",
416 .parent = &sys_clkin_ck,
417 .ops = &clkops_null,
418 .recalc = &followparent_recalc,
419};
420
421static const struct clksel dpll_core_m2_div[] = {
422 { .parent = &dpll_core_ck, .rates = div31_1to31_rates },
423 { .parent = NULL },
424};
425
426static struct clk dpll_core_m2_ck = {
427 .name = "dpll_core_m2_ck",
428 .parent = &dpll_core_ck,
429 .clksel = dpll_core_m2_div,
430 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_CORE,
431 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
432 .ops = &clkops_omap4_dpllmx_ops,
433 .recalc = &omap2_clksel_recalc,
434 .round_rate = &omap2_clksel_round_rate,
435 .set_rate = &omap2_clksel_set_rate,
436};
437
438static struct clk ddrphy_ck = {
439 .name = "ddrphy_ck",
440 .parent = &dpll_core_m2_ck,
441 .ops = &clkops_null,
442 .clkdm_name = "l3_emif_clkdm",
443 .fixed_div = 2,
444 .recalc = &omap_fixed_divisor_recalc,
445};
446
447static struct clk dpll_core_m5x2_ck = {
448 .name = "dpll_core_m5x2_ck",
449 .parent = &dpll_core_x2_ck,
450 .clksel = dpll_core_m6x2_div,
451 .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_CORE,
452 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
453 .ops = &clkops_omap4_dpllmx_ops,
454 .recalc = &omap2_clksel_recalc,
455 .round_rate = &omap2_clksel_round_rate,
456 .set_rate = &omap2_clksel_set_rate,
457};
458
459static const struct clksel div_core_div[] = {
460 { .parent = &dpll_core_m5x2_ck, .rates = div2_1to2_rates },
461 { .parent = NULL },
462};
463
464static struct clk div_core_ck = {
465 .name = "div_core_ck",
466 .parent = &dpll_core_m5x2_ck,
467 .clksel = div_core_div,
468 .clksel_reg = OMAP4430_CM_CLKSEL_CORE,
469 .clksel_mask = OMAP4430_CLKSEL_CORE_MASK,
470 .ops = &clkops_null,
471 .recalc = &omap2_clksel_recalc,
472 .round_rate = &omap2_clksel_round_rate,
473 .set_rate = &omap2_clksel_set_rate,
474};
475
476static const struct clksel_rate div4_1to8_rates[] = {
477 { .div = 1, .val = 0, .flags = RATE_IN_4430 },
478 { .div = 2, .val = 1, .flags = RATE_IN_4430 },
479 { .div = 4, .val = 2, .flags = RATE_IN_4430 },
480 { .div = 8, .val = 3, .flags = RATE_IN_4430 },
481 { .div = 0 },
482};
483
484static const struct clksel div_iva_hs_clk_div[] = {
485 { .parent = &dpll_core_m5x2_ck, .rates = div4_1to8_rates },
486 { .parent = NULL },
487};
488
489static struct clk div_iva_hs_clk = {
490 .name = "div_iva_hs_clk",
491 .parent = &dpll_core_m5x2_ck,
492 .clksel = div_iva_hs_clk_div,
493 .clksel_reg = OMAP4430_CM_BYPCLK_DPLL_IVA,
494 .clksel_mask = OMAP4430_CLKSEL_0_1_MASK,
495 .ops = &clkops_null,
496 .recalc = &omap2_clksel_recalc,
497 .round_rate = &omap2_clksel_round_rate,
498 .set_rate = &omap2_clksel_set_rate,
499};
500
501static struct clk div_mpu_hs_clk = {
502 .name = "div_mpu_hs_clk",
503 .parent = &dpll_core_m5x2_ck,
504 .clksel = div_iva_hs_clk_div,
505 .clksel_reg = OMAP4430_CM_BYPCLK_DPLL_MPU,
506 .clksel_mask = OMAP4430_CLKSEL_0_1_MASK,
507 .ops = &clkops_null,
508 .recalc = &omap2_clksel_recalc,
509 .round_rate = &omap2_clksel_round_rate,
510 .set_rate = &omap2_clksel_set_rate,
511};
512
513static struct clk dpll_core_m4x2_ck = {
514 .name = "dpll_core_m4x2_ck",
515 .parent = &dpll_core_x2_ck,
516 .clksel = dpll_core_m6x2_div,
517 .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_CORE,
518 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
519 .ops = &clkops_omap4_dpllmx_ops,
520 .recalc = &omap2_clksel_recalc,
521 .round_rate = &omap2_clksel_round_rate,
522 .set_rate = &omap2_clksel_set_rate,
523};
524
525static struct clk dll_clk_div_ck = {
526 .name = "dll_clk_div_ck",
527 .parent = &dpll_core_m4x2_ck,
528 .ops = &clkops_null,
529 .fixed_div = 2,
530 .recalc = &omap_fixed_divisor_recalc,
531};
532
533static const struct clksel dpll_abe_m2_div[] = {
534 { .parent = &dpll_abe_ck, .rates = div31_1to31_rates },
535 { .parent = NULL },
536};
537
538static struct clk dpll_abe_m2_ck = {
539 .name = "dpll_abe_m2_ck",
540 .parent = &dpll_abe_ck,
541 .clksel = dpll_abe_m2_div,
542 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE,
543 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
544 .ops = &clkops_omap4_dpllmx_ops,
545 .recalc = &omap2_clksel_recalc,
546 .round_rate = &omap2_clksel_round_rate,
547 .set_rate = &omap2_clksel_set_rate,
548};
549
550static struct clk dpll_core_m3x2_ck = {
551 .name = "dpll_core_m3x2_ck",
552 .parent = &dpll_core_x2_ck,
553 .clksel = dpll_core_m6x2_div,
554 .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_CORE,
555 .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
556 .ops = &clkops_omap2_dflt,
557 .recalc = &omap2_clksel_recalc,
558 .round_rate = &omap2_clksel_round_rate,
559 .set_rate = &omap2_clksel_set_rate,
560 .enable_reg = OMAP4430_CM_DIV_M3_DPLL_CORE,
561 .enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
562};
563
564static struct clk dpll_core_m7x2_ck = {
565 .name = "dpll_core_m7x2_ck",
566 .parent = &dpll_core_x2_ck,
567 .clksel = dpll_core_m6x2_div,
568 .clksel_reg = OMAP4430_CM_DIV_M7_DPLL_CORE,
569 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
570 .ops = &clkops_omap4_dpllmx_ops,
571 .recalc = &omap2_clksel_recalc,
572 .round_rate = &omap2_clksel_round_rate,
573 .set_rate = &omap2_clksel_set_rate,
574};
575
576static const struct clksel iva_hsd_byp_clk_mux_sel[] = {
577 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
578 { .parent = &div_iva_hs_clk, .rates = div_1_1_rates },
579 { .parent = NULL },
580};
581
582static struct clk iva_hsd_byp_clk_mux_ck = {
583 .name = "iva_hsd_byp_clk_mux_ck",
584 .parent = &sys_clkin_ck,
585 .clksel = iva_hsd_byp_clk_mux_sel,
586 .init = &omap2_init_clksel_parent,
587 .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_IVA,
588 .clksel_mask = OMAP4430_DPLL_BYP_CLKSEL_MASK,
589 .ops = &clkops_null,
590 .recalc = &omap2_clksel_recalc,
591};
592
593/* DPLL_IVA */
594static struct dpll_data dpll_iva_dd = {
595 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_IVA,
596 .clk_bypass = &iva_hsd_byp_clk_mux_ck,
597 .clk_ref = &sys_clkin_ck,
598 .control_reg = OMAP4430_CM_CLKMODE_DPLL_IVA,
599 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
600 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_IVA,
601 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_IVA,
602 .mult_mask = OMAP4430_DPLL_MULT_MASK,
603 .div1_mask = OMAP4430_DPLL_DIV_MASK,
604 .enable_mask = OMAP4430_DPLL_EN_MASK,
605 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
606 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
607 .max_multiplier = 2047,
608 .max_divider = 128,
609 .min_divider = 1,
610};
611
612
613static struct clk dpll_iva_ck = {
614 .name = "dpll_iva_ck",
615 .parent = &sys_clkin_ck,
616 .dpll_data = &dpll_iva_dd,
617 .init = &omap2_init_dpll_parent,
618 .ops = &clkops_omap3_noncore_dpll_ops,
619 .recalc = &omap3_dpll_recalc,
620 .round_rate = &omap2_dpll_round_rate,
621 .set_rate = &omap3_noncore_dpll_set_rate,
622};
623
624static struct clk dpll_iva_x2_ck = {
625 .name = "dpll_iva_x2_ck",
626 .parent = &dpll_iva_ck,
627 .flags = CLOCK_CLKOUTX2,
628 .ops = &clkops_null,
629 .recalc = &omap3_clkoutx2_recalc,
630};
631
632static const struct clksel dpll_iva_m4x2_div[] = {
633 { .parent = &dpll_iva_x2_ck, .rates = div31_1to31_rates },
634 { .parent = NULL },
635};
636
637static struct clk dpll_iva_m4x2_ck = {
638 .name = "dpll_iva_m4x2_ck",
639 .parent = &dpll_iva_x2_ck,
640 .clksel = dpll_iva_m4x2_div,
641 .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_IVA,
642 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
643 .ops = &clkops_omap4_dpllmx_ops,
644 .recalc = &omap2_clksel_recalc,
645 .round_rate = &omap2_clksel_round_rate,
646 .set_rate = &omap2_clksel_set_rate,
647};
648
649static struct clk dpll_iva_m5x2_ck = {
650 .name = "dpll_iva_m5x2_ck",
651 .parent = &dpll_iva_x2_ck,
652 .clksel = dpll_iva_m4x2_div,
653 .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_IVA,
654 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
655 .ops = &clkops_omap4_dpllmx_ops,
656 .recalc = &omap2_clksel_recalc,
657 .round_rate = &omap2_clksel_round_rate,
658 .set_rate = &omap2_clksel_set_rate,
659};
660
661/* DPLL_MPU */
662static struct dpll_data dpll_mpu_dd = {
663 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_MPU,
664 .clk_bypass = &div_mpu_hs_clk,
665 .clk_ref = &sys_clkin_ck,
666 .control_reg = OMAP4430_CM_CLKMODE_DPLL_MPU,
667 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
668 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_MPU,
669 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_MPU,
670 .mult_mask = OMAP4430_DPLL_MULT_MASK,
671 .div1_mask = OMAP4430_DPLL_DIV_MASK,
672 .enable_mask = OMAP4430_DPLL_EN_MASK,
673 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
674 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
675 .max_multiplier = 2047,
676 .max_divider = 128,
677 .min_divider = 1,
678};
679
680
681static struct clk dpll_mpu_ck = {
682 .name = "dpll_mpu_ck",
683 .parent = &sys_clkin_ck,
684 .dpll_data = &dpll_mpu_dd,
685 .init = &omap2_init_dpll_parent,
686 .ops = &clkops_omap3_noncore_dpll_ops,
687 .recalc = &omap3_dpll_recalc,
688 .round_rate = &omap2_dpll_round_rate,
689 .set_rate = &omap3_noncore_dpll_set_rate,
690};
691
692static const struct clksel dpll_mpu_m2_div[] = {
693 { .parent = &dpll_mpu_ck, .rates = div31_1to31_rates },
694 { .parent = NULL },
695};
696
697static struct clk dpll_mpu_m2_ck = {
698 .name = "dpll_mpu_m2_ck",
699 .parent = &dpll_mpu_ck,
700 .clkdm_name = "cm_clkdm",
701 .clksel = dpll_mpu_m2_div,
702 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_MPU,
703 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
704 .ops = &clkops_omap4_dpllmx_ops,
705 .recalc = &omap2_clksel_recalc,
706 .round_rate = &omap2_clksel_round_rate,
707 .set_rate = &omap2_clksel_set_rate,
708};
709
710static struct clk per_hs_clk_div_ck = {
711 .name = "per_hs_clk_div_ck",
712 .parent = &dpll_abe_m3x2_ck,
713 .ops = &clkops_null,
714 .fixed_div = 2,
715 .recalc = &omap_fixed_divisor_recalc,
716};
717
718static const struct clksel per_hsd_byp_clk_mux_sel[] = {
719 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
720 { .parent = &per_hs_clk_div_ck, .rates = div_1_1_rates },
721 { .parent = NULL },
722};
723
724static struct clk per_hsd_byp_clk_mux_ck = {
725 .name = "per_hsd_byp_clk_mux_ck",
726 .parent = &sys_clkin_ck,
727 .clksel = per_hsd_byp_clk_mux_sel,
728 .init = &omap2_init_clksel_parent,
729 .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_PER,
730 .clksel_mask = OMAP4430_DPLL_BYP_CLKSEL_MASK,
731 .ops = &clkops_null,
732 .recalc = &omap2_clksel_recalc,
733};
734
735/* DPLL_PER */
736static struct dpll_data dpll_per_dd = {
737 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_PER,
738 .clk_bypass = &per_hsd_byp_clk_mux_ck,
739 .clk_ref = &sys_clkin_ck,
740 .control_reg = OMAP4430_CM_CLKMODE_DPLL_PER,
741 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
742 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_PER,
743 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_PER,
744 .mult_mask = OMAP4430_DPLL_MULT_MASK,
745 .div1_mask = OMAP4430_DPLL_DIV_MASK,
746 .enable_mask = OMAP4430_DPLL_EN_MASK,
747 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
748 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
749 .max_multiplier = 2047,
750 .max_divider = 128,
751 .min_divider = 1,
752};
753
754
755static struct clk dpll_per_ck = {
756 .name = "dpll_per_ck",
757 .parent = &sys_clkin_ck,
758 .dpll_data = &dpll_per_dd,
759 .init = &omap2_init_dpll_parent,
760 .ops = &clkops_omap3_noncore_dpll_ops,
761 .recalc = &omap3_dpll_recalc,
762 .round_rate = &omap2_dpll_round_rate,
763 .set_rate = &omap3_noncore_dpll_set_rate,
764};
765
766static const struct clksel dpll_per_m2_div[] = {
767 { .parent = &dpll_per_ck, .rates = div31_1to31_rates },
768 { .parent = NULL },
769};
770
771static struct clk dpll_per_m2_ck = {
772 .name = "dpll_per_m2_ck",
773 .parent = &dpll_per_ck,
774 .clksel = dpll_per_m2_div,
775 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER,
776 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
777 .ops = &clkops_omap4_dpllmx_ops,
778 .recalc = &omap2_clksel_recalc,
779 .round_rate = &omap2_clksel_round_rate,
780 .set_rate = &omap2_clksel_set_rate,
781};
782
783static struct clk dpll_per_x2_ck = {
784 .name = "dpll_per_x2_ck",
785 .parent = &dpll_per_ck,
786 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER,
787 .flags = CLOCK_CLKOUTX2,
788 .ops = &clkops_omap4_dpllmx_ops,
789 .recalc = &omap3_clkoutx2_recalc,
790};
791
792static const struct clksel dpll_per_m2x2_div[] = {
793 { .parent = &dpll_per_x2_ck, .rates = div31_1to31_rates },
794 { .parent = NULL },
795};
796
797static struct clk dpll_per_m2x2_ck = {
798 .name = "dpll_per_m2x2_ck",
799 .parent = &dpll_per_x2_ck,
800 .clksel = dpll_per_m2x2_div,
801 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER,
802 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
803 .ops = &clkops_omap4_dpllmx_ops,
804 .recalc = &omap2_clksel_recalc,
805 .round_rate = &omap2_clksel_round_rate,
806 .set_rate = &omap2_clksel_set_rate,
807};
808
809static struct clk dpll_per_m3x2_ck = {
810 .name = "dpll_per_m3x2_ck",
811 .parent = &dpll_per_x2_ck,
812 .clksel = dpll_per_m2x2_div,
813 .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_PER,
814 .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
815 .ops = &clkops_omap2_dflt,
816 .recalc = &omap2_clksel_recalc,
817 .round_rate = &omap2_clksel_round_rate,
818 .set_rate = &omap2_clksel_set_rate,
819 .enable_reg = OMAP4430_CM_DIV_M3_DPLL_PER,
820 .enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
821};
822
823static struct clk dpll_per_m4x2_ck = {
824 .name = "dpll_per_m4x2_ck",
825 .parent = &dpll_per_x2_ck,
826 .clksel = dpll_per_m2x2_div,
827 .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_PER,
828 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
829 .ops = &clkops_omap4_dpllmx_ops,
830 .recalc = &omap2_clksel_recalc,
831 .round_rate = &omap2_clksel_round_rate,
832 .set_rate = &omap2_clksel_set_rate,
833};
834
835static struct clk dpll_per_m5x2_ck = {
836 .name = "dpll_per_m5x2_ck",
837 .parent = &dpll_per_x2_ck,
838 .clksel = dpll_per_m2x2_div,
839 .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_PER,
840 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
841 .ops = &clkops_omap4_dpllmx_ops,
842 .recalc = &omap2_clksel_recalc,
843 .round_rate = &omap2_clksel_round_rate,
844 .set_rate = &omap2_clksel_set_rate,
845};
846
847static struct clk dpll_per_m6x2_ck = {
848 .name = "dpll_per_m6x2_ck",
849 .parent = &dpll_per_x2_ck,
850 .clksel = dpll_per_m2x2_div,
851 .clksel_reg = OMAP4430_CM_DIV_M6_DPLL_PER,
852 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
853 .ops = &clkops_omap4_dpllmx_ops,
854 .recalc = &omap2_clksel_recalc,
855 .round_rate = &omap2_clksel_round_rate,
856 .set_rate = &omap2_clksel_set_rate,
857};
858
859static struct clk dpll_per_m7x2_ck = {
860 .name = "dpll_per_m7x2_ck",
861 .parent = &dpll_per_x2_ck,
862 .clksel = dpll_per_m2x2_div,
863 .clksel_reg = OMAP4430_CM_DIV_M7_DPLL_PER,
864 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
865 .ops = &clkops_omap4_dpllmx_ops,
866 .recalc = &omap2_clksel_recalc,
867 .round_rate = &omap2_clksel_round_rate,
868 .set_rate = &omap2_clksel_set_rate,
869};
870
871static struct clk usb_hs_clk_div_ck = {
872 .name = "usb_hs_clk_div_ck",
873 .parent = &dpll_abe_m3x2_ck,
874 .ops = &clkops_null,
875 .fixed_div = 3,
876 .recalc = &omap_fixed_divisor_recalc,
877};
878
879/* DPLL_USB */
880static struct dpll_data dpll_usb_dd = {
881 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_USB,
882 .clk_bypass = &usb_hs_clk_div_ck,
883 .flags = DPLL_J_TYPE,
884 .clk_ref = &sys_clkin_ck,
885 .control_reg = OMAP4430_CM_CLKMODE_DPLL_USB,
886 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
887 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_USB,
888 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_USB,
889 .mult_mask = OMAP4430_DPLL_MULT_USB_MASK,
890 .div1_mask = OMAP4430_DPLL_DIV_0_7_MASK,
891 .enable_mask = OMAP4430_DPLL_EN_MASK,
892 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
893 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
894 .sddiv_mask = OMAP4430_DPLL_SD_DIV_MASK,
895 .max_multiplier = 4095,
896 .max_divider = 256,
897 .min_divider = 1,
898};
899
900
901static struct clk dpll_usb_ck = {
902 .name = "dpll_usb_ck",
903 .parent = &sys_clkin_ck,
904 .dpll_data = &dpll_usb_dd,
905 .init = &omap2_init_dpll_parent,
906 .ops = &clkops_omap3_noncore_dpll_ops,
907 .recalc = &omap3_dpll_recalc,
908 .round_rate = &omap2_dpll_round_rate,
909 .set_rate = &omap3_noncore_dpll_set_rate,
910 .clkdm_name = "l3_init_clkdm",
911};
912
913static struct clk dpll_usb_clkdcoldo_ck = {
914 .name = "dpll_usb_clkdcoldo_ck",
915 .parent = &dpll_usb_ck,
916 .clksel_reg = OMAP4430_CM_CLKDCOLDO_DPLL_USB,
917 .ops = &clkops_omap4_dpllmx_ops,
918 .recalc = &followparent_recalc,
919};
920
921static const struct clksel dpll_usb_m2_div[] = {
922 { .parent = &dpll_usb_ck, .rates = div31_1to31_rates },
923 { .parent = NULL },
924};
925
926static struct clk dpll_usb_m2_ck = {
927 .name = "dpll_usb_m2_ck",
928 .parent = &dpll_usb_ck,
929 .clksel = dpll_usb_m2_div,
930 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_USB,
931 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK,
932 .ops = &clkops_omap4_dpllmx_ops,
933 .recalc = &omap2_clksel_recalc,
934 .round_rate = &omap2_clksel_round_rate,
935 .set_rate = &omap2_clksel_set_rate,
936};
937
938static const struct clksel ducati_clk_mux_sel[] = {
939 { .parent = &div_core_ck, .rates = div_1_0_rates },
940 { .parent = &dpll_per_m6x2_ck, .rates = div_1_1_rates },
941 { .parent = NULL },
942};
943
944static struct clk ducati_clk_mux_ck = {
945 .name = "ducati_clk_mux_ck",
946 .parent = &div_core_ck,
947 .clksel = ducati_clk_mux_sel,
948 .init = &omap2_init_clksel_parent,
949 .clksel_reg = OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT,
950 .clksel_mask = OMAP4430_CLKSEL_0_0_MASK,
951 .ops = &clkops_null,
952 .recalc = &omap2_clksel_recalc,
953};
954
955static struct clk func_12m_fclk = {
956 .name = "func_12m_fclk",
957 .parent = &dpll_per_m2x2_ck,
958 .ops = &clkops_null,
959 .fixed_div = 16,
960 .recalc = &omap_fixed_divisor_recalc,
961};
962
963static struct clk func_24m_clk = {
964 .name = "func_24m_clk",
965 .parent = &dpll_per_m2_ck,
966 .ops = &clkops_null,
967 .fixed_div = 4,
968 .recalc = &omap_fixed_divisor_recalc,
969};
970
971static struct clk func_24mc_fclk = {
972 .name = "func_24mc_fclk",
973 .parent = &dpll_per_m2x2_ck,
974 .ops = &clkops_null,
975 .fixed_div = 8,
976 .recalc = &omap_fixed_divisor_recalc,
977};
978
979static const struct clksel_rate div2_4to8_rates[] = {
980 { .div = 4, .val = 0, .flags = RATE_IN_4430 },
981 { .div = 8, .val = 1, .flags = RATE_IN_4430 },
982 { .div = 0 },
983};
984
985static const struct clksel func_48m_fclk_div[] = {
986 { .parent = &dpll_per_m2x2_ck, .rates = div2_4to8_rates },
987 { .parent = NULL },
988};
989
990static struct clk func_48m_fclk = {
991 .name = "func_48m_fclk",
992 .parent = &dpll_per_m2x2_ck,
993 .clksel = func_48m_fclk_div,
994 .clksel_reg = OMAP4430_CM_SCALE_FCLK,
995 .clksel_mask = OMAP4430_SCALE_FCLK_MASK,
996 .ops = &clkops_null,
997 .recalc = &omap2_clksel_recalc,
998 .round_rate = &omap2_clksel_round_rate,
999 .set_rate = &omap2_clksel_set_rate,
1000};
1001
1002static struct clk func_48mc_fclk = {
1003 .name = "func_48mc_fclk",
1004 .parent = &dpll_per_m2x2_ck,
1005 .ops = &clkops_null,
1006 .fixed_div = 4,
1007 .recalc = &omap_fixed_divisor_recalc,
1008};
1009
1010static const struct clksel_rate div2_2to4_rates[] = {
1011 { .div = 2, .val = 0, .flags = RATE_IN_4430 },
1012 { .div = 4, .val = 1, .flags = RATE_IN_4430 },
1013 { .div = 0 },
1014};
1015
1016static const struct clksel func_64m_fclk_div[] = {
1017 { .parent = &dpll_per_m4x2_ck, .rates = div2_2to4_rates },
1018 { .parent = NULL },
1019};
1020
1021static struct clk func_64m_fclk = {
1022 .name = "func_64m_fclk",
1023 .parent = &dpll_per_m4x2_ck,
1024 .clksel = func_64m_fclk_div,
1025 .clksel_reg = OMAP4430_CM_SCALE_FCLK,
1026 .clksel_mask = OMAP4430_SCALE_FCLK_MASK,
1027 .ops = &clkops_null,
1028 .recalc = &omap2_clksel_recalc,
1029 .round_rate = &omap2_clksel_round_rate,
1030 .set_rate = &omap2_clksel_set_rate,
1031};
1032
1033static const struct clksel func_96m_fclk_div[] = {
1034 { .parent = &dpll_per_m2x2_ck, .rates = div2_2to4_rates },
1035 { .parent = NULL },
1036};
1037
1038static struct clk func_96m_fclk = {
1039 .name = "func_96m_fclk",
1040 .parent = &dpll_per_m2x2_ck,
1041 .clksel = func_96m_fclk_div,
1042 .clksel_reg = OMAP4430_CM_SCALE_FCLK,
1043 .clksel_mask = OMAP4430_SCALE_FCLK_MASK,
1044 .ops = &clkops_null,
1045 .recalc = &omap2_clksel_recalc,
1046 .round_rate = &omap2_clksel_round_rate,
1047 .set_rate = &omap2_clksel_set_rate,
1048};
1049
1050static const struct clksel_rate div2_1to8_rates[] = {
1051 { .div = 1, .val = 0, .flags = RATE_IN_4430 },
1052 { .div = 8, .val = 1, .flags = RATE_IN_4430 },
1053 { .div = 0 },
1054};
1055
1056static const struct clksel init_60m_fclk_div[] = {
1057 { .parent = &dpll_usb_m2_ck, .rates = div2_1to8_rates },
1058 { .parent = NULL },
1059};
1060
1061static struct clk init_60m_fclk = {
1062 .name = "init_60m_fclk",
1063 .parent = &dpll_usb_m2_ck,
1064 .clksel = init_60m_fclk_div,
1065 .clksel_reg = OMAP4430_CM_CLKSEL_USB_60MHZ,
1066 .clksel_mask = OMAP4430_CLKSEL_0_0_MASK,
1067 .ops = &clkops_null,
1068 .recalc = &omap2_clksel_recalc,
1069 .round_rate = &omap2_clksel_round_rate,
1070 .set_rate = &omap2_clksel_set_rate,
1071};
1072
1073static const struct clksel l3_div_div[] = {
1074 { .parent = &div_core_ck, .rates = div2_1to2_rates },
1075 { .parent = NULL },
1076};
1077
1078static struct clk l3_div_ck = {
1079 .name = "l3_div_ck",
1080 .parent = &div_core_ck,
1081 .clkdm_name = "cm_clkdm",
1082 .clksel = l3_div_div,
1083 .clksel_reg = OMAP4430_CM_CLKSEL_CORE,
1084 .clksel_mask = OMAP4430_CLKSEL_L3_MASK,
1085 .ops = &clkops_null,
1086 .recalc = &omap2_clksel_recalc,
1087 .round_rate = &omap2_clksel_round_rate,
1088 .set_rate = &omap2_clksel_set_rate,
1089};
1090
1091static const struct clksel l4_div_div[] = {
1092 { .parent = &l3_div_ck, .rates = div2_1to2_rates },
1093 { .parent = NULL },
1094};
1095
1096static struct clk l4_div_ck = {
1097 .name = "l4_div_ck",
1098 .parent = &l3_div_ck,
1099 .clksel = l4_div_div,
1100 .clksel_reg = OMAP4430_CM_CLKSEL_CORE,
1101 .clksel_mask = OMAP4430_CLKSEL_L4_MASK,
1102 .ops = &clkops_null,
1103 .recalc = &omap2_clksel_recalc,
1104 .round_rate = &omap2_clksel_round_rate,
1105 .set_rate = &omap2_clksel_set_rate,
1106};
1107
1108static struct clk lp_clk_div_ck = {
1109 .name = "lp_clk_div_ck",
1110 .parent = &dpll_abe_m2x2_ck,
1111 .ops = &clkops_null,
1112 .fixed_div = 16,
1113 .recalc = &omap_fixed_divisor_recalc,
1114};
1115
1116static const struct clksel l4_wkup_clk_mux_sel[] = {
1117 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
1118 { .parent = &lp_clk_div_ck, .rates = div_1_1_rates },
1119 { .parent = NULL },
1120};
1121
1122static struct clk l4_wkup_clk_mux_ck = {
1123 .name = "l4_wkup_clk_mux_ck",
1124 .parent = &sys_clkin_ck,
1125 .clksel = l4_wkup_clk_mux_sel,
1126 .init = &omap2_init_clksel_parent,
1127 .clksel_reg = OMAP4430_CM_L4_WKUP_CLKSEL,
1128 .clksel_mask = OMAP4430_CLKSEL_0_0_MASK,
1129 .ops = &clkops_null,
1130 .recalc = &omap2_clksel_recalc,
1131};
1132
1133static const struct clksel_rate div2_2to1_rates[] = {
1134 { .div = 1, .val = 1, .flags = RATE_IN_4430 },
1135 { .div = 2, .val = 0, .flags = RATE_IN_4430 },
1136 { .div = 0 },
1137};
1138
1139static const struct clksel ocp_abe_iclk_div[] = {
1140 { .parent = &aess_fclk, .rates = div2_2to1_rates },
1141 { .parent = NULL },
1142};
1143
1144static struct clk mpu_periphclk = {
1145 .name = "mpu_periphclk",
1146 .parent = &dpll_mpu_ck,
1147 .ops = &clkops_null,
1148 .fixed_div = 2,
1149 .recalc = &omap_fixed_divisor_recalc,
1150};
1151
1152static struct clk ocp_abe_iclk = {
1153 .name = "ocp_abe_iclk",
1154 .parent = &aess_fclk,
1155 .clksel = ocp_abe_iclk_div,
1156 .clksel_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL,
1157 .clksel_mask = OMAP4430_CLKSEL_AESS_FCLK_MASK,
1158 .ops = &clkops_null,
1159 .recalc = &omap2_clksel_recalc,
1160};
1161
1162static struct clk per_abe_24m_fclk = {
1163 .name = "per_abe_24m_fclk",
1164 .parent = &dpll_abe_m2_ck,
1165 .ops = &clkops_null,
1166 .fixed_div = 4,
1167 .recalc = &omap_fixed_divisor_recalc,
1168};
1169
1170static const struct clksel per_abe_nc_fclk_div[] = {
1171 { .parent = &dpll_abe_m2_ck, .rates = div2_1to2_rates },
1172 { .parent = NULL },
1173};
1174
1175static struct clk per_abe_nc_fclk = {
1176 .name = "per_abe_nc_fclk",
1177 .parent = &dpll_abe_m2_ck,
1178 .clksel = per_abe_nc_fclk_div,
1179 .clksel_reg = OMAP4430_CM_SCALE_FCLK,
1180 .clksel_mask = OMAP4430_SCALE_FCLK_MASK,
1181 .ops = &clkops_null,
1182 .recalc = &omap2_clksel_recalc,
1183 .round_rate = &omap2_clksel_round_rate,
1184 .set_rate = &omap2_clksel_set_rate,
1185};
1186
1187static const struct clksel pmd_stm_clock_mux_sel[] = {
1188 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
1189 { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates },
1190 { .parent = &tie_low_clock_ck, .rates = div_1_2_rates },
1191 { .parent = NULL },
1192};
1193
1194static struct clk pmd_stm_clock_mux_ck = {
1195 .name = "pmd_stm_clock_mux_ck",
1196 .parent = &sys_clkin_ck,
1197 .ops = &clkops_null,
1198 .recalc = &followparent_recalc,
1199};
1200
1201static struct clk pmd_trace_clk_mux_ck = {
1202 .name = "pmd_trace_clk_mux_ck",
1203 .parent = &sys_clkin_ck,
1204 .ops = &clkops_null,
1205 .recalc = &followparent_recalc,
1206};
1207
1208static const struct clksel syc_clk_div_div[] = {
1209 { .parent = &sys_clkin_ck, .rates = div2_1to2_rates },
1210 { .parent = NULL },
1211};
1212
1213static struct clk syc_clk_div_ck = {
1214 .name = "syc_clk_div_ck",
1215 .parent = &sys_clkin_ck,
1216 .clksel = syc_clk_div_div,
1217 .clksel_reg = OMAP4430_CM_ABE_DSS_SYS_CLKSEL,
1218 .clksel_mask = OMAP4430_CLKSEL_0_0_MASK,
1219 .ops = &clkops_null,
1220 .recalc = &omap2_clksel_recalc,
1221 .round_rate = &omap2_clksel_round_rate,
1222 .set_rate = &omap2_clksel_set_rate,
1223};
1224
1225/* Leaf clocks controlled by modules */
1226
1227static struct clk aes1_fck = {
1228 .name = "aes1_fck",
1229 .ops = &clkops_omap2_dflt,
1230 .enable_reg = OMAP4430_CM_L4SEC_AES1_CLKCTRL,
1231 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1232 .clkdm_name = "l4_secure_clkdm",
1233 .parent = &l3_div_ck,
1234 .recalc = &followparent_recalc,
1235};
1236
1237static struct clk aes2_fck = {
1238 .name = "aes2_fck",
1239 .ops = &clkops_omap2_dflt,
1240 .enable_reg = OMAP4430_CM_L4SEC_AES2_CLKCTRL,
1241 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1242 .clkdm_name = "l4_secure_clkdm",
1243 .parent = &l3_div_ck,
1244 .recalc = &followparent_recalc,
1245};
1246
1247static struct clk aess_fck = {
1248 .name = "aess_fck",
1249 .ops = &clkops_omap2_dflt,
1250 .enable_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL,
1251 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1252 .clkdm_name = "abe_clkdm",
1253 .parent = &aess_fclk,
1254 .recalc = &followparent_recalc,
1255};
1256
1257static struct clk bandgap_fclk = {
1258 .name = "bandgap_fclk",
1259 .ops = &clkops_omap2_dflt,
1260 .enable_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
1261 .enable_bit = OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT,
1262 .clkdm_name = "l4_wkup_clkdm",
1263 .parent = &sys_32k_ck,
1264 .recalc = &followparent_recalc,
1265};
1266
1267static struct clk des3des_fck = {
1268 .name = "des3des_fck",
1269 .ops = &clkops_omap2_dflt,
1270 .enable_reg = OMAP4430_CM_L4SEC_DES3DES_CLKCTRL,
1271 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1272 .clkdm_name = "l4_secure_clkdm",
1273 .parent = &l4_div_ck,
1274 .recalc = &followparent_recalc,
1275};
1276
1277static const struct clksel dmic_sync_mux_sel[] = {
1278 { .parent = &abe_24m_fclk, .rates = div_1_0_rates },
1279 { .parent = &syc_clk_div_ck, .rates = div_1_1_rates },
1280 { .parent = &func_24m_clk, .rates = div_1_2_rates },
1281 { .parent = NULL },
1282};
1283
1284static struct clk dmic_sync_mux_ck = {
1285 .name = "dmic_sync_mux_ck",
1286 .parent = &abe_24m_fclk,
1287 .clksel = dmic_sync_mux_sel,
1288 .init = &omap2_init_clksel_parent,
1289 .clksel_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1290 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1291 .ops = &clkops_null,
1292 .recalc = &omap2_clksel_recalc,
1293};
1294
1295static const struct clksel func_dmic_abe_gfclk_sel[] = {
1296 { .parent = &dmic_sync_mux_ck, .rates = div_1_0_rates },
1297 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1298 { .parent = &slimbus_clk, .rates = div_1_2_rates },
1299 { .parent = NULL },
1300};
1301
1302/* Merged func_dmic_abe_gfclk into dmic */
1303static struct clk dmic_fck = {
1304 .name = "dmic_fck",
1305 .parent = &dmic_sync_mux_ck,
1306 .clksel = func_dmic_abe_gfclk_sel,
1307 .init = &omap2_init_clksel_parent,
1308 .clksel_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1309 .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK,
1310 .ops = &clkops_omap2_dflt,
1311 .recalc = &omap2_clksel_recalc,
1312 .enable_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1313 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1314 .clkdm_name = "abe_clkdm",
1315};
1316
1317static struct clk dsp_fck = {
1318 .name = "dsp_fck",
1319 .ops = &clkops_omap2_dflt,
1320 .enable_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
1321 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1322 .clkdm_name = "tesla_clkdm",
1323 .parent = &dpll_iva_m4x2_ck,
1324 .recalc = &followparent_recalc,
1325};
1326
1327static struct clk dss_sys_clk = {
1328 .name = "dss_sys_clk",
1329 .ops = &clkops_omap2_dflt,
1330 .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1331 .enable_bit = OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT,
1332 .clkdm_name = "l3_dss_clkdm",
1333 .parent = &syc_clk_div_ck,
1334 .recalc = &followparent_recalc,
1335};
1336
1337static struct clk dss_tv_clk = {
1338 .name = "dss_tv_clk",
1339 .ops = &clkops_omap2_dflt,
1340 .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1341 .enable_bit = OMAP4430_OPTFCLKEN_TV_CLK_SHIFT,
1342 .clkdm_name = "l3_dss_clkdm",
1343 .parent = &extalt_clkin_ck,
1344 .recalc = &followparent_recalc,
1345};
1346
1347static struct clk dss_dss_clk = {
1348 .name = "dss_dss_clk",
1349 .ops = &clkops_omap2_dflt,
1350 .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1351 .enable_bit = OMAP4430_OPTFCLKEN_DSSCLK_SHIFT,
1352 .clkdm_name = "l3_dss_clkdm",
1353 .parent = &dpll_per_m5x2_ck,
1354 .recalc = &followparent_recalc,
1355};
1356
1357static const struct clksel_rate div3_8to32_rates[] = {
1358 { .div = 8, .val = 0, .flags = RATE_IN_4460 },
1359 { .div = 16, .val = 1, .flags = RATE_IN_4460 },
1360 { .div = 32, .val = 2, .flags = RATE_IN_4460 },
1361 { .div = 0 },
1362};
1363
1364static const struct clksel div_ts_div[] = {
1365 { .parent = &l4_wkup_clk_mux_ck, .rates = div3_8to32_rates },
1366 { .parent = NULL },
1367};
1368
1369static struct clk div_ts_ck = {
1370 .name = "div_ts_ck",
1371 .parent = &l4_wkup_clk_mux_ck,
1372 .clksel = div_ts_div,
1373 .clksel_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
1374 .clksel_mask = OMAP4430_CLKSEL_24_25_MASK,
1375 .ops = &clkops_null,
1376 .recalc = &omap2_clksel_recalc,
1377 .round_rate = &omap2_clksel_round_rate,
1378 .set_rate = &omap2_clksel_set_rate,
1379};
1380
1381static struct clk bandgap_ts_fclk = {
1382 .name = "bandgap_ts_fclk",
1383 .ops = &clkops_omap2_dflt,
1384 .enable_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
1385 .enable_bit = OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT,
1386 .clkdm_name = "l4_wkup_clkdm",
1387 .parent = &div_ts_ck,
1388 .recalc = &followparent_recalc,
1389};
1390
1391static struct clk dss_48mhz_clk = {
1392 .name = "dss_48mhz_clk",
1393 .ops = &clkops_omap2_dflt,
1394 .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1395 .enable_bit = OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT,
1396 .clkdm_name = "l3_dss_clkdm",
1397 .parent = &func_48mc_fclk,
1398 .recalc = &followparent_recalc,
1399};
1400
1401static struct clk dss_fck = {
1402 .name = "dss_fck",
1403 .ops = &clkops_omap2_dflt,
1404 .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1405 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1406 .clkdm_name = "l3_dss_clkdm",
1407 .parent = &l3_div_ck,
1408 .recalc = &followparent_recalc,
1409};
1410
1411static struct clk efuse_ctrl_cust_fck = {
1412 .name = "efuse_ctrl_cust_fck",
1413 .ops = &clkops_omap2_dflt,
1414 .enable_reg = OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL,
1415 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1416 .clkdm_name = "l4_cefuse_clkdm",
1417 .parent = &sys_clkin_ck,
1418 .recalc = &followparent_recalc,
1419};
1420
1421static struct clk emif1_fck = {
1422 .name = "emif1_fck",
1423 .ops = &clkops_omap2_dflt,
1424 .enable_reg = OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL,
1425 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1426 .flags = ENABLE_ON_INIT,
1427 .clkdm_name = "l3_emif_clkdm",
1428 .parent = &ddrphy_ck,
1429 .recalc = &followparent_recalc,
1430};
1431
1432static struct clk emif2_fck = {
1433 .name = "emif2_fck",
1434 .ops = &clkops_omap2_dflt,
1435 .enable_reg = OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL,
1436 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1437 .flags = ENABLE_ON_INIT,
1438 .clkdm_name = "l3_emif_clkdm",
1439 .parent = &ddrphy_ck,
1440 .recalc = &followparent_recalc,
1441};
1442
1443static const struct clksel fdif_fclk_div[] = {
1444 { .parent = &dpll_per_m4x2_ck, .rates = div3_1to4_rates },
1445 { .parent = NULL },
1446};
1447
1448/* Merged fdif_fclk into fdif */
1449static struct clk fdif_fck = {
1450 .name = "fdif_fck",
1451 .parent = &dpll_per_m4x2_ck,
1452 .clksel = fdif_fclk_div,
1453 .clksel_reg = OMAP4430_CM_CAM_FDIF_CLKCTRL,
1454 .clksel_mask = OMAP4430_CLKSEL_FCLK_MASK,
1455 .ops = &clkops_omap2_dflt,
1456 .recalc = &omap2_clksel_recalc,
1457 .round_rate = &omap2_clksel_round_rate,
1458 .set_rate = &omap2_clksel_set_rate,
1459 .enable_reg = OMAP4430_CM_CAM_FDIF_CLKCTRL,
1460 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1461 .clkdm_name = "iss_clkdm",
1462};
1463
1464static struct clk fpka_fck = {
1465 .name = "fpka_fck",
1466 .ops = &clkops_omap2_dflt,
1467 .enable_reg = OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL,
1468 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1469 .clkdm_name = "l4_secure_clkdm",
1470 .parent = &l4_div_ck,
1471 .recalc = &followparent_recalc,
1472};
1473
1474static struct clk gpio1_dbclk = {
1475 .name = "gpio1_dbclk",
1476 .ops = &clkops_omap2_dflt,
1477 .enable_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
1478 .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1479 .clkdm_name = "l4_wkup_clkdm",
1480 .parent = &sys_32k_ck,
1481 .recalc = &followparent_recalc,
1482};
1483
1484static struct clk gpio1_ick = {
1485 .name = "gpio1_ick",
1486 .ops = &clkops_omap2_dflt,
1487 .enable_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
1488 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1489 .clkdm_name = "l4_wkup_clkdm",
1490 .parent = &l4_wkup_clk_mux_ck,
1491 .recalc = &followparent_recalc,
1492};
1493
1494static struct clk gpio2_dbclk = {
1495 .name = "gpio2_dbclk",
1496 .ops = &clkops_omap2_dflt,
1497 .enable_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
1498 .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1499 .clkdm_name = "l4_per_clkdm",
1500 .parent = &sys_32k_ck,
1501 .recalc = &followparent_recalc,
1502};
1503
1504static struct clk gpio2_ick = {
1505 .name = "gpio2_ick",
1506 .ops = &clkops_omap2_dflt,
1507 .enable_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
1508 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1509 .clkdm_name = "l4_per_clkdm",
1510 .parent = &l4_div_ck,
1511 .recalc = &followparent_recalc,
1512};
1513
1514static struct clk gpio3_dbclk = {
1515 .name = "gpio3_dbclk",
1516 .ops = &clkops_omap2_dflt,
1517 .enable_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
1518 .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1519 .clkdm_name = "l4_per_clkdm",
1520 .parent = &sys_32k_ck,
1521 .recalc = &followparent_recalc,
1522};
1523
1524static struct clk gpio3_ick = {
1525 .name = "gpio3_ick",
1526 .ops = &clkops_omap2_dflt,
1527 .enable_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
1528 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1529 .clkdm_name = "l4_per_clkdm",
1530 .parent = &l4_div_ck,
1531 .recalc = &followparent_recalc,
1532};
1533
1534static struct clk gpio4_dbclk = {
1535 .name = "gpio4_dbclk",
1536 .ops = &clkops_omap2_dflt,
1537 .enable_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
1538 .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1539 .clkdm_name = "l4_per_clkdm",
1540 .parent = &sys_32k_ck,
1541 .recalc = &followparent_recalc,
1542};
1543
1544static struct clk gpio4_ick = {
1545 .name = "gpio4_ick",
1546 .ops = &clkops_omap2_dflt,
1547 .enable_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
1548 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1549 .clkdm_name = "l4_per_clkdm",
1550 .parent = &l4_div_ck,
1551 .recalc = &followparent_recalc,
1552};
1553
1554static struct clk gpio5_dbclk = {
1555 .name = "gpio5_dbclk",
1556 .ops = &clkops_omap2_dflt,
1557 .enable_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
1558 .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1559 .clkdm_name = "l4_per_clkdm",
1560 .parent = &sys_32k_ck,
1561 .recalc = &followparent_recalc,
1562};
1563
1564static struct clk gpio5_ick = {
1565 .name = "gpio5_ick",
1566 .ops = &clkops_omap2_dflt,
1567 .enable_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
1568 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1569 .clkdm_name = "l4_per_clkdm",
1570 .parent = &l4_div_ck,
1571 .recalc = &followparent_recalc,
1572};
1573
1574static struct clk gpio6_dbclk = {
1575 .name = "gpio6_dbclk",
1576 .ops = &clkops_omap2_dflt,
1577 .enable_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
1578 .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1579 .clkdm_name = "l4_per_clkdm",
1580 .parent = &sys_32k_ck,
1581 .recalc = &followparent_recalc,
1582};
1583
1584static struct clk gpio6_ick = {
1585 .name = "gpio6_ick",
1586 .ops = &clkops_omap2_dflt,
1587 .enable_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
1588 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1589 .clkdm_name = "l4_per_clkdm",
1590 .parent = &l4_div_ck,
1591 .recalc = &followparent_recalc,
1592};
1593
1594static struct clk gpmc_ick = {
1595 .name = "gpmc_ick",
1596 .ops = &clkops_omap2_dflt,
1597 .enable_reg = OMAP4430_CM_L3_2_GPMC_CLKCTRL,
1598 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1599 .flags = ENABLE_ON_INIT,
1600 .clkdm_name = "l3_2_clkdm",
1601 .parent = &l3_div_ck,
1602 .recalc = &followparent_recalc,
1603};
1604
1605static const struct clksel sgx_clk_mux_sel[] = {
1606 { .parent = &dpll_core_m7x2_ck, .rates = div_1_0_rates },
1607 { .parent = &dpll_per_m7x2_ck, .rates = div_1_1_rates },
1608 { .parent = NULL },
1609};
1610
1611/* Merged sgx_clk_mux into gpu */
1612static struct clk gpu_fck = {
1613 .name = "gpu_fck",
1614 .parent = &dpll_core_m7x2_ck,
1615 .clksel = sgx_clk_mux_sel,
1616 .init = &omap2_init_clksel_parent,
1617 .clksel_reg = OMAP4430_CM_GFX_GFX_CLKCTRL,
1618 .clksel_mask = OMAP4430_CLKSEL_SGX_FCLK_MASK,
1619 .ops = &clkops_omap2_dflt,
1620 .recalc = &omap2_clksel_recalc,
1621 .enable_reg = OMAP4430_CM_GFX_GFX_CLKCTRL,
1622 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1623 .clkdm_name = "l3_gfx_clkdm",
1624};
1625
1626static struct clk hdq1w_fck = {
1627 .name = "hdq1w_fck",
1628 .ops = &clkops_omap2_dflt,
1629 .enable_reg = OMAP4430_CM_L4PER_HDQ1W_CLKCTRL,
1630 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1631 .clkdm_name = "l4_per_clkdm",
1632 .parent = &func_12m_fclk,
1633 .recalc = &followparent_recalc,
1634};
1635
1636static const struct clksel hsi_fclk_div[] = {
1637 { .parent = &dpll_per_m2x2_ck, .rates = div3_1to4_rates },
1638 { .parent = NULL },
1639};
1640
1641/* Merged hsi_fclk into hsi */
1642static struct clk hsi_fck = {
1643 .name = "hsi_fck",
1644 .parent = &dpll_per_m2x2_ck,
1645 .clksel = hsi_fclk_div,
1646 .clksel_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
1647 .clksel_mask = OMAP4430_CLKSEL_24_25_MASK,
1648 .ops = &clkops_omap2_dflt,
1649 .recalc = &omap2_clksel_recalc,
1650 .round_rate = &omap2_clksel_round_rate,
1651 .set_rate = &omap2_clksel_set_rate,
1652 .enable_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
1653 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1654 .clkdm_name = "l3_init_clkdm",
1655};
1656
1657static struct clk i2c1_fck = {
1658 .name = "i2c1_fck",
1659 .ops = &clkops_omap2_dflt,
1660 .enable_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL,
1661 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1662 .clkdm_name = "l4_per_clkdm",
1663 .parent = &func_96m_fclk,
1664 .recalc = &followparent_recalc,
1665};
1666
1667static struct clk i2c2_fck = {
1668 .name = "i2c2_fck",
1669 .ops = &clkops_omap2_dflt,
1670 .enable_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL,
1671 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1672 .clkdm_name = "l4_per_clkdm",
1673 .parent = &func_96m_fclk,
1674 .recalc = &followparent_recalc,
1675};
1676
1677static struct clk i2c3_fck = {
1678 .name = "i2c3_fck",
1679 .ops = &clkops_omap2_dflt,
1680 .enable_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL,
1681 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1682 .clkdm_name = "l4_per_clkdm",
1683 .parent = &func_96m_fclk,
1684 .recalc = &followparent_recalc,
1685};
1686
1687static struct clk i2c4_fck = {
1688 .name = "i2c4_fck",
1689 .ops = &clkops_omap2_dflt,
1690 .enable_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL,
1691 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1692 .clkdm_name = "l4_per_clkdm",
1693 .parent = &func_96m_fclk,
1694 .recalc = &followparent_recalc,
1695};
1696
1697static struct clk ipu_fck = {
1698 .name = "ipu_fck",
1699 .ops = &clkops_omap2_dflt,
1700 .enable_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
1701 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1702 .clkdm_name = "ducati_clkdm",
1703 .parent = &ducati_clk_mux_ck,
1704 .recalc = &followparent_recalc,
1705};
1706
1707static struct clk iss_ctrlclk = {
1708 .name = "iss_ctrlclk",
1709 .ops = &clkops_omap2_dflt,
1710 .enable_reg = OMAP4430_CM_CAM_ISS_CLKCTRL,
1711 .enable_bit = OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT,
1712 .clkdm_name = "iss_clkdm",
1713 .parent = &func_96m_fclk,
1714 .recalc = &followparent_recalc,
1715};
1716
1717static struct clk iss_fck = {
1718 .name = "iss_fck",
1719 .ops = &clkops_omap2_dflt,
1720 .enable_reg = OMAP4430_CM_CAM_ISS_CLKCTRL,
1721 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1722 .clkdm_name = "iss_clkdm",
1723 .parent = &ducati_clk_mux_ck,
1724 .recalc = &followparent_recalc,
1725};
1726
1727static struct clk iva_fck = {
1728 .name = "iva_fck",
1729 .ops = &clkops_omap2_dflt,
1730 .enable_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
1731 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1732 .clkdm_name = "ivahd_clkdm",
1733 .parent = &dpll_iva_m5x2_ck,
1734 .recalc = &followparent_recalc,
1735};
1736
1737static struct clk kbd_fck = {
1738 .name = "kbd_fck",
1739 .ops = &clkops_omap2_dflt,
1740 .enable_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
1741 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1742 .clkdm_name = "l4_wkup_clkdm",
1743 .parent = &sys_32k_ck,
1744 .recalc = &followparent_recalc,
1745};
1746
1747static struct clk l3_instr_ick = {
1748 .name = "l3_instr_ick",
1749 .ops = &clkops_omap2_dflt,
1750 .enable_reg = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL,
1751 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1752 .flags = ENABLE_ON_INIT,
1753 .clkdm_name = "l3_instr_clkdm",
1754 .parent = &l3_div_ck,
1755 .recalc = &followparent_recalc,
1756};
1757
1758static struct clk l3_main_3_ick = {
1759 .name = "l3_main_3_ick",
1760 .ops = &clkops_omap2_dflt,
1761 .enable_reg = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL,
1762 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1763 .flags = ENABLE_ON_INIT,
1764 .clkdm_name = "l3_instr_clkdm",
1765 .parent = &l3_div_ck,
1766 .recalc = &followparent_recalc,
1767};
1768
1769static struct clk mcasp_sync_mux_ck = {
1770 .name = "mcasp_sync_mux_ck",
1771 .parent = &abe_24m_fclk,
1772 .clksel = dmic_sync_mux_sel,
1773 .init = &omap2_init_clksel_parent,
1774 .clksel_reg = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1775 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1776 .ops = &clkops_null,
1777 .recalc = &omap2_clksel_recalc,
1778};
1779
1780static const struct clksel func_mcasp_abe_gfclk_sel[] = {
1781 { .parent = &mcasp_sync_mux_ck, .rates = div_1_0_rates },
1782 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1783 { .parent = &slimbus_clk, .rates = div_1_2_rates },
1784 { .parent = NULL },
1785};
1786
1787/* Merged func_mcasp_abe_gfclk into mcasp */
1788static struct clk mcasp_fck = {
1789 .name = "mcasp_fck",
1790 .parent = &mcasp_sync_mux_ck,
1791 .clksel = func_mcasp_abe_gfclk_sel,
1792 .init = &omap2_init_clksel_parent,
1793 .clksel_reg = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1794 .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK,
1795 .ops = &clkops_omap2_dflt,
1796 .recalc = &omap2_clksel_recalc,
1797 .enable_reg = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1798 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1799 .clkdm_name = "abe_clkdm",
1800};
1801
1802static struct clk mcbsp1_sync_mux_ck = {
1803 .name = "mcbsp1_sync_mux_ck",
1804 .parent = &abe_24m_fclk,
1805 .clksel = dmic_sync_mux_sel,
1806 .init = &omap2_init_clksel_parent,
1807 .clksel_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1808 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1809 .ops = &clkops_null,
1810 .recalc = &omap2_clksel_recalc,
1811};
1812
1813static const struct clksel func_mcbsp1_gfclk_sel[] = {
1814 { .parent = &mcbsp1_sync_mux_ck, .rates = div_1_0_rates },
1815 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1816 { .parent = &slimbus_clk, .rates = div_1_2_rates },
1817 { .parent = NULL },
1818};
1819
1820/* Merged func_mcbsp1_gfclk into mcbsp1 */
1821static struct clk mcbsp1_fck = {
1822 .name = "mcbsp1_fck",
1823 .parent = &mcbsp1_sync_mux_ck,
1824 .clksel = func_mcbsp1_gfclk_sel,
1825 .init = &omap2_init_clksel_parent,
1826 .clksel_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1827 .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK,
1828 .ops = &clkops_omap2_dflt,
1829 .recalc = &omap2_clksel_recalc,
1830 .enable_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1831 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1832 .clkdm_name = "abe_clkdm",
1833};
1834
1835static struct clk mcbsp2_sync_mux_ck = {
1836 .name = "mcbsp2_sync_mux_ck",
1837 .parent = &abe_24m_fclk,
1838 .clksel = dmic_sync_mux_sel,
1839 .init = &omap2_init_clksel_parent,
1840 .clksel_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1841 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1842 .ops = &clkops_null,
1843 .recalc = &omap2_clksel_recalc,
1844};
1845
1846static const struct clksel func_mcbsp2_gfclk_sel[] = {
1847 { .parent = &mcbsp2_sync_mux_ck, .rates = div_1_0_rates },
1848 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1849 { .parent = &slimbus_clk, .rates = div_1_2_rates },
1850 { .parent = NULL },
1851};
1852
1853/* Merged func_mcbsp2_gfclk into mcbsp2 */
1854static struct clk mcbsp2_fck = {
1855 .name = "mcbsp2_fck",
1856 .parent = &mcbsp2_sync_mux_ck,
1857 .clksel = func_mcbsp2_gfclk_sel,
1858 .init = &omap2_init_clksel_parent,
1859 .clksel_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1860 .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK,
1861 .ops = &clkops_omap2_dflt,
1862 .recalc = &omap2_clksel_recalc,
1863 .enable_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1864 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1865 .clkdm_name = "abe_clkdm",
1866};
1867
1868static struct clk mcbsp3_sync_mux_ck = {
1869 .name = "mcbsp3_sync_mux_ck",
1870 .parent = &abe_24m_fclk,
1871 .clksel = dmic_sync_mux_sel,
1872 .init = &omap2_init_clksel_parent,
1873 .clksel_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
1874 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1875 .ops = &clkops_null,
1876 .recalc = &omap2_clksel_recalc,
1877};
1878
1879static const struct clksel func_mcbsp3_gfclk_sel[] = {
1880 { .parent = &mcbsp3_sync_mux_ck, .rates = div_1_0_rates },
1881 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1882 { .parent = &slimbus_clk, .rates = div_1_2_rates },
1883 { .parent = NULL },
1884};
1885
1886/* Merged func_mcbsp3_gfclk into mcbsp3 */
1887static struct clk mcbsp3_fck = {
1888 .name = "mcbsp3_fck",
1889 .parent = &mcbsp3_sync_mux_ck,
1890 .clksel = func_mcbsp3_gfclk_sel,
1891 .init = &omap2_init_clksel_parent,
1892 .clksel_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
1893 .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK,
1894 .ops = &clkops_omap2_dflt,
1895 .recalc = &omap2_clksel_recalc,
1896 .enable_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
1897 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1898 .clkdm_name = "abe_clkdm",
1899};
1900
1901static const struct clksel mcbsp4_sync_mux_sel[] = {
1902 { .parent = &func_96m_fclk, .rates = div_1_0_rates },
1903 { .parent = &per_abe_nc_fclk, .rates = div_1_1_rates },
1904 { .parent = NULL },
1905};
1906
1907static struct clk mcbsp4_sync_mux_ck = {
1908 .name = "mcbsp4_sync_mux_ck",
1909 .parent = &func_96m_fclk,
1910 .clksel = mcbsp4_sync_mux_sel,
1911 .init = &omap2_init_clksel_parent,
1912 .clksel_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
1913 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1914 .ops = &clkops_null,
1915 .recalc = &omap2_clksel_recalc,
1916};
1917
1918static const struct clksel per_mcbsp4_gfclk_sel[] = {
1919 { .parent = &mcbsp4_sync_mux_ck, .rates = div_1_0_rates },
1920 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1921 { .parent = NULL },
1922};
1923
1924/* Merged per_mcbsp4_gfclk into mcbsp4 */
1925static struct clk mcbsp4_fck = {
1926 .name = "mcbsp4_fck",
1927 .parent = &mcbsp4_sync_mux_ck,
1928 .clksel = per_mcbsp4_gfclk_sel,
1929 .init = &omap2_init_clksel_parent,
1930 .clksel_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
1931 .clksel_mask = OMAP4430_CLKSEL_SOURCE_24_24_MASK,
1932 .ops = &clkops_omap2_dflt,
1933 .recalc = &omap2_clksel_recalc,
1934 .enable_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
1935 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1936 .clkdm_name = "l4_per_clkdm",
1937};
1938
1939static struct clk mcpdm_fck = {
1940 .name = "mcpdm_fck",
1941 .ops = &clkops_omap2_dflt,
1942 .enable_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL,
1943 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1944 .clkdm_name = "abe_clkdm",
1945 .parent = &pad_clks_ck,
1946 .recalc = &followparent_recalc,
1947};
1948
1949static struct clk mcspi1_fck = {
1950 .name = "mcspi1_fck",
1951 .ops = &clkops_omap2_dflt,
1952 .enable_reg = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
1953 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1954 .clkdm_name = "l4_per_clkdm",
1955 .parent = &func_48m_fclk,
1956 .recalc = &followparent_recalc,
1957};
1958
1959static struct clk mcspi2_fck = {
1960 .name = "mcspi2_fck",
1961 .ops = &clkops_omap2_dflt,
1962 .enable_reg = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
1963 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1964 .clkdm_name = "l4_per_clkdm",
1965 .parent = &func_48m_fclk,
1966 .recalc = &followparent_recalc,
1967};
1968
1969static struct clk mcspi3_fck = {
1970 .name = "mcspi3_fck",
1971 .ops = &clkops_omap2_dflt,
1972 .enable_reg = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
1973 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1974 .clkdm_name = "l4_per_clkdm",
1975 .parent = &func_48m_fclk,
1976 .recalc = &followparent_recalc,
1977};
1978
1979static struct clk mcspi4_fck = {
1980 .name = "mcspi4_fck",
1981 .ops = &clkops_omap2_dflt,
1982 .enable_reg = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
1983 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1984 .clkdm_name = "l4_per_clkdm",
1985 .parent = &func_48m_fclk,
1986 .recalc = &followparent_recalc,
1987};
1988
1989static const struct clksel hsmmc1_fclk_sel[] = {
1990 { .parent = &func_64m_fclk, .rates = div_1_0_rates },
1991 { .parent = &func_96m_fclk, .rates = div_1_1_rates },
1992 { .parent = NULL },
1993};
1994
1995/* Merged hsmmc1_fclk into mmc1 */
1996static struct clk mmc1_fck = {
1997 .name = "mmc1_fck",
1998 .parent = &func_64m_fclk,
1999 .clksel = hsmmc1_fclk_sel,
2000 .init = &omap2_init_clksel_parent,
2001 .clksel_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
2002 .clksel_mask = OMAP4430_CLKSEL_MASK,
2003 .ops = &clkops_omap2_dflt,
2004 .recalc = &omap2_clksel_recalc,
2005 .enable_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
2006 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2007 .clkdm_name = "l3_init_clkdm",
2008};
2009
2010/* Merged hsmmc2_fclk into mmc2 */
2011static struct clk mmc2_fck = {
2012 .name = "mmc2_fck",
2013 .parent = &func_64m_fclk,
2014 .clksel = hsmmc1_fclk_sel,
2015 .init = &omap2_init_clksel_parent,
2016 .clksel_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
2017 .clksel_mask = OMAP4430_CLKSEL_MASK,
2018 .ops = &clkops_omap2_dflt,
2019 .recalc = &omap2_clksel_recalc,
2020 .enable_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
2021 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2022 .clkdm_name = "l3_init_clkdm",
2023};
2024
2025static struct clk mmc3_fck = {
2026 .name = "mmc3_fck",
2027 .ops = &clkops_omap2_dflt,
2028 .enable_reg = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL,
2029 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2030 .clkdm_name = "l4_per_clkdm",
2031 .parent = &func_48m_fclk,
2032 .recalc = &followparent_recalc,
2033};
2034
2035static struct clk mmc4_fck = {
2036 .name = "mmc4_fck",
2037 .ops = &clkops_omap2_dflt,
2038 .enable_reg = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL,
2039 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2040 .clkdm_name = "l4_per_clkdm",
2041 .parent = &func_48m_fclk,
2042 .recalc = &followparent_recalc,
2043};
2044
2045static struct clk mmc5_fck = {
2046 .name = "mmc5_fck",
2047 .ops = &clkops_omap2_dflt,
2048 .enable_reg = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL,
2049 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2050 .clkdm_name = "l4_per_clkdm",
2051 .parent = &func_48m_fclk,
2052 .recalc = &followparent_recalc,
2053};
2054
2055static struct clk ocp2scp_usb_phy_phy_48m = {
2056 .name = "ocp2scp_usb_phy_phy_48m",
2057 .ops = &clkops_omap2_dflt,
2058 .enable_reg = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
2059 .enable_bit = OMAP4430_OPTFCLKEN_PHY_48M_SHIFT,
2060 .clkdm_name = "l3_init_clkdm",
2061 .parent = &func_48m_fclk,
2062 .recalc = &followparent_recalc,
2063};
2064
2065static struct clk ocp2scp_usb_phy_ick = {
2066 .name = "ocp2scp_usb_phy_ick",
2067 .ops = &clkops_omap2_dflt,
2068 .enable_reg = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
2069 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2070 .clkdm_name = "l3_init_clkdm",
2071 .parent = &l4_div_ck,
2072 .recalc = &followparent_recalc,
2073};
2074
2075static struct clk ocp_wp_noc_ick = {
2076 .name = "ocp_wp_noc_ick",
2077 .ops = &clkops_omap2_dflt,
2078 .enable_reg = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL,
2079 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2080 .flags = ENABLE_ON_INIT,
2081 .clkdm_name = "l3_instr_clkdm",
2082 .parent = &l3_div_ck,
2083 .recalc = &followparent_recalc,
2084};
2085
2086static struct clk rng_ick = {
2087 .name = "rng_ick",
2088 .ops = &clkops_omap2_dflt,
2089 .enable_reg = OMAP4430_CM_L4SEC_RNG_CLKCTRL,
2090 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2091 .clkdm_name = "l4_secure_clkdm",
2092 .parent = &l4_div_ck,
2093 .recalc = &followparent_recalc,
2094};
2095
2096static struct clk sha2md5_fck = {
2097 .name = "sha2md5_fck",
2098 .ops = &clkops_omap2_dflt,
2099 .enable_reg = OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL,
2100 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2101 .clkdm_name = "l4_secure_clkdm",
2102 .parent = &l3_div_ck,
2103 .recalc = &followparent_recalc,
2104};
2105
2106static struct clk sl2if_ick = {
2107 .name = "sl2if_ick",
2108 .ops = &clkops_omap2_dflt,
2109 .enable_reg = OMAP4430_CM_IVAHD_SL2_CLKCTRL,
2110 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2111 .clkdm_name = "ivahd_clkdm",
2112 .parent = &dpll_iva_m5x2_ck,
2113 .recalc = &followparent_recalc,
2114};
2115
2116static struct clk slimbus1_fclk_1 = {
2117 .name = "slimbus1_fclk_1",
2118 .ops = &clkops_omap2_dflt,
2119 .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2120 .enable_bit = OMAP4430_OPTFCLKEN_FCLK1_SHIFT,
2121 .clkdm_name = "abe_clkdm",
2122 .parent = &func_24m_clk,
2123 .recalc = &followparent_recalc,
2124};
2125
2126static struct clk slimbus1_fclk_0 = {
2127 .name = "slimbus1_fclk_0",
2128 .ops = &clkops_omap2_dflt,
2129 .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2130 .enable_bit = OMAP4430_OPTFCLKEN_FCLK0_SHIFT,
2131 .clkdm_name = "abe_clkdm",
2132 .parent = &abe_24m_fclk,
2133 .recalc = &followparent_recalc,
2134};
2135
2136static struct clk slimbus1_fclk_2 = {
2137 .name = "slimbus1_fclk_2",
2138 .ops = &clkops_omap2_dflt,
2139 .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2140 .enable_bit = OMAP4430_OPTFCLKEN_FCLK2_SHIFT,
2141 .clkdm_name = "abe_clkdm",
2142 .parent = &pad_clks_ck,
2143 .recalc = &followparent_recalc,
2144};
2145
2146static struct clk slimbus1_slimbus_clk = {
2147 .name = "slimbus1_slimbus_clk",
2148 .ops = &clkops_omap2_dflt,
2149 .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2150 .enable_bit = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT,
2151 .clkdm_name = "abe_clkdm",
2152 .parent = &slimbus_clk,
2153 .recalc = &followparent_recalc,
2154};
2155
2156static struct clk slimbus1_fck = {
2157 .name = "slimbus1_fck",
2158 .ops = &clkops_omap2_dflt,
2159 .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2160 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2161 .clkdm_name = "abe_clkdm",
2162 .parent = &ocp_abe_iclk,
2163 .recalc = &followparent_recalc,
2164};
2165
2166static struct clk slimbus2_fclk_1 = {
2167 .name = "slimbus2_fclk_1",
2168 .ops = &clkops_omap2_dflt,
2169 .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2170 .enable_bit = OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT,
2171 .clkdm_name = "l4_per_clkdm",
2172 .parent = &per_abe_24m_fclk,
2173 .recalc = &followparent_recalc,
2174};
2175
2176static struct clk slimbus2_fclk_0 = {
2177 .name = "slimbus2_fclk_0",
2178 .ops = &clkops_omap2_dflt,
2179 .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2180 .enable_bit = OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT,
2181 .clkdm_name = "l4_per_clkdm",
2182 .parent = &func_24mc_fclk,
2183 .recalc = &followparent_recalc,
2184};
2185
2186static struct clk slimbus2_slimbus_clk = {
2187 .name = "slimbus2_slimbus_clk",
2188 .ops = &clkops_omap2_dflt,
2189 .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2190 .enable_bit = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT,
2191 .clkdm_name = "l4_per_clkdm",
2192 .parent = &pad_slimbus_core_clks_ck,
2193 .recalc = &followparent_recalc,
2194};
2195
2196static struct clk slimbus2_fck = {
2197 .name = "slimbus2_fck",
2198 .ops = &clkops_omap2_dflt,
2199 .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2200 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2201 .clkdm_name = "l4_per_clkdm",
2202 .parent = &l4_div_ck,
2203 .recalc = &followparent_recalc,
2204};
2205
2206static struct clk smartreflex_core_fck = {
2207 .name = "smartreflex_core_fck",
2208 .ops = &clkops_omap2_dflt,
2209 .enable_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
2210 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2211 .clkdm_name = "l4_ao_clkdm",
2212 .parent = &l4_wkup_clk_mux_ck,
2213 .recalc = &followparent_recalc,
2214};
2215
2216static struct clk smartreflex_iva_fck = {
2217 .name = "smartreflex_iva_fck",
2218 .ops = &clkops_omap2_dflt,
2219 .enable_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
2220 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2221 .clkdm_name = "l4_ao_clkdm",
2222 .parent = &l4_wkup_clk_mux_ck,
2223 .recalc = &followparent_recalc,
2224};
2225
2226static struct clk smartreflex_mpu_fck = {
2227 .name = "smartreflex_mpu_fck",
2228 .ops = &clkops_omap2_dflt,
2229 .enable_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
2230 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2231 .clkdm_name = "l4_ao_clkdm",
2232 .parent = &l4_wkup_clk_mux_ck,
2233 .recalc = &followparent_recalc,
2234};
2235
2236/* Merged dmt1_clk_mux into timer1 */
2237static struct clk timer1_fck = {
2238 .name = "timer1_fck",
2239 .parent = &sys_clkin_ck,
2240 .clksel = abe_dpll_bypass_clk_mux_sel,
2241 .init = &omap2_init_clksel_parent,
2242 .clksel_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
2243 .clksel_mask = OMAP4430_CLKSEL_MASK,
2244 .ops = &clkops_omap2_dflt,
2245 .recalc = &omap2_clksel_recalc,
2246 .enable_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
2247 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2248 .clkdm_name = "l4_wkup_clkdm",
2249};
2250
2251/* Merged cm2_dm10_mux into timer10 */
2252static struct clk timer10_fck = {
2253 .name = "timer10_fck",
2254 .parent = &sys_clkin_ck,
2255 .clksel = abe_dpll_bypass_clk_mux_sel,
2256 .init = &omap2_init_clksel_parent,
2257 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
2258 .clksel_mask = OMAP4430_CLKSEL_MASK,
2259 .ops = &clkops_omap2_dflt,
2260 .recalc = &omap2_clksel_recalc,
2261 .enable_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
2262 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2263 .clkdm_name = "l4_per_clkdm",
2264};
2265
2266/* Merged cm2_dm11_mux into timer11 */
2267static struct clk timer11_fck = {
2268 .name = "timer11_fck",
2269 .parent = &sys_clkin_ck,
2270 .clksel = abe_dpll_bypass_clk_mux_sel,
2271 .init = &omap2_init_clksel_parent,
2272 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
2273 .clksel_mask = OMAP4430_CLKSEL_MASK,
2274 .ops = &clkops_omap2_dflt,
2275 .recalc = &omap2_clksel_recalc,
2276 .enable_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
2277 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2278 .clkdm_name = "l4_per_clkdm",
2279};
2280
2281/* Merged cm2_dm2_mux into timer2 */
2282static struct clk timer2_fck = {
2283 .name = "timer2_fck",
2284 .parent = &sys_clkin_ck,
2285 .clksel = abe_dpll_bypass_clk_mux_sel,
2286 .init = &omap2_init_clksel_parent,
2287 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
2288 .clksel_mask = OMAP4430_CLKSEL_MASK,
2289 .ops = &clkops_omap2_dflt,
2290 .recalc = &omap2_clksel_recalc,
2291 .enable_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
2292 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2293 .clkdm_name = "l4_per_clkdm",
2294};
2295
2296/* Merged cm2_dm3_mux into timer3 */
2297static struct clk timer3_fck = {
2298 .name = "timer3_fck",
2299 .parent = &sys_clkin_ck,
2300 .clksel = abe_dpll_bypass_clk_mux_sel,
2301 .init = &omap2_init_clksel_parent,
2302 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
2303 .clksel_mask = OMAP4430_CLKSEL_MASK,
2304 .ops = &clkops_omap2_dflt,
2305 .recalc = &omap2_clksel_recalc,
2306 .enable_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
2307 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2308 .clkdm_name = "l4_per_clkdm",
2309};
2310
2311/* Merged cm2_dm4_mux into timer4 */
2312static struct clk timer4_fck = {
2313 .name = "timer4_fck",
2314 .parent = &sys_clkin_ck,
2315 .clksel = abe_dpll_bypass_clk_mux_sel,
2316 .init = &omap2_init_clksel_parent,
2317 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
2318 .clksel_mask = OMAP4430_CLKSEL_MASK,
2319 .ops = &clkops_omap2_dflt,
2320 .recalc = &omap2_clksel_recalc,
2321 .enable_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
2322 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2323 .clkdm_name = "l4_per_clkdm",
2324};
2325
2326static const struct clksel timer5_sync_mux_sel[] = {
2327 { .parent = &syc_clk_div_ck, .rates = div_1_0_rates },
2328 { .parent = &sys_32k_ck, .rates = div_1_1_rates },
2329 { .parent = NULL },
2330};
2331
2332/* Merged timer5_sync_mux into timer5 */
2333static struct clk timer5_fck = {
2334 .name = "timer5_fck",
2335 .parent = &syc_clk_div_ck,
2336 .clksel = timer5_sync_mux_sel,
2337 .init = &omap2_init_clksel_parent,
2338 .clksel_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
2339 .clksel_mask = OMAP4430_CLKSEL_MASK,
2340 .ops = &clkops_omap2_dflt,
2341 .recalc = &omap2_clksel_recalc,
2342 .enable_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
2343 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2344 .clkdm_name = "abe_clkdm",
2345};
2346
2347/* Merged timer6_sync_mux into timer6 */
2348static struct clk timer6_fck = {
2349 .name = "timer6_fck",
2350 .parent = &syc_clk_div_ck,
2351 .clksel = timer5_sync_mux_sel,
2352 .init = &omap2_init_clksel_parent,
2353 .clksel_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
2354 .clksel_mask = OMAP4430_CLKSEL_MASK,
2355 .ops = &clkops_omap2_dflt,
2356 .recalc = &omap2_clksel_recalc,
2357 .enable_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
2358 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2359 .clkdm_name = "abe_clkdm",
2360};
2361
2362/* Merged timer7_sync_mux into timer7 */
2363static struct clk timer7_fck = {
2364 .name = "timer7_fck",
2365 .parent = &syc_clk_div_ck,
2366 .clksel = timer5_sync_mux_sel,
2367 .init = &omap2_init_clksel_parent,
2368 .clksel_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
2369 .clksel_mask = OMAP4430_CLKSEL_MASK,
2370 .ops = &clkops_omap2_dflt,
2371 .recalc = &omap2_clksel_recalc,
2372 .enable_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
2373 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2374 .clkdm_name = "abe_clkdm",
2375};
2376
2377/* Merged timer8_sync_mux into timer8 */
2378static struct clk timer8_fck = {
2379 .name = "timer8_fck",
2380 .parent = &syc_clk_div_ck,
2381 .clksel = timer5_sync_mux_sel,
2382 .init = &omap2_init_clksel_parent,
2383 .clksel_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
2384 .clksel_mask = OMAP4430_CLKSEL_MASK,
2385 .ops = &clkops_omap2_dflt,
2386 .recalc = &omap2_clksel_recalc,
2387 .enable_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
2388 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2389 .clkdm_name = "abe_clkdm",
2390};
2391
2392/* Merged cm2_dm9_mux into timer9 */
2393static struct clk timer9_fck = {
2394 .name = "timer9_fck",
2395 .parent = &sys_clkin_ck,
2396 .clksel = abe_dpll_bypass_clk_mux_sel,
2397 .init = &omap2_init_clksel_parent,
2398 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
2399 .clksel_mask = OMAP4430_CLKSEL_MASK,
2400 .ops = &clkops_omap2_dflt,
2401 .recalc = &omap2_clksel_recalc,
2402 .enable_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
2403 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2404 .clkdm_name = "l4_per_clkdm",
2405};
2406
2407static struct clk uart1_fck = {
2408 .name = "uart1_fck",
2409 .ops = &clkops_omap2_dflt,
2410 .enable_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL,
2411 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2412 .clkdm_name = "l4_per_clkdm",
2413 .parent = &func_48m_fclk,
2414 .recalc = &followparent_recalc,
2415};
2416
2417static struct clk uart2_fck = {
2418 .name = "uart2_fck",
2419 .ops = &clkops_omap2_dflt,
2420 .enable_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL,
2421 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2422 .clkdm_name = "l4_per_clkdm",
2423 .parent = &func_48m_fclk,
2424 .recalc = &followparent_recalc,
2425};
2426
2427static struct clk uart3_fck = {
2428 .name = "uart3_fck",
2429 .ops = &clkops_omap2_dflt,
2430 .enable_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL,
2431 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2432 .clkdm_name = "l4_per_clkdm",
2433 .parent = &func_48m_fclk,
2434 .recalc = &followparent_recalc,
2435};
2436
2437static struct clk uart4_fck = {
2438 .name = "uart4_fck",
2439 .ops = &clkops_omap2_dflt,
2440 .enable_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL,
2441 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2442 .clkdm_name = "l4_per_clkdm",
2443 .parent = &func_48m_fclk,
2444 .recalc = &followparent_recalc,
2445};
2446
2447static struct clk usb_host_fs_fck = {
2448 .name = "usb_host_fs_fck",
2449 .ops = &clkops_omap2_dflt,
2450 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL,
2451 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2452 .clkdm_name = "l3_init_clkdm",
2453 .parent = &func_48mc_fclk,
2454 .recalc = &followparent_recalc,
2455};
2456
2457static const struct clksel utmi_p1_gfclk_sel[] = {
2458 { .parent = &init_60m_fclk, .rates = div_1_0_rates },
2459 { .parent = &xclk60mhsp1_ck, .rates = div_1_1_rates },
2460 { .parent = NULL },
2461};
2462
2463static struct clk utmi_p1_gfclk = {
2464 .name = "utmi_p1_gfclk",
2465 .parent = &init_60m_fclk,
2466 .clksel = utmi_p1_gfclk_sel,
2467 .init = &omap2_init_clksel_parent,
2468 .clksel_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2469 .clksel_mask = OMAP4430_CLKSEL_UTMI_P1_MASK,
2470 .ops = &clkops_null,
2471 .recalc = &omap2_clksel_recalc,
2472};
2473
2474static struct clk usb_host_hs_utmi_p1_clk = {
2475 .name = "usb_host_hs_utmi_p1_clk",
2476 .ops = &clkops_omap2_dflt,
2477 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2478 .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT,
2479 .clkdm_name = "l3_init_clkdm",
2480 .parent = &utmi_p1_gfclk,
2481 .recalc = &followparent_recalc,
2482};
2483
2484static const struct clksel utmi_p2_gfclk_sel[] = {
2485 { .parent = &init_60m_fclk, .rates = div_1_0_rates },
2486 { .parent = &xclk60mhsp2_ck, .rates = div_1_1_rates },
2487 { .parent = NULL },
2488};
2489
2490static struct clk utmi_p2_gfclk = {
2491 .name = "utmi_p2_gfclk",
2492 .parent = &init_60m_fclk,
2493 .clksel = utmi_p2_gfclk_sel,
2494 .init = &omap2_init_clksel_parent,
2495 .clksel_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2496 .clksel_mask = OMAP4430_CLKSEL_UTMI_P2_MASK,
2497 .ops = &clkops_null,
2498 .recalc = &omap2_clksel_recalc,
2499};
2500
2501static struct clk usb_host_hs_utmi_p2_clk = {
2502 .name = "usb_host_hs_utmi_p2_clk",
2503 .ops = &clkops_omap2_dflt,
2504 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2505 .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT,
2506 .clkdm_name = "l3_init_clkdm",
2507 .parent = &utmi_p2_gfclk,
2508 .recalc = &followparent_recalc,
2509};
2510
2511static struct clk usb_host_hs_utmi_p3_clk = {
2512 .name = "usb_host_hs_utmi_p3_clk",
2513 .ops = &clkops_omap2_dflt,
2514 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2515 .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT,
2516 .clkdm_name = "l3_init_clkdm",
2517 .parent = &init_60m_fclk,
2518 .recalc = &followparent_recalc,
2519};
2520
2521static struct clk usb_host_hs_hsic480m_p1_clk = {
2522 .name = "usb_host_hs_hsic480m_p1_clk",
2523 .ops = &clkops_omap2_dflt,
2524 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2525 .enable_bit = OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT,
2526 .clkdm_name = "l3_init_clkdm",
2527 .parent = &dpll_usb_m2_ck,
2528 .recalc = &followparent_recalc,
2529};
2530
2531static struct clk usb_host_hs_hsic60m_p1_clk = {
2532 .name = "usb_host_hs_hsic60m_p1_clk",
2533 .ops = &clkops_omap2_dflt,
2534 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2535 .enable_bit = OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT,
2536 .clkdm_name = "l3_init_clkdm",
2537 .parent = &init_60m_fclk,
2538 .recalc = &followparent_recalc,
2539};
2540
2541static struct clk usb_host_hs_hsic60m_p2_clk = {
2542 .name = "usb_host_hs_hsic60m_p2_clk",
2543 .ops = &clkops_omap2_dflt,
2544 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2545 .enable_bit = OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT,
2546 .clkdm_name = "l3_init_clkdm",
2547 .parent = &init_60m_fclk,
2548 .recalc = &followparent_recalc,
2549};
2550
2551static struct clk usb_host_hs_hsic480m_p2_clk = {
2552 .name = "usb_host_hs_hsic480m_p2_clk",
2553 .ops = &clkops_omap2_dflt,
2554 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2555 .enable_bit = OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT,
2556 .clkdm_name = "l3_init_clkdm",
2557 .parent = &dpll_usb_m2_ck,
2558 .recalc = &followparent_recalc,
2559};
2560
2561static struct clk usb_host_hs_func48mclk = {
2562 .name = "usb_host_hs_func48mclk",
2563 .ops = &clkops_omap2_dflt,
2564 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2565 .enable_bit = OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT,
2566 .clkdm_name = "l3_init_clkdm",
2567 .parent = &func_48mc_fclk,
2568 .recalc = &followparent_recalc,
2569};
2570
2571static struct clk usb_host_hs_fck = {
2572 .name = "usb_host_hs_fck",
2573 .ops = &clkops_omap2_dflt,
2574 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2575 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2576 .clkdm_name = "l3_init_clkdm",
2577 .parent = &init_60m_fclk,
2578 .recalc = &followparent_recalc,
2579};
2580
2581static const struct clksel otg_60m_gfclk_sel[] = {
2582 { .parent = &utmi_phy_clkout_ck, .rates = div_1_0_rates },
2583 { .parent = &xclk60motg_ck, .rates = div_1_1_rates },
2584 { .parent = NULL },
2585};
2586
2587static struct clk otg_60m_gfclk = {
2588 .name = "otg_60m_gfclk",
2589 .parent = &utmi_phy_clkout_ck,
2590 .clksel = otg_60m_gfclk_sel,
2591 .init = &omap2_init_clksel_parent,
2592 .clksel_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2593 .clksel_mask = OMAP4430_CLKSEL_60M_MASK,
2594 .ops = &clkops_null,
2595 .recalc = &omap2_clksel_recalc,
2596};
2597
2598static struct clk usb_otg_hs_xclk = {
2599 .name = "usb_otg_hs_xclk",
2600 .ops = &clkops_omap2_dflt,
2601 .enable_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2602 .enable_bit = OMAP4430_OPTFCLKEN_XCLK_SHIFT,
2603 .clkdm_name = "l3_init_clkdm",
2604 .parent = &otg_60m_gfclk,
2605 .recalc = &followparent_recalc,
2606};
2607
2608static struct clk usb_otg_hs_ick = {
2609 .name = "usb_otg_hs_ick",
2610 .ops = &clkops_omap2_dflt,
2611 .enable_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2612 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2613 .clkdm_name = "l3_init_clkdm",
2614 .parent = &l3_div_ck,
2615 .recalc = &followparent_recalc,
2616};
2617
2618static struct clk usb_phy_cm_clk32k = {
2619 .name = "usb_phy_cm_clk32k",
2620 .ops = &clkops_omap2_dflt,
2621 .enable_reg = OMAP4430_CM_ALWON_USBPHY_CLKCTRL,
2622 .enable_bit = OMAP4430_OPTFCLKEN_CLK32K_SHIFT,
2623 .clkdm_name = "l4_ao_clkdm",
2624 .parent = &sys_32k_ck,
2625 .recalc = &followparent_recalc,
2626};
2627
2628static struct clk usb_tll_hs_usb_ch2_clk = {
2629 .name = "usb_tll_hs_usb_ch2_clk",
2630 .ops = &clkops_omap2_dflt,
2631 .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2632 .enable_bit = OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT,
2633 .clkdm_name = "l3_init_clkdm",
2634 .parent = &init_60m_fclk,
2635 .recalc = &followparent_recalc,
2636};
2637
2638static struct clk usb_tll_hs_usb_ch0_clk = {
2639 .name = "usb_tll_hs_usb_ch0_clk",
2640 .ops = &clkops_omap2_dflt,
2641 .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2642 .enable_bit = OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT,
2643 .clkdm_name = "l3_init_clkdm",
2644 .parent = &init_60m_fclk,
2645 .recalc = &followparent_recalc,
2646};
2647
2648static struct clk usb_tll_hs_usb_ch1_clk = {
2649 .name = "usb_tll_hs_usb_ch1_clk",
2650 .ops = &clkops_omap2_dflt,
2651 .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2652 .enable_bit = OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT,
2653 .clkdm_name = "l3_init_clkdm",
2654 .parent = &init_60m_fclk,
2655 .recalc = &followparent_recalc,
2656};
2657
2658static struct clk usb_tll_hs_ick = {
2659 .name = "usb_tll_hs_ick",
2660 .ops = &clkops_omap2_dflt,
2661 .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2662 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2663 .clkdm_name = "l3_init_clkdm",
2664 .parent = &l4_div_ck,
2665 .recalc = &followparent_recalc,
2666};
2667
2668static const struct clksel_rate div2_14to18_rates[] = {
2669 { .div = 14, .val = 0, .flags = RATE_IN_4430 },
2670 { .div = 18, .val = 1, .flags = RATE_IN_4430 },
2671 { .div = 0 },
2672};
2673
2674static const struct clksel usim_fclk_div[] = {
2675 { .parent = &dpll_per_m4x2_ck, .rates = div2_14to18_rates },
2676 { .parent = NULL },
2677};
2678
2679static struct clk usim_ck = {
2680 .name = "usim_ck",
2681 .parent = &dpll_per_m4x2_ck,
2682 .clksel = usim_fclk_div,
2683 .clksel_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL,
2684 .clksel_mask = OMAP4430_CLKSEL_DIV_MASK,
2685 .ops = &clkops_null,
2686 .recalc = &omap2_clksel_recalc,
2687 .round_rate = &omap2_clksel_round_rate,
2688 .set_rate = &omap2_clksel_set_rate,
2689};
2690
2691static struct clk usim_fclk = {
2692 .name = "usim_fclk",
2693 .ops = &clkops_omap2_dflt,
2694 .enable_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL,
2695 .enable_bit = OMAP4430_OPTFCLKEN_FCLK_SHIFT,
2696 .clkdm_name = "l4_wkup_clkdm",
2697 .parent = &usim_ck,
2698 .recalc = &followparent_recalc,
2699};
2700
2701static struct clk usim_fck = {
2702 .name = "usim_fck",
2703 .ops = &clkops_omap2_dflt,
2704 .enable_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL,
2705 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2706 .clkdm_name = "l4_wkup_clkdm",
2707 .parent = &sys_32k_ck,
2708 .recalc = &followparent_recalc,
2709};
2710
2711static struct clk wd_timer2_fck = {
2712 .name = "wd_timer2_fck",
2713 .ops = &clkops_omap2_dflt,
2714 .enable_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
2715 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2716 .clkdm_name = "l4_wkup_clkdm",
2717 .parent = &sys_32k_ck,
2718 .recalc = &followparent_recalc,
2719};
2720
2721static struct clk wd_timer3_fck = {
2722 .name = "wd_timer3_fck",
2723 .ops = &clkops_omap2_dflt,
2724 .enable_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
2725 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2726 .clkdm_name = "abe_clkdm",
2727 .parent = &sys_32k_ck,
2728 .recalc = &followparent_recalc,
2729};
2730
2731/* Remaining optional clocks */
2732static const struct clksel stm_clk_div_div[] = {
2733 { .parent = &pmd_stm_clock_mux_ck, .rates = div3_1to4_rates },
2734 { .parent = NULL },
2735};
2736
2737static struct clk stm_clk_div_ck = {
2738 .name = "stm_clk_div_ck",
2739 .parent = &pmd_stm_clock_mux_ck,
2740 .clksel = stm_clk_div_div,
2741 .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
2742 .clksel_mask = OMAP4430_CLKSEL_PMD_STM_CLK_MASK,
2743 .ops = &clkops_null,
2744 .recalc = &omap2_clksel_recalc,
2745 .round_rate = &omap2_clksel_round_rate,
2746 .set_rate = &omap2_clksel_set_rate,
2747};
2748
2749static const struct clksel trace_clk_div_div[] = {
2750 { .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates },
2751 { .parent = NULL },
2752};
2753
2754static struct clk trace_clk_div_ck = {
2755 .name = "trace_clk_div_ck",
2756 .parent = &pmd_trace_clk_mux_ck,
2757 .clkdm_name = "emu_sys_clkdm",
2758 .clksel = trace_clk_div_div,
2759 .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
2760 .clksel_mask = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK,
2761 .ops = &clkops_null,
2762 .recalc = &omap2_clksel_recalc,
2763 .round_rate = &omap2_clksel_round_rate,
2764 .set_rate = &omap2_clksel_set_rate,
2765};
2766
2767/* SCRM aux clk nodes */
2768
2769static const struct clksel auxclk_src_sel[] = {
2770 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
2771 { .parent = &dpll_core_m3x2_ck, .rates = div_1_1_rates },
2772 { .parent = &dpll_per_m3x2_ck, .rates = div_1_2_rates },
2773 { .parent = NULL },
2774};
2775
2776static const struct clksel_rate div16_1to16_rates[] = {
2777 { .div = 1, .val = 0, .flags = RATE_IN_4430 },
2778 { .div = 2, .val = 1, .flags = RATE_IN_4430 },
2779 { .div = 3, .val = 2, .flags = RATE_IN_4430 },
2780 { .div = 4, .val = 3, .flags = RATE_IN_4430 },
2781 { .div = 5, .val = 4, .flags = RATE_IN_4430 },
2782 { .div = 6, .val = 5, .flags = RATE_IN_4430 },
2783 { .div = 7, .val = 6, .flags = RATE_IN_4430 },
2784 { .div = 8, .val = 7, .flags = RATE_IN_4430 },
2785 { .div = 9, .val = 8, .flags = RATE_IN_4430 },
2786 { .div = 10, .val = 9, .flags = RATE_IN_4430 },
2787 { .div = 11, .val = 10, .flags = RATE_IN_4430 },
2788 { .div = 12, .val = 11, .flags = RATE_IN_4430 },
2789 { .div = 13, .val = 12, .flags = RATE_IN_4430 },
2790 { .div = 14, .val = 13, .flags = RATE_IN_4430 },
2791 { .div = 15, .val = 14, .flags = RATE_IN_4430 },
2792 { .div = 16, .val = 15, .flags = RATE_IN_4430 },
2793 { .div = 0 },
2794};
2795
2796static struct clk auxclk0_src_ck = {
2797 .name = "auxclk0_src_ck",
2798 .parent = &sys_clkin_ck,
2799 .init = &omap2_init_clksel_parent,
2800 .ops = &clkops_omap2_dflt,
2801 .clksel = auxclk_src_sel,
2802 .clksel_reg = OMAP4_SCRM_AUXCLK0,
2803 .clksel_mask = OMAP4_SRCSELECT_MASK,
2804 .recalc = &omap2_clksel_recalc,
2805 .enable_reg = OMAP4_SCRM_AUXCLK0,
2806 .enable_bit = OMAP4_ENABLE_SHIFT,
2807};
2808
2809static const struct clksel auxclk0_sel[] = {
2810 { .parent = &auxclk0_src_ck, .rates = div16_1to16_rates },
2811 { .parent = NULL },
2812};
2813
2814static struct clk auxclk0_ck = {
2815 .name = "auxclk0_ck",
2816 .parent = &auxclk0_src_ck,
2817 .clksel = auxclk0_sel,
2818 .clksel_reg = OMAP4_SCRM_AUXCLK0,
2819 .clksel_mask = OMAP4_CLKDIV_MASK,
2820 .ops = &clkops_null,
2821 .recalc = &omap2_clksel_recalc,
2822 .round_rate = &omap2_clksel_round_rate,
2823 .set_rate = &omap2_clksel_set_rate,
2824};
2825
2826static struct clk auxclk1_src_ck = {
2827 .name = "auxclk1_src_ck",
2828 .parent = &sys_clkin_ck,
2829 .init = &omap2_init_clksel_parent,
2830 .ops = &clkops_omap2_dflt,
2831 .clksel = auxclk_src_sel,
2832 .clksel_reg = OMAP4_SCRM_AUXCLK1,
2833 .clksel_mask = OMAP4_SRCSELECT_MASK,
2834 .recalc = &omap2_clksel_recalc,
2835 .enable_reg = OMAP4_SCRM_AUXCLK1,
2836 .enable_bit = OMAP4_ENABLE_SHIFT,
2837};
2838
2839static const struct clksel auxclk1_sel[] = {
2840 { .parent = &auxclk1_src_ck, .rates = div16_1to16_rates },
2841 { .parent = NULL },
2842};
2843
2844static struct clk auxclk1_ck = {
2845 .name = "auxclk1_ck",
2846 .parent = &auxclk1_src_ck,
2847 .clksel = auxclk1_sel,
2848 .clksel_reg = OMAP4_SCRM_AUXCLK1,
2849 .clksel_mask = OMAP4_CLKDIV_MASK,
2850 .ops = &clkops_null,
2851 .recalc = &omap2_clksel_recalc,
2852 .round_rate = &omap2_clksel_round_rate,
2853 .set_rate = &omap2_clksel_set_rate,
2854};
2855
2856static struct clk auxclk2_src_ck = {
2857 .name = "auxclk2_src_ck",
2858 .parent = &sys_clkin_ck,
2859 .init = &omap2_init_clksel_parent,
2860 .ops = &clkops_omap2_dflt,
2861 .clksel = auxclk_src_sel,
2862 .clksel_reg = OMAP4_SCRM_AUXCLK2,
2863 .clksel_mask = OMAP4_SRCSELECT_MASK,
2864 .recalc = &omap2_clksel_recalc,
2865 .enable_reg = OMAP4_SCRM_AUXCLK2,
2866 .enable_bit = OMAP4_ENABLE_SHIFT,
2867};
2868
2869static const struct clksel auxclk2_sel[] = {
2870 { .parent = &auxclk2_src_ck, .rates = div16_1to16_rates },
2871 { .parent = NULL },
2872};
2873
2874static struct clk auxclk2_ck = {
2875 .name = "auxclk2_ck",
2876 .parent = &auxclk2_src_ck,
2877 .clksel = auxclk2_sel,
2878 .clksel_reg = OMAP4_SCRM_AUXCLK2,
2879 .clksel_mask = OMAP4_CLKDIV_MASK,
2880 .ops = &clkops_null,
2881 .recalc = &omap2_clksel_recalc,
2882 .round_rate = &omap2_clksel_round_rate,
2883 .set_rate = &omap2_clksel_set_rate,
2884};
2885
2886static struct clk auxclk3_src_ck = {
2887 .name = "auxclk3_src_ck",
2888 .parent = &sys_clkin_ck,
2889 .init = &omap2_init_clksel_parent,
2890 .ops = &clkops_omap2_dflt,
2891 .clksel = auxclk_src_sel,
2892 .clksel_reg = OMAP4_SCRM_AUXCLK3,
2893 .clksel_mask = OMAP4_SRCSELECT_MASK,
2894 .recalc = &omap2_clksel_recalc,
2895 .enable_reg = OMAP4_SCRM_AUXCLK3,
2896 .enable_bit = OMAP4_ENABLE_SHIFT,
2897};
2898
2899static const struct clksel auxclk3_sel[] = {
2900 { .parent = &auxclk3_src_ck, .rates = div16_1to16_rates },
2901 { .parent = NULL },
2902};
2903
2904static struct clk auxclk3_ck = {
2905 .name = "auxclk3_ck",
2906 .parent = &auxclk3_src_ck,
2907 .clksel = auxclk3_sel,
2908 .clksel_reg = OMAP4_SCRM_AUXCLK3,
2909 .clksel_mask = OMAP4_CLKDIV_MASK,
2910 .ops = &clkops_null,
2911 .recalc = &omap2_clksel_recalc,
2912 .round_rate = &omap2_clksel_round_rate,
2913 .set_rate = &omap2_clksel_set_rate,
2914};
2915
2916static struct clk auxclk4_src_ck = {
2917 .name = "auxclk4_src_ck",
2918 .parent = &sys_clkin_ck,
2919 .init = &omap2_init_clksel_parent,
2920 .ops = &clkops_omap2_dflt,
2921 .clksel = auxclk_src_sel,
2922 .clksel_reg = OMAP4_SCRM_AUXCLK4,
2923 .clksel_mask = OMAP4_SRCSELECT_MASK,
2924 .recalc = &omap2_clksel_recalc,
2925 .enable_reg = OMAP4_SCRM_AUXCLK4,
2926 .enable_bit = OMAP4_ENABLE_SHIFT,
2927};
2928
2929static const struct clksel auxclk4_sel[] = {
2930 { .parent = &auxclk4_src_ck, .rates = div16_1to16_rates },
2931 { .parent = NULL },
2932};
2933
2934static struct clk auxclk4_ck = {
2935 .name = "auxclk4_ck",
2936 .parent = &auxclk4_src_ck,
2937 .clksel = auxclk4_sel,
2938 .clksel_reg = OMAP4_SCRM_AUXCLK4,
2939 .clksel_mask = OMAP4_CLKDIV_MASK,
2940 .ops = &clkops_null,
2941 .recalc = &omap2_clksel_recalc,
2942 .round_rate = &omap2_clksel_round_rate,
2943 .set_rate = &omap2_clksel_set_rate,
2944};
2945
2946static struct clk auxclk5_src_ck = {
2947 .name = "auxclk5_src_ck",
2948 .parent = &sys_clkin_ck,
2949 .init = &omap2_init_clksel_parent,
2950 .ops = &clkops_omap2_dflt,
2951 .clksel = auxclk_src_sel,
2952 .clksel_reg = OMAP4_SCRM_AUXCLK5,
2953 .clksel_mask = OMAP4_SRCSELECT_MASK,
2954 .recalc = &omap2_clksel_recalc,
2955 .enable_reg = OMAP4_SCRM_AUXCLK5,
2956 .enable_bit = OMAP4_ENABLE_SHIFT,
2957};
2958
2959static const struct clksel auxclk5_sel[] = {
2960 { .parent = &auxclk5_src_ck, .rates = div16_1to16_rates },
2961 { .parent = NULL },
2962};
2963
2964static struct clk auxclk5_ck = {
2965 .name = "auxclk5_ck",
2966 .parent = &auxclk5_src_ck,
2967 .clksel = auxclk5_sel,
2968 .clksel_reg = OMAP4_SCRM_AUXCLK5,
2969 .clksel_mask = OMAP4_CLKDIV_MASK,
2970 .ops = &clkops_null,
2971 .recalc = &omap2_clksel_recalc,
2972 .round_rate = &omap2_clksel_round_rate,
2973 .set_rate = &omap2_clksel_set_rate,
2974};
2975
2976static const struct clksel auxclkreq_sel[] = {
2977 { .parent = &auxclk0_ck, .rates = div_1_0_rates },
2978 { .parent = &auxclk1_ck, .rates = div_1_1_rates },
2979 { .parent = &auxclk2_ck, .rates = div_1_2_rates },
2980 { .parent = &auxclk3_ck, .rates = div_1_3_rates },
2981 { .parent = &auxclk4_ck, .rates = div_1_4_rates },
2982 { .parent = &auxclk5_ck, .rates = div_1_5_rates },
2983 { .parent = NULL },
2984};
2985
2986static struct clk auxclkreq0_ck = {
2987 .name = "auxclkreq0_ck",
2988 .parent = &auxclk0_ck,
2989 .init = &omap2_init_clksel_parent,
2990 .ops = &clkops_null,
2991 .clksel = auxclkreq_sel,
2992 .clksel_reg = OMAP4_SCRM_AUXCLKREQ0,
2993 .clksel_mask = OMAP4_MAPPING_MASK,
2994 .recalc = &omap2_clksel_recalc,
2995};
2996
2997static struct clk auxclkreq1_ck = {
2998 .name = "auxclkreq1_ck",
2999 .parent = &auxclk1_ck,
3000 .init = &omap2_init_clksel_parent,
3001 .ops = &clkops_null,
3002 .clksel = auxclkreq_sel,
3003 .clksel_reg = OMAP4_SCRM_AUXCLKREQ1,
3004 .clksel_mask = OMAP4_MAPPING_MASK,
3005 .recalc = &omap2_clksel_recalc,
3006};
3007
3008static struct clk auxclkreq2_ck = {
3009 .name = "auxclkreq2_ck",
3010 .parent = &auxclk2_ck,
3011 .init = &omap2_init_clksel_parent,
3012 .ops = &clkops_null,
3013 .clksel = auxclkreq_sel,
3014 .clksel_reg = OMAP4_SCRM_AUXCLKREQ2,
3015 .clksel_mask = OMAP4_MAPPING_MASK,
3016 .recalc = &omap2_clksel_recalc,
3017};
3018
3019static struct clk auxclkreq3_ck = {
3020 .name = "auxclkreq3_ck",
3021 .parent = &auxclk3_ck,
3022 .init = &omap2_init_clksel_parent,
3023 .ops = &clkops_null,
3024 .clksel = auxclkreq_sel,
3025 .clksel_reg = OMAP4_SCRM_AUXCLKREQ3,
3026 .clksel_mask = OMAP4_MAPPING_MASK,
3027 .recalc = &omap2_clksel_recalc,
3028};
3029
3030static struct clk auxclkreq4_ck = {
3031 .name = "auxclkreq4_ck",
3032 .parent = &auxclk4_ck,
3033 .init = &omap2_init_clksel_parent,
3034 .ops = &clkops_null,
3035 .clksel = auxclkreq_sel,
3036 .clksel_reg = OMAP4_SCRM_AUXCLKREQ4,
3037 .clksel_mask = OMAP4_MAPPING_MASK,
3038 .recalc = &omap2_clksel_recalc,
3039};
3040
3041static struct clk auxclkreq5_ck = {
3042 .name = "auxclkreq5_ck",
3043 .parent = &auxclk5_ck,
3044 .init = &omap2_init_clksel_parent,
3045 .ops = &clkops_null,
3046 .clksel = auxclkreq_sel,
3047 .clksel_reg = OMAP4_SCRM_AUXCLKREQ5,
3048 .clksel_mask = OMAP4_MAPPING_MASK,
3049 .recalc = &omap2_clksel_recalc,
3050};
3051
3052/*
3053 * clkdev
3054 */
3055
3056static struct omap_clk omap44xx_clks[] = {
3057 CLK(NULL, "extalt_clkin_ck", &extalt_clkin_ck, CK_443X),
3058 CLK(NULL, "pad_clks_ck", &pad_clks_ck, CK_443X),
3059 CLK(NULL, "pad_slimbus_core_clks_ck", &pad_slimbus_core_clks_ck, CK_443X),
3060 CLK(NULL, "secure_32k_clk_src_ck", &secure_32k_clk_src_ck, CK_443X),
3061 CLK(NULL, "slimbus_clk", &slimbus_clk, CK_443X),
3062 CLK(NULL, "sys_32k_ck", &sys_32k_ck, CK_443X),
3063 CLK(NULL, "virt_12000000_ck", &virt_12000000_ck, CK_443X),
3064 CLK(NULL, "virt_13000000_ck", &virt_13000000_ck, CK_443X),
3065 CLK(NULL, "virt_16800000_ck", &virt_16800000_ck, CK_443X),
3066 CLK(NULL, "virt_19200000_ck", &virt_19200000_ck, CK_443X),
3067 CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_443X),
3068 CLK(NULL, "virt_27000000_ck", &virt_27000000_ck, CK_443X),
3069 CLK(NULL, "virt_38400000_ck", &virt_38400000_ck, CK_443X),
3070 CLK(NULL, "sys_clkin_ck", &sys_clkin_ck, CK_443X),
3071 CLK(NULL, "tie_low_clock_ck", &tie_low_clock_ck, CK_443X),
3072 CLK(NULL, "utmi_phy_clkout_ck", &utmi_phy_clkout_ck, CK_443X),
3073 CLK(NULL, "xclk60mhsp1_ck", &xclk60mhsp1_ck, CK_443X),
3074 CLK(NULL, "xclk60mhsp2_ck", &xclk60mhsp2_ck, CK_443X),
3075 CLK(NULL, "xclk60motg_ck", &xclk60motg_ck, CK_443X),
3076 CLK(NULL, "abe_dpll_bypass_clk_mux_ck", &abe_dpll_bypass_clk_mux_ck, CK_443X),
3077 CLK(NULL, "abe_dpll_refclk_mux_ck", &abe_dpll_refclk_mux_ck, CK_443X),
3078 CLK(NULL, "dpll_abe_ck", &dpll_abe_ck, CK_443X),
3079 CLK(NULL, "dpll_abe_x2_ck", &dpll_abe_x2_ck, CK_443X),
3080 CLK(NULL, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, CK_443X),
3081 CLK(NULL, "abe_24m_fclk", &abe_24m_fclk, CK_443X),
3082 CLK(NULL, "abe_clk", &abe_clk, CK_443X),
3083 CLK(NULL, "aess_fclk", &aess_fclk, CK_443X),
3084 CLK(NULL, "dpll_abe_m3x2_ck", &dpll_abe_m3x2_ck, CK_443X),
3085 CLK(NULL, "core_hsd_byp_clk_mux_ck", &core_hsd_byp_clk_mux_ck, CK_443X),
3086 CLK(NULL, "dpll_core_ck", &dpll_core_ck, CK_443X),
3087 CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck, CK_443X),
3088 CLK(NULL, "dpll_core_m6x2_ck", &dpll_core_m6x2_ck, CK_443X),
3089 CLK(NULL, "dbgclk_mux_ck", &dbgclk_mux_ck, CK_443X),
3090 CLK(NULL, "dpll_core_m2_ck", &dpll_core_m2_ck, CK_443X),
3091 CLK(NULL, "ddrphy_ck", &ddrphy_ck, CK_443X),
3092 CLK(NULL, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, CK_443X),
3093 CLK(NULL, "div_core_ck", &div_core_ck, CK_443X),
3094 CLK(NULL, "div_iva_hs_clk", &div_iva_hs_clk, CK_443X),
3095 CLK(NULL, "div_mpu_hs_clk", &div_mpu_hs_clk, CK_443X),
3096 CLK(NULL, "dpll_core_m4x2_ck", &dpll_core_m4x2_ck, CK_443X),
3097 CLK(NULL, "dll_clk_div_ck", &dll_clk_div_ck, CK_443X),
3098 CLK(NULL, "dpll_abe_m2_ck", &dpll_abe_m2_ck, CK_443X),
3099 CLK(NULL, "dpll_core_m3x2_ck", &dpll_core_m3x2_ck, CK_443X),
3100 CLK(NULL, "dpll_core_m7x2_ck", &dpll_core_m7x2_ck, CK_443X),
3101 CLK(NULL, "iva_hsd_byp_clk_mux_ck", &iva_hsd_byp_clk_mux_ck, CK_443X),
3102 CLK(NULL, "dpll_iva_ck", &dpll_iva_ck, CK_443X),
3103 CLK(NULL, "dpll_iva_x2_ck", &dpll_iva_x2_ck, CK_443X),
3104 CLK(NULL, "dpll_iva_m4x2_ck", &dpll_iva_m4x2_ck, CK_443X),
3105 CLK(NULL, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck, CK_443X),
3106 CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_443X),
3107 CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_443X),
3108 CLK(NULL, "per_hs_clk_div_ck", &per_hs_clk_div_ck, CK_443X),
3109 CLK(NULL, "per_hsd_byp_clk_mux_ck", &per_hsd_byp_clk_mux_ck, CK_443X),
3110 CLK(NULL, "dpll_per_ck", &dpll_per_ck, CK_443X),
3111 CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck, CK_443X),
3112 CLK(NULL, "dpll_per_x2_ck", &dpll_per_x2_ck, CK_443X),
3113 CLK(NULL, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, CK_443X),
3114 CLK(NULL, "dpll_per_m3x2_ck", &dpll_per_m3x2_ck, CK_443X),
3115 CLK(NULL, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, CK_443X),
3116 CLK(NULL, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, CK_443X),
3117 CLK(NULL, "dpll_per_m6x2_ck", &dpll_per_m6x2_ck, CK_443X),
3118 CLK(NULL, "dpll_per_m7x2_ck", &dpll_per_m7x2_ck, CK_443X),
3119 CLK(NULL, "usb_hs_clk_div_ck", &usb_hs_clk_div_ck, CK_443X),
3120 CLK(NULL, "dpll_usb_ck", &dpll_usb_ck, CK_443X),
3121 CLK(NULL, "dpll_usb_clkdcoldo_ck", &dpll_usb_clkdcoldo_ck, CK_443X),
3122 CLK(NULL, "dpll_usb_m2_ck", &dpll_usb_m2_ck, CK_443X),
3123 CLK(NULL, "ducati_clk_mux_ck", &ducati_clk_mux_ck, CK_443X),
3124 CLK(NULL, "func_12m_fclk", &func_12m_fclk, CK_443X),
3125 CLK(NULL, "func_24m_clk", &func_24m_clk, CK_443X),
3126 CLK(NULL, "func_24mc_fclk", &func_24mc_fclk, CK_443X),
3127 CLK(NULL, "func_48m_fclk", &func_48m_fclk, CK_443X),
3128 CLK(NULL, "func_48mc_fclk", &func_48mc_fclk, CK_443X),
3129 CLK(NULL, "func_64m_fclk", &func_64m_fclk, CK_443X),
3130 CLK(NULL, "func_96m_fclk", &func_96m_fclk, CK_443X),
3131 CLK(NULL, "init_60m_fclk", &init_60m_fclk, CK_443X),
3132 CLK(NULL, "l3_div_ck", &l3_div_ck, CK_443X),
3133 CLK(NULL, "l4_div_ck", &l4_div_ck, CK_443X),
3134 CLK(NULL, "lp_clk_div_ck", &lp_clk_div_ck, CK_443X),
3135 CLK(NULL, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, CK_443X),
3136 CLK("smp_twd", NULL, &mpu_periphclk, CK_443X),
3137 CLK(NULL, "ocp_abe_iclk", &ocp_abe_iclk, CK_443X),
3138 CLK(NULL, "per_abe_24m_fclk", &per_abe_24m_fclk, CK_443X),
3139 CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk, CK_443X),
3140 CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck, CK_443X),
3141 CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck, CK_443X),
3142 CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck, CK_443X),
3143 CLK(NULL, "aes1_fck", &aes1_fck, CK_443X),
3144 CLK(NULL, "aes2_fck", &aes2_fck, CK_443X),
3145 CLK(NULL, "aess_fck", &aess_fck, CK_443X),
3146 CLK(NULL, "bandgap_fclk", &bandgap_fclk, CK_443X),
3147 CLK(NULL, "bandgap_ts_fclk", &bandgap_ts_fclk, CK_446X),
3148 CLK(NULL, "des3des_fck", &des3des_fck, CK_443X),
3149 CLK(NULL, "div_ts_ck", &div_ts_ck, CK_446X),
3150 CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X),
3151 CLK(NULL, "dmic_fck", &dmic_fck, CK_443X),
3152 CLK(NULL, "dsp_fck", &dsp_fck, CK_443X),
3153 CLK(NULL, "dss_sys_clk", &dss_sys_clk, CK_443X),
3154 CLK(NULL, "dss_tv_clk", &dss_tv_clk, CK_443X),
3155 CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk, CK_443X),
3156 CLK(NULL, "dss_dss_clk", &dss_dss_clk, CK_443X),
3157 CLK(NULL, "dss_fck", &dss_fck, CK_443X),
3158 CLK("omapdss_dss", "ick", &dss_fck, CK_443X),
3159 CLK(NULL, "efuse_ctrl_cust_fck", &efuse_ctrl_cust_fck, CK_443X),
3160 CLK(NULL, "emif1_fck", &emif1_fck, CK_443X),
3161 CLK(NULL, "emif2_fck", &emif2_fck, CK_443X),
3162 CLK(NULL, "fdif_fck", &fdif_fck, CK_443X),
3163 CLK(NULL, "fpka_fck", &fpka_fck, CK_443X),
3164 CLK(NULL, "gpio1_dbclk", &gpio1_dbclk, CK_443X),
3165 CLK(NULL, "gpio1_ick", &gpio1_ick, CK_443X),
3166 CLK(NULL, "gpio2_dbclk", &gpio2_dbclk, CK_443X),
3167 CLK(NULL, "gpio2_ick", &gpio2_ick, CK_443X),
3168 CLK(NULL, "gpio3_dbclk", &gpio3_dbclk, CK_443X),
3169 CLK(NULL, "gpio3_ick", &gpio3_ick, CK_443X),
3170 CLK(NULL, "gpio4_dbclk", &gpio4_dbclk, CK_443X),
3171 CLK(NULL, "gpio4_ick", &gpio4_ick, CK_443X),
3172 CLK(NULL, "gpio5_dbclk", &gpio5_dbclk, CK_443X),
3173 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_443X),
3174 CLK(NULL, "gpio6_dbclk", &gpio6_dbclk, CK_443X),
3175 CLK(NULL, "gpio6_ick", &gpio6_ick, CK_443X),
3176 CLK(NULL, "gpmc_ick", &gpmc_ick, CK_443X),
3177 CLK(NULL, "gpu_fck", &gpu_fck, CK_443X),
3178 CLK(NULL, "hdq1w_fck", &hdq1w_fck, CK_443X),
3179 CLK(NULL, "hsi_fck", &hsi_fck, CK_443X),
3180 CLK(NULL, "i2c1_fck", &i2c1_fck, CK_443X),
3181 CLK(NULL, "i2c2_fck", &i2c2_fck, CK_443X),
3182 CLK(NULL, "i2c3_fck", &i2c3_fck, CK_443X),
3183 CLK(NULL, "i2c4_fck", &i2c4_fck, CK_443X),
3184 CLK(NULL, "ipu_fck", &ipu_fck, CK_443X),
3185 CLK(NULL, "iss_ctrlclk", &iss_ctrlclk, CK_443X),
3186 CLK(NULL, "iss_fck", &iss_fck, CK_443X),
3187 CLK(NULL, "iva_fck", &iva_fck, CK_443X),
3188 CLK(NULL, "kbd_fck", &kbd_fck, CK_443X),
3189 CLK(NULL, "l3_instr_ick", &l3_instr_ick, CK_443X),
3190 CLK(NULL, "l3_main_3_ick", &l3_main_3_ick, CK_443X),
3191 CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck, CK_443X),
3192 CLK(NULL, "mcasp_fck", &mcasp_fck, CK_443X),
3193 CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck, CK_443X),
3194 CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_443X),
3195 CLK(NULL, "mcbsp2_sync_mux_ck", &mcbsp2_sync_mux_ck, CK_443X),
3196 CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_443X),
3197 CLK(NULL, "mcbsp3_sync_mux_ck", &mcbsp3_sync_mux_ck, CK_443X),
3198 CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_443X),
3199 CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck, CK_443X),
3200 CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_443X),
3201 CLK(NULL, "mcpdm_fck", &mcpdm_fck, CK_443X),
3202 CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_443X),
3203 CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_443X),
3204 CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_443X),
3205 CLK(NULL, "mcspi4_fck", &mcspi4_fck, CK_443X),
3206 CLK(NULL, "mmc1_fck", &mmc1_fck, CK_443X),
3207 CLK(NULL, "mmc2_fck", &mmc2_fck, CK_443X),
3208 CLK(NULL, "mmc3_fck", &mmc3_fck, CK_443X),
3209 CLK(NULL, "mmc4_fck", &mmc4_fck, CK_443X),
3210 CLK(NULL, "mmc5_fck", &mmc5_fck, CK_443X),
3211 CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m, CK_443X),
3212 CLK(NULL, "ocp2scp_usb_phy_ick", &ocp2scp_usb_phy_ick, CK_443X),
3213 CLK(NULL, "ocp_wp_noc_ick", &ocp_wp_noc_ick, CK_443X),
3214 CLK(NULL, "rng_ick", &rng_ick, CK_443X),
3215 CLK("omap_rng", "ick", &rng_ick, CK_443X),
3216 CLK(NULL, "sha2md5_fck", &sha2md5_fck, CK_443X),
3217 CLK(NULL, "sl2if_ick", &sl2if_ick, CK_443X),
3218 CLK(NULL, "slimbus1_fclk_1", &slimbus1_fclk_1, CK_443X),
3219 CLK(NULL, "slimbus1_fclk_0", &slimbus1_fclk_0, CK_443X),
3220 CLK(NULL, "slimbus1_fclk_2", &slimbus1_fclk_2, CK_443X),
3221 CLK(NULL, "slimbus1_slimbus_clk", &slimbus1_slimbus_clk, CK_443X),
3222 CLK(NULL, "slimbus1_fck", &slimbus1_fck, CK_443X),
3223 CLK(NULL, "slimbus2_fclk_1", &slimbus2_fclk_1, CK_443X),
3224 CLK(NULL, "slimbus2_fclk_0", &slimbus2_fclk_0, CK_443X),
3225 CLK(NULL, "slimbus2_slimbus_clk", &slimbus2_slimbus_clk, CK_443X),
3226 CLK(NULL, "slimbus2_fck", &slimbus2_fck, CK_443X),
3227 CLK(NULL, "smartreflex_core_fck", &smartreflex_core_fck, CK_443X),
3228 CLK(NULL, "smartreflex_iva_fck", &smartreflex_iva_fck, CK_443X),
3229 CLK(NULL, "smartreflex_mpu_fck", &smartreflex_mpu_fck, CK_443X),
3230 CLK(NULL, "timer1_fck", &timer1_fck, CK_443X),
3231 CLK(NULL, "timer10_fck", &timer10_fck, CK_443X),
3232 CLK(NULL, "timer11_fck", &timer11_fck, CK_443X),
3233 CLK(NULL, "timer2_fck", &timer2_fck, CK_443X),
3234 CLK(NULL, "timer3_fck", &timer3_fck, CK_443X),
3235 CLK(NULL, "timer4_fck", &timer4_fck, CK_443X),
3236 CLK(NULL, "timer5_fck", &timer5_fck, CK_443X),
3237 CLK(NULL, "timer6_fck", &timer6_fck, CK_443X),
3238 CLK(NULL, "timer7_fck", &timer7_fck, CK_443X),
3239 CLK(NULL, "timer8_fck", &timer8_fck, CK_443X),
3240 CLK(NULL, "timer9_fck", &timer9_fck, CK_443X),
3241 CLK(NULL, "uart1_fck", &uart1_fck, CK_443X),
3242 CLK(NULL, "uart2_fck", &uart2_fck, CK_443X),
3243 CLK(NULL, "uart3_fck", &uart3_fck, CK_443X),
3244 CLK(NULL, "uart4_fck", &uart4_fck, CK_443X),
3245 CLK("usbhs_omap", "fs_fck", &usb_host_fs_fck, CK_443X),
3246 CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X),
3247 CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_443X),
3248 CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk, CK_443X),
3249 CLK(NULL, "utmi_p2_gfclk", &utmi_p2_gfclk, CK_443X),
3250 CLK(NULL, "usb_host_hs_utmi_p2_clk", &usb_host_hs_utmi_p2_clk, CK_443X),
3251 CLK(NULL, "usb_host_hs_utmi_p3_clk", &usb_host_hs_utmi_p3_clk, CK_443X),
3252 CLK(NULL, "usb_host_hs_hsic480m_p1_clk", &usb_host_hs_hsic480m_p1_clk, CK_443X),
3253 CLK(NULL, "usb_host_hs_hsic60m_p1_clk", &usb_host_hs_hsic60m_p1_clk, CK_443X),
3254 CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk, CK_443X),
3255 CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk, CK_443X),
3256 CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk, CK_443X),
3257 CLK(NULL, "usb_host_hs_fck", &usb_host_hs_fck, CK_443X),
3258 CLK("usbhs_omap", "hs_fck", &usb_host_hs_fck, CK_443X),
3259 CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk, CK_443X),
3260 CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk, CK_443X),
3261 CLK(NULL, "usb_otg_hs_ick", &usb_otg_hs_ick, CK_443X),
3262 CLK("musb-omap2430", "ick", &usb_otg_hs_ick, CK_443X),
3263 CLK(NULL, "usb_phy_cm_clk32k", &usb_phy_cm_clk32k, CK_443X),
3264 CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk, CK_443X),
3265 CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk, CK_443X),
3266 CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk, CK_443X),
3267 CLK(NULL, "usb_tll_hs_ick", &usb_tll_hs_ick, CK_443X),
3268 CLK("usbhs_omap", "usbtll_ick", &usb_tll_hs_ick, CK_443X),
3269 CLK("usbhs_tll", "usbtll_ick", &usb_tll_hs_ick, CK_443X),
3270 CLK(NULL, "usim_ck", &usim_ck, CK_443X),
3271 CLK(NULL, "usim_fclk", &usim_fclk, CK_443X),
3272 CLK(NULL, "usim_fck", &usim_fck, CK_443X),
3273 CLK(NULL, "wd_timer2_fck", &wd_timer2_fck, CK_443X),
3274 CLK(NULL, "wd_timer3_fck", &wd_timer3_fck, CK_443X),
3275 CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X),
3276 CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X),
3277 CLK(NULL, "auxclk0_src_ck", &auxclk0_src_ck, CK_443X),
3278 CLK(NULL, "auxclk0_ck", &auxclk0_ck, CK_443X),
3279 CLK(NULL, "auxclkreq0_ck", &auxclkreq0_ck, CK_443X),
3280 CLK(NULL, "auxclk1_src_ck", &auxclk1_src_ck, CK_443X),
3281 CLK(NULL, "auxclk1_ck", &auxclk1_ck, CK_443X),
3282 CLK(NULL, "auxclkreq1_ck", &auxclkreq1_ck, CK_443X),
3283 CLK(NULL, "auxclk2_src_ck", &auxclk2_src_ck, CK_443X),
3284 CLK(NULL, "auxclk2_ck", &auxclk2_ck, CK_443X),
3285 CLK(NULL, "auxclkreq2_ck", &auxclkreq2_ck, CK_443X),
3286 CLK(NULL, "auxclk3_src_ck", &auxclk3_src_ck, CK_443X),
3287 CLK(NULL, "auxclk3_ck", &auxclk3_ck, CK_443X),
3288 CLK(NULL, "auxclkreq3_ck", &auxclkreq3_ck, CK_443X),
3289 CLK(NULL, "auxclk4_src_ck", &auxclk4_src_ck, CK_443X),
3290 CLK(NULL, "auxclk4_ck", &auxclk4_ck, CK_443X),
3291 CLK(NULL, "auxclkreq4_ck", &auxclkreq4_ck, CK_443X),
3292 CLK(NULL, "auxclk5_src_ck", &auxclk5_src_ck, CK_443X),
3293 CLK(NULL, "auxclk5_ck", &auxclk5_ck, CK_443X),
3294 CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck, CK_443X),
3295 CLK("omap-gpmc", "fck", &dummy_ck, CK_443X),
3296 CLK("omap_i2c.1", "ick", &dummy_ck, CK_443X),
3297 CLK("omap_i2c.2", "ick", &dummy_ck, CK_443X),
3298 CLK("omap_i2c.3", "ick", &dummy_ck, CK_443X),
3299 CLK("omap_i2c.4", "ick", &dummy_ck, CK_443X),
3300 CLK(NULL, "mailboxes_ick", &dummy_ck, CK_443X),
3301 CLK("omap_hsmmc.0", "ick", &dummy_ck, CK_443X),
3302 CLK("omap_hsmmc.1", "ick", &dummy_ck, CK_443X),
3303 CLK("omap_hsmmc.2", "ick", &dummy_ck, CK_443X),
3304 CLK("omap_hsmmc.3", "ick", &dummy_ck, CK_443X),
3305 CLK("omap_hsmmc.4", "ick", &dummy_ck, CK_443X),
3306 CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_443X),
3307 CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_443X),
3308 CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_443X),
3309 CLK("omap-mcbsp.4", "ick", &dummy_ck, CK_443X),
3310 CLK("omap2_mcspi.1", "ick", &dummy_ck, CK_443X),
3311 CLK("omap2_mcspi.2", "ick", &dummy_ck, CK_443X),
3312 CLK("omap2_mcspi.3", "ick", &dummy_ck, CK_443X),
3313 CLK("omap2_mcspi.4", "ick", &dummy_ck, CK_443X),
3314 CLK(NULL, "uart1_ick", &dummy_ck, CK_443X),
3315 CLK(NULL, "uart2_ick", &dummy_ck, CK_443X),
3316 CLK(NULL, "uart3_ick", &dummy_ck, CK_443X),
3317 CLK(NULL, "uart4_ick", &dummy_ck, CK_443X),
3318 CLK("usbhs_omap", "usbhost_ick", &dummy_ck, CK_443X),
3319 CLK("usbhs_omap", "usbtll_fck", &dummy_ck, CK_443X),
3320 CLK("usbhs_tll", "usbtll_fck", &dummy_ck, CK_443X),
3321 CLK("omap_wdt", "ick", &dummy_ck, CK_443X),
3322 CLK(NULL, "timer_32k_ck", &sys_32k_ck, CK_443X),
3323 /* TODO: Remove "omap_timer.X" aliases once DT migration is complete */
3324 CLK("omap_timer.1", "timer_sys_ck", &sys_clkin_ck, CK_443X),
3325 CLK("omap_timer.2", "timer_sys_ck", &sys_clkin_ck, CK_443X),
3326 CLK("omap_timer.3", "timer_sys_ck", &sys_clkin_ck, CK_443X),
3327 CLK("omap_timer.4", "timer_sys_ck", &sys_clkin_ck, CK_443X),
3328 CLK("omap_timer.9", "timer_sys_ck", &sys_clkin_ck, CK_443X),
3329 CLK("omap_timer.10", "timer_sys_ck", &sys_clkin_ck, CK_443X),
3330 CLK("omap_timer.11", "timer_sys_ck", &sys_clkin_ck, CK_443X),
3331 CLK("omap_timer.5", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
3332 CLK("omap_timer.6", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
3333 CLK("omap_timer.7", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
3334 CLK("omap_timer.8", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
3335 CLK("4a318000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X),
3336 CLK("48032000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X),
3337 CLK("48034000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X),
3338 CLK("48036000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X),
3339 CLK("4803e000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X),
3340 CLK("48086000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X),
3341 CLK("48088000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X),
3342 CLK("49038000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
3343 CLK("4903a000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
3344 CLK("4903c000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
3345 CLK("4903e000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
3346 CLK(NULL, "cpufreq_ck", &dpll_mpu_ck, CK_443X),
3347};
3348
3349int __init omap4xxx_clk_init(void)
3350{
3351 struct omap_clk *c;
3352 u32 cpu_clkflg;
3353
3354 if (cpu_is_omap443x()) {
3355 cpu_mask = RATE_IN_4430;
3356 cpu_clkflg = CK_443X;
3357 } else if (cpu_is_omap446x() || cpu_is_omap447x()) {
3358 cpu_mask = RATE_IN_4460 | RATE_IN_4430;
3359 cpu_clkflg = CK_446X | CK_443X;
3360
3361 if (cpu_is_omap447x())
3362 pr_warn("WARNING: OMAP4470 clock data incomplete!\n");
3363 } else {
3364 return 0;
3365 }
3366
3367 /*
3368 * Must stay commented until all OMAP SoC drivers are
3369 * converted to runtime PM, or drivers may start crashing
3370 *
3371 * omap2_clk_disable_clkdm_control();
3372 */
3373
3374 for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks);
3375 c++)
3376 clk_preinit(c->lk.clk);
3377
3378 for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks);
3379 c++)
3380 if (c->cpu & cpu_clkflg) {
3381 clkdev_add(&c->lk);
3382 clk_register(c->lk.clk);
3383 omap2_init_clk_clkdm(c->lk.clk);
3384 }
3385
3386 /* Disable autoidle on all clocks; let the PM code enable it later */
3387 omap_clk_disable_autoidle_all();
3388
3389 recalculate_root_clocks();
3390
3391 /*
3392 * Only enable those clocks we will need, let the drivers
3393 * enable other clocks as necessary
3394 */
3395 clk_enable_init_clocks();
3396
3397 return 0;
3398}
diff --git a/arch/arm/mach-omap2/clock_common_data.c b/arch/arm/mach-omap2/clock_common_data.c
index b9f3ba68148c..ef4d21bfb964 100644
--- a/arch/arm/mach-omap2/clock_common_data.c
+++ b/arch/arm/mach-omap2/clock_common_data.c
@@ -16,6 +16,7 @@
16 * OMAP3xxx clock definition files. 16 * OMAP3xxx clock definition files.
17 */ 17 */
18 18
19#include <linux/clk-private.h>
19#include "clock.h" 20#include "clock.h"
20 21
21/* clksel_rate data common to 24xx/343x */ 22/* clksel_rate data common to 24xx/343x */
@@ -52,6 +53,13 @@ const struct clksel_rate div_1_0_rates[] = {
52 { .div = 0 }, 53 { .div = 0 },
53}; 54};
54 55
56const struct clksel_rate div3_1to4_rates[] = {
57 { .div = 1, .val = 0, .flags = RATE_IN_4430 },
58 { .div = 2, .val = 1, .flags = RATE_IN_4430 },
59 { .div = 4, .val = 2, .flags = RATE_IN_4430 },
60 { .div = 0 },
61};
62
55const struct clksel_rate div_1_1_rates[] = { 63const struct clksel_rate div_1_1_rates[] = {
56 { .div = 1, .val = 1, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, 64 { .div = 1, .val = 1, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
57 { .div = 0 }, 65 { .div = 0 },
@@ -109,14 +117,10 @@ const struct clksel_rate div31_1to31_rates[] = {
109 117
110/* Clocks shared between various OMAP SoCs */ 118/* Clocks shared between various OMAP SoCs */
111 119
112struct clk virt_19200000_ck = { 120static struct clk_ops dummy_ck_ops = {};
113 .name = "virt_19200000_ck",
114 .ops = &clkops_null,
115 .rate = 19200000,
116};
117 121
118struct clk virt_26000000_ck = { 122struct clk dummy_ck = {
119 .name = "virt_26000000_ck", 123 .name = "dummy_clk",
120 .ops = &clkops_null, 124 .ops = &dummy_ck_ops,
121 .rate = 26000000, 125 .flags = CLK_IS_BASIC,
122}; 126};
diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
index 64e50465a4b5..384873580b23 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -22,6 +22,7 @@
22#include <linux/clk.h> 22#include <linux/clk.h>
23#include <linux/limits.h> 23#include <linux/limits.h>
24#include <linux/err.h> 24#include <linux/err.h>
25#include <linux/clk-provider.h>
25 26
26#include <linux/io.h> 27#include <linux/io.h>
27 28
@@ -947,35 +948,6 @@ static int _clkdm_clk_hwmod_enable(struct clockdomain *clkdm)
947 return 0; 948 return 0;
948} 949}
949 950
950static int _clkdm_clk_hwmod_disable(struct clockdomain *clkdm)
951{
952 unsigned long flags;
953
954 if (!clkdm || !arch_clkdm || !arch_clkdm->clkdm_clk_disable)
955 return -EINVAL;
956
957 spin_lock_irqsave(&clkdm->lock, flags);
958
959 if (atomic_read(&clkdm->usecount) == 0) {
960 spin_unlock_irqrestore(&clkdm->lock, flags);
961 WARN_ON(1); /* underflow */
962 return -ERANGE;
963 }
964
965 if (atomic_dec_return(&clkdm->usecount) > 0) {
966 spin_unlock_irqrestore(&clkdm->lock, flags);
967 return 0;
968 }
969
970 arch_clkdm->clkdm_clk_disable(clkdm);
971 pwrdm_state_switch(clkdm->pwrdm.ptr);
972 spin_unlock_irqrestore(&clkdm->lock, flags);
973
974 pr_debug("clockdomain: %s: disabled\n", clkdm->name);
975
976 return 0;
977}
978
979/** 951/**
980 * clkdm_clk_enable - add an enabled downstream clock to this clkdm 952 * clkdm_clk_enable - add an enabled downstream clock to this clkdm
981 * @clkdm: struct clockdomain * 953 * @clkdm: struct clockdomain *
@@ -1018,15 +990,37 @@ int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
1018 */ 990 */
1019int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk) 991int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk)
1020{ 992{
1021 /* 993 unsigned long flags;
1022 * XXX Rewrite this code to maintain a list of enabled
1023 * downstream clocks for debugging purposes?
1024 */
1025 994
1026 if (!clk) 995 if (!clkdm || !clk || !arch_clkdm || !arch_clkdm->clkdm_clk_disable)
1027 return -EINVAL; 996 return -EINVAL;
1028 997
1029 return _clkdm_clk_hwmod_disable(clkdm); 998 spin_lock_irqsave(&clkdm->lock, flags);
999
1000 /* corner case: disabling unused clocks */
1001 if (__clk_get_enable_count(clk) == 0)
1002 goto ccd_exit;
1003
1004 if (atomic_read(&clkdm->usecount) == 0) {
1005 spin_unlock_irqrestore(&clkdm->lock, flags);
1006 WARN_ON(1); /* underflow */
1007 return -ERANGE;
1008 }
1009
1010 if (atomic_dec_return(&clkdm->usecount) > 0) {
1011 spin_unlock_irqrestore(&clkdm->lock, flags);
1012 return 0;
1013 }
1014
1015 arch_clkdm->clkdm_clk_disable(clkdm);
1016 pwrdm_state_switch(clkdm->pwrdm.ptr);
1017
1018 pr_debug("clockdomain: %s: disabled\n", clkdm->name);
1019
1020ccd_exit:
1021 spin_unlock_irqrestore(&clkdm->lock, flags);
1022
1023 return 0;
1030} 1024}
1031 1025
1032/** 1026/**
@@ -1077,6 +1071,8 @@ int clkdm_hwmod_enable(struct clockdomain *clkdm, struct omap_hwmod *oh)
1077 */ 1071 */
1078int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh) 1072int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh)
1079{ 1073{
1074 unsigned long flags;
1075
1080 /* The clkdm attribute does not exist yet prior OMAP4 */ 1076 /* The clkdm attribute does not exist yet prior OMAP4 */
1081 if (cpu_is_omap24xx() || cpu_is_omap34xx()) 1077 if (cpu_is_omap24xx() || cpu_is_omap34xx())
1082 return 0; 1078 return 0;
@@ -1086,9 +1082,28 @@ int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh)
1086 * downstream hwmods for debugging purposes? 1082 * downstream hwmods for debugging purposes?
1087 */ 1083 */
1088 1084
1089 if (!oh) 1085 if (!clkdm || !oh || !arch_clkdm || !arch_clkdm->clkdm_clk_disable)
1090 return -EINVAL; 1086 return -EINVAL;
1091 1087
1092 return _clkdm_clk_hwmod_disable(clkdm); 1088 spin_lock_irqsave(&clkdm->lock, flags);
1089
1090 if (atomic_read(&clkdm->usecount) == 0) {
1091 spin_unlock_irqrestore(&clkdm->lock, flags);
1092 WARN_ON(1); /* underflow */
1093 return -ERANGE;
1094 }
1095
1096 if (atomic_dec_return(&clkdm->usecount) > 0) {
1097 spin_unlock_irqrestore(&clkdm->lock, flags);
1098 return 0;
1099 }
1100
1101 arch_clkdm->clkdm_clk_disable(clkdm);
1102 pwrdm_state_switch(clkdm->pwrdm.ptr);
1103 spin_unlock_irqrestore(&clkdm->lock, flags);
1104
1105 pr_debug("clockdomain: %s: disabled\n", clkdm->name);
1106
1107 return 0;
1093} 1108}
1094 1109
diff --git a/arch/arm/mach-omap2/cm-regbits-24xx.h b/arch/arm/mach-omap2/cm-regbits-24xx.h
index 11eaf16880c4..669ef51b17a8 100644
--- a/arch/arm/mach-omap2/cm-regbits-24xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-24xx.h
@@ -59,6 +59,7 @@
59/* CM_CLKSEL_MPU */ 59/* CM_CLKSEL_MPU */
60#define OMAP24XX_CLKSEL_MPU_SHIFT 0 60#define OMAP24XX_CLKSEL_MPU_SHIFT 0
61#define OMAP24XX_CLKSEL_MPU_MASK (0x1f << 0) 61#define OMAP24XX_CLKSEL_MPU_MASK (0x1f << 0)
62#define OMAP24XX_CLKSEL_MPU_WIDTH 5
62 63
63/* CM_CLKSTCTRL_MPU */ 64/* CM_CLKSTCTRL_MPU */
64#define OMAP24XX_AUTOSTATE_MPU_SHIFT 0 65#define OMAP24XX_AUTOSTATE_MPU_SHIFT 0
@@ -237,8 +238,10 @@
237#define OMAP24XX_CLKSEL_DSS1_MASK (0x1f << 8) 238#define OMAP24XX_CLKSEL_DSS1_MASK (0x1f << 8)
238#define OMAP24XX_CLKSEL_L4_SHIFT 5 239#define OMAP24XX_CLKSEL_L4_SHIFT 5
239#define OMAP24XX_CLKSEL_L4_MASK (0x3 << 5) 240#define OMAP24XX_CLKSEL_L4_MASK (0x3 << 5)
241#define OMAP24XX_CLKSEL_L4_WIDTH 2
240#define OMAP24XX_CLKSEL_L3_SHIFT 0 242#define OMAP24XX_CLKSEL_L3_SHIFT 0
241#define OMAP24XX_CLKSEL_L3_MASK (0x1f << 0) 243#define OMAP24XX_CLKSEL_L3_MASK (0x1f << 0)
244#define OMAP24XX_CLKSEL_L3_WIDTH 5
242 245
243/* CM_CLKSEL2_CORE */ 246/* CM_CLKSEL2_CORE */
244#define OMAP24XX_CLKSEL_GPT12_SHIFT 22 247#define OMAP24XX_CLKSEL_GPT12_SHIFT 22
@@ -363,8 +366,10 @@
363#define OMAP24XX_DPLL_DIV_MASK (0xf << 8) 366#define OMAP24XX_DPLL_DIV_MASK (0xf << 8)
364#define OMAP24XX_54M_SOURCE_SHIFT 5 367#define OMAP24XX_54M_SOURCE_SHIFT 5
365#define OMAP24XX_54M_SOURCE_MASK (1 << 5) 368#define OMAP24XX_54M_SOURCE_MASK (1 << 5)
369#define OMAP24XX_54M_SOURCE_WIDTH 1
366#define OMAP2430_96M_SOURCE_SHIFT 4 370#define OMAP2430_96M_SOURCE_SHIFT 4
367#define OMAP2430_96M_SOURCE_MASK (1 << 4) 371#define OMAP2430_96M_SOURCE_MASK (1 << 4)
372#define OMAP2430_96M_SOURCE_WIDTH 1
368#define OMAP24XX_48M_SOURCE_SHIFT 3 373#define OMAP24XX_48M_SOURCE_SHIFT 3
369#define OMAP24XX_48M_SOURCE_MASK (1 << 3) 374#define OMAP24XX_48M_SOURCE_MASK (1 << 3)
370#define OMAP2430_ALTCLK_SOURCE_SHIFT 0 375#define OMAP2430_ALTCLK_SOURCE_SHIFT 0
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h
index 59598ffd8783..adf78d325804 100644
--- a/arch/arm/mach-omap2/cm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-34xx.h
@@ -81,6 +81,7 @@
81/* CM_CLKSEL1_PLL_IVA2 */ 81/* CM_CLKSEL1_PLL_IVA2 */
82#define OMAP3430_IVA2_CLK_SRC_SHIFT 19 82#define OMAP3430_IVA2_CLK_SRC_SHIFT 19
83#define OMAP3430_IVA2_CLK_SRC_MASK (0x7 << 19) 83#define OMAP3430_IVA2_CLK_SRC_MASK (0x7 << 19)
84#define OMAP3430_IVA2_CLK_SRC_WIDTH 3
84#define OMAP3430_IVA2_DPLL_MULT_SHIFT 8 85#define OMAP3430_IVA2_DPLL_MULT_SHIFT 8
85#define OMAP3430_IVA2_DPLL_MULT_MASK (0x7ff << 8) 86#define OMAP3430_IVA2_DPLL_MULT_MASK (0x7ff << 8)
86#define OMAP3430_IVA2_DPLL_DIV_SHIFT 0 87#define OMAP3430_IVA2_DPLL_DIV_SHIFT 0
@@ -89,6 +90,7 @@
89/* CM_CLKSEL2_PLL_IVA2 */ 90/* CM_CLKSEL2_PLL_IVA2 */
90#define OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT 0 91#define OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT 0
91#define OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK (0x1f << 0) 92#define OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK (0x1f << 0)
93#define OMAP3430_IVA2_DPLL_CLKOUT_DIV_WIDTH 5
92 94
93/* CM_CLKSTCTRL_IVA2 */ 95/* CM_CLKSTCTRL_IVA2 */
94#define OMAP3430_CLKTRCTRL_IVA2_SHIFT 0 96#define OMAP3430_CLKTRCTRL_IVA2_SHIFT 0
@@ -118,6 +120,7 @@
118/* CM_IDLEST_PLL_MPU */ 120/* CM_IDLEST_PLL_MPU */
119#define OMAP3430_ST_MPU_CLK_SHIFT 0 121#define OMAP3430_ST_MPU_CLK_SHIFT 0
120#define OMAP3430_ST_MPU_CLK_MASK (1 << 0) 122#define OMAP3430_ST_MPU_CLK_MASK (1 << 0)
123#define OMAP3430_ST_MPU_CLK_WIDTH 1
121 124
122/* CM_AUTOIDLE_PLL_MPU */ 125/* CM_AUTOIDLE_PLL_MPU */
123#define OMAP3430_AUTO_MPU_DPLL_SHIFT 0 126#define OMAP3430_AUTO_MPU_DPLL_SHIFT 0
@@ -126,6 +129,7 @@
126/* CM_CLKSEL1_PLL_MPU */ 129/* CM_CLKSEL1_PLL_MPU */
127#define OMAP3430_MPU_CLK_SRC_SHIFT 19 130#define OMAP3430_MPU_CLK_SRC_SHIFT 19
128#define OMAP3430_MPU_CLK_SRC_MASK (0x7 << 19) 131#define OMAP3430_MPU_CLK_SRC_MASK (0x7 << 19)
132#define OMAP3430_MPU_CLK_SRC_WIDTH 3
129#define OMAP3430_MPU_DPLL_MULT_SHIFT 8 133#define OMAP3430_MPU_DPLL_MULT_SHIFT 8
130#define OMAP3430_MPU_DPLL_MULT_MASK (0x7ff << 8) 134#define OMAP3430_MPU_DPLL_MULT_MASK (0x7ff << 8)
131#define OMAP3430_MPU_DPLL_DIV_SHIFT 0 135#define OMAP3430_MPU_DPLL_DIV_SHIFT 0
@@ -134,6 +138,7 @@
134/* CM_CLKSEL2_PLL_MPU */ 138/* CM_CLKSEL2_PLL_MPU */
135#define OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT 0 139#define OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT 0
136#define OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK (0x1f << 0) 140#define OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK (0x1f << 0)
141#define OMAP3430_MPU_DPLL_CLKOUT_DIV_WIDTH 5
137 142
138/* CM_CLKSTCTRL_MPU */ 143/* CM_CLKSTCTRL_MPU */
139#define OMAP3430_CLKTRCTRL_MPU_SHIFT 0 144#define OMAP3430_CLKTRCTRL_MPU_SHIFT 0
@@ -345,10 +350,13 @@
345#define OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK (0x3 << 4) 350#define OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK (0x3 << 4)
346#define OMAP3430_CLKSEL_L4_SHIFT 2 351#define OMAP3430_CLKSEL_L4_SHIFT 2
347#define OMAP3430_CLKSEL_L4_MASK (0x3 << 2) 352#define OMAP3430_CLKSEL_L4_MASK (0x3 << 2)
353#define OMAP3430_CLKSEL_L4_WIDTH 2
348#define OMAP3430_CLKSEL_L3_SHIFT 0 354#define OMAP3430_CLKSEL_L3_SHIFT 0
349#define OMAP3430_CLKSEL_L3_MASK (0x3 << 0) 355#define OMAP3430_CLKSEL_L3_MASK (0x3 << 0)
356#define OMAP3430_CLKSEL_L3_WIDTH 2
350#define OMAP3630_CLKSEL_96M_SHIFT 12 357#define OMAP3630_CLKSEL_96M_SHIFT 12
351#define OMAP3630_CLKSEL_96M_MASK (0x3 << 12) 358#define OMAP3630_CLKSEL_96M_MASK (0x3 << 12)
359#define OMAP3630_CLKSEL_96M_WIDTH 2
352 360
353/* CM_CLKSTCTRL_CORE */ 361/* CM_CLKSTCTRL_CORE */
354#define OMAP3430ES1_CLKTRCTRL_D2D_SHIFT 4 362#define OMAP3430ES1_CLKTRCTRL_D2D_SHIFT 4
@@ -452,6 +460,7 @@
452#define OMAP3430ES2_CLKSEL_USIMOCP_MASK (0xf << 3) 460#define OMAP3430ES2_CLKSEL_USIMOCP_MASK (0xf << 3)
453#define OMAP3430_CLKSEL_RM_SHIFT 1 461#define OMAP3430_CLKSEL_RM_SHIFT 1
454#define OMAP3430_CLKSEL_RM_MASK (0x3 << 1) 462#define OMAP3430_CLKSEL_RM_MASK (0x3 << 1)
463#define OMAP3430_CLKSEL_RM_WIDTH 2
455#define OMAP3430_CLKSEL_GPT1_SHIFT 0 464#define OMAP3430_CLKSEL_GPT1_SHIFT 0
456#define OMAP3430_CLKSEL_GPT1_MASK (1 << 0) 465#define OMAP3430_CLKSEL_GPT1_MASK (1 << 0)
457 466
@@ -520,14 +529,17 @@
520/* Note that OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK was (0x3 << 27) on 3430ES1 */ 529/* Note that OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK was (0x3 << 27) on 3430ES1 */
521#define OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT 27 530#define OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT 27
522#define OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK (0x1f << 27) 531#define OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK (0x1f << 27)
532#define OMAP3430_CORE_DPLL_CLKOUT_DIV_WIDTH 5
523#define OMAP3430_CORE_DPLL_MULT_SHIFT 16 533#define OMAP3430_CORE_DPLL_MULT_SHIFT 16
524#define OMAP3430_CORE_DPLL_MULT_MASK (0x7ff << 16) 534#define OMAP3430_CORE_DPLL_MULT_MASK (0x7ff << 16)
525#define OMAP3430_CORE_DPLL_DIV_SHIFT 8 535#define OMAP3430_CORE_DPLL_DIV_SHIFT 8
526#define OMAP3430_CORE_DPLL_DIV_MASK (0x7f << 8) 536#define OMAP3430_CORE_DPLL_DIV_MASK (0x7f << 8)
527#define OMAP3430_SOURCE_96M_SHIFT 6 537#define OMAP3430_SOURCE_96M_SHIFT 6
528#define OMAP3430_SOURCE_96M_MASK (1 << 6) 538#define OMAP3430_SOURCE_96M_MASK (1 << 6)
539#define OMAP3430_SOURCE_96M_WIDTH 1
529#define OMAP3430_SOURCE_54M_SHIFT 5 540#define OMAP3430_SOURCE_54M_SHIFT 5
530#define OMAP3430_SOURCE_54M_MASK (1 << 5) 541#define OMAP3430_SOURCE_54M_MASK (1 << 5)
542#define OMAP3430_SOURCE_54M_WIDTH 1
531#define OMAP3430_SOURCE_48M_SHIFT 3 543#define OMAP3430_SOURCE_48M_SHIFT 3
532#define OMAP3430_SOURCE_48M_MASK (1 << 3) 544#define OMAP3430_SOURCE_48M_MASK (1 << 3)
533 545
@@ -545,7 +557,9 @@
545/* CM_CLKSEL3_PLL */ 557/* CM_CLKSEL3_PLL */
546#define OMAP3430_DIV_96M_SHIFT 0 558#define OMAP3430_DIV_96M_SHIFT 0
547#define OMAP3430_DIV_96M_MASK (0x1f << 0) 559#define OMAP3430_DIV_96M_MASK (0x1f << 0)
560#define OMAP3430_DIV_96M_WIDTH 5
548#define OMAP3630_DIV_96M_MASK (0x3f << 0) 561#define OMAP3630_DIV_96M_MASK (0x3f << 0)
562#define OMAP3630_DIV_96M_WIDTH 6
549 563
550/* CM_CLKSEL4_PLL */ 564/* CM_CLKSEL4_PLL */
551#define OMAP3430ES2_PERIPH2_DPLL_MULT_SHIFT 8 565#define OMAP3430ES2_PERIPH2_DPLL_MULT_SHIFT 8
@@ -556,12 +570,14 @@
556/* CM_CLKSEL5_PLL */ 570/* CM_CLKSEL5_PLL */
557#define OMAP3430ES2_DIV_120M_SHIFT 0 571#define OMAP3430ES2_DIV_120M_SHIFT 0
558#define OMAP3430ES2_DIV_120M_MASK (0x1f << 0) 572#define OMAP3430ES2_DIV_120M_MASK (0x1f << 0)
573#define OMAP3430ES2_DIV_120M_WIDTH 5
559 574
560/* CM_CLKOUT_CTRL */ 575/* CM_CLKOUT_CTRL */
561#define OMAP3430_CLKOUT2_EN_SHIFT 7 576#define OMAP3430_CLKOUT2_EN_SHIFT 7
562#define OMAP3430_CLKOUT2_EN_MASK (1 << 7) 577#define OMAP3430_CLKOUT2_EN_MASK (1 << 7)
563#define OMAP3430_CLKOUT2_DIV_SHIFT 3 578#define OMAP3430_CLKOUT2_DIV_SHIFT 3
564#define OMAP3430_CLKOUT2_DIV_MASK (0x7 << 3) 579#define OMAP3430_CLKOUT2_DIV_MASK (0x7 << 3)
580#define OMAP3430_CLKOUT2_DIV_WIDTH 3
565#define OMAP3430_CLKOUT2SOURCE_SHIFT 0 581#define OMAP3430_CLKOUT2SOURCE_SHIFT 0
566#define OMAP3430_CLKOUT2SOURCE_MASK (0x3 << 0) 582#define OMAP3430_CLKOUT2SOURCE_MASK (0x3 << 0)
567 583
@@ -592,10 +608,14 @@
592/* CM_CLKSEL_DSS */ 608/* CM_CLKSEL_DSS */
593#define OMAP3430_CLKSEL_TV_SHIFT 8 609#define OMAP3430_CLKSEL_TV_SHIFT 8
594#define OMAP3430_CLKSEL_TV_MASK (0x1f << 8) 610#define OMAP3430_CLKSEL_TV_MASK (0x1f << 8)
611#define OMAP3430_CLKSEL_TV_WIDTH 5
595#define OMAP3630_CLKSEL_TV_MASK (0x3f << 8) 612#define OMAP3630_CLKSEL_TV_MASK (0x3f << 8)
613#define OMAP3630_CLKSEL_TV_WIDTH 6
596#define OMAP3430_CLKSEL_DSS1_SHIFT 0 614#define OMAP3430_CLKSEL_DSS1_SHIFT 0
597#define OMAP3430_CLKSEL_DSS1_MASK (0x1f << 0) 615#define OMAP3430_CLKSEL_DSS1_MASK (0x1f << 0)
616#define OMAP3430_CLKSEL_DSS1_WIDTH 5
598#define OMAP3630_CLKSEL_DSS1_MASK (0x3f << 0) 617#define OMAP3630_CLKSEL_DSS1_MASK (0x3f << 0)
618#define OMAP3630_CLKSEL_DSS1_WIDTH 6
599 619
600/* CM_SLEEPDEP_DSS specific bits */ 620/* CM_SLEEPDEP_DSS specific bits */
601 621
@@ -623,7 +643,9 @@
623/* CM_CLKSEL_CAM */ 643/* CM_CLKSEL_CAM */
624#define OMAP3430_CLKSEL_CAM_SHIFT 0 644#define OMAP3430_CLKSEL_CAM_SHIFT 0
625#define OMAP3430_CLKSEL_CAM_MASK (0x1f << 0) 645#define OMAP3430_CLKSEL_CAM_MASK (0x1f << 0)
646#define OMAP3430_CLKSEL_CAM_WIDTH 5
626#define OMAP3630_CLKSEL_CAM_MASK (0x3f << 0) 647#define OMAP3630_CLKSEL_CAM_MASK (0x3f << 0)
648#define OMAP3630_CLKSEL_CAM_WIDTH 6
627 649
628/* CM_SLEEPDEP_CAM specific bits */ 650/* CM_SLEEPDEP_CAM specific bits */
629 651
@@ -721,21 +743,30 @@
721/* CM_CLKSEL1_EMU */ 743/* CM_CLKSEL1_EMU */
722#define OMAP3430_DIV_DPLL4_SHIFT 24 744#define OMAP3430_DIV_DPLL4_SHIFT 24
723#define OMAP3430_DIV_DPLL4_MASK (0x1f << 24) 745#define OMAP3430_DIV_DPLL4_MASK (0x1f << 24)
746#define OMAP3430_DIV_DPLL4_WIDTH 5
724#define OMAP3630_DIV_DPLL4_MASK (0x3f << 24) 747#define OMAP3630_DIV_DPLL4_MASK (0x3f << 24)
748#define OMAP3630_DIV_DPLL4_WIDTH 6
725#define OMAP3430_DIV_DPLL3_SHIFT 16 749#define OMAP3430_DIV_DPLL3_SHIFT 16
726#define OMAP3430_DIV_DPLL3_MASK (0x1f << 16) 750#define OMAP3430_DIV_DPLL3_MASK (0x1f << 16)
751#define OMAP3430_DIV_DPLL3_WIDTH 5
727#define OMAP3430_CLKSEL_TRACECLK_SHIFT 11 752#define OMAP3430_CLKSEL_TRACECLK_SHIFT 11
728#define OMAP3430_CLKSEL_TRACECLK_MASK (0x7 << 11) 753#define OMAP3430_CLKSEL_TRACECLK_MASK (0x7 << 11)
754#define OMAP3430_CLKSEL_TRACECLK_WIDTH 3
729#define OMAP3430_CLKSEL_PCLK_SHIFT 8 755#define OMAP3430_CLKSEL_PCLK_SHIFT 8
730#define OMAP3430_CLKSEL_PCLK_MASK (0x7 << 8) 756#define OMAP3430_CLKSEL_PCLK_MASK (0x7 << 8)
757#define OMAP3430_CLKSEL_PCLK_WIDTH 3
731#define OMAP3430_CLKSEL_PCLKX2_SHIFT 6 758#define OMAP3430_CLKSEL_PCLKX2_SHIFT 6
732#define OMAP3430_CLKSEL_PCLKX2_MASK (0x3 << 6) 759#define OMAP3430_CLKSEL_PCLKX2_MASK (0x3 << 6)
760#define OMAP3430_CLKSEL_PCLKX2_WIDTH 2
733#define OMAP3430_CLKSEL_ATCLK_SHIFT 4 761#define OMAP3430_CLKSEL_ATCLK_SHIFT 4
734#define OMAP3430_CLKSEL_ATCLK_MASK (0x3 << 4) 762#define OMAP3430_CLKSEL_ATCLK_MASK (0x3 << 4)
763#define OMAP3430_CLKSEL_ATCLK_WIDTH 2
735#define OMAP3430_TRACE_MUX_CTRL_SHIFT 2 764#define OMAP3430_TRACE_MUX_CTRL_SHIFT 2
736#define OMAP3430_TRACE_MUX_CTRL_MASK (0x3 << 2) 765#define OMAP3430_TRACE_MUX_CTRL_MASK (0x3 << 2)
766#define OMAP3430_TRACE_MUX_CTRL_WIDTH 2
737#define OMAP3430_MUX_CTRL_SHIFT 0 767#define OMAP3430_MUX_CTRL_SHIFT 0
738#define OMAP3430_MUX_CTRL_MASK (0x3 << 0) 768#define OMAP3430_MUX_CTRL_MASK (0x3 << 0)
769#define OMAP3430_MUX_CTRL_WIDTH 2
739 770
740/* CM_CLKSTCTRL_EMU */ 771/* CM_CLKSTCTRL_EMU */
741#define OMAP3430_CLKTRCTRL_EMU_SHIFT 0 772#define OMAP3430_CLKTRCTRL_EMU_SHIFT 0
diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.h b/arch/arm/mach-omap2/cm2xxx_3xxx.h
index 98e6b3c9cd9b..bfbd16fe9151 100644
--- a/arch/arm/mach-omap2/cm2xxx_3xxx.h
+++ b/arch/arm/mach-omap2/cm2xxx_3xxx.h
@@ -108,6 +108,7 @@ extern void omap2xxx_cm_apll96_disable(void);
108/* CM_CLKSEL_GFX */ 108/* CM_CLKSEL_GFX */
109#define OMAP_CLKSEL_GFX_SHIFT 0 109#define OMAP_CLKSEL_GFX_SHIFT 0
110#define OMAP_CLKSEL_GFX_MASK (0x7 << 0) 110#define OMAP_CLKSEL_GFX_MASK (0x7 << 0)
111#define OMAP_CLKSEL_GFX_WIDTH 3
111 112
112/* CM_ICLKEN_GFX */ 113/* CM_ICLKEN_GFX */
113#define OMAP_EN_GFX_SHIFT 0 114#define OMAP_EN_GFX_SHIFT 0
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index 4ca8747b3cc9..3d944d3263d2 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -201,6 +201,7 @@
201#define OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO 0x249 201#define OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO 0x249
202#define OMAP44XX_CONTROL_FUSE_CORE_OPP50 0x254 202#define OMAP44XX_CONTROL_FUSE_CORE_OPP50 0x254
203#define OMAP44XX_CONTROL_FUSE_CORE_OPP100 0x257 203#define OMAP44XX_CONTROL_FUSE_CORE_OPP100 0x257
204#define OMAP44XX_CONTROL_FUSE_CORE_OPP100OV 0x25A
204 205
205/* AM35XX only CONTROL_GENERAL register offsets */ 206/* AM35XX only CONTROL_GENERAL register offsets */
206#define AM35XX_CONTROL_MSUSPENDMUX_6 (OMAP2_CONTROL_GENERAL + 0x0038) 207#define AM35XX_CONTROL_MSUSPENDMUX_6 (OMAP2_CONTROL_GENERAL + 0x0038)
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 3cff7dc514df..c67a731cfbb7 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -24,7 +24,7 @@
24#include <asm/mach-types.h> 24#include <asm/mach-types.h>
25#include <asm/mach/map.h> 25#include <asm/mach/map.h>
26 26
27#include <plat-omap/dma-omap.h> 27#include <linux/omap-dma.h>
28 28
29#include "iomap.h" 29#include "iomap.h"
30#include "omap_hwmod.h" 30#include "omap_hwmod.h"
diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c
index e5aba58da5d2..612b98249873 100644
--- a/arch/arm/mach-omap2/dma.c
+++ b/arch/arm/mach-omap2/dma.c
@@ -28,7 +28,7 @@
28#include <linux/init.h> 28#include <linux/init.h>
29#include <linux/device.h> 29#include <linux/device.h>
30 30
31#include <plat-omap/dma-omap.h> 31#include <linux/omap-dma.h>
32 32
33#include "soc.h" 33#include "soc.h"
34#include "omap_hwmod.h" 34#include "omap_hwmod.h"
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index eacf51f2bc27..fafb28c0dcbc 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -29,6 +29,7 @@
29#include <linux/clkdev.h> 29#include <linux/clkdev.h>
30 30
31#include "soc.h" 31#include "soc.h"
32#include "clockdomain.h"
32#include "clock.h" 33#include "clock.h"
33#include "cm2xxx_3xxx.h" 34#include "cm2xxx_3xxx.h"
34#include "cm-regbits-34xx.h" 35#include "cm-regbits-34xx.h"
@@ -42,7 +43,7 @@
42/* Private functions */ 43/* Private functions */
43 44
44/* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */ 45/* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
45static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits) 46static void _omap3_dpll_write_clken(struct clk_hw_omap *clk, u8 clken_bits)
46{ 47{
47 const struct dpll_data *dd; 48 const struct dpll_data *dd;
48 u32 v; 49 u32 v;
@@ -56,7 +57,7 @@ static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits)
56} 57}
57 58
58/* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */ 59/* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
59static int _omap3_wait_dpll_status(struct clk *clk, u8 state) 60static int _omap3_wait_dpll_status(struct clk_hw_omap *clk, u8 state)
60{ 61{
61 const struct dpll_data *dd; 62 const struct dpll_data *dd;
62 int i = 0; 63 int i = 0;
@@ -64,7 +65,7 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
64 const char *clk_name; 65 const char *clk_name;
65 66
66 dd = clk->dpll_data; 67 dd = clk->dpll_data;
67 clk_name = __clk_get_name(clk); 68 clk_name = __clk_get_name(clk->hw.clk);
68 69
69 state <<= __ffs(dd->idlest_mask); 70 state <<= __ffs(dd->idlest_mask);
70 71
@@ -88,7 +89,7 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
88} 89}
89 90
90/* From 3430 TRM ES2 4.7.6.2 */ 91/* From 3430 TRM ES2 4.7.6.2 */
91static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n) 92static u16 _omap3_dpll_compute_freqsel(struct clk_hw_omap *clk, u8 n)
92{ 93{
93 unsigned long fint; 94 unsigned long fint;
94 u16 f = 0; 95 u16 f = 0;
@@ -133,14 +134,14 @@ static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n)
133 * locked successfully, return 0; if the DPLL did not lock in the time 134 * locked successfully, return 0; if the DPLL did not lock in the time
134 * allotted, or DPLL3 was passed in, return -EINVAL. 135 * allotted, or DPLL3 was passed in, return -EINVAL.
135 */ 136 */
136static int _omap3_noncore_dpll_lock(struct clk *clk) 137static int _omap3_noncore_dpll_lock(struct clk_hw_omap *clk)
137{ 138{
138 const struct dpll_data *dd; 139 const struct dpll_data *dd;
139 u8 ai; 140 u8 ai;
140 u8 state = 1; 141 u8 state = 1;
141 int r = 0; 142 int r = 0;
142 143
143 pr_debug("clock: locking DPLL %s\n", __clk_get_name(clk)); 144 pr_debug("clock: locking DPLL %s\n", __clk_get_name(clk->hw.clk));
144 145
145 dd = clk->dpll_data; 146 dd = clk->dpll_data;
146 state <<= __ffs(dd->idlest_mask); 147 state <<= __ffs(dd->idlest_mask);
@@ -178,7 +179,7 @@ done:
178 * DPLL3 was passed in, or the DPLL does not support low-power bypass, 179 * DPLL3 was passed in, or the DPLL does not support low-power bypass,
179 * return -EINVAL. 180 * return -EINVAL.
180 */ 181 */
181static int _omap3_noncore_dpll_bypass(struct clk *clk) 182static int _omap3_noncore_dpll_bypass(struct clk_hw_omap *clk)
182{ 183{
183 int r; 184 int r;
184 u8 ai; 185 u8 ai;
@@ -187,7 +188,7 @@ static int _omap3_noncore_dpll_bypass(struct clk *clk)
187 return -EINVAL; 188 return -EINVAL;
188 189
189 pr_debug("clock: configuring DPLL %s for low-power bypass\n", 190 pr_debug("clock: configuring DPLL %s for low-power bypass\n",
190 __clk_get_name(clk)); 191 __clk_get_name(clk->hw.clk));
191 192
192 ai = omap3_dpll_autoidle_read(clk); 193 ai = omap3_dpll_autoidle_read(clk);
193 194
@@ -210,14 +211,14 @@ static int _omap3_noncore_dpll_bypass(struct clk *clk)
210 * code. If DPLL3 was passed in, or the DPLL does not support 211 * code. If DPLL3 was passed in, or the DPLL does not support
211 * low-power stop, return -EINVAL; otherwise, return 0. 212 * low-power stop, return -EINVAL; otherwise, return 0.
212 */ 213 */
213static int _omap3_noncore_dpll_stop(struct clk *clk) 214static int _omap3_noncore_dpll_stop(struct clk_hw_omap *clk)
214{ 215{
215 u8 ai; 216 u8 ai;
216 217
217 if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP))) 218 if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP)))
218 return -EINVAL; 219 return -EINVAL;
219 220
220 pr_debug("clock: stopping DPLL %s\n", __clk_get_name(clk)); 221 pr_debug("clock: stopping DPLL %s\n", __clk_get_name(clk->hw.clk));
221 222
222 ai = omap3_dpll_autoidle_read(clk); 223 ai = omap3_dpll_autoidle_read(clk);
223 224
@@ -241,11 +242,11 @@ static int _omap3_noncore_dpll_stop(struct clk *clk)
241 * XXX This code is not needed for 3430/AM35xx; can it be optimized 242 * XXX This code is not needed for 3430/AM35xx; can it be optimized
242 * out in non-multi-OMAP builds for those chips? 243 * out in non-multi-OMAP builds for those chips?
243 */ 244 */
244static void _lookup_dco(struct clk *clk, u8 *dco, u16 m, u8 n) 245static void _lookup_dco(struct clk_hw_omap *clk, u8 *dco, u16 m, u8 n)
245{ 246{
246 unsigned long fint, clkinp; /* watch out for overflow */ 247 unsigned long fint, clkinp; /* watch out for overflow */
247 248
248 clkinp = __clk_get_rate(__clk_get_parent(clk)); 249 clkinp = __clk_get_rate(__clk_get_parent(clk->hw.clk));
249 fint = (clkinp / n) * m; 250 fint = (clkinp / n) * m;
250 251
251 if (fint < 1000000000) 252 if (fint < 1000000000)
@@ -266,12 +267,12 @@ static void _lookup_dco(struct clk *clk, u8 *dco, u16 m, u8 n)
266 * XXX This code is not needed for 3430/AM35xx; can it be optimized 267 * XXX This code is not needed for 3430/AM35xx; can it be optimized
267 * out in non-multi-OMAP builds for those chips? 268 * out in non-multi-OMAP builds for those chips?
268 */ 269 */
269static void _lookup_sddiv(struct clk *clk, u8 *sd_div, u16 m, u8 n) 270static void _lookup_sddiv(struct clk_hw_omap *clk, u8 *sd_div, u16 m, u8 n)
270{ 271{
271 unsigned long clkinp, sd; /* watch out for overflow */ 272 unsigned long clkinp, sd; /* watch out for overflow */
272 int mod1, mod2; 273 int mod1, mod2;
273 274
274 clkinp = __clk_get_rate(__clk_get_parent(clk)); 275 clkinp = __clk_get_rate(__clk_get_parent(clk->hw.clk));
275 276
276 /* 277 /*
277 * target sigma-delta to near 250MHz 278 * target sigma-delta to near 250MHz
@@ -298,7 +299,8 @@ static void _lookup_sddiv(struct clk *clk, u8 *sd_div, u16 m, u8 n)
298 * Program the DPLL with the supplied M, N values, and wait for the DPLL to 299 * Program the DPLL with the supplied M, N values, and wait for the DPLL to
299 * lock.. Returns -EINVAL upon error, or 0 upon success. 300 * lock.. Returns -EINVAL upon error, or 0 upon success.
300 */ 301 */
301static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel) 302static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 m, u8 n,
303 u16 freqsel)
302{ 304{
303 struct dpll_data *dd = clk->dpll_data; 305 struct dpll_data *dd = clk->dpll_data;
304 u8 dco, sd_div; 306 u8 dco, sd_div;
@@ -355,8 +357,10 @@ static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
355 * 357 *
356 * Recalculate and propagate the DPLL rate. 358 * Recalculate and propagate the DPLL rate.
357 */ 359 */
358unsigned long omap3_dpll_recalc(struct clk *clk) 360unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate)
359{ 361{
362 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
363
360 return omap2_get_dpll_rate(clk); 364 return omap2_get_dpll_rate(clk);
361} 365}
362 366
@@ -376,8 +380,9 @@ unsigned long omap3_dpll_recalc(struct clk *clk)
376 * support low-power stop, or if the DPLL took too long to enter 380 * support low-power stop, or if the DPLL took too long to enter
377 * bypass or lock, return -EINVAL; otherwise, return 0. 381 * bypass or lock, return -EINVAL; otherwise, return 0.
378 */ 382 */
379int omap3_noncore_dpll_enable(struct clk *clk) 383int omap3_noncore_dpll_enable(struct clk_hw *hw)
380{ 384{
385 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
381 int r; 386 int r;
382 struct dpll_data *dd; 387 struct dpll_data *dd;
383 struct clk *parent; 388 struct clk *parent;
@@ -386,22 +391,26 @@ int omap3_noncore_dpll_enable(struct clk *clk)
386 if (!dd) 391 if (!dd)
387 return -EINVAL; 392 return -EINVAL;
388 393
389 parent = __clk_get_parent(clk); 394 if (clk->clkdm) {
395 r = clkdm_clk_enable(clk->clkdm, hw->clk);
396 if (r) {
397 WARN(1,
398 "%s: could not enable %s's clockdomain %s: %d\n",
399 __func__, __clk_get_name(hw->clk),
400 clk->clkdm->name, r);
401 return r;
402 }
403 }
404
405 parent = __clk_get_parent(hw->clk);
390 406
391 if (__clk_get_rate(clk) == __clk_get_rate(dd->clk_bypass)) { 407 if (__clk_get_rate(hw->clk) == __clk_get_rate(dd->clk_bypass)) {
392 WARN_ON(parent != dd->clk_bypass); 408 WARN_ON(parent != dd->clk_bypass);
393 r = _omap3_noncore_dpll_bypass(clk); 409 r = _omap3_noncore_dpll_bypass(clk);
394 } else { 410 } else {
395 WARN_ON(parent != dd->clk_ref); 411 WARN_ON(parent != dd->clk_ref);
396 r = _omap3_noncore_dpll_lock(clk); 412 r = _omap3_noncore_dpll_lock(clk);
397 } 413 }
398 /*
399 *FIXME: this is dubious - if clk->rate has changed, what about
400 * propagating?
401 */
402 if (!r)
403 clk->rate = (clk->recalc) ? clk->recalc(clk) :
404 omap2_get_dpll_rate(clk);
405 414
406 return r; 415 return r;
407} 416}
@@ -413,9 +422,13 @@ int omap3_noncore_dpll_enable(struct clk *clk)
413 * Instructs a non-CORE DPLL to enter low-power stop. This function is 422 * Instructs a non-CORE DPLL to enter low-power stop. This function is
414 * intended for use in struct clkops. No return value. 423 * intended for use in struct clkops. No return value.
415 */ 424 */
416void omap3_noncore_dpll_disable(struct clk *clk) 425void omap3_noncore_dpll_disable(struct clk_hw *hw)
417{ 426{
427 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
428
418 _omap3_noncore_dpll_stop(clk); 429 _omap3_noncore_dpll_stop(clk);
430 if (clk->clkdm)
431 clkdm_clk_disable(clk->clkdm, hw->clk);
419} 432}
420 433
421 434
@@ -432,80 +445,72 @@ void omap3_noncore_dpll_disable(struct clk *clk)
432 * target rate if it hasn't been done already, then program and lock 445 * target rate if it hasn't been done already, then program and lock
433 * the DPLL. Returns -EINVAL upon error, or 0 upon success. 446 * the DPLL. Returns -EINVAL upon error, or 0 upon success.
434 */ 447 */
435int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate) 448int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
449 unsigned long parent_rate)
436{ 450{
451 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
437 struct clk *new_parent = NULL; 452 struct clk *new_parent = NULL;
438 unsigned long hw_rate, bypass_rate;
439 u16 freqsel = 0; 453 u16 freqsel = 0;
440 struct dpll_data *dd; 454 struct dpll_data *dd;
441 int ret; 455 int ret;
442 456
443 if (!clk || !rate) 457 if (!hw || !rate)
444 return -EINVAL; 458 return -EINVAL;
445 459
446 dd = clk->dpll_data; 460 dd = clk->dpll_data;
447 if (!dd) 461 if (!dd)
448 return -EINVAL; 462 return -EINVAL;
449 463
450 hw_rate = (clk->recalc) ? clk->recalc(clk) : omap2_get_dpll_rate(clk); 464 __clk_prepare(dd->clk_bypass);
451 if (rate == hw_rate) 465 clk_enable(dd->clk_bypass);
452 return 0; 466 __clk_prepare(dd->clk_ref);
453 467 clk_enable(dd->clk_ref);
454 /*
455 * Ensure both the bypass and ref clocks are enabled prior to
456 * doing anything; we need the bypass clock running to reprogram
457 * the DPLL.
458 */
459 omap2_clk_enable(dd->clk_bypass);
460 omap2_clk_enable(dd->clk_ref);
461 468
462 bypass_rate = __clk_get_rate(dd->clk_bypass); 469 if (__clk_get_rate(dd->clk_bypass) == rate &&
463 if (bypass_rate == rate && 470 (dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
464 (clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) { 471 pr_debug("%s: %s: set rate: entering bypass.\n",
465 pr_debug("clock: %s: set rate: entering bypass.\n", clk->name); 472 __func__, __clk_get_name(hw->clk));
466 473
467 ret = _omap3_noncore_dpll_bypass(clk); 474 ret = _omap3_noncore_dpll_bypass(clk);
468 if (!ret) 475 if (!ret)
469 new_parent = dd->clk_bypass; 476 new_parent = dd->clk_bypass;
470 } else { 477 } else {
471 if (dd->last_rounded_rate != rate) 478 if (dd->last_rounded_rate != rate)
472 rate = clk->round_rate(clk, rate); 479 rate = __clk_round_rate(hw->clk, rate);
473 480
474 if (dd->last_rounded_rate == 0) 481 if (dd->last_rounded_rate == 0)
475 return -EINVAL; 482 return -EINVAL;
476 483
477 /* No freqsel on OMAP4 and OMAP3630 */ 484 /* No freqsel on OMAP4 and OMAP3630 */
478 if (!soc_is_am33xx() && !cpu_is_omap44xx() && !cpu_is_omap3630()) { 485 if (!cpu_is_omap44xx() && !cpu_is_omap3630()) {
479 freqsel = _omap3_dpll_compute_freqsel(clk, 486 freqsel = _omap3_dpll_compute_freqsel(clk,
480 dd->last_rounded_n); 487 dd->last_rounded_n);
481 if (!freqsel) 488 if (!freqsel)
482 WARN_ON(1); 489 WARN_ON(1);
483 } 490 }
484 491
485 pr_debug("clock: %s: set rate: locking rate to %lu.\n", 492 pr_debug("%s: %s: set rate: locking rate to %lu.\n",
486 __clk_get_name(clk), rate); 493 __func__, __clk_get_name(hw->clk), rate);
487 494
488 ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m, 495 ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m,
489 dd->last_rounded_n, freqsel); 496 dd->last_rounded_n, freqsel);
490 if (!ret) 497 if (!ret)
491 new_parent = dd->clk_ref; 498 new_parent = dd->clk_ref;
492 } 499 }
493 if (!ret) { 500 /*
494 /* 501 * FIXME - this is all wrong. common code handles reparenting and
495 * Switch the parent clock in the hierarchy, and make sure 502 * migrating prepare/enable counts. dplls should be a multiplexer
496 * that the new parent's usecount is correct. Note: we 503 * clock and this should be a set_parent operation so that all of that
497 * enable the new parent before disabling the old to avoid 504 * stuff is inherited for free
498 * any unnecessary hardware disable->enable transitions. 505 */
499 */ 506
500 if (clk->usecount) { 507 if (!ret)
501 omap2_clk_enable(new_parent); 508 __clk_reparent(hw->clk, new_parent);
502 omap2_clk_disable(clk->parent); 509
503 } 510 clk_disable(dd->clk_ref);
504 clk_reparent(clk, new_parent); 511 __clk_unprepare(dd->clk_ref);
505 clk->rate = rate; 512 clk_disable(dd->clk_bypass);
506 } 513 __clk_unprepare(dd->clk_bypass);
507 omap2_clk_disable(dd->clk_ref);
508 omap2_clk_disable(dd->clk_bypass);
509 514
510 return 0; 515 return 0;
511} 516}
@@ -520,7 +525,7 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
520 * -EINVAL if passed a null pointer or if the struct clk does not 525 * -EINVAL if passed a null pointer or if the struct clk does not
521 * appear to refer to a DPLL. 526 * appear to refer to a DPLL.
522 */ 527 */
523u32 omap3_dpll_autoidle_read(struct clk *clk) 528u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk)
524{ 529{
525 const struct dpll_data *dd; 530 const struct dpll_data *dd;
526 u32 v; 531 u32 v;
@@ -549,7 +554,7 @@ u32 omap3_dpll_autoidle_read(struct clk *clk)
549 * OMAP3430. The DPLL will enter low-power stop when its downstream 554 * OMAP3430. The DPLL will enter low-power stop when its downstream
550 * clocks are gated. No return value. 555 * clocks are gated. No return value.
551 */ 556 */
552void omap3_dpll_allow_idle(struct clk *clk) 557void omap3_dpll_allow_idle(struct clk_hw_omap *clk)
553{ 558{
554 const struct dpll_data *dd; 559 const struct dpll_data *dd;
555 u32 v; 560 u32 v;
@@ -559,11 +564,8 @@ void omap3_dpll_allow_idle(struct clk *clk)
559 564
560 dd = clk->dpll_data; 565 dd = clk->dpll_data;
561 566
562 if (!dd->autoidle_reg) { 567 if (!dd->autoidle_reg)
563 pr_debug("clock: DPLL %s: autoidle not supported\n",
564 __clk_get_name(clk));
565 return; 568 return;
566 }
567 569
568 /* 570 /*
569 * REVISIT: CORE DPLL can optionally enter low-power bypass 571 * REVISIT: CORE DPLL can optionally enter low-power bypass
@@ -583,7 +585,7 @@ void omap3_dpll_allow_idle(struct clk *clk)
583 * 585 *
584 * Disable DPLL automatic idle control. No return value. 586 * Disable DPLL automatic idle control. No return value.
585 */ 587 */
586void omap3_dpll_deny_idle(struct clk *clk) 588void omap3_dpll_deny_idle(struct clk_hw_omap *clk)
587{ 589{
588 const struct dpll_data *dd; 590 const struct dpll_data *dd;
589 u32 v; 591 u32 v;
@@ -593,11 +595,8 @@ void omap3_dpll_deny_idle(struct clk *clk)
593 595
594 dd = clk->dpll_data; 596 dd = clk->dpll_data;
595 597
596 if (!dd->autoidle_reg) { 598 if (!dd->autoidle_reg)
597 pr_debug("clock: DPLL %s: autoidle not supported\n",
598 __clk_get_name(clk));
599 return; 599 return;
600 }
601 600
602 v = __raw_readl(dd->autoidle_reg); 601 v = __raw_readl(dd->autoidle_reg);
603 v &= ~dd->autoidle_mask; 602 v &= ~dd->autoidle_mask;
@@ -615,18 +614,25 @@ void omap3_dpll_deny_idle(struct clk *clk)
615 * Using parent clock DPLL data, look up DPLL state. If locked, set our 614 * Using parent clock DPLL data, look up DPLL state. If locked, set our
616 * rate to the dpll_clk * 2; otherwise, just use dpll_clk. 615 * rate to the dpll_clk * 2; otherwise, just use dpll_clk.
617 */ 616 */
618unsigned long omap3_clkoutx2_recalc(struct clk *clk) 617unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
618 unsigned long parent_rate)
619{ 619{
620 const struct dpll_data *dd; 620 const struct dpll_data *dd;
621 unsigned long rate; 621 unsigned long rate;
622 u32 v; 622 u32 v;
623 struct clk *pclk; 623 struct clk_hw_omap *pclk = NULL;
624 unsigned long parent_rate; 624 struct clk *parent;
625 625
626 /* Walk up the parents of clk, looking for a DPLL */ 626 /* Walk up the parents of clk, looking for a DPLL */
627 pclk = __clk_get_parent(clk); 627 do {
628 while (pclk && !pclk->dpll_data) 628 do {
629 pclk = __clk_get_parent(pclk); 629 parent = __clk_get_parent(hw->clk);
630 hw = __clk_get_hw(parent);
631 } while (hw && (__clk_get_flags(hw->clk) & CLK_IS_BASIC));
632 if (!hw)
633 break;
634 pclk = to_clk_hw_omap(hw);
635 } while (pclk && !pclk->dpll_data);
630 636
631 /* clk does not have a DPLL as a parent? error in the clock data */ 637 /* clk does not have a DPLL as a parent? error in the clock data */
632 if (!pclk) { 638 if (!pclk) {
@@ -638,7 +644,6 @@ unsigned long omap3_clkoutx2_recalc(struct clk *clk)
638 644
639 WARN_ON(!dd->enable_mask); 645 WARN_ON(!dd->enable_mask);
640 646
641 parent_rate = __clk_get_rate(__clk_get_parent(clk));
642 v = __raw_readl(dd->control_reg) & dd->enable_mask; 647 v = __raw_readl(dd->control_reg) & dd->enable_mask;
643 v >>= __ffs(dd->enable_mask); 648 v >>= __ffs(dd->enable_mask);
644 if ((v != OMAP3XXX_EN_DPLL_LOCKED) || (dd->flags & DPLL_J_TYPE)) 649 if ((v != OMAP3XXX_EN_DPLL_LOCKED) || (dd->flags & DPLL_J_TYPE))
@@ -649,15 +654,7 @@ unsigned long omap3_clkoutx2_recalc(struct clk *clk)
649} 654}
650 655
651/* OMAP3/4 non-CORE DPLL clkops */ 656/* OMAP3/4 non-CORE DPLL clkops */
652 657const struct clk_hw_omap_ops clkhwops_omap3_dpll = {
653const struct clkops clkops_omap3_noncore_dpll_ops = {
654 .enable = omap3_noncore_dpll_enable,
655 .disable = omap3_noncore_dpll_disable,
656 .allow_idle = omap3_dpll_allow_idle,
657 .deny_idle = omap3_dpll_deny_idle,
658};
659
660const struct clkops clkops_omap3_core_dpll_ops = {
661 .allow_idle = omap3_dpll_allow_idle, 658 .allow_idle = omap3_dpll_allow_idle,
662 .deny_idle = omap3_dpll_deny_idle, 659 .deny_idle = omap3_dpll_deny_idle,
663}; 660};
diff --git a/arch/arm/mach-omap2/dpll44xx.c b/arch/arm/mach-omap2/dpll44xx.c
index 5854da168a9c..d3326c474fdc 100644
--- a/arch/arm/mach-omap2/dpll44xx.c
+++ b/arch/arm/mach-omap2/dpll44xx.c
@@ -21,7 +21,7 @@
21#include "cm-regbits-44xx.h" 21#include "cm-regbits-44xx.h"
22 22
23/* Supported only on OMAP4 */ 23/* Supported only on OMAP4 */
24int omap4_dpllmx_gatectrl_read(struct clk *clk) 24int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk)
25{ 25{
26 u32 v; 26 u32 v;
27 u32 mask; 27 u32 mask;
@@ -40,7 +40,7 @@ int omap4_dpllmx_gatectrl_read(struct clk *clk)
40 return v; 40 return v;
41} 41}
42 42
43void omap4_dpllmx_allow_gatectrl(struct clk *clk) 43void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk)
44{ 44{
45 u32 v; 45 u32 v;
46 u32 mask; 46 u32 mask;
@@ -58,7 +58,7 @@ void omap4_dpllmx_allow_gatectrl(struct clk *clk)
58 __raw_writel(v, clk->clksel_reg); 58 __raw_writel(v, clk->clksel_reg);
59} 59}
60 60
61void omap4_dpllmx_deny_gatectrl(struct clk *clk) 61void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk)
62{ 62{
63 u32 v; 63 u32 v;
64 u32 mask; 64 u32 mask;
@@ -76,9 +76,9 @@ void omap4_dpllmx_deny_gatectrl(struct clk *clk)
76 __raw_writel(v, clk->clksel_reg); 76 __raw_writel(v, clk->clksel_reg);
77} 77}
78 78
79const struct clkops clkops_omap4_dpllmx_ops = { 79const struct clk_hw_omap_ops clkhwops_omap4_dpllmx = {
80 .allow_idle = omap4_dpllmx_allow_gatectrl, 80 .allow_idle = omap4_dpllmx_allow_gatectrl,
81 .deny_idle = omap4_dpllmx_deny_gatectrl, 81 .deny_idle = omap4_dpllmx_deny_gatectrl,
82}; 82};
83 83
84/** 84/**
@@ -90,8 +90,10 @@ const struct clkops clkops_omap4_dpllmx_ops = {
90 * OMAP4 ABE DPLL. Returns the DPLL's output rate (before M-dividers) 90 * OMAP4 ABE DPLL. Returns the DPLL's output rate (before M-dividers)
91 * upon success, or 0 upon error. 91 * upon success, or 0 upon error.
92 */ 92 */
93unsigned long omap4_dpll_regm4xen_recalc(struct clk *clk) 93unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
94 unsigned long parent_rate)
94{ 95{
96 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
95 u32 v; 97 u32 v;
96 unsigned long rate; 98 unsigned long rate;
97 struct dpll_data *dd; 99 struct dpll_data *dd;
@@ -123,8 +125,11 @@ unsigned long omap4_dpll_regm4xen_recalc(struct clk *clk)
123 * M-dividers) upon success, -EINVAL if @clk is null or not a DPLL, or 125 * M-dividers) upon success, -EINVAL if @clk is null or not a DPLL, or
124 * ~0 if an error occurred in omap2_dpll_round_rate(). 126 * ~0 if an error occurred in omap2_dpll_round_rate().
125 */ 127 */
126long omap4_dpll_regm4xen_round_rate(struct clk *clk, unsigned long target_rate) 128long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
129 unsigned long target_rate,
130 unsigned long *parent_rate)
127{ 131{
132 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
128 u32 v; 133 u32 v;
129 struct dpll_data *dd; 134 struct dpll_data *dd;
130 long r; 135 long r;
@@ -140,7 +145,7 @@ long omap4_dpll_regm4xen_round_rate(struct clk *clk, unsigned long target_rate)
140 if (v) 145 if (v)
141 target_rate = target_rate / OMAP4430_REGM4XEN_MULT; 146 target_rate = target_rate / OMAP4430_REGM4XEN_MULT;
142 147
143 r = omap2_dpll_round_rate(clk, target_rate); 148 r = omap2_dpll_round_rate(hw, target_rate, NULL);
144 if (r == ~0) 149 if (r == ~0)
145 return r; 150 return r;
146 151
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 9df757644cce..2c3fdd65387b 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -25,7 +25,7 @@
25#include <asm/tlb.h> 25#include <asm/tlb.h>
26#include <asm/mach/map.h> 26#include <asm/mach/map.h>
27 27
28#include <plat-omap/dma-omap.h> 28#include <linux/omap-dma.h>
29 29
30#include "omap_hwmod.h" 30#include "omap_hwmod.h"
31#include "soc.h" 31#include "soc.h"
@@ -50,6 +50,9 @@
50#include "prcm_mpu44xx.h" 50#include "prcm_mpu44xx.h"
51#include "prminst44xx.h" 51#include "prminst44xx.h"
52#include "cminst44xx.h" 52#include "cminst44xx.h"
53#include "prm2xxx.h"
54#include "prm3xxx.h"
55#include "prm44xx.h"
53 56
54/* 57/*
55 * The machine specific code may provide the extra mapping besides the 58 * The machine specific code may provide the extra mapping besides the
@@ -387,6 +390,7 @@ void __init omap2420_init_early(void)
387 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE)); 390 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE));
388 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE), NULL); 391 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE), NULL);
389 omap2xxx_check_revision(); 392 omap2xxx_check_revision();
393 omap2xxx_prm_init();
390 omap2xxx_cm_init(); 394 omap2xxx_cm_init();
391 omap2xxx_voltagedomains_init(); 395 omap2xxx_voltagedomains_init();
392 omap242x_powerdomains_init(); 396 omap242x_powerdomains_init();
@@ -401,6 +405,7 @@ void __init omap2420_init_late(void)
401 omap_mux_late_init(); 405 omap_mux_late_init();
402 omap2_common_pm_late_init(); 406 omap2_common_pm_late_init();
403 omap2_pm_init(); 407 omap2_pm_init();
408 omap2_clk_enable_autoidle_all();
404} 409}
405#endif 410#endif
406 411
@@ -415,6 +420,7 @@ void __init omap2430_init_early(void)
415 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE)); 420 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE));
416 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE), NULL); 421 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE), NULL);
417 omap2xxx_check_revision(); 422 omap2xxx_check_revision();
423 omap2xxx_prm_init();
418 omap2xxx_cm_init(); 424 omap2xxx_cm_init();
419 omap2xxx_voltagedomains_init(); 425 omap2xxx_voltagedomains_init();
420 omap243x_powerdomains_init(); 426 omap243x_powerdomains_init();
@@ -429,6 +435,7 @@ void __init omap2430_init_late(void)
429 omap_mux_late_init(); 435 omap_mux_late_init();
430 omap2_common_pm_late_init(); 436 omap2_common_pm_late_init();
431 omap2_pm_init(); 437 omap2_pm_init();
438 omap2_clk_enable_autoidle_all();
432} 439}
433#endif 440#endif
434 441
@@ -448,6 +455,7 @@ void __init omap3_init_early(void)
448 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE), NULL); 455 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE), NULL);
449 omap3xxx_check_revision(); 456 omap3xxx_check_revision();
450 omap3xxx_check_features(); 457 omap3xxx_check_features();
458 omap3xxx_prm_init();
451 omap3xxx_cm_init(); 459 omap3xxx_cm_init();
452 omap3xxx_voltagedomains_init(); 460 omap3xxx_voltagedomains_init();
453 omap3xxx_powerdomains_init(); 461 omap3xxx_powerdomains_init();
@@ -500,6 +508,7 @@ void __init omap3_init_late(void)
500 omap_mux_late_init(); 508 omap_mux_late_init();
501 omap2_common_pm_late_init(); 509 omap2_common_pm_late_init();
502 omap3_pm_init(); 510 omap3_pm_init();
511 omap2_clk_enable_autoidle_all();
503} 512}
504 513
505void __init omap3430_init_late(void) 514void __init omap3430_init_late(void)
@@ -507,6 +516,7 @@ void __init omap3430_init_late(void)
507 omap_mux_late_init(); 516 omap_mux_late_init();
508 omap2_common_pm_late_init(); 517 omap2_common_pm_late_init();
509 omap3_pm_init(); 518 omap3_pm_init();
519 omap2_clk_enable_autoidle_all();
510} 520}
511 521
512void __init omap35xx_init_late(void) 522void __init omap35xx_init_late(void)
@@ -514,6 +524,7 @@ void __init omap35xx_init_late(void)
514 omap_mux_late_init(); 524 omap_mux_late_init();
515 omap2_common_pm_late_init(); 525 omap2_common_pm_late_init();
516 omap3_pm_init(); 526 omap3_pm_init();
527 omap2_clk_enable_autoidle_all();
517} 528}
518 529
519void __init omap3630_init_late(void) 530void __init omap3630_init_late(void)
@@ -521,6 +532,7 @@ void __init omap3630_init_late(void)
521 omap_mux_late_init(); 532 omap_mux_late_init();
522 omap2_common_pm_late_init(); 533 omap2_common_pm_late_init();
523 omap3_pm_init(); 534 omap3_pm_init();
535 omap2_clk_enable_autoidle_all();
524} 536}
525 537
526void __init am35xx_init_late(void) 538void __init am35xx_init_late(void)
@@ -528,6 +540,7 @@ void __init am35xx_init_late(void)
528 omap_mux_late_init(); 540 omap_mux_late_init();
529 omap2_common_pm_late_init(); 541 omap2_common_pm_late_init();
530 omap3_pm_init(); 542 omap3_pm_init();
543 omap2_clk_enable_autoidle_all();
531} 544}
532 545
533void __init ti81xx_init_late(void) 546void __init ti81xx_init_late(void)
@@ -535,6 +548,7 @@ void __init ti81xx_init_late(void)
535 omap_mux_late_init(); 548 omap_mux_late_init();
536 omap2_common_pm_late_init(); 549 omap2_common_pm_late_init();
537 omap3_pm_init(); 550 omap3_pm_init();
551 omap2_clk_enable_autoidle_all();
538} 552}
539#endif 553#endif
540 554
@@ -573,6 +587,7 @@ void __init omap4430_init_early(void)
573 omap_cm_base_init(); 587 omap_cm_base_init();
574 omap4xxx_check_revision(); 588 omap4xxx_check_revision();
575 omap4xxx_check_features(); 589 omap4xxx_check_features();
590 omap44xx_prm_init();
576 omap44xx_voltagedomains_init(); 591 omap44xx_voltagedomains_init();
577 omap44xx_powerdomains_init(); 592 omap44xx_powerdomains_init();
578 omap44xx_clockdomains_init(); 593 omap44xx_clockdomains_init();
@@ -586,6 +601,7 @@ void __init omap4430_init_late(void)
586 omap_mux_late_init(); 601 omap_mux_late_init();
587 omap2_common_pm_late_init(); 602 omap2_common_pm_late_init();
588 omap4_pm_init(); 603 omap4_pm_init();
604 omap2_clk_enable_autoidle_all();
589} 605}
590#endif 606#endif
591 607
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index bf496510eb5e..df49f2a49461 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -21,7 +21,7 @@
21#include <linux/platform_data/asoc-ti-mcbsp.h> 21#include <linux/platform_data/asoc-ti-mcbsp.h>
22#include <linux/pm_runtime.h> 22#include <linux/pm_runtime.h>
23 23
24#include <plat-omap/dma-omap.h> 24#include <linux/omap-dma.h>
25 25
26#include "omap_device.h" 26#include "omap_device.h"
27 27
diff --git a/arch/arm/mach-omap2/omap_device.c b/arch/arm/mach-omap2/omap_device.c
index 0ef934fec364..e065daa537c0 100644
--- a/arch/arm/mach-omap2/omap_device.c
+++ b/arch/arm/mach-omap2/omap_device.c
@@ -441,19 +441,21 @@ int omap_device_get_context_loss_count(struct platform_device *pdev)
441/** 441/**
442 * omap_device_count_resources - count number of struct resource entries needed 442 * omap_device_count_resources - count number of struct resource entries needed
443 * @od: struct omap_device * 443 * @od: struct omap_device *
444 * @flags: Type of resources to include when counting (IRQ/DMA/MEM)
444 * 445 *
445 * Count the number of struct resource entries needed for this 446 * Count the number of struct resource entries needed for this
446 * omap_device @od. Used by omap_device_build_ss() to determine how 447 * omap_device @od. Used by omap_device_build_ss() to determine how
447 * much memory to allocate before calling 448 * much memory to allocate before calling
448 * omap_device_fill_resources(). Returns the count. 449 * omap_device_fill_resources(). Returns the count.
449 */ 450 */
450static int omap_device_count_resources(struct omap_device *od) 451static int omap_device_count_resources(struct omap_device *od,
452 unsigned long flags)
451{ 453{
452 int c = 0; 454 int c = 0;
453 int i; 455 int i;
454 456
455 for (i = 0; i < od->hwmods_cnt; i++) 457 for (i = 0; i < od->hwmods_cnt; i++)
456 c += omap_hwmod_count_resources(od->hwmods[i]); 458 c += omap_hwmod_count_resources(od->hwmods[i], flags);
457 459
458 pr_debug("omap_device: %s: counted %d total resources across %d hwmods\n", 460 pr_debug("omap_device: %s: counted %d total resources across %d hwmods\n",
459 od->pdev->name, c, od->hwmods_cnt); 461 od->pdev->name, c, od->hwmods_cnt);
@@ -557,52 +559,73 @@ struct omap_device *omap_device_alloc(struct platform_device *pdev,
557 od->hwmods = hwmods; 559 od->hwmods = hwmods;
558 od->pdev = pdev; 560 od->pdev = pdev;
559 561
560 res_count = omap_device_count_resources(od);
561 /* 562 /*
563 * Non-DT Boot:
564 * Here, pdev->num_resources = 0, and we should get all the
565 * resources from hwmod.
566 *
562 * DT Boot: 567 * DT Boot:
563 * OF framework will construct the resource structure (currently 568 * OF framework will construct the resource structure (currently
564 * does for MEM & IRQ resource) and we should respect/use these 569 * does for MEM & IRQ resource) and we should respect/use these
565 * resources, killing hwmod dependency. 570 * resources, killing hwmod dependency.
566 * If pdev->num_resources > 0, we assume that MEM & IRQ resources 571 * If pdev->num_resources > 0, we assume that MEM & IRQ resources
567 * have been allocated by OF layer already (through DTB). 572 * have been allocated by OF layer already (through DTB).
568 * 573 * As preparation for the future we examine the OF provided resources
569 * Non-DT Boot: 574 * to see if we have DMA resources provided already. In this case
570 * Here, pdev->num_resources = 0, and we should get all the 575 * there is no need to update the resources for the device, we use the
571 * resources from hwmod. 576 * OF provided ones.
572 * 577 *
573 * TODO: Once DMA resource is available from OF layer, we should 578 * TODO: Once DMA resource is available from OF layer, we should
574 * kill filling any resources from hwmod. 579 * kill filling any resources from hwmod.
575 */ 580 */
576 if (res_count > pdev->num_resources) { 581 if (!pdev->num_resources) {
577 /* Allocate resources memory to account for new resources */ 582 /* Count all resources for the device */
578 res = kzalloc(sizeof(struct resource) * res_count, GFP_KERNEL); 583 res_count = omap_device_count_resources(od, IORESOURCE_IRQ |
579 if (!res) 584 IORESOURCE_DMA |
580 goto oda_exit3; 585 IORESOURCE_MEM);
581 586 } else {
582 /* 587 /* Take a look if we already have DMA resource via DT */
583 * If pdev->num_resources > 0, then assume that, 588 for (i = 0; i < pdev->num_resources; i++) {
584 * MEM and IRQ resources will only come from DT and only 589 struct resource *r = &pdev->resource[i];
585 * fill DMA resource from hwmod layer. 590
586 */ 591 /* We have it, no need to touch the resources */
587 if (pdev->num_resources && pdev->resource) { 592 if (r->flags == IORESOURCE_DMA)
588 dev_dbg(&pdev->dev, "%s(): resources already allocated %d\n", 593 goto have_everything;
589 __func__, res_count);
590 memcpy(res, pdev->resource,
591 sizeof(struct resource) * pdev->num_resources);
592 _od_fill_dma_resources(od, &res[pdev->num_resources]);
593 } else {
594 dev_dbg(&pdev->dev, "%s(): using resources from hwmod %d\n",
595 __func__, res_count);
596 omap_device_fill_resources(od, res);
597 } 594 }
595 /* Count only DMA resources for the device */
596 res_count = omap_device_count_resources(od, IORESOURCE_DMA);
597 /* The device has no DMA resource, no need for update */
598 if (!res_count)
599 goto have_everything;
598 600
599 ret = platform_device_add_resources(pdev, res, res_count); 601 res_count += pdev->num_resources;
600 kfree(res); 602 }
601 603
602 if (ret) 604 /* Allocate resources memory to account for new resources */
603 goto oda_exit3; 605 res = kzalloc(sizeof(struct resource) * res_count, GFP_KERNEL);
606 if (!res)
607 goto oda_exit3;
608
609 if (!pdev->num_resources) {
610 dev_dbg(&pdev->dev, "%s: using %d resources from hwmod\n",
611 __func__, res_count);
612 omap_device_fill_resources(od, res);
613 } else {
614 dev_dbg(&pdev->dev,
615 "%s: appending %d DMA resources from hwmod\n",
616 __func__, res_count - pdev->num_resources);
617 memcpy(res, pdev->resource,
618 sizeof(struct resource) * pdev->num_resources);
619 _od_fill_dma_resources(od, &res[pdev->num_resources]);
604 } 620 }
605 621
622 ret = platform_device_add_resources(pdev, res, res_count);
623 kfree(res);
624
625 if (ret)
626 goto oda_exit3;
627
628have_everything:
606 if (!pm_lats) { 629 if (!pm_lats) {
607 pm_lats = omap_default_latency; 630 pm_lats = omap_default_latency;
608 pm_lats_cnt = ARRAY_SIZE(omap_default_latency); 631 pm_lats_cnt = ARRAY_SIZE(omap_default_latency);
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index b3b00f43dd7c..4653efb87a27 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -130,7 +130,7 @@
130#include <linux/kernel.h> 130#include <linux/kernel.h>
131#include <linux/errno.h> 131#include <linux/errno.h>
132#include <linux/io.h> 132#include <linux/io.h>
133#include <linux/clk.h> 133#include <linux/clk-provider.h>
134#include <linux/delay.h> 134#include <linux/delay.h>
135#include <linux/err.h> 135#include <linux/err.h>
136#include <linux/list.h> 136#include <linux/list.h>
@@ -187,6 +187,8 @@ struct omap_hwmod_soc_ops {
187 int (*is_hardreset_asserted)(struct omap_hwmod *oh, 187 int (*is_hardreset_asserted)(struct omap_hwmod *oh,
188 struct omap_hwmod_rst_info *ohri); 188 struct omap_hwmod_rst_info *ohri);
189 int (*init_clkdm)(struct omap_hwmod *oh); 189 int (*init_clkdm)(struct omap_hwmod *oh);
190 void (*update_context_lost)(struct omap_hwmod *oh);
191 int (*get_context_lost)(struct omap_hwmod *oh);
190}; 192};
191 193
192/* soc_ops: adapts the omap_hwmod code to the currently-booted SoC */ 194/* soc_ops: adapts the omap_hwmod code to the currently-booted SoC */
@@ -646,6 +648,19 @@ static int _disable_wakeup(struct omap_hwmod *oh, u32 *v)
646 return 0; 648 return 0;
647} 649}
648 650
651static struct clockdomain *_get_clkdm(struct omap_hwmod *oh)
652{
653 struct clk_hw_omap *clk;
654
655 if (oh->clkdm) {
656 return oh->clkdm;
657 } else if (oh->_clk) {
658 clk = to_clk_hw_omap(__clk_get_hw(oh->_clk));
659 return clk->clkdm;
660 }
661 return NULL;
662}
663
649/** 664/**
650 * _add_initiator_dep: prevent @oh from smart-idling while @init_oh is active 665 * _add_initiator_dep: prevent @oh from smart-idling while @init_oh is active
651 * @oh: struct omap_hwmod * 666 * @oh: struct omap_hwmod *
@@ -661,13 +676,18 @@ static int _disable_wakeup(struct omap_hwmod *oh, u32 *v)
661 */ 676 */
662static int _add_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh) 677static int _add_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh)
663{ 678{
664 if (!oh->_clk) 679 struct clockdomain *clkdm, *init_clkdm;
680
681 clkdm = _get_clkdm(oh);
682 init_clkdm = _get_clkdm(init_oh);
683
684 if (!clkdm || !init_clkdm)
665 return -EINVAL; 685 return -EINVAL;
666 686
667 if (oh->_clk->clkdm && oh->_clk->clkdm->flags & CLKDM_NO_AUTODEPS) 687 if (clkdm && clkdm->flags & CLKDM_NO_AUTODEPS)
668 return 0; 688 return 0;
669 689
670 return clkdm_add_sleepdep(oh->_clk->clkdm, init_oh->_clk->clkdm); 690 return clkdm_add_sleepdep(clkdm, init_clkdm);
671} 691}
672 692
673/** 693/**
@@ -685,13 +705,18 @@ static int _add_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh)
685 */ 705 */
686static int _del_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh) 706static int _del_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh)
687{ 707{
688 if (!oh->_clk) 708 struct clockdomain *clkdm, *init_clkdm;
709
710 clkdm = _get_clkdm(oh);
711 init_clkdm = _get_clkdm(init_oh);
712
713 if (!clkdm || !init_clkdm)
689 return -EINVAL; 714 return -EINVAL;
690 715
691 if (oh->_clk->clkdm && oh->_clk->clkdm->flags & CLKDM_NO_AUTODEPS) 716 if (clkdm && clkdm->flags & CLKDM_NO_AUTODEPS)
692 return 0; 717 return 0;
693 718
694 return clkdm_del_sleepdep(oh->_clk->clkdm, init_oh->_clk->clkdm); 719 return clkdm_del_sleepdep(clkdm, init_clkdm);
695} 720}
696 721
697/** 722/**
@@ -725,7 +750,7 @@ static int _init_main_clk(struct omap_hwmod *oh)
725 */ 750 */
726 clk_prepare(oh->_clk); 751 clk_prepare(oh->_clk);
727 752
728 if (!oh->_clk->clkdm) 753 if (!_get_clkdm(oh))
729 pr_debug("omap_hwmod: %s: missing clockdomain for %s.\n", 754 pr_debug("omap_hwmod: %s: missing clockdomain for %s.\n",
730 oh->name, oh->main_clk); 755 oh->name, oh->main_clk);
731 756
@@ -1308,6 +1333,7 @@ static void _enable_sysc(struct omap_hwmod *oh)
1308 u8 idlemode, sf; 1333 u8 idlemode, sf;
1309 u32 v; 1334 u32 v;
1310 bool clkdm_act; 1335 bool clkdm_act;
1336 struct clockdomain *clkdm;
1311 1337
1312 if (!oh->class->sysc) 1338 if (!oh->class->sysc)
1313 return; 1339 return;
@@ -1327,11 +1353,9 @@ static void _enable_sysc(struct omap_hwmod *oh)
1327 v = oh->_sysc_cache; 1353 v = oh->_sysc_cache;
1328 sf = oh->class->sysc->sysc_flags; 1354 sf = oh->class->sysc->sysc_flags;
1329 1355
1356 clkdm = _get_clkdm(oh);
1330 if (sf & SYSC_HAS_SIDLEMODE) { 1357 if (sf & SYSC_HAS_SIDLEMODE) {
1331 clkdm_act = ((oh->clkdm && 1358 clkdm_act = (clkdm && clkdm->flags & CLKDM_ACTIVE_WITH_MPU);
1332 oh->clkdm->flags & CLKDM_ACTIVE_WITH_MPU) ||
1333 (oh->_clk && oh->_clk->clkdm &&
1334 oh->_clk->clkdm->flags & CLKDM_ACTIVE_WITH_MPU));
1335 if (clkdm_act && !(oh->class->sysc->idlemodes & 1359 if (clkdm_act && !(oh->class->sysc->idlemodes &
1336 (SIDLE_SMART | SIDLE_SMART_WKUP))) 1360 (SIDLE_SMART | SIDLE_SMART_WKUP)))
1337 idlemode = HWMOD_IDLEMODE_FORCE; 1361 idlemode = HWMOD_IDLEMODE_FORCE;
@@ -1533,11 +1557,12 @@ static int _init_clocks(struct omap_hwmod *oh, void *data)
1533 1557
1534 pr_debug("omap_hwmod: %s: looking up clocks\n", oh->name); 1558 pr_debug("omap_hwmod: %s: looking up clocks\n", oh->name);
1535 1559
1560 if (soc_ops.init_clkdm)
1561 ret |= soc_ops.init_clkdm(oh);
1562
1536 ret |= _init_main_clk(oh); 1563 ret |= _init_main_clk(oh);
1537 ret |= _init_interface_clks(oh); 1564 ret |= _init_interface_clks(oh);
1538 ret |= _init_opt_clks(oh); 1565 ret |= _init_opt_clks(oh);
1539 if (soc_ops.init_clkdm)
1540 ret |= soc_ops.init_clkdm(oh);
1541 1566
1542 if (!ret) 1567 if (!ret)
1543 oh->_state = _HWMOD_STATE_CLKS_INITED; 1568 oh->_state = _HWMOD_STATE_CLKS_INITED;
@@ -1992,6 +2017,42 @@ static void _reconfigure_io_chain(void)
1992} 2017}
1993 2018
1994/** 2019/**
2020 * _omap4_update_context_lost - increment hwmod context loss counter if
2021 * hwmod context was lost, and clear hardware context loss reg
2022 * @oh: hwmod to check for context loss
2023 *
2024 * If the PRCM indicates that the hwmod @oh lost context, increment
2025 * our in-memory context loss counter, and clear the RM_*_CONTEXT
2026 * bits. No return value.
2027 */
2028static void _omap4_update_context_lost(struct omap_hwmod *oh)
2029{
2030 if (oh->prcm.omap4.flags & HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT)
2031 return;
2032
2033 if (!prm_was_any_context_lost_old(oh->clkdm->pwrdm.ptr->prcm_partition,
2034 oh->clkdm->pwrdm.ptr->prcm_offs,
2035 oh->prcm.omap4.context_offs))
2036 return;
2037
2038 oh->prcm.omap4.context_lost_counter++;
2039 prm_clear_context_loss_flags_old(oh->clkdm->pwrdm.ptr->prcm_partition,
2040 oh->clkdm->pwrdm.ptr->prcm_offs,
2041 oh->prcm.omap4.context_offs);
2042}
2043
2044/**
2045 * _omap4_get_context_lost - get context loss counter for a hwmod
2046 * @oh: hwmod to get context loss counter for
2047 *
2048 * Returns the in-memory context loss counter for a hwmod.
2049 */
2050static int _omap4_get_context_lost(struct omap_hwmod *oh)
2051{
2052 return oh->prcm.omap4.context_lost_counter;
2053}
2054
2055/**
1995 * _enable - enable an omap_hwmod 2056 * _enable - enable an omap_hwmod
1996 * @oh: struct omap_hwmod * 2057 * @oh: struct omap_hwmod *
1997 * 2058 *
@@ -2074,6 +2135,9 @@ static int _enable(struct omap_hwmod *oh)
2074 if (soc_ops.enable_module) 2135 if (soc_ops.enable_module)
2075 soc_ops.enable_module(oh); 2136 soc_ops.enable_module(oh);
2076 2137
2138 if (soc_ops.update_context_lost)
2139 soc_ops.update_context_lost(oh);
2140
2077 r = (soc_ops.wait_target_ready) ? soc_ops.wait_target_ready(oh) : 2141 r = (soc_ops.wait_target_ready) ? soc_ops.wait_target_ready(oh) :
2078 -EINVAL; 2142 -EINVAL;
2079 if (!r) { 2143 if (!r) {
@@ -3398,7 +3462,7 @@ int omap_hwmod_reset(struct omap_hwmod *oh)
3398/** 3462/**
3399 * omap_hwmod_count_resources - count number of struct resources needed by hwmod 3463 * omap_hwmod_count_resources - count number of struct resources needed by hwmod
3400 * @oh: struct omap_hwmod * 3464 * @oh: struct omap_hwmod *
3401 * @res: pointer to the first element of an array of struct resource to fill 3465 * @flags: Type of resources to include when counting (IRQ/DMA/MEM)
3402 * 3466 *
3403 * Count the number of struct resource array elements necessary to 3467 * Count the number of struct resource array elements necessary to
3404 * contain omap_hwmod @oh resources. Intended to be called by code 3468 * contain omap_hwmod @oh resources. Intended to be called by code
@@ -3411,20 +3475,25 @@ int omap_hwmod_reset(struct omap_hwmod *oh)
3411 * resource IDs. 3475 * resource IDs.
3412 * 3476 *
3413 */ 3477 */
3414int omap_hwmod_count_resources(struct omap_hwmod *oh) 3478int omap_hwmod_count_resources(struct omap_hwmod *oh, unsigned long flags)
3415{ 3479{
3416 struct omap_hwmod_ocp_if *os; 3480 int ret = 0;
3417 struct list_head *p;
3418 int ret;
3419 int i = 0;
3420 3481
3421 ret = _count_mpu_irqs(oh) + _count_sdma_reqs(oh); 3482 if (flags & IORESOURCE_IRQ)
3483 ret += _count_mpu_irqs(oh);
3422 3484
3423 p = oh->slave_ports.next; 3485 if (flags & IORESOURCE_DMA)
3486 ret += _count_sdma_reqs(oh);
3424 3487
3425 while (i < oh->slaves_cnt) { 3488 if (flags & IORESOURCE_MEM) {
3426 os = _fetch_next_ocp_if(&p, &i); 3489 int i = 0;
3427 ret += _count_ocp_if_addr_spaces(os); 3490 struct omap_hwmod_ocp_if *os;
3491 struct list_head *p = oh->slave_ports.next;
3492
3493 while (i < oh->slaves_cnt) {
3494 os = _fetch_next_ocp_if(&p, &i);
3495 ret += _count_ocp_if_addr_spaces(os);
3496 }
3428 } 3497 }
3429 3498
3430 return ret; 3499 return ret;
@@ -3591,10 +3660,15 @@ struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh)
3591{ 3660{
3592 struct clk *c; 3661 struct clk *c;
3593 struct omap_hwmod_ocp_if *oi; 3662 struct omap_hwmod_ocp_if *oi;
3663 struct clockdomain *clkdm;
3664 struct clk_hw_omap *clk;
3594 3665
3595 if (!oh) 3666 if (!oh)
3596 return NULL; 3667 return NULL;
3597 3668
3669 if (oh->clkdm)
3670 return oh->clkdm->pwrdm.ptr;
3671
3598 if (oh->_clk) { 3672 if (oh->_clk) {
3599 c = oh->_clk; 3673 c = oh->_clk;
3600 } else { 3674 } else {
@@ -3604,11 +3678,12 @@ struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh)
3604 c = oi->_clk; 3678 c = oi->_clk;
3605 } 3679 }
3606 3680
3607 if (!c->clkdm) 3681 clk = to_clk_hw_omap(__clk_get_hw(c));
3682 clkdm = clk->clkdm;
3683 if (!clkdm)
3608 return NULL; 3684 return NULL;
3609 3685
3610 return c->clkdm->pwrdm.ptr; 3686 return clkdm->pwrdm.ptr;
3611
3612} 3687}
3613 3688
3614/** 3689/**
@@ -3913,17 +3988,21 @@ ohsps_unlock:
3913 * omap_hwmod_get_context_loss_count - get lost context count 3988 * omap_hwmod_get_context_loss_count - get lost context count
3914 * @oh: struct omap_hwmod * 3989 * @oh: struct omap_hwmod *
3915 * 3990 *
3916 * Query the powerdomain of of @oh to get the context loss 3991 * Returns the context loss count of associated @oh
3917 * count for this device. 3992 * upon success, or zero if no context loss data is available.
3918 * 3993 *
3919 * Returns the context loss count of the powerdomain assocated with @oh 3994 * On OMAP4, this queries the per-hwmod context loss register,
3920 * upon success, or zero if no powerdomain exists for @oh. 3995 * assuming one exists. If not, or on OMAP2/3, this queries the
3996 * enclosing powerdomain context loss count.
3921 */ 3997 */
3922int omap_hwmod_get_context_loss_count(struct omap_hwmod *oh) 3998int omap_hwmod_get_context_loss_count(struct omap_hwmod *oh)
3923{ 3999{
3924 struct powerdomain *pwrdm; 4000 struct powerdomain *pwrdm;
3925 int ret = 0; 4001 int ret = 0;
3926 4002
4003 if (soc_ops.get_context_lost)
4004 return soc_ops.get_context_lost(oh);
4005
3927 pwrdm = omap_hwmod_get_pwrdm(oh); 4006 pwrdm = omap_hwmod_get_pwrdm(oh);
3928 if (pwrdm) 4007 if (pwrdm)
3929 ret = pwrdm_get_context_loss_count(pwrdm); 4008 ret = pwrdm_get_context_loss_count(pwrdm);
@@ -4038,6 +4117,8 @@ void __init omap_hwmod_init(void)
4038 soc_ops.deassert_hardreset = _omap4_deassert_hardreset; 4117 soc_ops.deassert_hardreset = _omap4_deassert_hardreset;
4039 soc_ops.is_hardreset_asserted = _omap4_is_hardreset_asserted; 4118 soc_ops.is_hardreset_asserted = _omap4_is_hardreset_asserted;
4040 soc_ops.init_clkdm = _init_clkdm; 4119 soc_ops.init_clkdm = _init_clkdm;
4120 soc_ops.update_context_lost = _omap4_update_context_lost;
4121 soc_ops.get_context_lost = _omap4_get_context_lost;
4041 } else if (soc_is_am33xx()) { 4122 } else if (soc_is_am33xx()) {
4042 soc_ops.enable_module = _am33xx_enable_module; 4123 soc_ops.enable_module = _am33xx_enable_module;
4043 soc_ops.disable_module = _am33xx_disable_module; 4124 soc_ops.disable_module = _am33xx_disable_module;
diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h
index 87a3c5b7aa74..3ae852a522f9 100644
--- a/arch/arm/mach-omap2/omap_hwmod.h
+++ b/arch/arm/mach-omap2/omap_hwmod.h
@@ -2,7 +2,7 @@
2 * omap_hwmod macros, structures 2 * omap_hwmod macros, structures
3 * 3 *
4 * Copyright (C) 2009-2011 Nokia Corporation 4 * Copyright (C) 2009-2011 Nokia Corporation
5 * Copyright (C) 2012 Texas Instruments, Inc. 5 * Copyright (C) 2011-2012 Texas Instruments, Inc.
6 * Paul Walmsley 6 * Paul Walmsley
7 * 7 *
8 * Created in collaboration with (alphabetical order): Benoît Cousson, 8 * Created in collaboration with (alphabetical order): Benoît Cousson,
@@ -394,12 +394,15 @@ struct omap_hwmod_omap2_prcm {
394 394
395/** 395/**
396 * struct omap_hwmod_omap4_prcm - OMAP4-specific PRCM data 396 * struct omap_hwmod_omap4_prcm - OMAP4-specific PRCM data
397 * @clkctrl_reg: PRCM address of the clock control register 397 * @clkctrl_offs: offset of the PRCM clock control register
398 * @rstctrl_reg: address of the XXX_RSTCTRL register located in the PRM 398 * @rstctrl_offs: offset of the XXX_RSTCTRL register located in the PRM
399 * @context_offs: offset of the RM_*_CONTEXT register
399 * @lostcontext_mask: bitmask for selecting bits from RM_*_CONTEXT register 400 * @lostcontext_mask: bitmask for selecting bits from RM_*_CONTEXT register
400 * @rstst_reg: (AM33XX only) address of the XXX_RSTST register in the PRM 401 * @rstst_reg: (AM33XX only) address of the XXX_RSTST register in the PRM
401 * @submodule_wkdep_bit: bit shift of the WKDEP range 402 * @submodule_wkdep_bit: bit shift of the WKDEP range
402 * @flags: PRCM register capabilities for this IP block 403 * @flags: PRCM register capabilities for this IP block
404 * @modulemode: allowable modulemodes
405 * @context_lost_counter: Count of module level context lost
403 * 406 *
404 * If @lostcontext_mask is not defined, context loss check code uses 407 * If @lostcontext_mask is not defined, context loss check code uses
405 * whole register without masking. @lostcontext_mask should only be 408 * whole register without masking. @lostcontext_mask should only be
@@ -415,6 +418,7 @@ struct omap_hwmod_omap4_prcm {
415 u8 submodule_wkdep_bit; 418 u8 submodule_wkdep_bit;
416 u8 modulemode; 419 u8 modulemode;
417 u8 flags; 420 u8 flags;
421 int context_lost_counter;
418}; 422};
419 423
420 424
@@ -633,7 +637,7 @@ void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs);
633u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs); 637u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs);
634int omap_hwmod_softreset(struct omap_hwmod *oh); 638int omap_hwmod_softreset(struct omap_hwmod *oh);
635 639
636int omap_hwmod_count_resources(struct omap_hwmod *oh); 640int omap_hwmod_count_resources(struct omap_hwmod *oh, unsigned long flags);
637int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res); 641int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res);
638int omap_hwmod_fill_dma_resources(struct omap_hwmod *oh, struct resource *res); 642int omap_hwmod_fill_dma_resources(struct omap_hwmod *oh, struct resource *res);
639int omap_hwmod_get_resource_byname(struct omap_hwmod *oh, unsigned int type, 643int omap_hwmod_get_resource_byname(struct omap_hwmod *oh, unsigned int type,
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index e8efe3d1da6c..b5efe58c0be0 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -15,8 +15,8 @@
15 15
16#include <linux/i2c-omap.h> 16#include <linux/i2c-omap.h>
17#include <linux/platform_data/spi-omap2-mcspi.h> 17#include <linux/platform_data/spi-omap2-mcspi.h>
18 18#include <linux/omap-dma.h>
19#include <plat-omap/dma-omap.h> 19#include <plat/dmtimer.h>
20 20
21#include "omap_hwmod.h" 21#include "omap_hwmod.h"
22#include "l3_2xxx.h" 22#include "l3_2xxx.h"
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index 32d17e3fd727..6c8fa70ddadd 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -16,8 +16,8 @@
16#include <linux/i2c-omap.h> 16#include <linux/i2c-omap.h>
17#include <linux/platform_data/asoc-ti-mcbsp.h> 17#include <linux/platform_data/asoc-ti-mcbsp.h>
18#include <linux/platform_data/spi-omap2-mcspi.h> 18#include <linux/platform_data/spi-omap2-mcspi.h>
19 19#include <linux/omap-dma.h>
20#include <plat-omap/dma-omap.h> 20#include <plat/dmtimer.h>
21 21
22#include "omap_hwmod.h" 22#include "omap_hwmod.h"
23#include "mmc.h" 23#include "mmc.h"
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
index 40d6c93d9853..534974e08add 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
@@ -10,7 +10,8 @@
10 * published by the Free Software Foundation. 10 * published by the Free Software Foundation.
11 */ 11 */
12 12
13#include <plat-omap/dma-omap.h> 13#include <linux/dmaengine.h>
14#include <linux/omap-dma.h>
14 15
15#include "omap_hwmod.h" 16#include "omap_hwmod.h"
16#include "hdq1w.h" 17#include "hdq1w.h"
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
index 0db8f450bad9..e596117004d4 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
@@ -10,7 +10,7 @@
10 */ 10 */
11 11
12#include <linux/platform_data/gpio-omap.h> 12#include <linux/platform_data/gpio-omap.h>
13#include <plat-omap/dma-omap.h> 13#include <linux/omap-dma.h>
14#include <plat/dmtimer.h> 14#include <plat/dmtimer.h>
15#include <linux/platform_data/spi-omap2-mcspi.h> 15#include <linux/platform_data/spi-omap2-mcspi.h>
16 16
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 7f73f2132acc..ec4499e5a4c9 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -19,7 +19,7 @@
19#include <linux/power/smartreflex.h> 19#include <linux/power/smartreflex.h>
20#include <linux/platform_data/gpio-omap.h> 20#include <linux/platform_data/gpio-omap.h>
21 21
22#include <plat-omap/dma-omap.h> 22#include <linux/omap-dma.h>
23#include "l3_3xxx.h" 23#include "l3_3xxx.h"
24#include "l4_3xxx.h" 24#include "l4_3xxx.h"
25#include <linux/platform_data/asoc-ti-mcbsp.h> 25#include <linux/platform_data/asoc-ti-mcbsp.h>
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 26f8e9f18190..eb61cfd9452b 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -21,9 +21,10 @@
21#include <linux/io.h> 21#include <linux/io.h>
22#include <linux/platform_data/gpio-omap.h> 22#include <linux/platform_data/gpio-omap.h>
23#include <linux/power/smartreflex.h> 23#include <linux/power/smartreflex.h>
24#include <linux/platform_data/omap_ocp2scp.h>
24#include <linux/i2c-omap.h> 25#include <linux/i2c-omap.h>
25 26
26#include <plat-omap/dma-omap.h> 27#include <linux/omap-dma.h>
27 28
28#include <linux/platform_data/omap_ocp2scp.h> 29#include <linux/platform_data/omap_ocp2scp.h>
29#include <linux/platform_data/spi-omap2-mcspi.h> 30#include <linux/platform_data/spi-omap2-mcspi.h>
diff --git a/arch/arm/mach-omap2/omap_opp_data.h b/arch/arm/mach-omap2/omap_opp_data.h
index 7e437bf6024c..336fdfcf88bb 100644
--- a/arch/arm/mach-omap2/omap_opp_data.h
+++ b/arch/arm/mach-omap2/omap_opp_data.h
@@ -89,8 +89,11 @@ extern struct omap_volt_data omap34xx_vddcore_volt_data[];
89extern struct omap_volt_data omap36xx_vddmpu_volt_data[]; 89extern struct omap_volt_data omap36xx_vddmpu_volt_data[];
90extern struct omap_volt_data omap36xx_vddcore_volt_data[]; 90extern struct omap_volt_data omap36xx_vddcore_volt_data[];
91 91
92extern struct omap_volt_data omap44xx_vdd_mpu_volt_data[]; 92extern struct omap_volt_data omap443x_vdd_mpu_volt_data[];
93extern struct omap_volt_data omap44xx_vdd_iva_volt_data[]; 93extern struct omap_volt_data omap443x_vdd_iva_volt_data[];
94extern struct omap_volt_data omap44xx_vdd_core_volt_data[]; 94extern struct omap_volt_data omap443x_vdd_core_volt_data[];
95extern struct omap_volt_data omap446x_vdd_mpu_volt_data[];
96extern struct omap_volt_data omap446x_vdd_iva_volt_data[];
97extern struct omap_volt_data omap446x_vdd_core_volt_data[];
95 98
96#endif /* __ARCH_ARM_MACH_OMAP2_OMAP_OPP_DATA_H */ 99#endif /* __ARCH_ARM_MACH_OMAP2_OMAP_OPP_DATA_H */
diff --git a/arch/arm/mach-omap2/omap_phy_internal.c b/arch/arm/mach-omap2/omap_phy_internal.c
index 4d76a3ca5bf3..e237602e10ea 100644
--- a/arch/arm/mach-omap2/omap_phy_internal.c
+++ b/arch/arm/mach-omap2/omap_phy_internal.c
@@ -33,6 +33,38 @@
33#include "control.h" 33#include "control.h"
34#include "usb.h" 34#include "usb.h"
35 35
36#define CONTROL_DEV_CONF 0x300
37#define PHY_PD 0x1
38
39/**
40 * omap4430_phy_power_down: disable MUSB PHY during early init
41 *
42 * OMAP4 MUSB PHY module is enabled by default on reset, but this will
43 * prevent core retention if not disabled by SW. USB driver will
44 * later on enable this, once and if the driver needs it.
45 */
46static int __init omap4430_phy_power_down(void)
47{
48 void __iomem *ctrl_base;
49
50 if (!cpu_is_omap44xx())
51 return 0;
52
53 ctrl_base = ioremap(OMAP443X_SCM_BASE, SZ_1K);
54 if (!ctrl_base) {
55 pr_err("control module ioremap failed\n");
56 return -ENOMEM;
57 }
58
59 /* Power down the phy */
60 __raw_writel(PHY_PD, ctrl_base + CONTROL_DEV_CONF);
61
62 iounmap(ctrl_base);
63
64 return 0;
65}
66early_initcall(omap4430_phy_power_down);
67
36void am35x_musb_reset(void) 68void am35x_musb_reset(void)
37{ 69{
38 u32 regval; 70 u32 regval;
diff --git a/arch/arm/mach-omap2/omap_twl.c b/arch/arm/mach-omap2/omap_twl.c
index 2bf35dc091be..fefd40166624 100644
--- a/arch/arm/mach-omap2/omap_twl.c
+++ b/arch/arm/mach-omap2/omap_twl.c
@@ -31,16 +31,6 @@
31#define OMAP3_VP_VSTEPMAX_VSTEPMAX 0x04 31#define OMAP3_VP_VSTEPMAX_VSTEPMAX 0x04
32#define OMAP3_VP_VLIMITTO_TIMEOUT_US 200 32#define OMAP3_VP_VLIMITTO_TIMEOUT_US 200
33 33
34#define OMAP3430_VP1_VLIMITTO_VDDMIN 0x14
35#define OMAP3430_VP1_VLIMITTO_VDDMAX 0x42
36#define OMAP3430_VP2_VLIMITTO_VDDMIN 0x18
37#define OMAP3430_VP2_VLIMITTO_VDDMAX 0x2c
38
39#define OMAP3630_VP1_VLIMITTO_VDDMIN 0x18
40#define OMAP3630_VP1_VLIMITTO_VDDMAX 0x3c
41#define OMAP3630_VP2_VLIMITTO_VDDMIN 0x18
42#define OMAP3630_VP2_VLIMITTO_VDDMAX 0x30
43
44#define OMAP4_SRI2C_SLAVE_ADDR 0x12 34#define OMAP4_SRI2C_SLAVE_ADDR 0x12
45#define OMAP4_VDD_MPU_SR_VOLT_REG 0x55 35#define OMAP4_VDD_MPU_SR_VOLT_REG 0x55
46#define OMAP4_VDD_MPU_SR_CMD_REG 0x56 36#define OMAP4_VDD_MPU_SR_CMD_REG 0x56
@@ -54,13 +44,6 @@
54#define OMAP4_VP_VSTEPMAX_VSTEPMAX 0x04 44#define OMAP4_VP_VSTEPMAX_VSTEPMAX 0x04
55#define OMAP4_VP_VLIMITTO_TIMEOUT_US 200 45#define OMAP4_VP_VLIMITTO_TIMEOUT_US 200
56 46
57#define OMAP4_VP_MPU_VLIMITTO_VDDMIN 0xA
58#define OMAP4_VP_MPU_VLIMITTO_VDDMAX 0x39
59#define OMAP4_VP_IVA_VLIMITTO_VDDMIN 0xA
60#define OMAP4_VP_IVA_VLIMITTO_VDDMAX 0x2D
61#define OMAP4_VP_CORE_VLIMITTO_VDDMIN 0xA
62#define OMAP4_VP_CORE_VLIMITTO_VDDMAX 0x28
63
64static bool is_offset_valid; 47static bool is_offset_valid;
65static u8 smps_offset; 48static u8 smps_offset;
66/* 49/*
@@ -159,16 +142,11 @@ static u8 twl6030_uv_to_vsel(unsigned long uv)
159static struct omap_voltdm_pmic omap3_mpu_pmic = { 142static struct omap_voltdm_pmic omap3_mpu_pmic = {
160 .slew_rate = 4000, 143 .slew_rate = 4000,
161 .step_size = 12500, 144 .step_size = 12500,
162 .on_volt = 1200000,
163 .onlp_volt = 1000000,
164 .ret_volt = 975000,
165 .off_volt = 600000,
166 .volt_setup_time = 0xfff,
167 .vp_erroroffset = OMAP3_VP_CONFIG_ERROROFFSET, 145 .vp_erroroffset = OMAP3_VP_CONFIG_ERROROFFSET,
168 .vp_vstepmin = OMAP3_VP_VSTEPMIN_VSTEPMIN, 146 .vp_vstepmin = OMAP3_VP_VSTEPMIN_VSTEPMIN,
169 .vp_vstepmax = OMAP3_VP_VSTEPMAX_VSTEPMAX, 147 .vp_vstepmax = OMAP3_VP_VSTEPMAX_VSTEPMAX,
170 .vp_vddmin = OMAP3430_VP1_VLIMITTO_VDDMIN, 148 .vddmin = 600000,
171 .vp_vddmax = OMAP3430_VP1_VLIMITTO_VDDMAX, 149 .vddmax = 1450000,
172 .vp_timeout_us = OMAP3_VP_VLIMITTO_TIMEOUT_US, 150 .vp_timeout_us = OMAP3_VP_VLIMITTO_TIMEOUT_US,
173 .i2c_slave_addr = OMAP3_SRI2C_SLAVE_ADDR, 151 .i2c_slave_addr = OMAP3_SRI2C_SLAVE_ADDR,
174 .volt_reg_addr = OMAP3_VDD_MPU_SR_CONTROL_REG, 152 .volt_reg_addr = OMAP3_VDD_MPU_SR_CONTROL_REG,
@@ -180,16 +158,11 @@ static struct omap_voltdm_pmic omap3_mpu_pmic = {
180static struct omap_voltdm_pmic omap3_core_pmic = { 158static struct omap_voltdm_pmic omap3_core_pmic = {
181 .slew_rate = 4000, 159 .slew_rate = 4000,
182 .step_size = 12500, 160 .step_size = 12500,
183 .on_volt = 1200000,
184 .onlp_volt = 1000000,
185 .ret_volt = 975000,
186 .off_volt = 600000,
187 .volt_setup_time = 0xfff,
188 .vp_erroroffset = OMAP3_VP_CONFIG_ERROROFFSET, 161 .vp_erroroffset = OMAP3_VP_CONFIG_ERROROFFSET,
189 .vp_vstepmin = OMAP3_VP_VSTEPMIN_VSTEPMIN, 162 .vp_vstepmin = OMAP3_VP_VSTEPMIN_VSTEPMIN,
190 .vp_vstepmax = OMAP3_VP_VSTEPMAX_VSTEPMAX, 163 .vp_vstepmax = OMAP3_VP_VSTEPMAX_VSTEPMAX,
191 .vp_vddmin = OMAP3430_VP2_VLIMITTO_VDDMIN, 164 .vddmin = 600000,
192 .vp_vddmax = OMAP3430_VP2_VLIMITTO_VDDMAX, 165 .vddmax = 1450000,
193 .vp_timeout_us = OMAP3_VP_VLIMITTO_TIMEOUT_US, 166 .vp_timeout_us = OMAP3_VP_VLIMITTO_TIMEOUT_US,
194 .i2c_slave_addr = OMAP3_SRI2C_SLAVE_ADDR, 167 .i2c_slave_addr = OMAP3_SRI2C_SLAVE_ADDR,
195 .volt_reg_addr = OMAP3_VDD_CORE_SR_CONTROL_REG, 168 .volt_reg_addr = OMAP3_VDD_CORE_SR_CONTROL_REG,
@@ -201,21 +174,17 @@ static struct omap_voltdm_pmic omap3_core_pmic = {
201static struct omap_voltdm_pmic omap4_mpu_pmic = { 174static struct omap_voltdm_pmic omap4_mpu_pmic = {
202 .slew_rate = 4000, 175 .slew_rate = 4000,
203 .step_size = 12660, 176 .step_size = 12660,
204 .on_volt = 1375000,
205 .onlp_volt = 1375000,
206 .ret_volt = 830000,
207 .off_volt = 0,
208 .volt_setup_time = 0,
209 .vp_erroroffset = OMAP4_VP_CONFIG_ERROROFFSET, 177 .vp_erroroffset = OMAP4_VP_CONFIG_ERROROFFSET,
210 .vp_vstepmin = OMAP4_VP_VSTEPMIN_VSTEPMIN, 178 .vp_vstepmin = OMAP4_VP_VSTEPMIN_VSTEPMIN,
211 .vp_vstepmax = OMAP4_VP_VSTEPMAX_VSTEPMAX, 179 .vp_vstepmax = OMAP4_VP_VSTEPMAX_VSTEPMAX,
212 .vp_vddmin = OMAP4_VP_MPU_VLIMITTO_VDDMIN, 180 .vddmin = 0,
213 .vp_vddmax = OMAP4_VP_MPU_VLIMITTO_VDDMAX, 181 .vddmax = 2100000,
214 .vp_timeout_us = OMAP4_VP_VLIMITTO_TIMEOUT_US, 182 .vp_timeout_us = OMAP4_VP_VLIMITTO_TIMEOUT_US,
215 .i2c_slave_addr = OMAP4_SRI2C_SLAVE_ADDR, 183 .i2c_slave_addr = OMAP4_SRI2C_SLAVE_ADDR,
216 .volt_reg_addr = OMAP4_VDD_MPU_SR_VOLT_REG, 184 .volt_reg_addr = OMAP4_VDD_MPU_SR_VOLT_REG,
217 .cmd_reg_addr = OMAP4_VDD_MPU_SR_CMD_REG, 185 .cmd_reg_addr = OMAP4_VDD_MPU_SR_CMD_REG,
218 .i2c_high_speed = true, 186 .i2c_high_speed = true,
187 .i2c_pad_load = 3,
219 .vsel_to_uv = twl6030_vsel_to_uv, 188 .vsel_to_uv = twl6030_vsel_to_uv,
220 .uv_to_vsel = twl6030_uv_to_vsel, 189 .uv_to_vsel = twl6030_uv_to_vsel,
221}; 190};
@@ -223,21 +192,17 @@ static struct omap_voltdm_pmic omap4_mpu_pmic = {
223static struct omap_voltdm_pmic omap4_iva_pmic = { 192static struct omap_voltdm_pmic omap4_iva_pmic = {
224 .slew_rate = 4000, 193 .slew_rate = 4000,
225 .step_size = 12660, 194 .step_size = 12660,
226 .on_volt = 1188000,
227 .onlp_volt = 1188000,
228 .ret_volt = 830000,
229 .off_volt = 0,
230 .volt_setup_time = 0,
231 .vp_erroroffset = OMAP4_VP_CONFIG_ERROROFFSET, 195 .vp_erroroffset = OMAP4_VP_CONFIG_ERROROFFSET,
232 .vp_vstepmin = OMAP4_VP_VSTEPMIN_VSTEPMIN, 196 .vp_vstepmin = OMAP4_VP_VSTEPMIN_VSTEPMIN,
233 .vp_vstepmax = OMAP4_VP_VSTEPMAX_VSTEPMAX, 197 .vp_vstepmax = OMAP4_VP_VSTEPMAX_VSTEPMAX,
234 .vp_vddmin = OMAP4_VP_IVA_VLIMITTO_VDDMIN, 198 .vddmin = 0,
235 .vp_vddmax = OMAP4_VP_IVA_VLIMITTO_VDDMAX, 199 .vddmax = 2100000,
236 .vp_timeout_us = OMAP4_VP_VLIMITTO_TIMEOUT_US, 200 .vp_timeout_us = OMAP4_VP_VLIMITTO_TIMEOUT_US,
237 .i2c_slave_addr = OMAP4_SRI2C_SLAVE_ADDR, 201 .i2c_slave_addr = OMAP4_SRI2C_SLAVE_ADDR,
238 .volt_reg_addr = OMAP4_VDD_IVA_SR_VOLT_REG, 202 .volt_reg_addr = OMAP4_VDD_IVA_SR_VOLT_REG,
239 .cmd_reg_addr = OMAP4_VDD_IVA_SR_CMD_REG, 203 .cmd_reg_addr = OMAP4_VDD_IVA_SR_CMD_REG,
240 .i2c_high_speed = true, 204 .i2c_high_speed = true,
205 .i2c_pad_load = 3,
241 .vsel_to_uv = twl6030_vsel_to_uv, 206 .vsel_to_uv = twl6030_vsel_to_uv,
242 .uv_to_vsel = twl6030_uv_to_vsel, 207 .uv_to_vsel = twl6030_uv_to_vsel,
243}; 208};
@@ -245,20 +210,17 @@ static struct omap_voltdm_pmic omap4_iva_pmic = {
245static struct omap_voltdm_pmic omap4_core_pmic = { 210static struct omap_voltdm_pmic omap4_core_pmic = {
246 .slew_rate = 4000, 211 .slew_rate = 4000,
247 .step_size = 12660, 212 .step_size = 12660,
248 .on_volt = 1200000,
249 .onlp_volt = 1200000,
250 .ret_volt = 830000,
251 .off_volt = 0,
252 .volt_setup_time = 0,
253 .vp_erroroffset = OMAP4_VP_CONFIG_ERROROFFSET, 213 .vp_erroroffset = OMAP4_VP_CONFIG_ERROROFFSET,
254 .vp_vstepmin = OMAP4_VP_VSTEPMIN_VSTEPMIN, 214 .vp_vstepmin = OMAP4_VP_VSTEPMIN_VSTEPMIN,
255 .vp_vstepmax = OMAP4_VP_VSTEPMAX_VSTEPMAX, 215 .vp_vstepmax = OMAP4_VP_VSTEPMAX_VSTEPMAX,
256 .vp_vddmin = OMAP4_VP_CORE_VLIMITTO_VDDMIN, 216 .vddmin = 0,
257 .vp_vddmax = OMAP4_VP_CORE_VLIMITTO_VDDMAX, 217 .vddmax = 2100000,
258 .vp_timeout_us = OMAP4_VP_VLIMITTO_TIMEOUT_US, 218 .vp_timeout_us = OMAP4_VP_VLIMITTO_TIMEOUT_US,
259 .i2c_slave_addr = OMAP4_SRI2C_SLAVE_ADDR, 219 .i2c_slave_addr = OMAP4_SRI2C_SLAVE_ADDR,
260 .volt_reg_addr = OMAP4_VDD_CORE_SR_VOLT_REG, 220 .volt_reg_addr = OMAP4_VDD_CORE_SR_VOLT_REG,
261 .cmd_reg_addr = OMAP4_VDD_CORE_SR_CMD_REG, 221 .cmd_reg_addr = OMAP4_VDD_CORE_SR_CMD_REG,
222 .i2c_high_speed = true,
223 .i2c_pad_load = 3,
262 .vsel_to_uv = twl6030_vsel_to_uv, 224 .vsel_to_uv = twl6030_vsel_to_uv,
263 .uv_to_vsel = twl6030_uv_to_vsel, 225 .uv_to_vsel = twl6030_uv_to_vsel,
264}; 226};
@@ -289,13 +251,6 @@ int __init omap3_twl_init(void)
289 if (!cpu_is_omap34xx()) 251 if (!cpu_is_omap34xx())
290 return -ENODEV; 252 return -ENODEV;
291 253
292 if (cpu_is_omap3630()) {
293 omap3_mpu_pmic.vp_vddmin = OMAP3630_VP1_VLIMITTO_VDDMIN;
294 omap3_mpu_pmic.vp_vddmax = OMAP3630_VP1_VLIMITTO_VDDMAX;
295 omap3_core_pmic.vp_vddmin = OMAP3630_VP2_VLIMITTO_VDDMIN;
296 omap3_core_pmic.vp_vddmax = OMAP3630_VP2_VLIMITTO_VDDMAX;
297 }
298
299 /* 254 /*
300 * The smartreflex bit on twl4030 specifies if the setting of voltage 255 * The smartreflex bit on twl4030 specifies if the setting of voltage
301 * is done over the I2C_SR path. Since this setting is independent of 256 * is done over the I2C_SR path. Since this setting is independent of
diff --git a/arch/arm/mach-omap2/opp4xxx_data.c b/arch/arm/mach-omap2/opp4xxx_data.c
index a9fd6d5fe79e..d470b728e720 100644
--- a/arch/arm/mach-omap2/opp4xxx_data.c
+++ b/arch/arm/mach-omap2/opp4xxx_data.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * OMAP4 OPP table definitions. 2 * OMAP4 OPP table definitions.
3 * 3 *
4 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ 4 * Copyright (C) 2010-2012 Texas Instruments Incorporated - http://www.ti.com/
5 * Nishanth Menon 5 * Nishanth Menon
6 * Kevin Hilman 6 * Kevin Hilman
7 * Thara Gopinath 7 * Thara Gopinath
@@ -35,7 +35,7 @@
35#define OMAP4430_VDD_MPU_OPPTURBO_UV 1313000 35#define OMAP4430_VDD_MPU_OPPTURBO_UV 1313000
36#define OMAP4430_VDD_MPU_OPPNITRO_UV 1375000 36#define OMAP4430_VDD_MPU_OPPNITRO_UV 1375000
37 37
38struct omap_volt_data omap44xx_vdd_mpu_volt_data[] = { 38struct omap_volt_data omap443x_vdd_mpu_volt_data[] = {
39 VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPP50_UV, OMAP44XX_CONTROL_FUSE_MPU_OPP50, 0xf4, 0x0c), 39 VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPP50_UV, OMAP44XX_CONTROL_FUSE_MPU_OPP50, 0xf4, 0x0c),
40 VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPP100_UV, OMAP44XX_CONTROL_FUSE_MPU_OPP100, 0xf9, 0x16), 40 VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPP100_UV, OMAP44XX_CONTROL_FUSE_MPU_OPP100, 0xf9, 0x16),
41 VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPPTURBO_UV, OMAP44XX_CONTROL_FUSE_MPU_OPPTURBO, 0xfa, 0x23), 41 VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPPTURBO_UV, OMAP44XX_CONTROL_FUSE_MPU_OPPTURBO, 0xfa, 0x23),
@@ -47,7 +47,7 @@ struct omap_volt_data omap44xx_vdd_mpu_volt_data[] = {
47#define OMAP4430_VDD_IVA_OPP100_UV 1188000 47#define OMAP4430_VDD_IVA_OPP100_UV 1188000
48#define OMAP4430_VDD_IVA_OPPTURBO_UV 1300000 48#define OMAP4430_VDD_IVA_OPPTURBO_UV 1300000
49 49
50struct omap_volt_data omap44xx_vdd_iva_volt_data[] = { 50struct omap_volt_data omap443x_vdd_iva_volt_data[] = {
51 VOLT_DATA_DEFINE(OMAP4430_VDD_IVA_OPP50_UV, OMAP44XX_CONTROL_FUSE_IVA_OPP50, 0xf4, 0x0c), 51 VOLT_DATA_DEFINE(OMAP4430_VDD_IVA_OPP50_UV, OMAP44XX_CONTROL_FUSE_IVA_OPP50, 0xf4, 0x0c),
52 VOLT_DATA_DEFINE(OMAP4430_VDD_IVA_OPP100_UV, OMAP44XX_CONTROL_FUSE_IVA_OPP100, 0xf9, 0x16), 52 VOLT_DATA_DEFINE(OMAP4430_VDD_IVA_OPP100_UV, OMAP44XX_CONTROL_FUSE_IVA_OPP100, 0xf9, 0x16),
53 VOLT_DATA_DEFINE(OMAP4430_VDD_IVA_OPPTURBO_UV, OMAP44XX_CONTROL_FUSE_IVA_OPPTURBO, 0xfa, 0x23), 53 VOLT_DATA_DEFINE(OMAP4430_VDD_IVA_OPPTURBO_UV, OMAP44XX_CONTROL_FUSE_IVA_OPPTURBO, 0xfa, 0x23),
@@ -57,14 +57,14 @@ struct omap_volt_data omap44xx_vdd_iva_volt_data[] = {
57#define OMAP4430_VDD_CORE_OPP50_UV 1025000 57#define OMAP4430_VDD_CORE_OPP50_UV 1025000
58#define OMAP4430_VDD_CORE_OPP100_UV 1200000 58#define OMAP4430_VDD_CORE_OPP100_UV 1200000
59 59
60struct omap_volt_data omap44xx_vdd_core_volt_data[] = { 60struct omap_volt_data omap443x_vdd_core_volt_data[] = {
61 VOLT_DATA_DEFINE(OMAP4430_VDD_CORE_OPP50_UV, OMAP44XX_CONTROL_FUSE_CORE_OPP50, 0xf4, 0x0c), 61 VOLT_DATA_DEFINE(OMAP4430_VDD_CORE_OPP50_UV, OMAP44XX_CONTROL_FUSE_CORE_OPP50, 0xf4, 0x0c),
62 VOLT_DATA_DEFINE(OMAP4430_VDD_CORE_OPP100_UV, OMAP44XX_CONTROL_FUSE_CORE_OPP100, 0xf9, 0x16), 62 VOLT_DATA_DEFINE(OMAP4430_VDD_CORE_OPP100_UV, OMAP44XX_CONTROL_FUSE_CORE_OPP100, 0xf9, 0x16),
63 VOLT_DATA_DEFINE(0, 0, 0, 0), 63 VOLT_DATA_DEFINE(0, 0, 0, 0),
64}; 64};
65 65
66 66
67static struct omap_opp_def __initdata omap44xx_opp_def_list[] = { 67static struct omap_opp_def __initdata omap443x_opp_def_list[] = {
68 /* MPU OPP1 - OPP50 */ 68 /* MPU OPP1 - OPP50 */
69 OPP_INITIALIZER("mpu", true, 300000000, OMAP4430_VDD_MPU_OPP50_UV), 69 OPP_INITIALIZER("mpu", true, 300000000, OMAP4430_VDD_MPU_OPP50_UV),
70 /* MPU OPP2 - OPP100 */ 70 /* MPU OPP2 - OPP100 */
@@ -86,6 +86,82 @@ static struct omap_opp_def __initdata omap44xx_opp_def_list[] = {
86 /* TODO: add DSP, aess, fdif, gpu */ 86 /* TODO: add DSP, aess, fdif, gpu */
87}; 87};
88 88
89#define OMAP4460_VDD_MPU_OPP50_UV 1025000
90#define OMAP4460_VDD_MPU_OPP100_UV 1200000
91#define OMAP4460_VDD_MPU_OPPTURBO_UV 1313000
92#define OMAP4460_VDD_MPU_OPPNITRO_UV 1375000
93
94struct omap_volt_data omap446x_vdd_mpu_volt_data[] = {
95 VOLT_DATA_DEFINE(OMAP4460_VDD_MPU_OPP50_UV, OMAP44XX_CONTROL_FUSE_MPU_OPP50, 0xf4, 0x0c),
96 VOLT_DATA_DEFINE(OMAP4460_VDD_MPU_OPP100_UV, OMAP44XX_CONTROL_FUSE_MPU_OPP100, 0xf9, 0x16),
97 VOLT_DATA_DEFINE(OMAP4460_VDD_MPU_OPPTURBO_UV, OMAP44XX_CONTROL_FUSE_MPU_OPPTURBO, 0xfa, 0x23),
98 VOLT_DATA_DEFINE(OMAP4460_VDD_MPU_OPPNITRO_UV, OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO, 0xfa, 0x27),
99 VOLT_DATA_DEFINE(0, 0, 0, 0),
100};
101
102#define OMAP4460_VDD_IVA_OPP50_UV 1025000
103#define OMAP4460_VDD_IVA_OPP100_UV 1200000
104#define OMAP4460_VDD_IVA_OPPTURBO_UV 1313000
105#define OMAP4460_VDD_IVA_OPPNITRO_UV 1375000
106
107struct omap_volt_data omap446x_vdd_iva_volt_data[] = {
108 VOLT_DATA_DEFINE(OMAP4460_VDD_IVA_OPP50_UV, OMAP44XX_CONTROL_FUSE_IVA_OPP50, 0xf4, 0x0c),
109 VOLT_DATA_DEFINE(OMAP4460_VDD_IVA_OPP100_UV, OMAP44XX_CONTROL_FUSE_IVA_OPP100, 0xf9, 0x16),
110 VOLT_DATA_DEFINE(OMAP4460_VDD_IVA_OPPTURBO_UV, OMAP44XX_CONTROL_FUSE_IVA_OPPTURBO, 0xfa, 0x23),
111 VOLT_DATA_DEFINE(OMAP4460_VDD_IVA_OPPNITRO_UV, OMAP44XX_CONTROL_FUSE_IVA_OPPNITRO, 0xfa, 0x23),
112 VOLT_DATA_DEFINE(0, 0, 0, 0),
113};
114
115#define OMAP4460_VDD_CORE_OPP50_UV 1025000
116#define OMAP4460_VDD_CORE_OPP100_UV 1200000
117#define OMAP4460_VDD_CORE_OPP100_OV_UV 1250000
118
119struct omap_volt_data omap446x_vdd_core_volt_data[] = {
120 VOLT_DATA_DEFINE(OMAP4460_VDD_CORE_OPP50_UV, OMAP44XX_CONTROL_FUSE_CORE_OPP50, 0xf4, 0x0c),
121 VOLT_DATA_DEFINE(OMAP4460_VDD_CORE_OPP100_UV, OMAP44XX_CONTROL_FUSE_CORE_OPP100, 0xf9, 0x16),
122 VOLT_DATA_DEFINE(OMAP4460_VDD_CORE_OPP100_OV_UV, OMAP44XX_CONTROL_FUSE_CORE_OPP100OV, 0xf9, 0x16),
123 VOLT_DATA_DEFINE(0, 0, 0, 0),
124};
125
126static struct omap_opp_def __initdata omap446x_opp_def_list[] = {
127 /* MPU OPP1 - OPP50 */
128 OPP_INITIALIZER("mpu", true, 350000000, OMAP4460_VDD_MPU_OPP50_UV),
129 /* MPU OPP2 - OPP100 */
130 OPP_INITIALIZER("mpu", true, 700000000, OMAP4460_VDD_MPU_OPP100_UV),
131 /* MPU OPP3 - OPP-Turbo */
132 OPP_INITIALIZER("mpu", true, 920000000, OMAP4460_VDD_MPU_OPPTURBO_UV),
133 /*
134 * MPU OPP4 - OPP-Nitro + Disabled as the reference schematics
135 * recommends TPS623631 - confirm and enable the opp in board file
136 * XXX: May be we should enable these based on mpu capability and
137 * Exception board files disable it...
138 */
139 OPP_INITIALIZER("mpu", false, 1200000000, OMAP4460_VDD_MPU_OPPNITRO_UV),
140 /* MPU OPP4 - OPP-Nitro SpeedBin */
141 OPP_INITIALIZER("mpu", false, 1500000000, OMAP4460_VDD_MPU_OPPNITRO_UV),
142 /* L3 OPP1 - OPP50 */
143 OPP_INITIALIZER("l3_main_1", true, 100000000, OMAP4460_VDD_CORE_OPP50_UV),
144 /* L3 OPP2 - OPP100 */
145 OPP_INITIALIZER("l3_main_1", true, 200000000, OMAP4460_VDD_CORE_OPP100_UV),
146 /* IVA OPP1 - OPP50 */
147 OPP_INITIALIZER("iva", true, 133000000, OMAP4460_VDD_IVA_OPP50_UV),
148 /* IVA OPP2 - OPP100 */
149 OPP_INITIALIZER("iva", true, 266100000, OMAP4460_VDD_IVA_OPP100_UV),
150 /*
151 * IVA OPP3 - OPP-Turbo + Disabled as the reference schematics
152 * recommends Phoenix VCORE2 which can supply only 600mA - so the ones
153 * above this OPP frequency, even though OMAP is capable, should be
154 * enabled by board file which is sure of the chip power capability
155 */
156 OPP_INITIALIZER("iva", false, 332000000, OMAP4460_VDD_IVA_OPPTURBO_UV),
157 /* IVA OPP4 - OPP-Nitro */
158 OPP_INITIALIZER("iva", false, 430000000, OMAP4460_VDD_IVA_OPPNITRO_UV),
159 /* IVA OPP5 - OPP-Nitro SpeedBin*/
160 OPP_INITIALIZER("iva", false, 500000000, OMAP4460_VDD_IVA_OPPNITRO_UV),
161
162 /* TODO: add DSP, aess, fdif, gpu */
163};
164
89/** 165/**
90 * omap4_opp_init() - initialize omap4 opp table 166 * omap4_opp_init() - initialize omap4 opp table
91 */ 167 */
@@ -93,12 +169,12 @@ int __init omap4_opp_init(void)
93{ 169{
94 int r = -ENODEV; 170 int r = -ENODEV;
95 171
96 if (!cpu_is_omap443x()) 172 if (cpu_is_omap443x())
97 return r; 173 r = omap_init_opp_table(omap443x_opp_def_list,
98 174 ARRAY_SIZE(omap443x_opp_def_list));
99 r = omap_init_opp_table(omap44xx_opp_def_list, 175 else if (cpu_is_omap446x())
100 ARRAY_SIZE(omap44xx_opp_def_list)); 176 r = omap_init_opp_table(omap446x_opp_def_list,
101 177 ARRAY_SIZE(omap446x_opp_def_list));
102 return r; 178 return r;
103} 179}
104device_initcall(omap4_opp_init); 180device_initcall(omap4_opp_init);
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 331478f9b864..f4b3143a8b1d 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -40,6 +40,38 @@ static struct omap_device_pm_latency *pm_lats;
40 */ 40 */
41int (*omap_pm_suspend)(void); 41int (*omap_pm_suspend)(void);
42 42
43#ifdef CONFIG_PM
44/**
45 * struct omap2_oscillator - Describe the board main oscillator latencies
46 * @startup_time: oscillator startup latency
47 * @shutdown_time: oscillator shutdown latency
48 */
49struct omap2_oscillator {
50 u32 startup_time;
51 u32 shutdown_time;
52};
53
54static struct omap2_oscillator oscillator = {
55 .startup_time = ULONG_MAX,
56 .shutdown_time = ULONG_MAX,
57};
58
59void omap_pm_setup_oscillator(u32 tstart, u32 tshut)
60{
61 oscillator.startup_time = tstart;
62 oscillator.shutdown_time = tshut;
63}
64
65void omap_pm_get_oscillator(u32 *tstart, u32 *tshut)
66{
67 if (!tstart || !tshut)
68 return;
69
70 *tstart = oscillator.startup_time;
71 *tshut = oscillator.shutdown_time;
72}
73#endif
74
43static int __init _init_omap_device(char *name) 75static int __init _init_omap_device(char *name)
44{ 76{
45 struct omap_hwmod *oh; 77 struct omap_hwmod *oh;
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index fc3c96d5e013..c22503b17abd 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -138,4 +138,14 @@ static inline int omap4_twl_init(void)
138} 138}
139#endif 139#endif
140 140
141#ifdef CONFIG_PM
142extern void omap_pm_setup_oscillator(u32 tstart, u32 tshut);
143extern void omap_pm_get_oscillator(u32 *tstart, u32 *tshut);
144extern void omap_pm_setup_sr_i2c_pcb_length(u32 mm);
145#else
146static inline void omap_pm_setup_oscillator(u32 tstart, u32 tshut) { }
147static inline void omap_pm_get_oscillator(u32 *tstart, u32 *tshut) { *tstart = *tshut = 0; }
148static inline void omap_pm_setup_sr_i2c_pcb_length(u32 mm) { }
149#endif
150
141#endif 151#endif
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index 13e1f4303989..c333fa6dffa8 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -25,7 +25,7 @@
25#include <linux/sysfs.h> 25#include <linux/sysfs.h>
26#include <linux/module.h> 26#include <linux/module.h>
27#include <linux/delay.h> 27#include <linux/delay.h>
28#include <linux/clk.h> 28#include <linux/clk-provider.h>
29#include <linux/irq.h> 29#include <linux/irq.h>
30#include <linux/time.h> 30#include <linux/time.h>
31#include <linux/gpio.h> 31#include <linux/gpio.h>
@@ -38,7 +38,7 @@
38#include <asm/mach-types.h> 38#include <asm/mach-types.h>
39#include <asm/system_misc.h> 39#include <asm/system_misc.h>
40 40
41#include <plat-omap/dma-omap.h> 41#include <linux/omap-dma.h>
42 42
43#include "soc.h" 43#include "soc.h"
44#include "common.h" 44#include "common.h"
@@ -203,7 +203,7 @@ static int omap2_can_sleep(void)
203{ 203{
204 if (omap2_fclks_active()) 204 if (omap2_fclks_active())
205 return 0; 205 return 0;
206 if (osc_ck->usecount > 1) 206 if (__clk_is_enabled(osc_ck))
207 return 0; 207 return 0;
208 if (omap_dma_running()) 208 if (omap_dma_running())
209 return 0; 209 return 0;
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 770320061422..7be3622cfc85 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -28,6 +28,7 @@
28#include <linux/clk.h> 28#include <linux/clk.h>
29#include <linux/delay.h> 29#include <linux/delay.h>
30#include <linux/slab.h> 30#include <linux/slab.h>
31#include <linux/omap-dma.h>
31#include <linux/platform_data/gpio-omap.h> 32#include <linux/platform_data/gpio-omap.h>
32 33
33#include <trace/events/power.h> 34#include <trace/events/power.h>
@@ -38,8 +39,6 @@
38 39
39#include "clockdomain.h" 40#include "clockdomain.h"
40#include "powerdomain.h" 41#include "powerdomain.h"
41#include <plat-omap/dma-omap.h>
42
43#include "soc.h" 42#include "soc.h"
44#include "common.h" 43#include "common.h"
45#include "cm3xxx.h" 44#include "cm3xxx.h"
diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
index 7da75aed1514..aa6fd98f606e 100644
--- a/arch/arm/mach-omap2/pm44xx.c
+++ b/arch/arm/mach-omap2/pm44xx.c
@@ -101,13 +101,6 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
101 if (!strncmp(pwrdm->name, "cpu", 3)) 101 if (!strncmp(pwrdm->name, "cpu", 3))
102 return 0; 102 return 0;
103 103
104 /*
105 * FIXME: Remove this check when core retention is supported
106 * Only MPUSS power domain is added in the list.
107 */
108 if (strcmp(pwrdm->name, "mpu_pwrdm"))
109 return 0;
110
111 pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC); 104 pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
112 if (!pwrst) 105 if (!pwrst)
113 return -ENOMEM; 106 return -ENOMEM;
diff --git a/arch/arm/mach-omap2/prm-regbits-24xx.h b/arch/arm/mach-omap2/prm-regbits-24xx.h
index 638da6dd41c3..91aa5106d637 100644
--- a/arch/arm/mach-omap2/prm-regbits-24xx.h
+++ b/arch/arm/mach-omap2/prm-regbits-24xx.h
@@ -107,12 +107,14 @@
107#define OMAP2420_CLKOUT2_EN_MASK (1 << 15) 107#define OMAP2420_CLKOUT2_EN_MASK (1 << 15)
108#define OMAP2420_CLKOUT2_DIV_SHIFT 11 108#define OMAP2420_CLKOUT2_DIV_SHIFT 11
109#define OMAP2420_CLKOUT2_DIV_MASK (0x7 << 11) 109#define OMAP2420_CLKOUT2_DIV_MASK (0x7 << 11)
110#define OMAP2420_CLKOUT2_DIV_WIDTH 3
110#define OMAP2420_CLKOUT2_SOURCE_SHIFT 8 111#define OMAP2420_CLKOUT2_SOURCE_SHIFT 8
111#define OMAP2420_CLKOUT2_SOURCE_MASK (0x3 << 8) 112#define OMAP2420_CLKOUT2_SOURCE_MASK (0x3 << 8)
112#define OMAP24XX_CLKOUT_EN_SHIFT 7 113#define OMAP24XX_CLKOUT_EN_SHIFT 7
113#define OMAP24XX_CLKOUT_EN_MASK (1 << 7) 114#define OMAP24XX_CLKOUT_EN_MASK (1 << 7)
114#define OMAP24XX_CLKOUT_DIV_SHIFT 3 115#define OMAP24XX_CLKOUT_DIV_SHIFT 3
115#define OMAP24XX_CLKOUT_DIV_MASK (0x7 << 3) 116#define OMAP24XX_CLKOUT_DIV_MASK (0x7 << 3)
117#define OMAP24XX_CLKOUT_DIV_WIDTH 3
116#define OMAP24XX_CLKOUT_SOURCE_SHIFT 0 118#define OMAP24XX_CLKOUT_SOURCE_SHIFT 0
117#define OMAP24XX_CLKOUT_SOURCE_MASK (0x3 << 0) 119#define OMAP24XX_CLKOUT_SOURCE_MASK (0x3 << 0)
118 120
diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h
index 838b594d4e13..b0a2142eeb91 100644
--- a/arch/arm/mach-omap2/prm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/prm-regbits-34xx.h
@@ -384,6 +384,7 @@
384/* PRM_CLKSEL */ 384/* PRM_CLKSEL */
385#define OMAP3430_SYS_CLKIN_SEL_SHIFT 0 385#define OMAP3430_SYS_CLKIN_SEL_SHIFT 0
386#define OMAP3430_SYS_CLKIN_SEL_MASK (0x7 << 0) 386#define OMAP3430_SYS_CLKIN_SEL_MASK (0x7 << 0)
387#define OMAP3430_SYS_CLKIN_SEL_WIDTH 3
387 388
388/* PRM_CLKOUT_CTRL */ 389/* PRM_CLKOUT_CTRL */
389#define OMAP3430_CLKOUT_EN_MASK (1 << 7) 390#define OMAP3430_CLKOUT_EN_MASK (1 << 7)
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
index a1a266ce90da..ac25ae6667cf 100644
--- a/arch/arm/mach-omap2/prm.h
+++ b/arch/arm/mach-omap2/prm.h
@@ -114,16 +114,25 @@ struct prm_reset_src_map {
114 114
115/** 115/**
116 * struct prm_ll_data - fn ptrs to per-SoC PRM function implementations 116 * struct prm_ll_data - fn ptrs to per-SoC PRM function implementations
117 * @read_reset_sources: ptr to the Soc PRM-specific get_reset_source impl 117 * @read_reset_sources: ptr to the SoC PRM-specific get_reset_source impl
118 * @was_any_context_lost_old: ptr to the SoC PRM context loss test fn
119 * @clear_context_loss_flags_old: ptr to the SoC PRM context loss flag clear fn
120 *
121 * XXX @was_any_context_lost_old and @clear_context_loss_flags_old are
122 * deprecated.
118 */ 123 */
119struct prm_ll_data { 124struct prm_ll_data {
120 u32 (*read_reset_sources)(void); 125 u32 (*read_reset_sources)(void);
126 bool (*was_any_context_lost_old)(u8 part, s16 inst, u16 idx);
127 void (*clear_context_loss_flags_old)(u8 part, s16 inst, u16 idx);
121}; 128};
122 129
123extern int prm_register(struct prm_ll_data *pld); 130extern int prm_register(struct prm_ll_data *pld);
124extern int prm_unregister(struct prm_ll_data *pld); 131extern int prm_unregister(struct prm_ll_data *pld);
125 132
126extern u32 prm_read_reset_sources(void); 133extern u32 prm_read_reset_sources(void);
134extern bool prm_was_any_context_lost_old(u8 part, s16 inst, u16 idx);
135extern void prm_clear_context_loss_flags_old(u8 part, s16 inst, u16 idx);
127 136
128#endif 137#endif
129 138
diff --git a/arch/arm/mach-omap2/prm2xxx.c b/arch/arm/mach-omap2/prm2xxx.c
index bf24fc47603b..faeab18696df 100644
--- a/arch/arm/mach-omap2/prm2xxx.c
+++ b/arch/arm/mach-omap2/prm2xxx.c
@@ -118,14 +118,13 @@ static struct prm_ll_data omap2xxx_prm_ll_data = {
118 .read_reset_sources = &omap2xxx_prm_read_reset_sources, 118 .read_reset_sources = &omap2xxx_prm_read_reset_sources,
119}; 119};
120 120
121static int __init omap2xxx_prm_init(void) 121int __init omap2xxx_prm_init(void)
122{ 122{
123 if (!cpu_is_omap24xx()) 123 if (!cpu_is_omap24xx())
124 return 0; 124 return 0;
125 125
126 return prm_register(&omap2xxx_prm_ll_data); 126 return prm_register(&omap2xxx_prm_ll_data);
127} 127}
128subsys_initcall(omap2xxx_prm_init);
129 128
130static void __exit omap2xxx_prm_exit(void) 129static void __exit omap2xxx_prm_exit(void)
131{ 130{
diff --git a/arch/arm/mach-omap2/prm2xxx.h b/arch/arm/mach-omap2/prm2xxx.h
index fe8a14f190ab..3194dd87e0e4 100644
--- a/arch/arm/mach-omap2/prm2xxx.h
+++ b/arch/arm/mach-omap2/prm2xxx.h
@@ -126,8 +126,7 @@ extern int omap2xxx_clkdm_wakeup(struct clockdomain *clkdm);
126 126
127extern void omap2xxx_prm_dpll_reset(void); 127extern void omap2xxx_prm_dpll_reset(void);
128 128
129extern int __init prm2xxx_init(void); 129extern int __init omap2xxx_prm_init(void);
130extern int __exit prm2xxx_exit(void);
131 130
132#endif 131#endif
133 132
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.h b/arch/arm/mach-omap2/prm2xxx_3xxx.h
index 78532d6fecd7..9624b40836d4 100644
--- a/arch/arm/mach-omap2/prm2xxx_3xxx.h
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.h
@@ -152,6 +152,7 @@ extern int omap2_clkdm_clear_all_wkdeps(struct clockdomain *clkdm);
152/* Named PRCM_CLKSRC_CTRL on the 24XX */ 152/* Named PRCM_CLKSRC_CTRL on the 24XX */
153#define OMAP_SYSCLKDIV_SHIFT 6 153#define OMAP_SYSCLKDIV_SHIFT 6
154#define OMAP_SYSCLKDIV_MASK (0x3 << 6) 154#define OMAP_SYSCLKDIV_MASK (0x3 << 6)
155#define OMAP_SYSCLKDIV_WIDTH 2
155#define OMAP_AUTOEXTCLKMODE_SHIFT 3 156#define OMAP_AUTOEXTCLKMODE_SHIFT 3
156#define OMAP_AUTOEXTCLKMODE_MASK (0x3 << 3) 157#define OMAP_AUTOEXTCLKMODE_MASK (0x3 << 3)
157#define OMAP_SYSCLKSEL_SHIFT 0 158#define OMAP_SYSCLKSEL_SHIFT 0
diff --git a/arch/arm/mach-omap2/prm3xxx.c b/arch/arm/mach-omap2/prm3xxx.c
index b86116cf0db9..db198d058584 100644
--- a/arch/arm/mach-omap2/prm3xxx.c
+++ b/arch/arm/mach-omap2/prm3xxx.c
@@ -383,27 +383,30 @@ static struct prm_ll_data omap3xxx_prm_ll_data = {
383 .read_reset_sources = &omap3xxx_prm_read_reset_sources, 383 .read_reset_sources = &omap3xxx_prm_read_reset_sources,
384}; 384};
385 385
386static int __init omap3xxx_prm_init(void) 386int __init omap3xxx_prm_init(void)
387{
388 if (!cpu_is_omap34xx())
389 return 0;
390
391 return prm_register(&omap3xxx_prm_ll_data);
392}
393
394static int __init omap3xxx_prm_late_init(void)
387{ 395{
388 int ret; 396 int ret;
389 397
390 if (!cpu_is_omap34xx()) 398 if (!cpu_is_omap34xx())
391 return 0; 399 return 0;
392 400
393 ret = prm_register(&omap3xxx_prm_ll_data);
394 if (ret)
395 return ret;
396
397 omap3xxx_prm_enable_io_wakeup(); 401 omap3xxx_prm_enable_io_wakeup();
398 ret = omap_prcm_register_chain_handler(&omap3_prcm_irq_setup); 402 ret = omap_prcm_register_chain_handler(&omap3_prcm_irq_setup);
399 if (!ret) 403 if (!ret)
400 irq_set_status_flags(omap_prcm_event_to_irq("io"), 404 irq_set_status_flags(omap_prcm_event_to_irq("io"),
401 IRQ_NOAUTOEN); 405 IRQ_NOAUTOEN);
402 406
403
404 return ret; 407 return ret;
405} 408}
406subsys_initcall(omap3xxx_prm_init); 409subsys_initcall(omap3xxx_prm_late_init);
407 410
408static void __exit omap3xxx_prm_exit(void) 411static void __exit omap3xxx_prm_exit(void)
409{ 412{
diff --git a/arch/arm/mach-omap2/prm3xxx.h b/arch/arm/mach-omap2/prm3xxx.h
index 10cd41a8129e..277f71794e61 100644
--- a/arch/arm/mach-omap2/prm3xxx.h
+++ b/arch/arm/mach-omap2/prm3xxx.h
@@ -154,6 +154,7 @@ extern void omap3xxx_prm_restore_irqen(u32 *saved_mask);
154 154
155extern void omap3xxx_prm_dpll3_reset(void); 155extern void omap3xxx_prm_dpll3_reset(void);
156 156
157extern int __init omap3xxx_prm_init(void);
157extern u32 omap3xxx_prm_get_reset_sources(void); 158extern u32 omap3xxx_prm_get_reset_sources(void);
158 159
159#endif /* __ASSEMBLER */ 160#endif /* __ASSEMBLER */
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index 6d3467af205d..7498bc77fe8b 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -346,6 +346,37 @@ static u32 omap44xx_prm_read_reset_sources(void)
346 return r; 346 return r;
347} 347}
348 348
349/**
350 * omap44xx_prm_was_any_context_lost_old - was module hardware context lost?
351 * @part: PRM partition ID (e.g., OMAP4430_PRM_PARTITION)
352 * @inst: PRM instance offset (e.g., OMAP4430_PRM_MPU_INST)
353 * @idx: CONTEXT register offset
354 *
355 * Return 1 if any bits were set in the *_CONTEXT_* register
356 * identified by (@part, @inst, @idx), which means that some context
357 * was lost for that module; otherwise, return 0.
358 */
359static bool omap44xx_prm_was_any_context_lost_old(u8 part, s16 inst, u16 idx)
360{
361 return (omap4_prminst_read_inst_reg(part, inst, idx)) ? 1 : 0;
362}
363
364/**
365 * omap44xx_prm_clear_context_lost_flags_old - clear context loss flags
366 * @part: PRM partition ID (e.g., OMAP4430_PRM_PARTITION)
367 * @inst: PRM instance offset (e.g., OMAP4430_PRM_MPU_INST)
368 * @idx: CONTEXT register offset
369 *
370 * Clear hardware context loss bits for the module identified by
371 * (@part, @inst, @idx). No return value. XXX Writes to reserved bits;
372 * is there a way to avoid this?
373 */
374static void omap44xx_prm_clear_context_loss_flags_old(u8 part, s16 inst,
375 u16 idx)
376{
377 omap4_prminst_write_inst_reg(0xffffffff, part, inst, idx);
378}
379
349/* Powerdomain low-level functions */ 380/* Powerdomain low-level functions */
350 381
351static int omap4_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) 382static int omap4_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
@@ -613,24 +644,28 @@ struct pwrdm_ops omap4_pwrdm_operations = {
613 */ 644 */
614static struct prm_ll_data omap44xx_prm_ll_data = { 645static struct prm_ll_data omap44xx_prm_ll_data = {
615 .read_reset_sources = &omap44xx_prm_read_reset_sources, 646 .read_reset_sources = &omap44xx_prm_read_reset_sources,
647 .was_any_context_lost_old = &omap44xx_prm_was_any_context_lost_old,
648 .clear_context_loss_flags_old = &omap44xx_prm_clear_context_loss_flags_old,
616}; 649};
617 650
618static int __init omap44xx_prm_init(void) 651int __init omap44xx_prm_init(void)
619{ 652{
620 int ret;
621
622 if (!cpu_is_omap44xx()) 653 if (!cpu_is_omap44xx())
623 return 0; 654 return 0;
624 655
625 ret = prm_register(&omap44xx_prm_ll_data); 656 return prm_register(&omap44xx_prm_ll_data);
626 if (ret) 657}
627 return ret; 658
659static int __init omap44xx_prm_late_init(void)
660{
661 if (!cpu_is_omap44xx())
662 return 0;
628 663
629 omap44xx_prm_enable_io_wakeup(); 664 omap44xx_prm_enable_io_wakeup();
630 665
631 return omap_prcm_register_chain_handler(&omap4_prcm_irq_setup); 666 return omap_prcm_register_chain_handler(&omap4_prcm_irq_setup);
632} 667}
633subsys_initcall(omap44xx_prm_init); 668subsys_initcall(omap44xx_prm_late_init);
634 669
635static void __exit omap44xx_prm_exit(void) 670static void __exit omap44xx_prm_exit(void)
636{ 671{
diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h
index c8e1accdc90e..22b0979206ca 100644
--- a/arch/arm/mach-omap2/prm44xx.h
+++ b/arch/arm/mach-omap2/prm44xx.h
@@ -771,6 +771,7 @@ extern void omap44xx_prm_ocp_barrier(void);
771extern void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask); 771extern void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask);
772extern void omap44xx_prm_restore_irqen(u32 *saved_mask); 772extern void omap44xx_prm_restore_irqen(u32 *saved_mask);
773 773
774extern int __init omap44xx_prm_init(void);
774extern u32 omap44xx_prm_get_reset_sources(void); 775extern u32 omap44xx_prm_get_reset_sources(void);
775 776
776# endif 777# endif
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index f596e1e91ffd..228b850e632f 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -365,6 +365,51 @@ u32 prm_read_reset_sources(void)
365} 365}
366 366
367/** 367/**
368 * prm_was_any_context_lost_old - was device context lost? (old API)
369 * @part: PRM partition ID (e.g., OMAP4430_PRM_PARTITION)
370 * @inst: PRM instance offset (e.g., OMAP4430_PRM_MPU_INST)
371 * @idx: CONTEXT register offset
372 *
373 * Return 1 if any bits were set in the *_CONTEXT_* register
374 * identified by (@part, @inst, @idx), which means that some context
375 * was lost for that module; otherwise, return 0. XXX Deprecated;
376 * callers need to use a less-SoC-dependent way to identify hardware
377 * IP blocks.
378 */
379bool prm_was_any_context_lost_old(u8 part, s16 inst, u16 idx)
380{
381 bool ret = true;
382
383 if (prm_ll_data->was_any_context_lost_old)
384 ret = prm_ll_data->was_any_context_lost_old(part, inst, idx);
385 else
386 WARN_ONCE(1, "prm: %s: no mapping function defined\n",
387 __func__);
388
389 return ret;
390}
391
392/**
393 * prm_clear_context_lost_flags_old - clear context loss flags (old API)
394 * @part: PRM partition ID (e.g., OMAP4430_PRM_PARTITION)
395 * @inst: PRM instance offset (e.g., OMAP4430_PRM_MPU_INST)
396 * @idx: CONTEXT register offset
397 *
398 * Clear hardware context loss bits for the module identified by
399 * (@part, @inst, @idx). No return value. XXX Deprecated; callers
400 * need to use a less-SoC-dependent way to identify hardware IP
401 * blocks.
402 */
403void prm_clear_context_loss_flags_old(u8 part, s16 inst, u16 idx)
404{
405 if (prm_ll_data->clear_context_loss_flags_old)
406 prm_ll_data->clear_context_loss_flags_old(part, inst, idx);
407 else
408 WARN_ONCE(1, "prm: %s: no mapping function defined\n",
409 __func__);
410}
411
412/**
368 * prm_register - register per-SoC low-level data with the PRM 413 * prm_register - register per-SoC low-level data with the PRM
369 * @pld: low-level per-SoC OMAP PRM data & function pointers to register 414 * @pld: low-level per-SoC OMAP PRM data & function pointers to register
370 * 415 *
diff --git a/arch/arm/mach-omap2/scrm44xx.h b/arch/arm/mach-omap2/scrm44xx.h
index 701bf2d32949..e897ac89a3fd 100644
--- a/arch/arm/mach-omap2/scrm44xx.h
+++ b/arch/arm/mach-omap2/scrm44xx.h
@@ -127,12 +127,14 @@
127/* AUXCLKREQ0 */ 127/* AUXCLKREQ0 */
128#define OMAP4_MAPPING_SHIFT 2 128#define OMAP4_MAPPING_SHIFT 2
129#define OMAP4_MAPPING_MASK (0x7 << 2) 129#define OMAP4_MAPPING_MASK (0x7 << 2)
130#define OMAP4_MAPPING_WIDTH 3
130#define OMAP4_ACCURACY_SHIFT 1 131#define OMAP4_ACCURACY_SHIFT 1
131#define OMAP4_ACCURACY_MASK (1 << 1) 132#define OMAP4_ACCURACY_MASK (1 << 1)
132 133
133/* AUXCLK0 */ 134/* AUXCLK0 */
134#define OMAP4_CLKDIV_SHIFT 16 135#define OMAP4_CLKDIV_SHIFT 16
135#define OMAP4_CLKDIV_MASK (0xf << 16) 136#define OMAP4_CLKDIV_MASK (0xf << 16)
137#define OMAP4_CLKDIV_WIDTH 4
136#define OMAP4_DISABLECLK_SHIFT 9 138#define OMAP4_DISABLECLK_SHIFT 9
137#define OMAP4_DISABLECLK_MASK (1 << 9) 139#define OMAP4_DISABLECLK_MASK (1 << 9)
138#define OMAP4_ENABLE_SHIFT 8 140#define OMAP4_ENABLE_SHIFT 8
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index aa30a3c20883..93d102535c85 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -26,9 +26,9 @@
26#include <linux/slab.h> 26#include <linux/slab.h>
27#include <linux/pm_runtime.h> 27#include <linux/pm_runtime.h>
28#include <linux/console.h> 28#include <linux/console.h>
29#include <linux/omap-dma.h>
29 30
30#include <plat/omap-serial.h> 31#include <plat/omap-serial.h>
31#include <plat-omap/dma-omap.h>
32 32
33#include "common.h" 33#include "common.h"
34#include "omap_hwmod.h" 34#include "omap_hwmod.h"
diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c
index b0e77a407047..b9753fe27232 100644
--- a/arch/arm/mach-omap2/sr_device.c
+++ b/arch/arm/mach-omap2/sr_device.c
@@ -121,6 +121,19 @@ static int __init sr_dev_init(struct omap_hwmod *oh, void *user)
121 sr_data->senn_mod = 0x1; 121 sr_data->senn_mod = 0x1;
122 sr_data->senp_mod = 0x1; 122 sr_data->senp_mod = 0x1;
123 123
124 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
125 sr_data->err_weight = OMAP3430_SR_ERRWEIGHT;
126 sr_data->err_maxlimit = OMAP3430_SR_ERRMAXLIMIT;
127 sr_data->accum_data = OMAP3430_SR_ACCUMDATA;
128 if (!(strcmp(sr_data->name, "smartreflex_mpu"))) {
129 sr_data->senn_avgweight = OMAP3430_SR1_SENNAVGWEIGHT;
130 sr_data->senp_avgweight = OMAP3430_SR1_SENPAVGWEIGHT;
131 } else {
132 sr_data->senn_avgweight = OMAP3430_SR2_SENNAVGWEIGHT;
133 sr_data->senp_avgweight = OMAP3430_SR2_SENPAVGWEIGHT;
134 }
135 }
136
124 sr_data->voltdm = voltdm_lookup(sr_dev_attr->sensor_voltdm_name); 137 sr_data->voltdm = voltdm_lookup(sr_dev_attr->sensor_voltdm_name);
125 if (!sr_data->voltdm) { 138 if (!sr_data->voltdm) {
126 pr_err("%s: Unable to get voltage domain pointer for VDD %s\n", 139 pr_err("%s: Unable to get voltage domain pointer for VDD %s\n",
diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c
index 75878c37959b..49ac7977e03e 100644
--- a/arch/arm/mach-omap2/vc.c
+++ b/arch/arm/mach-omap2/vc.c
@@ -11,13 +11,20 @@
11#include <linux/delay.h> 11#include <linux/delay.h>
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/bug.h> 13#include <linux/bug.h>
14#include <linux/io.h>
14 15
16#include <asm/div64.h>
17
18#include "iomap.h"
15#include "soc.h" 19#include "soc.h"
16#include "voltage.h" 20#include "voltage.h"
17#include "vc.h" 21#include "vc.h"
18#include "prm-regbits-34xx.h" 22#include "prm-regbits-34xx.h"
19#include "prm-regbits-44xx.h" 23#include "prm-regbits-44xx.h"
20#include "prm44xx.h" 24#include "prm44xx.h"
25#include "pm.h"
26#include "scrm44xx.h"
27#include "control.h"
21 28
22/** 29/**
23 * struct omap_vc_channel_cfg - describe the cfg_channel bitfield 30 * struct omap_vc_channel_cfg - describe the cfg_channel bitfield
@@ -63,6 +70,9 @@ static struct omap_vc_channel_cfg vc_mutant_channel_cfg = {
63}; 70};
64 71
65static struct omap_vc_channel_cfg *vc_cfg_bits; 72static struct omap_vc_channel_cfg *vc_cfg_bits;
73
74/* Default I2C trace length on pcb, 6.3cm. Used for capacitance calculations. */
75static u32 sr_i2c_pcb_length = 63;
66#define CFG_CHANNEL_MASK 0x1f 76#define CFG_CHANNEL_MASK 0x1f
67 77
68/** 78/**
@@ -135,6 +145,8 @@ int omap_vc_pre_scale(struct voltagedomain *voltdm,
135 vc_cmdval |= (*target_vsel << vc->common->cmd_on_shift); 145 vc_cmdval |= (*target_vsel << vc->common->cmd_on_shift);
136 voltdm->write(vc_cmdval, vc->cmdval_reg); 146 voltdm->write(vc_cmdval, vc->cmdval_reg);
137 147
148 voltdm->vc_param->on = target_volt;
149
138 omap_vp_update_errorgain(voltdm, target_volt); 150 omap_vp_update_errorgain(voltdm, target_volt);
139 151
140 return 0; 152 return 0;
@@ -202,46 +214,389 @@ int omap_vc_bypass_scale(struct voltagedomain *voltdm,
202 return 0; 214 return 0;
203} 215}
204 216
205static void __init omap3_vfsm_init(struct voltagedomain *voltdm) 217/* Convert microsecond value to number of 32kHz clock cycles */
218static inline u32 omap_usec_to_32k(u32 usec)
219{
220 return DIV_ROUND_UP_ULL(32768ULL * (u64)usec, 1000000ULL);
221}
222
223/* Set oscillator setup time for omap3 */
224static void omap3_set_clksetup(u32 usec, struct voltagedomain *voltdm)
225{
226 voltdm->write(omap_usec_to_32k(usec), OMAP3_PRM_CLKSETUP_OFFSET);
227}
228
229/**
230 * omap3_set_i2c_timings - sets i2c sleep timings for a channel
231 * @voltdm: channel to configure
232 * @off_mode: select whether retention or off mode values used
233 *
234 * Calculates and sets up voltage controller to use I2C based
235 * voltage scaling for sleep modes. This can be used for either off mode
236 * or retention. Off mode has additionally an option to use sys_off_mode
237 * pad, which uses a global signal to program the whole power IC to
238 * off-mode.
239 */
240static void omap3_set_i2c_timings(struct voltagedomain *voltdm, bool off_mode)
206{ 241{
242 unsigned long voltsetup1;
243 u32 tgt_volt;
244
245 /*
246 * Oscillator is shut down only if we are using sys_off_mode pad,
247 * thus we set a minimal setup time here
248 */
249 omap3_set_clksetup(1, voltdm);
250
251 if (off_mode)
252 tgt_volt = voltdm->vc_param->off;
253 else
254 tgt_volt = voltdm->vc_param->ret;
255
256 voltsetup1 = (voltdm->vc_param->on - tgt_volt) /
257 voltdm->pmic->slew_rate;
258
259 voltsetup1 = voltsetup1 * voltdm->sys_clk.rate / 8 / 1000000 + 1;
260
261 voltdm->rmw(voltdm->vfsm->voltsetup_mask,
262 voltsetup1 << __ffs(voltdm->vfsm->voltsetup_mask),
263 voltdm->vfsm->voltsetup_reg);
264
207 /* 265 /*
208 * Voltage Manager FSM parameters init 266 * pmic is not controlling the voltage scaling during retention,
209 * XXX This data should be passed in from the board file 267 * thus set voltsetup2 to 0
210 */ 268 */
211 voltdm->write(OMAP3_CLKSETUP, OMAP3_PRM_CLKSETUP_OFFSET); 269 voltdm->write(0, OMAP3_PRM_VOLTSETUP2_OFFSET);
212 voltdm->write(OMAP3_VOLTOFFSET, OMAP3_PRM_VOLTOFFSET_OFFSET);
213 voltdm->write(OMAP3_VOLTSETUP2, OMAP3_PRM_VOLTSETUP2_OFFSET);
214} 270}
215 271
216static void __init omap3_vc_init_channel(struct voltagedomain *voltdm) 272/**
273 * omap3_set_off_timings - sets off-mode timings for a channel
274 * @voltdm: channel to configure
275 *
276 * Calculates and sets up off-mode timings for a channel. Off-mode
277 * can use either I2C based voltage scaling, or alternatively
278 * sys_off_mode pad can be used to send a global command to power IC.
279 * This function first checks which mode is being used, and calls
280 * omap3_set_i2c_timings() if the system is using I2C control mode.
281 * sys_off_mode has the additional benefit that voltages can be
282 * scaled to zero volt level with TWL4030 / TWL5030, I2C can only
283 * scale to 600mV.
284 */
285static void omap3_set_off_timings(struct voltagedomain *voltdm)
217{ 286{
218 static bool is_initialized; 287 unsigned long clksetup;
288 unsigned long voltsetup2;
289 unsigned long voltsetup2_old;
290 u32 val;
291 u32 tstart, tshut;
219 292
220 if (is_initialized) 293 /* check if sys_off_mode is used to control off-mode voltages */
294 val = voltdm->read(OMAP3_PRM_VOLTCTRL_OFFSET);
295 if (!(val & OMAP3430_SEL_OFF_MASK)) {
296 /* No, omap is controlling them over I2C */
297 omap3_set_i2c_timings(voltdm, true);
221 return; 298 return;
299 }
300
301 omap_pm_get_oscillator(&tstart, &tshut);
302 omap3_set_clksetup(tstart, voltdm);
303
304 clksetup = voltdm->read(OMAP3_PRM_CLKSETUP_OFFSET);
305
306 /* voltsetup 2 in us */
307 voltsetup2 = voltdm->vc_param->on / voltdm->pmic->slew_rate;
308
309 /* convert to 32k clk cycles */
310 voltsetup2 = DIV_ROUND_UP(voltsetup2 * 32768, 1000000);
311
312 voltsetup2_old = voltdm->read(OMAP3_PRM_VOLTSETUP2_OFFSET);
313
314 /*
315 * Update voltsetup2 if higher than current value (needed because
316 * we have multiple channels with different ramp times), also
317 * update voltoffset always to value recommended by TRM
318 */
319 if (voltsetup2 > voltsetup2_old) {
320 voltdm->write(voltsetup2, OMAP3_PRM_VOLTSETUP2_OFFSET);
321 voltdm->write(clksetup - voltsetup2,
322 OMAP3_PRM_VOLTOFFSET_OFFSET);
323 } else
324 voltdm->write(clksetup - voltsetup2_old,
325 OMAP3_PRM_VOLTOFFSET_OFFSET);
326
327 /*
328 * omap is not controlling voltage scaling during off-mode,
329 * thus set voltsetup1 to 0
330 */
331 voltdm->rmw(voltdm->vfsm->voltsetup_mask, 0,
332 voltdm->vfsm->voltsetup_reg);
333
334 /* voltoffset must be clksetup minus voltsetup2 according to TRM */
335 voltdm->write(clksetup - voltsetup2, OMAP3_PRM_VOLTOFFSET_OFFSET);
336}
337
338static void __init omap3_vc_init_channel(struct voltagedomain *voltdm)
339{
340 omap3_set_off_timings(voltdm);
341}
342
343/**
344 * omap4_calc_volt_ramp - calculates voltage ramping delays on omap4
345 * @voltdm: channel to calculate values for
346 * @voltage_diff: voltage difference in microvolts
347 *
348 * Calculates voltage ramp prescaler + counter values for a voltage
349 * difference on omap4. Returns a field value suitable for writing to
350 * VOLTSETUP register for a channel in following format:
351 * bits[8:9] prescaler ... bits[0:5] counter. See OMAP4 TRM for reference.
352 */
353static u32 omap4_calc_volt_ramp(struct voltagedomain *voltdm, u32 voltage_diff)
354{
355 u32 prescaler;
356 u32 cycles;
357 u32 time;
358
359 time = voltage_diff / voltdm->pmic->slew_rate;
360
361 cycles = voltdm->sys_clk.rate / 1000 * time / 1000;
362
363 cycles /= 64;
364 prescaler = 0;
365
366 /* shift to next prescaler until no overflow */
367
368 /* scale for div 256 = 64 * 4 */
369 if (cycles > 63) {
370 cycles /= 4;
371 prescaler++;
372 }
373
374 /* scale for div 512 = 256 * 2 */
375 if (cycles > 63) {
376 cycles /= 2;
377 prescaler++;
378 }
379
380 /* scale for div 2048 = 512 * 4 */
381 if (cycles > 63) {
382 cycles /= 4;
383 prescaler++;
384 }
385
386 /* check for overflow => invalid ramp time */
387 if (cycles > 63) {
388 pr_warn("%s: invalid setuptime for vdd_%s\n", __func__,
389 voltdm->name);
390 return 0;
391 }
392
393 cycles++;
222 394
223 omap3_vfsm_init(voltdm); 395 return (prescaler << OMAP4430_RAMP_UP_PRESCAL_SHIFT) |
396 (cycles << OMAP4430_RAMP_UP_COUNT_SHIFT);
397}
398
399/**
400 * omap4_usec_to_val_scrm - convert microsecond value to SCRM module bitfield
401 * @usec: microseconds
402 * @shift: number of bits to shift left
403 * @mask: bitfield mask
404 *
405 * Converts microsecond value to OMAP4 SCRM bitfield. Bitfield is
406 * shifted to requested position, and checked agains the mask value.
407 * If larger, forced to the max value of the field (i.e. the mask itself.)
408 * Returns the SCRM bitfield value.
409 */
410static u32 omap4_usec_to_val_scrm(u32 usec, int shift, u32 mask)
411{
412 u32 val;
413
414 val = omap_usec_to_32k(usec) << shift;
224 415
225 is_initialized = true; 416 /* Check for overflow, if yes, force to max value */
417 if (val > mask)
418 val = mask;
419
420 return val;
226} 421}
227 422
423/**
424 * omap4_set_timings - set voltage ramp timings for a channel
425 * @voltdm: channel to configure
426 * @off_mode: whether off-mode values are used
427 *
428 * Calculates and sets the voltage ramp up / down values for a channel.
429 */
430static void omap4_set_timings(struct voltagedomain *voltdm, bool off_mode)
431{
432 u32 val;
433 u32 ramp;
434 int offset;
435 u32 tstart, tshut;
436
437 if (off_mode) {
438 ramp = omap4_calc_volt_ramp(voltdm,
439 voltdm->vc_param->on - voltdm->vc_param->off);
440 offset = voltdm->vfsm->voltsetup_off_reg;
441 } else {
442 ramp = omap4_calc_volt_ramp(voltdm,
443 voltdm->vc_param->on - voltdm->vc_param->ret);
444 offset = voltdm->vfsm->voltsetup_reg;
445 }
446
447 if (!ramp)
448 return;
449
450 val = voltdm->read(offset);
451
452 val |= ramp << OMAP4430_RAMP_DOWN_COUNT_SHIFT;
453
454 val |= ramp << OMAP4430_RAMP_UP_COUNT_SHIFT;
455
456 voltdm->write(val, offset);
457
458 omap_pm_get_oscillator(&tstart, &tshut);
459
460 val = omap4_usec_to_val_scrm(tstart, OMAP4_SETUPTIME_SHIFT,
461 OMAP4_SETUPTIME_MASK);
462 val |= omap4_usec_to_val_scrm(tshut, OMAP4_DOWNTIME_SHIFT,
463 OMAP4_DOWNTIME_MASK);
464
465 __raw_writel(val, OMAP4_SCRM_CLKSETUPTIME);
466}
228 467
229/* OMAP4 specific voltage init functions */ 468/* OMAP4 specific voltage init functions */
230static void __init omap4_vc_init_channel(struct voltagedomain *voltdm) 469static void __init omap4_vc_init_channel(struct voltagedomain *voltdm)
231{ 470{
232 static bool is_initialized; 471 omap4_set_timings(voltdm, true);
233 u32 vc_val; 472 omap4_set_timings(voltdm, false);
473}
474
475struct i2c_init_data {
476 u8 loadbits;
477 u8 load;
478 u8 hsscll_38_4;
479 u8 hsscll_26;
480 u8 hsscll_19_2;
481 u8 hsscll_16_8;
482 u8 hsscll_12;
483};
234 484
235 if (is_initialized) 485static const __initdata struct i2c_init_data omap4_i2c_timing_data[] = {
486 {
487 .load = 50,
488 .loadbits = 0x3,
489 .hsscll_38_4 = 13,
490 .hsscll_26 = 11,
491 .hsscll_19_2 = 9,
492 .hsscll_16_8 = 9,
493 .hsscll_12 = 8,
494 },
495 {
496 .load = 25,
497 .loadbits = 0x2,
498 .hsscll_38_4 = 13,
499 .hsscll_26 = 11,
500 .hsscll_19_2 = 9,
501 .hsscll_16_8 = 9,
502 .hsscll_12 = 8,
503 },
504 {
505 .load = 12,
506 .loadbits = 0x1,
507 .hsscll_38_4 = 11,
508 .hsscll_26 = 10,
509 .hsscll_19_2 = 9,
510 .hsscll_16_8 = 9,
511 .hsscll_12 = 8,
512 },
513 {
514 .load = 0,
515 .loadbits = 0x0,
516 .hsscll_38_4 = 12,
517 .hsscll_26 = 10,
518 .hsscll_19_2 = 9,
519 .hsscll_16_8 = 8,
520 .hsscll_12 = 8,
521 },
522};
523
524/**
525 * omap4_vc_i2c_timing_init - sets up board I2C timing parameters
526 * @voltdm: voltagedomain pointer to get data from
527 *
528 * Use PMIC + board supplied settings for calculating the total I2C
529 * channel capacitance and set the timing parameters based on this.
530 * Pre-calculated values are provided in data tables, as it is not
531 * too straightforward to calculate these runtime.
532 */
533static void __init omap4_vc_i2c_timing_init(struct voltagedomain *voltdm)
534{
535 u32 capacitance;
536 u32 val;
537 u16 hsscll;
538 const struct i2c_init_data *i2c_data;
539
540 if (!voltdm->pmic->i2c_high_speed) {
541 pr_warn("%s: only high speed supported!\n", __func__);
236 return; 542 return;
543 }
544
545 /* PCB trace capacitance, 0.125pF / mm => mm / 8 */
546 capacitance = DIV_ROUND_UP(sr_i2c_pcb_length, 8);
547
548 /* OMAP pad capacitance */
549 capacitance += 4;
550
551 /* PMIC pad capacitance */
552 capacitance += voltdm->pmic->i2c_pad_load;
553
554 /* Search for capacitance match in the table */
555 i2c_data = omap4_i2c_timing_data;
556
557 while (i2c_data->load > capacitance)
558 i2c_data++;
559
560 /* Select proper values based on sysclk frequency */
561 switch (voltdm->sys_clk.rate) {
562 case 38400000:
563 hsscll = i2c_data->hsscll_38_4;
564 break;
565 case 26000000:
566 hsscll = i2c_data->hsscll_26;
567 break;
568 case 19200000:
569 hsscll = i2c_data->hsscll_19_2;
570 break;
571 case 16800000:
572 hsscll = i2c_data->hsscll_16_8;
573 break;
574 case 12000000:
575 hsscll = i2c_data->hsscll_12;
576 break;
577 default:
578 pr_warn("%s: unsupported sysclk rate: %d!\n", __func__,
579 voltdm->sys_clk.rate);
580 return;
581 }
237 582
238 /* XXX These are magic numbers and do not belong! */ 583 /* Loadbits define pull setup for the I2C channels */
239 vc_val = (0x60 << OMAP4430_SCLL_SHIFT | 0x26 << OMAP4430_SCLH_SHIFT); 584 val = i2c_data->loadbits << 25 | i2c_data->loadbits << 29;
240 voltdm->write(vc_val, OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET);
241 585
242 is_initialized = true; 586 /* Write to SYSCTRL_PADCONF_WKUP_CTRL_I2C_2 to setup I2C pull */
587 __raw_writel(val, OMAP2_L4_IO_ADDRESS(OMAP4_CTRL_MODULE_PAD_WKUP +
588 OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_I2C_2));
589
590 /* HSSCLH can always be zero */
591 val = hsscll << OMAP4430_HSSCLL_SHIFT;
592 val |= (0x28 << OMAP4430_SCLL_SHIFT | 0x2c << OMAP4430_SCLH_SHIFT);
593
594 /* Write setup times to I2C config register */
595 voltdm->write(val, OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET);
243} 596}
244 597
598
599
245/** 600/**
246 * omap_vc_i2c_init - initialize I2C interface to PMIC 601 * omap_vc_i2c_init - initialize I2C interface to PMIC
247 * @voltdm: voltage domain containing VC data 602 * @voltdm: voltage domain containing VC data
@@ -281,9 +636,51 @@ static void __init omap_vc_i2c_init(struct voltagedomain *voltdm)
281 mcode << __ffs(vc->common->i2c_mcode_mask), 636 mcode << __ffs(vc->common->i2c_mcode_mask),
282 vc->common->i2c_cfg_reg); 637 vc->common->i2c_cfg_reg);
283 638
639 if (cpu_is_omap44xx())
640 omap4_vc_i2c_timing_init(voltdm);
641
284 initialized = true; 642 initialized = true;
285} 643}
286 644
645/**
646 * omap_vc_calc_vsel - calculate vsel value for a channel
647 * @voltdm: channel to calculate value for
648 * @uvolt: microvolt value to convert to vsel
649 *
650 * Converts a microvolt value to vsel value for the used PMIC.
651 * This checks whether the microvolt value is out of bounds, and
652 * adjusts the value accordingly. If unsupported value detected,
653 * warning is thrown.
654 */
655static u8 omap_vc_calc_vsel(struct voltagedomain *voltdm, u32 uvolt)
656{
657 if (voltdm->pmic->vddmin > uvolt)
658 uvolt = voltdm->pmic->vddmin;
659 if (voltdm->pmic->vddmax < uvolt) {
660 WARN(1, "%s: voltage not supported by pmic: %u vs max %u\n",
661 __func__, uvolt, voltdm->pmic->vddmax);
662 /* Lets try maximum value anyway */
663 uvolt = voltdm->pmic->vddmax;
664 }
665
666 return voltdm->pmic->uv_to_vsel(uvolt);
667}
668
669#ifdef CONFIG_PM
670/**
671 * omap_pm_setup_sr_i2c_pcb_length - set length of SR I2C traces on PCB
672 * @mm: length of the PCB trace in millimetres
673 *
674 * Sets the PCB trace length for the I2C channel. By default uses 63mm.
675 * This is needed for properly calculating the capacitance value for
676 * the PCB trace, and for setting the SR I2C channel timing parameters.
677 */
678void __init omap_pm_setup_sr_i2c_pcb_length(u32 mm)
679{
680 sr_i2c_pcb_length = mm;
681}
682#endif
683
287void __init omap_vc_init_channel(struct voltagedomain *voltdm) 684void __init omap_vc_init_channel(struct voltagedomain *voltdm)
288{ 685{
289 struct omap_vc_channel *vc = voltdm->vc; 686 struct omap_vc_channel *vc = voltdm->vc;
@@ -311,7 +708,6 @@ void __init omap_vc_init_channel(struct voltagedomain *voltdm)
311 vc->i2c_slave_addr = voltdm->pmic->i2c_slave_addr; 708 vc->i2c_slave_addr = voltdm->pmic->i2c_slave_addr;
312 vc->volt_reg_addr = voltdm->pmic->volt_reg_addr; 709 vc->volt_reg_addr = voltdm->pmic->volt_reg_addr;
313 vc->cmd_reg_addr = voltdm->pmic->cmd_reg_addr; 710 vc->cmd_reg_addr = voltdm->pmic->cmd_reg_addr;
314 vc->setup_time = voltdm->pmic->volt_setup_time;
315 711
316 /* Configure the i2c slave address for this VC */ 712 /* Configure the i2c slave address for this VC */
317 voltdm->rmw(vc->smps_sa_mask, 713 voltdm->rmw(vc->smps_sa_mask,
@@ -331,14 +727,18 @@ void __init omap_vc_init_channel(struct voltagedomain *voltdm)
331 voltdm->rmw(vc->smps_cmdra_mask, 727 voltdm->rmw(vc->smps_cmdra_mask,
332 vc->cmd_reg_addr << __ffs(vc->smps_cmdra_mask), 728 vc->cmd_reg_addr << __ffs(vc->smps_cmdra_mask),
333 vc->smps_cmdra_reg); 729 vc->smps_cmdra_reg);
334 vc->cfg_channel |= vc_cfg_bits->rac | vc_cfg_bits->racen; 730 vc->cfg_channel |= vc_cfg_bits->rac;
335 } 731 }
336 732
733 if (vc->cmd_reg_addr == vc->volt_reg_addr)
734 vc->cfg_channel |= vc_cfg_bits->racen;
735
337 /* Set up the on, inactive, retention and off voltage */ 736 /* Set up the on, inactive, retention and off voltage */
338 on_vsel = voltdm->pmic->uv_to_vsel(voltdm->pmic->on_volt); 737 on_vsel = omap_vc_calc_vsel(voltdm, voltdm->vc_param->on);
339 onlp_vsel = voltdm->pmic->uv_to_vsel(voltdm->pmic->onlp_volt); 738 onlp_vsel = omap_vc_calc_vsel(voltdm, voltdm->vc_param->onlp);
340 ret_vsel = voltdm->pmic->uv_to_vsel(voltdm->pmic->ret_volt); 739 ret_vsel = omap_vc_calc_vsel(voltdm, voltdm->vc_param->ret);
341 off_vsel = voltdm->pmic->uv_to_vsel(voltdm->pmic->off_volt); 740 off_vsel = omap_vc_calc_vsel(voltdm, voltdm->vc_param->off);
741
342 val = ((on_vsel << vc->common->cmd_on_shift) | 742 val = ((on_vsel << vc->common->cmd_on_shift) |
343 (onlp_vsel << vc->common->cmd_onlp_shift) | 743 (onlp_vsel << vc->common->cmd_onlp_shift) |
344 (ret_vsel << vc->common->cmd_ret_shift) | 744 (ret_vsel << vc->common->cmd_ret_shift) |
@@ -349,11 +749,6 @@ void __init omap_vc_init_channel(struct voltagedomain *voltdm)
349 /* Channel configuration */ 749 /* Channel configuration */
350 omap_vc_config_channel(voltdm); 750 omap_vc_config_channel(voltdm);
351 751
352 /* Configure the setup times */
353 voltdm->rmw(voltdm->vfsm->voltsetup_mask,
354 vc->setup_time << __ffs(voltdm->vfsm->voltsetup_mask),
355 voltdm->vfsm->voltsetup_reg);
356
357 omap_vc_i2c_init(voltdm); 752 omap_vc_i2c_init(voltdm);
358 753
359 if (cpu_is_omap34xx()) 754 if (cpu_is_omap34xx())
diff --git a/arch/arm/mach-omap2/vc.h b/arch/arm/mach-omap2/vc.h
index 478bf6b432c4..91c8d75bf2ea 100644
--- a/arch/arm/mach-omap2/vc.h
+++ b/arch/arm/mach-omap2/vc.h
@@ -86,7 +86,6 @@ struct omap_vc_channel {
86 u16 i2c_slave_addr; 86 u16 i2c_slave_addr;
87 u16 volt_reg_addr; 87 u16 volt_reg_addr;
88 u16 cmd_reg_addr; 88 u16 cmd_reg_addr;
89 u16 setup_time;
90 u8 cfg_channel; 89 u8 cfg_channel;
91 bool i2c_high_speed; 90 bool i2c_high_speed;
92 91
@@ -111,6 +110,13 @@ extern struct omap_vc_channel omap4_vc_mpu;
111extern struct omap_vc_channel omap4_vc_iva; 110extern struct omap_vc_channel omap4_vc_iva;
112extern struct omap_vc_channel omap4_vc_core; 111extern struct omap_vc_channel omap4_vc_core;
113 112
113extern struct omap_vc_param omap3_mpu_vc_data;
114extern struct omap_vc_param omap3_core_vc_data;
115
116extern struct omap_vc_param omap4_mpu_vc_data;
117extern struct omap_vc_param omap4_iva_vc_data;
118extern struct omap_vc_param omap4_core_vc_data;
119
114void omap_vc_init_channel(struct voltagedomain *voltdm); 120void omap_vc_init_channel(struct voltagedomain *voltdm);
115int omap_vc_pre_scale(struct voltagedomain *voltdm, 121int omap_vc_pre_scale(struct voltagedomain *voltdm,
116 unsigned long target_volt, 122 unsigned long target_volt,
diff --git a/arch/arm/mach-omap2/vc3xxx_data.c b/arch/arm/mach-omap2/vc3xxx_data.c
index 5d8eaf31569c..75bc4aa22b3a 100644
--- a/arch/arm/mach-omap2/vc3xxx_data.c
+++ b/arch/arm/mach-omap2/vc3xxx_data.c
@@ -71,3 +71,25 @@ struct omap_vc_channel omap3_vc_core = {
71 .smps_cmdra_mask = OMAP3430_CMDRA1_MASK, 71 .smps_cmdra_mask = OMAP3430_CMDRA1_MASK,
72 .cfg_channel_sa_shift = OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT, 72 .cfg_channel_sa_shift = OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT,
73}; 73};
74
75/*
76 * Voltage levels for different operating modes: on, sleep, retention and off
77 */
78#define OMAP3_ON_VOLTAGE_UV 1200000
79#define OMAP3_ONLP_VOLTAGE_UV 1000000
80#define OMAP3_RET_VOLTAGE_UV 975000
81#define OMAP3_OFF_VOLTAGE_UV 600000
82
83struct omap_vc_param omap3_mpu_vc_data = {
84 .on = OMAP3_ON_VOLTAGE_UV,
85 .onlp = OMAP3_ONLP_VOLTAGE_UV,
86 .ret = OMAP3_RET_VOLTAGE_UV,
87 .off = OMAP3_OFF_VOLTAGE_UV,
88};
89
90struct omap_vc_param omap3_core_vc_data = {
91 .on = OMAP3_ON_VOLTAGE_UV,
92 .onlp = OMAP3_ONLP_VOLTAGE_UV,
93 .ret = OMAP3_RET_VOLTAGE_UV,
94 .off = OMAP3_OFF_VOLTAGE_UV,
95};
diff --git a/arch/arm/mach-omap2/vc44xx_data.c b/arch/arm/mach-omap2/vc44xx_data.c
index d70b930f2739..085e5d6a04fd 100644
--- a/arch/arm/mach-omap2/vc44xx_data.c
+++ b/arch/arm/mach-omap2/vc44xx_data.c
@@ -87,3 +87,31 @@ struct omap_vc_channel omap4_vc_core = {
87 .cfg_channel_sa_shift = OMAP4430_SA_VDD_CORE_L_SHIFT, 87 .cfg_channel_sa_shift = OMAP4430_SA_VDD_CORE_L_SHIFT,
88}; 88};
89 89
90/*
91 * Voltage levels for different operating modes: on, sleep, retention and off
92 */
93#define OMAP4_ON_VOLTAGE_UV 1375000
94#define OMAP4_ONLP_VOLTAGE_UV 1375000
95#define OMAP4_RET_VOLTAGE_UV 837500
96#define OMAP4_OFF_VOLTAGE_UV 0
97
98struct omap_vc_param omap4_mpu_vc_data = {
99 .on = OMAP4_ON_VOLTAGE_UV,
100 .onlp = OMAP4_ONLP_VOLTAGE_UV,
101 .ret = OMAP4_RET_VOLTAGE_UV,
102 .off = OMAP4_OFF_VOLTAGE_UV,
103};
104
105struct omap_vc_param omap4_iva_vc_data = {
106 .on = OMAP4_ON_VOLTAGE_UV,
107 .onlp = OMAP4_ONLP_VOLTAGE_UV,
108 .ret = OMAP4_RET_VOLTAGE_UV,
109 .off = OMAP4_OFF_VOLTAGE_UV,
110};
111
112struct omap_vc_param omap4_core_vc_data = {
113 .on = OMAP4_ON_VOLTAGE_UV,
114 .onlp = OMAP4_ONLP_VOLTAGE_UV,
115 .ret = OMAP4_RET_VOLTAGE_UV,
116 .off = OMAP4_OFF_VOLTAGE_UV,
117};
diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h
index 7283b7ed7de8..a0ce4f10ff13 100644
--- a/arch/arm/mach-omap2/voltage.h
+++ b/arch/arm/mach-omap2/voltage.h
@@ -40,12 +40,14 @@ struct powerdomain;
40 * data 40 * data
41 * @voltsetup_mask: SETUP_TIME* bitmask in the PRM_VOLTSETUP* register 41 * @voltsetup_mask: SETUP_TIME* bitmask in the PRM_VOLTSETUP* register
42 * @voltsetup_reg: register offset of PRM_VOLTSETUP from PRM base 42 * @voltsetup_reg: register offset of PRM_VOLTSETUP from PRM base
43 * @voltsetup_off_reg: register offset of PRM_VOLTSETUP_OFF from PRM base
43 * 44 *
44 * XXX What about VOLTOFFSET/VOLTCTRL? 45 * XXX What about VOLTOFFSET/VOLTCTRL?
45 */ 46 */
46struct omap_vfsm_instance { 47struct omap_vfsm_instance {
47 u32 voltsetup_mask; 48 u32 voltsetup_mask;
48 u8 voltsetup_reg; 49 u8 voltsetup_reg;
50 u8 voltsetup_off_reg;
49}; 51};
50 52
51/** 53/**
@@ -74,6 +76,8 @@ struct voltagedomain {
74 const struct omap_vfsm_instance *vfsm; 76 const struct omap_vfsm_instance *vfsm;
75 struct omap_vp_instance *vp; 77 struct omap_vp_instance *vp;
76 struct omap_voltdm_pmic *pmic; 78 struct omap_voltdm_pmic *pmic;
79 struct omap_vp_param *vp_param;
80 struct omap_vc_param *vc_param;
77 81
78 /* VC/VP register access functions: SoC specific */ 82 /* VC/VP register access functions: SoC specific */
79 u32 (*read) (u8 offset); 83 u32 (*read) (u8 offset);
@@ -92,6 +96,24 @@ struct voltagedomain {
92 struct omap_volt_data *volt_data; 96 struct omap_volt_data *volt_data;
93}; 97};
94 98
99/* Min and max voltages from OMAP perspective */
100#define OMAP3430_VP1_VLIMITTO_VDDMIN 850000
101#define OMAP3430_VP1_VLIMITTO_VDDMAX 1425000
102#define OMAP3430_VP2_VLIMITTO_VDDMIN 900000
103#define OMAP3430_VP2_VLIMITTO_VDDMAX 1150000
104
105#define OMAP3630_VP1_VLIMITTO_VDDMIN 900000
106#define OMAP3630_VP1_VLIMITTO_VDDMAX 1350000
107#define OMAP3630_VP2_VLIMITTO_VDDMIN 900000
108#define OMAP3630_VP2_VLIMITTO_VDDMAX 1200000
109
110#define OMAP4_VP_MPU_VLIMITTO_VDDMIN 830000
111#define OMAP4_VP_MPU_VLIMITTO_VDDMAX 1410000
112#define OMAP4_VP_IVA_VLIMITTO_VDDMIN 830000
113#define OMAP4_VP_IVA_VLIMITTO_VDDMAX 1260000
114#define OMAP4_VP_CORE_VLIMITTO_VDDMIN 830000
115#define OMAP4_VP_CORE_VLIMITTO_VDDMAX 1200000
116
95/** 117/**
96 * struct omap_voltdm_pmic - PMIC specific data required by voltage driver. 118 * struct omap_voltdm_pmic - PMIC specific data required by voltage driver.
97 * @slew_rate: PMIC slew rate (in uv/us) 119 * @slew_rate: PMIC slew rate (in uv/us)
@@ -107,26 +129,34 @@ struct voltagedomain {
107struct omap_voltdm_pmic { 129struct omap_voltdm_pmic {
108 int slew_rate; 130 int slew_rate;
109 int step_size; 131 int step_size;
110 u32 on_volt;
111 u32 onlp_volt;
112 u32 ret_volt;
113 u32 off_volt;
114 u16 volt_setup_time;
115 u16 i2c_slave_addr; 132 u16 i2c_slave_addr;
116 u16 volt_reg_addr; 133 u16 volt_reg_addr;
117 u16 cmd_reg_addr; 134 u16 cmd_reg_addr;
118 u8 vp_erroroffset; 135 u8 vp_erroroffset;
119 u8 vp_vstepmin; 136 u8 vp_vstepmin;
120 u8 vp_vstepmax; 137 u8 vp_vstepmax;
121 u8 vp_vddmin; 138 u32 vddmin;
122 u8 vp_vddmax; 139 u32 vddmax;
123 u8 vp_timeout_us; 140 u8 vp_timeout_us;
124 bool i2c_high_speed; 141 bool i2c_high_speed;
142 u32 i2c_pad_load;
125 u8 i2c_mcode; 143 u8 i2c_mcode;
126 unsigned long (*vsel_to_uv) (const u8 vsel); 144 unsigned long (*vsel_to_uv) (const u8 vsel);
127 u8 (*uv_to_vsel) (unsigned long uV); 145 u8 (*uv_to_vsel) (unsigned long uV);
128}; 146};
129 147
148struct omap_vp_param {
149 u32 vddmax;
150 u32 vddmin;
151};
152
153struct omap_vc_param {
154 u32 on;
155 u32 onlp;
156 u32 ret;
157 u32 off;
158};
159
130void omap_voltage_get_volttable(struct voltagedomain *voltdm, 160void omap_voltage_get_volttable(struct voltagedomain *voltdm,
131 struct omap_volt_data **volt_data); 161 struct omap_volt_data **volt_data);
132struct omap_volt_data *omap_voltage_get_voltdata(struct voltagedomain *voltdm, 162struct omap_volt_data *omap_voltage_get_voltdata(struct voltagedomain *voltdm,
diff --git a/arch/arm/mach-omap2/voltagedomains3xxx_data.c b/arch/arm/mach-omap2/voltagedomains3xxx_data.c
index 63afbfed3cbc..261bb7cb4e60 100644
--- a/arch/arm/mach-omap2/voltagedomains3xxx_data.c
+++ b/arch/arm/mach-omap2/voltagedomains3xxx_data.c
@@ -117,6 +117,11 @@ void __init omap3xxx_voltagedomains_init(void)
117 } 117 }
118#endif 118#endif
119 119
120 omap3_voltdm_mpu.vp_param = &omap3_mpu_vp_data;
121 omap3_voltdm_core.vp_param = &omap3_core_vp_data;
122 omap3_voltdm_mpu.vc_param = &omap3_mpu_vc_data;
123 omap3_voltdm_core.vc_param = &omap3_core_vc_data;
124
120 if (soc_is_am35xx()) 125 if (soc_is_am35xx())
121 voltdms = voltagedomains_am35xx; 126 voltdms = voltagedomains_am35xx;
122 else 127 else
diff --git a/arch/arm/mach-omap2/voltagedomains44xx_data.c b/arch/arm/mach-omap2/voltagedomains44xx_data.c
index c3115f6853d4..48b22a0a0c88 100644
--- a/arch/arm/mach-omap2/voltagedomains44xx_data.c
+++ b/arch/arm/mach-omap2/voltagedomains44xx_data.c
@@ -22,7 +22,7 @@
22#include <linux/init.h> 22#include <linux/init.h>
23 23
24#include "common.h" 24#include "common.h"
25 25#include "soc.h"
26#include "prm-regbits-44xx.h" 26#include "prm-regbits-44xx.h"
27#include "prm44xx.h" 27#include "prm44xx.h"
28#include "prcm44xx.h" 28#include "prcm44xx.h"
@@ -34,14 +34,17 @@
34 34
35static const struct omap_vfsm_instance omap4_vdd_mpu_vfsm = { 35static const struct omap_vfsm_instance omap4_vdd_mpu_vfsm = {
36 .voltsetup_reg = OMAP4_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET, 36 .voltsetup_reg = OMAP4_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET,
37 .voltsetup_off_reg = OMAP4_PRM_VOLTSETUP_MPU_OFF_OFFSET,
37}; 38};
38 39
39static const struct omap_vfsm_instance omap4_vdd_iva_vfsm = { 40static const struct omap_vfsm_instance omap4_vdd_iva_vfsm = {
40 .voltsetup_reg = OMAP4_PRM_VOLTSETUP_IVA_RET_SLEEP_OFFSET, 41 .voltsetup_reg = OMAP4_PRM_VOLTSETUP_IVA_RET_SLEEP_OFFSET,
42 .voltsetup_off_reg = OMAP4_PRM_VOLTSETUP_IVA_OFF_OFFSET,
41}; 43};
42 44
43static const struct omap_vfsm_instance omap4_vdd_core_vfsm = { 45static const struct omap_vfsm_instance omap4_vdd_core_vfsm = {
44 .voltsetup_reg = OMAP4_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET, 46 .voltsetup_reg = OMAP4_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET,
47 .voltsetup_off_reg = OMAP4_PRM_VOLTSETUP_CORE_OFF_OFFSET,
45}; 48};
46 49
47static struct voltagedomain omap4_voltdm_mpu = { 50static struct voltagedomain omap4_voltdm_mpu = {
@@ -101,11 +104,25 @@ void __init omap44xx_voltagedomains_init(void)
101 * for the currently-running IC 104 * for the currently-running IC
102 */ 105 */
103#ifdef CONFIG_PM_OPP 106#ifdef CONFIG_PM_OPP
104 omap4_voltdm_mpu.volt_data = omap44xx_vdd_mpu_volt_data; 107 if (cpu_is_omap443x()) {
105 omap4_voltdm_iva.volt_data = omap44xx_vdd_iva_volt_data; 108 omap4_voltdm_mpu.volt_data = omap443x_vdd_mpu_volt_data;
106 omap4_voltdm_core.volt_data = omap44xx_vdd_core_volt_data; 109 omap4_voltdm_iva.volt_data = omap443x_vdd_iva_volt_data;
110 omap4_voltdm_core.volt_data = omap443x_vdd_core_volt_data;
111 } else if (cpu_is_omap446x()) {
112 omap4_voltdm_mpu.volt_data = omap446x_vdd_mpu_volt_data;
113 omap4_voltdm_iva.volt_data = omap446x_vdd_iva_volt_data;
114 omap4_voltdm_core.volt_data = omap446x_vdd_core_volt_data;
115 }
107#endif 116#endif
108 117
118 omap4_voltdm_mpu.vp_param = &omap4_mpu_vp_data;
119 omap4_voltdm_iva.vp_param = &omap4_iva_vp_data;
120 omap4_voltdm_core.vp_param = &omap4_core_vp_data;
121
122 omap4_voltdm_mpu.vc_param = &omap4_mpu_vc_data;
123 omap4_voltdm_iva.vc_param = &omap4_iva_vc_data;
124 omap4_voltdm_core.vc_param = &omap4_core_vc_data;
125
109 for (i = 0; voltdm = voltagedomains_omap4[i], voltdm; i++) 126 for (i = 0; voltdm = voltagedomains_omap4[i], voltdm; i++)
110 voltdm->sys_clk.name = sys_clk_name; 127 voltdm->sys_clk.name = sys_clk_name;
111 128
diff --git a/arch/arm/mach-omap2/vp.c b/arch/arm/mach-omap2/vp.c
index 85241b828c02..a3c30655aa30 100644
--- a/arch/arm/mach-omap2/vp.c
+++ b/arch/arm/mach-omap2/vp.c
@@ -58,8 +58,10 @@ void __init omap_vp_init(struct voltagedomain *voltdm)
58 sys_clk_rate = voltdm->sys_clk.rate / 1000; 58 sys_clk_rate = voltdm->sys_clk.rate / 1000;
59 59
60 timeout = (sys_clk_rate * voltdm->pmic->vp_timeout_us) / 1000; 60 timeout = (sys_clk_rate * voltdm->pmic->vp_timeout_us) / 1000;
61 vddmin = voltdm->pmic->vp_vddmin; 61 vddmin = max(voltdm->vp_param->vddmin, voltdm->pmic->vddmin);
62 vddmax = voltdm->pmic->vp_vddmax; 62 vddmax = min(voltdm->vp_param->vddmax, voltdm->pmic->vddmax);
63 vddmin = voltdm->pmic->uv_to_vsel(vddmin);
64 vddmax = voltdm->pmic->uv_to_vsel(vddmax);
63 65
64 waittime = DIV_ROUND_UP(voltdm->pmic->step_size * sys_clk_rate, 66 waittime = DIV_ROUND_UP(voltdm->pmic->step_size * sys_clk_rate,
65 1000 * voltdm->pmic->slew_rate); 67 1000 * voltdm->pmic->slew_rate);
@@ -138,7 +140,7 @@ int omap_vp_forceupdate_scale(struct voltagedomain *voltdm,
138 udelay(1); 140 udelay(1);
139 } 141 }
140 if (timeout >= VP_TRANXDONE_TIMEOUT) { 142 if (timeout >= VP_TRANXDONE_TIMEOUT) {
141 pr_warn("%s: vdd_%s TRANXDONE timeout exceeded. Voltage change aborted", 143 pr_warn("%s: vdd_%s TRANXDONE timeout exceeded. Voltage change aborted\n",
142 __func__, voltdm->name); 144 __func__, voltdm->name);
143 return -ETIMEDOUT; 145 return -ETIMEDOUT;
144 } 146 }
@@ -197,7 +199,7 @@ void omap_vp_enable(struct voltagedomain *voltdm)
197 u32 vpconfig, volt; 199 u32 vpconfig, volt;
198 200
199 if (!voltdm || IS_ERR(voltdm)) { 201 if (!voltdm || IS_ERR(voltdm)) {
200 pr_warning("%s: VDD specified does not exist!\n", __func__); 202 pr_warn("%s: VDD specified does not exist!\n", __func__);
201 return; 203 return;
202 } 204 }
203 205
@@ -214,8 +216,8 @@ void omap_vp_enable(struct voltagedomain *voltdm)
214 216
215 volt = voltdm_get_voltage(voltdm); 217 volt = voltdm_get_voltage(voltdm);
216 if (!volt) { 218 if (!volt) {
217 pr_warning("%s: unable to find current voltage for %s\n", 219 pr_warn("%s: unable to find current voltage for %s\n",
218 __func__, voltdm->name); 220 __func__, voltdm->name);
219 return; 221 return;
220 } 222 }
221 223
@@ -242,7 +244,7 @@ void omap_vp_disable(struct voltagedomain *voltdm)
242 int timeout; 244 int timeout;
243 245
244 if (!voltdm || IS_ERR(voltdm)) { 246 if (!voltdm || IS_ERR(voltdm)) {
245 pr_warning("%s: VDD specified does not exist!\n", __func__); 247 pr_warn("%s: VDD specified does not exist!\n", __func__);
246 return; 248 return;
247 } 249 }
248 250
@@ -272,8 +274,7 @@ void omap_vp_disable(struct voltagedomain *voltdm)
272 VP_IDLE_TIMEOUT, timeout); 274 VP_IDLE_TIMEOUT, timeout);
273 275
274 if (timeout >= VP_IDLE_TIMEOUT) 276 if (timeout >= VP_IDLE_TIMEOUT)
275 pr_warning("%s: vdd_%s idle timedout\n", 277 pr_warn("%s: vdd_%s idle timedout\n", __func__, voltdm->name);
276 __func__, voltdm->name);
277 278
278 vp->enabled = false; 279 vp->enabled = false;
279 280
diff --git a/arch/arm/mach-omap2/vp.h b/arch/arm/mach-omap2/vp.h
index 7c155d248aa3..0fdf7080e4a6 100644
--- a/arch/arm/mach-omap2/vp.h
+++ b/arch/arm/mach-omap2/vp.h
@@ -117,6 +117,13 @@ extern struct omap_vp_instance omap4_vp_mpu;
117extern struct omap_vp_instance omap4_vp_iva; 117extern struct omap_vp_instance omap4_vp_iva;
118extern struct omap_vp_instance omap4_vp_core; 118extern struct omap_vp_instance omap4_vp_core;
119 119
120extern struct omap_vp_param omap3_mpu_vp_data;
121extern struct omap_vp_param omap3_core_vp_data;
122
123extern struct omap_vp_param omap4_mpu_vp_data;
124extern struct omap_vp_param omap4_iva_vp_data;
125extern struct omap_vp_param omap4_core_vp_data;
126
120void omap_vp_init(struct voltagedomain *voltdm); 127void omap_vp_init(struct voltagedomain *voltdm);
121void omap_vp_enable(struct voltagedomain *voltdm); 128void omap_vp_enable(struct voltagedomain *voltdm);
122void omap_vp_disable(struct voltagedomain *voltdm); 129void omap_vp_disable(struct voltagedomain *voltdm);
diff --git a/arch/arm/mach-omap2/vp3xxx_data.c b/arch/arm/mach-omap2/vp3xxx_data.c
index bd89f80089f5..1914e026245e 100644
--- a/arch/arm/mach-omap2/vp3xxx_data.c
+++ b/arch/arm/mach-omap2/vp3xxx_data.c
@@ -77,3 +77,13 @@ struct omap_vp_instance omap3_vp_core = {
77 .vstatus = OMAP3_PRM_VP2_STATUS_OFFSET, 77 .vstatus = OMAP3_PRM_VP2_STATUS_OFFSET,
78 .voltage = OMAP3_PRM_VP2_VOLTAGE_OFFSET, 78 .voltage = OMAP3_PRM_VP2_VOLTAGE_OFFSET,
79}; 79};
80
81struct omap_vp_param omap3_mpu_vp_data = {
82 .vddmin = OMAP3430_VP1_VLIMITTO_VDDMIN,
83 .vddmax = OMAP3430_VP1_VLIMITTO_VDDMAX,
84};
85
86struct omap_vp_param omap3_core_vp_data = {
87 .vddmin = OMAP3430_VP2_VLIMITTO_VDDMIN,
88 .vddmax = OMAP3430_VP2_VLIMITTO_VDDMAX,
89};
diff --git a/arch/arm/mach-omap2/vp44xx_data.c b/arch/arm/mach-omap2/vp44xx_data.c
index 8c031d16879e..e62f6b018beb 100644
--- a/arch/arm/mach-omap2/vp44xx_data.c
+++ b/arch/arm/mach-omap2/vp44xx_data.c
@@ -87,3 +87,18 @@ struct omap_vp_instance omap4_vp_core = {
87 .vstatus = OMAP4_PRM_VP_CORE_STATUS_OFFSET, 87 .vstatus = OMAP4_PRM_VP_CORE_STATUS_OFFSET,
88 .voltage = OMAP4_PRM_VP_CORE_VOLTAGE_OFFSET, 88 .voltage = OMAP4_PRM_VP_CORE_VOLTAGE_OFFSET,
89}; 89};
90
91struct omap_vp_param omap4_mpu_vp_data = {
92 .vddmin = OMAP4_VP_MPU_VLIMITTO_VDDMIN,
93 .vddmax = OMAP4_VP_MPU_VLIMITTO_VDDMAX,
94};
95
96struct omap_vp_param omap4_iva_vp_data = {
97 .vddmin = OMAP4_VP_IVA_VLIMITTO_VDDMIN,
98 .vddmax = OMAP4_VP_IVA_VLIMITTO_VDDMAX,
99};
100
101struct omap_vp_param omap4_core_vp_data = {
102 .vddmin = OMAP4_VP_CORE_VLIMITTO_VDDMIN,
103 .vddmax = OMAP4_VP_CORE_VLIMITTO_VDDMAX,
104};
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index c288b76f8e6c..37a488aaa2ba 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -36,7 +36,7 @@
36#include <linux/slab.h> 36#include <linux/slab.h>
37#include <linux/delay.h> 37#include <linux/delay.h>
38 38
39#include <plat-omap/dma-omap.h> 39#include <linux/omap-dma.h>
40 40
41/* 41/*
42 * MAX_LOGICAL_DMA_CH_COUNT: the maximum number of logical DMA 42 * MAX_LOGICAL_DMA_CH_COUNT: the maximum number of logical DMA
diff --git a/arch/arm/plat-omap/include/plat-omap/dma-omap.h b/arch/arm/plat-omap/include/plat-omap/dma-omap.h
deleted file mode 100644
index 6f506ba9e453..000000000000
--- a/arch/arm/plat-omap/include/plat-omap/dma-omap.h
+++ /dev/null
@@ -1,377 +0,0 @@
1/*
2 * OMAP DMA handling defines and function
3 *
4 * Copyright (C) 2003 Nokia Corporation
5 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#ifndef __ASM_ARCH_DMA_H
22#define __ASM_ARCH_DMA_H
23
24#include <linux/platform_device.h>
25
26#define INT_DMA_LCD 25
27
28#define OMAP1_DMA_TOUT_IRQ (1 << 0)
29#define OMAP_DMA_DROP_IRQ (1 << 1)
30#define OMAP_DMA_HALF_IRQ (1 << 2)
31#define OMAP_DMA_FRAME_IRQ (1 << 3)
32#define OMAP_DMA_LAST_IRQ (1 << 4)
33#define OMAP_DMA_BLOCK_IRQ (1 << 5)
34#define OMAP1_DMA_SYNC_IRQ (1 << 6)
35#define OMAP2_DMA_PKT_IRQ (1 << 7)
36#define OMAP2_DMA_TRANS_ERR_IRQ (1 << 8)
37#define OMAP2_DMA_SECURE_ERR_IRQ (1 << 9)
38#define OMAP2_DMA_SUPERVISOR_ERR_IRQ (1 << 10)
39#define OMAP2_DMA_MISALIGNED_ERR_IRQ (1 << 11)
40
41#define OMAP_DMA_CCR_EN (1 << 7)
42#define OMAP_DMA_CCR_RD_ACTIVE (1 << 9)
43#define OMAP_DMA_CCR_WR_ACTIVE (1 << 10)
44#define OMAP_DMA_CCR_SEL_SRC_DST_SYNC (1 << 24)
45#define OMAP_DMA_CCR_BUFFERING_DISABLE (1 << 25)
46
47#define OMAP_DMA_DATA_TYPE_S8 0x00
48#define OMAP_DMA_DATA_TYPE_S16 0x01
49#define OMAP_DMA_DATA_TYPE_S32 0x02
50
51#define OMAP_DMA_SYNC_ELEMENT 0x00
52#define OMAP_DMA_SYNC_FRAME 0x01
53#define OMAP_DMA_SYNC_BLOCK 0x02
54#define OMAP_DMA_SYNC_PACKET 0x03
55
56#define OMAP_DMA_DST_SYNC_PREFETCH 0x02
57#define OMAP_DMA_SRC_SYNC 0x01
58#define OMAP_DMA_DST_SYNC 0x00
59
60#define OMAP_DMA_PORT_EMIFF 0x00
61#define OMAP_DMA_PORT_EMIFS 0x01
62#define OMAP_DMA_PORT_OCP_T1 0x02
63#define OMAP_DMA_PORT_TIPB 0x03
64#define OMAP_DMA_PORT_OCP_T2 0x04
65#define OMAP_DMA_PORT_MPUI 0x05
66
67#define OMAP_DMA_AMODE_CONSTANT 0x00
68#define OMAP_DMA_AMODE_POST_INC 0x01
69#define OMAP_DMA_AMODE_SINGLE_IDX 0x02
70#define OMAP_DMA_AMODE_DOUBLE_IDX 0x03
71
72#define DMA_DEFAULT_FIFO_DEPTH 0x10
73#define DMA_DEFAULT_ARB_RATE 0x01
74/* Pass THREAD_RESERVE ORed with THREAD_FIFO for tparams */
75#define DMA_THREAD_RESERVE_NORM (0x00 << 12) /* Def */
76#define DMA_THREAD_RESERVE_ONET (0x01 << 12)
77#define DMA_THREAD_RESERVE_TWOT (0x02 << 12)
78#define DMA_THREAD_RESERVE_THREET (0x03 << 12)
79#define DMA_THREAD_FIFO_NONE (0x00 << 14) /* Def */
80#define DMA_THREAD_FIFO_75 (0x01 << 14)
81#define DMA_THREAD_FIFO_25 (0x02 << 14)
82#define DMA_THREAD_FIFO_50 (0x03 << 14)
83
84/* DMA4_OCP_SYSCONFIG bits */
85#define DMA_SYSCONFIG_MIDLEMODE_MASK (3 << 12)
86#define DMA_SYSCONFIG_CLOCKACTIVITY_MASK (3 << 8)
87#define DMA_SYSCONFIG_EMUFREE (1 << 5)
88#define DMA_SYSCONFIG_SIDLEMODE_MASK (3 << 3)
89#define DMA_SYSCONFIG_SOFTRESET (1 << 2)
90#define DMA_SYSCONFIG_AUTOIDLE (1 << 0)
91
92#define DMA_SYSCONFIG_MIDLEMODE(n) ((n) << 12)
93#define DMA_SYSCONFIG_SIDLEMODE(n) ((n) << 3)
94
95#define DMA_IDLEMODE_SMARTIDLE 0x2
96#define DMA_IDLEMODE_NO_IDLE 0x1
97#define DMA_IDLEMODE_FORCE_IDLE 0x0
98
99/* Chaining modes*/
100#ifndef CONFIG_ARCH_OMAP1
101#define OMAP_DMA_STATIC_CHAIN 0x1
102#define OMAP_DMA_DYNAMIC_CHAIN 0x2
103#define OMAP_DMA_CHAIN_ACTIVE 0x1
104#define OMAP_DMA_CHAIN_INACTIVE 0x0
105#endif
106
107#define DMA_CH_PRIO_HIGH 0x1
108#define DMA_CH_PRIO_LOW 0x0 /* Def */
109
110/* Errata handling */
111#define IS_DMA_ERRATA(id) (errata & (id))
112#define SET_DMA_ERRATA(id) (errata |= (id))
113
114#define DMA_ERRATA_IFRAME_BUFFERING BIT(0x0)
115#define DMA_ERRATA_PARALLEL_CHANNELS BIT(0x1)
116#define DMA_ERRATA_i378 BIT(0x2)
117#define DMA_ERRATA_i541 BIT(0x3)
118#define DMA_ERRATA_i88 BIT(0x4)
119#define DMA_ERRATA_3_3 BIT(0x5)
120#define DMA_ROMCODE_BUG BIT(0x6)
121
122/* Attributes for OMAP DMA Contrller */
123#define DMA_LINKED_LCH BIT(0x0)
124#define GLOBAL_PRIORITY BIT(0x1)
125#define RESERVE_CHANNEL BIT(0x2)
126#define IS_CSSA_32 BIT(0x3)
127#define IS_CDSA_32 BIT(0x4)
128#define IS_RW_PRIORITY BIT(0x5)
129#define ENABLE_1510_MODE BIT(0x6)
130#define SRC_PORT BIT(0x7)
131#define DST_PORT BIT(0x8)
132#define SRC_INDEX BIT(0x9)
133#define DST_INDEX BIT(0xa)
134#define IS_BURST_ONLY4 BIT(0xb)
135#define CLEAR_CSR_ON_READ BIT(0xc)
136#define IS_WORD_16 BIT(0xd)
137#define ENABLE_16XX_MODE BIT(0xe)
138#define HS_CHANNELS_RESERVED BIT(0xf)
139
140/* Defines for DMA Capabilities */
141#define DMA_HAS_TRANSPARENT_CAPS (0x1 << 18)
142#define DMA_HAS_CONSTANT_FILL_CAPS (0x1 << 19)
143#define DMA_HAS_DESCRIPTOR_CAPS (0x3 << 20)
144
145enum omap_reg_offsets {
146
147GCR, GSCR, GRST1, HW_ID,
148PCH2_ID, PCH0_ID, PCH1_ID, PCHG_ID,
149PCHD_ID, CAPS_0, CAPS_1, CAPS_2,
150CAPS_3, CAPS_4, PCH2_SR, PCH0_SR,
151PCH1_SR, PCHD_SR, REVISION, IRQSTATUS_L0,
152IRQSTATUS_L1, IRQSTATUS_L2, IRQSTATUS_L3, IRQENABLE_L0,
153IRQENABLE_L1, IRQENABLE_L2, IRQENABLE_L3, SYSSTATUS,
154OCP_SYSCONFIG,
155
156/* omap1+ specific */
157CPC, CCR2, LCH_CTRL,
158
159/* Common registers for all omap's */
160CSDP, CCR, CICR, CSR,
161CEN, CFN, CSFI, CSEI,
162CSAC, CDAC, CDEI,
163CDFI, CLNK_CTRL,
164
165/* Channel specific registers */
166CSSA, CDSA, COLOR,
167CCEN, CCFN,
168
169/* omap3630 and omap4 specific */
170CDP, CNDP, CCDN,
171
172};
173
174enum omap_dma_burst_mode {
175 OMAP_DMA_DATA_BURST_DIS = 0,
176 OMAP_DMA_DATA_BURST_4,
177 OMAP_DMA_DATA_BURST_8,
178 OMAP_DMA_DATA_BURST_16,
179};
180
181enum end_type {
182 OMAP_DMA_LITTLE_ENDIAN = 0,
183 OMAP_DMA_BIG_ENDIAN
184};
185
186enum omap_dma_color_mode {
187 OMAP_DMA_COLOR_DIS = 0,
188 OMAP_DMA_CONSTANT_FILL,
189 OMAP_DMA_TRANSPARENT_COPY
190};
191
192enum omap_dma_write_mode {
193 OMAP_DMA_WRITE_NON_POSTED = 0,
194 OMAP_DMA_WRITE_POSTED,
195 OMAP_DMA_WRITE_LAST_NON_POSTED
196};
197
198enum omap_dma_channel_mode {
199 OMAP_DMA_LCH_2D = 0,
200 OMAP_DMA_LCH_G,
201 OMAP_DMA_LCH_P,
202 OMAP_DMA_LCH_PD
203};
204
205struct omap_dma_channel_params {
206 int data_type; /* data type 8,16,32 */
207 int elem_count; /* number of elements in a frame */
208 int frame_count; /* number of frames in a element */
209
210 int src_port; /* Only on OMAP1 REVISIT: Is this needed? */
211 int src_amode; /* constant, post increment, indexed,
212 double indexed */
213 unsigned long src_start; /* source address : physical */
214 int src_ei; /* source element index */
215 int src_fi; /* source frame index */
216
217 int dst_port; /* Only on OMAP1 REVISIT: Is this needed? */
218 int dst_amode; /* constant, post increment, indexed,
219 double indexed */
220 unsigned long dst_start; /* source address : physical */
221 int dst_ei; /* source element index */
222 int dst_fi; /* source frame index */
223
224 int trigger; /* trigger attached if the channel is
225 synchronized */
226 int sync_mode; /* sycn on element, frame , block or packet */
227 int src_or_dst_synch; /* source synch(1) or destination synch(0) */
228
229 int ie; /* interrupt enabled */
230
231 unsigned char read_prio;/* read priority */
232 unsigned char write_prio;/* write priority */
233
234#ifndef CONFIG_ARCH_OMAP1
235 enum omap_dma_burst_mode burst_mode; /* Burst mode 4/8/16 words */
236#endif
237};
238
239struct omap_dma_lch {
240 int next_lch;
241 int dev_id;
242 u16 saved_csr;
243 u16 enabled_irqs;
244 const char *dev_name;
245 void (*callback)(int lch, u16 ch_status, void *data);
246 void *data;
247 long flags;
248 /* required for Dynamic chaining */
249 int prev_linked_ch;
250 int next_linked_ch;
251 int state;
252 int chain_id;
253 int status;
254};
255
256struct omap_dma_dev_attr {
257 u32 dev_caps;
258 u16 lch_count;
259 u16 chan_count;
260 struct omap_dma_lch *chan;
261};
262
263/* System DMA platform data structure */
264struct omap_system_dma_plat_info {
265 struct omap_dma_dev_attr *dma_attr;
266 u32 errata;
267 void (*disable_irq_lch)(int lch);
268 void (*show_dma_caps)(void);
269 void (*clear_lch_regs)(int lch);
270 void (*clear_dma)(int lch);
271 void (*dma_write)(u32 val, int reg, int lch);
272 u32 (*dma_read)(int reg, int lch);
273};
274
275#ifdef CONFIG_ARCH_OMAP2PLUS
276#define dma_omap2plus() 1
277#else
278#define dma_omap2plus() 0
279#endif
280#define dma_omap1() (!dma_omap2plus())
281#define dma_omap15xx() ((dma_omap1() && (d->dev_caps & ENABLE_1510_MODE)))
282#define dma_omap16xx() ((dma_omap1() && (d->dev_caps & ENABLE_16XX_MODE)))
283
284extern void omap_set_dma_priority(int lch, int dst_port, int priority);
285extern int omap_request_dma(int dev_id, const char *dev_name,
286 void (*callback)(int lch, u16 ch_status, void *data),
287 void *data, int *dma_ch);
288extern void omap_enable_dma_irq(int ch, u16 irq_bits);
289extern void omap_disable_dma_irq(int ch, u16 irq_bits);
290extern void omap_free_dma(int ch);
291extern void omap_start_dma(int lch);
292extern void omap_stop_dma(int lch);
293extern void omap_set_dma_transfer_params(int lch, int data_type,
294 int elem_count, int frame_count,
295 int sync_mode,
296 int dma_trigger, int src_or_dst_synch);
297extern void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode,
298 u32 color);
299extern void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode);
300extern void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode);
301
302extern void omap_set_dma_src_params(int lch, int src_port, int src_amode,
303 unsigned long src_start,
304 int src_ei, int src_fi);
305extern void omap_set_dma_src_index(int lch, int eidx, int fidx);
306extern void omap_set_dma_src_data_pack(int lch, int enable);
307extern void omap_set_dma_src_burst_mode(int lch,
308 enum omap_dma_burst_mode burst_mode);
309
310extern void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
311 unsigned long dest_start,
312 int dst_ei, int dst_fi);
313extern void omap_set_dma_dest_index(int lch, int eidx, int fidx);
314extern void omap_set_dma_dest_data_pack(int lch, int enable);
315extern void omap_set_dma_dest_burst_mode(int lch,
316 enum omap_dma_burst_mode burst_mode);
317
318extern void omap_set_dma_params(int lch,
319 struct omap_dma_channel_params *params);
320
321extern void omap_dma_link_lch(int lch_head, int lch_queue);
322extern void omap_dma_unlink_lch(int lch_head, int lch_queue);
323
324extern int omap_set_dma_callback(int lch,
325 void (*callback)(int lch, u16 ch_status, void *data),
326 void *data);
327extern dma_addr_t omap_get_dma_src_pos(int lch);
328extern dma_addr_t omap_get_dma_dst_pos(int lch);
329extern void omap_clear_dma(int lch);
330extern int omap_get_dma_active_status(int lch);
331extern int omap_dma_running(void);
332extern void omap_dma_set_global_params(int arb_rate, int max_fifo_depth,
333 int tparams);
334extern int omap_dma_set_prio_lch(int lch, unsigned char read_prio,
335 unsigned char write_prio);
336extern void omap_set_dma_dst_endian_type(int lch, enum end_type etype);
337extern void omap_set_dma_src_endian_type(int lch, enum end_type etype);
338extern int omap_get_dma_index(int lch, int *ei, int *fi);
339
340void omap_dma_global_context_save(void);
341void omap_dma_global_context_restore(void);
342
343extern void omap_dma_disable_irq(int lch);
344
345/* Chaining APIs */
346#ifndef CONFIG_ARCH_OMAP1
347extern int omap_request_dma_chain(int dev_id, const char *dev_name,
348 void (*callback) (int lch, u16 ch_status,
349 void *data),
350 int *chain_id, int no_of_chans,
351 int chain_mode,
352 struct omap_dma_channel_params params);
353extern int omap_free_dma_chain(int chain_id);
354extern int omap_dma_chain_a_transfer(int chain_id, int src_start,
355 int dest_start, int elem_count,
356 int frame_count, void *callbk_data);
357extern int omap_start_dma_chain_transfers(int chain_id);
358extern int omap_stop_dma_chain_transfers(int chain_id);
359extern int omap_get_dma_chain_index(int chain_id, int *ei, int *fi);
360extern int omap_get_dma_chain_dst_pos(int chain_id);
361extern int omap_get_dma_chain_src_pos(int chain_id);
362
363extern int omap_modify_dma_chain_params(int chain_id,
364 struct omap_dma_channel_params params);
365extern int omap_dma_chain_status(int chain_id);
366#endif
367
368#if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_FB_OMAP)
369#include <mach/lcd_dma.h>
370#else
371static inline int omap_lcd_dma_running(void)
372{
373 return 0;
374}
375#endif
376
377#endif /* __ASM_ARCH_DMA_H */
diff --git a/arch/arm/plat-samsung/include/plat/pm.h b/arch/arm/plat-samsung/include/plat/pm.h
index 61fc53740fbd..887a0c954379 100644
--- a/arch/arm/plat-samsung/include/plat/pm.h
+++ b/arch/arm/plat-samsung/include/plat/pm.h
@@ -107,10 +107,12 @@ extern void s3c_pm_do_restore(struct sleep_save *ptr, int count);
107extern void s3c_pm_do_restore_core(struct sleep_save *ptr, int count); 107extern void s3c_pm_do_restore_core(struct sleep_save *ptr, int count);
108 108
109#ifdef CONFIG_PM 109#ifdef CONFIG_PM
110extern int s3c_irq_wake(struct irq_data *data, unsigned int state);
110extern int s3c_irqext_wake(struct irq_data *data, unsigned int state); 111extern int s3c_irqext_wake(struct irq_data *data, unsigned int state);
111extern int s3c24xx_irq_suspend(void); 112extern int s3c24xx_irq_suspend(void);
112extern void s3c24xx_irq_resume(void); 113extern void s3c24xx_irq_resume(void);
113#else 114#else
115#define s3c_irq_wake NULL
114#define s3c_irqext_wake NULL 116#define s3c_irqext_wake NULL
115#define s3c24xx_irq_suspend NULL 117#define s3c24xx_irq_suspend NULL
116#define s3c24xx_irq_resume NULL 118#define s3c24xx_irq_resume NULL
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-14 22:10:58 -0500