aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/mach-mvebu/Makefile2
-rw-r--r--arch/arm/mach-mvebu/armada-370-xp.c4
-rw-r--r--arch/arm/mach-mvebu/irq-armada-370-xp.c294
3 files changed, 3 insertions, 297 deletions
diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile
index da93bcbc74c1..c3be068f1c96 100644
--- a/arch/arm/mach-mvebu/Makefile
+++ b/arch/arm/mach-mvebu/Makefile
@@ -5,6 +5,6 @@ AFLAGS_coherency_ll.o := -Wa,-march=armv7-a
5 5
6obj-y += system-controller.o 6obj-y += system-controller.o
7obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o 7obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o
8obj-$(CONFIG_ARCH_MVEBU) += addr-map.o coherency.o coherency_ll.o pmsu.o irq-armada-370-xp.o 8obj-$(CONFIG_ARCH_MVEBU) += addr-map.o coherency.o coherency_ll.o pmsu.o
9obj-$(CONFIG_SMP) += platsmp.o headsmp.o 9obj-$(CONFIG_SMP) += platsmp.o headsmp.o
10obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o 10obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c
index c1bbfa74e646..433e8c5343b2 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.c
+++ b/arch/arm/mach-mvebu/armada-370-xp.c
@@ -19,6 +19,7 @@
19#include <linux/time-armada-370-xp.h> 19#include <linux/time-armada-370-xp.h>
20#include <linux/clk/mvebu.h> 20#include <linux/clk/mvebu.h>
21#include <linux/dma-mapping.h> 21#include <linux/dma-mapping.h>
22#include <linux/irqchip.h>
22#include <asm/hardware/cache-l2x0.h> 23#include <asm/hardware/cache-l2x0.h>
23#include <asm/mach/arch.h> 24#include <asm/mach/arch.h>
24#include <asm/mach/map.h> 25#include <asm/mach/map.h>
@@ -77,8 +78,7 @@ DT_MACHINE_START(ARMADA_XP_DT, "Marvell Armada 370/XP (Device Tree)")
77 .init_machine = armada_370_xp_dt_init, 78 .init_machine = armada_370_xp_dt_init,
78 .map_io = armada_370_xp_map_io, 79 .map_io = armada_370_xp_map_io,
79 .init_early = armada_370_xp_init_early, 80 .init_early = armada_370_xp_init_early,
80 .init_irq = armada_370_xp_init_irq, 81 .init_irq = irqchip_init,
81 .handle_irq = armada_370_xp_handle_irq,
82 .init_time = armada_370_xp_timer_and_clk_init, 82 .init_time = armada_370_xp_timer_and_clk_init,
83 .restart = mvebu_restart, 83 .restart = mvebu_restart,
84 .dt_compat = armada_370_xp_dt_compat, 84 .dt_compat = armada_370_xp_dt_compat,
diff --git a/arch/arm/mach-mvebu/irq-armada-370-xp.c b/arch/arm/mach-mvebu/irq-armada-370-xp.c
deleted file mode 100644
index f6699f303e6d..000000000000
--- a/arch/arm/mach-mvebu/irq-armada-370-xp.c
+++ /dev/null
@@ -1,294 +0,0 @@
1/*
2 * Marvell Armada 370 and Armada XP SoC IRQ handling
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * Ben Dooks <ben.dooks@codethink.co.uk>
10 *
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
14 */
15
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/init.h>
19#include <linux/irq.h>
20#include <linux/interrupt.h>
21#include <linux/io.h>
22#include <linux/of_address.h>
23#include <linux/of_irq.h>
24#include <linux/irqdomain.h>
25#include <asm/mach/arch.h>
26#include <asm/exception.h>
27#include <asm/smp_plat.h>
28
29/* Interrupt Controller Registers Map */
30#define ARMADA_370_XP_INT_SET_MASK_OFFS (0x48)
31#define ARMADA_370_XP_INT_CLEAR_MASK_OFFS (0x4C)
32
33#define ARMADA_370_XP_INT_CONTROL (0x00)
34#define ARMADA_370_XP_INT_SET_ENABLE_OFFS (0x30)
35#define ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS (0x34)
36#define ARMADA_370_XP_INT_SOURCE_CTL(irq) (0x100 + irq*4)
37
38#define ARMADA_370_XP_CPU_INTACK_OFFS (0x44)
39
40#define ARMADA_370_XP_SW_TRIG_INT_OFFS (0x4)
41#define ARMADA_370_XP_IN_DRBEL_MSK_OFFS (0xc)
42#define ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS (0x8)
43
44#define ARMADA_370_XP_MAX_PER_CPU_IRQS (28)
45
46#define ARMADA_370_XP_TIMER0_PER_CPU_IRQ (5)
47
48#define ACTIVE_DOORBELLS (8)
49
50static DEFINE_RAW_SPINLOCK(irq_controller_lock);
51
52static void __iomem *per_cpu_int_base;
53static void __iomem *main_int_base;
54static struct irq_domain *armada_370_xp_mpic_domain;
55
56/*
57 * In SMP mode:
58 * For shared global interrupts, mask/unmask global enable bit
59 * For CPU interrtups, mask/unmask the calling CPU's bit
60 */
61static void armada_370_xp_irq_mask(struct irq_data *d)
62{
63#ifdef CONFIG_SMP
64 irq_hw_number_t hwirq = irqd_to_hwirq(d);
65
66 if (hwirq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
67 writel(hwirq, main_int_base +
68 ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
69 else
70 writel(hwirq, per_cpu_int_base +
71 ARMADA_370_XP_INT_SET_MASK_OFFS);
72#else
73 writel(irqd_to_hwirq(d),
74 per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS);
75#endif
76}
77
78static void armada_370_xp_irq_unmask(struct irq_data *d)
79{
80#ifdef CONFIG_SMP
81 irq_hw_number_t hwirq = irqd_to_hwirq(d);
82
83 if (hwirq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
84 writel(hwirq, main_int_base +
85 ARMADA_370_XP_INT_SET_ENABLE_OFFS);
86 else
87 writel(hwirq, per_cpu_int_base +
88 ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
89#else
90 writel(irqd_to_hwirq(d),
91 per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
92#endif
93}
94
95#ifdef CONFIG_SMP
96static int armada_xp_set_affinity(struct irq_data *d,
97 const struct cpumask *mask_val, bool force)
98{
99 unsigned long reg;
100 unsigned long new_mask = 0;
101 unsigned long online_mask = 0;
102 unsigned long count = 0;
103 irq_hw_number_t hwirq = irqd_to_hwirq(d);
104 int cpu;
105
106 for_each_cpu(cpu, mask_val) {
107 new_mask |= 1 << cpu_logical_map(cpu);
108 count++;
109 }
110
111 /*
112 * Forbid mutlicore interrupt affinity
113 * This is required since the MPIC HW doesn't limit
114 * several CPUs from acknowledging the same interrupt.
115 */
116 if (count > 1)
117 return -EINVAL;
118
119 for_each_cpu(cpu, cpu_online_mask)
120 online_mask |= 1 << cpu_logical_map(cpu);
121
122 raw_spin_lock(&irq_controller_lock);
123
124 reg = readl(main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
125 reg = (reg & (~online_mask)) | new_mask;
126 writel(reg, main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
127
128 raw_spin_unlock(&irq_controller_lock);
129
130 return 0;
131}
132#endif
133
134static struct irq_chip armada_370_xp_irq_chip = {
135 .name = "armada_370_xp_irq",
136 .irq_mask = armada_370_xp_irq_mask,
137 .irq_mask_ack = armada_370_xp_irq_mask,
138 .irq_unmask = armada_370_xp_irq_unmask,
139#ifdef CONFIG_SMP
140 .irq_set_affinity = armada_xp_set_affinity,
141#endif
142};
143
144static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
145 unsigned int virq, irq_hw_number_t hw)
146{
147 armada_370_xp_irq_mask(irq_get_irq_data(virq));
148 writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS);
149 irq_set_status_flags(virq, IRQ_LEVEL);
150
151 if (hw == ARMADA_370_XP_TIMER0_PER_CPU_IRQ) {
152 irq_set_percpu_devid(virq);
153 irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
154 handle_percpu_devid_irq);
155
156 } else {
157 irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
158 handle_level_irq);
159 }
160 set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
161
162 return 0;
163}
164
165#ifdef CONFIG_SMP
166void armada_mpic_send_doorbell(const struct cpumask *mask, unsigned int irq)
167{
168 int cpu;
169 unsigned long map = 0;
170
171 /* Convert our logical CPU mask into a physical one. */
172 for_each_cpu(cpu, mask)
173 map |= 1 << cpu_logical_map(cpu);
174
175 /*
176 * Ensure that stores to Normal memory are visible to the
177 * other CPUs before issuing the IPI.
178 */
179 dsb();
180
181 /* submit softirq */
182 writel((map << 8) | irq, main_int_base +
183 ARMADA_370_XP_SW_TRIG_INT_OFFS);
184}
185
186void armada_xp_mpic_smp_cpu_init(void)
187{
188 /* Clear pending IPIs */
189 writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
190
191 /* Enable first 8 IPIs */
192 writel((1 << ACTIVE_DOORBELLS) - 1, per_cpu_int_base +
193 ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
194
195 /* Unmask IPI interrupt */
196 writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
197}
198#endif /* CONFIG_SMP */
199
200static struct irq_domain_ops armada_370_xp_mpic_irq_ops = {
201 .map = armada_370_xp_mpic_irq_map,
202 .xlate = irq_domain_xlate_onecell,
203};
204
205static int __init armada_370_xp_mpic_of_init(struct device_node *node,
206 struct device_node *parent)
207{
208 u32 control;
209
210 main_int_base = of_iomap(node, 0);
211 per_cpu_int_base = of_iomap(node, 1);
212
213 BUG_ON(!main_int_base);
214 BUG_ON(!per_cpu_int_base);
215
216 control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
217
218 armada_370_xp_mpic_domain =
219 irq_domain_add_linear(node, (control >> 2) & 0x3ff,
220 &armada_370_xp_mpic_irq_ops, NULL);
221
222 if (!armada_370_xp_mpic_domain)
223 panic("Unable to add Armada_370_Xp MPIC irq domain (DT)\n");
224
225 irq_set_default_host(armada_370_xp_mpic_domain);
226
227#ifdef CONFIG_SMP
228 armada_xp_mpic_smp_cpu_init();
229
230 /*
231 * Set the default affinity from all CPUs to the boot cpu.
232 * This is required since the MPIC doesn't limit several CPUs
233 * from acknowledging the same interrupt.
234 */
235 cpumask_clear(irq_default_affinity);
236 cpumask_set_cpu(smp_processor_id(), irq_default_affinity);
237
238#endif
239
240 return 0;
241}
242
243asmlinkage void __exception_irq_entry armada_370_xp_handle_irq(struct pt_regs
244 *regs)
245{
246 u32 irqstat, irqnr;
247
248 do {
249 irqstat = readl_relaxed(per_cpu_int_base +
250 ARMADA_370_XP_CPU_INTACK_OFFS);
251 irqnr = irqstat & 0x3FF;
252
253 if (irqnr > 1022)
254 break;
255
256 if (irqnr > 0) {
257 irqnr = irq_find_mapping(armada_370_xp_mpic_domain,
258 irqnr);
259 handle_IRQ(irqnr, regs);
260 continue;
261 }
262#ifdef CONFIG_SMP
263 /* IPI Handling */
264 if (irqnr == 0) {
265 u32 ipimask, ipinr;
266
267 ipimask = readl_relaxed(per_cpu_int_base +
268 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
269 & 0xFF;
270
271 writel(0x0, per_cpu_int_base +
272 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
273
274 /* Handle all pending doorbells */
275 for (ipinr = 0; ipinr < ACTIVE_DOORBELLS; ipinr++) {
276 if (ipimask & (0x1 << ipinr))
277 handle_IPI(ipinr, regs);
278 }
279 continue;
280 }
281#endif
282
283 } while (1);
284}
285
286static const struct of_device_id mpic_of_match[] __initconst = {
287 {.compatible = "marvell,mpic", .data = armada_370_xp_mpic_of_init},
288 {},
289};
290
291void __init armada_370_xp_init_irq(void)
292{
293 of_irq_init(mpic_of_match);
294}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-01 08:21:48 -0400