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-rw-r--r--arch/arm/Kconfig2
-rw-r--r--arch/arm/Kconfig.debug158
-rw-r--r--arch/arm/configs/at91cap9_defconfig108
-rw-r--r--arch/arm/include/asm/system.h1
-rw-r--r--arch/arm/kernel/process.c27
-rw-r--r--arch/arm/mach-at91/Kconfig26
-rw-r--r--arch/arm/mach-at91/Makefile4
-rw-r--r--arch/arm/mach-at91/Makefile.boot6
-rw-r--r--arch/arm/mach-at91/at91cap9.c396
-rw-r--r--arch/arm/mach-at91/at91cap9_devices.c1273
-rw-r--r--arch/arm/mach-at91/at91rm9200.c10
-rw-r--r--arch/arm/mach-at91/at91sam9260.c8
-rw-r--r--arch/arm/mach-at91/at91sam9261.c8
-rw-r--r--arch/arm/mach-at91/at91sam9263.c8
-rw-r--r--arch/arm/mach-at91/at91sam9263_devices.c13
-rw-r--r--arch/arm/mach-at91/at91sam9g45.c7
-rw-r--r--arch/arm/mach-at91/at91sam9g45_devices.c113
-rw-r--r--arch/arm/mach-at91/at91sam9rl.c8
-rw-r--r--arch/arm/mach-at91/at91sam9rl_devices.c8
-rw-r--r--arch/arm/mach-at91/at91x40.c12
-rw-r--r--arch/arm/mach-at91/board-cap9adk.c396
-rw-r--r--arch/arm/mach-at91/board-flexibity.c12
-rw-r--r--arch/arm/mach-at91/board-sam9m10g45ek.c80
-rw-r--r--arch/arm/mach-at91/clock.c5
-rw-r--r--arch/arm/mach-at91/generic.h1
-rw-r--r--arch/arm/mach-at91/include/mach/at91_pmc.h14
-rw-r--r--arch/arm/mach-at91/include/mach/at91cap9.h122
-rw-r--r--arch/arm/mach-at91/include/mach/at91cap9_matrix.h137
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h10
-rw-r--r--arch/arm/mach-at91/include/mach/board.h6
-rw-r--r--arch/arm/mach-at91/include/mach/cpu.h21
-rw-r--r--arch/arm/mach-at91/include/mach/hardware.h4
-rw-r--r--arch/arm/mach-at91/include/mach/system.h50
-rw-r--r--arch/arm/mach-at91/pm.c5
-rw-r--r--arch/arm/mach-at91/pm.h18
-rw-r--r--arch/arm/mach-at91/pm_slowclock.S12
-rw-r--r--arch/arm/mach-at91/setup.c17
-rw-r--r--arch/arm/mach-at91/soc.h5
-rw-r--r--arch/arm/mach-bcmring/core.c23
-rw-r--r--arch/arm/mach-bcmring/include/mach/system.h28
-rw-r--r--arch/arm/mach-clps711x/common.c16
-rw-r--r--arch/arm/mach-clps711x/include/mach/system.h35
-rw-r--r--arch/arm/mach-cns3xxx/include/mach/system.h25
-rw-r--r--arch/arm/mach-davinci/include/mach/system.h21
-rw-r--r--arch/arm/mach-dove/include/mach/system.h17
-rw-r--r--arch/arm/mach-ebsa110/core.c25
-rw-r--r--arch/arm/mach-ebsa110/include/mach/system.h37
-rw-r--r--arch/arm/mach-ep93xx/core.c46
-rw-r--r--arch/arm/mach-ep93xx/include/mach/system.h7
-rw-r--r--arch/arm/mach-exynos/common.c12
-rw-r--r--arch/arm/mach-exynos/dma.c38
-rw-r--r--arch/arm/mach-exynos/include/mach/system.h20
-rw-r--r--arch/arm/mach-footbridge/include/mach/system.h13
-rw-r--r--arch/arm/mach-gemini/Makefile2
-rw-r--r--arch/arm/mach-gemini/idle.c29
-rw-r--r--arch/arm/mach-gemini/include/mach/system.h14
-rw-r--r--arch/arm/mach-gemini/irq.c4
-rw-r--r--arch/arm/mach-h720x/common.c18
-rw-r--r--arch/arm/mach-h720x/include/mach/system.h27
-rw-r--r--arch/arm/mach-highbank/include/mach/system.h24
-rw-r--r--arch/arm/mach-imx/mach-mx31moboard.c2
-rw-r--r--arch/arm/mach-imx/mm-imx3.c52
-rw-r--r--arch/arm/mach-imx/mm-imx5.c28
-rw-r--r--arch/arm/mach-imx/pm-imx27.c3
-rw-r--r--arch/arm/mach-imx/pm-imx5.c4
-rw-r--r--arch/arm/mach-integrator/core.c70
-rw-r--r--arch/arm/mach-integrator/impd1.c9
-rw-r--r--arch/arm/mach-integrator/include/mach/system.h33
-rw-r--r--arch/arm/mach-integrator/integrator_cp.c49
-rw-r--r--arch/arm/mach-iop13xx/include/mach/system.h13
-rw-r--r--arch/arm/mach-iop32x/include/mach/system.h13
-rw-r--r--arch/arm/mach-iop33x/include/mach/system.h13
-rw-r--r--arch/arm/mach-ixp2000/include/mach/system.h14
-rw-r--r--arch/arm/mach-ixp23xx/core.c3
-rw-r--r--arch/arm/mach-ixp23xx/include/mach/system.h16
-rw-r--r--arch/arm/mach-ixp4xx/common.c6
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/system.h19
-rw-r--r--arch/arm/mach-kirkwood/include/mach/system.h17
-rw-r--r--arch/arm/mach-ks8695/include/mach/system.h27
-rw-r--r--arch/arm/mach-lpc32xx/include/mach/system.h27
-rw-r--r--arch/arm/mach-lpc32xx/phy3250.c32
-rw-r--r--arch/arm/mach-mmp/include/mach/system.h16
-rw-r--r--arch/arm/mach-msm/idle.S36
-rw-r--r--arch/arm/mach-msm/idle.c49
-rw-r--r--arch/arm/mach-msm/include/mach/system.h1
-rw-r--r--arch/arm/mach-mv78xx0/include/mach/system.h17
-rw-r--r--arch/arm/mach-mxs/devices.c8
-rw-r--r--arch/arm/mach-mxs/devices/amba-duart.c2
-rw-r--r--arch/arm/mach-mxs/include/mach/system.h25
-rw-r--r--arch/arm/mach-mxs/pm.c3
-rw-r--r--arch/arm/mach-netx/fb.c13
-rw-r--r--arch/arm/mach-netx/include/mach/system.h28
-rw-r--r--arch/arm/mach-nomadik/board-nhk8815.c17
-rw-r--r--arch/arm/mach-nomadik/cpu-8815.c9
-rw-r--r--arch/arm/mach-nomadik/include/mach/system.h32
-rw-r--r--arch/arm/mach-omap1/include/mach/system.h5
-rw-r--r--arch/arm/mach-omap1/pm.c19
-rw-r--r--arch/arm/mach-omap2/emu.c26
-rw-r--r--arch/arm/mach-omap2/include/mach/system.h5
-rw-r--r--arch/arm/mach-omap2/pm24xx.c4
-rw-r--r--arch/arm/mach-omap2/pm34xx.c6
-rw-r--r--arch/arm/mach-omap2/pm44xx.c8
-rw-r--r--arch/arm/mach-omap2/prm_common.c1
-rw-r--r--arch/arm/mach-orion5x/include/mach/system.h19
-rw-r--r--arch/arm/mach-picoxcell/include/mach/system.h26
-rw-r--r--arch/arm/mach-pnx4008/include/mach/system.h29
-rw-r--r--arch/arm/mach-prima2/include/mach/system.h17
-rw-r--r--arch/arm/mach-pxa/include/mach/system.h15
-rw-r--r--arch/arm/mach-realview/core.h20
-rw-r--r--arch/arm/mach-realview/include/mach/irqs-pb1176.h2
-rw-r--r--arch/arm/mach-realview/include/mach/system.h33
-rw-r--r--arch/arm/mach-realview/realview_eb.c78
-rw-r--r--arch/arm/mach-realview/realview_pb1176.c78
-rw-r--r--arch/arm/mach-realview/realview_pb11mp.c78
-rw-r--r--arch/arm/mach-realview/realview_pba8.c78
-rw-r--r--arch/arm/mach-realview/realview_pbx.c78
-rw-r--r--arch/arm/mach-rpc/include/mach/system.h13
-rw-r--r--arch/arm/mach-s3c2410/include/mach/system.h54
-rw-r--r--arch/arm/mach-s3c2412/s3c2412.c4
-rw-r--r--arch/arm/mach-s3c2416/s3c2416.c3
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/system.h19
-rw-r--r--arch/arm/mach-s5p64x0/common.c15
-rw-r--r--arch/arm/mach-s5p64x0/dma.c22
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/system.h21
-rw-r--r--arch/arm/mach-s5pc100/common.c12
-rw-r--r--arch/arm/mach-s5pc100/dma.c38
-rw-r--r--arch/arm/mach-s5pc100/include/mach/system.h19
-rw-r--r--arch/arm/mach-s5pv210/common.c12
-rw-r--r--arch/arm/mach-s5pv210/dma.c38
-rw-r--r--arch/arm/mach-s5pv210/include/mach/system.h21
-rw-r--r--arch/arm/mach-sa1100/include/mach/system.h9
-rw-r--r--arch/arm/mach-shark/core.c6
-rw-r--r--arch/arm/mach-shark/include/mach/system.h13
-rw-r--r--arch/arm/mach-shmobile/include/mach/system.h5
-rw-r--r--arch/arm/mach-spear3xx/include/mach/system.h19
-rw-r--r--arch/arm/mach-spear3xx/spear300.c14
-rw-r--r--arch/arm/mach-spear3xx/spear3xx.c27
-rw-r--r--arch/arm/mach-spear6xx/include/mach/system.h19
-rw-r--r--arch/arm/mach-spear6xx/spear6xx.c10
-rw-r--r--arch/arm/mach-tegra/common.c3
-rw-r--r--arch/arm/mach-tegra/include/mach/system.h28
-rw-r--r--arch/arm/mach-u300/core.c85
-rw-r--r--arch/arm/mach-u300/include/mach/system.h14
-rw-r--r--arch/arm/mach-ux500/devices-common.c13
-rw-r--r--arch/arm/mach-ux500/include/mach/system.h20
-rw-r--r--arch/arm/mach-versatile/core.c70
-rw-r--r--arch/arm/mach-versatile/core.h20
-rw-r--r--arch/arm/mach-versatile/include/mach/system.h33
-rw-r--r--arch/arm/mach-versatile/versatile_pb.c18
-rw-r--r--arch/arm/mach-vexpress/core.h17
-rw-r--r--arch/arm/mach-vexpress/ct-ca9x4.c8
-rw-r--r--arch/arm/mach-vexpress/include/mach/ct-ca9x4.h2
-rw-r--r--arch/arm/mach-vexpress/include/mach/system.h33
-rw-r--r--arch/arm/mach-vexpress/v2m.c20
-rw-r--r--arch/arm/mach-vt8500/include/mach/system.h5
-rw-r--r--arch/arm/mach-w90x900/dev.c1
-rw-r--r--arch/arm/mach-w90x900/include/mach/system.h19
-rw-r--r--arch/arm/mach-zynq/include/mach/system.h23
-rw-r--r--arch/arm/plat-mxc/audmux-v2.c8
-rw-r--r--arch/arm/plat-mxc/devices/platform-ahci-imx.c16
-rw-r--r--arch/arm/plat-mxc/epit.c2
-rw-r--r--arch/arm/plat-mxc/include/mach/system.h25
-rw-r--r--arch/arm/plat-mxc/pwm.c4
-rw-r--r--arch/arm/plat-mxc/system.c2
-rw-r--r--arch/arm/plat-mxc/time.c2
-rw-r--r--arch/arm/plat-omap/include/plat/system.h15
-rw-r--r--arch/arm/plat-s3c24xx/cpu.c27
-rw-r--r--arch/arm/plat-spear/include/plat/system.h26
168 files changed, 1010 insertions, 4885 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index a48aecc17eac..92c9c79c140c 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -324,7 +324,7 @@ config ARCH_AT91
324 select CLKDEV_LOOKUP 324 select CLKDEV_LOOKUP
325 help 325 help
326 This enables support for systems based on the Atmel AT91RM9200, 326 This enables support for systems based on the Atmel AT91RM9200,
327 AT91SAM9 and AT91CAP9 processors. 327 AT91SAM9 processors.
328 328
329config ARCH_BCMRING 329config ARCH_BCMRING
330 bool "Broadcom BCMRING" 330 bool "Broadcom BCMRING"
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index e0d236d7ff73..b895a2a92da8 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -81,47 +81,14 @@ choice
81 prompt "Kernel low-level debugging port" 81 prompt "Kernel low-level debugging port"
82 depends on DEBUG_LL 82 depends on DEBUG_LL
83 83
84 config DEBUG_LL_UART_NONE
85 bool "No low-level debugging UART"
86 help
87 Say Y here if your platform doesn't provide a UART option
88 below. This relies on your platform choosing the right UART
89 definition internally in order for low-level debugging to
90 work.
91
92 config DEBUG_ICEDCC
93 bool "Kernel low-level debugging via EmbeddedICE DCC channel"
94 help
95 Say Y here if you want the debug print routines to direct
96 their output to the EmbeddedICE macrocell's DCC channel using
97 co-processor 14. This is known to work on the ARM9 style ICE
98 channel and on the XScale with the PEEDI.
99
100 Note that the system will appear to hang during boot if there
101 is nothing connected to read from the DCC.
102
103 config AT91_DEBUG_LL_DBGU0 84 config AT91_DEBUG_LL_DBGU0
104 bool "Kernel low-level debugging on rm9200, 9260/9g20, 9261/9g10 and 9rl" 85 bool "Kernel low-level debugging on rm9200, 9260/9g20, 9261/9g10 and 9rl"
105 depends on HAVE_AT91_DBGU0 86 depends on HAVE_AT91_DBGU0
106 87
107 config AT91_DEBUG_LL_DBGU1 88 config AT91_DEBUG_LL_DBGU1
108 bool "Kernel low-level debugging on 9263, 9g45 and cap9" 89 bool "Kernel low-level debugging on 9263 and 9g45"
109 depends on HAVE_AT91_DBGU1 90 depends on HAVE_AT91_DBGU1
110 91
111 config DEBUG_FOOTBRIDGE_COM1
112 bool "Kernel low-level debugging messages via footbridge 8250 at PCI COM1"
113 depends on FOOTBRIDGE
114 help
115 Say Y here if you want the debug print routines to direct
116 their output to the 8250 at PCI COM1.
117
118 config DEBUG_DC21285_PORT
119 bool "Kernel low-level debugging messages via footbridge serial port"
120 depends on FOOTBRIDGE
121 help
122 Say Y here if you want the debug print routines to direct
123 their output to the serial port in the DC21285 (Footbridge).
124
125 config DEBUG_CLPS711X_UART1 92 config DEBUG_CLPS711X_UART1
126 bool "Kernel low-level debugging messages via UART1" 93 bool "Kernel low-level debugging messages via UART1"
127 depends on ARCH_CLPS711X 94 depends on ARCH_CLPS711X
@@ -136,6 +103,20 @@ choice
136 Say Y here if you want the debug print routines to direct 103 Say Y here if you want the debug print routines to direct
137 their output to the second serial port on these devices. 104 their output to the second serial port on these devices.
138 105
106 config DEBUG_DC21285_PORT
107 bool "Kernel low-level debugging messages via footbridge serial port"
108 depends on FOOTBRIDGE
109 help
110 Say Y here if you want the debug print routines to direct
111 their output to the serial port in the DC21285 (Footbridge).
112
113 config DEBUG_FOOTBRIDGE_COM1
114 bool "Kernel low-level debugging messages via footbridge 8250 at PCI COM1"
115 depends on FOOTBRIDGE
116 help
117 Say Y here if you want the debug print routines to direct
118 their output to the 8250 at PCI COM1.
119
139 config DEBUG_HIGHBANK_UART 120 config DEBUG_HIGHBANK_UART
140 bool "Kernel low-level debugging messages via Highbank UART" 121 bool "Kernel low-level debugging messages via Highbank UART"
141 depends on ARCH_HIGHBANK 122 depends on ARCH_HIGHBANK
@@ -206,38 +187,42 @@ choice
206 Say Y here if you want kernel low-level debugging support 187 Say Y here if you want kernel low-level debugging support
207 on i.MX6Q. 188 on i.MX6Q.
208 189
209 config DEBUG_S3C_UART0 190 config DEBUG_MSM_UART1
210 depends on PLAT_SAMSUNG 191 bool "Kernel low-level debugging messages via MSM UART1"
211 bool "Use S3C UART 0 for low-level debug" 192 depends on ARCH_MSM7X00A || ARCH_MSM7X30 || ARCH_QSD8X50
212 help 193 help
213 Say Y here if you want the debug print routines to direct 194 Say Y here if you want the debug print routines to direct
214 their output to UART 0. The port must have been initialised 195 their output to the first serial port on MSM devices.
215 by the boot-loader before use.
216
217 The uncompressor code port configuration is now handled
218 by CONFIG_S3C_LOWLEVEL_UART_PORT.
219 196
220 config DEBUG_S3C_UART1 197 config DEBUG_MSM_UART2
221 depends on PLAT_SAMSUNG 198 bool "Kernel low-level debugging messages via MSM UART2"
222 bool "Use S3C UART 1 for low-level debug" 199 depends on ARCH_MSM7X00A || ARCH_MSM7X30 || ARCH_QSD8X50
223 help 200 help
224 Say Y here if you want the debug print routines to direct 201 Say Y here if you want the debug print routines to direct
225 their output to UART 1. The port must have been initialised 202 their output to the second serial port on MSM devices.
226 by the boot-loader before use.
227 203
228 The uncompressor code port configuration is now handled 204 config DEBUG_MSM_UART3
229 by CONFIG_S3C_LOWLEVEL_UART_PORT. 205 bool "Kernel low-level debugging messages via MSM UART3"
206 depends on ARCH_MSM7X00A || ARCH_MSM7X30 || ARCH_QSD8X50
207 help
208 Say Y here if you want the debug print routines to direct
209 their output to the third serial port on MSM devices.
230 210
231 config DEBUG_S3C_UART2 211 config DEBUG_MSM8660_UART
232 depends on PLAT_SAMSUNG 212 bool "Kernel low-level debugging messages via MSM 8660 UART"
233 bool "Use S3C UART 2 for low-level debug" 213 depends on ARCH_MSM8X60
214 select MSM_HAS_DEBUG_UART_HS
234 help 215 help
235 Say Y here if you want the debug print routines to direct 216 Say Y here if you want the debug print routines to direct
236 their output to UART 2. The port must have been initialised 217 their output to the serial port on MSM 8660 devices.
237 by the boot-loader before use.
238 218
239 The uncompressor code port configuration is now handled 219 config DEBUG_MSM8960_UART
240 by CONFIG_S3C_LOWLEVEL_UART_PORT. 220 bool "Kernel low-level debugging messages via MSM 8960 UART"
221 depends on ARCH_MSM8960
222 select MSM_HAS_DEBUG_UART_HS
223 help
224 Say Y here if you want the debug print routines to direct
225 their output to the serial port on MSM 8960 devices.
241 226
242 config DEBUG_REALVIEW_STD_PORT 227 config DEBUG_REALVIEW_STD_PORT
243 bool "RealView Default UART" 228 bool "RealView Default UART"
@@ -255,42 +240,57 @@ choice
255 their output to the standard serial port on the RealView 240 their output to the standard serial port on the RealView
256 PB1176 platform. 241 PB1176 platform.
257 242
258 config DEBUG_MSM_UART1 243 config DEBUG_S3C_UART0
259 bool "Kernel low-level debugging messages via MSM UART1" 244 depends on PLAT_SAMSUNG
260 depends on ARCH_MSM7X00A || ARCH_MSM7X30 || ARCH_QSD8X50 245 bool "Use S3C UART 0 for low-level debug"
261 help 246 help
262 Say Y here if you want the debug print routines to direct 247 Say Y here if you want the debug print routines to direct
263 their output to the first serial port on MSM devices. 248 their output to UART 0. The port must have been initialised
249 by the boot-loader before use.
264 250
265 config DEBUG_MSM_UART2 251 The uncompressor code port configuration is now handled
266 bool "Kernel low-level debugging messages via MSM UART2" 252 by CONFIG_S3C_LOWLEVEL_UART_PORT.
267 depends on ARCH_MSM7X00A || ARCH_MSM7X30 || ARCH_QSD8X50 253
254 config DEBUG_S3C_UART1
255 depends on PLAT_SAMSUNG
256 bool "Use S3C UART 1 for low-level debug"
268 help 257 help
269 Say Y here if you want the debug print routines to direct 258 Say Y here if you want the debug print routines to direct
270 their output to the second serial port on MSM devices. 259 their output to UART 1. The port must have been initialised
260 by the boot-loader before use.
271 261
272 config DEBUG_MSM_UART3 262 The uncompressor code port configuration is now handled
273 bool "Kernel low-level debugging messages via MSM UART3" 263 by CONFIG_S3C_LOWLEVEL_UART_PORT.
274 depends on ARCH_MSM7X00A || ARCH_MSM7X30 || ARCH_QSD8X50 264
265 config DEBUG_S3C_UART2
266 depends on PLAT_SAMSUNG
267 bool "Use S3C UART 2 for low-level debug"
275 help 268 help
276 Say Y here if you want the debug print routines to direct 269 Say Y here if you want the debug print routines to direct
277 their output to the third serial port on MSM devices. 270 their output to UART 2. The port must have been initialised
271 by the boot-loader before use.
278 272
279 config DEBUG_MSM8660_UART 273 The uncompressor code port configuration is now handled
280 bool "Kernel low-level debugging messages via MSM 8660 UART" 274 by CONFIG_S3C_LOWLEVEL_UART_PORT.
281 depends on ARCH_MSM8X60 275
282 select MSM_HAS_DEBUG_UART_HS 276 config DEBUG_LL_UART_NONE
277 bool "No low-level debugging UART"
283 help 278 help
284 Say Y here if you want the debug print routines to direct 279 Say Y here if your platform doesn't provide a UART option
285 their output to the serial port on MSM 8660 devices. 280 below. This relies on your platform choosing the right UART
281 definition internally in order for low-level debugging to
282 work.
286 283
287 config DEBUG_MSM8960_UART 284 config DEBUG_ICEDCC
288 bool "Kernel low-level debugging messages via MSM 8960 UART" 285 bool "Kernel low-level debugging via EmbeddedICE DCC channel"
289 depends on ARCH_MSM8960
290 select MSM_HAS_DEBUG_UART_HS
291 help 286 help
292 Say Y here if you want the debug print routines to direct 287 Say Y here if you want the debug print routines to direct
293 their output to the serial port on MSM 8960 devices. 288 their output to the EmbeddedICE macrocell's DCC channel using
289 co-processor 14. This is known to work on the ARM9 style ICE
290 channel and on the XScale with the PEEDI.
291
292 Note that the system will appear to hang during boot if there
293 is nothing connected to read from the DCC.
294 294
295endchoice 295endchoice
296 296
diff --git a/arch/arm/configs/at91cap9_defconfig b/arch/arm/configs/at91cap9_defconfig
deleted file mode 100644
index 8826eb218e73..000000000000
--- a/arch/arm/configs/at91cap9_defconfig
+++ /dev/null
@@ -1,108 +0,0 @@
1CONFIG_EXPERIMENTAL=y
2# CONFIG_LOCALVERSION_AUTO is not set
3# CONFIG_SWAP is not set
4CONFIG_SYSVIPC=y
5CONFIG_LOG_BUF_SHIFT=14
6CONFIG_BLK_DEV_INITRD=y
7CONFIG_SLAB=y
8CONFIG_MODULES=y
9CONFIG_MODULE_UNLOAD=y
10# CONFIG_BLK_DEV_BSG is not set
11# CONFIG_IOSCHED_DEADLINE is not set
12# CONFIG_IOSCHED_CFQ is not set
13CONFIG_ARCH_AT91=y
14CONFIG_ARCH_AT91CAP9=y
15CONFIG_MACH_AT91CAP9ADK=y
16CONFIG_MTD_AT91_DATAFLASH_CARD=y
17CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
18# CONFIG_ARM_THUMB is not set
19CONFIG_AEABI=y
20CONFIG_LEDS=y
21CONFIG_LEDS_CPU=y
22CONFIG_ZBOOT_ROM_TEXT=0x0
23CONFIG_ZBOOT_ROM_BSS=0x0
24CONFIG_CMDLINE="console=ttyS0,115200 root=/dev/ram0 rw"
25CONFIG_FPE_NWFPE=y
26CONFIG_NET=y
27CONFIG_PACKET=y
28CONFIG_UNIX=y
29CONFIG_INET=y
30CONFIG_IP_PNP=y
31CONFIG_IP_PNP_BOOTP=y
32CONFIG_IP_PNP_RARP=y
33# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
34# CONFIG_INET_XFRM_MODE_TUNNEL is not set
35# CONFIG_INET_XFRM_MODE_BEET is not set
36# CONFIG_INET_LRO is not set
37# CONFIG_INET_DIAG is not set
38# CONFIG_IPV6 is not set
39CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
40CONFIG_MTD=y
41CONFIG_MTD_CMDLINE_PARTS=y
42CONFIG_MTD_CHAR=y
43CONFIG_MTD_BLOCK=y
44CONFIG_MTD_CFI=y
45CONFIG_MTD_JEDECPROBE=y
46CONFIG_MTD_CFI_AMDSTD=y
47CONFIG_MTD_PHYSMAP=y
48CONFIG_MTD_DATAFLASH=y
49CONFIG_MTD_NAND=y
50CONFIG_MTD_NAND_ATMEL=y
51CONFIG_BLK_DEV_LOOP=y
52CONFIG_BLK_DEV_RAM=y
53CONFIG_BLK_DEV_RAM_SIZE=8192
54CONFIG_SCSI=y
55CONFIG_BLK_DEV_SD=y
56CONFIG_SCSI_MULTI_LUN=y
57CONFIG_NETDEVICES=y
58CONFIG_MII=y
59CONFIG_MACB=y
60# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
61CONFIG_INPUT_EVDEV=y
62# CONFIG_INPUT_KEYBOARD is not set
63# CONFIG_INPUT_MOUSE is not set
64CONFIG_INPUT_TOUCHSCREEN=y
65CONFIG_TOUCHSCREEN_ADS7846=y
66# CONFIG_SERIO is not set
67CONFIG_SERIAL_ATMEL=y
68CONFIG_SERIAL_ATMEL_CONSOLE=y
69CONFIG_HW_RANDOM=y
70CONFIG_I2C=y
71CONFIG_I2C_CHARDEV=y
72CONFIG_SPI=y
73CONFIG_SPI_ATMEL=y
74# CONFIG_HWMON is not set
75CONFIG_WATCHDOG=y
76CONFIG_WATCHDOG_NOWAYOUT=y
77CONFIG_FB=y
78CONFIG_FB_ATMEL=y
79CONFIG_LOGO=y
80# CONFIG_LOGO_LINUX_MONO is not set
81# CONFIG_LOGO_LINUX_CLUT224 is not set
82# CONFIG_USB_HID is not set
83CONFIG_USB=y
84CONFIG_USB_DEVICEFS=y
85CONFIG_USB_MON=y
86CONFIG_USB_OHCI_HCD=y
87CONFIG_USB_STORAGE=y
88CONFIG_USB_GADGET=y
89CONFIG_USB_ETH=m
90CONFIG_USB_FILE_STORAGE=m
91CONFIG_MMC=y
92CONFIG_MMC_AT91=m
93CONFIG_RTC_CLASS=y
94CONFIG_RTC_DRV_AT91SAM9=y
95CONFIG_EXT2_FS=y
96CONFIG_VFAT_FS=y
97CONFIG_TMPFS=y
98CONFIG_JFFS2_FS=y
99CONFIG_CRAMFS=y
100CONFIG_NFS_FS=y
101CONFIG_ROOT_NFS=y
102CONFIG_NLS_CODEPAGE_437=y
103CONFIG_NLS_CODEPAGE_850=y
104CONFIG_NLS_ISO8859_1=y
105CONFIG_DEBUG_FS=y
106CONFIG_DEBUG_KERNEL=y
107CONFIG_DEBUG_INFO=y
108CONFIG_DEBUG_USER=y
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index e4c96cc6ec0c..424aa458c487 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -110,6 +110,7 @@ extern void cpu_init(void);
110 110
111void soft_restart(unsigned long); 111void soft_restart(unsigned long);
112extern void (*arm_pm_restart)(char str, const char *cmd); 112extern void (*arm_pm_restart)(char str, const char *cmd);
113extern void (*arm_pm_idle)(void);
113 114
114#define UDBG_UNDEFINED (1 << 0) 115#define UDBG_UNDEFINED (1 << 0)
115#define UDBG_SYSCALL (1 << 1) 116#define UDBG_SYSCALL (1 << 1)
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index 971d65c253a9..008e7ce766a7 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -61,8 +61,6 @@ extern void setup_mm_for_reboot(void);
61 61
62static volatile int hlt_counter; 62static volatile int hlt_counter;
63 63
64#include <mach/system.h>
65
66void disable_hlt(void) 64void disable_hlt(void)
67{ 65{
68 hlt_counter++; 66 hlt_counter++;
@@ -181,13 +179,17 @@ void cpu_idle_wait(void)
181EXPORT_SYMBOL_GPL(cpu_idle_wait); 179EXPORT_SYMBOL_GPL(cpu_idle_wait);
182 180
183/* 181/*
184 * This is our default idle handler. We need to disable 182 * This is our default idle handler.
185 * interrupts here to ensure we don't miss a wakeup call.
186 */ 183 */
184
185void (*arm_pm_idle)(void);
186
187static void default_idle(void) 187static void default_idle(void)
188{ 188{
189 if (!need_resched()) 189 if (arm_pm_idle)
190 arch_idle(); 190 arm_pm_idle();
191 else
192 cpu_do_idle();
191 local_irq_enable(); 193 local_irq_enable();
192} 194}
193 195
@@ -215,6 +217,10 @@ void cpu_idle(void)
215 cpu_die(); 217 cpu_die();
216#endif 218#endif
217 219
220 /*
221 * We need to disable interrupts here
222 * to ensure we don't miss a wakeup call.
223 */
218 local_irq_disable(); 224 local_irq_disable();
219#ifdef CONFIG_PL310_ERRATA_769419 225#ifdef CONFIG_PL310_ERRATA_769419
220 wmb(); 226 wmb();
@@ -222,19 +228,18 @@ void cpu_idle(void)
222 if (hlt_counter) { 228 if (hlt_counter) {
223 local_irq_enable(); 229 local_irq_enable();
224 cpu_relax(); 230 cpu_relax();
225 } else { 231 } else if (!need_resched()) {
226 stop_critical_timings(); 232 stop_critical_timings();
227 if (cpuidle_idle_call()) 233 if (cpuidle_idle_call())
228 pm_idle(); 234 pm_idle();
229 start_critical_timings(); 235 start_critical_timings();
230 /* 236 /*
231 * This will eventually be removed - pm_idle 237 * pm_idle functions must always
232 * functions should always return with IRQs 238 * return with IRQs enabled.
233 * enabled.
234 */ 239 */
235 WARN_ON(irqs_disabled()); 240 WARN_ON(irqs_disabled());
241 } else
236 local_irq_enable(); 242 local_irq_enable();
237 }
238 } 243 }
239 leds_event(led_idle_end); 244 leds_event(led_idle_end);
240 rcu_idle_exit(); 245 rcu_idle_exit();
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 71feb00a1e99..0284e66c47f9 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -102,15 +102,6 @@ config ARCH_AT91SAM9G45
102 select HAVE_AT91_DBGU1 102 select HAVE_AT91_DBGU1
103 select AT91_SAM9G45_RESET 103 select AT91_SAM9G45_RESET
104 104
105config ARCH_AT91CAP9
106 bool "AT91CAP9"
107 select CPU_ARM926T
108 select GENERIC_CLOCKEVENTS
109 select HAVE_FB_ATMEL
110 select HAVE_NET_MACB
111 select HAVE_AT91_DBGU1
112 select AT91_SAM9G45_RESET
113
114config ARCH_AT91X40 105config ARCH_AT91X40
115 bool "AT91x40" 106 bool "AT91x40"
116 select ARCH_USES_GETTIMEOFFSET 107 select ARCH_USES_GETTIMEOFFSET
@@ -447,21 +438,6 @@ endif
447 438
448# ---------------------------------------------------------- 439# ----------------------------------------------------------
449 440
450if ARCH_AT91CAP9
451
452comment "AT91CAP9 Board Type"
453
454config MACH_AT91CAP9ADK
455 bool "Atmel AT91CAP9A-DK Evaluation Kit"
456 select HAVE_AT91_DATAFLASH_CARD
457 help
458 Select this if you are using Atmel's AT91CAP9A-DK Evaluation Kit.
459 <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4138>
460
461endif
462
463# ----------------------------------------------------------
464
465if ARCH_AT91X40 441if ARCH_AT91X40
466 442
467comment "AT91X40 Board Type" 443comment "AT91X40 Board Type"
@@ -544,7 +520,7 @@ config AT91_EARLY_DBGU0
544 depends on HAVE_AT91_DBGU0 520 depends on HAVE_AT91_DBGU0
545 521
546config AT91_EARLY_DBGU1 522config AT91_EARLY_DBGU1
547 bool "DBGU on 9263, 9g45 and cap9" 523 bool "DBGU on 9263 and 9g45"
548 depends on HAVE_AT91_DBGU1 524 depends on HAVE_AT91_DBGU1
549 525
550config AT91_EARLY_USART0 526config AT91_EARLY_USART0
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 705e1fbded39..aeb76f1690d9 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -20,7 +20,6 @@ obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_d
20obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o sam9_smc.o 20obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o sam9_smc.o
21obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o 21obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o
22obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o 22obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o
23obj-$(CONFIG_ARCH_AT91CAP9) += at91cap9.o at91sam926x_time.o at91cap9_devices.o sam9_smc.o
24obj-$(CONFIG_ARCH_AT91X40) += at91x40.o at91x40_time.o 23obj-$(CONFIG_ARCH_AT91X40) += at91x40.o at91x40_time.o
25 24
26# AT91RM9200 board-specific support 25# AT91RM9200 board-specific support
@@ -81,9 +80,6 @@ obj-$(CONFIG_MACH_AT91SAM9M10G45EK) += board-sam9m10g45ek.o
81# AT91SAM board with device-tree 80# AT91SAM board with device-tree
82obj-$(CONFIG_MACH_AT91SAM_DT) += board-dt.o 81obj-$(CONFIG_MACH_AT91SAM_DT) += board-dt.o
83 82
84# AT91CAP9 board-specific support
85obj-$(CONFIG_MACH_AT91CAP9ADK) += board-cap9adk.o
86
87# AT91X40 board-specific support 83# AT91X40 board-specific support
88obj-$(CONFIG_MACH_AT91EB01) += board-eb01.o 84obj-$(CONFIG_MACH_AT91EB01) += board-eb01.o
89 85
diff --git a/arch/arm/mach-at91/Makefile.boot b/arch/arm/mach-at91/Makefile.boot
index 8ddafadfdc7d..2fd051eb2449 100644
--- a/arch/arm/mach-at91/Makefile.boot
+++ b/arch/arm/mach-at91/Makefile.boot
@@ -3,11 +3,7 @@
3# PARAMS_PHYS must be within 4MB of ZRELADDR 3# PARAMS_PHYS must be within 4MB of ZRELADDR
4# INITRD_PHYS must be in RAM 4# INITRD_PHYS must be in RAM
5 5
6ifeq ($(CONFIG_ARCH_AT91CAP9),y) 6ifeq ($(CONFIG_ARCH_AT91SAM9G45),y)
7 zreladdr-y += 0x70008000
8params_phys-y := 0x70000100
9initrd_phys-y := 0x70410000
10else ifeq ($(CONFIG_ARCH_AT91SAM9G45),y)
11 zreladdr-y += 0x70008000 7 zreladdr-y += 0x70008000
12params_phys-y := 0x70000100 8params_phys-y := 0x70000100
13initrd_phys-y := 0x70410000 9initrd_phys-y := 0x70410000
diff --git a/arch/arm/mach-at91/at91cap9.c b/arch/arm/mach-at91/at91cap9.c
deleted file mode 100644
index a42edc25a87e..000000000000
--- a/arch/arm/mach-at91/at91cap9.c
+++ /dev/null
@@ -1,396 +0,0 @@
1/*
2 * arch/arm/mach-at91/at91cap9.c
3 *
4 * Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
5 * Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
6 * Copyright (C) 2007 Atmel Corporation.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 */
14
15#include <linux/module.h>
16
17#include <asm/irq.h>
18#include <asm/mach/arch.h>
19#include <asm/mach/map.h>
20
21#include <mach/cpu.h>
22#include <mach/at91cap9.h>
23#include <mach/at91_pmc.h>
24
25#include "soc.h"
26#include "generic.h"
27#include "clock.h"
28#include "sam9_smc.h"
29
30/* --------------------------------------------------------------------
31 * Clocks
32 * -------------------------------------------------------------------- */
33
34/*
35 * The peripheral clocks.
36 */
37static struct clk pioABCD_clk = {
38 .name = "pioABCD_clk",
39 .pmc_mask = 1 << AT91CAP9_ID_PIOABCD,
40 .type = CLK_TYPE_PERIPHERAL,
41};
42static struct clk mpb0_clk = {
43 .name = "mpb0_clk",
44 .pmc_mask = 1 << AT91CAP9_ID_MPB0,
45 .type = CLK_TYPE_PERIPHERAL,
46};
47static struct clk mpb1_clk = {
48 .name = "mpb1_clk",
49 .pmc_mask = 1 << AT91CAP9_ID_MPB1,
50 .type = CLK_TYPE_PERIPHERAL,
51};
52static struct clk mpb2_clk = {
53 .name = "mpb2_clk",
54 .pmc_mask = 1 << AT91CAP9_ID_MPB2,
55 .type = CLK_TYPE_PERIPHERAL,
56};
57static struct clk mpb3_clk = {
58 .name = "mpb3_clk",
59 .pmc_mask = 1 << AT91CAP9_ID_MPB3,
60 .type = CLK_TYPE_PERIPHERAL,
61};
62static struct clk mpb4_clk = {
63 .name = "mpb4_clk",
64 .pmc_mask = 1 << AT91CAP9_ID_MPB4,
65 .type = CLK_TYPE_PERIPHERAL,
66};
67static struct clk usart0_clk = {
68 .name = "usart0_clk",
69 .pmc_mask = 1 << AT91CAP9_ID_US0,
70 .type = CLK_TYPE_PERIPHERAL,
71};
72static struct clk usart1_clk = {
73 .name = "usart1_clk",
74 .pmc_mask = 1 << AT91CAP9_ID_US1,
75 .type = CLK_TYPE_PERIPHERAL,
76};
77static struct clk usart2_clk = {
78 .name = "usart2_clk",
79 .pmc_mask = 1 << AT91CAP9_ID_US2,
80 .type = CLK_TYPE_PERIPHERAL,
81};
82static struct clk mmc0_clk = {
83 .name = "mci0_clk",
84 .pmc_mask = 1 << AT91CAP9_ID_MCI0,
85 .type = CLK_TYPE_PERIPHERAL,
86};
87static struct clk mmc1_clk = {
88 .name = "mci1_clk",
89 .pmc_mask = 1 << AT91CAP9_ID_MCI1,
90 .type = CLK_TYPE_PERIPHERAL,
91};
92static struct clk can_clk = {
93 .name = "can_clk",
94 .pmc_mask = 1 << AT91CAP9_ID_CAN,
95 .type = CLK_TYPE_PERIPHERAL,
96};
97static struct clk twi_clk = {
98 .name = "twi_clk",
99 .pmc_mask = 1 << AT91CAP9_ID_TWI,
100 .type = CLK_TYPE_PERIPHERAL,
101};
102static struct clk spi0_clk = {
103 .name = "spi0_clk",
104 .pmc_mask = 1 << AT91CAP9_ID_SPI0,
105 .type = CLK_TYPE_PERIPHERAL,
106};
107static struct clk spi1_clk = {
108 .name = "spi1_clk",
109 .pmc_mask = 1 << AT91CAP9_ID_SPI1,
110 .type = CLK_TYPE_PERIPHERAL,
111};
112static struct clk ssc0_clk = {
113 .name = "ssc0_clk",
114 .pmc_mask = 1 << AT91CAP9_ID_SSC0,
115 .type = CLK_TYPE_PERIPHERAL,
116};
117static struct clk ssc1_clk = {
118 .name = "ssc1_clk",
119 .pmc_mask = 1 << AT91CAP9_ID_SSC1,
120 .type = CLK_TYPE_PERIPHERAL,
121};
122static struct clk ac97_clk = {
123 .name = "ac97_clk",
124 .pmc_mask = 1 << AT91CAP9_ID_AC97C,
125 .type = CLK_TYPE_PERIPHERAL,
126};
127static struct clk tcb_clk = {
128 .name = "tcb_clk",
129 .pmc_mask = 1 << AT91CAP9_ID_TCB,
130 .type = CLK_TYPE_PERIPHERAL,
131};
132static struct clk pwm_clk = {
133 .name = "pwm_clk",
134 .pmc_mask = 1 << AT91CAP9_ID_PWMC,
135 .type = CLK_TYPE_PERIPHERAL,
136};
137static struct clk macb_clk = {
138 .name = "pclk",
139 .pmc_mask = 1 << AT91CAP9_ID_EMAC,
140 .type = CLK_TYPE_PERIPHERAL,
141};
142static struct clk aestdes_clk = {
143 .name = "aestdes_clk",
144 .pmc_mask = 1 << AT91CAP9_ID_AESTDES,
145 .type = CLK_TYPE_PERIPHERAL,
146};
147static struct clk adc_clk = {
148 .name = "adc_clk",
149 .pmc_mask = 1 << AT91CAP9_ID_ADC,
150 .type = CLK_TYPE_PERIPHERAL,
151};
152static struct clk isi_clk = {
153 .name = "isi_clk",
154 .pmc_mask = 1 << AT91CAP9_ID_ISI,
155 .type = CLK_TYPE_PERIPHERAL,
156};
157static struct clk lcdc_clk = {
158 .name = "lcdc_clk",
159 .pmc_mask = 1 << AT91CAP9_ID_LCDC,
160 .type = CLK_TYPE_PERIPHERAL,
161};
162static struct clk dma_clk = {
163 .name = "dma_clk",
164 .pmc_mask = 1 << AT91CAP9_ID_DMA,
165 .type = CLK_TYPE_PERIPHERAL,
166};
167static struct clk udphs_clk = {
168 .name = "udphs_clk",
169 .pmc_mask = 1 << AT91CAP9_ID_UDPHS,
170 .type = CLK_TYPE_PERIPHERAL,
171};
172static struct clk ohci_clk = {
173 .name = "ohci_clk",
174 .pmc_mask = 1 << AT91CAP9_ID_UHP,
175 .type = CLK_TYPE_PERIPHERAL,
176};
177
178static struct clk *periph_clocks[] __initdata = {
179 &pioABCD_clk,
180 &mpb0_clk,
181 &mpb1_clk,
182 &mpb2_clk,
183 &mpb3_clk,
184 &mpb4_clk,
185 &usart0_clk,
186 &usart1_clk,
187 &usart2_clk,
188 &mmc0_clk,
189 &mmc1_clk,
190 &can_clk,
191 &twi_clk,
192 &spi0_clk,
193 &spi1_clk,
194 &ssc0_clk,
195 &ssc1_clk,
196 &ac97_clk,
197 &tcb_clk,
198 &pwm_clk,
199 &macb_clk,
200 &aestdes_clk,
201 &adc_clk,
202 &isi_clk,
203 &lcdc_clk,
204 &dma_clk,
205 &udphs_clk,
206 &ohci_clk,
207 // irq0 .. irq1
208};
209
210static struct clk_lookup periph_clocks_lookups[] = {
211 /* One additional fake clock for macb_hclk */
212 CLKDEV_CON_ID("hclk", &macb_clk),
213 CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
214 CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
215 CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.0", &mmc0_clk),
216 CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.1", &mmc1_clk),
217 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
218 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
219 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk),
220 CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
221 CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
222 /* fake hclk clock */
223 CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
224 CLKDEV_CON_ID("pioA", &pioABCD_clk),
225 CLKDEV_CON_ID("pioB", &pioABCD_clk),
226 CLKDEV_CON_ID("pioC", &pioABCD_clk),
227 CLKDEV_CON_ID("pioD", &pioABCD_clk),
228};
229
230static struct clk_lookup usart_clocks_lookups[] = {
231 CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
232 CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
233 CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
234 CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
235};
236
237/*
238 * The four programmable clocks.
239 * You must configure pin multiplexing to bring these signals out.
240 */
241static struct clk pck0 = {
242 .name = "pck0",
243 .pmc_mask = AT91_PMC_PCK0,
244 .type = CLK_TYPE_PROGRAMMABLE,
245 .id = 0,
246};
247static struct clk pck1 = {
248 .name = "pck1",
249 .pmc_mask = AT91_PMC_PCK1,
250 .type = CLK_TYPE_PROGRAMMABLE,
251 .id = 1,
252};
253static struct clk pck2 = {
254 .name = "pck2",
255 .pmc_mask = AT91_PMC_PCK2,
256 .type = CLK_TYPE_PROGRAMMABLE,
257 .id = 2,
258};
259static struct clk pck3 = {
260 .name = "pck3",
261 .pmc_mask = AT91_PMC_PCK3,
262 .type = CLK_TYPE_PROGRAMMABLE,
263 .id = 3,
264};
265
266static void __init at91cap9_register_clocks(void)
267{
268 int i;
269
270 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
271 clk_register(periph_clocks[i]);
272
273 clkdev_add_table(periph_clocks_lookups,
274 ARRAY_SIZE(periph_clocks_lookups));
275 clkdev_add_table(usart_clocks_lookups,
276 ARRAY_SIZE(usart_clocks_lookups));
277
278 clk_register(&pck0);
279 clk_register(&pck1);
280 clk_register(&pck2);
281 clk_register(&pck3);
282}
283
284static struct clk_lookup console_clock_lookup;
285
286void __init at91cap9_set_console_clock(int id)
287{
288 if (id >= ARRAY_SIZE(usart_clocks_lookups))
289 return;
290
291 console_clock_lookup.con_id = "usart";
292 console_clock_lookup.clk = usart_clocks_lookups[id].clk;
293 clkdev_add(&console_clock_lookup);
294}
295
296/* --------------------------------------------------------------------
297 * GPIO
298 * -------------------------------------------------------------------- */
299
300static struct at91_gpio_bank at91cap9_gpio[] __initdata = {
301 {
302 .id = AT91CAP9_ID_PIOABCD,
303 .regbase = AT91CAP9_BASE_PIOA,
304 }, {
305 .id = AT91CAP9_ID_PIOABCD,
306 .regbase = AT91CAP9_BASE_PIOB,
307 }, {
308 .id = AT91CAP9_ID_PIOABCD,
309 .regbase = AT91CAP9_BASE_PIOC,
310 }, {
311 .id = AT91CAP9_ID_PIOABCD,
312 .regbase = AT91CAP9_BASE_PIOD,
313 }
314};
315
316/* --------------------------------------------------------------------
317 * AT91CAP9 processor initialization
318 * -------------------------------------------------------------------- */
319
320static void __init at91cap9_map_io(void)
321{
322 at91_init_sram(0, AT91CAP9_SRAM_BASE, AT91CAP9_SRAM_SIZE);
323}
324
325static void __init at91cap9_ioremap_registers(void)
326{
327 at91_ioremap_shdwc(AT91CAP9_BASE_SHDWC);
328 at91_ioremap_rstc(AT91CAP9_BASE_RSTC);
329 at91sam926x_ioremap_pit(AT91CAP9_BASE_PIT);
330 at91sam9_ioremap_smc(0, AT91CAP9_BASE_SMC);
331}
332
333static void __init at91cap9_initialize(void)
334{
335 arm_pm_restart = at91sam9g45_restart;
336 at91_extern_irq = (1 << AT91CAP9_ID_IRQ0) | (1 << AT91CAP9_ID_IRQ1);
337
338 /* Register GPIO subsystem */
339 at91_gpio_init(at91cap9_gpio, 4);
340
341 /* Remember the silicon revision */
342 if (cpu_is_at91cap9_revB())
343 system_rev = 0xB;
344 else if (cpu_is_at91cap9_revC())
345 system_rev = 0xC;
346}
347
348/* --------------------------------------------------------------------
349 * Interrupt initialization
350 * -------------------------------------------------------------------- */
351
352/*
353 * The default interrupt priority levels (0 = lowest, 7 = highest).
354 */
355static unsigned int at91cap9_default_irq_priority[NR_AIC_IRQS] __initdata = {
356 7, /* Advanced Interrupt Controller (FIQ) */
357 7, /* System Peripherals */
358 1, /* Parallel IO Controller A, B, C and D */
359 0, /* MP Block Peripheral 0 */
360 0, /* MP Block Peripheral 1 */
361 0, /* MP Block Peripheral 2 */
362 0, /* MP Block Peripheral 3 */
363 0, /* MP Block Peripheral 4 */
364 5, /* USART 0 */
365 5, /* USART 1 */
366 5, /* USART 2 */
367 0, /* Multimedia Card Interface 0 */
368 0, /* Multimedia Card Interface 1 */
369 3, /* CAN */
370 6, /* Two-Wire Interface */
371 5, /* Serial Peripheral Interface 0 */
372 5, /* Serial Peripheral Interface 1 */
373 4, /* Serial Synchronous Controller 0 */
374 4, /* Serial Synchronous Controller 1 */
375 5, /* AC97 Controller */
376 0, /* Timer Counter 0, 1 and 2 */
377 0, /* Pulse Width Modulation Controller */
378 3, /* Ethernet */
379 0, /* Advanced Encryption Standard, Triple DES*/
380 0, /* Analog-to-Digital Converter */
381 0, /* Image Sensor Interface */
382 3, /* LCD Controller */
383 0, /* DMA Controller */
384 2, /* USB Device Port */
385 2, /* USB Host port */
386 0, /* Advanced Interrupt Controller (IRQ0) */
387 0, /* Advanced Interrupt Controller (IRQ1) */
388};
389
390struct at91_init_soc __initdata at91cap9_soc = {
391 .map_io = at91cap9_map_io,
392 .default_irq_priority = at91cap9_default_irq_priority,
393 .ioremap_registers = at91cap9_ioremap_registers,
394 .register_clocks = at91cap9_register_clocks,
395 .init = at91cap9_initialize,
396};
diff --git a/arch/arm/mach-at91/at91cap9_devices.c b/arch/arm/mach-at91/at91cap9_devices.c
deleted file mode 100644
index d298fb7cb210..000000000000
--- a/arch/arm/mach-at91/at91cap9_devices.c
+++ /dev/null
@@ -1,1273 +0,0 @@
1/*
2 * arch/arm/mach-at91/at91cap9_devices.c
3 *
4 * Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
5 * Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
6 * Copyright (C) 2007 Atmel Corporation.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 */
14#include <asm/mach/arch.h>
15#include <asm/mach/map.h>
16#include <asm/mach/irq.h>
17
18#include <linux/dma-mapping.h>
19#include <linux/gpio.h>
20#include <linux/platform_device.h>
21#include <linux/i2c-gpio.h>
22
23#include <video/atmel_lcdc.h>
24
25#include <mach/board.h>
26#include <mach/cpu.h>
27#include <mach/at91cap9.h>
28#include <mach/at91cap9_matrix.h>
29#include <mach/at91sam9_smc.h>
30
31#include "generic.h"
32
33
34/* --------------------------------------------------------------------
35 * USB Host
36 * -------------------------------------------------------------------- */
37
38#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
39static u64 ohci_dmamask = DMA_BIT_MASK(32);
40static struct at91_usbh_data usbh_data;
41
42static struct resource usbh_resources[] = {
43 [0] = {
44 .start = AT91CAP9_UHP_BASE,
45 .end = AT91CAP9_UHP_BASE + SZ_1M - 1,
46 .flags = IORESOURCE_MEM,
47 },
48 [1] = {
49 .start = AT91CAP9_ID_UHP,
50 .end = AT91CAP9_ID_UHP,
51 .flags = IORESOURCE_IRQ,
52 },
53};
54
55static struct platform_device at91_usbh_device = {
56 .name = "at91_ohci",
57 .id = -1,
58 .dev = {
59 .dma_mask = &ohci_dmamask,
60 .coherent_dma_mask = DMA_BIT_MASK(32),
61 .platform_data = &usbh_data,
62 },
63 .resource = usbh_resources,
64 .num_resources = ARRAY_SIZE(usbh_resources),
65};
66
67void __init at91_add_device_usbh(struct at91_usbh_data *data)
68{
69 int i;
70
71 if (!data)
72 return;
73
74 if (cpu_is_at91cap9_revB())
75 irq_set_irq_type(AT91CAP9_ID_UHP, IRQ_TYPE_LEVEL_HIGH);
76
77 /* Enable VBus control for UHP ports */
78 for (i = 0; i < data->ports; i++) {
79 if (gpio_is_valid(data->vbus_pin[i]))
80 at91_set_gpio_output(data->vbus_pin[i], 0);
81 }
82
83 /* Enable overcurrent notification */
84 for (i = 0; i < data->ports; i++) {
85 if (data->overcurrent_pin[i])
86 at91_set_gpio_input(data->overcurrent_pin[i], 1);
87 }
88
89 usbh_data = *data;
90 platform_device_register(&at91_usbh_device);
91}
92#else
93void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
94#endif
95
96
97/* --------------------------------------------------------------------
98 * USB HS Device (Gadget)
99 * -------------------------------------------------------------------- */
100
101#if defined(CONFIG_USB_ATMEL_USBA) || defined(CONFIG_USB_ATMEL_USBA_MODULE)
102
103static struct resource usba_udc_resources[] = {
104 [0] = {
105 .start = AT91CAP9_UDPHS_FIFO,
106 .end = AT91CAP9_UDPHS_FIFO + SZ_512K - 1,
107 .flags = IORESOURCE_MEM,
108 },
109 [1] = {
110 .start = AT91CAP9_BASE_UDPHS,
111 .end = AT91CAP9_BASE_UDPHS + SZ_1K - 1,
112 .flags = IORESOURCE_MEM,
113 },
114 [2] = {
115 .start = AT91CAP9_ID_UDPHS,
116 .end = AT91CAP9_ID_UDPHS,
117 .flags = IORESOURCE_IRQ,
118 },
119};
120
121#define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
122 [idx] = { \
123 .name = nam, \
124 .index = idx, \
125 .fifo_size = maxpkt, \
126 .nr_banks = maxbk, \
127 .can_dma = dma, \
128 .can_isoc = isoc, \
129 }
130
131static struct usba_ep_data usba_udc_ep[] = {
132 EP("ep0", 0, 64, 1, 0, 0),
133 EP("ep1", 1, 1024, 3, 1, 1),
134 EP("ep2", 2, 1024, 3, 1, 1),
135 EP("ep3", 3, 1024, 2, 1, 1),
136 EP("ep4", 4, 1024, 2, 1, 1),
137 EP("ep5", 5, 1024, 2, 1, 0),
138 EP("ep6", 6, 1024, 2, 1, 0),
139 EP("ep7", 7, 1024, 2, 0, 0),
140};
141
142#undef EP
143
144/*
145 * pdata doesn't have room for any endpoints, so we need to
146 * append room for the ones we need right after it.
147 */
148static struct {
149 struct usba_platform_data pdata;
150 struct usba_ep_data ep[8];
151} usba_udc_data;
152
153static struct platform_device at91_usba_udc_device = {
154 .name = "atmel_usba_udc",
155 .id = -1,
156 .dev = {
157 .platform_data = &usba_udc_data.pdata,
158 },
159 .resource = usba_udc_resources,
160 .num_resources = ARRAY_SIZE(usba_udc_resources),
161};
162
163void __init at91_add_device_usba(struct usba_platform_data *data)
164{
165 if (cpu_is_at91cap9_revB()) {
166 irq_set_irq_type(AT91CAP9_ID_UDPHS, IRQ_TYPE_LEVEL_HIGH);
167 at91_sys_write(AT91_MATRIX_UDPHS, AT91_MATRIX_SELECT_UDPHS |
168 AT91_MATRIX_UDPHS_BYPASS_LOCK);
169 }
170 else
171 at91_sys_write(AT91_MATRIX_UDPHS, AT91_MATRIX_SELECT_UDPHS);
172
173 /*
174 * Invalid pins are 0 on AT91, but the usba driver is shared
175 * with AVR32, which use negative values instead. Once/if
176 * gpio_is_valid() is ported to AT91, revisit this code.
177 */
178 usba_udc_data.pdata.vbus_pin = -EINVAL;
179 usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep);
180 memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));
181
182 if (data && gpio_is_valid(data->vbus_pin)) {
183 at91_set_gpio_input(data->vbus_pin, 0);
184 at91_set_deglitch(data->vbus_pin, 1);
185 usba_udc_data.pdata.vbus_pin = data->vbus_pin;
186 }
187
188 /* Pullup pin is handled internally by USB device peripheral */
189
190 platform_device_register(&at91_usba_udc_device);
191}
192#else
193void __init at91_add_device_usba(struct usba_platform_data *data) {}
194#endif
195
196
197/* --------------------------------------------------------------------
198 * Ethernet
199 * -------------------------------------------------------------------- */
200
201#if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
202static u64 eth_dmamask = DMA_BIT_MASK(32);
203static struct macb_platform_data eth_data;
204
205static struct resource eth_resources[] = {
206 [0] = {
207 .start = AT91CAP9_BASE_EMAC,
208 .end = AT91CAP9_BASE_EMAC + SZ_16K - 1,
209 .flags = IORESOURCE_MEM,
210 },
211 [1] = {
212 .start = AT91CAP9_ID_EMAC,
213 .end = AT91CAP9_ID_EMAC,
214 .flags = IORESOURCE_IRQ,
215 },
216};
217
218static struct platform_device at91cap9_eth_device = {
219 .name = "macb",
220 .id = -1,
221 .dev = {
222 .dma_mask = &eth_dmamask,
223 .coherent_dma_mask = DMA_BIT_MASK(32),
224 .platform_data = &eth_data,
225 },
226 .resource = eth_resources,
227 .num_resources = ARRAY_SIZE(eth_resources),
228};
229
230void __init at91_add_device_eth(struct macb_platform_data *data)
231{
232 if (!data)
233 return;
234
235 if (gpio_is_valid(data->phy_irq_pin)) {
236 at91_set_gpio_input(data->phy_irq_pin, 0);
237 at91_set_deglitch(data->phy_irq_pin, 1);
238 }
239
240 /* Pins used for MII and RMII */
241 at91_set_A_periph(AT91_PIN_PB21, 0); /* ETXCK_EREFCK */
242 at91_set_A_periph(AT91_PIN_PB22, 0); /* ERXDV */
243 at91_set_A_periph(AT91_PIN_PB25, 0); /* ERX0 */
244 at91_set_A_periph(AT91_PIN_PB26, 0); /* ERX1 */
245 at91_set_A_periph(AT91_PIN_PB27, 0); /* ERXER */
246 at91_set_A_periph(AT91_PIN_PB28, 0); /* ETXEN */
247 at91_set_A_periph(AT91_PIN_PB23, 0); /* ETX0 */
248 at91_set_A_periph(AT91_PIN_PB24, 0); /* ETX1 */
249 at91_set_A_periph(AT91_PIN_PB30, 0); /* EMDIO */
250 at91_set_A_periph(AT91_PIN_PB29, 0); /* EMDC */
251
252 if (!data->is_rmii) {
253 at91_set_B_periph(AT91_PIN_PC25, 0); /* ECRS */
254 at91_set_B_periph(AT91_PIN_PC26, 0); /* ECOL */
255 at91_set_B_periph(AT91_PIN_PC22, 0); /* ERX2 */
256 at91_set_B_periph(AT91_PIN_PC23, 0); /* ERX3 */
257 at91_set_B_periph(AT91_PIN_PC27, 0); /* ERXCK */
258 at91_set_B_periph(AT91_PIN_PC20, 0); /* ETX2 */
259 at91_set_B_periph(AT91_PIN_PC21, 0); /* ETX3 */
260 at91_set_B_periph(AT91_PIN_PC24, 0); /* ETXER */
261 }
262
263 eth_data = *data;
264 platform_device_register(&at91cap9_eth_device);
265}
266#else
267void __init at91_add_device_eth(struct macb_platform_data *data) {}
268#endif
269
270
271/* --------------------------------------------------------------------
272 * MMC / SD
273 * -------------------------------------------------------------------- */
274
275#if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
276static u64 mmc_dmamask = DMA_BIT_MASK(32);
277static struct at91_mmc_data mmc0_data, mmc1_data;
278
279static struct resource mmc0_resources[] = {
280 [0] = {
281 .start = AT91CAP9_BASE_MCI0,
282 .end = AT91CAP9_BASE_MCI0 + SZ_16K - 1,
283 .flags = IORESOURCE_MEM,
284 },
285 [1] = {
286 .start = AT91CAP9_ID_MCI0,
287 .end = AT91CAP9_ID_MCI0,
288 .flags = IORESOURCE_IRQ,
289 },
290};
291
292static struct platform_device at91cap9_mmc0_device = {
293 .name = "at91_mci",
294 .id = 0,
295 .dev = {
296 .dma_mask = &mmc_dmamask,
297 .coherent_dma_mask = DMA_BIT_MASK(32),
298 .platform_data = &mmc0_data,
299 },
300 .resource = mmc0_resources,
301 .num_resources = ARRAY_SIZE(mmc0_resources),
302};
303
304static struct resource mmc1_resources[] = {
305 [0] = {
306 .start = AT91CAP9_BASE_MCI1,
307 .end = AT91CAP9_BASE_MCI1 + SZ_16K - 1,
308 .flags = IORESOURCE_MEM,
309 },
310 [1] = {
311 .start = AT91CAP9_ID_MCI1,
312 .end = AT91CAP9_ID_MCI1,
313 .flags = IORESOURCE_IRQ,
314 },
315};
316
317static struct platform_device at91cap9_mmc1_device = {
318 .name = "at91_mci",
319 .id = 1,
320 .dev = {
321 .dma_mask = &mmc_dmamask,
322 .coherent_dma_mask = DMA_BIT_MASK(32),
323 .platform_data = &mmc1_data,
324 },
325 .resource = mmc1_resources,
326 .num_resources = ARRAY_SIZE(mmc1_resources),
327};
328
329void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
330{
331 if (!data)
332 return;
333
334 /* input/irq */
335 if (gpio_is_valid(data->det_pin)) {
336 at91_set_gpio_input(data->det_pin, 1);
337 at91_set_deglitch(data->det_pin, 1);
338 }
339 if (gpio_is_valid(data->wp_pin))
340 at91_set_gpio_input(data->wp_pin, 1);
341 if (gpio_is_valid(data->vcc_pin))
342 at91_set_gpio_output(data->vcc_pin, 0);
343
344 if (mmc_id == 0) { /* MCI0 */
345 /* CLK */
346 at91_set_A_periph(AT91_PIN_PA2, 0);
347
348 /* CMD */
349 at91_set_A_periph(AT91_PIN_PA1, 1);
350
351 /* DAT0, maybe DAT1..DAT3 */
352 at91_set_A_periph(AT91_PIN_PA0, 1);
353 if (data->wire4) {
354 at91_set_A_periph(AT91_PIN_PA3, 1);
355 at91_set_A_periph(AT91_PIN_PA4, 1);
356 at91_set_A_periph(AT91_PIN_PA5, 1);
357 }
358
359 mmc0_data = *data;
360 platform_device_register(&at91cap9_mmc0_device);
361 } else { /* MCI1 */
362 /* CLK */
363 at91_set_A_periph(AT91_PIN_PA16, 0);
364
365 /* CMD */
366 at91_set_A_periph(AT91_PIN_PA17, 1);
367
368 /* DAT0, maybe DAT1..DAT3 */
369 at91_set_A_periph(AT91_PIN_PA18, 1);
370 if (data->wire4) {
371 at91_set_A_periph(AT91_PIN_PA19, 1);
372 at91_set_A_periph(AT91_PIN_PA20, 1);
373 at91_set_A_periph(AT91_PIN_PA21, 1);
374 }
375
376 mmc1_data = *data;
377 platform_device_register(&at91cap9_mmc1_device);
378 }
379}
380#else
381void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
382#endif
383
384
385/* --------------------------------------------------------------------
386 * NAND / SmartMedia
387 * -------------------------------------------------------------------- */
388
389#if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
390static struct atmel_nand_data nand_data;
391
392#define NAND_BASE AT91_CHIPSELECT_3
393
394static struct resource nand_resources[] = {
395 [0] = {
396 .start = NAND_BASE,
397 .end = NAND_BASE + SZ_256M - 1,
398 .flags = IORESOURCE_MEM,
399 },
400 [1] = {
401 .start = AT91CAP9_BASE_ECC,
402 .end = AT91CAP9_BASE_ECC + SZ_512 - 1,
403 .flags = IORESOURCE_MEM,
404 }
405};
406
407static struct platform_device at91cap9_nand_device = {
408 .name = "atmel_nand",
409 .id = -1,
410 .dev = {
411 .platform_data = &nand_data,
412 },
413 .resource = nand_resources,
414 .num_resources = ARRAY_SIZE(nand_resources),
415};
416
417void __init at91_add_device_nand(struct atmel_nand_data *data)
418{
419 unsigned long csa;
420
421 if (!data)
422 return;
423
424 csa = at91_sys_read(AT91_MATRIX_EBICSA);
425 at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
426
427 /* enable pin */
428 if (gpio_is_valid(data->enable_pin))
429 at91_set_gpio_output(data->enable_pin, 1);
430
431 /* ready/busy pin */
432 if (gpio_is_valid(data->rdy_pin))
433 at91_set_gpio_input(data->rdy_pin, 1);
434
435 /* card detect pin */
436 if (gpio_is_valid(data->det_pin))
437 at91_set_gpio_input(data->det_pin, 1);
438
439 nand_data = *data;
440 platform_device_register(&at91cap9_nand_device);
441}
442#else
443void __init at91_add_device_nand(struct atmel_nand_data *data) {}
444#endif
445
446
447/* --------------------------------------------------------------------
448 * TWI (i2c)
449 * -------------------------------------------------------------------- */
450
451/*
452 * Prefer the GPIO code since the TWI controller isn't robust
453 * (gets overruns and underruns under load) and can only issue
454 * repeated STARTs in one scenario (the driver doesn't yet handle them).
455 */
456#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
457
458static struct i2c_gpio_platform_data pdata = {
459 .sda_pin = AT91_PIN_PB4,
460 .sda_is_open_drain = 1,
461 .scl_pin = AT91_PIN_PB5,
462 .scl_is_open_drain = 1,
463 .udelay = 2, /* ~100 kHz */
464};
465
466static struct platform_device at91cap9_twi_device = {
467 .name = "i2c-gpio",
468 .id = -1,
469 .dev.platform_data = &pdata,
470};
471
472void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
473{
474 at91_set_GPIO_periph(AT91_PIN_PB4, 1); /* TWD (SDA) */
475 at91_set_multi_drive(AT91_PIN_PB4, 1);
476
477 at91_set_GPIO_periph(AT91_PIN_PB5, 1); /* TWCK (SCL) */
478 at91_set_multi_drive(AT91_PIN_PB5, 1);
479
480 i2c_register_board_info(0, devices, nr_devices);
481 platform_device_register(&at91cap9_twi_device);
482}
483
484#elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
485
486static struct resource twi_resources[] = {
487 [0] = {
488 .start = AT91CAP9_BASE_TWI,
489 .end = AT91CAP9_BASE_TWI + SZ_16K - 1,
490 .flags = IORESOURCE_MEM,
491 },
492 [1] = {
493 .start = AT91CAP9_ID_TWI,
494 .end = AT91CAP9_ID_TWI,
495 .flags = IORESOURCE_IRQ,
496 },
497};
498
499static struct platform_device at91cap9_twi_device = {
500 .name = "at91_i2c",
501 .id = -1,
502 .resource = twi_resources,
503 .num_resources = ARRAY_SIZE(twi_resources),
504};
505
506void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
507{
508 /* pins used for TWI interface */
509 at91_set_B_periph(AT91_PIN_PB4, 0); /* TWD */
510 at91_set_multi_drive(AT91_PIN_PB4, 1);
511
512 at91_set_B_periph(AT91_PIN_PB5, 0); /* TWCK */
513 at91_set_multi_drive(AT91_PIN_PB5, 1);
514
515 i2c_register_board_info(0, devices, nr_devices);
516 platform_device_register(&at91cap9_twi_device);
517}
518#else
519void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {}
520#endif
521
522/* --------------------------------------------------------------------
523 * SPI
524 * -------------------------------------------------------------------- */
525
526#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
527static u64 spi_dmamask = DMA_BIT_MASK(32);
528
529static struct resource spi0_resources[] = {
530 [0] = {
531 .start = AT91CAP9_BASE_SPI0,
532 .end = AT91CAP9_BASE_SPI0 + SZ_16K - 1,
533 .flags = IORESOURCE_MEM,
534 },
535 [1] = {
536 .start = AT91CAP9_ID_SPI0,
537 .end = AT91CAP9_ID_SPI0,
538 .flags = IORESOURCE_IRQ,
539 },
540};
541
542static struct platform_device at91cap9_spi0_device = {
543 .name = "atmel_spi",
544 .id = 0,
545 .dev = {
546 .dma_mask = &spi_dmamask,
547 .coherent_dma_mask = DMA_BIT_MASK(32),
548 },
549 .resource = spi0_resources,
550 .num_resources = ARRAY_SIZE(spi0_resources),
551};
552
553static const unsigned spi0_standard_cs[4] = { AT91_PIN_PA5, AT91_PIN_PA3, AT91_PIN_PD0, AT91_PIN_PD1 };
554
555static struct resource spi1_resources[] = {
556 [0] = {
557 .start = AT91CAP9_BASE_SPI1,
558 .end = AT91CAP9_BASE_SPI1 + SZ_16K - 1,
559 .flags = IORESOURCE_MEM,
560 },
561 [1] = {
562 .start = AT91CAP9_ID_SPI1,
563 .end = AT91CAP9_ID_SPI1,
564 .flags = IORESOURCE_IRQ,
565 },
566};
567
568static struct platform_device at91cap9_spi1_device = {
569 .name = "atmel_spi",
570 .id = 1,
571 .dev = {
572 .dma_mask = &spi_dmamask,
573 .coherent_dma_mask = DMA_BIT_MASK(32),
574 },
575 .resource = spi1_resources,
576 .num_resources = ARRAY_SIZE(spi1_resources),
577};
578
579static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB15, AT91_PIN_PB16, AT91_PIN_PB17, AT91_PIN_PB18 };
580
581void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
582{
583 int i;
584 unsigned long cs_pin;
585 short enable_spi0 = 0;
586 short enable_spi1 = 0;
587
588 /* Choose SPI chip-selects */
589 for (i = 0; i < nr_devices; i++) {
590 if (devices[i].controller_data)
591 cs_pin = (unsigned long) devices[i].controller_data;
592 else if (devices[i].bus_num == 0)
593 cs_pin = spi0_standard_cs[devices[i].chip_select];
594 else
595 cs_pin = spi1_standard_cs[devices[i].chip_select];
596
597 if (devices[i].bus_num == 0)
598 enable_spi0 = 1;
599 else
600 enable_spi1 = 1;
601
602 /* enable chip-select pin */
603 at91_set_gpio_output(cs_pin, 1);
604
605 /* pass chip-select pin to driver */
606 devices[i].controller_data = (void *) cs_pin;
607 }
608
609 spi_register_board_info(devices, nr_devices);
610
611 /* Configure SPI bus(es) */
612 if (enable_spi0) {
613 at91_set_B_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
614 at91_set_B_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
615 at91_set_B_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */
616
617 platform_device_register(&at91cap9_spi0_device);
618 }
619 if (enable_spi1) {
620 at91_set_A_periph(AT91_PIN_PB12, 0); /* SPI1_MISO */
621 at91_set_A_periph(AT91_PIN_PB13, 0); /* SPI1_MOSI */
622 at91_set_A_periph(AT91_PIN_PB14, 0); /* SPI1_SPCK */
623
624 platform_device_register(&at91cap9_spi1_device);
625 }
626}
627#else
628void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
629#endif
630
631
632/* --------------------------------------------------------------------
633 * Timer/Counter block
634 * -------------------------------------------------------------------- */
635
636#ifdef CONFIG_ATMEL_TCLIB
637
638static struct resource tcb_resources[] = {
639 [0] = {
640 .start = AT91CAP9_BASE_TCB0,
641 .end = AT91CAP9_BASE_TCB0 + SZ_16K - 1,
642 .flags = IORESOURCE_MEM,
643 },
644 [1] = {
645 .start = AT91CAP9_ID_TCB,
646 .end = AT91CAP9_ID_TCB,
647 .flags = IORESOURCE_IRQ,
648 },
649};
650
651static struct platform_device at91cap9_tcb_device = {
652 .name = "atmel_tcb",
653 .id = 0,
654 .resource = tcb_resources,
655 .num_resources = ARRAY_SIZE(tcb_resources),
656};
657
658static void __init at91_add_device_tc(void)
659{
660 platform_device_register(&at91cap9_tcb_device);
661}
662#else
663static void __init at91_add_device_tc(void) { }
664#endif
665
666
667/* --------------------------------------------------------------------
668 * RTT
669 * -------------------------------------------------------------------- */
670
671static struct resource rtt_resources[] = {
672 {
673 .start = AT91CAP9_BASE_RTT,
674 .end = AT91CAP9_BASE_RTT + SZ_16 - 1,
675 .flags = IORESOURCE_MEM,
676 }
677};
678
679static struct platform_device at91cap9_rtt_device = {
680 .name = "at91_rtt",
681 .id = 0,
682 .resource = rtt_resources,
683 .num_resources = ARRAY_SIZE(rtt_resources),
684};
685
686static void __init at91_add_device_rtt(void)
687{
688 platform_device_register(&at91cap9_rtt_device);
689}
690
691
692/* --------------------------------------------------------------------
693 * Watchdog
694 * -------------------------------------------------------------------- */
695
696#if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
697static struct resource wdt_resources[] = {
698 {
699 .start = AT91CAP9_BASE_WDT,
700 .end = AT91CAP9_BASE_WDT + SZ_16 - 1,
701 .flags = IORESOURCE_MEM,
702 }
703};
704
705static struct platform_device at91cap9_wdt_device = {
706 .name = "at91_wdt",
707 .id = -1,
708 .resource = wdt_resources,
709 .num_resources = ARRAY_SIZE(wdt_resources),
710};
711
712static void __init at91_add_device_watchdog(void)
713{
714 platform_device_register(&at91cap9_wdt_device);
715}
716#else
717static void __init at91_add_device_watchdog(void) {}
718#endif
719
720
721/* --------------------------------------------------------------------
722 * PWM
723 * --------------------------------------------------------------------*/
724
725#if defined(CONFIG_ATMEL_PWM)
726static u32 pwm_mask;
727
728static struct resource pwm_resources[] = {
729 [0] = {
730 .start = AT91CAP9_BASE_PWMC,
731 .end = AT91CAP9_BASE_PWMC + SZ_16K - 1,
732 .flags = IORESOURCE_MEM,
733 },
734 [1] = {
735 .start = AT91CAP9_ID_PWMC,
736 .end = AT91CAP9_ID_PWMC,
737 .flags = IORESOURCE_IRQ,
738 },
739};
740
741static struct platform_device at91cap9_pwm0_device = {
742 .name = "atmel_pwm",
743 .id = -1,
744 .dev = {
745 .platform_data = &pwm_mask,
746 },
747 .resource = pwm_resources,
748 .num_resources = ARRAY_SIZE(pwm_resources),
749};
750
751void __init at91_add_device_pwm(u32 mask)
752{
753 if (mask & (1 << AT91_PWM0))
754 at91_set_A_periph(AT91_PIN_PB19, 1); /* enable PWM0 */
755
756 if (mask & (1 << AT91_PWM1))
757 at91_set_B_periph(AT91_PIN_PB8, 1); /* enable PWM1 */
758
759 if (mask & (1 << AT91_PWM2))
760 at91_set_B_periph(AT91_PIN_PC29, 1); /* enable PWM2 */
761
762 if (mask & (1 << AT91_PWM3))
763 at91_set_B_periph(AT91_PIN_PA11, 1); /* enable PWM3 */
764
765 pwm_mask = mask;
766
767 platform_device_register(&at91cap9_pwm0_device);
768}
769#else
770void __init at91_add_device_pwm(u32 mask) {}
771#endif
772
773
774
775/* --------------------------------------------------------------------
776 * AC97
777 * -------------------------------------------------------------------- */
778
779#if defined(CONFIG_SND_ATMEL_AC97C) || defined(CONFIG_SND_ATMEL_AC97C_MODULE)
780static u64 ac97_dmamask = DMA_BIT_MASK(32);
781static struct ac97c_platform_data ac97_data;
782
783static struct resource ac97_resources[] = {
784 [0] = {
785 .start = AT91CAP9_BASE_AC97C,
786 .end = AT91CAP9_BASE_AC97C + SZ_16K - 1,
787 .flags = IORESOURCE_MEM,
788 },
789 [1] = {
790 .start = AT91CAP9_ID_AC97C,
791 .end = AT91CAP9_ID_AC97C,
792 .flags = IORESOURCE_IRQ,
793 },
794};
795
796static struct platform_device at91cap9_ac97_device = {
797 .name = "atmel_ac97c",
798 .id = 1,
799 .dev = {
800 .dma_mask = &ac97_dmamask,
801 .coherent_dma_mask = DMA_BIT_MASK(32),
802 .platform_data = &ac97_data,
803 },
804 .resource = ac97_resources,
805 .num_resources = ARRAY_SIZE(ac97_resources),
806};
807
808void __init at91_add_device_ac97(struct ac97c_platform_data *data)
809{
810 if (!data)
811 return;
812
813 at91_set_A_periph(AT91_PIN_PA6, 0); /* AC97FS */
814 at91_set_A_periph(AT91_PIN_PA7, 0); /* AC97CK */
815 at91_set_A_periph(AT91_PIN_PA8, 0); /* AC97TX */
816 at91_set_A_periph(AT91_PIN_PA9, 0); /* AC97RX */
817
818 /* reset */
819 if (gpio_is_valid(data->reset_pin))
820 at91_set_gpio_output(data->reset_pin, 0);
821
822 ac97_data = *data;
823 platform_device_register(&at91cap9_ac97_device);
824}
825#else
826void __init at91_add_device_ac97(struct ac97c_platform_data *data) {}
827#endif
828
829
830/* --------------------------------------------------------------------
831 * LCD Controller
832 * -------------------------------------------------------------------- */
833
834#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
835static u64 lcdc_dmamask = DMA_BIT_MASK(32);
836static struct atmel_lcdfb_info lcdc_data;
837
838static struct resource lcdc_resources[] = {
839 [0] = {
840 .start = AT91CAP9_LCDC_BASE,
841 .end = AT91CAP9_LCDC_BASE + SZ_4K - 1,
842 .flags = IORESOURCE_MEM,
843 },
844 [1] = {
845 .start = AT91CAP9_ID_LCDC,
846 .end = AT91CAP9_ID_LCDC,
847 .flags = IORESOURCE_IRQ,
848 },
849};
850
851static struct platform_device at91_lcdc_device = {
852 .name = "atmel_lcdfb",
853 .id = 0,
854 .dev = {
855 .dma_mask = &lcdc_dmamask,
856 .coherent_dma_mask = DMA_BIT_MASK(32),
857 .platform_data = &lcdc_data,
858 },
859 .resource = lcdc_resources,
860 .num_resources = ARRAY_SIZE(lcdc_resources),
861};
862
863void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
864{
865 if (!data)
866 return;
867
868 if (cpu_is_at91cap9_revB())
869 irq_set_irq_type(AT91CAP9_ID_LCDC, IRQ_TYPE_LEVEL_HIGH);
870
871 at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */
872 at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */
873 at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDDEN */
874 at91_set_B_periph(AT91_PIN_PB9, 0); /* LCDCC */
875 at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDD2 */
876 at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDD3 */
877 at91_set_A_periph(AT91_PIN_PC8, 0); /* LCDD4 */
878 at91_set_A_periph(AT91_PIN_PC9, 0); /* LCDD5 */
879 at91_set_A_periph(AT91_PIN_PC10, 0); /* LCDD6 */
880 at91_set_A_periph(AT91_PIN_PC11, 0); /* LCDD7 */
881 at91_set_A_periph(AT91_PIN_PC14, 0); /* LCDD10 */
882 at91_set_A_periph(AT91_PIN_PC15, 0); /* LCDD11 */
883 at91_set_A_periph(AT91_PIN_PC16, 0); /* LCDD12 */
884 at91_set_A_periph(AT91_PIN_PC17, 0); /* LCDD13 */
885 at91_set_A_periph(AT91_PIN_PC18, 0); /* LCDD14 */
886 at91_set_A_periph(AT91_PIN_PC19, 0); /* LCDD15 */
887 at91_set_A_periph(AT91_PIN_PC22, 0); /* LCDD18 */
888 at91_set_A_periph(AT91_PIN_PC23, 0); /* LCDD19 */
889 at91_set_A_periph(AT91_PIN_PC24, 0); /* LCDD20 */
890 at91_set_A_periph(AT91_PIN_PC25, 0); /* LCDD21 */
891 at91_set_A_periph(AT91_PIN_PC26, 0); /* LCDD22 */
892 at91_set_A_periph(AT91_PIN_PC27, 0); /* LCDD23 */
893
894 lcdc_data = *data;
895 platform_device_register(&at91_lcdc_device);
896}
897#else
898void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
899#endif
900
901
902/* --------------------------------------------------------------------
903 * SSC -- Synchronous Serial Controller
904 * -------------------------------------------------------------------- */
905
906#if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
907static u64 ssc0_dmamask = DMA_BIT_MASK(32);
908
909static struct resource ssc0_resources[] = {
910 [0] = {
911 .start = AT91CAP9_BASE_SSC0,
912 .end = AT91CAP9_BASE_SSC0 + SZ_16K - 1,
913 .flags = IORESOURCE_MEM,
914 },
915 [1] = {
916 .start = AT91CAP9_ID_SSC0,
917 .end = AT91CAP9_ID_SSC0,
918 .flags = IORESOURCE_IRQ,
919 },
920};
921
922static struct platform_device at91cap9_ssc0_device = {
923 .name = "ssc",
924 .id = 0,
925 .dev = {
926 .dma_mask = &ssc0_dmamask,
927 .coherent_dma_mask = DMA_BIT_MASK(32),
928 },
929 .resource = ssc0_resources,
930 .num_resources = ARRAY_SIZE(ssc0_resources),
931};
932
933static inline void configure_ssc0_pins(unsigned pins)
934{
935 if (pins & ATMEL_SSC_TF)
936 at91_set_A_periph(AT91_PIN_PB0, 1);
937 if (pins & ATMEL_SSC_TK)
938 at91_set_A_periph(AT91_PIN_PB1, 1);
939 if (pins & ATMEL_SSC_TD)
940 at91_set_A_periph(AT91_PIN_PB2, 1);
941 if (pins & ATMEL_SSC_RD)
942 at91_set_A_periph(AT91_PIN_PB3, 1);
943 if (pins & ATMEL_SSC_RK)
944 at91_set_A_periph(AT91_PIN_PB4, 1);
945 if (pins & ATMEL_SSC_RF)
946 at91_set_A_periph(AT91_PIN_PB5, 1);
947}
948
949static u64 ssc1_dmamask = DMA_BIT_MASK(32);
950
951static struct resource ssc1_resources[] = {
952 [0] = {
953 .start = AT91CAP9_BASE_SSC1,
954 .end = AT91CAP9_BASE_SSC1 + SZ_16K - 1,
955 .flags = IORESOURCE_MEM,
956 },
957 [1] = {
958 .start = AT91CAP9_ID_SSC1,
959 .end = AT91CAP9_ID_SSC1,
960 .flags = IORESOURCE_IRQ,
961 },
962};
963
964static struct platform_device at91cap9_ssc1_device = {
965 .name = "ssc",
966 .id = 1,
967 .dev = {
968 .dma_mask = &ssc1_dmamask,
969 .coherent_dma_mask = DMA_BIT_MASK(32),
970 },
971 .resource = ssc1_resources,
972 .num_resources = ARRAY_SIZE(ssc1_resources),
973};
974
975static inline void configure_ssc1_pins(unsigned pins)
976{
977 if (pins & ATMEL_SSC_TF)
978 at91_set_A_periph(AT91_PIN_PB6, 1);
979 if (pins & ATMEL_SSC_TK)
980 at91_set_A_periph(AT91_PIN_PB7, 1);
981 if (pins & ATMEL_SSC_TD)
982 at91_set_A_periph(AT91_PIN_PB8, 1);
983 if (pins & ATMEL_SSC_RD)
984 at91_set_A_periph(AT91_PIN_PB9, 1);
985 if (pins & ATMEL_SSC_RK)
986 at91_set_A_periph(AT91_PIN_PB10, 1);
987 if (pins & ATMEL_SSC_RF)
988 at91_set_A_periph(AT91_PIN_PB11, 1);
989}
990
991/*
992 * SSC controllers are accessed through library code, instead of any
993 * kind of all-singing/all-dancing driver. For example one could be
994 * used by a particular I2S audio codec's driver, while another one
995 * on the same system might be used by a custom data capture driver.
996 */
997void __init at91_add_device_ssc(unsigned id, unsigned pins)
998{
999 struct platform_device *pdev;
1000
1001 /*
1002 * NOTE: caller is responsible for passing information matching
1003 * "pins" to whatever will be using each particular controller.
1004 */
1005 switch (id) {
1006 case AT91CAP9_ID_SSC0:
1007 pdev = &at91cap9_ssc0_device;
1008 configure_ssc0_pins(pins);
1009 break;
1010 case AT91CAP9_ID_SSC1:
1011 pdev = &at91cap9_ssc1_device;
1012 configure_ssc1_pins(pins);
1013 break;
1014 default:
1015 return;
1016 }
1017
1018 platform_device_register(pdev);
1019}
1020
1021#else
1022void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
1023#endif
1024
1025
1026/* --------------------------------------------------------------------
1027 * UART
1028 * -------------------------------------------------------------------- */
1029
1030#if defined(CONFIG_SERIAL_ATMEL)
1031static struct resource dbgu_resources[] = {
1032 [0] = {
1033 .start = AT91CAP9_BASE_DBGU,
1034 .end = AT91CAP9_BASE_DBGU + SZ_512 - 1,
1035 .flags = IORESOURCE_MEM,
1036 },
1037 [1] = {
1038 .start = AT91_ID_SYS,
1039 .end = AT91_ID_SYS,
1040 .flags = IORESOURCE_IRQ,
1041 },
1042};
1043
1044static struct atmel_uart_data dbgu_data = {
1045 .use_dma_tx = 0,
1046 .use_dma_rx = 0, /* DBGU not capable of receive DMA */
1047};
1048
1049static u64 dbgu_dmamask = DMA_BIT_MASK(32);
1050
1051static struct platform_device at91cap9_dbgu_device = {
1052 .name = "atmel_usart",
1053 .id = 0,
1054 .dev = {
1055 .dma_mask = &dbgu_dmamask,
1056 .coherent_dma_mask = DMA_BIT_MASK(32),
1057 .platform_data = &dbgu_data,
1058 },
1059 .resource = dbgu_resources,
1060 .num_resources = ARRAY_SIZE(dbgu_resources),
1061};
1062
1063static inline void configure_dbgu_pins(void)
1064{
1065 at91_set_A_periph(AT91_PIN_PC30, 0); /* DRXD */
1066 at91_set_A_periph(AT91_PIN_PC31, 1); /* DTXD */
1067}
1068
1069static struct resource uart0_resources[] = {
1070 [0] = {
1071 .start = AT91CAP9_BASE_US0,
1072 .end = AT91CAP9_BASE_US0 + SZ_16K - 1,
1073 .flags = IORESOURCE_MEM,
1074 },
1075 [1] = {
1076 .start = AT91CAP9_ID_US0,
1077 .end = AT91CAP9_ID_US0,
1078 .flags = IORESOURCE_IRQ,
1079 },
1080};
1081
1082static struct atmel_uart_data uart0_data = {
1083 .use_dma_tx = 1,
1084 .use_dma_rx = 1,
1085};
1086
1087static u64 uart0_dmamask = DMA_BIT_MASK(32);
1088
1089static struct platform_device at91cap9_uart0_device = {
1090 .name = "atmel_usart",
1091 .id = 1,
1092 .dev = {
1093 .dma_mask = &uart0_dmamask,
1094 .coherent_dma_mask = DMA_BIT_MASK(32),
1095 .platform_data = &uart0_data,
1096 },
1097 .resource = uart0_resources,
1098 .num_resources = ARRAY_SIZE(uart0_resources),
1099};
1100
1101static inline void configure_usart0_pins(unsigned pins)
1102{
1103 at91_set_A_periph(AT91_PIN_PA22, 1); /* TXD0 */
1104 at91_set_A_periph(AT91_PIN_PA23, 0); /* RXD0 */
1105
1106 if (pins & ATMEL_UART_RTS)
1107 at91_set_A_periph(AT91_PIN_PA24, 0); /* RTS0 */
1108 if (pins & ATMEL_UART_CTS)
1109 at91_set_A_periph(AT91_PIN_PA25, 0); /* CTS0 */
1110}
1111
1112static struct resource uart1_resources[] = {
1113 [0] = {
1114 .start = AT91CAP9_BASE_US1,
1115 .end = AT91CAP9_BASE_US1 + SZ_16K - 1,
1116 .flags = IORESOURCE_MEM,
1117 },
1118 [1] = {
1119 .start = AT91CAP9_ID_US1,
1120 .end = AT91CAP9_ID_US1,
1121 .flags = IORESOURCE_IRQ,
1122 },
1123};
1124
1125static struct atmel_uart_data uart1_data = {
1126 .use_dma_tx = 1,
1127 .use_dma_rx = 1,
1128};
1129
1130static u64 uart1_dmamask = DMA_BIT_MASK(32);
1131
1132static struct platform_device at91cap9_uart1_device = {
1133 .name = "atmel_usart",
1134 .id = 2,
1135 .dev = {
1136 .dma_mask = &uart1_dmamask,
1137 .coherent_dma_mask = DMA_BIT_MASK(32),
1138 .platform_data = &uart1_data,
1139 },
1140 .resource = uart1_resources,
1141 .num_resources = ARRAY_SIZE(uart1_resources),
1142};
1143
1144static inline void configure_usart1_pins(unsigned pins)
1145{
1146 at91_set_A_periph(AT91_PIN_PD0, 1); /* TXD1 */
1147 at91_set_A_periph(AT91_PIN_PD1, 0); /* RXD1 */
1148
1149 if (pins & ATMEL_UART_RTS)
1150 at91_set_B_periph(AT91_PIN_PD7, 0); /* RTS1 */
1151 if (pins & ATMEL_UART_CTS)
1152 at91_set_B_periph(AT91_PIN_PD8, 0); /* CTS1 */
1153}
1154
1155static struct resource uart2_resources[] = {
1156 [0] = {
1157 .start = AT91CAP9_BASE_US2,
1158 .end = AT91CAP9_BASE_US2 + SZ_16K - 1,
1159 .flags = IORESOURCE_MEM,
1160 },
1161 [1] = {
1162 .start = AT91CAP9_ID_US2,
1163 .end = AT91CAP9_ID_US2,
1164 .flags = IORESOURCE_IRQ,
1165 },
1166};
1167
1168static struct atmel_uart_data uart2_data = {
1169 .use_dma_tx = 1,
1170 .use_dma_rx = 1,
1171};
1172
1173static u64 uart2_dmamask = DMA_BIT_MASK(32);
1174
1175static struct platform_device at91cap9_uart2_device = {
1176 .name = "atmel_usart",
1177 .id = 3,
1178 .dev = {
1179 .dma_mask = &uart2_dmamask,
1180 .coherent_dma_mask = DMA_BIT_MASK(32),
1181 .platform_data = &uart2_data,
1182 },
1183 .resource = uart2_resources,
1184 .num_resources = ARRAY_SIZE(uart2_resources),
1185};
1186
1187static inline void configure_usart2_pins(unsigned pins)
1188{
1189 at91_set_A_periph(AT91_PIN_PD2, 1); /* TXD2 */
1190 at91_set_A_periph(AT91_PIN_PD3, 0); /* RXD2 */
1191
1192 if (pins & ATMEL_UART_RTS)
1193 at91_set_B_periph(AT91_PIN_PD5, 0); /* RTS2 */
1194 if (pins & ATMEL_UART_CTS)
1195 at91_set_B_periph(AT91_PIN_PD6, 0); /* CTS2 */
1196}
1197
1198static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
1199struct platform_device *atmel_default_console_device; /* the serial console device */
1200
1201void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1202{
1203 struct platform_device *pdev;
1204 struct atmel_uart_data *pdata;
1205
1206 switch (id) {
1207 case 0: /* DBGU */
1208 pdev = &at91cap9_dbgu_device;
1209 configure_dbgu_pins();
1210 break;
1211 case AT91CAP9_ID_US0:
1212 pdev = &at91cap9_uart0_device;
1213 configure_usart0_pins(pins);
1214 break;
1215 case AT91CAP9_ID_US1:
1216 pdev = &at91cap9_uart1_device;
1217 configure_usart1_pins(pins);
1218 break;
1219 case AT91CAP9_ID_US2:
1220 pdev = &at91cap9_uart2_device;
1221 configure_usart2_pins(pins);
1222 break;
1223 default:
1224 return;
1225 }
1226 pdata = pdev->dev.platform_data;
1227 pdata->num = portnr; /* update to mapped ID */
1228
1229 if (portnr < ATMEL_MAX_UART)
1230 at91_uarts[portnr] = pdev;
1231}
1232
1233void __init at91_set_serial_console(unsigned portnr)
1234{
1235 if (portnr < ATMEL_MAX_UART) {
1236 atmel_default_console_device = at91_uarts[portnr];
1237 at91cap9_set_console_clock(at91_uarts[portnr]->id);
1238 }
1239}
1240
1241void __init at91_add_device_serial(void)
1242{
1243 int i;
1244
1245 for (i = 0; i < ATMEL_MAX_UART; i++) {
1246 if (at91_uarts[i])
1247 platform_device_register(at91_uarts[i]);
1248 }
1249
1250 if (!atmel_default_console_device)
1251 printk(KERN_INFO "AT91: No default serial console defined.\n");
1252}
1253#else
1254void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
1255void __init at91_set_serial_console(unsigned portnr) {}
1256void __init at91_add_device_serial(void) {}
1257#endif
1258
1259
1260/* -------------------------------------------------------------------- */
1261/*
1262 * These devices are always present and don't need any board-specific
1263 * setup.
1264 */
1265static int __init at91_add_standard_devices(void)
1266{
1267 at91_add_device_rtt();
1268 at91_add_device_watchdog();
1269 at91_add_device_tc();
1270 return 0;
1271}
1272
1273arch_initcall(at91_add_standard_devices);
diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
index 99c3174e24a2..dd6e2de13420 100644
--- a/arch/arm/mach-at91/at91rm9200.c
+++ b/arch/arm/mach-at91/at91rm9200.c
@@ -289,6 +289,15 @@ static struct at91_gpio_bank at91rm9200_gpio[] __initdata = {
289 } 289 }
290}; 290};
291 291
292static void at91rm9200_idle(void)
293{
294 /*
295 * Disable the processor clock. The processor will be automatically
296 * re-enabled by an interrupt or by a reset.
297 */
298 at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
299}
300
292static void at91rm9200_restart(char mode, const char *cmd) 301static void at91rm9200_restart(char mode, const char *cmd)
293{ 302{
294 /* 303 /*
@@ -314,6 +323,7 @@ static void __init at91rm9200_ioremap_registers(void)
314 323
315static void __init at91rm9200_initialize(void) 324static void __init at91rm9200_initialize(void)
316{ 325{
326 arm_pm_idle = at91rm9200_idle;
317 arm_pm_restart = at91rm9200_restart; 327 arm_pm_restart = at91rm9200_restart;
318 at91_extern_irq = (1 << AT91RM9200_ID_IRQ0) | (1 << AT91RM9200_ID_IRQ1) 328 at91_extern_irq = (1 << AT91RM9200_ID_IRQ0) | (1 << AT91RM9200_ID_IRQ1)
319 | (1 << AT91RM9200_ID_IRQ2) | (1 << AT91RM9200_ID_IRQ3) 329 | (1 << AT91RM9200_ID_IRQ2) | (1 << AT91RM9200_ID_IRQ3)
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index d4036ba43612..9ac8c6fe3363 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -12,6 +12,7 @@
12 12
13#include <linux/module.h> 13#include <linux/module.h>
14 14
15#include <asm/proc-fns.h>
15#include <asm/irq.h> 16#include <asm/irq.h>
16#include <asm/mach/arch.h> 17#include <asm/mach/arch.h>
17#include <asm/mach/map.h> 18#include <asm/mach/map.h>
@@ -328,8 +329,15 @@ static void __init at91sam9260_ioremap_registers(void)
328 at91sam9_ioremap_smc(0, AT91SAM9260_BASE_SMC); 329 at91sam9_ioremap_smc(0, AT91SAM9260_BASE_SMC);
329} 330}
330 331
332static void at91sam9260_idle(void)
333{
334 at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
335 cpu_do_idle();
336}
337
331static void __init at91sam9260_initialize(void) 338static void __init at91sam9260_initialize(void)
332{ 339{
340 arm_pm_idle = at91sam9260_idle;
333 arm_pm_restart = at91sam9_alt_restart; 341 arm_pm_restart = at91sam9_alt_restart;
334 at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1) 342 at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
335 | (1 << AT91SAM9260_ID_IRQ2); 343 | (1 << AT91SAM9260_ID_IRQ2);
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index 023c2ff138df..ab76868f01f5 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -12,6 +12,7 @@
12 12
13#include <linux/module.h> 13#include <linux/module.h>
14 14
15#include <asm/proc-fns.h>
15#include <asm/irq.h> 16#include <asm/irq.h>
16#include <asm/mach/arch.h> 17#include <asm/mach/arch.h>
17#include <asm/mach/map.h> 18#include <asm/mach/map.h>
@@ -286,8 +287,15 @@ static void __init at91sam9261_ioremap_registers(void)
286 at91sam9_ioremap_smc(0, AT91SAM9261_BASE_SMC); 287 at91sam9_ioremap_smc(0, AT91SAM9261_BASE_SMC);
287} 288}
288 289
290static void at91sam9261_idle(void)
291{
292 at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
293 cpu_do_idle();
294}
295
289static void __init at91sam9261_initialize(void) 296static void __init at91sam9261_initialize(void)
290{ 297{
298 arm_pm_idle = at91sam9261_idle;
291 arm_pm_restart = at91sam9_alt_restart; 299 arm_pm_restart = at91sam9_alt_restart;
292 at91_extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1) 300 at91_extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1)
293 | (1 << AT91SAM9261_ID_IRQ2); 301 | (1 << AT91SAM9261_ID_IRQ2);
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index 75e876c258af..247ab633abcc 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -12,6 +12,7 @@
12 12
13#include <linux/module.h> 13#include <linux/module.h>
14 14
15#include <asm/proc-fns.h>
15#include <asm/irq.h> 16#include <asm/irq.h>
16#include <asm/mach/arch.h> 17#include <asm/mach/arch.h>
17#include <asm/mach/map.h> 18#include <asm/mach/map.h>
@@ -307,8 +308,15 @@ static void __init at91sam9263_ioremap_registers(void)
307 at91sam9_ioremap_smc(1, AT91SAM9263_BASE_SMC1); 308 at91sam9_ioremap_smc(1, AT91SAM9263_BASE_SMC1);
308} 309}
309 310
311static void at91sam9263_idle(void)
312{
313 at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
314 cpu_do_idle();
315}
316
310static void __init at91sam9263_initialize(void) 317static void __init at91sam9263_initialize(void)
311{ 318{
319 arm_pm_idle = at91sam9263_idle;
312 arm_pm_restart = at91sam9_alt_restart; 320 arm_pm_restart = at91sam9_alt_restart;
313 at91_extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1); 321 at91_extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1);
314 322
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
index 7b46b2787022..49aa6a9f4323 100644
--- a/arch/arm/mach-at91/at91sam9263_devices.c
+++ b/arch/arm/mach-at91/at91sam9263_devices.c
@@ -891,7 +891,8 @@ static struct platform_device at91sam9263_isi_device = {
891 .num_resources = ARRAY_SIZE(isi_resources), 891 .num_resources = ARRAY_SIZE(isi_resources),
892}; 892};
893 893
894void __init at91_add_device_isi(void) 894void __init at91_add_device_isi(struct isi_platform_data *data,
895 bool use_pck_as_mck)
895{ 896{
896 at91_set_A_periph(AT91_PIN_PE0, 0); /* ISI_D0 */ 897 at91_set_A_periph(AT91_PIN_PE0, 0); /* ISI_D0 */
897 at91_set_A_periph(AT91_PIN_PE1, 0); /* ISI_D1 */ 898 at91_set_A_periph(AT91_PIN_PE1, 0); /* ISI_D1 */
@@ -904,14 +905,20 @@ void __init at91_add_device_isi(void)
904 at91_set_A_periph(AT91_PIN_PE8, 0); /* ISI_PCK */ 905 at91_set_A_periph(AT91_PIN_PE8, 0); /* ISI_PCK */
905 at91_set_A_periph(AT91_PIN_PE9, 0); /* ISI_HSYNC */ 906 at91_set_A_periph(AT91_PIN_PE9, 0); /* ISI_HSYNC */
906 at91_set_A_periph(AT91_PIN_PE10, 0); /* ISI_VSYNC */ 907 at91_set_A_periph(AT91_PIN_PE10, 0); /* ISI_VSYNC */
907 at91_set_B_periph(AT91_PIN_PE11, 0); /* ISI_MCK (PCK3) */
908 at91_set_B_periph(AT91_PIN_PE12, 0); /* ISI_PD8 */ 908 at91_set_B_periph(AT91_PIN_PE12, 0); /* ISI_PD8 */
909 at91_set_B_periph(AT91_PIN_PE13, 0); /* ISI_PD9 */ 909 at91_set_B_periph(AT91_PIN_PE13, 0); /* ISI_PD9 */
910 at91_set_B_periph(AT91_PIN_PE14, 0); /* ISI_PD10 */ 910 at91_set_B_periph(AT91_PIN_PE14, 0); /* ISI_PD10 */
911 at91_set_B_periph(AT91_PIN_PE15, 0); /* ISI_PD11 */ 911 at91_set_B_periph(AT91_PIN_PE15, 0); /* ISI_PD11 */
912
913 if (use_pck_as_mck) {
914 at91_set_B_periph(AT91_PIN_PE11, 0); /* ISI_MCK (PCK3) */
915
916 /* TODO: register the PCK for ISI_MCK and set its parent */
917 }
912} 918}
913#else 919#else
914void __init at91_add_device_isi(void) {} 920void __init at91_add_device_isi(struct isi_platform_data *data,
921 bool use_pck_as_mck) {}
915#endif 922#endif
916 923
917 924
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index 1cb6a96b1c1e..5b12192e52ec 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -317,6 +317,12 @@ static struct at91_gpio_bank at91sam9g45_gpio[] __initdata = {
317 } 317 }
318}; 318};
319 319
320static void at91sam9g45_idle(void)
321{
322 at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
323 cpu_do_idle();
324}
325
320/* -------------------------------------------------------------------- 326/* --------------------------------------------------------------------
321 * AT91SAM9G45 processor initialization 327 * AT91SAM9G45 processor initialization
322 * -------------------------------------------------------------------- */ 328 * -------------------------------------------------------------------- */
@@ -337,6 +343,7 @@ static void __init at91sam9g45_ioremap_registers(void)
337 343
338static void __init at91sam9g45_initialize(void) 344static void __init at91sam9g45_initialize(void)
339{ 345{
346 arm_pm_idle = at91sam9g45_idle;
340 arm_pm_restart = at91sam9g45_restart; 347 arm_pm_restart = at91sam9g45_restart;
341 at91_extern_irq = (1 << AT91SAM9G45_ID_IRQ0); 348 at91_extern_irq = (1 << AT91SAM9G45_ID_IRQ0);
342 349
diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c
index b7582dd10dc3..bd4e68cd3e2f 100644
--- a/arch/arm/mach-at91/at91sam9g45_devices.c
+++ b/arch/arm/mach-at91/at91sam9g45_devices.c
@@ -14,6 +14,7 @@
14 14
15#include <linux/dma-mapping.h> 15#include <linux/dma-mapping.h>
16#include <linux/gpio.h> 16#include <linux/gpio.h>
17#include <linux/clk.h>
17#include <linux/platform_device.h> 18#include <linux/platform_device.h>
18#include <linux/i2c-gpio.h> 19#include <linux/i2c-gpio.h>
19#include <linux/atmel-mci.h> 20#include <linux/atmel-mci.h>
@@ -28,7 +29,10 @@
28#include <mach/at_hdmac.h> 29#include <mach/at_hdmac.h>
29#include <mach/atmel-mci.h> 30#include <mach/atmel-mci.h>
30 31
32#include <media/atmel-isi.h>
33
31#include "generic.h" 34#include "generic.h"
35#include "clock.h"
32 36
33 37
34/* -------------------------------------------------------------------- 38/* --------------------------------------------------------------------
@@ -38,10 +42,6 @@
38#if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE) 42#if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
39static u64 hdmac_dmamask = DMA_BIT_MASK(32); 43static u64 hdmac_dmamask = DMA_BIT_MASK(32);
40 44
41static struct at_dma_platform_data atdma_pdata = {
42 .nr_channels = 8,
43};
44
45static struct resource hdmac_resources[] = { 45static struct resource hdmac_resources[] = {
46 [0] = { 46 [0] = {
47 .start = AT91SAM9G45_BASE_DMA, 47 .start = AT91SAM9G45_BASE_DMA,
@@ -56,12 +56,11 @@ static struct resource hdmac_resources[] = {
56}; 56};
57 57
58static struct platform_device at_hdmac_device = { 58static struct platform_device at_hdmac_device = {
59 .name = "at_hdmac", 59 .name = "at91sam9g45_dma",
60 .id = -1, 60 .id = -1,
61 .dev = { 61 .dev = {
62 .dma_mask = &hdmac_dmamask, 62 .dma_mask = &hdmac_dmamask,
63 .coherent_dma_mask = DMA_BIT_MASK(32), 63 .coherent_dma_mask = DMA_BIT_MASK(32),
64 .platform_data = &atdma_pdata,
65 }, 64 },
66 .resource = hdmac_resources, 65 .resource = hdmac_resources,
67 .num_resources = ARRAY_SIZE(hdmac_resources), 66 .num_resources = ARRAY_SIZE(hdmac_resources),
@@ -69,9 +68,15 @@ static struct platform_device at_hdmac_device = {
69 68
70void __init at91_add_device_hdmac(void) 69void __init at91_add_device_hdmac(void)
71{ 70{
72 dma_cap_set(DMA_MEMCPY, atdma_pdata.cap_mask); 71#if defined(CONFIG_OF)
73 dma_cap_set(DMA_SLAVE, atdma_pdata.cap_mask); 72 struct device_node *of_node =
74 platform_device_register(&at_hdmac_device); 73 of_find_node_by_name(NULL, "dma-controller");
74
75 if (of_node)
76 of_node_put(of_node);
77 else
78#endif
79 platform_device_register(&at_hdmac_device);
75} 80}
76#else 81#else
77void __init at91_add_device_hdmac(void) {} 82void __init at91_add_device_hdmac(void) {}
@@ -869,6 +874,96 @@ void __init at91_add_device_ac97(struct ac97c_platform_data *data)
869void __init at91_add_device_ac97(struct ac97c_platform_data *data) {} 874void __init at91_add_device_ac97(struct ac97c_platform_data *data) {}
870#endif 875#endif
871 876
877/* --------------------------------------------------------------------
878 * Image Sensor Interface
879 * -------------------------------------------------------------------- */
880#if defined(CONFIG_VIDEO_ATMEL_ISI) || defined(CONFIG_VIDEO_ATMEL_ISI_MODULE)
881static u64 isi_dmamask = DMA_BIT_MASK(32);
882static struct isi_platform_data isi_data;
883
884struct resource isi_resources[] = {
885 [0] = {
886 .start = AT91SAM9G45_BASE_ISI,
887 .end = AT91SAM9G45_BASE_ISI + SZ_16K - 1,
888 .flags = IORESOURCE_MEM,
889 },
890 [1] = {
891 .start = AT91SAM9G45_ID_ISI,
892 .end = AT91SAM9G45_ID_ISI,
893 .flags = IORESOURCE_IRQ,
894 },
895};
896
897static struct platform_device at91sam9g45_isi_device = {
898 .name = "atmel_isi",
899 .id = 0,
900 .dev = {
901 .dma_mask = &isi_dmamask,
902 .coherent_dma_mask = DMA_BIT_MASK(32),
903 .platform_data = &isi_data,
904 },
905 .resource = isi_resources,
906 .num_resources = ARRAY_SIZE(isi_resources),
907};
908
909static struct clk_lookup isi_mck_lookups[] = {
910 CLKDEV_CON_DEV_ID("isi_mck", "atmel_isi.0", NULL),
911};
912
913void __init at91_add_device_isi(struct isi_platform_data *data,
914 bool use_pck_as_mck)
915{
916 struct clk *pck;
917 struct clk *parent;
918
919 if (!data)
920 return;
921 isi_data = *data;
922
923 at91_set_A_periph(AT91_PIN_PB20, 0); /* ISI_D0 */
924 at91_set_A_periph(AT91_PIN_PB21, 0); /* ISI_D1 */
925 at91_set_A_periph(AT91_PIN_PB22, 0); /* ISI_D2 */
926 at91_set_A_periph(AT91_PIN_PB23, 0); /* ISI_D3 */
927 at91_set_A_periph(AT91_PIN_PB24, 0); /* ISI_D4 */
928 at91_set_A_periph(AT91_PIN_PB25, 0); /* ISI_D5 */
929 at91_set_A_periph(AT91_PIN_PB26, 0); /* ISI_D6 */
930 at91_set_A_periph(AT91_PIN_PB27, 0); /* ISI_D7 */
931 at91_set_A_periph(AT91_PIN_PB28, 0); /* ISI_PCK */
932 at91_set_A_periph(AT91_PIN_PB30, 0); /* ISI_HSYNC */
933 at91_set_A_periph(AT91_PIN_PB29, 0); /* ISI_VSYNC */
934 at91_set_B_periph(AT91_PIN_PB8, 0); /* ISI_PD8 */
935 at91_set_B_periph(AT91_PIN_PB9, 0); /* ISI_PD9 */
936 at91_set_B_periph(AT91_PIN_PB10, 0); /* ISI_PD10 */
937 at91_set_B_periph(AT91_PIN_PB11, 0); /* ISI_PD11 */
938
939 platform_device_register(&at91sam9g45_isi_device);
940
941 if (use_pck_as_mck) {
942 at91_set_B_periph(AT91_PIN_PB31, 0); /* ISI_MCK (PCK1) */
943
944 pck = clk_get(NULL, "pck1");
945 parent = clk_get(NULL, "plla");
946
947 BUG_ON(IS_ERR(pck) || IS_ERR(parent));
948
949 if (clk_set_parent(pck, parent)) {
950 pr_err("Failed to set PCK's parent\n");
951 } else {
952 /* Register PCK as ISI_MCK */
953 isi_mck_lookups[0].clk = pck;
954 clkdev_add_table(isi_mck_lookups,
955 ARRAY_SIZE(isi_mck_lookups));
956 }
957
958 clk_put(pck);
959 clk_put(parent);
960 }
961}
962#else
963void __init at91_add_device_isi(struct isi_platform_data *data,
964 bool use_pck_as_mck) {}
965#endif
966
872 967
873/* -------------------------------------------------------------------- 968/* --------------------------------------------------------------------
874 * LCD Controller 969 * LCD Controller
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
index d2c91a841cb8..fd60e226a987 100644
--- a/arch/arm/mach-at91/at91sam9rl.c
+++ b/arch/arm/mach-at91/at91sam9rl.c
@@ -11,6 +11,7 @@
11 11
12#include <linux/module.h> 12#include <linux/module.h>
13 13
14#include <asm/proc-fns.h>
14#include <asm/irq.h> 15#include <asm/irq.h>
15#include <asm/mach/arch.h> 16#include <asm/mach/arch.h>
16#include <asm/mach/map.h> 17#include <asm/mach/map.h>
@@ -291,8 +292,15 @@ static void __init at91sam9rl_ioremap_registers(void)
291 at91sam9_ioremap_smc(0, AT91SAM9RL_BASE_SMC); 292 at91sam9_ioremap_smc(0, AT91SAM9RL_BASE_SMC);
292} 293}
293 294
295static void at91sam9rl_idle(void)
296{
297 at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
298 cpu_do_idle();
299}
300
294static void __init at91sam9rl_initialize(void) 301static void __init at91sam9rl_initialize(void)
295{ 302{
303 arm_pm_idle = at91sam9rl_idle;
296 arm_pm_restart = at91sam9_alt_restart; 304 arm_pm_restart = at91sam9_alt_restart;
297 at91_extern_irq = (1 << AT91SAM9RL_ID_IRQ0); 305 at91_extern_irq = (1 << AT91SAM9RL_ID_IRQ0);
298 306
diff --git a/arch/arm/mach-at91/at91sam9rl_devices.c b/arch/arm/mach-at91/at91sam9rl_devices.c
index 61908dce9784..9be71c11d0f0 100644
--- a/arch/arm/mach-at91/at91sam9rl_devices.c
+++ b/arch/arm/mach-at91/at91sam9rl_devices.c
@@ -33,10 +33,6 @@
33#if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE) 33#if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
34static u64 hdmac_dmamask = DMA_BIT_MASK(32); 34static u64 hdmac_dmamask = DMA_BIT_MASK(32);
35 35
36static struct at_dma_platform_data atdma_pdata = {
37 .nr_channels = 2,
38};
39
40static struct resource hdmac_resources[] = { 36static struct resource hdmac_resources[] = {
41 [0] = { 37 [0] = {
42 .start = AT91SAM9RL_BASE_DMA, 38 .start = AT91SAM9RL_BASE_DMA,
@@ -51,12 +47,11 @@ static struct resource hdmac_resources[] = {
51}; 47};
52 48
53static struct platform_device at_hdmac_device = { 49static struct platform_device at_hdmac_device = {
54 .name = "at_hdmac", 50 .name = "at91sam9rl_dma",
55 .id = -1, 51 .id = -1,
56 .dev = { 52 .dev = {
57 .dma_mask = &hdmac_dmamask, 53 .dma_mask = &hdmac_dmamask,
58 .coherent_dma_mask = DMA_BIT_MASK(32), 54 .coherent_dma_mask = DMA_BIT_MASK(32),
59 .platform_data = &atdma_pdata,
60 }, 55 },
61 .resource = hdmac_resources, 56 .resource = hdmac_resources,
62 .num_resources = ARRAY_SIZE(hdmac_resources), 57 .num_resources = ARRAY_SIZE(hdmac_resources),
@@ -64,7 +59,6 @@ static struct platform_device at_hdmac_device = {
64 59
65void __init at91_add_device_hdmac(void) 60void __init at91_add_device_hdmac(void)
66{ 61{
67 dma_cap_set(DMA_MEMCPY, atdma_pdata.cap_mask);
68 platform_device_register(&at_hdmac_device); 62 platform_device_register(&at_hdmac_device);
69} 63}
70#else 64#else
diff --git a/arch/arm/mach-at91/at91x40.c b/arch/arm/mach-at91/at91x40.c
index 56ba3bd035ae..0154b7f44ff1 100644
--- a/arch/arm/mach-at91/at91x40.c
+++ b/arch/arm/mach-at91/at91x40.c
@@ -13,6 +13,7 @@
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/init.h> 14#include <linux/init.h>
15#include <linux/irq.h> 15#include <linux/irq.h>
16#include <asm/proc-fns.h>
16#include <asm/mach/arch.h> 17#include <asm/mach/arch.h>
17#include <mach/at91x40.h> 18#include <mach/at91x40.h>
18#include <mach/at91_st.h> 19#include <mach/at91_st.h>
@@ -37,8 +38,19 @@ unsigned long clk_get_rate(struct clk *clk)
37 return AT91X40_MASTER_CLOCK; 38 return AT91X40_MASTER_CLOCK;
38} 39}
39 40
41static void at91x40_idle(void)
42{
43 /*
44 * Disable the processor clock. The processor will be automatically
45 * re-enabled by an interrupt or by a reset.
46 */
47 at91_sys_write(AT91_PS_CR, AT91_PS_CR_CPU);
48 cpu_do_idle();
49}
50
40void __init at91x40_initialize(unsigned long main_clock) 51void __init at91x40_initialize(unsigned long main_clock)
41{ 52{
53 arm_pm_idle = at91x40_idle;
42 at91_extern_irq = (1 << AT91X40_ID_IRQ0) | (1 << AT91X40_ID_IRQ1) 54 at91_extern_irq = (1 << AT91X40_ID_IRQ0) | (1 << AT91X40_ID_IRQ1)
43 | (1 << AT91X40_ID_IRQ2); 55 | (1 << AT91X40_ID_IRQ2);
44} 56}
diff --git a/arch/arm/mach-at91/board-cap9adk.c b/arch/arm/mach-at91/board-cap9adk.c
deleted file mode 100644
index ac3de4f7c31d..000000000000
--- a/arch/arm/mach-at91/board-cap9adk.c
+++ /dev/null
@@ -1,396 +0,0 @@
1/*
2 * linux/arch/arm/mach-at91/board-cap9adk.c
3 *
4 * Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
5 * Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
6 * Copyright (C) 2005 SAN People
7 * Copyright (C) 2007 Atmel Corporation.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24#include <linux/types.h>
25#include <linux/gpio.h>
26#include <linux/init.h>
27#include <linux/mm.h>
28#include <linux/module.h>
29#include <linux/platform_device.h>
30#include <linux/spi/spi.h>
31#include <linux/spi/ads7846.h>
32#include <linux/fb.h>
33#include <linux/mtd/physmap.h>
34
35#include <video/atmel_lcdc.h>
36
37#include <mach/hardware.h>
38#include <asm/setup.h>
39#include <asm/mach-types.h>
40
41#include <asm/mach/arch.h>
42#include <asm/mach/map.h>
43
44#include <mach/board.h>
45#include <mach/at91cap9_matrix.h>
46#include <mach/at91sam9_smc.h>
47#include <mach/system_rev.h>
48
49#include "sam9_smc.h"
50#include "generic.h"
51
52
53static void __init cap9adk_init_early(void)
54{
55 /* Initialize processor: 12 MHz crystal */
56 at91_initialize(12000000);
57
58 /* Setup the LEDs: USER1 and USER2 LED for cpu/timer... */
59 at91_init_leds(AT91_PIN_PA10, AT91_PIN_PA11);
60 /* ... POWER LED always on */
61 at91_set_gpio_output(AT91_PIN_PC29, 1);
62
63 /* Setup the serial ports and console */
64 at91_register_uart(0, 0, 0); /* DBGU = ttyS0 */
65 at91_set_serial_console(0);
66}
67
68/*
69 * USB Host port
70 */
71static struct at91_usbh_data __initdata cap9adk_usbh_data = {
72 .ports = 2,
73 .vbus_pin = {-EINVAL, -EINVAL},
74 .overcurrent_pin= {-EINVAL, -EINVAL},
75};
76
77/*
78 * USB HS Device port
79 */
80static struct usba_platform_data __initdata cap9adk_usba_udc_data = {
81 .vbus_pin = AT91_PIN_PB31,
82};
83
84/*
85 * ADS7846 Touchscreen
86 */
87#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
88static int ads7843_pendown_state(void)
89{
90 return !at91_get_gpio_value(AT91_PIN_PC4); /* Touchscreen PENIRQ */
91}
92
93static struct ads7846_platform_data ads_info = {
94 .model = 7843,
95 .x_min = 150,
96 .x_max = 3830,
97 .y_min = 190,
98 .y_max = 3830,
99 .vref_delay_usecs = 100,
100 .x_plate_ohms = 450,
101 .y_plate_ohms = 250,
102 .pressure_max = 15000,
103 .debounce_max = 1,
104 .debounce_rep = 0,
105 .debounce_tol = (~0),
106 .get_pendown_state = ads7843_pendown_state,
107};
108
109static void __init cap9adk_add_device_ts(void)
110{
111 at91_set_gpio_input(AT91_PIN_PC4, 1); /* Touchscreen PENIRQ */
112 at91_set_gpio_input(AT91_PIN_PC5, 1); /* Touchscreen BUSY */
113}
114#else
115static void __init cap9adk_add_device_ts(void) {}
116#endif
117
118
119/*
120 * SPI devices.
121 */
122static struct spi_board_info cap9adk_spi_devices[] = {
123#if defined(CONFIG_MTD_AT91_DATAFLASH_CARD)
124 { /* DataFlash card */
125 .modalias = "mtd_dataflash",
126 .chip_select = 0,
127 .max_speed_hz = 15 * 1000 * 1000,
128 .bus_num = 0,
129 },
130#endif
131#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
132 {
133 .modalias = "ads7846",
134 .chip_select = 3, /* can be 2 or 3, depending on J2 jumper */
135 .max_speed_hz = 125000 * 26, /* (max sample rate @ 3V) * (cmd + data + overhead) */
136 .bus_num = 0,
137 .platform_data = &ads_info,
138 .irq = AT91_PIN_PC4,
139 },
140#endif
141};
142
143
144/*
145 * MCI (SD/MMC)
146 */
147static struct at91_mmc_data __initdata cap9adk_mmc_data = {
148 .wire4 = 1,
149 .det_pin = -EINVAL,
150 .wp_pin = -EINVAL,
151 .vcc_pin = -EINVAL,
152};
153
154
155/*
156 * MACB Ethernet device
157 */
158static struct macb_platform_data __initdata cap9adk_macb_data = {
159 .phy_irq_pin = -EINVAL,
160 .is_rmii = 1,
161};
162
163
164/*
165 * NAND flash
166 */
167static struct mtd_partition __initdata cap9adk_nand_partitions[] = {
168 {
169 .name = "NAND partition",
170 .offset = 0,
171 .size = MTDPART_SIZ_FULL,
172 },
173};
174
175static struct atmel_nand_data __initdata cap9adk_nand_data = {
176 .ale = 21,
177 .cle = 22,
178 .det_pin = -EINVAL,
179 .rdy_pin = -EINVAL,
180 .enable_pin = AT91_PIN_PD15,
181 .parts = cap9adk_nand_partitions,
182 .num_parts = ARRAY_SIZE(cap9adk_nand_partitions),
183};
184
185static struct sam9_smc_config __initdata cap9adk_nand_smc_config = {
186 .ncs_read_setup = 1,
187 .nrd_setup = 2,
188 .ncs_write_setup = 1,
189 .nwe_setup = 2,
190
191 .ncs_read_pulse = 6,
192 .nrd_pulse = 4,
193 .ncs_write_pulse = 6,
194 .nwe_pulse = 4,
195
196 .read_cycle = 8,
197 .write_cycle = 8,
198
199 .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE,
200 .tdf_cycles = 1,
201};
202
203static void __init cap9adk_add_device_nand(void)
204{
205 unsigned long csa;
206
207 csa = at91_sys_read(AT91_MATRIX_EBICSA);
208 at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_VDDIOMSEL_3_3V);
209
210 cap9adk_nand_data.bus_width_16 = board_have_nand_16bit();
211 /* setup bus-width (8 or 16) */
212 if (cap9adk_nand_data.bus_width_16)
213 cap9adk_nand_smc_config.mode |= AT91_SMC_DBW_16;
214 else
215 cap9adk_nand_smc_config.mode |= AT91_SMC_DBW_8;
216
217 /* configure chip-select 3 (NAND) */
218 sam9_smc_configure(0, 3, &cap9adk_nand_smc_config);
219
220 at91_add_device_nand(&cap9adk_nand_data);
221}
222
223
224/*
225 * NOR flash
226 */
227static struct mtd_partition cap9adk_nor_partitions[] = {
228 {
229 .name = "NOR partition",
230 .offset = 0,
231 .size = MTDPART_SIZ_FULL,
232 },
233};
234
235static struct physmap_flash_data cap9adk_nor_data = {
236 .width = 2,
237 .parts = cap9adk_nor_partitions,
238 .nr_parts = ARRAY_SIZE(cap9adk_nor_partitions),
239};
240
241#define NOR_BASE AT91_CHIPSELECT_0
242#define NOR_SIZE SZ_8M
243
244static struct resource nor_flash_resources[] = {
245 {
246 .start = NOR_BASE,
247 .end = NOR_BASE + NOR_SIZE - 1,
248 .flags = IORESOURCE_MEM,
249 }
250};
251
252static struct platform_device cap9adk_nor_flash = {
253 .name = "physmap-flash",
254 .id = 0,
255 .dev = {
256 .platform_data = &cap9adk_nor_data,
257 },
258 .resource = nor_flash_resources,
259 .num_resources = ARRAY_SIZE(nor_flash_resources),
260};
261
262static struct sam9_smc_config __initdata cap9adk_nor_smc_config = {
263 .ncs_read_setup = 2,
264 .nrd_setup = 4,
265 .ncs_write_setup = 2,
266 .nwe_setup = 4,
267
268 .ncs_read_pulse = 10,
269 .nrd_pulse = 8,
270 .ncs_write_pulse = 10,
271 .nwe_pulse = 8,
272
273 .read_cycle = 16,
274 .write_cycle = 16,
275
276 .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16,
277 .tdf_cycles = 1,
278};
279
280static __init void cap9adk_add_device_nor(void)
281{
282 unsigned long csa;
283
284 csa = at91_sys_read(AT91_MATRIX_EBICSA);
285 at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_VDDIOMSEL_3_3V);
286
287 /* configure chip-select 0 (NOR) */
288 sam9_smc_configure(0, 0, &cap9adk_nor_smc_config);
289
290 platform_device_register(&cap9adk_nor_flash);
291}
292
293
294/*
295 * LCD Controller
296 */
297#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
298static struct fb_videomode at91_tft_vga_modes[] = {
299 {
300 .name = "TX09D50VM1CCA @ 60",
301 .refresh = 60,
302 .xres = 240, .yres = 320,
303 .pixclock = KHZ2PICOS(4965),
304
305 .left_margin = 1, .right_margin = 33,
306 .upper_margin = 1, .lower_margin = 0,
307 .hsync_len = 5, .vsync_len = 1,
308
309 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
310 .vmode = FB_VMODE_NONINTERLACED,
311 },
312};
313
314static struct fb_monspecs at91fb_default_monspecs = {
315 .manufacturer = "HIT",
316 .monitor = "TX09D70VM1CCA",
317
318 .modedb = at91_tft_vga_modes,
319 .modedb_len = ARRAY_SIZE(at91_tft_vga_modes),
320 .hfmin = 15000,
321 .hfmax = 64000,
322 .vfmin = 50,
323 .vfmax = 150,
324};
325
326#define AT91CAP9_DEFAULT_LCDCON2 (ATMEL_LCDC_MEMOR_LITTLE \
327 | ATMEL_LCDC_DISTYPE_TFT \
328 | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE)
329
330static void at91_lcdc_power_control(int on)
331{
332 if (on)
333 at91_set_gpio_value(AT91_PIN_PC0, 0); /* power up */
334 else
335 at91_set_gpio_value(AT91_PIN_PC0, 1); /* power down */
336}
337
338/* Driver datas */
339static struct atmel_lcdfb_info __initdata cap9adk_lcdc_data = {
340 .default_bpp = 16,
341 .default_dmacon = ATMEL_LCDC_DMAEN,
342 .default_lcdcon2 = AT91CAP9_DEFAULT_LCDCON2,
343 .default_monspecs = &at91fb_default_monspecs,
344 .atmel_lcdfb_power_control = at91_lcdc_power_control,
345 .guard_time = 1,
346};
347
348#else
349static struct atmel_lcdfb_info __initdata cap9adk_lcdc_data;
350#endif
351
352
353/*
354 * AC97
355 */
356static struct ac97c_platform_data cap9adk_ac97_data = {
357 .reset_pin = -EINVAL,
358};
359
360
361static void __init cap9adk_board_init(void)
362{
363 /* Serial */
364 at91_add_device_serial();
365 /* USB Host */
366 at91_add_device_usbh(&cap9adk_usbh_data);
367 /* USB HS */
368 at91_add_device_usba(&cap9adk_usba_udc_data);
369 /* SPI */
370 at91_add_device_spi(cap9adk_spi_devices, ARRAY_SIZE(cap9adk_spi_devices));
371 /* Touchscreen */
372 cap9adk_add_device_ts();
373 /* MMC */
374 at91_add_device_mmc(1, &cap9adk_mmc_data);
375 /* Ethernet */
376 at91_add_device_eth(&cap9adk_macb_data);
377 /* NAND */
378 cap9adk_add_device_nand();
379 /* NOR Flash */
380 cap9adk_add_device_nor();
381 /* I2C */
382 at91_add_device_i2c(NULL, 0);
383 /* LCD Controller */
384 at91_add_device_lcdc(&cap9adk_lcdc_data);
385 /* AC97 */
386 at91_add_device_ac97(&cap9adk_ac97_data);
387}
388
389MACHINE_START(AT91CAP9ADK, "Atmel AT91CAP9A-DK")
390 /* Maintainer: Stelian Pop <stelian.pop@leadtechdesign.com> */
391 .timer = &at91sam926x_timer,
392 .map_io = at91_map_io,
393 .init_early = cap9adk_init_early,
394 .init_irq = at91_init_irq_default,
395 .init_machine = cap9adk_board_init,
396MACHINE_END
diff --git a/arch/arm/mach-at91/board-flexibity.c b/arch/arm/mach-at91/board-flexibity.c
index eec02cd57ced..1815152001f7 100644
--- a/arch/arm/mach-at91/board-flexibity.c
+++ b/arch/arm/mach-at91/board-flexibity.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * linux/arch/arm/mach-at91/board-flexibity.c 2 * linux/arch/arm/mach-at91/board-flexibity.c
3 * 3 *
4 * Copyright (C) 2010 Flexibity 4 * Copyright (C) 2010-2011 Flexibity
5 * Copyright (C) 2005 SAN People 5 * Copyright (C) 2005 SAN People
6 * Copyright (C) 2006 Atmel 6 * Copyright (C) 2006 Atmel
7 * 7 *
@@ -62,6 +62,13 @@ static struct at91_udc_data __initdata flexibity_udc_data = {
62 .pullup_pin = -EINVAL, /* pull-up driven by UDC */ 62 .pullup_pin = -EINVAL, /* pull-up driven by UDC */
63}; 63};
64 64
65/* I2C devices */
66static struct i2c_board_info __initdata flexibity_i2c_devices[] = {
67 {
68 I2C_BOARD_INFO("ds1307", 0x68),
69 },
70};
71
65/* SPI devices */ 72/* SPI devices */
66static struct spi_board_info flexibity_spi_devices[] = { 73static struct spi_board_info flexibity_spi_devices[] = {
67 { /* DataFlash chip */ 74 { /* DataFlash chip */
@@ -141,6 +148,9 @@ static void __init flexibity_board_init(void)
141 at91_add_device_usbh(&flexibity_usbh_data); 148 at91_add_device_usbh(&flexibity_usbh_data);
142 /* USB Device */ 149 /* USB Device */
143 at91_add_device_udc(&flexibity_udc_data); 150 at91_add_device_udc(&flexibity_udc_data);
151 /* I2C */
152 at91_add_device_i2c(flexibity_i2c_devices,
153 ARRAY_SIZE(flexibity_i2c_devices));
144 /* SPI */ 154 /* SPI */
145 at91_add_device_spi(flexibity_spi_devices, 155 at91_add_device_spi(flexibity_spi_devices,
146 ARRAY_SIZE(flexibity_spi_devices)); 156 ARRAY_SIZE(flexibity_spi_devices));
diff --git a/arch/arm/mach-at91/board-sam9m10g45ek.c b/arch/arm/mach-at91/board-sam9m10g45ek.c
index ea0d1b9c2b7b..57497e2b8878 100644
--- a/arch/arm/mach-at91/board-sam9m10g45ek.c
+++ b/arch/arm/mach-at91/board-sam9m10g45ek.c
@@ -24,11 +24,13 @@
24#include <linux/gpio_keys.h> 24#include <linux/gpio_keys.h>
25#include <linux/input.h> 25#include <linux/input.h>
26#include <linux/leds.h> 26#include <linux/leds.h>
27#include <linux/clk.h>
28#include <linux/atmel-mci.h> 27#include <linux/atmel-mci.h>
28#include <linux/delay.h>
29 29
30#include <mach/hardware.h> 30#include <mach/hardware.h>
31#include <video/atmel_lcdc.h> 31#include <video/atmel_lcdc.h>
32#include <media/soc_camera.h>
33#include <media/atmel-isi.h>
32 34
33#include <asm/setup.h> 35#include <asm/setup.h>
34#include <asm/mach-types.h> 36#include <asm/mach-types.h>
@@ -185,6 +187,71 @@ static void __init ek_add_device_nand(void)
185 187
186 188
187/* 189/*
190 * ISI
191 */
192static struct isi_platform_data __initdata isi_data = {
193 .frate = ISI_CFG1_FRATE_CAPTURE_ALL,
194 /* to use codec and preview path simultaneously */
195 .full_mode = 1,
196 .data_width_flags = ISI_DATAWIDTH_8 | ISI_DATAWIDTH_10,
197 /* ISI_MCK is provided by programmable clock or external clock */
198 .mck_hz = 25000000,
199};
200
201
202/*
203 * soc-camera OV2640
204 */
205#if defined(CONFIG_SOC_CAMERA_OV2640) || \
206 defined(CONFIG_SOC_CAMERA_OV2640_MODULE)
207static unsigned long isi_camera_query_bus_param(struct soc_camera_link *link)
208{
209 /* ISI board for ek using default 8-bits connection */
210 return SOCAM_DATAWIDTH_8;
211}
212
213static int i2c_camera_power(struct device *dev, int on)
214{
215 /* enable or disable the camera */
216 pr_debug("%s: %s the camera\n", __func__, on ? "ENABLE" : "DISABLE");
217 at91_set_gpio_output(AT91_PIN_PD13, !on);
218
219 if (!on)
220 goto out;
221
222 /* If enabled, give a reset impulse */
223 at91_set_gpio_output(AT91_PIN_PD12, 0);
224 msleep(20);
225 at91_set_gpio_output(AT91_PIN_PD12, 1);
226 msleep(100);
227
228out:
229 return 0;
230}
231
232static struct i2c_board_info i2c_camera = {
233 I2C_BOARD_INFO("ov2640", 0x30),
234};
235
236static struct soc_camera_link iclink_ov2640 = {
237 .bus_id = 0,
238 .board_info = &i2c_camera,
239 .i2c_adapter_id = 0,
240 .power = i2c_camera_power,
241 .query_bus_param = isi_camera_query_bus_param,
242};
243
244static struct platform_device isi_ov2640 = {
245 .name = "soc-camera-pdrv",
246 .id = 0,
247 .dev = {
248 .platform_data = &iclink_ov2640,
249 },
250};
251#endif
252
253
254/*
188 * LCD Controller 255 * LCD Controller
189 */ 256 */
190#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE) 257#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
@@ -377,7 +444,12 @@ static struct gpio_led ek_pwm_led[] = {
377#endif 444#endif
378}; 445};
379 446
380 447static struct platform_device *devices[] __initdata = {
448#if defined(CONFIG_SOC_CAMERA_OV2640) || \
449 defined(CONFIG_SOC_CAMERA_OV2640_MODULE)
450 &isi_ov2640,
451#endif
452};
381 453
382static void __init ek_board_init(void) 454static void __init ek_board_init(void)
383{ 455{
@@ -399,6 +471,8 @@ static void __init ek_board_init(void)
399 ek_add_device_nand(); 471 ek_add_device_nand();
400 /* I2C */ 472 /* I2C */
401 at91_add_device_i2c(0, NULL, 0); 473 at91_add_device_i2c(0, NULL, 0);
474 /* ISI, using programmable clock as ISI_MCK */
475 at91_add_device_isi(&isi_data, true);
402 /* LCD Controller */ 476 /* LCD Controller */
403 at91_add_device_lcdc(&ek_lcdc_data); 477 at91_add_device_lcdc(&ek_lcdc_data);
404 /* Touch Screen */ 478 /* Touch Screen */
@@ -410,6 +484,8 @@ static void __init ek_board_init(void)
410 /* LEDs */ 484 /* LEDs */
411 at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds)); 485 at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
412 at91_pwm_leds(ek_pwm_led, ARRAY_SIZE(ek_pwm_led)); 486 at91_pwm_leds(ek_pwm_led, ARRAY_SIZE(ek_pwm_led));
487 /* Other platform devices */
488 platform_add_devices(devices, ARRAY_SIZE(devices));
413} 489}
414 490
415MACHINE_START(AT91SAM9M10G45EK, "Atmel AT91SAM9M10G45-EK") 491MACHINE_START(AT91SAM9M10G45EK, "Atmel AT91SAM9M10G45-EK")
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
index 61873f3aa92d..aa04e22a9da6 100644
--- a/arch/arm/mach-at91/clock.c
+++ b/arch/arm/mach-at91/clock.c
@@ -47,8 +47,7 @@
47/* 47/*
48 * Chips have some kind of clocks : group them by functionality 48 * Chips have some kind of clocks : group them by functionality
49 */ 49 */
50#define cpu_has_utmi() ( cpu_is_at91cap9() \ 50#define cpu_has_utmi() ( cpu_is_at91sam9rl() \
51 || cpu_is_at91sam9rl() \
52 || cpu_is_at91sam9g45()) 51 || cpu_is_at91sam9g45())
53 52
54#define cpu_has_800M_plla() ( cpu_is_at91sam9g20() \ 53#define cpu_has_800M_plla() ( cpu_is_at91sam9g20() \
@@ -602,8 +601,6 @@ static void __init at91_pllb_usbfs_clock_init(unsigned long main_clock)
602 cpu_is_at91sam9g10()) { 601 cpu_is_at91sam9g10()) {
603 uhpck.pmc_mask = AT91SAM926x_PMC_UHP; 602 uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
604 udpck.pmc_mask = AT91SAM926x_PMC_UDP; 603 udpck.pmc_mask = AT91SAM926x_PMC_UDP;
605 } else if (cpu_is_at91cap9()) {
606 uhpck.pmc_mask = AT91CAP9_PMC_UHP;
607 } 604 }
608 at91_sys_write(AT91_CKGR_PLLBR, 0); 605 at91_sys_write(AT91_CKGR_PLLBR, 0);
609 606
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index 594133451c0c..7e8280e798c1 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -45,7 +45,6 @@ extern void __init at91sam9261_set_console_clock(int id);
45extern void __init at91sam9263_set_console_clock(int id); 45extern void __init at91sam9263_set_console_clock(int id);
46extern void __init at91sam9rl_set_console_clock(int id); 46extern void __init at91sam9rl_set_console_clock(int id);
47extern void __init at91sam9g45_set_console_clock(int id); 47extern void __init at91sam9g45_set_console_clock(int id);
48extern void __init at91cap9_set_console_clock(int id);
49#ifdef CONFIG_AT91_PMC_UNIT 48#ifdef CONFIG_AT91_PMC_UNIT
50extern int __init at91_clock_init(unsigned long main_clock); 49extern int __init at91_clock_init(unsigned long main_clock);
51#else 50#else
diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h
index e46f93e34aab..dbdd6ae473d5 100644
--- a/arch/arm/mach-at91/include/mach/at91_pmc.h
+++ b/arch/arm/mach-at91/include/mach/at91_pmc.h
@@ -23,10 +23,8 @@
23#define AT91_PMC_PCK (1 << 0) /* Processor Clock */ 23#define AT91_PMC_PCK (1 << 0) /* Processor Clock */
24#define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */ 24#define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */
25#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */ 25#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
26#define AT91CAP9_PMC_DDR (1 << 2) /* DDR Clock [CAP9 revC & some SAM9 only] */
27#define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */ 26#define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */
28#define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */ 27#define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */
29#define AT91CAP9_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91CAP9 only] */
30#define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */ 28#define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */
31#define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */ 29#define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */
32#define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */ 30#define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */
@@ -40,7 +38,7 @@
40#define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */ 38#define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */
41#define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */ 39#define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */
42 40
43#define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [some SAM9, CAP9] */ 41#define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [some SAM9] */
44#define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */ 42#define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */
45#define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */ 43#define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */
46#define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */ 44#define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */
@@ -48,7 +46,7 @@
48 46
49#define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */ 47#define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */
50#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ 48#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */
51#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [SAM9x, CAP9] */ 49#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [SAM9x] */
52#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */ 50#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */
53 51
54#define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */ 52#define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */
@@ -87,7 +85,7 @@
87#define AT91RM9200_PMC_MDIV_2 (1 << 8) 85#define AT91RM9200_PMC_MDIV_2 (1 << 8)
88#define AT91RM9200_PMC_MDIV_3 (2 << 8) 86#define AT91RM9200_PMC_MDIV_3 (2 << 8)
89#define AT91RM9200_PMC_MDIV_4 (3 << 8) 87#define AT91RM9200_PMC_MDIV_4 (3 << 8)
90#define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9,CAP9 only] */ 88#define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9 only] */
91#define AT91SAM9_PMC_MDIV_2 (1 << 8) 89#define AT91SAM9_PMC_MDIV_2 (1 << 8)
92#define AT91SAM9_PMC_MDIV_4 (2 << 8) 90#define AT91SAM9_PMC_MDIV_4 (2 << 8)
93#define AT91SAM9_PMC_MDIV_6 (3 << 8) /* [some SAM9 only] */ 91#define AT91SAM9_PMC_MDIV_6 (3 << 8) /* [some SAM9 only] */
@@ -117,17 +115,15 @@
117#define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */ 115#define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */
118#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */ 116#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */
119#define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */ 117#define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */
120#define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock [some SAM9, AT91CAP9 only] */ 118#define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock [some SAM9] */
121#define AT91_PMC_OSCSEL (1 << 7) /* Slow Clock Oscillator [AT91CAP9 revC only] */
122#define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */ 119#define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */
123#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */ 120#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */
124#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */ 121#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */
125#define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */ 122#define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */
126#define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */ 123#define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */
127 124
128#define AT91_PMC_PROT (AT91_PMC + 0xe4) /* Protect Register [AT91CAP9 revC only] */ 125#define AT91_PMC_PROT (AT91_PMC + 0xe4) /* Write Protect Mode Register [some SAM9] */
129#define AT91_PMC_PROTKEY 0x504d4301 /* Activation Code */ 126#define AT91_PMC_PROTKEY 0x504d4301 /* Activation Code */
130 127
131#define AT91_PMC_VER (AT91_PMC + 0xfc) /* PMC Module Version [AT91CAP9 only] */
132 128
133#endif 129#endif
diff --git a/arch/arm/mach-at91/include/mach/at91cap9.h b/arch/arm/mach-at91/include/mach/at91cap9.h
deleted file mode 100644
index 61d952902f2b..000000000000
--- a/arch/arm/mach-at91/include/mach/at91cap9.h
+++ /dev/null
@@ -1,122 +0,0 @@
1/*
2 * arch/arm/mach-at91/include/mach/at91cap9.h
3 *
4 * Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
5 * Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
6 * Copyright (C) 2007 Atmel Corporation.
7 *
8 * Common definitions.
9 * Based on AT91CAP9 datasheet revision B (Preliminary).
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 */
16
17#ifndef AT91CAP9_H
18#define AT91CAP9_H
19
20/*
21 * Peripheral identifiers/interrupts.
22 */
23#define AT91CAP9_ID_PIOABCD 2 /* Parallel IO Controller A, B, C and D */
24#define AT91CAP9_ID_MPB0 3 /* MP Block Peripheral 0 */
25#define AT91CAP9_ID_MPB1 4 /* MP Block Peripheral 1 */
26#define AT91CAP9_ID_MPB2 5 /* MP Block Peripheral 2 */
27#define AT91CAP9_ID_MPB3 6 /* MP Block Peripheral 3 */
28#define AT91CAP9_ID_MPB4 7 /* MP Block Peripheral 4 */
29#define AT91CAP9_ID_US0 8 /* USART 0 */
30#define AT91CAP9_ID_US1 9 /* USART 1 */
31#define AT91CAP9_ID_US2 10 /* USART 2 */
32#define AT91CAP9_ID_MCI0 11 /* Multimedia Card Interface 0 */
33#define AT91CAP9_ID_MCI1 12 /* Multimedia Card Interface 1 */
34#define AT91CAP9_ID_CAN 13 /* CAN */
35#define AT91CAP9_ID_TWI 14 /* Two-Wire Interface */
36#define AT91CAP9_ID_SPI0 15 /* Serial Peripheral Interface 0 */
37#define AT91CAP9_ID_SPI1 16 /* Serial Peripheral Interface 0 */
38#define AT91CAP9_ID_SSC0 17 /* Serial Synchronous Controller 0 */
39#define AT91CAP9_ID_SSC1 18 /* Serial Synchronous Controller 1 */
40#define AT91CAP9_ID_AC97C 19 /* AC97 Controller */
41#define AT91CAP9_ID_TCB 20 /* Timer Counter 0, 1 and 2 */
42#define AT91CAP9_ID_PWMC 21 /* Pulse Width Modulation Controller */
43#define AT91CAP9_ID_EMAC 22 /* Ethernet */
44#define AT91CAP9_ID_AESTDES 23 /* Advanced Encryption Standard, Triple DES */
45#define AT91CAP9_ID_ADC 24 /* Analog-to-Digital Converter */
46#define AT91CAP9_ID_ISI 25 /* Image Sensor Interface */
47#define AT91CAP9_ID_LCDC 26 /* LCD Controller */
48#define AT91CAP9_ID_DMA 27 /* DMA Controller */
49#define AT91CAP9_ID_UDPHS 28 /* USB High Speed Device Port */
50#define AT91CAP9_ID_UHP 29 /* USB Host Port */
51#define AT91CAP9_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */
52#define AT91CAP9_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */
53
54/*
55 * User Peripheral physical base addresses.
56 */
57#define AT91CAP9_BASE_UDPHS 0xfff78000
58#define AT91CAP9_BASE_TCB0 0xfff7c000
59#define AT91CAP9_BASE_TC0 0xfff7c000
60#define AT91CAP9_BASE_TC1 0xfff7c040
61#define AT91CAP9_BASE_TC2 0xfff7c080
62#define AT91CAP9_BASE_MCI0 0xfff80000
63#define AT91CAP9_BASE_MCI1 0xfff84000
64#define AT91CAP9_BASE_TWI 0xfff88000
65#define AT91CAP9_BASE_US0 0xfff8c000
66#define AT91CAP9_BASE_US1 0xfff90000
67#define AT91CAP9_BASE_US2 0xfff94000
68#define AT91CAP9_BASE_SSC0 0xfff98000
69#define AT91CAP9_BASE_SSC1 0xfff9c000
70#define AT91CAP9_BASE_AC97C 0xfffa0000
71#define AT91CAP9_BASE_SPI0 0xfffa4000
72#define AT91CAP9_BASE_SPI1 0xfffa8000
73#define AT91CAP9_BASE_CAN 0xfffac000
74#define AT91CAP9_BASE_PWMC 0xfffb8000
75#define AT91CAP9_BASE_EMAC 0xfffbc000
76#define AT91CAP9_BASE_ADC 0xfffc0000
77#define AT91CAP9_BASE_ISI 0xfffc4000
78
79/*
80 * System Peripherals (offset from AT91_BASE_SYS)
81 */
82#define AT91_BCRAMC (0xffffe400 - AT91_BASE_SYS)
83#define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS)
84#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS)
85#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
86#define AT91_GPBR (cpu_is_at91cap9_revB() ? \
87 (0xfffffd50 - AT91_BASE_SYS) : \
88 (0xfffffd60 - AT91_BASE_SYS))
89
90#define AT91CAP9_BASE_ECC 0xffffe200
91#define AT91CAP9_BASE_DMA 0xffffec00
92#define AT91CAP9_BASE_SMC 0xffffe800
93#define AT91CAP9_BASE_DBGU AT91_BASE_DBGU1
94#define AT91CAP9_BASE_PIOA 0xfffff200
95#define AT91CAP9_BASE_PIOB 0xfffff400
96#define AT91CAP9_BASE_PIOC 0xfffff600
97#define AT91CAP9_BASE_PIOD 0xfffff800
98#define AT91CAP9_BASE_RSTC 0xfffffd00
99#define AT91CAP9_BASE_SHDWC 0xfffffd10
100#define AT91CAP9_BASE_RTT 0xfffffd20
101#define AT91CAP9_BASE_PIT 0xfffffd30
102#define AT91CAP9_BASE_WDT 0xfffffd40
103
104#define AT91_USART0 AT91CAP9_BASE_US0
105#define AT91_USART1 AT91CAP9_BASE_US1
106#define AT91_USART2 AT91CAP9_BASE_US2
107
108
109/*
110 * Internal Memory.
111 */
112#define AT91CAP9_SRAM_BASE 0x00100000 /* Internal SRAM base address */
113#define AT91CAP9_SRAM_SIZE (32 * SZ_1K) /* Internal SRAM size (32Kb) */
114
115#define AT91CAP9_ROM_BASE 0x00400000 /* Internal ROM base address */
116#define AT91CAP9_ROM_SIZE (32 * SZ_1K) /* Internal ROM size (32Kb) */
117
118#define AT91CAP9_LCDC_BASE 0x00500000 /* LCD Controller */
119#define AT91CAP9_UDPHS_FIFO 0x00600000 /* USB High Speed Device Port */
120#define AT91CAP9_UHP_BASE 0x00700000 /* USB Host controller */
121
122#endif
diff --git a/arch/arm/mach-at91/include/mach/at91cap9_matrix.h b/arch/arm/mach-at91/include/mach/at91cap9_matrix.h
deleted file mode 100644
index 4b9d4aff4b4f..000000000000
--- a/arch/arm/mach-at91/include/mach/at91cap9_matrix.h
+++ /dev/null
@@ -1,137 +0,0 @@
1/*
2 * arch/arm/mach-at91/include/mach/at91cap9_matrix.h
3 *
4 * Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
5 * Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
6 * Copyright (C) 2006 Atmel Corporation.
7 *
8 * Memory Controllers (MATRIX, EBI) - System peripherals registers.
9 * Based on AT91CAP9 datasheet revision B (Preliminary).
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 */
16
17#ifndef AT91CAP9_MATRIX_H
18#define AT91CAP9_MATRIX_H
19
20#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */
21#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */
22#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */
23#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */
24#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */
25#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */
26#define AT91_MATRIX_MCFG6 (AT91_MATRIX + 0x18) /* Master Configuration Register 6 */
27#define AT91_MATRIX_MCFG7 (AT91_MATRIX + 0x1C) /* Master Configuration Register 7 */
28#define AT91_MATRIX_MCFG8 (AT91_MATRIX + 0x20) /* Master Configuration Register 8 */
29#define AT91_MATRIX_MCFG9 (AT91_MATRIX + 0x24) /* Master Configuration Register 9 */
30#define AT91_MATRIX_MCFG10 (AT91_MATRIX + 0x28) /* Master Configuration Register 10 */
31#define AT91_MATRIX_MCFG11 (AT91_MATRIX + 0x2C) /* Master Configuration Register 11 */
32#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
33#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
34#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
35#define AT91_MATRIX_ULBT_FOUR (2 << 0)
36#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
37#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
38
39#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */
40#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */
41#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */
42#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */
43#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */
44#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */
45#define AT91_MATRIX_SCFG6 (AT91_MATRIX + 0x58) /* Slave Configuration Register 6 */
46#define AT91_MATRIX_SCFG7 (AT91_MATRIX + 0x5C) /* Slave Configuration Register 7 */
47#define AT91_MATRIX_SCFG8 (AT91_MATRIX + 0x60) /* Slave Configuration Register 8 */
48#define AT91_MATRIX_SCFG9 (AT91_MATRIX + 0x64) /* Slave Configuration Register 9 */
49#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
50#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
51#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
52#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
53#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
54#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */
55#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
56#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
57#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
58
59#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */
60#define AT91_MATRIX_PRBS0 (AT91_MATRIX + 0x84) /* Priority Register B for Slave 0 */
61#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */
62#define AT91_MATRIX_PRBS1 (AT91_MATRIX + 0x8C) /* Priority Register B for Slave 1 */
63#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */
64#define AT91_MATRIX_PRBS2 (AT91_MATRIX + 0x94) /* Priority Register B for Slave 2 */
65#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */
66#define AT91_MATRIX_PRBS3 (AT91_MATRIX + 0x9C) /* Priority Register B for Slave 3 */
67#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */
68#define AT91_MATRIX_PRBS4 (AT91_MATRIX + 0xA4) /* Priority Register B for Slave 4 */
69#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */
70#define AT91_MATRIX_PRBS5 (AT91_MATRIX + 0xAC) /* Priority Register B for Slave 5 */
71#define AT91_MATRIX_PRAS6 (AT91_MATRIX + 0xB0) /* Priority Register A for Slave 6 */
72#define AT91_MATRIX_PRBS6 (AT91_MATRIX + 0xB4) /* Priority Register B for Slave 6 */
73#define AT91_MATRIX_PRAS7 (AT91_MATRIX + 0xB8) /* Priority Register A for Slave 7 */
74#define AT91_MATRIX_PRBS7 (AT91_MATRIX + 0xBC) /* Priority Register B for Slave 7 */
75#define AT91_MATRIX_PRAS8 (AT91_MATRIX + 0xC0) /* Priority Register A for Slave 8 */
76#define AT91_MATRIX_PRBS8 (AT91_MATRIX + 0xC4) /* Priority Register B for Slave 8 */
77#define AT91_MATRIX_PRAS9 (AT91_MATRIX + 0xC8) /* Priority Register A for Slave 9 */
78#define AT91_MATRIX_PRBS9 (AT91_MATRIX + 0xCC) /* Priority Register B for Slave 9 */
79#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
80#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
81#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
82#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
83#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
84#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
85#define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */
86#define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */
87#define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */
88#define AT91_MATRIX_M9PR (3 << 4) /* Master 9 Priority (in Register B) */
89#define AT91_MATRIX_M10PR (3 << 8) /* Master 10 Priority (in Register B) */
90#define AT91_MATRIX_M11PR (3 << 12) /* Master 11 Priority (in Register B) */
91
92#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */
93#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
94#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
95#define AT91_MATRIX_RCB2 (1 << 2)
96#define AT91_MATRIX_RCB3 (1 << 3)
97#define AT91_MATRIX_RCB4 (1 << 4)
98#define AT91_MATRIX_RCB5 (1 << 5)
99#define AT91_MATRIX_RCB6 (1 << 6)
100#define AT91_MATRIX_RCB7 (1 << 7)
101#define AT91_MATRIX_RCB8 (1 << 8)
102#define AT91_MATRIX_RCB9 (1 << 9)
103#define AT91_MATRIX_RCB10 (1 << 10)
104#define AT91_MATRIX_RCB11 (1 << 11)
105
106#define AT91_MPBS0_SFR (AT91_MATRIX + 0x114) /* MPBlock Slave 0 Special Function Register */
107#define AT91_MPBS1_SFR (AT91_MATRIX + 0x11C) /* MPBlock Slave 1 Special Function Register */
108
109#define AT91_MATRIX_UDPHS (AT91_MATRIX + 0x118) /* USBHS Special Function Register [AT91CAP9 only] */
110#define AT91_MATRIX_SELECT_UDPHS (0 << 31) /* select High Speed UDP */
111#define AT91_MATRIX_SELECT_UDP (1 << 31) /* select standard UDP */
112#define AT91_MATRIX_UDPHS_BYPASS_LOCK (1 << 30) /* bypass lock bit */
113
114#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x120) /* EBI Chip Select Assignment Register */
115#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
116#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1)
117#define AT91_MATRIX_EBI_CS1A_BCRAMC (1 << 1)
118#define AT91_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */
119#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3)
120#define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3)
121#define AT91_MATRIX_EBI_CS4A (1 << 4) /* Chip Select 4 Assignment */
122#define AT91_MATRIX_EBI_CS4A_SMC (0 << 4)
123#define AT91_MATRIX_EBI_CS4A_SMC_CF1 (1 << 4)
124#define AT91_MATRIX_EBI_CS5A (1 << 5) /* Chip Select 5 Assignment */
125#define AT91_MATRIX_EBI_CS5A_SMC (0 << 5)
126#define AT91_MATRIX_EBI_CS5A_SMC_CF2 (1 << 5)
127#define AT91_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
128#define AT91_MATRIX_EBI_DQSPDC (1 << 9) /* Data Qualifier Strobe Pull-Down Configuration */
129#define AT91_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */
130#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16)
131#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16)
132
133#define AT91_MPBS2_SFR (AT91_MATRIX + 0x12C) /* MPBlock Slave 2 Special Function Register */
134#define AT91_MPBS3_SFR (AT91_MATRIX + 0x130) /* MPBlock Slave 3 Special Function Register */
135#define AT91_APB_SFR (AT91_MATRIX + 0x134) /* APB Bridge Special Function Register */
136
137#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
index e2f8da8ce5bc..5d4a9f846584 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
@@ -59,7 +59,6 @@
59#define AT91_DDRSDRC_TRP (0xf << 16) /* Row precharge delay */ 59#define AT91_DDRSDRC_TRP (0xf << 16) /* Row precharge delay */
60#define AT91_DDRSDRC_TRRD (0xf << 20) /* Active BankA to BankB */ 60#define AT91_DDRSDRC_TRRD (0xf << 20) /* Active BankA to BankB */
61#define AT91_DDRSDRC_TWTR (0x7 << 24) /* Internal Write to Read delay */ 61#define AT91_DDRSDRC_TWTR (0x7 << 24) /* Internal Write to Read delay */
62#define AT91CAP9_DDRSDRC_TWTR (1 << 24) /* Internal Write to Read delay */
63#define AT91_DDRSDRC_RED_WRRD (0x1 << 27) /* Reduce Write to Read Delay [SAM9 Only] */ 62#define AT91_DDRSDRC_RED_WRRD (0x1 << 27) /* Reduce Write to Read Delay [SAM9 Only] */
64#define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */ 63#define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */
65 64
@@ -76,7 +75,6 @@
76#define AT91_DDRSDRC_TRTP (0x7 << 12) /* Read to Precharge delay */ 75#define AT91_DDRSDRC_TRTP (0x7 << 12) /* Read to Precharge delay */
77 76
78#define AT91_DDRSDRC_LPR 0x1C /* Low Power Register */ 77#define AT91_DDRSDRC_LPR 0x1C /* Low Power Register */
79#define AT91CAP9_DDRSDRC_LPR 0x18 /* Low Power Register */
80#define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */ 78#define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */
81#define AT91_DDRSDRC_LPCB_DISABLE 0 79#define AT91_DDRSDRC_LPCB_DISABLE 0
82#define AT91_DDRSDRC_LPCB_SELF_REFRESH 1 80#define AT91_DDRSDRC_LPCB_SELF_REFRESH 1
@@ -94,11 +92,9 @@
94#define AT91_DDRSDRC_UPD_MR (3 << 20) /* Update load mode register and extended mode register */ 92#define AT91_DDRSDRC_UPD_MR (3 << 20) /* Update load mode register and extended mode register */
95 93
96#define AT91_DDRSDRC_MDR 0x20 /* Memory Device Register */ 94#define AT91_DDRSDRC_MDR 0x20 /* Memory Device Register */
97#define AT91CAP9_DDRSDRC_MDR 0x1C /* Memory Device Register */
98#define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */ 95#define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */
99#define AT91_DDRSDRC_MD_SDR 0 96#define AT91_DDRSDRC_MD_SDR 0
100#define AT91_DDRSDRC_MD_LOW_POWER_SDR 1 97#define AT91_DDRSDRC_MD_LOW_POWER_SDR 1
101#define AT91CAP9_DDRSDRC_MD_DDR 2
102#define AT91_DDRSDRC_MD_LOW_POWER_DDR 3 98#define AT91_DDRSDRC_MD_LOW_POWER_DDR 3
103#define AT91_DDRSDRC_MD_DDR2 6 /* [SAM9 Only] */ 99#define AT91_DDRSDRC_MD_DDR2 6 /* [SAM9 Only] */
104#define AT91_DDRSDRC_DBW (1 << 4) /* Data Bus Width */ 100#define AT91_DDRSDRC_DBW (1 << 4) /* Data Bus Width */
@@ -106,16 +102,10 @@
106#define AT91_DDRSDRC_DBW_16BITS (1 << 4) 102#define AT91_DDRSDRC_DBW_16BITS (1 << 4)
107 103
108#define AT91_DDRSDRC_DLL 0x24 /* DLL Information Register */ 104#define AT91_DDRSDRC_DLL 0x24 /* DLL Information Register */
109#define AT91CAP9_DDRSDRC_DLL 0x20 /* DLL Information Register */
110#define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */ 105#define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */
111#define AT91_DDRSDRC_MDDEC (1 << 1) /* Master Delay decrement */ 106#define AT91_DDRSDRC_MDDEC (1 << 1) /* Master Delay decrement */
112#define AT91_DDRSDRC_MDOVF (1 << 2) /* Master Delay Overflow */ 107#define AT91_DDRSDRC_MDOVF (1 << 2) /* Master Delay Overflow */
113#define AT91CAP9_DDRSDRC_SDCOVF (1 << 3) /* Slave Delay Correction Overflow */
114#define AT91CAP9_DDRSDRC_SDCUDF (1 << 4) /* Slave Delay Correction Underflow */
115#define AT91CAP9_DDRSDRC_SDERF (1 << 5) /* Slave Delay Correction error */
116#define AT91_DDRSDRC_MDVAL (0xff << 8) /* Master Delay value */ 108#define AT91_DDRSDRC_MDVAL (0xff << 8) /* Master Delay value */
117#define AT91CAP9_DDRSDRC_SDVAL (0xff << 16) /* Slave Delay value */
118#define AT91CAP9_DDRSDRC_SDCVAL (0xff << 24) /* Slave Delay Correction value */
119 109
120#define AT91_DDRSDRC_HS 0x2C /* High Speed Register [SAM9 Only] */ 110#define AT91_DDRSDRC_HS 0x2C /* High Speed Register [SAM9 Only] */
121#define AT91_DDRSDRC_DIS_ATCP_RD (1 << 2) /* Anticip read access is disabled */ 111#define AT91_DDRSDRC_DIS_ATCP_RD (1 << 2) /* Anticip read access is disabled */
diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h
index 3b33f07b1e11..dc8d6d4f17cf 100644
--- a/arch/arm/mach-at91/include/mach/board.h
+++ b/arch/arm/mach-at91/include/mach/board.h
@@ -107,6 +107,8 @@ struct atmel_nand_data {
107 u8 ale; /* address line number connected to ALE */ 107 u8 ale; /* address line number connected to ALE */
108 u8 cle; /* address line number connected to CLE */ 108 u8 cle; /* address line number connected to CLE */
109 u8 bus_width_16; /* buswidth is 16 bit */ 109 u8 bus_width_16; /* buswidth is 16 bit */
110 u8 correction_cap; /* PMECC correction capability */
111 u16 sector_size; /* Sector size for PMECC */
110 struct mtd_partition *parts; 112 struct mtd_partition *parts;
111 unsigned int num_parts; 113 unsigned int num_parts;
112}; 114};
@@ -179,7 +181,9 @@ extern void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data);
179extern void __init at91_add_device_ac97(struct ac97c_platform_data *data); 181extern void __init at91_add_device_ac97(struct ac97c_platform_data *data);
180 182
181 /* ISI */ 183 /* ISI */
182extern void __init at91_add_device_isi(void); 184struct isi_platform_data;
185extern void __init at91_add_device_isi(struct isi_platform_data *data,
186 bool use_pck_as_mck);
183 187
184 /* Touchscreen Controller */ 188 /* Touchscreen Controller */
185struct at91_tsadcc_data { 189struct at91_tsadcc_data {
diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h
index f6ce936dba2b..0118c3338552 100644
--- a/arch/arm/mach-at91/include/mach/cpu.h
+++ b/arch/arm/mach-at91/include/mach/cpu.h
@@ -25,7 +25,6 @@
25#define ARCH_ID_AT91SAM9G45MRL 0x819b05a2 /* aka 9G45-ES2 & non ES lots */ 25#define ARCH_ID_AT91SAM9G45MRL 0x819b05a2 /* aka 9G45-ES2 & non ES lots */
26#define ARCH_ID_AT91SAM9G45ES 0x819b05a1 /* 9G45-ES (Engineering Sample) */ 26#define ARCH_ID_AT91SAM9G45ES 0x819b05a1 /* 9G45-ES (Engineering Sample) */
27#define ARCH_ID_AT91SAM9X5 0x819a05a0 27#define ARCH_ID_AT91SAM9X5 0x819a05a0
28#define ARCH_ID_AT91CAP9 0x039A03A0
29 28
30#define ARCH_ID_AT91SAM9XE128 0x329973a0 29#define ARCH_ID_AT91SAM9XE128 0x329973a0
31#define ARCH_ID_AT91SAM9XE256 0x329a93a0 30#define ARCH_ID_AT91SAM9XE256 0x329a93a0
@@ -51,10 +50,6 @@
51#define ARCH_FAMILY_AT91SAM9 0x01900000 50#define ARCH_FAMILY_AT91SAM9 0x01900000
52#define ARCH_FAMILY_AT91SAM9XE 0x02900000 51#define ARCH_FAMILY_AT91SAM9XE 0x02900000
53 52
54/* PMC revision */
55#define ARCH_REVISION_CAP9_B 0x399
56#define ARCH_REVISION_CAP9_C 0x601
57
58/* RM9200 type */ 53/* RM9200 type */
59#define ARCH_REVISON_9200_BGA (0 << 0) 54#define ARCH_REVISON_9200_BGA (0 << 0)
60#define ARCH_REVISON_9200_PQFP (1 << 0) 55#define ARCH_REVISON_9200_PQFP (1 << 0)
@@ -63,9 +58,6 @@ enum at91_soc_type {
63 /* 920T */ 58 /* 920T */
64 AT91_SOC_RM9200, 59 AT91_SOC_RM9200,
65 60
66 /* CAP */
67 AT91_SOC_CAP9,
68
69 /* SAM92xx */ 61 /* SAM92xx */
70 AT91_SOC_SAM9260, AT91_SOC_SAM9261, AT91_SOC_SAM9263, 62 AT91_SOC_SAM9260, AT91_SOC_SAM9261, AT91_SOC_SAM9263,
71 63
@@ -86,9 +78,6 @@ enum at91_soc_subtype {
86 /* RM9200 */ 78 /* RM9200 */
87 AT91_SOC_RM9200_BGA, AT91_SOC_RM9200_PQFP, 79 AT91_SOC_RM9200_BGA, AT91_SOC_RM9200_PQFP,
88 80
89 /* CAP9 */
90 AT91_SOC_CAP9_REV_B, AT91_SOC_CAP9_REV_C,
91
92 /* SAM9260 */ 81 /* SAM9260 */
93 AT91_SOC_SAM9XE, 82 AT91_SOC_SAM9XE,
94 83
@@ -195,16 +184,6 @@ static inline int at91_soc_is_detected(void)
195#define cpu_is_at91sam9x25() (0) 184#define cpu_is_at91sam9x25() (0)
196#endif 185#endif
197 186
198#ifdef CONFIG_ARCH_AT91CAP9
199#define cpu_is_at91cap9() (at91_soc_initdata.type == AT91_SOC_CAP9)
200#define cpu_is_at91cap9_revB() (at91_soc_initdata.subtype == AT91_SOC_CAP9_REV_B)
201#define cpu_is_at91cap9_revC() (at91_soc_initdata.subtype == AT91_SOC_CAP9_REV_C)
202#else
203#define cpu_is_at91cap9() (0)
204#define cpu_is_at91cap9_revB() (0)
205#define cpu_is_at91cap9_revC() (0)
206#endif
207
208/* 187/*
209 * Since this is ARM, we will never run on any AVR32 CPU. But these 188 * Since this is ARM, we will never run on any AVR32 CPU. But these
210 * definitions may reduce clutter in common drivers. 189 * definitions may reduce clutter in common drivers.
diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h
index 2d0e4e998566..c213f28628c0 100644
--- a/arch/arm/mach-at91/include/mach/hardware.h
+++ b/arch/arm/mach-at91/include/mach/hardware.h
@@ -19,7 +19,7 @@
19/* DBGU base */ 19/* DBGU base */
20/* rm9200, 9260/9g20, 9261/9g10, 9rl */ 20/* rm9200, 9260/9g20, 9261/9g10, 9rl */
21#define AT91_BASE_DBGU0 0xfffff200 21#define AT91_BASE_DBGU0 0xfffff200
22/* 9263, 9g45, cap9 */ 22/* 9263, 9g45 */
23#define AT91_BASE_DBGU1 0xffffee00 23#define AT91_BASE_DBGU1 0xffffee00
24 24
25#if defined(CONFIG_ARCH_AT91RM9200) 25#if defined(CONFIG_ARCH_AT91RM9200)
@@ -34,8 +34,6 @@
34#include <mach/at91sam9rl.h> 34#include <mach/at91sam9rl.h>
35#elif defined(CONFIG_ARCH_AT91SAM9G45) 35#elif defined(CONFIG_ARCH_AT91SAM9G45)
36#include <mach/at91sam9g45.h> 36#include <mach/at91sam9g45.h>
37#elif defined(CONFIG_ARCH_AT91CAP9)
38#include <mach/at91cap9.h>
39#elif defined(CONFIG_ARCH_AT91X40) 37#elif defined(CONFIG_ARCH_AT91X40)
40#include <mach/at91x40.h> 38#include <mach/at91x40.h>
41#else 39#else
diff --git a/arch/arm/mach-at91/include/mach/system.h b/arch/arm/mach-at91/include/mach/system.h
deleted file mode 100644
index cbd64f3bcecd..000000000000
--- a/arch/arm/mach-at91/include/mach/system.h
+++ /dev/null
@@ -1,50 +0,0 @@
1/*
2 * arch/arm/mach-at91/include/mach/system.h
3 *
4 * Copyright (C) 2003 SAN People
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#ifndef __ASM_ARCH_SYSTEM_H
22#define __ASM_ARCH_SYSTEM_H
23
24#include <mach/hardware.h>
25#include <mach/at91_st.h>
26#include <mach/at91_dbgu.h>
27#include <mach/at91_pmc.h>
28
29static inline void arch_idle(void)
30{
31 /*
32 * Disable the processor clock. The processor will be automatically
33 * re-enabled by an interrupt or by a reset.
34 */
35#ifdef AT91_PS
36 at91_sys_write(AT91_PS_CR, AT91_PS_CR_CPU);
37#else
38 at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
39#endif
40#ifndef CONFIG_CPU_ARM920T
41 /*
42 * Set the processor (CP15) into 'Wait for Interrupt' mode.
43 * Post-RM9200 processors need this in conjunction with the above
44 * to save power when idle.
45 */
46 cpu_do_idle();
47#endif
48}
49
50#endif
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index 1606379ac284..87be5aa18753 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -150,11 +150,6 @@ static int at91_pm_verify_clocks(void)
150 pr_err("AT91: PM - Suspend-to-RAM with USB still active\n"); 150 pr_err("AT91: PM - Suspend-to-RAM with USB still active\n");
151 return 0; 151 return 0;
152 } 152 }
153 } else if (cpu_is_at91cap9()) {
154 if ((scsr & AT91CAP9_PMC_UHP) != 0) {
155 pr_err("AT91: PM - Suspend-to-RAM with USB still active\n");
156 return 0;
157 }
158 } 153 }
159 154
160#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS 155#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h
index 7eb40d24242f..218d816427c0 100644
--- a/arch/arm/mach-at91/pm.h
+++ b/arch/arm/mach-at91/pm.h
@@ -24,24 +24,6 @@ static inline u32 sdram_selfrefresh_enable(void)
24#define wait_for_interrupt_enable() asm volatile ("mcr p15, 0, %0, c7, c0, 4" \ 24#define wait_for_interrupt_enable() asm volatile ("mcr p15, 0, %0, c7, c0, 4" \
25 : : "r" (0)) 25 : : "r" (0))
26 26
27#elif defined(CONFIG_ARCH_AT91CAP9)
28#include <mach/at91sam9_ddrsdr.h>
29
30
31static inline u32 sdram_selfrefresh_enable(void)
32{
33 u32 saved_lpr, lpr;
34
35 saved_lpr = at91_ramc_read(0, AT91CAP9_DDRSDRC_LPR);
36
37 lpr = saved_lpr & ~AT91_DDRSDRC_LPCB;
38 at91_ramc_write(0, AT91CAP9_DDRSDRC_LPR, lpr | AT91_DDRSDRC_LPCB_SELF_REFRESH);
39 return saved_lpr;
40}
41
42#define sdram_selfrefresh_disable(saved_lpr) at91_ramc_write(0, AT91CAP9_DDRSDRC_LPR, saved_lpr)
43#define wait_for_interrupt_enable() cpu_do_idle()
44
45#elif defined(CONFIG_ARCH_AT91SAM9G45) 27#elif defined(CONFIG_ARCH_AT91SAM9G45)
46#include <mach/at91sam9_ddrsdr.h> 28#include <mach/at91sam9_ddrsdr.h>
47 29
diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S
index 92dfb8461392..f8539a8bcd6c 100644
--- a/arch/arm/mach-at91/pm_slowclock.S
+++ b/arch/arm/mach-at91/pm_slowclock.S
@@ -18,8 +18,7 @@
18 18
19#if defined(CONFIG_ARCH_AT91RM9200) 19#if defined(CONFIG_ARCH_AT91RM9200)
20#include <mach/at91rm9200_mc.h> 20#include <mach/at91rm9200_mc.h>
21#elif defined(CONFIG_ARCH_AT91CAP9) \ 21#elif defined(CONFIG_ARCH_AT91SAM9G45)
22 || defined(CONFIG_ARCH_AT91SAM9G45)
23#include <mach/at91sam9_ddrsdr.h> 22#include <mach/at91sam9_ddrsdr.h>
24#else 23#else
25#include <mach/at91sam9_sdramc.h> 24#include <mach/at91sam9_sdramc.h>
@@ -130,8 +129,7 @@ ENTRY(at91_slow_clock)
130 /* Put SDRAM in self-refresh mode */ 129 /* Put SDRAM in self-refresh mode */
131 mov r3, #1 130 mov r3, #1
132 str r3, [r2, #AT91_SDRAMC_SRR] 131 str r3, [r2, #AT91_SDRAMC_SRR]
133#elif defined(CONFIG_ARCH_AT91CAP9) \ 132#elif defined(CONFIG_ARCH_AT91SAM9G45)
134 || defined(CONFIG_ARCH_AT91SAM9G45)
135 133
136 /* prepare for DDRAM self-refresh mode */ 134 /* prepare for DDRAM self-refresh mode */
137 ldr r3, [r2, #AT91_DDRSDRC_LPR] 135 ldr r3, [r2, #AT91_DDRSDRC_LPR]
@@ -263,8 +261,7 @@ ENTRY(at91_slow_clock)
263 261
264#ifdef CONFIG_ARCH_AT91RM9200 262#ifdef CONFIG_ARCH_AT91RM9200
265 /* Do nothing - self-refresh is automatically disabled. */ 263 /* Do nothing - self-refresh is automatically disabled. */
266#elif defined(CONFIG_ARCH_AT91CAP9) \ 264#elif defined(CONFIG_ARCH_AT91SAM9G45)
267 || defined(CONFIG_ARCH_AT91SAM9G45)
268 /* Restore LPR on AT91 with DDRAM */ 265 /* Restore LPR on AT91 with DDRAM */
269 ldr r3, .saved_sam9_lpr 266 ldr r3, .saved_sam9_lpr
270 str r3, [r2, #AT91_DDRSDRC_LPR] 267 str r3, [r2, #AT91_DDRSDRC_LPR]
@@ -305,8 +302,7 @@ ENTRY(at91_slow_clock)
305#ifdef CONFIG_ARCH_AT91RM9200 302#ifdef CONFIG_ARCH_AT91RM9200
306.at91_va_base_sdramc: 303.at91_va_base_sdramc:
307 .word AT91_VA_BASE_SYS 304 .word AT91_VA_BASE_SYS
308#elif defined(CONFIG_ARCH_AT91CAP9) \ 305#elif defined(CONFIG_ARCH_AT91SAM9G45)
309 || defined(CONFIG_ARCH_AT91SAM9G45)
310.at91_va_base_sdramc: 306.at91_va_base_sdramc:
311 .word AT91_VA_BASE_SYS + AT91_DDRSDRC0 307 .word AT91_VA_BASE_SYS + AT91_DDRSDRC0
312#else 308#else
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index 69d3fc4c46f3..620c67e8f814 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -86,20 +86,6 @@ static void __init soc_detect(u32 dbgu_base)
86 socid = cidr & ~AT91_CIDR_VERSION; 86 socid = cidr & ~AT91_CIDR_VERSION;
87 87
88 switch (socid) { 88 switch (socid) {
89 case ARCH_ID_AT91CAP9: {
90#ifdef CONFIG_AT91_PMC_UNIT
91 u32 pmc_ver = at91_sys_read(AT91_PMC_VER);
92
93 if (pmc_ver == ARCH_REVISION_CAP9_B)
94 at91_soc_initdata.subtype = AT91_SOC_CAP9_REV_B;
95 else if (pmc_ver == ARCH_REVISION_CAP9_C)
96 at91_soc_initdata.subtype = AT91_SOC_CAP9_REV_C;
97#endif
98 at91_soc_initdata.type = AT91_SOC_CAP9;
99 at91_boot_soc = at91cap9_soc;
100 break;
101 }
102
103 case ARCH_ID_AT91RM9200: 89 case ARCH_ID_AT91RM9200:
104 at91_soc_initdata.type = AT91_SOC_RM9200; 90 at91_soc_initdata.type = AT91_SOC_RM9200;
105 at91_boot_soc = at91rm9200_soc; 91 at91_boot_soc = at91rm9200_soc;
@@ -200,7 +186,6 @@ static void __init soc_detect(u32 dbgu_base)
200 186
201static const char *soc_name[] = { 187static const char *soc_name[] = {
202 [AT91_SOC_RM9200] = "at91rm9200", 188 [AT91_SOC_RM9200] = "at91rm9200",
203 [AT91_SOC_CAP9] = "at91cap9",
204 [AT91_SOC_SAM9260] = "at91sam9260", 189 [AT91_SOC_SAM9260] = "at91sam9260",
205 [AT91_SOC_SAM9261] = "at91sam9261", 190 [AT91_SOC_SAM9261] = "at91sam9261",
206 [AT91_SOC_SAM9263] = "at91sam9263", 191 [AT91_SOC_SAM9263] = "at91sam9263",
@@ -221,8 +206,6 @@ EXPORT_SYMBOL(at91_get_soc_type);
221static const char *soc_subtype_name[] = { 206static const char *soc_subtype_name[] = {
222 [AT91_SOC_RM9200_BGA] = "at91rm9200 BGA", 207 [AT91_SOC_RM9200_BGA] = "at91rm9200 BGA",
223 [AT91_SOC_RM9200_PQFP] = "at91rm9200 PQFP", 208 [AT91_SOC_RM9200_PQFP] = "at91rm9200 PQFP",
224 [AT91_SOC_CAP9_REV_B] = "at91cap9 revB",
225 [AT91_SOC_CAP9_REV_C] = "at91cap9 revC",
226 [AT91_SOC_SAM9XE] = "at91sam9xe", 209 [AT91_SOC_SAM9XE] = "at91sam9xe",
227 [AT91_SOC_SAM9G45ES] = "at91sam9g45es", 210 [AT91_SOC_SAM9G45ES] = "at91sam9g45es",
228 [AT91_SOC_SAM9M10] = "at91sam9m10", 211 [AT91_SOC_SAM9M10] = "at91sam9m10",
diff --git a/arch/arm/mach-at91/soc.h b/arch/arm/mach-at91/soc.h
index 4588ae6f7acd..5db4aa45404a 100644
--- a/arch/arm/mach-at91/soc.h
+++ b/arch/arm/mach-at91/soc.h
@@ -13,7 +13,6 @@ struct at91_init_soc {
13}; 13};
14 14
15extern struct at91_init_soc at91_boot_soc; 15extern struct at91_init_soc at91_boot_soc;
16extern struct at91_init_soc at91cap9_soc;
17extern struct at91_init_soc at91rm9200_soc; 16extern struct at91_init_soc at91rm9200_soc;
18extern struct at91_init_soc at91sam9260_soc; 17extern struct at91_init_soc at91sam9260_soc;
19extern struct at91_init_soc at91sam9261_soc; 18extern struct at91_init_soc at91sam9261_soc;
@@ -27,10 +26,6 @@ static inline int at91_soc_is_enabled(void)
27 return at91_boot_soc.init != NULL; 26 return at91_boot_soc.init != NULL;
28} 27}
29 28
30#if !defined(CONFIG_ARCH_AT91CAP9)
31#define at91cap9_soc at91_boot_soc
32#endif
33
34#if !defined(CONFIG_ARCH_AT91RM9200) 29#if !defined(CONFIG_ARCH_AT91RM9200)
35#define at91rm9200_soc at91_boot_soc 30#define at91rm9200_soc at91_boot_soc
36#endif 31#endif
diff --git a/arch/arm/mach-bcmring/core.c b/arch/arm/mach-bcmring/core.c
index 6b67b7e8426c..22e4e0a28ad1 100644
--- a/arch/arm/mach-bcmring/core.c
+++ b/arch/arm/mach-bcmring/core.c
@@ -52,27 +52,8 @@
52#include <mach/csp/chipcHw_inline.h> 52#include <mach/csp/chipcHw_inline.h>
53#include <mach/csp/tmrHw_reg.h> 53#include <mach/csp/tmrHw_reg.h>
54 54
55#define AMBA_DEVICE(name, initname, base, plat, size) \ 55static AMBA_APB_DEVICE(uartA, "uarta", MM_ADDR_IO_UARTA, { IRQ_UARTA }, NULL);
56static struct amba_device name##_device = { \ 56static AMBA_APB_DEVICE(uartB, "uartb", MM_ADDR_IO_UARTB, { IRQ_UARTB }, NULL);
57 .dev = { \
58 .coherent_dma_mask = ~0, \
59 .init_name = initname, \
60 .platform_data = plat \
61 }, \
62 .res = { \
63 .start = MM_ADDR_IO_##base, \
64 .end = MM_ADDR_IO_##base + (size) - 1, \
65 .flags = IORESOURCE_MEM \
66 }, \
67 .dma_mask = ~0, \
68 .irq = { \
69 IRQ_##base \
70 } \
71}
72
73
74AMBA_DEVICE(uartA, "uarta", UARTA, NULL, SZ_4K);
75AMBA_DEVICE(uartB, "uartb", UARTB, NULL, SZ_4K);
76 57
77static struct clk pll1_clk = { 58static struct clk pll1_clk = {
78 .name = "PLL1", 59 .name = "PLL1",
diff --git a/arch/arm/mach-bcmring/include/mach/system.h b/arch/arm/mach-bcmring/include/mach/system.h
deleted file mode 100644
index cb78250db649..000000000000
--- a/arch/arm/mach-bcmring/include/mach/system.h
+++ /dev/null
@@ -1,28 +0,0 @@
1/*
2 *
3 * Copyright (C) 1999 ARM Limited
4 * Copyright (C) 2000 Deep Blue Solutions Ltd
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#ifndef __ASM_ARCH_SYSTEM_H
21#define __ASM_ARCH_SYSTEM_H
22
23static inline void arch_idle(void)
24{
25 cpu_do_idle();
26}
27
28#endif
diff --git a/arch/arm/mach-clps711x/common.c b/arch/arm/mach-clps711x/common.c
index ab1711b9b4d6..8736c1acc166 100644
--- a/arch/arm/mach-clps711x/common.c
+++ b/arch/arm/mach-clps711x/common.c
@@ -225,3 +225,19 @@ void clps711x_restart(char mode, const char *cmd)
225{ 225{
226 soft_restart(0); 226 soft_restart(0);
227} 227}
228
229static void clps711x_idle(void)
230{
231 clps_writel(1, HALT);
232 __asm__ __volatile__(
233 "mov r0, r0\n\
234 mov r0, r0");
235}
236
237static int __init clps711x_idle_init(void)
238{
239 arm_pm_idle = clps711x_idle;
240 return 0;
241}
242
243arch_initcall(clps711x_idle_init);
diff --git a/arch/arm/mach-clps711x/include/mach/system.h b/arch/arm/mach-clps711x/include/mach/system.h
deleted file mode 100644
index 23d6ef8c84da..000000000000
--- a/arch/arm/mach-clps711x/include/mach/system.h
+++ /dev/null
@@ -1,35 +0,0 @@
1/*
2 * arch/arm/mach-clps711x/include/mach/system.h
3 *
4 * Copyright (C) 2000 Deep Blue Solutions Ltd
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#ifndef __ASM_ARCH_SYSTEM_H
21#define __ASM_ARCH_SYSTEM_H
22
23#include <linux/io.h>
24#include <mach/hardware.h>
25#include <asm/hardware/clps7111.h>
26
27static inline void arch_idle(void)
28{
29 clps_writel(1, HALT);
30 __asm__ __volatile__(
31 "mov r0, r0\n\
32 mov r0, r0");
33}
34
35#endif
diff --git a/arch/arm/mach-cns3xxx/include/mach/system.h b/arch/arm/mach-cns3xxx/include/mach/system.h
deleted file mode 100644
index 9e56b7dc133a..000000000000
--- a/arch/arm/mach-cns3xxx/include/mach/system.h
+++ /dev/null
@@ -1,25 +0,0 @@
1/*
2 * Copyright 2000 Deep Blue Solutions Ltd
3 * Copyright 2003 ARM Limited
4 * Copyright 2008 Cavium Networks
5 *
6 * This file is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License, Version 2, as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __MACH_SYSTEM_H
12#define __MACH_SYSTEM_H
13
14#include <asm/proc-fns.h>
15
16static inline void arch_idle(void)
17{
18 /*
19 * This should do all the clock switching
20 * and wait for interrupt tricks
21 */
22 cpu_do_idle();
23}
24
25#endif
diff --git a/arch/arm/mach-davinci/include/mach/system.h b/arch/arm/mach-davinci/include/mach/system.h
deleted file mode 100644
index fcb7a015aba5..000000000000
--- a/arch/arm/mach-davinci/include/mach/system.h
+++ /dev/null
@@ -1,21 +0,0 @@
1/*
2 * DaVinci system defines
3 *
4 * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
5 *
6 * 2007 (c) MontaVista Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11#ifndef __ASM_ARCH_SYSTEM_H
12#define __ASM_ARCH_SYSTEM_H
13
14#include <mach/common.h>
15
16static inline void arch_idle(void)
17{
18 cpu_do_idle();
19}
20
21#endif /* __ASM_ARCH_SYSTEM_H */
diff --git a/arch/arm/mach-dove/include/mach/system.h b/arch/arm/mach-dove/include/mach/system.h
deleted file mode 100644
index 3027954f6162..000000000000
--- a/arch/arm/mach-dove/include/mach/system.h
+++ /dev/null
@@ -1,17 +0,0 @@
1/*
2 * arch/arm/mach-dove/include/mach/system.h
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9#ifndef __ASM_ARCH_SYSTEM_H
10#define __ASM_ARCH_SYSTEM_H
11
12static inline void arch_idle(void)
13{
14 cpu_do_idle();
15}
16
17#endif
diff --git a/arch/arm/mach-ebsa110/core.c b/arch/arm/mach-ebsa110/core.c
index 294aad07f7a0..804c9122b7b3 100644
--- a/arch/arm/mach-ebsa110/core.c
+++ b/arch/arm/mach-ebsa110/core.c
@@ -271,8 +271,33 @@ static struct platform_device *ebsa110_devices[] = {
271 &am79c961_device, 271 &am79c961_device,
272}; 272};
273 273
274/*
275 * EBSA110 idling methodology:
276 *
277 * We can not execute the "wait for interrupt" instruction since that
278 * will stop our MCLK signal (which provides the clock for the glue
279 * logic, and therefore the timer interrupt).
280 *
281 * Instead, we spin, polling the IRQ_STAT register for the occurrence
282 * of any interrupt with core clock down to the memory clock.
283 */
284static void ebsa110_idle(void)
285{
286 const char *irq_stat = (char *)0xff000000;
287
288 /* disable clock switching */
289 asm volatile ("mcr p15, 0, ip, c15, c2, 2" : : : "cc");
290
291 /* wait for an interrupt to occur */
292 while (!*irq_stat);
293
294 /* enable clock switching */
295 asm volatile ("mcr p15, 0, ip, c15, c1, 2" : : : "cc");
296}
297
274static int __init ebsa110_init(void) 298static int __init ebsa110_init(void)
275{ 299{
300 arm_pm_idle = ebsa110_idle;
276 return platform_add_devices(ebsa110_devices, ARRAY_SIZE(ebsa110_devices)); 301 return platform_add_devices(ebsa110_devices, ARRAY_SIZE(ebsa110_devices));
277} 302}
278 303
diff --git a/arch/arm/mach-ebsa110/include/mach/system.h b/arch/arm/mach-ebsa110/include/mach/system.h
deleted file mode 100644
index 2e4af65edb6f..000000000000
--- a/arch/arm/mach-ebsa110/include/mach/system.h
+++ /dev/null
@@ -1,37 +0,0 @@
1/*
2 * arch/arm/mach-ebsa110/include/mach/system.h
3 *
4 * Copyright (C) 1996-2000 Russell King.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#ifndef __ASM_ARCH_SYSTEM_H
11#define __ASM_ARCH_SYSTEM_H
12
13/*
14 * EBSA110 idling methodology:
15 *
16 * We can not execute the "wait for interrupt" instruction since that
17 * will stop our MCLK signal (which provides the clock for the glue
18 * logic, and therefore the timer interrupt).
19 *
20 * Instead, we spin, polling the IRQ_STAT register for the occurrence
21 * of any interrupt with core clock down to the memory clock.
22 */
23static inline void arch_idle(void)
24{
25 const char *irq_stat = (char *)0xff000000;
26
27 /* disable clock switching */
28 asm volatile ("mcr p15, 0, ip, c15, c2, 2" : : : "cc");
29
30 /* wait for an interrupt to occur */
31 while (!*irq_stat);
32
33 /* enable clock switching */
34 asm volatile ("mcr p15, 0, ip, c15, c1, 2" : : : "cc");
35}
36
37#endif
diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
index 24203f9a6796..903edb02fe4f 100644
--- a/arch/arm/mach-ep93xx/core.c
+++ b/arch/arm/mach-ep93xx/core.c
@@ -279,48 +279,14 @@ static struct amba_pl010_data ep93xx_uart_data = {
279 .set_mctrl = ep93xx_uart_set_mctrl, 279 .set_mctrl = ep93xx_uart_set_mctrl,
280}; 280};
281 281
282static struct amba_device uart1_device = { 282static AMBA_APB_DEVICE(uart1, "apb:uart1", 0x00041010, EP93XX_UART1_PHYS_BASE,
283 .dev = { 283 { IRQ_EP93XX_UART1 }, &ep93xx_uart_data);
284 .init_name = "apb:uart1",
285 .platform_data = &ep93xx_uart_data,
286 },
287 .res = {
288 .start = EP93XX_UART1_PHYS_BASE,
289 .end = EP93XX_UART1_PHYS_BASE + 0x0fff,
290 .flags = IORESOURCE_MEM,
291 },
292 .irq = { IRQ_EP93XX_UART1, NO_IRQ },
293 .periphid = 0x00041010,
294};
295
296static struct amba_device uart2_device = {
297 .dev = {
298 .init_name = "apb:uart2",
299 .platform_data = &ep93xx_uart_data,
300 },
301 .res = {
302 .start = EP93XX_UART2_PHYS_BASE,
303 .end = EP93XX_UART2_PHYS_BASE + 0x0fff,
304 .flags = IORESOURCE_MEM,
305 },
306 .irq = { IRQ_EP93XX_UART2, NO_IRQ },
307 .periphid = 0x00041010,
308};
309 284
310static struct amba_device uart3_device = { 285static AMBA_APB_DEVICE(uart2, "apb:uart2", 0x00041010, EP93XX_UART2_PHYS_BASE,
311 .dev = { 286 { IRQ_EP93XX_UART2 }, &ep93xx_uart_data);
312 .init_name = "apb:uart3",
313 .platform_data = &ep93xx_uart_data,
314 },
315 .res = {
316 .start = EP93XX_UART3_PHYS_BASE,
317 .end = EP93XX_UART3_PHYS_BASE + 0x0fff,
318 .flags = IORESOURCE_MEM,
319 },
320 .irq = { IRQ_EP93XX_UART3, NO_IRQ },
321 .periphid = 0x00041010,
322};
323 287
288static AMBA_APB_DEVICE(uart3, "apb:uart3", 0x00041010, EP93XX_UART3_PHYS_BASE,
289 { IRQ_EP93XX_UART3 }, &ep93xx_uart_data);
324 290
325static struct resource ep93xx_rtc_resource[] = { 291static struct resource ep93xx_rtc_resource[] = {
326 { 292 {
diff --git a/arch/arm/mach-ep93xx/include/mach/system.h b/arch/arm/mach-ep93xx/include/mach/system.h
deleted file mode 100644
index b5bec7cb9b52..000000000000
--- a/arch/arm/mach-ep93xx/include/mach/system.h
+++ /dev/null
@@ -1,7 +0,0 @@
1/*
2 * arch/arm/mach-ep93xx/include/mach/system.h
3 */
4static inline void arch_idle(void)
5{
6 cpu_do_idle();
7}
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index c59e18871006..031c1e5b3dfe 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -201,14 +201,6 @@ static struct map_desc exynos4_iodesc1[] __initdata = {
201 }, 201 },
202}; 202};
203 203
204static void exynos_idle(void)
205{
206 if (!need_resched())
207 cpu_do_idle();
208
209 local_irq_enable();
210}
211
212void exynos4_restart(char mode, const char *cmd) 204void exynos4_restart(char mode, const char *cmd)
213{ 205{
214 __raw_writel(0x1, S5P_SWRESET); 206 __raw_writel(0x1, S5P_SWRESET);
@@ -467,10 +459,6 @@ early_initcall(exynos4_l2x0_cache_init);
467int __init exynos_init(void) 459int __init exynos_init(void)
468{ 460{
469 printk(KERN_INFO "EXYNOS: Initializing architecture\n"); 461 printk(KERN_INFO "EXYNOS: Initializing architecture\n");
470
471 /* set idle function */
472 pm_idle = exynos_idle;
473
474 return device_register(&exynos4_dev); 462 return device_register(&exynos4_dev);
475} 463}
476 464
diff --git a/arch/arm/mach-exynos/dma.c b/arch/arm/mach-exynos/dma.c
index b10fcd270f07..91370def4a70 100644
--- a/arch/arm/mach-exynos/dma.c
+++ b/arch/arm/mach-exynos/dma.c
@@ -74,21 +74,8 @@ struct dma_pl330_platdata exynos4_pdma0_pdata = {
74 .peri_id = pdma0_peri, 74 .peri_id = pdma0_peri,
75}; 75};
76 76
77struct amba_device exynos4_device_pdma0 = { 77AMBA_AHB_DEVICE(exynos4_pdma0, "dma-pl330.0", 0x00041330, EXYNOS4_PA_PDMA0,
78 .dev = { 78 {IRQ_PDMA0}, &exynos4_pdma0_pdata);
79 .init_name = "dma-pl330.0",
80 .dma_mask = &dma_dmamask,
81 .coherent_dma_mask = DMA_BIT_MASK(32),
82 .platform_data = &exynos4_pdma0_pdata,
83 },
84 .res = {
85 .start = EXYNOS4_PA_PDMA0,
86 .end = EXYNOS4_PA_PDMA0 + SZ_4K,
87 .flags = IORESOURCE_MEM,
88 },
89 .irq = {IRQ_PDMA0, NO_IRQ},
90 .periphid = 0x00041330,
91};
92 79
93u8 pdma1_peri[] = { 80u8 pdma1_peri[] = {
94 DMACH_PCM0_RX, 81 DMACH_PCM0_RX,
@@ -123,21 +110,8 @@ struct dma_pl330_platdata exynos4_pdma1_pdata = {
123 .peri_id = pdma1_peri, 110 .peri_id = pdma1_peri,
124}; 111};
125 112
126struct amba_device exynos4_device_pdma1 = { 113AMBA_AHB_DEVICE(exynos4_pdma1, "dma-pl330.1", 0x00041330, EXYNOS4_PA_PDMA1,
127 .dev = { 114 {IRQ_PDMA1}, &exynos4_pdma1_pdata);
128 .init_name = "dma-pl330.1",
129 .dma_mask = &dma_dmamask,
130 .coherent_dma_mask = DMA_BIT_MASK(32),
131 .platform_data = &exynos4_pdma1_pdata,
132 },
133 .res = {
134 .start = EXYNOS4_PA_PDMA1,
135 .end = EXYNOS4_PA_PDMA1 + SZ_4K,
136 .flags = IORESOURCE_MEM,
137 },
138 .irq = {IRQ_PDMA1, NO_IRQ},
139 .periphid = 0x00041330,
140};
141 115
142static int __init exynos4_dma_init(void) 116static int __init exynos4_dma_init(void)
143{ 117{
@@ -146,11 +120,11 @@ static int __init exynos4_dma_init(void)
146 120
147 dma_cap_set(DMA_SLAVE, exynos4_pdma0_pdata.cap_mask); 121 dma_cap_set(DMA_SLAVE, exynos4_pdma0_pdata.cap_mask);
148 dma_cap_set(DMA_CYCLIC, exynos4_pdma0_pdata.cap_mask); 122 dma_cap_set(DMA_CYCLIC, exynos4_pdma0_pdata.cap_mask);
149 amba_device_register(&exynos4_device_pdma0, &iomem_resource); 123 amba_device_register(&exynos4_pdma0_device, &iomem_resource);
150 124
151 dma_cap_set(DMA_SLAVE, exynos4_pdma1_pdata.cap_mask); 125 dma_cap_set(DMA_SLAVE, exynos4_pdma1_pdata.cap_mask);
152 dma_cap_set(DMA_CYCLIC, exynos4_pdma1_pdata.cap_mask); 126 dma_cap_set(DMA_CYCLIC, exynos4_pdma1_pdata.cap_mask);
153 amba_device_register(&exynos4_device_pdma1, &iomem_resource); 127 amba_device_register(&exynos4_pdma1_device, &iomem_resource);
154 128
155 return 0; 129 return 0;
156} 130}
diff --git a/arch/arm/mach-exynos/include/mach/system.h b/arch/arm/mach-exynos/include/mach/system.h
deleted file mode 100644
index 0063a6de3dc8..000000000000
--- a/arch/arm/mach-exynos/include/mach/system.h
+++ /dev/null
@@ -1,20 +0,0 @@
1/* linux/arch/arm/mach-exynos4/include/mach/system.h
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS4 - system support header
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_SYSTEM_H
14#define __ASM_ARCH_SYSTEM_H __FILE__
15
16static void arch_idle(void)
17{
18 /* nothing here yet */
19}
20#endif /* __ASM_ARCH_SYSTEM_H */
diff --git a/arch/arm/mach-footbridge/include/mach/system.h b/arch/arm/mach-footbridge/include/mach/system.h
deleted file mode 100644
index a174a5841bc2..000000000000
--- a/arch/arm/mach-footbridge/include/mach/system.h
+++ /dev/null
@@ -1,13 +0,0 @@
1/*
2 * arch/arm/mach-footbridge/include/mach/system.h
3 *
4 * Copyright (C) 1996-1999 Russell King.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10static inline void arch_idle(void)
11{
12 cpu_do_idle();
13}
diff --git a/arch/arm/mach-gemini/Makefile b/arch/arm/mach-gemini/Makefile
index c5b24b95a76e..7355c0bbcb5e 100644
--- a/arch/arm/mach-gemini/Makefile
+++ b/arch/arm/mach-gemini/Makefile
@@ -4,7 +4,7 @@
4 4
5# Object file lists. 5# Object file lists.
6 6
7obj-y := irq.o mm.o time.o devices.o gpio.o 7obj-y := irq.o mm.o time.o devices.o gpio.o idle.o
8 8
9# Board-specific support 9# Board-specific support
10obj-$(CONFIG_MACH_NAS4220B) += board-nas4220b.o 10obj-$(CONFIG_MACH_NAS4220B) += board-nas4220b.o
diff --git a/arch/arm/mach-gemini/idle.c b/arch/arm/mach-gemini/idle.c
new file mode 100644
index 000000000000..92bbd6bb600a
--- /dev/null
+++ b/arch/arm/mach-gemini/idle.c
@@ -0,0 +1,29 @@
1/*
2 * arch/arm/mach-gemini/idle.c
3 */
4
5#include <linux/init.h>
6#include <asm/system.h>
7#include <asm/proc-fns.h>
8
9static void gemini_idle(void)
10{
11 /*
12 * Because of broken hardware we have to enable interrupts or the CPU
13 * will never wakeup... Acctualy it is not very good to enable
14 * interrupts first since scheduler can miss a tick, but there is
15 * no other way around this. Platforms that needs it for power saving
16 * should call enable_hlt() in init code, since by default it is
17 * disabled.
18 */
19 local_irq_enable();
20 cpu_do_idle();
21}
22
23static int __init gemini_idle_init(void)
24{
25 arm_pm_idle = gemini_idle;
26 return 0;
27}
28
29arch_initcall(gemini_idle_init);
diff --git a/arch/arm/mach-gemini/include/mach/system.h b/arch/arm/mach-gemini/include/mach/system.h
index 4d9c1f872472..a33b5a1f8ab4 100644
--- a/arch/arm/mach-gemini/include/mach/system.h
+++ b/arch/arm/mach-gemini/include/mach/system.h
@@ -14,20 +14,6 @@
14#include <mach/hardware.h> 14#include <mach/hardware.h>
15#include <mach/global_reg.h> 15#include <mach/global_reg.h>
16 16
17static inline void arch_idle(void)
18{
19 /*
20 * Because of broken hardware we have to enable interrupts or the CPU
21 * will never wakeup... Acctualy it is not very good to enable
22 * interrupts here since scheduler can miss a tick, but there is
23 * no other way around this. Platforms that needs it for power saving
24 * should call enable_hlt() in init code, since by default it is
25 * disabled.
26 */
27 local_irq_enable();
28 cpu_do_idle();
29}
30
31static inline void arch_reset(char mode, const char *cmd) 17static inline void arch_reset(char mode, const char *cmd)
32{ 18{
33 __raw_writel(RESET_GLOBAL | RESET_CPU1, 19 __raw_writel(RESET_GLOBAL | RESET_CPU1,
diff --git a/arch/arm/mach-gemini/irq.c b/arch/arm/mach-gemini/irq.c
index 9485a8fdf851..ca70e5fcc7ac 100644
--- a/arch/arm/mach-gemini/irq.c
+++ b/arch/arm/mach-gemini/irq.c
@@ -73,8 +73,8 @@ void __init gemini_init_irq(void)
73 unsigned int i, mode = 0, level = 0; 73 unsigned int i, mode = 0, level = 0;
74 74
75 /* 75 /*
76 * Disable arch_idle() by default since it is buggy 76 * Disable the idle handler by default since it is buggy
77 * For more info see arch/arm/mach-gemini/include/mach/system.h 77 * For more info see arch/arm/mach-gemini/idle.c
78 */ 78 */
79 disable_hlt(); 79 disable_hlt();
80 80
diff --git a/arch/arm/mach-h720x/common.c b/arch/arm/mach-h720x/common.c
index f8a2f6bb5483..e756d1ac00c2 100644
--- a/arch/arm/mach-h720x/common.c
+++ b/arch/arm/mach-h720x/common.c
@@ -247,3 +247,21 @@ void h720x_restart(char mode, const char *cmd)
247{ 247{
248 CPU_REG (PMU_BASE, PMU_STAT) |= PMU_WARMRESET; 248 CPU_REG (PMU_BASE, PMU_STAT) |= PMU_WARMRESET;
249} 249}
250
251static void h720x__idle(void)
252{
253 CPU_REG (PMU_BASE, PMU_MODE) = PMU_MODE_IDLE;
254 nop();
255 nop();
256 CPU_REG (PMU_BASE, PMU_MODE) = PMU_MODE_RUN;
257 nop();
258 nop();
259}
260
261static int __init h720x_idle_init(void)
262{
263 arm_pm_idle = h720x__idle;
264 return 0;
265}
266
267arch_initcall(h720x_idle_init);
diff --git a/arch/arm/mach-h720x/include/mach/system.h b/arch/arm/mach-h720x/include/mach/system.h
deleted file mode 100644
index 16ac46e239aa..000000000000
--- a/arch/arm/mach-h720x/include/mach/system.h
+++ /dev/null
@@ -1,27 +0,0 @@
1/*
2 * arch/arm/mach-h720x/include/mach/system.h
3 *
4 * Copyright (C) 2001-2002 Jungjun Kim, Hynix Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 * arch/arm/mach-h720x/include/mach/system.h
10 *
11 */
12
13#ifndef __ASM_ARCH_SYSTEM_H
14#define __ASM_ARCH_SYSTEM_H
15#include <mach/hardware.h>
16
17static void arch_idle(void)
18{
19 CPU_REG (PMU_BASE, PMU_MODE) = PMU_MODE_IDLE;
20 nop();
21 nop();
22 CPU_REG (PMU_BASE, PMU_MODE) = PMU_MODE_RUN;
23 nop();
24 nop();
25}
26
27#endif
diff --git a/arch/arm/mach-highbank/include/mach/system.h b/arch/arm/mach-highbank/include/mach/system.h
deleted file mode 100644
index b1d8b5fbe373..000000000000
--- a/arch/arm/mach-highbank/include/mach/system.h
+++ /dev/null
@@ -1,24 +0,0 @@
1/*
2 * Copyright 2010-2011 Calxeda, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16#ifndef __MACH_SYSTEM_H
17#define __MACH_SYSTEM_H
18
19static inline void arch_idle(void)
20{
21 cpu_do_idle();
22}
23
24#endif
diff --git a/arch/arm/mach-imx/mach-mx31moboard.c b/arch/arm/mach-imx/mach-mx31moboard.c
index f225262b5c38..96e042d0c9a9 100644
--- a/arch/arm/mach-imx/mach-mx31moboard.c
+++ b/arch/arm/mach-imx/mach-mx31moboard.c
@@ -507,7 +507,7 @@ static void mx31moboard_poweroff(void)
507 struct clk *clk = clk_get_sys("imx2-wdt.0", NULL); 507 struct clk *clk = clk_get_sys("imx2-wdt.0", NULL);
508 508
509 if (!IS_ERR(clk)) 509 if (!IS_ERR(clk))
510 clk_enable(clk); 510 clk_prepare_enable(clk);
511 511
512 mxc_iomux_mode(MX31_PIN_WATCHDOG_RST__WATCHDOG_RST); 512 mxc_iomux_mode(MX31_PIN_WATCHDOG_RST__WATCHDOG_RST);
513 513
diff --git a/arch/arm/mach-imx/mm-imx3.c b/arch/arm/mach-imx/mm-imx3.c
index 31807d2a8b7b..8404ee72555a 100644
--- a/arch/arm/mach-imx/mm-imx3.c
+++ b/arch/arm/mach-imx/mm-imx3.c
@@ -34,31 +34,29 @@ static void imx3_idle(void)
34{ 34{
35 unsigned long reg = 0; 35 unsigned long reg = 0;
36 36
37 if (!need_resched()) 37 __asm__ __volatile__(
38 __asm__ __volatile__( 38 /* disable I and D cache */
39 /* disable I and D cache */ 39 "mrc p15, 0, %0, c1, c0, 0\n"
40 "mrc p15, 0, %0, c1, c0, 0\n" 40 "bic %0, %0, #0x00001000\n"
41 "bic %0, %0, #0x00001000\n" 41 "bic %0, %0, #0x00000004\n"
42 "bic %0, %0, #0x00000004\n" 42 "mcr p15, 0, %0, c1, c0, 0\n"
43 "mcr p15, 0, %0, c1, c0, 0\n" 43 /* invalidate I cache */
44 /* invalidate I cache */ 44 "mov %0, #0\n"
45 "mov %0, #0\n" 45 "mcr p15, 0, %0, c7, c5, 0\n"
46 "mcr p15, 0, %0, c7, c5, 0\n" 46 /* clear and invalidate D cache */
47 /* clear and invalidate D cache */ 47 "mov %0, #0\n"
48 "mov %0, #0\n" 48 "mcr p15, 0, %0, c7, c14, 0\n"
49 "mcr p15, 0, %0, c7, c14, 0\n" 49 /* WFI */
50 /* WFI */ 50 "mov %0, #0\n"
51 "mov %0, #0\n" 51 "mcr p15, 0, %0, c7, c0, 4\n"
52 "mcr p15, 0, %0, c7, c0, 4\n" 52 "nop\n" "nop\n" "nop\n" "nop\n"
53 "nop\n" "nop\n" "nop\n" "nop\n" 53 "nop\n" "nop\n" "nop\n"
54 "nop\n" "nop\n" "nop\n" 54 /* enable I and D cache */
55 /* enable I and D cache */ 55 "mrc p15, 0, %0, c1, c0, 0\n"
56 "mrc p15, 0, %0, c1, c0, 0\n" 56 "orr %0, %0, #0x00001000\n"
57 "orr %0, %0, #0x00001000\n" 57 "orr %0, %0, #0x00000004\n"
58 "orr %0, %0, #0x00000004\n" 58 "mcr p15, 0, %0, c1, c0, 0\n"
59 "mcr p15, 0, %0, c1, c0, 0\n" 59 : "=r" (reg));
60 : "=r" (reg));
61 local_irq_enable();
62} 60}
63 61
64static void __iomem *imx3_ioremap(unsigned long phys_addr, size_t size, 62static void __iomem *imx3_ioremap(unsigned long phys_addr, size_t size,
@@ -134,8 +132,8 @@ void __init imx31_init_early(void)
134{ 132{
135 mxc_set_cpu_type(MXC_CPU_MX31); 133 mxc_set_cpu_type(MXC_CPU_MX31);
136 mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR)); 134 mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
137 pm_idle = imx3_idle;
138 imx_ioremap = imx3_ioremap; 135 imx_ioremap = imx3_ioremap;
136 arm_pm_idle = imx3_idle;
139} 137}
140 138
141void __init mx31_init_irq(void) 139void __init mx31_init_irq(void)
@@ -197,7 +195,7 @@ void __init imx35_init_early(void)
197 mxc_set_cpu_type(MXC_CPU_MX35); 195 mxc_set_cpu_type(MXC_CPU_MX35);
198 mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR)); 196 mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
199 mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR)); 197 mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
200 pm_idle = imx3_idle; 198 arm_pm_idle = imx3_idle;
201 imx_ioremap = imx3_ioremap; 199 imx_ioremap = imx3_ioremap;
202} 200}
203 201
diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c
index bc17dfea3817..49549a72dc7d 100644
--- a/arch/arm/mach-imx/mm-imx5.c
+++ b/arch/arm/mach-imx/mm-imx5.c
@@ -26,23 +26,17 @@ static struct clk *gpc_dvfs_clk;
26 26
27static void imx5_idle(void) 27static void imx5_idle(void)
28{ 28{
29 if (!need_resched()) { 29 /* gpc clock is needed for SRPG */
30 /* gpc clock is needed for SRPG */ 30 if (gpc_dvfs_clk == NULL) {
31 if (gpc_dvfs_clk == NULL) { 31 gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs");
32 gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs"); 32 if (IS_ERR(gpc_dvfs_clk))
33 if (IS_ERR(gpc_dvfs_clk)) 33 return;
34 goto err0;
35 }
36 clk_enable(gpc_dvfs_clk);
37 mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
38 if (tzic_enable_wake())
39 goto err1;
40 cpu_do_idle();
41err1:
42 clk_disable(gpc_dvfs_clk);
43 } 34 }
44err0: 35 clk_enable(gpc_dvfs_clk);
45 local_irq_enable(); 36 mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
37 if (tzic_enable_wake() != 0)
38 cpu_do_idle();
39 clk_disable(gpc_dvfs_clk);
46} 40}
47 41
48/* 42/*
@@ -108,7 +102,7 @@ void __init imx51_init_early(void)
108 mxc_set_cpu_type(MXC_CPU_MX51); 102 mxc_set_cpu_type(MXC_CPU_MX51);
109 mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR)); 103 mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
110 mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR)); 104 mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
111 pm_idle = imx5_idle; 105 arm_pm_idle = imx5_idle;
112} 106}
113 107
114void __init imx53_init_early(void) 108void __init imx53_init_early(void)
diff --git a/arch/arm/mach-imx/pm-imx27.c b/arch/arm/mach-imx/pm-imx27.c
index e455d2f855bf..6fcffa7db978 100644
--- a/arch/arm/mach-imx/pm-imx27.c
+++ b/arch/arm/mach-imx/pm-imx27.c
@@ -10,7 +10,6 @@
10#include <linux/kernel.h> 10#include <linux/kernel.h>
11#include <linux/suspend.h> 11#include <linux/suspend.h>
12#include <linux/io.h> 12#include <linux/io.h>
13#include <mach/system.h>
14#include <mach/hardware.h> 13#include <mach/hardware.h>
15 14
16static int mx27_suspend_enter(suspend_state_t state) 15static int mx27_suspend_enter(suspend_state_t state)
@@ -23,7 +22,7 @@ static int mx27_suspend_enter(suspend_state_t state)
23 cscr &= 0xFFFFFFFC; 22 cscr &= 0xFFFFFFFC;
24 __raw_writel(cscr, MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR)); 23 __raw_writel(cscr, MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR));
25 /* Executes WFI */ 24 /* Executes WFI */
26 arch_idle(); 25 cpu_do_idle();
27 break; 26 break;
28 27
29 default: 28 default:
diff --git a/arch/arm/mach-imx/pm-imx5.c b/arch/arm/mach-imx/pm-imx5.c
index 6dc093448057..e26a9cb05ed8 100644
--- a/arch/arm/mach-imx/pm-imx5.c
+++ b/arch/arm/mach-imx/pm-imx5.c
@@ -89,7 +89,7 @@ void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode)
89 89
90static int mx5_suspend_prepare(void) 90static int mx5_suspend_prepare(void)
91{ 91{
92 return clk_enable(gpc_dvfs_clk); 92 return clk_prepare_enable(gpc_dvfs_clk);
93} 93}
94 94
95static int mx5_suspend_enter(suspend_state_t state) 95static int mx5_suspend_enter(suspend_state_t state)
@@ -119,7 +119,7 @@ static int mx5_suspend_enter(suspend_state_t state)
119 119
120static void mx5_suspend_finish(void) 120static void mx5_suspend_finish(void)
121{ 121{
122 clk_disable(gpc_dvfs_clk); 122 clk_disable_unprepare(gpc_dvfs_clk);
123} 123}
124 124
125static int mx5_pm_valid(suspend_state_t state) 125static int mx5_pm_valid(suspend_state_t state)
diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c
index 019f0ab08f66..15b87f26ac96 100644
--- a/arch/arm/mach-integrator/core.c
+++ b/arch/arm/mach-integrator/core.c
@@ -35,67 +35,23 @@
35 35
36static struct amba_pl010_data integrator_uart_data; 36static struct amba_pl010_data integrator_uart_data;
37 37
38static struct amba_device rtc_device = { 38#define INTEGRATOR_RTC_IRQ { IRQ_RTCINT }
39 .dev = { 39#define INTEGRATOR_UART0_IRQ { IRQ_UARTINT0 }
40 .init_name = "mb:15", 40#define INTEGRATOR_UART1_IRQ { IRQ_UARTINT1 }
41 }, 41#define KMI0_IRQ { IRQ_KMIINT0 }
42 .res = { 42#define KMI1_IRQ { IRQ_KMIINT1 }
43 .start = INTEGRATOR_RTC_BASE,
44 .end = INTEGRATOR_RTC_BASE + SZ_4K - 1,
45 .flags = IORESOURCE_MEM,
46 },
47 .irq = { IRQ_RTCINT, NO_IRQ },
48};
49 43
50static struct amba_device uart0_device = { 44static AMBA_APB_DEVICE(rtc, "mb:15", 0,
51 .dev = { 45 INTEGRATOR_RTC_BASE, INTEGRATOR_RTC_IRQ, NULL);
52 .init_name = "mb:16",
53 .platform_data = &integrator_uart_data,
54 },
55 .res = {
56 .start = INTEGRATOR_UART0_BASE,
57 .end = INTEGRATOR_UART0_BASE + SZ_4K - 1,
58 .flags = IORESOURCE_MEM,
59 },
60 .irq = { IRQ_UARTINT0, NO_IRQ },
61};
62 46
63static struct amba_device uart1_device = { 47static AMBA_APB_DEVICE(uart0, "mb:16", 0,
64 .dev = { 48 INTEGRATOR_UART0_BASE, INTEGRATOR_UART0_IRQ, &integrator_uart_data);
65 .init_name = "mb:17",
66 .platform_data = &integrator_uart_data,
67 },
68 .res = {
69 .start = INTEGRATOR_UART1_BASE,
70 .end = INTEGRATOR_UART1_BASE + SZ_4K - 1,
71 .flags = IORESOURCE_MEM,
72 },
73 .irq = { IRQ_UARTINT1, NO_IRQ },
74};
75 49
76static struct amba_device kmi0_device = { 50static AMBA_APB_DEVICE(uart1, "mb:17", 0,
77 .dev = { 51 INTEGRATOR_UART1_BASE, INTEGRATOR_UART1_IRQ, &integrator_uart_data);
78 .init_name = "mb:18",
79 },
80 .res = {
81 .start = KMI0_BASE,
82 .end = KMI0_BASE + SZ_4K - 1,
83 .flags = IORESOURCE_MEM,
84 },
85 .irq = { IRQ_KMIINT0, NO_IRQ },
86};
87 52
88static struct amba_device kmi1_device = { 53static AMBA_APB_DEVICE(kmi0, "mb:18", 0, KMI0_BASE, KMI0_IRQ, NULL);
89 .dev = { 54static AMBA_APB_DEVICE(kmi1, "mb:19", 0, KMI1_BASE, KMI1_IRQ, NULL);
90 .init_name = "mb:19",
91 },
92 .res = {
93 .start = KMI1_BASE,
94 .end = KMI1_BASE + SZ_4K - 1,
95 .flags = IORESOURCE_MEM,
96 },
97 .irq = { IRQ_KMIINT1, NO_IRQ },
98};
99 55
100static struct amba_device *amba_devs[] __initdata = { 56static struct amba_device *amba_devs[] __initdata = {
101 &rtc_device, 57 &rtc_device,
diff --git a/arch/arm/mach-integrator/impd1.c b/arch/arm/mach-integrator/impd1.c
index 8cbb75a96bd4..3e538da6cb1f 100644
--- a/arch/arm/mach-integrator/impd1.c
+++ b/arch/arm/mach-integrator/impd1.c
@@ -401,24 +401,21 @@ static int impd1_probe(struct lm_device *dev)
401 401
402 pc_base = dev->resource.start + idev->offset; 402 pc_base = dev->resource.start + idev->offset;
403 403
404 d = kzalloc(sizeof(struct amba_device), GFP_KERNEL); 404 d = amba_device_alloc(NULL, pc_base, SZ_4K);
405 if (!d) 405 if (!d)
406 continue; 406 continue;
407 407
408 dev_set_name(&d->dev, "lm%x:%5.5lx", dev->id, idev->offset >> 12); 408 dev_set_name(&d->dev, "lm%x:%5.5lx", dev->id, idev->offset >> 12);
409 d->dev.parent = &dev->dev; 409 d->dev.parent = &dev->dev;
410 d->res.start = dev->resource.start + idev->offset;
411 d->res.end = d->res.start + SZ_4K - 1;
412 d->res.flags = IORESOURCE_MEM;
413 d->irq[0] = dev->irq; 410 d->irq[0] = dev->irq;
414 d->irq[1] = dev->irq; 411 d->irq[1] = dev->irq;
415 d->periphid = idev->id; 412 d->periphid = idev->id;
416 d->dev.platform_data = idev->platform_data; 413 d->dev.platform_data = idev->platform_data;
417 414
418 ret = amba_device_register(d, &dev->resource); 415 ret = amba_device_add(d, &dev->resource);
419 if (ret) { 416 if (ret) {
420 dev_err(&d->dev, "unable to register device: %d\n", ret); 417 dev_err(&d->dev, "unable to register device: %d\n", ret);
421 kfree(d); 418 amba_device_put(d);
422 } 419 }
423 } 420 }
424 421
diff --git a/arch/arm/mach-integrator/include/mach/system.h b/arch/arm/mach-integrator/include/mach/system.h
deleted file mode 100644
index 901514eba4a6..000000000000
--- a/arch/arm/mach-integrator/include/mach/system.h
+++ /dev/null
@@ -1,33 +0,0 @@
1/*
2 * arch/arm/mach-integrator/include/mach/system.h
3 *
4 * Copyright (C) 1999 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#ifndef __ASM_ARCH_SYSTEM_H
22#define __ASM_ARCH_SYSTEM_H
23
24static inline void arch_idle(void)
25{
26 /*
27 * This should do all the clock switching
28 * and wait for interrupt tricks
29 */
30 cpu_do_idle();
31}
32
33#endif
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
index a8b6aa6003f3..be9ead4a3bcc 100644
--- a/arch/arm/mach-integrator/integrator_cp.c
+++ b/arch/arm/mach-integrator/integrator_cp.c
@@ -347,32 +347,14 @@ static struct mmci_platform_data mmc_data = {
347 .gpio_cd = -1, 347 .gpio_cd = -1,
348}; 348};
349 349
350static struct amba_device mmc_device = { 350#define INTEGRATOR_CP_MMC_IRQS { IRQ_CP_MMCIINT0, IRQ_CP_MMCIINT1 }
351 .dev = { 351#define INTEGRATOR_CP_AACI_IRQS { IRQ_CP_AACIINT }
352 .init_name = "mb:1c",
353 .platform_data = &mmc_data,
354 },
355 .res = {
356 .start = INTEGRATOR_CP_MMC_BASE,
357 .end = INTEGRATOR_CP_MMC_BASE + SZ_4K - 1,
358 .flags = IORESOURCE_MEM,
359 },
360 .irq = { IRQ_CP_MMCIINT0, IRQ_CP_MMCIINT1 },
361 .periphid = 0,
362};
363 352
364static struct amba_device aaci_device = { 353static AMBA_APB_DEVICE(mmc, "mb:1c", 0, INTEGRATOR_CP_MMC_BASE,
365 .dev = { 354 INTEGRATOR_CP_MMC_IRQS, &mmc_data);
366 .init_name = "mb:1d", 355
367 }, 356static AMBA_APB_DEVICE(aaci, "mb:1d", 0, INTEGRATOR_CP_AACI_BASE,
368 .res = { 357 INTEGRATOR_CP_AACI_IRQS, NULL);
369 .start = INTEGRATOR_CP_AACI_BASE,
370 .end = INTEGRATOR_CP_AACI_BASE + SZ_4K - 1,
371 .flags = IORESOURCE_MEM,
372 },
373 .irq = { IRQ_CP_AACIINT, NO_IRQ },
374 .periphid = 0,
375};
376 358
377 359
378/* 360/*
@@ -425,21 +407,8 @@ static struct clcd_board clcd_data = {
425 .remove = versatile_clcd_remove_dma, 407 .remove = versatile_clcd_remove_dma,
426}; 408};
427 409
428static struct amba_device clcd_device = { 410static AMBA_AHB_DEVICE(clcd, "mb:c0", 0, INTCP_PA_CLCD_BASE,
429 .dev = { 411 { IRQ_CP_CLCDCINT }, &clcd_data);
430 .init_name = "mb:c0",
431 .coherent_dma_mask = ~0,
432 .platform_data = &clcd_data,
433 },
434 .res = {
435 .start = INTCP_PA_CLCD_BASE,
436 .end = INTCP_PA_CLCD_BASE + SZ_4K - 1,
437 .flags = IORESOURCE_MEM,
438 },
439 .dma_mask = ~0,
440 .irq = { IRQ_CP_CLCDCINT, NO_IRQ },
441 .periphid = 0,
442};
443 412
444static struct amba_device *amba_devs[] __initdata = { 413static struct amba_device *amba_devs[] __initdata = {
445 &mmc_device, 414 &mmc_device,
diff --git a/arch/arm/mach-iop13xx/include/mach/system.h b/arch/arm/mach-iop13xx/include/mach/system.h
deleted file mode 100644
index 1f31ed3f8ae2..000000000000
--- a/arch/arm/mach-iop13xx/include/mach/system.h
+++ /dev/null
@@ -1,13 +0,0 @@
1/*
2 * arch/arm/mach-iop13xx/include/mach/system.h
3 *
4 * Copyright (C) 2004 Intel Corp.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10static inline void arch_idle(void)
11{
12 cpu_do_idle();
13}
diff --git a/arch/arm/mach-iop32x/include/mach/system.h b/arch/arm/mach-iop32x/include/mach/system.h
deleted file mode 100644
index 4a88727bca98..000000000000
--- a/arch/arm/mach-iop32x/include/mach/system.h
+++ /dev/null
@@ -1,13 +0,0 @@
1/*
2 * arch/arm/mach-iop32x/include/mach/system.h
3 *
4 * Copyright (C) 2001 MontaVista Software, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10static inline void arch_idle(void)
11{
12 cpu_do_idle();
13}
diff --git a/arch/arm/mach-iop33x/include/mach/system.h b/arch/arm/mach-iop33x/include/mach/system.h
deleted file mode 100644
index 4f98e765397c..000000000000
--- a/arch/arm/mach-iop33x/include/mach/system.h
+++ /dev/null
@@ -1,13 +0,0 @@
1/*
2 * arch/arm/mach-iop33x/include/mach/system.h
3 *
4 * Copyright (C) 2001 MontaVista Software, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10static inline void arch_idle(void)
11{
12 cpu_do_idle();
13}
diff --git a/arch/arm/mach-ixp2000/include/mach/system.h b/arch/arm/mach-ixp2000/include/mach/system.h
deleted file mode 100644
index a7fb08b2b8e7..000000000000
--- a/arch/arm/mach-ixp2000/include/mach/system.h
+++ /dev/null
@@ -1,14 +0,0 @@
1/*
2 * arch/arm/mach-ixp2000/include/mach/system.h
3 *
4 * Copyright (C) 2002 Intel Corp.
5 * Copyricht (C) 2003-2005 MontaVista Software, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11static inline void arch_idle(void)
12{
13 cpu_do_idle();
14}
diff --git a/arch/arm/mach-ixp23xx/core.c b/arch/arm/mach-ixp23xx/core.c
index 0923bb905cc0..7c1495e4fe7a 100644
--- a/arch/arm/mach-ixp23xx/core.c
+++ b/arch/arm/mach-ixp23xx/core.c
@@ -441,6 +441,9 @@ static struct platform_device *ixp23xx_devices[] __initdata = {
441 441
442void __init ixp23xx_sys_init(void) 442void __init ixp23xx_sys_init(void)
443{ 443{
444 /* by default, the idle code is disabled */
445 disable_hlt();
446
444 *IXP23XX_EXP_UNIT_FUSE |= 0xf; 447 *IXP23XX_EXP_UNIT_FUSE |= 0xf;
445 platform_add_devices(ixp23xx_devices, ARRAY_SIZE(ixp23xx_devices)); 448 platform_add_devices(ixp23xx_devices, ARRAY_SIZE(ixp23xx_devices));
446} 449}
diff --git a/arch/arm/mach-ixp23xx/include/mach/system.h b/arch/arm/mach-ixp23xx/include/mach/system.h
deleted file mode 100644
index 277dda7334b9..000000000000
--- a/arch/arm/mach-ixp23xx/include/mach/system.h
+++ /dev/null
@@ -1,16 +0,0 @@
1/*
2 * arch/arm/mach-ixp23xx/include/mach/system.h
3 *
4 * Copyright (C) 2003 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10static inline void arch_idle(void)
11{
12#if 0
13 if (!hlt_counter)
14 cpu_do_idle();
15#endif
16}
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
index 3841ab4146ba..a6329a0a8ec4 100644
--- a/arch/arm/mach-ixp4xx/common.c
+++ b/arch/arm/mach-ixp4xx/common.c
@@ -236,6 +236,12 @@ void __init ixp4xx_init_irq(void)
236{ 236{
237 int i = 0; 237 int i = 0;
238 238
239 /*
240 * ixp4xx does not implement the XScale PWRMODE register
241 * so it must not call cpu_do_idle().
242 */
243 disable_hlt();
244
239 /* Route all sources to IRQ instead of FIQ */ 245 /* Route all sources to IRQ instead of FIQ */
240 *IXP4XX_ICLR = 0x0; 246 *IXP4XX_ICLR = 0x0;
241 247
diff --git a/arch/arm/mach-ixp4xx/include/mach/system.h b/arch/arm/mach-ixp4xx/include/mach/system.h
deleted file mode 100644
index 140a9bef4466..000000000000
--- a/arch/arm/mach-ixp4xx/include/mach/system.h
+++ /dev/null
@@ -1,19 +0,0 @@
1/*
2 * arch/arm/mach-ixp4xx/include/mach/system.h
3 *
4 * Copyright (C) 2002 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11static inline void arch_idle(void)
12{
13 /* ixp4xx does not implement the XScale PWRMODE register,
14 * so it must not call cpu_do_idle() here.
15 */
16#if 0
17 cpu_do_idle();
18#endif
19}
diff --git a/arch/arm/mach-kirkwood/include/mach/system.h b/arch/arm/mach-kirkwood/include/mach/system.h
deleted file mode 100644
index 5fddde002b5e..000000000000
--- a/arch/arm/mach-kirkwood/include/mach/system.h
+++ /dev/null
@@ -1,17 +0,0 @@
1/*
2 * arch/arm/mach-kirkwood/include/mach/system.h
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9#ifndef __ASM_ARCH_SYSTEM_H
10#define __ASM_ARCH_SYSTEM_H
11
12static inline void arch_idle(void)
13{
14 cpu_do_idle();
15}
16
17#endif
diff --git a/arch/arm/mach-ks8695/include/mach/system.h b/arch/arm/mach-ks8695/include/mach/system.h
deleted file mode 100644
index 59fe992395bf..000000000000
--- a/arch/arm/mach-ks8695/include/mach/system.h
+++ /dev/null
@@ -1,27 +0,0 @@
1/*
2 * arch/arm/mach-s3c2410/include/mach/system.h
3 *
4 * Copyright (C) 2006 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * KS8695 - System function defines and includes
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#ifndef __ASM_ARCH_SYSTEM_H
15#define __ASM_ARCH_SYSTEM_H
16
17static void arch_idle(void)
18{
19 /*
20 * This should do all the clock switching
21 * and wait for interrupt tricks,
22 */
23 cpu_do_idle();
24
25}
26
27#endif
diff --git a/arch/arm/mach-lpc32xx/include/mach/system.h b/arch/arm/mach-lpc32xx/include/mach/system.h
deleted file mode 100644
index bf176c991520..000000000000
--- a/arch/arm/mach-lpc32xx/include/mach/system.h
+++ /dev/null
@@ -1,27 +0,0 @@
1/*
2 * arch/arm/mach-lpc32xx/include/mach/system.h
3 *
4 * Author: Kevin Wells <kevin.wells@nxp.com>
5 *
6 * Copyright (C) 2010 NXP Semiconductors
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#ifndef __ASM_ARCH_SYSTEM_H
20#define __ASM_ARCH_SYSTEM_H
21
22static void arch_idle(void)
23{
24 cpu_do_idle();
25}
26
27#endif
diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c
index bfee5b455105..5d51c102c255 100644
--- a/arch/arm/mach-lpc32xx/phy3250.c
+++ b/arch/arm/mach-lpc32xx/phy3250.c
@@ -149,20 +149,8 @@ static struct clcd_board lpc32xx_clcd_data = {
149 .remove = lpc32xx_clcd_remove, 149 .remove = lpc32xx_clcd_remove,
150}; 150};
151 151
152static struct amba_device lpc32xx_clcd_device = { 152static AMBA_AHB_DEVICE(lpc32xx_clcd, "dev:clcd", 0,
153 .dev = { 153 LPC32XX_LCD_BASE, { IRQ_LPC32XX_LCD }, &lpc32xx_clcd_data);
154 .coherent_dma_mask = ~0,
155 .init_name = "dev:clcd",
156 .platform_data = &lpc32xx_clcd_data,
157 },
158 .res = {
159 .start = LPC32XX_LCD_BASE,
160 .end = (LPC32XX_LCD_BASE + SZ_4K - 1),
161 .flags = IORESOURCE_MEM,
162 },
163 .dma_mask = ~0,
164 .irq = {IRQ_LPC32XX_LCD, NO_IRQ},
165};
166 154
167/* 155/*
168 * AMBA SSP (SPI) 156 * AMBA SSP (SPI)
@@ -191,20 +179,8 @@ static struct pl022_ssp_controller lpc32xx_ssp0_data = {
191 .enable_dma = 0, 179 .enable_dma = 0,
192}; 180};
193 181
194static struct amba_device lpc32xx_ssp0_device = { 182static AMBA_APB_DEVICE(lpc32xx_ssp0, "dev:ssp0", 0,
195 .dev = { 183 LPC32XX_SSP0_BASE, { IRQ_LPC32XX_SSP0 }, &lpc32xx_ssp0_data);
196 .coherent_dma_mask = ~0,
197 .init_name = "dev:ssp0",
198 .platform_data = &lpc32xx_ssp0_data,
199 },
200 .res = {
201 .start = LPC32XX_SSP0_BASE,
202 .end = (LPC32XX_SSP0_BASE + SZ_4K - 1),
203 .flags = IORESOURCE_MEM,
204 },
205 .dma_mask = ~0,
206 .irq = {IRQ_LPC32XX_SSP0, NO_IRQ},
207};
208 184
209/* AT25 driver registration */ 185/* AT25 driver registration */
210static int __init phy3250_spi_board_register(void) 186static int __init phy3250_spi_board_register(void)
diff --git a/arch/arm/mach-mmp/include/mach/system.h b/arch/arm/mach-mmp/include/mach/system.h
deleted file mode 100644
index 1d001eab81e1..000000000000
--- a/arch/arm/mach-mmp/include/mach/system.h
+++ /dev/null
@@ -1,16 +0,0 @@
1/*
2 * linux/arch/arm/mach-mmp/include/mach/system.h
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#ifndef __ASM_MACH_SYSTEM_H
10#define __ASM_MACH_SYSTEM_H
11
12static inline void arch_idle(void)
13{
14 cpu_do_idle();
15}
16#endif /* __ASM_MACH_SYSTEM_H */
diff --git a/arch/arm/mach-msm/idle.S b/arch/arm/mach-msm/idle.S
deleted file mode 100644
index 6a94f0527137..000000000000
--- a/arch/arm/mach-msm/idle.S
+++ /dev/null
@@ -1,36 +0,0 @@
1/* arch/arm/mach-msm/include/mach/idle.S
2 *
3 * Idle processing for MSM7K - work around bugs with SWFI.
4 *
5 * Copyright (c) 2007 QUALCOMM Incorporated.
6 * Copyright (C) 2007 Google, Inc.
7 *
8 * This software is licensed under the terms of the GNU General Public
9 * License version 2, as published by the Free Software Foundation, and
10 * may be copied, distributed, and modified under those terms.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 */
18
19#include <linux/linkage.h>
20#include <asm/assembler.h>
21
22ENTRY(arch_idle)
23#ifdef CONFIG_MSM7X00A_IDLE
24 mrc p15, 0, r1, c1, c0, 0 /* read current CR */
25 bic r0, r1, #(1 << 2) /* clear dcache bit */
26 bic r0, r0, #(1 << 12) /* clear icache bit */
27 mcr p15, 0, r0, c1, c0, 0 /* disable d/i cache */
28
29 mov r0, #0 /* prepare wfi value */
30 mcr p15, 0, r0, c7, c10, 0 /* flush the cache */
31 mcr p15, 0, r0, c7, c10, 4 /* memory barrier */
32 mcr p15, 0, r0, c7, c0, 4 /* wait for interrupt */
33
34 mcr p15, 0, r1, c1, c0, 0 /* restore d/i cache */
35#endif
36 mov pc, lr
diff --git a/arch/arm/mach-msm/idle.c b/arch/arm/mach-msm/idle.c
new file mode 100644
index 000000000000..0c9e13c65743
--- /dev/null
+++ b/arch/arm/mach-msm/idle.c
@@ -0,0 +1,49 @@
1/* arch/arm/mach-msm/idle.c
2 *
3 * Idle processing for MSM7K - work around bugs with SWFI.
4 *
5 * Copyright (c) 2007 QUALCOMM Incorporated.
6 * Copyright (C) 2007 Google, Inc.
7 *
8 * This software is licensed under the terms of the GNU General Public
9 * License version 2, as published by the Free Software Foundation, and
10 * may be copied, distributed, and modified under those terms.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 */
18
19#include <linux/init.h>
20#include <asm/system.h>
21
22static void msm_idle(void)
23{
24#ifdef CONFIG_MSM7X00A_IDLE
25 asm volatile (
26
27 "mrc p15, 0, r1, c1, c0, 0 /* read current CR */ \n\t"
28 "bic r0, r1, #(1 << 2) /* clear dcache bit */ \n\t"
29 "bic r0, r0, #(1 << 12) /* clear icache bit */ \n\t"
30 "mcr p15, 0, r0, c1, c0, 0 /* disable d/i cache */ \n\t"
31
32 "mov r0, #0 /* prepare wfi value */ \n\t"
33 "mcr p15, 0, r0, c7, c10, 0 /* flush the cache */ \n\t"
34 "mcr p15, 0, r0, c7, c10, 4 /* memory barrier */ \n\t"
35 "mcr p15, 0, r0, c7, c0, 4 /* wait for interrupt */ \n\t"
36
37 "mcr p15, 0, r1, c1, c0, 0 /* restore d/i cache */ \n\t"
38
39 : : : "r0","r1" );
40#endif
41}
42
43static int __init msm_idle_init(void)
44{
45 arm_pm_idle = msm_idle;
46 return 0;
47}
48
49arch_initcall(msm_idle_init);
diff --git a/arch/arm/mach-msm/include/mach/system.h b/arch/arm/mach-msm/include/mach/system.h
index 311db2b35da0..f5fb2ec87ffe 100644
--- a/arch/arm/mach-msm/include/mach/system.h
+++ b/arch/arm/mach-msm/include/mach/system.h
@@ -12,7 +12,6 @@
12 * GNU General Public License for more details. 12 * GNU General Public License for more details.
13 * 13 *
14 */ 14 */
15void arch_idle(void);
16 15
17/* low level hardware reset hook -- for example, hitting the 16/* low level hardware reset hook -- for example, hitting the
18 * PSHOLD line on the PMIC to hard reset the system 17 * PSHOLD line on the PMIC to hard reset the system
diff --git a/arch/arm/mach-mv78xx0/include/mach/system.h b/arch/arm/mach-mv78xx0/include/mach/system.h
deleted file mode 100644
index 8c3a5387cec7..000000000000
--- a/arch/arm/mach-mv78xx0/include/mach/system.h
+++ /dev/null
@@ -1,17 +0,0 @@
1/*
2 * arch/arm/mach-mv78xx0/include/mach/system.h
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9#ifndef __ASM_ARCH_SYSTEM_H
10#define __ASM_ARCH_SYSTEM_H
11
12static inline void arch_idle(void)
13{
14 cpu_do_idle();
15}
16
17#endif
diff --git a/arch/arm/mach-mxs/devices.c b/arch/arm/mach-mxs/devices.c
index fe3e847930c9..01faffec3064 100644
--- a/arch/arm/mach-mxs/devices.c
+++ b/arch/arm/mach-mxs/devices.c
@@ -77,16 +77,18 @@ err:
77 77
78int __init mxs_add_amba_device(const struct amba_device *dev) 78int __init mxs_add_amba_device(const struct amba_device *dev)
79{ 79{
80 struct amba_device *adev = kmalloc(sizeof(*adev), GFP_KERNEL); 80 struct amba_device *adev = amba_device_alloc(dev->dev.init_name,
81 dev->res.start, resource_size(&dev->res));
81 82
82 if (!adev) { 83 if (!adev) {
83 pr_err("%s: failed to allocate memory", __func__); 84 pr_err("%s: failed to allocate memory", __func__);
84 return -ENOMEM; 85 return -ENOMEM;
85 } 86 }
86 87
87 *adev = *dev; 88 adev->irq[0] = dev->irq[0];
89 adev->irq[1] = dev->irq[1];
88 90
89 return amba_device_register(adev, &iomem_resource); 91 return amba_device_add(adev, &iomem_resource);
90} 92}
91 93
92struct device mxs_apbh_bus = { 94struct device mxs_apbh_bus = {
diff --git a/arch/arm/mach-mxs/devices/amba-duart.c b/arch/arm/mach-mxs/devices/amba-duart.c
index a559db09b49c..a5479f766046 100644
--- a/arch/arm/mach-mxs/devices/amba-duart.c
+++ b/arch/arm/mach-mxs/devices/amba-duart.c
@@ -23,7 +23,7 @@ const struct amba_device name##_device __initconst = { \
23 .end = (soc ## _DUART_BASE_ADDR) + SZ_8K - 1, \ 23 .end = (soc ## _DUART_BASE_ADDR) + SZ_8K - 1, \
24 .flags = IORESOURCE_MEM, \ 24 .flags = IORESOURCE_MEM, \
25 }, \ 25 }, \
26 .irq = {soc ## _INT_DUART, NO_IRQ}, \ 26 .irq = {soc ## _INT_DUART}, \
27} 27}
28 28
29#ifdef CONFIG_SOC_IMX23 29#ifdef CONFIG_SOC_IMX23
diff --git a/arch/arm/mach-mxs/include/mach/system.h b/arch/arm/mach-mxs/include/mach/system.h
deleted file mode 100644
index e7ad1bb29423..000000000000
--- a/arch/arm/mach-mxs/include/mach/system.h
+++ /dev/null
@@ -1,25 +0,0 @@
1/*
2 * Copyright (C) 1999 ARM Limited
3 * Copyright (C) 2000 Deep Blue Solutions Ltd
4 * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#ifndef __MACH_MXS_SYSTEM_H__
18#define __MACH_MXS_SYSTEM_H__
19
20static inline void arch_idle(void)
21{
22 cpu_do_idle();
23}
24
25#endif /* __MACH_MXS_SYSTEM_H__ */
diff --git a/arch/arm/mach-mxs/pm.c b/arch/arm/mach-mxs/pm.c
index fb042da29bda..a9b4bbcdafb4 100644
--- a/arch/arm/mach-mxs/pm.c
+++ b/arch/arm/mach-mxs/pm.c
@@ -15,13 +15,12 @@
15#include <linux/kernel.h> 15#include <linux/kernel.h>
16#include <linux/suspend.h> 16#include <linux/suspend.h>
17#include <linux/io.h> 17#include <linux/io.h>
18#include <mach/system.h>
19 18
20static int mxs_suspend_enter(suspend_state_t state) 19static int mxs_suspend_enter(suspend_state_t state)
21{ 20{
22 switch (state) { 21 switch (state) {
23 case PM_SUSPEND_MEM: 22 case PM_SUSPEND_MEM:
24 arch_idle(); 23 cpu_do_idle();
25 break; 24 break;
26 25
27 default: 26 default:
diff --git a/arch/arm/mach-netx/fb.c b/arch/arm/mach-netx/fb.c
index b9913234bbf6..2cdf6ef69bee 100644
--- a/arch/arm/mach-netx/fb.c
+++ b/arch/arm/mach-netx/fb.c
@@ -92,18 +92,7 @@ void clk_put(struct clk *clk)
92{ 92{
93} 93}
94 94
95static struct amba_device fb_device = { 95static AMBA_AHB_DEVICE(fb, "fb", 0, 0x00104000, { NETX_IRQ_LCD }, NULL);
96 .dev = {
97 .init_name = "fb",
98 .coherent_dma_mask = ~0,
99 },
100 .res = {
101 .start = 0x00104000,
102 .end = 0x00104fff,
103 .flags = IORESOURCE_MEM,
104 },
105 .irq = { NETX_IRQ_LCD, NO_IRQ },
106};
107 96
108int netx_fb_init(struct clcd_board *board, struct clcd_panel *panel) 97int netx_fb_init(struct clcd_board *board, struct clcd_panel *panel)
109{ 98{
diff --git a/arch/arm/mach-netx/include/mach/system.h b/arch/arm/mach-netx/include/mach/system.h
deleted file mode 100644
index b38fa36d58c4..000000000000
--- a/arch/arm/mach-netx/include/mach/system.h
+++ /dev/null
@@ -1,28 +0,0 @@
1/*
2 * arch/arm/mach-netx/include/mach/system.h
3 *
4 * Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2
8 * as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19#ifndef __ASM_ARCH_SYSTEM_H
20#define __ASM_ARCH_SYSTEM_H
21
22static inline void arch_idle(void)
23{
24 cpu_do_idle();
25}
26
27#endif
28
diff --git a/arch/arm/mach-nomadik/board-nhk8815.c b/arch/arm/mach-nomadik/board-nhk8815.c
index 7c878bf00340..f6f74adbe8c4 100644
--- a/arch/arm/mach-nomadik/board-nhk8815.c
+++ b/arch/arm/mach-nomadik/board-nhk8815.c
@@ -185,20 +185,11 @@ static void __init nhk8815_onenand_init(void)
185#endif 185#endif
186} 186}
187 187
188#define __MEM_4K_RESOURCE(x) \ 188static AMBA_APB_DEVICE(uart0, "uart0", 0, NOMADIK_UART0_BASE,
189 .res = {.start = (x), .end = (x) + SZ_4K - 1, .flags = IORESOURCE_MEM} 189 { IRQ_UART0 }, NULL);
190 190
191static struct amba_device uart0_device = { 191static AMBA_APB_DEVICE(uart1, "uart1", 0, NOMADIK_UART1_BASE,
192 .dev = { .init_name = "uart0" }, 192 { IRQ_UART1 }, NULL);
193 __MEM_4K_RESOURCE(NOMADIK_UART0_BASE),
194 .irq = {IRQ_UART0, NO_IRQ},
195};
196
197static struct amba_device uart1_device = {
198 .dev = { .init_name = "uart1" },
199 __MEM_4K_RESOURCE(NOMADIK_UART1_BASE),
200 .irq = {IRQ_UART1, NO_IRQ},
201};
202 193
203static struct amba_device *amba_devs[] __initdata = { 194static struct amba_device *amba_devs[] __initdata = {
204 &uart0_device, 195 &uart0_device,
diff --git a/arch/arm/mach-nomadik/cpu-8815.c b/arch/arm/mach-nomadik/cpu-8815.c
index 65df7b4fdd3e..27f43a46985e 100644
--- a/arch/arm/mach-nomadik/cpu-8815.c
+++ b/arch/arm/mach-nomadik/cpu-8815.c
@@ -97,12 +97,7 @@ static struct platform_device cpu8815_platform_gpio[] = {
97 GPIO_DEVICE(3), 97 GPIO_DEVICE(3),
98}; 98};
99 99
100static struct amba_device cpu8815_amba_rng = { 100static AMBA_APB_DEVICE(cpu8815_amba_rng, "rng", 0, NOMADIK_RNG_BASE, { }, NULL);
101 .dev = {
102 .init_name = "rng",
103 },
104 __MEM_4K_RESOURCE(NOMADIK_RNG_BASE),
105};
106 101
107static struct platform_device *platform_devs[] __initdata = { 102static struct platform_device *platform_devs[] __initdata = {
108 cpu8815_platform_gpio + 0, 103 cpu8815_platform_gpio + 0,
@@ -112,7 +107,7 @@ static struct platform_device *platform_devs[] __initdata = {
112}; 107};
113 108
114static struct amba_device *amba_devs[] __initdata = { 109static struct amba_device *amba_devs[] __initdata = {
115 &cpu8815_amba_rng 110 &cpu8815_amba_rng_device
116}; 111};
117 112
118static int __init cpu8815_init(void) 113static int __init cpu8815_init(void)
diff --git a/arch/arm/mach-nomadik/include/mach/system.h b/arch/arm/mach-nomadik/include/mach/system.h
deleted file mode 100644
index 25e198b8976c..000000000000
--- a/arch/arm/mach-nomadik/include/mach/system.h
+++ /dev/null
@@ -1,32 +0,0 @@
1/*
2 * mach-nomadik/include/mach/system.h
3 *
4 * Copyright (C) 2008 STMicroelectronics
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#ifndef __ASM_ARCH_SYSTEM_H
21#define __ASM_ARCH_SYSTEM_H
22
23static inline void arch_idle(void)
24{
25 /*
26 * This should do all the clock switching
27 * and wait for interrupt tricks
28 */
29 cpu_do_idle();
30}
31
32#endif
diff --git a/arch/arm/mach-omap1/include/mach/system.h b/arch/arm/mach-omap1/include/mach/system.h
deleted file mode 100644
index a6c1b3a16dfc..000000000000
--- a/arch/arm/mach-omap1/include/mach/system.h
+++ /dev/null
@@ -1,5 +0,0 @@
1/*
2 * arch/arm/mach-omap1/include/mach/system.h
3 */
4
5#include <plat/system.h>
diff --git a/arch/arm/mach-omap1/pm.c b/arch/arm/mach-omap1/pm.c
index 89ea20ca0ccc..0c2c3669d594 100644
--- a/arch/arm/mach-omap1/pm.c
+++ b/arch/arm/mach-omap1/pm.c
@@ -42,9 +42,9 @@
42#include <linux/sysfs.h> 42#include <linux/sysfs.h>
43#include <linux/module.h> 43#include <linux/module.h>
44#include <linux/io.h> 44#include <linux/io.h>
45#include <linux/atomic.h>
45 46
46#include <asm/irq.h> 47#include <asm/irq.h>
47#include <linux/atomic.h>
48#include <asm/mach/time.h> 48#include <asm/mach/time.h>
49#include <asm/mach/irq.h> 49#include <asm/mach/irq.h>
50 50
@@ -108,13 +108,7 @@ void omap1_pm_idle(void)
108 __u32 use_idlect1 = arm_idlect1_mask; 108 __u32 use_idlect1 = arm_idlect1_mask;
109 int do_sleep = 0; 109 int do_sleep = 0;
110 110
111 local_irq_disable();
112 local_fiq_disable(); 111 local_fiq_disable();
113 if (need_resched()) {
114 local_fiq_enable();
115 local_irq_enable();
116 return;
117 }
118 112
119#if defined(CONFIG_OMAP_MPU_TIMER) && !defined(CONFIG_OMAP_DM_TIMER) 113#if defined(CONFIG_OMAP_MPU_TIMER) && !defined(CONFIG_OMAP_DM_TIMER)
120#warning Enable 32kHz OS timer in order to allow sleep states in idle 114#warning Enable 32kHz OS timer in order to allow sleep states in idle
@@ -157,14 +151,12 @@ void omap1_pm_idle(void)
157 omap_writel(saved_idlect1, ARM_IDLECT1); 151 omap_writel(saved_idlect1, ARM_IDLECT1);
158 152
159 local_fiq_enable(); 153 local_fiq_enable();
160 local_irq_enable();
161 return; 154 return;
162 } 155 }
163 omap_sram_suspend(omap_readl(ARM_IDLECT1), 156 omap_sram_suspend(omap_readl(ARM_IDLECT1),
164 omap_readl(ARM_IDLECT2)); 157 omap_readl(ARM_IDLECT2));
165 158
166 local_fiq_enable(); 159 local_fiq_enable();
167 local_irq_enable();
168} 160}
169 161
170/* 162/*
@@ -583,8 +575,6 @@ static void omap_pm_init_proc(void)
583 575
584#endif /* DEBUG && CONFIG_PROC_FS */ 576#endif /* DEBUG && CONFIG_PROC_FS */
585 577
586static void (*saved_idle)(void) = NULL;
587
588/* 578/*
589 * omap_pm_prepare - Do preliminary suspend work. 579 * omap_pm_prepare - Do preliminary suspend work.
590 * 580 *
@@ -592,8 +582,7 @@ static void (*saved_idle)(void) = NULL;
592static int omap_pm_prepare(void) 582static int omap_pm_prepare(void)
593{ 583{
594 /* We cannot sleep in idle until we have resumed */ 584 /* We cannot sleep in idle until we have resumed */
595 saved_idle = pm_idle; 585 disable_hlt();
596 pm_idle = NULL;
597 586
598 return 0; 587 return 0;
599} 588}
@@ -630,7 +619,7 @@ static int omap_pm_enter(suspend_state_t state)
630 619
631static void omap_pm_finish(void) 620static void omap_pm_finish(void)
632{ 621{
633 pm_idle = saved_idle; 622 enable_hlt();
634} 623}
635 624
636 625
@@ -687,7 +676,7 @@ static int __init omap_pm_init(void)
687 return -ENODEV; 676 return -ENODEV;
688 } 677 }
689 678
690 pm_idle = omap1_pm_idle; 679 arm_pm_idle = omap1_pm_idle;
691 680
692 if (cpu_is_omap7xx()) 681 if (cpu_is_omap7xx())
693 setup_irq(INT_7XX_WAKE_UP_REQ, &omap_wakeup_irq); 682 setup_irq(INT_7XX_WAKE_UP_REQ, &omap_wakeup_irq);
diff --git a/arch/arm/mach-omap2/emu.c b/arch/arm/mach-omap2/emu.c
index 9c442e290ccb..ce91aad4cdad 100644
--- a/arch/arm/mach-omap2/emu.c
+++ b/arch/arm/mach-omap2/emu.c
@@ -30,29 +30,8 @@ MODULE_AUTHOR("Alexander Shishkin");
30#define ETB_BASE (L4_EMU_34XX_PHYS + 0x1b000) 30#define ETB_BASE (L4_EMU_34XX_PHYS + 0x1b000)
31#define DAPCTL (L4_EMU_34XX_PHYS + 0x1d000) 31#define DAPCTL (L4_EMU_34XX_PHYS + 0x1d000)
32 32
33static struct amba_device omap3_etb_device = { 33static AMBA_APB_DEVICE(omap3_etb, "etb", 0x000bb907, ETB_BASE, { }, NULL);
34 .dev = { 34static AMBA_APB_DEVICE(omap3_etm, "etm", 0x102bb921, ETM_BASE, { }, NULL);
35 .init_name = "etb",
36 },
37 .res = {
38 .start = ETB_BASE,
39 .end = ETB_BASE + SZ_4K - 1,
40 .flags = IORESOURCE_MEM,
41 },
42 .periphid = 0x000bb907,
43};
44
45static struct amba_device omap3_etm_device = {
46 .dev = {
47 .init_name = "etm",
48 },
49 .res = {
50 .start = ETM_BASE,
51 .end = ETM_BASE + SZ_4K - 1,
52 .flags = IORESOURCE_MEM,
53 },
54 .periphid = 0x102bb921,
55};
56 35
57static int __init emu_init(void) 36static int __init emu_init(void)
58{ 37{
@@ -66,4 +45,3 @@ static int __init emu_init(void)
66} 45}
67 46
68subsys_initcall(emu_init); 47subsys_initcall(emu_init);
69
diff --git a/arch/arm/mach-omap2/include/mach/system.h b/arch/arm/mach-omap2/include/mach/system.h
deleted file mode 100644
index d488721ab90b..000000000000
--- a/arch/arm/mach-omap2/include/mach/system.h
+++ /dev/null
@@ -1,5 +0,0 @@
1/*
2 * arch/arm/mach-omap2/include/mach/system.h
3 */
4
5#include <plat/system.h>
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index b8822f8b2891..1f736222a629 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -232,7 +232,6 @@ static int omap2_can_sleep(void)
232 232
233static void omap2_pm_idle(void) 233static void omap2_pm_idle(void)
234{ 234{
235 local_irq_disable();
236 local_fiq_disable(); 235 local_fiq_disable();
237 236
238 if (!omap2_can_sleep()) { 237 if (!omap2_can_sleep()) {
@@ -249,7 +248,6 @@ static void omap2_pm_idle(void)
249 248
250out: 249out:
251 local_fiq_enable(); 250 local_fiq_enable();
252 local_irq_enable();
253} 251}
254 252
255#ifdef CONFIG_SUSPEND 253#ifdef CONFIG_SUSPEND
@@ -468,7 +466,7 @@ static int __init omap2_pm_init(void)
468 } 466 }
469 467
470 suspend_set_ops(&omap_pm_ops); 468 suspend_set_ops(&omap_pm_ops);
471 pm_idle = omap2_pm_idle; 469 arm_pm_idle = omap2_pm_idle;
472 470
473 return 0; 471 return 0;
474} 472}
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index fc6987578920..b77df735fa6c 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -418,10 +418,9 @@ void omap_sram_idle(void)
418 418
419static void omap3_pm_idle(void) 419static void omap3_pm_idle(void)
420{ 420{
421 local_irq_disable();
422 local_fiq_disable(); 421 local_fiq_disable();
423 422
424 if (omap_irq_pending() || need_resched()) 423 if (omap_irq_pending())
425 goto out; 424 goto out;
426 425
427 trace_power_start(POWER_CSTATE, 1, smp_processor_id()); 426 trace_power_start(POWER_CSTATE, 1, smp_processor_id());
@@ -434,7 +433,6 @@ static void omap3_pm_idle(void)
434 433
435out: 434out:
436 local_fiq_enable(); 435 local_fiq_enable();
437 local_irq_enable();
438} 436}
439 437
440#ifdef CONFIG_SUSPEND 438#ifdef CONFIG_SUSPEND
@@ -848,7 +846,7 @@ static int __init omap3_pm_init(void)
848 suspend_set_ops(&omap_pm_ops); 846 suspend_set_ops(&omap_pm_ops);
849#endif /* CONFIG_SUSPEND */ 847#endif /* CONFIG_SUSPEND */
850 848
851 pm_idle = omap3_pm_idle; 849 arm_pm_idle = omap3_pm_idle;
852 omap3_idle_init(); 850 omap3_idle_init();
853 851
854 /* 852 /*
diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
index c264ef7219c1..c840689df24a 100644
--- a/arch/arm/mach-omap2/pm44xx.c
+++ b/arch/arm/mach-omap2/pm44xx.c
@@ -173,18 +173,16 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
173 * omap_default_idle - OMAP4 default ilde routine.' 173 * omap_default_idle - OMAP4 default ilde routine.'
174 * 174 *
175 * Implements OMAP4 memory, IO ordering requirements which can't be addressed 175 * Implements OMAP4 memory, IO ordering requirements which can't be addressed
176 * with default arch_idle() hook. Used by all CPUs with !CONFIG_CPUIDLE and 176 * with default cpu_do_idle() hook. Used by all CPUs with !CONFIG_CPUIDLE and
177 * by secondary CPU with CONFIG_CPUIDLE. 177 * by secondary CPU with CONFIG_CPUIDLE.
178 */ 178 */
179static void omap_default_idle(void) 179static void omap_default_idle(void)
180{ 180{
181 local_irq_disable();
182 local_fiq_disable(); 181 local_fiq_disable();
183 182
184 omap_do_wfi(); 183 omap_do_wfi();
185 184
186 local_fiq_enable(); 185 local_fiq_enable();
187 local_irq_enable();
188} 186}
189 187
190/** 188/**
@@ -255,8 +253,8 @@ static int __init omap4_pm_init(void)
255 suspend_set_ops(&omap_pm_ops); 253 suspend_set_ops(&omap_pm_ops);
256#endif /* CONFIG_SUSPEND */ 254#endif /* CONFIG_SUSPEND */
257 255
258 /* Overwrite the default arch_idle() */ 256 /* Overwrite the default cpu_do_idle() */
259 pm_idle = omap_default_idle; 257 arm_pm_idle = omap_default_idle;
260 258
261 omap4_idle_init(); 259 omap4_idle_init();
262 260
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index 860118ab43e2..873b51d494ea 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -24,7 +24,6 @@
24#include <linux/interrupt.h> 24#include <linux/interrupt.h>
25#include <linux/slab.h> 25#include <linux/slab.h>
26 26
27#include <mach/system.h>
28#include <plat/common.h> 27#include <plat/common.h>
29#include <plat/prcm.h> 28#include <plat/prcm.h>
30#include <plat/irqs.h> 29#include <plat/irqs.h>
diff --git a/arch/arm/mach-orion5x/include/mach/system.h b/arch/arm/mach-orion5x/include/mach/system.h
deleted file mode 100644
index 825a2650cefa..000000000000
--- a/arch/arm/mach-orion5x/include/mach/system.h
+++ /dev/null
@@ -1,19 +0,0 @@
1/*
2 * arch/arm/mach-orion5x/include/mach/system.h
3 *
4 * Tzachi Perelstein <tzachi@marvell.com>
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#ifndef __ASM_ARCH_SYSTEM_H
12#define __ASM_ARCH_SYSTEM_H
13
14static inline void arch_idle(void)
15{
16 cpu_do_idle();
17}
18
19#endif
diff --git a/arch/arm/mach-picoxcell/include/mach/system.h b/arch/arm/mach-picoxcell/include/mach/system.h
deleted file mode 100644
index 1a5d8cb57df4..000000000000
--- a/arch/arm/mach-picoxcell/include/mach/system.h
+++ /dev/null
@@ -1,26 +0,0 @@
1/*
2 * Copyright (c) 2011 Picochip Ltd., Jamie Iles
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14#ifndef __ASM_ARCH_SYSTEM_H
15#define __ASM_ARCH_SYSTEM_H
16
17static inline void arch_idle(void)
18{
19 /*
20 * This should do all the clock switching and wait for interrupt
21 * tricks.
22 */
23 cpu_do_idle();
24}
25
26#endif /* __ASM_ARCH_SYSTEM_H */
diff --git a/arch/arm/mach-pnx4008/include/mach/system.h b/arch/arm/mach-pnx4008/include/mach/system.h
deleted file mode 100644
index 60cfe7188091..000000000000
--- a/arch/arm/mach-pnx4008/include/mach/system.h
+++ /dev/null
@@ -1,29 +0,0 @@
1/*
2 * arch/arm/mach-pnx4008/include/mach/system.h
3 *
4 * Copyright (C) 2003 Philips Semiconductors
5 * Copyright (C) 2005 MontaVista Software, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#ifndef __ASM_ARCH_SYSTEM_H
22#define __ASM_ARCH_SYSTEM_H
23
24static void arch_idle(void)
25{
26 cpu_do_idle();
27}
28
29#endif
diff --git a/arch/arm/mach-prima2/include/mach/system.h b/arch/arm/mach-prima2/include/mach/system.h
deleted file mode 100644
index 2c7d2a9d0c92..000000000000
--- a/arch/arm/mach-prima2/include/mach/system.h
+++ /dev/null
@@ -1,17 +0,0 @@
1/*
2 * arch/arm/mach-prima2/include/mach/system.h
3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#ifndef __MACH_SYSTEM_H__
10#define __MACH_SYSTEM_H__
11
12static inline void arch_idle(void)
13{
14 cpu_do_idle();
15}
16
17#endif
diff --git a/arch/arm/mach-pxa/include/mach/system.h b/arch/arm/mach-pxa/include/mach/system.h
deleted file mode 100644
index c5afacd3cc0b..000000000000
--- a/arch/arm/mach-pxa/include/mach/system.h
+++ /dev/null
@@ -1,15 +0,0 @@
1/*
2 * arch/arm/mach-pxa/include/mach/system.h
3 *
4 * Author: Nicolas Pitre
5 * Created: Jun 15, 2001
6 * Copyright: MontaVista Software Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12static inline void arch_idle(void)
13{
14 cpu_do_idle();
15}
diff --git a/arch/arm/mach-realview/core.h b/arch/arm/mach-realview/core.h
index 735b57aaf2d6..f8f2c0ac4c01 100644
--- a/arch/arm/mach-realview/core.h
+++ b/arch/arm/mach-realview/core.h
@@ -28,21 +28,11 @@
28#include <asm/setup.h> 28#include <asm/setup.h>
29#include <asm/leds.h> 29#include <asm/leds.h>
30 30
31#define AMBA_DEVICE(name,busid,base,plat) \ 31#define APB_DEVICE(name, busid, base, plat) \
32static struct amba_device name##_device = { \ 32static AMBA_APB_DEVICE(name, busid, 0, REALVIEW_##base##_BASE, base##_IRQ, plat)
33 .dev = { \ 33
34 .coherent_dma_mask = ~0, \ 34#define AHB_DEVICE(name, busid, base, plat) \
35 .init_name = busid, \ 35static AMBA_AHB_DEVICE(name, busid, 0, REALVIEW_##base##_BASE, base##_IRQ, plat)
36 .platform_data = plat, \
37 }, \
38 .res = { \
39 .start = REALVIEW_##base##_BASE, \
40 .end = (REALVIEW_##base##_BASE) + SZ_4K - 1, \
41 .flags = IORESOURCE_MEM, \
42 }, \
43 .dma_mask = ~0, \
44 .irq = base##_IRQ, \
45}
46 36
47struct machine_desc; 37struct machine_desc;
48 38
diff --git a/arch/arm/mach-realview/include/mach/irqs-pb1176.h b/arch/arm/mach-realview/include/mach/irqs-pb1176.h
index 5c3c625e3e04..708f84156f2c 100644
--- a/arch/arm/mach-realview/include/mach/irqs-pb1176.h
+++ b/arch/arm/mach-realview/include/mach/irqs-pb1176.h
@@ -40,6 +40,7 @@
40#define IRQ_DC1176_L2CC (IRQ_DC1176_GIC_START + 13) 40#define IRQ_DC1176_L2CC (IRQ_DC1176_GIC_START + 13)
41#define IRQ_DC1176_RTC (IRQ_DC1176_GIC_START + 14) 41#define IRQ_DC1176_RTC (IRQ_DC1176_GIC_START + 14)
42#define IRQ_DC1176_CLCD (IRQ_DC1176_GIC_START + 15) /* CLCD controller */ 42#define IRQ_DC1176_CLCD (IRQ_DC1176_GIC_START + 15) /* CLCD controller */
43#define IRQ_DC1176_GPIO0 (IRQ_DC1176_GIC_START + 16)
43#define IRQ_DC1176_SSP (IRQ_DC1176_GIC_START + 17) /* SSP port */ 44#define IRQ_DC1176_SSP (IRQ_DC1176_GIC_START + 17) /* SSP port */
44#define IRQ_DC1176_UART0 (IRQ_DC1176_GIC_START + 18) /* UART 0 on development chip */ 45#define IRQ_DC1176_UART0 (IRQ_DC1176_GIC_START + 18) /* UART 0 on development chip */
45#define IRQ_DC1176_UART1 (IRQ_DC1176_GIC_START + 19) /* UART 1 on development chip */ 46#define IRQ_DC1176_UART1 (IRQ_DC1176_GIC_START + 19) /* UART 1 on development chip */
@@ -73,7 +74,6 @@
73#define IRQ_PB1176_DMAC (IRQ_PB1176_GIC_START + 24) /* DMA controller */ 74#define IRQ_PB1176_DMAC (IRQ_PB1176_GIC_START + 24) /* DMA controller */
74#define IRQ_PB1176_RTC (IRQ_PB1176_GIC_START + 25) /* Real Time Clock */ 75#define IRQ_PB1176_RTC (IRQ_PB1176_GIC_START + 25) /* Real Time Clock */
75 76
76#define IRQ_PB1176_GPIO0 -1
77#define IRQ_PB1176_SCTL -1 77#define IRQ_PB1176_SCTL -1
78 78
79#define NR_GIC_PB1176 2 79#define NR_GIC_PB1176 2
diff --git a/arch/arm/mach-realview/include/mach/system.h b/arch/arm/mach-realview/include/mach/system.h
deleted file mode 100644
index 471b671159ce..000000000000
--- a/arch/arm/mach-realview/include/mach/system.h
+++ /dev/null
@@ -1,33 +0,0 @@
1/*
2 * arch/arm/mach-realview/include/mach/system.h
3 *
4 * Copyright (C) 2003 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#ifndef __ASM_ARCH_SYSTEM_H
22#define __ASM_ARCH_SYSTEM_H
23
24static inline void arch_idle(void)
25{
26 /*
27 * This should do all the clock switching
28 * and wait for interrupt tricks
29 */
30 cpu_do_idle();
31}
32
33#endif
diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c
index 9578145f2df0..157e1bc6e83c 100644
--- a/arch/arm/mach-realview/realview_eb.c
+++ b/arch/arm/mach-realview/realview_eb.c
@@ -135,63 +135,63 @@ static struct pl022_ssp_controller ssp0_plat_data = {
135/* 135/*
136 * These devices are connected via the core APB bridge 136 * These devices are connected via the core APB bridge
137 */ 137 */
138#define GPIO2_IRQ { IRQ_EB_GPIO2, NO_IRQ } 138#define GPIO2_IRQ { IRQ_EB_GPIO2 }
139#define GPIO3_IRQ { IRQ_EB_GPIO3, NO_IRQ } 139#define GPIO3_IRQ { IRQ_EB_GPIO3 }
140 140
141#define AACI_IRQ { IRQ_EB_AACI, NO_IRQ } 141#define AACI_IRQ { IRQ_EB_AACI }
142#define MMCI0_IRQ { IRQ_EB_MMCI0A, IRQ_EB_MMCI0B } 142#define MMCI0_IRQ { IRQ_EB_MMCI0A, IRQ_EB_MMCI0B }
143#define KMI0_IRQ { IRQ_EB_KMI0, NO_IRQ } 143#define KMI0_IRQ { IRQ_EB_KMI0 }
144#define KMI1_IRQ { IRQ_EB_KMI1, NO_IRQ } 144#define KMI1_IRQ { IRQ_EB_KMI1 }
145 145
146/* 146/*
147 * These devices are connected directly to the multi-layer AHB switch 147 * These devices are connected directly to the multi-layer AHB switch
148 */ 148 */
149#define EB_SMC_IRQ { NO_IRQ, NO_IRQ } 149#define EB_SMC_IRQ { }
150#define MPMC_IRQ { NO_IRQ, NO_IRQ } 150#define MPMC_IRQ { }
151#define EB_CLCD_IRQ { IRQ_EB_CLCD, NO_IRQ } 151#define EB_CLCD_IRQ { IRQ_EB_CLCD }
152#define DMAC_IRQ { IRQ_EB_DMA, NO_IRQ } 152#define DMAC_IRQ { IRQ_EB_DMA }
153 153
154/* 154/*
155 * These devices are connected via the core APB bridge 155 * These devices are connected via the core APB bridge
156 */ 156 */
157#define SCTL_IRQ { NO_IRQ, NO_IRQ } 157#define SCTL_IRQ { }
158#define EB_WATCHDOG_IRQ { IRQ_EB_WDOG, NO_IRQ } 158#define EB_WATCHDOG_IRQ { IRQ_EB_WDOG }
159#define EB_GPIO0_IRQ { IRQ_EB_GPIO0, NO_IRQ } 159#define EB_GPIO0_IRQ { IRQ_EB_GPIO0 }
160#define GPIO1_IRQ { IRQ_EB_GPIO1, NO_IRQ } 160#define GPIO1_IRQ { IRQ_EB_GPIO1 }
161#define EB_RTC_IRQ { IRQ_EB_RTC, NO_IRQ } 161#define EB_RTC_IRQ { IRQ_EB_RTC }
162 162
163/* 163/*
164 * These devices are connected via the DMA APB bridge 164 * These devices are connected via the DMA APB bridge
165 */ 165 */
166#define SCI_IRQ { IRQ_EB_SCI, NO_IRQ } 166#define SCI_IRQ { IRQ_EB_SCI }
167#define EB_UART0_IRQ { IRQ_EB_UART0, NO_IRQ } 167#define EB_UART0_IRQ { IRQ_EB_UART0 }
168#define EB_UART1_IRQ { IRQ_EB_UART1, NO_IRQ } 168#define EB_UART1_IRQ { IRQ_EB_UART1 }
169#define EB_UART2_IRQ { IRQ_EB_UART2, NO_IRQ } 169#define EB_UART2_IRQ { IRQ_EB_UART2 }
170#define EB_UART3_IRQ { IRQ_EB_UART3, NO_IRQ } 170#define EB_UART3_IRQ { IRQ_EB_UART3 }
171#define EB_SSP_IRQ { IRQ_EB_SSP, NO_IRQ } 171#define EB_SSP_IRQ { IRQ_EB_SSP }
172 172
173/* FPGA Primecells */ 173/* FPGA Primecells */
174AMBA_DEVICE(aaci, "fpga:aaci", AACI, NULL); 174APB_DEVICE(aaci, "fpga:aaci", AACI, NULL);
175AMBA_DEVICE(mmc0, "fpga:mmc0", MMCI0, &realview_mmc0_plat_data); 175APB_DEVICE(mmc0, "fpga:mmc0", MMCI0, &realview_mmc0_plat_data);
176AMBA_DEVICE(kmi0, "fpga:kmi0", KMI0, NULL); 176APB_DEVICE(kmi0, "fpga:kmi0", KMI0, NULL);
177AMBA_DEVICE(kmi1, "fpga:kmi1", KMI1, NULL); 177APB_DEVICE(kmi1, "fpga:kmi1", KMI1, NULL);
178AMBA_DEVICE(uart3, "fpga:uart3", EB_UART3, NULL); 178APB_DEVICE(uart3, "fpga:uart3", EB_UART3, NULL);
179 179
180/* DevChip Primecells */ 180/* DevChip Primecells */
181AMBA_DEVICE(smc, "dev:smc", EB_SMC, NULL); 181AHB_DEVICE(smc, "dev:smc", EB_SMC, NULL);
182AMBA_DEVICE(clcd, "dev:clcd", EB_CLCD, &clcd_plat_data); 182AHB_DEVICE(clcd, "dev:clcd", EB_CLCD, &clcd_plat_data);
183AMBA_DEVICE(dmac, "dev:dmac", DMAC, NULL); 183AHB_DEVICE(dmac, "dev:dmac", DMAC, NULL);
184AMBA_DEVICE(sctl, "dev:sctl", SCTL, NULL); 184AHB_DEVICE(sctl, "dev:sctl", SCTL, NULL);
185AMBA_DEVICE(wdog, "dev:wdog", EB_WATCHDOG, NULL); 185APB_DEVICE(wdog, "dev:wdog", EB_WATCHDOG, NULL);
186AMBA_DEVICE(gpio0, "dev:gpio0", EB_GPIO0, &gpio0_plat_data); 186APB_DEVICE(gpio0, "dev:gpio0", EB_GPIO0, &gpio0_plat_data);
187AMBA_DEVICE(gpio1, "dev:gpio1", GPIO1, &gpio1_plat_data); 187APB_DEVICE(gpio1, "dev:gpio1", GPIO1, &gpio1_plat_data);
188AMBA_DEVICE(gpio2, "dev:gpio2", GPIO2, &gpio2_plat_data); 188APB_DEVICE(gpio2, "dev:gpio2", GPIO2, &gpio2_plat_data);
189AMBA_DEVICE(rtc, "dev:rtc", EB_RTC, NULL); 189APB_DEVICE(rtc, "dev:rtc", EB_RTC, NULL);
190AMBA_DEVICE(sci0, "dev:sci0", SCI, NULL); 190APB_DEVICE(sci0, "dev:sci0", SCI, NULL);
191AMBA_DEVICE(uart0, "dev:uart0", EB_UART0, NULL); 191APB_DEVICE(uart0, "dev:uart0", EB_UART0, NULL);
192AMBA_DEVICE(uart1, "dev:uart1", EB_UART1, NULL); 192APB_DEVICE(uart1, "dev:uart1", EB_UART1, NULL);
193AMBA_DEVICE(uart2, "dev:uart2", EB_UART2, NULL); 193APB_DEVICE(uart2, "dev:uart2", EB_UART2, NULL);
194AMBA_DEVICE(ssp0, "dev:ssp0", EB_SSP, &ssp0_plat_data); 194APB_DEVICE(ssp0, "dev:ssp0", EB_SSP, &ssp0_plat_data);
195 195
196static struct amba_device *amba_devs[] __initdata = { 196static struct amba_device *amba_devs[] __initdata = {
197 &dmac_device, 197 &dmac_device,
diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c
index e4abe94fb11a..b1d7cafa1a6d 100644
--- a/arch/arm/mach-realview/realview_pb1176.c
+++ b/arch/arm/mach-realview/realview_pb1176.c
@@ -132,50 +132,50 @@ static struct pl022_ssp_controller ssp0_plat_data = {
132/* 132/*
133 * RealView PB1176 AMBA devices 133 * RealView PB1176 AMBA devices
134 */ 134 */
135#define GPIO2_IRQ { IRQ_PB1176_GPIO2, NO_IRQ } 135#define GPIO2_IRQ { IRQ_PB1176_GPIO2 }
136#define GPIO3_IRQ { IRQ_PB1176_GPIO3, NO_IRQ } 136#define GPIO3_IRQ { IRQ_PB1176_GPIO3 }
137#define AACI_IRQ { IRQ_PB1176_AACI, NO_IRQ } 137#define AACI_IRQ { IRQ_PB1176_AACI }
138#define MMCI0_IRQ { IRQ_PB1176_MMCI0A, IRQ_PB1176_MMCI0B } 138#define MMCI0_IRQ { IRQ_PB1176_MMCI0A, IRQ_PB1176_MMCI0B }
139#define KMI0_IRQ { IRQ_PB1176_KMI0, NO_IRQ } 139#define KMI0_IRQ { IRQ_PB1176_KMI0 }
140#define KMI1_IRQ { IRQ_PB1176_KMI1, NO_IRQ } 140#define KMI1_IRQ { IRQ_PB1176_KMI1 }
141#define PB1176_SMC_IRQ { NO_IRQ, NO_IRQ } 141#define PB1176_SMC_IRQ { }
142#define MPMC_IRQ { NO_IRQ, NO_IRQ } 142#define MPMC_IRQ { }
143#define PB1176_CLCD_IRQ { IRQ_DC1176_CLCD, NO_IRQ } 143#define PB1176_CLCD_IRQ { IRQ_DC1176_CLCD }
144#define SCTL_IRQ { NO_IRQ, NO_IRQ } 144#define SCTL_IRQ { }
145#define PB1176_WATCHDOG_IRQ { IRQ_DC1176_WATCHDOG, NO_IRQ } 145#define PB1176_WATCHDOG_IRQ { IRQ_DC1176_WATCHDOG }
146#define PB1176_GPIO0_IRQ { IRQ_PB1176_GPIO0, NO_IRQ } 146#define PB1176_GPIO0_IRQ { IRQ_DC1176_GPIO0 }
147#define GPIO1_IRQ { IRQ_PB1176_GPIO1, NO_IRQ } 147#define GPIO1_IRQ { IRQ_PB1176_GPIO1 }
148#define PB1176_RTC_IRQ { IRQ_DC1176_RTC, NO_IRQ } 148#define PB1176_RTC_IRQ { IRQ_DC1176_RTC }
149#define SCI_IRQ { IRQ_PB1176_SCI, NO_IRQ } 149#define SCI_IRQ { IRQ_PB1176_SCI }
150#define PB1176_UART0_IRQ { IRQ_DC1176_UART0, NO_IRQ } 150#define PB1176_UART0_IRQ { IRQ_DC1176_UART0 }
151#define PB1176_UART1_IRQ { IRQ_DC1176_UART1, NO_IRQ } 151#define PB1176_UART1_IRQ { IRQ_DC1176_UART1 }
152#define PB1176_UART2_IRQ { IRQ_DC1176_UART2, NO_IRQ } 152#define PB1176_UART2_IRQ { IRQ_DC1176_UART2 }
153#define PB1176_UART3_IRQ { IRQ_DC1176_UART3, NO_IRQ } 153#define PB1176_UART3_IRQ { IRQ_DC1176_UART3 }
154#define PB1176_UART4_IRQ { IRQ_PB1176_UART4, NO_IRQ } 154#define PB1176_UART4_IRQ { IRQ_PB1176_UART4 }
155#define PB1176_SSP_IRQ { IRQ_DC1176_SSP, NO_IRQ } 155#define PB1176_SSP_IRQ { IRQ_DC1176_SSP }
156 156
157/* FPGA Primecells */ 157/* FPGA Primecells */
158AMBA_DEVICE(aaci, "fpga:aaci", AACI, NULL); 158APB_DEVICE(aaci, "fpga:aaci", AACI, NULL);
159AMBA_DEVICE(mmc0, "fpga:mmc0", MMCI0, &realview_mmc0_plat_data); 159APB_DEVICE(mmc0, "fpga:mmc0", MMCI0, &realview_mmc0_plat_data);
160AMBA_DEVICE(kmi0, "fpga:kmi0", KMI0, NULL); 160APB_DEVICE(kmi0, "fpga:kmi0", KMI0, NULL);
161AMBA_DEVICE(kmi1, "fpga:kmi1", KMI1, NULL); 161APB_DEVICE(kmi1, "fpga:kmi1", KMI1, NULL);
162AMBA_DEVICE(uart4, "fpga:uart4", PB1176_UART4, NULL); 162APB_DEVICE(uart4, "fpga:uart4", PB1176_UART4, NULL);
163 163
164/* DevChip Primecells */ 164/* DevChip Primecells */
165AMBA_DEVICE(smc, "dev:smc", PB1176_SMC, NULL); 165AHB_DEVICE(smc, "dev:smc", PB1176_SMC, NULL);
166AMBA_DEVICE(sctl, "dev:sctl", SCTL, NULL); 166AHB_DEVICE(sctl, "dev:sctl", SCTL, NULL);
167AMBA_DEVICE(wdog, "dev:wdog", PB1176_WATCHDOG, NULL); 167APB_DEVICE(wdog, "dev:wdog", PB1176_WATCHDOG, NULL);
168AMBA_DEVICE(gpio0, "dev:gpio0", PB1176_GPIO0, &gpio0_plat_data); 168APB_DEVICE(gpio0, "dev:gpio0", PB1176_GPIO0, &gpio0_plat_data);
169AMBA_DEVICE(gpio1, "dev:gpio1", GPIO1, &gpio1_plat_data); 169APB_DEVICE(gpio1, "dev:gpio1", GPIO1, &gpio1_plat_data);
170AMBA_DEVICE(gpio2, "dev:gpio2", GPIO2, &gpio2_plat_data); 170APB_DEVICE(gpio2, "dev:gpio2", GPIO2, &gpio2_plat_data);
171AMBA_DEVICE(rtc, "dev:rtc", PB1176_RTC, NULL); 171APB_DEVICE(rtc, "dev:rtc", PB1176_RTC, NULL);
172AMBA_DEVICE(sci0, "dev:sci0", SCI, NULL); 172APB_DEVICE(sci0, "dev:sci0", SCI, NULL);
173AMBA_DEVICE(uart0, "dev:uart0", PB1176_UART0, NULL); 173APB_DEVICE(uart0, "dev:uart0", PB1176_UART0, NULL);
174AMBA_DEVICE(uart1, "dev:uart1", PB1176_UART1, NULL); 174APB_DEVICE(uart1, "dev:uart1", PB1176_UART1, NULL);
175AMBA_DEVICE(uart2, "dev:uart2", PB1176_UART2, NULL); 175APB_DEVICE(uart2, "dev:uart2", PB1176_UART2, NULL);
176AMBA_DEVICE(uart3, "dev:uart3", PB1176_UART3, NULL); 176APB_DEVICE(uart3, "dev:uart3", PB1176_UART3, NULL);
177AMBA_DEVICE(ssp0, "dev:ssp0", PB1176_SSP, &ssp0_plat_data); 177APB_DEVICE(ssp0, "dev:ssp0", PB1176_SSP, &ssp0_plat_data);
178AMBA_DEVICE(clcd, "dev:clcd", PB1176_CLCD, &clcd_plat_data); 178AHB_DEVICE(clcd, "dev:clcd", PB1176_CLCD, &clcd_plat_data);
179 179
180static struct amba_device *amba_devs[] __initdata = { 180static struct amba_device *amba_devs[] __initdata = {
181 &uart0_device, 181 &uart0_device,
diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c
index 2147335f66f5..ae7fe54f6eb6 100644
--- a/arch/arm/mach-realview/realview_pb11mp.c
+++ b/arch/arm/mach-realview/realview_pb11mp.c
@@ -127,52 +127,52 @@ static struct pl022_ssp_controller ssp0_plat_data = {
127 * RealView PB11MPCore AMBA devices 127 * RealView PB11MPCore AMBA devices
128 */ 128 */
129 129
130#define GPIO2_IRQ { IRQ_PB11MP_GPIO2, NO_IRQ } 130#define GPIO2_IRQ { IRQ_PB11MP_GPIO2 }
131#define GPIO3_IRQ { IRQ_PB11MP_GPIO3, NO_IRQ } 131#define GPIO3_IRQ { IRQ_PB11MP_GPIO3 }
132#define AACI_IRQ { IRQ_TC11MP_AACI, NO_IRQ } 132#define AACI_IRQ { IRQ_TC11MP_AACI }
133#define MMCI0_IRQ { IRQ_TC11MP_MMCI0A, IRQ_TC11MP_MMCI0B } 133#define MMCI0_IRQ { IRQ_TC11MP_MMCI0A, IRQ_TC11MP_MMCI0B }
134#define KMI0_IRQ { IRQ_TC11MP_KMI0, NO_IRQ } 134#define KMI0_IRQ { IRQ_TC11MP_KMI0 }
135#define KMI1_IRQ { IRQ_TC11MP_KMI1, NO_IRQ } 135#define KMI1_IRQ { IRQ_TC11MP_KMI1 }
136#define PB11MP_SMC_IRQ { NO_IRQ, NO_IRQ } 136#define PB11MP_SMC_IRQ { }
137#define MPMC_IRQ { NO_IRQ, NO_IRQ } 137#define MPMC_IRQ { }
138#define PB11MP_CLCD_IRQ { IRQ_PB11MP_CLCD, NO_IRQ } 138#define PB11MP_CLCD_IRQ { IRQ_PB11MP_CLCD }
139#define DMAC_IRQ { IRQ_PB11MP_DMAC, NO_IRQ } 139#define DMAC_IRQ { IRQ_PB11MP_DMAC }
140#define SCTL_IRQ { NO_IRQ, NO_IRQ } 140#define SCTL_IRQ { }
141#define PB11MP_WATCHDOG_IRQ { IRQ_PB11MP_WATCHDOG, NO_IRQ } 141#define PB11MP_WATCHDOG_IRQ { IRQ_PB11MP_WATCHDOG }
142#define PB11MP_GPIO0_IRQ { IRQ_PB11MP_GPIO0, NO_IRQ } 142#define PB11MP_GPIO0_IRQ { IRQ_PB11MP_GPIO0 }
143#define GPIO1_IRQ { IRQ_PB11MP_GPIO1, NO_IRQ } 143#define GPIO1_IRQ { IRQ_PB11MP_GPIO1 }
144#define PB11MP_RTC_IRQ { IRQ_TC11MP_RTC, NO_IRQ } 144#define PB11MP_RTC_IRQ { IRQ_TC11MP_RTC }
145#define SCI_IRQ { IRQ_PB11MP_SCI, NO_IRQ } 145#define SCI_IRQ { IRQ_PB11MP_SCI }
146#define PB11MP_UART0_IRQ { IRQ_TC11MP_UART0, NO_IRQ } 146#define PB11MP_UART0_IRQ { IRQ_TC11MP_UART0 }
147#define PB11MP_UART1_IRQ { IRQ_TC11MP_UART1, NO_IRQ } 147#define PB11MP_UART1_IRQ { IRQ_TC11MP_UART1 }
148#define PB11MP_UART2_IRQ { IRQ_PB11MP_UART2, NO_IRQ } 148#define PB11MP_UART2_IRQ { IRQ_PB11MP_UART2 }
149#define PB11MP_UART3_IRQ { IRQ_PB11MP_UART3, NO_IRQ } 149#define PB11MP_UART3_IRQ { IRQ_PB11MP_UART3 }
150#define PB11MP_SSP_IRQ { IRQ_PB11MP_SSP, NO_IRQ } 150#define PB11MP_SSP_IRQ { IRQ_PB11MP_SSP }
151 151
152/* FPGA Primecells */ 152/* FPGA Primecells */
153AMBA_DEVICE(aaci, "fpga:aaci", AACI, NULL); 153APB_DEVICE(aaci, "fpga:aaci", AACI, NULL);
154AMBA_DEVICE(mmc0, "fpga:mmc0", MMCI0, &realview_mmc0_plat_data); 154APB_DEVICE(mmc0, "fpga:mmc0", MMCI0, &realview_mmc0_plat_data);
155AMBA_DEVICE(kmi0, "fpga:kmi0", KMI0, NULL); 155APB_DEVICE(kmi0, "fpga:kmi0", KMI0, NULL);
156AMBA_DEVICE(kmi1, "fpga:kmi1", KMI1, NULL); 156APB_DEVICE(kmi1, "fpga:kmi1", KMI1, NULL);
157AMBA_DEVICE(uart3, "fpga:uart3", PB11MP_UART3, NULL); 157APB_DEVICE(uart3, "fpga:uart3", PB11MP_UART3, NULL);
158 158
159/* DevChip Primecells */ 159/* DevChip Primecells */
160AMBA_DEVICE(smc, "dev:smc", PB11MP_SMC, NULL); 160AHB_DEVICE(smc, "dev:smc", PB11MP_SMC, NULL);
161AMBA_DEVICE(sctl, "dev:sctl", SCTL, NULL); 161AHB_DEVICE(sctl, "dev:sctl", SCTL, NULL);
162AMBA_DEVICE(wdog, "dev:wdog", PB11MP_WATCHDOG, NULL); 162APB_DEVICE(wdog, "dev:wdog", PB11MP_WATCHDOG, NULL);
163AMBA_DEVICE(gpio0, "dev:gpio0", PB11MP_GPIO0, &gpio0_plat_data); 163APB_DEVICE(gpio0, "dev:gpio0", PB11MP_GPIO0, &gpio0_plat_data);
164AMBA_DEVICE(gpio1, "dev:gpio1", GPIO1, &gpio1_plat_data); 164APB_DEVICE(gpio1, "dev:gpio1", GPIO1, &gpio1_plat_data);
165AMBA_DEVICE(gpio2, "dev:gpio2", GPIO2, &gpio2_plat_data); 165APB_DEVICE(gpio2, "dev:gpio2", GPIO2, &gpio2_plat_data);
166AMBA_DEVICE(rtc, "dev:rtc", PB11MP_RTC, NULL); 166APB_DEVICE(rtc, "dev:rtc", PB11MP_RTC, NULL);
167AMBA_DEVICE(sci0, "dev:sci0", SCI, NULL); 167APB_DEVICE(sci0, "dev:sci0", SCI, NULL);
168AMBA_DEVICE(uart0, "dev:uart0", PB11MP_UART0, NULL); 168APB_DEVICE(uart0, "dev:uart0", PB11MP_UART0, NULL);
169AMBA_DEVICE(uart1, "dev:uart1", PB11MP_UART1, NULL); 169APB_DEVICE(uart1, "dev:uart1", PB11MP_UART1, NULL);
170AMBA_DEVICE(uart2, "dev:uart2", PB11MP_UART2, NULL); 170APB_DEVICE(uart2, "dev:uart2", PB11MP_UART2, NULL);
171AMBA_DEVICE(ssp0, "dev:ssp0", PB11MP_SSP, &ssp0_plat_data); 171APB_DEVICE(ssp0, "dev:ssp0", PB11MP_SSP, &ssp0_plat_data);
172 172
173/* Primecells on the NEC ISSP chip */ 173/* Primecells on the NEC ISSP chip */
174AMBA_DEVICE(clcd, "issp:clcd", PB11MP_CLCD, &clcd_plat_data); 174AHB_DEVICE(clcd, "issp:clcd", PB11MP_CLCD, &clcd_plat_data);
175AMBA_DEVICE(dmac, "issp:dmac", DMAC, NULL); 175AHB_DEVICE(dmac, "issp:dmac", DMAC, NULL);
176 176
177static struct amba_device *amba_devs[] __initdata = { 177static struct amba_device *amba_devs[] __initdata = {
178 &dmac_device, 178 &dmac_device,
diff --git a/arch/arm/mach-realview/realview_pba8.c b/arch/arm/mach-realview/realview_pba8.c
index 25b2e59296f8..59650174e6ed 100644
--- a/arch/arm/mach-realview/realview_pba8.c
+++ b/arch/arm/mach-realview/realview_pba8.c
@@ -122,52 +122,52 @@ static struct pl022_ssp_controller ssp0_plat_data = {
122 * RealView PBA8Core AMBA devices 122 * RealView PBA8Core AMBA devices
123 */ 123 */
124 124
125#define GPIO2_IRQ { IRQ_PBA8_GPIO2, NO_IRQ } 125#define GPIO2_IRQ { IRQ_PBA8_GPIO2 }
126#define GPIO3_IRQ { IRQ_PBA8_GPIO3, NO_IRQ } 126#define GPIO3_IRQ { IRQ_PBA8_GPIO3 }
127#define AACI_IRQ { IRQ_PBA8_AACI, NO_IRQ } 127#define AACI_IRQ { IRQ_PBA8_AACI }
128#define MMCI0_IRQ { IRQ_PBA8_MMCI0A, IRQ_PBA8_MMCI0B } 128#define MMCI0_IRQ { IRQ_PBA8_MMCI0A, IRQ_PBA8_MMCI0B }
129#define KMI0_IRQ { IRQ_PBA8_KMI0, NO_IRQ } 129#define KMI0_IRQ { IRQ_PBA8_KMI0 }
130#define KMI1_IRQ { IRQ_PBA8_KMI1, NO_IRQ } 130#define KMI1_IRQ { IRQ_PBA8_KMI1 }
131#define PBA8_SMC_IRQ { NO_IRQ, NO_IRQ } 131#define PBA8_SMC_IRQ { }
132#define MPMC_IRQ { NO_IRQ, NO_IRQ } 132#define MPMC_IRQ { }
133#define PBA8_CLCD_IRQ { IRQ_PBA8_CLCD, NO_IRQ } 133#define PBA8_CLCD_IRQ { IRQ_PBA8_CLCD }
134#define DMAC_IRQ { IRQ_PBA8_DMAC, NO_IRQ } 134#define DMAC_IRQ { IRQ_PBA8_DMAC }
135#define SCTL_IRQ { NO_IRQ, NO_IRQ } 135#define SCTL_IRQ { }
136#define PBA8_WATCHDOG_IRQ { IRQ_PBA8_WATCHDOG, NO_IRQ } 136#define PBA8_WATCHDOG_IRQ { IRQ_PBA8_WATCHDOG }
137#define PBA8_GPIO0_IRQ { IRQ_PBA8_GPIO0, NO_IRQ } 137#define PBA8_GPIO0_IRQ { IRQ_PBA8_GPIO0 }
138#define GPIO1_IRQ { IRQ_PBA8_GPIO1, NO_IRQ } 138#define GPIO1_IRQ { IRQ_PBA8_GPIO1 }
139#define PBA8_RTC_IRQ { IRQ_PBA8_RTC, NO_IRQ } 139#define PBA8_RTC_IRQ { IRQ_PBA8_RTC }
140#define SCI_IRQ { IRQ_PBA8_SCI, NO_IRQ } 140#define SCI_IRQ { IRQ_PBA8_SCI }
141#define PBA8_UART0_IRQ { IRQ_PBA8_UART0, NO_IRQ } 141#define PBA8_UART0_IRQ { IRQ_PBA8_UART0 }
142#define PBA8_UART1_IRQ { IRQ_PBA8_UART1, NO_IRQ } 142#define PBA8_UART1_IRQ { IRQ_PBA8_UART1 }
143#define PBA8_UART2_IRQ { IRQ_PBA8_UART2, NO_IRQ } 143#define PBA8_UART2_IRQ { IRQ_PBA8_UART2 }
144#define PBA8_UART3_IRQ { IRQ_PBA8_UART3, NO_IRQ } 144#define PBA8_UART3_IRQ { IRQ_PBA8_UART3 }
145#define PBA8_SSP_IRQ { IRQ_PBA8_SSP, NO_IRQ } 145#define PBA8_SSP_IRQ { IRQ_PBA8_SSP }
146 146
147/* FPGA Primecells */ 147/* FPGA Primecells */
148AMBA_DEVICE(aaci, "fpga:aaci", AACI, NULL); 148APB_DEVICE(aaci, "fpga:aaci", AACI, NULL);
149AMBA_DEVICE(mmc0, "fpga:mmc0", MMCI0, &realview_mmc0_plat_data); 149APB_DEVICE(mmc0, "fpga:mmc0", MMCI0, &realview_mmc0_plat_data);
150AMBA_DEVICE(kmi0, "fpga:kmi0", KMI0, NULL); 150APB_DEVICE(kmi0, "fpga:kmi0", KMI0, NULL);
151AMBA_DEVICE(kmi1, "fpga:kmi1", KMI1, NULL); 151APB_DEVICE(kmi1, "fpga:kmi1", KMI1, NULL);
152AMBA_DEVICE(uart3, "fpga:uart3", PBA8_UART3, NULL); 152APB_DEVICE(uart3, "fpga:uart3", PBA8_UART3, NULL);
153 153
154/* DevChip Primecells */ 154/* DevChip Primecells */
155AMBA_DEVICE(smc, "dev:smc", PBA8_SMC, NULL); 155AHB_DEVICE(smc, "dev:smc", PBA8_SMC, NULL);
156AMBA_DEVICE(sctl, "dev:sctl", SCTL, NULL); 156AHB_DEVICE(sctl, "dev:sctl", SCTL, NULL);
157AMBA_DEVICE(wdog, "dev:wdog", PBA8_WATCHDOG, NULL); 157APB_DEVICE(wdog, "dev:wdog", PBA8_WATCHDOG, NULL);
158AMBA_DEVICE(gpio0, "dev:gpio0", PBA8_GPIO0, &gpio0_plat_data); 158APB_DEVICE(gpio0, "dev:gpio0", PBA8_GPIO0, &gpio0_plat_data);
159AMBA_DEVICE(gpio1, "dev:gpio1", GPIO1, &gpio1_plat_data); 159APB_DEVICE(gpio1, "dev:gpio1", GPIO1, &gpio1_plat_data);
160AMBA_DEVICE(gpio2, "dev:gpio2", GPIO2, &gpio2_plat_data); 160APB_DEVICE(gpio2, "dev:gpio2", GPIO2, &gpio2_plat_data);
161AMBA_DEVICE(rtc, "dev:rtc", PBA8_RTC, NULL); 161APB_DEVICE(rtc, "dev:rtc", PBA8_RTC, NULL);
162AMBA_DEVICE(sci0, "dev:sci0", SCI, NULL); 162APB_DEVICE(sci0, "dev:sci0", SCI, NULL);
163AMBA_DEVICE(uart0, "dev:uart0", PBA8_UART0, NULL); 163APB_DEVICE(uart0, "dev:uart0", PBA8_UART0, NULL);
164AMBA_DEVICE(uart1, "dev:uart1", PBA8_UART1, NULL); 164APB_DEVICE(uart1, "dev:uart1", PBA8_UART1, NULL);
165AMBA_DEVICE(uart2, "dev:uart2", PBA8_UART2, NULL); 165APB_DEVICE(uart2, "dev:uart2", PBA8_UART2, NULL);
166AMBA_DEVICE(ssp0, "dev:ssp0", PBA8_SSP, &ssp0_plat_data); 166APB_DEVICE(ssp0, "dev:ssp0", PBA8_SSP, &ssp0_plat_data);
167 167
168/* Primecells on the NEC ISSP chip */ 168/* Primecells on the NEC ISSP chip */
169AMBA_DEVICE(clcd, "issp:clcd", PBA8_CLCD, &clcd_plat_data); 169AHB_DEVICE(clcd, "issp:clcd", PBA8_CLCD, &clcd_plat_data);
170AMBA_DEVICE(dmac, "issp:dmac", DMAC, NULL); 170AHB_DEVICE(dmac, "issp:dmac", DMAC, NULL);
171 171
172static struct amba_device *amba_devs[] __initdata = { 172static struct amba_device *amba_devs[] __initdata = {
173 &dmac_device, 173 &dmac_device,
diff --git a/arch/arm/mach-realview/realview_pbx.c b/arch/arm/mach-realview/realview_pbx.c
index ac715645b860..1cd9956f5875 100644
--- a/arch/arm/mach-realview/realview_pbx.c
+++ b/arch/arm/mach-realview/realview_pbx.c
@@ -144,52 +144,52 @@ static struct pl022_ssp_controller ssp0_plat_data = {
144 * RealView PBXCore AMBA devices 144 * RealView PBXCore AMBA devices
145 */ 145 */
146 146
147#define GPIO2_IRQ { IRQ_PBX_GPIO2, NO_IRQ } 147#define GPIO2_IRQ { IRQ_PBX_GPIO2 }
148#define GPIO3_IRQ { IRQ_PBX_GPIO3, NO_IRQ } 148#define GPIO3_IRQ { IRQ_PBX_GPIO3 }
149#define AACI_IRQ { IRQ_PBX_AACI, NO_IRQ } 149#define AACI_IRQ { IRQ_PBX_AACI }
150#define MMCI0_IRQ { IRQ_PBX_MMCI0A, IRQ_PBX_MMCI0B } 150#define MMCI0_IRQ { IRQ_PBX_MMCI0A, IRQ_PBX_MMCI0B }
151#define KMI0_IRQ { IRQ_PBX_KMI0, NO_IRQ } 151#define KMI0_IRQ { IRQ_PBX_KMI0 }
152#define KMI1_IRQ { IRQ_PBX_KMI1, NO_IRQ } 152#define KMI1_IRQ { IRQ_PBX_KMI1 }
153#define PBX_SMC_IRQ { NO_IRQ, NO_IRQ } 153#define PBX_SMC_IRQ { }
154#define MPMC_IRQ { NO_IRQ, NO_IRQ } 154#define MPMC_IRQ { }
155#define PBX_CLCD_IRQ { IRQ_PBX_CLCD, NO_IRQ } 155#define PBX_CLCD_IRQ { IRQ_PBX_CLCD }
156#define DMAC_IRQ { IRQ_PBX_DMAC, NO_IRQ } 156#define DMAC_IRQ { IRQ_PBX_DMAC }
157#define SCTL_IRQ { NO_IRQ, NO_IRQ } 157#define SCTL_IRQ { }
158#define PBX_WATCHDOG_IRQ { IRQ_PBX_WATCHDOG, NO_IRQ } 158#define PBX_WATCHDOG_IRQ { IRQ_PBX_WATCHDOG }
159#define PBX_GPIO0_IRQ { IRQ_PBX_GPIO0, NO_IRQ } 159#define PBX_GPIO0_IRQ { IRQ_PBX_GPIO0 }
160#define GPIO1_IRQ { IRQ_PBX_GPIO1, NO_IRQ } 160#define GPIO1_IRQ { IRQ_PBX_GPIO1 }
161#define PBX_RTC_IRQ { IRQ_PBX_RTC, NO_IRQ } 161#define PBX_RTC_IRQ { IRQ_PBX_RTC }
162#define SCI_IRQ { IRQ_PBX_SCI, NO_IRQ } 162#define SCI_IRQ { IRQ_PBX_SCI }
163#define PBX_UART0_IRQ { IRQ_PBX_UART0, NO_IRQ } 163#define PBX_UART0_IRQ { IRQ_PBX_UART0 }
164#define PBX_UART1_IRQ { IRQ_PBX_UART1, NO_IRQ } 164#define PBX_UART1_IRQ { IRQ_PBX_UART1 }
165#define PBX_UART2_IRQ { IRQ_PBX_UART2, NO_IRQ } 165#define PBX_UART2_IRQ { IRQ_PBX_UART2 }
166#define PBX_UART3_IRQ { IRQ_PBX_UART3, NO_IRQ } 166#define PBX_UART3_IRQ { IRQ_PBX_UART3 }
167#define PBX_SSP_IRQ { IRQ_PBX_SSP, NO_IRQ } 167#define PBX_SSP_IRQ { IRQ_PBX_SSP }
168 168
169/* FPGA Primecells */ 169/* FPGA Primecells */
170AMBA_DEVICE(aaci, "fpga:aaci", AACI, NULL); 170APB_DEVICE(aaci, "fpga:aaci", AACI, NULL);
171AMBA_DEVICE(mmc0, "fpga:mmc0", MMCI0, &realview_mmc0_plat_data); 171APB_DEVICE(mmc0, "fpga:mmc0", MMCI0, &realview_mmc0_plat_data);
172AMBA_DEVICE(kmi0, "fpga:kmi0", KMI0, NULL); 172APB_DEVICE(kmi0, "fpga:kmi0", KMI0, NULL);
173AMBA_DEVICE(kmi1, "fpga:kmi1", KMI1, NULL); 173APB_DEVICE(kmi1, "fpga:kmi1", KMI1, NULL);
174AMBA_DEVICE(uart3, "fpga:uart3", PBX_UART3, NULL); 174APB_DEVICE(uart3, "fpga:uart3", PBX_UART3, NULL);
175 175
176/* DevChip Primecells */ 176/* DevChip Primecells */
177AMBA_DEVICE(smc, "dev:smc", PBX_SMC, NULL); 177AHB_DEVICE(smc, "dev:smc", PBX_SMC, NULL);
178AMBA_DEVICE(sctl, "dev:sctl", SCTL, NULL); 178AHB_DEVICE(sctl, "dev:sctl", SCTL, NULL);
179AMBA_DEVICE(wdog, "dev:wdog", PBX_WATCHDOG, NULL); 179APB_DEVICE(wdog, "dev:wdog", PBX_WATCHDOG, NULL);
180AMBA_DEVICE(gpio0, "dev:gpio0", PBX_GPIO0, &gpio0_plat_data); 180APB_DEVICE(gpio0, "dev:gpio0", PBX_GPIO0, &gpio0_plat_data);
181AMBA_DEVICE(gpio1, "dev:gpio1", GPIO1, &gpio1_plat_data); 181APB_DEVICE(gpio1, "dev:gpio1", GPIO1, &gpio1_plat_data);
182AMBA_DEVICE(gpio2, "dev:gpio2", GPIO2, &gpio2_plat_data); 182APB_DEVICE(gpio2, "dev:gpio2", GPIO2, &gpio2_plat_data);
183AMBA_DEVICE(rtc, "dev:rtc", PBX_RTC, NULL); 183APB_DEVICE(rtc, "dev:rtc", PBX_RTC, NULL);
184AMBA_DEVICE(sci0, "dev:sci0", SCI, NULL); 184APB_DEVICE(sci0, "dev:sci0", SCI, NULL);
185AMBA_DEVICE(uart0, "dev:uart0", PBX_UART0, NULL); 185APB_DEVICE(uart0, "dev:uart0", PBX_UART0, NULL);
186AMBA_DEVICE(uart1, "dev:uart1", PBX_UART1, NULL); 186APB_DEVICE(uart1, "dev:uart1", PBX_UART1, NULL);
187AMBA_DEVICE(uart2, "dev:uart2", PBX_UART2, NULL); 187APB_DEVICE(uart2, "dev:uart2", PBX_UART2, NULL);
188AMBA_DEVICE(ssp0, "dev:ssp0", PBX_SSP, &ssp0_plat_data); 188APB_DEVICE(ssp0, "dev:ssp0", PBX_SSP, &ssp0_plat_data);
189 189
190/* Primecells on the NEC ISSP chip */ 190/* Primecells on the NEC ISSP chip */
191AMBA_DEVICE(clcd, "issp:clcd", PBX_CLCD, &clcd_plat_data); 191AHB_DEVICE(clcd, "issp:clcd", PBX_CLCD, &clcd_plat_data);
192AMBA_DEVICE(dmac, "issp:dmac", DMAC, NULL); 192AHB_DEVICE(dmac, "issp:dmac", DMAC, NULL);
193 193
194static struct amba_device *amba_devs[] __initdata = { 194static struct amba_device *amba_devs[] __initdata = {
195 &dmac_device, 195 &dmac_device,
diff --git a/arch/arm/mach-rpc/include/mach/system.h b/arch/arm/mach-rpc/include/mach/system.h
deleted file mode 100644
index 359bab94b6af..000000000000
--- a/arch/arm/mach-rpc/include/mach/system.h
+++ /dev/null
@@ -1,13 +0,0 @@
1/*
2 * arch/arm/mach-rpc/include/mach/system.h
3 *
4 * Copyright (C) 1996-1999 Russell King.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10static inline void arch_idle(void)
11{
12 cpu_do_idle();
13}
diff --git a/arch/arm/mach-s3c2410/include/mach/system.h b/arch/arm/mach-s3c2410/include/mach/system.h
deleted file mode 100644
index 5e215c1a5c8f..000000000000
--- a/arch/arm/mach-s3c2410/include/mach/system.h
+++ /dev/null
@@ -1,54 +0,0 @@
1/* arch/arm/mach-s3c2410/include/mach/system.h
2 *
3 * Copyright (c) 2003 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2410 - System function defines and includes
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/io.h>
14#include <mach/hardware.h>
15
16#include <mach/map.h>
17#include <mach/idle.h>
18
19#include <mach/regs-clock.h>
20
21void (*s3c24xx_idle)(void);
22
23void s3c24xx_default_idle(void)
24{
25 unsigned long tmp;
26 int i;
27
28 /* idle the system by using the idle mode which will wait for an
29 * interrupt to happen before restarting the system.
30 */
31
32 /* Warning: going into idle state upsets jtag scanning */
33
34 __raw_writel(__raw_readl(S3C2410_CLKCON) | S3C2410_CLKCON_IDLE,
35 S3C2410_CLKCON);
36
37 /* the samsung port seems to do a loop and then unset idle.. */
38 for (i = 0; i < 50; i++) {
39 tmp += __raw_readl(S3C2410_CLKCON); /* ensure loop not optimised out */
40 }
41
42 /* this bit is not cleared on re-start... */
43
44 __raw_writel(__raw_readl(S3C2410_CLKCON) & ~S3C2410_CLKCON_IDLE,
45 S3C2410_CLKCON);
46}
47
48static void arch_idle(void)
49{
50 if (s3c24xx_idle != NULL)
51 (s3c24xx_idle)();
52 else
53 s3c24xx_default_idle();
54}
diff --git a/arch/arm/mach-s3c2412/s3c2412.c b/arch/arm/mach-s3c2412/s3c2412.c
index aff6e85a97c6..c6eac9871093 100644
--- a/arch/arm/mach-s3c2412/s3c2412.c
+++ b/arch/arm/mach-s3c2412/s3c2412.c
@@ -32,8 +32,6 @@
32#include <asm/proc-fns.h> 32#include <asm/proc-fns.h>
33#include <asm/irq.h> 33#include <asm/irq.h>
34 34
35#include <mach/idle.h>
36
37#include <plat/cpu-freq.h> 35#include <plat/cpu-freq.h>
38 36
39#include <mach/regs-clock.h> 37#include <mach/regs-clock.h>
@@ -164,7 +162,7 @@ void __init s3c2412_map_io(void)
164 162
165 /* set our idle function */ 163 /* set our idle function */
166 164
167 s3c24xx_idle = s3c2412_idle; 165 arm_pm_idle = s3c2412_idle;
168 166
169 /* register our io-tables */ 167 /* register our io-tables */
170 168
diff --git a/arch/arm/mach-s3c2416/s3c2416.c b/arch/arm/mach-s3c2416/s3c2416.c
index 5536392458e2..0e9a71c90ed7 100644
--- a/arch/arm/mach-s3c2416/s3c2416.c
+++ b/arch/arm/mach-s3c2416/s3c2416.c
@@ -44,7 +44,6 @@
44#include <asm/proc-fns.h> 44#include <asm/proc-fns.h>
45#include <asm/irq.h> 45#include <asm/irq.h>
46 46
47#include <mach/idle.h>
48#include <mach/regs-s3c2443-clock.h> 47#include <mach/regs-s3c2443-clock.h>
49 48
50#include <plat/gpio-core.h> 49#include <plat/gpio-core.h>
@@ -89,8 +88,6 @@ int __init s3c2416_init(void)
89{ 88{
90 printk(KERN_INFO "S3C2416: Initializing architecture\n"); 89 printk(KERN_INFO "S3C2416: Initializing architecture\n");
91 90
92 /* s3c24xx_idle = s3c2416_idle; */
93
94 /* change WDT IRQ number */ 91 /* change WDT IRQ number */
95 s3c_device_wdt.resource[1].start = IRQ_S3C2443_WDT; 92 s3c_device_wdt.resource[1].start = IRQ_S3C2443_WDT;
96 s3c_device_wdt.resource[1].end = IRQ_S3C2443_WDT; 93 s3c_device_wdt.resource[1].end = IRQ_S3C2443_WDT;
diff --git a/arch/arm/mach-s3c64xx/include/mach/system.h b/arch/arm/mach-s3c64xx/include/mach/system.h
deleted file mode 100644
index 353ed4389ae7..000000000000
--- a/arch/arm/mach-s3c64xx/include/mach/system.h
+++ /dev/null
@@ -1,19 +0,0 @@
1/* linux/arch/arm/mach-s3c6400/include/mach/system.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C6400 - system implementation
9 */
10
11#ifndef __ASM_ARCH_SYSTEM_H
12#define __ASM_ARCH_SYSTEM_H __FILE__
13
14static void arch_idle(void)
15{
16 /* nothing here yet */
17}
18
19#endif /* __ASM_ARCH_IRQ_H */
diff --git a/arch/arm/mach-s5p64x0/common.c b/arch/arm/mach-s5p64x0/common.c
index 52b89a376447..9143f8b19962 100644
--- a/arch/arm/mach-s5p64x0/common.c
+++ b/arch/arm/mach-s5p64x0/common.c
@@ -146,15 +146,12 @@ static void s5p64x0_idle(void)
146{ 146{
147 unsigned long val; 147 unsigned long val;
148 148
149 if (!need_resched()) { 149 val = __raw_readl(S5P64X0_PWR_CFG);
150 val = __raw_readl(S5P64X0_PWR_CFG); 150 val &= ~(0x3 << 5);
151 val &= ~(0x3 << 5); 151 val |= (0x1 << 5);
152 val |= (0x1 << 5); 152 __raw_writel(val, S5P64X0_PWR_CFG);
153 __raw_writel(val, S5P64X0_PWR_CFG);
154 153
155 cpu_do_idle(); 154 cpu_do_idle();
156 }
157 local_irq_enable();
158} 155}
159 156
160/* 157/*
@@ -286,7 +283,7 @@ int __init s5p64x0_init(void)
286 printk(KERN_INFO "S5P64X0(S5P6440/S5P6450): Initializing architecture\n"); 283 printk(KERN_INFO "S5P64X0(S5P6440/S5P6450): Initializing architecture\n");
287 284
288 /* set idle function */ 285 /* set idle function */
289 pm_idle = s5p64x0_idle; 286 arm_pm_idle = s5p64x0_idle;
290 287
291 return device_register(&s5p64x0_dev); 288 return device_register(&s5p64x0_dev);
292} 289}
diff --git a/arch/arm/mach-s5p64x0/dma.c b/arch/arm/mach-s5p64x0/dma.c
index f820c0744405..f7f68ad77910 100644
--- a/arch/arm/mach-s5p64x0/dma.c
+++ b/arch/arm/mach-s5p64x0/dma.c
@@ -108,34 +108,22 @@ struct dma_pl330_platdata s5p6450_pdma_pdata = {
108 .peri_id = s5p6450_pdma_peri, 108 .peri_id = s5p6450_pdma_peri,
109}; 109};
110 110
111struct amba_device s5p64x0_device_pdma = { 111AMBA_AHB_DEVICE(s5p64x0_pdma, "dma-pl330", 0x00041330, S5P64X0_PA_PDMA,
112 .dev = { 112 {IRQ_DMA0}, NULL);
113 .init_name = "dma-pl330",
114 .dma_mask = &dma_dmamask,
115 .coherent_dma_mask = DMA_BIT_MASK(32),
116 },
117 .res = {
118 .start = S5P64X0_PA_PDMA,
119 .end = S5P64X0_PA_PDMA + SZ_4K,
120 .flags = IORESOURCE_MEM,
121 },
122 .irq = {IRQ_DMA0, NO_IRQ},
123 .periphid = 0x00041330,
124};
125 113
126static int __init s5p64x0_dma_init(void) 114static int __init s5p64x0_dma_init(void)
127{ 115{
128 if (soc_is_s5p6450()) { 116 if (soc_is_s5p6450()) {
129 dma_cap_set(DMA_SLAVE, s5p6450_pdma_pdata.cap_mask); 117 dma_cap_set(DMA_SLAVE, s5p6450_pdma_pdata.cap_mask);
130 dma_cap_set(DMA_CYCLIC, s5p6450_pdma_pdata.cap_mask); 118 dma_cap_set(DMA_CYCLIC, s5p6450_pdma_pdata.cap_mask);
131 s5p64x0_device_pdma.dev.platform_data = &s5p6450_pdma_pdata; 119 s5p64x0_pdma_device.dev.platform_data = &s5p6450_pdma_pdata;
132 } else { 120 } else {
133 dma_cap_set(DMA_SLAVE, s5p6440_pdma_pdata.cap_mask); 121 dma_cap_set(DMA_SLAVE, s5p6440_pdma_pdata.cap_mask);
134 dma_cap_set(DMA_CYCLIC, s5p6440_pdma_pdata.cap_mask); 122 dma_cap_set(DMA_CYCLIC, s5p6440_pdma_pdata.cap_mask);
135 s5p64x0_device_pdma.dev.platform_data = &s5p6440_pdma_pdata; 123 s5p64x0_pdma_device.dev.platform_data = &s5p6440_pdma_pdata;
136 } 124 }
137 125
138 amba_device_register(&s5p64x0_device_pdma, &iomem_resource); 126 amba_device_register(&s5p64x0_pdma_device, &iomem_resource);
139 127
140 return 0; 128 return 0;
141} 129}
diff --git a/arch/arm/mach-s5p64x0/include/mach/system.h b/arch/arm/mach-s5p64x0/include/mach/system.h
deleted file mode 100644
index cf26e0954a2f..000000000000
--- a/arch/arm/mach-s5p64x0/include/mach/system.h
+++ /dev/null
@@ -1,21 +0,0 @@
1/* linux/arch/arm/mach-s5p64x0/include/mach/system.h
2 *
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5P64X0 - system support header
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_SYSTEM_H
14#define __ASM_ARCH_SYSTEM_H __FILE__
15
16static void arch_idle(void)
17{
18 /* nothing here yet */
19}
20
21#endif /* __ASM_ARCH_SYSTEM_H */
diff --git a/arch/arm/mach-s5pc100/common.c b/arch/arm/mach-s5pc100/common.c
index c9095730a7f5..ff71e2d467c6 100644
--- a/arch/arm/mach-s5pc100/common.c
+++ b/arch/arm/mach-s5pc100/common.c
@@ -129,14 +129,6 @@ static struct map_desc s5pc100_iodesc[] __initdata = {
129 } 129 }
130}; 130};
131 131
132static void s5pc100_idle(void)
133{
134 if (!need_resched())
135 cpu_do_idle();
136
137 local_irq_enable();
138}
139
140/* 132/*
141 * s5pc100_map_io 133 * s5pc100_map_io
142 * 134 *
@@ -210,10 +202,6 @@ core_initcall(s5pc100_core_init);
210int __init s5pc100_init(void) 202int __init s5pc100_init(void)
211{ 203{
212 printk(KERN_INFO "S5PC100: Initializing architecture\n"); 204 printk(KERN_INFO "S5PC100: Initializing architecture\n");
213
214 /* set idle function */
215 pm_idle = s5pc100_idle;
216
217 return device_register(&s5pc100_dev); 205 return device_register(&s5pc100_dev);
218} 206}
219 207
diff --git a/arch/arm/mach-s5pc100/dma.c b/arch/arm/mach-s5pc100/dma.c
index c841f4d313f2..96b1ab3dcd48 100644
--- a/arch/arm/mach-s5pc100/dma.c
+++ b/arch/arm/mach-s5pc100/dma.c
@@ -73,21 +73,8 @@ struct dma_pl330_platdata s5pc100_pdma0_pdata = {
73 .peri_id = pdma0_peri, 73 .peri_id = pdma0_peri,
74}; 74};
75 75
76struct amba_device s5pc100_device_pdma0 = { 76AMBA_AHB_DEVICE(s5pc100_pdma0, "dma-pl330.0", 0x00041330, S5PC100_PA_PDMA0,
77 .dev = { 77 {IRQ_PDMA0}, &s5pc100_pdma0_pdata);
78 .init_name = "dma-pl330.0",
79 .dma_mask = &dma_dmamask,
80 .coherent_dma_mask = DMA_BIT_MASK(32),
81 .platform_data = &s5pc100_pdma0_pdata,
82 },
83 .res = {
84 .start = S5PC100_PA_PDMA0,
85 .end = S5PC100_PA_PDMA0 + SZ_4K,
86 .flags = IORESOURCE_MEM,
87 },
88 .irq = {IRQ_PDMA0, NO_IRQ},
89 .periphid = 0x00041330,
90};
91 78
92u8 pdma1_peri[] = { 79u8 pdma1_peri[] = {
93 DMACH_UART0_RX, 80 DMACH_UART0_RX,
@@ -127,31 +114,18 @@ struct dma_pl330_platdata s5pc100_pdma1_pdata = {
127 .peri_id = pdma1_peri, 114 .peri_id = pdma1_peri,
128}; 115};
129 116
130struct amba_device s5pc100_device_pdma1 = { 117AMBA_AHB_DEVICE(s5pc100_pdma1, "dma-pl330.1", 0x00041330, S5PC100_PA_PDMA1,
131 .dev = { 118 {IRQ_PDMA1}, &s5pc100_pdma1_pdata);
132 .init_name = "dma-pl330.1",
133 .dma_mask = &dma_dmamask,
134 .coherent_dma_mask = DMA_BIT_MASK(32),
135 .platform_data = &s5pc100_pdma1_pdata,
136 },
137 .res = {
138 .start = S5PC100_PA_PDMA1,
139 .end = S5PC100_PA_PDMA1 + SZ_4K,
140 .flags = IORESOURCE_MEM,
141 },
142 .irq = {IRQ_PDMA1, NO_IRQ},
143 .periphid = 0x00041330,
144};
145 119
146static int __init s5pc100_dma_init(void) 120static int __init s5pc100_dma_init(void)
147{ 121{
148 dma_cap_set(DMA_SLAVE, s5pc100_pdma0_pdata.cap_mask); 122 dma_cap_set(DMA_SLAVE, s5pc100_pdma0_pdata.cap_mask);
149 dma_cap_set(DMA_CYCLIC, s5pc100_pdma0_pdata.cap_mask); 123 dma_cap_set(DMA_CYCLIC, s5pc100_pdma0_pdata.cap_mask);
150 amba_device_register(&s5pc100_device_pdma0, &iomem_resource); 124 amba_device_register(&s5pc100_pdma0_device, &iomem_resource);
151 125
152 dma_cap_set(DMA_SLAVE, s5pc100_pdma1_pdata.cap_mask); 126 dma_cap_set(DMA_SLAVE, s5pc100_pdma1_pdata.cap_mask);
153 dma_cap_set(DMA_CYCLIC, s5pc100_pdma1_pdata.cap_mask); 127 dma_cap_set(DMA_CYCLIC, s5pc100_pdma1_pdata.cap_mask);
154 amba_device_register(&s5pc100_device_pdma1, &iomem_resource); 128 amba_device_register(&s5pc100_pdma1_device, &iomem_resource);
155 129
156 return 0; 130 return 0;
157} 131}
diff --git a/arch/arm/mach-s5pc100/include/mach/system.h b/arch/arm/mach-s5pc100/include/mach/system.h
deleted file mode 100644
index afc96c298518..000000000000
--- a/arch/arm/mach-s5pc100/include/mach/system.h
+++ /dev/null
@@ -1,19 +0,0 @@
1/* linux/arch/arm/mach-s5pc100/include/mach/system.h
2 *
3 * Copyright 2009 Samsung Electronics Co.
4 * Byungho Min <bhmin@samsung.com>
5 *
6 * S5PC100 - system implementation
7 *
8 * Based on mach-s3c6400/include/mach/system.h
9 */
10
11#ifndef __ASM_ARCH_SYSTEM_H
12#define __ASM_ARCH_SYSTEM_H __FILE__
13
14static void arch_idle(void)
15{
16 /* nothing here yet */
17}
18
19#endif /* __ASM_ARCH_IRQ_H */
diff --git a/arch/arm/mach-s5pv210/common.c b/arch/arm/mach-s5pv210/common.c
index 9c1bcdcc12c3..4c9e9027df9a 100644
--- a/arch/arm/mach-s5pv210/common.c
+++ b/arch/arm/mach-s5pv210/common.c
@@ -142,14 +142,6 @@ static struct map_desc s5pv210_iodesc[] __initdata = {
142 } 142 }
143}; 143};
144 144
145static void s5pv210_idle(void)
146{
147 if (!need_resched())
148 cpu_do_idle();
149
150 local_irq_enable();
151}
152
153void s5pv210_restart(char mode, const char *cmd) 145void s5pv210_restart(char mode, const char *cmd)
154{ 146{
155 __raw_writel(0x1, S5P_SWRESET); 147 __raw_writel(0x1, S5P_SWRESET);
@@ -247,10 +239,6 @@ core_initcall(s5pv210_core_init);
247int __init s5pv210_init(void) 239int __init s5pv210_init(void)
248{ 240{
249 printk(KERN_INFO "S5PV210: Initializing architecture\n"); 241 printk(KERN_INFO "S5PV210: Initializing architecture\n");
250
251 /* set idle function */
252 pm_idle = s5pv210_idle;
253
254 return device_register(&s5pv210_dev); 242 return device_register(&s5pv210_dev);
255} 243}
256 244
diff --git a/arch/arm/mach-s5pv210/dma.c b/arch/arm/mach-s5pv210/dma.c
index a6113e0267f2..f6885d247d14 100644
--- a/arch/arm/mach-s5pv210/dma.c
+++ b/arch/arm/mach-s5pv210/dma.c
@@ -71,21 +71,8 @@ struct dma_pl330_platdata s5pv210_pdma0_pdata = {
71 .peri_id = pdma0_peri, 71 .peri_id = pdma0_peri,
72}; 72};
73 73
74struct amba_device s5pv210_device_pdma0 = { 74AMBA_AHB_DEVICE(s5pv210_pdma0, "dma-pl330.0", 0x00041330, S5PV210_PA_PDMA0,
75 .dev = { 75 {IRQ_PDMA0}, &s5pv210_pdma0_pdata);
76 .init_name = "dma-pl330.0",
77 .dma_mask = &dma_dmamask,
78 .coherent_dma_mask = DMA_BIT_MASK(32),
79 .platform_data = &s5pv210_pdma0_pdata,
80 },
81 .res = {
82 .start = S5PV210_PA_PDMA0,
83 .end = S5PV210_PA_PDMA0 + SZ_4K,
84 .flags = IORESOURCE_MEM,
85 },
86 .irq = {IRQ_PDMA0, NO_IRQ},
87 .periphid = 0x00041330,
88};
89 76
90u8 pdma1_peri[] = { 77u8 pdma1_peri[] = {
91 DMACH_UART0_RX, 78 DMACH_UART0_RX,
@@ -127,31 +114,18 @@ struct dma_pl330_platdata s5pv210_pdma1_pdata = {
127 .peri_id = pdma1_peri, 114 .peri_id = pdma1_peri,
128}; 115};
129 116
130struct amba_device s5pv210_device_pdma1 = { 117AMBA_AHB_DEVICE(s5pv210_pdma1, "dma-pl330.1", 0x00041330, S5PV210_PA_PDMA1,
131 .dev = { 118 {IRQ_PDMA1}, &s5pv210_pdma1_pdata);
132 .init_name = "dma-pl330.1",
133 .dma_mask = &dma_dmamask,
134 .coherent_dma_mask = DMA_BIT_MASK(32),
135 .platform_data = &s5pv210_pdma1_pdata,
136 },
137 .res = {
138 .start = S5PV210_PA_PDMA1,
139 .end = S5PV210_PA_PDMA1 + SZ_4K,
140 .flags = IORESOURCE_MEM,
141 },
142 .irq = {IRQ_PDMA1, NO_IRQ},
143 .periphid = 0x00041330,
144};
145 119
146static int __init s5pv210_dma_init(void) 120static int __init s5pv210_dma_init(void)
147{ 121{
148 dma_cap_set(DMA_SLAVE, s5pv210_pdma0_pdata.cap_mask); 122 dma_cap_set(DMA_SLAVE, s5pv210_pdma0_pdata.cap_mask);
149 dma_cap_set(DMA_CYCLIC, s5pv210_pdma0_pdata.cap_mask); 123 dma_cap_set(DMA_CYCLIC, s5pv210_pdma0_pdata.cap_mask);
150 amba_device_register(&s5pv210_device_pdma0, &iomem_resource); 124 amba_device_register(&s5pv210_pdma0_device, &iomem_resource);
151 125
152 dma_cap_set(DMA_SLAVE, s5pv210_pdma1_pdata.cap_mask); 126 dma_cap_set(DMA_SLAVE, s5pv210_pdma1_pdata.cap_mask);
153 dma_cap_set(DMA_CYCLIC, s5pv210_pdma1_pdata.cap_mask); 127 dma_cap_set(DMA_CYCLIC, s5pv210_pdma1_pdata.cap_mask);
154 amba_device_register(&s5pv210_device_pdma1, &iomem_resource); 128 amba_device_register(&s5pv210_pdma1_device, &iomem_resource);
155 129
156 return 0; 130 return 0;
157} 131}
diff --git a/arch/arm/mach-s5pv210/include/mach/system.h b/arch/arm/mach-s5pv210/include/mach/system.h
deleted file mode 100644
index bf288ced860a..000000000000
--- a/arch/arm/mach-s5pv210/include/mach/system.h
+++ /dev/null
@@ -1,21 +0,0 @@
1/* linux/arch/arm/mach-s5pv210/include/mach/system.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5PV210 - system support header
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_SYSTEM_H
14#define __ASM_ARCH_SYSTEM_H __FILE__
15
16static void arch_idle(void)
17{
18 /* nothing here yet */
19}
20
21#endif /* __ASM_ARCH_SYSTEM_H */
diff --git a/arch/arm/mach-sa1100/include/mach/system.h b/arch/arm/mach-sa1100/include/mach/system.h
deleted file mode 100644
index e17b208f76d4..000000000000
--- a/arch/arm/mach-sa1100/include/mach/system.h
+++ /dev/null
@@ -1,9 +0,0 @@
1/*
2 * arch/arm/mach-sa1100/include/mach/system.h
3 *
4 * Copyright (c) 1999 Nicolas Pitre <nico@fluxnic.net>
5 */
6static inline void arch_idle(void)
7{
8 cpu_do_idle();
9}
diff --git a/arch/arm/mach-shark/core.c b/arch/arm/mach-shark/core.c
index a851c254ad6c..6a2a7f2c2557 100644
--- a/arch/arm/mach-shark/core.c
+++ b/arch/arm/mach-shark/core.c
@@ -149,10 +149,16 @@ static struct sys_timer shark_timer = {
149 .init = shark_timer_init, 149 .init = shark_timer_init,
150}; 150};
151 151
152static void shark_init_early(void)
153{
154 disable_hlt();
155}
156
152MACHINE_START(SHARK, "Shark") 157MACHINE_START(SHARK, "Shark")
153 /* Maintainer: Alexander Schulz */ 158 /* Maintainer: Alexander Schulz */
154 .atag_offset = 0x3000, 159 .atag_offset = 0x3000,
155 .map_io = shark_map_io, 160 .map_io = shark_map_io,
161 .init_early = shark_init_early,
156 .init_irq = shark_init_irq, 162 .init_irq = shark_init_irq,
157 .timer = &shark_timer, 163 .timer = &shark_timer,
158 .dma_zone_size = SZ_4M, 164 .dma_zone_size = SZ_4M,
diff --git a/arch/arm/mach-shark/include/mach/system.h b/arch/arm/mach-shark/include/mach/system.h
deleted file mode 100644
index 1b2f2c5050a8..000000000000
--- a/arch/arm/mach-shark/include/mach/system.h
+++ /dev/null
@@ -1,13 +0,0 @@
1/*
2 * arch/arm/mach-shark/include/mach/system.h
3 *
4 * by Alexander Schulz
5 */
6#ifndef __ASM_ARCH_SYSTEM_H
7#define __ASM_ARCH_SYSTEM_H
8
9static inline void arch_idle(void)
10{
11}
12
13#endif
diff --git a/arch/arm/mach-shmobile/include/mach/system.h b/arch/arm/mach-shmobile/include/mach/system.h
index 956ac18ddbf9..3bbcb3fa0775 100644
--- a/arch/arm/mach-shmobile/include/mach/system.h
+++ b/arch/arm/mach-shmobile/include/mach/system.h
@@ -1,11 +1,6 @@
1#ifndef __ASM_ARCH_SYSTEM_H 1#ifndef __ASM_ARCH_SYSTEM_H
2#define __ASM_ARCH_SYSTEM_H 2#define __ASM_ARCH_SYSTEM_H
3 3
4static inline void arch_idle(void)
5{
6 cpu_do_idle();
7}
8
9static inline void arch_reset(char mode, const char *cmd) 4static inline void arch_reset(char mode, const char *cmd)
10{ 5{
11 soft_restart(0); 6 soft_restart(0);
diff --git a/arch/arm/mach-spear3xx/include/mach/system.h b/arch/arm/mach-spear3xx/include/mach/system.h
deleted file mode 100644
index 92cee6335c90..000000000000
--- a/arch/arm/mach-spear3xx/include/mach/system.h
+++ /dev/null
@@ -1,19 +0,0 @@
1/*
2 * arch/arm/mach-spear3xx/include/mach/system.h
3 *
4 * SPEAr3xx Machine family specific architecture functions
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifndef __MACH_SYSTEM_H
15#define __MACH_SYSTEM_H
16
17#include <plat/system.h>
18
19#endif /* __MACH_SYSTEM_H */
diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c
index a5e46b4ade20..9da50e281e98 100644
--- a/arch/arm/mach-spear3xx/spear300.c
+++ b/arch/arm/mach-spear3xx/spear300.c
@@ -430,18 +430,8 @@ static struct pl061_platform_data gpio1_plat_data = {
430 .irq_base = SPEAR300_GPIO1_INT_BASE, 430 .irq_base = SPEAR300_GPIO1_INT_BASE,
431}; 431};
432 432
433struct amba_device spear300_gpio1_device = { 433AMBA_APB_DEVICE(spear300_gpio1, "gpio1", 0, SPEAR300_GPIO_BASE,
434 .dev = { 434 {SPEAR300_VIRQ_GPIO1}, &gpio1_plat_data);
435 .init_name = "gpio1",
436 .platform_data = &gpio1_plat_data,
437 },
438 .res = {
439 .start = SPEAR300_GPIO_BASE,
440 .end = SPEAR300_GPIO_BASE + SZ_4K - 1,
441 .flags = IORESOURCE_MEM,
442 },
443 .irq = {SPEAR300_VIRQ_GPIO1, NO_IRQ},
444};
445 435
446/* spear300 routines */ 436/* spear300 routines */
447void __init spear300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs, 437void __init spear300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index 10af45da86a0..b1733c37f209 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -28,31 +28,12 @@ static struct pl061_platform_data gpio_plat_data = {
28 .irq_base = SPEAR3XX_GPIO_INT_BASE, 28 .irq_base = SPEAR3XX_GPIO_INT_BASE,
29}; 29};
30 30
31struct amba_device spear3xx_gpio_device = { 31AMBA_APB_DEVICE(spear3xx_gpio, "gpio", 0, SPEAR3XX_ICM3_GPIO_BASE,
32 .dev = { 32 {SPEAR3XX_IRQ_BASIC_GPIO}, &gpio_plat_data);
33 .init_name = "gpio",
34 .platform_data = &gpio_plat_data,
35 },
36 .res = {
37 .start = SPEAR3XX_ICM3_GPIO_BASE,
38 .end = SPEAR3XX_ICM3_GPIO_BASE + SZ_4K - 1,
39 .flags = IORESOURCE_MEM,
40 },
41 .irq = {SPEAR3XX_IRQ_BASIC_GPIO, NO_IRQ},
42};
43 33
44/* uart device registration */ 34/* uart device registration */
45struct amba_device spear3xx_uart_device = { 35AMBA_APB_DEVICE(spear3xx_uart, "uart", 0, SPEAR3XX_ICM1_UART_BASE,
46 .dev = { 36 {SPEAR3XX_IRQ_UART}, NULL);
47 .init_name = "uart",
48 },
49 .res = {
50 .start = SPEAR3XX_ICM1_UART_BASE,
51 .end = SPEAR3XX_ICM1_UART_BASE + SZ_4K - 1,
52 .flags = IORESOURCE_MEM,
53 },
54 .irq = {SPEAR3XX_IRQ_UART, NO_IRQ},
55};
56 37
57/* Do spear3xx familiy common initialization part here */ 38/* Do spear3xx familiy common initialization part here */
58void __init spear3xx_init(void) 39void __init spear3xx_init(void)
diff --git a/arch/arm/mach-spear6xx/include/mach/system.h b/arch/arm/mach-spear6xx/include/mach/system.h
deleted file mode 100644
index 0b1d2be81cfb..000000000000
--- a/arch/arm/mach-spear6xx/include/mach/system.h
+++ /dev/null
@@ -1,19 +0,0 @@
1/*
2 * arch/arm/mach-spear6xx/include/mach/system.h
3 *
4 * SPEAr6xx Machine family specific architecture functions
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Rajeev Kumar<rajeev-dlh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifndef __MACH_SYSTEM_H
15#define __MACH_SYSTEM_H
16
17#include <plat/system.h>
18
19#endif /* __MACH_SYSTEM_H */
diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear6xx/spear6xx.c
index e0f6628c8b2c..b997b1b10ba0 100644
--- a/arch/arm/mach-spear6xx/spear6xx.c
+++ b/arch/arm/mach-spear6xx/spear6xx.c
@@ -34,7 +34,7 @@ struct amba_device uart_device[] = {
34 .end = SPEAR6XX_ICM1_UART0_BASE + SZ_4K - 1, 34 .end = SPEAR6XX_ICM1_UART0_BASE + SZ_4K - 1,
35 .flags = IORESOURCE_MEM, 35 .flags = IORESOURCE_MEM,
36 }, 36 },
37 .irq = {IRQ_UART_0, NO_IRQ}, 37 .irq = {IRQ_UART_0},
38 }, { 38 }, {
39 .dev = { 39 .dev = {
40 .init_name = "uart1", 40 .init_name = "uart1",
@@ -44,7 +44,7 @@ struct amba_device uart_device[] = {
44 .end = SPEAR6XX_ICM1_UART1_BASE + SZ_4K - 1, 44 .end = SPEAR6XX_ICM1_UART1_BASE + SZ_4K - 1,
45 .flags = IORESOURCE_MEM, 45 .flags = IORESOURCE_MEM,
46 }, 46 },
47 .irq = {IRQ_UART_1, NO_IRQ}, 47 .irq = {IRQ_UART_1},
48 } 48 }
49}; 49};
50 50
@@ -73,7 +73,7 @@ struct amba_device gpio_device[] = {
73 .end = SPEAR6XX_CPU_GPIO_BASE + SZ_4K - 1, 73 .end = SPEAR6XX_CPU_GPIO_BASE + SZ_4K - 1,
74 .flags = IORESOURCE_MEM, 74 .flags = IORESOURCE_MEM,
75 }, 75 },
76 .irq = {IRQ_LOCAL_GPIO, NO_IRQ}, 76 .irq = {IRQ_LOCAL_GPIO},
77 }, { 77 }, {
78 .dev = { 78 .dev = {
79 .init_name = "gpio1", 79 .init_name = "gpio1",
@@ -84,7 +84,7 @@ struct amba_device gpio_device[] = {
84 .end = SPEAR6XX_ICM3_GPIO_BASE + SZ_4K - 1, 84 .end = SPEAR6XX_ICM3_GPIO_BASE + SZ_4K - 1,
85 .flags = IORESOURCE_MEM, 85 .flags = IORESOURCE_MEM,
86 }, 86 },
87 .irq = {IRQ_BASIC_GPIO, NO_IRQ}, 87 .irq = {IRQ_BASIC_GPIO},
88 }, { 88 }, {
89 .dev = { 89 .dev = {
90 .init_name = "gpio2", 90 .init_name = "gpio2",
@@ -95,7 +95,7 @@ struct amba_device gpio_device[] = {
95 .end = SPEAR6XX_ICM2_GPIO_BASE + SZ_4K - 1, 95 .end = SPEAR6XX_ICM2_GPIO_BASE + SZ_4K - 1,
96 .flags = IORESOURCE_MEM, 96 .flags = IORESOURCE_MEM,
97 }, 97 },
98 .irq = {IRQ_APPL_GPIO, NO_IRQ}, 98 .irq = {IRQ_APPL_GPIO},
99 } 99 }
100}; 100};
101 101
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index a2eb90169aed..2db20da1d585 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -27,7 +27,6 @@
27#include <asm/hardware/gic.h> 27#include <asm/hardware/gic.h>
28 28
29#include <mach/iomap.h> 29#include <mach/iomap.h>
30#include <mach/system.h>
31 30
32#include "board.h" 31#include "board.h"
33#include "clock.h" 32#include "clock.h"
@@ -96,6 +95,8 @@ static void __init tegra_init_cache(u32 tag_latency, u32 data_latency)
96#ifdef CONFIG_ARCH_TEGRA_2x_SOC 95#ifdef CONFIG_ARCH_TEGRA_2x_SOC
97void __init tegra20_init_early(void) 96void __init tegra20_init_early(void)
98{ 97{
98 disable_hlt(); /* idle WFI usage needs to be confirmed */
99
99 tegra_init_fuse(); 100 tegra_init_fuse();
100 tegra2_init_clocks(); 101 tegra2_init_clocks();
101 tegra_clk_init_from_table(tegra20_clk_init_table); 102 tegra_clk_init_from_table(tegra20_clk_init_table);
diff --git a/arch/arm/mach-tegra/include/mach/system.h b/arch/arm/mach-tegra/include/mach/system.h
deleted file mode 100644
index a312988bf6f8..000000000000
--- a/arch/arm/mach-tegra/include/mach/system.h
+++ /dev/null
@@ -1,28 +0,0 @@
1/*
2 * arch/arm/mach-tegra/include/mach/system.h
3 *
4 * Copyright (C) 2010 Google, Inc.
5 *
6 * Author:
7 * Colin Cross <ccross@google.com>
8 * Erik Gilling <konkers@google.com>
9 *
10 * This software is licensed under the terms of the GNU General Public
11 * License version 2, as published by the Free Software Foundation, and
12 * may be copied, distributed, and modified under those terms.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 */
20
21#ifndef __MACH_TEGRA_SYSTEM_H
22#define __MACH_TEGRA_SYSTEM_H
23
24static inline void arch_idle(void)
25{
26}
27
28#endif
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index b4c6926a700c..b9865605da09 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -94,19 +94,9 @@ static struct amba_pl011_data uart0_plat_data = {
94#endif 94#endif
95}; 95};
96 96
97static struct amba_device uart0_device = { 97/* Slow device at 0x3000 offset */
98 .dev = { 98static AMBA_APB_DEVICE(uart0, "uart0", 0, U300_UART0_BASE,
99 .coherent_dma_mask = ~0, 99 { IRQ_U300_UART0 }, &uart0_plat_data);
100 .init_name = "uart0", /* Slow device at 0x3000 offset */
101 .platform_data = &uart0_plat_data,
102 },
103 .res = {
104 .start = U300_UART0_BASE,
105 .end = U300_UART0_BASE + SZ_4K - 1,
106 .flags = IORESOURCE_MEM,
107 },
108 .irq = { IRQ_U300_UART0, NO_IRQ },
109};
110 100
111/* The U335 have an additional UART1 on the APP CPU */ 101/* The U335 have an additional UART1 on the APP CPU */
112#ifdef CONFIG_MACH_U300_BS335 102#ifdef CONFIG_MACH_U300_BS335
@@ -118,71 +108,28 @@ static struct amba_pl011_data uart1_plat_data = {
118#endif 108#endif
119}; 109};
120 110
121static struct amba_device uart1_device = { 111/* Fast device at 0x7000 offset */
122 .dev = { 112static AMBA_APB_DEVICE(uart1, "uart1", 0, U300_UART1_BASE,
123 .coherent_dma_mask = ~0, 113 { IRQ_U300_UART1 }, &uart1_plat_data);
124 .init_name = "uart1", /* Fast device at 0x7000 offset */
125 .platform_data = &uart1_plat_data,
126 },
127 .res = {
128 .start = U300_UART1_BASE,
129 .end = U300_UART1_BASE + SZ_4K - 1,
130 .flags = IORESOURCE_MEM,
131 },
132 .irq = { IRQ_U300_UART1, NO_IRQ },
133};
134#endif 114#endif
135 115
136static struct amba_device pl172_device = { 116/* AHB device at 0x4000 offset */
137 .dev = { 117static AMBA_APB_DEVICE(pl172, "pl172", 0, U300_EMIF_CFG_BASE, { }, NULL);
138 .init_name = "pl172", /* AHB device at 0x4000 offset */
139 .platform_data = NULL,
140 },
141 .res = {
142 .start = U300_EMIF_CFG_BASE,
143 .end = U300_EMIF_CFG_BASE + SZ_4K - 1,
144 .flags = IORESOURCE_MEM,
145 },
146};
147 118
148 119
149/* 120/*
150 * Everything within this next ifdef deals with external devices connected to 121 * Everything within this next ifdef deals with external devices connected to
151 * the APP SPI bus. 122 * the APP SPI bus.
152 */ 123 */
153static struct amba_device pl022_device = { 124/* Fast device at 0x6000 offset */
154 .dev = { 125static AMBA_APB_DEVICE(pl022, "pl022", 0, U300_SPI_BASE,
155 .coherent_dma_mask = ~0, 126 { IRQ_U300_SPI }, NULL);
156 .init_name = "pl022", /* Fast device at 0x6000 offset */
157 },
158 .res = {
159 .start = U300_SPI_BASE,
160 .end = U300_SPI_BASE + SZ_4K - 1,
161 .flags = IORESOURCE_MEM,
162 },
163 .irq = {IRQ_U300_SPI, NO_IRQ },
164 /*
165 * This device has a DMA channel but the Linux driver does not use
166 * it currently.
167 */
168};
169 127
170static struct amba_device mmcsd_device = { 128/* Fast device at 0x1000 offset */
171 .dev = { 129#define U300_MMCSD_IRQS { IRQ_U300_MMCSD_MCIINTR0, IRQ_U300_MMCSD_MCIINTR1 }
172 .init_name = "mmci", /* Fast device at 0x1000 offset */ 130
173 .platform_data = NULL, /* Added later */ 131static AMBA_APB_DEVICE(mmcsd, "mmci", 0, U300_MMCSD_BASE,
174 }, 132 U300_MMCSD_IRQS, NULL);
175 .res = {
176 .start = U300_MMCSD_BASE,
177 .end = U300_MMCSD_BASE + SZ_4K - 1,
178 .flags = IORESOURCE_MEM,
179 },
180 .irq = {IRQ_U300_MMCSD_MCIINTR0, IRQ_U300_MMCSD_MCIINTR1 },
181 /*
182 * This device has a DMA channel but the Linux driver does not use
183 * it currently.
184 */
185};
186 133
187/* 134/*
188 * The order of device declaration may be important, since some devices 135 * The order of device declaration may be important, since some devices
diff --git a/arch/arm/mach-u300/include/mach/system.h b/arch/arm/mach-u300/include/mach/system.h
deleted file mode 100644
index 574d46e38290..000000000000
--- a/arch/arm/mach-u300/include/mach/system.h
+++ /dev/null
@@ -1,14 +0,0 @@
1/*
2 *
3 * arch/arm/mach-u300/include/mach/system.h
4 *
5 *
6 * Copyright (C) 2007-2009 ST-Ericsson AB
7 * License terms: GNU General Public License (GPL) version 2
8 * System shutdown and reset functions.
9 * Author: Linus Walleij <linus.walleij@stericsson.com>
10 */
11static inline void arch_idle(void)
12{
13 cpu_do_idle();
14}
diff --git a/arch/arm/mach-ux500/devices-common.c b/arch/arm/mach-ux500/devices-common.c
index c563e5418d80..898a64517b09 100644
--- a/arch/arm/mach-ux500/devices-common.c
+++ b/arch/arm/mach-ux500/devices-common.c
@@ -26,29 +26,22 @@ dbx500_add_amba_device(const char *name, resource_size_t base,
26 struct amba_device *dev; 26 struct amba_device *dev;
27 int ret; 27 int ret;
28 28
29 dev = kzalloc(sizeof *dev, GFP_KERNEL); 29 dev = amba_device_alloc(name, base, SZ_4K);
30 if (!dev) 30 if (!dev)
31 return ERR_PTR(-ENOMEM); 31 return ERR_PTR(-ENOMEM);
32 32
33 dev->dev.init_name = name;
34
35 dev->res.start = base;
36 dev->res.end = base + SZ_4K - 1;
37 dev->res.flags = IORESOURCE_MEM;
38
39 dev->dma_mask = DMA_BIT_MASK(32); 33 dev->dma_mask = DMA_BIT_MASK(32);
40 dev->dev.coherent_dma_mask = DMA_BIT_MASK(32); 34 dev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
41 35
42 dev->irq[0] = irq; 36 dev->irq[0] = irq;
43 dev->irq[1] = NO_IRQ;
44 37
45 dev->periphid = periphid; 38 dev->periphid = periphid;
46 39
47 dev->dev.platform_data = pdata; 40 dev->dev.platform_data = pdata;
48 41
49 ret = amba_device_register(dev, &iomem_resource); 42 ret = amba_device_add(dev, &iomem_resource);
50 if (ret) { 43 if (ret) {
51 kfree(dev); 44 amba_device_put(dev);
52 return ERR_PTR(ret); 45 return ERR_PTR(ret);
53 } 46 }
54 47
diff --git a/arch/arm/mach-ux500/include/mach/system.h b/arch/arm/mach-ux500/include/mach/system.h
deleted file mode 100644
index 258e5c919c24..000000000000
--- a/arch/arm/mach-ux500/include/mach/system.h
+++ /dev/null
@@ -1,20 +0,0 @@
1/*
2 * Copyright (C) 2009 ST-Ericsson.
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8#ifndef __ASM_ARCH_SYSTEM_H
9#define __ASM_ARCH_SYSTEM_H
10
11static inline void arch_idle(void)
12{
13 /*
14 * This should do all the clock switching
15 * and wait for interrupt tricks
16 */
17 cpu_do_idle();
18}
19
20#endif
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index 02b7b9303f3b..4f352e45be0a 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -582,58 +582,58 @@ static struct pl022_ssp_controller ssp0_plat_data = {
582 .num_chipselect = 1, 582 .num_chipselect = 1,
583}; 583};
584 584
585#define AACI_IRQ { IRQ_AACI, NO_IRQ } 585#define AACI_IRQ { IRQ_AACI }
586#define MMCI0_IRQ { IRQ_MMCI0A,IRQ_SIC_MMCI0B } 586#define MMCI0_IRQ { IRQ_MMCI0A,IRQ_SIC_MMCI0B }
587#define KMI0_IRQ { IRQ_SIC_KMI0, NO_IRQ } 587#define KMI0_IRQ { IRQ_SIC_KMI0 }
588#define KMI1_IRQ { IRQ_SIC_KMI1, NO_IRQ } 588#define KMI1_IRQ { IRQ_SIC_KMI1 }
589 589
590/* 590/*
591 * These devices are connected directly to the multi-layer AHB switch 591 * These devices are connected directly to the multi-layer AHB switch
592 */ 592 */
593#define SMC_IRQ { NO_IRQ, NO_IRQ } 593#define SMC_IRQ { }
594#define MPMC_IRQ { NO_IRQ, NO_IRQ } 594#define MPMC_IRQ { }
595#define CLCD_IRQ { IRQ_CLCDINT, NO_IRQ } 595#define CLCD_IRQ { IRQ_CLCDINT }
596#define DMAC_IRQ { IRQ_DMAINT, NO_IRQ } 596#define DMAC_IRQ { IRQ_DMAINT }
597 597
598/* 598/*
599 * These devices are connected via the core APB bridge 599 * These devices are connected via the core APB bridge
600 */ 600 */
601#define SCTL_IRQ { NO_IRQ, NO_IRQ } 601#define SCTL_IRQ { }
602#define WATCHDOG_IRQ { IRQ_WDOGINT, NO_IRQ } 602#define WATCHDOG_IRQ { IRQ_WDOGINT }
603#define GPIO0_IRQ { IRQ_GPIOINT0, NO_IRQ } 603#define GPIO0_IRQ { IRQ_GPIOINT0 }
604#define GPIO1_IRQ { IRQ_GPIOINT1, NO_IRQ } 604#define GPIO1_IRQ { IRQ_GPIOINT1 }
605#define RTC_IRQ { IRQ_RTCINT, NO_IRQ } 605#define RTC_IRQ { IRQ_RTCINT }
606 606
607/* 607/*
608 * These devices are connected via the DMA APB bridge 608 * These devices are connected via the DMA APB bridge
609 */ 609 */
610#define SCI_IRQ { IRQ_SCIINT, NO_IRQ } 610#define SCI_IRQ { IRQ_SCIINT }
611#define UART0_IRQ { IRQ_UARTINT0, NO_IRQ } 611#define UART0_IRQ { IRQ_UARTINT0 }
612#define UART1_IRQ { IRQ_UARTINT1, NO_IRQ } 612#define UART1_IRQ { IRQ_UARTINT1 }
613#define UART2_IRQ { IRQ_UARTINT2, NO_IRQ } 613#define UART2_IRQ { IRQ_UARTINT2 }
614#define SSP_IRQ { IRQ_SSPINT, NO_IRQ } 614#define SSP_IRQ { IRQ_SSPINT }
615 615
616/* FPGA Primecells */ 616/* FPGA Primecells */
617AMBA_DEVICE(aaci, "fpga:04", AACI, NULL); 617APB_DEVICE(aaci, "fpga:04", AACI, NULL);
618AMBA_DEVICE(mmc0, "fpga:05", MMCI0, &mmc0_plat_data); 618APB_DEVICE(mmc0, "fpga:05", MMCI0, &mmc0_plat_data);
619AMBA_DEVICE(kmi0, "fpga:06", KMI0, NULL); 619APB_DEVICE(kmi0, "fpga:06", KMI0, NULL);
620AMBA_DEVICE(kmi1, "fpga:07", KMI1, NULL); 620APB_DEVICE(kmi1, "fpga:07", KMI1, NULL);
621 621
622/* DevChip Primecells */ 622/* DevChip Primecells */
623AMBA_DEVICE(smc, "dev:00", SMC, NULL); 623AHB_DEVICE(smc, "dev:00", SMC, NULL);
624AMBA_DEVICE(mpmc, "dev:10", MPMC, NULL); 624AHB_DEVICE(mpmc, "dev:10", MPMC, NULL);
625AMBA_DEVICE(clcd, "dev:20", CLCD, &clcd_plat_data); 625AHB_DEVICE(clcd, "dev:20", CLCD, &clcd_plat_data);
626AMBA_DEVICE(dmac, "dev:30", DMAC, NULL); 626AHB_DEVICE(dmac, "dev:30", DMAC, NULL);
627AMBA_DEVICE(sctl, "dev:e0", SCTL, NULL); 627APB_DEVICE(sctl, "dev:e0", SCTL, NULL);
628AMBA_DEVICE(wdog, "dev:e1", WATCHDOG, NULL); 628APB_DEVICE(wdog, "dev:e1", WATCHDOG, NULL);
629AMBA_DEVICE(gpio0, "dev:e4", GPIO0, &gpio0_plat_data); 629APB_DEVICE(gpio0, "dev:e4", GPIO0, &gpio0_plat_data);
630AMBA_DEVICE(gpio1, "dev:e5", GPIO1, &gpio1_plat_data); 630APB_DEVICE(gpio1, "dev:e5", GPIO1, &gpio1_plat_data);
631AMBA_DEVICE(rtc, "dev:e8", RTC, NULL); 631APB_DEVICE(rtc, "dev:e8", RTC, NULL);
632AMBA_DEVICE(sci0, "dev:f0", SCI, NULL); 632APB_DEVICE(sci0, "dev:f0", SCI, NULL);
633AMBA_DEVICE(uart0, "dev:f1", UART0, NULL); 633APB_DEVICE(uart0, "dev:f1", UART0, NULL);
634AMBA_DEVICE(uart1, "dev:f2", UART1, NULL); 634APB_DEVICE(uart1, "dev:f2", UART1, NULL);
635AMBA_DEVICE(uart2, "dev:f3", UART2, NULL); 635APB_DEVICE(uart2, "dev:f3", UART2, NULL);
636AMBA_DEVICE(ssp0, "dev:f4", SSP, &ssp0_plat_data); 636APB_DEVICE(ssp0, "dev:f4", SSP, &ssp0_plat_data);
637 637
638static struct amba_device *amba_devs[] __initdata = { 638static struct amba_device *amba_devs[] __initdata = {
639 &dmac_device, 639 &dmac_device,
diff --git a/arch/arm/mach-versatile/core.h b/arch/arm/mach-versatile/core.h
index 2ef2f555f315..683e60776a85 100644
--- a/arch/arm/mach-versatile/core.h
+++ b/arch/arm/mach-versatile/core.h
@@ -36,20 +36,10 @@ extern unsigned int mmc_status(struct device *dev);
36extern struct of_dev_auxdata versatile_auxdata_lookup[]; 36extern struct of_dev_auxdata versatile_auxdata_lookup[];
37#endif 37#endif
38 38
39#define AMBA_DEVICE(name,busid,base,plat) \ 39#define APB_DEVICE(name, busid, base, plat) \
40static struct amba_device name##_device = { \ 40static AMBA_APB_DEVICE(name, busid, 0, VERSATILE_##base##_BASE, base##_IRQ, plat)
41 .dev = { \ 41
42 .coherent_dma_mask = ~0, \ 42#define AHB_DEVICE(name, busid, base, plat) \
43 .init_name = busid, \ 43static AMBA_AHB_DEVICE(name, busid, 0, VERSATILE_##base##_BASE, base##_IRQ, plat)
44 .platform_data = plat, \
45 }, \
46 .res = { \
47 .start = VERSATILE_##base##_BASE, \
48 .end = (VERSATILE_##base##_BASE) + SZ_4K - 1,\
49 .flags = IORESOURCE_MEM, \
50 }, \
51 .dma_mask = ~0, \
52 .irq = base##_IRQ, \
53}
54 44
55#endif 45#endif
diff --git a/arch/arm/mach-versatile/include/mach/system.h b/arch/arm/mach-versatile/include/mach/system.h
deleted file mode 100644
index f3fa347895f0..000000000000
--- a/arch/arm/mach-versatile/include/mach/system.h
+++ /dev/null
@@ -1,33 +0,0 @@
1/*
2 * arch/arm/mach-versatile/include/mach/system.h
3 *
4 * Copyright (C) 2003 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#ifndef __ASM_ARCH_SYSTEM_H
22#define __ASM_ARCH_SYSTEM_H
23
24static inline void arch_idle(void)
25{
26 /*
27 * This should do all the clock switching
28 * and wait for interrupt tricks
29 */
30 cpu_do_idle();
31}
32
33#endif
diff --git a/arch/arm/mach-versatile/versatile_pb.c b/arch/arm/mach-versatile/versatile_pb.c
index 9581c197500c..19738331bd3d 100644
--- a/arch/arm/mach-versatile/versatile_pb.c
+++ b/arch/arm/mach-versatile/versatile_pb.c
@@ -58,28 +58,28 @@ static struct pl061_platform_data gpio3_plat_data = {
58 .irq_base = IRQ_GPIO3_START, 58 .irq_base = IRQ_GPIO3_START,
59}; 59};
60 60
61#define UART3_IRQ { IRQ_SIC_UART3, NO_IRQ } 61#define UART3_IRQ { IRQ_SIC_UART3 }
62#define SCI1_IRQ { IRQ_SIC_SCI3, NO_IRQ } 62#define SCI1_IRQ { IRQ_SIC_SCI3 }
63#define MMCI1_IRQ { IRQ_MMCI1A, IRQ_SIC_MMCI1B } 63#define MMCI1_IRQ { IRQ_MMCI1A, IRQ_SIC_MMCI1B }
64 64
65/* 65/*
66 * These devices are connected via the core APB bridge 66 * These devices are connected via the core APB bridge
67 */ 67 */
68#define GPIO2_IRQ { IRQ_GPIOINT2, NO_IRQ } 68#define GPIO2_IRQ { IRQ_GPIOINT2 }
69#define GPIO3_IRQ { IRQ_GPIOINT3, NO_IRQ } 69#define GPIO3_IRQ { IRQ_GPIOINT3 }
70 70
71/* 71/*
72 * These devices are connected via the DMA APB bridge 72 * These devices are connected via the DMA APB bridge
73 */ 73 */
74 74
75/* FPGA Primecells */ 75/* FPGA Primecells */
76AMBA_DEVICE(uart3, "fpga:09", UART3, NULL); 76APB_DEVICE(uart3, "fpga:09", UART3, NULL);
77AMBA_DEVICE(sci1, "fpga:0a", SCI1, NULL); 77APB_DEVICE(sci1, "fpga:0a", SCI1, NULL);
78AMBA_DEVICE(mmc1, "fpga:0b", MMCI1, &mmc1_plat_data); 78APB_DEVICE(mmc1, "fpga:0b", MMCI1, &mmc1_plat_data);
79 79
80/* DevChip Primecells */ 80/* DevChip Primecells */
81AMBA_DEVICE(gpio2, "dev:e6", GPIO2, &gpio2_plat_data); 81APB_DEVICE(gpio2, "dev:e6", GPIO2, &gpio2_plat_data);
82AMBA_DEVICE(gpio3, "dev:e7", GPIO3, &gpio3_plat_data); 82APB_DEVICE(gpio3, "dev:e7", GPIO3, &gpio3_plat_data);
83 83
84static struct amba_device *amba_devs[] __initdata = { 84static struct amba_device *amba_devs[] __initdata = {
85 &uart3_device, 85 &uart3_device,
diff --git a/arch/arm/mach-vexpress/core.h b/arch/arm/mach-vexpress/core.h
index f4397159c173..9f0f2827c711 100644
--- a/arch/arm/mach-vexpress/core.h
+++ b/arch/arm/mach-vexpress/core.h
@@ -1,19 +1,2 @@
1#define __MMIO_P2V(x) (((x) & 0xfffff) | (((x) & 0x0f000000) >> 4) | 0xf8000000) 1#define __MMIO_P2V(x) (((x) & 0xfffff) | (((x) & 0x0f000000) >> 4) | 0xf8000000)
2#define MMIO_P2V(x) ((void __iomem *)__MMIO_P2V(x)) 2#define MMIO_P2V(x) ((void __iomem *)__MMIO_P2V(x))
3
4#define AMBA_DEVICE(name,busid,base,plat) \
5struct amba_device name##_device = { \
6 .dev = { \
7 .coherent_dma_mask = ~0UL, \
8 .init_name = busid, \
9 .platform_data = plat, \
10 }, \
11 .res = { \
12 .start = base, \
13 .end = base + SZ_4K - 1, \
14 .flags = IORESOURCE_MEM, \
15 }, \
16 .dma_mask = ~0UL, \
17 .irq = IRQ_##base, \
18 /* .dma = DMA_##base,*/ \
19}
diff --git a/arch/arm/mach-vexpress/ct-ca9x4.c b/arch/arm/mach-vexpress/ct-ca9x4.c
index b1e87c184e54..1b1d2e4892b9 100644
--- a/arch/arm/mach-vexpress/ct-ca9x4.c
+++ b/arch/arm/mach-vexpress/ct-ca9x4.c
@@ -109,10 +109,10 @@ static struct clcd_board ct_ca9x4_clcd_data = {
109 .remove = versatile_clcd_remove_dma, 109 .remove = versatile_clcd_remove_dma,
110}; 110};
111 111
112static AMBA_DEVICE(clcd, "ct:clcd", CT_CA9X4_CLCDC, &ct_ca9x4_clcd_data); 112static AMBA_AHB_DEVICE(clcd, "ct:clcd", 0, CT_CA9X4_CLCDC, IRQ_CT_CA9X4_CLCDC, &ct_ca9x4_clcd_data);
113static AMBA_DEVICE(dmc, "ct:dmc", CT_CA9X4_DMC, NULL); 113static AMBA_APB_DEVICE(dmc, "ct:dmc", 0, CT_CA9X4_DMC, IRQ_CT_CA9X4_DMC, NULL);
114static AMBA_DEVICE(smc, "ct:smc", CT_CA9X4_SMC, NULL); 114static AMBA_APB_DEVICE(smc, "ct:smc", 0, CT_CA9X4_SMC, IRQ_CT_CA9X4_SMC, NULL);
115static AMBA_DEVICE(gpio, "ct:gpio", CT_CA9X4_GPIO, NULL); 115static AMBA_APB_DEVICE(gpio, "ct:gpio", 0, CT_CA9X4_GPIO, IRQ_CT_CA9X4_GPIO, NULL);
116 116
117static struct amba_device *ct_ca9x4_amba_devs[] __initdata = { 117static struct amba_device *ct_ca9x4_amba_devs[] __initdata = {
118 &clcd_device, 118 &clcd_device,
diff --git a/arch/arm/mach-vexpress/include/mach/ct-ca9x4.h b/arch/arm/mach-vexpress/include/mach/ct-ca9x4.h
index a34d3d4faae1..a40468f3b938 100644
--- a/arch/arm/mach-vexpress/include/mach/ct-ca9x4.h
+++ b/arch/arm/mach-vexpress/include/mach/ct-ca9x4.h
@@ -35,7 +35,7 @@
35 * Interrupts. Those in {} are for AMBA devices 35 * Interrupts. Those in {} are for AMBA devices
36 */ 36 */
37#define IRQ_CT_CA9X4_CLCDC { 76 } 37#define IRQ_CT_CA9X4_CLCDC { 76 }
38#define IRQ_CT_CA9X4_DMC { -1 } 38#define IRQ_CT_CA9X4_DMC { 0 }
39#define IRQ_CT_CA9X4_SMC { 77, 78 } 39#define IRQ_CT_CA9X4_SMC { 77, 78 }
40#define IRQ_CT_CA9X4_TIMER0 80 40#define IRQ_CT_CA9X4_TIMER0 80
41#define IRQ_CT_CA9X4_TIMER1 81 41#define IRQ_CT_CA9X4_TIMER1 81
diff --git a/arch/arm/mach-vexpress/include/mach/system.h b/arch/arm/mach-vexpress/include/mach/system.h
deleted file mode 100644
index f653a8e265bd..000000000000
--- a/arch/arm/mach-vexpress/include/mach/system.h
+++ /dev/null
@@ -1,33 +0,0 @@
1/*
2 * arch/arm/mach-vexpress/include/mach/system.h
3 *
4 * Copyright (C) 2003 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#ifndef __ASM_ARCH_SYSTEM_H
22#define __ASM_ARCH_SYSTEM_H
23
24static inline void arch_idle(void)
25{
26 /*
27 * This should do all the clock switching
28 * and wait for interrupt tricks
29 */
30 cpu_do_idle();
31}
32
33#endif
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
index b4a28ca0e50a..ad64f97a2003 100644
--- a/arch/arm/mach-vexpress/v2m.c
+++ b/arch/arm/mach-vexpress/v2m.c
@@ -266,16 +266,16 @@ static struct mmci_platform_data v2m_mmci_data = {
266 .status = v2m_mmci_status, 266 .status = v2m_mmci_status,
267}; 267};
268 268
269static AMBA_DEVICE(aaci, "mb:aaci", V2M_AACI, NULL); 269static AMBA_APB_DEVICE(aaci, "mb:aaci", 0, V2M_AACI, IRQ_V2M_AACI, NULL);
270static AMBA_DEVICE(mmci, "mb:mmci", V2M_MMCI, &v2m_mmci_data); 270static AMBA_APB_DEVICE(mmci, "mb:mmci", 0, V2M_MMCI, IRQ_V2M_MMCI, &v2m_mmci_data);
271static AMBA_DEVICE(kmi0, "mb:kmi0", V2M_KMI0, NULL); 271static AMBA_APB_DEVICE(kmi0, "mb:kmi0", 0, V2M_KMI0, IRQ_V2M_KMI0, NULL);
272static AMBA_DEVICE(kmi1, "mb:kmi1", V2M_KMI1, NULL); 272static AMBA_APB_DEVICE(kmi1, "mb:kmi1", 0, V2M_KMI1, IRQ_V2M_KMI1, NULL);
273static AMBA_DEVICE(uart0, "mb:uart0", V2M_UART0, NULL); 273static AMBA_APB_DEVICE(uart0, "mb:uart0", 0, V2M_UART0, IRQ_V2M_UART0, NULL);
274static AMBA_DEVICE(uart1, "mb:uart1", V2M_UART1, NULL); 274static AMBA_APB_DEVICE(uart1, "mb:uart1", 0, V2M_UART1, IRQ_V2M_UART1, NULL);
275static AMBA_DEVICE(uart2, "mb:uart2", V2M_UART2, NULL); 275static AMBA_APB_DEVICE(uart2, "mb:uart2", 0, V2M_UART2, IRQ_V2M_UART2, NULL);
276static AMBA_DEVICE(uart3, "mb:uart3", V2M_UART3, NULL); 276static AMBA_APB_DEVICE(uart3, "mb:uart3", 0, V2M_UART3, IRQ_V2M_UART3, NULL);
277static AMBA_DEVICE(wdt, "mb:wdt", V2M_WDT, NULL); 277static AMBA_APB_DEVICE(wdt, "mb:wdt", 0, V2M_WDT, IRQ_V2M_WDT, NULL);
278static AMBA_DEVICE(rtc, "mb:rtc", V2M_RTC, NULL); 278static AMBA_APB_DEVICE(rtc, "mb:rtc", 0, V2M_RTC, IRQ_V2M_RTC, NULL);
279 279
280static struct amba_device *v2m_amba_devs[] __initdata = { 280static struct amba_device *v2m_amba_devs[] __initdata = {
281 &aaci_device, 281 &aaci_device,
diff --git a/arch/arm/mach-vt8500/include/mach/system.h b/arch/arm/mach-vt8500/include/mach/system.h
index d6c757eaf26b..58fa8010ee61 100644
--- a/arch/arm/mach-vt8500/include/mach/system.h
+++ b/arch/arm/mach-vt8500/include/mach/system.h
@@ -7,11 +7,6 @@
7/* PM Software Reset request register */ 7/* PM Software Reset request register */
8#define VT8500_PMSR_VIRT 0xf8130060 8#define VT8500_PMSR_VIRT 0xf8130060
9 9
10static inline void arch_idle(void)
11{
12 cpu_do_idle();
13}
14
15static inline void arch_reset(char mode, const char *cmd) 10static inline void arch_reset(char mode, const char *cmd)
16{ 11{
17 writel(1, VT8500_PMSR_VIRT); 12 writel(1, VT8500_PMSR_VIRT);
diff --git a/arch/arm/mach-w90x900/dev.c b/arch/arm/mach-w90x900/dev.c
index 78110befb7a9..db82568a998a 100644
--- a/arch/arm/mach-w90x900/dev.c
+++ b/arch/arm/mach-w90x900/dev.c
@@ -530,6 +530,7 @@ static struct platform_device *nuc900_public_dev[] __initdata = {
530 530
531void __init nuc900_board_init(struct platform_device **device, int size) 531void __init nuc900_board_init(struct platform_device **device, int size)
532{ 532{
533 disable_hlt();
533 platform_add_devices(device, size); 534 platform_add_devices(device, size);
534 platform_add_devices(nuc900_public_dev, ARRAY_SIZE(nuc900_public_dev)); 535 platform_add_devices(nuc900_public_dev, ARRAY_SIZE(nuc900_public_dev));
535 spi_register_board_info(nuc900_spi_board_info, 536 spi_register_board_info(nuc900_spi_board_info,
diff --git a/arch/arm/mach-w90x900/include/mach/system.h b/arch/arm/mach-w90x900/include/mach/system.h
deleted file mode 100644
index 2aaeb9311619..000000000000
--- a/arch/arm/mach-w90x900/include/mach/system.h
+++ /dev/null
@@ -1,19 +0,0 @@
1/*
2 * arch/arm/mach-w90x900/include/mach/system.h
3 *
4 * Copyright (c) 2008 Nuvoton technology corporation
5 * All rights reserved.
6 *
7 * Wan ZongShun <mcuos.com@gmail.com>
8 *
9 * Based on arch/arm/mach-s3c2410/include/mach/system.h
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 */
17static void arch_idle(void)
18{
19}
diff --git a/arch/arm/mach-zynq/include/mach/system.h b/arch/arm/mach-zynq/include/mach/system.h
deleted file mode 100644
index 8e88e0b8d2ba..000000000000
--- a/arch/arm/mach-zynq/include/mach/system.h
+++ /dev/null
@@ -1,23 +0,0 @@
1/* arch/arm/mach-zynq/include/mach/system.h
2 *
3 * Copyright (C) 2011 Xilinx
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#ifndef __MACH_SYSTEM_H__
16#define __MACH_SYSTEM_H__
17
18static inline void arch_idle(void)
19{
20 cpu_do_idle();
21}
22
23#endif
diff --git a/arch/arm/plat-mxc/audmux-v2.c b/arch/arm/plat-mxc/audmux-v2.c
index 8cced35009bd..0e51fc36b5be 100644
--- a/arch/arm/plat-mxc/audmux-v2.c
+++ b/arch/arm/plat-mxc/audmux-v2.c
@@ -73,13 +73,13 @@ static ssize_t audmux_read_file(struct file *file, char __user *user_buf,
73 return -ENOMEM; 73 return -ENOMEM;
74 74
75 if (audmux_clk) 75 if (audmux_clk)
76 clk_enable(audmux_clk); 76 clk_prepare_enable(audmux_clk);
77 77
78 ptcr = readl(audmux_base + MXC_AUDMUX_V2_PTCR(port)); 78 ptcr = readl(audmux_base + MXC_AUDMUX_V2_PTCR(port));
79 pdcr = readl(audmux_base + MXC_AUDMUX_V2_PDCR(port)); 79 pdcr = readl(audmux_base + MXC_AUDMUX_V2_PDCR(port));
80 80
81 if (audmux_clk) 81 if (audmux_clk)
82 clk_disable(audmux_clk); 82 clk_disable_unprepare(audmux_clk);
83 83
84 ret = snprintf(buf, PAGE_SIZE, "PDCR: %08x\nPTCR: %08x\n", 84 ret = snprintf(buf, PAGE_SIZE, "PDCR: %08x\nPTCR: %08x\n",
85 pdcr, ptcr); 85 pdcr, ptcr);
@@ -172,13 +172,13 @@ int mxc_audmux_v2_configure_port(unsigned int port, unsigned int ptcr,
172 return -ENOSYS; 172 return -ENOSYS;
173 173
174 if (audmux_clk) 174 if (audmux_clk)
175 clk_enable(audmux_clk); 175 clk_prepare_enable(audmux_clk);
176 176
177 writel(ptcr, audmux_base + MXC_AUDMUX_V2_PTCR(port)); 177 writel(ptcr, audmux_base + MXC_AUDMUX_V2_PTCR(port));
178 writel(pdcr, audmux_base + MXC_AUDMUX_V2_PDCR(port)); 178 writel(pdcr, audmux_base + MXC_AUDMUX_V2_PDCR(port));
179 179
180 if (audmux_clk) 180 if (audmux_clk)
181 clk_disable(audmux_clk); 181 clk_disable_unprepare(audmux_clk);
182 182
183 return 0; 183 return 0;
184} 184}
diff --git a/arch/arm/plat-mxc/devices/platform-ahci-imx.c b/arch/arm/plat-mxc/devices/platform-ahci-imx.c
index d8a56aee521b..ade4a1c4e2a3 100644
--- a/arch/arm/plat-mxc/devices/platform-ahci-imx.c
+++ b/arch/arm/plat-mxc/devices/platform-ahci-imx.c
@@ -60,9 +60,9 @@ static int imx_sata_init(struct device *dev, void __iomem *addr)
60 dev_err(dev, "no sata clock.\n"); 60 dev_err(dev, "no sata clock.\n");
61 return PTR_ERR(sata_clk); 61 return PTR_ERR(sata_clk);
62 } 62 }
63 ret = clk_enable(sata_clk); 63 ret = clk_prepare_enable(sata_clk);
64 if (ret) { 64 if (ret) {
65 dev_err(dev, "can't enable sata clock.\n"); 65 dev_err(dev, "can't prepare/enable sata clock.\n");
66 goto put_sata_clk; 66 goto put_sata_clk;
67 } 67 }
68 68
@@ -73,9 +73,9 @@ static int imx_sata_init(struct device *dev, void __iomem *addr)
73 ret = PTR_ERR(sata_ref_clk); 73 ret = PTR_ERR(sata_ref_clk);
74 goto release_sata_clk; 74 goto release_sata_clk;
75 } 75 }
76 ret = clk_enable(sata_ref_clk); 76 ret = clk_prepare_enable(sata_ref_clk);
77 if (ret) { 77 if (ret) {
78 dev_err(dev, "can't enable sata ref clock.\n"); 78 dev_err(dev, "can't prepare/enable sata ref clock.\n");
79 goto put_sata_ref_clk; 79 goto put_sata_ref_clk;
80 } 80 }
81 81
@@ -104,11 +104,11 @@ static int imx_sata_init(struct device *dev, void __iomem *addr)
104 return 0; 104 return 0;
105 105
106release_sata_ref_clk: 106release_sata_ref_clk:
107 clk_disable(sata_ref_clk); 107 clk_disable_unprepare(sata_ref_clk);
108put_sata_ref_clk: 108put_sata_ref_clk:
109 clk_put(sata_ref_clk); 109 clk_put(sata_ref_clk);
110release_sata_clk: 110release_sata_clk:
111 clk_disable(sata_clk); 111 clk_disable_unprepare(sata_clk);
112put_sata_clk: 112put_sata_clk:
113 clk_put(sata_clk); 113 clk_put(sata_clk);
114 114
@@ -117,10 +117,10 @@ put_sata_clk:
117 117
118static void imx_sata_exit(struct device *dev) 118static void imx_sata_exit(struct device *dev)
119{ 119{
120 clk_disable(sata_ref_clk); 120 clk_disable_unprepare(sata_ref_clk);
121 clk_put(sata_ref_clk); 121 clk_put(sata_ref_clk);
122 122
123 clk_disable(sata_clk); 123 clk_disable_unprepare(sata_clk);
124 clk_put(sata_clk); 124 clk_put(sata_clk);
125 125
126} 126}
diff --git a/arch/arm/plat-mxc/epit.c b/arch/arm/plat-mxc/epit.c
index d3467f818c33..9129c9e7d532 100644
--- a/arch/arm/plat-mxc/epit.c
+++ b/arch/arm/plat-mxc/epit.c
@@ -203,7 +203,7 @@ static int __init epit_clockevent_init(struct clk *timer_clk)
203 203
204void __init epit_timer_init(struct clk *timer_clk, void __iomem *base, int irq) 204void __init epit_timer_init(struct clk *timer_clk, void __iomem *base, int irq)
205{ 205{
206 clk_enable(timer_clk); 206 clk_prepare_enable(timer_clk);
207 207
208 timer_base = base; 208 timer_base = base;
209 209
diff --git a/arch/arm/plat-mxc/include/mach/system.h b/arch/arm/plat-mxc/include/mach/system.h
deleted file mode 100644
index 13ad0df2e860..000000000000
--- a/arch/arm/plat-mxc/include/mach/system.h
+++ /dev/null
@@ -1,25 +0,0 @@
1/*
2 * Copyright (C) 1999 ARM Limited
3 * Copyright (C) 2000 Deep Blue Solutions Ltd
4 * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#ifndef __ASM_ARCH_MXC_SYSTEM_H__
18#define __ASM_ARCH_MXC_SYSTEM_H__
19
20static inline void arch_idle(void)
21{
22 cpu_do_idle();
23}
24
25#endif /* __ASM_ARCH_MXC_SYSTEM_H__ */
diff --git a/arch/arm/plat-mxc/pwm.c b/arch/arm/plat-mxc/pwm.c
index e032717f7d02..c0cab2270dd1 100644
--- a/arch/arm/plat-mxc/pwm.c
+++ b/arch/arm/plat-mxc/pwm.c
@@ -132,7 +132,7 @@ int pwm_enable(struct pwm_device *pwm)
132 int rc = 0; 132 int rc = 0;
133 133
134 if (!pwm->clk_enabled) { 134 if (!pwm->clk_enabled) {
135 rc = clk_enable(pwm->clk); 135 rc = clk_prepare_enable(pwm->clk);
136 if (!rc) 136 if (!rc)
137 pwm->clk_enabled = 1; 137 pwm->clk_enabled = 1;
138 } 138 }
@@ -145,7 +145,7 @@ void pwm_disable(struct pwm_device *pwm)
145 writel(0, pwm->mmio_base + MX3_PWMCR); 145 writel(0, pwm->mmio_base + MX3_PWMCR);
146 146
147 if (pwm->clk_enabled) { 147 if (pwm->clk_enabled) {
148 clk_disable(pwm->clk); 148 clk_disable_unprepare(pwm->clk);
149 pwm->clk_enabled = 0; 149 pwm->clk_enabled = 0;
150 } 150 }
151} 151}
diff --git a/arch/arm/plat-mxc/system.c b/arch/arm/plat-mxc/system.c
index 3599bf2cfd4f..f30dcacbbd0a 100644
--- a/arch/arm/plat-mxc/system.c
+++ b/arch/arm/plat-mxc/system.c
@@ -48,7 +48,7 @@ void mxc_restart(char mode, const char *cmd)
48 48
49 clk = clk_get_sys("imx2-wdt.0", NULL); 49 clk = clk_get_sys("imx2-wdt.0", NULL);
50 if (!IS_ERR(clk)) 50 if (!IS_ERR(clk))
51 clk_enable(clk); 51 clk_prepare_enable(clk);
52 wcr_enable = (1 << 2); 52 wcr_enable = (1 << 2);
53 } 53 }
54 54
diff --git a/arch/arm/plat-mxc/time.c b/arch/arm/plat-mxc/time.c
index 1c96cdb4c35e..7daf7c9a413b 100644
--- a/arch/arm/plat-mxc/time.c
+++ b/arch/arm/plat-mxc/time.c
@@ -283,7 +283,7 @@ void __init mxc_timer_init(struct clk *timer_clk, void __iomem *base, int irq)
283{ 283{
284 uint32_t tctl_val; 284 uint32_t tctl_val;
285 285
286 clk_enable(timer_clk); 286 clk_prepare_enable(timer_clk);
287 287
288 timer_base = base; 288 timer_base = base;
289 289
diff --git a/arch/arm/plat-omap/include/plat/system.h b/arch/arm/plat-omap/include/plat/system.h
deleted file mode 100644
index 8e5ebd74b129..000000000000
--- a/arch/arm/plat-omap/include/plat/system.h
+++ /dev/null
@@ -1,15 +0,0 @@
1/*
2 * Copied from arch/arm/mach-sa1100/include/mach/system.h
3 * Copyright (c) 1999 Nicolas Pitre <nico@fluxnic.net>
4 */
5#ifndef __ASM_ARCH_SYSTEM_H
6#define __ASM_ARCH_SYSTEM_H
7
8#include <asm/proc-fns.h>
9
10static inline void arch_idle(void)
11{
12 cpu_do_idle();
13}
14
15#endif
diff --git a/arch/arm/plat-s3c24xx/cpu.c b/arch/arm/plat-s3c24xx/cpu.c
index 21f1fda8b661..32a09931350c 100644
--- a/arch/arm/plat-s3c24xx/cpu.c
+++ b/arch/arm/plat-s3c24xx/cpu.c
@@ -32,6 +32,7 @@
32#include <linux/io.h> 32#include <linux/io.h>
33 33
34#include <mach/hardware.h> 34#include <mach/hardware.h>
35#include <mach/regs-clock.h>
35#include <asm/irq.h> 36#include <asm/irq.h>
36#include <asm/cacheflush.h> 37#include <asm/cacheflush.h>
37 38
@@ -190,8 +191,34 @@ static unsigned long s3c24xx_read_idcode_v4(void)
190 return __raw_readl(S3C2410_GSTATUS1); 191 return __raw_readl(S3C2410_GSTATUS1);
191} 192}
192 193
194static void s3c24xx_default_idle(void)
195{
196 unsigned long tmp;
197 int i;
198
199 /* idle the system by using the idle mode which will wait for an
200 * interrupt to happen before restarting the system.
201 */
202
203 /* Warning: going into idle state upsets jtag scanning */
204
205 __raw_writel(__raw_readl(S3C2410_CLKCON) | S3C2410_CLKCON_IDLE,
206 S3C2410_CLKCON);
207
208 /* the samsung port seems to do a loop and then unset idle.. */
209 for (i = 0; i < 50; i++)
210 tmp += __raw_readl(S3C2410_CLKCON); /* ensure loop not optimised out */
211
212 /* this bit is not cleared on re-start... */
213
214 __raw_writel(__raw_readl(S3C2410_CLKCON) & ~S3C2410_CLKCON_IDLE,
215 S3C2410_CLKCON);
216}
217
193void __init s3c24xx_init_io(struct map_desc *mach_desc, int size) 218void __init s3c24xx_init_io(struct map_desc *mach_desc, int size)
194{ 219{
220 arm_pm_idle = s3c24xx_default_idle;
221
195 /* initialise the io descriptors we need for initialisation */ 222 /* initialise the io descriptors we need for initialisation */
196 iotable_init(mach_desc, size); 223 iotable_init(mach_desc, size);
197 iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc)); 224 iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
diff --git a/arch/arm/plat-spear/include/plat/system.h b/arch/arm/plat-spear/include/plat/system.h
deleted file mode 100644
index 86c6f83b44cc..000000000000
--- a/arch/arm/plat-spear/include/plat/system.h
+++ /dev/null
@@ -1,26 +0,0 @@
1/*
2 * arch/arm/plat-spear/include/plat/system.h
3 *
4 * SPEAr platform specific architecture functions
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifndef __PLAT_SYSTEM_H
15#define __PLAT_SYSTEM_H
16
17static inline void arch_idle(void)
18{
19 /*
20 * This should do all the clock switching
21 * and wait for interrupt tricks
22 */
23 cpu_do_idle();
24}
25
26#endif /* __PLAT_SYSTEM_H */