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-rw-r--r--arch/arm/mach-mx25/clock.c6
-rw-r--r--arch/arm/mach-mx25/devices-imx25.h7
-rw-r--r--arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c34
-rw-r--r--arch/arm/mach-mx25/mach-cpuimx25.c14
-rw-r--r--arch/arm/mach-mx3/devices-imx35.h9
-rw-r--r--arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c42
-rw-r--r--arch/arm/mach-mx3/mach-cpuimx35.c14
-rw-r--r--arch/arm/mach-mx3/mach-mx31ads.c7
-rw-r--r--arch/arm/mach-mx3/mach-pcm037_eet.c3
-rw-r--r--arch/arm/mach-mx3/mach-pcm043.c2
-rw-r--r--arch/arm/mach-mx5/Kconfig28
-rw-r--r--arch/arm/mach-mx5/Makefile2
-rw-r--r--arch/arm/mach-mx5/board-cpuimx51.c9
-rw-r--r--arch/arm/mach-mx5/board-cpuimx51sd.c333
-rw-r--r--arch/arm/mach-mx5/clock-mx51.c244
-rw-r--r--arch/arm/mach-mx5/devices-imx51.h4
-rw-r--r--arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c23
-rw-r--r--arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c166
-rw-r--r--arch/arm/plat-mxc/Kconfig4
-rw-r--r--arch/arm/plat-mxc/Makefile1
-rw-r--r--arch/arm/plat-mxc/devices/platform-esdhc.c56
-rw-r--r--arch/arm/plat-mxc/devices/platform-imx-i2c.c1
-rw-r--r--arch/arm/plat-mxc/include/mach/board-mx31ads.h33
-rw-r--r--arch/arm/plat-mxc/include/mach/devices-common.h10
-rw-r--r--arch/arm/plat-mxc/include/mach/eukrea-baseboards.h5
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx51.h59
-rw-r--r--arch/arm/plat-mxc/include/mach/iram.h41
-rw-r--r--arch/arm/plat-mxc/include/mach/mx25.h6
-rw-r--r--arch/arm/plat-mxc/include/mach/mx35.h6
-rw-r--r--arch/arm/plat-mxc/include/mach/mx51.h16
-rw-r--r--arch/arm/plat-mxc/include/mach/system.h32
-rw-r--r--arch/arm/plat-mxc/include/mach/uncompress.h1
-rw-r--r--arch/arm/plat-mxc/iram_alloc.c73
33 files changed, 1101 insertions, 190 deletions
diff --git a/arch/arm/mach-mx25/clock.c b/arch/arm/mach-mx25/clock.c
index 2179713873c2..9e4a5578c2fb 100644
--- a/arch/arm/mach-mx25/clock.c
+++ b/arch/arm/mach-mx25/clock.c
@@ -72,7 +72,7 @@ unsigned long get_rate_arm(struct clk *clk)
72 unsigned long rate = get_rate_mpll(); 72 unsigned long rate = get_rate_mpll();
73 73
74 if (cctl & (1 << 14)) 74 if (cctl & (1 << 14))
75 rate = (rate * 3) >> 1; 75 rate = (rate * 3) >> 2;
76 76
77 return rate / ((cctl >> 30) + 1); 77 return rate / ((cctl >> 30) + 1);
78} 78}
@@ -99,7 +99,7 @@ static unsigned long get_rate_per(int per)
99 if (readl(CRM_BASE + 0x64) & (1 << per)) 99 if (readl(CRM_BASE + 0x64) & (1 << per))
100 fref = get_rate_upll(); 100 fref = get_rate_upll();
101 else 101 else
102 fref = get_rate_ipg(NULL); 102 fref = get_rate_ahb(NULL);
103 103
104 return fref / (val + 1); 104 return fref / (val + 1);
105} 105}
@@ -261,7 +261,7 @@ DEFINE_CLOCK(esdhc2_clk, 1, CCM_CGCR1, 14, get_rate_esdhc2, NULL,
261DEFINE_CLOCK(audmux_clk, 0, CCM_CGCR1, 0, NULL, NULL, NULL); 261DEFINE_CLOCK(audmux_clk, 0, CCM_CGCR1, 0, NULL, NULL, NULL);
262DEFINE_CLOCK(csi_clk, 0, CCM_CGCR1, 4, get_rate_csi, NULL, &csi_per_clk); 262DEFINE_CLOCK(csi_clk, 0, CCM_CGCR1, 4, get_rate_csi, NULL, &csi_per_clk);
263DEFINE_CLOCK(can1_clk, 0, CCM_CGCR1, 2, get_rate_ipg, NULL, NULL); 263DEFINE_CLOCK(can1_clk, 0, CCM_CGCR1, 2, get_rate_ipg, NULL, NULL);
264DEFINE_CLOCK(can2_clk, 0, CCM_CGCR1, 3, get_rate_ipg, NULL, NULL); 264DEFINE_CLOCK(can2_clk, 1, CCM_CGCR1, 3, get_rate_ipg, NULL, NULL);
265 265
266#define _REGISTER_CLOCK(d, n, c) \ 266#define _REGISTER_CLOCK(d, n, c) \
267 { \ 267 { \
diff --git a/arch/arm/mach-mx25/devices-imx25.h b/arch/arm/mach-mx25/devices-imx25.h
index 733aaee5bae8..93afa10b13cf 100644
--- a/arch/arm/mach-mx25/devices-imx25.h
+++ b/arch/arm/mach-mx25/devices-imx25.h
@@ -49,7 +49,6 @@ extern const struct imx_spi_imx_data imx25_spi_imx_data[] __initconst;
49#define imx25_add_spi_imx1(pdata) imx25_add_spi_imx(1, pdata) 49#define imx25_add_spi_imx1(pdata) imx25_add_spi_imx(1, pdata)
50#define imx25_add_spi_imx2(pdata) imx25_add_spi_imx(2, pdata) 50#define imx25_add_spi_imx2(pdata) imx25_add_spi_imx(2, pdata)
51 51
52#define imx25_add_esdhc0(pdata) \ 52extern const struct imx_esdhc_imx_data imx25_esdhc_data[] __initconst;
53 imx_add_esdhc(0, MX25_ESDHC1_BASE_ADDR, SZ_16K, MX25_INT_MMC_SDHC1, pdata) 53#define imx25_add_esdhc(id, pdata) \
54#define imx25_add_esdhc1(pdata) \ 54 imx_add_esdhc(&imx25_esdhc_data[id], pdata)
55 imx_add_esdhc(1, MX25_ESDHC2_BASE_ADDR, SZ_16K, MX25_INT_MMC_SDHC2, pdata)
diff --git a/arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c
index c1fe048c445e..e765ac5d9a08 100644
--- a/arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c
+++ b/arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c
@@ -116,6 +116,38 @@ static struct imx_fb_videomode eukrea_mximxsd_modes[] = {
116 }, 116 },
117 .bpp = 16, 117 .bpp = 16,
118 .pcr = 0xCAD08B80, 118 .pcr = 0xCAD08B80,
119 }, {
120 .mode = {
121 .name = "DVI-VGA",
122 .refresh = 60,
123 .xres = 640,
124 .yres = 480,
125 .pixclock = 32000,
126 .hsync_len = 7,
127 .left_margin = 100,
128 .right_margin = 100,
129 .vsync_len = 7,
130 .upper_margin = 7,
131 .lower_margin = 100,
132 },
133 .pcr = 0xFA208B80,
134 .bpp = 16,
135 }, {
136 .mode = {
137 .name = "DVI-SVGA",
138 .refresh = 60,
139 .xres = 800,
140 .yres = 600,
141 .pixclock = 25000,
142 .hsync_len = 7,
143 .left_margin = 75,
144 .right_margin = 75,
145 .vsync_len = 7,
146 .upper_margin = 7,
147 .lower_margin = 75,
148 },
149 .pcr = 0xFA208B80,
150 .bpp = 16,
119 }, 151 },
120}; 152};
121 153
@@ -245,7 +277,7 @@ void __init eukrea_mbimxsd25_baseboard_init(void)
245 imx25_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata); 277 imx25_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata);
246 278
247 imx25_add_flexcan1(NULL); 279 imx25_add_flexcan1(NULL);
248 imx25_add_esdhc0(NULL); 280 imx25_add_esdhc(0, NULL);
249 281
250 gpio_request(GPIO_LED1, "LED1"); 282 gpio_request(GPIO_LED1, "LED1");
251 gpio_direction_output(GPIO_LED1, 1); 283 gpio_direction_output(GPIO_LED1, 1);
diff --git a/arch/arm/mach-mx25/mach-cpuimx25.c b/arch/arm/mach-mx25/mach-cpuimx25.c
index 21d9b9e9c92c..3b28a75007ad 100644
--- a/arch/arm/mach-mx25/mach-cpuimx25.c
+++ b/arch/arm/mach-mx25/mach-cpuimx25.c
@@ -40,7 +40,6 @@
40#include <mach/mxc_nand.h> 40#include <mach/mxc_nand.h>
41#include <mach/imxfb.h> 41#include <mach/imxfb.h>
42#include <mach/mxc_ehci.h> 42#include <mach/mxc_ehci.h>
43#include <mach/ulpi.h>
44#include <mach/iomux-mx25.h> 43#include <mach/iomux-mx25.h>
45 44
46#include "devices-imx25.h" 45#include "devices-imx25.h"
@@ -134,18 +133,13 @@ static void __init eukrea_cpuimx25_init(void)
134 ARRAY_SIZE(eukrea_cpuimx25_i2c_devices)); 133 ARRAY_SIZE(eukrea_cpuimx25_i2c_devices));
135 imx25_add_imx_i2c0(&eukrea_cpuimx25_i2c0_data); 134 imx25_add_imx_i2c0(&eukrea_cpuimx25_i2c0_data);
136 135
137#if defined(CONFIG_USB_ULPI) 136 if (otg_mode_host)
138 if (otg_mode_host) {
139 otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
140 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
141
142 mxc_register_device(&mxc_otg, &otg_pdata); 137 mxc_register_device(&mxc_otg, &otg_pdata);
143 } 138 else
144 mxc_register_device(&mxc_usbh2, &usbh2_pdata);
145#endif
146 if (!otg_mode_host)
147 mxc_register_device(&otg_udc_device, &otg_device_pdata); 139 mxc_register_device(&otg_udc_device, &otg_device_pdata);
148 140
141 mxc_register_device(&mxc_usbh2, &usbh2_pdata);
142
149#ifdef CONFIG_MACH_EUKREA_MBIMXSD25_BASEBOARD 143#ifdef CONFIG_MACH_EUKREA_MBIMXSD25_BASEBOARD
150 eukrea_mbimxsd25_baseboard_init(); 144 eukrea_mbimxsd25_baseboard_init();
151#endif 145#endif
diff --git a/arch/arm/mach-mx3/devices-imx35.h b/arch/arm/mach-mx3/devices-imx35.h
index 509b346b7fef..5eb917b638d0 100644
--- a/arch/arm/mach-mx3/devices-imx35.h
+++ b/arch/arm/mach-mx3/devices-imx35.h
@@ -46,9 +46,6 @@ extern const struct imx_spi_imx_data imx35_cspi_data[] __initconst;
46#define imx35_add_spi_imx0(pdata) imx35_add_cspi(0, pdata) 46#define imx35_add_spi_imx0(pdata) imx35_add_cspi(0, pdata)
47#define imx35_add_spi_imx1(pdata) imx35_add_cspi(1, pdata) 47#define imx35_add_spi_imx1(pdata) imx35_add_cspi(1, pdata)
48 48
49#define imx35_add_esdhc0(pdata) \ 49extern const struct imx_esdhc_imx_data imx35_esdhc_data[] __initconst;
50 imx_add_esdhc(0, MX35_ESDHC1_BASE_ADDR, SZ_16K, MX35_INT_MMC_SDHC1, pdata) 50#define imx35_add_esdhc(id, pdata) \
51#define imx35_add_esdhc1(pdata) \ 51 imx_add_esdhc(&imx35_esdhc_data[id], pdata)
52 imx_add_esdhc(1, MX35_ESDHC2_BASE_ADDR, SZ_16K, MX35_INT_MMC_SDHC2, pdata)
53#define imx35_add_esdhc2(pdata) \
54 imx_add_esdhc(2, MX35_ESDHC3_BASE_ADDR, SZ_16K, MX35_INT_MMC_SDHC3, pdata)
diff --git a/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c
index 886959906fbc..1abc10d52922 100644
--- a/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c
+++ b/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c
@@ -49,7 +49,7 @@
49 49
50static const struct fb_videomode fb_modedb[] = { 50static const struct fb_videomode fb_modedb[] = {
51 { 51 {
52 .name = "CMO_QVGA", 52 .name = "CMO-QVGA",
53 .refresh = 60, 53 .refresh = 60,
54 .xres = 320, 54 .xres = 320,
55 .yres = 240, 55 .yres = 240,
@@ -64,6 +64,40 @@ static const struct fb_videomode fb_modedb[] = {
64 .vmode = FB_VMODE_NONINTERLACED, 64 .vmode = FB_VMODE_NONINTERLACED,
65 .flag = 0, 65 .flag = 0,
66 }, 66 },
67 {
68 .name = "DVI-VGA",
69 .refresh = 60,
70 .xres = 640,
71 .yres = 480,
72 .pixclock = 32000,
73 .left_margin = 100,
74 .right_margin = 100,
75 .upper_margin = 7,
76 .lower_margin = 100,
77 .hsync_len = 7,
78 .vsync_len = 7,
79 .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT |
80 FB_SYNC_OE_ACT_HIGH | FB_SYNC_CLK_INVERT,
81 .vmode = FB_VMODE_NONINTERLACED,
82 .flag = 0,
83 },
84 {
85 .name = "DVI-SVGA",
86 .refresh = 60,
87 .xres = 800,
88 .yres = 600,
89 .pixclock = 25000,
90 .left_margin = 75,
91 .right_margin = 75,
92 .upper_margin = 7,
93 .lower_margin = 75,
94 .hsync_len = 7,
95 .vsync_len = 7,
96 .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT |
97 FB_SYNC_OE_ACT_HIGH | FB_SYNC_CLK_INVERT,
98 .vmode = FB_VMODE_NONINTERLACED,
99 .flag = 0,
100 },
67}; 101};
68 102
69static struct ipu_platform_data mx3_ipu_data = { 103static struct ipu_platform_data mx3_ipu_data = {
@@ -72,7 +106,7 @@ static struct ipu_platform_data mx3_ipu_data = {
72 106
73static struct mx3fb_platform_data mx3fb_pdata = { 107static struct mx3fb_platform_data mx3fb_pdata = {
74 .dma_dev = &mx3_ipu.dev, 108 .dma_dev = &mx3_ipu.dev,
75 .name = "CMO_QVGA", 109 .name = "CMO-QVGA",
76 .mode = fb_modedb, 110 .mode = fb_modedb,
77 .num_modes = ARRAY_SIZE(fb_modedb), 111 .num_modes = ARRAY_SIZE(fb_modedb),
78}; 112};
@@ -255,7 +289,7 @@ void __init eukrea_mbimxsd35_baseboard_init(void)
255 imx35_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata); 289 imx35_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata);
256 290
257 imx35_add_flexcan1(NULL); 291 imx35_add_flexcan1(NULL);
258 imx35_add_esdhc0(NULL); 292 imx35_add_esdhc(0, NULL);
259 293
260 gpio_request(GPIO_LED1, "LED1"); 294 gpio_request(GPIO_LED1, "LED1");
261 gpio_direction_output(GPIO_LED1, 1); 295 gpio_direction_output(GPIO_LED1, 1);
@@ -267,7 +301,7 @@ void __init eukrea_mbimxsd35_baseboard_init(void)
267 301
268 gpio_request(GPIO_LCDPWR, "LCDPWR"); 302 gpio_request(GPIO_LCDPWR, "LCDPWR");
269 gpio_direction_output(GPIO_LCDPWR, 1); 303 gpio_direction_output(GPIO_LCDPWR, 1);
270 gpio_free(GPIO_SWITCH1); 304 gpio_free(GPIO_LCDPWR);
271 305
272 i2c_register_board_info(0, eukrea_mbimxsd_i2c_devices, 306 i2c_register_board_info(0, eukrea_mbimxsd_i2c_devices,
273 ARRAY_SIZE(eukrea_mbimxsd_i2c_devices)); 307 ARRAY_SIZE(eukrea_mbimxsd_i2c_devices));
diff --git a/arch/arm/mach-mx3/mach-cpuimx35.c b/arch/arm/mach-mx3/mach-cpuimx35.c
index 6024bb958eea..bf2d6e2ec0d6 100644
--- a/arch/arm/mach-mx3/mach-cpuimx35.c
+++ b/arch/arm/mach-mx3/mach-cpuimx35.c
@@ -44,7 +44,6 @@
44#include <mach/iomux-mx35.h> 44#include <mach/iomux-mx35.h>
45#include <mach/mxc_nand.h> 45#include <mach/mxc_nand.h>
46#include <mach/mxc_ehci.h> 46#include <mach/mxc_ehci.h>
47#include <mach/ulpi.h>
48 47
49#include "devices-imx35.h" 48#include "devices-imx35.h"
50#include "devices.h" 49#include "devices.h"
@@ -167,18 +166,13 @@ static void __init mxc_board_init(void)
167 ARRAY_SIZE(eukrea_cpuimx35_i2c_devices)); 166 ARRAY_SIZE(eukrea_cpuimx35_i2c_devices));
168 imx35_add_imx_i2c0(&eukrea_cpuimx35_i2c0_data); 167 imx35_add_imx_i2c0(&eukrea_cpuimx35_i2c0_data);
169 168
170#if defined(CONFIG_USB_ULPI) 169 if (otg_mode_host)
171 if (otg_mode_host) {
172 otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
173 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
174
175 mxc_register_device(&mxc_otg_host, &otg_pdata); 170 mxc_register_device(&mxc_otg_host, &otg_pdata);
176 } 171 else
177 mxc_register_device(&mxc_usbh1, &usbh1_pdata);
178#endif
179 if (!otg_mode_host)
180 mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata); 172 mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata);
181 173
174 mxc_register_device(&mxc_usbh1, &usbh1_pdata);
175
182#ifdef CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD 176#ifdef CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD
183 eukrea_mbimxsd35_baseboard_init(); 177 eukrea_mbimxsd35_baseboard_init();
184#endif 178#endif
diff --git a/arch/arm/mach-mx3/mach-mx31ads.c b/arch/arm/mach-mx3/mach-mx31ads.c
index 96cedc4a47f5..5f670ba7f0c2 100644
--- a/arch/arm/mach-mx3/mach-mx31ads.c
+++ b/arch/arm/mach-mx3/mach-mx31ads.c
@@ -22,13 +22,13 @@
22#include <linux/i2c.h> 22#include <linux/i2c.h>
23#include <linux/irq.h> 23#include <linux/irq.h>
24 24
25#include <mach/hardware.h>
26#include <asm/mach-types.h> 25#include <asm/mach-types.h>
27#include <asm/mach/arch.h> 26#include <asm/mach/arch.h>
28#include <asm/mach/time.h> 27#include <asm/mach/time.h>
29#include <asm/memory.h> 28#include <asm/memory.h>
30#include <asm/mach/map.h> 29#include <asm/mach/map.h>
31#include <mach/common.h> 30#include <mach/common.h>
31#include <mach/board-mx31ads.h>
32#include <mach/iomux-mx3.h> 32#include <mach/iomux-mx3.h>
33 33
34#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1 34#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
@@ -40,10 +40,6 @@
40#include "devices-imx31.h" 40#include "devices-imx31.h"
41#include "devices.h" 41#include "devices.h"
42 42
43/* Base address of PBC controller */
44#define PBC_BASE_ADDRESS MX31_CS4_BASE_ADDR_VIRT
45/* Offsets for the PBC Controller register */
46
47/* PBC Board interrupt status register */ 43/* PBC Board interrupt status register */
48#define PBC_INTSTATUS 0x000016 44#define PBC_INTSTATUS 0x000016
49 45
@@ -67,7 +63,6 @@
67#define PBC_INTMASK_CLEAR_REG (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS) 63#define PBC_INTMASK_CLEAR_REG (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS)
68#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_4) 64#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_4)
69 65
70#define MXC_EXP_IO_BASE (MXC_BOARD_IRQ_START)
71#define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE) 66#define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE)
72 67
73#define EXPIO_INT_XUART_INTA (MXC_EXP_IO_BASE + 10) 68#define EXPIO_INT_XUART_INTA (MXC_EXP_IO_BASE + 10)
diff --git a/arch/arm/mach-mx3/mach-pcm037_eet.c b/arch/arm/mach-mx3/mach-pcm037_eet.c
index c8b98218efee..99e0894e07db 100644
--- a/arch/arm/mach-mx3/mach-pcm037_eet.c
+++ b/arch/arm/mach-mx3/mach-pcm037_eet.c
@@ -19,6 +19,7 @@
19 19
20#include "pcm037.h" 20#include "pcm037.h"
21#include "devices.h" 21#include "devices.h"
22#include "devices-imx31.h"
22 23
23static unsigned int pcm037_eet_pins[] = { 24static unsigned int pcm037_eet_pins[] = {
24 /* Reserve and hardwire GPIO 57 high - S6E63D6 chipselect */ 25 /* Reserve and hardwire GPIO 57 high - S6E63D6 chipselect */
@@ -181,7 +182,7 @@ static int eet_init_devices(void)
181 /* SPI */ 182 /* SPI */
182 spi_register_board_info(pcm037_spi_dev, ARRAY_SIZE(pcm037_spi_dev)); 183 spi_register_board_info(pcm037_spi_dev, ARRAY_SIZE(pcm037_spi_dev));
183#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE) 184#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
184 imx35_add_spi_imx0(&pcm037_spi1_pdata); 185 imx31_add_spi_imx0(&pcm037_spi1_pdata);
185#endif 186#endif
186 187
187 platform_device_register(&pcm037_gpio_keys_device); 188 platform_device_register(&pcm037_gpio_keys_device);
diff --git a/arch/arm/mach-mx3/mach-pcm043.c b/arch/arm/mach-mx3/mach-pcm043.c
index e790a00cf99f..a9397a4151e3 100644
--- a/arch/arm/mach-mx3/mach-pcm043.c
+++ b/arch/arm/mach-mx3/mach-pcm043.c
@@ -395,7 +395,7 @@ static void __init mxc_board_init(void)
395 mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata); 395 mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata);
396 396
397 imx35_add_flexcan1(NULL); 397 imx35_add_flexcan1(NULL);
398 imx35_add_esdhc0(NULL); 398 imx35_add_esdhc(0, NULL);
399} 399}
400 400
401static void __init pcm043_timer_init(void) 401static void __init pcm043_timer_init(void)
diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig
index fad31cc5004b..a2df9ac37996 100644
--- a/arch/arm/mach-mx5/Kconfig
+++ b/arch/arm/mach-mx5/Kconfig
@@ -31,6 +31,8 @@ config MACH_EUKREA_CPUIMX51
31 bool "Support Eukrea CPUIMX51 module" 31 bool "Support Eukrea CPUIMX51 module"
32 select IMX_HAVE_PLATFORM_IMX_I2C 32 select IMX_HAVE_PLATFORM_IMX_I2C
33 select IMX_HAVE_PLATFORM_IMX_UART 33 select IMX_HAVE_PLATFORM_IMX_UART
34 select IMX_HAVE_PLATFORM_MXC_NAND
35 select IMX_HAVE_PLATFORM_SPI_IMX
34 help 36 help
35 Include support for Eukrea CPUIMX51 platform. This includes 37 Include support for Eukrea CPUIMX51 platform. This includes
36 specific configurations for the module and its peripherals. 38 specific configurations for the module and its peripherals.
@@ -43,12 +45,38 @@ choice
43config MACH_EUKREA_MBIMX51_BASEBOARD 45config MACH_EUKREA_MBIMX51_BASEBOARD
44 prompt "Eukrea MBIMX51 development board" 46 prompt "Eukrea MBIMX51 development board"
45 bool 47 bool
48 select IMX_HAVE_PLATFORM_ESDHC
46 help 49 help
47 This adds board specific devices that can be found on Eukrea's 50 This adds board specific devices that can be found on Eukrea's
48 MBIMX51 evaluation board. 51 MBIMX51 evaluation board.
49 52
50endchoice 53endchoice
51 54
55config MACH_EUKREA_CPUIMX51SD
56 bool "Support Eukrea CPUIMX51SD module"
57 select IMX_HAVE_PLATFORM_IMX_I2C
58 select IMX_HAVE_PLATFORM_SPI_IMX
59 select IMX_HAVE_PLATFORM_IMX_UART
60 select IMX_HAVE_PLATFORM_MXC_NAND
61 help
62 Include support for Eukrea CPUIMX51SD platform. This includes
63 specific configurations for the module and its peripherals.
64
65choice
66 prompt "Baseboard"
67 depends on MACH_EUKREA_CPUIMX51SD
68 default MACH_EUKREA_MBIMXSD51_BASEBOARD
69
70config MACH_EUKREA_MBIMXSD51_BASEBOARD
71 prompt "Eukrea MBIMXSD development board"
72 bool
73 select IMX_HAVE_PLATFORM_ESDHC
74 help
75 This adds board specific devices that can be found on Eukrea's
76 MBIMXSD evaluation board.
77
78endchoice
79
52config MACH_MX51_EFIKAMX 80config MACH_MX51_EFIKAMX
53 bool "Support MX51 Genesi Efika MX nettop" 81 bool "Support MX51 Genesi Efika MX nettop"
54 select IMX_HAVE_PLATFORM_IMX_UART 82 select IMX_HAVE_PLATFORM_IMX_UART
diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile
index d1aac9c3d33c..1769c161a60d 100644
--- a/arch/arm/mach-mx5/Makefile
+++ b/arch/arm/mach-mx5/Makefile
@@ -9,4 +9,6 @@ obj-$(CONFIG_MACH_MX51_BABBAGE) += board-mx51_babbage.o
9obj-$(CONFIG_MACH_MX51_3DS) += board-mx51_3ds.o 9obj-$(CONFIG_MACH_MX51_3DS) += board-mx51_3ds.o
10obj-$(CONFIG_MACH_EUKREA_CPUIMX51) += board-cpuimx51.o 10obj-$(CONFIG_MACH_EUKREA_CPUIMX51) += board-cpuimx51.o
11obj-$(CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD) += eukrea_mbimx51-baseboard.o 11obj-$(CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD) += eukrea_mbimx51-baseboard.o
12obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += board-cpuimx51sd.o
13obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd-baseboard.o
12obj-$(CONFIG_MACH_MX51_EFIKAMX) += board-mx51_efikamx.o 14obj-$(CONFIG_MACH_MX51_EFIKAMX) += board-mx51_efikamx.o
diff --git a/arch/arm/mach-mx5/board-cpuimx51.c b/arch/arm/mach-mx5/board-cpuimx51.c
index 61f051043bbc..378f5327ae77 100644
--- a/arch/arm/mach-mx5/board-cpuimx51.c
+++ b/arch/arm/mach-mx5/board-cpuimx51.c
@@ -146,6 +146,13 @@ static struct pad_desc eukrea_cpuimx51_pads[] = {
146 MX51_PAD_USBH1_STP__USBH1_STP, 146 MX51_PAD_USBH1_STP__USBH1_STP,
147}; 147};
148 148
149static const struct mxc_nand_platform_data
150 eukrea_cpuimx51_nand_board_info __initconst = {
151 .width = 1,
152 .hw_ecc = 1,
153 .flash_bbt = 1,
154};
155
149static const struct imxuart_platform_data uart_pdata __initconst = { 156static const struct imxuart_platform_data uart_pdata __initconst = {
150 .flags = IMXUART_HAVE_RTSCTS, 157 .flags = IMXUART_HAVE_RTSCTS,
151}; 158};
@@ -239,6 +246,8 @@ static void __init eukrea_cpuimx51_init(void)
239 ARRAY_SIZE(eukrea_cpuimx51_pads)); 246 ARRAY_SIZE(eukrea_cpuimx51_pads));
240 247
241 imx51_add_imx_uart(0, &uart_pdata); 248 imx51_add_imx_uart(0, &uart_pdata);
249 imx51_add_mxc_nand(&eukrea_cpuimx51_nand_board_info);
250
242 gpio_request(CPUIMX51_QUARTA_GPIO, "quarta_irq"); 251 gpio_request(CPUIMX51_QUARTA_GPIO, "quarta_irq");
243 gpio_direction_input(CPUIMX51_QUARTA_GPIO); 252 gpio_direction_input(CPUIMX51_QUARTA_GPIO);
244 gpio_free(CPUIMX51_QUARTA_GPIO); 253 gpio_free(CPUIMX51_QUARTA_GPIO);
diff --git a/arch/arm/mach-mx5/board-cpuimx51sd.c b/arch/arm/mach-mx5/board-cpuimx51sd.c
new file mode 100644
index 000000000000..bd5eb61a7eba
--- /dev/null
+++ b/arch/arm/mach-mx5/board-cpuimx51sd.c
@@ -0,0 +1,333 @@
1/*
2 *
3 * Copyright (C) 2010 Eric Bénard <eric@eukrea.com>
4 *
5 * based on board-mx51_babbage.c which is
6 * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
8 *
9 * The code contained herein is licensed under the GNU General Public
10 * License. You may obtain a copy of the GNU General Public License
11 * Version 2 or later at the following locations:
12 *
13 * http://www.opensource.org/licenses/gpl-license.html
14 * http://www.gnu.org/copyleft/gpl.html
15 */
16
17#include <linux/init.h>
18#include <linux/platform_device.h>
19#include <linux/i2c.h>
20#include <linux/i2c/tsc2007.h>
21#include <linux/gpio.h>
22#include <linux/delay.h>
23#include <linux/io.h>
24#include <linux/interrupt.h>
25#include <linux/irq.h>
26#include <linux/fsl_devices.h>
27#include <linux/i2c-gpio.h>
28#include <linux/spi/spi.h>
29#include <linux/can/platform/mcp251x.h>
30
31#include <mach/eukrea-baseboards.h>
32#include <mach/common.h>
33#include <mach/hardware.h>
34#include <mach/iomux-mx51.h>
35#include <mach/mxc_ehci.h>
36
37#include <asm/irq.h>
38#include <asm/setup.h>
39#include <asm/mach-types.h>
40#include <asm/mach/arch.h>
41#include <asm/mach/time.h>
42
43#include "devices-imx51.h"
44#include "devices.h"
45
46#define USBH1_RST (1*32 + 28)
47#define ETH_RST (1*32 + 31)
48#define TSC2007_IRQGPIO (2*32 + 12)
49#define CAN_IRQGPIO (0*32 + 1)
50#define CAN_RST (3*32 + 15)
51#define CAN_NCS (3*32 + 24)
52#define CAN_RXOBF (0*32 + 4)
53#define CAN_RX1BF (0*32 + 6)
54#define CAN_TXORTS (0*32 + 7)
55#define CAN_TX1RTS (0*32 + 8)
56#define CAN_TX2RTS (0*32 + 9)
57#define I2C_SCL (3*32 + 16)
58#define I2C_SDA (3*32 + 17)
59
60/* USB_CTRL_1 */
61#define MX51_USB_CTRL_1_OFFSET 0x10
62#define MX51_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
63
64#define MX51_USB_PLLDIV_12_MHZ 0x00
65#define MX51_USB_PLL_DIV_19_2_MHZ 0x01
66#define MX51_USB_PLL_DIV_24_MHZ 0x02
67
68#define CPUIMX51SD_GPIO_3_12 IOMUX_PAD(0x57C, 0x194, 3, 0x0, 0, \
69 MX51_PAD_CTRL_1 | PAD_CTL_PUS_22K_UP)
70
71static struct pad_desc eukrea_cpuimx51sd_pads[] = {
72 /* UART1 */
73 MX51_PAD_UART1_RXD__UART1_RXD,
74 MX51_PAD_UART1_TXD__UART1_TXD,
75 MX51_PAD_UART1_RTS__UART1_RTS,
76 MX51_PAD_UART1_CTS__UART1_CTS,
77
78 /* USB HOST1 */
79 MX51_PAD_USBH1_CLK__USBH1_CLK,
80 MX51_PAD_USBH1_DIR__USBH1_DIR,
81 MX51_PAD_USBH1_NXT__USBH1_NXT,
82 MX51_PAD_USBH1_DATA0__USBH1_DATA0,
83 MX51_PAD_USBH1_DATA1__USBH1_DATA1,
84 MX51_PAD_USBH1_DATA2__USBH1_DATA2,
85 MX51_PAD_USBH1_DATA3__USBH1_DATA3,
86 MX51_PAD_USBH1_DATA4__USBH1_DATA4,
87 MX51_PAD_USBH1_DATA5__USBH1_DATA5,
88 MX51_PAD_USBH1_DATA6__USBH1_DATA6,
89 MX51_PAD_USBH1_DATA7__USBH1_DATA7,
90 MX51_PAD_USBH1_STP__USBH1_STP,
91 MX51_PAD_EIM_CS3__GPIO_2_28, /* PHY nRESET */
92
93 /* FEC */
94 MX51_PAD_EIM_DTACK__GPIO_2_31, /* PHY nRESET */
95
96 /* HSI2C */
97 MX51_PAD_I2C1_CLK__GPIO_4_16,
98 MX51_PAD_I2C1_DAT__GPIO_4_17,
99
100 /* CAN */
101 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
102 MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
103 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
104 MX51_PAD_CSPI1_SS0__GPIO_4_24, /* nCS */
105 MX51_PAD_CSI2_PIXCLK__GPIO_4_15, /* nReset */
106 MX51_PAD_GPIO_1_1__GPIO_1_1, /* IRQ */
107 MX51_PAD_GPIO_1_4__GPIO_1_4, /* Control signals */
108 MX51_PAD_GPIO_1_6__GPIO_1_6,
109 MX51_PAD_GPIO_1_7__GPIO_1_7,
110 MX51_PAD_GPIO_1_8__GPIO_1_8,
111 MX51_PAD_GPIO_1_9__GPIO_1_9,
112
113 /* Touchscreen */
114 CPUIMX51SD_GPIO_3_12, /* IRQ */
115};
116
117static const struct imxuart_platform_data uart_pdata __initconst = {
118 .flags = IMXUART_HAVE_RTSCTS,
119};
120
121static int ts_get_pendown_state(void)
122{
123 return gpio_get_value(TSC2007_IRQGPIO) ? 0 : 1;
124}
125
126static struct tsc2007_platform_data tsc2007_info = {
127 .model = 2007,
128 .x_plate_ohms = 180,
129 .get_pendown_state = ts_get_pendown_state,
130};
131
132static struct i2c_board_info eukrea_cpuimx51sd_i2c_devices[] = {
133 {
134 I2C_BOARD_INFO("pcf8563", 0x51),
135 }, {
136 I2C_BOARD_INFO("tsc2007", 0x49),
137 .type = "tsc2007",
138 .platform_data = &tsc2007_info,
139 .irq = gpio_to_irq(TSC2007_IRQGPIO),
140 },
141};
142
143static const struct mxc_nand_platform_data
144 eukrea_cpuimx51sd_nand_board_info __initconst = {
145 .width = 1,
146 .hw_ecc = 1,
147 .flash_bbt = 1,
148};
149
150/* This function is board specific as the bit mask for the plldiv will also
151be different for other Freescale SoCs, thus a common bitmask is not
152possible and cannot get place in /plat-mxc/ehci.c.*/
153static int initialize_otg_port(struct platform_device *pdev)
154{
155 u32 v;
156 void __iomem *usb_base;
157 void __iomem *usbother_base;
158
159 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
160 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
161
162 /* Set the PHY clock to 19.2MHz */
163 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
164 v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
165 v |= MX51_USB_PLL_DIV_19_2_MHZ;
166 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
167 iounmap(usb_base);
168 return 0;
169}
170
171static int initialize_usbh1_port(struct platform_device *pdev)
172{
173 u32 v;
174 void __iomem *usb_base;
175 void __iomem *usbother_base;
176
177 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
178 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
179
180 /* The clock for the USBH1 ULPI port will come from the PHY. */
181 v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
182 __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN,
183 usbother_base + MX51_USB_CTRL_1_OFFSET);
184 iounmap(usb_base);
185 return 0;
186}
187
188static struct mxc_usbh_platform_data dr_utmi_config = {
189 .init = initialize_otg_port,
190 .portsc = MXC_EHCI_UTMI_16BIT,
191 .flags = MXC_EHCI_INTERNAL_PHY,
192};
193
194static struct fsl_usb2_platform_data usb_pdata = {
195 .operating_mode = FSL_USB2_DR_DEVICE,
196 .phy_mode = FSL_USB2_PHY_UTMI_WIDE,
197};
198
199static struct mxc_usbh_platform_data usbh1_config = {
200 .init = initialize_usbh1_port,
201 .portsc = MXC_EHCI_MODE_ULPI,
202 .flags = (MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_ITC_NO_THRESHOLD),
203};
204
205static int otg_mode_host;
206
207static int __init eukrea_cpuimx51sd_otg_mode(char *options)
208{
209 if (!strcmp(options, "host"))
210 otg_mode_host = 1;
211 else if (!strcmp(options, "device"))
212 otg_mode_host = 0;
213 else
214 pr_info("otg_mode neither \"host\" nor \"device\". "
215 "Defaulting to device\n");
216 return 0;
217}
218__setup("otg_mode=", eukrea_cpuimx51sd_otg_mode);
219
220static struct i2c_gpio_platform_data pdata = {
221 .sda_pin = I2C_SDA,
222 .sda_is_open_drain = 0,
223 .scl_pin = I2C_SCL,
224 .scl_is_open_drain = 0,
225 .udelay = 2,
226};
227
228static struct platform_device hsi2c_gpio_device = {
229 .name = "i2c-gpio",
230 .id = 0,
231 .dev.platform_data = &pdata,
232};
233
234static struct mcp251x_platform_data mcp251x_info = {
235 .oscillator_frequency = 24E6,
236};
237
238static struct spi_board_info cpuimx51sd_spi_device[] = {
239 {
240 .modalias = "mcp2515",
241 .max_speed_hz = 6500000,
242 .bus_num = 0,
243 .mode = SPI_MODE_0,
244 .chip_select = 0,
245 .platform_data = &mcp251x_info,
246 .irq = gpio_to_irq(0 * 32 + 1)
247 },
248};
249
250static int cpuimx51sd_spi1_cs[] = {
251 CAN_NCS,
252};
253
254static const struct spi_imx_master cpuimx51sd_ecspi1_pdata __initconst = {
255 .chipselect = cpuimx51sd_spi1_cs,
256 .num_chipselect = ARRAY_SIZE(cpuimx51sd_spi1_cs),
257};
258
259static struct platform_device *platform_devices[] __initdata = {
260 &hsi2c_gpio_device,
261};
262
263static void __init eukrea_cpuimx51sd_init(void)
264{
265 mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51sd_pads,
266 ARRAY_SIZE(eukrea_cpuimx51sd_pads));
267
268 imx51_add_imx_uart(0, &uart_pdata);
269 imx51_add_mxc_nand(&eukrea_cpuimx51sd_nand_board_info);
270
271 gpio_request(ETH_RST, "eth_rst");
272 gpio_set_value(ETH_RST, 1);
273 imx51_add_fec(NULL);
274
275 gpio_request(CAN_IRQGPIO, "can_irq");
276 gpio_direction_input(CAN_IRQGPIO);
277 gpio_free(CAN_IRQGPIO);
278 gpio_request(CAN_NCS, "can_ncs");
279 gpio_direction_output(CAN_NCS, 1);
280 gpio_free(CAN_NCS);
281 gpio_request(CAN_RST, "can_rst");
282 gpio_direction_output(CAN_RST, 0);
283 msleep(20);
284 gpio_set_value(CAN_RST, 1);
285 imx51_add_ecspi(0, &cpuimx51sd_ecspi1_pdata);
286 spi_register_board_info(cpuimx51sd_spi_device,
287 ARRAY_SIZE(cpuimx51sd_spi_device));
288
289 gpio_request(TSC2007_IRQGPIO, "tsc2007_irq");
290 gpio_direction_input(TSC2007_IRQGPIO);
291 gpio_free(TSC2007_IRQGPIO);
292
293 i2c_register_board_info(0, eukrea_cpuimx51sd_i2c_devices,
294 ARRAY_SIZE(eukrea_cpuimx51sd_i2c_devices));
295 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
296
297 if (otg_mode_host)
298 mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
299 else {
300 initialize_otg_port(NULL);
301 mxc_register_device(&mxc_usbdr_udc_device, &usb_pdata);
302 }
303
304 gpio_request(USBH1_RST, "usb_rst");
305 gpio_direction_output(USBH1_RST, 0);
306 msleep(20);
307 gpio_set_value(USBH1_RST, 1);
308 mxc_register_device(&mxc_usbh1_device, &usbh1_config);
309
310#ifdef CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD
311 eukrea_mbimxsd51_baseboard_init();
312#endif
313}
314
315static void __init eukrea_cpuimx51sd_timer_init(void)
316{
317 mx51_clocks_init(32768, 24000000, 22579200, 0);
318}
319
320static struct sys_timer mxc_timer = {
321 .init = eukrea_cpuimx51sd_timer_init,
322};
323
324MACHINE_START(EUKREA_CPUIMX51SD, "Eukrea CPUIMX51SD")
325 /* Maintainer: Eric Bénard <eric@eukrea.com> */
326 .phys_io = MX51_AIPS1_BASE_ADDR,
327 .io_pg_offst = ((MX51_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
328 .boot_params = PHYS_OFFSET + 0x100,
329 .map_io = mx51_map_io,
330 .init_irq = mx51_init_irq,
331 .init_machine = eukrea_cpuimx51sd_init,
332 .timer = &mxc_timer,
333MACHINE_END
diff --git a/arch/arm/mach-mx5/clock-mx51.c b/arch/arm/mach-mx5/clock-mx51.c
index 21cecc040172..f2aae92cf0e2 100644
--- a/arch/arm/mach-mx5/clock-mx51.c
+++ b/arch/arm/mach-mx5/clock-mx51.c
@@ -41,6 +41,36 @@ static struct clk usboh3_clk;
41 41
42#define MAX_DPLL_WAIT_TRIES 1000 /* 1000 * udelay(1) = 1ms */ 42#define MAX_DPLL_WAIT_TRIES 1000 /* 1000 * udelay(1) = 1ms */
43 43
44/* calculate best pre and post dividers to get the required divider */
45static void __calc_pre_post_dividers(u32 div, u32 *pre, u32 *post,
46 u32 max_pre, u32 max_post)
47{
48 if (div >= max_pre * max_post) {
49 *pre = max_pre;
50 *post = max_post;
51 } else if (div >= max_pre) {
52 u32 min_pre, temp_pre, old_err, err;
53 min_pre = DIV_ROUND_UP(div, max_post);
54 old_err = max_pre;
55 for (temp_pre = max_pre; temp_pre >= min_pre; temp_pre--) {
56 err = div % temp_pre;
57 if (err == 0) {
58 *pre = temp_pre;
59 break;
60 }
61 err = temp_pre - err;
62 if (err < old_err) {
63 old_err = err;
64 *pre = temp_pre;
65 }
66 }
67 *post = DIV_ROUND_UP(div, *pre);
68 } else {
69 *pre = div;
70 *post = 1;
71 }
72}
73
44static void _clk_ccgr_setclk(struct clk *clk, unsigned mode) 74static void _clk_ccgr_setclk(struct clk *clk, unsigned mode)
45{ 75{
46 u32 reg = __raw_readl(clk->enable_reg); 76 u32 reg = __raw_readl(clk->enable_reg);
@@ -544,35 +574,6 @@ static int _clk_ipg_per_set_parent(struct clk *clk, struct clk *parent)
544 return 0; 574 return 0;
545} 575}
546 576
547static unsigned long clk_uart_get_rate(struct clk *clk)
548{
549 u32 reg, prediv, podf;
550 unsigned long parent_rate;
551
552 parent_rate = clk_get_rate(clk->parent);
553
554 reg = __raw_readl(MXC_CCM_CSCDR1);
555 prediv = ((reg & MXC_CCM_CSCDR1_UART_CLK_PRED_MASK) >>
556 MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET) + 1;
557 podf = ((reg & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK) >>
558 MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET) + 1;
559
560 return parent_rate / (prediv * podf);
561}
562
563static int _clk_uart_set_parent(struct clk *clk, struct clk *parent)
564{
565 u32 reg, mux;
566
567 mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk,
568 &lp_apm_clk);
569 reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_UART_CLK_SEL_MASK;
570 reg |= mux << MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET;
571 __raw_writel(reg, MXC_CCM_CSCMR1);
572
573 return 0;
574}
575
576#define clk_nfc_set_parent NULL 577#define clk_nfc_set_parent NULL
577 578
578static unsigned long clk_nfc_get_rate(struct clk *clk) 579static unsigned long clk_nfc_get_rate(struct clk *clk)
@@ -631,35 +632,6 @@ static int clk_nfc_set_rate(struct clk *clk, unsigned long rate)
631 return 0; 632 return 0;
632} 633}
633 634
634static unsigned long clk_usboh3_get_rate(struct clk *clk)
635{
636 u32 reg, prediv, podf;
637 unsigned long parent_rate;
638
639 parent_rate = clk_get_rate(clk->parent);
640
641 reg = __raw_readl(MXC_CCM_CSCDR1);
642 prediv = ((reg & MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK) >>
643 MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET) + 1;
644 podf = ((reg & MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK) >>
645 MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET) + 1;
646
647 return parent_rate / (prediv * podf);
648}
649
650static int _clk_usboh3_set_parent(struct clk *clk, struct clk *parent)
651{
652 u32 reg, mux;
653
654 mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk,
655 &lp_apm_clk);
656 reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK;
657 reg |= mux << MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET;
658 __raw_writel(reg, MXC_CCM_CSCMR1);
659
660 return 0;
661}
662
663static unsigned long get_high_reference_clock_rate(struct clk *clk) 635static unsigned long get_high_reference_clock_rate(struct clk *clk)
664{ 636{
665 return external_high_reference; 637 return external_high_reference;
@@ -786,18 +758,6 @@ static struct clk ipg_perclk = {
786 .set_parent = _clk_ipg_per_set_parent, 758 .set_parent = _clk_ipg_per_set_parent,
787}; 759};
788 760
789static struct clk uart_root_clk = {
790 .parent = &pll2_sw_clk,
791 .get_rate = clk_uart_get_rate,
792 .set_parent = _clk_uart_set_parent,
793};
794
795static struct clk usboh3_clk = {
796 .parent = &pll2_sw_clk,
797 .get_rate = clk_usboh3_get_rate,
798 .set_parent = _clk_usboh3_set_parent,
799};
800
801static struct clk ahb_max_clk = { 761static struct clk ahb_max_clk = {
802 .parent = &ahb_clk, 762 .parent = &ahb_clk,
803 .enable_reg = MXC_CCM_CCGR0, 763 .enable_reg = MXC_CCM_CCGR0,
@@ -842,7 +802,7 @@ static struct clk emi_slow_clk = {
842 .get_rate = clk_emi_slow_get_rate, 802 .get_rate = clk_emi_slow_get_rate,
843}; 803};
844 804
845#define DEFINE_CLOCK1(name, i, er, es, pfx, p, s) \ 805#define DEFINE_CLOCK_CCGR(name, i, er, es, pfx, p, s) \
846 static struct clk name = { \ 806 static struct clk name = { \
847 .id = i, \ 807 .id = i, \
848 .enable_reg = er, \ 808 .enable_reg = er, \
@@ -857,35 +817,104 @@ static struct clk emi_slow_clk = {
857 .secondary = s, \ 817 .secondary = s, \
858 } 818 }
859 819
860/* eCSPI */ 820#define DEFINE_CLOCK_MAX(name, i, er, es, pfx, p, s) \
861static unsigned long clk_ecspi_get_rate(struct clk *clk) 821 static struct clk name = { \
862{ 822 .id = i, \
863 u32 reg, pred, podf; 823 .enable_reg = er, \
824 .enable_shift = es, \
825 .get_rate = pfx##_get_rate, \
826 .set_rate = pfx##_set_rate, \
827 .set_parent = pfx##_set_parent, \
828 .enable = _clk_max_enable, \
829 .disable = _clk_max_disable, \
830 .parent = p, \
831 .secondary = s, \
832 }
864 833
865 reg = __raw_readl(MXC_CCM_CSCDR2); 834#define CLK_GET_RATE(name, nr, bitsname) \
835static unsigned long clk_##name##_get_rate(struct clk *clk) \
836{ \
837 u32 reg, pred, podf; \
838 \
839 reg = __raw_readl(MXC_CCM_CSCDR##nr); \
840 pred = (reg & MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_MASK) \
841 >> MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_OFFSET; \
842 podf = (reg & MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_MASK) \
843 >> MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_OFFSET; \
844 \
845 return DIV_ROUND_CLOSEST(clk_get_rate(clk->parent), \
846 (pred + 1) * (podf + 1)); \
847}
866 848
867 pred = (reg & MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK) >> 849#define CLK_SET_PARENT(name, nr, bitsname) \
868 MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET; 850static int clk_##name##_set_parent(struct clk *clk, struct clk *parent) \
869 podf = (reg & MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK) >> 851{ \
870 MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET; 852 u32 reg, mux; \
853 \
854 mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, \
855 &pll3_sw_clk, &lp_apm_clk); \
856 reg = __raw_readl(MXC_CCM_CSCMR##nr) & \
857 ~MXC_CCM_CSCMR##nr##_##bitsname##_CLK_SEL_MASK; \
858 reg |= mux << MXC_CCM_CSCMR##nr##_##bitsname##_CLK_SEL_OFFSET; \
859 __raw_writel(reg, MXC_CCM_CSCMR##nr); \
860 \
861 return 0; \
862}
871 863
872 return DIV_ROUND_CLOSEST(clk_get_rate(clk->parent), 864#define CLK_SET_RATE(name, nr, bitsname) \
873 (pred + 1) * (podf + 1)); 865static int clk_##name##_set_rate(struct clk *clk, unsigned long rate) \
866{ \
867 u32 reg, div, parent_rate; \
868 u32 pre = 0, post = 0; \
869 \
870 parent_rate = clk_get_rate(clk->parent); \
871 div = parent_rate / rate; \
872 \
873 if ((parent_rate / div) != rate) \
874 return -EINVAL; \
875 \
876 __calc_pre_post_dividers(div, &pre, &post, \
877 (MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_MASK >> \
878 MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_OFFSET) + 1, \
879 (MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_MASK >> \
880 MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_OFFSET) + 1);\
881 \
882 /* Set sdhc1 clock divider */ \
883 reg = __raw_readl(MXC_CCM_CSCDR##nr) & \
884 ~(MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_MASK \
885 | MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_MASK); \
886 reg |= (post - 1) << \
887 MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_OFFSET; \
888 reg |= (pre - 1) << \
889 MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_OFFSET; \
890 __raw_writel(reg, MXC_CCM_CSCDR##nr); \
891 \
892 return 0; \
874} 893}
875 894
876static int clk_ecspi_set_parent(struct clk *clk, struct clk *parent) 895/* UART */
877{ 896CLK_GET_RATE(uart, 1, UART)
878 u32 reg, mux; 897CLK_SET_PARENT(uart, 1, UART)
879 898
880 mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, 899static struct clk uart_root_clk = {
881 &lp_apm_clk); 900 .parent = &pll2_sw_clk,
901 .get_rate = clk_uart_get_rate,
902 .set_parent = clk_uart_set_parent,
903};
882 904
883 reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK; 905/* USBOH3 */
884 reg |= mux << MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET; 906CLK_GET_RATE(usboh3, 1, USBOH3)
885 __raw_writel(reg, MXC_CCM_CSCMR1); 907CLK_SET_PARENT(usboh3, 1, USBOH3)
886 908
887 return 0; 909static struct clk usboh3_clk = {
888} 910 .parent = &pll2_sw_clk,
911 .get_rate = clk_usboh3_get_rate,
912 .set_parent = clk_usboh3_set_parent,
913};
914
915/* eCSPI */
916CLK_GET_RATE(ecspi, 2, CSPI)
917CLK_SET_PARENT(ecspi, 1, CSPI)
889 918
890static struct clk ecspi_main_clk = { 919static struct clk ecspi_main_clk = {
891 .parent = &pll3_sw_clk, 920 .parent = &pll3_sw_clk,
@@ -893,6 +922,15 @@ static struct clk ecspi_main_clk = {
893 .set_parent = clk_ecspi_set_parent, 922 .set_parent = clk_ecspi_set_parent,
894}; 923};
895 924
925/* eSDHC */
926CLK_GET_RATE(esdhc1, 1, ESDHC1_MSHC1)
927CLK_SET_PARENT(esdhc1, 1, ESDHC1_MSHC1)
928CLK_SET_RATE(esdhc1, 1, ESDHC1_MSHC1)
929
930CLK_GET_RATE(esdhc2, 1, ESDHC2_MSHC2)
931CLK_SET_PARENT(esdhc2, 1, ESDHC2_MSHC2)
932CLK_SET_RATE(esdhc2, 1, ESDHC2_MSHC2)
933
896#define DEFINE_CLOCK_FULL(name, i, er, es, gr, sr, e, d, p, s) \ 934#define DEFINE_CLOCK_FULL(name, i, er, es, gr, sr, e, d, p, s) \
897 static struct clk name = { \ 935 static struct clk name = { \
898 .id = i, \ 936 .id = i, \
@@ -946,7 +984,7 @@ DEFINE_CLOCK(fec_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG12_OFFSET,
946 NULL, NULL, &ipg_clk, NULL); 984 NULL, NULL, &ipg_clk, NULL);
947 985
948/* NFC */ 986/* NFC */
949DEFINE_CLOCK1(nfc_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG10_OFFSET, 987DEFINE_CLOCK_CCGR(nfc_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG10_OFFSET,
950 clk_nfc, &emi_slow_clk, NULL); 988 clk_nfc, &emi_slow_clk, NULL);
951 989
952/* SSI */ 990/* SSI */
@@ -981,6 +1019,16 @@ DEFINE_CLOCK(cspi_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG13_OFFSET,
981DEFINE_CLOCK(sdma_clk, 1, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG15_OFFSET, 1019DEFINE_CLOCK(sdma_clk, 1, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG15_OFFSET,
982 NULL, NULL, &ahb_clk, NULL); 1020 NULL, NULL, &ahb_clk, NULL);
983 1021
1022/* eSDHC */
1023DEFINE_CLOCK_FULL(esdhc1_ipg_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG0_OFFSET,
1024 NULL, NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL);
1025DEFINE_CLOCK_MAX(esdhc1_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG1_OFFSET,
1026 clk_esdhc1, &pll2_sw_clk, &esdhc1_ipg_clk);
1027DEFINE_CLOCK_FULL(esdhc2_ipg_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG2_OFFSET,
1028 NULL, NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL);
1029DEFINE_CLOCK_MAX(esdhc2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG3_OFFSET,
1030 clk_esdhc2, &pll2_sw_clk, &esdhc2_ipg_clk);
1031
984#define _REGISTER_CLOCK(d, n, c) \ 1032#define _REGISTER_CLOCK(d, n, c) \
985 { \ 1033 { \
986 .dev_id = d, \ 1034 .dev_id = d, \
@@ -1014,6 +1062,8 @@ static struct clk_lookup lookups[] = {
1014 _REGISTER_CLOCK("imx51-ecspi.0", NULL, ecspi1_clk) 1062 _REGISTER_CLOCK("imx51-ecspi.0", NULL, ecspi1_clk)
1015 _REGISTER_CLOCK("imx51-ecspi.1", NULL, ecspi2_clk) 1063 _REGISTER_CLOCK("imx51-ecspi.1", NULL, ecspi2_clk)
1016 _REGISTER_CLOCK("imx51-cspi.0", NULL, cspi_clk) 1064 _REGISTER_CLOCK("imx51-cspi.0", NULL, cspi_clk)
1065 _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk)
1066 _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_clk)
1017}; 1067};
1018 1068
1019static void clk_tree_init(void) 1069static void clk_tree_init(void)
@@ -1057,6 +1107,14 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc,
1057 /* set the usboh3_clk parent to pll2_sw_clk */ 1107 /* set the usboh3_clk parent to pll2_sw_clk */
1058 clk_set_parent(&usboh3_clk, &pll2_sw_clk); 1108 clk_set_parent(&usboh3_clk, &pll2_sw_clk);
1059 1109
1110 /* Set SDHC parents to be PLL2 */
1111 clk_set_parent(&esdhc1_clk, &pll2_sw_clk);
1112 clk_set_parent(&esdhc2_clk, &pll2_sw_clk);
1113
1114 /* set SDHC root clock as 166.25MHZ*/
1115 clk_set_rate(&esdhc1_clk, 166250000);
1116 clk_set_rate(&esdhc2_clk, 166250000);
1117
1060 /* System timer */ 1118 /* System timer */
1061 mxc_timer_init(&gpt_clk, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR), 1119 mxc_timer_init(&gpt_clk, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR),
1062 MX51_MXC_INT_GPT); 1120 MX51_MXC_INT_GPT);
diff --git a/arch/arm/mach-mx5/devices-imx51.h b/arch/arm/mach-mx5/devices-imx51.h
index c233379256b8..5cc910e60538 100644
--- a/arch/arm/mach-mx5/devices-imx51.h
+++ b/arch/arm/mach-mx5/devices-imx51.h
@@ -36,3 +36,7 @@ extern const struct imx_spi_imx_data imx51_cspi_data __initconst;
36extern const struct imx_spi_imx_data imx51_ecspi_data[] __initconst; 36extern const struct imx_spi_imx_data imx51_ecspi_data[] __initconst;
37#define imx51_add_ecspi(id, pdata) \ 37#define imx51_add_ecspi(id, pdata) \
38 imx_add_spi_imx(&imx51_ecspi_data[id], pdata) 38 imx_add_spi_imx(&imx51_ecspi_data[id], pdata)
39
40extern const struct imx_esdhc_imx_data imx51_esdhc_data[] __initconst;
41#define imx51_add_esdhc(id, pdata) \
42 imx_add_esdhc(&imx51_esdhc_data[id], pdata)
diff --git a/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
index d0e417ce2c08..a2e6e8c39d25 100644
--- a/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
+++ b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
@@ -113,6 +113,22 @@ static struct pad_desc mbimx51_pads[] = {
113 MX51_PAD_KEY_COL1__KEY_COL1, 113 MX51_PAD_KEY_COL1__KEY_COL1,
114 MX51_PAD_KEY_COL2__KEY_COL2, 114 MX51_PAD_KEY_COL2__KEY_COL2,
115 MX51_PAD_KEY_COL3__KEY_COL3, 115 MX51_PAD_KEY_COL3__KEY_COL3,
116
117 /* SD 1 */
118 MX51_PAD_SD1_CMD__SD1_CMD,
119 MX51_PAD_SD1_CLK__SD1_CLK,
120 MX51_PAD_SD1_DATA0__SD1_DATA0,
121 MX51_PAD_SD1_DATA1__SD1_DATA1,
122 MX51_PAD_SD1_DATA2__SD1_DATA2,
123 MX51_PAD_SD1_DATA3__SD1_DATA3,
124
125 /* SD 2 */
126 MX51_PAD_SD2_CMD__SD2_CMD,
127 MX51_PAD_SD2_CLK__SD2_CLK,
128 MX51_PAD_SD2_DATA0__SD2_DATA0,
129 MX51_PAD_SD2_DATA1__SD2_DATA1,
130 MX51_PAD_SD2_DATA2__SD2_DATA2,
131 MX51_PAD_SD2_DATA3__SD2_DATA3,
116}; 132};
117 133
118static const struct imxuart_platform_data uart_pdata __initconst = { 134static const struct imxuart_platform_data uart_pdata __initconst = {
@@ -159,9 +175,11 @@ struct tsc2007_platform_data tsc2007_data = {
159 175
160static struct i2c_board_info mbimx51_i2c_devices[] = { 176static struct i2c_board_info mbimx51_i2c_devices[] = {
161 { 177 {
162 I2C_BOARD_INFO("tsc2007", 0x48), 178 I2C_BOARD_INFO("tsc2007", 0x49),
163 .irq = MBIMX51_TSC2007_IRQ, 179 .irq = MBIMX51_TSC2007_IRQ,
164 .platform_data = &tsc2007_data, 180 .platform_data = &tsc2007_data,
181 }, {
182 I2C_BOARD_INFO("tlv320aic23", 0x1a),
165 }, 183 },
166}; 184};
167 185
@@ -198,4 +216,7 @@ void __init eukrea_mbimx51_baseboard_init(void)
198 set_irq_type(MBIMX51_TSC2007_IRQ, IRQF_TRIGGER_FALLING); 216 set_irq_type(MBIMX51_TSC2007_IRQ, IRQF_TRIGGER_FALLING);
199 i2c_register_board_info(1, mbimx51_i2c_devices, 217 i2c_register_board_info(1, mbimx51_i2c_devices,
200 ARRAY_SIZE(mbimx51_i2c_devices)); 218 ARRAY_SIZE(mbimx51_i2c_devices));
219
220 imx51_add_esdhc(0, NULL);
221 imx51_add_esdhc(1, NULL);
201} 222}
diff --git a/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c
new file mode 100644
index 000000000000..2b48f5190830
--- /dev/null
+++ b/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c
@@ -0,0 +1,166 @@
1/*
2 * Copyright (C) 2010 Eric Benard - eric@eukrea.com
3 *
4 * Based on pcm970-baseboard.c which is :
5 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
19 * MA 02110-1301, USA.
20 */
21
22#include <linux/types.h>
23#include <linux/init.h>
24
25#include <linux/gpio.h>
26#include <linux/interrupt.h>
27#include <linux/irq.h>
28#include <linux/leds.h>
29#include <linux/platform_device.h>
30#include <linux/gpio_keys.h>
31#include <linux/input.h>
32#include <linux/i2c.h>
33
34#include <asm/mach-types.h>
35#include <asm/mach/arch.h>
36#include <asm/mach/time.h>
37#include <asm/mach/map.h>
38
39#include <mach/hardware.h>
40#include <mach/common.h>
41#include <mach/imx-uart.h>
42#include <mach/iomux-mx51.h>
43#include <mach/audmux.h>
44
45#include "devices-imx51.h"
46#include "devices.h"
47
48#define MBIMXSD_GPIO_3_31 IOMUX_PAD(0x554, 0x16C, 3, 0x0, 0, \
49 MX51_PAD_CTRL_1 | PAD_CTL_PUS_22K_UP)
50
51static struct pad_desc eukrea_mbimxsd_pads[] = {
52 /* LED */
53 MX51_PAD_NANDF_D10__GPIO_3_30,
54 /* SWITCH */
55 MBIMXSD_GPIO_3_31,
56 /* UART2 */
57 MX51_PAD_UART2_RXD__UART2_RXD,
58 MX51_PAD_UART2_TXD__UART2_TXD,
59 /* UART 3 */
60 MX51_PAD_UART3_RXD__UART3_RXD,
61 MX51_PAD_UART3_TXD__UART3_TXD,
62 MX51_PAD_KEY_COL4__UART3_RTS,
63 MX51_PAD_KEY_COL5__UART3_CTS,
64 /* SD */
65 MX51_PAD_SD1_CMD__SD1_CMD,
66 MX51_PAD_SD1_CLK__SD1_CLK,
67 MX51_PAD_SD1_DATA0__SD1_DATA0,
68 MX51_PAD_SD1_DATA1__SD1_DATA1,
69 MX51_PAD_SD1_DATA2__SD1_DATA2,
70 MX51_PAD_SD1_DATA3__SD1_DATA3,
71};
72
73#define GPIO_LED1 (2 * 32 + 30)
74#define GPIO_SWITCH1 (2 * 32 + 31)
75
76static struct gpio_led eukrea_mbimxsd_leds[] = {
77 {
78 .name = "led1",
79 .default_trigger = "heartbeat",
80 .active_low = 1,
81 .gpio = GPIO_LED1,
82 },
83};
84
85static struct gpio_led_platform_data eukrea_mbimxsd_led_info = {
86 .leds = eukrea_mbimxsd_leds,
87 .num_leds = ARRAY_SIZE(eukrea_mbimxsd_leds),
88};
89
90static struct platform_device eukrea_mbimxsd_leds_gpio = {
91 .name = "leds-gpio",
92 .id = -1,
93 .dev = {
94 .platform_data = &eukrea_mbimxsd_led_info,
95 },
96};
97
98static struct gpio_keys_button eukrea_mbimxsd_gpio_buttons[] = {
99 {
100 .gpio = GPIO_SWITCH1,
101 .code = BTN_0,
102 .desc = "BP1",
103 .active_low = 1,
104 .wakeup = 1,
105 },
106};
107
108static struct gpio_keys_platform_data eukrea_mbimxsd_button_data = {
109 .buttons = eukrea_mbimxsd_gpio_buttons,
110 .nbuttons = ARRAY_SIZE(eukrea_mbimxsd_gpio_buttons),
111};
112
113static struct platform_device eukrea_mbimxsd_button_device = {
114 .name = "gpio-keys",
115 .id = -1,
116 .num_resources = 0,
117 .dev = {
118 .platform_data = &eukrea_mbimxsd_button_data,
119 }
120};
121
122static struct platform_device *platform_devices[] __initdata = {
123 &eukrea_mbimxsd_leds_gpio,
124 &eukrea_mbimxsd_button_device,
125};
126
127static const struct imxuart_platform_data uart_pdata __initconst = {
128 .flags = IMXUART_HAVE_RTSCTS,
129};
130
131static struct i2c_board_info eukrea_mbimxsd_i2c_devices[] = {
132 {
133 I2C_BOARD_INFO("tlv320aic23", 0x1a),
134 },
135};
136
137/*
138 * system init for baseboard usage. Will be called by cpuimx51sd init.
139 *
140 * Add platform devices present on this baseboard and init
141 * them from CPU side as far as required to use them later on
142 */
143void __init eukrea_mbimxsd51_baseboard_init(void)
144{
145 if (mxc_iomux_v3_setup_multiple_pads(eukrea_mbimxsd_pads,
146 ARRAY_SIZE(eukrea_mbimxsd_pads)))
147 printk(KERN_ERR "error setting mbimxsd pads !\n");
148
149 imx51_add_imx_uart(1, NULL);
150 imx51_add_imx_uart(2, &uart_pdata);
151
152 imx51_add_esdhc(0, NULL);
153
154 gpio_request(GPIO_LED1, "LED1");
155 gpio_direction_output(GPIO_LED1, 1);
156 gpio_free(GPIO_LED1);
157
158 gpio_request(GPIO_SWITCH1, "SWITCH1");
159 gpio_direction_input(GPIO_SWITCH1);
160 gpio_free(GPIO_SWITCH1);
161
162 i2c_register_board_info(0, eukrea_mbimxsd_i2c_devices,
163 ARRAY_SIZE(eukrea_mbimxsd_i2c_devices));
164
165 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
166}
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index 95f8d614d4fc..64e3a64520e0 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -122,4 +122,8 @@ config ARCH_MXC_AUDMUX_V1
122config ARCH_MXC_AUDMUX_V2 122config ARCH_MXC_AUDMUX_V2
123 bool 123 bool
124 124
125config IRAM_ALLOC
126 bool
127 select GENERIC_ALLOCATOR
128
125endif 129endif
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
index bb3443f9751a..06875b4dd70f 100644
--- a/arch/arm/plat-mxc/Makefile
+++ b/arch/arm/plat-mxc/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_MXC_TZIC) += tzic.o
10 10
11obj-$(CONFIG_IMX_HAVE_IOMUX_V1) += iomux-v1.o 11obj-$(CONFIG_IMX_HAVE_IOMUX_V1) += iomux-v1.o
12obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o 12obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o
13obj-$(CONFIG_IRAM_ALLOC) += iram_alloc.o
13obj-$(CONFIG_MXC_PWM) += pwm.o 14obj-$(CONFIG_MXC_PWM) += pwm.o
14obj-$(CONFIG_USB_EHCI_MXC) += ehci.o 15obj-$(CONFIG_USB_EHCI_MXC) += ehci.o
15obj-$(CONFIG_MXC_ULPI) += ulpi.o 16obj-$(CONFIG_MXC_ULPI) += ulpi.o
diff --git a/arch/arm/plat-mxc/devices/platform-esdhc.c b/arch/arm/plat-mxc/devices/platform-esdhc.c
index 68db2a22d2cd..2605bfa0dfb0 100644
--- a/arch/arm/plat-mxc/devices/platform-esdhc.c
+++ b/arch/arm/plat-mxc/devices/platform-esdhc.c
@@ -6,26 +6,66 @@
6 * Free Software Foundation. 6 * Free Software Foundation.
7 */ 7 */
8 8
9#include <mach/hardware.h>
9#include <mach/devices-common.h> 10#include <mach/devices-common.h>
10#include <mach/esdhc.h> 11#include <mach/esdhc.h>
11 12
12struct platform_device *__init imx_add_esdhc(int id, 13#define imx_esdhc_imx_data_entry_single(soc, _id, hwid) \
13 resource_size_t iobase, resource_size_t iosize, 14 { \
14 resource_size_t irq, 15 .id = _id, \
16 .iobase = soc ## _ESDHC ## hwid ## _BASE_ADDR, \
17 .irq = soc ## _INT_ESDHC ## hwid, \
18 }
19
20#define imx_esdhc_imx_data_entry(soc, id, hwid) \
21 [id] = imx_esdhc_imx_data_entry_single(soc, id, hwid)
22
23#ifdef CONFIG_ARCH_MX25
24const struct imx_esdhc_imx_data imx25_esdhc_data[] __initconst = {
25#define imx25_esdhc_data_entry(_id, _hwid) \
26 imx_esdhc_imx_data_entry(MX25, _id, _hwid)
27 imx25_esdhc_data_entry(0, 1),
28 imx25_esdhc_data_entry(1, 2),
29};
30#endif /* ifdef CONFIG_ARCH_MX25 */
31
32#ifdef CONFIG_ARCH_MX35
33const struct imx_esdhc_imx_data imx35_esdhc_data[] __initconst = {
34#define imx35_esdhc_data_entry(_id, _hwid) \
35 imx_esdhc_imx_data_entry(MX35, _id, _hwid)
36 imx35_esdhc_data_entry(0, 1),
37 imx35_esdhc_data_entry(1, 2),
38 imx35_esdhc_data_entry(2, 3),
39};
40#endif /* ifdef CONFIG_ARCH_MX35 */
41
42#ifdef CONFIG_ARCH_MX51
43const struct imx_esdhc_imx_data imx51_esdhc_data[] __initconst = {
44#define imx51_esdhc_data_entry(_id, _hwid) \
45 imx_esdhc_imx_data_entry(MX51, _id, _hwid)
46 imx51_esdhc_data_entry(0, 1),
47 imx51_esdhc_data_entry(1, 2),
48 imx51_esdhc_data_entry(2, 3),
49 imx51_esdhc_data_entry(3, 4),
50};
51#endif /* ifdef CONFIG_ARCH_MX51 */
52
53struct platform_device *__init imx_add_esdhc(
54 const struct imx_esdhc_imx_data *data,
15 const struct esdhc_platform_data *pdata) 55 const struct esdhc_platform_data *pdata)
16{ 56{
17 struct resource res[] = { 57 struct resource res[] = {
18 { 58 {
19 .start = iobase, 59 .start = data->iobase,
20 .end = iobase + iosize - 1, 60 .end = data->iobase + SZ_16K - 1,
21 .flags = IORESOURCE_MEM, 61 .flags = IORESOURCE_MEM,
22 }, { 62 }, {
23 .start = irq, 63 .start = data->irq,
24 .end = irq, 64 .end = data->irq,
25 .flags = IORESOURCE_IRQ, 65 .flags = IORESOURCE_IRQ,
26 }, 66 },
27 }; 67 };
28 68
29 return imx_add_platform_device("sdhci-esdhc-imx", id, res, 69 return imx_add_platform_device("sdhci-esdhc-imx", data->id, res,
30 ARRAY_SIZE(res), pdata, sizeof(*pdata)); 70 ARRAY_SIZE(res), pdata, sizeof(*pdata));
31} 71}
diff --git a/arch/arm/plat-mxc/devices/platform-imx-i2c.c b/arch/arm/plat-mxc/devices/platform-imx-i2c.c
index ca988d40a3d7..679588453aad 100644
--- a/arch/arm/plat-mxc/devices/platform-imx-i2c.c
+++ b/arch/arm/plat-mxc/devices/platform-imx-i2c.c
@@ -65,6 +65,7 @@ const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst = {
65 imx_imx_i2c_data_entry(MX35, _id, _hwid, SZ_4K) 65 imx_imx_i2c_data_entry(MX35, _id, _hwid, SZ_4K)
66 imx35_imx_i2c_data_entry(0, 1), 66 imx35_imx_i2c_data_entry(0, 1),
67 imx35_imx_i2c_data_entry(1, 2), 67 imx35_imx_i2c_data_entry(1, 2),
68 imx35_imx_i2c_data_entry(2, 3),
68}; 69};
69#endif /* ifdef CONFIG_ARCH_MX35 */ 70#endif /* ifdef CONFIG_ARCH_MX35 */
70 71
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31ads.h b/arch/arm/plat-mxc/include/mach/board-mx31ads.h
new file mode 100644
index 000000000000..94b60dd47137
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/board-mx31ads.h
@@ -0,0 +1,33 @@
1/*
2 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_MXC_BOARD_MX31ADS_H__
12#define __ASM_ARCH_MXC_BOARD_MX31ADS_H__
13
14#include <mach/hardware.h>
15
16/*
17 * These symbols are used by drivers/net/cs89x0.c.
18 * This is ugly as hell, but we have to provide them until
19 * someone fixed the driver.
20 */
21
22/* Base address of PBC controller */
23#define PBC_BASE_ADDRESS MX31_CS4_BASE_ADDR_VIRT
24/* Offsets for the PBC Controller register */
25
26/* Ethernet Controller IO base address */
27#define PBC_CS8900A_IOBASE 0x020000
28
29#define MXC_EXP_IO_BASE (MXC_BOARD_IRQ_START)
30
31#define EXPIO_INT_ENET_INT (MXC_EXP_IO_BASE + 8)
32
33#endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h
index 049897880403..86d7575a564d 100644
--- a/arch/arm/plat-mxc/include/mach/devices-common.h
+++ b/arch/arm/plat-mxc/include/mach/devices-common.h
@@ -108,7 +108,11 @@ struct platform_device *__init imx_add_spi_imx(
108 const struct spi_imx_master *pdata); 108 const struct spi_imx_master *pdata);
109 109
110#include <mach/esdhc.h> 110#include <mach/esdhc.h>
111struct platform_device *__init imx_add_esdhc(int id, 111struct imx_esdhc_imx_data {
112 resource_size_t iobase, resource_size_t iosize, 112 int id;
113 resource_size_t irq, 113 resource_size_t iobase;
114 resource_size_t irq;
115};
116struct platform_device *__init imx_add_esdhc(
117 const struct imx_esdhc_imx_data *data,
114 const struct esdhc_platform_data *pdata); 118 const struct esdhc_platform_data *pdata);
diff --git a/arch/arm/plat-mxc/include/mach/eukrea-baseboards.h b/arch/arm/plat-mxc/include/mach/eukrea-baseboards.h
index 656acb45d434..a21d3313f994 100644
--- a/arch/arm/plat-mxc/include/mach/eukrea-baseboards.h
+++ b/arch/arm/plat-mxc/include/mach/eukrea-baseboards.h
@@ -28,19 +28,22 @@
28 * its own devices, it calls baseboard's init function. 28 * its own devices, it calls baseboard's init function.
29 * TODO: Add your own baseboard init function and call it from 29 * TODO: Add your own baseboard init function and call it from
30 * inside eukrea_cpuimx25_init() eukrea_cpuimx27_init() 30 * inside eukrea_cpuimx25_init() eukrea_cpuimx27_init()
31 * eukrea_cpuimx35_init() or eukrea_cpuimx51_init(). 31 * eukrea_cpuimx35_init() eukrea_cpuimx51_init()
32 * or eukrea_cpuimx51sd_init().
32 * 33 *
33 * This example here is for the development board. Refer 34 * This example here is for the development board. Refer
34 * mach-mx25/eukrea_mbimxsd-baseboard.c for cpuimx25 35 * mach-mx25/eukrea_mbimxsd-baseboard.c for cpuimx25
35 * mach-imx/eukrea_mbimx27-baseboard.c for cpuimx27 36 * mach-imx/eukrea_mbimx27-baseboard.c for cpuimx27
36 * mach-mx3/eukrea_mbimxsd-baseboard.c for cpuimx35 37 * mach-mx3/eukrea_mbimxsd-baseboard.c for cpuimx35
37 * mach-mx5/eukrea_mbimx51-baseboard.c for cpuimx51 38 * mach-mx5/eukrea_mbimx51-baseboard.c for cpuimx51
39 * mach-mx5/eukrea_mbimxsd-baseboard.c for cpuimx51sd
38 */ 40 */
39 41
40extern void eukrea_mbimxsd25_baseboard_init(void); 42extern void eukrea_mbimxsd25_baseboard_init(void);
41extern void eukrea_mbimx27_baseboard_init(void); 43extern void eukrea_mbimx27_baseboard_init(void);
42extern void eukrea_mbimxsd35_baseboard_init(void); 44extern void eukrea_mbimxsd35_baseboard_init(void);
43extern void eukrea_mbimx51_baseboard_init(void); 45extern void eukrea_mbimx51_baseboard_init(void);
46extern void eukrea_mbimxsd51_baseboard_init(void);
44 47
45#endif 48#endif
46 49
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
index 5160f1073ec9..e46b1c2836d4 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx51.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
@@ -47,6 +47,9 @@ typedef enum iomux_config {
47 PAD_CTL_SRE_FAST) 47 PAD_CTL_SRE_FAST)
48#define MX51_ECSPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \ 48#define MX51_ECSPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \
49 PAD_CTL_SRE_FAST) 49 PAD_CTL_SRE_FAST)
50#define MX51_SDHCI_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PUS_47K_UP | \
51 PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_SRE_FAST | \
52 PAD_CTL_DVS)
50 53
51#define MX51_PAD_CTRL_1 (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \ 54#define MX51_PAD_CTRL_1 (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
52 PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_HYS) 55 PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_HYS)
@@ -333,38 +336,50 @@ typedef enum iomux_config {
333#define MX51_PAD_DISP2_DAT13__DISP2_DAT13 IOMUX_PAD(0x790, 0x388, 0, 0x0, 0, NO_PAD_CTRL) 336#define MX51_PAD_DISP2_DAT13__DISP2_DAT13 IOMUX_PAD(0x790, 0x388, 0, 0x0, 0, NO_PAD_CTRL)
334#define MX51_PAD_DISP2_DAT14__DISP2_DAT14 IOMUX_PAD(0x794, 0x38C, 0, 0x0, 0, NO_PAD_CTRL) 337#define MX51_PAD_DISP2_DAT14__DISP2_DAT14 IOMUX_PAD(0x794, 0x38C, 0, 0x0, 0, NO_PAD_CTRL)
335#define MX51_PAD_DISP2_DAT15__DISP2_DAT15 IOMUX_PAD(0x798, 0x390, 0, 0x0, 0, NO_PAD_CTRL) 338#define MX51_PAD_DISP2_DAT15__DISP2_DAT15 IOMUX_PAD(0x798, 0x390, 0, 0x0, 0, NO_PAD_CTRL)
336#define MX51_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x79C, 0x394, 0, 0x0, 0, NO_PAD_CTRL) 339#define MX51_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x79C, 0x394, IOMUX_CONFIG_SION, 0x0, 0, \
340 MX51_SDHCI_PAD_CTRL)
337#define MX51_PAD_SD1_CMD__AUD5_RXFS IOMUX_PAD(0x79C, 0x394, 1, 0x8e0, 1, NO_PAD_CTRL) 341#define MX51_PAD_SD1_CMD__AUD5_RXFS IOMUX_PAD(0x79C, 0x394, 1, 0x8e0, 1, NO_PAD_CTRL)
338#define MX51_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x7A0, 0x398, 0, 0x0, 0, NO_PAD_CTRL) 342#define MX51_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x7A0, 0x398, IOMUX_CONFIG_SION, 0x0, 0, \
343 MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)
339#define MX51_PAD_SD1_CLK__AUD5_RXC IOMUX_PAD(0x7A0, 0x398, 1, 0x8dc, 1, NO_PAD_CTRL) 344#define MX51_PAD_SD1_CLK__AUD5_RXC IOMUX_PAD(0x7A0, 0x398, 1, 0x8dc, 1, NO_PAD_CTRL)
340#define MX51_PAD_SD1_DATA0__SD1_DATA0 IOMUX_PAD(0x7A4, 0x39C, 0, 0x0, 0, NO_PAD_CTRL) 345#define MX51_PAD_SD1_DATA0__SD1_DATA0 IOMUX_PAD(0x7A4, 0x39C, IOMUX_CONFIG_SION, 0x0, 0, \
346 MX51_SDHCI_PAD_CTRL)
341#define MX51_PAD_SD1_DATA0__AUD5_TXD IOMUX_PAD(0x7A4, 0x39C, 1, 0x8d8, 2, NO_PAD_CTRL) 347#define MX51_PAD_SD1_DATA0__AUD5_TXD IOMUX_PAD(0x7A4, 0x39C, 1, 0x8d8, 2, NO_PAD_CTRL)
342#define MX51_PAD_SD1_DATA1__SD1_DATA1 IOMUX_PAD(0x7A8, 0x3A0, 0, 0x0, 0, NO_PAD_CTRL) 348#define MX51_PAD_SD1_DATA1__SD1_DATA1 IOMUX_PAD(0x7A8, 0x3A0, IOMUX_CONFIG_SION, 0x0, 0, \
349 MX51_SDHCI_PAD_CTRL)
343#define MX51_PAD_SD1_DATA1__AUD5_RXD IOMUX_PAD(0x7A8, 0x3A0, 1, 0x8d4, 2, NO_PAD_CTRL) 350#define MX51_PAD_SD1_DATA1__AUD5_RXD IOMUX_PAD(0x7A8, 0x3A0, 1, 0x8d4, 2, NO_PAD_CTRL)
344#define MX51_PAD_SD1_DATA2__SD1_DATA2 IOMUX_PAD(0x7AC, 0x3A4, 0, 0x0, 0, NO_PAD_CTRL) 351#define MX51_PAD_SD1_DATA2__SD1_DATA2 IOMUX_PAD(0x7AC, 0x3A4, IOMUX_CONFIG_SION, 0x0, 0, \
352 MX51_SDHCI_PAD_CTRL)
345#define MX51_PAD_SD1_DATA2__AUD5_TXC IOMUX_PAD(0x7AC, 0x3A4, 1, 0x8e4, 2, NO_PAD_CTRL) 353#define MX51_PAD_SD1_DATA2__AUD5_TXC IOMUX_PAD(0x7AC, 0x3A4, 1, 0x8e4, 2, NO_PAD_CTRL)
346#define MX51_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x7B0, 0x3A8, 0, 0x0, 0, NO_PAD_CTRL) 354#define MX51_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x7B0, 0x3A8, IOMUX_CONFIG_SION, 0x0, 0, \
355 MX51_SDHCI_PAD_CTRL)
347#define MX51_PAD_SD1_DATA3__AUD5_TXFS IOMUX_PAD(0x7B0, 0x3A8, 1, 0x8e8, 2, NO_PAD_CTRL) 356#define MX51_PAD_SD1_DATA3__AUD5_TXFS IOMUX_PAD(0x7B0, 0x3A8, 1, 0x8e8, 2, NO_PAD_CTRL)
348#define MX51_PAD_GPIO_1_0__GPIO_1_0 IOMUX_PAD(0x7B4, 0x3AC, 1, 0x0, 0, NO_PAD_CTRL) 357#define MX51_PAD_SD2_CMD__SD2_CMD IOMUX_PAD(0x7BC, 0x3B4, IOMUX_CONFIG_SION, 0x0, 1, \
349#define MX51_PAD_GPIO_1_1__GPIO_1_1 IOMUX_PAD(0x7B8, 0x3B0, 1, 0x0, 0, NO_PAD_CTRL) 358 MX51_SDHCI_PAD_CTRL)
350#define MX51_PAD_SD2_CMD__SD2_CMD IOMUX_PAD(0x7BC, 0x3B4, 0, 0x0, 0, NO_PAD_CTRL) 359#define MX51_PAD_SD2_CLK__SD2_CLK IOMUX_PAD(0x7C0, 0x3B8, IOMUX_CONFIG_SION, 0x0, 0, \
351#define MX51_PAD_SD2_CLK__SD2_CLK IOMUX_PAD(0x7C0, 0x3B8, 0, 0x0, 0, NO_PAD_CTRL) 360 MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)
352#define MX51_PAD_SD2_DATA0__SD2_DATA0 IOMUX_PAD(0x7C4, 0x3BC, 0, 0x0, 0, NO_PAD_CTRL) 361#define MX51_PAD_SD2_DATA0__SD2_DATA0 IOMUX_PAD(0x7C4, 0x3BC, IOMUX_CONFIG_SION, 0x0, 0, \
353#define MX51_PAD_SD2_DATA1__SD2_DATA1 IOMUX_PAD(0x7C8, 0x3C0, 0, 0x0, 0, NO_PAD_CTRL) 362 MX51_SDHCI_PAD_CTRL)
354#define MX51_PAD_SD2_DATA2__SD2_DATA2 IOMUX_PAD(0x7CC, 0x3C4, 0, 0x0, 0, NO_PAD_CTRL) 363#define MX51_PAD_SD2_DATA1__SD2_DATA1 IOMUX_PAD(0x7C8, 0x3C0, IOMUX_CONFIG_SION, 0x0, 0, \
355#define MX51_PAD_SD2_DATA3__SD2_DATA3 IOMUX_PAD(0x7D0, 0x3C8, 0, 0x0, 0, NO_PAD_CTRL) 364 MX51_SDHCI_PAD_CTRL)
356#define MX51_PAD_GPIO_1_2__GPIO_1_2 IOMUX_PAD(0x7D4, 0x3CC, 0, 0x0, 0, NO_PAD_CTRL) 365#define MX51_PAD_SD2_DATA2__SD2_DATA2 IOMUX_PAD(0x7CC, 0x3C4, IOMUX_CONFIG_SION, 0x0, 0, \
366 MX51_SDHCI_PAD_CTRL)
367#define MX51_PAD_SD2_DATA3__SD2_DATA3 IOMUX_PAD(0x7D0, 0x3C8, IOMUX_CONFIG_SION, 0x0, 0, \
368 MX51_SDHCI_PAD_CTRL)
369#define MX51_PAD_GPIO_1_0__GPIO_1_0 IOMUX_PAD(0x7B4, 0x3AC, 1, 0x0, 0, MX51_GPIO_PAD_CTRL)
370#define MX51_PAD_GPIO_1_1__GPIO_1_1 IOMUX_PAD(0x7B8, 0x3B0, 1, 0x0, 0, MX51_GPIO_PAD_CTRL)
371#define MX51_PAD_GPIO_1_2__GPIO_1_2 IOMUX_PAD(0x7D4, 0x3CC, 1, 0x0, 0, MX51_GPIO_PAD_CTRL)
357#define MX51_PAD_GPIO_1_2__I2C2_SCL IOMUX_PAD(0x7D4, 0x3CC, (2 | IOMUX_CONFIG_SION), \ 372#define MX51_PAD_GPIO_1_2__I2C2_SCL IOMUX_PAD(0x7D4, 0x3CC, (2 | IOMUX_CONFIG_SION), \
358 0x9b8, 3, MX51_I2C_PAD_CTRL) 373 0x9b8, 3, MX51_I2C_PAD_CTRL)
359#define MX51_PAD_GPIO_1_3__GPIO_1_3 IOMUX_PAD(0x7D8, 0x3D0, 0, 0x0, 0, NO_PAD_CTRL) 374#define MX51_PAD_GPIO_1_3__GPIO_1_3 IOMUX_PAD(0x7D8, 0x3D0, 1, 0x0, 0, MX51_GPIO_PAD_CTRL)
360#define MX51_PAD_GPIO_1_3__I2C2_SDA IOMUX_PAD(0x7D8, 0x3D0, (2 | IOMUX_CONFIG_SION), \ 375#define MX51_PAD_GPIO_1_3__I2C2_SDA IOMUX_PAD(0x7D8, 0x3D0, (2 | IOMUX_CONFIG_SION), \
361 0x9bc, 3, MX51_I2C_PAD_CTRL) 376 0x9bc, 3, MX51_I2C_PAD_CTRL)
362#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0, 0, NO_PAD_CTRL) 377#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0, 0, NO_PAD_CTRL)
363#define MX51_PAD_GPIO_1_4__GPIO_1_4 IOMUX_PAD(0x804, 0x3D8, 0, 0x0, 0, NO_PAD_CTRL) 378#define MX51_PAD_GPIO_1_4__GPIO_1_4 IOMUX_PAD(0x804, 0x3D8, 1, 0x0, 0, MX51_GPIO_PAD_CTRL)
364#define MX51_PAD_GPIO_1_5__GPIO_1_5 IOMUX_PAD(0x808, 0x3DC, 0, 0x0, 0, NO_PAD_CTRL) 379#define MX51_PAD_GPIO_1_5__GPIO_1_5 IOMUX_PAD(0x808, 0x3DC, 1, 0x0, 0, MX51_GPIO_PAD_CTRL)
365#define MX51_PAD_GPIO_1_6__GPIO_1_6 IOMUX_PAD(0x80C, 0x3E0, 0, 0x0, 0, MX51_GPIO_PAD_CTRL) 380#define MX51_PAD_GPIO_1_6__GPIO_1_6 IOMUX_PAD(0x80C, 0x3E0, 1, 0x0, 0, MX51_GPIO_PAD_CTRL)
366#define MX51_PAD_GPIO_1_7__GPIO_1_7 IOMUX_PAD(0x810, 0x3E4, 0, 0x0, 0, MX51_GPIO_PAD_CTRL) 381#define MX51_PAD_GPIO_1_7__GPIO_1_7 IOMUX_PAD(0x810, 0x3E4, 1, 0x0, 0, MX51_GPIO_PAD_CTRL)
367#define MX51_PAD_GPIO_1_8__GPIO_1_8 IOMUX_PAD(0x814, 0x3E8, 0, 0x0, 1, MX51_GPIO_PAD_CTRL) 382#define MX51_PAD_GPIO_1_8__GPIO_1_8 IOMUX_PAD(0x814, 0x3E8, 1, 0x0, 0, MX51_GPIO_PAD_CTRL)
368#define MX51_PAD_GPIO_1_9__GPIO_1_9 IOMUX_PAD(0x818, 0x3EC, 0, 0x0, 0, NO_PAD_CTRL) 383#define MX51_PAD_GPIO_1_9__GPIO_1_9 IOMUX_PAD(0x818, 0x3EC, 1, 0x0, 0, MX51_GPIO_PAD_CTRL)
369 384
370#endif /* __MACH_IOMUX_MX51_H__ */ 385#endif /* __MACH_IOMUX_MX51_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/iram.h b/arch/arm/plat-mxc/include/mach/iram.h
new file mode 100644
index 000000000000..022690c33702
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/iram.h
@@ -0,0 +1,41 @@
1/*
2 * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19#include <linux/errno.h>
20
21#ifdef CONFIG_IRAM_ALLOC
22
23int __init iram_init(unsigned long base, unsigned long size);
24void __iomem *iram_alloc(unsigned int size, unsigned long *dma_addr);
25void iram_free(unsigned long dma_addr, unsigned int size);
26
27#else
28
29static inline int __init iram_init(unsigned long base, unsigned long size)
30{
31 return -ENOMEM;
32}
33
34static inline void __iomem *iram_alloc(unsigned int size, unsigned long *dma_addr)
35{
36 return NULL;
37}
38
39static inline void iram_free(unsigned long base, unsigned long size) {}
40
41#endif
diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h
index 153dd1b2a473..cf46a45b0d4e 100644
--- a/arch/arm/plat-mxc/include/mach/mx25.h
+++ b/arch/arm/plat-mxc/include/mach/mx25.h
@@ -54,6 +54,7 @@
54#define MX25_ESDHC2_BASE_ADDR 0x53fb8000 54#define MX25_ESDHC2_BASE_ADDR 0x53fb8000
55#define MX25_LCDC_BASE_ADDR 0x53fbc000 55#define MX25_LCDC_BASE_ADDR 0x53fbc000
56#define MX25_KPP_BASE_ADDR 0x43fa8000 56#define MX25_KPP_BASE_ADDR 0x43fa8000
57#define MX25_SDMA_BASE_ADDR 0x53fd4000
57#define MX25_OTG_BASE_ADDR 0x53ff4000 58#define MX25_OTG_BASE_ADDR 0x53ff4000
58#define MX25_CSI_BASE_ADDR 0x53ff8000 59#define MX25_CSI_BASE_ADDR 0x53ff8000
59 60
@@ -61,8 +62,8 @@
61#define MX25_INT_I2C1 3 62#define MX25_INT_I2C1 3
62#define MX25_INT_I2C2 4 63#define MX25_INT_I2C2 4
63#define MX25_INT_UART4 5 64#define MX25_INT_UART4 5
64#define MX25_INT_MMC_SDHC2 8 65#define MX25_INT_ESDHC2 8
65#define MX25_INT_MMC_SDHC1 9 66#define MX25_INT_ESDHC1 9
66#define MX25_INT_I2C3 10 67#define MX25_INT_I2C3 10
67#define MX25_INT_SSI2 11 68#define MX25_INT_SSI2 11
68#define MX25_INT_SSI1 12 69#define MX25_INT_SSI1 12
@@ -74,6 +75,7 @@
74#define MX25_INT_DRYICE 25 75#define MX25_INT_DRYICE 25
75#define MX25_INT_UART2 32 76#define MX25_INT_UART2 32
76#define MX25_INT_NFC 33 77#define MX25_INT_NFC 33
78#define MX25_INT_SDMA 34
77#define MX25_INT_LCDC 39 79#define MX25_INT_LCDC 39
78#define MX25_INT_UART5 40 80#define MX25_INT_UART5 40
79#define MX25_INT_CAN1 43 81#define MX25_INT_CAN1 43
diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h
index cb071b7b17e5..ff905cb32458 100644
--- a/arch/arm/plat-mxc/include/mach/mx35.h
+++ b/arch/arm/plat-mxc/include/mach/mx35.h
@@ -128,9 +128,9 @@
128#define MX35_INT_I2C3 3 128#define MX35_INT_I2C3 3
129#define MX35_INT_I2C2 4 129#define MX35_INT_I2C2 4
130#define MX35_INT_RTIC 6 130#define MX35_INT_RTIC 6
131#define MX35_INT_MMC_SDHC1 7 131#define MX35_INT_ESDHC1 7
132#define MX35_INT_MMC_SDHC2 8 132#define MX35_INT_ESDHC2 8
133#define MX35_INT_MMC_SDHC3 9 133#define MX35_INT_ESDHC3 9
134#define MX35_INT_I2C1 10 134#define MX35_INT_I2C1 10
135#define MX35_INT_SSI1 11 135#define MX35_INT_SSI1 11
136#define MX35_INT_SSI2 12 136#define MX35_INT_SSI2 12
diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h
index c54b5c32d82e..2af7a1056fc1 100644
--- a/arch/arm/plat-mxc/include/mach/mx51.h
+++ b/arch/arm/plat-mxc/include/mach/mx51.h
@@ -64,13 +64,13 @@
64#define MX51_SPBA0_BASE_ADDR_VIRT 0xfb100000 64#define MX51_SPBA0_BASE_ADDR_VIRT 0xfb100000
65#define MX51_SPBA0_SIZE SZ_1M 65#define MX51_SPBA0_SIZE SZ_1M
66 66
67#define MX51_MMC_SDHC1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x04000) 67#define MX51_ESDHC1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x04000)
68#define MX51_MMC_SDHC2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x08000) 68#define MX51_ESDHC2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x08000)
69#define MX51_UART3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x0c000) 69#define MX51_UART3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x0c000)
70#define MX51_ECSPI1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x10000) 70#define MX51_ECSPI1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x10000)
71#define MX51_SSI2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x14000) 71#define MX51_SSI2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x14000)
72#define MX51_MMC_SDHC3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x20000) 72#define MX51_ESDHC3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x20000)
73#define MX51_MMC_SDHC4_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x24000) 73#define MX51_ESDHC4_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x24000)
74#define MX51_SPDIF_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x28000) 74#define MX51_SPDIF_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x28000)
75#define MX51_ATA_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x30000) 75#define MX51_ATA_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x30000)
76#define MX51_SLIM_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x34000) 76#define MX51_SLIM_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x34000)
@@ -280,10 +280,10 @@
280 */ 280 */
281#define MX51_MXC_INT_BASE 0 281#define MX51_MXC_INT_BASE 0
282#define MX51_MXC_INT_RESV0 0 282#define MX51_MXC_INT_RESV0 0
283#define MX51_MXC_INT_MMC_SDHC1 1 283#define MX51_INT_ESDHC1 1
284#define MX51_MXC_INT_MMC_SDHC2 2 284#define MX51_INT_ESDHC2 2
285#define MX51_MXC_INT_MMC_SDHC3 3 285#define MX51_INT_ESDHC3 3
286#define MX51_MXC_INT_MMC_SDHC4 4 286#define MX51_INT_ESDHC4 4
287#define MX51_MXC_INT_RESV5 5 287#define MX51_MXC_INT_RESV5 5
288#define MX51_INT_SDMA 6 288#define MX51_INT_SDMA 6
289#define MX51_MXC_INT_IOMUX 7 289#define MX51_MXC_INT_IOMUX 7
diff --git a/arch/arm/plat-mxc/include/mach/system.h b/arch/arm/plat-mxc/include/mach/system.h
index 4acd1143a9bd..95be51bfe9a9 100644
--- a/arch/arm/plat-mxc/include/mach/system.h
+++ b/arch/arm/plat-mxc/include/mach/system.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * Copyright (C) 1999 ARM Limited 2 * Copyright (C) 1999 ARM Limited
3 * Copyright (C) 2000 Deep Blue Solutions Ltd 3 * Copyright (C) 2000 Deep Blue Solutions Ltd
4 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. 4 * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by 7 * it under the terms of the GNU General Public License as published by
@@ -28,8 +28,34 @@ static inline void arch_idle(void)
28 mxc91231_prepare_idle(); 28 mxc91231_prepare_idle();
29 } 29 }
30#endif 30#endif
31 31 /* fix i.MX31 errata TLSbo65953 and i.MX35 errata ENGcm09472 */
32 cpu_do_idle(); 32 if (cpu_is_mx31() || cpu_is_mx35()) {
33 unsigned long reg = 0;
34 __asm__ __volatile__(
35 /* disable I and D cache */
36 "mrc p15, 0, %0, c1, c0, 0\n"
37 "bic %0, %0, #0x00001000\n"
38 "bic %0, %0, #0x00000004\n"
39 "mcr p15, 0, %0, c1, c0, 0\n"
40 /* invalidate I cache */
41 "mov %0, #0\n"
42 "mcr p15, 0, %0, c7, c5, 0\n"
43 /* clear and invalidate D cache */
44 "mov %0, #0\n"
45 "mcr p15, 0, %0, c7, c14, 0\n"
46 /* WFI */
47 "mov %0, #0\n"
48 "mcr p15, 0, %0, c7, c0, 4\n"
49 "nop\n" "nop\n" "nop\n" "nop\n"
50 "nop\n" "nop\n" "nop\n"
51 /* enable I and D cache */
52 "mrc p15, 0, %0, c1, c0, 0\n"
53 "orr %0, %0, #0x00001000\n"
54 "orr %0, %0, #0x00000004\n"
55 "mcr p15, 0, %0, c1, c0, 0\n"
56 : "=r" (reg));
57 } else
58 cpu_do_idle();
33} 59}
34 60
35void arch_reset(char mode, const char *cmd); 61void arch_reset(char mode, const char *cmd);
diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h
index d9bd37e4667a..9dd9c2085aad 100644
--- a/arch/arm/plat-mxc/include/mach/uncompress.h
+++ b/arch/arm/plat-mxc/include/mach/uncompress.h
@@ -99,6 +99,7 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id)
99 uart_base = MX3X_UART2_BASE_ADDR; 99 uart_base = MX3X_UART2_BASE_ADDR;
100 break; 100 break;
101 case MACH_TYPE_MX51_BABBAGE: 101 case MACH_TYPE_MX51_BABBAGE:
102 case MACH_TYPE_EUKREA_CPUIMX51SD:
102 uart_base = MX51_UART1_BASE_ADDR; 103 uart_base = MX51_UART1_BASE_ADDR;
103 break; 104 break;
104 default: 105 default:
diff --git a/arch/arm/plat-mxc/iram_alloc.c b/arch/arm/plat-mxc/iram_alloc.c
new file mode 100644
index 000000000000..074c3869626a
--- /dev/null
+++ b/arch/arm/plat-mxc/iram_alloc.c
@@ -0,0 +1,73 @@
1/*
2 * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19
20#include <linux/kernel.h>
21#include <linux/io.h>
22#include <linux/module.h>
23#include <linux/spinlock.h>
24#include <linux/genalloc.h>
25#include <mach/iram.h>
26
27static unsigned long iram_phys_base;
28static void __iomem *iram_virt_base;
29static struct gen_pool *iram_pool;
30
31static inline void __iomem *iram_phys_to_virt(unsigned long p)
32{
33 return iram_virt_base + (p - iram_phys_base);
34}
35
36void __iomem *iram_alloc(unsigned int size, unsigned long *dma_addr)
37{
38 if (!iram_pool)
39 return NULL;
40
41 *dma_addr = gen_pool_alloc(iram_pool, size);
42 pr_debug("iram alloc - %dB@0x%lX\n", size, *dma_addr);
43 if (!*dma_addr)
44 return NULL;
45 return iram_phys_to_virt(*dma_addr);
46}
47EXPORT_SYMBOL(iram_alloc);
48
49void iram_free(unsigned long addr, unsigned int size)
50{
51 if (!iram_pool)
52 return;
53
54 gen_pool_free(iram_pool, addr, size);
55}
56EXPORT_SYMBOL(iram_free);
57
58int __init iram_init(unsigned long base, unsigned long size)
59{
60 iram_phys_base = base;
61
62 iram_pool = gen_pool_create(PAGE_SHIFT, -1);
63 if (!iram_pool)
64 return -ENOMEM;
65
66 gen_pool_add(iram_pool, base, size, -1);
67 iram_virt_base = ioremap(iram_phys_base, size);
68 if (!iram_virt_base)
69 return -EIO;
70
71 pr_debug("i.MX IRAM pool: %ld KB@0x%p\n", size / 1024, iram_virt_base);
72 return 0;
73}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-12 03:37:58 -0500