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-rw-r--r--arch/arm/mach-msm/gpio-v2.c4
-rw-r--r--arch/arm/mach-msm/gpio.c4
-rw-r--r--arch/arm/mach-msm/irq-vic.c4
-rw-r--r--arch/arm/mach-msm/irq.c4
-rw-r--r--arch/arm/mach-msm/sirc.c4
5 files changed, 10 insertions, 10 deletions
diff --git a/arch/arm/mach-msm/gpio-v2.c b/arch/arm/mach-msm/gpio-v2.c
index 394689a92198..e00e4dee4274 100644
--- a/arch/arm/mach-msm/gpio-v2.c
+++ b/arch/arm/mach-msm/gpio-v2.c
@@ -275,14 +275,14 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int flow_type)
275 275
276 if (flow_type & IRQ_TYPE_EDGE_BOTH) { 276 if (flow_type & IRQ_TYPE_EDGE_BOTH) {
277 bits |= BIT(INTR_DECT_CTL); 277 bits |= BIT(INTR_DECT_CTL);
278 irq_desc[irq].handle_irq = handle_edge_irq; 278 __irq_set_handler_locked(d->irq, handle_edge_irq);
279 if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) 279 if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
280 __set_bit(gpio, msm_gpio.dual_edge_irqs); 280 __set_bit(gpio, msm_gpio.dual_edge_irqs);
281 else 281 else
282 __clear_bit(gpio, msm_gpio.dual_edge_irqs); 282 __clear_bit(gpio, msm_gpio.dual_edge_irqs);
283 } else { 283 } else {
284 bits &= ~BIT(INTR_DECT_CTL); 284 bits &= ~BIT(INTR_DECT_CTL);
285 irq_desc[irq].handle_irq = handle_level_irq; 285 __irq_set_handler_locked(d->irq, handle_level_irq);
286 __clear_bit(gpio, msm_gpio.dual_edge_irqs); 286 __clear_bit(gpio, msm_gpio.dual_edge_irqs);
287 } 287 }
288 288
diff --git a/arch/arm/mach-msm/gpio.c b/arch/arm/mach-msm/gpio.c
index 176af9dcb8ee..448f2677051b 100644
--- a/arch/arm/mach-msm/gpio.c
+++ b/arch/arm/mach-msm/gpio.c
@@ -293,10 +293,10 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int flow_type)
293 val = readl(msm_chip->regs.int_edge); 293 val = readl(msm_chip->regs.int_edge);
294 if (flow_type & IRQ_TYPE_EDGE_BOTH) { 294 if (flow_type & IRQ_TYPE_EDGE_BOTH) {
295 writel(val | mask, msm_chip->regs.int_edge); 295 writel(val | mask, msm_chip->regs.int_edge);
296 irq_desc[d->irq].handle_irq = handle_edge_irq; 296 __irq_set_handler_locked(d->irq, handle_edge_irq);
297 } else { 297 } else {
298 writel(val & ~mask, msm_chip->regs.int_edge); 298 writel(val & ~mask, msm_chip->regs.int_edge);
299 irq_desc[d->irq].handle_irq = handle_level_irq; 299 __irq_set_handler_locked(d->irq, handle_level_irq);
300 } 300 }
301 if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { 301 if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
302 msm_chip->both_edge_detect |= mask; 302 msm_chip->both_edge_detect |= mask;
diff --git a/arch/arm/mach-msm/irq-vic.c b/arch/arm/mach-msm/irq-vic.c
index 68c28bbdc969..84b8103b4686 100644
--- a/arch/arm/mach-msm/irq-vic.c
+++ b/arch/arm/mach-msm/irq-vic.c
@@ -313,11 +313,11 @@ static int msm_irq_set_type(struct irq_data *d, unsigned int flow_type)
313 type = msm_irq_shadow_reg[index].int_type; 313 type = msm_irq_shadow_reg[index].int_type;
314 if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) { 314 if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
315 type |= b; 315 type |= b;
316 irq_desc[d->irq].handle_irq = handle_edge_irq; 316 __irq_set_handler_locked(d->irq, handle_edge_irq);
317 } 317 }
318 if (flow_type & (IRQF_TRIGGER_HIGH | IRQF_TRIGGER_LOW)) { 318 if (flow_type & (IRQF_TRIGGER_HIGH | IRQF_TRIGGER_LOW)) {
319 type &= ~b; 319 type &= ~b;
320 irq_desc[d->irq].handle_irq = handle_level_irq; 320 __irq_set_handler_locked(d->irq, handle_level_irq);
321 } 321 }
322 writel(type, treg); 322 writel(type, treg);
323 msm_irq_shadow_reg[index].int_type = type; 323 msm_irq_shadow_reg[index].int_type = type;
diff --git a/arch/arm/mach-msm/irq.c b/arch/arm/mach-msm/irq.c
index 0b27d899f40e..8033c6aab974 100644
--- a/arch/arm/mach-msm/irq.c
+++ b/arch/arm/mach-msm/irq.c
@@ -100,11 +100,11 @@ static int msm_irq_set_type(struct irq_data *d, unsigned int flow_type)
100 100
101 if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) { 101 if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
102 writel(readl(treg) | b, treg); 102 writel(readl(treg) | b, treg);
103 irq_desc[d->irq].handle_irq = handle_edge_irq; 103 __irq_set_handler_locked(d->irq, handle_edge_irq);
104 } 104 }
105 if (flow_type & (IRQF_TRIGGER_HIGH | IRQF_TRIGGER_LOW)) { 105 if (flow_type & (IRQF_TRIGGER_HIGH | IRQF_TRIGGER_LOW)) {
106 writel(readl(treg) & (~b), treg); 106 writel(readl(treg) & (~b), treg);
107 irq_desc[d->irq].handle_irq = handle_level_irq; 107 __irq_set_handler_locked(d->irq, handle_level_irq);
108 } 108 }
109 return 0; 109 return 0;
110} 110}
diff --git a/arch/arm/mach-msm/sirc.c b/arch/arm/mach-msm/sirc.c
index 11b54c7aeb09..cfab1c472fbc 100644
--- a/arch/arm/mach-msm/sirc.c
+++ b/arch/arm/mach-msm/sirc.c
@@ -105,10 +105,10 @@ static int sirc_irq_set_type(struct irq_data *d, unsigned int flow_type)
105 val = readl(sirc_regs.int_type); 105 val = readl(sirc_regs.int_type);
106 if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) { 106 if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
107 val |= mask; 107 val |= mask;
108 irq_desc[d->irq].handle_irq = handle_edge_irq; 108 __irq_set_handler_locked(d->irq, handle_edge_irq);
109 } else { 109 } else {
110 val &= ~mask; 110 val &= ~mask;
111 irq_desc[d->irq].handle_irq = handle_level_irq; 111 __irq_set_handler_locked(d->irq, handle_level_irq);
112 } 112 }
113 113
114 writel(val, sirc_regs.int_type); 114 writel(val, sirc_regs.int_type);