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-rw-r--r--arch/arm/Kconfig26
-rw-r--r--arch/arm/boot/compressed/mmcif-sh7372.c2
-rw-r--r--arch/arm/boot/compressed/sdhi-sh7372.c2
-rw-r--r--arch/arm/boot/dts/at91sam9g20.dtsi119
-rw-r--r--arch/arm/boot/dts/at91sam9g45.dtsi106
-rw-r--r--arch/arm/boot/dts/at91sam9m10g45ek.dts35
-rw-r--r--arch/arm/boot/dts/imx51-babbage.dts135
-rw-r--r--arch/arm/boot/dts/imx51.dtsi246
-rw-r--r--arch/arm/boot/dts/imx53-ard.dts113
-rw-r--r--arch/arm/boot/dts/imx53-evk.dts120
-rw-r--r--arch/arm/boot/dts/imx53-qsb.dts125
-rw-r--r--arch/arm/boot/dts/imx53-smd.dts169
-rw-r--r--arch/arm/boot/dts/imx53.dtsi301
-rw-r--r--arch/arm/boot/dts/tegra-harmony.dts12
-rw-r--r--arch/arm/boot/dts/tegra-seaboard.dts6
-rw-r--r--arch/arm/boot/dts/usb_a9g20.dts30
-rw-r--r--arch/arm/common/vic.c1
-rw-r--r--arch/arm/include/asm/futex.h34
-rw-r--r--arch/arm/include/asm/hardware/cache-l2x0.h11
-rw-r--r--arch/arm/include/asm/localtimer.h2
-rw-r--r--arch/arm/include/asm/pmu.h10
-rw-r--r--arch/arm/include/asm/unistd.h4
-rw-r--r--arch/arm/kernel/perf_event_v7.c4
-rw-r--r--arch/arm/kernel/pmu.c26
-rw-r--r--arch/arm/kernel/relocate_kernel.S3
-rw-r--r--arch/arm/kernel/setup.c15
-rw-r--r--arch/arm/kernel/smp_scu.c10
-rw-r--r--arch/arm/kernel/smp_twd.c4
-rw-r--r--arch/arm/kernel/vmlinux.lds.S15
-rw-r--r--arch/arm/mach-at91/Kconfig11
-rw-r--r--arch/arm/mach-at91/Makefile3
-rw-r--r--arch/arm/mach-at91/Makefile.boot2
-rw-r--r--arch/arm/mach-at91/at91sam9260.c8
-rw-r--r--arch/arm/mach-at91/at91sam9261.c2
-rw-r--r--arch/arm/mach-at91/at91sam9g45.c6
-rw-r--r--arch/arm/mach-at91/board-dt.c123
-rw-r--r--arch/arm/mach-cns3xxx/include/mach/entry-macro.S1
-rw-r--r--arch/arm/mach-cns3xxx/include/mach/system.h1
-rw-r--r--arch/arm/mach-cns3xxx/include/mach/uncompress.h1
-rw-r--r--arch/arm/mach-cns3xxx/pcie.c2
-rw-r--r--arch/arm/mach-davinci/board-da850-evm.c28
-rw-r--r--arch/arm/mach-davinci/include/mach/psc.h2
-rw-r--r--arch/arm/mach-davinci/sleep.S6
-rw-r--r--arch/arm/mach-dove/common.c2
-rw-r--r--arch/arm/mach-ep93xx/include/mach/ts72xx.h26
-rw-r--r--arch/arm/mach-exynos4/clock.c10
-rw-r--r--arch/arm/mach-exynos4/cpu.c11
-rw-r--r--arch/arm/mach-exynos4/include/mach/irqs.h5
-rw-r--r--arch/arm/mach-exynos4/include/mach/regs-pmu.h2
-rw-r--r--arch/arm/mach-exynos4/irq-eint.c7
-rw-r--r--arch/arm/mach-exynos4/mach-universal_c210.c4
-rw-r--r--arch/arm/mach-exynos4/mct.c10
-rw-r--r--arch/arm/mach-exynos4/platsmp.c2
-rw-r--r--arch/arm/mach-exynos4/setup-keypad.c11
-rw-r--r--arch/arm/mach-exynos4/setup-usb-phy.c2
-rw-r--r--arch/arm/mach-footbridge/Kconfig1
-rw-r--r--arch/arm/mach-footbridge/dc21285.c1
-rw-r--r--arch/arm/mach-imx/mach-cpuimx27.c2
-rw-r--r--arch/arm/mach-imx/mach-cpuimx35.c2
-rw-r--r--arch/arm/mach-imx/mach-eukrea_cpuimx25.c2
-rw-r--r--arch/arm/mach-integrator/integrator_ap.c8
-rw-r--r--arch/arm/mach-integrator/pci_v3.c2
-rw-r--r--arch/arm/mach-mx5/Kconfig21
-rw-r--r--arch/arm/mach-mx5/Makefile3
-rw-r--r--arch/arm/mach-mx5/board-mx51_babbage.c9
-rw-r--r--arch/arm/mach-mx5/board-mx53_ard.c12
-rw-r--r--arch/arm/mach-mx5/board-mx53_evk.c9
-rw-r--r--arch/arm/mach-mx5/board-mx53_loco.c9
-rw-r--r--arch/arm/mach-mx5/board-mx53_smd.c9
-rw-r--r--arch/arm/mach-mx5/clock-mx51-mx53.c39
-rw-r--r--arch/arm/mach-mx5/imx51-dt.c116
-rw-r--r--arch/arm/mach-mx5/imx53-dt.c126
-rw-r--r--arch/arm/mach-omap2/board-2430sdp.c3
-rw-r--r--arch/arm/mach-omap2/clock3xxx_data.c2
-rw-r--r--arch/arm/mach-omap2/clock44xx_data.c10
-rw-r--r--arch/arm/mach-omap2/clockdomain.c2
-rw-r--r--arch/arm/mach-omap2/hsmmc.c12
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2430_data.c1
-rw-r--r--arch/arm/mach-omap2/pm.c2
-rw-r--r--arch/arm/mach-omap2/powerdomain.c25
-rw-r--r--arch/arm/mach-omap2/usb-musb.c3
-rw-r--r--arch/arm/mach-orion5x/dns323-setup.c2
-rw-r--r--arch/arm/mach-orion5x/pci.c1
-rw-r--r--arch/arm/mach-prima2/clock.c1
-rw-r--r--arch/arm/mach-prima2/irq.c1
-rw-r--r--arch/arm/mach-prima2/rstc.c1
-rw-r--r--arch/arm/mach-prima2/timer.c1
-rw-r--r--arch/arm/mach-realview/include/mach/system.h1
-rw-r--r--arch/arm/mach-s3c2410/s3c2410.c2
-rw-r--r--arch/arm/mach-s3c2412/s3c2412.c2
-rw-r--r--arch/arm/mach-s3c2416/s3c2416.c2
-rw-r--r--arch/arm/mach-s3c2440/s3c2440.c2
-rw-r--r--arch/arm/mach-s3c2440/s3c2442.c2
-rw-r--r--arch/arm/mach-s3c2443/clock.c2
-rw-r--r--arch/arm/mach-s3c64xx/mach-smdk6410.c39
-rw-r--r--arch/arm/mach-s3c64xx/pm.c1
-rw-r--r--arch/arm/mach-s5p64x0/irq-eint.c2
-rw-r--r--arch/arm/mach-s5pv210/clock.c6
-rw-r--r--arch/arm/mach-s5pv210/pm.c2
-rw-r--r--arch/arm/mach-shmobile/board-ag5evm.c3
-rw-r--r--arch/arm/mach-shmobile/board-mackerel.c4
-rw-r--r--arch/arm/mach-shmobile/clock-sh7372.c29
-rw-r--r--arch/arm/mach-shmobile/clock-sh73a0.c2
-rw-r--r--arch/arm/mach-shmobile/include/mach/sh7372.h4
-rw-r--r--arch/arm/mach-shmobile/intc-sh7372.c7
-rw-r--r--arch/arm/mach-shmobile/setup-sh7372.c176
-rw-r--r--arch/arm/mach-tegra/cpu-tegra.c1
-rw-r--r--arch/arm/mach-ux500/Kconfig1
-rw-r--r--arch/arm/mach-vexpress/v2m.c7
-rw-r--r--arch/arm/mm/abort-macro.S2
-rw-r--r--arch/arm/mm/cache-l2x0.c21
-rw-r--r--arch/arm/mm/cache-v7.S20
-rw-r--r--arch/arm/mm/dma-mapping.c2
-rw-r--r--arch/arm/mm/init.c9
-rw-r--r--arch/arm/mm/proc-arm920.S2
-rw-r--r--arch/arm/mm/proc-arm926.S2
-rw-r--r--arch/arm/mm/proc-sa1100.S10
-rw-r--r--arch/arm/mm/proc-v6.S16
-rw-r--r--arch/arm/mm/proc-v7.S6
-rw-r--r--arch/arm/mm/proc-xsc3.S6
-rw-r--r--arch/arm/plat-mxc/include/mach/common.h8
-rw-r--r--arch/arm/plat-omap/omap_device.c3
-rw-r--r--arch/arm/plat-s5p/clock.c2
-rw-r--r--arch/arm/plat-s5p/irq-gpioint.c21
-rw-r--r--arch/arm/plat-samsung/clock.c11
-rw-r--r--arch/arm/plat-samsung/include/plat/backlight.h2
-rw-r--r--arch/arm/plat-samsung/include/plat/clock.h8
-rw-r--r--arch/arm/plat-samsung/include/plat/watchdog-reset.h10
-rw-r--r--arch/arm/plat-samsung/irq-vic-timer.c5
-rw-r--r--arch/arm/tools/mach-types6
130 files changed, 2631 insertions, 250 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 5ebc5d922ea1..3146ed3f6eca 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1271,6 +1271,32 @@ config ARM_ERRATA_754327
1271 This workaround defines cpu_relax() as smp_mb(), preventing correctly 1271 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1272 written polling loops from denying visibility of updates to memory. 1272 written polling loops from denying visibility of updates to memory.
1273 1273
1274config ARM_ERRATA_364296
1275 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1276 depends on CPU_V6 && !SMP
1277 help
1278 This options enables the workaround for the 364296 ARM1136
1279 r0p2 erratum (possible cache data corruption with
1280 hit-under-miss enabled). It sets the undocumented bit 31 in
1281 the auxiliary control register and the FI bit in the control
1282 register, thus disabling hit-under-miss without putting the
1283 processor into full low interrupt latency mode. ARM11MPCore
1284 is not affected.
1285
1286config ARM_ERRATA_764369
1287 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1288 depends on CPU_V7 && SMP
1289 help
1290 This option enables the workaround for erratum 764369
1291 affecting Cortex-A9 MPCore with two or more processors (all
1292 current revisions). Under certain timing circumstances, a data
1293 cache line maintenance operation by MVA targeting an Inner
1294 Shareable memory region may fail to proceed up to either the
1295 Point of Coherency or to the Point of Unification of the
1296 system. This workaround adds a DSB instruction before the
1297 relevant cache maintenance functions and sets a specific bit
1298 in the diagnostic control register of the SCU.
1299
1274endmenu 1300endmenu
1275 1301
1276source "arch/arm/common/Kconfig" 1302source "arch/arm/common/Kconfig"
diff --git a/arch/arm/boot/compressed/mmcif-sh7372.c b/arch/arm/boot/compressed/mmcif-sh7372.c
index b6f61d9a5a1b..672ae95db5c3 100644
--- a/arch/arm/boot/compressed/mmcif-sh7372.c
+++ b/arch/arm/boot/compressed/mmcif-sh7372.c
@@ -82,7 +82,7 @@ asmlinkage void mmc_loader(unsigned char *buf, unsigned long len)
82 82
83 83
84 /* Disable clock to MMC hardware block */ 84 /* Disable clock to MMC hardware block */
85 __raw_writel(__raw_readl(SMSTPCR3) & (1 << 12), SMSTPCR3); 85 __raw_writel(__raw_readl(SMSTPCR3) | (1 << 12), SMSTPCR3);
86 86
87 mmc_update_progress(MMC_PROGRESS_DONE); 87 mmc_update_progress(MMC_PROGRESS_DONE);
88} 88}
diff --git a/arch/arm/boot/compressed/sdhi-sh7372.c b/arch/arm/boot/compressed/sdhi-sh7372.c
index d403a8b24d7f..d279294f2381 100644
--- a/arch/arm/boot/compressed/sdhi-sh7372.c
+++ b/arch/arm/boot/compressed/sdhi-sh7372.c
@@ -85,7 +85,7 @@ asmlinkage void mmc_loader(unsigned short *buf, unsigned long len)
85 goto err; 85 goto err;
86 86
87 /* Disable clock to SDHI1 hardware block */ 87 /* Disable clock to SDHI1 hardware block */
88 __raw_writel(__raw_readl(SMSTPCR3) & (1 << 13), SMSTPCR3); 88 __raw_writel(__raw_readl(SMSTPCR3) | (1 << 13), SMSTPCR3);
89 89
90 mmc_update_progress(MMC_PROGRESS_DONE); 90 mmc_update_progress(MMC_PROGRESS_DONE);
91 91
diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi
new file mode 100644
index 000000000000..aeef04269cf8
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9g20.dtsi
@@ -0,0 +1,119 @@
1/*
2 * at91sam9g20.dtsi - Device Tree Include file for AT91SAM9G20 family SoC
3 *
4 * Copyright (C) 2011 Atmel,
5 * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>,
6 * 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
7 *
8 * Licensed under GPLv2 or later.
9 */
10
11/include/ "skeleton.dtsi"
12
13/ {
14 model = "Atmel AT91SAM9G20 family SoC";
15 compatible = "atmel,at91sam9g20";
16 interrupt-parent = <&aic>;
17
18 aliases {
19 serial0 = &dbgu;
20 serial1 = &usart0;
21 serial2 = &usart1;
22 serial3 = &usart2;
23 serial4 = &usart3;
24 serial5 = &usart4;
25 serial6 = &usart5;
26 };
27 cpus {
28 cpu@0 {
29 compatible = "arm,arm926ejs";
30 };
31 };
32
33 memory@20000000 {
34 reg = <0x20000000 0x08000000>;
35 };
36
37 ahb {
38 compatible = "simple-bus";
39 #address-cells = <1>;
40 #size-cells = <1>;
41 ranges;
42
43 apb {
44 compatible = "simple-bus";
45 #address-cells = <1>;
46 #size-cells = <1>;
47 ranges;
48
49 aic: interrupt-controller@fffff000 {
50 #interrupt-cells = <1>;
51 compatible = "atmel,at91rm9200-aic";
52 interrupt-controller;
53 interrupt-parent;
54 reg = <0xfffff000 0x200>;
55 };
56
57 dbgu: serial@fffff200 {
58 compatible = "atmel,at91sam9260-usart";
59 reg = <0xfffff200 0x200>;
60 interrupts = <1>;
61 status = "disabled";
62 };
63
64 usart0: serial@fffb0000 {
65 compatible = "atmel,at91sam9260-usart";
66 reg = <0xfffb0000 0x200>;
67 interrupts = <6>;
68 atmel,use-dma-rx;
69 atmel,use-dma-tx;
70 status = "disabled";
71 };
72
73 usart1: serial@fffb4000 {
74 compatible = "atmel,at91sam9260-usart";
75 reg = <0xfffb4000 0x200>;
76 interrupts = <7>;
77 atmel,use-dma-rx;
78 atmel,use-dma-tx;
79 status = "disabled";
80 };
81
82 usart2: serial@fffb8000 {
83 compatible = "atmel,at91sam9260-usart";
84 reg = <0xfffb8000 0x200>;
85 interrupts = <8>;
86 atmel,use-dma-rx;
87 atmel,use-dma-tx;
88 status = "disabled";
89 };
90
91 usart3: serial@fffd0000 {
92 compatible = "atmel,at91sam9260-usart";
93 reg = <0xfffd0000 0x200>;
94 interrupts = <23>;
95 atmel,use-dma-rx;
96 atmel,use-dma-tx;
97 status = "disabled";
98 };
99
100 usart4: serial@fffd4000 {
101 compatible = "atmel,at91sam9260-usart";
102 reg = <0xfffd4000 0x200>;
103 interrupts = <24>;
104 atmel,use-dma-rx;
105 atmel,use-dma-tx;
106 status = "disabled";
107 };
108
109 usart5: serial@fffd8000 {
110 compatible = "atmel,at91sam9260-usart";
111 reg = <0xfffd8000 0x200>;
112 interrupts = <25>;
113 atmel,use-dma-rx;
114 atmel,use-dma-tx;
115 status = "disabled";
116 };
117 };
118 };
119};
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
new file mode 100644
index 000000000000..db6a45202f26
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -0,0 +1,106 @@
1/*
2 * at91sam9g45.dtsi - Device Tree Include file for AT91SAM9G45 family SoC
3 * applies to AT91SAM9G45, AT91SAM9M10,
4 * AT91SAM9G46, AT91SAM9M11 SoC
5 *
6 * Copyright (C) 2011 Atmel,
7 * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>
8 *
9 * Licensed under GPLv2 or later.
10 */
11
12/include/ "skeleton.dtsi"
13
14/ {
15 model = "Atmel AT91SAM9G45 family SoC";
16 compatible = "atmel,at91sam9g45";
17 interrupt-parent = <&aic>;
18
19 aliases {
20 serial0 = &dbgu;
21 serial1 = &usart0;
22 serial2 = &usart1;
23 serial3 = &usart2;
24 serial4 = &usart3;
25 };
26 cpus {
27 cpu@0 {
28 compatible = "arm,arm926ejs";
29 };
30 };
31
32 memory@70000000 {
33 reg = <0x70000000 0x10000000>;
34 };
35
36 ahb {
37 compatible = "simple-bus";
38 #address-cells = <1>;
39 #size-cells = <1>;
40 ranges;
41
42 apb {
43 compatible = "simple-bus";
44 #address-cells = <1>;
45 #size-cells = <1>;
46 ranges;
47
48 aic: interrupt-controller@fffff000 {
49 #interrupt-cells = <1>;
50 compatible = "atmel,at91rm9200-aic";
51 interrupt-controller;
52 interrupt-parent;
53 reg = <0xfffff000 0x200>;
54 };
55
56 dma: dma-controller@ffffec00 {
57 compatible = "atmel,at91sam9g45-dma";
58 reg = <0xffffec00 0x200>;
59 interrupts = <21>;
60 };
61
62 dbgu: serial@ffffee00 {
63 compatible = "atmel,at91sam9260-usart";
64 reg = <0xffffee00 0x200>;
65 interrupts = <1>;
66 status = "disabled";
67 };
68
69 usart0: serial@fff8c000 {
70 compatible = "atmel,at91sam9260-usart";
71 reg = <0xfff8c000 0x200>;
72 interrupts = <7>;
73 atmel,use-dma-rx;
74 atmel,use-dma-tx;
75 status = "disabled";
76 };
77
78 usart1: serial@fff90000 {
79 compatible = "atmel,at91sam9260-usart";
80 reg = <0xfff90000 0x200>;
81 interrupts = <8>;
82 atmel,use-dma-rx;
83 atmel,use-dma-tx;
84 status = "disabled";
85 };
86
87 usart2: serial@fff94000 {
88 compatible = "atmel,at91sam9260-usart";
89 reg = <0xfff94000 0x200>;
90 interrupts = <9>;
91 atmel,use-dma-rx;
92 atmel,use-dma-tx;
93 status = "disabled";
94 };
95
96 usart3: serial@fff98000 {
97 compatible = "atmel,at91sam9260-usart";
98 reg = <0xfff98000 0x200>;
99 interrupts = <10>;
100 atmel,use-dma-rx;
101 atmel,use-dma-tx;
102 status = "disabled";
103 };
104 };
105 };
106};
diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts
new file mode 100644
index 000000000000..85b34f59cd82
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts
@@ -0,0 +1,35 @@
1/*
2 * at91sam9m10g45ek.dts - Device Tree file for AT91SAM9M10G45-EK board
3 *
4 * Copyright (C) 2011 Atmel,
5 * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>
6 *
7 * Licensed under GPLv2 or later.
8 */
9/dts-v1/;
10/include/ "at91sam9g45.dtsi"
11
12/ {
13 model = "Atmel AT91SAM9M10G45-EK";
14 compatible = "atmel,at91sam9m10g45ek", "atmel,at91sam9g45", "atmel,at91sam9";
15
16 chosen {
17 bootargs = "mem=64M console=ttyS0,115200 mtdparts=atmel_nand:4M(bootstrap/uboot/kernel)ro,60M(rootfs),-(data) root=/dev/mtdblock1 rw rootfstype=jffs2";
18 };
19
20 memory@70000000 {
21 reg = <0x70000000 0x4000000>;
22 };
23
24 ahb {
25 apb {
26 dbgu: serial@ffffee00 {
27 status = "okay";
28 };
29
30 usart1: serial@fff90000 {
31 status = "okay";
32 };
33 };
34 };
35};
diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts
new file mode 100644
index 000000000000..f8766af11215
--- /dev/null
+++ b/arch/arm/boot/dts/imx51-babbage.dts
@@ -0,0 +1,135 @@
1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/dts-v1/;
14/include/ "imx51.dtsi"
15
16/ {
17 model = "Freescale i.MX51 Babbage Board";
18 compatible = "fsl,imx51-babbage", "fsl,imx51";
19
20 chosen {
21 bootargs = "console=ttymxc0,115200 root=/dev/mmcblk0p3 rootwait";
22 };
23
24 memory {
25 reg = <0x90000000 0x20000000>;
26 };
27
28 soc {
29 aips@70000000 { /* aips-1 */
30 spba@70000000 {
31 esdhc@70004000 { /* ESDHC1 */
32 fsl,cd-internal;
33 fsl,wp-internal;
34 status = "okay";
35 };
36
37 esdhc@70008000 { /* ESDHC2 */
38 cd-gpios = <&gpio0 6 0>; /* GPIO1_6 */
39 wp-gpios = <&gpio0 5 0>; /* GPIO1_5 */
40 status = "okay";
41 };
42
43 uart2: uart@7000c000 { /* UART3 */
44 fsl,uart-has-rtscts;
45 status = "okay";
46 };
47
48 ecspi@70010000 { /* ECSPI1 */
49 fsl,spi-num-chipselects = <2>;
50 cs-gpios = <&gpio3 24 0>, /* GPIO4_24 */
51 <&gpio3 25 0>; /* GPIO4_25 */
52 status = "okay";
53
54 pmic: mc13892@0 {
55 #address-cells = <1>;
56 #size-cells = <0>;
57 compatible = "fsl,mc13892";
58 spi-max-frequency = <6000000>;
59 reg = <0>;
60 mc13xxx-irq-gpios = <&gpio0 8 0>; /* GPIO1_8 */
61 fsl,mc13xxx-uses-regulator;
62 };
63
64 flash: at45db321d@1 {
65 #address-cells = <1>;
66 #size-cells = <1>;
67 compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash";
68 spi-max-frequency = <25000000>;
69 reg = <1>;
70
71 partition@0 {
72 label = "U-Boot";
73 reg = <0x0 0x40000>;
74 read-only;
75 };
76
77 partition@40000 {
78 label = "Kernel";
79 reg = <0x40000 0x3c0000>;
80 };
81 };
82 };
83 };
84
85 wdog@73f98000 { /* WDOG1 */
86 status = "okay";
87 };
88
89 iomuxc@73fa8000 {
90 compatible = "fsl,imx51-iomuxc-babbage";
91 reg = <0x73fa8000 0x4000>;
92 };
93
94 uart0: uart@73fbc000 {
95 fsl,uart-has-rtscts;
96 status = "okay";
97 };
98
99 uart1: uart@73fc0000 {
100 status = "okay";
101 };
102 };
103
104 aips@80000000 { /* aips-2 */
105 sdma@83fb0000 {
106 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
107 };
108
109 i2c@83fc4000 { /* I2C2 */
110 status = "okay";
111
112 codec: sgtl5000@0a {
113 compatible = "fsl,sgtl5000";
114 reg = <0x0a>;
115 };
116 };
117
118 fec@83fec000 {
119 phy-mode = "mii";
120 status = "okay";
121 };
122 };
123 };
124
125 gpio-keys {
126 compatible = "gpio-keys";
127
128 power {
129 label = "Power Button";
130 gpios = <&gpio1 21 0>;
131 linux,code = <116>; /* KEY_POWER */
132 gpio-key,wakeup;
133 };
134 };
135};
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
new file mode 100644
index 000000000000..327ab8e3a4c8
--- /dev/null
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -0,0 +1,246 @@
1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/include/ "skeleton.dtsi"
14
15/ {
16 aliases {
17 serial0 = &uart0;
18 serial1 = &uart1;
19 serial2 = &uart2;
20 };
21
22 tzic: tz-interrupt-controller@e0000000 {
23 compatible = "fsl,imx51-tzic", "fsl,tzic";
24 interrupt-controller;
25 #interrupt-cells = <1>;
26 reg = <0xe0000000 0x4000>;
27 };
28
29 clocks {
30 #address-cells = <1>;
31 #size-cells = <0>;
32
33 ckil {
34 compatible = "fsl,imx-ckil", "fixed-clock";
35 clock-frequency = <32768>;
36 };
37
38 ckih1 {
39 compatible = "fsl,imx-ckih1", "fixed-clock";
40 clock-frequency = <22579200>;
41 };
42
43 ckih2 {
44 compatible = "fsl,imx-ckih2", "fixed-clock";
45 clock-frequency = <0>;
46 };
47
48 osc {
49 compatible = "fsl,imx-osc", "fixed-clock";
50 clock-frequency = <24000000>;
51 };
52 };
53
54 soc {
55 #address-cells = <1>;
56 #size-cells = <1>;
57 compatible = "simple-bus";
58 interrupt-parent = <&tzic>;
59 ranges;
60
61 aips@70000000 { /* AIPS1 */
62 compatible = "fsl,aips-bus", "simple-bus";
63 #address-cells = <1>;
64 #size-cells = <1>;
65 reg = <0x70000000 0x10000000>;
66 ranges;
67
68 spba@70000000 {
69 compatible = "fsl,spba-bus", "simple-bus";
70 #address-cells = <1>;
71 #size-cells = <1>;
72 reg = <0x70000000 0x40000>;
73 ranges;
74
75 esdhc@70004000 { /* ESDHC1 */
76 compatible = "fsl,imx51-esdhc";
77 reg = <0x70004000 0x4000>;
78 interrupts = <1>;
79 status = "disabled";
80 };
81
82 esdhc@70008000 { /* ESDHC2 */
83 compatible = "fsl,imx51-esdhc";
84 reg = <0x70008000 0x4000>;
85 interrupts = <2>;
86 status = "disabled";
87 };
88
89 uart2: uart@7000c000 { /* UART3 */
90 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
91 reg = <0x7000c000 0x4000>;
92 interrupts = <33>;
93 status = "disabled";
94 };
95
96 ecspi@70010000 { /* ECSPI1 */
97 #address-cells = <1>;
98 #size-cells = <0>;
99 compatible = "fsl,imx51-ecspi";
100 reg = <0x70010000 0x4000>;
101 interrupts = <36>;
102 status = "disabled";
103 };
104
105 esdhc@70020000 { /* ESDHC3 */
106 compatible = "fsl,imx51-esdhc";
107 reg = <0x70020000 0x4000>;
108 interrupts = <3>;
109 status = "disabled";
110 };
111
112 esdhc@70024000 { /* ESDHC4 */
113 compatible = "fsl,imx51-esdhc";
114 reg = <0x70024000 0x4000>;
115 interrupts = <4>;
116 status = "disabled";
117 };
118 };
119
120 gpio0: gpio@73f84000 { /* GPIO1 */
121 compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
122 reg = <0x73f84000 0x4000>;
123 interrupts = <50 51>;
124 gpio-controller;
125 #gpio-cells = <2>;
126 interrupt-controller;
127 #interrupt-cells = <1>;
128 };
129
130 gpio1: gpio@73f88000 { /* GPIO2 */
131 compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
132 reg = <0x73f88000 0x4000>;
133 interrupts = <52 53>;
134 gpio-controller;
135 #gpio-cells = <2>;
136 interrupt-controller;
137 #interrupt-cells = <1>;
138 };
139
140 gpio2: gpio@73f8c000 { /* GPIO3 */
141 compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
142 reg = <0x73f8c000 0x4000>;
143 interrupts = <54 55>;
144 gpio-controller;
145 #gpio-cells = <2>;
146 interrupt-controller;
147 #interrupt-cells = <1>;
148 };
149
150 gpio3: gpio@73f90000 { /* GPIO4 */
151 compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
152 reg = <0x73f90000 0x4000>;
153 interrupts = <56 57>;
154 gpio-controller;
155 #gpio-cells = <2>;
156 interrupt-controller;
157 #interrupt-cells = <1>;
158 };
159
160 wdog@73f98000 { /* WDOG1 */
161 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
162 reg = <0x73f98000 0x4000>;
163 interrupts = <58>;
164 status = "disabled";
165 };
166
167 wdog@73f9c000 { /* WDOG2 */
168 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
169 reg = <0x73f9c000 0x4000>;
170 interrupts = <59>;
171 status = "disabled";
172 };
173
174 uart0: uart@73fbc000 {
175 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
176 reg = <0x73fbc000 0x4000>;
177 interrupts = <31>;
178 status = "disabled";
179 };
180
181 uart1: uart@73fc0000 {
182 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
183 reg = <0x73fc0000 0x4000>;
184 interrupts = <32>;
185 status = "disabled";
186 };
187 };
188
189 aips@80000000 { /* AIPS2 */
190 compatible = "fsl,aips-bus", "simple-bus";
191 #address-cells = <1>;
192 #size-cells = <1>;
193 reg = <0x80000000 0x10000000>;
194 ranges;
195
196 ecspi@83fac000 { /* ECSPI2 */
197 #address-cells = <1>;
198 #size-cells = <0>;
199 compatible = "fsl,imx51-ecspi";
200 reg = <0x83fac000 0x4000>;
201 interrupts = <37>;
202 status = "disabled";
203 };
204
205 sdma@83fb0000 {
206 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
207 reg = <0x83fb0000 0x4000>;
208 interrupts = <6>;
209 };
210
211 cspi@83fc0000 {
212 #address-cells = <1>;
213 #size-cells = <0>;
214 compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
215 reg = <0x83fc0000 0x4000>;
216 interrupts = <38>;
217 status = "disabled";
218 };
219
220 i2c@83fc4000 { /* I2C2 */
221 #address-cells = <1>;
222 #size-cells = <0>;
223 compatible = "fsl,imx51-i2c", "fsl,imx1-i2c";
224 reg = <0x83fc4000 0x4000>;
225 interrupts = <63>;
226 status = "disabled";
227 };
228
229 i2c@83fc8000 { /* I2C1 */
230 #address-cells = <1>;
231 #size-cells = <0>;
232 compatible = "fsl,imx51-i2c", "fsl,imx1-i2c";
233 reg = <0x83fc8000 0x4000>;
234 interrupts = <62>;
235 status = "disabled";
236 };
237
238 fec@83fec000 {
239 compatible = "fsl,imx51-fec", "fsl,imx27-fec";
240 reg = <0x83fec000 0x4000>;
241 interrupts = <87>;
242 status = "disabled";
243 };
244 };
245 };
246};
diff --git a/arch/arm/boot/dts/imx53-ard.dts b/arch/arm/boot/dts/imx53-ard.dts
new file mode 100644
index 000000000000..2ab7f80a0a35
--- /dev/null
+++ b/arch/arm/boot/dts/imx53-ard.dts
@@ -0,0 +1,113 @@
1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/dts-v1/;
14/include/ "imx53.dtsi"
15
16/ {
17 model = "Freescale i.MX53 Automotive Reference Design Board";
18 compatible = "fsl,imx53-ard", "fsl,imx53";
19
20 chosen {
21 bootargs = "console=ttymxc0,115200 root=/dev/mmcblk0p3 rootwait";
22 };
23
24 memory {
25 reg = <0x70000000 0x40000000>;
26 };
27
28 soc {
29 aips@50000000 { /* AIPS1 */
30 spba@50000000 {
31 esdhc@50004000 { /* ESDHC1 */
32 cd-gpios = <&gpio0 1 0>; /* GPIO1_1 */
33 wp-gpios = <&gpio0 9 0>; /* GPIO1_9 */
34 status = "okay";
35 };
36 };
37
38 wdog@53f98000 { /* WDOG1 */
39 status = "okay";
40 };
41
42 iomuxc@53fa8000 {
43 compatible = "fsl,imx53-iomuxc-ard";
44 reg = <0x53fa8000 0x4000>;
45 };
46
47 uart0: uart@53fbc000 { /* UART1 */
48 status = "okay";
49 };
50 };
51
52 aips@60000000 { /* AIPS2 */
53 sdma@63fb0000 {
54 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
55 };
56 };
57 };
58
59 eim-cs1@f4000000 {
60 #address-cells = <1>;
61 #size-cells = <1>;
62 compatible = "fsl,eim-bus", "simple-bus";
63 reg = <0xf4000000 0x3ff0000>;
64 ranges;
65
66 lan9220@f4000000 {
67 compatible = "smsc,lan9220", "smsc,lan9115";
68 reg = <0xf4000000 0x2000000>;
69 phy-mode = "mii";
70 interrupt-parent = <&gpio1>;
71 interrupts = <31>;
72 reg-io-width = <4>;
73 smsc,irq-push-pull;
74 };
75 };
76
77 gpio-keys {
78 compatible = "gpio-keys";
79
80 home {
81 label = "Home";
82 gpios = <&gpio4 10 0>; /* GPIO5_10 */
83 linux,code = <102>; /* KEY_HOME */
84 gpio-key,wakeup;
85 };
86
87 back {
88 label = "Back";
89 gpios = <&gpio4 11 0>; /* GPIO5_11 */
90 linux,code = <158>; /* KEY_BACK */
91 gpio-key,wakeup;
92 };
93
94 program {
95 label = "Program";
96 gpios = <&gpio4 12 0>; /* GPIO5_12 */
97 linux,code = <362>; /* KEY_PROGRAM */
98 gpio-key,wakeup;
99 };
100
101 volume-up {
102 label = "Volume Up";
103 gpios = <&gpio4 13 0>; /* GPIO5_13 */
104 linux,code = <115>; /* KEY_VOLUMEUP */
105 };
106
107 volume-down {
108 label = "Volume Down";
109 gpios = <&gpio3 0 0>; /* GPIO4_0 */
110 linux,code = <114>; /* KEY_VOLUMEDOWN */
111 };
112 };
113};
diff --git a/arch/arm/boot/dts/imx53-evk.dts b/arch/arm/boot/dts/imx53-evk.dts
new file mode 100644
index 000000000000..3f3a88185ff8
--- /dev/null
+++ b/arch/arm/boot/dts/imx53-evk.dts
@@ -0,0 +1,120 @@
1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/dts-v1/;
14/include/ "imx53.dtsi"
15
16/ {
17 model = "Freescale i.MX53 Evaluation Kit";
18 compatible = "fsl,imx53-evk", "fsl,imx53";
19
20 chosen {
21 bootargs = "console=ttymxc0,115200 root=/dev/mmcblk0p3 rootwait";
22 };
23
24 memory {
25 reg = <0x70000000 0x80000000>;
26 };
27
28 soc {
29 aips@50000000 { /* AIPS1 */
30 spba@50000000 {
31 esdhc@50004000 { /* ESDHC1 */
32 cd-gpios = <&gpio2 13 0>; /* GPIO3_13 */
33 wp-gpios = <&gpio2 14 0>; /* GPIO3_14 */
34 status = "okay";
35 };
36
37 ecspi@50010000 { /* ECSPI1 */
38 fsl,spi-num-chipselects = <2>;
39 cs-gpios = <&gpio1 30 0>, /* GPIO2_30 */
40 <&gpio2 19 0>; /* GPIO3_19 */
41 status = "okay";
42
43 flash: at45db321d@1 {
44 #address-cells = <1>;
45 #size-cells = <1>;
46 compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash";
47 spi-max-frequency = <25000000>;
48 reg = <1>;
49
50 partition@0 {
51 label = "U-Boot";
52 reg = <0x0 0x40000>;
53 read-only;
54 };
55
56 partition@40000 {
57 label = "Kernel";
58 reg = <0x40000 0x3c0000>;
59 };
60 };
61 };
62
63 esdhc@50020000 { /* ESDHC3 */
64 cd-gpios = <&gpio2 11 0>; /* GPIO3_11 */
65 wp-gpios = <&gpio2 12 0>; /* GPIO3_12 */
66 status = "okay";
67 };
68 };
69
70 wdog@53f98000 { /* WDOG1 */
71 status = "okay";
72 };
73
74 iomuxc@53fa8000 {
75 compatible = "fsl,imx53-iomuxc-evk";
76 reg = <0x53fa8000 0x4000>;
77 };
78
79 uart0: uart@53fbc000 { /* UART1 */
80 status = "okay";
81 };
82 };
83
84 aips@60000000 { /* AIPS2 */
85 sdma@63fb0000 {
86 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
87 };
88
89 i2c@63fc4000 { /* I2C2 */
90 status = "okay";
91
92 pmic: mc13892@08 {
93 compatible = "fsl,mc13892", "fsl,mc13xxx";
94 reg = <0x08>;
95 };
96
97 codec: sgtl5000@0a {
98 compatible = "fsl,sgtl5000";
99 reg = <0x0a>;
100 };
101 };
102
103 fec@63fec000 {
104 phy-mode = "rmii";
105 phy-reset-gpios = <&gpio6 6 0>; /* GPIO7_6 */
106 status = "okay";
107 };
108 };
109 };
110
111 leds {
112 compatible = "gpio-leds";
113
114 green {
115 label = "Heartbeat";
116 gpios = <&gpio6 7 0>; /* GPIO7_7 */
117 linux,default-trigger = "heartbeat";
118 };
119 };
120};
diff --git a/arch/arm/boot/dts/imx53-qsb.dts b/arch/arm/boot/dts/imx53-qsb.dts
new file mode 100644
index 000000000000..ae6de6d0c3f1
--- /dev/null
+++ b/arch/arm/boot/dts/imx53-qsb.dts
@@ -0,0 +1,125 @@
1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/dts-v1/;
14/include/ "imx53.dtsi"
15
16/ {
17 model = "Freescale i.MX53 Quick Start Board";
18 compatible = "fsl,imx53-qsb", "fsl,imx53";
19
20 chosen {
21 bootargs = "console=ttymxc0,115200 root=/dev/mmcblk0p3 rootwait";
22 };
23
24 memory {
25 reg = <0x70000000 0x40000000>;
26 };
27
28 soc {
29 aips@50000000 { /* AIPS1 */
30 spba@50000000 {
31 esdhc@50004000 { /* ESDHC1 */
32 cd-gpios = <&gpio2 13 0>; /* GPIO3_13 */
33 status = "okay";
34 };
35
36 esdhc@50020000 { /* ESDHC3 */
37 cd-gpios = <&gpio2 11 0>; /* GPIO3_11 */
38 wp-gpios = <&gpio2 12 0>; /* GPIO3_12 */
39 status = "okay";
40 };
41 };
42
43 wdog@53f98000 { /* WDOG1 */
44 status = "okay";
45 };
46
47 iomuxc@53fa8000 {
48 compatible = "fsl,imx53-iomuxc-qsb";
49 reg = <0x53fa8000 0x4000>;
50 };
51
52 uart0: uart@53fbc000 { /* UART1 */
53 status = "okay";
54 };
55 };
56
57 aips@60000000 { /* AIPS2 */
58 sdma@63fb0000 {
59 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
60 };
61
62 i2c@63fc4000 { /* I2C2 */
63 status = "okay";
64
65 codec: sgtl5000@0a {
66 compatible = "fsl,sgtl5000";
67 reg = <0x0a>;
68 };
69 };
70
71 i2c@63fc8000 { /* I2C1 */
72 status = "okay";
73
74 accelerometer: mma8450@1c {
75 compatible = "fsl,mma8450";
76 reg = <0x1c>;
77 };
78
79 pmic: dialog@48 {
80 compatible = "dialog,da9053", "dialog,da9052";
81 reg = <0x48>;
82 };
83 };
84
85 fec@63fec000 {
86 phy-mode = "rmii";
87 phy-reset-gpios = <&gpio6 6 0>; /* GPIO7_6 */
88 status = "okay";
89 };
90 };
91 };
92
93 gpio-keys {
94 compatible = "gpio-keys";
95
96 power {
97 label = "Power Button";
98 gpios = <&gpio0 8 0>; /* GPIO1_8 */
99 linux,code = <116>; /* KEY_POWER */
100 gpio-key,wakeup;
101 };
102
103 volume-up {
104 label = "Volume Up";
105 gpios = <&gpio1 14 0>; /* GPIO2_14 */
106 linux,code = <115>; /* KEY_VOLUMEUP */
107 };
108
109 volume-down {
110 label = "Volume Down";
111 gpios = <&gpio1 15 0>; /* GPIO2_15 */
112 linux,code = <114>; /* KEY_VOLUMEDOWN */
113 };
114 };
115
116 leds {
117 compatible = "gpio-leds";
118
119 user {
120 label = "Heartbeat";
121 gpios = <&gpio6 7 0>; /* GPIO7_7 */
122 linux,default-trigger = "heartbeat";
123 };
124 };
125};
diff --git a/arch/arm/boot/dts/imx53-smd.dts b/arch/arm/boot/dts/imx53-smd.dts
new file mode 100644
index 000000000000..b1c062eea715
--- /dev/null
+++ b/arch/arm/boot/dts/imx53-smd.dts
@@ -0,0 +1,169 @@
1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/dts-v1/;
14/include/ "imx53.dtsi"
15
16/ {
17 model = "Freescale i.MX53 Smart Mobile Reference Design Board";
18 compatible = "fsl,imx53-smd", "fsl,imx53";
19
20 chosen {
21 bootargs = "console=ttymxc0,115200 root=/dev/mmcblk0p3 rootwait";
22 };
23
24 memory {
25 reg = <0x70000000 0x40000000>;
26 };
27
28 soc {
29 aips@50000000 { /* AIPS1 */
30 spba@50000000 {
31 esdhc@50004000 { /* ESDHC1 */
32 cd-gpios = <&gpio2 13 0>; /* GPIO3_13 */
33 wp-gpios = <&gpio3 11 0>; /* GPIO4_11 */
34 status = "okay";
35 };
36
37 esdhc@50008000 { /* ESDHC2 */
38 fsl,card-wired;
39 status = "okay";
40 };
41
42 uart2: uart@5000c000 { /* UART3 */
43 fsl,uart-has-rtscts;
44 status = "okay";
45 };
46
47 ecspi@50010000 { /* ECSPI1 */
48 fsl,spi-num-chipselects = <2>;
49 cs-gpios = <&gpio1 30 0>, /* GPIO2_30 */
50 <&gpio2 19 0>; /* GPIO3_19 */
51 status = "okay";
52
53 zigbee: mc1323@0 {
54 compatible = "fsl,mc1323";
55 spi-max-frequency = <8000000>;
56 reg = <0>;
57 };
58
59 flash: m25p32@1 {
60 #address-cells = <1>;
61 #size-cells = <1>;
62 compatible = "st,m25p32", "st,m25p";
63 spi-max-frequency = <20000000>;
64 reg = <1>;
65
66 partition@0 {
67 label = "U-Boot";
68 reg = <0x0 0x40000>;
69 read-only;
70 };
71
72 partition@40000 {
73 label = "Kernel";
74 reg = <0x40000 0x3c0000>;
75 };
76 };
77 };
78
79 esdhc@50020000 { /* ESDHC3 */
80 fsl,card-wired;
81 status = "okay";
82 };
83 };
84
85 wdog@53f98000 { /* WDOG1 */
86 status = "okay";
87 };
88
89 iomuxc@53fa8000 {
90 compatible = "fsl,imx53-iomuxc-smd";
91 reg = <0x53fa8000 0x4000>;
92 };
93
94 uart0: uart@53fbc000 { /* UART1 */
95 status = "okay";
96 };
97
98 uart1: uart@53fc0000 { /* UART2 */
99 status = "okay";
100 };
101 };
102
103 aips@60000000 { /* AIPS2 */
104 sdma@63fb0000 {
105 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
106 };
107
108 i2c@63fc4000 { /* I2C2 */
109 status = "okay";
110
111 codec: sgtl5000@0a {
112 compatible = "fsl,sgtl5000";
113 reg = <0x0a>;
114 };
115
116 magnetometer: mag3110@0e {
117 compatible = "fsl,mag3110";
118 reg = <0x0e>;
119 };
120
121 touchkey: mpr121@5a {
122 compatible = "fsl,mpr121";
123 reg = <0x5a>;
124 };
125 };
126
127 i2c@63fc8000 { /* I2C1 */
128 status = "okay";
129
130 accelerometer: mma8450@1c {
131 compatible = "fsl,mma8450";
132 reg = <0x1c>;
133 };
134
135 camera: ov5642@3c {
136 compatible = "ovti,ov5642";
137 reg = <0x3c>;
138 };
139
140 pmic: dialog@48 {
141 compatible = "dialog,da9053", "dialog,da9052";
142 reg = <0x48>;
143 };
144 };
145
146 fec@63fec000 {
147 phy-mode = "rmii";
148 phy-reset-gpios = <&gpio6 6 0>; /* GPIO7_6 */
149 status = "okay";
150 };
151 };
152 };
153
154 gpio-keys {
155 compatible = "gpio-keys";
156
157 volume-up {
158 label = "Volume Up";
159 gpios = <&gpio1 14 0>; /* GPIO2_14 */
160 linux,code = <115>; /* KEY_VOLUMEUP */
161 };
162
163 volume-down {
164 label = "Volume Down";
165 gpios = <&gpio1 15 0>; /* GPIO2_15 */
166 linux,code = <114>; /* KEY_VOLUMEDOWN */
167 };
168 };
169};
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
new file mode 100644
index 000000000000..099cd84ee372
--- /dev/null
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -0,0 +1,301 @@
1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/include/ "skeleton.dtsi"
14
15/ {
16 aliases {
17 serial0 = &uart0;
18 serial1 = &uart1;
19 serial2 = &uart2;
20 serial3 = &uart3;
21 serial4 = &uart4;
22 };
23
24 tzic: tz-interrupt-controller@0fffc000 {
25 compatible = "fsl,imx53-tzic", "fsl,tzic";
26 interrupt-controller;
27 #interrupt-cells = <1>;
28 reg = <0x0fffc000 0x4000>;
29 };
30
31 clocks {
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 ckil {
36 compatible = "fsl,imx-ckil", "fixed-clock";
37 clock-frequency = <32768>;
38 };
39
40 ckih1 {
41 compatible = "fsl,imx-ckih1", "fixed-clock";
42 clock-frequency = <22579200>;
43 };
44
45 ckih2 {
46 compatible = "fsl,imx-ckih2", "fixed-clock";
47 clock-frequency = <0>;
48 };
49
50 osc {
51 compatible = "fsl,imx-osc", "fixed-clock";
52 clock-frequency = <24000000>;
53 };
54 };
55
56 soc {
57 #address-cells = <1>;
58 #size-cells = <1>;
59 compatible = "simple-bus";
60 interrupt-parent = <&tzic>;
61 ranges;
62
63 aips@50000000 { /* AIPS1 */
64 compatible = "fsl,aips-bus", "simple-bus";
65 #address-cells = <1>;
66 #size-cells = <1>;
67 reg = <0x50000000 0x10000000>;
68 ranges;
69
70 spba@50000000 {
71 compatible = "fsl,spba-bus", "simple-bus";
72 #address-cells = <1>;
73 #size-cells = <1>;
74 reg = <0x50000000 0x40000>;
75 ranges;
76
77 esdhc@50004000 { /* ESDHC1 */
78 compatible = "fsl,imx53-esdhc";
79 reg = <0x50004000 0x4000>;
80 interrupts = <1>;
81 status = "disabled";
82 };
83
84 esdhc@50008000 { /* ESDHC2 */
85 compatible = "fsl,imx53-esdhc";
86 reg = <0x50008000 0x4000>;
87 interrupts = <2>;
88 status = "disabled";
89 };
90
91 uart2: uart@5000c000 { /* UART3 */
92 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
93 reg = <0x5000c000 0x4000>;
94 interrupts = <33>;
95 status = "disabled";
96 };
97
98 ecspi@50010000 { /* ECSPI1 */
99 #address-cells = <1>;
100 #size-cells = <0>;
101 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
102 reg = <0x50010000 0x4000>;
103 interrupts = <36>;
104 status = "disabled";
105 };
106
107 esdhc@50020000 { /* ESDHC3 */
108 compatible = "fsl,imx53-esdhc";
109 reg = <0x50020000 0x4000>;
110 interrupts = <3>;
111 status = "disabled";
112 };
113
114 esdhc@50024000 { /* ESDHC4 */
115 compatible = "fsl,imx53-esdhc";
116 reg = <0x50024000 0x4000>;
117 interrupts = <4>;
118 status = "disabled";
119 };
120 };
121
122 gpio0: gpio@53f84000 { /* GPIO1 */
123 compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
124 reg = <0x53f84000 0x4000>;
125 interrupts = <50 51>;
126 gpio-controller;
127 #gpio-cells = <2>;
128 interrupt-controller;
129 #interrupt-cells = <1>;
130 };
131
132 gpio1: gpio@53f88000 { /* GPIO2 */
133 compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
134 reg = <0x53f88000 0x4000>;
135 interrupts = <52 53>;
136 gpio-controller;
137 #gpio-cells = <2>;
138 interrupt-controller;
139 #interrupt-cells = <1>;
140 };
141
142 gpio2: gpio@53f8c000 { /* GPIO3 */
143 compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
144 reg = <0x53f8c000 0x4000>;
145 interrupts = <54 55>;
146 gpio-controller;
147 #gpio-cells = <2>;
148 interrupt-controller;
149 #interrupt-cells = <1>;
150 };
151
152 gpio3: gpio@53f90000 { /* GPIO4 */
153 compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
154 reg = <0x53f90000 0x4000>;
155 interrupts = <56 57>;
156 gpio-controller;
157 #gpio-cells = <2>;
158 interrupt-controller;
159 #interrupt-cells = <1>;
160 };
161
162 wdog@53f98000 { /* WDOG1 */
163 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
164 reg = <0x53f98000 0x4000>;
165 interrupts = <58>;
166 status = "disabled";
167 };
168
169 wdog@53f9c000 { /* WDOG2 */
170 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
171 reg = <0x53f9c000 0x4000>;
172 interrupts = <59>;
173 status = "disabled";
174 };
175
176 uart0: uart@53fbc000 { /* UART1 */
177 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
178 reg = <0x53fbc000 0x4000>;
179 interrupts = <31>;
180 status = "disabled";
181 };
182
183 uart1: uart@53fc0000 { /* UART2 */
184 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
185 reg = <0x53fc0000 0x4000>;
186 interrupts = <32>;
187 status = "disabled";
188 };
189
190 gpio4: gpio@53fdc000 { /* GPIO5 */
191 compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
192 reg = <0x53fdc000 0x4000>;
193 interrupts = <103 104>;
194 gpio-controller;
195 #gpio-cells = <2>;
196 interrupt-controller;
197 #interrupt-cells = <1>;
198 };
199
200 gpio5: gpio@53fe0000 { /* GPIO6 */
201 compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
202 reg = <0x53fe0000 0x4000>;
203 interrupts = <105 106>;
204 gpio-controller;
205 #gpio-cells = <2>;
206 interrupt-controller;
207 #interrupt-cells = <1>;
208 };
209
210 gpio6: gpio@53fe4000 { /* GPIO7 */
211 compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
212 reg = <0x53fe4000 0x4000>;
213 interrupts = <107 108>;
214 gpio-controller;
215 #gpio-cells = <2>;
216 interrupt-controller;
217 #interrupt-cells = <1>;
218 };
219
220 i2c@53fec000 { /* I2C3 */
221 #address-cells = <1>;
222 #size-cells = <0>;
223 compatible = "fsl,imx53-i2c", "fsl,imx1-i2c";
224 reg = <0x53fec000 0x4000>;
225 interrupts = <64>;
226 status = "disabled";
227 };
228
229 uart3: uart@53ff0000 { /* UART4 */
230 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
231 reg = <0x53ff0000 0x4000>;
232 interrupts = <13>;
233 status = "disabled";
234 };
235 };
236
237 aips@60000000 { /* AIPS2 */
238 compatible = "fsl,aips-bus", "simple-bus";
239 #address-cells = <1>;
240 #size-cells = <1>;
241 reg = <0x60000000 0x10000000>;
242 ranges;
243
244 uart4: uart@63f90000 { /* UART5 */
245 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
246 reg = <0x63f90000 0x4000>;
247 interrupts = <86>;
248 status = "disabled";
249 };
250
251 ecspi@63fac000 { /* ECSPI2 */
252 #address-cells = <1>;
253 #size-cells = <0>;
254 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
255 reg = <0x63fac000 0x4000>;
256 interrupts = <37>;
257 status = "disabled";
258 };
259
260 sdma@63fb0000 {
261 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
262 reg = <0x63fb0000 0x4000>;
263 interrupts = <6>;
264 };
265
266 cspi@63fc0000 {
267 #address-cells = <1>;
268 #size-cells = <0>;
269 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
270 reg = <0x63fc0000 0x4000>;
271 interrupts = <38>;
272 status = "disabled";
273 };
274
275 i2c@63fc4000 { /* I2C2 */
276 #address-cells = <1>;
277 #size-cells = <0>;
278 compatible = "fsl,imx53-i2c", "fsl,imx1-i2c";
279 reg = <0x63fc4000 0x4000>;
280 interrupts = <63>;
281 status = "disabled";
282 };
283
284 i2c@63fc8000 { /* I2C1 */
285 #address-cells = <1>;
286 #size-cells = <0>;
287 compatible = "fsl,imx53-i2c", "fsl,imx1-i2c";
288 reg = <0x63fc8000 0x4000>;
289 interrupts = <62>;
290 status = "disabled";
291 };
292
293 fec@63fec000 {
294 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
295 reg = <0x63fec000 0x4000>;
296 interrupts = <87>;
297 status = "disabled";
298 };
299 };
300 };
301};
diff --git a/arch/arm/boot/dts/tegra-harmony.dts b/arch/arm/boot/dts/tegra-harmony.dts
index 4c053340ce33..e5818668d091 100644
--- a/arch/arm/boot/dts/tegra-harmony.dts
+++ b/arch/arm/boot/dts/tegra-harmony.dts
@@ -57,14 +57,14 @@
57 }; 57 };
58 58
59 sdhci@c8000200 { 59 sdhci@c8000200 {
60 gpios = <&gpio 69 0>, /* cd, gpio PI5 */ 60 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
61 <&gpio 57 0>, /* wp, gpio PH1 */ 61 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
62 <&gpio 155 0>; /* power, gpio PT3 */ 62 power-gpios = <&gpio 155 0>; /* gpio PT3 */
63 }; 63 };
64 64
65 sdhci@c8000600 { 65 sdhci@c8000600 {
66 gpios = <&gpio 58 0>, /* cd, gpio PH2 */ 66 cd-gpios = <&gpio 58 0>; /* gpio PH2 */
67 <&gpio 59 0>, /* wp, gpio PH3 */ 67 wp-gpios = <&gpio 59 0>; /* gpio PH3 */
68 <&gpio 70 0>; /* power, gpio PI6 */ 68 power-gpios = <&gpio 70 0>; /* gpio PI6 */
69 }; 69 };
70}; 70};
diff --git a/arch/arm/boot/dts/tegra-seaboard.dts b/arch/arm/boot/dts/tegra-seaboard.dts
index 1940cae00748..64cedca6fc79 100644
--- a/arch/arm/boot/dts/tegra-seaboard.dts
+++ b/arch/arm/boot/dts/tegra-seaboard.dts
@@ -21,8 +21,8 @@
21 }; 21 };
22 22
23 sdhci@c8000400 { 23 sdhci@c8000400 {
24 gpios = <&gpio 69 0>, /* cd, gpio PI5 */ 24 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
25 <&gpio 57 0>, /* wp, gpio PH1 */ 25 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
26 <&gpio 70 0>; /* power, gpio PI6 */ 26 power-gpios = <&gpio 70 0>; /* gpio PI6 */
27 }; 27 };
28}; 28};
diff --git a/arch/arm/boot/dts/usb_a9g20.dts b/arch/arm/boot/dts/usb_a9g20.dts
new file mode 100644
index 000000000000..d66e2c00ac35
--- /dev/null
+++ b/arch/arm/boot/dts/usb_a9g20.dts
@@ -0,0 +1,30 @@
1/*
2 * usb_a9g20.dts - Device Tree file for Caloa USB A9G20 board
3 *
4 * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Licensed under GPLv2 or later.
7 */
8/dts-v1/;
9/include/ "at91sam9g20.dtsi"
10
11/ {
12 model = "Calao USB A9G20";
13 compatible = "calao,usb-a9g20", "atmel,at91sam9g20", "atmel,at91sam9";
14
15 chosen {
16 bootargs = "mem=64M console=ttyS0,115200 mtdparts=atmel_nand:128k(at91bootstrap),256k(barebox)ro,128k(bareboxenv),128k(bareboxenv2),4M(kernel),120M(rootfs),-(data) root=/dev/mtdblock5 rw rootfstype=ubifs";
17 };
18
19 memory@20000000 {
20 reg = <0x20000000 0x4000000>;
21 };
22
23 ahb {
24 apb {
25 dbgu: serial@fffff200 {
26 status = "okay";
27 };
28 };
29 };
30};
diff --git a/arch/arm/common/vic.c b/arch/arm/common/vic.c
index 7aa4262ada7a..197f81c77351 100644
--- a/arch/arm/common/vic.c
+++ b/arch/arm/common/vic.c
@@ -259,7 +259,6 @@ static void __init vic_disable(void __iomem *base)
259 writel(0, base + VIC_INT_SELECT); 259 writel(0, base + VIC_INT_SELECT);
260 writel(0, base + VIC_INT_ENABLE); 260 writel(0, base + VIC_INT_ENABLE);
261 writel(~0, base + VIC_INT_ENABLE_CLEAR); 261 writel(~0, base + VIC_INT_ENABLE_CLEAR);
262 writel(0, base + VIC_IRQ_STATUS);
263 writel(0, base + VIC_ITCR); 262 writel(0, base + VIC_ITCR);
264 writel(~0, base + VIC_INT_SOFT_CLEAR); 263 writel(~0, base + VIC_INT_SOFT_CLEAR);
265} 264}
diff --git a/arch/arm/include/asm/futex.h b/arch/arm/include/asm/futex.h
index 8c73900da9ed..253cc86318bf 100644
--- a/arch/arm/include/asm/futex.h
+++ b/arch/arm/include/asm/futex.h
@@ -25,17 +25,17 @@
25 25
26#ifdef CONFIG_SMP 26#ifdef CONFIG_SMP
27 27
28#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \ 28#define __futex_atomic_op(insn, ret, oldval, tmp, uaddr, oparg) \
29 smp_mb(); \ 29 smp_mb(); \
30 __asm__ __volatile__( \ 30 __asm__ __volatile__( \
31 "1: ldrex %1, [%2]\n" \ 31 "1: ldrex %1, [%3]\n" \
32 " " insn "\n" \ 32 " " insn "\n" \
33 "2: strex %1, %0, [%2]\n" \ 33 "2: strex %2, %0, [%3]\n" \
34 " teq %1, #0\n" \ 34 " teq %2, #0\n" \
35 " bne 1b\n" \ 35 " bne 1b\n" \
36 " mov %0, #0\n" \ 36 " mov %0, #0\n" \
37 __futex_atomic_ex_table("%4") \ 37 __futex_atomic_ex_table("%5") \
38 : "=&r" (ret), "=&r" (oldval) \ 38 : "=&r" (ret), "=&r" (oldval), "=&r" (tmp) \
39 : "r" (uaddr), "r" (oparg), "Ir" (-EFAULT) \ 39 : "r" (uaddr), "r" (oparg), "Ir" (-EFAULT) \
40 : "cc", "memory") 40 : "cc", "memory")
41 41
@@ -73,14 +73,14 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
73#include <linux/preempt.h> 73#include <linux/preempt.h>
74#include <asm/domain.h> 74#include <asm/domain.h>
75 75
76#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \ 76#define __futex_atomic_op(insn, ret, oldval, tmp, uaddr, oparg) \
77 __asm__ __volatile__( \ 77 __asm__ __volatile__( \
78 "1: " T(ldr) " %1, [%2]\n" \ 78 "1: " T(ldr) " %1, [%3]\n" \
79 " " insn "\n" \ 79 " " insn "\n" \
80 "2: " T(str) " %0, [%2]\n" \ 80 "2: " T(str) " %0, [%3]\n" \
81 " mov %0, #0\n" \ 81 " mov %0, #0\n" \
82 __futex_atomic_ex_table("%4") \ 82 __futex_atomic_ex_table("%5") \
83 : "=&r" (ret), "=&r" (oldval) \ 83 : "=&r" (ret), "=&r" (oldval), "=&r" (tmp) \
84 : "r" (uaddr), "r" (oparg), "Ir" (-EFAULT) \ 84 : "r" (uaddr), "r" (oparg), "Ir" (-EFAULT) \
85 : "cc", "memory") 85 : "cc", "memory")
86 86
@@ -117,7 +117,7 @@ futex_atomic_op_inuser (int encoded_op, u32 __user *uaddr)
117 int cmp = (encoded_op >> 24) & 15; 117 int cmp = (encoded_op >> 24) & 15;
118 int oparg = (encoded_op << 8) >> 20; 118 int oparg = (encoded_op << 8) >> 20;
119 int cmparg = (encoded_op << 20) >> 20; 119 int cmparg = (encoded_op << 20) >> 20;
120 int oldval = 0, ret; 120 int oldval = 0, ret, tmp;
121 121
122 if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28)) 122 if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
123 oparg = 1 << oparg; 123 oparg = 1 << oparg;
@@ -129,19 +129,19 @@ futex_atomic_op_inuser (int encoded_op, u32 __user *uaddr)
129 129
130 switch (op) { 130 switch (op) {
131 case FUTEX_OP_SET: 131 case FUTEX_OP_SET:
132 __futex_atomic_op("mov %0, %3", ret, oldval, uaddr, oparg); 132 __futex_atomic_op("mov %0, %4", ret, oldval, tmp, uaddr, oparg);
133 break; 133 break;
134 case FUTEX_OP_ADD: 134 case FUTEX_OP_ADD:
135 __futex_atomic_op("add %0, %1, %3", ret, oldval, uaddr, oparg); 135 __futex_atomic_op("add %0, %1, %4", ret, oldval, tmp, uaddr, oparg);
136 break; 136 break;
137 case FUTEX_OP_OR: 137 case FUTEX_OP_OR:
138 __futex_atomic_op("orr %0, %1, %3", ret, oldval, uaddr, oparg); 138 __futex_atomic_op("orr %0, %1, %4", ret, oldval, tmp, uaddr, oparg);
139 break; 139 break;
140 case FUTEX_OP_ANDN: 140 case FUTEX_OP_ANDN:
141 __futex_atomic_op("and %0, %1, %3", ret, oldval, uaddr, ~oparg); 141 __futex_atomic_op("and %0, %1, %4", ret, oldval, tmp, uaddr, ~oparg);
142 break; 142 break;
143 case FUTEX_OP_XOR: 143 case FUTEX_OP_XOR:
144 __futex_atomic_op("eor %0, %1, %3", ret, oldval, uaddr, oparg); 144 __futex_atomic_op("eor %0, %1, %4", ret, oldval, tmp, uaddr, oparg);
145 break; 145 break;
146 default: 146 default:
147 ret = -ENOSYS; 147 ret = -ENOSYS;
diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h
index 16bd48031583..99a6ed7e1bfd 100644
--- a/arch/arm/include/asm/hardware/cache-l2x0.h
+++ b/arch/arm/include/asm/hardware/cache-l2x0.h
@@ -45,8 +45,13 @@
45#define L2X0_CLEAN_INV_LINE_PA 0x7F0 45#define L2X0_CLEAN_INV_LINE_PA 0x7F0
46#define L2X0_CLEAN_INV_LINE_IDX 0x7F8 46#define L2X0_CLEAN_INV_LINE_IDX 0x7F8
47#define L2X0_CLEAN_INV_WAY 0x7FC 47#define L2X0_CLEAN_INV_WAY 0x7FC
48#define L2X0_LOCKDOWN_WAY_D 0x900 48/*
49#define L2X0_LOCKDOWN_WAY_I 0x904 49 * The lockdown registers repeat 8 times for L310, the L210 has only one
50 * D and one I lockdown register at 0x0900 and 0x0904.
51 */
52#define L2X0_LOCKDOWN_WAY_D_BASE 0x900
53#define L2X0_LOCKDOWN_WAY_I_BASE 0x904
54#define L2X0_LOCKDOWN_STRIDE 0x08
50#define L2X0_TEST_OPERATION 0xF00 55#define L2X0_TEST_OPERATION 0xF00
51#define L2X0_LINE_DATA 0xF10 56#define L2X0_LINE_DATA 0xF10
52#define L2X0_LINE_TAG 0xF30 57#define L2X0_LINE_TAG 0xF30
@@ -64,7 +69,7 @@
64#define L2X0_AUX_CTRL_MASK 0xc0000fff 69#define L2X0_AUX_CTRL_MASK 0xc0000fff
65#define L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT 16 70#define L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT 16
66#define L2X0_AUX_CTRL_WAY_SIZE_SHIFT 17 71#define L2X0_AUX_CTRL_WAY_SIZE_SHIFT 17
67#define L2X0_AUX_CTRL_WAY_SIZE_MASK (0x3 << 17) 72#define L2X0_AUX_CTRL_WAY_SIZE_MASK (0x7 << 17)
68#define L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT 22 73#define L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT 22
69#define L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT 26 74#define L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT 26
70#define L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT 27 75#define L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT 27
diff --git a/arch/arm/include/asm/localtimer.h b/arch/arm/include/asm/localtimer.h
index 080d74f8128d..ff66638ff54d 100644
--- a/arch/arm/include/asm/localtimer.h
+++ b/arch/arm/include/asm/localtimer.h
@@ -10,6 +10,8 @@
10#ifndef __ASM_ARM_LOCALTIMER_H 10#ifndef __ASM_ARM_LOCALTIMER_H
11#define __ASM_ARM_LOCALTIMER_H 11#define __ASM_ARM_LOCALTIMER_H
12 12
13#include <linux/errno.h>
14
13struct clock_event_device; 15struct clock_event_device;
14 16
15/* 17/*
diff --git a/arch/arm/include/asm/pmu.h b/arch/arm/include/asm/pmu.h
index 67c70a31a1be..b7e82c4aced6 100644
--- a/arch/arm/include/asm/pmu.h
+++ b/arch/arm/include/asm/pmu.h
@@ -41,7 +41,7 @@ struct arm_pmu_platdata {
41 * encoded error on failure. 41 * encoded error on failure.
42 */ 42 */
43extern struct platform_device * 43extern struct platform_device *
44reserve_pmu(enum arm_pmu_type device); 44reserve_pmu(enum arm_pmu_type type);
45 45
46/** 46/**
47 * release_pmu() - Relinquish control of the performance counters 47 * release_pmu() - Relinquish control of the performance counters
@@ -62,26 +62,26 @@ release_pmu(enum arm_pmu_type type);
62 * the actual hardware initialisation. 62 * the actual hardware initialisation.
63 */ 63 */
64extern int 64extern int
65init_pmu(enum arm_pmu_type device); 65init_pmu(enum arm_pmu_type type);
66 66
67#else /* CONFIG_CPU_HAS_PMU */ 67#else /* CONFIG_CPU_HAS_PMU */
68 68
69#include <linux/err.h> 69#include <linux/err.h>
70 70
71static inline struct platform_device * 71static inline struct platform_device *
72reserve_pmu(enum arm_pmu_type device) 72reserve_pmu(enum arm_pmu_type type)
73{ 73{
74 return ERR_PTR(-ENODEV); 74 return ERR_PTR(-ENODEV);
75} 75}
76 76
77static inline int 77static inline int
78release_pmu(struct platform_device *pdev) 78release_pmu(enum arm_pmu_type type)
79{ 79{
80 return -ENODEV; 80 return -ENODEV;
81} 81}
82 82
83static inline int 83static inline int
84init_pmu(enum arm_pmu_type device) 84init_pmu(enum arm_pmu_type type)
85{ 85{
86 return -ENODEV; 86 return -ENODEV;
87} 87}
diff --git a/arch/arm/include/asm/unistd.h b/arch/arm/include/asm/unistd.h
index 2c04ed5efeb5..c60a2944f95b 100644
--- a/arch/arm/include/asm/unistd.h
+++ b/arch/arm/include/asm/unistd.h
@@ -478,8 +478,8 @@
478/* 478/*
479 * Unimplemented (or alternatively implemented) syscalls 479 * Unimplemented (or alternatively implemented) syscalls
480 */ 480 */
481#define __IGNORE_fadvise64_64 1 481#define __IGNORE_fadvise64_64
482#define __IGNORE_migrate_pages 1 482#define __IGNORE_migrate_pages
483 483
484#endif /* __KERNEL__ */ 484#endif /* __KERNEL__ */
485#endif /* __ASM_ARM_UNISTD_H */ 485#endif /* __ASM_ARM_UNISTD_H */
diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c
index 4c851834f68e..6be3e2e4d838 100644
--- a/arch/arm/kernel/perf_event_v7.c
+++ b/arch/arm/kernel/perf_event_v7.c
@@ -321,8 +321,8 @@ static const unsigned armv7_a9_perf_map[PERF_COUNT_HW_MAX] = {
321 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, 321 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES,
322 [PERF_COUNT_HW_INSTRUCTIONS] = 322 [PERF_COUNT_HW_INSTRUCTIONS] =
323 ARMV7_PERFCTR_INST_OUT_OF_RENAME_STAGE, 323 ARMV7_PERFCTR_INST_OUT_OF_RENAME_STAGE,
324 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_COHERENT_LINE_HIT, 324 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_DCACHE_ACCESS,
325 [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_COHERENT_LINE_MISS, 325 [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_DCACHE_REFILL,
326 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE, 326 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
327 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 327 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
328 [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_CLOCK_CYCLES, 328 [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_CLOCK_CYCLES,
diff --git a/arch/arm/kernel/pmu.c b/arch/arm/kernel/pmu.c
index 2b70709376c3..c53474fe84df 100644
--- a/arch/arm/kernel/pmu.c
+++ b/arch/arm/kernel/pmu.c
@@ -31,7 +31,7 @@ static int __devinit pmu_register(struct platform_device *pdev,
31{ 31{
32 if (type < 0 || type >= ARM_NUM_PMU_DEVICES) { 32 if (type < 0 || type >= ARM_NUM_PMU_DEVICES) {
33 pr_warning("received registration request for unknown " 33 pr_warning("received registration request for unknown "
34 "device %d\n", type); 34 "PMU device type %d\n", type);
35 return -EINVAL; 35 return -EINVAL;
36 } 36 }
37 37
@@ -112,17 +112,17 @@ static int __init register_pmu_driver(void)
112device_initcall(register_pmu_driver); 112device_initcall(register_pmu_driver);
113 113
114struct platform_device * 114struct platform_device *
115reserve_pmu(enum arm_pmu_type device) 115reserve_pmu(enum arm_pmu_type type)
116{ 116{
117 struct platform_device *pdev; 117 struct platform_device *pdev;
118 118
119 if (test_and_set_bit_lock(device, &pmu_lock)) { 119 if (test_and_set_bit_lock(type, &pmu_lock)) {
120 pdev = ERR_PTR(-EBUSY); 120 pdev = ERR_PTR(-EBUSY);
121 } else if (pmu_devices[device] == NULL) { 121 } else if (pmu_devices[type] == NULL) {
122 clear_bit_unlock(device, &pmu_lock); 122 clear_bit_unlock(type, &pmu_lock);
123 pdev = ERR_PTR(-ENODEV); 123 pdev = ERR_PTR(-ENODEV);
124 } else { 124 } else {
125 pdev = pmu_devices[device]; 125 pdev = pmu_devices[type];
126 } 126 }
127 127
128 return pdev; 128 return pdev;
@@ -130,11 +130,11 @@ reserve_pmu(enum arm_pmu_type device)
130EXPORT_SYMBOL_GPL(reserve_pmu); 130EXPORT_SYMBOL_GPL(reserve_pmu);
131 131
132int 132int
133release_pmu(enum arm_pmu_type device) 133release_pmu(enum arm_pmu_type type)
134{ 134{
135 if (WARN_ON(!pmu_devices[device])) 135 if (WARN_ON(!pmu_devices[type]))
136 return -EINVAL; 136 return -EINVAL;
137 clear_bit_unlock(device, &pmu_lock); 137 clear_bit_unlock(type, &pmu_lock);
138 return 0; 138 return 0;
139} 139}
140EXPORT_SYMBOL_GPL(release_pmu); 140EXPORT_SYMBOL_GPL(release_pmu);
@@ -182,17 +182,17 @@ init_cpu_pmu(void)
182} 182}
183 183
184int 184int
185init_pmu(enum arm_pmu_type device) 185init_pmu(enum arm_pmu_type type)
186{ 186{
187 int err = 0; 187 int err = 0;
188 188
189 switch (device) { 189 switch (type) {
190 case ARM_PMU_DEVICE_CPU: 190 case ARM_PMU_DEVICE_CPU:
191 err = init_cpu_pmu(); 191 err = init_cpu_pmu();
192 break; 192 break;
193 default: 193 default:
194 pr_warning("attempt to initialise unknown device %d\n", 194 pr_warning("attempt to initialise PMU of unknown "
195 device); 195 "type %d\n", type);
196 err = -EINVAL; 196 err = -EINVAL;
197 } 197 }
198 198
diff --git a/arch/arm/kernel/relocate_kernel.S b/arch/arm/kernel/relocate_kernel.S
index 9cf4cbf8f95b..d0cdedf4864d 100644
--- a/arch/arm/kernel/relocate_kernel.S
+++ b/arch/arm/kernel/relocate_kernel.S
@@ -57,7 +57,8 @@ relocate_new_kernel:
57 mov r0,#0 57 mov r0,#0
58 ldr r1,kexec_mach_type 58 ldr r1,kexec_mach_type
59 ldr r2,kexec_boot_atags 59 ldr r2,kexec_boot_atags
60 mov pc,lr 60 ARM( mov pc, lr )
61 THUMB( bx lr )
61 62
62 .align 63 .align
63 64
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 70bca649e925..e514c76043b4 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -280,18 +280,19 @@ static void __init cacheid_init(void)
280 if (arch >= CPU_ARCH_ARMv6) { 280 if (arch >= CPU_ARCH_ARMv6) {
281 if ((cachetype & (7 << 29)) == 4 << 29) { 281 if ((cachetype & (7 << 29)) == 4 << 29) {
282 /* ARMv7 register format */ 282 /* ARMv7 register format */
283 arch = CPU_ARCH_ARMv7;
283 cacheid = CACHEID_VIPT_NONALIASING; 284 cacheid = CACHEID_VIPT_NONALIASING;
284 if ((cachetype & (3 << 14)) == 1 << 14) 285 if ((cachetype & (3 << 14)) == 1 << 14)
285 cacheid |= CACHEID_ASID_TAGGED; 286 cacheid |= CACHEID_ASID_TAGGED;
286 else if (cpu_has_aliasing_icache(CPU_ARCH_ARMv7))
287 cacheid |= CACHEID_VIPT_I_ALIASING;
288 } else if (cachetype & (1 << 23)) {
289 cacheid = CACHEID_VIPT_ALIASING;
290 } else { 287 } else {
291 cacheid = CACHEID_VIPT_NONALIASING; 288 arch = CPU_ARCH_ARMv6;
292 if (cpu_has_aliasing_icache(CPU_ARCH_ARMv6)) 289 if (cachetype & (1 << 23))
293 cacheid |= CACHEID_VIPT_I_ALIASING; 290 cacheid = CACHEID_VIPT_ALIASING;
291 else
292 cacheid = CACHEID_VIPT_NONALIASING;
294 } 293 }
294 if (cpu_has_aliasing_icache(arch))
295 cacheid |= CACHEID_VIPT_I_ALIASING;
295 } else { 296 } else {
296 cacheid = CACHEID_VIVT; 297 cacheid = CACHEID_VIVT;
297 } 298 }
diff --git a/arch/arm/kernel/smp_scu.c b/arch/arm/kernel/smp_scu.c
index 79ed5e7f204a..7fcddb75c877 100644
--- a/arch/arm/kernel/smp_scu.c
+++ b/arch/arm/kernel/smp_scu.c
@@ -13,6 +13,7 @@
13 13
14#include <asm/smp_scu.h> 14#include <asm/smp_scu.h>
15#include <asm/cacheflush.h> 15#include <asm/cacheflush.h>
16#include <asm/cputype.h>
16 17
17#define SCU_CTRL 0x00 18#define SCU_CTRL 0x00
18#define SCU_CONFIG 0x04 19#define SCU_CONFIG 0x04
@@ -37,6 +38,15 @@ void __init scu_enable(void __iomem *scu_base)
37{ 38{
38 u32 scu_ctrl; 39 u32 scu_ctrl;
39 40
41#ifdef CONFIG_ARM_ERRATA_764369
42 /* Cortex-A9 only */
43 if ((read_cpuid(CPUID_ID) & 0xff0ffff0) == 0x410fc090) {
44 scu_ctrl = __raw_readl(scu_base + 0x30);
45 if (!(scu_ctrl & 1))
46 __raw_writel(scu_ctrl | 0x1, scu_base + 0x30);
47 }
48#endif
49
40 scu_ctrl = __raw_readl(scu_base + SCU_CTRL); 50 scu_ctrl = __raw_readl(scu_base + SCU_CTRL);
41 /* already enabled? */ 51 /* already enabled? */
42 if (scu_ctrl & 1) 52 if (scu_ctrl & 1)
diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c
index 2c277d40cee6..01c186222f3b 100644
--- a/arch/arm/kernel/smp_twd.c
+++ b/arch/arm/kernel/smp_twd.c
@@ -137,8 +137,8 @@ void __cpuinit twd_timer_setup(struct clock_event_device *clk)
137 clk->max_delta_ns = clockevent_delta2ns(0xffffffff, clk); 137 clk->max_delta_ns = clockevent_delta2ns(0xffffffff, clk);
138 clk->min_delta_ns = clockevent_delta2ns(0xf, clk); 138 clk->min_delta_ns = clockevent_delta2ns(0xf, clk);
139 139
140 clockevents_register_device(clk);
141
140 /* Make sure our local interrupt controller has this enabled */ 142 /* Make sure our local interrupt controller has this enabled */
141 gic_enable_ppi(clk->irq); 143 gic_enable_ppi(clk->irq);
142
143 clockevents_register_device(clk);
144} 144}
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
index bf977f8514f6..4e66f62b8d41 100644
--- a/arch/arm/kernel/vmlinux.lds.S
+++ b/arch/arm/kernel/vmlinux.lds.S
@@ -23,8 +23,10 @@
23 23
24#if defined(CONFIG_SMP_ON_UP) && !defined(CONFIG_DEBUG_SPINLOCK) 24#if defined(CONFIG_SMP_ON_UP) && !defined(CONFIG_DEBUG_SPINLOCK)
25#define ARM_EXIT_KEEP(x) x 25#define ARM_EXIT_KEEP(x) x
26#define ARM_EXIT_DISCARD(x)
26#else 27#else
27#define ARM_EXIT_KEEP(x) 28#define ARM_EXIT_KEEP(x)
29#define ARM_EXIT_DISCARD(x) x
28#endif 30#endif
29 31
30OUTPUT_ARCH(arm) 32OUTPUT_ARCH(arm)
@@ -39,6 +41,11 @@ jiffies = jiffies_64 + 4;
39SECTIONS 41SECTIONS
40{ 42{
41 /* 43 /*
44 * XXX: The linker does not define how output sections are
45 * assigned to input sections when there are multiple statements
46 * matching the same input section name. There is no documented
47 * order of matching.
48 *
42 * unwind exit sections must be discarded before the rest of the 49 * unwind exit sections must be discarded before the rest of the
43 * unwind sections get included. 50 * unwind sections get included.
44 */ 51 */
@@ -47,6 +54,9 @@ SECTIONS
47 *(.ARM.extab.exit.text) 54 *(.ARM.extab.exit.text)
48 ARM_CPU_DISCARD(*(.ARM.exidx.cpuexit.text)) 55 ARM_CPU_DISCARD(*(.ARM.exidx.cpuexit.text))
49 ARM_CPU_DISCARD(*(.ARM.extab.cpuexit.text)) 56 ARM_CPU_DISCARD(*(.ARM.extab.cpuexit.text))
57 ARM_EXIT_DISCARD(EXIT_TEXT)
58 ARM_EXIT_DISCARD(EXIT_DATA)
59 EXIT_CALL
50#ifndef CONFIG_HOTPLUG 60#ifndef CONFIG_HOTPLUG
51 *(.ARM.exidx.devexit.text) 61 *(.ARM.exidx.devexit.text)
52 *(.ARM.extab.devexit.text) 62 *(.ARM.extab.devexit.text)
@@ -58,6 +68,8 @@ SECTIONS
58#ifndef CONFIG_SMP_ON_UP 68#ifndef CONFIG_SMP_ON_UP
59 *(.alt.smp.init) 69 *(.alt.smp.init)
60#endif 70#endif
71 *(.discard)
72 *(.discard.*)
61 } 73 }
62 74
63#ifdef CONFIG_XIP_KERNEL 75#ifdef CONFIG_XIP_KERNEL
@@ -279,9 +291,6 @@ SECTIONS
279 291
280 STABS_DEBUG 292 STABS_DEBUG
281 .comment 0 : { *(.comment) } 293 .comment 0 : { *(.comment) }
282
283 /* Default discards */
284 DISCARDS
285} 294}
286 295
287/* 296/*
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 22484670e7ba..4b59d96e1cd8 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -442,6 +442,17 @@ endif
442 442
443# ---------------------------------------------------------- 443# ----------------------------------------------------------
444 444
445comment "Generic Board Type"
446
447config MACH_AT91SAM_DT
448 bool "Atmel AT91SAM Evaluation Kits with device-tree support"
449 select USE_OF
450 help
451 Select this if you want to experiment device-tree with
452 an Atmel Evaluation Kit.
453
454# ----------------------------------------------------------
455
445comment "AT91 Board Options" 456comment "AT91 Board Options"
446 457
447config MTD_AT91_DATAFLASH_CARD 458config MTD_AT91_DATAFLASH_CARD
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index bf57e8b1c9d0..3ff245ebcad1 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -74,6 +74,9 @@ obj-$(CONFIG_MACH_SNAPPER_9260) += board-snapper9260.o
74# AT91SAM9G45 board-specific support 74# AT91SAM9G45 board-specific support
75obj-$(CONFIG_MACH_AT91SAM9M10G45EK) += board-sam9m10g45ek.o 75obj-$(CONFIG_MACH_AT91SAM9M10G45EK) += board-sam9m10g45ek.o
76 76
77# AT91SAM board with device-tree
78obj-$(CONFIG_MACH_AT91SAM_DT) += board-dt.o
79
77# AT91CAP9 board-specific support 80# AT91CAP9 board-specific support
78obj-$(CONFIG_MACH_AT91CAP9ADK) += board-cap9adk.o 81obj-$(CONFIG_MACH_AT91CAP9ADK) += board-cap9adk.o
79 82
diff --git a/arch/arm/mach-at91/Makefile.boot b/arch/arm/mach-at91/Makefile.boot
index 3462b815054a..08c665affde4 100644
--- a/arch/arm/mach-at91/Makefile.boot
+++ b/arch/arm/mach-at91/Makefile.boot
@@ -16,3 +16,5 @@ else
16params_phys-y := 0x20000100 16params_phys-y := 0x20000100
17initrd_phys-y := 0x20410000 17initrd_phys-y := 0x20410000
18endif 18endif
19
20dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9m10g45ek.dtb usb_a9g20.dtb
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index cb397be14448..f4518b49cb82 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -199,6 +199,14 @@ static struct clk_lookup periph_clocks_lookups[] = {
199 CLKDEV_CON_DEV_ID("t4_clk", "atmel_tcb.1", &tc4_clk), 199 CLKDEV_CON_DEV_ID("t4_clk", "atmel_tcb.1", &tc4_clk),
200 CLKDEV_CON_DEV_ID("t5_clk", "atmel_tcb.1", &tc5_clk), 200 CLKDEV_CON_DEV_ID("t5_clk", "atmel_tcb.1", &tc5_clk),
201 CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc_clk), 201 CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc_clk),
202 /* more usart lookup table for DT entries */
203 CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
204 CLKDEV_CON_DEV_ID("usart", "fffb0000.serial", &usart0_clk),
205 CLKDEV_CON_DEV_ID("usart", "fffb4000.serial", &usart1_clk),
206 CLKDEV_CON_DEV_ID("usart", "fffb8000.serial", &usart2_clk),
207 CLKDEV_CON_DEV_ID("usart", "fffd0000.serial", &usart3_clk),
208 CLKDEV_CON_DEV_ID("usart", "fffd4000.serial", &usart4_clk),
209 CLKDEV_CON_DEV_ID("usart", "fffd8000.serial", &usart5_clk),
202}; 210};
203 211
204static struct clk_lookup usart_clocks_lookups[] = { 212static struct clk_lookup usart_clocks_lookups[] = {
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index d522b47e30b5..6c8e3b5f669f 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -157,7 +157,7 @@ static struct clk_lookup periph_clocks_lookups[] = {
157 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk), 157 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
158 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk), 158 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
159 CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk), 159 CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
160 CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc1_clk), 160 CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
161 CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk), 161 CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
162 CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk), 162 CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
163 CLKDEV_CON_DEV_ID("pclk", "ssc.2", &ssc2_clk), 163 CLKDEV_CON_DEV_ID("pclk", "ssc.2", &ssc2_clk),
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index e04c5fb6f1ee..8baf5a1ed167 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -215,6 +215,12 @@ static struct clk_lookup periph_clocks_lookups[] = {
215 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tcb0_clk), 215 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tcb0_clk),
216 CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk), 216 CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
217 CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk), 217 CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
218 /* more usart lookup table for DT entries */
219 CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck),
220 CLKDEV_CON_DEV_ID("usart", "fff8c000.serial", &usart0_clk),
221 CLKDEV_CON_DEV_ID("usart", "fff90000.serial", &usart1_clk),
222 CLKDEV_CON_DEV_ID("usart", "fff94000.serial", &usart2_clk),
223 CLKDEV_CON_DEV_ID("usart", "fff98000.serial", &usart3_clk),
218}; 224};
219 225
220static struct clk_lookup usart_clocks_lookups[] = { 226static struct clk_lookup usart_clocks_lookups[] = {
diff --git a/arch/arm/mach-at91/board-dt.c b/arch/arm/mach-at91/board-dt.c
new file mode 100644
index 000000000000..0b7d32778210
--- /dev/null
+++ b/arch/arm/mach-at91/board-dt.c
@@ -0,0 +1,123 @@
1/*
2 * Setup code for AT91SAM Evaluation Kits with Device Tree support
3 *
4 * Covers: * AT91SAM9G45-EKES board
5 * * AT91SAM9M10-EKES board
6 * * AT91SAM9M10G45-EK board
7 *
8 * Copyright (C) 2011 Atmel,
9 * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>
10 *
11 * Licensed under GPLv2 or later.
12 */
13
14#include <linux/types.h>
15#include <linux/init.h>
16#include <linux/module.h>
17#include <linux/gpio.h>
18#include <linux/irqdomain.h>
19#include <linux/of_irq.h>
20#include <linux/of_platform.h>
21
22#include <mach/hardware.h>
23#include <mach/board.h>
24#include <mach/system_rev.h>
25#include <mach/at91sam9_smc.h>
26
27#include <asm/setup.h>
28#include <asm/irq.h>
29#include <asm/mach/arch.h>
30#include <asm/mach/map.h>
31#include <asm/mach/irq.h>
32
33#include "sam9_smc.h"
34#include "generic.h"
35
36
37static void __init ek_init_early(void)
38{
39 /* Initialize processor: 12.000 MHz crystal */
40 at91_initialize(12000000);
41
42 /* DGBU on ttyS0. (Rx & Tx only) */
43 at91_register_uart(0, 0, 0);
44
45 /* set serial console to ttyS0 (ie, DBGU) */
46 at91_set_serial_console(0);
47}
48
49/* det_pin is not connected */
50static struct atmel_nand_data __initdata ek_nand_data = {
51 .ale = 21,
52 .cle = 22,
53 .rdy_pin = AT91_PIN_PC8,
54 .enable_pin = AT91_PIN_PC14,
55};
56
57static struct sam9_smc_config __initdata ek_nand_smc_config = {
58 .ncs_read_setup = 0,
59 .nrd_setup = 2,
60 .ncs_write_setup = 0,
61 .nwe_setup = 2,
62
63 .ncs_read_pulse = 4,
64 .nrd_pulse = 4,
65 .ncs_write_pulse = 4,
66 .nwe_pulse = 4,
67
68 .read_cycle = 7,
69 .write_cycle = 7,
70
71 .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE,
72 .tdf_cycles = 3,
73};
74
75static void __init ek_add_device_nand(void)
76{
77 ek_nand_data.bus_width_16 = board_have_nand_16bit();
78 /* setup bus-width (8 or 16) */
79 if (ek_nand_data.bus_width_16)
80 ek_nand_smc_config.mode |= AT91_SMC_DBW_16;
81 else
82 ek_nand_smc_config.mode |= AT91_SMC_DBW_8;
83
84 /* configure chip-select 3 (NAND) */
85 sam9_smc_configure(3, &ek_nand_smc_config);
86
87 at91_add_device_nand(&ek_nand_data);
88}
89
90static const struct of_device_id aic_of_match[] __initconst = {
91 { .compatible = "atmel,at91rm9200-aic", },
92 {},
93};
94
95static void __init at91_dt_init_irq(void)
96{
97 irq_domain_generate_simple(aic_of_match, 0xfffff000, 0);
98 at91_init_irq_default();
99}
100
101static void __init at91_dt_device_init(void)
102{
103 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
104
105 /* NAND */
106 ek_add_device_nand();
107}
108
109static const char *at91_dt_board_compat[] __initdata = {
110 "atmel,at91sam9m10g45ek",
111 "calao,usb-a9g20",
112 NULL
113};
114
115DT_MACHINE_START(at91sam_dt, "Atmel AT91SAM (Device Tree)")
116 /* Maintainer: Atmel */
117 .timer = &at91sam926x_timer,
118 .map_io = at91_map_io,
119 .init_early = ek_init_early,
120 .init_irq = at91_dt_init_irq,
121 .init_machine = at91_dt_device_init,
122 .dt_compat = at91_dt_board_compat,
123MACHINE_END
diff --git a/arch/arm/mach-cns3xxx/include/mach/entry-macro.S b/arch/arm/mach-cns3xxx/include/mach/entry-macro.S
index 6bd83ed90afe..d87bfc397d39 100644
--- a/arch/arm/mach-cns3xxx/include/mach/entry-macro.S
+++ b/arch/arm/mach-cns3xxx/include/mach/entry-macro.S
@@ -8,7 +8,6 @@
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 */ 9 */
10 10
11#include <mach/hardware.h>
12#include <asm/hardware/entry-macro-gic.S> 11#include <asm/hardware/entry-macro-gic.S>
13 12
14 .macro disable_fiq 13 .macro disable_fiq
diff --git a/arch/arm/mach-cns3xxx/include/mach/system.h b/arch/arm/mach-cns3xxx/include/mach/system.h
index 58bb03ae3cf4..4f16c9b79f78 100644
--- a/arch/arm/mach-cns3xxx/include/mach/system.h
+++ b/arch/arm/mach-cns3xxx/include/mach/system.h
@@ -13,7 +13,6 @@
13 13
14#include <linux/io.h> 14#include <linux/io.h>
15#include <asm/proc-fns.h> 15#include <asm/proc-fns.h>
16#include <mach/hardware.h>
17 16
18static inline void arch_idle(void) 17static inline void arch_idle(void)
19{ 18{
diff --git a/arch/arm/mach-cns3xxx/include/mach/uncompress.h b/arch/arm/mach-cns3xxx/include/mach/uncompress.h
index de8ead9b91f7..a91b6058ab4f 100644
--- a/arch/arm/mach-cns3xxx/include/mach/uncompress.h
+++ b/arch/arm/mach-cns3xxx/include/mach/uncompress.h
@@ -8,7 +8,6 @@
8 */ 8 */
9 9
10#include <asm/mach-types.h> 10#include <asm/mach-types.h>
11#include <mach/hardware.h>
12#include <mach/cns3xxx.h> 11#include <mach/cns3xxx.h>
13 12
14#define AMBA_UART_DR(base) (*(volatile unsigned char *)((base) + 0x00)) 13#define AMBA_UART_DR(base) (*(volatile unsigned char *)((base) + 0x00))
diff --git a/arch/arm/mach-cns3xxx/pcie.c b/arch/arm/mach-cns3xxx/pcie.c
index 06fd25d70aec..0f8fca48a5ed 100644
--- a/arch/arm/mach-cns3xxx/pcie.c
+++ b/arch/arm/mach-cns3xxx/pcie.c
@@ -49,7 +49,7 @@ static struct cns3xxx_pcie *sysdata_to_cnspci(void *sysdata)
49 return &cns3xxx_pcie[root->domain]; 49 return &cns3xxx_pcie[root->domain];
50} 50}
51 51
52static struct cns3xxx_pcie *pdev_to_cnspci(struct pci_dev *dev) 52static struct cns3xxx_pcie *pdev_to_cnspci(const struct pci_dev *dev)
53{ 53{
54 return sysdata_to_cnspci(dev->sysdata); 54 return sysdata_to_cnspci(dev->sysdata);
55} 55}
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index bd5394537c88..008d51407cd7 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -115,6 +115,32 @@ static struct spi_board_info da850evm_spi_info[] = {
115 }, 115 },
116}; 116};
117 117
118#ifdef CONFIG_MTD
119static void da850_evm_m25p80_notify_add(struct mtd_info *mtd)
120{
121 char *mac_addr = davinci_soc_info.emac_pdata->mac_addr;
122 size_t retlen;
123
124 if (!strcmp(mtd->name, "MAC-Address")) {
125 mtd->read(mtd, 0, ETH_ALEN, &retlen, mac_addr);
126 if (retlen == ETH_ALEN)
127 pr_info("Read MAC addr from SPI Flash: %pM\n",
128 mac_addr);
129 }
130}
131
132static struct mtd_notifier da850evm_spi_notifier = {
133 .add = da850_evm_m25p80_notify_add,
134};
135
136static void da850_evm_setup_mac_addr(void)
137{
138 register_mtd_user(&da850evm_spi_notifier);
139}
140#else
141static void da850_evm_setup_mac_addr(void) { }
142#endif
143
118static struct mtd_partition da850_evm_norflash_partition[] = { 144static struct mtd_partition da850_evm_norflash_partition[] = {
119 { 145 {
120 .name = "bootloaders + env", 146 .name = "bootloaders + env",
@@ -1244,6 +1270,8 @@ static __init void da850_evm_init(void)
1244 if (ret) 1270 if (ret)
1245 pr_warning("da850_evm_init: sata registration failed: %d\n", 1271 pr_warning("da850_evm_init: sata registration failed: %d\n",
1246 ret); 1272 ret);
1273
1274 da850_evm_setup_mac_addr();
1247} 1275}
1248 1276
1249#ifdef CONFIG_SERIAL_8250_CONSOLE 1277#ifdef CONFIG_SERIAL_8250_CONSOLE
diff --git a/arch/arm/mach-davinci/include/mach/psc.h b/arch/arm/mach-davinci/include/mach/psc.h
index 47fd0bc3d3e7..fa59c097223d 100644
--- a/arch/arm/mach-davinci/include/mach/psc.h
+++ b/arch/arm/mach-davinci/include/mach/psc.h
@@ -243,7 +243,7 @@
243#define PSC_STATE_DISABLE 2 243#define PSC_STATE_DISABLE 2
244#define PSC_STATE_ENABLE 3 244#define PSC_STATE_ENABLE 3
245 245
246#define MDSTAT_STATE_MASK 0x1f 246#define MDSTAT_STATE_MASK 0x3f
247#define MDCTL_FORCE BIT(31) 247#define MDCTL_FORCE BIT(31)
248 248
249#ifndef __ASSEMBLER__ 249#ifndef __ASSEMBLER__
diff --git a/arch/arm/mach-davinci/sleep.S b/arch/arm/mach-davinci/sleep.S
index fb5e72b532b0..5f1e045a3ad1 100644
--- a/arch/arm/mach-davinci/sleep.S
+++ b/arch/arm/mach-davinci/sleep.S
@@ -217,7 +217,11 @@ ddr2clk_stop_done:
217ENDPROC(davinci_ddr_psc_config) 217ENDPROC(davinci_ddr_psc_config)
218 218
219CACHE_FLUSH: 219CACHE_FLUSH:
220 .word arm926_flush_kern_cache_all 220#ifdef CONFIG_CPU_V6
221 .word v6_flush_kern_cache_all
222#else
223 .word arm926_flush_kern_cache_all
224#endif
221 225
222ENTRY(davinci_cpu_suspend_sz) 226ENTRY(davinci_cpu_suspend_sz)
223 .word . - davinci_cpu_suspend 227 .word . - davinci_cpu_suspend
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index 83dce859886d..a9e0dae86a26 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -158,7 +158,7 @@ void __init dove_spi0_init(void)
158 158
159void __init dove_spi1_init(void) 159void __init dove_spi1_init(void)
160{ 160{
161 orion_spi_init(DOVE_SPI1_PHYS_BASE, get_tclk()); 161 orion_spi_1_init(DOVE_SPI1_PHYS_BASE, get_tclk());
162} 162}
163 163
164/***************************************************************************** 164/*****************************************************************************
diff --git a/arch/arm/mach-ep93xx/include/mach/ts72xx.h b/arch/arm/mach-ep93xx/include/mach/ts72xx.h
index 0eabec62cd9d..f1397a13e76b 100644
--- a/arch/arm/mach-ep93xx/include/mach/ts72xx.h
+++ b/arch/arm/mach-ep93xx/include/mach/ts72xx.h
@@ -6,7 +6,7 @@
6 * TS72xx memory map: 6 * TS72xx memory map:
7 * 7 *
8 * virt phys size 8 * virt phys size
9 * febff000 22000000 4K model number register 9 * febff000 22000000 4K model number register (bits 0-2)
10 * febfe000 22400000 4K options register 10 * febfe000 22400000 4K options register
11 * febfd000 22800000 4K options register #2 11 * febfd000 22800000 4K options register #2
12 * febf9000 10800000 4K TS-5620 RTC index register 12 * febf9000 10800000 4K TS-5620 RTC index register
@@ -20,6 +20,9 @@
20#define TS72XX_MODEL_TS7200 0x00 20#define TS72XX_MODEL_TS7200 0x00
21#define TS72XX_MODEL_TS7250 0x01 21#define TS72XX_MODEL_TS7250 0x01
22#define TS72XX_MODEL_TS7260 0x02 22#define TS72XX_MODEL_TS7260 0x02
23#define TS72XX_MODEL_TS7300 0x03
24#define TS72XX_MODEL_TS7400 0x04
25#define TS72XX_MODEL_MASK 0x07
23 26
24 27
25#define TS72XX_OPTIONS_PHYS_BASE 0x22400000 28#define TS72XX_OPTIONS_PHYS_BASE 0x22400000
@@ -51,19 +54,34 @@
51 54
52#ifndef __ASSEMBLY__ 55#ifndef __ASSEMBLY__
53 56
57static inline int ts72xx_model(void)
58{
59 return __raw_readb(TS72XX_MODEL_VIRT_BASE) & TS72XX_MODEL_MASK;
60}
61
54static inline int board_is_ts7200(void) 62static inline int board_is_ts7200(void)
55{ 63{
56 return __raw_readb(TS72XX_MODEL_VIRT_BASE) == TS72XX_MODEL_TS7200; 64 return ts72xx_model() == TS72XX_MODEL_TS7200;
57} 65}
58 66
59static inline int board_is_ts7250(void) 67static inline int board_is_ts7250(void)
60{ 68{
61 return __raw_readb(TS72XX_MODEL_VIRT_BASE) == TS72XX_MODEL_TS7250; 69 return ts72xx_model() == TS72XX_MODEL_TS7250;
62} 70}
63 71
64static inline int board_is_ts7260(void) 72static inline int board_is_ts7260(void)
65{ 73{
66 return __raw_readb(TS72XX_MODEL_VIRT_BASE) == TS72XX_MODEL_TS7260; 74 return ts72xx_model() == TS72XX_MODEL_TS7260;
75}
76
77static inline int board_is_ts7300(void)
78{
79 return ts72xx_model() == TS72XX_MODEL_TS7300;
80}
81
82static inline int board_is_ts7400(void)
83{
84 return ts72xx_model() == TS72XX_MODEL_TS7400;
67} 85}
68 86
69static inline int is_max197_installed(void) 87static inline int is_max197_installed(void)
diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c
index 851dea018578..86964d2e9e1b 100644
--- a/arch/arm/mach-exynos4/clock.c
+++ b/arch/arm/mach-exynos4/clock.c
@@ -520,7 +520,7 @@ static struct clk init_clocks_off[] = {
520 .ctrlbit = (1 << 21), 520 .ctrlbit = (1 << 21),
521 }, { 521 }, {
522 .name = "ac97", 522 .name = "ac97",
523 .id = -1, 523 .devname = "samsung-ac97",
524 .enable = exynos4_clk_ip_peril_ctrl, 524 .enable = exynos4_clk_ip_peril_ctrl,
525 .ctrlbit = (1 << 27), 525 .ctrlbit = (1 << 27),
526 }, { 526 }, {
@@ -899,8 +899,7 @@ static struct clksrc_clk clksrcs[] = {
899 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 28, .size = 4 }, 899 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 28, .size = 4 },
900 }, { 900 }, {
901 .clk = { 901 .clk = {
902 .name = "sclk_cam", 902 .name = "sclk_cam0",
903 .devname = "exynos4-fimc.0",
904 .enable = exynos4_clksrc_mask_cam_ctrl, 903 .enable = exynos4_clksrc_mask_cam_ctrl,
905 .ctrlbit = (1 << 16), 904 .ctrlbit = (1 << 16),
906 }, 905 },
@@ -909,8 +908,7 @@ static struct clksrc_clk clksrcs[] = {
909 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 16, .size = 4 }, 908 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 16, .size = 4 },
910 }, { 909 }, {
911 .clk = { 910 .clk = {
912 .name = "sclk_cam", 911 .name = "sclk_cam1",
913 .devname = "exynos4-fimc.1",
914 .enable = exynos4_clksrc_mask_cam_ctrl, 912 .enable = exynos4_clksrc_mask_cam_ctrl,
915 .ctrlbit = (1 << 20), 913 .ctrlbit = (1 << 20),
916 }, 914 },
@@ -1160,7 +1158,7 @@ void __init_or_cpufreq exynos4_setup_clocks(void)
1160 1158
1161 vpllsrc = clk_get_rate(&clk_vpllsrc.clk); 1159 vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
1162 vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0), 1160 vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
1163 __raw_readl(S5P_VPLL_CON1), pll_4650); 1161 __raw_readl(S5P_VPLL_CON1), pll_4650c);
1164 1162
1165 clk_fout_apll.ops = &exynos4_fout_apll_ops; 1163 clk_fout_apll.ops = &exynos4_fout_apll_ops;
1166 clk_fout_mpll.rate = mpll; 1164 clk_fout_mpll.rate = mpll;
diff --git a/arch/arm/mach-exynos4/cpu.c b/arch/arm/mach-exynos4/cpu.c
index 2d8a40c9e6e5..746d6fc6d397 100644
--- a/arch/arm/mach-exynos4/cpu.c
+++ b/arch/arm/mach-exynos4/cpu.c
@@ -24,12 +24,13 @@
24#include <plat/exynos4.h> 24#include <plat/exynos4.h>
25#include <plat/adc-core.h> 25#include <plat/adc-core.h>
26#include <plat/sdhci.h> 26#include <plat/sdhci.h>
27#include <plat/devs.h>
28#include <plat/fb-core.h> 27#include <plat/fb-core.h>
29#include <plat/fimc-core.h> 28#include <plat/fimc-core.h>
30#include <plat/iic-core.h> 29#include <plat/iic-core.h>
30#include <plat/reset.h>
31 31
32#include <mach/regs-irq.h> 32#include <mach/regs-irq.h>
33#include <mach/regs-pmu.h>
33 34
34extern int combiner_init(unsigned int combiner_nr, void __iomem *base, 35extern int combiner_init(unsigned int combiner_nr, void __iomem *base,
35 unsigned int irq_start); 36 unsigned int irq_start);
@@ -128,6 +129,11 @@ static void exynos4_idle(void)
128 local_irq_enable(); 129 local_irq_enable();
129} 130}
130 131
132static void exynos4_sw_reset(void)
133{
134 __raw_writel(0x1, S5P_SWRESET);
135}
136
131/* 137/*
132 * exynos4_map_io 138 * exynos4_map_io
133 * 139 *
@@ -241,5 +247,8 @@ int __init exynos4_init(void)
241 /* set idle function */ 247 /* set idle function */
242 pm_idle = exynos4_idle; 248 pm_idle = exynos4_idle;
243 249
250 /* set sw_reset function */
251 s5p_reset_hook = exynos4_sw_reset;
252
244 return sysdev_register(&exynos4_sysdev); 253 return sysdev_register(&exynos4_sysdev);
245} 254}
diff --git a/arch/arm/mach-exynos4/include/mach/irqs.h b/arch/arm/mach-exynos4/include/mach/irqs.h
index 934d2a493982..f8952f8f3757 100644
--- a/arch/arm/mach-exynos4/include/mach/irqs.h
+++ b/arch/arm/mach-exynos4/include/mach/irqs.h
@@ -80,9 +80,8 @@
80#define IRQ_HSMMC3 IRQ_SPI(76) 80#define IRQ_HSMMC3 IRQ_SPI(76)
81#define IRQ_DWMCI IRQ_SPI(77) 81#define IRQ_DWMCI IRQ_SPI(77)
82 82
83#define IRQ_MIPICSI0 IRQ_SPI(78) 83#define IRQ_MIPI_CSIS0 IRQ_SPI(78)
84 84#define IRQ_MIPI_CSIS1 IRQ_SPI(80)
85#define IRQ_MIPICSI1 IRQ_SPI(80)
86 85
87#define IRQ_ONENAND_AUDI IRQ_SPI(82) 86#define IRQ_ONENAND_AUDI IRQ_SPI(82)
88#define IRQ_ROTATOR IRQ_SPI(83) 87#define IRQ_ROTATOR IRQ_SPI(83)
diff --git a/arch/arm/mach-exynos4/include/mach/regs-pmu.h b/arch/arm/mach-exynos4/include/mach/regs-pmu.h
index fa49bbb8e7b0..cdf9b47c303c 100644
--- a/arch/arm/mach-exynos4/include/mach/regs-pmu.h
+++ b/arch/arm/mach-exynos4/include/mach/regs-pmu.h
@@ -29,6 +29,8 @@
29#define S5P_USE_STANDBY_WFE1 (1 << 25) 29#define S5P_USE_STANDBY_WFE1 (1 << 25)
30#define S5P_USE_MASK ((0x3 << 16) | (0x3 << 24)) 30#define S5P_USE_MASK ((0x3 << 16) | (0x3 << 24))
31 31
32#define S5P_SWRESET S5P_PMUREG(0x0400)
33
32#define S5P_WAKEUP_STAT S5P_PMUREG(0x0600) 34#define S5P_WAKEUP_STAT S5P_PMUREG(0x0600)
33#define S5P_EINT_WAKEUP_MASK S5P_PMUREG(0x0604) 35#define S5P_EINT_WAKEUP_MASK S5P_PMUREG(0x0604)
34#define S5P_WAKEUP_MASK S5P_PMUREG(0x0608) 36#define S5P_WAKEUP_MASK S5P_PMUREG(0x0608)
diff --git a/arch/arm/mach-exynos4/irq-eint.c b/arch/arm/mach-exynos4/irq-eint.c
index 9d87d2ac7f68..badb8c66fc9b 100644
--- a/arch/arm/mach-exynos4/irq-eint.c
+++ b/arch/arm/mach-exynos4/irq-eint.c
@@ -23,6 +23,8 @@
23 23
24#include <mach/regs-gpio.h> 24#include <mach/regs-gpio.h>
25 25
26#include <asm/mach/irq.h>
27
26static DEFINE_SPINLOCK(eint_lock); 28static DEFINE_SPINLOCK(eint_lock);
27 29
28static unsigned int eint0_15_data[16]; 30static unsigned int eint0_15_data[16];
@@ -184,8 +186,11 @@ static inline void exynos4_irq_demux_eint(unsigned int start)
184 186
185static void exynos4_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc) 187static void exynos4_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
186{ 188{
189 struct irq_chip *chip = irq_get_chip(irq);
190 chained_irq_enter(chip, desc);
187 exynos4_irq_demux_eint(IRQ_EINT(16)); 191 exynos4_irq_demux_eint(IRQ_EINT(16));
188 exynos4_irq_demux_eint(IRQ_EINT(24)); 192 exynos4_irq_demux_eint(IRQ_EINT(24));
193 chained_irq_exit(chip, desc);
189} 194}
190 195
191static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc) 196static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
@@ -193,6 +198,7 @@ static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
193 u32 *irq_data = irq_get_handler_data(irq); 198 u32 *irq_data = irq_get_handler_data(irq);
194 struct irq_chip *chip = irq_get_chip(irq); 199 struct irq_chip *chip = irq_get_chip(irq);
195 200
201 chained_irq_enter(chip, desc);
196 chip->irq_mask(&desc->irq_data); 202 chip->irq_mask(&desc->irq_data);
197 203
198 if (chip->irq_ack) 204 if (chip->irq_ack)
@@ -201,6 +207,7 @@ static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
201 generic_handle_irq(*irq_data); 207 generic_handle_irq(*irq_data);
202 208
203 chip->irq_unmask(&desc->irq_data); 209 chip->irq_unmask(&desc->irq_data);
210 chained_irq_exit(chip, desc);
204} 211}
205 212
206int __init exynos4_init_irq_eint(void) 213int __init exynos4_init_irq_eint(void)
diff --git a/arch/arm/mach-exynos4/mach-universal_c210.c b/arch/arm/mach-exynos4/mach-universal_c210.c
index 0e280d12301e..b3b5d8911004 100644
--- a/arch/arm/mach-exynos4/mach-universal_c210.c
+++ b/arch/arm/mach-exynos4/mach-universal_c210.c
@@ -79,7 +79,7 @@ static struct s3c2410_uartcfg universal_uartcfgs[] __initdata = {
79}; 79};
80 80
81static struct regulator_consumer_supply max8952_consumer = 81static struct regulator_consumer_supply max8952_consumer =
82 REGULATOR_SUPPLY("vddarm", NULL); 82 REGULATOR_SUPPLY("vdd_arm", NULL);
83 83
84static struct max8952_platform_data universal_max8952_pdata __initdata = { 84static struct max8952_platform_data universal_max8952_pdata __initdata = {
85 .gpio_vid0 = EXYNOS4_GPX0(3), 85 .gpio_vid0 = EXYNOS4_GPX0(3),
@@ -105,7 +105,7 @@ static struct max8952_platform_data universal_max8952_pdata __initdata = {
105}; 105};
106 106
107static struct regulator_consumer_supply lp3974_buck1_consumer = 107static struct regulator_consumer_supply lp3974_buck1_consumer =
108 REGULATOR_SUPPLY("vddint", NULL); 108 REGULATOR_SUPPLY("vdd_int", NULL);
109 109
110static struct regulator_consumer_supply lp3974_buck2_consumer = 110static struct regulator_consumer_supply lp3974_buck2_consumer =
111 REGULATOR_SUPPLY("vddg3d", NULL); 111 REGULATOR_SUPPLY("vddg3d", NULL);
diff --git a/arch/arm/mach-exynos4/mct.c b/arch/arm/mach-exynos4/mct.c
index 1ae059b7ad7b..ddd86864fb83 100644
--- a/arch/arm/mach-exynos4/mct.c
+++ b/arch/arm/mach-exynos4/mct.c
@@ -132,12 +132,18 @@ static cycle_t exynos4_frc_read(struct clocksource *cs)
132 return ((cycle_t)hi << 32) | lo; 132 return ((cycle_t)hi << 32) | lo;
133} 133}
134 134
135static void exynos4_frc_resume(struct clocksource *cs)
136{
137 exynos4_mct_frc_start(0, 0);
138}
139
135struct clocksource mct_frc = { 140struct clocksource mct_frc = {
136 .name = "mct-frc", 141 .name = "mct-frc",
137 .rating = 400, 142 .rating = 400,
138 .read = exynos4_frc_read, 143 .read = exynos4_frc_read,
139 .mask = CLOCKSOURCE_MASK(64), 144 .mask = CLOCKSOURCE_MASK(64),
140 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 145 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
146 .resume = exynos4_frc_resume,
141}; 147};
142 148
143static void __init exynos4_clocksource_init(void) 149static void __init exynos4_clocksource_init(void)
@@ -389,9 +395,11 @@ static void exynos4_mct_tick_init(struct clock_event_device *evt)
389} 395}
390 396
391/* Setup the local clock events for a CPU */ 397/* Setup the local clock events for a CPU */
392void __cpuinit local_timer_setup(struct clock_event_device *evt) 398int __cpuinit local_timer_setup(struct clock_event_device *evt)
393{ 399{
394 exynos4_mct_tick_init(evt); 400 exynos4_mct_tick_init(evt);
401
402 return 0;
395} 403}
396 404
397int local_timer_ack(void) 405int local_timer_ack(void)
diff --git a/arch/arm/mach-exynos4/platsmp.c b/arch/arm/mach-exynos4/platsmp.c
index 7c2282c6ba81..df6ef1b2f98b 100644
--- a/arch/arm/mach-exynos4/platsmp.c
+++ b/arch/arm/mach-exynos4/platsmp.c
@@ -106,6 +106,8 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
106 */ 106 */
107 spin_lock(&boot_lock); 107 spin_lock(&boot_lock);
108 spin_unlock(&boot_lock); 108 spin_unlock(&boot_lock);
109
110 set_cpu_online(cpu, true);
109} 111}
110 112
111int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) 113int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
diff --git a/arch/arm/mach-exynos4/setup-keypad.c b/arch/arm/mach-exynos4/setup-keypad.c
index 1ee0ebff111f..7862bfb5933d 100644
--- a/arch/arm/mach-exynos4/setup-keypad.c
+++ b/arch/arm/mach-exynos4/setup-keypad.c
@@ -19,15 +19,16 @@ void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols)
19 19
20 if (rows > 8) { 20 if (rows > 8) {
21 /* Set all the necessary GPX2 pins: KP_ROW[0~7] */ 21 /* Set all the necessary GPX2 pins: KP_ROW[0~7] */
22 s3c_gpio_cfgrange_nopull(EXYNOS4_GPX2(0), 8, S3C_GPIO_SFN(3)); 22 s3c_gpio_cfgall_range(EXYNOS4_GPX2(0), 8, S3C_GPIO_SFN(3),
23 S3C_GPIO_PULL_UP);
23 24
24 /* Set all the necessary GPX3 pins: KP_ROW[8~] */ 25 /* Set all the necessary GPX3 pins: KP_ROW[8~] */
25 s3c_gpio_cfgrange_nopull(EXYNOS4_GPX3(0), (rows - 8), 26 s3c_gpio_cfgall_range(EXYNOS4_GPX3(0), (rows - 8),
26 S3C_GPIO_SFN(3)); 27 S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
27 } else { 28 } else {
28 /* Set all the necessary GPX2 pins: KP_ROW[x] */ 29 /* Set all the necessary GPX2 pins: KP_ROW[x] */
29 s3c_gpio_cfgrange_nopull(EXYNOS4_GPX2(0), rows, 30 s3c_gpio_cfgall_range(EXYNOS4_GPX2(0), rows, S3C_GPIO_SFN(3),
30 S3C_GPIO_SFN(3)); 31 S3C_GPIO_PULL_UP);
31 } 32 }
32 33
33 /* Set all the necessary GPX1 pins to special-function 3: KP_COL[x] */ 34 /* Set all the necessary GPX1 pins to special-function 3: KP_COL[x] */
diff --git a/arch/arm/mach-exynos4/setup-usb-phy.c b/arch/arm/mach-exynos4/setup-usb-phy.c
index 0883c1b824b9..39aca045f660 100644
--- a/arch/arm/mach-exynos4/setup-usb-phy.c
+++ b/arch/arm/mach-exynos4/setup-usb-phy.c
@@ -82,7 +82,7 @@ static int exynos4_usb_phy1_init(struct platform_device *pdev)
82 82
83 rstcon &= ~(HOST_LINK_PORT_SWRST_MASK | PHY1_SWRST_MASK); 83 rstcon &= ~(HOST_LINK_PORT_SWRST_MASK | PHY1_SWRST_MASK);
84 writel(rstcon, EXYNOS4_RSTCON); 84 writel(rstcon, EXYNOS4_RSTCON);
85 udelay(50); 85 udelay(80);
86 86
87 clk_disable(otg_clk); 87 clk_disable(otg_clk);
88 clk_put(otg_clk); 88 clk_put(otg_clk);
diff --git a/arch/arm/mach-footbridge/Kconfig b/arch/arm/mach-footbridge/Kconfig
index dc26fff22cf0..c8e7afcf14ec 100644
--- a/arch/arm/mach-footbridge/Kconfig
+++ b/arch/arm/mach-footbridge/Kconfig
@@ -62,6 +62,7 @@ config ARCH_EBSA285_HOST
62config ARCH_NETWINDER 62config ARCH_NETWINDER
63 bool "NetWinder" 63 bool "NetWinder"
64 select CLKSRC_I8253 64 select CLKSRC_I8253
65 select CLKEVT_I8253
65 select FOOTBRIDGE_HOST 66 select FOOTBRIDGE_HOST
66 select ISA 67 select ISA
67 select ISA_DMA 68 select ISA_DMA
diff --git a/arch/arm/mach-footbridge/dc21285.c b/arch/arm/mach-footbridge/dc21285.c
index 1331fff51ae2..18c32a5541d9 100644
--- a/arch/arm/mach-footbridge/dc21285.c
+++ b/arch/arm/mach-footbridge/dc21285.c
@@ -18,6 +18,7 @@
18#include <linux/irq.h> 18#include <linux/irq.h>
19#include <linux/io.h> 19#include <linux/io.h>
20#include <linux/spinlock.h> 20#include <linux/spinlock.h>
21#include <video/vga.h>
21 22
22#include <asm/irq.h> 23#include <asm/irq.h>
23#include <asm/system.h> 24#include <asm/system.h>
diff --git a/arch/arm/mach-imx/mach-cpuimx27.c b/arch/arm/mach-imx/mach-cpuimx27.c
index 87887ac5806b..f851fe903687 100644
--- a/arch/arm/mach-imx/mach-cpuimx27.c
+++ b/arch/arm/mach-imx/mach-cpuimx27.c
@@ -310,7 +310,7 @@ static struct sys_timer eukrea_cpuimx27_timer = {
310 .init = eukrea_cpuimx27_timer_init, 310 .init = eukrea_cpuimx27_timer_init,
311}; 311};
312 312
313MACHINE_START(CPUIMX27, "EUKREA CPUIMX27") 313MACHINE_START(EUKREA_CPUIMX27, "EUKREA CPUIMX27")
314 .boot_params = MX27_PHYS_OFFSET + 0x100, 314 .boot_params = MX27_PHYS_OFFSET + 0x100,
315 .map_io = mx27_map_io, 315 .map_io = mx27_map_io,
316 .init_early = imx27_init_early, 316 .init_early = imx27_init_early,
diff --git a/arch/arm/mach-imx/mach-cpuimx35.c b/arch/arm/mach-imx/mach-cpuimx35.c
index f39a478ba1a6..4bd083ba9af2 100644
--- a/arch/arm/mach-imx/mach-cpuimx35.c
+++ b/arch/arm/mach-imx/mach-cpuimx35.c
@@ -192,7 +192,7 @@ struct sys_timer eukrea_cpuimx35_timer = {
192 .init = eukrea_cpuimx35_timer_init, 192 .init = eukrea_cpuimx35_timer_init,
193}; 193};
194 194
195MACHINE_START(EUKREA_CPUIMX35, "Eukrea CPUIMX35") 195MACHINE_START(EUKREA_CPUIMX35SD, "Eukrea CPUIMX35")
196 /* Maintainer: Eukrea Electromatique */ 196 /* Maintainer: Eukrea Electromatique */
197 .boot_params = MX3x_PHYS_OFFSET + 0x100, 197 .boot_params = MX3x_PHYS_OFFSET + 0x100,
198 .map_io = mx35_map_io, 198 .map_io = mx35_map_io,
diff --git a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
index da36da52969d..2442d5da883d 100644
--- a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
+++ b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
@@ -161,7 +161,7 @@ static struct sys_timer eukrea_cpuimx25_timer = {
161 .init = eukrea_cpuimx25_timer_init, 161 .init = eukrea_cpuimx25_timer_init,
162}; 162};
163 163
164MACHINE_START(EUKREA_CPUIMX25, "Eukrea CPUIMX25") 164MACHINE_START(EUKREA_CPUIMX25SD, "Eukrea CPUIMX25")
165 /* Maintainer: Eukrea Electromatique */ 165 /* Maintainer: Eukrea Electromatique */
166 .boot_params = MX25_PHYS_OFFSET + 0x100, 166 .boot_params = MX25_PHYS_OFFSET + 0x100,
167 .map_io = mx25_map_io, 167 .map_io = mx25_map_io,
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
index 2fbbdd5eac35..8cdc730dcb3a 100644
--- a/arch/arm/mach-integrator/integrator_ap.c
+++ b/arch/arm/mach-integrator/integrator_ap.c
@@ -32,6 +32,7 @@
32#include <linux/interrupt.h> 32#include <linux/interrupt.h>
33#include <linux/io.h> 33#include <linux/io.h>
34#include <linux/mtd/physmap.h> 34#include <linux/mtd/physmap.h>
35#include <video/vga.h>
35 36
36#include <mach/hardware.h> 37#include <mach/hardware.h>
37#include <mach/platform.h> 38#include <mach/platform.h>
@@ -154,6 +155,7 @@ static struct map_desc ap_io_desc[] __initdata = {
154static void __init ap_map_io(void) 155static void __init ap_map_io(void)
155{ 156{
156 iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc)); 157 iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc));
158 vga_base = PCI_MEMORY_VADDR;
157} 159}
158 160
159#define INTEGRATOR_SC_VALID_INT 0x003fffff 161#define INTEGRATOR_SC_VALID_INT 0x003fffff
@@ -337,15 +339,15 @@ static unsigned long timer_reload;
337static void integrator_clocksource_init(u32 khz) 339static void integrator_clocksource_init(u32 khz)
338{ 340{
339 void __iomem *base = (void __iomem *)TIMER2_VA_BASE; 341 void __iomem *base = (void __iomem *)TIMER2_VA_BASE;
340 u32 ctrl = TIMER_CTRL_ENABLE; 342 u32 ctrl = TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC;
341 343
342 if (khz >= 1500) { 344 if (khz >= 1500) {
343 khz /= 16; 345 khz /= 16;
344 ctrl = TIMER_CTRL_DIV16; 346 ctrl |= TIMER_CTRL_DIV16;
345 } 347 }
346 348
347 writel(ctrl, base + TIMER_CTRL);
348 writel(0xffff, base + TIMER_LOAD); 349 writel(0xffff, base + TIMER_LOAD);
350 writel(ctrl, base + TIMER_CTRL);
349 351
350 clocksource_mmio_init(base + TIMER_VALUE, "timer2", 352 clocksource_mmio_init(base + TIMER_VALUE, "timer2",
351 khz * 1000, 200, 16, clocksource_mmio_readl_down); 353 khz * 1000, 200, 16, clocksource_mmio_readl_down);
diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c
index dd56bfb351e3..11b86e5b71c2 100644
--- a/arch/arm/mach-integrator/pci_v3.c
+++ b/arch/arm/mach-integrator/pci_v3.c
@@ -27,7 +27,6 @@
27#include <linux/spinlock.h> 27#include <linux/spinlock.h>
28#include <linux/init.h> 28#include <linux/init.h>
29#include <linux/io.h> 29#include <linux/io.h>
30#include <video/vga.h>
31 30
32#include <mach/hardware.h> 31#include <mach/hardware.h>
33#include <mach/platform.h> 32#include <mach/platform.h>
@@ -505,7 +504,6 @@ void __init pci_v3_preinit(void)
505 504
506 pcibios_min_io = 0x6000; 505 pcibios_min_io = 0x6000;
507 pcibios_min_mem = 0x00100000; 506 pcibios_min_mem = 0x00100000;
508 vga_base = PCI_MEMORY_VADDR;
509 507
510 /* 508 /*
511 * Hook in our fault handler for PCI errors 509 * Hook in our fault handler for PCI errors
diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig
index b4e7c58bbb38..bda12e84429a 100644
--- a/arch/arm/mach-mx5/Kconfig
+++ b/arch/arm/mach-mx5/Kconfig
@@ -62,6 +62,15 @@ endif # ARCH_MX50_SUPPORTED
62if ARCH_MX51 62if ARCH_MX51
63comment "i.MX51 machines:" 63comment "i.MX51 machines:"
64 64
65config MACH_IMX51_DT
66 bool "Support i.MX51 platforms from device tree"
67 select SOC_IMX51
68 select USE_OF
69 select MACH_MX51_BABBAGE
70 help
71 Include support for Freescale i.MX51 based platforms
72 using the device tree for discovery
73
65config MACH_MX51_BABBAGE 74config MACH_MX51_BABBAGE
66 bool "Support MX51 BABBAGE platforms" 75 bool "Support MX51 BABBAGE platforms"
67 select SOC_IMX51 76 select SOC_IMX51
@@ -172,6 +181,18 @@ endif # ARCH_MX51
172if ARCH_MX53_SUPPORTED 181if ARCH_MX53_SUPPORTED
173comment "i.MX53 machines:" 182comment "i.MX53 machines:"
174 183
184config MACH_IMX53_DT
185 bool "Support i.MX53 platforms from device tree"
186 select SOC_IMX53
187 select USE_OF
188 select MACH_MX53_ARD
189 select MACH_MX53_EVK
190 select MACH_MX53_LOCO
191 select MACH_MX53_SMD
192 help
193 Include support for Freescale i.MX53 based platforms
194 using the device tree for discovery
195
175config MACH_MX53_EVK 196config MACH_MX53_EVK
176 bool "Support MX53 EVK platforms" 197 bool "Support MX53 EVK platforms"
177 select SOC_IMX53 198 select SOC_IMX53
diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile
index 383e7cd3fbcb..a3c75f368f4b 100644
--- a/arch/arm/mach-mx5/Makefile
+++ b/arch/arm/mach-mx5/Makefile
@@ -22,3 +22,6 @@ obj-$(CONFIG_MX51_EFIKA_COMMON) += mx51_efika.o
22obj-$(CONFIG_MACH_MX51_EFIKAMX) += board-mx51_efikamx.o 22obj-$(CONFIG_MACH_MX51_EFIKAMX) += board-mx51_efikamx.o
23obj-$(CONFIG_MACH_MX51_EFIKASB) += board-mx51_efikasb.o 23obj-$(CONFIG_MACH_MX51_EFIKASB) += board-mx51_efikasb.o
24obj-$(CONFIG_MACH_MX50_RDP) += board-mx50_rdp.o 24obj-$(CONFIG_MACH_MX50_RDP) += board-mx50_rdp.o
25
26obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o
27obj-$(CONFIG_MACH_IMX53_DT) += imx53-dt.o
diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c
index 11b0ff67f89d..5cc28e0ce3e5 100644
--- a/arch/arm/mach-mx5/board-mx51_babbage.c
+++ b/arch/arm/mach-mx5/board-mx51_babbage.c
@@ -351,6 +351,12 @@ static const struct esdhc_platform_data mx51_babbage_sd2_data __initconst = {
351 .wp_type = ESDHC_WP_GPIO, 351 .wp_type = ESDHC_WP_GPIO,
352}; 352};
353 353
354void __init imx51_babbage_common_init(void)
355{
356 mxc_iomux_v3_setup_multiple_pads(mx51babbage_pads,
357 ARRAY_SIZE(mx51babbage_pads));
358}
359
354/* 360/*
355 * Board specific initialization. 361 * Board specific initialization.
356 */ 362 */
@@ -365,8 +371,7 @@ static void __init mx51_babbage_init(void)
365#if defined(CONFIG_CPU_FREQ_IMX) 371#if defined(CONFIG_CPU_FREQ_IMX)
366 get_cpu_op = mx51_get_cpu_op; 372 get_cpu_op = mx51_get_cpu_op;
367#endif 373#endif
368 mxc_iomux_v3_setup_multiple_pads(mx51babbage_pads, 374 imx51_babbage_common_init();
369 ARRAY_SIZE(mx51babbage_pads));
370 375
371 imx51_add_imx_uart(0, &uart_pdata); 376 imx51_add_imx_uart(0, &uart_pdata);
372 imx51_add_imx_uart(1, NULL); 377 imx51_add_imx_uart(1, NULL);
diff --git a/arch/arm/mach-mx5/board-mx53_ard.c b/arch/arm/mach-mx5/board-mx53_ard.c
index 76a67c4a2a0b..9b4395d7a07c 100644
--- a/arch/arm/mach-mx5/board-mx53_ard.c
+++ b/arch/arm/mach-mx5/board-mx53_ard.c
@@ -171,9 +171,6 @@ static struct imxi2c_platform_data mx53_ard_i2c3_data = {
171 171
172static void __init mx53_ard_io_init(void) 172static void __init mx53_ard_io_init(void)
173{ 173{
174 mxc_iomux_v3_setup_multiple_pads(mx53_ard_pads,
175 ARRAY_SIZE(mx53_ard_pads));
176
177 gpio_request(ARD_ETHERNET_INT_B, "eth-int-b"); 174 gpio_request(ARD_ETHERNET_INT_B, "eth-int-b");
178 gpio_direction_input(ARD_ETHERNET_INT_B); 175 gpio_direction_input(ARD_ETHERNET_INT_B);
179 176
@@ -216,6 +213,13 @@ static int weim_cs_config(void)
216 return 0; 213 return 0;
217} 214}
218 215
216void __init imx53_ard_common_init(void)
217{
218 mxc_iomux_v3_setup_multiple_pads(mx53_ard_pads,
219 ARRAY_SIZE(mx53_ard_pads));
220 weim_cs_config();
221}
222
219static struct platform_device *devices[] __initdata = { 223static struct platform_device *devices[] __initdata = {
220 &ard_smsc_lan9220_device, 224 &ard_smsc_lan9220_device,
221}; 225};
@@ -225,8 +229,8 @@ static void __init mx53_ard_board_init(void)
225 imx53_soc_init(); 229 imx53_soc_init();
226 imx53_add_imx_uart(0, NULL); 230 imx53_add_imx_uart(0, NULL);
227 231
232 imx53_ard_common_init();
228 mx53_ard_io_init(); 233 mx53_ard_io_init();
229 weim_cs_config();
230 platform_add_devices(devices, ARRAY_SIZE(devices)); 234 platform_add_devices(devices, ARRAY_SIZE(devices));
231 235
232 imx53_add_sdhci_esdhc_imx(0, &mx53_ard_sd1_data); 236 imx53_add_sdhci_esdhc_imx(0, &mx53_ard_sd1_data);
diff --git a/arch/arm/mach-mx5/board-mx53_evk.c b/arch/arm/mach-mx5/board-mx53_evk.c
index 1b417b06b736..7663905d5c6d 100644
--- a/arch/arm/mach-mx5/board-mx53_evk.c
+++ b/arch/arm/mach-mx5/board-mx53_evk.c
@@ -131,12 +131,17 @@ static const struct spi_imx_master mx53_evk_spi_data __initconst = {
131 .num_chipselect = ARRAY_SIZE(mx53_evk_spi_cs), 131 .num_chipselect = ARRAY_SIZE(mx53_evk_spi_cs),
132}; 132};
133 133
134void __init imx53_evk_common_init(void)
135{
136 mxc_iomux_v3_setup_multiple_pads(mx53_evk_pads,
137 ARRAY_SIZE(mx53_evk_pads));
138}
139
134static void __init mx53_evk_board_init(void) 140static void __init mx53_evk_board_init(void)
135{ 141{
136 imx53_soc_init(); 142 imx53_soc_init();
143 imx53_evk_common_init();
137 144
138 mxc_iomux_v3_setup_multiple_pads(mx53_evk_pads,
139 ARRAY_SIZE(mx53_evk_pads));
140 mx53_evk_init_uart(); 145 mx53_evk_init_uart();
141 mx53_evk_fec_reset(); 146 mx53_evk_fec_reset();
142 imx53_add_fec(&mx53_evk_fec_pdata); 147 imx53_add_fec(&mx53_evk_fec_pdata);
diff --git a/arch/arm/mach-mx5/board-mx53_loco.c b/arch/arm/mach-mx5/board-mx53_loco.c
index 4e1d51d252dc..3922cd5ea854 100644
--- a/arch/arm/mach-mx5/board-mx53_loco.c
+++ b/arch/arm/mach-mx5/board-mx53_loco.c
@@ -257,12 +257,17 @@ static const struct gpio_led_platform_data mx53loco_leds_data __initconst = {
257 .num_leds = ARRAY_SIZE(mx53loco_leds), 257 .num_leds = ARRAY_SIZE(mx53loco_leds),
258}; 258};
259 259
260void __init imx53_qsb_common_init(void)
261{
262 mxc_iomux_v3_setup_multiple_pads(mx53_loco_pads,
263 ARRAY_SIZE(mx53_loco_pads));
264}
265
260static void __init mx53_loco_board_init(void) 266static void __init mx53_loco_board_init(void)
261{ 267{
262 imx53_soc_init(); 268 imx53_soc_init();
269 imx53_qsb_common_init();
263 270
264 mxc_iomux_v3_setup_multiple_pads(mx53_loco_pads,
265 ARRAY_SIZE(mx53_loco_pads));
266 imx53_add_imx_uart(0, NULL); 271 imx53_add_imx_uart(0, NULL);
267 mx53_loco_fec_reset(); 272 mx53_loco_fec_reset();
268 imx53_add_fec(&mx53_loco_fec_data); 273 imx53_add_fec(&mx53_loco_fec_data);
diff --git a/arch/arm/mach-mx5/board-mx53_smd.c b/arch/arm/mach-mx5/board-mx53_smd.c
index bc02894eafef..b10c89982fbc 100644
--- a/arch/arm/mach-mx5/board-mx53_smd.c
+++ b/arch/arm/mach-mx5/board-mx53_smd.c
@@ -111,12 +111,17 @@ static const struct imxi2c_platform_data mx53_smd_i2c_data __initconst = {
111 .bitrate = 100000, 111 .bitrate = 100000,
112}; 112};
113 113
114void __init imx53_smd_common_init(void)
115{
116 mxc_iomux_v3_setup_multiple_pads(mx53_smd_pads,
117 ARRAY_SIZE(mx53_smd_pads));
118}
119
114static void __init mx53_smd_board_init(void) 120static void __init mx53_smd_board_init(void)
115{ 121{
116 imx53_soc_init(); 122 imx53_soc_init();
123 imx53_smd_common_init();
117 124
118 mxc_iomux_v3_setup_multiple_pads(mx53_smd_pads,
119 ARRAY_SIZE(mx53_smd_pads));
120 mx53_smd_init_uart(); 125 mx53_smd_init_uart();
121 mx53_smd_fec_reset(); 126 mx53_smd_fec_reset();
122 imx53_add_fec(&mx53_smd_fec_data); 127 imx53_add_fec(&mx53_smd_fec_data);
diff --git a/arch/arm/mach-mx5/clock-mx51-mx53.c b/arch/arm/mach-mx5/clock-mx51-mx53.c
index f7bf996f463b..cc3547c88261 100644
--- a/arch/arm/mach-mx5/clock-mx51-mx53.c
+++ b/arch/arm/mach-mx5/clock-mx51-mx53.c
@@ -15,6 +15,7 @@
15#include <linux/clk.h> 15#include <linux/clk.h>
16#include <linux/io.h> 16#include <linux/io.h>
17#include <linux/clkdev.h> 17#include <linux/clkdev.h>
18#include <linux/of.h>
18 19
19#include <asm/div64.h> 20#include <asm/div64.h>
20 21
@@ -1609,3 +1610,41 @@ int __init mx53_clocks_init(unsigned long ckil, unsigned long osc,
1609 MX53_INT_GPT); 1610 MX53_INT_GPT);
1610 return 0; 1611 return 0;
1611} 1612}
1613
1614static void __init clk_get_freq_dt(unsigned long *ckil, unsigned long *osc,
1615 unsigned long *ckih1, unsigned long *ckih2)
1616{
1617 struct device_node *np;
1618
1619 /* retrieve the freqency of fixed clocks from device tree */
1620 for_each_compatible_node(np, NULL, "fixed-clock") {
1621 u32 rate;
1622 if (of_property_read_u32(np, "clock-frequency", &rate))
1623 continue;
1624
1625 if (of_device_is_compatible(np, "fsl,imx-ckil"))
1626 *ckil = rate;
1627 else if (of_device_is_compatible(np, "fsl,imx-osc"))
1628 *osc = rate;
1629 else if (of_device_is_compatible(np, "fsl,imx-ckih1"))
1630 *ckih1 = rate;
1631 else if (of_device_is_compatible(np, "fsl,imx-ckih2"))
1632 *ckih2 = rate;
1633 }
1634}
1635
1636int __init mx51_clocks_init_dt(void)
1637{
1638 unsigned long ckil, osc, ckih1, ckih2;
1639
1640 clk_get_freq_dt(&ckil, &osc, &ckih1, &ckih2);
1641 return mx51_clocks_init(ckil, osc, ckih1, ckih2);
1642}
1643
1644int __init mx53_clocks_init_dt(void)
1645{
1646 unsigned long ckil, osc, ckih1, ckih2;
1647
1648 clk_get_freq_dt(&ckil, &osc, &ckih1, &ckih2);
1649 return mx53_clocks_init(ckil, osc, ckih1, ckih2);
1650}
diff --git a/arch/arm/mach-mx5/imx51-dt.c b/arch/arm/mach-mx5/imx51-dt.c
new file mode 100644
index 000000000000..ccc61585659b
--- /dev/null
+++ b/arch/arm/mach-mx5/imx51-dt.c
@@ -0,0 +1,116 @@
1/*
2 * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13#include <linux/irq.h>
14#include <linux/irqdomain.h>
15#include <linux/of_irq.h>
16#include <linux/of_platform.h>
17#include <asm/mach/arch.h>
18#include <asm/mach/time.h>
19#include <mach/common.h>
20#include <mach/mx51.h>
21
22/*
23 * Lookup table for attaching a specific name and platform_data pointer to
24 * devices as they get created by of_platform_populate(). Ideally this table
25 * would not exist, but the current clock implementation depends on some devices
26 * having a specific name.
27 */
28static const struct of_dev_auxdata imx51_auxdata_lookup[] __initconst = {
29 OF_DEV_AUXDATA("fsl,imx51-uart", MX51_UART1_BASE_ADDR, "imx21-uart.0", NULL),
30 OF_DEV_AUXDATA("fsl,imx51-uart", MX51_UART2_BASE_ADDR, "imx21-uart.1", NULL),
31 OF_DEV_AUXDATA("fsl,imx51-uart", MX51_UART3_BASE_ADDR, "imx21-uart.2", NULL),
32 OF_DEV_AUXDATA("fsl,imx51-fec", MX51_FEC_BASE_ADDR, "imx27-fec.0", NULL),
33 OF_DEV_AUXDATA("fsl,imx51-esdhc", MX51_ESDHC1_BASE_ADDR, "sdhci-esdhc-imx51.0", NULL),
34 OF_DEV_AUXDATA("fsl,imx51-esdhc", MX51_ESDHC2_BASE_ADDR, "sdhci-esdhc-imx51.1", NULL),
35 OF_DEV_AUXDATA("fsl,imx51-esdhc", MX51_ESDHC3_BASE_ADDR, "sdhci-esdhc-imx51.2", NULL),
36 OF_DEV_AUXDATA("fsl,imx51-esdhc", MX51_ESDHC4_BASE_ADDR, "sdhci-esdhc-imx51.3", NULL),
37 OF_DEV_AUXDATA("fsl,imx51-ecspi", MX51_ECSPI1_BASE_ADDR, "imx51-ecspi.0", NULL),
38 OF_DEV_AUXDATA("fsl,imx51-ecspi", MX51_ECSPI2_BASE_ADDR, "imx51-ecspi.1", NULL),
39 OF_DEV_AUXDATA("fsl,imx51-cspi", MX51_CSPI_BASE_ADDR, "imx35-cspi.0", NULL),
40 OF_DEV_AUXDATA("fsl,imx51-i2c", MX51_I2C1_BASE_ADDR, "imx-i2c.0", NULL),
41 OF_DEV_AUXDATA("fsl,imx51-i2c", MX51_I2C2_BASE_ADDR, "imx-i2c.1", NULL),
42 OF_DEV_AUXDATA("fsl,imx51-sdma", MX51_SDMA_BASE_ADDR, "imx35-sdma", NULL),
43 OF_DEV_AUXDATA("fsl,imx51-wdt", MX51_WDOG1_BASE_ADDR, "imx2-wdt.0", NULL),
44 { /* sentinel */ }
45};
46
47static void __init imx51_tzic_add_irq_domain(struct device_node *np,
48 struct device_node *interrupt_parent)
49{
50 irq_domain_add_simple(np, 0);
51}
52
53static void __init imx51_gpio_add_irq_domain(struct device_node *np,
54 struct device_node *interrupt_parent)
55{
56 static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS -
57 32 * 4; /* imx51 gets 4 gpio ports */
58
59 irq_domain_add_simple(np, gpio_irq_base);
60 gpio_irq_base += 32;
61}
62
63static const struct of_device_id imx51_irq_match[] __initconst = {
64 { .compatible = "fsl,imx51-tzic", .data = imx51_tzic_add_irq_domain, },
65 { .compatible = "fsl,imx51-gpio", .data = imx51_gpio_add_irq_domain, },
66 { /* sentinel */ }
67};
68
69static const struct of_device_id imx51_iomuxc_of_match[] __initconst = {
70 { .compatible = "fsl,imx51-iomuxc-babbage", .data = imx51_babbage_common_init, },
71 { /* sentinel */ }
72};
73
74static void __init imx51_dt_init(void)
75{
76 struct device_node *node;
77 const struct of_device_id *of_id;
78 void (*func)(void);
79
80 of_irq_init(imx51_irq_match);
81
82 node = of_find_matching_node(NULL, imx51_iomuxc_of_match);
83 if (node) {
84 of_id = of_match_node(imx51_iomuxc_of_match, node);
85 func = of_id->data;
86 func();
87 of_node_put(node);
88 }
89
90 of_platform_populate(NULL, of_default_bus_match_table,
91 imx51_auxdata_lookup, NULL);
92}
93
94static void __init imx51_timer_init(void)
95{
96 mx51_clocks_init_dt();
97}
98
99static struct sys_timer imx51_timer = {
100 .init = imx51_timer_init,
101};
102
103static const char *imx51_dt_board_compat[] __initdata = {
104 "fsl,imx51-babbage",
105 NULL
106};
107
108DT_MACHINE_START(IMX51_DT, "Freescale i.MX51 (Device Tree Support)")
109 .map_io = mx51_map_io,
110 .init_early = imx51_init_early,
111 .init_irq = mx51_init_irq,
112 .handle_irq = imx51_handle_irq,
113 .timer = &imx51_timer,
114 .init_machine = imx51_dt_init,
115 .dt_compat = imx51_dt_board_compat,
116MACHINE_END
diff --git a/arch/arm/mach-mx5/imx53-dt.c b/arch/arm/mach-mx5/imx53-dt.c
new file mode 100644
index 000000000000..ccaa0b81b768
--- /dev/null
+++ b/arch/arm/mach-mx5/imx53-dt.c
@@ -0,0 +1,126 @@
1/*
2 * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13#include <linux/io.h>
14#include <linux/irq.h>
15#include <linux/irqdomain.h>
16#include <linux/of_irq.h>
17#include <linux/of_platform.h>
18#include <asm/mach/arch.h>
19#include <asm/mach/time.h>
20#include <mach/common.h>
21#include <mach/mx53.h>
22
23/*
24 * Lookup table for attaching a specific name and platform_data pointer to
25 * devices as they get created by of_platform_populate(). Ideally this table
26 * would not exist, but the current clock implementation depends on some devices
27 * having a specific name.
28 */
29static const struct of_dev_auxdata imx53_auxdata_lookup[] __initconst = {
30 OF_DEV_AUXDATA("fsl,imx53-uart", MX53_UART1_BASE_ADDR, "imx21-uart.0", NULL),
31 OF_DEV_AUXDATA("fsl,imx53-uart", MX53_UART2_BASE_ADDR, "imx21-uart.1", NULL),
32 OF_DEV_AUXDATA("fsl,imx53-uart", MX53_UART3_BASE_ADDR, "imx21-uart.2", NULL),
33 OF_DEV_AUXDATA("fsl,imx53-uart", MX53_UART4_BASE_ADDR, "imx21-uart.3", NULL),
34 OF_DEV_AUXDATA("fsl,imx53-uart", MX53_UART5_BASE_ADDR, "imx21-uart.4", NULL),
35 OF_DEV_AUXDATA("fsl,imx53-fec", MX53_FEC_BASE_ADDR, "imx25-fec.0", NULL),
36 OF_DEV_AUXDATA("fsl,imx53-esdhc", MX53_ESDHC1_BASE_ADDR, "sdhci-esdhc-imx53.0", NULL),
37 OF_DEV_AUXDATA("fsl,imx53-esdhc", MX53_ESDHC2_BASE_ADDR, "sdhci-esdhc-imx53.1", NULL),
38 OF_DEV_AUXDATA("fsl,imx53-esdhc", MX53_ESDHC3_BASE_ADDR, "sdhci-esdhc-imx53.2", NULL),
39 OF_DEV_AUXDATA("fsl,imx53-esdhc", MX53_ESDHC4_BASE_ADDR, "sdhci-esdhc-imx53.3", NULL),
40 OF_DEV_AUXDATA("fsl,imx53-ecspi", MX53_ECSPI1_BASE_ADDR, "imx51-ecspi.0", NULL),
41 OF_DEV_AUXDATA("fsl,imx53-ecspi", MX53_ECSPI2_BASE_ADDR, "imx51-ecspi.1", NULL),
42 OF_DEV_AUXDATA("fsl,imx53-cspi", MX53_CSPI_BASE_ADDR, "imx35-cspi.0", NULL),
43 OF_DEV_AUXDATA("fsl,imx53-i2c", MX53_I2C1_BASE_ADDR, "imx-i2c.0", NULL),
44 OF_DEV_AUXDATA("fsl,imx53-i2c", MX53_I2C2_BASE_ADDR, "imx-i2c.1", NULL),
45 OF_DEV_AUXDATA("fsl,imx53-i2c", MX53_I2C3_BASE_ADDR, "imx-i2c.2", NULL),
46 OF_DEV_AUXDATA("fsl,imx53-sdma", MX53_SDMA_BASE_ADDR, "imx35-sdma", NULL),
47 OF_DEV_AUXDATA("fsl,imx53-wdt", MX53_WDOG1_BASE_ADDR, "imx2-wdt.0", NULL),
48 { /* sentinel */ }
49};
50
51static void __init imx53_tzic_add_irq_domain(struct device_node *np,
52 struct device_node *interrupt_parent)
53{
54 irq_domain_add_simple(np, 0);
55}
56
57static void __init imx53_gpio_add_irq_domain(struct device_node *np,
58 struct device_node *interrupt_parent)
59{
60 static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS -
61 32 * 7; /* imx53 gets 7 gpio ports */
62
63 irq_domain_add_simple(np, gpio_irq_base);
64 gpio_irq_base += 32;
65}
66
67static const struct of_device_id imx53_irq_match[] __initconst = {
68 { .compatible = "fsl,imx53-tzic", .data = imx53_tzic_add_irq_domain, },
69 { .compatible = "fsl,imx53-gpio", .data = imx53_gpio_add_irq_domain, },
70 { /* sentinel */ }
71};
72
73static const struct of_device_id imx53_iomuxc_of_match[] __initconst = {
74 { .compatible = "fsl,imx53-iomuxc-ard", .data = imx53_ard_common_init, },
75 { .compatible = "fsl,imx53-iomuxc-evk", .data = imx53_evk_common_init, },
76 { .compatible = "fsl,imx53-iomuxc-qsb", .data = imx53_qsb_common_init, },
77 { .compatible = "fsl,imx53-iomuxc-smd", .data = imx53_smd_common_init, },
78 { /* sentinel */ }
79};
80
81static void __init imx53_dt_init(void)
82{
83 struct device_node *node;
84 const struct of_device_id *of_id;
85 void (*func)(void);
86
87 of_irq_init(imx53_irq_match);
88
89 node = of_find_matching_node(NULL, imx53_iomuxc_of_match);
90 if (node) {
91 of_id = of_match_node(imx53_iomuxc_of_match, node);
92 func = of_id->data;
93 func();
94 of_node_put(node);
95 }
96
97 of_platform_populate(NULL, of_default_bus_match_table,
98 imx53_auxdata_lookup, NULL);
99}
100
101static void __init imx53_timer_init(void)
102{
103 mx53_clocks_init_dt();
104}
105
106static struct sys_timer imx53_timer = {
107 .init = imx53_timer_init,
108};
109
110static const char *imx53_dt_board_compat[] __initdata = {
111 "fsl,imx53-ard",
112 "fsl,imx53-evk",
113 "fsl,imx53-qsb",
114 "fsl,imx53-smd",
115 NULL
116};
117
118DT_MACHINE_START(IMX53_DT, "Freescale i.MX53 (Device Tree Support)")
119 .map_io = mx53_map_io,
120 .init_early = imx53_init_early,
121 .init_irq = mx53_init_irq,
122 .handle_irq = imx53_handle_irq,
123 .timer = &imx53_timer,
124 .init_machine = imx53_dt_init,
125 .dt_compat = imx53_dt_board_compat,
126MACHINE_END
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index 2028464cf5b9..f79b7d2a8ed4 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -193,7 +193,8 @@ static int __init omap2430_i2c_init(void)
193{ 193{
194 omap_register_i2c_bus(1, 100, sdp2430_i2c1_boardinfo, 194 omap_register_i2c_bus(1, 100, sdp2430_i2c1_boardinfo,
195 ARRAY_SIZE(sdp2430_i2c1_boardinfo)); 195 ARRAY_SIZE(sdp2430_i2c1_boardinfo));
196 omap2_pmic_init("twl4030", &sdp2430_twldata); 196 omap_pmic_init(2, 100, "twl4030", INT_24XX_SYS_NIRQ,
197 &sdp2430_twldata);
197 return 0; 198 return 0;
198} 199}
199 200
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index ffd55b1c4396..b9b844683147 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -3078,6 +3078,7 @@ static struct clk gpt12_fck = {
3078 .name = "gpt12_fck", 3078 .name = "gpt12_fck",
3079 .ops = &clkops_null, 3079 .ops = &clkops_null,
3080 .parent = &secure_32k_fck, 3080 .parent = &secure_32k_fck,
3081 .clkdm_name = "wkup_clkdm",
3081 .recalc = &followparent_recalc, 3082 .recalc = &followparent_recalc,
3082}; 3083};
3083 3084
@@ -3085,6 +3086,7 @@ static struct clk wdt1_fck = {
3085 .name = "wdt1_fck", 3086 .name = "wdt1_fck",
3086 .ops = &clkops_null, 3087 .ops = &clkops_null,
3087 .parent = &secure_32k_fck, 3088 .parent = &secure_32k_fck,
3089 .clkdm_name = "wkup_clkdm",
3088 .recalc = &followparent_recalc, 3090 .recalc = &followparent_recalc,
3089}; 3091};
3090 3092
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index 2af0e3f00ce1..c0b6fbda3408 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -3376,10 +3376,18 @@ int __init omap4xxx_clk_init(void)
3376 } else if (cpu_is_omap446x()) { 3376 } else if (cpu_is_omap446x()) {
3377 cpu_mask = RATE_IN_4460; 3377 cpu_mask = RATE_IN_4460;
3378 cpu_clkflg = CK_446X; 3378 cpu_clkflg = CK_446X;
3379 } else {
3380 return 0;
3379 } 3381 }
3380 3382
3381 clk_init(&omap2_clk_functions); 3383 clk_init(&omap2_clk_functions);
3382 omap2_clk_disable_clkdm_control(); 3384
3385 /*
3386 * Must stay commented until all OMAP SoC drivers are
3387 * converted to runtime PM, or drivers may start crashing
3388 *
3389 * omap2_clk_disable_clkdm_control();
3390 */
3383 3391
3384 for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks); 3392 for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks);
3385 c++) 3393 c++)
diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
index ab7db083f97f..8f0890685d7b 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -747,6 +747,7 @@ int clkdm_wakeup(struct clockdomain *clkdm)
747 spin_lock_irqsave(&clkdm->lock, flags); 747 spin_lock_irqsave(&clkdm->lock, flags);
748 clkdm->_flags &= ~_CLKDM_FLAG_HWSUP_ENABLED; 748 clkdm->_flags &= ~_CLKDM_FLAG_HWSUP_ENABLED;
749 ret = arch_clkdm->clkdm_wakeup(clkdm); 749 ret = arch_clkdm->clkdm_wakeup(clkdm);
750 ret |= pwrdm_state_switch(clkdm->pwrdm.ptr);
750 spin_unlock_irqrestore(&clkdm->lock, flags); 751 spin_unlock_irqrestore(&clkdm->lock, flags);
751 return ret; 752 return ret;
752} 753}
@@ -818,6 +819,7 @@ void clkdm_deny_idle(struct clockdomain *clkdm)
818 spin_lock_irqsave(&clkdm->lock, flags); 819 spin_lock_irqsave(&clkdm->lock, flags);
819 clkdm->_flags &= ~_CLKDM_FLAG_HWSUP_ENABLED; 820 clkdm->_flags &= ~_CLKDM_FLAG_HWSUP_ENABLED;
820 arch_clkdm->clkdm_deny_idle(clkdm); 821 arch_clkdm->clkdm_deny_idle(clkdm);
822 pwrdm_state_switch(clkdm->pwrdm.ptr);
821 spin_unlock_irqrestore(&clkdm->lock, flags); 823 spin_unlock_irqrestore(&clkdm->lock, flags);
822} 824}
823 825
diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
index a9b45c76e1d3..097a42d81e59 100644
--- a/arch/arm/mach-omap2/hsmmc.c
+++ b/arch/arm/mach-omap2/hsmmc.c
@@ -137,8 +137,7 @@ static void omap4_hsmmc1_before_set_reg(struct device *dev, int slot,
137 */ 137 */
138 reg = omap4_ctrl_pad_readl(control_pbias_offset); 138 reg = omap4_ctrl_pad_readl(control_pbias_offset);
139 reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK | 139 reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
140 OMAP4_MMC1_PWRDNZ_MASK | 140 OMAP4_MMC1_PWRDNZ_MASK);
141 OMAP4_USBC1_ICUSB_PWRDNZ_MASK);
142 omap4_ctrl_pad_writel(reg, control_pbias_offset); 141 omap4_ctrl_pad_writel(reg, control_pbias_offset);
143} 142}
144 143
@@ -156,8 +155,7 @@ static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot,
156 else 155 else
157 reg |= OMAP4_MMC1_PBIASLITE_VMODE_MASK; 156 reg |= OMAP4_MMC1_PBIASLITE_VMODE_MASK;
158 reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK | 157 reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
159 OMAP4_MMC1_PWRDNZ_MASK | 158 OMAP4_MMC1_PWRDNZ_MASK);
160 OMAP4_USBC1_ICUSB_PWRDNZ_MASK);
161 omap4_ctrl_pad_writel(reg, control_pbias_offset); 159 omap4_ctrl_pad_writel(reg, control_pbias_offset);
162 160
163 timeout = jiffies + msecs_to_jiffies(5); 161 timeout = jiffies + msecs_to_jiffies(5);
@@ -171,16 +169,14 @@ static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot,
171 if (reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK) { 169 if (reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK) {
172 pr_err("Pbias Voltage is not same as LDO\n"); 170 pr_err("Pbias Voltage is not same as LDO\n");
173 /* Caution : On VMODE_ERROR Power Down MMC IO */ 171 /* Caution : On VMODE_ERROR Power Down MMC IO */
174 reg &= ~(OMAP4_MMC1_PWRDNZ_MASK | 172 reg &= ~(OMAP4_MMC1_PWRDNZ_MASK);
175 OMAP4_USBC1_ICUSB_PWRDNZ_MASK);
176 omap4_ctrl_pad_writel(reg, control_pbias_offset); 173 omap4_ctrl_pad_writel(reg, control_pbias_offset);
177 } 174 }
178 } else { 175 } else {
179 reg = omap4_ctrl_pad_readl(control_pbias_offset); 176 reg = omap4_ctrl_pad_readl(control_pbias_offset);
180 reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK | 177 reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
181 OMAP4_MMC1_PWRDNZ_MASK | 178 OMAP4_MMC1_PWRDNZ_MASK |
182 OMAP4_MMC1_PBIASLITE_VMODE_MASK | 179 OMAP4_MMC1_PBIASLITE_VMODE_MASK);
183 OMAP4_USBC1_ICUSB_PWRDNZ_MASK);
184 omap4_ctrl_pad_writel(reg, control_pbias_offset); 180 omap4_ctrl_pad_writel(reg, control_pbias_offset);
185 } 181 }
186} 182}
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index 16743c7d6e8e..408193d8e044 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -192,6 +192,7 @@ static struct omap_hwmod_addr_space omap2430_usbhsotg_addrs[] = {
192 .pa_end = OMAP243X_HS_BASE + SZ_4K - 1, 192 .pa_end = OMAP243X_HS_BASE + SZ_4K - 1,
193 .flags = ADDR_TYPE_RT 193 .flags = ADDR_TYPE_RT
194 }, 194 },
195 { }
195}; 196};
196 197
197/* l4_core ->usbhsotg interface */ 198/* l4_core ->usbhsotg interface */
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 3feb35911a32..472bf22d5e84 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -130,7 +130,6 @@ int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
130 } else { 130 } else {
131 hwsup = clkdm_in_hwsup(pwrdm->pwrdm_clkdms[0]); 131 hwsup = clkdm_in_hwsup(pwrdm->pwrdm_clkdms[0]);
132 clkdm_wakeup(pwrdm->pwrdm_clkdms[0]); 132 clkdm_wakeup(pwrdm->pwrdm_clkdms[0]);
133 pwrdm_wait_transition(pwrdm);
134 sleep_switch = FORCEWAKEUP_SWITCH; 133 sleep_switch = FORCEWAKEUP_SWITCH;
135 } 134 }
136 } 135 }
@@ -156,7 +155,6 @@ int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
156 return ret; 155 return ret;
157 } 156 }
158 157
159 pwrdm_wait_transition(pwrdm);
160 pwrdm_state_switch(pwrdm); 158 pwrdm_state_switch(pwrdm);
161err: 159err:
162 return ret; 160 return ret;
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index 9af08473bf10..ef71fdd40fc4 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -195,28 +195,35 @@ static int _pwrdm_post_transition_cb(struct powerdomain *pwrdm, void *unused)
195 195
196/** 196/**
197 * pwrdm_init - set up the powerdomain layer 197 * pwrdm_init - set up the powerdomain layer
198 * @pwrdm_list: array of struct powerdomain pointers to register 198 * @pwrdms: array of struct powerdomain pointers to register
199 * @custom_funcs: func pointers for arch specific implementations 199 * @custom_funcs: func pointers for arch specific implementations
200 * 200 *
201 * Loop through the array of powerdomains @pwrdm_list, registering all 201 * Loop through the array of powerdomains @pwrdms, registering all
202 * that are available on the current CPU. If pwrdm_list is supplied 202 * that are available on the current CPU. Also, program all
203 * and not null, all of the referenced powerdomains will be 203 * powerdomain target state as ON; this is to prevent domains from
204 * registered. No return value. XXX pwrdm_list is not really a 204 * hitting low power states (if bootloader has target states set to
205 * "list"; it is an array. Rename appropriately. 205 * something other than ON) and potentially even losing context while
206 * PM is not fully initialized. The PM late init code can then program
207 * the desired target state for all the power domains. No return
208 * value.
206 */ 209 */
207void pwrdm_init(struct powerdomain **pwrdm_list, struct pwrdm_ops *custom_funcs) 210void pwrdm_init(struct powerdomain **pwrdms, struct pwrdm_ops *custom_funcs)
208{ 211{
209 struct powerdomain **p = NULL; 212 struct powerdomain **p = NULL;
213 struct powerdomain *temp_p;
210 214
211 if (!custom_funcs) 215 if (!custom_funcs)
212 WARN(1, "powerdomain: No custom pwrdm functions registered\n"); 216 WARN(1, "powerdomain: No custom pwrdm functions registered\n");
213 else 217 else
214 arch_pwrdm = custom_funcs; 218 arch_pwrdm = custom_funcs;
215 219
216 if (pwrdm_list) { 220 if (pwrdms) {
217 for (p = pwrdm_list; *p; p++) 221 for (p = pwrdms; *p; p++)
218 _pwrdm_register(*p); 222 _pwrdm_register(*p);
219 } 223 }
224
225 list_for_each_entry(temp_p, &pwrdm_list, node)
226 pwrdm_set_next_pwrst(temp_p, PWRDM_POWER_ON);
220} 227}
221 228
222/** 229/**
diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c
index a65145b02a55..19e4dac62a8c 100644
--- a/arch/arm/mach-omap2/usb-musb.c
+++ b/arch/arm/mach-omap2/usb-musb.c
@@ -137,9 +137,6 @@ void __init usb_musb_init(struct omap_musb_board_data *musb_board_data)
137 musb_plat.mode = board_data->mode; 137 musb_plat.mode = board_data->mode;
138 musb_plat.extvbus = board_data->extvbus; 138 musb_plat.extvbus = board_data->extvbus;
139 139
140 if (cpu_is_omap44xx())
141 omap4430_phy_init(dev);
142
143 if (cpu_is_omap3517() || cpu_is_omap3505()) { 140 if (cpu_is_omap3517() || cpu_is_omap3505()) {
144 oh_name = "am35x_otg_hs"; 141 oh_name = "am35x_otg_hs";
145 name = "musb-am35x"; 142 name = "musb-am35x";
diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c
index a6eddae82a0b..c105556a0ee1 100644
--- a/arch/arm/mach-orion5x/dns323-setup.c
+++ b/arch/arm/mach-orion5x/dns323-setup.c
@@ -77,7 +77,7 @@ static int __init dns323_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
77 /* 77 /*
78 * Check for devices with hard-wired IRQs. 78 * Check for devices with hard-wired IRQs.
79 */ 79 */
80 irq = orion5x_pci_map_irq(const dev, slot, pin); 80 irq = orion5x_pci_map_irq(dev, slot, pin);
81 if (irq != -1) 81 if (irq != -1)
82 return irq; 82 return irq;
83 83
diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c
index 28b8760ab9fa..bc4a920e26ee 100644
--- a/arch/arm/mach-orion5x/pci.c
+++ b/arch/arm/mach-orion5x/pci.c
@@ -14,6 +14,7 @@
14#include <linux/pci.h> 14#include <linux/pci.h>
15#include <linux/slab.h> 15#include <linux/slab.h>
16#include <linux/mbus.h> 16#include <linux/mbus.h>
17#include <video/vga.h>
17#include <asm/irq.h> 18#include <asm/irq.h>
18#include <asm/mach/pci.h> 19#include <asm/mach/pci.h>
19#include <plat/pcie.h> 20#include <plat/pcie.h>
diff --git a/arch/arm/mach-prima2/clock.c b/arch/arm/mach-prima2/clock.c
index f9a2aaf63f71..615a4e75ceab 100644
--- a/arch/arm/mach-prima2/clock.c
+++ b/arch/arm/mach-prima2/clock.c
@@ -481,6 +481,7 @@ static void __init sirfsoc_clk_init(void)
481 481
482static struct of_device_id clkc_ids[] = { 482static struct of_device_id clkc_ids[] = {
483 { .compatible = "sirf,prima2-clkc" }, 483 { .compatible = "sirf,prima2-clkc" },
484 {},
484}; 485};
485 486
486void __init sirfsoc_of_clk_init(void) 487void __init sirfsoc_of_clk_init(void)
diff --git a/arch/arm/mach-prima2/irq.c b/arch/arm/mach-prima2/irq.c
index c3404cbb6ff7..7af254d046ba 100644
--- a/arch/arm/mach-prima2/irq.c
+++ b/arch/arm/mach-prima2/irq.c
@@ -51,6 +51,7 @@ static __init void sirfsoc_irq_init(void)
51 51
52static struct of_device_id intc_ids[] = { 52static struct of_device_id intc_ids[] = {
53 { .compatible = "sirf,prima2-intc" }, 53 { .compatible = "sirf,prima2-intc" },
54 {},
54}; 55};
55 56
56void __init sirfsoc_of_irq_init(void) 57void __init sirfsoc_of_irq_init(void)
diff --git a/arch/arm/mach-prima2/rstc.c b/arch/arm/mach-prima2/rstc.c
index d074786e83d4..492cfa8d2610 100644
--- a/arch/arm/mach-prima2/rstc.c
+++ b/arch/arm/mach-prima2/rstc.c
@@ -19,6 +19,7 @@ static DEFINE_MUTEX(rstc_lock);
19 19
20static struct of_device_id rstc_ids[] = { 20static struct of_device_id rstc_ids[] = {
21 { .compatible = "sirf,prima2-rstc" }, 21 { .compatible = "sirf,prima2-rstc" },
22 {},
22}; 23};
23 24
24static int __init sirfsoc_of_rstc_init(void) 25static int __init sirfsoc_of_rstc_init(void)
diff --git a/arch/arm/mach-prima2/timer.c b/arch/arm/mach-prima2/timer.c
index 44027f34a88a..ed7ec48d11da 100644
--- a/arch/arm/mach-prima2/timer.c
+++ b/arch/arm/mach-prima2/timer.c
@@ -190,6 +190,7 @@ static void __init sirfsoc_timer_init(void)
190 190
191static struct of_device_id timer_ids[] = { 191static struct of_device_id timer_ids[] = {
192 { .compatible = "sirf,prima2-tick" }, 192 { .compatible = "sirf,prima2-tick" },
193 {},
193}; 194};
194 195
195static void __init sirfsoc_of_timer_map(void) 196static void __init sirfsoc_of_timer_map(void)
diff --git a/arch/arm/mach-realview/include/mach/system.h b/arch/arm/mach-realview/include/mach/system.h
index a30f2e3ec178..6657ff231161 100644
--- a/arch/arm/mach-realview/include/mach/system.h
+++ b/arch/arm/mach-realview/include/mach/system.h
@@ -44,6 +44,7 @@ static inline void arch_reset(char mode, const char *cmd)
44 */ 44 */
45 if (realview_reset) 45 if (realview_reset)
46 realview_reset(mode); 46 realview_reset(mode);
47 dsb();
47} 48}
48 49
49#endif 50#endif
diff --git a/arch/arm/mach-s3c2410/s3c2410.c b/arch/arm/mach-s3c2410/s3c2410.c
index f1d3bd8f6f17..343a540d86a9 100644
--- a/arch/arm/mach-s3c2410/s3c2410.c
+++ b/arch/arm/mach-s3c2410/s3c2410.c
@@ -170,7 +170,9 @@ int __init s3c2410_init(void)
170{ 170{
171 printk("S3C2410: Initialising architecture\n"); 171 printk("S3C2410: Initialising architecture\n");
172 172
173#ifdef CONFIG_PM
173 register_syscore_ops(&s3c2410_pm_syscore_ops); 174 register_syscore_ops(&s3c2410_pm_syscore_ops);
175#endif
174 register_syscore_ops(&s3c24xx_irq_syscore_ops); 176 register_syscore_ops(&s3c24xx_irq_syscore_ops);
175 177
176 return sysdev_register(&s3c2410_sysdev); 178 return sysdev_register(&s3c2410_sysdev);
diff --git a/arch/arm/mach-s3c2412/s3c2412.c b/arch/arm/mach-s3c2412/s3c2412.c
index ef0958d3e5c6..57a1e01e4e50 100644
--- a/arch/arm/mach-s3c2412/s3c2412.c
+++ b/arch/arm/mach-s3c2412/s3c2412.c
@@ -245,7 +245,9 @@ int __init s3c2412_init(void)
245{ 245{
246 printk("S3C2412: Initialising architecture\n"); 246 printk("S3C2412: Initialising architecture\n");
247 247
248#ifdef CONFIG_PM
248 register_syscore_ops(&s3c2412_pm_syscore_ops); 249 register_syscore_ops(&s3c2412_pm_syscore_ops);
250#endif
249 register_syscore_ops(&s3c24xx_irq_syscore_ops); 251 register_syscore_ops(&s3c24xx_irq_syscore_ops);
250 252
251 return sysdev_register(&s3c2412_sysdev); 253 return sysdev_register(&s3c2412_sysdev);
diff --git a/arch/arm/mach-s3c2416/s3c2416.c b/arch/arm/mach-s3c2416/s3c2416.c
index 494ce913dc95..20b3fdfb3051 100644
--- a/arch/arm/mach-s3c2416/s3c2416.c
+++ b/arch/arm/mach-s3c2416/s3c2416.c
@@ -97,7 +97,9 @@ int __init s3c2416_init(void)
97 97
98 s3c_fb_setname("s3c2443-fb"); 98 s3c_fb_setname("s3c2443-fb");
99 99
100#ifdef CONFIG_PM
100 register_syscore_ops(&s3c2416_pm_syscore_ops); 101 register_syscore_ops(&s3c2416_pm_syscore_ops);
102#endif
101 register_syscore_ops(&s3c24xx_irq_syscore_ops); 103 register_syscore_ops(&s3c24xx_irq_syscore_ops);
102 104
103 return sysdev_register(&s3c2416_sysdev); 105 return sysdev_register(&s3c2416_sysdev);
diff --git a/arch/arm/mach-s3c2440/s3c2440.c b/arch/arm/mach-s3c2440/s3c2440.c
index ce99ff72838d..2270d3360216 100644
--- a/arch/arm/mach-s3c2440/s3c2440.c
+++ b/arch/arm/mach-s3c2440/s3c2440.c
@@ -55,7 +55,9 @@ int __init s3c2440_init(void)
55 55
56 /* register suspend/resume handlers */ 56 /* register suspend/resume handlers */
57 57
58#ifdef CONFIG_PM
58 register_syscore_ops(&s3c2410_pm_syscore_ops); 59 register_syscore_ops(&s3c2410_pm_syscore_ops);
60#endif
59 register_syscore_ops(&s3c244x_pm_syscore_ops); 61 register_syscore_ops(&s3c244x_pm_syscore_ops);
60 register_syscore_ops(&s3c24xx_irq_syscore_ops); 62 register_syscore_ops(&s3c24xx_irq_syscore_ops);
61 63
diff --git a/arch/arm/mach-s3c2440/s3c2442.c b/arch/arm/mach-s3c2440/s3c2442.c
index 9ad99f8016a1..6f2b65e6e068 100644
--- a/arch/arm/mach-s3c2440/s3c2442.c
+++ b/arch/arm/mach-s3c2440/s3c2442.c
@@ -169,7 +169,9 @@ int __init s3c2442_init(void)
169{ 169{
170 printk("S3C2442: Initialising architecture\n"); 170 printk("S3C2442: Initialising architecture\n");
171 171
172#ifdef CONFIG_PM
172 register_syscore_ops(&s3c2410_pm_syscore_ops); 173 register_syscore_ops(&s3c2410_pm_syscore_ops);
174#endif
173 register_syscore_ops(&s3c244x_pm_syscore_ops); 175 register_syscore_ops(&s3c244x_pm_syscore_ops);
174 register_syscore_ops(&s3c24xx_irq_syscore_ops); 176 register_syscore_ops(&s3c24xx_irq_syscore_ops);
175 177
diff --git a/arch/arm/mach-s3c2443/clock.c b/arch/arm/mach-s3c2443/clock.c
index a1a7176675b9..38058af48972 100644
--- a/arch/arm/mach-s3c2443/clock.c
+++ b/arch/arm/mach-s3c2443/clock.c
@@ -128,7 +128,7 @@ static int s3c2443_armclk_setrate(struct clk *clk, unsigned long rate)
128 unsigned long clkcon0; 128 unsigned long clkcon0;
129 129
130 clkcon0 = __raw_readl(S3C2443_CLKDIV0); 130 clkcon0 = __raw_readl(S3C2443_CLKDIV0);
131 clkcon0 &= S3C2443_CLKDIV0_ARMDIV_MASK; 131 clkcon0 &= ~S3C2443_CLKDIV0_ARMDIV_MASK;
132 clkcon0 |= val << S3C2443_CLKDIV0_ARMDIV_SHIFT; 132 clkcon0 |= val << S3C2443_CLKDIV0_ARMDIV_SHIFT;
133 __raw_writel(clkcon0, S3C2443_CLKDIV0); 133 __raw_writel(clkcon0, S3C2443_CLKDIV0);
134 } 134 }
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c
index ecbea92bf83b..a9f3183e0290 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
@@ -262,45 +262,6 @@ static struct samsung_keypad_platdata smdk6410_keypad_data __initdata = {
262 .cols = 8, 262 .cols = 8,
263}; 263};
264 264
265static int smdk6410_backlight_init(struct device *dev)
266{
267 int ret;
268
269 ret = gpio_request(S3C64XX_GPF(15), "Backlight");
270 if (ret) {
271 printk(KERN_ERR "failed to request GPF for PWM-OUT1\n");
272 return ret;
273 }
274
275 /* Configure GPIO pin with S3C64XX_GPF15_PWM_TOUT1 */
276 s3c_gpio_cfgpin(S3C64XX_GPF(15), S3C_GPIO_SFN(2));
277
278 return 0;
279}
280
281static void smdk6410_backlight_exit(struct device *dev)
282{
283 s3c_gpio_cfgpin(S3C64XX_GPF(15), S3C_GPIO_OUTPUT);
284 gpio_free(S3C64XX_GPF(15));
285}
286
287static struct platform_pwm_backlight_data smdk6410_backlight_data = {
288 .pwm_id = 1,
289 .max_brightness = 255,
290 .dft_brightness = 255,
291 .pwm_period_ns = 78770,
292 .init = smdk6410_backlight_init,
293 .exit = smdk6410_backlight_exit,
294};
295
296static struct platform_device smdk6410_backlight_device = {
297 .name = "pwm-backlight",
298 .dev = {
299 .parent = &s3c_device_timer[1].dev,
300 .platform_data = &smdk6410_backlight_data,
301 },
302};
303
304static struct map_desc smdk6410_iodesc[] = {}; 265static struct map_desc smdk6410_iodesc[] = {};
305 266
306static struct platform_device *smdk6410_devices[] __initdata = { 267static struct platform_device *smdk6410_devices[] __initdata = {
diff --git a/arch/arm/mach-s3c64xx/pm.c b/arch/arm/mach-s3c64xx/pm.c
index 8bad64370689..055e2858b0dd 100644
--- a/arch/arm/mach-s3c64xx/pm.c
+++ b/arch/arm/mach-s3c64xx/pm.c
@@ -16,6 +16,7 @@
16#include <linux/suspend.h> 16#include <linux/suspend.h>
17#include <linux/serial_core.h> 17#include <linux/serial_core.h>
18#include <linux/io.h> 18#include <linux/io.h>
19#include <linux/gpio.h>
19 20
20#include <mach/map.h> 21#include <mach/map.h>
21#include <mach/irqs.h> 22#include <mach/irqs.h>
diff --git a/arch/arm/mach-s5p64x0/irq-eint.c b/arch/arm/mach-s5p64x0/irq-eint.c
index 69ed4545112b..fe7380f5c3cd 100644
--- a/arch/arm/mach-s5p64x0/irq-eint.c
+++ b/arch/arm/mach-s5p64x0/irq-eint.c
@@ -129,7 +129,7 @@ static int s5p64x0_alloc_gc(void)
129 } 129 }
130 130
131 ct = gc->chip_types; 131 ct = gc->chip_types;
132 ct->chip.irq_ack = irq_gc_ack; 132 ct->chip.irq_ack = irq_gc_ack_set_bit;
133 ct->chip.irq_mask = irq_gc_mask_set_bit; 133 ct->chip.irq_mask = irq_gc_mask_set_bit;
134 ct->chip.irq_unmask = irq_gc_mask_clr_bit; 134 ct->chip.irq_unmask = irq_gc_mask_clr_bit;
135 ct->chip.irq_set_type = s5p64x0_irq_eint_set_type; 135 ct->chip.irq_set_type = s5p64x0_irq_eint_set_type;
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
index 52a8e607bcc2..f5f8fa89679c 100644
--- a/arch/arm/mach-s5pv210/clock.c
+++ b/arch/arm/mach-s5pv210/clock.c
@@ -815,8 +815,7 @@ static struct clksrc_clk clksrcs[] = {
815 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 20, .size = 4 }, 815 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 20, .size = 4 },
816 }, { 816 }, {
817 .clk = { 817 .clk = {
818 .name = "sclk_cam", 818 .name = "sclk_cam0",
819 .devname = "s5pv210-fimc.0",
820 .enable = s5pv210_clk_mask0_ctrl, 819 .enable = s5pv210_clk_mask0_ctrl,
821 .ctrlbit = (1 << 3), 820 .ctrlbit = (1 << 3),
822 }, 821 },
@@ -825,8 +824,7 @@ static struct clksrc_clk clksrcs[] = {
825 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 4 }, 824 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 4 },
826 }, { 825 }, {
827 .clk = { 826 .clk = {
828 .name = "sclk_cam", 827 .name = "sclk_cam1",
829 .devname = "s5pv210-fimc.1",
830 .enable = s5pv210_clk_mask0_ctrl, 828 .enable = s5pv210_clk_mask0_ctrl,
831 .ctrlbit = (1 << 4), 829 .ctrlbit = (1 << 4),
832 }, 830 },
diff --git a/arch/arm/mach-s5pv210/pm.c b/arch/arm/mach-s5pv210/pm.c
index 309e388a8a83..f149d278377b 100644
--- a/arch/arm/mach-s5pv210/pm.c
+++ b/arch/arm/mach-s5pv210/pm.c
@@ -88,7 +88,7 @@ static struct sleep_save s5pv210_core_save[] = {
88 SAVE_ITEM(S3C2410_TCNTO(0)), 88 SAVE_ITEM(S3C2410_TCNTO(0)),
89}; 89};
90 90
91void s5pv210_cpu_suspend(unsigned long arg) 91static int s5pv210_cpu_suspend(unsigned long arg)
92{ 92{
93 unsigned long tmp; 93 unsigned long tmp;
94 94
diff --git a/arch/arm/mach-shmobile/board-ag5evm.c b/arch/arm/mach-shmobile/board-ag5evm.c
index ce5c2513c6ce..cdfdd624d21d 100644
--- a/arch/arm/mach-shmobile/board-ag5evm.c
+++ b/arch/arm/mach-shmobile/board-ag5evm.c
@@ -341,6 +341,7 @@ static struct platform_device mipidsi0_device = {
341static struct sh_mobile_sdhi_info sdhi0_info = { 341static struct sh_mobile_sdhi_info sdhi0_info = {
342 .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX, 342 .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX,
343 .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX, 343 .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX,
344 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT,
344 .tmio_caps = MMC_CAP_SD_HIGHSPEED, 345 .tmio_caps = MMC_CAP_SD_HIGHSPEED,
345 .tmio_ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29, 346 .tmio_ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
346}; 347};
@@ -382,7 +383,7 @@ void ag5evm_sdhi1_set_pwr(struct platform_device *pdev, int state)
382} 383}
383 384
384static struct sh_mobile_sdhi_info sh_sdhi1_info = { 385static struct sh_mobile_sdhi_info sh_sdhi1_info = {
385 .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE, 386 .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE | TMIO_MMC_HAS_IDLE_WAIT,
386 .tmio_caps = MMC_CAP_NONREMOVABLE | MMC_CAP_SDIO_IRQ, 387 .tmio_caps = MMC_CAP_NONREMOVABLE | MMC_CAP_SDIO_IRQ,
387 .tmio_ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, 388 .tmio_ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34,
388 .set_pwr = ag5evm_sdhi1_set_pwr, 389 .set_pwr = ag5evm_sdhi1_set_pwr,
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index 0ea71f8d4b89..17c19dc25604 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -641,6 +641,8 @@ static struct usbhs_private usbhs0_private = {
641 }, 641 },
642 .driver_param = { 642 .driver_param = {
643 .buswait_bwait = 4, 643 .buswait_bwait = 4,
644 .d0_tx_id = SHDMA_SLAVE_USB0_TX,
645 .d1_rx_id = SHDMA_SLAVE_USB0_RX,
644 }, 646 },
645 }, 647 },
646}; 648};
@@ -810,6 +812,8 @@ static struct usbhs_private usbhs1_private = {
810 .buswait_bwait = 4, 812 .buswait_bwait = 4,
811 .pipe_type = usbhs1_pipe_cfg, 813 .pipe_type = usbhs1_pipe_cfg,
812 .pipe_size = ARRAY_SIZE(usbhs1_pipe_cfg), 814 .pipe_size = ARRAY_SIZE(usbhs1_pipe_cfg),
815 .d0_tx_id = SHDMA_SLAVE_USB1_TX,
816 .d1_rx_id = SHDMA_SLAVE_USB1_RX,
813 }, 817 },
814 }, 818 },
815}; 819};
diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c
index e6e11e4e2d43..66975921e646 100644
--- a/arch/arm/mach-shmobile/clock-sh7372.c
+++ b/arch/arm/mach-shmobile/clock-sh7372.c
@@ -503,16 +503,17 @@ static struct clk *late_main_clks[] = {
503 &sh7372_fsidivb_clk, 503 &sh7372_fsidivb_clk,
504}; 504};
505 505
506enum { MSTP001, 506enum { MSTP001, MSTP000,
507 MSTP131, MSTP130, 507 MSTP131, MSTP130,
508 MSTP129, MSTP128, MSTP127, MSTP126, MSTP125, 508 MSTP129, MSTP128, MSTP127, MSTP126, MSTP125,
509 MSTP118, MSTP117, MSTP116, MSTP113, 509 MSTP118, MSTP117, MSTP116, MSTP113,
510 MSTP106, MSTP101, MSTP100, 510 MSTP106, MSTP101, MSTP100,
511 MSTP223, 511 MSTP223,
512 MSTP218, MSTP217, MSTP216, 512 MSTP218, MSTP217, MSTP216, MSTP214, MSTP208, MSTP207,
513 MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200, 513 MSTP206, MSTP205, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
514 MSTP329, MSTP328, MSTP323, MSTP322, MSTP314, MSTP313, MSTP312, 514 MSTP328, MSTP323, MSTP322, MSTP314, MSTP313, MSTP312,
515 MSTP423, MSTP415, MSTP413, MSTP411, MSTP410, MSTP406, MSTP403, 515 MSTP423, MSTP415, MSTP413, MSTP411, MSTP410, MSTP407, MSTP406,
516 MSTP405, MSTP404, MSTP403, MSTP400,
516 MSTP_NR }; 517 MSTP_NR };
517 518
518#define MSTP(_parent, _reg, _bit, _flags) \ 519#define MSTP(_parent, _reg, _bit, _flags) \
@@ -520,6 +521,7 @@ enum { MSTP001,
520 521
521static struct clk mstp_clks[MSTP_NR] = { 522static struct clk mstp_clks[MSTP_NR] = {
522 [MSTP001] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR0, 1, 0), /* IIC2 */ 523 [MSTP001] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR0, 1, 0), /* IIC2 */
524 [MSTP000] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR0, 0, 0), /* MSIOF0 */
523 [MSTP131] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 31, 0), /* VEU3 */ 525 [MSTP131] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 31, 0), /* VEU3 */
524 [MSTP130] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 30, 0), /* VEU2 */ 526 [MSTP130] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 30, 0), /* VEU2 */
525 [MSTP129] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 29, 0), /* VEU1 */ 527 [MSTP129] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 29, 0), /* VEU1 */
@@ -538,14 +540,16 @@ static struct clk mstp_clks[MSTP_NR] = {
538 [MSTP218] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 18, 0), /* DMAC1 */ 540 [MSTP218] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 18, 0), /* DMAC1 */
539 [MSTP217] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 17, 0), /* DMAC2 */ 541 [MSTP217] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 17, 0), /* DMAC2 */
540 [MSTP216] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 16, 0), /* DMAC3 */ 542 [MSTP216] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 16, 0), /* DMAC3 */
543 [MSTP214] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 14, 0), /* USBDMAC */
544 [MSTP208] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 8, 0), /* MSIOF1 */
541 [MSTP207] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */ 545 [MSTP207] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */
542 [MSTP206] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */ 546 [MSTP206] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */
547 [MSTP205] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 5, 0), /* MSIOF2 */
543 [MSTP204] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 4, 0), /* SCIFA0 */ 548 [MSTP204] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 4, 0), /* SCIFA0 */
544 [MSTP203] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 3, 0), /* SCIFA1 */ 549 [MSTP203] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 3, 0), /* SCIFA1 */
545 [MSTP202] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 2, 0), /* SCIFA2 */ 550 [MSTP202] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 2, 0), /* SCIFA2 */
546 [MSTP201] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 1, 0), /* SCIFA3 */ 551 [MSTP201] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 1, 0), /* SCIFA3 */
547 [MSTP200] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */ 552 [MSTP200] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */
548 [MSTP329] = MSTP(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */
549 [MSTP328] = MSTP(&div6_clks[DIV6_SPU], SMSTPCR3, 28, 0), /* FSI2 */ 553 [MSTP328] = MSTP(&div6_clks[DIV6_SPU], SMSTPCR3, 28, 0), /* FSI2 */
550 [MSTP323] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 23, 0), /* IIC1 */ 554 [MSTP323] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 23, 0), /* IIC1 */
551 [MSTP322] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 22, 0), /* USB0 */ 555 [MSTP322] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 22, 0), /* USB0 */
@@ -557,8 +561,12 @@ static struct clk mstp_clks[MSTP_NR] = {
557 [MSTP413] = MSTP(&pllc1_div2_clk, SMSTPCR4, 13, 0), /* HDMI */ 561 [MSTP413] = MSTP(&pllc1_div2_clk, SMSTPCR4, 13, 0), /* HDMI */
558 [MSTP411] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 11, 0), /* IIC3 */ 562 [MSTP411] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 11, 0), /* IIC3 */
559 [MSTP410] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 10, 0), /* IIC4 */ 563 [MSTP410] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 10, 0), /* IIC4 */
564 [MSTP407] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 7, 0), /* USB-DMAC1 */
560 [MSTP406] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 6, 0), /* USB1 */ 565 [MSTP406] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 6, 0), /* USB1 */
566 [MSTP405] = MSTP(&r_clk, SMSTPCR4, 5, 0), /* CMT4 */
567 [MSTP404] = MSTP(&r_clk, SMSTPCR4, 4, 0), /* CMT3 */
561 [MSTP403] = MSTP(&r_clk, SMSTPCR4, 3, 0), /* KEYSC */ 568 [MSTP403] = MSTP(&r_clk, SMSTPCR4, 3, 0), /* KEYSC */
569 [MSTP400] = MSTP(&r_clk, SMSTPCR4, 0, 0), /* CMT2 */
562}; 570};
563 571
564static struct clk_lookup lookups[] = { 572static struct clk_lookup lookups[] = {
@@ -609,6 +617,7 @@ static struct clk_lookup lookups[] = {
609 617
610 /* MSTP32 clocks */ 618 /* MSTP32 clocks */
611 CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* IIC2 */ 619 CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* IIC2 */
620 CLKDEV_DEV_ID("spi_sh_msiof.0", &mstp_clks[MSTP000]), /* MSIOF0 */
612 CLKDEV_DEV_ID("uio_pdrv_genirq.4", &mstp_clks[MSTP131]), /* VEU3 */ 621 CLKDEV_DEV_ID("uio_pdrv_genirq.4", &mstp_clks[MSTP131]), /* VEU3 */
613 CLKDEV_DEV_ID("uio_pdrv_genirq.3", &mstp_clks[MSTP130]), /* VEU2 */ 622 CLKDEV_DEV_ID("uio_pdrv_genirq.3", &mstp_clks[MSTP130]), /* VEU2 */
614 CLKDEV_DEV_ID("uio_pdrv_genirq.2", &mstp_clks[MSTP129]), /* VEU1 */ 623 CLKDEV_DEV_ID("uio_pdrv_genirq.2", &mstp_clks[MSTP129]), /* VEU1 */
@@ -629,14 +638,16 @@ static struct clk_lookup lookups[] = {
629 CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]), /* DMAC1 */ 638 CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]), /* DMAC1 */
630 CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[MSTP217]), /* DMAC2 */ 639 CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[MSTP217]), /* DMAC2 */
631 CLKDEV_DEV_ID("sh-dma-engine.2", &mstp_clks[MSTP216]), /* DMAC3 */ 640 CLKDEV_DEV_ID("sh-dma-engine.2", &mstp_clks[MSTP216]), /* DMAC3 */
641 CLKDEV_DEV_ID("sh-dma-engine.3", &mstp_clks[MSTP214]), /* USB-DMAC0 */
642 CLKDEV_DEV_ID("spi_sh_msiof.1", &mstp_clks[MSTP208]), /* MSIOF1 */
632 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */ 643 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */
633 CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP206]), /* SCIFB */ 644 CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP206]), /* SCIFB */
645 CLKDEV_DEV_ID("spi_sh_msiof.2", &mstp_clks[MSTP205]), /* MSIOF2 */
634 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */ 646 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */
635 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */ 647 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */
636 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]), /* SCIFA2 */ 648 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]), /* SCIFA2 */
637 CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]), /* SCIFA3 */ 649 CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]), /* SCIFA3 */
638 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), /* SCIFA4 */ 650 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), /* SCIFA4 */
639 CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), /* CMT10 */
640 CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]), /* FSI2 */ 651 CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]), /* FSI2 */
641 CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* IIC1 */ 652 CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* IIC1 */
642 CLKDEV_DEV_ID("r8a66597_hcd.0", &mstp_clks[MSTP322]), /* USB0 */ 653 CLKDEV_DEV_ID("r8a66597_hcd.0", &mstp_clks[MSTP322]), /* USB0 */
@@ -650,10 +661,14 @@ static struct clk_lookup lookups[] = {
650 CLKDEV_DEV_ID("sh-mobile-hdmi", &mstp_clks[MSTP413]), /* HDMI */ 661 CLKDEV_DEV_ID("sh-mobile-hdmi", &mstp_clks[MSTP413]), /* HDMI */
651 CLKDEV_DEV_ID("i2c-sh_mobile.3", &mstp_clks[MSTP411]), /* IIC3 */ 662 CLKDEV_DEV_ID("i2c-sh_mobile.3", &mstp_clks[MSTP411]), /* IIC3 */
652 CLKDEV_DEV_ID("i2c-sh_mobile.4", &mstp_clks[MSTP410]), /* IIC4 */ 663 CLKDEV_DEV_ID("i2c-sh_mobile.4", &mstp_clks[MSTP410]), /* IIC4 */
664 CLKDEV_DEV_ID("sh-dma-engine.4", &mstp_clks[MSTP407]), /* USB-DMAC1 */
653 CLKDEV_DEV_ID("r8a66597_hcd.1", &mstp_clks[MSTP406]), /* USB1 */ 665 CLKDEV_DEV_ID("r8a66597_hcd.1", &mstp_clks[MSTP406]), /* USB1 */
654 CLKDEV_DEV_ID("r8a66597_udc.1", &mstp_clks[MSTP406]), /* USB1 */ 666 CLKDEV_DEV_ID("r8a66597_udc.1", &mstp_clks[MSTP406]), /* USB1 */
655 CLKDEV_DEV_ID("renesas_usbhs.1", &mstp_clks[MSTP406]), /* USB1 */ 667 CLKDEV_DEV_ID("renesas_usbhs.1", &mstp_clks[MSTP406]), /* USB1 */
668 CLKDEV_DEV_ID("sh_cmt.4", &mstp_clks[MSTP405]), /* CMT4 */
669 CLKDEV_DEV_ID("sh_cmt.3", &mstp_clks[MSTP404]), /* CMT3 */
656 CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */ 670 CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */
671 CLKDEV_DEV_ID("sh_cmt.2", &mstp_clks[MSTP400]), /* CMT2 */
657 672
658 CLKDEV_ICK_ID("hdmi", "sh_mobile_lcdc_fb.1", 673 CLKDEV_ICK_ID("hdmi", "sh_mobile_lcdc_fb.1",
659 &div6_reparent_clks[DIV6_HDMI]), 674 &div6_reparent_clks[DIV6_HDMI]),
diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c
index 6db2ccabc2bf..61a846bb30f2 100644
--- a/arch/arm/mach-shmobile/clock-sh73a0.c
+++ b/arch/arm/mach-shmobile/clock-sh73a0.c
@@ -365,7 +365,7 @@ void __init sh73a0_clock_init(void)
365 __raw_writel(0x108, SD2CKCR); 365 __raw_writel(0x108, SD2CKCR);
366 366
367 /* detect main clock parent */ 367 /* detect main clock parent */
368 switch ((__raw_readl(CKSCR) >> 24) & 0x03) { 368 switch ((__raw_readl(CKSCR) >> 28) & 0x03) {
369 case 0: 369 case 0:
370 main_clk.parent = &sh73a0_extal1_clk; 370 main_clk.parent = &sh73a0_extal1_clk;
371 break; 371 break;
diff --git a/arch/arm/mach-shmobile/include/mach/sh7372.h b/arch/arm/mach-shmobile/include/mach/sh7372.h
index ce595cee86cd..24e63a85e669 100644
--- a/arch/arm/mach-shmobile/include/mach/sh7372.h
+++ b/arch/arm/mach-shmobile/include/mach/sh7372.h
@@ -459,6 +459,10 @@ enum {
459 SHDMA_SLAVE_SDHI2_TX, 459 SHDMA_SLAVE_SDHI2_TX,
460 SHDMA_SLAVE_MMCIF_RX, 460 SHDMA_SLAVE_MMCIF_RX,
461 SHDMA_SLAVE_MMCIF_TX, 461 SHDMA_SLAVE_MMCIF_TX,
462 SHDMA_SLAVE_USB0_TX,
463 SHDMA_SLAVE_USB0_RX,
464 SHDMA_SLAVE_USB1_TX,
465 SHDMA_SLAVE_USB1_RX,
462}; 466};
463 467
464extern struct clk sh7372_extal1_clk; 468extern struct clk sh7372_extal1_clk;
diff --git a/arch/arm/mach-shmobile/intc-sh7372.c b/arch/arm/mach-shmobile/intc-sh7372.c
index 3b28743c77eb..739315e30eb9 100644
--- a/arch/arm/mach-shmobile/intc-sh7372.c
+++ b/arch/arm/mach-shmobile/intc-sh7372.c
@@ -379,7 +379,7 @@ enum {
379 /* BBIF2 */ 379 /* BBIF2 */
380 VPU, 380 VPU,
381 TSIF1, 381 TSIF1,
382 _3DG_SGX530, 382 /* 3DG */
383 _2DDMAC, 383 _2DDMAC,
384 IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2, 384 IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2,
385 IPMMU_IPMMUR, IPMMU_IPMMUR2, 385 IPMMU_IPMMUR, IPMMU_IPMMUR2,
@@ -436,7 +436,7 @@ static struct intc_vect intcs_vectors[] = {
436 /* BBIF2 */ 436 /* BBIF2 */
437 INTCS_VECT(VPU, 0x980), 437 INTCS_VECT(VPU, 0x980),
438 INTCS_VECT(TSIF1, 0x9a0), 438 INTCS_VECT(TSIF1, 0x9a0),
439 INTCS_VECT(_3DG_SGX530, 0x9e0), 439 /* 3DG */
440 INTCS_VECT(_2DDMAC, 0xa00), 440 INTCS_VECT(_2DDMAC, 0xa00),
441 INTCS_VECT(IIC2_ALI2, 0xa80), INTCS_VECT(IIC2_TACKI2, 0xaa0), 441 INTCS_VECT(IIC2_ALI2, 0xa80), INTCS_VECT(IIC2_TACKI2, 0xaa0),
442 INTCS_VECT(IIC2_WAITI2, 0xac0), INTCS_VECT(IIC2_DTEI2, 0xae0), 442 INTCS_VECT(IIC2_WAITI2, 0xac0), INTCS_VECT(IIC2_DTEI2, 0xae0),
@@ -521,7 +521,7 @@ static struct intc_mask_reg intcs_mask_registers[] = {
521 RTDMAC_1_DEI3, RTDMAC_1_DEI2, RTDMAC_1_DEI1, RTDMAC_1_DEI0 } }, 521 RTDMAC_1_DEI3, RTDMAC_1_DEI2, RTDMAC_1_DEI1, RTDMAC_1_DEI0 } },
522 { 0xffd20198, 0xffd201d8, 8, /* IMR6SA / IMCR6SA */ 522 { 0xffd20198, 0xffd201d8, 8, /* IMR6SA / IMCR6SA */
523 { 0, 0, MSIOF, 0, 523 { 0, 0, MSIOF, 0,
524 _3DG_SGX530, 0, 0, 0 } }, 524 0, 0, 0, 0 } },
525 { 0xffd2019c, 0xffd201dc, 8, /* IMR7SA / IMCR7SA */ 525 { 0xffd2019c, 0xffd201dc, 8, /* IMR7SA / IMCR7SA */
526 { 0, TMU_TUNI2, TMU_TUNI1, TMU_TUNI0, 526 { 0, TMU_TUNI2, TMU_TUNI1, TMU_TUNI0,
527 0, 0, 0, 0 } }, 527 0, 0, 0, 0 } },
@@ -561,7 +561,6 @@ static struct intc_prio_reg intcs_prio_registers[] = {
561 TMU_TUNI2, TSIF1 } }, 561 TMU_TUNI2, TSIF1 } },
562 { 0xffd2001c, 0, 16, 4, /* IPRHS */ { 0, 0, VEU, BEU } }, 562 { 0xffd2001c, 0, 16, 4, /* IPRHS */ { 0, 0, VEU, BEU } },
563 { 0xffd20020, 0, 16, 4, /* IPRIS */ { 0, MSIOF, TSIF0, IIC0 } }, 563 { 0xffd20020, 0, 16, 4, /* IPRIS */ { 0, MSIOF, TSIF0, IIC0 } },
564 { 0xffd20024, 0, 16, 4, /* IPRJS */ { 0, _3DG_SGX530, 0, 0 } },
565 { 0xffd20028, 0, 16, 4, /* IPRKS */ { 0, 0, LMB, 0 } }, 564 { 0xffd20028, 0, 16, 4, /* IPRKS */ { 0, 0, LMB, 0 } },
566 { 0xffd2002c, 0, 16, 4, /* IPRLS */ { IPMMU, 0, 0, 0 } }, 565 { 0xffd2002c, 0, 16, 4, /* IPRLS */ { IPMMU, 0, 0, 0 } },
567 { 0xffd20030, 0, 16, 4, /* IPRMS */ { IIC2, 0, 0, 0 } }, 566 { 0xffd20030, 0, 16, 4, /* IPRMS */ { IIC2, 0, 0, 0 } },
diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c
index 79f0413d8725..2d9b1b1a2538 100644
--- a/arch/arm/mach-shmobile/setup-sh7372.c
+++ b/arch/arm/mach-shmobile/setup-sh7372.c
@@ -169,35 +169,35 @@ static struct platform_device scif6_device = {
169}; 169};
170 170
171/* CMT */ 171/* CMT */
172static struct sh_timer_config cmt10_platform_data = { 172static struct sh_timer_config cmt2_platform_data = {
173 .name = "CMT10", 173 .name = "CMT2",
174 .channel_offset = 0x10, 174 .channel_offset = 0x40,
175 .timer_bit = 0, 175 .timer_bit = 5,
176 .clockevent_rating = 125, 176 .clockevent_rating = 125,
177 .clocksource_rating = 125, 177 .clocksource_rating = 125,
178}; 178};
179 179
180static struct resource cmt10_resources[] = { 180static struct resource cmt2_resources[] = {
181 [0] = { 181 [0] = {
182 .name = "CMT10", 182 .name = "CMT2",
183 .start = 0xe6138010, 183 .start = 0xe6130040,
184 .end = 0xe613801b, 184 .end = 0xe613004b,
185 .flags = IORESOURCE_MEM, 185 .flags = IORESOURCE_MEM,
186 }, 186 },
187 [1] = { 187 [1] = {
188 .start = evt2irq(0x0b00), /* CMT1_CMT10 */ 188 .start = evt2irq(0x0b80), /* CMT2 */
189 .flags = IORESOURCE_IRQ, 189 .flags = IORESOURCE_IRQ,
190 }, 190 },
191}; 191};
192 192
193static struct platform_device cmt10_device = { 193static struct platform_device cmt2_device = {
194 .name = "sh_cmt", 194 .name = "sh_cmt",
195 .id = 10, 195 .id = 2,
196 .dev = { 196 .dev = {
197 .platform_data = &cmt10_platform_data, 197 .platform_data = &cmt2_platform_data,
198 }, 198 },
199 .resource = cmt10_resources, 199 .resource = cmt2_resources,
200 .num_resources = ARRAY_SIZE(cmt10_resources), 200 .num_resources = ARRAY_SIZE(cmt2_resources),
201}; 201};
202 202
203/* TMU */ 203/* TMU */
@@ -602,6 +602,150 @@ static struct platform_device dma2_device = {
602 }, 602 },
603}; 603};
604 604
605/*
606 * USB-DMAC
607 */
608
609unsigned int usbts_shift[] = {3, 4, 5};
610
611enum {
612 XMIT_SZ_8BYTE = 0,
613 XMIT_SZ_16BYTE = 1,
614 XMIT_SZ_32BYTE = 2,
615};
616
617#define USBTS_INDEX2VAL(i) (((i) & 3) << 6)
618
619static const struct sh_dmae_channel sh7372_usb_dmae_channels[] = {
620 {
621 .offset = 0,
622 }, {
623 .offset = 0x20,
624 },
625};
626
627/* USB DMAC0 */
628static const struct sh_dmae_slave_config sh7372_usb_dmae0_slaves[] = {
629 {
630 .slave_id = SHDMA_SLAVE_USB0_TX,
631 .chcr = USBTS_INDEX2VAL(XMIT_SZ_8BYTE),
632 }, {
633 .slave_id = SHDMA_SLAVE_USB0_RX,
634 .chcr = USBTS_INDEX2VAL(XMIT_SZ_8BYTE),
635 },
636};
637
638static struct sh_dmae_pdata usb_dma0_platform_data = {
639 .slave = sh7372_usb_dmae0_slaves,
640 .slave_num = ARRAY_SIZE(sh7372_usb_dmae0_slaves),
641 .channel = sh7372_usb_dmae_channels,
642 .channel_num = ARRAY_SIZE(sh7372_usb_dmae_channels),
643 .ts_low_shift = 6,
644 .ts_low_mask = 0xc0,
645 .ts_high_shift = 0,
646 .ts_high_mask = 0,
647 .ts_shift = usbts_shift,
648 .ts_shift_num = ARRAY_SIZE(usbts_shift),
649 .dmaor_init = DMAOR_DME,
650 .chcr_offset = 0x14,
651 .chcr_ie_bit = 1 << 5,
652 .dmaor_is_32bit = 1,
653 .needs_tend_set = 1,
654 .no_dmars = 1,
655};
656
657static struct resource sh7372_usb_dmae0_resources[] = {
658 {
659 /* Channel registers and DMAOR */
660 .start = 0xe68a0020,
661 .end = 0xe68a0064 - 1,
662 .flags = IORESOURCE_MEM,
663 },
664 {
665 /* VCR/SWR/DMICR */
666 .start = 0xe68a0000,
667 .end = 0xe68a0014 - 1,
668 .flags = IORESOURCE_MEM,
669 },
670 {
671 /* IRQ for channels */
672 .start = evt2irq(0x0a00),
673 .end = evt2irq(0x0a00),
674 .flags = IORESOURCE_IRQ,
675 },
676};
677
678static struct platform_device usb_dma0_device = {
679 .name = "sh-dma-engine",
680 .id = 3,
681 .resource = sh7372_usb_dmae0_resources,
682 .num_resources = ARRAY_SIZE(sh7372_usb_dmae0_resources),
683 .dev = {
684 .platform_data = &usb_dma0_platform_data,
685 },
686};
687
688/* USB DMAC1 */
689static const struct sh_dmae_slave_config sh7372_usb_dmae1_slaves[] = {
690 {
691 .slave_id = SHDMA_SLAVE_USB1_TX,
692 .chcr = USBTS_INDEX2VAL(XMIT_SZ_8BYTE),
693 }, {
694 .slave_id = SHDMA_SLAVE_USB1_RX,
695 .chcr = USBTS_INDEX2VAL(XMIT_SZ_8BYTE),
696 },
697};
698
699static struct sh_dmae_pdata usb_dma1_platform_data = {
700 .slave = sh7372_usb_dmae1_slaves,
701 .slave_num = ARRAY_SIZE(sh7372_usb_dmae1_slaves),
702 .channel = sh7372_usb_dmae_channels,
703 .channel_num = ARRAY_SIZE(sh7372_usb_dmae_channels),
704 .ts_low_shift = 6,
705 .ts_low_mask = 0xc0,
706 .ts_high_shift = 0,
707 .ts_high_mask = 0,
708 .ts_shift = usbts_shift,
709 .ts_shift_num = ARRAY_SIZE(usbts_shift),
710 .dmaor_init = DMAOR_DME,
711 .chcr_offset = 0x14,
712 .chcr_ie_bit = 1 << 5,
713 .dmaor_is_32bit = 1,
714 .needs_tend_set = 1,
715 .no_dmars = 1,
716};
717
718static struct resource sh7372_usb_dmae1_resources[] = {
719 {
720 /* Channel registers and DMAOR */
721 .start = 0xe68c0020,
722 .end = 0xe68c0064 - 1,
723 .flags = IORESOURCE_MEM,
724 },
725 {
726 /* VCR/SWR/DMICR */
727 .start = 0xe68c0000,
728 .end = 0xe68c0014 - 1,
729 .flags = IORESOURCE_MEM,
730 },
731 {
732 /* IRQ for channels */
733 .start = evt2irq(0x1d00),
734 .end = evt2irq(0x1d00),
735 .flags = IORESOURCE_IRQ,
736 },
737};
738
739static struct platform_device usb_dma1_device = {
740 .name = "sh-dma-engine",
741 .id = 4,
742 .resource = sh7372_usb_dmae1_resources,
743 .num_resources = ARRAY_SIZE(sh7372_usb_dmae1_resources),
744 .dev = {
745 .platform_data = &usb_dma1_platform_data,
746 },
747};
748
605/* VPU */ 749/* VPU */
606static struct uio_info vpu_platform_data = { 750static struct uio_info vpu_platform_data = {
607 .name = "VPU5HG", 751 .name = "VPU5HG",
@@ -818,7 +962,7 @@ static struct platform_device *sh7372_early_devices[] __initdata = {
818 &scif4_device, 962 &scif4_device,
819 &scif5_device, 963 &scif5_device,
820 &scif6_device, 964 &scif6_device,
821 &cmt10_device, 965 &cmt2_device,
822 &tmu00_device, 966 &tmu00_device,
823 &tmu01_device, 967 &tmu01_device,
824}; 968};
@@ -829,6 +973,8 @@ static struct platform_device *sh7372_late_devices[] __initdata = {
829 &dma0_device, 973 &dma0_device,
830 &dma1_device, 974 &dma1_device,
831 &dma2_device, 975 &dma2_device,
976 &usb_dma0_device,
977 &usb_dma1_device,
832 &vpu_device, 978 &vpu_device,
833 &veu0_device, 979 &veu0_device,
834 &veu1_device, 980 &veu1_device,
diff --git a/arch/arm/mach-tegra/cpu-tegra.c b/arch/arm/mach-tegra/cpu-tegra.c
index 0e1016a827ac..0e0fd4d889bd 100644
--- a/arch/arm/mach-tegra/cpu-tegra.c
+++ b/arch/arm/mach-tegra/cpu-tegra.c
@@ -32,7 +32,6 @@
32 32
33#include <asm/system.h> 33#include <asm/system.h>
34 34
35#include <mach/hardware.h>
36#include <mach/clk.h> 35#include <mach/clk.h>
37 36
38/* Frequency table index must be sequential starting at 0 */ 37/* Frequency table index must be sequential starting at 0 */
diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
index 4210cb434dbc..a3e0c8692f0d 100644
--- a/arch/arm/mach-ux500/Kconfig
+++ b/arch/arm/mach-ux500/Kconfig
@@ -6,6 +6,7 @@ config UX500_SOC_COMMON
6 select ARM_GIC 6 select ARM_GIC
7 select HAS_MTU 7 select HAS_MTU
8 select ARM_ERRATA_753970 8 select ARM_ERRATA_753970
9 select ARM_ERRATA_754322
9 10
10menu "Ux500 SoC" 11menu "Ux500 SoC"
11 12
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
index 9e6b93b1a043..d0d267a8d3f9 100644
--- a/arch/arm/mach-vexpress/v2m.c
+++ b/arch/arm/mach-vexpress/v2m.c
@@ -318,6 +318,10 @@ static struct clk v2m_sp804_clk = {
318 .rate = 1000000, 318 .rate = 1000000,
319}; 319};
320 320
321static struct clk v2m_ref_clk = {
322 .rate = 32768,
323};
324
321static struct clk dummy_apb_pclk; 325static struct clk dummy_apb_pclk;
322 326
323static struct clk_lookup v2m_lookups[] = { 327static struct clk_lookup v2m_lookups[] = {
@@ -348,6 +352,9 @@ static struct clk_lookup v2m_lookups[] = {
348 }, { /* CLCD */ 352 }, { /* CLCD */
349 .dev_id = "mb:clcd", 353 .dev_id = "mb:clcd",
350 .clk = &osc1_clk, 354 .clk = &osc1_clk,
355 }, { /* SP805 WDT */
356 .dev_id = "mb:wdt",
357 .clk = &v2m_ref_clk,
351 }, { /* SP804 timers */ 358 }, { /* SP804 timers */
352 .dev_id = "sp804", 359 .dev_id = "sp804",
353 .con_id = "v2m-timer0", 360 .con_id = "v2m-timer0",
diff --git a/arch/arm/mm/abort-macro.S b/arch/arm/mm/abort-macro.S
index 52162d59407a..2cbf68ef0e83 100644
--- a/arch/arm/mm/abort-macro.S
+++ b/arch/arm/mm/abort-macro.S
@@ -17,7 +17,7 @@
17 cmp \tmp, # 0x5600 @ Is it ldrsb? 17 cmp \tmp, # 0x5600 @ Is it ldrsb?
18 orreq \tmp, \tmp, #1 << 11 @ Set L-bit if yes 18 orreq \tmp, \tmp, #1 << 11 @ Set L-bit if yes
19 tst \tmp, #1 << 11 @ L = 0 -> write 19 tst \tmp, #1 << 11 @ L = 0 -> write
20 orreq \psr, \psr, #1 << 11 @ yes. 20 orreq \fsr, \fsr, #1 << 11 @ yes.
21 b do_DataAbort 21 b do_DataAbort
22not_thumb: 22not_thumb:
23 .endm 23 .endm
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 44c086710d2b..9ecfdb511951 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -277,6 +277,25 @@ static void l2x0_disable(void)
277 spin_unlock_irqrestore(&l2x0_lock, flags); 277 spin_unlock_irqrestore(&l2x0_lock, flags);
278} 278}
279 279
280static void __init l2x0_unlock(__u32 cache_id)
281{
282 int lockregs;
283 int i;
284
285 if (cache_id == L2X0_CACHE_ID_PART_L310)
286 lockregs = 8;
287 else
288 /* L210 and unknown types */
289 lockregs = 1;
290
291 for (i = 0; i < lockregs; i++) {
292 writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_D_BASE +
293 i * L2X0_LOCKDOWN_STRIDE);
294 writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_I_BASE +
295 i * L2X0_LOCKDOWN_STRIDE);
296 }
297}
298
280void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask) 299void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
281{ 300{
282 __u32 aux; 301 __u32 aux;
@@ -328,6 +347,8 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
328 * accessing the below registers will fault. 347 * accessing the below registers will fault.
329 */ 348 */
330 if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) { 349 if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {
350 /* Make sure that I&D is not locked down when starting */
351 l2x0_unlock(cache_id);
331 352
332 /* l2x0 controller is disabled */ 353 /* l2x0 controller is disabled */
333 writel_relaxed(aux, l2x0_base + L2X0_AUX_CTRL); 354 writel_relaxed(aux, l2x0_base + L2X0_AUX_CTRL);
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index 3b24bfa3b828..07c4bc8ea0a4 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -174,6 +174,10 @@ ENTRY(v7_coherent_user_range)
174 dcache_line_size r2, r3 174 dcache_line_size r2, r3
175 sub r3, r2, #1 175 sub r3, r2, #1
176 bic r12, r0, r3 176 bic r12, r0, r3
177#ifdef CONFIG_ARM_ERRATA_764369
178 ALT_SMP(W(dsb))
179 ALT_UP(W(nop))
180#endif
1771: 1811:
178 USER( mcr p15, 0, r12, c7, c11, 1 ) @ clean D line to the point of unification 182 USER( mcr p15, 0, r12, c7, c11, 1 ) @ clean D line to the point of unification
179 add r12, r12, r2 183 add r12, r12, r2
@@ -223,6 +227,10 @@ ENTRY(v7_flush_kern_dcache_area)
223 add r1, r0, r1 227 add r1, r0, r1
224 sub r3, r2, #1 228 sub r3, r2, #1
225 bic r0, r0, r3 229 bic r0, r0, r3
230#ifdef CONFIG_ARM_ERRATA_764369
231 ALT_SMP(W(dsb))
232 ALT_UP(W(nop))
233#endif
2261: 2341:
227 mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line / unified line 235 mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line / unified line
228 add r0, r0, r2 236 add r0, r0, r2
@@ -247,6 +255,10 @@ v7_dma_inv_range:
247 sub r3, r2, #1 255 sub r3, r2, #1
248 tst r0, r3 256 tst r0, r3
249 bic r0, r0, r3 257 bic r0, r0, r3
258#ifdef CONFIG_ARM_ERRATA_764369
259 ALT_SMP(W(dsb))
260 ALT_UP(W(nop))
261#endif
250 mcrne p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line 262 mcrne p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line
251 263
252 tst r1, r3 264 tst r1, r3
@@ -270,6 +282,10 @@ v7_dma_clean_range:
270 dcache_line_size r2, r3 282 dcache_line_size r2, r3
271 sub r3, r2, #1 283 sub r3, r2, #1
272 bic r0, r0, r3 284 bic r0, r0, r3
285#ifdef CONFIG_ARM_ERRATA_764369
286 ALT_SMP(W(dsb))
287 ALT_UP(W(nop))
288#endif
2731: 2891:
274 mcr p15, 0, r0, c7, c10, 1 @ clean D / U line 290 mcr p15, 0, r0, c7, c10, 1 @ clean D / U line
275 add r0, r0, r2 291 add r0, r0, r2
@@ -288,6 +304,10 @@ ENTRY(v7_dma_flush_range)
288 dcache_line_size r2, r3 304 dcache_line_size r2, r3
289 sub r3, r2, #1 305 sub r3, r2, #1
290 bic r0, r0, r3 306 bic r0, r0, r3
307#ifdef CONFIG_ARM_ERRATA_764369
308 ALT_SMP(W(dsb))
309 ALT_UP(W(nop))
310#endif
2911: 3111:
292 mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line 312 mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line
293 add r0, r0, r2 313 add r0, r0, r2
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 0a0a1e7c20d2..c3ff82f92d9c 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -324,6 +324,8 @@ __dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp,
324 324
325 if (addr) 325 if (addr)
326 *handle = pfn_to_dma(dev, page_to_pfn(page)); 326 *handle = pfn_to_dma(dev, page_to_pfn(page));
327 else
328 __dma_free_buffer(page, size);
327 329
328 return addr; 330 return addr;
329} 331}
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 91bca355cd31..f8037ba338ac 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -298,7 +298,7 @@ static void __init arm_bootmem_free(unsigned long min, unsigned long max_low,
298#ifdef CONFIG_HAVE_ARCH_PFN_VALID 298#ifdef CONFIG_HAVE_ARCH_PFN_VALID
299int pfn_valid(unsigned long pfn) 299int pfn_valid(unsigned long pfn)
300{ 300{
301 return memblock_is_memory(pfn << PAGE_SHIFT); 301 return memblock_is_memory(__pfn_to_phys(pfn));
302} 302}
303EXPORT_SYMBOL(pfn_valid); 303EXPORT_SYMBOL(pfn_valid);
304#endif 304#endif
@@ -496,6 +496,13 @@ static void __init free_unused_memmap(struct meminfo *mi)
496 */ 496 */
497 bank_start = min(bank_start, 497 bank_start = min(bank_start,
498 ALIGN(prev_bank_end, PAGES_PER_SECTION)); 498 ALIGN(prev_bank_end, PAGES_PER_SECTION));
499#else
500 /*
501 * Align down here since the VM subsystem insists that the
502 * memmap entries are valid from the bank start aligned to
503 * MAX_ORDER_NR_PAGES.
504 */
505 bank_start = round_down(bank_start, MAX_ORDER_NR_PAGES);
499#endif 506#endif
500 /* 507 /*
501 * If we had a previous bank, and there is a space 508 * If we had a previous bank, and there is a space
diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S
index 92bd102e3982..2e6849b41f66 100644
--- a/arch/arm/mm/proc-arm920.S
+++ b/arch/arm/mm/proc-arm920.S
@@ -379,7 +379,7 @@ ENTRY(cpu_arm920_set_pte_ext)
379 379
380/* Suspend/resume support: taken from arch/arm/plat-s3c24xx/sleep.S */ 380/* Suspend/resume support: taken from arch/arm/plat-s3c24xx/sleep.S */
381.globl cpu_arm920_suspend_size 381.globl cpu_arm920_suspend_size
382.equ cpu_arm920_suspend_size, 4 * 3 382.equ cpu_arm920_suspend_size, 4 * 4
383#ifdef CONFIG_PM_SLEEP 383#ifdef CONFIG_PM_SLEEP
384ENTRY(cpu_arm920_do_suspend) 384ENTRY(cpu_arm920_do_suspend)
385 stmfd sp!, {r4 - r7, lr} 385 stmfd sp!, {r4 - r7, lr}
diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S
index 2bbcf053dffd..cd8f79c3a282 100644
--- a/arch/arm/mm/proc-arm926.S
+++ b/arch/arm/mm/proc-arm926.S
@@ -394,7 +394,7 @@ ENTRY(cpu_arm926_set_pte_ext)
394 394
395/* Suspend/resume support: taken from arch/arm/plat-s3c24xx/sleep.S */ 395/* Suspend/resume support: taken from arch/arm/plat-s3c24xx/sleep.S */
396.globl cpu_arm926_suspend_size 396.globl cpu_arm926_suspend_size
397.equ cpu_arm926_suspend_size, 4 * 3 397.equ cpu_arm926_suspend_size, 4 * 4
398#ifdef CONFIG_PM_SLEEP 398#ifdef CONFIG_PM_SLEEP
399ENTRY(cpu_arm926_do_suspend) 399ENTRY(cpu_arm926_do_suspend)
400 stmfd sp!, {r4 - r7, lr} 400 stmfd sp!, {r4 - r7, lr}
diff --git a/arch/arm/mm/proc-sa1100.S b/arch/arm/mm/proc-sa1100.S
index 07219c2ae114..69e7f2ef7384 100644
--- a/arch/arm/mm/proc-sa1100.S
+++ b/arch/arm/mm/proc-sa1100.S
@@ -182,11 +182,11 @@ ENDPROC(cpu_sa1100_do_suspend)
182 182
183ENTRY(cpu_sa1100_do_resume) 183ENTRY(cpu_sa1100_do_resume)
184 ldmia r0, {r4 - r7} @ load cp regs 184 ldmia r0, {r4 - r7} @ load cp regs
185 mov r1, #0 185 mov ip, #0
186 mcr p15, 0, r1, c8, c7, 0 @ flush I+D TLBs 186 mcr p15, 0, ip, c8, c7, 0 @ flush I+D TLBs
187 mcr p15, 0, r1, c7, c7, 0 @ flush I&D cache 187 mcr p15, 0, ip, c7, c7, 0 @ flush I&D cache
188 mcr p15, 0, r1, c9, c0, 0 @ invalidate RB 188 mcr p15, 0, ip, c9, c0, 0 @ invalidate RB
189 mcr p15, 0, r1, c9, c0, 5 @ allow user space to use RB 189 mcr p15, 0, ip, c9, c0, 5 @ allow user space to use RB
190 190
191 mcr p15, 0, r4, c3, c0, 0 @ domain ID 191 mcr p15, 0, r4, c3, c0, 0 @ domain ID
192 mcr p15, 0, r5, c2, c0, 0 @ translation table base addr 192 mcr p15, 0, r5, c2, c0, 0 @ translation table base addr
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 219138d2f158..a923aa0fd00d 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -223,6 +223,22 @@ __v6_setup:
223 mrc p15, 0, r0, c1, c0, 0 @ read control register 223 mrc p15, 0, r0, c1, c0, 0 @ read control register
224 bic r0, r0, r5 @ clear bits them 224 bic r0, r0, r5 @ clear bits them
225 orr r0, r0, r6 @ set them 225 orr r0, r0, r6 @ set them
226#ifdef CONFIG_ARM_ERRATA_364296
227 /*
228 * Workaround for the 364296 ARM1136 r0p2 erratum (possible cache data
229 * corruption with hit-under-miss enabled). The conditional code below
230 * (setting the undocumented bit 31 in the auxiliary control register
231 * and the FI bit in the control register) disables hit-under-miss
232 * without putting the processor into full low interrupt latency mode.
233 */
234 ldr r6, =0x4107b362 @ id for ARM1136 r0p2
235 mrc p15, 0, r5, c0, c0, 0 @ get processor id
236 teq r5, r6 @ check for the faulty core
237 mrceq p15, 0, r5, c1, c0, 1 @ load aux control reg
238 orreq r5, r5, #(1 << 31) @ set the undocumented bit 31
239 mcreq p15, 0, r5, c1, c0, 1 @ write aux control reg
240 orreq r0, r0, #(1 << 21) @ low interrupt latency configuration
241#endif
226 mov pc, lr @ return to head.S:__ret 242 mov pc, lr @ return to head.S:__ret
227 243
228 /* 244 /*
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index a30e78542ccf..9049c0764db2 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -66,6 +66,7 @@ ENDPROC(cpu_v7_proc_fin)
66ENTRY(cpu_v7_reset) 66ENTRY(cpu_v7_reset)
67 mrc p15, 0, r1, c1, c0, 0 @ ctrl register 67 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
68 bic r1, r1, #0x1 @ ...............m 68 bic r1, r1, #0x1 @ ...............m
69 THUMB( bic r1, r1, #1 << 30 ) @ SCTLR.TE (Thumb exceptions)
69 mcr p15, 0, r1, c1, c0, 0 @ disable MMU 70 mcr p15, 0, r1, c1, c0, 0 @ disable MMU
70 isb 71 isb
71 mov pc, r0 72 mov pc, r0
@@ -247,13 +248,16 @@ ENTRY(cpu_v7_do_resume)
247 mcr p15, 0, r7, c2, c0, 0 @ TTB 0 248 mcr p15, 0, r7, c2, c0, 0 @ TTB 0
248 mcr p15, 0, r8, c2, c0, 1 @ TTB 1 249 mcr p15, 0, r8, c2, c0, 1 @ TTB 1
249 mcr p15, 0, ip, c2, c0, 2 @ TTB control register 250 mcr p15, 0, ip, c2, c0, 2 @ TTB control register
250 mcr p15, 0, r10, c1, c0, 1 @ Auxiliary control register 251 mrc p15, 0, r4, c1, c0, 1 @ Read Auxiliary control register
252 teq r4, r10 @ Is it already set?
253 mcrne p15, 0, r10, c1, c0, 1 @ No, so write it
251 mcr p15, 0, r11, c1, c0, 2 @ Co-processor access control 254 mcr p15, 0, r11, c1, c0, 2 @ Co-processor access control
252 ldr r4, =PRRR @ PRRR 255 ldr r4, =PRRR @ PRRR
253 ldr r5, =NMRR @ NMRR 256 ldr r5, =NMRR @ NMRR
254 mcr p15, 0, r4, c10, c2, 0 @ write PRRR 257 mcr p15, 0, r4, c10, c2, 0 @ write PRRR
255 mcr p15, 0, r5, c10, c2, 1 @ write NMRR 258 mcr p15, 0, r5, c10, c2, 1 @ write NMRR
256 isb 259 isb
260 dsb
257 mov r0, r9 @ control register 261 mov r0, r9 @ control register
258 mov r2, r7, lsr #14 @ get TTB0 base 262 mov r2, r7, lsr #14 @ get TTB0 base
259 mov r2, r2, lsl #14 263 mov r2, r2, lsl #14
diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S
index 28c72a2006a1..755e1bf22681 100644
--- a/arch/arm/mm/proc-xsc3.S
+++ b/arch/arm/mm/proc-xsc3.S
@@ -406,7 +406,7 @@ ENTRY(cpu_xsc3_set_pte_ext)
406 .align 406 .align
407 407
408.globl cpu_xsc3_suspend_size 408.globl cpu_xsc3_suspend_size
409.equ cpu_xsc3_suspend_size, 4 * 8 409.equ cpu_xsc3_suspend_size, 4 * 7
410#ifdef CONFIG_PM_SLEEP 410#ifdef CONFIG_PM_SLEEP
411ENTRY(cpu_xsc3_do_suspend) 411ENTRY(cpu_xsc3_do_suspend)
412 stmfd sp!, {r4 - r10, lr} 412 stmfd sp!, {r4 - r10, lr}
@@ -418,12 +418,12 @@ ENTRY(cpu_xsc3_do_suspend)
418 mrc p15, 0, r9, c1, c0, 1 @ auxiliary control reg 418 mrc p15, 0, r9, c1, c0, 1 @ auxiliary control reg
419 mrc p15, 0, r10, c1, c0, 0 @ control reg 419 mrc p15, 0, r10, c1, c0, 0 @ control reg
420 bic r4, r4, #2 @ clear frequency change bit 420 bic r4, r4, #2 @ clear frequency change bit
421 stmia r0, {r1, r4 - r10} @ store v:p offset + cp regs 421 stmia r0, {r4 - r10} @ store cp regs
422 ldmia sp!, {r4 - r10, pc} 422 ldmia sp!, {r4 - r10, pc}
423ENDPROC(cpu_xsc3_do_suspend) 423ENDPROC(cpu_xsc3_do_suspend)
424 424
425ENTRY(cpu_xsc3_do_resume) 425ENTRY(cpu_xsc3_do_resume)
426 ldmia r0, {r1, r4 - r10} @ load v:p offset + cp regs 426 ldmia r0, {r4 - r10} @ load cp regs
427 mov ip, #0 427 mov ip, #0
428 mcr p15, 0, ip, c7, c7, 0 @ invalidate I & D caches, BTB 428 mcr p15, 0, ip, c7, c7, 0 @ invalidate I & D caches, BTB
429 mcr p15, 0, ip, c7, c10, 4 @ drain write (&fill) buffer 429 mcr p15, 0, ip, c7, c10, 4 @ drain write (&fill) buffer
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index 4e3d97890d69..d19703930ef6 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -64,6 +64,8 @@ extern int mx51_clocks_init(unsigned long ckil, unsigned long osc,
64 unsigned long ckih1, unsigned long ckih2); 64 unsigned long ckih1, unsigned long ckih2);
65extern int mx53_clocks_init(unsigned long ckil, unsigned long osc, 65extern int mx53_clocks_init(unsigned long ckil, unsigned long osc,
66 unsigned long ckih1, unsigned long ckih2); 66 unsigned long ckih1, unsigned long ckih2);
67extern int mx51_clocks_init_dt(void);
68extern int mx53_clocks_init_dt(void);
67extern struct platform_device *mxc_register_gpio(char *name, int id, 69extern struct platform_device *mxc_register_gpio(char *name, int id,
68 resource_size_t iobase, resource_size_t iosize, int irq, int irq_high); 70 resource_size_t iobase, resource_size_t iosize, int irq, int irq_high);
69extern int mxc_register_device(struct platform_device *pdev, void *data); 71extern int mxc_register_device(struct platform_device *pdev, void *data);
@@ -72,4 +74,10 @@ extern void mxc_arch_reset_init(void __iomem *);
72extern void mx51_efikamx_reset(void); 74extern void mx51_efikamx_reset(void);
73extern int mx53_revision(void); 75extern int mx53_revision(void);
74extern int mx53_display_revision(void); 76extern int mx53_display_revision(void);
77
78extern void imx51_babbage_common_init(void);
79extern void imx53_ard_common_init(void);
80extern void imx53_evk_common_init(void);
81extern void imx53_qsb_common_init(void);
82extern void imx53_smd_common_init(void);
75#endif 83#endif
diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
index 9a6a53854911..02609eee0562 100644
--- a/arch/arm/plat-omap/omap_device.c
+++ b/arch/arm/plat-omap/omap_device.c
@@ -615,6 +615,9 @@ static int _od_resume_noirq(struct device *dev)
615 615
616 return pm_generic_resume_noirq(dev); 616 return pm_generic_resume_noirq(dev);
617} 617}
618#else
619#define _od_suspend_noirq NULL
620#define _od_resume_noirq NULL
618#endif 621#endif
619 622
620static struct dev_pm_domain omap_device_pm_domain = { 623static struct dev_pm_domain omap_device_pm_domain = {
diff --git a/arch/arm/plat-s5p/clock.c b/arch/arm/plat-s5p/clock.c
index 02af235298e2..5f84a3f13ef9 100644
--- a/arch/arm/plat-s5p/clock.c
+++ b/arch/arm/plat-s5p/clock.c
@@ -192,7 +192,7 @@ unsigned long s5p_spdif_get_rate(struct clk *clk)
192 if (IS_ERR(pclk)) 192 if (IS_ERR(pclk))
193 return -EINVAL; 193 return -EINVAL;
194 194
195 rate = pclk->ops->get_rate(clk); 195 rate = pclk->ops->get_rate(pclk);
196 clk_put(pclk); 196 clk_put(pclk);
197 197
198 return rate; 198 return rate;
diff --git a/arch/arm/plat-s5p/irq-gpioint.c b/arch/arm/plat-s5p/irq-gpioint.c
index 327ab9f662e8..c65eb791d1bb 100644
--- a/arch/arm/plat-s5p/irq-gpioint.c
+++ b/arch/arm/plat-s5p/irq-gpioint.c
@@ -23,6 +23,8 @@
23#include <plat/gpio-core.h> 23#include <plat/gpio-core.h>
24#include <plat/gpio-cfg.h> 24#include <plat/gpio-cfg.h>
25 25
26#include <asm/mach/irq.h>
27
26#define GPIO_BASE(chip) (((unsigned long)(chip)->base) & 0xFFFFF000u) 28#define GPIO_BASE(chip) (((unsigned long)(chip)->base) & 0xFFFFF000u)
27 29
28#define CON_OFFSET 0x700 30#define CON_OFFSET 0x700
@@ -81,6 +83,9 @@ static void s5p_gpioint_handler(unsigned int irq, struct irq_desc *desc)
81 int group, pend_offset, mask_offset; 83 int group, pend_offset, mask_offset;
82 unsigned int pend, mask; 84 unsigned int pend, mask;
83 85
86 struct irq_chip *chip = irq_get_chip(irq);
87 chained_irq_enter(chip, desc);
88
84 for (group = 0; group < bank->nr_groups; group++) { 89 for (group = 0; group < bank->nr_groups; group++) {
85 struct s3c_gpio_chip *chip = bank->chips[group]; 90 struct s3c_gpio_chip *chip = bank->chips[group];
86 if (!chip) 91 if (!chip)
@@ -102,23 +107,25 @@ static void s5p_gpioint_handler(unsigned int irq, struct irq_desc *desc)
102 pend &= ~BIT(offset); 107 pend &= ~BIT(offset);
103 } 108 }
104 } 109 }
110 chained_irq_exit(chip, desc);
105} 111}
106 112
107static __init int s5p_gpioint_add(struct s3c_gpio_chip *chip) 113static __init int s5p_gpioint_add(struct s3c_gpio_chip *chip)
108{ 114{
109 static int used_gpioint_groups = 0; 115 static int used_gpioint_groups = 0;
110 int group = chip->group; 116 int group = chip->group;
111 struct s5p_gpioint_bank *bank = NULL; 117 struct s5p_gpioint_bank *b, *bank = NULL;
112 struct irq_chip_generic *gc; 118 struct irq_chip_generic *gc;
113 struct irq_chip_type *ct; 119 struct irq_chip_type *ct;
114 120
115 if (used_gpioint_groups >= S5P_GPIOINT_GROUP_COUNT) 121 if (used_gpioint_groups >= S5P_GPIOINT_GROUP_COUNT)
116 return -ENOMEM; 122 return -ENOMEM;
117 123
118 list_for_each_entry(bank, &banks, list) { 124 list_for_each_entry(b, &banks, list) {
119 if (group >= bank->start && 125 if (group >= b->start && group < b->start + b->nr_groups) {
120 group < bank->start + bank->nr_groups) 126 bank = b;
121 break; 127 break;
128 }
122 } 129 }
123 if (!bank) 130 if (!bank)
124 return -EINVAL; 131 return -EINVAL;
@@ -156,9 +163,9 @@ static __init int s5p_gpioint_add(struct s3c_gpio_chip *chip)
156 ct->chip.irq_mask = irq_gc_mask_set_bit; 163 ct->chip.irq_mask = irq_gc_mask_set_bit;
157 ct->chip.irq_unmask = irq_gc_mask_clr_bit; 164 ct->chip.irq_unmask = irq_gc_mask_clr_bit;
158 ct->chip.irq_set_type = s5p_gpioint_set_type, 165 ct->chip.irq_set_type = s5p_gpioint_set_type,
159 ct->regs.ack = PEND_OFFSET + REG_OFFSET(chip->group); 166 ct->regs.ack = PEND_OFFSET + REG_OFFSET(group - bank->start);
160 ct->regs.mask = MASK_OFFSET + REG_OFFSET(chip->group); 167 ct->regs.mask = MASK_OFFSET + REG_OFFSET(group - bank->start);
161 ct->regs.type = CON_OFFSET + REG_OFFSET(chip->group); 168 ct->regs.type = CON_OFFSET + REG_OFFSET(group - bank->start);
162 irq_setup_generic_chip(gc, IRQ_MSK(chip->chip.ngpio), 169 irq_setup_generic_chip(gc, IRQ_MSK(chip->chip.ngpio),
163 IRQ_GC_INIT_MASK_CACHE, 170 IRQ_GC_INIT_MASK_CACHE,
164 IRQ_NOREQUEST | IRQ_NOPROBE, 0); 171 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
diff --git a/arch/arm/plat-samsung/clock.c b/arch/arm/plat-samsung/clock.c
index 302c42670bd1..3b4451979d1b 100644
--- a/arch/arm/plat-samsung/clock.c
+++ b/arch/arm/plat-samsung/clock.c
@@ -64,6 +64,17 @@ static LIST_HEAD(clocks);
64 */ 64 */
65DEFINE_SPINLOCK(clocks_lock); 65DEFINE_SPINLOCK(clocks_lock);
66 66
67/* Global watchdog clock used by arch_wtd_reset() callback */
68struct clk *s3c2410_wdtclk;
69static int __init s3c_wdt_reset_init(void)
70{
71 s3c2410_wdtclk = clk_get(NULL, "watchdog");
72 if (IS_ERR(s3c2410_wdtclk))
73 printk(KERN_WARNING "%s: warning: cannot get watchdog clock\n", __func__);
74 return 0;
75}
76arch_initcall(s3c_wdt_reset_init);
77
67/* enable and disable calls for use with the clk struct */ 78/* enable and disable calls for use with the clk struct */
68 79
69static int clk_null_enable(struct clk *clk, int enable) 80static int clk_null_enable(struct clk *clk, int enable)
diff --git a/arch/arm/plat-samsung/include/plat/backlight.h b/arch/arm/plat-samsung/include/plat/backlight.h
index 51d8da846a62..ad530c78fe8c 100644
--- a/arch/arm/plat-samsung/include/plat/backlight.h
+++ b/arch/arm/plat-samsung/include/plat/backlight.h
@@ -20,7 +20,7 @@ struct samsung_bl_gpio_info {
20 int func; 20 int func;
21}; 21};
22 22
23extern void samsung_bl_set(struct samsung_bl_gpio_info *gpio_info, 23extern void __init samsung_bl_set(struct samsung_bl_gpio_info *gpio_info,
24 struct platform_pwm_backlight_data *bl_data); 24 struct platform_pwm_backlight_data *bl_data);
25 25
26#endif /* __ASM_PLAT_BACKLIGHT_H */ 26#endif /* __ASM_PLAT_BACKLIGHT_H */
diff --git a/arch/arm/plat-samsung/include/plat/clock.h b/arch/arm/plat-samsung/include/plat/clock.h
index 87d5b38a86fb..73c66d4d10fa 100644
--- a/arch/arm/plat-samsung/include/plat/clock.h
+++ b/arch/arm/plat-samsung/include/plat/clock.h
@@ -9,6 +9,9 @@
9 * published by the Free Software Foundation. 9 * published by the Free Software Foundation.
10*/ 10*/
11 11
12#ifndef __ASM_PLAT_CLOCK_H
13#define __ASM_PLAT_CLOCK_H __FILE__
14
12#include <linux/spinlock.h> 15#include <linux/spinlock.h>
13#include <linux/clkdev.h> 16#include <linux/clkdev.h>
14 17
@@ -121,3 +124,8 @@ extern int s3c64xx_sclk_ctrl(struct clk *clk, int enable);
121 124
122extern void s3c_pwmclk_init(void); 125extern void s3c_pwmclk_init(void);
123 126
127/* Global watchdog clock used by arch_wtd_reset() callback */
128
129extern struct clk *s3c2410_wdtclk;
130
131#endif /* __ASM_PLAT_CLOCK_H */
diff --git a/arch/arm/plat-samsung/include/plat/watchdog-reset.h b/arch/arm/plat-samsung/include/plat/watchdog-reset.h
index 54b762acb5a0..40dbb2b0ae22 100644
--- a/arch/arm/plat-samsung/include/plat/watchdog-reset.h
+++ b/arch/arm/plat-samsung/include/plat/watchdog-reset.h
@@ -10,6 +10,7 @@
10 * published by the Free Software Foundation. 10 * published by the Free Software Foundation.
11*/ 11*/
12 12
13#include <plat/clock.h>
13#include <plat/regs-watchdog.h> 14#include <plat/regs-watchdog.h>
14#include <mach/map.h> 15#include <mach/map.h>
15 16
@@ -19,17 +20,12 @@
19 20
20static inline void arch_wdt_reset(void) 21static inline void arch_wdt_reset(void)
21{ 22{
22 struct clk *wdtclk;
23
24 printk("arch_reset: attempting watchdog reset\n"); 23 printk("arch_reset: attempting watchdog reset\n");
25 24
26 __raw_writel(0, S3C2410_WTCON); /* disable watchdog, to be safe */ 25 __raw_writel(0, S3C2410_WTCON); /* disable watchdog, to be safe */
27 26
28 wdtclk = clk_get(NULL, "watchdog"); 27 if (s3c2410_wdtclk)
29 if (!IS_ERR(wdtclk)) { 28 clk_enable(s3c2410_wdtclk);
30 clk_enable(wdtclk);
31 } else
32 printk(KERN_WARNING "%s: warning: cannot get watchdog clock\n", __func__);
33 29
34 /* put initial values into count and data */ 30 /* put initial values into count and data */
35 __raw_writel(0x80, S3C2410_WTCNT); 31 __raw_writel(0x80, S3C2410_WTCNT);
diff --git a/arch/arm/plat-samsung/irq-vic-timer.c b/arch/arm/plat-samsung/irq-vic-timer.c
index f714d060370d..51583cd30164 100644
--- a/arch/arm/plat-samsung/irq-vic-timer.c
+++ b/arch/arm/plat-samsung/irq-vic-timer.c
@@ -22,9 +22,14 @@
22#include <plat/irq-vic-timer.h> 22#include <plat/irq-vic-timer.h>
23#include <plat/regs-timer.h> 23#include <plat/regs-timer.h>
24 24
25#include <asm/mach/irq.h>
26
25static void s3c_irq_demux_vic_timer(unsigned int irq, struct irq_desc *desc) 27static void s3c_irq_demux_vic_timer(unsigned int irq, struct irq_desc *desc)
26{ 28{
29 struct irq_chip *chip = irq_get_chip(irq);
30 chained_irq_enter(chip, desc);
27 generic_handle_irq((int)desc->irq_data.handler_data); 31 generic_handle_irq((int)desc->irq_data.handler_data);
32 chained_irq_exit(chip, desc);
28} 33}
29 34
30/* We assume the IRQ_TIMER0..IRQ_TIMER4 range is continuous. */ 35/* We assume the IRQ_TIMER0..IRQ_TIMER4 range is continuous. */
diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types
index fff68d0d521b..62cc8f981171 100644
--- a/arch/arm/tools/mach-types
+++ b/arch/arm/tools/mach-types
@@ -351,7 +351,7 @@ centro MACH_CENTRO CENTRO 1944
351nokia_rx51 MACH_NOKIA_RX51 NOKIA_RX51 1955 351nokia_rx51 MACH_NOKIA_RX51 NOKIA_RX51 1955
352omap_zoom2 MACH_OMAP_ZOOM2 OMAP_ZOOM2 1967 352omap_zoom2 MACH_OMAP_ZOOM2 OMAP_ZOOM2 1967
353cpuat9260 MACH_CPUAT9260 CPUAT9260 1973 353cpuat9260 MACH_CPUAT9260 CPUAT9260 1973
354eukrea_cpuimx27 MACH_CPUIMX27 CPUIMX27 1975 354eukrea_cpuimx27 MACH_EUKREA_CPUIMX27 EUKREA_CPUIMX27 1975
355acs5k MACH_ACS5K ACS5K 1982 355acs5k MACH_ACS5K ACS5K 1982
356snapper_9260 MACH_SNAPPER_9260 SNAPPER_9260 1987 356snapper_9260 MACH_SNAPPER_9260 SNAPPER_9260 1987
357dsm320 MACH_DSM320 DSM320 1988 357dsm320 MACH_DSM320 DSM320 1988
@@ -476,8 +476,8 @@ cns3420vb MACH_CNS3420VB CNS3420VB 2776
476omap4_panda MACH_OMAP4_PANDA OMAP4_PANDA 2791 476omap4_panda MACH_OMAP4_PANDA OMAP4_PANDA 2791
477ti8168evm MACH_TI8168EVM TI8168EVM 2800 477ti8168evm MACH_TI8168EVM TI8168EVM 2800
478teton_bga MACH_TETON_BGA TETON_BGA 2816 478teton_bga MACH_TETON_BGA TETON_BGA 2816
479eukrea_cpuimx25sd MACH_EUKREA_CPUIMX25 EUKREA_CPUIMX25 2820 479eukrea_cpuimx25sd MACH_EUKREA_CPUIMX25SD EUKREA_CPUIMX25SD 2820
480eukrea_cpuimx35sd MACH_EUKREA_CPUIMX35 EUKREA_CPUIMX35 2821 480eukrea_cpuimx35sd MACH_EUKREA_CPUIMX35SD EUKREA_CPUIMX35SD 2821
481eukrea_cpuimx51sd MACH_EUKREA_CPUIMX51SD EUKREA_CPUIMX51SD 2822 481eukrea_cpuimx51sd MACH_EUKREA_CPUIMX51SD EUKREA_CPUIMX51SD 2822
482eukrea_cpuimx51 MACH_EUKREA_CPUIMX51 EUKREA_CPUIMX51 2823 482eukrea_cpuimx51 MACH_EUKREA_CPUIMX51 EUKREA_CPUIMX51 2823
483smdkc210 MACH_SMDKC210 SMDKC210 2838 483smdkc210 MACH_SMDKC210 SMDKC210 2838