diff options
Diffstat (limited to 'arch/arm')
204 files changed, 26954 insertions, 9137 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index cf8a99f19dc4..233a222752c0 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig | |||
@@ -603,6 +603,7 @@ config ARCH_SA1100 | |||
603 | select ARCH_SPARSEMEM_ENABLE | 603 | select ARCH_SPARSEMEM_ENABLE |
604 | select ARCH_MTD_XIP | 604 | select ARCH_MTD_XIP |
605 | select ARCH_HAS_CPUFREQ | 605 | select ARCH_HAS_CPUFREQ |
606 | select CPU_FREQ | ||
606 | select GENERIC_GPIO | 607 | select GENERIC_GPIO |
607 | select GENERIC_TIME | 608 | select GENERIC_TIME |
608 | select GENERIC_CLOCKEVENTS | 609 | select GENERIC_CLOCKEVENTS |
@@ -1359,13 +1360,9 @@ source "drivers/cpufreq/Kconfig" | |||
1359 | 1360 | ||
1360 | config CPU_FREQ_SA1100 | 1361 | config CPU_FREQ_SA1100 |
1361 | bool | 1362 | bool |
1362 | depends on CPU_FREQ && (SA1100_H3100 || SA1100_H3600 || SA1100_LART || SA1100_PLEB || SA1100_BADGE4 || SA1100_HACKKIT) | ||
1363 | default y | ||
1364 | 1363 | ||
1365 | config CPU_FREQ_SA1110 | 1364 | config CPU_FREQ_SA1110 |
1366 | bool | 1365 | bool |
1367 | depends on CPU_FREQ && (SA1100_ASSABET || SA1100_CERF || SA1100_PT_SYSTEM3) | ||
1368 | default y | ||
1369 | 1366 | ||
1370 | config CPU_FREQ_INTEGRATOR | 1367 | config CPU_FREQ_INTEGRATOR |
1371 | tristate "CPUfreq driver for ARM Integrator CPUs" | 1368 | tristate "CPUfreq driver for ARM Integrator CPUs" |
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index ff54c23d085e..5cb9326df7a7 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug | |||
@@ -71,6 +71,14 @@ config DEBUG_LL | |||
71 | in the kernel. This is helpful if you are debugging code that | 71 | in the kernel. This is helpful if you are debugging code that |
72 | executes before the console is initialized. | 72 | executes before the console is initialized. |
73 | 73 | ||
74 | config EARLY_PRINTK | ||
75 | bool "Early printk" | ||
76 | depends on DEBUG_LL | ||
77 | help | ||
78 | Say Y here if you want to have an early console using the | ||
79 | kernel low-level debugging functions. Add earlyprintk to your | ||
80 | kernel parameters to enable this console. | ||
81 | |||
74 | config DEBUG_ICEDCC | 82 | config DEBUG_ICEDCC |
75 | bool "Kernel low-level debugging via EmbeddedICE DCC channel" | 83 | bool "Kernel low-level debugging via EmbeddedICE DCC channel" |
76 | depends on DEBUG_LL | 84 | depends on DEBUG_LL |
diff --git a/arch/arm/configs/htcherald_defconfig b/arch/arm/configs/htcherald_defconfig index 338267674075..1b39691b816f 100644 --- a/arch/arm/configs/htcherald_defconfig +++ b/arch/arm/configs/htcherald_defconfig | |||
@@ -1,7 +1,7 @@ | |||
1 | # | 1 | # |
2 | # Automatically generated make config: don't edit | 2 | # Automatically generated make config: don't edit |
3 | # Linux kernel version: 2.6.32-rc6 | 3 | # Linux kernel version: 2.6.32-rc8 |
4 | # Sat Nov 14 10:56:01 2009 | 4 | # Sat Dec 5 12:16:24 2009 |
5 | # | 5 | # |
6 | CONFIG_ARM=y | 6 | CONFIG_ARM=y |
7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y | 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y |
@@ -198,7 +198,9 @@ CONFIG_ARCH_OMAP1=y | |||
198 | # OMAP Feature Selections | 198 | # OMAP Feature Selections |
199 | # | 199 | # |
200 | # CONFIG_OMAP_RESET_CLOCKS is not set | 200 | # CONFIG_OMAP_RESET_CLOCKS is not set |
201 | # CONFIG_OMAP_MUX is not set | 201 | CONFIG_OMAP_MUX=y |
202 | # CONFIG_OMAP_MUX_DEBUG is not set | ||
203 | CONFIG_OMAP_MUX_WARNINGS=y | ||
202 | CONFIG_OMAP_MCBSP=y | 204 | CONFIG_OMAP_MCBSP=y |
203 | # CONFIG_OMAP_MBOX_FWK is not set | 205 | # CONFIG_OMAP_MBOX_FWK is not set |
204 | CONFIG_OMAP_MPU_TIMER=y | 206 | CONFIG_OMAP_MPU_TIMER=y |
@@ -207,6 +209,7 @@ CONFIG_OMAP_LL_DEBUG_UART1=y | |||
207 | # CONFIG_OMAP_LL_DEBUG_UART2 is not set | 209 | # CONFIG_OMAP_LL_DEBUG_UART2 is not set |
208 | # CONFIG_OMAP_LL_DEBUG_UART3 is not set | 210 | # CONFIG_OMAP_LL_DEBUG_UART3 is not set |
209 | # CONFIG_OMAP_LL_DEBUG_NONE is not set | 211 | # CONFIG_OMAP_LL_DEBUG_NONE is not set |
212 | CONFIG_OMAP_SERIAL_WAKE=y | ||
210 | # CONFIG_OMAP_PM_NONE is not set | 213 | # CONFIG_OMAP_PM_NONE is not set |
211 | CONFIG_OMAP_PM_NOOP=y | 214 | CONFIG_OMAP_PM_NOOP=y |
212 | 215 | ||
diff --git a/arch/arm/configs/omap3_touchbook_defconfig b/arch/arm/configs/omap3_touchbook_defconfig new file mode 100644 index 000000000000..7c8515e65c02 --- /dev/null +++ b/arch/arm/configs/omap3_touchbook_defconfig | |||
@@ -0,0 +1,2431 @@ | |||
1 | # | ||
2 | # Automatically generated make config: don't edit | ||
3 | # Linux kernel version: 2.6.32-rc8 | ||
4 | # Fri Dec 4 16:02:17 2009 | ||
5 | # | ||
6 | CONFIG_ARM=y | ||
7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y | ||
8 | CONFIG_GENERIC_GPIO=y | ||
9 | CONFIG_GENERIC_TIME=y | ||
10 | CONFIG_GENERIC_CLOCKEVENTS=y | ||
11 | CONFIG_GENERIC_HARDIRQS=y | ||
12 | CONFIG_STACKTRACE_SUPPORT=y | ||
13 | CONFIG_HAVE_LATENCYTOP_SUPPORT=y | ||
14 | CONFIG_LOCKDEP_SUPPORT=y | ||
15 | CONFIG_TRACE_IRQFLAGS_SUPPORT=y | ||
16 | CONFIG_HARDIRQS_SW_RESEND=y | ||
17 | CONFIG_GENERIC_IRQ_PROBE=y | ||
18 | CONFIG_RWSEM_GENERIC_SPINLOCK=y | ||
19 | CONFIG_ARCH_HAS_CPUFREQ=y | ||
20 | CONFIG_GENERIC_HWEIGHT=y | ||
21 | CONFIG_GENERIC_CALIBRATE_DELAY=y | ||
22 | CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y | ||
23 | CONFIG_OPROFILE_ARMV7=y | ||
24 | CONFIG_VECTORS_BASE=0xffff0000 | ||
25 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | ||
26 | CONFIG_CONSTRUCTORS=y | ||
27 | |||
28 | # | ||
29 | # General setup | ||
30 | # | ||
31 | CONFIG_EXPERIMENTAL=y | ||
32 | CONFIG_BROKEN_ON_SMP=y | ||
33 | CONFIG_LOCK_KERNEL=y | ||
34 | CONFIG_INIT_ENV_ARG_LIMIT=32 | ||
35 | CONFIG_LOCALVERSION="" | ||
36 | # CONFIG_LOCALVERSION_AUTO is not set | ||
37 | CONFIG_SWAP=y | ||
38 | CONFIG_SYSVIPC=y | ||
39 | CONFIG_SYSVIPC_SYSCTL=y | ||
40 | # CONFIG_POSIX_MQUEUE is not set | ||
41 | CONFIG_BSD_PROCESS_ACCT=y | ||
42 | # CONFIG_BSD_PROCESS_ACCT_V3 is not set | ||
43 | CONFIG_TASKSTATS=y | ||
44 | CONFIG_TASK_DELAY_ACCT=y | ||
45 | CONFIG_TASK_XACCT=y | ||
46 | CONFIG_TASK_IO_ACCOUNTING=y | ||
47 | # CONFIG_AUDIT is not set | ||
48 | |||
49 | # | ||
50 | # RCU Subsystem | ||
51 | # | ||
52 | CONFIG_TREE_RCU=y | ||
53 | # CONFIG_TREE_PREEMPT_RCU is not set | ||
54 | # CONFIG_RCU_TRACE is not set | ||
55 | CONFIG_RCU_FANOUT=32 | ||
56 | # CONFIG_RCU_FANOUT_EXACT is not set | ||
57 | # CONFIG_TREE_RCU_TRACE is not set | ||
58 | CONFIG_IKCONFIG=y | ||
59 | CONFIG_IKCONFIG_PROC=y | ||
60 | CONFIG_LOG_BUF_SHIFT=15 | ||
61 | CONFIG_GROUP_SCHED=y | ||
62 | CONFIG_FAIR_GROUP_SCHED=y | ||
63 | # CONFIG_RT_GROUP_SCHED is not set | ||
64 | CONFIG_USER_SCHED=y | ||
65 | # CONFIG_CGROUP_SCHED is not set | ||
66 | # CONFIG_CGROUPS is not set | ||
67 | # CONFIG_SYSFS_DEPRECATED_V2 is not set | ||
68 | # CONFIG_RELAY is not set | ||
69 | # CONFIG_NAMESPACES is not set | ||
70 | CONFIG_BLK_DEV_INITRD=y | ||
71 | CONFIG_INITRAMFS_SOURCE="" | ||
72 | CONFIG_RD_GZIP=y | ||
73 | # CONFIG_RD_BZIP2 is not set | ||
74 | # CONFIG_RD_LZMA is not set | ||
75 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y | ||
76 | CONFIG_SYSCTL=y | ||
77 | CONFIG_ANON_INODES=y | ||
78 | CONFIG_EMBEDDED=y | ||
79 | CONFIG_UID16=y | ||
80 | # CONFIG_SYSCTL_SYSCALL is not set | ||
81 | CONFIG_KALLSYMS=y | ||
82 | # CONFIG_KALLSYMS_ALL is not set | ||
83 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | ||
84 | CONFIG_HOTPLUG=y | ||
85 | CONFIG_PRINTK=y | ||
86 | CONFIG_BUG=y | ||
87 | # CONFIG_ELF_CORE is not set | ||
88 | CONFIG_BASE_FULL=y | ||
89 | CONFIG_FUTEX=y | ||
90 | CONFIG_EPOLL=y | ||
91 | CONFIG_SIGNALFD=y | ||
92 | CONFIG_TIMERFD=y | ||
93 | CONFIG_EVENTFD=y | ||
94 | CONFIG_SHMEM=y | ||
95 | CONFIG_AIO=y | ||
96 | |||
97 | # | ||
98 | # Kernel Performance Events And Counters | ||
99 | # | ||
100 | CONFIG_VM_EVENT_COUNTERS=y | ||
101 | # CONFIG_COMPAT_BRK is not set | ||
102 | CONFIG_SLAB=y | ||
103 | # CONFIG_SLUB is not set | ||
104 | # CONFIG_SLOB is not set | ||
105 | CONFIG_PROFILING=y | ||
106 | CONFIG_TRACEPOINTS=y | ||
107 | CONFIG_OPROFILE=y | ||
108 | CONFIG_HAVE_OPROFILE=y | ||
109 | # CONFIG_KPROBES is not set | ||
110 | CONFIG_HAVE_KPROBES=y | ||
111 | CONFIG_HAVE_KRETPROBES=y | ||
112 | CONFIG_HAVE_CLK=y | ||
113 | |||
114 | # | ||
115 | # GCOV-based kernel profiling | ||
116 | # | ||
117 | # CONFIG_GCOV_KERNEL is not set | ||
118 | CONFIG_SLOW_WORK=y | ||
119 | CONFIG_HAVE_GENERIC_DMA_COHERENT=y | ||
120 | CONFIG_SLABINFO=y | ||
121 | CONFIG_RT_MUTEXES=y | ||
122 | CONFIG_BASE_SMALL=0 | ||
123 | CONFIG_MODULES=y | ||
124 | CONFIG_MODULE_FORCE_LOAD=y | ||
125 | CONFIG_MODULE_UNLOAD=y | ||
126 | CONFIG_MODULE_FORCE_UNLOAD=y | ||
127 | CONFIG_MODVERSIONS=y | ||
128 | CONFIG_MODULE_SRCVERSION_ALL=y | ||
129 | CONFIG_BLOCK=y | ||
130 | CONFIG_LBDAF=y | ||
131 | # CONFIG_BLK_DEV_BSG is not set | ||
132 | # CONFIG_BLK_DEV_INTEGRITY is not set | ||
133 | |||
134 | # | ||
135 | # IO Schedulers | ||
136 | # | ||
137 | CONFIG_IOSCHED_NOOP=y | ||
138 | CONFIG_IOSCHED_AS=y | ||
139 | CONFIG_IOSCHED_DEADLINE=y | ||
140 | CONFIG_IOSCHED_CFQ=y | ||
141 | # CONFIG_DEFAULT_AS is not set | ||
142 | # CONFIG_DEFAULT_DEADLINE is not set | ||
143 | CONFIG_DEFAULT_CFQ=y | ||
144 | # CONFIG_DEFAULT_NOOP is not set | ||
145 | CONFIG_DEFAULT_IOSCHED="cfq" | ||
146 | CONFIG_FREEZER=y | ||
147 | |||
148 | # | ||
149 | # System Type | ||
150 | # | ||
151 | CONFIG_MMU=y | ||
152 | # CONFIG_ARCH_AAEC2000 is not set | ||
153 | # CONFIG_ARCH_INTEGRATOR is not set | ||
154 | # CONFIG_ARCH_REALVIEW is not set | ||
155 | # CONFIG_ARCH_VERSATILE is not set | ||
156 | # CONFIG_ARCH_AT91 is not set | ||
157 | # CONFIG_ARCH_CLPS711X is not set | ||
158 | # CONFIG_ARCH_GEMINI is not set | ||
159 | # CONFIG_ARCH_EBSA110 is not set | ||
160 | # CONFIG_ARCH_EP93XX is not set | ||
161 | # CONFIG_ARCH_FOOTBRIDGE is not set | ||
162 | # CONFIG_ARCH_MXC is not set | ||
163 | # CONFIG_ARCH_STMP3XXX is not set | ||
164 | # CONFIG_ARCH_NETX is not set | ||
165 | # CONFIG_ARCH_H720X is not set | ||
166 | # CONFIG_ARCH_NOMADIK is not set | ||
167 | # CONFIG_ARCH_IOP13XX is not set | ||
168 | # CONFIG_ARCH_IOP32X is not set | ||
169 | # CONFIG_ARCH_IOP33X is not set | ||
170 | # CONFIG_ARCH_IXP23XX is not set | ||
171 | # CONFIG_ARCH_IXP2000 is not set | ||
172 | # CONFIG_ARCH_IXP4XX is not set | ||
173 | # CONFIG_ARCH_L7200 is not set | ||
174 | # CONFIG_ARCH_KIRKWOOD is not set | ||
175 | # CONFIG_ARCH_LOKI is not set | ||
176 | # CONFIG_ARCH_MV78XX0 is not set | ||
177 | # CONFIG_ARCH_ORION5X is not set | ||
178 | # CONFIG_ARCH_MMP is not set | ||
179 | # CONFIG_ARCH_KS8695 is not set | ||
180 | # CONFIG_ARCH_NS9XXX is not set | ||
181 | # CONFIG_ARCH_W90X900 is not set | ||
182 | # CONFIG_ARCH_PNX4008 is not set | ||
183 | # CONFIG_ARCH_PXA is not set | ||
184 | # CONFIG_ARCH_MSM is not set | ||
185 | # CONFIG_ARCH_RPC is not set | ||
186 | # CONFIG_ARCH_SA1100 is not set | ||
187 | # CONFIG_ARCH_S3C2410 is not set | ||
188 | # CONFIG_ARCH_S3C64XX is not set | ||
189 | # CONFIG_ARCH_S5PC1XX is not set | ||
190 | # CONFIG_ARCH_SHARK is not set | ||
191 | # CONFIG_ARCH_LH7A40X is not set | ||
192 | # CONFIG_ARCH_U300 is not set | ||
193 | # CONFIG_ARCH_DAVINCI is not set | ||
194 | CONFIG_ARCH_OMAP=y | ||
195 | # CONFIG_ARCH_BCMRING is not set | ||
196 | |||
197 | # | ||
198 | # TI OMAP Implementations | ||
199 | # | ||
200 | CONFIG_ARCH_OMAP_OTG=y | ||
201 | # CONFIG_ARCH_OMAP1 is not set | ||
202 | # CONFIG_ARCH_OMAP2 is not set | ||
203 | CONFIG_ARCH_OMAP3=y | ||
204 | # CONFIG_ARCH_OMAP4 is not set | ||
205 | |||
206 | # | ||
207 | # OMAP Feature Selections | ||
208 | # | ||
209 | # CONFIG_OMAP_DEBUG_POWERDOMAIN is not set | ||
210 | # CONFIG_OMAP_DEBUG_CLOCKDOMAIN is not set | ||
211 | CONFIG_OMAP_RESET_CLOCKS=y | ||
212 | # CONFIG_OMAP_MUX is not set | ||
213 | CONFIG_OMAP_MCBSP=y | ||
214 | # CONFIG_OMAP_MBOX_FWK is not set | ||
215 | # CONFIG_OMAP_MPU_TIMER is not set | ||
216 | CONFIG_OMAP_32K_TIMER=y | ||
217 | CONFIG_OMAP_32K_TIMER_HZ=128 | ||
218 | CONFIG_OMAP_DM_TIMER=y | ||
219 | # CONFIG_OMAP_LL_DEBUG_UART1 is not set | ||
220 | # CONFIG_OMAP_LL_DEBUG_UART2 is not set | ||
221 | CONFIG_OMAP_LL_DEBUG_UART3=y | ||
222 | # CONFIG_OMAP_LL_DEBUG_NONE is not set | ||
223 | # CONFIG_OMAP_PM_NONE is not set | ||
224 | CONFIG_OMAP_PM_NOOP=y | ||
225 | CONFIG_ARCH_OMAP34XX=y | ||
226 | CONFIG_ARCH_OMAP3430=y | ||
227 | |||
228 | # | ||
229 | # OMAP Board Type | ||
230 | # | ||
231 | # CONFIG_MACH_OMAP3_BEAGLE is not set | ||
232 | # CONFIG_MACH_OMAP_LDP is not set | ||
233 | # CONFIG_MACH_OVERO is not set | ||
234 | # CONFIG_MACH_OMAP3EVM is not set | ||
235 | # CONFIG_MACH_OMAP3517EVM is not set | ||
236 | # CONFIG_MACH_OMAP3_PANDORA is not set | ||
237 | CONFIG_MACH_OMAP3_TOUCHBOOK=y | ||
238 | # CONFIG_MACH_OMAP_3430SDP is not set | ||
239 | # CONFIG_MACH_NOKIA_RX51 is not set | ||
240 | # CONFIG_MACH_OMAP_ZOOM2 is not set | ||
241 | # CONFIG_MACH_OMAP_ZOOM3 is not set | ||
242 | # CONFIG_MACH_CM_T35 is not set | ||
243 | # CONFIG_MACH_IGEP0020 is not set | ||
244 | # CONFIG_MACH_OMAP_3630SDP is not set | ||
245 | |||
246 | # | ||
247 | # Processor Type | ||
248 | # | ||
249 | CONFIG_CPU_32=y | ||
250 | CONFIG_CPU_32v6K=y | ||
251 | CONFIG_CPU_V7=y | ||
252 | CONFIG_CPU_32v7=y | ||
253 | CONFIG_CPU_ABRT_EV7=y | ||
254 | CONFIG_CPU_PABRT_V7=y | ||
255 | CONFIG_CPU_CACHE_V7=y | ||
256 | CONFIG_CPU_CACHE_VIPT=y | ||
257 | CONFIG_CPU_COPY_V6=y | ||
258 | CONFIG_CPU_TLB_V7=y | ||
259 | CONFIG_CPU_HAS_ASID=y | ||
260 | CONFIG_CPU_CP15=y | ||
261 | CONFIG_CPU_CP15_MMU=y | ||
262 | |||
263 | # | ||
264 | # Processor Features | ||
265 | # | ||
266 | CONFIG_ARM_THUMB=y | ||
267 | CONFIG_ARM_THUMBEE=y | ||
268 | # CONFIG_CPU_ICACHE_DISABLE is not set | ||
269 | # CONFIG_CPU_DCACHE_DISABLE is not set | ||
270 | # CONFIG_CPU_BPREDICT_DISABLE is not set | ||
271 | CONFIG_HAS_TLS_REG=y | ||
272 | CONFIG_ARM_L1_CACHE_SHIFT=6 | ||
273 | # CONFIG_ARM_ERRATA_430973 is not set | ||
274 | # CONFIG_ARM_ERRATA_458693 is not set | ||
275 | # CONFIG_ARM_ERRATA_460075 is not set | ||
276 | CONFIG_COMMON_CLKDEV=y | ||
277 | |||
278 | # | ||
279 | # Bus support | ||
280 | # | ||
281 | # CONFIG_PCI_SYSCALL is not set | ||
282 | # CONFIG_ARCH_SUPPORTS_MSI is not set | ||
283 | # CONFIG_PCCARD is not set | ||
284 | |||
285 | # | ||
286 | # Kernel Features | ||
287 | # | ||
288 | CONFIG_TICK_ONESHOT=y | ||
289 | CONFIG_NO_HZ=y | ||
290 | CONFIG_HIGH_RES_TIMERS=y | ||
291 | CONFIG_GENERIC_CLOCKEVENTS_BUILD=y | ||
292 | CONFIG_VMSPLIT_3G=y | ||
293 | # CONFIG_VMSPLIT_2G is not set | ||
294 | # CONFIG_VMSPLIT_1G is not set | ||
295 | CONFIG_PAGE_OFFSET=0xC0000000 | ||
296 | # CONFIG_PREEMPT_NONE is not set | ||
297 | # CONFIG_PREEMPT_VOLUNTARY is not set | ||
298 | CONFIG_PREEMPT=y | ||
299 | CONFIG_HZ=128 | ||
300 | # CONFIG_THUMB2_KERNEL is not set | ||
301 | CONFIG_AEABI=y | ||
302 | # CONFIG_OABI_COMPAT is not set | ||
303 | # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set | ||
304 | # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set | ||
305 | # CONFIG_HIGHMEM is not set | ||
306 | CONFIG_SELECT_MEMORY_MODEL=y | ||
307 | CONFIG_FLATMEM_MANUAL=y | ||
308 | # CONFIG_DISCONTIGMEM_MANUAL is not set | ||
309 | # CONFIG_SPARSEMEM_MANUAL is not set | ||
310 | CONFIG_FLATMEM=y | ||
311 | CONFIG_FLAT_NODE_MEM_MAP=y | ||
312 | CONFIG_PAGEFLAGS_EXTENDED=y | ||
313 | CONFIG_SPLIT_PTLOCK_CPUS=4 | ||
314 | # CONFIG_PHYS_ADDR_T_64BIT is not set | ||
315 | CONFIG_ZONE_DMA_FLAG=0 | ||
316 | CONFIG_VIRT_TO_BUS=y | ||
317 | CONFIG_HAVE_MLOCK=y | ||
318 | CONFIG_HAVE_MLOCKED_PAGE_BIT=y | ||
319 | # CONFIG_KSM is not set | ||
320 | CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 | ||
321 | CONFIG_LEDS=y | ||
322 | CONFIG_ALIGNMENT_TRAP=y | ||
323 | # CONFIG_UACCESS_WITH_MEMCPY is not set | ||
324 | |||
325 | # | ||
326 | # Boot options | ||
327 | # | ||
328 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
329 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
330 | CONFIG_CMDLINE=" debug " | ||
331 | # CONFIG_XIP_KERNEL is not set | ||
332 | CONFIG_KEXEC=y | ||
333 | CONFIG_ATAGS_PROC=y | ||
334 | |||
335 | # | ||
336 | # CPU Power Management | ||
337 | # | ||
338 | # CONFIG_CPU_FREQ is not set | ||
339 | # CONFIG_CPU_IDLE is not set | ||
340 | |||
341 | # | ||
342 | # Floating point emulation | ||
343 | # | ||
344 | |||
345 | # | ||
346 | # At least one emulation must be selected | ||
347 | # | ||
348 | CONFIG_VFP=y | ||
349 | CONFIG_VFPv3=y | ||
350 | CONFIG_NEON=y | ||
351 | |||
352 | # | ||
353 | # Userspace binary formats | ||
354 | # | ||
355 | CONFIG_BINFMT_ELF=y | ||
356 | CONFIG_HAVE_AOUT=y | ||
357 | CONFIG_BINFMT_AOUT=m | ||
358 | CONFIG_BINFMT_MISC=y | ||
359 | |||
360 | # | ||
361 | # Power management options | ||
362 | # | ||
363 | CONFIG_PM=y | ||
364 | CONFIG_PM_DEBUG=y | ||
365 | # CONFIG_PM_VERBOSE is not set | ||
366 | CONFIG_CAN_PM_TRACE=y | ||
367 | CONFIG_PM_SLEEP=y | ||
368 | CONFIG_SUSPEND=y | ||
369 | # CONFIG_PM_TEST_SUSPEND is not set | ||
370 | CONFIG_SUSPEND_FREEZER=y | ||
371 | # CONFIG_APM_EMULATION is not set | ||
372 | # CONFIG_PM_RUNTIME is not set | ||
373 | CONFIG_ARCH_SUSPEND_POSSIBLE=y | ||
374 | CONFIG_NET=y | ||
375 | |||
376 | # | ||
377 | # Networking options | ||
378 | # | ||
379 | CONFIG_PACKET=y | ||
380 | CONFIG_PACKET_MMAP=y | ||
381 | CONFIG_UNIX=y | ||
382 | CONFIG_XFRM=y | ||
383 | # CONFIG_XFRM_USER is not set | ||
384 | # CONFIG_XFRM_SUB_POLICY is not set | ||
385 | # CONFIG_XFRM_MIGRATE is not set | ||
386 | # CONFIG_XFRM_STATISTICS is not set | ||
387 | CONFIG_XFRM_IPCOMP=m | ||
388 | CONFIG_NET_KEY=y | ||
389 | # CONFIG_NET_KEY_MIGRATE is not set | ||
390 | CONFIG_INET=y | ||
391 | # CONFIG_IP_MULTICAST is not set | ||
392 | # CONFIG_IP_ADVANCED_ROUTER is not set | ||
393 | CONFIG_IP_FIB_HASH=y | ||
394 | CONFIG_IP_PNP=y | ||
395 | CONFIG_IP_PNP_DHCP=y | ||
396 | CONFIG_IP_PNP_BOOTP=y | ||
397 | CONFIG_IP_PNP_RARP=y | ||
398 | CONFIG_NET_IPIP=m | ||
399 | CONFIG_NET_IPGRE=m | ||
400 | # CONFIG_ARPD is not set | ||
401 | # CONFIG_SYN_COOKIES is not set | ||
402 | CONFIG_INET_AH=m | ||
403 | CONFIG_INET_ESP=m | ||
404 | CONFIG_INET_IPCOMP=m | ||
405 | CONFIG_INET_XFRM_TUNNEL=m | ||
406 | CONFIG_INET_TUNNEL=m | ||
407 | CONFIG_INET_XFRM_MODE_TRANSPORT=y | ||
408 | CONFIG_INET_XFRM_MODE_TUNNEL=y | ||
409 | CONFIG_INET_XFRM_MODE_BEET=y | ||
410 | CONFIG_INET_LRO=y | ||
411 | CONFIG_INET_DIAG=m | ||
412 | CONFIG_INET_TCP_DIAG=m | ||
413 | CONFIG_TCP_CONG_ADVANCED=y | ||
414 | CONFIG_TCP_CONG_BIC=m | ||
415 | CONFIG_TCP_CONG_CUBIC=y | ||
416 | CONFIG_TCP_CONG_WESTWOOD=m | ||
417 | CONFIG_TCP_CONG_HTCP=m | ||
418 | CONFIG_TCP_CONG_HSTCP=m | ||
419 | CONFIG_TCP_CONG_HYBLA=m | ||
420 | CONFIG_TCP_CONG_VEGAS=m | ||
421 | CONFIG_TCP_CONG_SCALABLE=m | ||
422 | CONFIG_TCP_CONG_LP=m | ||
423 | CONFIG_TCP_CONG_VENO=m | ||
424 | CONFIG_TCP_CONG_YEAH=m | ||
425 | CONFIG_TCP_CONG_ILLINOIS=m | ||
426 | # CONFIG_DEFAULT_BIC is not set | ||
427 | CONFIG_DEFAULT_CUBIC=y | ||
428 | # CONFIG_DEFAULT_HTCP is not set | ||
429 | # CONFIG_DEFAULT_VEGAS is not set | ||
430 | # CONFIG_DEFAULT_WESTWOOD is not set | ||
431 | # CONFIG_DEFAULT_RENO is not set | ||
432 | CONFIG_DEFAULT_TCP_CONG="cubic" | ||
433 | # CONFIG_TCP_MD5SIG is not set | ||
434 | CONFIG_IPV6=m | ||
435 | # CONFIG_IPV6_PRIVACY is not set | ||
436 | # CONFIG_IPV6_ROUTER_PREF is not set | ||
437 | # CONFIG_IPV6_OPTIMISTIC_DAD is not set | ||
438 | CONFIG_INET6_AH=m | ||
439 | CONFIG_INET6_ESP=m | ||
440 | CONFIG_INET6_IPCOMP=m | ||
441 | CONFIG_IPV6_MIP6=m | ||
442 | CONFIG_INET6_XFRM_TUNNEL=m | ||
443 | CONFIG_INET6_TUNNEL=m | ||
444 | CONFIG_INET6_XFRM_MODE_TRANSPORT=m | ||
445 | CONFIG_INET6_XFRM_MODE_TUNNEL=m | ||
446 | CONFIG_INET6_XFRM_MODE_BEET=m | ||
447 | CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m | ||
448 | CONFIG_IPV6_SIT=m | ||
449 | CONFIG_IPV6_NDISC_NODETYPE=y | ||
450 | CONFIG_IPV6_TUNNEL=m | ||
451 | CONFIG_IPV6_MULTIPLE_TABLES=y | ||
452 | CONFIG_IPV6_SUBTREES=y | ||
453 | CONFIG_IPV6_MROUTE=y | ||
454 | # CONFIG_IPV6_PIMSM_V2 is not set | ||
455 | # CONFIG_NETWORK_SECMARK is not set | ||
456 | CONFIG_NETFILTER=y | ||
457 | # CONFIG_NETFILTER_DEBUG is not set | ||
458 | CONFIG_NETFILTER_ADVANCED=y | ||
459 | CONFIG_BRIDGE_NETFILTER=y | ||
460 | |||
461 | # | ||
462 | # Core Netfilter Configuration | ||
463 | # | ||
464 | CONFIG_NETFILTER_NETLINK=m | ||
465 | CONFIG_NETFILTER_NETLINK_QUEUE=m | ||
466 | CONFIG_NETFILTER_NETLINK_LOG=m | ||
467 | CONFIG_NF_CONNTRACK=m | ||
468 | CONFIG_NF_CT_ACCT=y | ||
469 | CONFIG_NF_CONNTRACK_MARK=y | ||
470 | CONFIG_NF_CONNTRACK_EVENTS=y | ||
471 | CONFIG_NF_CT_PROTO_DCCP=m | ||
472 | CONFIG_NF_CT_PROTO_GRE=m | ||
473 | CONFIG_NF_CT_PROTO_SCTP=m | ||
474 | CONFIG_NF_CT_PROTO_UDPLITE=m | ||
475 | CONFIG_NF_CONNTRACK_AMANDA=m | ||
476 | CONFIG_NF_CONNTRACK_FTP=m | ||
477 | CONFIG_NF_CONNTRACK_H323=m | ||
478 | CONFIG_NF_CONNTRACK_IRC=m | ||
479 | CONFIG_NF_CONNTRACK_NETBIOS_NS=m | ||
480 | CONFIG_NF_CONNTRACK_PPTP=m | ||
481 | CONFIG_NF_CONNTRACK_SANE=m | ||
482 | CONFIG_NF_CONNTRACK_SIP=m | ||
483 | CONFIG_NF_CONNTRACK_TFTP=m | ||
484 | CONFIG_NF_CT_NETLINK=m | ||
485 | # CONFIG_NETFILTER_TPROXY is not set | ||
486 | CONFIG_NETFILTER_XTABLES=m | ||
487 | CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m | ||
488 | CONFIG_NETFILTER_XT_TARGET_CONNMARK=m | ||
489 | # CONFIG_NETFILTER_XT_TARGET_DSCP is not set | ||
490 | CONFIG_NETFILTER_XT_TARGET_HL=m | ||
491 | # CONFIG_NETFILTER_XT_TARGET_LED is not set | ||
492 | CONFIG_NETFILTER_XT_TARGET_MARK=m | ||
493 | CONFIG_NETFILTER_XT_TARGET_NFLOG=m | ||
494 | CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m | ||
495 | # CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set | ||
496 | CONFIG_NETFILTER_XT_TARGET_RATEEST=m | ||
497 | # CONFIG_NETFILTER_XT_TARGET_TRACE is not set | ||
498 | CONFIG_NETFILTER_XT_TARGET_TCPMSS=m | ||
499 | # CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set | ||
500 | # CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set | ||
501 | CONFIG_NETFILTER_XT_MATCH_COMMENT=m | ||
502 | CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m | ||
503 | CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m | ||
504 | CONFIG_NETFILTER_XT_MATCH_CONNMARK=m | ||
505 | CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m | ||
506 | CONFIG_NETFILTER_XT_MATCH_DCCP=m | ||
507 | CONFIG_NETFILTER_XT_MATCH_DSCP=m | ||
508 | CONFIG_NETFILTER_XT_MATCH_ESP=m | ||
509 | CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m | ||
510 | CONFIG_NETFILTER_XT_MATCH_HELPER=m | ||
511 | CONFIG_NETFILTER_XT_MATCH_HL=m | ||
512 | CONFIG_NETFILTER_XT_MATCH_IPRANGE=m | ||
513 | CONFIG_NETFILTER_XT_MATCH_LENGTH=m | ||
514 | CONFIG_NETFILTER_XT_MATCH_LIMIT=m | ||
515 | CONFIG_NETFILTER_XT_MATCH_MAC=m | ||
516 | CONFIG_NETFILTER_XT_MATCH_MARK=m | ||
517 | CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m | ||
518 | CONFIG_NETFILTER_XT_MATCH_OWNER=m | ||
519 | CONFIG_NETFILTER_XT_MATCH_POLICY=m | ||
520 | # CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set | ||
521 | CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m | ||
522 | CONFIG_NETFILTER_XT_MATCH_QUOTA=m | ||
523 | CONFIG_NETFILTER_XT_MATCH_RATEEST=m | ||
524 | CONFIG_NETFILTER_XT_MATCH_REALM=m | ||
525 | CONFIG_NETFILTER_XT_MATCH_RECENT=m | ||
526 | # CONFIG_NETFILTER_XT_MATCH_RECENT_PROC_COMPAT is not set | ||
527 | CONFIG_NETFILTER_XT_MATCH_SCTP=m | ||
528 | CONFIG_NETFILTER_XT_MATCH_STATE=m | ||
529 | CONFIG_NETFILTER_XT_MATCH_STATISTIC=m | ||
530 | CONFIG_NETFILTER_XT_MATCH_STRING=m | ||
531 | CONFIG_NETFILTER_XT_MATCH_TCPMSS=m | ||
532 | CONFIG_NETFILTER_XT_MATCH_TIME=m | ||
533 | CONFIG_NETFILTER_XT_MATCH_U32=m | ||
534 | # CONFIG_NETFILTER_XT_MATCH_OSF is not set | ||
535 | CONFIG_IP_VS=m | ||
536 | CONFIG_IP_VS_IPV6=y | ||
537 | CONFIG_IP_VS_DEBUG=y | ||
538 | CONFIG_IP_VS_TAB_BITS=12 | ||
539 | |||
540 | # | ||
541 | # IPVS transport protocol load balancing support | ||
542 | # | ||
543 | CONFIG_IP_VS_PROTO_TCP=y | ||
544 | CONFIG_IP_VS_PROTO_UDP=y | ||
545 | CONFIG_IP_VS_PROTO_AH_ESP=y | ||
546 | CONFIG_IP_VS_PROTO_ESP=y | ||
547 | CONFIG_IP_VS_PROTO_AH=y | ||
548 | |||
549 | # | ||
550 | # IPVS scheduler | ||
551 | # | ||
552 | CONFIG_IP_VS_RR=m | ||
553 | CONFIG_IP_VS_WRR=m | ||
554 | CONFIG_IP_VS_LC=m | ||
555 | CONFIG_IP_VS_WLC=m | ||
556 | CONFIG_IP_VS_LBLC=m | ||
557 | CONFIG_IP_VS_LBLCR=m | ||
558 | CONFIG_IP_VS_DH=m | ||
559 | CONFIG_IP_VS_SH=m | ||
560 | CONFIG_IP_VS_SED=m | ||
561 | CONFIG_IP_VS_NQ=m | ||
562 | |||
563 | # | ||
564 | # IPVS application helper | ||
565 | # | ||
566 | CONFIG_IP_VS_FTP=m | ||
567 | |||
568 | # | ||
569 | # IP: Netfilter Configuration | ||
570 | # | ||
571 | CONFIG_NF_DEFRAG_IPV4=m | ||
572 | CONFIG_NF_CONNTRACK_IPV4=m | ||
573 | CONFIG_NF_CONNTRACK_PROC_COMPAT=y | ||
574 | CONFIG_IP_NF_QUEUE=m | ||
575 | CONFIG_IP_NF_IPTABLES=m | ||
576 | CONFIG_IP_NF_MATCH_ADDRTYPE=m | ||
577 | CONFIG_IP_NF_MATCH_AH=m | ||
578 | CONFIG_IP_NF_MATCH_ECN=m | ||
579 | CONFIG_IP_NF_MATCH_TTL=m | ||
580 | CONFIG_IP_NF_FILTER=m | ||
581 | CONFIG_IP_NF_TARGET_REJECT=m | ||
582 | CONFIG_IP_NF_TARGET_LOG=m | ||
583 | CONFIG_IP_NF_TARGET_ULOG=m | ||
584 | CONFIG_NF_NAT=m | ||
585 | CONFIG_NF_NAT_NEEDED=y | ||
586 | CONFIG_IP_NF_TARGET_MASQUERADE=m | ||
587 | CONFIG_IP_NF_TARGET_NETMAP=m | ||
588 | CONFIG_IP_NF_TARGET_REDIRECT=m | ||
589 | CONFIG_NF_NAT_SNMP_BASIC=m | ||
590 | CONFIG_NF_NAT_PROTO_DCCP=m | ||
591 | CONFIG_NF_NAT_PROTO_GRE=m | ||
592 | CONFIG_NF_NAT_PROTO_UDPLITE=m | ||
593 | CONFIG_NF_NAT_PROTO_SCTP=m | ||
594 | CONFIG_NF_NAT_FTP=m | ||
595 | CONFIG_NF_NAT_IRC=m | ||
596 | CONFIG_NF_NAT_TFTP=m | ||
597 | CONFIG_NF_NAT_AMANDA=m | ||
598 | CONFIG_NF_NAT_PPTP=m | ||
599 | CONFIG_NF_NAT_H323=m | ||
600 | CONFIG_NF_NAT_SIP=m | ||
601 | CONFIG_IP_NF_MANGLE=m | ||
602 | CONFIG_IP_NF_TARGET_CLUSTERIP=m | ||
603 | CONFIG_IP_NF_TARGET_ECN=m | ||
604 | CONFIG_IP_NF_TARGET_TTL=m | ||
605 | CONFIG_IP_NF_RAW=m | ||
606 | CONFIG_IP_NF_ARPTABLES=m | ||
607 | CONFIG_IP_NF_ARPFILTER=m | ||
608 | CONFIG_IP_NF_ARP_MANGLE=m | ||
609 | |||
610 | # | ||
611 | # IPv6: Netfilter Configuration | ||
612 | # | ||
613 | CONFIG_NF_CONNTRACK_IPV6=m | ||
614 | CONFIG_IP6_NF_QUEUE=m | ||
615 | CONFIG_IP6_NF_IPTABLES=m | ||
616 | CONFIG_IP6_NF_MATCH_AH=m | ||
617 | CONFIG_IP6_NF_MATCH_EUI64=m | ||
618 | CONFIG_IP6_NF_MATCH_FRAG=m | ||
619 | CONFIG_IP6_NF_MATCH_OPTS=m | ||
620 | CONFIG_IP6_NF_MATCH_HL=m | ||
621 | CONFIG_IP6_NF_MATCH_IPV6HEADER=m | ||
622 | CONFIG_IP6_NF_MATCH_MH=m | ||
623 | CONFIG_IP6_NF_MATCH_RT=m | ||
624 | CONFIG_IP6_NF_TARGET_HL=m | ||
625 | CONFIG_IP6_NF_TARGET_LOG=m | ||
626 | CONFIG_IP6_NF_FILTER=m | ||
627 | CONFIG_IP6_NF_TARGET_REJECT=m | ||
628 | CONFIG_IP6_NF_MANGLE=m | ||
629 | CONFIG_IP6_NF_RAW=m | ||
630 | # CONFIG_BRIDGE_NF_EBTABLES is not set | ||
631 | CONFIG_IP_DCCP=m | ||
632 | CONFIG_INET_DCCP_DIAG=m | ||
633 | |||
634 | # | ||
635 | # DCCP CCIDs Configuration (EXPERIMENTAL) | ||
636 | # | ||
637 | # CONFIG_IP_DCCP_CCID2_DEBUG is not set | ||
638 | CONFIG_IP_DCCP_CCID3=y | ||
639 | # CONFIG_IP_DCCP_CCID3_DEBUG is not set | ||
640 | CONFIG_IP_DCCP_CCID3_RTO=100 | ||
641 | CONFIG_IP_DCCP_TFRC_LIB=y | ||
642 | |||
643 | # | ||
644 | # DCCP Kernel Hacking | ||
645 | # | ||
646 | # CONFIG_IP_DCCP_DEBUG is not set | ||
647 | CONFIG_IP_SCTP=m | ||
648 | # CONFIG_SCTP_DBG_MSG is not set | ||
649 | # CONFIG_SCTP_DBG_OBJCNT is not set | ||
650 | # CONFIG_SCTP_HMAC_NONE is not set | ||
651 | # CONFIG_SCTP_HMAC_SHA1 is not set | ||
652 | CONFIG_SCTP_HMAC_MD5=y | ||
653 | # CONFIG_RDS is not set | ||
654 | CONFIG_TIPC=m | ||
655 | # CONFIG_TIPC_ADVANCED is not set | ||
656 | # CONFIG_TIPC_DEBUG is not set | ||
657 | CONFIG_ATM=m | ||
658 | CONFIG_ATM_CLIP=m | ||
659 | # CONFIG_ATM_CLIP_NO_ICMP is not set | ||
660 | CONFIG_ATM_LANE=m | ||
661 | CONFIG_ATM_MPOA=m | ||
662 | CONFIG_ATM_BR2684=m | ||
663 | # CONFIG_ATM_BR2684_IPFILTER is not set | ||
664 | CONFIG_STP=m | ||
665 | CONFIG_GARP=m | ||
666 | CONFIG_BRIDGE=m | ||
667 | # CONFIG_NET_DSA is not set | ||
668 | CONFIG_VLAN_8021Q=m | ||
669 | CONFIG_VLAN_8021Q_GVRP=y | ||
670 | # CONFIG_DECNET is not set | ||
671 | CONFIG_LLC=m | ||
672 | # CONFIG_LLC2 is not set | ||
673 | # CONFIG_IPX is not set | ||
674 | # CONFIG_ATALK is not set | ||
675 | # CONFIG_X25 is not set | ||
676 | # CONFIG_LAPB is not set | ||
677 | # CONFIG_ECONET is not set | ||
678 | CONFIG_WAN_ROUTER=m | ||
679 | # CONFIG_PHONET is not set | ||
680 | # CONFIG_IEEE802154 is not set | ||
681 | CONFIG_NET_SCHED=y | ||
682 | |||
683 | # | ||
684 | # Queueing/Scheduling | ||
685 | # | ||
686 | CONFIG_NET_SCH_CBQ=m | ||
687 | CONFIG_NET_SCH_HTB=m | ||
688 | CONFIG_NET_SCH_HFSC=m | ||
689 | CONFIG_NET_SCH_ATM=m | ||
690 | CONFIG_NET_SCH_PRIO=m | ||
691 | CONFIG_NET_SCH_MULTIQ=m | ||
692 | CONFIG_NET_SCH_RED=m | ||
693 | CONFIG_NET_SCH_SFQ=m | ||
694 | CONFIG_NET_SCH_TEQL=m | ||
695 | CONFIG_NET_SCH_TBF=m | ||
696 | CONFIG_NET_SCH_GRED=m | ||
697 | CONFIG_NET_SCH_DSMARK=m | ||
698 | CONFIG_NET_SCH_NETEM=m | ||
699 | CONFIG_NET_SCH_DRR=m | ||
700 | |||
701 | # | ||
702 | # Classification | ||
703 | # | ||
704 | CONFIG_NET_CLS=y | ||
705 | CONFIG_NET_CLS_BASIC=m | ||
706 | CONFIG_NET_CLS_TCINDEX=m | ||
707 | CONFIG_NET_CLS_ROUTE4=m | ||
708 | CONFIG_NET_CLS_ROUTE=y | ||
709 | CONFIG_NET_CLS_FW=m | ||
710 | CONFIG_NET_CLS_U32=m | ||
711 | CONFIG_CLS_U32_PERF=y | ||
712 | CONFIG_CLS_U32_MARK=y | ||
713 | CONFIG_NET_CLS_RSVP=m | ||
714 | CONFIG_NET_CLS_RSVP6=m | ||
715 | CONFIG_NET_CLS_FLOW=m | ||
716 | # CONFIG_NET_EMATCH is not set | ||
717 | # CONFIG_NET_CLS_ACT is not set | ||
718 | CONFIG_NET_CLS_IND=y | ||
719 | CONFIG_NET_SCH_FIFO=y | ||
720 | # CONFIG_DCB is not set | ||
721 | |||
722 | # | ||
723 | # Network testing | ||
724 | # | ||
725 | # CONFIG_NET_PKTGEN is not set | ||
726 | # CONFIG_NET_DROP_MONITOR is not set | ||
727 | # CONFIG_HAMRADIO is not set | ||
728 | # CONFIG_CAN is not set | ||
729 | # CONFIG_IRDA is not set | ||
730 | CONFIG_BT=y | ||
731 | CONFIG_BT_L2CAP=y | ||
732 | CONFIG_BT_SCO=y | ||
733 | CONFIG_BT_RFCOMM=y | ||
734 | CONFIG_BT_RFCOMM_TTY=y | ||
735 | CONFIG_BT_BNEP=y | ||
736 | CONFIG_BT_BNEP_MC_FILTER=y | ||
737 | CONFIG_BT_BNEP_PROTO_FILTER=y | ||
738 | CONFIG_BT_HIDP=y | ||
739 | |||
740 | # | ||
741 | # Bluetooth device drivers | ||
742 | # | ||
743 | CONFIG_BT_HCIBTUSB=y | ||
744 | CONFIG_BT_HCIBTSDIO=y | ||
745 | CONFIG_BT_HCIUART=y | ||
746 | CONFIG_BT_HCIUART_H4=y | ||
747 | CONFIG_BT_HCIUART_BCSP=y | ||
748 | CONFIG_BT_HCIUART_LL=y | ||
749 | CONFIG_BT_HCIBCM203X=y | ||
750 | CONFIG_BT_HCIBPA10X=y | ||
751 | CONFIG_BT_HCIBFUSB=y | ||
752 | # CONFIG_BT_HCIVHCI is not set | ||
753 | # CONFIG_BT_MRVL is not set | ||
754 | CONFIG_AF_RXRPC=m | ||
755 | # CONFIG_AF_RXRPC_DEBUG is not set | ||
756 | # CONFIG_RXKAD is not set | ||
757 | CONFIG_FIB_RULES=y | ||
758 | CONFIG_WIRELESS=y | ||
759 | CONFIG_CFG80211=m | ||
760 | # CONFIG_NL80211_TESTMODE is not set | ||
761 | # CONFIG_CFG80211_DEVELOPER_WARNINGS is not set | ||
762 | # CONFIG_CFG80211_REG_DEBUG is not set | ||
763 | CONFIG_CFG80211_DEFAULT_PS=y | ||
764 | CONFIG_CFG80211_DEFAULT_PS_VALUE=1 | ||
765 | # CONFIG_CFG80211_DEBUGFS is not set | ||
766 | # CONFIG_WIRELESS_OLD_REGULATORY is not set | ||
767 | CONFIG_WIRELESS_EXT=y | ||
768 | CONFIG_WIRELESS_EXT_SYSFS=y | ||
769 | CONFIG_LIB80211=y | ||
770 | # CONFIG_LIB80211_DEBUG is not set | ||
771 | CONFIG_MAC80211=m | ||
772 | CONFIG_MAC80211_RC_PID=y | ||
773 | # CONFIG_MAC80211_RC_MINSTREL is not set | ||
774 | CONFIG_MAC80211_RC_DEFAULT_PID=y | ||
775 | # CONFIG_MAC80211_RC_DEFAULT_MINSTREL is not set | ||
776 | CONFIG_MAC80211_RC_DEFAULT="pid" | ||
777 | # CONFIG_MAC80211_MESH is not set | ||
778 | # CONFIG_MAC80211_LEDS is not set | ||
779 | # CONFIG_MAC80211_DEBUGFS is not set | ||
780 | # CONFIG_MAC80211_DEBUG_MENU is not set | ||
781 | CONFIG_WIMAX=m | ||
782 | CONFIG_WIMAX_DEBUG_LEVEL=8 | ||
783 | # CONFIG_RFKILL is not set | ||
784 | # CONFIG_NET_9P is not set | ||
785 | |||
786 | # | ||
787 | # Device Drivers | ||
788 | # | ||
789 | |||
790 | # | ||
791 | # Generic Driver Options | ||
792 | # | ||
793 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
794 | # CONFIG_DEVTMPFS is not set | ||
795 | CONFIG_STANDALONE=y | ||
796 | CONFIG_PREVENT_FIRMWARE_BUILD=y | ||
797 | CONFIG_FW_LOADER=y | ||
798 | CONFIG_FIRMWARE_IN_KERNEL=y | ||
799 | CONFIG_EXTRA_FIRMWARE="" | ||
800 | # CONFIG_DEBUG_DRIVER is not set | ||
801 | # CONFIG_DEBUG_DEVRES is not set | ||
802 | # CONFIG_SYS_HYPERVISOR is not set | ||
803 | # CONFIG_CONNECTOR is not set | ||
804 | CONFIG_MTD=y | ||
805 | # CONFIG_MTD_DEBUG is not set | ||
806 | # CONFIG_MTD_TESTS is not set | ||
807 | CONFIG_MTD_CONCAT=y | ||
808 | CONFIG_MTD_PARTITIONS=y | ||
809 | # CONFIG_MTD_REDBOOT_PARTS is not set | ||
810 | # CONFIG_MTD_CMDLINE_PARTS is not set | ||
811 | # CONFIG_MTD_AFS_PARTS is not set | ||
812 | # CONFIG_MTD_AR7_PARTS is not set | ||
813 | |||
814 | # | ||
815 | # User Modules And Translation Layers | ||
816 | # | ||
817 | CONFIG_MTD_CHAR=y | ||
818 | CONFIG_MTD_BLKDEVS=y | ||
819 | CONFIG_MTD_BLOCK=y | ||
820 | # CONFIG_FTL is not set | ||
821 | # CONFIG_NFTL is not set | ||
822 | # CONFIG_INFTL is not set | ||
823 | # CONFIG_RFD_FTL is not set | ||
824 | # CONFIG_SSFDC is not set | ||
825 | # CONFIG_MTD_OOPS is not set | ||
826 | |||
827 | # | ||
828 | # RAM/ROM/Flash chip drivers | ||
829 | # | ||
830 | # CONFIG_MTD_CFI is not set | ||
831 | # CONFIG_MTD_JEDECPROBE is not set | ||
832 | CONFIG_MTD_MAP_BANK_WIDTH_1=y | ||
833 | CONFIG_MTD_MAP_BANK_WIDTH_2=y | ||
834 | CONFIG_MTD_MAP_BANK_WIDTH_4=y | ||
835 | # CONFIG_MTD_MAP_BANK_WIDTH_8 is not set | ||
836 | # CONFIG_MTD_MAP_BANK_WIDTH_16 is not set | ||
837 | # CONFIG_MTD_MAP_BANK_WIDTH_32 is not set | ||
838 | CONFIG_MTD_CFI_I1=y | ||
839 | CONFIG_MTD_CFI_I2=y | ||
840 | # CONFIG_MTD_CFI_I4 is not set | ||
841 | # CONFIG_MTD_CFI_I8 is not set | ||
842 | # CONFIG_MTD_RAM is not set | ||
843 | # CONFIG_MTD_ROM is not set | ||
844 | # CONFIG_MTD_ABSENT is not set | ||
845 | |||
846 | # | ||
847 | # Mapping drivers for chip access | ||
848 | # | ||
849 | # CONFIG_MTD_COMPLEX_MAPPINGS is not set | ||
850 | # CONFIG_MTD_PLATRAM is not set | ||
851 | |||
852 | # | ||
853 | # Self-contained MTD device drivers | ||
854 | # | ||
855 | # CONFIG_MTD_DATAFLASH is not set | ||
856 | # CONFIG_MTD_M25P80 is not set | ||
857 | # CONFIG_MTD_SST25L is not set | ||
858 | # CONFIG_MTD_SLRAM is not set | ||
859 | # CONFIG_MTD_PHRAM is not set | ||
860 | # CONFIG_MTD_MTDRAM is not set | ||
861 | # CONFIG_MTD_BLOCK2MTD is not set | ||
862 | |||
863 | # | ||
864 | # Disk-On-Chip Device Drivers | ||
865 | # | ||
866 | # CONFIG_MTD_DOC2000 is not set | ||
867 | # CONFIG_MTD_DOC2001 is not set | ||
868 | # CONFIG_MTD_DOC2001PLUS is not set | ||
869 | CONFIG_MTD_NAND=y | ||
870 | # CONFIG_MTD_NAND_VERIFY_WRITE is not set | ||
871 | # CONFIG_MTD_NAND_ECC_SMC is not set | ||
872 | # CONFIG_MTD_NAND_MUSEUM_IDS is not set | ||
873 | # CONFIG_MTD_NAND_GPIO is not set | ||
874 | CONFIG_MTD_NAND_OMAP2=y | ||
875 | CONFIG_MTD_NAND_OMAP_PREFETCH=y | ||
876 | # CONFIG_MTD_NAND_OMAP_PREFETCH_DMA is not set | ||
877 | CONFIG_MTD_NAND_IDS=y | ||
878 | # CONFIG_MTD_NAND_DISKONCHIP is not set | ||
879 | # CONFIG_MTD_NAND_NANDSIM is not set | ||
880 | CONFIG_MTD_NAND_PLATFORM=y | ||
881 | # CONFIG_MTD_ALAUDA is not set | ||
882 | # CONFIG_MTD_ONENAND is not set | ||
883 | |||
884 | # | ||
885 | # LPDDR flash memory drivers | ||
886 | # | ||
887 | # CONFIG_MTD_LPDDR is not set | ||
888 | |||
889 | # | ||
890 | # UBI - Unsorted block images | ||
891 | # | ||
892 | CONFIG_MTD_UBI=y | ||
893 | CONFIG_MTD_UBI_WL_THRESHOLD=4096 | ||
894 | CONFIG_MTD_UBI_BEB_RESERVE=1 | ||
895 | # CONFIG_MTD_UBI_GLUEBI is not set | ||
896 | |||
897 | # | ||
898 | # UBI debugging options | ||
899 | # | ||
900 | # CONFIG_MTD_UBI_DEBUG is not set | ||
901 | # CONFIG_PARPORT is not set | ||
902 | CONFIG_BLK_DEV=y | ||
903 | # CONFIG_BLK_DEV_COW_COMMON is not set | ||
904 | CONFIG_BLK_DEV_LOOP=y | ||
905 | CONFIG_BLK_DEV_CRYPTOLOOP=m | ||
906 | # CONFIG_BLK_DEV_NBD is not set | ||
907 | # CONFIG_BLK_DEV_UB is not set | ||
908 | CONFIG_BLK_DEV_RAM=y | ||
909 | CONFIG_BLK_DEV_RAM_COUNT=16 | ||
910 | CONFIG_BLK_DEV_RAM_SIZE=16384 | ||
911 | # CONFIG_BLK_DEV_XIP is not set | ||
912 | CONFIG_CDROM_PKTCDVD=m | ||
913 | CONFIG_CDROM_PKTCDVD_BUFFERS=8 | ||
914 | # CONFIG_CDROM_PKTCDVD_WCACHE is not set | ||
915 | # CONFIG_ATA_OVER_ETH is not set | ||
916 | # CONFIG_MG_DISK is not set | ||
917 | CONFIG_MISC_DEVICES=y | ||
918 | # CONFIG_ICS932S401 is not set | ||
919 | # CONFIG_ENCLOSURE_SERVICES is not set | ||
920 | # CONFIG_ISL29003 is not set | ||
921 | # CONFIG_C2PORT is not set | ||
922 | |||
923 | # | ||
924 | # EEPROM support | ||
925 | # | ||
926 | # CONFIG_EEPROM_AT24 is not set | ||
927 | # CONFIG_EEPROM_AT25 is not set | ||
928 | # CONFIG_EEPROM_LEGACY is not set | ||
929 | # CONFIG_EEPROM_MAX6875 is not set | ||
930 | CONFIG_EEPROM_93CX6=y | ||
931 | CONFIG_HAVE_IDE=y | ||
932 | # CONFIG_IDE is not set | ||
933 | |||
934 | # | ||
935 | # SCSI device support | ||
936 | # | ||
937 | CONFIG_RAID_ATTRS=m | ||
938 | CONFIG_SCSI=y | ||
939 | CONFIG_SCSI_DMA=y | ||
940 | # CONFIG_SCSI_TGT is not set | ||
941 | # CONFIG_SCSI_NETLINK is not set | ||
942 | CONFIG_SCSI_PROC_FS=y | ||
943 | |||
944 | # | ||
945 | # SCSI support type (disk, tape, CD-ROM) | ||
946 | # | ||
947 | CONFIG_BLK_DEV_SD=y | ||
948 | # CONFIG_CHR_DEV_ST is not set | ||
949 | # CONFIG_CHR_DEV_OSST is not set | ||
950 | CONFIG_BLK_DEV_SR=y | ||
951 | CONFIG_BLK_DEV_SR_VENDOR=y | ||
952 | CONFIG_CHR_DEV_SG=y | ||
953 | CONFIG_CHR_DEV_SCH=m | ||
954 | CONFIG_SCSI_MULTI_LUN=y | ||
955 | # CONFIG_SCSI_CONSTANTS is not set | ||
956 | # CONFIG_SCSI_LOGGING is not set | ||
957 | # CONFIG_SCSI_SCAN_ASYNC is not set | ||
958 | CONFIG_SCSI_WAIT_SCAN=m | ||
959 | |||
960 | # | ||
961 | # SCSI Transports | ||
962 | # | ||
963 | # CONFIG_SCSI_SPI_ATTRS is not set | ||
964 | # CONFIG_SCSI_FC_ATTRS is not set | ||
965 | CONFIG_SCSI_ISCSI_ATTRS=m | ||
966 | # CONFIG_SCSI_SAS_LIBSAS is not set | ||
967 | # CONFIG_SCSI_SRP_ATTRS is not set | ||
968 | CONFIG_SCSI_LOWLEVEL=y | ||
969 | CONFIG_ISCSI_TCP=m | ||
970 | # CONFIG_LIBFC is not set | ||
971 | # CONFIG_LIBFCOE is not set | ||
972 | # CONFIG_SCSI_DEBUG is not set | ||
973 | # CONFIG_SCSI_DH is not set | ||
974 | # CONFIG_SCSI_OSD_INITIATOR is not set | ||
975 | # CONFIG_ATA is not set | ||
976 | CONFIG_MD=y | ||
977 | CONFIG_BLK_DEV_MD=m | ||
978 | CONFIG_MD_LINEAR=m | ||
979 | CONFIG_MD_RAID0=m | ||
980 | CONFIG_MD_RAID1=m | ||
981 | CONFIG_MD_RAID10=m | ||
982 | CONFIG_MD_RAID456=m | ||
983 | CONFIG_MD_RAID6_PQ=m | ||
984 | # CONFIG_ASYNC_RAID6_TEST is not set | ||
985 | CONFIG_MD_MULTIPATH=m | ||
986 | CONFIG_MD_FAULTY=m | ||
987 | CONFIG_BLK_DEV_DM=m | ||
988 | # CONFIG_DM_DEBUG is not set | ||
989 | CONFIG_DM_CRYPT=m | ||
990 | CONFIG_DM_SNAPSHOT=m | ||
991 | CONFIG_DM_MIRROR=m | ||
992 | # CONFIG_DM_LOG_USERSPACE is not set | ||
993 | CONFIG_DM_ZERO=m | ||
994 | CONFIG_DM_MULTIPATH=m | ||
995 | # CONFIG_DM_MULTIPATH_QL is not set | ||
996 | # CONFIG_DM_MULTIPATH_ST is not set | ||
997 | CONFIG_DM_DELAY=m | ||
998 | # CONFIG_DM_UEVENT is not set | ||
999 | CONFIG_NETDEVICES=y | ||
1000 | CONFIG_DUMMY=m | ||
1001 | CONFIG_BONDING=m | ||
1002 | CONFIG_MACVLAN=m | ||
1003 | CONFIG_EQUALIZER=m | ||
1004 | CONFIG_TUN=m | ||
1005 | CONFIG_VETH=m | ||
1006 | # CONFIG_NET_ETHERNET is not set | ||
1007 | # CONFIG_NETDEV_1000 is not set | ||
1008 | # CONFIG_NETDEV_10000 is not set | ||
1009 | CONFIG_WLAN=y | ||
1010 | # CONFIG_WLAN_PRE80211 is not set | ||
1011 | CONFIG_WLAN_80211=y | ||
1012 | # CONFIG_LIBERTAS is not set | ||
1013 | # CONFIG_LIBERTAS_THINFIRM is not set | ||
1014 | # CONFIG_AT76C50X_USB is not set | ||
1015 | # CONFIG_USB_ZD1201 is not set | ||
1016 | # CONFIG_USB_NET_RNDIS_WLAN is not set | ||
1017 | # CONFIG_RTL8187 is not set | ||
1018 | # CONFIG_MAC80211_HWSIM is not set | ||
1019 | # CONFIG_P54_COMMON is not set | ||
1020 | # CONFIG_ATH_COMMON is not set | ||
1021 | # CONFIG_HOSTAP is not set | ||
1022 | # CONFIG_B43 is not set | ||
1023 | # CONFIG_B43LEGACY is not set | ||
1024 | # CONFIG_ZD1211RW is not set | ||
1025 | # CONFIG_RT2X00 is not set | ||
1026 | # CONFIG_WL12XX is not set | ||
1027 | # CONFIG_IWM is not set | ||
1028 | |||
1029 | # | ||
1030 | # WiMAX Wireless Broadband devices | ||
1031 | # | ||
1032 | # CONFIG_WIMAX_I2400M_USB is not set | ||
1033 | # CONFIG_WIMAX_I2400M_SDIO is not set | ||
1034 | |||
1035 | # | ||
1036 | # USB Network Adapters | ||
1037 | # | ||
1038 | # CONFIG_USB_CATC is not set | ||
1039 | # CONFIG_USB_KAWETH is not set | ||
1040 | # CONFIG_USB_PEGASUS is not set | ||
1041 | # CONFIG_USB_RTL8150 is not set | ||
1042 | # CONFIG_USB_USBNET is not set | ||
1043 | # CONFIG_WAN is not set | ||
1044 | # CONFIG_ATM_DRIVERS is not set | ||
1045 | CONFIG_PPP=m | ||
1046 | CONFIG_PPP_MULTILINK=y | ||
1047 | CONFIG_PPP_FILTER=y | ||
1048 | CONFIG_PPP_ASYNC=m | ||
1049 | CONFIG_PPP_SYNC_TTY=m | ||
1050 | CONFIG_PPP_DEFLATE=m | ||
1051 | CONFIG_PPP_BSDCOMP=m | ||
1052 | CONFIG_PPP_MPPE=m | ||
1053 | CONFIG_PPPOE=m | ||
1054 | # CONFIG_PPPOATM is not set | ||
1055 | CONFIG_PPPOL2TP=m | ||
1056 | # CONFIG_SLIP is not set | ||
1057 | CONFIG_SLHC=m | ||
1058 | CONFIG_NETCONSOLE=m | ||
1059 | CONFIG_NETCONSOLE_DYNAMIC=y | ||
1060 | CONFIG_NETPOLL=y | ||
1061 | CONFIG_NETPOLL_TRAP=y | ||
1062 | CONFIG_NET_POLL_CONTROLLER=y | ||
1063 | # CONFIG_ISDN is not set | ||
1064 | # CONFIG_PHONE is not set | ||
1065 | |||
1066 | # | ||
1067 | # Input device support | ||
1068 | # | ||
1069 | CONFIG_INPUT=y | ||
1070 | CONFIG_INPUT_FF_MEMLESS=y | ||
1071 | # CONFIG_INPUT_POLLDEV is not set | ||
1072 | |||
1073 | # | ||
1074 | # Userland interfaces | ||
1075 | # | ||
1076 | CONFIG_INPUT_MOUSEDEV=y | ||
1077 | CONFIG_INPUT_MOUSEDEV_PSAUX=y | ||
1078 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 | ||
1079 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 | ||
1080 | # CONFIG_INPUT_JOYDEV is not set | ||
1081 | CONFIG_INPUT_EVDEV=y | ||
1082 | # CONFIG_INPUT_EVBUG is not set | ||
1083 | |||
1084 | # | ||
1085 | # Input Device Drivers | ||
1086 | # | ||
1087 | CONFIG_INPUT_KEYBOARD=y | ||
1088 | # CONFIG_KEYBOARD_ADP5588 is not set | ||
1089 | # CONFIG_KEYBOARD_ATKBD is not set | ||
1090 | # CONFIG_QT2160 is not set | ||
1091 | # CONFIG_KEYBOARD_LKKBD is not set | ||
1092 | CONFIG_KEYBOARD_GPIO=y | ||
1093 | # CONFIG_KEYBOARD_MATRIX is not set | ||
1094 | # CONFIG_KEYBOARD_LM8323 is not set | ||
1095 | # CONFIG_KEYBOARD_MAX7359 is not set | ||
1096 | # CONFIG_KEYBOARD_NEWTON is not set | ||
1097 | # CONFIG_KEYBOARD_OPENCORES is not set | ||
1098 | # CONFIG_KEYBOARD_STOWAWAY is not set | ||
1099 | # CONFIG_KEYBOARD_SUNKBD is not set | ||
1100 | # CONFIG_KEYBOARD_TWL4030 is not set | ||
1101 | # CONFIG_KEYBOARD_XTKBD is not set | ||
1102 | CONFIG_INPUT_MOUSE=y | ||
1103 | CONFIG_MOUSE_PS2=y | ||
1104 | CONFIG_MOUSE_PS2_ALPS=y | ||
1105 | CONFIG_MOUSE_PS2_LOGIPS2PP=y | ||
1106 | CONFIG_MOUSE_PS2_SYNAPTICS=y | ||
1107 | CONFIG_MOUSE_PS2_TRACKPOINT=y | ||
1108 | # CONFIG_MOUSE_PS2_ELANTECH is not set | ||
1109 | # CONFIG_MOUSE_PS2_SENTELIC is not set | ||
1110 | # CONFIG_MOUSE_PS2_TOUCHKIT is not set | ||
1111 | # CONFIG_MOUSE_SERIAL is not set | ||
1112 | # CONFIG_MOUSE_APPLETOUCH is not set | ||
1113 | # CONFIG_MOUSE_BCM5974 is not set | ||
1114 | # CONFIG_MOUSE_VSXXXAA is not set | ||
1115 | # CONFIG_MOUSE_GPIO is not set | ||
1116 | # CONFIG_MOUSE_SYNAPTICS_I2C is not set | ||
1117 | # CONFIG_INPUT_JOYSTICK is not set | ||
1118 | # CONFIG_INPUT_TABLET is not set | ||
1119 | CONFIG_INPUT_TOUCHSCREEN=y | ||
1120 | CONFIG_TOUCHSCREEN_ADS7846=y | ||
1121 | # CONFIG_TOUCHSCREEN_AD7877 is not set | ||
1122 | # CONFIG_TOUCHSCREEN_AD7879_I2C is not set | ||
1123 | # CONFIG_TOUCHSCREEN_AD7879_SPI is not set | ||
1124 | # CONFIG_TOUCHSCREEN_AD7879 is not set | ||
1125 | # CONFIG_TOUCHSCREEN_EETI is not set | ||
1126 | # CONFIG_TOUCHSCREEN_FUJITSU is not set | ||
1127 | # CONFIG_TOUCHSCREEN_GUNZE is not set | ||
1128 | # CONFIG_TOUCHSCREEN_ELO is not set | ||
1129 | # CONFIG_TOUCHSCREEN_WACOM_W8001 is not set | ||
1130 | # CONFIG_TOUCHSCREEN_MCS5000 is not set | ||
1131 | # CONFIG_TOUCHSCREEN_MTOUCH is not set | ||
1132 | # CONFIG_TOUCHSCREEN_INEXIO is not set | ||
1133 | # CONFIG_TOUCHSCREEN_MK712 is not set | ||
1134 | # CONFIG_TOUCHSCREEN_PENMOUNT is not set | ||
1135 | # CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set | ||
1136 | # CONFIG_TOUCHSCREEN_TOUCHWIN is not set | ||
1137 | # CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set | ||
1138 | # CONFIG_TOUCHSCREEN_TOUCHIT213 is not set | ||
1139 | # CONFIG_TOUCHSCREEN_TSC2007 is not set | ||
1140 | # CONFIG_TOUCHSCREEN_W90X900 is not set | ||
1141 | CONFIG_INPUT_MISC=y | ||
1142 | # CONFIG_INPUT_ATI_REMOTE is not set | ||
1143 | # CONFIG_INPUT_ATI_REMOTE2 is not set | ||
1144 | # CONFIG_INPUT_KEYSPAN_REMOTE is not set | ||
1145 | # CONFIG_INPUT_POWERMATE is not set | ||
1146 | # CONFIG_INPUT_YEALINK is not set | ||
1147 | # CONFIG_INPUT_CM109 is not set | ||
1148 | CONFIG_INPUT_TWL4030_PWRBUTTON=y | ||
1149 | CONFIG_INPUT_UINPUT=y | ||
1150 | # CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set | ||
1151 | |||
1152 | # | ||
1153 | # Hardware I/O ports | ||
1154 | # | ||
1155 | CONFIG_SERIO=y | ||
1156 | CONFIG_SERIO_SERPORT=y | ||
1157 | CONFIG_SERIO_LIBPS2=y | ||
1158 | # CONFIG_SERIO_RAW is not set | ||
1159 | # CONFIG_GAMEPORT is not set | ||
1160 | |||
1161 | # | ||
1162 | # Character devices | ||
1163 | # | ||
1164 | CONFIG_VT=y | ||
1165 | CONFIG_CONSOLE_TRANSLATIONS=y | ||
1166 | CONFIG_VT_CONSOLE=y | ||
1167 | CONFIG_HW_CONSOLE=y | ||
1168 | CONFIG_VT_HW_CONSOLE_BINDING=y | ||
1169 | CONFIG_DEVKMEM=y | ||
1170 | # CONFIG_SERIAL_NONSTANDARD is not set | ||
1171 | |||
1172 | # | ||
1173 | # Serial drivers | ||
1174 | # | ||
1175 | CONFIG_SERIAL_8250=y | ||
1176 | CONFIG_SERIAL_8250_CONSOLE=y | ||
1177 | CONFIG_SERIAL_8250_NR_UARTS=32 | ||
1178 | CONFIG_SERIAL_8250_RUNTIME_UARTS=4 | ||
1179 | CONFIG_SERIAL_8250_EXTENDED=y | ||
1180 | CONFIG_SERIAL_8250_MANY_PORTS=y | ||
1181 | CONFIG_SERIAL_8250_SHARE_IRQ=y | ||
1182 | CONFIG_SERIAL_8250_DETECT_IRQ=y | ||
1183 | CONFIG_SERIAL_8250_RSA=y | ||
1184 | |||
1185 | # | ||
1186 | # Non-8250 serial port support | ||
1187 | # | ||
1188 | # CONFIG_SERIAL_MAX3100 is not set | ||
1189 | CONFIG_SERIAL_CORE=y | ||
1190 | CONFIG_SERIAL_CORE_CONSOLE=y | ||
1191 | CONFIG_UNIX98_PTYS=y | ||
1192 | # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set | ||
1193 | # CONFIG_LEGACY_PTYS is not set | ||
1194 | # CONFIG_IPMI_HANDLER is not set | ||
1195 | CONFIG_HW_RANDOM=y | ||
1196 | # CONFIG_HW_RANDOM_TIMERIOMEM is not set | ||
1197 | # CONFIG_R3964 is not set | ||
1198 | # CONFIG_RAW_DRIVER is not set | ||
1199 | # CONFIG_TCG_TPM is not set | ||
1200 | CONFIG_I2C=y | ||
1201 | CONFIG_I2C_BOARDINFO=y | ||
1202 | CONFIG_I2C_COMPAT=y | ||
1203 | CONFIG_I2C_CHARDEV=y | ||
1204 | CONFIG_I2C_HELPER_AUTO=y | ||
1205 | |||
1206 | # | ||
1207 | # I2C Hardware Bus support | ||
1208 | # | ||
1209 | |||
1210 | # | ||
1211 | # I2C system bus drivers (mostly embedded / system-on-chip) | ||
1212 | # | ||
1213 | # CONFIG_I2C_DESIGNWARE is not set | ||
1214 | # CONFIG_I2C_GPIO is not set | ||
1215 | # CONFIG_I2C_OCORES is not set | ||
1216 | CONFIG_I2C_OMAP=y | ||
1217 | # CONFIG_I2C_SIMTEC is not set | ||
1218 | |||
1219 | # | ||
1220 | # External I2C/SMBus adapter drivers | ||
1221 | # | ||
1222 | # CONFIG_I2C_PARPORT_LIGHT is not set | ||
1223 | # CONFIG_I2C_TAOS_EVM is not set | ||
1224 | # CONFIG_I2C_TINY_USB is not set | ||
1225 | |||
1226 | # | ||
1227 | # Other I2C/SMBus bus drivers | ||
1228 | # | ||
1229 | # CONFIG_I2C_PCA_PLATFORM is not set | ||
1230 | # CONFIG_I2C_STUB is not set | ||
1231 | |||
1232 | # | ||
1233 | # Miscellaneous I2C Chip support | ||
1234 | # | ||
1235 | # CONFIG_DS1682 is not set | ||
1236 | # CONFIG_SENSORS_TSL2550 is not set | ||
1237 | # CONFIG_I2C_DEBUG_CORE is not set | ||
1238 | # CONFIG_I2C_DEBUG_ALGO is not set | ||
1239 | # CONFIG_I2C_DEBUG_BUS is not set | ||
1240 | # CONFIG_I2C_DEBUG_CHIP is not set | ||
1241 | CONFIG_SPI=y | ||
1242 | # CONFIG_SPI_DEBUG is not set | ||
1243 | CONFIG_SPI_MASTER=y | ||
1244 | |||
1245 | # | ||
1246 | # SPI Master Controller Drivers | ||
1247 | # | ||
1248 | # CONFIG_SPI_BITBANG is not set | ||
1249 | # CONFIG_SPI_GPIO is not set | ||
1250 | CONFIG_SPI_OMAP24XX=y | ||
1251 | |||
1252 | # | ||
1253 | # SPI Protocol Masters | ||
1254 | # | ||
1255 | CONFIG_SPI_SPIDEV=y | ||
1256 | # CONFIG_SPI_TLE62X0 is not set | ||
1257 | |||
1258 | # | ||
1259 | # PPS support | ||
1260 | # | ||
1261 | # CONFIG_PPS is not set | ||
1262 | CONFIG_ARCH_REQUIRE_GPIOLIB=y | ||
1263 | CONFIG_GPIOLIB=y | ||
1264 | # CONFIG_DEBUG_GPIO is not set | ||
1265 | CONFIG_GPIO_SYSFS=y | ||
1266 | |||
1267 | # | ||
1268 | # Memory mapped GPIO expanders: | ||
1269 | # | ||
1270 | |||
1271 | # | ||
1272 | # I2C GPIO expanders: | ||
1273 | # | ||
1274 | # CONFIG_GPIO_MAX732X is not set | ||
1275 | # CONFIG_GPIO_PCA953X is not set | ||
1276 | # CONFIG_GPIO_PCF857X is not set | ||
1277 | CONFIG_GPIO_TWL4030=y | ||
1278 | |||
1279 | # | ||
1280 | # PCI GPIO expanders: | ||
1281 | # | ||
1282 | |||
1283 | # | ||
1284 | # SPI GPIO expanders: | ||
1285 | # | ||
1286 | # CONFIG_GPIO_MAX7301 is not set | ||
1287 | # CONFIG_GPIO_MCP23S08 is not set | ||
1288 | # CONFIG_GPIO_MC33880 is not set | ||
1289 | |||
1290 | # | ||
1291 | # AC97 GPIO expanders: | ||
1292 | # | ||
1293 | # CONFIG_W1 is not set | ||
1294 | CONFIG_POWER_SUPPLY=y | ||
1295 | # CONFIG_POWER_SUPPLY_DEBUG is not set | ||
1296 | # CONFIG_PDA_POWER is not set | ||
1297 | # CONFIG_BATTERY_DS2760 is not set | ||
1298 | # CONFIG_BATTERY_DS2782 is not set | ||
1299 | CONFIG_BATTERY_BQ27x00=y | ||
1300 | # CONFIG_BATTERY_MAX17040 is not set | ||
1301 | CONFIG_HWMON=y | ||
1302 | # CONFIG_HWMON_VID is not set | ||
1303 | # CONFIG_HWMON_DEBUG_CHIP is not set | ||
1304 | |||
1305 | # | ||
1306 | # Native drivers | ||
1307 | # | ||
1308 | # CONFIG_SENSORS_AD7414 is not set | ||
1309 | # CONFIG_SENSORS_AD7418 is not set | ||
1310 | # CONFIG_SENSORS_ADCXX is not set | ||
1311 | # CONFIG_SENSORS_ADM1021 is not set | ||
1312 | # CONFIG_SENSORS_ADM1025 is not set | ||
1313 | # CONFIG_SENSORS_ADM1026 is not set | ||
1314 | # CONFIG_SENSORS_ADM1029 is not set | ||
1315 | # CONFIG_SENSORS_ADM1031 is not set | ||
1316 | # CONFIG_SENSORS_ADM9240 is not set | ||
1317 | # CONFIG_SENSORS_ADT7462 is not set | ||
1318 | # CONFIG_SENSORS_ADT7470 is not set | ||
1319 | # CONFIG_SENSORS_ADT7473 is not set | ||
1320 | # CONFIG_SENSORS_ADT7475 is not set | ||
1321 | # CONFIG_SENSORS_ATXP1 is not set | ||
1322 | # CONFIG_SENSORS_DS1621 is not set | ||
1323 | # CONFIG_SENSORS_F71805F is not set | ||
1324 | # CONFIG_SENSORS_F71882FG is not set | ||
1325 | # CONFIG_SENSORS_F75375S is not set | ||
1326 | # CONFIG_SENSORS_G760A is not set | ||
1327 | # CONFIG_SENSORS_GL518SM is not set | ||
1328 | # CONFIG_SENSORS_GL520SM is not set | ||
1329 | # CONFIG_SENSORS_IT87 is not set | ||
1330 | # CONFIG_SENSORS_LM63 is not set | ||
1331 | # CONFIG_SENSORS_LM70 is not set | ||
1332 | # CONFIG_SENSORS_LM75 is not set | ||
1333 | # CONFIG_SENSORS_LM77 is not set | ||
1334 | # CONFIG_SENSORS_LM78 is not set | ||
1335 | # CONFIG_SENSORS_LM80 is not set | ||
1336 | # CONFIG_SENSORS_LM83 is not set | ||
1337 | # CONFIG_SENSORS_LM85 is not set | ||
1338 | # CONFIG_SENSORS_LM87 is not set | ||
1339 | # CONFIG_SENSORS_LM90 is not set | ||
1340 | # CONFIG_SENSORS_LM92 is not set | ||
1341 | # CONFIG_SENSORS_LM93 is not set | ||
1342 | # CONFIG_SENSORS_LTC4215 is not set | ||
1343 | # CONFIG_SENSORS_LTC4245 is not set | ||
1344 | # CONFIG_SENSORS_LM95241 is not set | ||
1345 | # CONFIG_SENSORS_MAX1111 is not set | ||
1346 | # CONFIG_SENSORS_MAX1619 is not set | ||
1347 | # CONFIG_SENSORS_MAX6650 is not set | ||
1348 | # CONFIG_SENSORS_PC87360 is not set | ||
1349 | # CONFIG_SENSORS_PC87427 is not set | ||
1350 | # CONFIG_SENSORS_PCF8591 is not set | ||
1351 | # CONFIG_SENSORS_SHT15 is not set | ||
1352 | # CONFIG_SENSORS_DME1737 is not set | ||
1353 | # CONFIG_SENSORS_SMSC47M1 is not set | ||
1354 | # CONFIG_SENSORS_SMSC47M192 is not set | ||
1355 | # CONFIG_SENSORS_SMSC47B397 is not set | ||
1356 | # CONFIG_SENSORS_ADS7828 is not set | ||
1357 | # CONFIG_SENSORS_THMC50 is not set | ||
1358 | # CONFIG_SENSORS_TMP401 is not set | ||
1359 | # CONFIG_SENSORS_TMP421 is not set | ||
1360 | # CONFIG_SENSORS_VT1211 is not set | ||
1361 | # CONFIG_SENSORS_W83781D is not set | ||
1362 | # CONFIG_SENSORS_W83791D is not set | ||
1363 | # CONFIG_SENSORS_W83792D is not set | ||
1364 | # CONFIG_SENSORS_W83793 is not set | ||
1365 | # CONFIG_SENSORS_W83L785TS is not set | ||
1366 | # CONFIG_SENSORS_W83L786NG is not set | ||
1367 | # CONFIG_SENSORS_W83627HF is not set | ||
1368 | # CONFIG_SENSORS_W83627EHF is not set | ||
1369 | # CONFIG_SENSORS_LIS3_SPI is not set | ||
1370 | CONFIG_THERMAL=y | ||
1371 | CONFIG_THERMAL_HWMON=y | ||
1372 | CONFIG_WATCHDOG=y | ||
1373 | CONFIG_WATCHDOG_NOWAYOUT=y | ||
1374 | |||
1375 | # | ||
1376 | # Watchdog Device Drivers | ||
1377 | # | ||
1378 | # CONFIG_SOFT_WATCHDOG is not set | ||
1379 | CONFIG_OMAP_WATCHDOG=y | ||
1380 | # CONFIG_TWL4030_WATCHDOG is not set | ||
1381 | |||
1382 | # | ||
1383 | # USB-based Watchdog Cards | ||
1384 | # | ||
1385 | # CONFIG_USBPCWATCHDOG is not set | ||
1386 | CONFIG_SSB_POSSIBLE=y | ||
1387 | |||
1388 | # | ||
1389 | # Sonics Silicon Backplane | ||
1390 | # | ||
1391 | # CONFIG_SSB is not set | ||
1392 | |||
1393 | # | ||
1394 | # Multifunction device drivers | ||
1395 | # | ||
1396 | # CONFIG_MFD_CORE is not set | ||
1397 | # CONFIG_MFD_SM501 is not set | ||
1398 | # CONFIG_MFD_ASIC3 is not set | ||
1399 | # CONFIG_HTC_EGPIO is not set | ||
1400 | # CONFIG_HTC_PASIC3 is not set | ||
1401 | # CONFIG_TPS65010 is not set | ||
1402 | CONFIG_TWL4030_CORE=y | ||
1403 | # CONFIG_TWL4030_POWER is not set | ||
1404 | # CONFIG_TWL4030_CODEC is not set | ||
1405 | # CONFIG_MFD_TMIO is not set | ||
1406 | # CONFIG_MFD_T7L66XB is not set | ||
1407 | # CONFIG_MFD_TC6387XB is not set | ||
1408 | # CONFIG_MFD_TC6393XB is not set | ||
1409 | # CONFIG_PMIC_DA903X is not set | ||
1410 | # CONFIG_MFD_WM8400 is not set | ||
1411 | # CONFIG_MFD_WM831X is not set | ||
1412 | # CONFIG_MFD_WM8350_I2C is not set | ||
1413 | # CONFIG_MFD_PCF50633 is not set | ||
1414 | # CONFIG_MFD_MC13783 is not set | ||
1415 | # CONFIG_AB3100_CORE is not set | ||
1416 | # CONFIG_EZX_PCAP is not set | ||
1417 | CONFIG_REGULATOR=y | ||
1418 | # CONFIG_REGULATOR_DEBUG is not set | ||
1419 | # CONFIG_REGULATOR_FIXED_VOLTAGE is not set | ||
1420 | # CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set | ||
1421 | # CONFIG_REGULATOR_USERSPACE_CONSUMER is not set | ||
1422 | # CONFIG_REGULATOR_BQ24022 is not set | ||
1423 | # CONFIG_REGULATOR_MAX1586 is not set | ||
1424 | CONFIG_REGULATOR_TWL4030=y | ||
1425 | # CONFIG_REGULATOR_LP3971 is not set | ||
1426 | # CONFIG_REGULATOR_TPS65023 is not set | ||
1427 | # CONFIG_REGULATOR_TPS6507X is not set | ||
1428 | # CONFIG_MEDIA_SUPPORT is not set | ||
1429 | |||
1430 | # | ||
1431 | # Graphics support | ||
1432 | # | ||
1433 | # CONFIG_VGASTATE is not set | ||
1434 | # CONFIG_VIDEO_OUTPUT_CONTROL is not set | ||
1435 | CONFIG_FB=y | ||
1436 | # CONFIG_FIRMWARE_EDID is not set | ||
1437 | # CONFIG_FB_DDC is not set | ||
1438 | # CONFIG_FB_BOOT_VESA_SUPPORT is not set | ||
1439 | # CONFIG_FB_CFB_FILLRECT is not set | ||
1440 | # CONFIG_FB_CFB_COPYAREA is not set | ||
1441 | # CONFIG_FB_CFB_IMAGEBLIT is not set | ||
1442 | # CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set | ||
1443 | # CONFIG_FB_SYS_FILLRECT is not set | ||
1444 | # CONFIG_FB_SYS_COPYAREA is not set | ||
1445 | # CONFIG_FB_SYS_IMAGEBLIT is not set | ||
1446 | # CONFIG_FB_FOREIGN_ENDIAN is not set | ||
1447 | # CONFIG_FB_SYS_FOPS is not set | ||
1448 | # CONFIG_FB_SVGALIB is not set | ||
1449 | # CONFIG_FB_MACMODES is not set | ||
1450 | # CONFIG_FB_BACKLIGHT is not set | ||
1451 | # CONFIG_FB_MODE_HELPERS is not set | ||
1452 | # CONFIG_FB_TILEBLITTING is not set | ||
1453 | |||
1454 | # | ||
1455 | # Frame buffer hardware drivers | ||
1456 | # | ||
1457 | # CONFIG_FB_S1D13XXX is not set | ||
1458 | # CONFIG_FB_VIRTUAL is not set | ||
1459 | # CONFIG_FB_METRONOME is not set | ||
1460 | # CONFIG_FB_MB862XX is not set | ||
1461 | # CONFIG_FB_BROADSHEET is not set | ||
1462 | # CONFIG_FB_OMAP is not set | ||
1463 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | ||
1464 | CONFIG_BACKLIGHT_CLASS_DEVICE=y | ||
1465 | CONFIG_BACKLIGHT_GENERIC=y | ||
1466 | |||
1467 | # | ||
1468 | # Display device support | ||
1469 | # | ||
1470 | CONFIG_DISPLAY_SUPPORT=y | ||
1471 | |||
1472 | # | ||
1473 | # Display hardware drivers | ||
1474 | # | ||
1475 | |||
1476 | # | ||
1477 | # Console display driver support | ||
1478 | # | ||
1479 | # CONFIG_VGA_CONSOLE is not set | ||
1480 | CONFIG_DUMMY_CONSOLE=y | ||
1481 | CONFIG_FRAMEBUFFER_CONSOLE=y | ||
1482 | # CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set | ||
1483 | CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y | ||
1484 | # CONFIG_FONTS is not set | ||
1485 | CONFIG_FONT_8x8=y | ||
1486 | CONFIG_FONT_8x16=y | ||
1487 | CONFIG_LOGO=y | ||
1488 | CONFIG_LOGO_LINUX_MONO=y | ||
1489 | CONFIG_LOGO_LINUX_VGA16=y | ||
1490 | CONFIG_LOGO_LINUX_CLUT224=y | ||
1491 | CONFIG_SOUND=y | ||
1492 | CONFIG_SOUND_OSS_CORE=y | ||
1493 | CONFIG_SOUND_OSS_CORE_PRECLAIM=y | ||
1494 | CONFIG_SND=y | ||
1495 | CONFIG_SND_TIMER=y | ||
1496 | CONFIG_SND_PCM=y | ||
1497 | CONFIG_SND_HWDEP=y | ||
1498 | CONFIG_SND_RAWMIDI=y | ||
1499 | CONFIG_SND_JACK=y | ||
1500 | CONFIG_SND_SEQUENCER=m | ||
1501 | # CONFIG_SND_SEQ_DUMMY is not set | ||
1502 | CONFIG_SND_OSSEMUL=y | ||
1503 | CONFIG_SND_MIXER_OSS=y | ||
1504 | CONFIG_SND_PCM_OSS=y | ||
1505 | CONFIG_SND_PCM_OSS_PLUGINS=y | ||
1506 | CONFIG_SND_SEQUENCER_OSS=y | ||
1507 | CONFIG_SND_HRTIMER=m | ||
1508 | CONFIG_SND_SEQ_HRTIMER_DEFAULT=y | ||
1509 | # CONFIG_SND_DYNAMIC_MINORS is not set | ||
1510 | CONFIG_SND_SUPPORT_OLD_API=y | ||
1511 | CONFIG_SND_VERBOSE_PROCFS=y | ||
1512 | # CONFIG_SND_VERBOSE_PRINTK is not set | ||
1513 | # CONFIG_SND_DEBUG is not set | ||
1514 | CONFIG_SND_RAWMIDI_SEQ=m | ||
1515 | # CONFIG_SND_OPL3_LIB_SEQ is not set | ||
1516 | # CONFIG_SND_OPL4_LIB_SEQ is not set | ||
1517 | # CONFIG_SND_SBAWE_SEQ is not set | ||
1518 | # CONFIG_SND_EMU10K1_SEQ is not set | ||
1519 | CONFIG_SND_DRIVERS=y | ||
1520 | # CONFIG_SND_DUMMY is not set | ||
1521 | # CONFIG_SND_VIRMIDI is not set | ||
1522 | # CONFIG_SND_MTPAV is not set | ||
1523 | # CONFIG_SND_SERIAL_U16550 is not set | ||
1524 | # CONFIG_SND_MPU401 is not set | ||
1525 | # CONFIG_SND_ARM is not set | ||
1526 | CONFIG_SND_SPI=y | ||
1527 | CONFIG_SND_USB=y | ||
1528 | CONFIG_SND_USB_AUDIO=y | ||
1529 | CONFIG_SND_USB_CAIAQ=m | ||
1530 | CONFIG_SND_USB_CAIAQ_INPUT=y | ||
1531 | CONFIG_SND_SOC=y | ||
1532 | CONFIG_SND_OMAP_SOC=y | ||
1533 | CONFIG_SND_SOC_I2C_AND_SPI=y | ||
1534 | # CONFIG_SND_SOC_ALL_CODECS is not set | ||
1535 | # CONFIG_SOUND_PRIME is not set | ||
1536 | CONFIG_HID_SUPPORT=y | ||
1537 | CONFIG_HID=y | ||
1538 | # CONFIG_HIDRAW is not set | ||
1539 | |||
1540 | # | ||
1541 | # USB Input Devices | ||
1542 | # | ||
1543 | CONFIG_USB_HID=y | ||
1544 | # CONFIG_HID_PID is not set | ||
1545 | # CONFIG_USB_HIDDEV is not set | ||
1546 | |||
1547 | # | ||
1548 | # Special HID drivers | ||
1549 | # | ||
1550 | # CONFIG_HID_A4TECH is not set | ||
1551 | # CONFIG_HID_APPLE is not set | ||
1552 | # CONFIG_HID_BELKIN is not set | ||
1553 | # CONFIG_HID_CHERRY is not set | ||
1554 | # CONFIG_HID_CHICONY is not set | ||
1555 | # CONFIG_HID_CYPRESS is not set | ||
1556 | # CONFIG_HID_DRAGONRISE is not set | ||
1557 | # CONFIG_HID_EZKEY is not set | ||
1558 | # CONFIG_HID_KYE is not set | ||
1559 | # CONFIG_HID_GYRATION is not set | ||
1560 | # CONFIG_HID_TWINHAN is not set | ||
1561 | # CONFIG_HID_KENSINGTON is not set | ||
1562 | # CONFIG_HID_LOGITECH is not set | ||
1563 | # CONFIG_HID_MICROSOFT is not set | ||
1564 | # CONFIG_HID_MONTEREY is not set | ||
1565 | # CONFIG_HID_NTRIG is not set | ||
1566 | # CONFIG_HID_PANTHERLORD is not set | ||
1567 | # CONFIG_HID_PETALYNX is not set | ||
1568 | # CONFIG_HID_SAMSUNG is not set | ||
1569 | # CONFIG_HID_SONY is not set | ||
1570 | # CONFIG_HID_SUNPLUS is not set | ||
1571 | # CONFIG_HID_GREENASIA is not set | ||
1572 | # CONFIG_HID_SMARTJOYPLUS is not set | ||
1573 | # CONFIG_HID_TOPSEED is not set | ||
1574 | # CONFIG_HID_THRUSTMASTER is not set | ||
1575 | # CONFIG_HID_WACOM is not set | ||
1576 | # CONFIG_HID_ZEROPLUS is not set | ||
1577 | CONFIG_USB_SUPPORT=y | ||
1578 | CONFIG_USB_ARCH_HAS_HCD=y | ||
1579 | CONFIG_USB_ARCH_HAS_OHCI=y | ||
1580 | # CONFIG_USB_ARCH_HAS_EHCI is not set | ||
1581 | CONFIG_USB=y | ||
1582 | # CONFIG_USB_DEBUG is not set | ||
1583 | # CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set | ||
1584 | |||
1585 | # | ||
1586 | # Miscellaneous USB options | ||
1587 | # | ||
1588 | CONFIG_USB_DEVICEFS=y | ||
1589 | CONFIG_USB_DEVICE_CLASS=y | ||
1590 | # CONFIG_USB_DYNAMIC_MINORS is not set | ||
1591 | CONFIG_USB_SUSPEND=y | ||
1592 | CONFIG_USB_OTG=y | ||
1593 | # CONFIG_USB_OTG_WHITELIST is not set | ||
1594 | # CONFIG_USB_OTG_BLACKLIST_HUB is not set | ||
1595 | CONFIG_USB_MON=y | ||
1596 | # CONFIG_USB_WUSB is not set | ||
1597 | # CONFIG_USB_WUSB_CBAF is not set | ||
1598 | |||
1599 | # | ||
1600 | # USB Host Controller Drivers | ||
1601 | # | ||
1602 | # CONFIG_USB_C67X00_HCD is not set | ||
1603 | CONFIG_USB_OXU210HP_HCD=y | ||
1604 | # CONFIG_USB_ISP116X_HCD is not set | ||
1605 | # CONFIG_USB_ISP1760_HCD is not set | ||
1606 | # CONFIG_USB_ISP1362_HCD is not set | ||
1607 | # CONFIG_USB_OHCI_HCD is not set | ||
1608 | # CONFIG_USB_SL811_HCD is not set | ||
1609 | # CONFIG_USB_R8A66597_HCD is not set | ||
1610 | # CONFIG_USB_HWA_HCD is not set | ||
1611 | CONFIG_USB_MUSB_HDRC=y | ||
1612 | CONFIG_USB_MUSB_SOC=y | ||
1613 | |||
1614 | # | ||
1615 | # OMAP 343x high speed USB support | ||
1616 | # | ||
1617 | # CONFIG_USB_MUSB_HOST is not set | ||
1618 | # CONFIG_USB_MUSB_PERIPHERAL is not set | ||
1619 | CONFIG_USB_MUSB_OTG=y | ||
1620 | CONFIG_USB_GADGET_MUSB_HDRC=y | ||
1621 | CONFIG_USB_MUSB_HDRC_HCD=y | ||
1622 | # CONFIG_MUSB_PIO_ONLY is not set | ||
1623 | CONFIG_USB_INVENTRA_DMA=y | ||
1624 | # CONFIG_USB_TI_CPPI_DMA is not set | ||
1625 | # CONFIG_USB_MUSB_DEBUG is not set | ||
1626 | |||
1627 | # | ||
1628 | # USB Device Class drivers | ||
1629 | # | ||
1630 | CONFIG_USB_ACM=m | ||
1631 | CONFIG_USB_PRINTER=m | ||
1632 | CONFIG_USB_WDM=m | ||
1633 | CONFIG_USB_TMC=m | ||
1634 | |||
1635 | # | ||
1636 | # NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may | ||
1637 | # | ||
1638 | |||
1639 | # | ||
1640 | # also be needed; see USB_STORAGE Help for more info | ||
1641 | # | ||
1642 | CONFIG_USB_STORAGE=y | ||
1643 | # CONFIG_USB_STORAGE_DEBUG is not set | ||
1644 | # CONFIG_USB_STORAGE_DATAFAB is not set | ||
1645 | # CONFIG_USB_STORAGE_FREECOM is not set | ||
1646 | # CONFIG_USB_STORAGE_ISD200 is not set | ||
1647 | # CONFIG_USB_STORAGE_USBAT is not set | ||
1648 | # CONFIG_USB_STORAGE_SDDR09 is not set | ||
1649 | # CONFIG_USB_STORAGE_SDDR55 is not set | ||
1650 | # CONFIG_USB_STORAGE_JUMPSHOT is not set | ||
1651 | # CONFIG_USB_STORAGE_ALAUDA is not set | ||
1652 | # CONFIG_USB_STORAGE_ONETOUCH is not set | ||
1653 | # CONFIG_USB_STORAGE_KARMA is not set | ||
1654 | # CONFIG_USB_STORAGE_CYPRESS_ATACB is not set | ||
1655 | # CONFIG_USB_LIBUSUAL is not set | ||
1656 | |||
1657 | # | ||
1658 | # USB Imaging devices | ||
1659 | # | ||
1660 | # CONFIG_USB_MDC800 is not set | ||
1661 | # CONFIG_USB_MICROTEK is not set | ||
1662 | |||
1663 | # | ||
1664 | # USB port drivers | ||
1665 | # | ||
1666 | CONFIG_USB_SERIAL=m | ||
1667 | CONFIG_USB_EZUSB=y | ||
1668 | CONFIG_USB_SERIAL_GENERIC=y | ||
1669 | CONFIG_USB_SERIAL_AIRCABLE=m | ||
1670 | CONFIG_USB_SERIAL_ARK3116=m | ||
1671 | CONFIG_USB_SERIAL_BELKIN=m | ||
1672 | CONFIG_USB_SERIAL_CH341=m | ||
1673 | CONFIG_USB_SERIAL_WHITEHEAT=m | ||
1674 | CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m | ||
1675 | # CONFIG_USB_SERIAL_CP210X is not set | ||
1676 | CONFIG_USB_SERIAL_CYPRESS_M8=m | ||
1677 | CONFIG_USB_SERIAL_EMPEG=m | ||
1678 | CONFIG_USB_SERIAL_FTDI_SIO=m | ||
1679 | CONFIG_USB_SERIAL_FUNSOFT=m | ||
1680 | CONFIG_USB_SERIAL_VISOR=m | ||
1681 | CONFIG_USB_SERIAL_IPAQ=m | ||
1682 | CONFIG_USB_SERIAL_IR=m | ||
1683 | CONFIG_USB_SERIAL_EDGEPORT=m | ||
1684 | CONFIG_USB_SERIAL_EDGEPORT_TI=m | ||
1685 | CONFIG_USB_SERIAL_GARMIN=m | ||
1686 | CONFIG_USB_SERIAL_IPW=m | ||
1687 | CONFIG_USB_SERIAL_IUU=m | ||
1688 | CONFIG_USB_SERIAL_KEYSPAN_PDA=m | ||
1689 | CONFIG_USB_SERIAL_KEYSPAN=m | ||
1690 | CONFIG_USB_SERIAL_KEYSPAN_MPR=y | ||
1691 | CONFIG_USB_SERIAL_KEYSPAN_USA28=y | ||
1692 | CONFIG_USB_SERIAL_KEYSPAN_USA28X=y | ||
1693 | CONFIG_USB_SERIAL_KEYSPAN_USA28XA=y | ||
1694 | CONFIG_USB_SERIAL_KEYSPAN_USA28XB=y | ||
1695 | CONFIG_USB_SERIAL_KEYSPAN_USA19=y | ||
1696 | CONFIG_USB_SERIAL_KEYSPAN_USA18X=y | ||
1697 | CONFIG_USB_SERIAL_KEYSPAN_USA19W=y | ||
1698 | CONFIG_USB_SERIAL_KEYSPAN_USA19QW=y | ||
1699 | CONFIG_USB_SERIAL_KEYSPAN_USA19QI=y | ||
1700 | CONFIG_USB_SERIAL_KEYSPAN_USA49W=y | ||
1701 | CONFIG_USB_SERIAL_KEYSPAN_USA49WLC=y | ||
1702 | CONFIG_USB_SERIAL_KLSI=m | ||
1703 | CONFIG_USB_SERIAL_KOBIL_SCT=m | ||
1704 | CONFIG_USB_SERIAL_MCT_U232=m | ||
1705 | CONFIG_USB_SERIAL_MOS7720=m | ||
1706 | CONFIG_USB_SERIAL_MOS7840=m | ||
1707 | CONFIG_USB_SERIAL_MOTOROLA=m | ||
1708 | CONFIG_USB_SERIAL_NAVMAN=m | ||
1709 | CONFIG_USB_SERIAL_PL2303=m | ||
1710 | CONFIG_USB_SERIAL_OTI6858=m | ||
1711 | # CONFIG_USB_SERIAL_QUALCOMM is not set | ||
1712 | CONFIG_USB_SERIAL_SPCP8X5=m | ||
1713 | CONFIG_USB_SERIAL_HP4X=m | ||
1714 | CONFIG_USB_SERIAL_SAFE=m | ||
1715 | # CONFIG_USB_SERIAL_SAFE_PADDED is not set | ||
1716 | CONFIG_USB_SERIAL_SIEMENS_MPI=m | ||
1717 | CONFIG_USB_SERIAL_SIERRAWIRELESS=m | ||
1718 | # CONFIG_USB_SERIAL_SYMBOL is not set | ||
1719 | CONFIG_USB_SERIAL_TI=m | ||
1720 | CONFIG_USB_SERIAL_CYBERJACK=m | ||
1721 | CONFIG_USB_SERIAL_XIRCOM=m | ||
1722 | CONFIG_USB_SERIAL_OPTION=m | ||
1723 | CONFIG_USB_SERIAL_OMNINET=m | ||
1724 | CONFIG_USB_SERIAL_OPTICON=m | ||
1725 | CONFIG_USB_SERIAL_DEBUG=m | ||
1726 | |||
1727 | # | ||
1728 | # USB Miscellaneous drivers | ||
1729 | # | ||
1730 | CONFIG_USB_EMI62=m | ||
1731 | CONFIG_USB_EMI26=m | ||
1732 | # CONFIG_USB_ADUTUX is not set | ||
1733 | # CONFIG_USB_SEVSEG is not set | ||
1734 | # CONFIG_USB_RIO500 is not set | ||
1735 | # CONFIG_USB_LEGOTOWER is not set | ||
1736 | # CONFIG_USB_LCD is not set | ||
1737 | # CONFIG_USB_BERRY_CHARGE is not set | ||
1738 | # CONFIG_USB_LED is not set | ||
1739 | # CONFIG_USB_CYPRESS_CY7C63 is not set | ||
1740 | # CONFIG_USB_CYTHERM is not set | ||
1741 | # CONFIG_USB_IDMOUSE is not set | ||
1742 | # CONFIG_USB_FTDI_ELAN is not set | ||
1743 | # CONFIG_USB_APPLEDISPLAY is not set | ||
1744 | CONFIG_USB_SISUSBVGA=m | ||
1745 | CONFIG_USB_SISUSBVGA_CON=y | ||
1746 | # CONFIG_USB_LD is not set | ||
1747 | # CONFIG_USB_TRANCEVIBRATOR is not set | ||
1748 | # CONFIG_USB_IOWARRIOR is not set | ||
1749 | CONFIG_USB_TEST=m | ||
1750 | # CONFIG_USB_ISIGHTFW is not set | ||
1751 | # CONFIG_USB_VST is not set | ||
1752 | # CONFIG_USB_ATM is not set | ||
1753 | CONFIG_USB_GADGET=m | ||
1754 | # CONFIG_USB_GADGET_DEBUG is not set | ||
1755 | # CONFIG_USB_GADGET_DEBUG_FILES is not set | ||
1756 | CONFIG_USB_GADGET_DEBUG_FS=y | ||
1757 | CONFIG_USB_GADGET_VBUS_DRAW=2 | ||
1758 | CONFIG_USB_GADGET_SELECTED=y | ||
1759 | # CONFIG_USB_GADGET_AT91 is not set | ||
1760 | # CONFIG_USB_GADGET_ATMEL_USBA is not set | ||
1761 | # CONFIG_USB_GADGET_FSL_USB2 is not set | ||
1762 | # CONFIG_USB_GADGET_LH7A40X is not set | ||
1763 | # CONFIG_USB_GADGET_OMAP is not set | ||
1764 | # CONFIG_USB_GADGET_PXA25X is not set | ||
1765 | # CONFIG_USB_GADGET_R8A66597 is not set | ||
1766 | # CONFIG_USB_GADGET_PXA27X is not set | ||
1767 | # CONFIG_USB_GADGET_S3C_HSOTG is not set | ||
1768 | # CONFIG_USB_GADGET_IMX is not set | ||
1769 | # CONFIG_USB_GADGET_S3C2410 is not set | ||
1770 | # CONFIG_USB_GADGET_M66592 is not set | ||
1771 | # CONFIG_USB_GADGET_AMD5536UDC is not set | ||
1772 | # CONFIG_USB_GADGET_FSL_QE is not set | ||
1773 | # CONFIG_USB_GADGET_CI13XXX is not set | ||
1774 | # CONFIG_USB_GADGET_NET2280 is not set | ||
1775 | # CONFIG_USB_GADGET_GOKU is not set | ||
1776 | # CONFIG_USB_GADGET_LANGWELL is not set | ||
1777 | # CONFIG_USB_GADGET_DUMMY_HCD is not set | ||
1778 | CONFIG_USB_GADGET_DUALSPEED=y | ||
1779 | CONFIG_USB_ZERO=m | ||
1780 | CONFIG_USB_ZERO_HNPTEST=y | ||
1781 | # CONFIG_USB_AUDIO is not set | ||
1782 | CONFIG_USB_ETH=m | ||
1783 | CONFIG_USB_ETH_RNDIS=y | ||
1784 | # CONFIG_USB_ETH_EEM is not set | ||
1785 | CONFIG_USB_GADGETFS=m | ||
1786 | CONFIG_USB_FILE_STORAGE=m | ||
1787 | # CONFIG_USB_FILE_STORAGE_TEST is not set | ||
1788 | CONFIG_USB_G_SERIAL=m | ||
1789 | CONFIG_USB_MIDI_GADGET=m | ||
1790 | CONFIG_USB_G_PRINTER=m | ||
1791 | CONFIG_USB_CDC_COMPOSITE=m | ||
1792 | |||
1793 | # | ||
1794 | # OTG and related infrastructure | ||
1795 | # | ||
1796 | CONFIG_USB_OTG_UTILS=y | ||
1797 | CONFIG_USB_GPIO_VBUS=y | ||
1798 | # CONFIG_ISP1301_OMAP is not set | ||
1799 | CONFIG_TWL4030_USB=y | ||
1800 | # CONFIG_NOP_USB_XCEIV is not set | ||
1801 | CONFIG_MMC=y | ||
1802 | # CONFIG_MMC_DEBUG is not set | ||
1803 | CONFIG_MMC_UNSAFE_RESUME=y | ||
1804 | |||
1805 | # | ||
1806 | # MMC/SD/SDIO Card Drivers | ||
1807 | # | ||
1808 | CONFIG_MMC_BLOCK=y | ||
1809 | CONFIG_MMC_BLOCK_BOUNCE=y | ||
1810 | CONFIG_SDIO_UART=y | ||
1811 | # CONFIG_MMC_TEST is not set | ||
1812 | |||
1813 | # | ||
1814 | # MMC/SD/SDIO Host Controller Drivers | ||
1815 | # | ||
1816 | # CONFIG_MMC_SDHCI is not set | ||
1817 | # CONFIG_MMC_OMAP is not set | ||
1818 | CONFIG_MMC_OMAP_HS=y | ||
1819 | # CONFIG_MMC_AT91 is not set | ||
1820 | # CONFIG_MMC_ATMELMCI is not set | ||
1821 | CONFIG_MMC_SPI=m | ||
1822 | # CONFIG_MEMSTICK is not set | ||
1823 | CONFIG_NEW_LEDS=y | ||
1824 | CONFIG_LEDS_CLASS=y | ||
1825 | |||
1826 | # | ||
1827 | # LED drivers | ||
1828 | # | ||
1829 | # CONFIG_LEDS_PCA9532 is not set | ||
1830 | CONFIG_LEDS_GPIO=y | ||
1831 | CONFIG_LEDS_GPIO_PLATFORM=y | ||
1832 | # CONFIG_LEDS_LP3944 is not set | ||
1833 | # CONFIG_LEDS_PCA955X is not set | ||
1834 | # CONFIG_LEDS_DAC124S085 is not set | ||
1835 | # CONFIG_LEDS_BD2802 is not set | ||
1836 | |||
1837 | # | ||
1838 | # LED Triggers | ||
1839 | # | ||
1840 | CONFIG_LEDS_TRIGGERS=y | ||
1841 | CONFIG_LEDS_TRIGGER_TIMER=m | ||
1842 | CONFIG_LEDS_TRIGGER_HEARTBEAT=y | ||
1843 | CONFIG_LEDS_TRIGGER_BACKLIGHT=m | ||
1844 | # CONFIG_LEDS_TRIGGER_GPIO is not set | ||
1845 | CONFIG_LEDS_TRIGGER_DEFAULT_ON=m | ||
1846 | |||
1847 | # | ||
1848 | # iptables trigger is under Netfilter config (LED target) | ||
1849 | # | ||
1850 | # CONFIG_ACCESSIBILITY is not set | ||
1851 | CONFIG_RTC_LIB=y | ||
1852 | CONFIG_RTC_CLASS=y | ||
1853 | CONFIG_RTC_HCTOSYS=y | ||
1854 | CONFIG_RTC_HCTOSYS_DEVICE="rtc0" | ||
1855 | # CONFIG_RTC_DEBUG is not set | ||
1856 | |||
1857 | # | ||
1858 | # RTC interfaces | ||
1859 | # | ||
1860 | CONFIG_RTC_INTF_SYSFS=y | ||
1861 | CONFIG_RTC_INTF_PROC=y | ||
1862 | CONFIG_RTC_INTF_DEV=y | ||
1863 | # CONFIG_RTC_INTF_DEV_UIE_EMUL is not set | ||
1864 | # CONFIG_RTC_DRV_TEST is not set | ||
1865 | |||
1866 | # | ||
1867 | # I2C RTC drivers | ||
1868 | # | ||
1869 | # CONFIG_RTC_DRV_DS1307 is not set | ||
1870 | # CONFIG_RTC_DRV_DS1374 is not set | ||
1871 | # CONFIG_RTC_DRV_DS1672 is not set | ||
1872 | # CONFIG_RTC_DRV_MAX6900 is not set | ||
1873 | # CONFIG_RTC_DRV_RS5C372 is not set | ||
1874 | # CONFIG_RTC_DRV_ISL1208 is not set | ||
1875 | # CONFIG_RTC_DRV_X1205 is not set | ||
1876 | # CONFIG_RTC_DRV_PCF8563 is not set | ||
1877 | # CONFIG_RTC_DRV_PCF8583 is not set | ||
1878 | # CONFIG_RTC_DRV_M41T80 is not set | ||
1879 | CONFIG_RTC_DRV_TWL4030=y | ||
1880 | # CONFIG_RTC_DRV_S35390A is not set | ||
1881 | # CONFIG_RTC_DRV_FM3130 is not set | ||
1882 | # CONFIG_RTC_DRV_RX8581 is not set | ||
1883 | # CONFIG_RTC_DRV_RX8025 is not set | ||
1884 | |||
1885 | # | ||
1886 | # SPI RTC drivers | ||
1887 | # | ||
1888 | # CONFIG_RTC_DRV_M41T94 is not set | ||
1889 | # CONFIG_RTC_DRV_DS1305 is not set | ||
1890 | # CONFIG_RTC_DRV_DS1390 is not set | ||
1891 | # CONFIG_RTC_DRV_MAX6902 is not set | ||
1892 | # CONFIG_RTC_DRV_R9701 is not set | ||
1893 | # CONFIG_RTC_DRV_RS5C348 is not set | ||
1894 | # CONFIG_RTC_DRV_DS3234 is not set | ||
1895 | # CONFIG_RTC_DRV_PCF2123 is not set | ||
1896 | |||
1897 | # | ||
1898 | # Platform RTC drivers | ||
1899 | # | ||
1900 | # CONFIG_RTC_DRV_CMOS is not set | ||
1901 | # CONFIG_RTC_DRV_DS1286 is not set | ||
1902 | # CONFIG_RTC_DRV_DS1511 is not set | ||
1903 | # CONFIG_RTC_DRV_DS1553 is not set | ||
1904 | # CONFIG_RTC_DRV_DS1742 is not set | ||
1905 | # CONFIG_RTC_DRV_STK17TA8 is not set | ||
1906 | # CONFIG_RTC_DRV_M48T86 is not set | ||
1907 | # CONFIG_RTC_DRV_M48T35 is not set | ||
1908 | # CONFIG_RTC_DRV_M48T59 is not set | ||
1909 | # CONFIG_RTC_DRV_BQ4802 is not set | ||
1910 | # CONFIG_RTC_DRV_V3020 is not set | ||
1911 | |||
1912 | # | ||
1913 | # on-CPU RTC drivers | ||
1914 | # | ||
1915 | # CONFIG_DMADEVICES is not set | ||
1916 | # CONFIG_AUXDISPLAY is not set | ||
1917 | CONFIG_UIO=m | ||
1918 | CONFIG_UIO_PDRV=m | ||
1919 | CONFIG_UIO_PDRV_GENIRQ=m | ||
1920 | # CONFIG_UIO_SMX is not set | ||
1921 | # CONFIG_UIO_SERCOS3 is not set | ||
1922 | |||
1923 | # | ||
1924 | # TI VLYNQ | ||
1925 | # | ||
1926 | CONFIG_STAGING=y | ||
1927 | # CONFIG_STAGING_EXCLUDE_BUILD is not set | ||
1928 | # CONFIG_USB_IP_COMMON is not set | ||
1929 | # CONFIG_W35UND is not set | ||
1930 | # CONFIG_PRISM2_USB is not set | ||
1931 | # CONFIG_ECHO is not set | ||
1932 | # CONFIG_OTUS is not set | ||
1933 | # CONFIG_COMEDI is not set | ||
1934 | # CONFIG_ASUS_OLED is not set | ||
1935 | # CONFIG_INPUT_MIMIO is not set | ||
1936 | # CONFIG_TRANZPORT is not set | ||
1937 | |||
1938 | # | ||
1939 | # Android | ||
1940 | # | ||
1941 | |||
1942 | # | ||
1943 | # Qualcomm MSM Camera And Video | ||
1944 | # | ||
1945 | |||
1946 | # | ||
1947 | # Camera Sensor Selection | ||
1948 | # | ||
1949 | # CONFIG_INPUT_GPIO is not set | ||
1950 | # CONFIG_DST is not set | ||
1951 | # CONFIG_POHMELFS is not set | ||
1952 | # CONFIG_PLAN9AUTH is not set | ||
1953 | # CONFIG_LINE6_USB is not set | ||
1954 | # CONFIG_USB_SERIAL_QUATECH2 is not set | ||
1955 | # CONFIG_USB_SERIAL_QUATECH_USB2 is not set | ||
1956 | # CONFIG_VT6656 is not set | ||
1957 | # CONFIG_FB_UDL is not set | ||
1958 | |||
1959 | # | ||
1960 | # RAR Register Driver | ||
1961 | # | ||
1962 | # CONFIG_RAR_REGISTER is not set | ||
1963 | # CONFIG_IIO is not set | ||
1964 | |||
1965 | # | ||
1966 | # File systems | ||
1967 | # | ||
1968 | CONFIG_EXT2_FS=y | ||
1969 | # CONFIG_EXT2_FS_XATTR is not set | ||
1970 | # CONFIG_EXT2_FS_XIP is not set | ||
1971 | CONFIG_EXT3_FS=y | ||
1972 | # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set | ||
1973 | # CONFIG_EXT3_FS_XATTR is not set | ||
1974 | CONFIG_EXT4_FS=m | ||
1975 | CONFIG_EXT4_FS_XATTR=y | ||
1976 | # CONFIG_EXT4_FS_POSIX_ACL is not set | ||
1977 | # CONFIG_EXT4_FS_SECURITY is not set | ||
1978 | # CONFIG_EXT4_DEBUG is not set | ||
1979 | CONFIG_JBD=y | ||
1980 | # CONFIG_JBD_DEBUG is not set | ||
1981 | CONFIG_JBD2=m | ||
1982 | # CONFIG_JBD2_DEBUG is not set | ||
1983 | CONFIG_FS_MBCACHE=m | ||
1984 | CONFIG_REISERFS_FS=m | ||
1985 | # CONFIG_REISERFS_CHECK is not set | ||
1986 | CONFIG_REISERFS_PROC_INFO=y | ||
1987 | CONFIG_REISERFS_FS_XATTR=y | ||
1988 | # CONFIG_REISERFS_FS_POSIX_ACL is not set | ||
1989 | # CONFIG_REISERFS_FS_SECURITY is not set | ||
1990 | CONFIG_JFS_FS=m | ||
1991 | # CONFIG_JFS_POSIX_ACL is not set | ||
1992 | # CONFIG_JFS_SECURITY is not set | ||
1993 | # CONFIG_JFS_DEBUG is not set | ||
1994 | # CONFIG_JFS_STATISTICS is not set | ||
1995 | CONFIG_FS_POSIX_ACL=y | ||
1996 | CONFIG_XFS_FS=m | ||
1997 | # CONFIG_XFS_QUOTA is not set | ||
1998 | # CONFIG_XFS_POSIX_ACL is not set | ||
1999 | # CONFIG_XFS_RT is not set | ||
2000 | # CONFIG_XFS_DEBUG is not set | ||
2001 | # CONFIG_GFS2_FS is not set | ||
2002 | # CONFIG_OCFS2_FS is not set | ||
2003 | # CONFIG_BTRFS_FS is not set | ||
2004 | # CONFIG_NILFS2_FS is not set | ||
2005 | CONFIG_FILE_LOCKING=y | ||
2006 | CONFIG_FSNOTIFY=y | ||
2007 | CONFIG_DNOTIFY=y | ||
2008 | CONFIG_INOTIFY=y | ||
2009 | CONFIG_INOTIFY_USER=y | ||
2010 | CONFIG_QUOTA=y | ||
2011 | # CONFIG_QUOTA_NETLINK_INTERFACE is not set | ||
2012 | CONFIG_PRINT_QUOTA_WARNING=y | ||
2013 | CONFIG_QUOTA_TREE=y | ||
2014 | # CONFIG_QFMT_V1 is not set | ||
2015 | CONFIG_QFMT_V2=y | ||
2016 | CONFIG_QUOTACTL=y | ||
2017 | # CONFIG_AUTOFS_FS is not set | ||
2018 | CONFIG_AUTOFS4_FS=m | ||
2019 | CONFIG_FUSE_FS=y | ||
2020 | # CONFIG_CUSE is not set | ||
2021 | |||
2022 | # | ||
2023 | # Caches | ||
2024 | # | ||
2025 | # CONFIG_FSCACHE is not set | ||
2026 | |||
2027 | # | ||
2028 | # CD-ROM/DVD Filesystems | ||
2029 | # | ||
2030 | CONFIG_ISO9660_FS=m | ||
2031 | CONFIG_JOLIET=y | ||
2032 | CONFIG_ZISOFS=y | ||
2033 | CONFIG_UDF_FS=m | ||
2034 | CONFIG_UDF_NLS=y | ||
2035 | |||
2036 | # | ||
2037 | # DOS/FAT/NT Filesystems | ||
2038 | # | ||
2039 | CONFIG_FAT_FS=y | ||
2040 | CONFIG_MSDOS_FS=y | ||
2041 | CONFIG_VFAT_FS=y | ||
2042 | CONFIG_FAT_DEFAULT_CODEPAGE=437 | ||
2043 | CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" | ||
2044 | CONFIG_NTFS_FS=m | ||
2045 | # CONFIG_NTFS_DEBUG is not set | ||
2046 | CONFIG_NTFS_RW=y | ||
2047 | |||
2048 | # | ||
2049 | # Pseudo filesystems | ||
2050 | # | ||
2051 | CONFIG_PROC_FS=y | ||
2052 | CONFIG_PROC_SYSCTL=y | ||
2053 | CONFIG_PROC_PAGE_MONITOR=y | ||
2054 | CONFIG_SYSFS=y | ||
2055 | CONFIG_TMPFS=y | ||
2056 | # CONFIG_TMPFS_POSIX_ACL is not set | ||
2057 | # CONFIG_HUGETLB_PAGE is not set | ||
2058 | CONFIG_CONFIGFS_FS=m | ||
2059 | CONFIG_MISC_FILESYSTEMS=y | ||
2060 | # CONFIG_ADFS_FS is not set | ||
2061 | # CONFIG_AFFS_FS is not set | ||
2062 | # CONFIG_ECRYPT_FS is not set | ||
2063 | # CONFIG_HFS_FS is not set | ||
2064 | # CONFIG_HFSPLUS_FS is not set | ||
2065 | # CONFIG_BEFS_FS is not set | ||
2066 | # CONFIG_BFS_FS is not set | ||
2067 | # CONFIG_EFS_FS is not set | ||
2068 | CONFIG_JFFS2_FS=y | ||
2069 | CONFIG_JFFS2_FS_DEBUG=0 | ||
2070 | CONFIG_JFFS2_FS_WRITEBUFFER=y | ||
2071 | # CONFIG_JFFS2_FS_WBUF_VERIFY is not set | ||
2072 | CONFIG_JFFS2_SUMMARY=y | ||
2073 | CONFIG_JFFS2_FS_XATTR=y | ||
2074 | CONFIG_JFFS2_FS_POSIX_ACL=y | ||
2075 | CONFIG_JFFS2_FS_SECURITY=y | ||
2076 | CONFIG_JFFS2_COMPRESSION_OPTIONS=y | ||
2077 | CONFIG_JFFS2_ZLIB=y | ||
2078 | CONFIG_JFFS2_LZO=y | ||
2079 | CONFIG_JFFS2_RTIME=y | ||
2080 | CONFIG_JFFS2_RUBIN=y | ||
2081 | # CONFIG_JFFS2_CMODE_NONE is not set | ||
2082 | # CONFIG_JFFS2_CMODE_PRIORITY is not set | ||
2083 | # CONFIG_JFFS2_CMODE_SIZE is not set | ||
2084 | CONFIG_JFFS2_CMODE_FAVOURLZO=y | ||
2085 | CONFIG_UBIFS_FS=y | ||
2086 | CONFIG_UBIFS_FS_XATTR=y | ||
2087 | CONFIG_UBIFS_FS_ADVANCED_COMPR=y | ||
2088 | CONFIG_UBIFS_FS_LZO=y | ||
2089 | CONFIG_UBIFS_FS_ZLIB=y | ||
2090 | # CONFIG_UBIFS_FS_DEBUG is not set | ||
2091 | # CONFIG_CRAMFS is not set | ||
2092 | CONFIG_SQUASHFS=y | ||
2093 | # CONFIG_SQUASHFS_EMBEDDED is not set | ||
2094 | CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 | ||
2095 | # CONFIG_VXFS_FS is not set | ||
2096 | # CONFIG_MINIX_FS is not set | ||
2097 | # CONFIG_OMFS_FS is not set | ||
2098 | # CONFIG_HPFS_FS is not set | ||
2099 | # CONFIG_QNX4FS_FS is not set | ||
2100 | # CONFIG_ROMFS_FS is not set | ||
2101 | # CONFIG_SYSV_FS is not set | ||
2102 | # CONFIG_UFS_FS is not set | ||
2103 | CONFIG_NETWORK_FILESYSTEMS=y | ||
2104 | CONFIG_NFS_FS=y | ||
2105 | CONFIG_NFS_V3=y | ||
2106 | # CONFIG_NFS_V3_ACL is not set | ||
2107 | CONFIG_NFS_V4=y | ||
2108 | # CONFIG_NFS_V4_1 is not set | ||
2109 | CONFIG_ROOT_NFS=y | ||
2110 | CONFIG_NFSD=m | ||
2111 | CONFIG_NFSD_V2_ACL=y | ||
2112 | CONFIG_NFSD_V3=y | ||
2113 | CONFIG_NFSD_V3_ACL=y | ||
2114 | CONFIG_NFSD_V4=y | ||
2115 | CONFIG_LOCKD=y | ||
2116 | CONFIG_LOCKD_V4=y | ||
2117 | CONFIG_EXPORTFS=m | ||
2118 | CONFIG_NFS_ACL_SUPPORT=m | ||
2119 | CONFIG_NFS_COMMON=y | ||
2120 | CONFIG_SUNRPC=y | ||
2121 | CONFIG_SUNRPC_GSS=y | ||
2122 | CONFIG_RPCSEC_GSS_KRB5=y | ||
2123 | # CONFIG_RPCSEC_GSS_SPKM3 is not set | ||
2124 | # CONFIG_SMB_FS is not set | ||
2125 | CONFIG_CIFS=m | ||
2126 | CONFIG_CIFS_STATS=y | ||
2127 | CONFIG_CIFS_STATS2=y | ||
2128 | # CONFIG_CIFS_WEAK_PW_HASH is not set | ||
2129 | # CONFIG_CIFS_UPCALL is not set | ||
2130 | # CONFIG_CIFS_XATTR is not set | ||
2131 | # CONFIG_CIFS_DEBUG2 is not set | ||
2132 | # CONFIG_CIFS_DFS_UPCALL is not set | ||
2133 | CONFIG_CIFS_EXPERIMENTAL=y | ||
2134 | # CONFIG_NCP_FS is not set | ||
2135 | # CONFIG_CODA_FS is not set | ||
2136 | # CONFIG_AFS_FS is not set | ||
2137 | |||
2138 | # | ||
2139 | # Partition Types | ||
2140 | # | ||
2141 | CONFIG_PARTITION_ADVANCED=y | ||
2142 | # CONFIG_ACORN_PARTITION is not set | ||
2143 | # CONFIG_OSF_PARTITION is not set | ||
2144 | # CONFIG_AMIGA_PARTITION is not set | ||
2145 | # CONFIG_ATARI_PARTITION is not set | ||
2146 | # CONFIG_MAC_PARTITION is not set | ||
2147 | CONFIG_MSDOS_PARTITION=y | ||
2148 | CONFIG_BSD_DISKLABEL=y | ||
2149 | CONFIG_MINIX_SUBPARTITION=y | ||
2150 | CONFIG_SOLARIS_X86_PARTITION=y | ||
2151 | CONFIG_UNIXWARE_DISKLABEL=y | ||
2152 | # CONFIG_LDM_PARTITION is not set | ||
2153 | # CONFIG_SGI_PARTITION is not set | ||
2154 | # CONFIG_ULTRIX_PARTITION is not set | ||
2155 | # CONFIG_SUN_PARTITION is not set | ||
2156 | # CONFIG_KARMA_PARTITION is not set | ||
2157 | CONFIG_EFI_PARTITION=y | ||
2158 | # CONFIG_SYSV68_PARTITION is not set | ||
2159 | CONFIG_NLS=y | ||
2160 | CONFIG_NLS_DEFAULT="iso8859-1" | ||
2161 | CONFIG_NLS_CODEPAGE_437=y | ||
2162 | CONFIG_NLS_CODEPAGE_737=m | ||
2163 | CONFIG_NLS_CODEPAGE_775=m | ||
2164 | CONFIG_NLS_CODEPAGE_850=m | ||
2165 | CONFIG_NLS_CODEPAGE_852=m | ||
2166 | CONFIG_NLS_CODEPAGE_855=m | ||
2167 | CONFIG_NLS_CODEPAGE_857=m | ||
2168 | CONFIG_NLS_CODEPAGE_860=m | ||
2169 | CONFIG_NLS_CODEPAGE_861=m | ||
2170 | CONFIG_NLS_CODEPAGE_862=m | ||
2171 | CONFIG_NLS_CODEPAGE_863=m | ||
2172 | CONFIG_NLS_CODEPAGE_864=m | ||
2173 | CONFIG_NLS_CODEPAGE_865=m | ||
2174 | CONFIG_NLS_CODEPAGE_866=m | ||
2175 | CONFIG_NLS_CODEPAGE_869=m | ||
2176 | CONFIG_NLS_CODEPAGE_936=m | ||
2177 | CONFIG_NLS_CODEPAGE_950=m | ||
2178 | CONFIG_NLS_CODEPAGE_932=m | ||
2179 | CONFIG_NLS_CODEPAGE_949=m | ||
2180 | CONFIG_NLS_CODEPAGE_874=m | ||
2181 | CONFIG_NLS_ISO8859_8=m | ||
2182 | CONFIG_NLS_CODEPAGE_1250=m | ||
2183 | CONFIG_NLS_CODEPAGE_1251=m | ||
2184 | CONFIG_NLS_ASCII=m | ||
2185 | CONFIG_NLS_ISO8859_1=m | ||
2186 | CONFIG_NLS_ISO8859_2=m | ||
2187 | CONFIG_NLS_ISO8859_3=m | ||
2188 | CONFIG_NLS_ISO8859_4=m | ||
2189 | CONFIG_NLS_ISO8859_5=m | ||
2190 | CONFIG_NLS_ISO8859_6=m | ||
2191 | CONFIG_NLS_ISO8859_7=m | ||
2192 | CONFIG_NLS_ISO8859_9=m | ||
2193 | CONFIG_NLS_ISO8859_13=m | ||
2194 | CONFIG_NLS_ISO8859_14=m | ||
2195 | CONFIG_NLS_ISO8859_15=m | ||
2196 | CONFIG_NLS_KOI8_R=m | ||
2197 | CONFIG_NLS_KOI8_U=m | ||
2198 | CONFIG_NLS_UTF8=y | ||
2199 | # CONFIG_DLM is not set | ||
2200 | |||
2201 | # | ||
2202 | # Kernel hacking | ||
2203 | # | ||
2204 | CONFIG_PRINTK_TIME=y | ||
2205 | CONFIG_ENABLE_WARN_DEPRECATED=y | ||
2206 | CONFIG_ENABLE_MUST_CHECK=y | ||
2207 | CONFIG_FRAME_WARN=1024 | ||
2208 | CONFIG_MAGIC_SYSRQ=y | ||
2209 | # CONFIG_STRIP_ASM_SYMS is not set | ||
2210 | # CONFIG_UNUSED_SYMBOLS is not set | ||
2211 | CONFIG_DEBUG_FS=y | ||
2212 | # CONFIG_HEADERS_CHECK is not set | ||
2213 | CONFIG_DEBUG_KERNEL=y | ||
2214 | # CONFIG_DEBUG_SHIRQ is not set | ||
2215 | CONFIG_DETECT_SOFTLOCKUP=y | ||
2216 | # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set | ||
2217 | CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 | ||
2218 | CONFIG_DETECT_HUNG_TASK=y | ||
2219 | # CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set | ||
2220 | CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 | ||
2221 | CONFIG_SCHED_DEBUG=y | ||
2222 | CONFIG_SCHEDSTATS=y | ||
2223 | CONFIG_TIMER_STATS=y | ||
2224 | # CONFIG_DEBUG_OBJECTS is not set | ||
2225 | # CONFIG_DEBUG_SLAB is not set | ||
2226 | # CONFIG_DEBUG_KMEMLEAK is not set | ||
2227 | CONFIG_DEBUG_PREEMPT=y | ||
2228 | # CONFIG_DEBUG_RT_MUTEXES is not set | ||
2229 | # CONFIG_RT_MUTEX_TESTER is not set | ||
2230 | # CONFIG_DEBUG_SPINLOCK is not set | ||
2231 | CONFIG_DEBUG_MUTEXES=y | ||
2232 | # CONFIG_DEBUG_LOCK_ALLOC is not set | ||
2233 | # CONFIG_PROVE_LOCKING is not set | ||
2234 | # CONFIG_LOCK_STAT is not set | ||
2235 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set | ||
2236 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set | ||
2237 | CONFIG_STACKTRACE=y | ||
2238 | # CONFIG_DEBUG_KOBJECT is not set | ||
2239 | # CONFIG_DEBUG_BUGVERBOSE is not set | ||
2240 | # CONFIG_DEBUG_INFO is not set | ||
2241 | # CONFIG_DEBUG_VM is not set | ||
2242 | # CONFIG_DEBUG_WRITECOUNT is not set | ||
2243 | # CONFIG_DEBUG_MEMORY_INIT is not set | ||
2244 | # CONFIG_DEBUG_LIST is not set | ||
2245 | # CONFIG_DEBUG_SG is not set | ||
2246 | # CONFIG_DEBUG_NOTIFIERS is not set | ||
2247 | # CONFIG_DEBUG_CREDENTIALS is not set | ||
2248 | # CONFIG_BOOT_PRINTK_DELAY is not set | ||
2249 | # CONFIG_RCU_TORTURE_TEST is not set | ||
2250 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
2251 | # CONFIG_BACKTRACE_SELF_TEST is not set | ||
2252 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set | ||
2253 | # CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set | ||
2254 | # CONFIG_FAULT_INJECTION is not set | ||
2255 | # CONFIG_LATENCYTOP is not set | ||
2256 | # CONFIG_PAGE_POISONING is not set | ||
2257 | CONFIG_NOP_TRACER=y | ||
2258 | CONFIG_HAVE_FUNCTION_TRACER=y | ||
2259 | CONFIG_RING_BUFFER=y | ||
2260 | CONFIG_EVENT_TRACING=y | ||
2261 | CONFIG_CONTEXT_SWITCH_TRACER=y | ||
2262 | CONFIG_RING_BUFFER_ALLOW_SWAP=y | ||
2263 | CONFIG_TRACING=y | ||
2264 | CONFIG_TRACING_SUPPORT=y | ||
2265 | CONFIG_FTRACE=y | ||
2266 | # CONFIG_FUNCTION_TRACER is not set | ||
2267 | # CONFIG_IRQSOFF_TRACER is not set | ||
2268 | # CONFIG_PREEMPT_TRACER is not set | ||
2269 | # CONFIG_SCHED_TRACER is not set | ||
2270 | # CONFIG_ENABLE_DEFAULT_TRACERS is not set | ||
2271 | # CONFIG_BOOT_TRACER is not set | ||
2272 | CONFIG_BRANCH_PROFILE_NONE=y | ||
2273 | # CONFIG_PROFILE_ANNOTATED_BRANCHES is not set | ||
2274 | # CONFIG_PROFILE_ALL_BRANCHES is not set | ||
2275 | # CONFIG_STACK_TRACER is not set | ||
2276 | # CONFIG_KMEMTRACE is not set | ||
2277 | # CONFIG_WORKQUEUE_TRACER is not set | ||
2278 | # CONFIG_BLK_DEV_IO_TRACE is not set | ||
2279 | # CONFIG_RING_BUFFER_BENCHMARK is not set | ||
2280 | # CONFIG_DYNAMIC_DEBUG is not set | ||
2281 | # CONFIG_SAMPLES is not set | ||
2282 | CONFIG_HAVE_ARCH_KGDB=y | ||
2283 | # CONFIG_KGDB is not set | ||
2284 | CONFIG_ARM_UNWIND=y | ||
2285 | # CONFIG_DEBUG_USER is not set | ||
2286 | # CONFIG_DEBUG_ERRORS is not set | ||
2287 | # CONFIG_DEBUG_STACK_USAGE is not set | ||
2288 | # CONFIG_DEBUG_LL is not set | ||
2289 | |||
2290 | # | ||
2291 | # Security options | ||
2292 | # | ||
2293 | CONFIG_KEYS=y | ||
2294 | # CONFIG_KEYS_DEBUG_PROC_KEYS is not set | ||
2295 | # CONFIG_SECURITY is not set | ||
2296 | # CONFIG_SECURITYFS is not set | ||
2297 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set | ||
2298 | CONFIG_XOR_BLOCKS=m | ||
2299 | CONFIG_ASYNC_CORE=m | ||
2300 | CONFIG_ASYNC_MEMCPY=m | ||
2301 | CONFIG_ASYNC_XOR=m | ||
2302 | CONFIG_ASYNC_PQ=m | ||
2303 | CONFIG_ASYNC_RAID6_RECOV=m | ||
2304 | CONFIG_CRYPTO=y | ||
2305 | |||
2306 | # | ||
2307 | # Crypto core or helper | ||
2308 | # | ||
2309 | CONFIG_CRYPTO_FIPS=y | ||
2310 | CONFIG_CRYPTO_ALGAPI=y | ||
2311 | CONFIG_CRYPTO_ALGAPI2=y | ||
2312 | CONFIG_CRYPTO_AEAD=m | ||
2313 | CONFIG_CRYPTO_AEAD2=y | ||
2314 | CONFIG_CRYPTO_BLKCIPHER=y | ||
2315 | CONFIG_CRYPTO_BLKCIPHER2=y | ||
2316 | CONFIG_CRYPTO_HASH=y | ||
2317 | CONFIG_CRYPTO_HASH2=y | ||
2318 | CONFIG_CRYPTO_RNG=m | ||
2319 | CONFIG_CRYPTO_RNG2=y | ||
2320 | CONFIG_CRYPTO_PCOMP=y | ||
2321 | CONFIG_CRYPTO_MANAGER=y | ||
2322 | CONFIG_CRYPTO_MANAGER2=y | ||
2323 | CONFIG_CRYPTO_GF128MUL=m | ||
2324 | CONFIG_CRYPTO_NULL=m | ||
2325 | CONFIG_CRYPTO_WORKQUEUE=y | ||
2326 | CONFIG_CRYPTO_CRYPTD=m | ||
2327 | CONFIG_CRYPTO_AUTHENC=m | ||
2328 | CONFIG_CRYPTO_TEST=m | ||
2329 | |||
2330 | # | ||
2331 | # Authenticated Encryption with Associated Data | ||
2332 | # | ||
2333 | CONFIG_CRYPTO_CCM=m | ||
2334 | CONFIG_CRYPTO_GCM=m | ||
2335 | CONFIG_CRYPTO_SEQIV=m | ||
2336 | |||
2337 | # | ||
2338 | # Block modes | ||
2339 | # | ||
2340 | CONFIG_CRYPTO_CBC=y | ||
2341 | CONFIG_CRYPTO_CTR=m | ||
2342 | CONFIG_CRYPTO_CTS=m | ||
2343 | CONFIG_CRYPTO_ECB=y | ||
2344 | CONFIG_CRYPTO_LRW=m | ||
2345 | CONFIG_CRYPTO_PCBC=m | ||
2346 | CONFIG_CRYPTO_XTS=m | ||
2347 | |||
2348 | # | ||
2349 | # Hash modes | ||
2350 | # | ||
2351 | CONFIG_CRYPTO_HMAC=m | ||
2352 | CONFIG_CRYPTO_XCBC=m | ||
2353 | # CONFIG_CRYPTO_VMAC is not set | ||
2354 | |||
2355 | # | ||
2356 | # Digest | ||
2357 | # | ||
2358 | CONFIG_CRYPTO_CRC32C=y | ||
2359 | CONFIG_CRYPTO_GHASH=m | ||
2360 | CONFIG_CRYPTO_MD4=m | ||
2361 | CONFIG_CRYPTO_MD5=y | ||
2362 | CONFIG_CRYPTO_MICHAEL_MIC=y | ||
2363 | CONFIG_CRYPTO_RMD128=m | ||
2364 | CONFIG_CRYPTO_RMD160=m | ||
2365 | CONFIG_CRYPTO_RMD256=m | ||
2366 | CONFIG_CRYPTO_RMD320=m | ||
2367 | CONFIG_CRYPTO_SHA1=m | ||
2368 | CONFIG_CRYPTO_SHA256=m | ||
2369 | CONFIG_CRYPTO_SHA512=m | ||
2370 | CONFIG_CRYPTO_TGR192=m | ||
2371 | CONFIG_CRYPTO_WP512=m | ||
2372 | |||
2373 | # | ||
2374 | # Ciphers | ||
2375 | # | ||
2376 | CONFIG_CRYPTO_AES=y | ||
2377 | CONFIG_CRYPTO_ANUBIS=m | ||
2378 | CONFIG_CRYPTO_ARC4=y | ||
2379 | CONFIG_CRYPTO_BLOWFISH=m | ||
2380 | CONFIG_CRYPTO_CAMELLIA=m | ||
2381 | CONFIG_CRYPTO_CAST5=m | ||
2382 | CONFIG_CRYPTO_CAST6=m | ||
2383 | CONFIG_CRYPTO_DES=y | ||
2384 | CONFIG_CRYPTO_FCRYPT=m | ||
2385 | CONFIG_CRYPTO_KHAZAD=m | ||
2386 | CONFIG_CRYPTO_SALSA20=m | ||
2387 | CONFIG_CRYPTO_SEED=m | ||
2388 | CONFIG_CRYPTO_SERPENT=m | ||
2389 | CONFIG_CRYPTO_TEA=m | ||
2390 | CONFIG_CRYPTO_TWOFISH=m | ||
2391 | CONFIG_CRYPTO_TWOFISH_COMMON=m | ||
2392 | |||
2393 | # | ||
2394 | # Compression | ||
2395 | # | ||
2396 | CONFIG_CRYPTO_DEFLATE=y | ||
2397 | # CONFIG_CRYPTO_ZLIB is not set | ||
2398 | CONFIG_CRYPTO_LZO=y | ||
2399 | |||
2400 | # | ||
2401 | # Random Number Generation | ||
2402 | # | ||
2403 | CONFIG_CRYPTO_ANSI_CPRNG=m | ||
2404 | CONFIG_CRYPTO_HW=y | ||
2405 | CONFIG_BINARY_PRINTF=y | ||
2406 | |||
2407 | # | ||
2408 | # Library routines | ||
2409 | # | ||
2410 | CONFIG_BITREVERSE=y | ||
2411 | CONFIG_GENERIC_FIND_LAST_BIT=y | ||
2412 | CONFIG_CRC_CCITT=y | ||
2413 | CONFIG_CRC16=y | ||
2414 | CONFIG_CRC_T10DIF=y | ||
2415 | CONFIG_CRC_ITU_T=y | ||
2416 | CONFIG_CRC32=y | ||
2417 | CONFIG_CRC7=y | ||
2418 | CONFIG_LIBCRC32C=y | ||
2419 | CONFIG_ZLIB_INFLATE=y | ||
2420 | CONFIG_ZLIB_DEFLATE=y | ||
2421 | CONFIG_LZO_COMPRESS=y | ||
2422 | CONFIG_LZO_DECOMPRESS=y | ||
2423 | CONFIG_DECOMPRESS_GZIP=y | ||
2424 | CONFIG_TEXTSEARCH=y | ||
2425 | CONFIG_TEXTSEARCH_KMP=m | ||
2426 | CONFIG_TEXTSEARCH_BM=m | ||
2427 | CONFIG_TEXTSEARCH_FSM=m | ||
2428 | CONFIG_HAS_IOMEM=y | ||
2429 | CONFIG_HAS_IOPORT=y | ||
2430 | CONFIG_HAS_DMA=y | ||
2431 | CONFIG_NLATTR=y | ||
diff --git a/arch/arm/configs/omap_4430sdp_defconfig b/arch/arm/configs/omap_4430sdp_defconfig index a464ca332a23..2319113c86bf 100644 --- a/arch/arm/configs/omap_4430sdp_defconfig +++ b/arch/arm/configs/omap_4430sdp_defconfig | |||
@@ -1,26 +1,29 @@ | |||
1 | # | 1 | # |
2 | # Automatically generated make config: don't edit | 2 | # Automatically generated make config: don't edit |
3 | # Linux kernel version: 2.6.30-rc7 | 3 | # Linux kernel version: 2.6.32 |
4 | # Tue Jun 9 12:36:23 2009 | 4 | # Sun Dec 6 23:37:45 2009 |
5 | # | 5 | # |
6 | CONFIG_ARM=y | 6 | CONFIG_ARM=y |
7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y | 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y |
8 | CONFIG_GENERIC_GPIO=y | 8 | CONFIG_GENERIC_GPIO=y |
9 | CONFIG_GENERIC_TIME=y | 9 | CONFIG_GENERIC_TIME=y |
10 | CONFIG_GENERIC_CLOCKEVENTS=y | 10 | CONFIG_GENERIC_CLOCKEVENTS=y |
11 | CONFIG_MMU=y | 11 | CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y |
12 | CONFIG_GENERIC_HARDIRQS=y | 12 | CONFIG_GENERIC_HARDIRQS=y |
13 | CONFIG_STACKTRACE_SUPPORT=y | 13 | CONFIG_STACKTRACE_SUPPORT=y |
14 | CONFIG_LOCKDEP_SUPPORT=y | 14 | CONFIG_LOCKDEP_SUPPORT=y |
15 | CONFIG_TRACE_IRQFLAGS_SUPPORT=y | 15 | CONFIG_TRACE_IRQFLAGS_SUPPORT=y |
16 | CONFIG_HARDIRQS_SW_RESEND=y | 16 | CONFIG_HARDIRQS_SW_RESEND=y |
17 | CONFIG_GENERIC_IRQ_PROBE=y | 17 | CONFIG_GENERIC_IRQ_PROBE=y |
18 | CONFIG_GENERIC_LOCKBREAK=y | ||
18 | CONFIG_RWSEM_GENERIC_SPINLOCK=y | 19 | CONFIG_RWSEM_GENERIC_SPINLOCK=y |
20 | CONFIG_ARCH_HAS_CPUFREQ=y | ||
19 | CONFIG_GENERIC_HWEIGHT=y | 21 | CONFIG_GENERIC_HWEIGHT=y |
20 | CONFIG_GENERIC_CALIBRATE_DELAY=y | 22 | CONFIG_GENERIC_CALIBRATE_DELAY=y |
21 | CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y | 23 | CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y |
22 | CONFIG_VECTORS_BASE=0xffff0000 | 24 | CONFIG_VECTORS_BASE=0xffff0000 |
23 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | 25 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" |
26 | CONFIG_CONSTRUCTORS=y | ||
24 | 27 | ||
25 | # | 28 | # |
26 | # General setup | 29 | # General setup |
@@ -39,11 +42,12 @@ CONFIG_BSD_PROCESS_ACCT=y | |||
39 | # | 42 | # |
40 | # RCU Subsystem | 43 | # RCU Subsystem |
41 | # | 44 | # |
42 | CONFIG_CLASSIC_RCU=y | 45 | CONFIG_TREE_RCU=y |
43 | # CONFIG_TREE_RCU is not set | 46 | # CONFIG_TREE_PREEMPT_RCU is not set |
44 | # CONFIG_PREEMPT_RCU is not set | 47 | # CONFIG_RCU_TRACE is not set |
48 | CONFIG_RCU_FANOUT=32 | ||
49 | # CONFIG_RCU_FANOUT_EXACT is not set | ||
45 | # CONFIG_TREE_RCU_TRACE is not set | 50 | # CONFIG_TREE_RCU_TRACE is not set |
46 | # CONFIG_PREEMPT_RCU_TRACE is not set | ||
47 | # CONFIG_IKCONFIG is not set | 51 | # CONFIG_IKCONFIG is not set |
48 | CONFIG_LOG_BUF_SHIFT=14 | 52 | CONFIG_LOG_BUF_SHIFT=14 |
49 | CONFIG_GROUP_SCHED=y | 53 | CONFIG_GROUP_SCHED=y |
@@ -52,8 +56,7 @@ CONFIG_FAIR_GROUP_SCHED=y | |||
52 | CONFIG_USER_SCHED=y | 56 | CONFIG_USER_SCHED=y |
53 | # CONFIG_CGROUP_SCHED is not set | 57 | # CONFIG_CGROUP_SCHED is not set |
54 | # CONFIG_CGROUPS is not set | 58 | # CONFIG_CGROUPS is not set |
55 | # CONFIG_SYSFS_DEPRECATED=y is not set | 59 | # CONFIG_SYSFS_DEPRECATED_V2 is not set |
56 | # CONFIG_SYSFS_DEPRECATED_V2=y is not set | ||
57 | # CONFIG_RELAY is not set | 60 | # CONFIG_RELAY is not set |
58 | # CONFIG_NAMESPACES is not set | 61 | # CONFIG_NAMESPACES is not set |
59 | CONFIG_BLK_DEV_INITRD=y | 62 | CONFIG_BLK_DEV_INITRD=y |
@@ -70,7 +73,6 @@ CONFIG_UID16=y | |||
70 | CONFIG_KALLSYMS=y | 73 | CONFIG_KALLSYMS=y |
71 | # CONFIG_KALLSYMS_ALL is not set | 74 | # CONFIG_KALLSYMS_ALL is not set |
72 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | 75 | # CONFIG_KALLSYMS_EXTRA_PASS is not set |
73 | # CONFIG_STRIP_ASM_SYMS is not set | ||
74 | CONFIG_HOTPLUG=y | 76 | CONFIG_HOTPLUG=y |
75 | CONFIG_PRINTK=y | 77 | CONFIG_PRINTK=y |
76 | CONFIG_BUG=y | 78 | CONFIG_BUG=y |
@@ -83,6 +85,10 @@ CONFIG_TIMERFD=y | |||
83 | CONFIG_EVENTFD=y | 85 | CONFIG_EVENTFD=y |
84 | CONFIG_SHMEM=y | 86 | CONFIG_SHMEM=y |
85 | CONFIG_AIO=y | 87 | CONFIG_AIO=y |
88 | |||
89 | # | ||
90 | # Kernel Performance Events And Counters | ||
91 | # | ||
86 | CONFIG_VM_EVENT_COUNTERS=y | 92 | CONFIG_VM_EVENT_COUNTERS=y |
87 | CONFIG_SLUB_DEBUG=y | 93 | CONFIG_SLUB_DEBUG=y |
88 | CONFIG_COMPAT_BRK=y | 94 | CONFIG_COMPAT_BRK=y |
@@ -90,13 +96,16 @@ CONFIG_COMPAT_BRK=y | |||
90 | CONFIG_SLUB=y | 96 | CONFIG_SLUB=y |
91 | # CONFIG_SLOB is not set | 97 | # CONFIG_SLOB is not set |
92 | # CONFIG_PROFILING is not set | 98 | # CONFIG_PROFILING is not set |
93 | # CONFIG_MARKERS is not set | ||
94 | CONFIG_HAVE_OPROFILE=y | 99 | CONFIG_HAVE_OPROFILE=y |
95 | # CONFIG_KPROBES is not set | 100 | # CONFIG_KPROBES is not set |
96 | CONFIG_HAVE_KPROBES=y | 101 | CONFIG_HAVE_KPROBES=y |
97 | CONFIG_HAVE_KRETPROBES=y | 102 | CONFIG_HAVE_KRETPROBES=y |
98 | CONFIG_USE_GENERIC_SMP_HELPERS=y | 103 | CONFIG_USE_GENERIC_SMP_HELPERS=y |
99 | CONFIG_HAVE_CLK=y | 104 | CONFIG_HAVE_CLK=y |
105 | |||
106 | # | ||
107 | # GCOV-based kernel profiling | ||
108 | # | ||
100 | # CONFIG_SLOW_WORK is not set | 109 | # CONFIG_SLOW_WORK is not set |
101 | CONFIG_HAVE_GENERIC_DMA_COHERENT=y | 110 | CONFIG_HAVE_GENERIC_DMA_COHERENT=y |
102 | CONFIG_SLABINFO=y | 111 | CONFIG_SLABINFO=y |
@@ -110,7 +119,7 @@ CONFIG_MODVERSIONS=y | |||
110 | CONFIG_MODULE_SRCVERSION_ALL=y | 119 | CONFIG_MODULE_SRCVERSION_ALL=y |
111 | CONFIG_STOP_MACHINE=y | 120 | CONFIG_STOP_MACHINE=y |
112 | CONFIG_BLOCK=y | 121 | CONFIG_BLOCK=y |
113 | # CONFIG_LBD is not set | 122 | CONFIG_LBDAF=y |
114 | # CONFIG_BLK_DEV_BSG is not set | 123 | # CONFIG_BLK_DEV_BSG is not set |
115 | # CONFIG_BLK_DEV_INTEGRITY is not set | 124 | # CONFIG_BLK_DEV_INTEGRITY is not set |
116 | 125 | ||
@@ -131,6 +140,7 @@ CONFIG_DEFAULT_IOSCHED="anticipatory" | |||
131 | # | 140 | # |
132 | # System Type | 141 | # System Type |
133 | # | 142 | # |
143 | CONFIG_MMU=y | ||
134 | # CONFIG_ARCH_AAEC2000 is not set | 144 | # CONFIG_ARCH_AAEC2000 is not set |
135 | # CONFIG_ARCH_INTEGRATOR is not set | 145 | # CONFIG_ARCH_INTEGRATOR is not set |
136 | # CONFIG_ARCH_REALVIEW is not set | 146 | # CONFIG_ARCH_REALVIEW is not set |
@@ -142,8 +152,10 @@ CONFIG_DEFAULT_IOSCHED="anticipatory" | |||
142 | # CONFIG_ARCH_EP93XX is not set | 152 | # CONFIG_ARCH_EP93XX is not set |
143 | # CONFIG_ARCH_FOOTBRIDGE is not set | 153 | # CONFIG_ARCH_FOOTBRIDGE is not set |
144 | # CONFIG_ARCH_MXC is not set | 154 | # CONFIG_ARCH_MXC is not set |
155 | # CONFIG_ARCH_STMP3XXX is not set | ||
145 | # CONFIG_ARCH_NETX is not set | 156 | # CONFIG_ARCH_NETX is not set |
146 | # CONFIG_ARCH_H720X is not set | 157 | # CONFIG_ARCH_H720X is not set |
158 | # CONFIG_ARCH_NOMADIK is not set | ||
147 | # CONFIG_ARCH_IOP13XX is not set | 159 | # CONFIG_ARCH_IOP13XX is not set |
148 | # CONFIG_ARCH_IOP32X is not set | 160 | # CONFIG_ARCH_IOP32X is not set |
149 | # CONFIG_ARCH_IOP33X is not set | 161 | # CONFIG_ARCH_IOP33X is not set |
@@ -166,10 +178,13 @@ CONFIG_DEFAULT_IOSCHED="anticipatory" | |||
166 | # CONFIG_ARCH_SA1100 is not set | 178 | # CONFIG_ARCH_SA1100 is not set |
167 | # CONFIG_ARCH_S3C2410 is not set | 179 | # CONFIG_ARCH_S3C2410 is not set |
168 | # CONFIG_ARCH_S3C64XX is not set | 180 | # CONFIG_ARCH_S3C64XX is not set |
181 | # CONFIG_ARCH_S5PC1XX is not set | ||
169 | # CONFIG_ARCH_SHARK is not set | 182 | # CONFIG_ARCH_SHARK is not set |
170 | # CONFIG_ARCH_LH7A40X is not set | 183 | # CONFIG_ARCH_LH7A40X is not set |
184 | # CONFIG_ARCH_U300 is not set | ||
171 | # CONFIG_ARCH_DAVINCI is not set | 185 | # CONFIG_ARCH_DAVINCI is not set |
172 | CONFIG_ARCH_OMAP=y | 186 | CONFIG_ARCH_OMAP=y |
187 | # CONFIG_ARCH_BCMRING is not set | ||
173 | 188 | ||
174 | # | 189 | # |
175 | # TI OMAP Implementations | 190 | # TI OMAP Implementations |
@@ -190,9 +205,12 @@ CONFIG_ARCH_OMAP4=y | |||
190 | CONFIG_OMAP_32K_TIMER=y | 205 | CONFIG_OMAP_32K_TIMER=y |
191 | CONFIG_OMAP_32K_TIMER_HZ=128 | 206 | CONFIG_OMAP_32K_TIMER_HZ=128 |
192 | CONFIG_OMAP_DM_TIMER=y | 207 | CONFIG_OMAP_DM_TIMER=y |
193 | CONFIG_OMAP_LL_DEBUG_UART1=y | 208 | # CONFIG_OMAP_LL_DEBUG_UART1 is not set |
194 | # CONFIG_OMAP_LL_DEBUG_UART2 is not set | 209 | # CONFIG_OMAP_LL_DEBUG_UART2 is not set |
195 | # CONFIG_OMAP_LL_DEBUG_UART3 is not set | 210 | CONFIG_OMAP_LL_DEBUG_UART3=y |
211 | # CONFIG_OMAP_LL_DEBUG_NONE is not set | ||
212 | # CONFIG_OMAP_PM_NONE is not set | ||
213 | CONFIG_OMAP_PM_NOOP=y | ||
196 | 214 | ||
197 | # | 215 | # |
198 | # OMAP Board Type | 216 | # OMAP Board Type |
@@ -207,7 +225,7 @@ CONFIG_CPU_32v6K=y | |||
207 | CONFIG_CPU_V7=y | 225 | CONFIG_CPU_V7=y |
208 | CONFIG_CPU_32v7=y | 226 | CONFIG_CPU_32v7=y |
209 | CONFIG_CPU_ABRT_EV7=y | 227 | CONFIG_CPU_ABRT_EV7=y |
210 | CONFIG_CPU_PABRT_IFAR=y | 228 | CONFIG_CPU_PABRT_V7=y |
211 | CONFIG_CPU_CACHE_V7=y | 229 | CONFIG_CPU_CACHE_V7=y |
212 | CONFIG_CPU_CACHE_VIPT=y | 230 | CONFIG_CPU_CACHE_VIPT=y |
213 | CONFIG_CPU_COPY_V6=y | 231 | CONFIG_CPU_COPY_V6=y |
@@ -222,9 +240,10 @@ CONFIG_CPU_CP15_MMU=y | |||
222 | # CONFIG_ARM_THUMB is not set | 240 | # CONFIG_ARM_THUMB is not set |
223 | # CONFIG_ARM_THUMBEE is not set | 241 | # CONFIG_ARM_THUMBEE is not set |
224 | # CONFIG_CPU_ICACHE_DISABLE is not set | 242 | # CONFIG_CPU_ICACHE_DISABLE is not set |
225 | CONFIG_CPU_DCACHE_DISABLE=y | 243 | # CONFIG_CPU_DCACHE_DISABLE is not set |
226 | # CONFIG_CPU_BPREDICT_DISABLE is not set | 244 | # CONFIG_CPU_BPREDICT_DISABLE is not set |
227 | CONFIG_HAS_TLS_REG=y | 245 | CONFIG_HAS_TLS_REG=y |
246 | CONFIG_ARM_L1_CACHE_SHIFT=5 | ||
228 | # CONFIG_ARM_ERRATA_430973 is not set | 247 | # CONFIG_ARM_ERRATA_430973 is not set |
229 | # CONFIG_ARM_ERRATA_458693 is not set | 248 | # CONFIG_ARM_ERRATA_458693 is not set |
230 | # CONFIG_ARM_ERRATA_460075 is not set | 249 | # CONFIG_ARM_ERRATA_460075 is not set |
@@ -245,18 +264,20 @@ CONFIG_ARM_GIC=y | |||
245 | CONFIG_GENERIC_CLOCKEVENTS_BUILD=y | 264 | CONFIG_GENERIC_CLOCKEVENTS_BUILD=y |
246 | CONFIG_SMP=y | 265 | CONFIG_SMP=y |
247 | CONFIG_HAVE_ARM_SCU=y | 266 | CONFIG_HAVE_ARM_SCU=y |
248 | CONFIG_HAVE_ARM_TWD=y | ||
249 | CONFIG_VMSPLIT_3G=y | 267 | CONFIG_VMSPLIT_3G=y |
250 | # CONFIG_VMSPLIT_2G is not set | 268 | # CONFIG_VMSPLIT_2G is not set |
251 | # CONFIG_VMSPLIT_1G is not set | 269 | # CONFIG_VMSPLIT_1G is not set |
252 | CONFIG_PAGE_OFFSET=0xC0000000 | 270 | CONFIG_PAGE_OFFSET=0xC0000000 |
253 | CONFIG_NR_CPUS=2 | 271 | CONFIG_NR_CPUS=2 |
254 | # CONFIG_HOTPLUG_CPU is not set | 272 | # CONFIG_HOTPLUG_CPU is not set |
255 | CONFIG_LOCAL_TIMERS=y | 273 | # CONFIG_LOCAL_TIMERS is not set |
256 | # CONFIG_PREEMPT is not set | 274 | # CONFIG_PREEMPT_NONE is not set |
275 | # CONFIG_PREEMPT_VOLUNTARY is not set | ||
276 | CONFIG_PREEMPT=y | ||
257 | CONFIG_HZ=128 | 277 | CONFIG_HZ=128 |
278 | # CONFIG_THUMB2_KERNEL is not set | ||
258 | CONFIG_AEABI=y | 279 | CONFIG_AEABI=y |
259 | # CONFIG_OABI_COMPAT is not set | 280 | CONFIG_OABI_COMPAT=y |
260 | # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set | 281 | # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set |
261 | # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set | 282 | # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set |
262 | # CONFIG_HIGHMEM is not set | 283 | # CONFIG_HIGHMEM is not set |
@@ -271,10 +292,13 @@ CONFIG_SPLIT_PTLOCK_CPUS=4 | |||
271 | # CONFIG_PHYS_ADDR_T_64BIT is not set | 292 | # CONFIG_PHYS_ADDR_T_64BIT is not set |
272 | CONFIG_ZONE_DMA_FLAG=0 | 293 | CONFIG_ZONE_DMA_FLAG=0 |
273 | CONFIG_VIRT_TO_BUS=y | 294 | CONFIG_VIRT_TO_BUS=y |
274 | # CONFIG_UNEVICTABLE_LRU is not set | ||
275 | CONFIG_HAVE_MLOCK=y | 295 | CONFIG_HAVE_MLOCK=y |
296 | CONFIG_HAVE_MLOCKED_PAGE_BIT=y | ||
297 | # CONFIG_KSM is not set | ||
298 | CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 | ||
276 | # CONFIG_LEDS is not set | 299 | # CONFIG_LEDS is not set |
277 | CONFIG_ALIGNMENT_TRAP=y | 300 | CONFIG_ALIGNMENT_TRAP=y |
301 | # CONFIG_UACCESS_WITH_MEMCPY is not set | ||
278 | 302 | ||
279 | # | 303 | # |
280 | # Boot options | 304 | # Boot options |
@@ -298,9 +322,11 @@ CONFIG_CMDLINE="root=/dev/ram0 rw mem=128M console=ttyS0,115200n8 initrd=0x81600 | |||
298 | # | 322 | # |
299 | # At least one emulation must be selected | 323 | # At least one emulation must be selected |
300 | # | 324 | # |
325 | # CONFIG_FPE_NWFPE is not set | ||
326 | # CONFIG_FPE_FASTFPE is not set | ||
301 | CONFIG_VFP=y | 327 | CONFIG_VFP=y |
302 | CONFIG_VFPv3=y | 328 | CONFIG_VFPv3=y |
303 | # CONFIG_NEON is not set | 329 | CONFIG_NEON=y |
304 | 330 | ||
305 | # | 331 | # |
306 | # Userspace binary formats | 332 | # Userspace binary formats |
@@ -325,6 +351,7 @@ CONFIG_ARCH_SUSPEND_POSSIBLE=y | |||
325 | # Generic Driver Options | 351 | # Generic Driver Options |
326 | # | 352 | # |
327 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | 353 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" |
354 | # CONFIG_DEVTMPFS is not set | ||
328 | CONFIG_STANDALONE=y | 355 | CONFIG_STANDALONE=y |
329 | CONFIG_PREVENT_FIRMWARE_BUILD=y | 356 | CONFIG_PREVENT_FIRMWARE_BUILD=y |
330 | # CONFIG_FW_LOADER is not set | 357 | # CONFIG_FW_LOADER is not set |
@@ -342,6 +369,7 @@ CONFIG_BLK_DEV_RAM_COUNT=16 | |||
342 | CONFIG_BLK_DEV_RAM_SIZE=16384 | 369 | CONFIG_BLK_DEV_RAM_SIZE=16384 |
343 | # CONFIG_BLK_DEV_XIP is not set | 370 | # CONFIG_BLK_DEV_XIP is not set |
344 | # CONFIG_CDROM_PKTCDVD is not set | 371 | # CONFIG_CDROM_PKTCDVD is not set |
372 | # CONFIG_MG_DISK is not set | ||
345 | # CONFIG_MISC_DEVICES is not set | 373 | # CONFIG_MISC_DEVICES is not set |
346 | CONFIG_HAVE_IDE=y | 374 | CONFIG_HAVE_IDE=y |
347 | # CONFIG_IDE is not set | 375 | # CONFIG_IDE is not set |
@@ -355,6 +383,7 @@ CONFIG_HAVE_IDE=y | |||
355 | # CONFIG_SCSI_NETLINK is not set | 383 | # CONFIG_SCSI_NETLINK is not set |
356 | # CONFIG_ATA is not set | 384 | # CONFIG_ATA is not set |
357 | # CONFIG_MD is not set | 385 | # CONFIG_MD is not set |
386 | # CONFIG_PHONE is not set | ||
358 | 387 | ||
359 | # | 388 | # |
360 | # Input device support | 389 | # Input device support |
@@ -427,6 +456,11 @@ CONFIG_HW_RANDOM=y | |||
427 | # CONFIG_TCG_TPM is not set | 456 | # CONFIG_TCG_TPM is not set |
428 | # CONFIG_I2C is not set | 457 | # CONFIG_I2C is not set |
429 | # CONFIG_SPI is not set | 458 | # CONFIG_SPI is not set |
459 | |||
460 | # | ||
461 | # PPS support | ||
462 | # | ||
463 | # CONFIG_PPS is not set | ||
430 | CONFIG_ARCH_REQUIRE_GPIOLIB=y | 464 | CONFIG_ARCH_REQUIRE_GPIOLIB=y |
431 | CONFIG_GPIOLIB=y | 465 | CONFIG_GPIOLIB=y |
432 | # CONFIG_DEBUG_GPIO is not set | 466 | # CONFIG_DEBUG_GPIO is not set |
@@ -447,11 +481,14 @@ CONFIG_GPIOLIB=y | |||
447 | # | 481 | # |
448 | # SPI GPIO expanders: | 482 | # SPI GPIO expanders: |
449 | # | 483 | # |
484 | |||
485 | # | ||
486 | # AC97 GPIO expanders: | ||
487 | # | ||
450 | # CONFIG_W1 is not set | 488 | # CONFIG_W1 is not set |
451 | # CONFIG_POWER_SUPPLY is not set | 489 | # CONFIG_POWER_SUPPLY is not set |
452 | # CONFIG_HWMON is not set | 490 | # CONFIG_HWMON is not set |
453 | # CONFIG_THERMAL is not set | 491 | # CONFIG_THERMAL is not set |
454 | # CONFIG_THERMAL_HWMON is not set | ||
455 | # CONFIG_WATCHDOG is not set | 492 | # CONFIG_WATCHDOG is not set |
456 | CONFIG_SSB_POSSIBLE=y | 493 | CONFIG_SSB_POSSIBLE=y |
457 | 494 | ||
@@ -472,21 +509,8 @@ CONFIG_SSB_POSSIBLE=y | |||
472 | # CONFIG_MFD_T7L66XB is not set | 509 | # CONFIG_MFD_T7L66XB is not set |
473 | # CONFIG_MFD_TC6387XB is not set | 510 | # CONFIG_MFD_TC6387XB is not set |
474 | # CONFIG_MFD_TC6393XB is not set | 511 | # CONFIG_MFD_TC6393XB is not set |
475 | 512 | # CONFIG_REGULATOR is not set | |
476 | # | 513 | # CONFIG_MEDIA_SUPPORT is not set |
477 | # Multimedia devices | ||
478 | # | ||
479 | |||
480 | # | ||
481 | # Multimedia core support | ||
482 | # | ||
483 | # CONFIG_VIDEO_DEV is not set | ||
484 | # CONFIG_VIDEO_MEDIA is not set | ||
485 | |||
486 | # | ||
487 | # Multimedia drivers | ||
488 | # | ||
489 | CONFIG_DAB=y | ||
490 | 514 | ||
491 | # | 515 | # |
492 | # Graphics support | 516 | # Graphics support |
@@ -511,14 +535,17 @@ CONFIG_DUMMY_CONSOLE=y | |||
511 | # CONFIG_USB_SUPPORT is not set | 535 | # CONFIG_USB_SUPPORT is not set |
512 | # CONFIG_MMC is not set | 536 | # CONFIG_MMC is not set |
513 | # CONFIG_MEMSTICK is not set | 537 | # CONFIG_MEMSTICK is not set |
514 | # CONFIG_ACCESSIBILITY is not set | ||
515 | # CONFIG_NEW_LEDS is not set | 538 | # CONFIG_NEW_LEDS is not set |
539 | # CONFIG_ACCESSIBILITY is not set | ||
516 | CONFIG_RTC_LIB=y | 540 | CONFIG_RTC_LIB=y |
517 | # CONFIG_RTC_CLASS is not set | 541 | # CONFIG_RTC_CLASS is not set |
518 | # CONFIG_DMADEVICES is not set | 542 | # CONFIG_DMADEVICES is not set |
519 | # CONFIG_AUXDISPLAY is not set | 543 | # CONFIG_AUXDISPLAY is not set |
520 | # CONFIG_REGULATOR is not set | ||
521 | # CONFIG_UIO is not set | 544 | # CONFIG_UIO is not set |
545 | |||
546 | # | ||
547 | # TI VLYNQ | ||
548 | # | ||
522 | # CONFIG_STAGING is not set | 549 | # CONFIG_STAGING is not set |
523 | 550 | ||
524 | # | 551 | # |
@@ -535,9 +562,12 @@ CONFIG_JBD=y | |||
535 | # CONFIG_REISERFS_FS is not set | 562 | # CONFIG_REISERFS_FS is not set |
536 | # CONFIG_JFS_FS is not set | 563 | # CONFIG_JFS_FS is not set |
537 | # CONFIG_FS_POSIX_ACL is not set | 564 | # CONFIG_FS_POSIX_ACL is not set |
538 | CONFIG_FILE_LOCKING=y | ||
539 | # CONFIG_XFS_FS is not set | 565 | # CONFIG_XFS_FS is not set |
566 | # CONFIG_GFS2_FS is not set | ||
540 | # CONFIG_BTRFS_FS is not set | 567 | # CONFIG_BTRFS_FS is not set |
568 | # CONFIG_NILFS2_FS is not set | ||
569 | CONFIG_FILE_LOCKING=y | ||
570 | CONFIG_FSNOTIFY=y | ||
541 | CONFIG_DNOTIFY=y | 571 | CONFIG_DNOTIFY=y |
542 | CONFIG_INOTIFY=y | 572 | CONFIG_INOTIFY=y |
543 | CONFIG_INOTIFY_USER=y | 573 | CONFIG_INOTIFY_USER=y |
@@ -601,7 +631,6 @@ CONFIG_MISC_FILESYSTEMS=y | |||
601 | # CONFIG_ROMFS_FS is not set | 631 | # CONFIG_ROMFS_FS is not set |
602 | # CONFIG_SYSV_FS is not set | 632 | # CONFIG_SYSV_FS is not set |
603 | # CONFIG_UFS_FS is not set | 633 | # CONFIG_UFS_FS is not set |
604 | # CONFIG_NILFS2_FS is not set | ||
605 | 634 | ||
606 | # | 635 | # |
607 | # Partition Types | 636 | # Partition Types |
@@ -673,23 +702,24 @@ CONFIG_NLS_ISO8859_1=y | |||
673 | # CONFIG_ENABLE_MUST_CHECK is not set | 702 | # CONFIG_ENABLE_MUST_CHECK is not set |
674 | CONFIG_FRAME_WARN=1024 | 703 | CONFIG_FRAME_WARN=1024 |
675 | CONFIG_MAGIC_SYSRQ=y | 704 | CONFIG_MAGIC_SYSRQ=y |
705 | # CONFIG_STRIP_ASM_SYMS is not set | ||
676 | # CONFIG_UNUSED_SYMBOLS is not set | 706 | # CONFIG_UNUSED_SYMBOLS is not set |
677 | # CONFIG_DEBUG_FS is not set | 707 | # CONFIG_DEBUG_FS is not set |
678 | # CONFIG_HEADERS_CHECK is not set | 708 | # CONFIG_HEADERS_CHECK is not set |
679 | CONFIG_DEBUG_KERNEL=y | 709 | CONFIG_DEBUG_KERNEL=y |
680 | # CONFIG_DEBUG_SHIRQ is not set | 710 | # CONFIG_DEBUG_SHIRQ is not set |
681 | CONFIG_DETECT_SOFTLOCKUP=y | 711 | # CONFIG_DETECT_SOFTLOCKUP is not set |
682 | # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set | ||
683 | CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 | ||
684 | CONFIG_DETECT_HUNG_TASK=y | 712 | CONFIG_DETECT_HUNG_TASK=y |
685 | # CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set | 713 | # CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set |
686 | CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 | 714 | CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 |
687 | CONFIG_SCHED_DEBUG=y | 715 | # CONFIG_SCHED_DEBUG is not set |
688 | # CONFIG_SCHEDSTATS is not set | 716 | # CONFIG_SCHEDSTATS is not set |
689 | # CONFIG_TIMER_STATS is not set | 717 | # CONFIG_TIMER_STATS is not set |
690 | # CONFIG_DEBUG_OBJECTS is not set | 718 | # CONFIG_DEBUG_OBJECTS is not set |
691 | # CONFIG_SLUB_DEBUG_ON is not set | 719 | # CONFIG_SLUB_DEBUG_ON is not set |
692 | # CONFIG_SLUB_STATS is not set | 720 | # CONFIG_SLUB_STATS is not set |
721 | # CONFIG_DEBUG_KMEMLEAK is not set | ||
722 | # CONFIG_DEBUG_PREEMPT is not set | ||
693 | # CONFIG_DEBUG_RT_MUTEXES is not set | 723 | # CONFIG_DEBUG_RT_MUTEXES is not set |
694 | # CONFIG_RT_MUTEX_TESTER is not set | 724 | # CONFIG_RT_MUTEX_TESTER is not set |
695 | # CONFIG_DEBUG_SPINLOCK is not set | 725 | # CONFIG_DEBUG_SPINLOCK is not set |
@@ -708,31 +738,22 @@ CONFIG_DEBUG_INFO=y | |||
708 | # CONFIG_DEBUG_LIST is not set | 738 | # CONFIG_DEBUG_LIST is not set |
709 | # CONFIG_DEBUG_SG is not set | 739 | # CONFIG_DEBUG_SG is not set |
710 | # CONFIG_DEBUG_NOTIFIERS is not set | 740 | # CONFIG_DEBUG_NOTIFIERS is not set |
741 | # CONFIG_DEBUG_CREDENTIALS is not set | ||
711 | CONFIG_FRAME_POINTER=y | 742 | CONFIG_FRAME_POINTER=y |
712 | # CONFIG_BOOT_PRINTK_DELAY is not set | 743 | # CONFIG_BOOT_PRINTK_DELAY is not set |
713 | # CONFIG_RCU_TORTURE_TEST is not set | 744 | # CONFIG_RCU_TORTURE_TEST is not set |
714 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | 745 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set |
715 | # CONFIG_BACKTRACE_SELF_TEST is not set | 746 | # CONFIG_BACKTRACE_SELF_TEST is not set |
716 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set | 747 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set |
748 | # CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set | ||
717 | # CONFIG_FAULT_INJECTION is not set | 749 | # CONFIG_FAULT_INJECTION is not set |
718 | # CONFIG_PAGE_POISONING is not set | 750 | # CONFIG_PAGE_POISONING is not set |
719 | CONFIG_HAVE_FUNCTION_TRACER=y | 751 | CONFIG_HAVE_FUNCTION_TRACER=y |
720 | CONFIG_TRACING_SUPPORT=y | 752 | CONFIG_TRACING_SUPPORT=y |
721 | 753 | # CONFIG_FTRACE is not set | |
722 | # | 754 | # CONFIG_BRANCH_PROFILE_NONE is not set |
723 | # Tracers | 755 | # CONFIG_PROFILE_ANNOTATED_BRANCHES is not set |
724 | # | 756 | # CONFIG_PROFILE_ALL_BRANCHES is not set |
725 | # CONFIG_FUNCTION_TRACER is not set | ||
726 | # CONFIG_IRQSOFF_TRACER is not set | ||
727 | # CONFIG_SCHED_TRACER is not set | ||
728 | # CONFIG_CONTEXT_SWITCH_TRACER is not set | ||
729 | # CONFIG_EVENT_TRACER is not set | ||
730 | # CONFIG_BOOT_TRACER is not set | ||
731 | # CONFIG_TRACE_BRANCH_PROFILING is not set | ||
732 | # CONFIG_STACK_TRACER is not set | ||
733 | # CONFIG_KMEMTRACE is not set | ||
734 | # CONFIG_WORKQUEUE_TRACER is not set | ||
735 | # CONFIG_BLK_DEV_IO_TRACE is not set | ||
736 | # CONFIG_SAMPLES is not set | 757 | # CONFIG_SAMPLES is not set |
737 | CONFIG_HAVE_ARCH_KGDB=y | 758 | CONFIG_HAVE_ARCH_KGDB=y |
738 | # CONFIG_KGDB is not set | 759 | # CONFIG_KGDB is not set |
@@ -754,7 +775,6 @@ CONFIG_CRYPTO=y | |||
754 | # | 775 | # |
755 | # Crypto core or helper | 776 | # Crypto core or helper |
756 | # | 777 | # |
757 | # CONFIG_CRYPTO_FIPS is not set | ||
758 | CONFIG_CRYPTO_ALGAPI=y | 778 | CONFIG_CRYPTO_ALGAPI=y |
759 | CONFIG_CRYPTO_ALGAPI2=y | 779 | CONFIG_CRYPTO_ALGAPI2=y |
760 | CONFIG_CRYPTO_AEAD2=y | 780 | CONFIG_CRYPTO_AEAD2=y |
@@ -796,11 +816,13 @@ CONFIG_CRYPTO_PCBC=m | |||
796 | # | 816 | # |
797 | # CONFIG_CRYPTO_HMAC is not set | 817 | # CONFIG_CRYPTO_HMAC is not set |
798 | # CONFIG_CRYPTO_XCBC is not set | 818 | # CONFIG_CRYPTO_XCBC is not set |
819 | # CONFIG_CRYPTO_VMAC is not set | ||
799 | 820 | ||
800 | # | 821 | # |
801 | # Digest | 822 | # Digest |
802 | # | 823 | # |
803 | CONFIG_CRYPTO_CRC32C=y | 824 | CONFIG_CRYPTO_CRC32C=y |
825 | # CONFIG_CRYPTO_GHASH is not set | ||
804 | # CONFIG_CRYPTO_MD4 is not set | 826 | # CONFIG_CRYPTO_MD4 is not set |
805 | CONFIG_CRYPTO_MD5=y | 827 | CONFIG_CRYPTO_MD5=y |
806 | # CONFIG_CRYPTO_MICHAEL_MIC is not set | 828 | # CONFIG_CRYPTO_MICHAEL_MIC is not set |
diff --git a/arch/arm/configs/omap_zoom2_defconfig b/arch/arm/configs/omap_zoom2_defconfig index eef93627fb13..4b00a4306812 100644 --- a/arch/arm/configs/omap_zoom2_defconfig +++ b/arch/arm/configs/omap_zoom2_defconfig | |||
@@ -610,7 +610,8 @@ CONFIG_INPUT_EVDEV=y | |||
610 | # | 610 | # |
611 | # Input Device Drivers | 611 | # Input Device Drivers |
612 | # | 612 | # |
613 | # CONFIG_INPUT_KEYBOARD is not set | 613 | CONFIG_INPUT_KEYBOARD=y |
614 | CONFIG_KEYBOARD_TWL4030=y | ||
614 | # CONFIG_INPUT_MOUSE is not set | 615 | # CONFIG_INPUT_MOUSE is not set |
615 | # CONFIG_INPUT_JOYSTICK is not set | 616 | # CONFIG_INPUT_JOYSTICK is not set |
616 | # CONFIG_INPUT_TABLET is not set | 617 | # CONFIG_INPUT_TABLET is not set |
diff --git a/arch/arm/configs/omap_zoom3_defconfig b/arch/arm/configs/omap_zoom3_defconfig index f0e7d0f85582..0d7e37a3651b 100644 --- a/arch/arm/configs/omap_zoom3_defconfig +++ b/arch/arm/configs/omap_zoom3_defconfig | |||
@@ -629,7 +629,8 @@ CONFIG_INPUT_EVDEV=y | |||
629 | # | 629 | # |
630 | # Input Device Drivers | 630 | # Input Device Drivers |
631 | # | 631 | # |
632 | # CONFIG_INPUT_KEYBOARD is not set | 632 | CONFIG_INPUT_KEYBOARD=y |
633 | CONFIG_KEYBOARD_TWL4030=y | ||
633 | # CONFIG_INPUT_MOUSE is not set | 634 | # CONFIG_INPUT_MOUSE is not set |
634 | # CONFIG_INPUT_JOYSTICK is not set | 635 | # CONFIG_INPUT_JOYSTICK is not set |
635 | # CONFIG_INPUT_TABLET is not set | 636 | # CONFIG_INPUT_TABLET is not set |
diff --git a/arch/arm/configs/zeus_defconfig b/arch/arm/configs/zeus_defconfig new file mode 100644 index 000000000000..823b11e7091a --- /dev/null +++ b/arch/arm/configs/zeus_defconfig | |||
@@ -0,0 +1,2032 @@ | |||
1 | # | ||
2 | # Automatically generated make config: don't edit | ||
3 | # Linux kernel version: 2.6.32 | ||
4 | # Tue Dec 8 20:27:05 2009 | ||
5 | # | ||
6 | CONFIG_ARM=y | ||
7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y | ||
8 | CONFIG_GENERIC_GPIO=y | ||
9 | CONFIG_GENERIC_TIME=y | ||
10 | CONFIG_GENERIC_CLOCKEVENTS=y | ||
11 | CONFIG_GENERIC_HARDIRQS=y | ||
12 | CONFIG_STACKTRACE_SUPPORT=y | ||
13 | CONFIG_HAVE_LATENCYTOP_SUPPORT=y | ||
14 | CONFIG_LOCKDEP_SUPPORT=y | ||
15 | CONFIG_TRACE_IRQFLAGS_SUPPORT=y | ||
16 | CONFIG_HARDIRQS_SW_RESEND=y | ||
17 | CONFIG_GENERIC_IRQ_PROBE=y | ||
18 | CONFIG_RWSEM_GENERIC_SPINLOCK=y | ||
19 | CONFIG_ARCH_HAS_CPUFREQ=y | ||
20 | CONFIG_GENERIC_HWEIGHT=y | ||
21 | CONFIG_GENERIC_CALIBRATE_DELAY=y | ||
22 | CONFIG_ARCH_MTD_XIP=y | ||
23 | CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y | ||
24 | CONFIG_VECTORS_BASE=0xffff0000 | ||
25 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | ||
26 | CONFIG_CONSTRUCTORS=y | ||
27 | |||
28 | # | ||
29 | # General setup | ||
30 | # | ||
31 | CONFIG_EXPERIMENTAL=y | ||
32 | CONFIG_BROKEN_ON_SMP=y | ||
33 | CONFIG_INIT_ENV_ARG_LIMIT=32 | ||
34 | CONFIG_LOCALVERSION="" | ||
35 | CONFIG_LOCALVERSION_AUTO=y | ||
36 | CONFIG_SWAP=y | ||
37 | CONFIG_SYSVIPC=y | ||
38 | CONFIG_SYSVIPC_SYSCTL=y | ||
39 | # CONFIG_POSIX_MQUEUE is not set | ||
40 | # CONFIG_BSD_PROCESS_ACCT is not set | ||
41 | # CONFIG_TASKSTATS is not set | ||
42 | # CONFIG_AUDIT is not set | ||
43 | |||
44 | # | ||
45 | # RCU Subsystem | ||
46 | # | ||
47 | # CONFIG_TREE_RCU is not set | ||
48 | # CONFIG_TREE_PREEMPT_RCU is not set | ||
49 | CONFIG_TINY_RCU=y | ||
50 | # CONFIG_TREE_RCU_TRACE is not set | ||
51 | # CONFIG_IKCONFIG is not set | ||
52 | CONFIG_LOG_BUF_SHIFT=13 | ||
53 | # CONFIG_GROUP_SCHED is not set | ||
54 | # CONFIG_CGROUPS is not set | ||
55 | # CONFIG_SYSFS_DEPRECATED_V2 is not set | ||
56 | # CONFIG_RELAY is not set | ||
57 | CONFIG_NAMESPACES=y | ||
58 | # CONFIG_UTS_NS is not set | ||
59 | # CONFIG_IPC_NS is not set | ||
60 | # CONFIG_USER_NS is not set | ||
61 | # CONFIG_PID_NS is not set | ||
62 | # CONFIG_NET_NS is not set | ||
63 | # CONFIG_BLK_DEV_INITRD is not set | ||
64 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y | ||
65 | CONFIG_SYSCTL=y | ||
66 | CONFIG_ANON_INODES=y | ||
67 | # CONFIG_EMBEDDED is not set | ||
68 | CONFIG_UID16=y | ||
69 | CONFIG_SYSCTL_SYSCALL=y | ||
70 | CONFIG_KALLSYMS=y | ||
71 | # CONFIG_KALLSYMS_ALL is not set | ||
72 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | ||
73 | CONFIG_HOTPLUG=y | ||
74 | CONFIG_PRINTK=y | ||
75 | CONFIG_BUG=y | ||
76 | CONFIG_ELF_CORE=y | ||
77 | CONFIG_BASE_FULL=y | ||
78 | CONFIG_FUTEX=y | ||
79 | CONFIG_EPOLL=y | ||
80 | CONFIG_SIGNALFD=y | ||
81 | CONFIG_TIMERFD=y | ||
82 | CONFIG_EVENTFD=y | ||
83 | CONFIG_SHMEM=y | ||
84 | CONFIG_AIO=y | ||
85 | |||
86 | # | ||
87 | # Kernel Performance Events And Counters | ||
88 | # | ||
89 | CONFIG_VM_EVENT_COUNTERS=y | ||
90 | CONFIG_SLUB_DEBUG=y | ||
91 | CONFIG_COMPAT_BRK=y | ||
92 | # CONFIG_SLAB is not set | ||
93 | CONFIG_SLUB=y | ||
94 | # CONFIG_SLOB is not set | ||
95 | # CONFIG_PROFILING is not set | ||
96 | CONFIG_HAVE_OPROFILE=y | ||
97 | # CONFIG_KPROBES is not set | ||
98 | CONFIG_HAVE_KPROBES=y | ||
99 | CONFIG_HAVE_KRETPROBES=y | ||
100 | CONFIG_HAVE_CLK=y | ||
101 | |||
102 | # | ||
103 | # GCOV-based kernel profiling | ||
104 | # | ||
105 | # CONFIG_SLOW_WORK is not set | ||
106 | CONFIG_HAVE_GENERIC_DMA_COHERENT=y | ||
107 | CONFIG_SLABINFO=y | ||
108 | CONFIG_RT_MUTEXES=y | ||
109 | CONFIG_BASE_SMALL=0 | ||
110 | CONFIG_MODULES=y | ||
111 | # CONFIG_MODULE_FORCE_LOAD is not set | ||
112 | CONFIG_MODULE_UNLOAD=y | ||
113 | # CONFIG_MODULE_FORCE_UNLOAD is not set | ||
114 | # CONFIG_MODVERSIONS is not set | ||
115 | # CONFIG_MODULE_SRCVERSION_ALL is not set | ||
116 | CONFIG_BLOCK=y | ||
117 | CONFIG_LBDAF=y | ||
118 | # CONFIG_BLK_DEV_BSG is not set | ||
119 | # CONFIG_BLK_DEV_INTEGRITY is not set | ||
120 | |||
121 | # | ||
122 | # IO Schedulers | ||
123 | # | ||
124 | CONFIG_IOSCHED_NOOP=y | ||
125 | CONFIG_IOSCHED_DEADLINE=y | ||
126 | # CONFIG_IOSCHED_CFQ is not set | ||
127 | CONFIG_DEFAULT_DEADLINE=y | ||
128 | # CONFIG_DEFAULT_CFQ is not set | ||
129 | # CONFIG_DEFAULT_NOOP is not set | ||
130 | CONFIG_DEFAULT_IOSCHED="deadline" | ||
131 | # CONFIG_INLINE_SPIN_TRYLOCK is not set | ||
132 | # CONFIG_INLINE_SPIN_TRYLOCK_BH is not set | ||
133 | # CONFIG_INLINE_SPIN_LOCK is not set | ||
134 | # CONFIG_INLINE_SPIN_LOCK_BH is not set | ||
135 | # CONFIG_INLINE_SPIN_LOCK_IRQ is not set | ||
136 | # CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set | ||
137 | CONFIG_INLINE_SPIN_UNLOCK=y | ||
138 | # CONFIG_INLINE_SPIN_UNLOCK_BH is not set | ||
139 | CONFIG_INLINE_SPIN_UNLOCK_IRQ=y | ||
140 | # CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set | ||
141 | # CONFIG_INLINE_READ_TRYLOCK is not set | ||
142 | # CONFIG_INLINE_READ_LOCK is not set | ||
143 | # CONFIG_INLINE_READ_LOCK_BH is not set | ||
144 | # CONFIG_INLINE_READ_LOCK_IRQ is not set | ||
145 | # CONFIG_INLINE_READ_LOCK_IRQSAVE is not set | ||
146 | CONFIG_INLINE_READ_UNLOCK=y | ||
147 | # CONFIG_INLINE_READ_UNLOCK_BH is not set | ||
148 | CONFIG_INLINE_READ_UNLOCK_IRQ=y | ||
149 | # CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set | ||
150 | # CONFIG_INLINE_WRITE_TRYLOCK is not set | ||
151 | # CONFIG_INLINE_WRITE_LOCK is not set | ||
152 | # CONFIG_INLINE_WRITE_LOCK_BH is not set | ||
153 | # CONFIG_INLINE_WRITE_LOCK_IRQ is not set | ||
154 | # CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set | ||
155 | CONFIG_INLINE_WRITE_UNLOCK=y | ||
156 | # CONFIG_INLINE_WRITE_UNLOCK_BH is not set | ||
157 | CONFIG_INLINE_WRITE_UNLOCK_IRQ=y | ||
158 | # CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set | ||
159 | # CONFIG_MUTEX_SPIN_ON_OWNER is not set | ||
160 | CONFIG_FREEZER=y | ||
161 | |||
162 | # | ||
163 | # System Type | ||
164 | # | ||
165 | CONFIG_MMU=y | ||
166 | # CONFIG_ARCH_AAEC2000 is not set | ||
167 | # CONFIG_ARCH_INTEGRATOR is not set | ||
168 | # CONFIG_ARCH_REALVIEW is not set | ||
169 | # CONFIG_ARCH_VERSATILE is not set | ||
170 | # CONFIG_ARCH_AT91 is not set | ||
171 | # CONFIG_ARCH_CLPS711X is not set | ||
172 | # CONFIG_ARCH_GEMINI is not set | ||
173 | # CONFIG_ARCH_EBSA110 is not set | ||
174 | # CONFIG_ARCH_EP93XX is not set | ||
175 | # CONFIG_ARCH_FOOTBRIDGE is not set | ||
176 | # CONFIG_ARCH_MXC is not set | ||
177 | # CONFIG_ARCH_STMP3XXX is not set | ||
178 | # CONFIG_ARCH_NETX is not set | ||
179 | # CONFIG_ARCH_H720X is not set | ||
180 | # CONFIG_ARCH_NOMADIK is not set | ||
181 | # CONFIG_ARCH_IOP13XX is not set | ||
182 | # CONFIG_ARCH_IOP32X is not set | ||
183 | # CONFIG_ARCH_IOP33X is not set | ||
184 | # CONFIG_ARCH_IXP23XX is not set | ||
185 | # CONFIG_ARCH_IXP2000 is not set | ||
186 | # CONFIG_ARCH_IXP4XX is not set | ||
187 | # CONFIG_ARCH_L7200 is not set | ||
188 | # CONFIG_ARCH_DOVE is not set | ||
189 | # CONFIG_ARCH_KIRKWOOD is not set | ||
190 | # CONFIG_ARCH_LOKI is not set | ||
191 | # CONFIG_ARCH_MV78XX0 is not set | ||
192 | # CONFIG_ARCH_ORION5X is not set | ||
193 | # CONFIG_ARCH_MMP is not set | ||
194 | # CONFIG_ARCH_KS8695 is not set | ||
195 | # CONFIG_ARCH_NS9XXX is not set | ||
196 | # CONFIG_ARCH_W90X900 is not set | ||
197 | # CONFIG_ARCH_PNX4008 is not set | ||
198 | CONFIG_ARCH_PXA=y | ||
199 | # CONFIG_ARCH_MSM is not set | ||
200 | # CONFIG_ARCH_RPC is not set | ||
201 | # CONFIG_ARCH_SA1100 is not set | ||
202 | # CONFIG_ARCH_S3C2410 is not set | ||
203 | # CONFIG_ARCH_S3C64XX is not set | ||
204 | # CONFIG_ARCH_S5PC1XX is not set | ||
205 | # CONFIG_ARCH_SHARK is not set | ||
206 | # CONFIG_ARCH_LH7A40X is not set | ||
207 | # CONFIG_ARCH_U300 is not set | ||
208 | # CONFIG_ARCH_DAVINCI is not set | ||
209 | # CONFIG_ARCH_OMAP is not set | ||
210 | # CONFIG_ARCH_BCMRING is not set | ||
211 | # CONFIG_ARCH_U8500 is not set | ||
212 | |||
213 | # | ||
214 | # Intel PXA2xx/PXA3xx Implementations | ||
215 | # | ||
216 | |||
217 | # | ||
218 | # Intel/Marvell Dev Platforms (sorted by hardware release time) | ||
219 | # | ||
220 | # CONFIG_ARCH_LUBBOCK is not set | ||
221 | # CONFIG_MACH_MAINSTONE is not set | ||
222 | # CONFIG_MACH_ZYLONITE300 is not set | ||
223 | # CONFIG_MACH_ZYLONITE320 is not set | ||
224 | # CONFIG_MACH_LITTLETON is not set | ||
225 | # CONFIG_MACH_TAVOREVB is not set | ||
226 | # CONFIG_MACH_SAAR is not set | ||
227 | |||
228 | # | ||
229 | # Third Party Dev Platforms (sorted by vendor name) | ||
230 | # | ||
231 | # CONFIG_ARCH_PXA_IDP is not set | ||
232 | # CONFIG_ARCH_VIPER is not set | ||
233 | CONFIG_MACH_ARCOM_ZEUS=y | ||
234 | # CONFIG_MACH_BALLOON3 is not set | ||
235 | # CONFIG_MACH_CSB726 is not set | ||
236 | # CONFIG_MACH_ARMCORE is not set | ||
237 | # CONFIG_MACH_EM_X270 is not set | ||
238 | # CONFIG_MACH_EXEDA is not set | ||
239 | # CONFIG_MACH_CM_X300 is not set | ||
240 | # CONFIG_ARCH_GUMSTIX is not set | ||
241 | # CONFIG_MACH_INTELMOTE2 is not set | ||
242 | # CONFIG_MACH_STARGATE2 is not set | ||
243 | # CONFIG_MACH_XCEP is not set | ||
244 | # CONFIG_TRIZEPS_PXA is not set | ||
245 | CONFIG_ARCOM_PCMCIA=y | ||
246 | # CONFIG_MACH_LOGICPD_PXA270 is not set | ||
247 | # CONFIG_MACH_PCM027 is not set | ||
248 | # CONFIG_MACH_COLIBRI is not set | ||
249 | # CONFIG_MACH_COLIBRI300 is not set | ||
250 | # CONFIG_MACH_COLIBRI320 is not set | ||
251 | |||
252 | # | ||
253 | # End-user Products (sorted by vendor name) | ||
254 | # | ||
255 | # CONFIG_MACH_H4700 is not set | ||
256 | # CONFIG_MACH_H5000 is not set | ||
257 | # CONFIG_MACH_HIMALAYA is not set | ||
258 | # CONFIG_MACH_MAGICIAN is not set | ||
259 | # CONFIG_MACH_MIOA701 is not set | ||
260 | # CONFIG_PXA_EZX is not set | ||
261 | # CONFIG_MACH_MP900C is not set | ||
262 | # CONFIG_ARCH_PXA_PALM is not set | ||
263 | # CONFIG_PXA_SHARPSL is not set | ||
264 | # CONFIG_ARCH_PXA_ESERIES is not set | ||
265 | CONFIG_PXA27x=y | ||
266 | CONFIG_PXA_SSP=y | ||
267 | CONFIG_PXA_HAVE_BOARD_IRQS=y | ||
268 | CONFIG_PXA_HAVE_ISA_IRQS=y | ||
269 | CONFIG_PLAT_PXA=y | ||
270 | |||
271 | # | ||
272 | # Processor Type | ||
273 | # | ||
274 | CONFIG_CPU_32=y | ||
275 | CONFIG_CPU_XSCALE=y | ||
276 | CONFIG_CPU_32v5=y | ||
277 | CONFIG_CPU_ABRT_EV5T=y | ||
278 | CONFIG_CPU_PABRT_LEGACY=y | ||
279 | CONFIG_CPU_CACHE_VIVT=y | ||
280 | CONFIG_CPU_TLB_V4WBI=y | ||
281 | CONFIG_CPU_CP15=y | ||
282 | CONFIG_CPU_CP15_MMU=y | ||
283 | |||
284 | # | ||
285 | # Processor Features | ||
286 | # | ||
287 | CONFIG_ARM_THUMB=y | ||
288 | # CONFIG_CPU_DCACHE_DISABLE is not set | ||
289 | CONFIG_ARM_L1_CACHE_SHIFT=5 | ||
290 | CONFIG_IWMMXT=y | ||
291 | CONFIG_XSCALE_PMU=y | ||
292 | CONFIG_COMMON_CLKDEV=y | ||
293 | |||
294 | # | ||
295 | # Bus support | ||
296 | # | ||
297 | CONFIG_ISA=y | ||
298 | # CONFIG_PCI_SYSCALL is not set | ||
299 | # CONFIG_ARCH_SUPPORTS_MSI is not set | ||
300 | CONFIG_PCCARD=m | ||
301 | CONFIG_PCMCIA=m | ||
302 | CONFIG_PCMCIA_LOAD_CIS=y | ||
303 | CONFIG_PCMCIA_IOCTL=y | ||
304 | |||
305 | # | ||
306 | # PC-card bridges | ||
307 | # | ||
308 | # CONFIG_I82365 is not set | ||
309 | # CONFIG_TCIC is not set | ||
310 | CONFIG_PCMCIA_SOC_COMMON=m | ||
311 | CONFIG_PCMCIA_PXA2XX=m | ||
312 | # CONFIG_PCMCIA_DEBUG is not set | ||
313 | CONFIG_PCMCIA_PROBE=y | ||
314 | |||
315 | # | ||
316 | # Kernel Features | ||
317 | # | ||
318 | CONFIG_TICK_ONESHOT=y | ||
319 | # CONFIG_NO_HZ is not set | ||
320 | # CONFIG_HIGH_RES_TIMERS is not set | ||
321 | CONFIG_GENERIC_CLOCKEVENTS_BUILD=y | ||
322 | CONFIG_VMSPLIT_3G=y | ||
323 | # CONFIG_VMSPLIT_2G is not set | ||
324 | # CONFIG_VMSPLIT_1G is not set | ||
325 | CONFIG_PAGE_OFFSET=0xC0000000 | ||
326 | CONFIG_PREEMPT_NONE=y | ||
327 | # CONFIG_PREEMPT_VOLUNTARY is not set | ||
328 | # CONFIG_PREEMPT is not set | ||
329 | CONFIG_HZ=100 | ||
330 | CONFIG_AEABI=y | ||
331 | CONFIG_OABI_COMPAT=y | ||
332 | # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set | ||
333 | # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set | ||
334 | # CONFIG_HIGHMEM is not set | ||
335 | CONFIG_SELECT_MEMORY_MODEL=y | ||
336 | CONFIG_FLATMEM_MANUAL=y | ||
337 | # CONFIG_DISCONTIGMEM_MANUAL is not set | ||
338 | # CONFIG_SPARSEMEM_MANUAL is not set | ||
339 | CONFIG_FLATMEM=y | ||
340 | CONFIG_FLAT_NODE_MEM_MAP=y | ||
341 | CONFIG_PAGEFLAGS_EXTENDED=y | ||
342 | CONFIG_SPLIT_PTLOCK_CPUS=4096 | ||
343 | # CONFIG_PHYS_ADDR_T_64BIT is not set | ||
344 | CONFIG_ZONE_DMA_FLAG=0 | ||
345 | CONFIG_VIRT_TO_BUS=y | ||
346 | CONFIG_HAVE_MLOCK=y | ||
347 | CONFIG_HAVE_MLOCKED_PAGE_BIT=y | ||
348 | # CONFIG_KSM is not set | ||
349 | CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 | ||
350 | CONFIG_ALIGNMENT_TRAP=y | ||
351 | # CONFIG_UACCESS_WITH_MEMCPY is not set | ||
352 | |||
353 | # | ||
354 | # Boot options | ||
355 | # | ||
356 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
357 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
358 | CONFIG_CMDLINE="root=31:02 rootfstype=jffs2 ro console=ttyS0,115200" | ||
359 | # CONFIG_XIP_KERNEL is not set | ||
360 | # CONFIG_KEXEC is not set | ||
361 | |||
362 | # | ||
363 | # CPU Power Management | ||
364 | # | ||
365 | CONFIG_CPU_FREQ=y | ||
366 | CONFIG_CPU_FREQ_TABLE=y | ||
367 | # CONFIG_CPU_FREQ_DEBUG is not set | ||
368 | CONFIG_CPU_FREQ_STAT=y | ||
369 | # CONFIG_CPU_FREQ_STAT_DETAILS is not set | ||
370 | CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y | ||
371 | # CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set | ||
372 | # CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set | ||
373 | # CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set | ||
374 | # CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set | ||
375 | CONFIG_CPU_FREQ_GOV_PERFORMANCE=y | ||
376 | CONFIG_CPU_FREQ_GOV_POWERSAVE=m | ||
377 | CONFIG_CPU_FREQ_GOV_USERSPACE=m | ||
378 | CONFIG_CPU_FREQ_GOV_ONDEMAND=m | ||
379 | CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m | ||
380 | # CONFIG_CPU_IDLE is not set | ||
381 | |||
382 | # | ||
383 | # Floating point emulation | ||
384 | # | ||
385 | |||
386 | # | ||
387 | # At least one emulation must be selected | ||
388 | # | ||
389 | CONFIG_FPE_NWFPE=y | ||
390 | # CONFIG_FPE_NWFPE_XP is not set | ||
391 | # CONFIG_FPE_FASTFPE is not set | ||
392 | |||
393 | # | ||
394 | # Userspace binary formats | ||
395 | # | ||
396 | CONFIG_BINFMT_ELF=y | ||
397 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set | ||
398 | CONFIG_HAVE_AOUT=y | ||
399 | # CONFIG_BINFMT_AOUT is not set | ||
400 | # CONFIG_BINFMT_MISC is not set | ||
401 | |||
402 | # | ||
403 | # Power management options | ||
404 | # | ||
405 | CONFIG_PM=y | ||
406 | # CONFIG_PM_DEBUG is not set | ||
407 | CONFIG_PM_SLEEP=y | ||
408 | CONFIG_SUSPEND=y | ||
409 | CONFIG_SUSPEND_FREEZER=y | ||
410 | CONFIG_APM_EMULATION=y | ||
411 | # CONFIG_PM_RUNTIME is not set | ||
412 | CONFIG_ARCH_SUSPEND_POSSIBLE=y | ||
413 | CONFIG_NET=y | ||
414 | |||
415 | # | ||
416 | # Networking options | ||
417 | # | ||
418 | CONFIG_PACKET=y | ||
419 | # CONFIG_PACKET_MMAP is not set | ||
420 | CONFIG_UNIX=y | ||
421 | CONFIG_XFRM=y | ||
422 | # CONFIG_XFRM_USER is not set | ||
423 | # CONFIG_XFRM_SUB_POLICY is not set | ||
424 | # CONFIG_XFRM_MIGRATE is not set | ||
425 | # CONFIG_XFRM_STATISTICS is not set | ||
426 | # CONFIG_NET_KEY is not set | ||
427 | CONFIG_INET=y | ||
428 | # CONFIG_IP_MULTICAST is not set | ||
429 | # CONFIG_IP_ADVANCED_ROUTER is not set | ||
430 | CONFIG_IP_FIB_HASH=y | ||
431 | CONFIG_IP_PNP=y | ||
432 | CONFIG_IP_PNP_DHCP=y | ||
433 | # CONFIG_IP_PNP_BOOTP is not set | ||
434 | # CONFIG_IP_PNP_RARP is not set | ||
435 | # CONFIG_NET_IPIP is not set | ||
436 | # CONFIG_NET_IPGRE is not set | ||
437 | # CONFIG_ARPD is not set | ||
438 | CONFIG_SYN_COOKIES=y | ||
439 | # CONFIG_INET_AH is not set | ||
440 | # CONFIG_INET_ESP is not set | ||
441 | # CONFIG_INET_IPCOMP is not set | ||
442 | # CONFIG_INET_XFRM_TUNNEL is not set | ||
443 | # CONFIG_INET_TUNNEL is not set | ||
444 | CONFIG_INET_XFRM_MODE_TRANSPORT=y | ||
445 | CONFIG_INET_XFRM_MODE_TUNNEL=y | ||
446 | CONFIG_INET_XFRM_MODE_BEET=y | ||
447 | # CONFIG_INET_LRO is not set | ||
448 | CONFIG_INET_DIAG=y | ||
449 | CONFIG_INET_TCP_DIAG=y | ||
450 | # CONFIG_TCP_CONG_ADVANCED is not set | ||
451 | CONFIG_TCP_CONG_CUBIC=y | ||
452 | CONFIG_DEFAULT_TCP_CONG="cubic" | ||
453 | # CONFIG_TCP_MD5SIG is not set | ||
454 | # CONFIG_IPV6 is not set | ||
455 | # CONFIG_NETWORK_SECMARK is not set | ||
456 | # CONFIG_NETFILTER is not set | ||
457 | # CONFIG_IP_DCCP is not set | ||
458 | # CONFIG_IP_SCTP is not set | ||
459 | # CONFIG_RDS is not set | ||
460 | # CONFIG_TIPC is not set | ||
461 | # CONFIG_ATM is not set | ||
462 | # CONFIG_BRIDGE is not set | ||
463 | # CONFIG_NET_DSA is not set | ||
464 | # CONFIG_VLAN_8021Q is not set | ||
465 | # CONFIG_DECNET is not set | ||
466 | # CONFIG_LLC2 is not set | ||
467 | # CONFIG_IPX is not set | ||
468 | # CONFIG_ATALK is not set | ||
469 | # CONFIG_X25 is not set | ||
470 | # CONFIG_LAPB is not set | ||
471 | # CONFIG_ECONET is not set | ||
472 | # CONFIG_WAN_ROUTER is not set | ||
473 | # CONFIG_PHONET is not set | ||
474 | # CONFIG_IEEE802154 is not set | ||
475 | # CONFIG_NET_SCHED is not set | ||
476 | # CONFIG_DCB is not set | ||
477 | |||
478 | # | ||
479 | # Network testing | ||
480 | # | ||
481 | # CONFIG_NET_PKTGEN is not set | ||
482 | # CONFIG_HAMRADIO is not set | ||
483 | # CONFIG_CAN is not set | ||
484 | # CONFIG_IRDA is not set | ||
485 | CONFIG_BT=m | ||
486 | CONFIG_BT_L2CAP=m | ||
487 | # CONFIG_BT_SCO is not set | ||
488 | CONFIG_BT_RFCOMM=m | ||
489 | CONFIG_BT_RFCOMM_TTY=y | ||
490 | CONFIG_BT_BNEP=m | ||
491 | # CONFIG_BT_BNEP_MC_FILTER is not set | ||
492 | # CONFIG_BT_BNEP_PROTO_FILTER is not set | ||
493 | # CONFIG_BT_HIDP is not set | ||
494 | |||
495 | # | ||
496 | # Bluetooth device drivers | ||
497 | # | ||
498 | # CONFIG_BT_HCIBTUSB is not set | ||
499 | # CONFIG_BT_HCIBTSDIO is not set | ||
500 | CONFIG_BT_HCIUART=m | ||
501 | CONFIG_BT_HCIUART_H4=y | ||
502 | CONFIG_BT_HCIUART_BCSP=y | ||
503 | # CONFIG_BT_HCIUART_LL is not set | ||
504 | # CONFIG_BT_HCIBCM203X is not set | ||
505 | # CONFIG_BT_HCIBPA10X is not set | ||
506 | # CONFIG_BT_HCIBFUSB is not set | ||
507 | # CONFIG_BT_HCIDTL1 is not set | ||
508 | # CONFIG_BT_HCIBT3C is not set | ||
509 | # CONFIG_BT_HCIBLUECARD is not set | ||
510 | # CONFIG_BT_HCIBTUART is not set | ||
511 | # CONFIG_BT_HCIVHCI is not set | ||
512 | # CONFIG_BT_MRVL is not set | ||
513 | # CONFIG_AF_RXRPC is not set | ||
514 | CONFIG_WIRELESS=y | ||
515 | CONFIG_WIRELESS_EXT=y | ||
516 | CONFIG_WEXT_CORE=y | ||
517 | CONFIG_WEXT_PROC=y | ||
518 | CONFIG_WEXT_SPY=y | ||
519 | CONFIG_WEXT_PRIV=y | ||
520 | CONFIG_CFG80211=m | ||
521 | # CONFIG_NL80211_TESTMODE is not set | ||
522 | # CONFIG_CFG80211_DEVELOPER_WARNINGS is not set | ||
523 | # CONFIG_CFG80211_REG_DEBUG is not set | ||
524 | CONFIG_CFG80211_DEFAULT_PS=y | ||
525 | # CONFIG_WIRELESS_OLD_REGULATORY is not set | ||
526 | CONFIG_CFG80211_WEXT=y | ||
527 | CONFIG_WIRELESS_EXT_SYSFS=y | ||
528 | CONFIG_LIB80211=m | ||
529 | # CONFIG_LIB80211_DEBUG is not set | ||
530 | CONFIG_MAC80211=m | ||
531 | CONFIG_MAC80211_RC_MINSTREL=y | ||
532 | # CONFIG_MAC80211_RC_DEFAULT_PID is not set | ||
533 | CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y | ||
534 | CONFIG_MAC80211_RC_DEFAULT="minstrel" | ||
535 | # CONFIG_MAC80211_MESH is not set | ||
536 | # CONFIG_MAC80211_LEDS is not set | ||
537 | # CONFIG_MAC80211_DEBUG_MENU is not set | ||
538 | # CONFIG_WIMAX is not set | ||
539 | # CONFIG_RFKILL is not set | ||
540 | # CONFIG_NET_9P is not set | ||
541 | |||
542 | # | ||
543 | # Device Drivers | ||
544 | # | ||
545 | |||
546 | # | ||
547 | # Generic Driver Options | ||
548 | # | ||
549 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
550 | # CONFIG_DEVTMPFS is not set | ||
551 | CONFIG_STANDALONE=y | ||
552 | CONFIG_PREVENT_FIRMWARE_BUILD=y | ||
553 | CONFIG_FW_LOADER=y | ||
554 | CONFIG_FIRMWARE_IN_KERNEL=y | ||
555 | CONFIG_EXTRA_FIRMWARE="" | ||
556 | # CONFIG_DEBUG_DRIVER is not set | ||
557 | # CONFIG_DEBUG_DEVRES is not set | ||
558 | # CONFIG_SYS_HYPERVISOR is not set | ||
559 | # CONFIG_CONNECTOR is not set | ||
560 | CONFIG_MTD=y | ||
561 | # CONFIG_MTD_DEBUG is not set | ||
562 | # CONFIG_MTD_TESTS is not set | ||
563 | # CONFIG_MTD_CONCAT is not set | ||
564 | CONFIG_MTD_PARTITIONS=y | ||
565 | CONFIG_MTD_REDBOOT_PARTS=y | ||
566 | CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1 | ||
567 | # CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set | ||
568 | CONFIG_MTD_REDBOOT_PARTS_READONLY=y | ||
569 | # CONFIG_MTD_CMDLINE_PARTS is not set | ||
570 | # CONFIG_MTD_AFS_PARTS is not set | ||
571 | # CONFIG_MTD_AR7_PARTS is not set | ||
572 | |||
573 | # | ||
574 | # User Modules And Translation Layers | ||
575 | # | ||
576 | CONFIG_MTD_CHAR=m | ||
577 | CONFIG_MTD_BLKDEVS=y | ||
578 | CONFIG_MTD_BLOCK=y | ||
579 | # CONFIG_FTL is not set | ||
580 | # CONFIG_NFTL is not set | ||
581 | # CONFIG_INFTL is not set | ||
582 | # CONFIG_RFD_FTL is not set | ||
583 | # CONFIG_SSFDC is not set | ||
584 | # CONFIG_MTD_OOPS is not set | ||
585 | |||
586 | # | ||
587 | # RAM/ROM/Flash chip drivers | ||
588 | # | ||
589 | CONFIG_MTD_CFI=y | ||
590 | CONFIG_MTD_JEDECPROBE=y | ||
591 | CONFIG_MTD_GEN_PROBE=y | ||
592 | CONFIG_MTD_CFI_ADV_OPTIONS=y | ||
593 | CONFIG_MTD_CFI_NOSWAP=y | ||
594 | # CONFIG_MTD_CFI_BE_BYTE_SWAP is not set | ||
595 | # CONFIG_MTD_CFI_LE_BYTE_SWAP is not set | ||
596 | CONFIG_MTD_CFI_GEOMETRY=y | ||
597 | CONFIG_MTD_MAP_BANK_WIDTH_1=y | ||
598 | CONFIG_MTD_MAP_BANK_WIDTH_2=y | ||
599 | # CONFIG_MTD_MAP_BANK_WIDTH_4 is not set | ||
600 | # CONFIG_MTD_MAP_BANK_WIDTH_8 is not set | ||
601 | # CONFIG_MTD_MAP_BANK_WIDTH_16 is not set | ||
602 | # CONFIG_MTD_MAP_BANK_WIDTH_32 is not set | ||
603 | CONFIG_MTD_CFI_I1=y | ||
604 | # CONFIG_MTD_CFI_I2 is not set | ||
605 | # CONFIG_MTD_CFI_I4 is not set | ||
606 | # CONFIG_MTD_CFI_I8 is not set | ||
607 | # CONFIG_MTD_OTP is not set | ||
608 | CONFIG_MTD_CFI_INTELEXT=y | ||
609 | CONFIG_MTD_CFI_AMDSTD=y | ||
610 | # CONFIG_MTD_CFI_STAA is not set | ||
611 | CONFIG_MTD_CFI_UTIL=y | ||
612 | CONFIG_MTD_RAM=y | ||
613 | # CONFIG_MTD_ROM is not set | ||
614 | # CONFIG_MTD_ABSENT is not set | ||
615 | # CONFIG_MTD_XIP is not set | ||
616 | |||
617 | # | ||
618 | # Mapping drivers for chip access | ||
619 | # | ||
620 | CONFIG_MTD_COMPLEX_MAPPINGS=y | ||
621 | CONFIG_MTD_PHYSMAP=y | ||
622 | # CONFIG_MTD_PHYSMAP_COMPAT is not set | ||
623 | CONFIG_MTD_PXA2XX=y | ||
624 | # CONFIG_MTD_ARM_INTEGRATOR is not set | ||
625 | # CONFIG_MTD_IMPA7 is not set | ||
626 | # CONFIG_MTD_GPIO_ADDR is not set | ||
627 | # CONFIG_MTD_PLATRAM is not set | ||
628 | |||
629 | # | ||
630 | # Self-contained MTD device drivers | ||
631 | # | ||
632 | # CONFIG_MTD_DATAFLASH is not set | ||
633 | # CONFIG_MTD_M25P80 is not set | ||
634 | # CONFIG_MTD_SST25L is not set | ||
635 | # CONFIG_MTD_SLRAM is not set | ||
636 | # CONFIG_MTD_PHRAM is not set | ||
637 | # CONFIG_MTD_MTDRAM is not set | ||
638 | # CONFIG_MTD_BLOCK2MTD is not set | ||
639 | |||
640 | # | ||
641 | # Disk-On-Chip Device Drivers | ||
642 | # | ||
643 | # CONFIG_MTD_DOC2000 is not set | ||
644 | # CONFIG_MTD_DOC2001 is not set | ||
645 | # CONFIG_MTD_DOC2001PLUS is not set | ||
646 | # CONFIG_MTD_NAND is not set | ||
647 | # CONFIG_MTD_ONENAND is not set | ||
648 | |||
649 | # | ||
650 | # LPDDR flash memory drivers | ||
651 | # | ||
652 | # CONFIG_MTD_LPDDR is not set | ||
653 | |||
654 | # | ||
655 | # UBI - Unsorted block images | ||
656 | # | ||
657 | # CONFIG_MTD_UBI is not set | ||
658 | # CONFIG_PARPORT is not set | ||
659 | # CONFIG_PNP is not set | ||
660 | CONFIG_BLK_DEV=y | ||
661 | # CONFIG_BLK_DEV_COW_COMMON is not set | ||
662 | CONFIG_BLK_DEV_LOOP=m | ||
663 | # CONFIG_BLK_DEV_CRYPTOLOOP is not set | ||
664 | |||
665 | # | ||
666 | # DRBD disabled because PROC_FS, INET or CONNECTOR not selected | ||
667 | # | ||
668 | # CONFIG_BLK_DEV_NBD is not set | ||
669 | # CONFIG_BLK_DEV_UB is not set | ||
670 | # CONFIG_BLK_DEV_RAM is not set | ||
671 | # CONFIG_CDROM_PKTCDVD is not set | ||
672 | # CONFIG_ATA_OVER_ETH is not set | ||
673 | # CONFIG_MG_DISK is not set | ||
674 | CONFIG_MISC_DEVICES=y | ||
675 | # CONFIG_ICS932S401 is not set | ||
676 | # CONFIG_ENCLOSURE_SERVICES is not set | ||
677 | # CONFIG_ISL29003 is not set | ||
678 | # CONFIG_DS1682 is not set | ||
679 | # CONFIG_C2PORT is not set | ||
680 | |||
681 | # | ||
682 | # EEPROM support | ||
683 | # | ||
684 | CONFIG_EEPROM_AT24=m | ||
685 | # CONFIG_EEPROM_AT25 is not set | ||
686 | # CONFIG_EEPROM_LEGACY is not set | ||
687 | # CONFIG_EEPROM_MAX6875 is not set | ||
688 | # CONFIG_EEPROM_93CX6 is not set | ||
689 | # CONFIG_IWMC3200TOP is not set | ||
690 | CONFIG_HAVE_IDE=y | ||
691 | # CONFIG_IDE is not set | ||
692 | |||
693 | # | ||
694 | # SCSI device support | ||
695 | # | ||
696 | # CONFIG_RAID_ATTRS is not set | ||
697 | CONFIG_SCSI=m | ||
698 | CONFIG_SCSI_DMA=y | ||
699 | # CONFIG_SCSI_TGT is not set | ||
700 | # CONFIG_SCSI_NETLINK is not set | ||
701 | # CONFIG_SCSI_PROC_FS is not set | ||
702 | |||
703 | # | ||
704 | # SCSI support type (disk, tape, CD-ROM) | ||
705 | # | ||
706 | CONFIG_BLK_DEV_SD=m | ||
707 | # CONFIG_CHR_DEV_ST is not set | ||
708 | # CONFIG_CHR_DEV_OSST is not set | ||
709 | # CONFIG_BLK_DEV_SR is not set | ||
710 | # CONFIG_CHR_DEV_SG is not set | ||
711 | # CONFIG_CHR_DEV_SCH is not set | ||
712 | # CONFIG_SCSI_MULTI_LUN is not set | ||
713 | # CONFIG_SCSI_CONSTANTS is not set | ||
714 | # CONFIG_SCSI_LOGGING is not set | ||
715 | # CONFIG_SCSI_SCAN_ASYNC is not set | ||
716 | CONFIG_SCSI_WAIT_SCAN=m | ||
717 | |||
718 | # | ||
719 | # SCSI Transports | ||
720 | # | ||
721 | # CONFIG_SCSI_SPI_ATTRS is not set | ||
722 | # CONFIG_SCSI_FC_ATTRS is not set | ||
723 | # CONFIG_SCSI_ISCSI_ATTRS is not set | ||
724 | # CONFIG_SCSI_SAS_LIBSAS is not set | ||
725 | # CONFIG_SCSI_SRP_ATTRS is not set | ||
726 | CONFIG_SCSI_LOWLEVEL=y | ||
727 | # CONFIG_ISCSI_TCP is not set | ||
728 | # CONFIG_SCSI_AHA152X is not set | ||
729 | # CONFIG_SCSI_AIC7XXX_OLD is not set | ||
730 | # CONFIG_SCSI_ADVANSYS is not set | ||
731 | # CONFIG_SCSI_IN2000 is not set | ||
732 | # CONFIG_LIBFC is not set | ||
733 | # CONFIG_LIBFCOE is not set | ||
734 | # CONFIG_SCSI_DTC3280 is not set | ||
735 | # CONFIG_SCSI_FUTURE_DOMAIN is not set | ||
736 | # CONFIG_SCSI_GENERIC_NCR5380 is not set | ||
737 | # CONFIG_SCSI_GENERIC_NCR5380_MMIO is not set | ||
738 | # CONFIG_SCSI_NCR53C406A is not set | ||
739 | # CONFIG_SCSI_PAS16 is not set | ||
740 | # CONFIG_SCSI_QLOGIC_FAS is not set | ||
741 | # CONFIG_SCSI_SYM53C416 is not set | ||
742 | # CONFIG_SCSI_T128 is not set | ||
743 | # CONFIG_SCSI_DEBUG is not set | ||
744 | # CONFIG_SCSI_LOWLEVEL_PCMCIA is not set | ||
745 | # CONFIG_SCSI_DH is not set | ||
746 | # CONFIG_SCSI_OSD_INITIATOR is not set | ||
747 | CONFIG_ATA=m | ||
748 | # CONFIG_ATA_NONSTANDARD is not set | ||
749 | CONFIG_ATA_VERBOSE_ERROR=y | ||
750 | # CONFIG_SATA_PMP is not set | ||
751 | CONFIG_ATA_SFF=y | ||
752 | # CONFIG_SATA_MV is not set | ||
753 | # CONFIG_PATA_LEGACY is not set | ||
754 | CONFIG_PATA_PCMCIA=m | ||
755 | # CONFIG_PATA_QDI is not set | ||
756 | # CONFIG_PATA_WINBOND_VLB is not set | ||
757 | # CONFIG_MD is not set | ||
758 | CONFIG_NETDEVICES=y | ||
759 | # CONFIG_DUMMY is not set | ||
760 | # CONFIG_BONDING is not set | ||
761 | # CONFIG_MACVLAN is not set | ||
762 | # CONFIG_EQUALIZER is not set | ||
763 | # CONFIG_TUN is not set | ||
764 | # CONFIG_VETH is not set | ||
765 | # CONFIG_ARCNET is not set | ||
766 | # CONFIG_PHYLIB is not set | ||
767 | CONFIG_NET_ETHERNET=y | ||
768 | CONFIG_MII=y | ||
769 | # CONFIG_AX88796 is not set | ||
770 | # CONFIG_NET_VENDOR_3COM is not set | ||
771 | # CONFIG_NET_VENDOR_SMC is not set | ||
772 | # CONFIG_SMC91X is not set | ||
773 | CONFIG_DM9000=y | ||
774 | CONFIG_DM9000_DEBUGLEVEL=4 | ||
775 | # CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL is not set | ||
776 | # CONFIG_ENC28J60 is not set | ||
777 | # CONFIG_ETHOC is not set | ||
778 | # CONFIG_SMC911X is not set | ||
779 | # CONFIG_SMSC911X is not set | ||
780 | # CONFIG_NET_VENDOR_RACAL is not set | ||
781 | # CONFIG_DNET is not set | ||
782 | # CONFIG_AT1700 is not set | ||
783 | # CONFIG_DEPCA is not set | ||
784 | # CONFIG_HP100 is not set | ||
785 | # CONFIG_NET_ISA is not set | ||
786 | # CONFIG_IBM_NEW_EMAC_ZMII is not set | ||
787 | # CONFIG_IBM_NEW_EMAC_RGMII is not set | ||
788 | # CONFIG_IBM_NEW_EMAC_TAH is not set | ||
789 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set | ||
790 | # CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set | ||
791 | # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set | ||
792 | # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set | ||
793 | # CONFIG_NET_PCI is not set | ||
794 | # CONFIG_B44 is not set | ||
795 | # CONFIG_CS89x0 is not set | ||
796 | # CONFIG_KS8842 is not set | ||
797 | # CONFIG_KS8851 is not set | ||
798 | # CONFIG_KS8851_MLL is not set | ||
799 | # CONFIG_NETDEV_1000 is not set | ||
800 | # CONFIG_NETDEV_10000 is not set | ||
801 | # CONFIG_TR is not set | ||
802 | CONFIG_WLAN=y | ||
803 | # CONFIG_PCMCIA_RAYCS is not set | ||
804 | # CONFIG_LIBERTAS_THINFIRM is not set | ||
805 | # CONFIG_ATMEL is not set | ||
806 | # CONFIG_AT76C50X_USB is not set | ||
807 | # CONFIG_AIRO_CS is not set | ||
808 | # CONFIG_PCMCIA_WL3501 is not set | ||
809 | # CONFIG_USB_ZD1201 is not set | ||
810 | # CONFIG_USB_NET_RNDIS_WLAN is not set | ||
811 | # CONFIG_RTL8187 is not set | ||
812 | # CONFIG_MAC80211_HWSIM is not set | ||
813 | # CONFIG_ATH_COMMON is not set | ||
814 | # CONFIG_B43 is not set | ||
815 | # CONFIG_B43LEGACY is not set | ||
816 | # CONFIG_HOSTAP is not set | ||
817 | # CONFIG_IWM is not set | ||
818 | # CONFIG_LIBERTAS is not set | ||
819 | CONFIG_HERMES=m | ||
820 | CONFIG_HERMES_CACHE_FW_ON_INIT=y | ||
821 | CONFIG_PCMCIA_HERMES=m | ||
822 | # CONFIG_PCMCIA_SPECTRUM is not set | ||
823 | # CONFIG_P54_COMMON is not set | ||
824 | CONFIG_RT2X00=m | ||
825 | # CONFIG_RT2500USB is not set | ||
826 | CONFIG_RT73USB=m | ||
827 | # CONFIG_RT2800USB is not set | ||
828 | CONFIG_RT2X00_LIB_USB=m | ||
829 | CONFIG_RT2X00_LIB=m | ||
830 | CONFIG_RT2X00_LIB_FIRMWARE=y | ||
831 | CONFIG_RT2X00_LIB_CRYPTO=y | ||
832 | CONFIG_RT2X00_LIB_LEDS=y | ||
833 | # CONFIG_RT2X00_DEBUG is not set | ||
834 | # CONFIG_WL12XX is not set | ||
835 | # CONFIG_ZD1211RW is not set | ||
836 | |||
837 | # | ||
838 | # Enable WiMAX (Networking options) to see the WiMAX drivers | ||
839 | # | ||
840 | |||
841 | # | ||
842 | # USB Network Adapters | ||
843 | # | ||
844 | # CONFIG_USB_CATC is not set | ||
845 | # CONFIG_USB_KAWETH is not set | ||
846 | # CONFIG_USB_PEGASUS is not set | ||
847 | # CONFIG_USB_RTL8150 is not set | ||
848 | # CONFIG_USB_USBNET is not set | ||
849 | CONFIG_NET_PCMCIA=y | ||
850 | # CONFIG_PCMCIA_3C589 is not set | ||
851 | # CONFIG_PCMCIA_3C574 is not set | ||
852 | # CONFIG_PCMCIA_FMVJ18X is not set | ||
853 | # CONFIG_PCMCIA_PCNET is not set | ||
854 | # CONFIG_PCMCIA_NMCLAN is not set | ||
855 | # CONFIG_PCMCIA_SMC91C92 is not set | ||
856 | # CONFIG_PCMCIA_XIRC2PS is not set | ||
857 | # CONFIG_PCMCIA_AXNET is not set | ||
858 | # CONFIG_WAN is not set | ||
859 | CONFIG_PPP=m | ||
860 | # CONFIG_PPP_MULTILINK is not set | ||
861 | # CONFIG_PPP_FILTER is not set | ||
862 | CONFIG_PPP_ASYNC=m | ||
863 | # CONFIG_PPP_SYNC_TTY is not set | ||
864 | CONFIG_PPP_DEFLATE=m | ||
865 | CONFIG_PPP_BSDCOMP=m | ||
866 | # CONFIG_PPP_MPPE is not set | ||
867 | # CONFIG_PPPOE is not set | ||
868 | # CONFIG_PPPOL2TP is not set | ||
869 | # CONFIG_SLIP is not set | ||
870 | CONFIG_SLHC=m | ||
871 | # CONFIG_NETCONSOLE is not set | ||
872 | # CONFIG_NETPOLL is not set | ||
873 | # CONFIG_NET_POLL_CONTROLLER is not set | ||
874 | # CONFIG_ISDN is not set | ||
875 | # CONFIG_PHONE is not set | ||
876 | |||
877 | # | ||
878 | # Input device support | ||
879 | # | ||
880 | CONFIG_INPUT=y | ||
881 | # CONFIG_INPUT_FF_MEMLESS is not set | ||
882 | # CONFIG_INPUT_POLLDEV is not set | ||
883 | |||
884 | # | ||
885 | # Userland interfaces | ||
886 | # | ||
887 | CONFIG_INPUT_MOUSEDEV=y | ||
888 | # CONFIG_INPUT_MOUSEDEV_PSAUX is not set | ||
889 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 | ||
890 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 | ||
891 | # CONFIG_INPUT_JOYDEV is not set | ||
892 | CONFIG_INPUT_EVDEV=m | ||
893 | # CONFIG_INPUT_EVBUG is not set | ||
894 | |||
895 | # | ||
896 | # Input Device Drivers | ||
897 | # | ||
898 | # CONFIG_INPUT_KEYBOARD is not set | ||
899 | # CONFIG_INPUT_MOUSE is not set | ||
900 | # CONFIG_INPUT_JOYSTICK is not set | ||
901 | # CONFIG_INPUT_TABLET is not set | ||
902 | CONFIG_INPUT_TOUCHSCREEN=y | ||
903 | # CONFIG_TOUCHSCREEN_ADS7846 is not set | ||
904 | # CONFIG_TOUCHSCREEN_AD7877 is not set | ||
905 | # CONFIG_TOUCHSCREEN_AD7879_I2C is not set | ||
906 | # CONFIG_TOUCHSCREEN_AD7879_SPI is not set | ||
907 | # CONFIG_TOUCHSCREEN_AD7879 is not set | ||
908 | # CONFIG_TOUCHSCREEN_EETI is not set | ||
909 | CONFIG_TOUCHSCREEN_FUJITSU=m | ||
910 | # CONFIG_TOUCHSCREEN_GUNZE is not set | ||
911 | CONFIG_TOUCHSCREEN_ELO=m | ||
912 | # CONFIG_TOUCHSCREEN_WACOM_W8001 is not set | ||
913 | # CONFIG_TOUCHSCREEN_MCS5000 is not set | ||
914 | CONFIG_TOUCHSCREEN_MTOUCH=m | ||
915 | CONFIG_TOUCHSCREEN_INEXIO=m | ||
916 | # CONFIG_TOUCHSCREEN_MK712 is not set | ||
917 | CONFIG_TOUCHSCREEN_HTCPEN=m | ||
918 | CONFIG_TOUCHSCREEN_PENMOUNT=m | ||
919 | CONFIG_TOUCHSCREEN_TOUCHRIGHT=m | ||
920 | CONFIG_TOUCHSCREEN_TOUCHWIN=m | ||
921 | # CONFIG_TOUCHSCREEN_WM97XX is not set | ||
922 | # CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set | ||
923 | CONFIG_TOUCHSCREEN_TOUCHIT213=m | ||
924 | # CONFIG_TOUCHSCREEN_TSC2007 is not set | ||
925 | # CONFIG_TOUCHSCREEN_W90X900 is not set | ||
926 | CONFIG_INPUT_MISC=y | ||
927 | # CONFIG_INPUT_ATI_REMOTE is not set | ||
928 | # CONFIG_INPUT_ATI_REMOTE2 is not set | ||
929 | # CONFIG_INPUT_KEYSPAN_REMOTE is not set | ||
930 | # CONFIG_INPUT_POWERMATE is not set | ||
931 | # CONFIG_INPUT_YEALINK is not set | ||
932 | # CONFIG_INPUT_CM109 is not set | ||
933 | CONFIG_INPUT_UINPUT=m | ||
934 | # CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set | ||
935 | |||
936 | # | ||
937 | # Hardware I/O ports | ||
938 | # | ||
939 | CONFIG_SERIO=y | ||
940 | CONFIG_SERIO_SERPORT=y | ||
941 | # CONFIG_SERIO_RAW is not set | ||
942 | # CONFIG_GAMEPORT is not set | ||
943 | |||
944 | # | ||
945 | # Character devices | ||
946 | # | ||
947 | CONFIG_VT=y | ||
948 | CONFIG_CONSOLE_TRANSLATIONS=y | ||
949 | CONFIG_VT_CONSOLE=y | ||
950 | CONFIG_HW_CONSOLE=y | ||
951 | # CONFIG_VT_HW_CONSOLE_BINDING is not set | ||
952 | CONFIG_DEVKMEM=y | ||
953 | # CONFIG_SERIAL_NONSTANDARD is not set | ||
954 | |||
955 | # | ||
956 | # Serial drivers | ||
957 | # | ||
958 | CONFIG_SERIAL_8250=y | ||
959 | CONFIG_SERIAL_8250_CONSOLE=y | ||
960 | # CONFIG_SERIAL_8250_CS is not set | ||
961 | CONFIG_SERIAL_8250_NR_UARTS=7 | ||
962 | CONFIG_SERIAL_8250_RUNTIME_UARTS=7 | ||
963 | # CONFIG_SERIAL_8250_EXTENDED is not set | ||
964 | |||
965 | # | ||
966 | # Non-8250 serial port support | ||
967 | # | ||
968 | # CONFIG_SERIAL_MAX3100 is not set | ||
969 | # CONFIG_SERIAL_PXA is not set | ||
970 | CONFIG_SERIAL_CORE=y | ||
971 | CONFIG_SERIAL_CORE_CONSOLE=y | ||
972 | CONFIG_UNIX98_PTYS=y | ||
973 | # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set | ||
974 | # CONFIG_LEGACY_PTYS is not set | ||
975 | # CONFIG_IPMI_HANDLER is not set | ||
976 | CONFIG_HW_RANDOM=m | ||
977 | # CONFIG_HW_RANDOM_TIMERIOMEM is not set | ||
978 | # CONFIG_DTLK is not set | ||
979 | # CONFIG_R3964 is not set | ||
980 | |||
981 | # | ||
982 | # PCMCIA character devices | ||
983 | # | ||
984 | # CONFIG_SYNCLINK_CS is not set | ||
985 | # CONFIG_CARDMAN_4000 is not set | ||
986 | # CONFIG_CARDMAN_4040 is not set | ||
987 | # CONFIG_IPWIRELESS is not set | ||
988 | # CONFIG_RAW_DRIVER is not set | ||
989 | # CONFIG_TCG_TPM is not set | ||
990 | CONFIG_DEVPORT=y | ||
991 | CONFIG_I2C=y | ||
992 | CONFIG_I2C_BOARDINFO=y | ||
993 | CONFIG_I2C_COMPAT=y | ||
994 | CONFIG_I2C_CHARDEV=y | ||
995 | # CONFIG_I2C_HELPER_AUTO is not set | ||
996 | |||
997 | # | ||
998 | # I2C Algorithms | ||
999 | # | ||
1000 | CONFIG_I2C_ALGOBIT=y | ||
1001 | # CONFIG_I2C_ALGOPCF is not set | ||
1002 | # CONFIG_I2C_ALGOPCA is not set | ||
1003 | |||
1004 | # | ||
1005 | # I2C Hardware Bus support | ||
1006 | # | ||
1007 | |||
1008 | # | ||
1009 | # I2C system bus drivers (mostly embedded / system-on-chip) | ||
1010 | # | ||
1011 | # CONFIG_I2C_DESIGNWARE is not set | ||
1012 | CONFIG_I2C_GPIO=y | ||
1013 | # CONFIG_I2C_OCORES is not set | ||
1014 | CONFIG_I2C_PXA=y | ||
1015 | # CONFIG_I2C_PXA_SLAVE is not set | ||
1016 | # CONFIG_I2C_SIMTEC is not set | ||
1017 | |||
1018 | # | ||
1019 | # External I2C/SMBus adapter drivers | ||
1020 | # | ||
1021 | # CONFIG_I2C_PARPORT_LIGHT is not set | ||
1022 | # CONFIG_I2C_TAOS_EVM is not set | ||
1023 | # CONFIG_I2C_TINY_USB is not set | ||
1024 | |||
1025 | # | ||
1026 | # Other I2C/SMBus bus drivers | ||
1027 | # | ||
1028 | # CONFIG_I2C_ELEKTOR is not set | ||
1029 | # CONFIG_I2C_PCA_ISA is not set | ||
1030 | # CONFIG_I2C_PCA_PLATFORM is not set | ||
1031 | # CONFIG_I2C_STUB is not set | ||
1032 | |||
1033 | # | ||
1034 | # Miscellaneous I2C Chip support | ||
1035 | # | ||
1036 | # CONFIG_SENSORS_TSL2550 is not set | ||
1037 | # CONFIG_I2C_DEBUG_CORE is not set | ||
1038 | # CONFIG_I2C_DEBUG_ALGO is not set | ||
1039 | # CONFIG_I2C_DEBUG_BUS is not set | ||
1040 | # CONFIG_I2C_DEBUG_CHIP is not set | ||
1041 | CONFIG_SPI=y | ||
1042 | # CONFIG_SPI_DEBUG is not set | ||
1043 | CONFIG_SPI_MASTER=y | ||
1044 | |||
1045 | # | ||
1046 | # SPI Master Controller Drivers | ||
1047 | # | ||
1048 | # CONFIG_SPI_BITBANG is not set | ||
1049 | # CONFIG_SPI_GPIO is not set | ||
1050 | CONFIG_SPI_PXA2XX=y | ||
1051 | |||
1052 | # | ||
1053 | # SPI Protocol Masters | ||
1054 | # | ||
1055 | # CONFIG_SPI_SPIDEV is not set | ||
1056 | # CONFIG_SPI_TLE62X0 is not set | ||
1057 | |||
1058 | # | ||
1059 | # PPS support | ||
1060 | # | ||
1061 | # CONFIG_PPS is not set | ||
1062 | CONFIG_ARCH_REQUIRE_GPIOLIB=y | ||
1063 | CONFIG_GPIOLIB=y | ||
1064 | # CONFIG_DEBUG_GPIO is not set | ||
1065 | CONFIG_GPIO_SYSFS=y | ||
1066 | |||
1067 | # | ||
1068 | # Memory mapped GPIO expanders: | ||
1069 | # | ||
1070 | |||
1071 | # | ||
1072 | # I2C GPIO expanders: | ||
1073 | # | ||
1074 | # CONFIG_GPIO_MAX732X is not set | ||
1075 | CONFIG_GPIO_PCA953X=y | ||
1076 | # CONFIG_GPIO_PCF857X is not set | ||
1077 | |||
1078 | # | ||
1079 | # PCI GPIO expanders: | ||
1080 | # | ||
1081 | |||
1082 | # | ||
1083 | # SPI GPIO expanders: | ||
1084 | # | ||
1085 | # CONFIG_GPIO_MAX7301 is not set | ||
1086 | # CONFIG_GPIO_MCP23S08 is not set | ||
1087 | # CONFIG_GPIO_MC33880 is not set | ||
1088 | |||
1089 | # | ||
1090 | # AC97 GPIO expanders: | ||
1091 | # | ||
1092 | # CONFIG_W1 is not set | ||
1093 | # CONFIG_POWER_SUPPLY is not set | ||
1094 | CONFIG_HWMON=y | ||
1095 | # CONFIG_HWMON_VID is not set | ||
1096 | # CONFIG_HWMON_DEBUG_CHIP is not set | ||
1097 | |||
1098 | # | ||
1099 | # Native drivers | ||
1100 | # | ||
1101 | # CONFIG_SENSORS_AD7414 is not set | ||
1102 | # CONFIG_SENSORS_AD7418 is not set | ||
1103 | # CONFIG_SENSORS_ADCXX is not set | ||
1104 | # CONFIG_SENSORS_ADM1021 is not set | ||
1105 | # CONFIG_SENSORS_ADM1025 is not set | ||
1106 | # CONFIG_SENSORS_ADM1026 is not set | ||
1107 | # CONFIG_SENSORS_ADM1029 is not set | ||
1108 | # CONFIG_SENSORS_ADM1031 is not set | ||
1109 | # CONFIG_SENSORS_ADM9240 is not set | ||
1110 | # CONFIG_SENSORS_ADT7462 is not set | ||
1111 | # CONFIG_SENSORS_ADT7470 is not set | ||
1112 | # CONFIG_SENSORS_ADT7473 is not set | ||
1113 | # CONFIG_SENSORS_ADT7475 is not set | ||
1114 | # CONFIG_SENSORS_ATXP1 is not set | ||
1115 | # CONFIG_SENSORS_DS1621 is not set | ||
1116 | # CONFIG_SENSORS_F71805F is not set | ||
1117 | # CONFIG_SENSORS_F71882FG is not set | ||
1118 | # CONFIG_SENSORS_F75375S is not set | ||
1119 | # CONFIG_SENSORS_G760A is not set | ||
1120 | # CONFIG_SENSORS_GL518SM is not set | ||
1121 | # CONFIG_SENSORS_GL520SM is not set | ||
1122 | # CONFIG_SENSORS_IT87 is not set | ||
1123 | # CONFIG_SENSORS_LM63 is not set | ||
1124 | # CONFIG_SENSORS_LM70 is not set | ||
1125 | CONFIG_SENSORS_LM75=m | ||
1126 | # CONFIG_SENSORS_LM77 is not set | ||
1127 | # CONFIG_SENSORS_LM78 is not set | ||
1128 | # CONFIG_SENSORS_LM80 is not set | ||
1129 | # CONFIG_SENSORS_LM83 is not set | ||
1130 | # CONFIG_SENSORS_LM85 is not set | ||
1131 | # CONFIG_SENSORS_LM87 is not set | ||
1132 | # CONFIG_SENSORS_LM90 is not set | ||
1133 | # CONFIG_SENSORS_LM92 is not set | ||
1134 | # CONFIG_SENSORS_LM93 is not set | ||
1135 | # CONFIG_SENSORS_LTC4215 is not set | ||
1136 | # CONFIG_SENSORS_LTC4245 is not set | ||
1137 | # CONFIG_SENSORS_LM95241 is not set | ||
1138 | # CONFIG_SENSORS_MAX1111 is not set | ||
1139 | # CONFIG_SENSORS_MAX1619 is not set | ||
1140 | # CONFIG_SENSORS_MAX6650 is not set | ||
1141 | # CONFIG_SENSORS_PC87360 is not set | ||
1142 | # CONFIG_SENSORS_PC87427 is not set | ||
1143 | # CONFIG_SENSORS_PCF8591 is not set | ||
1144 | # CONFIG_SENSORS_SHT15 is not set | ||
1145 | # CONFIG_SENSORS_DME1737 is not set | ||
1146 | # CONFIG_SENSORS_SMSC47M1 is not set | ||
1147 | # CONFIG_SENSORS_SMSC47M192 is not set | ||
1148 | # CONFIG_SENSORS_SMSC47B397 is not set | ||
1149 | # CONFIG_SENSORS_ADS7828 is not set | ||
1150 | # CONFIG_SENSORS_THMC50 is not set | ||
1151 | # CONFIG_SENSORS_TMP401 is not set | ||
1152 | # CONFIG_SENSORS_TMP421 is not set | ||
1153 | # CONFIG_SENSORS_VT1211 is not set | ||
1154 | # CONFIG_SENSORS_W83781D is not set | ||
1155 | # CONFIG_SENSORS_W83791D is not set | ||
1156 | # CONFIG_SENSORS_W83792D is not set | ||
1157 | # CONFIG_SENSORS_W83793 is not set | ||
1158 | # CONFIG_SENSORS_W83L785TS is not set | ||
1159 | # CONFIG_SENSORS_W83L786NG is not set | ||
1160 | # CONFIG_SENSORS_W83627HF is not set | ||
1161 | # CONFIG_SENSORS_W83627EHF is not set | ||
1162 | # CONFIG_SENSORS_LIS3_SPI is not set | ||
1163 | # CONFIG_THERMAL is not set | ||
1164 | CONFIG_WATCHDOG=y | ||
1165 | # CONFIG_WATCHDOG_NOWAYOUT is not set | ||
1166 | |||
1167 | # | ||
1168 | # Watchdog Device Drivers | ||
1169 | # | ||
1170 | # CONFIG_SOFT_WATCHDOG is not set | ||
1171 | # CONFIG_SA1100_WATCHDOG is not set | ||
1172 | |||
1173 | # | ||
1174 | # ISA-based Watchdog Cards | ||
1175 | # | ||
1176 | # CONFIG_PCWATCHDOG is not set | ||
1177 | # CONFIG_MIXCOMWD is not set | ||
1178 | # CONFIG_WDT is not set | ||
1179 | |||
1180 | # | ||
1181 | # USB-based Watchdog Cards | ||
1182 | # | ||
1183 | # CONFIG_USBPCWATCHDOG is not set | ||
1184 | CONFIG_SSB_POSSIBLE=y | ||
1185 | |||
1186 | # | ||
1187 | # Sonics Silicon Backplane | ||
1188 | # | ||
1189 | # CONFIG_SSB is not set | ||
1190 | |||
1191 | # | ||
1192 | # Multifunction device drivers | ||
1193 | # | ||
1194 | # CONFIG_MFD_CORE is not set | ||
1195 | # CONFIG_MFD_SM501 is not set | ||
1196 | # CONFIG_MFD_ASIC3 is not set | ||
1197 | # CONFIG_HTC_EGPIO is not set | ||
1198 | # CONFIG_HTC_PASIC3 is not set | ||
1199 | # CONFIG_UCB1400_CORE is not set | ||
1200 | # CONFIG_TPS65010 is not set | ||
1201 | # CONFIG_TWL4030_CORE is not set | ||
1202 | # CONFIG_MFD_TMIO is not set | ||
1203 | # CONFIG_MFD_T7L66XB is not set | ||
1204 | # CONFIG_MFD_TC6387XB is not set | ||
1205 | # CONFIG_MFD_TC6393XB is not set | ||
1206 | # CONFIG_PMIC_DA903X is not set | ||
1207 | # CONFIG_MFD_WM8400 is not set | ||
1208 | # CONFIG_MFD_WM831X is not set | ||
1209 | # CONFIG_MFD_WM8350_I2C is not set | ||
1210 | # CONFIG_MFD_PCF50633 is not set | ||
1211 | # CONFIG_MFD_MC13783 is not set | ||
1212 | # CONFIG_AB3100_CORE is not set | ||
1213 | # CONFIG_EZX_PCAP is not set | ||
1214 | # CONFIG_REGULATOR is not set | ||
1215 | # CONFIG_MEDIA_SUPPORT is not set | ||
1216 | |||
1217 | # | ||
1218 | # Graphics support | ||
1219 | # | ||
1220 | # CONFIG_VGASTATE is not set | ||
1221 | # CONFIG_VIDEO_OUTPUT_CONTROL is not set | ||
1222 | CONFIG_FB=y | ||
1223 | # CONFIG_FIRMWARE_EDID is not set | ||
1224 | # CONFIG_FB_DDC is not set | ||
1225 | # CONFIG_FB_BOOT_VESA_SUPPORT is not set | ||
1226 | CONFIG_FB_CFB_FILLRECT=m | ||
1227 | CONFIG_FB_CFB_COPYAREA=m | ||
1228 | CONFIG_FB_CFB_IMAGEBLIT=m | ||
1229 | # CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set | ||
1230 | # CONFIG_FB_SYS_FILLRECT is not set | ||
1231 | # CONFIG_FB_SYS_COPYAREA is not set | ||
1232 | # CONFIG_FB_SYS_IMAGEBLIT is not set | ||
1233 | # CONFIG_FB_FOREIGN_ENDIAN is not set | ||
1234 | # CONFIG_FB_SYS_FOPS is not set | ||
1235 | # CONFIG_FB_SVGALIB is not set | ||
1236 | # CONFIG_FB_MACMODES is not set | ||
1237 | # CONFIG_FB_BACKLIGHT is not set | ||
1238 | # CONFIG_FB_MODE_HELPERS is not set | ||
1239 | # CONFIG_FB_TILEBLITTING is not set | ||
1240 | |||
1241 | # | ||
1242 | # Frame buffer hardware drivers | ||
1243 | # | ||
1244 | # CONFIG_FB_S1D13XXX is not set | ||
1245 | CONFIG_FB_PXA=m | ||
1246 | # CONFIG_FB_PXA_OVERLAY is not set | ||
1247 | # CONFIG_FB_PXA_SMARTPANEL is not set | ||
1248 | CONFIG_FB_PXA_PARAMETERS=y | ||
1249 | # CONFIG_FB_MBX is not set | ||
1250 | # CONFIG_FB_W100 is not set | ||
1251 | # CONFIG_FB_VIRTUAL is not set | ||
1252 | # CONFIG_FB_METRONOME is not set | ||
1253 | # CONFIG_FB_MB862XX is not set | ||
1254 | # CONFIG_FB_BROADSHEET is not set | ||
1255 | CONFIG_BACKLIGHT_LCD_SUPPORT=y | ||
1256 | CONFIG_LCD_CLASS_DEVICE=m | ||
1257 | # CONFIG_LCD_LMS283GF05 is not set | ||
1258 | # CONFIG_LCD_LTV350QV is not set | ||
1259 | # CONFIG_LCD_ILI9320 is not set | ||
1260 | # CONFIG_LCD_TDO24M is not set | ||
1261 | # CONFIG_LCD_VGG2432A4 is not set | ||
1262 | # CONFIG_LCD_PLATFORM is not set | ||
1263 | CONFIG_BACKLIGHT_CLASS_DEVICE=m | ||
1264 | CONFIG_BACKLIGHT_GENERIC=m | ||
1265 | |||
1266 | # | ||
1267 | # Display device support | ||
1268 | # | ||
1269 | # CONFIG_DISPLAY_SUPPORT is not set | ||
1270 | |||
1271 | # | ||
1272 | # Console display driver support | ||
1273 | # | ||
1274 | # CONFIG_VGA_CONSOLE is not set | ||
1275 | # CONFIG_MDA_CONSOLE is not set | ||
1276 | CONFIG_DUMMY_CONSOLE=y | ||
1277 | CONFIG_FRAMEBUFFER_CONSOLE=m | ||
1278 | # CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set | ||
1279 | # CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set | ||
1280 | # CONFIG_FONTS is not set | ||
1281 | CONFIG_FONT_8x8=y | ||
1282 | CONFIG_FONT_8x16=y | ||
1283 | CONFIG_LOGO=y | ||
1284 | CONFIG_LOGO_LINUX_MONO=y | ||
1285 | CONFIG_LOGO_LINUX_VGA16=y | ||
1286 | CONFIG_LOGO_LINUX_CLUT224=y | ||
1287 | CONFIG_SOUND=m | ||
1288 | CONFIG_SOUND_OSS_CORE=y | ||
1289 | CONFIG_SOUND_OSS_CORE_PRECLAIM=y | ||
1290 | CONFIG_SND=m | ||
1291 | CONFIG_SND_TIMER=m | ||
1292 | CONFIG_SND_PCM=m | ||
1293 | CONFIG_SND_JACK=y | ||
1294 | # CONFIG_SND_SEQUENCER is not set | ||
1295 | CONFIG_SND_OSSEMUL=y | ||
1296 | CONFIG_SND_MIXER_OSS=m | ||
1297 | CONFIG_SND_PCM_OSS=m | ||
1298 | CONFIG_SND_PCM_OSS_PLUGINS=y | ||
1299 | # CONFIG_SND_DYNAMIC_MINORS is not set | ||
1300 | # CONFIG_SND_SUPPORT_OLD_API is not set | ||
1301 | CONFIG_SND_VERBOSE_PROCFS=y | ||
1302 | # CONFIG_SND_VERBOSE_PRINTK is not set | ||
1303 | # CONFIG_SND_DEBUG is not set | ||
1304 | CONFIG_SND_VMASTER=y | ||
1305 | # CONFIG_SND_RAWMIDI_SEQ is not set | ||
1306 | # CONFIG_SND_OPL3_LIB_SEQ is not set | ||
1307 | # CONFIG_SND_OPL4_LIB_SEQ is not set | ||
1308 | # CONFIG_SND_SBAWE_SEQ is not set | ||
1309 | # CONFIG_SND_EMU10K1_SEQ is not set | ||
1310 | CONFIG_SND_AC97_CODEC=m | ||
1311 | CONFIG_SND_DRIVERS=y | ||
1312 | # CONFIG_SND_DUMMY is not set | ||
1313 | # CONFIG_SND_MTPAV is not set | ||
1314 | # CONFIG_SND_SERIAL_U16550 is not set | ||
1315 | # CONFIG_SND_MPU401 is not set | ||
1316 | # CONFIG_SND_AC97_POWER_SAVE is not set | ||
1317 | CONFIG_SND_ARM=y | ||
1318 | CONFIG_SND_PXA2XX_PCM=m | ||
1319 | CONFIG_SND_PXA2XX_LIB=m | ||
1320 | CONFIG_SND_PXA2XX_LIB_AC97=y | ||
1321 | CONFIG_SND_PXA2XX_AC97=m | ||
1322 | # CONFIG_SND_SPI is not set | ||
1323 | CONFIG_SND_USB=y | ||
1324 | # CONFIG_SND_USB_AUDIO is not set | ||
1325 | # CONFIG_SND_USB_CAIAQ is not set | ||
1326 | # CONFIG_SND_PCMCIA is not set | ||
1327 | CONFIG_SND_SOC=m | ||
1328 | CONFIG_SND_PXA2XX_SOC=m | ||
1329 | CONFIG_SND_SOC_I2C_AND_SPI=m | ||
1330 | # CONFIG_SND_SOC_ALL_CODECS is not set | ||
1331 | # CONFIG_SOUND_PRIME is not set | ||
1332 | CONFIG_AC97_BUS=m | ||
1333 | # CONFIG_HID_SUPPORT is not set | ||
1334 | CONFIG_USB_SUPPORT=y | ||
1335 | CONFIG_USB_ARCH_HAS_HCD=y | ||
1336 | CONFIG_USB_ARCH_HAS_OHCI=y | ||
1337 | # CONFIG_USB_ARCH_HAS_EHCI is not set | ||
1338 | CONFIG_USB=m | ||
1339 | # CONFIG_USB_DEBUG is not set | ||
1340 | # CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set | ||
1341 | |||
1342 | # | ||
1343 | # Miscellaneous USB options | ||
1344 | # | ||
1345 | CONFIG_USB_DEVICEFS=y | ||
1346 | CONFIG_USB_DEVICE_CLASS=y | ||
1347 | # CONFIG_USB_DYNAMIC_MINORS is not set | ||
1348 | CONFIG_USB_SUSPEND=y | ||
1349 | # CONFIG_USB_OTG is not set | ||
1350 | # CONFIG_USB_MON is not set | ||
1351 | # CONFIG_USB_WUSB is not set | ||
1352 | # CONFIG_USB_WUSB_CBAF is not set | ||
1353 | |||
1354 | # | ||
1355 | # USB Host Controller Drivers | ||
1356 | # | ||
1357 | # CONFIG_USB_C67X00_HCD is not set | ||
1358 | # CONFIG_USB_OXU210HP_HCD is not set | ||
1359 | # CONFIG_USB_ISP116X_HCD is not set | ||
1360 | # CONFIG_USB_ISP1760_HCD is not set | ||
1361 | # CONFIG_USB_ISP1362_HCD is not set | ||
1362 | CONFIG_USB_OHCI_HCD=m | ||
1363 | # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set | ||
1364 | # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set | ||
1365 | CONFIG_USB_OHCI_LITTLE_ENDIAN=y | ||
1366 | # CONFIG_USB_SL811_HCD is not set | ||
1367 | # CONFIG_USB_R8A66597_HCD is not set | ||
1368 | # CONFIG_USB_HWA_HCD is not set | ||
1369 | # CONFIG_USB_MUSB_HDRC is not set | ||
1370 | # CONFIG_USB_GADGET_MUSB_HDRC is not set | ||
1371 | |||
1372 | # | ||
1373 | # USB Device Class drivers | ||
1374 | # | ||
1375 | CONFIG_USB_ACM=m | ||
1376 | # CONFIG_USB_PRINTER is not set | ||
1377 | # CONFIG_USB_WDM is not set | ||
1378 | # CONFIG_USB_TMC is not set | ||
1379 | |||
1380 | # | ||
1381 | # NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may | ||
1382 | # | ||
1383 | |||
1384 | # | ||
1385 | # also be needed; see USB_STORAGE Help for more info | ||
1386 | # | ||
1387 | CONFIG_USB_STORAGE=m | ||
1388 | # CONFIG_USB_STORAGE_DEBUG is not set | ||
1389 | # CONFIG_USB_STORAGE_DATAFAB is not set | ||
1390 | # CONFIG_USB_STORAGE_FREECOM is not set | ||
1391 | # CONFIG_USB_STORAGE_ISD200 is not set | ||
1392 | # CONFIG_USB_STORAGE_USBAT is not set | ||
1393 | # CONFIG_USB_STORAGE_SDDR09 is not set | ||
1394 | # CONFIG_USB_STORAGE_SDDR55 is not set | ||
1395 | # CONFIG_USB_STORAGE_JUMPSHOT is not set | ||
1396 | # CONFIG_USB_STORAGE_ALAUDA is not set | ||
1397 | # CONFIG_USB_STORAGE_ONETOUCH is not set | ||
1398 | # CONFIG_USB_STORAGE_KARMA is not set | ||
1399 | # CONFIG_USB_STORAGE_CYPRESS_ATACB is not set | ||
1400 | # CONFIG_USB_LIBUSUAL is not set | ||
1401 | |||
1402 | # | ||
1403 | # USB Imaging devices | ||
1404 | # | ||
1405 | # CONFIG_USB_MDC800 is not set | ||
1406 | # CONFIG_USB_MICROTEK is not set | ||
1407 | |||
1408 | # | ||
1409 | # USB port drivers | ||
1410 | # | ||
1411 | CONFIG_USB_SERIAL=m | ||
1412 | # CONFIG_USB_EZUSB is not set | ||
1413 | CONFIG_USB_SERIAL_GENERIC=y | ||
1414 | # CONFIG_USB_SERIAL_AIRCABLE is not set | ||
1415 | # CONFIG_USB_SERIAL_ARK3116 is not set | ||
1416 | # CONFIG_USB_SERIAL_BELKIN is not set | ||
1417 | # CONFIG_USB_SERIAL_CH341 is not set | ||
1418 | # CONFIG_USB_SERIAL_WHITEHEAT is not set | ||
1419 | # CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set | ||
1420 | # CONFIG_USB_SERIAL_CP210X is not set | ||
1421 | # CONFIG_USB_SERIAL_CYPRESS_M8 is not set | ||
1422 | # CONFIG_USB_SERIAL_EMPEG is not set | ||
1423 | # CONFIG_USB_SERIAL_FTDI_SIO is not set | ||
1424 | # CONFIG_USB_SERIAL_FUNSOFT is not set | ||
1425 | # CONFIG_USB_SERIAL_VISOR is not set | ||
1426 | # CONFIG_USB_SERIAL_IPAQ is not set | ||
1427 | # CONFIG_USB_SERIAL_IR is not set | ||
1428 | # CONFIG_USB_SERIAL_EDGEPORT is not set | ||
1429 | # CONFIG_USB_SERIAL_EDGEPORT_TI is not set | ||
1430 | # CONFIG_USB_SERIAL_GARMIN is not set | ||
1431 | # CONFIG_USB_SERIAL_IPW is not set | ||
1432 | # CONFIG_USB_SERIAL_IUU is not set | ||
1433 | # CONFIG_USB_SERIAL_KEYSPAN_PDA is not set | ||
1434 | # CONFIG_USB_SERIAL_KEYSPAN is not set | ||
1435 | # CONFIG_USB_SERIAL_KLSI is not set | ||
1436 | # CONFIG_USB_SERIAL_KOBIL_SCT is not set | ||
1437 | CONFIG_USB_SERIAL_MCT_U232=m | ||
1438 | # CONFIG_USB_SERIAL_MOS7720 is not set | ||
1439 | # CONFIG_USB_SERIAL_MOS7840 is not set | ||
1440 | # CONFIG_USB_SERIAL_MOTOROLA is not set | ||
1441 | # CONFIG_USB_SERIAL_NAVMAN is not set | ||
1442 | # CONFIG_USB_SERIAL_PL2303 is not set | ||
1443 | # CONFIG_USB_SERIAL_OTI6858 is not set | ||
1444 | # CONFIG_USB_SERIAL_QUALCOMM is not set | ||
1445 | # CONFIG_USB_SERIAL_SPCP8X5 is not set | ||
1446 | # CONFIG_USB_SERIAL_HP4X is not set | ||
1447 | # CONFIG_USB_SERIAL_SAFE is not set | ||
1448 | # CONFIG_USB_SERIAL_SIEMENS_MPI is not set | ||
1449 | # CONFIG_USB_SERIAL_SIERRAWIRELESS is not set | ||
1450 | # CONFIG_USB_SERIAL_SYMBOL is not set | ||
1451 | # CONFIG_USB_SERIAL_TI is not set | ||
1452 | # CONFIG_USB_SERIAL_CYBERJACK is not set | ||
1453 | # CONFIG_USB_SERIAL_XIRCOM is not set | ||
1454 | # CONFIG_USB_SERIAL_OPTION is not set | ||
1455 | # CONFIG_USB_SERIAL_OMNINET is not set | ||
1456 | # CONFIG_USB_SERIAL_OPTICON is not set | ||
1457 | # CONFIG_USB_SERIAL_DEBUG is not set | ||
1458 | |||
1459 | # | ||
1460 | # USB Miscellaneous drivers | ||
1461 | # | ||
1462 | # CONFIG_USB_EMI62 is not set | ||
1463 | # CONFIG_USB_EMI26 is not set | ||
1464 | # CONFIG_USB_ADUTUX is not set | ||
1465 | # CONFIG_USB_SEVSEG is not set | ||
1466 | # CONFIG_USB_RIO500 is not set | ||
1467 | # CONFIG_USB_LEGOTOWER is not set | ||
1468 | # CONFIG_USB_LCD is not set | ||
1469 | # CONFIG_USB_BERRY_CHARGE is not set | ||
1470 | # CONFIG_USB_LED is not set | ||
1471 | # CONFIG_USB_CYPRESS_CY7C63 is not set | ||
1472 | # CONFIG_USB_CYTHERM is not set | ||
1473 | # CONFIG_USB_IDMOUSE is not set | ||
1474 | # CONFIG_USB_FTDI_ELAN is not set | ||
1475 | # CONFIG_USB_APPLEDISPLAY is not set | ||
1476 | # CONFIG_USB_LD is not set | ||
1477 | # CONFIG_USB_TRANCEVIBRATOR is not set | ||
1478 | # CONFIG_USB_IOWARRIOR is not set | ||
1479 | # CONFIG_USB_TEST is not set | ||
1480 | # CONFIG_USB_ISIGHTFW is not set | ||
1481 | # CONFIG_USB_VST is not set | ||
1482 | CONFIG_USB_GADGET=m | ||
1483 | # CONFIG_USB_GADGET_DEBUG is not set | ||
1484 | # CONFIG_USB_GADGET_DEBUG_FILES is not set | ||
1485 | CONFIG_USB_GADGET_VBUS_DRAW=2 | ||
1486 | CONFIG_USB_GADGET_SELECTED=y | ||
1487 | # CONFIG_USB_GADGET_AT91 is not set | ||
1488 | # CONFIG_USB_GADGET_ATMEL_USBA is not set | ||
1489 | # CONFIG_USB_GADGET_FSL_USB2 is not set | ||
1490 | # CONFIG_USB_GADGET_LH7A40X is not set | ||
1491 | # CONFIG_USB_GADGET_OMAP is not set | ||
1492 | # CONFIG_USB_GADGET_PXA25X is not set | ||
1493 | # CONFIG_USB_GADGET_R8A66597 is not set | ||
1494 | CONFIG_USB_GADGET_PXA27X=y | ||
1495 | CONFIG_USB_PXA27X=m | ||
1496 | # CONFIG_USB_GADGET_S3C_HSOTG is not set | ||
1497 | # CONFIG_USB_GADGET_IMX is not set | ||
1498 | # CONFIG_USB_GADGET_S3C2410 is not set | ||
1499 | # CONFIG_USB_GADGET_M66592 is not set | ||
1500 | # CONFIG_USB_GADGET_AMD5536UDC is not set | ||
1501 | # CONFIG_USB_GADGET_FSL_QE is not set | ||
1502 | # CONFIG_USB_GADGET_CI13XXX is not set | ||
1503 | # CONFIG_USB_GADGET_NET2280 is not set | ||
1504 | # CONFIG_USB_GADGET_GOKU is not set | ||
1505 | # CONFIG_USB_GADGET_LANGWELL is not set | ||
1506 | # CONFIG_USB_GADGET_DUMMY_HCD is not set | ||
1507 | # CONFIG_USB_GADGET_DUALSPEED is not set | ||
1508 | # CONFIG_USB_ZERO is not set | ||
1509 | # CONFIG_USB_AUDIO is not set | ||
1510 | CONFIG_USB_ETH=m | ||
1511 | CONFIG_USB_ETH_RNDIS=y | ||
1512 | # CONFIG_USB_ETH_EEM is not set | ||
1513 | CONFIG_USB_GADGETFS=m | ||
1514 | CONFIG_USB_FILE_STORAGE=m | ||
1515 | # CONFIG_USB_FILE_STORAGE_TEST is not set | ||
1516 | CONFIG_USB_G_SERIAL=m | ||
1517 | # CONFIG_USB_MIDI_GADGET is not set | ||
1518 | CONFIG_USB_G_PRINTER=m | ||
1519 | # CONFIG_USB_CDC_COMPOSITE is not set | ||
1520 | |||
1521 | # | ||
1522 | # OTG and related infrastructure | ||
1523 | # | ||
1524 | CONFIG_USB_OTG_UTILS=y | ||
1525 | # CONFIG_USB_GPIO_VBUS is not set | ||
1526 | # CONFIG_NOP_USB_XCEIV is not set | ||
1527 | CONFIG_MMC=y | ||
1528 | # CONFIG_MMC_DEBUG is not set | ||
1529 | # CONFIG_MMC_UNSAFE_RESUME is not set | ||
1530 | |||
1531 | # | ||
1532 | # MMC/SD/SDIO Card Drivers | ||
1533 | # | ||
1534 | CONFIG_MMC_BLOCK=y | ||
1535 | # CONFIG_MMC_BLOCK_BOUNCE is not set | ||
1536 | # CONFIG_SDIO_UART is not set | ||
1537 | # CONFIG_MMC_TEST is not set | ||
1538 | |||
1539 | # | ||
1540 | # MMC/SD/SDIO Host Controller Drivers | ||
1541 | # | ||
1542 | CONFIG_MMC_PXA=y | ||
1543 | # CONFIG_MMC_SDHCI is not set | ||
1544 | # CONFIG_MMC_AT91 is not set | ||
1545 | # CONFIG_MMC_ATMELMCI is not set | ||
1546 | # CONFIG_MMC_SPI is not set | ||
1547 | # CONFIG_MEMSTICK is not set | ||
1548 | CONFIG_NEW_LEDS=y | ||
1549 | CONFIG_LEDS_CLASS=m | ||
1550 | |||
1551 | # | ||
1552 | # LED drivers | ||
1553 | # | ||
1554 | # CONFIG_LEDS_PCA9532 is not set | ||
1555 | CONFIG_LEDS_GPIO=m | ||
1556 | CONFIG_LEDS_GPIO_PLATFORM=y | ||
1557 | # CONFIG_LEDS_LP3944 is not set | ||
1558 | # CONFIG_LEDS_PCA955X is not set | ||
1559 | # CONFIG_LEDS_DAC124S085 is not set | ||
1560 | # CONFIG_LEDS_BD2802 is not set | ||
1561 | |||
1562 | # | ||
1563 | # LED Triggers | ||
1564 | # | ||
1565 | CONFIG_LEDS_TRIGGERS=y | ||
1566 | CONFIG_LEDS_TRIGGER_TIMER=m | ||
1567 | CONFIG_LEDS_TRIGGER_HEARTBEAT=m | ||
1568 | CONFIG_LEDS_TRIGGER_BACKLIGHT=m | ||
1569 | CONFIG_LEDS_TRIGGER_GPIO=m | ||
1570 | CONFIG_LEDS_TRIGGER_DEFAULT_ON=m | ||
1571 | |||
1572 | # | ||
1573 | # iptables trigger is under Netfilter config (LED target) | ||
1574 | # | ||
1575 | # CONFIG_ACCESSIBILITY is not set | ||
1576 | CONFIG_RTC_LIB=y | ||
1577 | CONFIG_RTC_CLASS=m | ||
1578 | |||
1579 | # | ||
1580 | # RTC interfaces | ||
1581 | # | ||
1582 | CONFIG_RTC_INTF_SYSFS=y | ||
1583 | CONFIG_RTC_INTF_PROC=y | ||
1584 | CONFIG_RTC_INTF_DEV=y | ||
1585 | # CONFIG_RTC_INTF_DEV_UIE_EMUL is not set | ||
1586 | # CONFIG_RTC_DRV_TEST is not set | ||
1587 | |||
1588 | # | ||
1589 | # I2C RTC drivers | ||
1590 | # | ||
1591 | # CONFIG_RTC_DRV_DS1307 is not set | ||
1592 | # CONFIG_RTC_DRV_DS1374 is not set | ||
1593 | # CONFIG_RTC_DRV_DS1672 is not set | ||
1594 | # CONFIG_RTC_DRV_MAX6900 is not set | ||
1595 | # CONFIG_RTC_DRV_RS5C372 is not set | ||
1596 | CONFIG_RTC_DRV_ISL1208=m | ||
1597 | # CONFIG_RTC_DRV_X1205 is not set | ||
1598 | # CONFIG_RTC_DRV_PCF8563 is not set | ||
1599 | # CONFIG_RTC_DRV_PCF8583 is not set | ||
1600 | # CONFIG_RTC_DRV_M41T80 is not set | ||
1601 | # CONFIG_RTC_DRV_S35390A is not set | ||
1602 | # CONFIG_RTC_DRV_FM3130 is not set | ||
1603 | # CONFIG_RTC_DRV_RX8581 is not set | ||
1604 | # CONFIG_RTC_DRV_RX8025 is not set | ||
1605 | |||
1606 | # | ||
1607 | # SPI RTC drivers | ||
1608 | # | ||
1609 | # CONFIG_RTC_DRV_M41T94 is not set | ||
1610 | # CONFIG_RTC_DRV_DS1305 is not set | ||
1611 | # CONFIG_RTC_DRV_DS1390 is not set | ||
1612 | # CONFIG_RTC_DRV_MAX6902 is not set | ||
1613 | # CONFIG_RTC_DRV_R9701 is not set | ||
1614 | # CONFIG_RTC_DRV_RS5C348 is not set | ||
1615 | # CONFIG_RTC_DRV_DS3234 is not set | ||
1616 | # CONFIG_RTC_DRV_PCF2123 is not set | ||
1617 | |||
1618 | # | ||
1619 | # Platform RTC drivers | ||
1620 | # | ||
1621 | # CONFIG_RTC_DRV_CMOS is not set | ||
1622 | # CONFIG_RTC_DRV_DS1286 is not set | ||
1623 | # CONFIG_RTC_DRV_DS1511 is not set | ||
1624 | # CONFIG_RTC_DRV_DS1553 is not set | ||
1625 | # CONFIG_RTC_DRV_DS1742 is not set | ||
1626 | # CONFIG_RTC_DRV_STK17TA8 is not set | ||
1627 | # CONFIG_RTC_DRV_M48T86 is not set | ||
1628 | # CONFIG_RTC_DRV_M48T35 is not set | ||
1629 | # CONFIG_RTC_DRV_M48T59 is not set | ||
1630 | # CONFIG_RTC_DRV_MSM6242 is not set | ||
1631 | # CONFIG_RTC_DRV_BQ4802 is not set | ||
1632 | # CONFIG_RTC_DRV_RP5C01 is not set | ||
1633 | # CONFIG_RTC_DRV_V3020 is not set | ||
1634 | |||
1635 | # | ||
1636 | # on-CPU RTC drivers | ||
1637 | # | ||
1638 | # CONFIG_RTC_DRV_SA1100 is not set | ||
1639 | CONFIG_RTC_DRV_PXA=m | ||
1640 | # CONFIG_DMADEVICES is not set | ||
1641 | # CONFIG_AUXDISPLAY is not set | ||
1642 | # CONFIG_UIO is not set | ||
1643 | |||
1644 | # | ||
1645 | # TI VLYNQ | ||
1646 | # | ||
1647 | # CONFIG_STAGING is not set | ||
1648 | |||
1649 | # | ||
1650 | # File systems | ||
1651 | # | ||
1652 | CONFIG_EXT2_FS=y | ||
1653 | # CONFIG_EXT2_FS_XATTR is not set | ||
1654 | # CONFIG_EXT2_FS_XIP is not set | ||
1655 | CONFIG_EXT3_FS=y | ||
1656 | # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set | ||
1657 | # CONFIG_EXT3_FS_XATTR is not set | ||
1658 | # CONFIG_EXT4_FS is not set | ||
1659 | CONFIG_JBD=y | ||
1660 | # CONFIG_REISERFS_FS is not set | ||
1661 | # CONFIG_JFS_FS is not set | ||
1662 | # CONFIG_FS_POSIX_ACL is not set | ||
1663 | # CONFIG_XFS_FS is not set | ||
1664 | # CONFIG_GFS2_FS is not set | ||
1665 | # CONFIG_OCFS2_FS is not set | ||
1666 | # CONFIG_BTRFS_FS is not set | ||
1667 | # CONFIG_NILFS2_FS is not set | ||
1668 | CONFIG_FILE_LOCKING=y | ||
1669 | CONFIG_FSNOTIFY=y | ||
1670 | # CONFIG_DNOTIFY is not set | ||
1671 | CONFIG_INOTIFY=y | ||
1672 | CONFIG_INOTIFY_USER=y | ||
1673 | # CONFIG_QUOTA is not set | ||
1674 | # CONFIG_AUTOFS_FS is not set | ||
1675 | # CONFIG_AUTOFS4_FS is not set | ||
1676 | # CONFIG_FUSE_FS is not set | ||
1677 | |||
1678 | # | ||
1679 | # Caches | ||
1680 | # | ||
1681 | # CONFIG_FSCACHE is not set | ||
1682 | |||
1683 | # | ||
1684 | # CD-ROM/DVD Filesystems | ||
1685 | # | ||
1686 | # CONFIG_ISO9660_FS is not set | ||
1687 | # CONFIG_UDF_FS is not set | ||
1688 | |||
1689 | # | ||
1690 | # DOS/FAT/NT Filesystems | ||
1691 | # | ||
1692 | CONFIG_FAT_FS=m | ||
1693 | # CONFIG_MSDOS_FS is not set | ||
1694 | CONFIG_VFAT_FS=m | ||
1695 | CONFIG_FAT_DEFAULT_CODEPAGE=437 | ||
1696 | CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" | ||
1697 | # CONFIG_NTFS_FS is not set | ||
1698 | |||
1699 | # | ||
1700 | # Pseudo filesystems | ||
1701 | # | ||
1702 | CONFIG_PROC_FS=y | ||
1703 | CONFIG_PROC_SYSCTL=y | ||
1704 | CONFIG_PROC_PAGE_MONITOR=y | ||
1705 | CONFIG_SYSFS=y | ||
1706 | CONFIG_TMPFS=y | ||
1707 | # CONFIG_TMPFS_POSIX_ACL is not set | ||
1708 | # CONFIG_HUGETLB_PAGE is not set | ||
1709 | # CONFIG_CONFIGFS_FS is not set | ||
1710 | CONFIG_MISC_FILESYSTEMS=y | ||
1711 | # CONFIG_ADFS_FS is not set | ||
1712 | # CONFIG_AFFS_FS is not set | ||
1713 | # CONFIG_HFS_FS is not set | ||
1714 | # CONFIG_HFSPLUS_FS is not set | ||
1715 | # CONFIG_BEFS_FS is not set | ||
1716 | # CONFIG_BFS_FS is not set | ||
1717 | # CONFIG_EFS_FS is not set | ||
1718 | CONFIG_JFFS2_FS=y | ||
1719 | CONFIG_JFFS2_FS_DEBUG=0 | ||
1720 | CONFIG_JFFS2_FS_WRITEBUFFER=y | ||
1721 | # CONFIG_JFFS2_FS_WBUF_VERIFY is not set | ||
1722 | # CONFIG_JFFS2_SUMMARY is not set | ||
1723 | # CONFIG_JFFS2_FS_XATTR is not set | ||
1724 | # CONFIG_JFFS2_COMPRESSION_OPTIONS is not set | ||
1725 | CONFIG_JFFS2_ZLIB=y | ||
1726 | # CONFIG_JFFS2_LZO is not set | ||
1727 | CONFIG_JFFS2_RTIME=y | ||
1728 | # CONFIG_JFFS2_RUBIN is not set | ||
1729 | # CONFIG_CRAMFS is not set | ||
1730 | # CONFIG_SQUASHFS is not set | ||
1731 | # CONFIG_VXFS_FS is not set | ||
1732 | # CONFIG_MINIX_FS is not set | ||
1733 | # CONFIG_OMFS_FS is not set | ||
1734 | # CONFIG_HPFS_FS is not set | ||
1735 | # CONFIG_QNX4FS_FS is not set | ||
1736 | # CONFIG_ROMFS_FS is not set | ||
1737 | # CONFIG_SYSV_FS is not set | ||
1738 | # CONFIG_UFS_FS is not set | ||
1739 | CONFIG_NETWORK_FILESYSTEMS=y | ||
1740 | CONFIG_NFS_FS=y | ||
1741 | CONFIG_NFS_V3=y | ||
1742 | # CONFIG_NFS_V3_ACL is not set | ||
1743 | # CONFIG_NFS_V4 is not set | ||
1744 | CONFIG_ROOT_NFS=y | ||
1745 | CONFIG_NFSD=m | ||
1746 | CONFIG_NFSD_V3=y | ||
1747 | # CONFIG_NFSD_V3_ACL is not set | ||
1748 | # CONFIG_NFSD_V4 is not set | ||
1749 | CONFIG_LOCKD=y | ||
1750 | CONFIG_LOCKD_V4=y | ||
1751 | CONFIG_EXPORTFS=m | ||
1752 | CONFIG_NFS_COMMON=y | ||
1753 | CONFIG_SUNRPC=y | ||
1754 | # CONFIG_RPCSEC_GSS_KRB5 is not set | ||
1755 | # CONFIG_RPCSEC_GSS_SPKM3 is not set | ||
1756 | # CONFIG_SMB_FS is not set | ||
1757 | # CONFIG_CIFS is not set | ||
1758 | # CONFIG_NCP_FS is not set | ||
1759 | # CONFIG_CODA_FS is not set | ||
1760 | # CONFIG_AFS_FS is not set | ||
1761 | |||
1762 | # | ||
1763 | # Partition Types | ||
1764 | # | ||
1765 | CONFIG_PARTITION_ADVANCED=y | ||
1766 | # CONFIG_ACORN_PARTITION is not set | ||
1767 | # CONFIG_OSF_PARTITION is not set | ||
1768 | # CONFIG_AMIGA_PARTITION is not set | ||
1769 | # CONFIG_ATARI_PARTITION is not set | ||
1770 | # CONFIG_MAC_PARTITION is not set | ||
1771 | CONFIG_MSDOS_PARTITION=y | ||
1772 | # CONFIG_BSD_DISKLABEL is not set | ||
1773 | # CONFIG_MINIX_SUBPARTITION is not set | ||
1774 | # CONFIG_SOLARIS_X86_PARTITION is not set | ||
1775 | # CONFIG_UNIXWARE_DISKLABEL is not set | ||
1776 | # CONFIG_LDM_PARTITION is not set | ||
1777 | # CONFIG_SGI_PARTITION is not set | ||
1778 | # CONFIG_ULTRIX_PARTITION is not set | ||
1779 | # CONFIG_SUN_PARTITION is not set | ||
1780 | # CONFIG_KARMA_PARTITION is not set | ||
1781 | # CONFIG_EFI_PARTITION is not set | ||
1782 | # CONFIG_SYSV68_PARTITION is not set | ||
1783 | CONFIG_NLS=m | ||
1784 | CONFIG_NLS_DEFAULT="iso8859-1" | ||
1785 | CONFIG_NLS_CODEPAGE_437=m | ||
1786 | # CONFIG_NLS_CODEPAGE_737 is not set | ||
1787 | # CONFIG_NLS_CODEPAGE_775 is not set | ||
1788 | CONFIG_NLS_CODEPAGE_850=m | ||
1789 | # CONFIG_NLS_CODEPAGE_852 is not set | ||
1790 | # CONFIG_NLS_CODEPAGE_855 is not set | ||
1791 | # CONFIG_NLS_CODEPAGE_857 is not set | ||
1792 | # CONFIG_NLS_CODEPAGE_860 is not set | ||
1793 | # CONFIG_NLS_CODEPAGE_861 is not set | ||
1794 | # CONFIG_NLS_CODEPAGE_862 is not set | ||
1795 | # CONFIG_NLS_CODEPAGE_863 is not set | ||
1796 | # CONFIG_NLS_CODEPAGE_864 is not set | ||
1797 | # CONFIG_NLS_CODEPAGE_865 is not set | ||
1798 | # CONFIG_NLS_CODEPAGE_866 is not set | ||
1799 | # CONFIG_NLS_CODEPAGE_869 is not set | ||
1800 | # CONFIG_NLS_CODEPAGE_936 is not set | ||
1801 | # CONFIG_NLS_CODEPAGE_950 is not set | ||
1802 | # CONFIG_NLS_CODEPAGE_932 is not set | ||
1803 | # CONFIG_NLS_CODEPAGE_949 is not set | ||
1804 | # CONFIG_NLS_CODEPAGE_874 is not set | ||
1805 | # CONFIG_NLS_ISO8859_8 is not set | ||
1806 | # CONFIG_NLS_CODEPAGE_1250 is not set | ||
1807 | # CONFIG_NLS_CODEPAGE_1251 is not set | ||
1808 | # CONFIG_NLS_ASCII is not set | ||
1809 | CONFIG_NLS_ISO8859_1=m | ||
1810 | # CONFIG_NLS_ISO8859_2 is not set | ||
1811 | # CONFIG_NLS_ISO8859_3 is not set | ||
1812 | # CONFIG_NLS_ISO8859_4 is not set | ||
1813 | # CONFIG_NLS_ISO8859_5 is not set | ||
1814 | # CONFIG_NLS_ISO8859_6 is not set | ||
1815 | # CONFIG_NLS_ISO8859_7 is not set | ||
1816 | # CONFIG_NLS_ISO8859_9 is not set | ||
1817 | # CONFIG_NLS_ISO8859_13 is not set | ||
1818 | # CONFIG_NLS_ISO8859_14 is not set | ||
1819 | CONFIG_NLS_ISO8859_15=m | ||
1820 | # CONFIG_NLS_KOI8_R is not set | ||
1821 | # CONFIG_NLS_KOI8_U is not set | ||
1822 | CONFIG_NLS_UTF8=m | ||
1823 | # CONFIG_DLM is not set | ||
1824 | |||
1825 | # | ||
1826 | # Kernel hacking | ||
1827 | # | ||
1828 | # CONFIG_PRINTK_TIME is not set | ||
1829 | CONFIG_ENABLE_WARN_DEPRECATED=y | ||
1830 | CONFIG_ENABLE_MUST_CHECK=y | ||
1831 | CONFIG_FRAME_WARN=1024 | ||
1832 | CONFIG_MAGIC_SYSRQ=y | ||
1833 | # CONFIG_STRIP_ASM_SYMS is not set | ||
1834 | # CONFIG_UNUSED_SYMBOLS is not set | ||
1835 | # CONFIG_DEBUG_FS is not set | ||
1836 | # CONFIG_HEADERS_CHECK is not set | ||
1837 | CONFIG_DEBUG_KERNEL=y | ||
1838 | # CONFIG_DEBUG_SHIRQ is not set | ||
1839 | CONFIG_DETECT_SOFTLOCKUP=y | ||
1840 | # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set | ||
1841 | CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 | ||
1842 | CONFIG_DETECT_HUNG_TASK=y | ||
1843 | # CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set | ||
1844 | CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 | ||
1845 | CONFIG_SCHED_DEBUG=y | ||
1846 | # CONFIG_SCHEDSTATS is not set | ||
1847 | # CONFIG_TIMER_STATS is not set | ||
1848 | # CONFIG_DEBUG_OBJECTS is not set | ||
1849 | # CONFIG_SLUB_DEBUG_ON is not set | ||
1850 | # CONFIG_SLUB_STATS is not set | ||
1851 | # CONFIG_DEBUG_KMEMLEAK is not set | ||
1852 | # CONFIG_DEBUG_RT_MUTEXES is not set | ||
1853 | # CONFIG_RT_MUTEX_TESTER is not set | ||
1854 | # CONFIG_DEBUG_SPINLOCK is not set | ||
1855 | CONFIG_DEBUG_MUTEXES=y | ||
1856 | # CONFIG_DEBUG_LOCK_ALLOC is not set | ||
1857 | # CONFIG_PROVE_LOCKING is not set | ||
1858 | # CONFIG_LOCK_STAT is not set | ||
1859 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set | ||
1860 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set | ||
1861 | # CONFIG_DEBUG_KOBJECT is not set | ||
1862 | CONFIG_DEBUG_BUGVERBOSE=y | ||
1863 | # CONFIG_DEBUG_INFO is not set | ||
1864 | # CONFIG_DEBUG_VM is not set | ||
1865 | # CONFIG_DEBUG_WRITECOUNT is not set | ||
1866 | CONFIG_DEBUG_MEMORY_INIT=y | ||
1867 | # CONFIG_DEBUG_LIST is not set | ||
1868 | # CONFIG_DEBUG_SG is not set | ||
1869 | # CONFIG_DEBUG_NOTIFIERS is not set | ||
1870 | # CONFIG_DEBUG_CREDENTIALS is not set | ||
1871 | # CONFIG_BOOT_PRINTK_DELAY is not set | ||
1872 | # CONFIG_RCU_TORTURE_TEST is not set | ||
1873 | # CONFIG_BACKTRACE_SELF_TEST is not set | ||
1874 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set | ||
1875 | # CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set | ||
1876 | # CONFIG_FAULT_INJECTION is not set | ||
1877 | # CONFIG_LATENCYTOP is not set | ||
1878 | CONFIG_SYSCTL_SYSCALL_CHECK=y | ||
1879 | # CONFIG_PAGE_POISONING is not set | ||
1880 | CONFIG_HAVE_FUNCTION_TRACER=y | ||
1881 | CONFIG_TRACING_SUPPORT=y | ||
1882 | CONFIG_FTRACE=y | ||
1883 | # CONFIG_FUNCTION_TRACER is not set | ||
1884 | # CONFIG_IRQSOFF_TRACER is not set | ||
1885 | # CONFIG_SCHED_TRACER is not set | ||
1886 | # CONFIG_ENABLE_DEFAULT_TRACERS is not set | ||
1887 | # CONFIG_BOOT_TRACER is not set | ||
1888 | CONFIG_BRANCH_PROFILE_NONE=y | ||
1889 | # CONFIG_PROFILE_ANNOTATED_BRANCHES is not set | ||
1890 | # CONFIG_PROFILE_ALL_BRANCHES is not set | ||
1891 | # CONFIG_STACK_TRACER is not set | ||
1892 | # CONFIG_KMEMTRACE is not set | ||
1893 | # CONFIG_WORKQUEUE_TRACER is not set | ||
1894 | # CONFIG_BLK_DEV_IO_TRACE is not set | ||
1895 | # CONFIG_SAMPLES is not set | ||
1896 | CONFIG_HAVE_ARCH_KGDB=y | ||
1897 | # CONFIG_KGDB is not set | ||
1898 | CONFIG_ARM_UNWIND=y | ||
1899 | # CONFIG_DEBUG_USER is not set | ||
1900 | CONFIG_DEBUG_ERRORS=y | ||
1901 | # CONFIG_DEBUG_STACK_USAGE is not set | ||
1902 | # CONFIG_DEBUG_LL is not set | ||
1903 | # CONFIG_OC_ETM is not set | ||
1904 | |||
1905 | # | ||
1906 | # Security options | ||
1907 | # | ||
1908 | # CONFIG_KEYS is not set | ||
1909 | # CONFIG_SECURITY is not set | ||
1910 | # CONFIG_SECURITYFS is not set | ||
1911 | # CONFIG_DEFAULT_SECURITY_SELINUX is not set | ||
1912 | # CONFIG_DEFAULT_SECURITY_SMACK is not set | ||
1913 | # CONFIG_DEFAULT_SECURITY_TOMOYO is not set | ||
1914 | CONFIG_DEFAULT_SECURITY_DAC=y | ||
1915 | CONFIG_DEFAULT_SECURITY="" | ||
1916 | CONFIG_CRYPTO=y | ||
1917 | |||
1918 | # | ||
1919 | # Crypto core or helper | ||
1920 | # | ||
1921 | CONFIG_CRYPTO_ALGAPI=m | ||
1922 | CONFIG_CRYPTO_ALGAPI2=m | ||
1923 | CONFIG_CRYPTO_AEAD2=m | ||
1924 | CONFIG_CRYPTO_BLKCIPHER=m | ||
1925 | CONFIG_CRYPTO_BLKCIPHER2=m | ||
1926 | CONFIG_CRYPTO_HASH=m | ||
1927 | CONFIG_CRYPTO_HASH2=m | ||
1928 | CONFIG_CRYPTO_RNG2=m | ||
1929 | CONFIG_CRYPTO_PCOMP=m | ||
1930 | CONFIG_CRYPTO_MANAGER=m | ||
1931 | CONFIG_CRYPTO_MANAGER2=m | ||
1932 | # CONFIG_CRYPTO_GF128MUL is not set | ||
1933 | # CONFIG_CRYPTO_NULL is not set | ||
1934 | CONFIG_CRYPTO_WORKQUEUE=m | ||
1935 | # CONFIG_CRYPTO_CRYPTD is not set | ||
1936 | # CONFIG_CRYPTO_AUTHENC is not set | ||
1937 | # CONFIG_CRYPTO_TEST is not set | ||
1938 | |||
1939 | # | ||
1940 | # Authenticated Encryption with Associated Data | ||
1941 | # | ||
1942 | # CONFIG_CRYPTO_CCM is not set | ||
1943 | # CONFIG_CRYPTO_GCM is not set | ||
1944 | # CONFIG_CRYPTO_SEQIV is not set | ||
1945 | |||
1946 | # | ||
1947 | # Block modes | ||
1948 | # | ||
1949 | # CONFIG_CRYPTO_CBC is not set | ||
1950 | # CONFIG_CRYPTO_CTR is not set | ||
1951 | # CONFIG_CRYPTO_CTS is not set | ||
1952 | CONFIG_CRYPTO_ECB=m | ||
1953 | # CONFIG_CRYPTO_LRW is not set | ||
1954 | # CONFIG_CRYPTO_PCBC is not set | ||
1955 | # CONFIG_CRYPTO_XTS is not set | ||
1956 | |||
1957 | # | ||
1958 | # Hash modes | ||
1959 | # | ||
1960 | # CONFIG_CRYPTO_HMAC is not set | ||
1961 | # CONFIG_CRYPTO_XCBC is not set | ||
1962 | # CONFIG_CRYPTO_VMAC is not set | ||
1963 | |||
1964 | # | ||
1965 | # Digest | ||
1966 | # | ||
1967 | # CONFIG_CRYPTO_CRC32C is not set | ||
1968 | # CONFIG_CRYPTO_GHASH is not set | ||
1969 | # CONFIG_CRYPTO_MD4 is not set | ||
1970 | # CONFIG_CRYPTO_MD5 is not set | ||
1971 | CONFIG_CRYPTO_MICHAEL_MIC=m | ||
1972 | # CONFIG_CRYPTO_RMD128 is not set | ||
1973 | # CONFIG_CRYPTO_RMD160 is not set | ||
1974 | # CONFIG_CRYPTO_RMD256 is not set | ||
1975 | # CONFIG_CRYPTO_RMD320 is not set | ||
1976 | # CONFIG_CRYPTO_SHA1 is not set | ||
1977 | # CONFIG_CRYPTO_SHA256 is not set | ||
1978 | # CONFIG_CRYPTO_SHA512 is not set | ||
1979 | # CONFIG_CRYPTO_TGR192 is not set | ||
1980 | # CONFIG_CRYPTO_WP512 is not set | ||
1981 | |||
1982 | # | ||
1983 | # Ciphers | ||
1984 | # | ||
1985 | CONFIG_CRYPTO_AES=m | ||
1986 | # CONFIG_CRYPTO_ANUBIS is not set | ||
1987 | CONFIG_CRYPTO_ARC4=m | ||
1988 | # CONFIG_CRYPTO_BLOWFISH is not set | ||
1989 | # CONFIG_CRYPTO_CAMELLIA is not set | ||
1990 | # CONFIG_CRYPTO_CAST5 is not set | ||
1991 | # CONFIG_CRYPTO_CAST6 is not set | ||
1992 | # CONFIG_CRYPTO_DES is not set | ||
1993 | # CONFIG_CRYPTO_FCRYPT is not set | ||
1994 | # CONFIG_CRYPTO_KHAZAD is not set | ||
1995 | # CONFIG_CRYPTO_SALSA20 is not set | ||
1996 | # CONFIG_CRYPTO_SEED is not set | ||
1997 | # CONFIG_CRYPTO_SERPENT is not set | ||
1998 | # CONFIG_CRYPTO_TEA is not set | ||
1999 | # CONFIG_CRYPTO_TWOFISH is not set | ||
2000 | |||
2001 | # | ||
2002 | # Compression | ||
2003 | # | ||
2004 | # CONFIG_CRYPTO_DEFLATE is not set | ||
2005 | # CONFIG_CRYPTO_ZLIB is not set | ||
2006 | # CONFIG_CRYPTO_LZO is not set | ||
2007 | |||
2008 | # | ||
2009 | # Random Number Generation | ||
2010 | # | ||
2011 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | ||
2012 | CONFIG_CRYPTO_HW=y | ||
2013 | # CONFIG_BINARY_PRINTF is not set | ||
2014 | |||
2015 | # | ||
2016 | # Library routines | ||
2017 | # | ||
2018 | CONFIG_BITREVERSE=y | ||
2019 | CONFIG_GENERIC_FIND_LAST_BIT=y | ||
2020 | CONFIG_CRC_CCITT=m | ||
2021 | CONFIG_CRC16=m | ||
2022 | CONFIG_CRC_T10DIF=m | ||
2023 | CONFIG_CRC_ITU_T=m | ||
2024 | CONFIG_CRC32=y | ||
2025 | # CONFIG_CRC7 is not set | ||
2026 | # CONFIG_LIBCRC32C is not set | ||
2027 | CONFIG_ZLIB_INFLATE=y | ||
2028 | CONFIG_ZLIB_DEFLATE=y | ||
2029 | CONFIG_HAS_IOMEM=y | ||
2030 | CONFIG_HAS_IOPORT=y | ||
2031 | CONFIG_HAS_DMA=y | ||
2032 | CONFIG_NLATTR=y | ||
diff --git a/arch/arm/include/asm/elf.h b/arch/arm/include/asm/elf.h index 6aac3f5bb2f3..a399bb5730f1 100644 --- a/arch/arm/include/asm/elf.h +++ b/arch/arm/include/asm/elf.h | |||
@@ -101,7 +101,6 @@ extern int arm_elf_read_implies_exec(const struct elf32_hdr *, int); | |||
101 | int dump_task_regs(struct task_struct *t, elf_gregset_t *elfregs); | 101 | int dump_task_regs(struct task_struct *t, elf_gregset_t *elfregs); |
102 | #define ELF_CORE_COPY_TASK_REGS dump_task_regs | 102 | #define ELF_CORE_COPY_TASK_REGS dump_task_regs |
103 | 103 | ||
104 | #define USE_ELF_CORE_DUMP | ||
105 | #define ELF_EXEC_PAGESIZE 4096 | 104 | #define ELF_EXEC_PAGESIZE 4096 |
106 | 105 | ||
107 | /* This is the location that an ET_DYN program is loaded if exec'ed. Typical | 106 | /* This is the location that an ET_DYN program is loaded if exec'ed. Typical |
diff --git a/arch/arm/include/asm/mach/irq.h b/arch/arm/include/asm/mach/irq.h index acac5302e4ea..8920b2d6e3b8 100644 --- a/arch/arm/include/asm/mach/irq.h +++ b/arch/arm/include/asm/mach/irq.h | |||
@@ -26,9 +26,9 @@ extern int show_fiq_list(struct seq_file *, void *); | |||
26 | */ | 26 | */ |
27 | #define do_bad_IRQ(irq,desc) \ | 27 | #define do_bad_IRQ(irq,desc) \ |
28 | do { \ | 28 | do { \ |
29 | spin_lock(&desc->lock); \ | 29 | raw_spin_lock(&desc->lock); \ |
30 | handle_bad_irq(irq, desc); \ | 30 | handle_bad_irq(irq, desc); \ |
31 | spin_unlock(&desc->lock); \ | 31 | raw_spin_unlock(&desc->lock); \ |
32 | } while(0) | 32 | } while(0) |
33 | 33 | ||
34 | #endif | 34 | #endif |
diff --git a/arch/arm/include/asm/spinlock.h b/arch/arm/include/asm/spinlock.h index c13681ac1ede..c91c64cab922 100644 --- a/arch/arm/include/asm/spinlock.h +++ b/arch/arm/include/asm/spinlock.h | |||
@@ -17,13 +17,13 @@ | |||
17 | * Locked value: 1 | 17 | * Locked value: 1 |
18 | */ | 18 | */ |
19 | 19 | ||
20 | #define __raw_spin_is_locked(x) ((x)->lock != 0) | 20 | #define arch_spin_is_locked(x) ((x)->lock != 0) |
21 | #define __raw_spin_unlock_wait(lock) \ | 21 | #define arch_spin_unlock_wait(lock) \ |
22 | do { while (__raw_spin_is_locked(lock)) cpu_relax(); } while (0) | 22 | do { while (arch_spin_is_locked(lock)) cpu_relax(); } while (0) |
23 | 23 | ||
24 | #define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock) | 24 | #define arch_spin_lock_flags(lock, flags) arch_spin_lock(lock) |
25 | 25 | ||
26 | static inline void __raw_spin_lock(raw_spinlock_t *lock) | 26 | static inline void arch_spin_lock(arch_spinlock_t *lock) |
27 | { | 27 | { |
28 | unsigned long tmp; | 28 | unsigned long tmp; |
29 | 29 | ||
@@ -43,7 +43,7 @@ static inline void __raw_spin_lock(raw_spinlock_t *lock) | |||
43 | smp_mb(); | 43 | smp_mb(); |
44 | } | 44 | } |
45 | 45 | ||
46 | static inline int __raw_spin_trylock(raw_spinlock_t *lock) | 46 | static inline int arch_spin_trylock(arch_spinlock_t *lock) |
47 | { | 47 | { |
48 | unsigned long tmp; | 48 | unsigned long tmp; |
49 | 49 | ||
@@ -63,7 +63,7 @@ static inline int __raw_spin_trylock(raw_spinlock_t *lock) | |||
63 | } | 63 | } |
64 | } | 64 | } |
65 | 65 | ||
66 | static inline void __raw_spin_unlock(raw_spinlock_t *lock) | 66 | static inline void arch_spin_unlock(arch_spinlock_t *lock) |
67 | { | 67 | { |
68 | smp_mb(); | 68 | smp_mb(); |
69 | 69 | ||
@@ -86,7 +86,7 @@ static inline void __raw_spin_unlock(raw_spinlock_t *lock) | |||
86 | * just write zero since the lock is exclusively held. | 86 | * just write zero since the lock is exclusively held. |
87 | */ | 87 | */ |
88 | 88 | ||
89 | static inline void __raw_write_lock(raw_rwlock_t *rw) | 89 | static inline void arch_write_lock(arch_rwlock_t *rw) |
90 | { | 90 | { |
91 | unsigned long tmp; | 91 | unsigned long tmp; |
92 | 92 | ||
@@ -106,7 +106,7 @@ static inline void __raw_write_lock(raw_rwlock_t *rw) | |||
106 | smp_mb(); | 106 | smp_mb(); |
107 | } | 107 | } |
108 | 108 | ||
109 | static inline int __raw_write_trylock(raw_rwlock_t *rw) | 109 | static inline int arch_write_trylock(arch_rwlock_t *rw) |
110 | { | 110 | { |
111 | unsigned long tmp; | 111 | unsigned long tmp; |
112 | 112 | ||
@@ -126,7 +126,7 @@ static inline int __raw_write_trylock(raw_rwlock_t *rw) | |||
126 | } | 126 | } |
127 | } | 127 | } |
128 | 128 | ||
129 | static inline void __raw_write_unlock(raw_rwlock_t *rw) | 129 | static inline void arch_write_unlock(arch_rwlock_t *rw) |
130 | { | 130 | { |
131 | smp_mb(); | 131 | smp_mb(); |
132 | 132 | ||
@@ -142,7 +142,7 @@ static inline void __raw_write_unlock(raw_rwlock_t *rw) | |||
142 | } | 142 | } |
143 | 143 | ||
144 | /* write_can_lock - would write_trylock() succeed? */ | 144 | /* write_can_lock - would write_trylock() succeed? */ |
145 | #define __raw_write_can_lock(x) ((x)->lock == 0) | 145 | #define arch_write_can_lock(x) ((x)->lock == 0) |
146 | 146 | ||
147 | /* | 147 | /* |
148 | * Read locks are a bit more hairy: | 148 | * Read locks are a bit more hairy: |
@@ -156,7 +156,7 @@ static inline void __raw_write_unlock(raw_rwlock_t *rw) | |||
156 | * currently active. However, we know we won't have any write | 156 | * currently active. However, we know we won't have any write |
157 | * locks. | 157 | * locks. |
158 | */ | 158 | */ |
159 | static inline void __raw_read_lock(raw_rwlock_t *rw) | 159 | static inline void arch_read_lock(arch_rwlock_t *rw) |
160 | { | 160 | { |
161 | unsigned long tmp, tmp2; | 161 | unsigned long tmp, tmp2; |
162 | 162 | ||
@@ -176,7 +176,7 @@ static inline void __raw_read_lock(raw_rwlock_t *rw) | |||
176 | smp_mb(); | 176 | smp_mb(); |
177 | } | 177 | } |
178 | 178 | ||
179 | static inline void __raw_read_unlock(raw_rwlock_t *rw) | 179 | static inline void arch_read_unlock(arch_rwlock_t *rw) |
180 | { | 180 | { |
181 | unsigned long tmp, tmp2; | 181 | unsigned long tmp, tmp2; |
182 | 182 | ||
@@ -198,7 +198,7 @@ static inline void __raw_read_unlock(raw_rwlock_t *rw) | |||
198 | : "cc"); | 198 | : "cc"); |
199 | } | 199 | } |
200 | 200 | ||
201 | static inline int __raw_read_trylock(raw_rwlock_t *rw) | 201 | static inline int arch_read_trylock(arch_rwlock_t *rw) |
202 | { | 202 | { |
203 | unsigned long tmp, tmp2 = 1; | 203 | unsigned long tmp, tmp2 = 1; |
204 | 204 | ||
@@ -215,13 +215,13 @@ static inline int __raw_read_trylock(raw_rwlock_t *rw) | |||
215 | } | 215 | } |
216 | 216 | ||
217 | /* read_can_lock - would read_trylock() succeed? */ | 217 | /* read_can_lock - would read_trylock() succeed? */ |
218 | #define __raw_read_can_lock(x) ((x)->lock < 0x80000000) | 218 | #define arch_read_can_lock(x) ((x)->lock < 0x80000000) |
219 | 219 | ||
220 | #define __raw_read_lock_flags(lock, flags) __raw_read_lock(lock) | 220 | #define arch_read_lock_flags(lock, flags) arch_read_lock(lock) |
221 | #define __raw_write_lock_flags(lock, flags) __raw_write_lock(lock) | 221 | #define arch_write_lock_flags(lock, flags) arch_write_lock(lock) |
222 | 222 | ||
223 | #define _raw_spin_relax(lock) cpu_relax() | 223 | #define arch_spin_relax(lock) cpu_relax() |
224 | #define _raw_read_relax(lock) cpu_relax() | 224 | #define arch_read_relax(lock) cpu_relax() |
225 | #define _raw_write_relax(lock) cpu_relax() | 225 | #define arch_write_relax(lock) cpu_relax() |
226 | 226 | ||
227 | #endif /* __ASM_SPINLOCK_H */ | 227 | #endif /* __ASM_SPINLOCK_H */ |
diff --git a/arch/arm/include/asm/spinlock_types.h b/arch/arm/include/asm/spinlock_types.h index 43e83f6d2ee5..d14d197ae04a 100644 --- a/arch/arm/include/asm/spinlock_types.h +++ b/arch/arm/include/asm/spinlock_types.h | |||
@@ -7,14 +7,14 @@ | |||
7 | 7 | ||
8 | typedef struct { | 8 | typedef struct { |
9 | volatile unsigned int lock; | 9 | volatile unsigned int lock; |
10 | } raw_spinlock_t; | 10 | } arch_spinlock_t; |
11 | 11 | ||
12 | #define __RAW_SPIN_LOCK_UNLOCKED { 0 } | 12 | #define __ARCH_SPIN_LOCK_UNLOCKED { 0 } |
13 | 13 | ||
14 | typedef struct { | 14 | typedef struct { |
15 | volatile unsigned int lock; | 15 | volatile unsigned int lock; |
16 | } raw_rwlock_t; | 16 | } arch_rwlock_t; |
17 | 17 | ||
18 | #define __RAW_RW_LOCK_UNLOCKED { 0 } | 18 | #define __ARCH_RW_LOCK_UNLOCKED { 0 } |
19 | 19 | ||
20 | #endif | 20 | #endif |
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile index e7ccf7e697ce..dd00f747e2ad 100644 --- a/arch/arm/kernel/Makefile +++ b/arch/arm/kernel/Makefile | |||
@@ -54,5 +54,6 @@ endif | |||
54 | 54 | ||
55 | head-y := head$(MMUEXT).o | 55 | head-y := head$(MMUEXT).o |
56 | obj-$(CONFIG_DEBUG_LL) += debug.o | 56 | obj-$(CONFIG_DEBUG_LL) += debug.o |
57 | obj-$(CONFIG_EARLY_PRINTK) += early_printk.o | ||
57 | 58 | ||
58 | extra-y := $(head-y) init_task.o vmlinux.lds | 59 | extra-y := $(head-y) init_task.o vmlinux.lds |
diff --git a/arch/arm/kernel/armksyms.c b/arch/arm/kernel/armksyms.c index 0e627705f746..8214bfebfaca 100644 --- a/arch/arm/kernel/armksyms.c +++ b/arch/arm/kernel/armksyms.c | |||
@@ -48,27 +48,7 @@ extern void __aeabi_uidivmod(void); | |||
48 | extern void __aeabi_ulcmp(void); | 48 | extern void __aeabi_ulcmp(void); |
49 | 49 | ||
50 | extern void fpundefinstr(void); | 50 | extern void fpundefinstr(void); |
51 | extern void fp_enter(void); | ||
52 | 51 | ||
53 | /* | ||
54 | * This has a special calling convention; it doesn't | ||
55 | * modify any of the usual registers, except for LR. | ||
56 | */ | ||
57 | #define EXPORT_CRC_ALIAS(sym) __CRC_SYMBOL(sym, "") | ||
58 | |||
59 | #define EXPORT_SYMBOL_ALIAS(sym,orig) \ | ||
60 | EXPORT_CRC_ALIAS(sym) \ | ||
61 | static const struct kernel_symbol __ksymtab_##sym \ | ||
62 | __used __attribute__((section("__ksymtab"))) = \ | ||
63 | { (unsigned long)&orig, #sym }; | ||
64 | |||
65 | /* | ||
66 | * floating point math emulator support. | ||
67 | * These symbols will never change their calling convention... | ||
68 | */ | ||
69 | EXPORT_SYMBOL_ALIAS(kern_fp_enter,fp_enter); | ||
70 | EXPORT_SYMBOL_ALIAS(fp_printk,printk); | ||
71 | EXPORT_SYMBOL_ALIAS(fp_send_sig,send_sig); | ||
72 | 52 | ||
73 | EXPORT_SYMBOL(__backtrace); | 53 | EXPORT_SYMBOL(__backtrace); |
74 | 54 | ||
diff --git a/arch/arm/kernel/early_printk.c b/arch/arm/kernel/early_printk.c new file mode 100644 index 000000000000..85aa2b292692 --- /dev/null +++ b/arch/arm/kernel/early_printk.c | |||
@@ -0,0 +1,57 @@ | |||
1 | /* | ||
2 | * linux/arch/arm/kernel/early_printk.c | ||
3 | * | ||
4 | * Copyright (C) 2009 Sascha Hauer <s.hauer@pengutronix.de> | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | |||
11 | #include <linux/kernel.h> | ||
12 | #include <linux/console.h> | ||
13 | #include <linux/init.h> | ||
14 | |||
15 | extern void printch(int); | ||
16 | |||
17 | static void early_write(const char *s, unsigned n) | ||
18 | { | ||
19 | while (n-- > 0) { | ||
20 | if (*s == '\n') | ||
21 | printch('\r'); | ||
22 | printch(*s); | ||
23 | s++; | ||
24 | } | ||
25 | } | ||
26 | |||
27 | static void early_console_write(struct console *con, const char *s, unsigned n) | ||
28 | { | ||
29 | early_write(s, n); | ||
30 | } | ||
31 | |||
32 | static struct console early_console = { | ||
33 | .name = "earlycon", | ||
34 | .write = early_console_write, | ||
35 | .flags = CON_PRINTBUFFER | CON_BOOT, | ||
36 | .index = -1, | ||
37 | }; | ||
38 | |||
39 | asmlinkage void early_printk(const char *fmt, ...) | ||
40 | { | ||
41 | char buf[512]; | ||
42 | int n; | ||
43 | va_list ap; | ||
44 | |||
45 | va_start(ap, fmt); | ||
46 | n = vscnprintf(buf, sizeof(buf), fmt, ap); | ||
47 | early_write(buf, n); | ||
48 | va_end(ap); | ||
49 | } | ||
50 | |||
51 | static int __init setup_early_printk(char *buf) | ||
52 | { | ||
53 | register_console(&early_console); | ||
54 | return 0; | ||
55 | } | ||
56 | |||
57 | early_param("earlyprintk", setup_early_printk); | ||
diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c index c9a8619f3856..b7cb45bb91e8 100644 --- a/arch/arm/kernel/irq.c +++ b/arch/arm/kernel/irq.c | |||
@@ -69,7 +69,7 @@ int show_interrupts(struct seq_file *p, void *v) | |||
69 | } | 69 | } |
70 | 70 | ||
71 | if (i < NR_IRQS) { | 71 | if (i < NR_IRQS) { |
72 | spin_lock_irqsave(&irq_desc[i].lock, flags); | 72 | raw_spin_lock_irqsave(&irq_desc[i].lock, flags); |
73 | action = irq_desc[i].action; | 73 | action = irq_desc[i].action; |
74 | if (!action) | 74 | if (!action) |
75 | goto unlock; | 75 | goto unlock; |
@@ -84,7 +84,7 @@ int show_interrupts(struct seq_file *p, void *v) | |||
84 | 84 | ||
85 | seq_putc(p, '\n'); | 85 | seq_putc(p, '\n'); |
86 | unlock: | 86 | unlock: |
87 | spin_unlock_irqrestore(&irq_desc[i].lock, flags); | 87 | raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags); |
88 | } else if (i == NR_IRQS) { | 88 | } else if (i == NR_IRQS) { |
89 | #ifdef CONFIG_FIQ | 89 | #ifdef CONFIG_FIQ |
90 | show_fiq_list(p, v); | 90 | show_fiq_list(p, v); |
@@ -139,7 +139,7 @@ void set_irq_flags(unsigned int irq, unsigned int iflags) | |||
139 | } | 139 | } |
140 | 140 | ||
141 | desc = irq_desc + irq; | 141 | desc = irq_desc + irq; |
142 | spin_lock_irqsave(&desc->lock, flags); | 142 | raw_spin_lock_irqsave(&desc->lock, flags); |
143 | desc->status |= IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; | 143 | desc->status |= IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; |
144 | if (iflags & IRQF_VALID) | 144 | if (iflags & IRQF_VALID) |
145 | desc->status &= ~IRQ_NOREQUEST; | 145 | desc->status &= ~IRQ_NOREQUEST; |
@@ -147,7 +147,7 @@ void set_irq_flags(unsigned int irq, unsigned int iflags) | |||
147 | desc->status &= ~IRQ_NOPROBE; | 147 | desc->status &= ~IRQ_NOPROBE; |
148 | if (!(iflags & IRQF_NOAUTOEN)) | 148 | if (!(iflags & IRQF_NOAUTOEN)) |
149 | desc->status &= ~IRQ_NOAUTOEN; | 149 | desc->status &= ~IRQ_NOAUTOEN; |
150 | spin_unlock_irqrestore(&desc->lock, flags); | 150 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
151 | } | 151 | } |
152 | 152 | ||
153 | void __init init_IRQ(void) | 153 | void __init init_IRQ(void) |
@@ -166,9 +166,9 @@ static void route_irq(struct irq_desc *desc, unsigned int irq, unsigned int cpu) | |||
166 | { | 166 | { |
167 | pr_debug("IRQ%u: moving from cpu%u to cpu%u\n", irq, desc->node, cpu); | 167 | pr_debug("IRQ%u: moving from cpu%u to cpu%u\n", irq, desc->node, cpu); |
168 | 168 | ||
169 | spin_lock_irq(&desc->lock); | 169 | raw_spin_lock_irq(&desc->lock); |
170 | desc->chip->set_affinity(irq, cpumask_of(cpu)); | 170 | desc->chip->set_affinity(irq, cpumask_of(cpu)); |
171 | spin_unlock_irq(&desc->lock); | 171 | raw_spin_unlock_irq(&desc->lock); |
172 | } | 172 | } |
173 | 173 | ||
174 | /* | 174 | /* |
diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c index a73a34dccf2a..ea02a7b1c244 100644 --- a/arch/arm/kernel/smp_twd.c +++ b/arch/arm/kernel/smp_twd.c | |||
@@ -160,6 +160,7 @@ void __cpuinit twd_timer_setup(struct clock_event_device *clk) | |||
160 | 160 | ||
161 | /* Make sure our local interrupt controller has this enabled */ | 161 | /* Make sure our local interrupt controller has this enabled */ |
162 | local_irq_save(flags); | 162 | local_irq_save(flags); |
163 | irq_to_desc(clk->irq)->status |= IRQ_NOPROBE; | ||
163 | get_irq_chip(clk->irq)->unmask(clk->irq); | 164 | get_irq_chip(clk->irq)->unmask(clk->irq); |
164 | local_irq_restore(flags); | 165 | local_irq_restore(flags); |
165 | 166 | ||
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S index 71151bd87a36..4957e13ef55b 100644 --- a/arch/arm/kernel/vmlinux.lds.S +++ b/arch/arm/kernel/vmlinux.lds.S | |||
@@ -65,11 +65,11 @@ SECTIONS | |||
65 | __init_end = .; | 65 | __init_end = .; |
66 | #endif | 66 | #endif |
67 | 67 | ||
68 | /DISCARD/ : { /* Exit code and data */ | 68 | /* |
69 | EXIT_TEXT | 69 | * unwind exit sections must be discarded before the rest of the |
70 | EXIT_DATA | 70 | * unwind sections get included. |
71 | *(.exitcall.exit) | 71 | */ |
72 | *(.discard) | 72 | /DISCARD/ : { |
73 | *(.ARM.exidx.exit.text) | 73 | *(.ARM.exidx.exit.text) |
74 | *(.ARM.extab.exit.text) | 74 | *(.ARM.extab.exit.text) |
75 | #ifndef CONFIG_HOTPLUG_CPU | 75 | #ifndef CONFIG_HOTPLUG_CPU |
@@ -238,6 +238,9 @@ SECTIONS | |||
238 | 238 | ||
239 | STABS_DEBUG | 239 | STABS_DEBUG |
240 | .comment 0 : { *(.comment) } | 240 | .comment 0 : { *(.comment) } |
241 | |||
242 | /* Default discards */ | ||
243 | DISCARDS | ||
241 | } | 244 | } |
242 | 245 | ||
243 | /* | 246 | /* |
diff --git a/arch/arm/mach-at91/include/mach/atmel-mci.h b/arch/arm/mach-at91/include/mach/atmel-mci.h new file mode 100644 index 000000000000..998cb0c07135 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/atmel-mci.h | |||
@@ -0,0 +1,24 @@ | |||
1 | #ifndef __MACH_ATMEL_MCI_H | ||
2 | #define __MACH_ATMEL_MCI_H | ||
3 | |||
4 | #include <mach/at_hdmac.h> | ||
5 | |||
6 | /** | ||
7 | * struct mci_dma_data - DMA data for MCI interface | ||
8 | */ | ||
9 | struct mci_dma_data { | ||
10 | struct at_dma_slave sdata; | ||
11 | }; | ||
12 | |||
13 | /* accessor macros */ | ||
14 | #define slave_data_ptr(s) (&(s)->sdata) | ||
15 | #define find_slave_dev(s) ((s)->sdata.dma_dev) | ||
16 | |||
17 | #define setup_dma_addr(s, t, r) do { \ | ||
18 | if (s) { \ | ||
19 | (s)->sdata.tx_reg = (t); \ | ||
20 | (s)->sdata.rx_reg = (r); \ | ||
21 | } \ | ||
22 | } while (0) | ||
23 | |||
24 | #endif /* __MACH_ATMEL_MCI_H */ | ||
diff --git a/arch/arm/mach-bcmring/arch.c b/arch/arm/mach-bcmring/arch.c index fbe6fa02c882..53dd2a9eecf9 100644 --- a/arch/arm/mach-bcmring/arch.c +++ b/arch/arm/mach-bcmring/arch.c | |||
@@ -70,9 +70,19 @@ static struct ctl_table bcmring_sysctl_reboot[] = { | |||
70 | {} | 70 | {} |
71 | }; | 71 | }; |
72 | 72 | ||
73 | static struct resource nand_resource[] = { | ||
74 | [0] = { | ||
75 | .start = MM_ADDR_IO_NAND, | ||
76 | .end = MM_ADDR_IO_NAND + 0x1000 - 1, | ||
77 | .flags = IORESOURCE_MEM, | ||
78 | }, | ||
79 | }; | ||
80 | |||
73 | static struct platform_device nand_device = { | 81 | static struct platform_device nand_device = { |
74 | .name = "bcm-nand", | 82 | .name = "bcm-nand", |
75 | .id = -1, | 83 | .id = -1, |
84 | .resource = nand_resource, | ||
85 | .num_resources = ARRAY_SIZE(nand_resource), | ||
76 | }; | 86 | }; |
77 | 87 | ||
78 | static struct platform_device *devices[] __initdata = { | 88 | static struct platform_device *devices[] __initdata = { |
diff --git a/arch/arm/mach-bcmring/include/mach/reg_nand.h b/arch/arm/mach-bcmring/include/mach/reg_nand.h new file mode 100644 index 000000000000..387376ffb56b --- /dev/null +++ b/arch/arm/mach-bcmring/include/mach/reg_nand.h | |||
@@ -0,0 +1,66 @@ | |||
1 | /***************************************************************************** | ||
2 | * Copyright 2001 - 2008 Broadcom Corporation. All rights reserved. | ||
3 | * | ||
4 | * Unless you and Broadcom execute a separate written software license | ||
5 | * agreement governing use of this software, this software is licensed to you | ||
6 | * under the terms of the GNU General Public License version 2, available at | ||
7 | * http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). | ||
8 | * | ||
9 | * Notwithstanding the above, under no circumstances may you combine this | ||
10 | * software in any way with any other Broadcom software provided under a | ||
11 | * license other than the GPL, without Broadcom's express prior written | ||
12 | * consent. | ||
13 | *****************************************************************************/ | ||
14 | |||
15 | /* | ||
16 | * | ||
17 | ***************************************************************************** | ||
18 | * | ||
19 | * REG_NAND.h | ||
20 | * | ||
21 | * PURPOSE: | ||
22 | * | ||
23 | * This file contains definitions for the nand registers: | ||
24 | * | ||
25 | * NOTES: | ||
26 | * | ||
27 | *****************************************************************************/ | ||
28 | |||
29 | #if !defined(__ASM_ARCH_REG_NAND_H) | ||
30 | #define __ASM_ARCH_REG_NAND_H | ||
31 | |||
32 | /* ---- Include Files ---------------------------------------------------- */ | ||
33 | #include <csp/reg.h> | ||
34 | #include <mach/reg_umi.h> | ||
35 | |||
36 | /* ---- Constants and Types ---------------------------------------------- */ | ||
37 | |||
38 | #define HW_NAND_BASE MM_IO_BASE_NAND /* NAND Flash */ | ||
39 | |||
40 | /* DMA accesses by the bootstrap need hard nonvirtual addresses */ | ||
41 | #define REG_NAND_CMD __REG16(HW_NAND_BASE + 0) | ||
42 | #define REG_NAND_ADDR __REG16(HW_NAND_BASE + 4) | ||
43 | |||
44 | #define REG_NAND_PHYS_DATA16 (HW_NAND_BASE + 8) | ||
45 | #define REG_NAND_PHYS_DATA8 (HW_NAND_BASE + 8) | ||
46 | #define REG_NAND_DATA16 __REG16(REG_NAND_PHYS_DATA16) | ||
47 | #define REG_NAND_DATA8 __REG8(REG_NAND_PHYS_DATA8) | ||
48 | |||
49 | /* use appropriate offset to make sure it start at the 1K boundary */ | ||
50 | #define REG_NAND_PHYS_DATA_DMA (HW_NAND_BASE + 0x400) | ||
51 | #define REG_NAND_DATA_DMA __REG32(REG_NAND_PHYS_DATA_DMA) | ||
52 | |||
53 | /* Linux DMA requires physical address of the data register */ | ||
54 | #define REG_NAND_DATA16_PADDR HW_IO_VIRT_TO_PHYS(REG_NAND_PHYS_DATA16) | ||
55 | #define REG_NAND_DATA8_PADDR HW_IO_VIRT_TO_PHYS(REG_NAND_PHYS_DATA8) | ||
56 | #define REG_NAND_DATA_PADDR HW_IO_VIRT_TO_PHYS(REG_NAND_PHYS_DATA_DMA) | ||
57 | |||
58 | #define NAND_BUS_16BIT() (0) | ||
59 | #define NAND_BUS_8BIT() (!NAND_BUS_16BIT()) | ||
60 | |||
61 | /* Register offsets */ | ||
62 | #define REG_NAND_CMD_OFFSET (0) | ||
63 | #define REG_NAND_ADDR_OFFSET (4) | ||
64 | #define REG_NAND_DATA8_OFFSET (8) | ||
65 | |||
66 | #endif | ||
diff --git a/arch/arm/mach-bcmring/include/mach/reg_umi.h b/arch/arm/mach-bcmring/include/mach/reg_umi.h new file mode 100644 index 000000000000..06a355481ea6 --- /dev/null +++ b/arch/arm/mach-bcmring/include/mach/reg_umi.h | |||
@@ -0,0 +1,237 @@ | |||
1 | /***************************************************************************** | ||
2 | * Copyright 2005 - 2008 Broadcom Corporation. All rights reserved. | ||
3 | * | ||
4 | * Unless you and Broadcom execute a separate written software license | ||
5 | * agreement governing use of this software, this software is licensed to you | ||
6 | * under the terms of the GNU General Public License version 2, available at | ||
7 | * http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). | ||
8 | * | ||
9 | * Notwithstanding the above, under no circumstances may you combine this | ||
10 | * software in any way with any other Broadcom software provided under a | ||
11 | * license other than the GPL, without Broadcom's express prior written | ||
12 | * consent. | ||
13 | *****************************************************************************/ | ||
14 | |||
15 | /* | ||
16 | * | ||
17 | ***************************************************************************** | ||
18 | * | ||
19 | * REG_UMI.h | ||
20 | * | ||
21 | * PURPOSE: | ||
22 | * | ||
23 | * This file contains definitions for the nand registers: | ||
24 | * | ||
25 | * NOTES: | ||
26 | * | ||
27 | *****************************************************************************/ | ||
28 | |||
29 | #if !defined(__ASM_ARCH_REG_UMI_H) | ||
30 | #define __ASM_ARCH_REG_UMI_H | ||
31 | |||
32 | /* ---- Include Files ---------------------------------------------------- */ | ||
33 | #include <csp/reg.h> | ||
34 | #include <mach/csp/mm_io.h> | ||
35 | |||
36 | /* ---- Constants and Types ---------------------------------------------- */ | ||
37 | |||
38 | /* Unified Memory Interface Ctrl Register */ | ||
39 | #define HW_UMI_BASE MM_IO_BASE_UMI | ||
40 | |||
41 | /* Flash bank 0 timing and control register */ | ||
42 | #define REG_UMI_FLASH0_TCR __REG32(HW_UMI_BASE + 0x00) | ||
43 | /* Flash bank 1 timing and control register */ | ||
44 | #define REG_UMI_FLASH1_TCR __REG32(HW_UMI_BASE + 0x04) | ||
45 | /* Flash bank 2 timing and control register */ | ||
46 | #define REG_UMI_FLASH2_TCR __REG32(HW_UMI_BASE + 0x08) | ||
47 | /* MMD interface and control register */ | ||
48 | #define REG_UMI_MMD_ICR __REG32(HW_UMI_BASE + 0x0c) | ||
49 | /* NAND timing and control register */ | ||
50 | #define REG_UMI_NAND_TCR __REG32(HW_UMI_BASE + 0x18) | ||
51 | /* NAND ready/chip select register */ | ||
52 | #define REG_UMI_NAND_RCSR __REG32(HW_UMI_BASE + 0x1c) | ||
53 | /* NAND ECC control & status register */ | ||
54 | #define REG_UMI_NAND_ECC_CSR __REG32(HW_UMI_BASE + 0x20) | ||
55 | /* NAND ECC data register XXB2B1B0 */ | ||
56 | #define REG_UMI_NAND_ECC_DATA __REG32(HW_UMI_BASE + 0x24) | ||
57 | /* BCH ECC Parameter N */ | ||
58 | #define REG_UMI_BCH_N __REG32(HW_UMI_BASE + 0x40) | ||
59 | /* BCH ECC Parameter T */ | ||
60 | #define REG_UMI_BCH_K __REG32(HW_UMI_BASE + 0x44) | ||
61 | /* BCH ECC Parameter K */ | ||
62 | #define REG_UMI_BCH_T __REG32(HW_UMI_BASE + 0x48) | ||
63 | /* BCH ECC Contro Status */ | ||
64 | #define REG_UMI_BCH_CTRL_STATUS __REG32(HW_UMI_BASE + 0x4C) | ||
65 | /* BCH WR ECC 31:0 */ | ||
66 | #define REG_UMI_BCH_WR_ECC_0 __REG32(HW_UMI_BASE + 0x50) | ||
67 | /* BCH WR ECC 63:32 */ | ||
68 | #define REG_UMI_BCH_WR_ECC_1 __REG32(HW_UMI_BASE + 0x54) | ||
69 | /* BCH WR ECC 95:64 */ | ||
70 | #define REG_UMI_BCH_WR_ECC_2 __REG32(HW_UMI_BASE + 0x58) | ||
71 | /* BCH WR ECC 127:96 */ | ||
72 | #define REG_UMI_BCH_WR_ECC_3 __REG32(HW_UMI_BASE + 0x5c) | ||
73 | /* BCH WR ECC 155:128 */ | ||
74 | #define REG_UMI_BCH_WR_ECC_4 __REG32(HW_UMI_BASE + 0x60) | ||
75 | /* BCH Read Error Location 1,0 */ | ||
76 | #define REG_UMI_BCH_RD_ERR_LOC_1_0 __REG32(HW_UMI_BASE + 0x64) | ||
77 | /* BCH Read Error Location 3,2 */ | ||
78 | #define REG_UMI_BCH_RD_ERR_LOC_3_2 __REG32(HW_UMI_BASE + 0x68) | ||
79 | /* BCH Read Error Location 5,4 */ | ||
80 | #define REG_UMI_BCH_RD_ERR_LOC_5_4 __REG32(HW_UMI_BASE + 0x6c) | ||
81 | /* BCH Read Error Location 7,6 */ | ||
82 | #define REG_UMI_BCH_RD_ERR_LOC_7_6 __REG32(HW_UMI_BASE + 0x70) | ||
83 | /* BCH Read Error Location 9,8 */ | ||
84 | #define REG_UMI_BCH_RD_ERR_LOC_9_8 __REG32(HW_UMI_BASE + 0x74) | ||
85 | /* BCH Read Error Location 11,10 */ | ||
86 | #define REG_UMI_BCH_RD_ERR_LOC_B_A __REG32(HW_UMI_BASE + 0x78) | ||
87 | |||
88 | /* REG_UMI_FLASH0/1/2_TCR, REG_UMI_SRAM0/1_TCR bits */ | ||
89 | /* Enable wait pin during burst write or read */ | ||
90 | #define REG_UMI_TCR_WAITEN 0x80000000 | ||
91 | /* Enable mem ctrlr to work iwth ext mem of lower freq than AHB clk */ | ||
92 | #define REG_UMI_TCR_LOWFREQ 0x40000000 | ||
93 | /* 1=synch write, 0=async write */ | ||
94 | #define REG_UMI_TCR_MEMTYPE_SYNCWRITE 0x20000000 | ||
95 | /* 1=synch read, 0=async read */ | ||
96 | #define REG_UMI_TCR_MEMTYPE_SYNCREAD 0x10000000 | ||
97 | /* 1=page mode read, 0=normal mode read */ | ||
98 | #define REG_UMI_TCR_MEMTYPE_PAGEREAD 0x08000000 | ||
99 | /* page size/burst size (wrap only) */ | ||
100 | #define REG_UMI_TCR_MEMTYPE_PGSZ_MASK 0x07000000 | ||
101 | /* 4 word */ | ||
102 | #define REG_UMI_TCR_MEMTYPE_PGSZ_4 0x00000000 | ||
103 | /* 8 word */ | ||
104 | #define REG_UMI_TCR_MEMTYPE_PGSZ_8 0x01000000 | ||
105 | /* 16 word */ | ||
106 | #define REG_UMI_TCR_MEMTYPE_PGSZ_16 0x02000000 | ||
107 | /* 32 word */ | ||
108 | #define REG_UMI_TCR_MEMTYPE_PGSZ_32 0x03000000 | ||
109 | /* 64 word */ | ||
110 | #define REG_UMI_TCR_MEMTYPE_PGSZ_64 0x04000000 | ||
111 | /* 128 word */ | ||
112 | #define REG_UMI_TCR_MEMTYPE_PGSZ_128 0x05000000 | ||
113 | /* 256 word */ | ||
114 | #define REG_UMI_TCR_MEMTYPE_PGSZ_256 0x06000000 | ||
115 | /* 512 word */ | ||
116 | #define REG_UMI_TCR_MEMTYPE_PGSZ_512 0x07000000 | ||
117 | /* Page read access cycle / Burst write latency (n+2 / n+1) */ | ||
118 | #define REG_UMI_TCR_TPRC_TWLC_MASK 0x00f80000 | ||
119 | /* Bus turnaround cycle (n) */ | ||
120 | #define REG_UMI_TCR_TBTA_MASK 0x00070000 | ||
121 | /* Write pulse width cycle (n+1) */ | ||
122 | #define REG_UMI_TCR_TWP_MASK 0x0000f800 | ||
123 | /* Write recovery cycle (n+1) */ | ||
124 | #define REG_UMI_TCR_TWR_MASK 0x00000600 | ||
125 | /* Write address setup cycle (n+1) */ | ||
126 | #define REG_UMI_TCR_TAS_MASK 0x00000180 | ||
127 | /* Output enable delay cycle (n) */ | ||
128 | #define REG_UMI_TCR_TOE_MASK 0x00000060 | ||
129 | /* Read access cycle / Burst read latency (n+2 / n+1) */ | ||
130 | #define REG_UMI_TCR_TRC_TLC_MASK 0x0000001f | ||
131 | |||
132 | /* REG_UMI_MMD_ICR bits */ | ||
133 | /* Flash write protection pin control */ | ||
134 | #define REG_UMI_MMD_ICR_FLASH_WP 0x8000 | ||
135 | /* Extend hold time for sram0, sram1 csn (39 MHz operation) */ | ||
136 | #define REG_UMI_MMD_ICR_XHCS 0x4000 | ||
137 | /* Enable SDRAM 2 interface control */ | ||
138 | #define REG_UMI_MMD_ICR_SDRAM2EN 0x2000 | ||
139 | /* Enable merge of flash banks 0/1 to 512 MBit bank */ | ||
140 | #define REG_UMI_MMD_ICR_INST512 0x1000 | ||
141 | /* Enable merge of flash banks 1/2 to 512 MBit bank */ | ||
142 | #define REG_UMI_MMD_ICR_DATA512 0x0800 | ||
143 | /* Enable SDRAM interface control */ | ||
144 | #define REG_UMI_MMD_ICR_SDRAMEN 0x0400 | ||
145 | /* Polarity of busy state of Burst Wait Signal */ | ||
146 | #define REG_UMI_MMD_ICR_WAITPOL 0x0200 | ||
147 | /* Enable burst clock stopped when not accessing external burst flash/sram */ | ||
148 | #define REG_UMI_MMD_ICR_BCLKSTOP 0x0100 | ||
149 | /* Enable the peri1_csn to replace flash1_csn in 512 Mb flash mode */ | ||
150 | #define REG_UMI_MMD_ICR_PERI1EN 0x0080 | ||
151 | /* Enable the peri2_csn to replace sdram_csn */ | ||
152 | #define REG_UMI_MMD_ICR_PERI2EN 0x0040 | ||
153 | /* Enable the peri3_csn to replace sdram2_csn */ | ||
154 | #define REG_UMI_MMD_ICR_PERI3EN 0x0020 | ||
155 | /* Enable sram bank1 for H/W controlled MRS */ | ||
156 | #define REG_UMI_MMD_ICR_MRSB1 0x0010 | ||
157 | /* Enable sram bank0 for H/W controlled MRS */ | ||
158 | #define REG_UMI_MMD_ICR_MRSB0 0x0008 | ||
159 | /* Polarity for assert3ed state of H/W controlled MRS */ | ||
160 | #define REG_UMI_MMD_ICR_MRSPOL 0x0004 | ||
161 | /* 0: S/W controllable ZZ/MRS/CRE/P-Mode pin */ | ||
162 | /* 1: H/W controlled ZZ/MRS/CRE/P-Mode, same timing as CS */ | ||
163 | #define REG_UMI_MMD_ICR_MRSMODE 0x0002 | ||
164 | /* MRS state for S/W controlled mode */ | ||
165 | #define REG_UMI_MMD_ICR_MRSSTATE 0x0001 | ||
166 | |||
167 | /* REG_UMI_NAND_TCR bits */ | ||
168 | /* Enable software to control CS */ | ||
169 | #define REG_UMI_NAND_TCR_CS_SWCTRL 0x80000000 | ||
170 | /* 16-bit nand wordsize if set */ | ||
171 | #define REG_UMI_NAND_TCR_WORD16 0x40000000 | ||
172 | /* Bus turnaround cycle (n) */ | ||
173 | #define REG_UMI_NAND_TCR_TBTA_MASK 0x00070000 | ||
174 | /* Write pulse width cycle (n+1) */ | ||
175 | #define REG_UMI_NAND_TCR_TWP_MASK 0x0000f800 | ||
176 | /* Write recovery cycle (n+1) */ | ||
177 | #define REG_UMI_NAND_TCR_TWR_MASK 0x00000600 | ||
178 | /* Write address setup cycle (n+1) */ | ||
179 | #define REG_UMI_NAND_TCR_TAS_MASK 0x00000180 | ||
180 | /* Output enable delay cycle (n) */ | ||
181 | #define REG_UMI_NAND_TCR_TOE_MASK 0x00000060 | ||
182 | /* Read access cycle (n+2) */ | ||
183 | #define REG_UMI_NAND_TCR_TRC_TLC_MASK 0x0000001f | ||
184 | |||
185 | /* REG_UMI_NAND_RCSR bits */ | ||
186 | /* Status: Ready=1, Busy=0 */ | ||
187 | #define REG_UMI_NAND_RCSR_RDY 0x02 | ||
188 | /* Keep CS asserted during operation */ | ||
189 | #define REG_UMI_NAND_RCSR_CS_ASSERTED 0x01 | ||
190 | |||
191 | /* REG_UMI_NAND_ECC_CSR bits */ | ||
192 | /* Interrupt status - read-only */ | ||
193 | #define REG_UMI_NAND_ECC_CSR_NANDINT 0x80000000 | ||
194 | /* Read: Status of ECC done, Write: clear ECC interrupt */ | ||
195 | #define REG_UMI_NAND_ECC_CSR_ECCINT_RAW 0x00800000 | ||
196 | /* Read: Status of R/B, Write: clear R/B interrupt */ | ||
197 | #define REG_UMI_NAND_ECC_CSR_RBINT_RAW 0x00400000 | ||
198 | /* 1 = Enable ECC Interrupt */ | ||
199 | #define REG_UMI_NAND_ECC_CSR_ECCINT_ENABLE 0x00008000 | ||
200 | /* 1 = Assert interrupt at rising edge of R/B_ */ | ||
201 | #define REG_UMI_NAND_ECC_CSR_RBINT_ENABLE 0x00004000 | ||
202 | /* Calculate ECC by 0=512 bytes, 1=256 bytes */ | ||
203 | #define REG_UMI_NAND_ECC_CSR_256BYTE 0x00000080 | ||
204 | /* Enable ECC in hardware */ | ||
205 | #define REG_UMI_NAND_ECC_CSR_ECC_ENABLE 0x00000001 | ||
206 | |||
207 | /* REG_UMI_BCH_CTRL_STATUS bits */ | ||
208 | /* Shift to Indicate Number of correctable errors detected */ | ||
209 | #define REG_UMI_BCH_CTRL_STATUS_NB_CORR_ERROR_SHIFT 20 | ||
210 | /* Indicate Number of correctable errors detected */ | ||
211 | #define REG_UMI_BCH_CTRL_STATUS_NB_CORR_ERROR 0x00F00000 | ||
212 | /* Indicate Errors detected during read but uncorrectable */ | ||
213 | #define REG_UMI_BCH_CTRL_STATUS_UNCORR_ERR 0x00080000 | ||
214 | /* Indicate Errors detected during read and are correctable */ | ||
215 | #define REG_UMI_BCH_CTRL_STATUS_CORR_ERR 0x00040000 | ||
216 | /* Flag indicates BCH's ECC status of read process are valid */ | ||
217 | #define REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID 0x00020000 | ||
218 | /* Flag indicates BCH's ECC status of write process are valid */ | ||
219 | #define REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID 0x00010000 | ||
220 | /* Pause ECC calculation */ | ||
221 | #define REG_UMI_BCH_CTRL_STATUS_PAUSE_ECC_DEC 0x00000010 | ||
222 | /* Enable Interrupt */ | ||
223 | #define REG_UMI_BCH_CTRL_STATUS_INT_EN 0x00000004 | ||
224 | /* Enable ECC during read */ | ||
225 | #define REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN 0x00000002 | ||
226 | /* Enable ECC during write */ | ||
227 | #define REG_UMI_BCH_CTRL_STATUS_ECC_WR_EN 0x00000001 | ||
228 | /* Mask for location */ | ||
229 | #define REG_UMI_BCH_ERR_LOC_MASK 0x00001FFF | ||
230 | /* location within a byte */ | ||
231 | #define REG_UMI_BCH_ERR_LOC_BYTE 0x00000007 | ||
232 | /* location within a word */ | ||
233 | #define REG_UMI_BCH_ERR_LOC_WORD 0x00000018 | ||
234 | /* location within a page (512 byte) */ | ||
235 | #define REG_UMI_BCH_ERR_LOC_PAGE 0x00001FE0 | ||
236 | #define REG_UMI_BCH_ERR_LOC_ADDR(index) (__REG32(HW_UMI_BASE + 0x64 + (index / 2)*4) >> ((index % 2) * 16)) | ||
237 | #endif | ||
diff --git a/arch/arm/mach-clps711x/include/mach/memory.h b/arch/arm/mach-clps711x/include/mach/memory.h index e522b20bcbc2..f70d52be48a2 100644 --- a/arch/arm/mach-clps711x/include/mach/memory.h +++ b/arch/arm/mach-clps711x/include/mach/memory.h | |||
@@ -30,6 +30,8 @@ | |||
30 | 30 | ||
31 | #define __virt_to_bus(x) ((x) - PAGE_OFFSET) | 31 | #define __virt_to_bus(x) ((x) - PAGE_OFFSET) |
32 | #define __bus_to_virt(x) ((x) + PAGE_OFFSET) | 32 | #define __bus_to_virt(x) ((x) + PAGE_OFFSET) |
33 | #define __pfn_to_bus(x) (__pfn_to_phys(x) - PHYS_OFFSET) | ||
34 | #define __bus_to_pfn(x) __phys_to_pfn((x) + PHYS_OFFSET) | ||
33 | 35 | ||
34 | #endif | 36 | #endif |
35 | 37 | ||
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c index 62b98bffc158..07de8db14581 100644 --- a/arch/arm/mach-davinci/board-da850-evm.c +++ b/arch/arm/mach-davinci/board-da850-evm.c | |||
@@ -339,6 +339,15 @@ static struct davinci_mmc_config da850_mmc_config = { | |||
339 | .version = MMC_CTLR_VERSION_2, | 339 | .version = MMC_CTLR_VERSION_2, |
340 | }; | 340 | }; |
341 | 341 | ||
342 | static void da850_panel_power_ctrl(int val) | ||
343 | { | ||
344 | /* lcd backlight */ | ||
345 | gpio_set_value(DA850_LCD_BL_PIN, val); | ||
346 | |||
347 | /* lcd power */ | ||
348 | gpio_set_value(DA850_LCD_PWR_PIN, val); | ||
349 | } | ||
350 | |||
342 | static int da850_lcd_hw_init(void) | 351 | static int da850_lcd_hw_init(void) |
343 | { | 352 | { |
344 | int status; | 353 | int status; |
@@ -356,17 +365,11 @@ static int da850_lcd_hw_init(void) | |||
356 | gpio_direction_output(DA850_LCD_BL_PIN, 0); | 365 | gpio_direction_output(DA850_LCD_BL_PIN, 0); |
357 | gpio_direction_output(DA850_LCD_PWR_PIN, 0); | 366 | gpio_direction_output(DA850_LCD_PWR_PIN, 0); |
358 | 367 | ||
359 | /* disable lcd backlight */ | 368 | /* Switch off panel power and backlight */ |
360 | gpio_set_value(DA850_LCD_BL_PIN, 0); | 369 | da850_panel_power_ctrl(0); |
361 | |||
362 | /* disable lcd power */ | ||
363 | gpio_set_value(DA850_LCD_PWR_PIN, 0); | ||
364 | |||
365 | /* enable lcd power */ | ||
366 | gpio_set_value(DA850_LCD_PWR_PIN, 1); | ||
367 | 370 | ||
368 | /* enable lcd backlight */ | 371 | /* Switch on panel power and backlight */ |
369 | gpio_set_value(DA850_LCD_BL_PIN, 1); | 372 | da850_panel_power_ctrl(1); |
370 | 373 | ||
371 | return 0; | 374 | return 0; |
372 | } | 375 | } |
@@ -674,6 +677,7 @@ static __init void da850_evm_init(void) | |||
674 | pr_warning("da850_evm_init: lcd initialization failed: %d\n", | 677 | pr_warning("da850_evm_init: lcd initialization failed: %d\n", |
675 | ret); | 678 | ret); |
676 | 679 | ||
680 | sharp_lk043t1dg01_pdata.panel_power_ctrl = da850_panel_power_ctrl, | ||
677 | ret = da8xx_register_lcdc(&sharp_lk043t1dg01_pdata); | 681 | ret = da8xx_register_lcdc(&sharp_lk043t1dg01_pdata); |
678 | if (ret) | 682 | if (ret) |
679 | pr_warning("da850_evm_init: lcdc registration failed: %d\n", | 683 | pr_warning("da850_evm_init: lcdc registration failed: %d\n", |
diff --git a/arch/arm/mach-davinci/include/mach/nand.h b/arch/arm/mach-davinci/include/mach/nand.h index b520c4b5678a..b2ad8090bd10 100644 --- a/arch/arm/mach-davinci/include/mach/nand.h +++ b/arch/arm/mach-davinci/include/mach/nand.h | |||
@@ -79,6 +79,10 @@ struct davinci_nand_pdata { /* platform_data */ | |||
79 | 79 | ||
80 | /* e.g. NAND_BUSWIDTH_16 or NAND_USE_FLASH_BBT */ | 80 | /* e.g. NAND_BUSWIDTH_16 or NAND_USE_FLASH_BBT */ |
81 | unsigned options; | 81 | unsigned options; |
82 | |||
83 | /* Main and mirror bbt descriptor overrides */ | ||
84 | struct nand_bbt_descr *bbt_td; | ||
85 | struct nand_bbt_descr *bbt_md; | ||
82 | }; | 86 | }; |
83 | 87 | ||
84 | #endif /* __ARCH_ARM_DAVINCI_NAND_H */ | 88 | #endif /* __ARCH_ARM_DAVINCI_NAND_H */ |
diff --git a/arch/arm/mach-ep93xx/include/mach/ep93xx_keypad.h b/arch/arm/mach-ep93xx/include/mach/ep93xx_keypad.h index 83f31cd0a274..62d17421e48c 100644 --- a/arch/arm/mach-ep93xx/include/mach/ep93xx_keypad.h +++ b/arch/arm/mach-ep93xx/include/mach/ep93xx_keypad.h | |||
@@ -5,9 +5,6 @@ | |||
5 | #ifndef __ASM_ARCH_EP93XX_KEYPAD_H | 5 | #ifndef __ASM_ARCH_EP93XX_KEYPAD_H |
6 | #define __ASM_ARCH_EP93XX_KEYPAD_H | 6 | #define __ASM_ARCH_EP93XX_KEYPAD_H |
7 | 7 | ||
8 | #define MAX_MATRIX_KEY_ROWS (8) | ||
9 | #define MAX_MATRIX_KEY_COLS (8) | ||
10 | |||
11 | /* flags for the ep93xx_keypad driver */ | 8 | /* flags for the ep93xx_keypad driver */ |
12 | #define EP93XX_KEYPAD_DISABLE_3_KEY (1<<0) /* disable 3-key reset */ | 9 | #define EP93XX_KEYPAD_DISABLE_3_KEY (1<<0) /* disable 3-key reset */ |
13 | #define EP93XX_KEYPAD_DIAG_MODE (1<<1) /* diagnostic mode */ | 10 | #define EP93XX_KEYPAD_DIAG_MODE (1<<1) /* diagnostic mode */ |
@@ -18,8 +15,6 @@ | |||
18 | 15 | ||
19 | /** | 16 | /** |
20 | * struct ep93xx_keypad_platform_data - platform specific device structure | 17 | * struct ep93xx_keypad_platform_data - platform specific device structure |
21 | * @matrix_key_rows: number of rows in the keypad matrix | ||
22 | * @matrix_key_cols: number of columns in the keypad matrix | ||
23 | * @matrix_key_map: array of keycodes defining the keypad matrix | 18 | * @matrix_key_map: array of keycodes defining the keypad matrix |
24 | * @matrix_key_map_size: ARRAY_SIZE(matrix_key_map) | 19 | * @matrix_key_map_size: ARRAY_SIZE(matrix_key_map) |
25 | * @debounce: debounce start count; terminal count is 0xff | 20 | * @debounce: debounce start count; terminal count is 0xff |
@@ -27,8 +22,6 @@ | |||
27 | * @flags: see above | 22 | * @flags: see above |
28 | */ | 23 | */ |
29 | struct ep93xx_keypad_platform_data { | 24 | struct ep93xx_keypad_platform_data { |
30 | unsigned int matrix_key_rows; | ||
31 | unsigned int matrix_key_cols; | ||
32 | unsigned int *matrix_key_map; | 25 | unsigned int *matrix_key_map; |
33 | int matrix_key_map_size; | 26 | int matrix_key_map_size; |
34 | unsigned int debounce; | 27 | unsigned int debounce; |
@@ -36,7 +29,7 @@ struct ep93xx_keypad_platform_data { | |||
36 | unsigned int flags; | 29 | unsigned int flags; |
37 | }; | 30 | }; |
38 | 31 | ||
39 | /* macro for creating the matrix_key_map table */ | 32 | #define EP93XX_MATRIX_ROWS (8) |
40 | #define KEY(row, col, val) (((row) << 28) | ((col) << 24) | (val)) | 33 | #define EP93XX_MATRIX_COLS (8) |
41 | 34 | ||
42 | #endif /* __ASM_ARCH_EP93XX_KEYPAD_H */ | 35 | #endif /* __ASM_ARCH_EP93XX_KEYPAD_H */ |
diff --git a/arch/arm/mach-footbridge/common.c b/arch/arm/mach-footbridge/common.c index b97f529e58e8..41febc796b1c 100644 --- a/arch/arm/mach-footbridge/common.c +++ b/arch/arm/mach-footbridge/common.c | |||
@@ -201,6 +201,11 @@ void __init footbridge_map_io(void) | |||
201 | 201 | ||
202 | #ifdef CONFIG_FOOTBRIDGE_ADDIN | 202 | #ifdef CONFIG_FOOTBRIDGE_ADDIN |
203 | 203 | ||
204 | static inline unsigned long fb_bus_sdram_offset(void) | ||
205 | { | ||
206 | return *CSR_PCISDRAMBASE & 0xfffffff0; | ||
207 | } | ||
208 | |||
204 | /* | 209 | /* |
205 | * These two functions convert virtual addresses to PCI addresses and PCI | 210 | * These two functions convert virtual addresses to PCI addresses and PCI |
206 | * addresses to virtual addresses. Note that it is only legal to use these | 211 | * addresses to virtual addresses. Note that it is only legal to use these |
@@ -210,14 +215,13 @@ unsigned long __virt_to_bus(unsigned long res) | |||
210 | { | 215 | { |
211 | WARN_ON(res < PAGE_OFFSET || res >= (unsigned long)high_memory); | 216 | WARN_ON(res < PAGE_OFFSET || res >= (unsigned long)high_memory); |
212 | 217 | ||
213 | return (res - PAGE_OFFSET) + (*CSR_PCISDRAMBASE & 0xfffffff0); | 218 | return res + (fb_bus_sdram_offset() - PAGE_OFFSET); |
214 | } | 219 | } |
215 | EXPORT_SYMBOL(__virt_to_bus); | 220 | EXPORT_SYMBOL(__virt_to_bus); |
216 | 221 | ||
217 | unsigned long __bus_to_virt(unsigned long res) | 222 | unsigned long __bus_to_virt(unsigned long res) |
218 | { | 223 | { |
219 | res -= (*CSR_PCISDRAMBASE & 0xfffffff0); | 224 | res = res - (fb_bus_sdram_offset() - PAGE_OFFSET); |
220 | res += PAGE_OFFSET; | ||
221 | 225 | ||
222 | WARN_ON(res < PAGE_OFFSET || res >= (unsigned long)high_memory); | 226 | WARN_ON(res < PAGE_OFFSET || res >= (unsigned long)high_memory); |
223 | 227 | ||
@@ -225,4 +229,16 @@ unsigned long __bus_to_virt(unsigned long res) | |||
225 | } | 229 | } |
226 | EXPORT_SYMBOL(__bus_to_virt); | 230 | EXPORT_SYMBOL(__bus_to_virt); |
227 | 231 | ||
232 | unsigned long __pfn_to_bus(unsigned long pfn) | ||
233 | { | ||
234 | return __pfn_to_phys(pfn) + (fb_bus_sdram_offset() - PHYS_OFFSET)); | ||
235 | } | ||
236 | EXPORT_SYMBOL(__pfn_to_bus); | ||
237 | |||
238 | unsigned long __bus_to_pfn(unsigned long bus) | ||
239 | { | ||
240 | return __phys_to_pfn(bus - (fb_bus_sdram_offset() - PHYS_OFFSET)); | ||
241 | } | ||
242 | EXPORT_SYMBOL(__bus_to_pfn); | ||
243 | |||
228 | #endif | 244 | #endif |
diff --git a/arch/arm/mach-footbridge/include/mach/memory.h b/arch/arm/mach-footbridge/include/mach/memory.h index cb16e59d87b6..8d64f4574087 100644 --- a/arch/arm/mach-footbridge/include/mach/memory.h +++ b/arch/arm/mach-footbridge/include/mach/memory.h | |||
@@ -29,6 +29,8 @@ | |||
29 | #ifndef __ASSEMBLY__ | 29 | #ifndef __ASSEMBLY__ |
30 | extern unsigned long __virt_to_bus(unsigned long); | 30 | extern unsigned long __virt_to_bus(unsigned long); |
31 | extern unsigned long __bus_to_virt(unsigned long); | 31 | extern unsigned long __bus_to_virt(unsigned long); |
32 | extern unsigned long __pfn_to_bus(unsigned long); | ||
33 | extern unsigned long __bus_to_pfn(unsigned long); | ||
32 | #endif | 34 | #endif |
33 | #define __virt_to_bus __virt_to_bus | 35 | #define __virt_to_bus __virt_to_bus |
34 | #define __bus_to_virt __bus_to_virt | 36 | #define __bus_to_virt __bus_to_virt |
@@ -36,14 +38,15 @@ extern unsigned long __bus_to_virt(unsigned long); | |||
36 | #elif defined(CONFIG_FOOTBRIDGE_HOST) | 38 | #elif defined(CONFIG_FOOTBRIDGE_HOST) |
37 | 39 | ||
38 | /* | 40 | /* |
39 | * The footbridge is programmed to expose the system RAM at the corresponding | 41 | * The footbridge is programmed to expose the system RAM at 0xe0000000. |
40 | * address. So, if PAGE_OFFSET is 0xc0000000, RAM appears at 0xe0000000. | 42 | * The requirement is that the RAM isn't placed at bus address 0, which |
41 | * If 0x80000000, then its exposed at 0xa0000000 on the bus. etc. | ||
42 | * The only requirement is that the RAM isn't placed at bus address 0 which | ||
43 | * would clash with VGA cards. | 43 | * would clash with VGA cards. |
44 | */ | 44 | */ |
45 | #define __virt_to_bus(x) ((x) - 0xe0000000) | 45 | #define BUS_OFFSET 0xe0000000 |
46 | #define __bus_to_virt(x) ((x) + 0xe0000000) | 46 | #define __virt_to_bus(x) ((x) + (BUS_OFFSET - PAGE_OFFSET)) |
47 | #define __bus_to_virt(x) ((x) - (BUS_OFFSET - PAGE_OFFSET)) | ||
48 | #define __pfn_to_bus(x) (__pfn_to_phys(x) + (BUS_OFFSET - PHYS_OFFSET)) | ||
49 | #define __bus_to_pfn(x) __phys_to_pfn((x) - (BUS_OFFSET - PHYS_OFFSET)) | ||
47 | 50 | ||
48 | #else | 51 | #else |
49 | 52 | ||
diff --git a/arch/arm/mach-integrator/include/mach/memory.h b/arch/arm/mach-integrator/include/mach/memory.h index 4891828454f5..991f24d2c115 100644 --- a/arch/arm/mach-integrator/include/mach/memory.h +++ b/arch/arm/mach-integrator/include/mach/memory.h | |||
@@ -28,6 +28,7 @@ | |||
28 | #define BUS_OFFSET UL(0x80000000) | 28 | #define BUS_OFFSET UL(0x80000000) |
29 | #define __virt_to_bus(x) ((x) - PAGE_OFFSET + BUS_OFFSET) | 29 | #define __virt_to_bus(x) ((x) - PAGE_OFFSET + BUS_OFFSET) |
30 | #define __bus_to_virt(x) ((x) - BUS_OFFSET + PAGE_OFFSET) | 30 | #define __bus_to_virt(x) ((x) - BUS_OFFSET + PAGE_OFFSET) |
31 | #define __pfn_to_bus(x) (((x) << PAGE_SHIFT) + BUS_OFFSET) | 31 | #define __pfn_to_bus(x) (__pfn_to_phys(x) + (BUS_OFFSET - PHYS_OFFSET)) |
32 | #define __bus_to_pfn(x) __phys_to_pfn((x) - (BUS_OFFSET - PHYS_OFFSET)) | ||
32 | 33 | ||
33 | #endif | 34 | #endif |
diff --git a/arch/arm/mach-ixp2000/include/mach/memory.h b/arch/arm/mach-ixp2000/include/mach/memory.h index aee7eb8a71b2..98e3471be15b 100644 --- a/arch/arm/mach-ixp2000/include/mach/memory.h +++ b/arch/arm/mach-ixp2000/include/mach/memory.h | |||
@@ -17,11 +17,15 @@ | |||
17 | 17 | ||
18 | #include <mach/ixp2000-regs.h> | 18 | #include <mach/ixp2000-regs.h> |
19 | 19 | ||
20 | #define __virt_to_bus(v) \ | 20 | #define IXP2000_PCI_SDRAM_OFFSET (*IXP2000_PCI_SDRAM_BAR & 0xfffffff0) |
21 | (((__virt_to_phys(v) - 0x0) + (*IXP2000_PCI_SDRAM_BAR & 0xfffffff0))) | ||
22 | 21 | ||
23 | #define __bus_to_virt(b) \ | 22 | #define __phys_to_bus(x) ((x) + (IXP2000_PCI_SDRAM_OFFSET - PHYS_OFFSET)) |
24 | __phys_to_virt((((b - (*IXP2000_PCI_SDRAM_BAR & 0xfffffff0)) + 0x0))) | 23 | #define __bus_to_phys(x) ((x) - (IXP2000_PCI_SDRAM_OFFSET - PHYS_OFFSET)) |
24 | |||
25 | #define __virt_to_bus(v) __phys_to_bus(__virt_to_phys(v)) | ||
26 | #define __bus_to_virt(b) __phys_to_virt(__bus_to_phys(b)) | ||
27 | #define __pfn_to_bus(p) __phys_to_bus(__pfn_to_phys(p)) | ||
28 | #define __bus_to_pfn(b) __phys_to_pfn(__bus_to_phys(b)) | ||
25 | 29 | ||
26 | #endif | 30 | #endif |
27 | 31 | ||
diff --git a/arch/arm/mach-ixp23xx/include/mach/memory.h b/arch/arm/mach-ixp23xx/include/mach/memory.h index fdd138706c70..94a3a86cfeb8 100644 --- a/arch/arm/mach-ixp23xx/include/mach/memory.h +++ b/arch/arm/mach-ixp23xx/include/mach/memory.h | |||
@@ -19,16 +19,15 @@ | |||
19 | */ | 19 | */ |
20 | #define PHYS_OFFSET (0x00000000) | 20 | #define PHYS_OFFSET (0x00000000) |
21 | 21 | ||
22 | #define __virt_to_bus(v) \ | 22 | #define IXP23XX_PCI_SDRAM_OFFSET (*((volatile int *)IXP23XX_PCI_SDRAM_BAR) & 0xfffffff0)) |
23 | ({ unsigned int ret; \ | 23 | |
24 | ret = ((__virt_to_phys(v) - 0x00000000) + \ | 24 | #define __phys_to_bus(x) ((x) + (IXP23XX_PCI_SDRAM_OFFSET - PHYS_OFFSET)) |
25 | (*((volatile int *)IXP23XX_PCI_SDRAM_BAR) & 0xfffffff0)); \ | 25 | #define __bus_to_phys(x) ((x) - (IXP23XX_PCI_SDRAM_OFFSET - PHYS_OFFSET)) |
26 | ret; }) | 26 | |
27 | 27 | #define __virt_to_bus(v) __phys_to_bus(__virt_to_phys(v)) | |
28 | #define __bus_to_virt(b) \ | 28 | #define __bus_to_virt(b) __phys_to_virt(__bus_to_phys(b)) |
29 | ({ unsigned int data; \ | 29 | #define __pfn_to_bus(p) __phys_to_bus(__pfn_to_phys(p)) |
30 | data = *((volatile int *)IXP23XX_PCI_SDRAM_BAR); \ | 30 | #define __bus_to_pfn(b) __phys_to_pfn(__bus_to_phys(b)) |
31 | __phys_to_virt((((b - (data & 0xfffffff0)) + 0x00000000))); }) | ||
32 | 31 | ||
33 | #define arch_is_coherent() 1 | 32 | #define arch_is_coherent() 1 |
34 | 33 | ||
diff --git a/arch/arm/mach-ixp4xx/Kconfig b/arch/arm/mach-ixp4xx/Kconfig index 264f4d59f898..9e5070da17ae 100644 --- a/arch/arm/mach-ixp4xx/Kconfig +++ b/arch/arm/mach-ixp4xx/Kconfig | |||
@@ -179,21 +179,21 @@ config IXP4XX_INDIRECT_PCI | |||
179 | help | 179 | help |
180 | IXP4xx provides two methods of accessing PCI memory space: | 180 | IXP4xx provides two methods of accessing PCI memory space: |
181 | 181 | ||
182 | 1) A direct mapped window from 0x48000000 to 0x4bffffff (64MB). | 182 | 1) A direct mapped window from 0x48000000 to 0x4BFFFFFF (64MB). |
183 | To access PCI via this space, we simply ioremap() the BAR | 183 | To access PCI via this space, we simply ioremap() the BAR |
184 | into the kernel and we can use the standard read[bwl]/write[bwl] | 184 | into the kernel and we can use the standard read[bwl]/write[bwl] |
185 | macros. This is the preferred method due to speed but it | 185 | macros. This is the preferred method due to speed but it |
186 | limits the system to just 64MB of PCI memory. This can be | 186 | limits the system to just 64MB of PCI memory. This can be |
187 | problematic if using video cards and other memory-heavy devices. | 187 | problematic if using video cards and other memory-heavy devices. |
188 | 188 | ||
189 | 2) If > 64MB of memory space is required, the IXP4xx can be | 189 | 2) If > 64MB of memory space is required, the IXP4xx can be |
190 | configured to use indirect registers to access PCI This allows | 190 | configured to use indirect registers to access the whole PCI |
191 | for up to 128MB (0x48000000 to 0x4fffffff) of memory on the bus. | 191 | memory space. This currently allows for up to 1 GB (0x10000000 |
192 | The disadvantage of this is that every PCI access requires | 192 | to 0x4FFFFFFF) of memory on the bus. The disadvantage of this |
193 | three local register accesses plus a spinlock, but in some | 193 | is that every PCI access requires three local register accesses |
194 | cases the performance hit is acceptable. In addition, you cannot | 194 | plus a spinlock, but in some cases the performance hit is |
195 | mmap() PCI devices in this case due to the indirect nature | 195 | acceptable. In addition, you cannot mmap() PCI devices in this |
196 | of the PCI window. | 196 | case due to the indirect nature of the PCI window. |
197 | 197 | ||
198 | By default, the direct method is used. Choose this option if you | 198 | By default, the direct method is used. Choose this option if you |
199 | need to use the indirect method instead. If you don't know | 199 | need to use the indirect method instead. If you don't know |
diff --git a/arch/arm/mach-ixp4xx/avila-pci.c b/arch/arm/mach-ixp4xx/avila-pci.c index 08d65dcdb5fe..845e1b500548 100644 --- a/arch/arm/mach-ixp4xx/avila-pci.c +++ b/arch/arm/mach-ixp4xx/avila-pci.c | |||
@@ -22,40 +22,45 @@ | |||
22 | #include <linux/init.h> | 22 | #include <linux/init.h> |
23 | #include <linux/irq.h> | 23 | #include <linux/irq.h> |
24 | #include <linux/delay.h> | 24 | #include <linux/delay.h> |
25 | |||
26 | #include <asm/mach/pci.h> | 25 | #include <asm/mach/pci.h> |
27 | #include <asm/irq.h> | 26 | #include <asm/irq.h> |
28 | #include <mach/hardware.h> | 27 | #include <mach/hardware.h> |
29 | #include <asm/mach-types.h> | 28 | #include <asm/mach-types.h> |
30 | 29 | ||
30 | #define AVILA_MAX_DEV 4 | ||
31 | #define LOFT_MAX_DEV 6 | ||
32 | #define IRQ_LINES 4 | ||
33 | |||
34 | /* PCI controller GPIO to IRQ pin mappings */ | ||
35 | #define INTA 11 | ||
36 | #define INTB 10 | ||
37 | #define INTC 9 | ||
38 | #define INTD 8 | ||
39 | |||
31 | void __init avila_pci_preinit(void) | 40 | void __init avila_pci_preinit(void) |
32 | { | 41 | { |
33 | set_irq_type(IRQ_AVILA_PCI_INTA, IRQ_TYPE_LEVEL_LOW); | 42 | set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); |
34 | set_irq_type(IRQ_AVILA_PCI_INTB, IRQ_TYPE_LEVEL_LOW); | 43 | set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); |
35 | set_irq_type(IRQ_AVILA_PCI_INTC, IRQ_TYPE_LEVEL_LOW); | 44 | set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); |
36 | set_irq_type(IRQ_AVILA_PCI_INTD, IRQ_TYPE_LEVEL_LOW); | 45 | set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW); |
37 | |||
38 | ixp4xx_pci_preinit(); | 46 | ixp4xx_pci_preinit(); |
39 | } | 47 | } |
40 | 48 | ||
41 | static int __init avila_map_irq(struct pci_dev *dev, u8 slot, u8 pin) | 49 | static int __init avila_map_irq(struct pci_dev *dev, u8 slot, u8 pin) |
42 | { | 50 | { |
43 | static int pci_irq_table[AVILA_PCI_IRQ_LINES] = { | 51 | static int pci_irq_table[IRQ_LINES] = { |
44 | IRQ_AVILA_PCI_INTA, | 52 | IXP4XX_GPIO_IRQ(INTA), |
45 | IRQ_AVILA_PCI_INTB, | 53 | IXP4XX_GPIO_IRQ(INTB), |
46 | IRQ_AVILA_PCI_INTC, | 54 | IXP4XX_GPIO_IRQ(INTC), |
47 | IRQ_AVILA_PCI_INTD | 55 | IXP4XX_GPIO_IRQ(INTD) |
48 | }; | 56 | }; |
49 | 57 | ||
50 | int irq = -1; | ||
51 | |||
52 | if (slot >= 1 && | 58 | if (slot >= 1 && |
53 | slot <= (machine_is_loft() ? LOFT_PCI_MAX_DEV : AVILA_PCI_MAX_DEV) && | 59 | slot <= (machine_is_loft() ? LOFT_MAX_DEV : AVILA_MAX_DEV) && |
54 | pin >= 1 && pin <= AVILA_PCI_IRQ_LINES) { | 60 | pin >= 1 && pin <= IRQ_LINES) |
55 | irq = pci_irq_table[(slot + pin - 2) % 4]; | 61 | return pci_irq_table[(slot + pin - 2) % 4]; |
56 | } | ||
57 | 62 | ||
58 | return irq; | 63 | return -1; |
59 | } | 64 | } |
60 | 65 | ||
61 | struct hw_pci avila_pci __initdata = { | 66 | struct hw_pci avila_pci __initdata = { |
@@ -75,4 +80,3 @@ int __init avila_pci_init(void) | |||
75 | } | 80 | } |
76 | 81 | ||
77 | subsys_initcall(avila_pci_init); | 82 | subsys_initcall(avila_pci_init); |
78 | |||
diff --git a/arch/arm/mach-ixp4xx/avila-setup.c b/arch/arm/mach-ixp4xx/avila-setup.c index 797995ce18b9..6e558a76457d 100644 --- a/arch/arm/mach-ixp4xx/avila-setup.c +++ b/arch/arm/mach-ixp4xx/avila-setup.c | |||
@@ -19,7 +19,6 @@ | |||
19 | #include <linux/serial_8250.h> | 19 | #include <linux/serial_8250.h> |
20 | #include <linux/slab.h> | 20 | #include <linux/slab.h> |
21 | #include <linux/i2c-gpio.h> | 21 | #include <linux/i2c-gpio.h> |
22 | |||
23 | #include <asm/types.h> | 22 | #include <asm/types.h> |
24 | #include <asm/setup.h> | 23 | #include <asm/setup.h> |
25 | #include <asm/memory.h> | 24 | #include <asm/memory.h> |
@@ -29,6 +28,9 @@ | |||
29 | #include <asm/mach/arch.h> | 28 | #include <asm/mach/arch.h> |
30 | #include <asm/mach/flash.h> | 29 | #include <asm/mach/flash.h> |
31 | 30 | ||
31 | #define AVILA_SDA_PIN 7 | ||
32 | #define AVILA_SCL_PIN 6 | ||
33 | |||
32 | static struct flash_platform_data avila_flash_data = { | 34 | static struct flash_platform_data avila_flash_data = { |
33 | .map_name = "cfi_probe", | 35 | .map_name = "cfi_probe", |
34 | .width = 2, | 36 | .width = 2, |
diff --git a/arch/arm/mach-ixp4xx/common-pci.c b/arch/arm/mach-ixp4xx/common-pci.c index 70afcfe5b881..c4a01594c761 100644 --- a/arch/arm/mach-ixp4xx/common-pci.c +++ b/arch/arm/mach-ixp4xx/common-pci.c | |||
@@ -481,11 +481,7 @@ int ixp4xx_setup(int nr, struct pci_sys_data *sys) | |||
481 | 481 | ||
482 | res[1].name = "PCI Memory Space"; | 482 | res[1].name = "PCI Memory Space"; |
483 | res[1].start = PCIBIOS_MIN_MEM; | 483 | res[1].start = PCIBIOS_MIN_MEM; |
484 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | 484 | res[1].end = PCIBIOS_MAX_MEM; |
485 | res[1].end = 0x4bffffff; | ||
486 | #else | ||
487 | res[1].end = 0x4fffffff; | ||
488 | #endif | ||
489 | res[1].flags = IORESOURCE_MEM; | 485 | res[1].flags = IORESOURCE_MEM; |
490 | 486 | ||
491 | request_resource(&ioport_resource, &res[0]); | 487 | request_resource(&ioport_resource, &res[0]); |
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c index cfd52fb341cb..3bbf40f6d964 100644 --- a/arch/arm/mach-ixp4xx/common.c +++ b/arch/arm/mach-ixp4xx/common.c | |||
@@ -117,7 +117,7 @@ int gpio_to_irq(int gpio) | |||
117 | } | 117 | } |
118 | EXPORT_SYMBOL(gpio_to_irq); | 118 | EXPORT_SYMBOL(gpio_to_irq); |
119 | 119 | ||
120 | int irq_to_gpio(int irq) | 120 | int irq_to_gpio(unsigned int irq) |
121 | { | 121 | { |
122 | int gpio = (irq < 32) ? irq2gpio[irq] : -EINVAL; | 122 | int gpio = (irq < 32) ? irq2gpio[irq] : -EINVAL; |
123 | 123 | ||
diff --git a/arch/arm/mach-ixp4xx/coyote-pci.c b/arch/arm/mach-ixp4xx/coyote-pci.c index efddf01ed17b..b978ea8bd6f0 100644 --- a/arch/arm/mach-ixp4xx/coyote-pci.c +++ b/arch/arm/mach-ixp4xx/coyote-pci.c | |||
@@ -18,27 +18,31 @@ | |||
18 | #include <linux/pci.h> | 18 | #include <linux/pci.h> |
19 | #include <linux/init.h> | 19 | #include <linux/init.h> |
20 | #include <linux/irq.h> | 20 | #include <linux/irq.h> |
21 | |||
22 | #include <asm/mach-types.h> | 21 | #include <asm/mach-types.h> |
23 | #include <mach/hardware.h> | 22 | #include <mach/hardware.h> |
24 | #include <asm/irq.h> | 23 | #include <asm/irq.h> |
25 | |||
26 | #include <asm/mach/pci.h> | 24 | #include <asm/mach/pci.h> |
27 | 25 | ||
26 | #define SLOT0_DEVID 14 | ||
27 | #define SLOT1_DEVID 15 | ||
28 | |||
29 | /* PCI controller GPIO to IRQ pin mappings */ | ||
30 | #define SLOT0_INTA 6 | ||
31 | #define SLOT1_INTA 11 | ||
32 | |||
28 | void __init coyote_pci_preinit(void) | 33 | void __init coyote_pci_preinit(void) |
29 | { | 34 | { |
30 | set_irq_type(IRQ_COYOTE_PCI_SLOT0, IRQ_TYPE_LEVEL_LOW); | 35 | set_irq_type(IXP4XX_GPIO_IRQ(SLOT0_INTA), IRQ_TYPE_LEVEL_LOW); |
31 | set_irq_type(IRQ_COYOTE_PCI_SLOT1, IRQ_TYPE_LEVEL_LOW); | 36 | set_irq_type(IXP4XX_GPIO_IRQ(SLOT1_INTA), IRQ_TYPE_LEVEL_LOW); |
32 | |||
33 | ixp4xx_pci_preinit(); | 37 | ixp4xx_pci_preinit(); |
34 | } | 38 | } |
35 | 39 | ||
36 | static int __init coyote_map_irq(struct pci_dev *dev, u8 slot, u8 pin) | 40 | static int __init coyote_map_irq(struct pci_dev *dev, u8 slot, u8 pin) |
37 | { | 41 | { |
38 | if (slot == COYOTE_PCI_SLOT0_DEVID) | 42 | if (slot == SLOT0_DEVID) |
39 | return IRQ_COYOTE_PCI_SLOT0; | 43 | return IXP4XX_GPIO_IRQ(SLOT0_INTA); |
40 | else if (slot == COYOTE_PCI_SLOT1_DEVID) | 44 | else if (slot == SLOT1_DEVID) |
41 | return IRQ_COYOTE_PCI_SLOT1; | 45 | return IXP4XX_GPIO_IRQ(SLOT1_INTA); |
42 | else return -1; | 46 | else return -1; |
43 | } | 47 | } |
44 | 48 | ||
diff --git a/arch/arm/mach-ixp4xx/coyote-setup.c b/arch/arm/mach-ixp4xx/coyote-setup.c index aab1954e2747..25bf5ad770ea 100644 --- a/arch/arm/mach-ixp4xx/coyote-setup.c +++ b/arch/arm/mach-ixp4xx/coyote-setup.c | |||
@@ -25,6 +25,15 @@ | |||
25 | #include <asm/mach/arch.h> | 25 | #include <asm/mach/arch.h> |
26 | #include <asm/mach/flash.h> | 26 | #include <asm/mach/flash.h> |
27 | 27 | ||
28 | #define COYOTE_IDE_BASE_PHYS IXP4XX_EXP_BUS_BASE(3) | ||
29 | #define COYOTE_IDE_BASE_VIRT 0xFFFE1000 | ||
30 | #define COYOTE_IDE_REGION_SIZE 0x1000 | ||
31 | |||
32 | #define COYOTE_IDE_DATA_PORT 0xFFFE10E0 | ||
33 | #define COYOTE_IDE_CTRL_PORT 0xFFFE10FC | ||
34 | #define COYOTE_IDE_ERROR_PORT 0xFFFE10E2 | ||
35 | #define IRQ_COYOTE_IDE IRQ_IXP4XX_GPIO5 | ||
36 | |||
28 | static struct flash_platform_data coyote_flash_data = { | 37 | static struct flash_platform_data coyote_flash_data = { |
29 | .map_name = "cfi_probe", | 38 | .map_name = "cfi_probe", |
30 | .width = 2, | 39 | .width = 2, |
diff --git a/arch/arm/mach-ixp4xx/dsmg600-pci.c b/arch/arm/mach-ixp4xx/dsmg600-pci.c index 926d15f885fb..fa70fed462ba 100644 --- a/arch/arm/mach-ixp4xx/dsmg600-pci.c +++ b/arch/arm/mach-ixp4xx/dsmg600-pci.c | |||
@@ -19,39 +19,45 @@ | |||
19 | #include <linux/pci.h> | 19 | #include <linux/pci.h> |
20 | #include <linux/init.h> | 20 | #include <linux/init.h> |
21 | #include <linux/irq.h> | 21 | #include <linux/irq.h> |
22 | |||
23 | #include <asm/mach/pci.h> | 22 | #include <asm/mach/pci.h> |
24 | #include <asm/mach-types.h> | 23 | #include <asm/mach-types.h> |
25 | 24 | ||
25 | #define MAX_DEV 4 | ||
26 | #define IRQ_LINES 3 | ||
27 | |||
28 | /* PCI controller GPIO to IRQ pin mappings */ | ||
29 | #define INTA 11 | ||
30 | #define INTB 10 | ||
31 | #define INTC 9 | ||
32 | #define INTD 8 | ||
33 | #define INTE 7 | ||
34 | #define INTF 6 | ||
35 | |||
26 | void __init dsmg600_pci_preinit(void) | 36 | void __init dsmg600_pci_preinit(void) |
27 | { | 37 | { |
28 | set_irq_type(IRQ_DSMG600_PCI_INTA, IRQ_TYPE_LEVEL_LOW); | 38 | set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); |
29 | set_irq_type(IRQ_DSMG600_PCI_INTB, IRQ_TYPE_LEVEL_LOW); | 39 | set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); |
30 | set_irq_type(IRQ_DSMG600_PCI_INTC, IRQ_TYPE_LEVEL_LOW); | 40 | set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); |
31 | set_irq_type(IRQ_DSMG600_PCI_INTD, IRQ_TYPE_LEVEL_LOW); | 41 | set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW); |
32 | set_irq_type(IRQ_DSMG600_PCI_INTE, IRQ_TYPE_LEVEL_LOW); | 42 | set_irq_type(IXP4XX_GPIO_IRQ(INTE), IRQ_TYPE_LEVEL_LOW); |
33 | set_irq_type(IRQ_DSMG600_PCI_INTF, IRQ_TYPE_LEVEL_LOW); | 43 | set_irq_type(IXP4XX_GPIO_IRQ(INTF), IRQ_TYPE_LEVEL_LOW); |
34 | |||
35 | ixp4xx_pci_preinit(); | 44 | ixp4xx_pci_preinit(); |
36 | } | 45 | } |
37 | 46 | ||
38 | static int __init dsmg600_map_irq(struct pci_dev *dev, u8 slot, u8 pin) | 47 | static int __init dsmg600_map_irq(struct pci_dev *dev, u8 slot, u8 pin) |
39 | { | 48 | { |
40 | static int pci_irq_table[DSMG600_PCI_MAX_DEV][DSMG600_PCI_IRQ_LINES] = | 49 | static int pci_irq_table[MAX_DEV][IRQ_LINES] = { |
41 | { | 50 | { IXP4XX_GPIO_IRQ(INTE), -1, -1 }, |
42 | { IRQ_DSMG600_PCI_INTE, -1, -1 }, | 51 | { IXP4XX_GPIO_IRQ(INTA), -1, -1 }, |
43 | { IRQ_DSMG600_PCI_INTA, -1, -1 }, | 52 | { IXP4XX_GPIO_IRQ(INTB), IXP4XX_GPIO_IRQ(INTC), |
44 | { IRQ_DSMG600_PCI_INTB, IRQ_DSMG600_PCI_INTC, IRQ_DSMG600_PCI_INTD }, | 53 | IXP4XX_GPIO_IRQ(INTD) }, |
45 | { IRQ_DSMG600_PCI_INTF, -1, -1 }, | 54 | { IXP4XX_GPIO_IRQ(INTF), -1, -1 }, |
46 | }; | 55 | }; |
47 | 56 | ||
48 | int irq = -1; | 57 | if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES) |
49 | 58 | return pci_irq_table[slot - 1][pin - 1]; | |
50 | if (slot >= 1 && slot <= DSMG600_PCI_MAX_DEV && | ||
51 | pin >= 1 && pin <= DSMG600_PCI_IRQ_LINES) | ||
52 | irq = pci_irq_table[slot-1][pin-1]; | ||
53 | 59 | ||
54 | return irq; | 60 | return -1; |
55 | } | 61 | } |
56 | 62 | ||
57 | struct hw_pci __initdata dsmg600_pci = { | 63 | struct hw_pci __initdata dsmg600_pci = { |
diff --git a/arch/arm/mach-ixp4xx/dsmg600-setup.c b/arch/arm/mach-ixp4xx/dsmg600-setup.c index a51bfa6978b6..7c1fa54a6145 100644 --- a/arch/arm/mach-ixp4xx/dsmg600-setup.c +++ b/arch/arm/mach-ixp4xx/dsmg600-setup.c | |||
@@ -33,6 +33,23 @@ | |||
33 | #include <asm/mach/time.h> | 33 | #include <asm/mach/time.h> |
34 | #include <asm/gpio.h> | 34 | #include <asm/gpio.h> |
35 | 35 | ||
36 | #define DSMG600_SDA_PIN 5 | ||
37 | #define DSMG600_SCL_PIN 4 | ||
38 | |||
39 | /* DSM-G600 Timer Setting */ | ||
40 | #define DSMG600_FREQ 66000000 | ||
41 | |||
42 | /* Buttons */ | ||
43 | #define DSMG600_PB_GPIO 15 /* power button */ | ||
44 | #define DSMG600_RB_GPIO 3 /* reset button */ | ||
45 | |||
46 | /* Power control */ | ||
47 | #define DSMG600_PO_GPIO 2 /* power off */ | ||
48 | |||
49 | /* LEDs */ | ||
50 | #define DSMG600_LED_PWR_GPIO 0 | ||
51 | #define DSMG600_LED_WLAN_GPIO 14 | ||
52 | |||
36 | static struct flash_platform_data dsmg600_flash_data = { | 53 | static struct flash_platform_data dsmg600_flash_data = { |
37 | .map_name = "cfi_probe", | 54 | .map_name = "cfi_probe", |
38 | .width = 2, | 55 | .width = 2, |
diff --git a/arch/arm/mach-ixp4xx/fsg-pci.c b/arch/arm/mach-ixp4xx/fsg-pci.c index ca12a9ca0830..5a810c930624 100644 --- a/arch/arm/mach-ixp4xx/fsg-pci.c +++ b/arch/arm/mach-ixp4xx/fsg-pci.c | |||
@@ -19,33 +19,38 @@ | |||
19 | #include <linux/pci.h> | 19 | #include <linux/pci.h> |
20 | #include <linux/init.h> | 20 | #include <linux/init.h> |
21 | #include <linux/irq.h> | 21 | #include <linux/irq.h> |
22 | |||
23 | #include <asm/mach/pci.h> | 22 | #include <asm/mach/pci.h> |
24 | #include <asm/mach-types.h> | 23 | #include <asm/mach-types.h> |
25 | 24 | ||
25 | #define MAX_DEV 3 | ||
26 | #define IRQ_LINES 3 | ||
27 | |||
28 | /* PCI controller GPIO to IRQ pin mappings */ | ||
29 | #define INTA 6 | ||
30 | #define INTB 7 | ||
31 | #define INTC 5 | ||
32 | |||
26 | void __init fsg_pci_preinit(void) | 33 | void __init fsg_pci_preinit(void) |
27 | { | 34 | { |
28 | set_irq_type(IRQ_FSG_PCI_INTA, IRQ_TYPE_LEVEL_LOW); | 35 | set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); |
29 | set_irq_type(IRQ_FSG_PCI_INTB, IRQ_TYPE_LEVEL_LOW); | 36 | set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); |
30 | set_irq_type(IRQ_FSG_PCI_INTC, IRQ_TYPE_LEVEL_LOW); | 37 | set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); |
31 | |||
32 | ixp4xx_pci_preinit(); | 38 | ixp4xx_pci_preinit(); |
33 | } | 39 | } |
34 | 40 | ||
35 | static int __init fsg_map_irq(struct pci_dev *dev, u8 slot, u8 pin) | 41 | static int __init fsg_map_irq(struct pci_dev *dev, u8 slot, u8 pin) |
36 | { | 42 | { |
37 | static int pci_irq_table[FSG_PCI_IRQ_LINES] = { | 43 | static int pci_irq_table[IRQ_LINES] = { |
38 | IRQ_FSG_PCI_INTC, | 44 | IXP4XX_GPIO_IRQ(INTC), |
39 | IRQ_FSG_PCI_INTB, | 45 | IXP4XX_GPIO_IRQ(INTB), |
40 | IRQ_FSG_PCI_INTA, | 46 | IXP4XX_GPIO_IRQ(INTA), |
41 | }; | 47 | }; |
42 | 48 | ||
43 | int irq = -1; | 49 | int irq = -1; |
44 | slot = slot - 11; | 50 | slot -= 11; |
45 | 51 | ||
46 | if (slot >= 1 && slot <= FSG_PCI_MAX_DEV && | 52 | if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES) |
47 | pin >= 1 && pin <= FSG_PCI_IRQ_LINES) | 53 | irq = pci_irq_table[slot - 1]; |
48 | irq = pci_irq_table[(slot - 1)]; | ||
49 | printk(KERN_INFO "%s: Mapped slot %d pin %d to IRQ %d\n", | 54 | printk(KERN_INFO "%s: Mapped slot %d pin %d to IRQ %d\n", |
50 | __func__, slot, pin, irq); | 55 | __func__, slot, pin, irq); |
51 | 56 | ||
diff --git a/arch/arm/mach-ixp4xx/fsg-setup.c b/arch/arm/mach-ixp4xx/fsg-setup.c index 5add22fc9899..e7f4befba422 100644 --- a/arch/arm/mach-ixp4xx/fsg-setup.c +++ b/arch/arm/mach-ixp4xx/fsg-setup.c | |||
@@ -24,12 +24,18 @@ | |||
24 | #include <linux/i2c.h> | 24 | #include <linux/i2c.h> |
25 | #include <linux/i2c-gpio.h> | 25 | #include <linux/i2c-gpio.h> |
26 | #include <linux/io.h> | 26 | #include <linux/io.h> |
27 | |||
28 | #include <asm/mach-types.h> | 27 | #include <asm/mach-types.h> |
29 | #include <asm/mach/arch.h> | 28 | #include <asm/mach/arch.h> |
30 | #include <asm/mach/flash.h> | 29 | #include <asm/mach/flash.h> |
31 | #include <asm/gpio.h> | 30 | #include <asm/gpio.h> |
32 | 31 | ||
32 | #define FSG_SDA_PIN 12 | ||
33 | #define FSG_SCL_PIN 13 | ||
34 | |||
35 | #define FSG_SB_GPIO 4 /* sync button */ | ||
36 | #define FSG_RB_GPIO 9 /* reset button */ | ||
37 | #define FSG_UB_GPIO 10 /* usb button */ | ||
38 | |||
33 | static struct flash_platform_data fsg_flash_data = { | 39 | static struct flash_platform_data fsg_flash_data = { |
34 | .map_name = "cfi_probe", | 40 | .map_name = "cfi_probe", |
35 | .width = 2, | 41 | .width = 2, |
diff --git a/arch/arm/mach-ixp4xx/goramo_mlr.c b/arch/arm/mach-ixp4xx/goramo_mlr.c index a733b8ff3cec..1c28048209c1 100644 --- a/arch/arm/mach-ixp4xx/goramo_mlr.c +++ b/arch/arm/mach-ixp4xx/goramo_mlr.c | |||
@@ -17,29 +17,28 @@ | |||
17 | #include <asm/mach/flash.h> | 17 | #include <asm/mach/flash.h> |
18 | #include <asm/mach/pci.h> | 18 | #include <asm/mach/pci.h> |
19 | 19 | ||
20 | #define xgpio_irq(n) (IRQ_IXP4XX_GPIO ## n) | ||
21 | #define gpio_irq(n) xgpio_irq(n) | ||
22 | |||
23 | #define SLOT_ETHA 0x0B /* IDSEL = AD21 */ | 20 | #define SLOT_ETHA 0x0B /* IDSEL = AD21 */ |
24 | #define SLOT_ETHB 0x0C /* IDSEL = AD20 */ | 21 | #define SLOT_ETHB 0x0C /* IDSEL = AD20 */ |
25 | #define SLOT_MPCI 0x0D /* IDSEL = AD19 */ | 22 | #define SLOT_MPCI 0x0D /* IDSEL = AD19 */ |
26 | #define SLOT_NEC 0x0E /* IDSEL = AD18 */ | 23 | #define SLOT_NEC 0x0E /* IDSEL = AD18 */ |
27 | 24 | ||
28 | #define IRQ_ETHA IRQ_IXP4XX_GPIO4 | ||
29 | #define IRQ_ETHB IRQ_IXP4XX_GPIO5 | ||
30 | #define IRQ_NEC IRQ_IXP4XX_GPIO3 | ||
31 | #define IRQ_MPCI IRQ_IXP4XX_GPIO12 | ||
32 | |||
33 | /* GPIO lines */ | 25 | /* GPIO lines */ |
34 | #define GPIO_SCL 0 | 26 | #define GPIO_SCL 0 |
35 | #define GPIO_SDA 1 | 27 | #define GPIO_SDA 1 |
36 | #define GPIO_STR 2 | 28 | #define GPIO_STR 2 |
29 | #define GPIO_IRQ_NEC 3 | ||
30 | #define GPIO_IRQ_ETHA 4 | ||
31 | #define GPIO_IRQ_ETHB 5 | ||
37 | #define GPIO_HSS0_DCD_N 6 | 32 | #define GPIO_HSS0_DCD_N 6 |
38 | #define GPIO_HSS1_DCD_N 7 | 33 | #define GPIO_HSS1_DCD_N 7 |
34 | #define GPIO_UART0_DCD 8 | ||
35 | #define GPIO_UART1_DCD 9 | ||
39 | #define GPIO_HSS0_CTS_N 10 | 36 | #define GPIO_HSS0_CTS_N 10 |
40 | #define GPIO_HSS1_CTS_N 11 | 37 | #define GPIO_HSS1_CTS_N 11 |
38 | #define GPIO_IRQ_MPCI 12 | ||
41 | #define GPIO_HSS1_RTS_N 13 | 39 | #define GPIO_HSS1_RTS_N 13 |
42 | #define GPIO_HSS0_RTS_N 14 | 40 | #define GPIO_HSS0_RTS_N 14 |
41 | /* GPIO15 is not connected */ | ||
43 | 42 | ||
44 | /* Control outputs from 74HC4094 */ | 43 | /* Control outputs from 74HC4094 */ |
45 | #define CONTROL_HSS0_CLK_INT 0 | 44 | #define CONTROL_HSS0_CLK_INT 0 |
@@ -152,7 +151,7 @@ static int hss_set_clock(int port, unsigned int clock_type) | |||
152 | 151 | ||
153 | static irqreturn_t hss_dcd_irq(int irq, void *pdev) | 152 | static irqreturn_t hss_dcd_irq(int irq, void *pdev) |
154 | { | 153 | { |
155 | int i, port = (irq == gpio_irq(GPIO_HSS1_DCD_N)); | 154 | int i, port = (irq == IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N)); |
156 | gpio_line_get(port ? GPIO_HSS1_DCD_N : GPIO_HSS0_DCD_N, &i); | 155 | gpio_line_get(port ? GPIO_HSS1_DCD_N : GPIO_HSS0_DCD_N, &i); |
157 | set_carrier_cb_tab[port](pdev, !i); | 156 | set_carrier_cb_tab[port](pdev, !i); |
158 | return IRQ_HANDLED; | 157 | return IRQ_HANDLED; |
@@ -165,9 +164,9 @@ static int hss_open(int port, void *pdev, | |||
165 | int i, irq; | 164 | int i, irq; |
166 | 165 | ||
167 | if (!port) | 166 | if (!port) |
168 | irq = gpio_irq(GPIO_HSS0_DCD_N); | 167 | irq = IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N); |
169 | else | 168 | else |
170 | irq = gpio_irq(GPIO_HSS1_DCD_N); | 169 | irq = IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N); |
171 | 170 | ||
172 | gpio_line_get(port ? GPIO_HSS1_DCD_N : GPIO_HSS0_DCD_N, &i); | 171 | gpio_line_get(port ? GPIO_HSS1_DCD_N : GPIO_HSS0_DCD_N, &i); |
173 | set_carrier_cb(pdev, !i); | 172 | set_carrier_cb(pdev, !i); |
@@ -188,8 +187,8 @@ static int hss_open(int port, void *pdev, | |||
188 | 187 | ||
189 | static void hss_close(int port, void *pdev) | 188 | static void hss_close(int port, void *pdev) |
190 | { | 189 | { |
191 | free_irq(port ? gpio_irq(GPIO_HSS1_DCD_N) : gpio_irq(GPIO_HSS0_DCD_N), | 190 | free_irq(port ? IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N) : |
192 | pdev); | 191 | IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N), pdev); |
193 | set_carrier_cb_tab[!!port] = NULL; /* catch bugs */ | 192 | set_carrier_cb_tab[!!port] = NULL; /* catch bugs */ |
194 | 193 | ||
195 | set_control(port ? CONTROL_HSS1_DTR_N : CONTROL_HSS0_DTR_N, 1); | 194 | set_control(port ? CONTROL_HSS1_DTR_N : CONTROL_HSS0_DTR_N, 1); |
@@ -421,8 +420,8 @@ static void __init gmlr_init(void) | |||
421 | gpio_line_config(GPIO_HSS1_RTS_N, IXP4XX_GPIO_OUT); | 420 | gpio_line_config(GPIO_HSS1_RTS_N, IXP4XX_GPIO_OUT); |
422 | gpio_line_config(GPIO_HSS0_DCD_N, IXP4XX_GPIO_IN); | 421 | gpio_line_config(GPIO_HSS0_DCD_N, IXP4XX_GPIO_IN); |
423 | gpio_line_config(GPIO_HSS1_DCD_N, IXP4XX_GPIO_IN); | 422 | gpio_line_config(GPIO_HSS1_DCD_N, IXP4XX_GPIO_IN); |
424 | set_irq_type(gpio_irq(GPIO_HSS0_DCD_N), IRQ_TYPE_EDGE_BOTH); | 423 | set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N), IRQ_TYPE_EDGE_BOTH); |
425 | set_irq_type(gpio_irq(GPIO_HSS1_DCD_N), IRQ_TYPE_EDGE_BOTH); | 424 | set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N), IRQ_TYPE_EDGE_BOTH); |
426 | 425 | ||
427 | set_control(CONTROL_HSS0_DTR_N, 1); | 426 | set_control(CONTROL_HSS0_DTR_N, 1); |
428 | set_control(CONTROL_HSS1_DTR_N, 1); | 427 | set_control(CONTROL_HSS1_DTR_N, 1); |
@@ -442,10 +441,10 @@ static void __init gmlr_init(void) | |||
442 | #ifdef CONFIG_PCI | 441 | #ifdef CONFIG_PCI |
443 | static void __init gmlr_pci_preinit(void) | 442 | static void __init gmlr_pci_preinit(void) |
444 | { | 443 | { |
445 | set_irq_type(IRQ_ETHA, IRQ_TYPE_LEVEL_LOW); | 444 | set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHA), IRQ_TYPE_LEVEL_LOW); |
446 | set_irq_type(IRQ_ETHB, IRQ_TYPE_LEVEL_LOW); | 445 | set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHB), IRQ_TYPE_LEVEL_LOW); |
447 | set_irq_type(IRQ_NEC, IRQ_TYPE_LEVEL_LOW); | 446 | set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_NEC), IRQ_TYPE_LEVEL_LOW); |
448 | set_irq_type(IRQ_MPCI, IRQ_TYPE_LEVEL_LOW); | 447 | set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_MPCI), IRQ_TYPE_LEVEL_LOW); |
449 | ixp4xx_pci_preinit(); | 448 | ixp4xx_pci_preinit(); |
450 | } | 449 | } |
451 | 450 | ||
@@ -466,10 +465,10 @@ static void __init gmlr_pci_postinit(void) | |||
466 | static int __init gmlr_map_irq(struct pci_dev *dev, u8 slot, u8 pin) | 465 | static int __init gmlr_map_irq(struct pci_dev *dev, u8 slot, u8 pin) |
467 | { | 466 | { |
468 | switch(slot) { | 467 | switch(slot) { |
469 | case SLOT_ETHA: return IRQ_ETHA; | 468 | case SLOT_ETHA: return IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHA); |
470 | case SLOT_ETHB: return IRQ_ETHB; | 469 | case SLOT_ETHB: return IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHB); |
471 | case SLOT_NEC: return IRQ_NEC; | 470 | case SLOT_NEC: return IXP4XX_GPIO_IRQ(GPIO_IRQ_NEC); |
472 | default: return IRQ_MPCI; | 471 | default: return IXP4XX_GPIO_IRQ(GPIO_IRQ_MPCI); |
473 | } | 472 | } |
474 | } | 473 | } |
475 | 474 | ||
diff --git a/arch/arm/mach-ixp4xx/gtwx5715-pci.c b/arch/arm/mach-ixp4xx/gtwx5715-pci.c index 7b8a2c323840..25d2c333c204 100644 --- a/arch/arm/mach-ixp4xx/gtwx5715-pci.c +++ b/arch/arm/mach-ixp4xx/gtwx5715-pci.c | |||
@@ -26,14 +26,16 @@ | |||
26 | #include <linux/init.h> | 26 | #include <linux/init.h> |
27 | #include <linux/delay.h> | 27 | #include <linux/delay.h> |
28 | #include <linux/irq.h> | 28 | #include <linux/irq.h> |
29 | |||
30 | #include <asm/mach-types.h> | 29 | #include <asm/mach-types.h> |
31 | #include <mach/hardware.h> | 30 | #include <mach/hardware.h> |
32 | #include <mach/gtwx5715.h> | ||
33 | #include <asm/mach/pci.h> | 31 | #include <asm/mach/pci.h> |
34 | 32 | ||
33 | #define SLOT0_DEVID 0 | ||
34 | #define SLOT1_DEVID 1 | ||
35 | #define INTA 10 /* slot 1 has INTA and INTB crossed */ | ||
36 | #define INTB 11 | ||
37 | |||
35 | /* | 38 | /* |
36 | * The exact GPIO pins and IRQs are defined in arch-ixp4xx/gtwx5715.h | ||
37 | * Slot 0 isn't actually populated with a card connector but | 39 | * Slot 0 isn't actually populated with a card connector but |
38 | * we initialize it anyway in case a future version has the | 40 | * we initialize it anyway in case a future version has the |
39 | * slot populated or someone with good soldering skills has | 41 | * slot populated or someone with good soldering skills has |
@@ -41,32 +43,26 @@ | |||
41 | */ | 43 | */ |
42 | void __init gtwx5715_pci_preinit(void) | 44 | void __init gtwx5715_pci_preinit(void) |
43 | { | 45 | { |
44 | set_irq_type(GTWX5715_PCI_SLOT0_INTA_IRQ, IRQ_TYPE_LEVEL_LOW); | 46 | set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); |
45 | set_irq_type(GTWX5715_PCI_SLOT0_INTB_IRQ, IRQ_TYPE_LEVEL_LOW); | 47 | set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); |
46 | set_irq_type(GTWX5715_PCI_SLOT1_INTA_IRQ, IRQ_TYPE_LEVEL_LOW); | ||
47 | set_irq_type(GTWX5715_PCI_SLOT1_INTB_IRQ, IRQ_TYPE_LEVEL_LOW); | ||
48 | |||
49 | ixp4xx_pci_preinit(); | 48 | ixp4xx_pci_preinit(); |
50 | } | 49 | } |
51 | 50 | ||
52 | 51 | ||
53 | static int __init gtwx5715_map_irq(struct pci_dev *dev, u8 slot, u8 pin) | 52 | static int __init gtwx5715_map_irq(struct pci_dev *dev, u8 slot, u8 pin) |
54 | { | 53 | { |
55 | int rc; | 54 | int rc = -1; |
56 | static int gtwx5715_irqmap | ||
57 | [GTWX5715_PCI_SLOT_COUNT] | ||
58 | [GTWX5715_PCI_INT_PIN_COUNT] = { | ||
59 | {GTWX5715_PCI_SLOT0_INTA_IRQ, GTWX5715_PCI_SLOT0_INTB_IRQ}, | ||
60 | {GTWX5715_PCI_SLOT1_INTA_IRQ, GTWX5715_PCI_SLOT1_INTB_IRQ}, | ||
61 | }; | ||
62 | 55 | ||
63 | if (slot >= GTWX5715_PCI_SLOT_COUNT || | 56 | if ((slot == SLOT0_DEVID && pin == 1) || |
64 | pin >= GTWX5715_PCI_INT_PIN_COUNT) rc = -1; | 57 | (slot == SLOT1_DEVID && pin == 2)) |
65 | else | 58 | rc = IXP4XX_GPIO_IRQ(INTA); |
66 | rc = gtwx5715_irqmap[slot][pin-1]; | 59 | else if ((slot == SLOT0_DEVID && pin == 2) || |
60 | (slot == SLOT1_DEVID && pin == 1)) | ||
61 | rc = IXP4XX_GPIO_IRQ(INTB); | ||
67 | 62 | ||
68 | printk("%s: Mapped slot %d pin %d to IRQ %d\n", __func__, slot, pin, rc); | 63 | printk(KERN_INFO "%s: Mapped slot %d pin %d to IRQ %d\n", |
69 | return(rc); | 64 | __func__, slot, pin, rc); |
65 | return rc; | ||
70 | } | 66 | } |
71 | 67 | ||
72 | struct hw_pci gtwx5715_pci __initdata = { | 68 | struct hw_pci gtwx5715_pci __initdata = { |
@@ -81,9 +77,7 @@ struct hw_pci gtwx5715_pci __initdata = { | |||
81 | int __init gtwx5715_pci_init(void) | 77 | int __init gtwx5715_pci_init(void) |
82 | { | 78 | { |
83 | if (machine_is_gtwx5715()) | 79 | if (machine_is_gtwx5715()) |
84 | { | ||
85 | pci_common_init(>wx5715_pci); | 80 | pci_common_init(>wx5715_pci); |
86 | } | ||
87 | 81 | ||
88 | return 0; | 82 | return 0; |
89 | } | 83 | } |
diff --git a/arch/arm/mach-ixp4xx/gtwx5715-setup.c b/arch/arm/mach-ixp4xx/gtwx5715-setup.c index 25c21d6665ec..0bc7185cb6f7 100644 --- a/arch/arm/mach-ixp4xx/gtwx5715-setup.c +++ b/arch/arm/mach-ixp4xx/gtwx5715-setup.c | |||
@@ -28,7 +28,6 @@ | |||
28 | #include <linux/tty.h> | 28 | #include <linux/tty.h> |
29 | #include <linux/serial_8250.h> | 29 | #include <linux/serial_8250.h> |
30 | #include <linux/slab.h> | 30 | #include <linux/slab.h> |
31 | |||
32 | #include <asm/types.h> | 31 | #include <asm/types.h> |
33 | #include <asm/setup.h> | 32 | #include <asm/setup.h> |
34 | #include <asm/memory.h> | 33 | #include <asm/memory.h> |
@@ -37,7 +36,34 @@ | |||
37 | #include <asm/mach-types.h> | 36 | #include <asm/mach-types.h> |
38 | #include <asm/mach/arch.h> | 37 | #include <asm/mach/arch.h> |
39 | #include <asm/mach/flash.h> | 38 | #include <asm/mach/flash.h> |
40 | #include <mach/gtwx5715.h> | 39 | |
40 | /* GPIO 5,6,7 and 12 are hard wired to the Kendin KS8995M Switch | ||
41 | and operate as an SPI type interface. The details of the interface | ||
42 | are available on Kendin/Micrel's web site. */ | ||
43 | |||
44 | #define GTWX5715_KSSPI_SELECT 5 | ||
45 | #define GTWX5715_KSSPI_TXD 6 | ||
46 | #define GTWX5715_KSSPI_CLOCK 7 | ||
47 | #define GTWX5715_KSSPI_RXD 12 | ||
48 | |||
49 | /* The "reset" button is wired to GPIO 3. | ||
50 | The GPIO is brought "low" when the button is pushed. */ | ||
51 | |||
52 | #define GTWX5715_BUTTON_GPIO 3 | ||
53 | |||
54 | /* Board Label Front Label | ||
55 | LED1 Power | ||
56 | LED2 Wireless-G | ||
57 | LED3 not populated but could be | ||
58 | LED4 Internet | ||
59 | LED5 - LED8 Controlled by KS8995M Switch | ||
60 | LED9 DMZ */ | ||
61 | |||
62 | #define GTWX5715_LED1_GPIO 2 | ||
63 | #define GTWX5715_LED2_GPIO 9 | ||
64 | #define GTWX5715_LED3_GPIO 8 | ||
65 | #define GTWX5715_LED4_GPIO 1 | ||
66 | #define GTWX5715_LED9_GPIO 4 | ||
41 | 67 | ||
42 | /* | 68 | /* |
43 | * Xscale UART registers are 32 bits wide with only the least | 69 | * Xscale UART registers are 32 bits wide with only the least |
diff --git a/arch/arm/mach-ixp4xx/include/mach/avila.h b/arch/arm/mach-ixp4xx/include/mach/avila.h deleted file mode 100644 index 1640cb61972b..000000000000 --- a/arch/arm/mach-ixp4xx/include/mach/avila.h +++ /dev/null | |||
@@ -1,39 +0,0 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-ixp4xx/include/mach/avila.h | ||
3 | * | ||
4 | * Gateworks Avila platform specific definitions | ||
5 | * | ||
6 | * Author: Michael-Luke Jones <mlj28@cam.ac.uk> | ||
7 | * | ||
8 | * Based on ixdp425.h | ||
9 | * Author: Deepak Saxena <dsaxena@plexity.net> | ||
10 | * | ||
11 | * Copyright 2004 (c) MontaVista, Software, Inc. | ||
12 | * | ||
13 | * This file is licensed under the terms of the GNU General Public | ||
14 | * License version 2. This program is licensed "as is" without any | ||
15 | * warranty of any kind, whether express or implied. | ||
16 | */ | ||
17 | |||
18 | #ifndef __ASM_ARCH_HARDWARE_H__ | ||
19 | #error "Do not include this directly, instead #include <mach/hardware.h>" | ||
20 | #endif | ||
21 | |||
22 | #define AVILA_SDA_PIN 7 | ||
23 | #define AVILA_SCL_PIN 6 | ||
24 | |||
25 | /* | ||
26 | * AVILA PCI IRQs | ||
27 | */ | ||
28 | #define AVILA_PCI_MAX_DEV 4 | ||
29 | #define LOFT_PCI_MAX_DEV 6 | ||
30 | #define AVILA_PCI_IRQ_LINES 4 | ||
31 | |||
32 | |||
33 | /* PCI controller GPIO to IRQ pin mappings */ | ||
34 | #define AVILA_PCI_INTA_PIN 11 | ||
35 | #define AVILA_PCI_INTB_PIN 10 | ||
36 | #define AVILA_PCI_INTC_PIN 9 | ||
37 | #define AVILA_PCI_INTD_PIN 8 | ||
38 | |||
39 | |||
diff --git a/arch/arm/mach-ixp4xx/include/mach/coyote.h b/arch/arm/mach-ixp4xx/include/mach/coyote.h deleted file mode 100644 index 717ac6d16f55..000000000000 --- a/arch/arm/mach-ixp4xx/include/mach/coyote.h +++ /dev/null | |||
@@ -1,33 +0,0 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-ixp4xx/include/mach/coyote.h | ||
3 | * | ||
4 | * ADI Engineering platform specific definitions | ||
5 | * | ||
6 | * Author: Deepak Saxena <dsaxena@plexity.net> | ||
7 | * | ||
8 | * Copyright 2004 (c) MontaVista, Software, Inc. | ||
9 | * | ||
10 | * This file is licensed under the terms of the GNU General Public | ||
11 | * License version 2. This program is licensed "as is" without any | ||
12 | * warranty of any kind, whether express or implied. | ||
13 | */ | ||
14 | |||
15 | #ifndef __ASM_ARCH_HARDWARE_H__ | ||
16 | #error "Do not include this directly, instead #include <mach/hardware.h>" | ||
17 | #endif | ||
18 | |||
19 | /* PCI controller GPIO to IRQ pin mappings */ | ||
20 | #define COYOTE_PCI_SLOT0_PIN 6 | ||
21 | #define COYOTE_PCI_SLOT1_PIN 11 | ||
22 | |||
23 | #define COYOTE_PCI_SLOT0_DEVID 14 | ||
24 | #define COYOTE_PCI_SLOT1_DEVID 15 | ||
25 | |||
26 | #define COYOTE_IDE_BASE_PHYS IXP4XX_EXP_BUS_BASE(3) | ||
27 | #define COYOTE_IDE_BASE_VIRT 0xFFFE1000 | ||
28 | #define COYOTE_IDE_REGION_SIZE 0x1000 | ||
29 | |||
30 | #define COYOTE_IDE_DATA_PORT 0xFFFE10E0 | ||
31 | #define COYOTE_IDE_CTRL_PORT 0xFFFE10FC | ||
32 | #define COYOTE_IDE_ERROR_PORT 0xFFFE10E2 | ||
33 | |||
diff --git a/arch/arm/mach-ixp4xx/include/mach/dsmg600.h b/arch/arm/mach-ixp4xx/include/mach/dsmg600.h deleted file mode 100644 index dc087a34a268..000000000000 --- a/arch/arm/mach-ixp4xx/include/mach/dsmg600.h +++ /dev/null | |||
@@ -1,52 +0,0 @@ | |||
1 | /* | ||
2 | * DSM-G600 platform specific definitions | ||
3 | * | ||
4 | * Copyright (C) 2006 Tower Technologies | ||
5 | * Author: Alessandro Zummo <a.zummo@towertech.it> | ||
6 | * | ||
7 | * based on ixdp425.h: | ||
8 | * Copyright 2004 (C) MontaVista, Software, Inc. | ||
9 | * | ||
10 | * This file is licensed under the terms of the GNU General Public | ||
11 | * License version 2. This program is licensed "as is" without any | ||
12 | * warranty of any kind, whether express or implied. | ||
13 | */ | ||
14 | |||
15 | #ifndef __ASM_ARCH_HARDWARE_H__ | ||
16 | #error "Do not include this directly, instead #include <mach/hardware.h>" | ||
17 | #endif | ||
18 | |||
19 | #define DSMG600_SDA_PIN 5 | ||
20 | #define DSMG600_SCL_PIN 4 | ||
21 | |||
22 | /* | ||
23 | * DSMG600 PCI IRQs | ||
24 | */ | ||
25 | #define DSMG600_PCI_MAX_DEV 4 | ||
26 | #define DSMG600_PCI_IRQ_LINES 3 | ||
27 | |||
28 | |||
29 | /* PCI controller GPIO to IRQ pin mappings */ | ||
30 | #define DSMG600_PCI_INTA_PIN 11 | ||
31 | #define DSMG600_PCI_INTB_PIN 10 | ||
32 | #define DSMG600_PCI_INTC_PIN 9 | ||
33 | #define DSMG600_PCI_INTD_PIN 8 | ||
34 | #define DSMG600_PCI_INTE_PIN 7 | ||
35 | #define DSMG600_PCI_INTF_PIN 6 | ||
36 | |||
37 | /* DSM-G600 Timer Setting */ | ||
38 | #define DSMG600_FREQ 66000000 | ||
39 | |||
40 | /* Buttons */ | ||
41 | |||
42 | #define DSMG600_PB_GPIO 15 /* power button */ | ||
43 | #define DSMG600_RB_GPIO 3 /* reset button */ | ||
44 | |||
45 | /* Power control */ | ||
46 | |||
47 | #define DSMG600_PO_GPIO 2 /* power off */ | ||
48 | |||
49 | /* LEDs */ | ||
50 | |||
51 | #define DSMG600_LED_PWR_GPIO 0 | ||
52 | #define DSMG600_LED_WLAN_GPIO 14 | ||
diff --git a/arch/arm/mach-ixp4xx/include/mach/fsg.h b/arch/arm/mach-ixp4xx/include/mach/fsg.h deleted file mode 100644 index 1f02b7e22a13..000000000000 --- a/arch/arm/mach-ixp4xx/include/mach/fsg.h +++ /dev/null | |||
@@ -1,50 +0,0 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-ixp4xx/include/mach/fsg.h | ||
3 | * | ||
4 | * Freecom FSG-3 platform specific definitions | ||
5 | * | ||
6 | * Author: Rod Whitby <rod@whitby.id.au> | ||
7 | * Author: Tomasz Chmielewski <mangoo@wpkg.org> | ||
8 | * Maintainers: http://www.nslu2-linux.org | ||
9 | * | ||
10 | * Based on coyote.h by | ||
11 | * Copyright 2004 (c) MontaVista, Software, Inc. | ||
12 | * | ||
13 | * This file is licensed under the terms of the GNU General Public | ||
14 | * License version 2. This program is licensed "as is" without any | ||
15 | * warranty of any kind, whether express or implied. | ||
16 | */ | ||
17 | |||
18 | #ifndef __ASM_ARCH_HARDWARE_H__ | ||
19 | #error "Do not include this directly, instead #include <mach/hardware.h>" | ||
20 | #endif | ||
21 | |||
22 | #define FSG_SDA_PIN 12 | ||
23 | #define FSG_SCL_PIN 13 | ||
24 | |||
25 | /* | ||
26 | * FSG PCI IRQs | ||
27 | */ | ||
28 | #define FSG_PCI_MAX_DEV 3 | ||
29 | #define FSG_PCI_IRQ_LINES 3 | ||
30 | |||
31 | |||
32 | /* PCI controller GPIO to IRQ pin mappings */ | ||
33 | #define FSG_PCI_INTA_PIN 6 | ||
34 | #define FSG_PCI_INTB_PIN 7 | ||
35 | #define FSG_PCI_INTC_PIN 5 | ||
36 | |||
37 | /* Buttons */ | ||
38 | |||
39 | #define FSG_SB_GPIO 4 /* sync button */ | ||
40 | #define FSG_RB_GPIO 9 /* reset button */ | ||
41 | #define FSG_UB_GPIO 10 /* usb button */ | ||
42 | |||
43 | /* LEDs */ | ||
44 | |||
45 | #define FSG_LED_WLAN_BIT 0 | ||
46 | #define FSG_LED_WAN_BIT 1 | ||
47 | #define FSG_LED_SATA_BIT 2 | ||
48 | #define FSG_LED_USB_BIT 4 | ||
49 | #define FSG_LED_RING_BIT 5 | ||
50 | #define FSG_LED_SYNC_BIT 7 | ||
diff --git a/arch/arm/mach-ixp4xx/include/mach/gpio.h b/arch/arm/mach-ixp4xx/include/mach/gpio.h index cd5aec26c072..a5f87ded2f28 100644 --- a/arch/arm/mach-ixp4xx/include/mach/gpio.h +++ b/arch/arm/mach-ixp4xx/include/mach/gpio.h | |||
@@ -70,7 +70,7 @@ static inline void gpio_set_value(unsigned gpio, int value) | |||
70 | #include <asm-generic/gpio.h> /* cansleep wrappers */ | 70 | #include <asm-generic/gpio.h> /* cansleep wrappers */ |
71 | 71 | ||
72 | extern int gpio_to_irq(int gpio); | 72 | extern int gpio_to_irq(int gpio); |
73 | extern int irq_to_gpio(int gpio); | 73 | extern int irq_to_gpio(unsigned int irq); |
74 | 74 | ||
75 | #endif | 75 | #endif |
76 | 76 | ||
diff --git a/arch/arm/mach-ixp4xx/include/mach/gtwx5715.h b/arch/arm/mach-ixp4xx/include/mach/gtwx5715.h deleted file mode 100644 index 5d5e201cac7e..000000000000 --- a/arch/arm/mach-ixp4xx/include/mach/gtwx5715.h +++ /dev/null | |||
@@ -1,116 +0,0 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-ixp4xx/include/mach/gtwx5715.h | ||
3 | * | ||
4 | * Gemtek GTWX5715 Gateway (Linksys WRV54G) | ||
5 | * | ||
6 | * Copyright 2004 (c) George T. Joseph | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or | ||
9 | * modify it under the terms of the GNU General Public License | ||
10 | * as published by the Free Software Foundation; either version 2 | ||
11 | * of the License, or (at your option) any later version. | ||
12 | * | ||
13 | * This program is distributed in the hope that it will be useful, | ||
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
16 | * GNU General Public License for more details. | ||
17 | * | ||
18 | * You should have received a copy of the GNU General Public License | ||
19 | * along with this program; if not, write to the Free Software | ||
20 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | ||
21 | */ | ||
22 | |||
23 | #ifndef __ASM_ARCH_HARDWARE_H__ | ||
24 | #error "Do not include this directly, instead #include <mach/hardware.h>" | ||
25 | #endif | ||
26 | #include "irqs.h" | ||
27 | |||
28 | #define GTWX5715_GPIO0 0 | ||
29 | #define GTWX5715_GPIO1 1 | ||
30 | #define GTWX5715_GPIO2 2 | ||
31 | #define GTWX5715_GPIO3 3 | ||
32 | #define GTWX5715_GPIO4 4 | ||
33 | #define GTWX5715_GPIO5 5 | ||
34 | #define GTWX5715_GPIO6 6 | ||
35 | #define GTWX5715_GPIO7 7 | ||
36 | #define GTWX5715_GPIO8 8 | ||
37 | #define GTWX5715_GPIO9 9 | ||
38 | #define GTWX5715_GPIO10 10 | ||
39 | #define GTWX5715_GPIO11 11 | ||
40 | #define GTWX5715_GPIO12 12 | ||
41 | #define GTWX5715_GPIO13 13 | ||
42 | #define GTWX5715_GPIO14 14 | ||
43 | |||
44 | #define GTWX5715_GPIO0_IRQ IRQ_IXP4XX_GPIO0 | ||
45 | #define GTWX5715_GPIO1_IRQ IRQ_IXP4XX_GPIO1 | ||
46 | #define GTWX5715_GPIO2_IRQ IRQ_IXP4XX_GPIO2 | ||
47 | #define GTWX5715_GPIO3_IRQ IRQ_IXP4XX_GPIO3 | ||
48 | #define GTWX5715_GPIO4_IRQ IRQ_IXP4XX_GPIO4 | ||
49 | #define GTWX5715_GPIO5_IRQ IRQ_IXP4XX_GPIO5 | ||
50 | #define GTWX5715_GPIO6_IRQ IRQ_IXP4XX_GPIO6 | ||
51 | #define GTWX5715_GPIO7_IRQ IRQ_IXP4XX_GPIO7 | ||
52 | #define GTWX5715_GPIO8_IRQ IRQ_IXP4XX_GPIO8 | ||
53 | #define GTWX5715_GPIO9_IRQ IRQ_IXP4XX_GPIO9 | ||
54 | #define GTWX5715_GPIO10_IRQ IRQ_IXP4XX_GPIO10 | ||
55 | #define GTWX5715_GPIO11_IRQ IRQ_IXP4XX_GPIO11 | ||
56 | #define GTWX5715_GPIO12_IRQ IRQ_IXP4XX_GPIO12 | ||
57 | #define GTWX5715_GPIO13_IRQ IRQ_IXP4XX_SW_INT1 | ||
58 | #define GTWX5715_GPIO14_IRQ IRQ_IXP4XX_SW_INT2 | ||
59 | |||
60 | /* PCI controller GPIO to IRQ pin mappings | ||
61 | |||
62 | INTA INTB | ||
63 | SLOT 0 10 11 | ||
64 | SLOT 1 11 10 | ||
65 | |||
66 | */ | ||
67 | |||
68 | #define GTWX5715_PCI_SLOT0_DEVID 0 | ||
69 | #define GTWX5715_PCI_SLOT0_INTA_GPIO GTWX5715_GPIO10 | ||
70 | #define GTWX5715_PCI_SLOT0_INTB_GPIO GTWX5715_GPIO11 | ||
71 | #define GTWX5715_PCI_SLOT0_INTA_IRQ GTWX5715_GPIO10_IRQ | ||
72 | #define GTWX5715_PCI_SLOT0_INTB_IRQ GTWX5715_GPIO11_IRQ | ||
73 | |||
74 | #define GTWX5715_PCI_SLOT1_DEVID 1 | ||
75 | #define GTWX5715_PCI_SLOT1_INTA_GPIO GTWX5715_GPIO11 | ||
76 | #define GTWX5715_PCI_SLOT1_INTB_GPIO GTWX5715_GPIO10 | ||
77 | #define GTWX5715_PCI_SLOT1_INTA_IRQ GTWX5715_GPIO11_IRQ | ||
78 | #define GTWX5715_PCI_SLOT1_INTB_IRQ GTWX5715_GPIO10_IRQ | ||
79 | |||
80 | #define GTWX5715_PCI_SLOT_COUNT 2 | ||
81 | #define GTWX5715_PCI_INT_PIN_COUNT 2 | ||
82 | |||
83 | /* | ||
84 | * GPIO 5,6,7 and12 are hard wired to the Kendin KS8995M Switch | ||
85 | * and operate as an SPI type interface. The details of the interface | ||
86 | * are available on Kendin/Micrel's web site. | ||
87 | */ | ||
88 | |||
89 | #define GTWX5715_KSSPI_SELECT GTWX5715_GPIO5 | ||
90 | #define GTWX5715_KSSPI_TXD GTWX5715_GPIO6 | ||
91 | #define GTWX5715_KSSPI_CLOCK GTWX5715_GPIO7 | ||
92 | #define GTWX5715_KSSPI_RXD GTWX5715_GPIO12 | ||
93 | |||
94 | /* | ||
95 | * The "reset" button is wired to GPIO 3. | ||
96 | * The GPIO is brought "low" when the button is pushed. | ||
97 | */ | ||
98 | |||
99 | #define GTWX5715_BUTTON_GPIO GTWX5715_GPIO3 | ||
100 | #define GTWX5715_BUTTON_IRQ GTWX5715_GPIO3_IRQ | ||
101 | |||
102 | /* | ||
103 | * Board Label Front Label | ||
104 | * LED1 Power | ||
105 | * LED2 Wireless-G | ||
106 | * LED3 not populated but could be | ||
107 | * LED4 Internet | ||
108 | * LED5 - LED8 Controlled by KS8995M Switch | ||
109 | * LED9 DMZ | ||
110 | */ | ||
111 | |||
112 | #define GTWX5715_LED1_GPIO GTWX5715_GPIO2 | ||
113 | #define GTWX5715_LED2_GPIO GTWX5715_GPIO9 | ||
114 | #define GTWX5715_LED3_GPIO GTWX5715_GPIO8 | ||
115 | #define GTWX5715_LED4_GPIO GTWX5715_GPIO1 | ||
116 | #define GTWX5715_LED9_GPIO GTWX5715_GPIO4 | ||
diff --git a/arch/arm/mach-ixp4xx/include/mach/hardware.h b/arch/arm/mach-ixp4xx/include/mach/hardware.h index f58a43a23966..f9d1c43e4a54 100644 --- a/arch/arm/mach-ixp4xx/include/mach/hardware.h +++ b/arch/arm/mach-ixp4xx/include/mach/hardware.h | |||
@@ -18,7 +18,13 @@ | |||
18 | #define __ASM_ARCH_HARDWARE_H__ | 18 | #define __ASM_ARCH_HARDWARE_H__ |
19 | 19 | ||
20 | #define PCIBIOS_MIN_IO 0x00001000 | 20 | #define PCIBIOS_MIN_IO 0x00001000 |
21 | #define PCIBIOS_MIN_MEM (cpu_is_ixp43x() ? 0x40000000 : 0x48000000) | 21 | #ifdef CONFIG_IXP4XX_INDIRECT_PCI |
22 | #define PCIBIOS_MIN_MEM 0x10000000 /* 1 GB of indirect PCI MMIO space */ | ||
23 | #define PCIBIOS_MAX_MEM 0x4FFFFFFF | ||
24 | #else | ||
25 | #define PCIBIOS_MIN_MEM 0x48000000 /* 64 MB of PCI MMIO space */ | ||
26 | #define PCIBIOS_MAX_MEM 0x4BFFFFFF | ||
27 | #endif | ||
22 | 28 | ||
23 | /* | 29 | /* |
24 | * We override the standard dma-mask routines for bouncing. | 30 | * We override the standard dma-mask routines for bouncing. |
@@ -37,14 +43,4 @@ | |||
37 | /* Platform helper functions and definitions */ | 43 | /* Platform helper functions and definitions */ |
38 | #include "platform.h" | 44 | #include "platform.h" |
39 | 45 | ||
40 | /* Platform specific details */ | ||
41 | #include "ixdp425.h" | ||
42 | #include "avila.h" | ||
43 | #include "coyote.h" | ||
44 | #include "prpmc1100.h" | ||
45 | #include "nslu2.h" | ||
46 | #include "nas100d.h" | ||
47 | #include "dsmg600.h" | ||
48 | #include "fsg.h" | ||
49 | |||
50 | #endif /* _ASM_ARCH_HARDWARE_H */ | 46 | #endif /* _ASM_ARCH_HARDWARE_H */ |
diff --git a/arch/arm/mach-ixp4xx/include/mach/io.h b/arch/arm/mach-ixp4xx/include/mach/io.h index 8a947d42a6f1..6ea7e2fb2701 100644 --- a/arch/arm/mach-ixp4xx/include/mach/io.h +++ b/arch/arm/mach-ixp4xx/include/mach/io.h | |||
@@ -26,22 +26,20 @@ extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data); | |||
26 | /* | 26 | /* |
27 | * IXP4xx provides two methods of accessing PCI memory space: | 27 | * IXP4xx provides two methods of accessing PCI memory space: |
28 | * | 28 | * |
29 | * 1) A direct mapped window from 0x48000000 to 0x4bffffff (64MB). | 29 | * 1) A direct mapped window from 0x48000000 to 0x4BFFFFFF (64MB). |
30 | * To access PCI via this space, we simply ioremap() the BAR | 30 | * To access PCI via this space, we simply ioremap() the BAR |
31 | * into the kernel and we can use the standard read[bwl]/write[bwl] | 31 | * into the kernel and we can use the standard read[bwl]/write[bwl] |
32 | * macros. This is the preffered method due to speed but it | 32 | * macros. This is the preffered method due to speed but it |
33 | * limits the system to just 64MB of PCI memory. This can be | 33 | * limits the system to just 64MB of PCI memory. This can be |
34 | * problamatic if using video cards and other memory-heavy | 34 | * problematic if using video cards and other memory-heavy targets. |
35 | * targets. | ||
36 | * | ||
37 | * 2) If > 64MB of memory space is required, the IXP4xx can be configured | ||
38 | * to use indirect registers to access PCI (as we do below for I/O | ||
39 | * transactions). This allows for up to 128MB (0x48000000 to 0x4fffffff) | ||
40 | * of memory on the bus. The disadvantage of this is that every | ||
41 | * PCI access requires three local register accesses plus a spinlock, | ||
42 | * but in some cases the performance hit is acceptable. In addition, | ||
43 | * you cannot mmap() PCI devices in this case. | ||
44 | * | 35 | * |
36 | * 2) If > 64MB of memory space is required, the IXP4xx can use indirect | ||
37 | * registers to access the whole 4 GB of PCI memory space (as we do below | ||
38 | * for I/O transactions). This allows currently for up to 1 GB (0x10000000 | ||
39 | * to 0x4FFFFFFF) of memory on the bus. The disadvantage of this is that | ||
40 | * every PCI access requires three local register accesses plus a spinlock, | ||
41 | * but in some cases the performance hit is acceptable. In addition, you | ||
42 | * cannot mmap() PCI devices in this case. | ||
45 | */ | 43 | */ |
46 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | 44 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI |
47 | 45 | ||
@@ -55,48 +53,52 @@ extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data); | |||
55 | * access registers. If something outside of PCI is ioremap'd, we | 53 | * access registers. If something outside of PCI is ioremap'd, we |
56 | * fallback to the default. | 54 | * fallback to the default. |
57 | */ | 55 | */ |
58 | static inline void __iomem * | 56 | |
59 | __ixp4xx_ioremap(unsigned long addr, size_t size, unsigned int mtype) | 57 | static inline int is_pci_memory(u32 addr) |
58 | { | ||
59 | return (addr >= PCIBIOS_MIN_MEM) && (addr <= 0x4FFFFFFF); | ||
60 | } | ||
61 | |||
62 | static inline void __iomem * __indirect_ioremap(unsigned long addr, size_t size, | ||
63 | unsigned int mtype) | ||
60 | { | 64 | { |
61 | if((addr < PCIBIOS_MIN_MEM) || (addr > 0x4fffffff)) | 65 | if (!is_pci_memory(addr)) |
62 | return __arm_ioremap(addr, size, mtype); | 66 | return __arm_ioremap(addr, size, mtype); |
63 | 67 | ||
64 | return (void __iomem *)addr; | 68 | return (void __iomem *)addr; |
65 | } | 69 | } |
66 | 70 | ||
67 | static inline void | 71 | static inline void __indirect_iounmap(void __iomem *addr) |
68 | __ixp4xx_iounmap(void __iomem *addr) | ||
69 | { | 72 | { |
70 | if ((__force u32)addr >= VMALLOC_START) | 73 | if (!is_pci_memory((__force u32)addr)) |
71 | __iounmap(addr); | 74 | __iounmap(addr); |
72 | } | 75 | } |
73 | 76 | ||
74 | #define __arch_ioremap(a, s, f) __ixp4xx_ioremap(a, s, f) | 77 | #define __arch_ioremap(a, s, f) __indirect_ioremap(a, s, f) |
75 | #define __arch_iounmap(a) __ixp4xx_iounmap(a) | 78 | #define __arch_iounmap(a) __indirect_iounmap(a) |
76 | 79 | ||
77 | #define writeb(v, p) __ixp4xx_writeb(v, p) | 80 | #define writeb(v, p) __indirect_writeb(v, p) |
78 | #define writew(v, p) __ixp4xx_writew(v, p) | 81 | #define writew(v, p) __indirect_writew(v, p) |
79 | #define writel(v, p) __ixp4xx_writel(v, p) | 82 | #define writel(v, p) __indirect_writel(v, p) |
80 | 83 | ||
81 | #define writesb(p, v, l) __ixp4xx_writesb(p, v, l) | 84 | #define writesb(p, v, l) __indirect_writesb(p, v, l) |
82 | #define writesw(p, v, l) __ixp4xx_writesw(p, v, l) | 85 | #define writesw(p, v, l) __indirect_writesw(p, v, l) |
83 | #define writesl(p, v, l) __ixp4xx_writesl(p, v, l) | 86 | #define writesl(p, v, l) __indirect_writesl(p, v, l) |
84 | |||
85 | #define readb(p) __ixp4xx_readb(p) | ||
86 | #define readw(p) __ixp4xx_readw(p) | ||
87 | #define readl(p) __ixp4xx_readl(p) | ||
88 | |||
89 | #define readsb(p, v, l) __ixp4xx_readsb(p, v, l) | ||
90 | #define readsw(p, v, l) __ixp4xx_readsw(p, v, l) | ||
91 | #define readsl(p, v, l) __ixp4xx_readsl(p, v, l) | ||
92 | 87 | ||
93 | static inline void | 88 | #define readb(p) __indirect_readb(p) |
94 | __ixp4xx_writeb(u8 value, volatile void __iomem *p) | 89 | #define readw(p) __indirect_readw(p) |
90 | #define readl(p) __indirect_readl(p) | ||
91 | |||
92 | #define readsb(p, v, l) __indirect_readsb(p, v, l) | ||
93 | #define readsw(p, v, l) __indirect_readsw(p, v, l) | ||
94 | #define readsl(p, v, l) __indirect_readsl(p, v, l) | ||
95 | |||
96 | static inline void __indirect_writeb(u8 value, volatile void __iomem *p) | ||
95 | { | 97 | { |
96 | u32 addr = (u32)p; | 98 | u32 addr = (u32)p; |
97 | u32 n, byte_enables, data; | 99 | u32 n, byte_enables, data; |
98 | 100 | ||
99 | if (addr >= VMALLOC_START) { | 101 | if (!is_pci_memory(addr)) { |
100 | __raw_writeb(value, addr); | 102 | __raw_writeb(value, addr); |
101 | return; | 103 | return; |
102 | } | 104 | } |
@@ -107,20 +109,19 @@ __ixp4xx_writeb(u8 value, volatile void __iomem *p) | |||
107 | ixp4xx_pci_write(addr, byte_enables | NP_CMD_MEMWRITE, data); | 109 | ixp4xx_pci_write(addr, byte_enables | NP_CMD_MEMWRITE, data); |
108 | } | 110 | } |
109 | 111 | ||
110 | static inline void | 112 | static inline void __indirect_writesb(volatile void __iomem *bus_addr, |
111 | __ixp4xx_writesb(volatile void __iomem *bus_addr, const u8 *vaddr, int count) | 113 | const u8 *vaddr, int count) |
112 | { | 114 | { |
113 | while (count--) | 115 | while (count--) |
114 | writeb(*vaddr++, bus_addr); | 116 | writeb(*vaddr++, bus_addr); |
115 | } | 117 | } |
116 | 118 | ||
117 | static inline void | 119 | static inline void __indirect_writew(u16 value, volatile void __iomem *p) |
118 | __ixp4xx_writew(u16 value, volatile void __iomem *p) | ||
119 | { | 120 | { |
120 | u32 addr = (u32)p; | 121 | u32 addr = (u32)p; |
121 | u32 n, byte_enables, data; | 122 | u32 n, byte_enables, data; |
122 | 123 | ||
123 | if (addr >= VMALLOC_START) { | 124 | if (!is_pci_memory(addr)) { |
124 | __raw_writew(value, addr); | 125 | __raw_writew(value, addr); |
125 | return; | 126 | return; |
126 | } | 127 | } |
@@ -131,18 +132,18 @@ __ixp4xx_writew(u16 value, volatile void __iomem *p) | |||
131 | ixp4xx_pci_write(addr, byte_enables | NP_CMD_MEMWRITE, data); | 132 | ixp4xx_pci_write(addr, byte_enables | NP_CMD_MEMWRITE, data); |
132 | } | 133 | } |
133 | 134 | ||
134 | static inline void | 135 | static inline void __indirect_writesw(volatile void __iomem *bus_addr, |
135 | __ixp4xx_writesw(volatile void __iomem *bus_addr, const u16 *vaddr, int count) | 136 | const u16 *vaddr, int count) |
136 | { | 137 | { |
137 | while (count--) | 138 | while (count--) |
138 | writew(*vaddr++, bus_addr); | 139 | writew(*vaddr++, bus_addr); |
139 | } | 140 | } |
140 | 141 | ||
141 | static inline void | 142 | static inline void __indirect_writel(u32 value, volatile void __iomem *p) |
142 | __ixp4xx_writel(u32 value, volatile void __iomem *p) | ||
143 | { | 143 | { |
144 | u32 addr = (__force u32)p; | 144 | u32 addr = (__force u32)p; |
145 | if (addr >= VMALLOC_START) { | 145 | |
146 | if (!is_pci_memory(addr)) { | ||
146 | __raw_writel(value, p); | 147 | __raw_writel(value, p); |
147 | return; | 148 | return; |
148 | } | 149 | } |
@@ -150,20 +151,19 @@ __ixp4xx_writel(u32 value, volatile void __iomem *p) | |||
150 | ixp4xx_pci_write(addr, NP_CMD_MEMWRITE, value); | 151 | ixp4xx_pci_write(addr, NP_CMD_MEMWRITE, value); |
151 | } | 152 | } |
152 | 153 | ||
153 | static inline void | 154 | static inline void __indirect_writesl(volatile void __iomem *bus_addr, |
154 | __ixp4xx_writesl(volatile void __iomem *bus_addr, const u32 *vaddr, int count) | 155 | const u32 *vaddr, int count) |
155 | { | 156 | { |
156 | while (count--) | 157 | while (count--) |
157 | writel(*vaddr++, bus_addr); | 158 | writel(*vaddr++, bus_addr); |
158 | } | 159 | } |
159 | 160 | ||
160 | static inline unsigned char | 161 | static inline unsigned char __indirect_readb(const volatile void __iomem *p) |
161 | __ixp4xx_readb(const volatile void __iomem *p) | ||
162 | { | 162 | { |
163 | u32 addr = (u32)p; | 163 | u32 addr = (u32)p; |
164 | u32 n, byte_enables, data; | 164 | u32 n, byte_enables, data; |
165 | 165 | ||
166 | if (addr >= VMALLOC_START) | 166 | if (!is_pci_memory(addr)) |
167 | return __raw_readb(addr); | 167 | return __raw_readb(addr); |
168 | 168 | ||
169 | n = addr % 4; | 169 | n = addr % 4; |
@@ -174,20 +174,19 @@ __ixp4xx_readb(const volatile void __iomem *p) | |||
174 | return data >> (8*n); | 174 | return data >> (8*n); |
175 | } | 175 | } |
176 | 176 | ||
177 | static inline void | 177 | static inline void __indirect_readsb(const volatile void __iomem *bus_addr, |
178 | __ixp4xx_readsb(const volatile void __iomem *bus_addr, u8 *vaddr, u32 count) | 178 | u8 *vaddr, u32 count) |
179 | { | 179 | { |
180 | while (count--) | 180 | while (count--) |
181 | *vaddr++ = readb(bus_addr); | 181 | *vaddr++ = readb(bus_addr); |
182 | } | 182 | } |
183 | 183 | ||
184 | static inline unsigned short | 184 | static inline unsigned short __indirect_readw(const volatile void __iomem *p) |
185 | __ixp4xx_readw(const volatile void __iomem *p) | ||
186 | { | 185 | { |
187 | u32 addr = (u32)p; | 186 | u32 addr = (u32)p; |
188 | u32 n, byte_enables, data; | 187 | u32 n, byte_enables, data; |
189 | 188 | ||
190 | if (addr >= VMALLOC_START) | 189 | if (!is_pci_memory(addr)) |
191 | return __raw_readw(addr); | 190 | return __raw_readw(addr); |
192 | 191 | ||
193 | n = addr % 4; | 192 | n = addr % 4; |
@@ -198,20 +197,19 @@ __ixp4xx_readw(const volatile void __iomem *p) | |||
198 | return data>>(8*n); | 197 | return data>>(8*n); |
199 | } | 198 | } |
200 | 199 | ||
201 | static inline void | 200 | static inline void __indirect_readsw(const volatile void __iomem *bus_addr, |
202 | __ixp4xx_readsw(const volatile void __iomem *bus_addr, u16 *vaddr, u32 count) | 201 | u16 *vaddr, u32 count) |
203 | { | 202 | { |
204 | while (count--) | 203 | while (count--) |
205 | *vaddr++ = readw(bus_addr); | 204 | *vaddr++ = readw(bus_addr); |
206 | } | 205 | } |
207 | 206 | ||
208 | static inline unsigned long | 207 | static inline unsigned long __indirect_readl(const volatile void __iomem *p) |
209 | __ixp4xx_readl(const volatile void __iomem *p) | ||
210 | { | 208 | { |
211 | u32 addr = (__force u32)p; | 209 | u32 addr = (__force u32)p; |
212 | u32 data; | 210 | u32 data; |
213 | 211 | ||
214 | if (addr >= VMALLOC_START) | 212 | if (!is_pci_memory(addr)) |
215 | return __raw_readl(p); | 213 | return __raw_readl(p); |
216 | 214 | ||
217 | if (ixp4xx_pci_read(addr, NP_CMD_MEMREAD, &data)) | 215 | if (ixp4xx_pci_read(addr, NP_CMD_MEMREAD, &data)) |
@@ -220,8 +218,8 @@ __ixp4xx_readl(const volatile void __iomem *p) | |||
220 | return data; | 218 | return data; |
221 | } | 219 | } |
222 | 220 | ||
223 | static inline void | 221 | static inline void __indirect_readsl(const volatile void __iomem *bus_addr, |
224 | __ixp4xx_readsl(const volatile void __iomem *bus_addr, u32 *vaddr, u32 count) | 222 | u32 *vaddr, u32 count) |
225 | { | 223 | { |
226 | while (count--) | 224 | while (count--) |
227 | *vaddr++ = readl(bus_addr); | 225 | *vaddr++ = readl(bus_addr); |
@@ -235,7 +233,7 @@ __ixp4xx_readsl(const volatile void __iomem *bus_addr, u32 *vaddr, u32 count) | |||
235 | #define memcpy_fromio(a,c,l) _memcpy_fromio((a),(c),(l)) | 233 | #define memcpy_fromio(a,c,l) _memcpy_fromio((a),(c),(l)) |
236 | #define memcpy_toio(c,a,l) _memcpy_toio((c),(a),(l)) | 234 | #define memcpy_toio(c,a,l) _memcpy_toio((c),(a),(l)) |
237 | 235 | ||
238 | #endif | 236 | #endif /* CONFIG_IXP4XX_INDIRECT_PCI */ |
239 | 237 | ||
240 | #ifndef CONFIG_PCI | 238 | #ifndef CONFIG_PCI |
241 | 239 | ||
@@ -250,25 +248,8 @@ __ixp4xx_readsl(const volatile void __iomem *bus_addr, u32 *vaddr, u32 count) | |||
250 | * transaction. This means that we need to override the default | 248 | * transaction. This means that we need to override the default |
251 | * I/O functions. | 249 | * I/O functions. |
252 | */ | 250 | */ |
253 | #define outb(p, v) __ixp4xx_outb(p, v) | ||
254 | #define outw(p, v) __ixp4xx_outw(p, v) | ||
255 | #define outl(p, v) __ixp4xx_outl(p, v) | ||
256 | |||
257 | #define outsb(p, v, l) __ixp4xx_outsb(p, v, l) | ||
258 | #define outsw(p, v, l) __ixp4xx_outsw(p, v, l) | ||
259 | #define outsl(p, v, l) __ixp4xx_outsl(p, v, l) | ||
260 | 251 | ||
261 | #define inb(p) __ixp4xx_inb(p) | 252 | static inline void outb(u8 value, u32 addr) |
262 | #define inw(p) __ixp4xx_inw(p) | ||
263 | #define inl(p) __ixp4xx_inl(p) | ||
264 | |||
265 | #define insb(p, v, l) __ixp4xx_insb(p, v, l) | ||
266 | #define insw(p, v, l) __ixp4xx_insw(p, v, l) | ||
267 | #define insl(p, v, l) __ixp4xx_insl(p, v, l) | ||
268 | |||
269 | |||
270 | static inline void | ||
271 | __ixp4xx_outb(u8 value, u32 addr) | ||
272 | { | 253 | { |
273 | u32 n, byte_enables, data; | 254 | u32 n, byte_enables, data; |
274 | n = addr % 4; | 255 | n = addr % 4; |
@@ -277,15 +258,13 @@ __ixp4xx_outb(u8 value, u32 addr) | |||
277 | ixp4xx_pci_write(addr, byte_enables | NP_CMD_IOWRITE, data); | 258 | ixp4xx_pci_write(addr, byte_enables | NP_CMD_IOWRITE, data); |
278 | } | 259 | } |
279 | 260 | ||
280 | static inline void | 261 | static inline void outsb(u32 io_addr, const u8 *vaddr, u32 count) |
281 | __ixp4xx_outsb(u32 io_addr, const u8 *vaddr, u32 count) | ||
282 | { | 262 | { |
283 | while (count--) | 263 | while (count--) |
284 | outb(*vaddr++, io_addr); | 264 | outb(*vaddr++, io_addr); |
285 | } | 265 | } |
286 | 266 | ||
287 | static inline void | 267 | static inline void outw(u16 value, u32 addr) |
288 | __ixp4xx_outw(u16 value, u32 addr) | ||
289 | { | 268 | { |
290 | u32 n, byte_enables, data; | 269 | u32 n, byte_enables, data; |
291 | n = addr % 4; | 270 | n = addr % 4; |
@@ -294,28 +273,24 @@ __ixp4xx_outw(u16 value, u32 addr) | |||
294 | ixp4xx_pci_write(addr, byte_enables | NP_CMD_IOWRITE, data); | 273 | ixp4xx_pci_write(addr, byte_enables | NP_CMD_IOWRITE, data); |
295 | } | 274 | } |
296 | 275 | ||
297 | static inline void | 276 | static inline void outsw(u32 io_addr, const u16 *vaddr, u32 count) |
298 | __ixp4xx_outsw(u32 io_addr, const u16 *vaddr, u32 count) | ||
299 | { | 277 | { |
300 | while (count--) | 278 | while (count--) |
301 | outw(cpu_to_le16(*vaddr++), io_addr); | 279 | outw(cpu_to_le16(*vaddr++), io_addr); |
302 | } | 280 | } |
303 | 281 | ||
304 | static inline void | 282 | static inline void outl(u32 value, u32 addr) |
305 | __ixp4xx_outl(u32 value, u32 addr) | ||
306 | { | 283 | { |
307 | ixp4xx_pci_write(addr, NP_CMD_IOWRITE, value); | 284 | ixp4xx_pci_write(addr, NP_CMD_IOWRITE, value); |
308 | } | 285 | } |
309 | 286 | ||
310 | static inline void | 287 | static inline void outsl(u32 io_addr, const u32 *vaddr, u32 count) |
311 | __ixp4xx_outsl(u32 io_addr, const u32 *vaddr, u32 count) | ||
312 | { | 288 | { |
313 | while (count--) | 289 | while (count--) |
314 | outl(*vaddr++, io_addr); | 290 | outl(cpu_to_le32(*vaddr++), io_addr); |
315 | } | 291 | } |
316 | 292 | ||
317 | static inline u8 | 293 | static inline u8 inb(u32 addr) |
318 | __ixp4xx_inb(u32 addr) | ||
319 | { | 294 | { |
320 | u32 n, byte_enables, data; | 295 | u32 n, byte_enables, data; |
321 | n = addr % 4; | 296 | n = addr % 4; |
@@ -326,15 +301,13 @@ __ixp4xx_inb(u32 addr) | |||
326 | return data >> (8*n); | 301 | return data >> (8*n); |
327 | } | 302 | } |
328 | 303 | ||
329 | static inline void | 304 | static inline void insb(u32 io_addr, u8 *vaddr, u32 count) |
330 | __ixp4xx_insb(u32 io_addr, u8 *vaddr, u32 count) | ||
331 | { | 305 | { |
332 | while (count--) | 306 | while (count--) |
333 | *vaddr++ = inb(io_addr); | 307 | *vaddr++ = inb(io_addr); |
334 | } | 308 | } |
335 | 309 | ||
336 | static inline u16 | 310 | static inline u16 inw(u32 addr) |
337 | __ixp4xx_inw(u32 addr) | ||
338 | { | 311 | { |
339 | u32 n, byte_enables, data; | 312 | u32 n, byte_enables, data; |
340 | n = addr % 4; | 313 | n = addr % 4; |
@@ -345,15 +318,13 @@ __ixp4xx_inw(u32 addr) | |||
345 | return data>>(8*n); | 318 | return data>>(8*n); |
346 | } | 319 | } |
347 | 320 | ||
348 | static inline void | 321 | static inline void insw(u32 io_addr, u16 *vaddr, u32 count) |
349 | __ixp4xx_insw(u32 io_addr, u16 *vaddr, u32 count) | ||
350 | { | 322 | { |
351 | while (count--) | 323 | while (count--) |
352 | *vaddr++ = le16_to_cpu(inw(io_addr)); | 324 | *vaddr++ = le16_to_cpu(inw(io_addr)); |
353 | } | 325 | } |
354 | 326 | ||
355 | static inline u32 | 327 | static inline u32 inl(u32 addr) |
356 | __ixp4xx_inl(u32 addr) | ||
357 | { | 328 | { |
358 | u32 data; | 329 | u32 data; |
359 | if (ixp4xx_pci_read(addr, NP_CMD_IOREAD, &data)) | 330 | if (ixp4xx_pci_read(addr, NP_CMD_IOREAD, &data)) |
@@ -362,11 +333,10 @@ __ixp4xx_inl(u32 addr) | |||
362 | return data; | 333 | return data; |
363 | } | 334 | } |
364 | 335 | ||
365 | static inline void | 336 | static inline void insl(u32 io_addr, u32 *vaddr, u32 count) |
366 | __ixp4xx_insl(u32 io_addr, u32 *vaddr, u32 count) | ||
367 | { | 337 | { |
368 | while (count--) | 338 | while (count--) |
369 | *vaddr++ = inl(io_addr); | 339 | *vaddr++ = le32_to_cpu(inl(io_addr)); |
370 | } | 340 | } |
371 | 341 | ||
372 | #define PIO_OFFSET 0x10000UL | 342 | #define PIO_OFFSET 0x10000UL |
@@ -374,194 +344,183 @@ __ixp4xx_insl(u32 io_addr, u32 *vaddr, u32 count) | |||
374 | 344 | ||
375 | #define __is_io_address(p) (((unsigned long)p >= PIO_OFFSET) && \ | 345 | #define __is_io_address(p) (((unsigned long)p >= PIO_OFFSET) && \ |
376 | ((unsigned long)p <= (PIO_MASK + PIO_OFFSET))) | 346 | ((unsigned long)p <= (PIO_MASK + PIO_OFFSET))) |
377 | static inline unsigned int | 347 | |
378 | __ixp4xx_ioread8(const void __iomem *addr) | 348 | #define ioread8(p) ioread8(p) |
349 | static inline unsigned int ioread8(const void __iomem *addr) | ||
379 | { | 350 | { |
380 | unsigned long port = (unsigned long __force)addr; | 351 | unsigned long port = (unsigned long __force)addr; |
381 | if (__is_io_address(port)) | 352 | if (__is_io_address(port)) |
382 | return (unsigned int)__ixp4xx_inb(port & PIO_MASK); | 353 | return (unsigned int)inb(port & PIO_MASK); |
383 | else | 354 | else |
384 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | 355 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI |
385 | return (unsigned int)__raw_readb(port); | 356 | return (unsigned int)__raw_readb(port); |
386 | #else | 357 | #else |
387 | return (unsigned int)__ixp4xx_readb(addr); | 358 | return (unsigned int)__indirect_readb(addr); |
388 | #endif | 359 | #endif |
389 | } | 360 | } |
390 | 361 | ||
391 | static inline void | 362 | #define ioread8_rep(p, v, c) ioread8_rep(p, v, c) |
392 | __ixp4xx_ioread8_rep(const void __iomem *addr, void *vaddr, u32 count) | 363 | static inline void ioread8_rep(const void __iomem *addr, void *vaddr, u32 count) |
393 | { | 364 | { |
394 | unsigned long port = (unsigned long __force)addr; | 365 | unsigned long port = (unsigned long __force)addr; |
395 | if (__is_io_address(port)) | 366 | if (__is_io_address(port)) |
396 | __ixp4xx_insb(port & PIO_MASK, vaddr, count); | 367 | insb(port & PIO_MASK, vaddr, count); |
397 | else | 368 | else |
398 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | 369 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI |
399 | __raw_readsb(addr, vaddr, count); | 370 | __raw_readsb(addr, vaddr, count); |
400 | #else | 371 | #else |
401 | __ixp4xx_readsb(addr, vaddr, count); | 372 | __indirect_readsb(addr, vaddr, count); |
402 | #endif | 373 | #endif |
403 | } | 374 | } |
404 | 375 | ||
405 | static inline unsigned int | 376 | #define ioread16(p) ioread16(p) |
406 | __ixp4xx_ioread16(const void __iomem *addr) | 377 | static inline unsigned int ioread16(const void __iomem *addr) |
407 | { | 378 | { |
408 | unsigned long port = (unsigned long __force)addr; | 379 | unsigned long port = (unsigned long __force)addr; |
409 | if (__is_io_address(port)) | 380 | if (__is_io_address(port)) |
410 | return (unsigned int)__ixp4xx_inw(port & PIO_MASK); | 381 | return (unsigned int)inw(port & PIO_MASK); |
411 | else | 382 | else |
412 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | 383 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI |
413 | return le16_to_cpu(__raw_readw((u32)port)); | 384 | return le16_to_cpu(__raw_readw((u32)port)); |
414 | #else | 385 | #else |
415 | return (unsigned int)__ixp4xx_readw(addr); | 386 | return (unsigned int)__indirect_readw(addr); |
416 | #endif | 387 | #endif |
417 | } | 388 | } |
418 | 389 | ||
419 | static inline void | 390 | #define ioread16_rep(p, v, c) ioread16_rep(p, v, c) |
420 | __ixp4xx_ioread16_rep(const void __iomem *addr, void *vaddr, u32 count) | 391 | static inline void ioread16_rep(const void __iomem *addr, void *vaddr, |
392 | u32 count) | ||
421 | { | 393 | { |
422 | unsigned long port = (unsigned long __force)addr; | 394 | unsigned long port = (unsigned long __force)addr; |
423 | if (__is_io_address(port)) | 395 | if (__is_io_address(port)) |
424 | __ixp4xx_insw(port & PIO_MASK, vaddr, count); | 396 | insw(port & PIO_MASK, vaddr, count); |
425 | else | 397 | else |
426 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | 398 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI |
427 | __raw_readsw(addr, vaddr, count); | 399 | __raw_readsw(addr, vaddr, count); |
428 | #else | 400 | #else |
429 | __ixp4xx_readsw(addr, vaddr, count); | 401 | __indirect_readsw(addr, vaddr, count); |
430 | #endif | 402 | #endif |
431 | } | 403 | } |
432 | 404 | ||
433 | static inline unsigned int | 405 | #define ioread32(p) ioread32(p) |
434 | __ixp4xx_ioread32(const void __iomem *addr) | 406 | static inline unsigned int ioread32(const void __iomem *addr) |
435 | { | 407 | { |
436 | unsigned long port = (unsigned long __force)addr; | 408 | unsigned long port = (unsigned long __force)addr; |
437 | if (__is_io_address(port)) | 409 | if (__is_io_address(port)) |
438 | return (unsigned int)__ixp4xx_inl(port & PIO_MASK); | 410 | return (unsigned int)inl(port & PIO_MASK); |
439 | else { | 411 | else { |
440 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | 412 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI |
441 | return le32_to_cpu((__force __le32)__raw_readl(addr)); | 413 | return le32_to_cpu((__force __le32)__raw_readl(addr)); |
442 | #else | 414 | #else |
443 | return (unsigned int)__ixp4xx_readl(addr); | 415 | return (unsigned int)__indirect_readl(addr); |
444 | #endif | 416 | #endif |
445 | } | 417 | } |
446 | } | 418 | } |
447 | 419 | ||
448 | static inline void | 420 | #define ioread32_rep(p, v, c) ioread32_rep(p, v, c) |
449 | __ixp4xx_ioread32_rep(const void __iomem *addr, void *vaddr, u32 count) | 421 | static inline void ioread32_rep(const void __iomem *addr, void *vaddr, |
422 | u32 count) | ||
450 | { | 423 | { |
451 | unsigned long port = (unsigned long __force)addr; | 424 | unsigned long port = (unsigned long __force)addr; |
452 | if (__is_io_address(port)) | 425 | if (__is_io_address(port)) |
453 | __ixp4xx_insl(port & PIO_MASK, vaddr, count); | 426 | insl(port & PIO_MASK, vaddr, count); |
454 | else | 427 | else |
455 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | 428 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI |
456 | __raw_readsl(addr, vaddr, count); | 429 | __raw_readsl(addr, vaddr, count); |
457 | #else | 430 | #else |
458 | __ixp4xx_readsl(addr, vaddr, count); | 431 | __indirect_readsl(addr, vaddr, count); |
459 | #endif | 432 | #endif |
460 | } | 433 | } |
461 | 434 | ||
462 | static inline void | 435 | #define iowrite8(v, p) iowrite8(v, p) |
463 | __ixp4xx_iowrite8(u8 value, void __iomem *addr) | 436 | static inline void iowrite8(u8 value, void __iomem *addr) |
464 | { | 437 | { |
465 | unsigned long port = (unsigned long __force)addr; | 438 | unsigned long port = (unsigned long __force)addr; |
466 | if (__is_io_address(port)) | 439 | if (__is_io_address(port)) |
467 | __ixp4xx_outb(value, port & PIO_MASK); | 440 | outb(value, port & PIO_MASK); |
468 | else | 441 | else |
469 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | 442 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI |
470 | __raw_writeb(value, port); | 443 | __raw_writeb(value, port); |
471 | #else | 444 | #else |
472 | __ixp4xx_writeb(value, addr); | 445 | __indirect_writeb(value, addr); |
473 | #endif | 446 | #endif |
474 | } | 447 | } |
475 | 448 | ||
476 | static inline void | 449 | #define iowrite8_rep(p, v, c) iowrite8_rep(p, v, c) |
477 | __ixp4xx_iowrite8_rep(void __iomem *addr, const void *vaddr, u32 count) | 450 | static inline void iowrite8_rep(void __iomem *addr, const void *vaddr, |
451 | u32 count) | ||
478 | { | 452 | { |
479 | unsigned long port = (unsigned long __force)addr; | 453 | unsigned long port = (unsigned long __force)addr; |
480 | if (__is_io_address(port)) | 454 | if (__is_io_address(port)) |
481 | __ixp4xx_outsb(port & PIO_MASK, vaddr, count); | 455 | outsb(port & PIO_MASK, vaddr, count); |
482 | else | 456 | else |
483 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | 457 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI |
484 | __raw_writesb(addr, vaddr, count); | 458 | __raw_writesb(addr, vaddr, count); |
485 | #else | 459 | #else |
486 | __ixp4xx_writesb(addr, vaddr, count); | 460 | __indirect_writesb(addr, vaddr, count); |
487 | #endif | 461 | #endif |
488 | } | 462 | } |
489 | 463 | ||
490 | static inline void | 464 | #define iowrite16(v, p) iowrite16(v, p) |
491 | __ixp4xx_iowrite16(u16 value, void __iomem *addr) | 465 | static inline void iowrite16(u16 value, void __iomem *addr) |
492 | { | 466 | { |
493 | unsigned long port = (unsigned long __force)addr; | 467 | unsigned long port = (unsigned long __force)addr; |
494 | if (__is_io_address(port)) | 468 | if (__is_io_address(port)) |
495 | __ixp4xx_outw(value, port & PIO_MASK); | 469 | outw(value, port & PIO_MASK); |
496 | else | 470 | else |
497 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | 471 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI |
498 | __raw_writew(cpu_to_le16(value), addr); | 472 | __raw_writew(cpu_to_le16(value), addr); |
499 | #else | 473 | #else |
500 | __ixp4xx_writew(value, addr); | 474 | __indirect_writew(value, addr); |
501 | #endif | 475 | #endif |
502 | } | 476 | } |
503 | 477 | ||
504 | static inline void | 478 | #define iowrite16_rep(p, v, c) iowrite16_rep(p, v, c) |
505 | __ixp4xx_iowrite16_rep(void __iomem *addr, const void *vaddr, u32 count) | 479 | static inline void iowrite16_rep(void __iomem *addr, const void *vaddr, |
480 | u32 count) | ||
506 | { | 481 | { |
507 | unsigned long port = (unsigned long __force)addr; | 482 | unsigned long port = (unsigned long __force)addr; |
508 | if (__is_io_address(port)) | 483 | if (__is_io_address(port)) |
509 | __ixp4xx_outsw(port & PIO_MASK, vaddr, count); | 484 | outsw(port & PIO_MASK, vaddr, count); |
510 | else | 485 | else |
511 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | 486 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI |
512 | __raw_writesw(addr, vaddr, count); | 487 | __raw_writesw(addr, vaddr, count); |
513 | #else | 488 | #else |
514 | __ixp4xx_writesw(addr, vaddr, count); | 489 | __indirect_writesw(addr, vaddr, count); |
515 | #endif | 490 | #endif |
516 | } | 491 | } |
517 | 492 | ||
518 | static inline void | 493 | #define iowrite32(v, p) iowrite32(v, p) |
519 | __ixp4xx_iowrite32(u32 value, void __iomem *addr) | 494 | static inline void iowrite32(u32 value, void __iomem *addr) |
520 | { | 495 | { |
521 | unsigned long port = (unsigned long __force)addr; | 496 | unsigned long port = (unsigned long __force)addr; |
522 | if (__is_io_address(port)) | 497 | if (__is_io_address(port)) |
523 | __ixp4xx_outl(value, port & PIO_MASK); | 498 | outl(value, port & PIO_MASK); |
524 | else | 499 | else |
525 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | 500 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI |
526 | __raw_writel((u32 __force)cpu_to_le32(value), addr); | 501 | __raw_writel((u32 __force)cpu_to_le32(value), addr); |
527 | #else | 502 | #else |
528 | __ixp4xx_writel(value, addr); | 503 | __indirect_writel(value, addr); |
529 | #endif | 504 | #endif |
530 | } | 505 | } |
531 | 506 | ||
532 | static inline void | 507 | #define iowrite32_rep(p, v, c) iowrite32_rep(p, v, c) |
533 | __ixp4xx_iowrite32_rep(void __iomem *addr, const void *vaddr, u32 count) | 508 | static inline void iowrite32_rep(void __iomem *addr, const void *vaddr, |
509 | u32 count) | ||
534 | { | 510 | { |
535 | unsigned long port = (unsigned long __force)addr; | 511 | unsigned long port = (unsigned long __force)addr; |
536 | if (__is_io_address(port)) | 512 | if (__is_io_address(port)) |
537 | __ixp4xx_outsl(port & PIO_MASK, vaddr, count); | 513 | outsl(port & PIO_MASK, vaddr, count); |
538 | else | 514 | else |
539 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | 515 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI |
540 | __raw_writesl(addr, vaddr, count); | 516 | __raw_writesl(addr, vaddr, count); |
541 | #else | 517 | #else |
542 | __ixp4xx_writesl(addr, vaddr, count); | 518 | __indirect_writesl(addr, vaddr, count); |
543 | #endif | 519 | #endif |
544 | } | 520 | } |
545 | 521 | ||
546 | #define ioread8(p) __ixp4xx_ioread8(p) | ||
547 | #define ioread16(p) __ixp4xx_ioread16(p) | ||
548 | #define ioread32(p) __ixp4xx_ioread32(p) | ||
549 | |||
550 | #define ioread8_rep(p, v, c) __ixp4xx_ioread8_rep(p, v, c) | ||
551 | #define ioread16_rep(p, v, c) __ixp4xx_ioread16_rep(p, v, c) | ||
552 | #define ioread32_rep(p, v, c) __ixp4xx_ioread32_rep(p, v, c) | ||
553 | |||
554 | #define iowrite8(v,p) __ixp4xx_iowrite8(v,p) | ||
555 | #define iowrite16(v,p) __ixp4xx_iowrite16(v,p) | ||
556 | #define iowrite32(v,p) __ixp4xx_iowrite32(v,p) | ||
557 | |||
558 | #define iowrite8_rep(p, v, c) __ixp4xx_iowrite8_rep(p, v, c) | ||
559 | #define iowrite16_rep(p, v, c) __ixp4xx_iowrite16_rep(p, v, c) | ||
560 | #define iowrite32_rep(p, v, c) __ixp4xx_iowrite32_rep(p, v, c) | ||
561 | |||
562 | #define ioport_map(port, nr) ((void __iomem*)(port + PIO_OFFSET)) | 522 | #define ioport_map(port, nr) ((void __iomem*)(port + PIO_OFFSET)) |
563 | #define ioport_unmap(addr) | 523 | #define ioport_unmap(addr) |
564 | #endif // !CONFIG_PCI | 524 | #endif /* CONFIG_PCI */ |
565 | |||
566 | #endif // __ASM_ARM_ARCH_IO_H | ||
567 | 525 | ||
526 | #endif /* __ASM_ARM_ARCH_IO_H */ | ||
diff --git a/arch/arm/mach-ixp4xx/include/mach/irqs.h b/arch/arm/mach-ixp4xx/include/mach/irqs.h index f4d74de1566a..7e6d4cce7c27 100644 --- a/arch/arm/mach-ixp4xx/include/mach/irqs.h +++ b/arch/arm/mach-ixp4xx/include/mach/irqs.h | |||
@@ -15,7 +15,6 @@ | |||
15 | #ifndef _ARCH_IXP4XX_IRQS_H_ | 15 | #ifndef _ARCH_IXP4XX_IRQS_H_ |
16 | #define _ARCH_IXP4XX_IRQS_H_ | 16 | #define _ARCH_IXP4XX_IRQS_H_ |
17 | 17 | ||
18 | |||
19 | #define IRQ_IXP4XX_NPEA 0 | 18 | #define IRQ_IXP4XX_NPEA 0 |
20 | #define IRQ_IXP4XX_NPEB 1 | 19 | #define IRQ_IXP4XX_NPEB 1 |
21 | #define IRQ_IXP4XX_NPEC 2 | 20 | #define IRQ_IXP4XX_NPEC 2 |
@@ -59,6 +58,9 @@ | |||
59 | #define IRQ_IXP4XX_MCU_ECC 61 | 58 | #define IRQ_IXP4XX_MCU_ECC 61 |
60 | #define IRQ_IXP4XX_EXP_PE 62 | 59 | #define IRQ_IXP4XX_EXP_PE 62 |
61 | 60 | ||
61 | #define _IXP4XX_GPIO_IRQ(n) (IRQ_IXP4XX_GPIO ## n) | ||
62 | #define IXP4XX_GPIO_IRQ(n) _IXP4XX_GPIO_IRQ(n) | ||
63 | |||
62 | /* | 64 | /* |
63 | * Only first 32 sources are valid if running on IXP42x systems | 65 | * Only first 32 sources are valid if running on IXP42x systems |
64 | */ | 66 | */ |
@@ -70,69 +72,4 @@ | |||
70 | 72 | ||
71 | #define XSCALE_PMU_IRQ (IRQ_IXP4XX_XSCALE_PMU) | 73 | #define XSCALE_PMU_IRQ (IRQ_IXP4XX_XSCALE_PMU) |
72 | 74 | ||
73 | /* | ||
74 | * IXDP425 board IRQs | ||
75 | */ | ||
76 | #define IRQ_IXDP425_PCI_INTA IRQ_IXP4XX_GPIO11 | ||
77 | #define IRQ_IXDP425_PCI_INTB IRQ_IXP4XX_GPIO10 | ||
78 | #define IRQ_IXDP425_PCI_INTC IRQ_IXP4XX_GPIO9 | ||
79 | #define IRQ_IXDP425_PCI_INTD IRQ_IXP4XX_GPIO8 | ||
80 | |||
81 | /* | ||
82 | * Gateworks Avila board IRQs | ||
83 | */ | ||
84 | #define IRQ_AVILA_PCI_INTA IRQ_IXP4XX_GPIO11 | ||
85 | #define IRQ_AVILA_PCI_INTB IRQ_IXP4XX_GPIO10 | ||
86 | #define IRQ_AVILA_PCI_INTC IRQ_IXP4XX_GPIO9 | ||
87 | #define IRQ_AVILA_PCI_INTD IRQ_IXP4XX_GPIO8 | ||
88 | |||
89 | |||
90 | /* | ||
91 | * PrPMC1100 Board IRQs | ||
92 | */ | ||
93 | #define IRQ_PRPMC1100_PCI_INTA IRQ_IXP4XX_GPIO11 | ||
94 | #define IRQ_PRPMC1100_PCI_INTB IRQ_IXP4XX_GPIO10 | ||
95 | #define IRQ_PRPMC1100_PCI_INTC IRQ_IXP4XX_GPIO9 | ||
96 | #define IRQ_PRPMC1100_PCI_INTD IRQ_IXP4XX_GPIO8 | ||
97 | |||
98 | /* | ||
99 | * ADI Coyote Board IRQs | ||
100 | */ | ||
101 | #define IRQ_COYOTE_PCI_SLOT0 IRQ_IXP4XX_GPIO6 | ||
102 | #define IRQ_COYOTE_PCI_SLOT1 IRQ_IXP4XX_GPIO11 | ||
103 | #define IRQ_COYOTE_IDE IRQ_IXP4XX_GPIO5 | ||
104 | |||
105 | /* | ||
106 | * NSLU2 board IRQs | ||
107 | */ | ||
108 | #define IRQ_NSLU2_PCI_INTA IRQ_IXP4XX_GPIO11 | ||
109 | #define IRQ_NSLU2_PCI_INTB IRQ_IXP4XX_GPIO10 | ||
110 | #define IRQ_NSLU2_PCI_INTC IRQ_IXP4XX_GPIO9 | ||
111 | |||
112 | /* | ||
113 | * NAS100D board IRQs | ||
114 | */ | ||
115 | #define IRQ_NAS100D_PCI_INTA IRQ_IXP4XX_GPIO11 | ||
116 | #define IRQ_NAS100D_PCI_INTB IRQ_IXP4XX_GPIO10 | ||
117 | #define IRQ_NAS100D_PCI_INTC IRQ_IXP4XX_GPIO9 | ||
118 | #define IRQ_NAS100D_PCI_INTD IRQ_IXP4XX_GPIO8 | ||
119 | #define IRQ_NAS100D_PCI_INTE IRQ_IXP4XX_GPIO7 | ||
120 | |||
121 | /* | ||
122 | * D-Link DSM-G600 RevA board IRQs | ||
123 | */ | ||
124 | #define IRQ_DSMG600_PCI_INTA IRQ_IXP4XX_GPIO11 | ||
125 | #define IRQ_DSMG600_PCI_INTB IRQ_IXP4XX_GPIO10 | ||
126 | #define IRQ_DSMG600_PCI_INTC IRQ_IXP4XX_GPIO9 | ||
127 | #define IRQ_DSMG600_PCI_INTD IRQ_IXP4XX_GPIO8 | ||
128 | #define IRQ_DSMG600_PCI_INTE IRQ_IXP4XX_GPIO7 | ||
129 | #define IRQ_DSMG600_PCI_INTF IRQ_IXP4XX_GPIO6 | ||
130 | |||
131 | /* | ||
132 | * Freecom FSG-3 Board IRQs | ||
133 | */ | ||
134 | #define IRQ_FSG_PCI_INTA IRQ_IXP4XX_GPIO6 | ||
135 | #define IRQ_FSG_PCI_INTB IRQ_IXP4XX_GPIO7 | ||
136 | #define IRQ_FSG_PCI_INTC IRQ_IXP4XX_GPIO5 | ||
137 | |||
138 | #endif | 75 | #endif |
diff --git a/arch/arm/mach-ixp4xx/include/mach/ixdp425.h b/arch/arm/mach-ixp4xx/include/mach/ixdp425.h deleted file mode 100644 index 2cafe65ebfee..000000000000 --- a/arch/arm/mach-ixp4xx/include/mach/ixdp425.h +++ /dev/null | |||
@@ -1,39 +0,0 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-ixp4xx/include/mach/ixdp425.h | ||
3 | * | ||
4 | * IXDP425 platform specific definitions | ||
5 | * | ||
6 | * Author: Deepak Saxena <dsaxena@plexity.net> | ||
7 | * | ||
8 | * Copyright 2004 (c) MontaVista, Software, Inc. | ||
9 | * | ||
10 | * This file is licensed under the terms of the GNU General Public | ||
11 | * License version 2. This program is licensed "as is" without any | ||
12 | * warranty of any kind, whether express or implied. | ||
13 | */ | ||
14 | |||
15 | #ifndef __ASM_ARCH_HARDWARE_H__ | ||
16 | #error "Do not include this directly, instead #include <mach/hardware.h>" | ||
17 | #endif | ||
18 | |||
19 | #define IXDP425_SDA_PIN 7 | ||
20 | #define IXDP425_SCL_PIN 6 | ||
21 | |||
22 | /* | ||
23 | * IXDP425 PCI IRQs | ||
24 | */ | ||
25 | #define IXDP425_PCI_MAX_DEV 4 | ||
26 | #define IXDP425_PCI_IRQ_LINES 4 | ||
27 | |||
28 | |||
29 | /* PCI controller GPIO to IRQ pin mappings */ | ||
30 | #define IXDP425_PCI_INTA_PIN 11 | ||
31 | #define IXDP425_PCI_INTB_PIN 10 | ||
32 | #define IXDP425_PCI_INTC_PIN 9 | ||
33 | #define IXDP425_PCI_INTD_PIN 8 | ||
34 | |||
35 | /* NAND Flash pins */ | ||
36 | #define IXDP425_NAND_NCE_PIN 12 | ||
37 | |||
38 | #define IXDP425_NAND_CMD_BYTE 0x01 | ||
39 | #define IXDP425_NAND_ADDR_BYTE 0x02 | ||
diff --git a/arch/arm/mach-ixp4xx/include/mach/nas100d.h b/arch/arm/mach-ixp4xx/include/mach/nas100d.h deleted file mode 100644 index 3771d62a9748..000000000000 --- a/arch/arm/mach-ixp4xx/include/mach/nas100d.h +++ /dev/null | |||
@@ -1,52 +0,0 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-ixp4xx/include/mach/nas100d.h | ||
3 | * | ||
4 | * NAS100D platform specific definitions | ||
5 | * | ||
6 | * Copyright (c) 2005 Tower Technologies | ||
7 | * | ||
8 | * Author: Alessandro Zummo <a.zummo@towertech.it> | ||
9 | * | ||
10 | * based on ixdp425.h: | ||
11 | * Copyright 2004 (c) MontaVista, Software, Inc. | ||
12 | * | ||
13 | * This file is licensed under the terms of the GNU General Public | ||
14 | * License version 2. This program is licensed "as is" without any | ||
15 | * warranty of any kind, whether express or implied. | ||
16 | */ | ||
17 | |||
18 | #ifndef __ASM_ARCH_HARDWARE_H__ | ||
19 | #error "Do not include this directly, instead #include <mach/hardware.h>" | ||
20 | #endif | ||
21 | |||
22 | #define NAS100D_SDA_PIN 5 | ||
23 | #define NAS100D_SCL_PIN 6 | ||
24 | |||
25 | /* | ||
26 | * NAS100D PCI IRQs | ||
27 | */ | ||
28 | #define NAS100D_PCI_MAX_DEV 3 | ||
29 | #define NAS100D_PCI_IRQ_LINES 3 | ||
30 | |||
31 | |||
32 | /* PCI controller GPIO to IRQ pin mappings */ | ||
33 | #define NAS100D_PCI_INTA_PIN 11 | ||
34 | #define NAS100D_PCI_INTB_PIN 10 | ||
35 | #define NAS100D_PCI_INTC_PIN 9 | ||
36 | #define NAS100D_PCI_INTD_PIN 8 | ||
37 | #define NAS100D_PCI_INTE_PIN 7 | ||
38 | |||
39 | /* Buttons */ | ||
40 | |||
41 | #define NAS100D_PB_GPIO 14 /* power button */ | ||
42 | #define NAS100D_RB_GPIO 4 /* reset button */ | ||
43 | |||
44 | /* Power control */ | ||
45 | |||
46 | #define NAS100D_PO_GPIO 12 /* power off */ | ||
47 | |||
48 | /* LEDs */ | ||
49 | |||
50 | #define NAS100D_LED_WLAN_GPIO 0 | ||
51 | #define NAS100D_LED_DISK_GPIO 3 | ||
52 | #define NAS100D_LED_PWR_GPIO 15 | ||
diff --git a/arch/arm/mach-ixp4xx/include/mach/npe.h b/arch/arm/mach-ixp4xx/include/mach/npe.h index 37d0511689dc..e320db2457ae 100644 --- a/arch/arm/mach-ixp4xx/include/mach/npe.h +++ b/arch/arm/mach-ixp4xx/include/mach/npe.h | |||
@@ -33,7 +33,7 @@ int npe_send_message(struct npe *npe, const void *msg, const char *what); | |||
33 | int npe_recv_message(struct npe *npe, void *msg, const char *what); | 33 | int npe_recv_message(struct npe *npe, void *msg, const char *what); |
34 | int npe_send_recv_message(struct npe *npe, void *msg, const char *what); | 34 | int npe_send_recv_message(struct npe *npe, void *msg, const char *what); |
35 | int npe_load_firmware(struct npe *npe, const char *name, struct device *dev); | 35 | int npe_load_firmware(struct npe *npe, const char *name, struct device *dev); |
36 | struct npe *npe_request(int id); | 36 | struct npe *npe_request(unsigned id); |
37 | void npe_release(struct npe *npe); | 37 | void npe_release(struct npe *npe); |
38 | 38 | ||
39 | #endif /* __IXP4XX_NPE_H */ | 39 | #endif /* __IXP4XX_NPE_H */ |
diff --git a/arch/arm/mach-ixp4xx/include/mach/nslu2.h b/arch/arm/mach-ixp4xx/include/mach/nslu2.h deleted file mode 100644 index 85d00adbfb92..000000000000 --- a/arch/arm/mach-ixp4xx/include/mach/nslu2.h +++ /dev/null | |||
@@ -1,55 +0,0 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-ixp4xx/include/mach/nslu2.h | ||
3 | * | ||
4 | * NSLU2 platform specific definitions | ||
5 | * | ||
6 | * Author: Mark Rakes <mrakes AT mac.com> | ||
7 | * Maintainers: http://www.nslu2-linux.org | ||
8 | * | ||
9 | * based on ixdp425.h: | ||
10 | * Copyright 2004 (c) MontaVista, Software, Inc. | ||
11 | * | ||
12 | * This file is licensed under the terms of the GNU General Public | ||
13 | * License version 2. This program is licensed "as is" without any | ||
14 | * warranty of any kind, whether express or implied. | ||
15 | */ | ||
16 | |||
17 | #ifndef __ASM_ARCH_HARDWARE_H__ | ||
18 | #error "Do not include this directly, instead #include <mach/hardware.h>" | ||
19 | #endif | ||
20 | |||
21 | #define NSLU2_SDA_PIN 7 | ||
22 | #define NSLU2_SCL_PIN 6 | ||
23 | |||
24 | /* | ||
25 | * NSLU2 PCI IRQs | ||
26 | */ | ||
27 | #define NSLU2_PCI_MAX_DEV 3 | ||
28 | #define NSLU2_PCI_IRQ_LINES 3 | ||
29 | |||
30 | |||
31 | /* PCI controller GPIO to IRQ pin mappings */ | ||
32 | #define NSLU2_PCI_INTA_PIN 11 | ||
33 | #define NSLU2_PCI_INTB_PIN 10 | ||
34 | #define NSLU2_PCI_INTC_PIN 9 | ||
35 | #define NSLU2_PCI_INTD_PIN 8 | ||
36 | |||
37 | /* NSLU2 Timer */ | ||
38 | #define NSLU2_FREQ 66000000 | ||
39 | |||
40 | /* Buttons */ | ||
41 | |||
42 | #define NSLU2_PB_GPIO 5 /* power button */ | ||
43 | #define NSLU2_PO_GPIO 8 /* power off */ | ||
44 | #define NSLU2_RB_GPIO 12 /* reset button */ | ||
45 | |||
46 | /* Buzzer */ | ||
47 | |||
48 | #define NSLU2_GPIO_BUZZ 4 | ||
49 | |||
50 | /* LEDs */ | ||
51 | |||
52 | #define NSLU2_LED_RED_GPIO 0 | ||
53 | #define NSLU2_LED_GRN_GPIO 1 | ||
54 | #define NSLU2_LED_DISK1_GPIO 3 | ||
55 | #define NSLU2_LED_DISK2_GPIO 2 | ||
diff --git a/arch/arm/mach-ixp4xx/include/mach/prpmc1100.h b/arch/arm/mach-ixp4xx/include/mach/prpmc1100.h deleted file mode 100644 index 17274a2e3dec..000000000000 --- a/arch/arm/mach-ixp4xx/include/mach/prpmc1100.h +++ /dev/null | |||
@@ -1,33 +0,0 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-ixp4xx/include/mach/prpmc1100.h | ||
3 | * | ||
4 | * Motorolla PrPMC1100 platform specific definitions | ||
5 | * | ||
6 | * Author: Deepak Saxena <dsaxena@plexity.net> | ||
7 | * | ||
8 | * Copyright 2004 (c) MontaVista, Software, Inc. | ||
9 | * | ||
10 | * This file is licensed under the terms of the GNU General Public | ||
11 | * License version 2. This program is licensed "as is" without any | ||
12 | * warranty of any kind, whether express or implied. | ||
13 | */ | ||
14 | |||
15 | #ifndef __ASM_ARCH_HARDWARE_H__ | ||
16 | #error "Do not include this directly, instead #include <mach/hardware.h>" | ||
17 | #endif | ||
18 | |||
19 | #define PRPMC1100_FLASH_BASE IXP4XX_EXP_BUS_CS0_BASE_PHYS | ||
20 | #define PRPMC1100_FLASH_SIZE IXP4XX_EXP_BUS_CSX_REGION_SIZE | ||
21 | |||
22 | #define PRPMC1100_PCI_MIN_DEVID 10 | ||
23 | #define PRPMC1100_PCI_MAX_DEVID 16 | ||
24 | #define PRPMC1100_PCI_IRQ_LINES 4 | ||
25 | |||
26 | |||
27 | /* PCI controller GPIO to IRQ pin mappings */ | ||
28 | #define PRPMC1100_PCI_INTA_PIN 11 | ||
29 | #define PRPMC1100_PCI_INTB_PIN 10 | ||
30 | #define PRPMC1100_PCI_INTC_PIN 9 | ||
31 | #define PRPMC1100_PCI_INTD_PIN 8 | ||
32 | |||
33 | |||
diff --git a/arch/arm/mach-ixp4xx/include/mach/timex.h b/arch/arm/mach-ixp4xx/include/mach/timex.h index 89ce3ee84698..2c3f93c3eb79 100644 --- a/arch/arm/mach-ixp4xx/include/mach/timex.h +++ b/arch/arm/mach-ixp4xx/include/mach/timex.h | |||
@@ -10,6 +10,6 @@ | |||
10 | * 66.66... MHz. We do a convulted calculation of CLOCK_TICK_RATE b/c the | 10 | * 66.66... MHz. We do a convulted calculation of CLOCK_TICK_RATE b/c the |
11 | * timer register ignores the bottom 2 bits of the LATCH value. | 11 | * timer register ignores the bottom 2 bits of the LATCH value. |
12 | */ | 12 | */ |
13 | #define FREQ 66666666 | 13 | #define FREQ 66666000 |
14 | #define CLOCK_TICK_RATE (((FREQ / HZ & ~IXP4XX_OST_RELOAD_MASK) + 1) * HZ) | 14 | #define CLOCK_TICK_RATE (((FREQ / HZ & ~IXP4XX_OST_RELOAD_MASK) + 1) * HZ) |
15 | 15 | ||
diff --git a/arch/arm/mach-ixp4xx/ixdp425-pci.c b/arch/arm/mach-ixp4xx/ixdp425-pci.c index 64c29aacaac9..1ba165a6edac 100644 --- a/arch/arm/mach-ixp4xx/ixdp425-pci.c +++ b/arch/arm/mach-ixp4xx/ixdp425-pci.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * arch/arm/mach-ixp4xx/ixdp425-pci.c | 2 | * arch/arm/mach-ixp4xx/ixdp425-pci.c |
3 | * | 3 | * |
4 | * IXDP425 board-level PCI initialization | 4 | * IXDP425 board-level PCI initialization |
5 | * | 5 | * |
@@ -19,39 +19,43 @@ | |||
19 | #include <linux/init.h> | 19 | #include <linux/init.h> |
20 | #include <linux/irq.h> | 20 | #include <linux/irq.h> |
21 | #include <linux/delay.h> | 21 | #include <linux/delay.h> |
22 | |||
23 | #include <asm/mach/pci.h> | 22 | #include <asm/mach/pci.h> |
24 | #include <asm/irq.h> | 23 | #include <asm/irq.h> |
25 | #include <mach/hardware.h> | 24 | #include <mach/hardware.h> |
26 | #include <asm/mach-types.h> | 25 | #include <asm/mach-types.h> |
27 | 26 | ||
27 | #define MAX_DEV 4 | ||
28 | #define IRQ_LINES 4 | ||
29 | |||
30 | /* PCI controller GPIO to IRQ pin mappings */ | ||
31 | #define INTA 11 | ||
32 | #define INTB 10 | ||
33 | #define INTC 9 | ||
34 | #define INTD 8 | ||
35 | |||
36 | |||
28 | void __init ixdp425_pci_preinit(void) | 37 | void __init ixdp425_pci_preinit(void) |
29 | { | 38 | { |
30 | set_irq_type(IRQ_IXDP425_PCI_INTA, IRQ_TYPE_LEVEL_LOW); | 39 | set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); |
31 | set_irq_type(IRQ_IXDP425_PCI_INTB, IRQ_TYPE_LEVEL_LOW); | 40 | set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); |
32 | set_irq_type(IRQ_IXDP425_PCI_INTC, IRQ_TYPE_LEVEL_LOW); | 41 | set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); |
33 | set_irq_type(IRQ_IXDP425_PCI_INTD, IRQ_TYPE_LEVEL_LOW); | 42 | set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW); |
34 | |||
35 | ixp4xx_pci_preinit(); | 43 | ixp4xx_pci_preinit(); |
36 | } | 44 | } |
37 | 45 | ||
38 | static int __init ixdp425_map_irq(struct pci_dev *dev, u8 slot, u8 pin) | 46 | static int __init ixdp425_map_irq(struct pci_dev *dev, u8 slot, u8 pin) |
39 | { | 47 | { |
40 | static int pci_irq_table[IXDP425_PCI_IRQ_LINES] = { | 48 | static int pci_irq_table[IRQ_LINES] = { |
41 | IRQ_IXDP425_PCI_INTA, | 49 | IXP4XX_GPIO_IRQ(INTA), |
42 | IRQ_IXDP425_PCI_INTB, | 50 | IXP4XX_GPIO_IRQ(INTB), |
43 | IRQ_IXDP425_PCI_INTC, | 51 | IXP4XX_GPIO_IRQ(INTC), |
44 | IRQ_IXDP425_PCI_INTD | 52 | IXP4XX_GPIO_IRQ(INTD) |
45 | }; | 53 | }; |
46 | 54 | ||
47 | int irq = -1; | 55 | if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES) |
48 | 56 | return pci_irq_table[(slot + pin - 2) % 4]; | |
49 | if (slot >= 1 && slot <= IXDP425_PCI_MAX_DEV && | ||
50 | pin >= 1 && pin <= IXDP425_PCI_IRQ_LINES) { | ||
51 | irq = pci_irq_table[(slot + pin - 2) % 4]; | ||
52 | } | ||
53 | 57 | ||
54 | return irq; | 58 | return -1; |
55 | } | 59 | } |
56 | 60 | ||
57 | struct hw_pci ixdp425_pci __initdata = { | 61 | struct hw_pci ixdp425_pci __initdata = { |
@@ -72,4 +76,3 @@ int __init ixdp425_pci_init(void) | |||
72 | } | 76 | } |
73 | 77 | ||
74 | subsys_initcall(ixdp425_pci_init); | 78 | subsys_initcall(ixdp425_pci_init); |
75 | |||
diff --git a/arch/arm/mach-ixp4xx/ixdp425-setup.c b/arch/arm/mach-ixp4xx/ixdp425-setup.c index f4a0c1bc1331..bbb768988845 100644 --- a/arch/arm/mach-ixp4xx/ixdp425-setup.c +++ b/arch/arm/mach-ixp4xx/ixdp425-setup.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * arch/arm/mach-ixp4xx/ixdp425-setup.c | 2 | * arch/arm/mach-ixp4xx/ixdp425-setup.c |
3 | * | 3 | * |
4 | * IXDP425/IXCDP1100 board-setup | 4 | * IXDP425/IXCDP1100 board-setup |
5 | * | 5 | * |
6 | * Copyright (C) 2003-2005 MontaVista Software, Inc. | 6 | * Copyright (C) 2003-2005 MontaVista Software, Inc. |
7 | * | 7 | * |
@@ -21,7 +21,6 @@ | |||
21 | #include <linux/mtd/nand.h> | 21 | #include <linux/mtd/nand.h> |
22 | #include <linux/mtd/partitions.h> | 22 | #include <linux/mtd/partitions.h> |
23 | #include <linux/delay.h> | 23 | #include <linux/delay.h> |
24 | |||
25 | #include <asm/types.h> | 24 | #include <asm/types.h> |
26 | #include <asm/setup.h> | 25 | #include <asm/setup.h> |
27 | #include <asm/memory.h> | 26 | #include <asm/memory.h> |
@@ -31,6 +30,15 @@ | |||
31 | #include <asm/mach/arch.h> | 30 | #include <asm/mach/arch.h> |
32 | #include <asm/mach/flash.h> | 31 | #include <asm/mach/flash.h> |
33 | 32 | ||
33 | #define IXDP425_SDA_PIN 7 | ||
34 | #define IXDP425_SCL_PIN 6 | ||
35 | |||
36 | /* NAND Flash pins */ | ||
37 | #define IXDP425_NAND_NCE_PIN 12 | ||
38 | |||
39 | #define IXDP425_NAND_CMD_BYTE 0x01 | ||
40 | #define IXDP425_NAND_ADDR_BYTE 0x02 | ||
41 | |||
34 | static struct flash_platform_data ixdp425_flash_data = { | 42 | static struct flash_platform_data ixdp425_flash_data = { |
35 | .map_name = "cfi_probe", | 43 | .map_name = "cfi_probe", |
36 | .width = 2, | 44 | .width = 2, |
diff --git a/arch/arm/mach-ixp4xx/ixp4xx_npe.c b/arch/arm/mach-ixp4xx/ixp4xx_npe.c index 47ac69c7ec78..e8bb25778166 100644 --- a/arch/arm/mach-ixp4xx/ixp4xx_npe.c +++ b/arch/arm/mach-ixp4xx/ixp4xx_npe.c | |||
@@ -665,7 +665,7 @@ err: | |||
665 | } | 665 | } |
666 | 666 | ||
667 | 667 | ||
668 | struct npe *npe_request(int id) | 668 | struct npe *npe_request(unsigned id) |
669 | { | 669 | { |
670 | if (id < NPE_COUNT) | 670 | if (id < NPE_COUNT) |
671 | if (npe_tab[id].valid) | 671 | if (npe_tab[id].valid) |
diff --git a/arch/arm/mach-ixp4xx/nas100d-pci.c b/arch/arm/mach-ixp4xx/nas100d-pci.c index 1088426fdcee..d0cea34cf61e 100644 --- a/arch/arm/mach-ixp4xx/nas100d-pci.c +++ b/arch/arm/mach-ixp4xx/nas100d-pci.c | |||
@@ -18,37 +18,42 @@ | |||
18 | #include <linux/pci.h> | 18 | #include <linux/pci.h> |
19 | #include <linux/init.h> | 19 | #include <linux/init.h> |
20 | #include <linux/irq.h> | 20 | #include <linux/irq.h> |
21 | |||
22 | #include <asm/mach/pci.h> | 21 | #include <asm/mach/pci.h> |
23 | #include <asm/mach-types.h> | 22 | #include <asm/mach-types.h> |
24 | 23 | ||
24 | #define MAX_DEV 3 | ||
25 | #define IRQ_LINES 3 | ||
26 | |||
27 | /* PCI controller GPIO to IRQ pin mappings */ | ||
28 | #define INTA 11 | ||
29 | #define INTB 10 | ||
30 | #define INTC 9 | ||
31 | #define INTD 8 | ||
32 | #define INTE 7 | ||
33 | |||
25 | void __init nas100d_pci_preinit(void) | 34 | void __init nas100d_pci_preinit(void) |
26 | { | 35 | { |
27 | set_irq_type(IRQ_NAS100D_PCI_INTA, IRQ_TYPE_LEVEL_LOW); | 36 | set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); |
28 | set_irq_type(IRQ_NAS100D_PCI_INTB, IRQ_TYPE_LEVEL_LOW); | 37 | set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); |
29 | set_irq_type(IRQ_NAS100D_PCI_INTC, IRQ_TYPE_LEVEL_LOW); | 38 | set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); |
30 | set_irq_type(IRQ_NAS100D_PCI_INTD, IRQ_TYPE_LEVEL_LOW); | 39 | set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW); |
31 | set_irq_type(IRQ_NAS100D_PCI_INTE, IRQ_TYPE_LEVEL_LOW); | 40 | set_irq_type(IXP4XX_GPIO_IRQ(INTE), IRQ_TYPE_LEVEL_LOW); |
32 | |||
33 | ixp4xx_pci_preinit(); | 41 | ixp4xx_pci_preinit(); |
34 | } | 42 | } |
35 | 43 | ||
36 | static int __init nas100d_map_irq(struct pci_dev *dev, u8 slot, u8 pin) | 44 | static int __init nas100d_map_irq(struct pci_dev *dev, u8 slot, u8 pin) |
37 | { | 45 | { |
38 | static int pci_irq_table[NAS100D_PCI_MAX_DEV][NAS100D_PCI_IRQ_LINES] = | 46 | static int pci_irq_table[MAX_DEV][IRQ_LINES] = { |
39 | { | 47 | { IXP4XX_GPIO_IRQ(INTA), -1, -1 }, |
40 | { IRQ_NAS100D_PCI_INTA, -1, -1 }, | 48 | { IXP4XX_GPIO_IRQ(INTB), -1, -1 }, |
41 | { IRQ_NAS100D_PCI_INTB, -1, -1 }, | 49 | { IXP4XX_GPIO_IRQ(INTC), IXP4XX_GPIO_IRQ(INTD), |
42 | { IRQ_NAS100D_PCI_INTC, IRQ_NAS100D_PCI_INTD, IRQ_NAS100D_PCI_INTE }, | 50 | IXP4XX_GPIO_IRQ(INTE) }, |
43 | }; | 51 | }; |
44 | 52 | ||
45 | int irq = -1; | 53 | if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES) |
46 | 54 | return pci_irq_table[slot - 1][pin - 1]; | |
47 | if (slot >= 1 && slot <= NAS100D_PCI_MAX_DEV && | ||
48 | pin >= 1 && pin <= NAS100D_PCI_IRQ_LINES) | ||
49 | irq = pci_irq_table[slot-1][pin-1]; | ||
50 | 55 | ||
51 | return irq; | 56 | return -1; |
52 | } | 57 | } |
53 | 58 | ||
54 | struct hw_pci __initdata nas100d_pci = { | 59 | struct hw_pci __initdata nas100d_pci = { |
diff --git a/arch/arm/mach-ixp4xx/nas100d-setup.c b/arch/arm/mach-ixp4xx/nas100d-setup.c index 921c947b5b6b..e3ee880aa1e6 100644 --- a/arch/arm/mach-ixp4xx/nas100d-setup.c +++ b/arch/arm/mach-ixp4xx/nas100d-setup.c | |||
@@ -29,12 +29,26 @@ | |||
29 | #include <linux/i2c.h> | 29 | #include <linux/i2c.h> |
30 | #include <linux/i2c-gpio.h> | 30 | #include <linux/i2c-gpio.h> |
31 | #include <linux/io.h> | 31 | #include <linux/io.h> |
32 | |||
33 | #include <asm/mach-types.h> | 32 | #include <asm/mach-types.h> |
34 | #include <asm/mach/arch.h> | 33 | #include <asm/mach/arch.h> |
35 | #include <asm/mach/flash.h> | 34 | #include <asm/mach/flash.h> |
36 | #include <asm/gpio.h> | 35 | #include <asm/gpio.h> |
37 | 36 | ||
37 | #define NAS100D_SDA_PIN 5 | ||
38 | #define NAS100D_SCL_PIN 6 | ||
39 | |||
40 | /* Buttons */ | ||
41 | #define NAS100D_PB_GPIO 14 /* power button */ | ||
42 | #define NAS100D_RB_GPIO 4 /* reset button */ | ||
43 | |||
44 | /* Power control */ | ||
45 | #define NAS100D_PO_GPIO 12 /* power off */ | ||
46 | |||
47 | /* LEDs */ | ||
48 | #define NAS100D_LED_WLAN_GPIO 0 | ||
49 | #define NAS100D_LED_DISK_GPIO 3 | ||
50 | #define NAS100D_LED_PWR_GPIO 15 | ||
51 | |||
38 | static struct flash_platform_data nas100d_flash_data = { | 52 | static struct flash_platform_data nas100d_flash_data = { |
39 | .map_name = "cfi_probe", | 53 | .map_name = "cfi_probe", |
40 | .width = 2, | 54 | .width = 2, |
diff --git a/arch/arm/mach-ixp4xx/nslu2-pci.c b/arch/arm/mach-ixp4xx/nslu2-pci.c index 4429b8448b61..1eb5a90470bc 100644 --- a/arch/arm/mach-ixp4xx/nslu2-pci.c +++ b/arch/arm/mach-ixp4xx/nslu2-pci.c | |||
@@ -18,35 +18,38 @@ | |||
18 | #include <linux/pci.h> | 18 | #include <linux/pci.h> |
19 | #include <linux/init.h> | 19 | #include <linux/init.h> |
20 | #include <linux/irq.h> | 20 | #include <linux/irq.h> |
21 | |||
22 | #include <asm/mach/pci.h> | 21 | #include <asm/mach/pci.h> |
23 | #include <asm/mach-types.h> | 22 | #include <asm/mach-types.h> |
24 | 23 | ||
24 | #define MAX_DEV 3 | ||
25 | #define IRQ_LINES 3 | ||
26 | |||
27 | /* PCI controller GPIO to IRQ pin mappings */ | ||
28 | #define INTA 11 | ||
29 | #define INTB 10 | ||
30 | #define INTC 9 | ||
31 | #define INTD 8 | ||
32 | |||
25 | void __init nslu2_pci_preinit(void) | 33 | void __init nslu2_pci_preinit(void) |
26 | { | 34 | { |
27 | set_irq_type(IRQ_NSLU2_PCI_INTA, IRQ_TYPE_LEVEL_LOW); | 35 | set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); |
28 | set_irq_type(IRQ_NSLU2_PCI_INTB, IRQ_TYPE_LEVEL_LOW); | 36 | set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); |
29 | set_irq_type(IRQ_NSLU2_PCI_INTC, IRQ_TYPE_LEVEL_LOW); | 37 | set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); |
30 | |||
31 | ixp4xx_pci_preinit(); | 38 | ixp4xx_pci_preinit(); |
32 | } | 39 | } |
33 | 40 | ||
34 | static int __init nslu2_map_irq(struct pci_dev *dev, u8 slot, u8 pin) | 41 | static int __init nslu2_map_irq(struct pci_dev *dev, u8 slot, u8 pin) |
35 | { | 42 | { |
36 | static int pci_irq_table[NSLU2_PCI_IRQ_LINES] = { | 43 | static int pci_irq_table[IRQ_LINES] = { |
37 | IRQ_NSLU2_PCI_INTA, | 44 | IXP4XX_GPIO_IRQ(INTA), |
38 | IRQ_NSLU2_PCI_INTB, | 45 | IXP4XX_GPIO_IRQ(INTB), |
39 | IRQ_NSLU2_PCI_INTC, | 46 | IXP4XX_GPIO_IRQ(INTC), |
40 | }; | 47 | }; |
41 | 48 | ||
42 | int irq = -1; | 49 | if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES) |
43 | 50 | return pci_irq_table[(slot + pin - 2) % IRQ_LINES]; | |
44 | if (slot >= 1 && slot <= NSLU2_PCI_MAX_DEV && | ||
45 | pin >= 1 && pin <= NSLU2_PCI_IRQ_LINES) { | ||
46 | irq = pci_irq_table[(slot + pin - 2) % NSLU2_PCI_IRQ_LINES]; | ||
47 | } | ||
48 | 51 | ||
49 | return irq; | 52 | return -1; |
50 | } | 53 | } |
51 | 54 | ||
52 | struct hw_pci __initdata nslu2_pci = { | 55 | struct hw_pci __initdata nslu2_pci = { |
diff --git a/arch/arm/mach-ixp4xx/nslu2-setup.c b/arch/arm/mach-ixp4xx/nslu2-setup.c index ff6a08d02cc4..c14e0034be4b 100644 --- a/arch/arm/mach-ixp4xx/nslu2-setup.c +++ b/arch/arm/mach-ixp4xx/nslu2-setup.c | |||
@@ -26,13 +26,32 @@ | |||
26 | #include <linux/i2c.h> | 26 | #include <linux/i2c.h> |
27 | #include <linux/i2c-gpio.h> | 27 | #include <linux/i2c-gpio.h> |
28 | #include <linux/io.h> | 28 | #include <linux/io.h> |
29 | |||
30 | #include <asm/mach-types.h> | 29 | #include <asm/mach-types.h> |
31 | #include <asm/mach/arch.h> | 30 | #include <asm/mach/arch.h> |
32 | #include <asm/mach/flash.h> | 31 | #include <asm/mach/flash.h> |
33 | #include <asm/mach/time.h> | 32 | #include <asm/mach/time.h> |
34 | #include <asm/gpio.h> | 33 | #include <asm/gpio.h> |
35 | 34 | ||
35 | #define NSLU2_SDA_PIN 7 | ||
36 | #define NSLU2_SCL_PIN 6 | ||
37 | |||
38 | /* NSLU2 Timer */ | ||
39 | #define NSLU2_FREQ 66000000 | ||
40 | |||
41 | /* Buttons */ | ||
42 | #define NSLU2_PB_GPIO 5 /* power button */ | ||
43 | #define NSLU2_PO_GPIO 8 /* power off */ | ||
44 | #define NSLU2_RB_GPIO 12 /* reset button */ | ||
45 | |||
46 | /* Buzzer */ | ||
47 | #define NSLU2_GPIO_BUZZ 4 | ||
48 | |||
49 | /* LEDs */ | ||
50 | #define NSLU2_LED_RED_GPIO 0 | ||
51 | #define NSLU2_LED_GRN_GPIO 1 | ||
52 | #define NSLU2_LED_DISK1_GPIO 3 | ||
53 | #define NSLU2_LED_DISK2_GPIO 2 | ||
54 | |||
36 | static struct flash_platform_data nslu2_flash_data = { | 55 | static struct flash_platform_data nslu2_flash_data = { |
37 | .map_name = "cfi_probe", | 56 | .map_name = "cfi_probe", |
38 | .width = 2, | 57 | .width = 2, |
diff --git a/arch/arm/mach-lh7a40x/clocks.c b/arch/arm/mach-lh7a40x/clocks.c index 6182f5410b4d..fcaf876f19b6 100644 --- a/arch/arm/mach-lh7a40x/clocks.c +++ b/arch/arm/mach-lh7a40x/clocks.c | |||
@@ -7,8 +7,6 @@ | |||
7 | * version 2 as published by the Free Software Foundation. | 7 | * version 2 as published by the Free Software Foundation. |
8 | * | 8 | * |
9 | */ | 9 | */ |
10 | |||
11 | #include <linux/cpufreq.h> | ||
12 | #include <mach/hardware.h> | 10 | #include <mach/hardware.h> |
13 | #include <mach/clocks.h> | 11 | #include <mach/clocks.h> |
14 | #include <linux/err.h> | 12 | #include <linux/err.h> |
@@ -31,12 +29,6 @@ struct clk { | |||
31 | #define HCLKDIV(c) (((c) >> 0) & 0x02) | 29 | #define HCLKDIV(c) (((c) >> 0) & 0x02) |
32 | #define PCLKDIV(c) (((c) >> 16) & 0x03) | 30 | #define PCLKDIV(c) (((c) >> 16) & 0x03) |
33 | 31 | ||
34 | unsigned int cpufreq_get (unsigned int cpu) /* in kHz */ | ||
35 | { | ||
36 | return fclkfreq_get ()/1000; | ||
37 | } | ||
38 | EXPORT_SYMBOL(cpufreq_get); | ||
39 | |||
40 | unsigned int fclkfreq_get (void) | 32 | unsigned int fclkfreq_get (void) |
41 | { | 33 | { |
42 | unsigned int clkset = CSC_CLKSET; | 34 | unsigned int clkset = CSC_CLKSET; |
diff --git a/arch/arm/mach-nomadik/board-nhk8815.c b/arch/arm/mach-nomadik/board-nhk8815.c index 116394484e71..9438bf6613a3 100644 --- a/arch/arm/mach-nomadik/board-nhk8815.c +++ b/arch/arm/mach-nomadik/board-nhk8815.c | |||
@@ -18,6 +18,7 @@ | |||
18 | #include <linux/gpio.h> | 18 | #include <linux/gpio.h> |
19 | #include <linux/mtd/mtd.h> | 19 | #include <linux/mtd/mtd.h> |
20 | #include <linux/mtd/nand.h> | 20 | #include <linux/mtd/nand.h> |
21 | #include <linux/mtd/onenand.h> | ||
21 | #include <linux/mtd/partitions.h> | 22 | #include <linux/mtd/partitions.h> |
22 | #include <linux/io.h> | 23 | #include <linux/io.h> |
23 | #include <asm/sizes.h> | 24 | #include <asm/sizes.h> |
@@ -149,7 +150,7 @@ static struct mtd_partition nhk8815_onenand_partitions[] = { | |||
149 | } | 150 | } |
150 | }; | 151 | }; |
151 | 152 | ||
152 | static struct flash_platform_data nhk8815_onenand_data = { | 153 | static struct onenand_platform_data nhk8815_onenand_data = { |
153 | .parts = nhk8815_onenand_partitions, | 154 | .parts = nhk8815_onenand_partitions, |
154 | .nr_parts = ARRAY_SIZE(nhk8815_onenand_partitions), | 155 | .nr_parts = ARRAY_SIZE(nhk8815_onenand_partitions), |
155 | }; | 156 | }; |
@@ -163,7 +164,7 @@ static struct resource nhk8815_onenand_resource[] = { | |||
163 | }; | 164 | }; |
164 | 165 | ||
165 | static struct platform_device nhk8815_onenand_device = { | 166 | static struct platform_device nhk8815_onenand_device = { |
166 | .name = "onenand", | 167 | .name = "onenand-flash", |
167 | .id = -1, | 168 | .id = -1, |
168 | .dev = { | 169 | .dev = { |
169 | .platform_data = &nhk8815_onenand_data, | 170 | .platform_data = &nhk8815_onenand_data, |
@@ -174,10 +175,10 @@ static struct platform_device nhk8815_onenand_device = { | |||
174 | 175 | ||
175 | static void __init nhk8815_onenand_init(void) | 176 | static void __init nhk8815_onenand_init(void) |
176 | { | 177 | { |
177 | #ifdef CONFIG_ONENAND | 178 | #ifdef CONFIG_MTD_ONENAND |
178 | /* Set up SMCS0 for OneNand */ | 179 | /* Set up SMCS0 for OneNand */ |
179 | writel(0x000030db, FSMC_BCR0); | 180 | writel(0x000030db, FSMC_BCR(0)); |
180 | writel(0x02100551, FSMC_BTR0); | 181 | writel(0x02100551, FSMC_BTR(0)); |
181 | #endif | 182 | #endif |
182 | } | 183 | } |
183 | 184 | ||
diff --git a/arch/arm/mach-ns9xxx/irq.c b/arch/arm/mach-ns9xxx/irq.c index feb0e54a91de..038f24d47023 100644 --- a/arch/arm/mach-ns9xxx/irq.c +++ b/arch/arm/mach-ns9xxx/irq.c | |||
@@ -66,7 +66,7 @@ static void handle_prio_irq(unsigned int irq, struct irq_desc *desc) | |||
66 | struct irqaction *action; | 66 | struct irqaction *action; |
67 | irqreturn_t action_ret; | 67 | irqreturn_t action_ret; |
68 | 68 | ||
69 | spin_lock(&desc->lock); | 69 | raw_spin_lock(&desc->lock); |
70 | 70 | ||
71 | BUG_ON(desc->status & IRQ_INPROGRESS); | 71 | BUG_ON(desc->status & IRQ_INPROGRESS); |
72 | 72 | ||
@@ -78,7 +78,7 @@ static void handle_prio_irq(unsigned int irq, struct irq_desc *desc) | |||
78 | goto out_mask; | 78 | goto out_mask; |
79 | 79 | ||
80 | desc->status |= IRQ_INPROGRESS; | 80 | desc->status |= IRQ_INPROGRESS; |
81 | spin_unlock(&desc->lock); | 81 | raw_spin_unlock(&desc->lock); |
82 | 82 | ||
83 | action_ret = handle_IRQ_event(irq, action); | 83 | action_ret = handle_IRQ_event(irq, action); |
84 | 84 | ||
@@ -87,7 +87,7 @@ static void handle_prio_irq(unsigned int irq, struct irq_desc *desc) | |||
87 | * Maybe this function should go to kernel/irq/chip.c? */ | 87 | * Maybe this function should go to kernel/irq/chip.c? */ |
88 | note_interrupt(irq, desc, action_ret); | 88 | note_interrupt(irq, desc, action_ret); |
89 | 89 | ||
90 | spin_lock(&desc->lock); | 90 | raw_spin_lock(&desc->lock); |
91 | desc->status &= ~IRQ_INPROGRESS; | 91 | desc->status &= ~IRQ_INPROGRESS; |
92 | 92 | ||
93 | if (desc->status & IRQ_DISABLED) | 93 | if (desc->status & IRQ_DISABLED) |
@@ -97,7 +97,7 @@ out_mask: | |||
97 | /* ack unconditionally to unmask lower prio irqs */ | 97 | /* ack unconditionally to unmask lower prio irqs */ |
98 | desc->chip->ack(irq); | 98 | desc->chip->ack(irq); |
99 | 99 | ||
100 | spin_unlock(&desc->lock); | 100 | raw_spin_unlock(&desc->lock); |
101 | } | 101 | } |
102 | #define handle_irq handle_prio_irq | 102 | #define handle_irq handle_prio_irq |
103 | #endif | 103 | #endif |
diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile index 87e539aa8ad9..9ce17f13d3f1 100644 --- a/arch/arm/mach-omap1/Makefile +++ b/arch/arm/mach-omap1/Makefile | |||
@@ -3,7 +3,8 @@ | |||
3 | # | 3 | # |
4 | 4 | ||
5 | # Common support | 5 | # Common support |
6 | obj-y := io.o id.o sram.o clock.o irq.o mux.o serial.o devices.o | 6 | obj-y := io.o id.o sram.o irq.o mux.o serial.o devices.o |
7 | obj-y += clock.o clock_data.o opp_data.o | ||
7 | 8 | ||
8 | obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o | 9 | obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o |
9 | 10 | ||
@@ -17,6 +18,9 @@ obj-$(CONFIG_PM) += pm.o sleep.o | |||
17 | obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o | 18 | obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o |
18 | mailbox_mach-objs := mailbox.o | 19 | mailbox_mach-objs := mailbox.o |
19 | 20 | ||
21 | i2c-omap-$(CONFIG_I2C_OMAP) := i2c.o | ||
22 | obj-y += $(i2c-omap-m) $(i2c-omap-y) | ||
23 | |||
20 | led-y := leds.o | 24 | led-y := leds.o |
21 | 25 | ||
22 | # Specific board support | 26 | # Specific board support |
@@ -48,3 +52,7 @@ led-$(CONFIG_MACH_OMAP_INNOVATOR) += leds-innovator.o | |||
48 | led-$(CONFIG_MACH_OMAP_PERSEUS2) += leds-h2p2-debug.o | 52 | led-$(CONFIG_MACH_OMAP_PERSEUS2) += leds-h2p2-debug.o |
49 | led-$(CONFIG_MACH_OMAP_OSK) += leds-osk.o | 53 | led-$(CONFIG_MACH_OMAP_OSK) += leds-osk.o |
50 | obj-$(CONFIG_LEDS) += $(led-y) | 54 | obj-$(CONFIG_LEDS) += $(led-y) |
55 | |||
56 | ifneq ($(CONFIG_FB_OMAP),) | ||
57 | obj-y += lcd_dma.o | ||
58 | endif | ||
diff --git a/arch/arm/mach-omap1/board-fsample.c b/arch/arm/mach-omap1/board-fsample.c index f4b72c1654f5..7e70c3c08da6 100644 --- a/arch/arm/mach-omap1/board-fsample.c +++ b/arch/arm/mach-omap1/board-fsample.c | |||
@@ -19,6 +19,7 @@ | |||
19 | #include <linux/mtd/nand.h> | 19 | #include <linux/mtd/nand.h> |
20 | #include <linux/mtd/partitions.h> | 20 | #include <linux/mtd/partitions.h> |
21 | #include <linux/input.h> | 21 | #include <linux/input.h> |
22 | #include <linux/smc91x.h> | ||
22 | 23 | ||
23 | #include <mach/hardware.h> | 24 | #include <mach/hardware.h> |
24 | #include <asm/mach-types.h> | 25 | #include <asm/mach-types.h> |
@@ -30,7 +31,6 @@ | |||
30 | #include <mach/gpio.h> | 31 | #include <mach/gpio.h> |
31 | #include <plat/mux.h> | 32 | #include <plat/mux.h> |
32 | #include <plat/fpga.h> | 33 | #include <plat/fpga.h> |
33 | #include <plat/nand.h> | ||
34 | #include <plat/keypad.h> | 34 | #include <plat/keypad.h> |
35 | #include <plat/common.h> | 35 | #include <plat/common.h> |
36 | #include <plat/board.h> | 36 | #include <plat/board.h> |
@@ -100,6 +100,12 @@ static int fsample_keymap[] = { | |||
100 | 0 | 100 | 0 |
101 | }; | 101 | }; |
102 | 102 | ||
103 | static struct smc91x_platdata smc91x_info = { | ||
104 | .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, | ||
105 | .leda = RPC_LED_100_10, | ||
106 | .ledb = RPC_LED_TX_RX, | ||
107 | }; | ||
108 | |||
103 | static struct resource smc91x_resources[] = { | 109 | static struct resource smc91x_resources[] = { |
104 | [0] = { | 110 | [0] = { |
105 | .start = H2P2_DBG_FPGA_ETHR_START, /* Physical */ | 111 | .start = H2P2_DBG_FPGA_ETHR_START, /* Physical */ |
@@ -167,8 +173,40 @@ static struct platform_device nor_device = { | |||
167 | .resource = &nor_resource, | 173 | .resource = &nor_resource, |
168 | }; | 174 | }; |
169 | 175 | ||
170 | static struct omap_nand_platform_data nand_data = { | 176 | static void nand_cmd_ctl(struct mtd_info *mtd, int cmd, unsigned int ctrl) |
171 | .options = NAND_SAMSUNG_LP_OPTIONS, | 177 | { |
178 | struct nand_chip *this = mtd->priv; | ||
179 | unsigned long mask; | ||
180 | |||
181 | if (cmd == NAND_CMD_NONE) | ||
182 | return; | ||
183 | |||
184 | mask = (ctrl & NAND_CLE) ? 0x02 : 0; | ||
185 | if (ctrl & NAND_ALE) | ||
186 | mask |= 0x04; | ||
187 | writeb(cmd, (unsigned long)this->IO_ADDR_W | mask); | ||
188 | } | ||
189 | |||
190 | #define FSAMPLE_NAND_RB_GPIO_PIN 62 | ||
191 | |||
192 | static int nand_dev_ready(struct mtd_info *mtd) | ||
193 | { | ||
194 | return gpio_get_value(FSAMPLE_NAND_RB_GPIO_PIN); | ||
195 | } | ||
196 | |||
197 | static const char *part_probes[] = { "cmdlinepart", NULL }; | ||
198 | |||
199 | static struct platform_nand_data nand_data = { | ||
200 | .chip = { | ||
201 | .nr_chips = 1, | ||
202 | .chip_offset = 0, | ||
203 | .options = NAND_SAMSUNG_LP_OPTIONS, | ||
204 | .part_probe_types = part_probes, | ||
205 | }, | ||
206 | .ctrl = { | ||
207 | .cmd_ctrl = nand_cmd_ctl, | ||
208 | .dev_ready = nand_dev_ready, | ||
209 | }, | ||
172 | }; | 210 | }; |
173 | 211 | ||
174 | static struct resource nand_resource = { | 212 | static struct resource nand_resource = { |
@@ -178,7 +216,7 @@ static struct resource nand_resource = { | |||
178 | }; | 216 | }; |
179 | 217 | ||
180 | static struct platform_device nand_device = { | 218 | static struct platform_device nand_device = { |
181 | .name = "omapnand", | 219 | .name = "gen_nand", |
182 | .id = 0, | 220 | .id = 0, |
183 | .dev = { | 221 | .dev = { |
184 | .platform_data = &nand_data, | 222 | .platform_data = &nand_data, |
@@ -190,6 +228,9 @@ static struct platform_device nand_device = { | |||
190 | static struct platform_device smc91x_device = { | 228 | static struct platform_device smc91x_device = { |
191 | .name = "smc91x", | 229 | .name = "smc91x", |
192 | .id = 0, | 230 | .id = 0, |
231 | .dev = { | ||
232 | .platform_data = &smc91x_info, | ||
233 | }, | ||
193 | .num_resources = ARRAY_SIZE(smc91x_resources), | 234 | .num_resources = ARRAY_SIZE(smc91x_resources), |
194 | .resource = smc91x_resources, | 235 | .resource = smc91x_resources, |
195 | }; | 236 | }; |
@@ -233,13 +274,6 @@ static struct platform_device *devices[] __initdata = { | |||
233 | &lcd_device, | 274 | &lcd_device, |
234 | }; | 275 | }; |
235 | 276 | ||
236 | #define P2_NAND_RB_GPIO_PIN 62 | ||
237 | |||
238 | static int nand_dev_ready(struct omap_nand_platform_data *data) | ||
239 | { | ||
240 | return gpio_get_value(P2_NAND_RB_GPIO_PIN); | ||
241 | } | ||
242 | |||
243 | static struct omap_lcd_config fsample_lcd_config __initdata = { | 277 | static struct omap_lcd_config fsample_lcd_config __initdata = { |
244 | .ctrl_name = "internal", | 278 | .ctrl_name = "internal", |
245 | }; | 279 | }; |
@@ -250,9 +284,9 @@ static struct omap_board_config_kernel fsample_config[] = { | |||
250 | 284 | ||
251 | static void __init omap_fsample_init(void) | 285 | static void __init omap_fsample_init(void) |
252 | { | 286 | { |
253 | if (gpio_request(P2_NAND_RB_GPIO_PIN, "NAND ready") < 0) | 287 | if (gpio_request(FSAMPLE_NAND_RB_GPIO_PIN, "NAND ready") < 0) |
254 | BUG(); | 288 | BUG(); |
255 | nand_data.dev_ready = nand_dev_ready; | 289 | gpio_direction_input(FSAMPLE_NAND_RB_GPIO_PIN); |
256 | 290 | ||
257 | omap_cfg_reg(L3_1610_FLASH_CS2B_OE); | 291 | omap_cfg_reg(L3_1610_FLASH_CS2B_OE); |
258 | omap_cfg_reg(M8_1610_FLASH_CS2B_WE); | 292 | omap_cfg_reg(M8_1610_FLASH_CS2B_WE); |
diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c index 89ba8ec4bbf4..fa7cecea19f9 100644 --- a/arch/arm/mach-omap1/board-h2.c +++ b/arch/arm/mach-omap1/board-h2.c | |||
@@ -28,6 +28,7 @@ | |||
28 | #include <linux/mtd/partitions.h> | 28 | #include <linux/mtd/partitions.h> |
29 | #include <linux/input.h> | 29 | #include <linux/input.h> |
30 | #include <linux/i2c/tps65010.h> | 30 | #include <linux/i2c/tps65010.h> |
31 | #include <linux/smc91x.h> | ||
31 | 32 | ||
32 | #include <mach/hardware.h> | 33 | #include <mach/hardware.h> |
33 | #include <asm/gpio.h> | 34 | #include <asm/gpio.h> |
@@ -40,7 +41,6 @@ | |||
40 | #include <plat/mux.h> | 41 | #include <plat/mux.h> |
41 | #include <plat/dma.h> | 42 | #include <plat/dma.h> |
42 | #include <plat/tc.h> | 43 | #include <plat/tc.h> |
43 | #include <plat/nand.h> | ||
44 | #include <plat/irda.h> | 44 | #include <plat/irda.h> |
45 | #include <plat/usb.h> | 45 | #include <plat/usb.h> |
46 | #include <plat/keypad.h> | 46 | #include <plat/keypad.h> |
@@ -179,11 +179,43 @@ static struct mtd_partition h2_nand_partitions[] = { | |||
179 | }, | 179 | }, |
180 | }; | 180 | }; |
181 | 181 | ||
182 | /* dip switches control NAND chip access: 8 bit, 16 bit, or neither */ | 182 | static void h2_nand_cmd_ctl(struct mtd_info *mtd, int cmd, unsigned int ctrl) |
183 | static struct omap_nand_platform_data h2_nand_data = { | 183 | { |
184 | .options = NAND_SAMSUNG_LP_OPTIONS, | 184 | struct nand_chip *this = mtd->priv; |
185 | .parts = h2_nand_partitions, | 185 | unsigned long mask; |
186 | .nr_parts = ARRAY_SIZE(h2_nand_partitions), | 186 | |
187 | if (cmd == NAND_CMD_NONE) | ||
188 | return; | ||
189 | |||
190 | mask = (ctrl & NAND_CLE) ? 0x02 : 0; | ||
191 | if (ctrl & NAND_ALE) | ||
192 | mask |= 0x04; | ||
193 | writeb(cmd, (unsigned long)this->IO_ADDR_W | mask); | ||
194 | } | ||
195 | |||
196 | #define H2_NAND_RB_GPIO_PIN 62 | ||
197 | |||
198 | static int h2_nand_dev_ready(struct mtd_info *mtd) | ||
199 | { | ||
200 | return gpio_get_value(H2_NAND_RB_GPIO_PIN); | ||
201 | } | ||
202 | |||
203 | static const char *h2_part_probes[] = { "cmdlinepart", NULL }; | ||
204 | |||
205 | struct platform_nand_data h2_nand_platdata = { | ||
206 | .chip = { | ||
207 | .nr_chips = 1, | ||
208 | .chip_offset = 0, | ||
209 | .nr_partitions = ARRAY_SIZE(h2_nand_partitions), | ||
210 | .partitions = h2_nand_partitions, | ||
211 | .options = NAND_SAMSUNG_LP_OPTIONS, | ||
212 | .part_probe_types = h2_part_probes, | ||
213 | }, | ||
214 | .ctrl = { | ||
215 | .cmd_ctrl = h2_nand_cmd_ctl, | ||
216 | .dev_ready = h2_nand_dev_ready, | ||
217 | |||
218 | }, | ||
187 | }; | 219 | }; |
188 | 220 | ||
189 | static struct resource h2_nand_resource = { | 221 | static struct resource h2_nand_resource = { |
@@ -191,15 +223,21 @@ static struct resource h2_nand_resource = { | |||
191 | }; | 223 | }; |
192 | 224 | ||
193 | static struct platform_device h2_nand_device = { | 225 | static struct platform_device h2_nand_device = { |
194 | .name = "omapnand", | 226 | .name = "gen_nand", |
195 | .id = 0, | 227 | .id = 0, |
196 | .dev = { | 228 | .dev = { |
197 | .platform_data = &h2_nand_data, | 229 | .platform_data = &h2_nand_platdata, |
198 | }, | 230 | }, |
199 | .num_resources = 1, | 231 | .num_resources = 1, |
200 | .resource = &h2_nand_resource, | 232 | .resource = &h2_nand_resource, |
201 | }; | 233 | }; |
202 | 234 | ||
235 | static struct smc91x_platdata h2_smc91x_info = { | ||
236 | .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, | ||
237 | .leda = RPC_LED_100_10, | ||
238 | .ledb = RPC_LED_TX_RX, | ||
239 | }; | ||
240 | |||
203 | static struct resource h2_smc91x_resources[] = { | 241 | static struct resource h2_smc91x_resources[] = { |
204 | [0] = { | 242 | [0] = { |
205 | .start = OMAP1610_ETHR_START, /* Physical */ | 243 | .start = OMAP1610_ETHR_START, /* Physical */ |
@@ -216,6 +254,9 @@ static struct resource h2_smc91x_resources[] = { | |||
216 | static struct platform_device h2_smc91x_device = { | 254 | static struct platform_device h2_smc91x_device = { |
217 | .name = "smc91x", | 255 | .name = "smc91x", |
218 | .id = 0, | 256 | .id = 0, |
257 | .dev = { | ||
258 | .platform_data = &h2_smc91x_info, | ||
259 | }, | ||
219 | .num_resources = ARRAY_SIZE(h2_smc91x_resources), | 260 | .num_resources = ARRAY_SIZE(h2_smc91x_resources), |
220 | .resource = h2_smc91x_resources, | 261 | .resource = h2_smc91x_resources, |
221 | }; | 262 | }; |
@@ -368,8 +409,6 @@ static struct omap_board_config_kernel h2_config[] __initdata = { | |||
368 | { OMAP_TAG_LCD, &h2_lcd_config }, | 409 | { OMAP_TAG_LCD, &h2_lcd_config }, |
369 | }; | 410 | }; |
370 | 411 | ||
371 | #define H2_NAND_RB_GPIO_PIN 62 | ||
372 | |||
373 | static void __init h2_init(void) | 412 | static void __init h2_init(void) |
374 | { | 413 | { |
375 | /* Here we assume the NOR boot config: NOR on CS3 (possibly swapped | 414 | /* Here we assume the NOR boot config: NOR on CS3 (possibly swapped |
diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c index f5cc0a730524..6a7f9c391cf1 100644 --- a/arch/arm/mach-omap1/board-h3.c +++ b/arch/arm/mach-omap1/board-h3.c | |||
@@ -28,6 +28,7 @@ | |||
28 | #include <linux/input.h> | 28 | #include <linux/input.h> |
29 | #include <linux/spi/spi.h> | 29 | #include <linux/spi/spi.h> |
30 | #include <linux/i2c/tps65010.h> | 30 | #include <linux/i2c/tps65010.h> |
31 | #include <linux/smc91x.h> | ||
31 | 32 | ||
32 | #include <asm/setup.h> | 33 | #include <asm/setup.h> |
33 | #include <asm/page.h> | 34 | #include <asm/page.h> |
@@ -42,7 +43,6 @@ | |||
42 | #include <mach/irqs.h> | 43 | #include <mach/irqs.h> |
43 | #include <plat/mux.h> | 44 | #include <plat/mux.h> |
44 | #include <plat/tc.h> | 45 | #include <plat/tc.h> |
45 | #include <plat/nand.h> | ||
46 | #include <plat/usb.h> | 46 | #include <plat/usb.h> |
47 | #include <plat/keypad.h> | 47 | #include <plat/keypad.h> |
48 | #include <plat/dma.h> | 48 | #include <plat/dma.h> |
@@ -181,11 +181,43 @@ static struct mtd_partition nand_partitions[] = { | |||
181 | }, | 181 | }, |
182 | }; | 182 | }; |
183 | 183 | ||
184 | /* dip switches control NAND chip access: 8 bit, 16 bit, or neither */ | 184 | static void nand_cmd_ctl(struct mtd_info *mtd, int cmd, unsigned int ctrl) |
185 | static struct omap_nand_platform_data nand_data = { | 185 | { |
186 | .options = NAND_SAMSUNG_LP_OPTIONS, | 186 | struct nand_chip *this = mtd->priv; |
187 | .parts = nand_partitions, | 187 | unsigned long mask; |
188 | .nr_parts = ARRAY_SIZE(nand_partitions), | 188 | |
189 | if (cmd == NAND_CMD_NONE) | ||
190 | return; | ||
191 | |||
192 | mask = (ctrl & NAND_CLE) ? 0x02 : 0; | ||
193 | if (ctrl & NAND_ALE) | ||
194 | mask |= 0x04; | ||
195 | writeb(cmd, (unsigned long)this->IO_ADDR_W | mask); | ||
196 | } | ||
197 | |||
198 | #define H3_NAND_RB_GPIO_PIN 10 | ||
199 | |||
200 | static int nand_dev_ready(struct mtd_info *mtd) | ||
201 | { | ||
202 | return gpio_get_value(H3_NAND_RB_GPIO_PIN); | ||
203 | } | ||
204 | |||
205 | static const char *part_probes[] = { "cmdlinepart", NULL }; | ||
206 | |||
207 | struct platform_nand_data nand_platdata = { | ||
208 | .chip = { | ||
209 | .nr_chips = 1, | ||
210 | .chip_offset = 0, | ||
211 | .nr_partitions = ARRAY_SIZE(nand_partitions), | ||
212 | .partitions = nand_partitions, | ||
213 | .options = NAND_SAMSUNG_LP_OPTIONS, | ||
214 | .part_probe_types = part_probes, | ||
215 | }, | ||
216 | .ctrl = { | ||
217 | .cmd_ctrl = nand_cmd_ctl, | ||
218 | .dev_ready = nand_dev_ready, | ||
219 | |||
220 | }, | ||
189 | }; | 221 | }; |
190 | 222 | ||
191 | static struct resource nand_resource = { | 223 | static struct resource nand_resource = { |
@@ -193,15 +225,21 @@ static struct resource nand_resource = { | |||
193 | }; | 225 | }; |
194 | 226 | ||
195 | static struct platform_device nand_device = { | 227 | static struct platform_device nand_device = { |
196 | .name = "omapnand", | 228 | .name = "gen_nand", |
197 | .id = 0, | 229 | .id = 0, |
198 | .dev = { | 230 | .dev = { |
199 | .platform_data = &nand_data, | 231 | .platform_data = &nand_platdata, |
200 | }, | 232 | }, |
201 | .num_resources = 1, | 233 | .num_resources = 1, |
202 | .resource = &nand_resource, | 234 | .resource = &nand_resource, |
203 | }; | 235 | }; |
204 | 236 | ||
237 | static struct smc91x_platdata smc91x_info = { | ||
238 | .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, | ||
239 | .leda = RPC_LED_100_10, | ||
240 | .ledb = RPC_LED_TX_RX, | ||
241 | }; | ||
242 | |||
205 | static struct resource smc91x_resources[] = { | 243 | static struct resource smc91x_resources[] = { |
206 | [0] = { | 244 | [0] = { |
207 | .start = OMAP1710_ETHR_START, /* Physical */ | 245 | .start = OMAP1710_ETHR_START, /* Physical */ |
@@ -218,6 +256,9 @@ static struct resource smc91x_resources[] = { | |||
218 | static struct platform_device smc91x_device = { | 256 | static struct platform_device smc91x_device = { |
219 | .name = "smc91x", | 257 | .name = "smc91x", |
220 | .id = 0, | 258 | .id = 0, |
259 | .dev = { | ||
260 | .platform_data = &smc91x_info, | ||
261 | }, | ||
221 | .num_resources = ARRAY_SIZE(smc91x_resources), | 262 | .num_resources = ARRAY_SIZE(smc91x_resources), |
222 | .resource = smc91x_resources, | 263 | .resource = smc91x_resources, |
223 | }; | 264 | }; |
@@ -332,13 +373,6 @@ static struct i2c_board_info __initdata h3_i2c_board_info[] = { | |||
332 | }, | 373 | }, |
333 | }; | 374 | }; |
334 | 375 | ||
335 | #define H3_NAND_RB_GPIO_PIN 10 | ||
336 | |||
337 | static int nand_dev_ready(struct omap_nand_platform_data *data) | ||
338 | { | ||
339 | return gpio_get_value(H3_NAND_RB_GPIO_PIN); | ||
340 | } | ||
341 | |||
342 | static void __init h3_init(void) | 376 | static void __init h3_init(void) |
343 | { | 377 | { |
344 | /* Here we assume the NOR boot config: NOR on CS3 (possibly swapped | 378 | /* Here we assume the NOR boot config: NOR on CS3 (possibly swapped |
@@ -356,7 +390,7 @@ static void __init h3_init(void) | |||
356 | nand_resource.end += SZ_4K - 1; | 390 | nand_resource.end += SZ_4K - 1; |
357 | if (gpio_request(H3_NAND_RB_GPIO_PIN, "NAND ready") < 0) | 391 | if (gpio_request(H3_NAND_RB_GPIO_PIN, "NAND ready") < 0) |
358 | BUG(); | 392 | BUG(); |
359 | nand_data.dev_ready = nand_dev_ready; | 393 | gpio_direction_input(H3_NAND_RB_GPIO_PIN); |
360 | 394 | ||
361 | /* GPIO10 Func_MUX_CTRL reg bit 29:27, Configure V2 to mode1 as GPIO */ | 395 | /* GPIO10 Func_MUX_CTRL reg bit 29:27, Configure V2 to mode1 as GPIO */ |
362 | /* GPIO10 pullup/down register, Enable pullup on GPIO10 */ | 396 | /* GPIO10 pullup/down register, Enable pullup on GPIO10 */ |
diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c index 5f28a5ceacac..e36639f66150 100644 --- a/arch/arm/mach-omap1/board-htcherald.c +++ b/arch/arm/mach-omap1/board-htcherald.c | |||
@@ -39,6 +39,7 @@ | |||
39 | #include <plat/common.h> | 39 | #include <plat/common.h> |
40 | #include <plat/board.h> | 40 | #include <plat/board.h> |
41 | #include <plat/keypad.h> | 41 | #include <plat/keypad.h> |
42 | #include <plat/usb.h> | ||
42 | 43 | ||
43 | #include <mach/irqs.h> | 44 | #include <mach/irqs.h> |
44 | 45 | ||
@@ -140,6 +141,15 @@ static struct platform_device kp_device = { | |||
140 | .resource = kp_resources, | 141 | .resource = kp_resources, |
141 | }; | 142 | }; |
142 | 143 | ||
144 | /* USB Device */ | ||
145 | static struct omap_usb_config htcherald_usb_config __initdata = { | ||
146 | .otg = 0, | ||
147 | .register_host = 0, | ||
148 | .register_dev = 1, | ||
149 | .hmc_mode = 4, | ||
150 | .pins[0] = 2, | ||
151 | }; | ||
152 | |||
143 | /* LCD Device resources */ | 153 | /* LCD Device resources */ |
144 | static struct platform_device lcd_device = { | 154 | static struct platform_device lcd_device = { |
145 | .name = "lcd_htcherald", | 155 | .name = "lcd_htcherald", |
@@ -214,6 +224,57 @@ static void __init htcherald_disable_watchdog(void) | |||
214 | } | 224 | } |
215 | } | 225 | } |
216 | 226 | ||
227 | #define HTCHERALD_GPIO_USB_EN1 33 | ||
228 | #define HTCHERALD_GPIO_USB_EN2 73 | ||
229 | #define HTCHERALD_GPIO_USB_DM 35 | ||
230 | #define HTCHERALD_GPIO_USB_DP 36 | ||
231 | |||
232 | static void __init htcherald_usb_enable(void) | ||
233 | { | ||
234 | unsigned int tries = 20; | ||
235 | unsigned int value = 0; | ||
236 | |||
237 | /* Request the GPIOs we need to control here */ | ||
238 | if (gpio_request(HTCHERALD_GPIO_USB_EN1, "herald_usb") < 0) | ||
239 | goto err1; | ||
240 | |||
241 | if (gpio_request(HTCHERALD_GPIO_USB_EN2, "herald_usb") < 0) | ||
242 | goto err2; | ||
243 | |||
244 | if (gpio_request(HTCHERALD_GPIO_USB_DM, "herald_usb") < 0) | ||
245 | goto err3; | ||
246 | |||
247 | if (gpio_request(HTCHERALD_GPIO_USB_DP, "herald_usb") < 0) | ||
248 | goto err4; | ||
249 | |||
250 | /* force USB_EN GPIO to 0 */ | ||
251 | do { | ||
252 | /* output low */ | ||
253 | gpio_direction_output(HTCHERALD_GPIO_USB_EN1, 0); | ||
254 | } while ((value = gpio_get_value(HTCHERALD_GPIO_USB_EN1)) == 1 && | ||
255 | --tries); | ||
256 | |||
257 | if (value == 1) | ||
258 | printk(KERN_WARNING "Unable to reset USB, trying to continue\n"); | ||
259 | |||
260 | gpio_direction_output(HTCHERALD_GPIO_USB_EN2, 0); /* output low */ | ||
261 | gpio_direction_input(HTCHERALD_GPIO_USB_DM); /* input */ | ||
262 | gpio_direction_input(HTCHERALD_GPIO_USB_DP); /* input */ | ||
263 | |||
264 | goto done; | ||
265 | |||
266 | err4: | ||
267 | gpio_free(HTCHERALD_GPIO_USB_DM); | ||
268 | err3: | ||
269 | gpio_free(HTCHERALD_GPIO_USB_EN2); | ||
270 | err2: | ||
271 | gpio_free(HTCHERALD_GPIO_USB_EN1); | ||
272 | err1: | ||
273 | printk(KERN_ERR "Unabled to request GPIO for USB\n"); | ||
274 | done: | ||
275 | printk(KERN_INFO "USB setup complete.\n"); | ||
276 | } | ||
277 | |||
217 | static void __init htcherald_init(void) | 278 | static void __init htcherald_init(void) |
218 | { | 279 | { |
219 | printk(KERN_INFO "HTC Herald init.\n"); | 280 | printk(KERN_INFO "HTC Herald init.\n"); |
@@ -225,6 +286,9 @@ static void __init htcherald_init(void) | |||
225 | platform_add_devices(devices, ARRAY_SIZE(devices)); | 286 | platform_add_devices(devices, ARRAY_SIZE(devices)); |
226 | 287 | ||
227 | htcherald_disable_watchdog(); | 288 | htcherald_disable_watchdog(); |
289 | |||
290 | htcherald_usb_enable(); | ||
291 | omap_usb_init(&htcherald_usb_config); | ||
228 | } | 292 | } |
229 | 293 | ||
230 | static void __init htcherald_init_irq(void) | 294 | static void __init htcherald_init_irq(void) |
diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c index cf0fdb9c182f..2133b006f6a3 100644 --- a/arch/arm/mach-omap1/board-innovator.c +++ b/arch/arm/mach-omap1/board-innovator.c | |||
@@ -23,6 +23,7 @@ | |||
23 | #include <linux/mtd/mtd.h> | 23 | #include <linux/mtd/mtd.h> |
24 | #include <linux/mtd/partitions.h> | 24 | #include <linux/mtd/partitions.h> |
25 | #include <linux/input.h> | 25 | #include <linux/input.h> |
26 | #include <linux/smc91x.h> | ||
26 | 27 | ||
27 | #include <mach/hardware.h> | 28 | #include <mach/hardware.h> |
28 | #include <asm/mach-types.h> | 29 | #include <asm/mach-types.h> |
@@ -142,6 +143,11 @@ static struct platform_device innovator_kp_device = { | |||
142 | .resource = innovator_kp_resources, | 143 | .resource = innovator_kp_resources, |
143 | }; | 144 | }; |
144 | 145 | ||
146 | static struct smc91x_platdata innovator_smc91x_info = { | ||
147 | .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, | ||
148 | .leda = RPC_LED_100_10, | ||
149 | .ledb = RPC_LED_TX_RX, | ||
150 | }; | ||
145 | 151 | ||
146 | #ifdef CONFIG_ARCH_OMAP15XX | 152 | #ifdef CONFIG_ARCH_OMAP15XX |
147 | 153 | ||
@@ -175,6 +181,9 @@ static struct resource innovator1510_smc91x_resources[] = { | |||
175 | static struct platform_device innovator1510_smc91x_device = { | 181 | static struct platform_device innovator1510_smc91x_device = { |
176 | .name = "smc91x", | 182 | .name = "smc91x", |
177 | .id = 0, | 183 | .id = 0, |
184 | .dev = { | ||
185 | .platform_data = &innovator_smc91x_info, | ||
186 | }, | ||
178 | .num_resources = ARRAY_SIZE(innovator1510_smc91x_resources), | 187 | .num_resources = ARRAY_SIZE(innovator1510_smc91x_resources), |
179 | .resource = innovator1510_smc91x_resources, | 188 | .resource = innovator1510_smc91x_resources, |
180 | }; | 189 | }; |
@@ -241,6 +250,9 @@ static struct resource innovator1610_smc91x_resources[] = { | |||
241 | static struct platform_device innovator1610_smc91x_device = { | 250 | static struct platform_device innovator1610_smc91x_device = { |
242 | .name = "smc91x", | 251 | .name = "smc91x", |
243 | .id = 0, | 252 | .id = 0, |
253 | .dev = { | ||
254 | .platform_data = &innovator_smc91x_info, | ||
255 | }, | ||
244 | .num_resources = ARRAY_SIZE(innovator1610_smc91x_resources), | 256 | .num_resources = ARRAY_SIZE(innovator1610_smc91x_resources), |
245 | .resource = innovator1610_smc91x_resources, | 257 | .resource = innovator1610_smc91x_resources, |
246 | }; | 258 | }; |
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c index 50c92c13e48a..ccea4f448e9a 100644 --- a/arch/arm/mach-omap1/board-osk.c +++ b/arch/arm/mach-omap1/board-osk.c | |||
@@ -33,6 +33,7 @@ | |||
33 | #include <linux/irq.h> | 33 | #include <linux/irq.h> |
34 | #include <linux/i2c.h> | 34 | #include <linux/i2c.h> |
35 | #include <linux/leds.h> | 35 | #include <linux/leds.h> |
36 | #include <linux/smc91x.h> | ||
36 | 37 | ||
37 | #include <linux/mtd/mtd.h> | 38 | #include <linux/mtd/mtd.h> |
38 | #include <linux/mtd/partitions.h> | 39 | #include <linux/mtd/partitions.h> |
@@ -115,6 +116,12 @@ static struct platform_device osk5912_flash_device = { | |||
115 | .resource = &osk_flash_resource, | 116 | .resource = &osk_flash_resource, |
116 | }; | 117 | }; |
117 | 118 | ||
119 | static struct smc91x_platdata osk5912_smc91x_info = { | ||
120 | .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, | ||
121 | .leda = RPC_LED_100_10, | ||
122 | .ledb = RPC_LED_TX_RX, | ||
123 | }; | ||
124 | |||
118 | static struct resource osk5912_smc91x_resources[] = { | 125 | static struct resource osk5912_smc91x_resources[] = { |
119 | [0] = { | 126 | [0] = { |
120 | .start = OMAP_OSK_ETHR_START, /* Physical */ | 127 | .start = OMAP_OSK_ETHR_START, /* Physical */ |
@@ -131,6 +138,9 @@ static struct resource osk5912_smc91x_resources[] = { | |||
131 | static struct platform_device osk5912_smc91x_device = { | 138 | static struct platform_device osk5912_smc91x_device = { |
132 | .name = "smc91x", | 139 | .name = "smc91x", |
133 | .id = -1, | 140 | .id = -1, |
141 | .dev = { | ||
142 | .platform_data = &osk5912_smc91x_info, | ||
143 | }, | ||
134 | .num_resources = ARRAY_SIZE(osk5912_smc91x_resources), | 144 | .num_resources = ARRAY_SIZE(osk5912_smc91x_resources), |
135 | .resource = osk5912_smc91x_resources, | 145 | .resource = osk5912_smc91x_resources, |
136 | }; | 146 | }; |
diff --git a/arch/arm/mach-omap1/board-perseus2.c b/arch/arm/mach-omap1/board-perseus2.c index ca7df1e93efc..1387a4f15da9 100644 --- a/arch/arm/mach-omap1/board-perseus2.c +++ b/arch/arm/mach-omap1/board-perseus2.c | |||
@@ -19,6 +19,7 @@ | |||
19 | #include <linux/mtd/nand.h> | 19 | #include <linux/mtd/nand.h> |
20 | #include <linux/mtd/partitions.h> | 20 | #include <linux/mtd/partitions.h> |
21 | #include <linux/input.h> | 21 | #include <linux/input.h> |
22 | #include <linux/smc91x.h> | ||
22 | 23 | ||
23 | #include <mach/hardware.h> | 24 | #include <mach/hardware.h> |
24 | #include <asm/mach-types.h> | 25 | #include <asm/mach-types.h> |
@@ -30,7 +31,6 @@ | |||
30 | #include <mach/gpio.h> | 31 | #include <mach/gpio.h> |
31 | #include <plat/mux.h> | 32 | #include <plat/mux.h> |
32 | #include <plat/fpga.h> | 33 | #include <plat/fpga.h> |
33 | #include <plat/nand.h> | ||
34 | #include <plat/keypad.h> | 34 | #include <plat/keypad.h> |
35 | #include <plat/common.h> | 35 | #include <plat/common.h> |
36 | #include <plat/board.h> | 36 | #include <plat/board.h> |
@@ -67,6 +67,12 @@ static int p2_keymap[] = { | |||
67 | 0 | 67 | 0 |
68 | }; | 68 | }; |
69 | 69 | ||
70 | static struct smc91x_platdata smc91x_info = { | ||
71 | .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, | ||
72 | .leda = RPC_LED_100_10, | ||
73 | .ledb = RPC_LED_TX_RX, | ||
74 | }; | ||
75 | |||
70 | static struct resource smc91x_resources[] = { | 76 | static struct resource smc91x_resources[] = { |
71 | [0] = { | 77 | [0] = { |
72 | .start = H2P2_DBG_FPGA_ETHR_START, /* Physical */ | 78 | .start = H2P2_DBG_FPGA_ETHR_START, /* Physical */ |
@@ -134,8 +140,40 @@ static struct platform_device nor_device = { | |||
134 | .resource = &nor_resource, | 140 | .resource = &nor_resource, |
135 | }; | 141 | }; |
136 | 142 | ||
137 | static struct omap_nand_platform_data nand_data = { | 143 | static void nand_cmd_ctl(struct mtd_info *mtd, int cmd, unsigned int ctrl) |
138 | .options = NAND_SAMSUNG_LP_OPTIONS, | 144 | { |
145 | struct nand_chip *this = mtd->priv; | ||
146 | unsigned long mask; | ||
147 | |||
148 | if (cmd == NAND_CMD_NONE) | ||
149 | return; | ||
150 | |||
151 | mask = (ctrl & NAND_CLE) ? 0x02 : 0; | ||
152 | if (ctrl & NAND_ALE) | ||
153 | mask |= 0x04; | ||
154 | writeb(cmd, (unsigned long)this->IO_ADDR_W | mask); | ||
155 | } | ||
156 | |||
157 | #define P2_NAND_RB_GPIO_PIN 62 | ||
158 | |||
159 | static int nand_dev_ready(struct mtd_info *mtd) | ||
160 | { | ||
161 | return gpio_get_value(P2_NAND_RB_GPIO_PIN); | ||
162 | } | ||
163 | |||
164 | static const char *part_probes[] = { "cmdlinepart", NULL }; | ||
165 | |||
166 | static struct platform_nand_data nand_data = { | ||
167 | .chip = { | ||
168 | .nr_chips = 1, | ||
169 | .chip_offset = 0, | ||
170 | .options = NAND_SAMSUNG_LP_OPTIONS, | ||
171 | .part_probe_types = part_probes, | ||
172 | }, | ||
173 | .ctrl = { | ||
174 | .cmd_ctrl = nand_cmd_ctl, | ||
175 | .dev_ready = nand_dev_ready, | ||
176 | }, | ||
139 | }; | 177 | }; |
140 | 178 | ||
141 | static struct resource nand_resource = { | 179 | static struct resource nand_resource = { |
@@ -145,7 +183,7 @@ static struct resource nand_resource = { | |||
145 | }; | 183 | }; |
146 | 184 | ||
147 | static struct platform_device nand_device = { | 185 | static struct platform_device nand_device = { |
148 | .name = "omapnand", | 186 | .name = "gen_nand", |
149 | .id = 0, | 187 | .id = 0, |
150 | .dev = { | 188 | .dev = { |
151 | .platform_data = &nand_data, | 189 | .platform_data = &nand_data, |
@@ -157,6 +195,9 @@ static struct platform_device nand_device = { | |||
157 | static struct platform_device smc91x_device = { | 195 | static struct platform_device smc91x_device = { |
158 | .name = "smc91x", | 196 | .name = "smc91x", |
159 | .id = 0, | 197 | .id = 0, |
198 | .dev = { | ||
199 | .platform_data = &smc91x_info, | ||
200 | }, | ||
160 | .num_resources = ARRAY_SIZE(smc91x_resources), | 201 | .num_resources = ARRAY_SIZE(smc91x_resources), |
161 | .resource = smc91x_resources, | 202 | .resource = smc91x_resources, |
162 | }; | 203 | }; |
@@ -201,13 +242,6 @@ static struct platform_device *devices[] __initdata = { | |||
201 | &lcd_device, | 242 | &lcd_device, |
202 | }; | 243 | }; |
203 | 244 | ||
204 | #define P2_NAND_RB_GPIO_PIN 62 | ||
205 | |||
206 | static int nand_dev_ready(struct omap_nand_platform_data *data) | ||
207 | { | ||
208 | return gpio_get_value(P2_NAND_RB_GPIO_PIN); | ||
209 | } | ||
210 | |||
211 | static struct omap_lcd_config perseus2_lcd_config __initdata = { | 245 | static struct omap_lcd_config perseus2_lcd_config __initdata = { |
212 | .ctrl_name = "internal", | 246 | .ctrl_name = "internal", |
213 | }; | 247 | }; |
@@ -220,7 +254,7 @@ static void __init omap_perseus2_init(void) | |||
220 | { | 254 | { |
221 | if (gpio_request(P2_NAND_RB_GPIO_PIN, "NAND ready") < 0) | 255 | if (gpio_request(P2_NAND_RB_GPIO_PIN, "NAND ready") < 0) |
222 | BUG(); | 256 | BUG(); |
223 | nand_data.dev_ready = nand_dev_ready; | 257 | gpio_direction_input(P2_NAND_RB_GPIO_PIN); |
224 | 258 | ||
225 | omap_cfg_reg(L3_1610_FLASH_CS2B_OE); | 259 | omap_cfg_reg(L3_1610_FLASH_CS2B_OE); |
226 | omap_cfg_reg(M8_1610_FLASH_CS2B_WE); | 260 | omap_cfg_reg(M8_1610_FLASH_CS2B_WE); |
diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c index 35c75c1bd0aa..169183537997 100644 --- a/arch/arm/mach-omap1/board-voiceblue.c +++ b/arch/arm/mach-omap1/board-voiceblue.c | |||
@@ -22,6 +22,7 @@ | |||
22 | #include <linux/reboot.h> | 22 | #include <linux/reboot.h> |
23 | #include <linux/serial_8250.h> | 23 | #include <linux/serial_8250.h> |
24 | #include <linux/serial_reg.h> | 24 | #include <linux/serial_reg.h> |
25 | #include <linux/smc91x.h> | ||
25 | 26 | ||
26 | #include <mach/hardware.h> | 27 | #include <mach/hardware.h> |
27 | #include <asm/mach-types.h> | 28 | #include <asm/mach-types.h> |
@@ -106,6 +107,12 @@ static struct platform_device voiceblue_flash_device = { | |||
106 | .resource = &voiceblue_flash_resource, | 107 | .resource = &voiceblue_flash_resource, |
107 | }; | 108 | }; |
108 | 109 | ||
110 | static struct smc91x_platdata voiceblue_smc91x_info = { | ||
111 | .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, | ||
112 | .leda = RPC_LED_100_10, | ||
113 | .ledb = RPC_LED_TX_RX, | ||
114 | }; | ||
115 | |||
109 | static struct resource voiceblue_smc91x_resources[] = { | 116 | static struct resource voiceblue_smc91x_resources[] = { |
110 | [0] = { | 117 | [0] = { |
111 | .start = OMAP_CS2_PHYS + 0x300, | 118 | .start = OMAP_CS2_PHYS + 0x300, |
@@ -122,6 +129,9 @@ static struct resource voiceblue_smc91x_resources[] = { | |||
122 | static struct platform_device voiceblue_smc91x_device = { | 129 | static struct platform_device voiceblue_smc91x_device = { |
123 | .name = "smc91x", | 130 | .name = "smc91x", |
124 | .id = 0, | 131 | .id = 0, |
132 | .dev = { | ||
133 | .platform_data = &voiceblue_smc91x_info, | ||
134 | }, | ||
125 | .num_resources = ARRAY_SIZE(voiceblue_smc91x_resources), | 135 | .num_resources = ARRAY_SIZE(voiceblue_smc91x_resources), |
126 | .resource = voiceblue_smc91x_resources, | 136 | .resource = voiceblue_smc91x_resources, |
127 | }; | 137 | }; |
diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c index 42cbe203da36..2ba9ab953731 100644 --- a/arch/arm/mach-omap1/clock.c +++ b/arch/arm/mach-omap1/clock.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * linux/arch/arm/mach-omap1/clock.c | 2 | * linux/arch/arm/mach-omap1/clock.c |
3 | * | 3 | * |
4 | * Copyright (C) 2004 - 2005 Nokia corporation | 4 | * Copyright (C) 2004 - 2005, 2009 Nokia corporation |
5 | * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> | 5 | * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> |
6 | * | 6 | * |
7 | * Modified to use omap shared clock framework by | 7 | * Modified to use omap shared clock framework by |
@@ -26,12 +26,17 @@ | |||
26 | #include <plat/usb.h> | 26 | #include <plat/usb.h> |
27 | #include <plat/clock.h> | 27 | #include <plat/clock.h> |
28 | #include <plat/sram.h> | 28 | #include <plat/sram.h> |
29 | 29 | #include <plat/clkdev_omap.h> | |
30 | static const struct clkops clkops_generic; | ||
31 | static const struct clkops clkops_uart; | ||
32 | static const struct clkops clkops_dspck; | ||
33 | 30 | ||
34 | #include "clock.h" | 31 | #include "clock.h" |
32 | #include "opp.h" | ||
33 | |||
34 | __u32 arm_idlect1_mask; | ||
35 | struct clk *api_ck_p, *ck_dpll1_p, *ck_ref_p; | ||
36 | |||
37 | /*------------------------------------------------------------------------- | ||
38 | * Omap1 specific clock functions | ||
39 | *-------------------------------------------------------------------------*/ | ||
35 | 40 | ||
36 | static int clk_omap1_dummy_enable(struct clk *clk) | 41 | static int clk_omap1_dummy_enable(struct clk *clk) |
37 | { | 42 | { |
@@ -42,134 +47,24 @@ static void clk_omap1_dummy_disable(struct clk *clk) | |||
42 | { | 47 | { |
43 | } | 48 | } |
44 | 49 | ||
45 | static const struct clkops clkops_dummy = { | 50 | const struct clkops clkops_dummy = { |
46 | .enable = clk_omap1_dummy_enable, | 51 | .enable = clk_omap1_dummy_enable, |
47 | .disable = clk_omap1_dummy_disable, | 52 | .disable = clk_omap1_dummy_disable, |
48 | }; | ||
49 | |||
50 | static struct clk dummy_ck = { | ||
51 | .name = "dummy", | ||
52 | .ops = &clkops_dummy, | ||
53 | .flags = RATE_FIXED, | ||
54 | }; | ||
55 | |||
56 | struct omap_clk { | ||
57 | u32 cpu; | ||
58 | struct clk_lookup lk; | ||
59 | }; | 53 | }; |
60 | 54 | ||
61 | #define CLK(dev, con, ck, cp) \ | 55 | /* XXX can be replaced with a fixed_divisor_recalc */ |
62 | { \ | 56 | unsigned long omap1_watchdog_recalc(struct clk *clk) |
63 | .cpu = cp, \ | ||
64 | .lk = { \ | ||
65 | .dev_id = dev, \ | ||
66 | .con_id = con, \ | ||
67 | .clk = ck, \ | ||
68 | }, \ | ||
69 | } | ||
70 | |||
71 | #define CK_310 (1 << 0) | ||
72 | #define CK_7XX (1 << 1) | ||
73 | #define CK_1510 (1 << 2) | ||
74 | #define CK_16XX (1 << 3) | ||
75 | |||
76 | static struct omap_clk omap_clks[] = { | ||
77 | /* non-ULPD clocks */ | ||
78 | CLK(NULL, "ck_ref", &ck_ref, CK_16XX | CK_1510 | CK_310 | CK_7XX), | ||
79 | CLK(NULL, "ck_dpll1", &ck_dpll1, CK_16XX | CK_1510 | CK_310), | ||
80 | /* CK_GEN1 clocks */ | ||
81 | CLK(NULL, "ck_dpll1out", &ck_dpll1out.clk, CK_16XX), | ||
82 | CLK(NULL, "ck_sossi", &sossi_ck, CK_16XX), | ||
83 | CLK(NULL, "arm_ck", &arm_ck, CK_16XX | CK_1510 | CK_310), | ||
84 | CLK(NULL, "armper_ck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310), | ||
85 | CLK(NULL, "arm_gpio_ck", &arm_gpio_ck, CK_1510 | CK_310), | ||
86 | CLK(NULL, "armxor_ck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX), | ||
87 | CLK(NULL, "armtim_ck", &armtim_ck.clk, CK_16XX | CK_1510 | CK_310), | ||
88 | CLK("omap_wdt", "fck", &armwdt_ck.clk, CK_16XX | CK_1510 | CK_310), | ||
89 | CLK("omap_wdt", "ick", &armper_ck.clk, CK_16XX), | ||
90 | CLK("omap_wdt", "ick", &dummy_ck, CK_1510 | CK_310), | ||
91 | CLK(NULL, "arminth_ck", &arminth_ck1510, CK_1510 | CK_310), | ||
92 | CLK(NULL, "arminth_ck", &arminth_ck16xx, CK_16XX), | ||
93 | /* CK_GEN2 clocks */ | ||
94 | CLK(NULL, "dsp_ck", &dsp_ck, CK_16XX | CK_1510 | CK_310), | ||
95 | CLK(NULL, "dspmmu_ck", &dspmmu_ck, CK_16XX | CK_1510 | CK_310), | ||
96 | CLK(NULL, "dspper_ck", &dspper_ck, CK_16XX | CK_1510 | CK_310), | ||
97 | CLK(NULL, "dspxor_ck", &dspxor_ck, CK_16XX | CK_1510 | CK_310), | ||
98 | CLK(NULL, "dsptim_ck", &dsptim_ck, CK_16XX | CK_1510 | CK_310), | ||
99 | /* CK_GEN3 clocks */ | ||
100 | CLK(NULL, "tc_ck", &tc_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX), | ||
101 | CLK(NULL, "tipb_ck", &tipb_ck, CK_1510 | CK_310), | ||
102 | CLK(NULL, "l3_ocpi_ck", &l3_ocpi_ck, CK_16XX | CK_7XX), | ||
103 | CLK(NULL, "tc1_ck", &tc1_ck, CK_16XX), | ||
104 | CLK(NULL, "tc2_ck", &tc2_ck, CK_16XX), | ||
105 | CLK(NULL, "dma_ck", &dma_ck, CK_16XX | CK_1510 | CK_310), | ||
106 | CLK(NULL, "dma_lcdfree_ck", &dma_lcdfree_ck, CK_16XX), | ||
107 | CLK(NULL, "api_ck", &api_ck.clk, CK_16XX | CK_1510 | CK_310), | ||
108 | CLK(NULL, "lb_ck", &lb_ck.clk, CK_1510 | CK_310), | ||
109 | CLK(NULL, "rhea1_ck", &rhea1_ck, CK_16XX), | ||
110 | CLK(NULL, "rhea2_ck", &rhea2_ck, CK_16XX), | ||
111 | CLK(NULL, "lcd_ck", &lcd_ck_16xx, CK_16XX | CK_7XX), | ||
112 | CLK(NULL, "lcd_ck", &lcd_ck_1510.clk, CK_1510 | CK_310), | ||
113 | /* ULPD clocks */ | ||
114 | CLK(NULL, "uart1_ck", &uart1_1510, CK_1510 | CK_310), | ||
115 | CLK(NULL, "uart1_ck", &uart1_16xx.clk, CK_16XX), | ||
116 | CLK(NULL, "uart2_ck", &uart2_ck, CK_16XX | CK_1510 | CK_310), | ||
117 | CLK(NULL, "uart3_ck", &uart3_1510, CK_1510 | CK_310), | ||
118 | CLK(NULL, "uart3_ck", &uart3_16xx.clk, CK_16XX), | ||
119 | CLK(NULL, "usb_clko", &usb_clko, CK_16XX | CK_1510 | CK_310), | ||
120 | CLK(NULL, "usb_hhc_ck", &usb_hhc_ck1510, CK_1510 | CK_310), | ||
121 | CLK(NULL, "usb_hhc_ck", &usb_hhc_ck16xx, CK_16XX), | ||
122 | CLK(NULL, "usb_dc_ck", &usb_dc_ck, CK_16XX), | ||
123 | CLK(NULL, "usb_dc_ck", &usb_dc_ck7xx, CK_7XX), | ||
124 | CLK(NULL, "mclk", &mclk_1510, CK_1510 | CK_310), | ||
125 | CLK(NULL, "mclk", &mclk_16xx, CK_16XX), | ||
126 | CLK(NULL, "bclk", &bclk_1510, CK_1510 | CK_310), | ||
127 | CLK(NULL, "bclk", &bclk_16xx, CK_16XX), | ||
128 | CLK("mmci-omap.0", "fck", &mmc1_ck, CK_16XX | CK_1510 | CK_310), | ||
129 | CLK("mmci-omap.0", "fck", &mmc3_ck, CK_7XX), | ||
130 | CLK("mmci-omap.0", "ick", &armper_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX), | ||
131 | CLK("mmci-omap.1", "fck", &mmc2_ck, CK_16XX), | ||
132 | CLK("mmci-omap.1", "ick", &armper_ck.clk, CK_16XX), | ||
133 | /* Virtual clocks */ | ||
134 | CLK(NULL, "mpu", &virtual_ck_mpu, CK_16XX | CK_1510 | CK_310), | ||
135 | CLK("i2c_omap.1", "fck", &i2c_fck, CK_16XX | CK_1510 | CK_310), | ||
136 | CLK("i2c_omap.1", "ick", &i2c_ick, CK_16XX), | ||
137 | CLK("i2c_omap.1", "ick", &dummy_ck, CK_1510 | CK_310), | ||
138 | CLK("omap_uwire", "fck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310), | ||
139 | CLK("omap-mcbsp.1", "ick", &dspper_ck, CK_16XX), | ||
140 | CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_1510 | CK_310), | ||
141 | CLK("omap-mcbsp.2", "ick", &armper_ck.clk, CK_16XX), | ||
142 | CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_1510 | CK_310), | ||
143 | CLK("omap-mcbsp.3", "ick", &dspper_ck, CK_16XX), | ||
144 | CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_1510 | CK_310), | ||
145 | CLK("omap-mcbsp.1", "fck", &dspxor_ck, CK_16XX | CK_1510 | CK_310), | ||
146 | CLK("omap-mcbsp.2", "fck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310), | ||
147 | CLK("omap-mcbsp.3", "fck", &dspxor_ck, CK_16XX | CK_1510 | CK_310), | ||
148 | }; | ||
149 | |||
150 | static int omap1_clk_enable_generic(struct clk * clk); | ||
151 | static int omap1_clk_enable(struct clk *clk); | ||
152 | static void omap1_clk_disable_generic(struct clk * clk); | ||
153 | static void omap1_clk_disable(struct clk *clk); | ||
154 | |||
155 | __u32 arm_idlect1_mask; | ||
156 | |||
157 | /*------------------------------------------------------------------------- | ||
158 | * Omap1 specific clock functions | ||
159 | *-------------------------------------------------------------------------*/ | ||
160 | |||
161 | static unsigned long omap1_watchdog_recalc(struct clk *clk) | ||
162 | { | 57 | { |
163 | return clk->parent->rate / 14; | 58 | return clk->parent->rate / 14; |
164 | } | 59 | } |
165 | 60 | ||
166 | static unsigned long omap1_uart_recalc(struct clk *clk) | 61 | unsigned long omap1_uart_recalc(struct clk *clk) |
167 | { | 62 | { |
168 | unsigned int val = __raw_readl(clk->enable_reg); | 63 | unsigned int val = __raw_readl(clk->enable_reg); |
169 | return val & clk->enable_bit ? 48000000 : 12000000; | 64 | return val & clk->enable_bit ? 48000000 : 12000000; |
170 | } | 65 | } |
171 | 66 | ||
172 | static unsigned long omap1_sossi_recalc(struct clk *clk) | 67 | unsigned long omap1_sossi_recalc(struct clk *clk) |
173 | { | 68 | { |
174 | u32 div = omap_readl(MOD_CONF_CTRL_1); | 69 | u32 div = omap_readl(MOD_CONF_CTRL_1); |
175 | 70 | ||
@@ -179,64 +74,6 @@ static unsigned long omap1_sossi_recalc(struct clk *clk) | |||
179 | return clk->parent->rate / div; | 74 | return clk->parent->rate / div; |
180 | } | 75 | } |
181 | 76 | ||
182 | static int omap1_clk_enable_dsp_domain(struct clk *clk) | ||
183 | { | ||
184 | int retval; | ||
185 | |||
186 | retval = omap1_clk_enable(&api_ck.clk); | ||
187 | if (!retval) { | ||
188 | retval = omap1_clk_enable_generic(clk); | ||
189 | omap1_clk_disable(&api_ck.clk); | ||
190 | } | ||
191 | |||
192 | return retval; | ||
193 | } | ||
194 | |||
195 | static void omap1_clk_disable_dsp_domain(struct clk *clk) | ||
196 | { | ||
197 | if (omap1_clk_enable(&api_ck.clk) == 0) { | ||
198 | omap1_clk_disable_generic(clk); | ||
199 | omap1_clk_disable(&api_ck.clk); | ||
200 | } | ||
201 | } | ||
202 | |||
203 | static const struct clkops clkops_dspck = { | ||
204 | .enable = &omap1_clk_enable_dsp_domain, | ||
205 | .disable = &omap1_clk_disable_dsp_domain, | ||
206 | }; | ||
207 | |||
208 | static int omap1_clk_enable_uart_functional(struct clk *clk) | ||
209 | { | ||
210 | int ret; | ||
211 | struct uart_clk *uclk; | ||
212 | |||
213 | ret = omap1_clk_enable_generic(clk); | ||
214 | if (ret == 0) { | ||
215 | /* Set smart idle acknowledgement mode */ | ||
216 | uclk = (struct uart_clk *)clk; | ||
217 | omap_writeb((omap_readb(uclk->sysc_addr) & ~0x10) | 8, | ||
218 | uclk->sysc_addr); | ||
219 | } | ||
220 | |||
221 | return ret; | ||
222 | } | ||
223 | |||
224 | static void omap1_clk_disable_uart_functional(struct clk *clk) | ||
225 | { | ||
226 | struct uart_clk *uclk; | ||
227 | |||
228 | /* Set force idle acknowledgement mode */ | ||
229 | uclk = (struct uart_clk *)clk; | ||
230 | omap_writeb((omap_readb(uclk->sysc_addr) & ~0x18), uclk->sysc_addr); | ||
231 | |||
232 | omap1_clk_disable_generic(clk); | ||
233 | } | ||
234 | |||
235 | static const struct clkops clkops_uart = { | ||
236 | .enable = &omap1_clk_enable_uart_functional, | ||
237 | .disable = &omap1_clk_disable_uart_functional, | ||
238 | }; | ||
239 | |||
240 | static void omap1_clk_allow_idle(struct clk *clk) | 77 | static void omap1_clk_allow_idle(struct clk *clk) |
241 | { | 78 | { |
242 | struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk; | 79 | struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk; |
@@ -344,7 +181,7 @@ static int calc_dsor_exp(struct clk *clk, unsigned long rate) | |||
344 | return dsor_exp; | 181 | return dsor_exp; |
345 | } | 182 | } |
346 | 183 | ||
347 | static unsigned long omap1_ckctl_recalc(struct clk *clk) | 184 | unsigned long omap1_ckctl_recalc(struct clk *clk) |
348 | { | 185 | { |
349 | /* Calculate divisor encoded as 2-bit exponent */ | 186 | /* Calculate divisor encoded as 2-bit exponent */ |
350 | int dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset)); | 187 | int dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset)); |
@@ -352,7 +189,7 @@ static unsigned long omap1_ckctl_recalc(struct clk *clk) | |||
352 | return clk->parent->rate / dsor; | 189 | return clk->parent->rate / dsor; |
353 | } | 190 | } |
354 | 191 | ||
355 | static unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk) | 192 | unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk) |
356 | { | 193 | { |
357 | int dsor; | 194 | int dsor; |
358 | 195 | ||
@@ -363,28 +200,29 @@ static unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk) | |||
363 | * Note that DSP_CKCTL virt addr = phys addr, so | 200 | * Note that DSP_CKCTL virt addr = phys addr, so |
364 | * we must use __raw_readw() instead of omap_readw(). | 201 | * we must use __raw_readw() instead of omap_readw(). |
365 | */ | 202 | */ |
366 | omap1_clk_enable(&api_ck.clk); | 203 | omap1_clk_enable(api_ck_p); |
367 | dsor = 1 << (3 & (__raw_readw(DSP_CKCTL) >> clk->rate_offset)); | 204 | dsor = 1 << (3 & (__raw_readw(DSP_CKCTL) >> clk->rate_offset)); |
368 | omap1_clk_disable(&api_ck.clk); | 205 | omap1_clk_disable(api_ck_p); |
369 | 206 | ||
370 | return clk->parent->rate / dsor; | 207 | return clk->parent->rate / dsor; |
371 | } | 208 | } |
372 | 209 | ||
373 | /* MPU virtual clock functions */ | 210 | /* MPU virtual clock functions */ |
374 | static int omap1_select_table_rate(struct clk * clk, unsigned long rate) | 211 | int omap1_select_table_rate(struct clk *clk, unsigned long rate) |
375 | { | 212 | { |
376 | /* Find the highest supported frequency <= rate and switch to it */ | 213 | /* Find the highest supported frequency <= rate and switch to it */ |
377 | struct mpu_rate * ptr; | 214 | struct mpu_rate * ptr; |
215 | unsigned long dpll1_rate, ref_rate; | ||
378 | 216 | ||
379 | if (clk != &virtual_ck_mpu) | 217 | dpll1_rate = clk_get_rate(ck_dpll1_p); |
380 | return -EINVAL; | 218 | ref_rate = clk_get_rate(ck_ref_p); |
381 | 219 | ||
382 | for (ptr = rate_table; ptr->rate; ptr++) { | 220 | for (ptr = omap1_rate_table; ptr->rate; ptr++) { |
383 | if (ptr->xtal != ck_ref.rate) | 221 | if (ptr->xtal != ref_rate) |
384 | continue; | 222 | continue; |
385 | 223 | ||
386 | /* DPLL1 cannot be reprogrammed without risking system crash */ | 224 | /* DPLL1 cannot be reprogrammed without risking system crash */ |
387 | if (likely(ck_dpll1.rate!=0) && ptr->pll_rate != ck_dpll1.rate) | 225 | if (likely(dpll1_rate != 0) && ptr->pll_rate != dpll1_rate) |
388 | continue; | 226 | continue; |
389 | 227 | ||
390 | /* Can check only after xtal frequency check */ | 228 | /* Can check only after xtal frequency check */ |
@@ -405,11 +243,13 @@ static int omap1_select_table_rate(struct clk * clk, unsigned long rate) | |||
405 | else | 243 | else |
406 | omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val); | 244 | omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val); |
407 | 245 | ||
408 | ck_dpll1.rate = ptr->pll_rate; | 246 | /* XXX Do we need to recalculate the tree below DPLL1 at this point? */ |
247 | ck_dpll1_p->rate = ptr->pll_rate; | ||
248 | |||
409 | return 0; | 249 | return 0; |
410 | } | 250 | } |
411 | 251 | ||
412 | static int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate) | 252 | int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate) |
413 | { | 253 | { |
414 | int dsor_exp; | 254 | int dsor_exp; |
415 | u16 regval; | 255 | u16 regval; |
@@ -429,7 +269,7 @@ static int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate) | |||
429 | return 0; | 269 | return 0; |
430 | } | 270 | } |
431 | 271 | ||
432 | static long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate) | 272 | long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate) |
433 | { | 273 | { |
434 | int dsor_exp = calc_dsor_exp(clk, rate); | 274 | int dsor_exp = calc_dsor_exp(clk, rate); |
435 | if (dsor_exp < 0) | 275 | if (dsor_exp < 0) |
@@ -439,7 +279,7 @@ static long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate) | |||
439 | return clk->parent->rate / (1 << dsor_exp); | 279 | return clk->parent->rate / (1 << dsor_exp); |
440 | } | 280 | } |
441 | 281 | ||
442 | static int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate) | 282 | int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate) |
443 | { | 283 | { |
444 | int dsor_exp; | 284 | int dsor_exp; |
445 | u16 regval; | 285 | u16 regval; |
@@ -459,19 +299,19 @@ static int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate) | |||
459 | return 0; | 299 | return 0; |
460 | } | 300 | } |
461 | 301 | ||
462 | static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate) | 302 | long omap1_round_to_table_rate(struct clk *clk, unsigned long rate) |
463 | { | 303 | { |
464 | /* Find the highest supported frequency <= rate */ | 304 | /* Find the highest supported frequency <= rate */ |
465 | struct mpu_rate * ptr; | 305 | struct mpu_rate * ptr; |
466 | long highest_rate; | 306 | long highest_rate; |
307 | unsigned long ref_rate; | ||
467 | 308 | ||
468 | if (clk != &virtual_ck_mpu) | 309 | ref_rate = clk_get_rate(ck_ref_p); |
469 | return -EINVAL; | ||
470 | 310 | ||
471 | highest_rate = -EINVAL; | 311 | highest_rate = -EINVAL; |
472 | 312 | ||
473 | for (ptr = rate_table; ptr->rate; ptr++) { | 313 | for (ptr = omap1_rate_table; ptr->rate; ptr++) { |
474 | if (ptr->xtal != ck_ref.rate) | 314 | if (ptr->xtal != ref_rate) |
475 | continue; | 315 | continue; |
476 | 316 | ||
477 | highest_rate = ptr->rate; | 317 | highest_rate = ptr->rate; |
@@ -506,8 +346,8 @@ static unsigned calc_ext_dsor(unsigned long rate) | |||
506 | return dsor; | 346 | return dsor; |
507 | } | 347 | } |
508 | 348 | ||
509 | /* Only needed on 1510 */ | 349 | /* XXX Only needed on 1510 */ |
510 | static int omap1_set_uart_rate(struct clk * clk, unsigned long rate) | 350 | int omap1_set_uart_rate(struct clk *clk, unsigned long rate) |
511 | { | 351 | { |
512 | unsigned int val; | 352 | unsigned int val; |
513 | 353 | ||
@@ -525,7 +365,7 @@ static int omap1_set_uart_rate(struct clk * clk, unsigned long rate) | |||
525 | } | 365 | } |
526 | 366 | ||
527 | /* External clock (MCLK & BCLK) functions */ | 367 | /* External clock (MCLK & BCLK) functions */ |
528 | static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate) | 368 | int omap1_set_ext_clk_rate(struct clk *clk, unsigned long rate) |
529 | { | 369 | { |
530 | unsigned dsor; | 370 | unsigned dsor; |
531 | __u16 ratio_bits; | 371 | __u16 ratio_bits; |
@@ -543,7 +383,7 @@ static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate) | |||
543 | return 0; | 383 | return 0; |
544 | } | 384 | } |
545 | 385 | ||
546 | static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate) | 386 | int omap1_set_sossi_rate(struct clk *clk, unsigned long rate) |
547 | { | 387 | { |
548 | u32 l; | 388 | u32 l; |
549 | int div; | 389 | int div; |
@@ -566,12 +406,12 @@ static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate) | |||
566 | return 0; | 406 | return 0; |
567 | } | 407 | } |
568 | 408 | ||
569 | static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate) | 409 | long omap1_round_ext_clk_rate(struct clk *clk, unsigned long rate) |
570 | { | 410 | { |
571 | return 96000000 / calc_ext_dsor(rate); | 411 | return 96000000 / calc_ext_dsor(rate); |
572 | } | 412 | } |
573 | 413 | ||
574 | static void omap1_init_ext_clk(struct clk * clk) | 414 | void omap1_init_ext_clk(struct clk *clk) |
575 | { | 415 | { |
576 | unsigned dsor; | 416 | unsigned dsor; |
577 | __u16 ratio_bits; | 417 | __u16 ratio_bits; |
@@ -589,7 +429,7 @@ static void omap1_init_ext_clk(struct clk * clk) | |||
589 | clk-> rate = 96000000 / dsor; | 429 | clk-> rate = 96000000 / dsor; |
590 | } | 430 | } |
591 | 431 | ||
592 | static int omap1_clk_enable(struct clk *clk) | 432 | int omap1_clk_enable(struct clk *clk) |
593 | { | 433 | { |
594 | int ret = 0; | 434 | int ret = 0; |
595 | 435 | ||
@@ -617,7 +457,7 @@ err: | |||
617 | return ret; | 457 | return ret; |
618 | } | 458 | } |
619 | 459 | ||
620 | static void omap1_clk_disable(struct clk *clk) | 460 | void omap1_clk_disable(struct clk *clk) |
621 | { | 461 | { |
622 | if (clk->usecount > 0 && !(--clk->usecount)) { | 462 | if (clk->usecount > 0 && !(--clk->usecount)) { |
623 | clk->ops->disable(clk); | 463 | clk->ops->disable(clk); |
@@ -672,12 +512,70 @@ static void omap1_clk_disable_generic(struct clk *clk) | |||
672 | } | 512 | } |
673 | } | 513 | } |
674 | 514 | ||
675 | static const struct clkops clkops_generic = { | 515 | const struct clkops clkops_generic = { |
676 | .enable = &omap1_clk_enable_generic, | 516 | .enable = omap1_clk_enable_generic, |
677 | .disable = &omap1_clk_disable_generic, | 517 | .disable = omap1_clk_disable_generic, |
518 | }; | ||
519 | |||
520 | static int omap1_clk_enable_dsp_domain(struct clk *clk) | ||
521 | { | ||
522 | int retval; | ||
523 | |||
524 | retval = omap1_clk_enable(api_ck_p); | ||
525 | if (!retval) { | ||
526 | retval = omap1_clk_enable_generic(clk); | ||
527 | omap1_clk_disable(api_ck_p); | ||
528 | } | ||
529 | |||
530 | return retval; | ||
531 | } | ||
532 | |||
533 | static void omap1_clk_disable_dsp_domain(struct clk *clk) | ||
534 | { | ||
535 | if (omap1_clk_enable(api_ck_p) == 0) { | ||
536 | omap1_clk_disable_generic(clk); | ||
537 | omap1_clk_disable(api_ck_p); | ||
538 | } | ||
539 | } | ||
540 | |||
541 | const struct clkops clkops_dspck = { | ||
542 | .enable = omap1_clk_enable_dsp_domain, | ||
543 | .disable = omap1_clk_disable_dsp_domain, | ||
544 | }; | ||
545 | |||
546 | static int omap1_clk_enable_uart_functional(struct clk *clk) | ||
547 | { | ||
548 | int ret; | ||
549 | struct uart_clk *uclk; | ||
550 | |||
551 | ret = omap1_clk_enable_generic(clk); | ||
552 | if (ret == 0) { | ||
553 | /* Set smart idle acknowledgement mode */ | ||
554 | uclk = (struct uart_clk *)clk; | ||
555 | omap_writeb((omap_readb(uclk->sysc_addr) & ~0x10) | 8, | ||
556 | uclk->sysc_addr); | ||
557 | } | ||
558 | |||
559 | return ret; | ||
560 | } | ||
561 | |||
562 | static void omap1_clk_disable_uart_functional(struct clk *clk) | ||
563 | { | ||
564 | struct uart_clk *uclk; | ||
565 | |||
566 | /* Set force idle acknowledgement mode */ | ||
567 | uclk = (struct uart_clk *)clk; | ||
568 | omap_writeb((omap_readb(uclk->sysc_addr) & ~0x18), uclk->sysc_addr); | ||
569 | |||
570 | omap1_clk_disable_generic(clk); | ||
571 | } | ||
572 | |||
573 | const struct clkops clkops_uart = { | ||
574 | .enable = omap1_clk_enable_uart_functional, | ||
575 | .disable = omap1_clk_disable_uart_functional, | ||
678 | }; | 576 | }; |
679 | 577 | ||
680 | static long omap1_clk_round_rate(struct clk *clk, unsigned long rate) | 578 | long omap1_clk_round_rate(struct clk *clk, unsigned long rate) |
681 | { | 579 | { |
682 | if (clk->flags & RATE_FIXED) | 580 | if (clk->flags & RATE_FIXED) |
683 | return clk->rate; | 581 | return clk->rate; |
@@ -688,7 +586,7 @@ static long omap1_clk_round_rate(struct clk *clk, unsigned long rate) | |||
688 | return clk->rate; | 586 | return clk->rate; |
689 | } | 587 | } |
690 | 588 | ||
691 | static int omap1_clk_set_rate(struct clk *clk, unsigned long rate) | 589 | int omap1_clk_set_rate(struct clk *clk, unsigned long rate) |
692 | { | 590 | { |
693 | int ret = -EINVAL; | 591 | int ret = -EINVAL; |
694 | 592 | ||
@@ -703,7 +601,7 @@ static int omap1_clk_set_rate(struct clk *clk, unsigned long rate) | |||
703 | 601 | ||
704 | #ifdef CONFIG_OMAP_RESET_CLOCKS | 602 | #ifdef CONFIG_OMAP_RESET_CLOCKS |
705 | 603 | ||
706 | static void __init omap1_clk_disable_unused(struct clk *clk) | 604 | void __init omap1_clk_disable_unused(struct clk *clk) |
707 | { | 605 | { |
708 | __u32 regval32; | 606 | __u32 regval32; |
709 | 607 | ||
@@ -724,184 +622,9 @@ static void __init omap1_clk_disable_unused(struct clk *clk) | |||
724 | if ((regval32 & (1 << clk->enable_bit)) == 0) | 622 | if ((regval32 & (1 << clk->enable_bit)) == 0) |
725 | return; | 623 | return; |
726 | 624 | ||
727 | /* FIXME: This clock seems to be necessary but no-one | ||
728 | * has asked for its activation. */ | ||
729 | if (clk == &tc2_ck /* FIX: pm.c (SRAM), CCP, Camera */ | ||
730 | || clk == &ck_dpll1out.clk /* FIX: SoSSI, SSR */ | ||
731 | || clk == &arm_gpio_ck /* FIX: GPIO code for 1510 */ | ||
732 | ) { | ||
733 | printk(KERN_INFO "FIXME: Clock \"%s\" seems unused\n", | ||
734 | clk->name); | ||
735 | return; | ||
736 | } | ||
737 | |||
738 | printk(KERN_INFO "Disabling unused clock \"%s\"... ", clk->name); | 625 | printk(KERN_INFO "Disabling unused clock \"%s\"... ", clk->name); |
739 | clk->ops->disable(clk); | 626 | clk->ops->disable(clk); |
740 | printk(" done\n"); | 627 | printk(" done\n"); |
741 | } | 628 | } |
742 | 629 | ||
743 | #else | ||
744 | #define omap1_clk_disable_unused NULL | ||
745 | #endif | 630 | #endif |
746 | |||
747 | static struct clk_functions omap1_clk_functions = { | ||
748 | .clk_enable = omap1_clk_enable, | ||
749 | .clk_disable = omap1_clk_disable, | ||
750 | .clk_round_rate = omap1_clk_round_rate, | ||
751 | .clk_set_rate = omap1_clk_set_rate, | ||
752 | .clk_disable_unused = omap1_clk_disable_unused, | ||
753 | }; | ||
754 | |||
755 | int __init omap1_clk_init(void) | ||
756 | { | ||
757 | struct omap_clk *c; | ||
758 | const struct omap_clock_config *info; | ||
759 | int crystal_type = 0; /* Default 12 MHz */ | ||
760 | u32 reg, cpu_mask; | ||
761 | |||
762 | #ifdef CONFIG_DEBUG_LL | ||
763 | /* Resets some clocks that may be left on from bootloader, | ||
764 | * but leaves serial clocks on. | ||
765 | */ | ||
766 | omap_writel(0x3 << 29, MOD_CONF_CTRL_0); | ||
767 | #endif | ||
768 | |||
769 | /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */ | ||
770 | reg = omap_readw(SOFT_REQ_REG) & (1 << 4); | ||
771 | omap_writew(reg, SOFT_REQ_REG); | ||
772 | if (!cpu_is_omap15xx()) | ||
773 | omap_writew(0, SOFT_REQ_REG2); | ||
774 | |||
775 | clk_init(&omap1_clk_functions); | ||
776 | |||
777 | /* By default all idlect1 clocks are allowed to idle */ | ||
778 | arm_idlect1_mask = ~0; | ||
779 | |||
780 | for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++) | ||
781 | clk_preinit(c->lk.clk); | ||
782 | |||
783 | cpu_mask = 0; | ||
784 | if (cpu_is_omap16xx()) | ||
785 | cpu_mask |= CK_16XX; | ||
786 | if (cpu_is_omap1510()) | ||
787 | cpu_mask |= CK_1510; | ||
788 | if (cpu_is_omap7xx()) | ||
789 | cpu_mask |= CK_7XX; | ||
790 | if (cpu_is_omap310()) | ||
791 | cpu_mask |= CK_310; | ||
792 | |||
793 | for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++) | ||
794 | if (c->cpu & cpu_mask) { | ||
795 | clkdev_add(&c->lk); | ||
796 | clk_register(c->lk.clk); | ||
797 | } | ||
798 | |||
799 | info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config); | ||
800 | if (info != NULL) { | ||
801 | if (!cpu_is_omap15xx()) | ||
802 | crystal_type = info->system_clock_type; | ||
803 | } | ||
804 | |||
805 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) | ||
806 | ck_ref.rate = 13000000; | ||
807 | #elif defined(CONFIG_ARCH_OMAP16XX) | ||
808 | if (crystal_type == 2) | ||
809 | ck_ref.rate = 19200000; | ||
810 | #endif | ||
811 | |||
812 | printk("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n", | ||
813 | omap_readw(ARM_SYSST), omap_readw(DPLL_CTL), | ||
814 | omap_readw(ARM_CKCTL)); | ||
815 | |||
816 | /* We want to be in syncronous scalable mode */ | ||
817 | omap_writew(0x1000, ARM_SYSST); | ||
818 | |||
819 | #ifdef CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER | ||
820 | /* Use values set by bootloader. Determine PLL rate and recalculate | ||
821 | * dependent clocks as if kernel had changed PLL or divisors. | ||
822 | */ | ||
823 | { | ||
824 | unsigned pll_ctl_val = omap_readw(DPLL_CTL); | ||
825 | |||
826 | ck_dpll1.rate = ck_ref.rate; /* Base xtal rate */ | ||
827 | if (pll_ctl_val & 0x10) { | ||
828 | /* PLL enabled, apply multiplier and divisor */ | ||
829 | if (pll_ctl_val & 0xf80) | ||
830 | ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7; | ||
831 | ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1; | ||
832 | } else { | ||
833 | /* PLL disabled, apply bypass divisor */ | ||
834 | switch (pll_ctl_val & 0xc) { | ||
835 | case 0: | ||
836 | break; | ||
837 | case 0x4: | ||
838 | ck_dpll1.rate /= 2; | ||
839 | break; | ||
840 | default: | ||
841 | ck_dpll1.rate /= 4; | ||
842 | break; | ||
843 | } | ||
844 | } | ||
845 | } | ||
846 | #else | ||
847 | /* Find the highest supported frequency and enable it */ | ||
848 | if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) { | ||
849 | printk(KERN_ERR "System frequencies not set. Check your config.\n"); | ||
850 | /* Guess sane values (60MHz) */ | ||
851 | omap_writew(0x2290, DPLL_CTL); | ||
852 | omap_writew(cpu_is_omap7xx() ? 0x3005 : 0x1005, ARM_CKCTL); | ||
853 | ck_dpll1.rate = 60000000; | ||
854 | } | ||
855 | #endif | ||
856 | propagate_rate(&ck_dpll1); | ||
857 | /* Cache rates for clocks connected to ck_ref (not dpll1) */ | ||
858 | propagate_rate(&ck_ref); | ||
859 | printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): " | ||
860 | "%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n", | ||
861 | ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10, | ||
862 | ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10, | ||
863 | arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10); | ||
864 | |||
865 | #if defined(CONFIG_MACH_OMAP_PERSEUS2) || defined(CONFIG_MACH_OMAP_FSAMPLE) | ||
866 | /* Select slicer output as OMAP input clock */ | ||
867 | omap_writew(omap_readw(OMAP7XX_PCC_UPLD_CTRL) & ~0x1, OMAP7XX_PCC_UPLD_CTRL); | ||
868 | #endif | ||
869 | |||
870 | /* Amstrad Delta wants BCLK high when inactive */ | ||
871 | if (machine_is_ams_delta()) | ||
872 | omap_writel(omap_readl(ULPD_CLOCK_CTRL) | | ||
873 | (1 << SDW_MCLK_INV_BIT), | ||
874 | ULPD_CLOCK_CTRL); | ||
875 | |||
876 | /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */ | ||
877 | /* (on 730, bit 13 must not be cleared) */ | ||
878 | if (cpu_is_omap7xx()) | ||
879 | omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL); | ||
880 | else | ||
881 | omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL); | ||
882 | |||
883 | /* Put DSP/MPUI into reset until needed */ | ||
884 | omap_writew(0, ARM_RSTCT1); | ||
885 | omap_writew(1, ARM_RSTCT2); | ||
886 | omap_writew(0x400, ARM_IDLECT1); | ||
887 | |||
888 | /* | ||
889 | * According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8) | ||
890 | * of the ARM_IDLECT2 register must be set to zero. The power-on | ||
891 | * default value of this bit is one. | ||
892 | */ | ||
893 | omap_writew(0x0000, ARM_IDLECT2); /* Turn LCD clock off also */ | ||
894 | |||
895 | /* | ||
896 | * Only enable those clocks we will need, let the drivers | ||
897 | * enable other clocks as necessary | ||
898 | */ | ||
899 | clk_enable(&armper_ck.clk); | ||
900 | clk_enable(&armxor_ck.clk); | ||
901 | clk_enable(&armtim_ck.clk); /* This should be done by timer code */ | ||
902 | |||
903 | if (cpu_is_omap15xx()) | ||
904 | clk_enable(&arm_gpio_ck); | ||
905 | |||
906 | return 0; | ||
907 | } | ||
diff --git a/arch/arm/mach-omap1/clock.h b/arch/arm/mach-omap1/clock.h index 29ffa97dc7f3..a4190afb8614 100644 --- a/arch/arm/mach-omap1/clock.h +++ b/arch/arm/mach-omap1/clock.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * linux/arch/arm/mach-omap1/clock.h | 2 | * linux/arch/arm/mach-omap1/clock.h |
3 | * | 3 | * |
4 | * Copyright (C) 2004 - 2005 Nokia corporation | 4 | * Copyright (C) 2004 - 2005, 2009 Nokia corporation |
5 | * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> | 5 | * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> |
6 | * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc | 6 | * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc |
7 | * | 7 | * |
@@ -13,30 +13,36 @@ | |||
13 | #ifndef __ARCH_ARM_MACH_OMAP1_CLOCK_H | 13 | #ifndef __ARCH_ARM_MACH_OMAP1_CLOCK_H |
14 | #define __ARCH_ARM_MACH_OMAP1_CLOCK_H | 14 | #define __ARCH_ARM_MACH_OMAP1_CLOCK_H |
15 | 15 | ||
16 | static unsigned long omap1_ckctl_recalc(struct clk *clk); | 16 | #include <linux/clk.h> |
17 | static unsigned long omap1_watchdog_recalc(struct clk *clk); | 17 | |
18 | static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate); | 18 | #include <plat/clock.h> |
19 | static unsigned long omap1_sossi_recalc(struct clk *clk); | 19 | |
20 | static unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk); | 20 | extern int __init omap1_clk_init(void); |
21 | static int omap1_clk_set_rate_dsp_domain(struct clk * clk, unsigned long rate); | 21 | extern int omap1_clk_enable(struct clk *clk); |
22 | static int omap1_set_uart_rate(struct clk * clk, unsigned long rate); | 22 | extern void omap1_clk_disable(struct clk *clk); |
23 | static unsigned long omap1_uart_recalc(struct clk *clk); | 23 | extern long omap1_clk_round_rate(struct clk *clk, unsigned long rate); |
24 | static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate); | 24 | extern int omap1_clk_set_rate(struct clk *clk, unsigned long rate); |
25 | static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate); | 25 | extern unsigned long omap1_ckctl_recalc(struct clk *clk); |
26 | static void omap1_init_ext_clk(struct clk * clk); | 26 | extern int omap1_set_sossi_rate(struct clk *clk, unsigned long rate); |
27 | static int omap1_select_table_rate(struct clk * clk, unsigned long rate); | 27 | extern unsigned long omap1_sossi_recalc(struct clk *clk); |
28 | static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate); | 28 | extern unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk); |
29 | 29 | extern int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate); | |
30 | static int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate); | 30 | extern int omap1_set_uart_rate(struct clk *clk, unsigned long rate); |
31 | static long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate); | 31 | extern unsigned long omap1_uart_recalc(struct clk *clk); |
32 | 32 | extern int omap1_set_ext_clk_rate(struct clk *clk, unsigned long rate); | |
33 | struct mpu_rate { | 33 | extern long omap1_round_ext_clk_rate(struct clk *clk, unsigned long rate); |
34 | unsigned long rate; | 34 | extern void omap1_init_ext_clk(struct clk *clk); |
35 | unsigned long xtal; | 35 | extern int omap1_select_table_rate(struct clk *clk, unsigned long rate); |
36 | unsigned long pll_rate; | 36 | extern long omap1_round_to_table_rate(struct clk *clk, unsigned long rate); |
37 | __u16 ckctl_val; | 37 | extern int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate); |
38 | __u16 dpllctl_val; | 38 | extern long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate); |
39 | }; | 39 | extern unsigned long omap1_watchdog_recalc(struct clk *clk); |
40 | |||
41 | #ifdef CONFIG_OMAP_RESET_CLOCKS | ||
42 | extern void __init omap1_clk_disable_unused(struct clk *clk); | ||
43 | #else | ||
44 | #define omap1_clk_disable_unused NULL | ||
45 | #endif | ||
40 | 46 | ||
41 | struct uart_clk { | 47 | struct uart_clk { |
42 | struct clk clk; | 48 | struct clk clk; |
@@ -96,596 +102,12 @@ struct arm_idlect1_clk { | |||
96 | #define SOFT_REQ_REG 0xfffe0834 | 102 | #define SOFT_REQ_REG 0xfffe0834 |
97 | #define SOFT_REQ_REG2 0xfffe0880 | 103 | #define SOFT_REQ_REG2 0xfffe0880 |
98 | 104 | ||
99 | /*------------------------------------------------------------------------- | 105 | extern __u32 arm_idlect1_mask; |
100 | * Omap1 MPU rate table | 106 | extern struct clk *api_ck_p, *ck_dpll1_p, *ck_ref_p; |
101 | *-------------------------------------------------------------------------*/ | ||
102 | static struct mpu_rate rate_table[] = { | ||
103 | /* MPU MHz, xtal MHz, dpll1 MHz, CKCTL, DPLL_CTL | ||
104 | * NOTE: Comment order here is different from bits in CKCTL value: | ||
105 | * armdiv, dspdiv, dspmmu, tcdiv, perdiv, lcddiv | ||
106 | */ | ||
107 | #if defined(CONFIG_OMAP_ARM_216MHZ) | ||
108 | { 216000000, 12000000, 216000000, 0x050d, 0x2910 }, /* 1/1/2/2/2/8 */ | ||
109 | #endif | ||
110 | #if defined(CONFIG_OMAP_ARM_195MHZ) | ||
111 | { 195000000, 13000000, 195000000, 0x050e, 0x2790 }, /* 1/1/2/2/4/8 */ | ||
112 | #endif | ||
113 | #if defined(CONFIG_OMAP_ARM_192MHZ) | ||
114 | { 192000000, 19200000, 192000000, 0x050f, 0x2510 }, /* 1/1/2/2/8/8 */ | ||
115 | { 192000000, 12000000, 192000000, 0x050f, 0x2810 }, /* 1/1/2/2/8/8 */ | ||
116 | { 96000000, 12000000, 192000000, 0x055f, 0x2810 }, /* 2/2/2/2/8/8 */ | ||
117 | { 48000000, 12000000, 192000000, 0x0baf, 0x2810 }, /* 4/4/4/8/8/8 */ | ||
118 | { 24000000, 12000000, 192000000, 0x0fff, 0x2810 }, /* 8/8/8/8/8/8 */ | ||
119 | #endif | ||
120 | #if defined(CONFIG_OMAP_ARM_182MHZ) | ||
121 | { 182000000, 13000000, 182000000, 0x050e, 0x2710 }, /* 1/1/2/2/4/8 */ | ||
122 | #endif | ||
123 | #if defined(CONFIG_OMAP_ARM_168MHZ) | ||
124 | { 168000000, 12000000, 168000000, 0x010f, 0x2710 }, /* 1/1/1/2/8/8 */ | ||
125 | #endif | ||
126 | #if defined(CONFIG_OMAP_ARM_150MHZ) | ||
127 | { 150000000, 12000000, 150000000, 0x010a, 0x2cb0 }, /* 1/1/1/2/4/4 */ | ||
128 | #endif | ||
129 | #if defined(CONFIG_OMAP_ARM_120MHZ) | ||
130 | { 120000000, 12000000, 120000000, 0x010a, 0x2510 }, /* 1/1/1/2/4/4 */ | ||
131 | #endif | ||
132 | #if defined(CONFIG_OMAP_ARM_96MHZ) | ||
133 | { 96000000, 12000000, 96000000, 0x0005, 0x2410 }, /* 1/1/1/1/2/2 */ | ||
134 | #endif | ||
135 | #if defined(CONFIG_OMAP_ARM_60MHZ) | ||
136 | { 60000000, 12000000, 60000000, 0x0005, 0x2290 }, /* 1/1/1/1/2/2 */ | ||
137 | #endif | ||
138 | #if defined(CONFIG_OMAP_ARM_30MHZ) | ||
139 | { 30000000, 12000000, 60000000, 0x0555, 0x2290 }, /* 2/2/2/2/2/2 */ | ||
140 | #endif | ||
141 | { 0, 0, 0, 0, 0 }, | ||
142 | }; | ||
143 | |||
144 | /*------------------------------------------------------------------------- | ||
145 | * Omap1 clocks | ||
146 | *-------------------------------------------------------------------------*/ | ||
147 | |||
148 | static struct clk ck_ref = { | ||
149 | .name = "ck_ref", | ||
150 | .ops = &clkops_null, | ||
151 | .rate = 12000000, | ||
152 | }; | ||
153 | |||
154 | static struct clk ck_dpll1 = { | ||
155 | .name = "ck_dpll1", | ||
156 | .ops = &clkops_null, | ||
157 | .parent = &ck_ref, | ||
158 | }; | ||
159 | |||
160 | static struct arm_idlect1_clk ck_dpll1out = { | ||
161 | .clk = { | ||
162 | .name = "ck_dpll1out", | ||
163 | .ops = &clkops_generic, | ||
164 | .parent = &ck_dpll1, | ||
165 | .flags = CLOCK_IDLE_CONTROL | ENABLE_REG_32BIT, | ||
166 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), | ||
167 | .enable_bit = EN_CKOUT_ARM, | ||
168 | .recalc = &followparent_recalc, | ||
169 | }, | ||
170 | .idlect_shift = 12, | ||
171 | }; | ||
172 | |||
173 | static struct clk sossi_ck = { | ||
174 | .name = "ck_sossi", | ||
175 | .ops = &clkops_generic, | ||
176 | .parent = &ck_dpll1out.clk, | ||
177 | .flags = CLOCK_NO_IDLE_PARENT | ENABLE_REG_32BIT, | ||
178 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1), | ||
179 | .enable_bit = 16, | ||
180 | .recalc = &omap1_sossi_recalc, | ||
181 | .set_rate = &omap1_set_sossi_rate, | ||
182 | }; | ||
183 | |||
184 | static struct clk arm_ck = { | ||
185 | .name = "arm_ck", | ||
186 | .ops = &clkops_null, | ||
187 | .parent = &ck_dpll1, | ||
188 | .rate_offset = CKCTL_ARMDIV_OFFSET, | ||
189 | .recalc = &omap1_ckctl_recalc, | ||
190 | .round_rate = omap1_clk_round_rate_ckctl_arm, | ||
191 | .set_rate = omap1_clk_set_rate_ckctl_arm, | ||
192 | }; | ||
193 | |||
194 | static struct arm_idlect1_clk armper_ck = { | ||
195 | .clk = { | ||
196 | .name = "armper_ck", | ||
197 | .ops = &clkops_generic, | ||
198 | .parent = &ck_dpll1, | ||
199 | .flags = CLOCK_IDLE_CONTROL, | ||
200 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), | ||
201 | .enable_bit = EN_PERCK, | ||
202 | .rate_offset = CKCTL_PERDIV_OFFSET, | ||
203 | .recalc = &omap1_ckctl_recalc, | ||
204 | .round_rate = omap1_clk_round_rate_ckctl_arm, | ||
205 | .set_rate = omap1_clk_set_rate_ckctl_arm, | ||
206 | }, | ||
207 | .idlect_shift = 2, | ||
208 | }; | ||
209 | |||
210 | static struct clk arm_gpio_ck = { | ||
211 | .name = "arm_gpio_ck", | ||
212 | .ops = &clkops_generic, | ||
213 | .parent = &ck_dpll1, | ||
214 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), | ||
215 | .enable_bit = EN_GPIOCK, | ||
216 | .recalc = &followparent_recalc, | ||
217 | }; | ||
218 | |||
219 | static struct arm_idlect1_clk armxor_ck = { | ||
220 | .clk = { | ||
221 | .name = "armxor_ck", | ||
222 | .ops = &clkops_generic, | ||
223 | .parent = &ck_ref, | ||
224 | .flags = CLOCK_IDLE_CONTROL, | ||
225 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), | ||
226 | .enable_bit = EN_XORPCK, | ||
227 | .recalc = &followparent_recalc, | ||
228 | }, | ||
229 | .idlect_shift = 1, | ||
230 | }; | ||
231 | |||
232 | static struct arm_idlect1_clk armtim_ck = { | ||
233 | .clk = { | ||
234 | .name = "armtim_ck", | ||
235 | .ops = &clkops_generic, | ||
236 | .parent = &ck_ref, | ||
237 | .flags = CLOCK_IDLE_CONTROL, | ||
238 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), | ||
239 | .enable_bit = EN_TIMCK, | ||
240 | .recalc = &followparent_recalc, | ||
241 | }, | ||
242 | .idlect_shift = 9, | ||
243 | }; | ||
244 | |||
245 | static struct arm_idlect1_clk armwdt_ck = { | ||
246 | .clk = { | ||
247 | .name = "armwdt_ck", | ||
248 | .ops = &clkops_generic, | ||
249 | .parent = &ck_ref, | ||
250 | .flags = CLOCK_IDLE_CONTROL, | ||
251 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), | ||
252 | .enable_bit = EN_WDTCK, | ||
253 | .recalc = &omap1_watchdog_recalc, | ||
254 | }, | ||
255 | .idlect_shift = 0, | ||
256 | }; | ||
257 | |||
258 | static struct clk arminth_ck16xx = { | ||
259 | .name = "arminth_ck", | ||
260 | .ops = &clkops_null, | ||
261 | .parent = &arm_ck, | ||
262 | .recalc = &followparent_recalc, | ||
263 | /* Note: On 16xx the frequency can be divided by 2 by programming | ||
264 | * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1 | ||
265 | * | ||
266 | * 1510 version is in TC clocks. | ||
267 | */ | ||
268 | }; | ||
269 | |||
270 | static struct clk dsp_ck = { | ||
271 | .name = "dsp_ck", | ||
272 | .ops = &clkops_generic, | ||
273 | .parent = &ck_dpll1, | ||
274 | .enable_reg = OMAP1_IO_ADDRESS(ARM_CKCTL), | ||
275 | .enable_bit = EN_DSPCK, | ||
276 | .rate_offset = CKCTL_DSPDIV_OFFSET, | ||
277 | .recalc = &omap1_ckctl_recalc, | ||
278 | .round_rate = omap1_clk_round_rate_ckctl_arm, | ||
279 | .set_rate = omap1_clk_set_rate_ckctl_arm, | ||
280 | }; | ||
281 | |||
282 | static struct clk dspmmu_ck = { | ||
283 | .name = "dspmmu_ck", | ||
284 | .ops = &clkops_null, | ||
285 | .parent = &ck_dpll1, | ||
286 | .rate_offset = CKCTL_DSPMMUDIV_OFFSET, | ||
287 | .recalc = &omap1_ckctl_recalc, | ||
288 | .round_rate = omap1_clk_round_rate_ckctl_arm, | ||
289 | .set_rate = omap1_clk_set_rate_ckctl_arm, | ||
290 | }; | ||
291 | |||
292 | static struct clk dspper_ck = { | ||
293 | .name = "dspper_ck", | ||
294 | .ops = &clkops_dspck, | ||
295 | .parent = &ck_dpll1, | ||
296 | .enable_reg = DSP_IDLECT2, | ||
297 | .enable_bit = EN_PERCK, | ||
298 | .rate_offset = CKCTL_PERDIV_OFFSET, | ||
299 | .recalc = &omap1_ckctl_recalc_dsp_domain, | ||
300 | .round_rate = omap1_clk_round_rate_ckctl_arm, | ||
301 | .set_rate = &omap1_clk_set_rate_dsp_domain, | ||
302 | }; | ||
303 | |||
304 | static struct clk dspxor_ck = { | ||
305 | .name = "dspxor_ck", | ||
306 | .ops = &clkops_dspck, | ||
307 | .parent = &ck_ref, | ||
308 | .enable_reg = DSP_IDLECT2, | ||
309 | .enable_bit = EN_XORPCK, | ||
310 | .recalc = &followparent_recalc, | ||
311 | }; | ||
312 | |||
313 | static struct clk dsptim_ck = { | ||
314 | .name = "dsptim_ck", | ||
315 | .ops = &clkops_dspck, | ||
316 | .parent = &ck_ref, | ||
317 | .enable_reg = DSP_IDLECT2, | ||
318 | .enable_bit = EN_DSPTIMCK, | ||
319 | .recalc = &followparent_recalc, | ||
320 | }; | ||
321 | |||
322 | /* Tie ARM_IDLECT1:IDLIF_ARM to this logical clock structure */ | ||
323 | static struct arm_idlect1_clk tc_ck = { | ||
324 | .clk = { | ||
325 | .name = "tc_ck", | ||
326 | .ops = &clkops_null, | ||
327 | .parent = &ck_dpll1, | ||
328 | .flags = CLOCK_IDLE_CONTROL, | ||
329 | .rate_offset = CKCTL_TCDIV_OFFSET, | ||
330 | .recalc = &omap1_ckctl_recalc, | ||
331 | .round_rate = omap1_clk_round_rate_ckctl_arm, | ||
332 | .set_rate = omap1_clk_set_rate_ckctl_arm, | ||
333 | }, | ||
334 | .idlect_shift = 6, | ||
335 | }; | ||
336 | |||
337 | static struct clk arminth_ck1510 = { | ||
338 | .name = "arminth_ck", | ||
339 | .ops = &clkops_null, | ||
340 | .parent = &tc_ck.clk, | ||
341 | .recalc = &followparent_recalc, | ||
342 | /* Note: On 1510 the frequency follows TC_CK | ||
343 | * | ||
344 | * 16xx version is in MPU clocks. | ||
345 | */ | ||
346 | }; | ||
347 | |||
348 | static struct clk tipb_ck = { | ||
349 | /* No-idle controlled by "tc_ck" */ | ||
350 | .name = "tipb_ck", | ||
351 | .ops = &clkops_null, | ||
352 | .parent = &tc_ck.clk, | ||
353 | .recalc = &followparent_recalc, | ||
354 | }; | ||
355 | |||
356 | static struct clk l3_ocpi_ck = { | ||
357 | /* No-idle controlled by "tc_ck" */ | ||
358 | .name = "l3_ocpi_ck", | ||
359 | .ops = &clkops_generic, | ||
360 | .parent = &tc_ck.clk, | ||
361 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3), | ||
362 | .enable_bit = EN_OCPI_CK, | ||
363 | .recalc = &followparent_recalc, | ||
364 | }; | ||
365 | |||
366 | static struct clk tc1_ck = { | ||
367 | .name = "tc1_ck", | ||
368 | .ops = &clkops_generic, | ||
369 | .parent = &tc_ck.clk, | ||
370 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3), | ||
371 | .enable_bit = EN_TC1_CK, | ||
372 | .recalc = &followparent_recalc, | ||
373 | }; | ||
374 | 107 | ||
375 | static struct clk tc2_ck = { | 108 | extern const struct clkops clkops_dspck; |
376 | .name = "tc2_ck", | 109 | extern const struct clkops clkops_dummy; |
377 | .ops = &clkops_generic, | 110 | extern const struct clkops clkops_uart; |
378 | .parent = &tc_ck.clk, | 111 | extern const struct clkops clkops_generic; |
379 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3), | ||
380 | .enable_bit = EN_TC2_CK, | ||
381 | .recalc = &followparent_recalc, | ||
382 | }; | ||
383 | |||
384 | static struct clk dma_ck = { | ||
385 | /* No-idle controlled by "tc_ck" */ | ||
386 | .name = "dma_ck", | ||
387 | .ops = &clkops_null, | ||
388 | .parent = &tc_ck.clk, | ||
389 | .recalc = &followparent_recalc, | ||
390 | }; | ||
391 | |||
392 | static struct clk dma_lcdfree_ck = { | ||
393 | .name = "dma_lcdfree_ck", | ||
394 | .ops = &clkops_null, | ||
395 | .parent = &tc_ck.clk, | ||
396 | .recalc = &followparent_recalc, | ||
397 | }; | ||
398 | |||
399 | static struct arm_idlect1_clk api_ck = { | ||
400 | .clk = { | ||
401 | .name = "api_ck", | ||
402 | .ops = &clkops_generic, | ||
403 | .parent = &tc_ck.clk, | ||
404 | .flags = CLOCK_IDLE_CONTROL, | ||
405 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), | ||
406 | .enable_bit = EN_APICK, | ||
407 | .recalc = &followparent_recalc, | ||
408 | }, | ||
409 | .idlect_shift = 8, | ||
410 | }; | ||
411 | |||
412 | static struct arm_idlect1_clk lb_ck = { | ||
413 | .clk = { | ||
414 | .name = "lb_ck", | ||
415 | .ops = &clkops_generic, | ||
416 | .parent = &tc_ck.clk, | ||
417 | .flags = CLOCK_IDLE_CONTROL, | ||
418 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), | ||
419 | .enable_bit = EN_LBCK, | ||
420 | .recalc = &followparent_recalc, | ||
421 | }, | ||
422 | .idlect_shift = 4, | ||
423 | }; | ||
424 | |||
425 | static struct clk rhea1_ck = { | ||
426 | .name = "rhea1_ck", | ||
427 | .ops = &clkops_null, | ||
428 | .parent = &tc_ck.clk, | ||
429 | .recalc = &followparent_recalc, | ||
430 | }; | ||
431 | |||
432 | static struct clk rhea2_ck = { | ||
433 | .name = "rhea2_ck", | ||
434 | .ops = &clkops_null, | ||
435 | .parent = &tc_ck.clk, | ||
436 | .recalc = &followparent_recalc, | ||
437 | }; | ||
438 | |||
439 | static struct clk lcd_ck_16xx = { | ||
440 | .name = "lcd_ck", | ||
441 | .ops = &clkops_generic, | ||
442 | .parent = &ck_dpll1, | ||
443 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), | ||
444 | .enable_bit = EN_LCDCK, | ||
445 | .rate_offset = CKCTL_LCDDIV_OFFSET, | ||
446 | .recalc = &omap1_ckctl_recalc, | ||
447 | .round_rate = omap1_clk_round_rate_ckctl_arm, | ||
448 | .set_rate = omap1_clk_set_rate_ckctl_arm, | ||
449 | }; | ||
450 | |||
451 | static struct arm_idlect1_clk lcd_ck_1510 = { | ||
452 | .clk = { | ||
453 | .name = "lcd_ck", | ||
454 | .ops = &clkops_generic, | ||
455 | .parent = &ck_dpll1, | ||
456 | .flags = CLOCK_IDLE_CONTROL, | ||
457 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), | ||
458 | .enable_bit = EN_LCDCK, | ||
459 | .rate_offset = CKCTL_LCDDIV_OFFSET, | ||
460 | .recalc = &omap1_ckctl_recalc, | ||
461 | .round_rate = omap1_clk_round_rate_ckctl_arm, | ||
462 | .set_rate = omap1_clk_set_rate_ckctl_arm, | ||
463 | }, | ||
464 | .idlect_shift = 3, | ||
465 | }; | ||
466 | |||
467 | static struct clk uart1_1510 = { | ||
468 | .name = "uart1_ck", | ||
469 | .ops = &clkops_null, | ||
470 | /* Direct from ULPD, no real parent */ | ||
471 | .parent = &armper_ck.clk, | ||
472 | .rate = 12000000, | ||
473 | .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, | ||
474 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), | ||
475 | .enable_bit = 29, /* Chooses between 12MHz and 48MHz */ | ||
476 | .set_rate = &omap1_set_uart_rate, | ||
477 | .recalc = &omap1_uart_recalc, | ||
478 | }; | ||
479 | |||
480 | static struct uart_clk uart1_16xx = { | ||
481 | .clk = { | ||
482 | .name = "uart1_ck", | ||
483 | .ops = &clkops_uart, | ||
484 | /* Direct from ULPD, no real parent */ | ||
485 | .parent = &armper_ck.clk, | ||
486 | .rate = 48000000, | ||
487 | .flags = RATE_FIXED | ENABLE_REG_32BIT | | ||
488 | CLOCK_NO_IDLE_PARENT, | ||
489 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), | ||
490 | .enable_bit = 29, | ||
491 | }, | ||
492 | .sysc_addr = 0xfffb0054, | ||
493 | }; | ||
494 | |||
495 | static struct clk uart2_ck = { | ||
496 | .name = "uart2_ck", | ||
497 | .ops = &clkops_null, | ||
498 | /* Direct from ULPD, no real parent */ | ||
499 | .parent = &armper_ck.clk, | ||
500 | .rate = 12000000, | ||
501 | .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, | ||
502 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), | ||
503 | .enable_bit = 30, /* Chooses between 12MHz and 48MHz */ | ||
504 | .set_rate = &omap1_set_uart_rate, | ||
505 | .recalc = &omap1_uart_recalc, | ||
506 | }; | ||
507 | |||
508 | static struct clk uart3_1510 = { | ||
509 | .name = "uart3_ck", | ||
510 | .ops = &clkops_null, | ||
511 | /* Direct from ULPD, no real parent */ | ||
512 | .parent = &armper_ck.clk, | ||
513 | .rate = 12000000, | ||
514 | .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, | ||
515 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), | ||
516 | .enable_bit = 31, /* Chooses between 12MHz and 48MHz */ | ||
517 | .set_rate = &omap1_set_uart_rate, | ||
518 | .recalc = &omap1_uart_recalc, | ||
519 | }; | ||
520 | |||
521 | static struct uart_clk uart3_16xx = { | ||
522 | .clk = { | ||
523 | .name = "uart3_ck", | ||
524 | .ops = &clkops_uart, | ||
525 | /* Direct from ULPD, no real parent */ | ||
526 | .parent = &armper_ck.clk, | ||
527 | .rate = 48000000, | ||
528 | .flags = RATE_FIXED | ENABLE_REG_32BIT | | ||
529 | CLOCK_NO_IDLE_PARENT, | ||
530 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), | ||
531 | .enable_bit = 31, | ||
532 | }, | ||
533 | .sysc_addr = 0xfffb9854, | ||
534 | }; | ||
535 | |||
536 | static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */ | ||
537 | .name = "usb_clko", | ||
538 | .ops = &clkops_generic, | ||
539 | /* Direct from ULPD, no parent */ | ||
540 | .rate = 6000000, | ||
541 | .flags = RATE_FIXED | ENABLE_REG_32BIT, | ||
542 | .enable_reg = OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL), | ||
543 | .enable_bit = USB_MCLK_EN_BIT, | ||
544 | }; | ||
545 | |||
546 | static struct clk usb_hhc_ck1510 = { | ||
547 | .name = "usb_hhc_ck", | ||
548 | .ops = &clkops_generic, | ||
549 | /* Direct from ULPD, no parent */ | ||
550 | .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */ | ||
551 | .flags = RATE_FIXED | ENABLE_REG_32BIT, | ||
552 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), | ||
553 | .enable_bit = USB_HOST_HHC_UHOST_EN, | ||
554 | }; | ||
555 | |||
556 | static struct clk usb_hhc_ck16xx = { | ||
557 | .name = "usb_hhc_ck", | ||
558 | .ops = &clkops_generic, | ||
559 | /* Direct from ULPD, no parent */ | ||
560 | .rate = 48000000, | ||
561 | /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */ | ||
562 | .flags = RATE_FIXED | ENABLE_REG_32BIT, | ||
563 | .enable_reg = OMAP1_IO_ADDRESS(OTG_BASE + 0x08), /* OTG_SYSCON_2 */ | ||
564 | .enable_bit = 8 /* UHOST_EN */, | ||
565 | }; | ||
566 | |||
567 | static struct clk usb_dc_ck = { | ||
568 | .name = "usb_dc_ck", | ||
569 | .ops = &clkops_generic, | ||
570 | /* Direct from ULPD, no parent */ | ||
571 | .rate = 48000000, | ||
572 | .flags = RATE_FIXED, | ||
573 | .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), | ||
574 | .enable_bit = 4, | ||
575 | }; | ||
576 | |||
577 | static struct clk usb_dc_ck7xx = { | ||
578 | .name = "usb_dc_ck", | ||
579 | .ops = &clkops_generic, | ||
580 | /* Direct from ULPD, no parent */ | ||
581 | .rate = 48000000, | ||
582 | .flags = RATE_FIXED, | ||
583 | .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), | ||
584 | .enable_bit = 8, | ||
585 | }; | ||
586 | |||
587 | static struct clk mclk_1510 = { | ||
588 | .name = "mclk", | ||
589 | .ops = &clkops_generic, | ||
590 | /* Direct from ULPD, no parent. May be enabled by ext hardware. */ | ||
591 | .rate = 12000000, | ||
592 | .flags = RATE_FIXED, | ||
593 | .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), | ||
594 | .enable_bit = 6, | ||
595 | }; | ||
596 | |||
597 | static struct clk mclk_16xx = { | ||
598 | .name = "mclk", | ||
599 | .ops = &clkops_generic, | ||
600 | /* Direct from ULPD, no parent. May be enabled by ext hardware. */ | ||
601 | .enable_reg = OMAP1_IO_ADDRESS(COM_CLK_DIV_CTRL_SEL), | ||
602 | .enable_bit = COM_ULPD_PLL_CLK_REQ, | ||
603 | .set_rate = &omap1_set_ext_clk_rate, | ||
604 | .round_rate = &omap1_round_ext_clk_rate, | ||
605 | .init = &omap1_init_ext_clk, | ||
606 | }; | ||
607 | |||
608 | static struct clk bclk_1510 = { | ||
609 | .name = "bclk", | ||
610 | .ops = &clkops_generic, | ||
611 | /* Direct from ULPD, no parent. May be enabled by ext hardware. */ | ||
612 | .rate = 12000000, | ||
613 | .flags = RATE_FIXED, | ||
614 | }; | ||
615 | |||
616 | static struct clk bclk_16xx = { | ||
617 | .name = "bclk", | ||
618 | .ops = &clkops_generic, | ||
619 | /* Direct from ULPD, no parent. May be enabled by ext hardware. */ | ||
620 | .enable_reg = OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL), | ||
621 | .enable_bit = SWD_ULPD_PLL_CLK_REQ, | ||
622 | .set_rate = &omap1_set_ext_clk_rate, | ||
623 | .round_rate = &omap1_round_ext_clk_rate, | ||
624 | .init = &omap1_init_ext_clk, | ||
625 | }; | ||
626 | |||
627 | static struct clk mmc1_ck = { | ||
628 | .name = "mmc_ck", | ||
629 | .ops = &clkops_generic, | ||
630 | /* Functional clock is direct from ULPD, interface clock is ARMPER */ | ||
631 | .parent = &armper_ck.clk, | ||
632 | .rate = 48000000, | ||
633 | .flags = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, | ||
634 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), | ||
635 | .enable_bit = 23, | ||
636 | }; | ||
637 | |||
638 | static struct clk mmc2_ck = { | ||
639 | .name = "mmc_ck", | ||
640 | .id = 1, | ||
641 | .ops = &clkops_generic, | ||
642 | /* Functional clock is direct from ULPD, interface clock is ARMPER */ | ||
643 | .parent = &armper_ck.clk, | ||
644 | .rate = 48000000, | ||
645 | .flags = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, | ||
646 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), | ||
647 | .enable_bit = 20, | ||
648 | }; | ||
649 | |||
650 | static struct clk mmc3_ck = { | ||
651 | .name = "mmc_ck", | ||
652 | .id = 2, | ||
653 | .ops = &clkops_generic, | ||
654 | /* Functional clock is direct from ULPD, interface clock is ARMPER */ | ||
655 | .parent = &armper_ck.clk, | ||
656 | .rate = 48000000, | ||
657 | .flags = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, | ||
658 | .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), | ||
659 | .enable_bit = 12, | ||
660 | }; | ||
661 | |||
662 | static struct clk virtual_ck_mpu = { | ||
663 | .name = "mpu", | ||
664 | .ops = &clkops_null, | ||
665 | .parent = &arm_ck, /* Is smarter alias for */ | ||
666 | .recalc = &followparent_recalc, | ||
667 | .set_rate = &omap1_select_table_rate, | ||
668 | .round_rate = &omap1_round_to_table_rate, | ||
669 | }; | ||
670 | |||
671 | /* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK | ||
672 | remains active during MPU idle whenever this is enabled */ | ||
673 | static struct clk i2c_fck = { | ||
674 | .name = "i2c_fck", | ||
675 | .id = 1, | ||
676 | .ops = &clkops_null, | ||
677 | .flags = CLOCK_NO_IDLE_PARENT, | ||
678 | .parent = &armxor_ck.clk, | ||
679 | .recalc = &followparent_recalc, | ||
680 | }; | ||
681 | |||
682 | static struct clk i2c_ick = { | ||
683 | .name = "i2c_ick", | ||
684 | .id = 1, | ||
685 | .ops = &clkops_null, | ||
686 | .flags = CLOCK_NO_IDLE_PARENT, | ||
687 | .parent = &armper_ck.clk, | ||
688 | .recalc = &followparent_recalc, | ||
689 | }; | ||
690 | 112 | ||
691 | #endif | 113 | #endif |
diff --git a/arch/arm/mach-omap1/clock_data.c b/arch/arm/mach-omap1/clock_data.c new file mode 100644 index 000000000000..ab995a9c606c --- /dev/null +++ b/arch/arm/mach-omap1/clock_data.c | |||
@@ -0,0 +1,843 @@ | |||
1 | /* | ||
2 | * linux/arch/arm/mach-omap1/clock_data.c | ||
3 | * | ||
4 | * Copyright (C) 2004 - 2005, 2009 Nokia corporation | ||
5 | * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> | ||
6 | * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #include <linux/kernel.h> | ||
14 | #include <linux/clk.h> | ||
15 | #include <linux/io.h> | ||
16 | |||
17 | #include <asm/mach-types.h> /* for machine_is_* */ | ||
18 | |||
19 | #include <plat/clock.h> | ||
20 | #include <plat/cpu.h> | ||
21 | #include <plat/clkdev_omap.h> | ||
22 | #include <plat/usb.h> /* for OTG_BASE */ | ||
23 | |||
24 | #include "clock.h" | ||
25 | |||
26 | /*------------------------------------------------------------------------ | ||
27 | * Omap1 clocks | ||
28 | *-------------------------------------------------------------------------*/ | ||
29 | |||
30 | /* XXX is this necessary? */ | ||
31 | static struct clk dummy_ck = { | ||
32 | .name = "dummy", | ||
33 | .ops = &clkops_dummy, | ||
34 | .flags = RATE_FIXED, | ||
35 | }; | ||
36 | |||
37 | static struct clk ck_ref = { | ||
38 | .name = "ck_ref", | ||
39 | .ops = &clkops_null, | ||
40 | .rate = 12000000, | ||
41 | }; | ||
42 | |||
43 | static struct clk ck_dpll1 = { | ||
44 | .name = "ck_dpll1", | ||
45 | .ops = &clkops_null, | ||
46 | .parent = &ck_ref, | ||
47 | }; | ||
48 | |||
49 | /* | ||
50 | * FIXME: This clock seems to be necessary but no-one has asked for its | ||
51 | * activation. [ FIX: SoSSI, SSR ] | ||
52 | */ | ||
53 | static struct arm_idlect1_clk ck_dpll1out = { | ||
54 | .clk = { | ||
55 | .name = "ck_dpll1out", | ||
56 | .ops = &clkops_generic, | ||
57 | .parent = &ck_dpll1, | ||
58 | .flags = CLOCK_IDLE_CONTROL | ENABLE_REG_32BIT | | ||
59 | ENABLE_ON_INIT, | ||
60 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), | ||
61 | .enable_bit = EN_CKOUT_ARM, | ||
62 | .recalc = &followparent_recalc, | ||
63 | }, | ||
64 | .idlect_shift = 12, | ||
65 | }; | ||
66 | |||
67 | static struct clk sossi_ck = { | ||
68 | .name = "ck_sossi", | ||
69 | .ops = &clkops_generic, | ||
70 | .parent = &ck_dpll1out.clk, | ||
71 | .flags = CLOCK_NO_IDLE_PARENT | ENABLE_REG_32BIT, | ||
72 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1), | ||
73 | .enable_bit = 16, | ||
74 | .recalc = &omap1_sossi_recalc, | ||
75 | .set_rate = &omap1_set_sossi_rate, | ||
76 | }; | ||
77 | |||
78 | static struct clk arm_ck = { | ||
79 | .name = "arm_ck", | ||
80 | .ops = &clkops_null, | ||
81 | .parent = &ck_dpll1, | ||
82 | .rate_offset = CKCTL_ARMDIV_OFFSET, | ||
83 | .recalc = &omap1_ckctl_recalc, | ||
84 | .round_rate = omap1_clk_round_rate_ckctl_arm, | ||
85 | .set_rate = omap1_clk_set_rate_ckctl_arm, | ||
86 | }; | ||
87 | |||
88 | static struct arm_idlect1_clk armper_ck = { | ||
89 | .clk = { | ||
90 | .name = "armper_ck", | ||
91 | .ops = &clkops_generic, | ||
92 | .parent = &ck_dpll1, | ||
93 | .flags = CLOCK_IDLE_CONTROL, | ||
94 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), | ||
95 | .enable_bit = EN_PERCK, | ||
96 | .rate_offset = CKCTL_PERDIV_OFFSET, | ||
97 | .recalc = &omap1_ckctl_recalc, | ||
98 | .round_rate = omap1_clk_round_rate_ckctl_arm, | ||
99 | .set_rate = omap1_clk_set_rate_ckctl_arm, | ||
100 | }, | ||
101 | .idlect_shift = 2, | ||
102 | }; | ||
103 | |||
104 | /* | ||
105 | * FIXME: This clock seems to be necessary but no-one has asked for its | ||
106 | * activation. [ GPIO code for 1510 ] | ||
107 | */ | ||
108 | static struct clk arm_gpio_ck = { | ||
109 | .name = "arm_gpio_ck", | ||
110 | .ops = &clkops_generic, | ||
111 | .parent = &ck_dpll1, | ||
112 | .flags = ENABLE_ON_INIT, | ||
113 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), | ||
114 | .enable_bit = EN_GPIOCK, | ||
115 | .recalc = &followparent_recalc, | ||
116 | }; | ||
117 | |||
118 | static struct arm_idlect1_clk armxor_ck = { | ||
119 | .clk = { | ||
120 | .name = "armxor_ck", | ||
121 | .ops = &clkops_generic, | ||
122 | .parent = &ck_ref, | ||
123 | .flags = CLOCK_IDLE_CONTROL, | ||
124 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), | ||
125 | .enable_bit = EN_XORPCK, | ||
126 | .recalc = &followparent_recalc, | ||
127 | }, | ||
128 | .idlect_shift = 1, | ||
129 | }; | ||
130 | |||
131 | static struct arm_idlect1_clk armtim_ck = { | ||
132 | .clk = { | ||
133 | .name = "armtim_ck", | ||
134 | .ops = &clkops_generic, | ||
135 | .parent = &ck_ref, | ||
136 | .flags = CLOCK_IDLE_CONTROL, | ||
137 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), | ||
138 | .enable_bit = EN_TIMCK, | ||
139 | .recalc = &followparent_recalc, | ||
140 | }, | ||
141 | .idlect_shift = 9, | ||
142 | }; | ||
143 | |||
144 | static struct arm_idlect1_clk armwdt_ck = { | ||
145 | .clk = { | ||
146 | .name = "armwdt_ck", | ||
147 | .ops = &clkops_generic, | ||
148 | .parent = &ck_ref, | ||
149 | .flags = CLOCK_IDLE_CONTROL, | ||
150 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), | ||
151 | .enable_bit = EN_WDTCK, | ||
152 | .recalc = &omap1_watchdog_recalc, | ||
153 | }, | ||
154 | .idlect_shift = 0, | ||
155 | }; | ||
156 | |||
157 | static struct clk arminth_ck16xx = { | ||
158 | .name = "arminth_ck", | ||
159 | .ops = &clkops_null, | ||
160 | .parent = &arm_ck, | ||
161 | .recalc = &followparent_recalc, | ||
162 | /* Note: On 16xx the frequency can be divided by 2 by programming | ||
163 | * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1 | ||
164 | * | ||
165 | * 1510 version is in TC clocks. | ||
166 | */ | ||
167 | }; | ||
168 | |||
169 | static struct clk dsp_ck = { | ||
170 | .name = "dsp_ck", | ||
171 | .ops = &clkops_generic, | ||
172 | .parent = &ck_dpll1, | ||
173 | .enable_reg = OMAP1_IO_ADDRESS(ARM_CKCTL), | ||
174 | .enable_bit = EN_DSPCK, | ||
175 | .rate_offset = CKCTL_DSPDIV_OFFSET, | ||
176 | .recalc = &omap1_ckctl_recalc, | ||
177 | .round_rate = omap1_clk_round_rate_ckctl_arm, | ||
178 | .set_rate = omap1_clk_set_rate_ckctl_arm, | ||
179 | }; | ||
180 | |||
181 | static struct clk dspmmu_ck = { | ||
182 | .name = "dspmmu_ck", | ||
183 | .ops = &clkops_null, | ||
184 | .parent = &ck_dpll1, | ||
185 | .rate_offset = CKCTL_DSPMMUDIV_OFFSET, | ||
186 | .recalc = &omap1_ckctl_recalc, | ||
187 | .round_rate = omap1_clk_round_rate_ckctl_arm, | ||
188 | .set_rate = omap1_clk_set_rate_ckctl_arm, | ||
189 | }; | ||
190 | |||
191 | static struct clk dspper_ck = { | ||
192 | .name = "dspper_ck", | ||
193 | .ops = &clkops_dspck, | ||
194 | .parent = &ck_dpll1, | ||
195 | .enable_reg = DSP_IDLECT2, | ||
196 | .enable_bit = EN_PERCK, | ||
197 | .rate_offset = CKCTL_PERDIV_OFFSET, | ||
198 | .recalc = &omap1_ckctl_recalc_dsp_domain, | ||
199 | .round_rate = omap1_clk_round_rate_ckctl_arm, | ||
200 | .set_rate = &omap1_clk_set_rate_dsp_domain, | ||
201 | }; | ||
202 | |||
203 | static struct clk dspxor_ck = { | ||
204 | .name = "dspxor_ck", | ||
205 | .ops = &clkops_dspck, | ||
206 | .parent = &ck_ref, | ||
207 | .enable_reg = DSP_IDLECT2, | ||
208 | .enable_bit = EN_XORPCK, | ||
209 | .recalc = &followparent_recalc, | ||
210 | }; | ||
211 | |||
212 | static struct clk dsptim_ck = { | ||
213 | .name = "dsptim_ck", | ||
214 | .ops = &clkops_dspck, | ||
215 | .parent = &ck_ref, | ||
216 | .enable_reg = DSP_IDLECT2, | ||
217 | .enable_bit = EN_DSPTIMCK, | ||
218 | .recalc = &followparent_recalc, | ||
219 | }; | ||
220 | |||
221 | /* Tie ARM_IDLECT1:IDLIF_ARM to this logical clock structure */ | ||
222 | static struct arm_idlect1_clk tc_ck = { | ||
223 | .clk = { | ||
224 | .name = "tc_ck", | ||
225 | .ops = &clkops_null, | ||
226 | .parent = &ck_dpll1, | ||
227 | .flags = CLOCK_IDLE_CONTROL, | ||
228 | .rate_offset = CKCTL_TCDIV_OFFSET, | ||
229 | .recalc = &omap1_ckctl_recalc, | ||
230 | .round_rate = omap1_clk_round_rate_ckctl_arm, | ||
231 | .set_rate = omap1_clk_set_rate_ckctl_arm, | ||
232 | }, | ||
233 | .idlect_shift = 6, | ||
234 | }; | ||
235 | |||
236 | static struct clk arminth_ck1510 = { | ||
237 | .name = "arminth_ck", | ||
238 | .ops = &clkops_null, | ||
239 | .parent = &tc_ck.clk, | ||
240 | .recalc = &followparent_recalc, | ||
241 | /* Note: On 1510 the frequency follows TC_CK | ||
242 | * | ||
243 | * 16xx version is in MPU clocks. | ||
244 | */ | ||
245 | }; | ||
246 | |||
247 | static struct clk tipb_ck = { | ||
248 | /* No-idle controlled by "tc_ck" */ | ||
249 | .name = "tipb_ck", | ||
250 | .ops = &clkops_null, | ||
251 | .parent = &tc_ck.clk, | ||
252 | .recalc = &followparent_recalc, | ||
253 | }; | ||
254 | |||
255 | static struct clk l3_ocpi_ck = { | ||
256 | /* No-idle controlled by "tc_ck" */ | ||
257 | .name = "l3_ocpi_ck", | ||
258 | .ops = &clkops_generic, | ||
259 | .parent = &tc_ck.clk, | ||
260 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3), | ||
261 | .enable_bit = EN_OCPI_CK, | ||
262 | .recalc = &followparent_recalc, | ||
263 | }; | ||
264 | |||
265 | static struct clk tc1_ck = { | ||
266 | .name = "tc1_ck", | ||
267 | .ops = &clkops_generic, | ||
268 | .parent = &tc_ck.clk, | ||
269 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3), | ||
270 | .enable_bit = EN_TC1_CK, | ||
271 | .recalc = &followparent_recalc, | ||
272 | }; | ||
273 | |||
274 | /* | ||
275 | * FIXME: This clock seems to be necessary but no-one has asked for its | ||
276 | * activation. [ pm.c (SRAM), CCP, Camera ] | ||
277 | */ | ||
278 | static struct clk tc2_ck = { | ||
279 | .name = "tc2_ck", | ||
280 | .ops = &clkops_generic, | ||
281 | .parent = &tc_ck.clk, | ||
282 | .flags = ENABLE_ON_INIT, | ||
283 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3), | ||
284 | .enable_bit = EN_TC2_CK, | ||
285 | .recalc = &followparent_recalc, | ||
286 | }; | ||
287 | |||
288 | static struct clk dma_ck = { | ||
289 | /* No-idle controlled by "tc_ck" */ | ||
290 | .name = "dma_ck", | ||
291 | .ops = &clkops_null, | ||
292 | .parent = &tc_ck.clk, | ||
293 | .recalc = &followparent_recalc, | ||
294 | }; | ||
295 | |||
296 | static struct clk dma_lcdfree_ck = { | ||
297 | .name = "dma_lcdfree_ck", | ||
298 | .ops = &clkops_null, | ||
299 | .parent = &tc_ck.clk, | ||
300 | .recalc = &followparent_recalc, | ||
301 | }; | ||
302 | |||
303 | static struct arm_idlect1_clk api_ck = { | ||
304 | .clk = { | ||
305 | .name = "api_ck", | ||
306 | .ops = &clkops_generic, | ||
307 | .parent = &tc_ck.clk, | ||
308 | .flags = CLOCK_IDLE_CONTROL, | ||
309 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), | ||
310 | .enable_bit = EN_APICK, | ||
311 | .recalc = &followparent_recalc, | ||
312 | }, | ||
313 | .idlect_shift = 8, | ||
314 | }; | ||
315 | |||
316 | static struct arm_idlect1_clk lb_ck = { | ||
317 | .clk = { | ||
318 | .name = "lb_ck", | ||
319 | .ops = &clkops_generic, | ||
320 | .parent = &tc_ck.clk, | ||
321 | .flags = CLOCK_IDLE_CONTROL, | ||
322 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), | ||
323 | .enable_bit = EN_LBCK, | ||
324 | .recalc = &followparent_recalc, | ||
325 | }, | ||
326 | .idlect_shift = 4, | ||
327 | }; | ||
328 | |||
329 | static struct clk rhea1_ck = { | ||
330 | .name = "rhea1_ck", | ||
331 | .ops = &clkops_null, | ||
332 | .parent = &tc_ck.clk, | ||
333 | .recalc = &followparent_recalc, | ||
334 | }; | ||
335 | |||
336 | static struct clk rhea2_ck = { | ||
337 | .name = "rhea2_ck", | ||
338 | .ops = &clkops_null, | ||
339 | .parent = &tc_ck.clk, | ||
340 | .recalc = &followparent_recalc, | ||
341 | }; | ||
342 | |||
343 | static struct clk lcd_ck_16xx = { | ||
344 | .name = "lcd_ck", | ||
345 | .ops = &clkops_generic, | ||
346 | .parent = &ck_dpll1, | ||
347 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), | ||
348 | .enable_bit = EN_LCDCK, | ||
349 | .rate_offset = CKCTL_LCDDIV_OFFSET, | ||
350 | .recalc = &omap1_ckctl_recalc, | ||
351 | .round_rate = omap1_clk_round_rate_ckctl_arm, | ||
352 | .set_rate = omap1_clk_set_rate_ckctl_arm, | ||
353 | }; | ||
354 | |||
355 | static struct arm_idlect1_clk lcd_ck_1510 = { | ||
356 | .clk = { | ||
357 | .name = "lcd_ck", | ||
358 | .ops = &clkops_generic, | ||
359 | .parent = &ck_dpll1, | ||
360 | .flags = CLOCK_IDLE_CONTROL, | ||
361 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), | ||
362 | .enable_bit = EN_LCDCK, | ||
363 | .rate_offset = CKCTL_LCDDIV_OFFSET, | ||
364 | .recalc = &omap1_ckctl_recalc, | ||
365 | .round_rate = omap1_clk_round_rate_ckctl_arm, | ||
366 | .set_rate = omap1_clk_set_rate_ckctl_arm, | ||
367 | }, | ||
368 | .idlect_shift = 3, | ||
369 | }; | ||
370 | |||
371 | static struct clk uart1_1510 = { | ||
372 | .name = "uart1_ck", | ||
373 | .ops = &clkops_null, | ||
374 | /* Direct from ULPD, no real parent */ | ||
375 | .parent = &armper_ck.clk, | ||
376 | .rate = 12000000, | ||
377 | .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, | ||
378 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), | ||
379 | .enable_bit = 29, /* Chooses between 12MHz and 48MHz */ | ||
380 | .set_rate = &omap1_set_uart_rate, | ||
381 | .recalc = &omap1_uart_recalc, | ||
382 | }; | ||
383 | |||
384 | static struct uart_clk uart1_16xx = { | ||
385 | .clk = { | ||
386 | .name = "uart1_ck", | ||
387 | .ops = &clkops_uart, | ||
388 | /* Direct from ULPD, no real parent */ | ||
389 | .parent = &armper_ck.clk, | ||
390 | .rate = 48000000, | ||
391 | .flags = RATE_FIXED | ENABLE_REG_32BIT | | ||
392 | CLOCK_NO_IDLE_PARENT, | ||
393 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), | ||
394 | .enable_bit = 29, | ||
395 | }, | ||
396 | .sysc_addr = 0xfffb0054, | ||
397 | }; | ||
398 | |||
399 | static struct clk uart2_ck = { | ||
400 | .name = "uart2_ck", | ||
401 | .ops = &clkops_null, | ||
402 | /* Direct from ULPD, no real parent */ | ||
403 | .parent = &armper_ck.clk, | ||
404 | .rate = 12000000, | ||
405 | .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, | ||
406 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), | ||
407 | .enable_bit = 30, /* Chooses between 12MHz and 48MHz */ | ||
408 | .set_rate = &omap1_set_uart_rate, | ||
409 | .recalc = &omap1_uart_recalc, | ||
410 | }; | ||
411 | |||
412 | static struct clk uart3_1510 = { | ||
413 | .name = "uart3_ck", | ||
414 | .ops = &clkops_null, | ||
415 | /* Direct from ULPD, no real parent */ | ||
416 | .parent = &armper_ck.clk, | ||
417 | .rate = 12000000, | ||
418 | .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, | ||
419 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), | ||
420 | .enable_bit = 31, /* Chooses between 12MHz and 48MHz */ | ||
421 | .set_rate = &omap1_set_uart_rate, | ||
422 | .recalc = &omap1_uart_recalc, | ||
423 | }; | ||
424 | |||
425 | static struct uart_clk uart3_16xx = { | ||
426 | .clk = { | ||
427 | .name = "uart3_ck", | ||
428 | .ops = &clkops_uart, | ||
429 | /* Direct from ULPD, no real parent */ | ||
430 | .parent = &armper_ck.clk, | ||
431 | .rate = 48000000, | ||
432 | .flags = RATE_FIXED | ENABLE_REG_32BIT | | ||
433 | CLOCK_NO_IDLE_PARENT, | ||
434 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), | ||
435 | .enable_bit = 31, | ||
436 | }, | ||
437 | .sysc_addr = 0xfffb9854, | ||
438 | }; | ||
439 | |||
440 | static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */ | ||
441 | .name = "usb_clko", | ||
442 | .ops = &clkops_generic, | ||
443 | /* Direct from ULPD, no parent */ | ||
444 | .rate = 6000000, | ||
445 | .flags = RATE_FIXED | ENABLE_REG_32BIT, | ||
446 | .enable_reg = OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL), | ||
447 | .enable_bit = USB_MCLK_EN_BIT, | ||
448 | }; | ||
449 | |||
450 | static struct clk usb_hhc_ck1510 = { | ||
451 | .name = "usb_hhc_ck", | ||
452 | .ops = &clkops_generic, | ||
453 | /* Direct from ULPD, no parent */ | ||
454 | .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */ | ||
455 | .flags = RATE_FIXED | ENABLE_REG_32BIT, | ||
456 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), | ||
457 | .enable_bit = USB_HOST_HHC_UHOST_EN, | ||
458 | }; | ||
459 | |||
460 | static struct clk usb_hhc_ck16xx = { | ||
461 | .name = "usb_hhc_ck", | ||
462 | .ops = &clkops_generic, | ||
463 | /* Direct from ULPD, no parent */ | ||
464 | .rate = 48000000, | ||
465 | /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */ | ||
466 | .flags = RATE_FIXED | ENABLE_REG_32BIT, | ||
467 | .enable_reg = OMAP1_IO_ADDRESS(OTG_BASE + 0x08), /* OTG_SYSCON_2 */ | ||
468 | .enable_bit = 8 /* UHOST_EN */, | ||
469 | }; | ||
470 | |||
471 | static struct clk usb_dc_ck = { | ||
472 | .name = "usb_dc_ck", | ||
473 | .ops = &clkops_generic, | ||
474 | /* Direct from ULPD, no parent */ | ||
475 | .rate = 48000000, | ||
476 | .flags = RATE_FIXED, | ||
477 | .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), | ||
478 | .enable_bit = 4, | ||
479 | }; | ||
480 | |||
481 | static struct clk usb_dc_ck7xx = { | ||
482 | .name = "usb_dc_ck", | ||
483 | .ops = &clkops_generic, | ||
484 | /* Direct from ULPD, no parent */ | ||
485 | .rate = 48000000, | ||
486 | .flags = RATE_FIXED, | ||
487 | .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), | ||
488 | .enable_bit = 8, | ||
489 | }; | ||
490 | |||
491 | static struct clk mclk_1510 = { | ||
492 | .name = "mclk", | ||
493 | .ops = &clkops_generic, | ||
494 | /* Direct from ULPD, no parent. May be enabled by ext hardware. */ | ||
495 | .rate = 12000000, | ||
496 | .flags = RATE_FIXED, | ||
497 | .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), | ||
498 | .enable_bit = 6, | ||
499 | }; | ||
500 | |||
501 | static struct clk mclk_16xx = { | ||
502 | .name = "mclk", | ||
503 | .ops = &clkops_generic, | ||
504 | /* Direct from ULPD, no parent. May be enabled by ext hardware. */ | ||
505 | .enable_reg = OMAP1_IO_ADDRESS(COM_CLK_DIV_CTRL_SEL), | ||
506 | .enable_bit = COM_ULPD_PLL_CLK_REQ, | ||
507 | .set_rate = &omap1_set_ext_clk_rate, | ||
508 | .round_rate = &omap1_round_ext_clk_rate, | ||
509 | .init = &omap1_init_ext_clk, | ||
510 | }; | ||
511 | |||
512 | static struct clk bclk_1510 = { | ||
513 | .name = "bclk", | ||
514 | .ops = &clkops_generic, | ||
515 | /* Direct from ULPD, no parent. May be enabled by ext hardware. */ | ||
516 | .rate = 12000000, | ||
517 | .flags = RATE_FIXED, | ||
518 | }; | ||
519 | |||
520 | static struct clk bclk_16xx = { | ||
521 | .name = "bclk", | ||
522 | .ops = &clkops_generic, | ||
523 | /* Direct from ULPD, no parent. May be enabled by ext hardware. */ | ||
524 | .enable_reg = OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL), | ||
525 | .enable_bit = SWD_ULPD_PLL_CLK_REQ, | ||
526 | .set_rate = &omap1_set_ext_clk_rate, | ||
527 | .round_rate = &omap1_round_ext_clk_rate, | ||
528 | .init = &omap1_init_ext_clk, | ||
529 | }; | ||
530 | |||
531 | static struct clk mmc1_ck = { | ||
532 | .name = "mmc_ck", | ||
533 | .ops = &clkops_generic, | ||
534 | /* Functional clock is direct from ULPD, interface clock is ARMPER */ | ||
535 | .parent = &armper_ck.clk, | ||
536 | .rate = 48000000, | ||
537 | .flags = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, | ||
538 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), | ||
539 | .enable_bit = 23, | ||
540 | }; | ||
541 | |||
542 | static struct clk mmc2_ck = { | ||
543 | .name = "mmc_ck", | ||
544 | .id = 1, | ||
545 | .ops = &clkops_generic, | ||
546 | /* Functional clock is direct from ULPD, interface clock is ARMPER */ | ||
547 | .parent = &armper_ck.clk, | ||
548 | .rate = 48000000, | ||
549 | .flags = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, | ||
550 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), | ||
551 | .enable_bit = 20, | ||
552 | }; | ||
553 | |||
554 | static struct clk mmc3_ck = { | ||
555 | .name = "mmc_ck", | ||
556 | .id = 2, | ||
557 | .ops = &clkops_generic, | ||
558 | /* Functional clock is direct from ULPD, interface clock is ARMPER */ | ||
559 | .parent = &armper_ck.clk, | ||
560 | .rate = 48000000, | ||
561 | .flags = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, | ||
562 | .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), | ||
563 | .enable_bit = 12, | ||
564 | }; | ||
565 | |||
566 | static struct clk virtual_ck_mpu = { | ||
567 | .name = "mpu", | ||
568 | .ops = &clkops_null, | ||
569 | .parent = &arm_ck, /* Is smarter alias for */ | ||
570 | .recalc = &followparent_recalc, | ||
571 | .set_rate = &omap1_select_table_rate, | ||
572 | .round_rate = &omap1_round_to_table_rate, | ||
573 | }; | ||
574 | |||
575 | /* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK | ||
576 | remains active during MPU idle whenever this is enabled */ | ||
577 | static struct clk i2c_fck = { | ||
578 | .name = "i2c_fck", | ||
579 | .id = 1, | ||
580 | .ops = &clkops_null, | ||
581 | .flags = CLOCK_NO_IDLE_PARENT, | ||
582 | .parent = &armxor_ck.clk, | ||
583 | .recalc = &followparent_recalc, | ||
584 | }; | ||
585 | |||
586 | static struct clk i2c_ick = { | ||
587 | .name = "i2c_ick", | ||
588 | .id = 1, | ||
589 | .ops = &clkops_null, | ||
590 | .flags = CLOCK_NO_IDLE_PARENT, | ||
591 | .parent = &armper_ck.clk, | ||
592 | .recalc = &followparent_recalc, | ||
593 | }; | ||
594 | |||
595 | /* | ||
596 | * clkdev integration | ||
597 | */ | ||
598 | |||
599 | static struct omap_clk omap_clks[] = { | ||
600 | /* non-ULPD clocks */ | ||
601 | CLK(NULL, "ck_ref", &ck_ref, CK_16XX | CK_1510 | CK_310 | CK_7XX), | ||
602 | CLK(NULL, "ck_dpll1", &ck_dpll1, CK_16XX | CK_1510 | CK_310), | ||
603 | /* CK_GEN1 clocks */ | ||
604 | CLK(NULL, "ck_dpll1out", &ck_dpll1out.clk, CK_16XX), | ||
605 | CLK(NULL, "ck_sossi", &sossi_ck, CK_16XX), | ||
606 | CLK(NULL, "arm_ck", &arm_ck, CK_16XX | CK_1510 | CK_310), | ||
607 | CLK(NULL, "armper_ck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310), | ||
608 | CLK(NULL, "arm_gpio_ck", &arm_gpio_ck, CK_1510 | CK_310), | ||
609 | CLK(NULL, "armxor_ck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX), | ||
610 | CLK(NULL, "armtim_ck", &armtim_ck.clk, CK_16XX | CK_1510 | CK_310), | ||
611 | CLK("omap_wdt", "fck", &armwdt_ck.clk, CK_16XX | CK_1510 | CK_310), | ||
612 | CLK("omap_wdt", "ick", &armper_ck.clk, CK_16XX), | ||
613 | CLK("omap_wdt", "ick", &dummy_ck, CK_1510 | CK_310), | ||
614 | CLK(NULL, "arminth_ck", &arminth_ck1510, CK_1510 | CK_310), | ||
615 | CLK(NULL, "arminth_ck", &arminth_ck16xx, CK_16XX), | ||
616 | /* CK_GEN2 clocks */ | ||
617 | CLK(NULL, "dsp_ck", &dsp_ck, CK_16XX | CK_1510 | CK_310), | ||
618 | CLK(NULL, "dspmmu_ck", &dspmmu_ck, CK_16XX | CK_1510 | CK_310), | ||
619 | CLK(NULL, "dspper_ck", &dspper_ck, CK_16XX | CK_1510 | CK_310), | ||
620 | CLK(NULL, "dspxor_ck", &dspxor_ck, CK_16XX | CK_1510 | CK_310), | ||
621 | CLK(NULL, "dsptim_ck", &dsptim_ck, CK_16XX | CK_1510 | CK_310), | ||
622 | /* CK_GEN3 clocks */ | ||
623 | CLK(NULL, "tc_ck", &tc_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX), | ||
624 | CLK(NULL, "tipb_ck", &tipb_ck, CK_1510 | CK_310), | ||
625 | CLK(NULL, "l3_ocpi_ck", &l3_ocpi_ck, CK_16XX | CK_7XX), | ||
626 | CLK(NULL, "tc1_ck", &tc1_ck, CK_16XX), | ||
627 | CLK(NULL, "tc2_ck", &tc2_ck, CK_16XX), | ||
628 | CLK(NULL, "dma_ck", &dma_ck, CK_16XX | CK_1510 | CK_310), | ||
629 | CLK(NULL, "dma_lcdfree_ck", &dma_lcdfree_ck, CK_16XX), | ||
630 | CLK(NULL, "api_ck", &api_ck.clk, CK_16XX | CK_1510 | CK_310), | ||
631 | CLK(NULL, "lb_ck", &lb_ck.clk, CK_1510 | CK_310), | ||
632 | CLK(NULL, "rhea1_ck", &rhea1_ck, CK_16XX), | ||
633 | CLK(NULL, "rhea2_ck", &rhea2_ck, CK_16XX), | ||
634 | CLK(NULL, "lcd_ck", &lcd_ck_16xx, CK_16XX | CK_7XX), | ||
635 | CLK(NULL, "lcd_ck", &lcd_ck_1510.clk, CK_1510 | CK_310), | ||
636 | /* ULPD clocks */ | ||
637 | CLK(NULL, "uart1_ck", &uart1_1510, CK_1510 | CK_310), | ||
638 | CLK(NULL, "uart1_ck", &uart1_16xx.clk, CK_16XX), | ||
639 | CLK(NULL, "uart2_ck", &uart2_ck, CK_16XX | CK_1510 | CK_310), | ||
640 | CLK(NULL, "uart3_ck", &uart3_1510, CK_1510 | CK_310), | ||
641 | CLK(NULL, "uart3_ck", &uart3_16xx.clk, CK_16XX), | ||
642 | CLK(NULL, "usb_clko", &usb_clko, CK_16XX | CK_1510 | CK_310), | ||
643 | CLK(NULL, "usb_hhc_ck", &usb_hhc_ck1510, CK_1510 | CK_310), | ||
644 | CLK(NULL, "usb_hhc_ck", &usb_hhc_ck16xx, CK_16XX), | ||
645 | CLK(NULL, "usb_dc_ck", &usb_dc_ck, CK_16XX), | ||
646 | CLK(NULL, "usb_dc_ck", &usb_dc_ck7xx, CK_7XX), | ||
647 | CLK(NULL, "mclk", &mclk_1510, CK_1510 | CK_310), | ||
648 | CLK(NULL, "mclk", &mclk_16xx, CK_16XX), | ||
649 | CLK(NULL, "bclk", &bclk_1510, CK_1510 | CK_310), | ||
650 | CLK(NULL, "bclk", &bclk_16xx, CK_16XX), | ||
651 | CLK("mmci-omap.0", "fck", &mmc1_ck, CK_16XX | CK_1510 | CK_310), | ||
652 | CLK("mmci-omap.0", "fck", &mmc3_ck, CK_7XX), | ||
653 | CLK("mmci-omap.0", "ick", &armper_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX), | ||
654 | CLK("mmci-omap.1", "fck", &mmc2_ck, CK_16XX), | ||
655 | CLK("mmci-omap.1", "ick", &armper_ck.clk, CK_16XX), | ||
656 | /* Virtual clocks */ | ||
657 | CLK(NULL, "mpu", &virtual_ck_mpu, CK_16XX | CK_1510 | CK_310), | ||
658 | CLK("i2c_omap.1", "fck", &i2c_fck, CK_16XX | CK_1510 | CK_310 | CK_7XX), | ||
659 | CLK("i2c_omap.1", "ick", &i2c_ick, CK_16XX), | ||
660 | CLK("i2c_omap.1", "ick", &dummy_ck, CK_1510 | CK_310 | CK_7XX), | ||
661 | CLK("omap_uwire", "fck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310), | ||
662 | CLK("omap-mcbsp.1", "ick", &dspper_ck, CK_16XX), | ||
663 | CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_1510 | CK_310), | ||
664 | CLK("omap-mcbsp.2", "ick", &armper_ck.clk, CK_16XX), | ||
665 | CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_1510 | CK_310), | ||
666 | CLK("omap-mcbsp.3", "ick", &dspper_ck, CK_16XX), | ||
667 | CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_1510 | CK_310), | ||
668 | CLK("omap-mcbsp.1", "fck", &dspxor_ck, CK_16XX | CK_1510 | CK_310), | ||
669 | CLK("omap-mcbsp.2", "fck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310), | ||
670 | CLK("omap-mcbsp.3", "fck", &dspxor_ck, CK_16XX | CK_1510 | CK_310), | ||
671 | }; | ||
672 | |||
673 | /* | ||
674 | * init | ||
675 | */ | ||
676 | |||
677 | static struct clk_functions omap1_clk_functions __initdata = { | ||
678 | .clk_enable = omap1_clk_enable, | ||
679 | .clk_disable = omap1_clk_disable, | ||
680 | .clk_round_rate = omap1_clk_round_rate, | ||
681 | .clk_set_rate = omap1_clk_set_rate, | ||
682 | .clk_disable_unused = omap1_clk_disable_unused, | ||
683 | }; | ||
684 | |||
685 | int __init omap1_clk_init(void) | ||
686 | { | ||
687 | struct omap_clk *c; | ||
688 | const struct omap_clock_config *info; | ||
689 | int crystal_type = 0; /* Default 12 MHz */ | ||
690 | u32 reg, cpu_mask; | ||
691 | |||
692 | #ifdef CONFIG_DEBUG_LL | ||
693 | /* | ||
694 | * Resets some clocks that may be left on from bootloader, | ||
695 | * but leaves serial clocks on. | ||
696 | */ | ||
697 | omap_writel(0x3 << 29, MOD_CONF_CTRL_0); | ||
698 | #endif | ||
699 | |||
700 | /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */ | ||
701 | reg = omap_readw(SOFT_REQ_REG) & (1 << 4); | ||
702 | omap_writew(reg, SOFT_REQ_REG); | ||
703 | if (!cpu_is_omap15xx()) | ||
704 | omap_writew(0, SOFT_REQ_REG2); | ||
705 | |||
706 | clk_init(&omap1_clk_functions); | ||
707 | |||
708 | /* By default all idlect1 clocks are allowed to idle */ | ||
709 | arm_idlect1_mask = ~0; | ||
710 | |||
711 | for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++) | ||
712 | clk_preinit(c->lk.clk); | ||
713 | |||
714 | cpu_mask = 0; | ||
715 | if (cpu_is_omap16xx()) | ||
716 | cpu_mask |= CK_16XX; | ||
717 | if (cpu_is_omap1510()) | ||
718 | cpu_mask |= CK_1510; | ||
719 | if (cpu_is_omap7xx()) | ||
720 | cpu_mask |= CK_7XX; | ||
721 | if (cpu_is_omap310()) | ||
722 | cpu_mask |= CK_310; | ||
723 | |||
724 | for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++) | ||
725 | if (c->cpu & cpu_mask) { | ||
726 | clkdev_add(&c->lk); | ||
727 | clk_register(c->lk.clk); | ||
728 | } | ||
729 | |||
730 | /* Pointers to these clocks are needed by code in clock.c */ | ||
731 | api_ck_p = clk_get(NULL, "api_ck"); | ||
732 | ck_dpll1_p = clk_get(NULL, "ck_dpll1"); | ||
733 | ck_ref_p = clk_get(NULL, "ck_ref"); | ||
734 | |||
735 | info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config); | ||
736 | if (info != NULL) { | ||
737 | if (!cpu_is_omap15xx()) | ||
738 | crystal_type = info->system_clock_type; | ||
739 | } | ||
740 | |||
741 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) | ||
742 | ck_ref.rate = 13000000; | ||
743 | #elif defined(CONFIG_ARCH_OMAP16XX) | ||
744 | if (crystal_type == 2) | ||
745 | ck_ref.rate = 19200000; | ||
746 | #endif | ||
747 | |||
748 | pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: " | ||
749 | "0x%04x\n", omap_readw(ARM_SYSST), omap_readw(DPLL_CTL), | ||
750 | omap_readw(ARM_CKCTL)); | ||
751 | |||
752 | /* We want to be in syncronous scalable mode */ | ||
753 | omap_writew(0x1000, ARM_SYSST); | ||
754 | |||
755 | #ifdef CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER | ||
756 | /* Use values set by bootloader. Determine PLL rate and recalculate | ||
757 | * dependent clocks as if kernel had changed PLL or divisors. | ||
758 | */ | ||
759 | { | ||
760 | unsigned pll_ctl_val = omap_readw(DPLL_CTL); | ||
761 | |||
762 | ck_dpll1.rate = ck_ref.rate; /* Base xtal rate */ | ||
763 | if (pll_ctl_val & 0x10) { | ||
764 | /* PLL enabled, apply multiplier and divisor */ | ||
765 | if (pll_ctl_val & 0xf80) | ||
766 | ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7; | ||
767 | ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1; | ||
768 | } else { | ||
769 | /* PLL disabled, apply bypass divisor */ | ||
770 | switch (pll_ctl_val & 0xc) { | ||
771 | case 0: | ||
772 | break; | ||
773 | case 0x4: | ||
774 | ck_dpll1.rate /= 2; | ||
775 | break; | ||
776 | default: | ||
777 | ck_dpll1.rate /= 4; | ||
778 | break; | ||
779 | } | ||
780 | } | ||
781 | } | ||
782 | #else | ||
783 | /* Find the highest supported frequency and enable it */ | ||
784 | if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) { | ||
785 | printk(KERN_ERR "System frequencies not set. Check your config.\n"); | ||
786 | /* Guess sane values (60MHz) */ | ||
787 | omap_writew(0x2290, DPLL_CTL); | ||
788 | omap_writew(cpu_is_omap7xx() ? 0x3005 : 0x1005, ARM_CKCTL); | ||
789 | ck_dpll1.rate = 60000000; | ||
790 | } | ||
791 | #endif | ||
792 | propagate_rate(&ck_dpll1); | ||
793 | /* Cache rates for clocks connected to ck_ref (not dpll1) */ | ||
794 | propagate_rate(&ck_ref); | ||
795 | printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): " | ||
796 | "%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n", | ||
797 | ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10, | ||
798 | ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10, | ||
799 | arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10); | ||
800 | |||
801 | #if defined(CONFIG_MACH_OMAP_PERSEUS2) || defined(CONFIG_MACH_OMAP_FSAMPLE) | ||
802 | /* Select slicer output as OMAP input clock */ | ||
803 | omap_writew(omap_readw(OMAP7XX_PCC_UPLD_CTRL) & ~0x1, OMAP7XX_PCC_UPLD_CTRL); | ||
804 | #endif | ||
805 | |||
806 | /* Amstrad Delta wants BCLK high when inactive */ | ||
807 | if (machine_is_ams_delta()) | ||
808 | omap_writel(omap_readl(ULPD_CLOCK_CTRL) | | ||
809 | (1 << SDW_MCLK_INV_BIT), | ||
810 | ULPD_CLOCK_CTRL); | ||
811 | |||
812 | /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */ | ||
813 | /* (on 730, bit 13 must not be cleared) */ | ||
814 | if (cpu_is_omap7xx()) | ||
815 | omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL); | ||
816 | else | ||
817 | omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL); | ||
818 | |||
819 | /* Put DSP/MPUI into reset until needed */ | ||
820 | omap_writew(0, ARM_RSTCT1); | ||
821 | omap_writew(1, ARM_RSTCT2); | ||
822 | omap_writew(0x400, ARM_IDLECT1); | ||
823 | |||
824 | /* | ||
825 | * According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8) | ||
826 | * of the ARM_IDLECT2 register must be set to zero. The power-on | ||
827 | * default value of this bit is one. | ||
828 | */ | ||
829 | omap_writew(0x0000, ARM_IDLECT2); /* Turn LCD clock off also */ | ||
830 | |||
831 | /* | ||
832 | * Only enable those clocks we will need, let the drivers | ||
833 | * enable other clocks as necessary | ||
834 | */ | ||
835 | clk_enable(&armper_ck.clk); | ||
836 | clk_enable(&armxor_ck.clk); | ||
837 | clk_enable(&armtim_ck.clk); /* This should be done by timer code */ | ||
838 | |||
839 | if (cpu_is_omap15xx()) | ||
840 | clk_enable(&arm_gpio_ck); | ||
841 | |||
842 | return 0; | ||
843 | } | ||
diff --git a/arch/arm/mach-omap1/i2c.c b/arch/arm/mach-omap1/i2c.c new file mode 100644 index 000000000000..1bf4735e27a6 --- /dev/null +++ b/arch/arm/mach-omap1/i2c.c | |||
@@ -0,0 +1,39 @@ | |||
1 | /* | ||
2 | * Helper module for board specific I2C bus registration | ||
3 | * | ||
4 | * Copyright (C) 2009 Nokia Corporation. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or | ||
7 | * modify it under the terms of the GNU General Public License | ||
8 | * version 2 as published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope that it will be useful, but | ||
11 | * WITHOUT ANY WARRANTY; without even the implied warranty of | ||
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | ||
13 | * General Public License for more details. | ||
14 | * | ||
15 | * You should have received a copy of the GNU General Public License | ||
16 | * along with this program; if not, write to the Free Software | ||
17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | ||
18 | * 02110-1301 USA | ||
19 | * | ||
20 | */ | ||
21 | |||
22 | #include <plat/i2c.h> | ||
23 | #include <plat/mux.h> | ||
24 | #include <plat/cpu.h> | ||
25 | |||
26 | int __init omap_register_i2c_bus(int bus_id, u32 clkrate, | ||
27 | struct i2c_board_info const *info, | ||
28 | unsigned len) | ||
29 | { | ||
30 | if (cpu_is_omap7xx()) { | ||
31 | omap_cfg_reg(I2C_7XX_SDA); | ||
32 | omap_cfg_reg(I2C_7XX_SCL); | ||
33 | } else { | ||
34 | omap_cfg_reg(I2C_SDA); | ||
35 | omap_cfg_reg(I2C_SCL); | ||
36 | } | ||
37 | |||
38 | return omap_plat_register_i2c_bus(bus_id, clkrate, info, len); | ||
39 | } | ||
diff --git a/arch/arm/mach-omap1/include/mach/lcd_dma.h b/arch/arm/mach-omap1/include/mach/lcd_dma.h new file mode 100644 index 000000000000..d7a457bbcb7f --- /dev/null +++ b/arch/arm/mach-omap1/include/mach/lcd_dma.h | |||
@@ -0,0 +1,78 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-omap1/include/mach/lcd_dma.h | ||
3 | * | ||
4 | * Extracted from arch/arm/plat-omap/include/plat/dma.h | ||
5 | * Copyright (C) 2003 Nokia Corporation | ||
6 | * Author: Juha Yrjölä <juha.yrjola@nokia.com> | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License as published by | ||
10 | * the Free Software Foundation; either version 2 of the License, or | ||
11 | * (at your option) any later version. | ||
12 | * | ||
13 | * This program is distributed in the hope that it will be useful, | ||
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
16 | * GNU General Public License for more details. | ||
17 | * | ||
18 | * You should have received a copy of the GNU General Public License | ||
19 | * along with this program; if not, write to the Free Software | ||
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
21 | */ | ||
22 | #ifndef __MACH_OMAP1_LCD_DMA_H__ | ||
23 | #define __MACH_OMAP1_LCD_DMA_H__ | ||
24 | |||
25 | /* Hardware registers for LCD DMA */ | ||
26 | #define OMAP1510_DMA_LCD_BASE (0xfffedb00) | ||
27 | #define OMAP1510_DMA_LCD_CTRL (OMAP1510_DMA_LCD_BASE + 0x00) | ||
28 | #define OMAP1510_DMA_LCD_TOP_F1_L (OMAP1510_DMA_LCD_BASE + 0x02) | ||
29 | #define OMAP1510_DMA_LCD_TOP_F1_U (OMAP1510_DMA_LCD_BASE + 0x04) | ||
30 | #define OMAP1510_DMA_LCD_BOT_F1_L (OMAP1510_DMA_LCD_BASE + 0x06) | ||
31 | #define OMAP1510_DMA_LCD_BOT_F1_U (OMAP1510_DMA_LCD_BASE + 0x08) | ||
32 | |||
33 | #define OMAP1610_DMA_LCD_BASE (0xfffee300) | ||
34 | #define OMAP1610_DMA_LCD_CSDP (OMAP1610_DMA_LCD_BASE + 0xc0) | ||
35 | #define OMAP1610_DMA_LCD_CCR (OMAP1610_DMA_LCD_BASE + 0xc2) | ||
36 | #define OMAP1610_DMA_LCD_CTRL (OMAP1610_DMA_LCD_BASE + 0xc4) | ||
37 | #define OMAP1610_DMA_LCD_TOP_B1_L (OMAP1610_DMA_LCD_BASE + 0xc8) | ||
38 | #define OMAP1610_DMA_LCD_TOP_B1_U (OMAP1610_DMA_LCD_BASE + 0xca) | ||
39 | #define OMAP1610_DMA_LCD_BOT_B1_L (OMAP1610_DMA_LCD_BASE + 0xcc) | ||
40 | #define OMAP1610_DMA_LCD_BOT_B1_U (OMAP1610_DMA_LCD_BASE + 0xce) | ||
41 | #define OMAP1610_DMA_LCD_TOP_B2_L (OMAP1610_DMA_LCD_BASE + 0xd0) | ||
42 | #define OMAP1610_DMA_LCD_TOP_B2_U (OMAP1610_DMA_LCD_BASE + 0xd2) | ||
43 | #define OMAP1610_DMA_LCD_BOT_B2_L (OMAP1610_DMA_LCD_BASE + 0xd4) | ||
44 | #define OMAP1610_DMA_LCD_BOT_B2_U (OMAP1610_DMA_LCD_BASE + 0xd6) | ||
45 | #define OMAP1610_DMA_LCD_SRC_EI_B1 (OMAP1610_DMA_LCD_BASE + 0xd8) | ||
46 | #define OMAP1610_DMA_LCD_SRC_FI_B1_L (OMAP1610_DMA_LCD_BASE + 0xda) | ||
47 | #define OMAP1610_DMA_LCD_SRC_EN_B1 (OMAP1610_DMA_LCD_BASE + 0xe0) | ||
48 | #define OMAP1610_DMA_LCD_SRC_FN_B1 (OMAP1610_DMA_LCD_BASE + 0xe4) | ||
49 | #define OMAP1610_DMA_LCD_LCH_CTRL (OMAP1610_DMA_LCD_BASE + 0xea) | ||
50 | #define OMAP1610_DMA_LCD_SRC_FI_B1_U (OMAP1610_DMA_LCD_BASE + 0xf4) | ||
51 | |||
52 | /* LCD DMA block numbers */ | ||
53 | enum { | ||
54 | OMAP_LCD_DMA_B1_TOP, | ||
55 | OMAP_LCD_DMA_B1_BOTTOM, | ||
56 | OMAP_LCD_DMA_B2_TOP, | ||
57 | OMAP_LCD_DMA_B2_BOTTOM | ||
58 | }; | ||
59 | |||
60 | /* LCD DMA functions */ | ||
61 | extern int omap_request_lcd_dma(void (*callback)(u16 status, void *data), | ||
62 | void *data); | ||
63 | extern void omap_free_lcd_dma(void); | ||
64 | extern void omap_setup_lcd_dma(void); | ||
65 | extern void omap_enable_lcd_dma(void); | ||
66 | extern void omap_stop_lcd_dma(void); | ||
67 | extern void omap_set_lcd_dma_ext_controller(int external); | ||
68 | extern void omap_set_lcd_dma_single_transfer(int single); | ||
69 | extern void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres, | ||
70 | int data_type); | ||
71 | extern void omap_set_lcd_dma_b1_rotation(int rotate); | ||
72 | extern void omap_set_lcd_dma_b1_vxres(unsigned long vxres); | ||
73 | extern void omap_set_lcd_dma_b1_mirror(int mirror); | ||
74 | extern void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale); | ||
75 | |||
76 | extern int omap_lcd_dma_running(void); | ||
77 | |||
78 | #endif /* __MACH_OMAP1_LCD_DMA_H__ */ | ||
diff --git a/arch/arm/mach-omap1/include/mach/lcdc.h b/arch/arm/mach-omap1/include/mach/lcdc.h new file mode 100644 index 000000000000..89bd703adaf6 --- /dev/null +++ b/arch/arm/mach-omap1/include/mach/lcdc.h | |||
@@ -0,0 +1,57 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-omap1/include/mach/lcdc.h | ||
3 | * | ||
4 | * Extracted from drivers/video/omap/lcdc.c | ||
5 | * Copyright (C) 2004 Nokia Corporation | ||
6 | * Author: Imre Deak <imre.deak@nokia.com> | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify it | ||
9 | * under the terms of the GNU General Public License as published by the | ||
10 | * Free Software Foundation; either version 2 of the License, or (at your | ||
11 | * option) any later version. | ||
12 | * | ||
13 | * This program is distributed in the hope that it will be useful, but | ||
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of | ||
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | ||
16 | * General Public License for more details. | ||
17 | * | ||
18 | * You should have received a copy of the GNU General Public License along | ||
19 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
20 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | ||
21 | */ | ||
22 | #ifndef __MACH_LCDC_H__ | ||
23 | #define __MACH_LCDC_H__ | ||
24 | |||
25 | #define OMAP_LCDC_BASE 0xfffec000 | ||
26 | #define OMAP_LCDC_SIZE 256 | ||
27 | #define OMAP_LCDC_IRQ INT_LCD_CTRL | ||
28 | |||
29 | #define OMAP_LCDC_CONTROL (OMAP_LCDC_BASE + 0x00) | ||
30 | #define OMAP_LCDC_TIMING0 (OMAP_LCDC_BASE + 0x04) | ||
31 | #define OMAP_LCDC_TIMING1 (OMAP_LCDC_BASE + 0x08) | ||
32 | #define OMAP_LCDC_TIMING2 (OMAP_LCDC_BASE + 0x0c) | ||
33 | #define OMAP_LCDC_STATUS (OMAP_LCDC_BASE + 0x10) | ||
34 | #define OMAP_LCDC_SUBPANEL (OMAP_LCDC_BASE + 0x14) | ||
35 | #define OMAP_LCDC_LINE_INT (OMAP_LCDC_BASE + 0x18) | ||
36 | #define OMAP_LCDC_DISPLAY_STATUS (OMAP_LCDC_BASE + 0x1c) | ||
37 | |||
38 | #define OMAP_LCDC_STAT_DONE (1 << 0) | ||
39 | #define OMAP_LCDC_STAT_VSYNC (1 << 1) | ||
40 | #define OMAP_LCDC_STAT_SYNC_LOST (1 << 2) | ||
41 | #define OMAP_LCDC_STAT_ABC (1 << 3) | ||
42 | #define OMAP_LCDC_STAT_LINE_INT (1 << 4) | ||
43 | #define OMAP_LCDC_STAT_FUF (1 << 5) | ||
44 | #define OMAP_LCDC_STAT_LOADED_PALETTE (1 << 6) | ||
45 | |||
46 | #define OMAP_LCDC_CTRL_LCD_EN (1 << 0) | ||
47 | #define OMAP_LCDC_CTRL_LCD_TFT (1 << 7) | ||
48 | #define OMAP_LCDC_CTRL_LINE_IRQ_CLR_SEL (1 << 10) | ||
49 | |||
50 | #define OMAP_LCDC_IRQ_VSYNC (1 << 2) | ||
51 | #define OMAP_LCDC_IRQ_DONE (1 << 3) | ||
52 | #define OMAP_LCDC_IRQ_LOADED_PALETTE (1 << 4) | ||
53 | #define OMAP_LCDC_IRQ_LINE_NIRQ (1 << 5) | ||
54 | #define OMAP_LCDC_IRQ_LINE (1 << 6) | ||
55 | #define OMAP_LCDC_IRQ_MASK (((1 << 5) - 1) << 2) | ||
56 | |||
57 | #endif /* __MACH_LCDC_H__ */ | ||
diff --git a/arch/arm/mach-omap1/io.c b/arch/arm/mach-omap1/io.c index 2a6d68aa3489..d9b8d82530ae 100644 --- a/arch/arm/mach-omap1/io.c +++ b/arch/arm/mach-omap1/io.c | |||
@@ -18,7 +18,8 @@ | |||
18 | #include <plat/mux.h> | 18 | #include <plat/mux.h> |
19 | #include <plat/tc.h> | 19 | #include <plat/tc.h> |
20 | 20 | ||
21 | extern int omap1_clk_init(void); | 21 | #include "clock.h" |
22 | |||
22 | extern void omap_check_revision(void); | 23 | extern void omap_check_revision(void); |
23 | extern void omap_sram_init(void); | 24 | extern void omap_sram_init(void); |
24 | extern void omapfb_reserve_sdram(void); | 25 | extern void omapfb_reserve_sdram(void); |
diff --git a/arch/arm/mach-omap1/lcd_dma.c b/arch/arm/mach-omap1/lcd_dma.c new file mode 100644 index 000000000000..3be11af687bb --- /dev/null +++ b/arch/arm/mach-omap1/lcd_dma.c | |||
@@ -0,0 +1,448 @@ | |||
1 | /* | ||
2 | * linux/arch/arm/mach-omap1/lcd_dma.c | ||
3 | * | ||
4 | * Extracted from arch/arm/plat-omap/dma.c | ||
5 | * Copyright (C) 2003 - 2008 Nokia Corporation | ||
6 | * Author: Juha Yrjölä <juha.yrjola@nokia.com> | ||
7 | * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com> | ||
8 | * Graphics DMA and LCD DMA graphics tranformations | ||
9 | * by Imre Deak <imre.deak@nokia.com> | ||
10 | * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc. | ||
11 | * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com> | ||
12 | * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc. | ||
13 | * | ||
14 | * Copyright (C) 2009 Texas Instruments | ||
15 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> | ||
16 | * | ||
17 | * Support functions for the OMAP internal DMA channels. | ||
18 | * | ||
19 | * This program is free software; you can redistribute it and/or modify | ||
20 | * it under the terms of the GNU General Public License version 2 as | ||
21 | * published by the Free Software Foundation. | ||
22 | * | ||
23 | */ | ||
24 | |||
25 | #include <linux/module.h> | ||
26 | #include <linux/spinlock.h> | ||
27 | #include <linux/interrupt.h> | ||
28 | #include <linux/io.h> | ||
29 | |||
30 | #include <mach/hardware.h> | ||
31 | #include <mach/lcdc.h> | ||
32 | #include <plat/dma.h> | ||
33 | |||
34 | int omap_lcd_dma_running(void) | ||
35 | { | ||
36 | /* | ||
37 | * On OMAP1510, internal LCD controller will start the transfer | ||
38 | * when it gets enabled, so assume DMA running if LCD enabled. | ||
39 | */ | ||
40 | if (cpu_is_omap1510()) | ||
41 | if (omap_readw(OMAP_LCDC_CONTROL) & OMAP_LCDC_CTRL_LCD_EN) | ||
42 | return 1; | ||
43 | |||
44 | /* Check if LCD DMA is running */ | ||
45 | if (cpu_is_omap16xx()) | ||
46 | if (omap_readw(OMAP1610_DMA_LCD_CCR) & OMAP_DMA_CCR_EN) | ||
47 | return 1; | ||
48 | |||
49 | return 0; | ||
50 | } | ||
51 | |||
52 | static struct lcd_dma_info { | ||
53 | spinlock_t lock; | ||
54 | int reserved; | ||
55 | void (*callback)(u16 status, void *data); | ||
56 | void *cb_data; | ||
57 | |||
58 | int active; | ||
59 | unsigned long addr, size; | ||
60 | int rotate, data_type, xres, yres; | ||
61 | int vxres; | ||
62 | int mirror; | ||
63 | int xscale, yscale; | ||
64 | int ext_ctrl; | ||
65 | int src_port; | ||
66 | int single_transfer; | ||
67 | } lcd_dma; | ||
68 | |||
69 | void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres, | ||
70 | int data_type) | ||
71 | { | ||
72 | lcd_dma.addr = addr; | ||
73 | lcd_dma.data_type = data_type; | ||
74 | lcd_dma.xres = fb_xres; | ||
75 | lcd_dma.yres = fb_yres; | ||
76 | } | ||
77 | EXPORT_SYMBOL(omap_set_lcd_dma_b1); | ||
78 | |||
79 | void omap_set_lcd_dma_src_port(int port) | ||
80 | { | ||
81 | lcd_dma.src_port = port; | ||
82 | } | ||
83 | |||
84 | void omap_set_lcd_dma_ext_controller(int external) | ||
85 | { | ||
86 | lcd_dma.ext_ctrl = external; | ||
87 | } | ||
88 | EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller); | ||
89 | |||
90 | void omap_set_lcd_dma_single_transfer(int single) | ||
91 | { | ||
92 | lcd_dma.single_transfer = single; | ||
93 | } | ||
94 | EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer); | ||
95 | |||
96 | void omap_set_lcd_dma_b1_rotation(int rotate) | ||
97 | { | ||
98 | if (cpu_is_omap1510()) { | ||
99 | printk(KERN_ERR "DMA rotation is not supported in 1510 mode\n"); | ||
100 | BUG(); | ||
101 | return; | ||
102 | } | ||
103 | lcd_dma.rotate = rotate; | ||
104 | } | ||
105 | EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation); | ||
106 | |||
107 | void omap_set_lcd_dma_b1_mirror(int mirror) | ||
108 | { | ||
109 | if (cpu_is_omap1510()) { | ||
110 | printk(KERN_ERR "DMA mirror is not supported in 1510 mode\n"); | ||
111 | BUG(); | ||
112 | } | ||
113 | lcd_dma.mirror = mirror; | ||
114 | } | ||
115 | EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror); | ||
116 | |||
117 | void omap_set_lcd_dma_b1_vxres(unsigned long vxres) | ||
118 | { | ||
119 | if (cpu_is_omap1510()) { | ||
120 | printk(KERN_ERR "DMA virtual resulotion is not supported " | ||
121 | "in 1510 mode\n"); | ||
122 | BUG(); | ||
123 | } | ||
124 | lcd_dma.vxres = vxres; | ||
125 | } | ||
126 | EXPORT_SYMBOL(omap_set_lcd_dma_b1_vxres); | ||
127 | |||
128 | void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale) | ||
129 | { | ||
130 | if (cpu_is_omap1510()) { | ||
131 | printk(KERN_ERR "DMA scale is not supported in 1510 mode\n"); | ||
132 | BUG(); | ||
133 | } | ||
134 | lcd_dma.xscale = xscale; | ||
135 | lcd_dma.yscale = yscale; | ||
136 | } | ||
137 | EXPORT_SYMBOL(omap_set_lcd_dma_b1_scale); | ||
138 | |||
139 | static void set_b1_regs(void) | ||
140 | { | ||
141 | unsigned long top, bottom; | ||
142 | int es; | ||
143 | u16 w; | ||
144 | unsigned long en, fn; | ||
145 | long ei, fi; | ||
146 | unsigned long vxres; | ||
147 | unsigned int xscale, yscale; | ||
148 | |||
149 | switch (lcd_dma.data_type) { | ||
150 | case OMAP_DMA_DATA_TYPE_S8: | ||
151 | es = 1; | ||
152 | break; | ||
153 | case OMAP_DMA_DATA_TYPE_S16: | ||
154 | es = 2; | ||
155 | break; | ||
156 | case OMAP_DMA_DATA_TYPE_S32: | ||
157 | es = 4; | ||
158 | break; | ||
159 | default: | ||
160 | BUG(); | ||
161 | return; | ||
162 | } | ||
163 | |||
164 | vxres = lcd_dma.vxres ? lcd_dma.vxres : lcd_dma.xres; | ||
165 | xscale = lcd_dma.xscale ? lcd_dma.xscale : 1; | ||
166 | yscale = lcd_dma.yscale ? lcd_dma.yscale : 1; | ||
167 | BUG_ON(vxres < lcd_dma.xres); | ||
168 | |||
169 | #define PIXADDR(x, y) (lcd_dma.addr + \ | ||
170 | ((y) * vxres * yscale + (x) * xscale) * es) | ||
171 | #define PIXSTEP(sx, sy, dx, dy) (PIXADDR(dx, dy) - PIXADDR(sx, sy) - es + 1) | ||
172 | |||
173 | switch (lcd_dma.rotate) { | ||
174 | case 0: | ||
175 | if (!lcd_dma.mirror) { | ||
176 | top = PIXADDR(0, 0); | ||
177 | bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1); | ||
178 | /* 1510 DMA requires the bottom address to be 2 more | ||
179 | * than the actual last memory access location. */ | ||
180 | if (cpu_is_omap1510() && | ||
181 | lcd_dma.data_type == OMAP_DMA_DATA_TYPE_S32) | ||
182 | bottom += 2; | ||
183 | ei = PIXSTEP(0, 0, 1, 0); | ||
184 | fi = PIXSTEP(lcd_dma.xres - 1, 0, 0, 1); | ||
185 | } else { | ||
186 | top = PIXADDR(lcd_dma.xres - 1, 0); | ||
187 | bottom = PIXADDR(0, lcd_dma.yres - 1); | ||
188 | ei = PIXSTEP(1, 0, 0, 0); | ||
189 | fi = PIXSTEP(0, 0, lcd_dma.xres - 1, 1); | ||
190 | } | ||
191 | en = lcd_dma.xres; | ||
192 | fn = lcd_dma.yres; | ||
193 | break; | ||
194 | case 90: | ||
195 | if (!lcd_dma.mirror) { | ||
196 | top = PIXADDR(0, lcd_dma.yres - 1); | ||
197 | bottom = PIXADDR(lcd_dma.xres - 1, 0); | ||
198 | ei = PIXSTEP(0, 1, 0, 0); | ||
199 | fi = PIXSTEP(0, 0, 1, lcd_dma.yres - 1); | ||
200 | } else { | ||
201 | top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1); | ||
202 | bottom = PIXADDR(0, 0); | ||
203 | ei = PIXSTEP(0, 1, 0, 0); | ||
204 | fi = PIXSTEP(1, 0, 0, lcd_dma.yres - 1); | ||
205 | } | ||
206 | en = lcd_dma.yres; | ||
207 | fn = lcd_dma.xres; | ||
208 | break; | ||
209 | case 180: | ||
210 | if (!lcd_dma.mirror) { | ||
211 | top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1); | ||
212 | bottom = PIXADDR(0, 0); | ||
213 | ei = PIXSTEP(1, 0, 0, 0); | ||
214 | fi = PIXSTEP(0, 1, lcd_dma.xres - 1, 0); | ||
215 | } else { | ||
216 | top = PIXADDR(0, lcd_dma.yres - 1); | ||
217 | bottom = PIXADDR(lcd_dma.xres - 1, 0); | ||
218 | ei = PIXSTEP(0, 0, 1, 0); | ||
219 | fi = PIXSTEP(lcd_dma.xres - 1, 1, 0, 0); | ||
220 | } | ||
221 | en = lcd_dma.xres; | ||
222 | fn = lcd_dma.yres; | ||
223 | break; | ||
224 | case 270: | ||
225 | if (!lcd_dma.mirror) { | ||
226 | top = PIXADDR(lcd_dma.xres - 1, 0); | ||
227 | bottom = PIXADDR(0, lcd_dma.yres - 1); | ||
228 | ei = PIXSTEP(0, 0, 0, 1); | ||
229 | fi = PIXSTEP(1, lcd_dma.yres - 1, 0, 0); | ||
230 | } else { | ||
231 | top = PIXADDR(0, 0); | ||
232 | bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1); | ||
233 | ei = PIXSTEP(0, 0, 0, 1); | ||
234 | fi = PIXSTEP(0, lcd_dma.yres - 1, 1, 0); | ||
235 | } | ||
236 | en = lcd_dma.yres; | ||
237 | fn = lcd_dma.xres; | ||
238 | break; | ||
239 | default: | ||
240 | BUG(); | ||
241 | return; /* Suppress warning about uninitialized vars */ | ||
242 | } | ||
243 | |||
244 | if (cpu_is_omap1510()) { | ||
245 | omap_writew(top >> 16, OMAP1510_DMA_LCD_TOP_F1_U); | ||
246 | omap_writew(top, OMAP1510_DMA_LCD_TOP_F1_L); | ||
247 | omap_writew(bottom >> 16, OMAP1510_DMA_LCD_BOT_F1_U); | ||
248 | omap_writew(bottom, OMAP1510_DMA_LCD_BOT_F1_L); | ||
249 | |||
250 | return; | ||
251 | } | ||
252 | |||
253 | /* 1610 regs */ | ||
254 | omap_writew(top >> 16, OMAP1610_DMA_LCD_TOP_B1_U); | ||
255 | omap_writew(top, OMAP1610_DMA_LCD_TOP_B1_L); | ||
256 | omap_writew(bottom >> 16, OMAP1610_DMA_LCD_BOT_B1_U); | ||
257 | omap_writew(bottom, OMAP1610_DMA_LCD_BOT_B1_L); | ||
258 | |||
259 | omap_writew(en, OMAP1610_DMA_LCD_SRC_EN_B1); | ||
260 | omap_writew(fn, OMAP1610_DMA_LCD_SRC_FN_B1); | ||
261 | |||
262 | w = omap_readw(OMAP1610_DMA_LCD_CSDP); | ||
263 | w &= ~0x03; | ||
264 | w |= lcd_dma.data_type; | ||
265 | omap_writew(w, OMAP1610_DMA_LCD_CSDP); | ||
266 | |||
267 | w = omap_readw(OMAP1610_DMA_LCD_CTRL); | ||
268 | /* Always set the source port as SDRAM for now*/ | ||
269 | w &= ~(0x03 << 6); | ||
270 | if (lcd_dma.callback != NULL) | ||
271 | w |= 1 << 1; /* Block interrupt enable */ | ||
272 | else | ||
273 | w &= ~(1 << 1); | ||
274 | omap_writew(w, OMAP1610_DMA_LCD_CTRL); | ||
275 | |||
276 | if (!(lcd_dma.rotate || lcd_dma.mirror || | ||
277 | lcd_dma.vxres || lcd_dma.xscale || lcd_dma.yscale)) | ||
278 | return; | ||
279 | |||
280 | w = omap_readw(OMAP1610_DMA_LCD_CCR); | ||
281 | /* Set the double-indexed addressing mode */ | ||
282 | w |= (0x03 << 12); | ||
283 | omap_writew(w, OMAP1610_DMA_LCD_CCR); | ||
284 | |||
285 | omap_writew(ei, OMAP1610_DMA_LCD_SRC_EI_B1); | ||
286 | omap_writew(fi >> 16, OMAP1610_DMA_LCD_SRC_FI_B1_U); | ||
287 | omap_writew(fi, OMAP1610_DMA_LCD_SRC_FI_B1_L); | ||
288 | } | ||
289 | |||
290 | static irqreturn_t lcd_dma_irq_handler(int irq, void *dev_id) | ||
291 | { | ||
292 | u16 w; | ||
293 | |||
294 | w = omap_readw(OMAP1610_DMA_LCD_CTRL); | ||
295 | if (unlikely(!(w & (1 << 3)))) { | ||
296 | printk(KERN_WARNING "Spurious LCD DMA IRQ\n"); | ||
297 | return IRQ_NONE; | ||
298 | } | ||
299 | /* Ack the IRQ */ | ||
300 | w |= (1 << 3); | ||
301 | omap_writew(w, OMAP1610_DMA_LCD_CTRL); | ||
302 | lcd_dma.active = 0; | ||
303 | if (lcd_dma.callback != NULL) | ||
304 | lcd_dma.callback(w, lcd_dma.cb_data); | ||
305 | |||
306 | return IRQ_HANDLED; | ||
307 | } | ||
308 | |||
309 | int omap_request_lcd_dma(void (*callback)(u16 status, void *data), | ||
310 | void *data) | ||
311 | { | ||
312 | spin_lock_irq(&lcd_dma.lock); | ||
313 | if (lcd_dma.reserved) { | ||
314 | spin_unlock_irq(&lcd_dma.lock); | ||
315 | printk(KERN_ERR "LCD DMA channel already reserved\n"); | ||
316 | BUG(); | ||
317 | return -EBUSY; | ||
318 | } | ||
319 | lcd_dma.reserved = 1; | ||
320 | spin_unlock_irq(&lcd_dma.lock); | ||
321 | lcd_dma.callback = callback; | ||
322 | lcd_dma.cb_data = data; | ||
323 | lcd_dma.active = 0; | ||
324 | lcd_dma.single_transfer = 0; | ||
325 | lcd_dma.rotate = 0; | ||
326 | lcd_dma.vxres = 0; | ||
327 | lcd_dma.mirror = 0; | ||
328 | lcd_dma.xscale = 0; | ||
329 | lcd_dma.yscale = 0; | ||
330 | lcd_dma.ext_ctrl = 0; | ||
331 | lcd_dma.src_port = 0; | ||
332 | |||
333 | return 0; | ||
334 | } | ||
335 | EXPORT_SYMBOL(omap_request_lcd_dma); | ||
336 | |||
337 | void omap_free_lcd_dma(void) | ||
338 | { | ||
339 | spin_lock(&lcd_dma.lock); | ||
340 | if (!lcd_dma.reserved) { | ||
341 | spin_unlock(&lcd_dma.lock); | ||
342 | printk(KERN_ERR "LCD DMA is not reserved\n"); | ||
343 | BUG(); | ||
344 | return; | ||
345 | } | ||
346 | if (!cpu_is_omap1510()) | ||
347 | omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR) & ~1, | ||
348 | OMAP1610_DMA_LCD_CCR); | ||
349 | lcd_dma.reserved = 0; | ||
350 | spin_unlock(&lcd_dma.lock); | ||
351 | } | ||
352 | EXPORT_SYMBOL(omap_free_lcd_dma); | ||
353 | |||
354 | void omap_enable_lcd_dma(void) | ||
355 | { | ||
356 | u16 w; | ||
357 | |||
358 | /* | ||
359 | * Set the Enable bit only if an external controller is | ||
360 | * connected. Otherwise the OMAP internal controller will | ||
361 | * start the transfer when it gets enabled. | ||
362 | */ | ||
363 | if (cpu_is_omap1510() || !lcd_dma.ext_ctrl) | ||
364 | return; | ||
365 | |||
366 | w = omap_readw(OMAP1610_DMA_LCD_CTRL); | ||
367 | w |= 1 << 8; | ||
368 | omap_writew(w, OMAP1610_DMA_LCD_CTRL); | ||
369 | |||
370 | lcd_dma.active = 1; | ||
371 | |||
372 | w = omap_readw(OMAP1610_DMA_LCD_CCR); | ||
373 | w |= 1 << 7; | ||
374 | omap_writew(w, OMAP1610_DMA_LCD_CCR); | ||
375 | } | ||
376 | EXPORT_SYMBOL(omap_enable_lcd_dma); | ||
377 | |||
378 | void omap_setup_lcd_dma(void) | ||
379 | { | ||
380 | BUG_ON(lcd_dma.active); | ||
381 | if (!cpu_is_omap1510()) { | ||
382 | /* Set some reasonable defaults */ | ||
383 | omap_writew(0x5440, OMAP1610_DMA_LCD_CCR); | ||
384 | omap_writew(0x9102, OMAP1610_DMA_LCD_CSDP); | ||
385 | omap_writew(0x0004, OMAP1610_DMA_LCD_LCH_CTRL); | ||
386 | } | ||
387 | set_b1_regs(); | ||
388 | if (!cpu_is_omap1510()) { | ||
389 | u16 w; | ||
390 | |||
391 | w = omap_readw(OMAP1610_DMA_LCD_CCR); | ||
392 | /* | ||
393 | * If DMA was already active set the end_prog bit to have | ||
394 | * the programmed register set loaded into the active | ||
395 | * register set. | ||
396 | */ | ||
397 | w |= 1 << 11; /* End_prog */ | ||
398 | if (!lcd_dma.single_transfer) | ||
399 | w |= (3 << 8); /* Auto_init, repeat */ | ||
400 | omap_writew(w, OMAP1610_DMA_LCD_CCR); | ||
401 | } | ||
402 | } | ||
403 | EXPORT_SYMBOL(omap_setup_lcd_dma); | ||
404 | |||
405 | void omap_stop_lcd_dma(void) | ||
406 | { | ||
407 | u16 w; | ||
408 | |||
409 | lcd_dma.active = 0; | ||
410 | if (cpu_is_omap1510() || !lcd_dma.ext_ctrl) | ||
411 | return; | ||
412 | |||
413 | w = omap_readw(OMAP1610_DMA_LCD_CCR); | ||
414 | w &= ~(1 << 7); | ||
415 | omap_writew(w, OMAP1610_DMA_LCD_CCR); | ||
416 | |||
417 | w = omap_readw(OMAP1610_DMA_LCD_CTRL); | ||
418 | w &= ~(1 << 8); | ||
419 | omap_writew(w, OMAP1610_DMA_LCD_CTRL); | ||
420 | } | ||
421 | EXPORT_SYMBOL(omap_stop_lcd_dma); | ||
422 | |||
423 | static int __init omap_init_lcd_dma(void) | ||
424 | { | ||
425 | int r; | ||
426 | |||
427 | if (cpu_is_omap16xx()) { | ||
428 | u16 w; | ||
429 | |||
430 | /* this would prevent OMAP sleep */ | ||
431 | w = omap_readw(OMAP1610_DMA_LCD_CTRL); | ||
432 | w &= ~(1 << 8); | ||
433 | omap_writew(w, OMAP1610_DMA_LCD_CTRL); | ||
434 | } | ||
435 | |||
436 | spin_lock_init(&lcd_dma.lock); | ||
437 | |||
438 | r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0, | ||
439 | "LCD DMA", NULL); | ||
440 | if (r != 0) | ||
441 | printk(KERN_ERR "unable to request IRQ for LCD DMA " | ||
442 | "(error %d)\n", r); | ||
443 | |||
444 | return r; | ||
445 | } | ||
446 | |||
447 | arch_initcall(omap_init_lcd_dma); | ||
448 | |||
diff --git a/arch/arm/mach-omap1/mux.c b/arch/arm/mach-omap1/mux.c index 785371e982fc..07212cc621ae 100644 --- a/arch/arm/mach-omap1/mux.c +++ b/arch/arm/mach-omap1/mux.c | |||
@@ -50,12 +50,18 @@ MUX_CFG_7XX("E3_7XX_KBC4", 13, 25, 0, 24, 1, 0) | |||
50 | 50 | ||
51 | MUX_CFG_7XX("AA17_7XX_USB_DM", 2, 21, 0, 20, 0, 0) | 51 | MUX_CFG_7XX("AA17_7XX_USB_DM", 2, 21, 0, 20, 0, 0) |
52 | MUX_CFG_7XX("W16_7XX_USB_PU_EN", 2, 25, 0, 24, 0, 0) | 52 | MUX_CFG_7XX("W16_7XX_USB_PU_EN", 2, 25, 0, 24, 0, 0) |
53 | MUX_CFG_7XX("W17_7XX_USB_VBUSI", 2, 29, 0, 28, 0, 0) | 53 | MUX_CFG_7XX("W17_7XX_USB_VBUSI", 2, 29, 6, 28, 1, 0) |
54 | MUX_CFG_7XX("W18_7XX_USB_DMCK_OUT",3, 3, 1, 2, 0, 0) | ||
55 | MUX_CFG_7XX("W19_7XX_USB_DCRST", 3, 7, 1, 6, 0, 0) | ||
54 | 56 | ||
55 | /* MMC Pins */ | 57 | /* MMC Pins */ |
56 | MUX_CFG_7XX("MMC_7XX_CMD", 2, 9, 0, 8, 1, 0) | 58 | MUX_CFG_7XX("MMC_7XX_CMD", 2, 9, 0, 8, 1, 0) |
57 | MUX_CFG_7XX("MMC_7XX_CLK", 2, 13, 0, 12, 1, 0) | 59 | MUX_CFG_7XX("MMC_7XX_CLK", 2, 13, 0, 12, 1, 0) |
58 | MUX_CFG_7XX("MMC_7XX_DAT0", 2, 17, 0, 16, 1, 0) | 60 | MUX_CFG_7XX("MMC_7XX_DAT0", 2, 17, 0, 16, 1, 0) |
61 | |||
62 | /* I2C interface */ | ||
63 | MUX_CFG_7XX("I2C_7XX_SCL", 5, 1, 0, 0, 1, 0) | ||
64 | MUX_CFG_7XX("I2C_7XX_SDA", 5, 5, 0, 0, 1, 0) | ||
59 | }; | 65 | }; |
60 | #define OMAP7XX_PINS_SZ ARRAY_SIZE(omap7xx_pins) | 66 | #define OMAP7XX_PINS_SZ ARRAY_SIZE(omap7xx_pins) |
61 | #else | 67 | #else |
diff --git a/arch/arm/mach-omap1/opp.h b/arch/arm/mach-omap1/opp.h new file mode 100644 index 000000000000..07074d79adce --- /dev/null +++ b/arch/arm/mach-omap1/opp.h | |||
@@ -0,0 +1,28 @@ | |||
1 | /* | ||
2 | * linux/arch/arm/mach-omap1/opp.h | ||
3 | * | ||
4 | * Copyright (C) 2004 - 2005 Nokia corporation | ||
5 | * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> | ||
6 | * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #ifndef __ARCH_ARM_MACH_OMAP1_OPP_H | ||
14 | #define __ARCH_ARM_MACH_OMAP1_OPP_H | ||
15 | |||
16 | #include <linux/types.h> | ||
17 | |||
18 | struct mpu_rate { | ||
19 | unsigned long rate; | ||
20 | unsigned long xtal; | ||
21 | unsigned long pll_rate; | ||
22 | __u16 ckctl_val; | ||
23 | __u16 dpllctl_val; | ||
24 | }; | ||
25 | |||
26 | extern struct mpu_rate omap1_rate_table[]; | ||
27 | |||
28 | #endif | ||
diff --git a/arch/arm/mach-omap1/opp_data.c b/arch/arm/mach-omap1/opp_data.c new file mode 100644 index 000000000000..75a546514994 --- /dev/null +++ b/arch/arm/mach-omap1/opp_data.c | |||
@@ -0,0 +1,59 @@ | |||
1 | /* | ||
2 | * linux/arch/arm/mach-omap1/opp_data.c | ||
3 | * | ||
4 | * Copyright (C) 2004 - 2005 Nokia corporation | ||
5 | * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> | ||
6 | * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #include "opp.h" | ||
14 | |||
15 | /*------------------------------------------------------------------------- | ||
16 | * Omap1 MPU rate table | ||
17 | *-------------------------------------------------------------------------*/ | ||
18 | struct mpu_rate omap1_rate_table[] = { | ||
19 | /* MPU MHz, xtal MHz, dpll1 MHz, CKCTL, DPLL_CTL | ||
20 | * NOTE: Comment order here is different from bits in CKCTL value: | ||
21 | * armdiv, dspdiv, dspmmu, tcdiv, perdiv, lcddiv | ||
22 | */ | ||
23 | #if defined(CONFIG_OMAP_ARM_216MHZ) | ||
24 | { 216000000, 12000000, 216000000, 0x050d, 0x2910 }, /* 1/1/2/2/2/8 */ | ||
25 | #endif | ||
26 | #if defined(CONFIG_OMAP_ARM_195MHZ) | ||
27 | { 195000000, 13000000, 195000000, 0x050e, 0x2790 }, /* 1/1/2/2/4/8 */ | ||
28 | #endif | ||
29 | #if defined(CONFIG_OMAP_ARM_192MHZ) | ||
30 | { 192000000, 19200000, 192000000, 0x050f, 0x2510 }, /* 1/1/2/2/8/8 */ | ||
31 | { 192000000, 12000000, 192000000, 0x050f, 0x2810 }, /* 1/1/2/2/8/8 */ | ||
32 | { 96000000, 12000000, 192000000, 0x055f, 0x2810 }, /* 2/2/2/2/8/8 */ | ||
33 | { 48000000, 12000000, 192000000, 0x0baf, 0x2810 }, /* 4/4/4/8/8/8 */ | ||
34 | { 24000000, 12000000, 192000000, 0x0fff, 0x2810 }, /* 8/8/8/8/8/8 */ | ||
35 | #endif | ||
36 | #if defined(CONFIG_OMAP_ARM_182MHZ) | ||
37 | { 182000000, 13000000, 182000000, 0x050e, 0x2710 }, /* 1/1/2/2/4/8 */ | ||
38 | #endif | ||
39 | #if defined(CONFIG_OMAP_ARM_168MHZ) | ||
40 | { 168000000, 12000000, 168000000, 0x010f, 0x2710 }, /* 1/1/1/2/8/8 */ | ||
41 | #endif | ||
42 | #if defined(CONFIG_OMAP_ARM_150MHZ) | ||
43 | { 150000000, 12000000, 150000000, 0x010a, 0x2cb0 }, /* 1/1/1/2/4/4 */ | ||
44 | #endif | ||
45 | #if defined(CONFIG_OMAP_ARM_120MHZ) | ||
46 | { 120000000, 12000000, 120000000, 0x010a, 0x2510 }, /* 1/1/1/2/4/4 */ | ||
47 | #endif | ||
48 | #if defined(CONFIG_OMAP_ARM_96MHZ) | ||
49 | { 96000000, 12000000, 96000000, 0x0005, 0x2410 }, /* 1/1/1/1/2/2 */ | ||
50 | #endif | ||
51 | #if defined(CONFIG_OMAP_ARM_60MHZ) | ||
52 | { 60000000, 12000000, 60000000, 0x0005, 0x2290 }, /* 1/1/1/1/2/2 */ | ||
53 | #endif | ||
54 | #if defined(CONFIG_OMAP_ARM_30MHZ) | ||
55 | { 30000000, 12000000, 60000000, 0x0555, 0x2290 }, /* 2/2/2/2/2/2 */ | ||
56 | #endif | ||
57 | { 0, 0, 0, 0, 0 }, | ||
58 | }; | ||
59 | |||
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 7309aab305a9..76c11ee113e9 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig | |||
@@ -24,6 +24,18 @@ config ARCH_OMAP3430 | |||
24 | depends on ARCH_OMAP3 && ARCH_OMAP34XX | 24 | depends on ARCH_OMAP3 && ARCH_OMAP34XX |
25 | select ARCH_OMAP_OTG | 25 | select ARCH_OMAP_OTG |
26 | 26 | ||
27 | config OMAP_PACKAGE_CBC | ||
28 | bool | ||
29 | |||
30 | config OMAP_PACKAGE_CBB | ||
31 | bool | ||
32 | |||
33 | config OMAP_PACKAGE_CUS | ||
34 | bool | ||
35 | |||
36 | config OMAP_PACKAGE_CBP | ||
37 | bool | ||
38 | |||
27 | comment "OMAP Board Type" | 39 | comment "OMAP Board Type" |
28 | depends on ARCH_OMAP2 || ARCH_OMAP3 || ARCH_OMAP4 | 40 | depends on ARCH_OMAP2 || ARCH_OMAP3 || ARCH_OMAP4 |
29 | 41 | ||
@@ -52,14 +64,17 @@ config MACH_OMAP_2430SDP | |||
52 | config MACH_OMAP3_BEAGLE | 64 | config MACH_OMAP3_BEAGLE |
53 | bool "OMAP3 BEAGLE board" | 65 | bool "OMAP3 BEAGLE board" |
54 | depends on ARCH_OMAP3 && ARCH_OMAP34XX | 66 | depends on ARCH_OMAP3 && ARCH_OMAP34XX |
67 | select OMAP_PACKAGE_CBB | ||
55 | 68 | ||
56 | config MACH_OMAP_LDP | 69 | config MACH_OMAP_LDP |
57 | bool "OMAP3 LDP board" | 70 | bool "OMAP3 LDP board" |
58 | depends on ARCH_OMAP3 && ARCH_OMAP34XX | 71 | depends on ARCH_OMAP3 && ARCH_OMAP34XX |
72 | select OMAP_PACKAGE_CBB | ||
59 | 73 | ||
60 | config MACH_OVERO | 74 | config MACH_OVERO |
61 | bool "Gumstix Overo board" | 75 | bool "Gumstix Overo board" |
62 | depends on ARCH_OMAP3 && ARCH_OMAP34XX | 76 | depends on ARCH_OMAP3 && ARCH_OMAP34XX |
77 | select OMAP_PACKAGE_CBB | ||
63 | 78 | ||
64 | config MACH_OMAP3EVM | 79 | config MACH_OMAP3EVM |
65 | bool "OMAP 3530 EVM board" | 80 | bool "OMAP 3530 EVM board" |
@@ -68,14 +83,22 @@ config MACH_OMAP3EVM | |||
68 | config MACH_OMAP3517EVM | 83 | config MACH_OMAP3517EVM |
69 | bool "OMAP3517/ AM3517 EVM board" | 84 | bool "OMAP3517/ AM3517 EVM board" |
70 | depends on ARCH_OMAP3 && ARCH_OMAP34XX | 85 | depends on ARCH_OMAP3 && ARCH_OMAP34XX |
86 | select OMAP_PACKAGE_CBB | ||
71 | 87 | ||
72 | config MACH_OMAP3_PANDORA | 88 | config MACH_OMAP3_PANDORA |
73 | bool "OMAP3 Pandora" | 89 | bool "OMAP3 Pandora" |
74 | depends on ARCH_OMAP3 && ARCH_OMAP34XX | 90 | depends on ARCH_OMAP3 && ARCH_OMAP34XX |
91 | select OMAP_PACKAGE_CBB | ||
92 | |||
93 | config MACH_OMAP3_TOUCHBOOK | ||
94 | bool "OMAP3 Touch Book" | ||
95 | depends on ARCH_OMAP3 && ARCH_OMAP34XX | ||
96 | select BACKLIGHT_CLASS_DEVICE | ||
75 | 97 | ||
76 | config MACH_OMAP_3430SDP | 98 | config MACH_OMAP_3430SDP |
77 | bool "OMAP 3430 SDP board" | 99 | bool "OMAP 3430 SDP board" |
78 | depends on ARCH_OMAP3 && ARCH_OMAP34XX | 100 | depends on ARCH_OMAP3 && ARCH_OMAP34XX |
101 | select OMAP_PACKAGE_CBB | ||
79 | 102 | ||
80 | config MACH_NOKIA_N800 | 103 | config MACH_NOKIA_N800 |
81 | bool | 104 | bool |
@@ -96,26 +119,33 @@ config MACH_NOKIA_N8X0 | |||
96 | config MACH_NOKIA_RX51 | 119 | config MACH_NOKIA_RX51 |
97 | bool "Nokia RX-51 board" | 120 | bool "Nokia RX-51 board" |
98 | depends on ARCH_OMAP3 && ARCH_OMAP34XX | 121 | depends on ARCH_OMAP3 && ARCH_OMAP34XX |
122 | select OMAP_PACKAGE_CBB | ||
99 | 123 | ||
100 | config MACH_OMAP_ZOOM2 | 124 | config MACH_OMAP_ZOOM2 |
101 | bool "OMAP3 Zoom2 board" | 125 | bool "OMAP3 Zoom2 board" |
102 | depends on ARCH_OMAP3 && ARCH_OMAP34XX | 126 | depends on ARCH_OMAP3 && ARCH_OMAP34XX |
127 | select OMAP_PACKAGE_CBB | ||
103 | 128 | ||
104 | config MACH_OMAP_ZOOM3 | 129 | config MACH_OMAP_ZOOM3 |
105 | bool "OMAP3630 Zoom3 board" | 130 | bool "OMAP3630 Zoom3 board" |
106 | depends on ARCH_OMAP3 && ARCH_OMAP34XX | 131 | depends on ARCH_OMAP3 && ARCH_OMAP34XX |
132 | select OMAP_PACKAGE_CBP | ||
107 | 133 | ||
108 | config MACH_CM_T35 | 134 | config MACH_CM_T35 |
109 | bool "CompuLab CM-T35 module" | 135 | bool "CompuLab CM-T35 module" |
110 | depends on ARCH_OMAP3 && ARCH_OMAP34XX | 136 | depends on ARCH_OMAP3 && ARCH_OMAP34XX |
137 | select OMAP_PACKAGE_CUS | ||
138 | select OMAP_MUX | ||
111 | 139 | ||
112 | config MACH_IGEP0020 | 140 | config MACH_IGEP0020 |
113 | bool "IGEP0020" | 141 | bool "IGEP0020" |
114 | depends on ARCH_OMAP3 && ARCH_OMAP34XX | 142 | depends on ARCH_OMAP3 && ARCH_OMAP34XX |
143 | select OMAP_PACKAGE_CBB | ||
115 | 144 | ||
116 | config MACH_OMAP_3630SDP | 145 | config MACH_OMAP_3630SDP |
117 | bool "OMAP3630 SDP board" | 146 | bool "OMAP3630 SDP board" |
118 | depends on ARCH_OMAP3 && ARCH_OMAP34XX | 147 | depends on ARCH_OMAP3 && ARCH_OMAP34XX |
148 | select OMAP_PACKAGE_CBP | ||
119 | 149 | ||
120 | config MACH_OMAP_4430SDP | 150 | config MACH_OMAP_4430SDP |
121 | bool "OMAP 4430 SDP board" | 151 | bool "OMAP 4430 SDP board" |
@@ -128,3 +158,15 @@ config OMAP3_EMU | |||
128 | help | 158 | help |
129 | Say Y here to enable debugging hardware of omap3 | 159 | Say Y here to enable debugging hardware of omap3 |
130 | 160 | ||
161 | config OMAP3_SDRC_AC_TIMING | ||
162 | bool "Enable SDRC AC timing register changes" | ||
163 | depends on ARCH_OMAP3 && ARCH_OMAP34XX | ||
164 | default n | ||
165 | help | ||
166 | If you know that none of your system initiators will attempt to | ||
167 | access SDRAM during CORE DVFS, select Y here. This should boost | ||
168 | SDRAM performance at lower CORE OPPs. There are relatively few | ||
169 | users who will wish to say yes at this point - almost everyone will | ||
170 | wish to say no. Selecting yes without understanding what is | ||
171 | going on could result in system crashes; | ||
172 | |||
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 32548a4510c5..b32678b848bc 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile | |||
@@ -6,11 +6,14 @@ | |||
6 | obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o | 6 | obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o |
7 | 7 | ||
8 | omap-2-3-common = irq.o sdrc.o omap_hwmod.o | 8 | omap-2-3-common = irq.o sdrc.o omap_hwmod.o |
9 | omap-3-4-common = dpll.o | ||
9 | prcm-common = prcm.o powerdomain.o | 10 | prcm-common = prcm.o powerdomain.o |
10 | clock-common = clock.o clockdomain.o | 11 | clock-common = clock.o clock_common_data.o clockdomain.o |
11 | 12 | ||
12 | obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(prcm-common) $(clock-common) | 13 | obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(prcm-common) $(clock-common) |
13 | obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(prcm-common) $(clock-common) | 14 | obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(prcm-common) $(clock-common) \ |
15 | $(omap-3-4-common) | ||
16 | obj-$(CONFIG_ARCH_OMAP4) += $(omap-3-4-common) prcm.o clock.o | ||
14 | 17 | ||
15 | obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o | 18 | obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o |
16 | 19 | ||
@@ -23,6 +26,9 @@ obj-$(CONFIG_ARCH_OMAP2420) += sram242x.o | |||
23 | obj-$(CONFIG_ARCH_OMAP2430) += sram243x.o | 26 | obj-$(CONFIG_ARCH_OMAP2430) += sram243x.o |
24 | obj-$(CONFIG_ARCH_OMAP3) += sram34xx.o | 27 | obj-$(CONFIG_ARCH_OMAP3) += sram34xx.o |
25 | 28 | ||
29 | # Pin multiplexing | ||
30 | obj-$(CONFIG_ARCH_OMAP3) += mux34xx.o | ||
31 | |||
26 | # SMS/SDRC | 32 | # SMS/SDRC |
27 | obj-$(CONFIG_ARCH_OMAP2) += sdrc2xxx.o | 33 | obj-$(CONFIG_ARCH_OMAP2) += sdrc2xxx.o |
28 | # obj-$(CONFIG_ARCH_OMAP3) += sdrc3xxx.o | 34 | # obj-$(CONFIG_ARCH_OMAP3) += sdrc3xxx.o |
@@ -41,8 +47,11 @@ obj-$(CONFIG_ARCH_OMAP3) += cm.o | |||
41 | obj-$(CONFIG_ARCH_OMAP4) += cm4xxx.o | 47 | obj-$(CONFIG_ARCH_OMAP4) += cm4xxx.o |
42 | 48 | ||
43 | # Clock framework | 49 | # Clock framework |
44 | obj-$(CONFIG_ARCH_OMAP2) += clock24xx.o | 50 | obj-$(CONFIG_ARCH_OMAP2) += clock2xxx.o clock2xxx_data.o |
45 | obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o | 51 | obj-$(CONFIG_ARCH_OMAP2420) += opp2420_data.o |
52 | obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o clock34xx_data.o | ||
53 | obj-$(CONFIG_ARCH_OMAP2430) += opp2430_data.o | ||
54 | obj-$(CONFIG_ARCH_OMAP4) += clock44xx.o clock44xx_data.o | ||
46 | 55 | ||
47 | # EMU peripherals | 56 | # EMU peripherals |
48 | obj-$(CONFIG_OMAP3_EMU) += emu.o | 57 | obj-$(CONFIG_OMAP3_EMU) += emu.o |
@@ -55,6 +64,9 @@ iommu-$(CONFIG_ARCH_OMAP3) += omap3-iommu.o | |||
55 | 64 | ||
56 | obj-$(CONFIG_OMAP_IOMMU) += $(iommu-y) | 65 | obj-$(CONFIG_OMAP_IOMMU) += $(iommu-y) |
57 | 66 | ||
67 | i2c-omap-$(CONFIG_I2C_OMAP) := i2c.o | ||
68 | obj-y += $(i2c-omap-m) $(i2c-omap-y) | ||
69 | |||
58 | # Specific board support | 70 | # Specific board support |
59 | obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o | 71 | obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o |
60 | obj-$(CONFIG_MACH_OMAP_H4) += board-h4.o | 72 | obj-$(CONFIG_MACH_OMAP_H4) += board-h4.o |
@@ -93,7 +105,8 @@ obj-$(CONFIG_MACH_CM_T35) += board-cm-t35.o \ | |||
93 | mmc-twl4030.o | 105 | mmc-twl4030.o |
94 | obj-$(CONFIG_MACH_IGEP0020) += board-igep0020.o \ | 106 | obj-$(CONFIG_MACH_IGEP0020) += board-igep0020.o \ |
95 | mmc-twl4030.o | 107 | mmc-twl4030.o |
96 | 108 | obj-$(CONFIG_MACH_OMAP3_TOUCHBOOK) += board-omap3touchbook.o \ | |
109 | mmc-twl4030.o | ||
97 | obj-$(CONFIG_MACH_OMAP_4430SDP) += board-4430sdp.o | 110 | obj-$(CONFIG_MACH_OMAP_4430SDP) += board-4430sdp.o |
98 | 111 | ||
99 | obj-$(CONFIG_MACH_OMAP3517EVM) += board-am3517evm.o | 112 | obj-$(CONFIG_MACH_OMAP3517EVM) += board-am3517evm.o |
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c index db9374bc528b..e508904fb67e 100644 --- a/arch/arm/mach-omap2/board-2430sdp.c +++ b/arch/arm/mach-omap2/board-2430sdp.c | |||
@@ -19,7 +19,7 @@ | |||
19 | #include <linux/mtd/mtd.h> | 19 | #include <linux/mtd/mtd.h> |
20 | #include <linux/mtd/partitions.h> | 20 | #include <linux/mtd/partitions.h> |
21 | #include <linux/delay.h> | 21 | #include <linux/delay.h> |
22 | #include <linux/i2c/twl4030.h> | 22 | #include <linux/i2c/twl.h> |
23 | #include <linux/err.h> | 23 | #include <linux/err.h> |
24 | #include <linux/clk.h> | 24 | #include <linux/clk.h> |
25 | #include <linux/io.h> | 25 | #include <linux/io.h> |
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c index 5bda9fdbee9e..c90b0d0b1927 100644 --- a/arch/arm/mach-omap2/board-3430sdp.c +++ b/arch/arm/mach-omap2/board-3430sdp.c | |||
@@ -20,7 +20,7 @@ | |||
20 | #include <linux/input/matrix_keypad.h> | 20 | #include <linux/input/matrix_keypad.h> |
21 | #include <linux/spi/spi.h> | 21 | #include <linux/spi/spi.h> |
22 | #include <linux/spi/ads7846.h> | 22 | #include <linux/spi/ads7846.h> |
23 | #include <linux/i2c/twl4030.h> | 23 | #include <linux/i2c/twl.h> |
24 | #include <linux/regulator/machine.h> | 24 | #include <linux/regulator/machine.h> |
25 | #include <linux/io.h> | 25 | #include <linux/io.h> |
26 | #include <linux/gpio.h> | 26 | #include <linux/gpio.h> |
@@ -31,7 +31,6 @@ | |||
31 | #include <asm/mach/map.h> | 31 | #include <asm/mach/map.h> |
32 | 32 | ||
33 | #include <plat/mcspi.h> | 33 | #include <plat/mcspi.h> |
34 | #include <plat/mux.h> | ||
35 | #include <plat/board.h> | 34 | #include <plat/board.h> |
36 | #include <plat/usb.h> | 35 | #include <plat/usb.h> |
37 | #include <plat/common.h> | 36 | #include <plat/common.h> |
@@ -42,6 +41,7 @@ | |||
42 | #include <plat/control.h> | 41 | #include <plat/control.h> |
43 | #include <plat/gpmc-smc91x.h> | 42 | #include <plat/gpmc-smc91x.h> |
44 | 43 | ||
44 | #include "mux.h" | ||
45 | #include "sdram-qimonda-hyb18m512160af-6.h" | 45 | #include "sdram-qimonda-hyb18m512160af-6.h" |
46 | #include "mmc-twl4030.h" | 46 | #include "mmc-twl4030.h" |
47 | 47 | ||
@@ -625,7 +625,9 @@ static inline void board_smc91x_init(void) | |||
625 | 625 | ||
626 | static void enable_board_wakeup_source(void) | 626 | static void enable_board_wakeup_source(void) |
627 | { | 627 | { |
628 | omap_cfg_reg(AF26_34XX_SYS_NIRQ); /* T2 interrupt line (keypad) */ | 628 | /* T2 interrupt line (keypad) */ |
629 | omap_mux_init_signal("sys_nirq", | ||
630 | OMAP_WAKEUP_EN | OMAP_PIN_INPUT_PULLUP); | ||
629 | } | 631 | } |
630 | 632 | ||
631 | static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { | 633 | static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { |
@@ -640,8 +642,17 @@ static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { | |||
640 | .reset_gpio_port[2] = -EINVAL | 642 | .reset_gpio_port[2] = -EINVAL |
641 | }; | 643 | }; |
642 | 644 | ||
645 | #ifdef CONFIG_OMAP_MUX | ||
646 | static struct omap_board_mux board_mux[] __initdata = { | ||
647 | { .reg_offset = OMAP_MUX_TERMINATOR }, | ||
648 | }; | ||
649 | #else | ||
650 | #define board_mux NULL | ||
651 | #endif | ||
652 | |||
643 | static void __init omap_3430sdp_init(void) | 653 | static void __init omap_3430sdp_init(void) |
644 | { | 654 | { |
655 | omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); | ||
645 | omap3430_i2c_init(); | 656 | omap3430_i2c_init(); |
646 | platform_add_devices(sdp3430_devices, ARRAY_SIZE(sdp3430_devices)); | 657 | platform_add_devices(sdp3430_devices, ARRAY_SIZE(sdp3430_devices)); |
647 | if (omap_rev() > OMAP3430_REV_ES1_0) | 658 | if (omap_rev() > OMAP3430_REV_ES1_0) |
diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c index 348b70b98336..739059632811 100755 --- a/arch/arm/mach-omap2/board-3630sdp.c +++ b/arch/arm/mach-omap2/board-3630sdp.c | |||
@@ -23,6 +23,7 @@ | |||
23 | 23 | ||
24 | #include <mach/board-zoom.h> | 24 | #include <mach/board-zoom.h> |
25 | 25 | ||
26 | #include "mux.h" | ||
26 | #include "sdram-hynix-h8mbx00u0mer-0em.h" | 27 | #include "sdram-hynix-h8mbx00u0mer-0em.h" |
27 | 28 | ||
28 | #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) | 29 | #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) |
@@ -48,7 +49,9 @@ static inline void board_smc91x_init(void) | |||
48 | 49 | ||
49 | static void enable_board_wakeup_source(void) | 50 | static void enable_board_wakeup_source(void) |
50 | { | 51 | { |
51 | omap_cfg_reg(AF26_34XX_SYS_NIRQ); /* T2 interrupt line (keypad) */ | 52 | /* T2 interrupt line (keypad) */ |
53 | omap_mux_init_signal("sys_nirq", | ||
54 | OMAP_WAKEUP_EN | OMAP_PIN_INPUT_PULLUP); | ||
52 | } | 55 | } |
53 | 56 | ||
54 | static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { | 57 | static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { |
@@ -82,8 +85,17 @@ static void __init omap_sdp_init_irq(void) | |||
82 | omap_gpio_init(); | 85 | omap_gpio_init(); |
83 | } | 86 | } |
84 | 87 | ||
88 | #ifdef CONFIG_OMAP_MUX | ||
89 | static struct omap_board_mux board_mux[] __initdata = { | ||
90 | { .reg_offset = OMAP_MUX_TERMINATOR }, | ||
91 | }; | ||
92 | #else | ||
93 | #define board_mux NULL | ||
94 | #endif | ||
95 | |||
85 | static void __init omap_sdp_init(void) | 96 | static void __init omap_sdp_init(void) |
86 | { | 97 | { |
98 | omap3_mux_init(board_mux, OMAP_PACKAGE_CBP); | ||
87 | zoom_peripherals_init(); | 99 | zoom_peripherals_init(); |
88 | board_smc91x_init(); | 100 | board_smc91x_init(); |
89 | enable_board_wakeup_source(); | 101 | enable_board_wakeup_source(); |
diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c index 415a13d767cc..b4e6eca0e8a9 100644 --- a/arch/arm/mach-omap2/board-am3517evm.c +++ b/arch/arm/mach-omap2/board-am3517evm.c | |||
@@ -30,6 +30,8 @@ | |||
30 | #include <plat/common.h> | 30 | #include <plat/common.h> |
31 | #include <plat/usb.h> | 31 | #include <plat/usb.h> |
32 | 32 | ||
33 | #include "mux.h" | ||
34 | |||
33 | /* | 35 | /* |
34 | * Board initialization | 36 | * Board initialization |
35 | */ | 37 | */ |
@@ -60,8 +62,17 @@ static struct ehci_hcd_omap_platform_data ehci_pdata __initdata = { | |||
60 | .reset_gpio_port[2] = -EINVAL | 62 | .reset_gpio_port[2] = -EINVAL |
61 | }; | 63 | }; |
62 | 64 | ||
65 | #ifdef CONFIG_OMAP_MUX | ||
66 | static struct omap_board_mux board_mux[] __initdata = { | ||
67 | { .reg_offset = OMAP_MUX_TERMINATOR }, | ||
68 | }; | ||
69 | #else | ||
70 | #define board_mux NULL | ||
71 | #endif | ||
72 | |||
63 | static void __init am3517_evm_init(void) | 73 | static void __init am3517_evm_init(void) |
64 | { | 74 | { |
75 | omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); | ||
65 | platform_add_devices(am3517_evm_devices, | 76 | platform_add_devices(am3517_evm_devices, |
66 | ARRAY_SIZE(am3517_evm_devices)); | 77 | ARRAY_SIZE(am3517_evm_devices)); |
67 | 78 | ||
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c index 8a2ce77a02ec..fbbd68d69cc8 100644 --- a/arch/arm/mach-omap2/board-apollon.c +++ b/arch/arm/mach-omap2/board-apollon.c | |||
@@ -26,6 +26,7 @@ | |||
26 | #include <linux/leds.h> | 26 | #include <linux/leds.h> |
27 | #include <linux/err.h> | 27 | #include <linux/err.h> |
28 | #include <linux/clk.h> | 28 | #include <linux/clk.h> |
29 | #include <linux/smc91x.h> | ||
29 | 30 | ||
30 | #include <mach/hardware.h> | 31 | #include <mach/hardware.h> |
31 | #include <asm/mach-types.h> | 32 | #include <asm/mach-types.h> |
@@ -120,6 +121,12 @@ static void __init apollon_flash_init(void) | |||
120 | apollon_flash_resource[0].end = base + SZ_128K - 1; | 121 | apollon_flash_resource[0].end = base + SZ_128K - 1; |
121 | } | 122 | } |
122 | 123 | ||
124 | static struct smc91x_platdata appolon_smc91x_info = { | ||
125 | .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, | ||
126 | .leda = RPC_LED_100_10, | ||
127 | .ledb = RPC_LED_TX_RX, | ||
128 | }; | ||
129 | |||
123 | static struct resource apollon_smc91x_resources[] = { | 130 | static struct resource apollon_smc91x_resources[] = { |
124 | [0] = { | 131 | [0] = { |
125 | .flags = IORESOURCE_MEM, | 132 | .flags = IORESOURCE_MEM, |
@@ -134,6 +141,9 @@ static struct resource apollon_smc91x_resources[] = { | |||
134 | static struct platform_device apollon_smc91x_device = { | 141 | static struct platform_device apollon_smc91x_device = { |
135 | .name = "smc91x", | 142 | .name = "smc91x", |
136 | .id = -1, | 143 | .id = -1, |
144 | .dev = { | ||
145 | .platform_data = &appolon_smc91x_info, | ||
146 | }, | ||
137 | .num_resources = ARRAY_SIZE(apollon_smc91x_resources), | 147 | .num_resources = ARRAY_SIZE(apollon_smc91x_resources), |
138 | .resource = apollon_smc91x_resources, | 148 | .resource = apollon_smc91x_resources, |
139 | }; | 149 | }; |
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c index 22c45290db63..1591aae64500 100644 --- a/arch/arm/mach-omap2/board-cm-t35.c +++ b/arch/arm/mach-omap2/board-cm-t35.c | |||
@@ -38,13 +38,13 @@ | |||
38 | 38 | ||
39 | #include <plat/board.h> | 39 | #include <plat/board.h> |
40 | #include <plat/common.h> | 40 | #include <plat/common.h> |
41 | #include <plat/mux.h> | ||
42 | #include <plat/nand.h> | 41 | #include <plat/nand.h> |
43 | #include <plat/gpmc.h> | 42 | #include <plat/gpmc.h> |
44 | #include <plat/usb.h> | 43 | #include <plat/usb.h> |
45 | 44 | ||
46 | #include <mach/hardware.h> | 45 | #include <mach/hardware.h> |
47 | 46 | ||
47 | #include "mux.h" | ||
48 | #include "sdram-micron-mt46h32m32lf-6.h" | 48 | #include "sdram-micron-mt46h32m32lf-6.h" |
49 | #include "mmc-twl4030.h" | 49 | #include "mmc-twl4030.h" |
50 | 50 | ||
@@ -482,8 +482,102 @@ static void __init cm_t35_map_io(void) | |||
482 | omap2_map_common_io(); | 482 | omap2_map_common_io(); |
483 | } | 483 | } |
484 | 484 | ||
485 | static struct omap_board_mux board_mux[] __initdata = { | ||
486 | /* nCS and IRQ for CM-T35 ethernet */ | ||
487 | OMAP3_MUX(GPMC_NCS5, OMAP_MUX_MODE0), | ||
488 | OMAP3_MUX(UART3_CTS_RCTX, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP), | ||
489 | |||
490 | /* nCS and IRQ for SB-T35 ethernet */ | ||
491 | OMAP3_MUX(GPMC_NCS4, OMAP_MUX_MODE0), | ||
492 | OMAP3_MUX(GPMC_WAIT3, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP), | ||
493 | |||
494 | /* PENDOWN GPIO */ | ||
495 | OMAP3_MUX(GPMC_NCS6, OMAP_MUX_MODE4 | OMAP_PIN_INPUT), | ||
496 | |||
497 | /* mUSB */ | ||
498 | OMAP3_MUX(HSUSB0_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | ||
499 | OMAP3_MUX(HSUSB0_STP, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | ||
500 | OMAP3_MUX(HSUSB0_DIR, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | ||
501 | OMAP3_MUX(HSUSB0_NXT, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | ||
502 | OMAP3_MUX(HSUSB0_DATA0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | ||
503 | OMAP3_MUX(HSUSB0_DATA1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | ||
504 | OMAP3_MUX(HSUSB0_DATA2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | ||
505 | OMAP3_MUX(HSUSB0_DATA3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | ||
506 | OMAP3_MUX(HSUSB0_DATA4, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | ||
507 | OMAP3_MUX(HSUSB0_DATA5, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | ||
508 | OMAP3_MUX(HSUSB0_DATA6, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | ||
509 | OMAP3_MUX(HSUSB0_DATA7, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | ||
510 | |||
511 | /* MMC 2 */ | ||
512 | OMAP3_MUX(SDMMC2_DAT4, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT), | ||
513 | OMAP3_MUX(SDMMC2_DAT5, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT), | ||
514 | OMAP3_MUX(SDMMC2_DAT6, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT), | ||
515 | OMAP3_MUX(SDMMC2_DAT7, OMAP_MUX_MODE1 | OMAP_PIN_INPUT), | ||
516 | |||
517 | /* McSPI 1 */ | ||
518 | OMAP3_MUX(MCSPI1_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | ||
519 | OMAP3_MUX(MCSPI1_SIMO, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | ||
520 | OMAP3_MUX(MCSPI1_SOMI, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | ||
521 | OMAP3_MUX(MCSPI1_CS0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN), | ||
522 | |||
523 | /* McSPI 4 */ | ||
524 | OMAP3_MUX(MCBSP1_CLKR, OMAP_MUX_MODE1 | OMAP_PIN_INPUT), | ||
525 | OMAP3_MUX(MCBSP1_DX, OMAP_MUX_MODE1 | OMAP_PIN_INPUT), | ||
526 | OMAP3_MUX(MCBSP1_DR, OMAP_MUX_MODE1 | OMAP_PIN_INPUT), | ||
527 | OMAP3_MUX(MCBSP1_FSX, OMAP_MUX_MODE1 | OMAP_PIN_INPUT_PULLUP), | ||
528 | |||
529 | /* McBSP 2 */ | ||
530 | OMAP3_MUX(MCBSP2_FSX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | ||
531 | OMAP3_MUX(MCBSP2_CLKX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | ||
532 | OMAP3_MUX(MCBSP2_DR, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | ||
533 | OMAP3_MUX(MCBSP2_DX, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | ||
534 | |||
535 | /* serial ports */ | ||
536 | OMAP3_MUX(MCBSP3_CLKX, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT), | ||
537 | OMAP3_MUX(MCBSP3_FSX, OMAP_MUX_MODE1 | OMAP_PIN_INPUT), | ||
538 | OMAP3_MUX(UART1_TX, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | ||
539 | OMAP3_MUX(UART1_RX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | ||
540 | |||
541 | /* DSS */ | ||
542 | OMAP3_MUX(DSS_PCLK, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | ||
543 | OMAP3_MUX(DSS_HSYNC, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | ||
544 | OMAP3_MUX(DSS_VSYNC, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | ||
545 | OMAP3_MUX(DSS_ACBIAS, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | ||
546 | OMAP3_MUX(DSS_DATA0, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | ||
547 | OMAP3_MUX(DSS_DATA1, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | ||
548 | OMAP3_MUX(DSS_DATA2, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | ||
549 | OMAP3_MUX(DSS_DATA3, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | ||
550 | OMAP3_MUX(DSS_DATA4, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | ||
551 | OMAP3_MUX(DSS_DATA5, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | ||
552 | OMAP3_MUX(DSS_DATA6, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | ||
553 | OMAP3_MUX(DSS_DATA7, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | ||
554 | OMAP3_MUX(DSS_DATA8, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | ||
555 | OMAP3_MUX(DSS_DATA9, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | ||
556 | OMAP3_MUX(DSS_DATA10, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | ||
557 | OMAP3_MUX(DSS_DATA11, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | ||
558 | OMAP3_MUX(DSS_DATA12, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | ||
559 | OMAP3_MUX(DSS_DATA13, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | ||
560 | OMAP3_MUX(DSS_DATA14, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | ||
561 | OMAP3_MUX(DSS_DATA15, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | ||
562 | OMAP3_MUX(DSS_DATA16, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | ||
563 | OMAP3_MUX(DSS_DATA17, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | ||
564 | OMAP3_MUX(DSS_DATA18, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | ||
565 | OMAP3_MUX(DSS_DATA19, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | ||
566 | OMAP3_MUX(DSS_DATA20, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | ||
567 | OMAP3_MUX(DSS_DATA21, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | ||
568 | OMAP3_MUX(DSS_DATA22, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | ||
569 | OMAP3_MUX(DSS_DATA23, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | ||
570 | |||
571 | /* TPS IRQ */ | ||
572 | OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_WAKEUP_EN | \ | ||
573 | OMAP_PIN_INPUT_PULLUP), | ||
574 | |||
575 | { .reg_offset = OMAP_MUX_TERMINATOR }, | ||
576 | }; | ||
577 | |||
485 | static void __init cm_t35_init(void) | 578 | static void __init cm_t35_init(void) |
486 | { | 579 | { |
580 | omap3_mux_init(board_mux, OMAP_PACKAGE_CUS); | ||
487 | omap_serial_init(); | 581 | omap_serial_init(); |
488 | cm_t35_init_i2c(); | 582 | cm_t35_init_i2c(); |
489 | cm_t35_init_nand(); | 583 | cm_t35_init_nand(); |
@@ -492,8 +586,6 @@ static void __init cm_t35_init(void) | |||
492 | cm_t35_init_led(); | 586 | cm_t35_init_led(); |
493 | 587 | ||
494 | usb_musb_init(); | 588 | usb_musb_init(); |
495 | |||
496 | omap_cfg_reg(AF26_34XX_SYS_NIRQ); | ||
497 | } | 589 | } |
498 | 590 | ||
499 | MACHINE_START(CM_T35, "Compulab CM-T35") | 591 | MACHINE_START(CM_T35, "Compulab CM-T35") |
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c index fa62e80c13b7..44239e3ec02e 100644 --- a/arch/arm/mach-omap2/board-igep0020.c +++ b/arch/arm/mach-omap2/board-igep0020.c | |||
@@ -27,9 +27,9 @@ | |||
27 | #include <plat/board.h> | 27 | #include <plat/board.h> |
28 | #include <plat/common.h> | 28 | #include <plat/common.h> |
29 | #include <plat/gpmc.h> | 29 | #include <plat/gpmc.h> |
30 | #include <plat/mux.h> | ||
31 | #include <plat/usb.h> | 30 | #include <plat/usb.h> |
32 | 31 | ||
32 | #include "mux.h" | ||
33 | #include "mmc-twl4030.h" | 33 | #include "mmc-twl4030.h" |
34 | 34 | ||
35 | #define IGEP2_SMSC911X_CS 5 | 35 | #define IGEP2_SMSC911X_CS 5 |
@@ -203,8 +203,17 @@ static int __init igep2_i2c_init(void) | |||
203 | return 0; | 203 | return 0; |
204 | } | 204 | } |
205 | 205 | ||
206 | #ifdef CONFIG_OMAP_MUX | ||
207 | static struct omap_board_mux board_mux[] __initdata = { | ||
208 | { .reg_offset = OMAP_MUX_TERMINATOR }, | ||
209 | }; | ||
210 | #else | ||
211 | #define board_mux NULL | ||
212 | #endif | ||
213 | |||
206 | static void __init igep2_init(void) | 214 | static void __init igep2_init(void) |
207 | { | 215 | { |
216 | omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); | ||
208 | igep2_i2c_init(); | 217 | igep2_i2c_init(); |
209 | omap_serial_init(); | 218 | omap_serial_init(); |
210 | usb_musb_init(); | 219 | usb_musb_init(); |
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c index c062238fe881..995d4a2b2dfd 100644 --- a/arch/arm/mach-omap2/board-ldp.c +++ b/arch/arm/mach-omap2/board-ldp.c | |||
@@ -24,7 +24,7 @@ | |||
24 | #include <linux/spi/spi.h> | 24 | #include <linux/spi/spi.h> |
25 | #include <linux/spi/ads7846.h> | 25 | #include <linux/spi/ads7846.h> |
26 | #include <linux/regulator/machine.h> | 26 | #include <linux/regulator/machine.h> |
27 | #include <linux/i2c/twl4030.h> | 27 | #include <linux/i2c/twl.h> |
28 | #include <linux/io.h> | 28 | #include <linux/io.h> |
29 | #include <linux/smsc911x.h> | 29 | #include <linux/smsc911x.h> |
30 | 30 | ||
@@ -43,6 +43,7 @@ | |||
43 | #include <plat/control.h> | 43 | #include <plat/control.h> |
44 | #include <plat/usb.h> | 44 | #include <plat/usb.h> |
45 | 45 | ||
46 | #include "mux.h" | ||
46 | #include "mmc-twl4030.h" | 47 | #include "mmc-twl4030.h" |
47 | 48 | ||
48 | #define LDP_SMSC911X_CS 1 | 49 | #define LDP_SMSC911X_CS 1 |
@@ -374,8 +375,17 @@ static struct platform_device *ldp_devices[] __initdata = { | |||
374 | &ldp_gpio_keys_device, | 375 | &ldp_gpio_keys_device, |
375 | }; | 376 | }; |
376 | 377 | ||
378 | #ifdef CONFIG_OMAP_MUX | ||
379 | static struct omap_board_mux board_mux[] __initdata = { | ||
380 | { .reg_offset = OMAP_MUX_TERMINATOR }, | ||
381 | }; | ||
382 | #else | ||
383 | #define board_mux NULL | ||
384 | #endif | ||
385 | |||
377 | static void __init omap_ldp_init(void) | 386 | static void __init omap_ldp_init(void) |
378 | { | 387 | { |
388 | omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); | ||
379 | omap_i2c_init(); | 389 | omap_i2c_init(); |
380 | platform_add_devices(ldp_devices, ARRAY_SIZE(ldp_devices)); | 390 | platform_add_devices(ldp_devices, ARRAY_SIZE(ldp_devices)); |
381 | ts_gpio = 54; | 391 | ts_gpio = 54; |
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c index 41480bd0e58a..231cb4ec1847 100644 --- a/arch/arm/mach-omap2/board-omap3beagle.c +++ b/arch/arm/mach-omap2/board-omap3beagle.c | |||
@@ -29,7 +29,7 @@ | |||
29 | #include <linux/mtd/nand.h> | 29 | #include <linux/mtd/nand.h> |
30 | 30 | ||
31 | #include <linux/regulator/machine.h> | 31 | #include <linux/regulator/machine.h> |
32 | #include <linux/i2c/twl4030.h> | 32 | #include <linux/i2c/twl.h> |
33 | 33 | ||
34 | #include <mach/hardware.h> | 34 | #include <mach/hardware.h> |
35 | #include <asm/mach-types.h> | 35 | #include <asm/mach-types.h> |
@@ -41,10 +41,10 @@ | |||
41 | #include <plat/common.h> | 41 | #include <plat/common.h> |
42 | #include <plat/gpmc.h> | 42 | #include <plat/gpmc.h> |
43 | #include <plat/nand.h> | 43 | #include <plat/nand.h> |
44 | #include <plat/mux.h> | ||
45 | #include <plat/usb.h> | 44 | #include <plat/usb.h> |
46 | #include <plat/timer-gp.h> | 45 | #include <plat/timer-gp.h> |
47 | 46 | ||
47 | #include "mux.h" | ||
48 | #include "mmc-twl4030.h" | 48 | #include "mmc-twl4030.h" |
49 | 49 | ||
50 | #define GPMC_CS0_BASE 0x60 | 50 | #define GPMC_CS0_BASE 0x60 |
@@ -140,10 +140,10 @@ static int beagle_twl_gpio_setup(struct device *dev, | |||
140 | unsigned gpio, unsigned ngpio) | 140 | unsigned gpio, unsigned ngpio) |
141 | { | 141 | { |
142 | if (system_rev >= 0x20 && system_rev <= 0x34301000) { | 142 | if (system_rev >= 0x20 && system_rev <= 0x34301000) { |
143 | omap_cfg_reg(AG9_34XX_GPIO23); | 143 | omap_mux_init_gpio(23, OMAP_PIN_INPUT); |
144 | mmc[0].gpio_wp = 23; | 144 | mmc[0].gpio_wp = 23; |
145 | } else { | 145 | } else { |
146 | omap_cfg_reg(AH8_34XX_GPIO29); | 146 | omap_mux_init_gpio(29, OMAP_PIN_INPUT); |
147 | } | 147 | } |
148 | /* gpio + 0 is "mmc0_cd" (input/IRQ) */ | 148 | /* gpio + 0 is "mmc0_cd" (input/IRQ) */ |
149 | mmc[0].gpio_cd = gpio + 0; | 149 | mmc[0].gpio_cd = gpio + 0; |
@@ -422,14 +422,23 @@ static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { | |||
422 | .reset_gpio_port[2] = -EINVAL | 422 | .reset_gpio_port[2] = -EINVAL |
423 | }; | 423 | }; |
424 | 424 | ||
425 | #ifdef CONFIG_OMAP_MUX | ||
426 | static struct omap_board_mux board_mux[] __initdata = { | ||
427 | { .reg_offset = OMAP_MUX_TERMINATOR }, | ||
428 | }; | ||
429 | #else | ||
430 | #define board_mux NULL | ||
431 | #endif | ||
432 | |||
425 | static void __init omap3_beagle_init(void) | 433 | static void __init omap3_beagle_init(void) |
426 | { | 434 | { |
435 | omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); | ||
427 | omap3_beagle_i2c_init(); | 436 | omap3_beagle_i2c_init(); |
428 | platform_add_devices(omap3_beagle_devices, | 437 | platform_add_devices(omap3_beagle_devices, |
429 | ARRAY_SIZE(omap3_beagle_devices)); | 438 | ARRAY_SIZE(omap3_beagle_devices)); |
430 | omap_serial_init(); | 439 | omap_serial_init(); |
431 | 440 | ||
432 | omap_cfg_reg(J25_34XX_GPIO170); | 441 | omap_mux_init_gpio(170, OMAP_PIN_INPUT); |
433 | gpio_request(170, "DVI_nPD"); | 442 | gpio_request(170, "DVI_nPD"); |
434 | /* REVISIT leave DVI powered down until it's needed ... */ | 443 | /* REVISIT leave DVI powered down until it's needed ... */ |
435 | gpio_direction_output(170, true); | 444 | gpio_direction_output(170, true); |
@@ -439,8 +448,8 @@ static void __init omap3_beagle_init(void) | |||
439 | omap3beagle_flash_init(); | 448 | omap3beagle_flash_init(); |
440 | 449 | ||
441 | /* Ensure SDRC pins are mux'd for self-refresh */ | 450 | /* Ensure SDRC pins are mux'd for self-refresh */ |
442 | omap_cfg_reg(H16_34XX_SDRC_CKE0); | 451 | omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT); |
443 | omap_cfg_reg(H17_34XX_SDRC_CKE1); | 452 | omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT); |
444 | } | 453 | } |
445 | 454 | ||
446 | static void __init omap3_beagle_map_io(void) | 455 | static void __init omap3_beagle_map_io(void) |
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c index 5efc2e9068db..18913e96e34d 100644 --- a/arch/arm/mach-omap2/board-omap3evm.c +++ b/arch/arm/mach-omap2/board-omap3evm.c | |||
@@ -38,11 +38,11 @@ | |||
38 | #include <asm/mach/map.h> | 38 | #include <asm/mach/map.h> |
39 | 39 | ||
40 | #include <plat/board.h> | 40 | #include <plat/board.h> |
41 | #include <plat/mux.h> | ||
42 | #include <plat/usb.h> | 41 | #include <plat/usb.h> |
43 | #include <plat/common.h> | 42 | #include <plat/common.h> |
44 | #include <plat/mcspi.h> | 43 | #include <plat/mcspi.h> |
45 | 44 | ||
45 | #include "mux.h" | ||
46 | #include "sdram-micron-mt46h32m32lf-6.h" | 46 | #include "sdram-micron-mt46h32m32lf-6.h" |
47 | #include "mmc-twl4030.h" | 47 | #include "mmc-twl4030.h" |
48 | 48 | ||
@@ -223,7 +223,7 @@ static int omap3evm_twl_gpio_setup(struct device *dev, | |||
223 | unsigned gpio, unsigned ngpio) | 223 | unsigned gpio, unsigned ngpio) |
224 | { | 224 | { |
225 | /* gpio + 0 is "mmc0_cd" (input/IRQ) */ | 225 | /* gpio + 0 is "mmc0_cd" (input/IRQ) */ |
226 | omap_cfg_reg(L8_34XX_GPIO63); | 226 | omap_mux_init_gpio(63, OMAP_PIN_INPUT); |
227 | mmc[0].gpio_cd = gpio + 0; | 227 | mmc[0].gpio_cd = gpio + 0; |
228 | twl4030_mmc_init(mmc); | 228 | twl4030_mmc_init(mmc); |
229 | 229 | ||
@@ -422,9 +422,18 @@ static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { | |||
422 | .reset_gpio_port[2] = -EINVAL | 422 | .reset_gpio_port[2] = -EINVAL |
423 | }; | 423 | }; |
424 | 424 | ||
425 | #ifdef CONFIG_OMAP_MUX | ||
426 | static struct omap_board_mux board_mux[] __initdata = { | ||
427 | { .reg_offset = OMAP_MUX_TERMINATOR }, | ||
428 | }; | ||
429 | #else | ||
430 | #define board_mux NULL | ||
431 | #endif | ||
432 | |||
425 | static void __init omap3_evm_init(void) | 433 | static void __init omap3_evm_init(void) |
426 | { | 434 | { |
427 | omap3_evm_get_revision(); | 435 | omap3_evm_get_revision(); |
436 | omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); | ||
428 | 437 | ||
429 | omap3_evm_i2c_init(); | 438 | omap3_evm_i2c_init(); |
430 | 439 | ||
@@ -440,24 +449,24 @@ static void __init omap3_evm_init(void) | |||
440 | #endif | 449 | #endif |
441 | if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2) { | 450 | if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2) { |
442 | /* enable EHCI VBUS using GPIO22 */ | 451 | /* enable EHCI VBUS using GPIO22 */ |
443 | omap_cfg_reg(AF9_34XX_GPIO22); | 452 | omap_mux_init_gpio(22, OMAP_PIN_INPUT_PULLUP); |
444 | gpio_request(OMAP3_EVM_EHCI_VBUS, "enable EHCI VBUS"); | 453 | gpio_request(OMAP3_EVM_EHCI_VBUS, "enable EHCI VBUS"); |
445 | gpio_direction_output(OMAP3_EVM_EHCI_VBUS, 0); | 454 | gpio_direction_output(OMAP3_EVM_EHCI_VBUS, 0); |
446 | gpio_set_value(OMAP3_EVM_EHCI_VBUS, 1); | 455 | gpio_set_value(OMAP3_EVM_EHCI_VBUS, 1); |
447 | 456 | ||
448 | /* Select EHCI port on main board */ | 457 | /* Select EHCI port on main board */ |
449 | omap_cfg_reg(U3_34XX_GPIO61); | 458 | omap_mux_init_gpio(61, OMAP_PIN_INPUT_PULLUP); |
450 | gpio_request(OMAP3_EVM_EHCI_SELECT, "select EHCI port"); | 459 | gpio_request(OMAP3_EVM_EHCI_SELECT, "select EHCI port"); |
451 | gpio_direction_output(OMAP3_EVM_EHCI_SELECT, 0); | 460 | gpio_direction_output(OMAP3_EVM_EHCI_SELECT, 0); |
452 | gpio_set_value(OMAP3_EVM_EHCI_SELECT, 0); | 461 | gpio_set_value(OMAP3_EVM_EHCI_SELECT, 0); |
453 | 462 | ||
454 | /* setup EHCI phy reset config */ | 463 | /* setup EHCI phy reset config */ |
455 | omap_cfg_reg(AH14_34XX_GPIO21); | 464 | omap_mux_init_gpio(21, OMAP_PIN_INPUT_PULLUP); |
456 | ehci_pdata.reset_gpio_port[1] = 21; | 465 | ehci_pdata.reset_gpio_port[1] = 21; |
457 | 466 | ||
458 | } else { | 467 | } else { |
459 | /* setup EHCI phy reset on MDC */ | 468 | /* setup EHCI phy reset on MDC */ |
460 | omap_cfg_reg(AF4_34XX_GPIO135_OUT); | 469 | omap_mux_init_gpio(135, OMAP_PIN_OUTPUT); |
461 | ehci_pdata.reset_gpio_port[1] = 135; | 470 | ehci_pdata.reset_gpio_port[1] = 135; |
462 | } | 471 | } |
463 | usb_musb_init(); | 472 | usb_musb_init(); |
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c index 2db5ba5b3bf7..ef17cf1ab6d7 100644 --- a/arch/arm/mach-omap2/board-omap3pandora.c +++ b/arch/arm/mach-omap2/board-omap3pandora.c | |||
@@ -24,7 +24,7 @@ | |||
24 | #include <linux/spi/spi.h> | 24 | #include <linux/spi/spi.h> |
25 | #include <linux/spi/ads7846.h> | 25 | #include <linux/spi/ads7846.h> |
26 | #include <linux/regulator/machine.h> | 26 | #include <linux/regulator/machine.h> |
27 | #include <linux/i2c/twl4030.h> | 27 | #include <linux/i2c/twl.h> |
28 | #include <linux/leds.h> | 28 | #include <linux/leds.h> |
29 | #include <linux/input.h> | 29 | #include <linux/input.h> |
30 | #include <linux/input/matrix_keypad.h> | 30 | #include <linux/input/matrix_keypad.h> |
@@ -40,8 +40,8 @@ | |||
40 | #include <mach/hardware.h> | 40 | #include <mach/hardware.h> |
41 | #include <plat/mcspi.h> | 41 | #include <plat/mcspi.h> |
42 | #include <plat/usb.h> | 42 | #include <plat/usb.h> |
43 | #include <plat/mux.h> | ||
44 | 43 | ||
44 | #include "mux.h" | ||
45 | #include "sdram-micron-mt46h32m32lf-6.h" | 45 | #include "sdram-micron-mt46h32m32lf-6.h" |
46 | #include "mmc-twl4030.h" | 46 | #include "mmc-twl4030.h" |
47 | 47 | ||
@@ -98,10 +98,10 @@ static struct gpio_keys_button pandora_gpio_keys[] = { | |||
98 | GPIO_BUTTON_LOW(103, KEY_DOWN, "down"), | 98 | GPIO_BUTTON_LOW(103, KEY_DOWN, "down"), |
99 | GPIO_BUTTON_LOW(96, KEY_LEFT, "left"), | 99 | GPIO_BUTTON_LOW(96, KEY_LEFT, "left"), |
100 | GPIO_BUTTON_LOW(98, KEY_RIGHT, "right"), | 100 | GPIO_BUTTON_LOW(98, KEY_RIGHT, "right"), |
101 | GPIO_BUTTON_LOW(111, BTN_A, "a"), | 101 | GPIO_BUTTON_LOW(109, KEY_KP1, "game 1"), |
102 | GPIO_BUTTON_LOW(106, BTN_B, "b"), | 102 | GPIO_BUTTON_LOW(111, KEY_KP2, "game 2"), |
103 | GPIO_BUTTON_LOW(109, BTN_X, "x"), | 103 | GPIO_BUTTON_LOW(106, KEY_KP3, "game 3"), |
104 | GPIO_BUTTON_LOW(101, BTN_Y, "y"), | 104 | GPIO_BUTTON_LOW(101, KEY_KP4, "game 4"), |
105 | GPIO_BUTTON_LOW(102, BTN_TL, "l"), | 105 | GPIO_BUTTON_LOW(102, BTN_TL, "l"), |
106 | GPIO_BUTTON_LOW(97, BTN_TL2, "l2"), | 106 | GPIO_BUTTON_LOW(97, BTN_TL2, "l2"), |
107 | GPIO_BUTTON_LOW(105, BTN_TR, "r"), | 107 | GPIO_BUTTON_LOW(105, BTN_TR, "r"), |
@@ -315,7 +315,7 @@ static int __init omap3pandora_i2c_init(void) | |||
315 | omap_register_i2c_bus(1, 2600, omap3pandora_i2c_boardinfo, | 315 | omap_register_i2c_bus(1, 2600, omap3pandora_i2c_boardinfo, |
316 | ARRAY_SIZE(omap3pandora_i2c_boardinfo)); | 316 | ARRAY_SIZE(omap3pandora_i2c_boardinfo)); |
317 | /* i2c2 pins are not connected */ | 317 | /* i2c2 pins are not connected */ |
318 | omap_register_i2c_bus(3, 400, NULL, 0); | 318 | omap_register_i2c_bus(3, 100, NULL, 0); |
319 | return 0; | 319 | return 0; |
320 | } | 320 | } |
321 | 321 | ||
@@ -368,23 +368,8 @@ static struct spi_board_info omap3pandora_spi_board_info[] __initdata = { | |||
368 | } | 368 | } |
369 | }; | 369 | }; |
370 | 370 | ||
371 | static struct platform_device omap3pandora_lcd_device = { | ||
372 | .name = "pandora_lcd", | ||
373 | .id = -1, | ||
374 | }; | ||
375 | |||
376 | static struct omap_lcd_config omap3pandora_lcd_config __initdata = { | ||
377 | .ctrl_name = "internal", | ||
378 | }; | ||
379 | |||
380 | static struct omap_board_config_kernel omap3pandora_config[] __initdata = { | ||
381 | { OMAP_TAG_LCD, &omap3pandora_lcd_config }, | ||
382 | }; | ||
383 | |||
384 | static void __init omap3pandora_init_irq(void) | 371 | static void __init omap3pandora_init_irq(void) |
385 | { | 372 | { |
386 | omap_board_config = omap3pandora_config; | ||
387 | omap_board_config_size = ARRAY_SIZE(omap3pandora_config); | ||
388 | omap2_init_common_hw(mt46h32m32lf6_sdrc_params, | 373 | omap2_init_common_hw(mt46h32m32lf6_sdrc_params, |
389 | mt46h32m32lf6_sdrc_params); | 374 | mt46h32m32lf6_sdrc_params); |
390 | omap_init_irq(); | 375 | omap_init_irq(); |
@@ -392,7 +377,6 @@ static void __init omap3pandora_init_irq(void) | |||
392 | } | 377 | } |
393 | 378 | ||
394 | static struct platform_device *omap3pandora_devices[] __initdata = { | 379 | static struct platform_device *omap3pandora_devices[] __initdata = { |
395 | &omap3pandora_lcd_device, | ||
396 | &pandora_leds_gpio, | 380 | &pandora_leds_gpio, |
397 | &pandora_keys_gpio, | 381 | &pandora_keys_gpio, |
398 | }; | 382 | }; |
@@ -409,8 +393,17 @@ static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { | |||
409 | .reset_gpio_port[2] = -EINVAL | 393 | .reset_gpio_port[2] = -EINVAL |
410 | }; | 394 | }; |
411 | 395 | ||
396 | #ifdef CONFIG_OMAP_MUX | ||
397 | static struct omap_board_mux board_mux[] __initdata = { | ||
398 | { .reg_offset = OMAP_MUX_TERMINATOR }, | ||
399 | }; | ||
400 | #else | ||
401 | #define board_mux NULL | ||
402 | #endif | ||
403 | |||
412 | static void __init omap3pandora_init(void) | 404 | static void __init omap3pandora_init(void) |
413 | { | 405 | { |
406 | omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); | ||
414 | omap3pandora_i2c_init(); | 407 | omap3pandora_i2c_init(); |
415 | platform_add_devices(omap3pandora_devices, | 408 | platform_add_devices(omap3pandora_devices, |
416 | ARRAY_SIZE(omap3pandora_devices)); | 409 | ARRAY_SIZE(omap3pandora_devices)); |
@@ -423,8 +416,8 @@ static void __init omap3pandora_init(void) | |||
423 | usb_musb_init(); | 416 | usb_musb_init(); |
424 | 417 | ||
425 | /* Ensure SDRC pins are mux'd for self-refresh */ | 418 | /* Ensure SDRC pins are mux'd for self-refresh */ |
426 | omap_cfg_reg(H16_34XX_SDRC_CKE0); | 419 | omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT); |
427 | omap_cfg_reg(H17_34XX_SDRC_CKE1); | 420 | omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT); |
428 | } | 421 | } |
429 | 422 | ||
430 | static void __init omap3pandora_map_io(void) | 423 | static void __init omap3pandora_map_io(void) |
diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c new file mode 100644 index 000000000000..c9e5ebb4d91d --- /dev/null +++ b/arch/arm/mach-omap2/board-omap3touchbook.c | |||
@@ -0,0 +1,572 @@ | |||
1 | /* | ||
2 | * linux/arch/arm/mach-omap2/board-omap3touchbook.c | ||
3 | * | ||
4 | * Copyright (C) 2009 Always Innovating | ||
5 | * | ||
6 | * Modified from mach-omap2/board-omap3beagleboard.c | ||
7 | * | ||
8 | * Initial code: Grégoire Gentil, Tim Yamin | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #include <linux/kernel.h> | ||
16 | #include <linux/init.h> | ||
17 | #include <linux/platform_device.h> | ||
18 | #include <linux/delay.h> | ||
19 | #include <linux/err.h> | ||
20 | #include <linux/clk.h> | ||
21 | #include <linux/io.h> | ||
22 | #include <linux/leds.h> | ||
23 | #include <linux/gpio.h> | ||
24 | #include <linux/input.h> | ||
25 | #include <linux/gpio_keys.h> | ||
26 | |||
27 | #include <linux/mtd/mtd.h> | ||
28 | #include <linux/mtd/partitions.h> | ||
29 | #include <linux/mtd/nand.h> | ||
30 | |||
31 | #include <plat/mcspi.h> | ||
32 | #include <linux/spi/spi.h> | ||
33 | |||
34 | #include <linux/spi/ads7846.h> | ||
35 | |||
36 | #include <linux/regulator/machine.h> | ||
37 | #include <linux/i2c/twl4030.h> | ||
38 | |||
39 | #include <mach/hardware.h> | ||
40 | #include <asm/mach-types.h> | ||
41 | #include <asm/mach/arch.h> | ||
42 | #include <asm/mach/map.h> | ||
43 | #include <asm/mach/flash.h> | ||
44 | |||
45 | #include <plat/board.h> | ||
46 | #include <plat/common.h> | ||
47 | #include <plat/gpmc.h> | ||
48 | #include <plat/nand.h> | ||
49 | #include <plat/usb.h> | ||
50 | #include <plat/timer-gp.h> | ||
51 | |||
52 | #include "mux.h" | ||
53 | #include "mmc-twl4030.h" | ||
54 | |||
55 | #include <asm/setup.h> | ||
56 | |||
57 | #define GPMC_CS0_BASE 0x60 | ||
58 | #define GPMC_CS_SIZE 0x30 | ||
59 | |||
60 | #define NAND_BLOCK_SIZE SZ_128K | ||
61 | |||
62 | #define OMAP3_AC_GPIO 136 | ||
63 | #define OMAP3_TS_GPIO 162 | ||
64 | #define TB_BL_PWM_TIMER 9 | ||
65 | #define TB_KILL_POWER_GPIO 168 | ||
66 | |||
67 | unsigned long touchbook_revision; | ||
68 | |||
69 | static struct mtd_partition omap3touchbook_nand_partitions[] = { | ||
70 | /* All the partition sizes are listed in terms of NAND block size */ | ||
71 | { | ||
72 | .name = "X-Loader", | ||
73 | .offset = 0, | ||
74 | .size = 4 * NAND_BLOCK_SIZE, | ||
75 | .mask_flags = MTD_WRITEABLE, /* force read-only */ | ||
76 | }, | ||
77 | { | ||
78 | .name = "U-Boot", | ||
79 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */ | ||
80 | .size = 15 * NAND_BLOCK_SIZE, | ||
81 | .mask_flags = MTD_WRITEABLE, /* force read-only */ | ||
82 | }, | ||
83 | { | ||
84 | .name = "U-Boot Env", | ||
85 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x260000 */ | ||
86 | .size = 1 * NAND_BLOCK_SIZE, | ||
87 | }, | ||
88 | { | ||
89 | .name = "Kernel", | ||
90 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x280000 */ | ||
91 | .size = 32 * NAND_BLOCK_SIZE, | ||
92 | }, | ||
93 | { | ||
94 | .name = "File System", | ||
95 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x680000 */ | ||
96 | .size = MTDPART_SIZ_FULL, | ||
97 | }, | ||
98 | }; | ||
99 | |||
100 | static struct omap_nand_platform_data omap3touchbook_nand_data = { | ||
101 | .options = NAND_BUSWIDTH_16, | ||
102 | .parts = omap3touchbook_nand_partitions, | ||
103 | .nr_parts = ARRAY_SIZE(omap3touchbook_nand_partitions), | ||
104 | .dma_channel = -1, /* disable DMA in OMAP NAND driver */ | ||
105 | .nand_setup = NULL, | ||
106 | .dev_ready = NULL, | ||
107 | }; | ||
108 | |||
109 | static struct resource omap3touchbook_nand_resource = { | ||
110 | .flags = IORESOURCE_MEM, | ||
111 | }; | ||
112 | |||
113 | static struct platform_device omap3touchbook_nand_device = { | ||
114 | .name = "omap2-nand", | ||
115 | .id = -1, | ||
116 | .dev = { | ||
117 | .platform_data = &omap3touchbook_nand_data, | ||
118 | }, | ||
119 | .num_resources = 1, | ||
120 | .resource = &omap3touchbook_nand_resource, | ||
121 | }; | ||
122 | |||
123 | #include "sdram-micron-mt46h32m32lf-6.h" | ||
124 | |||
125 | static struct twl4030_hsmmc_info mmc[] = { | ||
126 | { | ||
127 | .mmc = 1, | ||
128 | .wires = 8, | ||
129 | .gpio_wp = 29, | ||
130 | }, | ||
131 | {} /* Terminator */ | ||
132 | }; | ||
133 | |||
134 | static struct platform_device omap3_touchbook_lcd_device = { | ||
135 | .name = "omap3touchbook_lcd", | ||
136 | .id = -1, | ||
137 | }; | ||
138 | |||
139 | static struct omap_lcd_config omap3_touchbook_lcd_config __initdata = { | ||
140 | .ctrl_name = "internal", | ||
141 | }; | ||
142 | |||
143 | static struct regulator_consumer_supply touchbook_vmmc1_supply = { | ||
144 | .supply = "vmmc", | ||
145 | }; | ||
146 | |||
147 | static struct regulator_consumer_supply touchbook_vsim_supply = { | ||
148 | .supply = "vmmc_aux", | ||
149 | }; | ||
150 | |||
151 | static struct gpio_led gpio_leds[]; | ||
152 | |||
153 | static int touchbook_twl_gpio_setup(struct device *dev, | ||
154 | unsigned gpio, unsigned ngpio) | ||
155 | { | ||
156 | if (system_rev >= 0x20 && system_rev <= 0x34301000) { | ||
157 | omap_mux_init_gpio(23, OMAP_PIN_INPUT); | ||
158 | mmc[0].gpio_wp = 23; | ||
159 | } else { | ||
160 | omap_mux_init_gpio(29, OMAP_PIN_INPUT); | ||
161 | } | ||
162 | /* gpio + 0 is "mmc0_cd" (input/IRQ) */ | ||
163 | mmc[0].gpio_cd = gpio + 0; | ||
164 | twl4030_mmc_init(mmc); | ||
165 | |||
166 | /* link regulators to MMC adapters */ | ||
167 | touchbook_vmmc1_supply.dev = mmc[0].dev; | ||
168 | touchbook_vsim_supply.dev = mmc[0].dev; | ||
169 | |||
170 | /* REVISIT: need ehci-omap hooks for external VBUS | ||
171 | * power switch and overcurrent detect | ||
172 | */ | ||
173 | |||
174 | gpio_request(gpio + 1, "EHCI_nOC"); | ||
175 | gpio_direction_input(gpio + 1); | ||
176 | |||
177 | /* TWL4030_GPIO_MAX + 0 == ledA, EHCI nEN_USB_PWR (out, active low) */ | ||
178 | gpio_request(gpio + TWL4030_GPIO_MAX, "nEN_USB_PWR"); | ||
179 | gpio_direction_output(gpio + TWL4030_GPIO_MAX, 0); | ||
180 | |||
181 | /* TWL4030_GPIO_MAX + 1 == ledB, PMU_STAT (out, active low LED) */ | ||
182 | gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1; | ||
183 | |||
184 | return 0; | ||
185 | } | ||
186 | |||
187 | static struct twl4030_gpio_platform_data touchbook_gpio_data = { | ||
188 | .gpio_base = OMAP_MAX_GPIO_LINES, | ||
189 | .irq_base = TWL4030_GPIO_IRQ_BASE, | ||
190 | .irq_end = TWL4030_GPIO_IRQ_END, | ||
191 | .use_leds = true, | ||
192 | .pullups = BIT(1), | ||
193 | .pulldowns = BIT(2) | BIT(6) | BIT(7) | BIT(8) | BIT(13) | ||
194 | | BIT(15) | BIT(16) | BIT(17), | ||
195 | .setup = touchbook_twl_gpio_setup, | ||
196 | }; | ||
197 | |||
198 | static struct regulator_consumer_supply touchbook_vdac_supply = { | ||
199 | .supply = "vdac", | ||
200 | .dev = &omap3_touchbook_lcd_device.dev, | ||
201 | }; | ||
202 | |||
203 | static struct regulator_consumer_supply touchbook_vdvi_supply = { | ||
204 | .supply = "vdvi", | ||
205 | .dev = &omap3_touchbook_lcd_device.dev, | ||
206 | }; | ||
207 | |||
208 | /* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */ | ||
209 | static struct regulator_init_data touchbook_vmmc1 = { | ||
210 | .constraints = { | ||
211 | .min_uV = 1850000, | ||
212 | .max_uV = 3150000, | ||
213 | .valid_modes_mask = REGULATOR_MODE_NORMAL | ||
214 | | REGULATOR_MODE_STANDBY, | ||
215 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | ||
216 | | REGULATOR_CHANGE_MODE | ||
217 | | REGULATOR_CHANGE_STATUS, | ||
218 | }, | ||
219 | .num_consumer_supplies = 1, | ||
220 | .consumer_supplies = &touchbook_vmmc1_supply, | ||
221 | }; | ||
222 | |||
223 | /* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */ | ||
224 | static struct regulator_init_data touchbook_vsim = { | ||
225 | .constraints = { | ||
226 | .min_uV = 1800000, | ||
227 | .max_uV = 3000000, | ||
228 | .valid_modes_mask = REGULATOR_MODE_NORMAL | ||
229 | | REGULATOR_MODE_STANDBY, | ||
230 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | ||
231 | | REGULATOR_CHANGE_MODE | ||
232 | | REGULATOR_CHANGE_STATUS, | ||
233 | }, | ||
234 | .num_consumer_supplies = 1, | ||
235 | .consumer_supplies = &touchbook_vsim_supply, | ||
236 | }; | ||
237 | |||
238 | /* VDAC for DSS driving S-Video (8 mA unloaded, max 65 mA) */ | ||
239 | static struct regulator_init_data touchbook_vdac = { | ||
240 | .constraints = { | ||
241 | .min_uV = 1800000, | ||
242 | .max_uV = 1800000, | ||
243 | .valid_modes_mask = REGULATOR_MODE_NORMAL | ||
244 | | REGULATOR_MODE_STANDBY, | ||
245 | .valid_ops_mask = REGULATOR_CHANGE_MODE | ||
246 | | REGULATOR_CHANGE_STATUS, | ||
247 | }, | ||
248 | .num_consumer_supplies = 1, | ||
249 | .consumer_supplies = &touchbook_vdac_supply, | ||
250 | }; | ||
251 | |||
252 | /* VPLL2 for digital video outputs */ | ||
253 | static struct regulator_init_data touchbook_vpll2 = { | ||
254 | .constraints = { | ||
255 | .name = "VDVI", | ||
256 | .min_uV = 1800000, | ||
257 | .max_uV = 1800000, | ||
258 | .valid_modes_mask = REGULATOR_MODE_NORMAL | ||
259 | | REGULATOR_MODE_STANDBY, | ||
260 | .valid_ops_mask = REGULATOR_CHANGE_MODE | ||
261 | | REGULATOR_CHANGE_STATUS, | ||
262 | }, | ||
263 | .num_consumer_supplies = 1, | ||
264 | .consumer_supplies = &touchbook_vdvi_supply, | ||
265 | }; | ||
266 | |||
267 | static struct twl4030_usb_data touchbook_usb_data = { | ||
268 | .usb_mode = T2_USB_MODE_ULPI, | ||
269 | }; | ||
270 | |||
271 | static struct twl4030_codec_audio_data touchbook_audio_data = { | ||
272 | .audio_mclk = 26000000, | ||
273 | }; | ||
274 | |||
275 | static struct twl4030_codec_data touchbook_codec_data = { | ||
276 | .audio_mclk = 26000000, | ||
277 | .audio = &touchbook_audio_data, | ||
278 | }; | ||
279 | |||
280 | static struct twl4030_platform_data touchbook_twldata = { | ||
281 | .irq_base = TWL4030_IRQ_BASE, | ||
282 | .irq_end = TWL4030_IRQ_END, | ||
283 | |||
284 | /* platform_data for children goes here */ | ||
285 | .usb = &touchbook_usb_data, | ||
286 | .gpio = &touchbook_gpio_data, | ||
287 | .codec = &touchbook_codec_data, | ||
288 | .vmmc1 = &touchbook_vmmc1, | ||
289 | .vsim = &touchbook_vsim, | ||
290 | .vdac = &touchbook_vdac, | ||
291 | .vpll2 = &touchbook_vpll2, | ||
292 | }; | ||
293 | |||
294 | static struct i2c_board_info __initdata touchbook_i2c_boardinfo[] = { | ||
295 | { | ||
296 | I2C_BOARD_INFO("twl4030", 0x48), | ||
297 | .flags = I2C_CLIENT_WAKE, | ||
298 | .irq = INT_34XX_SYS_NIRQ, | ||
299 | .platform_data = &touchbook_twldata, | ||
300 | }, | ||
301 | }; | ||
302 | |||
303 | static struct i2c_board_info __initdata touchBook_i2c_boardinfo[] = { | ||
304 | { | ||
305 | I2C_BOARD_INFO("bq27200", 0x55), | ||
306 | }, | ||
307 | }; | ||
308 | |||
309 | static int __init omap3_touchbook_i2c_init(void) | ||
310 | { | ||
311 | /* Standard TouchBook bus */ | ||
312 | omap_register_i2c_bus(1, 2600, touchbook_i2c_boardinfo, | ||
313 | ARRAY_SIZE(touchbook_i2c_boardinfo)); | ||
314 | |||
315 | /* Additional TouchBook bus */ | ||
316 | omap_register_i2c_bus(3, 100, touchBook_i2c_boardinfo, | ||
317 | ARRAY_SIZE(touchBook_i2c_boardinfo)); | ||
318 | |||
319 | return 0; | ||
320 | } | ||
321 | |||
322 | static void __init omap3_ads7846_init(void) | ||
323 | { | ||
324 | if (gpio_request(OMAP3_TS_GPIO, "ads7846_pen_down")) { | ||
325 | printk(KERN_ERR "Failed to request GPIO %d for " | ||
326 | "ads7846 pen down IRQ\n", OMAP3_TS_GPIO); | ||
327 | return; | ||
328 | } | ||
329 | |||
330 | gpio_direction_input(OMAP3_TS_GPIO); | ||
331 | omap_set_gpio_debounce(OMAP3_TS_GPIO, 1); | ||
332 | omap_set_gpio_debounce_time(OMAP3_TS_GPIO, 0xa); | ||
333 | } | ||
334 | |||
335 | static struct ads7846_platform_data ads7846_config = { | ||
336 | .x_min = 100, | ||
337 | .y_min = 265, | ||
338 | .x_max = 3950, | ||
339 | .y_max = 3750, | ||
340 | .x_plate_ohms = 40, | ||
341 | .pressure_max = 255, | ||
342 | .debounce_max = 10, | ||
343 | .debounce_tol = 5, | ||
344 | .debounce_rep = 1, | ||
345 | .gpio_pendown = OMAP3_TS_GPIO, | ||
346 | .keep_vref_on = 1, | ||
347 | }; | ||
348 | |||
349 | static struct omap2_mcspi_device_config ads7846_mcspi_config = { | ||
350 | .turbo_mode = 0, | ||
351 | .single_channel = 1, /* 0: slave, 1: master */ | ||
352 | }; | ||
353 | |||
354 | static struct spi_board_info omap3_ads7846_spi_board_info[] __initdata = { | ||
355 | { | ||
356 | .modalias = "ads7846", | ||
357 | .bus_num = 4, | ||
358 | .chip_select = 0, | ||
359 | .max_speed_hz = 1500000, | ||
360 | .controller_data = &ads7846_mcspi_config, | ||
361 | .irq = OMAP_GPIO_IRQ(OMAP3_TS_GPIO), | ||
362 | .platform_data = &ads7846_config, | ||
363 | } | ||
364 | }; | ||
365 | |||
366 | static struct gpio_led gpio_leds[] = { | ||
367 | { | ||
368 | .name = "touchbook::usr0", | ||
369 | .default_trigger = "heartbeat", | ||
370 | .gpio = 150, | ||
371 | }, | ||
372 | { | ||
373 | .name = "touchbook::usr1", | ||
374 | .default_trigger = "mmc0", | ||
375 | .gpio = 149, | ||
376 | }, | ||
377 | { | ||
378 | .name = "touchbook::pmu_stat", | ||
379 | .gpio = -EINVAL, /* gets replaced */ | ||
380 | .active_low = true, | ||
381 | }, | ||
382 | }; | ||
383 | |||
384 | static struct gpio_led_platform_data gpio_led_info = { | ||
385 | .leds = gpio_leds, | ||
386 | .num_leds = ARRAY_SIZE(gpio_leds), | ||
387 | }; | ||
388 | |||
389 | static struct platform_device leds_gpio = { | ||
390 | .name = "leds-gpio", | ||
391 | .id = -1, | ||
392 | .dev = { | ||
393 | .platform_data = &gpio_led_info, | ||
394 | }, | ||
395 | }; | ||
396 | |||
397 | static struct gpio_keys_button gpio_buttons[] = { | ||
398 | { | ||
399 | .code = BTN_EXTRA, | ||
400 | .gpio = 7, | ||
401 | .desc = "user", | ||
402 | .wakeup = 1, | ||
403 | }, | ||
404 | { | ||
405 | .code = KEY_POWER, | ||
406 | .gpio = 183, | ||
407 | .desc = "power", | ||
408 | .wakeup = 1, | ||
409 | }, | ||
410 | }; | ||
411 | |||
412 | static struct gpio_keys_platform_data gpio_key_info = { | ||
413 | .buttons = gpio_buttons, | ||
414 | .nbuttons = ARRAY_SIZE(gpio_buttons), | ||
415 | }; | ||
416 | |||
417 | static struct platform_device keys_gpio = { | ||
418 | .name = "gpio-keys", | ||
419 | .id = -1, | ||
420 | .dev = { | ||
421 | .platform_data = &gpio_key_info, | ||
422 | }, | ||
423 | }; | ||
424 | |||
425 | static struct omap_board_config_kernel omap3_touchbook_config[] __initdata = { | ||
426 | { OMAP_TAG_LCD, &omap3_touchbook_lcd_config }, | ||
427 | }; | ||
428 | |||
429 | #ifdef CONFIG_OMAP_MUX | ||
430 | static struct omap_board_mux board_mux[] __initdata = { | ||
431 | { .reg_offset = OMAP_MUX_TERMINATOR }, | ||
432 | }; | ||
433 | #else | ||
434 | #define board_mux NULL | ||
435 | #endif | ||
436 | |||
437 | static void __init omap3_touchbook_init_irq(void) | ||
438 | { | ||
439 | omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); | ||
440 | omap_board_config = omap3_touchbook_config; | ||
441 | omap_board_config_size = ARRAY_SIZE(omap3_touchbook_config); | ||
442 | omap2_init_common_hw(mt46h32m32lf6_sdrc_params, | ||
443 | mt46h32m32lf6_sdrc_params); | ||
444 | omap_init_irq(); | ||
445 | #ifdef CONFIG_OMAP_32K_TIMER | ||
446 | omap2_gp_clockevent_set_gptimer(12); | ||
447 | #endif | ||
448 | omap_gpio_init(); | ||
449 | } | ||
450 | |||
451 | static struct platform_device *omap3_touchbook_devices[] __initdata = { | ||
452 | &omap3_touchbook_lcd_device, | ||
453 | &leds_gpio, | ||
454 | &keys_gpio, | ||
455 | }; | ||
456 | |||
457 | static void __init omap3touchbook_flash_init(void) | ||
458 | { | ||
459 | u8 cs = 0; | ||
460 | u8 nandcs = GPMC_CS_NUM + 1; | ||
461 | |||
462 | u32 gpmc_base_add = OMAP34XX_GPMC_VIRT; | ||
463 | |||
464 | /* find out the chip-select on which NAND exists */ | ||
465 | while (cs < GPMC_CS_NUM) { | ||
466 | u32 ret = 0; | ||
467 | ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); | ||
468 | |||
469 | if ((ret & 0xC00) == 0x800) { | ||
470 | printk(KERN_INFO "Found NAND on CS%d\n", cs); | ||
471 | if (nandcs > GPMC_CS_NUM) | ||
472 | nandcs = cs; | ||
473 | } | ||
474 | cs++; | ||
475 | } | ||
476 | |||
477 | if (nandcs > GPMC_CS_NUM) { | ||
478 | printk(KERN_INFO "NAND: Unable to find configuration " | ||
479 | "in GPMC\n "); | ||
480 | return; | ||
481 | } | ||
482 | |||
483 | if (nandcs < GPMC_CS_NUM) { | ||
484 | omap3touchbook_nand_data.cs = nandcs; | ||
485 | omap3touchbook_nand_data.gpmc_cs_baseaddr = (void *) | ||
486 | (gpmc_base_add + GPMC_CS0_BASE + nandcs * GPMC_CS_SIZE); | ||
487 | omap3touchbook_nand_data.gpmc_baseaddr = | ||
488 | (void *) (gpmc_base_add); | ||
489 | |||
490 | printk(KERN_INFO "Registering NAND on CS%d\n", nandcs); | ||
491 | if (platform_device_register(&omap3touchbook_nand_device) < 0) | ||
492 | printk(KERN_ERR "Unable to register NAND device\n"); | ||
493 | } | ||
494 | } | ||
495 | |||
496 | static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { | ||
497 | |||
498 | .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY, | ||
499 | .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY, | ||
500 | .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, | ||
501 | |||
502 | .phy_reset = true, | ||
503 | .reset_gpio_port[0] = -EINVAL, | ||
504 | .reset_gpio_port[1] = 147, | ||
505 | .reset_gpio_port[2] = -EINVAL | ||
506 | }; | ||
507 | |||
508 | static void omap3_touchbook_poweroff(void) | ||
509 | { | ||
510 | int r; | ||
511 | |||
512 | r = gpio_request(TB_KILL_POWER_GPIO, "DVI reset"); | ||
513 | if (r < 0) { | ||
514 | printk(KERN_ERR "Unable to get kill power GPIO\n"); | ||
515 | return; | ||
516 | } | ||
517 | |||
518 | gpio_direction_output(TB_KILL_POWER_GPIO, 0); | ||
519 | } | ||
520 | |||
521 | static void __init early_touchbook_revision(char **p) | ||
522 | { | ||
523 | if (!*p) | ||
524 | return; | ||
525 | |||
526 | strict_strtoul(*p, 10, &touchbook_revision); | ||
527 | } | ||
528 | __early_param("tbr=", early_touchbook_revision); | ||
529 | |||
530 | static void __init omap3_touchbook_init(void) | ||
531 | { | ||
532 | pm_power_off = omap3_touchbook_poweroff; | ||
533 | |||
534 | omap3_touchbook_i2c_init(); | ||
535 | platform_add_devices(omap3_touchbook_devices, | ||
536 | ARRAY_SIZE(omap3_touchbook_devices)); | ||
537 | omap_serial_init(); | ||
538 | |||
539 | omap_mux_init_gpio(170, OMAP_PIN_INPUT); | ||
540 | gpio_request(176, "DVI_nPD"); | ||
541 | /* REVISIT leave DVI powered down until it's needed ... */ | ||
542 | gpio_direction_output(176, true); | ||
543 | |||
544 | /* Touchscreen and accelerometer */ | ||
545 | spi_register_board_info(omap3_ads7846_spi_board_info, | ||
546 | ARRAY_SIZE(omap3_ads7846_spi_board_info)); | ||
547 | omap3_ads7846_init(); | ||
548 | usb_musb_init(); | ||
549 | usb_ehci_init(&ehci_pdata); | ||
550 | omap3touchbook_flash_init(); | ||
551 | |||
552 | /* Ensure SDRC pins are mux'd for self-refresh */ | ||
553 | omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT); | ||
554 | omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT); | ||
555 | } | ||
556 | |||
557 | static void __init omap3_touchbook_map_io(void) | ||
558 | { | ||
559 | omap2_set_globals_343x(); | ||
560 | omap2_map_common_io(); | ||
561 | } | ||
562 | |||
563 | MACHINE_START(TOUCHBOOK, "OMAP3 touchbook Board") | ||
564 | /* Maintainer: Gregoire Gentil - http://www.alwaysinnovating.com */ | ||
565 | .phys_io = 0x48000000, | ||
566 | .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, | ||
567 | .boot_params = 0x80000100, | ||
568 | .map_io = omap3_touchbook_map_io, | ||
569 | .init_irq = omap3_touchbook_init_irq, | ||
570 | .init_machine = omap3_touchbook_init, | ||
571 | .timer = &omap_timer, | ||
572 | MACHINE_END | ||
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c index 52dfd51a938e..d192dd98a591 100644 --- a/arch/arm/mach-omap2/board-overo.c +++ b/arch/arm/mach-omap2/board-overo.c | |||
@@ -26,7 +26,7 @@ | |||
26 | #include <linux/io.h> | 26 | #include <linux/io.h> |
27 | #include <linux/kernel.h> | 27 | #include <linux/kernel.h> |
28 | #include <linux/platform_device.h> | 28 | #include <linux/platform_device.h> |
29 | #include <linux/i2c/twl4030.h> | 29 | #include <linux/i2c/twl.h> |
30 | #include <linux/regulator/machine.h> | 30 | #include <linux/regulator/machine.h> |
31 | 31 | ||
32 | #include <linux/mtd/mtd.h> | 32 | #include <linux/mtd/mtd.h> |
@@ -44,9 +44,9 @@ | |||
44 | #include <plat/gpmc.h> | 44 | #include <plat/gpmc.h> |
45 | #include <mach/hardware.h> | 45 | #include <mach/hardware.h> |
46 | #include <plat/nand.h> | 46 | #include <plat/nand.h> |
47 | #include <plat/mux.h> | ||
48 | #include <plat/usb.h> | 47 | #include <plat/usb.h> |
49 | 48 | ||
49 | #include "mux.h" | ||
50 | #include "sdram-micron-mt46h32m32lf-6.h" | 50 | #include "sdram-micron-mt46h32m32lf-6.h" |
51 | #include "mmc-twl4030.h" | 51 | #include "mmc-twl4030.h" |
52 | 52 | ||
@@ -405,9 +405,17 @@ static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { | |||
405 | .reset_gpio_port[2] = -EINVAL | 405 | .reset_gpio_port[2] = -EINVAL |
406 | }; | 406 | }; |
407 | 407 | ||
408 | #ifdef CONFIG_OMAP_MUX | ||
409 | static struct omap_board_mux board_mux[] __initdata = { | ||
410 | { .reg_offset = OMAP_MUX_TERMINATOR }, | ||
411 | }; | ||
412 | #else | ||
413 | #define board_mux NULL | ||
414 | #endif | ||
408 | 415 | ||
409 | static void __init overo_init(void) | 416 | static void __init overo_init(void) |
410 | { | 417 | { |
418 | omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); | ||
411 | overo_i2c_init(); | 419 | overo_i2c_init(); |
412 | platform_add_devices(overo_devices, ARRAY_SIZE(overo_devices)); | 420 | platform_add_devices(overo_devices, ARRAY_SIZE(overo_devices)); |
413 | omap_serial_init(); | 421 | omap_serial_init(); |
@@ -418,8 +426,8 @@ static void __init overo_init(void) | |||
418 | overo_init_smsc911x(); | 426 | overo_init_smsc911x(); |
419 | 427 | ||
420 | /* Ensure SDRC pins are mux'd for self-refresh */ | 428 | /* Ensure SDRC pins are mux'd for self-refresh */ |
421 | omap_cfg_reg(H16_34XX_SDRC_CKE0); | 429 | omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT); |
422 | omap_cfg_reg(H17_34XX_SDRC_CKE1); | 430 | omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT); |
423 | 431 | ||
424 | if ((gpio_request(OVERO_GPIO_W2W_NRESET, | 432 | if ((gpio_request(OVERO_GPIO_W2W_NRESET, |
425 | "OVERO_GPIO_W2W_NRESET") == 0) && | 433 | "OVERO_GPIO_W2W_NRESET") == 0) && |
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c index 15ce6514c5fd..17f3c91231db 100644 --- a/arch/arm/mach-omap2/board-rx51-peripherals.c +++ b/arch/arm/mach-omap2/board-rx51-peripherals.c | |||
@@ -33,6 +33,7 @@ | |||
33 | #include <plat/onenand.h> | 33 | #include <plat/onenand.h> |
34 | #include <plat/gpmc-smc91x.h> | 34 | #include <plat/gpmc-smc91x.h> |
35 | 35 | ||
36 | #include "mux.h" | ||
36 | #include "mmc-twl4030.h" | 37 | #include "mmc-twl4030.h" |
37 | 38 | ||
38 | #define SYSTEM_REV_B_USES_VAUX3 0x1699 | 39 | #define SYSTEM_REV_B_USES_VAUX3 0x1699 |
@@ -59,7 +60,7 @@ static struct spi_board_info rx51_peripherals_spi_board_info[] __initdata = { | |||
59 | .bus_num = 4, | 60 | .bus_num = 4, |
60 | .chip_select = 0, | 61 | .chip_select = 0, |
61 | .max_speed_hz = 48000000, | 62 | .max_speed_hz = 48000000, |
62 | .mode = SPI_MODE_2, | 63 | .mode = SPI_MODE_3, |
63 | .controller_data = &wl1251_mcspi_config, | 64 | .controller_data = &wl1251_mcspi_config, |
64 | .platform_data = &wl1251_pdata, | 65 | .platform_data = &wl1251_pdata, |
65 | }, | 66 | }, |
@@ -401,15 +402,9 @@ static struct twl4030_usb_data rx51_usb_data = { | |||
401 | 402 | ||
402 | static struct twl4030_ins sleep_on_seq[] __initdata = { | 403 | static struct twl4030_ins sleep_on_seq[] __initdata = { |
403 | /* | 404 | /* |
404 | * Turn off VDD1 and VDD2. | 405 | * Turn off everything |
405 | */ | 406 | */ |
406 | {MSG_SINGULAR(DEV_GRP_P1, 0xf, RES_STATE_OFF), 4}, | 407 | {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, 1, 0, RES_STATE_SLEEP), 2}, |
407 | {MSG_SINGULAR(DEV_GRP_P1, 0x10, RES_STATE_OFF), 2}, | ||
408 | /* | ||
409 | * And also turn off the OMAP3 PLLs and the sysclk output. | ||
410 | */ | ||
411 | {MSG_SINGULAR(DEV_GRP_P1, 0x7, RES_STATE_OFF), 3}, | ||
412 | {MSG_SINGULAR(DEV_GRP_P1, 0x17, RES_STATE_OFF), 3}, | ||
413 | }; | 408 | }; |
414 | 409 | ||
415 | static struct twl4030_script sleep_on_script __initdata = { | 410 | static struct twl4030_script sleep_on_script __initdata = { |
@@ -420,14 +415,9 @@ static struct twl4030_script sleep_on_script __initdata = { | |||
420 | 415 | ||
421 | static struct twl4030_ins wakeup_seq[] __initdata = { | 416 | static struct twl4030_ins wakeup_seq[] __initdata = { |
422 | /* | 417 | /* |
423 | * Reenable the OMAP3 PLLs. | 418 | * Reenable everything |
424 | * Wakeup VDD1 and VDD2. | ||
425 | * Reenable sysclk output. | ||
426 | */ | 419 | */ |
427 | {MSG_SINGULAR(DEV_GRP_P1, 0x7, RES_STATE_ACTIVE), 0x30}, | 420 | {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, 1, 0, RES_STATE_ACTIVE), 2}, |
428 | {MSG_SINGULAR(DEV_GRP_P1, 0xf, RES_STATE_ACTIVE), 0x30}, | ||
429 | {MSG_SINGULAR(DEV_GRP_P1, 0x10, RES_STATE_ACTIVE), 0x37}, | ||
430 | {MSG_SINGULAR(DEV_GRP_P1, 0x19, RES_STATE_ACTIVE), 3}, | ||
431 | }; | 421 | }; |
432 | 422 | ||
433 | static struct twl4030_script wakeup_script __initdata = { | 423 | static struct twl4030_script wakeup_script __initdata = { |
@@ -438,10 +428,9 @@ static struct twl4030_script wakeup_script __initdata = { | |||
438 | 428 | ||
439 | static struct twl4030_ins wakeup_p3_seq[] __initdata = { | 429 | static struct twl4030_ins wakeup_p3_seq[] __initdata = { |
440 | /* | 430 | /* |
441 | * Wakeup VDD1 (dummy to be able to insert a delay) | 431 | * Reenable everything |
442 | * Enable CLKEN | ||
443 | */ | 432 | */ |
444 | {MSG_SINGULAR(DEV_GRP_P1, 0x17, RES_STATE_ACTIVE), 3}, | 433 | {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, 1, 0, RES_STATE_ACTIVE), 2}, |
445 | }; | 434 | }; |
446 | 435 | ||
447 | static struct twl4030_script wakeup_p3_script __initdata = { | 436 | static struct twl4030_script wakeup_p3_script __initdata = { |
@@ -462,12 +451,11 @@ static struct twl4030_ins wrst_seq[] __initdata = { | |||
462 | {MSG_SINGULAR(DEV_GRP_NULL, RES_RESET, RES_STATE_OFF), 2}, | 451 | {MSG_SINGULAR(DEV_GRP_NULL, RES_RESET, RES_STATE_OFF), 2}, |
463 | {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, 0, 1, RES_STATE_ACTIVE), | 452 | {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, 0, 1, RES_STATE_ACTIVE), |
464 | 0x13}, | 453 | 0x13}, |
465 | {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_PP, 0, 2, RES_STATE_WRST), 0x13}, | ||
466 | {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_PP, 0, 3, RES_STATE_OFF), 0x13}, | 454 | {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_PP, 0, 3, RES_STATE_OFF), 0x13}, |
467 | {MSG_SINGULAR(DEV_GRP_NULL, RES_VDD1, RES_STATE_WRST), 0x13}, | 455 | {MSG_SINGULAR(DEV_GRP_NULL, RES_VDD1, RES_STATE_WRST), 0x13}, |
468 | {MSG_SINGULAR(DEV_GRP_NULL, RES_VDD2, RES_STATE_WRST), 0x13}, | 456 | {MSG_SINGULAR(DEV_GRP_NULL, RES_VDD2, RES_STATE_WRST), 0x13}, |
469 | {MSG_SINGULAR(DEV_GRP_NULL, RES_VPLL1, RES_STATE_WRST), 0x35}, | 457 | {MSG_SINGULAR(DEV_GRP_NULL, RES_VPLL1, RES_STATE_WRST), 0x35}, |
470 | {MSG_SINGULAR(DEV_GRP_P1, RES_HFCLKOUT, RES_STATE_ACTIVE), 2}, | 458 | {MSG_SINGULAR(DEV_GRP_P3, RES_HFCLKOUT, RES_STATE_ACTIVE), 2}, |
471 | {MSG_SINGULAR(DEV_GRP_NULL, RES_RESET, RES_STATE_ACTIVE), 2}, | 459 | {MSG_SINGULAR(DEV_GRP_NULL, RES_RESET, RES_STATE_ACTIVE), 2}, |
472 | }; | 460 | }; |
473 | 461 | ||
@@ -489,22 +477,81 @@ static struct twl4030_script *twl4030_scripts[] __initdata = { | |||
489 | }; | 477 | }; |
490 | 478 | ||
491 | static struct twl4030_resconfig twl4030_rconfig[] __initdata = { | 479 | static struct twl4030_resconfig twl4030_rconfig[] __initdata = { |
492 | { .resource = RES_VINTANA1, .devgroup = -1, .type = -1, .type2 = 1 }, | 480 | { .resource = RES_VDD1, .devgroup = -1, |
493 | { .resource = RES_VINTANA2, .devgroup = -1, .type = -1, .type2 = 1 }, | 481 | .type = 1, .type2 = -1, .remap_off = RES_STATE_OFF, |
494 | { .resource = RES_VINTDIG, .devgroup = -1, .type = -1, .type2 = 1 }, | 482 | .remap_sleep = RES_STATE_OFF |
495 | { .resource = RES_VMMC1, .devgroup = -1, .type = -1, .type2 = 3}, | 483 | }, |
496 | { .resource = RES_VMMC2, .devgroup = DEV_GRP_NULL, .type = -1, | 484 | { .resource = RES_VDD2, .devgroup = -1, |
497 | .type2 = 3}, | 485 | .type = 1, .type2 = -1, .remap_off = RES_STATE_OFF, |
498 | { .resource = RES_VAUX1, .devgroup = -1, .type = -1, .type2 = 3}, | 486 | .remap_sleep = RES_STATE_OFF |
499 | { .resource = RES_VAUX2, .devgroup = -1, .type = -1, .type2 = 3}, | 487 | }, |
500 | { .resource = RES_VAUX3, .devgroup = -1, .type = -1, .type2 = 3}, | 488 | { .resource = RES_VPLL1, .devgroup = -1, |
501 | { .resource = RES_VAUX4, .devgroup = -1, .type = -1, .type2 = 3}, | 489 | .type = 1, .type2 = -1, .remap_off = RES_STATE_OFF, |
502 | { .resource = RES_VPLL2, .devgroup = -1, .type = -1, .type2 = 3}, | 490 | .remap_sleep = RES_STATE_OFF |
503 | { .resource = RES_VDAC, .devgroup = -1, .type = -1, .type2 = 3}, | 491 | }, |
504 | { .resource = RES_VSIM, .devgroup = DEV_GRP_NULL, .type = -1, | 492 | { .resource = RES_VPLL2, .devgroup = -1, |
505 | .type2 = 3}, | 493 | .type = -1, .type2 = 3, .remap_off = -1, .remap_sleep = -1 |
506 | { .resource = RES_CLKEN, .devgroup = DEV_GRP_P3, .type = -1, | 494 | }, |
507 | .type2 = 1 }, | 495 | { .resource = RES_VAUX1, .devgroup = -1, |
496 | .type = -1, .type2 = 3, .remap_off = -1, .remap_sleep = -1 | ||
497 | }, | ||
498 | { .resource = RES_VAUX2, .devgroup = -1, | ||
499 | .type = -1, .type2 = 3, .remap_off = -1, .remap_sleep = -1 | ||
500 | }, | ||
501 | { .resource = RES_VAUX3, .devgroup = -1, | ||
502 | .type = -1, .type2 = 3, .remap_off = -1, .remap_sleep = -1 | ||
503 | }, | ||
504 | { .resource = RES_VAUX4, .devgroup = -1, | ||
505 | .type = -1, .type2 = 3, .remap_off = -1, .remap_sleep = -1 | ||
506 | }, | ||
507 | { .resource = RES_VMMC1, .devgroup = -1, | ||
508 | .type = -1, .type2 = 3, .remap_off = -1, .remap_sleep = -1 | ||
509 | }, | ||
510 | { .resource = RES_VMMC2, .devgroup = -1, | ||
511 | .type = -1, .type2 = 3, .remap_off = -1, .remap_sleep = -1 | ||
512 | }, | ||
513 | { .resource = RES_VDAC, .devgroup = -1, | ||
514 | .type = -1, .type2 = 3, .remap_off = -1, .remap_sleep = -1 | ||
515 | }, | ||
516 | { .resource = RES_VSIM, .devgroup = -1, | ||
517 | .type = -1, .type2 = 3, .remap_off = -1, .remap_sleep = -1 | ||
518 | }, | ||
519 | { .resource = RES_VINTANA1, .devgroup = DEV_GRP_P1 | DEV_GRP_P3, | ||
520 | .type = -1, .type2 = -1, .remap_off = -1, .remap_sleep = -1 | ||
521 | }, | ||
522 | { .resource = RES_VINTANA2, .devgroup = DEV_GRP_P1 | DEV_GRP_P3, | ||
523 | .type = 1, .type2 = -1, .remap_off = -1, .remap_sleep = -1 | ||
524 | }, | ||
525 | { .resource = RES_VINTDIG, .devgroup = DEV_GRP_P1 | DEV_GRP_P3, | ||
526 | .type = -1, .type2 = -1, .remap_off = -1, .remap_sleep = -1 | ||
527 | }, | ||
528 | { .resource = RES_VIO, .devgroup = DEV_GRP_P3, | ||
529 | .type = 1, .type2 = -1, .remap_off = -1, .remap_sleep = -1 | ||
530 | }, | ||
531 | { .resource = RES_CLKEN, .devgroup = DEV_GRP_P1 | DEV_GRP_P3, | ||
532 | .type = 1, .type2 = -1 , .remap_off = -1, .remap_sleep = -1 | ||
533 | }, | ||
534 | { .resource = RES_REGEN, .devgroup = DEV_GRP_P1 | DEV_GRP_P3, | ||
535 | .type = 1, .type2 = -1, .remap_off = -1, .remap_sleep = -1 | ||
536 | }, | ||
537 | { .resource = RES_NRES_PWRON, .devgroup = DEV_GRP_P1 | DEV_GRP_P3, | ||
538 | .type = 1, .type2 = -1, .remap_off = -1, .remap_sleep = -1 | ||
539 | }, | ||
540 | { .resource = RES_SYSEN, .devgroup = DEV_GRP_P1 | DEV_GRP_P3, | ||
541 | .type = 1, .type2 = -1, .remap_off = -1, .remap_sleep = -1 | ||
542 | }, | ||
543 | { .resource = RES_HFCLKOUT, .devgroup = DEV_GRP_P3, | ||
544 | .type = 1, .type2 = -1, .remap_off = -1, .remap_sleep = -1 | ||
545 | }, | ||
546 | { .resource = RES_32KCLKOUT, .devgroup = -1, | ||
547 | .type = 1, .type2 = -1, .remap_off = -1, .remap_sleep = -1 | ||
548 | }, | ||
549 | { .resource = RES_RESET, .devgroup = -1, | ||
550 | .type = 1, .type2 = -1, .remap_off = -1, .remap_sleep = -1 | ||
551 | }, | ||
552 | { .resource = RES_Main_Ref, .devgroup = -1, | ||
553 | .type = 1, .type2 = -1, .remap_off = -1, .remap_sleep = -1 | ||
554 | }, | ||
508 | { 0, 0}, | 555 | { 0, 0}, |
509 | }; | 556 | }; |
510 | 557 | ||
@@ -630,9 +677,9 @@ static struct omap_smc91x_platform_data board_smc91x_data = { | |||
630 | 677 | ||
631 | static void __init board_smc91x_init(void) | 678 | static void __init board_smc91x_init(void) |
632 | { | 679 | { |
633 | omap_cfg_reg(U8_34XX_GPIO54_DOWN); | 680 | omap_mux_init_gpio(54, OMAP_PIN_INPUT_PULLDOWN); |
634 | omap_cfg_reg(G25_34XX_GPIO86_OUT); | 681 | omap_mux_init_gpio(86, OMAP_PIN_OUTPUT); |
635 | omap_cfg_reg(H19_34XX_GPIO164_OUT); | 682 | omap_mux_init_gpio(164, OMAP_PIN_OUTPUT); |
636 | 683 | ||
637 | gpmc_smc91x_init(&board_smc91x_data); | 684 | gpmc_smc91x_init(&board_smc91x_data); |
638 | } | 685 | } |
diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c index 1bb1de245917..67bb3476b707 100644 --- a/arch/arm/mach-omap2/board-rx51.c +++ b/arch/arm/mach-omap2/board-rx51.c | |||
@@ -23,13 +23,14 @@ | |||
23 | #include <asm/mach/map.h> | 23 | #include <asm/mach/map.h> |
24 | 24 | ||
25 | #include <plat/mcspi.h> | 25 | #include <plat/mcspi.h> |
26 | #include <plat/mux.h> | ||
27 | #include <plat/board.h> | 26 | #include <plat/board.h> |
28 | #include <plat/common.h> | 27 | #include <plat/common.h> |
29 | #include <plat/dma.h> | 28 | #include <plat/dma.h> |
30 | #include <plat/gpmc.h> | 29 | #include <plat/gpmc.h> |
31 | #include <plat/usb.h> | 30 | #include <plat/usb.h> |
32 | 31 | ||
32 | #include "mux.h" | ||
33 | |||
33 | struct omap_sdrc_params *rx51_get_sdram_timings(void); | 34 | struct omap_sdrc_params *rx51_get_sdram_timings(void); |
34 | 35 | ||
35 | static struct omap_lcd_config rx51_lcd_config = { | 36 | static struct omap_lcd_config rx51_lcd_config = { |
@@ -69,15 +70,24 @@ static void __init rx51_init_irq(void) | |||
69 | 70 | ||
70 | extern void __init rx51_peripherals_init(void); | 71 | extern void __init rx51_peripherals_init(void); |
71 | 72 | ||
73 | #ifdef CONFIG_OMAP_MUX | ||
74 | static struct omap_board_mux board_mux[] __initdata = { | ||
75 | { .reg_offset = OMAP_MUX_TERMINATOR }, | ||
76 | }; | ||
77 | #else | ||
78 | #define board_mux NULL | ||
79 | #endif | ||
80 | |||
72 | static void __init rx51_init(void) | 81 | static void __init rx51_init(void) |
73 | { | 82 | { |
83 | omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); | ||
74 | omap_serial_init(); | 84 | omap_serial_init(); |
75 | usb_musb_init(); | 85 | usb_musb_init(); |
76 | rx51_peripherals_init(); | 86 | rx51_peripherals_init(); |
77 | 87 | ||
78 | /* Ensure SDRC pins are mux'd for self-refresh */ | 88 | /* Ensure SDRC pins are mux'd for self-refresh */ |
79 | omap_cfg_reg(H16_34XX_SDRC_CKE0); | 89 | omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT); |
80 | omap_cfg_reg(H17_34XX_SDRC_CKE1); | 90 | omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT); |
81 | } | 91 | } |
82 | 92 | ||
83 | static void __init rx51_map_io(void) | 93 | static void __init rx51_map_io(void) |
diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c index f14baa392760..258794db488f 100755 --- a/arch/arm/mach-omap2/board-zoom-peripherals.c +++ b/arch/arm/mach-omap2/board-zoom-peripherals.c | |||
@@ -152,14 +152,20 @@ static struct regulator_init_data zoom_vsim = { | |||
152 | 152 | ||
153 | static struct twl4030_hsmmc_info mmc[] __initdata = { | 153 | static struct twl4030_hsmmc_info mmc[] __initdata = { |
154 | { | 154 | { |
155 | .name = "external", | ||
155 | .mmc = 1, | 156 | .mmc = 1, |
156 | .wires = 4, | 157 | .wires = 4, |
157 | .gpio_wp = -EINVAL, | 158 | .gpio_wp = -EINVAL, |
159 | .power_saving = true, | ||
158 | }, | 160 | }, |
159 | { | 161 | { |
162 | .name = "internal", | ||
160 | .mmc = 2, | 163 | .mmc = 2, |
161 | .wires = 4, | 164 | .wires = 8, |
165 | .gpio_cd = -EINVAL, | ||
162 | .gpio_wp = -EINVAL, | 166 | .gpio_wp = -EINVAL, |
167 | .nonremovable = true, | ||
168 | .power_saving = true, | ||
163 | }, | 169 | }, |
164 | {} /* Terminator */ | 170 | {} /* Terminator */ |
165 | }; | 171 | }; |
@@ -167,11 +173,8 @@ static struct twl4030_hsmmc_info mmc[] __initdata = { | |||
167 | static int zoom_twl_gpio_setup(struct device *dev, | 173 | static int zoom_twl_gpio_setup(struct device *dev, |
168 | unsigned gpio, unsigned ngpio) | 174 | unsigned gpio, unsigned ngpio) |
169 | { | 175 | { |
170 | /* gpio + 0 is "mmc0_cd" (input/IRQ), | 176 | /* gpio + 0 is "mmc0_cd" (input/IRQ) */ |
171 | * gpio + 1 is "mmc1_cd" (input/IRQ) | ||
172 | */ | ||
173 | mmc[0].gpio_cd = gpio + 0; | 177 | mmc[0].gpio_cd = gpio + 0; |
174 | mmc[1].gpio_cd = gpio + 1; | ||
175 | twl4030_mmc_init(mmc); | 178 | twl4030_mmc_init(mmc); |
176 | 179 | ||
177 | /* link regulators to MMC adapters ... we "know" the | 180 | /* link regulators to MMC adapters ... we "know" the |
@@ -236,6 +239,7 @@ static struct twl4030_platform_data zoom_twldata = { | |||
236 | .gpio = &zoom_gpio_data, | 239 | .gpio = &zoom_gpio_data, |
237 | .keypad = &zoom_kp_twl4030_data, | 240 | .keypad = &zoom_kp_twl4030_data, |
238 | .codec = &zoom_codec_data, | 241 | .codec = &zoom_codec_data, |
242 | .vmmc1 = &zoom_vmmc1, | ||
239 | .vmmc2 = &zoom_vmmc2, | 243 | .vmmc2 = &zoom_vmmc2, |
240 | .vsim = &zoom_vsim, | 244 | .vsim = &zoom_vsim, |
241 | 245 | ||
diff --git a/arch/arm/mach-omap2/board-zoom2.c b/arch/arm/mach-omap2/board-zoom2.c index d94d047c7dce..bb87cf7878ff 100644 --- a/arch/arm/mach-omap2/board-zoom2.c +++ b/arch/arm/mach-omap2/board-zoom2.c | |||
@@ -23,6 +23,7 @@ | |||
23 | 23 | ||
24 | #include <mach/board-zoom.h> | 24 | #include <mach/board-zoom.h> |
25 | 25 | ||
26 | #include "mux.h" | ||
26 | #include "sdram-micron-mt46h32m32lf-6.h" | 27 | #include "sdram-micron-mt46h32m32lf-6.h" |
27 | 28 | ||
28 | static void __init omap_zoom2_init_irq(void) | 29 | static void __init omap_zoom2_init_irq(void) |
@@ -68,8 +69,17 @@ static struct twl4030_platform_data zoom2_twldata = { | |||
68 | 69 | ||
69 | #endif | 70 | #endif |
70 | 71 | ||
72 | #ifdef CONFIG_OMAP_MUX | ||
73 | static struct omap_board_mux board_mux[] __initdata = { | ||
74 | { .reg_offset = OMAP_MUX_TERMINATOR }, | ||
75 | }; | ||
76 | #else | ||
77 | #define board_mux NULL | ||
78 | #endif | ||
79 | |||
71 | static void __init omap_zoom2_init(void) | 80 | static void __init omap_zoom2_init(void) |
72 | { | 81 | { |
82 | omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); | ||
73 | zoom_peripherals_init(); | 83 | zoom_peripherals_init(); |
74 | zoom_debugboard_init(); | 84 | zoom_debugboard_init(); |
75 | } | 85 | } |
diff --git a/arch/arm/mach-omap2/board-zoom3.c b/arch/arm/mach-omap2/board-zoom3.c index 8d965a6516c8..a9fe9181b010 100644 --- a/arch/arm/mach-omap2/board-zoom3.c +++ b/arch/arm/mach-omap2/board-zoom3.c | |||
@@ -21,6 +21,7 @@ | |||
21 | #include <plat/common.h> | 21 | #include <plat/common.h> |
22 | #include <plat/board.h> | 22 | #include <plat/board.h> |
23 | 23 | ||
24 | #include "mux.h" | ||
24 | #include "sdram-hynix-h8mbx00u0mer-0em.h" | 25 | #include "sdram-hynix-h8mbx00u0mer-0em.h" |
25 | 26 | ||
26 | static void __init omap_zoom_map_io(void) | 27 | static void __init omap_zoom_map_io(void) |
@@ -42,8 +43,17 @@ static void __init omap_zoom_init_irq(void) | |||
42 | omap_gpio_init(); | 43 | omap_gpio_init(); |
43 | } | 44 | } |
44 | 45 | ||
46 | #ifdef CONFIG_OMAP_MUX | ||
47 | static struct omap_board_mux board_mux[] __initdata = { | ||
48 | { .reg_offset = OMAP_MUX_TERMINATOR }, | ||
49 | }; | ||
50 | #else | ||
51 | #define board_mux NULL | ||
52 | #endif | ||
53 | |||
45 | static void __init omap_zoom_init(void) | 54 | static void __init omap_zoom_init(void) |
46 | { | 55 | { |
56 | omap3_mux_init(board_mux, OMAP_PACKAGE_CBP); | ||
47 | zoom_peripherals_init(); | 57 | zoom_peripherals_init(); |
48 | zoom_debugboard_init(); | 58 | zoom_debugboard_init(); |
49 | } | 59 | } |
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 4716206547ac..759c72a48f7f 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c | |||
@@ -70,9 +70,41 @@ | |||
70 | u8 cpu_mask; | 70 | u8 cpu_mask; |
71 | 71 | ||
72 | /*------------------------------------------------------------------------- | 72 | /*------------------------------------------------------------------------- |
73 | * OMAP2/3 specific clock functions | 73 | * OMAP2/3/4 specific clock functions |
74 | *-------------------------------------------------------------------------*/ | 74 | *-------------------------------------------------------------------------*/ |
75 | 75 | ||
76 | void omap2_init_dpll_parent(struct clk *clk) | ||
77 | { | ||
78 | u32 v; | ||
79 | struct dpll_data *dd; | ||
80 | |||
81 | dd = clk->dpll_data; | ||
82 | if (!dd) | ||
83 | return; | ||
84 | |||
85 | /* Return bypass rate if DPLL is bypassed */ | ||
86 | v = __raw_readl(dd->control_reg); | ||
87 | v &= dd->enable_mask; | ||
88 | v >>= __ffs(dd->enable_mask); | ||
89 | |||
90 | /* Reparent in case the dpll is in bypass */ | ||
91 | if (cpu_is_omap24xx()) { | ||
92 | if (v == OMAP2XXX_EN_DPLL_LPBYPASS || | ||
93 | v == OMAP2XXX_EN_DPLL_FRBYPASS) | ||
94 | clk_reparent(clk, dd->clk_bypass); | ||
95 | } else if (cpu_is_omap34xx()) { | ||
96 | if (v == OMAP3XXX_EN_DPLL_LPBYPASS || | ||
97 | v == OMAP3XXX_EN_DPLL_FRBYPASS) | ||
98 | clk_reparent(clk, dd->clk_bypass); | ||
99 | } else if (cpu_is_omap44xx()) { | ||
100 | if (v == OMAP4XXX_EN_DPLL_LPBYPASS || | ||
101 | v == OMAP4XXX_EN_DPLL_FRBYPASS || | ||
102 | v == OMAP4XXX_EN_DPLL_MNBYPASS) | ||
103 | clk_reparent(clk, dd->clk_bypass); | ||
104 | } | ||
105 | return; | ||
106 | } | ||
107 | |||
76 | /** | 108 | /** |
77 | * _omap2xxx_clk_commit - commit clock parent/rate changes in hardware | 109 | * _omap2xxx_clk_commit - commit clock parent/rate changes in hardware |
78 | * @clk: struct clk * | 110 | * @clk: struct clk * |
@@ -149,6 +181,7 @@ static int _dpll_test_fint(struct clk *clk, u8 n) | |||
149 | * clockdomain pointer, and save it into the struct clk. Intended to be | 181 | * clockdomain pointer, and save it into the struct clk. Intended to be |
150 | * called during clk_register(). No return value. | 182 | * called during clk_register(). No return value. |
151 | */ | 183 | */ |
184 | #ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdm f/w is in place */ | ||
152 | void omap2_init_clk_clkdm(struct clk *clk) | 185 | void omap2_init_clk_clkdm(struct clk *clk) |
153 | { | 186 | { |
154 | struct clockdomain *clkdm; | 187 | struct clockdomain *clkdm; |
@@ -166,6 +199,7 @@ void omap2_init_clk_clkdm(struct clk *clk) | |||
166 | "clkdm %s\n", clk->name, clk->clkdm_name); | 199 | "clkdm %s\n", clk->name, clk->clkdm_name); |
167 | } | 200 | } |
168 | } | 201 | } |
202 | #endif | ||
169 | 203 | ||
170 | /** | 204 | /** |
171 | * omap2_init_clksel_parent - set a clksel clk's parent field from the hardware | 205 | * omap2_init_clksel_parent - set a clksel clk's parent field from the hardware |
@@ -247,6 +281,11 @@ u32 omap2_get_dpll_rate(struct clk *clk) | |||
247 | if (v == OMAP3XXX_EN_DPLL_LPBYPASS || | 281 | if (v == OMAP3XXX_EN_DPLL_LPBYPASS || |
248 | v == OMAP3XXX_EN_DPLL_FRBYPASS) | 282 | v == OMAP3XXX_EN_DPLL_FRBYPASS) |
249 | return dd->clk_bypass->rate; | 283 | return dd->clk_bypass->rate; |
284 | } else if (cpu_is_omap44xx()) { | ||
285 | if (v == OMAP4XXX_EN_DPLL_LPBYPASS || | ||
286 | v == OMAP4XXX_EN_DPLL_FRBYPASS || | ||
287 | v == OMAP4XXX_EN_DPLL_MNBYPASS) | ||
288 | return dd->clk_bypass->rate; | ||
250 | } | 289 | } |
251 | 290 | ||
252 | v = __raw_readl(dd->mult_div1_reg); | 291 | v = __raw_readl(dd->mult_div1_reg); |
@@ -437,8 +476,10 @@ void omap2_clk_disable(struct clk *clk) | |||
437 | _omap2_clk_disable(clk); | 476 | _omap2_clk_disable(clk); |
438 | if (clk->parent) | 477 | if (clk->parent) |
439 | omap2_clk_disable(clk->parent); | 478 | omap2_clk_disable(clk->parent); |
479 | #ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdm f/w is in place */ | ||
440 | if (clk->clkdm) | 480 | if (clk->clkdm) |
441 | omap2_clkdm_clk_disable(clk->clkdm, clk); | 481 | omap2_clkdm_clk_disable(clk->clkdm, clk); |
482 | #endif | ||
442 | 483 | ||
443 | } | 484 | } |
444 | } | 485 | } |
@@ -448,8 +489,10 @@ int omap2_clk_enable(struct clk *clk) | |||
448 | int ret = 0; | 489 | int ret = 0; |
449 | 490 | ||
450 | if (clk->usecount++ == 0) { | 491 | if (clk->usecount++ == 0) { |
492 | #ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdm f/w is in place */ | ||
451 | if (clk->clkdm) | 493 | if (clk->clkdm) |
452 | omap2_clkdm_clk_enable(clk->clkdm, clk); | 494 | omap2_clkdm_clk_enable(clk->clkdm, clk); |
495 | #endif | ||
453 | 496 | ||
454 | if (clk->parent) { | 497 | if (clk->parent) { |
455 | ret = omap2_clk_enable(clk->parent); | 498 | ret = omap2_clk_enable(clk->parent); |
@@ -468,8 +511,10 @@ int omap2_clk_enable(struct clk *clk) | |||
468 | return ret; | 511 | return ret; |
469 | 512 | ||
470 | err: | 513 | err: |
514 | #ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdm f/w is in place */ | ||
471 | if (clk->clkdm) | 515 | if (clk->clkdm) |
472 | omap2_clkdm_clk_disable(clk->clkdm, clk); | 516 | omap2_clkdm_clk_disable(clk->clkdm, clk); |
517 | #endif | ||
473 | clk->usecount--; | 518 | clk->usecount--; |
474 | return ret; | 519 | return ret; |
475 | } | 520 | } |
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index 43b6bedaafd6..93c48df3b5b1 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h | |||
@@ -1,8 +1,8 @@ | |||
1 | /* | 1 | /* |
2 | * linux/arch/arm/mach-omap2/clock.h | 2 | * linux/arch/arm/mach-omap2/clock.h |
3 | * | 3 | * |
4 | * Copyright (C) 2005-2008 Texas Instruments, Inc. | 4 | * Copyright (C) 2005-2009 Texas Instruments, Inc. |
5 | * Copyright (C) 2004-2008 Nokia Corporation | 5 | * Copyright (C) 2004-2009 Nokia Corporation |
6 | * | 6 | * |
7 | * Contacts: | 7 | * Contacts: |
8 | * Richard Woodruff <r-woodruff2@ti.com> | 8 | * Richard Woodruff <r-woodruff2@ti.com> |
@@ -36,6 +36,17 @@ | |||
36 | #define OMAP3XXX_EN_DPLL_FRBYPASS 0x6 | 36 | #define OMAP3XXX_EN_DPLL_FRBYPASS 0x6 |
37 | #define OMAP3XXX_EN_DPLL_LOCKED 0x7 | 37 | #define OMAP3XXX_EN_DPLL_LOCKED 0x7 |
38 | 38 | ||
39 | /* OMAP4xxx CM_CLKMODE_DPLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */ | ||
40 | #define OMAP4XXX_EN_DPLL_MNBYPASS 0x4 | ||
41 | #define OMAP4XXX_EN_DPLL_LPBYPASS 0x5 | ||
42 | #define OMAP4XXX_EN_DPLL_FRBYPASS 0x6 | ||
43 | #define OMAP4XXX_EN_DPLL_LOCKED 0x7 | ||
44 | |||
45 | /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */ | ||
46 | #define DPLL_LOW_POWER_STOP 0x1 | ||
47 | #define DPLL_LOW_POWER_BYPASS 0x5 | ||
48 | #define DPLL_LOCKED 0x7 | ||
49 | |||
39 | int omap2_clk_init(void); | 50 | int omap2_clk_init(void); |
40 | int omap2_clk_enable(struct clk *clk); | 51 | int omap2_clk_enable(struct clk *clk); |
41 | void omap2_clk_disable(struct clk *clk); | 52 | void omap2_clk_disable(struct clk *clk); |
@@ -44,6 +55,14 @@ int omap2_clk_set_rate(struct clk *clk, unsigned long rate); | |||
44 | int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent); | 55 | int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent); |
45 | int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance); | 56 | int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance); |
46 | long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate); | 57 | long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate); |
58 | unsigned long omap3_dpll_recalc(struct clk *clk); | ||
59 | unsigned long omap3_clkoutx2_recalc(struct clk *clk); | ||
60 | void omap3_dpll_allow_idle(struct clk *clk); | ||
61 | void omap3_dpll_deny_idle(struct clk *clk); | ||
62 | u32 omap3_dpll_autoidle_read(struct clk *clk); | ||
63 | int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate); | ||
64 | int omap3_noncore_dpll_enable(struct clk *clk); | ||
65 | void omap3_noncore_dpll_disable(struct clk *clk); | ||
47 | 66 | ||
48 | #ifdef CONFIG_OMAP_RESET_CLOCKS | 67 | #ifdef CONFIG_OMAP_RESET_CLOCKS |
49 | void omap2_clk_disable_unused(struct clk *clk); | 68 | void omap2_clk_disable_unused(struct clk *clk); |
@@ -63,6 +82,7 @@ unsigned long omap2_fixed_divisor_recalc(struct clk *clk); | |||
63 | long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate); | 82 | long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate); |
64 | int omap2_clksel_set_rate(struct clk *clk, unsigned long rate); | 83 | int omap2_clksel_set_rate(struct clk *clk, unsigned long rate); |
65 | u32 omap2_get_dpll_rate(struct clk *clk); | 84 | u32 omap2_get_dpll_rate(struct clk *clk); |
85 | void omap2_init_dpll_parent(struct clk *clk); | ||
66 | int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name); | 86 | int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name); |
67 | void omap2_clk_prepare_for_reboot(void); | 87 | void omap2_clk_prepare_for_reboot(void); |
68 | int omap2_dflt_clk_enable(struct clk *clk); | 88 | int omap2_dflt_clk_enable(struct clk *clk); |
@@ -72,29 +92,17 @@ void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg, | |||
72 | void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg, | 92 | void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg, |
73 | u8 *idlest_bit); | 93 | u8 *idlest_bit); |
74 | 94 | ||
95 | extern u8 cpu_mask; | ||
96 | |||
75 | extern const struct clkops clkops_omap2_dflt_wait; | 97 | extern const struct clkops clkops_omap2_dflt_wait; |
76 | extern const struct clkops clkops_omap2_dflt; | 98 | extern const struct clkops clkops_omap2_dflt; |
77 | 99 | ||
78 | extern u8 cpu_mask; | 100 | extern struct clk_functions omap2_clk_functions; |
101 | extern struct clk *vclk, *sclk; | ||
79 | 102 | ||
80 | /* clksel_rate data common to 24xx/343x */ | 103 | extern const struct clksel_rate gpt_32k_rates[]; |
81 | static const struct clksel_rate gpt_32k_rates[] = { | 104 | extern const struct clksel_rate gpt_sys_rates[]; |
82 | { .div = 1, .val = 0, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE }, | 105 | extern const struct clksel_rate gfx_l3_rates[]; |
83 | { .div = 0 } | ||
84 | }; | ||
85 | |||
86 | static const struct clksel_rate gpt_sys_rates[] = { | ||
87 | { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE }, | ||
88 | { .div = 0 } | ||
89 | }; | ||
90 | |||
91 | static const struct clksel_rate gfx_l3_rates[] = { | ||
92 | { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_343X }, | ||
93 | { .div = 2, .val = 2, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE }, | ||
94 | { .div = 3, .val = 3, .flags = RATE_IN_243X | RATE_IN_343X }, | ||
95 | { .div = 4, .val = 4, .flags = RATE_IN_243X | RATE_IN_343X }, | ||
96 | { .div = 0 } | ||
97 | }; | ||
98 | 106 | ||
99 | 107 | ||
100 | #endif | 108 | #endif |
diff --git a/arch/arm/mach-omap2/clock24xx.c b/arch/arm/mach-omap2/clock24xx.c deleted file mode 100644 index 845b478ebeee..000000000000 --- a/arch/arm/mach-omap2/clock24xx.c +++ /dev/null | |||
@@ -1,805 +0,0 @@ | |||
1 | /* | ||
2 | * linux/arch/arm/mach-omap2/clock.c | ||
3 | * | ||
4 | * Copyright (C) 2005-2008 Texas Instruments, Inc. | ||
5 | * Copyright (C) 2004-2008 Nokia Corporation | ||
6 | * | ||
7 | * Contacts: | ||
8 | * Richard Woodruff <r-woodruff2@ti.com> | ||
9 | * Paul Walmsley | ||
10 | * | ||
11 | * Based on earlier work by Tuukka Tikkanen, Tony Lindgren, | ||
12 | * Gordon McNutt and RidgeRun, Inc. | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or modify | ||
15 | * it under the terms of the GNU General Public License version 2 as | ||
16 | * published by the Free Software Foundation. | ||
17 | */ | ||
18 | #undef DEBUG | ||
19 | |||
20 | #include <linux/module.h> | ||
21 | #include <linux/kernel.h> | ||
22 | #include <linux/device.h> | ||
23 | #include <linux/list.h> | ||
24 | #include <linux/errno.h> | ||
25 | #include <linux/delay.h> | ||
26 | #include <linux/clk.h> | ||
27 | #include <linux/io.h> | ||
28 | #include <linux/cpufreq.h> | ||
29 | #include <linux/bitops.h> | ||
30 | |||
31 | #include <plat/clock.h> | ||
32 | #include <plat/sram.h> | ||
33 | #include <plat/prcm.h> | ||
34 | #include <asm/div64.h> | ||
35 | #include <asm/clkdev.h> | ||
36 | |||
37 | #include <plat/sdrc.h> | ||
38 | #include "clock.h" | ||
39 | #include "prm.h" | ||
40 | #include "prm-regbits-24xx.h" | ||
41 | #include "cm.h" | ||
42 | #include "cm-regbits-24xx.h" | ||
43 | |||
44 | static const struct clkops clkops_oscck; | ||
45 | static const struct clkops clkops_fixed; | ||
46 | |||
47 | static void omap2430_clk_i2chs_find_idlest(struct clk *clk, | ||
48 | void __iomem **idlest_reg, | ||
49 | u8 *idlest_bit); | ||
50 | |||
51 | /* 2430 I2CHS has non-standard IDLEST register */ | ||
52 | static const struct clkops clkops_omap2430_i2chs_wait = { | ||
53 | .enable = omap2_dflt_clk_enable, | ||
54 | .disable = omap2_dflt_clk_disable, | ||
55 | .find_idlest = omap2430_clk_i2chs_find_idlest, | ||
56 | .find_companion = omap2_clk_dflt_find_companion, | ||
57 | }; | ||
58 | |||
59 | #include "clock24xx.h" | ||
60 | |||
61 | struct omap_clk { | ||
62 | u32 cpu; | ||
63 | struct clk_lookup lk; | ||
64 | }; | ||
65 | |||
66 | #define CLK(dev, con, ck, cp) \ | ||
67 | { \ | ||
68 | .cpu = cp, \ | ||
69 | .lk = { \ | ||
70 | .dev_id = dev, \ | ||
71 | .con_id = con, \ | ||
72 | .clk = ck, \ | ||
73 | }, \ | ||
74 | } | ||
75 | |||
76 | #define CK_243X RATE_IN_243X | ||
77 | #define CK_242X RATE_IN_242X | ||
78 | |||
79 | static struct omap_clk omap24xx_clks[] = { | ||
80 | /* external root sources */ | ||
81 | CLK(NULL, "func_32k_ck", &func_32k_ck, CK_243X | CK_242X), | ||
82 | CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_243X | CK_242X), | ||
83 | CLK(NULL, "osc_ck", &osc_ck, CK_243X | CK_242X), | ||
84 | CLK(NULL, "sys_ck", &sys_ck, CK_243X | CK_242X), | ||
85 | CLK(NULL, "alt_ck", &alt_ck, CK_243X | CK_242X), | ||
86 | /* internal analog sources */ | ||
87 | CLK(NULL, "dpll_ck", &dpll_ck, CK_243X | CK_242X), | ||
88 | CLK(NULL, "apll96_ck", &apll96_ck, CK_243X | CK_242X), | ||
89 | CLK(NULL, "apll54_ck", &apll54_ck, CK_243X | CK_242X), | ||
90 | /* internal prcm root sources */ | ||
91 | CLK(NULL, "func_54m_ck", &func_54m_ck, CK_243X | CK_242X), | ||
92 | CLK(NULL, "core_ck", &core_ck, CK_243X | CK_242X), | ||
93 | CLK(NULL, "func_96m_ck", &func_96m_ck, CK_243X | CK_242X), | ||
94 | CLK(NULL, "func_48m_ck", &func_48m_ck, CK_243X | CK_242X), | ||
95 | CLK(NULL, "func_12m_ck", &func_12m_ck, CK_243X | CK_242X), | ||
96 | CLK(NULL, "ck_wdt1_osc", &wdt1_osc_ck, CK_243X | CK_242X), | ||
97 | CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_243X | CK_242X), | ||
98 | CLK(NULL, "sys_clkout", &sys_clkout, CK_243X | CK_242X), | ||
99 | CLK(NULL, "sys_clkout2_src", &sys_clkout2_src, CK_242X), | ||
100 | CLK(NULL, "sys_clkout2", &sys_clkout2, CK_242X), | ||
101 | CLK(NULL, "emul_ck", &emul_ck, CK_242X), | ||
102 | /* mpu domain clocks */ | ||
103 | CLK(NULL, "mpu_ck", &mpu_ck, CK_243X | CK_242X), | ||
104 | /* dsp domain clocks */ | ||
105 | CLK(NULL, "dsp_fck", &dsp_fck, CK_243X | CK_242X), | ||
106 | CLK(NULL, "dsp_irate_ick", &dsp_irate_ick, CK_243X | CK_242X), | ||
107 | CLK(NULL, "dsp_ick", &dsp_ick, CK_242X), | ||
108 | CLK(NULL, "iva2_1_ick", &iva2_1_ick, CK_243X), | ||
109 | CLK(NULL, "iva1_ifck", &iva1_ifck, CK_242X), | ||
110 | CLK(NULL, "iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X), | ||
111 | /* GFX domain clocks */ | ||
112 | CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_243X | CK_242X), | ||
113 | CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_243X | CK_242X), | ||
114 | CLK(NULL, "gfx_ick", &gfx_ick, CK_243X | CK_242X), | ||
115 | /* Modem domain clocks */ | ||
116 | CLK(NULL, "mdm_ick", &mdm_ick, CK_243X), | ||
117 | CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X), | ||
118 | /* DSS domain clocks */ | ||
119 | CLK("omapdss", "ick", &dss_ick, CK_243X | CK_242X), | ||
120 | CLK("omapdss", "dss1_fck", &dss1_fck, CK_243X | CK_242X), | ||
121 | CLK("omapdss", "dss2_fck", &dss2_fck, CK_243X | CK_242X), | ||
122 | CLK("omapdss", "tv_fck", &dss_54m_fck, CK_243X | CK_242X), | ||
123 | /* L3 domain clocks */ | ||
124 | CLK(NULL, "core_l3_ck", &core_l3_ck, CK_243X | CK_242X), | ||
125 | CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_243X | CK_242X), | ||
126 | CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_243X | CK_242X), | ||
127 | /* L4 domain clocks */ | ||
128 | CLK(NULL, "l4_ck", &l4_ck, CK_243X | CK_242X), | ||
129 | CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_243X | CK_242X), | ||
130 | /* virtual meta-group clock */ | ||
131 | CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_243X | CK_242X), | ||
132 | /* general l4 interface ck, multi-parent functional clk */ | ||
133 | CLK(NULL, "gpt1_ick", &gpt1_ick, CK_243X | CK_242X), | ||
134 | CLK(NULL, "gpt1_fck", &gpt1_fck, CK_243X | CK_242X), | ||
135 | CLK(NULL, "gpt2_ick", &gpt2_ick, CK_243X | CK_242X), | ||
136 | CLK(NULL, "gpt2_fck", &gpt2_fck, CK_243X | CK_242X), | ||
137 | CLK(NULL, "gpt3_ick", &gpt3_ick, CK_243X | CK_242X), | ||
138 | CLK(NULL, "gpt3_fck", &gpt3_fck, CK_243X | CK_242X), | ||
139 | CLK(NULL, "gpt4_ick", &gpt4_ick, CK_243X | CK_242X), | ||
140 | CLK(NULL, "gpt4_fck", &gpt4_fck, CK_243X | CK_242X), | ||
141 | CLK(NULL, "gpt5_ick", &gpt5_ick, CK_243X | CK_242X), | ||
142 | CLK(NULL, "gpt5_fck", &gpt5_fck, CK_243X | CK_242X), | ||
143 | CLK(NULL, "gpt6_ick", &gpt6_ick, CK_243X | CK_242X), | ||
144 | CLK(NULL, "gpt6_fck", &gpt6_fck, CK_243X | CK_242X), | ||
145 | CLK(NULL, "gpt7_ick", &gpt7_ick, CK_243X | CK_242X), | ||
146 | CLK(NULL, "gpt7_fck", &gpt7_fck, CK_243X | CK_242X), | ||
147 | CLK(NULL, "gpt8_ick", &gpt8_ick, CK_243X | CK_242X), | ||
148 | CLK(NULL, "gpt8_fck", &gpt8_fck, CK_243X | CK_242X), | ||
149 | CLK(NULL, "gpt9_ick", &gpt9_ick, CK_243X | CK_242X), | ||
150 | CLK(NULL, "gpt9_fck", &gpt9_fck, CK_243X | CK_242X), | ||
151 | CLK(NULL, "gpt10_ick", &gpt10_ick, CK_243X | CK_242X), | ||
152 | CLK(NULL, "gpt10_fck", &gpt10_fck, CK_243X | CK_242X), | ||
153 | CLK(NULL, "gpt11_ick", &gpt11_ick, CK_243X | CK_242X), | ||
154 | CLK(NULL, "gpt11_fck", &gpt11_fck, CK_243X | CK_242X), | ||
155 | CLK(NULL, "gpt12_ick", &gpt12_ick, CK_243X | CK_242X), | ||
156 | CLK(NULL, "gpt12_fck", &gpt12_fck, CK_243X | CK_242X), | ||
157 | CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_243X | CK_242X), | ||
158 | CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_243X | CK_242X), | ||
159 | CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_243X | CK_242X), | ||
160 | CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_243X | CK_242X), | ||
161 | CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_243X), | ||
162 | CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_243X), | ||
163 | CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_243X), | ||
164 | CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_243X), | ||
165 | CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_243X), | ||
166 | CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_243X), | ||
167 | CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_243X | CK_242X), | ||
168 | CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_243X | CK_242X), | ||
169 | CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_243X | CK_242X), | ||
170 | CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_243X | CK_242X), | ||
171 | CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_243X), | ||
172 | CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_243X), | ||
173 | CLK(NULL, "uart1_ick", &uart1_ick, CK_243X | CK_242X), | ||
174 | CLK(NULL, "uart1_fck", &uart1_fck, CK_243X | CK_242X), | ||
175 | CLK(NULL, "uart2_ick", &uart2_ick, CK_243X | CK_242X), | ||
176 | CLK(NULL, "uart2_fck", &uart2_fck, CK_243X | CK_242X), | ||
177 | CLK(NULL, "uart3_ick", &uart3_ick, CK_243X | CK_242X), | ||
178 | CLK(NULL, "uart3_fck", &uart3_fck, CK_243X | CK_242X), | ||
179 | CLK(NULL, "gpios_ick", &gpios_ick, CK_243X | CK_242X), | ||
180 | CLK(NULL, "gpios_fck", &gpios_fck, CK_243X | CK_242X), | ||
181 | CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_243X | CK_242X), | ||
182 | CLK("omap_wdt", "fck", &mpu_wdt_fck, CK_243X | CK_242X), | ||
183 | CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_243X | CK_242X), | ||
184 | CLK(NULL, "wdt1_ick", &wdt1_ick, CK_243X | CK_242X), | ||
185 | CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_243X | CK_242X), | ||
186 | CLK(NULL, "icr_ick", &icr_ick, CK_243X), | ||
187 | CLK("omap24xxcam", "fck", &cam_fck, CK_243X | CK_242X), | ||
188 | CLK("omap24xxcam", "ick", &cam_ick, CK_243X | CK_242X), | ||
189 | CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_243X | CK_242X), | ||
190 | CLK(NULL, "wdt4_ick", &wdt4_ick, CK_243X | CK_242X), | ||
191 | CLK(NULL, "wdt4_fck", &wdt4_fck, CK_243X | CK_242X), | ||
192 | CLK(NULL, "wdt3_ick", &wdt3_ick, CK_242X), | ||
193 | CLK(NULL, "wdt3_fck", &wdt3_fck, CK_242X), | ||
194 | CLK(NULL, "mspro_ick", &mspro_ick, CK_243X | CK_242X), | ||
195 | CLK(NULL, "mspro_fck", &mspro_fck, CK_243X | CK_242X), | ||
196 | CLK("mmci-omap.0", "ick", &mmc_ick, CK_242X), | ||
197 | CLK("mmci-omap.0", "fck", &mmc_fck, CK_242X), | ||
198 | CLK(NULL, "fac_ick", &fac_ick, CK_243X | CK_242X), | ||
199 | CLK(NULL, "fac_fck", &fac_fck, CK_243X | CK_242X), | ||
200 | CLK(NULL, "eac_ick", &eac_ick, CK_242X), | ||
201 | CLK(NULL, "eac_fck", &eac_fck, CK_242X), | ||
202 | CLK("omap_hdq.0", "ick", &hdq_ick, CK_243X | CK_242X), | ||
203 | CLK("omap_hdq.1", "fck", &hdq_fck, CK_243X | CK_242X), | ||
204 | CLK("i2c_omap.1", "ick", &i2c1_ick, CK_243X | CK_242X), | ||
205 | CLK("i2c_omap.1", "fck", &i2c1_fck, CK_242X), | ||
206 | CLK("i2c_omap.1", "fck", &i2chs1_fck, CK_243X), | ||
207 | CLK("i2c_omap.2", "ick", &i2c2_ick, CK_243X | CK_242X), | ||
208 | CLK("i2c_omap.2", "fck", &i2c2_fck, CK_242X), | ||
209 | CLK("i2c_omap.2", "fck", &i2chs2_fck, CK_243X), | ||
210 | CLK(NULL, "gpmc_fck", &gpmc_fck, CK_243X | CK_242X), | ||
211 | CLK(NULL, "sdma_fck", &sdma_fck, CK_243X | CK_242X), | ||
212 | CLK(NULL, "sdma_ick", &sdma_ick, CK_243X | CK_242X), | ||
213 | CLK(NULL, "vlynq_ick", &vlynq_ick, CK_242X), | ||
214 | CLK(NULL, "vlynq_fck", &vlynq_fck, CK_242X), | ||
215 | CLK(NULL, "sdrc_ick", &sdrc_ick, CK_243X), | ||
216 | CLK(NULL, "des_ick", &des_ick, CK_243X | CK_242X), | ||
217 | CLK(NULL, "sha_ick", &sha_ick, CK_243X | CK_242X), | ||
218 | CLK("omap_rng", "ick", &rng_ick, CK_243X | CK_242X), | ||
219 | CLK(NULL, "aes_ick", &aes_ick, CK_243X | CK_242X), | ||
220 | CLK(NULL, "pka_ick", &pka_ick, CK_243X | CK_242X), | ||
221 | CLK(NULL, "usb_fck", &usb_fck, CK_243X | CK_242X), | ||
222 | CLK("musb_hdrc", "ick", &usbhs_ick, CK_243X), | ||
223 | CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_243X), | ||
224 | CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_243X), | ||
225 | CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_243X), | ||
226 | CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_243X), | ||
227 | CLK(NULL, "gpio5_ick", &gpio5_ick, CK_243X), | ||
228 | CLK(NULL, "gpio5_fck", &gpio5_fck, CK_243X), | ||
229 | CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X), | ||
230 | CLK("mmci-omap-hs.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X), | ||
231 | CLK("mmci-omap-hs.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X), | ||
232 | }; | ||
233 | |||
234 | /* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */ | ||
235 | #define EN_APLL_STOPPED 0 | ||
236 | #define EN_APLL_LOCKED 3 | ||
237 | |||
238 | /* CM_CLKSEL1_PLL.APLLS_CLKIN options (24XX) */ | ||
239 | #define APLLS_CLKIN_19_2MHZ 0 | ||
240 | #define APLLS_CLKIN_13MHZ 2 | ||
241 | #define APLLS_CLKIN_12MHZ 3 | ||
242 | |||
243 | /* #define DOWN_VARIABLE_DPLL 1 */ /* Experimental */ | ||
244 | |||
245 | static struct prcm_config *curr_prcm_set; | ||
246 | static struct clk *vclk; | ||
247 | static struct clk *sclk; | ||
248 | |||
249 | static void __iomem *prcm_clksrc_ctrl; | ||
250 | |||
251 | /*------------------------------------------------------------------------- | ||
252 | * Omap24xx specific clock functions | ||
253 | *-------------------------------------------------------------------------*/ | ||
254 | |||
255 | /** | ||
256 | * omap2430_clk_i2chs_find_idlest - return CM_IDLEST info for 2430 I2CHS | ||
257 | * @clk: struct clk * being enabled | ||
258 | * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into | ||
259 | * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into | ||
260 | * | ||
261 | * OMAP2430 I2CHS CM_IDLEST bits are in CM_IDLEST1_CORE, but the | ||
262 | * CM_*CLKEN bits are in CM_{I,F}CLKEN2_CORE. This custom function | ||
263 | * passes back the correct CM_IDLEST register address for I2CHS | ||
264 | * modules. No return value. | ||
265 | */ | ||
266 | static void omap2430_clk_i2chs_find_idlest(struct clk *clk, | ||
267 | void __iomem **idlest_reg, | ||
268 | u8 *idlest_bit) | ||
269 | { | ||
270 | *idlest_reg = OMAP_CM_REGADDR(CORE_MOD, CM_IDLEST); | ||
271 | *idlest_bit = clk->enable_bit; | ||
272 | } | ||
273 | |||
274 | |||
275 | /** | ||
276 | * omap2xxx_clk_get_core_rate - return the CORE_CLK rate | ||
277 | * @clk: pointer to the combined dpll_ck + core_ck (currently "dpll_ck") | ||
278 | * | ||
279 | * Returns the CORE_CLK rate. CORE_CLK can have one of three rate | ||
280 | * sources on OMAP2xxx: the DPLL CLKOUT rate, DPLL CLKOUTX2, or 32KHz | ||
281 | * (the latter is unusual). This currently should be called with | ||
282 | * struct clk *dpll_ck, which is a composite clock of dpll_ck and | ||
283 | * core_ck. | ||
284 | */ | ||
285 | static unsigned long omap2xxx_clk_get_core_rate(struct clk *clk) | ||
286 | { | ||
287 | long long core_clk; | ||
288 | u32 v; | ||
289 | |||
290 | core_clk = omap2_get_dpll_rate(clk); | ||
291 | |||
292 | v = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); | ||
293 | v &= OMAP24XX_CORE_CLK_SRC_MASK; | ||
294 | |||
295 | if (v == CORE_CLK_SRC_32K) | ||
296 | core_clk = 32768; | ||
297 | else | ||
298 | core_clk *= v; | ||
299 | |||
300 | return core_clk; | ||
301 | } | ||
302 | |||
303 | static int omap2_enable_osc_ck(struct clk *clk) | ||
304 | { | ||
305 | u32 pcc; | ||
306 | |||
307 | pcc = __raw_readl(prcm_clksrc_ctrl); | ||
308 | |||
309 | __raw_writel(pcc & ~OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl); | ||
310 | |||
311 | return 0; | ||
312 | } | ||
313 | |||
314 | static void omap2_disable_osc_ck(struct clk *clk) | ||
315 | { | ||
316 | u32 pcc; | ||
317 | |||
318 | pcc = __raw_readl(prcm_clksrc_ctrl); | ||
319 | |||
320 | __raw_writel(pcc | OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl); | ||
321 | } | ||
322 | |||
323 | static const struct clkops clkops_oscck = { | ||
324 | .enable = &omap2_enable_osc_ck, | ||
325 | .disable = &omap2_disable_osc_ck, | ||
326 | }; | ||
327 | |||
328 | #ifdef OLD_CK | ||
329 | /* Recalculate SYST_CLK */ | ||
330 | static void omap2_sys_clk_recalc(struct clk * clk) | ||
331 | { | ||
332 | u32 div = PRCM_CLKSRC_CTRL; | ||
333 | div &= (1 << 7) | (1 << 6); /* Test if ext clk divided by 1 or 2 */ | ||
334 | div >>= clk->rate_offset; | ||
335 | clk->rate = (clk->parent->rate / div); | ||
336 | propagate_rate(clk); | ||
337 | } | ||
338 | #endif /* OLD_CK */ | ||
339 | |||
340 | /* Enable an APLL if off */ | ||
341 | static int omap2_clk_fixed_enable(struct clk *clk) | ||
342 | { | ||
343 | u32 cval, apll_mask; | ||
344 | |||
345 | apll_mask = EN_APLL_LOCKED << clk->enable_bit; | ||
346 | |||
347 | cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN); | ||
348 | |||
349 | if ((cval & apll_mask) == apll_mask) | ||
350 | return 0; /* apll already enabled */ | ||
351 | |||
352 | cval &= ~apll_mask; | ||
353 | cval |= apll_mask; | ||
354 | cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN); | ||
355 | |||
356 | if (clk == &apll96_ck) | ||
357 | cval = OMAP24XX_ST_96M_APLL; | ||
358 | else if (clk == &apll54_ck) | ||
359 | cval = OMAP24XX_ST_54M_APLL; | ||
360 | |||
361 | omap2_cm_wait_idlest(OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), cval, | ||
362 | clk->name); | ||
363 | |||
364 | /* | ||
365 | * REVISIT: Should we return an error code if omap2_wait_clock_ready() | ||
366 | * fails? | ||
367 | */ | ||
368 | return 0; | ||
369 | } | ||
370 | |||
371 | /* Stop APLL */ | ||
372 | static void omap2_clk_fixed_disable(struct clk *clk) | ||
373 | { | ||
374 | u32 cval; | ||
375 | |||
376 | cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN); | ||
377 | cval &= ~(EN_APLL_LOCKED << clk->enable_bit); | ||
378 | cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN); | ||
379 | } | ||
380 | |||
381 | static const struct clkops clkops_fixed = { | ||
382 | .enable = &omap2_clk_fixed_enable, | ||
383 | .disable = &omap2_clk_fixed_disable, | ||
384 | }; | ||
385 | |||
386 | /* | ||
387 | * Uses the current prcm set to tell if a rate is valid. | ||
388 | * You can go slower, but not faster within a given rate set. | ||
389 | */ | ||
390 | static long omap2_dpllcore_round_rate(unsigned long target_rate) | ||
391 | { | ||
392 | u32 high, low, core_clk_src; | ||
393 | |||
394 | core_clk_src = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); | ||
395 | core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK; | ||
396 | |||
397 | if (core_clk_src == CORE_CLK_SRC_DPLL) { /* DPLL clockout */ | ||
398 | high = curr_prcm_set->dpll_speed * 2; | ||
399 | low = curr_prcm_set->dpll_speed; | ||
400 | } else { /* DPLL clockout x 2 */ | ||
401 | high = curr_prcm_set->dpll_speed; | ||
402 | low = curr_prcm_set->dpll_speed / 2; | ||
403 | } | ||
404 | |||
405 | #ifdef DOWN_VARIABLE_DPLL | ||
406 | if (target_rate > high) | ||
407 | return high; | ||
408 | else | ||
409 | return target_rate; | ||
410 | #else | ||
411 | if (target_rate > low) | ||
412 | return high; | ||
413 | else | ||
414 | return low; | ||
415 | #endif | ||
416 | |||
417 | } | ||
418 | |||
419 | static unsigned long omap2_dpllcore_recalc(struct clk *clk) | ||
420 | { | ||
421 | return omap2xxx_clk_get_core_rate(clk); | ||
422 | } | ||
423 | |||
424 | static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate) | ||
425 | { | ||
426 | u32 cur_rate, low, mult, div, valid_rate, done_rate; | ||
427 | u32 bypass = 0; | ||
428 | struct prcm_config tmpset; | ||
429 | const struct dpll_data *dd; | ||
430 | |||
431 | cur_rate = omap2xxx_clk_get_core_rate(&dpll_ck); | ||
432 | mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); | ||
433 | mult &= OMAP24XX_CORE_CLK_SRC_MASK; | ||
434 | |||
435 | if ((rate == (cur_rate / 2)) && (mult == 2)) { | ||
436 | omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1); | ||
437 | } else if ((rate == (cur_rate * 2)) && (mult == 1)) { | ||
438 | omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1); | ||
439 | } else if (rate != cur_rate) { | ||
440 | valid_rate = omap2_dpllcore_round_rate(rate); | ||
441 | if (valid_rate != rate) | ||
442 | return -EINVAL; | ||
443 | |||
444 | if (mult == 1) | ||
445 | low = curr_prcm_set->dpll_speed; | ||
446 | else | ||
447 | low = curr_prcm_set->dpll_speed / 2; | ||
448 | |||
449 | dd = clk->dpll_data; | ||
450 | if (!dd) | ||
451 | return -EINVAL; | ||
452 | |||
453 | tmpset.cm_clksel1_pll = __raw_readl(dd->mult_div1_reg); | ||
454 | tmpset.cm_clksel1_pll &= ~(dd->mult_mask | | ||
455 | dd->div1_mask); | ||
456 | div = ((curr_prcm_set->xtal_speed / 1000000) - 1); | ||
457 | tmpset.cm_clksel2_pll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); | ||
458 | tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK; | ||
459 | if (rate > low) { | ||
460 | tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2; | ||
461 | mult = ((rate / 2) / 1000000); | ||
462 | done_rate = CORE_CLK_SRC_DPLL_X2; | ||
463 | } else { | ||
464 | tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL; | ||
465 | mult = (rate / 1000000); | ||
466 | done_rate = CORE_CLK_SRC_DPLL; | ||
467 | } | ||
468 | tmpset.cm_clksel1_pll |= (div << __ffs(dd->mult_mask)); | ||
469 | tmpset.cm_clksel1_pll |= (mult << __ffs(dd->div1_mask)); | ||
470 | |||
471 | /* Worst case */ | ||
472 | tmpset.base_sdrc_rfr = SDRC_RFR_CTRL_BYPASS; | ||
473 | |||
474 | if (rate == curr_prcm_set->xtal_speed) /* If asking for 1-1 */ | ||
475 | bypass = 1; | ||
476 | |||
477 | /* For omap2xxx_sdrc_init_params() */ | ||
478 | omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1); | ||
479 | |||
480 | /* Force dll lock mode */ | ||
481 | omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr, | ||
482 | bypass); | ||
483 | |||
484 | /* Errata: ret dll entry state */ | ||
485 | omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked()); | ||
486 | omap2xxx_sdrc_reprogram(done_rate, 0); | ||
487 | } | ||
488 | |||
489 | return 0; | ||
490 | } | ||
491 | |||
492 | /** | ||
493 | * omap2_table_mpu_recalc - just return the MPU speed | ||
494 | * @clk: virt_prcm_set struct clk | ||
495 | * | ||
496 | * Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set. | ||
497 | */ | ||
498 | static unsigned long omap2_table_mpu_recalc(struct clk *clk) | ||
499 | { | ||
500 | return curr_prcm_set->mpu_speed; | ||
501 | } | ||
502 | |||
503 | /* | ||
504 | * Look for a rate equal or less than the target rate given a configuration set. | ||
505 | * | ||
506 | * What's not entirely clear is "which" field represents the key field. | ||
507 | * Some might argue L3-DDR, others ARM, others IVA. This code is simple and | ||
508 | * just uses the ARM rates. | ||
509 | */ | ||
510 | static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate) | ||
511 | { | ||
512 | struct prcm_config *ptr; | ||
513 | long highest_rate; | ||
514 | |||
515 | if (clk != &virt_prcm_set) | ||
516 | return -EINVAL; | ||
517 | |||
518 | highest_rate = -EINVAL; | ||
519 | |||
520 | for (ptr = rate_table; ptr->mpu_speed; ptr++) { | ||
521 | if (!(ptr->flags & cpu_mask)) | ||
522 | continue; | ||
523 | if (ptr->xtal_speed != sys_ck.rate) | ||
524 | continue; | ||
525 | |||
526 | highest_rate = ptr->mpu_speed; | ||
527 | |||
528 | /* Can check only after xtal frequency check */ | ||
529 | if (ptr->mpu_speed <= rate) | ||
530 | break; | ||
531 | } | ||
532 | return highest_rate; | ||
533 | } | ||
534 | |||
535 | /* Sets basic clocks based on the specified rate */ | ||
536 | static int omap2_select_table_rate(struct clk *clk, unsigned long rate) | ||
537 | { | ||
538 | u32 cur_rate, done_rate, bypass = 0, tmp; | ||
539 | struct prcm_config *prcm; | ||
540 | unsigned long found_speed = 0; | ||
541 | unsigned long flags; | ||
542 | |||
543 | if (clk != &virt_prcm_set) | ||
544 | return -EINVAL; | ||
545 | |||
546 | for (prcm = rate_table; prcm->mpu_speed; prcm++) { | ||
547 | if (!(prcm->flags & cpu_mask)) | ||
548 | continue; | ||
549 | |||
550 | if (prcm->xtal_speed != sys_ck.rate) | ||
551 | continue; | ||
552 | |||
553 | if (prcm->mpu_speed <= rate) { | ||
554 | found_speed = prcm->mpu_speed; | ||
555 | break; | ||
556 | } | ||
557 | } | ||
558 | |||
559 | if (!found_speed) { | ||
560 | printk(KERN_INFO "Could not set MPU rate to %luMHz\n", | ||
561 | rate / 1000000); | ||
562 | return -EINVAL; | ||
563 | } | ||
564 | |||
565 | curr_prcm_set = prcm; | ||
566 | cur_rate = omap2xxx_clk_get_core_rate(&dpll_ck); | ||
567 | |||
568 | if (prcm->dpll_speed == cur_rate / 2) { | ||
569 | omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1); | ||
570 | } else if (prcm->dpll_speed == cur_rate * 2) { | ||
571 | omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1); | ||
572 | } else if (prcm->dpll_speed != cur_rate) { | ||
573 | local_irq_save(flags); | ||
574 | |||
575 | if (prcm->dpll_speed == prcm->xtal_speed) | ||
576 | bypass = 1; | ||
577 | |||
578 | if ((prcm->cm_clksel2_pll & OMAP24XX_CORE_CLK_SRC_MASK) == | ||
579 | CORE_CLK_SRC_DPLL_X2) | ||
580 | done_rate = CORE_CLK_SRC_DPLL_X2; | ||
581 | else | ||
582 | done_rate = CORE_CLK_SRC_DPLL; | ||
583 | |||
584 | /* MPU divider */ | ||
585 | cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL); | ||
586 | |||
587 | /* dsp + iva1 div(2420), iva2.1(2430) */ | ||
588 | cm_write_mod_reg(prcm->cm_clksel_dsp, | ||
589 | OMAP24XX_DSP_MOD, CM_CLKSEL); | ||
590 | |||
591 | cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL); | ||
592 | |||
593 | /* Major subsystem dividers */ | ||
594 | tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK; | ||
595 | cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD, | ||
596 | CM_CLKSEL1); | ||
597 | |||
598 | if (cpu_is_omap2430()) | ||
599 | cm_write_mod_reg(prcm->cm_clksel_mdm, | ||
600 | OMAP2430_MDM_MOD, CM_CLKSEL); | ||
601 | |||
602 | /* x2 to enter omap2xxx_sdrc_init_params() */ | ||
603 | omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1); | ||
604 | |||
605 | omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr, | ||
606 | bypass); | ||
607 | |||
608 | omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked()); | ||
609 | omap2xxx_sdrc_reprogram(done_rate, 0); | ||
610 | |||
611 | local_irq_restore(flags); | ||
612 | } | ||
613 | |||
614 | return 0; | ||
615 | } | ||
616 | |||
617 | #ifdef CONFIG_CPU_FREQ | ||
618 | /* | ||
619 | * Walk PRCM rate table and fillout cpufreq freq_table | ||
620 | */ | ||
621 | static struct cpufreq_frequency_table freq_table[ARRAY_SIZE(rate_table)]; | ||
622 | |||
623 | void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table) | ||
624 | { | ||
625 | struct prcm_config *prcm; | ||
626 | int i = 0; | ||
627 | |||
628 | for (prcm = rate_table; prcm->mpu_speed; prcm++) { | ||
629 | if (!(prcm->flags & cpu_mask)) | ||
630 | continue; | ||
631 | if (prcm->xtal_speed != sys_ck.rate) | ||
632 | continue; | ||
633 | |||
634 | /* don't put bypass rates in table */ | ||
635 | if (prcm->dpll_speed == prcm->xtal_speed) | ||
636 | continue; | ||
637 | |||
638 | freq_table[i].index = i; | ||
639 | freq_table[i].frequency = prcm->mpu_speed / 1000; | ||
640 | i++; | ||
641 | } | ||
642 | |||
643 | if (i == 0) { | ||
644 | printk(KERN_WARNING "%s: failed to initialize frequency " | ||
645 | "table\n", __func__); | ||
646 | return; | ||
647 | } | ||
648 | |||
649 | freq_table[i].index = i; | ||
650 | freq_table[i].frequency = CPUFREQ_TABLE_END; | ||
651 | |||
652 | *table = &freq_table[0]; | ||
653 | } | ||
654 | #endif | ||
655 | |||
656 | static struct clk_functions omap2_clk_functions = { | ||
657 | .clk_enable = omap2_clk_enable, | ||
658 | .clk_disable = omap2_clk_disable, | ||
659 | .clk_round_rate = omap2_clk_round_rate, | ||
660 | .clk_set_rate = omap2_clk_set_rate, | ||
661 | .clk_set_parent = omap2_clk_set_parent, | ||
662 | .clk_disable_unused = omap2_clk_disable_unused, | ||
663 | #ifdef CONFIG_CPU_FREQ | ||
664 | .clk_init_cpufreq_table = omap2_clk_init_cpufreq_table, | ||
665 | #endif | ||
666 | }; | ||
667 | |||
668 | static u32 omap2_get_apll_clkin(void) | ||
669 | { | ||
670 | u32 aplls, srate = 0; | ||
671 | |||
672 | aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1); | ||
673 | aplls &= OMAP24XX_APLLS_CLKIN_MASK; | ||
674 | aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT; | ||
675 | |||
676 | if (aplls == APLLS_CLKIN_19_2MHZ) | ||
677 | srate = 19200000; | ||
678 | else if (aplls == APLLS_CLKIN_13MHZ) | ||
679 | srate = 13000000; | ||
680 | else if (aplls == APLLS_CLKIN_12MHZ) | ||
681 | srate = 12000000; | ||
682 | |||
683 | return srate; | ||
684 | } | ||
685 | |||
686 | static u32 omap2_get_sysclkdiv(void) | ||
687 | { | ||
688 | u32 div; | ||
689 | |||
690 | div = __raw_readl(prcm_clksrc_ctrl); | ||
691 | div &= OMAP_SYSCLKDIV_MASK; | ||
692 | div >>= OMAP_SYSCLKDIV_SHIFT; | ||
693 | |||
694 | return div; | ||
695 | } | ||
696 | |||
697 | static unsigned long omap2_osc_clk_recalc(struct clk *clk) | ||
698 | { | ||
699 | return omap2_get_apll_clkin() * omap2_get_sysclkdiv(); | ||
700 | } | ||
701 | |||
702 | static unsigned long omap2_sys_clk_recalc(struct clk *clk) | ||
703 | { | ||
704 | return clk->parent->rate / omap2_get_sysclkdiv(); | ||
705 | } | ||
706 | |||
707 | /* | ||
708 | * Set clocks for bypass mode for reboot to work. | ||
709 | */ | ||
710 | void omap2_clk_prepare_for_reboot(void) | ||
711 | { | ||
712 | u32 rate; | ||
713 | |||
714 | if (vclk == NULL || sclk == NULL) | ||
715 | return; | ||
716 | |||
717 | rate = clk_get_rate(sclk); | ||
718 | clk_set_rate(vclk, rate); | ||
719 | } | ||
720 | |||
721 | /* | ||
722 | * Switch the MPU rate if specified on cmdline. | ||
723 | * We cannot do this early until cmdline is parsed. | ||
724 | */ | ||
725 | static int __init omap2_clk_arch_init(void) | ||
726 | { | ||
727 | if (!mpurate) | ||
728 | return -EINVAL; | ||
729 | |||
730 | if (clk_set_rate(&virt_prcm_set, mpurate)) | ||
731 | printk(KERN_ERR "Could not find matching MPU rate\n"); | ||
732 | |||
733 | recalculate_root_clocks(); | ||
734 | |||
735 | printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL/MPU): " | ||
736 | "%ld.%01ld/%ld/%ld MHz\n", | ||
737 | (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10, | ||
738 | (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ; | ||
739 | |||
740 | return 0; | ||
741 | } | ||
742 | arch_initcall(omap2_clk_arch_init); | ||
743 | |||
744 | int __init omap2_clk_init(void) | ||
745 | { | ||
746 | struct prcm_config *prcm; | ||
747 | struct omap_clk *c; | ||
748 | u32 clkrate; | ||
749 | |||
750 | if (cpu_is_omap242x()) { | ||
751 | prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL; | ||
752 | cpu_mask = RATE_IN_242X; | ||
753 | } else if (cpu_is_omap2430()) { | ||
754 | prcm_clksrc_ctrl = OMAP2430_PRCM_CLKSRC_CTRL; | ||
755 | cpu_mask = RATE_IN_243X; | ||
756 | } | ||
757 | |||
758 | clk_init(&omap2_clk_functions); | ||
759 | |||
760 | for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++) | ||
761 | clk_preinit(c->lk.clk); | ||
762 | |||
763 | osc_ck.rate = omap2_osc_clk_recalc(&osc_ck); | ||
764 | propagate_rate(&osc_ck); | ||
765 | sys_ck.rate = omap2_sys_clk_recalc(&sys_ck); | ||
766 | propagate_rate(&sys_ck); | ||
767 | |||
768 | for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++) | ||
769 | if (c->cpu & cpu_mask) { | ||
770 | clkdev_add(&c->lk); | ||
771 | clk_register(c->lk.clk); | ||
772 | omap2_init_clk_clkdm(c->lk.clk); | ||
773 | } | ||
774 | |||
775 | /* Check the MPU rate set by bootloader */ | ||
776 | clkrate = omap2xxx_clk_get_core_rate(&dpll_ck); | ||
777 | for (prcm = rate_table; prcm->mpu_speed; prcm++) { | ||
778 | if (!(prcm->flags & cpu_mask)) | ||
779 | continue; | ||
780 | if (prcm->xtal_speed != sys_ck.rate) | ||
781 | continue; | ||
782 | if (prcm->dpll_speed <= clkrate) | ||
783 | break; | ||
784 | } | ||
785 | curr_prcm_set = prcm; | ||
786 | |||
787 | recalculate_root_clocks(); | ||
788 | |||
789 | printk(KERN_INFO "Clocking rate (Crystal/DPLL/MPU): " | ||
790 | "%ld.%01ld/%ld/%ld MHz\n", | ||
791 | (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10, | ||
792 | (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ; | ||
793 | |||
794 | /* | ||
795 | * Only enable those clocks we will need, let the drivers | ||
796 | * enable other clocks as necessary | ||
797 | */ | ||
798 | clk_enable_init_clocks(); | ||
799 | |||
800 | /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */ | ||
801 | vclk = clk_get(NULL, "virt_prcm_set"); | ||
802 | sclk = clk_get(NULL, "sys_ck"); | ||
803 | |||
804 | return 0; | ||
805 | } | ||
diff --git a/arch/arm/mach-omap2/clock2xxx.c b/arch/arm/mach-omap2/clock2xxx.c new file mode 100644 index 000000000000..d0e3fb7f9298 --- /dev/null +++ b/arch/arm/mach-omap2/clock2xxx.c | |||
@@ -0,0 +1,587 @@ | |||
1 | /* | ||
2 | * linux/arch/arm/mach-omap2/clock.c | ||
3 | * | ||
4 | * Copyright (C) 2005-2008 Texas Instruments, Inc. | ||
5 | * Copyright (C) 2004-2008 Nokia Corporation | ||
6 | * | ||
7 | * Contacts: | ||
8 | * Richard Woodruff <r-woodruff2@ti.com> | ||
9 | * Paul Walmsley | ||
10 | * | ||
11 | * Based on earlier work by Tuukka Tikkanen, Tony Lindgren, | ||
12 | * Gordon McNutt and RidgeRun, Inc. | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or modify | ||
15 | * it under the terms of the GNU General Public License version 2 as | ||
16 | * published by the Free Software Foundation. | ||
17 | */ | ||
18 | #undef DEBUG | ||
19 | |||
20 | #include <linux/module.h> | ||
21 | #include <linux/kernel.h> | ||
22 | #include <linux/device.h> | ||
23 | #include <linux/list.h> | ||
24 | #include <linux/errno.h> | ||
25 | #include <linux/delay.h> | ||
26 | #include <linux/clk.h> | ||
27 | #include <linux/io.h> | ||
28 | #include <linux/cpufreq.h> | ||
29 | #include <linux/bitops.h> | ||
30 | |||
31 | #include <plat/clock.h> | ||
32 | #include <plat/sram.h> | ||
33 | #include <plat/prcm.h> | ||
34 | #include <plat/clkdev_omap.h> | ||
35 | #include <asm/div64.h> | ||
36 | #include <asm/clkdev.h> | ||
37 | |||
38 | #include <plat/sdrc.h> | ||
39 | #include "clock.h" | ||
40 | #include "clock2xxx.h" | ||
41 | #include "opp2xxx.h" | ||
42 | #include "prm.h" | ||
43 | #include "prm-regbits-24xx.h" | ||
44 | #include "cm.h" | ||
45 | #include "cm-regbits-24xx.h" | ||
46 | |||
47 | |||
48 | /* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */ | ||
49 | #define EN_APLL_STOPPED 0 | ||
50 | #define EN_APLL_LOCKED 3 | ||
51 | |||
52 | /* CM_CLKSEL1_PLL.APLLS_CLKIN options (24XX) */ | ||
53 | #define APLLS_CLKIN_19_2MHZ 0 | ||
54 | #define APLLS_CLKIN_13MHZ 2 | ||
55 | #define APLLS_CLKIN_12MHZ 3 | ||
56 | |||
57 | /* #define DOWN_VARIABLE_DPLL 1 */ /* Experimental */ | ||
58 | |||
59 | const struct prcm_config *curr_prcm_set; | ||
60 | const struct prcm_config *rate_table; | ||
61 | |||
62 | struct clk *vclk, *sclk, *dclk; | ||
63 | |||
64 | void __iomem *prcm_clksrc_ctrl; | ||
65 | |||
66 | /*------------------------------------------------------------------------- | ||
67 | * Omap24xx specific clock functions | ||
68 | *-------------------------------------------------------------------------*/ | ||
69 | |||
70 | /** | ||
71 | * omap2430_clk_i2chs_find_idlest - return CM_IDLEST info for 2430 I2CHS | ||
72 | * @clk: struct clk * being enabled | ||
73 | * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into | ||
74 | * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into | ||
75 | * | ||
76 | * OMAP2430 I2CHS CM_IDLEST bits are in CM_IDLEST1_CORE, but the | ||
77 | * CM_*CLKEN bits are in CM_{I,F}CLKEN2_CORE. This custom function | ||
78 | * passes back the correct CM_IDLEST register address for I2CHS | ||
79 | * modules. No return value. | ||
80 | */ | ||
81 | static void omap2430_clk_i2chs_find_idlest(struct clk *clk, | ||
82 | void __iomem **idlest_reg, | ||
83 | u8 *idlest_bit) | ||
84 | { | ||
85 | *idlest_reg = OMAP_CM_REGADDR(CORE_MOD, CM_IDLEST); | ||
86 | *idlest_bit = clk->enable_bit; | ||
87 | } | ||
88 | |||
89 | /* 2430 I2CHS has non-standard IDLEST register */ | ||
90 | const struct clkops clkops_omap2430_i2chs_wait = { | ||
91 | .enable = omap2_dflt_clk_enable, | ||
92 | .disable = omap2_dflt_clk_disable, | ||
93 | .find_idlest = omap2430_clk_i2chs_find_idlest, | ||
94 | .find_companion = omap2_clk_dflt_find_companion, | ||
95 | }; | ||
96 | |||
97 | /** | ||
98 | * omap2xxx_clk_get_core_rate - return the CORE_CLK rate | ||
99 | * @clk: pointer to the combined dpll_ck + core_ck (currently "dpll_ck") | ||
100 | * | ||
101 | * Returns the CORE_CLK rate. CORE_CLK can have one of three rate | ||
102 | * sources on OMAP2xxx: the DPLL CLKOUT rate, DPLL CLKOUTX2, or 32KHz | ||
103 | * (the latter is unusual). This currently should be called with | ||
104 | * struct clk *dpll_ck, which is a composite clock of dpll_ck and | ||
105 | * core_ck. | ||
106 | */ | ||
107 | unsigned long omap2xxx_clk_get_core_rate(struct clk *clk) | ||
108 | { | ||
109 | long long core_clk; | ||
110 | u32 v; | ||
111 | |||
112 | core_clk = omap2_get_dpll_rate(clk); | ||
113 | |||
114 | v = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); | ||
115 | v &= OMAP24XX_CORE_CLK_SRC_MASK; | ||
116 | |||
117 | if (v == CORE_CLK_SRC_32K) | ||
118 | core_clk = 32768; | ||
119 | else | ||
120 | core_clk *= v; | ||
121 | |||
122 | return core_clk; | ||
123 | } | ||
124 | |||
125 | static int omap2_enable_osc_ck(struct clk *clk) | ||
126 | { | ||
127 | u32 pcc; | ||
128 | |||
129 | pcc = __raw_readl(prcm_clksrc_ctrl); | ||
130 | |||
131 | __raw_writel(pcc & ~OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl); | ||
132 | |||
133 | return 0; | ||
134 | } | ||
135 | |||
136 | static void omap2_disable_osc_ck(struct clk *clk) | ||
137 | { | ||
138 | u32 pcc; | ||
139 | |||
140 | pcc = __raw_readl(prcm_clksrc_ctrl); | ||
141 | |||
142 | __raw_writel(pcc | OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl); | ||
143 | } | ||
144 | |||
145 | const struct clkops clkops_oscck = { | ||
146 | .enable = omap2_enable_osc_ck, | ||
147 | .disable = omap2_disable_osc_ck, | ||
148 | }; | ||
149 | |||
150 | #ifdef OLD_CK | ||
151 | /* Recalculate SYST_CLK */ | ||
152 | static void omap2_sys_clk_recalc(struct clk *clk) | ||
153 | { | ||
154 | u32 div = PRCM_CLKSRC_CTRL; | ||
155 | div &= (1 << 7) | (1 << 6); /* Test if ext clk divided by 1 or 2 */ | ||
156 | div >>= clk->rate_offset; | ||
157 | clk->rate = (clk->parent->rate / div); | ||
158 | propagate_rate(clk); | ||
159 | } | ||
160 | #endif /* OLD_CK */ | ||
161 | |||
162 | /* Enable an APLL if off */ | ||
163 | static int omap2_clk_apll_enable(struct clk *clk, u32 status_mask) | ||
164 | { | ||
165 | u32 cval, apll_mask; | ||
166 | |||
167 | apll_mask = EN_APLL_LOCKED << clk->enable_bit; | ||
168 | |||
169 | cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN); | ||
170 | |||
171 | if ((cval & apll_mask) == apll_mask) | ||
172 | return 0; /* apll already enabled */ | ||
173 | |||
174 | cval &= ~apll_mask; | ||
175 | cval |= apll_mask; | ||
176 | cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN); | ||
177 | |||
178 | omap2_cm_wait_idlest(OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), status_mask, | ||
179 | clk->name); | ||
180 | |||
181 | /* | ||
182 | * REVISIT: Should we return an error code if omap2_wait_clock_ready() | ||
183 | * fails? | ||
184 | */ | ||
185 | return 0; | ||
186 | } | ||
187 | |||
188 | static int omap2_clk_apll96_enable(struct clk *clk) | ||
189 | { | ||
190 | return omap2_clk_apll_enable(clk, OMAP24XX_ST_96M_APLL); | ||
191 | } | ||
192 | |||
193 | static int omap2_clk_apll54_enable(struct clk *clk) | ||
194 | { | ||
195 | return omap2_clk_apll_enable(clk, OMAP24XX_ST_54M_APLL); | ||
196 | } | ||
197 | |||
198 | /* Stop APLL */ | ||
199 | static void omap2_clk_apll_disable(struct clk *clk) | ||
200 | { | ||
201 | u32 cval; | ||
202 | |||
203 | cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN); | ||
204 | cval &= ~(EN_APLL_LOCKED << clk->enable_bit); | ||
205 | cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN); | ||
206 | } | ||
207 | |||
208 | const struct clkops clkops_apll96 = { | ||
209 | .enable = omap2_clk_apll96_enable, | ||
210 | .disable = omap2_clk_apll_disable, | ||
211 | }; | ||
212 | |||
213 | const struct clkops clkops_apll54 = { | ||
214 | .enable = omap2_clk_apll54_enable, | ||
215 | .disable = omap2_clk_apll_disable, | ||
216 | }; | ||
217 | |||
218 | /* | ||
219 | * Uses the current prcm set to tell if a rate is valid. | ||
220 | * You can go slower, but not faster within a given rate set. | ||
221 | */ | ||
222 | long omap2_dpllcore_round_rate(unsigned long target_rate) | ||
223 | { | ||
224 | u32 high, low, core_clk_src; | ||
225 | |||
226 | core_clk_src = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); | ||
227 | core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK; | ||
228 | |||
229 | if (core_clk_src == CORE_CLK_SRC_DPLL) { /* DPLL clockout */ | ||
230 | high = curr_prcm_set->dpll_speed * 2; | ||
231 | low = curr_prcm_set->dpll_speed; | ||
232 | } else { /* DPLL clockout x 2 */ | ||
233 | high = curr_prcm_set->dpll_speed; | ||
234 | low = curr_prcm_set->dpll_speed / 2; | ||
235 | } | ||
236 | |||
237 | #ifdef DOWN_VARIABLE_DPLL | ||
238 | if (target_rate > high) | ||
239 | return high; | ||
240 | else | ||
241 | return target_rate; | ||
242 | #else | ||
243 | if (target_rate > low) | ||
244 | return high; | ||
245 | else | ||
246 | return low; | ||
247 | #endif | ||
248 | |||
249 | } | ||
250 | |||
251 | unsigned long omap2_dpllcore_recalc(struct clk *clk) | ||
252 | { | ||
253 | return omap2xxx_clk_get_core_rate(clk); | ||
254 | } | ||
255 | |||
256 | int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate) | ||
257 | { | ||
258 | u32 cur_rate, low, mult, div, valid_rate, done_rate; | ||
259 | u32 bypass = 0; | ||
260 | struct prcm_config tmpset; | ||
261 | const struct dpll_data *dd; | ||
262 | |||
263 | cur_rate = omap2xxx_clk_get_core_rate(dclk); | ||
264 | mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); | ||
265 | mult &= OMAP24XX_CORE_CLK_SRC_MASK; | ||
266 | |||
267 | if ((rate == (cur_rate / 2)) && (mult == 2)) { | ||
268 | omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1); | ||
269 | } else if ((rate == (cur_rate * 2)) && (mult == 1)) { | ||
270 | omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1); | ||
271 | } else if (rate != cur_rate) { | ||
272 | valid_rate = omap2_dpllcore_round_rate(rate); | ||
273 | if (valid_rate != rate) | ||
274 | return -EINVAL; | ||
275 | |||
276 | if (mult == 1) | ||
277 | low = curr_prcm_set->dpll_speed; | ||
278 | else | ||
279 | low = curr_prcm_set->dpll_speed / 2; | ||
280 | |||
281 | dd = clk->dpll_data; | ||
282 | if (!dd) | ||
283 | return -EINVAL; | ||
284 | |||
285 | tmpset.cm_clksel1_pll = __raw_readl(dd->mult_div1_reg); | ||
286 | tmpset.cm_clksel1_pll &= ~(dd->mult_mask | | ||
287 | dd->div1_mask); | ||
288 | div = ((curr_prcm_set->xtal_speed / 1000000) - 1); | ||
289 | tmpset.cm_clksel2_pll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); | ||
290 | tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK; | ||
291 | if (rate > low) { | ||
292 | tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2; | ||
293 | mult = ((rate / 2) / 1000000); | ||
294 | done_rate = CORE_CLK_SRC_DPLL_X2; | ||
295 | } else { | ||
296 | tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL; | ||
297 | mult = (rate / 1000000); | ||
298 | done_rate = CORE_CLK_SRC_DPLL; | ||
299 | } | ||
300 | tmpset.cm_clksel1_pll |= (div << __ffs(dd->mult_mask)); | ||
301 | tmpset.cm_clksel1_pll |= (mult << __ffs(dd->div1_mask)); | ||
302 | |||
303 | /* Worst case */ | ||
304 | tmpset.base_sdrc_rfr = SDRC_RFR_CTRL_BYPASS; | ||
305 | |||
306 | if (rate == curr_prcm_set->xtal_speed) /* If asking for 1-1 */ | ||
307 | bypass = 1; | ||
308 | |||
309 | /* For omap2xxx_sdrc_init_params() */ | ||
310 | omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1); | ||
311 | |||
312 | /* Force dll lock mode */ | ||
313 | omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr, | ||
314 | bypass); | ||
315 | |||
316 | /* Errata: ret dll entry state */ | ||
317 | omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked()); | ||
318 | omap2xxx_sdrc_reprogram(done_rate, 0); | ||
319 | } | ||
320 | |||
321 | return 0; | ||
322 | } | ||
323 | |||
324 | /** | ||
325 | * omap2_table_mpu_recalc - just return the MPU speed | ||
326 | * @clk: virt_prcm_set struct clk | ||
327 | * | ||
328 | * Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set. | ||
329 | */ | ||
330 | unsigned long omap2_table_mpu_recalc(struct clk *clk) | ||
331 | { | ||
332 | return curr_prcm_set->mpu_speed; | ||
333 | } | ||
334 | |||
335 | /* | ||
336 | * Look for a rate equal or less than the target rate given a configuration set. | ||
337 | * | ||
338 | * What's not entirely clear is "which" field represents the key field. | ||
339 | * Some might argue L3-DDR, others ARM, others IVA. This code is simple and | ||
340 | * just uses the ARM rates. | ||
341 | */ | ||
342 | long omap2_round_to_table_rate(struct clk *clk, unsigned long rate) | ||
343 | { | ||
344 | const struct prcm_config *ptr; | ||
345 | long highest_rate; | ||
346 | long sys_ck_rate; | ||
347 | |||
348 | sys_ck_rate = clk_get_rate(sclk); | ||
349 | |||
350 | highest_rate = -EINVAL; | ||
351 | |||
352 | for (ptr = rate_table; ptr->mpu_speed; ptr++) { | ||
353 | if (!(ptr->flags & cpu_mask)) | ||
354 | continue; | ||
355 | if (ptr->xtal_speed != sys_ck_rate) | ||
356 | continue; | ||
357 | |||
358 | highest_rate = ptr->mpu_speed; | ||
359 | |||
360 | /* Can check only after xtal frequency check */ | ||
361 | if (ptr->mpu_speed <= rate) | ||
362 | break; | ||
363 | } | ||
364 | return highest_rate; | ||
365 | } | ||
366 | |||
367 | /* Sets basic clocks based on the specified rate */ | ||
368 | int omap2_select_table_rate(struct clk *clk, unsigned long rate) | ||
369 | { | ||
370 | u32 cur_rate, done_rate, bypass = 0, tmp; | ||
371 | const struct prcm_config *prcm; | ||
372 | unsigned long found_speed = 0; | ||
373 | unsigned long flags; | ||
374 | long sys_ck_rate; | ||
375 | |||
376 | sys_ck_rate = clk_get_rate(sclk); | ||
377 | |||
378 | for (prcm = rate_table; prcm->mpu_speed; prcm++) { | ||
379 | if (!(prcm->flags & cpu_mask)) | ||
380 | continue; | ||
381 | |||
382 | if (prcm->xtal_speed != sys_ck_rate) | ||
383 | continue; | ||
384 | |||
385 | if (prcm->mpu_speed <= rate) { | ||
386 | found_speed = prcm->mpu_speed; | ||
387 | break; | ||
388 | } | ||
389 | } | ||
390 | |||
391 | if (!found_speed) { | ||
392 | printk(KERN_INFO "Could not set MPU rate to %luMHz\n", | ||
393 | rate / 1000000); | ||
394 | return -EINVAL; | ||
395 | } | ||
396 | |||
397 | curr_prcm_set = prcm; | ||
398 | cur_rate = omap2xxx_clk_get_core_rate(dclk); | ||
399 | |||
400 | if (prcm->dpll_speed == cur_rate / 2) { | ||
401 | omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1); | ||
402 | } else if (prcm->dpll_speed == cur_rate * 2) { | ||
403 | omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1); | ||
404 | } else if (prcm->dpll_speed != cur_rate) { | ||
405 | local_irq_save(flags); | ||
406 | |||
407 | if (prcm->dpll_speed == prcm->xtal_speed) | ||
408 | bypass = 1; | ||
409 | |||
410 | if ((prcm->cm_clksel2_pll & OMAP24XX_CORE_CLK_SRC_MASK) == | ||
411 | CORE_CLK_SRC_DPLL_X2) | ||
412 | done_rate = CORE_CLK_SRC_DPLL_X2; | ||
413 | else | ||
414 | done_rate = CORE_CLK_SRC_DPLL; | ||
415 | |||
416 | /* MPU divider */ | ||
417 | cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL); | ||
418 | |||
419 | /* dsp + iva1 div(2420), iva2.1(2430) */ | ||
420 | cm_write_mod_reg(prcm->cm_clksel_dsp, | ||
421 | OMAP24XX_DSP_MOD, CM_CLKSEL); | ||
422 | |||
423 | cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL); | ||
424 | |||
425 | /* Major subsystem dividers */ | ||
426 | tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK; | ||
427 | cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD, | ||
428 | CM_CLKSEL1); | ||
429 | |||
430 | if (cpu_is_omap2430()) | ||
431 | cm_write_mod_reg(prcm->cm_clksel_mdm, | ||
432 | OMAP2430_MDM_MOD, CM_CLKSEL); | ||
433 | |||
434 | /* x2 to enter omap2xxx_sdrc_init_params() */ | ||
435 | omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1); | ||
436 | |||
437 | omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr, | ||
438 | bypass); | ||
439 | |||
440 | omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked()); | ||
441 | omap2xxx_sdrc_reprogram(done_rate, 0); | ||
442 | |||
443 | local_irq_restore(flags); | ||
444 | } | ||
445 | |||
446 | return 0; | ||
447 | } | ||
448 | |||
449 | #ifdef CONFIG_CPU_FREQ | ||
450 | /* | ||
451 | * Walk PRCM rate table and fillout cpufreq freq_table | ||
452 | */ | ||
453 | static struct cpufreq_frequency_table freq_table[ARRAY_SIZE(rate_table)]; | ||
454 | |||
455 | void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table) | ||
456 | { | ||
457 | struct prcm_config *prcm; | ||
458 | int i = 0; | ||
459 | |||
460 | for (prcm = rate_table; prcm->mpu_speed; prcm++) { | ||
461 | if (!(prcm->flags & cpu_mask)) | ||
462 | continue; | ||
463 | if (prcm->xtal_speed != sys_ck.rate) | ||
464 | continue; | ||
465 | |||
466 | /* don't put bypass rates in table */ | ||
467 | if (prcm->dpll_speed == prcm->xtal_speed) | ||
468 | continue; | ||
469 | |||
470 | freq_table[i].index = i; | ||
471 | freq_table[i].frequency = prcm->mpu_speed / 1000; | ||
472 | i++; | ||
473 | } | ||
474 | |||
475 | if (i == 0) { | ||
476 | printk(KERN_WARNING "%s: failed to initialize frequency " | ||
477 | "table\n", __func__); | ||
478 | return; | ||
479 | } | ||
480 | |||
481 | freq_table[i].index = i; | ||
482 | freq_table[i].frequency = CPUFREQ_TABLE_END; | ||
483 | |||
484 | *table = &freq_table[0]; | ||
485 | } | ||
486 | #endif | ||
487 | |||
488 | struct clk_functions omap2_clk_functions = { | ||
489 | .clk_enable = omap2_clk_enable, | ||
490 | .clk_disable = omap2_clk_disable, | ||
491 | .clk_round_rate = omap2_clk_round_rate, | ||
492 | .clk_set_rate = omap2_clk_set_rate, | ||
493 | .clk_set_parent = omap2_clk_set_parent, | ||
494 | .clk_disable_unused = omap2_clk_disable_unused, | ||
495 | #ifdef CONFIG_CPU_FREQ | ||
496 | .clk_init_cpufreq_table = omap2_clk_init_cpufreq_table, | ||
497 | #endif | ||
498 | }; | ||
499 | |||
500 | static u32 omap2_get_apll_clkin(void) | ||
501 | { | ||
502 | u32 aplls, srate = 0; | ||
503 | |||
504 | aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1); | ||
505 | aplls &= OMAP24XX_APLLS_CLKIN_MASK; | ||
506 | aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT; | ||
507 | |||
508 | if (aplls == APLLS_CLKIN_19_2MHZ) | ||
509 | srate = 19200000; | ||
510 | else if (aplls == APLLS_CLKIN_13MHZ) | ||
511 | srate = 13000000; | ||
512 | else if (aplls == APLLS_CLKIN_12MHZ) | ||
513 | srate = 12000000; | ||
514 | |||
515 | return srate; | ||
516 | } | ||
517 | |||
518 | static u32 omap2_get_sysclkdiv(void) | ||
519 | { | ||
520 | u32 div; | ||
521 | |||
522 | div = __raw_readl(prcm_clksrc_ctrl); | ||
523 | div &= OMAP_SYSCLKDIV_MASK; | ||
524 | div >>= OMAP_SYSCLKDIV_SHIFT; | ||
525 | |||
526 | return div; | ||
527 | } | ||
528 | |||
529 | unsigned long omap2_osc_clk_recalc(struct clk *clk) | ||
530 | { | ||
531 | return omap2_get_apll_clkin() * omap2_get_sysclkdiv(); | ||
532 | } | ||
533 | |||
534 | unsigned long omap2_sys_clk_recalc(struct clk *clk) | ||
535 | { | ||
536 | return clk->parent->rate / omap2_get_sysclkdiv(); | ||
537 | } | ||
538 | |||
539 | /* | ||
540 | * Set clocks for bypass mode for reboot to work. | ||
541 | */ | ||
542 | void omap2_clk_prepare_for_reboot(void) | ||
543 | { | ||
544 | u32 rate; | ||
545 | |||
546 | if (vclk == NULL || sclk == NULL) | ||
547 | return; | ||
548 | |||
549 | rate = clk_get_rate(sclk); | ||
550 | clk_set_rate(vclk, rate); | ||
551 | } | ||
552 | |||
553 | /* | ||
554 | * Switch the MPU rate if specified on cmdline. | ||
555 | * We cannot do this early until cmdline is parsed. | ||
556 | */ | ||
557 | static int __init omap2_clk_arch_init(void) | ||
558 | { | ||
559 | struct clk *virt_prcm_set, *sys_ck, *dpll_ck, *mpu_ck; | ||
560 | unsigned long sys_ck_rate; | ||
561 | |||
562 | if (!mpurate) | ||
563 | return -EINVAL; | ||
564 | |||
565 | virt_prcm_set = clk_get(NULL, "virt_prcm_set"); | ||
566 | sys_ck = clk_get(NULL, "sys_ck"); | ||
567 | dpll_ck = clk_get(NULL, "dpll_ck"); | ||
568 | mpu_ck = clk_get(NULL, "mpu_ck"); | ||
569 | |||
570 | if (clk_set_rate(virt_prcm_set, mpurate)) | ||
571 | printk(KERN_ERR "Could not find matching MPU rate\n"); | ||
572 | |||
573 | recalculate_root_clocks(); | ||
574 | |||
575 | sys_ck_rate = clk_get_rate(sys_ck); | ||
576 | |||
577 | pr_info("Switched to new clocking rate (Crystal/DPLL/MPU): " | ||
578 | "%ld.%01ld/%ld/%ld MHz\n", | ||
579 | (sys_ck_rate / 1000000), (sys_ck_rate / 100000) % 10, | ||
580 | (clk_get_rate(dpll_ck) / 1000000), | ||
581 | (clk_get_rate(mpu_ck) / 1000000)); | ||
582 | |||
583 | return 0; | ||
584 | } | ||
585 | arch_initcall(omap2_clk_arch_init); | ||
586 | |||
587 | |||
diff --git a/arch/arm/mach-omap2/clock2xxx.h b/arch/arm/mach-omap2/clock2xxx.h new file mode 100644 index 000000000000..e35efde4bd80 --- /dev/null +++ b/arch/arm/mach-omap2/clock2xxx.h | |||
@@ -0,0 +1,41 @@ | |||
1 | /* | ||
2 | * OMAP2 clock function prototypes and macros | ||
3 | * | ||
4 | * Copyright (C) 2005-2009 Texas Instruments, Inc. | ||
5 | * Copyright (C) 2004-2009 Nokia Corporation | ||
6 | */ | ||
7 | |||
8 | #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_24XX_H | ||
9 | #define __ARCH_ARM_MACH_OMAP2_CLOCK_24XX_H | ||
10 | |||
11 | unsigned long omap2_table_mpu_recalc(struct clk *clk); | ||
12 | int omap2_select_table_rate(struct clk *clk, unsigned long rate); | ||
13 | long omap2_round_to_table_rate(struct clk *clk, unsigned long rate); | ||
14 | unsigned long omap2_sys_clk_recalc(struct clk *clk); | ||
15 | unsigned long omap2_osc_clk_recalc(struct clk *clk); | ||
16 | unsigned long omap2_sys_clk_recalc(struct clk *clk); | ||
17 | unsigned long omap2_dpllcore_recalc(struct clk *clk); | ||
18 | int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate); | ||
19 | unsigned long omap2xxx_clk_get_core_rate(struct clk *clk); | ||
20 | |||
21 | /* REVISIT: These should be set dynamically for CONFIG_MULTI_OMAP2 */ | ||
22 | #ifdef CONFIG_ARCH_OMAP2420 | ||
23 | #define OMAP_CM_REGADDR OMAP2420_CM_REGADDR | ||
24 | #define OMAP24XX_PRCM_CLKOUT_CTRL OMAP2420_PRCM_CLKOUT_CTRL | ||
25 | #define OMAP24XX_PRCM_CLKEMUL_CTRL OMAP2420_PRCM_CLKEMUL_CTRL | ||
26 | #else | ||
27 | #define OMAP_CM_REGADDR OMAP2430_CM_REGADDR | ||
28 | #define OMAP24XX_PRCM_CLKOUT_CTRL OMAP2430_PRCM_CLKOUT_CTRL | ||
29 | #define OMAP24XX_PRCM_CLKEMUL_CTRL OMAP2430_PRCM_CLKEMUL_CTRL | ||
30 | #endif | ||
31 | |||
32 | extern void __iomem *prcm_clksrc_ctrl; | ||
33 | |||
34 | extern struct clk *dclk; | ||
35 | |||
36 | extern const struct clkops clkops_omap2430_i2chs_wait; | ||
37 | extern const struct clkops clkops_oscck; | ||
38 | extern const struct clkops clkops_apll96; | ||
39 | extern const struct clkops clkops_apll54; | ||
40 | |||
41 | #endif | ||
diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock2xxx_data.c index d19cf7a7d8db..97dc7cf7751d 100644 --- a/arch/arm/mach-omap2/clock24xx.h +++ b/arch/arm/mach-omap2/clock2xxx_data.c | |||
@@ -1,8 +1,8 @@ | |||
1 | /* | 1 | /* |
2 | * linux/arch/arm/mach-omap2/clock24xx.h | 2 | * linux/arch/arm/mach-omap2/clock2xxx_data.c |
3 | * | 3 | * |
4 | * Copyright (C) 2005-2008 Texas Instruments, Inc. | 4 | * Copyright (C) 2005-2009 Texas Instruments, Inc. |
5 | * Copyright (C) 2004-2008 Nokia Corporation | 5 | * Copyright (C) 2004-2009 Nokia Corporation |
6 | * | 6 | * |
7 | * Contacts: | 7 | * Contacts: |
8 | * Richard Woodruff <r-woodruff2@ti.com> | 8 | * Richard Woodruff <r-woodruff2@ti.com> |
@@ -13,600 +13,21 @@ | |||
13 | * published by the Free Software Foundation. | 13 | * published by the Free Software Foundation. |
14 | */ | 14 | */ |
15 | 15 | ||
16 | #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H | 16 | #include <linux/module.h> |
17 | #define __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H | 17 | #include <linux/kernel.h> |
18 | #include <linux/clk.h> | ||
18 | 19 | ||
19 | #include "clock.h" | 20 | #include <plat/clkdev_omap.h> |
20 | 21 | ||
22 | #include "clock.h" | ||
23 | #include "clock2xxx.h" | ||
24 | #include "opp2xxx.h" | ||
21 | #include "prm.h" | 25 | #include "prm.h" |
22 | #include "cm.h" | 26 | #include "cm.h" |
23 | #include "prm-regbits-24xx.h" | 27 | #include "prm-regbits-24xx.h" |
24 | #include "cm-regbits-24xx.h" | 28 | #include "cm-regbits-24xx.h" |
25 | #include "sdrc.h" | 29 | #include "sdrc.h" |
26 | 30 | ||
27 | /* REVISIT: These should be set dynamically for CONFIG_MULTI_OMAP2 */ | ||
28 | #ifdef CONFIG_ARCH_OMAP2420 | ||
29 | #define OMAP_CM_REGADDR OMAP2420_CM_REGADDR | ||
30 | #define OMAP24XX_PRCM_CLKOUT_CTRL OMAP2420_PRCM_CLKOUT_CTRL | ||
31 | #define OMAP24XX_PRCM_CLKEMUL_CTRL OMAP2420_PRCM_CLKEMUL_CTRL | ||
32 | #else | ||
33 | #define OMAP_CM_REGADDR OMAP2430_CM_REGADDR | ||
34 | #define OMAP24XX_PRCM_CLKOUT_CTRL OMAP2430_PRCM_CLKOUT_CTRL | ||
35 | #define OMAP24XX_PRCM_CLKEMUL_CTRL OMAP2430_PRCM_CLKEMUL_CTRL | ||
36 | #endif | ||
37 | |||
38 | static unsigned long omap2_table_mpu_recalc(struct clk *clk); | ||
39 | static int omap2_select_table_rate(struct clk *clk, unsigned long rate); | ||
40 | static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate); | ||
41 | static unsigned long omap2_sys_clk_recalc(struct clk *clk); | ||
42 | static unsigned long omap2_osc_clk_recalc(struct clk *clk); | ||
43 | static unsigned long omap2_sys_clk_recalc(struct clk *clk); | ||
44 | static unsigned long omap2_dpllcore_recalc(struct clk *clk); | ||
45 | static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate); | ||
46 | |||
47 | /* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated. | ||
48 | * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP | ||
49 | * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM | ||
50 | */ | ||
51 | struct prcm_config { | ||
52 | unsigned long xtal_speed; /* crystal rate */ | ||
53 | unsigned long dpll_speed; /* dpll: out*xtal*M/(N-1)table_recalc */ | ||
54 | unsigned long mpu_speed; /* speed of MPU */ | ||
55 | unsigned long cm_clksel_mpu; /* mpu divider */ | ||
56 | unsigned long cm_clksel_dsp; /* dsp+iva1 div(2420), iva2.1(2430) */ | ||
57 | unsigned long cm_clksel_gfx; /* gfx dividers */ | ||
58 | unsigned long cm_clksel1_core; /* major subsystem dividers */ | ||
59 | unsigned long cm_clksel1_pll; /* m,n */ | ||
60 | unsigned long cm_clksel2_pll; /* dpllx1 or x2 out */ | ||
61 | unsigned long cm_clksel_mdm; /* modem dividers 2430 only */ | ||
62 | unsigned long base_sdrc_rfr; /* base refresh timing for a set */ | ||
63 | unsigned char flags; | ||
64 | }; | ||
65 | |||
66 | /* | ||
67 | * The OMAP2 processor can be run at several discrete 'PRCM configurations'. | ||
68 | * These configurations are characterized by voltage and speed for clocks. | ||
69 | * The device is only validated for certain combinations. One way to express | ||
70 | * these combinations is via the 'ratio's' which the clocks operate with | ||
71 | * respect to each other. These ratio sets are for a given voltage/DPLL | ||
72 | * setting. All configurations can be described by a DPLL setting and a ratio | ||
73 | * There are 3 ratio sets for the 2430 and X ratio sets for 2420. | ||
74 | * | ||
75 | * 2430 differs from 2420 in that there are no more phase synchronizers used. | ||
76 | * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs | ||
77 | * 2430 (iva2.1, NOdsp, mdm) | ||
78 | */ | ||
79 | |||
80 | /* Core fields for cm_clksel, not ratio governed */ | ||
81 | #define RX_CLKSEL_DSS1 (0x10 << 8) | ||
82 | #define RX_CLKSEL_DSS2 (0x0 << 13) | ||
83 | #define RX_CLKSEL_SSI (0x5 << 20) | ||
84 | |||
85 | /*------------------------------------------------------------------------- | ||
86 | * Voltage/DPLL ratios | ||
87 | *-------------------------------------------------------------------------*/ | ||
88 | |||
89 | /* 2430 Ratio's, 2430-Ratio Config 1 */ | ||
90 | #define R1_CLKSEL_L3 (4 << 0) | ||
91 | #define R1_CLKSEL_L4 (2 << 5) | ||
92 | #define R1_CLKSEL_USB (4 << 25) | ||
93 | #define R1_CM_CLKSEL1_CORE_VAL R1_CLKSEL_USB | RX_CLKSEL_SSI | \ | ||
94 | RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \ | ||
95 | R1_CLKSEL_L4 | R1_CLKSEL_L3 | ||
96 | #define R1_CLKSEL_MPU (2 << 0) | ||
97 | #define R1_CM_CLKSEL_MPU_VAL R1_CLKSEL_MPU | ||
98 | #define R1_CLKSEL_DSP (2 << 0) | ||
99 | #define R1_CLKSEL_DSP_IF (2 << 5) | ||
100 | #define R1_CM_CLKSEL_DSP_VAL R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF | ||
101 | #define R1_CLKSEL_GFX (2 << 0) | ||
102 | #define R1_CM_CLKSEL_GFX_VAL R1_CLKSEL_GFX | ||
103 | #define R1_CLKSEL_MDM (4 << 0) | ||
104 | #define R1_CM_CLKSEL_MDM_VAL R1_CLKSEL_MDM | ||
105 | |||
106 | /* 2430-Ratio Config 2 */ | ||
107 | #define R2_CLKSEL_L3 (6 << 0) | ||
108 | #define R2_CLKSEL_L4 (2 << 5) | ||
109 | #define R2_CLKSEL_USB (2 << 25) | ||
110 | #define R2_CM_CLKSEL1_CORE_VAL R2_CLKSEL_USB | RX_CLKSEL_SSI | \ | ||
111 | RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \ | ||
112 | R2_CLKSEL_L4 | R2_CLKSEL_L3 | ||
113 | #define R2_CLKSEL_MPU (2 << 0) | ||
114 | #define R2_CM_CLKSEL_MPU_VAL R2_CLKSEL_MPU | ||
115 | #define R2_CLKSEL_DSP (2 << 0) | ||
116 | #define R2_CLKSEL_DSP_IF (3 << 5) | ||
117 | #define R2_CM_CLKSEL_DSP_VAL R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF | ||
118 | #define R2_CLKSEL_GFX (2 << 0) | ||
119 | #define R2_CM_CLKSEL_GFX_VAL R2_CLKSEL_GFX | ||
120 | #define R2_CLKSEL_MDM (6 << 0) | ||
121 | #define R2_CM_CLKSEL_MDM_VAL R2_CLKSEL_MDM | ||
122 | |||
123 | /* 2430-Ratio Bootm (BYPASS) */ | ||
124 | #define RB_CLKSEL_L3 (1 << 0) | ||
125 | #define RB_CLKSEL_L4 (1 << 5) | ||
126 | #define RB_CLKSEL_USB (1 << 25) | ||
127 | #define RB_CM_CLKSEL1_CORE_VAL RB_CLKSEL_USB | RX_CLKSEL_SSI | \ | ||
128 | RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \ | ||
129 | RB_CLKSEL_L4 | RB_CLKSEL_L3 | ||
130 | #define RB_CLKSEL_MPU (1 << 0) | ||
131 | #define RB_CM_CLKSEL_MPU_VAL RB_CLKSEL_MPU | ||
132 | #define RB_CLKSEL_DSP (1 << 0) | ||
133 | #define RB_CLKSEL_DSP_IF (1 << 5) | ||
134 | #define RB_CM_CLKSEL_DSP_VAL RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF | ||
135 | #define RB_CLKSEL_GFX (1 << 0) | ||
136 | #define RB_CM_CLKSEL_GFX_VAL RB_CLKSEL_GFX | ||
137 | #define RB_CLKSEL_MDM (1 << 0) | ||
138 | #define RB_CM_CLKSEL_MDM_VAL RB_CLKSEL_MDM | ||
139 | |||
140 | /* 2420 Ratio Equivalents */ | ||
141 | #define RXX_CLKSEL_VLYNQ (0x12 << 15) | ||
142 | #define RXX_CLKSEL_SSI (0x8 << 20) | ||
143 | |||
144 | /* 2420-PRCM III 532MHz core */ | ||
145 | #define RIII_CLKSEL_L3 (4 << 0) /* 133MHz */ | ||
146 | #define RIII_CLKSEL_L4 (2 << 5) /* 66.5MHz */ | ||
147 | #define RIII_CLKSEL_USB (4 << 25) /* 33.25MHz */ | ||
148 | #define RIII_CM_CLKSEL1_CORE_VAL RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \ | ||
149 | RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \ | ||
150 | RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \ | ||
151 | RIII_CLKSEL_L3 | ||
152 | #define RIII_CLKSEL_MPU (2 << 0) /* 266MHz */ | ||
153 | #define RIII_CM_CLKSEL_MPU_VAL RIII_CLKSEL_MPU | ||
154 | #define RIII_CLKSEL_DSP (3 << 0) /* c5x - 177.3MHz */ | ||
155 | #define RIII_CLKSEL_DSP_IF (2 << 5) /* c5x - 88.67MHz */ | ||
156 | #define RIII_SYNC_DSP (1 << 7) /* Enable sync */ | ||
157 | #define RIII_CLKSEL_IVA (6 << 8) /* iva1 - 88.67MHz */ | ||
158 | #define RIII_SYNC_IVA (1 << 13) /* Enable sync */ | ||
159 | #define RIII_CM_CLKSEL_DSP_VAL RIII_SYNC_IVA | RIII_CLKSEL_IVA | \ | ||
160 | RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \ | ||
161 | RIII_CLKSEL_DSP | ||
162 | #define RIII_CLKSEL_GFX (2 << 0) /* 66.5MHz */ | ||
163 | #define RIII_CM_CLKSEL_GFX_VAL RIII_CLKSEL_GFX | ||
164 | |||
165 | /* 2420-PRCM II 600MHz core */ | ||
166 | #define RII_CLKSEL_L3 (6 << 0) /* 100MHz */ | ||
167 | #define RII_CLKSEL_L4 (2 << 5) /* 50MHz */ | ||
168 | #define RII_CLKSEL_USB (2 << 25) /* 50MHz */ | ||
169 | #define RII_CM_CLKSEL1_CORE_VAL RII_CLKSEL_USB | \ | ||
170 | RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \ | ||
171 | RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \ | ||
172 | RII_CLKSEL_L4 | RII_CLKSEL_L3 | ||
173 | #define RII_CLKSEL_MPU (2 << 0) /* 300MHz */ | ||
174 | #define RII_CM_CLKSEL_MPU_VAL RII_CLKSEL_MPU | ||
175 | #define RII_CLKSEL_DSP (3 << 0) /* c5x - 200MHz */ | ||
176 | #define RII_CLKSEL_DSP_IF (2 << 5) /* c5x - 100MHz */ | ||
177 | #define RII_SYNC_DSP (0 << 7) /* Bypass sync */ | ||
178 | #define RII_CLKSEL_IVA (3 << 8) /* iva1 - 200MHz */ | ||
179 | #define RII_SYNC_IVA (0 << 13) /* Bypass sync */ | ||
180 | #define RII_CM_CLKSEL_DSP_VAL RII_SYNC_IVA | RII_CLKSEL_IVA | \ | ||
181 | RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \ | ||
182 | RII_CLKSEL_DSP | ||
183 | #define RII_CLKSEL_GFX (2 << 0) /* 50MHz */ | ||
184 | #define RII_CM_CLKSEL_GFX_VAL RII_CLKSEL_GFX | ||
185 | |||
186 | /* 2420-PRCM I 660MHz core */ | ||
187 | #define RI_CLKSEL_L3 (4 << 0) /* 165MHz */ | ||
188 | #define RI_CLKSEL_L4 (2 << 5) /* 82.5MHz */ | ||
189 | #define RI_CLKSEL_USB (4 << 25) /* 41.25MHz */ | ||
190 | #define RI_CM_CLKSEL1_CORE_VAL RI_CLKSEL_USB | \ | ||
191 | RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \ | ||
192 | RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \ | ||
193 | RI_CLKSEL_L4 | RI_CLKSEL_L3 | ||
194 | #define RI_CLKSEL_MPU (2 << 0) /* 330MHz */ | ||
195 | #define RI_CM_CLKSEL_MPU_VAL RI_CLKSEL_MPU | ||
196 | #define RI_CLKSEL_DSP (3 << 0) /* c5x - 220MHz */ | ||
197 | #define RI_CLKSEL_DSP_IF (2 << 5) /* c5x - 110MHz */ | ||
198 | #define RI_SYNC_DSP (1 << 7) /* Activate sync */ | ||
199 | #define RI_CLKSEL_IVA (4 << 8) /* iva1 - 165MHz */ | ||
200 | #define RI_SYNC_IVA (0 << 13) /* Bypass sync */ | ||
201 | #define RI_CM_CLKSEL_DSP_VAL RI_SYNC_IVA | RI_CLKSEL_IVA | \ | ||
202 | RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \ | ||
203 | RI_CLKSEL_DSP | ||
204 | #define RI_CLKSEL_GFX (1 << 0) /* 165MHz */ | ||
205 | #define RI_CM_CLKSEL_GFX_VAL RI_CLKSEL_GFX | ||
206 | |||
207 | /* 2420-PRCM VII (boot) */ | ||
208 | #define RVII_CLKSEL_L3 (1 << 0) | ||
209 | #define RVII_CLKSEL_L4 (1 << 5) | ||
210 | #define RVII_CLKSEL_DSS1 (1 << 8) | ||
211 | #define RVII_CLKSEL_DSS2 (0 << 13) | ||
212 | #define RVII_CLKSEL_VLYNQ (1 << 15) | ||
213 | #define RVII_CLKSEL_SSI (1 << 20) | ||
214 | #define RVII_CLKSEL_USB (1 << 25) | ||
215 | |||
216 | #define RVII_CM_CLKSEL1_CORE_VAL RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \ | ||
217 | RVII_CLKSEL_VLYNQ | RVII_CLKSEL_DSS2 | \ | ||
218 | RVII_CLKSEL_DSS1 | RVII_CLKSEL_L4 | RVII_CLKSEL_L3 | ||
219 | |||
220 | #define RVII_CLKSEL_MPU (1 << 0) /* all divide by 1 */ | ||
221 | #define RVII_CM_CLKSEL_MPU_VAL RVII_CLKSEL_MPU | ||
222 | |||
223 | #define RVII_CLKSEL_DSP (1 << 0) | ||
224 | #define RVII_CLKSEL_DSP_IF (1 << 5) | ||
225 | #define RVII_SYNC_DSP (0 << 7) | ||
226 | #define RVII_CLKSEL_IVA (1 << 8) | ||
227 | #define RVII_SYNC_IVA (0 << 13) | ||
228 | #define RVII_CM_CLKSEL_DSP_VAL RVII_SYNC_IVA | RVII_CLKSEL_IVA | RVII_SYNC_DSP | \ | ||
229 | RVII_CLKSEL_DSP_IF | RVII_CLKSEL_DSP | ||
230 | |||
231 | #define RVII_CLKSEL_GFX (1 << 0) | ||
232 | #define RVII_CM_CLKSEL_GFX_VAL RVII_CLKSEL_GFX | ||
233 | |||
234 | /*------------------------------------------------------------------------- | ||
235 | * 2430 Target modes: Along with each configuration the CPU has several | ||
236 | * modes which goes along with them. Modes mainly are the addition of | ||
237 | * describe DPLL combinations to go along with a ratio. | ||
238 | *-------------------------------------------------------------------------*/ | ||
239 | |||
240 | /* Hardware governed */ | ||
241 | #define MX_48M_SRC (0 << 3) | ||
242 | #define MX_54M_SRC (0 << 5) | ||
243 | #define MX_APLLS_CLIKIN_12 (3 << 23) | ||
244 | #define MX_APLLS_CLIKIN_13 (2 << 23) | ||
245 | #define MX_APLLS_CLIKIN_19_2 (0 << 23) | ||
246 | |||
247 | /* | ||
248 | * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed | ||
249 | * #5a (ratio1) baseport-target, target DPLL = 266*2 = 532MHz | ||
250 | */ | ||
251 | #define M5A_DPLL_MULT_12 (133 << 12) | ||
252 | #define M5A_DPLL_DIV_12 (5 << 8) | ||
253 | #define M5A_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \ | ||
254 | M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \ | ||
255 | MX_APLLS_CLIKIN_12 | ||
256 | #define M5A_DPLL_MULT_13 (61 << 12) | ||
257 | #define M5A_DPLL_DIV_13 (2 << 8) | ||
258 | #define M5A_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \ | ||
259 | M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \ | ||
260 | MX_APLLS_CLIKIN_13 | ||
261 | #define M5A_DPLL_MULT_19 (55 << 12) | ||
262 | #define M5A_DPLL_DIV_19 (3 << 8) | ||
263 | #define M5A_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \ | ||
264 | M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \ | ||
265 | MX_APLLS_CLIKIN_19_2 | ||
266 | /* #5b (ratio1) target DPLL = 200*2 = 400MHz */ | ||
267 | #define M5B_DPLL_MULT_12 (50 << 12) | ||
268 | #define M5B_DPLL_DIV_12 (2 << 8) | ||
269 | #define M5B_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \ | ||
270 | M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \ | ||
271 | MX_APLLS_CLIKIN_12 | ||
272 | #define M5B_DPLL_MULT_13 (200 << 12) | ||
273 | #define M5B_DPLL_DIV_13 (12 << 8) | ||
274 | |||
275 | #define M5B_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \ | ||
276 | M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \ | ||
277 | MX_APLLS_CLIKIN_13 | ||
278 | #define M5B_DPLL_MULT_19 (125 << 12) | ||
279 | #define M5B_DPLL_DIV_19 (31 << 8) | ||
280 | #define M5B_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \ | ||
281 | M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \ | ||
282 | MX_APLLS_CLIKIN_19_2 | ||
283 | /* | ||
284 | * #4 (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz | ||
285 | */ | ||
286 | #define M4_DPLL_MULT_12 (133 << 12) | ||
287 | #define M4_DPLL_DIV_12 (3 << 8) | ||
288 | #define M4_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \ | ||
289 | M4_DPLL_DIV_12 | M4_DPLL_MULT_12 | \ | ||
290 | MX_APLLS_CLIKIN_12 | ||
291 | |||
292 | #define M4_DPLL_MULT_13 (399 << 12) | ||
293 | #define M4_DPLL_DIV_13 (12 << 8) | ||
294 | #define M4_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \ | ||
295 | M4_DPLL_DIV_13 | M4_DPLL_MULT_13 | \ | ||
296 | MX_APLLS_CLIKIN_13 | ||
297 | |||
298 | #define M4_DPLL_MULT_19 (145 << 12) | ||
299 | #define M4_DPLL_DIV_19 (6 << 8) | ||
300 | #define M4_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \ | ||
301 | M4_DPLL_DIV_19 | M4_DPLL_MULT_19 | \ | ||
302 | MX_APLLS_CLIKIN_19_2 | ||
303 | |||
304 | /* | ||
305 | * #3 (ratio2) baseport-target, target DPLL = 330*2 = 660MHz | ||
306 | */ | ||
307 | #define M3_DPLL_MULT_12 (55 << 12) | ||
308 | #define M3_DPLL_DIV_12 (1 << 8) | ||
309 | #define M3_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \ | ||
310 | M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \ | ||
311 | MX_APLLS_CLIKIN_12 | ||
312 | #define M3_DPLL_MULT_13 (76 << 12) | ||
313 | #define M3_DPLL_DIV_13 (2 << 8) | ||
314 | #define M3_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \ | ||
315 | M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \ | ||
316 | MX_APLLS_CLIKIN_13 | ||
317 | #define M3_DPLL_MULT_19 (17 << 12) | ||
318 | #define M3_DPLL_DIV_19 (0 << 8) | ||
319 | #define M3_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \ | ||
320 | M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \ | ||
321 | MX_APLLS_CLIKIN_19_2 | ||
322 | |||
323 | /* | ||
324 | * #2 (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz | ||
325 | */ | ||
326 | #define M2_DPLL_MULT_12 (55 << 12) | ||
327 | #define M2_DPLL_DIV_12 (1 << 8) | ||
328 | #define M2_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \ | ||
329 | M2_DPLL_DIV_12 | M2_DPLL_MULT_12 | \ | ||
330 | MX_APLLS_CLIKIN_12 | ||
331 | |||
332 | /* Speed changes - Used 658.7MHz instead of 660MHz for LP-Refresh M=76 N=2, | ||
333 | * relock time issue */ | ||
334 | /* Core frequency changed from 330/165 to 329/164 MHz*/ | ||
335 | #define M2_DPLL_MULT_13 (76 << 12) | ||
336 | #define M2_DPLL_DIV_13 (2 << 8) | ||
337 | #define M2_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \ | ||
338 | M2_DPLL_DIV_13 | M2_DPLL_MULT_13 | \ | ||
339 | MX_APLLS_CLIKIN_13 | ||
340 | |||
341 | #define M2_DPLL_MULT_19 (17 << 12) | ||
342 | #define M2_DPLL_DIV_19 (0 << 8) | ||
343 | #define M2_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \ | ||
344 | M2_DPLL_DIV_19 | M2_DPLL_MULT_19 | \ | ||
345 | MX_APLLS_CLIKIN_19_2 | ||
346 | |||
347 | /* boot (boot) */ | ||
348 | #define MB_DPLL_MULT (1 << 12) | ||
349 | #define MB_DPLL_DIV (0 << 8) | ||
350 | #define MB_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\ | ||
351 | MB_DPLL_MULT | MX_APLLS_CLIKIN_12 | ||
352 | |||
353 | #define MB_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\ | ||
354 | MB_DPLL_MULT | MX_APLLS_CLIKIN_13 | ||
355 | |||
356 | #define MB_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\ | ||
357 | MB_DPLL_MULT | MX_APLLS_CLIKIN_19 | ||
358 | |||
359 | /* | ||
360 | * 2430 - chassis (sedna) | ||
361 | * 165 (ratio1) same as above #2 | ||
362 | * 150 (ratio1) | ||
363 | * 133 (ratio2) same as above #4 | ||
364 | * 110 (ratio2) same as above #3 | ||
365 | * 104 (ratio2) | ||
366 | * boot (boot) | ||
367 | */ | ||
368 | |||
369 | /* PRCM I target DPLL = 2*330MHz = 660MHz */ | ||
370 | #define MI_DPLL_MULT_12 (55 << 12) | ||
371 | #define MI_DPLL_DIV_12 (1 << 8) | ||
372 | #define MI_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \ | ||
373 | MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \ | ||
374 | MX_APLLS_CLIKIN_12 | ||
375 | |||
376 | /* | ||
377 | * 2420 Equivalent - mode registers | ||
378 | * PRCM II , target DPLL = 2*300MHz = 600MHz | ||
379 | */ | ||
380 | #define MII_DPLL_MULT_12 (50 << 12) | ||
381 | #define MII_DPLL_DIV_12 (1 << 8) | ||
382 | #define MII_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \ | ||
383 | MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \ | ||
384 | MX_APLLS_CLIKIN_12 | ||
385 | #define MII_DPLL_MULT_13 (300 << 12) | ||
386 | #define MII_DPLL_DIV_13 (12 << 8) | ||
387 | #define MII_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \ | ||
388 | MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \ | ||
389 | MX_APLLS_CLIKIN_13 | ||
390 | |||
391 | /* PRCM III target DPLL = 2*266 = 532MHz*/ | ||
392 | #define MIII_DPLL_MULT_12 (133 << 12) | ||
393 | #define MIII_DPLL_DIV_12 (5 << 8) | ||
394 | #define MIII_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \ | ||
395 | MIII_DPLL_DIV_12 | MIII_DPLL_MULT_12 | \ | ||
396 | MX_APLLS_CLIKIN_12 | ||
397 | #define MIII_DPLL_MULT_13 (266 << 12) | ||
398 | #define MIII_DPLL_DIV_13 (12 << 8) | ||
399 | #define MIII_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \ | ||
400 | MIII_DPLL_DIV_13 | MIII_DPLL_MULT_13 | \ | ||
401 | MX_APLLS_CLIKIN_13 | ||
402 | |||
403 | /* PRCM VII (boot bypass) */ | ||
404 | #define MVII_CM_CLKSEL1_PLL_12_VAL MB_CM_CLKSEL1_PLL_12_VAL | ||
405 | #define MVII_CM_CLKSEL1_PLL_13_VAL MB_CM_CLKSEL1_PLL_13_VAL | ||
406 | |||
407 | /* High and low operation value */ | ||
408 | #define MX_CLKSEL2_PLL_2x_VAL (2 << 0) | ||
409 | #define MX_CLKSEL2_PLL_1x_VAL (1 << 0) | ||
410 | |||
411 | /* MPU speed defines */ | ||
412 | #define S12M 12000000 | ||
413 | #define S13M 13000000 | ||
414 | #define S19M 19200000 | ||
415 | #define S26M 26000000 | ||
416 | #define S100M 100000000 | ||
417 | #define S133M 133000000 | ||
418 | #define S150M 150000000 | ||
419 | #define S164M 164000000 | ||
420 | #define S165M 165000000 | ||
421 | #define S199M 199000000 | ||
422 | #define S200M 200000000 | ||
423 | #define S266M 266000000 | ||
424 | #define S300M 300000000 | ||
425 | #define S329M 329000000 | ||
426 | #define S330M 330000000 | ||
427 | #define S399M 399000000 | ||
428 | #define S400M 400000000 | ||
429 | #define S532M 532000000 | ||
430 | #define S600M 600000000 | ||
431 | #define S658M 658000000 | ||
432 | #define S660M 660000000 | ||
433 | #define S798M 798000000 | ||
434 | |||
435 | /*------------------------------------------------------------------------- | ||
436 | * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated. | ||
437 | * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU, | ||
438 | * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL, | ||
439 | * CM_CLKSEL2_PLL, CM_CLKSEL_MDM | ||
440 | * | ||
441 | * Filling in table based on H4 boards and 2430-SDPs variants available. | ||
442 | * There are quite a few more rates combinations which could be defined. | ||
443 | * | ||
444 | * When multiple values are defined the start up will try and choose the | ||
445 | * fastest one. If a 'fast' value is defined, then automatically, the /2 | ||
446 | * one should be included as it can be used. Generally having more that | ||
447 | * one fast set does not make sense, as static timings need to be changed | ||
448 | * to change the set. The exception is the bypass setting which is | ||
449 | * availble for low power bypass. | ||
450 | * | ||
451 | * Note: This table needs to be sorted, fastest to slowest. | ||
452 | *-------------------------------------------------------------------------*/ | ||
453 | static struct prcm_config rate_table[] = { | ||
454 | /* PRCM I - FAST */ | ||
455 | {S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */ | ||
456 | RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL, | ||
457 | RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL, | ||
458 | MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_165MHz, | ||
459 | RATE_IN_242X}, | ||
460 | |||
461 | /* PRCM II - FAST */ | ||
462 | {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */ | ||
463 | RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL, | ||
464 | RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL, | ||
465 | MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz, | ||
466 | RATE_IN_242X}, | ||
467 | |||
468 | {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */ | ||
469 | RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL, | ||
470 | RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL, | ||
471 | MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz, | ||
472 | RATE_IN_242X}, | ||
473 | |||
474 | /* PRCM III - FAST */ | ||
475 | {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */ | ||
476 | RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL, | ||
477 | RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL, | ||
478 | MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz, | ||
479 | RATE_IN_242X}, | ||
480 | |||
481 | {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */ | ||
482 | RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL, | ||
483 | RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL, | ||
484 | MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz, | ||
485 | RATE_IN_242X}, | ||
486 | |||
487 | /* PRCM II - SLOW */ | ||
488 | {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */ | ||
489 | RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL, | ||
490 | RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL, | ||
491 | MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz, | ||
492 | RATE_IN_242X}, | ||
493 | |||
494 | {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */ | ||
495 | RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL, | ||
496 | RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL, | ||
497 | MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz, | ||
498 | RATE_IN_242X}, | ||
499 | |||
500 | /* PRCM III - SLOW */ | ||
501 | {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */ | ||
502 | RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL, | ||
503 | RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL, | ||
504 | MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz, | ||
505 | RATE_IN_242X}, | ||
506 | |||
507 | {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */ | ||
508 | RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL, | ||
509 | RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL, | ||
510 | MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz, | ||
511 | RATE_IN_242X}, | ||
512 | |||
513 | /* PRCM-VII (boot-bypass) */ | ||
514 | {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL, /* 12MHz ARM*/ | ||
515 | RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL, | ||
516 | RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL, | ||
517 | MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS, | ||
518 | RATE_IN_242X}, | ||
519 | |||
520 | /* PRCM-VII (boot-bypass) */ | ||
521 | {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL, /* 13MHz ARM */ | ||
522 | RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL, | ||
523 | RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL, | ||
524 | MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS, | ||
525 | RATE_IN_242X}, | ||
526 | |||
527 | /* PRCM #4 - ratio2 (ES2.1) - FAST */ | ||
528 | {S13M, S798M, S399M, R2_CM_CLKSEL_MPU_VAL, /* 399MHz ARM */ | ||
529 | R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL, | ||
530 | R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL, | ||
531 | MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL, | ||
532 | SDRC_RFR_CTRL_133MHz, | ||
533 | RATE_IN_243X}, | ||
534 | |||
535 | /* PRCM #2 - ratio1 (ES2) - FAST */ | ||
536 | {S13M, S658M, S329M, R1_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */ | ||
537 | R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, | ||
538 | R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL, | ||
539 | MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL, | ||
540 | SDRC_RFR_CTRL_165MHz, | ||
541 | RATE_IN_243X}, | ||
542 | |||
543 | /* PRCM #5a - ratio1 - FAST */ | ||
544 | {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */ | ||
545 | R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, | ||
546 | R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL, | ||
547 | MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL, | ||
548 | SDRC_RFR_CTRL_133MHz, | ||
549 | RATE_IN_243X}, | ||
550 | |||
551 | /* PRCM #5b - ratio1 - FAST */ | ||
552 | {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */ | ||
553 | R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, | ||
554 | R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL, | ||
555 | MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL, | ||
556 | SDRC_RFR_CTRL_100MHz, | ||
557 | RATE_IN_243X}, | ||
558 | |||
559 | /* PRCM #4 - ratio1 (ES2.1) - SLOW */ | ||
560 | {S13M, S399M, S199M, R2_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */ | ||
561 | R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL, | ||
562 | R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL, | ||
563 | MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL, | ||
564 | SDRC_RFR_CTRL_133MHz, | ||
565 | RATE_IN_243X}, | ||
566 | |||
567 | /* PRCM #2 - ratio1 (ES2) - SLOW */ | ||
568 | {S13M, S329M, S164M, R1_CM_CLKSEL_MPU_VAL, /* 165MHz ARM */ | ||
569 | R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, | ||
570 | R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL, | ||
571 | MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL, | ||
572 | SDRC_RFR_CTRL_165MHz, | ||
573 | RATE_IN_243X}, | ||
574 | |||
575 | /* PRCM #5a - ratio1 - SLOW */ | ||
576 | {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */ | ||
577 | R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, | ||
578 | R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL, | ||
579 | MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL, | ||
580 | SDRC_RFR_CTRL_133MHz, | ||
581 | RATE_IN_243X}, | ||
582 | |||
583 | /* PRCM #5b - ratio1 - SLOW*/ | ||
584 | {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL, /* 100MHz ARM */ | ||
585 | R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, | ||
586 | R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL, | ||
587 | MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL, | ||
588 | SDRC_RFR_CTRL_100MHz, | ||
589 | RATE_IN_243X}, | ||
590 | |||
591 | /* PRCM-boot/bypass */ | ||
592 | {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL, /* 13Mhz */ | ||
593 | RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL, | ||
594 | RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL, | ||
595 | MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL, | ||
596 | SDRC_RFR_CTRL_BYPASS, | ||
597 | RATE_IN_243X}, | ||
598 | |||
599 | /* PRCM-boot/bypass */ | ||
600 | {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL, /* 12Mhz */ | ||
601 | RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL, | ||
602 | RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL, | ||
603 | MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL, | ||
604 | SDRC_RFR_CTRL_BYPASS, | ||
605 | RATE_IN_243X}, | ||
606 | |||
607 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, | ||
608 | }; | ||
609 | |||
610 | /*------------------------------------------------------------------------- | 31 | /*------------------------------------------------------------------------- |
611 | * 24xx clock tree. | 32 | * 24xx clock tree. |
612 | * | 33 | * |
@@ -708,7 +129,7 @@ static struct clk dpll_ck = { | |||
708 | 129 | ||
709 | static struct clk apll96_ck = { | 130 | static struct clk apll96_ck = { |
710 | .name = "apll96_ck", | 131 | .name = "apll96_ck", |
711 | .ops = &clkops_fixed, | 132 | .ops = &clkops_apll96, |
712 | .parent = &sys_ck, | 133 | .parent = &sys_ck, |
713 | .rate = 96000000, | 134 | .rate = 96000000, |
714 | .flags = RATE_FIXED | ENABLE_ON_INIT, | 135 | .flags = RATE_FIXED | ENABLE_ON_INIT, |
@@ -719,7 +140,7 @@ static struct clk apll96_ck = { | |||
719 | 140 | ||
720 | static struct clk apll54_ck = { | 141 | static struct clk apll54_ck = { |
721 | .name = "apll54_ck", | 142 | .name = "apll54_ck", |
722 | .ops = &clkops_fixed, | 143 | .ops = &clkops_apll54, |
723 | .parent = &sys_ck, | 144 | .parent = &sys_ck, |
724 | .rate = 54000000, | 145 | .rate = 54000000, |
725 | .flags = RATE_FIXED | ENABLE_ON_INIT, | 146 | .flags = RATE_FIXED | ENABLE_ON_INIT, |
@@ -2653,5 +2074,236 @@ static struct clk virt_prcm_set = { | |||
2653 | .round_rate = &omap2_round_to_table_rate, | 2074 | .round_rate = &omap2_round_to_table_rate, |
2654 | }; | 2075 | }; |
2655 | 2076 | ||
2656 | #endif | 2077 | |
2078 | /* | ||
2079 | * clkdev integration | ||
2080 | */ | ||
2081 | |||
2082 | static struct omap_clk omap24xx_clks[] = { | ||
2083 | /* external root sources */ | ||
2084 | CLK(NULL, "func_32k_ck", &func_32k_ck, CK_243X | CK_242X), | ||
2085 | CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_243X | CK_242X), | ||
2086 | CLK(NULL, "osc_ck", &osc_ck, CK_243X | CK_242X), | ||
2087 | CLK(NULL, "sys_ck", &sys_ck, CK_243X | CK_242X), | ||
2088 | CLK(NULL, "alt_ck", &alt_ck, CK_243X | CK_242X), | ||
2089 | /* internal analog sources */ | ||
2090 | CLK(NULL, "dpll_ck", &dpll_ck, CK_243X | CK_242X), | ||
2091 | CLK(NULL, "apll96_ck", &apll96_ck, CK_243X | CK_242X), | ||
2092 | CLK(NULL, "apll54_ck", &apll54_ck, CK_243X | CK_242X), | ||
2093 | /* internal prcm root sources */ | ||
2094 | CLK(NULL, "func_54m_ck", &func_54m_ck, CK_243X | CK_242X), | ||
2095 | CLK(NULL, "core_ck", &core_ck, CK_243X | CK_242X), | ||
2096 | CLK(NULL, "func_96m_ck", &func_96m_ck, CK_243X | CK_242X), | ||
2097 | CLK(NULL, "func_48m_ck", &func_48m_ck, CK_243X | CK_242X), | ||
2098 | CLK(NULL, "func_12m_ck", &func_12m_ck, CK_243X | CK_242X), | ||
2099 | CLK(NULL, "ck_wdt1_osc", &wdt1_osc_ck, CK_243X | CK_242X), | ||
2100 | CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_243X | CK_242X), | ||
2101 | CLK(NULL, "sys_clkout", &sys_clkout, CK_243X | CK_242X), | ||
2102 | CLK(NULL, "sys_clkout2_src", &sys_clkout2_src, CK_242X), | ||
2103 | CLK(NULL, "sys_clkout2", &sys_clkout2, CK_242X), | ||
2104 | CLK(NULL, "emul_ck", &emul_ck, CK_242X), | ||
2105 | /* mpu domain clocks */ | ||
2106 | CLK(NULL, "mpu_ck", &mpu_ck, CK_243X | CK_242X), | ||
2107 | /* dsp domain clocks */ | ||
2108 | CLK(NULL, "dsp_fck", &dsp_fck, CK_243X | CK_242X), | ||
2109 | CLK(NULL, "dsp_irate_ick", &dsp_irate_ick, CK_243X | CK_242X), | ||
2110 | CLK(NULL, "dsp_ick", &dsp_ick, CK_242X), | ||
2111 | CLK(NULL, "iva2_1_ick", &iva2_1_ick, CK_243X), | ||
2112 | CLK(NULL, "iva1_ifck", &iva1_ifck, CK_242X), | ||
2113 | CLK(NULL, "iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X), | ||
2114 | /* GFX domain clocks */ | ||
2115 | CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_243X | CK_242X), | ||
2116 | CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_243X | CK_242X), | ||
2117 | CLK(NULL, "gfx_ick", &gfx_ick, CK_243X | CK_242X), | ||
2118 | /* Modem domain clocks */ | ||
2119 | CLK(NULL, "mdm_ick", &mdm_ick, CK_243X), | ||
2120 | CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X), | ||
2121 | /* DSS domain clocks */ | ||
2122 | CLK("omapdss", "ick", &dss_ick, CK_243X | CK_242X), | ||
2123 | CLK("omapdss", "dss1_fck", &dss1_fck, CK_243X | CK_242X), | ||
2124 | CLK("omapdss", "dss2_fck", &dss2_fck, CK_243X | CK_242X), | ||
2125 | CLK("omapdss", "tv_fck", &dss_54m_fck, CK_243X | CK_242X), | ||
2126 | /* L3 domain clocks */ | ||
2127 | CLK(NULL, "core_l3_ck", &core_l3_ck, CK_243X | CK_242X), | ||
2128 | CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_243X | CK_242X), | ||
2129 | CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_243X | CK_242X), | ||
2130 | /* L4 domain clocks */ | ||
2131 | CLK(NULL, "l4_ck", &l4_ck, CK_243X | CK_242X), | ||
2132 | CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_243X | CK_242X), | ||
2133 | /* virtual meta-group clock */ | ||
2134 | CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_243X | CK_242X), | ||
2135 | /* general l4 interface ck, multi-parent functional clk */ | ||
2136 | CLK(NULL, "gpt1_ick", &gpt1_ick, CK_243X | CK_242X), | ||
2137 | CLK(NULL, "gpt1_fck", &gpt1_fck, CK_243X | CK_242X), | ||
2138 | CLK(NULL, "gpt2_ick", &gpt2_ick, CK_243X | CK_242X), | ||
2139 | CLK(NULL, "gpt2_fck", &gpt2_fck, CK_243X | CK_242X), | ||
2140 | CLK(NULL, "gpt3_ick", &gpt3_ick, CK_243X | CK_242X), | ||
2141 | CLK(NULL, "gpt3_fck", &gpt3_fck, CK_243X | CK_242X), | ||
2142 | CLK(NULL, "gpt4_ick", &gpt4_ick, CK_243X | CK_242X), | ||
2143 | CLK(NULL, "gpt4_fck", &gpt4_fck, CK_243X | CK_242X), | ||
2144 | CLK(NULL, "gpt5_ick", &gpt5_ick, CK_243X | CK_242X), | ||
2145 | CLK(NULL, "gpt5_fck", &gpt5_fck, CK_243X | CK_242X), | ||
2146 | CLK(NULL, "gpt6_ick", &gpt6_ick, CK_243X | CK_242X), | ||
2147 | CLK(NULL, "gpt6_fck", &gpt6_fck, CK_243X | CK_242X), | ||
2148 | CLK(NULL, "gpt7_ick", &gpt7_ick, CK_243X | CK_242X), | ||
2149 | CLK(NULL, "gpt7_fck", &gpt7_fck, CK_243X | CK_242X), | ||
2150 | CLK(NULL, "gpt8_ick", &gpt8_ick, CK_243X | CK_242X), | ||
2151 | CLK(NULL, "gpt8_fck", &gpt8_fck, CK_243X | CK_242X), | ||
2152 | CLK(NULL, "gpt9_ick", &gpt9_ick, CK_243X | CK_242X), | ||
2153 | CLK(NULL, "gpt9_fck", &gpt9_fck, CK_243X | CK_242X), | ||
2154 | CLK(NULL, "gpt10_ick", &gpt10_ick, CK_243X | CK_242X), | ||
2155 | CLK(NULL, "gpt10_fck", &gpt10_fck, CK_243X | CK_242X), | ||
2156 | CLK(NULL, "gpt11_ick", &gpt11_ick, CK_243X | CK_242X), | ||
2157 | CLK(NULL, "gpt11_fck", &gpt11_fck, CK_243X | CK_242X), | ||
2158 | CLK(NULL, "gpt12_ick", &gpt12_ick, CK_243X | CK_242X), | ||
2159 | CLK(NULL, "gpt12_fck", &gpt12_fck, CK_243X | CK_242X), | ||
2160 | CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_243X | CK_242X), | ||
2161 | CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_243X | CK_242X), | ||
2162 | CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_243X | CK_242X), | ||
2163 | CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_243X | CK_242X), | ||
2164 | CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_243X), | ||
2165 | CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_243X), | ||
2166 | CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_243X), | ||
2167 | CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_243X), | ||
2168 | CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_243X), | ||
2169 | CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_243X), | ||
2170 | CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_243X | CK_242X), | ||
2171 | CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_243X | CK_242X), | ||
2172 | CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_243X | CK_242X), | ||
2173 | CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_243X | CK_242X), | ||
2174 | CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_243X), | ||
2175 | CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_243X), | ||
2176 | CLK(NULL, "uart1_ick", &uart1_ick, CK_243X | CK_242X), | ||
2177 | CLK(NULL, "uart1_fck", &uart1_fck, CK_243X | CK_242X), | ||
2178 | CLK(NULL, "uart2_ick", &uart2_ick, CK_243X | CK_242X), | ||
2179 | CLK(NULL, "uart2_fck", &uart2_fck, CK_243X | CK_242X), | ||
2180 | CLK(NULL, "uart3_ick", &uart3_ick, CK_243X | CK_242X), | ||
2181 | CLK(NULL, "uart3_fck", &uart3_fck, CK_243X | CK_242X), | ||
2182 | CLK(NULL, "gpios_ick", &gpios_ick, CK_243X | CK_242X), | ||
2183 | CLK(NULL, "gpios_fck", &gpios_fck, CK_243X | CK_242X), | ||
2184 | CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_243X | CK_242X), | ||
2185 | CLK("omap_wdt", "fck", &mpu_wdt_fck, CK_243X | CK_242X), | ||
2186 | CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_243X | CK_242X), | ||
2187 | CLK(NULL, "wdt1_ick", &wdt1_ick, CK_243X | CK_242X), | ||
2188 | CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_243X | CK_242X), | ||
2189 | CLK(NULL, "icr_ick", &icr_ick, CK_243X), | ||
2190 | CLK("omap24xxcam", "fck", &cam_fck, CK_243X | CK_242X), | ||
2191 | CLK("omap24xxcam", "ick", &cam_ick, CK_243X | CK_242X), | ||
2192 | CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_243X | CK_242X), | ||
2193 | CLK(NULL, "wdt4_ick", &wdt4_ick, CK_243X | CK_242X), | ||
2194 | CLK(NULL, "wdt4_fck", &wdt4_fck, CK_243X | CK_242X), | ||
2195 | CLK(NULL, "wdt3_ick", &wdt3_ick, CK_242X), | ||
2196 | CLK(NULL, "wdt3_fck", &wdt3_fck, CK_242X), | ||
2197 | CLK(NULL, "mspro_ick", &mspro_ick, CK_243X | CK_242X), | ||
2198 | CLK(NULL, "mspro_fck", &mspro_fck, CK_243X | CK_242X), | ||
2199 | CLK("mmci-omap.0", "ick", &mmc_ick, CK_242X), | ||
2200 | CLK("mmci-omap.0", "fck", &mmc_fck, CK_242X), | ||
2201 | CLK(NULL, "fac_ick", &fac_ick, CK_243X | CK_242X), | ||
2202 | CLK(NULL, "fac_fck", &fac_fck, CK_243X | CK_242X), | ||
2203 | CLK(NULL, "eac_ick", &eac_ick, CK_242X), | ||
2204 | CLK(NULL, "eac_fck", &eac_fck, CK_242X), | ||
2205 | CLK("omap_hdq.0", "ick", &hdq_ick, CK_243X | CK_242X), | ||
2206 | CLK("omap_hdq.1", "fck", &hdq_fck, CK_243X | CK_242X), | ||
2207 | CLK("i2c_omap.1", "ick", &i2c1_ick, CK_243X | CK_242X), | ||
2208 | CLK("i2c_omap.1", "fck", &i2c1_fck, CK_242X), | ||
2209 | CLK("i2c_omap.1", "fck", &i2chs1_fck, CK_243X), | ||
2210 | CLK("i2c_omap.2", "ick", &i2c2_ick, CK_243X | CK_242X), | ||
2211 | CLK("i2c_omap.2", "fck", &i2c2_fck, CK_242X), | ||
2212 | CLK("i2c_omap.2", "fck", &i2chs2_fck, CK_243X), | ||
2213 | CLK(NULL, "gpmc_fck", &gpmc_fck, CK_243X | CK_242X), | ||
2214 | CLK(NULL, "sdma_fck", &sdma_fck, CK_243X | CK_242X), | ||
2215 | CLK(NULL, "sdma_ick", &sdma_ick, CK_243X | CK_242X), | ||
2216 | CLK(NULL, "vlynq_ick", &vlynq_ick, CK_242X), | ||
2217 | CLK(NULL, "vlynq_fck", &vlynq_fck, CK_242X), | ||
2218 | CLK(NULL, "sdrc_ick", &sdrc_ick, CK_243X), | ||
2219 | CLK(NULL, "des_ick", &des_ick, CK_243X | CK_242X), | ||
2220 | CLK(NULL, "sha_ick", &sha_ick, CK_243X | CK_242X), | ||
2221 | CLK("omap_rng", "ick", &rng_ick, CK_243X | CK_242X), | ||
2222 | CLK(NULL, "aes_ick", &aes_ick, CK_243X | CK_242X), | ||
2223 | CLK(NULL, "pka_ick", &pka_ick, CK_243X | CK_242X), | ||
2224 | CLK(NULL, "usb_fck", &usb_fck, CK_243X | CK_242X), | ||
2225 | CLK("musb_hdrc", "ick", &usbhs_ick, CK_243X), | ||
2226 | CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_243X), | ||
2227 | CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_243X), | ||
2228 | CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_243X), | ||
2229 | CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_243X), | ||
2230 | CLK(NULL, "gpio5_ick", &gpio5_ick, CK_243X), | ||
2231 | CLK(NULL, "gpio5_fck", &gpio5_fck, CK_243X), | ||
2232 | CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X), | ||
2233 | CLK("mmci-omap-hs.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X), | ||
2234 | CLK("mmci-omap-hs.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X), | ||
2235 | }; | ||
2236 | |||
2237 | /* | ||
2238 | * init code | ||
2239 | */ | ||
2240 | |||
2241 | int __init omap2_clk_init(void) | ||
2242 | { | ||
2243 | const struct prcm_config *prcm; | ||
2244 | struct omap_clk *c; | ||
2245 | u32 clkrate; | ||
2246 | u16 cpu_clkflg; | ||
2247 | |||
2248 | if (cpu_is_omap242x()) { | ||
2249 | prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL; | ||
2250 | cpu_mask = RATE_IN_242X; | ||
2251 | cpu_clkflg = CK_242X; | ||
2252 | rate_table = omap2420_rate_table; | ||
2253 | } else if (cpu_is_omap2430()) { | ||
2254 | prcm_clksrc_ctrl = OMAP2430_PRCM_CLKSRC_CTRL; | ||
2255 | cpu_mask = RATE_IN_243X; | ||
2256 | cpu_clkflg = CK_243X; | ||
2257 | rate_table = omap2430_rate_table; | ||
2258 | } | ||
2259 | |||
2260 | clk_init(&omap2_clk_functions); | ||
2261 | |||
2262 | for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++) | ||
2263 | clk_preinit(c->lk.clk); | ||
2264 | |||
2265 | osc_ck.rate = omap2_osc_clk_recalc(&osc_ck); | ||
2266 | propagate_rate(&osc_ck); | ||
2267 | sys_ck.rate = omap2_sys_clk_recalc(&sys_ck); | ||
2268 | propagate_rate(&sys_ck); | ||
2269 | |||
2270 | for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++) | ||
2271 | if (c->cpu & cpu_clkflg) { | ||
2272 | clkdev_add(&c->lk); | ||
2273 | clk_register(c->lk.clk); | ||
2274 | omap2_init_clk_clkdm(c->lk.clk); | ||
2275 | } | ||
2276 | |||
2277 | /* Check the MPU rate set by bootloader */ | ||
2278 | clkrate = omap2xxx_clk_get_core_rate(&dpll_ck); | ||
2279 | for (prcm = rate_table; prcm->mpu_speed; prcm++) { | ||
2280 | if (!(prcm->flags & cpu_mask)) | ||
2281 | continue; | ||
2282 | if (prcm->xtal_speed != sys_ck.rate) | ||
2283 | continue; | ||
2284 | if (prcm->dpll_speed <= clkrate) | ||
2285 | break; | ||
2286 | } | ||
2287 | curr_prcm_set = prcm; | ||
2288 | |||
2289 | recalculate_root_clocks(); | ||
2290 | |||
2291 | printk(KERN_INFO "Clocking rate (Crystal/DPLL/MPU): " | ||
2292 | "%ld.%01ld/%ld/%ld MHz\n", | ||
2293 | (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10, | ||
2294 | (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ; | ||
2295 | |||
2296 | /* | ||
2297 | * Only enable those clocks we will need, let the drivers | ||
2298 | * enable other clocks as necessary | ||
2299 | */ | ||
2300 | clk_enable_init_clocks(); | ||
2301 | |||
2302 | /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */ | ||
2303 | vclk = clk_get(NULL, "virt_prcm_set"); | ||
2304 | sclk = clk_get(NULL, "sys_ck"); | ||
2305 | dclk = clk_get(NULL, "dpll_ck"); | ||
2306 | |||
2307 | return 0; | ||
2308 | } | ||
2657 | 2309 | ||
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c index ecbb5cd8eec8..ded32364f32b 100644 --- a/arch/arm/mach-omap2/clock34xx.c +++ b/arch/arm/mach-omap2/clock34xx.c | |||
@@ -30,314 +30,21 @@ | |||
30 | #include <plat/cpu.h> | 30 | #include <plat/cpu.h> |
31 | #include <plat/clock.h> | 31 | #include <plat/clock.h> |
32 | #include <plat/sram.h> | 32 | #include <plat/sram.h> |
33 | #include <plat/sdrc.h> | ||
33 | #include <asm/div64.h> | 34 | #include <asm/div64.h> |
34 | #include <asm/clkdev.h> | 35 | #include <asm/clkdev.h> |
35 | 36 | ||
36 | #include <plat/sdrc.h> | 37 | #include <plat/sdrc.h> |
37 | #include "clock.h" | 38 | #include "clock.h" |
39 | #include "clock34xx.h" | ||
40 | #include "sdrc.h" | ||
38 | #include "prm.h" | 41 | #include "prm.h" |
39 | #include "prm-regbits-34xx.h" | 42 | #include "prm-regbits-34xx.h" |
40 | #include "cm.h" | 43 | #include "cm.h" |
41 | #include "cm-regbits-34xx.h" | 44 | #include "cm-regbits-34xx.h" |
42 | 45 | ||
43 | static const struct clkops clkops_noncore_dpll_ops; | ||
44 | |||
45 | static void omap3430es2_clk_ssi_find_idlest(struct clk *clk, | ||
46 | void __iomem **idlest_reg, | ||
47 | u8 *idlest_bit); | ||
48 | static void omap3430es2_clk_hsotgusb_find_idlest(struct clk *clk, | ||
49 | void __iomem **idlest_reg, | ||
50 | u8 *idlest_bit); | ||
51 | static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk *clk, | ||
52 | void __iomem **idlest_reg, | ||
53 | u8 *idlest_bit); | ||
54 | |||
55 | static const struct clkops clkops_omap3430es2_ssi_wait = { | ||
56 | .enable = omap2_dflt_clk_enable, | ||
57 | .disable = omap2_dflt_clk_disable, | ||
58 | .find_idlest = omap3430es2_clk_ssi_find_idlest, | ||
59 | .find_companion = omap2_clk_dflt_find_companion, | ||
60 | }; | ||
61 | |||
62 | static const struct clkops clkops_omap3430es2_hsotgusb_wait = { | ||
63 | .enable = omap2_dflt_clk_enable, | ||
64 | .disable = omap2_dflt_clk_disable, | ||
65 | .find_idlest = omap3430es2_clk_hsotgusb_find_idlest, | ||
66 | .find_companion = omap2_clk_dflt_find_companion, | ||
67 | }; | ||
68 | |||
69 | static const struct clkops clkops_omap3430es2_dss_usbhost_wait = { | ||
70 | .enable = omap2_dflt_clk_enable, | ||
71 | .disable = omap2_dflt_clk_disable, | ||
72 | .find_idlest = omap3430es2_clk_dss_usbhost_find_idlest, | ||
73 | .find_companion = omap2_clk_dflt_find_companion, | ||
74 | }; | ||
75 | |||
76 | #include "clock34xx.h" | ||
77 | |||
78 | struct omap_clk { | ||
79 | u32 cpu; | ||
80 | struct clk_lookup lk; | ||
81 | }; | ||
82 | |||
83 | #define CLK(dev, con, ck, cp) \ | ||
84 | { \ | ||
85 | .cpu = cp, \ | ||
86 | .lk = { \ | ||
87 | .dev_id = dev, \ | ||
88 | .con_id = con, \ | ||
89 | .clk = ck, \ | ||
90 | }, \ | ||
91 | } | ||
92 | |||
93 | #define CK_343X (1 << 0) | ||
94 | #define CK_3430ES1 (1 << 1) | ||
95 | #define CK_3430ES2 (1 << 2) | ||
96 | |||
97 | static struct omap_clk omap34xx_clks[] = { | ||
98 | CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_343X), | ||
99 | CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_343X), | ||
100 | CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_343X), | ||
101 | CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2), | ||
102 | CLK(NULL, "virt_19_2m_ck", &virt_19_2m_ck, CK_343X), | ||
103 | CLK(NULL, "virt_26m_ck", &virt_26m_ck, CK_343X), | ||
104 | CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck, CK_343X), | ||
105 | CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_343X), | ||
106 | CLK(NULL, "sys_ck", &sys_ck, CK_343X), | ||
107 | CLK(NULL, "sys_altclk", &sys_altclk, CK_343X), | ||
108 | CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_343X), | ||
109 | CLK(NULL, "sys_clkout1", &sys_clkout1, CK_343X), | ||
110 | CLK(NULL, "dpll1_ck", &dpll1_ck, CK_343X), | ||
111 | CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck, CK_343X), | ||
112 | CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_343X), | ||
113 | CLK(NULL, "dpll2_ck", &dpll2_ck, CK_343X), | ||
114 | CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck, CK_343X), | ||
115 | CLK(NULL, "dpll3_ck", &dpll3_ck, CK_343X), | ||
116 | CLK(NULL, "core_ck", &core_ck, CK_343X), | ||
117 | CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck, CK_343X), | ||
118 | CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck, CK_343X), | ||
119 | CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_343X), | ||
120 | CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck, CK_343X), | ||
121 | CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_343X), | ||
122 | CLK("etb", "emu_core_alwon_ck", &emu_core_alwon_ck, CK_343X), | ||
123 | CLK(NULL, "dpll4_ck", &dpll4_ck, CK_343X), | ||
124 | CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck, CK_343X), | ||
125 | CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_343X), | ||
126 | CLK(NULL, "omap_96m_fck", &omap_96m_fck, CK_343X), | ||
127 | CLK(NULL, "cm_96m_fck", &cm_96m_fck, CK_343X), | ||
128 | CLK(NULL, "omap_54m_fck", &omap_54m_fck, CK_343X), | ||
129 | CLK(NULL, "omap_48m_fck", &omap_48m_fck, CK_343X), | ||
130 | CLK(NULL, "omap_12m_fck", &omap_12m_fck, CK_343X), | ||
131 | CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck, CK_343X), | ||
132 | CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_343X), | ||
133 | CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck, CK_343X), | ||
134 | CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_343X), | ||
135 | CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck, CK_343X), | ||
136 | CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_343X), | ||
137 | CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck, CK_343X), | ||
138 | CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_343X), | ||
139 | CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck, CK_343X), | ||
140 | CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_343X), | ||
141 | CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck, CK_343X), | ||
142 | CLK(NULL, "dpll5_ck", &dpll5_ck, CK_3430ES2), | ||
143 | CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2), | ||
144 | CLK(NULL, "clkout2_src_ck", &clkout2_src_ck, CK_343X), | ||
145 | CLK(NULL, "sys_clkout2", &sys_clkout2, CK_343X), | ||
146 | CLK(NULL, "corex2_fck", &corex2_fck, CK_343X), | ||
147 | CLK(NULL, "dpll1_fck", &dpll1_fck, CK_343X), | ||
148 | CLK(NULL, "mpu_ck", &mpu_ck, CK_343X), | ||
149 | CLK(NULL, "arm_fck", &arm_fck, CK_343X), | ||
150 | CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_343X), | ||
151 | CLK(NULL, "dpll2_fck", &dpll2_fck, CK_343X), | ||
152 | CLK(NULL, "iva2_ck", &iva2_ck, CK_343X), | ||
153 | CLK(NULL, "l3_ick", &l3_ick, CK_343X), | ||
154 | CLK(NULL, "l4_ick", &l4_ick, CK_343X), | ||
155 | CLK(NULL, "rm_ick", &rm_ick, CK_343X), | ||
156 | CLK(NULL, "gfx_l3_ck", &gfx_l3_ck, CK_3430ES1), | ||
157 | CLK(NULL, "gfx_l3_fck", &gfx_l3_fck, CK_3430ES1), | ||
158 | CLK(NULL, "gfx_l3_ick", &gfx_l3_ick, CK_3430ES1), | ||
159 | CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck, CK_3430ES1), | ||
160 | CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck, CK_3430ES1), | ||
161 | CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2), | ||
162 | CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2), | ||
163 | CLK(NULL, "d2d_26m_fck", &d2d_26m_fck, CK_3430ES1), | ||
164 | CLK(NULL, "modem_fck", &modem_fck, CK_343X), | ||
165 | CLK(NULL, "sad2d_ick", &sad2d_ick, CK_343X), | ||
166 | CLK(NULL, "mad2d_ick", &mad2d_ick, CK_343X), | ||
167 | CLK(NULL, "gpt10_fck", &gpt10_fck, CK_343X), | ||
168 | CLK(NULL, "gpt11_fck", &gpt11_fck, CK_343X), | ||
169 | CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2), | ||
170 | CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2), | ||
171 | CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2), | ||
172 | CLK(NULL, "core_96m_fck", &core_96m_fck, CK_343X), | ||
173 | CLK("mmci-omap-hs.2", "fck", &mmchs3_fck, CK_3430ES2), | ||
174 | CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_343X), | ||
175 | CLK(NULL, "mspro_fck", &mspro_fck, CK_343X), | ||
176 | CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_343X), | ||
177 | CLK("i2c_omap.3", "fck", &i2c3_fck, CK_343X), | ||
178 | CLK("i2c_omap.2", "fck", &i2c2_fck, CK_343X), | ||
179 | CLK("i2c_omap.1", "fck", &i2c1_fck, CK_343X), | ||
180 | CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_343X), | ||
181 | CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_343X), | ||
182 | CLK(NULL, "core_48m_fck", &core_48m_fck, CK_343X), | ||
183 | CLK("omap2_mcspi.4", "fck", &mcspi4_fck, CK_343X), | ||
184 | CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_343X), | ||
185 | CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_343X), | ||
186 | CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_343X), | ||
187 | CLK(NULL, "uart2_fck", &uart2_fck, CK_343X), | ||
188 | CLK(NULL, "uart1_fck", &uart1_fck, CK_343X), | ||
189 | CLK(NULL, "fshostusb_fck", &fshostusb_fck, CK_3430ES1), | ||
190 | CLK(NULL, "core_12m_fck", &core_12m_fck, CK_343X), | ||
191 | CLK("omap_hdq.0", "fck", &hdq_fck, CK_343X), | ||
192 | CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1, CK_3430ES1), | ||
193 | CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2, CK_3430ES2), | ||
194 | CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1, CK_3430ES1), | ||
195 | CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es2, CK_3430ES2), | ||
196 | CLK(NULL, "core_l3_ick", &core_l3_ick, CK_343X), | ||
197 | CLK("musb_hdrc", "ick", &hsotgusb_ick_3430es1, CK_3430ES1), | ||
198 | CLK("musb_hdrc", "ick", &hsotgusb_ick_3430es2, CK_3430ES2), | ||
199 | CLK(NULL, "sdrc_ick", &sdrc_ick, CK_343X), | ||
200 | CLK(NULL, "gpmc_fck", &gpmc_fck, CK_343X), | ||
201 | CLK(NULL, "security_l3_ick", &security_l3_ick, CK_343X), | ||
202 | CLK(NULL, "pka_ick", &pka_ick, CK_343X), | ||
203 | CLK(NULL, "core_l4_ick", &core_l4_ick, CK_343X), | ||
204 | CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2), | ||
205 | CLK("mmci-omap-hs.2", "ick", &mmchs3_ick, CK_3430ES2), | ||
206 | CLK(NULL, "icr_ick", &icr_ick, CK_343X), | ||
207 | CLK(NULL, "aes2_ick", &aes2_ick, CK_343X), | ||
208 | CLK(NULL, "sha12_ick", &sha12_ick, CK_343X), | ||
209 | CLK(NULL, "des2_ick", &des2_ick, CK_343X), | ||
210 | CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_343X), | ||
211 | CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_343X), | ||
212 | CLK(NULL, "mspro_ick", &mspro_ick, CK_343X), | ||
213 | CLK("omap_hdq.0", "ick", &hdq_ick, CK_343X), | ||
214 | CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_343X), | ||
215 | CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_343X), | ||
216 | CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_343X), | ||
217 | CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_343X), | ||
218 | CLK("i2c_omap.3", "ick", &i2c3_ick, CK_343X), | ||
219 | CLK("i2c_omap.2", "ick", &i2c2_ick, CK_343X), | ||
220 | CLK("i2c_omap.1", "ick", &i2c1_ick, CK_343X), | ||
221 | CLK(NULL, "uart2_ick", &uart2_ick, CK_343X), | ||
222 | CLK(NULL, "uart1_ick", &uart1_ick, CK_343X), | ||
223 | CLK(NULL, "gpt11_ick", &gpt11_ick, CK_343X), | ||
224 | CLK(NULL, "gpt10_ick", &gpt10_ick, CK_343X), | ||
225 | CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_343X), | ||
226 | CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_343X), | ||
227 | CLK(NULL, "fac_ick", &fac_ick, CK_3430ES1), | ||
228 | CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_343X), | ||
229 | CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_343X), | ||
230 | CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_343X), | ||
231 | CLK(NULL, "ssi_ick", &ssi_ick_3430es1, CK_3430ES1), | ||
232 | CLK(NULL, "ssi_ick", &ssi_ick_3430es2, CK_3430ES2), | ||
233 | CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_3430ES1), | ||
234 | CLK(NULL, "security_l4_ick2", &security_l4_ick2, CK_343X), | ||
235 | CLK(NULL, "aes1_ick", &aes1_ick, CK_343X), | ||
236 | CLK("omap_rng", "ick", &rng_ick, CK_343X), | ||
237 | CLK(NULL, "sha11_ick", &sha11_ick, CK_343X), | ||
238 | CLK(NULL, "des1_ick", &des1_ick, CK_343X), | ||
239 | CLK("omapdss", "dss1_fck", &dss1_alwon_fck_3430es1, CK_3430ES1), | ||
240 | CLK("omapdss", "dss1_fck", &dss1_alwon_fck_3430es2, CK_3430ES2), | ||
241 | CLK("omapdss", "tv_fck", &dss_tv_fck, CK_343X), | ||
242 | CLK("omapdss", "video_fck", &dss_96m_fck, CK_343X), | ||
243 | CLK("omapdss", "dss2_fck", &dss2_alwon_fck, CK_343X), | ||
244 | CLK("omapdss", "ick", &dss_ick_3430es1, CK_3430ES1), | ||
245 | CLK("omapdss", "ick", &dss_ick_3430es2, CK_3430ES2), | ||
246 | CLK(NULL, "cam_mclk", &cam_mclk, CK_343X), | ||
247 | CLK(NULL, "cam_ick", &cam_ick, CK_343X), | ||
248 | CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_343X), | ||
249 | CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2), | ||
250 | CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2), | ||
251 | CLK(NULL, "usbhost_ick", &usbhost_ick, CK_3430ES2), | ||
252 | CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2), | ||
253 | CLK(NULL, "gpt1_fck", &gpt1_fck, CK_343X), | ||
254 | CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_343X), | ||
255 | CLK(NULL, "gpio1_dbck", &gpio1_dbck, CK_343X), | ||
256 | CLK("omap_wdt", "fck", &wdt2_fck, CK_343X), | ||
257 | CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_343X), | ||
258 | CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2), | ||
259 | CLK("omap_wdt", "ick", &wdt2_ick, CK_343X), | ||
260 | CLK(NULL, "wdt1_ick", &wdt1_ick, CK_343X), | ||
261 | CLK(NULL, "gpio1_ick", &gpio1_ick, CK_343X), | ||
262 | CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_343X), | ||
263 | CLK(NULL, "gpt12_ick", &gpt12_ick, CK_343X), | ||
264 | CLK(NULL, "gpt1_ick", &gpt1_ick, CK_343X), | ||
265 | CLK(NULL, "per_96m_fck", &per_96m_fck, CK_343X), | ||
266 | CLK(NULL, "per_48m_fck", &per_48m_fck, CK_343X), | ||
267 | CLK(NULL, "uart3_fck", &uart3_fck, CK_343X), | ||
268 | CLK(NULL, "gpt2_fck", &gpt2_fck, CK_343X), | ||
269 | CLK(NULL, "gpt3_fck", &gpt3_fck, CK_343X), | ||
270 | CLK(NULL, "gpt4_fck", &gpt4_fck, CK_343X), | ||
271 | CLK(NULL, "gpt5_fck", &gpt5_fck, CK_343X), | ||
272 | CLK(NULL, "gpt6_fck", &gpt6_fck, CK_343X), | ||
273 | CLK(NULL, "gpt7_fck", &gpt7_fck, CK_343X), | ||
274 | CLK(NULL, "gpt8_fck", &gpt8_fck, CK_343X), | ||
275 | CLK(NULL, "gpt9_fck", &gpt9_fck, CK_343X), | ||
276 | CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck, CK_343X), | ||
277 | CLK(NULL, "gpio6_dbck", &gpio6_dbck, CK_343X), | ||
278 | CLK(NULL, "gpio5_dbck", &gpio5_dbck, CK_343X), | ||
279 | CLK(NULL, "gpio4_dbck", &gpio4_dbck, CK_343X), | ||
280 | CLK(NULL, "gpio3_dbck", &gpio3_dbck, CK_343X), | ||
281 | CLK(NULL, "gpio2_dbck", &gpio2_dbck, CK_343X), | ||
282 | CLK(NULL, "wdt3_fck", &wdt3_fck, CK_343X), | ||
283 | CLK(NULL, "per_l4_ick", &per_l4_ick, CK_343X), | ||
284 | CLK(NULL, "gpio6_ick", &gpio6_ick, CK_343X), | ||
285 | CLK(NULL, "gpio5_ick", &gpio5_ick, CK_343X), | ||
286 | CLK(NULL, "gpio4_ick", &gpio4_ick, CK_343X), | ||
287 | CLK(NULL, "gpio3_ick", &gpio3_ick, CK_343X), | ||
288 | CLK(NULL, "gpio2_ick", &gpio2_ick, CK_343X), | ||
289 | CLK(NULL, "wdt3_ick", &wdt3_ick, CK_343X), | ||
290 | CLK(NULL, "uart3_ick", &uart3_ick, CK_343X), | ||
291 | CLK(NULL, "gpt9_ick", &gpt9_ick, CK_343X), | ||
292 | CLK(NULL, "gpt8_ick", &gpt8_ick, CK_343X), | ||
293 | CLK(NULL, "gpt7_ick", &gpt7_ick, CK_343X), | ||
294 | CLK(NULL, "gpt6_ick", &gpt6_ick, CK_343X), | ||
295 | CLK(NULL, "gpt5_ick", &gpt5_ick, CK_343X), | ||
296 | CLK(NULL, "gpt4_ick", &gpt4_ick, CK_343X), | ||
297 | CLK(NULL, "gpt3_ick", &gpt3_ick, CK_343X), | ||
298 | CLK(NULL, "gpt2_ick", &gpt2_ick, CK_343X), | ||
299 | CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_343X), | ||
300 | CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_343X), | ||
301 | CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_343X), | ||
302 | CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_343X), | ||
303 | CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_343X), | ||
304 | CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_343X), | ||
305 | CLK("etb", "emu_src_ck", &emu_src_ck, CK_343X), | ||
306 | CLK(NULL, "pclk_fck", &pclk_fck, CK_343X), | ||
307 | CLK(NULL, "pclkx2_fck", &pclkx2_fck, CK_343X), | ||
308 | CLK(NULL, "atclk_fck", &atclk_fck, CK_343X), | ||
309 | CLK(NULL, "traceclk_src_fck", &traceclk_src_fck, CK_343X), | ||
310 | CLK(NULL, "traceclk_fck", &traceclk_fck, CK_343X), | ||
311 | CLK(NULL, "sr1_fck", &sr1_fck, CK_343X), | ||
312 | CLK(NULL, "sr2_fck", &sr2_fck, CK_343X), | ||
313 | CLK(NULL, "sr_l4_ick", &sr_l4_ick, CK_343X), | ||
314 | CLK(NULL, "secure_32k_fck", &secure_32k_fck, CK_343X), | ||
315 | CLK(NULL, "gpt12_fck", &gpt12_fck, CK_343X), | ||
316 | CLK(NULL, "wdt1_fck", &wdt1_fck, CK_343X), | ||
317 | }; | ||
318 | |||
319 | /* CM_AUTOIDLE_PLL*.AUTO_* bit values */ | ||
320 | #define DPLL_AUTOIDLE_DISABLE 0x0 | ||
321 | #define DPLL_AUTOIDLE_LOW_POWER_STOP 0x1 | ||
322 | |||
323 | #define MAX_DPLL_WAIT_TRIES 1000000 | ||
324 | |||
325 | #define MIN_SDRC_DLL_LOCK_FREQ 83000000 | ||
326 | |||
327 | #define CYCLES_PER_MHZ 1000000 | 46 | #define CYCLES_PER_MHZ 1000000 |
328 | 47 | ||
329 | /* Scale factor for fixed-point arith in omap3_core_dpll_m2_set_rate() */ | ||
330 | #define SDRC_MPURATE_SCALE 8 | ||
331 | |||
332 | /* 2^SDRC_MPURATE_BASE_SHIFT: MPU MHz that SDRC_MPURATE_LOOPS is defined for */ | ||
333 | #define SDRC_MPURATE_BASE_SHIFT 9 | ||
334 | |||
335 | /* | ||
336 | * SDRC_MPURATE_LOOPS: Number of MPU loops to execute at | ||
337 | * 2^MPURATE_BASE_SHIFT MHz for SDRC to stabilize | ||
338 | */ | ||
339 | #define SDRC_MPURATE_LOOPS 96 | ||
340 | |||
341 | /* | 48 | /* |
342 | * DPLL5_FREQ_FOR_USBHOST: USBHOST and USBTLL are the only clocks | 49 | * DPLL5_FREQ_FOR_USBHOST: USBHOST and USBTLL are the only clocks |
343 | * that are sourced by DPLL5, and both of these require this clock | 50 | * that are sourced by DPLL5, and both of these require this clock |
@@ -345,6 +52,9 @@ static struct omap_clk omap34xx_clks[] = { | |||
345 | */ | 52 | */ |
346 | #define DPLL5_FREQ_FOR_USBHOST 120000000 | 53 | #define DPLL5_FREQ_FOR_USBHOST 120000000 |
347 | 54 | ||
55 | /* needed by omap3_core_dpll_m2_set_rate() */ | ||
56 | struct clk *sdrc_ick_p, *arm_fck_p; | ||
57 | |||
348 | /** | 58 | /** |
349 | * omap3430es2_clk_ssi_find_idlest - return CM_IDLEST info for SSI | 59 | * omap3430es2_clk_ssi_find_idlest - return CM_IDLEST info for SSI |
350 | * @clk: struct clk * being enabled | 60 | * @clk: struct clk * being enabled |
@@ -366,6 +76,13 @@ static void omap3430es2_clk_ssi_find_idlest(struct clk *clk, | |||
366 | *idlest_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT; | 76 | *idlest_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT; |
367 | } | 77 | } |
368 | 78 | ||
79 | const struct clkops clkops_omap3430es2_ssi_wait = { | ||
80 | .enable = omap2_dflt_clk_enable, | ||
81 | .disable = omap2_dflt_clk_disable, | ||
82 | .find_idlest = omap3430es2_clk_ssi_find_idlest, | ||
83 | .find_companion = omap2_clk_dflt_find_companion, | ||
84 | }; | ||
85 | |||
369 | /** | 86 | /** |
370 | * omap3430es2_clk_dss_usbhost_find_idlest - CM_IDLEST info for DSS, USBHOST | 87 | * omap3430es2_clk_dss_usbhost_find_idlest - CM_IDLEST info for DSS, USBHOST |
371 | * @clk: struct clk * being enabled | 88 | * @clk: struct clk * being enabled |
@@ -391,6 +108,13 @@ static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk *clk, | |||
391 | *idlest_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT; | 108 | *idlest_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT; |
392 | } | 109 | } |
393 | 110 | ||
111 | const struct clkops clkops_omap3430es2_dss_usbhost_wait = { | ||
112 | .enable = omap2_dflt_clk_enable, | ||
113 | .disable = omap2_dflt_clk_disable, | ||
114 | .find_idlest = omap3430es2_clk_dss_usbhost_find_idlest, | ||
115 | .find_companion = omap2_clk_dflt_find_companion, | ||
116 | }; | ||
117 | |||
394 | /** | 118 | /** |
395 | * omap3430es2_clk_hsotgusb_find_idlest - return CM_IDLEST info for HSOTGUSB | 119 | * omap3430es2_clk_hsotgusb_find_idlest - return CM_IDLEST info for HSOTGUSB |
396 | * @clk: struct clk * being enabled | 120 | * @clk: struct clk * being enabled |
@@ -412,395 +136,19 @@ static void omap3430es2_clk_hsotgusb_find_idlest(struct clk *clk, | |||
412 | *idlest_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT; | 136 | *idlest_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT; |
413 | } | 137 | } |
414 | 138 | ||
415 | /** | 139 | const struct clkops clkops_omap3430es2_hsotgusb_wait = { |
416 | * omap3_dpll_recalc - recalculate DPLL rate | 140 | .enable = omap2_dflt_clk_enable, |
417 | * @clk: DPLL struct clk | 141 | .disable = omap2_dflt_clk_disable, |
418 | * | 142 | .find_idlest = omap3430es2_clk_hsotgusb_find_idlest, |
419 | * Recalculate and propagate the DPLL rate. | 143 | .find_companion = omap2_clk_dflt_find_companion, |
420 | */ | 144 | }; |
421 | static unsigned long omap3_dpll_recalc(struct clk *clk) | ||
422 | { | ||
423 | return omap2_get_dpll_rate(clk); | ||
424 | } | ||
425 | |||
426 | /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */ | ||
427 | static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits) | ||
428 | { | ||
429 | const struct dpll_data *dd; | ||
430 | u32 v; | ||
431 | |||
432 | dd = clk->dpll_data; | ||
433 | |||
434 | v = __raw_readl(dd->control_reg); | ||
435 | v &= ~dd->enable_mask; | ||
436 | v |= clken_bits << __ffs(dd->enable_mask); | ||
437 | __raw_writel(v, dd->control_reg); | ||
438 | } | ||
439 | |||
440 | /* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */ | ||
441 | static int _omap3_wait_dpll_status(struct clk *clk, u8 state) | ||
442 | { | ||
443 | const struct dpll_data *dd; | ||
444 | int i = 0; | ||
445 | int ret = -EINVAL; | ||
446 | |||
447 | dd = clk->dpll_data; | ||
448 | |||
449 | state <<= __ffs(dd->idlest_mask); | ||
450 | |||
451 | while (((__raw_readl(dd->idlest_reg) & dd->idlest_mask) != state) && | ||
452 | i < MAX_DPLL_WAIT_TRIES) { | ||
453 | i++; | ||
454 | udelay(1); | ||
455 | } | ||
456 | |||
457 | if (i == MAX_DPLL_WAIT_TRIES) { | ||
458 | printk(KERN_ERR "clock: %s failed transition to '%s'\n", | ||
459 | clk->name, (state) ? "locked" : "bypassed"); | ||
460 | } else { | ||
461 | pr_debug("clock: %s transition to '%s' in %d loops\n", | ||
462 | clk->name, (state) ? "locked" : "bypassed", i); | ||
463 | |||
464 | ret = 0; | ||
465 | } | ||
466 | |||
467 | return ret; | ||
468 | } | ||
469 | |||
470 | /* From 3430 TRM ES2 4.7.6.2 */ | ||
471 | static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n) | ||
472 | { | ||
473 | unsigned long fint; | ||
474 | u16 f = 0; | ||
475 | |||
476 | fint = clk->dpll_data->clk_ref->rate / n; | ||
477 | |||
478 | pr_debug("clock: fint is %lu\n", fint); | ||
479 | |||
480 | if (fint >= 750000 && fint <= 1000000) | ||
481 | f = 0x3; | ||
482 | else if (fint > 1000000 && fint <= 1250000) | ||
483 | f = 0x4; | ||
484 | else if (fint > 1250000 && fint <= 1500000) | ||
485 | f = 0x5; | ||
486 | else if (fint > 1500000 && fint <= 1750000) | ||
487 | f = 0x6; | ||
488 | else if (fint > 1750000 && fint <= 2100000) | ||
489 | f = 0x7; | ||
490 | else if (fint > 7500000 && fint <= 10000000) | ||
491 | f = 0xB; | ||
492 | else if (fint > 10000000 && fint <= 12500000) | ||
493 | f = 0xC; | ||
494 | else if (fint > 12500000 && fint <= 15000000) | ||
495 | f = 0xD; | ||
496 | else if (fint > 15000000 && fint <= 17500000) | ||
497 | f = 0xE; | ||
498 | else if (fint > 17500000 && fint <= 21000000) | ||
499 | f = 0xF; | ||
500 | else | ||
501 | pr_debug("clock: unknown freqsel setting for %d\n", n); | ||
502 | |||
503 | return f; | ||
504 | } | ||
505 | |||
506 | /* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */ | ||
507 | |||
508 | /* | ||
509 | * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness | ||
510 | * @clk: pointer to a DPLL struct clk | ||
511 | * | ||
512 | * Instructs a non-CORE DPLL to lock. Waits for the DPLL to report | ||
513 | * readiness before returning. Will save and restore the DPLL's | ||
514 | * autoidle state across the enable, per the CDP code. If the DPLL | ||
515 | * locked successfully, return 0; if the DPLL did not lock in the time | ||
516 | * allotted, or DPLL3 was passed in, return -EINVAL. | ||
517 | */ | ||
518 | static int _omap3_noncore_dpll_lock(struct clk *clk) | ||
519 | { | ||
520 | u8 ai; | ||
521 | int r; | ||
522 | |||
523 | if (clk == &dpll3_ck) | ||
524 | return -EINVAL; | ||
525 | |||
526 | pr_debug("clock: locking DPLL %s\n", clk->name); | ||
527 | |||
528 | ai = omap3_dpll_autoidle_read(clk); | ||
529 | |||
530 | omap3_dpll_deny_idle(clk); | ||
531 | |||
532 | _omap3_dpll_write_clken(clk, DPLL_LOCKED); | ||
533 | |||
534 | r = _omap3_wait_dpll_status(clk, 1); | ||
535 | |||
536 | if (ai) | ||
537 | omap3_dpll_allow_idle(clk); | ||
538 | |||
539 | return r; | ||
540 | } | ||
541 | |||
542 | /* | ||
543 | * _omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness | ||
544 | * @clk: pointer to a DPLL struct clk | ||
545 | * | ||
546 | * Instructs a non-CORE DPLL to enter low-power bypass mode. In | ||
547 | * bypass mode, the DPLL's rate is set equal to its parent clock's | ||
548 | * rate. Waits for the DPLL to report readiness before returning. | ||
549 | * Will save and restore the DPLL's autoidle state across the enable, | ||
550 | * per the CDP code. If the DPLL entered bypass mode successfully, | ||
551 | * return 0; if the DPLL did not enter bypass in the time allotted, or | ||
552 | * DPLL3 was passed in, or the DPLL does not support low-power bypass, | ||
553 | * return -EINVAL. | ||
554 | */ | ||
555 | static int _omap3_noncore_dpll_bypass(struct clk *clk) | ||
556 | { | ||
557 | int r; | ||
558 | u8 ai; | ||
559 | |||
560 | if (clk == &dpll3_ck) | ||
561 | return -EINVAL; | ||
562 | |||
563 | if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) | ||
564 | return -EINVAL; | ||
565 | |||
566 | pr_debug("clock: configuring DPLL %s for low-power bypass\n", | ||
567 | clk->name); | ||
568 | |||
569 | ai = omap3_dpll_autoidle_read(clk); | ||
570 | |||
571 | _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_BYPASS); | ||
572 | |||
573 | r = _omap3_wait_dpll_status(clk, 0); | ||
574 | |||
575 | if (ai) | ||
576 | omap3_dpll_allow_idle(clk); | ||
577 | else | ||
578 | omap3_dpll_deny_idle(clk); | ||
579 | |||
580 | return r; | ||
581 | } | ||
582 | |||
583 | /* | ||
584 | * _omap3_noncore_dpll_stop - instruct a DPLL to stop | ||
585 | * @clk: pointer to a DPLL struct clk | ||
586 | * | ||
587 | * Instructs a non-CORE DPLL to enter low-power stop. Will save and | ||
588 | * restore the DPLL's autoidle state across the stop, per the CDP | ||
589 | * code. If DPLL3 was passed in, or the DPLL does not support | ||
590 | * low-power stop, return -EINVAL; otherwise, return 0. | ||
591 | */ | ||
592 | static int _omap3_noncore_dpll_stop(struct clk *clk) | ||
593 | { | ||
594 | u8 ai; | ||
595 | |||
596 | if (clk == &dpll3_ck) | ||
597 | return -EINVAL; | ||
598 | |||
599 | if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP))) | ||
600 | return -EINVAL; | ||
601 | |||
602 | pr_debug("clock: stopping DPLL %s\n", clk->name); | ||
603 | |||
604 | ai = omap3_dpll_autoidle_read(clk); | ||
605 | |||
606 | _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_STOP); | ||
607 | |||
608 | if (ai) | ||
609 | omap3_dpll_allow_idle(clk); | ||
610 | else | ||
611 | omap3_dpll_deny_idle(clk); | ||
612 | |||
613 | return 0; | ||
614 | } | ||
615 | |||
616 | /** | ||
617 | * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode | ||
618 | * @clk: pointer to a DPLL struct clk | ||
619 | * | ||
620 | * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock. | ||
621 | * The choice of modes depends on the DPLL's programmed rate: if it is | ||
622 | * the same as the DPLL's parent clock, it will enter bypass; | ||
623 | * otherwise, it will enter lock. This code will wait for the DPLL to | ||
624 | * indicate readiness before returning, unless the DPLL takes too long | ||
625 | * to enter the target state. Intended to be used as the struct clk's | ||
626 | * enable function. If DPLL3 was passed in, or the DPLL does not | ||
627 | * support low-power stop, or if the DPLL took too long to enter | ||
628 | * bypass or lock, return -EINVAL; otherwise, return 0. | ||
629 | */ | ||
630 | static int omap3_noncore_dpll_enable(struct clk *clk) | ||
631 | { | ||
632 | int r; | ||
633 | struct dpll_data *dd; | ||
634 | |||
635 | if (clk == &dpll3_ck) | ||
636 | return -EINVAL; | ||
637 | |||
638 | dd = clk->dpll_data; | ||
639 | if (!dd) | ||
640 | return -EINVAL; | ||
641 | |||
642 | if (clk->rate == dd->clk_bypass->rate) { | ||
643 | WARN_ON(clk->parent != dd->clk_bypass); | ||
644 | r = _omap3_noncore_dpll_bypass(clk); | ||
645 | } else { | ||
646 | WARN_ON(clk->parent != dd->clk_ref); | ||
647 | r = _omap3_noncore_dpll_lock(clk); | ||
648 | } | ||
649 | /* FIXME: this is dubious - if clk->rate has changed, what about propagating? */ | ||
650 | if (!r) | ||
651 | clk->rate = omap2_get_dpll_rate(clk); | ||
652 | |||
653 | return r; | ||
654 | } | ||
655 | |||
656 | /** | ||
657 | * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode | ||
658 | * @clk: pointer to a DPLL struct clk | ||
659 | * | ||
660 | * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock. | ||
661 | * The choice of modes depends on the DPLL's programmed rate: if it is | ||
662 | * the same as the DPLL's parent clock, it will enter bypass; | ||
663 | * otherwise, it will enter lock. This code will wait for the DPLL to | ||
664 | * indicate readiness before returning, unless the DPLL takes too long | ||
665 | * to enter the target state. Intended to be used as the struct clk's | ||
666 | * enable function. If DPLL3 was passed in, or the DPLL does not | ||
667 | * support low-power stop, or if the DPLL took too long to enter | ||
668 | * bypass or lock, return -EINVAL; otherwise, return 0. | ||
669 | */ | ||
670 | static void omap3_noncore_dpll_disable(struct clk *clk) | ||
671 | { | ||
672 | if (clk == &dpll3_ck) | ||
673 | return; | ||
674 | |||
675 | _omap3_noncore_dpll_stop(clk); | ||
676 | } | ||
677 | |||
678 | |||
679 | /* Non-CORE DPLL rate set code */ | ||
680 | |||
681 | /* | ||
682 | * omap3_noncore_dpll_program - set non-core DPLL M,N values directly | ||
683 | * @clk: struct clk * of DPLL to set | ||
684 | * @m: DPLL multiplier to set | ||
685 | * @n: DPLL divider to set | ||
686 | * @freqsel: FREQSEL value to set | ||
687 | * | ||
688 | * Program the DPLL with the supplied M, N values, and wait for the DPLL to | ||
689 | * lock.. Returns -EINVAL upon error, or 0 upon success. | ||
690 | */ | ||
691 | static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel) | ||
692 | { | ||
693 | struct dpll_data *dd = clk->dpll_data; | ||
694 | u32 v; | ||
695 | |||
696 | /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */ | ||
697 | _omap3_noncore_dpll_bypass(clk); | ||
698 | |||
699 | /* Set jitter correction */ | ||
700 | v = __raw_readl(dd->control_reg); | ||
701 | v &= ~dd->freqsel_mask; | ||
702 | v |= freqsel << __ffs(dd->freqsel_mask); | ||
703 | __raw_writel(v, dd->control_reg); | ||
704 | |||
705 | /* Set DPLL multiplier, divider */ | ||
706 | v = __raw_readl(dd->mult_div1_reg); | ||
707 | v &= ~(dd->mult_mask | dd->div1_mask); | ||
708 | v |= m << __ffs(dd->mult_mask); | ||
709 | v |= (n - 1) << __ffs(dd->div1_mask); | ||
710 | __raw_writel(v, dd->mult_div1_reg); | ||
711 | |||
712 | /* We let the clock framework set the other output dividers later */ | ||
713 | |||
714 | /* REVISIT: Set ramp-up delay? */ | ||
715 | |||
716 | _omap3_noncore_dpll_lock(clk); | ||
717 | |||
718 | return 0; | ||
719 | } | ||
720 | |||
721 | /** | ||
722 | * omap3_noncore_dpll_set_rate - set non-core DPLL rate | ||
723 | * @clk: struct clk * of DPLL to set | ||
724 | * @rate: rounded target rate | ||
725 | * | ||
726 | * Set the DPLL CLKOUT to the target rate. If the DPLL can enter | ||
727 | * low-power bypass, and the target rate is the bypass source clock | ||
728 | * rate, then configure the DPLL for bypass. Otherwise, round the | ||
729 | * target rate if it hasn't been done already, then program and lock | ||
730 | * the DPLL. Returns -EINVAL upon error, or 0 upon success. | ||
731 | */ | ||
732 | static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate) | ||
733 | { | ||
734 | struct clk *new_parent = NULL; | ||
735 | u16 freqsel; | ||
736 | struct dpll_data *dd; | ||
737 | int ret; | ||
738 | |||
739 | if (!clk || !rate) | ||
740 | return -EINVAL; | ||
741 | |||
742 | dd = clk->dpll_data; | ||
743 | if (!dd) | ||
744 | return -EINVAL; | ||
745 | |||
746 | if (rate == omap2_get_dpll_rate(clk)) | ||
747 | return 0; | ||
748 | |||
749 | /* | ||
750 | * Ensure both the bypass and ref clocks are enabled prior to | ||
751 | * doing anything; we need the bypass clock running to reprogram | ||
752 | * the DPLL. | ||
753 | */ | ||
754 | omap2_clk_enable(dd->clk_bypass); | ||
755 | omap2_clk_enable(dd->clk_ref); | ||
756 | |||
757 | if (dd->clk_bypass->rate == rate && | ||
758 | (clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) { | ||
759 | pr_debug("clock: %s: set rate: entering bypass.\n", clk->name); | ||
760 | |||
761 | ret = _omap3_noncore_dpll_bypass(clk); | ||
762 | if (!ret) | ||
763 | new_parent = dd->clk_bypass; | ||
764 | } else { | ||
765 | if (dd->last_rounded_rate != rate) | ||
766 | omap2_dpll_round_rate(clk, rate); | ||
767 | |||
768 | if (dd->last_rounded_rate == 0) | ||
769 | return -EINVAL; | ||
770 | |||
771 | freqsel = _omap3_dpll_compute_freqsel(clk, dd->last_rounded_n); | ||
772 | if (!freqsel) | ||
773 | WARN_ON(1); | ||
774 | |||
775 | pr_debug("clock: %s: set rate: locking rate to %lu.\n", | ||
776 | clk->name, rate); | ||
777 | |||
778 | ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m, | ||
779 | dd->last_rounded_n, freqsel); | ||
780 | if (!ret) | ||
781 | new_parent = dd->clk_ref; | ||
782 | } | ||
783 | if (!ret) { | ||
784 | /* | ||
785 | * Switch the parent clock in the heirarchy, and make sure | ||
786 | * that the new parent's usecount is correct. Note: we | ||
787 | * enable the new parent before disabling the old to avoid | ||
788 | * any unnecessary hardware disable->enable transitions. | ||
789 | */ | ||
790 | if (clk->usecount) { | ||
791 | omap2_clk_enable(new_parent); | ||
792 | omap2_clk_disable(clk->parent); | ||
793 | } | ||
794 | clk_reparent(clk, new_parent); | ||
795 | clk->rate = rate; | ||
796 | } | ||
797 | omap2_clk_disable(dd->clk_ref); | ||
798 | omap2_clk_disable(dd->clk_bypass); | ||
799 | 145 | ||
800 | return 0; | 146 | const struct clkops clkops_noncore_dpll_ops = { |
801 | } | 147 | .enable = omap3_noncore_dpll_enable, |
148 | .disable = omap3_noncore_dpll_disable, | ||
149 | }; | ||
802 | 150 | ||
803 | static int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate) | 151 | int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate) |
804 | { | 152 | { |
805 | /* | 153 | /* |
806 | * According to the 12-5 CDP code from TI, "Limitation 2.5" | 154 | * According to the 12-5 CDP code from TI, "Limitation 2.5" |
@@ -831,12 +179,12 @@ static int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate) | |||
831 | * Program the DPLL M2 divider with the rounded target rate. Returns | 179 | * Program the DPLL M2 divider with the rounded target rate. Returns |
832 | * -EINVAL upon error, or 0 upon success. | 180 | * -EINVAL upon error, or 0 upon success. |
833 | */ | 181 | */ |
834 | static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) | 182 | int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) |
835 | { | 183 | { |
836 | u32 new_div = 0; | 184 | u32 new_div = 0; |
837 | u32 unlock_dll = 0; | 185 | u32 unlock_dll = 0; |
838 | u32 c; | 186 | u32 c; |
839 | unsigned long validrate, sdrcrate, mpurate; | 187 | unsigned long validrate, sdrcrate, _mpurate; |
840 | struct omap_sdrc_params *sdrc_cs0; | 188 | struct omap_sdrc_params *sdrc_cs0; |
841 | struct omap_sdrc_params *sdrc_cs1; | 189 | struct omap_sdrc_params *sdrc_cs1; |
842 | int ret; | 190 | int ret; |
@@ -844,14 +192,11 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) | |||
844 | if (!clk || !rate) | 192 | if (!clk || !rate) |
845 | return -EINVAL; | 193 | return -EINVAL; |
846 | 194 | ||
847 | if (clk != &dpll3_m2_ck) | ||
848 | return -EINVAL; | ||
849 | |||
850 | validrate = omap2_clksel_round_rate_div(clk, rate, &new_div); | 195 | validrate = omap2_clksel_round_rate_div(clk, rate, &new_div); |
851 | if (validrate != rate) | 196 | if (validrate != rate) |
852 | return -EINVAL; | 197 | return -EINVAL; |
853 | 198 | ||
854 | sdrcrate = sdrc_ick.rate; | 199 | sdrcrate = sdrc_ick_p->rate; |
855 | if (rate > clk->rate) | 200 | if (rate > clk->rate) |
856 | sdrcrate <<= ((rate / clk->rate) >> 1); | 201 | sdrcrate <<= ((rate / clk->rate) >> 1); |
857 | else | 202 | else |
@@ -869,8 +214,8 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) | |||
869 | /* | 214 | /* |
870 | * XXX This only needs to be done when the CPU frequency changes | 215 | * XXX This only needs to be done when the CPU frequency changes |
871 | */ | 216 | */ |
872 | mpurate = arm_fck.rate / CYCLES_PER_MHZ; | 217 | _mpurate = arm_fck_p->rate / CYCLES_PER_MHZ; |
873 | c = (mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT; | 218 | c = (_mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT; |
874 | c += 1; /* for safety */ | 219 | c += 1; /* for safety */ |
875 | c *= SDRC_MPURATE_LOOPS; | 220 | c *= SDRC_MPURATE_LOOPS; |
876 | c >>= SDRC_MPURATE_SCALE; | 221 | c >>= SDRC_MPURATE_SCALE; |
@@ -906,129 +251,6 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) | |||
906 | return 0; | 251 | return 0; |
907 | } | 252 | } |
908 | 253 | ||
909 | |||
910 | static const struct clkops clkops_noncore_dpll_ops = { | ||
911 | .enable = &omap3_noncore_dpll_enable, | ||
912 | .disable = &omap3_noncore_dpll_disable, | ||
913 | }; | ||
914 | |||
915 | /* DPLL autoidle read/set code */ | ||
916 | |||
917 | |||
918 | /** | ||
919 | * omap3_dpll_autoidle_read - read a DPLL's autoidle bits | ||
920 | * @clk: struct clk * of the DPLL to read | ||
921 | * | ||
922 | * Return the DPLL's autoidle bits, shifted down to bit 0. Returns | ||
923 | * -EINVAL if passed a null pointer or if the struct clk does not | ||
924 | * appear to refer to a DPLL. | ||
925 | */ | ||
926 | static u32 omap3_dpll_autoidle_read(struct clk *clk) | ||
927 | { | ||
928 | const struct dpll_data *dd; | ||
929 | u32 v; | ||
930 | |||
931 | if (!clk || !clk->dpll_data) | ||
932 | return -EINVAL; | ||
933 | |||
934 | dd = clk->dpll_data; | ||
935 | |||
936 | v = __raw_readl(dd->autoidle_reg); | ||
937 | v &= dd->autoidle_mask; | ||
938 | v >>= __ffs(dd->autoidle_mask); | ||
939 | |||
940 | return v; | ||
941 | } | ||
942 | |||
943 | /** | ||
944 | * omap3_dpll_allow_idle - enable DPLL autoidle bits | ||
945 | * @clk: struct clk * of the DPLL to operate on | ||
946 | * | ||
947 | * Enable DPLL automatic idle control. This automatic idle mode | ||
948 | * switching takes effect only when the DPLL is locked, at least on | ||
949 | * OMAP3430. The DPLL will enter low-power stop when its downstream | ||
950 | * clocks are gated. No return value. | ||
951 | */ | ||
952 | static void omap3_dpll_allow_idle(struct clk *clk) | ||
953 | { | ||
954 | const struct dpll_data *dd; | ||
955 | u32 v; | ||
956 | |||
957 | if (!clk || !clk->dpll_data) | ||
958 | return; | ||
959 | |||
960 | dd = clk->dpll_data; | ||
961 | |||
962 | /* | ||
963 | * REVISIT: CORE DPLL can optionally enter low-power bypass | ||
964 | * by writing 0x5 instead of 0x1. Add some mechanism to | ||
965 | * optionally enter this mode. | ||
966 | */ | ||
967 | v = __raw_readl(dd->autoidle_reg); | ||
968 | v &= ~dd->autoidle_mask; | ||
969 | v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask); | ||
970 | __raw_writel(v, dd->autoidle_reg); | ||
971 | } | ||
972 | |||
973 | /** | ||
974 | * omap3_dpll_deny_idle - prevent DPLL from automatically idling | ||
975 | * @clk: struct clk * of the DPLL to operate on | ||
976 | * | ||
977 | * Disable DPLL automatic idle control. No return value. | ||
978 | */ | ||
979 | static void omap3_dpll_deny_idle(struct clk *clk) | ||
980 | { | ||
981 | const struct dpll_data *dd; | ||
982 | u32 v; | ||
983 | |||
984 | if (!clk || !clk->dpll_data) | ||
985 | return; | ||
986 | |||
987 | dd = clk->dpll_data; | ||
988 | |||
989 | v = __raw_readl(dd->autoidle_reg); | ||
990 | v &= ~dd->autoidle_mask; | ||
991 | v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask); | ||
992 | __raw_writel(v, dd->autoidle_reg); | ||
993 | } | ||
994 | |||
995 | /* Clock control for DPLL outputs */ | ||
996 | |||
997 | /** | ||
998 | * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate | ||
999 | * @clk: DPLL output struct clk | ||
1000 | * | ||
1001 | * Using parent clock DPLL data, look up DPLL state. If locked, set our | ||
1002 | * rate to the dpll_clk * 2; otherwise, just use dpll_clk. | ||
1003 | */ | ||
1004 | static unsigned long omap3_clkoutx2_recalc(struct clk *clk) | ||
1005 | { | ||
1006 | const struct dpll_data *dd; | ||
1007 | unsigned long rate; | ||
1008 | u32 v; | ||
1009 | struct clk *pclk; | ||
1010 | |||
1011 | /* Walk up the parents of clk, looking for a DPLL */ | ||
1012 | pclk = clk->parent; | ||
1013 | while (pclk && !pclk->dpll_data) | ||
1014 | pclk = pclk->parent; | ||
1015 | |||
1016 | /* clk does not have a DPLL as a parent? */ | ||
1017 | WARN_ON(!pclk); | ||
1018 | |||
1019 | dd = pclk->dpll_data; | ||
1020 | |||
1021 | WARN_ON(!dd->enable_mask); | ||
1022 | |||
1023 | v = __raw_readl(dd->control_reg) & dd->enable_mask; | ||
1024 | v >>= __ffs(dd->enable_mask); | ||
1025 | if (v != OMAP3XXX_EN_DPLL_LOCKED) | ||
1026 | rate = clk->parent->rate; | ||
1027 | else | ||
1028 | rate = clk->parent->rate * 2; | ||
1029 | return rate; | ||
1030 | } | ||
1031 | |||
1032 | /* Common clock code */ | 254 | /* Common clock code */ |
1033 | 255 | ||
1034 | /* | 256 | /* |
@@ -1037,7 +259,7 @@ static unsigned long omap3_clkoutx2_recalc(struct clk *clk) | |||
1037 | */ | 259 | */ |
1038 | #if defined(CONFIG_ARCH_OMAP3) | 260 | #if defined(CONFIG_ARCH_OMAP3) |
1039 | 261 | ||
1040 | static struct clk_functions omap2_clk_functions = { | 262 | struct clk_functions omap2_clk_functions = { |
1041 | .clk_enable = omap2_clk_enable, | 263 | .clk_enable = omap2_clk_enable, |
1042 | .clk_disable = omap2_clk_disable, | 264 | .clk_disable = omap2_clk_disable, |
1043 | .clk_round_rate = omap2_clk_round_rate, | 265 | .clk_round_rate = omap2_clk_round_rate, |
@@ -1063,7 +285,7 @@ void omap2_clk_prepare_for_reboot(void) | |||
1063 | #endif | 285 | #endif |
1064 | } | 286 | } |
1065 | 287 | ||
1066 | static void omap3_clk_lock_dpll5(void) | 288 | void omap3_clk_lock_dpll5(void) |
1067 | { | 289 | { |
1068 | struct clk *dpll5_clk; | 290 | struct clk *dpll5_clk; |
1069 | struct clk *dpll5_m2_clk; | 291 | struct clk *dpll5_m2_clk; |
@@ -1093,19 +315,32 @@ static void omap3_clk_lock_dpll5(void) | |||
1093 | */ | 315 | */ |
1094 | static int __init omap2_clk_arch_init(void) | 316 | static int __init omap2_clk_arch_init(void) |
1095 | { | 317 | { |
318 | struct clk *osc_sys_ck, *dpll1_ck, *arm_fck, *core_ck; | ||
319 | unsigned long osc_sys_rate; | ||
320 | |||
1096 | if (!mpurate) | 321 | if (!mpurate) |
1097 | return -EINVAL; | 322 | return -EINVAL; |
1098 | 323 | ||
324 | /* XXX test these for success */ | ||
325 | dpll1_ck = clk_get(NULL, "dpll1_ck"); | ||
326 | arm_fck = clk_get(NULL, "arm_fck"); | ||
327 | core_ck = clk_get(NULL, "core_ck"); | ||
328 | osc_sys_ck = clk_get(NULL, "osc_sys_ck"); | ||
329 | |||
1099 | /* REVISIT: not yet ready for 343x */ | 330 | /* REVISIT: not yet ready for 343x */ |
1100 | if (clk_set_rate(&dpll1_ck, mpurate)) | 331 | if (clk_set_rate(dpll1_ck, mpurate)) |
1101 | printk(KERN_ERR "*** Unable to set MPU rate\n"); | 332 | printk(KERN_ERR "*** Unable to set MPU rate\n"); |
1102 | 333 | ||
1103 | recalculate_root_clocks(); | 334 | recalculate_root_clocks(); |
1104 | 335 | ||
1105 | printk(KERN_INFO "Switched to new clocking rate (Crystal/Core/MPU): " | 336 | osc_sys_rate = clk_get_rate(osc_sys_ck); |
1106 | "%ld.%01ld/%ld/%ld MHz\n", | 337 | |
1107 | (osc_sys_ck.rate / 1000000), ((osc_sys_ck.rate / 100000) % 10), | 338 | pr_info("Switched to new clocking rate (Crystal/Core/MPU): " |
1108 | (core_ck.rate / 1000000), (arm_fck.rate / 1000000)) ; | 339 | "%ld.%01ld/%ld/%ld MHz\n", |
340 | (osc_sys_rate / 1000000), | ||
341 | ((osc_sys_rate / 100000) % 10), | ||
342 | (clk_get_rate(core_ck) / 1000000), | ||
343 | (clk_get_rate(arm_fck) / 1000000)); | ||
1109 | 344 | ||
1110 | calibrate_delay(); | 345 | calibrate_delay(); |
1111 | 346 | ||
@@ -1113,83 +348,7 @@ static int __init omap2_clk_arch_init(void) | |||
1113 | } | 348 | } |
1114 | arch_initcall(omap2_clk_arch_init); | 349 | arch_initcall(omap2_clk_arch_init); |
1115 | 350 | ||
1116 | int __init omap2_clk_init(void) | ||
1117 | { | ||
1118 | /* struct prcm_config *prcm; */ | ||
1119 | struct omap_clk *c; | ||
1120 | /* u32 clkrate; */ | ||
1121 | u32 cpu_clkflg; | ||
1122 | |||
1123 | if (cpu_is_omap34xx()) { | ||
1124 | cpu_mask = RATE_IN_343X; | ||
1125 | cpu_clkflg = CK_343X; | ||
1126 | |||
1127 | /* | ||
1128 | * Update this if there are further clock changes between ES2 | ||
1129 | * and production parts | ||
1130 | */ | ||
1131 | if (omap_rev() == OMAP3430_REV_ES1_0) { | ||
1132 | /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */ | ||
1133 | cpu_clkflg |= CK_3430ES1; | ||
1134 | } else { | ||
1135 | cpu_mask |= RATE_IN_3430ES2; | ||
1136 | cpu_clkflg |= CK_3430ES2; | ||
1137 | } | ||
1138 | } | ||
1139 | |||
1140 | clk_init(&omap2_clk_functions); | ||
1141 | |||
1142 | for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++) | ||
1143 | clk_preinit(c->lk.clk); | ||
1144 | 351 | ||
1145 | for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++) | ||
1146 | if (c->cpu & cpu_clkflg) { | ||
1147 | clkdev_add(&c->lk); | ||
1148 | clk_register(c->lk.clk); | ||
1149 | omap2_init_clk_clkdm(c->lk.clk); | ||
1150 | } | ||
1151 | |||
1152 | /* REVISIT: Not yet ready for OMAP3 */ | ||
1153 | #if 0 | ||
1154 | /* Check the MPU rate set by bootloader */ | ||
1155 | clkrate = omap2_get_dpll_rate_24xx(&dpll_ck); | ||
1156 | for (prcm = rate_table; prcm->mpu_speed; prcm++) { | ||
1157 | if (!(prcm->flags & cpu_mask)) | ||
1158 | continue; | ||
1159 | if (prcm->xtal_speed != sys_ck.rate) | ||
1160 | continue; | ||
1161 | if (prcm->dpll_speed <= clkrate) | ||
1162 | break; | ||
1163 | } | ||
1164 | curr_prcm_set = prcm; | ||
1165 | #endif | 352 | #endif |
1166 | 353 | ||
1167 | recalculate_root_clocks(); | ||
1168 | |||
1169 | printk(KERN_INFO "Clocking rate (Crystal/Core/MPU): " | ||
1170 | "%ld.%01ld/%ld/%ld MHz\n", | ||
1171 | (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10, | ||
1172 | (core_ck.rate / 1000000), (arm_fck.rate / 1000000)); | ||
1173 | |||
1174 | /* | ||
1175 | * Only enable those clocks we will need, let the drivers | ||
1176 | * enable other clocks as necessary | ||
1177 | */ | ||
1178 | clk_enable_init_clocks(); | ||
1179 | |||
1180 | /* | ||
1181 | * Lock DPLL5 and put it in autoidle. | ||
1182 | */ | ||
1183 | if (omap_rev() >= OMAP3430_REV_ES2_0) | ||
1184 | omap3_clk_lock_dpll5(); | ||
1185 | 354 | ||
1186 | /* Avoid sleeping during omap2_clk_prepare_for_reboot() */ | ||
1187 | /* REVISIT: not yet ready for 343x */ | ||
1188 | #if 0 | ||
1189 | vclk = clk_get(NULL, "virt_prcm_set"); | ||
1190 | sclk = clk_get(NULL, "sys_ck"); | ||
1191 | #endif | ||
1192 | return 0; | ||
1193 | } | ||
1194 | |||
1195 | #endif | ||
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h index 8fe1bcb23dd9..9a2c07eac9ad 100644 --- a/arch/arm/mach-omap2/clock34xx.h +++ b/arch/arm/mach-omap2/clock34xx.h | |||
@@ -1,2993 +1,24 @@ | |||
1 | /* | 1 | /* |
2 | * OMAP3 clock framework | 2 | * OMAP3 clock function prototypes and macros |
3 | * | 3 | * |
4 | * Copyright (C) 2007-2008 Texas Instruments, Inc. | 4 | * Copyright (C) 2007-2009 Texas Instruments, Inc. |
5 | * Copyright (C) 2007-2008 Nokia Corporation | 5 | * Copyright (C) 2007-2009 Nokia Corporation |
6 | * | ||
7 | * Written by Paul Walmsley | ||
8 | * With many device clock fixes by Kevin Hilman and Jouni Högander | ||
9 | * DPLL bypass clock support added by Roman Tereshonkov | ||
10 | * | ||
11 | */ | ||
12 | |||
13 | /* | ||
14 | * Virtual clocks are introduced as convenient tools. | ||
15 | * They are sources for other clocks and not supposed | ||
16 | * to be requested from drivers directly. | ||
17 | */ | ||
18 | |||
19 | #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H | ||
20 | #define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H | ||
21 | |||
22 | #include <plat/control.h> | ||
23 | |||
24 | #include "clock.h" | ||
25 | #include "cm.h" | ||
26 | #include "cm-regbits-34xx.h" | ||
27 | #include "prm.h" | ||
28 | #include "prm-regbits-34xx.h" | ||
29 | |||
30 | #define OMAP_CM_REGADDR OMAP34XX_CM_REGADDR | ||
31 | |||
32 | static unsigned long omap3_dpll_recalc(struct clk *clk); | ||
33 | static unsigned long omap3_clkoutx2_recalc(struct clk *clk); | ||
34 | static void omap3_dpll_allow_idle(struct clk *clk); | ||
35 | static void omap3_dpll_deny_idle(struct clk *clk); | ||
36 | static u32 omap3_dpll_autoidle_read(struct clk *clk); | ||
37 | static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate); | ||
38 | static int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate); | ||
39 | static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate); | ||
40 | |||
41 | /* Maximum DPLL multiplier, divider values for OMAP3 */ | ||
42 | #define OMAP3_MAX_DPLL_MULT 2048 | ||
43 | #define OMAP3_MAX_DPLL_DIV 128 | ||
44 | |||
45 | /* | ||
46 | * DPLL1 supplies clock to the MPU. | ||
47 | * DPLL2 supplies clock to the IVA2. | ||
48 | * DPLL3 supplies CORE domain clocks. | ||
49 | * DPLL4 supplies peripheral clocks. | ||
50 | * DPLL5 supplies other peripheral clocks (USBHOST, USIM). | ||
51 | */ | ||
52 | |||
53 | /* Forward declarations for DPLL bypass clocks */ | ||
54 | static struct clk dpll1_fck; | ||
55 | static struct clk dpll2_fck; | ||
56 | |||
57 | /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */ | ||
58 | #define DPLL_LOW_POWER_STOP 0x1 | ||
59 | #define DPLL_LOW_POWER_BYPASS 0x5 | ||
60 | #define DPLL_LOCKED 0x7 | ||
61 | |||
62 | /* PRM CLOCKS */ | ||
63 | |||
64 | /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */ | ||
65 | static struct clk omap_32k_fck = { | ||
66 | .name = "omap_32k_fck", | ||
67 | .ops = &clkops_null, | ||
68 | .rate = 32768, | ||
69 | .flags = RATE_FIXED, | ||
70 | }; | ||
71 | |||
72 | static struct clk secure_32k_fck = { | ||
73 | .name = "secure_32k_fck", | ||
74 | .ops = &clkops_null, | ||
75 | .rate = 32768, | ||
76 | .flags = RATE_FIXED, | ||
77 | }; | ||
78 | |||
79 | /* Virtual source clocks for osc_sys_ck */ | ||
80 | static struct clk virt_12m_ck = { | ||
81 | .name = "virt_12m_ck", | ||
82 | .ops = &clkops_null, | ||
83 | .rate = 12000000, | ||
84 | .flags = RATE_FIXED, | ||
85 | }; | ||
86 | |||
87 | static struct clk virt_13m_ck = { | ||
88 | .name = "virt_13m_ck", | ||
89 | .ops = &clkops_null, | ||
90 | .rate = 13000000, | ||
91 | .flags = RATE_FIXED, | ||
92 | }; | ||
93 | |||
94 | static struct clk virt_16_8m_ck = { | ||
95 | .name = "virt_16_8m_ck", | ||
96 | .ops = &clkops_null, | ||
97 | .rate = 16800000, | ||
98 | .flags = RATE_FIXED, | ||
99 | }; | ||
100 | |||
101 | static struct clk virt_19_2m_ck = { | ||
102 | .name = "virt_19_2m_ck", | ||
103 | .ops = &clkops_null, | ||
104 | .rate = 19200000, | ||
105 | .flags = RATE_FIXED, | ||
106 | }; | ||
107 | |||
108 | static struct clk virt_26m_ck = { | ||
109 | .name = "virt_26m_ck", | ||
110 | .ops = &clkops_null, | ||
111 | .rate = 26000000, | ||
112 | .flags = RATE_FIXED, | ||
113 | }; | ||
114 | |||
115 | static struct clk virt_38_4m_ck = { | ||
116 | .name = "virt_38_4m_ck", | ||
117 | .ops = &clkops_null, | ||
118 | .rate = 38400000, | ||
119 | .flags = RATE_FIXED, | ||
120 | }; | ||
121 | |||
122 | static const struct clksel_rate osc_sys_12m_rates[] = { | ||
123 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
124 | { .div = 0 } | ||
125 | }; | ||
126 | |||
127 | static const struct clksel_rate osc_sys_13m_rates[] = { | ||
128 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
129 | { .div = 0 } | ||
130 | }; | ||
131 | |||
132 | static const struct clksel_rate osc_sys_16_8m_rates[] = { | ||
133 | { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE }, | ||
134 | { .div = 0 } | ||
135 | }; | ||
136 | |||
137 | static const struct clksel_rate osc_sys_19_2m_rates[] = { | ||
138 | { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
139 | { .div = 0 } | ||
140 | }; | ||
141 | |||
142 | static const struct clksel_rate osc_sys_26m_rates[] = { | ||
143 | { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
144 | { .div = 0 } | ||
145 | }; | ||
146 | |||
147 | static const struct clksel_rate osc_sys_38_4m_rates[] = { | ||
148 | { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
149 | { .div = 0 } | ||
150 | }; | ||
151 | |||
152 | static const struct clksel osc_sys_clksel[] = { | ||
153 | { .parent = &virt_12m_ck, .rates = osc_sys_12m_rates }, | ||
154 | { .parent = &virt_13m_ck, .rates = osc_sys_13m_rates }, | ||
155 | { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates }, | ||
156 | { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates }, | ||
157 | { .parent = &virt_26m_ck, .rates = osc_sys_26m_rates }, | ||
158 | { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates }, | ||
159 | { .parent = NULL }, | ||
160 | }; | ||
161 | |||
162 | /* Oscillator clock */ | ||
163 | /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */ | ||
164 | static struct clk osc_sys_ck = { | ||
165 | .name = "osc_sys_ck", | ||
166 | .ops = &clkops_null, | ||
167 | .init = &omap2_init_clksel_parent, | ||
168 | .clksel_reg = OMAP3430_PRM_CLKSEL, | ||
169 | .clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK, | ||
170 | .clksel = osc_sys_clksel, | ||
171 | /* REVISIT: deal with autoextclkmode? */ | ||
172 | .flags = RATE_FIXED, | ||
173 | .recalc = &omap2_clksel_recalc, | ||
174 | }; | ||
175 | |||
176 | static const struct clksel_rate div2_rates[] = { | ||
177 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
178 | { .div = 2, .val = 2, .flags = RATE_IN_343X }, | ||
179 | { .div = 0 } | ||
180 | }; | ||
181 | |||
182 | static const struct clksel sys_clksel[] = { | ||
183 | { .parent = &osc_sys_ck, .rates = div2_rates }, | ||
184 | { .parent = NULL } | ||
185 | }; | ||
186 | |||
187 | /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */ | ||
188 | /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */ | ||
189 | static struct clk sys_ck = { | ||
190 | .name = "sys_ck", | ||
191 | .ops = &clkops_null, | ||
192 | .parent = &osc_sys_ck, | ||
193 | .init = &omap2_init_clksel_parent, | ||
194 | .clksel_reg = OMAP3430_PRM_CLKSRC_CTRL, | ||
195 | .clksel_mask = OMAP_SYSCLKDIV_MASK, | ||
196 | .clksel = sys_clksel, | ||
197 | .recalc = &omap2_clksel_recalc, | ||
198 | }; | ||
199 | |||
200 | static struct clk sys_altclk = { | ||
201 | .name = "sys_altclk", | ||
202 | .ops = &clkops_null, | ||
203 | }; | ||
204 | |||
205 | /* Optional external clock input for some McBSPs */ | ||
206 | static struct clk mcbsp_clks = { | ||
207 | .name = "mcbsp_clks", | ||
208 | .ops = &clkops_null, | ||
209 | }; | ||
210 | |||
211 | /* PRM EXTERNAL CLOCK OUTPUT */ | ||
212 | |||
213 | static struct clk sys_clkout1 = { | ||
214 | .name = "sys_clkout1", | ||
215 | .ops = &clkops_omap2_dflt, | ||
216 | .parent = &osc_sys_ck, | ||
217 | .enable_reg = OMAP3430_PRM_CLKOUT_CTRL, | ||
218 | .enable_bit = OMAP3430_CLKOUT_EN_SHIFT, | ||
219 | .recalc = &followparent_recalc, | ||
220 | }; | ||
221 | |||
222 | /* DPLLS */ | ||
223 | |||
224 | /* CM CLOCKS */ | ||
225 | |||
226 | static const struct clksel_rate div16_dpll_rates[] = { | ||
227 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
228 | { .div = 2, .val = 2, .flags = RATE_IN_343X }, | ||
229 | { .div = 3, .val = 3, .flags = RATE_IN_343X }, | ||
230 | { .div = 4, .val = 4, .flags = RATE_IN_343X }, | ||
231 | { .div = 5, .val = 5, .flags = RATE_IN_343X }, | ||
232 | { .div = 6, .val = 6, .flags = RATE_IN_343X }, | ||
233 | { .div = 7, .val = 7, .flags = RATE_IN_343X }, | ||
234 | { .div = 8, .val = 8, .flags = RATE_IN_343X }, | ||
235 | { .div = 9, .val = 9, .flags = RATE_IN_343X }, | ||
236 | { .div = 10, .val = 10, .flags = RATE_IN_343X }, | ||
237 | { .div = 11, .val = 11, .flags = RATE_IN_343X }, | ||
238 | { .div = 12, .val = 12, .flags = RATE_IN_343X }, | ||
239 | { .div = 13, .val = 13, .flags = RATE_IN_343X }, | ||
240 | { .div = 14, .val = 14, .flags = RATE_IN_343X }, | ||
241 | { .div = 15, .val = 15, .flags = RATE_IN_343X }, | ||
242 | { .div = 16, .val = 16, .flags = RATE_IN_343X }, | ||
243 | { .div = 0 } | ||
244 | }; | ||
245 | |||
246 | /* DPLL1 */ | ||
247 | /* MPU clock source */ | ||
248 | /* Type: DPLL */ | ||
249 | static struct dpll_data dpll1_dd = { | ||
250 | .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), | ||
251 | .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK, | ||
252 | .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK, | ||
253 | .clk_bypass = &dpll1_fck, | ||
254 | .clk_ref = &sys_ck, | ||
255 | .freqsel_mask = OMAP3430_MPU_DPLL_FREQSEL_MASK, | ||
256 | .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL), | ||
257 | .enable_mask = OMAP3430_EN_MPU_DPLL_MASK, | ||
258 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), | ||
259 | .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT, | ||
260 | .recal_en_bit = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT, | ||
261 | .recal_st_bit = OMAP3430_MPU_DPLL_ST_SHIFT, | ||
262 | .autoidle_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL), | ||
263 | .autoidle_mask = OMAP3430_AUTO_MPU_DPLL_MASK, | ||
264 | .idlest_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), | ||
265 | .idlest_mask = OMAP3430_ST_MPU_CLK_MASK, | ||
266 | .max_multiplier = OMAP3_MAX_DPLL_MULT, | ||
267 | .min_divider = 1, | ||
268 | .max_divider = OMAP3_MAX_DPLL_DIV, | ||
269 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE | ||
270 | }; | ||
271 | |||
272 | static struct clk dpll1_ck = { | ||
273 | .name = "dpll1_ck", | ||
274 | .ops = &clkops_null, | ||
275 | .parent = &sys_ck, | ||
276 | .dpll_data = &dpll1_dd, | ||
277 | .round_rate = &omap2_dpll_round_rate, | ||
278 | .set_rate = &omap3_noncore_dpll_set_rate, | ||
279 | .clkdm_name = "dpll1_clkdm", | ||
280 | .recalc = &omap3_dpll_recalc, | ||
281 | }; | ||
282 | |||
283 | /* | ||
284 | * This virtual clock provides the CLKOUTX2 output from the DPLL if the | ||
285 | * DPLL isn't bypassed. | ||
286 | */ | ||
287 | static struct clk dpll1_x2_ck = { | ||
288 | .name = "dpll1_x2_ck", | ||
289 | .ops = &clkops_null, | ||
290 | .parent = &dpll1_ck, | ||
291 | .clkdm_name = "dpll1_clkdm", | ||
292 | .recalc = &omap3_clkoutx2_recalc, | ||
293 | }; | ||
294 | |||
295 | /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */ | ||
296 | static const struct clksel div16_dpll1_x2m2_clksel[] = { | ||
297 | { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates }, | ||
298 | { .parent = NULL } | ||
299 | }; | ||
300 | |||
301 | /* | ||
302 | * Does not exist in the TRM - needed to separate the M2 divider from | ||
303 | * bypass selection in mpu_ck | ||
304 | */ | ||
305 | static struct clk dpll1_x2m2_ck = { | ||
306 | .name = "dpll1_x2m2_ck", | ||
307 | .ops = &clkops_null, | ||
308 | .parent = &dpll1_x2_ck, | ||
309 | .init = &omap2_init_clksel_parent, | ||
310 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL), | ||
311 | .clksel_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK, | ||
312 | .clksel = div16_dpll1_x2m2_clksel, | ||
313 | .clkdm_name = "dpll1_clkdm", | ||
314 | .recalc = &omap2_clksel_recalc, | ||
315 | }; | ||
316 | |||
317 | /* DPLL2 */ | ||
318 | /* IVA2 clock source */ | ||
319 | /* Type: DPLL */ | ||
320 | |||
321 | static struct dpll_data dpll2_dd = { | ||
322 | .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), | ||
323 | .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK, | ||
324 | .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK, | ||
325 | .clk_bypass = &dpll2_fck, | ||
326 | .clk_ref = &sys_ck, | ||
327 | .freqsel_mask = OMAP3430_IVA2_DPLL_FREQSEL_MASK, | ||
328 | .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL), | ||
329 | .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK, | ||
330 | .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) | | ||
331 | (1 << DPLL_LOW_POWER_BYPASS), | ||
332 | .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT, | ||
333 | .recal_en_bit = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT, | ||
334 | .recal_st_bit = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT, | ||
335 | .autoidle_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL), | ||
336 | .autoidle_mask = OMAP3430_AUTO_IVA2_DPLL_MASK, | ||
337 | .idlest_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL), | ||
338 | .idlest_mask = OMAP3430_ST_IVA2_CLK_MASK, | ||
339 | .max_multiplier = OMAP3_MAX_DPLL_MULT, | ||
340 | .min_divider = 1, | ||
341 | .max_divider = OMAP3_MAX_DPLL_DIV, | ||
342 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE | ||
343 | }; | ||
344 | |||
345 | static struct clk dpll2_ck = { | ||
346 | .name = "dpll2_ck", | ||
347 | .ops = &clkops_noncore_dpll_ops, | ||
348 | .parent = &sys_ck, | ||
349 | .dpll_data = &dpll2_dd, | ||
350 | .round_rate = &omap2_dpll_round_rate, | ||
351 | .set_rate = &omap3_noncore_dpll_set_rate, | ||
352 | .clkdm_name = "dpll2_clkdm", | ||
353 | .recalc = &omap3_dpll_recalc, | ||
354 | }; | ||
355 | |||
356 | static const struct clksel div16_dpll2_m2x2_clksel[] = { | ||
357 | { .parent = &dpll2_ck, .rates = div16_dpll_rates }, | ||
358 | { .parent = NULL } | ||
359 | }; | ||
360 | |||
361 | /* | ||
362 | * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT | ||
363 | * or CLKOUTX2. CLKOUT seems most plausible. | ||
364 | */ | ||
365 | static struct clk dpll2_m2_ck = { | ||
366 | .name = "dpll2_m2_ck", | ||
367 | .ops = &clkops_null, | ||
368 | .parent = &dpll2_ck, | ||
369 | .init = &omap2_init_clksel_parent, | ||
370 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, | ||
371 | OMAP3430_CM_CLKSEL2_PLL), | ||
372 | .clksel_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK, | ||
373 | .clksel = div16_dpll2_m2x2_clksel, | ||
374 | .clkdm_name = "dpll2_clkdm", | ||
375 | .recalc = &omap2_clksel_recalc, | ||
376 | }; | ||
377 | |||
378 | /* | ||
379 | * DPLL3 | ||
380 | * Source clock for all interfaces and for some device fclks | ||
381 | * REVISIT: Also supports fast relock bypass - not included below | ||
382 | */ | ||
383 | static struct dpll_data dpll3_dd = { | ||
384 | .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | ||
385 | .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK, | ||
386 | .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK, | ||
387 | .clk_bypass = &sys_ck, | ||
388 | .clk_ref = &sys_ck, | ||
389 | .freqsel_mask = OMAP3430_CORE_DPLL_FREQSEL_MASK, | ||
390 | .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | ||
391 | .enable_mask = OMAP3430_EN_CORE_DPLL_MASK, | ||
392 | .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT, | ||
393 | .recal_en_bit = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT, | ||
394 | .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT, | ||
395 | .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE), | ||
396 | .autoidle_mask = OMAP3430_AUTO_CORE_DPLL_MASK, | ||
397 | .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), | ||
398 | .idlest_mask = OMAP3430_ST_CORE_CLK_MASK, | ||
399 | .max_multiplier = OMAP3_MAX_DPLL_MULT, | ||
400 | .min_divider = 1, | ||
401 | .max_divider = OMAP3_MAX_DPLL_DIV, | ||
402 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE | ||
403 | }; | ||
404 | |||
405 | static struct clk dpll3_ck = { | ||
406 | .name = "dpll3_ck", | ||
407 | .ops = &clkops_null, | ||
408 | .parent = &sys_ck, | ||
409 | .dpll_data = &dpll3_dd, | ||
410 | .round_rate = &omap2_dpll_round_rate, | ||
411 | .clkdm_name = "dpll3_clkdm", | ||
412 | .recalc = &omap3_dpll_recalc, | ||
413 | }; | ||
414 | |||
415 | /* | ||
416 | * This virtual clock provides the CLKOUTX2 output from the DPLL if the | ||
417 | * DPLL isn't bypassed | ||
418 | */ | ||
419 | static struct clk dpll3_x2_ck = { | ||
420 | .name = "dpll3_x2_ck", | ||
421 | .ops = &clkops_null, | ||
422 | .parent = &dpll3_ck, | ||
423 | .clkdm_name = "dpll3_clkdm", | ||
424 | .recalc = &omap3_clkoutx2_recalc, | ||
425 | }; | ||
426 | |||
427 | static const struct clksel_rate div31_dpll3_rates[] = { | ||
428 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
429 | { .div = 2, .val = 2, .flags = RATE_IN_343X }, | ||
430 | { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 }, | ||
431 | { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 }, | ||
432 | { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 }, | ||
433 | { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 }, | ||
434 | { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 }, | ||
435 | { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 }, | ||
436 | { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 }, | ||
437 | { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 }, | ||
438 | { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 }, | ||
439 | { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 }, | ||
440 | { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 }, | ||
441 | { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 }, | ||
442 | { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 }, | ||
443 | { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 }, | ||
444 | { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 }, | ||
445 | { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 }, | ||
446 | { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 }, | ||
447 | { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 }, | ||
448 | { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 }, | ||
449 | { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 }, | ||
450 | { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 }, | ||
451 | { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 }, | ||
452 | { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 }, | ||
453 | { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 }, | ||
454 | { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 }, | ||
455 | { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 }, | ||
456 | { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 }, | ||
457 | { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 }, | ||
458 | { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 }, | ||
459 | { .div = 0 }, | ||
460 | }; | ||
461 | |||
462 | static const struct clksel div31_dpll3m2_clksel[] = { | ||
463 | { .parent = &dpll3_ck, .rates = div31_dpll3_rates }, | ||
464 | { .parent = NULL } | ||
465 | }; | ||
466 | |||
467 | /* DPLL3 output M2 - primary control point for CORE speed */ | ||
468 | static struct clk dpll3_m2_ck = { | ||
469 | .name = "dpll3_m2_ck", | ||
470 | .ops = &clkops_null, | ||
471 | .parent = &dpll3_ck, | ||
472 | .init = &omap2_init_clksel_parent, | ||
473 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | ||
474 | .clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK, | ||
475 | .clksel = div31_dpll3m2_clksel, | ||
476 | .clkdm_name = "dpll3_clkdm", | ||
477 | .round_rate = &omap2_clksel_round_rate, | ||
478 | .set_rate = &omap3_core_dpll_m2_set_rate, | ||
479 | .recalc = &omap2_clksel_recalc, | ||
480 | }; | ||
481 | |||
482 | static struct clk core_ck = { | ||
483 | .name = "core_ck", | ||
484 | .ops = &clkops_null, | ||
485 | .parent = &dpll3_m2_ck, | ||
486 | .recalc = &followparent_recalc, | ||
487 | }; | ||
488 | |||
489 | static struct clk dpll3_m2x2_ck = { | ||
490 | .name = "dpll3_m2x2_ck", | ||
491 | .ops = &clkops_null, | ||
492 | .parent = &dpll3_m2_ck, | ||
493 | .clkdm_name = "dpll3_clkdm", | ||
494 | .recalc = &omap3_clkoutx2_recalc, | ||
495 | }; | ||
496 | |||
497 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | ||
498 | static const struct clksel div16_dpll3_clksel[] = { | ||
499 | { .parent = &dpll3_ck, .rates = div16_dpll_rates }, | ||
500 | { .parent = NULL } | ||
501 | }; | ||
502 | |||
503 | /* This virtual clock is the source for dpll3_m3x2_ck */ | ||
504 | static struct clk dpll3_m3_ck = { | ||
505 | .name = "dpll3_m3_ck", | ||
506 | .ops = &clkops_null, | ||
507 | .parent = &dpll3_ck, | ||
508 | .init = &omap2_init_clksel_parent, | ||
509 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | ||
510 | .clksel_mask = OMAP3430_DIV_DPLL3_MASK, | ||
511 | .clksel = div16_dpll3_clksel, | ||
512 | .clkdm_name = "dpll3_clkdm", | ||
513 | .recalc = &omap2_clksel_recalc, | ||
514 | }; | ||
515 | |||
516 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | ||
517 | static struct clk dpll3_m3x2_ck = { | ||
518 | .name = "dpll3_m3x2_ck", | ||
519 | .ops = &clkops_omap2_dflt_wait, | ||
520 | .parent = &dpll3_m3_ck, | ||
521 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | ||
522 | .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT, | ||
523 | .flags = INVERT_ENABLE, | ||
524 | .clkdm_name = "dpll3_clkdm", | ||
525 | .recalc = &omap3_clkoutx2_recalc, | ||
526 | }; | ||
527 | |||
528 | static struct clk emu_core_alwon_ck = { | ||
529 | .name = "emu_core_alwon_ck", | ||
530 | .ops = &clkops_null, | ||
531 | .parent = &dpll3_m3x2_ck, | ||
532 | .clkdm_name = "dpll3_clkdm", | ||
533 | .recalc = &followparent_recalc, | ||
534 | }; | ||
535 | |||
536 | /* DPLL4 */ | ||
537 | /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */ | ||
538 | /* Type: DPLL */ | ||
539 | static struct dpll_data dpll4_dd = { | ||
540 | .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2), | ||
541 | .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK, | ||
542 | .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK, | ||
543 | .clk_bypass = &sys_ck, | ||
544 | .clk_ref = &sys_ck, | ||
545 | .freqsel_mask = OMAP3430_PERIPH_DPLL_FREQSEL_MASK, | ||
546 | .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | ||
547 | .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK, | ||
548 | .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED), | ||
549 | .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT, | ||
550 | .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT, | ||
551 | .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT, | ||
552 | .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE), | ||
553 | .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK, | ||
554 | .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), | ||
555 | .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK, | ||
556 | .max_multiplier = OMAP3_MAX_DPLL_MULT, | ||
557 | .min_divider = 1, | ||
558 | .max_divider = OMAP3_MAX_DPLL_DIV, | ||
559 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE | ||
560 | }; | ||
561 | |||
562 | static struct clk dpll4_ck = { | ||
563 | .name = "dpll4_ck", | ||
564 | .ops = &clkops_noncore_dpll_ops, | ||
565 | .parent = &sys_ck, | ||
566 | .dpll_data = &dpll4_dd, | ||
567 | .round_rate = &omap2_dpll_round_rate, | ||
568 | .set_rate = &omap3_dpll4_set_rate, | ||
569 | .clkdm_name = "dpll4_clkdm", | ||
570 | .recalc = &omap3_dpll_recalc, | ||
571 | }; | ||
572 | |||
573 | /* | ||
574 | * This virtual clock provides the CLKOUTX2 output from the DPLL if the | ||
575 | * DPLL isn't bypassed -- | ||
576 | * XXX does this serve any downstream clocks? | ||
577 | */ | ||
578 | static struct clk dpll4_x2_ck = { | ||
579 | .name = "dpll4_x2_ck", | ||
580 | .ops = &clkops_null, | ||
581 | .parent = &dpll4_ck, | ||
582 | .clkdm_name = "dpll4_clkdm", | ||
583 | .recalc = &omap3_clkoutx2_recalc, | ||
584 | }; | ||
585 | |||
586 | static const struct clksel div16_dpll4_clksel[] = { | ||
587 | { .parent = &dpll4_ck, .rates = div16_dpll_rates }, | ||
588 | { .parent = NULL } | ||
589 | }; | ||
590 | |||
591 | /* This virtual clock is the source for dpll4_m2x2_ck */ | ||
592 | static struct clk dpll4_m2_ck = { | ||
593 | .name = "dpll4_m2_ck", | ||
594 | .ops = &clkops_null, | ||
595 | .parent = &dpll4_ck, | ||
596 | .init = &omap2_init_clksel_parent, | ||
597 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3), | ||
598 | .clksel_mask = OMAP3430_DIV_96M_MASK, | ||
599 | .clksel = div16_dpll4_clksel, | ||
600 | .clkdm_name = "dpll4_clkdm", | ||
601 | .recalc = &omap2_clksel_recalc, | ||
602 | }; | ||
603 | |||
604 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | ||
605 | static struct clk dpll4_m2x2_ck = { | ||
606 | .name = "dpll4_m2x2_ck", | ||
607 | .ops = &clkops_omap2_dflt_wait, | ||
608 | .parent = &dpll4_m2_ck, | ||
609 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | ||
610 | .enable_bit = OMAP3430_PWRDN_96M_SHIFT, | ||
611 | .flags = INVERT_ENABLE, | ||
612 | .clkdm_name = "dpll4_clkdm", | ||
613 | .recalc = &omap3_clkoutx2_recalc, | ||
614 | }; | ||
615 | |||
616 | /* | ||
617 | * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as | ||
618 | * PRM_96M_ALWON_(F)CLK. Two clocks then emerge from the PRM: | ||
619 | * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and | ||
620 | * CM_96K_(F)CLK. | ||
621 | */ | ||
622 | static struct clk omap_96m_alwon_fck = { | ||
623 | .name = "omap_96m_alwon_fck", | ||
624 | .ops = &clkops_null, | ||
625 | .parent = &dpll4_m2x2_ck, | ||
626 | .recalc = &followparent_recalc, | ||
627 | }; | ||
628 | |||
629 | static struct clk cm_96m_fck = { | ||
630 | .name = "cm_96m_fck", | ||
631 | .ops = &clkops_null, | ||
632 | .parent = &omap_96m_alwon_fck, | ||
633 | .recalc = &followparent_recalc, | ||
634 | }; | ||
635 | |||
636 | static const struct clksel_rate omap_96m_dpll_rates[] = { | ||
637 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
638 | { .div = 0 } | ||
639 | }; | ||
640 | |||
641 | static const struct clksel_rate omap_96m_sys_rates[] = { | ||
642 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
643 | { .div = 0 } | ||
644 | }; | ||
645 | |||
646 | static const struct clksel omap_96m_fck_clksel[] = { | ||
647 | { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates }, | ||
648 | { .parent = &sys_ck, .rates = omap_96m_sys_rates }, | ||
649 | { .parent = NULL } | ||
650 | }; | ||
651 | |||
652 | static struct clk omap_96m_fck = { | ||
653 | .name = "omap_96m_fck", | ||
654 | .ops = &clkops_null, | ||
655 | .parent = &sys_ck, | ||
656 | .init = &omap2_init_clksel_parent, | ||
657 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | ||
658 | .clksel_mask = OMAP3430_SOURCE_96M_MASK, | ||
659 | .clksel = omap_96m_fck_clksel, | ||
660 | .recalc = &omap2_clksel_recalc, | ||
661 | }; | ||
662 | |||
663 | /* This virtual clock is the source for dpll4_m3x2_ck */ | ||
664 | static struct clk dpll4_m3_ck = { | ||
665 | .name = "dpll4_m3_ck", | ||
666 | .ops = &clkops_null, | ||
667 | .parent = &dpll4_ck, | ||
668 | .init = &omap2_init_clksel_parent, | ||
669 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), | ||
670 | .clksel_mask = OMAP3430_CLKSEL_TV_MASK, | ||
671 | .clksel = div16_dpll4_clksel, | ||
672 | .clkdm_name = "dpll4_clkdm", | ||
673 | .recalc = &omap2_clksel_recalc, | ||
674 | }; | ||
675 | |||
676 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | ||
677 | static struct clk dpll4_m3x2_ck = { | ||
678 | .name = "dpll4_m3x2_ck", | ||
679 | .ops = &clkops_omap2_dflt_wait, | ||
680 | .parent = &dpll4_m3_ck, | ||
681 | .init = &omap2_init_clksel_parent, | ||
682 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | ||
683 | .enable_bit = OMAP3430_PWRDN_TV_SHIFT, | ||
684 | .flags = INVERT_ENABLE, | ||
685 | .clkdm_name = "dpll4_clkdm", | ||
686 | .recalc = &omap3_clkoutx2_recalc, | ||
687 | }; | ||
688 | |||
689 | static const struct clksel_rate omap_54m_d4m3x2_rates[] = { | ||
690 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
691 | { .div = 0 } | ||
692 | }; | ||
693 | |||
694 | static const struct clksel_rate omap_54m_alt_rates[] = { | ||
695 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
696 | { .div = 0 } | ||
697 | }; | ||
698 | |||
699 | static const struct clksel omap_54m_clksel[] = { | ||
700 | { .parent = &dpll4_m3x2_ck, .rates = omap_54m_d4m3x2_rates }, | ||
701 | { .parent = &sys_altclk, .rates = omap_54m_alt_rates }, | ||
702 | { .parent = NULL } | ||
703 | }; | ||
704 | |||
705 | static struct clk omap_54m_fck = { | ||
706 | .name = "omap_54m_fck", | ||
707 | .ops = &clkops_null, | ||
708 | .init = &omap2_init_clksel_parent, | ||
709 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | ||
710 | .clksel_mask = OMAP3430_SOURCE_54M_MASK, | ||
711 | .clksel = omap_54m_clksel, | ||
712 | .recalc = &omap2_clksel_recalc, | ||
713 | }; | ||
714 | |||
715 | static const struct clksel_rate omap_48m_cm96m_rates[] = { | ||
716 | { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
717 | { .div = 0 } | ||
718 | }; | ||
719 | |||
720 | static const struct clksel_rate omap_48m_alt_rates[] = { | ||
721 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
722 | { .div = 0 } | ||
723 | }; | ||
724 | |||
725 | static const struct clksel omap_48m_clksel[] = { | ||
726 | { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates }, | ||
727 | { .parent = &sys_altclk, .rates = omap_48m_alt_rates }, | ||
728 | { .parent = NULL } | ||
729 | }; | ||
730 | |||
731 | static struct clk omap_48m_fck = { | ||
732 | .name = "omap_48m_fck", | ||
733 | .ops = &clkops_null, | ||
734 | .init = &omap2_init_clksel_parent, | ||
735 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | ||
736 | .clksel_mask = OMAP3430_SOURCE_48M_MASK, | ||
737 | .clksel = omap_48m_clksel, | ||
738 | .recalc = &omap2_clksel_recalc, | ||
739 | }; | ||
740 | |||
741 | static struct clk omap_12m_fck = { | ||
742 | .name = "omap_12m_fck", | ||
743 | .ops = &clkops_null, | ||
744 | .parent = &omap_48m_fck, | ||
745 | .fixed_div = 4, | ||
746 | .recalc = &omap2_fixed_divisor_recalc, | ||
747 | }; | ||
748 | |||
749 | /* This virstual clock is the source for dpll4_m4x2_ck */ | ||
750 | static struct clk dpll4_m4_ck = { | ||
751 | .name = "dpll4_m4_ck", | ||
752 | .ops = &clkops_null, | ||
753 | .parent = &dpll4_ck, | ||
754 | .init = &omap2_init_clksel_parent, | ||
755 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), | ||
756 | .clksel_mask = OMAP3430_CLKSEL_DSS1_MASK, | ||
757 | .clksel = div16_dpll4_clksel, | ||
758 | .clkdm_name = "dpll4_clkdm", | ||
759 | .recalc = &omap2_clksel_recalc, | ||
760 | .set_rate = &omap2_clksel_set_rate, | ||
761 | .round_rate = &omap2_clksel_round_rate, | ||
762 | }; | ||
763 | |||
764 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | ||
765 | static struct clk dpll4_m4x2_ck = { | ||
766 | .name = "dpll4_m4x2_ck", | ||
767 | .ops = &clkops_omap2_dflt_wait, | ||
768 | .parent = &dpll4_m4_ck, | ||
769 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | ||
770 | .enable_bit = OMAP3430_PWRDN_CAM_SHIFT, | ||
771 | .flags = INVERT_ENABLE, | ||
772 | .clkdm_name = "dpll4_clkdm", | ||
773 | .recalc = &omap3_clkoutx2_recalc, | ||
774 | }; | ||
775 | |||
776 | /* This virtual clock is the source for dpll4_m5x2_ck */ | ||
777 | static struct clk dpll4_m5_ck = { | ||
778 | .name = "dpll4_m5_ck", | ||
779 | .ops = &clkops_null, | ||
780 | .parent = &dpll4_ck, | ||
781 | .init = &omap2_init_clksel_parent, | ||
782 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL), | ||
783 | .clksel_mask = OMAP3430_CLKSEL_CAM_MASK, | ||
784 | .clksel = div16_dpll4_clksel, | ||
785 | .clkdm_name = "dpll4_clkdm", | ||
786 | .recalc = &omap2_clksel_recalc, | ||
787 | }; | ||
788 | |||
789 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | ||
790 | static struct clk dpll4_m5x2_ck = { | ||
791 | .name = "dpll4_m5x2_ck", | ||
792 | .ops = &clkops_omap2_dflt_wait, | ||
793 | .parent = &dpll4_m5_ck, | ||
794 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | ||
795 | .enable_bit = OMAP3430_PWRDN_CAM_SHIFT, | ||
796 | .flags = INVERT_ENABLE, | ||
797 | .clkdm_name = "dpll4_clkdm", | ||
798 | .recalc = &omap3_clkoutx2_recalc, | ||
799 | }; | ||
800 | |||
801 | /* This virtual clock is the source for dpll4_m6x2_ck */ | ||
802 | static struct clk dpll4_m6_ck = { | ||
803 | .name = "dpll4_m6_ck", | ||
804 | .ops = &clkops_null, | ||
805 | .parent = &dpll4_ck, | ||
806 | .init = &omap2_init_clksel_parent, | ||
807 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | ||
808 | .clksel_mask = OMAP3430_DIV_DPLL4_MASK, | ||
809 | .clksel = div16_dpll4_clksel, | ||
810 | .clkdm_name = "dpll4_clkdm", | ||
811 | .recalc = &omap2_clksel_recalc, | ||
812 | }; | ||
813 | |||
814 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | ||
815 | static struct clk dpll4_m6x2_ck = { | ||
816 | .name = "dpll4_m6x2_ck", | ||
817 | .ops = &clkops_omap2_dflt_wait, | ||
818 | .parent = &dpll4_m6_ck, | ||
819 | .init = &omap2_init_clksel_parent, | ||
820 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | ||
821 | .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT, | ||
822 | .flags = INVERT_ENABLE, | ||
823 | .clkdm_name = "dpll4_clkdm", | ||
824 | .recalc = &omap3_clkoutx2_recalc, | ||
825 | }; | ||
826 | |||
827 | static struct clk emu_per_alwon_ck = { | ||
828 | .name = "emu_per_alwon_ck", | ||
829 | .ops = &clkops_null, | ||
830 | .parent = &dpll4_m6x2_ck, | ||
831 | .clkdm_name = "dpll4_clkdm", | ||
832 | .recalc = &followparent_recalc, | ||
833 | }; | ||
834 | |||
835 | /* DPLL5 */ | ||
836 | /* Supplies 120MHz clock, USIM source clock */ | ||
837 | /* Type: DPLL */ | ||
838 | /* 3430ES2 only */ | ||
839 | static struct dpll_data dpll5_dd = { | ||
840 | .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4), | ||
841 | .mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK, | ||
842 | .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK, | ||
843 | .clk_bypass = &sys_ck, | ||
844 | .clk_ref = &sys_ck, | ||
845 | .freqsel_mask = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK, | ||
846 | .control_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2), | ||
847 | .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK, | ||
848 | .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED), | ||
849 | .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT, | ||
850 | .recal_en_bit = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT, | ||
851 | .recal_st_bit = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT, | ||
852 | .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL), | ||
853 | .autoidle_mask = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK, | ||
854 | .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2), | ||
855 | .idlest_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK, | ||
856 | .max_multiplier = OMAP3_MAX_DPLL_MULT, | ||
857 | .min_divider = 1, | ||
858 | .max_divider = OMAP3_MAX_DPLL_DIV, | ||
859 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE | ||
860 | }; | ||
861 | |||
862 | static struct clk dpll5_ck = { | ||
863 | .name = "dpll5_ck", | ||
864 | .ops = &clkops_noncore_dpll_ops, | ||
865 | .parent = &sys_ck, | ||
866 | .dpll_data = &dpll5_dd, | ||
867 | .round_rate = &omap2_dpll_round_rate, | ||
868 | .set_rate = &omap3_noncore_dpll_set_rate, | ||
869 | .clkdm_name = "dpll5_clkdm", | ||
870 | .recalc = &omap3_dpll_recalc, | ||
871 | }; | ||
872 | |||
873 | static const struct clksel div16_dpll5_clksel[] = { | ||
874 | { .parent = &dpll5_ck, .rates = div16_dpll_rates }, | ||
875 | { .parent = NULL } | ||
876 | }; | ||
877 | |||
878 | static struct clk dpll5_m2_ck = { | ||
879 | .name = "dpll5_m2_ck", | ||
880 | .ops = &clkops_null, | ||
881 | .parent = &dpll5_ck, | ||
882 | .init = &omap2_init_clksel_parent, | ||
883 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5), | ||
884 | .clksel_mask = OMAP3430ES2_DIV_120M_MASK, | ||
885 | .clksel = div16_dpll5_clksel, | ||
886 | .clkdm_name = "dpll5_clkdm", | ||
887 | .recalc = &omap2_clksel_recalc, | ||
888 | }; | ||
889 | |||
890 | /* CM EXTERNAL CLOCK OUTPUTS */ | ||
891 | |||
892 | static const struct clksel_rate clkout2_src_core_rates[] = { | ||
893 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
894 | { .div = 0 } | ||
895 | }; | ||
896 | |||
897 | static const struct clksel_rate clkout2_src_sys_rates[] = { | ||
898 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
899 | { .div = 0 } | ||
900 | }; | ||
901 | |||
902 | static const struct clksel_rate clkout2_src_96m_rates[] = { | ||
903 | { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
904 | { .div = 0 } | ||
905 | }; | ||
906 | |||
907 | static const struct clksel_rate clkout2_src_54m_rates[] = { | ||
908 | { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
909 | { .div = 0 } | ||
910 | }; | ||
911 | |||
912 | static const struct clksel clkout2_src_clksel[] = { | ||
913 | { .parent = &core_ck, .rates = clkout2_src_core_rates }, | ||
914 | { .parent = &sys_ck, .rates = clkout2_src_sys_rates }, | ||
915 | { .parent = &cm_96m_fck, .rates = clkout2_src_96m_rates }, | ||
916 | { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates }, | ||
917 | { .parent = NULL } | ||
918 | }; | ||
919 | |||
920 | static struct clk clkout2_src_ck = { | ||
921 | .name = "clkout2_src_ck", | ||
922 | .ops = &clkops_omap2_dflt, | ||
923 | .init = &omap2_init_clksel_parent, | ||
924 | .enable_reg = OMAP3430_CM_CLKOUT_CTRL, | ||
925 | .enable_bit = OMAP3430_CLKOUT2_EN_SHIFT, | ||
926 | .clksel_reg = OMAP3430_CM_CLKOUT_CTRL, | ||
927 | .clksel_mask = OMAP3430_CLKOUT2SOURCE_MASK, | ||
928 | .clksel = clkout2_src_clksel, | ||
929 | .clkdm_name = "core_clkdm", | ||
930 | .recalc = &omap2_clksel_recalc, | ||
931 | }; | ||
932 | |||
933 | static const struct clksel_rate sys_clkout2_rates[] = { | ||
934 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
935 | { .div = 2, .val = 1, .flags = RATE_IN_343X }, | ||
936 | { .div = 4, .val = 2, .flags = RATE_IN_343X }, | ||
937 | { .div = 8, .val = 3, .flags = RATE_IN_343X }, | ||
938 | { .div = 16, .val = 4, .flags = RATE_IN_343X }, | ||
939 | { .div = 0 }, | ||
940 | }; | ||
941 | |||
942 | static const struct clksel sys_clkout2_clksel[] = { | ||
943 | { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates }, | ||
944 | { .parent = NULL }, | ||
945 | }; | ||
946 | |||
947 | static struct clk sys_clkout2 = { | ||
948 | .name = "sys_clkout2", | ||
949 | .ops = &clkops_null, | ||
950 | .init = &omap2_init_clksel_parent, | ||
951 | .clksel_reg = OMAP3430_CM_CLKOUT_CTRL, | ||
952 | .clksel_mask = OMAP3430_CLKOUT2_DIV_MASK, | ||
953 | .clksel = sys_clkout2_clksel, | ||
954 | .recalc = &omap2_clksel_recalc, | ||
955 | }; | ||
956 | |||
957 | /* CM OUTPUT CLOCKS */ | ||
958 | |||
959 | static struct clk corex2_fck = { | ||
960 | .name = "corex2_fck", | ||
961 | .ops = &clkops_null, | ||
962 | .parent = &dpll3_m2x2_ck, | ||
963 | .recalc = &followparent_recalc, | ||
964 | }; | ||
965 | |||
966 | /* DPLL power domain clock controls */ | ||
967 | |||
968 | static const struct clksel_rate div4_rates[] = { | ||
969 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
970 | { .div = 2, .val = 2, .flags = RATE_IN_343X }, | ||
971 | { .div = 4, .val = 4, .flags = RATE_IN_343X }, | ||
972 | { .div = 0 } | ||
973 | }; | ||
974 | |||
975 | static const struct clksel div4_core_clksel[] = { | ||
976 | { .parent = &core_ck, .rates = div4_rates }, | ||
977 | { .parent = NULL } | ||
978 | }; | ||
979 | |||
980 | /* | ||
981 | * REVISIT: Are these in DPLL power domain or CM power domain? docs | ||
982 | * may be inconsistent here? | ||
983 | */ | ||
984 | static struct clk dpll1_fck = { | ||
985 | .name = "dpll1_fck", | ||
986 | .ops = &clkops_null, | ||
987 | .parent = &core_ck, | ||
988 | .init = &omap2_init_clksel_parent, | ||
989 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), | ||
990 | .clksel_mask = OMAP3430_MPU_CLK_SRC_MASK, | ||
991 | .clksel = div4_core_clksel, | ||
992 | .recalc = &omap2_clksel_recalc, | ||
993 | }; | ||
994 | |||
995 | static struct clk mpu_ck = { | ||
996 | .name = "mpu_ck", | ||
997 | .ops = &clkops_null, | ||
998 | .parent = &dpll1_x2m2_ck, | ||
999 | .clkdm_name = "mpu_clkdm", | ||
1000 | .recalc = &followparent_recalc, | ||
1001 | }; | ||
1002 | |||
1003 | /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */ | ||
1004 | static const struct clksel_rate arm_fck_rates[] = { | ||
1005 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
1006 | { .div = 2, .val = 1, .flags = RATE_IN_343X }, | ||
1007 | { .div = 0 }, | ||
1008 | }; | ||
1009 | |||
1010 | static const struct clksel arm_fck_clksel[] = { | ||
1011 | { .parent = &mpu_ck, .rates = arm_fck_rates }, | ||
1012 | { .parent = NULL } | ||
1013 | }; | ||
1014 | |||
1015 | static struct clk arm_fck = { | ||
1016 | .name = "arm_fck", | ||
1017 | .ops = &clkops_null, | ||
1018 | .parent = &mpu_ck, | ||
1019 | .init = &omap2_init_clksel_parent, | ||
1020 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), | ||
1021 | .clksel_mask = OMAP3430_ST_MPU_CLK_MASK, | ||
1022 | .clksel = arm_fck_clksel, | ||
1023 | .clkdm_name = "mpu_clkdm", | ||
1024 | .recalc = &omap2_clksel_recalc, | ||
1025 | }; | ||
1026 | |||
1027 | /* XXX What about neon_clkdm ? */ | ||
1028 | |||
1029 | /* | ||
1030 | * REVISIT: This clock is never specifically defined in the 3430 TRM, | ||
1031 | * although it is referenced - so this is a guess | ||
1032 | */ | ||
1033 | static struct clk emu_mpu_alwon_ck = { | ||
1034 | .name = "emu_mpu_alwon_ck", | ||
1035 | .ops = &clkops_null, | ||
1036 | .parent = &mpu_ck, | ||
1037 | .recalc = &followparent_recalc, | ||
1038 | }; | ||
1039 | |||
1040 | static struct clk dpll2_fck = { | ||
1041 | .name = "dpll2_fck", | ||
1042 | .ops = &clkops_null, | ||
1043 | .parent = &core_ck, | ||
1044 | .init = &omap2_init_clksel_parent, | ||
1045 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), | ||
1046 | .clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK, | ||
1047 | .clksel = div4_core_clksel, | ||
1048 | .recalc = &omap2_clksel_recalc, | ||
1049 | }; | ||
1050 | |||
1051 | static struct clk iva2_ck = { | ||
1052 | .name = "iva2_ck", | ||
1053 | .ops = &clkops_omap2_dflt_wait, | ||
1054 | .parent = &dpll2_m2_ck, | ||
1055 | .init = &omap2_init_clksel_parent, | ||
1056 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN), | ||
1057 | .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT, | ||
1058 | .clkdm_name = "iva2_clkdm", | ||
1059 | .recalc = &followparent_recalc, | ||
1060 | }; | ||
1061 | |||
1062 | /* Common interface clocks */ | ||
1063 | |||
1064 | static const struct clksel div2_core_clksel[] = { | ||
1065 | { .parent = &core_ck, .rates = div2_rates }, | ||
1066 | { .parent = NULL } | ||
1067 | }; | ||
1068 | |||
1069 | static struct clk l3_ick = { | ||
1070 | .name = "l3_ick", | ||
1071 | .ops = &clkops_null, | ||
1072 | .parent = &core_ck, | ||
1073 | .init = &omap2_init_clksel_parent, | ||
1074 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), | ||
1075 | .clksel_mask = OMAP3430_CLKSEL_L3_MASK, | ||
1076 | .clksel = div2_core_clksel, | ||
1077 | .clkdm_name = "core_l3_clkdm", | ||
1078 | .recalc = &omap2_clksel_recalc, | ||
1079 | }; | ||
1080 | |||
1081 | static const struct clksel div2_l3_clksel[] = { | ||
1082 | { .parent = &l3_ick, .rates = div2_rates }, | ||
1083 | { .parent = NULL } | ||
1084 | }; | ||
1085 | |||
1086 | static struct clk l4_ick = { | ||
1087 | .name = "l4_ick", | ||
1088 | .ops = &clkops_null, | ||
1089 | .parent = &l3_ick, | ||
1090 | .init = &omap2_init_clksel_parent, | ||
1091 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), | ||
1092 | .clksel_mask = OMAP3430_CLKSEL_L4_MASK, | ||
1093 | .clksel = div2_l3_clksel, | ||
1094 | .clkdm_name = "core_l4_clkdm", | ||
1095 | .recalc = &omap2_clksel_recalc, | ||
1096 | |||
1097 | }; | ||
1098 | |||
1099 | static const struct clksel div2_l4_clksel[] = { | ||
1100 | { .parent = &l4_ick, .rates = div2_rates }, | ||
1101 | { .parent = NULL } | ||
1102 | }; | ||
1103 | |||
1104 | static struct clk rm_ick = { | ||
1105 | .name = "rm_ick", | ||
1106 | .ops = &clkops_null, | ||
1107 | .parent = &l4_ick, | ||
1108 | .init = &omap2_init_clksel_parent, | ||
1109 | .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), | ||
1110 | .clksel_mask = OMAP3430_CLKSEL_RM_MASK, | ||
1111 | .clksel = div2_l4_clksel, | ||
1112 | .recalc = &omap2_clksel_recalc, | ||
1113 | }; | ||
1114 | |||
1115 | /* GFX power domain */ | ||
1116 | |||
1117 | /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */ | ||
1118 | |||
1119 | static const struct clksel gfx_l3_clksel[] = { | ||
1120 | { .parent = &l3_ick, .rates = gfx_l3_rates }, | ||
1121 | { .parent = NULL } | ||
1122 | }; | ||
1123 | |||
1124 | /* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */ | ||
1125 | static struct clk gfx_l3_ck = { | ||
1126 | .name = "gfx_l3_ck", | ||
1127 | .ops = &clkops_omap2_dflt_wait, | ||
1128 | .parent = &l3_ick, | ||
1129 | .init = &omap2_init_clksel_parent, | ||
1130 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), | ||
1131 | .enable_bit = OMAP_EN_GFX_SHIFT, | ||
1132 | .recalc = &followparent_recalc, | ||
1133 | }; | ||
1134 | |||
1135 | static struct clk gfx_l3_fck = { | ||
1136 | .name = "gfx_l3_fck", | ||
1137 | .ops = &clkops_null, | ||
1138 | .parent = &gfx_l3_ck, | ||
1139 | .init = &omap2_init_clksel_parent, | ||
1140 | .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), | ||
1141 | .clksel_mask = OMAP_CLKSEL_GFX_MASK, | ||
1142 | .clksel = gfx_l3_clksel, | ||
1143 | .clkdm_name = "gfx_3430es1_clkdm", | ||
1144 | .recalc = &omap2_clksel_recalc, | ||
1145 | }; | ||
1146 | |||
1147 | static struct clk gfx_l3_ick = { | ||
1148 | .name = "gfx_l3_ick", | ||
1149 | .ops = &clkops_null, | ||
1150 | .parent = &gfx_l3_ck, | ||
1151 | .clkdm_name = "gfx_3430es1_clkdm", | ||
1152 | .recalc = &followparent_recalc, | ||
1153 | }; | ||
1154 | |||
1155 | static struct clk gfx_cg1_ck = { | ||
1156 | .name = "gfx_cg1_ck", | ||
1157 | .ops = &clkops_omap2_dflt_wait, | ||
1158 | .parent = &gfx_l3_fck, /* REVISIT: correct? */ | ||
1159 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), | ||
1160 | .enable_bit = OMAP3430ES1_EN_2D_SHIFT, | ||
1161 | .clkdm_name = "gfx_3430es1_clkdm", | ||
1162 | .recalc = &followparent_recalc, | ||
1163 | }; | ||
1164 | |||
1165 | static struct clk gfx_cg2_ck = { | ||
1166 | .name = "gfx_cg2_ck", | ||
1167 | .ops = &clkops_omap2_dflt_wait, | ||
1168 | .parent = &gfx_l3_fck, /* REVISIT: correct? */ | ||
1169 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), | ||
1170 | .enable_bit = OMAP3430ES1_EN_3D_SHIFT, | ||
1171 | .clkdm_name = "gfx_3430es1_clkdm", | ||
1172 | .recalc = &followparent_recalc, | ||
1173 | }; | ||
1174 | |||
1175 | /* SGX power domain - 3430ES2 only */ | ||
1176 | |||
1177 | static const struct clksel_rate sgx_core_rates[] = { | ||
1178 | { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
1179 | { .div = 4, .val = 1, .flags = RATE_IN_343X }, | ||
1180 | { .div = 6, .val = 2, .flags = RATE_IN_343X }, | ||
1181 | { .div = 0 }, | ||
1182 | }; | ||
1183 | |||
1184 | static const struct clksel_rate sgx_96m_rates[] = { | ||
1185 | { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
1186 | { .div = 0 }, | ||
1187 | }; | ||
1188 | |||
1189 | static const struct clksel sgx_clksel[] = { | ||
1190 | { .parent = &core_ck, .rates = sgx_core_rates }, | ||
1191 | { .parent = &cm_96m_fck, .rates = sgx_96m_rates }, | ||
1192 | { .parent = NULL }, | ||
1193 | }; | ||
1194 | |||
1195 | static struct clk sgx_fck = { | ||
1196 | .name = "sgx_fck", | ||
1197 | .ops = &clkops_omap2_dflt_wait, | ||
1198 | .init = &omap2_init_clksel_parent, | ||
1199 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN), | ||
1200 | .enable_bit = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT, | ||
1201 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL), | ||
1202 | .clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK, | ||
1203 | .clksel = sgx_clksel, | ||
1204 | .clkdm_name = "sgx_clkdm", | ||
1205 | .recalc = &omap2_clksel_recalc, | ||
1206 | }; | ||
1207 | |||
1208 | static struct clk sgx_ick = { | ||
1209 | .name = "sgx_ick", | ||
1210 | .ops = &clkops_omap2_dflt_wait, | ||
1211 | .parent = &l3_ick, | ||
1212 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN), | ||
1213 | .enable_bit = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT, | ||
1214 | .clkdm_name = "sgx_clkdm", | ||
1215 | .recalc = &followparent_recalc, | ||
1216 | }; | ||
1217 | |||
1218 | /* CORE power domain */ | ||
1219 | |||
1220 | static struct clk d2d_26m_fck = { | ||
1221 | .name = "d2d_26m_fck", | ||
1222 | .ops = &clkops_omap2_dflt_wait, | ||
1223 | .parent = &sys_ck, | ||
1224 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
1225 | .enable_bit = OMAP3430ES1_EN_D2D_SHIFT, | ||
1226 | .clkdm_name = "d2d_clkdm", | ||
1227 | .recalc = &followparent_recalc, | ||
1228 | }; | ||
1229 | |||
1230 | static struct clk modem_fck = { | ||
1231 | .name = "modem_fck", | ||
1232 | .ops = &clkops_omap2_dflt_wait, | ||
1233 | .parent = &sys_ck, | ||
1234 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
1235 | .enable_bit = OMAP3430_EN_MODEM_SHIFT, | ||
1236 | .clkdm_name = "d2d_clkdm", | ||
1237 | .recalc = &followparent_recalc, | ||
1238 | }; | ||
1239 | |||
1240 | static struct clk sad2d_ick = { | ||
1241 | .name = "sad2d_ick", | ||
1242 | .ops = &clkops_omap2_dflt_wait, | ||
1243 | .parent = &l3_ick, | ||
1244 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1245 | .enable_bit = OMAP3430_EN_SAD2D_SHIFT, | ||
1246 | .clkdm_name = "d2d_clkdm", | ||
1247 | .recalc = &followparent_recalc, | ||
1248 | }; | ||
1249 | |||
1250 | static struct clk mad2d_ick = { | ||
1251 | .name = "mad2d_ick", | ||
1252 | .ops = &clkops_omap2_dflt_wait, | ||
1253 | .parent = &l3_ick, | ||
1254 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), | ||
1255 | .enable_bit = OMAP3430_EN_MAD2D_SHIFT, | ||
1256 | .clkdm_name = "d2d_clkdm", | ||
1257 | .recalc = &followparent_recalc, | ||
1258 | }; | ||
1259 | |||
1260 | static const struct clksel omap343x_gpt_clksel[] = { | ||
1261 | { .parent = &omap_32k_fck, .rates = gpt_32k_rates }, | ||
1262 | { .parent = &sys_ck, .rates = gpt_sys_rates }, | ||
1263 | { .parent = NULL} | ||
1264 | }; | ||
1265 | |||
1266 | static struct clk gpt10_fck = { | ||
1267 | .name = "gpt10_fck", | ||
1268 | .ops = &clkops_omap2_dflt_wait, | ||
1269 | .parent = &sys_ck, | ||
1270 | .init = &omap2_init_clksel_parent, | ||
1271 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
1272 | .enable_bit = OMAP3430_EN_GPT10_SHIFT, | ||
1273 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), | ||
1274 | .clksel_mask = OMAP3430_CLKSEL_GPT10_MASK, | ||
1275 | .clksel = omap343x_gpt_clksel, | ||
1276 | .clkdm_name = "core_l4_clkdm", | ||
1277 | .recalc = &omap2_clksel_recalc, | ||
1278 | }; | ||
1279 | |||
1280 | static struct clk gpt11_fck = { | ||
1281 | .name = "gpt11_fck", | ||
1282 | .ops = &clkops_omap2_dflt_wait, | ||
1283 | .parent = &sys_ck, | ||
1284 | .init = &omap2_init_clksel_parent, | ||
1285 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
1286 | .enable_bit = OMAP3430_EN_GPT11_SHIFT, | ||
1287 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), | ||
1288 | .clksel_mask = OMAP3430_CLKSEL_GPT11_MASK, | ||
1289 | .clksel = omap343x_gpt_clksel, | ||
1290 | .clkdm_name = "core_l4_clkdm", | ||
1291 | .recalc = &omap2_clksel_recalc, | ||
1292 | }; | ||
1293 | |||
1294 | static struct clk cpefuse_fck = { | ||
1295 | .name = "cpefuse_fck", | ||
1296 | .ops = &clkops_omap2_dflt, | ||
1297 | .parent = &sys_ck, | ||
1298 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), | ||
1299 | .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT, | ||
1300 | .recalc = &followparent_recalc, | ||
1301 | }; | ||
1302 | |||
1303 | static struct clk ts_fck = { | ||
1304 | .name = "ts_fck", | ||
1305 | .ops = &clkops_omap2_dflt, | ||
1306 | .parent = &omap_32k_fck, | ||
1307 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), | ||
1308 | .enable_bit = OMAP3430ES2_EN_TS_SHIFT, | ||
1309 | .recalc = &followparent_recalc, | ||
1310 | }; | ||
1311 | |||
1312 | static struct clk usbtll_fck = { | ||
1313 | .name = "usbtll_fck", | ||
1314 | .ops = &clkops_omap2_dflt, | ||
1315 | .parent = &dpll5_m2_ck, | ||
1316 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), | ||
1317 | .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, | ||
1318 | .recalc = &followparent_recalc, | ||
1319 | }; | ||
1320 | |||
1321 | /* CORE 96M FCLK-derived clocks */ | ||
1322 | |||
1323 | static struct clk core_96m_fck = { | ||
1324 | .name = "core_96m_fck", | ||
1325 | .ops = &clkops_null, | ||
1326 | .parent = &omap_96m_fck, | ||
1327 | .clkdm_name = "core_l4_clkdm", | ||
1328 | .recalc = &followparent_recalc, | ||
1329 | }; | ||
1330 | |||
1331 | static struct clk mmchs3_fck = { | ||
1332 | .name = "mmchs_fck", | ||
1333 | .ops = &clkops_omap2_dflt_wait, | ||
1334 | .id = 2, | ||
1335 | .parent = &core_96m_fck, | ||
1336 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
1337 | .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, | ||
1338 | .clkdm_name = "core_l4_clkdm", | ||
1339 | .recalc = &followparent_recalc, | ||
1340 | }; | ||
1341 | |||
1342 | static struct clk mmchs2_fck = { | ||
1343 | .name = "mmchs_fck", | ||
1344 | .ops = &clkops_omap2_dflt_wait, | ||
1345 | .id = 1, | ||
1346 | .parent = &core_96m_fck, | ||
1347 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
1348 | .enable_bit = OMAP3430_EN_MMC2_SHIFT, | ||
1349 | .clkdm_name = "core_l4_clkdm", | ||
1350 | .recalc = &followparent_recalc, | ||
1351 | }; | ||
1352 | |||
1353 | static struct clk mspro_fck = { | ||
1354 | .name = "mspro_fck", | ||
1355 | .ops = &clkops_omap2_dflt_wait, | ||
1356 | .parent = &core_96m_fck, | ||
1357 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
1358 | .enable_bit = OMAP3430_EN_MSPRO_SHIFT, | ||
1359 | .clkdm_name = "core_l4_clkdm", | ||
1360 | .recalc = &followparent_recalc, | ||
1361 | }; | ||
1362 | |||
1363 | static struct clk mmchs1_fck = { | ||
1364 | .name = "mmchs_fck", | ||
1365 | .ops = &clkops_omap2_dflt_wait, | ||
1366 | .parent = &core_96m_fck, | ||
1367 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
1368 | .enable_bit = OMAP3430_EN_MMC1_SHIFT, | ||
1369 | .clkdm_name = "core_l4_clkdm", | ||
1370 | .recalc = &followparent_recalc, | ||
1371 | }; | ||
1372 | |||
1373 | static struct clk i2c3_fck = { | ||
1374 | .name = "i2c_fck", | ||
1375 | .ops = &clkops_omap2_dflt_wait, | ||
1376 | .id = 3, | ||
1377 | .parent = &core_96m_fck, | ||
1378 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
1379 | .enable_bit = OMAP3430_EN_I2C3_SHIFT, | ||
1380 | .clkdm_name = "core_l4_clkdm", | ||
1381 | .recalc = &followparent_recalc, | ||
1382 | }; | ||
1383 | |||
1384 | static struct clk i2c2_fck = { | ||
1385 | .name = "i2c_fck", | ||
1386 | .ops = &clkops_omap2_dflt_wait, | ||
1387 | .id = 2, | ||
1388 | .parent = &core_96m_fck, | ||
1389 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
1390 | .enable_bit = OMAP3430_EN_I2C2_SHIFT, | ||
1391 | .clkdm_name = "core_l4_clkdm", | ||
1392 | .recalc = &followparent_recalc, | ||
1393 | }; | ||
1394 | |||
1395 | static struct clk i2c1_fck = { | ||
1396 | .name = "i2c_fck", | ||
1397 | .ops = &clkops_omap2_dflt_wait, | ||
1398 | .id = 1, | ||
1399 | .parent = &core_96m_fck, | ||
1400 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
1401 | .enable_bit = OMAP3430_EN_I2C1_SHIFT, | ||
1402 | .clkdm_name = "core_l4_clkdm", | ||
1403 | .recalc = &followparent_recalc, | ||
1404 | }; | ||
1405 | |||
1406 | /* | ||
1407 | * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck; | ||
1408 | * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck. | ||
1409 | */ | ||
1410 | static const struct clksel_rate common_mcbsp_96m_rates[] = { | ||
1411 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
1412 | { .div = 0 } | ||
1413 | }; | ||
1414 | |||
1415 | static const struct clksel_rate common_mcbsp_mcbsp_rates[] = { | ||
1416 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
1417 | { .div = 0 } | ||
1418 | }; | ||
1419 | |||
1420 | static const struct clksel mcbsp_15_clksel[] = { | ||
1421 | { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates }, | ||
1422 | { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, | ||
1423 | { .parent = NULL } | ||
1424 | }; | ||
1425 | |||
1426 | static struct clk mcbsp5_fck = { | ||
1427 | .name = "mcbsp_fck", | ||
1428 | .ops = &clkops_omap2_dflt_wait, | ||
1429 | .id = 5, | ||
1430 | .init = &omap2_init_clksel_parent, | ||
1431 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
1432 | .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, | ||
1433 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), | ||
1434 | .clksel_mask = OMAP2_MCBSP5_CLKS_MASK, | ||
1435 | .clksel = mcbsp_15_clksel, | ||
1436 | .clkdm_name = "core_l4_clkdm", | ||
1437 | .recalc = &omap2_clksel_recalc, | ||
1438 | }; | ||
1439 | |||
1440 | static struct clk mcbsp1_fck = { | ||
1441 | .name = "mcbsp_fck", | ||
1442 | .ops = &clkops_omap2_dflt_wait, | ||
1443 | .id = 1, | ||
1444 | .init = &omap2_init_clksel_parent, | ||
1445 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
1446 | .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, | ||
1447 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), | ||
1448 | .clksel_mask = OMAP2_MCBSP1_CLKS_MASK, | ||
1449 | .clksel = mcbsp_15_clksel, | ||
1450 | .clkdm_name = "core_l4_clkdm", | ||
1451 | .recalc = &omap2_clksel_recalc, | ||
1452 | }; | ||
1453 | |||
1454 | /* CORE_48M_FCK-derived clocks */ | ||
1455 | |||
1456 | static struct clk core_48m_fck = { | ||
1457 | .name = "core_48m_fck", | ||
1458 | .ops = &clkops_null, | ||
1459 | .parent = &omap_48m_fck, | ||
1460 | .clkdm_name = "core_l4_clkdm", | ||
1461 | .recalc = &followparent_recalc, | ||
1462 | }; | ||
1463 | |||
1464 | static struct clk mcspi4_fck = { | ||
1465 | .name = "mcspi_fck", | ||
1466 | .ops = &clkops_omap2_dflt_wait, | ||
1467 | .id = 4, | ||
1468 | .parent = &core_48m_fck, | ||
1469 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
1470 | .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, | ||
1471 | .recalc = &followparent_recalc, | ||
1472 | }; | ||
1473 | |||
1474 | static struct clk mcspi3_fck = { | ||
1475 | .name = "mcspi_fck", | ||
1476 | .ops = &clkops_omap2_dflt_wait, | ||
1477 | .id = 3, | ||
1478 | .parent = &core_48m_fck, | ||
1479 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
1480 | .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, | ||
1481 | .recalc = &followparent_recalc, | ||
1482 | }; | ||
1483 | |||
1484 | static struct clk mcspi2_fck = { | ||
1485 | .name = "mcspi_fck", | ||
1486 | .ops = &clkops_omap2_dflt_wait, | ||
1487 | .id = 2, | ||
1488 | .parent = &core_48m_fck, | ||
1489 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
1490 | .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, | ||
1491 | .recalc = &followparent_recalc, | ||
1492 | }; | ||
1493 | |||
1494 | static struct clk mcspi1_fck = { | ||
1495 | .name = "mcspi_fck", | ||
1496 | .ops = &clkops_omap2_dflt_wait, | ||
1497 | .id = 1, | ||
1498 | .parent = &core_48m_fck, | ||
1499 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
1500 | .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, | ||
1501 | .recalc = &followparent_recalc, | ||
1502 | }; | ||
1503 | |||
1504 | static struct clk uart2_fck = { | ||
1505 | .name = "uart2_fck", | ||
1506 | .ops = &clkops_omap2_dflt_wait, | ||
1507 | .parent = &core_48m_fck, | ||
1508 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
1509 | .enable_bit = OMAP3430_EN_UART2_SHIFT, | ||
1510 | .recalc = &followparent_recalc, | ||
1511 | }; | ||
1512 | |||
1513 | static struct clk uart1_fck = { | ||
1514 | .name = "uart1_fck", | ||
1515 | .ops = &clkops_omap2_dflt_wait, | ||
1516 | .parent = &core_48m_fck, | ||
1517 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
1518 | .enable_bit = OMAP3430_EN_UART1_SHIFT, | ||
1519 | .recalc = &followparent_recalc, | ||
1520 | }; | ||
1521 | |||
1522 | static struct clk fshostusb_fck = { | ||
1523 | .name = "fshostusb_fck", | ||
1524 | .ops = &clkops_omap2_dflt_wait, | ||
1525 | .parent = &core_48m_fck, | ||
1526 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
1527 | .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT, | ||
1528 | .recalc = &followparent_recalc, | ||
1529 | }; | ||
1530 | |||
1531 | /* CORE_12M_FCK based clocks */ | ||
1532 | |||
1533 | static struct clk core_12m_fck = { | ||
1534 | .name = "core_12m_fck", | ||
1535 | .ops = &clkops_null, | ||
1536 | .parent = &omap_12m_fck, | ||
1537 | .clkdm_name = "core_l4_clkdm", | ||
1538 | .recalc = &followparent_recalc, | ||
1539 | }; | ||
1540 | |||
1541 | static struct clk hdq_fck = { | ||
1542 | .name = "hdq_fck", | ||
1543 | .ops = &clkops_omap2_dflt_wait, | ||
1544 | .parent = &core_12m_fck, | ||
1545 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
1546 | .enable_bit = OMAP3430_EN_HDQ_SHIFT, | ||
1547 | .recalc = &followparent_recalc, | ||
1548 | }; | ||
1549 | |||
1550 | /* DPLL3-derived clock */ | ||
1551 | |||
1552 | static const struct clksel_rate ssi_ssr_corex2_rates[] = { | ||
1553 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
1554 | { .div = 2, .val = 2, .flags = RATE_IN_343X }, | ||
1555 | { .div = 3, .val = 3, .flags = RATE_IN_343X }, | ||
1556 | { .div = 4, .val = 4, .flags = RATE_IN_343X }, | ||
1557 | { .div = 6, .val = 6, .flags = RATE_IN_343X }, | ||
1558 | { .div = 8, .val = 8, .flags = RATE_IN_343X }, | ||
1559 | { .div = 0 } | ||
1560 | }; | ||
1561 | |||
1562 | static const struct clksel ssi_ssr_clksel[] = { | ||
1563 | { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates }, | ||
1564 | { .parent = NULL } | ||
1565 | }; | ||
1566 | |||
1567 | static struct clk ssi_ssr_fck_3430es1 = { | ||
1568 | .name = "ssi_ssr_fck", | ||
1569 | .ops = &clkops_omap2_dflt, | ||
1570 | .init = &omap2_init_clksel_parent, | ||
1571 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
1572 | .enable_bit = OMAP3430_EN_SSI_SHIFT, | ||
1573 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), | ||
1574 | .clksel_mask = OMAP3430_CLKSEL_SSI_MASK, | ||
1575 | .clksel = ssi_ssr_clksel, | ||
1576 | .clkdm_name = "core_l4_clkdm", | ||
1577 | .recalc = &omap2_clksel_recalc, | ||
1578 | }; | ||
1579 | |||
1580 | static struct clk ssi_ssr_fck_3430es2 = { | ||
1581 | .name = "ssi_ssr_fck", | ||
1582 | .ops = &clkops_omap3430es2_ssi_wait, | ||
1583 | .init = &omap2_init_clksel_parent, | ||
1584 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
1585 | .enable_bit = OMAP3430_EN_SSI_SHIFT, | ||
1586 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), | ||
1587 | .clksel_mask = OMAP3430_CLKSEL_SSI_MASK, | ||
1588 | .clksel = ssi_ssr_clksel, | ||
1589 | .clkdm_name = "core_l4_clkdm", | ||
1590 | .recalc = &omap2_clksel_recalc, | ||
1591 | }; | ||
1592 | |||
1593 | static struct clk ssi_sst_fck_3430es1 = { | ||
1594 | .name = "ssi_sst_fck", | ||
1595 | .ops = &clkops_null, | ||
1596 | .parent = &ssi_ssr_fck_3430es1, | ||
1597 | .fixed_div = 2, | ||
1598 | .recalc = &omap2_fixed_divisor_recalc, | ||
1599 | }; | ||
1600 | |||
1601 | static struct clk ssi_sst_fck_3430es2 = { | ||
1602 | .name = "ssi_sst_fck", | ||
1603 | .ops = &clkops_null, | ||
1604 | .parent = &ssi_ssr_fck_3430es2, | ||
1605 | .fixed_div = 2, | ||
1606 | .recalc = &omap2_fixed_divisor_recalc, | ||
1607 | }; | ||
1608 | |||
1609 | |||
1610 | |||
1611 | /* CORE_L3_ICK based clocks */ | ||
1612 | |||
1613 | /* | ||
1614 | * XXX must add clk_enable/clk_disable for these if standard code won't | ||
1615 | * handle it | ||
1616 | */ | ||
1617 | static struct clk core_l3_ick = { | ||
1618 | .name = "core_l3_ick", | ||
1619 | .ops = &clkops_null, | ||
1620 | .parent = &l3_ick, | ||
1621 | .clkdm_name = "core_l3_clkdm", | ||
1622 | .recalc = &followparent_recalc, | ||
1623 | }; | ||
1624 | |||
1625 | static struct clk hsotgusb_ick_3430es1 = { | ||
1626 | .name = "hsotgusb_ick", | ||
1627 | .ops = &clkops_omap2_dflt, | ||
1628 | .parent = &core_l3_ick, | ||
1629 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1630 | .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT, | ||
1631 | .clkdm_name = "core_l3_clkdm", | ||
1632 | .recalc = &followparent_recalc, | ||
1633 | }; | ||
1634 | |||
1635 | static struct clk hsotgusb_ick_3430es2 = { | ||
1636 | .name = "hsotgusb_ick", | ||
1637 | .ops = &clkops_omap3430es2_hsotgusb_wait, | ||
1638 | .parent = &core_l3_ick, | ||
1639 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1640 | .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT, | ||
1641 | .clkdm_name = "core_l3_clkdm", | ||
1642 | .recalc = &followparent_recalc, | ||
1643 | }; | ||
1644 | |||
1645 | static struct clk sdrc_ick = { | ||
1646 | .name = "sdrc_ick", | ||
1647 | .ops = &clkops_omap2_dflt_wait, | ||
1648 | .parent = &core_l3_ick, | ||
1649 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1650 | .enable_bit = OMAP3430_EN_SDRC_SHIFT, | ||
1651 | .flags = ENABLE_ON_INIT, | ||
1652 | .clkdm_name = "core_l3_clkdm", | ||
1653 | .recalc = &followparent_recalc, | ||
1654 | }; | ||
1655 | |||
1656 | static struct clk gpmc_fck = { | ||
1657 | .name = "gpmc_fck", | ||
1658 | .ops = &clkops_null, | ||
1659 | .parent = &core_l3_ick, | ||
1660 | .flags = ENABLE_ON_INIT, /* huh? */ | ||
1661 | .clkdm_name = "core_l3_clkdm", | ||
1662 | .recalc = &followparent_recalc, | ||
1663 | }; | ||
1664 | |||
1665 | /* SECURITY_L3_ICK based clocks */ | ||
1666 | |||
1667 | static struct clk security_l3_ick = { | ||
1668 | .name = "security_l3_ick", | ||
1669 | .ops = &clkops_null, | ||
1670 | .parent = &l3_ick, | ||
1671 | .recalc = &followparent_recalc, | ||
1672 | }; | ||
1673 | |||
1674 | static struct clk pka_ick = { | ||
1675 | .name = "pka_ick", | ||
1676 | .ops = &clkops_omap2_dflt_wait, | ||
1677 | .parent = &security_l3_ick, | ||
1678 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | ||
1679 | .enable_bit = OMAP3430_EN_PKA_SHIFT, | ||
1680 | .recalc = &followparent_recalc, | ||
1681 | }; | ||
1682 | |||
1683 | /* CORE_L4_ICK based clocks */ | ||
1684 | |||
1685 | static struct clk core_l4_ick = { | ||
1686 | .name = "core_l4_ick", | ||
1687 | .ops = &clkops_null, | ||
1688 | .parent = &l4_ick, | ||
1689 | .clkdm_name = "core_l4_clkdm", | ||
1690 | .recalc = &followparent_recalc, | ||
1691 | }; | ||
1692 | |||
1693 | static struct clk usbtll_ick = { | ||
1694 | .name = "usbtll_ick", | ||
1695 | .ops = &clkops_omap2_dflt_wait, | ||
1696 | .parent = &core_l4_ick, | ||
1697 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), | ||
1698 | .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, | ||
1699 | .clkdm_name = "core_l4_clkdm", | ||
1700 | .recalc = &followparent_recalc, | ||
1701 | }; | ||
1702 | |||
1703 | static struct clk mmchs3_ick = { | ||
1704 | .name = "mmchs_ick", | ||
1705 | .ops = &clkops_omap2_dflt_wait, | ||
1706 | .id = 2, | ||
1707 | .parent = &core_l4_ick, | ||
1708 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1709 | .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, | ||
1710 | .clkdm_name = "core_l4_clkdm", | ||
1711 | .recalc = &followparent_recalc, | ||
1712 | }; | ||
1713 | |||
1714 | /* Intersystem Communication Registers - chassis mode only */ | ||
1715 | static struct clk icr_ick = { | ||
1716 | .name = "icr_ick", | ||
1717 | .ops = &clkops_omap2_dflt_wait, | ||
1718 | .parent = &core_l4_ick, | ||
1719 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1720 | .enable_bit = OMAP3430_EN_ICR_SHIFT, | ||
1721 | .clkdm_name = "core_l4_clkdm", | ||
1722 | .recalc = &followparent_recalc, | ||
1723 | }; | ||
1724 | |||
1725 | static struct clk aes2_ick = { | ||
1726 | .name = "aes2_ick", | ||
1727 | .ops = &clkops_omap2_dflt_wait, | ||
1728 | .parent = &core_l4_ick, | ||
1729 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1730 | .enable_bit = OMAP3430_EN_AES2_SHIFT, | ||
1731 | .clkdm_name = "core_l4_clkdm", | ||
1732 | .recalc = &followparent_recalc, | ||
1733 | }; | ||
1734 | |||
1735 | static struct clk sha12_ick = { | ||
1736 | .name = "sha12_ick", | ||
1737 | .ops = &clkops_omap2_dflt_wait, | ||
1738 | .parent = &core_l4_ick, | ||
1739 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1740 | .enable_bit = OMAP3430_EN_SHA12_SHIFT, | ||
1741 | .clkdm_name = "core_l4_clkdm", | ||
1742 | .recalc = &followparent_recalc, | ||
1743 | }; | ||
1744 | |||
1745 | static struct clk des2_ick = { | ||
1746 | .name = "des2_ick", | ||
1747 | .ops = &clkops_omap2_dflt_wait, | ||
1748 | .parent = &core_l4_ick, | ||
1749 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1750 | .enable_bit = OMAP3430_EN_DES2_SHIFT, | ||
1751 | .clkdm_name = "core_l4_clkdm", | ||
1752 | .recalc = &followparent_recalc, | ||
1753 | }; | ||
1754 | |||
1755 | static struct clk mmchs2_ick = { | ||
1756 | .name = "mmchs_ick", | ||
1757 | .ops = &clkops_omap2_dflt_wait, | ||
1758 | .id = 1, | ||
1759 | .parent = &core_l4_ick, | ||
1760 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1761 | .enable_bit = OMAP3430_EN_MMC2_SHIFT, | ||
1762 | .clkdm_name = "core_l4_clkdm", | ||
1763 | .recalc = &followparent_recalc, | ||
1764 | }; | ||
1765 | |||
1766 | static struct clk mmchs1_ick = { | ||
1767 | .name = "mmchs_ick", | ||
1768 | .ops = &clkops_omap2_dflt_wait, | ||
1769 | .parent = &core_l4_ick, | ||
1770 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1771 | .enable_bit = OMAP3430_EN_MMC1_SHIFT, | ||
1772 | .clkdm_name = "core_l4_clkdm", | ||
1773 | .recalc = &followparent_recalc, | ||
1774 | }; | ||
1775 | |||
1776 | static struct clk mspro_ick = { | ||
1777 | .name = "mspro_ick", | ||
1778 | .ops = &clkops_omap2_dflt_wait, | ||
1779 | .parent = &core_l4_ick, | ||
1780 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1781 | .enable_bit = OMAP3430_EN_MSPRO_SHIFT, | ||
1782 | .clkdm_name = "core_l4_clkdm", | ||
1783 | .recalc = &followparent_recalc, | ||
1784 | }; | ||
1785 | |||
1786 | static struct clk hdq_ick = { | ||
1787 | .name = "hdq_ick", | ||
1788 | .ops = &clkops_omap2_dflt_wait, | ||
1789 | .parent = &core_l4_ick, | ||
1790 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1791 | .enable_bit = OMAP3430_EN_HDQ_SHIFT, | ||
1792 | .clkdm_name = "core_l4_clkdm", | ||
1793 | .recalc = &followparent_recalc, | ||
1794 | }; | ||
1795 | |||
1796 | static struct clk mcspi4_ick = { | ||
1797 | .name = "mcspi_ick", | ||
1798 | .ops = &clkops_omap2_dflt_wait, | ||
1799 | .id = 4, | ||
1800 | .parent = &core_l4_ick, | ||
1801 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1802 | .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, | ||
1803 | .clkdm_name = "core_l4_clkdm", | ||
1804 | .recalc = &followparent_recalc, | ||
1805 | }; | ||
1806 | |||
1807 | static struct clk mcspi3_ick = { | ||
1808 | .name = "mcspi_ick", | ||
1809 | .ops = &clkops_omap2_dflt_wait, | ||
1810 | .id = 3, | ||
1811 | .parent = &core_l4_ick, | ||
1812 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1813 | .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, | ||
1814 | .clkdm_name = "core_l4_clkdm", | ||
1815 | .recalc = &followparent_recalc, | ||
1816 | }; | ||
1817 | |||
1818 | static struct clk mcspi2_ick = { | ||
1819 | .name = "mcspi_ick", | ||
1820 | .ops = &clkops_omap2_dflt_wait, | ||
1821 | .id = 2, | ||
1822 | .parent = &core_l4_ick, | ||
1823 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1824 | .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, | ||
1825 | .clkdm_name = "core_l4_clkdm", | ||
1826 | .recalc = &followparent_recalc, | ||
1827 | }; | ||
1828 | |||
1829 | static struct clk mcspi1_ick = { | ||
1830 | .name = "mcspi_ick", | ||
1831 | .ops = &clkops_omap2_dflt_wait, | ||
1832 | .id = 1, | ||
1833 | .parent = &core_l4_ick, | ||
1834 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1835 | .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, | ||
1836 | .clkdm_name = "core_l4_clkdm", | ||
1837 | .recalc = &followparent_recalc, | ||
1838 | }; | ||
1839 | |||
1840 | static struct clk i2c3_ick = { | ||
1841 | .name = "i2c_ick", | ||
1842 | .ops = &clkops_omap2_dflt_wait, | ||
1843 | .id = 3, | ||
1844 | .parent = &core_l4_ick, | ||
1845 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1846 | .enable_bit = OMAP3430_EN_I2C3_SHIFT, | ||
1847 | .clkdm_name = "core_l4_clkdm", | ||
1848 | .recalc = &followparent_recalc, | ||
1849 | }; | ||
1850 | |||
1851 | static struct clk i2c2_ick = { | ||
1852 | .name = "i2c_ick", | ||
1853 | .ops = &clkops_omap2_dflt_wait, | ||
1854 | .id = 2, | ||
1855 | .parent = &core_l4_ick, | ||
1856 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1857 | .enable_bit = OMAP3430_EN_I2C2_SHIFT, | ||
1858 | .clkdm_name = "core_l4_clkdm", | ||
1859 | .recalc = &followparent_recalc, | ||
1860 | }; | ||
1861 | |||
1862 | static struct clk i2c1_ick = { | ||
1863 | .name = "i2c_ick", | ||
1864 | .ops = &clkops_omap2_dflt_wait, | ||
1865 | .id = 1, | ||
1866 | .parent = &core_l4_ick, | ||
1867 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1868 | .enable_bit = OMAP3430_EN_I2C1_SHIFT, | ||
1869 | .clkdm_name = "core_l4_clkdm", | ||
1870 | .recalc = &followparent_recalc, | ||
1871 | }; | ||
1872 | |||
1873 | static struct clk uart2_ick = { | ||
1874 | .name = "uart2_ick", | ||
1875 | .ops = &clkops_omap2_dflt_wait, | ||
1876 | .parent = &core_l4_ick, | ||
1877 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1878 | .enable_bit = OMAP3430_EN_UART2_SHIFT, | ||
1879 | .clkdm_name = "core_l4_clkdm", | ||
1880 | .recalc = &followparent_recalc, | ||
1881 | }; | ||
1882 | |||
1883 | static struct clk uart1_ick = { | ||
1884 | .name = "uart1_ick", | ||
1885 | .ops = &clkops_omap2_dflt_wait, | ||
1886 | .parent = &core_l4_ick, | ||
1887 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1888 | .enable_bit = OMAP3430_EN_UART1_SHIFT, | ||
1889 | .clkdm_name = "core_l4_clkdm", | ||
1890 | .recalc = &followparent_recalc, | ||
1891 | }; | ||
1892 | |||
1893 | static struct clk gpt11_ick = { | ||
1894 | .name = "gpt11_ick", | ||
1895 | .ops = &clkops_omap2_dflt_wait, | ||
1896 | .parent = &core_l4_ick, | ||
1897 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1898 | .enable_bit = OMAP3430_EN_GPT11_SHIFT, | ||
1899 | .clkdm_name = "core_l4_clkdm", | ||
1900 | .recalc = &followparent_recalc, | ||
1901 | }; | ||
1902 | |||
1903 | static struct clk gpt10_ick = { | ||
1904 | .name = "gpt10_ick", | ||
1905 | .ops = &clkops_omap2_dflt_wait, | ||
1906 | .parent = &core_l4_ick, | ||
1907 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1908 | .enable_bit = OMAP3430_EN_GPT10_SHIFT, | ||
1909 | .clkdm_name = "core_l4_clkdm", | ||
1910 | .recalc = &followparent_recalc, | ||
1911 | }; | ||
1912 | |||
1913 | static struct clk mcbsp5_ick = { | ||
1914 | .name = "mcbsp_ick", | ||
1915 | .ops = &clkops_omap2_dflt_wait, | ||
1916 | .id = 5, | ||
1917 | .parent = &core_l4_ick, | ||
1918 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1919 | .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, | ||
1920 | .clkdm_name = "core_l4_clkdm", | ||
1921 | .recalc = &followparent_recalc, | ||
1922 | }; | ||
1923 | |||
1924 | static struct clk mcbsp1_ick = { | ||
1925 | .name = "mcbsp_ick", | ||
1926 | .ops = &clkops_omap2_dflt_wait, | ||
1927 | .id = 1, | ||
1928 | .parent = &core_l4_ick, | ||
1929 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1930 | .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, | ||
1931 | .clkdm_name = "core_l4_clkdm", | ||
1932 | .recalc = &followparent_recalc, | ||
1933 | }; | ||
1934 | |||
1935 | static struct clk fac_ick = { | ||
1936 | .name = "fac_ick", | ||
1937 | .ops = &clkops_omap2_dflt_wait, | ||
1938 | .parent = &core_l4_ick, | ||
1939 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1940 | .enable_bit = OMAP3430ES1_EN_FAC_SHIFT, | ||
1941 | .clkdm_name = "core_l4_clkdm", | ||
1942 | .recalc = &followparent_recalc, | ||
1943 | }; | ||
1944 | |||
1945 | static struct clk mailboxes_ick = { | ||
1946 | .name = "mailboxes_ick", | ||
1947 | .ops = &clkops_omap2_dflt_wait, | ||
1948 | .parent = &core_l4_ick, | ||
1949 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1950 | .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT, | ||
1951 | .clkdm_name = "core_l4_clkdm", | ||
1952 | .recalc = &followparent_recalc, | ||
1953 | }; | ||
1954 | |||
1955 | static struct clk omapctrl_ick = { | ||
1956 | .name = "omapctrl_ick", | ||
1957 | .ops = &clkops_omap2_dflt_wait, | ||
1958 | .parent = &core_l4_ick, | ||
1959 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1960 | .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT, | ||
1961 | .flags = ENABLE_ON_INIT, | ||
1962 | .recalc = &followparent_recalc, | ||
1963 | }; | ||
1964 | |||
1965 | /* SSI_L4_ICK based clocks */ | ||
1966 | |||
1967 | static struct clk ssi_l4_ick = { | ||
1968 | .name = "ssi_l4_ick", | ||
1969 | .ops = &clkops_null, | ||
1970 | .parent = &l4_ick, | ||
1971 | .clkdm_name = "core_l4_clkdm", | ||
1972 | .recalc = &followparent_recalc, | ||
1973 | }; | ||
1974 | |||
1975 | static struct clk ssi_ick_3430es1 = { | ||
1976 | .name = "ssi_ick", | ||
1977 | .ops = &clkops_omap2_dflt, | ||
1978 | .parent = &ssi_l4_ick, | ||
1979 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1980 | .enable_bit = OMAP3430_EN_SSI_SHIFT, | ||
1981 | .clkdm_name = "core_l4_clkdm", | ||
1982 | .recalc = &followparent_recalc, | ||
1983 | }; | ||
1984 | |||
1985 | static struct clk ssi_ick_3430es2 = { | ||
1986 | .name = "ssi_ick", | ||
1987 | .ops = &clkops_omap3430es2_ssi_wait, | ||
1988 | .parent = &ssi_l4_ick, | ||
1989 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1990 | .enable_bit = OMAP3430_EN_SSI_SHIFT, | ||
1991 | .clkdm_name = "core_l4_clkdm", | ||
1992 | .recalc = &followparent_recalc, | ||
1993 | }; | ||
1994 | |||
1995 | /* REVISIT: Technically the TRM claims that this is CORE_CLK based, | ||
1996 | * but l4_ick makes more sense to me */ | ||
1997 | |||
1998 | static const struct clksel usb_l4_clksel[] = { | ||
1999 | { .parent = &l4_ick, .rates = div2_rates }, | ||
2000 | { .parent = NULL }, | ||
2001 | }; | ||
2002 | |||
2003 | static struct clk usb_l4_ick = { | ||
2004 | .name = "usb_l4_ick", | ||
2005 | .ops = &clkops_omap2_dflt_wait, | ||
2006 | .parent = &l4_ick, | ||
2007 | .init = &omap2_init_clksel_parent, | ||
2008 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
2009 | .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT, | ||
2010 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), | ||
2011 | .clksel_mask = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK, | ||
2012 | .clksel = usb_l4_clksel, | ||
2013 | .recalc = &omap2_clksel_recalc, | ||
2014 | }; | ||
2015 | |||
2016 | /* SECURITY_L4_ICK2 based clocks */ | ||
2017 | |||
2018 | static struct clk security_l4_ick2 = { | ||
2019 | .name = "security_l4_ick2", | ||
2020 | .ops = &clkops_null, | ||
2021 | .parent = &l4_ick, | ||
2022 | .recalc = &followparent_recalc, | ||
2023 | }; | ||
2024 | |||
2025 | static struct clk aes1_ick = { | ||
2026 | .name = "aes1_ick", | ||
2027 | .ops = &clkops_omap2_dflt_wait, | ||
2028 | .parent = &security_l4_ick2, | ||
2029 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | ||
2030 | .enable_bit = OMAP3430_EN_AES1_SHIFT, | ||
2031 | .recalc = &followparent_recalc, | ||
2032 | }; | ||
2033 | |||
2034 | static struct clk rng_ick = { | ||
2035 | .name = "rng_ick", | ||
2036 | .ops = &clkops_omap2_dflt_wait, | ||
2037 | .parent = &security_l4_ick2, | ||
2038 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | ||
2039 | .enable_bit = OMAP3430_EN_RNG_SHIFT, | ||
2040 | .recalc = &followparent_recalc, | ||
2041 | }; | ||
2042 | |||
2043 | static struct clk sha11_ick = { | ||
2044 | .name = "sha11_ick", | ||
2045 | .ops = &clkops_omap2_dflt_wait, | ||
2046 | .parent = &security_l4_ick2, | ||
2047 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | ||
2048 | .enable_bit = OMAP3430_EN_SHA11_SHIFT, | ||
2049 | .recalc = &followparent_recalc, | ||
2050 | }; | ||
2051 | |||
2052 | static struct clk des1_ick = { | ||
2053 | .name = "des1_ick", | ||
2054 | .ops = &clkops_omap2_dflt_wait, | ||
2055 | .parent = &security_l4_ick2, | ||
2056 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | ||
2057 | .enable_bit = OMAP3430_EN_DES1_SHIFT, | ||
2058 | .recalc = &followparent_recalc, | ||
2059 | }; | ||
2060 | |||
2061 | /* DSS */ | ||
2062 | static struct clk dss1_alwon_fck_3430es1 = { | ||
2063 | .name = "dss1_alwon_fck", | ||
2064 | .ops = &clkops_omap2_dflt, | ||
2065 | .parent = &dpll4_m4x2_ck, | ||
2066 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), | ||
2067 | .enable_bit = OMAP3430_EN_DSS1_SHIFT, | ||
2068 | .clkdm_name = "dss_clkdm", | ||
2069 | .recalc = &followparent_recalc, | ||
2070 | }; | ||
2071 | |||
2072 | static struct clk dss1_alwon_fck_3430es2 = { | ||
2073 | .name = "dss1_alwon_fck", | ||
2074 | .ops = &clkops_omap3430es2_dss_usbhost_wait, | ||
2075 | .parent = &dpll4_m4x2_ck, | ||
2076 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), | ||
2077 | .enable_bit = OMAP3430_EN_DSS1_SHIFT, | ||
2078 | .clkdm_name = "dss_clkdm", | ||
2079 | .recalc = &followparent_recalc, | ||
2080 | }; | ||
2081 | |||
2082 | static struct clk dss_tv_fck = { | ||
2083 | .name = "dss_tv_fck", | ||
2084 | .ops = &clkops_omap2_dflt, | ||
2085 | .parent = &omap_54m_fck, | ||
2086 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), | ||
2087 | .enable_bit = OMAP3430_EN_TV_SHIFT, | ||
2088 | .clkdm_name = "dss_clkdm", | ||
2089 | .recalc = &followparent_recalc, | ||
2090 | }; | ||
2091 | |||
2092 | static struct clk dss_96m_fck = { | ||
2093 | .name = "dss_96m_fck", | ||
2094 | .ops = &clkops_omap2_dflt, | ||
2095 | .parent = &omap_96m_fck, | ||
2096 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), | ||
2097 | .enable_bit = OMAP3430_EN_TV_SHIFT, | ||
2098 | .clkdm_name = "dss_clkdm", | ||
2099 | .recalc = &followparent_recalc, | ||
2100 | }; | ||
2101 | |||
2102 | static struct clk dss2_alwon_fck = { | ||
2103 | .name = "dss2_alwon_fck", | ||
2104 | .ops = &clkops_omap2_dflt, | ||
2105 | .parent = &sys_ck, | ||
2106 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), | ||
2107 | .enable_bit = OMAP3430_EN_DSS2_SHIFT, | ||
2108 | .clkdm_name = "dss_clkdm", | ||
2109 | .recalc = &followparent_recalc, | ||
2110 | }; | ||
2111 | |||
2112 | static struct clk dss_ick_3430es1 = { | ||
2113 | /* Handles both L3 and L4 clocks */ | ||
2114 | .name = "dss_ick", | ||
2115 | .ops = &clkops_omap2_dflt, | ||
2116 | .parent = &l4_ick, | ||
2117 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN), | ||
2118 | .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT, | ||
2119 | .clkdm_name = "dss_clkdm", | ||
2120 | .recalc = &followparent_recalc, | ||
2121 | }; | ||
2122 | |||
2123 | static struct clk dss_ick_3430es2 = { | ||
2124 | /* Handles both L3 and L4 clocks */ | ||
2125 | .name = "dss_ick", | ||
2126 | .ops = &clkops_omap3430es2_dss_usbhost_wait, | ||
2127 | .parent = &l4_ick, | ||
2128 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN), | ||
2129 | .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT, | ||
2130 | .clkdm_name = "dss_clkdm", | ||
2131 | .recalc = &followparent_recalc, | ||
2132 | }; | ||
2133 | |||
2134 | /* CAM */ | ||
2135 | |||
2136 | static struct clk cam_mclk = { | ||
2137 | .name = "cam_mclk", | ||
2138 | .ops = &clkops_omap2_dflt, | ||
2139 | .parent = &dpll4_m5x2_ck, | ||
2140 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN), | ||
2141 | .enable_bit = OMAP3430_EN_CAM_SHIFT, | ||
2142 | .clkdm_name = "cam_clkdm", | ||
2143 | .recalc = &followparent_recalc, | ||
2144 | }; | ||
2145 | |||
2146 | static struct clk cam_ick = { | ||
2147 | /* Handles both L3 and L4 clocks */ | ||
2148 | .name = "cam_ick", | ||
2149 | .ops = &clkops_omap2_dflt, | ||
2150 | .parent = &l4_ick, | ||
2151 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN), | ||
2152 | .enable_bit = OMAP3430_EN_CAM_SHIFT, | ||
2153 | .clkdm_name = "cam_clkdm", | ||
2154 | .recalc = &followparent_recalc, | ||
2155 | }; | ||
2156 | |||
2157 | static struct clk csi2_96m_fck = { | ||
2158 | .name = "csi2_96m_fck", | ||
2159 | .ops = &clkops_omap2_dflt, | ||
2160 | .parent = &core_96m_fck, | ||
2161 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN), | ||
2162 | .enable_bit = OMAP3430_EN_CSI2_SHIFT, | ||
2163 | .clkdm_name = "cam_clkdm", | ||
2164 | .recalc = &followparent_recalc, | ||
2165 | }; | ||
2166 | |||
2167 | /* USBHOST - 3430ES2 only */ | ||
2168 | |||
2169 | static struct clk usbhost_120m_fck = { | ||
2170 | .name = "usbhost_120m_fck", | ||
2171 | .ops = &clkops_omap2_dflt, | ||
2172 | .parent = &dpll5_m2_ck, | ||
2173 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), | ||
2174 | .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT, | ||
2175 | .clkdm_name = "usbhost_clkdm", | ||
2176 | .recalc = &followparent_recalc, | ||
2177 | }; | ||
2178 | |||
2179 | static struct clk usbhost_48m_fck = { | ||
2180 | .name = "usbhost_48m_fck", | ||
2181 | .ops = &clkops_omap3430es2_dss_usbhost_wait, | ||
2182 | .parent = &omap_48m_fck, | ||
2183 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), | ||
2184 | .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT, | ||
2185 | .clkdm_name = "usbhost_clkdm", | ||
2186 | .recalc = &followparent_recalc, | ||
2187 | }; | ||
2188 | |||
2189 | static struct clk usbhost_ick = { | ||
2190 | /* Handles both L3 and L4 clocks */ | ||
2191 | .name = "usbhost_ick", | ||
2192 | .ops = &clkops_omap3430es2_dss_usbhost_wait, | ||
2193 | .parent = &l4_ick, | ||
2194 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN), | ||
2195 | .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT, | ||
2196 | .clkdm_name = "usbhost_clkdm", | ||
2197 | .recalc = &followparent_recalc, | ||
2198 | }; | ||
2199 | |||
2200 | /* WKUP */ | ||
2201 | |||
2202 | static const struct clksel_rate usim_96m_rates[] = { | ||
2203 | { .div = 2, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
2204 | { .div = 4, .val = 4, .flags = RATE_IN_343X }, | ||
2205 | { .div = 8, .val = 5, .flags = RATE_IN_343X }, | ||
2206 | { .div = 10, .val = 6, .flags = RATE_IN_343X }, | ||
2207 | { .div = 0 }, | ||
2208 | }; | ||
2209 | |||
2210 | static const struct clksel_rate usim_120m_rates[] = { | ||
2211 | { .div = 4, .val = 7, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
2212 | { .div = 8, .val = 8, .flags = RATE_IN_343X }, | ||
2213 | { .div = 16, .val = 9, .flags = RATE_IN_343X }, | ||
2214 | { .div = 20, .val = 10, .flags = RATE_IN_343X }, | ||
2215 | { .div = 0 }, | ||
2216 | }; | ||
2217 | |||
2218 | static const struct clksel usim_clksel[] = { | ||
2219 | { .parent = &omap_96m_fck, .rates = usim_96m_rates }, | ||
2220 | { .parent = &dpll5_m2_ck, .rates = usim_120m_rates }, | ||
2221 | { .parent = &sys_ck, .rates = div2_rates }, | ||
2222 | { .parent = NULL }, | ||
2223 | }; | ||
2224 | |||
2225 | /* 3430ES2 only */ | ||
2226 | static struct clk usim_fck = { | ||
2227 | .name = "usim_fck", | ||
2228 | .ops = &clkops_omap2_dflt_wait, | ||
2229 | .init = &omap2_init_clksel_parent, | ||
2230 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | ||
2231 | .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT, | ||
2232 | .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), | ||
2233 | .clksel_mask = OMAP3430ES2_CLKSEL_USIMOCP_MASK, | ||
2234 | .clksel = usim_clksel, | ||
2235 | .recalc = &omap2_clksel_recalc, | ||
2236 | }; | ||
2237 | |||
2238 | /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */ | ||
2239 | static struct clk gpt1_fck = { | ||
2240 | .name = "gpt1_fck", | ||
2241 | .ops = &clkops_omap2_dflt_wait, | ||
2242 | .init = &omap2_init_clksel_parent, | ||
2243 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | ||
2244 | .enable_bit = OMAP3430_EN_GPT1_SHIFT, | ||
2245 | .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), | ||
2246 | .clksel_mask = OMAP3430_CLKSEL_GPT1_MASK, | ||
2247 | .clksel = omap343x_gpt_clksel, | ||
2248 | .clkdm_name = "wkup_clkdm", | ||
2249 | .recalc = &omap2_clksel_recalc, | ||
2250 | }; | ||
2251 | |||
2252 | static struct clk wkup_32k_fck = { | ||
2253 | .name = "wkup_32k_fck", | ||
2254 | .ops = &clkops_null, | ||
2255 | .parent = &omap_32k_fck, | ||
2256 | .clkdm_name = "wkup_clkdm", | ||
2257 | .recalc = &followparent_recalc, | ||
2258 | }; | ||
2259 | |||
2260 | static struct clk gpio1_dbck = { | ||
2261 | .name = "gpio1_dbck", | ||
2262 | .ops = &clkops_omap2_dflt, | ||
2263 | .parent = &wkup_32k_fck, | ||
2264 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | ||
2265 | .enable_bit = OMAP3430_EN_GPIO1_SHIFT, | ||
2266 | .clkdm_name = "wkup_clkdm", | ||
2267 | .recalc = &followparent_recalc, | ||
2268 | }; | ||
2269 | |||
2270 | static struct clk wdt2_fck = { | ||
2271 | .name = "wdt2_fck", | ||
2272 | .ops = &clkops_omap2_dflt_wait, | ||
2273 | .parent = &wkup_32k_fck, | ||
2274 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | ||
2275 | .enable_bit = OMAP3430_EN_WDT2_SHIFT, | ||
2276 | .clkdm_name = "wkup_clkdm", | ||
2277 | .recalc = &followparent_recalc, | ||
2278 | }; | ||
2279 | |||
2280 | static struct clk wkup_l4_ick = { | ||
2281 | .name = "wkup_l4_ick", | ||
2282 | .ops = &clkops_null, | ||
2283 | .parent = &sys_ck, | ||
2284 | .clkdm_name = "wkup_clkdm", | ||
2285 | .recalc = &followparent_recalc, | ||
2286 | }; | ||
2287 | |||
2288 | /* 3430ES2 only */ | ||
2289 | /* Never specifically named in the TRM, so we have to infer a likely name */ | ||
2290 | static struct clk usim_ick = { | ||
2291 | .name = "usim_ick", | ||
2292 | .ops = &clkops_omap2_dflt_wait, | ||
2293 | .parent = &wkup_l4_ick, | ||
2294 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | ||
2295 | .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT, | ||
2296 | .clkdm_name = "wkup_clkdm", | ||
2297 | .recalc = &followparent_recalc, | ||
2298 | }; | ||
2299 | |||
2300 | static struct clk wdt2_ick = { | ||
2301 | .name = "wdt2_ick", | ||
2302 | .ops = &clkops_omap2_dflt_wait, | ||
2303 | .parent = &wkup_l4_ick, | ||
2304 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | ||
2305 | .enable_bit = OMAP3430_EN_WDT2_SHIFT, | ||
2306 | .clkdm_name = "wkup_clkdm", | ||
2307 | .recalc = &followparent_recalc, | ||
2308 | }; | ||
2309 | |||
2310 | static struct clk wdt1_ick = { | ||
2311 | .name = "wdt1_ick", | ||
2312 | .ops = &clkops_omap2_dflt_wait, | ||
2313 | .parent = &wkup_l4_ick, | ||
2314 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | ||
2315 | .enable_bit = OMAP3430_EN_WDT1_SHIFT, | ||
2316 | .clkdm_name = "wkup_clkdm", | ||
2317 | .recalc = &followparent_recalc, | ||
2318 | }; | ||
2319 | |||
2320 | static struct clk gpio1_ick = { | ||
2321 | .name = "gpio1_ick", | ||
2322 | .ops = &clkops_omap2_dflt_wait, | ||
2323 | .parent = &wkup_l4_ick, | ||
2324 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | ||
2325 | .enable_bit = OMAP3430_EN_GPIO1_SHIFT, | ||
2326 | .clkdm_name = "wkup_clkdm", | ||
2327 | .recalc = &followparent_recalc, | ||
2328 | }; | ||
2329 | |||
2330 | static struct clk omap_32ksync_ick = { | ||
2331 | .name = "omap_32ksync_ick", | ||
2332 | .ops = &clkops_omap2_dflt_wait, | ||
2333 | .parent = &wkup_l4_ick, | ||
2334 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | ||
2335 | .enable_bit = OMAP3430_EN_32KSYNC_SHIFT, | ||
2336 | .clkdm_name = "wkup_clkdm", | ||
2337 | .recalc = &followparent_recalc, | ||
2338 | }; | ||
2339 | |||
2340 | /* XXX This clock no longer exists in 3430 TRM rev F */ | ||
2341 | static struct clk gpt12_ick = { | ||
2342 | .name = "gpt12_ick", | ||
2343 | .ops = &clkops_omap2_dflt_wait, | ||
2344 | .parent = &wkup_l4_ick, | ||
2345 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | ||
2346 | .enable_bit = OMAP3430_EN_GPT12_SHIFT, | ||
2347 | .clkdm_name = "wkup_clkdm", | ||
2348 | .recalc = &followparent_recalc, | ||
2349 | }; | ||
2350 | |||
2351 | static struct clk gpt1_ick = { | ||
2352 | .name = "gpt1_ick", | ||
2353 | .ops = &clkops_omap2_dflt_wait, | ||
2354 | .parent = &wkup_l4_ick, | ||
2355 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | ||
2356 | .enable_bit = OMAP3430_EN_GPT1_SHIFT, | ||
2357 | .clkdm_name = "wkup_clkdm", | ||
2358 | .recalc = &followparent_recalc, | ||
2359 | }; | ||
2360 | |||
2361 | |||
2362 | |||
2363 | /* PER clock domain */ | ||
2364 | |||
2365 | static struct clk per_96m_fck = { | ||
2366 | .name = "per_96m_fck", | ||
2367 | .ops = &clkops_null, | ||
2368 | .parent = &omap_96m_alwon_fck, | ||
2369 | .clkdm_name = "per_clkdm", | ||
2370 | .recalc = &followparent_recalc, | ||
2371 | }; | ||
2372 | |||
2373 | static struct clk per_48m_fck = { | ||
2374 | .name = "per_48m_fck", | ||
2375 | .ops = &clkops_null, | ||
2376 | .parent = &omap_48m_fck, | ||
2377 | .clkdm_name = "per_clkdm", | ||
2378 | .recalc = &followparent_recalc, | ||
2379 | }; | ||
2380 | |||
2381 | static struct clk uart3_fck = { | ||
2382 | .name = "uart3_fck", | ||
2383 | .ops = &clkops_omap2_dflt_wait, | ||
2384 | .parent = &per_48m_fck, | ||
2385 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | ||
2386 | .enable_bit = OMAP3430_EN_UART3_SHIFT, | ||
2387 | .clkdm_name = "per_clkdm", | ||
2388 | .recalc = &followparent_recalc, | ||
2389 | }; | ||
2390 | |||
2391 | static struct clk gpt2_fck = { | ||
2392 | .name = "gpt2_fck", | ||
2393 | .ops = &clkops_omap2_dflt_wait, | ||
2394 | .init = &omap2_init_clksel_parent, | ||
2395 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | ||
2396 | .enable_bit = OMAP3430_EN_GPT2_SHIFT, | ||
2397 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | ||
2398 | .clksel_mask = OMAP3430_CLKSEL_GPT2_MASK, | ||
2399 | .clksel = omap343x_gpt_clksel, | ||
2400 | .clkdm_name = "per_clkdm", | ||
2401 | .recalc = &omap2_clksel_recalc, | ||
2402 | }; | ||
2403 | |||
2404 | static struct clk gpt3_fck = { | ||
2405 | .name = "gpt3_fck", | ||
2406 | .ops = &clkops_omap2_dflt_wait, | ||
2407 | .init = &omap2_init_clksel_parent, | ||
2408 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | ||
2409 | .enable_bit = OMAP3430_EN_GPT3_SHIFT, | ||
2410 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | ||
2411 | .clksel_mask = OMAP3430_CLKSEL_GPT3_MASK, | ||
2412 | .clksel = omap343x_gpt_clksel, | ||
2413 | .clkdm_name = "per_clkdm", | ||
2414 | .recalc = &omap2_clksel_recalc, | ||
2415 | }; | ||
2416 | |||
2417 | static struct clk gpt4_fck = { | ||
2418 | .name = "gpt4_fck", | ||
2419 | .ops = &clkops_omap2_dflt_wait, | ||
2420 | .init = &omap2_init_clksel_parent, | ||
2421 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | ||
2422 | .enable_bit = OMAP3430_EN_GPT4_SHIFT, | ||
2423 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | ||
2424 | .clksel_mask = OMAP3430_CLKSEL_GPT4_MASK, | ||
2425 | .clksel = omap343x_gpt_clksel, | ||
2426 | .clkdm_name = "per_clkdm", | ||
2427 | .recalc = &omap2_clksel_recalc, | ||
2428 | }; | ||
2429 | |||
2430 | static struct clk gpt5_fck = { | ||
2431 | .name = "gpt5_fck", | ||
2432 | .ops = &clkops_omap2_dflt_wait, | ||
2433 | .init = &omap2_init_clksel_parent, | ||
2434 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | ||
2435 | .enable_bit = OMAP3430_EN_GPT5_SHIFT, | ||
2436 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | ||
2437 | .clksel_mask = OMAP3430_CLKSEL_GPT5_MASK, | ||
2438 | .clksel = omap343x_gpt_clksel, | ||
2439 | .clkdm_name = "per_clkdm", | ||
2440 | .recalc = &omap2_clksel_recalc, | ||
2441 | }; | ||
2442 | |||
2443 | static struct clk gpt6_fck = { | ||
2444 | .name = "gpt6_fck", | ||
2445 | .ops = &clkops_omap2_dflt_wait, | ||
2446 | .init = &omap2_init_clksel_parent, | ||
2447 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | ||
2448 | .enable_bit = OMAP3430_EN_GPT6_SHIFT, | ||
2449 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | ||
2450 | .clksel_mask = OMAP3430_CLKSEL_GPT6_MASK, | ||
2451 | .clksel = omap343x_gpt_clksel, | ||
2452 | .clkdm_name = "per_clkdm", | ||
2453 | .recalc = &omap2_clksel_recalc, | ||
2454 | }; | ||
2455 | |||
2456 | static struct clk gpt7_fck = { | ||
2457 | .name = "gpt7_fck", | ||
2458 | .ops = &clkops_omap2_dflt_wait, | ||
2459 | .init = &omap2_init_clksel_parent, | ||
2460 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | ||
2461 | .enable_bit = OMAP3430_EN_GPT7_SHIFT, | ||
2462 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | ||
2463 | .clksel_mask = OMAP3430_CLKSEL_GPT7_MASK, | ||
2464 | .clksel = omap343x_gpt_clksel, | ||
2465 | .clkdm_name = "per_clkdm", | ||
2466 | .recalc = &omap2_clksel_recalc, | ||
2467 | }; | ||
2468 | |||
2469 | static struct clk gpt8_fck = { | ||
2470 | .name = "gpt8_fck", | ||
2471 | .ops = &clkops_omap2_dflt_wait, | ||
2472 | .init = &omap2_init_clksel_parent, | ||
2473 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | ||
2474 | .enable_bit = OMAP3430_EN_GPT8_SHIFT, | ||
2475 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | ||
2476 | .clksel_mask = OMAP3430_CLKSEL_GPT8_MASK, | ||
2477 | .clksel = omap343x_gpt_clksel, | ||
2478 | .clkdm_name = "per_clkdm", | ||
2479 | .recalc = &omap2_clksel_recalc, | ||
2480 | }; | ||
2481 | |||
2482 | static struct clk gpt9_fck = { | ||
2483 | .name = "gpt9_fck", | ||
2484 | .ops = &clkops_omap2_dflt_wait, | ||
2485 | .init = &omap2_init_clksel_parent, | ||
2486 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | ||
2487 | .enable_bit = OMAP3430_EN_GPT9_SHIFT, | ||
2488 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | ||
2489 | .clksel_mask = OMAP3430_CLKSEL_GPT9_MASK, | ||
2490 | .clksel = omap343x_gpt_clksel, | ||
2491 | .clkdm_name = "per_clkdm", | ||
2492 | .recalc = &omap2_clksel_recalc, | ||
2493 | }; | ||
2494 | |||
2495 | static struct clk per_32k_alwon_fck = { | ||
2496 | .name = "per_32k_alwon_fck", | ||
2497 | .ops = &clkops_null, | ||
2498 | .parent = &omap_32k_fck, | ||
2499 | .clkdm_name = "per_clkdm", | ||
2500 | .recalc = &followparent_recalc, | ||
2501 | }; | ||
2502 | |||
2503 | static struct clk gpio6_dbck = { | ||
2504 | .name = "gpio6_dbck", | ||
2505 | .ops = &clkops_omap2_dflt, | ||
2506 | .parent = &per_32k_alwon_fck, | ||
2507 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | ||
2508 | .enable_bit = OMAP3430_EN_GPIO6_SHIFT, | ||
2509 | .clkdm_name = "per_clkdm", | ||
2510 | .recalc = &followparent_recalc, | ||
2511 | }; | ||
2512 | |||
2513 | static struct clk gpio5_dbck = { | ||
2514 | .name = "gpio5_dbck", | ||
2515 | .ops = &clkops_omap2_dflt, | ||
2516 | .parent = &per_32k_alwon_fck, | ||
2517 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | ||
2518 | .enable_bit = OMAP3430_EN_GPIO5_SHIFT, | ||
2519 | .clkdm_name = "per_clkdm", | ||
2520 | .recalc = &followparent_recalc, | ||
2521 | }; | ||
2522 | |||
2523 | static struct clk gpio4_dbck = { | ||
2524 | .name = "gpio4_dbck", | ||
2525 | .ops = &clkops_omap2_dflt, | ||
2526 | .parent = &per_32k_alwon_fck, | ||
2527 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | ||
2528 | .enable_bit = OMAP3430_EN_GPIO4_SHIFT, | ||
2529 | .clkdm_name = "per_clkdm", | ||
2530 | .recalc = &followparent_recalc, | ||
2531 | }; | ||
2532 | |||
2533 | static struct clk gpio3_dbck = { | ||
2534 | .name = "gpio3_dbck", | ||
2535 | .ops = &clkops_omap2_dflt, | ||
2536 | .parent = &per_32k_alwon_fck, | ||
2537 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | ||
2538 | .enable_bit = OMAP3430_EN_GPIO3_SHIFT, | ||
2539 | .clkdm_name = "per_clkdm", | ||
2540 | .recalc = &followparent_recalc, | ||
2541 | }; | ||
2542 | |||
2543 | static struct clk gpio2_dbck = { | ||
2544 | .name = "gpio2_dbck", | ||
2545 | .ops = &clkops_omap2_dflt, | ||
2546 | .parent = &per_32k_alwon_fck, | ||
2547 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | ||
2548 | .enable_bit = OMAP3430_EN_GPIO2_SHIFT, | ||
2549 | .clkdm_name = "per_clkdm", | ||
2550 | .recalc = &followparent_recalc, | ||
2551 | }; | ||
2552 | |||
2553 | static struct clk wdt3_fck = { | ||
2554 | .name = "wdt3_fck", | ||
2555 | .ops = &clkops_omap2_dflt_wait, | ||
2556 | .parent = &per_32k_alwon_fck, | ||
2557 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | ||
2558 | .enable_bit = OMAP3430_EN_WDT3_SHIFT, | ||
2559 | .clkdm_name = "per_clkdm", | ||
2560 | .recalc = &followparent_recalc, | ||
2561 | }; | ||
2562 | |||
2563 | static struct clk per_l4_ick = { | ||
2564 | .name = "per_l4_ick", | ||
2565 | .ops = &clkops_null, | ||
2566 | .parent = &l4_ick, | ||
2567 | .clkdm_name = "per_clkdm", | ||
2568 | .recalc = &followparent_recalc, | ||
2569 | }; | ||
2570 | |||
2571 | static struct clk gpio6_ick = { | ||
2572 | .name = "gpio6_ick", | ||
2573 | .ops = &clkops_omap2_dflt_wait, | ||
2574 | .parent = &per_l4_ick, | ||
2575 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | ||
2576 | .enable_bit = OMAP3430_EN_GPIO6_SHIFT, | ||
2577 | .clkdm_name = "per_clkdm", | ||
2578 | .recalc = &followparent_recalc, | ||
2579 | }; | ||
2580 | |||
2581 | static struct clk gpio5_ick = { | ||
2582 | .name = "gpio5_ick", | ||
2583 | .ops = &clkops_omap2_dflt_wait, | ||
2584 | .parent = &per_l4_ick, | ||
2585 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | ||
2586 | .enable_bit = OMAP3430_EN_GPIO5_SHIFT, | ||
2587 | .clkdm_name = "per_clkdm", | ||
2588 | .recalc = &followparent_recalc, | ||
2589 | }; | ||
2590 | |||
2591 | static struct clk gpio4_ick = { | ||
2592 | .name = "gpio4_ick", | ||
2593 | .ops = &clkops_omap2_dflt_wait, | ||
2594 | .parent = &per_l4_ick, | ||
2595 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | ||
2596 | .enable_bit = OMAP3430_EN_GPIO4_SHIFT, | ||
2597 | .clkdm_name = "per_clkdm", | ||
2598 | .recalc = &followparent_recalc, | ||
2599 | }; | ||
2600 | |||
2601 | static struct clk gpio3_ick = { | ||
2602 | .name = "gpio3_ick", | ||
2603 | .ops = &clkops_omap2_dflt_wait, | ||
2604 | .parent = &per_l4_ick, | ||
2605 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | ||
2606 | .enable_bit = OMAP3430_EN_GPIO3_SHIFT, | ||
2607 | .clkdm_name = "per_clkdm", | ||
2608 | .recalc = &followparent_recalc, | ||
2609 | }; | ||
2610 | |||
2611 | static struct clk gpio2_ick = { | ||
2612 | .name = "gpio2_ick", | ||
2613 | .ops = &clkops_omap2_dflt_wait, | ||
2614 | .parent = &per_l4_ick, | ||
2615 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | ||
2616 | .enable_bit = OMAP3430_EN_GPIO2_SHIFT, | ||
2617 | .clkdm_name = "per_clkdm", | ||
2618 | .recalc = &followparent_recalc, | ||
2619 | }; | ||
2620 | |||
2621 | static struct clk wdt3_ick = { | ||
2622 | .name = "wdt3_ick", | ||
2623 | .ops = &clkops_omap2_dflt_wait, | ||
2624 | .parent = &per_l4_ick, | ||
2625 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | ||
2626 | .enable_bit = OMAP3430_EN_WDT3_SHIFT, | ||
2627 | .clkdm_name = "per_clkdm", | ||
2628 | .recalc = &followparent_recalc, | ||
2629 | }; | ||
2630 | |||
2631 | static struct clk uart3_ick = { | ||
2632 | .name = "uart3_ick", | ||
2633 | .ops = &clkops_omap2_dflt_wait, | ||
2634 | .parent = &per_l4_ick, | ||
2635 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | ||
2636 | .enable_bit = OMAP3430_EN_UART3_SHIFT, | ||
2637 | .clkdm_name = "per_clkdm", | ||
2638 | .recalc = &followparent_recalc, | ||
2639 | }; | ||
2640 | |||
2641 | static struct clk gpt9_ick = { | ||
2642 | .name = "gpt9_ick", | ||
2643 | .ops = &clkops_omap2_dflt_wait, | ||
2644 | .parent = &per_l4_ick, | ||
2645 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | ||
2646 | .enable_bit = OMAP3430_EN_GPT9_SHIFT, | ||
2647 | .clkdm_name = "per_clkdm", | ||
2648 | .recalc = &followparent_recalc, | ||
2649 | }; | ||
2650 | |||
2651 | static struct clk gpt8_ick = { | ||
2652 | .name = "gpt8_ick", | ||
2653 | .ops = &clkops_omap2_dflt_wait, | ||
2654 | .parent = &per_l4_ick, | ||
2655 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | ||
2656 | .enable_bit = OMAP3430_EN_GPT8_SHIFT, | ||
2657 | .clkdm_name = "per_clkdm", | ||
2658 | .recalc = &followparent_recalc, | ||
2659 | }; | ||
2660 | |||
2661 | static struct clk gpt7_ick = { | ||
2662 | .name = "gpt7_ick", | ||
2663 | .ops = &clkops_omap2_dflt_wait, | ||
2664 | .parent = &per_l4_ick, | ||
2665 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | ||
2666 | .enable_bit = OMAP3430_EN_GPT7_SHIFT, | ||
2667 | .clkdm_name = "per_clkdm", | ||
2668 | .recalc = &followparent_recalc, | ||
2669 | }; | ||
2670 | |||
2671 | static struct clk gpt6_ick = { | ||
2672 | .name = "gpt6_ick", | ||
2673 | .ops = &clkops_omap2_dflt_wait, | ||
2674 | .parent = &per_l4_ick, | ||
2675 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | ||
2676 | .enable_bit = OMAP3430_EN_GPT6_SHIFT, | ||
2677 | .clkdm_name = "per_clkdm", | ||
2678 | .recalc = &followparent_recalc, | ||
2679 | }; | ||
2680 | |||
2681 | static struct clk gpt5_ick = { | ||
2682 | .name = "gpt5_ick", | ||
2683 | .ops = &clkops_omap2_dflt_wait, | ||
2684 | .parent = &per_l4_ick, | ||
2685 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | ||
2686 | .enable_bit = OMAP3430_EN_GPT5_SHIFT, | ||
2687 | .clkdm_name = "per_clkdm", | ||
2688 | .recalc = &followparent_recalc, | ||
2689 | }; | ||
2690 | |||
2691 | static struct clk gpt4_ick = { | ||
2692 | .name = "gpt4_ick", | ||
2693 | .ops = &clkops_omap2_dflt_wait, | ||
2694 | .parent = &per_l4_ick, | ||
2695 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | ||
2696 | .enable_bit = OMAP3430_EN_GPT4_SHIFT, | ||
2697 | .clkdm_name = "per_clkdm", | ||
2698 | .recalc = &followparent_recalc, | ||
2699 | }; | ||
2700 | |||
2701 | static struct clk gpt3_ick = { | ||
2702 | .name = "gpt3_ick", | ||
2703 | .ops = &clkops_omap2_dflt_wait, | ||
2704 | .parent = &per_l4_ick, | ||
2705 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | ||
2706 | .enable_bit = OMAP3430_EN_GPT3_SHIFT, | ||
2707 | .clkdm_name = "per_clkdm", | ||
2708 | .recalc = &followparent_recalc, | ||
2709 | }; | ||
2710 | |||
2711 | static struct clk gpt2_ick = { | ||
2712 | .name = "gpt2_ick", | ||
2713 | .ops = &clkops_omap2_dflt_wait, | ||
2714 | .parent = &per_l4_ick, | ||
2715 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | ||
2716 | .enable_bit = OMAP3430_EN_GPT2_SHIFT, | ||
2717 | .clkdm_name = "per_clkdm", | ||
2718 | .recalc = &followparent_recalc, | ||
2719 | }; | ||
2720 | |||
2721 | static struct clk mcbsp2_ick = { | ||
2722 | .name = "mcbsp_ick", | ||
2723 | .ops = &clkops_omap2_dflt_wait, | ||
2724 | .id = 2, | ||
2725 | .parent = &per_l4_ick, | ||
2726 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | ||
2727 | .enable_bit = OMAP3430_EN_MCBSP2_SHIFT, | ||
2728 | .clkdm_name = "per_clkdm", | ||
2729 | .recalc = &followparent_recalc, | ||
2730 | }; | ||
2731 | |||
2732 | static struct clk mcbsp3_ick = { | ||
2733 | .name = "mcbsp_ick", | ||
2734 | .ops = &clkops_omap2_dflt_wait, | ||
2735 | .id = 3, | ||
2736 | .parent = &per_l4_ick, | ||
2737 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | ||
2738 | .enable_bit = OMAP3430_EN_MCBSP3_SHIFT, | ||
2739 | .clkdm_name = "per_clkdm", | ||
2740 | .recalc = &followparent_recalc, | ||
2741 | }; | ||
2742 | |||
2743 | static struct clk mcbsp4_ick = { | ||
2744 | .name = "mcbsp_ick", | ||
2745 | .ops = &clkops_omap2_dflt_wait, | ||
2746 | .id = 4, | ||
2747 | .parent = &per_l4_ick, | ||
2748 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | ||
2749 | .enable_bit = OMAP3430_EN_MCBSP4_SHIFT, | ||
2750 | .clkdm_name = "per_clkdm", | ||
2751 | .recalc = &followparent_recalc, | ||
2752 | }; | ||
2753 | |||
2754 | static const struct clksel mcbsp_234_clksel[] = { | ||
2755 | { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates }, | ||
2756 | { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, | ||
2757 | { .parent = NULL } | ||
2758 | }; | ||
2759 | |||
2760 | static struct clk mcbsp2_fck = { | ||
2761 | .name = "mcbsp_fck", | ||
2762 | .ops = &clkops_omap2_dflt_wait, | ||
2763 | .id = 2, | ||
2764 | .init = &omap2_init_clksel_parent, | ||
2765 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | ||
2766 | .enable_bit = OMAP3430_EN_MCBSP2_SHIFT, | ||
2767 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), | ||
2768 | .clksel_mask = OMAP2_MCBSP2_CLKS_MASK, | ||
2769 | .clksel = mcbsp_234_clksel, | ||
2770 | .clkdm_name = "per_clkdm", | ||
2771 | .recalc = &omap2_clksel_recalc, | ||
2772 | }; | ||
2773 | |||
2774 | static struct clk mcbsp3_fck = { | ||
2775 | .name = "mcbsp_fck", | ||
2776 | .ops = &clkops_omap2_dflt_wait, | ||
2777 | .id = 3, | ||
2778 | .init = &omap2_init_clksel_parent, | ||
2779 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | ||
2780 | .enable_bit = OMAP3430_EN_MCBSP3_SHIFT, | ||
2781 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), | ||
2782 | .clksel_mask = OMAP2_MCBSP3_CLKS_MASK, | ||
2783 | .clksel = mcbsp_234_clksel, | ||
2784 | .clkdm_name = "per_clkdm", | ||
2785 | .recalc = &omap2_clksel_recalc, | ||
2786 | }; | ||
2787 | |||
2788 | static struct clk mcbsp4_fck = { | ||
2789 | .name = "mcbsp_fck", | ||
2790 | .ops = &clkops_omap2_dflt_wait, | ||
2791 | .id = 4, | ||
2792 | .init = &omap2_init_clksel_parent, | ||
2793 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | ||
2794 | .enable_bit = OMAP3430_EN_MCBSP4_SHIFT, | ||
2795 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), | ||
2796 | .clksel_mask = OMAP2_MCBSP4_CLKS_MASK, | ||
2797 | .clksel = mcbsp_234_clksel, | ||
2798 | .clkdm_name = "per_clkdm", | ||
2799 | .recalc = &omap2_clksel_recalc, | ||
2800 | }; | ||
2801 | |||
2802 | /* EMU clocks */ | ||
2803 | |||
2804 | /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */ | ||
2805 | |||
2806 | static const struct clksel_rate emu_src_sys_rates[] = { | ||
2807 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
2808 | { .div = 0 }, | ||
2809 | }; | ||
2810 | |||
2811 | static const struct clksel_rate emu_src_core_rates[] = { | ||
2812 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
2813 | { .div = 0 }, | ||
2814 | }; | ||
2815 | |||
2816 | static const struct clksel_rate emu_src_per_rates[] = { | ||
2817 | { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
2818 | { .div = 0 }, | ||
2819 | }; | ||
2820 | |||
2821 | static const struct clksel_rate emu_src_mpu_rates[] = { | ||
2822 | { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
2823 | { .div = 0 }, | ||
2824 | }; | ||
2825 | |||
2826 | static const struct clksel emu_src_clksel[] = { | ||
2827 | { .parent = &sys_ck, .rates = emu_src_sys_rates }, | ||
2828 | { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates }, | ||
2829 | { .parent = &emu_per_alwon_ck, .rates = emu_src_per_rates }, | ||
2830 | { .parent = &emu_mpu_alwon_ck, .rates = emu_src_mpu_rates }, | ||
2831 | { .parent = NULL }, | ||
2832 | }; | ||
2833 | |||
2834 | /* | ||
2835 | * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only | ||
2836 | * to switch the source of some of the EMU clocks. | ||
2837 | * XXX Are there CLKEN bits for these EMU clks? | ||
2838 | */ | 6 | */ |
2839 | static struct clk emu_src_ck = { | ||
2840 | .name = "emu_src_ck", | ||
2841 | .ops = &clkops_null, | ||
2842 | .init = &omap2_init_clksel_parent, | ||
2843 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | ||
2844 | .clksel_mask = OMAP3430_MUX_CTRL_MASK, | ||
2845 | .clksel = emu_src_clksel, | ||
2846 | .clkdm_name = "emu_clkdm", | ||
2847 | .recalc = &omap2_clksel_recalc, | ||
2848 | }; | ||
2849 | |||
2850 | static const struct clksel_rate pclk_emu_rates[] = { | ||
2851 | { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
2852 | { .div = 3, .val = 3, .flags = RATE_IN_343X }, | ||
2853 | { .div = 4, .val = 4, .flags = RATE_IN_343X }, | ||
2854 | { .div = 6, .val = 6, .flags = RATE_IN_343X }, | ||
2855 | { .div = 0 }, | ||
2856 | }; | ||
2857 | |||
2858 | static const struct clksel pclk_emu_clksel[] = { | ||
2859 | { .parent = &emu_src_ck, .rates = pclk_emu_rates }, | ||
2860 | { .parent = NULL }, | ||
2861 | }; | ||
2862 | |||
2863 | static struct clk pclk_fck = { | ||
2864 | .name = "pclk_fck", | ||
2865 | .ops = &clkops_null, | ||
2866 | .init = &omap2_init_clksel_parent, | ||
2867 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | ||
2868 | .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK, | ||
2869 | .clksel = pclk_emu_clksel, | ||
2870 | .clkdm_name = "emu_clkdm", | ||
2871 | .recalc = &omap2_clksel_recalc, | ||
2872 | }; | ||
2873 | |||
2874 | static const struct clksel_rate pclkx2_emu_rates[] = { | ||
2875 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
2876 | { .div = 2, .val = 2, .flags = RATE_IN_343X }, | ||
2877 | { .div = 3, .val = 3, .flags = RATE_IN_343X }, | ||
2878 | { .div = 0 }, | ||
2879 | }; | ||
2880 | |||
2881 | static const struct clksel pclkx2_emu_clksel[] = { | ||
2882 | { .parent = &emu_src_ck, .rates = pclkx2_emu_rates }, | ||
2883 | { .parent = NULL }, | ||
2884 | }; | ||
2885 | |||
2886 | static struct clk pclkx2_fck = { | ||
2887 | .name = "pclkx2_fck", | ||
2888 | .ops = &clkops_null, | ||
2889 | .init = &omap2_init_clksel_parent, | ||
2890 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | ||
2891 | .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK, | ||
2892 | .clksel = pclkx2_emu_clksel, | ||
2893 | .clkdm_name = "emu_clkdm", | ||
2894 | .recalc = &omap2_clksel_recalc, | ||
2895 | }; | ||
2896 | |||
2897 | static const struct clksel atclk_emu_clksel[] = { | ||
2898 | { .parent = &emu_src_ck, .rates = div2_rates }, | ||
2899 | { .parent = NULL }, | ||
2900 | }; | ||
2901 | |||
2902 | static struct clk atclk_fck = { | ||
2903 | .name = "atclk_fck", | ||
2904 | .ops = &clkops_null, | ||
2905 | .init = &omap2_init_clksel_parent, | ||
2906 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | ||
2907 | .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK, | ||
2908 | .clksel = atclk_emu_clksel, | ||
2909 | .clkdm_name = "emu_clkdm", | ||
2910 | .recalc = &omap2_clksel_recalc, | ||
2911 | }; | ||
2912 | |||
2913 | static struct clk traceclk_src_fck = { | ||
2914 | .name = "traceclk_src_fck", | ||
2915 | .ops = &clkops_null, | ||
2916 | .init = &omap2_init_clksel_parent, | ||
2917 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | ||
2918 | .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK, | ||
2919 | .clksel = emu_src_clksel, | ||
2920 | .clkdm_name = "emu_clkdm", | ||
2921 | .recalc = &omap2_clksel_recalc, | ||
2922 | }; | ||
2923 | |||
2924 | static const struct clksel_rate traceclk_rates[] = { | ||
2925 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
2926 | { .div = 2, .val = 2, .flags = RATE_IN_343X }, | ||
2927 | { .div = 4, .val = 4, .flags = RATE_IN_343X }, | ||
2928 | { .div = 0 }, | ||
2929 | }; | ||
2930 | |||
2931 | static const struct clksel traceclk_clksel[] = { | ||
2932 | { .parent = &traceclk_src_fck, .rates = traceclk_rates }, | ||
2933 | { .parent = NULL }, | ||
2934 | }; | ||
2935 | |||
2936 | static struct clk traceclk_fck = { | ||
2937 | .name = "traceclk_fck", | ||
2938 | .ops = &clkops_null, | ||
2939 | .init = &omap2_init_clksel_parent, | ||
2940 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | ||
2941 | .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK, | ||
2942 | .clksel = traceclk_clksel, | ||
2943 | .clkdm_name = "emu_clkdm", | ||
2944 | .recalc = &omap2_clksel_recalc, | ||
2945 | }; | ||
2946 | |||
2947 | /* SR clocks */ | ||
2948 | |||
2949 | /* SmartReflex fclk (VDD1) */ | ||
2950 | static struct clk sr1_fck = { | ||
2951 | .name = "sr1_fck", | ||
2952 | .ops = &clkops_omap2_dflt_wait, | ||
2953 | .parent = &sys_ck, | ||
2954 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | ||
2955 | .enable_bit = OMAP3430_EN_SR1_SHIFT, | ||
2956 | .recalc = &followparent_recalc, | ||
2957 | }; | ||
2958 | |||
2959 | /* SmartReflex fclk (VDD2) */ | ||
2960 | static struct clk sr2_fck = { | ||
2961 | .name = "sr2_fck", | ||
2962 | .ops = &clkops_omap2_dflt_wait, | ||
2963 | .parent = &sys_ck, | ||
2964 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | ||
2965 | .enable_bit = OMAP3430_EN_SR2_SHIFT, | ||
2966 | .recalc = &followparent_recalc, | ||
2967 | }; | ||
2968 | 7 | ||
2969 | static struct clk sr_l4_ick = { | 8 | #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_34XX_H |
2970 | .name = "sr_l4_ick", | 9 | #define __ARCH_ARM_MACH_OMAP2_CLOCK_34XX_H |
2971 | .ops = &clkops_null, /* RMK: missing? */ | ||
2972 | .parent = &l4_ick, | ||
2973 | .clkdm_name = "core_l4_clkdm", | ||
2974 | .recalc = &followparent_recalc, | ||
2975 | }; | ||
2976 | 10 | ||
2977 | /* SECURE_32K_FCK clocks */ | 11 | int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate); |
12 | int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate); | ||
13 | void omap3_clk_lock_dpll5(void); | ||
2978 | 14 | ||
2979 | static struct clk gpt12_fck = { | 15 | extern struct clk *sdrc_ick_p; |
2980 | .name = "gpt12_fck", | 16 | extern struct clk *arm_fck_p; |
2981 | .ops = &clkops_null, | ||
2982 | .parent = &secure_32k_fck, | ||
2983 | .recalc = &followparent_recalc, | ||
2984 | }; | ||
2985 | 17 | ||
2986 | static struct clk wdt1_fck = { | 18 | /* OMAP34xx-specific clkops */ |
2987 | .name = "wdt1_fck", | 19 | extern const struct clkops clkops_omap3430es2_ssi_wait; |
2988 | .ops = &clkops_null, | 20 | extern const struct clkops clkops_omap3430es2_hsotgusb_wait; |
2989 | .parent = &secure_32k_fck, | 21 | extern const struct clkops clkops_omap3430es2_dss_usbhost_wait; |
2990 | .recalc = &followparent_recalc, | 22 | extern const struct clkops clkops_noncore_dpll_ops; |
2991 | }; | ||
2992 | 23 | ||
2993 | #endif | 24 | #endif |
diff --git a/arch/arm/mach-omap2/clock34xx_data.c b/arch/arm/mach-omap2/clock34xx_data.c new file mode 100644 index 000000000000..8bdcc9cc7f9a --- /dev/null +++ b/arch/arm/mach-omap2/clock34xx_data.c | |||
@@ -0,0 +1,3289 @@ | |||
1 | /* | ||
2 | * OMAP3 clock data | ||
3 | * | ||
4 | * Copyright (C) 2007-2009 Texas Instruments, Inc. | ||
5 | * Copyright (C) 2007-2009 Nokia Corporation | ||
6 | * | ||
7 | * Written by Paul Walmsley | ||
8 | * With many device clock fixes by Kevin Hilman and Jouni Högander | ||
9 | * DPLL bypass clock support added by Roman Tereshonkov | ||
10 | * | ||
11 | */ | ||
12 | |||
13 | /* | ||
14 | * Virtual clocks are introduced as convenient tools. | ||
15 | * They are sources for other clocks and not supposed | ||
16 | * to be requested from drivers directly. | ||
17 | */ | ||
18 | |||
19 | #include <linux/module.h> | ||
20 | #include <linux/kernel.h> | ||
21 | #include <linux/clk.h> | ||
22 | |||
23 | #include <plat/control.h> | ||
24 | #include <plat/clkdev_omap.h> | ||
25 | |||
26 | #include "clock.h" | ||
27 | #include "clock34xx.h" | ||
28 | #include "cm.h" | ||
29 | #include "cm-regbits-34xx.h" | ||
30 | #include "prm.h" | ||
31 | #include "prm-regbits-34xx.h" | ||
32 | |||
33 | /* | ||
34 | * clocks | ||
35 | */ | ||
36 | |||
37 | #define OMAP_CM_REGADDR OMAP34XX_CM_REGADDR | ||
38 | |||
39 | /* Maximum DPLL multiplier, divider values for OMAP3 */ | ||
40 | #define OMAP3_MAX_DPLL_MULT 2048 | ||
41 | #define OMAP3_MAX_DPLL_DIV 128 | ||
42 | |||
43 | /* | ||
44 | * DPLL1 supplies clock to the MPU. | ||
45 | * DPLL2 supplies clock to the IVA2. | ||
46 | * DPLL3 supplies CORE domain clocks. | ||
47 | * DPLL4 supplies peripheral clocks. | ||
48 | * DPLL5 supplies other peripheral clocks (USBHOST, USIM). | ||
49 | */ | ||
50 | |||
51 | /* Forward declarations for DPLL bypass clocks */ | ||
52 | static struct clk dpll1_fck; | ||
53 | static struct clk dpll2_fck; | ||
54 | |||
55 | /* PRM CLOCKS */ | ||
56 | |||
57 | /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */ | ||
58 | static struct clk omap_32k_fck = { | ||
59 | .name = "omap_32k_fck", | ||
60 | .ops = &clkops_null, | ||
61 | .rate = 32768, | ||
62 | .flags = RATE_FIXED, | ||
63 | }; | ||
64 | |||
65 | static struct clk secure_32k_fck = { | ||
66 | .name = "secure_32k_fck", | ||
67 | .ops = &clkops_null, | ||
68 | .rate = 32768, | ||
69 | .flags = RATE_FIXED, | ||
70 | }; | ||
71 | |||
72 | /* Virtual source clocks for osc_sys_ck */ | ||
73 | static struct clk virt_12m_ck = { | ||
74 | .name = "virt_12m_ck", | ||
75 | .ops = &clkops_null, | ||
76 | .rate = 12000000, | ||
77 | .flags = RATE_FIXED, | ||
78 | }; | ||
79 | |||
80 | static struct clk virt_13m_ck = { | ||
81 | .name = "virt_13m_ck", | ||
82 | .ops = &clkops_null, | ||
83 | .rate = 13000000, | ||
84 | .flags = RATE_FIXED, | ||
85 | }; | ||
86 | |||
87 | static struct clk virt_16_8m_ck = { | ||
88 | .name = "virt_16_8m_ck", | ||
89 | .ops = &clkops_null, | ||
90 | .rate = 16800000, | ||
91 | .flags = RATE_FIXED, | ||
92 | }; | ||
93 | |||
94 | static struct clk virt_19_2m_ck = { | ||
95 | .name = "virt_19_2m_ck", | ||
96 | .ops = &clkops_null, | ||
97 | .rate = 19200000, | ||
98 | .flags = RATE_FIXED, | ||
99 | }; | ||
100 | |||
101 | static struct clk virt_26m_ck = { | ||
102 | .name = "virt_26m_ck", | ||
103 | .ops = &clkops_null, | ||
104 | .rate = 26000000, | ||
105 | .flags = RATE_FIXED, | ||
106 | }; | ||
107 | |||
108 | static struct clk virt_38_4m_ck = { | ||
109 | .name = "virt_38_4m_ck", | ||
110 | .ops = &clkops_null, | ||
111 | .rate = 38400000, | ||
112 | .flags = RATE_FIXED, | ||
113 | }; | ||
114 | |||
115 | static const struct clksel_rate osc_sys_12m_rates[] = { | ||
116 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
117 | { .div = 0 } | ||
118 | }; | ||
119 | |||
120 | static const struct clksel_rate osc_sys_13m_rates[] = { | ||
121 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
122 | { .div = 0 } | ||
123 | }; | ||
124 | |||
125 | static const struct clksel_rate osc_sys_16_8m_rates[] = { | ||
126 | { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE }, | ||
127 | { .div = 0 } | ||
128 | }; | ||
129 | |||
130 | static const struct clksel_rate osc_sys_19_2m_rates[] = { | ||
131 | { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
132 | { .div = 0 } | ||
133 | }; | ||
134 | |||
135 | static const struct clksel_rate osc_sys_26m_rates[] = { | ||
136 | { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
137 | { .div = 0 } | ||
138 | }; | ||
139 | |||
140 | static const struct clksel_rate osc_sys_38_4m_rates[] = { | ||
141 | { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
142 | { .div = 0 } | ||
143 | }; | ||
144 | |||
145 | static const struct clksel osc_sys_clksel[] = { | ||
146 | { .parent = &virt_12m_ck, .rates = osc_sys_12m_rates }, | ||
147 | { .parent = &virt_13m_ck, .rates = osc_sys_13m_rates }, | ||
148 | { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates }, | ||
149 | { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates }, | ||
150 | { .parent = &virt_26m_ck, .rates = osc_sys_26m_rates }, | ||
151 | { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates }, | ||
152 | { .parent = NULL }, | ||
153 | }; | ||
154 | |||
155 | /* Oscillator clock */ | ||
156 | /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */ | ||
157 | static struct clk osc_sys_ck = { | ||
158 | .name = "osc_sys_ck", | ||
159 | .ops = &clkops_null, | ||
160 | .init = &omap2_init_clksel_parent, | ||
161 | .clksel_reg = OMAP3430_PRM_CLKSEL, | ||
162 | .clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK, | ||
163 | .clksel = osc_sys_clksel, | ||
164 | /* REVISIT: deal with autoextclkmode? */ | ||
165 | .flags = RATE_FIXED, | ||
166 | .recalc = &omap2_clksel_recalc, | ||
167 | }; | ||
168 | |||
169 | static const struct clksel_rate div2_rates[] = { | ||
170 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
171 | { .div = 2, .val = 2, .flags = RATE_IN_343X }, | ||
172 | { .div = 0 } | ||
173 | }; | ||
174 | |||
175 | static const struct clksel sys_clksel[] = { | ||
176 | { .parent = &osc_sys_ck, .rates = div2_rates }, | ||
177 | { .parent = NULL } | ||
178 | }; | ||
179 | |||
180 | /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */ | ||
181 | /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */ | ||
182 | static struct clk sys_ck = { | ||
183 | .name = "sys_ck", | ||
184 | .ops = &clkops_null, | ||
185 | .parent = &osc_sys_ck, | ||
186 | .init = &omap2_init_clksel_parent, | ||
187 | .clksel_reg = OMAP3430_PRM_CLKSRC_CTRL, | ||
188 | .clksel_mask = OMAP_SYSCLKDIV_MASK, | ||
189 | .clksel = sys_clksel, | ||
190 | .recalc = &omap2_clksel_recalc, | ||
191 | }; | ||
192 | |||
193 | static struct clk sys_altclk = { | ||
194 | .name = "sys_altclk", | ||
195 | .ops = &clkops_null, | ||
196 | }; | ||
197 | |||
198 | /* Optional external clock input for some McBSPs */ | ||
199 | static struct clk mcbsp_clks = { | ||
200 | .name = "mcbsp_clks", | ||
201 | .ops = &clkops_null, | ||
202 | }; | ||
203 | |||
204 | /* PRM EXTERNAL CLOCK OUTPUT */ | ||
205 | |||
206 | static struct clk sys_clkout1 = { | ||
207 | .name = "sys_clkout1", | ||
208 | .ops = &clkops_omap2_dflt, | ||
209 | .parent = &osc_sys_ck, | ||
210 | .enable_reg = OMAP3430_PRM_CLKOUT_CTRL, | ||
211 | .enable_bit = OMAP3430_CLKOUT_EN_SHIFT, | ||
212 | .recalc = &followparent_recalc, | ||
213 | }; | ||
214 | |||
215 | /* DPLLS */ | ||
216 | |||
217 | /* CM CLOCKS */ | ||
218 | |||
219 | static const struct clksel_rate div16_dpll_rates[] = { | ||
220 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
221 | { .div = 2, .val = 2, .flags = RATE_IN_343X }, | ||
222 | { .div = 3, .val = 3, .flags = RATE_IN_343X }, | ||
223 | { .div = 4, .val = 4, .flags = RATE_IN_343X }, | ||
224 | { .div = 5, .val = 5, .flags = RATE_IN_343X }, | ||
225 | { .div = 6, .val = 6, .flags = RATE_IN_343X }, | ||
226 | { .div = 7, .val = 7, .flags = RATE_IN_343X }, | ||
227 | { .div = 8, .val = 8, .flags = RATE_IN_343X }, | ||
228 | { .div = 9, .val = 9, .flags = RATE_IN_343X }, | ||
229 | { .div = 10, .val = 10, .flags = RATE_IN_343X }, | ||
230 | { .div = 11, .val = 11, .flags = RATE_IN_343X }, | ||
231 | { .div = 12, .val = 12, .flags = RATE_IN_343X }, | ||
232 | { .div = 13, .val = 13, .flags = RATE_IN_343X }, | ||
233 | { .div = 14, .val = 14, .flags = RATE_IN_343X }, | ||
234 | { .div = 15, .val = 15, .flags = RATE_IN_343X }, | ||
235 | { .div = 16, .val = 16, .flags = RATE_IN_343X }, | ||
236 | { .div = 0 } | ||
237 | }; | ||
238 | |||
239 | /* DPLL1 */ | ||
240 | /* MPU clock source */ | ||
241 | /* Type: DPLL */ | ||
242 | static struct dpll_data dpll1_dd = { | ||
243 | .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), | ||
244 | .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK, | ||
245 | .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK, | ||
246 | .clk_bypass = &dpll1_fck, | ||
247 | .clk_ref = &sys_ck, | ||
248 | .freqsel_mask = OMAP3430_MPU_DPLL_FREQSEL_MASK, | ||
249 | .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL), | ||
250 | .enable_mask = OMAP3430_EN_MPU_DPLL_MASK, | ||
251 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), | ||
252 | .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT, | ||
253 | .recal_en_bit = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT, | ||
254 | .recal_st_bit = OMAP3430_MPU_DPLL_ST_SHIFT, | ||
255 | .autoidle_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL), | ||
256 | .autoidle_mask = OMAP3430_AUTO_MPU_DPLL_MASK, | ||
257 | .idlest_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), | ||
258 | .idlest_mask = OMAP3430_ST_MPU_CLK_MASK, | ||
259 | .max_multiplier = OMAP3_MAX_DPLL_MULT, | ||
260 | .min_divider = 1, | ||
261 | .max_divider = OMAP3_MAX_DPLL_DIV, | ||
262 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE | ||
263 | }; | ||
264 | |||
265 | static struct clk dpll1_ck = { | ||
266 | .name = "dpll1_ck", | ||
267 | .ops = &clkops_null, | ||
268 | .parent = &sys_ck, | ||
269 | .dpll_data = &dpll1_dd, | ||
270 | .round_rate = &omap2_dpll_round_rate, | ||
271 | .set_rate = &omap3_noncore_dpll_set_rate, | ||
272 | .clkdm_name = "dpll1_clkdm", | ||
273 | .recalc = &omap3_dpll_recalc, | ||
274 | }; | ||
275 | |||
276 | /* | ||
277 | * This virtual clock provides the CLKOUTX2 output from the DPLL if the | ||
278 | * DPLL isn't bypassed. | ||
279 | */ | ||
280 | static struct clk dpll1_x2_ck = { | ||
281 | .name = "dpll1_x2_ck", | ||
282 | .ops = &clkops_null, | ||
283 | .parent = &dpll1_ck, | ||
284 | .clkdm_name = "dpll1_clkdm", | ||
285 | .recalc = &omap3_clkoutx2_recalc, | ||
286 | }; | ||
287 | |||
288 | /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */ | ||
289 | static const struct clksel div16_dpll1_x2m2_clksel[] = { | ||
290 | { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates }, | ||
291 | { .parent = NULL } | ||
292 | }; | ||
293 | |||
294 | /* | ||
295 | * Does not exist in the TRM - needed to separate the M2 divider from | ||
296 | * bypass selection in mpu_ck | ||
297 | */ | ||
298 | static struct clk dpll1_x2m2_ck = { | ||
299 | .name = "dpll1_x2m2_ck", | ||
300 | .ops = &clkops_null, | ||
301 | .parent = &dpll1_x2_ck, | ||
302 | .init = &omap2_init_clksel_parent, | ||
303 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL), | ||
304 | .clksel_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK, | ||
305 | .clksel = div16_dpll1_x2m2_clksel, | ||
306 | .clkdm_name = "dpll1_clkdm", | ||
307 | .recalc = &omap2_clksel_recalc, | ||
308 | }; | ||
309 | |||
310 | /* DPLL2 */ | ||
311 | /* IVA2 clock source */ | ||
312 | /* Type: DPLL */ | ||
313 | |||
314 | static struct dpll_data dpll2_dd = { | ||
315 | .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), | ||
316 | .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK, | ||
317 | .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK, | ||
318 | .clk_bypass = &dpll2_fck, | ||
319 | .clk_ref = &sys_ck, | ||
320 | .freqsel_mask = OMAP3430_IVA2_DPLL_FREQSEL_MASK, | ||
321 | .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL), | ||
322 | .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK, | ||
323 | .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) | | ||
324 | (1 << DPLL_LOW_POWER_BYPASS), | ||
325 | .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT, | ||
326 | .recal_en_bit = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT, | ||
327 | .recal_st_bit = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT, | ||
328 | .autoidle_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL), | ||
329 | .autoidle_mask = OMAP3430_AUTO_IVA2_DPLL_MASK, | ||
330 | .idlest_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL), | ||
331 | .idlest_mask = OMAP3430_ST_IVA2_CLK_MASK, | ||
332 | .max_multiplier = OMAP3_MAX_DPLL_MULT, | ||
333 | .min_divider = 1, | ||
334 | .max_divider = OMAP3_MAX_DPLL_DIV, | ||
335 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE | ||
336 | }; | ||
337 | |||
338 | static struct clk dpll2_ck = { | ||
339 | .name = "dpll2_ck", | ||
340 | .ops = &clkops_noncore_dpll_ops, | ||
341 | .parent = &sys_ck, | ||
342 | .dpll_data = &dpll2_dd, | ||
343 | .round_rate = &omap2_dpll_round_rate, | ||
344 | .set_rate = &omap3_noncore_dpll_set_rate, | ||
345 | .clkdm_name = "dpll2_clkdm", | ||
346 | .recalc = &omap3_dpll_recalc, | ||
347 | }; | ||
348 | |||
349 | static const struct clksel div16_dpll2_m2x2_clksel[] = { | ||
350 | { .parent = &dpll2_ck, .rates = div16_dpll_rates }, | ||
351 | { .parent = NULL } | ||
352 | }; | ||
353 | |||
354 | /* | ||
355 | * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT | ||
356 | * or CLKOUTX2. CLKOUT seems most plausible. | ||
357 | */ | ||
358 | static struct clk dpll2_m2_ck = { | ||
359 | .name = "dpll2_m2_ck", | ||
360 | .ops = &clkops_null, | ||
361 | .parent = &dpll2_ck, | ||
362 | .init = &omap2_init_clksel_parent, | ||
363 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, | ||
364 | OMAP3430_CM_CLKSEL2_PLL), | ||
365 | .clksel_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK, | ||
366 | .clksel = div16_dpll2_m2x2_clksel, | ||
367 | .clkdm_name = "dpll2_clkdm", | ||
368 | .recalc = &omap2_clksel_recalc, | ||
369 | }; | ||
370 | |||
371 | /* | ||
372 | * DPLL3 | ||
373 | * Source clock for all interfaces and for some device fclks | ||
374 | * REVISIT: Also supports fast relock bypass - not included below | ||
375 | */ | ||
376 | static struct dpll_data dpll3_dd = { | ||
377 | .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | ||
378 | .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK, | ||
379 | .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK, | ||
380 | .clk_bypass = &sys_ck, | ||
381 | .clk_ref = &sys_ck, | ||
382 | .freqsel_mask = OMAP3430_CORE_DPLL_FREQSEL_MASK, | ||
383 | .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | ||
384 | .enable_mask = OMAP3430_EN_CORE_DPLL_MASK, | ||
385 | .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT, | ||
386 | .recal_en_bit = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT, | ||
387 | .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT, | ||
388 | .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE), | ||
389 | .autoidle_mask = OMAP3430_AUTO_CORE_DPLL_MASK, | ||
390 | .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), | ||
391 | .idlest_mask = OMAP3430_ST_CORE_CLK_MASK, | ||
392 | .max_multiplier = OMAP3_MAX_DPLL_MULT, | ||
393 | .min_divider = 1, | ||
394 | .max_divider = OMAP3_MAX_DPLL_DIV, | ||
395 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE | ||
396 | }; | ||
397 | |||
398 | static struct clk dpll3_ck = { | ||
399 | .name = "dpll3_ck", | ||
400 | .ops = &clkops_null, | ||
401 | .parent = &sys_ck, | ||
402 | .dpll_data = &dpll3_dd, | ||
403 | .round_rate = &omap2_dpll_round_rate, | ||
404 | .clkdm_name = "dpll3_clkdm", | ||
405 | .recalc = &omap3_dpll_recalc, | ||
406 | }; | ||
407 | |||
408 | /* | ||
409 | * This virtual clock provides the CLKOUTX2 output from the DPLL if the | ||
410 | * DPLL isn't bypassed | ||
411 | */ | ||
412 | static struct clk dpll3_x2_ck = { | ||
413 | .name = "dpll3_x2_ck", | ||
414 | .ops = &clkops_null, | ||
415 | .parent = &dpll3_ck, | ||
416 | .clkdm_name = "dpll3_clkdm", | ||
417 | .recalc = &omap3_clkoutx2_recalc, | ||
418 | }; | ||
419 | |||
420 | static const struct clksel_rate div31_dpll3_rates[] = { | ||
421 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
422 | { .div = 2, .val = 2, .flags = RATE_IN_343X }, | ||
423 | { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 }, | ||
424 | { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 }, | ||
425 | { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 }, | ||
426 | { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 }, | ||
427 | { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 }, | ||
428 | { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 }, | ||
429 | { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 }, | ||
430 | { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 }, | ||
431 | { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 }, | ||
432 | { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 }, | ||
433 | { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 }, | ||
434 | { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 }, | ||
435 | { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 }, | ||
436 | { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 }, | ||
437 | { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 }, | ||
438 | { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 }, | ||
439 | { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 }, | ||
440 | { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 }, | ||
441 | { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 }, | ||
442 | { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 }, | ||
443 | { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 }, | ||
444 | { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 }, | ||
445 | { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 }, | ||
446 | { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 }, | ||
447 | { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 }, | ||
448 | { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 }, | ||
449 | { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 }, | ||
450 | { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 }, | ||
451 | { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 }, | ||
452 | { .div = 0 }, | ||
453 | }; | ||
454 | |||
455 | static const struct clksel div31_dpll3m2_clksel[] = { | ||
456 | { .parent = &dpll3_ck, .rates = div31_dpll3_rates }, | ||
457 | { .parent = NULL } | ||
458 | }; | ||
459 | |||
460 | /* DPLL3 output M2 - primary control point for CORE speed */ | ||
461 | static struct clk dpll3_m2_ck = { | ||
462 | .name = "dpll3_m2_ck", | ||
463 | .ops = &clkops_null, | ||
464 | .parent = &dpll3_ck, | ||
465 | .init = &omap2_init_clksel_parent, | ||
466 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | ||
467 | .clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK, | ||
468 | .clksel = div31_dpll3m2_clksel, | ||
469 | .clkdm_name = "dpll3_clkdm", | ||
470 | .round_rate = &omap2_clksel_round_rate, | ||
471 | .set_rate = &omap3_core_dpll_m2_set_rate, | ||
472 | .recalc = &omap2_clksel_recalc, | ||
473 | }; | ||
474 | |||
475 | static struct clk core_ck = { | ||
476 | .name = "core_ck", | ||
477 | .ops = &clkops_null, | ||
478 | .parent = &dpll3_m2_ck, | ||
479 | .recalc = &followparent_recalc, | ||
480 | }; | ||
481 | |||
482 | static struct clk dpll3_m2x2_ck = { | ||
483 | .name = "dpll3_m2x2_ck", | ||
484 | .ops = &clkops_null, | ||
485 | .parent = &dpll3_m2_ck, | ||
486 | .clkdm_name = "dpll3_clkdm", | ||
487 | .recalc = &omap3_clkoutx2_recalc, | ||
488 | }; | ||
489 | |||
490 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | ||
491 | static const struct clksel div16_dpll3_clksel[] = { | ||
492 | { .parent = &dpll3_ck, .rates = div16_dpll_rates }, | ||
493 | { .parent = NULL } | ||
494 | }; | ||
495 | |||
496 | /* This virtual clock is the source for dpll3_m3x2_ck */ | ||
497 | static struct clk dpll3_m3_ck = { | ||
498 | .name = "dpll3_m3_ck", | ||
499 | .ops = &clkops_null, | ||
500 | .parent = &dpll3_ck, | ||
501 | .init = &omap2_init_clksel_parent, | ||
502 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | ||
503 | .clksel_mask = OMAP3430_DIV_DPLL3_MASK, | ||
504 | .clksel = div16_dpll3_clksel, | ||
505 | .clkdm_name = "dpll3_clkdm", | ||
506 | .recalc = &omap2_clksel_recalc, | ||
507 | }; | ||
508 | |||
509 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | ||
510 | static struct clk dpll3_m3x2_ck = { | ||
511 | .name = "dpll3_m3x2_ck", | ||
512 | .ops = &clkops_omap2_dflt_wait, | ||
513 | .parent = &dpll3_m3_ck, | ||
514 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | ||
515 | .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT, | ||
516 | .flags = INVERT_ENABLE, | ||
517 | .clkdm_name = "dpll3_clkdm", | ||
518 | .recalc = &omap3_clkoutx2_recalc, | ||
519 | }; | ||
520 | |||
521 | static struct clk emu_core_alwon_ck = { | ||
522 | .name = "emu_core_alwon_ck", | ||
523 | .ops = &clkops_null, | ||
524 | .parent = &dpll3_m3x2_ck, | ||
525 | .clkdm_name = "dpll3_clkdm", | ||
526 | .recalc = &followparent_recalc, | ||
527 | }; | ||
528 | |||
529 | /* DPLL4 */ | ||
530 | /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */ | ||
531 | /* Type: DPLL */ | ||
532 | static struct dpll_data dpll4_dd = { | ||
533 | .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2), | ||
534 | .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK, | ||
535 | .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK, | ||
536 | .clk_bypass = &sys_ck, | ||
537 | .clk_ref = &sys_ck, | ||
538 | .freqsel_mask = OMAP3430_PERIPH_DPLL_FREQSEL_MASK, | ||
539 | .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | ||
540 | .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK, | ||
541 | .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED), | ||
542 | .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT, | ||
543 | .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT, | ||
544 | .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT, | ||
545 | .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE), | ||
546 | .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK, | ||
547 | .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), | ||
548 | .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK, | ||
549 | .max_multiplier = OMAP3_MAX_DPLL_MULT, | ||
550 | .min_divider = 1, | ||
551 | .max_divider = OMAP3_MAX_DPLL_DIV, | ||
552 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE | ||
553 | }; | ||
554 | |||
555 | static struct clk dpll4_ck = { | ||
556 | .name = "dpll4_ck", | ||
557 | .ops = &clkops_noncore_dpll_ops, | ||
558 | .parent = &sys_ck, | ||
559 | .dpll_data = &dpll4_dd, | ||
560 | .round_rate = &omap2_dpll_round_rate, | ||
561 | .set_rate = &omap3_dpll4_set_rate, | ||
562 | .clkdm_name = "dpll4_clkdm", | ||
563 | .recalc = &omap3_dpll_recalc, | ||
564 | }; | ||
565 | |||
566 | /* | ||
567 | * This virtual clock provides the CLKOUTX2 output from the DPLL if the | ||
568 | * DPLL isn't bypassed -- | ||
569 | * XXX does this serve any downstream clocks? | ||
570 | */ | ||
571 | static struct clk dpll4_x2_ck = { | ||
572 | .name = "dpll4_x2_ck", | ||
573 | .ops = &clkops_null, | ||
574 | .parent = &dpll4_ck, | ||
575 | .clkdm_name = "dpll4_clkdm", | ||
576 | .recalc = &omap3_clkoutx2_recalc, | ||
577 | }; | ||
578 | |||
579 | static const struct clksel div16_dpll4_clksel[] = { | ||
580 | { .parent = &dpll4_ck, .rates = div16_dpll_rates }, | ||
581 | { .parent = NULL } | ||
582 | }; | ||
583 | |||
584 | /* This virtual clock is the source for dpll4_m2x2_ck */ | ||
585 | static struct clk dpll4_m2_ck = { | ||
586 | .name = "dpll4_m2_ck", | ||
587 | .ops = &clkops_null, | ||
588 | .parent = &dpll4_ck, | ||
589 | .init = &omap2_init_clksel_parent, | ||
590 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3), | ||
591 | .clksel_mask = OMAP3430_DIV_96M_MASK, | ||
592 | .clksel = div16_dpll4_clksel, | ||
593 | .clkdm_name = "dpll4_clkdm", | ||
594 | .recalc = &omap2_clksel_recalc, | ||
595 | }; | ||
596 | |||
597 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | ||
598 | static struct clk dpll4_m2x2_ck = { | ||
599 | .name = "dpll4_m2x2_ck", | ||
600 | .ops = &clkops_omap2_dflt_wait, | ||
601 | .parent = &dpll4_m2_ck, | ||
602 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | ||
603 | .enable_bit = OMAP3430_PWRDN_96M_SHIFT, | ||
604 | .flags = INVERT_ENABLE, | ||
605 | .clkdm_name = "dpll4_clkdm", | ||
606 | .recalc = &omap3_clkoutx2_recalc, | ||
607 | }; | ||
608 | |||
609 | /* | ||
610 | * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as | ||
611 | * PRM_96M_ALWON_(F)CLK. Two clocks then emerge from the PRM: | ||
612 | * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and | ||
613 | * CM_96K_(F)CLK. | ||
614 | */ | ||
615 | static struct clk omap_96m_alwon_fck = { | ||
616 | .name = "omap_96m_alwon_fck", | ||
617 | .ops = &clkops_null, | ||
618 | .parent = &dpll4_m2x2_ck, | ||
619 | .recalc = &followparent_recalc, | ||
620 | }; | ||
621 | |||
622 | static struct clk cm_96m_fck = { | ||
623 | .name = "cm_96m_fck", | ||
624 | .ops = &clkops_null, | ||
625 | .parent = &omap_96m_alwon_fck, | ||
626 | .recalc = &followparent_recalc, | ||
627 | }; | ||
628 | |||
629 | static const struct clksel_rate omap_96m_dpll_rates[] = { | ||
630 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
631 | { .div = 0 } | ||
632 | }; | ||
633 | |||
634 | static const struct clksel_rate omap_96m_sys_rates[] = { | ||
635 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
636 | { .div = 0 } | ||
637 | }; | ||
638 | |||
639 | static const struct clksel omap_96m_fck_clksel[] = { | ||
640 | { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates }, | ||
641 | { .parent = &sys_ck, .rates = omap_96m_sys_rates }, | ||
642 | { .parent = NULL } | ||
643 | }; | ||
644 | |||
645 | static struct clk omap_96m_fck = { | ||
646 | .name = "omap_96m_fck", | ||
647 | .ops = &clkops_null, | ||
648 | .parent = &sys_ck, | ||
649 | .init = &omap2_init_clksel_parent, | ||
650 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | ||
651 | .clksel_mask = OMAP3430_SOURCE_96M_MASK, | ||
652 | .clksel = omap_96m_fck_clksel, | ||
653 | .recalc = &omap2_clksel_recalc, | ||
654 | }; | ||
655 | |||
656 | /* This virtual clock is the source for dpll4_m3x2_ck */ | ||
657 | static struct clk dpll4_m3_ck = { | ||
658 | .name = "dpll4_m3_ck", | ||
659 | .ops = &clkops_null, | ||
660 | .parent = &dpll4_ck, | ||
661 | .init = &omap2_init_clksel_parent, | ||
662 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), | ||
663 | .clksel_mask = OMAP3430_CLKSEL_TV_MASK, | ||
664 | .clksel = div16_dpll4_clksel, | ||
665 | .clkdm_name = "dpll4_clkdm", | ||
666 | .recalc = &omap2_clksel_recalc, | ||
667 | }; | ||
668 | |||
669 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | ||
670 | static struct clk dpll4_m3x2_ck = { | ||
671 | .name = "dpll4_m3x2_ck", | ||
672 | .ops = &clkops_omap2_dflt_wait, | ||
673 | .parent = &dpll4_m3_ck, | ||
674 | .init = &omap2_init_clksel_parent, | ||
675 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | ||
676 | .enable_bit = OMAP3430_PWRDN_TV_SHIFT, | ||
677 | .flags = INVERT_ENABLE, | ||
678 | .clkdm_name = "dpll4_clkdm", | ||
679 | .recalc = &omap3_clkoutx2_recalc, | ||
680 | }; | ||
681 | |||
682 | static const struct clksel_rate omap_54m_d4m3x2_rates[] = { | ||
683 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
684 | { .div = 0 } | ||
685 | }; | ||
686 | |||
687 | static const struct clksel_rate omap_54m_alt_rates[] = { | ||
688 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
689 | { .div = 0 } | ||
690 | }; | ||
691 | |||
692 | static const struct clksel omap_54m_clksel[] = { | ||
693 | { .parent = &dpll4_m3x2_ck, .rates = omap_54m_d4m3x2_rates }, | ||
694 | { .parent = &sys_altclk, .rates = omap_54m_alt_rates }, | ||
695 | { .parent = NULL } | ||
696 | }; | ||
697 | |||
698 | static struct clk omap_54m_fck = { | ||
699 | .name = "omap_54m_fck", | ||
700 | .ops = &clkops_null, | ||
701 | .init = &omap2_init_clksel_parent, | ||
702 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | ||
703 | .clksel_mask = OMAP3430_SOURCE_54M_MASK, | ||
704 | .clksel = omap_54m_clksel, | ||
705 | .recalc = &omap2_clksel_recalc, | ||
706 | }; | ||
707 | |||
708 | static const struct clksel_rate omap_48m_cm96m_rates[] = { | ||
709 | { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
710 | { .div = 0 } | ||
711 | }; | ||
712 | |||
713 | static const struct clksel_rate omap_48m_alt_rates[] = { | ||
714 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
715 | { .div = 0 } | ||
716 | }; | ||
717 | |||
718 | static const struct clksel omap_48m_clksel[] = { | ||
719 | { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates }, | ||
720 | { .parent = &sys_altclk, .rates = omap_48m_alt_rates }, | ||
721 | { .parent = NULL } | ||
722 | }; | ||
723 | |||
724 | static struct clk omap_48m_fck = { | ||
725 | .name = "omap_48m_fck", | ||
726 | .ops = &clkops_null, | ||
727 | .init = &omap2_init_clksel_parent, | ||
728 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | ||
729 | .clksel_mask = OMAP3430_SOURCE_48M_MASK, | ||
730 | .clksel = omap_48m_clksel, | ||
731 | .recalc = &omap2_clksel_recalc, | ||
732 | }; | ||
733 | |||
734 | static struct clk omap_12m_fck = { | ||
735 | .name = "omap_12m_fck", | ||
736 | .ops = &clkops_null, | ||
737 | .parent = &omap_48m_fck, | ||
738 | .fixed_div = 4, | ||
739 | .recalc = &omap2_fixed_divisor_recalc, | ||
740 | }; | ||
741 | |||
742 | /* This virstual clock is the source for dpll4_m4x2_ck */ | ||
743 | static struct clk dpll4_m4_ck = { | ||
744 | .name = "dpll4_m4_ck", | ||
745 | .ops = &clkops_null, | ||
746 | .parent = &dpll4_ck, | ||
747 | .init = &omap2_init_clksel_parent, | ||
748 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), | ||
749 | .clksel_mask = OMAP3430_CLKSEL_DSS1_MASK, | ||
750 | .clksel = div16_dpll4_clksel, | ||
751 | .clkdm_name = "dpll4_clkdm", | ||
752 | .recalc = &omap2_clksel_recalc, | ||
753 | .set_rate = &omap2_clksel_set_rate, | ||
754 | .round_rate = &omap2_clksel_round_rate, | ||
755 | }; | ||
756 | |||
757 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | ||
758 | static struct clk dpll4_m4x2_ck = { | ||
759 | .name = "dpll4_m4x2_ck", | ||
760 | .ops = &clkops_omap2_dflt_wait, | ||
761 | .parent = &dpll4_m4_ck, | ||
762 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | ||
763 | .enable_bit = OMAP3430_PWRDN_CAM_SHIFT, | ||
764 | .flags = INVERT_ENABLE, | ||
765 | .clkdm_name = "dpll4_clkdm", | ||
766 | .recalc = &omap3_clkoutx2_recalc, | ||
767 | }; | ||
768 | |||
769 | /* This virtual clock is the source for dpll4_m5x2_ck */ | ||
770 | static struct clk dpll4_m5_ck = { | ||
771 | .name = "dpll4_m5_ck", | ||
772 | .ops = &clkops_null, | ||
773 | .parent = &dpll4_ck, | ||
774 | .init = &omap2_init_clksel_parent, | ||
775 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL), | ||
776 | .clksel_mask = OMAP3430_CLKSEL_CAM_MASK, | ||
777 | .clksel = div16_dpll4_clksel, | ||
778 | .clkdm_name = "dpll4_clkdm", | ||
779 | .recalc = &omap2_clksel_recalc, | ||
780 | }; | ||
781 | |||
782 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | ||
783 | static struct clk dpll4_m5x2_ck = { | ||
784 | .name = "dpll4_m5x2_ck", | ||
785 | .ops = &clkops_omap2_dflt_wait, | ||
786 | .parent = &dpll4_m5_ck, | ||
787 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | ||
788 | .enable_bit = OMAP3430_PWRDN_CAM_SHIFT, | ||
789 | .flags = INVERT_ENABLE, | ||
790 | .clkdm_name = "dpll4_clkdm", | ||
791 | .recalc = &omap3_clkoutx2_recalc, | ||
792 | }; | ||
793 | |||
794 | /* This virtual clock is the source for dpll4_m6x2_ck */ | ||
795 | static struct clk dpll4_m6_ck = { | ||
796 | .name = "dpll4_m6_ck", | ||
797 | .ops = &clkops_null, | ||
798 | .parent = &dpll4_ck, | ||
799 | .init = &omap2_init_clksel_parent, | ||
800 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | ||
801 | .clksel_mask = OMAP3430_DIV_DPLL4_MASK, | ||
802 | .clksel = div16_dpll4_clksel, | ||
803 | .clkdm_name = "dpll4_clkdm", | ||
804 | .recalc = &omap2_clksel_recalc, | ||
805 | }; | ||
806 | |||
807 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | ||
808 | static struct clk dpll4_m6x2_ck = { | ||
809 | .name = "dpll4_m6x2_ck", | ||
810 | .ops = &clkops_omap2_dflt_wait, | ||
811 | .parent = &dpll4_m6_ck, | ||
812 | .init = &omap2_init_clksel_parent, | ||
813 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | ||
814 | .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT, | ||
815 | .flags = INVERT_ENABLE, | ||
816 | .clkdm_name = "dpll4_clkdm", | ||
817 | .recalc = &omap3_clkoutx2_recalc, | ||
818 | }; | ||
819 | |||
820 | static struct clk emu_per_alwon_ck = { | ||
821 | .name = "emu_per_alwon_ck", | ||
822 | .ops = &clkops_null, | ||
823 | .parent = &dpll4_m6x2_ck, | ||
824 | .clkdm_name = "dpll4_clkdm", | ||
825 | .recalc = &followparent_recalc, | ||
826 | }; | ||
827 | |||
828 | /* DPLL5 */ | ||
829 | /* Supplies 120MHz clock, USIM source clock */ | ||
830 | /* Type: DPLL */ | ||
831 | /* 3430ES2 only */ | ||
832 | static struct dpll_data dpll5_dd = { | ||
833 | .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4), | ||
834 | .mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK, | ||
835 | .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK, | ||
836 | .clk_bypass = &sys_ck, | ||
837 | .clk_ref = &sys_ck, | ||
838 | .freqsel_mask = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK, | ||
839 | .control_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2), | ||
840 | .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK, | ||
841 | .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED), | ||
842 | .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT, | ||
843 | .recal_en_bit = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT, | ||
844 | .recal_st_bit = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT, | ||
845 | .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL), | ||
846 | .autoidle_mask = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK, | ||
847 | .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2), | ||
848 | .idlest_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK, | ||
849 | .max_multiplier = OMAP3_MAX_DPLL_MULT, | ||
850 | .min_divider = 1, | ||
851 | .max_divider = OMAP3_MAX_DPLL_DIV, | ||
852 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE | ||
853 | }; | ||
854 | |||
855 | static struct clk dpll5_ck = { | ||
856 | .name = "dpll5_ck", | ||
857 | .ops = &clkops_noncore_dpll_ops, | ||
858 | .parent = &sys_ck, | ||
859 | .dpll_data = &dpll5_dd, | ||
860 | .round_rate = &omap2_dpll_round_rate, | ||
861 | .set_rate = &omap3_noncore_dpll_set_rate, | ||
862 | .clkdm_name = "dpll5_clkdm", | ||
863 | .recalc = &omap3_dpll_recalc, | ||
864 | }; | ||
865 | |||
866 | static const struct clksel div16_dpll5_clksel[] = { | ||
867 | { .parent = &dpll5_ck, .rates = div16_dpll_rates }, | ||
868 | { .parent = NULL } | ||
869 | }; | ||
870 | |||
871 | static struct clk dpll5_m2_ck = { | ||
872 | .name = "dpll5_m2_ck", | ||
873 | .ops = &clkops_null, | ||
874 | .parent = &dpll5_ck, | ||
875 | .init = &omap2_init_clksel_parent, | ||
876 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5), | ||
877 | .clksel_mask = OMAP3430ES2_DIV_120M_MASK, | ||
878 | .clksel = div16_dpll5_clksel, | ||
879 | .clkdm_name = "dpll5_clkdm", | ||
880 | .recalc = &omap2_clksel_recalc, | ||
881 | }; | ||
882 | |||
883 | /* CM EXTERNAL CLOCK OUTPUTS */ | ||
884 | |||
885 | static const struct clksel_rate clkout2_src_core_rates[] = { | ||
886 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
887 | { .div = 0 } | ||
888 | }; | ||
889 | |||
890 | static const struct clksel_rate clkout2_src_sys_rates[] = { | ||
891 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
892 | { .div = 0 } | ||
893 | }; | ||
894 | |||
895 | static const struct clksel_rate clkout2_src_96m_rates[] = { | ||
896 | { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
897 | { .div = 0 } | ||
898 | }; | ||
899 | |||
900 | static const struct clksel_rate clkout2_src_54m_rates[] = { | ||
901 | { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
902 | { .div = 0 } | ||
903 | }; | ||
904 | |||
905 | static const struct clksel clkout2_src_clksel[] = { | ||
906 | { .parent = &core_ck, .rates = clkout2_src_core_rates }, | ||
907 | { .parent = &sys_ck, .rates = clkout2_src_sys_rates }, | ||
908 | { .parent = &cm_96m_fck, .rates = clkout2_src_96m_rates }, | ||
909 | { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates }, | ||
910 | { .parent = NULL } | ||
911 | }; | ||
912 | |||
913 | static struct clk clkout2_src_ck = { | ||
914 | .name = "clkout2_src_ck", | ||
915 | .ops = &clkops_omap2_dflt, | ||
916 | .init = &omap2_init_clksel_parent, | ||
917 | .enable_reg = OMAP3430_CM_CLKOUT_CTRL, | ||
918 | .enable_bit = OMAP3430_CLKOUT2_EN_SHIFT, | ||
919 | .clksel_reg = OMAP3430_CM_CLKOUT_CTRL, | ||
920 | .clksel_mask = OMAP3430_CLKOUT2SOURCE_MASK, | ||
921 | .clksel = clkout2_src_clksel, | ||
922 | .clkdm_name = "core_clkdm", | ||
923 | .recalc = &omap2_clksel_recalc, | ||
924 | }; | ||
925 | |||
926 | static const struct clksel_rate sys_clkout2_rates[] = { | ||
927 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
928 | { .div = 2, .val = 1, .flags = RATE_IN_343X }, | ||
929 | { .div = 4, .val = 2, .flags = RATE_IN_343X }, | ||
930 | { .div = 8, .val = 3, .flags = RATE_IN_343X }, | ||
931 | { .div = 16, .val = 4, .flags = RATE_IN_343X }, | ||
932 | { .div = 0 }, | ||
933 | }; | ||
934 | |||
935 | static const struct clksel sys_clkout2_clksel[] = { | ||
936 | { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates }, | ||
937 | { .parent = NULL }, | ||
938 | }; | ||
939 | |||
940 | static struct clk sys_clkout2 = { | ||
941 | .name = "sys_clkout2", | ||
942 | .ops = &clkops_null, | ||
943 | .init = &omap2_init_clksel_parent, | ||
944 | .clksel_reg = OMAP3430_CM_CLKOUT_CTRL, | ||
945 | .clksel_mask = OMAP3430_CLKOUT2_DIV_MASK, | ||
946 | .clksel = sys_clkout2_clksel, | ||
947 | .recalc = &omap2_clksel_recalc, | ||
948 | }; | ||
949 | |||
950 | /* CM OUTPUT CLOCKS */ | ||
951 | |||
952 | static struct clk corex2_fck = { | ||
953 | .name = "corex2_fck", | ||
954 | .ops = &clkops_null, | ||
955 | .parent = &dpll3_m2x2_ck, | ||
956 | .recalc = &followparent_recalc, | ||
957 | }; | ||
958 | |||
959 | /* DPLL power domain clock controls */ | ||
960 | |||
961 | static const struct clksel_rate div4_rates[] = { | ||
962 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
963 | { .div = 2, .val = 2, .flags = RATE_IN_343X }, | ||
964 | { .div = 4, .val = 4, .flags = RATE_IN_343X }, | ||
965 | { .div = 0 } | ||
966 | }; | ||
967 | |||
968 | static const struct clksel div4_core_clksel[] = { | ||
969 | { .parent = &core_ck, .rates = div4_rates }, | ||
970 | { .parent = NULL } | ||
971 | }; | ||
972 | |||
973 | /* | ||
974 | * REVISIT: Are these in DPLL power domain or CM power domain? docs | ||
975 | * may be inconsistent here? | ||
976 | */ | ||
977 | static struct clk dpll1_fck = { | ||
978 | .name = "dpll1_fck", | ||
979 | .ops = &clkops_null, | ||
980 | .parent = &core_ck, | ||
981 | .init = &omap2_init_clksel_parent, | ||
982 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), | ||
983 | .clksel_mask = OMAP3430_MPU_CLK_SRC_MASK, | ||
984 | .clksel = div4_core_clksel, | ||
985 | .recalc = &omap2_clksel_recalc, | ||
986 | }; | ||
987 | |||
988 | static struct clk mpu_ck = { | ||
989 | .name = "mpu_ck", | ||
990 | .ops = &clkops_null, | ||
991 | .parent = &dpll1_x2m2_ck, | ||
992 | .clkdm_name = "mpu_clkdm", | ||
993 | .recalc = &followparent_recalc, | ||
994 | }; | ||
995 | |||
996 | /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */ | ||
997 | static const struct clksel_rate arm_fck_rates[] = { | ||
998 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
999 | { .div = 2, .val = 1, .flags = RATE_IN_343X }, | ||
1000 | { .div = 0 }, | ||
1001 | }; | ||
1002 | |||
1003 | static const struct clksel arm_fck_clksel[] = { | ||
1004 | { .parent = &mpu_ck, .rates = arm_fck_rates }, | ||
1005 | { .parent = NULL } | ||
1006 | }; | ||
1007 | |||
1008 | static struct clk arm_fck = { | ||
1009 | .name = "arm_fck", | ||
1010 | .ops = &clkops_null, | ||
1011 | .parent = &mpu_ck, | ||
1012 | .init = &omap2_init_clksel_parent, | ||
1013 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), | ||
1014 | .clksel_mask = OMAP3430_ST_MPU_CLK_MASK, | ||
1015 | .clksel = arm_fck_clksel, | ||
1016 | .clkdm_name = "mpu_clkdm", | ||
1017 | .recalc = &omap2_clksel_recalc, | ||
1018 | }; | ||
1019 | |||
1020 | /* XXX What about neon_clkdm ? */ | ||
1021 | |||
1022 | /* | ||
1023 | * REVISIT: This clock is never specifically defined in the 3430 TRM, | ||
1024 | * although it is referenced - so this is a guess | ||
1025 | */ | ||
1026 | static struct clk emu_mpu_alwon_ck = { | ||
1027 | .name = "emu_mpu_alwon_ck", | ||
1028 | .ops = &clkops_null, | ||
1029 | .parent = &mpu_ck, | ||
1030 | .recalc = &followparent_recalc, | ||
1031 | }; | ||
1032 | |||
1033 | static struct clk dpll2_fck = { | ||
1034 | .name = "dpll2_fck", | ||
1035 | .ops = &clkops_null, | ||
1036 | .parent = &core_ck, | ||
1037 | .init = &omap2_init_clksel_parent, | ||
1038 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), | ||
1039 | .clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK, | ||
1040 | .clksel = div4_core_clksel, | ||
1041 | .recalc = &omap2_clksel_recalc, | ||
1042 | }; | ||
1043 | |||
1044 | static struct clk iva2_ck = { | ||
1045 | .name = "iva2_ck", | ||
1046 | .ops = &clkops_omap2_dflt_wait, | ||
1047 | .parent = &dpll2_m2_ck, | ||
1048 | .init = &omap2_init_clksel_parent, | ||
1049 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN), | ||
1050 | .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT, | ||
1051 | .clkdm_name = "iva2_clkdm", | ||
1052 | .recalc = &followparent_recalc, | ||
1053 | }; | ||
1054 | |||
1055 | /* Common interface clocks */ | ||
1056 | |||
1057 | static const struct clksel div2_core_clksel[] = { | ||
1058 | { .parent = &core_ck, .rates = div2_rates }, | ||
1059 | { .parent = NULL } | ||
1060 | }; | ||
1061 | |||
1062 | static struct clk l3_ick = { | ||
1063 | .name = "l3_ick", | ||
1064 | .ops = &clkops_null, | ||
1065 | .parent = &core_ck, | ||
1066 | .init = &omap2_init_clksel_parent, | ||
1067 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), | ||
1068 | .clksel_mask = OMAP3430_CLKSEL_L3_MASK, | ||
1069 | .clksel = div2_core_clksel, | ||
1070 | .clkdm_name = "core_l3_clkdm", | ||
1071 | .recalc = &omap2_clksel_recalc, | ||
1072 | }; | ||
1073 | |||
1074 | static const struct clksel div2_l3_clksel[] = { | ||
1075 | { .parent = &l3_ick, .rates = div2_rates }, | ||
1076 | { .parent = NULL } | ||
1077 | }; | ||
1078 | |||
1079 | static struct clk l4_ick = { | ||
1080 | .name = "l4_ick", | ||
1081 | .ops = &clkops_null, | ||
1082 | .parent = &l3_ick, | ||
1083 | .init = &omap2_init_clksel_parent, | ||
1084 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), | ||
1085 | .clksel_mask = OMAP3430_CLKSEL_L4_MASK, | ||
1086 | .clksel = div2_l3_clksel, | ||
1087 | .clkdm_name = "core_l4_clkdm", | ||
1088 | .recalc = &omap2_clksel_recalc, | ||
1089 | |||
1090 | }; | ||
1091 | |||
1092 | static const struct clksel div2_l4_clksel[] = { | ||
1093 | { .parent = &l4_ick, .rates = div2_rates }, | ||
1094 | { .parent = NULL } | ||
1095 | }; | ||
1096 | |||
1097 | static struct clk rm_ick = { | ||
1098 | .name = "rm_ick", | ||
1099 | .ops = &clkops_null, | ||
1100 | .parent = &l4_ick, | ||
1101 | .init = &omap2_init_clksel_parent, | ||
1102 | .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), | ||
1103 | .clksel_mask = OMAP3430_CLKSEL_RM_MASK, | ||
1104 | .clksel = div2_l4_clksel, | ||
1105 | .recalc = &omap2_clksel_recalc, | ||
1106 | }; | ||
1107 | |||
1108 | /* GFX power domain */ | ||
1109 | |||
1110 | /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */ | ||
1111 | |||
1112 | static const struct clksel gfx_l3_clksel[] = { | ||
1113 | { .parent = &l3_ick, .rates = gfx_l3_rates }, | ||
1114 | { .parent = NULL } | ||
1115 | }; | ||
1116 | |||
1117 | /* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */ | ||
1118 | static struct clk gfx_l3_ck = { | ||
1119 | .name = "gfx_l3_ck", | ||
1120 | .ops = &clkops_omap2_dflt_wait, | ||
1121 | .parent = &l3_ick, | ||
1122 | .init = &omap2_init_clksel_parent, | ||
1123 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), | ||
1124 | .enable_bit = OMAP_EN_GFX_SHIFT, | ||
1125 | .recalc = &followparent_recalc, | ||
1126 | }; | ||
1127 | |||
1128 | static struct clk gfx_l3_fck = { | ||
1129 | .name = "gfx_l3_fck", | ||
1130 | .ops = &clkops_null, | ||
1131 | .parent = &gfx_l3_ck, | ||
1132 | .init = &omap2_init_clksel_parent, | ||
1133 | .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), | ||
1134 | .clksel_mask = OMAP_CLKSEL_GFX_MASK, | ||
1135 | .clksel = gfx_l3_clksel, | ||
1136 | .clkdm_name = "gfx_3430es1_clkdm", | ||
1137 | .recalc = &omap2_clksel_recalc, | ||
1138 | }; | ||
1139 | |||
1140 | static struct clk gfx_l3_ick = { | ||
1141 | .name = "gfx_l3_ick", | ||
1142 | .ops = &clkops_null, | ||
1143 | .parent = &gfx_l3_ck, | ||
1144 | .clkdm_name = "gfx_3430es1_clkdm", | ||
1145 | .recalc = &followparent_recalc, | ||
1146 | }; | ||
1147 | |||
1148 | static struct clk gfx_cg1_ck = { | ||
1149 | .name = "gfx_cg1_ck", | ||
1150 | .ops = &clkops_omap2_dflt_wait, | ||
1151 | .parent = &gfx_l3_fck, /* REVISIT: correct? */ | ||
1152 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), | ||
1153 | .enable_bit = OMAP3430ES1_EN_2D_SHIFT, | ||
1154 | .clkdm_name = "gfx_3430es1_clkdm", | ||
1155 | .recalc = &followparent_recalc, | ||
1156 | }; | ||
1157 | |||
1158 | static struct clk gfx_cg2_ck = { | ||
1159 | .name = "gfx_cg2_ck", | ||
1160 | .ops = &clkops_omap2_dflt_wait, | ||
1161 | .parent = &gfx_l3_fck, /* REVISIT: correct? */ | ||
1162 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), | ||
1163 | .enable_bit = OMAP3430ES1_EN_3D_SHIFT, | ||
1164 | .clkdm_name = "gfx_3430es1_clkdm", | ||
1165 | .recalc = &followparent_recalc, | ||
1166 | }; | ||
1167 | |||
1168 | /* SGX power domain - 3430ES2 only */ | ||
1169 | |||
1170 | static const struct clksel_rate sgx_core_rates[] = { | ||
1171 | { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
1172 | { .div = 4, .val = 1, .flags = RATE_IN_343X }, | ||
1173 | { .div = 6, .val = 2, .flags = RATE_IN_343X }, | ||
1174 | { .div = 0 }, | ||
1175 | }; | ||
1176 | |||
1177 | static const struct clksel_rate sgx_96m_rates[] = { | ||
1178 | { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
1179 | { .div = 0 }, | ||
1180 | }; | ||
1181 | |||
1182 | static const struct clksel sgx_clksel[] = { | ||
1183 | { .parent = &core_ck, .rates = sgx_core_rates }, | ||
1184 | { .parent = &cm_96m_fck, .rates = sgx_96m_rates }, | ||
1185 | { .parent = NULL }, | ||
1186 | }; | ||
1187 | |||
1188 | static struct clk sgx_fck = { | ||
1189 | .name = "sgx_fck", | ||
1190 | .ops = &clkops_omap2_dflt_wait, | ||
1191 | .init = &omap2_init_clksel_parent, | ||
1192 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN), | ||
1193 | .enable_bit = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT, | ||
1194 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL), | ||
1195 | .clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK, | ||
1196 | .clksel = sgx_clksel, | ||
1197 | .clkdm_name = "sgx_clkdm", | ||
1198 | .recalc = &omap2_clksel_recalc, | ||
1199 | }; | ||
1200 | |||
1201 | static struct clk sgx_ick = { | ||
1202 | .name = "sgx_ick", | ||
1203 | .ops = &clkops_omap2_dflt_wait, | ||
1204 | .parent = &l3_ick, | ||
1205 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN), | ||
1206 | .enable_bit = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT, | ||
1207 | .clkdm_name = "sgx_clkdm", | ||
1208 | .recalc = &followparent_recalc, | ||
1209 | }; | ||
1210 | |||
1211 | /* CORE power domain */ | ||
1212 | |||
1213 | static struct clk d2d_26m_fck = { | ||
1214 | .name = "d2d_26m_fck", | ||
1215 | .ops = &clkops_omap2_dflt_wait, | ||
1216 | .parent = &sys_ck, | ||
1217 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
1218 | .enable_bit = OMAP3430ES1_EN_D2D_SHIFT, | ||
1219 | .clkdm_name = "d2d_clkdm", | ||
1220 | .recalc = &followparent_recalc, | ||
1221 | }; | ||
1222 | |||
1223 | static struct clk modem_fck = { | ||
1224 | .name = "modem_fck", | ||
1225 | .ops = &clkops_omap2_dflt_wait, | ||
1226 | .parent = &sys_ck, | ||
1227 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
1228 | .enable_bit = OMAP3430_EN_MODEM_SHIFT, | ||
1229 | .clkdm_name = "d2d_clkdm", | ||
1230 | .recalc = &followparent_recalc, | ||
1231 | }; | ||
1232 | |||
1233 | static struct clk sad2d_ick = { | ||
1234 | .name = "sad2d_ick", | ||
1235 | .ops = &clkops_omap2_dflt_wait, | ||
1236 | .parent = &l3_ick, | ||
1237 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1238 | .enable_bit = OMAP3430_EN_SAD2D_SHIFT, | ||
1239 | .clkdm_name = "d2d_clkdm", | ||
1240 | .recalc = &followparent_recalc, | ||
1241 | }; | ||
1242 | |||
1243 | static struct clk mad2d_ick = { | ||
1244 | .name = "mad2d_ick", | ||
1245 | .ops = &clkops_omap2_dflt_wait, | ||
1246 | .parent = &l3_ick, | ||
1247 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), | ||
1248 | .enable_bit = OMAP3430_EN_MAD2D_SHIFT, | ||
1249 | .clkdm_name = "d2d_clkdm", | ||
1250 | .recalc = &followparent_recalc, | ||
1251 | }; | ||
1252 | |||
1253 | static const struct clksel omap343x_gpt_clksel[] = { | ||
1254 | { .parent = &omap_32k_fck, .rates = gpt_32k_rates }, | ||
1255 | { .parent = &sys_ck, .rates = gpt_sys_rates }, | ||
1256 | { .parent = NULL} | ||
1257 | }; | ||
1258 | |||
1259 | static struct clk gpt10_fck = { | ||
1260 | .name = "gpt10_fck", | ||
1261 | .ops = &clkops_omap2_dflt_wait, | ||
1262 | .parent = &sys_ck, | ||
1263 | .init = &omap2_init_clksel_parent, | ||
1264 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
1265 | .enable_bit = OMAP3430_EN_GPT10_SHIFT, | ||
1266 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), | ||
1267 | .clksel_mask = OMAP3430_CLKSEL_GPT10_MASK, | ||
1268 | .clksel = omap343x_gpt_clksel, | ||
1269 | .clkdm_name = "core_l4_clkdm", | ||
1270 | .recalc = &omap2_clksel_recalc, | ||
1271 | }; | ||
1272 | |||
1273 | static struct clk gpt11_fck = { | ||
1274 | .name = "gpt11_fck", | ||
1275 | .ops = &clkops_omap2_dflt_wait, | ||
1276 | .parent = &sys_ck, | ||
1277 | .init = &omap2_init_clksel_parent, | ||
1278 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
1279 | .enable_bit = OMAP3430_EN_GPT11_SHIFT, | ||
1280 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), | ||
1281 | .clksel_mask = OMAP3430_CLKSEL_GPT11_MASK, | ||
1282 | .clksel = omap343x_gpt_clksel, | ||
1283 | .clkdm_name = "core_l4_clkdm", | ||
1284 | .recalc = &omap2_clksel_recalc, | ||
1285 | }; | ||
1286 | |||
1287 | static struct clk cpefuse_fck = { | ||
1288 | .name = "cpefuse_fck", | ||
1289 | .ops = &clkops_omap2_dflt, | ||
1290 | .parent = &sys_ck, | ||
1291 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), | ||
1292 | .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT, | ||
1293 | .recalc = &followparent_recalc, | ||
1294 | }; | ||
1295 | |||
1296 | static struct clk ts_fck = { | ||
1297 | .name = "ts_fck", | ||
1298 | .ops = &clkops_omap2_dflt, | ||
1299 | .parent = &omap_32k_fck, | ||
1300 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), | ||
1301 | .enable_bit = OMAP3430ES2_EN_TS_SHIFT, | ||
1302 | .recalc = &followparent_recalc, | ||
1303 | }; | ||
1304 | |||
1305 | static struct clk usbtll_fck = { | ||
1306 | .name = "usbtll_fck", | ||
1307 | .ops = &clkops_omap2_dflt, | ||
1308 | .parent = &dpll5_m2_ck, | ||
1309 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), | ||
1310 | .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, | ||
1311 | .recalc = &followparent_recalc, | ||
1312 | }; | ||
1313 | |||
1314 | /* CORE 96M FCLK-derived clocks */ | ||
1315 | |||
1316 | static struct clk core_96m_fck = { | ||
1317 | .name = "core_96m_fck", | ||
1318 | .ops = &clkops_null, | ||
1319 | .parent = &omap_96m_fck, | ||
1320 | .clkdm_name = "core_l4_clkdm", | ||
1321 | .recalc = &followparent_recalc, | ||
1322 | }; | ||
1323 | |||
1324 | static struct clk mmchs3_fck = { | ||
1325 | .name = "mmchs_fck", | ||
1326 | .ops = &clkops_omap2_dflt_wait, | ||
1327 | .id = 2, | ||
1328 | .parent = &core_96m_fck, | ||
1329 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
1330 | .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, | ||
1331 | .clkdm_name = "core_l4_clkdm", | ||
1332 | .recalc = &followparent_recalc, | ||
1333 | }; | ||
1334 | |||
1335 | static struct clk mmchs2_fck = { | ||
1336 | .name = "mmchs_fck", | ||
1337 | .ops = &clkops_omap2_dflt_wait, | ||
1338 | .id = 1, | ||
1339 | .parent = &core_96m_fck, | ||
1340 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
1341 | .enable_bit = OMAP3430_EN_MMC2_SHIFT, | ||
1342 | .clkdm_name = "core_l4_clkdm", | ||
1343 | .recalc = &followparent_recalc, | ||
1344 | }; | ||
1345 | |||
1346 | static struct clk mspro_fck = { | ||
1347 | .name = "mspro_fck", | ||
1348 | .ops = &clkops_omap2_dflt_wait, | ||
1349 | .parent = &core_96m_fck, | ||
1350 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
1351 | .enable_bit = OMAP3430_EN_MSPRO_SHIFT, | ||
1352 | .clkdm_name = "core_l4_clkdm", | ||
1353 | .recalc = &followparent_recalc, | ||
1354 | }; | ||
1355 | |||
1356 | static struct clk mmchs1_fck = { | ||
1357 | .name = "mmchs_fck", | ||
1358 | .ops = &clkops_omap2_dflt_wait, | ||
1359 | .parent = &core_96m_fck, | ||
1360 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
1361 | .enable_bit = OMAP3430_EN_MMC1_SHIFT, | ||
1362 | .clkdm_name = "core_l4_clkdm", | ||
1363 | .recalc = &followparent_recalc, | ||
1364 | }; | ||
1365 | |||
1366 | static struct clk i2c3_fck = { | ||
1367 | .name = "i2c_fck", | ||
1368 | .ops = &clkops_omap2_dflt_wait, | ||
1369 | .id = 3, | ||
1370 | .parent = &core_96m_fck, | ||
1371 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
1372 | .enable_bit = OMAP3430_EN_I2C3_SHIFT, | ||
1373 | .clkdm_name = "core_l4_clkdm", | ||
1374 | .recalc = &followparent_recalc, | ||
1375 | }; | ||
1376 | |||
1377 | static struct clk i2c2_fck = { | ||
1378 | .name = "i2c_fck", | ||
1379 | .ops = &clkops_omap2_dflt_wait, | ||
1380 | .id = 2, | ||
1381 | .parent = &core_96m_fck, | ||
1382 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
1383 | .enable_bit = OMAP3430_EN_I2C2_SHIFT, | ||
1384 | .clkdm_name = "core_l4_clkdm", | ||
1385 | .recalc = &followparent_recalc, | ||
1386 | }; | ||
1387 | |||
1388 | static struct clk i2c1_fck = { | ||
1389 | .name = "i2c_fck", | ||
1390 | .ops = &clkops_omap2_dflt_wait, | ||
1391 | .id = 1, | ||
1392 | .parent = &core_96m_fck, | ||
1393 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
1394 | .enable_bit = OMAP3430_EN_I2C1_SHIFT, | ||
1395 | .clkdm_name = "core_l4_clkdm", | ||
1396 | .recalc = &followparent_recalc, | ||
1397 | }; | ||
1398 | |||
1399 | /* | ||
1400 | * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck; | ||
1401 | * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck. | ||
1402 | */ | ||
1403 | static const struct clksel_rate common_mcbsp_96m_rates[] = { | ||
1404 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
1405 | { .div = 0 } | ||
1406 | }; | ||
1407 | |||
1408 | static const struct clksel_rate common_mcbsp_mcbsp_rates[] = { | ||
1409 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
1410 | { .div = 0 } | ||
1411 | }; | ||
1412 | |||
1413 | static const struct clksel mcbsp_15_clksel[] = { | ||
1414 | { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates }, | ||
1415 | { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, | ||
1416 | { .parent = NULL } | ||
1417 | }; | ||
1418 | |||
1419 | static struct clk mcbsp5_fck = { | ||
1420 | .name = "mcbsp_fck", | ||
1421 | .ops = &clkops_omap2_dflt_wait, | ||
1422 | .id = 5, | ||
1423 | .init = &omap2_init_clksel_parent, | ||
1424 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
1425 | .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, | ||
1426 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), | ||
1427 | .clksel_mask = OMAP2_MCBSP5_CLKS_MASK, | ||
1428 | .clksel = mcbsp_15_clksel, | ||
1429 | .clkdm_name = "core_l4_clkdm", | ||
1430 | .recalc = &omap2_clksel_recalc, | ||
1431 | }; | ||
1432 | |||
1433 | static struct clk mcbsp1_fck = { | ||
1434 | .name = "mcbsp_fck", | ||
1435 | .ops = &clkops_omap2_dflt_wait, | ||
1436 | .id = 1, | ||
1437 | .init = &omap2_init_clksel_parent, | ||
1438 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
1439 | .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, | ||
1440 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), | ||
1441 | .clksel_mask = OMAP2_MCBSP1_CLKS_MASK, | ||
1442 | .clksel = mcbsp_15_clksel, | ||
1443 | .clkdm_name = "core_l4_clkdm", | ||
1444 | .recalc = &omap2_clksel_recalc, | ||
1445 | }; | ||
1446 | |||
1447 | /* CORE_48M_FCK-derived clocks */ | ||
1448 | |||
1449 | static struct clk core_48m_fck = { | ||
1450 | .name = "core_48m_fck", | ||
1451 | .ops = &clkops_null, | ||
1452 | .parent = &omap_48m_fck, | ||
1453 | .clkdm_name = "core_l4_clkdm", | ||
1454 | .recalc = &followparent_recalc, | ||
1455 | }; | ||
1456 | |||
1457 | static struct clk mcspi4_fck = { | ||
1458 | .name = "mcspi_fck", | ||
1459 | .ops = &clkops_omap2_dflt_wait, | ||
1460 | .id = 4, | ||
1461 | .parent = &core_48m_fck, | ||
1462 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
1463 | .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, | ||
1464 | .recalc = &followparent_recalc, | ||
1465 | }; | ||
1466 | |||
1467 | static struct clk mcspi3_fck = { | ||
1468 | .name = "mcspi_fck", | ||
1469 | .ops = &clkops_omap2_dflt_wait, | ||
1470 | .id = 3, | ||
1471 | .parent = &core_48m_fck, | ||
1472 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
1473 | .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, | ||
1474 | .recalc = &followparent_recalc, | ||
1475 | }; | ||
1476 | |||
1477 | static struct clk mcspi2_fck = { | ||
1478 | .name = "mcspi_fck", | ||
1479 | .ops = &clkops_omap2_dflt_wait, | ||
1480 | .id = 2, | ||
1481 | .parent = &core_48m_fck, | ||
1482 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
1483 | .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, | ||
1484 | .recalc = &followparent_recalc, | ||
1485 | }; | ||
1486 | |||
1487 | static struct clk mcspi1_fck = { | ||
1488 | .name = "mcspi_fck", | ||
1489 | .ops = &clkops_omap2_dflt_wait, | ||
1490 | .id = 1, | ||
1491 | .parent = &core_48m_fck, | ||
1492 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
1493 | .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, | ||
1494 | .recalc = &followparent_recalc, | ||
1495 | }; | ||
1496 | |||
1497 | static struct clk uart2_fck = { | ||
1498 | .name = "uart2_fck", | ||
1499 | .ops = &clkops_omap2_dflt_wait, | ||
1500 | .parent = &core_48m_fck, | ||
1501 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
1502 | .enable_bit = OMAP3430_EN_UART2_SHIFT, | ||
1503 | .recalc = &followparent_recalc, | ||
1504 | }; | ||
1505 | |||
1506 | static struct clk uart1_fck = { | ||
1507 | .name = "uart1_fck", | ||
1508 | .ops = &clkops_omap2_dflt_wait, | ||
1509 | .parent = &core_48m_fck, | ||
1510 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
1511 | .enable_bit = OMAP3430_EN_UART1_SHIFT, | ||
1512 | .recalc = &followparent_recalc, | ||
1513 | }; | ||
1514 | |||
1515 | static struct clk fshostusb_fck = { | ||
1516 | .name = "fshostusb_fck", | ||
1517 | .ops = &clkops_omap2_dflt_wait, | ||
1518 | .parent = &core_48m_fck, | ||
1519 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
1520 | .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT, | ||
1521 | .recalc = &followparent_recalc, | ||
1522 | }; | ||
1523 | |||
1524 | /* CORE_12M_FCK based clocks */ | ||
1525 | |||
1526 | static struct clk core_12m_fck = { | ||
1527 | .name = "core_12m_fck", | ||
1528 | .ops = &clkops_null, | ||
1529 | .parent = &omap_12m_fck, | ||
1530 | .clkdm_name = "core_l4_clkdm", | ||
1531 | .recalc = &followparent_recalc, | ||
1532 | }; | ||
1533 | |||
1534 | static struct clk hdq_fck = { | ||
1535 | .name = "hdq_fck", | ||
1536 | .ops = &clkops_omap2_dflt_wait, | ||
1537 | .parent = &core_12m_fck, | ||
1538 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
1539 | .enable_bit = OMAP3430_EN_HDQ_SHIFT, | ||
1540 | .recalc = &followparent_recalc, | ||
1541 | }; | ||
1542 | |||
1543 | /* DPLL3-derived clock */ | ||
1544 | |||
1545 | static const struct clksel_rate ssi_ssr_corex2_rates[] = { | ||
1546 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
1547 | { .div = 2, .val = 2, .flags = RATE_IN_343X }, | ||
1548 | { .div = 3, .val = 3, .flags = RATE_IN_343X }, | ||
1549 | { .div = 4, .val = 4, .flags = RATE_IN_343X }, | ||
1550 | { .div = 6, .val = 6, .flags = RATE_IN_343X }, | ||
1551 | { .div = 8, .val = 8, .flags = RATE_IN_343X }, | ||
1552 | { .div = 0 } | ||
1553 | }; | ||
1554 | |||
1555 | static const struct clksel ssi_ssr_clksel[] = { | ||
1556 | { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates }, | ||
1557 | { .parent = NULL } | ||
1558 | }; | ||
1559 | |||
1560 | static struct clk ssi_ssr_fck_3430es1 = { | ||
1561 | .name = "ssi_ssr_fck", | ||
1562 | .ops = &clkops_omap2_dflt, | ||
1563 | .init = &omap2_init_clksel_parent, | ||
1564 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
1565 | .enable_bit = OMAP3430_EN_SSI_SHIFT, | ||
1566 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), | ||
1567 | .clksel_mask = OMAP3430_CLKSEL_SSI_MASK, | ||
1568 | .clksel = ssi_ssr_clksel, | ||
1569 | .clkdm_name = "core_l4_clkdm", | ||
1570 | .recalc = &omap2_clksel_recalc, | ||
1571 | }; | ||
1572 | |||
1573 | static struct clk ssi_ssr_fck_3430es2 = { | ||
1574 | .name = "ssi_ssr_fck", | ||
1575 | .ops = &clkops_omap3430es2_ssi_wait, | ||
1576 | .init = &omap2_init_clksel_parent, | ||
1577 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
1578 | .enable_bit = OMAP3430_EN_SSI_SHIFT, | ||
1579 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), | ||
1580 | .clksel_mask = OMAP3430_CLKSEL_SSI_MASK, | ||
1581 | .clksel = ssi_ssr_clksel, | ||
1582 | .clkdm_name = "core_l4_clkdm", | ||
1583 | .recalc = &omap2_clksel_recalc, | ||
1584 | }; | ||
1585 | |||
1586 | static struct clk ssi_sst_fck_3430es1 = { | ||
1587 | .name = "ssi_sst_fck", | ||
1588 | .ops = &clkops_null, | ||
1589 | .parent = &ssi_ssr_fck_3430es1, | ||
1590 | .fixed_div = 2, | ||
1591 | .recalc = &omap2_fixed_divisor_recalc, | ||
1592 | }; | ||
1593 | |||
1594 | static struct clk ssi_sst_fck_3430es2 = { | ||
1595 | .name = "ssi_sst_fck", | ||
1596 | .ops = &clkops_null, | ||
1597 | .parent = &ssi_ssr_fck_3430es2, | ||
1598 | .fixed_div = 2, | ||
1599 | .recalc = &omap2_fixed_divisor_recalc, | ||
1600 | }; | ||
1601 | |||
1602 | |||
1603 | |||
1604 | /* CORE_L3_ICK based clocks */ | ||
1605 | |||
1606 | /* | ||
1607 | * XXX must add clk_enable/clk_disable for these if standard code won't | ||
1608 | * handle it | ||
1609 | */ | ||
1610 | static struct clk core_l3_ick = { | ||
1611 | .name = "core_l3_ick", | ||
1612 | .ops = &clkops_null, | ||
1613 | .parent = &l3_ick, | ||
1614 | .clkdm_name = "core_l3_clkdm", | ||
1615 | .recalc = &followparent_recalc, | ||
1616 | }; | ||
1617 | |||
1618 | static struct clk hsotgusb_ick_3430es1 = { | ||
1619 | .name = "hsotgusb_ick", | ||
1620 | .ops = &clkops_omap2_dflt, | ||
1621 | .parent = &core_l3_ick, | ||
1622 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1623 | .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT, | ||
1624 | .clkdm_name = "core_l3_clkdm", | ||
1625 | .recalc = &followparent_recalc, | ||
1626 | }; | ||
1627 | |||
1628 | static struct clk hsotgusb_ick_3430es2 = { | ||
1629 | .name = "hsotgusb_ick", | ||
1630 | .ops = &clkops_omap3430es2_hsotgusb_wait, | ||
1631 | .parent = &core_l3_ick, | ||
1632 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1633 | .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT, | ||
1634 | .clkdm_name = "core_l3_clkdm", | ||
1635 | .recalc = &followparent_recalc, | ||
1636 | }; | ||
1637 | |||
1638 | static struct clk sdrc_ick = { | ||
1639 | .name = "sdrc_ick", | ||
1640 | .ops = &clkops_omap2_dflt_wait, | ||
1641 | .parent = &core_l3_ick, | ||
1642 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1643 | .enable_bit = OMAP3430_EN_SDRC_SHIFT, | ||
1644 | .flags = ENABLE_ON_INIT, | ||
1645 | .clkdm_name = "core_l3_clkdm", | ||
1646 | .recalc = &followparent_recalc, | ||
1647 | }; | ||
1648 | |||
1649 | static struct clk gpmc_fck = { | ||
1650 | .name = "gpmc_fck", | ||
1651 | .ops = &clkops_null, | ||
1652 | .parent = &core_l3_ick, | ||
1653 | .flags = ENABLE_ON_INIT, /* huh? */ | ||
1654 | .clkdm_name = "core_l3_clkdm", | ||
1655 | .recalc = &followparent_recalc, | ||
1656 | }; | ||
1657 | |||
1658 | /* SECURITY_L3_ICK based clocks */ | ||
1659 | |||
1660 | static struct clk security_l3_ick = { | ||
1661 | .name = "security_l3_ick", | ||
1662 | .ops = &clkops_null, | ||
1663 | .parent = &l3_ick, | ||
1664 | .recalc = &followparent_recalc, | ||
1665 | }; | ||
1666 | |||
1667 | static struct clk pka_ick = { | ||
1668 | .name = "pka_ick", | ||
1669 | .ops = &clkops_omap2_dflt_wait, | ||
1670 | .parent = &security_l3_ick, | ||
1671 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | ||
1672 | .enable_bit = OMAP3430_EN_PKA_SHIFT, | ||
1673 | .recalc = &followparent_recalc, | ||
1674 | }; | ||
1675 | |||
1676 | /* CORE_L4_ICK based clocks */ | ||
1677 | |||
1678 | static struct clk core_l4_ick = { | ||
1679 | .name = "core_l4_ick", | ||
1680 | .ops = &clkops_null, | ||
1681 | .parent = &l4_ick, | ||
1682 | .clkdm_name = "core_l4_clkdm", | ||
1683 | .recalc = &followparent_recalc, | ||
1684 | }; | ||
1685 | |||
1686 | static struct clk usbtll_ick = { | ||
1687 | .name = "usbtll_ick", | ||
1688 | .ops = &clkops_omap2_dflt_wait, | ||
1689 | .parent = &core_l4_ick, | ||
1690 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), | ||
1691 | .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, | ||
1692 | .clkdm_name = "core_l4_clkdm", | ||
1693 | .recalc = &followparent_recalc, | ||
1694 | }; | ||
1695 | |||
1696 | static struct clk mmchs3_ick = { | ||
1697 | .name = "mmchs_ick", | ||
1698 | .ops = &clkops_omap2_dflt_wait, | ||
1699 | .id = 2, | ||
1700 | .parent = &core_l4_ick, | ||
1701 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1702 | .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, | ||
1703 | .clkdm_name = "core_l4_clkdm", | ||
1704 | .recalc = &followparent_recalc, | ||
1705 | }; | ||
1706 | |||
1707 | /* Intersystem Communication Registers - chassis mode only */ | ||
1708 | static struct clk icr_ick = { | ||
1709 | .name = "icr_ick", | ||
1710 | .ops = &clkops_omap2_dflt_wait, | ||
1711 | .parent = &core_l4_ick, | ||
1712 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1713 | .enable_bit = OMAP3430_EN_ICR_SHIFT, | ||
1714 | .clkdm_name = "core_l4_clkdm", | ||
1715 | .recalc = &followparent_recalc, | ||
1716 | }; | ||
1717 | |||
1718 | static struct clk aes2_ick = { | ||
1719 | .name = "aes2_ick", | ||
1720 | .ops = &clkops_omap2_dflt_wait, | ||
1721 | .parent = &core_l4_ick, | ||
1722 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1723 | .enable_bit = OMAP3430_EN_AES2_SHIFT, | ||
1724 | .clkdm_name = "core_l4_clkdm", | ||
1725 | .recalc = &followparent_recalc, | ||
1726 | }; | ||
1727 | |||
1728 | static struct clk sha12_ick = { | ||
1729 | .name = "sha12_ick", | ||
1730 | .ops = &clkops_omap2_dflt_wait, | ||
1731 | .parent = &core_l4_ick, | ||
1732 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1733 | .enable_bit = OMAP3430_EN_SHA12_SHIFT, | ||
1734 | .clkdm_name = "core_l4_clkdm", | ||
1735 | .recalc = &followparent_recalc, | ||
1736 | }; | ||
1737 | |||
1738 | static struct clk des2_ick = { | ||
1739 | .name = "des2_ick", | ||
1740 | .ops = &clkops_omap2_dflt_wait, | ||
1741 | .parent = &core_l4_ick, | ||
1742 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1743 | .enable_bit = OMAP3430_EN_DES2_SHIFT, | ||
1744 | .clkdm_name = "core_l4_clkdm", | ||
1745 | .recalc = &followparent_recalc, | ||
1746 | }; | ||
1747 | |||
1748 | static struct clk mmchs2_ick = { | ||
1749 | .name = "mmchs_ick", | ||
1750 | .ops = &clkops_omap2_dflt_wait, | ||
1751 | .id = 1, | ||
1752 | .parent = &core_l4_ick, | ||
1753 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1754 | .enable_bit = OMAP3430_EN_MMC2_SHIFT, | ||
1755 | .clkdm_name = "core_l4_clkdm", | ||
1756 | .recalc = &followparent_recalc, | ||
1757 | }; | ||
1758 | |||
1759 | static struct clk mmchs1_ick = { | ||
1760 | .name = "mmchs_ick", | ||
1761 | .ops = &clkops_omap2_dflt_wait, | ||
1762 | .parent = &core_l4_ick, | ||
1763 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1764 | .enable_bit = OMAP3430_EN_MMC1_SHIFT, | ||
1765 | .clkdm_name = "core_l4_clkdm", | ||
1766 | .recalc = &followparent_recalc, | ||
1767 | }; | ||
1768 | |||
1769 | static struct clk mspro_ick = { | ||
1770 | .name = "mspro_ick", | ||
1771 | .ops = &clkops_omap2_dflt_wait, | ||
1772 | .parent = &core_l4_ick, | ||
1773 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1774 | .enable_bit = OMAP3430_EN_MSPRO_SHIFT, | ||
1775 | .clkdm_name = "core_l4_clkdm", | ||
1776 | .recalc = &followparent_recalc, | ||
1777 | }; | ||
1778 | |||
1779 | static struct clk hdq_ick = { | ||
1780 | .name = "hdq_ick", | ||
1781 | .ops = &clkops_omap2_dflt_wait, | ||
1782 | .parent = &core_l4_ick, | ||
1783 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1784 | .enable_bit = OMAP3430_EN_HDQ_SHIFT, | ||
1785 | .clkdm_name = "core_l4_clkdm", | ||
1786 | .recalc = &followparent_recalc, | ||
1787 | }; | ||
1788 | |||
1789 | static struct clk mcspi4_ick = { | ||
1790 | .name = "mcspi_ick", | ||
1791 | .ops = &clkops_omap2_dflt_wait, | ||
1792 | .id = 4, | ||
1793 | .parent = &core_l4_ick, | ||
1794 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1795 | .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, | ||
1796 | .clkdm_name = "core_l4_clkdm", | ||
1797 | .recalc = &followparent_recalc, | ||
1798 | }; | ||
1799 | |||
1800 | static struct clk mcspi3_ick = { | ||
1801 | .name = "mcspi_ick", | ||
1802 | .ops = &clkops_omap2_dflt_wait, | ||
1803 | .id = 3, | ||
1804 | .parent = &core_l4_ick, | ||
1805 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1806 | .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, | ||
1807 | .clkdm_name = "core_l4_clkdm", | ||
1808 | .recalc = &followparent_recalc, | ||
1809 | }; | ||
1810 | |||
1811 | static struct clk mcspi2_ick = { | ||
1812 | .name = "mcspi_ick", | ||
1813 | .ops = &clkops_omap2_dflt_wait, | ||
1814 | .id = 2, | ||
1815 | .parent = &core_l4_ick, | ||
1816 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1817 | .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, | ||
1818 | .clkdm_name = "core_l4_clkdm", | ||
1819 | .recalc = &followparent_recalc, | ||
1820 | }; | ||
1821 | |||
1822 | static struct clk mcspi1_ick = { | ||
1823 | .name = "mcspi_ick", | ||
1824 | .ops = &clkops_omap2_dflt_wait, | ||
1825 | .id = 1, | ||
1826 | .parent = &core_l4_ick, | ||
1827 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1828 | .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, | ||
1829 | .clkdm_name = "core_l4_clkdm", | ||
1830 | .recalc = &followparent_recalc, | ||
1831 | }; | ||
1832 | |||
1833 | static struct clk i2c3_ick = { | ||
1834 | .name = "i2c_ick", | ||
1835 | .ops = &clkops_omap2_dflt_wait, | ||
1836 | .id = 3, | ||
1837 | .parent = &core_l4_ick, | ||
1838 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1839 | .enable_bit = OMAP3430_EN_I2C3_SHIFT, | ||
1840 | .clkdm_name = "core_l4_clkdm", | ||
1841 | .recalc = &followparent_recalc, | ||
1842 | }; | ||
1843 | |||
1844 | static struct clk i2c2_ick = { | ||
1845 | .name = "i2c_ick", | ||
1846 | .ops = &clkops_omap2_dflt_wait, | ||
1847 | .id = 2, | ||
1848 | .parent = &core_l4_ick, | ||
1849 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1850 | .enable_bit = OMAP3430_EN_I2C2_SHIFT, | ||
1851 | .clkdm_name = "core_l4_clkdm", | ||
1852 | .recalc = &followparent_recalc, | ||
1853 | }; | ||
1854 | |||
1855 | static struct clk i2c1_ick = { | ||
1856 | .name = "i2c_ick", | ||
1857 | .ops = &clkops_omap2_dflt_wait, | ||
1858 | .id = 1, | ||
1859 | .parent = &core_l4_ick, | ||
1860 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1861 | .enable_bit = OMAP3430_EN_I2C1_SHIFT, | ||
1862 | .clkdm_name = "core_l4_clkdm", | ||
1863 | .recalc = &followparent_recalc, | ||
1864 | }; | ||
1865 | |||
1866 | static struct clk uart2_ick = { | ||
1867 | .name = "uart2_ick", | ||
1868 | .ops = &clkops_omap2_dflt_wait, | ||
1869 | .parent = &core_l4_ick, | ||
1870 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1871 | .enable_bit = OMAP3430_EN_UART2_SHIFT, | ||
1872 | .clkdm_name = "core_l4_clkdm", | ||
1873 | .recalc = &followparent_recalc, | ||
1874 | }; | ||
1875 | |||
1876 | static struct clk uart1_ick = { | ||
1877 | .name = "uart1_ick", | ||
1878 | .ops = &clkops_omap2_dflt_wait, | ||
1879 | .parent = &core_l4_ick, | ||
1880 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1881 | .enable_bit = OMAP3430_EN_UART1_SHIFT, | ||
1882 | .clkdm_name = "core_l4_clkdm", | ||
1883 | .recalc = &followparent_recalc, | ||
1884 | }; | ||
1885 | |||
1886 | static struct clk gpt11_ick = { | ||
1887 | .name = "gpt11_ick", | ||
1888 | .ops = &clkops_omap2_dflt_wait, | ||
1889 | .parent = &core_l4_ick, | ||
1890 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1891 | .enable_bit = OMAP3430_EN_GPT11_SHIFT, | ||
1892 | .clkdm_name = "core_l4_clkdm", | ||
1893 | .recalc = &followparent_recalc, | ||
1894 | }; | ||
1895 | |||
1896 | static struct clk gpt10_ick = { | ||
1897 | .name = "gpt10_ick", | ||
1898 | .ops = &clkops_omap2_dflt_wait, | ||
1899 | .parent = &core_l4_ick, | ||
1900 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1901 | .enable_bit = OMAP3430_EN_GPT10_SHIFT, | ||
1902 | .clkdm_name = "core_l4_clkdm", | ||
1903 | .recalc = &followparent_recalc, | ||
1904 | }; | ||
1905 | |||
1906 | static struct clk mcbsp5_ick = { | ||
1907 | .name = "mcbsp_ick", | ||
1908 | .ops = &clkops_omap2_dflt_wait, | ||
1909 | .id = 5, | ||
1910 | .parent = &core_l4_ick, | ||
1911 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1912 | .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, | ||
1913 | .clkdm_name = "core_l4_clkdm", | ||
1914 | .recalc = &followparent_recalc, | ||
1915 | }; | ||
1916 | |||
1917 | static struct clk mcbsp1_ick = { | ||
1918 | .name = "mcbsp_ick", | ||
1919 | .ops = &clkops_omap2_dflt_wait, | ||
1920 | .id = 1, | ||
1921 | .parent = &core_l4_ick, | ||
1922 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1923 | .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, | ||
1924 | .clkdm_name = "core_l4_clkdm", | ||
1925 | .recalc = &followparent_recalc, | ||
1926 | }; | ||
1927 | |||
1928 | static struct clk fac_ick = { | ||
1929 | .name = "fac_ick", | ||
1930 | .ops = &clkops_omap2_dflt_wait, | ||
1931 | .parent = &core_l4_ick, | ||
1932 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1933 | .enable_bit = OMAP3430ES1_EN_FAC_SHIFT, | ||
1934 | .clkdm_name = "core_l4_clkdm", | ||
1935 | .recalc = &followparent_recalc, | ||
1936 | }; | ||
1937 | |||
1938 | static struct clk mailboxes_ick = { | ||
1939 | .name = "mailboxes_ick", | ||
1940 | .ops = &clkops_omap2_dflt_wait, | ||
1941 | .parent = &core_l4_ick, | ||
1942 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1943 | .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT, | ||
1944 | .clkdm_name = "core_l4_clkdm", | ||
1945 | .recalc = &followparent_recalc, | ||
1946 | }; | ||
1947 | |||
1948 | static struct clk omapctrl_ick = { | ||
1949 | .name = "omapctrl_ick", | ||
1950 | .ops = &clkops_omap2_dflt_wait, | ||
1951 | .parent = &core_l4_ick, | ||
1952 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1953 | .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT, | ||
1954 | .flags = ENABLE_ON_INIT, | ||
1955 | .recalc = &followparent_recalc, | ||
1956 | }; | ||
1957 | |||
1958 | /* SSI_L4_ICK based clocks */ | ||
1959 | |||
1960 | static struct clk ssi_l4_ick = { | ||
1961 | .name = "ssi_l4_ick", | ||
1962 | .ops = &clkops_null, | ||
1963 | .parent = &l4_ick, | ||
1964 | .clkdm_name = "core_l4_clkdm", | ||
1965 | .recalc = &followparent_recalc, | ||
1966 | }; | ||
1967 | |||
1968 | static struct clk ssi_ick_3430es1 = { | ||
1969 | .name = "ssi_ick", | ||
1970 | .ops = &clkops_omap2_dflt, | ||
1971 | .parent = &ssi_l4_ick, | ||
1972 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1973 | .enable_bit = OMAP3430_EN_SSI_SHIFT, | ||
1974 | .clkdm_name = "core_l4_clkdm", | ||
1975 | .recalc = &followparent_recalc, | ||
1976 | }; | ||
1977 | |||
1978 | static struct clk ssi_ick_3430es2 = { | ||
1979 | .name = "ssi_ick", | ||
1980 | .ops = &clkops_omap3430es2_ssi_wait, | ||
1981 | .parent = &ssi_l4_ick, | ||
1982 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1983 | .enable_bit = OMAP3430_EN_SSI_SHIFT, | ||
1984 | .clkdm_name = "core_l4_clkdm", | ||
1985 | .recalc = &followparent_recalc, | ||
1986 | }; | ||
1987 | |||
1988 | /* REVISIT: Technically the TRM claims that this is CORE_CLK based, | ||
1989 | * but l4_ick makes more sense to me */ | ||
1990 | |||
1991 | static const struct clksel usb_l4_clksel[] = { | ||
1992 | { .parent = &l4_ick, .rates = div2_rates }, | ||
1993 | { .parent = NULL }, | ||
1994 | }; | ||
1995 | |||
1996 | static struct clk usb_l4_ick = { | ||
1997 | .name = "usb_l4_ick", | ||
1998 | .ops = &clkops_omap2_dflt_wait, | ||
1999 | .parent = &l4_ick, | ||
2000 | .init = &omap2_init_clksel_parent, | ||
2001 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
2002 | .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT, | ||
2003 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), | ||
2004 | .clksel_mask = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK, | ||
2005 | .clksel = usb_l4_clksel, | ||
2006 | .recalc = &omap2_clksel_recalc, | ||
2007 | }; | ||
2008 | |||
2009 | /* SECURITY_L4_ICK2 based clocks */ | ||
2010 | |||
2011 | static struct clk security_l4_ick2 = { | ||
2012 | .name = "security_l4_ick2", | ||
2013 | .ops = &clkops_null, | ||
2014 | .parent = &l4_ick, | ||
2015 | .recalc = &followparent_recalc, | ||
2016 | }; | ||
2017 | |||
2018 | static struct clk aes1_ick = { | ||
2019 | .name = "aes1_ick", | ||
2020 | .ops = &clkops_omap2_dflt_wait, | ||
2021 | .parent = &security_l4_ick2, | ||
2022 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | ||
2023 | .enable_bit = OMAP3430_EN_AES1_SHIFT, | ||
2024 | .recalc = &followparent_recalc, | ||
2025 | }; | ||
2026 | |||
2027 | static struct clk rng_ick = { | ||
2028 | .name = "rng_ick", | ||
2029 | .ops = &clkops_omap2_dflt_wait, | ||
2030 | .parent = &security_l4_ick2, | ||
2031 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | ||
2032 | .enable_bit = OMAP3430_EN_RNG_SHIFT, | ||
2033 | .recalc = &followparent_recalc, | ||
2034 | }; | ||
2035 | |||
2036 | static struct clk sha11_ick = { | ||
2037 | .name = "sha11_ick", | ||
2038 | .ops = &clkops_omap2_dflt_wait, | ||
2039 | .parent = &security_l4_ick2, | ||
2040 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | ||
2041 | .enable_bit = OMAP3430_EN_SHA11_SHIFT, | ||
2042 | .recalc = &followparent_recalc, | ||
2043 | }; | ||
2044 | |||
2045 | static struct clk des1_ick = { | ||
2046 | .name = "des1_ick", | ||
2047 | .ops = &clkops_omap2_dflt_wait, | ||
2048 | .parent = &security_l4_ick2, | ||
2049 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | ||
2050 | .enable_bit = OMAP3430_EN_DES1_SHIFT, | ||
2051 | .recalc = &followparent_recalc, | ||
2052 | }; | ||
2053 | |||
2054 | /* DSS */ | ||
2055 | static struct clk dss1_alwon_fck_3430es1 = { | ||
2056 | .name = "dss1_alwon_fck", | ||
2057 | .ops = &clkops_omap2_dflt, | ||
2058 | .parent = &dpll4_m4x2_ck, | ||
2059 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), | ||
2060 | .enable_bit = OMAP3430_EN_DSS1_SHIFT, | ||
2061 | .clkdm_name = "dss_clkdm", | ||
2062 | .recalc = &followparent_recalc, | ||
2063 | }; | ||
2064 | |||
2065 | static struct clk dss1_alwon_fck_3430es2 = { | ||
2066 | .name = "dss1_alwon_fck", | ||
2067 | .ops = &clkops_omap3430es2_dss_usbhost_wait, | ||
2068 | .parent = &dpll4_m4x2_ck, | ||
2069 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), | ||
2070 | .enable_bit = OMAP3430_EN_DSS1_SHIFT, | ||
2071 | .clkdm_name = "dss_clkdm", | ||
2072 | .recalc = &followparent_recalc, | ||
2073 | }; | ||
2074 | |||
2075 | static struct clk dss_tv_fck = { | ||
2076 | .name = "dss_tv_fck", | ||
2077 | .ops = &clkops_omap2_dflt, | ||
2078 | .parent = &omap_54m_fck, | ||
2079 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), | ||
2080 | .enable_bit = OMAP3430_EN_TV_SHIFT, | ||
2081 | .clkdm_name = "dss_clkdm", | ||
2082 | .recalc = &followparent_recalc, | ||
2083 | }; | ||
2084 | |||
2085 | static struct clk dss_96m_fck = { | ||
2086 | .name = "dss_96m_fck", | ||
2087 | .ops = &clkops_omap2_dflt, | ||
2088 | .parent = &omap_96m_fck, | ||
2089 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), | ||
2090 | .enable_bit = OMAP3430_EN_TV_SHIFT, | ||
2091 | .clkdm_name = "dss_clkdm", | ||
2092 | .recalc = &followparent_recalc, | ||
2093 | }; | ||
2094 | |||
2095 | static struct clk dss2_alwon_fck = { | ||
2096 | .name = "dss2_alwon_fck", | ||
2097 | .ops = &clkops_omap2_dflt, | ||
2098 | .parent = &sys_ck, | ||
2099 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), | ||
2100 | .enable_bit = OMAP3430_EN_DSS2_SHIFT, | ||
2101 | .clkdm_name = "dss_clkdm", | ||
2102 | .recalc = &followparent_recalc, | ||
2103 | }; | ||
2104 | |||
2105 | static struct clk dss_ick_3430es1 = { | ||
2106 | /* Handles both L3 and L4 clocks */ | ||
2107 | .name = "dss_ick", | ||
2108 | .ops = &clkops_omap2_dflt, | ||
2109 | .parent = &l4_ick, | ||
2110 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN), | ||
2111 | .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT, | ||
2112 | .clkdm_name = "dss_clkdm", | ||
2113 | .recalc = &followparent_recalc, | ||
2114 | }; | ||
2115 | |||
2116 | static struct clk dss_ick_3430es2 = { | ||
2117 | /* Handles both L3 and L4 clocks */ | ||
2118 | .name = "dss_ick", | ||
2119 | .ops = &clkops_omap3430es2_dss_usbhost_wait, | ||
2120 | .parent = &l4_ick, | ||
2121 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN), | ||
2122 | .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT, | ||
2123 | .clkdm_name = "dss_clkdm", | ||
2124 | .recalc = &followparent_recalc, | ||
2125 | }; | ||
2126 | |||
2127 | /* CAM */ | ||
2128 | |||
2129 | static struct clk cam_mclk = { | ||
2130 | .name = "cam_mclk", | ||
2131 | .ops = &clkops_omap2_dflt, | ||
2132 | .parent = &dpll4_m5x2_ck, | ||
2133 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN), | ||
2134 | .enable_bit = OMAP3430_EN_CAM_SHIFT, | ||
2135 | .clkdm_name = "cam_clkdm", | ||
2136 | .recalc = &followparent_recalc, | ||
2137 | }; | ||
2138 | |||
2139 | static struct clk cam_ick = { | ||
2140 | /* Handles both L3 and L4 clocks */ | ||
2141 | .name = "cam_ick", | ||
2142 | .ops = &clkops_omap2_dflt, | ||
2143 | .parent = &l4_ick, | ||
2144 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN), | ||
2145 | .enable_bit = OMAP3430_EN_CAM_SHIFT, | ||
2146 | .clkdm_name = "cam_clkdm", | ||
2147 | .recalc = &followparent_recalc, | ||
2148 | }; | ||
2149 | |||
2150 | static struct clk csi2_96m_fck = { | ||
2151 | .name = "csi2_96m_fck", | ||
2152 | .ops = &clkops_omap2_dflt, | ||
2153 | .parent = &core_96m_fck, | ||
2154 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN), | ||
2155 | .enable_bit = OMAP3430_EN_CSI2_SHIFT, | ||
2156 | .clkdm_name = "cam_clkdm", | ||
2157 | .recalc = &followparent_recalc, | ||
2158 | }; | ||
2159 | |||
2160 | /* USBHOST - 3430ES2 only */ | ||
2161 | |||
2162 | static struct clk usbhost_120m_fck = { | ||
2163 | .name = "usbhost_120m_fck", | ||
2164 | .ops = &clkops_omap2_dflt, | ||
2165 | .parent = &dpll5_m2_ck, | ||
2166 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), | ||
2167 | .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT, | ||
2168 | .clkdm_name = "usbhost_clkdm", | ||
2169 | .recalc = &followparent_recalc, | ||
2170 | }; | ||
2171 | |||
2172 | static struct clk usbhost_48m_fck = { | ||
2173 | .name = "usbhost_48m_fck", | ||
2174 | .ops = &clkops_omap3430es2_dss_usbhost_wait, | ||
2175 | .parent = &omap_48m_fck, | ||
2176 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), | ||
2177 | .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT, | ||
2178 | .clkdm_name = "usbhost_clkdm", | ||
2179 | .recalc = &followparent_recalc, | ||
2180 | }; | ||
2181 | |||
2182 | static struct clk usbhost_ick = { | ||
2183 | /* Handles both L3 and L4 clocks */ | ||
2184 | .name = "usbhost_ick", | ||
2185 | .ops = &clkops_omap3430es2_dss_usbhost_wait, | ||
2186 | .parent = &l4_ick, | ||
2187 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN), | ||
2188 | .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT, | ||
2189 | .clkdm_name = "usbhost_clkdm", | ||
2190 | .recalc = &followparent_recalc, | ||
2191 | }; | ||
2192 | |||
2193 | /* WKUP */ | ||
2194 | |||
2195 | static const struct clksel_rate usim_96m_rates[] = { | ||
2196 | { .div = 2, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
2197 | { .div = 4, .val = 4, .flags = RATE_IN_343X }, | ||
2198 | { .div = 8, .val = 5, .flags = RATE_IN_343X }, | ||
2199 | { .div = 10, .val = 6, .flags = RATE_IN_343X }, | ||
2200 | { .div = 0 }, | ||
2201 | }; | ||
2202 | |||
2203 | static const struct clksel_rate usim_120m_rates[] = { | ||
2204 | { .div = 4, .val = 7, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
2205 | { .div = 8, .val = 8, .flags = RATE_IN_343X }, | ||
2206 | { .div = 16, .val = 9, .flags = RATE_IN_343X }, | ||
2207 | { .div = 20, .val = 10, .flags = RATE_IN_343X }, | ||
2208 | { .div = 0 }, | ||
2209 | }; | ||
2210 | |||
2211 | static const struct clksel usim_clksel[] = { | ||
2212 | { .parent = &omap_96m_fck, .rates = usim_96m_rates }, | ||
2213 | { .parent = &dpll5_m2_ck, .rates = usim_120m_rates }, | ||
2214 | { .parent = &sys_ck, .rates = div2_rates }, | ||
2215 | { .parent = NULL }, | ||
2216 | }; | ||
2217 | |||
2218 | /* 3430ES2 only */ | ||
2219 | static struct clk usim_fck = { | ||
2220 | .name = "usim_fck", | ||
2221 | .ops = &clkops_omap2_dflt_wait, | ||
2222 | .init = &omap2_init_clksel_parent, | ||
2223 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | ||
2224 | .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT, | ||
2225 | .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), | ||
2226 | .clksel_mask = OMAP3430ES2_CLKSEL_USIMOCP_MASK, | ||
2227 | .clksel = usim_clksel, | ||
2228 | .recalc = &omap2_clksel_recalc, | ||
2229 | }; | ||
2230 | |||
2231 | /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */ | ||
2232 | static struct clk gpt1_fck = { | ||
2233 | .name = "gpt1_fck", | ||
2234 | .ops = &clkops_omap2_dflt_wait, | ||
2235 | .init = &omap2_init_clksel_parent, | ||
2236 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | ||
2237 | .enable_bit = OMAP3430_EN_GPT1_SHIFT, | ||
2238 | .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), | ||
2239 | .clksel_mask = OMAP3430_CLKSEL_GPT1_MASK, | ||
2240 | .clksel = omap343x_gpt_clksel, | ||
2241 | .clkdm_name = "wkup_clkdm", | ||
2242 | .recalc = &omap2_clksel_recalc, | ||
2243 | }; | ||
2244 | |||
2245 | static struct clk wkup_32k_fck = { | ||
2246 | .name = "wkup_32k_fck", | ||
2247 | .ops = &clkops_null, | ||
2248 | .parent = &omap_32k_fck, | ||
2249 | .clkdm_name = "wkup_clkdm", | ||
2250 | .recalc = &followparent_recalc, | ||
2251 | }; | ||
2252 | |||
2253 | static struct clk gpio1_dbck = { | ||
2254 | .name = "gpio1_dbck", | ||
2255 | .ops = &clkops_omap2_dflt, | ||
2256 | .parent = &wkup_32k_fck, | ||
2257 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | ||
2258 | .enable_bit = OMAP3430_EN_GPIO1_SHIFT, | ||
2259 | .clkdm_name = "wkup_clkdm", | ||
2260 | .recalc = &followparent_recalc, | ||
2261 | }; | ||
2262 | |||
2263 | static struct clk wdt2_fck = { | ||
2264 | .name = "wdt2_fck", | ||
2265 | .ops = &clkops_omap2_dflt_wait, | ||
2266 | .parent = &wkup_32k_fck, | ||
2267 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | ||
2268 | .enable_bit = OMAP3430_EN_WDT2_SHIFT, | ||
2269 | .clkdm_name = "wkup_clkdm", | ||
2270 | .recalc = &followparent_recalc, | ||
2271 | }; | ||
2272 | |||
2273 | static struct clk wkup_l4_ick = { | ||
2274 | .name = "wkup_l4_ick", | ||
2275 | .ops = &clkops_null, | ||
2276 | .parent = &sys_ck, | ||
2277 | .clkdm_name = "wkup_clkdm", | ||
2278 | .recalc = &followparent_recalc, | ||
2279 | }; | ||
2280 | |||
2281 | /* 3430ES2 only */ | ||
2282 | /* Never specifically named in the TRM, so we have to infer a likely name */ | ||
2283 | static struct clk usim_ick = { | ||
2284 | .name = "usim_ick", | ||
2285 | .ops = &clkops_omap2_dflt_wait, | ||
2286 | .parent = &wkup_l4_ick, | ||
2287 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | ||
2288 | .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT, | ||
2289 | .clkdm_name = "wkup_clkdm", | ||
2290 | .recalc = &followparent_recalc, | ||
2291 | }; | ||
2292 | |||
2293 | static struct clk wdt2_ick = { | ||
2294 | .name = "wdt2_ick", | ||
2295 | .ops = &clkops_omap2_dflt_wait, | ||
2296 | .parent = &wkup_l4_ick, | ||
2297 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | ||
2298 | .enable_bit = OMAP3430_EN_WDT2_SHIFT, | ||
2299 | .clkdm_name = "wkup_clkdm", | ||
2300 | .recalc = &followparent_recalc, | ||
2301 | }; | ||
2302 | |||
2303 | static struct clk wdt1_ick = { | ||
2304 | .name = "wdt1_ick", | ||
2305 | .ops = &clkops_omap2_dflt_wait, | ||
2306 | .parent = &wkup_l4_ick, | ||
2307 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | ||
2308 | .enable_bit = OMAP3430_EN_WDT1_SHIFT, | ||
2309 | .clkdm_name = "wkup_clkdm", | ||
2310 | .recalc = &followparent_recalc, | ||
2311 | }; | ||
2312 | |||
2313 | static struct clk gpio1_ick = { | ||
2314 | .name = "gpio1_ick", | ||
2315 | .ops = &clkops_omap2_dflt_wait, | ||
2316 | .parent = &wkup_l4_ick, | ||
2317 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | ||
2318 | .enable_bit = OMAP3430_EN_GPIO1_SHIFT, | ||
2319 | .clkdm_name = "wkup_clkdm", | ||
2320 | .recalc = &followparent_recalc, | ||
2321 | }; | ||
2322 | |||
2323 | static struct clk omap_32ksync_ick = { | ||
2324 | .name = "omap_32ksync_ick", | ||
2325 | .ops = &clkops_omap2_dflt_wait, | ||
2326 | .parent = &wkup_l4_ick, | ||
2327 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | ||
2328 | .enable_bit = OMAP3430_EN_32KSYNC_SHIFT, | ||
2329 | .clkdm_name = "wkup_clkdm", | ||
2330 | .recalc = &followparent_recalc, | ||
2331 | }; | ||
2332 | |||
2333 | /* XXX This clock no longer exists in 3430 TRM rev F */ | ||
2334 | static struct clk gpt12_ick = { | ||
2335 | .name = "gpt12_ick", | ||
2336 | .ops = &clkops_omap2_dflt_wait, | ||
2337 | .parent = &wkup_l4_ick, | ||
2338 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | ||
2339 | .enable_bit = OMAP3430_EN_GPT12_SHIFT, | ||
2340 | .clkdm_name = "wkup_clkdm", | ||
2341 | .recalc = &followparent_recalc, | ||
2342 | }; | ||
2343 | |||
2344 | static struct clk gpt1_ick = { | ||
2345 | .name = "gpt1_ick", | ||
2346 | .ops = &clkops_omap2_dflt_wait, | ||
2347 | .parent = &wkup_l4_ick, | ||
2348 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | ||
2349 | .enable_bit = OMAP3430_EN_GPT1_SHIFT, | ||
2350 | .clkdm_name = "wkup_clkdm", | ||
2351 | .recalc = &followparent_recalc, | ||
2352 | }; | ||
2353 | |||
2354 | |||
2355 | |||
2356 | /* PER clock domain */ | ||
2357 | |||
2358 | static struct clk per_96m_fck = { | ||
2359 | .name = "per_96m_fck", | ||
2360 | .ops = &clkops_null, | ||
2361 | .parent = &omap_96m_alwon_fck, | ||
2362 | .clkdm_name = "per_clkdm", | ||
2363 | .recalc = &followparent_recalc, | ||
2364 | }; | ||
2365 | |||
2366 | static struct clk per_48m_fck = { | ||
2367 | .name = "per_48m_fck", | ||
2368 | .ops = &clkops_null, | ||
2369 | .parent = &omap_48m_fck, | ||
2370 | .clkdm_name = "per_clkdm", | ||
2371 | .recalc = &followparent_recalc, | ||
2372 | }; | ||
2373 | |||
2374 | static struct clk uart3_fck = { | ||
2375 | .name = "uart3_fck", | ||
2376 | .ops = &clkops_omap2_dflt_wait, | ||
2377 | .parent = &per_48m_fck, | ||
2378 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | ||
2379 | .enable_bit = OMAP3430_EN_UART3_SHIFT, | ||
2380 | .clkdm_name = "per_clkdm", | ||
2381 | .recalc = &followparent_recalc, | ||
2382 | }; | ||
2383 | |||
2384 | static struct clk gpt2_fck = { | ||
2385 | .name = "gpt2_fck", | ||
2386 | .ops = &clkops_omap2_dflt_wait, | ||
2387 | .init = &omap2_init_clksel_parent, | ||
2388 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | ||
2389 | .enable_bit = OMAP3430_EN_GPT2_SHIFT, | ||
2390 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | ||
2391 | .clksel_mask = OMAP3430_CLKSEL_GPT2_MASK, | ||
2392 | .clksel = omap343x_gpt_clksel, | ||
2393 | .clkdm_name = "per_clkdm", | ||
2394 | .recalc = &omap2_clksel_recalc, | ||
2395 | }; | ||
2396 | |||
2397 | static struct clk gpt3_fck = { | ||
2398 | .name = "gpt3_fck", | ||
2399 | .ops = &clkops_omap2_dflt_wait, | ||
2400 | .init = &omap2_init_clksel_parent, | ||
2401 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | ||
2402 | .enable_bit = OMAP3430_EN_GPT3_SHIFT, | ||
2403 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | ||
2404 | .clksel_mask = OMAP3430_CLKSEL_GPT3_MASK, | ||
2405 | .clksel = omap343x_gpt_clksel, | ||
2406 | .clkdm_name = "per_clkdm", | ||
2407 | .recalc = &omap2_clksel_recalc, | ||
2408 | }; | ||
2409 | |||
2410 | static struct clk gpt4_fck = { | ||
2411 | .name = "gpt4_fck", | ||
2412 | .ops = &clkops_omap2_dflt_wait, | ||
2413 | .init = &omap2_init_clksel_parent, | ||
2414 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | ||
2415 | .enable_bit = OMAP3430_EN_GPT4_SHIFT, | ||
2416 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | ||
2417 | .clksel_mask = OMAP3430_CLKSEL_GPT4_MASK, | ||
2418 | .clksel = omap343x_gpt_clksel, | ||
2419 | .clkdm_name = "per_clkdm", | ||
2420 | .recalc = &omap2_clksel_recalc, | ||
2421 | }; | ||
2422 | |||
2423 | static struct clk gpt5_fck = { | ||
2424 | .name = "gpt5_fck", | ||
2425 | .ops = &clkops_omap2_dflt_wait, | ||
2426 | .init = &omap2_init_clksel_parent, | ||
2427 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | ||
2428 | .enable_bit = OMAP3430_EN_GPT5_SHIFT, | ||
2429 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | ||
2430 | .clksel_mask = OMAP3430_CLKSEL_GPT5_MASK, | ||
2431 | .clksel = omap343x_gpt_clksel, | ||
2432 | .clkdm_name = "per_clkdm", | ||
2433 | .recalc = &omap2_clksel_recalc, | ||
2434 | }; | ||
2435 | |||
2436 | static struct clk gpt6_fck = { | ||
2437 | .name = "gpt6_fck", | ||
2438 | .ops = &clkops_omap2_dflt_wait, | ||
2439 | .init = &omap2_init_clksel_parent, | ||
2440 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | ||
2441 | .enable_bit = OMAP3430_EN_GPT6_SHIFT, | ||
2442 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | ||
2443 | .clksel_mask = OMAP3430_CLKSEL_GPT6_MASK, | ||
2444 | .clksel = omap343x_gpt_clksel, | ||
2445 | .clkdm_name = "per_clkdm", | ||
2446 | .recalc = &omap2_clksel_recalc, | ||
2447 | }; | ||
2448 | |||
2449 | static struct clk gpt7_fck = { | ||
2450 | .name = "gpt7_fck", | ||
2451 | .ops = &clkops_omap2_dflt_wait, | ||
2452 | .init = &omap2_init_clksel_parent, | ||
2453 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | ||
2454 | .enable_bit = OMAP3430_EN_GPT7_SHIFT, | ||
2455 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | ||
2456 | .clksel_mask = OMAP3430_CLKSEL_GPT7_MASK, | ||
2457 | .clksel = omap343x_gpt_clksel, | ||
2458 | .clkdm_name = "per_clkdm", | ||
2459 | .recalc = &omap2_clksel_recalc, | ||
2460 | }; | ||
2461 | |||
2462 | static struct clk gpt8_fck = { | ||
2463 | .name = "gpt8_fck", | ||
2464 | .ops = &clkops_omap2_dflt_wait, | ||
2465 | .init = &omap2_init_clksel_parent, | ||
2466 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | ||
2467 | .enable_bit = OMAP3430_EN_GPT8_SHIFT, | ||
2468 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | ||
2469 | .clksel_mask = OMAP3430_CLKSEL_GPT8_MASK, | ||
2470 | .clksel = omap343x_gpt_clksel, | ||
2471 | .clkdm_name = "per_clkdm", | ||
2472 | .recalc = &omap2_clksel_recalc, | ||
2473 | }; | ||
2474 | |||
2475 | static struct clk gpt9_fck = { | ||
2476 | .name = "gpt9_fck", | ||
2477 | .ops = &clkops_omap2_dflt_wait, | ||
2478 | .init = &omap2_init_clksel_parent, | ||
2479 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | ||
2480 | .enable_bit = OMAP3430_EN_GPT9_SHIFT, | ||
2481 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | ||
2482 | .clksel_mask = OMAP3430_CLKSEL_GPT9_MASK, | ||
2483 | .clksel = omap343x_gpt_clksel, | ||
2484 | .clkdm_name = "per_clkdm", | ||
2485 | .recalc = &omap2_clksel_recalc, | ||
2486 | }; | ||
2487 | |||
2488 | static struct clk per_32k_alwon_fck = { | ||
2489 | .name = "per_32k_alwon_fck", | ||
2490 | .ops = &clkops_null, | ||
2491 | .parent = &omap_32k_fck, | ||
2492 | .clkdm_name = "per_clkdm", | ||
2493 | .recalc = &followparent_recalc, | ||
2494 | }; | ||
2495 | |||
2496 | static struct clk gpio6_dbck = { | ||
2497 | .name = "gpio6_dbck", | ||
2498 | .ops = &clkops_omap2_dflt, | ||
2499 | .parent = &per_32k_alwon_fck, | ||
2500 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | ||
2501 | .enable_bit = OMAP3430_EN_GPIO6_SHIFT, | ||
2502 | .clkdm_name = "per_clkdm", | ||
2503 | .recalc = &followparent_recalc, | ||
2504 | }; | ||
2505 | |||
2506 | static struct clk gpio5_dbck = { | ||
2507 | .name = "gpio5_dbck", | ||
2508 | .ops = &clkops_omap2_dflt, | ||
2509 | .parent = &per_32k_alwon_fck, | ||
2510 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | ||
2511 | .enable_bit = OMAP3430_EN_GPIO5_SHIFT, | ||
2512 | .clkdm_name = "per_clkdm", | ||
2513 | .recalc = &followparent_recalc, | ||
2514 | }; | ||
2515 | |||
2516 | static struct clk gpio4_dbck = { | ||
2517 | .name = "gpio4_dbck", | ||
2518 | .ops = &clkops_omap2_dflt, | ||
2519 | .parent = &per_32k_alwon_fck, | ||
2520 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | ||
2521 | .enable_bit = OMAP3430_EN_GPIO4_SHIFT, | ||
2522 | .clkdm_name = "per_clkdm", | ||
2523 | .recalc = &followparent_recalc, | ||
2524 | }; | ||
2525 | |||
2526 | static struct clk gpio3_dbck = { | ||
2527 | .name = "gpio3_dbck", | ||
2528 | .ops = &clkops_omap2_dflt, | ||
2529 | .parent = &per_32k_alwon_fck, | ||
2530 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | ||
2531 | .enable_bit = OMAP3430_EN_GPIO3_SHIFT, | ||
2532 | .clkdm_name = "per_clkdm", | ||
2533 | .recalc = &followparent_recalc, | ||
2534 | }; | ||
2535 | |||
2536 | static struct clk gpio2_dbck = { | ||
2537 | .name = "gpio2_dbck", | ||
2538 | .ops = &clkops_omap2_dflt, | ||
2539 | .parent = &per_32k_alwon_fck, | ||
2540 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | ||
2541 | .enable_bit = OMAP3430_EN_GPIO2_SHIFT, | ||
2542 | .clkdm_name = "per_clkdm", | ||
2543 | .recalc = &followparent_recalc, | ||
2544 | }; | ||
2545 | |||
2546 | static struct clk wdt3_fck = { | ||
2547 | .name = "wdt3_fck", | ||
2548 | .ops = &clkops_omap2_dflt_wait, | ||
2549 | .parent = &per_32k_alwon_fck, | ||
2550 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | ||
2551 | .enable_bit = OMAP3430_EN_WDT3_SHIFT, | ||
2552 | .clkdm_name = "per_clkdm", | ||
2553 | .recalc = &followparent_recalc, | ||
2554 | }; | ||
2555 | |||
2556 | static struct clk per_l4_ick = { | ||
2557 | .name = "per_l4_ick", | ||
2558 | .ops = &clkops_null, | ||
2559 | .parent = &l4_ick, | ||
2560 | .clkdm_name = "per_clkdm", | ||
2561 | .recalc = &followparent_recalc, | ||
2562 | }; | ||
2563 | |||
2564 | static struct clk gpio6_ick = { | ||
2565 | .name = "gpio6_ick", | ||
2566 | .ops = &clkops_omap2_dflt_wait, | ||
2567 | .parent = &per_l4_ick, | ||
2568 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | ||
2569 | .enable_bit = OMAP3430_EN_GPIO6_SHIFT, | ||
2570 | .clkdm_name = "per_clkdm", | ||
2571 | .recalc = &followparent_recalc, | ||
2572 | }; | ||
2573 | |||
2574 | static struct clk gpio5_ick = { | ||
2575 | .name = "gpio5_ick", | ||
2576 | .ops = &clkops_omap2_dflt_wait, | ||
2577 | .parent = &per_l4_ick, | ||
2578 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | ||
2579 | .enable_bit = OMAP3430_EN_GPIO5_SHIFT, | ||
2580 | .clkdm_name = "per_clkdm", | ||
2581 | .recalc = &followparent_recalc, | ||
2582 | }; | ||
2583 | |||
2584 | static struct clk gpio4_ick = { | ||
2585 | .name = "gpio4_ick", | ||
2586 | .ops = &clkops_omap2_dflt_wait, | ||
2587 | .parent = &per_l4_ick, | ||
2588 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | ||
2589 | .enable_bit = OMAP3430_EN_GPIO4_SHIFT, | ||
2590 | .clkdm_name = "per_clkdm", | ||
2591 | .recalc = &followparent_recalc, | ||
2592 | }; | ||
2593 | |||
2594 | static struct clk gpio3_ick = { | ||
2595 | .name = "gpio3_ick", | ||
2596 | .ops = &clkops_omap2_dflt_wait, | ||
2597 | .parent = &per_l4_ick, | ||
2598 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | ||
2599 | .enable_bit = OMAP3430_EN_GPIO3_SHIFT, | ||
2600 | .clkdm_name = "per_clkdm", | ||
2601 | .recalc = &followparent_recalc, | ||
2602 | }; | ||
2603 | |||
2604 | static struct clk gpio2_ick = { | ||
2605 | .name = "gpio2_ick", | ||
2606 | .ops = &clkops_omap2_dflt_wait, | ||
2607 | .parent = &per_l4_ick, | ||
2608 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | ||
2609 | .enable_bit = OMAP3430_EN_GPIO2_SHIFT, | ||
2610 | .clkdm_name = "per_clkdm", | ||
2611 | .recalc = &followparent_recalc, | ||
2612 | }; | ||
2613 | |||
2614 | static struct clk wdt3_ick = { | ||
2615 | .name = "wdt3_ick", | ||
2616 | .ops = &clkops_omap2_dflt_wait, | ||
2617 | .parent = &per_l4_ick, | ||
2618 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | ||
2619 | .enable_bit = OMAP3430_EN_WDT3_SHIFT, | ||
2620 | .clkdm_name = "per_clkdm", | ||
2621 | .recalc = &followparent_recalc, | ||
2622 | }; | ||
2623 | |||
2624 | static struct clk uart3_ick = { | ||
2625 | .name = "uart3_ick", | ||
2626 | .ops = &clkops_omap2_dflt_wait, | ||
2627 | .parent = &per_l4_ick, | ||
2628 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | ||
2629 | .enable_bit = OMAP3430_EN_UART3_SHIFT, | ||
2630 | .clkdm_name = "per_clkdm", | ||
2631 | .recalc = &followparent_recalc, | ||
2632 | }; | ||
2633 | |||
2634 | static struct clk gpt9_ick = { | ||
2635 | .name = "gpt9_ick", | ||
2636 | .ops = &clkops_omap2_dflt_wait, | ||
2637 | .parent = &per_l4_ick, | ||
2638 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | ||
2639 | .enable_bit = OMAP3430_EN_GPT9_SHIFT, | ||
2640 | .clkdm_name = "per_clkdm", | ||
2641 | .recalc = &followparent_recalc, | ||
2642 | }; | ||
2643 | |||
2644 | static struct clk gpt8_ick = { | ||
2645 | .name = "gpt8_ick", | ||
2646 | .ops = &clkops_omap2_dflt_wait, | ||
2647 | .parent = &per_l4_ick, | ||
2648 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | ||
2649 | .enable_bit = OMAP3430_EN_GPT8_SHIFT, | ||
2650 | .clkdm_name = "per_clkdm", | ||
2651 | .recalc = &followparent_recalc, | ||
2652 | }; | ||
2653 | |||
2654 | static struct clk gpt7_ick = { | ||
2655 | .name = "gpt7_ick", | ||
2656 | .ops = &clkops_omap2_dflt_wait, | ||
2657 | .parent = &per_l4_ick, | ||
2658 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | ||
2659 | .enable_bit = OMAP3430_EN_GPT7_SHIFT, | ||
2660 | .clkdm_name = "per_clkdm", | ||
2661 | .recalc = &followparent_recalc, | ||
2662 | }; | ||
2663 | |||
2664 | static struct clk gpt6_ick = { | ||
2665 | .name = "gpt6_ick", | ||
2666 | .ops = &clkops_omap2_dflt_wait, | ||
2667 | .parent = &per_l4_ick, | ||
2668 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | ||
2669 | .enable_bit = OMAP3430_EN_GPT6_SHIFT, | ||
2670 | .clkdm_name = "per_clkdm", | ||
2671 | .recalc = &followparent_recalc, | ||
2672 | }; | ||
2673 | |||
2674 | static struct clk gpt5_ick = { | ||
2675 | .name = "gpt5_ick", | ||
2676 | .ops = &clkops_omap2_dflt_wait, | ||
2677 | .parent = &per_l4_ick, | ||
2678 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | ||
2679 | .enable_bit = OMAP3430_EN_GPT5_SHIFT, | ||
2680 | .clkdm_name = "per_clkdm", | ||
2681 | .recalc = &followparent_recalc, | ||
2682 | }; | ||
2683 | |||
2684 | static struct clk gpt4_ick = { | ||
2685 | .name = "gpt4_ick", | ||
2686 | .ops = &clkops_omap2_dflt_wait, | ||
2687 | .parent = &per_l4_ick, | ||
2688 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | ||
2689 | .enable_bit = OMAP3430_EN_GPT4_SHIFT, | ||
2690 | .clkdm_name = "per_clkdm", | ||
2691 | .recalc = &followparent_recalc, | ||
2692 | }; | ||
2693 | |||
2694 | static struct clk gpt3_ick = { | ||
2695 | .name = "gpt3_ick", | ||
2696 | .ops = &clkops_omap2_dflt_wait, | ||
2697 | .parent = &per_l4_ick, | ||
2698 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | ||
2699 | .enable_bit = OMAP3430_EN_GPT3_SHIFT, | ||
2700 | .clkdm_name = "per_clkdm", | ||
2701 | .recalc = &followparent_recalc, | ||
2702 | }; | ||
2703 | |||
2704 | static struct clk gpt2_ick = { | ||
2705 | .name = "gpt2_ick", | ||
2706 | .ops = &clkops_omap2_dflt_wait, | ||
2707 | .parent = &per_l4_ick, | ||
2708 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | ||
2709 | .enable_bit = OMAP3430_EN_GPT2_SHIFT, | ||
2710 | .clkdm_name = "per_clkdm", | ||
2711 | .recalc = &followparent_recalc, | ||
2712 | }; | ||
2713 | |||
2714 | static struct clk mcbsp2_ick = { | ||
2715 | .name = "mcbsp_ick", | ||
2716 | .ops = &clkops_omap2_dflt_wait, | ||
2717 | .id = 2, | ||
2718 | .parent = &per_l4_ick, | ||
2719 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | ||
2720 | .enable_bit = OMAP3430_EN_MCBSP2_SHIFT, | ||
2721 | .clkdm_name = "per_clkdm", | ||
2722 | .recalc = &followparent_recalc, | ||
2723 | }; | ||
2724 | |||
2725 | static struct clk mcbsp3_ick = { | ||
2726 | .name = "mcbsp_ick", | ||
2727 | .ops = &clkops_omap2_dflt_wait, | ||
2728 | .id = 3, | ||
2729 | .parent = &per_l4_ick, | ||
2730 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | ||
2731 | .enable_bit = OMAP3430_EN_MCBSP3_SHIFT, | ||
2732 | .clkdm_name = "per_clkdm", | ||
2733 | .recalc = &followparent_recalc, | ||
2734 | }; | ||
2735 | |||
2736 | static struct clk mcbsp4_ick = { | ||
2737 | .name = "mcbsp_ick", | ||
2738 | .ops = &clkops_omap2_dflt_wait, | ||
2739 | .id = 4, | ||
2740 | .parent = &per_l4_ick, | ||
2741 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | ||
2742 | .enable_bit = OMAP3430_EN_MCBSP4_SHIFT, | ||
2743 | .clkdm_name = "per_clkdm", | ||
2744 | .recalc = &followparent_recalc, | ||
2745 | }; | ||
2746 | |||
2747 | static const struct clksel mcbsp_234_clksel[] = { | ||
2748 | { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates }, | ||
2749 | { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, | ||
2750 | { .parent = NULL } | ||
2751 | }; | ||
2752 | |||
2753 | static struct clk mcbsp2_fck = { | ||
2754 | .name = "mcbsp_fck", | ||
2755 | .ops = &clkops_omap2_dflt_wait, | ||
2756 | .id = 2, | ||
2757 | .init = &omap2_init_clksel_parent, | ||
2758 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | ||
2759 | .enable_bit = OMAP3430_EN_MCBSP2_SHIFT, | ||
2760 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), | ||
2761 | .clksel_mask = OMAP2_MCBSP2_CLKS_MASK, | ||
2762 | .clksel = mcbsp_234_clksel, | ||
2763 | .clkdm_name = "per_clkdm", | ||
2764 | .recalc = &omap2_clksel_recalc, | ||
2765 | }; | ||
2766 | |||
2767 | static struct clk mcbsp3_fck = { | ||
2768 | .name = "mcbsp_fck", | ||
2769 | .ops = &clkops_omap2_dflt_wait, | ||
2770 | .id = 3, | ||
2771 | .init = &omap2_init_clksel_parent, | ||
2772 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | ||
2773 | .enable_bit = OMAP3430_EN_MCBSP3_SHIFT, | ||
2774 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), | ||
2775 | .clksel_mask = OMAP2_MCBSP3_CLKS_MASK, | ||
2776 | .clksel = mcbsp_234_clksel, | ||
2777 | .clkdm_name = "per_clkdm", | ||
2778 | .recalc = &omap2_clksel_recalc, | ||
2779 | }; | ||
2780 | |||
2781 | static struct clk mcbsp4_fck = { | ||
2782 | .name = "mcbsp_fck", | ||
2783 | .ops = &clkops_omap2_dflt_wait, | ||
2784 | .id = 4, | ||
2785 | .init = &omap2_init_clksel_parent, | ||
2786 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | ||
2787 | .enable_bit = OMAP3430_EN_MCBSP4_SHIFT, | ||
2788 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), | ||
2789 | .clksel_mask = OMAP2_MCBSP4_CLKS_MASK, | ||
2790 | .clksel = mcbsp_234_clksel, | ||
2791 | .clkdm_name = "per_clkdm", | ||
2792 | .recalc = &omap2_clksel_recalc, | ||
2793 | }; | ||
2794 | |||
2795 | /* EMU clocks */ | ||
2796 | |||
2797 | /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */ | ||
2798 | |||
2799 | static const struct clksel_rate emu_src_sys_rates[] = { | ||
2800 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
2801 | { .div = 0 }, | ||
2802 | }; | ||
2803 | |||
2804 | static const struct clksel_rate emu_src_core_rates[] = { | ||
2805 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
2806 | { .div = 0 }, | ||
2807 | }; | ||
2808 | |||
2809 | static const struct clksel_rate emu_src_per_rates[] = { | ||
2810 | { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
2811 | { .div = 0 }, | ||
2812 | }; | ||
2813 | |||
2814 | static const struct clksel_rate emu_src_mpu_rates[] = { | ||
2815 | { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
2816 | { .div = 0 }, | ||
2817 | }; | ||
2818 | |||
2819 | static const struct clksel emu_src_clksel[] = { | ||
2820 | { .parent = &sys_ck, .rates = emu_src_sys_rates }, | ||
2821 | { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates }, | ||
2822 | { .parent = &emu_per_alwon_ck, .rates = emu_src_per_rates }, | ||
2823 | { .parent = &emu_mpu_alwon_ck, .rates = emu_src_mpu_rates }, | ||
2824 | { .parent = NULL }, | ||
2825 | }; | ||
2826 | |||
2827 | /* | ||
2828 | * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only | ||
2829 | * to switch the source of some of the EMU clocks. | ||
2830 | * XXX Are there CLKEN bits for these EMU clks? | ||
2831 | */ | ||
2832 | static struct clk emu_src_ck = { | ||
2833 | .name = "emu_src_ck", | ||
2834 | .ops = &clkops_null, | ||
2835 | .init = &omap2_init_clksel_parent, | ||
2836 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | ||
2837 | .clksel_mask = OMAP3430_MUX_CTRL_MASK, | ||
2838 | .clksel = emu_src_clksel, | ||
2839 | .clkdm_name = "emu_clkdm", | ||
2840 | .recalc = &omap2_clksel_recalc, | ||
2841 | }; | ||
2842 | |||
2843 | static const struct clksel_rate pclk_emu_rates[] = { | ||
2844 | { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
2845 | { .div = 3, .val = 3, .flags = RATE_IN_343X }, | ||
2846 | { .div = 4, .val = 4, .flags = RATE_IN_343X }, | ||
2847 | { .div = 6, .val = 6, .flags = RATE_IN_343X }, | ||
2848 | { .div = 0 }, | ||
2849 | }; | ||
2850 | |||
2851 | static const struct clksel pclk_emu_clksel[] = { | ||
2852 | { .parent = &emu_src_ck, .rates = pclk_emu_rates }, | ||
2853 | { .parent = NULL }, | ||
2854 | }; | ||
2855 | |||
2856 | static struct clk pclk_fck = { | ||
2857 | .name = "pclk_fck", | ||
2858 | .ops = &clkops_null, | ||
2859 | .init = &omap2_init_clksel_parent, | ||
2860 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | ||
2861 | .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK, | ||
2862 | .clksel = pclk_emu_clksel, | ||
2863 | .clkdm_name = "emu_clkdm", | ||
2864 | .recalc = &omap2_clksel_recalc, | ||
2865 | }; | ||
2866 | |||
2867 | static const struct clksel_rate pclkx2_emu_rates[] = { | ||
2868 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
2869 | { .div = 2, .val = 2, .flags = RATE_IN_343X }, | ||
2870 | { .div = 3, .val = 3, .flags = RATE_IN_343X }, | ||
2871 | { .div = 0 }, | ||
2872 | }; | ||
2873 | |||
2874 | static const struct clksel pclkx2_emu_clksel[] = { | ||
2875 | { .parent = &emu_src_ck, .rates = pclkx2_emu_rates }, | ||
2876 | { .parent = NULL }, | ||
2877 | }; | ||
2878 | |||
2879 | static struct clk pclkx2_fck = { | ||
2880 | .name = "pclkx2_fck", | ||
2881 | .ops = &clkops_null, | ||
2882 | .init = &omap2_init_clksel_parent, | ||
2883 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | ||
2884 | .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK, | ||
2885 | .clksel = pclkx2_emu_clksel, | ||
2886 | .clkdm_name = "emu_clkdm", | ||
2887 | .recalc = &omap2_clksel_recalc, | ||
2888 | }; | ||
2889 | |||
2890 | static const struct clksel atclk_emu_clksel[] = { | ||
2891 | { .parent = &emu_src_ck, .rates = div2_rates }, | ||
2892 | { .parent = NULL }, | ||
2893 | }; | ||
2894 | |||
2895 | static struct clk atclk_fck = { | ||
2896 | .name = "atclk_fck", | ||
2897 | .ops = &clkops_null, | ||
2898 | .init = &omap2_init_clksel_parent, | ||
2899 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | ||
2900 | .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK, | ||
2901 | .clksel = atclk_emu_clksel, | ||
2902 | .clkdm_name = "emu_clkdm", | ||
2903 | .recalc = &omap2_clksel_recalc, | ||
2904 | }; | ||
2905 | |||
2906 | static struct clk traceclk_src_fck = { | ||
2907 | .name = "traceclk_src_fck", | ||
2908 | .ops = &clkops_null, | ||
2909 | .init = &omap2_init_clksel_parent, | ||
2910 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | ||
2911 | .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK, | ||
2912 | .clksel = emu_src_clksel, | ||
2913 | .clkdm_name = "emu_clkdm", | ||
2914 | .recalc = &omap2_clksel_recalc, | ||
2915 | }; | ||
2916 | |||
2917 | static const struct clksel_rate traceclk_rates[] = { | ||
2918 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
2919 | { .div = 2, .val = 2, .flags = RATE_IN_343X }, | ||
2920 | { .div = 4, .val = 4, .flags = RATE_IN_343X }, | ||
2921 | { .div = 0 }, | ||
2922 | }; | ||
2923 | |||
2924 | static const struct clksel traceclk_clksel[] = { | ||
2925 | { .parent = &traceclk_src_fck, .rates = traceclk_rates }, | ||
2926 | { .parent = NULL }, | ||
2927 | }; | ||
2928 | |||
2929 | static struct clk traceclk_fck = { | ||
2930 | .name = "traceclk_fck", | ||
2931 | .ops = &clkops_null, | ||
2932 | .init = &omap2_init_clksel_parent, | ||
2933 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | ||
2934 | .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK, | ||
2935 | .clksel = traceclk_clksel, | ||
2936 | .clkdm_name = "emu_clkdm", | ||
2937 | .recalc = &omap2_clksel_recalc, | ||
2938 | }; | ||
2939 | |||
2940 | /* SR clocks */ | ||
2941 | |||
2942 | /* SmartReflex fclk (VDD1) */ | ||
2943 | static struct clk sr1_fck = { | ||
2944 | .name = "sr1_fck", | ||
2945 | .ops = &clkops_omap2_dflt_wait, | ||
2946 | .parent = &sys_ck, | ||
2947 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | ||
2948 | .enable_bit = OMAP3430_EN_SR1_SHIFT, | ||
2949 | .recalc = &followparent_recalc, | ||
2950 | }; | ||
2951 | |||
2952 | /* SmartReflex fclk (VDD2) */ | ||
2953 | static struct clk sr2_fck = { | ||
2954 | .name = "sr2_fck", | ||
2955 | .ops = &clkops_omap2_dflt_wait, | ||
2956 | .parent = &sys_ck, | ||
2957 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | ||
2958 | .enable_bit = OMAP3430_EN_SR2_SHIFT, | ||
2959 | .recalc = &followparent_recalc, | ||
2960 | }; | ||
2961 | |||
2962 | static struct clk sr_l4_ick = { | ||
2963 | .name = "sr_l4_ick", | ||
2964 | .ops = &clkops_null, /* RMK: missing? */ | ||
2965 | .parent = &l4_ick, | ||
2966 | .clkdm_name = "core_l4_clkdm", | ||
2967 | .recalc = &followparent_recalc, | ||
2968 | }; | ||
2969 | |||
2970 | /* SECURE_32K_FCK clocks */ | ||
2971 | |||
2972 | static struct clk gpt12_fck = { | ||
2973 | .name = "gpt12_fck", | ||
2974 | .ops = &clkops_null, | ||
2975 | .parent = &secure_32k_fck, | ||
2976 | .recalc = &followparent_recalc, | ||
2977 | }; | ||
2978 | |||
2979 | static struct clk wdt1_fck = { | ||
2980 | .name = "wdt1_fck", | ||
2981 | .ops = &clkops_null, | ||
2982 | .parent = &secure_32k_fck, | ||
2983 | .recalc = &followparent_recalc, | ||
2984 | }; | ||
2985 | |||
2986 | |||
2987 | /* | ||
2988 | * clkdev | ||
2989 | */ | ||
2990 | |||
2991 | static struct omap_clk omap34xx_clks[] = { | ||
2992 | CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_343X), | ||
2993 | CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_343X), | ||
2994 | CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_343X), | ||
2995 | CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2), | ||
2996 | CLK(NULL, "virt_19_2m_ck", &virt_19_2m_ck, CK_343X), | ||
2997 | CLK(NULL, "virt_26m_ck", &virt_26m_ck, CK_343X), | ||
2998 | CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck, CK_343X), | ||
2999 | CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_343X), | ||
3000 | CLK(NULL, "sys_ck", &sys_ck, CK_343X), | ||
3001 | CLK(NULL, "sys_altclk", &sys_altclk, CK_343X), | ||
3002 | CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_343X), | ||
3003 | CLK(NULL, "sys_clkout1", &sys_clkout1, CK_343X), | ||
3004 | CLK(NULL, "dpll1_ck", &dpll1_ck, CK_343X), | ||
3005 | CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck, CK_343X), | ||
3006 | CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_343X), | ||
3007 | CLK(NULL, "dpll2_ck", &dpll2_ck, CK_343X), | ||
3008 | CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck, CK_343X), | ||
3009 | CLK(NULL, "dpll3_ck", &dpll3_ck, CK_343X), | ||
3010 | CLK(NULL, "core_ck", &core_ck, CK_343X), | ||
3011 | CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck, CK_343X), | ||
3012 | CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck, CK_343X), | ||
3013 | CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_343X), | ||
3014 | CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck, CK_343X), | ||
3015 | CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_343X), | ||
3016 | CLK("etb", "emu_core_alwon_ck", &emu_core_alwon_ck, CK_343X), | ||
3017 | CLK(NULL, "dpll4_ck", &dpll4_ck, CK_343X), | ||
3018 | CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck, CK_343X), | ||
3019 | CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_343X), | ||
3020 | CLK(NULL, "omap_96m_fck", &omap_96m_fck, CK_343X), | ||
3021 | CLK(NULL, "cm_96m_fck", &cm_96m_fck, CK_343X), | ||
3022 | CLK(NULL, "omap_54m_fck", &omap_54m_fck, CK_343X), | ||
3023 | CLK(NULL, "omap_48m_fck", &omap_48m_fck, CK_343X), | ||
3024 | CLK(NULL, "omap_12m_fck", &omap_12m_fck, CK_343X), | ||
3025 | CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck, CK_343X), | ||
3026 | CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_343X), | ||
3027 | CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck, CK_343X), | ||
3028 | CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_343X), | ||
3029 | CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck, CK_343X), | ||
3030 | CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_343X), | ||
3031 | CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck, CK_343X), | ||
3032 | CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_343X), | ||
3033 | CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck, CK_343X), | ||
3034 | CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_343X), | ||
3035 | CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck, CK_343X), | ||
3036 | CLK(NULL, "dpll5_ck", &dpll5_ck, CK_3430ES2), | ||
3037 | CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2), | ||
3038 | CLK(NULL, "clkout2_src_ck", &clkout2_src_ck, CK_343X), | ||
3039 | CLK(NULL, "sys_clkout2", &sys_clkout2, CK_343X), | ||
3040 | CLK(NULL, "corex2_fck", &corex2_fck, CK_343X), | ||
3041 | CLK(NULL, "dpll1_fck", &dpll1_fck, CK_343X), | ||
3042 | CLK(NULL, "mpu_ck", &mpu_ck, CK_343X), | ||
3043 | CLK(NULL, "arm_fck", &arm_fck, CK_343X), | ||
3044 | CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_343X), | ||
3045 | CLK(NULL, "dpll2_fck", &dpll2_fck, CK_343X), | ||
3046 | CLK(NULL, "iva2_ck", &iva2_ck, CK_343X), | ||
3047 | CLK(NULL, "l3_ick", &l3_ick, CK_343X), | ||
3048 | CLK(NULL, "l4_ick", &l4_ick, CK_343X), | ||
3049 | CLK(NULL, "rm_ick", &rm_ick, CK_343X), | ||
3050 | CLK(NULL, "gfx_l3_ck", &gfx_l3_ck, CK_3430ES1), | ||
3051 | CLK(NULL, "gfx_l3_fck", &gfx_l3_fck, CK_3430ES1), | ||
3052 | CLK(NULL, "gfx_l3_ick", &gfx_l3_ick, CK_3430ES1), | ||
3053 | CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck, CK_3430ES1), | ||
3054 | CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck, CK_3430ES1), | ||
3055 | CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2), | ||
3056 | CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2), | ||
3057 | CLK(NULL, "d2d_26m_fck", &d2d_26m_fck, CK_3430ES1), | ||
3058 | CLK(NULL, "modem_fck", &modem_fck, CK_343X), | ||
3059 | CLK(NULL, "sad2d_ick", &sad2d_ick, CK_343X), | ||
3060 | CLK(NULL, "mad2d_ick", &mad2d_ick, CK_343X), | ||
3061 | CLK(NULL, "gpt10_fck", &gpt10_fck, CK_343X), | ||
3062 | CLK(NULL, "gpt11_fck", &gpt11_fck, CK_343X), | ||
3063 | CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2), | ||
3064 | CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2), | ||
3065 | CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2), | ||
3066 | CLK(NULL, "core_96m_fck", &core_96m_fck, CK_343X), | ||
3067 | CLK("mmci-omap-hs.2", "fck", &mmchs3_fck, CK_3430ES2), | ||
3068 | CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_343X), | ||
3069 | CLK(NULL, "mspro_fck", &mspro_fck, CK_343X), | ||
3070 | CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_343X), | ||
3071 | CLK("i2c_omap.3", "fck", &i2c3_fck, CK_343X), | ||
3072 | CLK("i2c_omap.2", "fck", &i2c2_fck, CK_343X), | ||
3073 | CLK("i2c_omap.1", "fck", &i2c1_fck, CK_343X), | ||
3074 | CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_343X), | ||
3075 | CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_343X), | ||
3076 | CLK(NULL, "core_48m_fck", &core_48m_fck, CK_343X), | ||
3077 | CLK("omap2_mcspi.4", "fck", &mcspi4_fck, CK_343X), | ||
3078 | CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_343X), | ||
3079 | CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_343X), | ||
3080 | CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_343X), | ||
3081 | CLK(NULL, "uart2_fck", &uart2_fck, CK_343X), | ||
3082 | CLK(NULL, "uart1_fck", &uart1_fck, CK_343X), | ||
3083 | CLK(NULL, "fshostusb_fck", &fshostusb_fck, CK_3430ES1), | ||
3084 | CLK(NULL, "core_12m_fck", &core_12m_fck, CK_343X), | ||
3085 | CLK("omap_hdq.0", "fck", &hdq_fck, CK_343X), | ||
3086 | CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1, CK_3430ES1), | ||
3087 | CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2, CK_3430ES2), | ||
3088 | CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1, CK_3430ES1), | ||
3089 | CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es2, CK_3430ES2), | ||
3090 | CLK(NULL, "core_l3_ick", &core_l3_ick, CK_343X), | ||
3091 | CLK("musb_hdrc", "ick", &hsotgusb_ick_3430es1, CK_3430ES1), | ||
3092 | CLK("musb_hdrc", "ick", &hsotgusb_ick_3430es2, CK_3430ES2), | ||
3093 | CLK(NULL, "sdrc_ick", &sdrc_ick, CK_343X), | ||
3094 | CLK(NULL, "gpmc_fck", &gpmc_fck, CK_343X), | ||
3095 | CLK(NULL, "security_l3_ick", &security_l3_ick, CK_343X), | ||
3096 | CLK(NULL, "pka_ick", &pka_ick, CK_343X), | ||
3097 | CLK(NULL, "core_l4_ick", &core_l4_ick, CK_343X), | ||
3098 | CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2), | ||
3099 | CLK("mmci-omap-hs.2", "ick", &mmchs3_ick, CK_3430ES2), | ||
3100 | CLK(NULL, "icr_ick", &icr_ick, CK_343X), | ||
3101 | CLK(NULL, "aes2_ick", &aes2_ick, CK_343X), | ||
3102 | CLK(NULL, "sha12_ick", &sha12_ick, CK_343X), | ||
3103 | CLK(NULL, "des2_ick", &des2_ick, CK_343X), | ||
3104 | CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_343X), | ||
3105 | CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_343X), | ||
3106 | CLK(NULL, "mspro_ick", &mspro_ick, CK_343X), | ||
3107 | CLK("omap_hdq.0", "ick", &hdq_ick, CK_343X), | ||
3108 | CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_343X), | ||
3109 | CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_343X), | ||
3110 | CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_343X), | ||
3111 | CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_343X), | ||
3112 | CLK("i2c_omap.3", "ick", &i2c3_ick, CK_343X), | ||
3113 | CLK("i2c_omap.2", "ick", &i2c2_ick, CK_343X), | ||
3114 | CLK("i2c_omap.1", "ick", &i2c1_ick, CK_343X), | ||
3115 | CLK(NULL, "uart2_ick", &uart2_ick, CK_343X), | ||
3116 | CLK(NULL, "uart1_ick", &uart1_ick, CK_343X), | ||
3117 | CLK(NULL, "gpt11_ick", &gpt11_ick, CK_343X), | ||
3118 | CLK(NULL, "gpt10_ick", &gpt10_ick, CK_343X), | ||
3119 | CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_343X), | ||
3120 | CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_343X), | ||
3121 | CLK(NULL, "fac_ick", &fac_ick, CK_3430ES1), | ||
3122 | CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_343X), | ||
3123 | CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_343X), | ||
3124 | CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_343X), | ||
3125 | CLK(NULL, "ssi_ick", &ssi_ick_3430es1, CK_3430ES1), | ||
3126 | CLK(NULL, "ssi_ick", &ssi_ick_3430es2, CK_3430ES2), | ||
3127 | CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_3430ES1), | ||
3128 | CLK(NULL, "security_l4_ick2", &security_l4_ick2, CK_343X), | ||
3129 | CLK(NULL, "aes1_ick", &aes1_ick, CK_343X), | ||
3130 | CLK("omap_rng", "ick", &rng_ick, CK_343X), | ||
3131 | CLK(NULL, "sha11_ick", &sha11_ick, CK_343X), | ||
3132 | CLK(NULL, "des1_ick", &des1_ick, CK_343X), | ||
3133 | CLK("omapdss", "dss1_fck", &dss1_alwon_fck_3430es1, CK_3430ES1), | ||
3134 | CLK("omapdss", "dss1_fck", &dss1_alwon_fck_3430es2, CK_3430ES2), | ||
3135 | CLK("omapdss", "tv_fck", &dss_tv_fck, CK_343X), | ||
3136 | CLK("omapdss", "video_fck", &dss_96m_fck, CK_343X), | ||
3137 | CLK("omapdss", "dss2_fck", &dss2_alwon_fck, CK_343X), | ||
3138 | CLK("omapdss", "ick", &dss_ick_3430es1, CK_3430ES1), | ||
3139 | CLK("omapdss", "ick", &dss_ick_3430es2, CK_3430ES2), | ||
3140 | CLK(NULL, "cam_mclk", &cam_mclk, CK_343X), | ||
3141 | CLK(NULL, "cam_ick", &cam_ick, CK_343X), | ||
3142 | CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_343X), | ||
3143 | CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2), | ||
3144 | CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2), | ||
3145 | CLK(NULL, "usbhost_ick", &usbhost_ick, CK_3430ES2), | ||
3146 | CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2), | ||
3147 | CLK(NULL, "gpt1_fck", &gpt1_fck, CK_343X), | ||
3148 | CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_343X), | ||
3149 | CLK(NULL, "gpio1_dbck", &gpio1_dbck, CK_343X), | ||
3150 | CLK("omap_wdt", "fck", &wdt2_fck, CK_343X), | ||
3151 | CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_343X), | ||
3152 | CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2), | ||
3153 | CLK("omap_wdt", "ick", &wdt2_ick, CK_343X), | ||
3154 | CLK(NULL, "wdt1_ick", &wdt1_ick, CK_343X), | ||
3155 | CLK(NULL, "gpio1_ick", &gpio1_ick, CK_343X), | ||
3156 | CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_343X), | ||
3157 | CLK(NULL, "gpt12_ick", &gpt12_ick, CK_343X), | ||
3158 | CLK(NULL, "gpt1_ick", &gpt1_ick, CK_343X), | ||
3159 | CLK(NULL, "per_96m_fck", &per_96m_fck, CK_343X), | ||
3160 | CLK(NULL, "per_48m_fck", &per_48m_fck, CK_343X), | ||
3161 | CLK(NULL, "uart3_fck", &uart3_fck, CK_343X), | ||
3162 | CLK(NULL, "gpt2_fck", &gpt2_fck, CK_343X), | ||
3163 | CLK(NULL, "gpt3_fck", &gpt3_fck, CK_343X), | ||
3164 | CLK(NULL, "gpt4_fck", &gpt4_fck, CK_343X), | ||
3165 | CLK(NULL, "gpt5_fck", &gpt5_fck, CK_343X), | ||
3166 | CLK(NULL, "gpt6_fck", &gpt6_fck, CK_343X), | ||
3167 | CLK(NULL, "gpt7_fck", &gpt7_fck, CK_343X), | ||
3168 | CLK(NULL, "gpt8_fck", &gpt8_fck, CK_343X), | ||
3169 | CLK(NULL, "gpt9_fck", &gpt9_fck, CK_343X), | ||
3170 | CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck, CK_343X), | ||
3171 | CLK(NULL, "gpio6_dbck", &gpio6_dbck, CK_343X), | ||
3172 | CLK(NULL, "gpio5_dbck", &gpio5_dbck, CK_343X), | ||
3173 | CLK(NULL, "gpio4_dbck", &gpio4_dbck, CK_343X), | ||
3174 | CLK(NULL, "gpio3_dbck", &gpio3_dbck, CK_343X), | ||
3175 | CLK(NULL, "gpio2_dbck", &gpio2_dbck, CK_343X), | ||
3176 | CLK(NULL, "wdt3_fck", &wdt3_fck, CK_343X), | ||
3177 | CLK(NULL, "per_l4_ick", &per_l4_ick, CK_343X), | ||
3178 | CLK(NULL, "gpio6_ick", &gpio6_ick, CK_343X), | ||
3179 | CLK(NULL, "gpio5_ick", &gpio5_ick, CK_343X), | ||
3180 | CLK(NULL, "gpio4_ick", &gpio4_ick, CK_343X), | ||
3181 | CLK(NULL, "gpio3_ick", &gpio3_ick, CK_343X), | ||
3182 | CLK(NULL, "gpio2_ick", &gpio2_ick, CK_343X), | ||
3183 | CLK(NULL, "wdt3_ick", &wdt3_ick, CK_343X), | ||
3184 | CLK(NULL, "uart3_ick", &uart3_ick, CK_343X), | ||
3185 | CLK(NULL, "gpt9_ick", &gpt9_ick, CK_343X), | ||
3186 | CLK(NULL, "gpt8_ick", &gpt8_ick, CK_343X), | ||
3187 | CLK(NULL, "gpt7_ick", &gpt7_ick, CK_343X), | ||
3188 | CLK(NULL, "gpt6_ick", &gpt6_ick, CK_343X), | ||
3189 | CLK(NULL, "gpt5_ick", &gpt5_ick, CK_343X), | ||
3190 | CLK(NULL, "gpt4_ick", &gpt4_ick, CK_343X), | ||
3191 | CLK(NULL, "gpt3_ick", &gpt3_ick, CK_343X), | ||
3192 | CLK(NULL, "gpt2_ick", &gpt2_ick, CK_343X), | ||
3193 | CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_343X), | ||
3194 | CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_343X), | ||
3195 | CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_343X), | ||
3196 | CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_343X), | ||
3197 | CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_343X), | ||
3198 | CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_343X), | ||
3199 | CLK("etb", "emu_src_ck", &emu_src_ck, CK_343X), | ||
3200 | CLK(NULL, "pclk_fck", &pclk_fck, CK_343X), | ||
3201 | CLK(NULL, "pclkx2_fck", &pclkx2_fck, CK_343X), | ||
3202 | CLK(NULL, "atclk_fck", &atclk_fck, CK_343X), | ||
3203 | CLK(NULL, "traceclk_src_fck", &traceclk_src_fck, CK_343X), | ||
3204 | CLK(NULL, "traceclk_fck", &traceclk_fck, CK_343X), | ||
3205 | CLK(NULL, "sr1_fck", &sr1_fck, CK_343X), | ||
3206 | CLK(NULL, "sr2_fck", &sr2_fck, CK_343X), | ||
3207 | CLK(NULL, "sr_l4_ick", &sr_l4_ick, CK_343X), | ||
3208 | CLK(NULL, "secure_32k_fck", &secure_32k_fck, CK_343X), | ||
3209 | CLK(NULL, "gpt12_fck", &gpt12_fck, CK_343X), | ||
3210 | CLK(NULL, "wdt1_fck", &wdt1_fck, CK_343X), | ||
3211 | }; | ||
3212 | |||
3213 | |||
3214 | int __init omap2_clk_init(void) | ||
3215 | { | ||
3216 | /* struct prcm_config *prcm; */ | ||
3217 | struct omap_clk *c; | ||
3218 | /* u32 clkrate; */ | ||
3219 | u32 cpu_clkflg; | ||
3220 | |||
3221 | if (cpu_is_omap34xx()) { | ||
3222 | cpu_mask = RATE_IN_343X; | ||
3223 | cpu_clkflg = CK_343X; | ||
3224 | |||
3225 | /* | ||
3226 | * Update this if there are further clock changes between ES2 | ||
3227 | * and production parts | ||
3228 | */ | ||
3229 | if (omap_rev() == OMAP3430_REV_ES1_0) { | ||
3230 | /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */ | ||
3231 | cpu_clkflg |= CK_3430ES1; | ||
3232 | } else { | ||
3233 | cpu_mask |= RATE_IN_3430ES2; | ||
3234 | cpu_clkflg |= CK_3430ES2; | ||
3235 | } | ||
3236 | } | ||
3237 | |||
3238 | clk_init(&omap2_clk_functions); | ||
3239 | |||
3240 | for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++) | ||
3241 | clk_preinit(c->lk.clk); | ||
3242 | |||
3243 | for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++) | ||
3244 | if (c->cpu & cpu_clkflg) { | ||
3245 | clkdev_add(&c->lk); | ||
3246 | clk_register(c->lk.clk); | ||
3247 | omap2_init_clk_clkdm(c->lk.clk); | ||
3248 | } | ||
3249 | |||
3250 | /* REVISIT: Not yet ready for OMAP3 */ | ||
3251 | #if 0 | ||
3252 | /* Check the MPU rate set by bootloader */ | ||
3253 | clkrate = omap2_get_dpll_rate_24xx(&dpll_ck); | ||
3254 | for (prcm = rate_table; prcm->mpu_speed; prcm++) { | ||
3255 | if (!(prcm->flags & cpu_mask)) | ||
3256 | continue; | ||
3257 | if (prcm->xtal_speed != sys_ck.rate) | ||
3258 | continue; | ||
3259 | if (prcm->dpll_speed <= clkrate) | ||
3260 | break; | ||
3261 | } | ||
3262 | curr_prcm_set = prcm; | ||
3263 | #endif | ||
3264 | |||
3265 | recalculate_root_clocks(); | ||
3266 | |||
3267 | printk(KERN_INFO "Clocking rate (Crystal/Core/MPU): " | ||
3268 | "%ld.%01ld/%ld/%ld MHz\n", | ||
3269 | (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10, | ||
3270 | (core_ck.rate / 1000000), (arm_fck.rate / 1000000)); | ||
3271 | |||
3272 | /* | ||
3273 | * Only enable those clocks we will need, let the drivers | ||
3274 | * enable other clocks as necessary | ||
3275 | */ | ||
3276 | clk_enable_init_clocks(); | ||
3277 | |||
3278 | /* | ||
3279 | * Lock DPLL5 and put it in autoidle. | ||
3280 | */ | ||
3281 | if (omap_rev() >= OMAP3430_REV_ES2_0) | ||
3282 | omap3_clk_lock_dpll5(); | ||
3283 | |||
3284 | /* Avoid sleeping during omap3_core_dpll_m2_set_rate() */ | ||
3285 | sdrc_ick_p = clk_get(NULL, "sdrc_ick"); | ||
3286 | arm_fck_p = clk_get(NULL, "arm_fck"); | ||
3287 | |||
3288 | return 0; | ||
3289 | } | ||
diff --git a/arch/arm/mach-omap2/clock44xx.c b/arch/arm/mach-omap2/clock44xx.c new file mode 100644 index 000000000000..e370868a79a8 --- /dev/null +++ b/arch/arm/mach-omap2/clock44xx.c | |||
@@ -0,0 +1,33 @@ | |||
1 | /* | ||
2 | * OMAP4-specific clock framework functions | ||
3 | * | ||
4 | * Copyright (C) 2009 Texas Instruments, Inc. | ||
5 | * | ||
6 | * Rajendra Nayak (rnayak@ti.com) | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #include <linux/errno.h> | ||
14 | #include "clock.h" | ||
15 | |||
16 | struct clk_functions omap2_clk_functions = { | ||
17 | .clk_enable = omap2_clk_enable, | ||
18 | .clk_disable = omap2_clk_disable, | ||
19 | .clk_round_rate = omap2_clk_round_rate, | ||
20 | .clk_set_rate = omap2_clk_set_rate, | ||
21 | .clk_set_parent = omap2_clk_set_parent, | ||
22 | .clk_disable_unused = omap2_clk_disable_unused, | ||
23 | }; | ||
24 | |||
25 | const struct clkops clkops_noncore_dpll_ops = { | ||
26 | .enable = &omap3_noncore_dpll_enable, | ||
27 | .disable = &omap3_noncore_dpll_disable, | ||
28 | }; | ||
29 | |||
30 | void omap2_clk_prepare_for_reboot(void) | ||
31 | { | ||
32 | return; | ||
33 | } | ||
diff --git a/arch/arm/mach-omap2/clock44xx.h b/arch/arm/mach-omap2/clock44xx.h new file mode 100644 index 000000000000..59b9ced4daa1 --- /dev/null +++ b/arch/arm/mach-omap2/clock44xx.h | |||
@@ -0,0 +1,15 @@ | |||
1 | /* | ||
2 | * OMAP4 clock function prototypes and macros | ||
3 | * | ||
4 | * Copyright (C) 2009 Texas Instruments, Inc. | ||
5 | */ | ||
6 | |||
7 | #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_44XX_H | ||
8 | #define __ARCH_ARM_MACH_OMAP2_CLOCK_44XX_H | ||
9 | |||
10 | #define OMAP4430_MAX_DPLL_MULT 2048 | ||
11 | #define OMAP4430_MAX_DPLL_DIV 128 | ||
12 | |||
13 | extern const struct clkops clkops_noncore_dpll_ops; | ||
14 | |||
15 | #endif | ||
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c new file mode 100644 index 000000000000..2210e227d78a --- /dev/null +++ b/arch/arm/mach-omap2/clock44xx_data.c | |||
@@ -0,0 +1,2766 @@ | |||
1 | /* | ||
2 | * OMAP4 Clock data | ||
3 | * | ||
4 | * Copyright (C) 2009 Texas Instruments, Inc. | ||
5 | * Copyright (C) 2009 Nokia Corporation | ||
6 | * | ||
7 | * Paul Walmsley (paul@pwsan.com) | ||
8 | * Rajendra Nayak (rnayak@ti.com) | ||
9 | * Benoit Cousson (b-cousson@ti.com) | ||
10 | * | ||
11 | * This file is automatically generated from the OMAP hardware databases. | ||
12 | * We respectfully ask that any modifications to this file be coordinated | ||
13 | * with the public linux-omap@vger.kernel.org mailing list and the | ||
14 | * authors above to ensure that the autogeneration scripts are kept | ||
15 | * up-to-date with the file contents. | ||
16 | * | ||
17 | * This program is free software; you can redistribute it and/or modify | ||
18 | * it under the terms of the GNU General Public License version 2 as | ||
19 | * published by the Free Software Foundation. | ||
20 | */ | ||
21 | |||
22 | #include <linux/kernel.h> | ||
23 | #include <linux/module.h> | ||
24 | #include <linux/clk.h> | ||
25 | |||
26 | #include <plat/control.h> | ||
27 | #include <plat/clkdev_omap.h> | ||
28 | |||
29 | #include "clock.h" | ||
30 | #include "clock44xx.h" | ||
31 | #include "cm.h" | ||
32 | #include "cm-regbits-44xx.h" | ||
33 | #include "prm.h" | ||
34 | #include "prm-regbits-44xx.h" | ||
35 | |||
36 | /* Root clocks */ | ||
37 | |||
38 | static struct clk extalt_clkin_ck = { | ||
39 | .name = "extalt_clkin_ck", | ||
40 | .rate = 59000000, | ||
41 | .ops = &clkops_null, | ||
42 | .flags = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED, | ||
43 | }; | ||
44 | |||
45 | static struct clk pad_clks_ck = { | ||
46 | .name = "pad_clks_ck", | ||
47 | .rate = 12000000, | ||
48 | .ops = &clkops_null, | ||
49 | .flags = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED, | ||
50 | }; | ||
51 | |||
52 | static struct clk pad_slimbus_core_clks_ck = { | ||
53 | .name = "pad_slimbus_core_clks_ck", | ||
54 | .rate = 12000000, | ||
55 | .ops = &clkops_null, | ||
56 | .flags = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED, | ||
57 | }; | ||
58 | |||
59 | static struct clk secure_32k_clk_src_ck = { | ||
60 | .name = "secure_32k_clk_src_ck", | ||
61 | .rate = 32768, | ||
62 | .ops = &clkops_null, | ||
63 | .flags = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED, | ||
64 | }; | ||
65 | |||
66 | static struct clk slimbus_clk = { | ||
67 | .name = "slimbus_clk", | ||
68 | .rate = 12000000, | ||
69 | .ops = &clkops_null, | ||
70 | .flags = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED, | ||
71 | }; | ||
72 | |||
73 | static struct clk sys_32k_ck = { | ||
74 | .name = "sys_32k_ck", | ||
75 | .rate = 32768, | ||
76 | .ops = &clkops_null, | ||
77 | .flags = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED, | ||
78 | }; | ||
79 | |||
80 | static struct clk virt_12000000_ck = { | ||
81 | .name = "virt_12000000_ck", | ||
82 | .ops = &clkops_null, | ||
83 | .rate = 12000000, | ||
84 | }; | ||
85 | |||
86 | static struct clk virt_13000000_ck = { | ||
87 | .name = "virt_13000000_ck", | ||
88 | .ops = &clkops_null, | ||
89 | .rate = 13000000, | ||
90 | }; | ||
91 | |||
92 | static struct clk virt_16800000_ck = { | ||
93 | .name = "virt_16800000_ck", | ||
94 | .ops = &clkops_null, | ||
95 | .rate = 16800000, | ||
96 | }; | ||
97 | |||
98 | static struct clk virt_19200000_ck = { | ||
99 | .name = "virt_19200000_ck", | ||
100 | .ops = &clkops_null, | ||
101 | .rate = 19200000, | ||
102 | }; | ||
103 | |||
104 | static struct clk virt_26000000_ck = { | ||
105 | .name = "virt_26000000_ck", | ||
106 | .ops = &clkops_null, | ||
107 | .rate = 26000000, | ||
108 | }; | ||
109 | |||
110 | static struct clk virt_27000000_ck = { | ||
111 | .name = "virt_27000000_ck", | ||
112 | .ops = &clkops_null, | ||
113 | .rate = 27000000, | ||
114 | }; | ||
115 | |||
116 | static struct clk virt_38400000_ck = { | ||
117 | .name = "virt_38400000_ck", | ||
118 | .ops = &clkops_null, | ||
119 | .rate = 38400000, | ||
120 | }; | ||
121 | |||
122 | static const struct clksel_rate div_1_0_rates[] = { | ||
123 | { .div = 1, .val = 0, .flags = RATE_IN_4430 }, | ||
124 | { .div = 0 }, | ||
125 | }; | ||
126 | |||
127 | static const struct clksel_rate div_1_1_rates[] = { | ||
128 | { .div = 1, .val = 1, .flags = RATE_IN_4430 }, | ||
129 | { .div = 0 }, | ||
130 | }; | ||
131 | |||
132 | static const struct clksel_rate div_1_2_rates[] = { | ||
133 | { .div = 1, .val = 2, .flags = RATE_IN_4430 }, | ||
134 | { .div = 0 }, | ||
135 | }; | ||
136 | |||
137 | static const struct clksel_rate div_1_3_rates[] = { | ||
138 | { .div = 1, .val = 3, .flags = RATE_IN_4430 }, | ||
139 | { .div = 0 }, | ||
140 | }; | ||
141 | |||
142 | static const struct clksel_rate div_1_4_rates[] = { | ||
143 | { .div = 1, .val = 4, .flags = RATE_IN_4430 }, | ||
144 | { .div = 0 }, | ||
145 | }; | ||
146 | |||
147 | static const struct clksel_rate div_1_5_rates[] = { | ||
148 | { .div = 1, .val = 5, .flags = RATE_IN_4430 }, | ||
149 | { .div = 0 }, | ||
150 | }; | ||
151 | |||
152 | static const struct clksel_rate div_1_6_rates[] = { | ||
153 | { .div = 1, .val = 6, .flags = RATE_IN_4430 }, | ||
154 | { .div = 0 }, | ||
155 | }; | ||
156 | |||
157 | static const struct clksel_rate div_1_7_rates[] = { | ||
158 | { .div = 1, .val = 7, .flags = RATE_IN_4430 }, | ||
159 | { .div = 0 }, | ||
160 | }; | ||
161 | |||
162 | static const struct clksel sys_clkin_sel[] = { | ||
163 | { .parent = &virt_12000000_ck, .rates = div_1_1_rates }, | ||
164 | { .parent = &virt_13000000_ck, .rates = div_1_2_rates }, | ||
165 | { .parent = &virt_16800000_ck, .rates = div_1_3_rates }, | ||
166 | { .parent = &virt_19200000_ck, .rates = div_1_4_rates }, | ||
167 | { .parent = &virt_26000000_ck, .rates = div_1_5_rates }, | ||
168 | { .parent = &virt_27000000_ck, .rates = div_1_6_rates }, | ||
169 | { .parent = &virt_38400000_ck, .rates = div_1_7_rates }, | ||
170 | { .parent = NULL }, | ||
171 | }; | ||
172 | |||
173 | static struct clk sys_clkin_ck = { | ||
174 | .name = "sys_clkin_ck", | ||
175 | .rate = 38400000, | ||
176 | .clksel = sys_clkin_sel, | ||
177 | .init = &omap2_init_clksel_parent, | ||
178 | .clksel_reg = OMAP4430_CM_SYS_CLKSEL, | ||
179 | .clksel_mask = OMAP4430_SYS_CLKSEL_MASK, | ||
180 | .ops = &clkops_null, | ||
181 | .recalc = &omap2_clksel_recalc, | ||
182 | .flags = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED, | ||
183 | }; | ||
184 | |||
185 | static struct clk utmi_phy_clkout_ck = { | ||
186 | .name = "utmi_phy_clkout_ck", | ||
187 | .rate = 12000000, | ||
188 | .ops = &clkops_null, | ||
189 | .flags = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED, | ||
190 | }; | ||
191 | |||
192 | static struct clk xclk60mhsp1_ck = { | ||
193 | .name = "xclk60mhsp1_ck", | ||
194 | .rate = 12000000, | ||
195 | .ops = &clkops_null, | ||
196 | .flags = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED, | ||
197 | }; | ||
198 | |||
199 | static struct clk xclk60mhsp2_ck = { | ||
200 | .name = "xclk60mhsp2_ck", | ||
201 | .rate = 12000000, | ||
202 | .ops = &clkops_null, | ||
203 | .flags = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED, | ||
204 | }; | ||
205 | |||
206 | static struct clk xclk60motg_ck = { | ||
207 | .name = "xclk60motg_ck", | ||
208 | .rate = 60000000, | ||
209 | .ops = &clkops_null, | ||
210 | .flags = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED, | ||
211 | }; | ||
212 | |||
213 | /* Module clocks and DPLL outputs */ | ||
214 | |||
215 | static const struct clksel_rate div2_1to2_rates[] = { | ||
216 | { .div = 1, .val = 0, .flags = RATE_IN_4430 }, | ||
217 | { .div = 2, .val = 1, .flags = RATE_IN_4430 }, | ||
218 | { .div = 0 }, | ||
219 | }; | ||
220 | |||
221 | static const struct clksel dpll_sys_ref_clk_div[] = { | ||
222 | { .parent = &sys_clkin_ck, .rates = div2_1to2_rates }, | ||
223 | { .parent = NULL }, | ||
224 | }; | ||
225 | |||
226 | static struct clk dpll_sys_ref_clk = { | ||
227 | .name = "dpll_sys_ref_clk", | ||
228 | .parent = &sys_clkin_ck, | ||
229 | .clksel = dpll_sys_ref_clk_div, | ||
230 | .clksel_reg = OMAP4430_CM_DPLL_SYS_REF_CLKSEL, | ||
231 | .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, | ||
232 | .ops = &clkops_null, | ||
233 | .recalc = &omap2_clksel_recalc, | ||
234 | .round_rate = &omap2_clksel_round_rate, | ||
235 | .set_rate = &omap2_clksel_set_rate, | ||
236 | .flags = CLOCK_IN_OMAP4430, | ||
237 | }; | ||
238 | |||
239 | static const struct clksel abe_dpll_refclk_mux_sel[] = { | ||
240 | { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates }, | ||
241 | { .parent = &sys_32k_ck, .rates = div_1_1_rates }, | ||
242 | { .parent = NULL }, | ||
243 | }; | ||
244 | |||
245 | static struct clk abe_dpll_refclk_mux_ck = { | ||
246 | .name = "abe_dpll_refclk_mux_ck", | ||
247 | .parent = &dpll_sys_ref_clk, | ||
248 | .clksel = abe_dpll_refclk_mux_sel, | ||
249 | .init = &omap2_init_clksel_parent, | ||
250 | .clksel_reg = OMAP4430_CM_ABE_PLL_REF_CLKSEL, | ||
251 | .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, | ||
252 | .ops = &clkops_null, | ||
253 | .recalc = &omap2_clksel_recalc, | ||
254 | .flags = CLOCK_IN_OMAP4430, | ||
255 | }; | ||
256 | |||
257 | /* DPLL_ABE */ | ||
258 | static struct dpll_data dpll_abe_dd = { | ||
259 | .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_ABE, | ||
260 | .clk_bypass = &sys_clkin_ck, | ||
261 | .clk_ref = &abe_dpll_refclk_mux_ck, | ||
262 | .control_reg = OMAP4430_CM_CLKMODE_DPLL_ABE, | ||
263 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), | ||
264 | .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_ABE, | ||
265 | .idlest_reg = OMAP4430_CM_IDLEST_DPLL_ABE, | ||
266 | .mult_mask = OMAP4430_DPLL_MULT_MASK, | ||
267 | .div1_mask = OMAP4430_DPLL_DIV_MASK, | ||
268 | .enable_mask = OMAP4430_DPLL_EN_MASK, | ||
269 | .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, | ||
270 | .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, | ||
271 | .max_multiplier = OMAP4430_MAX_DPLL_MULT, | ||
272 | .max_divider = OMAP4430_MAX_DPLL_DIV, | ||
273 | .min_divider = 1, | ||
274 | }; | ||
275 | |||
276 | |||
277 | static struct clk dpll_abe_ck = { | ||
278 | .name = "dpll_abe_ck", | ||
279 | .parent = &abe_dpll_refclk_mux_ck, | ||
280 | .dpll_data = &dpll_abe_dd, | ||
281 | .init = &omap2_init_dpll_parent, | ||
282 | .ops = &clkops_noncore_dpll_ops, | ||
283 | .recalc = &omap3_dpll_recalc, | ||
284 | .round_rate = &omap2_dpll_round_rate, | ||
285 | .set_rate = &omap3_noncore_dpll_set_rate, | ||
286 | .flags = CLOCK_IN_OMAP4430, | ||
287 | }; | ||
288 | |||
289 | static struct clk dpll_abe_m2x2_ck = { | ||
290 | .name = "dpll_abe_m2x2_ck", | ||
291 | .parent = &dpll_abe_ck, | ||
292 | .ops = &clkops_null, | ||
293 | .recalc = &followparent_recalc, | ||
294 | .flags = CLOCK_IN_OMAP4430, | ||
295 | }; | ||
296 | |||
297 | static struct clk abe_24m_fclk = { | ||
298 | .name = "abe_24m_fclk", | ||
299 | .parent = &dpll_abe_m2x2_ck, | ||
300 | .ops = &clkops_null, | ||
301 | .recalc = &followparent_recalc, | ||
302 | .flags = CLOCK_IN_OMAP4430, | ||
303 | }; | ||
304 | |||
305 | static const struct clksel_rate div3_1to4_rates[] = { | ||
306 | { .div = 1, .val = 0, .flags = RATE_IN_4430 }, | ||
307 | { .div = 2, .val = 1, .flags = RATE_IN_4430 }, | ||
308 | { .div = 4, .val = 2, .flags = RATE_IN_4430 }, | ||
309 | { .div = 0 }, | ||
310 | }; | ||
311 | |||
312 | static const struct clksel abe_clk_div[] = { | ||
313 | { .parent = &dpll_abe_m2x2_ck, .rates = div3_1to4_rates }, | ||
314 | { .parent = NULL }, | ||
315 | }; | ||
316 | |||
317 | static struct clk abe_clk = { | ||
318 | .name = "abe_clk", | ||
319 | .parent = &dpll_abe_m2x2_ck, | ||
320 | .clksel = abe_clk_div, | ||
321 | .clksel_reg = OMAP4430_CM_CLKSEL_ABE, | ||
322 | .clksel_mask = OMAP4430_CLKSEL_OPP_MASK, | ||
323 | .ops = &clkops_null, | ||
324 | .recalc = &omap2_clksel_recalc, | ||
325 | .round_rate = &omap2_clksel_round_rate, | ||
326 | .set_rate = &omap2_clksel_set_rate, | ||
327 | .flags = CLOCK_IN_OMAP4430, | ||
328 | }; | ||
329 | |||
330 | static const struct clksel aess_fclk_div[] = { | ||
331 | { .parent = &abe_clk, .rates = div2_1to2_rates }, | ||
332 | { .parent = NULL }, | ||
333 | }; | ||
334 | |||
335 | static struct clk aess_fclk = { | ||
336 | .name = "aess_fclk", | ||
337 | .parent = &abe_clk, | ||
338 | .clksel = aess_fclk_div, | ||
339 | .clksel_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL, | ||
340 | .clksel_mask = OMAP4430_CLKSEL_AESS_FCLK_MASK, | ||
341 | .ops = &clkops_null, | ||
342 | .recalc = &omap2_clksel_recalc, | ||
343 | .round_rate = &omap2_clksel_round_rate, | ||
344 | .set_rate = &omap2_clksel_set_rate, | ||
345 | .flags = CLOCK_IN_OMAP4430, | ||
346 | }; | ||
347 | |||
348 | static const struct clksel_rate div31_1to31_rates[] = { | ||
349 | { .div = 1, .val = 0, .flags = RATE_IN_4430 }, | ||
350 | { .div = 2, .val = 1, .flags = RATE_IN_4430 }, | ||
351 | { .div = 3, .val = 2, .flags = RATE_IN_4430 }, | ||
352 | { .div = 4, .val = 3, .flags = RATE_IN_4430 }, | ||
353 | { .div = 5, .val = 4, .flags = RATE_IN_4430 }, | ||
354 | { .div = 6, .val = 5, .flags = RATE_IN_4430 }, | ||
355 | { .div = 7, .val = 6, .flags = RATE_IN_4430 }, | ||
356 | { .div = 8, .val = 7, .flags = RATE_IN_4430 }, | ||
357 | { .div = 9, .val = 8, .flags = RATE_IN_4430 }, | ||
358 | { .div = 10, .val = 9, .flags = RATE_IN_4430 }, | ||
359 | { .div = 11, .val = 10, .flags = RATE_IN_4430 }, | ||
360 | { .div = 12, .val = 11, .flags = RATE_IN_4430 }, | ||
361 | { .div = 13, .val = 12, .flags = RATE_IN_4430 }, | ||
362 | { .div = 14, .val = 13, .flags = RATE_IN_4430 }, | ||
363 | { .div = 15, .val = 14, .flags = RATE_IN_4430 }, | ||
364 | { .div = 16, .val = 15, .flags = RATE_IN_4430 }, | ||
365 | { .div = 17, .val = 16, .flags = RATE_IN_4430 }, | ||
366 | { .div = 18, .val = 17, .flags = RATE_IN_4430 }, | ||
367 | { .div = 19, .val = 18, .flags = RATE_IN_4430 }, | ||
368 | { .div = 20, .val = 19, .flags = RATE_IN_4430 }, | ||
369 | { .div = 21, .val = 20, .flags = RATE_IN_4430 }, | ||
370 | { .div = 22, .val = 21, .flags = RATE_IN_4430 }, | ||
371 | { .div = 23, .val = 22, .flags = RATE_IN_4430 }, | ||
372 | { .div = 24, .val = 23, .flags = RATE_IN_4430 }, | ||
373 | { .div = 25, .val = 24, .flags = RATE_IN_4430 }, | ||
374 | { .div = 26, .val = 25, .flags = RATE_IN_4430 }, | ||
375 | { .div = 27, .val = 26, .flags = RATE_IN_4430 }, | ||
376 | { .div = 28, .val = 27, .flags = RATE_IN_4430 }, | ||
377 | { .div = 29, .val = 28, .flags = RATE_IN_4430 }, | ||
378 | { .div = 30, .val = 29, .flags = RATE_IN_4430 }, | ||
379 | { .div = 31, .val = 30, .flags = RATE_IN_4430 }, | ||
380 | { .div = 0 }, | ||
381 | }; | ||
382 | |||
383 | static const struct clksel dpll_abe_m3_div[] = { | ||
384 | { .parent = &dpll_abe_ck, .rates = div31_1to31_rates }, | ||
385 | { .parent = NULL }, | ||
386 | }; | ||
387 | |||
388 | static struct clk dpll_abe_m3_ck = { | ||
389 | .name = "dpll_abe_m3_ck", | ||
390 | .parent = &dpll_abe_ck, | ||
391 | .clksel = dpll_abe_m3_div, | ||
392 | .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_ABE, | ||
393 | .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, | ||
394 | .ops = &clkops_null, | ||
395 | .recalc = &omap2_clksel_recalc, | ||
396 | .round_rate = &omap2_clksel_round_rate, | ||
397 | .set_rate = &omap2_clksel_set_rate, | ||
398 | .flags = CLOCK_IN_OMAP4430, | ||
399 | }; | ||
400 | |||
401 | static const struct clksel core_hsd_byp_clk_mux_sel[] = { | ||
402 | { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates }, | ||
403 | { .parent = &dpll_abe_m3_ck, .rates = div_1_1_rates }, | ||
404 | { .parent = NULL }, | ||
405 | }; | ||
406 | |||
407 | static struct clk core_hsd_byp_clk_mux_ck = { | ||
408 | .name = "core_hsd_byp_clk_mux_ck", | ||
409 | .parent = &dpll_sys_ref_clk, | ||
410 | .clksel = core_hsd_byp_clk_mux_sel, | ||
411 | .init = &omap2_init_clksel_parent, | ||
412 | .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_CORE, | ||
413 | .clksel_mask = OMAP4430_DPLL_BYP_CLKSEL_MASK, | ||
414 | .ops = &clkops_null, | ||
415 | .recalc = &omap2_clksel_recalc, | ||
416 | .flags = CLOCK_IN_OMAP4430, | ||
417 | }; | ||
418 | |||
419 | /* DPLL_CORE */ | ||
420 | static struct dpll_data dpll_core_dd = { | ||
421 | .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_CORE, | ||
422 | .clk_bypass = &core_hsd_byp_clk_mux_ck, | ||
423 | .clk_ref = &dpll_sys_ref_clk, | ||
424 | .control_reg = OMAP4430_CM_CLKMODE_DPLL_CORE, | ||
425 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), | ||
426 | .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_CORE, | ||
427 | .idlest_reg = OMAP4430_CM_IDLEST_DPLL_CORE, | ||
428 | .mult_mask = OMAP4430_DPLL_MULT_MASK, | ||
429 | .div1_mask = OMAP4430_DPLL_DIV_MASK, | ||
430 | .enable_mask = OMAP4430_DPLL_EN_MASK, | ||
431 | .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, | ||
432 | .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, | ||
433 | .max_multiplier = OMAP4430_MAX_DPLL_MULT, | ||
434 | .max_divider = OMAP4430_MAX_DPLL_DIV, | ||
435 | .min_divider = 1, | ||
436 | }; | ||
437 | |||
438 | |||
439 | static struct clk dpll_core_ck = { | ||
440 | .name = "dpll_core_ck", | ||
441 | .parent = &dpll_sys_ref_clk, | ||
442 | .dpll_data = &dpll_core_dd, | ||
443 | .init = &omap2_init_dpll_parent, | ||
444 | .ops = &clkops_null, | ||
445 | .recalc = &omap3_dpll_recalc, | ||
446 | .flags = CLOCK_IN_OMAP4430, | ||
447 | }; | ||
448 | |||
449 | static const struct clksel dpll_core_m6_div[] = { | ||
450 | { .parent = &dpll_core_ck, .rates = div31_1to31_rates }, | ||
451 | { .parent = NULL }, | ||
452 | }; | ||
453 | |||
454 | static struct clk dpll_core_m6_ck = { | ||
455 | .name = "dpll_core_m6_ck", | ||
456 | .parent = &dpll_core_ck, | ||
457 | .clksel = dpll_core_m6_div, | ||
458 | .clksel_reg = OMAP4430_CM_DIV_M6_DPLL_CORE, | ||
459 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK, | ||
460 | .ops = &clkops_null, | ||
461 | .recalc = &omap2_clksel_recalc, | ||
462 | .round_rate = &omap2_clksel_round_rate, | ||
463 | .set_rate = &omap2_clksel_set_rate, | ||
464 | .flags = CLOCK_IN_OMAP4430, | ||
465 | }; | ||
466 | |||
467 | static const struct clksel dbgclk_mux_sel[] = { | ||
468 | { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, | ||
469 | { .parent = &dpll_core_m6_ck, .rates = div_1_1_rates }, | ||
470 | { .parent = NULL }, | ||
471 | }; | ||
472 | |||
473 | static struct clk dbgclk_mux_ck = { | ||
474 | .name = "dbgclk_mux_ck", | ||
475 | .parent = &sys_clkin_ck, | ||
476 | .ops = &clkops_null, | ||
477 | .recalc = &followparent_recalc, | ||
478 | .flags = CLOCK_IN_OMAP4430, | ||
479 | }; | ||
480 | |||
481 | static struct clk dpll_core_m2_ck = { | ||
482 | .name = "dpll_core_m2_ck", | ||
483 | .parent = &dpll_core_ck, | ||
484 | .clksel = dpll_core_m6_div, | ||
485 | .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_CORE, | ||
486 | .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, | ||
487 | .ops = &clkops_null, | ||
488 | .recalc = &omap2_clksel_recalc, | ||
489 | .round_rate = &omap2_clksel_round_rate, | ||
490 | .set_rate = &omap2_clksel_set_rate, | ||
491 | .flags = CLOCK_IN_OMAP4430, | ||
492 | }; | ||
493 | |||
494 | static struct clk ddrphy_ck = { | ||
495 | .name = "ddrphy_ck", | ||
496 | .parent = &dpll_core_m2_ck, | ||
497 | .ops = &clkops_null, | ||
498 | .recalc = &followparent_recalc, | ||
499 | .flags = CLOCK_IN_OMAP4430, | ||
500 | }; | ||
501 | |||
502 | static struct clk dpll_core_m5_ck = { | ||
503 | .name = "dpll_core_m5_ck", | ||
504 | .parent = &dpll_core_ck, | ||
505 | .clksel = dpll_core_m6_div, | ||
506 | .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_CORE, | ||
507 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK, | ||
508 | .ops = &clkops_null, | ||
509 | .recalc = &omap2_clksel_recalc, | ||
510 | .round_rate = &omap2_clksel_round_rate, | ||
511 | .set_rate = &omap2_clksel_set_rate, | ||
512 | .flags = CLOCK_IN_OMAP4430, | ||
513 | }; | ||
514 | |||
515 | static const struct clksel div_core_div[] = { | ||
516 | { .parent = &dpll_core_m5_ck, .rates = div2_1to2_rates }, | ||
517 | { .parent = NULL }, | ||
518 | }; | ||
519 | |||
520 | static struct clk div_core_ck = { | ||
521 | .name = "div_core_ck", | ||
522 | .parent = &dpll_core_m5_ck, | ||
523 | .clksel = div_core_div, | ||
524 | .clksel_reg = OMAP4430_CM_CLKSEL_CORE, | ||
525 | .clksel_mask = OMAP4430_CLKSEL_CORE_MASK, | ||
526 | .ops = &clkops_null, | ||
527 | .recalc = &omap2_clksel_recalc, | ||
528 | .round_rate = &omap2_clksel_round_rate, | ||
529 | .set_rate = &omap2_clksel_set_rate, | ||
530 | .flags = CLOCK_IN_OMAP4430, | ||
531 | }; | ||
532 | |||
533 | static const struct clksel_rate div4_1to8_rates[] = { | ||
534 | { .div = 1, .val = 0, .flags = RATE_IN_4430 }, | ||
535 | { .div = 2, .val = 1, .flags = RATE_IN_4430 }, | ||
536 | { .div = 4, .val = 2, .flags = RATE_IN_4430 }, | ||
537 | { .div = 8, .val = 3, .flags = RATE_IN_4430 }, | ||
538 | { .div = 0 }, | ||
539 | }; | ||
540 | |||
541 | static const struct clksel div_iva_hs_clk_div[] = { | ||
542 | { .parent = &dpll_core_m5_ck, .rates = div4_1to8_rates }, | ||
543 | { .parent = NULL }, | ||
544 | }; | ||
545 | |||
546 | static struct clk div_iva_hs_clk = { | ||
547 | .name = "div_iva_hs_clk", | ||
548 | .parent = &dpll_core_m5_ck, | ||
549 | .clksel = div_iva_hs_clk_div, | ||
550 | .clksel_reg = OMAP4430_CM_BYPCLK_DPLL_IVA, | ||
551 | .clksel_mask = OMAP4430_CLKSEL_0_1_MASK, | ||
552 | .ops = &clkops_null, | ||
553 | .recalc = &omap2_clksel_recalc, | ||
554 | .round_rate = &omap2_clksel_round_rate, | ||
555 | .set_rate = &omap2_clksel_set_rate, | ||
556 | .flags = CLOCK_IN_OMAP4430, | ||
557 | }; | ||
558 | |||
559 | static struct clk div_mpu_hs_clk = { | ||
560 | .name = "div_mpu_hs_clk", | ||
561 | .parent = &dpll_core_m5_ck, | ||
562 | .clksel = div_iva_hs_clk_div, | ||
563 | .clksel_reg = OMAP4430_CM_BYPCLK_DPLL_MPU, | ||
564 | .clksel_mask = OMAP4430_CLKSEL_0_1_MASK, | ||
565 | .ops = &clkops_null, | ||
566 | .recalc = &omap2_clksel_recalc, | ||
567 | .round_rate = &omap2_clksel_round_rate, | ||
568 | .set_rate = &omap2_clksel_set_rate, | ||
569 | .flags = CLOCK_IN_OMAP4430, | ||
570 | }; | ||
571 | |||
572 | static struct clk dpll_core_m4_ck = { | ||
573 | .name = "dpll_core_m4_ck", | ||
574 | .parent = &dpll_core_ck, | ||
575 | .clksel = dpll_core_m6_div, | ||
576 | .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_CORE, | ||
577 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK, | ||
578 | .ops = &clkops_null, | ||
579 | .recalc = &omap2_clksel_recalc, | ||
580 | .round_rate = &omap2_clksel_round_rate, | ||
581 | .set_rate = &omap2_clksel_set_rate, | ||
582 | .flags = CLOCK_IN_OMAP4430, | ||
583 | }; | ||
584 | |||
585 | static struct clk dll_clk_div_ck = { | ||
586 | .name = "dll_clk_div_ck", | ||
587 | .parent = &dpll_core_m4_ck, | ||
588 | .ops = &clkops_null, | ||
589 | .recalc = &followparent_recalc, | ||
590 | .flags = CLOCK_IN_OMAP4430, | ||
591 | }; | ||
592 | |||
593 | static struct clk dpll_abe_m2_ck = { | ||
594 | .name = "dpll_abe_m2_ck", | ||
595 | .parent = &dpll_abe_ck, | ||
596 | .clksel = dpll_abe_m3_div, | ||
597 | .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE, | ||
598 | .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, | ||
599 | .ops = &clkops_null, | ||
600 | .recalc = &omap2_clksel_recalc, | ||
601 | .round_rate = &omap2_clksel_round_rate, | ||
602 | .set_rate = &omap2_clksel_set_rate, | ||
603 | .flags = CLOCK_IN_OMAP4430, | ||
604 | }; | ||
605 | |||
606 | static struct clk dpll_core_m3_ck = { | ||
607 | .name = "dpll_core_m3_ck", | ||
608 | .parent = &dpll_core_ck, | ||
609 | .clksel = dpll_core_m6_div, | ||
610 | .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_CORE, | ||
611 | .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, | ||
612 | .ops = &clkops_null, | ||
613 | .recalc = &omap2_clksel_recalc, | ||
614 | .round_rate = &omap2_clksel_round_rate, | ||
615 | .set_rate = &omap2_clksel_set_rate, | ||
616 | .flags = CLOCK_IN_OMAP4430, | ||
617 | }; | ||
618 | |||
619 | static struct clk dpll_core_m7_ck = { | ||
620 | .name = "dpll_core_m7_ck", | ||
621 | .parent = &dpll_core_ck, | ||
622 | .clksel = dpll_core_m6_div, | ||
623 | .clksel_reg = OMAP4430_CM_DIV_M7_DPLL_CORE, | ||
624 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK, | ||
625 | .ops = &clkops_null, | ||
626 | .recalc = &omap2_clksel_recalc, | ||
627 | .round_rate = &omap2_clksel_round_rate, | ||
628 | .set_rate = &omap2_clksel_set_rate, | ||
629 | .flags = CLOCK_IN_OMAP4430, | ||
630 | }; | ||
631 | |||
632 | static const struct clksel iva_hsd_byp_clk_mux_sel[] = { | ||
633 | { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates }, | ||
634 | { .parent = &div_iva_hs_clk, .rates = div_1_1_rates }, | ||
635 | { .parent = NULL }, | ||
636 | }; | ||
637 | |||
638 | static struct clk iva_hsd_byp_clk_mux_ck = { | ||
639 | .name = "iva_hsd_byp_clk_mux_ck", | ||
640 | .parent = &dpll_sys_ref_clk, | ||
641 | .ops = &clkops_null, | ||
642 | .recalc = &followparent_recalc, | ||
643 | .flags = CLOCK_IN_OMAP4430, | ||
644 | }; | ||
645 | |||
646 | /* DPLL_IVA */ | ||
647 | static struct dpll_data dpll_iva_dd = { | ||
648 | .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_IVA, | ||
649 | .clk_bypass = &iva_hsd_byp_clk_mux_ck, | ||
650 | .clk_ref = &dpll_sys_ref_clk, | ||
651 | .control_reg = OMAP4430_CM_CLKMODE_DPLL_IVA, | ||
652 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), | ||
653 | .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_IVA, | ||
654 | .idlest_reg = OMAP4430_CM_IDLEST_DPLL_IVA, | ||
655 | .mult_mask = OMAP4430_DPLL_MULT_MASK, | ||
656 | .div1_mask = OMAP4430_DPLL_DIV_MASK, | ||
657 | .enable_mask = OMAP4430_DPLL_EN_MASK, | ||
658 | .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, | ||
659 | .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, | ||
660 | .max_multiplier = OMAP4430_MAX_DPLL_MULT, | ||
661 | .max_divider = OMAP4430_MAX_DPLL_DIV, | ||
662 | .min_divider = 1, | ||
663 | }; | ||
664 | |||
665 | |||
666 | static struct clk dpll_iva_ck = { | ||
667 | .name = "dpll_iva_ck", | ||
668 | .parent = &dpll_sys_ref_clk, | ||
669 | .dpll_data = &dpll_iva_dd, | ||
670 | .init = &omap2_init_dpll_parent, | ||
671 | .ops = &clkops_noncore_dpll_ops, | ||
672 | .recalc = &omap3_dpll_recalc, | ||
673 | .round_rate = &omap2_dpll_round_rate, | ||
674 | .set_rate = &omap3_noncore_dpll_set_rate, | ||
675 | .flags = CLOCK_IN_OMAP4430, | ||
676 | }; | ||
677 | |||
678 | static const struct clksel dpll_iva_m4_div[] = { | ||
679 | { .parent = &dpll_iva_ck, .rates = div31_1to31_rates }, | ||
680 | { .parent = NULL }, | ||
681 | }; | ||
682 | |||
683 | static struct clk dpll_iva_m4_ck = { | ||
684 | .name = "dpll_iva_m4_ck", | ||
685 | .parent = &dpll_iva_ck, | ||
686 | .clksel = dpll_iva_m4_div, | ||
687 | .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_IVA, | ||
688 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK, | ||
689 | .ops = &clkops_null, | ||
690 | .recalc = &omap2_clksel_recalc, | ||
691 | .round_rate = &omap2_clksel_round_rate, | ||
692 | .set_rate = &omap2_clksel_set_rate, | ||
693 | .flags = CLOCK_IN_OMAP4430, | ||
694 | }; | ||
695 | |||
696 | static struct clk dpll_iva_m5_ck = { | ||
697 | .name = "dpll_iva_m5_ck", | ||
698 | .parent = &dpll_iva_ck, | ||
699 | .clksel = dpll_iva_m4_div, | ||
700 | .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_IVA, | ||
701 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK, | ||
702 | .ops = &clkops_null, | ||
703 | .recalc = &omap2_clksel_recalc, | ||
704 | .round_rate = &omap2_clksel_round_rate, | ||
705 | .set_rate = &omap2_clksel_set_rate, | ||
706 | .flags = CLOCK_IN_OMAP4430, | ||
707 | }; | ||
708 | |||
709 | /* DPLL_MPU */ | ||
710 | static struct dpll_data dpll_mpu_dd = { | ||
711 | .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_MPU, | ||
712 | .clk_bypass = &div_mpu_hs_clk, | ||
713 | .clk_ref = &dpll_sys_ref_clk, | ||
714 | .control_reg = OMAP4430_CM_CLKMODE_DPLL_MPU, | ||
715 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), | ||
716 | .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_MPU, | ||
717 | .idlest_reg = OMAP4430_CM_IDLEST_DPLL_MPU, | ||
718 | .mult_mask = OMAP4430_DPLL_MULT_MASK, | ||
719 | .div1_mask = OMAP4430_DPLL_DIV_MASK, | ||
720 | .enable_mask = OMAP4430_DPLL_EN_MASK, | ||
721 | .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, | ||
722 | .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, | ||
723 | .max_multiplier = OMAP4430_MAX_DPLL_MULT, | ||
724 | .max_divider = OMAP4430_MAX_DPLL_DIV, | ||
725 | .min_divider = 1, | ||
726 | }; | ||
727 | |||
728 | |||
729 | static struct clk dpll_mpu_ck = { | ||
730 | .name = "dpll_mpu_ck", | ||
731 | .parent = &dpll_sys_ref_clk, | ||
732 | .dpll_data = &dpll_mpu_dd, | ||
733 | .init = &omap2_init_dpll_parent, | ||
734 | .ops = &clkops_noncore_dpll_ops, | ||
735 | .recalc = &omap3_dpll_recalc, | ||
736 | .round_rate = &omap2_dpll_round_rate, | ||
737 | .set_rate = &omap3_noncore_dpll_set_rate, | ||
738 | .flags = CLOCK_IN_OMAP4430, | ||
739 | }; | ||
740 | |||
741 | static const struct clksel dpll_mpu_m2_div[] = { | ||
742 | { .parent = &dpll_mpu_ck, .rates = div31_1to31_rates }, | ||
743 | { .parent = NULL }, | ||
744 | }; | ||
745 | |||
746 | static struct clk dpll_mpu_m2_ck = { | ||
747 | .name = "dpll_mpu_m2_ck", | ||
748 | .parent = &dpll_mpu_ck, | ||
749 | .clksel = dpll_mpu_m2_div, | ||
750 | .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_MPU, | ||
751 | .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, | ||
752 | .ops = &clkops_null, | ||
753 | .recalc = &omap2_clksel_recalc, | ||
754 | .round_rate = &omap2_clksel_round_rate, | ||
755 | .set_rate = &omap2_clksel_set_rate, | ||
756 | .flags = CLOCK_IN_OMAP4430, | ||
757 | }; | ||
758 | |||
759 | static struct clk per_hs_clk_div_ck = { | ||
760 | .name = "per_hs_clk_div_ck", | ||
761 | .parent = &dpll_abe_m3_ck, | ||
762 | .ops = &clkops_null, | ||
763 | .recalc = &followparent_recalc, | ||
764 | .flags = CLOCK_IN_OMAP4430, | ||
765 | }; | ||
766 | |||
767 | static const struct clksel per_hsd_byp_clk_mux_sel[] = { | ||
768 | { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates }, | ||
769 | { .parent = &per_hs_clk_div_ck, .rates = div_1_1_rates }, | ||
770 | { .parent = NULL }, | ||
771 | }; | ||
772 | |||
773 | static struct clk per_hsd_byp_clk_mux_ck = { | ||
774 | .name = "per_hsd_byp_clk_mux_ck", | ||
775 | .parent = &dpll_sys_ref_clk, | ||
776 | .clksel = per_hsd_byp_clk_mux_sel, | ||
777 | .init = &omap2_init_clksel_parent, | ||
778 | .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_PER, | ||
779 | .clksel_mask = OMAP4430_DPLL_BYP_CLKSEL_MASK, | ||
780 | .ops = &clkops_null, | ||
781 | .recalc = &omap2_clksel_recalc, | ||
782 | .flags = CLOCK_IN_OMAP4430, | ||
783 | }; | ||
784 | |||
785 | /* DPLL_PER */ | ||
786 | static struct dpll_data dpll_per_dd = { | ||
787 | .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_PER, | ||
788 | .clk_bypass = &per_hsd_byp_clk_mux_ck, | ||
789 | .clk_ref = &dpll_sys_ref_clk, | ||
790 | .control_reg = OMAP4430_CM_CLKMODE_DPLL_PER, | ||
791 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), | ||
792 | .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_PER, | ||
793 | .idlest_reg = OMAP4430_CM_IDLEST_DPLL_PER, | ||
794 | .mult_mask = OMAP4430_DPLL_MULT_MASK, | ||
795 | .div1_mask = OMAP4430_DPLL_DIV_MASK, | ||
796 | .enable_mask = OMAP4430_DPLL_EN_MASK, | ||
797 | .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, | ||
798 | .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, | ||
799 | .max_multiplier = OMAP4430_MAX_DPLL_MULT, | ||
800 | .max_divider = OMAP4430_MAX_DPLL_DIV, | ||
801 | .min_divider = 1, | ||
802 | }; | ||
803 | |||
804 | |||
805 | static struct clk dpll_per_ck = { | ||
806 | .name = "dpll_per_ck", | ||
807 | .parent = &dpll_sys_ref_clk, | ||
808 | .dpll_data = &dpll_per_dd, | ||
809 | .init = &omap2_init_dpll_parent, | ||
810 | .ops = &clkops_noncore_dpll_ops, | ||
811 | .recalc = &omap3_dpll_recalc, | ||
812 | .round_rate = &omap2_dpll_round_rate, | ||
813 | .set_rate = &omap3_noncore_dpll_set_rate, | ||
814 | .flags = CLOCK_IN_OMAP4430, | ||
815 | }; | ||
816 | |||
817 | static const struct clksel dpll_per_m2_div[] = { | ||
818 | { .parent = &dpll_per_ck, .rates = div31_1to31_rates }, | ||
819 | { .parent = NULL }, | ||
820 | }; | ||
821 | |||
822 | static struct clk dpll_per_m2_ck = { | ||
823 | .name = "dpll_per_m2_ck", | ||
824 | .parent = &dpll_per_ck, | ||
825 | .clksel = dpll_per_m2_div, | ||
826 | .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER, | ||
827 | .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, | ||
828 | .ops = &clkops_null, | ||
829 | .recalc = &omap2_clksel_recalc, | ||
830 | .round_rate = &omap2_clksel_round_rate, | ||
831 | .set_rate = &omap2_clksel_set_rate, | ||
832 | .flags = CLOCK_IN_OMAP4430, | ||
833 | }; | ||
834 | |||
835 | static struct clk dpll_per_m2x2_ck = { | ||
836 | .name = "dpll_per_m2x2_ck", | ||
837 | .parent = &dpll_per_ck, | ||
838 | .ops = &clkops_null, | ||
839 | .recalc = &followparent_recalc, | ||
840 | .flags = CLOCK_IN_OMAP4430, | ||
841 | }; | ||
842 | |||
843 | static struct clk dpll_per_m3_ck = { | ||
844 | .name = "dpll_per_m3_ck", | ||
845 | .parent = &dpll_per_ck, | ||
846 | .clksel = dpll_per_m2_div, | ||
847 | .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_PER, | ||
848 | .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, | ||
849 | .ops = &clkops_null, | ||
850 | .recalc = &omap2_clksel_recalc, | ||
851 | .round_rate = &omap2_clksel_round_rate, | ||
852 | .set_rate = &omap2_clksel_set_rate, | ||
853 | .flags = CLOCK_IN_OMAP4430, | ||
854 | }; | ||
855 | |||
856 | static struct clk dpll_per_m4_ck = { | ||
857 | .name = "dpll_per_m4_ck", | ||
858 | .parent = &dpll_per_ck, | ||
859 | .clksel = dpll_per_m2_div, | ||
860 | .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_PER, | ||
861 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK, | ||
862 | .ops = &clkops_null, | ||
863 | .recalc = &omap2_clksel_recalc, | ||
864 | .round_rate = &omap2_clksel_round_rate, | ||
865 | .set_rate = &omap2_clksel_set_rate, | ||
866 | .flags = CLOCK_IN_OMAP4430, | ||
867 | }; | ||
868 | |||
869 | static struct clk dpll_per_m5_ck = { | ||
870 | .name = "dpll_per_m5_ck", | ||
871 | .parent = &dpll_per_ck, | ||
872 | .clksel = dpll_per_m2_div, | ||
873 | .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_PER, | ||
874 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK, | ||
875 | .ops = &clkops_null, | ||
876 | .recalc = &omap2_clksel_recalc, | ||
877 | .round_rate = &omap2_clksel_round_rate, | ||
878 | .set_rate = &omap2_clksel_set_rate, | ||
879 | .flags = CLOCK_IN_OMAP4430, | ||
880 | }; | ||
881 | |||
882 | static struct clk dpll_per_m6_ck = { | ||
883 | .name = "dpll_per_m6_ck", | ||
884 | .parent = &dpll_per_ck, | ||
885 | .clksel = dpll_per_m2_div, | ||
886 | .clksel_reg = OMAP4430_CM_DIV_M6_DPLL_PER, | ||
887 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK, | ||
888 | .ops = &clkops_null, | ||
889 | .recalc = &omap2_clksel_recalc, | ||
890 | .round_rate = &omap2_clksel_round_rate, | ||
891 | .set_rate = &omap2_clksel_set_rate, | ||
892 | .flags = CLOCK_IN_OMAP4430, | ||
893 | }; | ||
894 | |||
895 | static struct clk dpll_per_m7_ck = { | ||
896 | .name = "dpll_per_m7_ck", | ||
897 | .parent = &dpll_per_ck, | ||
898 | .clksel = dpll_per_m2_div, | ||
899 | .clksel_reg = OMAP4430_CM_DIV_M7_DPLL_PER, | ||
900 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK, | ||
901 | .ops = &clkops_null, | ||
902 | .recalc = &omap2_clksel_recalc, | ||
903 | .round_rate = &omap2_clksel_round_rate, | ||
904 | .set_rate = &omap2_clksel_set_rate, | ||
905 | .flags = CLOCK_IN_OMAP4430, | ||
906 | }; | ||
907 | |||
908 | /* DPLL_UNIPRO */ | ||
909 | static struct dpll_data dpll_unipro_dd = { | ||
910 | .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_UNIPRO, | ||
911 | .clk_bypass = &dpll_sys_ref_clk, | ||
912 | .clk_ref = &dpll_sys_ref_clk, | ||
913 | .control_reg = OMAP4430_CM_CLKMODE_DPLL_UNIPRO, | ||
914 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), | ||
915 | .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO, | ||
916 | .idlest_reg = OMAP4430_CM_IDLEST_DPLL_UNIPRO, | ||
917 | .mult_mask = OMAP4430_DPLL_MULT_MASK, | ||
918 | .div1_mask = OMAP4430_DPLL_DIV_MASK, | ||
919 | .enable_mask = OMAP4430_DPLL_EN_MASK, | ||
920 | .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, | ||
921 | .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, | ||
922 | .max_multiplier = OMAP4430_MAX_DPLL_MULT, | ||
923 | .max_divider = OMAP4430_MAX_DPLL_DIV, | ||
924 | .min_divider = 1, | ||
925 | }; | ||
926 | |||
927 | |||
928 | static struct clk dpll_unipro_ck = { | ||
929 | .name = "dpll_unipro_ck", | ||
930 | .parent = &dpll_sys_ref_clk, | ||
931 | .dpll_data = &dpll_unipro_dd, | ||
932 | .init = &omap2_init_dpll_parent, | ||
933 | .ops = &clkops_noncore_dpll_ops, | ||
934 | .recalc = &omap3_dpll_recalc, | ||
935 | .round_rate = &omap2_dpll_round_rate, | ||
936 | .set_rate = &omap3_noncore_dpll_set_rate, | ||
937 | .flags = CLOCK_IN_OMAP4430, | ||
938 | }; | ||
939 | |||
940 | static const struct clksel dpll_unipro_m2x2_div[] = { | ||
941 | { .parent = &dpll_unipro_ck, .rates = div31_1to31_rates }, | ||
942 | { .parent = NULL }, | ||
943 | }; | ||
944 | |||
945 | static struct clk dpll_unipro_m2x2_ck = { | ||
946 | .name = "dpll_unipro_m2x2_ck", | ||
947 | .parent = &dpll_unipro_ck, | ||
948 | .clksel = dpll_unipro_m2x2_div, | ||
949 | .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_UNIPRO, | ||
950 | .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, | ||
951 | .ops = &clkops_null, | ||
952 | .recalc = &omap2_clksel_recalc, | ||
953 | .round_rate = &omap2_clksel_round_rate, | ||
954 | .set_rate = &omap2_clksel_set_rate, | ||
955 | .flags = CLOCK_IN_OMAP4430, | ||
956 | }; | ||
957 | |||
958 | static struct clk usb_hs_clk_div_ck = { | ||
959 | .name = "usb_hs_clk_div_ck", | ||
960 | .parent = &dpll_abe_m3_ck, | ||
961 | .ops = &clkops_null, | ||
962 | .recalc = &followparent_recalc, | ||
963 | .flags = CLOCK_IN_OMAP4430, | ||
964 | }; | ||
965 | |||
966 | /* DPLL_USB */ | ||
967 | static struct dpll_data dpll_usb_dd = { | ||
968 | .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_USB, | ||
969 | .clk_bypass = &usb_hs_clk_div_ck, | ||
970 | .clk_ref = &dpll_sys_ref_clk, | ||
971 | .control_reg = OMAP4430_CM_CLKMODE_DPLL_USB, | ||
972 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), | ||
973 | .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_USB, | ||
974 | .idlest_reg = OMAP4430_CM_IDLEST_DPLL_USB, | ||
975 | .mult_mask = OMAP4430_DPLL_MULT_MASK, | ||
976 | .div1_mask = OMAP4430_DPLL_DIV_MASK, | ||
977 | .enable_mask = OMAP4430_DPLL_EN_MASK, | ||
978 | .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, | ||
979 | .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, | ||
980 | .max_multiplier = OMAP4430_MAX_DPLL_MULT, | ||
981 | .max_divider = OMAP4430_MAX_DPLL_DIV, | ||
982 | .min_divider = 1, | ||
983 | }; | ||
984 | |||
985 | |||
986 | static struct clk dpll_usb_ck = { | ||
987 | .name = "dpll_usb_ck", | ||
988 | .parent = &dpll_sys_ref_clk, | ||
989 | .dpll_data = &dpll_usb_dd, | ||
990 | .init = &omap2_init_dpll_parent, | ||
991 | .ops = &clkops_noncore_dpll_ops, | ||
992 | .recalc = &omap3_dpll_recalc, | ||
993 | .round_rate = &omap2_dpll_round_rate, | ||
994 | .set_rate = &omap3_noncore_dpll_set_rate, | ||
995 | .flags = CLOCK_IN_OMAP4430, | ||
996 | }; | ||
997 | |||
998 | static struct clk dpll_usb_clkdcoldo_ck = { | ||
999 | .name = "dpll_usb_clkdcoldo_ck", | ||
1000 | .parent = &dpll_usb_ck, | ||
1001 | .ops = &clkops_null, | ||
1002 | .recalc = &followparent_recalc, | ||
1003 | .flags = CLOCK_IN_OMAP4430, | ||
1004 | }; | ||
1005 | |||
1006 | static const struct clksel dpll_usb_m2_div[] = { | ||
1007 | { .parent = &dpll_usb_ck, .rates = div31_1to31_rates }, | ||
1008 | { .parent = NULL }, | ||
1009 | }; | ||
1010 | |||
1011 | static struct clk dpll_usb_m2_ck = { | ||
1012 | .name = "dpll_usb_m2_ck", | ||
1013 | .parent = &dpll_usb_ck, | ||
1014 | .clksel = dpll_usb_m2_div, | ||
1015 | .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_USB, | ||
1016 | .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK, | ||
1017 | .ops = &clkops_null, | ||
1018 | .recalc = &omap2_clksel_recalc, | ||
1019 | .round_rate = &omap2_clksel_round_rate, | ||
1020 | .set_rate = &omap2_clksel_set_rate, | ||
1021 | .flags = CLOCK_IN_OMAP4430, | ||
1022 | }; | ||
1023 | |||
1024 | static const struct clksel ducati_clk_mux_sel[] = { | ||
1025 | { .parent = &div_core_ck, .rates = div_1_0_rates }, | ||
1026 | { .parent = &dpll_per_m6_ck, .rates = div_1_1_rates }, | ||
1027 | { .parent = NULL }, | ||
1028 | }; | ||
1029 | |||
1030 | static struct clk ducati_clk_mux_ck = { | ||
1031 | .name = "ducati_clk_mux_ck", | ||
1032 | .parent = &div_core_ck, | ||
1033 | .clksel = ducati_clk_mux_sel, | ||
1034 | .init = &omap2_init_clksel_parent, | ||
1035 | .clksel_reg = OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT, | ||
1036 | .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, | ||
1037 | .ops = &clkops_null, | ||
1038 | .recalc = &omap2_clksel_recalc, | ||
1039 | .flags = CLOCK_IN_OMAP4430, | ||
1040 | }; | ||
1041 | |||
1042 | static struct clk func_12m_fclk = { | ||
1043 | .name = "func_12m_fclk", | ||
1044 | .parent = &dpll_per_m2x2_ck, | ||
1045 | .ops = &clkops_null, | ||
1046 | .recalc = &followparent_recalc, | ||
1047 | .flags = CLOCK_IN_OMAP4430, | ||
1048 | }; | ||
1049 | |||
1050 | static struct clk func_24m_clk = { | ||
1051 | .name = "func_24m_clk", | ||
1052 | .parent = &dpll_per_m2_ck, | ||
1053 | .ops = &clkops_null, | ||
1054 | .recalc = &followparent_recalc, | ||
1055 | .flags = CLOCK_IN_OMAP4430, | ||
1056 | }; | ||
1057 | |||
1058 | static struct clk func_24mc_fclk = { | ||
1059 | .name = "func_24mc_fclk", | ||
1060 | .parent = &dpll_per_m2x2_ck, | ||
1061 | .ops = &clkops_null, | ||
1062 | .recalc = &followparent_recalc, | ||
1063 | .flags = CLOCK_IN_OMAP4430, | ||
1064 | }; | ||
1065 | |||
1066 | static const struct clksel_rate div2_4to8_rates[] = { | ||
1067 | { .div = 4, .val = 0, .flags = RATE_IN_4430 }, | ||
1068 | { .div = 8, .val = 1, .flags = RATE_IN_4430 }, | ||
1069 | { .div = 0 }, | ||
1070 | }; | ||
1071 | |||
1072 | static const struct clksel func_48m_fclk_div[] = { | ||
1073 | { .parent = &dpll_per_m2x2_ck, .rates = div2_4to8_rates }, | ||
1074 | { .parent = NULL }, | ||
1075 | }; | ||
1076 | |||
1077 | static struct clk func_48m_fclk = { | ||
1078 | .name = "func_48m_fclk", | ||
1079 | .parent = &dpll_per_m2x2_ck, | ||
1080 | .clksel = func_48m_fclk_div, | ||
1081 | .clksel_reg = OMAP4430_CM_SCALE_FCLK, | ||
1082 | .clksel_mask = OMAP4430_SCALE_FCLK_MASK, | ||
1083 | .ops = &clkops_null, | ||
1084 | .recalc = &omap2_clksel_recalc, | ||
1085 | .round_rate = &omap2_clksel_round_rate, | ||
1086 | .set_rate = &omap2_clksel_set_rate, | ||
1087 | .flags = CLOCK_IN_OMAP4430, | ||
1088 | }; | ||
1089 | |||
1090 | static struct clk func_48mc_fclk = { | ||
1091 | .name = "func_48mc_fclk", | ||
1092 | .parent = &dpll_per_m2x2_ck, | ||
1093 | .ops = &clkops_null, | ||
1094 | .recalc = &followparent_recalc, | ||
1095 | .flags = CLOCK_IN_OMAP4430, | ||
1096 | }; | ||
1097 | |||
1098 | static const struct clksel_rate div2_2to4_rates[] = { | ||
1099 | { .div = 2, .val = 0, .flags = RATE_IN_4430 }, | ||
1100 | { .div = 4, .val = 1, .flags = RATE_IN_4430 }, | ||
1101 | { .div = 0 }, | ||
1102 | }; | ||
1103 | |||
1104 | static const struct clksel func_64m_fclk_div[] = { | ||
1105 | { .parent = &dpll_per_m4_ck, .rates = div2_2to4_rates }, | ||
1106 | { .parent = NULL }, | ||
1107 | }; | ||
1108 | |||
1109 | static struct clk func_64m_fclk = { | ||
1110 | .name = "func_64m_fclk", | ||
1111 | .parent = &dpll_per_m4_ck, | ||
1112 | .clksel = func_64m_fclk_div, | ||
1113 | .clksel_reg = OMAP4430_CM_SCALE_FCLK, | ||
1114 | .clksel_mask = OMAP4430_SCALE_FCLK_MASK, | ||
1115 | .ops = &clkops_null, | ||
1116 | .recalc = &omap2_clksel_recalc, | ||
1117 | .round_rate = &omap2_clksel_round_rate, | ||
1118 | .set_rate = &omap2_clksel_set_rate, | ||
1119 | .flags = CLOCK_IN_OMAP4430, | ||
1120 | }; | ||
1121 | |||
1122 | static const struct clksel func_96m_fclk_div[] = { | ||
1123 | { .parent = &dpll_per_m2x2_ck, .rates = div2_2to4_rates }, | ||
1124 | { .parent = NULL }, | ||
1125 | }; | ||
1126 | |||
1127 | static struct clk func_96m_fclk = { | ||
1128 | .name = "func_96m_fclk", | ||
1129 | .parent = &dpll_per_m2x2_ck, | ||
1130 | .clksel = func_96m_fclk_div, | ||
1131 | .clksel_reg = OMAP4430_CM_SCALE_FCLK, | ||
1132 | .clksel_mask = OMAP4430_SCALE_FCLK_MASK, | ||
1133 | .ops = &clkops_null, | ||
1134 | .recalc = &omap2_clksel_recalc, | ||
1135 | .round_rate = &omap2_clksel_round_rate, | ||
1136 | .set_rate = &omap2_clksel_set_rate, | ||
1137 | .flags = CLOCK_IN_OMAP4430, | ||
1138 | }; | ||
1139 | |||
1140 | static const struct clksel hsmmc6_fclk_sel[] = { | ||
1141 | { .parent = &func_64m_fclk, .rates = div_1_0_rates }, | ||
1142 | { .parent = &func_96m_fclk, .rates = div_1_1_rates }, | ||
1143 | { .parent = NULL }, | ||
1144 | }; | ||
1145 | |||
1146 | static struct clk hsmmc6_fclk = { | ||
1147 | .name = "hsmmc6_fclk", | ||
1148 | .parent = &func_64m_fclk, | ||
1149 | .ops = &clkops_null, | ||
1150 | .recalc = &followparent_recalc, | ||
1151 | .flags = CLOCK_IN_OMAP4430, | ||
1152 | }; | ||
1153 | |||
1154 | static const struct clksel_rate div2_1to8_rates[] = { | ||
1155 | { .div = 1, .val = 0, .flags = RATE_IN_4430 }, | ||
1156 | { .div = 8, .val = 1, .flags = RATE_IN_4430 }, | ||
1157 | { .div = 0 }, | ||
1158 | }; | ||
1159 | |||
1160 | static const struct clksel init_60m_fclk_div[] = { | ||
1161 | { .parent = &dpll_usb_m2_ck, .rates = div2_1to8_rates }, | ||
1162 | { .parent = NULL }, | ||
1163 | }; | ||
1164 | |||
1165 | static struct clk init_60m_fclk = { | ||
1166 | .name = "init_60m_fclk", | ||
1167 | .parent = &dpll_usb_m2_ck, | ||
1168 | .clksel = init_60m_fclk_div, | ||
1169 | .clksel_reg = OMAP4430_CM_CLKSEL_USB_60MHZ, | ||
1170 | .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, | ||
1171 | .ops = &clkops_null, | ||
1172 | .recalc = &omap2_clksel_recalc, | ||
1173 | .round_rate = &omap2_clksel_round_rate, | ||
1174 | .set_rate = &omap2_clksel_set_rate, | ||
1175 | .flags = CLOCK_IN_OMAP4430, | ||
1176 | }; | ||
1177 | |||
1178 | static const struct clksel l3_div_div[] = { | ||
1179 | { .parent = &div_core_ck, .rates = div2_1to2_rates }, | ||
1180 | { .parent = NULL }, | ||
1181 | }; | ||
1182 | |||
1183 | static struct clk l3_div_ck = { | ||
1184 | .name = "l3_div_ck", | ||
1185 | .parent = &div_core_ck, | ||
1186 | .clksel = l3_div_div, | ||
1187 | .clksel_reg = OMAP4430_CM_CLKSEL_CORE, | ||
1188 | .clksel_mask = OMAP4430_CLKSEL_L3_MASK, | ||
1189 | .ops = &clkops_null, | ||
1190 | .recalc = &omap2_clksel_recalc, | ||
1191 | .round_rate = &omap2_clksel_round_rate, | ||
1192 | .set_rate = &omap2_clksel_set_rate, | ||
1193 | .flags = CLOCK_IN_OMAP4430, | ||
1194 | }; | ||
1195 | |||
1196 | static const struct clksel l4_div_div[] = { | ||
1197 | { .parent = &l3_div_ck, .rates = div2_1to2_rates }, | ||
1198 | { .parent = NULL }, | ||
1199 | }; | ||
1200 | |||
1201 | static struct clk l4_div_ck = { | ||
1202 | .name = "l4_div_ck", | ||
1203 | .parent = &l3_div_ck, | ||
1204 | .clksel = l4_div_div, | ||
1205 | .clksel_reg = OMAP4430_CM_CLKSEL_CORE, | ||
1206 | .clksel_mask = OMAP4430_CLKSEL_L4_MASK, | ||
1207 | .ops = &clkops_null, | ||
1208 | .recalc = &omap2_clksel_recalc, | ||
1209 | .round_rate = &omap2_clksel_round_rate, | ||
1210 | .set_rate = &omap2_clksel_set_rate, | ||
1211 | .flags = CLOCK_IN_OMAP4430, | ||
1212 | }; | ||
1213 | |||
1214 | static struct clk lp_clk_div_ck = { | ||
1215 | .name = "lp_clk_div_ck", | ||
1216 | .parent = &dpll_abe_m2x2_ck, | ||
1217 | .ops = &clkops_null, | ||
1218 | .recalc = &followparent_recalc, | ||
1219 | .flags = CLOCK_IN_OMAP4430, | ||
1220 | }; | ||
1221 | |||
1222 | static const struct clksel l4_wkup_clk_mux_sel[] = { | ||
1223 | { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, | ||
1224 | { .parent = &lp_clk_div_ck, .rates = div_1_1_rates }, | ||
1225 | { .parent = NULL }, | ||
1226 | }; | ||
1227 | |||
1228 | static struct clk l4_wkup_clk_mux_ck = { | ||
1229 | .name = "l4_wkup_clk_mux_ck", | ||
1230 | .parent = &sys_clkin_ck, | ||
1231 | .clksel = l4_wkup_clk_mux_sel, | ||
1232 | .init = &omap2_init_clksel_parent, | ||
1233 | .clksel_reg = OMAP4430_CM_L4_WKUP_CLKSEL, | ||
1234 | .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, | ||
1235 | .ops = &clkops_null, | ||
1236 | .recalc = &omap2_clksel_recalc, | ||
1237 | .flags = CLOCK_IN_OMAP4430, | ||
1238 | }; | ||
1239 | |||
1240 | static const struct clksel per_abe_nc_fclk_div[] = { | ||
1241 | { .parent = &dpll_abe_m2_ck, .rates = div2_1to2_rates }, | ||
1242 | { .parent = NULL }, | ||
1243 | }; | ||
1244 | |||
1245 | static struct clk per_abe_nc_fclk = { | ||
1246 | .name = "per_abe_nc_fclk", | ||
1247 | .parent = &dpll_abe_m2_ck, | ||
1248 | .clksel = per_abe_nc_fclk_div, | ||
1249 | .clksel_reg = OMAP4430_CM_SCALE_FCLK, | ||
1250 | .clksel_mask = OMAP4430_SCALE_FCLK_MASK, | ||
1251 | .ops = &clkops_null, | ||
1252 | .recalc = &omap2_clksel_recalc, | ||
1253 | .round_rate = &omap2_clksel_round_rate, | ||
1254 | .set_rate = &omap2_clksel_set_rate, | ||
1255 | .flags = CLOCK_IN_OMAP4430, | ||
1256 | }; | ||
1257 | |||
1258 | static const struct clksel mcasp2_fclk_sel[] = { | ||
1259 | { .parent = &func_96m_fclk, .rates = div_1_0_rates }, | ||
1260 | { .parent = &per_abe_nc_fclk, .rates = div_1_1_rates }, | ||
1261 | { .parent = NULL }, | ||
1262 | }; | ||
1263 | |||
1264 | static struct clk mcasp2_fclk = { | ||
1265 | .name = "mcasp2_fclk", | ||
1266 | .parent = &func_96m_fclk, | ||
1267 | .ops = &clkops_null, | ||
1268 | .recalc = &followparent_recalc, | ||
1269 | .flags = CLOCK_IN_OMAP4430, | ||
1270 | }; | ||
1271 | |||
1272 | static struct clk mcasp3_fclk = { | ||
1273 | .name = "mcasp3_fclk", | ||
1274 | .parent = &func_96m_fclk, | ||
1275 | .ops = &clkops_null, | ||
1276 | .recalc = &followparent_recalc, | ||
1277 | .flags = CLOCK_IN_OMAP4430, | ||
1278 | }; | ||
1279 | |||
1280 | static struct clk ocp_abe_iclk = { | ||
1281 | .name = "ocp_abe_iclk", | ||
1282 | .parent = &aess_fclk, | ||
1283 | .ops = &clkops_null, | ||
1284 | .recalc = &followparent_recalc, | ||
1285 | .flags = CLOCK_IN_OMAP4430, | ||
1286 | }; | ||
1287 | |||
1288 | static struct clk per_abe_24m_fclk = { | ||
1289 | .name = "per_abe_24m_fclk", | ||
1290 | .parent = &dpll_abe_m2_ck, | ||
1291 | .ops = &clkops_null, | ||
1292 | .recalc = &followparent_recalc, | ||
1293 | .flags = CLOCK_IN_OMAP4430, | ||
1294 | }; | ||
1295 | |||
1296 | static const struct clksel pmd_stm_clock_mux_sel[] = { | ||
1297 | { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, | ||
1298 | { .parent = &dpll_core_m6_ck, .rates = div_1_1_rates }, | ||
1299 | { .parent = &dpll_per_m7_ck, .rates = div_1_2_rates }, | ||
1300 | { .parent = NULL }, | ||
1301 | }; | ||
1302 | |||
1303 | static struct clk pmd_stm_clock_mux_ck = { | ||
1304 | .name = "pmd_stm_clock_mux_ck", | ||
1305 | .parent = &sys_clkin_ck, | ||
1306 | .ops = &clkops_null, | ||
1307 | .recalc = &followparent_recalc, | ||
1308 | .flags = CLOCK_IN_OMAP4430, | ||
1309 | }; | ||
1310 | |||
1311 | static struct clk pmd_trace_clk_mux_ck = { | ||
1312 | .name = "pmd_trace_clk_mux_ck", | ||
1313 | .parent = &sys_clkin_ck, | ||
1314 | .ops = &clkops_null, | ||
1315 | .recalc = &followparent_recalc, | ||
1316 | .flags = CLOCK_IN_OMAP4430, | ||
1317 | }; | ||
1318 | |||
1319 | static struct clk syc_clk_div_ck = { | ||
1320 | .name = "syc_clk_div_ck", | ||
1321 | .parent = &sys_clkin_ck, | ||
1322 | .clksel = dpll_sys_ref_clk_div, | ||
1323 | .clksel_reg = OMAP4430_CM_ABE_DSS_SYS_CLKSEL, | ||
1324 | .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, | ||
1325 | .ops = &clkops_null, | ||
1326 | .recalc = &omap2_clksel_recalc, | ||
1327 | .round_rate = &omap2_clksel_round_rate, | ||
1328 | .set_rate = &omap2_clksel_set_rate, | ||
1329 | .flags = CLOCK_IN_OMAP4430, | ||
1330 | }; | ||
1331 | |||
1332 | /* Leaf clocks controlled by modules */ | ||
1333 | |||
1334 | static struct clk aes1_ck = { | ||
1335 | .name = "aes1_ck", | ||
1336 | .ops = &clkops_omap2_dflt, | ||
1337 | .enable_reg = OMAP4430_CM_L4SEC_AES1_CLKCTRL, | ||
1338 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | ||
1339 | .clkdm_name = "l4_secure_clkdm", | ||
1340 | .parent = &l3_div_ck, | ||
1341 | .recalc = &followparent_recalc, | ||
1342 | }; | ||
1343 | |||
1344 | static struct clk aes2_ck = { | ||
1345 | .name = "aes2_ck", | ||
1346 | .ops = &clkops_omap2_dflt, | ||
1347 | .enable_reg = OMAP4430_CM_L4SEC_AES2_CLKCTRL, | ||
1348 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | ||
1349 | .clkdm_name = "l4_secure_clkdm", | ||
1350 | .parent = &l3_div_ck, | ||
1351 | .recalc = &followparent_recalc, | ||
1352 | }; | ||
1353 | |||
1354 | static struct clk aess_ck = { | ||
1355 | .name = "aess_ck", | ||
1356 | .ops = &clkops_omap2_dflt, | ||
1357 | .enable_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL, | ||
1358 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | ||
1359 | .clkdm_name = "abe_clkdm", | ||
1360 | .parent = &aess_fclk, | ||
1361 | .recalc = &followparent_recalc, | ||
1362 | }; | ||
1363 | |||
1364 | static struct clk cust_efuse_ck = { | ||
1365 | .name = "cust_efuse_ck", | ||
1366 | .ops = &clkops_omap2_dflt, | ||
1367 | .enable_reg = OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL, | ||
1368 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | ||
1369 | .clkdm_name = "l4_cefuse_clkdm", | ||
1370 | .parent = &sys_clkin_ck, | ||
1371 | .recalc = &followparent_recalc, | ||
1372 | }; | ||
1373 | |||
1374 | static struct clk des3des_ck = { | ||
1375 | .name = "des3des_ck", | ||
1376 | .ops = &clkops_omap2_dflt, | ||
1377 | .enable_reg = OMAP4430_CM_L4SEC_DES3DES_CLKCTRL, | ||
1378 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | ||
1379 | .clkdm_name = "l4_secure_clkdm", | ||
1380 | .parent = &l4_div_ck, | ||
1381 | .recalc = &followparent_recalc, | ||
1382 | }; | ||
1383 | |||
1384 | static const struct clksel dmic_sync_mux_sel[] = { | ||
1385 | { .parent = &abe_24m_fclk, .rates = div_1_0_rates }, | ||
1386 | { .parent = &syc_clk_div_ck, .rates = div_1_1_rates }, | ||
1387 | { .parent = &func_24m_clk, .rates = div_1_2_rates }, | ||
1388 | { .parent = NULL }, | ||
1389 | }; | ||
1390 | |||
1391 | static struct clk dmic_sync_mux_ck = { | ||
1392 | .name = "dmic_sync_mux_ck", | ||
1393 | .parent = &abe_24m_fclk, | ||
1394 | .clksel = dmic_sync_mux_sel, | ||
1395 | .init = &omap2_init_clksel_parent, | ||
1396 | .clksel_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL, | ||
1397 | .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, | ||
1398 | .ops = &clkops_null, | ||
1399 | .recalc = &omap2_clksel_recalc, | ||
1400 | .flags = CLOCK_IN_OMAP4430, | ||
1401 | }; | ||
1402 | |||
1403 | static const struct clksel func_dmic_abe_gfclk_sel[] = { | ||
1404 | { .parent = &dmic_sync_mux_ck, .rates = div_1_0_rates }, | ||
1405 | { .parent = &pad_clks_ck, .rates = div_1_1_rates }, | ||
1406 | { .parent = &slimbus_clk, .rates = div_1_2_rates }, | ||
1407 | { .parent = NULL }, | ||
1408 | }; | ||
1409 | |||
1410 | /* Merged func_dmic_abe_gfclk into dmic_ck */ | ||
1411 | static struct clk dmic_ck = { | ||
1412 | .name = "dmic_ck", | ||
1413 | .parent = &dmic_sync_mux_ck, | ||
1414 | .clksel = func_dmic_abe_gfclk_sel, | ||
1415 | .init = &omap2_init_clksel_parent, | ||
1416 | .clksel_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL, | ||
1417 | .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, | ||
1418 | .ops = &clkops_omap2_dflt, | ||
1419 | .recalc = &omap2_clksel_recalc, | ||
1420 | .flags = CLOCK_IN_OMAP4430, | ||
1421 | .enable_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL, | ||
1422 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | ||
1423 | .clkdm_name = "abe_clkdm", | ||
1424 | }; | ||
1425 | |||
1426 | static struct clk dss_ck = { | ||
1427 | .name = "dss_ck", | ||
1428 | .ops = &clkops_omap2_dflt, | ||
1429 | .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, | ||
1430 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | ||
1431 | .clkdm_name = "l3_dss_clkdm", | ||
1432 | .parent = &l3_div_ck, | ||
1433 | .recalc = &followparent_recalc, | ||
1434 | }; | ||
1435 | |||
1436 | static struct clk ducati_ck = { | ||
1437 | .name = "ducati_ck", | ||
1438 | .ops = &clkops_omap2_dflt, | ||
1439 | .enable_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL, | ||
1440 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | ||
1441 | .clkdm_name = "ducati_clkdm", | ||
1442 | .parent = &ducati_clk_mux_ck, | ||
1443 | .recalc = &followparent_recalc, | ||
1444 | }; | ||
1445 | |||
1446 | static struct clk emif1_ck = { | ||
1447 | .name = "emif1_ck", | ||
1448 | .ops = &clkops_omap2_dflt, | ||
1449 | .enable_reg = OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL, | ||
1450 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | ||
1451 | .clkdm_name = "l3_emif_clkdm", | ||
1452 | .parent = &ddrphy_ck, | ||
1453 | .recalc = &followparent_recalc, | ||
1454 | }; | ||
1455 | |||
1456 | static struct clk emif2_ck = { | ||
1457 | .name = "emif2_ck", | ||
1458 | .ops = &clkops_omap2_dflt, | ||
1459 | .enable_reg = OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL, | ||
1460 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | ||
1461 | .clkdm_name = "l3_emif_clkdm", | ||
1462 | .parent = &ddrphy_ck, | ||
1463 | .recalc = &followparent_recalc, | ||
1464 | }; | ||
1465 | |||
1466 | static const struct clksel fdif_fclk_div[] = { | ||
1467 | { .parent = &dpll_per_m4_ck, .rates = div3_1to4_rates }, | ||
1468 | { .parent = NULL }, | ||
1469 | }; | ||
1470 | |||
1471 | /* Merged fdif_fclk into fdif_ck */ | ||
1472 | static struct clk fdif_ck = { | ||
1473 | .name = "fdif_ck", | ||
1474 | .parent = &dpll_per_m4_ck, | ||
1475 | .clksel = fdif_fclk_div, | ||
1476 | .clksel_reg = OMAP4430_CM_CAM_FDIF_CLKCTRL, | ||
1477 | .clksel_mask = OMAP4430_CLKSEL_FCLK_MASK, | ||
1478 | .ops = &clkops_omap2_dflt, | ||
1479 | .recalc = &omap2_clksel_recalc, | ||
1480 | .round_rate = &omap2_clksel_round_rate, | ||
1481 | .set_rate = &omap2_clksel_set_rate, | ||
1482 | .flags = CLOCK_IN_OMAP4430, | ||
1483 | .enable_reg = OMAP4430_CM_CAM_FDIF_CLKCTRL, | ||
1484 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | ||
1485 | .clkdm_name = "iss_clkdm", | ||
1486 | }; | ||
1487 | |||
1488 | static const struct clksel per_sgx_fclk_div[] = { | ||
1489 | { .parent = &dpll_per_m2x2_ck, .rates = div3_1to4_rates }, | ||
1490 | { .parent = NULL }, | ||
1491 | }; | ||
1492 | |||
1493 | static struct clk per_sgx_fclk = { | ||
1494 | .name = "per_sgx_fclk", | ||
1495 | .parent = &dpll_per_m2x2_ck, | ||
1496 | .clksel = per_sgx_fclk_div, | ||
1497 | .clksel_reg = OMAP4430_CM_GFX_GFX_CLKCTRL, | ||
1498 | .clksel_mask = OMAP4430_CLKSEL_PER_192M_MASK, | ||
1499 | .ops = &clkops_null, | ||
1500 | .recalc = &omap2_clksel_recalc, | ||
1501 | .round_rate = &omap2_clksel_round_rate, | ||
1502 | .set_rate = &omap2_clksel_set_rate, | ||
1503 | .flags = CLOCK_IN_OMAP4430, | ||
1504 | }; | ||
1505 | |||
1506 | static const struct clksel sgx_clk_mux_sel[] = { | ||
1507 | { .parent = &dpll_core_m7_ck, .rates = div_1_0_rates }, | ||
1508 | { .parent = &per_sgx_fclk, .rates = div_1_1_rates }, | ||
1509 | { .parent = NULL }, | ||
1510 | }; | ||
1511 | |||
1512 | /* Merged sgx_clk_mux into gfx_ck */ | ||
1513 | static struct clk gfx_ck = { | ||
1514 | .name = "gfx_ck", | ||
1515 | .parent = &dpll_core_m7_ck, | ||
1516 | .clksel = sgx_clk_mux_sel, | ||
1517 | .init = &omap2_init_clksel_parent, | ||
1518 | .clksel_reg = OMAP4430_CM_GFX_GFX_CLKCTRL, | ||
1519 | .clksel_mask = OMAP4430_CLKSEL_SGX_FCLK_MASK, | ||
1520 | .ops = &clkops_omap2_dflt, | ||
1521 | .recalc = &omap2_clksel_recalc, | ||
1522 | .flags = CLOCK_IN_OMAP4430, | ||
1523 | .enable_reg = OMAP4430_CM_GFX_GFX_CLKCTRL, | ||
1524 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | ||
1525 | .clkdm_name = "l3_gfx_clkdm", | ||
1526 | }; | ||
1527 | |||
1528 | static struct clk gpio1_ck = { | ||
1529 | .name = "gpio1_ck", | ||
1530 | .ops = &clkops_omap2_dflt, | ||
1531 | .enable_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL, | ||
1532 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | ||
1533 | .clkdm_name = "l4_wkup_clkdm", | ||
1534 | .parent = &l4_wkup_clk_mux_ck, | ||
1535 | .recalc = &followparent_recalc, | ||
1536 | }; | ||
1537 | |||
1538 | static struct clk gpio2_ck = { | ||
1539 | .name = "gpio2_ck", | ||
1540 | .ops = &clkops_omap2_dflt, | ||
1541 | .enable_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL, | ||
1542 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | ||
1543 | .clkdm_name = "l4_per_clkdm", | ||
1544 | .parent = &l4_div_ck, | ||
1545 | .recalc = &followparent_recalc, | ||
1546 | }; | ||
1547 | |||
1548 | static struct clk gpio3_ck = { | ||
1549 | .name = "gpio3_ck", | ||
1550 | .ops = &clkops_omap2_dflt, | ||
1551 | .enable_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL, | ||
1552 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | ||
1553 | .clkdm_name = "l4_per_clkdm", | ||
1554 | .parent = &l4_div_ck, | ||
1555 | .recalc = &followparent_recalc, | ||
1556 | }; | ||
1557 | |||
1558 | static struct clk gpio4_ck = { | ||
1559 | .name = "gpio4_ck", | ||
1560 | .ops = &clkops_omap2_dflt, | ||
1561 | .enable_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL, | ||
1562 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | ||
1563 | .clkdm_name = "l4_per_clkdm", | ||
1564 | .parent = &l4_div_ck, | ||
1565 | .recalc = &followparent_recalc, | ||
1566 | }; | ||
1567 | |||
1568 | static struct clk gpio5_ck = { | ||
1569 | .name = "gpio5_ck", | ||
1570 | .ops = &clkops_omap2_dflt, | ||
1571 | .enable_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL, | ||
1572 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | ||
1573 | .clkdm_name = "l4_per_clkdm", | ||
1574 | .parent = &l4_div_ck, | ||
1575 | .recalc = &followparent_recalc, | ||
1576 | }; | ||
1577 | |||
1578 | static struct clk gpio6_ck = { | ||
1579 | .name = "gpio6_ck", | ||
1580 | .ops = &clkops_omap2_dflt, | ||
1581 | .enable_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL, | ||
1582 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | ||
1583 | .clkdm_name = "l4_per_clkdm", | ||
1584 | .parent = &l4_div_ck, | ||
1585 | .recalc = &followparent_recalc, | ||
1586 | }; | ||
1587 | |||
1588 | static struct clk gpmc_ck = { | ||
1589 | .name = "gpmc_ck", | ||
1590 | .ops = &clkops_omap2_dflt, | ||
1591 | .enable_reg = OMAP4430_CM_L3_2_GPMC_CLKCTRL, | ||
1592 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | ||
1593 | .clkdm_name = "l3_2_clkdm", | ||
1594 | .parent = &l3_div_ck, | ||
1595 | .recalc = &followparent_recalc, | ||
1596 | }; | ||
1597 | |||
1598 | static const struct clksel dmt1_clk_mux_sel[] = { | ||
1599 | { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, | ||
1600 | { .parent = &sys_32k_ck, .rates = div_1_1_rates }, | ||
1601 | { .parent = NULL }, | ||
1602 | }; | ||
1603 | |||
1604 | /* Merged dmt1_clk_mux into gptimer1_ck */ | ||
1605 | static struct clk gptimer1_ck = { | ||
1606 | .name = "gptimer1_ck", | ||
1607 | .parent = &sys_clkin_ck, | ||
1608 | .clksel = dmt1_clk_mux_sel, | ||
1609 | .init = &omap2_init_clksel_parent, | ||
1610 | .clksel_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL, | ||
1611 | .clksel_mask = OMAP4430_CLKSEL_MASK, | ||
1612 | .ops = &clkops_omap2_dflt, | ||
1613 | .recalc = &omap2_clksel_recalc, | ||
1614 | .flags = CLOCK_IN_OMAP4430, | ||
1615 | .enable_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL, | ||
1616 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | ||
1617 | .clkdm_name = "l4_wkup_clkdm", | ||
1618 | }; | ||
1619 | |||
1620 | /* Merged cm2_dm10_mux into gptimer10_ck */ | ||
1621 | static struct clk gptimer10_ck = { | ||
1622 | .name = "gptimer10_ck", | ||
1623 | .parent = &sys_clkin_ck, | ||
1624 | .clksel = dmt1_clk_mux_sel, | ||
1625 | .init = &omap2_init_clksel_parent, | ||
1626 | .clksel_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, | ||
1627 | .clksel_mask = OMAP4430_CLKSEL_MASK, | ||
1628 | .ops = &clkops_omap2_dflt, | ||
1629 | .recalc = &omap2_clksel_recalc, | ||
1630 | .flags = CLOCK_IN_OMAP4430, | ||
1631 | .enable_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, | ||
1632 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | ||
1633 | .clkdm_name = "l4_per_clkdm", | ||
1634 | }; | ||
1635 | |||
1636 | /* Merged cm2_dm11_mux into gptimer11_ck */ | ||
1637 | static struct clk gptimer11_ck = { | ||
1638 | .name = "gptimer11_ck", | ||
1639 | .parent = &sys_clkin_ck, | ||
1640 | .clksel = dmt1_clk_mux_sel, | ||
1641 | .init = &omap2_init_clksel_parent, | ||
1642 | .clksel_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, | ||
1643 | .clksel_mask = OMAP4430_CLKSEL_MASK, | ||
1644 | .ops = &clkops_omap2_dflt, | ||
1645 | .recalc = &omap2_clksel_recalc, | ||
1646 | .flags = CLOCK_IN_OMAP4430, | ||
1647 | .enable_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, | ||
1648 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | ||
1649 | .clkdm_name = "l4_per_clkdm", | ||
1650 | }; | ||
1651 | |||
1652 | /* Merged cm2_dm2_mux into gptimer2_ck */ | ||
1653 | static struct clk gptimer2_ck = { | ||
1654 | .name = "gptimer2_ck", | ||
1655 | .parent = &sys_clkin_ck, | ||
1656 | .clksel = dmt1_clk_mux_sel, | ||
1657 | .init = &omap2_init_clksel_parent, | ||
1658 | .clksel_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, | ||
1659 | .clksel_mask = OMAP4430_CLKSEL_MASK, | ||
1660 | .ops = &clkops_omap2_dflt, | ||
1661 | .recalc = &omap2_clksel_recalc, | ||
1662 | .flags = CLOCK_IN_OMAP4430, | ||
1663 | .enable_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, | ||
1664 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | ||
1665 | .clkdm_name = "l4_per_clkdm", | ||
1666 | }; | ||
1667 | |||
1668 | /* Merged cm2_dm3_mux into gptimer3_ck */ | ||
1669 | static struct clk gptimer3_ck = { | ||
1670 | .name = "gptimer3_ck", | ||
1671 | .parent = &sys_clkin_ck, | ||
1672 | .clksel = dmt1_clk_mux_sel, | ||
1673 | .init = &omap2_init_clksel_parent, | ||
1674 | .clksel_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, | ||
1675 | .clksel_mask = OMAP4430_CLKSEL_MASK, | ||
1676 | .ops = &clkops_omap2_dflt, | ||
1677 | .recalc = &omap2_clksel_recalc, | ||
1678 | .flags = CLOCK_IN_OMAP4430, | ||
1679 | .enable_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, | ||
1680 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | ||
1681 | .clkdm_name = "l4_per_clkdm", | ||
1682 | }; | ||
1683 | |||
1684 | /* Merged cm2_dm4_mux into gptimer4_ck */ | ||
1685 | static struct clk gptimer4_ck = { | ||
1686 | .name = "gptimer4_ck", | ||
1687 | .parent = &sys_clkin_ck, | ||
1688 | .clksel = dmt1_clk_mux_sel, | ||
1689 | .init = &omap2_init_clksel_parent, | ||
1690 | .clksel_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, | ||
1691 | .clksel_mask = OMAP4430_CLKSEL_MASK, | ||
1692 | .ops = &clkops_omap2_dflt, | ||
1693 | .recalc = &omap2_clksel_recalc, | ||
1694 | .flags = CLOCK_IN_OMAP4430, | ||
1695 | .enable_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, | ||
1696 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | ||
1697 | .clkdm_name = "l4_per_clkdm", | ||
1698 | }; | ||
1699 | |||
1700 | static const struct clksel timer5_sync_mux_sel[] = { | ||
1701 | { .parent = &syc_clk_div_ck, .rates = div_1_0_rates }, | ||
1702 | { .parent = &sys_32k_ck, .rates = div_1_1_rates }, | ||
1703 | { .parent = NULL }, | ||
1704 | }; | ||
1705 | |||
1706 | /* Merged timer5_sync_mux into gptimer5_ck */ | ||
1707 | static struct clk gptimer5_ck = { | ||
1708 | .name = "gptimer5_ck", | ||
1709 | .parent = &syc_clk_div_ck, | ||
1710 | .clksel = timer5_sync_mux_sel, | ||
1711 | .init = &omap2_init_clksel_parent, | ||
1712 | .clksel_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL, | ||
1713 | .clksel_mask = OMAP4430_CLKSEL_MASK, | ||
1714 | .ops = &clkops_omap2_dflt, | ||
1715 | .recalc = &omap2_clksel_recalc, | ||
1716 | .flags = CLOCK_IN_OMAP4430, | ||
1717 | .enable_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL, | ||
1718 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | ||
1719 | .clkdm_name = "abe_clkdm", | ||
1720 | }; | ||
1721 | |||
1722 | /* Merged timer6_sync_mux into gptimer6_ck */ | ||
1723 | static struct clk gptimer6_ck = { | ||
1724 | .name = "gptimer6_ck", | ||
1725 | .parent = &syc_clk_div_ck, | ||
1726 | .clksel = timer5_sync_mux_sel, | ||
1727 | .init = &omap2_init_clksel_parent, | ||
1728 | .clksel_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL, | ||
1729 | .clksel_mask = OMAP4430_CLKSEL_MASK, | ||
1730 | .ops = &clkops_omap2_dflt, | ||
1731 | .recalc = &omap2_clksel_recalc, | ||
1732 | .flags = CLOCK_IN_OMAP4430, | ||
1733 | .enable_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL, | ||
1734 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | ||
1735 | .clkdm_name = "abe_clkdm", | ||
1736 | }; | ||
1737 | |||
1738 | /* Merged timer7_sync_mux into gptimer7_ck */ | ||
1739 | static struct clk gptimer7_ck = { | ||
1740 | .name = "gptimer7_ck", | ||
1741 | .parent = &syc_clk_div_ck, | ||
1742 | .clksel = timer5_sync_mux_sel, | ||
1743 | .init = &omap2_init_clksel_parent, | ||
1744 | .clksel_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL, | ||
1745 | .clksel_mask = OMAP4430_CLKSEL_MASK, | ||
1746 | .ops = &clkops_omap2_dflt, | ||
1747 | .recalc = &omap2_clksel_recalc, | ||
1748 | .flags = CLOCK_IN_OMAP4430, | ||
1749 | .enable_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL, | ||
1750 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | ||
1751 | .clkdm_name = "abe_clkdm", | ||
1752 | }; | ||
1753 | |||
1754 | /* Merged timer8_sync_mux into gptimer8_ck */ | ||
1755 | static struct clk gptimer8_ck = { | ||
1756 | .name = "gptimer8_ck", | ||
1757 | .parent = &syc_clk_div_ck, | ||
1758 | .clksel = timer5_sync_mux_sel, | ||
1759 | .init = &omap2_init_clksel_parent, | ||
1760 | .clksel_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL, | ||
1761 | .clksel_mask = OMAP4430_CLKSEL_MASK, | ||
1762 | .ops = &clkops_omap2_dflt, | ||
1763 | .recalc = &omap2_clksel_recalc, | ||
1764 | .flags = CLOCK_IN_OMAP4430, | ||
1765 | .enable_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL, | ||
1766 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | ||
1767 | .clkdm_name = "abe_clkdm", | ||
1768 | }; | ||
1769 | |||
1770 | /* Merged cm2_dm9_mux into gptimer9_ck */ | ||
1771 | static struct clk gptimer9_ck = { | ||
1772 | .name = "gptimer9_ck", | ||
1773 | .parent = &sys_clkin_ck, | ||
1774 | .clksel = dmt1_clk_mux_sel, | ||
1775 | .init = &omap2_init_clksel_parent, | ||
1776 | .clksel_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, | ||
1777 | .clksel_mask = OMAP4430_CLKSEL_MASK, | ||
1778 | .ops = &clkops_omap2_dflt, | ||
1779 | .recalc = &omap2_clksel_recalc, | ||
1780 | .flags = CLOCK_IN_OMAP4430, | ||
1781 | .enable_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, | ||
1782 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | ||
1783 | .clkdm_name = "l4_per_clkdm", | ||
1784 | }; | ||
1785 | |||
1786 | static struct clk hdq1w_ck = { | ||
1787 | .name = "hdq1w_ck", | ||
1788 | .ops = &clkops_omap2_dflt, | ||
1789 | .enable_reg = OMAP4430_CM_L4PER_HDQ1W_CLKCTRL, | ||
1790 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | ||
1791 | .clkdm_name = "l4_per_clkdm", | ||
1792 | .parent = &func_12m_fclk, | ||
1793 | .recalc = &followparent_recalc, | ||
1794 | }; | ||
1795 | |||
1796 | /* Merged hsi_fclk into hsi_ck */ | ||
1797 | static struct clk hsi_ck = { | ||
1798 | .name = "hsi_ck", | ||
1799 | .parent = &dpll_per_m2x2_ck, | ||
1800 | .clksel = per_sgx_fclk_div, | ||
1801 | .clksel_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL, | ||
1802 | .clksel_mask = OMAP4430_CLKSEL_24_25_MASK, | ||
1803 | .ops = &clkops_omap2_dflt, | ||
1804 | .recalc = &omap2_clksel_recalc, | ||
1805 | .round_rate = &omap2_clksel_round_rate, | ||
1806 | .set_rate = &omap2_clksel_set_rate, | ||
1807 | .flags = CLOCK_IN_OMAP4430, | ||
1808 | .enable_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL, | ||
1809 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | ||
1810 | .clkdm_name = "l3_init_clkdm", | ||
1811 | }; | ||
1812 | |||
1813 | static struct clk i2c1_ck = { | ||
1814 | .name = "i2c1_ck", | ||
1815 | .ops = &clkops_omap2_dflt, | ||
1816 | .enable_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL, | ||
1817 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | ||
1818 | .clkdm_name = "l4_per_clkdm", | ||
1819 | .parent = &func_96m_fclk, | ||
1820 | .recalc = &followparent_recalc, | ||
1821 | }; | ||
1822 | |||
1823 | static struct clk i2c2_ck = { | ||
1824 | .name = "i2c2_ck", | ||
1825 | .ops = &clkops_omap2_dflt, | ||
1826 | .enable_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL, | ||
1827 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | ||
1828 | .clkdm_name = "l4_per_clkdm", | ||
1829 | .parent = &func_96m_fclk, | ||
1830 | .recalc = &followparent_recalc, | ||
1831 | }; | ||
1832 | |||
1833 | static struct clk i2c3_ck = { | ||
1834 | .name = "i2c3_ck", | ||
1835 | .ops = &clkops_omap2_dflt, | ||
1836 | .enable_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL, | ||
1837 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | ||
1838 | .clkdm_name = "l4_per_clkdm", | ||
1839 | .parent = &func_96m_fclk, | ||
1840 | .recalc = &followparent_recalc, | ||
1841 | }; | ||
1842 | |||
1843 | static struct clk i2c4_ck = { | ||
1844 | .name = "i2c4_ck", | ||
1845 | .ops = &clkops_omap2_dflt, | ||
1846 | .enable_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL, | ||
1847 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | ||
1848 | .clkdm_name = "l4_per_clkdm", | ||
1849 | .parent = &func_96m_fclk, | ||
1850 | .recalc = &followparent_recalc, | ||
1851 | }; | ||
1852 | |||
1853 | static struct clk iss_ck = { | ||
1854 | .name = "iss_ck", | ||
1855 | .ops = &clkops_omap2_dflt, | ||
1856 | .enable_reg = OMAP4430_CM_CAM_ISS_CLKCTRL, | ||
1857 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | ||
1858 | .clkdm_name = "iss_clkdm", | ||
1859 | .parent = &ducati_clk_mux_ck, | ||
1860 | .recalc = &followparent_recalc, | ||
1861 | }; | ||
1862 | |||
1863 | static struct clk ivahd_ck = { | ||
1864 | .name = "ivahd_ck", | ||
1865 | .ops = &clkops_omap2_dflt, | ||
1866 | .enable_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL, | ||
1867 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | ||
1868 | .clkdm_name = "ivahd_clkdm", | ||
1869 | .parent = &dpll_iva_m5_ck, | ||
1870 | .recalc = &followparent_recalc, | ||
1871 | }; | ||
1872 | |||
1873 | static struct clk keyboard_ck = { | ||
1874 | .name = "keyboard_ck", | ||
1875 | .ops = &clkops_omap2_dflt, | ||
1876 | .enable_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL, | ||
1877 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | ||
1878 | .clkdm_name = "l4_wkup_clkdm", | ||
1879 | .parent = &sys_32k_ck, | ||
1880 | .recalc = &followparent_recalc, | ||
1881 | }; | ||
1882 | |||
1883 | static struct clk l3_instr_interconnect_ck = { | ||
1884 | .name = "l3_instr_interconnect_ck", | ||
1885 | .ops = &clkops_omap2_dflt, | ||
1886 | .enable_reg = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL, | ||
1887 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | ||
1888 | .clkdm_name = "l3_instr_clkdm", | ||
1889 | .parent = &l3_div_ck, | ||
1890 | .recalc = &followparent_recalc, | ||
1891 | }; | ||
1892 | |||
1893 | static struct clk l3_interconnect_3_ck = { | ||
1894 | .name = "l3_interconnect_3_ck", | ||
1895 | .ops = &clkops_omap2_dflt, | ||
1896 | .enable_reg = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL, | ||
1897 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | ||
1898 | .clkdm_name = "l3_instr_clkdm", | ||
1899 | .parent = &l3_div_ck, | ||
1900 | .recalc = &followparent_recalc, | ||
1901 | }; | ||
1902 | |||
1903 | static struct clk mcasp_sync_mux_ck = { | ||
1904 | .name = "mcasp_sync_mux_ck", | ||
1905 | .parent = &abe_24m_fclk, | ||
1906 | .clksel = dmic_sync_mux_sel, | ||
1907 | .init = &omap2_init_clksel_parent, | ||
1908 | .clksel_reg = OMAP4430_CM1_ABE_MCASP_CLKCTRL, | ||
1909 | .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, | ||
1910 | .ops = &clkops_null, | ||
1911 | .recalc = &omap2_clksel_recalc, | ||
1912 | .flags = CLOCK_IN_OMAP4430, | ||
1913 | }; | ||
1914 | |||
1915 | static const struct clksel func_mcasp_abe_gfclk_sel[] = { | ||
1916 | { .parent = &mcasp_sync_mux_ck, .rates = div_1_0_rates }, | ||
1917 | { .parent = &pad_clks_ck, .rates = div_1_1_rates }, | ||
1918 | { .parent = &slimbus_clk, .rates = div_1_2_rates }, | ||
1919 | { .parent = NULL }, | ||
1920 | }; | ||
1921 | |||
1922 | /* Merged func_mcasp_abe_gfclk into mcasp_ck */ | ||
1923 | static struct clk mcasp_ck = { | ||
1924 | .name = "mcasp_ck", | ||
1925 | .parent = &mcasp_sync_mux_ck, | ||
1926 | .clksel = func_mcasp_abe_gfclk_sel, | ||
1927 | .init = &omap2_init_clksel_parent, | ||
1928 | .clksel_reg = OMAP4430_CM1_ABE_MCASP_CLKCTRL, | ||
1929 | .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, | ||
1930 | .ops = &clkops_omap2_dflt, | ||
1931 | .recalc = &omap2_clksel_recalc, | ||
1932 | .flags = CLOCK_IN_OMAP4430, | ||
1933 | .enable_reg = OMAP4430_CM1_ABE_MCASP_CLKCTRL, | ||
1934 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | ||
1935 | .clkdm_name = "abe_clkdm", | ||
1936 | }; | ||
1937 | |||
1938 | static struct clk mcbsp1_sync_mux_ck = { | ||
1939 | .name = "mcbsp1_sync_mux_ck", | ||
1940 | .parent = &abe_24m_fclk, | ||
1941 | .clksel = dmic_sync_mux_sel, | ||
1942 | .init = &omap2_init_clksel_parent, | ||
1943 | .clksel_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL, | ||
1944 | .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, | ||
1945 | .ops = &clkops_null, | ||
1946 | .recalc = &omap2_clksel_recalc, | ||
1947 | .flags = CLOCK_IN_OMAP4430, | ||
1948 | }; | ||
1949 | |||
1950 | static const struct clksel func_mcbsp1_gfclk_sel[] = { | ||
1951 | { .parent = &mcbsp1_sync_mux_ck, .rates = div_1_0_rates }, | ||
1952 | { .parent = &pad_clks_ck, .rates = div_1_1_rates }, | ||
1953 | { .parent = &slimbus_clk, .rates = div_1_2_rates }, | ||
1954 | { .parent = NULL }, | ||
1955 | }; | ||
1956 | |||
1957 | /* Merged func_mcbsp1_gfclk into mcbsp1_ck */ | ||
1958 | static struct clk mcbsp1_ck = { | ||
1959 | .name = "mcbsp1_ck", | ||
1960 | .parent = &mcbsp1_sync_mux_ck, | ||
1961 | .clksel = func_mcbsp1_gfclk_sel, | ||
1962 | .init = &omap2_init_clksel_parent, | ||
1963 | .clksel_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL, | ||
1964 | .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, | ||
1965 | .ops = &clkops_omap2_dflt, | ||
1966 | .recalc = &omap2_clksel_recalc, | ||
1967 | .flags = CLOCK_IN_OMAP4430, | ||
1968 | .enable_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL, | ||
1969 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | ||
1970 | .clkdm_name = "abe_clkdm", | ||
1971 | }; | ||
1972 | |||
1973 | static struct clk mcbsp2_sync_mux_ck = { | ||
1974 | .name = "mcbsp2_sync_mux_ck", | ||
1975 | .parent = &abe_24m_fclk, | ||
1976 | .clksel = dmic_sync_mux_sel, | ||
1977 | .init = &omap2_init_clksel_parent, | ||
1978 | .clksel_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL, | ||
1979 | .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, | ||
1980 | .ops = &clkops_null, | ||
1981 | .recalc = &omap2_clksel_recalc, | ||
1982 | .flags = CLOCK_IN_OMAP4430, | ||
1983 | }; | ||
1984 | |||
1985 | static const struct clksel func_mcbsp2_gfclk_sel[] = { | ||
1986 | { .parent = &mcbsp2_sync_mux_ck, .rates = div_1_0_rates }, | ||
1987 | { .parent = &pad_clks_ck, .rates = div_1_1_rates }, | ||
1988 | { .parent = &slimbus_clk, .rates = div_1_2_rates }, | ||
1989 | { .parent = NULL }, | ||
1990 | }; | ||
1991 | |||
1992 | /* Merged func_mcbsp2_gfclk into mcbsp2_ck */ | ||
1993 | static struct clk mcbsp2_ck = { | ||
1994 | .name = "mcbsp2_ck", | ||
1995 | .parent = &mcbsp2_sync_mux_ck, | ||
1996 | .clksel = func_mcbsp2_gfclk_sel, | ||
1997 | .init = &omap2_init_clksel_parent, | ||
1998 | .clksel_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL, | ||
1999 | .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, | ||
2000 | .ops = &clkops_omap2_dflt, | ||
2001 | .recalc = &omap2_clksel_recalc, | ||
2002 | .flags = CLOCK_IN_OMAP4430, | ||
2003 | .enable_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL, | ||
2004 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | ||
2005 | .clkdm_name = "abe_clkdm", | ||
2006 | }; | ||
2007 | |||
2008 | static struct clk mcbsp3_sync_mux_ck = { | ||
2009 | .name = "mcbsp3_sync_mux_ck", | ||
2010 | .parent = &abe_24m_fclk, | ||
2011 | .clksel = dmic_sync_mux_sel, | ||
2012 | .init = &omap2_init_clksel_parent, | ||
2013 | .clksel_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL, | ||
2014 | .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, | ||
2015 | .ops = &clkops_null, | ||
2016 | .recalc = &omap2_clksel_recalc, | ||
2017 | .flags = CLOCK_IN_OMAP4430, | ||
2018 | }; | ||
2019 | |||
2020 | static const struct clksel func_mcbsp3_gfclk_sel[] = { | ||
2021 | { .parent = &mcbsp3_sync_mux_ck, .rates = div_1_0_rates }, | ||
2022 | { .parent = &pad_clks_ck, .rates = div_1_1_rates }, | ||
2023 | { .parent = &slimbus_clk, .rates = div_1_2_rates }, | ||
2024 | { .parent = NULL }, | ||
2025 | }; | ||
2026 | |||
2027 | /* Merged func_mcbsp3_gfclk into mcbsp3_ck */ | ||
2028 | static struct clk mcbsp3_ck = { | ||
2029 | .name = "mcbsp3_ck", | ||
2030 | .parent = &mcbsp3_sync_mux_ck, | ||
2031 | .clksel = func_mcbsp3_gfclk_sel, | ||
2032 | .init = &omap2_init_clksel_parent, | ||
2033 | .clksel_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL, | ||
2034 | .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, | ||
2035 | .ops = &clkops_omap2_dflt, | ||
2036 | .recalc = &omap2_clksel_recalc, | ||
2037 | .flags = CLOCK_IN_OMAP4430, | ||
2038 | .enable_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL, | ||
2039 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | ||
2040 | .clkdm_name = "abe_clkdm", | ||
2041 | }; | ||
2042 | |||
2043 | static struct clk mcbsp4_sync_mux_ck = { | ||
2044 | .name = "mcbsp4_sync_mux_ck", | ||
2045 | .parent = &func_96m_fclk, | ||
2046 | .clksel = mcasp2_fclk_sel, | ||
2047 | .init = &omap2_init_clksel_parent, | ||
2048 | .clksel_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL, | ||
2049 | .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, | ||
2050 | .ops = &clkops_null, | ||
2051 | .recalc = &omap2_clksel_recalc, | ||
2052 | .flags = CLOCK_IN_OMAP4430, | ||
2053 | }; | ||
2054 | |||
2055 | static const struct clksel per_mcbsp4_gfclk_sel[] = { | ||
2056 | { .parent = &mcbsp4_sync_mux_ck, .rates = div_1_0_rates }, | ||
2057 | { .parent = &pad_clks_ck, .rates = div_1_1_rates }, | ||
2058 | { .parent = NULL }, | ||
2059 | }; | ||
2060 | |||
2061 | /* Merged per_mcbsp4_gfclk into mcbsp4_ck */ | ||
2062 | static struct clk mcbsp4_ck = { | ||
2063 | .name = "mcbsp4_ck", | ||
2064 | .parent = &mcbsp4_sync_mux_ck, | ||
2065 | .clksel = per_mcbsp4_gfclk_sel, | ||
2066 | .init = &omap2_init_clksel_parent, | ||
2067 | .clksel_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL, | ||
2068 | .clksel_mask = OMAP4430_CLKSEL_SOURCE_24_24_MASK, | ||
2069 | .ops = &clkops_omap2_dflt, | ||
2070 | .recalc = &omap2_clksel_recalc, | ||
2071 | .flags = CLOCK_IN_OMAP4430, | ||
2072 | .enable_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL, | ||
2073 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | ||
2074 | .clkdm_name = "l4_per_clkdm", | ||
2075 | }; | ||
2076 | |||
2077 | static struct clk mcspi1_ck = { | ||
2078 | .name = "mcspi1_ck", | ||
2079 | .ops = &clkops_omap2_dflt, | ||
2080 | .enable_reg = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL, | ||
2081 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | ||
2082 | .clkdm_name = "l4_per_clkdm", | ||
2083 | .parent = &func_48m_fclk, | ||
2084 | .recalc = &followparent_recalc, | ||
2085 | }; | ||
2086 | |||
2087 | static struct clk mcspi2_ck = { | ||
2088 | .name = "mcspi2_ck", | ||
2089 | .ops = &clkops_omap2_dflt, | ||
2090 | .enable_reg = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL, | ||
2091 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | ||
2092 | .clkdm_name = "l4_per_clkdm", | ||
2093 | .parent = &func_48m_fclk, | ||
2094 | .recalc = &followparent_recalc, | ||
2095 | }; | ||
2096 | |||
2097 | static struct clk mcspi3_ck = { | ||
2098 | .name = "mcspi3_ck", | ||
2099 | .ops = &clkops_omap2_dflt, | ||
2100 | .enable_reg = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL, | ||
2101 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | ||
2102 | .clkdm_name = "l4_per_clkdm", | ||
2103 | .parent = &func_48m_fclk, | ||
2104 | .recalc = &followparent_recalc, | ||
2105 | }; | ||
2106 | |||
2107 | static struct clk mcspi4_ck = { | ||
2108 | .name = "mcspi4_ck", | ||
2109 | .ops = &clkops_omap2_dflt, | ||
2110 | .enable_reg = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL, | ||
2111 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | ||
2112 | .clkdm_name = "l4_per_clkdm", | ||
2113 | .parent = &func_48m_fclk, | ||
2114 | .recalc = &followparent_recalc, | ||
2115 | }; | ||
2116 | |||
2117 | /* Merged hsmmc1_fclk into mmc1_ck */ | ||
2118 | static struct clk mmc1_ck = { | ||
2119 | .name = "mmc1_ck", | ||
2120 | .parent = &func_64m_fclk, | ||
2121 | .clksel = hsmmc6_fclk_sel, | ||
2122 | .init = &omap2_init_clksel_parent, | ||
2123 | .clksel_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL, | ||
2124 | .clksel_mask = OMAP4430_CLKSEL_MASK, | ||
2125 | .ops = &clkops_omap2_dflt, | ||
2126 | .recalc = &omap2_clksel_recalc, | ||
2127 | .flags = CLOCK_IN_OMAP4430, | ||
2128 | .enable_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL, | ||
2129 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | ||
2130 | .clkdm_name = "l3_init_clkdm", | ||
2131 | }; | ||
2132 | |||
2133 | /* Merged hsmmc2_fclk into mmc2_ck */ | ||
2134 | static struct clk mmc2_ck = { | ||
2135 | .name = "mmc2_ck", | ||
2136 | .parent = &func_64m_fclk, | ||
2137 | .clksel = hsmmc6_fclk_sel, | ||
2138 | .init = &omap2_init_clksel_parent, | ||
2139 | .clksel_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL, | ||
2140 | .clksel_mask = OMAP4430_CLKSEL_MASK, | ||
2141 | .ops = &clkops_omap2_dflt, | ||
2142 | .recalc = &omap2_clksel_recalc, | ||
2143 | .flags = CLOCK_IN_OMAP4430, | ||
2144 | .enable_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL, | ||
2145 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | ||
2146 | .clkdm_name = "l3_init_clkdm", | ||
2147 | }; | ||
2148 | |||
2149 | static struct clk mmc3_ck = { | ||
2150 | .name = "mmc3_ck", | ||
2151 | .ops = &clkops_omap2_dflt, | ||
2152 | .enable_reg = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL, | ||
2153 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | ||
2154 | .clkdm_name = "l4_per_clkdm", | ||
2155 | .parent = &func_48m_fclk, | ||
2156 | .recalc = &followparent_recalc, | ||
2157 | }; | ||
2158 | |||
2159 | static struct clk mmc4_ck = { | ||
2160 | .name = "mmc4_ck", | ||
2161 | .ops = &clkops_omap2_dflt, | ||
2162 | .enable_reg = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL, | ||
2163 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | ||
2164 | .clkdm_name = "l4_per_clkdm", | ||
2165 | .parent = &func_48m_fclk, | ||
2166 | .recalc = &followparent_recalc, | ||
2167 | }; | ||
2168 | |||
2169 | static struct clk mmc5_ck = { | ||
2170 | .name = "mmc5_ck", | ||
2171 | .ops = &clkops_omap2_dflt, | ||
2172 | .enable_reg = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL, | ||
2173 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | ||
2174 | .clkdm_name = "l4_per_clkdm", | ||
2175 | .parent = &func_48m_fclk, | ||
2176 | .recalc = &followparent_recalc, | ||
2177 | }; | ||
2178 | |||
2179 | static struct clk ocp_wp1_ck = { | ||
2180 | .name = "ocp_wp1_ck", | ||
2181 | .ops = &clkops_omap2_dflt, | ||
2182 | .enable_reg = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL, | ||
2183 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | ||
2184 | .clkdm_name = "l3_instr_clkdm", | ||
2185 | .parent = &l3_div_ck, | ||
2186 | .recalc = &followparent_recalc, | ||
2187 | }; | ||
2188 | |||
2189 | static struct clk pdm_ck = { | ||
2190 | .name = "pdm_ck", | ||
2191 | .ops = &clkops_omap2_dflt, | ||
2192 | .enable_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL, | ||
2193 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | ||
2194 | .clkdm_name = "abe_clkdm", | ||
2195 | .parent = &pad_clks_ck, | ||
2196 | .recalc = &followparent_recalc, | ||
2197 | }; | ||
2198 | |||
2199 | static struct clk pkaeip29_ck = { | ||
2200 | .name = "pkaeip29_ck", | ||
2201 | .ops = &clkops_omap2_dflt, | ||
2202 | .enable_reg = OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL, | ||
2203 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | ||
2204 | .clkdm_name = "l4_secure_clkdm", | ||
2205 | .parent = &l4_div_ck, | ||
2206 | .recalc = &followparent_recalc, | ||
2207 | }; | ||
2208 | |||
2209 | static struct clk rng_ck = { | ||
2210 | .name = "rng_ck", | ||
2211 | .ops = &clkops_omap2_dflt, | ||
2212 | .enable_reg = OMAP4430_CM_L4SEC_RNG_CLKCTRL, | ||
2213 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | ||
2214 | .clkdm_name = "l4_secure_clkdm", | ||
2215 | .parent = &l4_div_ck, | ||
2216 | .recalc = &followparent_recalc, | ||
2217 | }; | ||
2218 | |||
2219 | static struct clk sha2md51_ck = { | ||
2220 | .name = "sha2md51_ck", | ||
2221 | .ops = &clkops_omap2_dflt, | ||
2222 | .enable_reg = OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL, | ||
2223 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | ||
2224 | .clkdm_name = "l4_secure_clkdm", | ||
2225 | .parent = &l3_div_ck, | ||
2226 | .recalc = &followparent_recalc, | ||
2227 | }; | ||
2228 | |||
2229 | static struct clk sl2_ck = { | ||
2230 | .name = "sl2_ck", | ||
2231 | .ops = &clkops_omap2_dflt, | ||
2232 | .enable_reg = OMAP4430_CM_IVAHD_SL2_CLKCTRL, | ||
2233 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | ||
2234 | .clkdm_name = "ivahd_clkdm", | ||
2235 | .parent = &dpll_iva_m5_ck, | ||
2236 | .recalc = &followparent_recalc, | ||
2237 | }; | ||
2238 | |||
2239 | static struct clk slimbus1_ck = { | ||
2240 | .name = "slimbus1_ck", | ||
2241 | .ops = &clkops_omap2_dflt, | ||
2242 | .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, | ||
2243 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | ||
2244 | .clkdm_name = "abe_clkdm", | ||
2245 | .parent = &ocp_abe_iclk, | ||
2246 | .recalc = &followparent_recalc, | ||
2247 | }; | ||
2248 | |||
2249 | static struct clk slimbus2_ck = { | ||
2250 | .name = "slimbus2_ck", | ||
2251 | .ops = &clkops_omap2_dflt, | ||
2252 | .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, | ||
2253 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | ||
2254 | .clkdm_name = "l4_per_clkdm", | ||
2255 | .parent = &l4_div_ck, | ||
2256 | .recalc = &followparent_recalc, | ||
2257 | }; | ||
2258 | |||
2259 | static struct clk sr_core_ck = { | ||
2260 | .name = "sr_core_ck", | ||
2261 | .ops = &clkops_omap2_dflt, | ||
2262 | .enable_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL, | ||
2263 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | ||
2264 | .clkdm_name = "l4_ao_clkdm", | ||
2265 | .parent = &l4_wkup_clk_mux_ck, | ||
2266 | .recalc = &followparent_recalc, | ||
2267 | }; | ||
2268 | |||
2269 | static struct clk sr_iva_ck = { | ||
2270 | .name = "sr_iva_ck", | ||
2271 | .ops = &clkops_omap2_dflt, | ||
2272 | .enable_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL, | ||
2273 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | ||
2274 | .clkdm_name = "l4_ao_clkdm", | ||
2275 | .parent = &l4_wkup_clk_mux_ck, | ||
2276 | .recalc = &followparent_recalc, | ||
2277 | }; | ||
2278 | |||
2279 | static struct clk sr_mpu_ck = { | ||
2280 | .name = "sr_mpu_ck", | ||
2281 | .ops = &clkops_omap2_dflt, | ||
2282 | .enable_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL, | ||
2283 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | ||
2284 | .clkdm_name = "l4_ao_clkdm", | ||
2285 | .parent = &l4_wkup_clk_mux_ck, | ||
2286 | .recalc = &followparent_recalc, | ||
2287 | }; | ||
2288 | |||
2289 | static struct clk tesla_ck = { | ||
2290 | .name = "tesla_ck", | ||
2291 | .ops = &clkops_omap2_dflt, | ||
2292 | .enable_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL, | ||
2293 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | ||
2294 | .clkdm_name = "tesla_clkdm", | ||
2295 | .parent = &dpll_iva_m4_ck, | ||
2296 | .recalc = &followparent_recalc, | ||
2297 | }; | ||
2298 | |||
2299 | static struct clk uart1_ck = { | ||
2300 | .name = "uart1_ck", | ||
2301 | .ops = &clkops_omap2_dflt, | ||
2302 | .enable_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL, | ||
2303 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | ||
2304 | .clkdm_name = "l4_per_clkdm", | ||
2305 | .parent = &func_48m_fclk, | ||
2306 | .recalc = &followparent_recalc, | ||
2307 | }; | ||
2308 | |||
2309 | static struct clk uart2_ck = { | ||
2310 | .name = "uart2_ck", | ||
2311 | .ops = &clkops_omap2_dflt, | ||
2312 | .enable_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL, | ||
2313 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | ||
2314 | .clkdm_name = "l4_per_clkdm", | ||
2315 | .parent = &func_48m_fclk, | ||
2316 | .recalc = &followparent_recalc, | ||
2317 | }; | ||
2318 | |||
2319 | static struct clk uart3_ck = { | ||
2320 | .name = "uart3_ck", | ||
2321 | .ops = &clkops_omap2_dflt, | ||
2322 | .enable_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL, | ||
2323 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | ||
2324 | .clkdm_name = "l4_per_clkdm", | ||
2325 | .parent = &func_48m_fclk, | ||
2326 | .recalc = &followparent_recalc, | ||
2327 | }; | ||
2328 | |||
2329 | static struct clk uart4_ck = { | ||
2330 | .name = "uart4_ck", | ||
2331 | .ops = &clkops_omap2_dflt, | ||
2332 | .enable_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL, | ||
2333 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | ||
2334 | .clkdm_name = "l4_per_clkdm", | ||
2335 | .parent = &func_48m_fclk, | ||
2336 | .recalc = &followparent_recalc, | ||
2337 | }; | ||
2338 | |||
2339 | static struct clk unipro1_ck = { | ||
2340 | .name = "unipro1_ck", | ||
2341 | .ops = &clkops_omap2_dflt, | ||
2342 | .enable_reg = OMAP4430_CM_L3INIT_UNIPRO1_CLKCTRL, | ||
2343 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | ||
2344 | .clkdm_name = "l3_init_clkdm", | ||
2345 | .parent = &func_96m_fclk, | ||
2346 | .recalc = &followparent_recalc, | ||
2347 | }; | ||
2348 | |||
2349 | static struct clk usb_host_ck = { | ||
2350 | .name = "usb_host_ck", | ||
2351 | .ops = &clkops_omap2_dflt, | ||
2352 | .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, | ||
2353 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | ||
2354 | .clkdm_name = "l3_init_clkdm", | ||
2355 | .parent = &init_60m_fclk, | ||
2356 | .recalc = &followparent_recalc, | ||
2357 | }; | ||
2358 | |||
2359 | static struct clk usb_host_fs_ck = { | ||
2360 | .name = "usb_host_fs_ck", | ||
2361 | .ops = &clkops_omap2_dflt, | ||
2362 | .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL, | ||
2363 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | ||
2364 | .clkdm_name = "l3_init_clkdm", | ||
2365 | .parent = &func_48mc_fclk, | ||
2366 | .recalc = &followparent_recalc, | ||
2367 | }; | ||
2368 | |||
2369 | static struct clk usb_otg_ck = { | ||
2370 | .name = "usb_otg_ck", | ||
2371 | .ops = &clkops_omap2_dflt, | ||
2372 | .enable_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, | ||
2373 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | ||
2374 | .clkdm_name = "l3_init_clkdm", | ||
2375 | .parent = &l3_div_ck, | ||
2376 | .recalc = &followparent_recalc, | ||
2377 | }; | ||
2378 | |||
2379 | static struct clk usb_tll_ck = { | ||
2380 | .name = "usb_tll_ck", | ||
2381 | .ops = &clkops_omap2_dflt, | ||
2382 | .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, | ||
2383 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | ||
2384 | .clkdm_name = "l3_init_clkdm", | ||
2385 | .parent = &l4_div_ck, | ||
2386 | .recalc = &followparent_recalc, | ||
2387 | }; | ||
2388 | |||
2389 | static struct clk usbphyocp2scp_ck = { | ||
2390 | .name = "usbphyocp2scp_ck", | ||
2391 | .ops = &clkops_omap2_dflt, | ||
2392 | .enable_reg = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, | ||
2393 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | ||
2394 | .clkdm_name = "l3_init_clkdm", | ||
2395 | .parent = &l4_div_ck, | ||
2396 | .recalc = &followparent_recalc, | ||
2397 | }; | ||
2398 | |||
2399 | static struct clk usim_ck = { | ||
2400 | .name = "usim_ck", | ||
2401 | .ops = &clkops_omap2_dflt, | ||
2402 | .enable_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL, | ||
2403 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | ||
2404 | .clkdm_name = "l4_wkup_clkdm", | ||
2405 | .parent = &sys_32k_ck, | ||
2406 | .recalc = &followparent_recalc, | ||
2407 | }; | ||
2408 | |||
2409 | static struct clk wdt2_ck = { | ||
2410 | .name = "wdt2_ck", | ||
2411 | .ops = &clkops_omap2_dflt, | ||
2412 | .enable_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL, | ||
2413 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | ||
2414 | .clkdm_name = "l4_wkup_clkdm", | ||
2415 | .parent = &sys_32k_ck, | ||
2416 | .recalc = &followparent_recalc, | ||
2417 | }; | ||
2418 | |||
2419 | static struct clk wdt3_ck = { | ||
2420 | .name = "wdt3_ck", | ||
2421 | .ops = &clkops_omap2_dflt, | ||
2422 | .enable_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL, | ||
2423 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | ||
2424 | .clkdm_name = "abe_clkdm", | ||
2425 | .parent = &sys_32k_ck, | ||
2426 | .recalc = &followparent_recalc, | ||
2427 | }; | ||
2428 | |||
2429 | /* Remaining optional clocks */ | ||
2430 | static const struct clksel otg_60m_gfclk_sel[] = { | ||
2431 | { .parent = &utmi_phy_clkout_ck, .rates = div_1_0_rates }, | ||
2432 | { .parent = &xclk60motg_ck, .rates = div_1_1_rates }, | ||
2433 | { .parent = NULL }, | ||
2434 | }; | ||
2435 | |||
2436 | static struct clk otg_60m_gfclk_ck = { | ||
2437 | .name = "otg_60m_gfclk_ck", | ||
2438 | .parent = &utmi_phy_clkout_ck, | ||
2439 | .clksel = otg_60m_gfclk_sel, | ||
2440 | .init = &omap2_init_clksel_parent, | ||
2441 | .clksel_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, | ||
2442 | .clksel_mask = OMAP4430_CLKSEL_60M_MASK, | ||
2443 | .ops = &clkops_null, | ||
2444 | .recalc = &omap2_clksel_recalc, | ||
2445 | .flags = CLOCK_IN_OMAP4430, | ||
2446 | }; | ||
2447 | |||
2448 | static const struct clksel stm_clk_div_div[] = { | ||
2449 | { .parent = &pmd_stm_clock_mux_ck, .rates = div3_1to4_rates }, | ||
2450 | { .parent = NULL }, | ||
2451 | }; | ||
2452 | |||
2453 | static struct clk stm_clk_div_ck = { | ||
2454 | .name = "stm_clk_div_ck", | ||
2455 | .parent = &pmd_stm_clock_mux_ck, | ||
2456 | .clksel = stm_clk_div_div, | ||
2457 | .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, | ||
2458 | .clksel_mask = OMAP4430_CLKSEL_PMD_STM_CLK_MASK, | ||
2459 | .ops = &clkops_null, | ||
2460 | .recalc = &omap2_clksel_recalc, | ||
2461 | .round_rate = &omap2_clksel_round_rate, | ||
2462 | .set_rate = &omap2_clksel_set_rate, | ||
2463 | .flags = CLOCK_IN_OMAP4430, | ||
2464 | }; | ||
2465 | |||
2466 | static const struct clksel trace_clk_div_div[] = { | ||
2467 | { .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates }, | ||
2468 | { .parent = NULL }, | ||
2469 | }; | ||
2470 | |||
2471 | static struct clk trace_clk_div_ck = { | ||
2472 | .name = "trace_clk_div_ck", | ||
2473 | .parent = &pmd_trace_clk_mux_ck, | ||
2474 | .clksel = trace_clk_div_div, | ||
2475 | .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, | ||
2476 | .clksel_mask = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK, | ||
2477 | .ops = &clkops_null, | ||
2478 | .recalc = &omap2_clksel_recalc, | ||
2479 | .round_rate = &omap2_clksel_round_rate, | ||
2480 | .set_rate = &omap2_clksel_set_rate, | ||
2481 | .flags = CLOCK_IN_OMAP4430, | ||
2482 | }; | ||
2483 | |||
2484 | static const struct clksel_rate div2_14to18_rates[] = { | ||
2485 | { .div = 14, .val = 0, .flags = RATE_IN_4430 }, | ||
2486 | { .div = 18, .val = 1, .flags = RATE_IN_4430 }, | ||
2487 | { .div = 0 }, | ||
2488 | }; | ||
2489 | |||
2490 | static const struct clksel usim_fclk_div[] = { | ||
2491 | { .parent = &dpll_per_m4_ck, .rates = div2_14to18_rates }, | ||
2492 | { .parent = NULL }, | ||
2493 | }; | ||
2494 | |||
2495 | static struct clk usim_fclk = { | ||
2496 | .name = "usim_fclk", | ||
2497 | .parent = &dpll_per_m4_ck, | ||
2498 | .clksel = usim_fclk_div, | ||
2499 | .clksel_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL, | ||
2500 | .clksel_mask = OMAP4430_CLKSEL_DIV_MASK, | ||
2501 | .ops = &clkops_null, | ||
2502 | .recalc = &omap2_clksel_recalc, | ||
2503 | .round_rate = &omap2_clksel_round_rate, | ||
2504 | .set_rate = &omap2_clksel_set_rate, | ||
2505 | .flags = CLOCK_IN_OMAP4430, | ||
2506 | }; | ||
2507 | |||
2508 | static const struct clksel utmi_p1_gfclk_sel[] = { | ||
2509 | { .parent = &init_60m_fclk, .rates = div_1_0_rates }, | ||
2510 | { .parent = &xclk60mhsp1_ck, .rates = div_1_1_rates }, | ||
2511 | { .parent = NULL }, | ||
2512 | }; | ||
2513 | |||
2514 | static struct clk utmi_p1_gfclk_ck = { | ||
2515 | .name = "utmi_p1_gfclk_ck", | ||
2516 | .parent = &init_60m_fclk, | ||
2517 | .clksel = utmi_p1_gfclk_sel, | ||
2518 | .init = &omap2_init_clksel_parent, | ||
2519 | .clksel_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, | ||
2520 | .clksel_mask = OMAP4430_CLKSEL_UTMI_P1_MASK, | ||
2521 | .ops = &clkops_null, | ||
2522 | .recalc = &omap2_clksel_recalc, | ||
2523 | .flags = CLOCK_IN_OMAP4430, | ||
2524 | }; | ||
2525 | |||
2526 | static const struct clksel utmi_p2_gfclk_sel[] = { | ||
2527 | { .parent = &init_60m_fclk, .rates = div_1_0_rates }, | ||
2528 | { .parent = &xclk60mhsp2_ck, .rates = div_1_1_rates }, | ||
2529 | { .parent = NULL }, | ||
2530 | }; | ||
2531 | |||
2532 | static struct clk utmi_p2_gfclk_ck = { | ||
2533 | .name = "utmi_p2_gfclk_ck", | ||
2534 | .parent = &init_60m_fclk, | ||
2535 | .clksel = utmi_p2_gfclk_sel, | ||
2536 | .init = &omap2_init_clksel_parent, | ||
2537 | .clksel_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, | ||
2538 | .clksel_mask = OMAP4430_CLKSEL_UTMI_P2_MASK, | ||
2539 | .ops = &clkops_null, | ||
2540 | .recalc = &omap2_clksel_recalc, | ||
2541 | .flags = CLOCK_IN_OMAP4430, | ||
2542 | }; | ||
2543 | |||
2544 | /* | ||
2545 | * clkdev | ||
2546 | */ | ||
2547 | |||
2548 | static struct omap_clk omap44xx_clks[] = { | ||
2549 | CLK(NULL, "extalt_clkin_ck", &extalt_clkin_ck, CK_443X), | ||
2550 | CLK(NULL, "pad_clks_ck", &pad_clks_ck, CK_443X), | ||
2551 | CLK(NULL, "pad_slimbus_core_clks_ck", &pad_slimbus_core_clks_ck, CK_443X), | ||
2552 | CLK(NULL, "secure_32k_clk_src_ck", &secure_32k_clk_src_ck, CK_443X), | ||
2553 | CLK(NULL, "slimbus_clk", &slimbus_clk, CK_443X), | ||
2554 | CLK(NULL, "sys_32k_ck", &sys_32k_ck, CK_443X), | ||
2555 | CLK(NULL, "virt_12000000_ck", &virt_12000000_ck, CK_443X), | ||
2556 | CLK(NULL, "virt_13000000_ck", &virt_13000000_ck, CK_443X), | ||
2557 | CLK(NULL, "virt_16800000_ck", &virt_16800000_ck, CK_443X), | ||
2558 | CLK(NULL, "virt_19200000_ck", &virt_19200000_ck, CK_443X), | ||
2559 | CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_443X), | ||
2560 | CLK(NULL, "virt_27000000_ck", &virt_27000000_ck, CK_443X), | ||
2561 | CLK(NULL, "virt_38400000_ck", &virt_38400000_ck, CK_443X), | ||
2562 | CLK(NULL, "sys_clkin_ck", &sys_clkin_ck, CK_443X), | ||
2563 | CLK(NULL, "utmi_phy_clkout_ck", &utmi_phy_clkout_ck, CK_443X), | ||
2564 | CLK(NULL, "xclk60mhsp1_ck", &xclk60mhsp1_ck, CK_443X), | ||
2565 | CLK(NULL, "xclk60mhsp2_ck", &xclk60mhsp2_ck, CK_443X), | ||
2566 | CLK(NULL, "xclk60motg_ck", &xclk60motg_ck, CK_443X), | ||
2567 | CLK(NULL, "dpll_sys_ref_clk", &dpll_sys_ref_clk, CK_443X), | ||
2568 | CLK(NULL, "abe_dpll_refclk_mux_ck", &abe_dpll_refclk_mux_ck, CK_443X), | ||
2569 | CLK(NULL, "dpll_abe_ck", &dpll_abe_ck, CK_443X), | ||
2570 | CLK(NULL, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, CK_443X), | ||
2571 | CLK(NULL, "abe_24m_fclk", &abe_24m_fclk, CK_443X), | ||
2572 | CLK(NULL, "abe_clk", &abe_clk, CK_443X), | ||
2573 | CLK(NULL, "aess_fclk", &aess_fclk, CK_443X), | ||
2574 | CLK(NULL, "dpll_abe_m3_ck", &dpll_abe_m3_ck, CK_443X), | ||
2575 | CLK(NULL, "core_hsd_byp_clk_mux_ck", &core_hsd_byp_clk_mux_ck, CK_443X), | ||
2576 | CLK(NULL, "dpll_core_ck", &dpll_core_ck, CK_443X), | ||
2577 | CLK(NULL, "dpll_core_m6_ck", &dpll_core_m6_ck, CK_443X), | ||
2578 | CLK(NULL, "dbgclk_mux_ck", &dbgclk_mux_ck, CK_443X), | ||
2579 | CLK(NULL, "dpll_core_m2_ck", &dpll_core_m2_ck, CK_443X), | ||
2580 | CLK(NULL, "ddrphy_ck", &ddrphy_ck, CK_443X), | ||
2581 | CLK(NULL, "dpll_core_m5_ck", &dpll_core_m5_ck, CK_443X), | ||
2582 | CLK(NULL, "div_core_ck", &div_core_ck, CK_443X), | ||
2583 | CLK(NULL, "div_iva_hs_clk", &div_iva_hs_clk, CK_443X), | ||
2584 | CLK(NULL, "div_mpu_hs_clk", &div_mpu_hs_clk, CK_443X), | ||
2585 | CLK(NULL, "dpll_core_m4_ck", &dpll_core_m4_ck, CK_443X), | ||
2586 | CLK(NULL, "dll_clk_div_ck", &dll_clk_div_ck, CK_443X), | ||
2587 | CLK(NULL, "dpll_abe_m2_ck", &dpll_abe_m2_ck, CK_443X), | ||
2588 | CLK(NULL, "dpll_core_m3_ck", &dpll_core_m3_ck, CK_443X), | ||
2589 | CLK(NULL, "dpll_core_m7_ck", &dpll_core_m7_ck, CK_443X), | ||
2590 | CLK(NULL, "iva_hsd_byp_clk_mux_ck", &iva_hsd_byp_clk_mux_ck, CK_443X), | ||
2591 | CLK(NULL, "dpll_iva_ck", &dpll_iva_ck, CK_443X), | ||
2592 | CLK(NULL, "dpll_iva_m4_ck", &dpll_iva_m4_ck, CK_443X), | ||
2593 | CLK(NULL, "dpll_iva_m5_ck", &dpll_iva_m5_ck, CK_443X), | ||
2594 | CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_443X), | ||
2595 | CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_443X), | ||
2596 | CLK(NULL, "per_hs_clk_div_ck", &per_hs_clk_div_ck, CK_443X), | ||
2597 | CLK(NULL, "per_hsd_byp_clk_mux_ck", &per_hsd_byp_clk_mux_ck, CK_443X), | ||
2598 | CLK(NULL, "dpll_per_ck", &dpll_per_ck, CK_443X), | ||
2599 | CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck, CK_443X), | ||
2600 | CLK(NULL, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, CK_443X), | ||
2601 | CLK(NULL, "dpll_per_m3_ck", &dpll_per_m3_ck, CK_443X), | ||
2602 | CLK(NULL, "dpll_per_m4_ck", &dpll_per_m4_ck, CK_443X), | ||
2603 | CLK(NULL, "dpll_per_m5_ck", &dpll_per_m5_ck, CK_443X), | ||
2604 | CLK(NULL, "dpll_per_m6_ck", &dpll_per_m6_ck, CK_443X), | ||
2605 | CLK(NULL, "dpll_per_m7_ck", &dpll_per_m7_ck, CK_443X), | ||
2606 | CLK(NULL, "dpll_unipro_ck", &dpll_unipro_ck, CK_443X), | ||
2607 | CLK(NULL, "dpll_unipro_m2x2_ck", &dpll_unipro_m2x2_ck, CK_443X), | ||
2608 | CLK(NULL, "usb_hs_clk_div_ck", &usb_hs_clk_div_ck, CK_443X), | ||
2609 | CLK(NULL, "dpll_usb_ck", &dpll_usb_ck, CK_443X), | ||
2610 | CLK(NULL, "dpll_usb_clkdcoldo_ck", &dpll_usb_clkdcoldo_ck, CK_443X), | ||
2611 | CLK(NULL, "dpll_usb_m2_ck", &dpll_usb_m2_ck, CK_443X), | ||
2612 | CLK(NULL, "ducati_clk_mux_ck", &ducati_clk_mux_ck, CK_443X), | ||
2613 | CLK(NULL, "func_12m_fclk", &func_12m_fclk, CK_443X), | ||
2614 | CLK(NULL, "func_24m_clk", &func_24m_clk, CK_443X), | ||
2615 | CLK(NULL, "func_24mc_fclk", &func_24mc_fclk, CK_443X), | ||
2616 | CLK(NULL, "func_48m_fclk", &func_48m_fclk, CK_443X), | ||
2617 | CLK(NULL, "func_48mc_fclk", &func_48mc_fclk, CK_443X), | ||
2618 | CLK(NULL, "func_64m_fclk", &func_64m_fclk, CK_443X), | ||
2619 | CLK(NULL, "func_96m_fclk", &func_96m_fclk, CK_443X), | ||
2620 | CLK(NULL, "hsmmc6_fclk", &hsmmc6_fclk, CK_443X), | ||
2621 | CLK(NULL, "init_60m_fclk", &init_60m_fclk, CK_443X), | ||
2622 | CLK(NULL, "l3_div_ck", &l3_div_ck, CK_443X), | ||
2623 | CLK(NULL, "l4_div_ck", &l4_div_ck, CK_443X), | ||
2624 | CLK(NULL, "lp_clk_div_ck", &lp_clk_div_ck, CK_443X), | ||
2625 | CLK(NULL, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, CK_443X), | ||
2626 | CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk, CK_443X), | ||
2627 | CLK(NULL, "mcasp2_fclk", &mcasp2_fclk, CK_443X), | ||
2628 | CLK(NULL, "mcasp3_fclk", &mcasp3_fclk, CK_443X), | ||
2629 | CLK(NULL, "ocp_abe_iclk", &ocp_abe_iclk, CK_443X), | ||
2630 | CLK(NULL, "per_abe_24m_fclk", &per_abe_24m_fclk, CK_443X), | ||
2631 | CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck, CK_443X), | ||
2632 | CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck, CK_443X), | ||
2633 | CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck, CK_443X), | ||
2634 | CLK(NULL, "aes1_ck", &aes1_ck, CK_443X), | ||
2635 | CLK(NULL, "aes2_ck", &aes2_ck, CK_443X), | ||
2636 | CLK(NULL, "aess_ck", &aess_ck, CK_443X), | ||
2637 | CLK(NULL, "cust_efuse_ck", &cust_efuse_ck, CK_443X), | ||
2638 | CLK(NULL, "des3des_ck", &des3des_ck, CK_443X), | ||
2639 | CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X), | ||
2640 | CLK(NULL, "dmic_ck", &dmic_ck, CK_443X), | ||
2641 | CLK(NULL, "dss_ck", &dss_ck, CK_443X), | ||
2642 | CLK(NULL, "ducati_ck", &ducati_ck, CK_443X), | ||
2643 | CLK(NULL, "emif1_ck", &emif1_ck, CK_443X), | ||
2644 | CLK(NULL, "emif2_ck", &emif2_ck, CK_443X), | ||
2645 | CLK(NULL, "fdif_ck", &fdif_ck, CK_443X), | ||
2646 | CLK(NULL, "per_sgx_fclk", &per_sgx_fclk, CK_443X), | ||
2647 | CLK(NULL, "gfx_ck", &gfx_ck, CK_443X), | ||
2648 | CLK(NULL, "gpio1_ck", &gpio1_ck, CK_443X), | ||
2649 | CLK(NULL, "gpio2_ck", &gpio2_ck, CK_443X), | ||
2650 | CLK(NULL, "gpio3_ck", &gpio3_ck, CK_443X), | ||
2651 | CLK(NULL, "gpio4_ck", &gpio4_ck, CK_443X), | ||
2652 | CLK(NULL, "gpio5_ck", &gpio5_ck, CK_443X), | ||
2653 | CLK(NULL, "gpio6_ck", &gpio6_ck, CK_443X), | ||
2654 | CLK(NULL, "gpmc_ck", &gpmc_ck, CK_443X), | ||
2655 | CLK(NULL, "gptimer1_ck", &gptimer1_ck, CK_443X), | ||
2656 | CLK(NULL, "gptimer10_ck", &gptimer10_ck, CK_443X), | ||
2657 | CLK(NULL, "gptimer11_ck", &gptimer11_ck, CK_443X), | ||
2658 | CLK(NULL, "gptimer2_ck", &gptimer2_ck, CK_443X), | ||
2659 | CLK(NULL, "gptimer3_ck", &gptimer3_ck, CK_443X), | ||
2660 | CLK(NULL, "gptimer4_ck", &gptimer4_ck, CK_443X), | ||
2661 | CLK(NULL, "gptimer5_ck", &gptimer5_ck, CK_443X), | ||
2662 | CLK(NULL, "gptimer6_ck", &gptimer6_ck, CK_443X), | ||
2663 | CLK(NULL, "gptimer7_ck", &gptimer7_ck, CK_443X), | ||
2664 | CLK(NULL, "gptimer8_ck", &gptimer8_ck, CK_443X), | ||
2665 | CLK(NULL, "gptimer9_ck", &gptimer9_ck, CK_443X), | ||
2666 | CLK("omap2_hdq.0", "ick", &hdq1w_ck, CK_443X), | ||
2667 | CLK(NULL, "hsi_ck", &hsi_ck, CK_443X), | ||
2668 | CLK("i2c_omap.1", "ick", &i2c1_ck, CK_443X), | ||
2669 | CLK("i2c_omap.2", "ick", &i2c2_ck, CK_443X), | ||
2670 | CLK("i2c_omap.3", "ick", &i2c3_ck, CK_443X), | ||
2671 | CLK("i2c_omap.4", "ick", &i2c4_ck, CK_443X), | ||
2672 | CLK(NULL, "iss_ck", &iss_ck, CK_443X), | ||
2673 | CLK(NULL, "ivahd_ck", &ivahd_ck, CK_443X), | ||
2674 | CLK(NULL, "keyboard_ck", &keyboard_ck, CK_443X), | ||
2675 | CLK(NULL, "l3_instr_interconnect_ck", &l3_instr_interconnect_ck, CK_443X), | ||
2676 | CLK(NULL, "l3_interconnect_3_ck", &l3_interconnect_3_ck, CK_443X), | ||
2677 | CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck, CK_443X), | ||
2678 | CLK(NULL, "mcasp_ck", &mcasp_ck, CK_443X), | ||
2679 | CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck, CK_443X), | ||
2680 | CLK("omap-mcbsp.1", "fck", &mcbsp1_ck, CK_443X), | ||
2681 | CLK(NULL, "mcbsp2_sync_mux_ck", &mcbsp2_sync_mux_ck, CK_443X), | ||
2682 | CLK("omap-mcbsp.2", "fck", &mcbsp2_ck, CK_443X), | ||
2683 | CLK(NULL, "mcbsp3_sync_mux_ck", &mcbsp3_sync_mux_ck, CK_443X), | ||
2684 | CLK("omap-mcbsp.3", "fck", &mcbsp3_ck, CK_443X), | ||
2685 | CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck, CK_443X), | ||
2686 | CLK("omap-mcbsp.4", "fck", &mcbsp4_ck, CK_443X), | ||
2687 | CLK("omap2_mcspi.1", "fck", &mcspi1_ck, CK_443X), | ||
2688 | CLK("omap2_mcspi.2", "fck", &mcspi2_ck, CK_443X), | ||
2689 | CLK("omap2_mcspi.3", "fck", &mcspi3_ck, CK_443X), | ||
2690 | CLK("omap2_mcspi.4", "fck", &mcspi4_ck, CK_443X), | ||
2691 | CLK("mmci-omap-hs.0", "fck", &mmc1_ck, CK_443X), | ||
2692 | CLK("mmci-omap-hs.1", "fck", &mmc2_ck, CK_443X), | ||
2693 | CLK("mmci-omap-hs.2", "fck", &mmc3_ck, CK_443X), | ||
2694 | CLK("mmci-omap-hs.3", "fck", &mmc4_ck, CK_443X), | ||
2695 | CLK("mmci-omap-hs.4", "fck", &mmc5_ck, CK_443X), | ||
2696 | CLK(NULL, "ocp_wp1_ck", &ocp_wp1_ck, CK_443X), | ||
2697 | CLK(NULL, "pdm_ck", &pdm_ck, CK_443X), | ||
2698 | CLK(NULL, "pkaeip29_ck", &pkaeip29_ck, CK_443X), | ||
2699 | CLK("omap_rng", "ick", &rng_ck, CK_443X), | ||
2700 | CLK(NULL, "sha2md51_ck", &sha2md51_ck, CK_443X), | ||
2701 | CLK(NULL, "sl2_ck", &sl2_ck, CK_443X), | ||
2702 | CLK(NULL, "slimbus1_ck", &slimbus1_ck, CK_443X), | ||
2703 | CLK(NULL, "slimbus2_ck", &slimbus2_ck, CK_443X), | ||
2704 | CLK(NULL, "sr_core_ck", &sr_core_ck, CK_443X), | ||
2705 | CLK(NULL, "sr_iva_ck", &sr_iva_ck, CK_443X), | ||
2706 | CLK(NULL, "sr_mpu_ck", &sr_mpu_ck, CK_443X), | ||
2707 | CLK(NULL, "tesla_ck", &tesla_ck, CK_443X), | ||
2708 | CLK(NULL, "uart1_ck", &uart1_ck, CK_443X), | ||
2709 | CLK(NULL, "uart2_ck", &uart2_ck, CK_443X), | ||
2710 | CLK(NULL, "uart3_ck", &uart3_ck, CK_443X), | ||
2711 | CLK(NULL, "uart4_ck", &uart4_ck, CK_443X), | ||
2712 | CLK(NULL, "unipro1_ck", &unipro1_ck, CK_443X), | ||
2713 | CLK(NULL, "usb_host_ck", &usb_host_ck, CK_443X), | ||
2714 | CLK(NULL, "usb_host_fs_ck", &usb_host_fs_ck, CK_443X), | ||
2715 | CLK("musb_hdrc", "ick", &usb_otg_ck, CK_443X), | ||
2716 | CLK(NULL, "usb_tll_ck", &usb_tll_ck, CK_443X), | ||
2717 | CLK(NULL, "usbphyocp2scp_ck", &usbphyocp2scp_ck, CK_443X), | ||
2718 | CLK(NULL, "usim_ck", &usim_ck, CK_443X), | ||
2719 | CLK("omap_wdt", "fck", &wdt2_ck, CK_443X), | ||
2720 | CLK(NULL, "wdt3_ck", &wdt3_ck, CK_443X), | ||
2721 | CLK(NULL, "otg_60m_gfclk_ck", &otg_60m_gfclk_ck, CK_443X), | ||
2722 | CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X), | ||
2723 | CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X), | ||
2724 | CLK(NULL, "usim_fclk", &usim_fclk, CK_443X), | ||
2725 | CLK(NULL, "utmi_p1_gfclk_ck", &utmi_p1_gfclk_ck, CK_443X), | ||
2726 | CLK(NULL, "utmi_p2_gfclk_ck", &utmi_p2_gfclk_ck, CK_443X), | ||
2727 | }; | ||
2728 | |||
2729 | int __init omap2_clk_init(void) | ||
2730 | { | ||
2731 | /* struct prcm_config *prcm; */ | ||
2732 | struct omap_clk *c; | ||
2733 | /* u32 clkrate; */ | ||
2734 | u32 cpu_clkflg; | ||
2735 | |||
2736 | if (cpu_is_omap44xx()) { | ||
2737 | cpu_mask = RATE_IN_4430; | ||
2738 | cpu_clkflg = CK_443X; | ||
2739 | } | ||
2740 | |||
2741 | clk_init(&omap2_clk_functions); | ||
2742 | |||
2743 | for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks); | ||
2744 | c++) | ||
2745 | clk_preinit(c->lk.clk); | ||
2746 | |||
2747 | for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks); | ||
2748 | c++) | ||
2749 | if (c->cpu & cpu_clkflg) { | ||
2750 | clkdev_add(&c->lk); | ||
2751 | clk_register(c->lk.clk); | ||
2752 | /* TODO | ||
2753 | omap2_init_clk_clkdm(c->lk.clk); | ||
2754 | */ | ||
2755 | } | ||
2756 | |||
2757 | recalculate_root_clocks(); | ||
2758 | |||
2759 | /* | ||
2760 | * Only enable those clocks we will need, let the drivers | ||
2761 | * enable other clocks as necessary | ||
2762 | */ | ||
2763 | clk_enable_init_clocks(); | ||
2764 | |||
2765 | return 0; | ||
2766 | } | ||
diff --git a/arch/arm/mach-omap2/clock_common_data.c b/arch/arm/mach-omap2/clock_common_data.c new file mode 100644 index 000000000000..f69096b88cdb --- /dev/null +++ b/arch/arm/mach-omap2/clock_common_data.c | |||
@@ -0,0 +1,39 @@ | |||
1 | /* | ||
2 | * linux/arch/arm/mach-omap2/clock_common_data.c | ||
3 | * | ||
4 | * Copyright (C) 2005-2009 Texas Instruments, Inc. | ||
5 | * Copyright (C) 2004-2009 Nokia Corporation | ||
6 | * | ||
7 | * Contacts: | ||
8 | * Richard Woodruff <r-woodruff2@ti.com> | ||
9 | * Paul Walmsley | ||
10 | * | ||
11 | * This program is free software; you can redistribute it and/or modify | ||
12 | * it under the terms of the GNU General Public License version 2 as | ||
13 | * published by the Free Software Foundation. | ||
14 | * | ||
15 | * This file contains clock data that is common to both the OMAP2xxx and | ||
16 | * OMAP3xxx clock definition files. | ||
17 | */ | ||
18 | |||
19 | #include "clock.h" | ||
20 | |||
21 | /* clksel_rate data common to 24xx/343x */ | ||
22 | const struct clksel_rate gpt_32k_rates[] = { | ||
23 | { .div = 1, .val = 0, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE }, | ||
24 | { .div = 0 } | ||
25 | }; | ||
26 | |||
27 | const struct clksel_rate gpt_sys_rates[] = { | ||
28 | { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE }, | ||
29 | { .div = 0 } | ||
30 | }; | ||
31 | |||
32 | const struct clksel_rate gfx_l3_rates[] = { | ||
33 | { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_343X }, | ||
34 | { .div = 2, .val = 2, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE }, | ||
35 | { .div = 3, .val = 3, .flags = RATE_IN_243X | RATE_IN_343X }, | ||
36 | { .div = 4, .val = 4, .flags = RATE_IN_243X | RATE_IN_343X }, | ||
37 | { .div = 0 } | ||
38 | }; | ||
39 | |||
diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c index fcd82320a6a3..1a45ed1e8ba1 100644 --- a/arch/arm/mach-omap2/clockdomain.c +++ b/arch/arm/mach-omap2/clockdomain.c | |||
@@ -2,7 +2,7 @@ | |||
2 | * OMAP2/3 clockdomain framework functions | 2 | * OMAP2/3 clockdomain framework functions |
3 | * | 3 | * |
4 | * Copyright (C) 2008 Texas Instruments, Inc. | 4 | * Copyright (C) 2008 Texas Instruments, Inc. |
5 | * Copyright (C) 2008 Nokia Corporation | 5 | * Copyright (C) 2008-2009 Nokia Corporation |
6 | * | 6 | * |
7 | * Written by Paul Walmsley and Jouni Högander | 7 | * Written by Paul Walmsley and Jouni Högander |
8 | * | 8 | * |
@@ -10,9 +10,7 @@ | |||
10 | * it under the terms of the GNU General Public License version 2 as | 10 | * it under the terms of the GNU General Public License version 2 as |
11 | * published by the Free Software Foundation. | 11 | * published by the Free Software Foundation. |
12 | */ | 12 | */ |
13 | #ifdef CONFIG_OMAP_DEBUG_CLOCKDOMAIN | 13 | #undef DEBUG |
14 | # define DEBUG | ||
15 | #endif | ||
16 | 14 | ||
17 | #include <linux/module.h> | 15 | #include <linux/module.h> |
18 | #include <linux/kernel.h> | 16 | #include <linux/kernel.h> |
diff --git a/arch/arm/mach-omap2/cm-regbits-44xx.h b/arch/arm/mach-omap2/cm-regbits-44xx.h new file mode 100644 index 000000000000..0e67f75aa35c --- /dev/null +++ b/arch/arm/mach-omap2/cm-regbits-44xx.h | |||
@@ -0,0 +1,1474 @@ | |||
1 | /* | ||
2 | * OMAP44xx Clock Management register bits | ||
3 | * | ||
4 | * Copyright (C) 2009 Texas Instruments, Inc. | ||
5 | * Copyright (C) 2009 Nokia Corporation | ||
6 | * | ||
7 | * Paul Walmsley (paul@pwsan.com) | ||
8 | * Rajendra Nayak (rnayak@ti.com) | ||
9 | * Benoit Cousson (b-cousson@ti.com) | ||
10 | * | ||
11 | * This file is automatically generated from the OMAP hardware databases. | ||
12 | * We respectfully ask that any modifications to this file be coordinated | ||
13 | * with the public linux-omap@vger.kernel.org mailing list and the | ||
14 | * authors above to ensure that the autogeneration scripts are kept | ||
15 | * up-to-date with the file contents. | ||
16 | * | ||
17 | * This program is free software; you can redistribute it and/or modify | ||
18 | * it under the terms of the GNU General Public License version 2 as | ||
19 | * published by the Free Software Foundation. | ||
20 | */ | ||
21 | |||
22 | #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H | ||
23 | #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H | ||
24 | |||
25 | #include "cm.h" | ||
26 | |||
27 | |||
28 | /* Used by CM_L3_1_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP */ | ||
29 | #define OMAP4430_ABE_DYNDEP_SHIFT (1 << 3) | ||
30 | #define OMAP4430_ABE_DYNDEP_MASK BITFIELD(3, 3) | ||
31 | |||
32 | /* | ||
33 | * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, | ||
34 | * CM_L3INIT_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP, | ||
35 | * CM_TESLA_STATICDEP | ||
36 | */ | ||
37 | #define OMAP4430_ABE_STATDEP_SHIFT (1 << 3) | ||
38 | #define OMAP4430_ABE_STATDEP_MASK BITFIELD(3, 3) | ||
39 | |||
40 | /* Used by CM_L4CFG_DYNAMICDEP */ | ||
41 | #define OMAP4430_ALWONCORE_DYNDEP_SHIFT (1 << 16) | ||
42 | #define OMAP4430_ALWONCORE_DYNDEP_MASK BITFIELD(16, 16) | ||
43 | |||
44 | /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */ | ||
45 | #define OMAP4430_ALWONCORE_STATDEP_SHIFT (1 << 16) | ||
46 | #define OMAP4430_ALWONCORE_STATDEP_MASK BITFIELD(16, 16) | ||
47 | |||
48 | /* | ||
49 | * Used by CM_AUTOIDLE_DPLL_PER, CM_AUTOIDLE_DPLL_UNIPRO, CM_AUTOIDLE_DPLL_USB, | ||
50 | * CM_AUTOIDLE_DPLL_CORE_RESTORE, CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE, | ||
51 | * CM_AUTOIDLE_DPLL_DDRPHY, CM_AUTOIDLE_DPLL_IVA, CM_AUTOIDLE_DPLL_MPU | ||
52 | */ | ||
53 | #define OMAP4430_AUTO_DPLL_MODE_SHIFT (1 << 0) | ||
54 | #define OMAP4430_AUTO_DPLL_MODE_MASK BITFIELD(0, 2) | ||
55 | |||
56 | /* Used by CM_L4CFG_DYNAMICDEP */ | ||
57 | #define OMAP4430_CEFUSE_DYNDEP_SHIFT (1 << 17) | ||
58 | #define OMAP4430_CEFUSE_DYNDEP_MASK BITFIELD(17, 17) | ||
59 | |||
60 | /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */ | ||
61 | #define OMAP4430_CEFUSE_STATDEP_SHIFT (1 << 17) | ||
62 | #define OMAP4430_CEFUSE_STATDEP_MASK BITFIELD(17, 17) | ||
63 | |||
64 | /* Used by CM1_ABE_CLKSTCTRL */ | ||
65 | #define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_SHIFT (1 << 13) | ||
66 | #define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_MASK BITFIELD(13, 13) | ||
67 | |||
68 | /* Used by CM1_ABE_CLKSTCTRL */ | ||
69 | #define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_SHIFT (1 << 12) | ||
70 | #define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_MASK BITFIELD(12, 12) | ||
71 | |||
72 | /* Used by CM_WKUP_CLKSTCTRL */ | ||
73 | #define OMAP4430_CLKACTIVITY_ABE_LP_CLK_SHIFT (1 << 9) | ||
74 | #define OMAP4430_CLKACTIVITY_ABE_LP_CLK_MASK BITFIELD(9, 9) | ||
75 | |||
76 | /* Used by CM1_ABE_CLKSTCTRL */ | ||
77 | #define OMAP4430_CLKACTIVITY_ABE_SYSCLK_SHIFT (1 << 11) | ||
78 | #define OMAP4430_CLKACTIVITY_ABE_SYSCLK_MASK BITFIELD(11, 11) | ||
79 | |||
80 | /* Used by CM1_ABE_CLKSTCTRL */ | ||
81 | #define OMAP4430_CLKACTIVITY_ABE_X2_CLK_SHIFT (1 << 8) | ||
82 | #define OMAP4430_CLKACTIVITY_ABE_X2_CLK_MASK BITFIELD(8, 8) | ||
83 | |||
84 | /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ | ||
85 | #define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_SHIFT (1 << 11) | ||
86 | #define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_MASK BITFIELD(11, 11) | ||
87 | |||
88 | /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ | ||
89 | #define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_SHIFT (1 << 12) | ||
90 | #define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_MASK BITFIELD(12, 12) | ||
91 | |||
92 | /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ | ||
93 | #define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_SHIFT (1 << 13) | ||
94 | #define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_MASK BITFIELD(13, 13) | ||
95 | |||
96 | /* Used by CM_CAM_CLKSTCTRL */ | ||
97 | #define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_SHIFT (1 << 9) | ||
98 | #define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_MASK BITFIELD(9, 9) | ||
99 | |||
100 | /* Used by CM_EMU_CLKSTCTRL */ | ||
101 | #define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_SHIFT (1 << 9) | ||
102 | #define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_MASK BITFIELD(9, 9) | ||
103 | |||
104 | /* Used by CM_CEFUSE_CLKSTCTRL */ | ||
105 | #define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT (1 << 9) | ||
106 | #define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK BITFIELD(9, 9) | ||
107 | |||
108 | /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ | ||
109 | #define OMAP4430_CLKACTIVITY_DLL_CLK_SHIFT (1 << 9) | ||
110 | #define OMAP4430_CLKACTIVITY_DLL_CLK_MASK BITFIELD(9, 9) | ||
111 | |||
112 | /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ | ||
113 | #define OMAP4430_CLKACTIVITY_DMT10_GFCLK_SHIFT (1 << 9) | ||
114 | #define OMAP4430_CLKACTIVITY_DMT10_GFCLK_MASK BITFIELD(9, 9) | ||
115 | |||
116 | /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ | ||
117 | #define OMAP4430_CLKACTIVITY_DMT11_GFCLK_SHIFT (1 << 10) | ||
118 | #define OMAP4430_CLKACTIVITY_DMT11_GFCLK_MASK BITFIELD(10, 10) | ||
119 | |||
120 | /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ | ||
121 | #define OMAP4430_CLKACTIVITY_DMT2_GFCLK_SHIFT (1 << 11) | ||
122 | #define OMAP4430_CLKACTIVITY_DMT2_GFCLK_MASK BITFIELD(11, 11) | ||
123 | |||
124 | /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ | ||
125 | #define OMAP4430_CLKACTIVITY_DMT3_GFCLK_SHIFT (1 << 12) | ||
126 | #define OMAP4430_CLKACTIVITY_DMT3_GFCLK_MASK BITFIELD(12, 12) | ||
127 | |||
128 | /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ | ||
129 | #define OMAP4430_CLKACTIVITY_DMT4_GFCLK_SHIFT (1 << 13) | ||
130 | #define OMAP4430_CLKACTIVITY_DMT4_GFCLK_MASK BITFIELD(13, 13) | ||
131 | |||
132 | /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ | ||
133 | #define OMAP4430_CLKACTIVITY_DMT9_GFCLK_SHIFT (1 << 14) | ||
134 | #define OMAP4430_CLKACTIVITY_DMT9_GFCLK_MASK BITFIELD(14, 14) | ||
135 | |||
136 | /* Used by CM_DSS_CLKSTCTRL */ | ||
137 | #define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_SHIFT (1 << 10) | ||
138 | #define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_MASK BITFIELD(10, 10) | ||
139 | |||
140 | /* Used by CM_DSS_CLKSTCTRL */ | ||
141 | #define OMAP4430_CLKACTIVITY_DSS_FCLK_SHIFT (1 << 9) | ||
142 | #define OMAP4430_CLKACTIVITY_DSS_FCLK_MASK BITFIELD(9, 9) | ||
143 | |||
144 | /* Used by CM_DUCATI_CLKSTCTRL */ | ||
145 | #define OMAP4430_CLKACTIVITY_DUCATI_GCLK_SHIFT (1 << 8) | ||
146 | #define OMAP4430_CLKACTIVITY_DUCATI_GCLK_MASK BITFIELD(8, 8) | ||
147 | |||
148 | /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ | ||
149 | #define OMAP4430_CLKACTIVITY_EMAC_50MHZ_CLK_SHIFT (1 << 10) | ||
150 | #define OMAP4430_CLKACTIVITY_EMAC_50MHZ_CLK_MASK BITFIELD(10, 10) | ||
151 | |||
152 | /* Used by CM_EMU_CLKSTCTRL */ | ||
153 | #define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_SHIFT (1 << 8) | ||
154 | #define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_MASK BITFIELD(8, 8) | ||
155 | |||
156 | /* Used by CM_CAM_CLKSTCTRL */ | ||
157 | #define OMAP4430_CLKACTIVITY_FDIF_GFCLK_SHIFT (1 << 10) | ||
158 | #define OMAP4430_CLKACTIVITY_FDIF_GFCLK_MASK BITFIELD(10, 10) | ||
159 | |||
160 | /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ | ||
161 | #define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_SHIFT (1 << 15) | ||
162 | #define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_MASK BITFIELD(15, 15) | ||
163 | |||
164 | /* Used by CM1_ABE_CLKSTCTRL */ | ||
165 | #define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_SHIFT (1 << 10) | ||
166 | #define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_MASK BITFIELD(10, 10) | ||
167 | |||
168 | /* Used by CM_DSS_CLKSTCTRL */ | ||
169 | #define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_SHIFT (1 << 11) | ||
170 | #define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_MASK BITFIELD(11, 11) | ||
171 | |||
172 | /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ | ||
173 | #define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT (1 << 20) | ||
174 | #define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK BITFIELD(20, 20) | ||
175 | |||
176 | /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ | ||
177 | #define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT (1 << 26) | ||
178 | #define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_MASK BITFIELD(26, 26) | ||
179 | |||
180 | /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ | ||
181 | #define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT (1 << 21) | ||
182 | #define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK BITFIELD(21, 21) | ||
183 | |||
184 | /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ | ||
185 | #define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT (1 << 27) | ||
186 | #define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_MASK BITFIELD(27, 27) | ||
187 | |||
188 | /* Used by CM_L3INIT_CLKSTCTRL */ | ||
189 | #define OMAP4430_CLKACTIVITY_INIT_32K_GFCLK_SHIFT (1 << 31) | ||
190 | #define OMAP4430_CLKACTIVITY_INIT_32K_GFCLK_MASK BITFIELD(31, 31) | ||
191 | |||
192 | /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ | ||
193 | #define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_SHIFT (1 << 13) | ||
194 | #define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_MASK BITFIELD(13, 13) | ||
195 | |||
196 | /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ | ||
197 | #define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_SHIFT (1 << 12) | ||
198 | #define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_MASK BITFIELD(12, 12) | ||
199 | |||
200 | /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ | ||
201 | #define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_SHIFT (1 << 28) | ||
202 | #define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_MASK BITFIELD(28, 28) | ||
203 | |||
204 | /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ | ||
205 | #define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_SHIFT (1 << 29) | ||
206 | #define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_MASK BITFIELD(29, 29) | ||
207 | |||
208 | /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ | ||
209 | #define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_SHIFT (1 << 11) | ||
210 | #define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_MASK BITFIELD(11, 11) | ||
211 | |||
212 | /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ | ||
213 | #define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_SHIFT (1 << 16) | ||
214 | #define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_MASK BITFIELD(16, 16) | ||
215 | |||
216 | /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ | ||
217 | #define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_SHIFT (1 << 17) | ||
218 | #define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_MASK BITFIELD(17, 17) | ||
219 | |||
220 | /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ | ||
221 | #define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_SHIFT (1 << 18) | ||
222 | #define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_MASK BITFIELD(18, 18) | ||
223 | |||
224 | /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ | ||
225 | #define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_SHIFT (1 << 19) | ||
226 | #define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_MASK BITFIELD(19, 19) | ||
227 | |||
228 | /* Used by CM_CAM_CLKSTCTRL */ | ||
229 | #define OMAP4430_CLKACTIVITY_ISS_GCLK_SHIFT (1 << 8) | ||
230 | #define OMAP4430_CLKACTIVITY_ISS_GCLK_MASK BITFIELD(8, 8) | ||
231 | |||
232 | /* Used by CM_IVAHD_CLKSTCTRL */ | ||
233 | #define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_SHIFT (1 << 8) | ||
234 | #define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_MASK BITFIELD(8, 8) | ||
235 | |||
236 | /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ | ||
237 | #define OMAP4430_CLKACTIVITY_L3INIT_DPLL_ALWON_CLK_SHIFT (1 << 14) | ||
238 | #define OMAP4430_CLKACTIVITY_L3INIT_DPLL_ALWON_CLK_MASK BITFIELD(14, 14) | ||
239 | |||
240 | /* Used by CM_L3_1_CLKSTCTRL, CM_L3_1_CLKSTCTRL_RESTORE */ | ||
241 | #define OMAP4430_CLKACTIVITY_L3_1_GICLK_SHIFT (1 << 8) | ||
242 | #define OMAP4430_CLKACTIVITY_L3_1_GICLK_MASK BITFIELD(8, 8) | ||
243 | |||
244 | /* Used by CM_L3_2_CLKSTCTRL, CM_L3_2_CLKSTCTRL_RESTORE */ | ||
245 | #define OMAP4430_CLKACTIVITY_L3_2_GICLK_SHIFT (1 << 8) | ||
246 | #define OMAP4430_CLKACTIVITY_L3_2_GICLK_MASK BITFIELD(8, 8) | ||
247 | |||
248 | /* Used by CM_D2D_CLKSTCTRL */ | ||
249 | #define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_SHIFT (1 << 8) | ||
250 | #define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_MASK BITFIELD(8, 8) | ||
251 | |||
252 | /* Used by CM_SDMA_CLKSTCTRL */ | ||
253 | #define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_SHIFT (1 << 8) | ||
254 | #define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_MASK BITFIELD(8, 8) | ||
255 | |||
256 | /* Used by CM_DSS_CLKSTCTRL */ | ||
257 | #define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_SHIFT (1 << 8) | ||
258 | #define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_MASK BITFIELD(8, 8) | ||
259 | |||
260 | /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ | ||
261 | #define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_SHIFT (1 << 8) | ||
262 | #define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_MASK BITFIELD(8, 8) | ||
263 | |||
264 | /* Used by CM_GFX_CLKSTCTRL */ | ||
265 | #define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_SHIFT (1 << 8) | ||
266 | #define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_MASK BITFIELD(8, 8) | ||
267 | |||
268 | /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ | ||
269 | #define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_SHIFT (1 << 8) | ||
270 | #define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_MASK BITFIELD(8, 8) | ||
271 | |||
272 | /* Used by CM_L3INSTR_CLKSTCTRL */ | ||
273 | #define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_SHIFT (1 << 8) | ||
274 | #define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_MASK BITFIELD(8, 8) | ||
275 | |||
276 | /* Used by CM_L4SEC_CLKSTCTRL */ | ||
277 | #define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_SHIFT (1 << 8) | ||
278 | #define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_MASK BITFIELD(8, 8) | ||
279 | |||
280 | /* Used by CM_ALWON_CLKSTCTRL */ | ||
281 | #define OMAP4430_CLKACTIVITY_L4_AO_ICLK_SHIFT (1 << 8) | ||
282 | #define OMAP4430_CLKACTIVITY_L4_AO_ICLK_MASK BITFIELD(8, 8) | ||
283 | |||
284 | /* Used by CM_CEFUSE_CLKSTCTRL */ | ||
285 | #define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT (1 << 8) | ||
286 | #define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_MASK BITFIELD(8, 8) | ||
287 | |||
288 | /* Used by CM_L4CFG_CLKSTCTRL, CM_L4CFG_CLKSTCTRL_RESTORE */ | ||
289 | #define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_SHIFT (1 << 8) | ||
290 | #define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_MASK BITFIELD(8, 8) | ||
291 | |||
292 | /* Used by CM_D2D_CLKSTCTRL */ | ||
293 | #define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_SHIFT (1 << 9) | ||
294 | #define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_MASK BITFIELD(9, 9) | ||
295 | |||
296 | /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ | ||
297 | #define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_SHIFT (1 << 9) | ||
298 | #define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_MASK BITFIELD(9, 9) | ||
299 | |||
300 | /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ | ||
301 | #define OMAP4430_CLKACTIVITY_L4_PER_GICLK_SHIFT (1 << 8) | ||
302 | #define OMAP4430_CLKACTIVITY_L4_PER_GICLK_MASK BITFIELD(8, 8) | ||
303 | |||
304 | /* Used by CM_L4SEC_CLKSTCTRL */ | ||
305 | #define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_SHIFT (1 << 9) | ||
306 | #define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_MASK BITFIELD(9, 9) | ||
307 | |||
308 | /* Used by CM_WKUP_CLKSTCTRL */ | ||
309 | #define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_SHIFT (1 << 12) | ||
310 | #define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_MASK BITFIELD(12, 12) | ||
311 | |||
312 | /* Used by CM_MPU_CLKSTCTRL, CM_MPU_CLKSTCTRL_RESTORE */ | ||
313 | #define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_SHIFT (1 << 8) | ||
314 | #define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_MASK BITFIELD(8, 8) | ||
315 | |||
316 | /* Used by CM1_ABE_CLKSTCTRL */ | ||
317 | #define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_SHIFT (1 << 9) | ||
318 | #define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_MASK BITFIELD(9, 9) | ||
319 | |||
320 | /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ | ||
321 | #define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_SHIFT (1 << 16) | ||
322 | #define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_MASK BITFIELD(16, 16) | ||
323 | |||
324 | /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ | ||
325 | #define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_SHIFT (1 << 17) | ||
326 | #define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_MASK BITFIELD(17, 17) | ||
327 | |||
328 | /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ | ||
329 | #define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_SHIFT (1 << 18) | ||
330 | #define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_MASK BITFIELD(18, 18) | ||
331 | |||
332 | /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ | ||
333 | #define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_SHIFT (1 << 19) | ||
334 | #define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_MASK BITFIELD(19, 19) | ||
335 | |||
336 | /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ | ||
337 | #define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_SHIFT (1 << 25) | ||
338 | #define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_MASK BITFIELD(25, 25) | ||
339 | |||
340 | /* Used by CM_EMU_CLKSTCTRL */ | ||
341 | #define OMAP4430_CLKACTIVITY_PER_DPLL_EMU_CLK_SHIFT (1 << 10) | ||
342 | #define OMAP4430_CLKACTIVITY_PER_DPLL_EMU_CLK_MASK BITFIELD(10, 10) | ||
343 | |||
344 | /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ | ||
345 | #define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_SHIFT (1 << 20) | ||
346 | #define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_MASK BITFIELD(20, 20) | ||
347 | |||
348 | /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ | ||
349 | #define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_SHIFT (1 << 21) | ||
350 | #define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_MASK BITFIELD(21, 21) | ||
351 | |||
352 | /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ | ||
353 | #define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_SHIFT (1 << 22) | ||
354 | #define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_MASK BITFIELD(22, 22) | ||
355 | |||
356 | /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ | ||
357 | #define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_SHIFT (1 << 24) | ||
358 | #define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_MASK BITFIELD(24, 24) | ||
359 | |||
360 | /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ | ||
361 | #define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_SHIFT (1 << 10) | ||
362 | #define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_MASK BITFIELD(10, 10) | ||
363 | |||
364 | /* Used by CM_GFX_CLKSTCTRL */ | ||
365 | #define OMAP4430_CLKACTIVITY_SGX_GFCLK_SHIFT (1 << 9) | ||
366 | #define OMAP4430_CLKACTIVITY_SGX_GFCLK_MASK BITFIELD(9, 9) | ||
367 | |||
368 | /* Used by CM_ALWON_CLKSTCTRL */ | ||
369 | #define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_SHIFT (1 << 11) | ||
370 | #define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_MASK BITFIELD(11, 11) | ||
371 | |||
372 | /* Used by CM_ALWON_CLKSTCTRL */ | ||
373 | #define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_SHIFT (1 << 10) | ||
374 | #define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_MASK BITFIELD(10, 10) | ||
375 | |||
376 | /* Used by CM_ALWON_CLKSTCTRL */ | ||
377 | #define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_SHIFT (1 << 9) | ||
378 | #define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_MASK BITFIELD(9, 9) | ||
379 | |||
380 | /* Used by CM_WKUP_CLKSTCTRL */ | ||
381 | #define OMAP4430_CLKACTIVITY_SYS_CLK_SHIFT (1 << 8) | ||
382 | #define OMAP4430_CLKACTIVITY_SYS_CLK_MASK BITFIELD(8, 8) | ||
383 | |||
384 | /* Used by CM_TESLA_CLKSTCTRL */ | ||
385 | #define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_SHIFT (1 << 8) | ||
386 | #define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_MASK BITFIELD(8, 8) | ||
387 | |||
388 | /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ | ||
389 | #define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT (1 << 22) | ||
390 | #define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_MASK BITFIELD(22, 22) | ||
391 | |||
392 | /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ | ||
393 | #define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT (1 << 23) | ||
394 | #define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_MASK BITFIELD(23, 23) | ||
395 | |||
396 | /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ | ||
397 | #define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT (1 << 24) | ||
398 | #define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_MASK BITFIELD(24, 24) | ||
399 | |||
400 | /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ | ||
401 | #define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT (1 << 15) | ||
402 | #define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_MASK BITFIELD(15, 15) | ||
403 | |||
404 | /* Used by CM_WKUP_CLKSTCTRL */ | ||
405 | #define OMAP4430_CLKACTIVITY_USIM_GFCLK_SHIFT (1 << 10) | ||
406 | #define OMAP4430_CLKACTIVITY_USIM_GFCLK_MASK BITFIELD(10, 10) | ||
407 | |||
408 | /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ | ||
409 | #define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT (1 << 30) | ||
410 | #define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_MASK BITFIELD(30, 30) | ||
411 | |||
412 | /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ | ||
413 | #define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT (1 << 25) | ||
414 | #define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK BITFIELD(25, 25) | ||
415 | |||
416 | /* Used by CM_WKUP_CLKSTCTRL */ | ||
417 | #define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_SHIFT (1 << 11) | ||
418 | #define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_MASK BITFIELD(11, 11) | ||
419 | |||
420 | /* | ||
421 | * Used by CM_WKUP_TIMER1_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL, | ||
422 | * CM_L4PER_DMTIMER11_CLKCTRL, CM_L4PER_DMTIMER2_CLKCTRL, | ||
423 | * CM_L4PER_DMTIMER3_CLKCTRL, CM_L4PER_DMTIMER4_CLKCTRL, | ||
424 | * CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL, | ||
425 | * CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_MMC6_CLKCTRL, | ||
426 | * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, | ||
427 | * CM1_ABE_TIMER8_CLKCTRL | ||
428 | */ | ||
429 | #define OMAP4430_CLKSEL_SHIFT (1 << 24) | ||
430 | #define OMAP4430_CLKSEL_MASK BITFIELD(24, 24) | ||
431 | |||
432 | /* | ||
433 | * Renamed from CLKSEL Used by CM_ABE_DSS_SYS_CLKSEL, CM_ABE_PLL_REF_CLKSEL, | ||
434 | * CM_DPLL_SYS_REF_CLKSEL, CM_L4_WKUP_CLKSEL, CM_CLKSEL_DUCATI_ISS_ROOT, | ||
435 | * CM_CLKSEL_USB_60MHZ | ||
436 | */ | ||
437 | #define OMAP4430_CLKSEL_0_0_SHIFT (1 << 0) | ||
438 | #define OMAP4430_CLKSEL_0_0_MASK BITFIELD(0, 0) | ||
439 | |||
440 | /* Renamed from CLKSEL Used by CM_BYPCLK_DPLL_IVA, CM_BYPCLK_DPLL_MPU */ | ||
441 | #define OMAP4430_CLKSEL_0_1_SHIFT (1 << 0) | ||
442 | #define OMAP4430_CLKSEL_0_1_MASK BITFIELD(0, 1) | ||
443 | |||
444 | /* Renamed from CLKSEL Used by CM_L3INIT_HSI_CLKCTRL */ | ||
445 | #define OMAP4430_CLKSEL_24_25_SHIFT (1 << 24) | ||
446 | #define OMAP4430_CLKSEL_24_25_MASK BITFIELD(24, 25) | ||
447 | |||
448 | /* Used by CM_L3INIT_USB_OTG_CLKCTRL */ | ||
449 | #define OMAP4430_CLKSEL_60M_SHIFT (1 << 24) | ||
450 | #define OMAP4430_CLKSEL_60M_MASK BITFIELD(24, 24) | ||
451 | |||
452 | /* Used by CM1_ABE_AESS_CLKCTRL */ | ||
453 | #define OMAP4430_CLKSEL_AESS_FCLK_SHIFT (1 << 24) | ||
454 | #define OMAP4430_CLKSEL_AESS_FCLK_MASK BITFIELD(24, 24) | ||
455 | |||
456 | /* Used by CM_CLKSEL_CORE_RESTORE, CM_CLKSEL_CORE */ | ||
457 | #define OMAP4430_CLKSEL_CORE_SHIFT (1 << 0) | ||
458 | #define OMAP4430_CLKSEL_CORE_MASK BITFIELD(0, 0) | ||
459 | |||
460 | /* Renamed from CLKSEL_CORE Used by CM_SHADOW_FREQ_CONFIG2 */ | ||
461 | #define OMAP4430_CLKSEL_CORE_1_1_SHIFT (1 << 1) | ||
462 | #define OMAP4430_CLKSEL_CORE_1_1_MASK BITFIELD(1, 1) | ||
463 | |||
464 | /* Used by CM_WKUP_USIM_CLKCTRL */ | ||
465 | #define OMAP4430_CLKSEL_DIV_SHIFT (1 << 24) | ||
466 | #define OMAP4430_CLKSEL_DIV_MASK BITFIELD(24, 24) | ||
467 | |||
468 | /* Used by CM_CAM_FDIF_CLKCTRL */ | ||
469 | #define OMAP4430_CLKSEL_FCLK_SHIFT (1 << 24) | ||
470 | #define OMAP4430_CLKSEL_FCLK_MASK BITFIELD(24, 25) | ||
471 | |||
472 | /* Used by CM_L4PER_MCBSP4_CLKCTRL */ | ||
473 | #define OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT (1 << 25) | ||
474 | #define OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK BITFIELD(25, 25) | ||
475 | |||
476 | /* | ||
477 | * Renamed from CLKSEL_INTERNAL_SOURCE Used by CM1_ABE_DMIC_CLKCTRL, | ||
478 | * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL, | ||
479 | * CM1_ABE_MCBSP3_CLKCTRL | ||
480 | */ | ||
481 | #define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_SHIFT (1 << 26) | ||
482 | #define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_MASK BITFIELD(26, 27) | ||
483 | |||
484 | /* Used by CM_CLKSEL_CORE_RESTORE, CM_CLKSEL_CORE */ | ||
485 | #define OMAP4430_CLKSEL_L3_SHIFT (1 << 4) | ||
486 | #define OMAP4430_CLKSEL_L3_MASK BITFIELD(4, 4) | ||
487 | |||
488 | /* Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2 */ | ||
489 | #define OMAP4430_CLKSEL_L3_SHADOW_SHIFT (1 << 2) | ||
490 | #define OMAP4430_CLKSEL_L3_SHADOW_MASK BITFIELD(2, 2) | ||
491 | |||
492 | /* Used by CM_CLKSEL_CORE_RESTORE, CM_CLKSEL_CORE */ | ||
493 | #define OMAP4430_CLKSEL_L4_SHIFT (1 << 8) | ||
494 | #define OMAP4430_CLKSEL_L4_MASK BITFIELD(8, 8) | ||
495 | |||
496 | /* Used by CM_CLKSEL_ABE */ | ||
497 | #define OMAP4430_CLKSEL_OPP_SHIFT (1 << 0) | ||
498 | #define OMAP4430_CLKSEL_OPP_MASK BITFIELD(0, 1) | ||
499 | |||
500 | /* Used by CM_GFX_GFX_CLKCTRL */ | ||
501 | #define OMAP4430_CLKSEL_PER_192M_SHIFT (1 << 25) | ||
502 | #define OMAP4430_CLKSEL_PER_192M_MASK BITFIELD(25, 26) | ||
503 | |||
504 | /* Used by CM_EMU_DEBUGSS_CLKCTRL */ | ||
505 | #define OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT (1 << 27) | ||
506 | #define OMAP4430_CLKSEL_PMD_STM_CLK_MASK BITFIELD(27, 29) | ||
507 | |||
508 | /* Used by CM_EMU_DEBUGSS_CLKCTRL */ | ||
509 | #define OMAP4430_CLKSEL_PMD_TRACE_CLK_SHIFT (1 << 24) | ||
510 | #define OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK BITFIELD(24, 26) | ||
511 | |||
512 | /* Used by CM_GFX_GFX_CLKCTRL */ | ||
513 | #define OMAP4430_CLKSEL_SGX_FCLK_SHIFT (1 << 24) | ||
514 | #define OMAP4430_CLKSEL_SGX_FCLK_MASK BITFIELD(24, 24) | ||
515 | |||
516 | /* | ||
517 | * Used by CM1_ABE_DMIC_CLKCTRL, CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, | ||
518 | * CM1_ABE_MCBSP2_CLKCTRL, CM1_ABE_MCBSP3_CLKCTRL | ||
519 | */ | ||
520 | #define OMAP4430_CLKSEL_SOURCE_SHIFT (1 << 24) | ||
521 | #define OMAP4430_CLKSEL_SOURCE_MASK BITFIELD(24, 25) | ||
522 | |||
523 | /* Renamed from CLKSEL_SOURCE Used by CM_L4PER_MCBSP4_CLKCTRL */ | ||
524 | #define OMAP4430_CLKSEL_SOURCE_24_24_SHIFT (1 << 24) | ||
525 | #define OMAP4430_CLKSEL_SOURCE_24_24_MASK BITFIELD(24, 24) | ||
526 | |||
527 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ | ||
528 | #define OMAP4430_CLKSEL_UTMI_P1_SHIFT (1 << 24) | ||
529 | #define OMAP4430_CLKSEL_UTMI_P1_MASK BITFIELD(24, 24) | ||
530 | |||
531 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ | ||
532 | #define OMAP4430_CLKSEL_UTMI_P2_SHIFT (1 << 25) | ||
533 | #define OMAP4430_CLKSEL_UTMI_P2_MASK BITFIELD(25, 25) | ||
534 | |||
535 | /* | ||
536 | * Used by CM_WKUP_CLKSTCTRL, CM_EMU_CLKSTCTRL, CM_D2D_CLKSTCTRL, | ||
537 | * CM_DUCATI_CLKSTCTRL, CM_L3INSTR_CLKSTCTRL, CM_L3_1_CLKSTCTRL, | ||
538 | * CM_L3_2_CLKSTCTRL, CM_L4CFG_CLKSTCTRL, CM_MEMIF_CLKSTCTRL, | ||
539 | * CM_SDMA_CLKSTCTRL, CM_GFX_CLKSTCTRL, CM_L4PER_CLKSTCTRL, CM_L4SEC_CLKSTCTRL, | ||
540 | * CM_L3INIT_CLKSTCTRL, CM_CAM_CLKSTCTRL, CM_CEFUSE_CLKSTCTRL, | ||
541 | * CM_L3INIT_CLKSTCTRL_RESTORE, CM_L3_1_CLKSTCTRL_RESTORE, | ||
542 | * CM_L3_2_CLKSTCTRL_RESTORE, CM_L4CFG_CLKSTCTRL_RESTORE, | ||
543 | * CM_L4PER_CLKSTCTRL_RESTORE, CM_MEMIF_CLKSTCTRL_RESTORE, CM_ALWON_CLKSTCTRL, | ||
544 | * CM_IVAHD_CLKSTCTRL, CM_DSS_CLKSTCTRL, CM_MPU_CLKSTCTRL, CM_TESLA_CLKSTCTRL, | ||
545 | * CM1_ABE_CLKSTCTRL, CM_MPU_CLKSTCTRL_RESTORE | ||
546 | */ | ||
547 | #define OMAP4430_CLKTRCTRL_SHIFT (1 << 0) | ||
548 | #define OMAP4430_CLKTRCTRL_MASK BITFIELD(0, 1) | ||
549 | |||
550 | /* Used by CM_EMU_OVERRIDE_DPLL_CORE */ | ||
551 | #define OMAP4430_CORE_DPLL_EMU_DIV_SHIFT (1 << 0) | ||
552 | #define OMAP4430_CORE_DPLL_EMU_DIV_MASK BITFIELD(0, 6) | ||
553 | |||
554 | /* Used by CM_EMU_OVERRIDE_DPLL_CORE */ | ||
555 | #define OMAP4430_CORE_DPLL_EMU_MULT_SHIFT (1 << 8) | ||
556 | #define OMAP4430_CORE_DPLL_EMU_MULT_MASK BITFIELD(8, 18) | ||
557 | |||
558 | /* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */ | ||
559 | #define OMAP4430_D2D_DYNDEP_SHIFT (1 << 18) | ||
560 | #define OMAP4430_D2D_DYNDEP_MASK BITFIELD(18, 18) | ||
561 | |||
562 | /* Used by CM_MPU_STATICDEP */ | ||
563 | #define OMAP4430_D2D_STATDEP_SHIFT (1 << 18) | ||
564 | #define OMAP4430_D2D_STATDEP_MASK BITFIELD(18, 18) | ||
565 | |||
566 | /* | ||
567 | * Used by CM_SSC_DELTAMSTEP_DPLL_PER, CM_SSC_DELTAMSTEP_DPLL_UNIPRO, | ||
568 | * CM_SSC_DELTAMSTEP_DPLL_USB, CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE, | ||
569 | * CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE, | ||
570 | * CM_SSC_DELTAMSTEP_DPLL_DDRPHY, CM_SSC_DELTAMSTEP_DPLL_IVA, | ||
571 | * CM_SSC_DELTAMSTEP_DPLL_MPU | ||
572 | */ | ||
573 | #define OMAP4430_DELTAMSTEP_SHIFT (1 << 0) | ||
574 | #define OMAP4430_DELTAMSTEP_MASK BITFIELD(0, 19) | ||
575 | |||
576 | /* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */ | ||
577 | #define OMAP4430_DLL_OVERRIDE_SHIFT (1 << 2) | ||
578 | #define OMAP4430_DLL_OVERRIDE_MASK BITFIELD(2, 2) | ||
579 | |||
580 | /* Renamed from DLL_OVERRIDE Used by CM_DLL_CTRL */ | ||
581 | #define OMAP4430_DLL_OVERRIDE_0_0_SHIFT (1 << 0) | ||
582 | #define OMAP4430_DLL_OVERRIDE_0_0_MASK BITFIELD(0, 0) | ||
583 | |||
584 | /* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */ | ||
585 | #define OMAP4430_DLL_RESET_SHIFT (1 << 3) | ||
586 | #define OMAP4430_DLL_RESET_MASK BITFIELD(3, 3) | ||
587 | |||
588 | /* | ||
589 | * Used by CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO, CM_CLKSEL_DPLL_USB, | ||
590 | * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, | ||
591 | * CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU | ||
592 | */ | ||
593 | #define OMAP4430_DPLL_BYP_CLKSEL_SHIFT (1 << 23) | ||
594 | #define OMAP4430_DPLL_BYP_CLKSEL_MASK BITFIELD(23, 23) | ||
595 | |||
596 | /* Used by CM_CLKDCOLDO_DPLL_USB */ | ||
597 | #define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT (1 << 8) | ||
598 | #define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_MASK BITFIELD(8, 8) | ||
599 | |||
600 | /* Used by CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_CORE */ | ||
601 | #define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_SHIFT (1 << 20) | ||
602 | #define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_MASK BITFIELD(20, 20) | ||
603 | |||
604 | /* | ||
605 | * Used by CM_DIV_M3_DPLL_PER, CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_ABE, | ||
606 | * CM_DIV_M3_DPLL_CORE | ||
607 | */ | ||
608 | #define OMAP4430_DPLL_CLKOUTHIF_DIV_SHIFT (1 << 0) | ||
609 | #define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK BITFIELD(0, 4) | ||
610 | |||
611 | /* | ||
612 | * Used by CM_DIV_M3_DPLL_PER, CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_ABE, | ||
613 | * CM_DIV_M3_DPLL_CORE | ||
614 | */ | ||
615 | #define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_SHIFT (1 << 5) | ||
616 | #define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_MASK BITFIELD(5, 5) | ||
617 | |||
618 | /* | ||
619 | * Used by CM_DIV_M3_DPLL_PER, CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_ABE, | ||
620 | * CM_DIV_M3_DPLL_CORE | ||
621 | */ | ||
622 | #define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT (1 << 8) | ||
623 | #define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_MASK BITFIELD(8, 8) | ||
624 | |||
625 | /* Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO, CM_DIV_M2_DPLL_ABE */ | ||
626 | #define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_SHIFT (1 << 10) | ||
627 | #define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK BITFIELD(10, 10) | ||
628 | |||
629 | /* | ||
630 | * Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO, | ||
631 | * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, | ||
632 | * CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU | ||
633 | */ | ||
634 | #define OMAP4430_DPLL_CLKOUT_DIV_SHIFT (1 << 0) | ||
635 | #define OMAP4430_DPLL_CLKOUT_DIV_MASK BITFIELD(0, 4) | ||
636 | |||
637 | /* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_USB */ | ||
638 | #define OMAP4430_DPLL_CLKOUT_DIV_0_6_SHIFT (1 << 0) | ||
639 | #define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK BITFIELD(0, 6) | ||
640 | |||
641 | /* | ||
642 | * Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO, | ||
643 | * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, | ||
644 | * CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU | ||
645 | */ | ||
646 | #define OMAP4430_DPLL_CLKOUT_DIVCHACK_SHIFT (1 << 5) | ||
647 | #define OMAP4430_DPLL_CLKOUT_DIVCHACK_MASK BITFIELD(5, 5) | ||
648 | |||
649 | /* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_USB */ | ||
650 | #define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_SHIFT (1 << 7) | ||
651 | #define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_MASK BITFIELD(7, 7) | ||
652 | |||
653 | /* | ||
654 | * Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB, CM_DIV_M2_DPLL_CORE_RESTORE, | ||
655 | * CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY, | ||
656 | * CM_DIV_M2_DPLL_MPU | ||
657 | */ | ||
658 | #define OMAP4430_DPLL_CLKOUT_GATE_CTRL_SHIFT (1 << 8) | ||
659 | #define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK BITFIELD(8, 8) | ||
660 | |||
661 | /* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */ | ||
662 | #define OMAP4430_DPLL_CORE_DPLL_EN_SHIFT (1 << 8) | ||
663 | #define OMAP4430_DPLL_CORE_DPLL_EN_MASK BITFIELD(8, 10) | ||
664 | |||
665 | /* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */ | ||
666 | #define OMAP4430_DPLL_CORE_M2_DIV_SHIFT (1 << 11) | ||
667 | #define OMAP4430_DPLL_CORE_M2_DIV_MASK BITFIELD(11, 15) | ||
668 | |||
669 | /* Used by CM_SHADOW_FREQ_CONFIG2 */ | ||
670 | #define OMAP4430_DPLL_CORE_M5_DIV_SHIFT (1 << 3) | ||
671 | #define OMAP4430_DPLL_CORE_M5_DIV_MASK BITFIELD(3, 7) | ||
672 | |||
673 | /* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */ | ||
674 | #define OMAP4430_DPLL_CORE_SYS_REF_CLKSEL_SHIFT (1 << 1) | ||
675 | #define OMAP4430_DPLL_CORE_SYS_REF_CLKSEL_MASK BITFIELD(1, 1) | ||
676 | |||
677 | /* | ||
678 | * Used by CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO, | ||
679 | * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, | ||
680 | * CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU | ||
681 | */ | ||
682 | #define OMAP4430_DPLL_DIV_SHIFT (1 << 0) | ||
683 | #define OMAP4430_DPLL_DIV_MASK BITFIELD(0, 6) | ||
684 | |||
685 | /* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_USB */ | ||
686 | #define OMAP4430_DPLL_DIV_0_7_SHIFT (1 << 0) | ||
687 | #define OMAP4430_DPLL_DIV_0_7_MASK BITFIELD(0, 7) | ||
688 | |||
689 | /* | ||
690 | * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_USB, | ||
691 | * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, | ||
692 | * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU | ||
693 | */ | ||
694 | #define OMAP4430_DPLL_DRIFTGUARD_EN_SHIFT (1 << 8) | ||
695 | #define OMAP4430_DPLL_DRIFTGUARD_EN_MASK BITFIELD(8, 8) | ||
696 | |||
697 | /* Renamed from DPLL_DRIFTGUARD_EN Used by CM_CLKMODE_DPLL_UNIPRO */ | ||
698 | #define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_SHIFT (1 << 3) | ||
699 | #define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_MASK BITFIELD(3, 3) | ||
700 | |||
701 | /* | ||
702 | * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB, | ||
703 | * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, | ||
704 | * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU | ||
705 | */ | ||
706 | #define OMAP4430_DPLL_EN_SHIFT (1 << 0) | ||
707 | #define OMAP4430_DPLL_EN_MASK BITFIELD(0, 2) | ||
708 | |||
709 | /* | ||
710 | * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, | ||
711 | * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, | ||
712 | * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU | ||
713 | */ | ||
714 | #define OMAP4430_DPLL_LPMODE_EN_SHIFT (1 << 10) | ||
715 | #define OMAP4430_DPLL_LPMODE_EN_MASK BITFIELD(10, 10) | ||
716 | |||
717 | /* | ||
718 | * Used by CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO, | ||
719 | * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, | ||
720 | * CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU | ||
721 | */ | ||
722 | #define OMAP4430_DPLL_MULT_SHIFT (1 << 8) | ||
723 | #define OMAP4430_DPLL_MULT_MASK BITFIELD(8, 18) | ||
724 | |||
725 | /* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_USB */ | ||
726 | #define OMAP4430_DPLL_MULT_USB_SHIFT (1 << 8) | ||
727 | #define OMAP4430_DPLL_MULT_USB_MASK BITFIELD(8, 19) | ||
728 | |||
729 | /* | ||
730 | * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, | ||
731 | * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, | ||
732 | * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU | ||
733 | */ | ||
734 | #define OMAP4430_DPLL_REGM4XEN_SHIFT (1 << 11) | ||
735 | #define OMAP4430_DPLL_REGM4XEN_MASK BITFIELD(11, 11) | ||
736 | |||
737 | /* Used by CM_CLKSEL_DPLL_USB */ | ||
738 | #define OMAP4430_DPLL_SD_DIV_SHIFT (1 << 24) | ||
739 | #define OMAP4430_DPLL_SD_DIV_MASK BITFIELD(24, 31) | ||
740 | |||
741 | /* | ||
742 | * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB, | ||
743 | * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, | ||
744 | * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU | ||
745 | */ | ||
746 | #define OMAP4430_DPLL_SSC_ACK_SHIFT (1 << 13) | ||
747 | #define OMAP4430_DPLL_SSC_ACK_MASK BITFIELD(13, 13) | ||
748 | |||
749 | /* | ||
750 | * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB, | ||
751 | * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, | ||
752 | * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU | ||
753 | */ | ||
754 | #define OMAP4430_DPLL_SSC_DOWNSPREAD_SHIFT (1 << 14) | ||
755 | #define OMAP4430_DPLL_SSC_DOWNSPREAD_MASK BITFIELD(14, 14) | ||
756 | |||
757 | /* | ||
758 | * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB, | ||
759 | * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, | ||
760 | * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU | ||
761 | */ | ||
762 | #define OMAP4430_DPLL_SSC_EN_SHIFT (1 << 12) | ||
763 | #define OMAP4430_DPLL_SSC_EN_MASK BITFIELD(12, 12) | ||
764 | |||
765 | /* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ | ||
766 | #define OMAP4430_DSS_DYNDEP_SHIFT (1 << 8) | ||
767 | #define OMAP4430_DSS_DYNDEP_MASK BITFIELD(8, 8) | ||
768 | |||
769 | /* | ||
770 | * Used by CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, | ||
771 | * CM_MPU_STATICDEP | ||
772 | */ | ||
773 | #define OMAP4430_DSS_STATDEP_SHIFT (1 << 8) | ||
774 | #define OMAP4430_DSS_STATDEP_MASK BITFIELD(8, 8) | ||
775 | |||
776 | /* Used by CM_L3_2_DYNAMICDEP */ | ||
777 | #define OMAP4430_DUCATI_DYNDEP_SHIFT (1 << 0) | ||
778 | #define OMAP4430_DUCATI_DYNDEP_MASK BITFIELD(0, 0) | ||
779 | |||
780 | /* Used by CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP */ | ||
781 | #define OMAP4430_DUCATI_STATDEP_SHIFT (1 << 0) | ||
782 | #define OMAP4430_DUCATI_STATDEP_MASK BITFIELD(0, 0) | ||
783 | |||
784 | /* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */ | ||
785 | #define OMAP4430_FREQ_UPDATE_SHIFT (1 << 0) | ||
786 | #define OMAP4430_FREQ_UPDATE_MASK BITFIELD(0, 0) | ||
787 | |||
788 | /* Used by CM_L3_2_DYNAMICDEP */ | ||
789 | #define OMAP4430_GFX_DYNDEP_SHIFT (1 << 10) | ||
790 | #define OMAP4430_GFX_DYNDEP_MASK BITFIELD(10, 10) | ||
791 | |||
792 | /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */ | ||
793 | #define OMAP4430_GFX_STATDEP_SHIFT (1 << 10) | ||
794 | #define OMAP4430_GFX_STATDEP_MASK BITFIELD(10, 10) | ||
795 | |||
796 | /* Used by CM_SHADOW_FREQ_CONFIG2 */ | ||
797 | #define OMAP4430_GPMC_FREQ_UPDATE_SHIFT (1 << 0) | ||
798 | #define OMAP4430_GPMC_FREQ_UPDATE_MASK BITFIELD(0, 0) | ||
799 | |||
800 | /* | ||
801 | * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE, | ||
802 | * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA | ||
803 | */ | ||
804 | #define OMAP4430_HSDIVIDER_CLKOUT1_DIV_SHIFT (1 << 0) | ||
805 | #define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK BITFIELD(0, 4) | ||
806 | |||
807 | /* | ||
808 | * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE, | ||
809 | * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA | ||
810 | */ | ||
811 | #define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT (1 << 5) | ||
812 | #define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_MASK BITFIELD(5, 5) | ||
813 | |||
814 | /* | ||
815 | * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE, | ||
816 | * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA | ||
817 | */ | ||
818 | #define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT (1 << 8) | ||
819 | #define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK BITFIELD(8, 8) | ||
820 | |||
821 | /* | ||
822 | * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE, | ||
823 | * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA | ||
824 | */ | ||
825 | #define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_SHIFT (1 << 12) | ||
826 | #define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_MASK BITFIELD(12, 12) | ||
827 | |||
828 | /* | ||
829 | * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE, | ||
830 | * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA | ||
831 | */ | ||
832 | #define OMAP4430_HSDIVIDER_CLKOUT2_DIV_SHIFT (1 << 0) | ||
833 | #define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK BITFIELD(0, 4) | ||
834 | |||
835 | /* | ||
836 | * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE, | ||
837 | * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA | ||
838 | */ | ||
839 | #define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT (1 << 5) | ||
840 | #define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_MASK BITFIELD(5, 5) | ||
841 | |||
842 | /* | ||
843 | * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE, | ||
844 | * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA | ||
845 | */ | ||
846 | #define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT (1 << 8) | ||
847 | #define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK BITFIELD(8, 8) | ||
848 | |||
849 | /* | ||
850 | * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE, | ||
851 | * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA | ||
852 | */ | ||
853 | #define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_SHIFT (1 << 12) | ||
854 | #define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_MASK BITFIELD(12, 12) | ||
855 | |||
856 | /* | ||
857 | * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE, | ||
858 | * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY | ||
859 | */ | ||
860 | #define OMAP4430_HSDIVIDER_CLKOUT3_DIV_SHIFT (1 << 0) | ||
861 | #define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK BITFIELD(0, 4) | ||
862 | |||
863 | /* | ||
864 | * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE, | ||
865 | * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY | ||
866 | */ | ||
867 | #define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT (1 << 5) | ||
868 | #define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_MASK BITFIELD(5, 5) | ||
869 | |||
870 | /* | ||
871 | * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE, | ||
872 | * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY | ||
873 | */ | ||
874 | #define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT (1 << 8) | ||
875 | #define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK BITFIELD(8, 8) | ||
876 | |||
877 | /* | ||
878 | * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE, | ||
879 | * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY | ||
880 | */ | ||
881 | #define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_SHIFT (1 << 12) | ||
882 | #define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_MASK BITFIELD(12, 12) | ||
883 | |||
884 | /* | ||
885 | * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE, | ||
886 | * CM_DIV_M7_DPLL_CORE | ||
887 | */ | ||
888 | #define OMAP4430_HSDIVIDER_CLKOUT4_DIV_SHIFT (1 << 0) | ||
889 | #define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK BITFIELD(0, 4) | ||
890 | |||
891 | /* | ||
892 | * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE, | ||
893 | * CM_DIV_M7_DPLL_CORE | ||
894 | */ | ||
895 | #define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_SHIFT (1 << 5) | ||
896 | #define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_MASK BITFIELD(5, 5) | ||
897 | |||
898 | /* | ||
899 | * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE, | ||
900 | * CM_DIV_M7_DPLL_CORE | ||
901 | */ | ||
902 | #define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_SHIFT (1 << 8) | ||
903 | #define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_MASK BITFIELD(8, 8) | ||
904 | |||
905 | /* | ||
906 | * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE, | ||
907 | * CM_DIV_M7_DPLL_CORE | ||
908 | */ | ||
909 | #define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_SHIFT (1 << 12) | ||
910 | #define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_MASK BITFIELD(12, 12) | ||
911 | |||
912 | /* | ||
913 | * Used by PRM_PRM_PROFILING_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, | ||
914 | * CM_WKUP_KEYBOARD_CLKCTRL, CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_RTC_CLKCTRL, | ||
915 | * CM_WKUP_SARRAM_CLKCTRL, CM_WKUP_SYNCTIMER_CLKCTRL, CM_WKUP_TIMER12_CLKCTRL, | ||
916 | * CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_USIM_CLKCTRL, CM_WKUP_WDT1_CLKCTRL, | ||
917 | * CM_WKUP_WDT2_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL, CM_D2D_MODEM_ICR_CLKCTRL, | ||
918 | * CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL, | ||
919 | * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL, | ||
920 | * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, | ||
921 | * CM_L3_2_L3_2_CLKCTRL, CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, | ||
922 | * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, | ||
923 | * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL, | ||
924 | * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MEMIF_EMIF_H1_CLKCTRL, | ||
925 | * CM_MEMIF_EMIF_H2_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, CM_GFX_GFX_CLKCTRL, | ||
926 | * CM_L4PER_ADC_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL, | ||
927 | * CM_L4PER_DMTIMER11_CLKCTRL, CM_L4PER_DMTIMER2_CLKCTRL, | ||
928 | * CM_L4PER_DMTIMER3_CLKCTRL, CM_L4PER_DMTIMER4_CLKCTRL, | ||
929 | * CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL, | ||
930 | * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, | ||
931 | * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_HECC1_CLKCTRL, | ||
932 | * CM_L4PER_HECC2_CLKCTRL, CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, | ||
933 | * CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, | ||
934 | * CM_L4PER_L4PER_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL, | ||
935 | * CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, | ||
936 | * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MGATE_CLKCTRL, | ||
937 | * CM_L4PER_MMCSD3_CLKCTRL, CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, | ||
938 | * CM_L4PER_MSPROHG_CLKCTRL, CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, | ||
939 | * CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, | ||
940 | * CM_L4SEC_AES1_CLKCTRL, CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, | ||
941 | * CM_L4SEC_DES3DES_CLKCTRL, CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, | ||
942 | * CM_L4SEC_SHA2MD51_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL, | ||
943 | * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, | ||
944 | * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL, | ||
945 | * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL, | ||
946 | * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL, | ||
947 | * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL, | ||
948 | * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_CAM_FDIF_CLKCTRL, | ||
949 | * CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, | ||
950 | * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE, | ||
951 | * CM_L3INSTR_L3_3_CLKCTRL_RESTORE, CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE, | ||
952 | * CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE, CM_L4PER_GPIO2_CLKCTRL_RESTORE, | ||
953 | * CM_L4PER_GPIO3_CLKCTRL_RESTORE, CM_L4PER_GPIO4_CLKCTRL_RESTORE, | ||
954 | * CM_L4PER_GPIO5_CLKCTRL_RESTORE, CM_L4PER_GPIO6_CLKCTRL_RESTORE, | ||
955 | * CM_ALWON_MDMINTC_CLKCTRL, CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, | ||
956 | * CM_ALWON_SR_MPU_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL, CM_IVAHD_SL2_CLKCTRL, | ||
957 | * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_CM2_PROFILING_CLKCTRL, | ||
958 | * CM_MPU_MPU_CLKCTRL, CM_TESLA_TESLA_CLKCTRL, CM1_ABE_AESS_CLKCTRL, | ||
959 | * CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL, CM1_ABE_MCASP_CLKCTRL, | ||
960 | * CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL, CM1_ABE_MCBSP3_CLKCTRL, | ||
961 | * CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL, CM1_ABE_TIMER5_CLKCTRL, | ||
962 | * CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL, | ||
963 | * CM1_ABE_WDT3_CLKCTRL, CM_CM1_PROFILING_CLKCTRL | ||
964 | */ | ||
965 | #define OMAP4430_IDLEST_SHIFT (1 << 16) | ||
966 | #define OMAP4430_IDLEST_MASK BITFIELD(16, 17) | ||
967 | |||
968 | /* Used by CM_DUCATI_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */ | ||
969 | #define OMAP4430_ISS_DYNDEP_SHIFT (1 << 9) | ||
970 | #define OMAP4430_ISS_DYNDEP_MASK BITFIELD(9, 9) | ||
971 | |||
972 | /* | ||
973 | * Used by CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, | ||
974 | * CM_MPU_STATICDEP, CM_TESLA_STATICDEP | ||
975 | */ | ||
976 | #define OMAP4430_ISS_STATDEP_SHIFT (1 << 9) | ||
977 | #define OMAP4430_ISS_STATDEP_MASK BITFIELD(9, 9) | ||
978 | |||
979 | /* Used by CM_L3_2_DYNAMICDEP, CM_TESLA_DYNAMICDEP */ | ||
980 | #define OMAP4430_IVAHD_DYNDEP_SHIFT (1 << 2) | ||
981 | #define OMAP4430_IVAHD_DYNDEP_MASK BITFIELD(2, 2) | ||
982 | |||
983 | /* | ||
984 | * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, | ||
985 | * CM_GFX_STATICDEP, CM_L3INIT_STATICDEP, CM_CAM_STATICDEP, | ||
986 | * CM_SDMA_STATICDEP_RESTORE, CM_DSS_STATICDEP, CM_MPU_STATICDEP, | ||
987 | * CM_TESLA_STATICDEP | ||
988 | */ | ||
989 | #define OMAP4430_IVAHD_STATDEP_SHIFT (1 << 2) | ||
990 | #define OMAP4430_IVAHD_STATDEP_MASK BITFIELD(2, 2) | ||
991 | |||
992 | /* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ | ||
993 | #define OMAP4430_L3INIT_DYNDEP_SHIFT (1 << 7) | ||
994 | #define OMAP4430_L3INIT_DYNDEP_MASK BITFIELD(7, 7) | ||
995 | |||
996 | /* | ||
997 | * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, | ||
998 | * CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP, CM_TESLA_STATICDEP | ||
999 | */ | ||
1000 | #define OMAP4430_L3INIT_STATDEP_SHIFT (1 << 7) | ||
1001 | #define OMAP4430_L3INIT_STATDEP_MASK BITFIELD(7, 7) | ||
1002 | |||
1003 | /* | ||
1004 | * Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, | ||
1005 | * CM_DSS_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP | ||
1006 | */ | ||
1007 | #define OMAP4430_L3_1_DYNDEP_SHIFT (1 << 5) | ||
1008 | #define OMAP4430_L3_1_DYNDEP_MASK BITFIELD(5, 5) | ||
1009 | |||
1010 | /* | ||
1011 | * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, | ||
1012 | * CM_GFX_STATICDEP, CM_L4SEC_STATICDEP, CM_L3INIT_STATICDEP, CM_CAM_STATICDEP, | ||
1013 | * CM_SDMA_STATICDEP_RESTORE, CM_IVAHD_STATICDEP, CM_DSS_STATICDEP, | ||
1014 | * CM_MPU_STATICDEP, CM_TESLA_STATICDEP | ||
1015 | */ | ||
1016 | #define OMAP4430_L3_1_STATDEP_SHIFT (1 << 5) | ||
1017 | #define OMAP4430_L3_1_STATDEP_MASK BITFIELD(5, 5) | ||
1018 | |||
1019 | /* | ||
1020 | * Used by CM_EMU_DYNAMICDEP, CM_D2D_DYNAMICDEP, CM_DUCATI_DYNAMICDEP, | ||
1021 | * CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_SDMA_DYNAMICDEP, | ||
1022 | * CM_GFX_DYNAMICDEP, CM_L4SEC_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, | ||
1023 | * CM_CAM_DYNAMICDEP, CM_IVAHD_DYNAMICDEP | ||
1024 | */ | ||
1025 | #define OMAP4430_L3_2_DYNDEP_SHIFT (1 << 6) | ||
1026 | #define OMAP4430_L3_2_DYNDEP_MASK BITFIELD(6, 6) | ||
1027 | |||
1028 | /* | ||
1029 | * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, | ||
1030 | * CM_GFX_STATICDEP, CM_L4SEC_STATICDEP, CM_L3INIT_STATICDEP, CM_CAM_STATICDEP, | ||
1031 | * CM_SDMA_STATICDEP_RESTORE, CM_IVAHD_STATICDEP, CM_DSS_STATICDEP, | ||
1032 | * CM_MPU_STATICDEP, CM_TESLA_STATICDEP | ||
1033 | */ | ||
1034 | #define OMAP4430_L3_2_STATDEP_SHIFT (1 << 6) | ||
1035 | #define OMAP4430_L3_2_STATDEP_MASK BITFIELD(6, 6) | ||
1036 | |||
1037 | /* Used by CM_L3_1_DYNAMICDEP */ | ||
1038 | #define OMAP4430_L4CFG_DYNDEP_SHIFT (1 << 12) | ||
1039 | #define OMAP4430_L4CFG_DYNDEP_MASK BITFIELD(12, 12) | ||
1040 | |||
1041 | /* | ||
1042 | * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, | ||
1043 | * CM_L3INIT_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP, | ||
1044 | * CM_TESLA_STATICDEP | ||
1045 | */ | ||
1046 | #define OMAP4430_L4CFG_STATDEP_SHIFT (1 << 12) | ||
1047 | #define OMAP4430_L4CFG_STATDEP_MASK BITFIELD(12, 12) | ||
1048 | |||
1049 | /* Used by CM_L3_2_DYNAMICDEP */ | ||
1050 | #define OMAP4430_L4PER_DYNDEP_SHIFT (1 << 13) | ||
1051 | #define OMAP4430_L4PER_DYNDEP_MASK BITFIELD(13, 13) | ||
1052 | |||
1053 | /* | ||
1054 | * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, | ||
1055 | * CM_L4SEC_STATICDEP, CM_L3INIT_STATICDEP, CM_SDMA_STATICDEP_RESTORE, | ||
1056 | * CM_MPU_STATICDEP, CM_TESLA_STATICDEP | ||
1057 | */ | ||
1058 | #define OMAP4430_L4PER_STATDEP_SHIFT (1 << 13) | ||
1059 | #define OMAP4430_L4PER_STATDEP_MASK BITFIELD(13, 13) | ||
1060 | |||
1061 | /* Used by CM_L3_2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ | ||
1062 | #define OMAP4430_L4SEC_DYNDEP_SHIFT (1 << 14) | ||
1063 | #define OMAP4430_L4SEC_DYNDEP_MASK BITFIELD(14, 14) | ||
1064 | |||
1065 | /* | ||
1066 | * Used by CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, CM_L3INIT_STATICDEP, | ||
1067 | * CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP | ||
1068 | */ | ||
1069 | #define OMAP4430_L4SEC_STATDEP_SHIFT (1 << 14) | ||
1070 | #define OMAP4430_L4SEC_STATDEP_MASK BITFIELD(14, 14) | ||
1071 | |||
1072 | /* Used by CM_L4CFG_DYNAMICDEP */ | ||
1073 | #define OMAP4430_L4WKUP_DYNDEP_SHIFT (1 << 15) | ||
1074 | #define OMAP4430_L4WKUP_DYNDEP_MASK BITFIELD(15, 15) | ||
1075 | |||
1076 | /* | ||
1077 | * Used by CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, CM_L3INIT_STATICDEP, | ||
1078 | * CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP, CM_TESLA_STATICDEP | ||
1079 | */ | ||
1080 | #define OMAP4430_L4WKUP_STATDEP_SHIFT (1 << 15) | ||
1081 | #define OMAP4430_L4WKUP_STATDEP_MASK BITFIELD(15, 15) | ||
1082 | |||
1083 | /* | ||
1084 | * Used by CM_D2D_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, | ||
1085 | * CM_MPU_DYNAMICDEP | ||
1086 | */ | ||
1087 | #define OMAP4430_MEMIF_DYNDEP_SHIFT (1 << 4) | ||
1088 | #define OMAP4430_MEMIF_DYNDEP_MASK BITFIELD(4, 4) | ||
1089 | |||
1090 | /* | ||
1091 | * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, | ||
1092 | * CM_GFX_STATICDEP, CM_L4SEC_STATICDEP, CM_L3INIT_STATICDEP, CM_CAM_STATICDEP, | ||
1093 | * CM_SDMA_STATICDEP_RESTORE, CM_IVAHD_STATICDEP, CM_DSS_STATICDEP, | ||
1094 | * CM_MPU_STATICDEP, CM_TESLA_STATICDEP | ||
1095 | */ | ||
1096 | #define OMAP4430_MEMIF_STATDEP_SHIFT (1 << 4) | ||
1097 | #define OMAP4430_MEMIF_STATDEP_MASK BITFIELD(4, 4) | ||
1098 | |||
1099 | /* | ||
1100 | * Used by CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO, | ||
1101 | * CM_SSC_MODFREQDIV_DPLL_USB, CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE, | ||
1102 | * CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE, | ||
1103 | * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA, | ||
1104 | * CM_SSC_MODFREQDIV_DPLL_MPU | ||
1105 | */ | ||
1106 | #define OMAP4430_MODFREQDIV_EXPONENT_SHIFT (1 << 8) | ||
1107 | #define OMAP4430_MODFREQDIV_EXPONENT_MASK BITFIELD(8, 10) | ||
1108 | |||
1109 | /* | ||
1110 | * Used by CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO, | ||
1111 | * CM_SSC_MODFREQDIV_DPLL_USB, CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE, | ||
1112 | * CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE, | ||
1113 | * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA, | ||
1114 | * CM_SSC_MODFREQDIV_DPLL_MPU | ||
1115 | */ | ||
1116 | #define OMAP4430_MODFREQDIV_MANTISSA_SHIFT (1 << 0) | ||
1117 | #define OMAP4430_MODFREQDIV_MANTISSA_MASK BITFIELD(0, 6) | ||
1118 | |||
1119 | /* | ||
1120 | * Used by PRM_PRM_PROFILING_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, | ||
1121 | * CM_WKUP_KEYBOARD_CLKCTRL, CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_RTC_CLKCTRL, | ||
1122 | * CM_WKUP_SARRAM_CLKCTRL, CM_WKUP_SYNCTIMER_CLKCTRL, CM_WKUP_TIMER12_CLKCTRL, | ||
1123 | * CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_USIM_CLKCTRL, CM_WKUP_WDT1_CLKCTRL, | ||
1124 | * CM_WKUP_WDT2_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL, CM_D2D_MODEM_ICR_CLKCTRL, | ||
1125 | * CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL, | ||
1126 | * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL, | ||
1127 | * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, | ||
1128 | * CM_L3_2_L3_2_CLKCTRL, CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, | ||
1129 | * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, | ||
1130 | * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL, | ||
1131 | * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MEMIF_EMIF_H1_CLKCTRL, | ||
1132 | * CM_MEMIF_EMIF_H2_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, CM_GFX_GFX_CLKCTRL, | ||
1133 | * CM_L4PER_ADC_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL, | ||
1134 | * CM_L4PER_DMTIMER11_CLKCTRL, CM_L4PER_DMTIMER2_CLKCTRL, | ||
1135 | * CM_L4PER_DMTIMER3_CLKCTRL, CM_L4PER_DMTIMER4_CLKCTRL, | ||
1136 | * CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL, | ||
1137 | * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, | ||
1138 | * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_HECC1_CLKCTRL, | ||
1139 | * CM_L4PER_HECC2_CLKCTRL, CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, | ||
1140 | * CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, | ||
1141 | * CM_L4PER_L4PER_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL, | ||
1142 | * CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, | ||
1143 | * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MGATE_CLKCTRL, | ||
1144 | * CM_L4PER_MMCSD3_CLKCTRL, CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, | ||
1145 | * CM_L4PER_MSPROHG_CLKCTRL, CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, | ||
1146 | * CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, | ||
1147 | * CM_L4SEC_AES1_CLKCTRL, CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, | ||
1148 | * CM_L4SEC_DES3DES_CLKCTRL, CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, | ||
1149 | * CM_L4SEC_SHA2MD51_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL, | ||
1150 | * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, | ||
1151 | * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL, | ||
1152 | * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL, | ||
1153 | * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL, | ||
1154 | * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL, | ||
1155 | * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_CAM_FDIF_CLKCTRL, | ||
1156 | * CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, | ||
1157 | * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE, | ||
1158 | * CM_L3INSTR_L3_3_CLKCTRL_RESTORE, CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE, | ||
1159 | * CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE, CM_L4PER_GPIO2_CLKCTRL_RESTORE, | ||
1160 | * CM_L4PER_GPIO3_CLKCTRL_RESTORE, CM_L4PER_GPIO4_CLKCTRL_RESTORE, | ||
1161 | * CM_L4PER_GPIO5_CLKCTRL_RESTORE, CM_L4PER_GPIO6_CLKCTRL_RESTORE, | ||
1162 | * CM_ALWON_MDMINTC_CLKCTRL, CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, | ||
1163 | * CM_ALWON_SR_MPU_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL, CM_IVAHD_SL2_CLKCTRL, | ||
1164 | * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_CM2_PROFILING_CLKCTRL, | ||
1165 | * CM_MPU_MPU_CLKCTRL, CM_TESLA_TESLA_CLKCTRL, CM1_ABE_AESS_CLKCTRL, | ||
1166 | * CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL, CM1_ABE_MCASP_CLKCTRL, | ||
1167 | * CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL, CM1_ABE_MCBSP3_CLKCTRL, | ||
1168 | * CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL, CM1_ABE_TIMER5_CLKCTRL, | ||
1169 | * CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL, | ||
1170 | * CM1_ABE_WDT3_CLKCTRL, CM_CM1_PROFILING_CLKCTRL | ||
1171 | */ | ||
1172 | #define OMAP4430_MODULEMODE_SHIFT (1 << 0) | ||
1173 | #define OMAP4430_MODULEMODE_MASK BITFIELD(0, 1) | ||
1174 | |||
1175 | /* Used by CM_DSS_DSS_CLKCTRL */ | ||
1176 | #define OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT (1 << 9) | ||
1177 | #define OMAP4430_OPTFCLKEN_48MHZ_CLK_MASK BITFIELD(9, 9) | ||
1178 | |||
1179 | /* Used by CM_WKUP_BANDGAP_CLKCTRL */ | ||
1180 | #define OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT (1 << 8) | ||
1181 | #define OMAP4430_OPTFCLKEN_BGAP_32K_MASK BITFIELD(8, 8) | ||
1182 | |||
1183 | /* Used by CM_L3INIT_USBPHYOCP2SCP_CLKCTRL */ | ||
1184 | #define OMAP4430_OPTFCLKEN_CLK32K_SHIFT (1 << 9) | ||
1185 | #define OMAP4430_OPTFCLKEN_CLK32K_MASK BITFIELD(9, 9) | ||
1186 | |||
1187 | /* Used by CM_CAM_ISS_CLKCTRL */ | ||
1188 | #define OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT (1 << 8) | ||
1189 | #define OMAP4430_OPTFCLKEN_CTRLCLK_MASK BITFIELD(8, 8) | ||
1190 | |||
1191 | /* | ||
1192 | * Used by CM_WKUP_GPIO1_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL, | ||
1193 | * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, | ||
1194 | * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL_RESTORE, | ||
1195 | * CM_L4PER_GPIO3_CLKCTRL_RESTORE, CM_L4PER_GPIO4_CLKCTRL_RESTORE, | ||
1196 | * CM_L4PER_GPIO5_CLKCTRL_RESTORE, CM_L4PER_GPIO6_CLKCTRL_RESTORE | ||
1197 | */ | ||
1198 | #define OMAP4430_OPTFCLKEN_DBCLK_SHIFT (1 << 8) | ||
1199 | #define OMAP4430_OPTFCLKEN_DBCLK_MASK BITFIELD(8, 8) | ||
1200 | |||
1201 | /* Used by CM_MEMIF_DLL_CLKCTRL, CM_MEMIF_DLL_H_CLKCTRL */ | ||
1202 | #define OMAP4430_OPTFCLKEN_DLL_CLK_SHIFT (1 << 8) | ||
1203 | #define OMAP4430_OPTFCLKEN_DLL_CLK_MASK BITFIELD(8, 8) | ||
1204 | |||
1205 | /* Used by CM_DSS_DSS_CLKCTRL */ | ||
1206 | #define OMAP4430_OPTFCLKEN_DSSCLK_SHIFT (1 << 8) | ||
1207 | #define OMAP4430_OPTFCLKEN_DSSCLK_MASK BITFIELD(8, 8) | ||
1208 | |||
1209 | /* Used by CM1_ABE_SLIMBUS_CLKCTRL */ | ||
1210 | #define OMAP4430_OPTFCLKEN_FCLK0_SHIFT (1 << 8) | ||
1211 | #define OMAP4430_OPTFCLKEN_FCLK0_MASK BITFIELD(8, 8) | ||
1212 | |||
1213 | /* Used by CM1_ABE_SLIMBUS_CLKCTRL */ | ||
1214 | #define OMAP4430_OPTFCLKEN_FCLK1_SHIFT (1 << 9) | ||
1215 | #define OMAP4430_OPTFCLKEN_FCLK1_MASK BITFIELD(9, 9) | ||
1216 | |||
1217 | /* Used by CM1_ABE_SLIMBUS_CLKCTRL */ | ||
1218 | #define OMAP4430_OPTFCLKEN_FCLK2_SHIFT (1 << 10) | ||
1219 | #define OMAP4430_OPTFCLKEN_FCLK2_MASK BITFIELD(10, 10) | ||
1220 | |||
1221 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ | ||
1222 | #define OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT (1 << 15) | ||
1223 | #define OMAP4430_OPTFCLKEN_FUNC48MCLK_MASK BITFIELD(15, 15) | ||
1224 | |||
1225 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ | ||
1226 | #define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT (1 << 13) | ||
1227 | #define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_MASK BITFIELD(13, 13) | ||
1228 | |||
1229 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ | ||
1230 | #define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT (1 << 14) | ||
1231 | #define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_MASK BITFIELD(14, 14) | ||
1232 | |||
1233 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ | ||
1234 | #define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT (1 << 11) | ||
1235 | #define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_MASK BITFIELD(11, 11) | ||
1236 | |||
1237 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ | ||
1238 | #define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT (1 << 12) | ||
1239 | #define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_MASK BITFIELD(12, 12) | ||
1240 | |||
1241 | /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */ | ||
1242 | #define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT (1 << 8) | ||
1243 | #define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_MASK BITFIELD(8, 8) | ||
1244 | |||
1245 | /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */ | ||
1246 | #define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT (1 << 9) | ||
1247 | #define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_MASK BITFIELD(9, 9) | ||
1248 | |||
1249 | /* Used by CM_L3INIT_USBPHYOCP2SCP_CLKCTRL */ | ||
1250 | #define OMAP4430_OPTFCLKEN_PHY_48M_SHIFT (1 << 8) | ||
1251 | #define OMAP4430_OPTFCLKEN_PHY_48M_MASK BITFIELD(8, 8) | ||
1252 | |||
1253 | /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */ | ||
1254 | #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT (1 << 10) | ||
1255 | #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_MASK BITFIELD(10, 10) | ||
1256 | |||
1257 | /* Renamed from OPTFCLKEN_SLIMBUS_CLK Used by CM1_ABE_SLIMBUS_CLKCTRL */ | ||
1258 | #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT (1 << 11) | ||
1259 | #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_MASK BITFIELD(11, 11) | ||
1260 | |||
1261 | /* Used by CM_DSS_DSS_CLKCTRL */ | ||
1262 | #define OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT (1 << 10) | ||
1263 | #define OMAP4430_OPTFCLKEN_SYS_CLK_MASK BITFIELD(10, 10) | ||
1264 | |||
1265 | /* Used by CM_DSS_DSS_CLKCTRL */ | ||
1266 | #define OMAP4430_OPTFCLKEN_TV_CLK_SHIFT (1 << 11) | ||
1267 | #define OMAP4430_OPTFCLKEN_TV_CLK_MASK BITFIELD(11, 11) | ||
1268 | |||
1269 | /* Used by CM_L3INIT_UNIPRO1_CLKCTRL */ | ||
1270 | #define OMAP4430_OPTFCLKEN_TXPHYCLK_SHIFT (1 << 8) | ||
1271 | #define OMAP4430_OPTFCLKEN_TXPHYCLK_MASK BITFIELD(8, 8) | ||
1272 | |||
1273 | /* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */ | ||
1274 | #define OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT (1 << 8) | ||
1275 | #define OMAP4430_OPTFCLKEN_USB_CH0_CLK_MASK BITFIELD(8, 8) | ||
1276 | |||
1277 | /* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */ | ||
1278 | #define OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT (1 << 9) | ||
1279 | #define OMAP4430_OPTFCLKEN_USB_CH1_CLK_MASK BITFIELD(9, 9) | ||
1280 | |||
1281 | /* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */ | ||
1282 | #define OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT (1 << 10) | ||
1283 | #define OMAP4430_OPTFCLKEN_USB_CH2_CLK_MASK BITFIELD(10, 10) | ||
1284 | |||
1285 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ | ||
1286 | #define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT (1 << 8) | ||
1287 | #define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_MASK BITFIELD(8, 8) | ||
1288 | |||
1289 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ | ||
1290 | #define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT (1 << 9) | ||
1291 | #define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_MASK BITFIELD(9, 9) | ||
1292 | |||
1293 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ | ||
1294 | #define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT (1 << 10) | ||
1295 | #define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_MASK BITFIELD(10, 10) | ||
1296 | |||
1297 | /* Used by CM_L3INIT_USB_OTG_CLKCTRL */ | ||
1298 | #define OMAP4430_OPTFCLKEN_XCLK_SHIFT (1 << 8) | ||
1299 | #define OMAP4430_OPTFCLKEN_XCLK_MASK BITFIELD(8, 8) | ||
1300 | |||
1301 | /* Used by CM_EMU_OVERRIDE_DPLL_PER, CM_EMU_OVERRIDE_DPLL_CORE */ | ||
1302 | #define OMAP4430_OVERRIDE_ENABLE_SHIFT (1 << 19) | ||
1303 | #define OMAP4430_OVERRIDE_ENABLE_MASK BITFIELD(19, 19) | ||
1304 | |||
1305 | /* Used by CM_CLKSEL_ABE */ | ||
1306 | #define OMAP4430_PAD_CLKS_GATE_SHIFT (1 << 8) | ||
1307 | #define OMAP4430_PAD_CLKS_GATE_MASK BITFIELD(8, 8) | ||
1308 | |||
1309 | /* Used by CM_CORE_DVFS_CURRENT, CM_IVA_DVFS_CURRENT */ | ||
1310 | #define OMAP4430_PERF_CURRENT_SHIFT (1 << 0) | ||
1311 | #define OMAP4430_PERF_CURRENT_MASK BITFIELD(0, 7) | ||
1312 | |||
1313 | /* | ||
1314 | * Used by CM_CORE_DVFS_PERF1, CM_CORE_DVFS_PERF2, CM_CORE_DVFS_PERF3, | ||
1315 | * CM_CORE_DVFS_PERF4, CM_IVA_DVFS_PERF_ABE, CM_IVA_DVFS_PERF_IVAHD, | ||
1316 | * CM_IVA_DVFS_PERF_TESLA | ||
1317 | */ | ||
1318 | #define OMAP4430_PERF_REQ_SHIFT (1 << 0) | ||
1319 | #define OMAP4430_PERF_REQ_MASK BITFIELD(0, 7) | ||
1320 | |||
1321 | /* Used by CM_EMU_OVERRIDE_DPLL_PER */ | ||
1322 | #define OMAP4430_PER_DPLL_EMU_DIV_SHIFT (1 << 0) | ||
1323 | #define OMAP4430_PER_DPLL_EMU_DIV_MASK BITFIELD(0, 6) | ||
1324 | |||
1325 | /* Used by CM_EMU_OVERRIDE_DPLL_PER */ | ||
1326 | #define OMAP4430_PER_DPLL_EMU_MULT_SHIFT (1 << 8) | ||
1327 | #define OMAP4430_PER_DPLL_EMU_MULT_MASK BITFIELD(8, 18) | ||
1328 | |||
1329 | /* Used by CM_RESTORE_ST */ | ||
1330 | #define OMAP4430_PHASE1_COMPLETED_SHIFT (1 << 0) | ||
1331 | #define OMAP4430_PHASE1_COMPLETED_MASK BITFIELD(0, 0) | ||
1332 | |||
1333 | /* Used by CM_RESTORE_ST */ | ||
1334 | #define OMAP4430_PHASE2A_COMPLETED_SHIFT (1 << 1) | ||
1335 | #define OMAP4430_PHASE2A_COMPLETED_MASK BITFIELD(1, 1) | ||
1336 | |||
1337 | /* Used by CM_RESTORE_ST */ | ||
1338 | #define OMAP4430_PHASE2B_COMPLETED_SHIFT (1 << 2) | ||
1339 | #define OMAP4430_PHASE2B_COMPLETED_MASK BITFIELD(2, 2) | ||
1340 | |||
1341 | /* Used by CM_EMU_DEBUGSS_CLKCTRL */ | ||
1342 | #define OMAP4430_PMD_STM_MUX_CTRL_SHIFT (1 << 20) | ||
1343 | #define OMAP4430_PMD_STM_MUX_CTRL_MASK BITFIELD(20, 21) | ||
1344 | |||
1345 | /* Used by CM_EMU_DEBUGSS_CLKCTRL */ | ||
1346 | #define OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT (1 << 22) | ||
1347 | #define OMAP4430_PMD_TRACE_MUX_CTRL_MASK BITFIELD(22, 23) | ||
1348 | |||
1349 | /* Used by CM_DYN_DEP_PRESCAL */ | ||
1350 | #define OMAP4430_PRESCAL_SHIFT (1 << 0) | ||
1351 | #define OMAP4430_PRESCAL_MASK BITFIELD(0, 5) | ||
1352 | |||
1353 | /* Used by REVISION_CM2, REVISION_CM1 */ | ||
1354 | #define OMAP4430_REV_SHIFT (1 << 0) | ||
1355 | #define OMAP4430_REV_MASK BITFIELD(0, 7) | ||
1356 | |||
1357 | /* | ||
1358 | * Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL, | ||
1359 | * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE | ||
1360 | */ | ||
1361 | #define OMAP4430_SAR_MODE_SHIFT (1 << 4) | ||
1362 | #define OMAP4430_SAR_MODE_MASK BITFIELD(4, 4) | ||
1363 | |||
1364 | /* Used by CM_SCALE_FCLK */ | ||
1365 | #define OMAP4430_SCALE_FCLK_SHIFT (1 << 0) | ||
1366 | #define OMAP4430_SCALE_FCLK_MASK BITFIELD(0, 0) | ||
1367 | |||
1368 | /* Used by CM_L4CFG_DYNAMICDEP */ | ||
1369 | #define OMAP4430_SDMA_DYNDEP_SHIFT (1 << 11) | ||
1370 | #define OMAP4430_SDMA_DYNDEP_MASK BITFIELD(11, 11) | ||
1371 | |||
1372 | /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */ | ||
1373 | #define OMAP4430_SDMA_STATDEP_SHIFT (1 << 11) | ||
1374 | #define OMAP4430_SDMA_STATDEP_MASK BITFIELD(11, 11) | ||
1375 | |||
1376 | /* Used by CM_CLKSEL_ABE */ | ||
1377 | #define OMAP4430_SLIMBUS_CLK_GATE_SHIFT (1 << 10) | ||
1378 | #define OMAP4430_SLIMBUS_CLK_GATE_MASK BITFIELD(10, 10) | ||
1379 | |||
1380 | /* | ||
1381 | * Used by CM_EMU_DEBUGSS_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, | ||
1382 | * CM_DUCATI_DUCATI_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, CM_GFX_GFX_CLKCTRL, | ||
1383 | * CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL, | ||
1384 | * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, | ||
1385 | * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL, | ||
1386 | * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL, | ||
1387 | * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL, | ||
1388 | * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_CAM_FDIF_CLKCTRL, | ||
1389 | * CM_CAM_ISS_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, | ||
1390 | * CM_IVAHD_IVAHD_CLKCTRL, CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, | ||
1391 | * CM_MPU_MPU_CLKCTRL, CM_TESLA_TESLA_CLKCTRL, CM1_ABE_AESS_CLKCTRL | ||
1392 | */ | ||
1393 | #define OMAP4430_STBYST_SHIFT (1 << 18) | ||
1394 | #define OMAP4430_STBYST_MASK BITFIELD(18, 18) | ||
1395 | |||
1396 | /* | ||
1397 | * Used by CM_IDLEST_DPLL_PER, CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB, | ||
1398 | * CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDRPHY, | ||
1399 | * CM_IDLEST_DPLL_IVA, CM_IDLEST_DPLL_MPU | ||
1400 | */ | ||
1401 | #define OMAP4430_ST_DPLL_CLK_SHIFT (1 << 0) | ||
1402 | #define OMAP4430_ST_DPLL_CLK_MASK BITFIELD(0, 0) | ||
1403 | |||
1404 | /* Used by CM_CLKDCOLDO_DPLL_USB */ | ||
1405 | #define OMAP4430_ST_DPLL_CLKDCOLDO_SHIFT (1 << 9) | ||
1406 | #define OMAP4430_ST_DPLL_CLKDCOLDO_MASK BITFIELD(9, 9) | ||
1407 | |||
1408 | /* | ||
1409 | * Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB, CM_DIV_M2_DPLL_CORE_RESTORE, | ||
1410 | * CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY, | ||
1411 | * CM_DIV_M2_DPLL_MPU | ||
1412 | */ | ||
1413 | #define OMAP4430_ST_DPLL_CLKOUT_SHIFT (1 << 9) | ||
1414 | #define OMAP4430_ST_DPLL_CLKOUT_MASK BITFIELD(9, 9) | ||
1415 | |||
1416 | /* | ||
1417 | * Used by CM_DIV_M3_DPLL_PER, CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_ABE, | ||
1418 | * CM_DIV_M3_DPLL_CORE | ||
1419 | */ | ||
1420 | #define OMAP4430_ST_DPLL_CLKOUTHIF_SHIFT (1 << 9) | ||
1421 | #define OMAP4430_ST_DPLL_CLKOUTHIF_MASK BITFIELD(9, 9) | ||
1422 | |||
1423 | /* Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO, CM_DIV_M2_DPLL_ABE */ | ||
1424 | #define OMAP4430_ST_DPLL_CLKOUTX2_SHIFT (1 << 11) | ||
1425 | #define OMAP4430_ST_DPLL_CLKOUTX2_MASK BITFIELD(11, 11) | ||
1426 | |||
1427 | /* | ||
1428 | * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE, | ||
1429 | * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA | ||
1430 | */ | ||
1431 | #define OMAP4430_ST_HSDIVIDER_CLKOUT1_SHIFT (1 << 9) | ||
1432 | #define OMAP4430_ST_HSDIVIDER_CLKOUT1_MASK BITFIELD(9, 9) | ||
1433 | |||
1434 | /* | ||
1435 | * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE, | ||
1436 | * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA | ||
1437 | */ | ||
1438 | #define OMAP4430_ST_HSDIVIDER_CLKOUT2_SHIFT (1 << 9) | ||
1439 | #define OMAP4430_ST_HSDIVIDER_CLKOUT2_MASK BITFIELD(9, 9) | ||
1440 | |||
1441 | /* | ||
1442 | * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE, | ||
1443 | * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY | ||
1444 | */ | ||
1445 | #define OMAP4430_ST_HSDIVIDER_CLKOUT3_SHIFT (1 << 9) | ||
1446 | #define OMAP4430_ST_HSDIVIDER_CLKOUT3_MASK BITFIELD(9, 9) | ||
1447 | |||
1448 | /* | ||
1449 | * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE, | ||
1450 | * CM_DIV_M7_DPLL_CORE | ||
1451 | */ | ||
1452 | #define OMAP4430_ST_HSDIVIDER_CLKOUT4_SHIFT (1 << 9) | ||
1453 | #define OMAP4430_ST_HSDIVIDER_CLKOUT4_MASK BITFIELD(9, 9) | ||
1454 | |||
1455 | /* Used by CM_SYS_CLKSEL */ | ||
1456 | #define OMAP4430_SYS_CLKSEL_SHIFT (1 << 0) | ||
1457 | #define OMAP4430_SYS_CLKSEL_MASK BITFIELD(0, 2) | ||
1458 | |||
1459 | /* Used by CM_L4CFG_DYNAMICDEP */ | ||
1460 | #define OMAP4430_TESLA_DYNDEP_SHIFT (1 << 1) | ||
1461 | #define OMAP4430_TESLA_DYNDEP_MASK BITFIELD(1, 1) | ||
1462 | |||
1463 | /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */ | ||
1464 | #define OMAP4430_TESLA_STATDEP_SHIFT (1 << 1) | ||
1465 | #define OMAP4430_TESLA_STATDEP_MASK BITFIELD(1, 1) | ||
1466 | |||
1467 | /* | ||
1468 | * Used by CM_EMU_DYNAMICDEP, CM_D2D_DYNAMICDEP, CM_DUCATI_DYNAMICDEP, | ||
1469 | * CM_L3_1_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, | ||
1470 | * CM_L4PER_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP | ||
1471 | */ | ||
1472 | #define OMAP4430_WINDOWSIZE_SHIFT (1 << 24) | ||
1473 | #define OMAP4430_WINDOWSIZE_MASK BITFIELD(24, 27) | ||
1474 | #endif | ||
diff --git a/arch/arm/mach-omap2/cm.c b/arch/arm/mach-omap2/cm.c index 8eb2dab8c7db..58e4a1c557d8 100644 --- a/arch/arm/mach-omap2/cm.c +++ b/arch/arm/mach-omap2/cm.c | |||
@@ -21,6 +21,8 @@ | |||
21 | 21 | ||
22 | #include <asm/atomic.h> | 22 | #include <asm/atomic.h> |
23 | 23 | ||
24 | #include <plat/common.h> | ||
25 | |||
24 | #include "cm.h" | 26 | #include "cm.h" |
25 | #include "cm-regbits-24xx.h" | 27 | #include "cm-regbits-24xx.h" |
26 | #include "cm-regbits-34xx.h" | 28 | #include "cm-regbits-34xx.h" |
@@ -61,9 +63,8 @@ int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift) | |||
61 | mask = 1 << idlest_shift; | 63 | mask = 1 << idlest_shift; |
62 | 64 | ||
63 | /* XXX should be OMAP2 CM */ | 65 | /* XXX should be OMAP2 CM */ |
64 | while (((cm_read_mod_reg(prcm_mod, cm_idlest_reg) & mask) != ena) && | 66 | omap_test_timeout(((cm_read_mod_reg(prcm_mod, cm_idlest_reg) & mask) == ena), |
65 | (i++ < MAX_MODULE_READY_TIME)) | 67 | MAX_MODULE_READY_TIME, i); |
66 | udelay(1); | ||
67 | 68 | ||
68 | return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY; | 69 | return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY; |
69 | } | 70 | } |
diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h index a2fcfcc253cc..90a4086fbdf4 100644 --- a/arch/arm/mach-omap2/cm.h +++ b/arch/arm/mach-omap2/cm.h | |||
@@ -4,8 +4,8 @@ | |||
4 | /* | 4 | /* |
5 | * OMAP2/3 Clock Management (CM) register definitions | 5 | * OMAP2/3 Clock Management (CM) register definitions |
6 | * | 6 | * |
7 | * Copyright (C) 2007-2008 Texas Instruments, Inc. | 7 | * Copyright (C) 2007-2009 Texas Instruments, Inc. |
8 | * Copyright (C) 2007-2008 Nokia Corporation | 8 | * Copyright (C) 2007-2009 Nokia Corporation |
9 | * | 9 | * |
10 | * Written by Paul Walmsley | 10 | * Written by Paul Walmsley |
11 | * | 11 | * |
@@ -22,6 +22,12 @@ | |||
22 | OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg)) | 22 | OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg)) |
23 | #define OMAP34XX_CM_REGADDR(module, reg) \ | 23 | #define OMAP34XX_CM_REGADDR(module, reg) \ |
24 | OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg)) | 24 | OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg)) |
25 | #define OMAP44XX_CM1_REGADDR(module, reg) \ | ||
26 | OMAP2_L4_IO_ADDRESS(OMAP4430_CM1_BASE + (module) + (reg)) | ||
27 | #define OMAP44XX_CM2_REGADDR(module, reg) \ | ||
28 | OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE + (module) + (reg)) | ||
29 | |||
30 | #include "cm44xx.h" | ||
25 | 31 | ||
26 | /* | 32 | /* |
27 | * Architecture-specific global CM registers | 33 | * Architecture-specific global CM registers |
@@ -89,6 +95,11 @@ | |||
89 | #define OMAP3430_CM_CLKSEL2_EMU 0x0050 | 95 | #define OMAP3430_CM_CLKSEL2_EMU 0x0050 |
90 | #define OMAP3430_CM_CLKSEL3_EMU 0x0054 | 96 | #define OMAP3430_CM_CLKSEL3_EMU 0x0054 |
91 | 97 | ||
98 | /* CM2.CEFUSE_CM2 register offsets */ | ||
99 | |||
100 | /* OMAP4 modulemode control */ | ||
101 | #define OMAP4430_MODULEMODE_HWCTRL 0 | ||
102 | #define OMAP4430_MODULEMODE_SWCTRL 1 | ||
92 | 103 | ||
93 | /* Clock management domain register get/set */ | 104 | /* Clock management domain register get/set */ |
94 | 105 | ||
diff --git a/arch/arm/mach-omap2/cm44xx.h b/arch/arm/mach-omap2/cm44xx.h new file mode 100644 index 000000000000..c575b9b0c041 --- /dev/null +++ b/arch/arm/mach-omap2/cm44xx.h | |||
@@ -0,0 +1,358 @@ | |||
1 | /* | ||
2 | * OMAP44xx CM1 & CM2 instance offset macros | ||
3 | * | ||
4 | * Copyright (C) 2009 Texas Instruments, Inc. | ||
5 | * Copyright (C) 2009 Nokia Corporation | ||
6 | * | ||
7 | * Paul Walmsley (paul@pwsan.com) | ||
8 | * Rajendra Nayak (rnayak@ti.com) | ||
9 | * Benoit Cousson (b-cousson@ti.com) | ||
10 | * | ||
11 | * This file is automatically generated from the OMAP hardware databases. | ||
12 | * We respectfully ask that any modifications to this file be coordinated | ||
13 | * with the public linux-omap@vger.kernel.org mailing list and the | ||
14 | * authors above to ensure that the autogeneration scripts are kept | ||
15 | * up-to-date with the file contents. | ||
16 | * | ||
17 | * This program is free software; you can redistribute it and/or modify | ||
18 | * it under the terms of the GNU General Public License version 2 as | ||
19 | * published by the Free Software Foundation. | ||
20 | */ | ||
21 | |||
22 | #ifndef __ARCH_ARM_MACH_OMAP2_CM44XX_H | ||
23 | #define __ARCH_ARM_MACH_OMAP2_CM44XX_H | ||
24 | |||
25 | |||
26 | /* CM1 */ | ||
27 | |||
28 | |||
29 | /* CM1.OCP_SOCKET_CM1 register offsets */ | ||
30 | #define OMAP4430_REVISION_CM1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_MOD, 0x0000) | ||
31 | #define OMAP4430_CM_CM1_PROFILING_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_MOD, 0x0040) | ||
32 | |||
33 | /* CM1.CKGEN_CM1 register offsets */ | ||
34 | #define OMAP4430_CM_CLKSEL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0000) | ||
35 | #define OMAP4430_CM_CLKSEL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0008) | ||
36 | #define OMAP4430_CM_DLL_CTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0010) | ||
37 | #define OMAP4430_CM_CLKMODE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0020) | ||
38 | #define OMAP4430_CM_IDLEST_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0024) | ||
39 | #define OMAP4430_CM_AUTOIDLE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0028) | ||
40 | #define OMAP4430_CM_CLKSEL_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x002c) | ||
41 | #define OMAP4430_CM_DIV_M2_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0030) | ||
42 | #define OMAP4430_CM_DIV_M3_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0034) | ||
43 | #define OMAP4430_CM_DIV_M4_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0038) | ||
44 | #define OMAP4430_CM_DIV_M5_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x003c) | ||
45 | #define OMAP4430_CM_DIV_M6_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0040) | ||
46 | #define OMAP4430_CM_DIV_M7_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0044) | ||
47 | #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0048) | ||
48 | #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x004c) | ||
49 | #define OMAP4430_CM_EMU_OVERRIDE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0050) | ||
50 | #define OMAP4430_CM_CLKMODE_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0060) | ||
51 | #define OMAP4430_CM_IDLEST_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0064) | ||
52 | #define OMAP4430_CM_AUTOIDLE_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0068) | ||
53 | #define OMAP4430_CM_CLKSEL_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x006c) | ||
54 | #define OMAP4430_CM_DIV_M2_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0070) | ||
55 | #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0088) | ||
56 | #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x008c) | ||
57 | #define OMAP4430_CM_BYPCLK_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x009c) | ||
58 | #define OMAP4430_CM_CLKMODE_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00a0) | ||
59 | #define OMAP4430_CM_IDLEST_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00a4) | ||
60 | #define OMAP4430_CM_AUTOIDLE_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00a8) | ||
61 | #define OMAP4430_CM_CLKSEL_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00ac) | ||
62 | #define OMAP4430_CM_DIV_M4_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00b8) | ||
63 | #define OMAP4430_CM_DIV_M5_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00bc) | ||
64 | #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00c8) | ||
65 | #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00cc) | ||
66 | #define OMAP4430_CM_BYPCLK_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00dc) | ||
67 | #define OMAP4430_CM_CLKMODE_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00e0) | ||
68 | #define OMAP4430_CM_IDLEST_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00e4) | ||
69 | #define OMAP4430_CM_AUTOIDLE_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00e8) | ||
70 | #define OMAP4430_CM_CLKSEL_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00ec) | ||
71 | #define OMAP4430_CM_DIV_M2_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00f0) | ||
72 | #define OMAP4430_CM_DIV_M3_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00f4) | ||
73 | #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0108) | ||
74 | #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x010c) | ||
75 | #define OMAP4430_CM_CLKMODE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0120) | ||
76 | #define OMAP4430_CM_IDLEST_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0124) | ||
77 | #define OMAP4430_CM_AUTOIDLE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0128) | ||
78 | #define OMAP4430_CM_CLKSEL_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x012c) | ||
79 | #define OMAP4430_CM_DIV_M2_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0130) | ||
80 | #define OMAP4430_CM_DIV_M4_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0138) | ||
81 | #define OMAP4430_CM_DIV_M5_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x013c) | ||
82 | #define OMAP4430_CM_DIV_M6_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0140) | ||
83 | #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0148) | ||
84 | #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x014c) | ||
85 | #define OMAP4430_CM_SHADOW_FREQ_CONFIG1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0160) | ||
86 | #define OMAP4430_CM_SHADOW_FREQ_CONFIG2 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0164) | ||
87 | #define OMAP4430_CM_DYN_DEP_PRESCAL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0170) | ||
88 | #define OMAP4430_CM_RESTORE_ST OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0180) | ||
89 | |||
90 | /* CM1.MPU_CM1 register offsets */ | ||
91 | #define OMAP4430_CM_MPU_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x0000) | ||
92 | #define OMAP4430_CM_MPU_STATICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x0004) | ||
93 | #define OMAP4430_CM_MPU_DYNAMICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x0008) | ||
94 | #define OMAP4430_CM_MPU_MPU_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x0020) | ||
95 | |||
96 | /* CM1.TESLA_CM1 register offsets */ | ||
97 | #define OMAP4430_CM_TESLA_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_MOD, 0x0000) | ||
98 | #define OMAP4430_CM_TESLA_STATICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_MOD, 0x0004) | ||
99 | #define OMAP4430_CM_TESLA_DYNAMICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_MOD, 0x0008) | ||
100 | #define OMAP4430_CM_TESLA_TESLA_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_MOD, 0x0020) | ||
101 | |||
102 | /* CM1.ABE_CM1 register offsets */ | ||
103 | #define OMAP4430_CM1_ABE_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0000) | ||
104 | #define OMAP4430_CM1_ABE_L4ABE_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0020) | ||
105 | #define OMAP4430_CM1_ABE_AESS_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0028) | ||
106 | #define OMAP4430_CM1_ABE_PDM_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0030) | ||
107 | #define OMAP4430_CM1_ABE_DMIC_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0038) | ||
108 | #define OMAP4430_CM1_ABE_MCASP_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0040) | ||
109 | #define OMAP4430_CM1_ABE_MCBSP1_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0048) | ||
110 | #define OMAP4430_CM1_ABE_MCBSP2_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0050) | ||
111 | #define OMAP4430_CM1_ABE_MCBSP3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0058) | ||
112 | #define OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0060) | ||
113 | #define OMAP4430_CM1_ABE_TIMER5_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0068) | ||
114 | #define OMAP4430_CM1_ABE_TIMER6_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0070) | ||
115 | #define OMAP4430_CM1_ABE_TIMER7_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0078) | ||
116 | #define OMAP4430_CM1_ABE_TIMER8_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0080) | ||
117 | #define OMAP4430_CM1_ABE_WDT3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0088) | ||
118 | |||
119 | /* CM1.RESTORE_CM1 register offsets */ | ||
120 | #define OMAP4430_CM_CLKSEL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0000) | ||
121 | #define OMAP4430_CM_DIV_M2_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0004) | ||
122 | #define OMAP4430_CM_DIV_M3_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0008) | ||
123 | #define OMAP4430_CM_DIV_M4_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x000c) | ||
124 | #define OMAP4430_CM_DIV_M5_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0010) | ||
125 | #define OMAP4430_CM_DIV_M6_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0014) | ||
126 | #define OMAP4430_CM_DIV_M7_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0018) | ||
127 | #define OMAP4430_CM_CLKSEL_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x001c) | ||
128 | #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0020) | ||
129 | #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0024) | ||
130 | #define OMAP4430_CM_CLKMODE_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0028) | ||
131 | #define OMAP4430_CM_SHADOW_FREQ_CONFIG1_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x002c) | ||
132 | #define OMAP4430_CM_AUTOIDLE_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0030) | ||
133 | #define OMAP4430_CM_MPU_CLKSTCTRL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0034) | ||
134 | |||
135 | /* CM2 */ | ||
136 | |||
137 | |||
138 | /* CM2.OCP_SOCKET_CM2 register offsets */ | ||
139 | #define OMAP4430_REVISION_CM2 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_OCP_SOCKET_MOD, 0x0000) | ||
140 | #define OMAP4430_CM_CM2_PROFILING_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_OCP_SOCKET_MOD, 0x0040) | ||
141 | |||
142 | /* CM2.CKGEN_CM2 register offsets */ | ||
143 | #define OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0000) | ||
144 | #define OMAP4430_CM_CLKSEL_USB_60MHZ OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0004) | ||
145 | #define OMAP4430_CM_SCALE_FCLK OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0008) | ||
146 | #define OMAP4430_CM_CORE_DVFS_PERF1 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0010) | ||
147 | #define OMAP4430_CM_CORE_DVFS_PERF2 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0014) | ||
148 | #define OMAP4430_CM_CORE_DVFS_PERF3 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0018) | ||
149 | #define OMAP4430_CM_CORE_DVFS_PERF4 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x001c) | ||
150 | #define OMAP4430_CM_CORE_DVFS_CURRENT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0024) | ||
151 | #define OMAP4430_CM_IVA_DVFS_PERF_TESLA OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0028) | ||
152 | #define OMAP4430_CM_IVA_DVFS_PERF_IVAHD OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x002c) | ||
153 | #define OMAP4430_CM_IVA_DVFS_PERF_ABE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0030) | ||
154 | #define OMAP4430_CM_IVA_DVFS_CURRENT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0038) | ||
155 | #define OMAP4430_CM_CLKMODE_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0040) | ||
156 | #define OMAP4430_CM_IDLEST_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0044) | ||
157 | #define OMAP4430_CM_AUTOIDLE_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0048) | ||
158 | #define OMAP4430_CM_CLKSEL_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x004c) | ||
159 | #define OMAP4430_CM_DIV_M2_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0050) | ||
160 | #define OMAP4430_CM_DIV_M3_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0054) | ||
161 | #define OMAP4430_CM_DIV_M4_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0058) | ||
162 | #define OMAP4430_CM_DIV_M5_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x005c) | ||
163 | #define OMAP4430_CM_DIV_M6_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0060) | ||
164 | #define OMAP4430_CM_DIV_M7_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0064) | ||
165 | #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0068) | ||
166 | #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x006c) | ||
167 | #define OMAP4430_CM_EMU_OVERRIDE_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0070) | ||
168 | #define OMAP4430_CM_CLKMODE_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0080) | ||
169 | #define OMAP4430_CM_IDLEST_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0084) | ||
170 | #define OMAP4430_CM_AUTOIDLE_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0088) | ||
171 | #define OMAP4430_CM_CLKSEL_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x008c) | ||
172 | #define OMAP4430_CM_DIV_M2_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0090) | ||
173 | #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00a8) | ||
174 | #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00ac) | ||
175 | #define OMAP4430_CM_CLKDCOLDO_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00b4) | ||
176 | #define OMAP4430_CM_CLKMODE_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00c0) | ||
177 | #define OMAP4430_CM_IDLEST_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00c4) | ||
178 | #define OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00c8) | ||
179 | #define OMAP4430_CM_CLKSEL_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00cc) | ||
180 | #define OMAP4430_CM_DIV_M2_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00d0) | ||
181 | #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00e8) | ||
182 | #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00ec) | ||
183 | |||
184 | /* CM2.ALWAYS_ON_CM2 register offsets */ | ||
185 | #define OMAP4430_CM_ALWON_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0000) | ||
186 | #define OMAP4430_CM_ALWON_MDMINTC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0020) | ||
187 | #define OMAP4430_CM_ALWON_SR_MPU_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0028) | ||
188 | #define OMAP4430_CM_ALWON_SR_IVA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0030) | ||
189 | #define OMAP4430_CM_ALWON_SR_CORE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0038) | ||
190 | |||
191 | /* CM2.CORE_CM2 register offsets */ | ||
192 | #define OMAP4430_CM_L3_1_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0000) | ||
193 | #define OMAP4430_CM_L3_1_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0008) | ||
194 | #define OMAP4430_CM_L3_1_L3_1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0020) | ||
195 | #define OMAP4430_CM_L3_2_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0100) | ||
196 | #define OMAP4430_CM_L3_2_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0108) | ||
197 | #define OMAP4430_CM_L3_2_L3_2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0120) | ||
198 | #define OMAP4430_CM_L3_2_GPMC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0128) | ||
199 | #define OMAP4430_CM_L3_2_OCMC_RAM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0130) | ||
200 | #define OMAP4430_CM_DUCATI_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0200) | ||
201 | #define OMAP4430_CM_DUCATI_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0204) | ||
202 | #define OMAP4430_CM_DUCATI_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0208) | ||
203 | #define OMAP4430_CM_DUCATI_DUCATI_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0220) | ||
204 | #define OMAP4430_CM_SDMA_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0300) | ||
205 | #define OMAP4430_CM_SDMA_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0304) | ||
206 | #define OMAP4430_CM_SDMA_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0308) | ||
207 | #define OMAP4430_CM_SDMA_SDMA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0320) | ||
208 | #define OMAP4430_CM_MEMIF_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0400) | ||
209 | #define OMAP4430_CM_MEMIF_DMM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0420) | ||
210 | #define OMAP4430_CM_MEMIF_EMIF_FW_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0428) | ||
211 | #define OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0430) | ||
212 | #define OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0438) | ||
213 | #define OMAP4430_CM_MEMIF_DLL_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0440) | ||
214 | #define OMAP4430_CM_MEMIF_EMIF_H1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0450) | ||
215 | #define OMAP4430_CM_MEMIF_EMIF_H2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0458) | ||
216 | #define OMAP4430_CM_MEMIF_DLL_H_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0460) | ||
217 | #define OMAP4430_CM_D2D_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0500) | ||
218 | #define OMAP4430_CM_D2D_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0504) | ||
219 | #define OMAP4430_CM_D2D_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0508) | ||
220 | #define OMAP4430_CM_D2D_SAD2D_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0520) | ||
221 | #define OMAP4430_CM_D2D_MODEM_ICR_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0528) | ||
222 | #define OMAP4430_CM_D2D_SAD2D_FW_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0530) | ||
223 | #define OMAP4430_CM_L4CFG_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0600) | ||
224 | #define OMAP4430_CM_L4CFG_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0608) | ||
225 | #define OMAP4430_CM_L4CFG_L4_CFG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0620) | ||
226 | #define OMAP4430_CM_L4CFG_HW_SEM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0628) | ||
227 | #define OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0630) | ||
228 | #define OMAP4430_CM_L4CFG_SAR_ROM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0638) | ||
229 | #define OMAP4430_CM_L3INSTR_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0700) | ||
230 | #define OMAP4430_CM_L3INSTR_L3_3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0720) | ||
231 | #define OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0728) | ||
232 | #define OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0740) | ||
233 | |||
234 | /* CM2.IVAHD_CM2 register offsets */ | ||
235 | #define OMAP4430_CM_IVAHD_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0000) | ||
236 | #define OMAP4430_CM_IVAHD_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0004) | ||
237 | #define OMAP4430_CM_IVAHD_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0008) | ||
238 | #define OMAP4430_CM_IVAHD_IVAHD_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0020) | ||
239 | #define OMAP4430_CM_IVAHD_SL2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0028) | ||
240 | |||
241 | /* CM2.CAM_CM2 register offsets */ | ||
242 | #define OMAP4430_CM_CAM_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0000) | ||
243 | #define OMAP4430_CM_CAM_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0004) | ||
244 | #define OMAP4430_CM_CAM_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0008) | ||
245 | #define OMAP4430_CM_CAM_ISS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0020) | ||
246 | #define OMAP4430_CM_CAM_FDIF_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0028) | ||
247 | |||
248 | /* CM2.DSS_CM2 register offsets */ | ||
249 | #define OMAP4430_CM_DSS_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0000) | ||
250 | #define OMAP4430_CM_DSS_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0004) | ||
251 | #define OMAP4430_CM_DSS_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0008) | ||
252 | #define OMAP4430_CM_DSS_DSS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0020) | ||
253 | #define OMAP4430_CM_DSS_DEISS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0028) | ||
254 | |||
255 | /* CM2.GFX_CM2 register offsets */ | ||
256 | #define OMAP4430_CM_GFX_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x0000) | ||
257 | #define OMAP4430_CM_GFX_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x0004) | ||
258 | #define OMAP4430_CM_GFX_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x0008) | ||
259 | #define OMAP4430_CM_GFX_GFX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x0020) | ||
260 | |||
261 | /* CM2.L3INIT_CM2 register offsets */ | ||
262 | #define OMAP4430_CM_L3INIT_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0000) | ||
263 | #define OMAP4430_CM_L3INIT_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0004) | ||
264 | #define OMAP4430_CM_L3INIT_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0008) | ||
265 | #define OMAP4430_CM_L3INIT_MMC1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0028) | ||
266 | #define OMAP4430_CM_L3INIT_MMC2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0030) | ||
267 | #define OMAP4430_CM_L3INIT_HSI_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0038) | ||
268 | #define OMAP4430_CM_L3INIT_UNIPRO1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0040) | ||
269 | #define OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0058) | ||
270 | #define OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0060) | ||
271 | #define OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0068) | ||
272 | #define OMAP4430_CM_L3INIT_P1500_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0078) | ||
273 | #define OMAP4430_CM_L3INIT_EMAC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0080) | ||
274 | #define OMAP4430_CM_L3INIT_SATA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0088) | ||
275 | #define OMAP4430_CM_L3INIT_TPPSS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0090) | ||
276 | #define OMAP4430_CM_L3INIT_PCIESS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0098) | ||
277 | #define OMAP4430_CM_L3INIT_CCPTX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00a8) | ||
278 | #define OMAP4430_CM_L3INIT_XHPI_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00c0) | ||
279 | #define OMAP4430_CM_L3INIT_MMC6_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00c8) | ||
280 | #define OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00d0) | ||
281 | #define OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00e0) | ||
282 | |||
283 | /* CM2.L4PER_CM2 register offsets */ | ||
284 | #define OMAP4430_CM_L4PER_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0000) | ||
285 | #define OMAP4430_CM_L4PER_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0008) | ||
286 | #define OMAP4430_CM_L4PER_ADC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0020) | ||
287 | #define OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0028) | ||
288 | #define OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0030) | ||
289 | #define OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0038) | ||
290 | #define OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0040) | ||
291 | #define OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0048) | ||
292 | #define OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0050) | ||
293 | #define OMAP4430_CM_L4PER_ELM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0058) | ||
294 | #define OMAP4430_CM_L4PER_GPIO2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0060) | ||
295 | #define OMAP4430_CM_L4PER_GPIO3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0068) | ||
296 | #define OMAP4430_CM_L4PER_GPIO4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0070) | ||
297 | #define OMAP4430_CM_L4PER_GPIO5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0078) | ||
298 | #define OMAP4430_CM_L4PER_GPIO6_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0080) | ||
299 | #define OMAP4430_CM_L4PER_HDQ1W_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0088) | ||
300 | #define OMAP4430_CM_L4PER_HECC1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0090) | ||
301 | #define OMAP4430_CM_L4PER_HECC2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0098) | ||
302 | #define OMAP4430_CM_L4PER_I2C1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00a0) | ||
303 | #define OMAP4430_CM_L4PER_I2C2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00a8) | ||
304 | #define OMAP4430_CM_L4PER_I2C3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00b0) | ||
305 | #define OMAP4430_CM_L4PER_I2C4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00b8) | ||
306 | #define OMAP4430_CM_L4PER_L4PER_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00c0) | ||
307 | #define OMAP4430_CM_L4PER_MCASP2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00d0) | ||
308 | #define OMAP4430_CM_L4PER_MCASP3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00d8) | ||
309 | #define OMAP4430_CM_L4PER_MCBSP4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00e0) | ||
310 | #define OMAP4430_CM_L4PER_MGATE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00e8) | ||
311 | #define OMAP4430_CM_L4PER_MCSPI1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00f0) | ||
312 | #define OMAP4430_CM_L4PER_MCSPI2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00f8) | ||
313 | #define OMAP4430_CM_L4PER_MCSPI3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0100) | ||
314 | #define OMAP4430_CM_L4PER_MCSPI4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0108) | ||
315 | #define OMAP4430_CM_L4PER_MMCSD3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0120) | ||
316 | #define OMAP4430_CM_L4PER_MMCSD4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0128) | ||
317 | #define OMAP4430_CM_L4PER_MSPROHG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0130) | ||
318 | #define OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0138) | ||
319 | #define OMAP4430_CM_L4PER_UART1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0140) | ||
320 | #define OMAP4430_CM_L4PER_UART2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0148) | ||
321 | #define OMAP4430_CM_L4PER_UART3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0150) | ||
322 | #define OMAP4430_CM_L4PER_UART4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0158) | ||
323 | #define OMAP4430_CM_L4PER_MMCSD5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0160) | ||
324 | #define OMAP4430_CM_L4PER_I2C5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0168) | ||
325 | #define OMAP4430_CM_L4SEC_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0180) | ||
326 | #define OMAP4430_CM_L4SEC_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0184) | ||
327 | #define OMAP4430_CM_L4SEC_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0188) | ||
328 | #define OMAP4430_CM_L4SEC_AES1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01a0) | ||
329 | #define OMAP4430_CM_L4SEC_AES2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01a8) | ||
330 | #define OMAP4430_CM_L4SEC_DES3DES_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01b0) | ||
331 | #define OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01b8) | ||
332 | #define OMAP4430_CM_L4SEC_RNG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01c0) | ||
333 | #define OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01c8) | ||
334 | #define OMAP4430_CM_L4SEC_CRYPTODMA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01d8) | ||
335 | |||
336 | /* CM2.CEFUSE_CM2 register offsets */ | ||
337 | #define OMAP4430_CM_CEFUSE_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_MOD, 0x0000) | ||
338 | #define OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_MOD, 0x0020) | ||
339 | |||
340 | /* CM2.RESTORE_CM2 register offsets */ | ||
341 | #define OMAP4430_CM_L3_1_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0000) | ||
342 | #define OMAP4430_CM_L3_2_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0004) | ||
343 | #define OMAP4430_CM_L4CFG_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0008) | ||
344 | #define OMAP4430_CM_MEMIF_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x000c) | ||
345 | #define OMAP4430_CM_L4PER_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0010) | ||
346 | #define OMAP4430_CM_L3INIT_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0014) | ||
347 | #define OMAP4430_CM_L3INSTR_L3_3_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0018) | ||
348 | #define OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x001c) | ||
349 | #define OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0020) | ||
350 | #define OMAP4430_CM_L4PER_GPIO2_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0024) | ||
351 | #define OMAP4430_CM_L4PER_GPIO3_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0028) | ||
352 | #define OMAP4430_CM_L4PER_GPIO4_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x002c) | ||
353 | #define OMAP4430_CM_L4PER_GPIO5_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0030) | ||
354 | #define OMAP4430_CM_L4PER_GPIO6_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0034) | ||
355 | #define OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0038) | ||
356 | #define OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x003c) | ||
357 | #define OMAP4430_CM_SDMA_STATICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0040) | ||
358 | #endif | ||
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index 733d3dcff98b..18ad93160abb 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c | |||
@@ -27,6 +27,8 @@ | |||
27 | #include <mach/gpio.h> | 27 | #include <mach/gpio.h> |
28 | #include <plat/mmc.h> | 28 | #include <plat/mmc.h> |
29 | 29 | ||
30 | #include "mux.h" | ||
31 | |||
30 | #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE) | 32 | #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE) |
31 | 33 | ||
32 | static struct resource cam_resources[] = { | 34 | static struct resource cam_resources[] = { |
@@ -595,27 +597,40 @@ static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller, | |||
595 | 597 | ||
596 | if (cpu_is_omap34xx()) { | 598 | if (cpu_is_omap34xx()) { |
597 | if (controller_nr == 0) { | 599 | if (controller_nr == 0) { |
598 | omap_cfg_reg(N28_3430_MMC1_CLK); | 600 | omap_mux_init_signal("sdmmc1_clk", |
599 | omap_cfg_reg(M27_3430_MMC1_CMD); | 601 | OMAP_PIN_INPUT_PULLUP); |
600 | omap_cfg_reg(N27_3430_MMC1_DAT0); | 602 | omap_mux_init_signal("sdmmc1_cmd", |
603 | OMAP_PIN_INPUT_PULLUP); | ||
604 | omap_mux_init_signal("sdmmc1_dat0", | ||
605 | OMAP_PIN_INPUT_PULLUP); | ||
601 | if (mmc_controller->slots[0].wires == 4 || | 606 | if (mmc_controller->slots[0].wires == 4 || |
602 | mmc_controller->slots[0].wires == 8) { | 607 | mmc_controller->slots[0].wires == 8) { |
603 | omap_cfg_reg(N26_3430_MMC1_DAT1); | 608 | omap_mux_init_signal("sdmmc1_dat1", |
604 | omap_cfg_reg(N25_3430_MMC1_DAT2); | 609 | OMAP_PIN_INPUT_PULLUP); |
605 | omap_cfg_reg(P28_3430_MMC1_DAT3); | 610 | omap_mux_init_signal("sdmmc1_dat2", |
611 | OMAP_PIN_INPUT_PULLUP); | ||
612 | omap_mux_init_signal("sdmmc1_dat3", | ||
613 | OMAP_PIN_INPUT_PULLUP); | ||
606 | } | 614 | } |
607 | if (mmc_controller->slots[0].wires == 8) { | 615 | if (mmc_controller->slots[0].wires == 8) { |
608 | omap_cfg_reg(P27_3430_MMC1_DAT4); | 616 | omap_mux_init_signal("sdmmc1_dat4", |
609 | omap_cfg_reg(P26_3430_MMC1_DAT5); | 617 | OMAP_PIN_INPUT_PULLUP); |
610 | omap_cfg_reg(R27_3430_MMC1_DAT6); | 618 | omap_mux_init_signal("sdmmc1_dat5", |
611 | omap_cfg_reg(R25_3430_MMC1_DAT7); | 619 | OMAP_PIN_INPUT_PULLUP); |
620 | omap_mux_init_signal("sdmmc1_dat6", | ||
621 | OMAP_PIN_INPUT_PULLUP); | ||
622 | omap_mux_init_signal("sdmmc1_dat7", | ||
623 | OMAP_PIN_INPUT_PULLUP); | ||
612 | } | 624 | } |
613 | } | 625 | } |
614 | if (controller_nr == 1) { | 626 | if (controller_nr == 1) { |
615 | /* MMC2 */ | 627 | /* MMC2 */ |
616 | omap_cfg_reg(AE2_3430_MMC2_CLK); | 628 | omap_mux_init_signal("sdmmc2_clk", |
617 | omap_cfg_reg(AG5_3430_MMC2_CMD); | 629 | OMAP_PIN_INPUT_PULLUP); |
618 | omap_cfg_reg(AH5_3430_MMC2_DAT0); | 630 | omap_mux_init_signal("sdmmc2_cmd", |
631 | OMAP_PIN_INPUT_PULLUP); | ||
632 | omap_mux_init_signal("sdmmc2_dat0", | ||
633 | OMAP_PIN_INPUT_PULLUP); | ||
619 | 634 | ||
620 | /* | 635 | /* |
621 | * For 8 wire configurations, Lines DAT4, 5, 6 and 7 need to be muxed | 636 | * For 8 wire configurations, Lines DAT4, 5, 6 and 7 need to be muxed |
@@ -623,15 +638,22 @@ static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller, | |||
623 | */ | 638 | */ |
624 | if (mmc_controller->slots[0].wires == 4 || | 639 | if (mmc_controller->slots[0].wires == 4 || |
625 | mmc_controller->slots[0].wires == 8) { | 640 | mmc_controller->slots[0].wires == 8) { |
626 | omap_cfg_reg(AH4_3430_MMC2_DAT1); | 641 | omap_mux_init_signal("sdmmc2_dat1", |
627 | omap_cfg_reg(AG4_3430_MMC2_DAT2); | 642 | OMAP_PIN_INPUT_PULLUP); |
628 | omap_cfg_reg(AF4_3430_MMC2_DAT3); | 643 | omap_mux_init_signal("sdmmc2_dat2", |
644 | OMAP_PIN_INPUT_PULLUP); | ||
645 | omap_mux_init_signal("sdmmc2_dat3", | ||
646 | OMAP_PIN_INPUT_PULLUP); | ||
629 | } | 647 | } |
630 | if (mmc_controller->slots[0].wires == 8) { | 648 | if (mmc_controller->slots[0].wires == 8) { |
631 | omap_cfg_reg(AE4_3430_MMC2_DAT4); | 649 | omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4", |
632 | omap_cfg_reg(AH3_3430_MMC2_DAT5); | 650 | OMAP_PIN_INPUT_PULLUP); |
633 | omap_cfg_reg(AF3_3430_MMC2_DAT6); | 651 | omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5", |
634 | omap_cfg_reg(AE3_3430_MMC2_DAT7); | 652 | OMAP_PIN_INPUT_PULLUP); |
653 | omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6", | ||
654 | OMAP_PIN_INPUT_PULLUP); | ||
655 | omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7", | ||
656 | OMAP_PIN_INPUT_PULLUP); | ||
635 | } | 657 | } |
636 | } | 658 | } |
637 | 659 | ||
diff --git a/arch/arm/mach-omap2/dpll.c b/arch/arm/mach-omap2/dpll.c new file mode 100644 index 000000000000..f6055b493294 --- /dev/null +++ b/arch/arm/mach-omap2/dpll.c | |||
@@ -0,0 +1,538 @@ | |||
1 | /* | ||
2 | * OMAP3/4 - specific DPLL control functions | ||
3 | * | ||
4 | * Copyright (C) 2009 Texas Instruments, Inc. | ||
5 | * Copyright (C) 2009 Nokia Corporation | ||
6 | * | ||
7 | * Written by Paul Walmsley | ||
8 | * Testing and integration fixes by Jouni Högander | ||
9 | * | ||
10 | * Parts of this code are based on code written by | ||
11 | * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu | ||
12 | * | ||
13 | * This program is free software; you can redistribute it and/or modify | ||
14 | * it under the terms of the GNU General Public License version 2 as | ||
15 | * published by the Free Software Foundation. | ||
16 | */ | ||
17 | |||
18 | #include <linux/module.h> | ||
19 | #include <linux/kernel.h> | ||
20 | #include <linux/device.h> | ||
21 | #include <linux/list.h> | ||
22 | #include <linux/errno.h> | ||
23 | #include <linux/delay.h> | ||
24 | #include <linux/clk.h> | ||
25 | #include <linux/io.h> | ||
26 | #include <linux/limits.h> | ||
27 | #include <linux/bitops.h> | ||
28 | |||
29 | #include <plat/cpu.h> | ||
30 | #include <plat/clock.h> | ||
31 | #include <plat/sram.h> | ||
32 | #include <asm/div64.h> | ||
33 | #include <asm/clkdev.h> | ||
34 | |||
35 | #include "clock.h" | ||
36 | #include "prm.h" | ||
37 | #include "prm-regbits-34xx.h" | ||
38 | #include "cm.h" | ||
39 | #include "cm-regbits-34xx.h" | ||
40 | |||
41 | /* CM_AUTOIDLE_PLL*.AUTO_* bit values */ | ||
42 | #define DPLL_AUTOIDLE_DISABLE 0x0 | ||
43 | #define DPLL_AUTOIDLE_LOW_POWER_STOP 0x1 | ||
44 | |||
45 | #define MAX_DPLL_WAIT_TRIES 1000000 | ||
46 | |||
47 | |||
48 | /** | ||
49 | * omap3_dpll_recalc - recalculate DPLL rate | ||
50 | * @clk: DPLL struct clk | ||
51 | * | ||
52 | * Recalculate and propagate the DPLL rate. | ||
53 | */ | ||
54 | unsigned long omap3_dpll_recalc(struct clk *clk) | ||
55 | { | ||
56 | return omap2_get_dpll_rate(clk); | ||
57 | } | ||
58 | |||
59 | /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */ | ||
60 | static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits) | ||
61 | { | ||
62 | const struct dpll_data *dd; | ||
63 | u32 v; | ||
64 | |||
65 | dd = clk->dpll_data; | ||
66 | |||
67 | v = __raw_readl(dd->control_reg); | ||
68 | v &= ~dd->enable_mask; | ||
69 | v |= clken_bits << __ffs(dd->enable_mask); | ||
70 | __raw_writel(v, dd->control_reg); | ||
71 | } | ||
72 | |||
73 | /* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */ | ||
74 | static int _omap3_wait_dpll_status(struct clk *clk, u8 state) | ||
75 | { | ||
76 | const struct dpll_data *dd; | ||
77 | int i = 0; | ||
78 | int ret = -EINVAL; | ||
79 | |||
80 | dd = clk->dpll_data; | ||
81 | |||
82 | state <<= __ffs(dd->idlest_mask); | ||
83 | |||
84 | while (((__raw_readl(dd->idlest_reg) & dd->idlest_mask) != state) && | ||
85 | i < MAX_DPLL_WAIT_TRIES) { | ||
86 | i++; | ||
87 | udelay(1); | ||
88 | } | ||
89 | |||
90 | if (i == MAX_DPLL_WAIT_TRIES) { | ||
91 | printk(KERN_ERR "clock: %s failed transition to '%s'\n", | ||
92 | clk->name, (state) ? "locked" : "bypassed"); | ||
93 | } else { | ||
94 | pr_debug("clock: %s transition to '%s' in %d loops\n", | ||
95 | clk->name, (state) ? "locked" : "bypassed", i); | ||
96 | |||
97 | ret = 0; | ||
98 | } | ||
99 | |||
100 | return ret; | ||
101 | } | ||
102 | |||
103 | /* From 3430 TRM ES2 4.7.6.2 */ | ||
104 | static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n) | ||
105 | { | ||
106 | unsigned long fint; | ||
107 | u16 f = 0; | ||
108 | |||
109 | fint = clk->dpll_data->clk_ref->rate / n; | ||
110 | |||
111 | pr_debug("clock: fint is %lu\n", fint); | ||
112 | |||
113 | if (fint >= 750000 && fint <= 1000000) | ||
114 | f = 0x3; | ||
115 | else if (fint > 1000000 && fint <= 1250000) | ||
116 | f = 0x4; | ||
117 | else if (fint > 1250000 && fint <= 1500000) | ||
118 | f = 0x5; | ||
119 | else if (fint > 1500000 && fint <= 1750000) | ||
120 | f = 0x6; | ||
121 | else if (fint > 1750000 && fint <= 2100000) | ||
122 | f = 0x7; | ||
123 | else if (fint > 7500000 && fint <= 10000000) | ||
124 | f = 0xB; | ||
125 | else if (fint > 10000000 && fint <= 12500000) | ||
126 | f = 0xC; | ||
127 | else if (fint > 12500000 && fint <= 15000000) | ||
128 | f = 0xD; | ||
129 | else if (fint > 15000000 && fint <= 17500000) | ||
130 | f = 0xE; | ||
131 | else if (fint > 17500000 && fint <= 21000000) | ||
132 | f = 0xF; | ||
133 | else | ||
134 | pr_debug("clock: unknown freqsel setting for %d\n", n); | ||
135 | |||
136 | return f; | ||
137 | } | ||
138 | |||
139 | /* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */ | ||
140 | |||
141 | /* | ||
142 | * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness | ||
143 | * @clk: pointer to a DPLL struct clk | ||
144 | * | ||
145 | * Instructs a non-CORE DPLL to lock. Waits for the DPLL to report | ||
146 | * readiness before returning. Will save and restore the DPLL's | ||
147 | * autoidle state across the enable, per the CDP code. If the DPLL | ||
148 | * locked successfully, return 0; if the DPLL did not lock in the time | ||
149 | * allotted, or DPLL3 was passed in, return -EINVAL. | ||
150 | */ | ||
151 | static int _omap3_noncore_dpll_lock(struct clk *clk) | ||
152 | { | ||
153 | u8 ai; | ||
154 | int r; | ||
155 | |||
156 | pr_debug("clock: locking DPLL %s\n", clk->name); | ||
157 | |||
158 | ai = omap3_dpll_autoidle_read(clk); | ||
159 | |||
160 | omap3_dpll_deny_idle(clk); | ||
161 | |||
162 | _omap3_dpll_write_clken(clk, DPLL_LOCKED); | ||
163 | |||
164 | r = _omap3_wait_dpll_status(clk, 1); | ||
165 | |||
166 | if (ai) | ||
167 | omap3_dpll_allow_idle(clk); | ||
168 | |||
169 | return r; | ||
170 | } | ||
171 | |||
172 | /* | ||
173 | * _omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness | ||
174 | * @clk: pointer to a DPLL struct clk | ||
175 | * | ||
176 | * Instructs a non-CORE DPLL to enter low-power bypass mode. In | ||
177 | * bypass mode, the DPLL's rate is set equal to its parent clock's | ||
178 | * rate. Waits for the DPLL to report readiness before returning. | ||
179 | * Will save and restore the DPLL's autoidle state across the enable, | ||
180 | * per the CDP code. If the DPLL entered bypass mode successfully, | ||
181 | * return 0; if the DPLL did not enter bypass in the time allotted, or | ||
182 | * DPLL3 was passed in, or the DPLL does not support low-power bypass, | ||
183 | * return -EINVAL. | ||
184 | */ | ||
185 | static int _omap3_noncore_dpll_bypass(struct clk *clk) | ||
186 | { | ||
187 | int r; | ||
188 | u8 ai; | ||
189 | |||
190 | if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) | ||
191 | return -EINVAL; | ||
192 | |||
193 | pr_debug("clock: configuring DPLL %s for low-power bypass\n", | ||
194 | clk->name); | ||
195 | |||
196 | ai = omap3_dpll_autoidle_read(clk); | ||
197 | |||
198 | _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_BYPASS); | ||
199 | |||
200 | r = _omap3_wait_dpll_status(clk, 0); | ||
201 | |||
202 | if (ai) | ||
203 | omap3_dpll_allow_idle(clk); | ||
204 | else | ||
205 | omap3_dpll_deny_idle(clk); | ||
206 | |||
207 | return r; | ||
208 | } | ||
209 | |||
210 | /* | ||
211 | * _omap3_noncore_dpll_stop - instruct a DPLL to stop | ||
212 | * @clk: pointer to a DPLL struct clk | ||
213 | * | ||
214 | * Instructs a non-CORE DPLL to enter low-power stop. Will save and | ||
215 | * restore the DPLL's autoidle state across the stop, per the CDP | ||
216 | * code. If DPLL3 was passed in, or the DPLL does not support | ||
217 | * low-power stop, return -EINVAL; otherwise, return 0. | ||
218 | */ | ||
219 | static int _omap3_noncore_dpll_stop(struct clk *clk) | ||
220 | { | ||
221 | u8 ai; | ||
222 | |||
223 | if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP))) | ||
224 | return -EINVAL; | ||
225 | |||
226 | pr_debug("clock: stopping DPLL %s\n", clk->name); | ||
227 | |||
228 | ai = omap3_dpll_autoidle_read(clk); | ||
229 | |||
230 | _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_STOP); | ||
231 | |||
232 | if (ai) | ||
233 | omap3_dpll_allow_idle(clk); | ||
234 | else | ||
235 | omap3_dpll_deny_idle(clk); | ||
236 | |||
237 | return 0; | ||
238 | } | ||
239 | |||
240 | /** | ||
241 | * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode | ||
242 | * @clk: pointer to a DPLL struct clk | ||
243 | * | ||
244 | * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock. | ||
245 | * The choice of modes depends on the DPLL's programmed rate: if it is | ||
246 | * the same as the DPLL's parent clock, it will enter bypass; | ||
247 | * otherwise, it will enter lock. This code will wait for the DPLL to | ||
248 | * indicate readiness before returning, unless the DPLL takes too long | ||
249 | * to enter the target state. Intended to be used as the struct clk's | ||
250 | * enable function. If DPLL3 was passed in, or the DPLL does not | ||
251 | * support low-power stop, or if the DPLL took too long to enter | ||
252 | * bypass or lock, return -EINVAL; otherwise, return 0. | ||
253 | */ | ||
254 | int omap3_noncore_dpll_enable(struct clk *clk) | ||
255 | { | ||
256 | int r; | ||
257 | struct dpll_data *dd; | ||
258 | |||
259 | dd = clk->dpll_data; | ||
260 | if (!dd) | ||
261 | return -EINVAL; | ||
262 | |||
263 | if (clk->rate == dd->clk_bypass->rate) { | ||
264 | WARN_ON(clk->parent != dd->clk_bypass); | ||
265 | r = _omap3_noncore_dpll_bypass(clk); | ||
266 | } else { | ||
267 | WARN_ON(clk->parent != dd->clk_ref); | ||
268 | r = _omap3_noncore_dpll_lock(clk); | ||
269 | } | ||
270 | /* | ||
271 | *FIXME: this is dubious - if clk->rate has changed, what about | ||
272 | * propagating? | ||
273 | */ | ||
274 | if (!r) | ||
275 | clk->rate = omap2_get_dpll_rate(clk); | ||
276 | |||
277 | return r; | ||
278 | } | ||
279 | |||
280 | /** | ||
281 | * omap3_noncore_dpll_disable - instruct a DPLL to enter low-power stop | ||
282 | * @clk: pointer to a DPLL struct clk | ||
283 | * | ||
284 | * Instructs a non-CORE DPLL to enter low-power stop. This function is | ||
285 | * intended for use in struct clkops. No return value. | ||
286 | */ | ||
287 | void omap3_noncore_dpll_disable(struct clk *clk) | ||
288 | { | ||
289 | _omap3_noncore_dpll_stop(clk); | ||
290 | } | ||
291 | |||
292 | |||
293 | /* Non-CORE DPLL rate set code */ | ||
294 | |||
295 | /* | ||
296 | * omap3_noncore_dpll_program - set non-core DPLL M,N values directly | ||
297 | * @clk: struct clk * of DPLL to set | ||
298 | * @m: DPLL multiplier to set | ||
299 | * @n: DPLL divider to set | ||
300 | * @freqsel: FREQSEL value to set | ||
301 | * | ||
302 | * Program the DPLL with the supplied M, N values, and wait for the DPLL to | ||
303 | * lock.. Returns -EINVAL upon error, or 0 upon success. | ||
304 | */ | ||
305 | int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel) | ||
306 | { | ||
307 | struct dpll_data *dd = clk->dpll_data; | ||
308 | u32 v; | ||
309 | |||
310 | /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */ | ||
311 | _omap3_noncore_dpll_bypass(clk); | ||
312 | |||
313 | /* Set jitter correction */ | ||
314 | if (!cpu_is_omap44xx()) { | ||
315 | v = __raw_readl(dd->control_reg); | ||
316 | v &= ~dd->freqsel_mask; | ||
317 | v |= freqsel << __ffs(dd->freqsel_mask); | ||
318 | __raw_writel(v, dd->control_reg); | ||
319 | } | ||
320 | |||
321 | /* Set DPLL multiplier, divider */ | ||
322 | v = __raw_readl(dd->mult_div1_reg); | ||
323 | v &= ~(dd->mult_mask | dd->div1_mask); | ||
324 | v |= m << __ffs(dd->mult_mask); | ||
325 | v |= (n - 1) << __ffs(dd->div1_mask); | ||
326 | __raw_writel(v, dd->mult_div1_reg); | ||
327 | |||
328 | /* We let the clock framework set the other output dividers later */ | ||
329 | |||
330 | /* REVISIT: Set ramp-up delay? */ | ||
331 | |||
332 | _omap3_noncore_dpll_lock(clk); | ||
333 | |||
334 | return 0; | ||
335 | } | ||
336 | |||
337 | /** | ||
338 | * omap3_noncore_dpll_set_rate - set non-core DPLL rate | ||
339 | * @clk: struct clk * of DPLL to set | ||
340 | * @rate: rounded target rate | ||
341 | * | ||
342 | * Set the DPLL CLKOUT to the target rate. If the DPLL can enter | ||
343 | * low-power bypass, and the target rate is the bypass source clock | ||
344 | * rate, then configure the DPLL for bypass. Otherwise, round the | ||
345 | * target rate if it hasn't been done already, then program and lock | ||
346 | * the DPLL. Returns -EINVAL upon error, or 0 upon success. | ||
347 | */ | ||
348 | int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate) | ||
349 | { | ||
350 | struct clk *new_parent = NULL; | ||
351 | u16 freqsel = 0; | ||
352 | struct dpll_data *dd; | ||
353 | int ret; | ||
354 | |||
355 | if (!clk || !rate) | ||
356 | return -EINVAL; | ||
357 | |||
358 | dd = clk->dpll_data; | ||
359 | if (!dd) | ||
360 | return -EINVAL; | ||
361 | |||
362 | if (rate == omap2_get_dpll_rate(clk)) | ||
363 | return 0; | ||
364 | |||
365 | /* | ||
366 | * Ensure both the bypass and ref clocks are enabled prior to | ||
367 | * doing anything; we need the bypass clock running to reprogram | ||
368 | * the DPLL. | ||
369 | */ | ||
370 | omap2_clk_enable(dd->clk_bypass); | ||
371 | omap2_clk_enable(dd->clk_ref); | ||
372 | |||
373 | if (dd->clk_bypass->rate == rate && | ||
374 | (clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) { | ||
375 | pr_debug("clock: %s: set rate: entering bypass.\n", clk->name); | ||
376 | |||
377 | ret = _omap3_noncore_dpll_bypass(clk); | ||
378 | if (!ret) | ||
379 | new_parent = dd->clk_bypass; | ||
380 | } else { | ||
381 | if (dd->last_rounded_rate != rate) | ||
382 | omap2_dpll_round_rate(clk, rate); | ||
383 | |||
384 | if (dd->last_rounded_rate == 0) | ||
385 | return -EINVAL; | ||
386 | |||
387 | /* No freqsel on OMAP4 */ | ||
388 | if (!cpu_is_omap44xx()) { | ||
389 | freqsel = _omap3_dpll_compute_freqsel(clk, | ||
390 | dd->last_rounded_n); | ||
391 | if (!freqsel) | ||
392 | WARN_ON(1); | ||
393 | } | ||
394 | |||
395 | pr_debug("clock: %s: set rate: locking rate to %lu.\n", | ||
396 | clk->name, rate); | ||
397 | |||
398 | ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m, | ||
399 | dd->last_rounded_n, freqsel); | ||
400 | if (!ret) | ||
401 | new_parent = dd->clk_ref; | ||
402 | } | ||
403 | if (!ret) { | ||
404 | /* | ||
405 | * Switch the parent clock in the heirarchy, and make sure | ||
406 | * that the new parent's usecount is correct. Note: we | ||
407 | * enable the new parent before disabling the old to avoid | ||
408 | * any unnecessary hardware disable->enable transitions. | ||
409 | */ | ||
410 | if (clk->usecount) { | ||
411 | omap2_clk_enable(new_parent); | ||
412 | omap2_clk_disable(clk->parent); | ||
413 | } | ||
414 | clk_reparent(clk, new_parent); | ||
415 | clk->rate = rate; | ||
416 | } | ||
417 | omap2_clk_disable(dd->clk_ref); | ||
418 | omap2_clk_disable(dd->clk_bypass); | ||
419 | |||
420 | return 0; | ||
421 | } | ||
422 | |||
423 | /* DPLL autoidle read/set code */ | ||
424 | |||
425 | /** | ||
426 | * omap3_dpll_autoidle_read - read a DPLL's autoidle bits | ||
427 | * @clk: struct clk * of the DPLL to read | ||
428 | * | ||
429 | * Return the DPLL's autoidle bits, shifted down to bit 0. Returns | ||
430 | * -EINVAL if passed a null pointer or if the struct clk does not | ||
431 | * appear to refer to a DPLL. | ||
432 | */ | ||
433 | u32 omap3_dpll_autoidle_read(struct clk *clk) | ||
434 | { | ||
435 | const struct dpll_data *dd; | ||
436 | u32 v; | ||
437 | |||
438 | if (!clk || !clk->dpll_data) | ||
439 | return -EINVAL; | ||
440 | |||
441 | dd = clk->dpll_data; | ||
442 | |||
443 | v = __raw_readl(dd->autoidle_reg); | ||
444 | v &= dd->autoidle_mask; | ||
445 | v >>= __ffs(dd->autoidle_mask); | ||
446 | |||
447 | return v; | ||
448 | } | ||
449 | |||
450 | /** | ||
451 | * omap3_dpll_allow_idle - enable DPLL autoidle bits | ||
452 | * @clk: struct clk * of the DPLL to operate on | ||
453 | * | ||
454 | * Enable DPLL automatic idle control. This automatic idle mode | ||
455 | * switching takes effect only when the DPLL is locked, at least on | ||
456 | * OMAP3430. The DPLL will enter low-power stop when its downstream | ||
457 | * clocks are gated. No return value. | ||
458 | */ | ||
459 | void omap3_dpll_allow_idle(struct clk *clk) | ||
460 | { | ||
461 | const struct dpll_data *dd; | ||
462 | u32 v; | ||
463 | |||
464 | if (!clk || !clk->dpll_data) | ||
465 | return; | ||
466 | |||
467 | dd = clk->dpll_data; | ||
468 | |||
469 | /* | ||
470 | * REVISIT: CORE DPLL can optionally enter low-power bypass | ||
471 | * by writing 0x5 instead of 0x1. Add some mechanism to | ||
472 | * optionally enter this mode. | ||
473 | */ | ||
474 | v = __raw_readl(dd->autoidle_reg); | ||
475 | v &= ~dd->autoidle_mask; | ||
476 | v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask); | ||
477 | __raw_writel(v, dd->autoidle_reg); | ||
478 | } | ||
479 | |||
480 | /** | ||
481 | * omap3_dpll_deny_idle - prevent DPLL from automatically idling | ||
482 | * @clk: struct clk * of the DPLL to operate on | ||
483 | * | ||
484 | * Disable DPLL automatic idle control. No return value. | ||
485 | */ | ||
486 | void omap3_dpll_deny_idle(struct clk *clk) | ||
487 | { | ||
488 | const struct dpll_data *dd; | ||
489 | u32 v; | ||
490 | |||
491 | if (!clk || !clk->dpll_data) | ||
492 | return; | ||
493 | |||
494 | dd = clk->dpll_data; | ||
495 | |||
496 | v = __raw_readl(dd->autoidle_reg); | ||
497 | v &= ~dd->autoidle_mask; | ||
498 | v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask); | ||
499 | __raw_writel(v, dd->autoidle_reg); | ||
500 | |||
501 | } | ||
502 | |||
503 | /* Clock control for DPLL outputs */ | ||
504 | |||
505 | /** | ||
506 | * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate | ||
507 | * @clk: DPLL output struct clk | ||
508 | * | ||
509 | * Using parent clock DPLL data, look up DPLL state. If locked, set our | ||
510 | * rate to the dpll_clk * 2; otherwise, just use dpll_clk. | ||
511 | */ | ||
512 | unsigned long omap3_clkoutx2_recalc(struct clk *clk) | ||
513 | { | ||
514 | const struct dpll_data *dd; | ||
515 | unsigned long rate; | ||
516 | u32 v; | ||
517 | struct clk *pclk; | ||
518 | |||
519 | /* Walk up the parents of clk, looking for a DPLL */ | ||
520 | pclk = clk->parent; | ||
521 | while (pclk && !pclk->dpll_data) | ||
522 | pclk = pclk->parent; | ||
523 | |||
524 | /* clk does not have a DPLL as a parent? */ | ||
525 | WARN_ON(!pclk); | ||
526 | |||
527 | dd = pclk->dpll_data; | ||
528 | |||
529 | WARN_ON(!dd->enable_mask); | ||
530 | |||
531 | v = __raw_readl(dd->control_reg) & dd->enable_mask; | ||
532 | v >>= __ffs(dd->enable_mask); | ||
533 | if (v != OMAP3XXX_EN_DPLL_LOCKED) | ||
534 | rate = clk->parent->rate; | ||
535 | else | ||
536 | rate = clk->parent->rate * 2; | ||
537 | return rate; | ||
538 | } | ||
diff --git a/arch/arm/mach-omap2/gpmc-smc91x.c b/arch/arm/mach-omap2/gpmc-smc91x.c index 6083e21b3be6..877c6f5807b7 100644 --- a/arch/arm/mach-omap2/gpmc-smc91x.c +++ b/arch/arm/mach-omap2/gpmc-smc91x.c | |||
@@ -33,17 +33,19 @@ static struct resource gpmc_smc91x_resources[] = { | |||
33 | }; | 33 | }; |
34 | 34 | ||
35 | static struct smc91x_platdata gpmc_smc91x_info = { | 35 | static struct smc91x_platdata gpmc_smc91x_info = { |
36 | .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT | SMC91X_IO_SHIFT_0, | 36 | .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT | SMC91X_IO_SHIFT_0, |
37 | .leda = RPC_LED_100_10, | ||
38 | .ledb = RPC_LED_TX_RX, | ||
37 | }; | 39 | }; |
38 | 40 | ||
39 | static struct platform_device gpmc_smc91x_device = { | 41 | static struct platform_device gpmc_smc91x_device = { |
40 | .name = "smc91x", | 42 | .name = "smc91x", |
41 | .id = -1, | 43 | .id = -1, |
42 | .num_resources = ARRAY_SIZE(gpmc_smc91x_resources), | ||
43 | .resource = gpmc_smc91x_resources, | ||
44 | .dev = { | 44 | .dev = { |
45 | .platform_data = &gpmc_smc91x_info, | 45 | .platform_data = &gpmc_smc91x_info, |
46 | }, | 46 | }, |
47 | .num_resources = ARRAY_SIZE(gpmc_smc91x_resources), | ||
48 | .resource = gpmc_smc91x_resources, | ||
47 | }; | 49 | }; |
48 | 50 | ||
49 | /* | 51 | /* |
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c index e86f5ca180ea..bd8cb5974726 100644 --- a/arch/arm/mach-omap2/gpmc.c +++ b/arch/arm/mach-omap2/gpmc.c | |||
@@ -517,7 +517,7 @@ void __init gpmc_init(void) | |||
517 | ck = "gpmc_fck"; | 517 | ck = "gpmc_fck"; |
518 | l = OMAP34XX_GPMC_BASE; | 518 | l = OMAP34XX_GPMC_BASE; |
519 | } else if (cpu_is_omap44xx()) { | 519 | } else if (cpu_is_omap44xx()) { |
520 | ck = "gpmc_fck"; | 520 | ck = "gpmc_ck"; |
521 | l = OMAP44XX_GPMC_BASE; | 521 | l = OMAP44XX_GPMC_BASE; |
522 | } | 522 | } |
523 | 523 | ||
diff --git a/arch/arm/mach-omap2/i2c.c b/arch/arm/mach-omap2/i2c.c new file mode 100644 index 000000000000..789ca8c02f0c --- /dev/null +++ b/arch/arm/mach-omap2/i2c.c | |||
@@ -0,0 +1,56 @@ | |||
1 | /* | ||
2 | * Helper module for board specific I2C bus registration | ||
3 | * | ||
4 | * Copyright (C) 2009 Nokia Corporation. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or | ||
7 | * modify it under the terms of the GNU General Public License | ||
8 | * version 2 as published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope that it will be useful, but | ||
11 | * WITHOUT ANY WARRANTY; without even the implied warranty of | ||
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | ||
13 | * General Public License for more details. | ||
14 | * | ||
15 | * You should have received a copy of the GNU General Public License | ||
16 | * along with this program; if not, write to the Free Software | ||
17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | ||
18 | * 02110-1301 USA | ||
19 | * | ||
20 | */ | ||
21 | |||
22 | #include <plat/cpu.h> | ||
23 | #include <plat/i2c.h> | ||
24 | #include <plat/mux.h> | ||
25 | |||
26 | #include "mux.h" | ||
27 | |||
28 | int __init omap_register_i2c_bus(int bus_id, u32 clkrate, | ||
29 | struct i2c_board_info const *info, | ||
30 | unsigned len) | ||
31 | { | ||
32 | if (cpu_is_omap24xx()) { | ||
33 | const int omap24xx_pins[][2] = { | ||
34 | { M19_24XX_I2C1_SCL, L15_24XX_I2C1_SDA }, | ||
35 | { J15_24XX_I2C2_SCL, H19_24XX_I2C2_SDA }, | ||
36 | }; | ||
37 | int scl, sda; | ||
38 | |||
39 | scl = omap24xx_pins[bus_id - 1][0]; | ||
40 | sda = omap24xx_pins[bus_id - 1][1]; | ||
41 | omap_cfg_reg(sda); | ||
42 | omap_cfg_reg(scl); | ||
43 | } | ||
44 | |||
45 | /* First I2C bus is not muxable */ | ||
46 | if (cpu_is_omap34xx() && bus_id > 1) { | ||
47 | char mux_name[sizeof("i2c2_scl.i2c2_scl")]; | ||
48 | |||
49 | sprintf(mux_name, "i2c%i_scl.i2c%i_scl", bus_id, bus_id); | ||
50 | omap_mux_init_signal(mux_name, OMAP_PIN_INPUT); | ||
51 | sprintf(mux_name, "i2c%i_sda.i2c%i_sda", bus_id, bus_id); | ||
52 | omap_mux_init_signal(mux_name, OMAP_PIN_INPUT); | ||
53 | } | ||
54 | |||
55 | return omap_plat_register_i2c_bus(bus_id, clkrate, info, len); | ||
56 | } | ||
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index f48a4b2654dd..a091b53657b9 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c | |||
@@ -246,6 +246,31 @@ void __init omap3_check_revision(void) | |||
246 | } | 246 | } |
247 | } | 247 | } |
248 | 248 | ||
249 | void __init omap4_check_revision(void) | ||
250 | { | ||
251 | u32 idcode; | ||
252 | u16 hawkeye; | ||
253 | u8 rev; | ||
254 | char *rev_name = "ES1.0"; | ||
255 | |||
256 | /* | ||
257 | * The IC rev detection is done with hawkeye and rev. | ||
258 | * Note that rev does not map directly to defined processor | ||
259 | * revision numbers as ES1.0 uses value 0. | ||
260 | */ | ||
261 | idcode = read_tap_reg(OMAP_TAP_IDCODE); | ||
262 | hawkeye = (idcode >> 12) & 0xffff; | ||
263 | rev = (idcode >> 28) & 0xff; | ||
264 | |||
265 | if ((hawkeye == 0xb852) && (rev == 0x0)) { | ||
266 | omap_revision = OMAP4430_REV_ES1_0; | ||
267 | pr_info("OMAP%04x %s\n", omap_rev() >> 16, rev_name); | ||
268 | return; | ||
269 | } | ||
270 | |||
271 | pr_err("Unknown OMAP4 CPU id\n"); | ||
272 | } | ||
273 | |||
249 | #define OMAP3_SHOW_FEATURE(feat) \ | 274 | #define OMAP3_SHOW_FEATURE(feat) \ |
250 | if (omap3_has_ ##feat()) \ | 275 | if (omap3_has_ ##feat()) \ |
251 | printk(#feat" "); | 276 | printk(#feat" "); |
@@ -277,10 +302,10 @@ void __init omap3_cpuinfo(void) | |||
277 | } else if (omap3_has_iva() && omap3_has_sgx()) { | 302 | } else if (omap3_has_iva() && omap3_has_sgx()) { |
278 | /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */ | 303 | /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */ |
279 | strcpy(cpu_name, "OMAP3430/3530"); | 304 | strcpy(cpu_name, "OMAP3430/3530"); |
280 | } else if (omap3_has_sgx()) { | 305 | } else if (omap3_has_iva()) { |
281 | omap_revision = OMAP3525_REV(rev); | 306 | omap_revision = OMAP3525_REV(rev); |
282 | strcpy(cpu_name, "OMAP3525"); | 307 | strcpy(cpu_name, "OMAP3525"); |
283 | } else if (omap3_has_iva()) { | 308 | } else if (omap3_has_sgx()) { |
284 | omap_revision = OMAP3515_REV(rev); | 309 | omap_revision = OMAP3515_REV(rev); |
285 | strcpy(cpu_name, "OMAP3515"); | 310 | strcpy(cpu_name, "OMAP3515"); |
286 | } else { | 311 | } else { |
@@ -336,7 +361,7 @@ void __init omap2_check_revision(void) | |||
336 | omap3_check_features(); | 361 | omap3_check_features(); |
337 | omap3_cpuinfo(); | 362 | omap3_cpuinfo(); |
338 | } else if (cpu_is_omap44xx()) { | 363 | } else if (cpu_is_omap44xx()) { |
339 | printk(KERN_INFO "FIXME: CPU revision = OMAP4430\n"); | 364 | omap4_check_revision(); |
340 | return; | 365 | return; |
341 | } else { | 366 | } else { |
342 | pr_err("OMAP revision unknown, please fix!\n"); | 367 | pr_err("OMAP revision unknown, please fix!\n"); |
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 6a4d8e468703..a8749e8017b9 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c | |||
@@ -33,9 +33,9 @@ | |||
33 | #include <plat/sdrc.h> | 33 | #include <plat/sdrc.h> |
34 | #include <plat/gpmc.h> | 34 | #include <plat/gpmc.h> |
35 | #include <plat/serial.h> | 35 | #include <plat/serial.h> |
36 | #include <plat/mux.h> | ||
36 | #include <plat/vram.h> | 37 | #include <plat/vram.h> |
37 | 38 | ||
38 | #ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdev is ready */ | ||
39 | #include "clock.h" | 39 | #include "clock.h" |
40 | 40 | ||
41 | #include <plat/omap-pm.h> | 41 | #include <plat/omap-pm.h> |
@@ -44,7 +44,6 @@ | |||
44 | 44 | ||
45 | #include <plat/clockdomain.h> | 45 | #include <plat/clockdomain.h> |
46 | #include "clockdomains.h" | 46 | #include "clockdomains.h" |
47 | #endif | ||
48 | #include <plat/omap_hwmod.h> | 47 | #include <plat/omap_hwmod.h> |
49 | #include "omap_hwmod_2420.h" | 48 | #include "omap_hwmod_2420.h" |
50 | #include "omap_hwmod_2430.h" | 49 | #include "omap_hwmod_2430.h" |
@@ -321,8 +320,8 @@ void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0, | |||
321 | omap_pm_if_early_init(mpu_opps, dsp_opps, l3_opps); | 320 | omap_pm_if_early_init(mpu_opps, dsp_opps, l3_opps); |
322 | pwrdm_init(powerdomains_omap); | 321 | pwrdm_init(powerdomains_omap); |
323 | clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps); | 322 | clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps); |
324 | omap2_clk_init(); | ||
325 | #endif | 323 | #endif |
324 | omap2_clk_init(); | ||
326 | omap_serial_early_init(); | 325 | omap_serial_early_init(); |
327 | #ifndef CONFIG_ARCH_OMAP4 | 326 | #ifndef CONFIG_ARCH_OMAP4 |
328 | omap_hwmod_late_init(); | 327 | omap_hwmod_late_init(); |
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c index c18a94eca641..e071b3fd1878 100644 --- a/arch/arm/mach-omap2/mux.c +++ b/arch/arm/mach-omap2/mux.c | |||
@@ -27,19 +27,52 @@ | |||
27 | #include <linux/init.h> | 27 | #include <linux/init.h> |
28 | #include <linux/io.h> | 28 | #include <linux/io.h> |
29 | #include <linux/spinlock.h> | 29 | #include <linux/spinlock.h> |
30 | #include <linux/list.h> | ||
31 | #include <linux/ctype.h> | ||
32 | #include <linux/debugfs.h> | ||
33 | #include <linux/seq_file.h> | ||
34 | #include <linux/uaccess.h> | ||
30 | 35 | ||
31 | #include <asm/system.h> | 36 | #include <asm/system.h> |
32 | 37 | ||
33 | #include <plat/control.h> | 38 | #include <plat/control.h> |
34 | #include <plat/mux.h> | 39 | #include <plat/mux.h> |
35 | 40 | ||
36 | #ifdef CONFIG_OMAP_MUX | 41 | #include "mux.h" |
42 | |||
43 | #define OMAP_MUX_BASE_OFFSET 0x30 /* Offset from CTRL_BASE */ | ||
44 | #define OMAP_MUX_BASE_SZ 0x5ca | ||
45 | |||
46 | struct omap_mux_entry { | ||
47 | struct omap_mux mux; | ||
48 | struct list_head node; | ||
49 | }; | ||
50 | |||
51 | static unsigned long mux_phys; | ||
52 | static void __iomem *mux_base; | ||
53 | |||
54 | static inline u16 omap_mux_read(u16 reg) | ||
55 | { | ||
56 | if (cpu_is_omap24xx()) | ||
57 | return __raw_readb(mux_base + reg); | ||
58 | else | ||
59 | return __raw_readw(mux_base + reg); | ||
60 | } | ||
61 | |||
62 | static inline void omap_mux_write(u16 val, u16 reg) | ||
63 | { | ||
64 | if (cpu_is_omap24xx()) | ||
65 | __raw_writeb(val, mux_base + reg); | ||
66 | else | ||
67 | __raw_writew(val, mux_base + reg); | ||
68 | } | ||
69 | |||
70 | #if defined(CONFIG_ARCH_OMAP24XX) && defined(CONFIG_OMAP_MUX) | ||
37 | 71 | ||
38 | static struct omap_mux_cfg arch_mux_cfg; | 72 | static struct omap_mux_cfg arch_mux_cfg; |
39 | 73 | ||
40 | /* NOTE: See mux.h for the enumeration */ | 74 | /* NOTE: See mux.h for the enumeration */ |
41 | 75 | ||
42 | #ifdef CONFIG_ARCH_OMAP24XX | ||
43 | static struct pin_config __initdata_or_module omap24xx_pins[] = { | 76 | static struct pin_config __initdata_or_module omap24xx_pins[] = { |
44 | /* | 77 | /* |
45 | * description mux mux pull pull debug | 78 | * description mux mux pull pull debug |
@@ -249,342 +282,14 @@ MUX_CFG_24XX("AF19_2430_GPIO_85", 0x0113, 3, 0, 0, 1) | |||
249 | 282 | ||
250 | #define OMAP24XX_PINS_SZ ARRAY_SIZE(omap24xx_pins) | 283 | #define OMAP24XX_PINS_SZ ARRAY_SIZE(omap24xx_pins) |
251 | 284 | ||
252 | #else | ||
253 | #define omap24xx_pins NULL | ||
254 | #define OMAP24XX_PINS_SZ 0 | ||
255 | #endif /* CONFIG_ARCH_OMAP24XX */ | ||
256 | |||
257 | #ifdef CONFIG_ARCH_OMAP34XX | ||
258 | static struct pin_config __initdata_or_module omap34xx_pins[] = { | ||
259 | /* | ||
260 | * Name, reg-offset, | ||
261 | * mux-mode | [active-mode | off-mode] | ||
262 | */ | ||
263 | |||
264 | /* 34xx I2C */ | ||
265 | MUX_CFG_34XX("K21_34XX_I2C1_SCL", 0x1ba, | ||
266 | OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP) | ||
267 | MUX_CFG_34XX("J21_34XX_I2C1_SDA", 0x1bc, | ||
268 | OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP) | ||
269 | MUX_CFG_34XX("AF15_34XX_I2C2_SCL", 0x1be, | ||
270 | OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP) | ||
271 | MUX_CFG_34XX("AE15_34XX_I2C2_SDA", 0x1c0, | ||
272 | OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP) | ||
273 | MUX_CFG_34XX("AF14_34XX_I2C3_SCL", 0x1c2, | ||
274 | OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP) | ||
275 | MUX_CFG_34XX("AG14_34XX_I2C3_SDA", 0x1c4, | ||
276 | OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP) | ||
277 | MUX_CFG_34XX("AD26_34XX_I2C4_SCL", 0xa00, | ||
278 | OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP) | ||
279 | MUX_CFG_34XX("AE26_34XX_I2C4_SDA", 0xa02, | ||
280 | OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP) | ||
281 | |||
282 | /* PHY - HSUSB: 12-pin ULPI PHY: Port 1*/ | ||
283 | MUX_CFG_34XX("Y8_3430_USB1HS_PHY_CLK", 0x5da, | ||
284 | OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_OUTPUT) | ||
285 | MUX_CFG_34XX("Y9_3430_USB1HS_PHY_STP", 0x5d8, | ||
286 | OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_OUTPUT) | ||
287 | MUX_CFG_34XX("AA14_3430_USB1HS_PHY_DIR", 0x5ec, | ||
288 | OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN) | ||
289 | MUX_CFG_34XX("AA11_3430_USB1HS_PHY_NXT", 0x5ee, | ||
290 | OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN) | ||
291 | MUX_CFG_34XX("W13_3430_USB1HS_PHY_D0", 0x5dc, | ||
292 | OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN) | ||
293 | MUX_CFG_34XX("W12_3430_USB1HS_PHY_D1", 0x5de, | ||
294 | OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN) | ||
295 | MUX_CFG_34XX("W11_3430_USB1HS_PHY_D2", 0x5e0, | ||
296 | OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN) | ||
297 | MUX_CFG_34XX("Y11_3430_USB1HS_PHY_D3", 0x5ea, | ||
298 | OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN) | ||
299 | MUX_CFG_34XX("W9_3430_USB1HS_PHY_D4", 0x5e4, | ||
300 | OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN) | ||
301 | MUX_CFG_34XX("Y12_3430_USB1HS_PHY_D5", 0x5e6, | ||
302 | OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN) | ||
303 | MUX_CFG_34XX("W8_3430_USB1HS_PHY_D6", 0x5e8, | ||
304 | OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN) | ||
305 | MUX_CFG_34XX("Y13_3430_USB1HS_PHY_D7", 0x5e2, | ||
306 | OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN) | ||
307 | |||
308 | /* PHY - HSUSB: 12-pin ULPI PHY: Port 2*/ | ||
309 | MUX_CFG_34XX("AA8_3430_USB2HS_PHY_CLK", 0x5f0, | ||
310 | OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_OUTPUT) | ||
311 | MUX_CFG_34XX("AA10_3430_USB2HS_PHY_STP", 0x5f2, | ||
312 | OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_OUTPUT) | ||
313 | MUX_CFG_34XX("AA9_3430_USB2HS_PHY_DIR", 0x5f4, | ||
314 | OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN) | ||
315 | MUX_CFG_34XX("AB11_3430_USB2HS_PHY_NXT", 0x5f6, | ||
316 | OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN) | ||
317 | MUX_CFG_34XX("AB10_3430_USB2HS_PHY_D0", 0x5f8, | ||
318 | OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN) | ||
319 | MUX_CFG_34XX("AB9_3430_USB2HS_PHY_D1", 0x5fa, | ||
320 | OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN) | ||
321 | MUX_CFG_34XX("W3_3430_USB2HS_PHY_D2", 0x1d4, | ||
322 | OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN) | ||
323 | MUX_CFG_34XX("T4_3430_USB2HS_PHY_D3", 0x1de, | ||
324 | OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN) | ||
325 | MUX_CFG_34XX("T3_3430_USB2HS_PHY_D4", 0x1d8, | ||
326 | OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN) | ||
327 | MUX_CFG_34XX("R3_3430_USB2HS_PHY_D5", 0x1da, | ||
328 | OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN) | ||
329 | MUX_CFG_34XX("R4_3430_USB2HS_PHY_D6", 0x1dc, | ||
330 | OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN) | ||
331 | MUX_CFG_34XX("T2_3430_USB2HS_PHY_D7", 0x1d6, | ||
332 | OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN) | ||
333 | |||
334 | /* TLL - HSUSB: 12-pin TLL Port 1*/ | ||
335 | MUX_CFG_34XX("Y8_3430_USB1HS_TLL_CLK", 0x5da, | ||
336 | OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN) | ||
337 | MUX_CFG_34XX("Y9_3430_USB1HS_TLL_STP", 0x5d8, | ||
338 | OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLUP) | ||
339 | MUX_CFG_34XX("AA14_3430_USB1HS_TLL_DIR", 0x5ec, | ||
340 | OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN) | ||
341 | MUX_CFG_34XX("AA11_3430_USB1HS_TLL_NXT", 0x5ee, | ||
342 | OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN) | ||
343 | MUX_CFG_34XX("W13_3430_USB1HS_TLL_D0", 0x5dc, | ||
344 | OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN) | ||
345 | MUX_CFG_34XX("W12_3430_USB1HS_TLL_D1", 0x5de, | ||
346 | OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN) | ||
347 | MUX_CFG_34XX("W11_3430_USB1HS_TLL_D2", 0x5e0, | ||
348 | OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN) | ||
349 | MUX_CFG_34XX("Y11_3430_USB1HS_TLL_D3", 0x5ea, | ||
350 | OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN) | ||
351 | MUX_CFG_34XX("W9_3430_USB1HS_TLL_D4", 0x5e4, | ||
352 | OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN) | ||
353 | MUX_CFG_34XX("Y12_3430_USB1HS_TLL_D5", 0x5e6, | ||
354 | OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN) | ||
355 | MUX_CFG_34XX("W8_3430_USB1HS_TLL_D6", 0x5e8, | ||
356 | OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN) | ||
357 | MUX_CFG_34XX("Y13_3430_USB1HS_TLL_D7", 0x5e2, | ||
358 | OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN) | ||
359 | |||
360 | /* TLL - HSUSB: 12-pin TLL Port 2*/ | ||
361 | MUX_CFG_34XX("AA8_3430_USB2HS_TLL_CLK", 0x5f0, | ||
362 | OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN) | ||
363 | MUX_CFG_34XX("AA10_3430_USB2HS_TLL_STP", 0x5f2, | ||
364 | OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLUP) | ||
365 | MUX_CFG_34XX("AA9_3430_USB2HS_TLL_DIR", 0x5f4, | ||
366 | OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN) | ||
367 | MUX_CFG_34XX("AB11_3430_USB2HS_TLL_NXT", 0x5f6, | ||
368 | OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN) | ||
369 | MUX_CFG_34XX("AB10_3430_USB2HS_TLL_D0", 0x5f8, | ||
370 | OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN) | ||
371 | MUX_CFG_34XX("AB9_3430_USB2HS_TLL_D1", 0x5fa, | ||
372 | OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN) | ||
373 | MUX_CFG_34XX("W3_3430_USB2HS_TLL_D2", 0x1d4, | ||
374 | OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN) | ||
375 | MUX_CFG_34XX("T4_3430_USB2HS_TLL_D3", 0x1de, | ||
376 | OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN) | ||
377 | MUX_CFG_34XX("T3_3430_USB2HS_TLL_D4", 0x1d8, | ||
378 | OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN) | ||
379 | MUX_CFG_34XX("R3_3430_USB2HS_TLL_D5", 0x1da, | ||
380 | OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN) | ||
381 | MUX_CFG_34XX("R4_3430_USB2HS_TLL_D6", 0x1dc, | ||
382 | OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN) | ||
383 | MUX_CFG_34XX("T2_3430_USB2HS_TLL_D7", 0x1d6, | ||
384 | OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN) | ||
385 | |||
386 | /* TLL - HSUSB: 12-pin TLL Port 3*/ | ||
387 | MUX_CFG_34XX("AA6_3430_USB3HS_TLL_CLK", 0x180, | ||
388 | OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN) | ||
389 | MUX_CFG_34XX("AB3_3430_USB3HS_TLL_STP", 0x166, | ||
390 | OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLUP) | ||
391 | MUX_CFG_34XX("AA3_3430_USB3HS_TLL_DIR", 0x168, | ||
392 | OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN) | ||
393 | MUX_CFG_34XX("Y3_3430_USB3HS_TLL_NXT", 0x16a, | ||
394 | OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN) | ||
395 | MUX_CFG_34XX("AA5_3430_USB3HS_TLL_D0", 0x186, | ||
396 | OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN) | ||
397 | MUX_CFG_34XX("Y4_3430_USB3HS_TLL_D1", 0x184, | ||
398 | OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN) | ||
399 | MUX_CFG_34XX("Y5_3430_USB3HS_TLL_D2", 0x188, | ||
400 | OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN) | ||
401 | MUX_CFG_34XX("W5_3430_USB3HS_TLL_D3", 0x18a, | ||
402 | OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN) | ||
403 | MUX_CFG_34XX("AB12_3430_USB3HS_TLL_D4", 0x16c, | ||
404 | OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN) | ||
405 | MUX_CFG_34XX("AB13_3430_USB3HS_TLL_D5", 0x16e, | ||
406 | OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN) | ||
407 | MUX_CFG_34XX("AA13_3430_USB3HS_TLL_D6", 0x170, | ||
408 | OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN) | ||
409 | MUX_CFG_34XX("AA12_3430_USB3HS_TLL_D7", 0x172, | ||
410 | OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN) | ||
411 | |||
412 | /* PHY FSUSB: FS Serial for Port 1 (multiple PHY modes supported) */ | ||
413 | MUX_CFG_34XX("AF10_3430_USB1FS_PHY_MM1_RXDP", 0x5d8, | ||
414 | OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN) | ||
415 | MUX_CFG_34XX("AG9_3430_USB1FS_PHY_MM1_RXDM", 0x5ee, | ||
416 | OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN) | ||
417 | MUX_CFG_34XX("W13_3430_USB1FS_PHY_MM1_RXRCV", 0x5dc, | ||
418 | OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN) | ||
419 | MUX_CFG_34XX("W12_3430_USB1FS_PHY_MM1_TXSE0", 0x5de, | ||
420 | OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN) | ||
421 | MUX_CFG_34XX("W11_3430_USB1FS_PHY_MM1_TXDAT", 0x5e0, | ||
422 | OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN) | ||
423 | MUX_CFG_34XX("Y11_3430_USB1FS_PHY_MM1_TXEN_N", 0x5ea, | ||
424 | OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_OUTPUT) | ||
425 | |||
426 | /* PHY FSUSB: FS Serial for Port 2 (multiple PHY modes supported) */ | ||
427 | MUX_CFG_34XX("AF7_3430_USB2FS_PHY_MM2_RXDP", 0x5f2, | ||
428 | OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN) | ||
429 | MUX_CFG_34XX("AH7_3430_USB2FS_PHY_MM2_RXDM", 0x5f6, | ||
430 | OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN) | ||
431 | MUX_CFG_34XX("AB10_3430_USB2FS_PHY_MM2_RXRCV", 0x5f8, | ||
432 | OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN) | ||
433 | MUX_CFG_34XX("AB9_3430_USB2FS_PHY_MM2_TXSE0", 0x5fa, | ||
434 | OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN) | ||
435 | MUX_CFG_34XX("W3_3430_USB2FS_PHY_MM2_TXDAT", 0x1d4, | ||
436 | OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN) | ||
437 | MUX_CFG_34XX("T4_3430_USB2FS_PHY_MM2_TXEN_N", 0x1de, | ||
438 | OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_OUTPUT) | ||
439 | |||
440 | /* PHY FSUSB: FS Serial for Port 3 (multiple PHY modes supported) */ | ||
441 | MUX_CFG_34XX("AH3_3430_USB3FS_PHY_MM3_RXDP", 0x166, | ||
442 | OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN) | ||
443 | MUX_CFG_34XX("AE3_3430_USB3FS_PHY_MM3_RXDM", 0x16a, | ||
444 | OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN) | ||
445 | MUX_CFG_34XX("AD1_3430_USB3FS_PHY_MM3_RXRCV", 0x186, | ||
446 | OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN) | ||
447 | MUX_CFG_34XX("AE1_3430_USB3FS_PHY_MM3_TXSE0", 0x184, | ||
448 | OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN) | ||
449 | MUX_CFG_34XX("AD2_3430_USB3FS_PHY_MM3_TXDAT", 0x188, | ||
450 | OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN) | ||
451 | MUX_CFG_34XX("AC1_3430_USB3FS_PHY_MM3_TXEN_N", 0x18a, | ||
452 | OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_OUTPUT) | ||
453 | |||
454 | |||
455 | /* 34XX GPIO - bidirectional, unless the name has an "_OUT" suffix. | ||
456 | * (Always specify PIN_INPUT, except for names suffixed by "_OUT".) | ||
457 | * No internal pullup/pulldown without "_UP" or "_DOWN" suffix. | ||
458 | */ | ||
459 | MUX_CFG_34XX("AF26_34XX_GPIO0", 0x1e0, | ||
460 | OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT) | ||
461 | MUX_CFG_34XX("AF22_34XX_GPIO9", 0xa18, | ||
462 | OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT) | ||
463 | MUX_CFG_34XX("AG9_34XX_GPIO23", 0x5ee, | ||
464 | OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT) | ||
465 | MUX_CFG_34XX("AH8_34XX_GPIO29", 0x5fa, | ||
466 | OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT) | ||
467 | MUX_CFG_34XX("U8_34XX_GPIO54_OUT", 0x0b4, | ||
468 | OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT) | ||
469 | MUX_CFG_34XX("U8_34XX_GPIO54_DOWN", 0x0b4, | ||
470 | OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT_PULLDOWN) | ||
471 | MUX_CFG_34XX("L8_34XX_GPIO63", 0x0ce, | ||
472 | OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT) | ||
473 | MUX_CFG_34XX("G25_34XX_GPIO86_OUT", 0x0fc, | ||
474 | OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT) | ||
475 | MUX_CFG_34XX("AG4_34XX_GPIO134_OUT", 0x160, | ||
476 | OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT) | ||
477 | MUX_CFG_34XX("AF4_34XX_GPIO135_OUT", 0x162, | ||
478 | OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT) | ||
479 | MUX_CFG_34XX("AE4_34XX_GPIO136_OUT", 0x164, | ||
480 | OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT) | ||
481 | MUX_CFG_34XX("AF6_34XX_GPIO140_UP", 0x16c, | ||
482 | OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT_PULLUP) | ||
483 | MUX_CFG_34XX("AE6_34XX_GPIO141", 0x16e, | ||
484 | OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT) | ||
485 | MUX_CFG_34XX("AF5_34XX_GPIO142", 0x170, | ||
486 | OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT) | ||
487 | MUX_CFG_34XX("AE5_34XX_GPIO143", 0x172, | ||
488 | OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT) | ||
489 | MUX_CFG_34XX("H19_34XX_GPIO164_OUT", 0x19c, | ||
490 | OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT) | ||
491 | MUX_CFG_34XX("J25_34XX_GPIO170", 0x1c6, | ||
492 | OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT) | ||
493 | |||
494 | /* OMAP3 SDRC CKE signals to SDR/DDR ram chips */ | ||
495 | MUX_CFG_34XX("H16_34XX_SDRC_CKE0", 0x262, | ||
496 | OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_OUTPUT) | ||
497 | MUX_CFG_34XX("H17_34XX_SDRC_CKE1", 0x264, | ||
498 | OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_OUTPUT) | ||
499 | |||
500 | /* MMC1 */ | ||
501 | MUX_CFG_34XX("N28_3430_MMC1_CLK", 0x144, | ||
502 | OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP) | ||
503 | MUX_CFG_34XX("M27_3430_MMC1_CMD", 0x146, | ||
504 | OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP) | ||
505 | MUX_CFG_34XX("N27_3430_MMC1_DAT0", 0x148, | ||
506 | OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP) | ||
507 | MUX_CFG_34XX("N26_3430_MMC1_DAT1", 0x14a, | ||
508 | OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP) | ||
509 | MUX_CFG_34XX("N25_3430_MMC1_DAT2", 0x14c, | ||
510 | OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP) | ||
511 | MUX_CFG_34XX("P28_3430_MMC1_DAT3", 0x14e, | ||
512 | OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP) | ||
513 | MUX_CFG_34XX("P27_3430_MMC1_DAT4", 0x150, | ||
514 | OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP) | ||
515 | MUX_CFG_34XX("P26_3430_MMC1_DAT5", 0x152, | ||
516 | OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP) | ||
517 | MUX_CFG_34XX("R27_3430_MMC1_DAT6", 0x154, | ||
518 | OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP) | ||
519 | MUX_CFG_34XX("R25_3430_MMC1_DAT7", 0x156, | ||
520 | OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP) | ||
521 | |||
522 | /* MMC2 */ | ||
523 | MUX_CFG_34XX("AE2_3430_MMC2_CLK", 0x158, | ||
524 | OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP) | ||
525 | MUX_CFG_34XX("AG5_3430_MMC2_CMD", 0x15A, | ||
526 | OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP) | ||
527 | MUX_CFG_34XX("AH5_3430_MMC2_DAT0", 0x15c, | ||
528 | OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP) | ||
529 | MUX_CFG_34XX("AH4_3430_MMC2_DAT1", 0x15e, | ||
530 | OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP) | ||
531 | MUX_CFG_34XX("AG4_3430_MMC2_DAT2", 0x160, | ||
532 | OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP) | ||
533 | MUX_CFG_34XX("AF4_3430_MMC2_DAT3", 0x162, | ||
534 | OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP) | ||
535 | MUX_CFG_34XX("AE4_3430_MMC2_DAT4", 0x164, | ||
536 | OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP) | ||
537 | MUX_CFG_34XX("AH3_3430_MMC2_DAT5", 0x166, | ||
538 | OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP) | ||
539 | MUX_CFG_34XX("AF3_3430_MMC2_DAT6", 0x168, | ||
540 | OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP) | ||
541 | MUX_CFG_34XX("AE3_3430_MMC2_DAT7", 0x16A, | ||
542 | OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP) | ||
543 | |||
544 | /* MMC3 */ | ||
545 | MUX_CFG_34XX("AF10_3430_MMC3_CLK", 0x5d8, | ||
546 | OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLUP) | ||
547 | MUX_CFG_34XX("AC3_3430_MMC3_CMD", 0x1d0, | ||
548 | OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLUP) | ||
549 | MUX_CFG_34XX("AE11_3430_MMC3_DAT0", 0x5e4, | ||
550 | OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLUP) | ||
551 | MUX_CFG_34XX("AH9_3430_MMC3_DAT1", 0x5e6, | ||
552 | OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLUP) | ||
553 | MUX_CFG_34XX("AF13_3430_MMC3_DAT2", 0x5e8, | ||
554 | OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLUP) | ||
555 | MUX_CFG_34XX("AF13_3430_MMC3_DAT3", 0x5e2, | ||
556 | OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLUP) | ||
557 | |||
558 | /* SYS_NIRQ T2 INT1 */ | ||
559 | MUX_CFG_34XX("AF26_34XX_SYS_NIRQ", 0x1E0, | ||
560 | OMAP3_WAKEUP_EN | OMAP34XX_PIN_INPUT_PULLUP | | ||
561 | OMAP34XX_MUX_MODE0) | ||
562 | /* EHCI GPIO's on OMAP3EVM (Rev >= E) */ | ||
563 | MUX_CFG_34XX("AH14_34XX_GPIO21", 0x5ea, | ||
564 | OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT_PULLUP) | ||
565 | MUX_CFG_34XX("AF9_34XX_GPIO22", 0x5ec, | ||
566 | OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT_PULLUP) | ||
567 | MUX_CFG_34XX("U3_34XX_GPIO61", 0x0c8, | ||
568 | OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT_PULLUP) | ||
569 | }; | ||
570 | |||
571 | #define OMAP34XX_PINS_SZ ARRAY_SIZE(omap34xx_pins) | ||
572 | |||
573 | #else | ||
574 | #define omap34xx_pins NULL | ||
575 | #define OMAP34XX_PINS_SZ 0 | ||
576 | #endif /* CONFIG_ARCH_OMAP34XX */ | ||
577 | |||
578 | #if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS) | 285 | #if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS) |
286 | |||
579 | static void __init_or_module omap2_cfg_debug(const struct pin_config *cfg, u16 reg) | 287 | static void __init_or_module omap2_cfg_debug(const struct pin_config *cfg, u16 reg) |
580 | { | 288 | { |
581 | u16 orig; | 289 | u16 orig; |
582 | u8 warn = 0, debug = 0; | 290 | u8 warn = 0, debug = 0; |
583 | 291 | ||
584 | if (cpu_is_omap24xx()) | 292 | orig = omap_mux_read(cfg->mux_reg - OMAP_MUX_BASE_OFFSET); |
585 | orig = omap_ctrl_readb(cfg->mux_reg); | ||
586 | else | ||
587 | orig = omap_ctrl_readw(cfg->mux_reg); | ||
588 | 293 | ||
589 | #ifdef CONFIG_OMAP_MUX_DEBUG | 294 | #ifdef CONFIG_OMAP_MUX_DEBUG |
590 | debug = cfg->debug; | 295 | debug = cfg->debug; |
@@ -600,7 +305,6 @@ static void __init_or_module omap2_cfg_debug(const struct pin_config *cfg, u16 r | |||
600 | #define omap2_cfg_debug(x, y) do {} while (0) | 305 | #define omap2_cfg_debug(x, y) do {} while (0) |
601 | #endif | 306 | #endif |
602 | 307 | ||
603 | #ifdef CONFIG_ARCH_OMAP24XX | ||
604 | static int __init_or_module omap24xx_cfg_reg(const struct pin_config *cfg) | 308 | static int __init_or_module omap24xx_cfg_reg(const struct pin_config *cfg) |
605 | { | 309 | { |
606 | static DEFINE_SPINLOCK(mux_spin_lock); | 310 | static DEFINE_SPINLOCK(mux_spin_lock); |
@@ -614,47 +318,692 @@ static int __init_or_module omap24xx_cfg_reg(const struct pin_config *cfg) | |||
614 | if (cfg->pu_pd_val) | 318 | if (cfg->pu_pd_val) |
615 | reg |= OMAP2_PULL_UP; | 319 | reg |= OMAP2_PULL_UP; |
616 | omap2_cfg_debug(cfg, reg); | 320 | omap2_cfg_debug(cfg, reg); |
617 | omap_ctrl_writeb(reg, cfg->mux_reg); | 321 | omap_mux_write(reg, cfg->mux_reg - OMAP_MUX_BASE_OFFSET); |
618 | spin_unlock_irqrestore(&mux_spin_lock, flags); | 322 | spin_unlock_irqrestore(&mux_spin_lock, flags); |
619 | 323 | ||
620 | return 0; | 324 | return 0; |
621 | } | 325 | } |
326 | |||
327 | int __init omap2_mux_init(void) | ||
328 | { | ||
329 | u32 mux_pbase; | ||
330 | |||
331 | if (cpu_is_omap2420()) | ||
332 | mux_pbase = OMAP2420_CTRL_BASE + OMAP_MUX_BASE_OFFSET; | ||
333 | else if (cpu_is_omap2430()) | ||
334 | mux_pbase = OMAP243X_CTRL_BASE + OMAP_MUX_BASE_OFFSET; | ||
335 | else | ||
336 | return -ENODEV; | ||
337 | |||
338 | mux_base = ioremap(mux_pbase, OMAP_MUX_BASE_SZ); | ||
339 | if (!mux_base) { | ||
340 | printk(KERN_ERR "mux: Could not ioremap\n"); | ||
341 | return -ENODEV; | ||
342 | } | ||
343 | |||
344 | if (cpu_is_omap24xx()) { | ||
345 | arch_mux_cfg.pins = omap24xx_pins; | ||
346 | arch_mux_cfg.size = OMAP24XX_PINS_SZ; | ||
347 | arch_mux_cfg.cfg_reg = omap24xx_cfg_reg; | ||
348 | |||
349 | return omap_mux_register(&arch_mux_cfg); | ||
350 | } | ||
351 | |||
352 | return 0; | ||
353 | } | ||
354 | |||
622 | #else | 355 | #else |
623 | #define omap24xx_cfg_reg NULL | 356 | int __init omap2_mux_init(void) |
624 | #endif | 357 | { |
358 | return 0; | ||
359 | } | ||
360 | #endif /* CONFIG_OMAP_MUX */ | ||
361 | |||
362 | /*----------------------------------------------------------------------------*/ | ||
625 | 363 | ||
626 | #ifdef CONFIG_ARCH_OMAP34XX | 364 | #ifdef CONFIG_ARCH_OMAP34XX |
627 | static int __init_or_module omap34xx_cfg_reg(const struct pin_config *cfg) | 365 | static LIST_HEAD(muxmodes); |
366 | static DEFINE_MUTEX(muxmode_mutex); | ||
367 | |||
368 | #ifdef CONFIG_OMAP_MUX | ||
369 | |||
370 | static char *omap_mux_options; | ||
371 | |||
372 | int __init omap_mux_init_gpio(int gpio, int val) | ||
628 | { | 373 | { |
629 | static DEFINE_SPINLOCK(mux_spin_lock); | 374 | struct omap_mux_entry *e; |
630 | unsigned long flags; | 375 | int found = 0; |
631 | u16 reg = 0; | 376 | |
377 | if (!gpio) | ||
378 | return -EINVAL; | ||
379 | |||
380 | list_for_each_entry(e, &muxmodes, node) { | ||
381 | struct omap_mux *m = &e->mux; | ||
382 | if (gpio == m->gpio) { | ||
383 | u16 old_mode; | ||
384 | u16 mux_mode; | ||
385 | |||
386 | old_mode = omap_mux_read(m->reg_offset); | ||
387 | mux_mode = val & ~(OMAP_MUX_NR_MODES - 1); | ||
388 | mux_mode |= OMAP_MUX_MODE4; | ||
389 | printk(KERN_DEBUG "mux: Setting signal " | ||
390 | "%s.gpio%i 0x%04x -> 0x%04x\n", | ||
391 | m->muxnames[0], gpio, old_mode, mux_mode); | ||
392 | omap_mux_write(mux_mode, m->reg_offset); | ||
393 | found++; | ||
394 | } | ||
395 | } | ||
632 | 396 | ||
633 | spin_lock_irqsave(&mux_spin_lock, flags); | 397 | if (found == 1) |
634 | reg |= cfg->mux_val; | 398 | return 0; |
635 | omap2_cfg_debug(cfg, reg); | 399 | |
636 | omap_ctrl_writew(reg, cfg->mux_reg); | 400 | if (found > 1) { |
637 | spin_unlock_irqrestore(&mux_spin_lock, flags); | 401 | printk(KERN_ERR "mux: Multiple gpio paths for gpio%i\n", gpio); |
402 | return -EINVAL; | ||
403 | } | ||
404 | |||
405 | printk(KERN_ERR "mux: Could not set gpio%i\n", gpio); | ||
406 | |||
407 | return -ENODEV; | ||
408 | } | ||
409 | |||
410 | int __init omap_mux_init_signal(char *muxname, int val) | ||
411 | { | ||
412 | struct omap_mux_entry *e; | ||
413 | char *m0_name = NULL, *mode_name = NULL; | ||
414 | int found = 0; | ||
415 | |||
416 | mode_name = strchr(muxname, '.'); | ||
417 | if (mode_name) { | ||
418 | *mode_name = '\0'; | ||
419 | mode_name++; | ||
420 | m0_name = muxname; | ||
421 | } else { | ||
422 | mode_name = muxname; | ||
423 | } | ||
424 | |||
425 | list_for_each_entry(e, &muxmodes, node) { | ||
426 | struct omap_mux *m = &e->mux; | ||
427 | char *m0_entry = m->muxnames[0]; | ||
428 | int i; | ||
429 | |||
430 | if (m0_name && strcmp(m0_name, m0_entry)) | ||
431 | continue; | ||
432 | |||
433 | for (i = 0; i < OMAP_MUX_NR_MODES; i++) { | ||
434 | char *mode_cur = m->muxnames[i]; | ||
435 | |||
436 | if (!mode_cur) | ||
437 | continue; | ||
438 | |||
439 | if (!strcmp(mode_name, mode_cur)) { | ||
440 | u16 old_mode; | ||
441 | u16 mux_mode; | ||
442 | |||
443 | old_mode = omap_mux_read(m->reg_offset); | ||
444 | mux_mode = val | i; | ||
445 | printk(KERN_DEBUG "mux: Setting signal " | ||
446 | "%s.%s 0x%04x -> 0x%04x\n", | ||
447 | m0_entry, muxname, old_mode, mux_mode); | ||
448 | omap_mux_write(mux_mode, m->reg_offset); | ||
449 | found++; | ||
450 | } | ||
451 | } | ||
452 | } | ||
453 | |||
454 | if (found == 1) | ||
455 | return 0; | ||
456 | |||
457 | if (found > 1) { | ||
458 | printk(KERN_ERR "mux: Multiple signal paths (%i) for %s\n", | ||
459 | found, muxname); | ||
460 | return -EINVAL; | ||
461 | } | ||
462 | |||
463 | printk(KERN_ERR "mux: Could not set signal %s\n", muxname); | ||
464 | |||
465 | return -ENODEV; | ||
466 | } | ||
467 | |||
468 | #ifdef CONFIG_DEBUG_FS | ||
469 | |||
470 | #define OMAP_MUX_MAX_NR_FLAGS 10 | ||
471 | #define OMAP_MUX_TEST_FLAG(val, mask) \ | ||
472 | if (((val) & (mask)) == (mask)) { \ | ||
473 | i++; \ | ||
474 | flags[i] = #mask; \ | ||
475 | } | ||
476 | |||
477 | /* REVISIT: Add checking for non-optimal mux settings */ | ||
478 | static inline void omap_mux_decode(struct seq_file *s, u16 val) | ||
479 | { | ||
480 | char *flags[OMAP_MUX_MAX_NR_FLAGS]; | ||
481 | char mode[14]; | ||
482 | int i = -1; | ||
483 | |||
484 | sprintf(mode, "OMAP_MUX_MODE%d", val & 0x7); | ||
485 | i++; | ||
486 | flags[i] = mode; | ||
487 | |||
488 | OMAP_MUX_TEST_FLAG(val, OMAP_PIN_OFF_WAKEUPENABLE); | ||
489 | if (val & OMAP_OFF_EN) { | ||
490 | if (!(val & OMAP_OFFOUT_EN)) { | ||
491 | if (!(val & OMAP_OFF_PULL_UP)) { | ||
492 | OMAP_MUX_TEST_FLAG(val, | ||
493 | OMAP_PIN_OFF_INPUT_PULLDOWN); | ||
494 | } else { | ||
495 | OMAP_MUX_TEST_FLAG(val, | ||
496 | OMAP_PIN_OFF_INPUT_PULLUP); | ||
497 | } | ||
498 | } else { | ||
499 | if (!(val & OMAP_OFFOUT_VAL)) { | ||
500 | OMAP_MUX_TEST_FLAG(val, | ||
501 | OMAP_PIN_OFF_OUTPUT_LOW); | ||
502 | } else { | ||
503 | OMAP_MUX_TEST_FLAG(val, | ||
504 | OMAP_PIN_OFF_OUTPUT_HIGH); | ||
505 | } | ||
506 | } | ||
507 | } | ||
508 | |||
509 | if (val & OMAP_INPUT_EN) { | ||
510 | if (val & OMAP_PULL_ENA) { | ||
511 | if (!(val & OMAP_PULL_UP)) { | ||
512 | OMAP_MUX_TEST_FLAG(val, | ||
513 | OMAP_PIN_INPUT_PULLDOWN); | ||
514 | } else { | ||
515 | OMAP_MUX_TEST_FLAG(val, OMAP_PIN_INPUT_PULLUP); | ||
516 | } | ||
517 | } else { | ||
518 | OMAP_MUX_TEST_FLAG(val, OMAP_PIN_INPUT); | ||
519 | } | ||
520 | } else { | ||
521 | i++; | ||
522 | flags[i] = "OMAP_PIN_OUTPUT"; | ||
523 | } | ||
524 | |||
525 | do { | ||
526 | seq_printf(s, "%s", flags[i]); | ||
527 | if (i > 0) | ||
528 | seq_printf(s, " | "); | ||
529 | } while (i-- > 0); | ||
530 | } | ||
531 | |||
532 | #define OMAP_MUX_DEFNAME_LEN 16 | ||
533 | |||
534 | static int omap_mux_dbg_board_show(struct seq_file *s, void *unused) | ||
535 | { | ||
536 | struct omap_mux_entry *e; | ||
537 | |||
538 | list_for_each_entry(e, &muxmodes, node) { | ||
539 | struct omap_mux *m = &e->mux; | ||
540 | char m0_def[OMAP_MUX_DEFNAME_LEN]; | ||
541 | char *m0_name = m->muxnames[0]; | ||
542 | u16 val; | ||
543 | int i, mode; | ||
544 | |||
545 | if (!m0_name) | ||
546 | continue; | ||
547 | |||
548 | for (i = 0; i < OMAP_MUX_DEFNAME_LEN; i++) { | ||
549 | if (m0_name[i] == '\0') { | ||
550 | m0_def[i] = m0_name[i]; | ||
551 | break; | ||
552 | } | ||
553 | m0_def[i] = toupper(m0_name[i]); | ||
554 | } | ||
555 | val = omap_mux_read(m->reg_offset); | ||
556 | mode = val & OMAP_MUX_MODE7; | ||
557 | |||
558 | seq_printf(s, "OMAP%i_MUX(%s, ", | ||
559 | cpu_is_omap34xx() ? 3 : 0, m0_def); | ||
560 | omap_mux_decode(s, val); | ||
561 | seq_printf(s, "),\n"); | ||
562 | } | ||
563 | |||
564 | return 0; | ||
565 | } | ||
566 | |||
567 | static int omap_mux_dbg_board_open(struct inode *inode, struct file *file) | ||
568 | { | ||
569 | return single_open(file, omap_mux_dbg_board_show, &inode->i_private); | ||
570 | } | ||
571 | |||
572 | static const struct file_operations omap_mux_dbg_board_fops = { | ||
573 | .open = omap_mux_dbg_board_open, | ||
574 | .read = seq_read, | ||
575 | .llseek = seq_lseek, | ||
576 | .release = single_release, | ||
577 | }; | ||
578 | |||
579 | static int omap_mux_dbg_signal_show(struct seq_file *s, void *unused) | ||
580 | { | ||
581 | struct omap_mux *m = s->private; | ||
582 | const char *none = "NA"; | ||
583 | u16 val; | ||
584 | int mode; | ||
585 | |||
586 | val = omap_mux_read(m->reg_offset); | ||
587 | mode = val & OMAP_MUX_MODE7; | ||
588 | |||
589 | seq_printf(s, "name: %s.%s (0x%08lx/0x%03x = 0x%04x), b %s, t %s\n", | ||
590 | m->muxnames[0], m->muxnames[mode], | ||
591 | mux_phys + m->reg_offset, m->reg_offset, val, | ||
592 | m->balls[0] ? m->balls[0] : none, | ||
593 | m->balls[1] ? m->balls[1] : none); | ||
594 | seq_printf(s, "mode: "); | ||
595 | omap_mux_decode(s, val); | ||
596 | seq_printf(s, "\n"); | ||
597 | seq_printf(s, "signals: %s | %s | %s | %s | %s | %s | %s | %s\n", | ||
598 | m->muxnames[0] ? m->muxnames[0] : none, | ||
599 | m->muxnames[1] ? m->muxnames[1] : none, | ||
600 | m->muxnames[2] ? m->muxnames[2] : none, | ||
601 | m->muxnames[3] ? m->muxnames[3] : none, | ||
602 | m->muxnames[4] ? m->muxnames[4] : none, | ||
603 | m->muxnames[5] ? m->muxnames[5] : none, | ||
604 | m->muxnames[6] ? m->muxnames[6] : none, | ||
605 | m->muxnames[7] ? m->muxnames[7] : none); | ||
638 | 606 | ||
639 | return 0; | 607 | return 0; |
640 | } | 608 | } |
609 | |||
610 | #define OMAP_MUX_MAX_ARG_CHAR 7 | ||
611 | |||
612 | static ssize_t omap_mux_dbg_signal_write(struct file *file, | ||
613 | const char __user *user_buf, | ||
614 | size_t count, loff_t *ppos) | ||
615 | { | ||
616 | char buf[OMAP_MUX_MAX_ARG_CHAR]; | ||
617 | struct seq_file *seqf; | ||
618 | struct omap_mux *m; | ||
619 | unsigned long val; | ||
620 | int buf_size, ret; | ||
621 | |||
622 | if (count > OMAP_MUX_MAX_ARG_CHAR) | ||
623 | return -EINVAL; | ||
624 | |||
625 | memset(buf, 0, sizeof(buf)); | ||
626 | buf_size = min(count, sizeof(buf) - 1); | ||
627 | |||
628 | if (copy_from_user(buf, user_buf, buf_size)) | ||
629 | return -EFAULT; | ||
630 | |||
631 | ret = strict_strtoul(buf, 0x10, &val); | ||
632 | if (ret < 0) | ||
633 | return ret; | ||
634 | |||
635 | if (val > 0xffff) | ||
636 | return -EINVAL; | ||
637 | |||
638 | seqf = file->private_data; | ||
639 | m = seqf->private; | ||
640 | |||
641 | omap_mux_write((u16)val, m->reg_offset); | ||
642 | *ppos += count; | ||
643 | |||
644 | return count; | ||
645 | } | ||
646 | |||
647 | static int omap_mux_dbg_signal_open(struct inode *inode, struct file *file) | ||
648 | { | ||
649 | return single_open(file, omap_mux_dbg_signal_show, inode->i_private); | ||
650 | } | ||
651 | |||
652 | static const struct file_operations omap_mux_dbg_signal_fops = { | ||
653 | .open = omap_mux_dbg_signal_open, | ||
654 | .read = seq_read, | ||
655 | .write = omap_mux_dbg_signal_write, | ||
656 | .llseek = seq_lseek, | ||
657 | .release = single_release, | ||
658 | }; | ||
659 | |||
660 | static struct dentry *mux_dbg_dir; | ||
661 | |||
662 | static void __init omap_mux_dbg_init(void) | ||
663 | { | ||
664 | struct omap_mux_entry *e; | ||
665 | |||
666 | mux_dbg_dir = debugfs_create_dir("omap_mux", NULL); | ||
667 | if (!mux_dbg_dir) | ||
668 | return; | ||
669 | |||
670 | (void)debugfs_create_file("board", S_IRUGO, mux_dbg_dir, | ||
671 | NULL, &omap_mux_dbg_board_fops); | ||
672 | |||
673 | list_for_each_entry(e, &muxmodes, node) { | ||
674 | struct omap_mux *m = &e->mux; | ||
675 | |||
676 | (void)debugfs_create_file(m->muxnames[0], S_IWUGO, mux_dbg_dir, | ||
677 | m, &omap_mux_dbg_signal_fops); | ||
678 | } | ||
679 | } | ||
680 | |||
641 | #else | 681 | #else |
642 | #define omap34xx_cfg_reg NULL | 682 | static inline void omap_mux_dbg_init(void) |
683 | { | ||
684 | } | ||
685 | #endif /* CONFIG_DEBUG_FS */ | ||
686 | |||
687 | static void __init omap_mux_free_names(struct omap_mux *m) | ||
688 | { | ||
689 | int i; | ||
690 | |||
691 | for (i = 0; i < OMAP_MUX_NR_MODES; i++) | ||
692 | kfree(m->muxnames[i]); | ||
693 | |||
694 | #ifdef CONFIG_DEBUG_FS | ||
695 | for (i = 0; i < OMAP_MUX_NR_SIDES; i++) | ||
696 | kfree(m->balls[i]); | ||
643 | #endif | 697 | #endif |
644 | 698 | ||
645 | int __init omap2_mux_init(void) | 699 | } |
700 | |||
701 | /* Free all data except for GPIO pins unless CONFIG_DEBUG_FS is set */ | ||
702 | static int __init omap_mux_late_init(void) | ||
646 | { | 703 | { |
647 | if (cpu_is_omap24xx()) { | 704 | struct omap_mux_entry *e, *tmp; |
648 | arch_mux_cfg.pins = omap24xx_pins; | 705 | |
649 | arch_mux_cfg.size = OMAP24XX_PINS_SZ; | 706 | list_for_each_entry_safe(e, tmp, &muxmodes, node) { |
650 | arch_mux_cfg.cfg_reg = omap24xx_cfg_reg; | 707 | struct omap_mux *m = &e->mux; |
651 | } else if (cpu_is_omap34xx()) { | 708 | u16 mode = omap_mux_read(m->reg_offset); |
652 | arch_mux_cfg.pins = omap34xx_pins; | 709 | |
653 | arch_mux_cfg.size = OMAP34XX_PINS_SZ; | 710 | if (OMAP_MODE_GPIO(mode)) |
654 | arch_mux_cfg.cfg_reg = omap34xx_cfg_reg; | 711 | continue; |
712 | |||
713 | #ifndef CONFIG_DEBUG_FS | ||
714 | mutex_lock(&muxmode_mutex); | ||
715 | list_del(&e->node); | ||
716 | mutex_unlock(&muxmode_mutex); | ||
717 | omap_mux_free_names(m); | ||
718 | kfree(m); | ||
719 | #endif | ||
720 | |||
721 | } | ||
722 | |||
723 | omap_mux_dbg_init(); | ||
724 | |||
725 | return 0; | ||
726 | } | ||
727 | late_initcall(omap_mux_late_init); | ||
728 | |||
729 | static void __init omap_mux_package_fixup(struct omap_mux *p, | ||
730 | struct omap_mux *superset) | ||
731 | { | ||
732 | while (p->reg_offset != OMAP_MUX_TERMINATOR) { | ||
733 | struct omap_mux *s = superset; | ||
734 | int found = 0; | ||
735 | |||
736 | while (s->reg_offset != OMAP_MUX_TERMINATOR) { | ||
737 | if (s->reg_offset == p->reg_offset) { | ||
738 | *s = *p; | ||
739 | found++; | ||
740 | break; | ||
741 | } | ||
742 | s++; | ||
743 | } | ||
744 | if (!found) | ||
745 | printk(KERN_ERR "mux: Unknown entry offset 0x%x\n", | ||
746 | p->reg_offset); | ||
747 | p++; | ||
748 | } | ||
749 | } | ||
750 | |||
751 | #ifdef CONFIG_DEBUG_FS | ||
752 | |||
753 | static void __init omap_mux_package_init_balls(struct omap_ball *b, | ||
754 | struct omap_mux *superset) | ||
755 | { | ||
756 | while (b->reg_offset != OMAP_MUX_TERMINATOR) { | ||
757 | struct omap_mux *s = superset; | ||
758 | int found = 0; | ||
759 | |||
760 | while (s->reg_offset != OMAP_MUX_TERMINATOR) { | ||
761 | if (s->reg_offset == b->reg_offset) { | ||
762 | s->balls[0] = b->balls[0]; | ||
763 | s->balls[1] = b->balls[1]; | ||
764 | found++; | ||
765 | break; | ||
766 | } | ||
767 | s++; | ||
768 | } | ||
769 | if (!found) | ||
770 | printk(KERN_ERR "mux: Unknown ball offset 0x%x\n", | ||
771 | b->reg_offset); | ||
772 | b++; | ||
773 | } | ||
774 | } | ||
775 | |||
776 | #else /* CONFIG_DEBUG_FS */ | ||
777 | |||
778 | static inline void omap_mux_package_init_balls(struct omap_ball *b, | ||
779 | struct omap_mux *superset) | ||
780 | { | ||
781 | } | ||
782 | |||
783 | #endif /* CONFIG_DEBUG_FS */ | ||
784 | |||
785 | static int __init omap_mux_setup(char *options) | ||
786 | { | ||
787 | if (!options) | ||
788 | return 0; | ||
789 | |||
790 | omap_mux_options = options; | ||
791 | |||
792 | return 1; | ||
793 | } | ||
794 | __setup("omap_mux=", omap_mux_setup); | ||
795 | |||
796 | /* | ||
797 | * Note that the omap_mux=some.signal1=0x1234,some.signal2=0x1234 | ||
798 | * cmdline options only override the bootloader values. | ||
799 | * During development, please enable CONFIG_DEBUG_FS, and use the | ||
800 | * signal specific entries under debugfs. | ||
801 | */ | ||
802 | static void __init omap_mux_set_cmdline_signals(void) | ||
803 | { | ||
804 | char *options, *next_opt, *token; | ||
805 | |||
806 | if (!omap_mux_options) | ||
807 | return; | ||
808 | |||
809 | options = kmalloc(strlen(omap_mux_options) + 1, GFP_KERNEL); | ||
810 | if (!options) | ||
811 | return; | ||
812 | |||
813 | strcpy(options, omap_mux_options); | ||
814 | next_opt = options; | ||
815 | |||
816 | while ((token = strsep(&next_opt, ",")) != NULL) { | ||
817 | char *keyval, *name; | ||
818 | unsigned long val; | ||
819 | |||
820 | keyval = token; | ||
821 | name = strsep(&keyval, "="); | ||
822 | if (name) { | ||
823 | int res; | ||
824 | |||
825 | res = strict_strtoul(keyval, 0x10, &val); | ||
826 | if (res < 0) | ||
827 | continue; | ||
828 | |||
829 | omap_mux_init_signal(name, (u16)val); | ||
830 | } | ||
831 | } | ||
832 | |||
833 | kfree(options); | ||
834 | } | ||
835 | |||
836 | static void __init omap_mux_set_board_signals(struct omap_board_mux *board_mux) | ||
837 | { | ||
838 | while (board_mux->reg_offset != OMAP_MUX_TERMINATOR) { | ||
839 | omap_mux_write(board_mux->value, board_mux->reg_offset); | ||
840 | board_mux++; | ||
841 | } | ||
842 | } | ||
843 | |||
844 | static int __init omap_mux_copy_names(struct omap_mux *src, | ||
845 | struct omap_mux *dst) | ||
846 | { | ||
847 | int i; | ||
848 | |||
849 | for (i = 0; i < OMAP_MUX_NR_MODES; i++) { | ||
850 | if (src->muxnames[i]) { | ||
851 | dst->muxnames[i] = | ||
852 | kmalloc(strlen(src->muxnames[i]) + 1, | ||
853 | GFP_KERNEL); | ||
854 | if (!dst->muxnames[i]) | ||
855 | goto free; | ||
856 | strcpy(dst->muxnames[i], src->muxnames[i]); | ||
857 | } | ||
858 | } | ||
859 | |||
860 | #ifdef CONFIG_DEBUG_FS | ||
861 | for (i = 0; i < OMAP_MUX_NR_SIDES; i++) { | ||
862 | if (src->balls[i]) { | ||
863 | dst->balls[i] = | ||
864 | kmalloc(strlen(src->balls[i]) + 1, | ||
865 | GFP_KERNEL); | ||
866 | if (!dst->balls[i]) | ||
867 | goto free; | ||
868 | strcpy(dst->balls[i], src->balls[i]); | ||
869 | } | ||
870 | } | ||
871 | #endif | ||
872 | |||
873 | return 0; | ||
874 | |||
875 | free: | ||
876 | omap_mux_free_names(dst); | ||
877 | return -ENOMEM; | ||
878 | |||
879 | } | ||
880 | |||
881 | #endif /* CONFIG_OMAP_MUX */ | ||
882 | |||
883 | static u16 omap_mux_get_by_gpio(int gpio) | ||
884 | { | ||
885 | struct omap_mux_entry *e; | ||
886 | u16 offset = OMAP_MUX_TERMINATOR; | ||
887 | |||
888 | list_for_each_entry(e, &muxmodes, node) { | ||
889 | struct omap_mux *m = &e->mux; | ||
890 | if (m->gpio == gpio) { | ||
891 | offset = m->reg_offset; | ||
892 | break; | ||
893 | } | ||
894 | } | ||
895 | |||
896 | return offset; | ||
897 | } | ||
898 | |||
899 | /* Needed for dynamic muxing of GPIO pins for off-idle */ | ||
900 | u16 omap_mux_get_gpio(int gpio) | ||
901 | { | ||
902 | u16 offset; | ||
903 | |||
904 | offset = omap_mux_get_by_gpio(gpio); | ||
905 | if (offset == OMAP_MUX_TERMINATOR) { | ||
906 | printk(KERN_ERR "mux: Could not get gpio%i\n", gpio); | ||
907 | return offset; | ||
908 | } | ||
909 | |||
910 | return omap_mux_read(offset); | ||
911 | } | ||
912 | |||
913 | /* Needed for dynamic muxing of GPIO pins for off-idle */ | ||
914 | void omap_mux_set_gpio(u16 val, int gpio) | ||
915 | { | ||
916 | u16 offset; | ||
917 | |||
918 | offset = omap_mux_get_by_gpio(gpio); | ||
919 | if (offset == OMAP_MUX_TERMINATOR) { | ||
920 | printk(KERN_ERR "mux: Could not set gpio%i\n", gpio); | ||
921 | return; | ||
922 | } | ||
923 | |||
924 | omap_mux_write(val, offset); | ||
925 | } | ||
926 | |||
927 | static struct omap_mux * __init omap_mux_list_add(struct omap_mux *src) | ||
928 | { | ||
929 | struct omap_mux_entry *entry; | ||
930 | struct omap_mux *m; | ||
931 | |||
932 | entry = kzalloc(sizeof(struct omap_mux_entry), GFP_KERNEL); | ||
933 | if (!entry) | ||
934 | return NULL; | ||
935 | |||
936 | m = &entry->mux; | ||
937 | memcpy(m, src, sizeof(struct omap_mux_entry)); | ||
938 | |||
939 | #ifdef CONFIG_OMAP_MUX | ||
940 | if (omap_mux_copy_names(src, m)) { | ||
941 | kfree(entry); | ||
942 | return NULL; | ||
655 | } | 943 | } |
944 | #endif | ||
945 | |||
946 | mutex_lock(&muxmode_mutex); | ||
947 | list_add_tail(&entry->node, &muxmodes); | ||
948 | mutex_unlock(&muxmode_mutex); | ||
656 | 949 | ||
657 | return omap_mux_register(&arch_mux_cfg); | 950 | return m; |
658 | } | 951 | } |
659 | 952 | ||
953 | /* | ||
954 | * Note if CONFIG_OMAP_MUX is not selected, we will only initialize | ||
955 | * the GPIO to mux offset mapping that is needed for dynamic muxing | ||
956 | * of GPIO pins for off-idle. | ||
957 | */ | ||
958 | static void __init omap_mux_init_list(struct omap_mux *superset) | ||
959 | { | ||
960 | while (superset->reg_offset != OMAP_MUX_TERMINATOR) { | ||
961 | struct omap_mux *entry; | ||
962 | |||
963 | #ifndef CONFIG_OMAP_MUX | ||
964 | /* Skip pins that are not muxed as GPIO by bootloader */ | ||
965 | if (!OMAP_MODE_GPIO(omap_mux_read(superset->reg_offset))) { | ||
966 | superset++; | ||
967 | continue; | ||
968 | } | ||
660 | #endif | 969 | #endif |
970 | |||
971 | entry = omap_mux_list_add(superset); | ||
972 | if (!entry) { | ||
973 | printk(KERN_ERR "mux: Could not add entry\n"); | ||
974 | return; | ||
975 | } | ||
976 | superset++; | ||
977 | } | ||
978 | } | ||
979 | |||
980 | int __init omap_mux_init(u32 mux_pbase, u32 mux_size, | ||
981 | struct omap_mux *superset, | ||
982 | struct omap_mux *package_subset, | ||
983 | struct omap_board_mux *board_mux, | ||
984 | struct omap_ball *package_balls) | ||
985 | { | ||
986 | if (mux_base) | ||
987 | return -EBUSY; | ||
988 | |||
989 | mux_phys = mux_pbase; | ||
990 | mux_base = ioremap(mux_pbase, mux_size); | ||
991 | if (!mux_base) { | ||
992 | printk(KERN_ERR "mux: Could not ioremap\n"); | ||
993 | return -ENODEV; | ||
994 | } | ||
995 | |||
996 | #ifdef CONFIG_OMAP_MUX | ||
997 | omap_mux_package_fixup(package_subset, superset); | ||
998 | omap_mux_package_init_balls(package_balls, superset); | ||
999 | omap_mux_set_cmdline_signals(); | ||
1000 | omap_mux_set_board_signals(board_mux); | ||
1001 | #endif | ||
1002 | |||
1003 | omap_mux_init_list(superset); | ||
1004 | |||
1005 | return 0; | ||
1006 | } | ||
1007 | |||
1008 | #endif /* CONFIG_ARCH_OMAP34XX */ | ||
1009 | |||
diff --git a/arch/arm/mach-omap2/mux.h b/arch/arm/mach-omap2/mux.h new file mode 100644 index 000000000000..d8b4d5ad2278 --- /dev/null +++ b/arch/arm/mach-omap2/mux.h | |||
@@ -0,0 +1,163 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2009 Nokia | ||
3 | * Copyright (C) 2009 Texas Instruments | ||
4 | * | ||
5 | * This program is free software; you can redistribute it and/or modify | ||
6 | * it under the terms of the GNU General Public License version 2 as | ||
7 | * published by the Free Software Foundation. | ||
8 | */ | ||
9 | |||
10 | #include "mux34xx.h" | ||
11 | |||
12 | #define OMAP_MUX_TERMINATOR 0xffff | ||
13 | |||
14 | /* 34xx mux mode options for each pin. See TRM for options */ | ||
15 | #define OMAP_MUX_MODE0 0 | ||
16 | #define OMAP_MUX_MODE1 1 | ||
17 | #define OMAP_MUX_MODE2 2 | ||
18 | #define OMAP_MUX_MODE3 3 | ||
19 | #define OMAP_MUX_MODE4 4 | ||
20 | #define OMAP_MUX_MODE5 5 | ||
21 | #define OMAP_MUX_MODE6 6 | ||
22 | #define OMAP_MUX_MODE7 7 | ||
23 | |||
24 | /* 24xx/34xx mux bit defines */ | ||
25 | #define OMAP_PULL_ENA (1 << 3) | ||
26 | #define OMAP_PULL_UP (1 << 4) | ||
27 | #define OMAP_ALTELECTRICALSEL (1 << 5) | ||
28 | |||
29 | /* 34xx specific mux bit defines */ | ||
30 | #define OMAP_INPUT_EN (1 << 8) | ||
31 | #define OMAP_OFF_EN (1 << 9) | ||
32 | #define OMAP_OFFOUT_EN (1 << 10) | ||
33 | #define OMAP_OFFOUT_VAL (1 << 11) | ||
34 | #define OMAP_OFF_PULL_EN (1 << 12) | ||
35 | #define OMAP_OFF_PULL_UP (1 << 13) | ||
36 | #define OMAP_WAKEUP_EN (1 << 14) | ||
37 | |||
38 | /* Active pin states */ | ||
39 | #define OMAP_PIN_OUTPUT 0 | ||
40 | #define OMAP_PIN_INPUT OMAP_INPUT_EN | ||
41 | #define OMAP_PIN_INPUT_PULLUP (OMAP_PULL_ENA | OMAP_INPUT_EN \ | ||
42 | | OMAP_PULL_UP) | ||
43 | #define OMAP_PIN_INPUT_PULLDOWN (OMAP_PULL_ENA | OMAP_INPUT_EN) | ||
44 | |||
45 | /* Off mode states */ | ||
46 | #define OMAP_PIN_OFF_NONE 0 | ||
47 | #define OMAP_PIN_OFF_OUTPUT_HIGH (OMAP_OFF_EN | OMAP_OFFOUT_EN \ | ||
48 | | OMAP_OFFOUT_VAL) | ||
49 | #define OMAP_PIN_OFF_OUTPUT_LOW (OMAP_OFF_EN | OMAP_OFFOUT_EN) | ||
50 | #define OMAP_PIN_OFF_INPUT_PULLUP (OMAP_OFF_EN | OMAP_OFF_PULL_EN \ | ||
51 | | OMAP_OFF_PULL_UP) | ||
52 | #define OMAP_PIN_OFF_INPUT_PULLDOWN (OMAP_OFF_EN | OMAP_OFF_PULL_EN) | ||
53 | #define OMAP_PIN_OFF_WAKEUPENABLE OMAP_WAKEUP_EN | ||
54 | |||
55 | #define OMAP_MODE_GPIO(x) (((x) & OMAP_MUX_MODE7) == OMAP_MUX_MODE4) | ||
56 | |||
57 | /* Flags for omap_mux_init */ | ||
58 | #define OMAP_PACKAGE_MASK 0xffff | ||
59 | #define OMAP_PACKAGE_CBP 4 /* 515-pin 0.40 0.50 */ | ||
60 | #define OMAP_PACKAGE_CUS 3 /* 423-pin 0.65 */ | ||
61 | #define OMAP_PACKAGE_CBB 2 /* 515-pin 0.40 0.50 */ | ||
62 | #define OMAP_PACKAGE_CBC 1 /* 515-pin 0.50 0.65 */ | ||
63 | |||
64 | |||
65 | #define OMAP_MUX_NR_MODES 8 /* Available modes */ | ||
66 | #define OMAP_MUX_NR_SIDES 2 /* Bottom & top */ | ||
67 | |||
68 | /** | ||
69 | * struct omap_mux - data for omap mux register offset and it's value | ||
70 | * @reg_offset: mux register offset from the mux base | ||
71 | * @gpio: GPIO number | ||
72 | * @muxnames: available signal modes for a ball | ||
73 | */ | ||
74 | struct omap_mux { | ||
75 | u16 reg_offset; | ||
76 | u16 gpio; | ||
77 | #ifdef CONFIG_OMAP_MUX | ||
78 | char *muxnames[OMAP_MUX_NR_MODES]; | ||
79 | #ifdef CONFIG_DEBUG_FS | ||
80 | char *balls[OMAP_MUX_NR_SIDES]; | ||
81 | #endif | ||
82 | #endif | ||
83 | }; | ||
84 | |||
85 | /** | ||
86 | * struct omap_ball - data for balls on omap package | ||
87 | * @reg_offset: mux register offset from the mux base | ||
88 | * @balls: available balls on the package | ||
89 | */ | ||
90 | struct omap_ball { | ||
91 | u16 reg_offset; | ||
92 | char *balls[OMAP_MUX_NR_SIDES]; | ||
93 | }; | ||
94 | |||
95 | /** | ||
96 | * struct omap_board_mux - data for initializing mux registers | ||
97 | * @reg_offset: mux register offset from the mux base | ||
98 | * @mux_value: desired mux value to set | ||
99 | */ | ||
100 | struct omap_board_mux { | ||
101 | u16 reg_offset; | ||
102 | u16 value; | ||
103 | }; | ||
104 | |||
105 | #if defined(CONFIG_OMAP_MUX) && defined(CONFIG_ARCH_OMAP34XX) | ||
106 | |||
107 | /** | ||
108 | * omap_mux_init_gpio - initialize a signal based on the GPIO number | ||
109 | * @gpio: GPIO number | ||
110 | * @val: Options for the mux register value | ||
111 | */ | ||
112 | int omap_mux_init_gpio(int gpio, int val); | ||
113 | |||
114 | /** | ||
115 | * omap_mux_init_signal - initialize a signal based on the signal name | ||
116 | * @muxname: Mux name in mode0_name.signal_name format | ||
117 | * @val: Options for the mux register value | ||
118 | */ | ||
119 | int omap_mux_init_signal(char *muxname, int val); | ||
120 | |||
121 | #else | ||
122 | |||
123 | static inline int omap_mux_init_gpio(int gpio, int val) | ||
124 | { | ||
125 | return 0; | ||
126 | } | ||
127 | static inline int omap_mux_init_signal(char *muxname, int val) | ||
128 | { | ||
129 | return 0; | ||
130 | } | ||
131 | |||
132 | #endif | ||
133 | |||
134 | /** | ||
135 | * omap_mux_get_gpio() - get mux register value based on GPIO number | ||
136 | * @gpio: GPIO number | ||
137 | * | ||
138 | */ | ||
139 | u16 omap_mux_get_gpio(int gpio); | ||
140 | |||
141 | /** | ||
142 | * omap_mux_set_gpio() - set mux register value based on GPIO number | ||
143 | * @val: New mux register value | ||
144 | * @gpio: GPIO number | ||
145 | * | ||
146 | */ | ||
147 | void omap_mux_set_gpio(u16 val, int gpio); | ||
148 | |||
149 | /** | ||
150 | * omap3_mux_init() - initialize mux system with board specific set | ||
151 | * @board_mux: Board specific mux table | ||
152 | * @flags: OMAP package type used for the board | ||
153 | */ | ||
154 | int omap3_mux_init(struct omap_board_mux *board_mux, int flags); | ||
155 | |||
156 | /** | ||
157 | * omap_mux_init - private mux init function, do not call | ||
158 | */ | ||
159 | int omap_mux_init(u32 mux_pbase, u32 mux_size, | ||
160 | struct omap_mux *superset, | ||
161 | struct omap_mux *package_subset, | ||
162 | struct omap_board_mux *board_mux, | ||
163 | struct omap_ball *package_balls); | ||
diff --git a/arch/arm/mach-omap2/mux34xx.c b/arch/arm/mach-omap2/mux34xx.c new file mode 100644 index 000000000000..68e0a595f9a1 --- /dev/null +++ b/arch/arm/mach-omap2/mux34xx.c | |||
@@ -0,0 +1,2099 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2009 Nokia | ||
3 | * Copyright (C) 2009 Texas Instruments | ||
4 | * | ||
5 | * This program is free software; you can redistribute it and/or modify | ||
6 | * it under the terms of the GNU General Public License version 2 as | ||
7 | * published by the Free Software Foundation. | ||
8 | */ | ||
9 | |||
10 | #include <linux/module.h> | ||
11 | #include <linux/init.h> | ||
12 | |||
13 | #include "mux.h" | ||
14 | |||
15 | #ifdef CONFIG_OMAP_MUX | ||
16 | |||
17 | #define _OMAP3_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \ | ||
18 | { \ | ||
19 | .reg_offset = (OMAP3_CONTROL_PADCONF_##M0##_OFFSET), \ | ||
20 | .gpio = (g), \ | ||
21 | .muxnames = { m0, m1, m2, m3, m4, m5, m6, m7 }, \ | ||
22 | } | ||
23 | |||
24 | #else | ||
25 | |||
26 | #define _OMAP3_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \ | ||
27 | { \ | ||
28 | .reg_offset = (OMAP3_CONTROL_PADCONF_##M0##_OFFSET), \ | ||
29 | .gpio = (g), \ | ||
30 | } | ||
31 | |||
32 | #endif | ||
33 | |||
34 | #define _OMAP3_BALLENTRY(M0, bb, bt) \ | ||
35 | { \ | ||
36 | .reg_offset = (OMAP3_CONTROL_PADCONF_##M0##_OFFSET), \ | ||
37 | .balls = { bb, bt }, \ | ||
38 | } | ||
39 | |||
40 | /* | ||
41 | * Superset of all mux modes for omap3 | ||
42 | */ | ||
43 | static struct omap_mux __initdata omap3_muxmodes[] = { | ||
44 | _OMAP3_MUXENTRY(CAM_D0, 99, | ||
45 | "cam_d0", NULL, NULL, NULL, | ||
46 | "gpio_99", NULL, NULL, "safe_mode"), | ||
47 | _OMAP3_MUXENTRY(CAM_D1, 100, | ||
48 | "cam_d1", NULL, NULL, NULL, | ||
49 | "gpio_100", NULL, NULL, "safe_mode"), | ||
50 | _OMAP3_MUXENTRY(CAM_D10, 109, | ||
51 | "cam_d10", NULL, NULL, NULL, | ||
52 | "gpio_109", "hw_dbg8", NULL, "safe_mode"), | ||
53 | _OMAP3_MUXENTRY(CAM_D11, 110, | ||
54 | "cam_d11", NULL, NULL, NULL, | ||
55 | "gpio_110", "hw_dbg9", NULL, "safe_mode"), | ||
56 | _OMAP3_MUXENTRY(CAM_D2, 101, | ||
57 | "cam_d2", NULL, NULL, NULL, | ||
58 | "gpio_101", "hw_dbg4", NULL, "safe_mode"), | ||
59 | _OMAP3_MUXENTRY(CAM_D3, 102, | ||
60 | "cam_d3", NULL, NULL, NULL, | ||
61 | "gpio_102", "hw_dbg5", NULL, "safe_mode"), | ||
62 | _OMAP3_MUXENTRY(CAM_D4, 103, | ||
63 | "cam_d4", NULL, NULL, NULL, | ||
64 | "gpio_103", "hw_dbg6", NULL, "safe_mode"), | ||
65 | _OMAP3_MUXENTRY(CAM_D5, 104, | ||
66 | "cam_d5", NULL, NULL, NULL, | ||
67 | "gpio_104", "hw_dbg7", NULL, "safe_mode"), | ||
68 | _OMAP3_MUXENTRY(CAM_D6, 105, | ||
69 | "cam_d6", NULL, NULL, NULL, | ||
70 | "gpio_105", NULL, NULL, "safe_mode"), | ||
71 | _OMAP3_MUXENTRY(CAM_D7, 106, | ||
72 | "cam_d7", NULL, NULL, NULL, | ||
73 | "gpio_106", NULL, NULL, "safe_mode"), | ||
74 | _OMAP3_MUXENTRY(CAM_D8, 107, | ||
75 | "cam_d8", NULL, NULL, NULL, | ||
76 | "gpio_107", NULL, NULL, "safe_mode"), | ||
77 | _OMAP3_MUXENTRY(CAM_D9, 108, | ||
78 | "cam_d9", NULL, NULL, NULL, | ||
79 | "gpio_108", NULL, NULL, "safe_mode"), | ||
80 | _OMAP3_MUXENTRY(CAM_FLD, 98, | ||
81 | "cam_fld", NULL, "cam_global_reset", NULL, | ||
82 | "gpio_98", "hw_dbg3", NULL, "safe_mode"), | ||
83 | _OMAP3_MUXENTRY(CAM_HS, 94, | ||
84 | "cam_hs", NULL, NULL, NULL, | ||
85 | "gpio_94", "hw_dbg0", NULL, "safe_mode"), | ||
86 | _OMAP3_MUXENTRY(CAM_PCLK, 97, | ||
87 | "cam_pclk", NULL, NULL, NULL, | ||
88 | "gpio_97", "hw_dbg2", NULL, "safe_mode"), | ||
89 | _OMAP3_MUXENTRY(CAM_STROBE, 126, | ||
90 | "cam_strobe", NULL, NULL, NULL, | ||
91 | "gpio_126", "hw_dbg11", NULL, "safe_mode"), | ||
92 | _OMAP3_MUXENTRY(CAM_VS, 95, | ||
93 | "cam_vs", NULL, NULL, NULL, | ||
94 | "gpio_95", "hw_dbg1", NULL, "safe_mode"), | ||
95 | _OMAP3_MUXENTRY(CAM_WEN, 167, | ||
96 | "cam_wen", NULL, "cam_shutter", NULL, | ||
97 | "gpio_167", "hw_dbg10", NULL, "safe_mode"), | ||
98 | _OMAP3_MUXENTRY(CAM_XCLKA, 96, | ||
99 | "cam_xclka", NULL, NULL, NULL, | ||
100 | "gpio_96", NULL, NULL, "safe_mode"), | ||
101 | _OMAP3_MUXENTRY(CAM_XCLKB, 111, | ||
102 | "cam_xclkb", NULL, NULL, NULL, | ||
103 | "gpio_111", NULL, NULL, "safe_mode"), | ||
104 | _OMAP3_MUXENTRY(CSI2_DX0, 112, | ||
105 | "csi2_dx0", NULL, NULL, NULL, | ||
106 | "gpio_112", NULL, NULL, "safe_mode"), | ||
107 | _OMAP3_MUXENTRY(CSI2_DX1, 114, | ||
108 | "csi2_dx1", NULL, NULL, NULL, | ||
109 | "gpio_114", NULL, NULL, "safe_mode"), | ||
110 | _OMAP3_MUXENTRY(CSI2_DY0, 113, | ||
111 | "csi2_dy0", NULL, NULL, NULL, | ||
112 | "gpio_113", NULL, NULL, "safe_mode"), | ||
113 | _OMAP3_MUXENTRY(CSI2_DY1, 115, | ||
114 | "csi2_dy1", NULL, NULL, NULL, | ||
115 | "gpio_115", NULL, NULL, "safe_mode"), | ||
116 | _OMAP3_MUXENTRY(DSS_ACBIAS, 69, | ||
117 | "dss_acbias", NULL, NULL, NULL, | ||
118 | "gpio_69", NULL, NULL, "safe_mode"), | ||
119 | _OMAP3_MUXENTRY(DSS_DATA0, 70, | ||
120 | "dss_data0", NULL, "uart1_cts", NULL, | ||
121 | "gpio_70", NULL, NULL, "safe_mode"), | ||
122 | _OMAP3_MUXENTRY(DSS_DATA1, 71, | ||
123 | "dss_data1", NULL, "uart1_rts", NULL, | ||
124 | "gpio_71", NULL, NULL, "safe_mode"), | ||
125 | _OMAP3_MUXENTRY(DSS_DATA10, 80, | ||
126 | "dss_data10", NULL, NULL, NULL, | ||
127 | "gpio_80", NULL, NULL, "safe_mode"), | ||
128 | _OMAP3_MUXENTRY(DSS_DATA11, 81, | ||
129 | "dss_data11", NULL, NULL, NULL, | ||
130 | "gpio_81", NULL, NULL, "safe_mode"), | ||
131 | _OMAP3_MUXENTRY(DSS_DATA12, 82, | ||
132 | "dss_data12", NULL, NULL, NULL, | ||
133 | "gpio_82", NULL, NULL, "safe_mode"), | ||
134 | _OMAP3_MUXENTRY(DSS_DATA13, 83, | ||
135 | "dss_data13", NULL, NULL, NULL, | ||
136 | "gpio_83", NULL, NULL, "safe_mode"), | ||
137 | _OMAP3_MUXENTRY(DSS_DATA14, 84, | ||
138 | "dss_data14", NULL, NULL, NULL, | ||
139 | "gpio_84", NULL, NULL, "safe_mode"), | ||
140 | _OMAP3_MUXENTRY(DSS_DATA15, 85, | ||
141 | "dss_data15", NULL, NULL, NULL, | ||
142 | "gpio_85", NULL, NULL, "safe_mode"), | ||
143 | _OMAP3_MUXENTRY(DSS_DATA16, 86, | ||
144 | "dss_data16", NULL, NULL, NULL, | ||
145 | "gpio_86", NULL, NULL, "safe_mode"), | ||
146 | _OMAP3_MUXENTRY(DSS_DATA17, 87, | ||
147 | "dss_data17", NULL, NULL, NULL, | ||
148 | "gpio_87", NULL, NULL, "safe_mode"), | ||
149 | _OMAP3_MUXENTRY(DSS_DATA18, 88, | ||
150 | "dss_data18", NULL, "mcspi3_clk", "dss_data0", | ||
151 | "gpio_88", NULL, NULL, "safe_mode"), | ||
152 | _OMAP3_MUXENTRY(DSS_DATA19, 89, | ||
153 | "dss_data19", NULL, "mcspi3_simo", "dss_data1", | ||
154 | "gpio_89", NULL, NULL, "safe_mode"), | ||
155 | _OMAP3_MUXENTRY(DSS_DATA20, 90, | ||
156 | "dss_data20", NULL, "mcspi3_somi", "dss_data2", | ||
157 | "gpio_90", NULL, NULL, "safe_mode"), | ||
158 | _OMAP3_MUXENTRY(DSS_DATA21, 91, | ||
159 | "dss_data21", NULL, "mcspi3_cs0", "dss_data3", | ||
160 | "gpio_91", NULL, NULL, "safe_mode"), | ||
161 | _OMAP3_MUXENTRY(DSS_DATA22, 92, | ||
162 | "dss_data22", NULL, "mcspi3_cs1", "dss_data4", | ||
163 | "gpio_92", NULL, NULL, "safe_mode"), | ||
164 | _OMAP3_MUXENTRY(DSS_DATA23, 93, | ||
165 | "dss_data23", NULL, NULL, "dss_data5", | ||
166 | "gpio_93", NULL, NULL, "safe_mode"), | ||
167 | _OMAP3_MUXENTRY(DSS_DATA2, 72, | ||
168 | "dss_data2", NULL, NULL, NULL, | ||
169 | "gpio_72", NULL, NULL, "safe_mode"), | ||
170 | _OMAP3_MUXENTRY(DSS_DATA3, 73, | ||
171 | "dss_data3", NULL, NULL, NULL, | ||
172 | "gpio_73", NULL, NULL, "safe_mode"), | ||
173 | _OMAP3_MUXENTRY(DSS_DATA4, 74, | ||
174 | "dss_data4", NULL, "uart3_rx_irrx", NULL, | ||
175 | "gpio_74", NULL, NULL, "safe_mode"), | ||
176 | _OMAP3_MUXENTRY(DSS_DATA5, 75, | ||
177 | "dss_data5", NULL, "uart3_tx_irtx", NULL, | ||
178 | "gpio_75", NULL, NULL, "safe_mode"), | ||
179 | _OMAP3_MUXENTRY(DSS_DATA6, 76, | ||
180 | "dss_data6", NULL, "uart1_tx", NULL, | ||
181 | "gpio_76", "hw_dbg14", NULL, "safe_mode"), | ||
182 | _OMAP3_MUXENTRY(DSS_DATA7, 77, | ||
183 | "dss_data7", NULL, "uart1_rx", NULL, | ||
184 | "gpio_77", "hw_dbg15", NULL, "safe_mode"), | ||
185 | _OMAP3_MUXENTRY(DSS_DATA8, 78, | ||
186 | "dss_data8", NULL, NULL, NULL, | ||
187 | "gpio_78", "hw_dbg16", NULL, "safe_mode"), | ||
188 | _OMAP3_MUXENTRY(DSS_DATA9, 79, | ||
189 | "dss_data9", NULL, NULL, NULL, | ||
190 | "gpio_79", "hw_dbg17", NULL, "safe_mode"), | ||
191 | _OMAP3_MUXENTRY(DSS_HSYNC, 67, | ||
192 | "dss_hsync", NULL, NULL, NULL, | ||
193 | "gpio_67", "hw_dbg13", NULL, "safe_mode"), | ||
194 | _OMAP3_MUXENTRY(DSS_PCLK, 66, | ||
195 | "dss_pclk", NULL, NULL, NULL, | ||
196 | "gpio_66", "hw_dbg12", NULL, "safe_mode"), | ||
197 | _OMAP3_MUXENTRY(DSS_VSYNC, 68, | ||
198 | "dss_vsync", NULL, NULL, NULL, | ||
199 | "gpio_68", NULL, NULL, "safe_mode"), | ||
200 | _OMAP3_MUXENTRY(ETK_CLK, 12, | ||
201 | "etk_clk", "mcbsp5_clkx", "sdmmc3_clk", "hsusb1_stp", | ||
202 | "gpio_12", "mm1_rxdp", "hsusb1_tll_stp", "hw_dbg0"), | ||
203 | _OMAP3_MUXENTRY(ETK_CTL, 13, | ||
204 | "etk_ctl", NULL, "sdmmc3_cmd", "hsusb1_clk", | ||
205 | "gpio_13", NULL, "hsusb1_tll_clk", "hw_dbg1"), | ||
206 | _OMAP3_MUXENTRY(ETK_D0, 14, | ||
207 | "etk_d0", "mcspi3_simo", "sdmmc3_dat4", "hsusb1_data0", | ||
208 | "gpio_14", "mm1_rxrcv", "hsusb1_tll_data0", "hw_dbg2"), | ||
209 | _OMAP3_MUXENTRY(ETK_D1, 15, | ||
210 | "etk_d1", "mcspi3_somi", NULL, "hsusb1_data1", | ||
211 | "gpio_15", "mm1_txse0", "hsusb1_tll_data1", "hw_dbg3"), | ||
212 | _OMAP3_MUXENTRY(ETK_D10, 24, | ||
213 | "etk_d10", NULL, "uart1_rx", "hsusb2_clk", | ||
214 | "gpio_24", NULL, "hsusb2_tll_clk", "hw_dbg12"), | ||
215 | _OMAP3_MUXENTRY(ETK_D11, 25, | ||
216 | "etk_d11", NULL, NULL, "hsusb2_stp", | ||
217 | "gpio_25", "mm2_rxdp", "hsusb2_tll_stp", "hw_dbg13"), | ||
218 | _OMAP3_MUXENTRY(ETK_D12, 26, | ||
219 | "etk_d12", NULL, NULL, "hsusb2_dir", | ||
220 | "gpio_26", NULL, "hsusb2_tll_dir", "hw_dbg14"), | ||
221 | _OMAP3_MUXENTRY(ETK_D13, 27, | ||
222 | "etk_d13", NULL, NULL, "hsusb2_nxt", | ||
223 | "gpio_27", "mm2_rxdm", "hsusb2_tll_nxt", "hw_dbg15"), | ||
224 | _OMAP3_MUXENTRY(ETK_D14, 28, | ||
225 | "etk_d14", NULL, NULL, "hsusb2_data0", | ||
226 | "gpio_28", "mm2_rxrcv", "hsusb2_tll_data0", "hw_dbg16"), | ||
227 | _OMAP3_MUXENTRY(ETK_D15, 29, | ||
228 | "etk_d15", NULL, NULL, "hsusb2_data1", | ||
229 | "gpio_29", "mm2_txse0", "hsusb2_tll_data1", "hw_dbg17"), | ||
230 | _OMAP3_MUXENTRY(ETK_D2, 16, | ||
231 | "etk_d2", "mcspi3_cs0", NULL, "hsusb1_data2", | ||
232 | "gpio_16", "mm1_txdat", "hsusb1_tll_data2", "hw_dbg4"), | ||
233 | _OMAP3_MUXENTRY(ETK_D3, 17, | ||
234 | "etk_d3", "mcspi3_clk", "sdmmc3_dat3", "hsusb1_data7", | ||
235 | "gpio_17", NULL, "hsusb1_tll_data7", "hw_dbg5"), | ||
236 | _OMAP3_MUXENTRY(ETK_D4, 18, | ||
237 | "etk_d4", "mcbsp5_dr", "sdmmc3_dat0", "hsusb1_data4", | ||
238 | "gpio_18", NULL, "hsusb1_tll_data4", "hw_dbg6"), | ||
239 | _OMAP3_MUXENTRY(ETK_D5, 19, | ||
240 | "etk_d5", "mcbsp5_fsx", "sdmmc3_dat1", "hsusb1_data5", | ||
241 | "gpio_19", NULL, "hsusb1_tll_data5", "hw_dbg7"), | ||
242 | _OMAP3_MUXENTRY(ETK_D6, 20, | ||
243 | "etk_d6", "mcbsp5_dx", "sdmmc3_dat2", "hsusb1_data6", | ||
244 | "gpio_20", NULL, "hsusb1_tll_data6", "hw_dbg8"), | ||
245 | _OMAP3_MUXENTRY(ETK_D7, 21, | ||
246 | "etk_d7", "mcspi3_cs1", "sdmmc3_dat7", "hsusb1_data3", | ||
247 | "gpio_21", "mm1_txen_n", "hsusb1_tll_data3", "hw_dbg9"), | ||
248 | _OMAP3_MUXENTRY(ETK_D8, 22, | ||
249 | "etk_d8", "sys_drm_msecure", "sdmmc3_dat6", "hsusb1_dir", | ||
250 | "gpio_22", NULL, "hsusb1_tll_dir", "hw_dbg10"), | ||
251 | _OMAP3_MUXENTRY(ETK_D9, 23, | ||
252 | "etk_d9", "sys_secure_indicator", "sdmmc3_dat5", "hsusb1_nxt", | ||
253 | "gpio_23", "mm1_rxdm", "hsusb1_tll_nxt", "hw_dbg11"), | ||
254 | _OMAP3_MUXENTRY(GPMC_A1, 34, | ||
255 | "gpmc_a1", NULL, NULL, NULL, | ||
256 | "gpio_34", NULL, NULL, "safe_mode"), | ||
257 | _OMAP3_MUXENTRY(GPMC_A10, 43, | ||
258 | "gpmc_a10", "sys_ndmareq3", NULL, NULL, | ||
259 | "gpio_43", NULL, NULL, "safe_mode"), | ||
260 | _OMAP3_MUXENTRY(GPMC_A2, 35, | ||
261 | "gpmc_a2", NULL, NULL, NULL, | ||
262 | "gpio_35", NULL, NULL, "safe_mode"), | ||
263 | _OMAP3_MUXENTRY(GPMC_A3, 36, | ||
264 | "gpmc_a3", NULL, NULL, NULL, | ||
265 | "gpio_36", NULL, NULL, "safe_mode"), | ||
266 | _OMAP3_MUXENTRY(GPMC_A4, 37, | ||
267 | "gpmc_a4", NULL, NULL, NULL, | ||
268 | "gpio_37", NULL, NULL, "safe_mode"), | ||
269 | _OMAP3_MUXENTRY(GPMC_A5, 38, | ||
270 | "gpmc_a5", NULL, NULL, NULL, | ||
271 | "gpio_38", NULL, NULL, "safe_mode"), | ||
272 | _OMAP3_MUXENTRY(GPMC_A6, 39, | ||
273 | "gpmc_a6", NULL, NULL, NULL, | ||
274 | "gpio_39", NULL, NULL, "safe_mode"), | ||
275 | _OMAP3_MUXENTRY(GPMC_A7, 40, | ||
276 | "gpmc_a7", NULL, NULL, NULL, | ||
277 | "gpio_40", NULL, NULL, "safe_mode"), | ||
278 | _OMAP3_MUXENTRY(GPMC_A8, 41, | ||
279 | "gpmc_a8", NULL, NULL, NULL, | ||
280 | "gpio_41", NULL, NULL, "safe_mode"), | ||
281 | _OMAP3_MUXENTRY(GPMC_A9, 42, | ||
282 | "gpmc_a9", "sys_ndmareq2", NULL, NULL, | ||
283 | "gpio_42", NULL, NULL, "safe_mode"), | ||
284 | _OMAP3_MUXENTRY(GPMC_CLK, 59, | ||
285 | "gpmc_clk", NULL, NULL, NULL, | ||
286 | "gpio_59", NULL, NULL, "safe_mode"), | ||
287 | _OMAP3_MUXENTRY(GPMC_D10, 46, | ||
288 | "gpmc_d10", NULL, NULL, NULL, | ||
289 | "gpio_46", NULL, NULL, "safe_mode"), | ||
290 | _OMAP3_MUXENTRY(GPMC_D11, 47, | ||
291 | "gpmc_d11", NULL, NULL, NULL, | ||
292 | "gpio_47", NULL, NULL, "safe_mode"), | ||
293 | _OMAP3_MUXENTRY(GPMC_D12, 48, | ||
294 | "gpmc_d12", NULL, NULL, NULL, | ||
295 | "gpio_48", NULL, NULL, "safe_mode"), | ||
296 | _OMAP3_MUXENTRY(GPMC_D13, 49, | ||
297 | "gpmc_d13", NULL, NULL, NULL, | ||
298 | "gpio_49", NULL, NULL, "safe_mode"), | ||
299 | _OMAP3_MUXENTRY(GPMC_D14, 50, | ||
300 | "gpmc_d14", NULL, NULL, NULL, | ||
301 | "gpio_50", NULL, NULL, "safe_mode"), | ||
302 | _OMAP3_MUXENTRY(GPMC_D15, 51, | ||
303 | "gpmc_d15", NULL, NULL, NULL, | ||
304 | "gpio_51", NULL, NULL, "safe_mode"), | ||
305 | _OMAP3_MUXENTRY(GPMC_D8, 44, | ||
306 | "gpmc_d8", NULL, NULL, NULL, | ||
307 | "gpio_44", NULL, NULL, "safe_mode"), | ||
308 | _OMAP3_MUXENTRY(GPMC_D9, 45, | ||
309 | "gpmc_d9", NULL, NULL, NULL, | ||
310 | "gpio_45", NULL, NULL, "safe_mode"), | ||
311 | _OMAP3_MUXENTRY(GPMC_NBE0_CLE, 60, | ||
312 | "gpmc_nbe0_cle", NULL, NULL, NULL, | ||
313 | "gpio_60", NULL, NULL, "safe_mode"), | ||
314 | _OMAP3_MUXENTRY(GPMC_NBE1, 61, | ||
315 | "gpmc_nbe1", NULL, NULL, NULL, | ||
316 | "gpio_61", NULL, NULL, "safe_mode"), | ||
317 | _OMAP3_MUXENTRY(GPMC_NCS1, 52, | ||
318 | "gpmc_ncs1", NULL, NULL, NULL, | ||
319 | "gpio_52", NULL, NULL, "safe_mode"), | ||
320 | _OMAP3_MUXENTRY(GPMC_NCS2, 53, | ||
321 | "gpmc_ncs2", NULL, NULL, NULL, | ||
322 | "gpio_53", NULL, NULL, "safe_mode"), | ||
323 | _OMAP3_MUXENTRY(GPMC_NCS3, 54, | ||
324 | "gpmc_ncs3", "sys_ndmareq0", NULL, NULL, | ||
325 | "gpio_54", NULL, NULL, "safe_mode"), | ||
326 | _OMAP3_MUXENTRY(GPMC_NCS4, 55, | ||
327 | "gpmc_ncs4", "sys_ndmareq1", "mcbsp4_clkx", "gpt9_pwm_evt", | ||
328 | "gpio_55", NULL, NULL, "safe_mode"), | ||
329 | _OMAP3_MUXENTRY(GPMC_NCS5, 56, | ||
330 | "gpmc_ncs5", "sys_ndmareq2", "mcbsp4_dr", "gpt10_pwm_evt", | ||
331 | "gpio_56", NULL, NULL, "safe_mode"), | ||
332 | _OMAP3_MUXENTRY(GPMC_NCS6, 57, | ||
333 | "gpmc_ncs6", "sys_ndmareq3", "mcbsp4_dx", "gpt11_pwm_evt", | ||
334 | "gpio_57", NULL, NULL, "safe_mode"), | ||
335 | _OMAP3_MUXENTRY(GPMC_NCS7, 58, | ||
336 | "gpmc_ncs7", "gpmc_io_dir", "mcbsp4_fsx", "gpt8_pwm_evt", | ||
337 | "gpio_58", NULL, NULL, "safe_mode"), | ||
338 | _OMAP3_MUXENTRY(GPMC_NWP, 62, | ||
339 | "gpmc_nwp", NULL, NULL, NULL, | ||
340 | "gpio_62", NULL, NULL, "safe_mode"), | ||
341 | _OMAP3_MUXENTRY(GPMC_WAIT1, 63, | ||
342 | "gpmc_wait1", NULL, NULL, NULL, | ||
343 | "gpio_63", NULL, NULL, "safe_mode"), | ||
344 | _OMAP3_MUXENTRY(GPMC_WAIT2, 64, | ||
345 | "gpmc_wait2", NULL, NULL, NULL, | ||
346 | "gpio_64", NULL, NULL, "safe_mode"), | ||
347 | _OMAP3_MUXENTRY(GPMC_WAIT3, 65, | ||
348 | "gpmc_wait3", "sys_ndmareq1", NULL, NULL, | ||
349 | "gpio_65", NULL, NULL, "safe_mode"), | ||
350 | _OMAP3_MUXENTRY(HDQ_SIO, 170, | ||
351 | "hdq_sio", "sys_altclk", "i2c2_sccbe", "i2c3_sccbe", | ||
352 | "gpio_170", NULL, NULL, "safe_mode"), | ||
353 | _OMAP3_MUXENTRY(HSUSB0_CLK, 120, | ||
354 | "hsusb0_clk", NULL, NULL, NULL, | ||
355 | "gpio_120", NULL, NULL, "safe_mode"), | ||
356 | _OMAP3_MUXENTRY(HSUSB0_DATA0, 125, | ||
357 | "hsusb0_data0", NULL, "uart3_tx_irtx", NULL, | ||
358 | "gpio_125", NULL, NULL, "safe_mode"), | ||
359 | _OMAP3_MUXENTRY(HSUSB0_DATA1, 130, | ||
360 | "hsusb0_data1", NULL, "uart3_rx_irrx", NULL, | ||
361 | "gpio_130", NULL, NULL, "safe_mode"), | ||
362 | _OMAP3_MUXENTRY(HSUSB0_DATA2, 131, | ||
363 | "hsusb0_data2", NULL, "uart3_rts_sd", NULL, | ||
364 | "gpio_131", NULL, NULL, "safe_mode"), | ||
365 | _OMAP3_MUXENTRY(HSUSB0_DATA3, 169, | ||
366 | "hsusb0_data3", NULL, "uart3_cts_rctx", NULL, | ||
367 | "gpio_169", NULL, NULL, "safe_mode"), | ||
368 | _OMAP3_MUXENTRY(HSUSB0_DATA4, 188, | ||
369 | "hsusb0_data4", NULL, NULL, NULL, | ||
370 | "gpio_188", NULL, NULL, "safe_mode"), | ||
371 | _OMAP3_MUXENTRY(HSUSB0_DATA5, 189, | ||
372 | "hsusb0_data5", NULL, NULL, NULL, | ||
373 | "gpio_189", NULL, NULL, "safe_mode"), | ||
374 | _OMAP3_MUXENTRY(HSUSB0_DATA6, 190, | ||
375 | "hsusb0_data6", NULL, NULL, NULL, | ||
376 | "gpio_190", NULL, NULL, "safe_mode"), | ||
377 | _OMAP3_MUXENTRY(HSUSB0_DATA7, 191, | ||
378 | "hsusb0_data7", NULL, NULL, NULL, | ||
379 | "gpio_191", NULL, NULL, "safe_mode"), | ||
380 | _OMAP3_MUXENTRY(HSUSB0_DIR, 122, | ||
381 | "hsusb0_dir", NULL, NULL, NULL, | ||
382 | "gpio_122", NULL, NULL, "safe_mode"), | ||
383 | _OMAP3_MUXENTRY(HSUSB0_NXT, 124, | ||
384 | "hsusb0_nxt", NULL, NULL, NULL, | ||
385 | "gpio_124", NULL, NULL, "safe_mode"), | ||
386 | _OMAP3_MUXENTRY(HSUSB0_STP, 121, | ||
387 | "hsusb0_stp", NULL, NULL, NULL, | ||
388 | "gpio_121", NULL, NULL, "safe_mode"), | ||
389 | _OMAP3_MUXENTRY(I2C2_SCL, 168, | ||
390 | "i2c2_scl", NULL, NULL, NULL, | ||
391 | "gpio_168", NULL, NULL, "safe_mode"), | ||
392 | _OMAP3_MUXENTRY(I2C2_SDA, 183, | ||
393 | "i2c2_sda", NULL, NULL, NULL, | ||
394 | "gpio_183", NULL, NULL, "safe_mode"), | ||
395 | _OMAP3_MUXENTRY(I2C3_SCL, 184, | ||
396 | "i2c3_scl", NULL, NULL, NULL, | ||
397 | "gpio_184", NULL, NULL, "safe_mode"), | ||
398 | _OMAP3_MUXENTRY(I2C3_SDA, 185, | ||
399 | "i2c3_sda", NULL, NULL, NULL, | ||
400 | "gpio_185", NULL, NULL, "safe_mode"), | ||
401 | _OMAP3_MUXENTRY(I2C4_SCL, 0, | ||
402 | "i2c4_scl", "sys_nvmode1", NULL, NULL, | ||
403 | NULL, NULL, NULL, "safe_mode"), | ||
404 | _OMAP3_MUXENTRY(I2C4_SDA, 0, | ||
405 | "i2c4_sda", "sys_nvmode2", NULL, NULL, | ||
406 | NULL, NULL, NULL, "safe_mode"), | ||
407 | _OMAP3_MUXENTRY(JTAG_EMU0, 11, | ||
408 | "jtag_emu0", NULL, NULL, NULL, | ||
409 | "gpio_11", NULL, NULL, "safe_mode"), | ||
410 | _OMAP3_MUXENTRY(JTAG_EMU1, 31, | ||
411 | "jtag_emu1", NULL, NULL, NULL, | ||
412 | "gpio_31", NULL, NULL, "safe_mode"), | ||
413 | _OMAP3_MUXENTRY(MCBSP1_CLKR, 156, | ||
414 | "mcbsp1_clkr", "mcspi4_clk", NULL, NULL, | ||
415 | "gpio_156", NULL, NULL, "safe_mode"), | ||
416 | _OMAP3_MUXENTRY(MCBSP1_CLKX, 162, | ||
417 | "mcbsp1_clkx", NULL, "mcbsp3_clkx", NULL, | ||
418 | "gpio_162", NULL, NULL, "safe_mode"), | ||
419 | _OMAP3_MUXENTRY(MCBSP1_DR, 159, | ||
420 | "mcbsp1_dr", "mcspi4_somi", "mcbsp3_dr", NULL, | ||
421 | "gpio_159", NULL, NULL, "safe_mode"), | ||
422 | _OMAP3_MUXENTRY(MCBSP1_DX, 158, | ||
423 | "mcbsp1_dx", "mcspi4_simo", "mcbsp3_dx", NULL, | ||
424 | "gpio_158", NULL, NULL, "safe_mode"), | ||
425 | _OMAP3_MUXENTRY(MCBSP1_FSR, 157, | ||
426 | "mcbsp1_fsr", NULL, "cam_global_reset", NULL, | ||
427 | "gpio_157", NULL, NULL, "safe_mode"), | ||
428 | _OMAP3_MUXENTRY(MCBSP1_FSX, 161, | ||
429 | "mcbsp1_fsx", "mcspi4_cs0", "mcbsp3_fsx", NULL, | ||
430 | "gpio_161", NULL, NULL, "safe_mode"), | ||
431 | _OMAP3_MUXENTRY(MCBSP2_CLKX, 117, | ||
432 | "mcbsp2_clkx", NULL, NULL, NULL, | ||
433 | "gpio_117", NULL, NULL, "safe_mode"), | ||
434 | _OMAP3_MUXENTRY(MCBSP2_DR, 118, | ||
435 | "mcbsp2_dr", NULL, NULL, NULL, | ||
436 | "gpio_118", NULL, NULL, "safe_mode"), | ||
437 | _OMAP3_MUXENTRY(MCBSP2_DX, 119, | ||
438 | "mcbsp2_dx", NULL, NULL, NULL, | ||
439 | "gpio_119", NULL, NULL, "safe_mode"), | ||
440 | _OMAP3_MUXENTRY(MCBSP2_FSX, 116, | ||
441 | "mcbsp2_fsx", NULL, NULL, NULL, | ||
442 | "gpio_116", NULL, NULL, "safe_mode"), | ||
443 | _OMAP3_MUXENTRY(MCBSP3_CLKX, 142, | ||
444 | "mcbsp3_clkx", "uart2_tx", NULL, NULL, | ||
445 | "gpio_142", "hsusb3_tll_data6", NULL, "safe_mode"), | ||
446 | _OMAP3_MUXENTRY(MCBSP3_DR, 141, | ||
447 | "mcbsp3_dr", "uart2_rts", NULL, NULL, | ||
448 | "gpio_141", "hsusb3_tll_data5", NULL, "safe_mode"), | ||
449 | _OMAP3_MUXENTRY(MCBSP3_DX, 140, | ||
450 | "mcbsp3_dx", "uart2_cts", NULL, NULL, | ||
451 | "gpio_140", "hsusb3_tll_data4", NULL, "safe_mode"), | ||
452 | _OMAP3_MUXENTRY(MCBSP3_FSX, 143, | ||
453 | "mcbsp3_fsx", "uart2_rx", NULL, NULL, | ||
454 | "gpio_143", "hsusb3_tll_data7", NULL, "safe_mode"), | ||
455 | _OMAP3_MUXENTRY(MCBSP4_CLKX, 152, | ||
456 | "mcbsp4_clkx", NULL, NULL, NULL, | ||
457 | "gpio_152", "hsusb3_tll_data1", "mm3_txse0", "safe_mode"), | ||
458 | _OMAP3_MUXENTRY(MCBSP4_DR, 153, | ||
459 | "mcbsp4_dr", NULL, NULL, NULL, | ||
460 | "gpio_153", "hsusb3_tll_data0", "mm3_rxrcv", "safe_mode"), | ||
461 | _OMAP3_MUXENTRY(MCBSP4_DX, 154, | ||
462 | "mcbsp4_dx", NULL, NULL, NULL, | ||
463 | "gpio_154", "hsusb3_tll_data2", "mm3_txdat", "safe_mode"), | ||
464 | _OMAP3_MUXENTRY(MCBSP4_FSX, 155, | ||
465 | "mcbsp4_fsx", NULL, NULL, NULL, | ||
466 | "gpio_155", "hsusb3_tll_data3", "mm3_txen_n", "safe_mode"), | ||
467 | _OMAP3_MUXENTRY(MCBSP_CLKS, 160, | ||
468 | "mcbsp_clks", NULL, "cam_shutter", NULL, | ||
469 | "gpio_160", "uart1_cts", NULL, "safe_mode"), | ||
470 | _OMAP3_MUXENTRY(MCSPI1_CLK, 171, | ||
471 | "mcspi1_clk", "sdmmc2_dat4", NULL, NULL, | ||
472 | "gpio_171", NULL, NULL, "safe_mode"), | ||
473 | _OMAP3_MUXENTRY(MCSPI1_CS0, 174, | ||
474 | "mcspi1_cs0", "sdmmc2_dat7", NULL, NULL, | ||
475 | "gpio_174", NULL, NULL, "safe_mode"), | ||
476 | _OMAP3_MUXENTRY(MCSPI1_CS1, 175, | ||
477 | "mcspi1_cs1", NULL, NULL, "sdmmc3_cmd", | ||
478 | "gpio_175", NULL, NULL, "safe_mode"), | ||
479 | _OMAP3_MUXENTRY(MCSPI1_CS2, 176, | ||
480 | "mcspi1_cs2", NULL, NULL, "sdmmc3_clk", | ||
481 | "gpio_176", NULL, NULL, "safe_mode"), | ||
482 | _OMAP3_MUXENTRY(MCSPI1_CS3, 177, | ||
483 | "mcspi1_cs3", NULL, "hsusb2_tll_data2", "hsusb2_data2", | ||
484 | "gpio_177", "mm2_txdat", NULL, "safe_mode"), | ||
485 | _OMAP3_MUXENTRY(MCSPI1_SIMO, 172, | ||
486 | "mcspi1_simo", "sdmmc2_dat5", NULL, NULL, | ||
487 | "gpio_172", NULL, NULL, "safe_mode"), | ||
488 | _OMAP3_MUXENTRY(MCSPI1_SOMI, 173, | ||
489 | "mcspi1_somi", "sdmmc2_dat6", NULL, NULL, | ||
490 | "gpio_173", NULL, NULL, "safe_mode"), | ||
491 | _OMAP3_MUXENTRY(MCSPI2_CLK, 178, | ||
492 | "mcspi2_clk", NULL, "hsusb2_tll_data7", "hsusb2_data7", | ||
493 | "gpio_178", NULL, NULL, "safe_mode"), | ||
494 | _OMAP3_MUXENTRY(MCSPI2_CS0, 181, | ||
495 | "mcspi2_cs0", "gpt11_pwm_evt", | ||
496 | "hsusb2_tll_data6", "hsusb2_data6", | ||
497 | "gpio_181", NULL, NULL, "safe_mode"), | ||
498 | _OMAP3_MUXENTRY(MCSPI2_CS1, 182, | ||
499 | "mcspi2_cs1", "gpt8_pwm_evt", | ||
500 | "hsusb2_tll_data3", "hsusb2_data3", | ||
501 | "gpio_182", "mm2_txen_n", NULL, "safe_mode"), | ||
502 | _OMAP3_MUXENTRY(MCSPI2_SIMO, 179, | ||
503 | "mcspi2_simo", "gpt9_pwm_evt", | ||
504 | "hsusb2_tll_data4", "hsusb2_data4", | ||
505 | "gpio_179", NULL, NULL, "safe_mode"), | ||
506 | _OMAP3_MUXENTRY(MCSPI2_SOMI, 180, | ||
507 | "mcspi2_somi", "gpt10_pwm_evt", | ||
508 | "hsusb2_tll_data5", "hsusb2_data5", | ||
509 | "gpio_180", NULL, NULL, "safe_mode"), | ||
510 | _OMAP3_MUXENTRY(SDMMC1_CLK, 120, | ||
511 | "sdmmc1_clk", NULL, NULL, NULL, | ||
512 | "gpio_120", NULL, NULL, "safe_mode"), | ||
513 | _OMAP3_MUXENTRY(SDMMC1_CMD, 121, | ||
514 | "sdmmc1_cmd", NULL, NULL, NULL, | ||
515 | "gpio_121", NULL, NULL, "safe_mode"), | ||
516 | _OMAP3_MUXENTRY(SDMMC1_DAT0, 122, | ||
517 | "sdmmc1_dat0", NULL, NULL, NULL, | ||
518 | "gpio_122", NULL, NULL, "safe_mode"), | ||
519 | _OMAP3_MUXENTRY(SDMMC1_DAT1, 123, | ||
520 | "sdmmc1_dat1", NULL, NULL, NULL, | ||
521 | "gpio_123", NULL, NULL, "safe_mode"), | ||
522 | _OMAP3_MUXENTRY(SDMMC1_DAT2, 124, | ||
523 | "sdmmc1_dat2", NULL, NULL, NULL, | ||
524 | "gpio_124", NULL, NULL, "safe_mode"), | ||
525 | _OMAP3_MUXENTRY(SDMMC1_DAT3, 125, | ||
526 | "sdmmc1_dat3", NULL, NULL, NULL, | ||
527 | "gpio_125", NULL, NULL, "safe_mode"), | ||
528 | _OMAP3_MUXENTRY(SDMMC1_DAT4, 126, | ||
529 | "sdmmc1_dat4", NULL, "sim_io", NULL, | ||
530 | "gpio_126", NULL, NULL, "safe_mode"), | ||
531 | _OMAP3_MUXENTRY(SDMMC1_DAT5, 127, | ||
532 | "sdmmc1_dat5", NULL, "sim_clk", NULL, | ||
533 | "gpio_127", NULL, NULL, "safe_mode"), | ||
534 | _OMAP3_MUXENTRY(SDMMC1_DAT6, 128, | ||
535 | "sdmmc1_dat6", NULL, "sim_pwrctrl", NULL, | ||
536 | "gpio_128", NULL, NULL, "safe_mode"), | ||
537 | _OMAP3_MUXENTRY(SDMMC1_DAT7, 129, | ||
538 | "sdmmc1_dat7", NULL, "sim_rst", NULL, | ||
539 | "gpio_129", NULL, NULL, "safe_mode"), | ||
540 | _OMAP3_MUXENTRY(SDMMC2_CLK, 130, | ||
541 | "sdmmc2_clk", "mcspi3_clk", NULL, NULL, | ||
542 | "gpio_130", NULL, NULL, "safe_mode"), | ||
543 | _OMAP3_MUXENTRY(SDMMC2_CMD, 131, | ||
544 | "sdmmc2_cmd", "mcspi3_simo", NULL, NULL, | ||
545 | "gpio_131", NULL, NULL, "safe_mode"), | ||
546 | _OMAP3_MUXENTRY(SDMMC2_DAT0, 132, | ||
547 | "sdmmc2_dat0", "mcspi3_somi", NULL, NULL, | ||
548 | "gpio_132", NULL, NULL, "safe_mode"), | ||
549 | _OMAP3_MUXENTRY(SDMMC2_DAT1, 133, | ||
550 | "sdmmc2_dat1", NULL, NULL, NULL, | ||
551 | "gpio_133", NULL, NULL, "safe_mode"), | ||
552 | _OMAP3_MUXENTRY(SDMMC2_DAT2, 134, | ||
553 | "sdmmc2_dat2", "mcspi3_cs1", NULL, NULL, | ||
554 | "gpio_134", NULL, NULL, "safe_mode"), | ||
555 | _OMAP3_MUXENTRY(SDMMC2_DAT3, 135, | ||
556 | "sdmmc2_dat3", "mcspi3_cs0", NULL, NULL, | ||
557 | "gpio_135", NULL, NULL, "safe_mode"), | ||
558 | _OMAP3_MUXENTRY(SDMMC2_DAT4, 136, | ||
559 | "sdmmc2_dat4", "sdmmc2_dir_dat0", NULL, "sdmmc3_dat0", | ||
560 | "gpio_136", NULL, NULL, "safe_mode"), | ||
561 | _OMAP3_MUXENTRY(SDMMC2_DAT5, 137, | ||
562 | "sdmmc2_dat5", "sdmmc2_dir_dat1", | ||
563 | "cam_global_reset", "sdmmc3_dat1", | ||
564 | "gpio_137", "hsusb3_tll_stp", "mm3_rxdp", "safe_mode"), | ||
565 | _OMAP3_MUXENTRY(SDMMC2_DAT6, 138, | ||
566 | "sdmmc2_dat6", "sdmmc2_dir_cmd", "cam_shutter", "sdmmc3_dat2", | ||
567 | "gpio_138", "hsusb3_tll_dir", NULL, "safe_mode"), | ||
568 | _OMAP3_MUXENTRY(SDMMC2_DAT7, 139, | ||
569 | "sdmmc2_dat7", "sdmmc2_clkin", NULL, "sdmmc3_dat3", | ||
570 | "gpio_139", "hsusb3_tll_nxt", "mm3_rxdm", "safe_mode"), | ||
571 | _OMAP3_MUXENTRY(SDRC_CKE0, 0, | ||
572 | "sdrc_cke0", NULL, NULL, NULL, | ||
573 | NULL, NULL, NULL, "safe_mode"), | ||
574 | _OMAP3_MUXENTRY(SDRC_CKE1, 0, | ||
575 | "sdrc_cke1", NULL, NULL, NULL, | ||
576 | NULL, NULL, NULL, "safe_mode"), | ||
577 | _OMAP3_MUXENTRY(SYS_BOOT0, 2, | ||
578 | "sys_boot0", NULL, NULL, NULL, | ||
579 | "gpio_2", NULL, NULL, "safe_mode"), | ||
580 | _OMAP3_MUXENTRY(SYS_BOOT1, 3, | ||
581 | "sys_boot1", NULL, NULL, NULL, | ||
582 | "gpio_3", NULL, NULL, "safe_mode"), | ||
583 | _OMAP3_MUXENTRY(SYS_BOOT2, 4, | ||
584 | "sys_boot2", NULL, NULL, NULL, | ||
585 | "gpio_4", NULL, NULL, "safe_mode"), | ||
586 | _OMAP3_MUXENTRY(SYS_BOOT3, 5, | ||
587 | "sys_boot3", NULL, NULL, NULL, | ||
588 | "gpio_5", NULL, NULL, "safe_mode"), | ||
589 | _OMAP3_MUXENTRY(SYS_BOOT4, 6, | ||
590 | "sys_boot4", "sdmmc2_dir_dat2", NULL, NULL, | ||
591 | "gpio_6", NULL, NULL, "safe_mode"), | ||
592 | _OMAP3_MUXENTRY(SYS_BOOT5, 7, | ||
593 | "sys_boot5", "sdmmc2_dir_dat3", NULL, NULL, | ||
594 | "gpio_7", NULL, NULL, "safe_mode"), | ||
595 | _OMAP3_MUXENTRY(SYS_BOOT6, 8, | ||
596 | "sys_boot6", NULL, NULL, NULL, | ||
597 | "gpio_8", NULL, NULL, "safe_mode"), | ||
598 | _OMAP3_MUXENTRY(SYS_CLKOUT1, 10, | ||
599 | "sys_clkout1", NULL, NULL, NULL, | ||
600 | "gpio_10", NULL, NULL, "safe_mode"), | ||
601 | _OMAP3_MUXENTRY(SYS_CLKOUT2, 186, | ||
602 | "sys_clkout2", NULL, NULL, NULL, | ||
603 | "gpio_186", NULL, NULL, "safe_mode"), | ||
604 | _OMAP3_MUXENTRY(SYS_CLKREQ, 1, | ||
605 | "sys_clkreq", NULL, NULL, NULL, | ||
606 | "gpio_1", NULL, NULL, "safe_mode"), | ||
607 | _OMAP3_MUXENTRY(SYS_NIRQ, 0, | ||
608 | "sys_nirq", NULL, NULL, NULL, | ||
609 | "gpio_0", NULL, NULL, "safe_mode"), | ||
610 | _OMAP3_MUXENTRY(SYS_NRESWARM, 30, | ||
611 | "sys_nreswarm", NULL, NULL, NULL, | ||
612 | "gpio_30", NULL, NULL, "safe_mode"), | ||
613 | _OMAP3_MUXENTRY(SYS_OFF_MODE, 9, | ||
614 | "sys_off_mode", NULL, NULL, NULL, | ||
615 | "gpio_9", NULL, NULL, "safe_mode"), | ||
616 | _OMAP3_MUXENTRY(UART1_CTS, 150, | ||
617 | "uart1_cts", NULL, NULL, NULL, | ||
618 | "gpio_150", "hsusb3_tll_clk", NULL, "safe_mode"), | ||
619 | _OMAP3_MUXENTRY(UART1_RTS, 149, | ||
620 | "uart1_rts", NULL, NULL, NULL, | ||
621 | "gpio_149", NULL, NULL, "safe_mode"), | ||
622 | _OMAP3_MUXENTRY(UART1_RX, 151, | ||
623 | "uart1_rx", NULL, "mcbsp1_clkr", "mcspi4_clk", | ||
624 | "gpio_151", NULL, NULL, "safe_mode"), | ||
625 | _OMAP3_MUXENTRY(UART1_TX, 148, | ||
626 | "uart1_tx", NULL, NULL, NULL, | ||
627 | "gpio_148", NULL, NULL, "safe_mode"), | ||
628 | _OMAP3_MUXENTRY(UART2_CTS, 144, | ||
629 | "uart2_cts", "mcbsp3_dx", "gpt9_pwm_evt", NULL, | ||
630 | "gpio_144", NULL, NULL, "safe_mode"), | ||
631 | _OMAP3_MUXENTRY(UART2_RTS, 145, | ||
632 | "uart2_rts", "mcbsp3_dr", "gpt10_pwm_evt", NULL, | ||
633 | "gpio_145", NULL, NULL, "safe_mode"), | ||
634 | _OMAP3_MUXENTRY(UART2_RX, 147, | ||
635 | "uart2_rx", "mcbsp3_fsx", "gpt8_pwm_evt", NULL, | ||
636 | "gpio_147", NULL, NULL, "safe_mode"), | ||
637 | _OMAP3_MUXENTRY(UART2_TX, 146, | ||
638 | "uart2_tx", "mcbsp3_clkx", "gpt11_pwm_evt", NULL, | ||
639 | "gpio_146", NULL, NULL, "safe_mode"), | ||
640 | _OMAP3_MUXENTRY(UART3_CTS_RCTX, 163, | ||
641 | "uart3_cts_rctx", NULL, NULL, NULL, | ||
642 | "gpio_163", NULL, NULL, "safe_mode"), | ||
643 | _OMAP3_MUXENTRY(UART3_RTS_SD, 164, | ||
644 | "uart3_rts_sd", NULL, NULL, NULL, | ||
645 | "gpio_164", NULL, NULL, "safe_mode"), | ||
646 | _OMAP3_MUXENTRY(UART3_RX_IRRX, 165, | ||
647 | "uart3_rx_irrx", NULL, NULL, NULL, | ||
648 | "gpio_165", NULL, NULL, "safe_mode"), | ||
649 | _OMAP3_MUXENTRY(UART3_TX_IRTX, 166, | ||
650 | "uart3_tx_irtx", NULL, NULL, NULL, | ||
651 | "gpio_166", NULL, NULL, "safe_mode"), | ||
652 | { .reg_offset = OMAP_MUX_TERMINATOR }, | ||
653 | }; | ||
654 | |||
655 | /* | ||
656 | * Signals different on CBC package compared to the superset | ||
657 | */ | ||
658 | #if defined(CONFIG_OMAP_MUX) && defined(CONFIG_OMAP_PACKAGE_CBC) | ||
659 | struct omap_mux __initdata omap3_cbc_subset[] = { | ||
660 | { .reg_offset = OMAP_MUX_TERMINATOR }, | ||
661 | }; | ||
662 | #else | ||
663 | #define omap3_cbc_subset NULL | ||
664 | #endif | ||
665 | |||
666 | /* | ||
667 | * Balls for CBC package | ||
668 | * 515-pin s-PBGA Package, 0.65mm Ball Pitch (Top), 0.50mm Ball Pitch (Bottom) | ||
669 | * | ||
670 | * FIXME: What's up with the outdated TI documentation? See: | ||
671 | * | ||
672 | * http://wiki.davincidsp.com/index.php/Datasheet_Errata_for_OMAP35x_CBC_Package | ||
673 | * http://community.ti.com/forums/t/10982.aspx | ||
674 | */ | ||
675 | #if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \ | ||
676 | && defined(CONFIG_OMAP_PACKAGE_CBC) | ||
677 | struct omap_ball __initdata omap3_cbc_ball[] = { | ||
678 | _OMAP3_BALLENTRY(CAM_D0, "ae16", NULL), | ||
679 | _OMAP3_BALLENTRY(CAM_D1, "ae15", NULL), | ||
680 | _OMAP3_BALLENTRY(CAM_D10, "d25", NULL), | ||
681 | _OMAP3_BALLENTRY(CAM_D11, "e26", NULL), | ||
682 | _OMAP3_BALLENTRY(CAM_D2, "a24", NULL), | ||
683 | _OMAP3_BALLENTRY(CAM_D3, "b24", NULL), | ||
684 | _OMAP3_BALLENTRY(CAM_D4, "d24", NULL), | ||
685 | _OMAP3_BALLENTRY(CAM_D5, "c24", NULL), | ||
686 | _OMAP3_BALLENTRY(CAM_D6, "p25", NULL), | ||
687 | _OMAP3_BALLENTRY(CAM_D7, "p26", NULL), | ||
688 | _OMAP3_BALLENTRY(CAM_D8, "n25", NULL), | ||
689 | _OMAP3_BALLENTRY(CAM_D9, "n26", NULL), | ||
690 | _OMAP3_BALLENTRY(CAM_FLD, "b23", NULL), | ||
691 | _OMAP3_BALLENTRY(CAM_HS, "c23", NULL), | ||
692 | _OMAP3_BALLENTRY(CAM_PCLK, "c26", NULL), | ||
693 | _OMAP3_BALLENTRY(CAM_STROBE, "d26", NULL), | ||
694 | _OMAP3_BALLENTRY(CAM_VS, "d23", NULL), | ||
695 | _OMAP3_BALLENTRY(CAM_WEN, "a23", NULL), | ||
696 | _OMAP3_BALLENTRY(CAM_XCLKA, "c25", NULL), | ||
697 | _OMAP3_BALLENTRY(CAM_XCLKB, "e25", NULL), | ||
698 | _OMAP3_BALLENTRY(CSI2_DX0, "ad17", NULL), | ||
699 | _OMAP3_BALLENTRY(CSI2_DX1, "ae18", NULL), | ||
700 | _OMAP3_BALLENTRY(CSI2_DY0, "ad16", NULL), | ||
701 | _OMAP3_BALLENTRY(CSI2_DY1, "ae17", NULL), | ||
702 | _OMAP3_BALLENTRY(DSS_ACBIAS, "f26", NULL), | ||
703 | _OMAP3_BALLENTRY(DSS_DATA0, "ae21", NULL), | ||
704 | _OMAP3_BALLENTRY(DSS_DATA1, "ae22", NULL), | ||
705 | _OMAP3_BALLENTRY(DSS_DATA10, "ac26", NULL), | ||
706 | _OMAP3_BALLENTRY(DSS_DATA11, "ad26", NULL), | ||
707 | _OMAP3_BALLENTRY(DSS_DATA12, "aa25", NULL), | ||
708 | _OMAP3_BALLENTRY(DSS_DATA13, "y25", NULL), | ||
709 | _OMAP3_BALLENTRY(DSS_DATA14, "aa26", NULL), | ||
710 | _OMAP3_BALLENTRY(DSS_DATA15, "ab26", NULL), | ||
711 | _OMAP3_BALLENTRY(DSS_DATA16, "l25", NULL), | ||
712 | _OMAP3_BALLENTRY(DSS_DATA17, "l26", NULL), | ||
713 | _OMAP3_BALLENTRY(DSS_DATA18, "m24", NULL), | ||
714 | _OMAP3_BALLENTRY(DSS_DATA19, "m26", NULL), | ||
715 | _OMAP3_BALLENTRY(DSS_DATA2, "ae23", NULL), | ||
716 | _OMAP3_BALLENTRY(DSS_DATA20, "f25", NULL), | ||
717 | _OMAP3_BALLENTRY(DSS_DATA21, "n24", NULL), | ||
718 | _OMAP3_BALLENTRY(DSS_DATA22, "ac25", NULL), | ||
719 | _OMAP3_BALLENTRY(DSS_DATA23, "ab25", NULL), | ||
720 | _OMAP3_BALLENTRY(DSS_DATA3, "ae24", NULL), | ||
721 | _OMAP3_BALLENTRY(DSS_DATA4, "ad23", NULL), | ||
722 | _OMAP3_BALLENTRY(DSS_DATA5, "ad24", NULL), | ||
723 | _OMAP3_BALLENTRY(DSS_DATA6, "g26", NULL), | ||
724 | _OMAP3_BALLENTRY(DSS_DATA7, "h25", NULL), | ||
725 | _OMAP3_BALLENTRY(DSS_DATA8, "h26", NULL), | ||
726 | _OMAP3_BALLENTRY(DSS_DATA9, "j26", NULL), | ||
727 | _OMAP3_BALLENTRY(DSS_HSYNC, "k24", NULL), | ||
728 | _OMAP3_BALLENTRY(DSS_PCLK, "g25", NULL), | ||
729 | _OMAP3_BALLENTRY(DSS_VSYNC, "m25", NULL), | ||
730 | _OMAP3_BALLENTRY(ETK_CLK, "ab2", NULL), | ||
731 | _OMAP3_BALLENTRY(ETK_CTL, "ab3", NULL), | ||
732 | _OMAP3_BALLENTRY(ETK_D0, "ac3", NULL), | ||
733 | _OMAP3_BALLENTRY(ETK_D1, "ad4", NULL), | ||
734 | _OMAP3_BALLENTRY(ETK_D10, "ae4", NULL), | ||
735 | _OMAP3_BALLENTRY(ETK_D11, "af6", NULL), | ||
736 | _OMAP3_BALLENTRY(ETK_D12, "ae6", NULL), | ||
737 | _OMAP3_BALLENTRY(ETK_D13, "af7", NULL), | ||
738 | _OMAP3_BALLENTRY(ETK_D14, "af9", NULL), | ||
739 | _OMAP3_BALLENTRY(ETK_D15, "ae9", NULL), | ||
740 | _OMAP3_BALLENTRY(ETK_D2, "ad3", NULL), | ||
741 | _OMAP3_BALLENTRY(ETK_D3, "aa3", NULL), | ||
742 | _OMAP3_BALLENTRY(ETK_D4, "y3", NULL), | ||
743 | _OMAP3_BALLENTRY(ETK_D5, "ab1", NULL), | ||
744 | _OMAP3_BALLENTRY(ETK_D6, "ae3", NULL), | ||
745 | _OMAP3_BALLENTRY(ETK_D7, "ad2", NULL), | ||
746 | _OMAP3_BALLENTRY(ETK_D8, "aa4", NULL), | ||
747 | _OMAP3_BALLENTRY(ETK_D9, "v2", NULL), | ||
748 | _OMAP3_BALLENTRY(GPMC_A1, "j2", NULL), | ||
749 | _OMAP3_BALLENTRY(GPMC_A10, "d2", NULL), | ||
750 | _OMAP3_BALLENTRY(GPMC_A2, "h1", NULL), | ||
751 | _OMAP3_BALLENTRY(GPMC_A3, "h2", NULL), | ||
752 | _OMAP3_BALLENTRY(GPMC_A4, "g2", NULL), | ||
753 | _OMAP3_BALLENTRY(GPMC_A5, "f1", NULL), | ||
754 | _OMAP3_BALLENTRY(GPMC_A6, "f2", NULL), | ||
755 | _OMAP3_BALLENTRY(GPMC_A7, "e1", NULL), | ||
756 | _OMAP3_BALLENTRY(GPMC_A8, "e2", NULL), | ||
757 | _OMAP3_BALLENTRY(GPMC_A9, "d1", NULL), | ||
758 | _OMAP3_BALLENTRY(GPMC_CLK, "n1", "l1"), | ||
759 | _OMAP3_BALLENTRY(GPMC_D10, "t1", "n1"), | ||
760 | _OMAP3_BALLENTRY(GPMC_D11, "u2", "p2"), | ||
761 | _OMAP3_BALLENTRY(GPMC_D12, "u1", "p1"), | ||
762 | _OMAP3_BALLENTRY(GPMC_D13, "p1", "m1"), | ||
763 | _OMAP3_BALLENTRY(GPMC_D14, "l2", "j2"), | ||
764 | _OMAP3_BALLENTRY(GPMC_D15, "m2", "k2"), | ||
765 | _OMAP3_BALLENTRY(GPMC_D8, "v1", "r1"), | ||
766 | _OMAP3_BALLENTRY(GPMC_D9, "y1", "t1"), | ||
767 | _OMAP3_BALLENTRY(GPMC_NBE0_CLE, "k2", NULL), | ||
768 | _OMAP3_BALLENTRY(GPMC_NBE1, "j1", NULL), | ||
769 | _OMAP3_BALLENTRY(GPMC_NCS1, "ad1", "w1"), | ||
770 | _OMAP3_BALLENTRY(GPMC_NCS2, "a3", NULL), | ||
771 | _OMAP3_BALLENTRY(GPMC_NCS3, "b6", NULL), | ||
772 | _OMAP3_BALLENTRY(GPMC_NCS4, "b4", NULL), | ||
773 | _OMAP3_BALLENTRY(GPMC_NCS5, "c4", NULL), | ||
774 | _OMAP3_BALLENTRY(GPMC_NCS6, "b5", NULL), | ||
775 | _OMAP3_BALLENTRY(GPMC_NCS7, "c5", NULL), | ||
776 | _OMAP3_BALLENTRY(GPMC_NWP, "ac6", "y5"), | ||
777 | _OMAP3_BALLENTRY(GPMC_WAIT1, "ac8", "y8"), | ||
778 | _OMAP3_BALLENTRY(GPMC_WAIT2, "b3", NULL), | ||
779 | _OMAP3_BALLENTRY(GPMC_WAIT3, "c6", NULL), | ||
780 | _OMAP3_BALLENTRY(HDQ_SIO, "j23", NULL), | ||
781 | _OMAP3_BALLENTRY(HSUSB0_CLK, "w19", NULL), | ||
782 | _OMAP3_BALLENTRY(HSUSB0_DATA0, "v20", NULL), | ||
783 | _OMAP3_BALLENTRY(HSUSB0_DATA1, "y20", NULL), | ||
784 | _OMAP3_BALLENTRY(HSUSB0_DATA2, "v18", NULL), | ||
785 | _OMAP3_BALLENTRY(HSUSB0_DATA3, "w20", NULL), | ||
786 | _OMAP3_BALLENTRY(HSUSB0_DATA4, "w17", NULL), | ||
787 | _OMAP3_BALLENTRY(HSUSB0_DATA5, "y18", NULL), | ||
788 | _OMAP3_BALLENTRY(HSUSB0_DATA6, "y19", NULL), | ||
789 | _OMAP3_BALLENTRY(HSUSB0_DATA7, "y17", NULL), | ||
790 | _OMAP3_BALLENTRY(HSUSB0_DIR, "v19", NULL), | ||
791 | _OMAP3_BALLENTRY(HSUSB0_NXT, "w18", NULL), | ||
792 | _OMAP3_BALLENTRY(HSUSB0_STP, "u20", NULL), | ||
793 | _OMAP3_BALLENTRY(I2C2_SCL, "c2", NULL), | ||
794 | _OMAP3_BALLENTRY(I2C2_SDA, "c1", NULL), | ||
795 | _OMAP3_BALLENTRY(I2C3_SCL, "ab4", NULL), | ||
796 | _OMAP3_BALLENTRY(I2C3_SDA, "ac4", NULL), | ||
797 | _OMAP3_BALLENTRY(I2C4_SCL, "ad15", NULL), | ||
798 | _OMAP3_BALLENTRY(I2C4_SDA, "w16", NULL), | ||
799 | _OMAP3_BALLENTRY(JTAG_EMU0, "y15", NULL), | ||
800 | _OMAP3_BALLENTRY(JTAG_EMU1, "y14", NULL), | ||
801 | _OMAP3_BALLENTRY(MCBSP1_CLKR, "u19", NULL), | ||
802 | _OMAP3_BALLENTRY(MCBSP1_CLKX, "t17", NULL), | ||
803 | _OMAP3_BALLENTRY(MCBSP1_DR, "t20", NULL), | ||
804 | _OMAP3_BALLENTRY(MCBSP1_DX, "u17", NULL), | ||
805 | _OMAP3_BALLENTRY(MCBSP1_FSR, "v17", NULL), | ||
806 | _OMAP3_BALLENTRY(MCBSP1_FSX, "p20", NULL), | ||
807 | _OMAP3_BALLENTRY(MCBSP2_CLKX, "r18", NULL), | ||
808 | _OMAP3_BALLENTRY(MCBSP2_DR, "t18", NULL), | ||
809 | _OMAP3_BALLENTRY(MCBSP2_DX, "r19", NULL), | ||
810 | _OMAP3_BALLENTRY(MCBSP2_FSX, "u18", NULL), | ||
811 | _OMAP3_BALLENTRY(MCBSP3_CLKX, "u3", NULL), | ||
812 | _OMAP3_BALLENTRY(MCBSP3_DR, "n3", NULL), | ||
813 | _OMAP3_BALLENTRY(MCBSP3_DX, "p3", NULL), | ||
814 | _OMAP3_BALLENTRY(MCBSP3_FSX, "w3", NULL), | ||
815 | _OMAP3_BALLENTRY(MCBSP4_CLKX, "v3", NULL), | ||
816 | _OMAP3_BALLENTRY(MCBSP4_DR, "u4", NULL), | ||
817 | _OMAP3_BALLENTRY(MCBSP4_DX, "r3", NULL), | ||
818 | _OMAP3_BALLENTRY(MCBSP4_FSX, "t3", NULL), | ||
819 | _OMAP3_BALLENTRY(MCBSP_CLKS, "t19", NULL), | ||
820 | _OMAP3_BALLENTRY(MCSPI1_CLK, "p9", NULL), | ||
821 | _OMAP3_BALLENTRY(MCSPI1_CS0, "r7", NULL), | ||
822 | _OMAP3_BALLENTRY(MCSPI1_CS1, "r8", NULL), | ||
823 | _OMAP3_BALLENTRY(MCSPI1_CS2, "r9", NULL), | ||
824 | _OMAP3_BALLENTRY(MCSPI1_CS3, "t8", NULL), | ||
825 | _OMAP3_BALLENTRY(MCSPI1_SIMO, "p8", NULL), | ||
826 | _OMAP3_BALLENTRY(MCSPI1_SOMI, "p7", NULL), | ||
827 | _OMAP3_BALLENTRY(MCSPI2_CLK, "w7", NULL), | ||
828 | _OMAP3_BALLENTRY(MCSPI2_CS0, "v8", NULL), | ||
829 | _OMAP3_BALLENTRY(MCSPI2_CS1, "v9", NULL), | ||
830 | _OMAP3_BALLENTRY(MCSPI2_SIMO, "w8", NULL), | ||
831 | _OMAP3_BALLENTRY(MCSPI2_SOMI, "u8", NULL), | ||
832 | _OMAP3_BALLENTRY(SDMMC1_CLK, "n19", NULL), | ||
833 | _OMAP3_BALLENTRY(SDMMC1_CMD, "l18", NULL), | ||
834 | _OMAP3_BALLENTRY(SDMMC1_DAT0, "m19", NULL), | ||
835 | _OMAP3_BALLENTRY(SDMMC1_DAT1, "m18", NULL), | ||
836 | _OMAP3_BALLENTRY(SDMMC1_DAT2, "k18", NULL), | ||
837 | _OMAP3_BALLENTRY(SDMMC1_DAT3, "n20", NULL), | ||
838 | _OMAP3_BALLENTRY(SDMMC1_DAT4, "m20", NULL), | ||
839 | _OMAP3_BALLENTRY(SDMMC1_DAT5, "p17", NULL), | ||
840 | _OMAP3_BALLENTRY(SDMMC1_DAT6, "p18", NULL), | ||
841 | _OMAP3_BALLENTRY(SDMMC1_DAT7, "p19", NULL), | ||
842 | _OMAP3_BALLENTRY(SDMMC2_CLK, "w10", NULL), | ||
843 | _OMAP3_BALLENTRY(SDMMC2_CMD, "r10", NULL), | ||
844 | _OMAP3_BALLENTRY(SDMMC2_DAT0, "t10", NULL), | ||
845 | _OMAP3_BALLENTRY(SDMMC2_DAT1, "t9", NULL), | ||
846 | _OMAP3_BALLENTRY(SDMMC2_DAT2, "u10", NULL), | ||
847 | _OMAP3_BALLENTRY(SDMMC2_DAT3, "u9", NULL), | ||
848 | _OMAP3_BALLENTRY(SDMMC2_DAT4, "v10", NULL), | ||
849 | _OMAP3_BALLENTRY(SDMMC2_DAT5, "m3", NULL), | ||
850 | _OMAP3_BALLENTRY(SDMMC2_DAT6, "l3", NULL), | ||
851 | _OMAP3_BALLENTRY(SDMMC2_DAT7, "k3", NULL), | ||
852 | _OMAP3_BALLENTRY(SYS_BOOT0, "f3", NULL), | ||
853 | _OMAP3_BALLENTRY(SYS_BOOT1, "d3", NULL), | ||
854 | _OMAP3_BALLENTRY(SYS_BOOT2, "c3", NULL), | ||
855 | _OMAP3_BALLENTRY(SYS_BOOT3, "e3", NULL), | ||
856 | _OMAP3_BALLENTRY(SYS_BOOT4, "e4", NULL), | ||
857 | _OMAP3_BALLENTRY(SYS_BOOT5, "g3", NULL), | ||
858 | _OMAP3_BALLENTRY(SYS_BOOT6, "d4", NULL), | ||
859 | _OMAP3_BALLENTRY(SYS_CLKOUT1, "ae14", NULL), | ||
860 | _OMAP3_BALLENTRY(SYS_CLKOUT2, "w11", NULL), | ||
861 | _OMAP3_BALLENTRY(SYS_CLKREQ, "w15", NULL), | ||
862 | _OMAP3_BALLENTRY(SYS_NIRQ, "v16", NULL), | ||
863 | _OMAP3_BALLENTRY(SYS_NRESWARM, "ad7", "aa5"), | ||
864 | _OMAP3_BALLENTRY(SYS_OFF_MODE, "v12", NULL), | ||
865 | _OMAP3_BALLENTRY(UART1_CTS, "w2", NULL), | ||
866 | _OMAP3_BALLENTRY(UART1_RTS, "r2", NULL), | ||
867 | _OMAP3_BALLENTRY(UART1_RX, "h3", NULL), | ||
868 | _OMAP3_BALLENTRY(UART1_TX, "l4", NULL), | ||
869 | _OMAP3_BALLENTRY(UART2_CTS, "y24", NULL), | ||
870 | _OMAP3_BALLENTRY(UART2_RTS, "aa24", NULL), | ||
871 | _OMAP3_BALLENTRY(UART2_RX, "ad21", NULL), | ||
872 | _OMAP3_BALLENTRY(UART2_TX, "ad22", NULL), | ||
873 | _OMAP3_BALLENTRY(UART3_CTS_RCTX, "f23", NULL), | ||
874 | _OMAP3_BALLENTRY(UART3_RTS_SD, "f24", NULL), | ||
875 | _OMAP3_BALLENTRY(UART3_RX_IRRX, "h24", NULL), | ||
876 | _OMAP3_BALLENTRY(UART3_TX_IRTX, "g24", NULL), | ||
877 | { .reg_offset = OMAP_MUX_TERMINATOR }, | ||
878 | }; | ||
879 | #else | ||
880 | #define omap3_cbc_ball NULL | ||
881 | #endif | ||
882 | |||
883 | /* | ||
884 | * Signals different on CUS package compared to superset | ||
885 | */ | ||
886 | #if defined(CONFIG_OMAP_MUX) && defined(CONFIG_OMAP_PACKAGE_CUS) | ||
887 | struct omap_mux __initdata omap3_cus_subset[] = { | ||
888 | _OMAP3_MUXENTRY(CAM_D10, 109, | ||
889 | "cam_d10", NULL, NULL, NULL, | ||
890 | "gpio_109", NULL, NULL, "safe_mode"), | ||
891 | _OMAP3_MUXENTRY(CAM_D11, 110, | ||
892 | "cam_d11", NULL, NULL, NULL, | ||
893 | "gpio_110", NULL, NULL, "safe_mode"), | ||
894 | _OMAP3_MUXENTRY(CAM_D2, 101, | ||
895 | "cam_d2", NULL, NULL, NULL, | ||
896 | "gpio_101", NULL, NULL, "safe_mode"), | ||
897 | _OMAP3_MUXENTRY(CAM_D3, 102, | ||
898 | "cam_d3", NULL, NULL, NULL, | ||
899 | "gpio_102", NULL, NULL, "safe_mode"), | ||
900 | _OMAP3_MUXENTRY(CAM_D4, 103, | ||
901 | "cam_d4", NULL, NULL, NULL, | ||
902 | "gpio_103", NULL, NULL, "safe_mode"), | ||
903 | _OMAP3_MUXENTRY(CAM_D5, 104, | ||
904 | "cam_d5", NULL, NULL, NULL, | ||
905 | "gpio_104", NULL, NULL, "safe_mode"), | ||
906 | _OMAP3_MUXENTRY(CAM_FLD, 98, | ||
907 | "cam_fld", NULL, "cam_global_reset", NULL, | ||
908 | "gpio_98", NULL, NULL, "safe_mode"), | ||
909 | _OMAP3_MUXENTRY(CAM_HS, 94, | ||
910 | "cam_hs", NULL, NULL, NULL, | ||
911 | "gpio_94", NULL, NULL, "safe_mode"), | ||
912 | _OMAP3_MUXENTRY(CAM_PCLK, 97, | ||
913 | "cam_pclk", NULL, NULL, NULL, | ||
914 | "gpio_97", NULL, NULL, "safe_mode"), | ||
915 | _OMAP3_MUXENTRY(CAM_STROBE, 126, | ||
916 | "cam_strobe", NULL, NULL, NULL, | ||
917 | "gpio_126", NULL, NULL, "safe_mode"), | ||
918 | _OMAP3_MUXENTRY(CAM_VS, 95, | ||
919 | "cam_vs", NULL, NULL, NULL, | ||
920 | "gpio_95", NULL, NULL, "safe_mode"), | ||
921 | _OMAP3_MUXENTRY(CAM_WEN, 167, | ||
922 | "cam_wen", NULL, "cam_shutter", NULL, | ||
923 | "gpio_167", NULL, NULL, "safe_mode"), | ||
924 | _OMAP3_MUXENTRY(DSS_DATA6, 76, | ||
925 | "dss_data6", NULL, "uart1_tx", NULL, | ||
926 | "gpio_76", NULL, NULL, "safe_mode"), | ||
927 | _OMAP3_MUXENTRY(DSS_DATA7, 77, | ||
928 | "dss_data7", NULL, "uart1_rx", NULL, | ||
929 | "gpio_77", NULL, NULL, "safe_mode"), | ||
930 | _OMAP3_MUXENTRY(DSS_DATA8, 78, | ||
931 | "dss_data8", NULL, NULL, NULL, | ||
932 | "gpio_78", NULL, NULL, "safe_mode"), | ||
933 | _OMAP3_MUXENTRY(DSS_DATA9, 79, | ||
934 | "dss_data9", NULL, NULL, NULL, | ||
935 | "gpio_79", NULL, NULL, "safe_mode"), | ||
936 | _OMAP3_MUXENTRY(DSS_HSYNC, 67, | ||
937 | "dss_hsync", NULL, NULL, NULL, | ||
938 | "gpio_67", NULL, NULL, "safe_mode"), | ||
939 | _OMAP3_MUXENTRY(DSS_PCLK, 66, | ||
940 | "dss_pclk", NULL, NULL, NULL, | ||
941 | "gpio_66", NULL, NULL, "safe_mode"), | ||
942 | _OMAP3_MUXENTRY(ETK_CLK, 12, | ||
943 | "etk_clk", "mcbsp5_clkx", "sdmmc3_clk", "hsusb1_stp", | ||
944 | "gpio_12", "mm1_rxdp", "hsusb1_tll_stp", NULL), | ||
945 | _OMAP3_MUXENTRY(ETK_CTL, 13, | ||
946 | "etk_ctl", NULL, "sdmmc3_cmd", "hsusb1_clk", | ||
947 | "gpio_13", NULL, "hsusb1_tll_clk", NULL), | ||
948 | _OMAP3_MUXENTRY(ETK_D0, 14, | ||
949 | "etk_d0", "mcspi3_simo", "sdmmc3_dat4", "hsusb1_data0", | ||
950 | "gpio_14", "mm1_rxrcv", "hsusb1_tll_data0", NULL), | ||
951 | _OMAP3_MUXENTRY(ETK_D1, 15, | ||
952 | "etk_d1", "mcspi3_somi", NULL, "hsusb1_data1", | ||
953 | "gpio_15", "mm1_txse0", "hsusb1_tll_data1", NULL), | ||
954 | _OMAP3_MUXENTRY(ETK_D10, 24, | ||
955 | "etk_d10", NULL, "uart1_rx", "hsusb2_clk", | ||
956 | "gpio_24", NULL, "hsusb2_tll_clk", NULL), | ||
957 | _OMAP3_MUXENTRY(ETK_D11, 25, | ||
958 | "etk_d11", NULL, NULL, "hsusb2_stp", | ||
959 | "gpio_25", "mm2_rxdp", "hsusb2_tll_stp", NULL), | ||
960 | _OMAP3_MUXENTRY(ETK_D12, 26, | ||
961 | "etk_d12", NULL, NULL, "hsusb2_dir", | ||
962 | "gpio_26", NULL, "hsusb2_tll_dir", NULL), | ||
963 | _OMAP3_MUXENTRY(ETK_D13, 27, | ||
964 | "etk_d13", NULL, NULL, "hsusb2_nxt", | ||
965 | "gpio_27", "mm2_rxdm", "hsusb2_tll_nxt", NULL), | ||
966 | _OMAP3_MUXENTRY(ETK_D14, 28, | ||
967 | "etk_d14", NULL, NULL, "hsusb2_data0", | ||
968 | "gpio_28", "mm2_rxrcv", "hsusb2_tll_data0", NULL), | ||
969 | _OMAP3_MUXENTRY(ETK_D15, 29, | ||
970 | "etk_d15", NULL, NULL, "hsusb2_data1", | ||
971 | "gpio_29", "mm2_txse0", "hsusb2_tll_data1", NULL), | ||
972 | _OMAP3_MUXENTRY(ETK_D2, 16, | ||
973 | "etk_d2", "mcspi3_cs0", NULL, "hsusb1_data2", | ||
974 | "gpio_16", "mm1_txdat", "hsusb1_tll_data2", NULL), | ||
975 | _OMAP3_MUXENTRY(ETK_D3, 17, | ||
976 | "etk_d3", "mcspi3_clk", "sdmmc3_dat3", "hsusb1_data7", | ||
977 | "gpio_17", NULL, "hsusb1_tll_data7", NULL), | ||
978 | _OMAP3_MUXENTRY(ETK_D4, 18, | ||
979 | "etk_d4", "mcbsp5_dr", "sdmmc3_dat0", "hsusb1_data4", | ||
980 | "gpio_18", NULL, "hsusb1_tll_data4", NULL), | ||
981 | _OMAP3_MUXENTRY(ETK_D5, 19, | ||
982 | "etk_d5", "mcbsp5_fsx", "sdmmc3_dat1", "hsusb1_data5", | ||
983 | "gpio_19", NULL, "hsusb1_tll_data5", NULL), | ||
984 | _OMAP3_MUXENTRY(ETK_D6, 20, | ||
985 | "etk_d6", "mcbsp5_dx", "sdmmc3_dat2", "hsusb1_data6", | ||
986 | "gpio_20", NULL, "hsusb1_tll_data6", NULL), | ||
987 | _OMAP3_MUXENTRY(ETK_D7, 21, | ||
988 | "etk_d7", "mcspi3_cs1", "sdmmc3_dat7", "hsusb1_data3", | ||
989 | "gpio_21", "mm1_txen_n", "hsusb1_tll_data3", NULL), | ||
990 | _OMAP3_MUXENTRY(ETK_D8, 22, | ||
991 | "etk_d8", "sys_drm_msecure", "sdmmc3_dat6", "hsusb1_dir", | ||
992 | "gpio_22", NULL, "hsusb1_tll_dir", NULL), | ||
993 | _OMAP3_MUXENTRY(ETK_D9, 23, | ||
994 | "etk_d9", "sys_secure_indicator", "sdmmc3_dat5", "hsusb1_nxt", | ||
995 | "gpio_23", "mm1_rxdm", "hsusb1_tll_nxt", NULL), | ||
996 | _OMAP3_MUXENTRY(MCBSP3_CLKX, 142, | ||
997 | "mcbsp3_clkx", "uart2_tx", NULL, NULL, | ||
998 | "gpio_142", NULL, NULL, "safe_mode"), | ||
999 | _OMAP3_MUXENTRY(MCBSP3_DR, 141, | ||
1000 | "mcbsp3_dr", "uart2_rts", NULL, NULL, | ||
1001 | "gpio_141", NULL, NULL, "safe_mode"), | ||
1002 | _OMAP3_MUXENTRY(MCBSP3_DX, 140, | ||
1003 | "mcbsp3_dx", "uart2_cts", NULL, NULL, | ||
1004 | "gpio_140", NULL, NULL, "safe_mode"), | ||
1005 | _OMAP3_MUXENTRY(MCBSP3_FSX, 143, | ||
1006 | "mcbsp3_fsx", "uart2_rx", NULL, NULL, | ||
1007 | "gpio_143", NULL, NULL, "safe_mode"), | ||
1008 | _OMAP3_MUXENTRY(SDMMC2_DAT5, 137, | ||
1009 | "sdmmc2_dat5", "sdmmc2_dir_dat1", | ||
1010 | "cam_global_reset", "sdmmc3_dat1", | ||
1011 | "gpio_137", NULL, NULL, "safe_mode"), | ||
1012 | _OMAP3_MUXENTRY(SDMMC2_DAT6, 138, | ||
1013 | "sdmmc2_dat6", "sdmmc2_dir_cmd", "cam_shutter", "sdmmc3_dat2", | ||
1014 | "gpio_138", NULL, NULL, "safe_mode"), | ||
1015 | _OMAP3_MUXENTRY(SDMMC2_DAT7, 139, | ||
1016 | "sdmmc2_dat7", "sdmmc2_clkin", NULL, "sdmmc3_dat3", | ||
1017 | "gpio_139", NULL, NULL, "safe_mode"), | ||
1018 | _OMAP3_MUXENTRY(UART1_CTS, 150, | ||
1019 | "uart1_cts", NULL, NULL, NULL, | ||
1020 | "gpio_150", NULL, NULL, "safe_mode"), | ||
1021 | { .reg_offset = OMAP_MUX_TERMINATOR }, | ||
1022 | }; | ||
1023 | #else | ||
1024 | #define omap3_cus_subset NULL | ||
1025 | #endif | ||
1026 | |||
1027 | /* | ||
1028 | * Balls for CUS package | ||
1029 | * 423-pin s-PBGA Package, 0.65mm Ball Pitch (Bottom) | ||
1030 | */ | ||
1031 | #if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \ | ||
1032 | && defined(CONFIG_OMAP_PACKAGE_CUS) | ||
1033 | struct omap_ball __initdata omap3_cus_ball[] = { | ||
1034 | _OMAP3_BALLENTRY(CAM_D0, "ab18", NULL), | ||
1035 | _OMAP3_BALLENTRY(CAM_D1, "ac18", NULL), | ||
1036 | _OMAP3_BALLENTRY(CAM_D10, "f21", NULL), | ||
1037 | _OMAP3_BALLENTRY(CAM_D11, "g21", NULL), | ||
1038 | _OMAP3_BALLENTRY(CAM_D2, "g19", NULL), | ||
1039 | _OMAP3_BALLENTRY(CAM_D3, "f19", NULL), | ||
1040 | _OMAP3_BALLENTRY(CAM_D4, "g20", NULL), | ||
1041 | _OMAP3_BALLENTRY(CAM_D5, "b21", NULL), | ||
1042 | _OMAP3_BALLENTRY(CAM_D6, "l24", NULL), | ||
1043 | _OMAP3_BALLENTRY(CAM_D7, "k24", NULL), | ||
1044 | _OMAP3_BALLENTRY(CAM_D8, "j23", NULL), | ||
1045 | _OMAP3_BALLENTRY(CAM_D9, "k23", NULL), | ||
1046 | _OMAP3_BALLENTRY(CAM_FLD, "h24", NULL), | ||
1047 | _OMAP3_BALLENTRY(CAM_HS, "a22", NULL), | ||
1048 | _OMAP3_BALLENTRY(CAM_PCLK, "j19", NULL), | ||
1049 | _OMAP3_BALLENTRY(CAM_STROBE, "j20", NULL), | ||
1050 | _OMAP3_BALLENTRY(CAM_VS, "e18", NULL), | ||
1051 | _OMAP3_BALLENTRY(CAM_WEN, "f18", NULL), | ||
1052 | _OMAP3_BALLENTRY(CAM_XCLKA, "b22", NULL), | ||
1053 | _OMAP3_BALLENTRY(CAM_XCLKB, "c22", NULL), | ||
1054 | _OMAP3_BALLENTRY(DSS_ACBIAS, "j21", NULL), | ||
1055 | _OMAP3_BALLENTRY(DSS_DATA0, "ac19", NULL), | ||
1056 | _OMAP3_BALLENTRY(DSS_DATA1, "ab19", NULL), | ||
1057 | _OMAP3_BALLENTRY(DSS_DATA10, "ac22", NULL), | ||
1058 | _OMAP3_BALLENTRY(DSS_DATA11, "ac23", NULL), | ||
1059 | _OMAP3_BALLENTRY(DSS_DATA12, "ab22", NULL), | ||
1060 | _OMAP3_BALLENTRY(DSS_DATA13, "y22", NULL), | ||
1061 | _OMAP3_BALLENTRY(DSS_DATA14, "w22", NULL), | ||
1062 | _OMAP3_BALLENTRY(DSS_DATA15, "v22", NULL), | ||
1063 | _OMAP3_BALLENTRY(DSS_DATA16, "j22", NULL), | ||
1064 | _OMAP3_BALLENTRY(DSS_DATA17, "g23", NULL), | ||
1065 | _OMAP3_BALLENTRY(DSS_DATA18, "g24", NULL), | ||
1066 | _OMAP3_BALLENTRY(DSS_DATA19, "h23", NULL), | ||
1067 | _OMAP3_BALLENTRY(DSS_DATA2, "ad20", NULL), | ||
1068 | _OMAP3_BALLENTRY(DSS_DATA20, "d23", NULL), | ||
1069 | _OMAP3_BALLENTRY(DSS_DATA21, "k22", NULL), | ||
1070 | _OMAP3_BALLENTRY(DSS_DATA22, "v21", NULL), | ||
1071 | _OMAP3_BALLENTRY(DSS_DATA23, "w21", NULL), | ||
1072 | _OMAP3_BALLENTRY(DSS_DATA3, "ac20", NULL), | ||
1073 | _OMAP3_BALLENTRY(DSS_DATA4, "ad21", NULL), | ||
1074 | _OMAP3_BALLENTRY(DSS_DATA5, "ac21", NULL), | ||
1075 | _OMAP3_BALLENTRY(DSS_DATA6, "d24", NULL), | ||
1076 | _OMAP3_BALLENTRY(DSS_DATA7, "e23", NULL), | ||
1077 | _OMAP3_BALLENTRY(DSS_DATA8, "e24", NULL), | ||
1078 | _OMAP3_BALLENTRY(DSS_DATA9, "f23", NULL), | ||
1079 | _OMAP3_BALLENTRY(DSS_HSYNC, "e22", NULL), | ||
1080 | _OMAP3_BALLENTRY(DSS_PCLK, "g22", NULL), | ||
1081 | _OMAP3_BALLENTRY(DSS_VSYNC, "f22", NULL), | ||
1082 | _OMAP3_BALLENTRY(ETK_CLK, "ac1", NULL), | ||
1083 | _OMAP3_BALLENTRY(ETK_CTL, "ad3", NULL), | ||
1084 | _OMAP3_BALLENTRY(ETK_D0, "ad6", NULL), | ||
1085 | _OMAP3_BALLENTRY(ETK_D1, "ac6", NULL), | ||
1086 | _OMAP3_BALLENTRY(ETK_D10, "ac3", NULL), | ||
1087 | _OMAP3_BALLENTRY(ETK_D11, "ac9", NULL), | ||
1088 | _OMAP3_BALLENTRY(ETK_D12, "ac10", NULL), | ||
1089 | _OMAP3_BALLENTRY(ETK_D13, "ad11", NULL), | ||
1090 | _OMAP3_BALLENTRY(ETK_D14, "ac11", NULL), | ||
1091 | _OMAP3_BALLENTRY(ETK_D15, "ad12", NULL), | ||
1092 | _OMAP3_BALLENTRY(ETK_D2, "ac7", NULL), | ||
1093 | _OMAP3_BALLENTRY(ETK_D3, "ad8", NULL), | ||
1094 | _OMAP3_BALLENTRY(ETK_D4, "ac5", NULL), | ||
1095 | _OMAP3_BALLENTRY(ETK_D5, "ad2", NULL), | ||
1096 | _OMAP3_BALLENTRY(ETK_D6, "ac8", NULL), | ||
1097 | _OMAP3_BALLENTRY(ETK_D7, "ad9", NULL), | ||
1098 | _OMAP3_BALLENTRY(ETK_D8, "ac4", NULL), | ||
1099 | _OMAP3_BALLENTRY(ETK_D9, "ad5", NULL), | ||
1100 | _OMAP3_BALLENTRY(GPMC_A1, "k4", NULL), | ||
1101 | _OMAP3_BALLENTRY(GPMC_A10, "g2", NULL), | ||
1102 | _OMAP3_BALLENTRY(GPMC_A2, "k3", NULL), | ||
1103 | _OMAP3_BALLENTRY(GPMC_A3, "k2", NULL), | ||
1104 | _OMAP3_BALLENTRY(GPMC_A4, "j4", NULL), | ||
1105 | _OMAP3_BALLENTRY(GPMC_A5, "j3", NULL), | ||
1106 | _OMAP3_BALLENTRY(GPMC_A6, "j2", NULL), | ||
1107 | _OMAP3_BALLENTRY(GPMC_A7, "j1", NULL), | ||
1108 | _OMAP3_BALLENTRY(GPMC_A8, "h1", NULL), | ||
1109 | _OMAP3_BALLENTRY(GPMC_A9, "h2", NULL), | ||
1110 | _OMAP3_BALLENTRY(GPMC_CLK, "w2", NULL), | ||
1111 | _OMAP3_BALLENTRY(GPMC_D10, "u1", NULL), | ||
1112 | _OMAP3_BALLENTRY(GPMC_D11, "r3", NULL), | ||
1113 | _OMAP3_BALLENTRY(GPMC_D12, "t3", NULL), | ||
1114 | _OMAP3_BALLENTRY(GPMC_D13, "u2", NULL), | ||
1115 | _OMAP3_BALLENTRY(GPMC_D14, "v1", NULL), | ||
1116 | _OMAP3_BALLENTRY(GPMC_D15, "v2", NULL), | ||
1117 | _OMAP3_BALLENTRY(GPMC_D8, "r2", NULL), | ||
1118 | _OMAP3_BALLENTRY(GPMC_D9, "t2", NULL), | ||
1119 | _OMAP3_BALLENTRY(GPMC_NBE0_CLE, "k5", NULL), | ||
1120 | _OMAP3_BALLENTRY(GPMC_NBE1, "l1", NULL), | ||
1121 | _OMAP3_BALLENTRY(GPMC_NCS3, "d2", NULL), | ||
1122 | _OMAP3_BALLENTRY(GPMC_NCS4, "f4", NULL), | ||
1123 | _OMAP3_BALLENTRY(GPMC_NCS5, "g5", NULL), | ||
1124 | _OMAP3_BALLENTRY(GPMC_NCS6, "f3", NULL), | ||
1125 | _OMAP3_BALLENTRY(GPMC_NCS7, "g4", NULL), | ||
1126 | _OMAP3_BALLENTRY(GPMC_NWP, "e1", NULL), | ||
1127 | _OMAP3_BALLENTRY(GPMC_WAIT3, "c2", NULL), | ||
1128 | _OMAP3_BALLENTRY(HDQ_SIO, "a24", NULL), | ||
1129 | _OMAP3_BALLENTRY(HSUSB0_CLK, "r21", NULL), | ||
1130 | _OMAP3_BALLENTRY(HSUSB0_DATA0, "t24", NULL), | ||
1131 | _OMAP3_BALLENTRY(HSUSB0_DATA1, "t23", NULL), | ||
1132 | _OMAP3_BALLENTRY(HSUSB0_DATA2, "u24", NULL), | ||
1133 | _OMAP3_BALLENTRY(HSUSB0_DATA3, "u23", NULL), | ||
1134 | _OMAP3_BALLENTRY(HSUSB0_DATA4, "w24", NULL), | ||
1135 | _OMAP3_BALLENTRY(HSUSB0_DATA5, "v23", NULL), | ||
1136 | _OMAP3_BALLENTRY(HSUSB0_DATA6, "w23", NULL), | ||
1137 | _OMAP3_BALLENTRY(HSUSB0_DATA7, "t22", NULL), | ||
1138 | _OMAP3_BALLENTRY(HSUSB0_DIR, "p23", NULL), | ||
1139 | _OMAP3_BALLENTRY(HSUSB0_NXT, "r22", NULL), | ||
1140 | _OMAP3_BALLENTRY(HSUSB0_STP, "r23", NULL), | ||
1141 | _OMAP3_BALLENTRY(I2C2_SCL, "ac15", NULL), | ||
1142 | _OMAP3_BALLENTRY(I2C2_SDA, "ac14", NULL), | ||
1143 | _OMAP3_BALLENTRY(I2C3_SCL, "ac13", NULL), | ||
1144 | _OMAP3_BALLENTRY(I2C3_SDA, "ac12", NULL), | ||
1145 | _OMAP3_BALLENTRY(I2C4_SCL, "y16", NULL), | ||
1146 | _OMAP3_BALLENTRY(I2C4_SDA, "y15", NULL), | ||
1147 | _OMAP3_BALLENTRY(JTAG_EMU0, "ac24", NULL), | ||
1148 | _OMAP3_BALLENTRY(JTAG_EMU1, "ad24", NULL), | ||
1149 | _OMAP3_BALLENTRY(MCBSP1_CLKR, "w19", NULL), | ||
1150 | _OMAP3_BALLENTRY(MCBSP1_CLKX, "v18", NULL), | ||
1151 | _OMAP3_BALLENTRY(MCBSP1_DR, "y18", NULL), | ||
1152 | _OMAP3_BALLENTRY(MCBSP1_DX, "w18", NULL), | ||
1153 | _OMAP3_BALLENTRY(MCBSP1_FSR, "ab20", NULL), | ||
1154 | _OMAP3_BALLENTRY(MCBSP1_FSX, "aa19", NULL), | ||
1155 | _OMAP3_BALLENTRY(MCBSP2_CLKX, "t21", NULL), | ||
1156 | _OMAP3_BALLENTRY(MCBSP2_DR, "v19", NULL), | ||
1157 | _OMAP3_BALLENTRY(MCBSP2_DX, "r20", NULL), | ||
1158 | _OMAP3_BALLENTRY(MCBSP2_FSX, "v20", NULL), | ||
1159 | _OMAP3_BALLENTRY(MCBSP3_CLKX, "w4", NULL), | ||
1160 | _OMAP3_BALLENTRY(MCBSP3_DR, "v5", NULL), | ||
1161 | _OMAP3_BALLENTRY(MCBSP3_DX, "v6", NULL), | ||
1162 | _OMAP3_BALLENTRY(MCBSP3_FSX, "v4", NULL), | ||
1163 | _OMAP3_BALLENTRY(MCBSP_CLKS, "aa18", NULL), | ||
1164 | _OMAP3_BALLENTRY(MCSPI1_CLK, "t5", NULL), | ||
1165 | _OMAP3_BALLENTRY(MCSPI1_CS0, "t6", NULL), | ||
1166 | _OMAP3_BALLENTRY(MCSPI1_CS3, "r5", NULL), | ||
1167 | _OMAP3_BALLENTRY(MCSPI1_SIMO, "r4", NULL), | ||
1168 | _OMAP3_BALLENTRY(MCSPI1_SOMI, "t4", NULL), | ||
1169 | _OMAP3_BALLENTRY(MCSPI2_CLK, "n5", NULL), | ||
1170 | _OMAP3_BALLENTRY(MCSPI2_CS0, "m5", NULL), | ||
1171 | _OMAP3_BALLENTRY(MCSPI2_CS1, "m4", NULL), | ||
1172 | _OMAP3_BALLENTRY(MCSPI2_SIMO, "n4", NULL), | ||
1173 | _OMAP3_BALLENTRY(MCSPI2_SOMI, "n3", NULL), | ||
1174 | _OMAP3_BALLENTRY(SDMMC1_CLK, "m23", NULL), | ||
1175 | _OMAP3_BALLENTRY(SDMMC1_CMD, "l23", NULL), | ||
1176 | _OMAP3_BALLENTRY(SDMMC1_DAT0, "m22", NULL), | ||
1177 | _OMAP3_BALLENTRY(SDMMC1_DAT1, "m21", NULL), | ||
1178 | _OMAP3_BALLENTRY(SDMMC1_DAT2, "m20", NULL), | ||
1179 | _OMAP3_BALLENTRY(SDMMC1_DAT3, "n23", NULL), | ||
1180 | _OMAP3_BALLENTRY(SDMMC1_DAT4, "n22", NULL), | ||
1181 | _OMAP3_BALLENTRY(SDMMC1_DAT5, "n21", NULL), | ||
1182 | _OMAP3_BALLENTRY(SDMMC1_DAT6, "n20", NULL), | ||
1183 | _OMAP3_BALLENTRY(SDMMC1_DAT7, "p24", NULL), | ||
1184 | _OMAP3_BALLENTRY(SDMMC2_CLK, "y1", NULL), | ||
1185 | _OMAP3_BALLENTRY(SDMMC2_CMD, "ab5", NULL), | ||
1186 | _OMAP3_BALLENTRY(SDMMC2_DAT0, "ab3", NULL), | ||
1187 | _OMAP3_BALLENTRY(SDMMC2_DAT1, "y3", NULL), | ||
1188 | _OMAP3_BALLENTRY(SDMMC2_DAT2, "w3", NULL), | ||
1189 | _OMAP3_BALLENTRY(SDMMC2_DAT3, "v3", NULL), | ||
1190 | _OMAP3_BALLENTRY(SDMMC2_DAT4, "ab2", NULL), | ||
1191 | _OMAP3_BALLENTRY(SDMMC2_DAT5, "aa2", NULL), | ||
1192 | _OMAP3_BALLENTRY(SDMMC2_DAT6, "y2", NULL), | ||
1193 | _OMAP3_BALLENTRY(SDMMC2_DAT7, "aa1", NULL), | ||
1194 | _OMAP3_BALLENTRY(SYS_BOOT0, "ab12", NULL), | ||
1195 | _OMAP3_BALLENTRY(SYS_BOOT1, "ac16", NULL), | ||
1196 | _OMAP3_BALLENTRY(SYS_BOOT2, "ad17", NULL), | ||
1197 | _OMAP3_BALLENTRY(SYS_BOOT3, "ad18", NULL), | ||
1198 | _OMAP3_BALLENTRY(SYS_BOOT4, "ac17", NULL), | ||
1199 | _OMAP3_BALLENTRY(SYS_BOOT5, "ab16", NULL), | ||
1200 | _OMAP3_BALLENTRY(SYS_BOOT6, "aa15", NULL), | ||
1201 | _OMAP3_BALLENTRY(SYS_CLKOUT1, "y7", NULL), | ||
1202 | _OMAP3_BALLENTRY(SYS_CLKOUT2, "aa6", NULL), | ||
1203 | _OMAP3_BALLENTRY(SYS_CLKREQ, "y13", NULL), | ||
1204 | _OMAP3_BALLENTRY(SYS_NIRQ, "w16", NULL), | ||
1205 | _OMAP3_BALLENTRY(SYS_NRESWARM, "y10", NULL), | ||
1206 | _OMAP3_BALLENTRY(SYS_OFF_MODE, "ad23", NULL), | ||
1207 | _OMAP3_BALLENTRY(UART1_CTS, "ac2", NULL), | ||
1208 | _OMAP3_BALLENTRY(UART1_RTS, "w6", NULL), | ||
1209 | _OMAP3_BALLENTRY(UART1_RX, "v7", NULL), | ||
1210 | _OMAP3_BALLENTRY(UART1_TX, "w7", NULL), | ||
1211 | _OMAP3_BALLENTRY(UART3_CTS_RCTX, "a23", NULL), | ||
1212 | _OMAP3_BALLENTRY(UART3_RTS_SD, "b23", NULL), | ||
1213 | _OMAP3_BALLENTRY(UART3_RX_IRRX, "b24", NULL), | ||
1214 | _OMAP3_BALLENTRY(UART3_TX_IRTX, "c23", NULL), | ||
1215 | { .reg_offset = OMAP_MUX_TERMINATOR }, | ||
1216 | }; | ||
1217 | #else | ||
1218 | #define omap3_cus_ball NULL | ||
1219 | #endif | ||
1220 | |||
1221 | /* | ||
1222 | * Signals different on CBB package comapared to superset | ||
1223 | */ | ||
1224 | #if defined(CONFIG_OMAP_MUX) && defined(CONFIG_OMAP_PACKAGE_CBB) | ||
1225 | struct omap_mux __initdata omap3_cbb_subset[] = { | ||
1226 | _OMAP3_MUXENTRY(CAM_D10, 109, | ||
1227 | "cam_d10", NULL, NULL, NULL, | ||
1228 | "gpio_109", NULL, NULL, "safe_mode"), | ||
1229 | _OMAP3_MUXENTRY(CAM_D11, 110, | ||
1230 | "cam_d11", NULL, NULL, NULL, | ||
1231 | "gpio_110", NULL, NULL, "safe_mode"), | ||
1232 | _OMAP3_MUXENTRY(CAM_D2, 101, | ||
1233 | "cam_d2", NULL, NULL, NULL, | ||
1234 | "gpio_101", NULL, NULL, "safe_mode"), | ||
1235 | _OMAP3_MUXENTRY(CAM_D3, 102, | ||
1236 | "cam_d3", NULL, NULL, NULL, | ||
1237 | "gpio_102", NULL, NULL, "safe_mode"), | ||
1238 | _OMAP3_MUXENTRY(CAM_D4, 103, | ||
1239 | "cam_d4", NULL, NULL, NULL, | ||
1240 | "gpio_103", NULL, NULL, "safe_mode"), | ||
1241 | _OMAP3_MUXENTRY(CAM_D5, 104, | ||
1242 | "cam_d5", NULL, NULL, NULL, | ||
1243 | "gpio_104", NULL, NULL, "safe_mode"), | ||
1244 | _OMAP3_MUXENTRY(CAM_FLD, 98, | ||
1245 | "cam_fld", NULL, "cam_global_reset", NULL, | ||
1246 | "gpio_98", NULL, NULL, "safe_mode"), | ||
1247 | _OMAP3_MUXENTRY(CAM_HS, 94, | ||
1248 | "cam_hs", NULL, NULL, NULL, | ||
1249 | "gpio_94", NULL, NULL, "safe_mode"), | ||
1250 | _OMAP3_MUXENTRY(CAM_PCLK, 97, | ||
1251 | "cam_pclk", NULL, NULL, NULL, | ||
1252 | "gpio_97", NULL, NULL, "safe_mode"), | ||
1253 | _OMAP3_MUXENTRY(CAM_STROBE, 126, | ||
1254 | "cam_strobe", NULL, NULL, NULL, | ||
1255 | "gpio_126", NULL, NULL, "safe_mode"), | ||
1256 | _OMAP3_MUXENTRY(CAM_VS, 95, | ||
1257 | "cam_vs", NULL, NULL, NULL, | ||
1258 | "gpio_95", NULL, NULL, "safe_mode"), | ||
1259 | _OMAP3_MUXENTRY(CAM_WEN, 167, | ||
1260 | "cam_wen", NULL, "cam_shutter", NULL, | ||
1261 | "gpio_167", NULL, NULL, "safe_mode"), | ||
1262 | _OMAP3_MUXENTRY(DSS_DATA6, 76, | ||
1263 | "dss_data6", NULL, "uart1_tx", NULL, | ||
1264 | "gpio_76", NULL, NULL, "safe_mode"), | ||
1265 | _OMAP3_MUXENTRY(DSS_DATA7, 77, | ||
1266 | "dss_data7", NULL, "uart1_rx", NULL, | ||
1267 | "gpio_77", NULL, NULL, "safe_mode"), | ||
1268 | _OMAP3_MUXENTRY(DSS_DATA8, 78, | ||
1269 | "dss_data8", NULL, NULL, NULL, | ||
1270 | "gpio_78", NULL, NULL, "safe_mode"), | ||
1271 | _OMAP3_MUXENTRY(DSS_DATA9, 79, | ||
1272 | "dss_data9", NULL, NULL, NULL, | ||
1273 | "gpio_79", NULL, NULL, "safe_mode"), | ||
1274 | _OMAP3_MUXENTRY(DSS_HSYNC, 67, | ||
1275 | "dss_hsync", NULL, NULL, NULL, | ||
1276 | "gpio_67", NULL, NULL, "safe_mode"), | ||
1277 | _OMAP3_MUXENTRY(DSS_PCLK, 66, | ||
1278 | "dss_pclk", NULL, NULL, NULL, | ||
1279 | "gpio_66", NULL, NULL, "safe_mode"), | ||
1280 | _OMAP3_MUXENTRY(ETK_CLK, 12, | ||
1281 | "etk_clk", "mcbsp5_clkx", "sdmmc3_clk", "hsusb1_stp", | ||
1282 | "gpio_12", "mm1_rxdp", "hsusb1_tll_stp", NULL), | ||
1283 | _OMAP3_MUXENTRY(ETK_CTL, 13, | ||
1284 | "etk_ctl", NULL, "sdmmc3_cmd", "hsusb1_clk", | ||
1285 | "gpio_13", NULL, "hsusb1_tll_clk", NULL), | ||
1286 | _OMAP3_MUXENTRY(ETK_D0, 14, | ||
1287 | "etk_d0", "mcspi3_simo", "sdmmc3_dat4", "hsusb1_data0", | ||
1288 | "gpio_14", "mm1_rxrcv", "hsusb1_tll_data0", NULL), | ||
1289 | _OMAP3_MUXENTRY(ETK_D1, 15, | ||
1290 | "etk_d1", "mcspi3_somi", NULL, "hsusb1_data1", | ||
1291 | "gpio_15", "mm1_txse0", "hsusb1_tll_data1", NULL), | ||
1292 | _OMAP3_MUXENTRY(ETK_D10, 24, | ||
1293 | "etk_d10", NULL, "uart1_rx", "hsusb2_clk", | ||
1294 | "gpio_24", NULL, "hsusb2_tll_clk", NULL), | ||
1295 | _OMAP3_MUXENTRY(ETK_D11, 25, | ||
1296 | "etk_d11", NULL, NULL, "hsusb2_stp", | ||
1297 | "gpio_25", "mm2_rxdp", "hsusb2_tll_stp", NULL), | ||
1298 | _OMAP3_MUXENTRY(ETK_D12, 26, | ||
1299 | "etk_d12", NULL, NULL, "hsusb2_dir", | ||
1300 | "gpio_26", NULL, "hsusb2_tll_dir", NULL), | ||
1301 | _OMAP3_MUXENTRY(ETK_D13, 27, | ||
1302 | "etk_d13", NULL, NULL, "hsusb2_nxt", | ||
1303 | "gpio_27", "mm2_rxdm", "hsusb2_tll_nxt", NULL), | ||
1304 | _OMAP3_MUXENTRY(ETK_D14, 28, | ||
1305 | "etk_d14", NULL, NULL, "hsusb2_data0", | ||
1306 | "gpio_28", "mm2_rxrcv", "hsusb2_tll_data0", NULL), | ||
1307 | _OMAP3_MUXENTRY(ETK_D15, 29, | ||
1308 | "etk_d15", NULL, NULL, "hsusb2_data1", | ||
1309 | "gpio_29", "mm2_txse0", "hsusb2_tll_data1", NULL), | ||
1310 | _OMAP3_MUXENTRY(ETK_D2, 16, | ||
1311 | "etk_d2", "mcspi3_cs0", NULL, "hsusb1_data2", | ||
1312 | "gpio_16", "mm1_txdat", "hsusb1_tll_data2", NULL), | ||
1313 | _OMAP3_MUXENTRY(ETK_D3, 17, | ||
1314 | "etk_d3", "mcspi3_clk", "sdmmc3_dat3", "hsusb1_data7", | ||
1315 | "gpio_17", NULL, "hsusb1_tll_data7", NULL), | ||
1316 | _OMAP3_MUXENTRY(ETK_D4, 18, | ||
1317 | "etk_d4", "mcbsp5_dr", "sdmmc3_dat0", "hsusb1_data4", | ||
1318 | "gpio_18", NULL, "hsusb1_tll_data4", NULL), | ||
1319 | _OMAP3_MUXENTRY(ETK_D5, 19, | ||
1320 | "etk_d5", "mcbsp5_fsx", "sdmmc3_dat1", "hsusb1_data5", | ||
1321 | "gpio_19", NULL, "hsusb1_tll_data5", NULL), | ||
1322 | _OMAP3_MUXENTRY(ETK_D6, 20, | ||
1323 | "etk_d6", "mcbsp5_dx", "sdmmc3_dat2", "hsusb1_data6", | ||
1324 | "gpio_20", NULL, "hsusb1_tll_data6", NULL), | ||
1325 | _OMAP3_MUXENTRY(ETK_D7, 21, | ||
1326 | "etk_d7", "mcspi3_cs1", "sdmmc3_dat7", "hsusb1_data3", | ||
1327 | "gpio_21", "mm1_txen_n", "hsusb1_tll_data3", NULL), | ||
1328 | _OMAP3_MUXENTRY(ETK_D8, 22, | ||
1329 | "etk_d8", "sys_drm_msecure", "sdmmc3_dat6", "hsusb1_dir", | ||
1330 | "gpio_22", NULL, "hsusb1_tll_dir", NULL), | ||
1331 | _OMAP3_MUXENTRY(ETK_D9, 23, | ||
1332 | "etk_d9", "sys_secure_indicator", "sdmmc3_dat5", "hsusb1_nxt", | ||
1333 | "gpio_23", "mm1_rxdm", "hsusb1_tll_nxt", NULL), | ||
1334 | { .reg_offset = OMAP_MUX_TERMINATOR }, | ||
1335 | }; | ||
1336 | #else | ||
1337 | #define omap3_cbb_subset NULL | ||
1338 | #endif | ||
1339 | |||
1340 | /* | ||
1341 | * Balls for CBB package | ||
1342 | * 515-pin s-PBGA Package, 0.50mm Ball Pitch (Top), 0.40mm Ball Pitch (Bottom) | ||
1343 | */ | ||
1344 | #if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \ | ||
1345 | && defined(CONFIG_OMAP_PACKAGE_CBB) | ||
1346 | struct omap_ball __initdata omap3_cbb_ball[] = { | ||
1347 | _OMAP3_BALLENTRY(CAM_D0, "ag17", NULL), | ||
1348 | _OMAP3_BALLENTRY(CAM_D1, "ah17", NULL), | ||
1349 | _OMAP3_BALLENTRY(CAM_D10, "b25", NULL), | ||
1350 | _OMAP3_BALLENTRY(CAM_D11, "c26", NULL), | ||
1351 | _OMAP3_BALLENTRY(CAM_D2, "b24", NULL), | ||
1352 | _OMAP3_BALLENTRY(CAM_D3, "c24", NULL), | ||
1353 | _OMAP3_BALLENTRY(CAM_D4, "d24", NULL), | ||
1354 | _OMAP3_BALLENTRY(CAM_D5, "a25", NULL), | ||
1355 | _OMAP3_BALLENTRY(CAM_D6, "k28", NULL), | ||
1356 | _OMAP3_BALLENTRY(CAM_D7, "l28", NULL), | ||
1357 | _OMAP3_BALLENTRY(CAM_D8, "k27", NULL), | ||
1358 | _OMAP3_BALLENTRY(CAM_D9, "l27", NULL), | ||
1359 | _OMAP3_BALLENTRY(CAM_FLD, "c23", NULL), | ||
1360 | _OMAP3_BALLENTRY(CAM_HS, "a24", NULL), | ||
1361 | _OMAP3_BALLENTRY(CAM_PCLK, "c27", NULL), | ||
1362 | _OMAP3_BALLENTRY(CAM_STROBE, "d25", NULL), | ||
1363 | _OMAP3_BALLENTRY(CAM_VS, "a23", NULL), | ||
1364 | _OMAP3_BALLENTRY(CAM_WEN, "b23", NULL), | ||
1365 | _OMAP3_BALLENTRY(CAM_XCLKA, "c25", NULL), | ||
1366 | _OMAP3_BALLENTRY(CAM_XCLKB, "b26", NULL), | ||
1367 | _OMAP3_BALLENTRY(CSI2_DX0, "ag19", NULL), | ||
1368 | _OMAP3_BALLENTRY(CSI2_DX1, "ag18", NULL), | ||
1369 | _OMAP3_BALLENTRY(CSI2_DY0, "ah19", NULL), | ||
1370 | _OMAP3_BALLENTRY(CSI2_DY1, "ah18", NULL), | ||
1371 | _OMAP3_BALLENTRY(DSS_ACBIAS, "e27", NULL), | ||
1372 | _OMAP3_BALLENTRY(DSS_DATA0, "ag22", NULL), | ||
1373 | _OMAP3_BALLENTRY(DSS_DATA1, "ah22", NULL), | ||
1374 | _OMAP3_BALLENTRY(DSS_DATA10, "ad28", NULL), | ||
1375 | _OMAP3_BALLENTRY(DSS_DATA11, "ad27", NULL), | ||
1376 | _OMAP3_BALLENTRY(DSS_DATA12, "ab28", NULL), | ||
1377 | _OMAP3_BALLENTRY(DSS_DATA13, "ab27", NULL), | ||
1378 | _OMAP3_BALLENTRY(DSS_DATA14, "aa28", NULL), | ||
1379 | _OMAP3_BALLENTRY(DSS_DATA15, "aa27", NULL), | ||
1380 | _OMAP3_BALLENTRY(DSS_DATA16, "g25", NULL), | ||
1381 | _OMAP3_BALLENTRY(DSS_DATA17, "h27", NULL), | ||
1382 | _OMAP3_BALLENTRY(DSS_DATA18, "h26", NULL), | ||
1383 | _OMAP3_BALLENTRY(DSS_DATA19, "h25", NULL), | ||
1384 | _OMAP3_BALLENTRY(DSS_DATA2, "ag23", NULL), | ||
1385 | _OMAP3_BALLENTRY(DSS_DATA20, "e28", NULL), | ||
1386 | _OMAP3_BALLENTRY(DSS_DATA21, "j26", NULL), | ||
1387 | _OMAP3_BALLENTRY(DSS_DATA22, "ac27", NULL), | ||
1388 | _OMAP3_BALLENTRY(DSS_DATA23, "ac28", NULL), | ||
1389 | _OMAP3_BALLENTRY(DSS_DATA3, "ah23", NULL), | ||
1390 | _OMAP3_BALLENTRY(DSS_DATA4, "ag24", NULL), | ||
1391 | _OMAP3_BALLENTRY(DSS_DATA5, "ah24", NULL), | ||
1392 | _OMAP3_BALLENTRY(DSS_DATA6, "e26", NULL), | ||
1393 | _OMAP3_BALLENTRY(DSS_DATA7, "f28", NULL), | ||
1394 | _OMAP3_BALLENTRY(DSS_DATA8, "f27", NULL), | ||
1395 | _OMAP3_BALLENTRY(DSS_DATA9, "g26", NULL), | ||
1396 | _OMAP3_BALLENTRY(DSS_HSYNC, "d26", NULL), | ||
1397 | _OMAP3_BALLENTRY(DSS_PCLK, "d28", NULL), | ||
1398 | _OMAP3_BALLENTRY(DSS_VSYNC, "d27", NULL), | ||
1399 | _OMAP3_BALLENTRY(ETK_CLK, "af10", NULL), | ||
1400 | _OMAP3_BALLENTRY(ETK_CTL, "ae10", NULL), | ||
1401 | _OMAP3_BALLENTRY(ETK_D0, "af11", NULL), | ||
1402 | _OMAP3_BALLENTRY(ETK_D1, "ag12", NULL), | ||
1403 | _OMAP3_BALLENTRY(ETK_D10, "ae7", NULL), | ||
1404 | _OMAP3_BALLENTRY(ETK_D11, "af7", NULL), | ||
1405 | _OMAP3_BALLENTRY(ETK_D12, "ag7", NULL), | ||
1406 | _OMAP3_BALLENTRY(ETK_D13, "ah7", NULL), | ||
1407 | _OMAP3_BALLENTRY(ETK_D14, "ag8", NULL), | ||
1408 | _OMAP3_BALLENTRY(ETK_D15, "ah8", NULL), | ||
1409 | _OMAP3_BALLENTRY(ETK_D2, "ah12", NULL), | ||
1410 | _OMAP3_BALLENTRY(ETK_D3, "ae13", NULL), | ||
1411 | _OMAP3_BALLENTRY(ETK_D4, "ae11", NULL), | ||
1412 | _OMAP3_BALLENTRY(ETK_D5, "ah9", NULL), | ||
1413 | _OMAP3_BALLENTRY(ETK_D6, "af13", NULL), | ||
1414 | _OMAP3_BALLENTRY(ETK_D7, "ah14", NULL), | ||
1415 | _OMAP3_BALLENTRY(ETK_D8, "af9", NULL), | ||
1416 | _OMAP3_BALLENTRY(ETK_D9, "ag9", NULL), | ||
1417 | _OMAP3_BALLENTRY(GPMC_A1, "n4", "ac15"), | ||
1418 | _OMAP3_BALLENTRY(GPMC_A10, "k3", "ab19"), | ||
1419 | _OMAP3_BALLENTRY(GPMC_A2, "m4", "ab15"), | ||
1420 | _OMAP3_BALLENTRY(GPMC_A3, "l4", "ac16"), | ||
1421 | _OMAP3_BALLENTRY(GPMC_A4, "k4", "ab16"), | ||
1422 | _OMAP3_BALLENTRY(GPMC_A5, "t3", "ac17"), | ||
1423 | _OMAP3_BALLENTRY(GPMC_A6, "r3", "ab17"), | ||
1424 | _OMAP3_BALLENTRY(GPMC_A7, "n3", "ac18"), | ||
1425 | _OMAP3_BALLENTRY(GPMC_A8, "m3", "ab18"), | ||
1426 | _OMAP3_BALLENTRY(GPMC_A9, "l3", "ac19"), | ||
1427 | _OMAP3_BALLENTRY(GPMC_CLK, "t4", "w2"), | ||
1428 | _OMAP3_BALLENTRY(GPMC_D10, "p1", "ab4"), | ||
1429 | _OMAP3_BALLENTRY(GPMC_D11, "r1", "ac4"), | ||
1430 | _OMAP3_BALLENTRY(GPMC_D12, "r2", "ab6"), | ||
1431 | _OMAP3_BALLENTRY(GPMC_D13, "t2", "ac6"), | ||
1432 | _OMAP3_BALLENTRY(GPMC_D14, "w1", "ab7"), | ||
1433 | _OMAP3_BALLENTRY(GPMC_D15, "y1", "ac7"), | ||
1434 | _OMAP3_BALLENTRY(GPMC_D8, "h2", "ab3"), | ||
1435 | _OMAP3_BALLENTRY(GPMC_D9, "k2", "ac3"), | ||
1436 | _OMAP3_BALLENTRY(GPMC_NBE0_CLE, "g3", "ac12"), | ||
1437 | _OMAP3_BALLENTRY(GPMC_NBE1, "u3", NULL), | ||
1438 | _OMAP3_BALLENTRY(GPMC_NCS1, "h3", "y1"), | ||
1439 | _OMAP3_BALLENTRY(GPMC_NCS2, "v8", NULL), | ||
1440 | _OMAP3_BALLENTRY(GPMC_NCS3, "u8", NULL), | ||
1441 | _OMAP3_BALLENTRY(GPMC_NCS4, "t8", NULL), | ||
1442 | _OMAP3_BALLENTRY(GPMC_NCS5, "r8", NULL), | ||
1443 | _OMAP3_BALLENTRY(GPMC_NCS6, "p8", NULL), | ||
1444 | _OMAP3_BALLENTRY(GPMC_NCS7, "n8", NULL), | ||
1445 | _OMAP3_BALLENTRY(GPMC_NWP, "h1", "ab10"), | ||
1446 | _OMAP3_BALLENTRY(GPMC_WAIT1, "l8", "ac10"), | ||
1447 | _OMAP3_BALLENTRY(GPMC_WAIT2, "k8", NULL), | ||
1448 | _OMAP3_BALLENTRY(GPMC_WAIT3, "j8", NULL), | ||
1449 | _OMAP3_BALLENTRY(HDQ_SIO, "j25", NULL), | ||
1450 | _OMAP3_BALLENTRY(HSUSB0_CLK, "t28", NULL), | ||
1451 | _OMAP3_BALLENTRY(HSUSB0_DATA0, "t27", NULL), | ||
1452 | _OMAP3_BALLENTRY(HSUSB0_DATA1, "u28", NULL), | ||
1453 | _OMAP3_BALLENTRY(HSUSB0_DATA2, "u27", NULL), | ||
1454 | _OMAP3_BALLENTRY(HSUSB0_DATA3, "u26", NULL), | ||
1455 | _OMAP3_BALLENTRY(HSUSB0_DATA4, "u25", NULL), | ||
1456 | _OMAP3_BALLENTRY(HSUSB0_DATA5, "v28", NULL), | ||
1457 | _OMAP3_BALLENTRY(HSUSB0_DATA6, "v27", NULL), | ||
1458 | _OMAP3_BALLENTRY(HSUSB0_DATA7, "v26", NULL), | ||
1459 | _OMAP3_BALLENTRY(HSUSB0_DIR, "r28", NULL), | ||
1460 | _OMAP3_BALLENTRY(HSUSB0_NXT, "t26", NULL), | ||
1461 | _OMAP3_BALLENTRY(HSUSB0_STP, "t25", NULL), | ||
1462 | _OMAP3_BALLENTRY(I2C2_SCL, "af15", NULL), | ||
1463 | _OMAP3_BALLENTRY(I2C2_SDA, "ae15", NULL), | ||
1464 | _OMAP3_BALLENTRY(I2C3_SCL, "af14", NULL), | ||
1465 | _OMAP3_BALLENTRY(I2C3_SDA, "ag14", NULL), | ||
1466 | _OMAP3_BALLENTRY(I2C4_SCL, "ad26", NULL), | ||
1467 | _OMAP3_BALLENTRY(I2C4_SDA, "ae26", NULL), | ||
1468 | _OMAP3_BALLENTRY(JTAG_EMU0, "aa11", NULL), | ||
1469 | _OMAP3_BALLENTRY(JTAG_EMU1, "aa10", NULL), | ||
1470 | _OMAP3_BALLENTRY(MCBSP1_CLKR, "y21", NULL), | ||
1471 | _OMAP3_BALLENTRY(MCBSP1_CLKX, "w21", NULL), | ||
1472 | _OMAP3_BALLENTRY(MCBSP1_DR, "u21", NULL), | ||
1473 | _OMAP3_BALLENTRY(MCBSP1_DX, "v21", NULL), | ||
1474 | _OMAP3_BALLENTRY(MCBSP1_FSR, "aa21", NULL), | ||
1475 | _OMAP3_BALLENTRY(MCBSP1_FSX, "k26", NULL), | ||
1476 | _OMAP3_BALLENTRY(MCBSP2_CLKX, "n21", NULL), | ||
1477 | _OMAP3_BALLENTRY(MCBSP2_DR, "r21", NULL), | ||
1478 | _OMAP3_BALLENTRY(MCBSP2_DX, "m21", NULL), | ||
1479 | _OMAP3_BALLENTRY(MCBSP2_FSX, "p21", NULL), | ||
1480 | _OMAP3_BALLENTRY(MCBSP3_CLKX, "af5", NULL), | ||
1481 | _OMAP3_BALLENTRY(MCBSP3_DR, "ae6", NULL), | ||
1482 | _OMAP3_BALLENTRY(MCBSP3_DX, "af6", NULL), | ||
1483 | _OMAP3_BALLENTRY(MCBSP3_FSX, "ae5", NULL), | ||
1484 | _OMAP3_BALLENTRY(MCBSP4_CLKX, "ae1", NULL), | ||
1485 | _OMAP3_BALLENTRY(MCBSP4_DR, "ad1", NULL), | ||
1486 | _OMAP3_BALLENTRY(MCBSP4_DX, "ad2", NULL), | ||
1487 | _OMAP3_BALLENTRY(MCBSP4_FSX, "ac1", NULL), | ||
1488 | _OMAP3_BALLENTRY(MCBSP_CLKS, "t21", NULL), | ||
1489 | _OMAP3_BALLENTRY(MCSPI1_CLK, "ab3", NULL), | ||
1490 | _OMAP3_BALLENTRY(MCSPI1_CS0, "ac2", NULL), | ||
1491 | _OMAP3_BALLENTRY(MCSPI1_CS1, "ac3", NULL), | ||
1492 | _OMAP3_BALLENTRY(MCSPI1_CS2, "ab1", NULL), | ||
1493 | _OMAP3_BALLENTRY(MCSPI1_CS3, "ab2", NULL), | ||
1494 | _OMAP3_BALLENTRY(MCSPI1_SIMO, "ab4", NULL), | ||
1495 | _OMAP3_BALLENTRY(MCSPI1_SOMI, "aa4", NULL), | ||
1496 | _OMAP3_BALLENTRY(MCSPI2_CLK, "aa3", NULL), | ||
1497 | _OMAP3_BALLENTRY(MCSPI2_CS0, "y4", NULL), | ||
1498 | _OMAP3_BALLENTRY(MCSPI2_CS1, "v3", NULL), | ||
1499 | _OMAP3_BALLENTRY(MCSPI2_SIMO, "y2", NULL), | ||
1500 | _OMAP3_BALLENTRY(MCSPI2_SOMI, "y3", NULL), | ||
1501 | _OMAP3_BALLENTRY(SDMMC1_CLK, "n28", NULL), | ||
1502 | _OMAP3_BALLENTRY(SDMMC1_CMD, "m27", NULL), | ||
1503 | _OMAP3_BALLENTRY(SDMMC1_DAT0, "n27", NULL), | ||
1504 | _OMAP3_BALLENTRY(SDMMC1_DAT1, "n26", NULL), | ||
1505 | _OMAP3_BALLENTRY(SDMMC1_DAT2, "n25", NULL), | ||
1506 | _OMAP3_BALLENTRY(SDMMC1_DAT3, "p28", NULL), | ||
1507 | _OMAP3_BALLENTRY(SDMMC1_DAT4, "p27", NULL), | ||
1508 | _OMAP3_BALLENTRY(SDMMC1_DAT5, "p26", NULL), | ||
1509 | _OMAP3_BALLENTRY(SDMMC1_DAT6, "r27", NULL), | ||
1510 | _OMAP3_BALLENTRY(SDMMC1_DAT7, "r25", NULL), | ||
1511 | _OMAP3_BALLENTRY(SDMMC2_CLK, "ae2", NULL), | ||
1512 | _OMAP3_BALLENTRY(SDMMC2_CMD, "ag5", NULL), | ||
1513 | _OMAP3_BALLENTRY(SDMMC2_DAT0, "ah5", NULL), | ||
1514 | _OMAP3_BALLENTRY(SDMMC2_DAT1, "ah4", NULL), | ||
1515 | _OMAP3_BALLENTRY(SDMMC2_DAT2, "ag4", NULL), | ||
1516 | _OMAP3_BALLENTRY(SDMMC2_DAT3, "af4", NULL), | ||
1517 | _OMAP3_BALLENTRY(SDMMC2_DAT4, "ae4", NULL), | ||
1518 | _OMAP3_BALLENTRY(SDMMC2_DAT5, "ah3", NULL), | ||
1519 | _OMAP3_BALLENTRY(SDMMC2_DAT6, "af3", NULL), | ||
1520 | _OMAP3_BALLENTRY(SDMMC2_DAT7, "ae3", NULL), | ||
1521 | _OMAP3_BALLENTRY(SYS_BOOT0, "ah26", NULL), | ||
1522 | _OMAP3_BALLENTRY(SYS_BOOT1, "ag26", NULL), | ||
1523 | _OMAP3_BALLENTRY(SYS_BOOT2, "ae14", NULL), | ||
1524 | _OMAP3_BALLENTRY(SYS_BOOT3, "af18", NULL), | ||
1525 | _OMAP3_BALLENTRY(SYS_BOOT4, "af19", NULL), | ||
1526 | _OMAP3_BALLENTRY(SYS_BOOT5, "ae21", NULL), | ||
1527 | _OMAP3_BALLENTRY(SYS_BOOT6, "af21", NULL), | ||
1528 | _OMAP3_BALLENTRY(SYS_CLKOUT1, "ag25", NULL), | ||
1529 | _OMAP3_BALLENTRY(SYS_CLKOUT2, "ae22", NULL), | ||
1530 | _OMAP3_BALLENTRY(SYS_CLKREQ, "af25", NULL), | ||
1531 | _OMAP3_BALLENTRY(SYS_NIRQ, "af26", NULL), | ||
1532 | _OMAP3_BALLENTRY(SYS_NRESWARM, "af24", NULL), | ||
1533 | _OMAP3_BALLENTRY(SYS_OFF_MODE, "af22", NULL), | ||
1534 | _OMAP3_BALLENTRY(UART1_CTS, "w8", NULL), | ||
1535 | _OMAP3_BALLENTRY(UART1_RTS, "aa9", NULL), | ||
1536 | _OMAP3_BALLENTRY(UART1_RX, "y8", NULL), | ||
1537 | _OMAP3_BALLENTRY(UART1_TX, "aa8", NULL), | ||
1538 | _OMAP3_BALLENTRY(UART2_CTS, "ab26", NULL), | ||
1539 | _OMAP3_BALLENTRY(UART2_RTS, "ab25", NULL), | ||
1540 | _OMAP3_BALLENTRY(UART2_RX, "ad25", NULL), | ||
1541 | _OMAP3_BALLENTRY(UART2_TX, "aa25", NULL), | ||
1542 | _OMAP3_BALLENTRY(UART3_CTS_RCTX, "h18", NULL), | ||
1543 | _OMAP3_BALLENTRY(UART3_RTS_SD, "h19", NULL), | ||
1544 | _OMAP3_BALLENTRY(UART3_RX_IRRX, "h20", NULL), | ||
1545 | _OMAP3_BALLENTRY(UART3_TX_IRTX, "h21", NULL), | ||
1546 | { .reg_offset = OMAP_MUX_TERMINATOR }, | ||
1547 | }; | ||
1548 | #else | ||
1549 | #define omap3_cbb_ball NULL | ||
1550 | #endif | ||
1551 | |||
1552 | /* | ||
1553 | * Signals different on 36XX CBP package comapared to 34XX CBC package | ||
1554 | */ | ||
1555 | #if defined(CONFIG_OMAP_MUX) && defined(CONFIG_OMAP_PACKAGE_CBP) | ||
1556 | struct omap_mux __initdata omap36xx_cbp_subset[] = { | ||
1557 | _OMAP3_MUXENTRY(CAM_D0, 99, | ||
1558 | "cam_d0", NULL, "csi2_dx2", NULL, | ||
1559 | "gpio_99", NULL, NULL, "safe_mode"), | ||
1560 | _OMAP3_MUXENTRY(CAM_D1, 100, | ||
1561 | "cam_d1", NULL, "csi2_dy2", NULL, | ||
1562 | "gpio_100", NULL, NULL, "safe_mode"), | ||
1563 | _OMAP3_MUXENTRY(CAM_D10, 109, | ||
1564 | "cam_d10", "ssi2_wake", NULL, NULL, | ||
1565 | "gpio_109", "hw_dbg8", NULL, "safe_mode"), | ||
1566 | _OMAP3_MUXENTRY(CAM_D2, 101, | ||
1567 | "cam_d2", "ssi2_rdy_tx", NULL, NULL, | ||
1568 | "gpio_101", "hw_dbg4", NULL, "safe_mode"), | ||
1569 | _OMAP3_MUXENTRY(CAM_D3, 102, | ||
1570 | "cam_d3", "ssi2_dat_rx", NULL, NULL, | ||
1571 | "gpio_102", "hw_dbg5", NULL, "safe_mode"), | ||
1572 | _OMAP3_MUXENTRY(CAM_D4, 103, | ||
1573 | "cam_d4", "ssi2_flag_rx", NULL, NULL, | ||
1574 | "gpio_103", "hw_dbg6", NULL, "safe_mode"), | ||
1575 | _OMAP3_MUXENTRY(CAM_D5, 104, | ||
1576 | "cam_d5", "ssi2_rdy_rx", NULL, NULL, | ||
1577 | "gpio_104", "hw_dbg7", NULL, "safe_mode"), | ||
1578 | _OMAP3_MUXENTRY(CAM_HS, 94, | ||
1579 | "cam_hs", "ssi2_dat_tx", NULL, NULL, | ||
1580 | "gpio_94", "hw_dbg0", NULL, "safe_mode"), | ||
1581 | _OMAP3_MUXENTRY(CAM_VS, 95, | ||
1582 | "cam_vs", "ssi2_flag_tx", NULL, NULL, | ||
1583 | "gpio_95", "hw_dbg1", NULL, "safe_mode"), | ||
1584 | _OMAP3_MUXENTRY(DSS_DATA0, 70, | ||
1585 | "dss_data0", "dsi_dx0", "uart1_cts", NULL, | ||
1586 | "gpio_70", NULL, NULL, "safe_mode"), | ||
1587 | _OMAP3_MUXENTRY(DSS_DATA1, 71, | ||
1588 | "dss_data1", "dsi_dy0", "uart1_rts", NULL, | ||
1589 | "gpio_71", NULL, NULL, "safe_mode"), | ||
1590 | _OMAP3_MUXENTRY(DSS_DATA2, 72, | ||
1591 | "dss_data2", "dsi_dx1", NULL, NULL, | ||
1592 | "gpio_72", NULL, NULL, "safe_mode"), | ||
1593 | _OMAP3_MUXENTRY(DSS_DATA3, 73, | ||
1594 | "dss_data3", "dsi_dy1", NULL, NULL, | ||
1595 | "gpio_73", NULL, NULL, "safe_mode"), | ||
1596 | _OMAP3_MUXENTRY(DSS_DATA4, 74, | ||
1597 | "dss_data4", "dsi_dx2", "uart3_rx_irrx", NULL, | ||
1598 | "gpio_74", NULL, NULL, "safe_mode"), | ||
1599 | _OMAP3_MUXENTRY(DSS_DATA5, 75, | ||
1600 | "dss_data5", "dsi_dy2", "uart3_tx_irtx", NULL, | ||
1601 | "gpio_75", NULL, NULL, "safe_mode"), | ||
1602 | _OMAP3_MUXENTRY(DSS_DATA6, 76, | ||
1603 | "dss_data6", NULL, "uart1_tx", "dssvenc656_data6", | ||
1604 | "gpio_76", "hw_dbg14", NULL, "safe_mode"), | ||
1605 | _OMAP3_MUXENTRY(DSS_DATA7, 77, | ||
1606 | "dss_data7", NULL, "uart1_rx", "dssvenc656_data7", | ||
1607 | "gpio_77", "hw_dbg15", NULL, "safe_mode"), | ||
1608 | _OMAP3_MUXENTRY(DSS_DATA8, 78, | ||
1609 | "dss_data8", NULL, "uart3_rx_irrx", NULL, | ||
1610 | "gpio_78", "hw_dbg16", NULL, "safe_mode"), | ||
1611 | _OMAP3_MUXENTRY(DSS_DATA9, 79, | ||
1612 | "dss_data9", NULL, "uart3_tx_irtx", NULL, | ||
1613 | "gpio_79", "hw_dbg17", NULL, "safe_mode"), | ||
1614 | _OMAP3_MUXENTRY(ETK_D12, 26, | ||
1615 | "etk_d12", "sys_drm_msecure", NULL, "hsusb2_dir", | ||
1616 | "gpio_26", NULL, "hsusb2_tll_dir", "hw_dbg14"), | ||
1617 | _OMAP3_MUXENTRY(GPMC_A11, 0, | ||
1618 | "gpmc_a11", NULL, NULL, NULL, | ||
1619 | NULL, NULL, NULL, "safe_mode"), | ||
1620 | _OMAP3_MUXENTRY(GPMC_WAIT2, 64, | ||
1621 | "gpmc_wait2", NULL, "uart4_tx", NULL, | ||
1622 | "gpio_64", NULL, NULL, "safe_mode"), | ||
1623 | _OMAP3_MUXENTRY(GPMC_WAIT3, 65, | ||
1624 | "gpmc_wait3", "sys_ndmareq1", "uart4_rx", NULL, | ||
1625 | "gpio_65", NULL, NULL, "safe_mode"), | ||
1626 | _OMAP3_MUXENTRY(HSUSB0_DATA0, 125, | ||
1627 | "hsusb0_data0", NULL, "uart3_tx_irtx", NULL, | ||
1628 | "gpio_125", "uart2_tx", NULL, "safe_mode"), | ||
1629 | _OMAP3_MUXENTRY(HSUSB0_DATA1, 130, | ||
1630 | "hsusb0_data1", NULL, "uart3_rx_irrx", NULL, | ||
1631 | "gpio_130", "uart2_rx", NULL, "safe_mode"), | ||
1632 | _OMAP3_MUXENTRY(HSUSB0_DATA2, 131, | ||
1633 | "hsusb0_data2", NULL, "uart3_rts_sd", NULL, | ||
1634 | "gpio_131", "uart2_rts", NULL, "safe_mode"), | ||
1635 | _OMAP3_MUXENTRY(HSUSB0_DATA3, 169, | ||
1636 | "hsusb0_data3", NULL, "uart3_cts_rctx", NULL, | ||
1637 | "gpio_169", "uart2_cts", NULL, "safe_mode"), | ||
1638 | _OMAP3_MUXENTRY(MCBSP1_CLKR, 156, | ||
1639 | "mcbsp1_clkr", "mcspi4_clk", "sim_cd", NULL, | ||
1640 | "gpio_156", NULL, NULL, "safe_mode"), | ||
1641 | _OMAP3_MUXENTRY(MCBSP1_FSR, 157, | ||
1642 | "mcbsp1_fsr", "adpllv2d_dithering_en1", | ||
1643 | "cam_global_reset", NULL, | ||
1644 | "gpio_157", NULL, NULL, "safe_mode"), | ||
1645 | _OMAP3_MUXENTRY(MCBSP4_CLKX, 152, | ||
1646 | "mcbsp4_clkx", "ssi1_dat_rx", NULL, NULL, | ||
1647 | "gpio_152", "hsusb3_tll_data1", "mm3_txse0", "safe_mode"), | ||
1648 | _OMAP3_MUXENTRY(MCBSP4_DR, 153, | ||
1649 | "mcbsp4_dr", "ssi1_flag_rx", NULL, NULL, | ||
1650 | "gpio_153", "hsusb3_tll_data0", "mm3_rxrcv", "safe_mode"), | ||
1651 | _OMAP3_MUXENTRY(MCBSP4_DX, 154, | ||
1652 | "mcbsp4_dx", "ssi1_rdy_rx", NULL, NULL, | ||
1653 | "gpio_154", "hsusb3_tll_data2", "mm3_txdat", "safe_mode"), | ||
1654 | _OMAP3_MUXENTRY(MCBSP4_FSX, 155, | ||
1655 | "mcbsp4_fsx", "ssi1_wake", NULL, NULL, | ||
1656 | "gpio_155", "hsusb3_tll_data3", "mm3_txen_n", "safe_mode"), | ||
1657 | _OMAP3_MUXENTRY(MCSPI1_CS1, 175, | ||
1658 | "mcspi1_cs1", "adpllv2d_dithering_en2", NULL, "sdmmc3_cmd", | ||
1659 | "gpio_175", NULL, NULL, "safe_mode"), | ||
1660 | _OMAP3_MUXENTRY(SAD2D_MBUSFLAG, 0, | ||
1661 | "sad2d_mbusflag", "mad2d_sbusflag", NULL, NULL, | ||
1662 | NULL, NULL, NULL, NULL), | ||
1663 | _OMAP3_MUXENTRY(SAD2D_MCAD28, 0, | ||
1664 | "sad2d_mcad28", "mad2d_mcad28", NULL, NULL, | ||
1665 | NULL, NULL, NULL, NULL), | ||
1666 | _OMAP3_MUXENTRY(SAD2D_MCAD29, 0, | ||
1667 | "sad2d_mcad29", "mad2d_mcad29", NULL, NULL, | ||
1668 | NULL, NULL, NULL, NULL), | ||
1669 | _OMAP3_MUXENTRY(SAD2D_MCAD32, 0, | ||
1670 | "sad2d_mcad32", "mad2d_mcad32", NULL, NULL, | ||
1671 | NULL, NULL, NULL, NULL), | ||
1672 | _OMAP3_MUXENTRY(SAD2D_MCAD33, 0, | ||
1673 | "sad2d_mcad33", "mad2d_mcad33", NULL, NULL, | ||
1674 | NULL, NULL, NULL, NULL), | ||
1675 | _OMAP3_MUXENTRY(SAD2D_MCAD34, 0, | ||
1676 | "sad2d_mcad34", "mad2d_mcad34", NULL, NULL, | ||
1677 | NULL, NULL, NULL, NULL), | ||
1678 | _OMAP3_MUXENTRY(SAD2D_MCAD35, 0, | ||
1679 | "sad2d_mcad35", "mad2d_mcad35", NULL, NULL, | ||
1680 | NULL, NULL, NULL, NULL), | ||
1681 | _OMAP3_MUXENTRY(SAD2D_MCAD36, 0, | ||
1682 | "sad2d_mcad36", "mad2d_mcad36", NULL, NULL, | ||
1683 | NULL, NULL, NULL, NULL), | ||
1684 | _OMAP3_MUXENTRY(SAD2D_MREAD, 0, | ||
1685 | "sad2d_mread", "mad2d_sread", NULL, NULL, | ||
1686 | NULL, NULL, NULL, NULL), | ||
1687 | _OMAP3_MUXENTRY(SAD2D_MWRITE, 0, | ||
1688 | "sad2d_mwrite", "mad2d_swrite", NULL, NULL, | ||
1689 | NULL, NULL, NULL, NULL), | ||
1690 | _OMAP3_MUXENTRY(SAD2D_SBUSFLAG, 0, | ||
1691 | "sad2d_sbusflag", "mad2d_mbusflag", NULL, NULL, | ||
1692 | NULL, NULL, NULL, NULL), | ||
1693 | _OMAP3_MUXENTRY(SAD2D_SREAD, 0, | ||
1694 | "sad2d_sread", "mad2d_mread", NULL, NULL, | ||
1695 | NULL, NULL, NULL, NULL), | ||
1696 | _OMAP3_MUXENTRY(SAD2D_SWRITE, 0, | ||
1697 | "sad2d_swrite", "mad2d_mwrite", NULL, NULL, | ||
1698 | NULL, NULL, NULL, NULL), | ||
1699 | _OMAP3_MUXENTRY(SDMMC1_CLK, 120, | ||
1700 | "sdmmc1_clk", "ms_clk", NULL, NULL, | ||
1701 | "gpio_120", NULL, NULL, "safe_mode"), | ||
1702 | _OMAP3_MUXENTRY(SDMMC1_CMD, 121, | ||
1703 | "sdmmc1_cmd", "ms_bs", NULL, NULL, | ||
1704 | "gpio_121", NULL, NULL, "safe_mode"), | ||
1705 | _OMAP3_MUXENTRY(SDMMC1_DAT0, 122, | ||
1706 | "sdmmc1_dat0", "ms_dat0", NULL, NULL, | ||
1707 | "gpio_122", NULL, NULL, "safe_mode"), | ||
1708 | _OMAP3_MUXENTRY(SDMMC1_DAT1, 123, | ||
1709 | "sdmmc1_dat1", "ms_dat1", NULL, NULL, | ||
1710 | "gpio_123", NULL, NULL, "safe_mode"), | ||
1711 | _OMAP3_MUXENTRY(SDMMC1_DAT2, 124, | ||
1712 | "sdmmc1_dat2", "ms_dat2", NULL, NULL, | ||
1713 | "gpio_124", NULL, NULL, "safe_mode"), | ||
1714 | _OMAP3_MUXENTRY(SDMMC1_DAT3, 125, | ||
1715 | "sdmmc1_dat3", "ms_dat3", NULL, NULL, | ||
1716 | "gpio_125", NULL, NULL, "safe_mode"), | ||
1717 | _OMAP3_MUXENTRY(SDRC_CKE0, 0, | ||
1718 | "sdrc_cke0", NULL, NULL, NULL, | ||
1719 | NULL, NULL, NULL, "safe_mode_out1"), | ||
1720 | _OMAP3_MUXENTRY(SDRC_CKE1, 0, | ||
1721 | "sdrc_cke1", NULL, NULL, NULL, | ||
1722 | NULL, NULL, NULL, "safe_mode_out1"), | ||
1723 | _OMAP3_MUXENTRY(SIM_IO, 126, | ||
1724 | "sim_io", "sim_io_low_impedance", NULL, NULL, | ||
1725 | "gpio_126", NULL, NULL, "safe_mode"), | ||
1726 | _OMAP3_MUXENTRY(SIM_CLK, 127, | ||
1727 | "sim_clk", NULL, NULL, NULL, | ||
1728 | "gpio_127", NULL, NULL, "safe_mode"), | ||
1729 | _OMAP3_MUXENTRY(SIM_PWRCTRL, 128, | ||
1730 | "sim_pwrctrl", NULL, NULL, NULL, | ||
1731 | "gpio_128", NULL, NULL, "safe_mode"), | ||
1732 | _OMAP3_MUXENTRY(SIM_RST, 129, | ||
1733 | "sim_rst", NULL, NULL, NULL, | ||
1734 | "gpio_129", NULL, NULL, "safe_mode"), | ||
1735 | _OMAP3_MUXENTRY(SYS_BOOT0, 2, | ||
1736 | "sys_boot0", NULL, NULL, "dss_data18", | ||
1737 | "gpio_2", NULL, NULL, "safe_mode"), | ||
1738 | _OMAP3_MUXENTRY(SYS_BOOT1, 3, | ||
1739 | "sys_boot1", NULL, NULL, "dss_data19", | ||
1740 | "gpio_3", NULL, NULL, "safe_mode"), | ||
1741 | _OMAP3_MUXENTRY(SYS_BOOT3, 5, | ||
1742 | "sys_boot3", NULL, NULL, "dss_data20", | ||
1743 | "gpio_5", NULL, NULL, "safe_mode"), | ||
1744 | _OMAP3_MUXENTRY(SYS_BOOT4, 6, | ||
1745 | "sys_boot4", "sdmmc2_dir_dat2", NULL, "dss_data21", | ||
1746 | "gpio_6", NULL, NULL, "safe_mode"), | ||
1747 | _OMAP3_MUXENTRY(SYS_BOOT5, 7, | ||
1748 | "sys_boot5", "sdmmc2_dir_dat3", NULL, "dss_data22", | ||
1749 | "gpio_7", NULL, NULL, "safe_mode"), | ||
1750 | _OMAP3_MUXENTRY(SYS_BOOT6, 8, | ||
1751 | "sys_boot6", NULL, NULL, "dss_data23", | ||
1752 | "gpio_8", NULL, NULL, "safe_mode"), | ||
1753 | _OMAP3_MUXENTRY(UART1_CTS, 150, | ||
1754 | "uart1_cts", "ssi1_rdy_tx", NULL, NULL, | ||
1755 | "gpio_150", "hsusb3_tll_clk", NULL, "safe_mode"), | ||
1756 | _OMAP3_MUXENTRY(UART1_RTS, 149, | ||
1757 | "uart1_rts", "ssi1_flag_tx", NULL, NULL, | ||
1758 | "gpio_149", NULL, NULL, "safe_mode"), | ||
1759 | _OMAP3_MUXENTRY(UART1_TX, 148, | ||
1760 | "uart1_tx", "ssi1_dat_tx", NULL, NULL, | ||
1761 | "gpio_148", NULL, NULL, "safe_mode"), | ||
1762 | { .reg_offset = OMAP_MUX_TERMINATOR }, | ||
1763 | }; | ||
1764 | #else | ||
1765 | #define omap36xx_cbp_subset NULL | ||
1766 | #endif | ||
1767 | |||
1768 | /* | ||
1769 | * Balls for 36XX CBP package | ||
1770 | * 515-pin s-PBGA Package, 0.50mm Ball Pitch (Top), 0.40mm Ball Pitch (Bottom) | ||
1771 | */ | ||
1772 | #if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \ | ||
1773 | && defined (CONFIG_OMAP_PACKAGE_CBP) | ||
1774 | struct omap_ball __initdata omap36xx_cbp_ball[] = { | ||
1775 | _OMAP3_BALLENTRY(CAM_D0, "ag17", NULL), | ||
1776 | _OMAP3_BALLENTRY(CAM_D1, "ah17", NULL), | ||
1777 | _OMAP3_BALLENTRY(CAM_D10, "b25", NULL), | ||
1778 | _OMAP3_BALLENTRY(CAM_D11, "c26", NULL), | ||
1779 | _OMAP3_BALLENTRY(CAM_D2, "b24", NULL), | ||
1780 | _OMAP3_BALLENTRY(CAM_D3, "c24", NULL), | ||
1781 | _OMAP3_BALLENTRY(CAM_D4, "d24", NULL), | ||
1782 | _OMAP3_BALLENTRY(CAM_D5, "a25", NULL), | ||
1783 | _OMAP3_BALLENTRY(CAM_D6, "k28", NULL), | ||
1784 | _OMAP3_BALLENTRY(CAM_D7, "l28", NULL), | ||
1785 | _OMAP3_BALLENTRY(CAM_D8, "k27", NULL), | ||
1786 | _OMAP3_BALLENTRY(CAM_D9, "l27", NULL), | ||
1787 | _OMAP3_BALLENTRY(CAM_FLD, "c23", NULL), | ||
1788 | _OMAP3_BALLENTRY(CAM_HS, "a24", NULL), | ||
1789 | _OMAP3_BALLENTRY(CAM_PCLK, "c27", NULL), | ||
1790 | _OMAP3_BALLENTRY(CAM_STROBE, "d25", NULL), | ||
1791 | _OMAP3_BALLENTRY(CAM_VS, "a23", NULL), | ||
1792 | _OMAP3_BALLENTRY(CAM_WEN, "b23", NULL), | ||
1793 | _OMAP3_BALLENTRY(CAM_XCLKA, "c25", NULL), | ||
1794 | _OMAP3_BALLENTRY(CAM_XCLKB, "b26", NULL), | ||
1795 | _OMAP3_BALLENTRY(CSI2_DX0, "ag19", NULL), | ||
1796 | _OMAP3_BALLENTRY(CSI2_DX1, "ag18", NULL), | ||
1797 | _OMAP3_BALLENTRY(CSI2_DY0, "ah19", NULL), | ||
1798 | _OMAP3_BALLENTRY(CSI2_DY1, "ah18", NULL), | ||
1799 | _OMAP3_BALLENTRY(DSS_ACBIAS, "e27", NULL), | ||
1800 | _OMAP3_BALLENTRY(DSS_DATA0, "ag22", NULL), | ||
1801 | _OMAP3_BALLENTRY(DSS_DATA1, "ah22", NULL), | ||
1802 | _OMAP3_BALLENTRY(DSS_DATA10, "ad28", NULL), | ||
1803 | _OMAP3_BALLENTRY(DSS_DATA11, "ad27", NULL), | ||
1804 | _OMAP3_BALLENTRY(DSS_DATA12, "ab28", NULL), | ||
1805 | _OMAP3_BALLENTRY(DSS_DATA13, "ab27", NULL), | ||
1806 | _OMAP3_BALLENTRY(DSS_DATA14, "aa28", NULL), | ||
1807 | _OMAP3_BALLENTRY(DSS_DATA15, "aa27", NULL), | ||
1808 | _OMAP3_BALLENTRY(DSS_DATA16, "g25", NULL), | ||
1809 | _OMAP3_BALLENTRY(DSS_DATA17, "h27", NULL), | ||
1810 | _OMAP3_BALLENTRY(DSS_DATA18, "h26", NULL), | ||
1811 | _OMAP3_BALLENTRY(DSS_DATA19, "h25", NULL), | ||
1812 | _OMAP3_BALLENTRY(DSS_DATA2, "ag23", NULL), | ||
1813 | _OMAP3_BALLENTRY(DSS_DATA20, "e28", NULL), | ||
1814 | _OMAP3_BALLENTRY(DSS_DATA21, "j26", NULL), | ||
1815 | _OMAP3_BALLENTRY(DSS_DATA22, "ac27", NULL), | ||
1816 | _OMAP3_BALLENTRY(DSS_DATA23, "ac28", NULL), | ||
1817 | _OMAP3_BALLENTRY(DSS_DATA3, "ah23", NULL), | ||
1818 | _OMAP3_BALLENTRY(DSS_DATA4, "ag24", NULL), | ||
1819 | _OMAP3_BALLENTRY(DSS_DATA5, "ah24", NULL), | ||
1820 | _OMAP3_BALLENTRY(DSS_DATA6, "e26", NULL), | ||
1821 | _OMAP3_BALLENTRY(DSS_DATA7, "f28", NULL), | ||
1822 | _OMAP3_BALLENTRY(DSS_DATA8, "f27", NULL), | ||
1823 | _OMAP3_BALLENTRY(DSS_DATA9, "g26", NULL), | ||
1824 | _OMAP3_BALLENTRY(DSS_HSYNC, "d26", NULL), | ||
1825 | _OMAP3_BALLENTRY(DSS_PCLK, "d28", NULL), | ||
1826 | _OMAP3_BALLENTRY(DSS_VSYNC, "d27", NULL), | ||
1827 | _OMAP3_BALLENTRY(ETK_CLK, "af10", NULL), | ||
1828 | _OMAP3_BALLENTRY(ETK_CTL, "ae10", NULL), | ||
1829 | _OMAP3_BALLENTRY(ETK_D0, "af11", NULL), | ||
1830 | _OMAP3_BALLENTRY(ETK_D1, "ag12", NULL), | ||
1831 | _OMAP3_BALLENTRY(ETK_D10, "ae7", NULL), | ||
1832 | _OMAP3_BALLENTRY(ETK_D11, "af7", NULL), | ||
1833 | _OMAP3_BALLENTRY(ETK_D12, "ag7", NULL), | ||
1834 | _OMAP3_BALLENTRY(ETK_D13, "ah7", NULL), | ||
1835 | _OMAP3_BALLENTRY(ETK_D14, "ag8", NULL), | ||
1836 | _OMAP3_BALLENTRY(ETK_D15, "ah8", NULL), | ||
1837 | _OMAP3_BALLENTRY(ETK_D2, "ah12", NULL), | ||
1838 | _OMAP3_BALLENTRY(ETK_D3, "ae13", NULL), | ||
1839 | _OMAP3_BALLENTRY(ETK_D4, "ae11", NULL), | ||
1840 | _OMAP3_BALLENTRY(ETK_D5, "ah9", NULL), | ||
1841 | _OMAP3_BALLENTRY(ETK_D6, "af13", NULL), | ||
1842 | _OMAP3_BALLENTRY(ETK_D7, "ah14", NULL), | ||
1843 | _OMAP3_BALLENTRY(ETK_D8, "af9", NULL), | ||
1844 | _OMAP3_BALLENTRY(ETK_D9, "ag9", NULL), | ||
1845 | _OMAP3_BALLENTRY(GPMC_A1, "n4", "ac15"), | ||
1846 | _OMAP3_BALLENTRY(GPMC_A10, "k3", "ab19"), | ||
1847 | _OMAP3_BALLENTRY(GPMC_A11, NULL, "ac20"), | ||
1848 | _OMAP3_BALLENTRY(GPMC_A2, "m4", "ab15"), | ||
1849 | _OMAP3_BALLENTRY(GPMC_A3, "l4", "ac16"), | ||
1850 | _OMAP3_BALLENTRY(GPMC_A4, "k4", "ab16"), | ||
1851 | _OMAP3_BALLENTRY(GPMC_A5, "t3", "ac17"), | ||
1852 | _OMAP3_BALLENTRY(GPMC_A6, "r3", "ab17"), | ||
1853 | _OMAP3_BALLENTRY(GPMC_A7, "n3", "ac18"), | ||
1854 | _OMAP3_BALLENTRY(GPMC_A8, "m3", "ab18"), | ||
1855 | _OMAP3_BALLENTRY(GPMC_A9, "l3", "ac19"), | ||
1856 | _OMAP3_BALLENTRY(GPMC_CLK, "t4", "w2"), | ||
1857 | _OMAP3_BALLENTRY(GPMC_D0, "k1", "m2"), | ||
1858 | _OMAP3_BALLENTRY(GPMC_D1, "l1", "m1"), | ||
1859 | _OMAP3_BALLENTRY(GPMC_D10, "p1", "ab4"), | ||
1860 | _OMAP3_BALLENTRY(GPMC_D11, "r1", "ac4"), | ||
1861 | _OMAP3_BALLENTRY(GPMC_D12, "r2", "ab6"), | ||
1862 | _OMAP3_BALLENTRY(GPMC_D13, "t2", "ac6"), | ||
1863 | _OMAP3_BALLENTRY(GPMC_D14, "w1", "ab7"), | ||
1864 | _OMAP3_BALLENTRY(GPMC_D15, "y1", "ac7"), | ||
1865 | _OMAP3_BALLENTRY(GPMC_D2, "l2", "n2"), | ||
1866 | _OMAP3_BALLENTRY(GPMC_D3, "p2", "n1"), | ||
1867 | _OMAP3_BALLENTRY(GPMC_D4, "t1", "r2"), | ||
1868 | _OMAP3_BALLENTRY(GPMC_D5, "v1", "r1"), | ||
1869 | _OMAP3_BALLENTRY(GPMC_D6, "v2", "t2"), | ||
1870 | _OMAP3_BALLENTRY(GPMC_D7, "w2", "t1"), | ||
1871 | _OMAP3_BALLENTRY(GPMC_D8, "h2", "ab3"), | ||
1872 | _OMAP3_BALLENTRY(GPMC_D9, "k2", "ac3"), | ||
1873 | _OMAP3_BALLENTRY(GPMC_NADV_ALE, "f3", "w1"), | ||
1874 | _OMAP3_BALLENTRY(GPMC_NBE0_CLE, "g3", "ac12"), | ||
1875 | _OMAP3_BALLENTRY(GPMC_NBE1, "u3", NULL), | ||
1876 | _OMAP3_BALLENTRY(GPMC_NCS0, "g4", "y2"), | ||
1877 | _OMAP3_BALLENTRY(GPMC_NCS1, "h3", "y1"), | ||
1878 | _OMAP3_BALLENTRY(GPMC_NCS2, "v8", NULL), | ||
1879 | _OMAP3_BALLENTRY(GPMC_NCS3, "u8", NULL), | ||
1880 | _OMAP3_BALLENTRY(GPMC_NCS4, "t8", NULL), | ||
1881 | _OMAP3_BALLENTRY(GPMC_NCS5, "r8", NULL), | ||
1882 | _OMAP3_BALLENTRY(GPMC_NCS6, "p8", NULL), | ||
1883 | _OMAP3_BALLENTRY(GPMC_NCS7, "n8", NULL), | ||
1884 | _OMAP3_BALLENTRY(GPMC_NOE, "g2", "v2"), | ||
1885 | _OMAP3_BALLENTRY(GPMC_NWE, "f4", "v1"), | ||
1886 | _OMAP3_BALLENTRY(GPMC_NWP, "h1", "ab10"), | ||
1887 | _OMAP3_BALLENTRY(GPMC_WAIT0, "m8", "ab12"), | ||
1888 | _OMAP3_BALLENTRY(GPMC_WAIT1, "l8", "ac10"), | ||
1889 | _OMAP3_BALLENTRY(GPMC_WAIT2, "k8", NULL), | ||
1890 | _OMAP3_BALLENTRY(GPMC_WAIT3, "j8", NULL), | ||
1891 | _OMAP3_BALLENTRY(HDQ_SIO, "j25", NULL), | ||
1892 | _OMAP3_BALLENTRY(HSUSB0_CLK, "t28", NULL), | ||
1893 | _OMAP3_BALLENTRY(HSUSB0_DATA0, "t27", NULL), | ||
1894 | _OMAP3_BALLENTRY(HSUSB0_DATA1, "u28", NULL), | ||
1895 | _OMAP3_BALLENTRY(HSUSB0_DATA2, "u27", NULL), | ||
1896 | _OMAP3_BALLENTRY(HSUSB0_DATA3, "u26", NULL), | ||
1897 | _OMAP3_BALLENTRY(HSUSB0_DATA4, "u25", NULL), | ||
1898 | _OMAP3_BALLENTRY(HSUSB0_DATA5, "v28", NULL), | ||
1899 | _OMAP3_BALLENTRY(HSUSB0_DATA6, "v27", NULL), | ||
1900 | _OMAP3_BALLENTRY(HSUSB0_DATA7, "v26", NULL), | ||
1901 | _OMAP3_BALLENTRY(HSUSB0_DIR, "r28", NULL), | ||
1902 | _OMAP3_BALLENTRY(HSUSB0_NXT, "t26", NULL), | ||
1903 | _OMAP3_BALLENTRY(HSUSB0_STP, "t25", NULL), | ||
1904 | _OMAP3_BALLENTRY(I2C1_SCL, "k21", NULL), | ||
1905 | _OMAP3_BALLENTRY(I2C1_SDA, "j21", NULL), | ||
1906 | _OMAP3_BALLENTRY(I2C2_SCL, "af15", NULL), | ||
1907 | _OMAP3_BALLENTRY(I2C2_SDA, "ae15", NULL), | ||
1908 | _OMAP3_BALLENTRY(I2C3_SCL, "af14", NULL), | ||
1909 | _OMAP3_BALLENTRY(I2C3_SDA, "ag14", NULL), | ||
1910 | _OMAP3_BALLENTRY(I2C4_SCL, "ad26", NULL), | ||
1911 | _OMAP3_BALLENTRY(I2C4_SDA, "ae26", NULL), | ||
1912 | _OMAP3_BALLENTRY(JTAG_EMU0, "aa11", NULL), | ||
1913 | _OMAP3_BALLENTRY(JTAG_EMU1, "aa10", NULL), | ||
1914 | _OMAP3_BALLENTRY(JTAG_RTCK, "aa12", NULL), | ||
1915 | _OMAP3_BALLENTRY(JTAG_TCK, "aa13", NULL), | ||
1916 | _OMAP3_BALLENTRY(JTAG_TDI, "aa20", NULL), | ||
1917 | _OMAP3_BALLENTRY(JTAG_TDO, "aa19", NULL), | ||
1918 | _OMAP3_BALLENTRY(JTAG_TMS_TMSC, "aa18", NULL), | ||
1919 | _OMAP3_BALLENTRY(MCBSP1_CLKR, "y21", NULL), | ||
1920 | _OMAP3_BALLENTRY(MCBSP1_CLKX, "w21", NULL), | ||
1921 | _OMAP3_BALLENTRY(MCBSP1_DR, "u21", NULL), | ||
1922 | _OMAP3_BALLENTRY(MCBSP1_DX, "v21", NULL), | ||
1923 | _OMAP3_BALLENTRY(MCBSP1_FSR, "aa21", NULL), | ||
1924 | _OMAP3_BALLENTRY(MCBSP1_FSX, "k26", NULL), | ||
1925 | _OMAP3_BALLENTRY(MCBSP2_CLKX, "n21", NULL), | ||
1926 | _OMAP3_BALLENTRY(MCBSP2_DR, "r21", NULL), | ||
1927 | _OMAP3_BALLENTRY(MCBSP2_DX, "m21", NULL), | ||
1928 | _OMAP3_BALLENTRY(MCBSP2_FSX, "p21", NULL), | ||
1929 | _OMAP3_BALLENTRY(MCBSP3_CLKX, "af5", NULL), | ||
1930 | _OMAP3_BALLENTRY(MCBSP3_DR, "ae6", NULL), | ||
1931 | _OMAP3_BALLENTRY(MCBSP3_DX, "af6", NULL), | ||
1932 | _OMAP3_BALLENTRY(MCBSP3_FSX, "ae5", NULL), | ||
1933 | _OMAP3_BALLENTRY(MCBSP4_CLKX, "ae1", NULL), | ||
1934 | _OMAP3_BALLENTRY(MCBSP4_DR, "ad1", NULL), | ||
1935 | _OMAP3_BALLENTRY(MCBSP4_DX, "ad2", NULL), | ||
1936 | _OMAP3_BALLENTRY(MCBSP4_FSX, "ac1", NULL), | ||
1937 | _OMAP3_BALLENTRY(MCBSP_CLKS, "t21", NULL), | ||
1938 | _OMAP3_BALLENTRY(MCSPI1_CLK, "ab3", NULL), | ||
1939 | _OMAP3_BALLENTRY(MCSPI1_CS0, "ac2", NULL), | ||
1940 | _OMAP3_BALLENTRY(MCSPI1_CS1, "ac3", NULL), | ||
1941 | _OMAP3_BALLENTRY(MCSPI1_CS2, "ab1", NULL), | ||
1942 | _OMAP3_BALLENTRY(MCSPI1_CS3, "ab2", NULL), | ||
1943 | _OMAP3_BALLENTRY(MCSPI1_SIMO, "ab4", NULL), | ||
1944 | _OMAP3_BALLENTRY(MCSPI1_SOMI, "aa4", NULL), | ||
1945 | _OMAP3_BALLENTRY(MCSPI2_CLK, "aa3", NULL), | ||
1946 | _OMAP3_BALLENTRY(MCSPI2_CS0, "y4", NULL), | ||
1947 | _OMAP3_BALLENTRY(MCSPI2_CS1, "v3", NULL), | ||
1948 | _OMAP3_BALLENTRY(MCSPI2_SIMO, "y2", NULL), | ||
1949 | _OMAP3_BALLENTRY(MCSPI2_SOMI, "y3", NULL), | ||
1950 | _OMAP3_BALLENTRY(SDMMC1_CLK, "n28", NULL), | ||
1951 | _OMAP3_BALLENTRY(SDMMC1_CMD, "m27", NULL), | ||
1952 | _OMAP3_BALLENTRY(SDMMC1_DAT0, "n27", NULL), | ||
1953 | _OMAP3_BALLENTRY(SDMMC1_DAT1, "n26", NULL), | ||
1954 | _OMAP3_BALLENTRY(SDMMC1_DAT2, "n25", NULL), | ||
1955 | _OMAP3_BALLENTRY(SDMMC1_DAT3, "p28", NULL), | ||
1956 | _OMAP3_BALLENTRY(SDMMC2_CLK, "ae2", NULL), | ||
1957 | _OMAP3_BALLENTRY(SDMMC2_CMD, "ag5", NULL), | ||
1958 | _OMAP3_BALLENTRY(SDMMC2_DAT0, "ah5", NULL), | ||
1959 | _OMAP3_BALLENTRY(SDMMC2_DAT1, "ah4", NULL), | ||
1960 | _OMAP3_BALLENTRY(SDMMC2_DAT2, "ag4", NULL), | ||
1961 | _OMAP3_BALLENTRY(SDMMC2_DAT3, "af4", NULL), | ||
1962 | _OMAP3_BALLENTRY(SDMMC2_DAT4, "ae4", NULL), | ||
1963 | _OMAP3_BALLENTRY(SDMMC2_DAT5, "ah3", NULL), | ||
1964 | _OMAP3_BALLENTRY(SDMMC2_DAT6, "af3", NULL), | ||
1965 | _OMAP3_BALLENTRY(SDMMC2_DAT7, "ae3", NULL), | ||
1966 | _OMAP3_BALLENTRY(SDRC_A0, NULL, "n22"), | ||
1967 | _OMAP3_BALLENTRY(SDRC_A1, NULL, "n23"), | ||
1968 | _OMAP3_BALLENTRY(SDRC_A10, NULL, "v22"), | ||
1969 | _OMAP3_BALLENTRY(SDRC_A11, NULL, "v23"), | ||
1970 | _OMAP3_BALLENTRY(SDRC_A12, NULL, "w22"), | ||
1971 | _OMAP3_BALLENTRY(SDRC_A13, NULL, "w23"), | ||
1972 | _OMAP3_BALLENTRY(SDRC_A14, NULL, "y22"), | ||
1973 | _OMAP3_BALLENTRY(SDRC_A2, NULL, "p22"), | ||
1974 | _OMAP3_BALLENTRY(SDRC_A3, NULL, "p23"), | ||
1975 | _OMAP3_BALLENTRY(SDRC_A4, NULL, "r22"), | ||
1976 | _OMAP3_BALLENTRY(SDRC_A5, NULL, "r23"), | ||
1977 | _OMAP3_BALLENTRY(SDRC_A6, NULL, "t22"), | ||
1978 | _OMAP3_BALLENTRY(SDRC_A7, NULL, "t23"), | ||
1979 | _OMAP3_BALLENTRY(SDRC_A8, NULL, "u22"), | ||
1980 | _OMAP3_BALLENTRY(SDRC_A9, NULL, "u23"), | ||
1981 | _OMAP3_BALLENTRY(SDRC_BA0, "h9", "ab21"), | ||
1982 | _OMAP3_BALLENTRY(SDRC_BA1, "h10", "ac21"), | ||
1983 | _OMAP3_BALLENTRY(SDRC_CKE0, "h16", "j22"), | ||
1984 | _OMAP3_BALLENTRY(SDRC_CKE1, "h17", "j23"), | ||
1985 | _OMAP3_BALLENTRY(SDRC_CLK, "a13", "a11"), | ||
1986 | _OMAP3_BALLENTRY(SDRC_D0, NULL, "j2"), | ||
1987 | _OMAP3_BALLENTRY(SDRC_D1, NULL, "j1"), | ||
1988 | _OMAP3_BALLENTRY(SDRC_D10, "c15", "b14"), | ||
1989 | _OMAP3_BALLENTRY(SDRC_D11, "b16", "a14"), | ||
1990 | _OMAP3_BALLENTRY(SDRC_D12, "d17", "b16"), | ||
1991 | _OMAP3_BALLENTRY(SDRC_D13, "c17", "a16"), | ||
1992 | _OMAP3_BALLENTRY(SDRC_D14, "b17", "b19"), | ||
1993 | _OMAP3_BALLENTRY(SDRC_D15, "d18", "a19"), | ||
1994 | _OMAP3_BALLENTRY(SDRC_D16, NULL, "b3"), | ||
1995 | _OMAP3_BALLENTRY(SDRC_D17, NULL, "a3"), | ||
1996 | _OMAP3_BALLENTRY(SDRC_D18, NULL, "b5"), | ||
1997 | _OMAP3_BALLENTRY(SDRC_D19, NULL, "a5"), | ||
1998 | _OMAP3_BALLENTRY(SDRC_D2, NULL, "g2"), | ||
1999 | _OMAP3_BALLENTRY(SDRC_D20, NULL, "b8"), | ||
2000 | _OMAP3_BALLENTRY(SDRC_D21, NULL, "a8"), | ||
2001 | _OMAP3_BALLENTRY(SDRC_D22, NULL, "b9"), | ||
2002 | _OMAP3_BALLENTRY(SDRC_D23, NULL, "a9"), | ||
2003 | _OMAP3_BALLENTRY(SDRC_D24, NULL, "b21"), | ||
2004 | _OMAP3_BALLENTRY(SDRC_D25, NULL, "a21"), | ||
2005 | _OMAP3_BALLENTRY(SDRC_D26, NULL, "d22"), | ||
2006 | _OMAP3_BALLENTRY(SDRC_D27, NULL, "d23"), | ||
2007 | _OMAP3_BALLENTRY(SDRC_D28, NULL, "e22"), | ||
2008 | _OMAP3_BALLENTRY(SDRC_D29, NULL, "e23"), | ||
2009 | _OMAP3_BALLENTRY(SDRC_D3, NULL, "g1"), | ||
2010 | _OMAP3_BALLENTRY(SDRC_D30, NULL, "g22"), | ||
2011 | _OMAP3_BALLENTRY(SDRC_D31, NULL, "g23"), | ||
2012 | _OMAP3_BALLENTRY(SDRC_D4, NULL, "f2"), | ||
2013 | _OMAP3_BALLENTRY(SDRC_D5, NULL, "f1"), | ||
2014 | _OMAP3_BALLENTRY(SDRC_D6, NULL, "d2"), | ||
2015 | _OMAP3_BALLENTRY(SDRC_D7, NULL, "d1"), | ||
2016 | _OMAP3_BALLENTRY(SDRC_D8, "c14", "b13"), | ||
2017 | _OMAP3_BALLENTRY(SDRC_D9, "b14", "a13"), | ||
2018 | _OMAP3_BALLENTRY(SDRC_DM0, NULL, "c1"), | ||
2019 | _OMAP3_BALLENTRY(SDRC_DM1, "a16", "a17"), | ||
2020 | _OMAP3_BALLENTRY(SDRC_DM2, NULL, "a6"), | ||
2021 | _OMAP3_BALLENTRY(SDRC_DM3, NULL, "a20"), | ||
2022 | _OMAP3_BALLENTRY(SDRC_DQS0, NULL, "c2"), | ||
2023 | _OMAP3_BALLENTRY(SDRC_DQS1, "a17", "b17"), | ||
2024 | _OMAP3_BALLENTRY(SDRC_DQS2, NULL, "b6"), | ||
2025 | _OMAP3_BALLENTRY(SDRC_DQS3, NULL, "b20"), | ||
2026 | _OMAP3_BALLENTRY(SDRC_NCAS, "h13", "l22"), | ||
2027 | _OMAP3_BALLENTRY(SDRC_NCLK, "a14", "b11"), | ||
2028 | _OMAP3_BALLENTRY(SDRC_NCS0, "h11", "m22"), | ||
2029 | _OMAP3_BALLENTRY(SDRC_NCS1, "h12", "m23"), | ||
2030 | _OMAP3_BALLENTRY(SDRC_NRAS, "h14", "l23"), | ||
2031 | _OMAP3_BALLENTRY(SDRC_NWE, "h15", "k23"), | ||
2032 | _OMAP3_BALLENTRY(SIM_CLK, "p26", NULL), | ||
2033 | _OMAP3_BALLENTRY(SIM_IO, "p27", NULL), | ||
2034 | _OMAP3_BALLENTRY(SIM_PWRCTRL, "r27", NULL), | ||
2035 | _OMAP3_BALLENTRY(SIM_RST, "r25", NULL), | ||
2036 | _OMAP3_BALLENTRY(SYS_32K, "ae25", NULL), | ||
2037 | _OMAP3_BALLENTRY(SYS_BOOT0, "ah26", NULL), | ||
2038 | _OMAP3_BALLENTRY(SYS_BOOT1, "ag26", NULL), | ||
2039 | _OMAP3_BALLENTRY(SYS_BOOT2, "ae14", NULL), | ||
2040 | _OMAP3_BALLENTRY(SYS_BOOT3, "af18", NULL), | ||
2041 | _OMAP3_BALLENTRY(SYS_BOOT4, "af19", NULL), | ||
2042 | _OMAP3_BALLENTRY(SYS_BOOT5, "ae21", NULL), | ||
2043 | _OMAP3_BALLENTRY(SYS_BOOT6, "af21", NULL), | ||
2044 | _OMAP3_BALLENTRY(SYS_CLKOUT1, "ag25", NULL), | ||
2045 | _OMAP3_BALLENTRY(SYS_CLKOUT2, "ae22", NULL), | ||
2046 | _OMAP3_BALLENTRY(SYS_CLKREQ, "af25", NULL), | ||
2047 | _OMAP3_BALLENTRY(SYS_NIRQ, "af26", NULL), | ||
2048 | _OMAP3_BALLENTRY(SYS_NRESWARM, "af24", NULL), | ||
2049 | _OMAP3_BALLENTRY(SYS_OFF_MODE, "af22", NULL), | ||
2050 | _OMAP3_BALLENTRY(UART1_CTS, "w8", NULL), | ||
2051 | _OMAP3_BALLENTRY(UART1_RTS, "aa9", NULL), | ||
2052 | _OMAP3_BALLENTRY(UART1_RX, "y8", NULL), | ||
2053 | _OMAP3_BALLENTRY(UART1_TX, "aa8", NULL), | ||
2054 | _OMAP3_BALLENTRY(UART2_CTS, "ab26", NULL), | ||
2055 | _OMAP3_BALLENTRY(UART2_RTS, "ab25", NULL), | ||
2056 | _OMAP3_BALLENTRY(UART2_RX, "ad25", NULL), | ||
2057 | _OMAP3_BALLENTRY(UART2_TX, "aa25", NULL), | ||
2058 | _OMAP3_BALLENTRY(UART3_CTS_RCTX, "h18", NULL), | ||
2059 | _OMAP3_BALLENTRY(UART3_RTS_SD, "h19", NULL), | ||
2060 | _OMAP3_BALLENTRY(UART3_RX_IRRX, "h20", NULL), | ||
2061 | _OMAP3_BALLENTRY(UART3_TX_IRTX, "h21", NULL), | ||
2062 | { .reg_offset = OMAP_MUX_TERMINATOR }, | ||
2063 | }; | ||
2064 | #else | ||
2065 | #define omap36xx_cbp_ball NULL | ||
2066 | #endif | ||
2067 | |||
2068 | int __init omap3_mux_init(struct omap_board_mux *board_subset, int flags) | ||
2069 | { | ||
2070 | struct omap_mux *package_subset; | ||
2071 | struct omap_ball *package_balls; | ||
2072 | |||
2073 | switch (flags & OMAP_PACKAGE_MASK) { | ||
2074 | case (OMAP_PACKAGE_CBC): | ||
2075 | package_subset = omap3_cbc_subset; | ||
2076 | package_balls = omap3_cbc_ball; | ||
2077 | break; | ||
2078 | case (OMAP_PACKAGE_CBB): | ||
2079 | package_subset = omap3_cbb_subset; | ||
2080 | package_balls = omap3_cbb_ball; | ||
2081 | break; | ||
2082 | case (OMAP_PACKAGE_CUS): | ||
2083 | package_subset = omap3_cus_subset; | ||
2084 | package_balls = omap3_cus_ball; | ||
2085 | break; | ||
2086 | case (OMAP_PACKAGE_CBP): | ||
2087 | package_subset = omap36xx_cbp_subset; | ||
2088 | package_balls = omap36xx_cbp_ball; | ||
2089 | break; | ||
2090 | default: | ||
2091 | printk(KERN_ERR "mux: Unknown omap package, mux disabled\n"); | ||
2092 | return -EINVAL; | ||
2093 | } | ||
2094 | |||
2095 | return omap_mux_init(OMAP3_CONTROL_PADCONF_MUX_PBASE, | ||
2096 | OMAP3_CONTROL_PADCONF_MUX_SIZE, | ||
2097 | omap3_muxmodes, package_subset, board_subset, | ||
2098 | package_balls); | ||
2099 | } | ||
diff --git a/arch/arm/mach-omap2/mux34xx.h b/arch/arm/mach-omap2/mux34xx.h new file mode 100644 index 000000000000..6543ebf8ecfc --- /dev/null +++ b/arch/arm/mach-omap2/mux34xx.h | |||
@@ -0,0 +1,398 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2009 Nokia | ||
3 | * Copyright (C) 2009 Texas Instruments | ||
4 | * | ||
5 | * This program is free software; you can redistribute it and/or modify | ||
6 | * it under the terms of the GNU General Public License version 2 as | ||
7 | * published by the Free Software Foundation. | ||
8 | */ | ||
9 | |||
10 | #define OMAP3_CONTROL_PADCONF_MUX_PBASE 0x48002030LU | ||
11 | |||
12 | #define OMAP3_MUX(mode0, mux_value) \ | ||
13 | { \ | ||
14 | .reg_offset = (OMAP3_CONTROL_PADCONF_##mode0##_OFFSET), \ | ||
15 | .value = (mux_value), \ | ||
16 | } | ||
17 | |||
18 | /* | ||
19 | * OMAP3 CONTROL_PADCONF* register offsets for pin-muxing | ||
20 | * | ||
21 | * Extracted from the TRM. Add 0x48002030 to these values to get the | ||
22 | * absolute addresses. The name in the macro is the mode-0 name of | ||
23 | * the pin. NOTE: These registers are 16-bits wide. | ||
24 | * | ||
25 | * Note that 34XX TRM uses MMC instead of SDMMC and SAD2D instead | ||
26 | * of CHASSIS for some registers. For the defines, we follow the | ||
27 | * 36XX naming, and use SDMMC and CHASSIS. | ||
28 | */ | ||
29 | #define OMAP3_CONTROL_PADCONF_SDRC_D0_OFFSET 0x000 | ||
30 | #define OMAP3_CONTROL_PADCONF_SDRC_D1_OFFSET 0x002 | ||
31 | #define OMAP3_CONTROL_PADCONF_SDRC_D2_OFFSET 0x004 | ||
32 | #define OMAP3_CONTROL_PADCONF_SDRC_D3_OFFSET 0x006 | ||
33 | #define OMAP3_CONTROL_PADCONF_SDRC_D4_OFFSET 0x008 | ||
34 | #define OMAP3_CONTROL_PADCONF_SDRC_D5_OFFSET 0x00a | ||
35 | #define OMAP3_CONTROL_PADCONF_SDRC_D6_OFFSET 0x00c | ||
36 | #define OMAP3_CONTROL_PADCONF_SDRC_D7_OFFSET 0x00e | ||
37 | #define OMAP3_CONTROL_PADCONF_SDRC_D8_OFFSET 0x010 | ||
38 | #define OMAP3_CONTROL_PADCONF_SDRC_D9_OFFSET 0x012 | ||
39 | #define OMAP3_CONTROL_PADCONF_SDRC_D10_OFFSET 0x014 | ||
40 | #define OMAP3_CONTROL_PADCONF_SDRC_D11_OFFSET 0x016 | ||
41 | #define OMAP3_CONTROL_PADCONF_SDRC_D12_OFFSET 0x018 | ||
42 | #define OMAP3_CONTROL_PADCONF_SDRC_D13_OFFSET 0x01a | ||
43 | #define OMAP3_CONTROL_PADCONF_SDRC_D14_OFFSET 0x01c | ||
44 | #define OMAP3_CONTROL_PADCONF_SDRC_D15_OFFSET 0x01e | ||
45 | #define OMAP3_CONTROL_PADCONF_SDRC_D16_OFFSET 0x020 | ||
46 | #define OMAP3_CONTROL_PADCONF_SDRC_D17_OFFSET 0x022 | ||
47 | #define OMAP3_CONTROL_PADCONF_SDRC_D18_OFFSET 0x024 | ||
48 | #define OMAP3_CONTROL_PADCONF_SDRC_D19_OFFSET 0x026 | ||
49 | #define OMAP3_CONTROL_PADCONF_SDRC_D20_OFFSET 0x028 | ||
50 | #define OMAP3_CONTROL_PADCONF_SDRC_D21_OFFSET 0x02a | ||
51 | #define OMAP3_CONTROL_PADCONF_SDRC_D22_OFFSET 0x02c | ||
52 | #define OMAP3_CONTROL_PADCONF_SDRC_D23_OFFSET 0x02e | ||
53 | #define OMAP3_CONTROL_PADCONF_SDRC_D24_OFFSET 0x030 | ||
54 | #define OMAP3_CONTROL_PADCONF_SDRC_D25_OFFSET 0x032 | ||
55 | #define OMAP3_CONTROL_PADCONF_SDRC_D26_OFFSET 0x034 | ||
56 | #define OMAP3_CONTROL_PADCONF_SDRC_D27_OFFSET 0x036 | ||
57 | #define OMAP3_CONTROL_PADCONF_SDRC_D28_OFFSET 0x038 | ||
58 | #define OMAP3_CONTROL_PADCONF_SDRC_D29_OFFSET 0x03a | ||
59 | #define OMAP3_CONTROL_PADCONF_SDRC_D30_OFFSET 0x03c | ||
60 | #define OMAP3_CONTROL_PADCONF_SDRC_D31_OFFSET 0x03e | ||
61 | #define OMAP3_CONTROL_PADCONF_SDRC_CLK_OFFSET 0x040 | ||
62 | #define OMAP3_CONTROL_PADCONF_SDRC_DQS0_OFFSET 0x042 | ||
63 | #define OMAP3_CONTROL_PADCONF_SDRC_DQS1_OFFSET 0x044 | ||
64 | #define OMAP3_CONTROL_PADCONF_SDRC_DQS2_OFFSET 0x046 | ||
65 | #define OMAP3_CONTROL_PADCONF_SDRC_DQS3_OFFSET 0x048 | ||
66 | #define OMAP3_CONTROL_PADCONF_GPMC_A1_OFFSET 0x04a | ||
67 | #define OMAP3_CONTROL_PADCONF_GPMC_A2_OFFSET 0x04c | ||
68 | #define OMAP3_CONTROL_PADCONF_GPMC_A3_OFFSET 0x04e | ||
69 | #define OMAP3_CONTROL_PADCONF_GPMC_A4_OFFSET 0x050 | ||
70 | #define OMAP3_CONTROL_PADCONF_GPMC_A5_OFFSET 0x052 | ||
71 | #define OMAP3_CONTROL_PADCONF_GPMC_A6_OFFSET 0x054 | ||
72 | #define OMAP3_CONTROL_PADCONF_GPMC_A7_OFFSET 0x056 | ||
73 | #define OMAP3_CONTROL_PADCONF_GPMC_A8_OFFSET 0x058 | ||
74 | #define OMAP3_CONTROL_PADCONF_GPMC_A9_OFFSET 0x05a | ||
75 | #define OMAP3_CONTROL_PADCONF_GPMC_A10_OFFSET 0x05c | ||
76 | #define OMAP3_CONTROL_PADCONF_GPMC_D0_OFFSET 0x05e | ||
77 | #define OMAP3_CONTROL_PADCONF_GPMC_D1_OFFSET 0x060 | ||
78 | #define OMAP3_CONTROL_PADCONF_GPMC_D2_OFFSET 0x062 | ||
79 | #define OMAP3_CONTROL_PADCONF_GPMC_D3_OFFSET 0x064 | ||
80 | #define OMAP3_CONTROL_PADCONF_GPMC_D4_OFFSET 0x066 | ||
81 | #define OMAP3_CONTROL_PADCONF_GPMC_D5_OFFSET 0x068 | ||
82 | #define OMAP3_CONTROL_PADCONF_GPMC_D6_OFFSET 0x06a | ||
83 | #define OMAP3_CONTROL_PADCONF_GPMC_D7_OFFSET 0x06c | ||
84 | #define OMAP3_CONTROL_PADCONF_GPMC_D8_OFFSET 0x06e | ||
85 | #define OMAP3_CONTROL_PADCONF_GPMC_D9_OFFSET 0x070 | ||
86 | #define OMAP3_CONTROL_PADCONF_GPMC_D10_OFFSET 0x072 | ||
87 | #define OMAP3_CONTROL_PADCONF_GPMC_D11_OFFSET 0x074 | ||
88 | #define OMAP3_CONTROL_PADCONF_GPMC_D12_OFFSET 0x076 | ||
89 | #define OMAP3_CONTROL_PADCONF_GPMC_D13_OFFSET 0x078 | ||
90 | #define OMAP3_CONTROL_PADCONF_GPMC_D14_OFFSET 0x07a | ||
91 | #define OMAP3_CONTROL_PADCONF_GPMC_D15_OFFSET 0x07c | ||
92 | #define OMAP3_CONTROL_PADCONF_GPMC_NCS0_OFFSET 0x07e | ||
93 | #define OMAP3_CONTROL_PADCONF_GPMC_NCS1_OFFSET 0x080 | ||
94 | #define OMAP3_CONTROL_PADCONF_GPMC_NCS2_OFFSET 0x082 | ||
95 | #define OMAP3_CONTROL_PADCONF_GPMC_NCS3_OFFSET 0x084 | ||
96 | #define OMAP3_CONTROL_PADCONF_GPMC_NCS4_OFFSET 0x086 | ||
97 | #define OMAP3_CONTROL_PADCONF_GPMC_NCS5_OFFSET 0x088 | ||
98 | #define OMAP3_CONTROL_PADCONF_GPMC_NCS6_OFFSET 0x08a | ||
99 | #define OMAP3_CONTROL_PADCONF_GPMC_NCS7_OFFSET 0x08c | ||
100 | #define OMAP3_CONTROL_PADCONF_GPMC_CLK_OFFSET 0x08e | ||
101 | #define OMAP3_CONTROL_PADCONF_GPMC_NADV_ALE_OFFSET 0x090 | ||
102 | #define OMAP3_CONTROL_PADCONF_GPMC_NOE_OFFSET 0x092 | ||
103 | #define OMAP3_CONTROL_PADCONF_GPMC_NWE_OFFSET 0x094 | ||
104 | #define OMAP3_CONTROL_PADCONF_GPMC_NBE0_CLE_OFFSET 0x096 | ||
105 | #define OMAP3_CONTROL_PADCONF_GPMC_NBE1_OFFSET 0x098 | ||
106 | #define OMAP3_CONTROL_PADCONF_GPMC_NWP_OFFSET 0x09a | ||
107 | #define OMAP3_CONTROL_PADCONF_GPMC_WAIT0_OFFSET 0x09c | ||
108 | #define OMAP3_CONTROL_PADCONF_GPMC_WAIT1_OFFSET 0x09e | ||
109 | #define OMAP3_CONTROL_PADCONF_GPMC_WAIT2_OFFSET 0x0a0 | ||
110 | #define OMAP3_CONTROL_PADCONF_GPMC_WAIT3_OFFSET 0x0a2 | ||
111 | #define OMAP3_CONTROL_PADCONF_DSS_PCLK_OFFSET 0x0a4 | ||
112 | #define OMAP3_CONTROL_PADCONF_DSS_HSYNC_OFFSET 0x0a6 | ||
113 | #define OMAP3_CONTROL_PADCONF_DSS_VSYNC_OFFSET 0x0a8 | ||
114 | #define OMAP3_CONTROL_PADCONF_DSS_ACBIAS_OFFSET 0x0aa | ||
115 | #define OMAP3_CONTROL_PADCONF_DSS_DATA0_OFFSET 0x0ac | ||
116 | #define OMAP3_CONTROL_PADCONF_DSS_DATA1_OFFSET 0x0ae | ||
117 | #define OMAP3_CONTROL_PADCONF_DSS_DATA2_OFFSET 0x0b0 | ||
118 | #define OMAP3_CONTROL_PADCONF_DSS_DATA3_OFFSET 0x0b2 | ||
119 | #define OMAP3_CONTROL_PADCONF_DSS_DATA4_OFFSET 0x0b4 | ||
120 | #define OMAP3_CONTROL_PADCONF_DSS_DATA5_OFFSET 0x0b6 | ||
121 | #define OMAP3_CONTROL_PADCONF_DSS_DATA6_OFFSET 0x0b8 | ||
122 | #define OMAP3_CONTROL_PADCONF_DSS_DATA7_OFFSET 0x0ba | ||
123 | #define OMAP3_CONTROL_PADCONF_DSS_DATA8_OFFSET 0x0bc | ||
124 | #define OMAP3_CONTROL_PADCONF_DSS_DATA9_OFFSET 0x0be | ||
125 | #define OMAP3_CONTROL_PADCONF_DSS_DATA10_OFFSET 0x0c0 | ||
126 | #define OMAP3_CONTROL_PADCONF_DSS_DATA11_OFFSET 0x0c2 | ||
127 | #define OMAP3_CONTROL_PADCONF_DSS_DATA12_OFFSET 0x0c4 | ||
128 | #define OMAP3_CONTROL_PADCONF_DSS_DATA13_OFFSET 0x0c6 | ||
129 | #define OMAP3_CONTROL_PADCONF_DSS_DATA14_OFFSET 0x0c8 | ||
130 | #define OMAP3_CONTROL_PADCONF_DSS_DATA15_OFFSET 0x0ca | ||
131 | #define OMAP3_CONTROL_PADCONF_DSS_DATA16_OFFSET 0x0cc | ||
132 | #define OMAP3_CONTROL_PADCONF_DSS_DATA17_OFFSET 0x0ce | ||
133 | #define OMAP3_CONTROL_PADCONF_DSS_DATA18_OFFSET 0x0d0 | ||
134 | #define OMAP3_CONTROL_PADCONF_DSS_DATA19_OFFSET 0x0d2 | ||
135 | #define OMAP3_CONTROL_PADCONF_DSS_DATA20_OFFSET 0x0d4 | ||
136 | #define OMAP3_CONTROL_PADCONF_DSS_DATA21_OFFSET 0x0d6 | ||
137 | #define OMAP3_CONTROL_PADCONF_DSS_DATA22_OFFSET 0x0d8 | ||
138 | #define OMAP3_CONTROL_PADCONF_DSS_DATA23_OFFSET 0x0da | ||
139 | #define OMAP3_CONTROL_PADCONF_CAM_HS_OFFSET 0x0dc | ||
140 | #define OMAP3_CONTROL_PADCONF_CAM_VS_OFFSET 0x0de | ||
141 | #define OMAP3_CONTROL_PADCONF_CAM_XCLKA_OFFSET 0x0e0 | ||
142 | #define OMAP3_CONTROL_PADCONF_CAM_PCLK_OFFSET 0x0e2 | ||
143 | #define OMAP3_CONTROL_PADCONF_CAM_FLD_OFFSET 0x0e4 | ||
144 | #define OMAP3_CONTROL_PADCONF_CAM_D0_OFFSET 0x0e6 | ||
145 | #define OMAP3_CONTROL_PADCONF_CAM_D1_OFFSET 0x0e8 | ||
146 | #define OMAP3_CONTROL_PADCONF_CAM_D2_OFFSET 0x0ea | ||
147 | #define OMAP3_CONTROL_PADCONF_CAM_D3_OFFSET 0x0ec | ||
148 | #define OMAP3_CONTROL_PADCONF_CAM_D4_OFFSET 0x0ee | ||
149 | #define OMAP3_CONTROL_PADCONF_CAM_D5_OFFSET 0x0f0 | ||
150 | #define OMAP3_CONTROL_PADCONF_CAM_D6_OFFSET 0x0f2 | ||
151 | #define OMAP3_CONTROL_PADCONF_CAM_D7_OFFSET 0x0f4 | ||
152 | #define OMAP3_CONTROL_PADCONF_CAM_D8_OFFSET 0x0f6 | ||
153 | #define OMAP3_CONTROL_PADCONF_CAM_D9_OFFSET 0x0f8 | ||
154 | #define OMAP3_CONTROL_PADCONF_CAM_D10_OFFSET 0x0fa | ||
155 | #define OMAP3_CONTROL_PADCONF_CAM_D11_OFFSET 0x0fc | ||
156 | #define OMAP3_CONTROL_PADCONF_CAM_XCLKB_OFFSET 0x0fe | ||
157 | #define OMAP3_CONTROL_PADCONF_CAM_WEN_OFFSET 0x100 | ||
158 | #define OMAP3_CONTROL_PADCONF_CAM_STROBE_OFFSET 0x102 | ||
159 | #define OMAP3_CONTROL_PADCONF_CSI2_DX0_OFFSET 0x104 | ||
160 | #define OMAP3_CONTROL_PADCONF_CSI2_DY0_OFFSET 0x106 | ||
161 | #define OMAP3_CONTROL_PADCONF_CSI2_DX1_OFFSET 0x108 | ||
162 | #define OMAP3_CONTROL_PADCONF_CSI2_DY1_OFFSET 0x10a | ||
163 | #define OMAP3_CONTROL_PADCONF_MCBSP2_FSX_OFFSET 0x10c | ||
164 | #define OMAP3_CONTROL_PADCONF_MCBSP2_CLKX_OFFSET 0x10e | ||
165 | #define OMAP3_CONTROL_PADCONF_MCBSP2_DR_OFFSET 0x110 | ||
166 | #define OMAP3_CONTROL_PADCONF_MCBSP2_DX_OFFSET 0x112 | ||
167 | #define OMAP3_CONTROL_PADCONF_SDMMC1_CLK_OFFSET 0x114 | ||
168 | #define OMAP3_CONTROL_PADCONF_SDMMC1_CMD_OFFSET 0x116 | ||
169 | #define OMAP3_CONTROL_PADCONF_SDMMC1_DAT0_OFFSET 0x118 | ||
170 | #define OMAP3_CONTROL_PADCONF_SDMMC1_DAT1_OFFSET 0x11a | ||
171 | #define OMAP3_CONTROL_PADCONF_SDMMC1_DAT2_OFFSET 0x11c | ||
172 | #define OMAP3_CONTROL_PADCONF_SDMMC1_DAT3_OFFSET 0x11e | ||
173 | |||
174 | /* SDMMC1_DAT4 - DAT7 are SIM_IO SIM_CLK SIM_PWRCTRL and SIM_RST on 36xx */ | ||
175 | #define OMAP3_CONTROL_PADCONF_SDMMC1_DAT4_OFFSET 0x120 | ||
176 | #define OMAP3_CONTROL_PADCONF_SDMMC1_DAT5_OFFSET 0x122 | ||
177 | #define OMAP3_CONTROL_PADCONF_SDMMC1_DAT6_OFFSET 0x124 | ||
178 | #define OMAP3_CONTROL_PADCONF_SDMMC1_DAT7_OFFSET 0x126 | ||
179 | |||
180 | #define OMAP3_CONTROL_PADCONF_SDMMC2_CLK_OFFSET 0x128 | ||
181 | #define OMAP3_CONTROL_PADCONF_SDMMC2_CMD_OFFSET 0x12a | ||
182 | #define OMAP3_CONTROL_PADCONF_SDMMC2_DAT0_OFFSET 0x12c | ||
183 | #define OMAP3_CONTROL_PADCONF_SDMMC2_DAT1_OFFSET 0x12e | ||
184 | #define OMAP3_CONTROL_PADCONF_SDMMC2_DAT2_OFFSET 0x130 | ||
185 | #define OMAP3_CONTROL_PADCONF_SDMMC2_DAT3_OFFSET 0x132 | ||
186 | #define OMAP3_CONTROL_PADCONF_SDMMC2_DAT4_OFFSET 0x134 | ||
187 | #define OMAP3_CONTROL_PADCONF_SDMMC2_DAT5_OFFSET 0x136 | ||
188 | #define OMAP3_CONTROL_PADCONF_SDMMC2_DAT6_OFFSET 0x138 | ||
189 | #define OMAP3_CONTROL_PADCONF_SDMMC2_DAT7_OFFSET 0x13a | ||
190 | #define OMAP3_CONTROL_PADCONF_MCBSP3_DX_OFFSET 0x13c | ||
191 | #define OMAP3_CONTROL_PADCONF_MCBSP3_DR_OFFSET 0x13e | ||
192 | #define OMAP3_CONTROL_PADCONF_MCBSP3_CLKX_OFFSET 0x140 | ||
193 | #define OMAP3_CONTROL_PADCONF_MCBSP3_FSX_OFFSET 0x142 | ||
194 | #define OMAP3_CONTROL_PADCONF_UART2_CTS_OFFSET 0x144 | ||
195 | #define OMAP3_CONTROL_PADCONF_UART2_RTS_OFFSET 0x146 | ||
196 | #define OMAP3_CONTROL_PADCONF_UART2_TX_OFFSET 0x148 | ||
197 | #define OMAP3_CONTROL_PADCONF_UART2_RX_OFFSET 0x14a | ||
198 | #define OMAP3_CONTROL_PADCONF_UART1_TX_OFFSET 0x14c | ||
199 | #define OMAP3_CONTROL_PADCONF_UART1_RTS_OFFSET 0x14e | ||
200 | #define OMAP3_CONTROL_PADCONF_UART1_CTS_OFFSET 0x150 | ||
201 | #define OMAP3_CONTROL_PADCONF_UART1_RX_OFFSET 0x152 | ||
202 | #define OMAP3_CONTROL_PADCONF_MCBSP4_CLKX_OFFSET 0x154 | ||
203 | #define OMAP3_CONTROL_PADCONF_MCBSP4_DR_OFFSET 0x156 | ||
204 | #define OMAP3_CONTROL_PADCONF_MCBSP4_DX_OFFSET 0x158 | ||
205 | #define OMAP3_CONTROL_PADCONF_MCBSP4_FSX_OFFSET 0x15a | ||
206 | #define OMAP3_CONTROL_PADCONF_MCBSP1_CLKR_OFFSET 0x15c | ||
207 | #define OMAP3_CONTROL_PADCONF_MCBSP1_FSR_OFFSET 0x15e | ||
208 | #define OMAP3_CONTROL_PADCONF_MCBSP1_DX_OFFSET 0x160 | ||
209 | #define OMAP3_CONTROL_PADCONF_MCBSP1_DR_OFFSET 0x162 | ||
210 | #define OMAP3_CONTROL_PADCONF_MCBSP_CLKS_OFFSET 0x164 | ||
211 | #define OMAP3_CONTROL_PADCONF_MCBSP1_FSX_OFFSET 0x166 | ||
212 | #define OMAP3_CONTROL_PADCONF_MCBSP1_CLKX_OFFSET 0x168 | ||
213 | #define OMAP3_CONTROL_PADCONF_UART3_CTS_RCTX_OFFSET 0x16a | ||
214 | #define OMAP3_CONTROL_PADCONF_UART3_RTS_SD_OFFSET 0x16c | ||
215 | #define OMAP3_CONTROL_PADCONF_UART3_RX_IRRX_OFFSET 0x16e | ||
216 | #define OMAP3_CONTROL_PADCONF_UART3_TX_IRTX_OFFSET 0x170 | ||
217 | #define OMAP3_CONTROL_PADCONF_HSUSB0_CLK_OFFSET 0x172 | ||
218 | #define OMAP3_CONTROL_PADCONF_HSUSB0_STP_OFFSET 0x174 | ||
219 | #define OMAP3_CONTROL_PADCONF_HSUSB0_DIR_OFFSET 0x176 | ||
220 | #define OMAP3_CONTROL_PADCONF_HSUSB0_NXT_OFFSET 0x178 | ||
221 | #define OMAP3_CONTROL_PADCONF_HSUSB0_DATA0_OFFSET 0x17a | ||
222 | #define OMAP3_CONTROL_PADCONF_HSUSB0_DATA1_OFFSET 0x17c | ||
223 | #define OMAP3_CONTROL_PADCONF_HSUSB0_DATA2_OFFSET 0x17e | ||
224 | #define OMAP3_CONTROL_PADCONF_HSUSB0_DATA3_OFFSET 0x180 | ||
225 | #define OMAP3_CONTROL_PADCONF_HSUSB0_DATA4_OFFSET 0x182 | ||
226 | #define OMAP3_CONTROL_PADCONF_HSUSB0_DATA5_OFFSET 0x184 | ||
227 | #define OMAP3_CONTROL_PADCONF_HSUSB0_DATA6_OFFSET 0x186 | ||
228 | #define OMAP3_CONTROL_PADCONF_HSUSB0_DATA7_OFFSET 0x188 | ||
229 | #define OMAP3_CONTROL_PADCONF_I2C1_SCL_OFFSET 0x18a | ||
230 | #define OMAP3_CONTROL_PADCONF_I2C1_SDA_OFFSET 0x18c | ||
231 | #define OMAP3_CONTROL_PADCONF_I2C2_SCL_OFFSET 0x18e | ||
232 | #define OMAP3_CONTROL_PADCONF_I2C2_SDA_OFFSET 0x190 | ||
233 | #define OMAP3_CONTROL_PADCONF_I2C3_SCL_OFFSET 0x192 | ||
234 | #define OMAP3_CONTROL_PADCONF_I2C3_SDA_OFFSET 0x194 | ||
235 | #define OMAP3_CONTROL_PADCONF_HDQ_SIO_OFFSET 0x196 | ||
236 | #define OMAP3_CONTROL_PADCONF_MCSPI1_CLK_OFFSET 0x198 | ||
237 | #define OMAP3_CONTROL_PADCONF_MCSPI1_SIMO_OFFSET 0x19a | ||
238 | #define OMAP3_CONTROL_PADCONF_MCSPI1_SOMI_OFFSET 0x19c | ||
239 | #define OMAP3_CONTROL_PADCONF_MCSPI1_CS0_OFFSET 0x19e | ||
240 | #define OMAP3_CONTROL_PADCONF_MCSPI1_CS1_OFFSET 0x1a0 | ||
241 | #define OMAP3_CONTROL_PADCONF_MCSPI1_CS2_OFFSET 0x1a2 | ||
242 | #define OMAP3_CONTROL_PADCONF_MCSPI1_CS3_OFFSET 0x1a4 | ||
243 | #define OMAP3_CONTROL_PADCONF_MCSPI2_CLK_OFFSET 0x1a6 | ||
244 | #define OMAP3_CONTROL_PADCONF_MCSPI2_SIMO_OFFSET 0x1a8 | ||
245 | #define OMAP3_CONTROL_PADCONF_MCSPI2_SOMI_OFFSET 0x1aa | ||
246 | #define OMAP3_CONTROL_PADCONF_MCSPI2_CS0_OFFSET 0x1ac | ||
247 | #define OMAP3_CONTROL_PADCONF_MCSPI2_CS1_OFFSET 0x1ae | ||
248 | #define OMAP3_CONTROL_PADCONF_SYS_NIRQ_OFFSET 0x1b0 | ||
249 | #define OMAP3_CONTROL_PADCONF_SYS_CLKOUT2_OFFSET 0x1b2 | ||
250 | #define OMAP3_CONTROL_PADCONF_SAD2D_MCAD0_OFFSET 0x1b4 | ||
251 | #define OMAP3_CONTROL_PADCONF_SAD2D_MCAD1_OFFSET 0x1b6 | ||
252 | #define OMAP3_CONTROL_PADCONF_SAD2D_MCAD2_OFFSET 0x1b8 | ||
253 | #define OMAP3_CONTROL_PADCONF_SAD2D_MCAD3_OFFSET 0x1ba | ||
254 | #define OMAP3_CONTROL_PADCONF_SAD2D_MCAD4_OFFSET 0x1bc | ||
255 | #define OMAP3_CONTROL_PADCONF_SAD2D_MCAD5_OFFSET 0x1be | ||
256 | #define OMAP3_CONTROL_PADCONF_SAD2D_MCAD6_OFFSET 0x1c0 | ||
257 | #define OMAP3_CONTROL_PADCONF_SAD2D_MCAD7_OFFSET 0x1c2 | ||
258 | #define OMAP3_CONTROL_PADCONF_SAD2D_MCAD8_OFFSET 0x1c4 | ||
259 | #define OMAP3_CONTROL_PADCONF_SAD2D_MCAD9_OFFSET 0x1c6 | ||
260 | #define OMAP3_CONTROL_PADCONF_SAD2D_MCAD10_OFFSET 0x1c8 | ||
261 | #define OMAP3_CONTROL_PADCONF_SAD2D_MCAD11_OFFSET 0x1ca | ||
262 | #define OMAP3_CONTROL_PADCONF_SAD2D_MCAD12_OFFSET 0x1cc | ||
263 | #define OMAP3_CONTROL_PADCONF_SAD2D_MCAD13_OFFSET 0x1ce | ||
264 | #define OMAP3_CONTROL_PADCONF_SAD2D_MCAD14_OFFSET 0x1d0 | ||
265 | #define OMAP3_CONTROL_PADCONF_SAD2D_MCAD15_OFFSET 0x1d2 | ||
266 | #define OMAP3_CONTROL_PADCONF_SAD2D_MCAD16_OFFSET 0x1d4 | ||
267 | #define OMAP3_CONTROL_PADCONF_SAD2D_MCAD17_OFFSET 0x1d6 | ||
268 | #define OMAP3_CONTROL_PADCONF_SAD2D_MCAD18_OFFSET 0x1d8 | ||
269 | #define OMAP3_CONTROL_PADCONF_SAD2D_MCAD19_OFFSET 0x1da | ||
270 | #define OMAP3_CONTROL_PADCONF_SAD2D_MCAD20_OFFSET 0x1dc | ||
271 | #define OMAP3_CONTROL_PADCONF_SAD2D_MCAD21_OFFSET 0x1de | ||
272 | #define OMAP3_CONTROL_PADCONF_SAD2D_MCAD22_OFFSET 0x1e0 | ||
273 | #define OMAP3_CONTROL_PADCONF_SAD2D_MCAD23_OFFSET 0x1e2 | ||
274 | #define OMAP3_CONTROL_PADCONF_SAD2D_MCAD24_OFFSET 0x1e4 | ||
275 | #define OMAP3_CONTROL_PADCONF_SAD2D_MCAD25_OFFSET 0x1e6 | ||
276 | #define OMAP3_CONTROL_PADCONF_SAD2D_MCAD26_OFFSET 0x1e8 | ||
277 | #define OMAP3_CONTROL_PADCONF_SAD2D_MCAD27_OFFSET 0x1ea | ||
278 | #define OMAP3_CONTROL_PADCONF_SAD2D_MCAD28_OFFSET 0x1ec | ||
279 | #define OMAP3_CONTROL_PADCONF_SAD2D_MCAD29_OFFSET 0x1ee | ||
280 | #define OMAP3_CONTROL_PADCONF_SAD2D_MCAD30_OFFSET 0x1f0 | ||
281 | #define OMAP3_CONTROL_PADCONF_SAD2D_MCAD31_OFFSET 0x1f2 | ||
282 | #define OMAP3_CONTROL_PADCONF_SAD2D_MCAD32_OFFSET 0x1f4 | ||
283 | #define OMAP3_CONTROL_PADCONF_SAD2D_MCAD33_OFFSET 0x1f6 | ||
284 | #define OMAP3_CONTROL_PADCONF_SAD2D_MCAD34_OFFSET 0x1f8 | ||
285 | #define OMAP3_CONTROL_PADCONF_SAD2D_MCAD35_OFFSET 0x1fa | ||
286 | #define OMAP3_CONTROL_PADCONF_SAD2D_MCAD36_OFFSET 0x1fc | ||
287 | |||
288 | /* Note that 34xx TRM has SAD2D instead of CHASSIS for these */ | ||
289 | #define OMAP3_CONTROL_PADCONF_CHASSIS_CLK26MI_OFFSET 0x1fe | ||
290 | #define OMAP3_CONTROL_PADCONF_CHASSIS_NRESPWRON_OFFSET 0x200 | ||
291 | #define OMAP3_CONTROL_PADCONF_CHASSIS_NRESWARW_OFFSET 0x202 | ||
292 | #define OMAP3_CONTROL_PADCONF_CHASSIS_NIRQ_OFFSET 0x204 | ||
293 | #define OMAP3_CONTROL_PADCONF_CHASSIS_FIQ_OFFSET 0x206 | ||
294 | #define OMAP3_CONTROL_PADCONF_CHASSIS_ARMIRQ_OFFSET 0x208 | ||
295 | #define OMAP3_CONTROL_PADCONF_CHASSIS_IVAIRQ_OFFSET 0x20a | ||
296 | #define OMAP3_CONTROL_PADCONF_CHASSIS_DMAREQ0_OFFSET 0x20c | ||
297 | #define OMAP3_CONTROL_PADCONF_CHASSIS_DMAREQ1_OFFSET 0x20e | ||
298 | #define OMAP3_CONTROL_PADCONF_CHASSIS_DMAREQ2_OFFSET 0x210 | ||
299 | #define OMAP3_CONTROL_PADCONF_CHASSIS_DMAREQ3_OFFSET 0x212 | ||
300 | #define OMAP3_CONTROL_PADCONF_CHASSIS_NTRST_OFFSET 0x214 | ||
301 | #define OMAP3_CONTROL_PADCONF_CHASSIS_TDI_OFFSET 0x216 | ||
302 | #define OMAP3_CONTROL_PADCONF_CHASSIS_TDO_OFFSET 0x218 | ||
303 | #define OMAP3_CONTROL_PADCONF_CHASSIS_TMS_OFFSET 0x21a | ||
304 | #define OMAP3_CONTROL_PADCONF_CHASSIS_TCK_OFFSET 0x21c | ||
305 | #define OMAP3_CONTROL_PADCONF_CHASSIS_RTCK_OFFSET 0x21e | ||
306 | #define OMAP3_CONTROL_PADCONF_CHASSIS_MSTDBY_OFFSET 0x220 | ||
307 | #define OMAP3_CONTROL_PADCONF_CHASSIS_IDLEREQ_OFFSET 0x222 | ||
308 | #define OMAP3_CONTROL_PADCONF_CHASSIS_IDLEACK_OFFSET 0x224 | ||
309 | |||
310 | #define OMAP3_CONTROL_PADCONF_SAD2D_MWRITE_OFFSET 0x226 | ||
311 | #define OMAP3_CONTROL_PADCONF_SAD2D_SWRITE_OFFSET 0x228 | ||
312 | #define OMAP3_CONTROL_PADCONF_SAD2D_MREAD_OFFSET 0x22a | ||
313 | #define OMAP3_CONTROL_PADCONF_SAD2D_SREAD_OFFSET 0x22c | ||
314 | #define OMAP3_CONTROL_PADCONF_SAD2D_MBUSFLAG_OFFSET 0x22e | ||
315 | #define OMAP3_CONTROL_PADCONF_SAD2D_SBUSFLAG_OFFSET 0x230 | ||
316 | #define OMAP3_CONTROL_PADCONF_SDRC_CKE0_OFFSET 0x232 | ||
317 | #define OMAP3_CONTROL_PADCONF_SDRC_CKE1_OFFSET 0x234 | ||
318 | |||
319 | /* 36xx only */ | ||
320 | #define OMAP3_CONTROL_PADCONF_GPMC_A11_OFFSET 0x236 | ||
321 | #define OMAP3_CONTROL_PADCONF_SDRC_BA0_OFFSET 0x570 | ||
322 | #define OMAP3_CONTROL_PADCONF_SDRC_BA1_OFFSET 0x572 | ||
323 | #define OMAP3_CONTROL_PADCONF_SDRC_A0_OFFSET 0x574 | ||
324 | #define OMAP3_CONTROL_PADCONF_SDRC_A1_OFFSET 0x576 | ||
325 | #define OMAP3_CONTROL_PADCONF_SDRC_A2_OFFSET 0x578 | ||
326 | #define OMAP3_CONTROL_PADCONF_SDRC_A3_OFFSET 0x57a | ||
327 | #define OMAP3_CONTROL_PADCONF_SDRC_A4_OFFSET 0x57c | ||
328 | #define OMAP3_CONTROL_PADCONF_SDRC_A5_OFFSET 0x57e | ||
329 | #define OMAP3_CONTROL_PADCONF_SDRC_A6_OFFSET 0x580 | ||
330 | #define OMAP3_CONTROL_PADCONF_SDRC_A7_OFFSET 0x582 | ||
331 | #define OMAP3_CONTROL_PADCONF_SDRC_A8_OFFSET 0x584 | ||
332 | #define OMAP3_CONTROL_PADCONF_SDRC_A9_OFFSET 0x586 | ||
333 | #define OMAP3_CONTROL_PADCONF_SDRC_A10_OFFSET 0x588 | ||
334 | #define OMAP3_CONTROL_PADCONF_SDRC_A11_OFFSET 0x58a | ||
335 | #define OMAP3_CONTROL_PADCONF_SDRC_A12_OFFSET 0x58c | ||
336 | #define OMAP3_CONTROL_PADCONF_SDRC_A13_OFFSET 0x58e | ||
337 | #define OMAP3_CONTROL_PADCONF_SDRC_A14_OFFSET 0x590 | ||
338 | #define OMAP3_CONTROL_PADCONF_SDRC_NCS0_OFFSET 0x592 | ||
339 | #define OMAP3_CONTROL_PADCONF_SDRC_NCS1_OFFSET 0x594 | ||
340 | #define OMAP3_CONTROL_PADCONF_SDRC_NCLK_OFFSET 0x596 | ||
341 | #define OMAP3_CONTROL_PADCONF_SDRC_NRAS_OFFSET 0x598 | ||
342 | #define OMAP3_CONTROL_PADCONF_SDRC_NCAS_OFFSET 0x59a | ||
343 | #define OMAP3_CONTROL_PADCONF_SDRC_NWE_OFFSET 0x59c | ||
344 | #define OMAP3_CONTROL_PADCONF_SDRC_DM0_OFFSET 0x59e | ||
345 | #define OMAP3_CONTROL_PADCONF_SDRC_DM1_OFFSET 0x5a0 | ||
346 | #define OMAP3_CONTROL_PADCONF_SDRC_DM2_OFFSET 0x5a2 | ||
347 | #define OMAP3_CONTROL_PADCONF_SDRC_DM3_OFFSET 0x5a4 | ||
348 | |||
349 | /* 36xx only, these are SDMMC1_DAT4 - DAT7 on 34xx */ | ||
350 | #define OMAP3_CONTROL_PADCONF_SIM_IO_OFFSET 0x120 | ||
351 | #define OMAP3_CONTROL_PADCONF_SIM_CLK_OFFSET 0x122 | ||
352 | #define OMAP3_CONTROL_PADCONF_SIM_PWRCTRL_OFFSET 0x124 | ||
353 | #define OMAP3_CONTROL_PADCONF_SIM_RST_OFFSET 0x126 | ||
354 | |||
355 | #define OMAP3_CONTROL_PADCONF_ETK_CLK_OFFSET 0x5a8 | ||
356 | #define OMAP3_CONTROL_PADCONF_ETK_CTL_OFFSET 0x5aa | ||
357 | #define OMAP3_CONTROL_PADCONF_ETK_D0_OFFSET 0x5ac | ||
358 | #define OMAP3_CONTROL_PADCONF_ETK_D1_OFFSET 0x5ae | ||
359 | #define OMAP3_CONTROL_PADCONF_ETK_D2_OFFSET 0x5b0 | ||
360 | #define OMAP3_CONTROL_PADCONF_ETK_D3_OFFSET 0x5b2 | ||
361 | #define OMAP3_CONTROL_PADCONF_ETK_D4_OFFSET 0x5b4 | ||
362 | #define OMAP3_CONTROL_PADCONF_ETK_D5_OFFSET 0x5b6 | ||
363 | #define OMAP3_CONTROL_PADCONF_ETK_D6_OFFSET 0x5b8 | ||
364 | #define OMAP3_CONTROL_PADCONF_ETK_D7_OFFSET 0x5ba | ||
365 | #define OMAP3_CONTROL_PADCONF_ETK_D8_OFFSET 0x5bc | ||
366 | #define OMAP3_CONTROL_PADCONF_ETK_D9_OFFSET 0x5be | ||
367 | #define OMAP3_CONTROL_PADCONF_ETK_D10_OFFSET 0x5c0 | ||
368 | #define OMAP3_CONTROL_PADCONF_ETK_D11_OFFSET 0x5c2 | ||
369 | #define OMAP3_CONTROL_PADCONF_ETK_D12_OFFSET 0x5c4 | ||
370 | #define OMAP3_CONTROL_PADCONF_ETK_D13_OFFSET 0x5c6 | ||
371 | #define OMAP3_CONTROL_PADCONF_ETK_D14_OFFSET 0x5c8 | ||
372 | #define OMAP3_CONTROL_PADCONF_ETK_D15_OFFSET 0x5ca | ||
373 | #define OMAP3_CONTROL_PADCONF_I2C4_SCL_OFFSET 0x9d0 | ||
374 | #define OMAP3_CONTROL_PADCONF_I2C4_SDA_OFFSET 0x9d2 | ||
375 | #define OMAP3_CONTROL_PADCONF_SYS_32K_OFFSET 0x9d4 | ||
376 | #define OMAP3_CONTROL_PADCONF_SYS_CLKREQ_OFFSET 0x9d6 | ||
377 | #define OMAP3_CONTROL_PADCONF_SYS_NRESWARM_OFFSET 0x9d8 | ||
378 | #define OMAP3_CONTROL_PADCONF_SYS_BOOT0_OFFSET 0x9da | ||
379 | #define OMAP3_CONTROL_PADCONF_SYS_BOOT1_OFFSET 0x9dc | ||
380 | #define OMAP3_CONTROL_PADCONF_SYS_BOOT2_OFFSET 0x9de | ||
381 | #define OMAP3_CONTROL_PADCONF_SYS_BOOT3_OFFSET 0x9e0 | ||
382 | #define OMAP3_CONTROL_PADCONF_SYS_BOOT4_OFFSET 0x9e2 | ||
383 | #define OMAP3_CONTROL_PADCONF_SYS_BOOT5_OFFSET 0x9e4 | ||
384 | #define OMAP3_CONTROL_PADCONF_SYS_BOOT6_OFFSET 0x9e6 | ||
385 | #define OMAP3_CONTROL_PADCONF_SYS_OFF_MODE_OFFSET 0x9e8 | ||
386 | #define OMAP3_CONTROL_PADCONF_SYS_CLKOUT1_OFFSET 0x9ea | ||
387 | #define OMAP3_CONTROL_PADCONF_JTAG_NTRST_OFFSET 0x9ec | ||
388 | #define OMAP3_CONTROL_PADCONF_JTAG_TCK_OFFSET 0x9ee | ||
389 | #define OMAP3_CONTROL_PADCONF_JTAG_TMS_TMSC_OFFSET 0x9f0 | ||
390 | #define OMAP3_CONTROL_PADCONF_JTAG_TDI_OFFSET 0x9f2 | ||
391 | #define OMAP3_CONTROL_PADCONF_JTAG_EMU0_OFFSET 0x9f4 | ||
392 | #define OMAP3_CONTROL_PADCONF_JTAG_EMU1_OFFSET 0x9f6 | ||
393 | #define OMAP3_CONTROL_PADCONF_SAD2D_SWAKEUP_OFFSET 0xa1c | ||
394 | #define OMAP3_CONTROL_PADCONF_JTAG_RTCK_OFFSET 0xa1e | ||
395 | #define OMAP3_CONTROL_PADCONF_JTAG_TDO_OFFSET 0xa20 | ||
396 | |||
397 | #define OMAP3_CONTROL_PADCONF_MUX_SIZE \ | ||
398 | (OMAP3_CONTROL_PADCONF_JTAG_TDO_OFFSET + 0x2) | ||
diff --git a/arch/arm/mach-omap2/omap-headsmp.S b/arch/arm/mach-omap2/omap-headsmp.S index 4afadba09477..aa3f65c2ac97 100644 --- a/arch/arm/mach-omap2/omap-headsmp.S +++ b/arch/arm/mach-omap2/omap-headsmp.S | |||
@@ -27,20 +27,39 @@ | |||
27 | * OMAP4 specific entry point for secondary CPU to jump from ROM | 27 | * OMAP4 specific entry point for secondary CPU to jump from ROM |
28 | * code. This routine also provides a holding flag into which | 28 | * code. This routine also provides a holding flag into which |
29 | * secondary core is held until we're ready for it to initialise. | 29 | * secondary core is held until we're ready for it to initialise. |
30 | * The primary core will update the this flag using a hardware | 30 | * The primary core will update this flag using a hardware |
31 | * register AuxCoreBoot1. | 31 | * register AuxCoreBoot0. |
32 | */ | 32 | */ |
33 | ENTRY(omap_secondary_startup) | 33 | ENTRY(omap_secondary_startup) |
34 | mrc p15, 0, r0, c0, c0, 5 | 34 | hold: ldr r12,=0x103 |
35 | and r0, r0, #0x0f | 35 | dsb |
36 | hold: ldr r1, =OMAP4_AUX_CORE_BOOT1_PA @ read from AuxCoreBoot1 | 36 | smc @ read from AuxCoreBoot0 |
37 | ldr r2, [r1] | 37 | mov r0, r0, lsr #9 |
38 | cmp r2, r0 | 38 | mrc p15, 0, r4, c0, c0, 5 |
39 | and r4, r4, #0x0f | ||
40 | cmp r0, r4 | ||
39 | bne hold | 41 | bne hold |
40 | 42 | ||
41 | /* | 43 | /* |
42 | * we've been released from the cpu_release,secondary_stack | 44 | * we've been released from the wait loop,secondary_stack |
43 | * should now contain the SVC stack for this core | 45 | * should now contain the SVC stack for this core |
44 | */ | 46 | */ |
45 | b secondary_startup | 47 | b secondary_startup |
48 | END(omap_secondary_startup) | ||
46 | 49 | ||
50 | |||
51 | ENTRY(omap_modify_auxcoreboot0) | ||
52 | stmfd sp!, {r1-r12, lr} | ||
53 | ldr r12, =0x104 | ||
54 | dsb | ||
55 | smc | ||
56 | ldmfd sp!, {r1-r12, pc} | ||
57 | END(omap_modify_auxcoreboot0) | ||
58 | |||
59 | ENTRY(omap_auxcoreboot_addr) | ||
60 | stmfd sp!, {r2-r12, lr} | ||
61 | ldr r12, =0x105 | ||
62 | dsb | ||
63 | smc | ||
64 | ldmfd sp!, {r2-r12, pc} | ||
65 | END(omap_auxcoreboot_addr) | ||
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c index 4890bcf4dadd..38153e5fbca0 100644 --- a/arch/arm/mach-omap2/omap-smp.c +++ b/arch/arm/mach-omap2/omap-smp.c | |||
@@ -17,19 +17,15 @@ | |||
17 | */ | 17 | */ |
18 | #include <linux/init.h> | 18 | #include <linux/init.h> |
19 | #include <linux/device.h> | 19 | #include <linux/device.h> |
20 | #include <linux/jiffies.h> | ||
21 | #include <linux/smp.h> | 20 | #include <linux/smp.h> |
22 | #include <linux/io.h> | 21 | #include <linux/io.h> |
23 | 22 | ||
23 | #include <asm/cacheflush.h> | ||
24 | #include <asm/localtimer.h> | 24 | #include <asm/localtimer.h> |
25 | #include <asm/smp_scu.h> | 25 | #include <asm/smp_scu.h> |
26 | #include <mach/hardware.h> | 26 | #include <mach/hardware.h> |
27 | #include <plat/common.h> | 27 | #include <plat/common.h> |
28 | 28 | ||
29 | /* Registers used for communicating startup information */ | ||
30 | static void __iomem *omap4_auxcoreboot_reg0; | ||
31 | static void __iomem *omap4_auxcoreboot_reg1; | ||
32 | |||
33 | /* SCU base address */ | 29 | /* SCU base address */ |
34 | static void __iomem *scu_base; | 30 | static void __iomem *scu_base; |
35 | 31 | ||
@@ -65,8 +61,6 @@ void __cpuinit platform_secondary_init(unsigned int cpu) | |||
65 | 61 | ||
66 | int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) | 62 | int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) |
67 | { | 63 | { |
68 | unsigned long timeout; | ||
69 | |||
70 | /* | 64 | /* |
71 | * Set synchronisation state between this boot processor | 65 | * Set synchronisation state between this boot processor |
72 | * and the secondary one | 66 | * and the secondary one |
@@ -74,18 +68,15 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) | |||
74 | spin_lock(&boot_lock); | 68 | spin_lock(&boot_lock); |
75 | 69 | ||
76 | /* | 70 | /* |
77 | * Update the AuxCoreBoot1 with boot state for secondary core. | 71 | * Update the AuxCoreBoot0 with boot state for secondary core. |
78 | * omap_secondary_startup() routine will hold the secondary core till | 72 | * omap_secondary_startup() routine will hold the secondary core till |
79 | * the AuxCoreBoot1 register is updated with cpu state | 73 | * the AuxCoreBoot1 register is updated with cpu state |
80 | * A barrier is added to ensure that write buffer is drained | 74 | * A barrier is added to ensure that write buffer is drained |
81 | */ | 75 | */ |
82 | __raw_writel(cpu, omap4_auxcoreboot_reg1); | 76 | omap_modify_auxcoreboot0(0x200, 0x0); |
77 | flush_cache_all(); | ||
83 | smp_wmb(); | 78 | smp_wmb(); |
84 | 79 | ||
85 | timeout = jiffies + (1 * HZ); | ||
86 | while (time_before(jiffies, timeout)) | ||
87 | ; | ||
88 | |||
89 | /* | 80 | /* |
90 | * Now the secondary core is starting up let it run its | 81 | * Now the secondary core is starting up let it run its |
91 | * calibrations, then wait for it to finish | 82 | * calibrations, then wait for it to finish |
@@ -99,17 +90,18 @@ static void __init wakeup_secondary(void) | |||
99 | { | 90 | { |
100 | /* | 91 | /* |
101 | * Write the address of secondary startup routine into the | 92 | * Write the address of secondary startup routine into the |
102 | * AuxCoreBoot0 where ROM code will jump and start executing | 93 | * AuxCoreBoot1 where ROM code will jump and start executing |
103 | * on secondary core once out of WFE | 94 | * on secondary core once out of WFE |
104 | * A barrier is added to ensure that write buffer is drained | 95 | * A barrier is added to ensure that write buffer is drained |
105 | */ | 96 | */ |
106 | __raw_writel(virt_to_phys(omap_secondary_startup), \ | 97 | omap_auxcoreboot_addr(virt_to_phys(omap_secondary_startup)); |
107 | omap4_auxcoreboot_reg0); | ||
108 | smp_wmb(); | 98 | smp_wmb(); |
109 | 99 | ||
110 | /* | 100 | /* |
111 | * Send a 'sev' to wake the secondary core from WFE. | 101 | * Send a 'sev' to wake the secondary core from WFE. |
102 | * Drain the outstanding writes to memory | ||
112 | */ | 103 | */ |
104 | dsb(); | ||
113 | set_event(); | 105 | set_event(); |
114 | mb(); | 106 | mb(); |
115 | } | 107 | } |
@@ -136,7 +128,6 @@ void __init smp_prepare_cpus(unsigned int max_cpus) | |||
136 | { | 128 | { |
137 | unsigned int ncores = get_core_count(); | 129 | unsigned int ncores = get_core_count(); |
138 | unsigned int cpu = smp_processor_id(); | 130 | unsigned int cpu = smp_processor_id(); |
139 | void __iomem *omap4_wkupgen_base; | ||
140 | int i; | 131 | int i; |
141 | 132 | ||
142 | /* sanity check */ | 133 | /* sanity check */ |
@@ -168,12 +159,6 @@ void __init smp_prepare_cpus(unsigned int max_cpus) | |||
168 | for (i = 0; i < max_cpus; i++) | 159 | for (i = 0; i < max_cpus; i++) |
169 | set_cpu_present(i, true); | 160 | set_cpu_present(i, true); |
170 | 161 | ||
171 | /* Never released */ | ||
172 | omap4_wkupgen_base = ioremap(OMAP44XX_WKUPGEN_BASE, SZ_4K); | ||
173 | BUG_ON(!omap4_wkupgen_base); | ||
174 | omap4_auxcoreboot_reg0 = omap4_wkupgen_base + 0x800; | ||
175 | omap4_auxcoreboot_reg1 = omap4_wkupgen_base + 0x804; | ||
176 | |||
177 | if (max_cpus > 1) { | 162 | if (max_cpus > 1) { |
178 | /* | 163 | /* |
179 | * Enable the local timer or broadcast device for the | 164 | * Enable the local timer or broadcast device for the |
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 633b216a8b26..d8c8545875b1 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c | |||
@@ -45,6 +45,7 @@ | |||
45 | #include <linux/mutex.h> | 45 | #include <linux/mutex.h> |
46 | #include <linux/bootmem.h> | 46 | #include <linux/bootmem.h> |
47 | 47 | ||
48 | #include <plat/common.h> | ||
48 | #include <plat/cpu.h> | 49 | #include <plat/cpu.h> |
49 | #include <plat/clockdomain.h> | 50 | #include <plat/clockdomain.h> |
50 | #include <plat/powerdomain.h> | 51 | #include <plat/powerdomain.h> |
@@ -210,6 +211,32 @@ static int _set_softreset(struct omap_hwmod *oh, u32 *v) | |||
210 | } | 211 | } |
211 | 212 | ||
212 | /** | 213 | /** |
214 | * _set_module_autoidle: set the OCP_SYSCONFIG AUTOIDLE field in @v | ||
215 | * @oh: struct omap_hwmod * | ||
216 | * @autoidle: desired AUTOIDLE bitfield value (0 or 1) | ||
217 | * @v: pointer to register contents to modify | ||
218 | * | ||
219 | * Update the module autoidle bit in @v to be @autoidle for the @oh | ||
220 | * hwmod. The autoidle bit controls whether the module can gate | ||
221 | * internal clocks automatically when it isn't doing anything; the | ||
222 | * exact function of this bit varies on a per-module basis. This | ||
223 | * function does not write to the hardware. Returns -EINVAL upon | ||
224 | * error or 0 upon success. | ||
225 | */ | ||
226 | static int _set_module_autoidle(struct omap_hwmod *oh, u8 autoidle, | ||
227 | u32 *v) | ||
228 | { | ||
229 | if (!oh->sysconfig || | ||
230 | !(oh->sysconfig->sysc_flags & SYSC_HAS_AUTOIDLE)) | ||
231 | return -EINVAL; | ||
232 | |||
233 | *v &= ~SYSC_AUTOIDLE_MASK; | ||
234 | *v |= autoidle << SYSC_AUTOIDLE_SHIFT; | ||
235 | |||
236 | return 0; | ||
237 | } | ||
238 | |||
239 | /** | ||
213 | * _enable_wakeup: set OCP_SYSCONFIG.ENAWAKEUP bit in the hardware | 240 | * _enable_wakeup: set OCP_SYSCONFIG.ENAWAKEUP bit in the hardware |
214 | * @oh: struct omap_hwmod * | 241 | * @oh: struct omap_hwmod * |
215 | * | 242 | * |
@@ -326,6 +353,9 @@ static int _init_main_clk(struct omap_hwmod *oh) | |||
326 | ret = -EINVAL; | 353 | ret = -EINVAL; |
327 | oh->_clk = c; | 354 | oh->_clk = c; |
328 | 355 | ||
356 | WARN(!c->clkdm, "omap_hwmod: %s: missing clockdomain for %s.\n", | ||
357 | oh->clkdev_con_id, c->name); | ||
358 | |||
329 | return ret; | 359 | return ret; |
330 | } | 360 | } |
331 | 361 | ||
@@ -557,8 +587,19 @@ static void _sysc_enable(struct omap_hwmod *oh) | |||
557 | _set_master_standbymode(oh, idlemode, &v); | 587 | _set_master_standbymode(oh, idlemode, &v); |
558 | } | 588 | } |
559 | 589 | ||
560 | /* XXX OCP AUTOIDLE bit? */ | 590 | if (oh->sysconfig->sysc_flags & SYSC_HAS_AUTOIDLE) { |
591 | idlemode = (oh->flags & HWMOD_NO_OCP_AUTOIDLE) ? | ||
592 | 0 : 1; | ||
593 | _set_module_autoidle(oh, idlemode, &v); | ||
594 | } | ||
595 | |||
596 | /* XXX OCP ENAWAKEUP bit? */ | ||
561 | 597 | ||
598 | /* | ||
599 | * XXX The clock framework should handle this, by | ||
600 | * calling into this code. But this must wait until the | ||
601 | * clock structures are tagged with omap_hwmod entries | ||
602 | */ | ||
562 | if (oh->flags & HWMOD_SET_DEFAULT_CLOCKACT && | 603 | if (oh->flags & HWMOD_SET_DEFAULT_CLOCKACT && |
563 | oh->sysconfig->sysc_flags & SYSC_HAS_CLOCKACTIVITY) | 604 | oh->sysconfig->sysc_flags & SYSC_HAS_CLOCKACTIVITY) |
564 | _set_clockactivity(oh, oh->sysconfig->clockact, &v); | 605 | _set_clockactivity(oh, oh->sysconfig->clockact, &v); |
@@ -622,7 +663,8 @@ static void _sysc_shutdown(struct omap_hwmod *oh) | |||
622 | if (oh->sysconfig->sysc_flags & SYSC_HAS_MIDLEMODE) | 663 | if (oh->sysconfig->sysc_flags & SYSC_HAS_MIDLEMODE) |
623 | _set_master_standbymode(oh, HWMOD_IDLEMODE_FORCE, &v); | 664 | _set_master_standbymode(oh, HWMOD_IDLEMODE_FORCE, &v); |
624 | 665 | ||
625 | /* XXX clear OCP AUTOIDLE bit? */ | 666 | if (oh->sysconfig->sysc_flags & SYSC_HAS_AUTOIDLE) |
667 | _set_module_autoidle(oh, 1, &v); | ||
626 | 668 | ||
627 | _write_sysconfig(v, oh); | 669 | _write_sysconfig(v, oh); |
628 | } | 670 | } |
@@ -736,7 +778,7 @@ static int _wait_target_ready(struct omap_hwmod *oh) | |||
736 | static int _reset(struct omap_hwmod *oh) | 778 | static int _reset(struct omap_hwmod *oh) |
737 | { | 779 | { |
738 | u32 r, v; | 780 | u32 r, v; |
739 | int c; | 781 | int c = 0; |
740 | 782 | ||
741 | if (!oh->sysconfig || | 783 | if (!oh->sysconfig || |
742 | !(oh->sysconfig->sysc_flags & SYSC_HAS_SOFTRESET) || | 784 | !(oh->sysconfig->sysc_flags & SYSC_HAS_SOFTRESET) || |
@@ -758,13 +800,9 @@ static int _reset(struct omap_hwmod *oh) | |||
758 | return r; | 800 | return r; |
759 | _write_sysconfig(v, oh); | 801 | _write_sysconfig(v, oh); |
760 | 802 | ||
761 | c = 0; | 803 | omap_test_timeout((omap_hwmod_readl(oh, oh->sysconfig->syss_offs) & |
762 | while (c < MAX_MODULE_RESET_WAIT && | 804 | SYSS_RESETDONE_MASK), |
763 | !(omap_hwmod_readl(oh, oh->sysconfig->syss_offs) & | 805 | MAX_MODULE_RESET_WAIT, c); |
764 | SYSS_RESETDONE_MASK)) { | ||
765 | udelay(1); | ||
766 | c++; | ||
767 | } | ||
768 | 806 | ||
769 | if (c == MAX_MODULE_RESET_WAIT) | 807 | if (c == MAX_MODULE_RESET_WAIT) |
770 | WARN(1, "omap_hwmod: %s: failed to reset in %d usec\n", | 808 | WARN(1, "omap_hwmod: %s: failed to reset in %d usec\n", |
@@ -884,33 +922,6 @@ static int _shutdown(struct omap_hwmod *oh) | |||
884 | } | 922 | } |
885 | 923 | ||
886 | /** | 924 | /** |
887 | * _write_clockact_lock - set the module's clockactivity bits | ||
888 | * @oh: struct omap_hwmod * | ||
889 | * @clockact: CLOCKACTIVITY field bits | ||
890 | * | ||
891 | * Writes the CLOCKACTIVITY bits @clockact to the hwmod @oh | ||
892 | * OCP_SYSCONFIG register. Returns -EINVAL if the hwmod is in the | ||
893 | * wrong state or returns 0. | ||
894 | */ | ||
895 | static int _write_clockact_lock(struct omap_hwmod *oh, u8 clockact) | ||
896 | { | ||
897 | u32 v; | ||
898 | |||
899 | if (!oh->sysconfig || | ||
900 | !(oh->sysconfig->sysc_flags & SYSC_HAS_CLOCKACTIVITY)) | ||
901 | return -EINVAL; | ||
902 | |||
903 | mutex_lock(&omap_hwmod_mutex); | ||
904 | v = oh->_sysc_cache; | ||
905 | _set_clockactivity(oh, clockact, &v); | ||
906 | _write_sysconfig(v, oh); | ||
907 | mutex_unlock(&omap_hwmod_mutex); | ||
908 | |||
909 | return 0; | ||
910 | } | ||
911 | |||
912 | |||
913 | /** | ||
914 | * _setup - do initial configuration of omap_hwmod | 925 | * _setup - do initial configuration of omap_hwmod |
915 | * @oh: struct omap_hwmod * | 926 | * @oh: struct omap_hwmod * |
916 | * | 927 | * |
@@ -948,11 +959,19 @@ static int _setup(struct omap_hwmod *oh) | |||
948 | 959 | ||
949 | _enable(oh); | 960 | _enable(oh); |
950 | 961 | ||
951 | if (!(oh->flags & HWMOD_INIT_NO_RESET)) | 962 | if (!(oh->flags & HWMOD_INIT_NO_RESET)) { |
952 | _reset(oh); | 963 | /* |
953 | 964 | * XXX Do the OCP_SYSCONFIG bits need to be | |
954 | /* XXX OCP AUTOIDLE bit? */ | 965 | * reprogrammed after a reset? If not, then this can |
955 | /* XXX OCP ENAWAKEUP bit? */ | 966 | * be removed. If they do, then probably the |
967 | * _enable() function should be split to avoid the | ||
968 | * rewrite of the OCP_SYSCONFIG register. | ||
969 | */ | ||
970 | if (oh->sysconfig) { | ||
971 | _update_sysc_cache(oh); | ||
972 | _sysc_enable(oh); | ||
973 | } | ||
974 | } | ||
956 | 975 | ||
957 | if (!(oh->flags & HWMOD_INIT_NO_IDLE)) | 976 | if (!(oh->flags & HWMOD_INIT_NO_IDLE)) |
958 | _idle(oh); | 977 | _idle(oh); |
@@ -1348,8 +1367,9 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res) | |||
1348 | /* For each IRQ, DMA, memory area, fill in array.*/ | 1367 | /* For each IRQ, DMA, memory area, fill in array.*/ |
1349 | 1368 | ||
1350 | for (i = 0; i < oh->mpu_irqs_cnt; i++) { | 1369 | for (i = 0; i < oh->mpu_irqs_cnt; i++) { |
1351 | (res + r)->start = *(oh->mpu_irqs + i); | 1370 | (res + r)->name = (oh->mpu_irqs + i)->name; |
1352 | (res + r)->end = *(oh->mpu_irqs + i); | 1371 | (res + r)->start = (oh->mpu_irqs + i)->irq; |
1372 | (res + r)->end = (oh->mpu_irqs + i)->irq; | ||
1353 | (res + r)->flags = IORESOURCE_IRQ; | 1373 | (res + r)->flags = IORESOURCE_IRQ; |
1354 | r++; | 1374 | r++; |
1355 | } | 1375 | } |
@@ -1454,62 +1474,6 @@ int omap_hwmod_del_initiator_dep(struct omap_hwmod *oh, | |||
1454 | } | 1474 | } |
1455 | 1475 | ||
1456 | /** | 1476 | /** |
1457 | * omap_hwmod_set_clockact_none - set clockactivity test to BOTH | ||
1458 | * @oh: struct omap_hwmod * | ||
1459 | * | ||
1460 | * On some modules, this function can affect the wakeup latency vs. | ||
1461 | * power consumption balance. Intended to be called by the | ||
1462 | * omap_device layer. Passes along the return value from | ||
1463 | * _write_clockact_lock(). | ||
1464 | */ | ||
1465 | int omap_hwmod_set_clockact_both(struct omap_hwmod *oh) | ||
1466 | { | ||
1467 | return _write_clockact_lock(oh, CLOCKACT_TEST_BOTH); | ||
1468 | } | ||
1469 | |||
1470 | /** | ||
1471 | * omap_hwmod_set_clockact_none - set clockactivity test to MAIN | ||
1472 | * @oh: struct omap_hwmod * | ||
1473 | * | ||
1474 | * On some modules, this function can affect the wakeup latency vs. | ||
1475 | * power consumption balance. Intended to be called by the | ||
1476 | * omap_device layer. Passes along the return value from | ||
1477 | * _write_clockact_lock(). | ||
1478 | */ | ||
1479 | int omap_hwmod_set_clockact_main(struct omap_hwmod *oh) | ||
1480 | { | ||
1481 | return _write_clockact_lock(oh, CLOCKACT_TEST_MAIN); | ||
1482 | } | ||
1483 | |||
1484 | /** | ||
1485 | * omap_hwmod_set_clockact_none - set clockactivity test to ICLK | ||
1486 | * @oh: struct omap_hwmod * | ||
1487 | * | ||
1488 | * On some modules, this function can affect the wakeup latency vs. | ||
1489 | * power consumption balance. Intended to be called by the | ||
1490 | * omap_device layer. Passes along the return value from | ||
1491 | * _write_clockact_lock(). | ||
1492 | */ | ||
1493 | int omap_hwmod_set_clockact_iclk(struct omap_hwmod *oh) | ||
1494 | { | ||
1495 | return _write_clockact_lock(oh, CLOCKACT_TEST_ICLK); | ||
1496 | } | ||
1497 | |||
1498 | /** | ||
1499 | * omap_hwmod_set_clockact_none - set clockactivity test to NONE | ||
1500 | * @oh: struct omap_hwmod * | ||
1501 | * | ||
1502 | * On some modules, this function can affect the wakeup latency vs. | ||
1503 | * power consumption balance. Intended to be called by the | ||
1504 | * omap_device layer. Passes along the return value from | ||
1505 | * _write_clockact_lock(). | ||
1506 | */ | ||
1507 | int omap_hwmod_set_clockact_none(struct omap_hwmod *oh) | ||
1508 | { | ||
1509 | return _write_clockact_lock(oh, CLOCKACT_TEST_NONE); | ||
1510 | } | ||
1511 | |||
1512 | /** | ||
1513 | * omap_hwmod_enable_wakeup - allow device to wake up the system | 1477 | * omap_hwmod_enable_wakeup - allow device to wake up the system |
1514 | * @oh: struct omap_hwmod * | 1478 | * @oh: struct omap_hwmod * |
1515 | * | 1479 | * |
diff --git a/arch/arm/mach-omap2/opp2420_data.c b/arch/arm/mach-omap2/opp2420_data.c new file mode 100644 index 000000000000..126a9396b3a8 --- /dev/null +++ b/arch/arm/mach-omap2/opp2420_data.c | |||
@@ -0,0 +1,126 @@ | |||
1 | /* | ||
2 | * opp2420_data.c - old-style "OPP" table for OMAP2420 | ||
3 | * | ||
4 | * Copyright (C) 2005-2009 Texas Instruments, Inc. | ||
5 | * Copyright (C) 2004-2009 Nokia Corporation | ||
6 | * | ||
7 | * Richard Woodruff <r-woodruff2@ti.com> | ||
8 | * | ||
9 | * The OMAP2 processor can be run at several discrete 'PRCM configurations'. | ||
10 | * These configurations are characterized by voltage and speed for clocks. | ||
11 | * The device is only validated for certain combinations. One way to express | ||
12 | * these combinations is via the 'ratio's' which the clocks operate with | ||
13 | * respect to each other. These ratio sets are for a given voltage/DPLL | ||
14 | * setting. All configurations can be described by a DPLL setting and a ratio | ||
15 | * There are 3 ratio sets for the 2430 and X ratio sets for 2420. | ||
16 | * | ||
17 | * 2430 differs from 2420 in that there are no more phase synchronizers used. | ||
18 | * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs | ||
19 | * 2430 (iva2.1, NOdsp, mdm) | ||
20 | * | ||
21 | * XXX Missing voltage data. | ||
22 | * | ||
23 | * THe format described in this file is deprecated. Once a reasonable | ||
24 | * OPP API exists, the data in this file should be converted to use it. | ||
25 | * | ||
26 | * This is technically part of the OMAP2xxx clock code. | ||
27 | */ | ||
28 | |||
29 | #include "opp2xxx.h" | ||
30 | #include "sdrc.h" | ||
31 | #include "clock.h" | ||
32 | |||
33 | /*------------------------------------------------------------------------- | ||
34 | * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated. | ||
35 | * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU, | ||
36 | * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL, | ||
37 | * CM_CLKSEL2_PLL, CM_CLKSEL_MDM | ||
38 | * | ||
39 | * Filling in table based on H4 boards and 2430-SDPs variants available. | ||
40 | * There are quite a few more rates combinations which could be defined. | ||
41 | * | ||
42 | * When multiple values are defined the start up will try and choose the | ||
43 | * fastest one. If a 'fast' value is defined, then automatically, the /2 | ||
44 | * one should be included as it can be used. Generally having more that | ||
45 | * one fast set does not make sense, as static timings need to be changed | ||
46 | * to change the set. The exception is the bypass setting which is | ||
47 | * availble for low power bypass. | ||
48 | * | ||
49 | * Note: This table needs to be sorted, fastest to slowest. | ||
50 | *-------------------------------------------------------------------------*/ | ||
51 | const struct prcm_config omap2420_rate_table[] = { | ||
52 | /* PRCM I - FAST */ | ||
53 | {S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */ | ||
54 | RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL, | ||
55 | RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL, | ||
56 | MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_165MHz, | ||
57 | RATE_IN_242X}, | ||
58 | |||
59 | /* PRCM II - FAST */ | ||
60 | {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */ | ||
61 | RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL, | ||
62 | RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL, | ||
63 | MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz, | ||
64 | RATE_IN_242X}, | ||
65 | |||
66 | {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */ | ||
67 | RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL, | ||
68 | RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL, | ||
69 | MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz, | ||
70 | RATE_IN_242X}, | ||
71 | |||
72 | /* PRCM III - FAST */ | ||
73 | {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */ | ||
74 | RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL, | ||
75 | RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL, | ||
76 | MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz, | ||
77 | RATE_IN_242X}, | ||
78 | |||
79 | {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */ | ||
80 | RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL, | ||
81 | RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL, | ||
82 | MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz, | ||
83 | RATE_IN_242X}, | ||
84 | |||
85 | /* PRCM II - SLOW */ | ||
86 | {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */ | ||
87 | RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL, | ||
88 | RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL, | ||
89 | MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz, | ||
90 | RATE_IN_242X}, | ||
91 | |||
92 | {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */ | ||
93 | RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL, | ||
94 | RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL, | ||
95 | MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz, | ||
96 | RATE_IN_242X}, | ||
97 | |||
98 | /* PRCM III - SLOW */ | ||
99 | {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */ | ||
100 | RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL, | ||
101 | RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL, | ||
102 | MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz, | ||
103 | RATE_IN_242X}, | ||
104 | |||
105 | {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */ | ||
106 | RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL, | ||
107 | RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL, | ||
108 | MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz, | ||
109 | RATE_IN_242X}, | ||
110 | |||
111 | /* PRCM-VII (boot-bypass) */ | ||
112 | {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL, /* 12MHz ARM*/ | ||
113 | RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL, | ||
114 | RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL, | ||
115 | MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS, | ||
116 | RATE_IN_242X}, | ||
117 | |||
118 | /* PRCM-VII (boot-bypass) */ | ||
119 | {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL, /* 13MHz ARM */ | ||
120 | RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL, | ||
121 | RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL, | ||
122 | MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS, | ||
123 | RATE_IN_242X}, | ||
124 | |||
125 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, | ||
126 | }; | ||
diff --git a/arch/arm/mach-omap2/opp2430_data.c b/arch/arm/mach-omap2/opp2430_data.c new file mode 100644 index 000000000000..edb81672c844 --- /dev/null +++ b/arch/arm/mach-omap2/opp2430_data.c | |||
@@ -0,0 +1,133 @@ | |||
1 | /* | ||
2 | * opp2420_data.c - old-style "OPP" table for OMAP2420 | ||
3 | * | ||
4 | * Copyright (C) 2005-2009 Texas Instruments, Inc. | ||
5 | * Copyright (C) 2004-2009 Nokia Corporation | ||
6 | * | ||
7 | * Richard Woodruff <r-woodruff2@ti.com> | ||
8 | * | ||
9 | * The OMAP2 processor can be run at several discrete 'PRCM configurations'. | ||
10 | * These configurations are characterized by voltage and speed for clocks. | ||
11 | * The device is only validated for certain combinations. One way to express | ||
12 | * these combinations is via the 'ratio's' which the clocks operate with | ||
13 | * respect to each other. These ratio sets are for a given voltage/DPLL | ||
14 | * setting. All configurations can be described by a DPLL setting and a ratio | ||
15 | * There are 3 ratio sets for the 2430 and X ratio sets for 2420. | ||
16 | * | ||
17 | * 2430 differs from 2420 in that there are no more phase synchronizers used. | ||
18 | * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs | ||
19 | * 2430 (iva2.1, NOdsp, mdm) | ||
20 | * | ||
21 | * XXX Missing voltage data. | ||
22 | * | ||
23 | * THe format described in this file is deprecated. Once a reasonable | ||
24 | * OPP API exists, the data in this file should be converted to use it. | ||
25 | * | ||
26 | * This is technically part of the OMAP2xxx clock code. | ||
27 | */ | ||
28 | |||
29 | #include "opp2xxx.h" | ||
30 | #include "sdrc.h" | ||
31 | #include "clock.h" | ||
32 | |||
33 | /*------------------------------------------------------------------------- | ||
34 | * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated. | ||
35 | * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU, | ||
36 | * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL, | ||
37 | * CM_CLKSEL2_PLL, CM_CLKSEL_MDM | ||
38 | * | ||
39 | * Filling in table based on H4 boards and 2430-SDPs variants available. | ||
40 | * There are quite a few more rates combinations which could be defined. | ||
41 | * | ||
42 | * When multiple values are defined the start up will try and choose the | ||
43 | * fastest one. If a 'fast' value is defined, then automatically, the /2 | ||
44 | * one should be included as it can be used. Generally having more that | ||
45 | * one fast set does not make sense, as static timings need to be changed | ||
46 | * to change the set. The exception is the bypass setting which is | ||
47 | * availble for low power bypass. | ||
48 | * | ||
49 | * Note: This table needs to be sorted, fastest to slowest. | ||
50 | *-------------------------------------------------------------------------*/ | ||
51 | const struct prcm_config omap2430_rate_table[] = { | ||
52 | /* PRCM #4 - ratio2 (ES2.1) - FAST */ | ||
53 | {S13M, S798M, S399M, R2_CM_CLKSEL_MPU_VAL, /* 399MHz ARM */ | ||
54 | R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL, | ||
55 | R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL, | ||
56 | MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL, | ||
57 | SDRC_RFR_CTRL_133MHz, | ||
58 | RATE_IN_243X}, | ||
59 | |||
60 | /* PRCM #2 - ratio1 (ES2) - FAST */ | ||
61 | {S13M, S658M, S329M, R1_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */ | ||
62 | R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, | ||
63 | R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL, | ||
64 | MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL, | ||
65 | SDRC_RFR_CTRL_165MHz, | ||
66 | RATE_IN_243X}, | ||
67 | |||
68 | /* PRCM #5a - ratio1 - FAST */ | ||
69 | {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */ | ||
70 | R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, | ||
71 | R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL, | ||
72 | MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL, | ||
73 | SDRC_RFR_CTRL_133MHz, | ||
74 | RATE_IN_243X}, | ||
75 | |||
76 | /* PRCM #5b - ratio1 - FAST */ | ||
77 | {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */ | ||
78 | R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, | ||
79 | R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL, | ||
80 | MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL, | ||
81 | SDRC_RFR_CTRL_100MHz, | ||
82 | RATE_IN_243X}, | ||
83 | |||
84 | /* PRCM #4 - ratio1 (ES2.1) - SLOW */ | ||
85 | {S13M, S399M, S199M, R2_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */ | ||
86 | R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL, | ||
87 | R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL, | ||
88 | MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL, | ||
89 | SDRC_RFR_CTRL_133MHz, | ||
90 | RATE_IN_243X}, | ||
91 | |||
92 | /* PRCM #2 - ratio1 (ES2) - SLOW */ | ||
93 | {S13M, S329M, S164M, R1_CM_CLKSEL_MPU_VAL, /* 165MHz ARM */ | ||
94 | R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, | ||
95 | R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL, | ||
96 | MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL, | ||
97 | SDRC_RFR_CTRL_165MHz, | ||
98 | RATE_IN_243X}, | ||
99 | |||
100 | /* PRCM #5a - ratio1 - SLOW */ | ||
101 | {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */ | ||
102 | R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, | ||
103 | R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL, | ||
104 | MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL, | ||
105 | SDRC_RFR_CTRL_133MHz, | ||
106 | RATE_IN_243X}, | ||
107 | |||
108 | /* PRCM #5b - ratio1 - SLOW*/ | ||
109 | {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL, /* 100MHz ARM */ | ||
110 | R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, | ||
111 | R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL, | ||
112 | MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL, | ||
113 | SDRC_RFR_CTRL_100MHz, | ||
114 | RATE_IN_243X}, | ||
115 | |||
116 | /* PRCM-boot/bypass */ | ||
117 | {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL, /* 13Mhz */ | ||
118 | RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL, | ||
119 | RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL, | ||
120 | MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL, | ||
121 | SDRC_RFR_CTRL_BYPASS, | ||
122 | RATE_IN_243X}, | ||
123 | |||
124 | /* PRCM-boot/bypass */ | ||
125 | {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL, /* 12Mhz */ | ||
126 | RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL, | ||
127 | RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL, | ||
128 | MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL, | ||
129 | SDRC_RFR_CTRL_BYPASS, | ||
130 | RATE_IN_243X}, | ||
131 | |||
132 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, | ||
133 | }; | ||
diff --git a/arch/arm/mach-omap2/opp2xxx.h b/arch/arm/mach-omap2/opp2xxx.h new file mode 100644 index 000000000000..ed6df04e2f29 --- /dev/null +++ b/arch/arm/mach-omap2/opp2xxx.h | |||
@@ -0,0 +1,424 @@ | |||
1 | /* | ||
2 | * opp2xxx.h - macros for old-style OMAP2xxx "OPP" definitions | ||
3 | * | ||
4 | * Copyright (C) 2005-2009 Texas Instruments, Inc. | ||
5 | * Copyright (C) 2004-2009 Nokia Corporation | ||
6 | * | ||
7 | * Richard Woodruff <r-woodruff2@ti.com> | ||
8 | * | ||
9 | * The OMAP2 processor can be run at several discrete 'PRCM configurations'. | ||
10 | * These configurations are characterized by voltage and speed for clocks. | ||
11 | * The device is only validated for certain combinations. One way to express | ||
12 | * these combinations is via the 'ratio's' which the clocks operate with | ||
13 | * respect to each other. These ratio sets are for a given voltage/DPLL | ||
14 | * setting. All configurations can be described by a DPLL setting and a ratio | ||
15 | * There are 3 ratio sets for the 2430 and X ratio sets for 2420. | ||
16 | * | ||
17 | * 2430 differs from 2420 in that there are no more phase synchronizers used. | ||
18 | * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs | ||
19 | * 2430 (iva2.1, NOdsp, mdm) | ||
20 | * | ||
21 | * XXX Missing voltage data. | ||
22 | * | ||
23 | * THe format described in this file is deprecated. Once a reasonable | ||
24 | * OPP API exists, the data in this file should be converted to use it. | ||
25 | * | ||
26 | * This is technically part of the OMAP2xxx clock code. | ||
27 | */ | ||
28 | |||
29 | #ifndef __ARCH_ARM_MACH_OMAP2_OPP2XXX_H | ||
30 | #define __ARCH_ARM_MACH_OMAP2_OPP2XXX_H | ||
31 | |||
32 | /** | ||
33 | * struct prcm_config - define clock rates on a per-OPP basis (24xx) | ||
34 | * | ||
35 | * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated. | ||
36 | * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP | ||
37 | * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM | ||
38 | * | ||
39 | * This is deprecated. As soon as we have a decent OPP API, we should | ||
40 | * move all this stuff to it. | ||
41 | */ | ||
42 | struct prcm_config { | ||
43 | unsigned long xtal_speed; /* crystal rate */ | ||
44 | unsigned long dpll_speed; /* dpll: out*xtal*M/(N-1)table_recalc */ | ||
45 | unsigned long mpu_speed; /* speed of MPU */ | ||
46 | unsigned long cm_clksel_mpu; /* mpu divider */ | ||
47 | unsigned long cm_clksel_dsp; /* dsp+iva1 div(2420), iva2.1(2430) */ | ||
48 | unsigned long cm_clksel_gfx; /* gfx dividers */ | ||
49 | unsigned long cm_clksel1_core; /* major subsystem dividers */ | ||
50 | unsigned long cm_clksel1_pll; /* m,n */ | ||
51 | unsigned long cm_clksel2_pll; /* dpllx1 or x2 out */ | ||
52 | unsigned long cm_clksel_mdm; /* modem dividers 2430 only */ | ||
53 | unsigned long base_sdrc_rfr; /* base refresh timing for a set */ | ||
54 | unsigned char flags; | ||
55 | }; | ||
56 | |||
57 | |||
58 | /* Core fields for cm_clksel, not ratio governed */ | ||
59 | #define RX_CLKSEL_DSS1 (0x10 << 8) | ||
60 | #define RX_CLKSEL_DSS2 (0x0 << 13) | ||
61 | #define RX_CLKSEL_SSI (0x5 << 20) | ||
62 | |||
63 | /*------------------------------------------------------------------------- | ||
64 | * Voltage/DPLL ratios | ||
65 | *-------------------------------------------------------------------------*/ | ||
66 | |||
67 | /* 2430 Ratio's, 2430-Ratio Config 1 */ | ||
68 | #define R1_CLKSEL_L3 (4 << 0) | ||
69 | #define R1_CLKSEL_L4 (2 << 5) | ||
70 | #define R1_CLKSEL_USB (4 << 25) | ||
71 | #define R1_CM_CLKSEL1_CORE_VAL (R1_CLKSEL_USB | RX_CLKSEL_SSI | \ | ||
72 | RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \ | ||
73 | R1_CLKSEL_L4 | R1_CLKSEL_L3) | ||
74 | #define R1_CLKSEL_MPU (2 << 0) | ||
75 | #define R1_CM_CLKSEL_MPU_VAL R1_CLKSEL_MPU | ||
76 | #define R1_CLKSEL_DSP (2 << 0) | ||
77 | #define R1_CLKSEL_DSP_IF (2 << 5) | ||
78 | #define R1_CM_CLKSEL_DSP_VAL (R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF) | ||
79 | #define R1_CLKSEL_GFX (2 << 0) | ||
80 | #define R1_CM_CLKSEL_GFX_VAL R1_CLKSEL_GFX | ||
81 | #define R1_CLKSEL_MDM (4 << 0) | ||
82 | #define R1_CM_CLKSEL_MDM_VAL R1_CLKSEL_MDM | ||
83 | |||
84 | /* 2430-Ratio Config 2 */ | ||
85 | #define R2_CLKSEL_L3 (6 << 0) | ||
86 | #define R2_CLKSEL_L4 (2 << 5) | ||
87 | #define R2_CLKSEL_USB (2 << 25) | ||
88 | #define R2_CM_CLKSEL1_CORE_VAL (R2_CLKSEL_USB | RX_CLKSEL_SSI | \ | ||
89 | RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \ | ||
90 | R2_CLKSEL_L4 | R2_CLKSEL_L3) | ||
91 | #define R2_CLKSEL_MPU (2 << 0) | ||
92 | #define R2_CM_CLKSEL_MPU_VAL R2_CLKSEL_MPU | ||
93 | #define R2_CLKSEL_DSP (2 << 0) | ||
94 | #define R2_CLKSEL_DSP_IF (3 << 5) | ||
95 | #define R2_CM_CLKSEL_DSP_VAL (R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF) | ||
96 | #define R2_CLKSEL_GFX (2 << 0) | ||
97 | #define R2_CM_CLKSEL_GFX_VAL R2_CLKSEL_GFX | ||
98 | #define R2_CLKSEL_MDM (6 << 0) | ||
99 | #define R2_CM_CLKSEL_MDM_VAL R2_CLKSEL_MDM | ||
100 | |||
101 | /* 2430-Ratio Bootm (BYPASS) */ | ||
102 | #define RB_CLKSEL_L3 (1 << 0) | ||
103 | #define RB_CLKSEL_L4 (1 << 5) | ||
104 | #define RB_CLKSEL_USB (1 << 25) | ||
105 | #define RB_CM_CLKSEL1_CORE_VAL (RB_CLKSEL_USB | RX_CLKSEL_SSI | \ | ||
106 | RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \ | ||
107 | RB_CLKSEL_L4 | RB_CLKSEL_L3) | ||
108 | #define RB_CLKSEL_MPU (1 << 0) | ||
109 | #define RB_CM_CLKSEL_MPU_VAL RB_CLKSEL_MPU | ||
110 | #define RB_CLKSEL_DSP (1 << 0) | ||
111 | #define RB_CLKSEL_DSP_IF (1 << 5) | ||
112 | #define RB_CM_CLKSEL_DSP_VAL (RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF) | ||
113 | #define RB_CLKSEL_GFX (1 << 0) | ||
114 | #define RB_CM_CLKSEL_GFX_VAL RB_CLKSEL_GFX | ||
115 | #define RB_CLKSEL_MDM (1 << 0) | ||
116 | #define RB_CM_CLKSEL_MDM_VAL RB_CLKSEL_MDM | ||
117 | |||
118 | /* 2420 Ratio Equivalents */ | ||
119 | #define RXX_CLKSEL_VLYNQ (0x12 << 15) | ||
120 | #define RXX_CLKSEL_SSI (0x8 << 20) | ||
121 | |||
122 | /* 2420-PRCM III 532MHz core */ | ||
123 | #define RIII_CLKSEL_L3 (4 << 0) /* 133MHz */ | ||
124 | #define RIII_CLKSEL_L4 (2 << 5) /* 66.5MHz */ | ||
125 | #define RIII_CLKSEL_USB (4 << 25) /* 33.25MHz */ | ||
126 | #define RIII_CM_CLKSEL1_CORE_VAL (RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \ | ||
127 | RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \ | ||
128 | RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \ | ||
129 | RIII_CLKSEL_L3) | ||
130 | #define RIII_CLKSEL_MPU (2 << 0) /* 266MHz */ | ||
131 | #define RIII_CM_CLKSEL_MPU_VAL RIII_CLKSEL_MPU | ||
132 | #define RIII_CLKSEL_DSP (3 << 0) /* c5x - 177.3MHz */ | ||
133 | #define RIII_CLKSEL_DSP_IF (2 << 5) /* c5x - 88.67MHz */ | ||
134 | #define RIII_SYNC_DSP (1 << 7) /* Enable sync */ | ||
135 | #define RIII_CLKSEL_IVA (6 << 8) /* iva1 - 88.67MHz */ | ||
136 | #define RIII_SYNC_IVA (1 << 13) /* Enable sync */ | ||
137 | #define RIII_CM_CLKSEL_DSP_VAL (RIII_SYNC_IVA | RIII_CLKSEL_IVA | \ | ||
138 | RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \ | ||
139 | RIII_CLKSEL_DSP) | ||
140 | #define RIII_CLKSEL_GFX (2 << 0) /* 66.5MHz */ | ||
141 | #define RIII_CM_CLKSEL_GFX_VAL RIII_CLKSEL_GFX | ||
142 | |||
143 | /* 2420-PRCM II 600MHz core */ | ||
144 | #define RII_CLKSEL_L3 (6 << 0) /* 100MHz */ | ||
145 | #define RII_CLKSEL_L4 (2 << 5) /* 50MHz */ | ||
146 | #define RII_CLKSEL_USB (2 << 25) /* 50MHz */ | ||
147 | #define RII_CM_CLKSEL1_CORE_VAL (RII_CLKSEL_USB | RXX_CLKSEL_SSI | \ | ||
148 | RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \ | ||
149 | RX_CLKSEL_DSS1 | RII_CLKSEL_L4 | \ | ||
150 | RII_CLKSEL_L3) | ||
151 | #define RII_CLKSEL_MPU (2 << 0) /* 300MHz */ | ||
152 | #define RII_CM_CLKSEL_MPU_VAL RII_CLKSEL_MPU | ||
153 | #define RII_CLKSEL_DSP (3 << 0) /* c5x - 200MHz */ | ||
154 | #define RII_CLKSEL_DSP_IF (2 << 5) /* c5x - 100MHz */ | ||
155 | #define RII_SYNC_DSP (0 << 7) /* Bypass sync */ | ||
156 | #define RII_CLKSEL_IVA (3 << 8) /* iva1 - 200MHz */ | ||
157 | #define RII_SYNC_IVA (0 << 13) /* Bypass sync */ | ||
158 | #define RII_CM_CLKSEL_DSP_VAL (RII_SYNC_IVA | RII_CLKSEL_IVA | \ | ||
159 | RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \ | ||
160 | RII_CLKSEL_DSP) | ||
161 | #define RII_CLKSEL_GFX (2 << 0) /* 50MHz */ | ||
162 | #define RII_CM_CLKSEL_GFX_VAL RII_CLKSEL_GFX | ||
163 | |||
164 | /* 2420-PRCM I 660MHz core */ | ||
165 | #define RI_CLKSEL_L3 (4 << 0) /* 165MHz */ | ||
166 | #define RI_CLKSEL_L4 (2 << 5) /* 82.5MHz */ | ||
167 | #define RI_CLKSEL_USB (4 << 25) /* 41.25MHz */ | ||
168 | #define RI_CM_CLKSEL1_CORE_VAL (RI_CLKSEL_USB | \ | ||
169 | RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \ | ||
170 | RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \ | ||
171 | RI_CLKSEL_L4 | RI_CLKSEL_L3) | ||
172 | #define RI_CLKSEL_MPU (2 << 0) /* 330MHz */ | ||
173 | #define RI_CM_CLKSEL_MPU_VAL RI_CLKSEL_MPU | ||
174 | #define RI_CLKSEL_DSP (3 << 0) /* c5x - 220MHz */ | ||
175 | #define RI_CLKSEL_DSP_IF (2 << 5) /* c5x - 110MHz */ | ||
176 | #define RI_SYNC_DSP (1 << 7) /* Activate sync */ | ||
177 | #define RI_CLKSEL_IVA (4 << 8) /* iva1 - 165MHz */ | ||
178 | #define RI_SYNC_IVA (0 << 13) /* Bypass sync */ | ||
179 | #define RI_CM_CLKSEL_DSP_VAL (RI_SYNC_IVA | RI_CLKSEL_IVA | \ | ||
180 | RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \ | ||
181 | RI_CLKSEL_DSP) | ||
182 | #define RI_CLKSEL_GFX (1 << 0) /* 165MHz */ | ||
183 | #define RI_CM_CLKSEL_GFX_VAL RI_CLKSEL_GFX | ||
184 | |||
185 | /* 2420-PRCM VII (boot) */ | ||
186 | #define RVII_CLKSEL_L3 (1 << 0) | ||
187 | #define RVII_CLKSEL_L4 (1 << 5) | ||
188 | #define RVII_CLKSEL_DSS1 (1 << 8) | ||
189 | #define RVII_CLKSEL_DSS2 (0 << 13) | ||
190 | #define RVII_CLKSEL_VLYNQ (1 << 15) | ||
191 | #define RVII_CLKSEL_SSI (1 << 20) | ||
192 | #define RVII_CLKSEL_USB (1 << 25) | ||
193 | |||
194 | #define RVII_CM_CLKSEL1_CORE_VAL (RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \ | ||
195 | RVII_CLKSEL_VLYNQ | \ | ||
196 | RVII_CLKSEL_DSS2 | RVII_CLKSEL_DSS1 | \ | ||
197 | RVII_CLKSEL_L4 | RVII_CLKSEL_L3) | ||
198 | |||
199 | #define RVII_CLKSEL_MPU (1 << 0) /* all divide by 1 */ | ||
200 | #define RVII_CM_CLKSEL_MPU_VAL RVII_CLKSEL_MPU | ||
201 | |||
202 | #define RVII_CLKSEL_DSP (1 << 0) | ||
203 | #define RVII_CLKSEL_DSP_IF (1 << 5) | ||
204 | #define RVII_SYNC_DSP (0 << 7) | ||
205 | #define RVII_CLKSEL_IVA (1 << 8) | ||
206 | #define RVII_SYNC_IVA (0 << 13) | ||
207 | #define RVII_CM_CLKSEL_DSP_VAL (RVII_SYNC_IVA | RVII_CLKSEL_IVA | \ | ||
208 | RVII_SYNC_DSP | RVII_CLKSEL_DSP_IF | \ | ||
209 | RVII_CLKSEL_DSP) | ||
210 | |||
211 | #define RVII_CLKSEL_GFX (1 << 0) | ||
212 | #define RVII_CM_CLKSEL_GFX_VAL RVII_CLKSEL_GFX | ||
213 | |||
214 | /*------------------------------------------------------------------------- | ||
215 | * 2430 Target modes: Along with each configuration the CPU has several | ||
216 | * modes which goes along with them. Modes mainly are the addition of | ||
217 | * describe DPLL combinations to go along with a ratio. | ||
218 | *-------------------------------------------------------------------------*/ | ||
219 | |||
220 | /* Hardware governed */ | ||
221 | #define MX_48M_SRC (0 << 3) | ||
222 | #define MX_54M_SRC (0 << 5) | ||
223 | #define MX_APLLS_CLIKIN_12 (3 << 23) | ||
224 | #define MX_APLLS_CLIKIN_13 (2 << 23) | ||
225 | #define MX_APLLS_CLIKIN_19_2 (0 << 23) | ||
226 | |||
227 | /* | ||
228 | * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed | ||
229 | * #5a (ratio1) baseport-target, target DPLL = 266*2 = 532MHz | ||
230 | */ | ||
231 | #define M5A_DPLL_MULT_12 (133 << 12) | ||
232 | #define M5A_DPLL_DIV_12 (5 << 8) | ||
233 | #define M5A_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \ | ||
234 | M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \ | ||
235 | MX_APLLS_CLIKIN_12) | ||
236 | #define M5A_DPLL_MULT_13 (61 << 12) | ||
237 | #define M5A_DPLL_DIV_13 (2 << 8) | ||
238 | #define M5A_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \ | ||
239 | M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \ | ||
240 | MX_APLLS_CLIKIN_13) | ||
241 | #define M5A_DPLL_MULT_19 (55 << 12) | ||
242 | #define M5A_DPLL_DIV_19 (3 << 8) | ||
243 | #define M5A_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \ | ||
244 | M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \ | ||
245 | MX_APLLS_CLIKIN_19_2) | ||
246 | /* #5b (ratio1) target DPLL = 200*2 = 400MHz */ | ||
247 | #define M5B_DPLL_MULT_12 (50 << 12) | ||
248 | #define M5B_DPLL_DIV_12 (2 << 8) | ||
249 | #define M5B_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \ | ||
250 | M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \ | ||
251 | MX_APLLS_CLIKIN_12) | ||
252 | #define M5B_DPLL_MULT_13 (200 << 12) | ||
253 | #define M5B_DPLL_DIV_13 (12 << 8) | ||
254 | |||
255 | #define M5B_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \ | ||
256 | M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \ | ||
257 | MX_APLLS_CLIKIN_13) | ||
258 | #define M5B_DPLL_MULT_19 (125 << 12) | ||
259 | #define M5B_DPLL_DIV_19 (31 << 8) | ||
260 | #define M5B_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \ | ||
261 | M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \ | ||
262 | MX_APLLS_CLIKIN_19_2) | ||
263 | /* | ||
264 | * #4 (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz | ||
265 | */ | ||
266 | #define M4_DPLL_MULT_12 (133 << 12) | ||
267 | #define M4_DPLL_DIV_12 (3 << 8) | ||
268 | #define M4_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \ | ||
269 | M4_DPLL_DIV_12 | M4_DPLL_MULT_12 | \ | ||
270 | MX_APLLS_CLIKIN_12) | ||
271 | |||
272 | #define M4_DPLL_MULT_13 (399 << 12) | ||
273 | #define M4_DPLL_DIV_13 (12 << 8) | ||
274 | #define M4_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \ | ||
275 | M4_DPLL_DIV_13 | M4_DPLL_MULT_13 | \ | ||
276 | MX_APLLS_CLIKIN_13) | ||
277 | |||
278 | #define M4_DPLL_MULT_19 (145 << 12) | ||
279 | #define M4_DPLL_DIV_19 (6 << 8) | ||
280 | #define M4_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \ | ||
281 | M4_DPLL_DIV_19 | M4_DPLL_MULT_19 | \ | ||
282 | MX_APLLS_CLIKIN_19_2) | ||
283 | |||
284 | /* | ||
285 | * #3 (ratio2) baseport-target, target DPLL = 330*2 = 660MHz | ||
286 | */ | ||
287 | #define M3_DPLL_MULT_12 (55 << 12) | ||
288 | #define M3_DPLL_DIV_12 (1 << 8) | ||
289 | #define M3_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \ | ||
290 | M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \ | ||
291 | MX_APLLS_CLIKIN_12) | ||
292 | #define M3_DPLL_MULT_13 (76 << 12) | ||
293 | #define M3_DPLL_DIV_13 (2 << 8) | ||
294 | #define M3_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \ | ||
295 | M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \ | ||
296 | MX_APLLS_CLIKIN_13) | ||
297 | #define M3_DPLL_MULT_19 (17 << 12) | ||
298 | #define M3_DPLL_DIV_19 (0 << 8) | ||
299 | #define M3_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \ | ||
300 | M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \ | ||
301 | MX_APLLS_CLIKIN_19_2) | ||
302 | |||
303 | /* | ||
304 | * #2 (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz | ||
305 | */ | ||
306 | #define M2_DPLL_MULT_12 (55 << 12) | ||
307 | #define M2_DPLL_DIV_12 (1 << 8) | ||
308 | #define M2_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \ | ||
309 | M2_DPLL_DIV_12 | M2_DPLL_MULT_12 | \ | ||
310 | MX_APLLS_CLIKIN_12) | ||
311 | |||
312 | /* Speed changes - Used 658.7MHz instead of 660MHz for LP-Refresh M=76 N=2, | ||
313 | * relock time issue */ | ||
314 | /* Core frequency changed from 330/165 to 329/164 MHz*/ | ||
315 | #define M2_DPLL_MULT_13 (76 << 12) | ||
316 | #define M2_DPLL_DIV_13 (2 << 8) | ||
317 | #define M2_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \ | ||
318 | M2_DPLL_DIV_13 | M2_DPLL_MULT_13 | \ | ||
319 | MX_APLLS_CLIKIN_13) | ||
320 | |||
321 | #define M2_DPLL_MULT_19 (17 << 12) | ||
322 | #define M2_DPLL_DIV_19 (0 << 8) | ||
323 | #define M2_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \ | ||
324 | M2_DPLL_DIV_19 | M2_DPLL_MULT_19 | \ | ||
325 | MX_APLLS_CLIKIN_19_2) | ||
326 | |||
327 | /* boot (boot) */ | ||
328 | #define MB_DPLL_MULT (1 << 12) | ||
329 | #define MB_DPLL_DIV (0 << 8) | ||
330 | #define MB_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \ | ||
331 | MB_DPLL_DIV | MB_DPLL_MULT | \ | ||
332 | MX_APLLS_CLIKIN_12) | ||
333 | |||
334 | #define MB_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \ | ||
335 | MB_DPLL_DIV | MB_DPLL_MULT | \ | ||
336 | MX_APLLS_CLIKIN_13) | ||
337 | |||
338 | #define MB_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \ | ||
339 | MB_DPLL_DIV | MB_DPLL_MULT | \ | ||
340 | MX_APLLS_CLIKIN_19) | ||
341 | |||
342 | /* | ||
343 | * 2430 - chassis (sedna) | ||
344 | * 165 (ratio1) same as above #2 | ||
345 | * 150 (ratio1) | ||
346 | * 133 (ratio2) same as above #4 | ||
347 | * 110 (ratio2) same as above #3 | ||
348 | * 104 (ratio2) | ||
349 | * boot (boot) | ||
350 | */ | ||
351 | |||
352 | /* PRCM I target DPLL = 2*330MHz = 660MHz */ | ||
353 | #define MI_DPLL_MULT_12 (55 << 12) | ||
354 | #define MI_DPLL_DIV_12 (1 << 8) | ||
355 | #define MI_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \ | ||
356 | MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \ | ||
357 | MX_APLLS_CLIKIN_12) | ||
358 | |||
359 | /* | ||
360 | * 2420 Equivalent - mode registers | ||
361 | * PRCM II , target DPLL = 2*300MHz = 600MHz | ||
362 | */ | ||
363 | #define MII_DPLL_MULT_12 (50 << 12) | ||
364 | #define MII_DPLL_DIV_12 (1 << 8) | ||
365 | #define MII_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \ | ||
366 | MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \ | ||
367 | MX_APLLS_CLIKIN_12) | ||
368 | #define MII_DPLL_MULT_13 (300 << 12) | ||
369 | #define MII_DPLL_DIV_13 (12 << 8) | ||
370 | #define MII_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \ | ||
371 | MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \ | ||
372 | MX_APLLS_CLIKIN_13) | ||
373 | |||
374 | /* PRCM III target DPLL = 2*266 = 532MHz*/ | ||
375 | #define MIII_DPLL_MULT_12 (133 << 12) | ||
376 | #define MIII_DPLL_DIV_12 (5 << 8) | ||
377 | #define MIII_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \ | ||
378 | MIII_DPLL_DIV_12 | \ | ||
379 | MIII_DPLL_MULT_12 | MX_APLLS_CLIKIN_12) | ||
380 | #define MIII_DPLL_MULT_13 (266 << 12) | ||
381 | #define MIII_DPLL_DIV_13 (12 << 8) | ||
382 | #define MIII_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \ | ||
383 | MIII_DPLL_DIV_13 | \ | ||
384 | MIII_DPLL_MULT_13 | MX_APLLS_CLIKIN_13) | ||
385 | |||
386 | /* PRCM VII (boot bypass) */ | ||
387 | #define MVII_CM_CLKSEL1_PLL_12_VAL MB_CM_CLKSEL1_PLL_12_VAL | ||
388 | #define MVII_CM_CLKSEL1_PLL_13_VAL MB_CM_CLKSEL1_PLL_13_VAL | ||
389 | |||
390 | /* High and low operation value */ | ||
391 | #define MX_CLKSEL2_PLL_2x_VAL (2 << 0) | ||
392 | #define MX_CLKSEL2_PLL_1x_VAL (1 << 0) | ||
393 | |||
394 | /* MPU speed defines */ | ||
395 | #define S12M 12000000 | ||
396 | #define S13M 13000000 | ||
397 | #define S19M 19200000 | ||
398 | #define S26M 26000000 | ||
399 | #define S100M 100000000 | ||
400 | #define S133M 133000000 | ||
401 | #define S150M 150000000 | ||
402 | #define S164M 164000000 | ||
403 | #define S165M 165000000 | ||
404 | #define S199M 199000000 | ||
405 | #define S200M 200000000 | ||
406 | #define S266M 266000000 | ||
407 | #define S300M 300000000 | ||
408 | #define S329M 329000000 | ||
409 | #define S330M 330000000 | ||
410 | #define S399M 399000000 | ||
411 | #define S400M 400000000 | ||
412 | #define S532M 532000000 | ||
413 | #define S600M 600000000 | ||
414 | #define S658M 658000000 | ||
415 | #define S660M 660000000 | ||
416 | #define S798M 798000000 | ||
417 | |||
418 | |||
419 | extern const struct prcm_config omap2420_rate_table[]; | ||
420 | extern const struct prcm_config omap2430_rate_table[]; | ||
421 | extern const struct prcm_config *rate_table; | ||
422 | extern const struct prcm_config *curr_prcm_set; | ||
423 | |||
424 | #endif | ||
diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c index 8baa30d2acfb..860b755d2220 100644 --- a/arch/arm/mach-omap2/pm-debug.c +++ b/arch/arm/mach-omap2/pm-debug.c | |||
@@ -326,7 +326,7 @@ int pm_dbg_regset_save(int reg_set) | |||
326 | return 0; | 326 | return 0; |
327 | } | 327 | } |
328 | 328 | ||
329 | static const char pwrdm_state_names[][4] = { | 329 | static const char pwrdm_state_names[][PWRDM_MAX_PWRSTS] = { |
330 | "OFF", | 330 | "OFF", |
331 | "RET", | 331 | "RET", |
332 | "INA", | 332 | "INA", |
@@ -381,7 +381,7 @@ static int pwrdm_dbg_show_counter(struct powerdomain *pwrdm, void *user) | |||
381 | 381 | ||
382 | seq_printf(s, "%s (%s)", pwrdm->name, | 382 | seq_printf(s, "%s (%s)", pwrdm->name, |
383 | pwrdm_state_names[pwrdm->state]); | 383 | pwrdm_state_names[pwrdm->state]); |
384 | for (i = 0; i < 4; i++) | 384 | for (i = 0; i < PWRDM_MAX_PWRSTS; i++) |
385 | seq_printf(s, ",%s:%d", pwrdm_state_names[i], | 385 | seq_printf(s, ",%s:%d", pwrdm_state_names[i], |
386 | pwrdm->state_counter[i]); | 386 | pwrdm->state_counter[i]); |
387 | 387 | ||
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c index b6990e377783..26b3f3ee82a3 100644 --- a/arch/arm/mach-omap2/powerdomain.c +++ b/arch/arm/mach-omap2/powerdomain.c | |||
@@ -10,9 +10,7 @@ | |||
10 | * it under the terms of the GNU General Public License version 2 as | 10 | * it under the terms of the GNU General Public License version 2 as |
11 | * published by the Free Software Foundation. | 11 | * published by the Free Software Foundation. |
12 | */ | 12 | */ |
13 | #ifdef CONFIG_OMAP_DEBUG_POWERDOMAIN | 13 | #undef DEBUG |
14 | # define DEBUG | ||
15 | #endif | ||
16 | 14 | ||
17 | #include <linux/kernel.h> | 15 | #include <linux/kernel.h> |
18 | #include <linux/module.h> | 16 | #include <linux/module.h> |
@@ -160,7 +158,7 @@ static __init void _pwrdm_setup(struct powerdomain *pwrdm) | |||
160 | { | 158 | { |
161 | int i; | 159 | int i; |
162 | 160 | ||
163 | for (i = 0; i < 4; i++) | 161 | for (i = 0; i < PWRDM_MAX_PWRSTS; i++) |
164 | pwrdm->state_counter[i] = 0; | 162 | pwrdm->state_counter[i] = 0; |
165 | 163 | ||
166 | pwrdm_wait_transition(pwrdm); | 164 | pwrdm_wait_transition(pwrdm); |
@@ -480,7 +478,7 @@ int pwrdm_add_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2) | |||
480 | if (IS_ERR(p)) { | 478 | if (IS_ERR(p)) { |
481 | pr_debug("powerdomain: hardware cannot set/clear wake up of " | 479 | pr_debug("powerdomain: hardware cannot set/clear wake up of " |
482 | "%s when %s wakes up\n", pwrdm1->name, pwrdm2->name); | 480 | "%s when %s wakes up\n", pwrdm1->name, pwrdm2->name); |
483 | return IS_ERR(p); | 481 | return PTR_ERR(p); |
484 | } | 482 | } |
485 | 483 | ||
486 | pr_debug("powerdomain: hardware will wake up %s when %s wakes up\n", | 484 | pr_debug("powerdomain: hardware will wake up %s when %s wakes up\n", |
@@ -513,7 +511,7 @@ int pwrdm_del_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2) | |||
513 | if (IS_ERR(p)) { | 511 | if (IS_ERR(p)) { |
514 | pr_debug("powerdomain: hardware cannot set/clear wake up of " | 512 | pr_debug("powerdomain: hardware cannot set/clear wake up of " |
515 | "%s when %s wakes up\n", pwrdm1->name, pwrdm2->name); | 513 | "%s when %s wakes up\n", pwrdm1->name, pwrdm2->name); |
516 | return IS_ERR(p); | 514 | return PTR_ERR(p); |
517 | } | 515 | } |
518 | 516 | ||
519 | pr_debug("powerdomain: hardware will no longer wake up %s after %s " | 517 | pr_debug("powerdomain: hardware will no longer wake up %s after %s " |
@@ -550,7 +548,7 @@ int pwrdm_read_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2) | |||
550 | if (IS_ERR(p)) { | 548 | if (IS_ERR(p)) { |
551 | pr_debug("powerdomain: hardware cannot set/clear wake up of " | 549 | pr_debug("powerdomain: hardware cannot set/clear wake up of " |
552 | "%s when %s wakes up\n", pwrdm1->name, pwrdm2->name); | 550 | "%s when %s wakes up\n", pwrdm1->name, pwrdm2->name); |
553 | return IS_ERR(p); | 551 | return PTR_ERR(p); |
554 | } | 552 | } |
555 | 553 | ||
556 | return prm_read_mod_bits_shift(pwrdm1->prcm_offs, PM_WKDEP, | 554 | return prm_read_mod_bits_shift(pwrdm1->prcm_offs, PM_WKDEP, |
@@ -573,10 +571,10 @@ int pwrdm_add_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2) | |||
573 | { | 571 | { |
574 | struct powerdomain *p; | 572 | struct powerdomain *p; |
575 | 573 | ||
576 | if (!pwrdm1) | 574 | if (!cpu_is_omap34xx()) |
577 | return -EINVAL; | 575 | return -EINVAL; |
578 | 576 | ||
579 | if (!cpu_is_omap34xx()) | 577 | if (!pwrdm1) |
580 | return -EINVAL; | 578 | return -EINVAL; |
581 | 579 | ||
582 | p = _pwrdm_deps_lookup(pwrdm2, pwrdm1->sleepdep_srcs); | 580 | p = _pwrdm_deps_lookup(pwrdm2, pwrdm1->sleepdep_srcs); |
@@ -584,7 +582,7 @@ int pwrdm_add_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2) | |||
584 | pr_debug("powerdomain: hardware cannot set/clear sleep " | 582 | pr_debug("powerdomain: hardware cannot set/clear sleep " |
585 | "dependency affecting %s from %s\n", pwrdm1->name, | 583 | "dependency affecting %s from %s\n", pwrdm1->name, |
586 | pwrdm2->name); | 584 | pwrdm2->name); |
587 | return IS_ERR(p); | 585 | return PTR_ERR(p); |
588 | } | 586 | } |
589 | 587 | ||
590 | pr_debug("powerdomain: will prevent %s from sleeping if %s is active\n", | 588 | pr_debug("powerdomain: will prevent %s from sleeping if %s is active\n", |
@@ -612,10 +610,10 @@ int pwrdm_del_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2) | |||
612 | { | 610 | { |
613 | struct powerdomain *p; | 611 | struct powerdomain *p; |
614 | 612 | ||
615 | if (!pwrdm1) | 613 | if (!cpu_is_omap34xx()) |
616 | return -EINVAL; | 614 | return -EINVAL; |
617 | 615 | ||
618 | if (!cpu_is_omap34xx()) | 616 | if (!pwrdm1) |
619 | return -EINVAL; | 617 | return -EINVAL; |
620 | 618 | ||
621 | p = _pwrdm_deps_lookup(pwrdm2, pwrdm1->sleepdep_srcs); | 619 | p = _pwrdm_deps_lookup(pwrdm2, pwrdm1->sleepdep_srcs); |
@@ -623,7 +621,7 @@ int pwrdm_del_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2) | |||
623 | pr_debug("powerdomain: hardware cannot set/clear sleep " | 621 | pr_debug("powerdomain: hardware cannot set/clear sleep " |
624 | "dependency affecting %s from %s\n", pwrdm1->name, | 622 | "dependency affecting %s from %s\n", pwrdm1->name, |
625 | pwrdm2->name); | 623 | pwrdm2->name); |
626 | return IS_ERR(p); | 624 | return PTR_ERR(p); |
627 | } | 625 | } |
628 | 626 | ||
629 | pr_debug("powerdomain: will no longer prevent %s from sleeping if " | 627 | pr_debug("powerdomain: will no longer prevent %s from sleeping if " |
@@ -655,10 +653,10 @@ int pwrdm_read_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2) | |||
655 | { | 653 | { |
656 | struct powerdomain *p; | 654 | struct powerdomain *p; |
657 | 655 | ||
658 | if (!pwrdm1) | 656 | if (!cpu_is_omap34xx()) |
659 | return -EINVAL; | 657 | return -EINVAL; |
660 | 658 | ||
661 | if (!cpu_is_omap34xx()) | 659 | if (!pwrdm1) |
662 | return -EINVAL; | 660 | return -EINVAL; |
663 | 661 | ||
664 | p = _pwrdm_deps_lookup(pwrdm2, pwrdm1->sleepdep_srcs); | 662 | p = _pwrdm_deps_lookup(pwrdm2, pwrdm1->sleepdep_srcs); |
@@ -666,7 +664,7 @@ int pwrdm_read_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2) | |||
666 | pr_debug("powerdomain: hardware cannot set/clear sleep " | 664 | pr_debug("powerdomain: hardware cannot set/clear sleep " |
667 | "dependency affecting %s from %s\n", pwrdm1->name, | 665 | "dependency affecting %s from %s\n", pwrdm1->name, |
668 | pwrdm2->name); | 666 | pwrdm2->name); |
669 | return IS_ERR(p); | 667 | return PTR_ERR(p); |
670 | } | 668 | } |
671 | 669 | ||
672 | return prm_read_mod_bits_shift(pwrdm1->prcm_offs, OMAP3430_CM_SLEEPDEP, | 670 | return prm_read_mod_bits_shift(pwrdm1->prcm_offs, OMAP3430_CM_SLEEPDEP, |
@@ -985,6 +983,9 @@ int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank) | |||
985 | if (pwrdm->banks < (bank + 1)) | 983 | if (pwrdm->banks < (bank + 1)) |
986 | return -EEXIST; | 984 | return -EEXIST; |
987 | 985 | ||
986 | if (pwrdm->flags & PWRDM_HAS_MPU_QUIRK) | ||
987 | bank = 1; | ||
988 | |||
988 | /* | 989 | /* |
989 | * The register bit names below may not correspond to the | 990 | * The register bit names below may not correspond to the |
990 | * actual names of the bits in each powerdomain's register, | 991 | * actual names of the bits in each powerdomain's register, |
@@ -1032,6 +1033,9 @@ int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank) | |||
1032 | if (pwrdm->banks < (bank + 1)) | 1033 | if (pwrdm->banks < (bank + 1)) |
1033 | return -EEXIST; | 1034 | return -EEXIST; |
1034 | 1035 | ||
1036 | if (pwrdm->flags & PWRDM_HAS_MPU_QUIRK) | ||
1037 | bank = 1; | ||
1038 | |||
1035 | /* | 1039 | /* |
1036 | * The register bit names below may not correspond to the | 1040 | * The register bit names below may not correspond to the |
1037 | * actual names of the bits in each powerdomain's register, | 1041 | * actual names of the bits in each powerdomain's register, |
diff --git a/arch/arm/mach-omap2/powerdomains34xx.h b/arch/arm/mach-omap2/powerdomains34xx.h index fd09b0827df0..588f7e07d0ea 100644 --- a/arch/arm/mach-omap2/powerdomains34xx.h +++ b/arch/arm/mach-omap2/powerdomains34xx.h | |||
@@ -190,6 +190,7 @@ static struct powerdomain mpu_34xx_pwrdm = { | |||
190 | .wkdep_srcs = mpu_34xx_wkdeps, | 190 | .wkdep_srcs = mpu_34xx_wkdeps, |
191 | .pwrsts = PWRSTS_OFF_RET_ON, | 191 | .pwrsts = PWRSTS_OFF_RET_ON, |
192 | .pwrsts_logic_ret = PWRSTS_OFF_RET, | 192 | .pwrsts_logic_ret = PWRSTS_OFF_RET, |
193 | .flags = PWRDM_HAS_MPU_QUIRK, | ||
193 | .banks = 1, | 194 | .banks = 1, |
194 | .pwrsts_mem_ret = { | 195 | .pwrsts_mem_ret = { |
195 | [0] = PWRSTS_OFF_RET, | 196 | [0] = PWRSTS_OFF_RET, |
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h index cb1ae84e0925..61ac2a418bd0 100644 --- a/arch/arm/mach-omap2/prcm-common.h +++ b/arch/arm/mach-omap2/prcm-common.h | |||
@@ -4,10 +4,12 @@ | |||
4 | /* | 4 | /* |
5 | * OMAP2/3 PRCM base and module definitions | 5 | * OMAP2/3 PRCM base and module definitions |
6 | * | 6 | * |
7 | * Copyright (C) 2007-2008 Texas Instruments, Inc. | 7 | * Copyright (C) 2007-2009 Texas Instruments, Inc. |
8 | * Copyright (C) 2007-2008 Nokia Corporation | 8 | * Copyright (C) 2007-2009 Nokia Corporation |
9 | * | 9 | * |
10 | * Written by Paul Walmsley | 10 | * Written by Paul Walmsley |
11 | * OMAP4 defines in this file are automatically generated from the OMAP hardware | ||
12 | * databases. | ||
11 | * | 13 | * |
12 | * This program is free software; you can redistribute it and/or modify | 14 | * This program is free software; you can redistribute it and/or modify |
13 | * it under the terms of the GNU General Public License version 2 as | 15 | * it under the terms of the GNU General Public License version 2 as |
@@ -49,6 +51,73 @@ | |||
49 | #define OMAP3430_NEON_MOD 0xb00 | 51 | #define OMAP3430_NEON_MOD 0xb00 |
50 | #define OMAP3430ES2_USBHOST_MOD 0xc00 | 52 | #define OMAP3430ES2_USBHOST_MOD 0xc00 |
51 | 53 | ||
54 | #define BITS(n_bit) \ | ||
55 | (((1 << n_bit) - 1) | (1 << n_bit)) | ||
56 | |||
57 | #define BITFIELD(l_bit, u_bit) \ | ||
58 | (BITS(u_bit) & ~((BITS(l_bit)) >> 1)) | ||
59 | |||
60 | /* OMAP44XX specific module offsets */ | ||
61 | |||
62 | /* CM1 instances */ | ||
63 | |||
64 | #define OMAP4430_CM1_OCP_SOCKET_MOD 0x0000 | ||
65 | #define OMAP4430_CM1_CKGEN_MOD 0x0100 | ||
66 | #define OMAP4430_CM1_MPU_MOD 0x0300 | ||
67 | #define OMAP4430_CM1_TESLA_MOD 0x0400 | ||
68 | #define OMAP4430_CM1_ABE_MOD 0x0500 | ||
69 | #define OMAP4430_CM1_RESTORE_MOD 0x0e00 | ||
70 | #define OMAP4430_CM1_INSTR_MOD 0x0f00 | ||
71 | |||
72 | /* CM2 instances */ | ||
73 | |||
74 | #define OMAP4430_CM2_OCP_SOCKET_MOD 0x0000 | ||
75 | #define OMAP4430_CM2_CKGEN_MOD 0x0100 | ||
76 | #define OMAP4430_CM2_ALWAYS_ON_MOD 0x0600 | ||
77 | #define OMAP4430_CM2_CORE_MOD 0x0700 | ||
78 | #define OMAP4430_CM2_IVAHD_MOD 0x0f00 | ||
79 | #define OMAP4430_CM2_CAM_MOD 0x1000 | ||
80 | #define OMAP4430_CM2_DSS_MOD 0x1100 | ||
81 | #define OMAP4430_CM2_GFX_MOD 0x1200 | ||
82 | #define OMAP4430_CM2_L3INIT_MOD 0x1300 | ||
83 | #define OMAP4430_CM2_L4PER_MOD 0x1400 | ||
84 | #define OMAP4430_CM2_CEFUSE_MOD 0x1600 | ||
85 | #define OMAP4430_CM2_RESTORE_MOD 0x1e00 | ||
86 | #define OMAP4430_CM2_INSTR_MOD 0x1f00 | ||
87 | |||
88 | /* PRM instances */ | ||
89 | |||
90 | #define OMAP4430_PRM_OCP_SOCKET_MOD 0x0000 | ||
91 | #define OMAP4430_PRM_CKGEN_MOD 0x0100 | ||
92 | #define OMAP4430_PRM_MPU_MOD 0x0300 | ||
93 | #define OMAP4430_PRM_TESLA_MOD 0x0400 | ||
94 | #define OMAP4430_PRM_ABE_MOD 0x0500 | ||
95 | #define OMAP4430_PRM_ALWAYS_ON_MOD 0x0600 | ||
96 | #define OMAP4430_PRM_CORE_MOD 0x0700 | ||
97 | #define OMAP4430_PRM_IVAHD_MOD 0x0f00 | ||
98 | #define OMAP4430_PRM_CAM_MOD 0x1000 | ||
99 | #define OMAP4430_PRM_DSS_MOD 0x1100 | ||
100 | #define OMAP4430_PRM_GFX_MOD 0x1200 | ||
101 | #define OMAP4430_PRM_L3INIT_MOD 0x1300 | ||
102 | #define OMAP4430_PRM_L4PER_MOD 0x1400 | ||
103 | #define OMAP4430_PRM_CEFUSE_MOD 0x1600 | ||
104 | #define OMAP4430_PRM_WKUP_MOD 0x1700 | ||
105 | #define OMAP4430_PRM_WKUP_CM_MOD 0x1800 | ||
106 | #define OMAP4430_PRM_EMU_MOD 0x1900 | ||
107 | #define OMAP4430_PRM_EMU_CM_MOD 0x1a00 | ||
108 | #define OMAP4430_PRM_DEVICE_MOD 0x1b00 | ||
109 | #define OMAP4430_PRM_INSTR_MOD 0x1f00 | ||
110 | |||
111 | /* SCRM instances */ | ||
112 | |||
113 | #define OMAP4430_SCRM_SCRM_MOD 0x0000 | ||
114 | |||
115 | /* CHIRONSS instances */ | ||
116 | |||
117 | #define OMAP4430_CHIRONSS_CHIRONSS_OCP_SOCKET_PRCM_MOD 0x0000 | ||
118 | #define OMAP4430_CHIRONSS_CHIRONSS_DEVICE_PRM_MOD 0x0200 | ||
119 | #define OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD 0x0400 | ||
120 | #define OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD 0x0800 | ||
52 | 121 | ||
53 | /* 24XX register bits shared between CM & PRM registers */ | 122 | /* 24XX register bits shared between CM & PRM registers */ |
54 | 123 | ||
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c index 029d376198d4..3ea8177ffb25 100644 --- a/arch/arm/mach-omap2/prcm.c +++ b/arch/arm/mach-omap2/prcm.c | |||
@@ -34,6 +34,7 @@ | |||
34 | 34 | ||
35 | static void __iomem *prm_base; | 35 | static void __iomem *prm_base; |
36 | static void __iomem *cm_base; | 36 | static void __iomem *cm_base; |
37 | static void __iomem *cm2_base; | ||
37 | 38 | ||
38 | #define MAX_MODULE_ENABLE_WAIT 100000 | 39 | #define MAX_MODULE_ENABLE_WAIT 100000 |
39 | 40 | ||
@@ -170,14 +171,12 @@ u32 prm_read_mod_reg(s16 module, u16 idx) | |||
170 | { | 171 | { |
171 | return __omap_prcm_read(prm_base, module, idx); | 172 | return __omap_prcm_read(prm_base, module, idx); |
172 | } | 173 | } |
173 | EXPORT_SYMBOL(prm_read_mod_reg); | ||
174 | 174 | ||
175 | /* Write into a register in a PRM module */ | 175 | /* Write into a register in a PRM module */ |
176 | void prm_write_mod_reg(u32 val, s16 module, u16 idx) | 176 | void prm_write_mod_reg(u32 val, s16 module, u16 idx) |
177 | { | 177 | { |
178 | __omap_prcm_write(val, prm_base, module, idx); | 178 | __omap_prcm_write(val, prm_base, module, idx); |
179 | } | 179 | } |
180 | EXPORT_SYMBOL(prm_write_mod_reg); | ||
181 | 180 | ||
182 | /* Read-modify-write a register in a PRM module. Caller must lock */ | 181 | /* Read-modify-write a register in a PRM module. Caller must lock */ |
183 | u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx) | 182 | u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx) |
@@ -191,21 +190,18 @@ u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx) | |||
191 | 190 | ||
192 | return v; | 191 | return v; |
193 | } | 192 | } |
194 | EXPORT_SYMBOL(prm_rmw_mod_reg_bits); | ||
195 | 193 | ||
196 | /* Read a register in a CM module */ | 194 | /* Read a register in a CM module */ |
197 | u32 cm_read_mod_reg(s16 module, u16 idx) | 195 | u32 cm_read_mod_reg(s16 module, u16 idx) |
198 | { | 196 | { |
199 | return __omap_prcm_read(cm_base, module, idx); | 197 | return __omap_prcm_read(cm_base, module, idx); |
200 | } | 198 | } |
201 | EXPORT_SYMBOL(cm_read_mod_reg); | ||
202 | 199 | ||
203 | /* Write into a register in a CM module */ | 200 | /* Write into a register in a CM module */ |
204 | void cm_write_mod_reg(u32 val, s16 module, u16 idx) | 201 | void cm_write_mod_reg(u32 val, s16 module, u16 idx) |
205 | { | 202 | { |
206 | __omap_prcm_write(val, cm_base, module, idx); | 203 | __omap_prcm_write(val, cm_base, module, idx); |
207 | } | 204 | } |
208 | EXPORT_SYMBOL(cm_write_mod_reg); | ||
209 | 205 | ||
210 | /* Read-modify-write a register in a CM module. Caller must lock */ | 206 | /* Read-modify-write a register in a CM module. Caller must lock */ |
211 | u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx) | 207 | u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx) |
@@ -219,7 +215,6 @@ u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx) | |||
219 | 215 | ||
220 | return v; | 216 | return v; |
221 | } | 217 | } |
222 | EXPORT_SYMBOL(cm_rmw_mod_reg_bits); | ||
223 | 218 | ||
224 | /** | 219 | /** |
225 | * omap2_cm_wait_idlest - wait for IDLEST bit to indicate module readiness | 220 | * omap2_cm_wait_idlest - wait for IDLEST bit to indicate module readiness |
@@ -247,9 +242,8 @@ int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, const char *name) | |||
247 | BUG(); | 242 | BUG(); |
248 | 243 | ||
249 | /* Wait for lock */ | 244 | /* Wait for lock */ |
250 | while (((__raw_readl(reg) & mask) != ena) && | 245 | omap_test_timeout(((__raw_readl(reg) & mask) == ena), |
251 | (i++ < MAX_MODULE_ENABLE_WAIT)) | 246 | MAX_MODULE_ENABLE_WAIT, i); |
252 | udelay(1); | ||
253 | 247 | ||
254 | if (i < MAX_MODULE_ENABLE_WAIT) | 248 | if (i < MAX_MODULE_ENABLE_WAIT) |
255 | pr_debug("cm: Module associated with clock %s ready after %d " | 249 | pr_debug("cm: Module associated with clock %s ready after %d " |
@@ -265,6 +259,7 @@ void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals) | |||
265 | { | 259 | { |
266 | prm_base = omap2_globals->prm; | 260 | prm_base = omap2_globals->prm; |
267 | cm_base = omap2_globals->cm; | 261 | cm_base = omap2_globals->cm; |
262 | cm2_base = omap2_globals->cm2; | ||
268 | } | 263 | } |
269 | 264 | ||
270 | #ifdef CONFIG_ARCH_OMAP3 | 265 | #ifdef CONFIG_ARCH_OMAP3 |
diff --git a/arch/arm/mach-omap2/prm-regbits-44xx.h b/arch/arm/mach-omap2/prm-regbits-44xx.h new file mode 100644 index 000000000000..301c810fb269 --- /dev/null +++ b/arch/arm/mach-omap2/prm-regbits-44xx.h | |||
@@ -0,0 +1,2205 @@ | |||
1 | /* | ||
2 | * OMAP44xx Power Management register bits | ||
3 | * | ||
4 | * Copyright (C) 2009 Texas Instruments, Inc. | ||
5 | * Copyright (C) 2009 Nokia Corporation | ||
6 | * | ||
7 | * Paul Walmsley (paul@pwsan.com) | ||
8 | * Rajendra Nayak (rnayak@ti.com) | ||
9 | * Benoit Cousson (b-cousson@ti.com) | ||
10 | * | ||
11 | * This file is automatically generated from the OMAP hardware databases. | ||
12 | * We respectfully ask that any modifications to this file be coordinated | ||
13 | * with the public linux-omap@vger.kernel.org mailing list and the | ||
14 | * authors above to ensure that the autogeneration scripts are kept | ||
15 | * up-to-date with the file contents. | ||
16 | * | ||
17 | * This program is free software; you can redistribute it and/or modify | ||
18 | * it under the terms of the GNU General Public License version 2 as | ||
19 | * published by the Free Software Foundation. | ||
20 | */ | ||
21 | |||
22 | #ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H | ||
23 | #define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H | ||
24 | |||
25 | #include "prm.h" | ||
26 | |||
27 | |||
28 | /* | ||
29 | * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, | ||
30 | * PRM_LDO_SRAM_MPU_SETUP | ||
31 | */ | ||
32 | #define OMAP4430_ABBOFF_ACT_EXPORT_SHIFT (1 << 1) | ||
33 | #define OMAP4430_ABBOFF_ACT_EXPORT_MASK BITFIELD(1, 1) | ||
34 | |||
35 | /* | ||
36 | * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, | ||
37 | * PRM_LDO_SRAM_MPU_SETUP | ||
38 | */ | ||
39 | #define OMAP4430_ABBOFF_SLEEP_EXPORT_SHIFT (1 << 2) | ||
40 | #define OMAP4430_ABBOFF_SLEEP_EXPORT_MASK BITFIELD(2, 2) | ||
41 | |||
42 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | ||
43 | #define OMAP4430_ABB_IVA_DONE_EN_SHIFT (1 << 31) | ||
44 | #define OMAP4430_ABB_IVA_DONE_EN_MASK BITFIELD(31, 31) | ||
45 | |||
46 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | ||
47 | #define OMAP4430_ABB_IVA_DONE_ST_SHIFT (1 << 31) | ||
48 | #define OMAP4430_ABB_IVA_DONE_ST_MASK BITFIELD(31, 31) | ||
49 | |||
50 | /* Used by PRM_IRQENABLE_MPU_2 */ | ||
51 | #define OMAP4430_ABB_MPU_DONE_EN_SHIFT (1 << 7) | ||
52 | #define OMAP4430_ABB_MPU_DONE_EN_MASK BITFIELD(7, 7) | ||
53 | |||
54 | /* Used by PRM_IRQSTATUS_MPU_2 */ | ||
55 | #define OMAP4430_ABB_MPU_DONE_ST_SHIFT (1 << 7) | ||
56 | #define OMAP4430_ABB_MPU_DONE_ST_MASK BITFIELD(7, 7) | ||
57 | |||
58 | /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ | ||
59 | #define OMAP4430_ACTIVE_FBB_SEL_SHIFT (1 << 2) | ||
60 | #define OMAP4430_ACTIVE_FBB_SEL_MASK BITFIELD(2, 2) | ||
61 | |||
62 | /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ | ||
63 | #define OMAP4430_ACTIVE_RBB_SEL_SHIFT (1 << 1) | ||
64 | #define OMAP4430_ACTIVE_RBB_SEL_MASK BITFIELD(1, 1) | ||
65 | |||
66 | /* Used by PM_ABE_PWRSTCTRL */ | ||
67 | #define OMAP4430_AESSMEM_ONSTATE_SHIFT (1 << 16) | ||
68 | #define OMAP4430_AESSMEM_ONSTATE_MASK BITFIELD(16, 17) | ||
69 | |||
70 | /* Used by PM_ABE_PWRSTCTRL */ | ||
71 | #define OMAP4430_AESSMEM_RETSTATE_SHIFT (1 << 8) | ||
72 | #define OMAP4430_AESSMEM_RETSTATE_MASK BITFIELD(8, 8) | ||
73 | |||
74 | /* Used by PM_ABE_PWRSTST */ | ||
75 | #define OMAP4430_AESSMEM_STATEST_SHIFT (1 << 4) | ||
76 | #define OMAP4430_AESSMEM_STATEST_MASK BITFIELD(4, 5) | ||
77 | |||
78 | /* | ||
79 | * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, | ||
80 | * PRM_LDO_SRAM_MPU_SETUP | ||
81 | */ | ||
82 | #define OMAP4430_AIPOFF_SHIFT (1 << 8) | ||
83 | #define OMAP4430_AIPOFF_MASK BITFIELD(8, 8) | ||
84 | |||
85 | /* Used by PRM_VOLTCTRL */ | ||
86 | #define OMAP4430_AUTO_CTRL_VDD_CORE_L_SHIFT (1 << 0) | ||
87 | #define OMAP4430_AUTO_CTRL_VDD_CORE_L_MASK BITFIELD(0, 1) | ||
88 | |||
89 | /* Used by PRM_VOLTCTRL */ | ||
90 | #define OMAP4430_AUTO_CTRL_VDD_IVA_L_SHIFT (1 << 4) | ||
91 | #define OMAP4430_AUTO_CTRL_VDD_IVA_L_MASK BITFIELD(4, 5) | ||
92 | |||
93 | /* Used by PRM_VOLTCTRL */ | ||
94 | #define OMAP4430_AUTO_CTRL_VDD_MPU_L_SHIFT (1 << 2) | ||
95 | #define OMAP4430_AUTO_CTRL_VDD_MPU_L_MASK BITFIELD(2, 3) | ||
96 | |||
97 | /* Used by PM_CAM_PWRSTCTRL */ | ||
98 | #define OMAP4430_CAM_MEM_ONSTATE_SHIFT (1 << 16) | ||
99 | #define OMAP4430_CAM_MEM_ONSTATE_MASK BITFIELD(16, 17) | ||
100 | |||
101 | /* Used by PM_CAM_PWRSTST */ | ||
102 | #define OMAP4430_CAM_MEM_STATEST_SHIFT (1 << 4) | ||
103 | #define OMAP4430_CAM_MEM_STATEST_MASK BITFIELD(4, 5) | ||
104 | |||
105 | /* Used by PRM_CLKREQCTRL */ | ||
106 | #define OMAP4430_CLKREQ_COND_SHIFT (1 << 0) | ||
107 | #define OMAP4430_CLKREQ_COND_MASK BITFIELD(0, 2) | ||
108 | |||
109 | /* Used by PRM_VC_VAL_SMPS_RA_CMD */ | ||
110 | #define OMAP4430_CMDRA_VDD_CORE_L_SHIFT (1 << 0) | ||
111 | #define OMAP4430_CMDRA_VDD_CORE_L_MASK BITFIELD(0, 7) | ||
112 | |||
113 | /* Used by PRM_VC_VAL_SMPS_RA_CMD */ | ||
114 | #define OMAP4430_CMDRA_VDD_IVA_L_SHIFT (1 << 8) | ||
115 | #define OMAP4430_CMDRA_VDD_IVA_L_MASK BITFIELD(8, 15) | ||
116 | |||
117 | /* Used by PRM_VC_VAL_SMPS_RA_CMD */ | ||
118 | #define OMAP4430_CMDRA_VDD_MPU_L_SHIFT (1 << 16) | ||
119 | #define OMAP4430_CMDRA_VDD_MPU_L_MASK BITFIELD(16, 23) | ||
120 | |||
121 | /* Used by PRM_VC_CFG_CHANNEL */ | ||
122 | #define OMAP4430_CMD_VDD_CORE_L_SHIFT (1 << 4) | ||
123 | #define OMAP4430_CMD_VDD_CORE_L_MASK BITFIELD(4, 4) | ||
124 | |||
125 | /* Used by PRM_VC_CFG_CHANNEL */ | ||
126 | #define OMAP4430_CMD_VDD_IVA_L_SHIFT (1 << 12) | ||
127 | #define OMAP4430_CMD_VDD_IVA_L_MASK BITFIELD(12, 12) | ||
128 | |||
129 | /* Used by PRM_VC_CFG_CHANNEL */ | ||
130 | #define OMAP4430_CMD_VDD_MPU_L_SHIFT (1 << 17) | ||
131 | #define OMAP4430_CMD_VDD_MPU_L_MASK BITFIELD(17, 17) | ||
132 | |||
133 | /* Used by PM_CORE_PWRSTCTRL */ | ||
134 | #define OMAP4430_CORE_OCMRAM_ONSTATE_SHIFT (1 << 18) | ||
135 | #define OMAP4430_CORE_OCMRAM_ONSTATE_MASK BITFIELD(18, 19) | ||
136 | |||
137 | /* Used by PM_CORE_PWRSTCTRL */ | ||
138 | #define OMAP4430_CORE_OCMRAM_RETSTATE_SHIFT (1 << 9) | ||
139 | #define OMAP4430_CORE_OCMRAM_RETSTATE_MASK BITFIELD(9, 9) | ||
140 | |||
141 | /* Used by PM_CORE_PWRSTST */ | ||
142 | #define OMAP4430_CORE_OCMRAM_STATEST_SHIFT (1 << 6) | ||
143 | #define OMAP4430_CORE_OCMRAM_STATEST_MASK BITFIELD(6, 7) | ||
144 | |||
145 | /* Used by PM_CORE_PWRSTCTRL */ | ||
146 | #define OMAP4430_CORE_OTHER_BANK_ONSTATE_SHIFT (1 << 16) | ||
147 | #define OMAP4430_CORE_OTHER_BANK_ONSTATE_MASK BITFIELD(16, 17) | ||
148 | |||
149 | /* Used by PM_CORE_PWRSTCTRL */ | ||
150 | #define OMAP4430_CORE_OTHER_BANK_RETSTATE_SHIFT (1 << 8) | ||
151 | #define OMAP4430_CORE_OTHER_BANK_RETSTATE_MASK BITFIELD(8, 8) | ||
152 | |||
153 | /* Used by PM_CORE_PWRSTST */ | ||
154 | #define OMAP4430_CORE_OTHER_BANK_STATEST_SHIFT (1 << 4) | ||
155 | #define OMAP4430_CORE_OTHER_BANK_STATEST_MASK BITFIELD(4, 5) | ||
156 | |||
157 | /* Used by PRM_VC_VAL_BYPASS */ | ||
158 | #define OMAP4430_DATA_SHIFT (1 << 16) | ||
159 | #define OMAP4430_DATA_MASK BITFIELD(16, 23) | ||
160 | |||
161 | /* Used by PRM_DEVICE_OFF_CTRL */ | ||
162 | #define OMAP4430_DEVICE_OFF_ENABLE_SHIFT (1 << 0) | ||
163 | #define OMAP4430_DEVICE_OFF_ENABLE_MASK BITFIELD(0, 0) | ||
164 | |||
165 | /* Used by PRM_VC_CFG_I2C_MODE */ | ||
166 | #define OMAP4430_DFILTEREN_SHIFT (1 << 6) | ||
167 | #define OMAP4430_DFILTEREN_MASK BITFIELD(6, 6) | ||
168 | |||
169 | /* Used by PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */ | ||
170 | #define OMAP4430_DPLL_ABE_RECAL_EN_SHIFT (1 << 4) | ||
171 | #define OMAP4430_DPLL_ABE_RECAL_EN_MASK BITFIELD(4, 4) | ||
172 | |||
173 | /* Used by PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */ | ||
174 | #define OMAP4430_DPLL_ABE_RECAL_ST_SHIFT (1 << 4) | ||
175 | #define OMAP4430_DPLL_ABE_RECAL_ST_MASK BITFIELD(4, 4) | ||
176 | |||
177 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | ||
178 | #define OMAP4430_DPLL_CORE_RECAL_EN_SHIFT (1 << 0) | ||
179 | #define OMAP4430_DPLL_CORE_RECAL_EN_MASK BITFIELD(0, 0) | ||
180 | |||
181 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | ||
182 | #define OMAP4430_DPLL_CORE_RECAL_ST_SHIFT (1 << 0) | ||
183 | #define OMAP4430_DPLL_CORE_RECAL_ST_MASK BITFIELD(0, 0) | ||
184 | |||
185 | /* Used by PRM_IRQENABLE_MPU */ | ||
186 | #define OMAP4430_DPLL_DDRPHY_RECAL_EN_SHIFT (1 << 6) | ||
187 | #define OMAP4430_DPLL_DDRPHY_RECAL_EN_MASK BITFIELD(6, 6) | ||
188 | |||
189 | /* Used by PRM_IRQSTATUS_MPU */ | ||
190 | #define OMAP4430_DPLL_DDRPHY_RECAL_ST_SHIFT (1 << 6) | ||
191 | #define OMAP4430_DPLL_DDRPHY_RECAL_ST_MASK BITFIELD(6, 6) | ||
192 | |||
193 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */ | ||
194 | #define OMAP4430_DPLL_IVA_RECAL_EN_SHIFT (1 << 2) | ||
195 | #define OMAP4430_DPLL_IVA_RECAL_EN_MASK BITFIELD(2, 2) | ||
196 | |||
197 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */ | ||
198 | #define OMAP4430_DPLL_IVA_RECAL_ST_SHIFT (1 << 2) | ||
199 | #define OMAP4430_DPLL_IVA_RECAL_ST_MASK BITFIELD(2, 2) | ||
200 | |||
201 | /* Used by PRM_IRQENABLE_MPU */ | ||
202 | #define OMAP4430_DPLL_MPU_RECAL_EN_SHIFT (1 << 1) | ||
203 | #define OMAP4430_DPLL_MPU_RECAL_EN_MASK BITFIELD(1, 1) | ||
204 | |||
205 | /* Used by PRM_IRQSTATUS_MPU */ | ||
206 | #define OMAP4430_DPLL_MPU_RECAL_ST_SHIFT (1 << 1) | ||
207 | #define OMAP4430_DPLL_MPU_RECAL_ST_MASK BITFIELD(1, 1) | ||
208 | |||
209 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | ||
210 | #define OMAP4430_DPLL_PER_RECAL_EN_SHIFT (1 << 3) | ||
211 | #define OMAP4430_DPLL_PER_RECAL_EN_MASK BITFIELD(3, 3) | ||
212 | |||
213 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | ||
214 | #define OMAP4430_DPLL_PER_RECAL_ST_SHIFT (1 << 3) | ||
215 | #define OMAP4430_DPLL_PER_RECAL_ST_MASK BITFIELD(3, 3) | ||
216 | |||
217 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | ||
218 | #define OMAP4430_DPLL_UNIPRO_RECAL_EN_SHIFT (1 << 7) | ||
219 | #define OMAP4430_DPLL_UNIPRO_RECAL_EN_MASK BITFIELD(7, 7) | ||
220 | |||
221 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | ||
222 | #define OMAP4430_DPLL_UNIPRO_RECAL_ST_SHIFT (1 << 7) | ||
223 | #define OMAP4430_DPLL_UNIPRO_RECAL_ST_MASK BITFIELD(7, 7) | ||
224 | |||
225 | /* Used by PRM_IRQENABLE_MPU */ | ||
226 | #define OMAP4430_DPLL_USB_RECAL_EN_SHIFT (1 << 5) | ||
227 | #define OMAP4430_DPLL_USB_RECAL_EN_MASK BITFIELD(5, 5) | ||
228 | |||
229 | /* Used by PRM_IRQSTATUS_MPU */ | ||
230 | #define OMAP4430_DPLL_USB_RECAL_ST_SHIFT (1 << 5) | ||
231 | #define OMAP4430_DPLL_USB_RECAL_ST_MASK BITFIELD(5, 5) | ||
232 | |||
233 | /* Used by PM_DSS_PWRSTCTRL */ | ||
234 | #define OMAP4430_DSS_MEM_ONSTATE_SHIFT (1 << 16) | ||
235 | #define OMAP4430_DSS_MEM_ONSTATE_MASK BITFIELD(16, 17) | ||
236 | |||
237 | /* Used by PM_DSS_PWRSTCTRL */ | ||
238 | #define OMAP4430_DSS_MEM_RETSTATE_SHIFT (1 << 8) | ||
239 | #define OMAP4430_DSS_MEM_RETSTATE_MASK BITFIELD(8, 8) | ||
240 | |||
241 | /* Used by PM_DSS_PWRSTST */ | ||
242 | #define OMAP4430_DSS_MEM_STATEST_SHIFT (1 << 4) | ||
243 | #define OMAP4430_DSS_MEM_STATEST_MASK BITFIELD(4, 5) | ||
244 | |||
245 | /* Used by PM_CORE_PWRSTCTRL */ | ||
246 | #define OMAP4430_DUCATI_L2RAM_ONSTATE_SHIFT (1 << 20) | ||
247 | #define OMAP4430_DUCATI_L2RAM_ONSTATE_MASK BITFIELD(20, 21) | ||
248 | |||
249 | /* Used by PM_CORE_PWRSTCTRL */ | ||
250 | #define OMAP4430_DUCATI_L2RAM_RETSTATE_SHIFT (1 << 10) | ||
251 | #define OMAP4430_DUCATI_L2RAM_RETSTATE_MASK BITFIELD(10, 10) | ||
252 | |||
253 | /* Used by PM_CORE_PWRSTST */ | ||
254 | #define OMAP4430_DUCATI_L2RAM_STATEST_SHIFT (1 << 8) | ||
255 | #define OMAP4430_DUCATI_L2RAM_STATEST_MASK BITFIELD(8, 9) | ||
256 | |||
257 | /* Used by PM_CORE_PWRSTCTRL */ | ||
258 | #define OMAP4430_DUCATI_UNICACHE_ONSTATE_SHIFT (1 << 22) | ||
259 | #define OMAP4430_DUCATI_UNICACHE_ONSTATE_MASK BITFIELD(22, 23) | ||
260 | |||
261 | /* Used by PM_CORE_PWRSTCTRL */ | ||
262 | #define OMAP4430_DUCATI_UNICACHE_RETSTATE_SHIFT (1 << 11) | ||
263 | #define OMAP4430_DUCATI_UNICACHE_RETSTATE_MASK BITFIELD(11, 11) | ||
264 | |||
265 | /* Used by PM_CORE_PWRSTST */ | ||
266 | #define OMAP4430_DUCATI_UNICACHE_STATEST_SHIFT (1 << 10) | ||
267 | #define OMAP4430_DUCATI_UNICACHE_STATEST_MASK BITFIELD(10, 11) | ||
268 | |||
269 | /* Used by RM_MPU_RSTST */ | ||
270 | #define OMAP4430_EMULATION_RST_SHIFT (1 << 0) | ||
271 | #define OMAP4430_EMULATION_RST_MASK BITFIELD(0, 0) | ||
272 | |||
273 | /* Used by RM_DUCATI_RSTST */ | ||
274 | #define OMAP4430_EMULATION_RST1ST_SHIFT (1 << 3) | ||
275 | #define OMAP4430_EMULATION_RST1ST_MASK BITFIELD(3, 3) | ||
276 | |||
277 | /* Used by RM_DUCATI_RSTST */ | ||
278 | #define OMAP4430_EMULATION_RST2ST_SHIFT (1 << 4) | ||
279 | #define OMAP4430_EMULATION_RST2ST_MASK BITFIELD(4, 4) | ||
280 | |||
281 | /* Used by RM_IVAHD_RSTST */ | ||
282 | #define OMAP4430_EMULATION_SEQ1_RST1ST_SHIFT (1 << 3) | ||
283 | #define OMAP4430_EMULATION_SEQ1_RST1ST_MASK BITFIELD(3, 3) | ||
284 | |||
285 | /* Used by RM_IVAHD_RSTST */ | ||
286 | #define OMAP4430_EMULATION_SEQ2_RST2ST_SHIFT (1 << 4) | ||
287 | #define OMAP4430_EMULATION_SEQ2_RST2ST_MASK BITFIELD(4, 4) | ||
288 | |||
289 | /* Used by PM_EMU_PWRSTCTRL */ | ||
290 | #define OMAP4430_EMU_BANK_ONSTATE_SHIFT (1 << 16) | ||
291 | #define OMAP4430_EMU_BANK_ONSTATE_MASK BITFIELD(16, 17) | ||
292 | |||
293 | /* Used by PM_EMU_PWRSTST */ | ||
294 | #define OMAP4430_EMU_BANK_STATEST_SHIFT (1 << 4) | ||
295 | #define OMAP4430_EMU_BANK_STATEST_MASK BITFIELD(4, 5) | ||
296 | |||
297 | /* | ||
298 | * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, | ||
299 | * PRM_LDO_SRAM_MPU_SETUP, PRM_SRAM_WKUP_SETUP | ||
300 | */ | ||
301 | #define OMAP4430_ENABLE_RTA_EXPORT_SHIFT (1 << 0) | ||
302 | #define OMAP4430_ENABLE_RTA_EXPORT_MASK BITFIELD(0, 0) | ||
303 | |||
304 | /* | ||
305 | * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, | ||
306 | * PRM_LDO_SRAM_MPU_SETUP | ||
307 | */ | ||
308 | #define OMAP4430_ENFUNC1_SHIFT (1 << 3) | ||
309 | #define OMAP4430_ENFUNC1_MASK BITFIELD(3, 3) | ||
310 | |||
311 | /* | ||
312 | * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, | ||
313 | * PRM_LDO_SRAM_MPU_SETUP | ||
314 | */ | ||
315 | #define OMAP4430_ENFUNC3_SHIFT (1 << 5) | ||
316 | #define OMAP4430_ENFUNC3_MASK BITFIELD(5, 5) | ||
317 | |||
318 | /* | ||
319 | * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, | ||
320 | * PRM_LDO_SRAM_MPU_SETUP | ||
321 | */ | ||
322 | #define OMAP4430_ENFUNC4_SHIFT (1 << 6) | ||
323 | #define OMAP4430_ENFUNC4_MASK BITFIELD(6, 6) | ||
324 | |||
325 | /* | ||
326 | * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, | ||
327 | * PRM_LDO_SRAM_MPU_SETUP | ||
328 | */ | ||
329 | #define OMAP4430_ENFUNC5_SHIFT (1 << 7) | ||
330 | #define OMAP4430_ENFUNC5_MASK BITFIELD(7, 7) | ||
331 | |||
332 | /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ | ||
333 | #define OMAP4430_ERRORGAIN_SHIFT (1 << 16) | ||
334 | #define OMAP4430_ERRORGAIN_MASK BITFIELD(16, 23) | ||
335 | |||
336 | /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ | ||
337 | #define OMAP4430_ERROROFFSET_SHIFT (1 << 24) | ||
338 | #define OMAP4430_ERROROFFSET_MASK BITFIELD(24, 31) | ||
339 | |||
340 | /* Used by PRM_RSTST */ | ||
341 | #define OMAP4430_EXTERNAL_WARM_RST_SHIFT (1 << 5) | ||
342 | #define OMAP4430_EXTERNAL_WARM_RST_MASK BITFIELD(5, 5) | ||
343 | |||
344 | /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ | ||
345 | #define OMAP4430_FORCEUPDATE_SHIFT (1 << 1) | ||
346 | #define OMAP4430_FORCEUPDATE_MASK BITFIELD(1, 1) | ||
347 | |||
348 | /* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_IVA_VOLTAGE, PRM_VP_MPU_VOLTAGE */ | ||
349 | #define OMAP4430_FORCEUPDATEWAIT_SHIFT (1 << 8) | ||
350 | #define OMAP4430_FORCEUPDATEWAIT_MASK BITFIELD(8, 31) | ||
351 | |||
352 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_TESLA */ | ||
353 | #define OMAP4430_FORCEWKUP_EN_SHIFT (1 << 10) | ||
354 | #define OMAP4430_FORCEWKUP_EN_MASK BITFIELD(10, 10) | ||
355 | |||
356 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_TESLA */ | ||
357 | #define OMAP4430_FORCEWKUP_ST_SHIFT (1 << 10) | ||
358 | #define OMAP4430_FORCEWKUP_ST_MASK BITFIELD(10, 10) | ||
359 | |||
360 | /* Used by PM_GFX_PWRSTCTRL */ | ||
361 | #define OMAP4430_GFX_MEM_ONSTATE_SHIFT (1 << 16) | ||
362 | #define OMAP4430_GFX_MEM_ONSTATE_MASK BITFIELD(16, 17) | ||
363 | |||
364 | /* Used by PM_GFX_PWRSTST */ | ||
365 | #define OMAP4430_GFX_MEM_STATEST_SHIFT (1 << 4) | ||
366 | #define OMAP4430_GFX_MEM_STATEST_MASK BITFIELD(4, 5) | ||
367 | |||
368 | /* Used by PRM_RSTST */ | ||
369 | #define OMAP4430_GLOBAL_COLD_RST_SHIFT (1 << 0) | ||
370 | #define OMAP4430_GLOBAL_COLD_RST_MASK BITFIELD(0, 0) | ||
371 | |||
372 | /* Used by PRM_RSTST */ | ||
373 | #define OMAP4430_GLOBAL_WARM_SW_RST_SHIFT (1 << 1) | ||
374 | #define OMAP4430_GLOBAL_WARM_SW_RST_MASK BITFIELD(1, 1) | ||
375 | |||
376 | /* Used by PRM_IO_PMCTRL */ | ||
377 | #define OMAP4430_GLOBAL_WUEN_SHIFT (1 << 16) | ||
378 | #define OMAP4430_GLOBAL_WUEN_MASK BITFIELD(16, 16) | ||
379 | |||
380 | /* Used by PRM_VC_CFG_I2C_MODE */ | ||
381 | #define OMAP4430_HSMCODE_SHIFT (1 << 0) | ||
382 | #define OMAP4430_HSMCODE_MASK BITFIELD(0, 2) | ||
383 | |||
384 | /* Used by PRM_VC_CFG_I2C_MODE */ | ||
385 | #define OMAP4430_HSMODEEN_SHIFT (1 << 3) | ||
386 | #define OMAP4430_HSMODEEN_MASK BITFIELD(3, 3) | ||
387 | |||
388 | /* Used by PRM_VC_CFG_I2C_CLK */ | ||
389 | #define OMAP4430_HSSCLH_SHIFT (1 << 16) | ||
390 | #define OMAP4430_HSSCLH_MASK BITFIELD(16, 23) | ||
391 | |||
392 | /* Used by PRM_VC_CFG_I2C_CLK */ | ||
393 | #define OMAP4430_HSSCLL_SHIFT (1 << 24) | ||
394 | #define OMAP4430_HSSCLL_MASK BITFIELD(24, 31) | ||
395 | |||
396 | /* Used by PM_IVAHD_PWRSTCTRL */ | ||
397 | #define OMAP4430_HWA_MEM_ONSTATE_SHIFT (1 << 16) | ||
398 | #define OMAP4430_HWA_MEM_ONSTATE_MASK BITFIELD(16, 17) | ||
399 | |||
400 | /* Used by PM_IVAHD_PWRSTCTRL */ | ||
401 | #define OMAP4430_HWA_MEM_RETSTATE_SHIFT (1 << 8) | ||
402 | #define OMAP4430_HWA_MEM_RETSTATE_MASK BITFIELD(8, 8) | ||
403 | |||
404 | /* Used by PM_IVAHD_PWRSTST */ | ||
405 | #define OMAP4430_HWA_MEM_STATEST_SHIFT (1 << 4) | ||
406 | #define OMAP4430_HWA_MEM_STATEST_MASK BITFIELD(4, 5) | ||
407 | |||
408 | /* Used by RM_MPU_RSTST */ | ||
409 | #define OMAP4430_ICECRUSHER_MPU_RST_SHIFT (1 << 1) | ||
410 | #define OMAP4430_ICECRUSHER_MPU_RST_MASK BITFIELD(1, 1) | ||
411 | |||
412 | /* Used by RM_DUCATI_RSTST */ | ||
413 | #define OMAP4430_ICECRUSHER_RST1ST_SHIFT (1 << 5) | ||
414 | #define OMAP4430_ICECRUSHER_RST1ST_MASK BITFIELD(5, 5) | ||
415 | |||
416 | /* Used by RM_DUCATI_RSTST */ | ||
417 | #define OMAP4430_ICECRUSHER_RST2ST_SHIFT (1 << 6) | ||
418 | #define OMAP4430_ICECRUSHER_RST2ST_MASK BITFIELD(6, 6) | ||
419 | |||
420 | /* Used by RM_IVAHD_RSTST */ | ||
421 | #define OMAP4430_ICECRUSHER_SEQ1_RST1ST_SHIFT (1 << 5) | ||
422 | #define OMAP4430_ICECRUSHER_SEQ1_RST1ST_MASK BITFIELD(5, 5) | ||
423 | |||
424 | /* Used by RM_IVAHD_RSTST */ | ||
425 | #define OMAP4430_ICECRUSHER_SEQ2_RST2ST_SHIFT (1 << 6) | ||
426 | #define OMAP4430_ICECRUSHER_SEQ2_RST2ST_MASK BITFIELD(6, 6) | ||
427 | |||
428 | /* Used by PRM_RSTST */ | ||
429 | #define OMAP4430_ICEPICK_RST_SHIFT (1 << 9) | ||
430 | #define OMAP4430_ICEPICK_RST_MASK BITFIELD(9, 9) | ||
431 | |||
432 | /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ | ||
433 | #define OMAP4430_INITVDD_SHIFT (1 << 2) | ||
434 | #define OMAP4430_INITVDD_MASK BITFIELD(2, 2) | ||
435 | |||
436 | /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ | ||
437 | #define OMAP4430_INITVOLTAGE_SHIFT (1 << 8) | ||
438 | #define OMAP4430_INITVOLTAGE_MASK BITFIELD(8, 15) | ||
439 | |||
440 | /* | ||
441 | * Used by PM_EMU_PWRSTST, PM_CORE_PWRSTST, PM_CAM_PWRSTST, PM_L3INIT_PWRSTST, | ||
442 | * PM_ABE_PWRSTST, PM_GFX_PWRSTST, PM_MPU_PWRSTST, PM_CEFUSE_PWRSTST, | ||
443 | * PM_DSS_PWRSTST, PM_L4PER_PWRSTST, PM_TESLA_PWRSTST, PM_IVAHD_PWRSTST | ||
444 | */ | ||
445 | #define OMAP4430_INTRANSITION_SHIFT (1 << 20) | ||
446 | #define OMAP4430_INTRANSITION_MASK BITFIELD(20, 20) | ||
447 | |||
448 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | ||
449 | #define OMAP4430_IO_EN_SHIFT (1 << 9) | ||
450 | #define OMAP4430_IO_EN_MASK BITFIELD(9, 9) | ||
451 | |||
452 | /* Used by PRM_IO_PMCTRL */ | ||
453 | #define OMAP4430_IO_ON_STATUS_SHIFT (1 << 5) | ||
454 | #define OMAP4430_IO_ON_STATUS_MASK BITFIELD(5, 5) | ||
455 | |||
456 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | ||
457 | #define OMAP4430_IO_ST_SHIFT (1 << 9) | ||
458 | #define OMAP4430_IO_ST_MASK BITFIELD(9, 9) | ||
459 | |||
460 | /* Used by PRM_IO_PMCTRL */ | ||
461 | #define OMAP4430_ISOCLK_OVERRIDE_SHIFT (1 << 0) | ||
462 | #define OMAP4430_ISOCLK_OVERRIDE_MASK BITFIELD(0, 0) | ||
463 | |||
464 | /* Used by PRM_IO_PMCTRL */ | ||
465 | #define OMAP4430_ISOCLK_STATUS_SHIFT (1 << 1) | ||
466 | #define OMAP4430_ISOCLK_STATUS_MASK BITFIELD(1, 1) | ||
467 | |||
468 | /* Used by PRM_IO_PMCTRL */ | ||
469 | #define OMAP4430_ISOOVR_EXTEND_SHIFT (1 << 4) | ||
470 | #define OMAP4430_ISOOVR_EXTEND_MASK BITFIELD(4, 4) | ||
471 | |||
472 | /* Used by PRM_IO_COUNT */ | ||
473 | #define OMAP4430_ISO_2_ON_TIME_SHIFT (1 << 0) | ||
474 | #define OMAP4430_ISO_2_ON_TIME_MASK BITFIELD(0, 7) | ||
475 | |||
476 | /* Used by PM_L3INIT_PWRSTCTRL */ | ||
477 | #define OMAP4430_L3INIT_BANK1_ONSTATE_SHIFT (1 << 16) | ||
478 | #define OMAP4430_L3INIT_BANK1_ONSTATE_MASK BITFIELD(16, 17) | ||
479 | |||
480 | /* Used by PM_L3INIT_PWRSTCTRL */ | ||
481 | #define OMAP4430_L3INIT_BANK1_RETSTATE_SHIFT (1 << 8) | ||
482 | #define OMAP4430_L3INIT_BANK1_RETSTATE_MASK BITFIELD(8, 8) | ||
483 | |||
484 | /* Used by PM_L3INIT_PWRSTST */ | ||
485 | #define OMAP4430_L3INIT_BANK1_STATEST_SHIFT (1 << 4) | ||
486 | #define OMAP4430_L3INIT_BANK1_STATEST_MASK BITFIELD(4, 5) | ||
487 | |||
488 | /* | ||
489 | * Used by PM_CORE_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_ABE_PWRSTCTRL, | ||
490 | * PM_MPU_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_L4PER_PWRSTCTRL, PM_TESLA_PWRSTCTRL, | ||
491 | * PM_IVAHD_PWRSTCTRL | ||
492 | */ | ||
493 | #define OMAP4430_LOGICRETSTATE_SHIFT (1 << 2) | ||
494 | #define OMAP4430_LOGICRETSTATE_MASK BITFIELD(2, 2) | ||
495 | |||
496 | /* | ||
497 | * Used by PM_EMU_PWRSTST, PM_CORE_PWRSTST, PM_CAM_PWRSTST, PM_L3INIT_PWRSTST, | ||
498 | * PM_ABE_PWRSTST, PM_GFX_PWRSTST, PM_MPU_PWRSTST, PM_CEFUSE_PWRSTST, | ||
499 | * PM_DSS_PWRSTST, PM_L4PER_PWRSTST, PM_TESLA_PWRSTST, PM_IVAHD_PWRSTST | ||
500 | */ | ||
501 | #define OMAP4430_LOGICSTATEST_SHIFT (1 << 2) | ||
502 | #define OMAP4430_LOGICSTATEST_MASK BITFIELD(2, 2) | ||
503 | |||
504 | /* | ||
505 | * Used by RM_WKUP_GPIO1_CONTEXT, RM_WKUP_KEYBOARD_CONTEXT, | ||
506 | * RM_WKUP_L4WKUP_CONTEXT, RM_WKUP_RTC_CONTEXT, RM_WKUP_SARRAM_CONTEXT, | ||
507 | * RM_WKUP_SYNCTIMER_CONTEXT, RM_WKUP_TIMER12_CONTEXT, RM_WKUP_TIMER1_CONTEXT, | ||
508 | * RM_WKUP_USIM_CONTEXT, RM_WKUP_WDT1_CONTEXT, RM_WKUP_WDT2_CONTEXT, | ||
509 | * RM_EMU_DEBUGSS_CONTEXT, RM_D2D_SAD2D_CONTEXT, RM_D2D_SAD2D_FW_CONTEXT, | ||
510 | * RM_DUCATI_DUCATI_CONTEXT, RM_L3INSTR_L3_3_CONTEXT, | ||
511 | * RM_L3INSTR_L3_INSTR_CONTEXT, RM_L3INSTR_OCP_WP1_CONTEXT, | ||
512 | * RM_L3_1_L3_1_CONTEXT, RM_L3_2_L3_2_CONTEXT, RM_L3_2_OCMC_RAM_CONTEXT, | ||
513 | * RM_L4CFG_L4_CFG_CONTEXT, RM_L4CFG_SAR_ROM_CONTEXT, RM_MEMIF_DLL_CONTEXT, | ||
514 | * RM_MEMIF_DLL_H_CONTEXT, RM_MEMIF_DMM_CONTEXT, RM_MEMIF_EMIF_FW_CONTEXT, | ||
515 | * RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT, RM_L3INIT_CCPTX_CONTEXT, | ||
516 | * RM_L3INIT_EMAC_CONTEXT, RM_L3INIT_P1500_CONTEXT, RM_L3INIT_PCIESS_CONTEXT, | ||
517 | * RM_L3INIT_SATA_CONTEXT, RM_L3INIT_TPPSS_CONTEXT, RM_L3INIT_UNIPRO1_CONTEXT, | ||
518 | * RM_L3INIT_USBPHYOCP2SCP_CONTEXT, RM_L3INIT_XHPI_CONTEXT, | ||
519 | * RM_ABE_AESS_CONTEXT, RM_ABE_DMIC_CONTEXT, RM_ABE_MCASP_CONTEXT, | ||
520 | * RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT, RM_ABE_MCBSP3_CONTEXT, | ||
521 | * RM_ABE_PDM_CONTEXT, RM_ABE_SLIMBUS_CONTEXT, RM_ABE_TIMER5_CONTEXT, | ||
522 | * RM_ABE_TIMER6_CONTEXT, RM_ABE_TIMER7_CONTEXT, RM_ABE_TIMER8_CONTEXT, | ||
523 | * RM_ABE_WDT3_CONTEXT, RM_GFX_GFX_CONTEXT, RM_MPU_MPU_CONTEXT, | ||
524 | * RM_CEFUSE_CEFUSE_CONTEXT, RM_ALWON_MDMINTC_CONTEXT, | ||
525 | * RM_ALWON_SR_CORE_CONTEXT, RM_ALWON_SR_IVA_CONTEXT, RM_ALWON_SR_MPU_CONTEXT, | ||
526 | * RM_DSS_DEISS_CONTEXT, RM_DSS_DSS_CONTEXT, RM_L4PER_ADC_CONTEXT, | ||
527 | * RM_L4PER_DMTIMER10_CONTEXT, RM_L4PER_DMTIMER11_CONTEXT, | ||
528 | * RM_L4PER_DMTIMER2_CONTEXT, RM_L4PER_DMTIMER3_CONTEXT, | ||
529 | * RM_L4PER_DMTIMER4_CONTEXT, RM_L4PER_DMTIMER9_CONTEXT, RM_L4PER_ELM_CONTEXT, | ||
530 | * RM_L4PER_HDQ1W_CONTEXT, RM_L4PER_HECC1_CONTEXT, RM_L4PER_HECC2_CONTEXT, | ||
531 | * RM_L4PER_I2C2_CONTEXT, RM_L4PER_I2C3_CONTEXT, RM_L4PER_I2C4_CONTEXT, | ||
532 | * RM_L4PER_I2C5_CONTEXT, RM_L4PER_L4_PER_CONTEXT, RM_L4PER_MCASP2_CONTEXT, | ||
533 | * RM_L4PER_MCASP3_CONTEXT, RM_L4PER_MCBSP4_CONTEXT, RM_L4PER_MCSPI1_CONTEXT, | ||
534 | * RM_L4PER_MCSPI2_CONTEXT, RM_L4PER_MCSPI3_CONTEXT, RM_L4PER_MCSPI4_CONTEXT, | ||
535 | * RM_L4PER_MGATE_CONTEXT, RM_L4PER_MMCSD3_CONTEXT, RM_L4PER_MMCSD4_CONTEXT, | ||
536 | * RM_L4PER_MMCSD5_CONTEXT, RM_L4PER_MSPROHG_CONTEXT, | ||
537 | * RM_L4PER_SLIMBUS2_CONTEXT, RM_L4SEC_PKAEIP29_CONTEXT, | ||
538 | * RM_TESLA_TESLA_CONTEXT, RM_IVAHD_IVAHD_CONTEXT, RM_IVAHD_SL2_CONTEXT | ||
539 | */ | ||
540 | #define OMAP4430_LOSTCONTEXT_DFF_SHIFT (1 << 0) | ||
541 | #define OMAP4430_LOSTCONTEXT_DFF_MASK BITFIELD(0, 0) | ||
542 | |||
543 | /* | ||
544 | * Used by RM_D2D_MODEM_ICR_CONTEXT, RM_D2D_SAD2D_CONTEXT, | ||
545 | * RM_D2D_SAD2D_FW_CONTEXT, RM_DUCATI_DUCATI_CONTEXT, RM_L3INSTR_L3_3_CONTEXT, | ||
546 | * RM_L3INSTR_OCP_WP1_CONTEXT, RM_L3_1_L3_1_CONTEXT, RM_L3_2_GPMC_CONTEXT, | ||
547 | * RM_L3_2_L3_2_CONTEXT, RM_L4CFG_HW_SEM_CONTEXT, RM_L4CFG_L4_CFG_CONTEXT, | ||
548 | * RM_L4CFG_MAILBOX_CONTEXT, RM_MEMIF_DMM_CONTEXT, RM_MEMIF_EMIF_1_CONTEXT, | ||
549 | * RM_MEMIF_EMIF_2_CONTEXT, RM_MEMIF_EMIF_FW_CONTEXT, RM_MEMIF_EMIF_H1_CONTEXT, | ||
550 | * RM_MEMIF_EMIF_H2_CONTEXT, RM_SDMA_SDMA_CONTEXT, RM_L3INIT_HSI_CONTEXT, | ||
551 | * RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT, RM_L3INIT_MMC6_CONTEXT, | ||
552 | * RM_L3INIT_USB_HOST_CONTEXT, RM_L3INIT_USB_HOST_FS_CONTEXT, | ||
553 | * RM_L3INIT_USB_OTG_CONTEXT, RM_L3INIT_USB_TLL_CONTEXT, RM_DSS_DSS_CONTEXT, | ||
554 | * RM_L4PER_GPIO2_CONTEXT, RM_L4PER_GPIO3_CONTEXT, RM_L4PER_GPIO4_CONTEXT, | ||
555 | * RM_L4PER_GPIO5_CONTEXT, RM_L4PER_GPIO6_CONTEXT, RM_L4PER_I2C1_CONTEXT, | ||
556 | * RM_L4PER_L4_PER_CONTEXT, RM_L4PER_UART1_CONTEXT, RM_L4PER_UART2_CONTEXT, | ||
557 | * RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT, RM_L4SEC_AES1_CONTEXT, | ||
558 | * RM_L4SEC_AES2_CONTEXT, RM_L4SEC_CRYPTODMA_CONTEXT, RM_L4SEC_DES3DES_CONTEXT, | ||
559 | * RM_L4SEC_RNG_CONTEXT, RM_L4SEC_SHA2MD51_CONTEXT, RM_TESLA_TESLA_CONTEXT | ||
560 | */ | ||
561 | #define OMAP4430_LOSTCONTEXT_RFF_SHIFT (1 << 1) | ||
562 | #define OMAP4430_LOSTCONTEXT_RFF_MASK BITFIELD(1, 1) | ||
563 | |||
564 | /* Used by RM_ABE_AESS_CONTEXT */ | ||
565 | #define OMAP4430_LOSTMEM_AESSMEM_SHIFT (1 << 8) | ||
566 | #define OMAP4430_LOSTMEM_AESSMEM_MASK BITFIELD(8, 8) | ||
567 | |||
568 | /* Used by RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT */ | ||
569 | #define OMAP4430_LOSTMEM_CAM_MEM_SHIFT (1 << 8) | ||
570 | #define OMAP4430_LOSTMEM_CAM_MEM_MASK BITFIELD(8, 8) | ||
571 | |||
572 | /* Used by RM_L3INSTR_OCP_WP1_CONTEXT */ | ||
573 | #define OMAP4430_LOSTMEM_CORE_NRET_BANK_SHIFT (1 << 8) | ||
574 | #define OMAP4430_LOSTMEM_CORE_NRET_BANK_MASK BITFIELD(8, 8) | ||
575 | |||
576 | /* Renamed from LOSTMEM_CORE_NRET_BANK Used by RM_MEMIF_DMM_CONTEXT */ | ||
577 | #define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_SHIFT (1 << 9) | ||
578 | #define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_MASK BITFIELD(9, 9) | ||
579 | |||
580 | /* Used by RM_L3_2_OCMC_RAM_CONTEXT */ | ||
581 | #define OMAP4430_LOSTMEM_CORE_OCMRAM_SHIFT (1 << 8) | ||
582 | #define OMAP4430_LOSTMEM_CORE_OCMRAM_MASK BITFIELD(8, 8) | ||
583 | |||
584 | /* | ||
585 | * Used by RM_D2D_MODEM_ICR_CONTEXT, RM_MEMIF_DMM_CONTEXT, | ||
586 | * RM_SDMA_SDMA_CONTEXT | ||
587 | */ | ||
588 | #define OMAP4430_LOSTMEM_CORE_OTHER_BANK_SHIFT (1 << 8) | ||
589 | #define OMAP4430_LOSTMEM_CORE_OTHER_BANK_MASK BITFIELD(8, 8) | ||
590 | |||
591 | /* Used by RM_DSS_DEISS_CONTEXT, RM_DSS_DSS_CONTEXT */ | ||
592 | #define OMAP4430_LOSTMEM_DSS_MEM_SHIFT (1 << 8) | ||
593 | #define OMAP4430_LOSTMEM_DSS_MEM_MASK BITFIELD(8, 8) | ||
594 | |||
595 | /* Used by RM_DUCATI_DUCATI_CONTEXT */ | ||
596 | #define OMAP4430_LOSTMEM_DUCATI_L2RAM_SHIFT (1 << 9) | ||
597 | #define OMAP4430_LOSTMEM_DUCATI_L2RAM_MASK BITFIELD(9, 9) | ||
598 | |||
599 | /* Used by RM_DUCATI_DUCATI_CONTEXT */ | ||
600 | #define OMAP4430_LOSTMEM_DUCATI_UNICACHE_SHIFT (1 << 8) | ||
601 | #define OMAP4430_LOSTMEM_DUCATI_UNICACHE_MASK BITFIELD(8, 8) | ||
602 | |||
603 | /* Used by RM_EMU_DEBUGSS_CONTEXT */ | ||
604 | #define OMAP4430_LOSTMEM_EMU_BANK_SHIFT (1 << 8) | ||
605 | #define OMAP4430_LOSTMEM_EMU_BANK_MASK BITFIELD(8, 8) | ||
606 | |||
607 | /* Used by RM_GFX_GFX_CONTEXT */ | ||
608 | #define OMAP4430_LOSTMEM_GFX_MEM_SHIFT (1 << 8) | ||
609 | #define OMAP4430_LOSTMEM_GFX_MEM_MASK BITFIELD(8, 8) | ||
610 | |||
611 | /* Used by RM_IVAHD_IVAHD_CONTEXT */ | ||
612 | #define OMAP4430_LOSTMEM_HWA_MEM_SHIFT (1 << 10) | ||
613 | #define OMAP4430_LOSTMEM_HWA_MEM_MASK BITFIELD(10, 10) | ||
614 | |||
615 | /* | ||
616 | * Used by RM_L3INIT_CCPTX_CONTEXT, RM_L3INIT_EMAC_CONTEXT, | ||
617 | * RM_L3INIT_HSI_CONTEXT, RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT, | ||
618 | * RM_L3INIT_MMC6_CONTEXT, RM_L3INIT_PCIESS_CONTEXT, RM_L3INIT_SATA_CONTEXT, | ||
619 | * RM_L3INIT_TPPSS_CONTEXT, RM_L3INIT_UNIPRO1_CONTEXT, | ||
620 | * RM_L3INIT_USB_OTG_CONTEXT, RM_L3INIT_XHPI_CONTEXT | ||
621 | */ | ||
622 | #define OMAP4430_LOSTMEM_L3INIT_BANK1_SHIFT (1 << 8) | ||
623 | #define OMAP4430_LOSTMEM_L3INIT_BANK1_MASK BITFIELD(8, 8) | ||
624 | |||
625 | /* Used by RM_MPU_MPU_CONTEXT */ | ||
626 | #define OMAP4430_LOSTMEM_MPU_L1_SHIFT (1 << 8) | ||
627 | #define OMAP4430_LOSTMEM_MPU_L1_MASK BITFIELD(8, 8) | ||
628 | |||
629 | /* Used by RM_MPU_MPU_CONTEXT */ | ||
630 | #define OMAP4430_LOSTMEM_MPU_L2_SHIFT (1 << 9) | ||
631 | #define OMAP4430_LOSTMEM_MPU_L2_MASK BITFIELD(9, 9) | ||
632 | |||
633 | /* Used by RM_MPU_MPU_CONTEXT */ | ||
634 | #define OMAP4430_LOSTMEM_MPU_RAM_SHIFT (1 << 10) | ||
635 | #define OMAP4430_LOSTMEM_MPU_RAM_MASK BITFIELD(10, 10) | ||
636 | |||
637 | /* | ||
638 | * Used by RM_L4PER_HECC1_CONTEXT, RM_L4PER_HECC2_CONTEXT, | ||
639 | * RM_L4PER_MCBSP4_CONTEXT, RM_L4PER_MMCSD3_CONTEXT, RM_L4PER_MMCSD4_CONTEXT, | ||
640 | * RM_L4PER_MMCSD5_CONTEXT, RM_L4PER_SLIMBUS2_CONTEXT, RM_L4SEC_PKAEIP29_CONTEXT | ||
641 | */ | ||
642 | #define OMAP4430_LOSTMEM_NONRETAINED_BANK_SHIFT (1 << 8) | ||
643 | #define OMAP4430_LOSTMEM_NONRETAINED_BANK_MASK BITFIELD(8, 8) | ||
644 | |||
645 | /* | ||
646 | * Used by RM_ABE_DMIC_CONTEXT, RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT, | ||
647 | * RM_ABE_MCBSP3_CONTEXT, RM_ABE_PDM_CONTEXT, RM_ABE_SLIMBUS_CONTEXT | ||
648 | */ | ||
649 | #define OMAP4430_LOSTMEM_PERIHPMEM_SHIFT (1 << 8) | ||
650 | #define OMAP4430_LOSTMEM_PERIHPMEM_MASK BITFIELD(8, 8) | ||
651 | |||
652 | /* | ||
653 | * Used by RM_L4PER_MSPROHG_CONTEXT, RM_L4PER_UART1_CONTEXT, | ||
654 | * RM_L4PER_UART2_CONTEXT, RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT, | ||
655 | * RM_L4SEC_CRYPTODMA_CONTEXT | ||
656 | */ | ||
657 | #define OMAP4430_LOSTMEM_RETAINED_BANK_SHIFT (1 << 8) | ||
658 | #define OMAP4430_LOSTMEM_RETAINED_BANK_MASK BITFIELD(8, 8) | ||
659 | |||
660 | /* Used by RM_IVAHD_SL2_CONTEXT */ | ||
661 | #define OMAP4430_LOSTMEM_SL2_MEM_SHIFT (1 << 8) | ||
662 | #define OMAP4430_LOSTMEM_SL2_MEM_MASK BITFIELD(8, 8) | ||
663 | |||
664 | /* Used by RM_IVAHD_IVAHD_CONTEXT */ | ||
665 | #define OMAP4430_LOSTMEM_TCM1_MEM_SHIFT (1 << 8) | ||
666 | #define OMAP4430_LOSTMEM_TCM1_MEM_MASK BITFIELD(8, 8) | ||
667 | |||
668 | /* Used by RM_IVAHD_IVAHD_CONTEXT */ | ||
669 | #define OMAP4430_LOSTMEM_TCM2_MEM_SHIFT (1 << 9) | ||
670 | #define OMAP4430_LOSTMEM_TCM2_MEM_MASK BITFIELD(9, 9) | ||
671 | |||
672 | /* Used by RM_TESLA_TESLA_CONTEXT */ | ||
673 | #define OMAP4430_LOSTMEM_TESLA_EDMA_SHIFT (1 << 10) | ||
674 | #define OMAP4430_LOSTMEM_TESLA_EDMA_MASK BITFIELD(10, 10) | ||
675 | |||
676 | /* Used by RM_TESLA_TESLA_CONTEXT */ | ||
677 | #define OMAP4430_LOSTMEM_TESLA_L1_SHIFT (1 << 8) | ||
678 | #define OMAP4430_LOSTMEM_TESLA_L1_MASK BITFIELD(8, 8) | ||
679 | |||
680 | /* Used by RM_TESLA_TESLA_CONTEXT */ | ||
681 | #define OMAP4430_LOSTMEM_TESLA_L2_SHIFT (1 << 9) | ||
682 | #define OMAP4430_LOSTMEM_TESLA_L2_MASK BITFIELD(9, 9) | ||
683 | |||
684 | /* Used by RM_WKUP_SARRAM_CONTEXT */ | ||
685 | #define OMAP4430_LOSTMEM_WKUP_BANK_SHIFT (1 << 8) | ||
686 | #define OMAP4430_LOSTMEM_WKUP_BANK_MASK BITFIELD(8, 8) | ||
687 | |||
688 | /* | ||
689 | * Used by PM_CORE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, | ||
690 | * PM_ABE_PWRSTCTRL, PM_GFX_PWRSTCTRL, PM_MPU_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, | ||
691 | * PM_DSS_PWRSTCTRL, PM_L4PER_PWRSTCTRL, PM_TESLA_PWRSTCTRL, PM_IVAHD_PWRSTCTRL | ||
692 | */ | ||
693 | #define OMAP4430_LOWPOWERSTATECHANGE_SHIFT (1 << 4) | ||
694 | #define OMAP4430_LOWPOWERSTATECHANGE_MASK BITFIELD(4, 4) | ||
695 | |||
696 | /* Used by PM_CORE_PWRSTCTRL */ | ||
697 | #define OMAP4430_MEMORYCHANGE_SHIFT (1 << 3) | ||
698 | #define OMAP4430_MEMORYCHANGE_MASK BITFIELD(3, 3) | ||
699 | |||
700 | /* Used by PRM_MODEM_IF_CTRL */ | ||
701 | #define OMAP4430_MODEM_READY_SHIFT (1 << 1) | ||
702 | #define OMAP4430_MODEM_READY_MASK BITFIELD(1, 1) | ||
703 | |||
704 | /* Used by PRM_MODEM_IF_CTRL */ | ||
705 | #define OMAP4430_MODEM_SHUTDOWN_IRQ_SHIFT (1 << 9) | ||
706 | #define OMAP4430_MODEM_SHUTDOWN_IRQ_MASK BITFIELD(9, 9) | ||
707 | |||
708 | /* Used by PRM_MODEM_IF_CTRL */ | ||
709 | #define OMAP4430_MODEM_SLEEP_ST_SHIFT (1 << 16) | ||
710 | #define OMAP4430_MODEM_SLEEP_ST_MASK BITFIELD(16, 16) | ||
711 | |||
712 | /* Used by PRM_MODEM_IF_CTRL */ | ||
713 | #define OMAP4430_MODEM_WAKE_IRQ_SHIFT (1 << 8) | ||
714 | #define OMAP4430_MODEM_WAKE_IRQ_MASK BITFIELD(8, 8) | ||
715 | |||
716 | /* Used by PM_MPU_PWRSTCTRL */ | ||
717 | #define OMAP4430_MPU_L1_ONSTATE_SHIFT (1 << 16) | ||
718 | #define OMAP4430_MPU_L1_ONSTATE_MASK BITFIELD(16, 17) | ||
719 | |||
720 | /* Used by PM_MPU_PWRSTCTRL */ | ||
721 | #define OMAP4430_MPU_L1_RETSTATE_SHIFT (1 << 8) | ||
722 | #define OMAP4430_MPU_L1_RETSTATE_MASK BITFIELD(8, 8) | ||
723 | |||
724 | /* Used by PM_MPU_PWRSTST */ | ||
725 | #define OMAP4430_MPU_L1_STATEST_SHIFT (1 << 4) | ||
726 | #define OMAP4430_MPU_L1_STATEST_MASK BITFIELD(4, 5) | ||
727 | |||
728 | /* Used by PM_MPU_PWRSTCTRL */ | ||
729 | #define OMAP4430_MPU_L2_ONSTATE_SHIFT (1 << 18) | ||
730 | #define OMAP4430_MPU_L2_ONSTATE_MASK BITFIELD(18, 19) | ||
731 | |||
732 | /* Used by PM_MPU_PWRSTCTRL */ | ||
733 | #define OMAP4430_MPU_L2_RETSTATE_SHIFT (1 << 9) | ||
734 | #define OMAP4430_MPU_L2_RETSTATE_MASK BITFIELD(9, 9) | ||
735 | |||
736 | /* Used by PM_MPU_PWRSTST */ | ||
737 | #define OMAP4430_MPU_L2_STATEST_SHIFT (1 << 6) | ||
738 | #define OMAP4430_MPU_L2_STATEST_MASK BITFIELD(6, 7) | ||
739 | |||
740 | /* Used by PM_MPU_PWRSTCTRL */ | ||
741 | #define OMAP4430_MPU_RAM_ONSTATE_SHIFT (1 << 20) | ||
742 | #define OMAP4430_MPU_RAM_ONSTATE_MASK BITFIELD(20, 21) | ||
743 | |||
744 | /* Used by PM_MPU_PWRSTCTRL */ | ||
745 | #define OMAP4430_MPU_RAM_RETSTATE_SHIFT (1 << 10) | ||
746 | #define OMAP4430_MPU_RAM_RETSTATE_MASK BITFIELD(10, 10) | ||
747 | |||
748 | /* Used by PM_MPU_PWRSTST */ | ||
749 | #define OMAP4430_MPU_RAM_STATEST_SHIFT (1 << 8) | ||
750 | #define OMAP4430_MPU_RAM_STATEST_MASK BITFIELD(8, 9) | ||
751 | |||
752 | /* Used by PRM_RSTST */ | ||
753 | #define OMAP4430_MPU_SECURITY_VIOL_RST_SHIFT (1 << 2) | ||
754 | #define OMAP4430_MPU_SECURITY_VIOL_RST_MASK BITFIELD(2, 2) | ||
755 | |||
756 | /* Used by PRM_RSTST */ | ||
757 | #define OMAP4430_MPU_WDT_RST_SHIFT (1 << 3) | ||
758 | #define OMAP4430_MPU_WDT_RST_MASK BITFIELD(3, 3) | ||
759 | |||
760 | /* Used by PM_L4PER_PWRSTCTRL */ | ||
761 | #define OMAP4430_NONRETAINED_BANK_ONSTATE_SHIFT (1 << 18) | ||
762 | #define OMAP4430_NONRETAINED_BANK_ONSTATE_MASK BITFIELD(18, 19) | ||
763 | |||
764 | /* Used by PM_L4PER_PWRSTCTRL */ | ||
765 | #define OMAP4430_NONRETAINED_BANK_RETSTATE_SHIFT (1 << 9) | ||
766 | #define OMAP4430_NONRETAINED_BANK_RETSTATE_MASK BITFIELD(9, 9) | ||
767 | |||
768 | /* Used by PM_L4PER_PWRSTST */ | ||
769 | #define OMAP4430_NONRETAINED_BANK_STATEST_SHIFT (1 << 6) | ||
770 | #define OMAP4430_NONRETAINED_BANK_STATEST_MASK BITFIELD(6, 7) | ||
771 | |||
772 | /* Used by PM_CORE_PWRSTCTRL */ | ||
773 | #define OMAP4430_OCP_NRET_BANK_ONSTATE_SHIFT (1 << 24) | ||
774 | #define OMAP4430_OCP_NRET_BANK_ONSTATE_MASK BITFIELD(24, 25) | ||
775 | |||
776 | /* Used by PM_CORE_PWRSTCTRL */ | ||
777 | #define OMAP4430_OCP_NRET_BANK_RETSTATE_SHIFT (1 << 12) | ||
778 | #define OMAP4430_OCP_NRET_BANK_RETSTATE_MASK BITFIELD(12, 12) | ||
779 | |||
780 | /* Used by PM_CORE_PWRSTST */ | ||
781 | #define OMAP4430_OCP_NRET_BANK_STATEST_SHIFT (1 << 12) | ||
782 | #define OMAP4430_OCP_NRET_BANK_STATEST_MASK BITFIELD(12, 13) | ||
783 | |||
784 | /* | ||
785 | * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, | ||
786 | * PRM_VC_VAL_CMD_VDD_MPU_L | ||
787 | */ | ||
788 | #define OMAP4430_OFF_SHIFT (1 << 0) | ||
789 | #define OMAP4430_OFF_MASK BITFIELD(0, 7) | ||
790 | |||
791 | /* Used by PRM_LDO_BANDGAP_CTRL */ | ||
792 | #define OMAP4430_OFF_ENABLE_SHIFT (1 << 0) | ||
793 | #define OMAP4430_OFF_ENABLE_MASK BITFIELD(0, 0) | ||
794 | |||
795 | /* | ||
796 | * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, | ||
797 | * PRM_VC_VAL_CMD_VDD_MPU_L | ||
798 | */ | ||
799 | #define OMAP4430_ON_SHIFT (1 << 24) | ||
800 | #define OMAP4430_ON_MASK BITFIELD(24, 31) | ||
801 | |||
802 | /* | ||
803 | * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, | ||
804 | * PRM_VC_VAL_CMD_VDD_MPU_L | ||
805 | */ | ||
806 | #define OMAP4430_ONLP_SHIFT (1 << 16) | ||
807 | #define OMAP4430_ONLP_MASK BITFIELD(16, 23) | ||
808 | |||
809 | /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ | ||
810 | #define OMAP4430_OPP_CHANGE_SHIFT (1 << 2) | ||
811 | #define OMAP4430_OPP_CHANGE_MASK BITFIELD(2, 2) | ||
812 | |||
813 | /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ | ||
814 | #define OMAP4430_OPP_SEL_SHIFT (1 << 0) | ||
815 | #define OMAP4430_OPP_SEL_MASK BITFIELD(0, 1) | ||
816 | |||
817 | /* Used by PRM_SRAM_COUNT */ | ||
818 | #define OMAP4430_PCHARGECNT_VALUE_SHIFT (1 << 0) | ||
819 | #define OMAP4430_PCHARGECNT_VALUE_MASK BITFIELD(0, 5) | ||
820 | |||
821 | /* Used by PRM_PSCON_COUNT */ | ||
822 | #define OMAP4430_PCHARGE_TIME_SHIFT (1 << 0) | ||
823 | #define OMAP4430_PCHARGE_TIME_MASK BITFIELD(0, 7) | ||
824 | |||
825 | /* Used by PM_ABE_PWRSTCTRL */ | ||
826 | #define OMAP4430_PERIPHMEM_ONSTATE_SHIFT (1 << 20) | ||
827 | #define OMAP4430_PERIPHMEM_ONSTATE_MASK BITFIELD(20, 21) | ||
828 | |||
829 | /* Used by PM_ABE_PWRSTCTRL */ | ||
830 | #define OMAP4430_PERIPHMEM_RETSTATE_SHIFT (1 << 10) | ||
831 | #define OMAP4430_PERIPHMEM_RETSTATE_MASK BITFIELD(10, 10) | ||
832 | |||
833 | /* Used by PM_ABE_PWRSTST */ | ||
834 | #define OMAP4430_PERIPHMEM_STATEST_SHIFT (1 << 8) | ||
835 | #define OMAP4430_PERIPHMEM_STATEST_MASK BITFIELD(8, 9) | ||
836 | |||
837 | /* Used by PRM_PHASE1_CNDP */ | ||
838 | #define OMAP4430_PHASE1_CNDP_SHIFT (1 << 0) | ||
839 | #define OMAP4430_PHASE1_CNDP_MASK BITFIELD(0, 31) | ||
840 | |||
841 | /* Used by PRM_PHASE2A_CNDP */ | ||
842 | #define OMAP4430_PHASE2A_CNDP_SHIFT (1 << 0) | ||
843 | #define OMAP4430_PHASE2A_CNDP_MASK BITFIELD(0, 31) | ||
844 | |||
845 | /* Used by PRM_PHASE2B_CNDP */ | ||
846 | #define OMAP4430_PHASE2B_CNDP_SHIFT (1 << 0) | ||
847 | #define OMAP4430_PHASE2B_CNDP_MASK BITFIELD(0, 31) | ||
848 | |||
849 | /* Used by PRM_PSCON_COUNT */ | ||
850 | #define OMAP4430_PONOUT_2_PGOODIN_TIME_SHIFT (1 << 8) | ||
851 | #define OMAP4430_PONOUT_2_PGOODIN_TIME_MASK BITFIELD(8, 15) | ||
852 | |||
853 | /* | ||
854 | * Used by PM_EMU_PWRSTCTRL, PM_CORE_PWRSTCTRL, PM_CAM_PWRSTCTRL, | ||
855 | * PM_L3INIT_PWRSTCTRL, PM_ABE_PWRSTCTRL, PM_GFX_PWRSTCTRL, PM_MPU_PWRSTCTRL, | ||
856 | * PM_CEFUSE_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_L4PER_PWRSTCTRL, | ||
857 | * PM_TESLA_PWRSTCTRL, PM_IVAHD_PWRSTCTRL | ||
858 | */ | ||
859 | #define OMAP4430_POWERSTATE_SHIFT (1 << 0) | ||
860 | #define OMAP4430_POWERSTATE_MASK BITFIELD(0, 1) | ||
861 | |||
862 | /* | ||
863 | * Used by PM_EMU_PWRSTST, PM_CORE_PWRSTST, PM_CAM_PWRSTST, PM_L3INIT_PWRSTST, | ||
864 | * PM_ABE_PWRSTST, PM_GFX_PWRSTST, PM_MPU_PWRSTST, PM_CEFUSE_PWRSTST, | ||
865 | * PM_DSS_PWRSTST, PM_L4PER_PWRSTST, PM_TESLA_PWRSTST, PM_IVAHD_PWRSTST | ||
866 | */ | ||
867 | #define OMAP4430_POWERSTATEST_SHIFT (1 << 0) | ||
868 | #define OMAP4430_POWERSTATEST_MASK BITFIELD(0, 1) | ||
869 | |||
870 | /* Used by PRM_PWRREQCTRL */ | ||
871 | #define OMAP4430_PWRREQ_COND_SHIFT (1 << 0) | ||
872 | #define OMAP4430_PWRREQ_COND_MASK BITFIELD(0, 1) | ||
873 | |||
874 | /* Used by PRM_VC_CFG_CHANNEL */ | ||
875 | #define OMAP4430_RACEN_VDD_CORE_L_SHIFT (1 << 3) | ||
876 | #define OMAP4430_RACEN_VDD_CORE_L_MASK BITFIELD(3, 3) | ||
877 | |||
878 | /* Used by PRM_VC_CFG_CHANNEL */ | ||
879 | #define OMAP4430_RACEN_VDD_IVA_L_SHIFT (1 << 11) | ||
880 | #define OMAP4430_RACEN_VDD_IVA_L_MASK BITFIELD(11, 11) | ||
881 | |||
882 | /* Used by PRM_VC_CFG_CHANNEL */ | ||
883 | #define OMAP4430_RACEN_VDD_MPU_L_SHIFT (1 << 20) | ||
884 | #define OMAP4430_RACEN_VDD_MPU_L_MASK BITFIELD(20, 20) | ||
885 | |||
886 | /* Used by PRM_VC_CFG_CHANNEL */ | ||
887 | #define OMAP4430_RAC_VDD_CORE_L_SHIFT (1 << 2) | ||
888 | #define OMAP4430_RAC_VDD_CORE_L_MASK BITFIELD(2, 2) | ||
889 | |||
890 | /* Used by PRM_VC_CFG_CHANNEL */ | ||
891 | #define OMAP4430_RAC_VDD_IVA_L_SHIFT (1 << 10) | ||
892 | #define OMAP4430_RAC_VDD_IVA_L_MASK BITFIELD(10, 10) | ||
893 | |||
894 | /* Used by PRM_VC_CFG_CHANNEL */ | ||
895 | #define OMAP4430_RAC_VDD_MPU_L_SHIFT (1 << 19) | ||
896 | #define OMAP4430_RAC_VDD_MPU_L_MASK BITFIELD(19, 19) | ||
897 | |||
898 | /* | ||
899 | * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, | ||
900 | * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, | ||
901 | * PRM_VOLTSETUP_MPU_RET_SLEEP | ||
902 | */ | ||
903 | #define OMAP4430_RAMP_DOWN_COUNT_SHIFT (1 << 16) | ||
904 | #define OMAP4430_RAMP_DOWN_COUNT_MASK BITFIELD(16, 21) | ||
905 | |||
906 | /* | ||
907 | * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, | ||
908 | * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, | ||
909 | * PRM_VOLTSETUP_MPU_RET_SLEEP | ||
910 | */ | ||
911 | #define OMAP4430_RAMP_DOWN_PRESCAL_SHIFT (1 << 24) | ||
912 | #define OMAP4430_RAMP_DOWN_PRESCAL_MASK BITFIELD(24, 25) | ||
913 | |||
914 | /* | ||
915 | * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, | ||
916 | * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, | ||
917 | * PRM_VOLTSETUP_MPU_RET_SLEEP | ||
918 | */ | ||
919 | #define OMAP4430_RAMP_UP_COUNT_SHIFT (1 << 0) | ||
920 | #define OMAP4430_RAMP_UP_COUNT_MASK BITFIELD(0, 5) | ||
921 | |||
922 | /* | ||
923 | * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, | ||
924 | * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, | ||
925 | * PRM_VOLTSETUP_MPU_RET_SLEEP | ||
926 | */ | ||
927 | #define OMAP4430_RAMP_UP_PRESCAL_SHIFT (1 << 8) | ||
928 | #define OMAP4430_RAMP_UP_PRESCAL_MASK BITFIELD(8, 9) | ||
929 | |||
930 | /* Used by PRM_VC_CFG_CHANNEL */ | ||
931 | #define OMAP4430_RAV_VDD_CORE_L_SHIFT (1 << 1) | ||
932 | #define OMAP4430_RAV_VDD_CORE_L_MASK BITFIELD(1, 1) | ||
933 | |||
934 | /* Used by PRM_VC_CFG_CHANNEL */ | ||
935 | #define OMAP4430_RAV_VDD_IVA_L_SHIFT (1 << 9) | ||
936 | #define OMAP4430_RAV_VDD_IVA_L_MASK BITFIELD(9, 9) | ||
937 | |||
938 | /* Used by PRM_VC_CFG_CHANNEL */ | ||
939 | #define OMAP4430_RAV_VDD_MPU_L_SHIFT (1 << 18) | ||
940 | #define OMAP4430_RAV_VDD_MPU_L_MASK BITFIELD(18, 18) | ||
941 | |||
942 | /* Used by PRM_VC_VAL_BYPASS */ | ||
943 | #define OMAP4430_REGADDR_SHIFT (1 << 8) | ||
944 | #define OMAP4430_REGADDR_MASK BITFIELD(8, 15) | ||
945 | |||
946 | /* | ||
947 | * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, | ||
948 | * PRM_VC_VAL_CMD_VDD_MPU_L | ||
949 | */ | ||
950 | #define OMAP4430_RET_SHIFT (1 << 8) | ||
951 | #define OMAP4430_RET_MASK BITFIELD(8, 15) | ||
952 | |||
953 | /* Used by PM_L4PER_PWRSTCTRL */ | ||
954 | #define OMAP4430_RETAINED_BANK_ONSTATE_SHIFT (1 << 16) | ||
955 | #define OMAP4430_RETAINED_BANK_ONSTATE_MASK BITFIELD(16, 17) | ||
956 | |||
957 | /* Used by PM_L4PER_PWRSTCTRL */ | ||
958 | #define OMAP4430_RETAINED_BANK_RETSTATE_SHIFT (1 << 8) | ||
959 | #define OMAP4430_RETAINED_BANK_RETSTATE_MASK BITFIELD(8, 8) | ||
960 | |||
961 | /* Used by PM_L4PER_PWRSTST */ | ||
962 | #define OMAP4430_RETAINED_BANK_STATEST_SHIFT (1 << 4) | ||
963 | #define OMAP4430_RETAINED_BANK_STATEST_MASK BITFIELD(4, 5) | ||
964 | |||
965 | /* | ||
966 | * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL, | ||
967 | * PRM_LDO_SRAM_MPU_CTRL | ||
968 | */ | ||
969 | #define OMAP4430_RETMODE_ENABLE_SHIFT (1 << 0) | ||
970 | #define OMAP4430_RETMODE_ENABLE_MASK BITFIELD(0, 0) | ||
971 | |||
972 | /* Used by REVISION_PRM */ | ||
973 | #define OMAP4430_REV_SHIFT (1 << 0) | ||
974 | #define OMAP4430_REV_MASK BITFIELD(0, 7) | ||
975 | |||
976 | /* Used by RM_DUCATI_RSTCTRL, RM_TESLA_RSTCTRL, RM_IVAHD_RSTCTRL */ | ||
977 | #define OMAP4430_RST1_SHIFT (1 << 0) | ||
978 | #define OMAP4430_RST1_MASK BITFIELD(0, 0) | ||
979 | |||
980 | /* Used by RM_DUCATI_RSTST, RM_TESLA_RSTST, RM_IVAHD_RSTST */ | ||
981 | #define OMAP4430_RST1ST_SHIFT (1 << 0) | ||
982 | #define OMAP4430_RST1ST_MASK BITFIELD(0, 0) | ||
983 | |||
984 | /* Used by RM_DUCATI_RSTCTRL, RM_TESLA_RSTCTRL, RM_IVAHD_RSTCTRL */ | ||
985 | #define OMAP4430_RST2_SHIFT (1 << 1) | ||
986 | #define OMAP4430_RST2_MASK BITFIELD(1, 1) | ||
987 | |||
988 | /* Used by RM_DUCATI_RSTST, RM_TESLA_RSTST, RM_IVAHD_RSTST */ | ||
989 | #define OMAP4430_RST2ST_SHIFT (1 << 1) | ||
990 | #define OMAP4430_RST2ST_MASK BITFIELD(1, 1) | ||
991 | |||
992 | /* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL */ | ||
993 | #define OMAP4430_RST3_SHIFT (1 << 2) | ||
994 | #define OMAP4430_RST3_MASK BITFIELD(2, 2) | ||
995 | |||
996 | /* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST */ | ||
997 | #define OMAP4430_RST3ST_SHIFT (1 << 2) | ||
998 | #define OMAP4430_RST3ST_MASK BITFIELD(2, 2) | ||
999 | |||
1000 | /* Used by PRM_RSTTIME */ | ||
1001 | #define OMAP4430_RSTTIME1_SHIFT (1 << 0) | ||
1002 | #define OMAP4430_RSTTIME1_MASK BITFIELD(0, 9) | ||
1003 | |||
1004 | /* Used by PRM_RSTTIME */ | ||
1005 | #define OMAP4430_RSTTIME2_SHIFT (1 << 10) | ||
1006 | #define OMAP4430_RSTTIME2_MASK BITFIELD(10, 14) | ||
1007 | |||
1008 | /* Used by PRM_RSTCTRL */ | ||
1009 | #define OMAP4430_RST_GLOBAL_COLD_SW_SHIFT (1 << 1) | ||
1010 | #define OMAP4430_RST_GLOBAL_COLD_SW_MASK BITFIELD(1, 1) | ||
1011 | |||
1012 | /* Used by PRM_RSTCTRL */ | ||
1013 | #define OMAP4430_RST_GLOBAL_WARM_SW_SHIFT (1 << 0) | ||
1014 | #define OMAP4430_RST_GLOBAL_WARM_SW_MASK BITFIELD(0, 0) | ||
1015 | |||
1016 | /* Used by PRM_VC_CFG_CHANNEL */ | ||
1017 | #define OMAP4430_SA_VDD_CORE_L_SHIFT (1 << 0) | ||
1018 | #define OMAP4430_SA_VDD_CORE_L_MASK BITFIELD(0, 0) | ||
1019 | |||
1020 | /* Renamed from SA_VDD_CORE_L Used by PRM_VC_SMPS_SA */ | ||
1021 | #define OMAP4430_SA_VDD_CORE_L_0_6_SHIFT (1 << 0) | ||
1022 | #define OMAP4430_SA_VDD_CORE_L_0_6_MASK BITFIELD(0, 6) | ||
1023 | |||
1024 | /* Used by PRM_VC_CFG_CHANNEL */ | ||
1025 | #define OMAP4430_SA_VDD_IVA_L_SHIFT (1 << 8) | ||
1026 | #define OMAP4430_SA_VDD_IVA_L_MASK BITFIELD(8, 8) | ||
1027 | |||
1028 | /* Renamed from SA_VDD_IVA_L Used by PRM_VC_SMPS_SA */ | ||
1029 | #define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_SHIFT (1 << 8) | ||
1030 | #define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK BITFIELD(8, 14) | ||
1031 | |||
1032 | /* Used by PRM_VC_CFG_CHANNEL */ | ||
1033 | #define OMAP4430_SA_VDD_MPU_L_SHIFT (1 << 16) | ||
1034 | #define OMAP4430_SA_VDD_MPU_L_MASK BITFIELD(16, 16) | ||
1035 | |||
1036 | /* Renamed from SA_VDD_MPU_L Used by PRM_VC_SMPS_SA */ | ||
1037 | #define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_SHIFT (1 << 16) | ||
1038 | #define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK BITFIELD(16, 22) | ||
1039 | |||
1040 | /* Used by PRM_VC_CFG_I2C_CLK */ | ||
1041 | #define OMAP4430_SCLH_SHIFT (1 << 0) | ||
1042 | #define OMAP4430_SCLH_MASK BITFIELD(0, 7) | ||
1043 | |||
1044 | /* Used by PRM_VC_CFG_I2C_CLK */ | ||
1045 | #define OMAP4430_SCLL_SHIFT (1 << 8) | ||
1046 | #define OMAP4430_SCLL_MASK BITFIELD(8, 15) | ||
1047 | |||
1048 | /* Used by PRM_RSTST */ | ||
1049 | #define OMAP4430_SECURE_WDT_RST_SHIFT (1 << 4) | ||
1050 | #define OMAP4430_SECURE_WDT_RST_MASK BITFIELD(4, 4) | ||
1051 | |||
1052 | /* Used by PM_IVAHD_PWRSTCTRL */ | ||
1053 | #define OMAP4430_SL2_MEM_ONSTATE_SHIFT (1 << 18) | ||
1054 | #define OMAP4430_SL2_MEM_ONSTATE_MASK BITFIELD(18, 19) | ||
1055 | |||
1056 | /* Used by PM_IVAHD_PWRSTCTRL */ | ||
1057 | #define OMAP4430_SL2_MEM_RETSTATE_SHIFT (1 << 9) | ||
1058 | #define OMAP4430_SL2_MEM_RETSTATE_MASK BITFIELD(9, 9) | ||
1059 | |||
1060 | /* Used by PM_IVAHD_PWRSTST */ | ||
1061 | #define OMAP4430_SL2_MEM_STATEST_SHIFT (1 << 6) | ||
1062 | #define OMAP4430_SL2_MEM_STATEST_MASK BITFIELD(6, 7) | ||
1063 | |||
1064 | /* Used by PRM_VC_VAL_BYPASS */ | ||
1065 | #define OMAP4430_SLAVEADDR_SHIFT (1 << 0) | ||
1066 | #define OMAP4430_SLAVEADDR_MASK BITFIELD(0, 6) | ||
1067 | |||
1068 | /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ | ||
1069 | #define OMAP4430_SLEEP_RBB_SEL_SHIFT (1 << 3) | ||
1070 | #define OMAP4430_SLEEP_RBB_SEL_MASK BITFIELD(3, 3) | ||
1071 | |||
1072 | /* Used by PRM_SRAM_COUNT */ | ||
1073 | #define OMAP4430_SLPCNT_VALUE_SHIFT (1 << 16) | ||
1074 | #define OMAP4430_SLPCNT_VALUE_MASK BITFIELD(16, 23) | ||
1075 | |||
1076 | /* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_IVA_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */ | ||
1077 | #define OMAP4430_SMPSWAITTIMEMAX_SHIFT (1 << 8) | ||
1078 | #define OMAP4430_SMPSWAITTIMEMAX_MASK BITFIELD(8, 23) | ||
1079 | |||
1080 | /* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_IVA_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */ | ||
1081 | #define OMAP4430_SMPSWAITTIMEMIN_SHIFT (1 << 8) | ||
1082 | #define OMAP4430_SMPSWAITTIMEMIN_MASK BITFIELD(8, 23) | ||
1083 | |||
1084 | /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ | ||
1085 | #define OMAP4430_SR2EN_SHIFT (1 << 0) | ||
1086 | #define OMAP4430_SR2EN_MASK BITFIELD(0, 0) | ||
1087 | |||
1088 | /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ | ||
1089 | #define OMAP4430_SR2_IN_TRANSITION_SHIFT (1 << 6) | ||
1090 | #define OMAP4430_SR2_IN_TRANSITION_MASK BITFIELD(6, 6) | ||
1091 | |||
1092 | /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ | ||
1093 | #define OMAP4430_SR2_STATUS_SHIFT (1 << 3) | ||
1094 | #define OMAP4430_SR2_STATUS_MASK BITFIELD(3, 4) | ||
1095 | |||
1096 | /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ | ||
1097 | #define OMAP4430_SR2_WTCNT_VALUE_SHIFT (1 << 8) | ||
1098 | #define OMAP4430_SR2_WTCNT_VALUE_MASK BITFIELD(8, 15) | ||
1099 | |||
1100 | /* | ||
1101 | * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL, | ||
1102 | * PRM_LDO_SRAM_MPU_CTRL | ||
1103 | */ | ||
1104 | #define OMAP4430_SRAMLDO_STATUS_SHIFT (1 << 8) | ||
1105 | #define OMAP4430_SRAMLDO_STATUS_MASK BITFIELD(8, 8) | ||
1106 | |||
1107 | /* | ||
1108 | * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL, | ||
1109 | * PRM_LDO_SRAM_MPU_CTRL | ||
1110 | */ | ||
1111 | #define OMAP4430_SRAM_IN_TRANSITION_SHIFT (1 << 9) | ||
1112 | #define OMAP4430_SRAM_IN_TRANSITION_MASK BITFIELD(9, 9) | ||
1113 | |||
1114 | /* Used by PRM_VC_CFG_I2C_MODE */ | ||
1115 | #define OMAP4430_SRMODEEN_SHIFT (1 << 4) | ||
1116 | #define OMAP4430_SRMODEEN_MASK BITFIELD(4, 4) | ||
1117 | |||
1118 | /* Used by PRM_VOLTSETUP_WARMRESET */ | ||
1119 | #define OMAP4430_STABLE_COUNT_SHIFT (1 << 0) | ||
1120 | #define OMAP4430_STABLE_COUNT_MASK BITFIELD(0, 5) | ||
1121 | |||
1122 | /* Used by PRM_VOLTSETUP_WARMRESET */ | ||
1123 | #define OMAP4430_STABLE_PRESCAL_SHIFT (1 << 8) | ||
1124 | #define OMAP4430_STABLE_PRESCAL_MASK BITFIELD(8, 9) | ||
1125 | |||
1126 | /* Used by PM_IVAHD_PWRSTCTRL */ | ||
1127 | #define OMAP4430_TCM1_MEM_ONSTATE_SHIFT (1 << 20) | ||
1128 | #define OMAP4430_TCM1_MEM_ONSTATE_MASK BITFIELD(20, 21) | ||
1129 | |||
1130 | /* Used by PM_IVAHD_PWRSTCTRL */ | ||
1131 | #define OMAP4430_TCM1_MEM_RETSTATE_SHIFT (1 << 10) | ||
1132 | #define OMAP4430_TCM1_MEM_RETSTATE_MASK BITFIELD(10, 10) | ||
1133 | |||
1134 | /* Used by PM_IVAHD_PWRSTST */ | ||
1135 | #define OMAP4430_TCM1_MEM_STATEST_SHIFT (1 << 8) | ||
1136 | #define OMAP4430_TCM1_MEM_STATEST_MASK BITFIELD(8, 9) | ||
1137 | |||
1138 | /* Used by PM_IVAHD_PWRSTCTRL */ | ||
1139 | #define OMAP4430_TCM2_MEM_ONSTATE_SHIFT (1 << 22) | ||
1140 | #define OMAP4430_TCM2_MEM_ONSTATE_MASK BITFIELD(22, 23) | ||
1141 | |||
1142 | /* Used by PM_IVAHD_PWRSTCTRL */ | ||
1143 | #define OMAP4430_TCM2_MEM_RETSTATE_SHIFT (1 << 11) | ||
1144 | #define OMAP4430_TCM2_MEM_RETSTATE_MASK BITFIELD(11, 11) | ||
1145 | |||
1146 | /* Used by PM_IVAHD_PWRSTST */ | ||
1147 | #define OMAP4430_TCM2_MEM_STATEST_SHIFT (1 << 10) | ||
1148 | #define OMAP4430_TCM2_MEM_STATEST_MASK BITFIELD(10, 11) | ||
1149 | |||
1150 | /* Used by RM_TESLA_RSTST */ | ||
1151 | #define OMAP4430_TESLASS_EMU_RSTST_SHIFT (1 << 2) | ||
1152 | #define OMAP4430_TESLASS_EMU_RSTST_MASK BITFIELD(2, 2) | ||
1153 | |||
1154 | /* Used by RM_TESLA_RSTST */ | ||
1155 | #define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_SHIFT (1 << 3) | ||
1156 | #define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_MASK BITFIELD(3, 3) | ||
1157 | |||
1158 | /* Used by PM_TESLA_PWRSTCTRL */ | ||
1159 | #define OMAP4430_TESLA_EDMA_ONSTATE_SHIFT (1 << 20) | ||
1160 | #define OMAP4430_TESLA_EDMA_ONSTATE_MASK BITFIELD(20, 21) | ||
1161 | |||
1162 | /* Used by PM_TESLA_PWRSTCTRL */ | ||
1163 | #define OMAP4430_TESLA_EDMA_RETSTATE_SHIFT (1 << 10) | ||
1164 | #define OMAP4430_TESLA_EDMA_RETSTATE_MASK BITFIELD(10, 10) | ||
1165 | |||
1166 | /* Used by PM_TESLA_PWRSTST */ | ||
1167 | #define OMAP4430_TESLA_EDMA_STATEST_SHIFT (1 << 8) | ||
1168 | #define OMAP4430_TESLA_EDMA_STATEST_MASK BITFIELD(8, 9) | ||
1169 | |||
1170 | /* Used by PM_TESLA_PWRSTCTRL */ | ||
1171 | #define OMAP4430_TESLA_L1_ONSTATE_SHIFT (1 << 16) | ||
1172 | #define OMAP4430_TESLA_L1_ONSTATE_MASK BITFIELD(16, 17) | ||
1173 | |||
1174 | /* Used by PM_TESLA_PWRSTCTRL */ | ||
1175 | #define OMAP4430_TESLA_L1_RETSTATE_SHIFT (1 << 8) | ||
1176 | #define OMAP4430_TESLA_L1_RETSTATE_MASK BITFIELD(8, 8) | ||
1177 | |||
1178 | /* Used by PM_TESLA_PWRSTST */ | ||
1179 | #define OMAP4430_TESLA_L1_STATEST_SHIFT (1 << 4) | ||
1180 | #define OMAP4430_TESLA_L1_STATEST_MASK BITFIELD(4, 5) | ||
1181 | |||
1182 | /* Used by PM_TESLA_PWRSTCTRL */ | ||
1183 | #define OMAP4430_TESLA_L2_ONSTATE_SHIFT (1 << 18) | ||
1184 | #define OMAP4430_TESLA_L2_ONSTATE_MASK BITFIELD(18, 19) | ||
1185 | |||
1186 | /* Used by PM_TESLA_PWRSTCTRL */ | ||
1187 | #define OMAP4430_TESLA_L2_RETSTATE_SHIFT (1 << 9) | ||
1188 | #define OMAP4430_TESLA_L2_RETSTATE_MASK BITFIELD(9, 9) | ||
1189 | |||
1190 | /* Used by PM_TESLA_PWRSTST */ | ||
1191 | #define OMAP4430_TESLA_L2_STATEST_SHIFT (1 << 6) | ||
1192 | #define OMAP4430_TESLA_L2_STATEST_MASK BITFIELD(6, 7) | ||
1193 | |||
1194 | /* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */ | ||
1195 | #define OMAP4430_TIMEOUT_SHIFT (1 << 0) | ||
1196 | #define OMAP4430_TIMEOUT_MASK BITFIELD(0, 15) | ||
1197 | |||
1198 | /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ | ||
1199 | #define OMAP4430_TIMEOUTEN_SHIFT (1 << 3) | ||
1200 | #define OMAP4430_TIMEOUTEN_MASK BITFIELD(3, 3) | ||
1201 | |||
1202 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | ||
1203 | #define OMAP4430_TRANSITION_EN_SHIFT (1 << 8) | ||
1204 | #define OMAP4430_TRANSITION_EN_MASK BITFIELD(8, 8) | ||
1205 | |||
1206 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | ||
1207 | #define OMAP4430_TRANSITION_ST_SHIFT (1 << 8) | ||
1208 | #define OMAP4430_TRANSITION_ST_MASK BITFIELD(8, 8) | ||
1209 | |||
1210 | /* Used by PRM_VC_VAL_BYPASS */ | ||
1211 | #define OMAP4430_VALID_SHIFT (1 << 24) | ||
1212 | #define OMAP4430_VALID_MASK BITFIELD(24, 24) | ||
1213 | |||
1214 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | ||
1215 | #define OMAP4430_VC_BYPASSACK_EN_SHIFT (1 << 14) | ||
1216 | #define OMAP4430_VC_BYPASSACK_EN_MASK BITFIELD(14, 14) | ||
1217 | |||
1218 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | ||
1219 | #define OMAP4430_VC_BYPASSACK_ST_SHIFT (1 << 14) | ||
1220 | #define OMAP4430_VC_BYPASSACK_ST_MASK BITFIELD(14, 14) | ||
1221 | |||
1222 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | ||
1223 | #define OMAP4430_VC_IVA_VPACK_EN_SHIFT (1 << 30) | ||
1224 | #define OMAP4430_VC_IVA_VPACK_EN_MASK BITFIELD(30, 30) | ||
1225 | |||
1226 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | ||
1227 | #define OMAP4430_VC_IVA_VPACK_ST_SHIFT (1 << 30) | ||
1228 | #define OMAP4430_VC_IVA_VPACK_ST_MASK BITFIELD(30, 30) | ||
1229 | |||
1230 | /* Used by PRM_IRQENABLE_MPU_2 */ | ||
1231 | #define OMAP4430_VC_MPU_VPACK_EN_SHIFT (1 << 6) | ||
1232 | #define OMAP4430_VC_MPU_VPACK_EN_MASK BITFIELD(6, 6) | ||
1233 | |||
1234 | /* Used by PRM_IRQSTATUS_MPU_2 */ | ||
1235 | #define OMAP4430_VC_MPU_VPACK_ST_SHIFT (1 << 6) | ||
1236 | #define OMAP4430_VC_MPU_VPACK_ST_MASK BITFIELD(6, 6) | ||
1237 | |||
1238 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | ||
1239 | #define OMAP4430_VC_RAERR_EN_SHIFT (1 << 12) | ||
1240 | #define OMAP4430_VC_RAERR_EN_MASK BITFIELD(12, 12) | ||
1241 | |||
1242 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | ||
1243 | #define OMAP4430_VC_RAERR_ST_SHIFT (1 << 12) | ||
1244 | #define OMAP4430_VC_RAERR_ST_MASK BITFIELD(12, 12) | ||
1245 | |||
1246 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | ||
1247 | #define OMAP4430_VC_SAERR_EN_SHIFT (1 << 11) | ||
1248 | #define OMAP4430_VC_SAERR_EN_MASK BITFIELD(11, 11) | ||
1249 | |||
1250 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | ||
1251 | #define OMAP4430_VC_SAERR_ST_SHIFT (1 << 11) | ||
1252 | #define OMAP4430_VC_SAERR_ST_MASK BITFIELD(11, 11) | ||
1253 | |||
1254 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | ||
1255 | #define OMAP4430_VC_TOERR_EN_SHIFT (1 << 13) | ||
1256 | #define OMAP4430_VC_TOERR_EN_MASK BITFIELD(13, 13) | ||
1257 | |||
1258 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | ||
1259 | #define OMAP4430_VC_TOERR_ST_SHIFT (1 << 13) | ||
1260 | #define OMAP4430_VC_TOERR_ST_MASK BITFIELD(13, 13) | ||
1261 | |||
1262 | /* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */ | ||
1263 | #define OMAP4430_VDDMAX_SHIFT (1 << 24) | ||
1264 | #define OMAP4430_VDDMAX_MASK BITFIELD(24, 31) | ||
1265 | |||
1266 | /* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */ | ||
1267 | #define OMAP4430_VDDMIN_SHIFT (1 << 16) | ||
1268 | #define OMAP4430_VDDMIN_MASK BITFIELD(16, 23) | ||
1269 | |||
1270 | /* Used by PRM_VOLTCTRL */ | ||
1271 | #define OMAP4430_VDD_CORE_I2C_DISABLE_SHIFT (1 << 12) | ||
1272 | #define OMAP4430_VDD_CORE_I2C_DISABLE_MASK BITFIELD(12, 12) | ||
1273 | |||
1274 | /* Used by PRM_RSTST */ | ||
1275 | #define OMAP4430_VDD_CORE_VOLT_MGR_RST_SHIFT (1 << 8) | ||
1276 | #define OMAP4430_VDD_CORE_VOLT_MGR_RST_MASK BITFIELD(8, 8) | ||
1277 | |||
1278 | /* Used by PRM_VOLTCTRL */ | ||
1279 | #define OMAP4430_VDD_IVA_I2C_DISABLE_SHIFT (1 << 14) | ||
1280 | #define OMAP4430_VDD_IVA_I2C_DISABLE_MASK BITFIELD(14, 14) | ||
1281 | |||
1282 | /* Used by PRM_VOLTCTRL */ | ||
1283 | #define OMAP4430_VDD_IVA_PRESENCE_SHIFT (1 << 9) | ||
1284 | #define OMAP4430_VDD_IVA_PRESENCE_MASK BITFIELD(9, 9) | ||
1285 | |||
1286 | /* Used by PRM_RSTST */ | ||
1287 | #define OMAP4430_VDD_IVA_VOLT_MGR_RST_SHIFT (1 << 7) | ||
1288 | #define OMAP4430_VDD_IVA_VOLT_MGR_RST_MASK BITFIELD(7, 7) | ||
1289 | |||
1290 | /* Used by PRM_VOLTCTRL */ | ||
1291 | #define OMAP4430_VDD_MPU_I2C_DISABLE_SHIFT (1 << 13) | ||
1292 | #define OMAP4430_VDD_MPU_I2C_DISABLE_MASK BITFIELD(13, 13) | ||
1293 | |||
1294 | /* Used by PRM_VOLTCTRL */ | ||
1295 | #define OMAP4430_VDD_MPU_PRESENCE_SHIFT (1 << 8) | ||
1296 | #define OMAP4430_VDD_MPU_PRESENCE_MASK BITFIELD(8, 8) | ||
1297 | |||
1298 | /* Used by PRM_RSTST */ | ||
1299 | #define OMAP4430_VDD_MPU_VOLT_MGR_RST_SHIFT (1 << 6) | ||
1300 | #define OMAP4430_VDD_MPU_VOLT_MGR_RST_MASK BITFIELD(6, 6) | ||
1301 | |||
1302 | /* Used by PRM_VC_VAL_SMPS_RA_VOL */ | ||
1303 | #define OMAP4430_VOLRA_VDD_CORE_L_SHIFT (1 << 0) | ||
1304 | #define OMAP4430_VOLRA_VDD_CORE_L_MASK BITFIELD(0, 7) | ||
1305 | |||
1306 | /* Used by PRM_VC_VAL_SMPS_RA_VOL */ | ||
1307 | #define OMAP4430_VOLRA_VDD_IVA_L_SHIFT (1 << 8) | ||
1308 | #define OMAP4430_VOLRA_VDD_IVA_L_MASK BITFIELD(8, 15) | ||
1309 | |||
1310 | /* Used by PRM_VC_VAL_SMPS_RA_VOL */ | ||
1311 | #define OMAP4430_VOLRA_VDD_MPU_L_SHIFT (1 << 16) | ||
1312 | #define OMAP4430_VOLRA_VDD_MPU_L_MASK BITFIELD(16, 23) | ||
1313 | |||
1314 | /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ | ||
1315 | #define OMAP4430_VPENABLE_SHIFT (1 << 0) | ||
1316 | #define OMAP4430_VPENABLE_MASK BITFIELD(0, 0) | ||
1317 | |||
1318 | /* Used by PRM_VP_CORE_STATUS, PRM_VP_IVA_STATUS, PRM_VP_MPU_STATUS */ | ||
1319 | #define OMAP4430_VPINIDLE_SHIFT (1 << 0) | ||
1320 | #define OMAP4430_VPINIDLE_MASK BITFIELD(0, 0) | ||
1321 | |||
1322 | /* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_IVA_VOLTAGE, PRM_VP_MPU_VOLTAGE */ | ||
1323 | #define OMAP4430_VPVOLTAGE_SHIFT (1 << 0) | ||
1324 | #define OMAP4430_VPVOLTAGE_MASK BITFIELD(0, 7) | ||
1325 | |||
1326 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | ||
1327 | #define OMAP4430_VP_CORE_EQVALUE_EN_SHIFT (1 << 20) | ||
1328 | #define OMAP4430_VP_CORE_EQVALUE_EN_MASK BITFIELD(20, 20) | ||
1329 | |||
1330 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | ||
1331 | #define OMAP4430_VP_CORE_EQVALUE_ST_SHIFT (1 << 20) | ||
1332 | #define OMAP4430_VP_CORE_EQVALUE_ST_MASK BITFIELD(20, 20) | ||
1333 | |||
1334 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | ||
1335 | #define OMAP4430_VP_CORE_MAXVDD_EN_SHIFT (1 << 18) | ||
1336 | #define OMAP4430_VP_CORE_MAXVDD_EN_MASK BITFIELD(18, 18) | ||
1337 | |||
1338 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | ||
1339 | #define OMAP4430_VP_CORE_MAXVDD_ST_SHIFT (1 << 18) | ||
1340 | #define OMAP4430_VP_CORE_MAXVDD_ST_MASK BITFIELD(18, 18) | ||
1341 | |||
1342 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | ||
1343 | #define OMAP4430_VP_CORE_MINVDD_EN_SHIFT (1 << 17) | ||
1344 | #define OMAP4430_VP_CORE_MINVDD_EN_MASK BITFIELD(17, 17) | ||
1345 | |||
1346 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | ||
1347 | #define OMAP4430_VP_CORE_MINVDD_ST_SHIFT (1 << 17) | ||
1348 | #define OMAP4430_VP_CORE_MINVDD_ST_MASK BITFIELD(17, 17) | ||
1349 | |||
1350 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | ||
1351 | #define OMAP4430_VP_CORE_NOSMPSACK_EN_SHIFT (1 << 19) | ||
1352 | #define OMAP4430_VP_CORE_NOSMPSACK_EN_MASK BITFIELD(19, 19) | ||
1353 | |||
1354 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | ||
1355 | #define OMAP4430_VP_CORE_NOSMPSACK_ST_SHIFT (1 << 19) | ||
1356 | #define OMAP4430_VP_CORE_NOSMPSACK_ST_MASK BITFIELD(19, 19) | ||
1357 | |||
1358 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | ||
1359 | #define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_SHIFT (1 << 16) | ||
1360 | #define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_MASK BITFIELD(16, 16) | ||
1361 | |||
1362 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | ||
1363 | #define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_SHIFT (1 << 16) | ||
1364 | #define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_MASK BITFIELD(16, 16) | ||
1365 | |||
1366 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | ||
1367 | #define OMAP4430_VP_CORE_TRANXDONE_EN_SHIFT (1 << 21) | ||
1368 | #define OMAP4430_VP_CORE_TRANXDONE_EN_MASK BITFIELD(21, 21) | ||
1369 | |||
1370 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | ||
1371 | #define OMAP4430_VP_CORE_TRANXDONE_ST_SHIFT (1 << 21) | ||
1372 | #define OMAP4430_VP_CORE_TRANXDONE_ST_MASK BITFIELD(21, 21) | ||
1373 | |||
1374 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | ||
1375 | #define OMAP4430_VP_IVA_EQVALUE_EN_SHIFT (1 << 28) | ||
1376 | #define OMAP4430_VP_IVA_EQVALUE_EN_MASK BITFIELD(28, 28) | ||
1377 | |||
1378 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | ||
1379 | #define OMAP4430_VP_IVA_EQVALUE_ST_SHIFT (1 << 28) | ||
1380 | #define OMAP4430_VP_IVA_EQVALUE_ST_MASK BITFIELD(28, 28) | ||
1381 | |||
1382 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | ||
1383 | #define OMAP4430_VP_IVA_MAXVDD_EN_SHIFT (1 << 26) | ||
1384 | #define OMAP4430_VP_IVA_MAXVDD_EN_MASK BITFIELD(26, 26) | ||
1385 | |||
1386 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | ||
1387 | #define OMAP4430_VP_IVA_MAXVDD_ST_SHIFT (1 << 26) | ||
1388 | #define OMAP4430_VP_IVA_MAXVDD_ST_MASK BITFIELD(26, 26) | ||
1389 | |||
1390 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | ||
1391 | #define OMAP4430_VP_IVA_MINVDD_EN_SHIFT (1 << 25) | ||
1392 | #define OMAP4430_VP_IVA_MINVDD_EN_MASK BITFIELD(25, 25) | ||
1393 | |||
1394 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | ||
1395 | #define OMAP4430_VP_IVA_MINVDD_ST_SHIFT (1 << 25) | ||
1396 | #define OMAP4430_VP_IVA_MINVDD_ST_MASK BITFIELD(25, 25) | ||
1397 | |||
1398 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | ||
1399 | #define OMAP4430_VP_IVA_NOSMPSACK_EN_SHIFT (1 << 27) | ||
1400 | #define OMAP4430_VP_IVA_NOSMPSACK_EN_MASK BITFIELD(27, 27) | ||
1401 | |||
1402 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | ||
1403 | #define OMAP4430_VP_IVA_NOSMPSACK_ST_SHIFT (1 << 27) | ||
1404 | #define OMAP4430_VP_IVA_NOSMPSACK_ST_MASK BITFIELD(27, 27) | ||
1405 | |||
1406 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | ||
1407 | #define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_SHIFT (1 << 24) | ||
1408 | #define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_MASK BITFIELD(24, 24) | ||
1409 | |||
1410 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | ||
1411 | #define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_SHIFT (1 << 24) | ||
1412 | #define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_MASK BITFIELD(24, 24) | ||
1413 | |||
1414 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | ||
1415 | #define OMAP4430_VP_IVA_TRANXDONE_EN_SHIFT (1 << 29) | ||
1416 | #define OMAP4430_VP_IVA_TRANXDONE_EN_MASK BITFIELD(29, 29) | ||
1417 | |||
1418 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | ||
1419 | #define OMAP4430_VP_IVA_TRANXDONE_ST_SHIFT (1 << 29) | ||
1420 | #define OMAP4430_VP_IVA_TRANXDONE_ST_MASK BITFIELD(29, 29) | ||
1421 | |||
1422 | /* Used by PRM_IRQENABLE_MPU_2 */ | ||
1423 | #define OMAP4430_VP_MPU_EQVALUE_EN_SHIFT (1 << 4) | ||
1424 | #define OMAP4430_VP_MPU_EQVALUE_EN_MASK BITFIELD(4, 4) | ||
1425 | |||
1426 | /* Used by PRM_IRQSTATUS_MPU_2 */ | ||
1427 | #define OMAP4430_VP_MPU_EQVALUE_ST_SHIFT (1 << 4) | ||
1428 | #define OMAP4430_VP_MPU_EQVALUE_ST_MASK BITFIELD(4, 4) | ||
1429 | |||
1430 | /* Used by PRM_IRQENABLE_MPU_2 */ | ||
1431 | #define OMAP4430_VP_MPU_MAXVDD_EN_SHIFT (1 << 2) | ||
1432 | #define OMAP4430_VP_MPU_MAXVDD_EN_MASK BITFIELD(2, 2) | ||
1433 | |||
1434 | /* Used by PRM_IRQSTATUS_MPU_2 */ | ||
1435 | #define OMAP4430_VP_MPU_MAXVDD_ST_SHIFT (1 << 2) | ||
1436 | #define OMAP4430_VP_MPU_MAXVDD_ST_MASK BITFIELD(2, 2) | ||
1437 | |||
1438 | /* Used by PRM_IRQENABLE_MPU_2 */ | ||
1439 | #define OMAP4430_VP_MPU_MINVDD_EN_SHIFT (1 << 1) | ||
1440 | #define OMAP4430_VP_MPU_MINVDD_EN_MASK BITFIELD(1, 1) | ||
1441 | |||
1442 | /* Used by PRM_IRQSTATUS_MPU_2 */ | ||
1443 | #define OMAP4430_VP_MPU_MINVDD_ST_SHIFT (1 << 1) | ||
1444 | #define OMAP4430_VP_MPU_MINVDD_ST_MASK BITFIELD(1, 1) | ||
1445 | |||
1446 | /* Used by PRM_IRQENABLE_MPU_2 */ | ||
1447 | #define OMAP4430_VP_MPU_NOSMPSACK_EN_SHIFT (1 << 3) | ||
1448 | #define OMAP4430_VP_MPU_NOSMPSACK_EN_MASK BITFIELD(3, 3) | ||
1449 | |||
1450 | /* Used by PRM_IRQSTATUS_MPU_2 */ | ||
1451 | #define OMAP4430_VP_MPU_NOSMPSACK_ST_SHIFT (1 << 3) | ||
1452 | #define OMAP4430_VP_MPU_NOSMPSACK_ST_MASK BITFIELD(3, 3) | ||
1453 | |||
1454 | /* Used by PRM_IRQENABLE_MPU_2 */ | ||
1455 | #define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_SHIFT (1 << 0) | ||
1456 | #define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_MASK BITFIELD(0, 0) | ||
1457 | |||
1458 | /* Used by PRM_IRQSTATUS_MPU_2 */ | ||
1459 | #define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_SHIFT (1 << 0) | ||
1460 | #define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_MASK BITFIELD(0, 0) | ||
1461 | |||
1462 | /* Used by PRM_IRQENABLE_MPU_2 */ | ||
1463 | #define OMAP4430_VP_MPU_TRANXDONE_EN_SHIFT (1 << 5) | ||
1464 | #define OMAP4430_VP_MPU_TRANXDONE_EN_MASK BITFIELD(5, 5) | ||
1465 | |||
1466 | /* Used by PRM_IRQSTATUS_MPU_2 */ | ||
1467 | #define OMAP4430_VP_MPU_TRANXDONE_ST_SHIFT (1 << 5) | ||
1468 | #define OMAP4430_VP_MPU_TRANXDONE_ST_MASK BITFIELD(5, 5) | ||
1469 | |||
1470 | /* Used by PRM_SRAM_COUNT */ | ||
1471 | #define OMAP4430_VSETUPCNT_VALUE_SHIFT (1 << 8) | ||
1472 | #define OMAP4430_VSETUPCNT_VALUE_MASK BITFIELD(8, 15) | ||
1473 | |||
1474 | /* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_IVA_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */ | ||
1475 | #define OMAP4430_VSTEPMAX_SHIFT (1 << 0) | ||
1476 | #define OMAP4430_VSTEPMAX_MASK BITFIELD(0, 7) | ||
1477 | |||
1478 | /* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_IVA_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */ | ||
1479 | #define OMAP4430_VSTEPMIN_SHIFT (1 << 0) | ||
1480 | #define OMAP4430_VSTEPMIN_MASK BITFIELD(0, 7) | ||
1481 | |||
1482 | /* Used by PRM_MODEM_IF_CTRL */ | ||
1483 | #define OMAP4430_WAKE_MODEM_SHIFT (1 << 0) | ||
1484 | #define OMAP4430_WAKE_MODEM_MASK BITFIELD(0, 0) | ||
1485 | |||
1486 | /* Used by PM_DSS_DSS_WKDEP */ | ||
1487 | #define OMAP4430_WKUPDEP_DISPC_DUCATI_SHIFT (1 << 1) | ||
1488 | #define OMAP4430_WKUPDEP_DISPC_DUCATI_MASK BITFIELD(1, 1) | ||
1489 | |||
1490 | /* Used by PM_DSS_DSS_WKDEP */ | ||
1491 | #define OMAP4430_WKUPDEP_DISPC_MPU_SHIFT (1 << 0) | ||
1492 | #define OMAP4430_WKUPDEP_DISPC_MPU_MASK BITFIELD(0, 0) | ||
1493 | |||
1494 | /* Used by PM_DSS_DSS_WKDEP */ | ||
1495 | #define OMAP4430_WKUPDEP_DISPC_SDMA_SHIFT (1 << 3) | ||
1496 | #define OMAP4430_WKUPDEP_DISPC_SDMA_MASK BITFIELD(3, 3) | ||
1497 | |||
1498 | /* Used by PM_DSS_DSS_WKDEP */ | ||
1499 | #define OMAP4430_WKUPDEP_DISPC_TESLA_SHIFT (1 << 2) | ||
1500 | #define OMAP4430_WKUPDEP_DISPC_TESLA_MASK BITFIELD(2, 2) | ||
1501 | |||
1502 | /* Used by PM_ABE_DMIC_WKDEP */ | ||
1503 | #define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_SHIFT (1 << 7) | ||
1504 | #define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_MASK BITFIELD(7, 7) | ||
1505 | |||
1506 | /* Used by PM_ABE_DMIC_WKDEP */ | ||
1507 | #define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_SHIFT (1 << 6) | ||
1508 | #define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_MASK BITFIELD(6, 6) | ||
1509 | |||
1510 | /* Used by PM_ABE_DMIC_WKDEP */ | ||
1511 | #define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_SHIFT (1 << 0) | ||
1512 | #define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_MASK BITFIELD(0, 0) | ||
1513 | |||
1514 | /* Used by PM_ABE_DMIC_WKDEP */ | ||
1515 | #define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_SHIFT (1 << 2) | ||
1516 | #define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_MASK BITFIELD(2, 2) | ||
1517 | |||
1518 | /* Used by PM_L4PER_DMTIMER10_WKDEP */ | ||
1519 | #define OMAP4430_WKUPDEP_DMTIMER10_MPU_SHIFT (1 << 0) | ||
1520 | #define OMAP4430_WKUPDEP_DMTIMER10_MPU_MASK BITFIELD(0, 0) | ||
1521 | |||
1522 | /* Used by PM_L4PER_DMTIMER11_WKDEP */ | ||
1523 | #define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_SHIFT (1 << 1) | ||
1524 | #define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_MASK BITFIELD(1, 1) | ||
1525 | |||
1526 | /* Used by PM_L4PER_DMTIMER11_WKDEP */ | ||
1527 | #define OMAP4430_WKUPDEP_DMTIMER11_MPU_SHIFT (1 << 0) | ||
1528 | #define OMAP4430_WKUPDEP_DMTIMER11_MPU_MASK BITFIELD(0, 0) | ||
1529 | |||
1530 | /* Used by PM_L4PER_DMTIMER2_WKDEP */ | ||
1531 | #define OMAP4430_WKUPDEP_DMTIMER2_MPU_SHIFT (1 << 0) | ||
1532 | #define OMAP4430_WKUPDEP_DMTIMER2_MPU_MASK BITFIELD(0, 0) | ||
1533 | |||
1534 | /* Used by PM_L4PER_DMTIMER3_WKDEP */ | ||
1535 | #define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_SHIFT (1 << 1) | ||
1536 | #define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_MASK BITFIELD(1, 1) | ||
1537 | |||
1538 | /* Used by PM_L4PER_DMTIMER3_WKDEP */ | ||
1539 | #define OMAP4430_WKUPDEP_DMTIMER3_MPU_SHIFT (1 << 0) | ||
1540 | #define OMAP4430_WKUPDEP_DMTIMER3_MPU_MASK BITFIELD(0, 0) | ||
1541 | |||
1542 | /* Used by PM_L4PER_DMTIMER4_WKDEP */ | ||
1543 | #define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_SHIFT (1 << 1) | ||
1544 | #define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_MASK BITFIELD(1, 1) | ||
1545 | |||
1546 | /* Used by PM_L4PER_DMTIMER4_WKDEP */ | ||
1547 | #define OMAP4430_WKUPDEP_DMTIMER4_MPU_SHIFT (1 << 0) | ||
1548 | #define OMAP4430_WKUPDEP_DMTIMER4_MPU_MASK BITFIELD(0, 0) | ||
1549 | |||
1550 | /* Used by PM_L4PER_DMTIMER9_WKDEP */ | ||
1551 | #define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_SHIFT (1 << 1) | ||
1552 | #define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_MASK BITFIELD(1, 1) | ||
1553 | |||
1554 | /* Used by PM_L4PER_DMTIMER9_WKDEP */ | ||
1555 | #define OMAP4430_WKUPDEP_DMTIMER9_MPU_SHIFT (1 << 0) | ||
1556 | #define OMAP4430_WKUPDEP_DMTIMER9_MPU_MASK BITFIELD(0, 0) | ||
1557 | |||
1558 | /* Used by PM_DSS_DSS_WKDEP */ | ||
1559 | #define OMAP4430_WKUPDEP_DSI1_DUCATI_SHIFT (1 << 5) | ||
1560 | #define OMAP4430_WKUPDEP_DSI1_DUCATI_MASK BITFIELD(5, 5) | ||
1561 | |||
1562 | /* Used by PM_DSS_DSS_WKDEP */ | ||
1563 | #define OMAP4430_WKUPDEP_DSI1_MPU_SHIFT (1 << 4) | ||
1564 | #define OMAP4430_WKUPDEP_DSI1_MPU_MASK BITFIELD(4, 4) | ||
1565 | |||
1566 | /* Used by PM_DSS_DSS_WKDEP */ | ||
1567 | #define OMAP4430_WKUPDEP_DSI1_SDMA_SHIFT (1 << 7) | ||
1568 | #define OMAP4430_WKUPDEP_DSI1_SDMA_MASK BITFIELD(7, 7) | ||
1569 | |||
1570 | /* Used by PM_DSS_DSS_WKDEP */ | ||
1571 | #define OMAP4430_WKUPDEP_DSI1_TESLA_SHIFT (1 << 6) | ||
1572 | #define OMAP4430_WKUPDEP_DSI1_TESLA_MASK BITFIELD(6, 6) | ||
1573 | |||
1574 | /* Used by PM_DSS_DSS_WKDEP */ | ||
1575 | #define OMAP4430_WKUPDEP_DSI2_DUCATI_SHIFT (1 << 9) | ||
1576 | #define OMAP4430_WKUPDEP_DSI2_DUCATI_MASK BITFIELD(9, 9) | ||
1577 | |||
1578 | /* Used by PM_DSS_DSS_WKDEP */ | ||
1579 | #define OMAP4430_WKUPDEP_DSI2_MPU_SHIFT (1 << 8) | ||
1580 | #define OMAP4430_WKUPDEP_DSI2_MPU_MASK BITFIELD(8, 8) | ||
1581 | |||
1582 | /* Used by PM_DSS_DSS_WKDEP */ | ||
1583 | #define OMAP4430_WKUPDEP_DSI2_SDMA_SHIFT (1 << 11) | ||
1584 | #define OMAP4430_WKUPDEP_DSI2_SDMA_MASK BITFIELD(11, 11) | ||
1585 | |||
1586 | /* Used by PM_DSS_DSS_WKDEP */ | ||
1587 | #define OMAP4430_WKUPDEP_DSI2_TESLA_SHIFT (1 << 10) | ||
1588 | #define OMAP4430_WKUPDEP_DSI2_TESLA_MASK BITFIELD(10, 10) | ||
1589 | |||
1590 | /* Used by PM_WKUP_GPIO1_WKDEP */ | ||
1591 | #define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_SHIFT (1 << 1) | ||
1592 | #define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_MASK BITFIELD(1, 1) | ||
1593 | |||
1594 | /* Used by PM_WKUP_GPIO1_WKDEP */ | ||
1595 | #define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_SHIFT (1 << 0) | ||
1596 | #define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_MASK BITFIELD(0, 0) | ||
1597 | |||
1598 | /* Used by PM_WKUP_GPIO1_WKDEP */ | ||
1599 | #define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_SHIFT (1 << 6) | ||
1600 | #define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_MASK BITFIELD(6, 6) | ||
1601 | |||
1602 | /* Used by PM_L4PER_GPIO2_WKDEP */ | ||
1603 | #define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_SHIFT (1 << 1) | ||
1604 | #define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_MASK BITFIELD(1, 1) | ||
1605 | |||
1606 | /* Used by PM_L4PER_GPIO2_WKDEP */ | ||
1607 | #define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_SHIFT (1 << 0) | ||
1608 | #define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_MASK BITFIELD(0, 0) | ||
1609 | |||
1610 | /* Used by PM_L4PER_GPIO2_WKDEP */ | ||
1611 | #define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_SHIFT (1 << 6) | ||
1612 | #define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_MASK BITFIELD(6, 6) | ||
1613 | |||
1614 | /* Used by PM_L4PER_GPIO3_WKDEP */ | ||
1615 | #define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_SHIFT (1 << 0) | ||
1616 | #define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_MASK BITFIELD(0, 0) | ||
1617 | |||
1618 | /* Used by PM_L4PER_GPIO3_WKDEP */ | ||
1619 | #define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_SHIFT (1 << 6) | ||
1620 | #define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_MASK BITFIELD(6, 6) | ||
1621 | |||
1622 | /* Used by PM_L4PER_GPIO4_WKDEP */ | ||
1623 | #define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_SHIFT (1 << 0) | ||
1624 | #define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_MASK BITFIELD(0, 0) | ||
1625 | |||
1626 | /* Used by PM_L4PER_GPIO4_WKDEP */ | ||
1627 | #define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_SHIFT (1 << 6) | ||
1628 | #define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_MASK BITFIELD(6, 6) | ||
1629 | |||
1630 | /* Used by PM_L4PER_GPIO5_WKDEP */ | ||
1631 | #define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_SHIFT (1 << 0) | ||
1632 | #define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_MASK BITFIELD(0, 0) | ||
1633 | |||
1634 | /* Used by PM_L4PER_GPIO5_WKDEP */ | ||
1635 | #define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_SHIFT (1 << 6) | ||
1636 | #define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_MASK BITFIELD(6, 6) | ||
1637 | |||
1638 | /* Used by PM_L4PER_GPIO6_WKDEP */ | ||
1639 | #define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_SHIFT (1 << 0) | ||
1640 | #define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_MASK BITFIELD(0, 0) | ||
1641 | |||
1642 | /* Used by PM_L4PER_GPIO6_WKDEP */ | ||
1643 | #define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_SHIFT (1 << 6) | ||
1644 | #define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_MASK BITFIELD(6, 6) | ||
1645 | |||
1646 | /* Used by PM_DSS_DSS_WKDEP */ | ||
1647 | #define OMAP4430_WKUPDEP_HDMIDMA_SDMA_SHIFT (1 << 19) | ||
1648 | #define OMAP4430_WKUPDEP_HDMIDMA_SDMA_MASK BITFIELD(19, 19) | ||
1649 | |||
1650 | /* Used by PM_DSS_DSS_WKDEP */ | ||
1651 | #define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_SHIFT (1 << 13) | ||
1652 | #define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_MASK BITFIELD(13, 13) | ||
1653 | |||
1654 | /* Used by PM_DSS_DSS_WKDEP */ | ||
1655 | #define OMAP4430_WKUPDEP_HDMIIRQ_MPU_SHIFT (1 << 12) | ||
1656 | #define OMAP4430_WKUPDEP_HDMIIRQ_MPU_MASK BITFIELD(12, 12) | ||
1657 | |||
1658 | /* Used by PM_DSS_DSS_WKDEP */ | ||
1659 | #define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_SHIFT (1 << 14) | ||
1660 | #define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_MASK BITFIELD(14, 14) | ||
1661 | |||
1662 | /* Used by PM_L4PER_HECC1_WKDEP */ | ||
1663 | #define OMAP4430_WKUPDEP_HECC1_MPU_SHIFT (1 << 0) | ||
1664 | #define OMAP4430_WKUPDEP_HECC1_MPU_MASK BITFIELD(0, 0) | ||
1665 | |||
1666 | /* Used by PM_L4PER_HECC2_WKDEP */ | ||
1667 | #define OMAP4430_WKUPDEP_HECC2_MPU_SHIFT (1 << 0) | ||
1668 | #define OMAP4430_WKUPDEP_HECC2_MPU_MASK BITFIELD(0, 0) | ||
1669 | |||
1670 | /* Used by PM_L3INIT_HSI_WKDEP */ | ||
1671 | #define OMAP4430_WKUPDEP_HSI_DSP_TESLA_SHIFT (1 << 6) | ||
1672 | #define OMAP4430_WKUPDEP_HSI_DSP_TESLA_MASK BITFIELD(6, 6) | ||
1673 | |||
1674 | /* Used by PM_L3INIT_HSI_WKDEP */ | ||
1675 | #define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_SHIFT (1 << 1) | ||
1676 | #define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_MASK BITFIELD(1, 1) | ||
1677 | |||
1678 | /* Used by PM_L3INIT_HSI_WKDEP */ | ||
1679 | #define OMAP4430_WKUPDEP_HSI_MCU_MPU_SHIFT (1 << 0) | ||
1680 | #define OMAP4430_WKUPDEP_HSI_MCU_MPU_MASK BITFIELD(0, 0) | ||
1681 | |||
1682 | /* Used by PM_L4PER_I2C1_WKDEP */ | ||
1683 | #define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_SHIFT (1 << 7) | ||
1684 | #define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_MASK BITFIELD(7, 7) | ||
1685 | |||
1686 | /* Used by PM_L4PER_I2C1_WKDEP */ | ||
1687 | #define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_SHIFT (1 << 1) | ||
1688 | #define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_MASK BITFIELD(1, 1) | ||
1689 | |||
1690 | /* Used by PM_L4PER_I2C1_WKDEP */ | ||
1691 | #define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_SHIFT (1 << 0) | ||
1692 | #define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_MASK BITFIELD(0, 0) | ||
1693 | |||
1694 | /* Used by PM_L4PER_I2C2_WKDEP */ | ||
1695 | #define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_SHIFT (1 << 7) | ||
1696 | #define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_MASK BITFIELD(7, 7) | ||
1697 | |||
1698 | /* Used by PM_L4PER_I2C2_WKDEP */ | ||
1699 | #define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_SHIFT (1 << 1) | ||
1700 | #define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_MASK BITFIELD(1, 1) | ||
1701 | |||
1702 | /* Used by PM_L4PER_I2C2_WKDEP */ | ||
1703 | #define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_SHIFT (1 << 0) | ||
1704 | #define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_MASK BITFIELD(0, 0) | ||
1705 | |||
1706 | /* Used by PM_L4PER_I2C3_WKDEP */ | ||
1707 | #define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_SHIFT (1 << 7) | ||
1708 | #define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_MASK BITFIELD(7, 7) | ||
1709 | |||
1710 | /* Used by PM_L4PER_I2C3_WKDEP */ | ||
1711 | #define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_SHIFT (1 << 1) | ||
1712 | #define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_MASK BITFIELD(1, 1) | ||
1713 | |||
1714 | /* Used by PM_L4PER_I2C3_WKDEP */ | ||
1715 | #define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_SHIFT (1 << 0) | ||
1716 | #define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_MASK BITFIELD(0, 0) | ||
1717 | |||
1718 | /* Used by PM_L4PER_I2C4_WKDEP */ | ||
1719 | #define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_SHIFT (1 << 7) | ||
1720 | #define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_MASK BITFIELD(7, 7) | ||
1721 | |||
1722 | /* Used by PM_L4PER_I2C4_WKDEP */ | ||
1723 | #define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_SHIFT (1 << 1) | ||
1724 | #define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_MASK BITFIELD(1, 1) | ||
1725 | |||
1726 | /* Used by PM_L4PER_I2C4_WKDEP */ | ||
1727 | #define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_SHIFT (1 << 0) | ||
1728 | #define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_MASK BITFIELD(0, 0) | ||
1729 | |||
1730 | /* Used by PM_L4PER_I2C5_WKDEP */ | ||
1731 | #define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_SHIFT (1 << 7) | ||
1732 | #define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_MASK BITFIELD(7, 7) | ||
1733 | |||
1734 | /* Used by PM_L4PER_I2C5_WKDEP */ | ||
1735 | #define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_SHIFT (1 << 0) | ||
1736 | #define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_MASK BITFIELD(0, 0) | ||
1737 | |||
1738 | /* Used by PM_WKUP_KEYBOARD_WKDEP */ | ||
1739 | #define OMAP4430_WKUPDEP_KEYBOARD_MPU_SHIFT (1 << 0) | ||
1740 | #define OMAP4430_WKUPDEP_KEYBOARD_MPU_MASK BITFIELD(0, 0) | ||
1741 | |||
1742 | /* Used by PM_ABE_MCASP_WKDEP */ | ||
1743 | #define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_SHIFT (1 << 7) | ||
1744 | #define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_MASK BITFIELD(7, 7) | ||
1745 | |||
1746 | /* Used by PM_ABE_MCASP_WKDEP */ | ||
1747 | #define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_SHIFT (1 << 6) | ||
1748 | #define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_MASK BITFIELD(6, 6) | ||
1749 | |||
1750 | /* Used by PM_ABE_MCASP_WKDEP */ | ||
1751 | #define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_SHIFT (1 << 0) | ||
1752 | #define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_MASK BITFIELD(0, 0) | ||
1753 | |||
1754 | /* Used by PM_ABE_MCASP_WKDEP */ | ||
1755 | #define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_SHIFT (1 << 2) | ||
1756 | #define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_MASK BITFIELD(2, 2) | ||
1757 | |||
1758 | /* Used by PM_L4PER_MCASP2_WKDEP */ | ||
1759 | #define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_SHIFT (1 << 7) | ||
1760 | #define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_MASK BITFIELD(7, 7) | ||
1761 | |||
1762 | /* Used by PM_L4PER_MCASP2_WKDEP */ | ||
1763 | #define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_SHIFT (1 << 6) | ||
1764 | #define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_MASK BITFIELD(6, 6) | ||
1765 | |||
1766 | /* Used by PM_L4PER_MCASP2_WKDEP */ | ||
1767 | #define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_SHIFT (1 << 0) | ||
1768 | #define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_MASK BITFIELD(0, 0) | ||
1769 | |||
1770 | /* Used by PM_L4PER_MCASP2_WKDEP */ | ||
1771 | #define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_SHIFT (1 << 2) | ||
1772 | #define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_MASK BITFIELD(2, 2) | ||
1773 | |||
1774 | /* Used by PM_L4PER_MCASP3_WKDEP */ | ||
1775 | #define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_SHIFT (1 << 7) | ||
1776 | #define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_MASK BITFIELD(7, 7) | ||
1777 | |||
1778 | /* Used by PM_L4PER_MCASP3_WKDEP */ | ||
1779 | #define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_SHIFT (1 << 6) | ||
1780 | #define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_MASK BITFIELD(6, 6) | ||
1781 | |||
1782 | /* Used by PM_L4PER_MCASP3_WKDEP */ | ||
1783 | #define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_SHIFT (1 << 0) | ||
1784 | #define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_MASK BITFIELD(0, 0) | ||
1785 | |||
1786 | /* Used by PM_L4PER_MCASP3_WKDEP */ | ||
1787 | #define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_SHIFT (1 << 2) | ||
1788 | #define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_MASK BITFIELD(2, 2) | ||
1789 | |||
1790 | /* Used by PM_ABE_MCBSP1_WKDEP */ | ||
1791 | #define OMAP4430_WKUPDEP_MCBSP1_MPU_SHIFT (1 << 0) | ||
1792 | #define OMAP4430_WKUPDEP_MCBSP1_MPU_MASK BITFIELD(0, 0) | ||
1793 | |||
1794 | /* Used by PM_ABE_MCBSP1_WKDEP */ | ||
1795 | #define OMAP4430_WKUPDEP_MCBSP1_SDMA_SHIFT (1 << 3) | ||
1796 | #define OMAP4430_WKUPDEP_MCBSP1_SDMA_MASK BITFIELD(3, 3) | ||
1797 | |||
1798 | /* Used by PM_ABE_MCBSP1_WKDEP */ | ||
1799 | #define OMAP4430_WKUPDEP_MCBSP1_TESLA_SHIFT (1 << 2) | ||
1800 | #define OMAP4430_WKUPDEP_MCBSP1_TESLA_MASK BITFIELD(2, 2) | ||
1801 | |||
1802 | /* Used by PM_ABE_MCBSP2_WKDEP */ | ||
1803 | #define OMAP4430_WKUPDEP_MCBSP2_MPU_SHIFT (1 << 0) | ||
1804 | #define OMAP4430_WKUPDEP_MCBSP2_MPU_MASK BITFIELD(0, 0) | ||
1805 | |||
1806 | /* Used by PM_ABE_MCBSP2_WKDEP */ | ||
1807 | #define OMAP4430_WKUPDEP_MCBSP2_SDMA_SHIFT (1 << 3) | ||
1808 | #define OMAP4430_WKUPDEP_MCBSP2_SDMA_MASK BITFIELD(3, 3) | ||
1809 | |||
1810 | /* Used by PM_ABE_MCBSP2_WKDEP */ | ||
1811 | #define OMAP4430_WKUPDEP_MCBSP2_TESLA_SHIFT (1 << 2) | ||
1812 | #define OMAP4430_WKUPDEP_MCBSP2_TESLA_MASK BITFIELD(2, 2) | ||
1813 | |||
1814 | /* Used by PM_ABE_MCBSP3_WKDEP */ | ||
1815 | #define OMAP4430_WKUPDEP_MCBSP3_MPU_SHIFT (1 << 0) | ||
1816 | #define OMAP4430_WKUPDEP_MCBSP3_MPU_MASK BITFIELD(0, 0) | ||
1817 | |||
1818 | /* Used by PM_ABE_MCBSP3_WKDEP */ | ||
1819 | #define OMAP4430_WKUPDEP_MCBSP3_SDMA_SHIFT (1 << 3) | ||
1820 | #define OMAP4430_WKUPDEP_MCBSP3_SDMA_MASK BITFIELD(3, 3) | ||
1821 | |||
1822 | /* Used by PM_ABE_MCBSP3_WKDEP */ | ||
1823 | #define OMAP4430_WKUPDEP_MCBSP3_TESLA_SHIFT (1 << 2) | ||
1824 | #define OMAP4430_WKUPDEP_MCBSP3_TESLA_MASK BITFIELD(2, 2) | ||
1825 | |||
1826 | /* Used by PM_L4PER_MCBSP4_WKDEP */ | ||
1827 | #define OMAP4430_WKUPDEP_MCBSP4_MPU_SHIFT (1 << 0) | ||
1828 | #define OMAP4430_WKUPDEP_MCBSP4_MPU_MASK BITFIELD(0, 0) | ||
1829 | |||
1830 | /* Used by PM_L4PER_MCBSP4_WKDEP */ | ||
1831 | #define OMAP4430_WKUPDEP_MCBSP4_SDMA_SHIFT (1 << 3) | ||
1832 | #define OMAP4430_WKUPDEP_MCBSP4_SDMA_MASK BITFIELD(3, 3) | ||
1833 | |||
1834 | /* Used by PM_L4PER_MCBSP4_WKDEP */ | ||
1835 | #define OMAP4430_WKUPDEP_MCBSP4_TESLA_SHIFT (1 << 2) | ||
1836 | #define OMAP4430_WKUPDEP_MCBSP4_TESLA_MASK BITFIELD(2, 2) | ||
1837 | |||
1838 | /* Used by PM_L4PER_MCSPI1_WKDEP */ | ||
1839 | #define OMAP4430_WKUPDEP_MCSPI1_DUCATI_SHIFT (1 << 1) | ||
1840 | #define OMAP4430_WKUPDEP_MCSPI1_DUCATI_MASK BITFIELD(1, 1) | ||
1841 | |||
1842 | /* Used by PM_L4PER_MCSPI1_WKDEP */ | ||
1843 | #define OMAP4430_WKUPDEP_MCSPI1_MPU_SHIFT (1 << 0) | ||
1844 | #define OMAP4430_WKUPDEP_MCSPI1_MPU_MASK BITFIELD(0, 0) | ||
1845 | |||
1846 | /* Used by PM_L4PER_MCSPI1_WKDEP */ | ||
1847 | #define OMAP4430_WKUPDEP_MCSPI1_SDMA_SHIFT (1 << 3) | ||
1848 | #define OMAP4430_WKUPDEP_MCSPI1_SDMA_MASK BITFIELD(3, 3) | ||
1849 | |||
1850 | /* Used by PM_L4PER_MCSPI1_WKDEP */ | ||
1851 | #define OMAP4430_WKUPDEP_MCSPI1_TESLA_SHIFT (1 << 2) | ||
1852 | #define OMAP4430_WKUPDEP_MCSPI1_TESLA_MASK BITFIELD(2, 2) | ||
1853 | |||
1854 | /* Used by PM_L4PER_MCSPI2_WKDEP */ | ||
1855 | #define OMAP4430_WKUPDEP_MCSPI2_DUCATI_SHIFT (1 << 1) | ||
1856 | #define OMAP4430_WKUPDEP_MCSPI2_DUCATI_MASK BITFIELD(1, 1) | ||
1857 | |||
1858 | /* Used by PM_L4PER_MCSPI2_WKDEP */ | ||
1859 | #define OMAP4430_WKUPDEP_MCSPI2_MPU_SHIFT (1 << 0) | ||
1860 | #define OMAP4430_WKUPDEP_MCSPI2_MPU_MASK BITFIELD(0, 0) | ||
1861 | |||
1862 | /* Used by PM_L4PER_MCSPI2_WKDEP */ | ||
1863 | #define OMAP4430_WKUPDEP_MCSPI2_SDMA_SHIFT (1 << 3) | ||
1864 | #define OMAP4430_WKUPDEP_MCSPI2_SDMA_MASK BITFIELD(3, 3) | ||
1865 | |||
1866 | /* Used by PM_L4PER_MCSPI3_WKDEP */ | ||
1867 | #define OMAP4430_WKUPDEP_MCSPI3_MPU_SHIFT (1 << 0) | ||
1868 | #define OMAP4430_WKUPDEP_MCSPI3_MPU_MASK BITFIELD(0, 0) | ||
1869 | |||
1870 | /* Used by PM_L4PER_MCSPI3_WKDEP */ | ||
1871 | #define OMAP4430_WKUPDEP_MCSPI3_SDMA_SHIFT (1 << 3) | ||
1872 | #define OMAP4430_WKUPDEP_MCSPI3_SDMA_MASK BITFIELD(3, 3) | ||
1873 | |||
1874 | /* Used by PM_L4PER_MCSPI4_WKDEP */ | ||
1875 | #define OMAP4430_WKUPDEP_MCSPI4_MPU_SHIFT (1 << 0) | ||
1876 | #define OMAP4430_WKUPDEP_MCSPI4_MPU_MASK BITFIELD(0, 0) | ||
1877 | |||
1878 | /* Used by PM_L4PER_MCSPI4_WKDEP */ | ||
1879 | #define OMAP4430_WKUPDEP_MCSPI4_SDMA_SHIFT (1 << 3) | ||
1880 | #define OMAP4430_WKUPDEP_MCSPI4_SDMA_MASK BITFIELD(3, 3) | ||
1881 | |||
1882 | /* Used by PM_L3INIT_MMC1_WKDEP */ | ||
1883 | #define OMAP4430_WKUPDEP_MMC1_DUCATI_SHIFT (1 << 1) | ||
1884 | #define OMAP4430_WKUPDEP_MMC1_DUCATI_MASK BITFIELD(1, 1) | ||
1885 | |||
1886 | /* Used by PM_L3INIT_MMC1_WKDEP */ | ||
1887 | #define OMAP4430_WKUPDEP_MMC1_MPU_SHIFT (1 << 0) | ||
1888 | #define OMAP4430_WKUPDEP_MMC1_MPU_MASK BITFIELD(0, 0) | ||
1889 | |||
1890 | /* Used by PM_L3INIT_MMC1_WKDEP */ | ||
1891 | #define OMAP4430_WKUPDEP_MMC1_SDMA_SHIFT (1 << 3) | ||
1892 | #define OMAP4430_WKUPDEP_MMC1_SDMA_MASK BITFIELD(3, 3) | ||
1893 | |||
1894 | /* Used by PM_L3INIT_MMC1_WKDEP */ | ||
1895 | #define OMAP4430_WKUPDEP_MMC1_TESLA_SHIFT (1 << 2) | ||
1896 | #define OMAP4430_WKUPDEP_MMC1_TESLA_MASK BITFIELD(2, 2) | ||
1897 | |||
1898 | /* Used by PM_L3INIT_MMC2_WKDEP */ | ||
1899 | #define OMAP4430_WKUPDEP_MMC2_DUCATI_SHIFT (1 << 1) | ||
1900 | #define OMAP4430_WKUPDEP_MMC2_DUCATI_MASK BITFIELD(1, 1) | ||
1901 | |||
1902 | /* Used by PM_L3INIT_MMC2_WKDEP */ | ||
1903 | #define OMAP4430_WKUPDEP_MMC2_MPU_SHIFT (1 << 0) | ||
1904 | #define OMAP4430_WKUPDEP_MMC2_MPU_MASK BITFIELD(0, 0) | ||
1905 | |||
1906 | /* Used by PM_L3INIT_MMC2_WKDEP */ | ||
1907 | #define OMAP4430_WKUPDEP_MMC2_SDMA_SHIFT (1 << 3) | ||
1908 | #define OMAP4430_WKUPDEP_MMC2_SDMA_MASK BITFIELD(3, 3) | ||
1909 | |||
1910 | /* Used by PM_L3INIT_MMC2_WKDEP */ | ||
1911 | #define OMAP4430_WKUPDEP_MMC2_TESLA_SHIFT (1 << 2) | ||
1912 | #define OMAP4430_WKUPDEP_MMC2_TESLA_MASK BITFIELD(2, 2) | ||
1913 | |||
1914 | /* Used by PM_L3INIT_MMC6_WKDEP */ | ||
1915 | #define OMAP4430_WKUPDEP_MMC6_DUCATI_SHIFT (1 << 1) | ||
1916 | #define OMAP4430_WKUPDEP_MMC6_DUCATI_MASK BITFIELD(1, 1) | ||
1917 | |||
1918 | /* Used by PM_L3INIT_MMC6_WKDEP */ | ||
1919 | #define OMAP4430_WKUPDEP_MMC6_MPU_SHIFT (1 << 0) | ||
1920 | #define OMAP4430_WKUPDEP_MMC6_MPU_MASK BITFIELD(0, 0) | ||
1921 | |||
1922 | /* Used by PM_L3INIT_MMC6_WKDEP */ | ||
1923 | #define OMAP4430_WKUPDEP_MMC6_TESLA_SHIFT (1 << 2) | ||
1924 | #define OMAP4430_WKUPDEP_MMC6_TESLA_MASK BITFIELD(2, 2) | ||
1925 | |||
1926 | /* Used by PM_L4PER_MMCSD3_WKDEP */ | ||
1927 | #define OMAP4430_WKUPDEP_MMCSD3_DUCATI_SHIFT (1 << 1) | ||
1928 | #define OMAP4430_WKUPDEP_MMCSD3_DUCATI_MASK BITFIELD(1, 1) | ||
1929 | |||
1930 | /* Used by PM_L4PER_MMCSD3_WKDEP */ | ||
1931 | #define OMAP4430_WKUPDEP_MMCSD3_MPU_SHIFT (1 << 0) | ||
1932 | #define OMAP4430_WKUPDEP_MMCSD3_MPU_MASK BITFIELD(0, 0) | ||
1933 | |||
1934 | /* Used by PM_L4PER_MMCSD3_WKDEP */ | ||
1935 | #define OMAP4430_WKUPDEP_MMCSD3_SDMA_SHIFT (1 << 3) | ||
1936 | #define OMAP4430_WKUPDEP_MMCSD3_SDMA_MASK BITFIELD(3, 3) | ||
1937 | |||
1938 | /* Used by PM_L4PER_MMCSD4_WKDEP */ | ||
1939 | #define OMAP4430_WKUPDEP_MMCSD4_DUCATI_SHIFT (1 << 1) | ||
1940 | #define OMAP4430_WKUPDEP_MMCSD4_DUCATI_MASK BITFIELD(1, 1) | ||
1941 | |||
1942 | /* Used by PM_L4PER_MMCSD4_WKDEP */ | ||
1943 | #define OMAP4430_WKUPDEP_MMCSD4_MPU_SHIFT (1 << 0) | ||
1944 | #define OMAP4430_WKUPDEP_MMCSD4_MPU_MASK BITFIELD(0, 0) | ||
1945 | |||
1946 | /* Used by PM_L4PER_MMCSD4_WKDEP */ | ||
1947 | #define OMAP4430_WKUPDEP_MMCSD4_SDMA_SHIFT (1 << 3) | ||
1948 | #define OMAP4430_WKUPDEP_MMCSD4_SDMA_MASK BITFIELD(3, 3) | ||
1949 | |||
1950 | /* Used by PM_L4PER_MMCSD5_WKDEP */ | ||
1951 | #define OMAP4430_WKUPDEP_MMCSD5_DUCATI_SHIFT (1 << 1) | ||
1952 | #define OMAP4430_WKUPDEP_MMCSD5_DUCATI_MASK BITFIELD(1, 1) | ||
1953 | |||
1954 | /* Used by PM_L4PER_MMCSD5_WKDEP */ | ||
1955 | #define OMAP4430_WKUPDEP_MMCSD5_MPU_SHIFT (1 << 0) | ||
1956 | #define OMAP4430_WKUPDEP_MMCSD5_MPU_MASK BITFIELD(0, 0) | ||
1957 | |||
1958 | /* Used by PM_L4PER_MMCSD5_WKDEP */ | ||
1959 | #define OMAP4430_WKUPDEP_MMCSD5_SDMA_SHIFT (1 << 3) | ||
1960 | #define OMAP4430_WKUPDEP_MMCSD5_SDMA_MASK BITFIELD(3, 3) | ||
1961 | |||
1962 | /* Used by PM_L3INIT_PCIESS_WKDEP */ | ||
1963 | #define OMAP4430_WKUPDEP_PCIESS_MPU_SHIFT (1 << 0) | ||
1964 | #define OMAP4430_WKUPDEP_PCIESS_MPU_MASK BITFIELD(0, 0) | ||
1965 | |||
1966 | /* Used by PM_L3INIT_PCIESS_WKDEP */ | ||
1967 | #define OMAP4430_WKUPDEP_PCIESS_TESLA_SHIFT (1 << 2) | ||
1968 | #define OMAP4430_WKUPDEP_PCIESS_TESLA_MASK BITFIELD(2, 2) | ||
1969 | |||
1970 | /* Used by PM_ABE_PDM_WKDEP */ | ||
1971 | #define OMAP4430_WKUPDEP_PDM_DMA_SDMA_SHIFT (1 << 7) | ||
1972 | #define OMAP4430_WKUPDEP_PDM_DMA_SDMA_MASK BITFIELD(7, 7) | ||
1973 | |||
1974 | /* Used by PM_ABE_PDM_WKDEP */ | ||
1975 | #define OMAP4430_WKUPDEP_PDM_DMA_TESLA_SHIFT (1 << 6) | ||
1976 | #define OMAP4430_WKUPDEP_PDM_DMA_TESLA_MASK BITFIELD(6, 6) | ||
1977 | |||
1978 | /* Used by PM_ABE_PDM_WKDEP */ | ||
1979 | #define OMAP4430_WKUPDEP_PDM_IRQ_MPU_SHIFT (1 << 0) | ||
1980 | #define OMAP4430_WKUPDEP_PDM_IRQ_MPU_MASK BITFIELD(0, 0) | ||
1981 | |||
1982 | /* Used by PM_ABE_PDM_WKDEP */ | ||
1983 | #define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_SHIFT (1 << 2) | ||
1984 | #define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_MASK BITFIELD(2, 2) | ||
1985 | |||
1986 | /* Used by PM_WKUP_RTC_WKDEP */ | ||
1987 | #define OMAP4430_WKUPDEP_RTC_MPU_SHIFT (1 << 0) | ||
1988 | #define OMAP4430_WKUPDEP_RTC_MPU_MASK BITFIELD(0, 0) | ||
1989 | |||
1990 | /* Used by PM_L3INIT_SATA_WKDEP */ | ||
1991 | #define OMAP4430_WKUPDEP_SATA_MPU_SHIFT (1 << 0) | ||
1992 | #define OMAP4430_WKUPDEP_SATA_MPU_MASK BITFIELD(0, 0) | ||
1993 | |||
1994 | /* Used by PM_L3INIT_SATA_WKDEP */ | ||
1995 | #define OMAP4430_WKUPDEP_SATA_TESLA_SHIFT (1 << 2) | ||
1996 | #define OMAP4430_WKUPDEP_SATA_TESLA_MASK BITFIELD(2, 2) | ||
1997 | |||
1998 | /* Used by PM_ABE_SLIMBUS_WKDEP */ | ||
1999 | #define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_SHIFT (1 << 7) | ||
2000 | #define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_MASK BITFIELD(7, 7) | ||
2001 | |||
2002 | /* Used by PM_ABE_SLIMBUS_WKDEP */ | ||
2003 | #define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_SHIFT (1 << 6) | ||
2004 | #define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_MASK BITFIELD(6, 6) | ||
2005 | |||
2006 | /* Used by PM_ABE_SLIMBUS_WKDEP */ | ||
2007 | #define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_SHIFT (1 << 0) | ||
2008 | #define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_MASK BITFIELD(0, 0) | ||
2009 | |||
2010 | /* Used by PM_ABE_SLIMBUS_WKDEP */ | ||
2011 | #define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_SHIFT (1 << 2) | ||
2012 | #define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_MASK BITFIELD(2, 2) | ||
2013 | |||
2014 | /* Used by PM_L4PER_SLIMBUS2_WKDEP */ | ||
2015 | #define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_SHIFT (1 << 7) | ||
2016 | #define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_MASK BITFIELD(7, 7) | ||
2017 | |||
2018 | /* Used by PM_L4PER_SLIMBUS2_WKDEP */ | ||
2019 | #define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_SHIFT (1 << 6) | ||
2020 | #define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_MASK BITFIELD(6, 6) | ||
2021 | |||
2022 | /* Used by PM_L4PER_SLIMBUS2_WKDEP */ | ||
2023 | #define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_SHIFT (1 << 0) | ||
2024 | #define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_MASK BITFIELD(0, 0) | ||
2025 | |||
2026 | /* Used by PM_L4PER_SLIMBUS2_WKDEP */ | ||
2027 | #define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_SHIFT (1 << 2) | ||
2028 | #define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_MASK BITFIELD(2, 2) | ||
2029 | |||
2030 | /* Used by PM_ALWON_SR_CORE_WKDEP */ | ||
2031 | #define OMAP4430_WKUPDEP_SR_CORE_DUCATI_SHIFT (1 << 1) | ||
2032 | #define OMAP4430_WKUPDEP_SR_CORE_DUCATI_MASK BITFIELD(1, 1) | ||
2033 | |||
2034 | /* Used by PM_ALWON_SR_CORE_WKDEP */ | ||
2035 | #define OMAP4430_WKUPDEP_SR_CORE_MPU_SHIFT (1 << 0) | ||
2036 | #define OMAP4430_WKUPDEP_SR_CORE_MPU_MASK BITFIELD(0, 0) | ||
2037 | |||
2038 | /* Used by PM_ALWON_SR_IVA_WKDEP */ | ||
2039 | #define OMAP4430_WKUPDEP_SR_IVA_DUCATI_SHIFT (1 << 1) | ||
2040 | #define OMAP4430_WKUPDEP_SR_IVA_DUCATI_MASK BITFIELD(1, 1) | ||
2041 | |||
2042 | /* Used by PM_ALWON_SR_IVA_WKDEP */ | ||
2043 | #define OMAP4430_WKUPDEP_SR_IVA_MPU_SHIFT (1 << 0) | ||
2044 | #define OMAP4430_WKUPDEP_SR_IVA_MPU_MASK BITFIELD(0, 0) | ||
2045 | |||
2046 | /* Used by PM_ALWON_SR_MPU_WKDEP */ | ||
2047 | #define OMAP4430_WKUPDEP_SR_MPU_MPU_SHIFT (1 << 0) | ||
2048 | #define OMAP4430_WKUPDEP_SR_MPU_MPU_MASK BITFIELD(0, 0) | ||
2049 | |||
2050 | /* Used by PM_WKUP_TIMER12_WKDEP */ | ||
2051 | #define OMAP4430_WKUPDEP_TIMER12_MPU_SHIFT (1 << 0) | ||
2052 | #define OMAP4430_WKUPDEP_TIMER12_MPU_MASK BITFIELD(0, 0) | ||
2053 | |||
2054 | /* Used by PM_WKUP_TIMER1_WKDEP */ | ||
2055 | #define OMAP4430_WKUPDEP_TIMER1_MPU_SHIFT (1 << 0) | ||
2056 | #define OMAP4430_WKUPDEP_TIMER1_MPU_MASK BITFIELD(0, 0) | ||
2057 | |||
2058 | /* Used by PM_ABE_TIMER5_WKDEP */ | ||
2059 | #define OMAP4430_WKUPDEP_TIMER5_MPU_SHIFT (1 << 0) | ||
2060 | #define OMAP4430_WKUPDEP_TIMER5_MPU_MASK BITFIELD(0, 0) | ||
2061 | |||
2062 | /* Used by PM_ABE_TIMER5_WKDEP */ | ||
2063 | #define OMAP4430_WKUPDEP_TIMER5_TESLA_SHIFT (1 << 2) | ||
2064 | #define OMAP4430_WKUPDEP_TIMER5_TESLA_MASK BITFIELD(2, 2) | ||
2065 | |||
2066 | /* Used by PM_ABE_TIMER6_WKDEP */ | ||
2067 | #define OMAP4430_WKUPDEP_TIMER6_MPU_SHIFT (1 << 0) | ||
2068 | #define OMAP4430_WKUPDEP_TIMER6_MPU_MASK BITFIELD(0, 0) | ||
2069 | |||
2070 | /* Used by PM_ABE_TIMER6_WKDEP */ | ||
2071 | #define OMAP4430_WKUPDEP_TIMER6_TESLA_SHIFT (1 << 2) | ||
2072 | #define OMAP4430_WKUPDEP_TIMER6_TESLA_MASK BITFIELD(2, 2) | ||
2073 | |||
2074 | /* Used by PM_ABE_TIMER7_WKDEP */ | ||
2075 | #define OMAP4430_WKUPDEP_TIMER7_MPU_SHIFT (1 << 0) | ||
2076 | #define OMAP4430_WKUPDEP_TIMER7_MPU_MASK BITFIELD(0, 0) | ||
2077 | |||
2078 | /* Used by PM_ABE_TIMER7_WKDEP */ | ||
2079 | #define OMAP4430_WKUPDEP_TIMER7_TESLA_SHIFT (1 << 2) | ||
2080 | #define OMAP4430_WKUPDEP_TIMER7_TESLA_MASK BITFIELD(2, 2) | ||
2081 | |||
2082 | /* Used by PM_ABE_TIMER8_WKDEP */ | ||
2083 | #define OMAP4430_WKUPDEP_TIMER8_MPU_SHIFT (1 << 0) | ||
2084 | #define OMAP4430_WKUPDEP_TIMER8_MPU_MASK BITFIELD(0, 0) | ||
2085 | |||
2086 | /* Used by PM_ABE_TIMER8_WKDEP */ | ||
2087 | #define OMAP4430_WKUPDEP_TIMER8_TESLA_SHIFT (1 << 2) | ||
2088 | #define OMAP4430_WKUPDEP_TIMER8_TESLA_MASK BITFIELD(2, 2) | ||
2089 | |||
2090 | /* Used by PM_L4PER_UART1_WKDEP */ | ||
2091 | #define OMAP4430_WKUPDEP_UART1_MPU_SHIFT (1 << 0) | ||
2092 | #define OMAP4430_WKUPDEP_UART1_MPU_MASK BITFIELD(0, 0) | ||
2093 | |||
2094 | /* Used by PM_L4PER_UART1_WKDEP */ | ||
2095 | #define OMAP4430_WKUPDEP_UART1_SDMA_SHIFT (1 << 3) | ||
2096 | #define OMAP4430_WKUPDEP_UART1_SDMA_MASK BITFIELD(3, 3) | ||
2097 | |||
2098 | /* Used by PM_L4PER_UART2_WKDEP */ | ||
2099 | #define OMAP4430_WKUPDEP_UART2_MPU_SHIFT (1 << 0) | ||
2100 | #define OMAP4430_WKUPDEP_UART2_MPU_MASK BITFIELD(0, 0) | ||
2101 | |||
2102 | /* Used by PM_L4PER_UART2_WKDEP */ | ||
2103 | #define OMAP4430_WKUPDEP_UART2_SDMA_SHIFT (1 << 3) | ||
2104 | #define OMAP4430_WKUPDEP_UART2_SDMA_MASK BITFIELD(3, 3) | ||
2105 | |||
2106 | /* Used by PM_L4PER_UART3_WKDEP */ | ||
2107 | #define OMAP4430_WKUPDEP_UART3_DUCATI_SHIFT (1 << 1) | ||
2108 | #define OMAP4430_WKUPDEP_UART3_DUCATI_MASK BITFIELD(1, 1) | ||
2109 | |||
2110 | /* Used by PM_L4PER_UART3_WKDEP */ | ||
2111 | #define OMAP4430_WKUPDEP_UART3_MPU_SHIFT (1 << 0) | ||
2112 | #define OMAP4430_WKUPDEP_UART3_MPU_MASK BITFIELD(0, 0) | ||
2113 | |||
2114 | /* Used by PM_L4PER_UART3_WKDEP */ | ||
2115 | #define OMAP4430_WKUPDEP_UART3_SDMA_SHIFT (1 << 3) | ||
2116 | #define OMAP4430_WKUPDEP_UART3_SDMA_MASK BITFIELD(3, 3) | ||
2117 | |||
2118 | /* Used by PM_L4PER_UART3_WKDEP */ | ||
2119 | #define OMAP4430_WKUPDEP_UART3_TESLA_SHIFT (1 << 2) | ||
2120 | #define OMAP4430_WKUPDEP_UART3_TESLA_MASK BITFIELD(2, 2) | ||
2121 | |||
2122 | /* Used by PM_L4PER_UART4_WKDEP */ | ||
2123 | #define OMAP4430_WKUPDEP_UART4_MPU_SHIFT (1 << 0) | ||
2124 | #define OMAP4430_WKUPDEP_UART4_MPU_MASK BITFIELD(0, 0) | ||
2125 | |||
2126 | /* Used by PM_L4PER_UART4_WKDEP */ | ||
2127 | #define OMAP4430_WKUPDEP_UART4_SDMA_SHIFT (1 << 3) | ||
2128 | #define OMAP4430_WKUPDEP_UART4_SDMA_MASK BITFIELD(3, 3) | ||
2129 | |||
2130 | /* Used by PM_L3INIT_UNIPRO1_WKDEP */ | ||
2131 | #define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_SHIFT (1 << 1) | ||
2132 | #define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_MASK BITFIELD(1, 1) | ||
2133 | |||
2134 | /* Used by PM_L3INIT_UNIPRO1_WKDEP */ | ||
2135 | #define OMAP4430_WKUPDEP_UNIPRO1_MPU_SHIFT (1 << 0) | ||
2136 | #define OMAP4430_WKUPDEP_UNIPRO1_MPU_MASK BITFIELD(0, 0) | ||
2137 | |||
2138 | /* Used by PM_L3INIT_USB_HOST_WKDEP */ | ||
2139 | #define OMAP4430_WKUPDEP_USB_HOST_DUCATI_SHIFT (1 << 1) | ||
2140 | #define OMAP4430_WKUPDEP_USB_HOST_DUCATI_MASK BITFIELD(1, 1) | ||
2141 | |||
2142 | /* Used by PM_L3INIT_USB_HOST_FS_WKDEP */ | ||
2143 | #define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_SHIFT (1 << 1) | ||
2144 | #define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_MASK BITFIELD(1, 1) | ||
2145 | |||
2146 | /* Used by PM_L3INIT_USB_HOST_FS_WKDEP */ | ||
2147 | #define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_SHIFT (1 << 0) | ||
2148 | #define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_MASK BITFIELD(0, 0) | ||
2149 | |||
2150 | /* Used by PM_L3INIT_USB_HOST_WKDEP */ | ||
2151 | #define OMAP4430_WKUPDEP_USB_HOST_MPU_SHIFT (1 << 0) | ||
2152 | #define OMAP4430_WKUPDEP_USB_HOST_MPU_MASK BITFIELD(0, 0) | ||
2153 | |||
2154 | /* Used by PM_L3INIT_USB_OTG_WKDEP */ | ||
2155 | #define OMAP4430_WKUPDEP_USB_OTG_DUCATI_SHIFT (1 << 1) | ||
2156 | #define OMAP4430_WKUPDEP_USB_OTG_DUCATI_MASK BITFIELD(1, 1) | ||
2157 | |||
2158 | /* Used by PM_L3INIT_USB_OTG_WKDEP */ | ||
2159 | #define OMAP4430_WKUPDEP_USB_OTG_MPU_SHIFT (1 << 0) | ||
2160 | #define OMAP4430_WKUPDEP_USB_OTG_MPU_MASK BITFIELD(0, 0) | ||
2161 | |||
2162 | /* Used by PM_L3INIT_USB_TLL_WKDEP */ | ||
2163 | #define OMAP4430_WKUPDEP_USB_TLL_DUCATI_SHIFT (1 << 1) | ||
2164 | #define OMAP4430_WKUPDEP_USB_TLL_DUCATI_MASK BITFIELD(1, 1) | ||
2165 | |||
2166 | /* Used by PM_L3INIT_USB_TLL_WKDEP */ | ||
2167 | #define OMAP4430_WKUPDEP_USB_TLL_MPU_SHIFT (1 << 0) | ||
2168 | #define OMAP4430_WKUPDEP_USB_TLL_MPU_MASK BITFIELD(0, 0) | ||
2169 | |||
2170 | /* Used by PM_WKUP_USIM_WKDEP */ | ||
2171 | #define OMAP4430_WKUPDEP_USIM_MPU_SHIFT (1 << 0) | ||
2172 | #define OMAP4430_WKUPDEP_USIM_MPU_MASK BITFIELD(0, 0) | ||
2173 | |||
2174 | /* Used by PM_WKUP_USIM_WKDEP */ | ||
2175 | #define OMAP4430_WKUPDEP_USIM_SDMA_SHIFT (1 << 3) | ||
2176 | #define OMAP4430_WKUPDEP_USIM_SDMA_MASK BITFIELD(3, 3) | ||
2177 | |||
2178 | /* Used by PM_WKUP_WDT2_WKDEP */ | ||
2179 | #define OMAP4430_WKUPDEP_WDT2_DUCATI_SHIFT (1 << 1) | ||
2180 | #define OMAP4430_WKUPDEP_WDT2_DUCATI_MASK BITFIELD(1, 1) | ||
2181 | |||
2182 | /* Used by PM_WKUP_WDT2_WKDEP */ | ||
2183 | #define OMAP4430_WKUPDEP_WDT2_MPU_SHIFT (1 << 0) | ||
2184 | #define OMAP4430_WKUPDEP_WDT2_MPU_MASK BITFIELD(0, 0) | ||
2185 | |||
2186 | /* Used by PM_ABE_WDT3_WKDEP */ | ||
2187 | #define OMAP4430_WKUPDEP_WDT3_MPU_SHIFT (1 << 0) | ||
2188 | #define OMAP4430_WKUPDEP_WDT3_MPU_MASK BITFIELD(0, 0) | ||
2189 | |||
2190 | /* Used by PM_L3INIT_HSI_WKDEP */ | ||
2191 | #define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_SHIFT (1 << 8) | ||
2192 | #define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_MASK BITFIELD(8, 8) | ||
2193 | |||
2194 | /* Used by PM_L3INIT_XHPI_WKDEP */ | ||
2195 | #define OMAP4430_WKUPDEP_XHPI_DUCATI_SHIFT (1 << 1) | ||
2196 | #define OMAP4430_WKUPDEP_XHPI_DUCATI_MASK BITFIELD(1, 1) | ||
2197 | |||
2198 | /* Used by PRM_IO_PMCTRL */ | ||
2199 | #define OMAP4430_WUCLK_CTRL_SHIFT (1 << 8) | ||
2200 | #define OMAP4430_WUCLK_CTRL_MASK BITFIELD(8, 8) | ||
2201 | |||
2202 | /* Used by PRM_IO_PMCTRL */ | ||
2203 | #define OMAP4430_WUCLK_STATUS_SHIFT (1 << 9) | ||
2204 | #define OMAP4430_WUCLK_STATUS_MASK BITFIELD(9, 9) | ||
2205 | #endif | ||
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h index a117f853ea39..ea050ce188a7 100644 --- a/arch/arm/mach-omap2/prm.h +++ b/arch/arm/mach-omap2/prm.h | |||
@@ -4,8 +4,8 @@ | |||
4 | /* | 4 | /* |
5 | * OMAP2/3 Power/Reset Management (PRM) register definitions | 5 | * OMAP2/3 Power/Reset Management (PRM) register definitions |
6 | * | 6 | * |
7 | * Copyright (C) 2007 Texas Instruments, Inc. | 7 | * Copyright (C) 2007-2009 Texas Instruments, Inc. |
8 | * Copyright (C) 2007 Nokia Corporation | 8 | * Copyright (C) 2009 Nokia Corporation |
9 | * | 9 | * |
10 | * Written by Paul Walmsley | 10 | * Written by Paul Walmsley |
11 | * | 11 | * |
@@ -22,6 +22,10 @@ | |||
22 | OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg)) | 22 | OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg)) |
23 | #define OMAP34XX_PRM_REGADDR(module, reg) \ | 23 | #define OMAP34XX_PRM_REGADDR(module, reg) \ |
24 | OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg)) | 24 | OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg)) |
25 | #define OMAP44XX_PRM_REGADDR(module, reg) \ | ||
26 | OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (module) + (reg)) | ||
27 | |||
28 | #include "prm44xx.h" | ||
25 | 29 | ||
26 | /* | 30 | /* |
27 | * Architecture-specific global PRM registers | 31 | * Architecture-specific global PRM registers |
diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h new file mode 100644 index 000000000000..89be97f0589d --- /dev/null +++ b/arch/arm/mach-omap2/prm44xx.h | |||
@@ -0,0 +1,411 @@ | |||
1 | /* | ||
2 | * OMAP44xx PRM instance offset macros | ||
3 | * | ||
4 | * Copyright (C) 2009 Texas Instruments, Inc. | ||
5 | * Copyright (C) 2009 Nokia Corporation | ||
6 | * | ||
7 | * Paul Walmsley (paul@pwsan.com) | ||
8 | * Rajendra Nayak (rnayak@ti.com) | ||
9 | * Benoit Cousson (b-cousson@ti.com) | ||
10 | * | ||
11 | * This file is automatically generated from the OMAP hardware databases. | ||
12 | * We respectfully ask that any modifications to this file be coordinated | ||
13 | * with the public linux-omap@vger.kernel.org mailing list and the | ||
14 | * authors above to ensure that the autogeneration scripts are kept | ||
15 | * up-to-date with the file contents. | ||
16 | * | ||
17 | * This program is free software; you can redistribute it and/or modify | ||
18 | * it under the terms of the GNU General Public License version 2 as | ||
19 | * published by the Free Software Foundation. | ||
20 | */ | ||
21 | |||
22 | #ifndef __ARCH_ARM_MACH_OMAP2_PRM44XX_H | ||
23 | #define __ARCH_ARM_MACH_OMAP2_PRM44XX_H | ||
24 | |||
25 | |||
26 | /* PRM */ | ||
27 | |||
28 | |||
29 | /* PRM.OCP_SOCKET_PRM register offsets */ | ||
30 | #define OMAP4430_REVISION_PRM OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0000) | ||
31 | #define OMAP4430_PRM_IRQSTATUS_MPU OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0010) | ||
32 | #define OMAP4430_PRM_IRQSTATUS_MPU_2 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0014) | ||
33 | #define OMAP4430_PRM_IRQENABLE_MPU OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0018) | ||
34 | #define OMAP4430_PRM_IRQENABLE_MPU_2 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x001c) | ||
35 | #define OMAP4430_PRM_IRQSTATUS_DUCATI OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0020) | ||
36 | #define OMAP4430_PRM_IRQENABLE_DUCATI OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0028) | ||
37 | #define OMAP4430_PRM_IRQSTATUS_TESLA OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0030) | ||
38 | #define OMAP4430_PRM_IRQENABLE_TESLA OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0038) | ||
39 | #define OMAP4430_PRM_PRM_PROFILING_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0040) | ||
40 | |||
41 | /* PRM.CKGEN_PRM register offsets */ | ||
42 | #define OMAP4430_CM_ABE_DSS_SYS_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0000) | ||
43 | #define OMAP4430_CM_DPLL_SYS_REF_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0004) | ||
44 | #define OMAP4430_CM_L4_WKUP_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0008) | ||
45 | #define OMAP4430_CM_ABE_PLL_REF_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x000c) | ||
46 | #define OMAP4430_CM_SYS_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0010) | ||
47 | |||
48 | /* PRM.MPU_PRM register offsets */ | ||
49 | #define OMAP4430_PM_MPU_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_MOD, 0x0000) | ||
50 | #define OMAP4430_PM_MPU_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_MOD, 0x0004) | ||
51 | #define OMAP4430_RM_MPU_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_MOD, 0x0014) | ||
52 | #define OMAP4430_RM_MPU_MPU_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_MOD, 0x0024) | ||
53 | |||
54 | /* PRM.TESLA_PRM register offsets */ | ||
55 | #define OMAP4430_PM_TESLA_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0000) | ||
56 | #define OMAP4430_PM_TESLA_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0004) | ||
57 | #define OMAP4430_RM_TESLA_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0010) | ||
58 | #define OMAP4430_RM_TESLA_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0014) | ||
59 | #define OMAP4430_RM_TESLA_TESLA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0024) | ||
60 | |||
61 | /* PRM.ABE_PRM register offsets */ | ||
62 | #define OMAP4430_PM_ABE_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0000) | ||
63 | #define OMAP4430_PM_ABE_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0004) | ||
64 | #define OMAP4430_RM_ABE_AESS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x002c) | ||
65 | #define OMAP4430_PM_ABE_PDM_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0030) | ||
66 | #define OMAP4430_RM_ABE_PDM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0034) | ||
67 | #define OMAP4430_PM_ABE_DMIC_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0038) | ||
68 | #define OMAP4430_RM_ABE_DMIC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x003c) | ||
69 | #define OMAP4430_PM_ABE_MCASP_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0040) | ||
70 | #define OMAP4430_RM_ABE_MCASP_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0044) | ||
71 | #define OMAP4430_PM_ABE_MCBSP1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0048) | ||
72 | #define OMAP4430_RM_ABE_MCBSP1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x004c) | ||
73 | #define OMAP4430_PM_ABE_MCBSP2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0050) | ||
74 | #define OMAP4430_RM_ABE_MCBSP2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0054) | ||
75 | #define OMAP4430_PM_ABE_MCBSP3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0058) | ||
76 | #define OMAP4430_RM_ABE_MCBSP3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x005c) | ||
77 | #define OMAP4430_PM_ABE_SLIMBUS_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0060) | ||
78 | #define OMAP4430_RM_ABE_SLIMBUS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0064) | ||
79 | #define OMAP4430_PM_ABE_TIMER5_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0068) | ||
80 | #define OMAP4430_RM_ABE_TIMER5_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x006c) | ||
81 | #define OMAP4430_PM_ABE_TIMER6_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0070) | ||
82 | #define OMAP4430_RM_ABE_TIMER6_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0074) | ||
83 | #define OMAP4430_PM_ABE_TIMER7_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0078) | ||
84 | #define OMAP4430_RM_ABE_TIMER7_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x007c) | ||
85 | #define OMAP4430_PM_ABE_TIMER8_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0080) | ||
86 | #define OMAP4430_RM_ABE_TIMER8_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0084) | ||
87 | #define OMAP4430_PM_ABE_WDT3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0088) | ||
88 | #define OMAP4430_RM_ABE_WDT3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x008c) | ||
89 | |||
90 | /* PRM.ALWAYS_ON_PRM register offsets */ | ||
91 | #define OMAP4430_RM_ALWON_MDMINTC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0024) | ||
92 | #define OMAP4430_PM_ALWON_SR_MPU_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0028) | ||
93 | #define OMAP4430_RM_ALWON_SR_MPU_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x002c) | ||
94 | #define OMAP4430_PM_ALWON_SR_IVA_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0030) | ||
95 | #define OMAP4430_RM_ALWON_SR_IVA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0034) | ||
96 | #define OMAP4430_PM_ALWON_SR_CORE_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0038) | ||
97 | #define OMAP4430_RM_ALWON_SR_CORE_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x003c) | ||
98 | |||
99 | /* PRM.CORE_PRM register offsets */ | ||
100 | #define OMAP4430_PM_CORE_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0000) | ||
101 | #define OMAP4430_PM_CORE_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0004) | ||
102 | #define OMAP4430_RM_L3_1_L3_1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0024) | ||
103 | #define OMAP4430_RM_L3_2_L3_2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0124) | ||
104 | #define OMAP4430_RM_L3_2_GPMC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x012c) | ||
105 | #define OMAP4430_RM_L3_2_OCMC_RAM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0134) | ||
106 | #define OMAP4430_RM_DUCATI_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0210) | ||
107 | #define OMAP4430_RM_DUCATI_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0214) | ||
108 | #define OMAP4430_RM_DUCATI_DUCATI_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0224) | ||
109 | #define OMAP4430_RM_SDMA_SDMA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0324) | ||
110 | #define OMAP4430_RM_MEMIF_DMM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0424) | ||
111 | #define OMAP4430_RM_MEMIF_EMIF_FW_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x042c) | ||
112 | #define OMAP4430_RM_MEMIF_EMIF_1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0434) | ||
113 | #define OMAP4430_RM_MEMIF_EMIF_2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x043c) | ||
114 | #define OMAP4430_RM_MEMIF_DLL_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0444) | ||
115 | #define OMAP4430_RM_MEMIF_EMIF_H1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0454) | ||
116 | #define OMAP4430_RM_MEMIF_EMIF_H2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x045c) | ||
117 | #define OMAP4430_RM_MEMIF_DLL_H_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0464) | ||
118 | #define OMAP4430_RM_D2D_SAD2D_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0524) | ||
119 | #define OMAP4430_RM_D2D_MODEM_ICR_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x052c) | ||
120 | #define OMAP4430_RM_D2D_SAD2D_FW_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0534) | ||
121 | #define OMAP4430_RM_L4CFG_L4_CFG_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0624) | ||
122 | #define OMAP4430_RM_L4CFG_HW_SEM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x062c) | ||
123 | #define OMAP4430_RM_L4CFG_MAILBOX_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0634) | ||
124 | #define OMAP4430_RM_L4CFG_SAR_ROM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x063c) | ||
125 | #define OMAP4430_RM_L3INSTR_L3_3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0724) | ||
126 | #define OMAP4430_RM_L3INSTR_L3_INSTR_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x072c) | ||
127 | #define OMAP4430_RM_L3INSTR_OCP_WP1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0744) | ||
128 | |||
129 | /* PRM.IVAHD_PRM register offsets */ | ||
130 | #define OMAP4430_PM_IVAHD_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0000) | ||
131 | #define OMAP4430_PM_IVAHD_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0004) | ||
132 | #define OMAP4430_RM_IVAHD_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0010) | ||
133 | #define OMAP4430_RM_IVAHD_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0014) | ||
134 | #define OMAP4430_RM_IVAHD_IVAHD_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0024) | ||
135 | #define OMAP4430_RM_IVAHD_SL2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x002c) | ||
136 | |||
137 | /* PRM.CAM_PRM register offsets */ | ||
138 | #define OMAP4430_PM_CAM_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_MOD, 0x0000) | ||
139 | #define OMAP4430_PM_CAM_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_MOD, 0x0004) | ||
140 | #define OMAP4430_RM_CAM_ISS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_MOD, 0x0024) | ||
141 | #define OMAP4430_RM_CAM_FDIF_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_MOD, 0x002c) | ||
142 | |||
143 | /* PRM.DSS_PRM register offsets */ | ||
144 | #define OMAP4430_PM_DSS_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x0000) | ||
145 | #define OMAP4430_PM_DSS_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x0004) | ||
146 | #define OMAP4430_PM_DSS_DSS_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x0020) | ||
147 | #define OMAP4430_RM_DSS_DSS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x0024) | ||
148 | #define OMAP4430_RM_DSS_DEISS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x002c) | ||
149 | |||
150 | /* PRM.GFX_PRM register offsets */ | ||
151 | #define OMAP4430_PM_GFX_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_MOD, 0x0000) | ||
152 | #define OMAP4430_PM_GFX_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_MOD, 0x0004) | ||
153 | #define OMAP4430_RM_GFX_GFX_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_MOD, 0x0024) | ||
154 | |||
155 | /* PRM.L3INIT_PRM register offsets */ | ||
156 | #define OMAP4430_PM_L3INIT_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0000) | ||
157 | #define OMAP4430_PM_L3INIT_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0004) | ||
158 | #define OMAP4430_PM_L3INIT_MMC1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0028) | ||
159 | #define OMAP4430_RM_L3INIT_MMC1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x002c) | ||
160 | #define OMAP4430_PM_L3INIT_MMC2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0030) | ||
161 | #define OMAP4430_RM_L3INIT_MMC2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0034) | ||
162 | #define OMAP4430_PM_L3INIT_HSI_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0038) | ||
163 | #define OMAP4430_RM_L3INIT_HSI_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x003c) | ||
164 | #define OMAP4430_PM_L3INIT_UNIPRO1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0040) | ||
165 | #define OMAP4430_RM_L3INIT_UNIPRO1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0044) | ||
166 | #define OMAP4430_PM_L3INIT_USB_HOST_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0058) | ||
167 | #define OMAP4430_RM_L3INIT_USB_HOST_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x005c) | ||
168 | #define OMAP4430_PM_L3INIT_USB_OTG_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0060) | ||
169 | #define OMAP4430_RM_L3INIT_USB_OTG_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0064) | ||
170 | #define OMAP4430_PM_L3INIT_USB_TLL_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0068) | ||
171 | #define OMAP4430_RM_L3INIT_USB_TLL_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x006c) | ||
172 | #define OMAP4430_RM_L3INIT_P1500_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x007c) | ||
173 | #define OMAP4430_RM_L3INIT_EMAC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0084) | ||
174 | #define OMAP4430_PM_L3INIT_SATA_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0088) | ||
175 | #define OMAP4430_RM_L3INIT_SATA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x008c) | ||
176 | #define OMAP4430_RM_L3INIT_TPPSS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0094) | ||
177 | #define OMAP4430_PM_L3INIT_PCIESS_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0098) | ||
178 | #define OMAP4430_RM_L3INIT_PCIESS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x009c) | ||
179 | #define OMAP4430_RM_L3INIT_CCPTX_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00ac) | ||
180 | #define OMAP4430_PM_L3INIT_XHPI_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00c0) | ||
181 | #define OMAP4430_RM_L3INIT_XHPI_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00c4) | ||
182 | #define OMAP4430_PM_L3INIT_MMC6_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00c8) | ||
183 | #define OMAP4430_RM_L3INIT_MMC6_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00cc) | ||
184 | #define OMAP4430_PM_L3INIT_USB_HOST_FS_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00d0) | ||
185 | #define OMAP4430_RM_L3INIT_USB_HOST_FS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00d4) | ||
186 | #define OMAP4430_RM_L3INIT_USBPHYOCP2SCP_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00e4) | ||
187 | |||
188 | /* PRM.L4PER_PRM register offsets */ | ||
189 | #define OMAP4430_PM_L4PER_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0000) | ||
190 | #define OMAP4430_PM_L4PER_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0004) | ||
191 | #define OMAP4430_RM_L4PER_ADC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0024) | ||
192 | #define OMAP4430_PM_L4PER_DMTIMER10_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0028) | ||
193 | #define OMAP4430_RM_L4PER_DMTIMER10_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x002c) | ||
194 | #define OMAP4430_PM_L4PER_DMTIMER11_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0030) | ||
195 | #define OMAP4430_RM_L4PER_DMTIMER11_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0034) | ||
196 | #define OMAP4430_PM_L4PER_DMTIMER2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0038) | ||
197 | #define OMAP4430_RM_L4PER_DMTIMER2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x003c) | ||
198 | #define OMAP4430_PM_L4PER_DMTIMER3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0040) | ||
199 | #define OMAP4430_RM_L4PER_DMTIMER3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0044) | ||
200 | #define OMAP4430_PM_L4PER_DMTIMER4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0048) | ||
201 | #define OMAP4430_RM_L4PER_DMTIMER4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x004c) | ||
202 | #define OMAP4430_PM_L4PER_DMTIMER9_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0050) | ||
203 | #define OMAP4430_RM_L4PER_DMTIMER9_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0054) | ||
204 | #define OMAP4430_RM_L4PER_ELM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x005c) | ||
205 | #define OMAP4430_PM_L4PER_GPIO2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0060) | ||
206 | #define OMAP4430_RM_L4PER_GPIO2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0064) | ||
207 | #define OMAP4430_PM_L4PER_GPIO3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0068) | ||
208 | #define OMAP4430_RM_L4PER_GPIO3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x006c) | ||
209 | #define OMAP4430_PM_L4PER_GPIO4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0070) | ||
210 | #define OMAP4430_RM_L4PER_GPIO4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0074) | ||
211 | #define OMAP4430_PM_L4PER_GPIO5_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0078) | ||
212 | #define OMAP4430_RM_L4PER_GPIO5_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x007c) | ||
213 | #define OMAP4430_PM_L4PER_GPIO6_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0080) | ||
214 | #define OMAP4430_RM_L4PER_GPIO6_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0084) | ||
215 | #define OMAP4430_RM_L4PER_HDQ1W_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x008c) | ||
216 | #define OMAP4430_PM_L4PER_HECC1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0090) | ||
217 | #define OMAP4430_RM_L4PER_HECC1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0094) | ||
218 | #define OMAP4430_PM_L4PER_HECC2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0098) | ||
219 | #define OMAP4430_RM_L4PER_HECC2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x009c) | ||
220 | #define OMAP4430_PM_L4PER_I2C1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00a0) | ||
221 | #define OMAP4430_RM_L4PER_I2C1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00a4) | ||
222 | #define OMAP4430_PM_L4PER_I2C2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00a8) | ||
223 | #define OMAP4430_RM_L4PER_I2C2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00ac) | ||
224 | #define OMAP4430_PM_L4PER_I2C3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00b0) | ||
225 | #define OMAP4430_RM_L4PER_I2C3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00b4) | ||
226 | #define OMAP4430_PM_L4PER_I2C4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00b8) | ||
227 | #define OMAP4430_RM_L4PER_I2C4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00bc) | ||
228 | #define OMAP4430_RM_L4PER_L4_PER_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00c0) | ||
229 | #define OMAP4430_PM_L4PER_MCASP2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00d0) | ||
230 | #define OMAP4430_RM_L4PER_MCASP2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00d4) | ||
231 | #define OMAP4430_PM_L4PER_MCASP3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00d8) | ||
232 | #define OMAP4430_RM_L4PER_MCASP3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00dc) | ||
233 | #define OMAP4430_PM_L4PER_MCBSP4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00e0) | ||
234 | #define OMAP4430_RM_L4PER_MCBSP4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00e4) | ||
235 | #define OMAP4430_RM_L4PER_MGATE_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00ec) | ||
236 | #define OMAP4430_PM_L4PER_MCSPI1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00f0) | ||
237 | #define OMAP4430_RM_L4PER_MCSPI1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00f4) | ||
238 | #define OMAP4430_PM_L4PER_MCSPI2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00f8) | ||
239 | #define OMAP4430_RM_L4PER_MCSPI2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00fc) | ||
240 | #define OMAP4430_PM_L4PER_MCSPI3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0100) | ||
241 | #define OMAP4430_RM_L4PER_MCSPI3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0104) | ||
242 | #define OMAP4430_PM_L4PER_MCSPI4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0108) | ||
243 | #define OMAP4430_RM_L4PER_MCSPI4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x010c) | ||
244 | #define OMAP4430_PM_L4PER_MMCSD3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0120) | ||
245 | #define OMAP4430_RM_L4PER_MMCSD3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0124) | ||
246 | #define OMAP4430_PM_L4PER_MMCSD4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0128) | ||
247 | #define OMAP4430_RM_L4PER_MMCSD4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x012c) | ||
248 | #define OMAP4430_RM_L4PER_MSPROHG_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0134) | ||
249 | #define OMAP4430_PM_L4PER_SLIMBUS2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0138) | ||
250 | #define OMAP4430_RM_L4PER_SLIMBUS2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x013c) | ||
251 | #define OMAP4430_PM_L4PER_UART1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0140) | ||
252 | #define OMAP4430_RM_L4PER_UART1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0144) | ||
253 | #define OMAP4430_PM_L4PER_UART2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0148) | ||
254 | #define OMAP4430_RM_L4PER_UART2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x014c) | ||
255 | #define OMAP4430_PM_L4PER_UART3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0150) | ||
256 | #define OMAP4430_RM_L4PER_UART3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0154) | ||
257 | #define OMAP4430_PM_L4PER_UART4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0158) | ||
258 | #define OMAP4430_RM_L4PER_UART4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x015c) | ||
259 | #define OMAP4430_PM_L4PER_MMCSD5_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0160) | ||
260 | #define OMAP4430_RM_L4PER_MMCSD5_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0164) | ||
261 | #define OMAP4430_PM_L4PER_I2C5_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0168) | ||
262 | #define OMAP4430_RM_L4PER_I2C5_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x016c) | ||
263 | #define OMAP4430_RM_L4SEC_AES1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01a4) | ||
264 | #define OMAP4430_RM_L4SEC_AES2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01ac) | ||
265 | #define OMAP4430_RM_L4SEC_DES3DES_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01b4) | ||
266 | #define OMAP4430_RM_L4SEC_PKAEIP29_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01bc) | ||
267 | #define OMAP4430_RM_L4SEC_RNG_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01c4) | ||
268 | #define OMAP4430_RM_L4SEC_SHA2MD51_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01cc) | ||
269 | #define OMAP4430_RM_L4SEC_CRYPTODMA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01dc) | ||
270 | |||
271 | /* PRM.CEFUSE_PRM register offsets */ | ||
272 | #define OMAP4430_PM_CEFUSE_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_MOD, 0x0000) | ||
273 | #define OMAP4430_PM_CEFUSE_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_MOD, 0x0004) | ||
274 | #define OMAP4430_RM_CEFUSE_CEFUSE_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_MOD, 0x0024) | ||
275 | |||
276 | /* PRM.WKUP_PRM register offsets */ | ||
277 | #define OMAP4430_RM_WKUP_L4WKUP_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0024) | ||
278 | #define OMAP4430_RM_WKUP_WDT1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x002c) | ||
279 | #define OMAP4430_PM_WKUP_WDT2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0030) | ||
280 | #define OMAP4430_RM_WKUP_WDT2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0034) | ||
281 | #define OMAP4430_PM_WKUP_GPIO1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0038) | ||
282 | #define OMAP4430_RM_WKUP_GPIO1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x003c) | ||
283 | #define OMAP4430_PM_WKUP_TIMER1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0040) | ||
284 | #define OMAP4430_RM_WKUP_TIMER1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0044) | ||
285 | #define OMAP4430_PM_WKUP_TIMER12_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0048) | ||
286 | #define OMAP4430_RM_WKUP_TIMER12_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x004c) | ||
287 | #define OMAP4430_RM_WKUP_SYNCTIMER_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0054) | ||
288 | #define OMAP4430_PM_WKUP_USIM_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0058) | ||
289 | #define OMAP4430_RM_WKUP_USIM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x005c) | ||
290 | #define OMAP4430_RM_WKUP_SARRAM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0064) | ||
291 | #define OMAP4430_PM_WKUP_KEYBOARD_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0078) | ||
292 | #define OMAP4430_RM_WKUP_KEYBOARD_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x007c) | ||
293 | #define OMAP4430_PM_WKUP_RTC_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0080) | ||
294 | #define OMAP4430_RM_WKUP_RTC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0084) | ||
295 | |||
296 | /* PRM.WKUP_CM register offsets */ | ||
297 | #define OMAP4430_CM_WKUP_CLKSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0000) | ||
298 | #define OMAP4430_CM_WKUP_L4WKUP_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0020) | ||
299 | #define OMAP4430_CM_WKUP_WDT1_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0028) | ||
300 | #define OMAP4430_CM_WKUP_WDT2_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0030) | ||
301 | #define OMAP4430_CM_WKUP_GPIO1_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0038) | ||
302 | #define OMAP4430_CM_WKUP_TIMER1_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0040) | ||
303 | #define OMAP4430_CM_WKUP_TIMER12_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0048) | ||
304 | #define OMAP4430_CM_WKUP_SYNCTIMER_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0050) | ||
305 | #define OMAP4430_CM_WKUP_USIM_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0058) | ||
306 | #define OMAP4430_CM_WKUP_SARRAM_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0060) | ||
307 | #define OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0078) | ||
308 | #define OMAP4430_CM_WKUP_RTC_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0080) | ||
309 | #define OMAP4430_CM_WKUP_BANDGAP_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0088) | ||
310 | |||
311 | /* PRM.EMU_PRM register offsets */ | ||
312 | #define OMAP4430_PM_EMU_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_MOD, 0x0000) | ||
313 | #define OMAP4430_PM_EMU_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_MOD, 0x0004) | ||
314 | #define OMAP4430_RM_EMU_DEBUGSS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_MOD, 0x0024) | ||
315 | |||
316 | /* PRM.EMU_CM register offsets */ | ||
317 | #define OMAP4430_CM_EMU_CLKSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_MOD, 0x0000) | ||
318 | #define OMAP4430_CM_EMU_DYNAMICDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_MOD, 0x0008) | ||
319 | #define OMAP4430_CM_EMU_DEBUGSS_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_MOD, 0x0020) | ||
320 | |||
321 | /* PRM.DEVICE_PRM register offsets */ | ||
322 | #define OMAP4430_PRM_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0000) | ||
323 | #define OMAP4430_PRM_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0004) | ||
324 | #define OMAP4430_PRM_RSTTIME OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0008) | ||
325 | #define OMAP4430_PRM_CLKREQCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x000c) | ||
326 | #define OMAP4430_PRM_VOLTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0010) | ||
327 | #define OMAP4430_PRM_PWRREQCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0014) | ||
328 | #define OMAP4430_PRM_PSCON_COUNT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0018) | ||
329 | #define OMAP4430_PRM_IO_COUNT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x001c) | ||
330 | #define OMAP4430_PRM_IO_PMCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0020) | ||
331 | #define OMAP4430_PRM_VOLTSETUP_WARMRESET OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0024) | ||
332 | #define OMAP4430_PRM_VOLTSETUP_CORE_OFF OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0028) | ||
333 | #define OMAP4430_PRM_VOLTSETUP_MPU_OFF OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x002c) | ||
334 | #define OMAP4430_PRM_VOLTSETUP_IVA_OFF OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0030) | ||
335 | #define OMAP4430_PRM_VOLTSETUP_CORE_RET_SLEEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0034) | ||
336 | #define OMAP4430_PRM_VOLTSETUP_MPU_RET_SLEEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0038) | ||
337 | #define OMAP4430_PRM_VOLTSETUP_IVA_RET_SLEEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x003c) | ||
338 | #define OMAP4430_PRM_VP_CORE_CONFIG OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0040) | ||
339 | #define OMAP4430_PRM_VP_CORE_STATUS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0044) | ||
340 | #define OMAP4430_PRM_VP_CORE_VLIMITTO OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0048) | ||
341 | #define OMAP4430_PRM_VP_CORE_VOLTAGE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x004c) | ||
342 | #define OMAP4430_PRM_VP_CORE_VSTEPMAX OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0050) | ||
343 | #define OMAP4430_PRM_VP_CORE_VSTEPMIN OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0054) | ||
344 | #define OMAP4430_PRM_VP_MPU_CONFIG OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0058) | ||
345 | #define OMAP4430_PRM_VP_MPU_STATUS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x005c) | ||
346 | #define OMAP4430_PRM_VP_MPU_VLIMITTO OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0060) | ||
347 | #define OMAP4430_PRM_VP_MPU_VOLTAGE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0064) | ||
348 | #define OMAP4430_PRM_VP_MPU_VSTEPMAX OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0068) | ||
349 | #define OMAP4430_PRM_VP_MPU_VSTEPMIN OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x006c) | ||
350 | #define OMAP4430_PRM_VP_IVA_CONFIG OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0070) | ||
351 | #define OMAP4430_PRM_VP_IVA_STATUS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0074) | ||
352 | #define OMAP4430_PRM_VP_IVA_VLIMITTO OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0078) | ||
353 | #define OMAP4430_PRM_VP_IVA_VOLTAGE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x007c) | ||
354 | #define OMAP4430_PRM_VP_IVA_VSTEPMAX OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0080) | ||
355 | #define OMAP4430_PRM_VP_IVA_VSTEPMIN OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0084) | ||
356 | #define OMAP4430_PRM_VC_SMPS_SA OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0088) | ||
357 | #define OMAP4430_PRM_VC_VAL_SMPS_RA_VOL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x008c) | ||
358 | #define OMAP4430_PRM_VC_VAL_SMPS_RA_CMD OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0090) | ||
359 | #define OMAP4430_PRM_VC_VAL_CMD_VDD_CORE_L OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0094) | ||
360 | #define OMAP4430_PRM_VC_VAL_CMD_VDD_MPU_L OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0098) | ||
361 | #define OMAP4430_PRM_VC_VAL_CMD_VDD_IVA_L OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x009c) | ||
362 | #define OMAP4430_PRM_VC_VAL_BYPASS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00a0) | ||
363 | #define OMAP4430_PRM_VC_CFG_CHANNEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00a4) | ||
364 | #define OMAP4430_PRM_VC_CFG_I2C_MODE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00a8) | ||
365 | #define OMAP4430_PRM_VC_CFG_I2C_CLK OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00ac) | ||
366 | #define OMAP4430_PRM_SRAM_COUNT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00b0) | ||
367 | #define OMAP4430_PRM_SRAM_WKUP_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00b4) | ||
368 | #define OMAP4430_PRM_LDO_SRAM_CORE_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00b8) | ||
369 | #define OMAP4430_PRM_LDO_SRAM_CORE_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00bc) | ||
370 | #define OMAP4430_PRM_LDO_SRAM_MPU_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00c0) | ||
371 | #define OMAP4430_PRM_LDO_SRAM_MPU_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00c4) | ||
372 | #define OMAP4430_PRM_LDO_SRAM_IVA_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00c8) | ||
373 | #define OMAP4430_PRM_LDO_SRAM_IVA_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00cc) | ||
374 | #define OMAP4430_PRM_LDO_ABB_MPU_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00d0) | ||
375 | #define OMAP4430_PRM_LDO_ABB_MPU_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00d4) | ||
376 | #define OMAP4430_PRM_LDO_ABB_IVA_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00d8) | ||
377 | #define OMAP4430_PRM_LDO_ABB_IVA_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00dc) | ||
378 | #define OMAP4430_PRM_LDO_BANDGAP_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e0) | ||
379 | #define OMAP4430_PRM_DEVICE_OFF_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e4) | ||
380 | #define OMAP4430_PRM_PHASE1_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e8) | ||
381 | #define OMAP4430_PRM_PHASE2A_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00ec) | ||
382 | #define OMAP4430_PRM_PHASE2B_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f0) | ||
383 | #define OMAP4430_PRM_MODEM_IF_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f4) | ||
384 | |||
385 | /* CHIRON_PRCM */ | ||
386 | |||
387 | |||
388 | /* CHIRON_PRCM.CHIRONSS_OCP_SOCKET_PRCM register offsets */ | ||
389 | #define OMAP4430_REVISION_PRCM OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_OCP_SOCKET_PRCM_MOD, 0x0000) | ||
390 | |||
391 | /* CHIRON_PRCM.CHIRONSS_DEVICE_PRM register offsets */ | ||
392 | #define OMAP4430_CHIRON_PRCM_PRM_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_DEVICE_PRM_MOD, 0x0000) | ||
393 | |||
394 | /* CHIRON_PRCM.CHIRONSS_CPU0 register offsets */ | ||
395 | #define OMAP4430_PM_PDA_CPU0_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0000) | ||
396 | #define OMAP4430_PM_PDA_CPU0_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0004) | ||
397 | #define OMAP4430_RM_PDA_CPU0_CPU0_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0008) | ||
398 | #define OMAP4430_RM_PDA_CPU0_CPU0_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x000c) | ||
399 | #define OMAP4430_RM_PDA_CPU0_CPU0_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0010) | ||
400 | #define OMAP4430_CM_PDA_CPU0_CPU0_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0014) | ||
401 | #define OMAP4430_CM_PDA_CPU0_CLKSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0018) | ||
402 | |||
403 | /* CHIRON_PRCM.CHIRONSS_CPU1 register offsets */ | ||
404 | #define OMAP4430_PM_PDA_CPU1_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0000) | ||
405 | #define OMAP4430_PM_PDA_CPU1_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0004) | ||
406 | #define OMAP4430_RM_PDA_CPU1_CPU1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0008) | ||
407 | #define OMAP4430_RM_PDA_CPU1_CPU1_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x000c) | ||
408 | #define OMAP4430_RM_PDA_CPU1_CPU1_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0010) | ||
409 | #define OMAP4430_CM_PDA_CPU1_CPU1_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0014) | ||
410 | #define OMAP4430_CM_PDA_CPU1_CLKSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0018) | ||
411 | #endif | ||
diff --git a/arch/arm/mach-omap2/sdrc.h b/arch/arm/mach-omap2/sdrc.h index 48207b018989..68f57bb67fc5 100644 --- a/arch/arm/mach-omap2/sdrc.h +++ b/arch/arm/mach-omap2/sdrc.h | |||
@@ -18,6 +18,9 @@ | |||
18 | #include <plat/sdrc.h> | 18 | #include <plat/sdrc.h> |
19 | 19 | ||
20 | #ifndef __ASSEMBLER__ | 20 | #ifndef __ASSEMBLER__ |
21 | |||
22 | #include <linux/io.h> | ||
23 | |||
21 | extern void __iomem *omap2_sdrc_base; | 24 | extern void __iomem *omap2_sdrc_base; |
22 | extern void __iomem *omap2_sms_base; | 25 | extern void __iomem *omap2_sms_base; |
23 | 26 | ||
@@ -56,4 +59,20 @@ static inline u32 sms_read_reg(u16 reg) | |||
56 | OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE + (reg)) | 59 | OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE + (reg)) |
57 | #endif /* __ASSEMBLER__ */ | 60 | #endif /* __ASSEMBLER__ */ |
58 | 61 | ||
62 | /* Minimum frequency that the SDRC DLL can lock at */ | ||
63 | #define MIN_SDRC_DLL_LOCK_FREQ 83000000 | ||
64 | |||
65 | /* Scale factor for fixed-point arith in omap3_core_dpll_m2_set_rate() */ | ||
66 | #define SDRC_MPURATE_SCALE 8 | ||
67 | |||
68 | /* 2^SDRC_MPURATE_BASE_SHIFT: MPU MHz that SDRC_MPURATE_LOOPS is defined for */ | ||
69 | #define SDRC_MPURATE_BASE_SHIFT 9 | ||
70 | |||
71 | /* | ||
72 | * SDRC_MPURATE_LOOPS: Number of MPU loops to execute at | ||
73 | * 2^MPURATE_BASE_SHIFT MHz for SDRC to stabilize | ||
74 | */ | ||
75 | #define SDRC_MPURATE_LOOPS 96 | ||
76 | |||
77 | |||
59 | #endif | 78 | #endif |
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c index 2e17b57f5b23..39b797bc14d6 100644 --- a/arch/arm/mach-omap2/serial.c +++ b/arch/arm/mach-omap2/serial.c | |||
@@ -33,6 +33,7 @@ | |||
33 | #include "pm.h" | 33 | #include "pm.h" |
34 | #include "prm-regbits-34xx.h" | 34 | #include "prm-regbits-34xx.h" |
35 | 35 | ||
36 | #define UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV 0x52 | ||
36 | #define UART_OMAP_WER 0x17 /* Wake-up enable register */ | 37 | #define UART_OMAP_WER 0x17 /* Wake-up enable register */ |
37 | 38 | ||
38 | #define DEFAULT_TIMEOUT (5 * HZ) | 39 | #define DEFAULT_TIMEOUT (5 * HZ) |
@@ -572,6 +573,23 @@ static struct omap_uart_state omap_uart[] = { | |||
572 | #endif | 573 | #endif |
573 | }; | 574 | }; |
574 | 575 | ||
576 | /* | ||
577 | * Override the default 8250 read handler: mem_serial_in() | ||
578 | * Empty RX fifo read causes an abort on omap3630 and omap4 | ||
579 | * This function makes sure that an empty rx fifo is not read on these silicons | ||
580 | * (OMAP1/2/3430 are not affected) | ||
581 | */ | ||
582 | static unsigned int serial_in_override(struct uart_port *up, int offset) | ||
583 | { | ||
584 | if (UART_RX == offset) { | ||
585 | unsigned int lsr; | ||
586 | lsr = serial_read_reg(omap_uart[up->line].p, UART_LSR); | ||
587 | if (!(lsr & UART_LSR_DR)) | ||
588 | return -EPERM; | ||
589 | } | ||
590 | return serial_read_reg(omap_uart[up->line].p, offset); | ||
591 | } | ||
592 | |||
575 | void __init omap_serial_early_init(void) | 593 | void __init omap_serial_early_init(void) |
576 | { | 594 | { |
577 | int i; | 595 | int i; |
@@ -631,24 +649,64 @@ void __init omap_serial_early_init(void) | |||
631 | } | 649 | } |
632 | } | 650 | } |
633 | 651 | ||
634 | void __init omap_serial_init(void) | 652 | /** |
653 | * omap_serial_init_port() - initialize single serial port | ||
654 | * @port: serial port number (0-3) | ||
655 | * | ||
656 | * This function initialies serial driver for given @port only. | ||
657 | * Platforms can call this function instead of omap_serial_init() | ||
658 | * if they don't plan to use all available UARTs as serial ports. | ||
659 | * | ||
660 | * Don't mix calls to omap_serial_init_port() and omap_serial_init(), | ||
661 | * use only one of the two. | ||
662 | */ | ||
663 | void __init omap_serial_init_port(int port) | ||
635 | { | 664 | { |
636 | int i; | 665 | struct omap_uart_state *uart; |
666 | struct platform_device *pdev; | ||
667 | struct device *dev; | ||
637 | 668 | ||
638 | for (i = 0; i < ARRAY_SIZE(omap_uart); i++) { | 669 | BUG_ON(port < 0); |
639 | struct omap_uart_state *uart = &omap_uart[i]; | 670 | BUG_ON(port >= ARRAY_SIZE(omap_uart)); |
640 | struct platform_device *pdev = &uart->pdev; | ||
641 | struct device *dev = &pdev->dev; | ||
642 | 671 | ||
643 | omap_uart_reset(uart); | 672 | uart = &omap_uart[port]; |
644 | omap_uart_idle_init(uart); | 673 | pdev = &uart->pdev; |
674 | dev = &pdev->dev; | ||
645 | 675 | ||
646 | if (WARN_ON(platform_device_register(pdev))) | 676 | omap_uart_reset(uart); |
647 | continue; | 677 | omap_uart_idle_init(uart); |
648 | if ((cpu_is_omap34xx() && uart->padconf) || | 678 | |
649 | (uart->wk_en && uart->wk_mask)) { | 679 | if (WARN_ON(platform_device_register(pdev))) |
650 | device_init_wakeup(dev, true); | 680 | return; |
651 | DEV_CREATE_FILE(dev, &dev_attr_sleep_timeout); | 681 | |
652 | } | 682 | if ((cpu_is_omap34xx() && uart->padconf) || |
683 | (uart->wk_en && uart->wk_mask)) { | ||
684 | device_init_wakeup(dev, true); | ||
685 | DEV_CREATE_FILE(dev, &dev_attr_sleep_timeout); | ||
653 | } | 686 | } |
687 | |||
688 | /* omap44xx: Never read empty UART fifo | ||
689 | * omap3xxx: Never read empty UART fifo on UARTs | ||
690 | * with IP rev >=0x52 | ||
691 | */ | ||
692 | if (cpu_is_omap44xx()) | ||
693 | uart->p->serial_in = serial_in_override; | ||
694 | else if ((serial_read_reg(uart->p, UART_OMAP_MVER) & 0xFF) | ||
695 | >= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV) | ||
696 | uart->p->serial_in = serial_in_override; | ||
697 | } | ||
698 | |||
699 | /** | ||
700 | * omap_serial_init() - intialize all supported serial ports | ||
701 | * | ||
702 | * Initializes all available UARTs as serial ports. Platforms | ||
703 | * can call this function when they want to have default behaviour | ||
704 | * for serial ports (e.g initialize them all as serial ports). | ||
705 | */ | ||
706 | void __init omap_serial_init(void) | ||
707 | { | ||
708 | int i; | ||
709 | |||
710 | for (i = 0; i < ARRAY_SIZE(omap_uart); i++) | ||
711 | omap_serial_init_port(i); | ||
654 | } | 712 | } |
diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S index 82aa4a3d160c..de99ba2a57ab 100644 --- a/arch/arm/mach-omap2/sram34xx.S +++ b/arch/arm/mach-omap2/sram34xx.S | |||
@@ -91,8 +91,19 @@ | |||
91 | * new SDRC_ACTIM_CTRL_B_1 register contents | 91 | * new SDRC_ACTIM_CTRL_B_1 register contents |
92 | * new SDRC_MR_1 register value | 92 | * new SDRC_MR_1 register value |
93 | * | 93 | * |
94 | * If the param SDRC_RFR_CTRL_1 is 0, the parameters | 94 | * If the param SDRC_RFR_CTRL_1 is 0, the parameters are not programmed into |
95 | * are not programmed into the SDRC CS1 registers | 95 | * the SDRC CS1 registers |
96 | * | ||
97 | * NOTE: This code no longer attempts to program the SDRC AC timing and MR | ||
98 | * registers. This is because the code currently cannot ensure that all | ||
99 | * L3 initiators (e.g., sDMA, IVA, DSS DISPC, etc.) are not accessing the | ||
100 | * SDRAM when the registers are written. If the registers are changed while | ||
101 | * an initiator is accessing SDRAM, memory can be corrupted and/or the SDRC | ||
102 | * may enter an unpredictable state. In the future, the intent is to | ||
103 | * re-enable this code in cases where we can ensure that no initiators are | ||
104 | * touching the SDRAM. Until that time, users who know that their use case | ||
105 | * can satisfy the above requirement can enable the CONFIG_OMAP3_SDRC_AC_TIMING | ||
106 | * option. | ||
96 | */ | 107 | */ |
97 | ENTRY(omap3_sram_configure_core_dpll) | 108 | ENTRY(omap3_sram_configure_core_dpll) |
98 | stmfd sp!, {r1-r12, lr} @ store regs to stack | 109 | stmfd sp!, {r1-r12, lr} @ store regs to stack |
@@ -219,6 +230,7 @@ configure_sdrc: | |||
219 | ldr r12, omap_sdrc_rfr_ctrl_0_val @ fetch value from SRAM | 230 | ldr r12, omap_sdrc_rfr_ctrl_0_val @ fetch value from SRAM |
220 | ldr r11, omap3_sdrc_rfr_ctrl_0 @ fetch addr from SRAM | 231 | ldr r11, omap3_sdrc_rfr_ctrl_0 @ fetch addr from SRAM |
221 | str r12, [r11] @ store | 232 | str r12, [r11] @ store |
233 | #ifdef CONFIG_OMAP3_SDRC_AC_TIMING | ||
222 | ldr r12, omap_sdrc_actim_ctrl_a_0_val | 234 | ldr r12, omap_sdrc_actim_ctrl_a_0_val |
223 | ldr r11, omap3_sdrc_actim_ctrl_a_0 | 235 | ldr r11, omap3_sdrc_actim_ctrl_a_0 |
224 | str r12, [r11] | 236 | str r12, [r11] |
@@ -228,11 +240,13 @@ configure_sdrc: | |||
228 | ldr r12, omap_sdrc_mr_0_val | 240 | ldr r12, omap_sdrc_mr_0_val |
229 | ldr r11, omap3_sdrc_mr_0 | 241 | ldr r11, omap3_sdrc_mr_0 |
230 | str r12, [r11] | 242 | str r12, [r11] |
243 | #endif | ||
231 | ldr r12, omap_sdrc_rfr_ctrl_1_val | 244 | ldr r12, omap_sdrc_rfr_ctrl_1_val |
232 | cmp r12, #0 @ if SDRC_RFR_CTRL_1 is 0, | 245 | cmp r12, #0 @ if SDRC_RFR_CTRL_1 is 0, |
233 | beq skip_cs1_prog @ do not program cs1 params | 246 | beq skip_cs1_prog @ do not program cs1 params |
234 | ldr r11, omap3_sdrc_rfr_ctrl_1 | 247 | ldr r11, omap3_sdrc_rfr_ctrl_1 |
235 | str r12, [r11] | 248 | str r12, [r11] |
249 | #ifdef CONFIG_OMAP3_SDRC_AC_TIMING | ||
236 | ldr r12, omap_sdrc_actim_ctrl_a_1_val | 250 | ldr r12, omap_sdrc_actim_ctrl_a_1_val |
237 | ldr r11, omap3_sdrc_actim_ctrl_a_1 | 251 | ldr r11, omap3_sdrc_actim_ctrl_a_1 |
238 | str r12, [r11] | 252 | str r12, [r11] |
@@ -242,6 +256,7 @@ configure_sdrc: | |||
242 | ldr r12, omap_sdrc_mr_1_val | 256 | ldr r12, omap_sdrc_mr_1_val |
243 | ldr r11, omap3_sdrc_mr_1 | 257 | ldr r11, omap3_sdrc_mr_1 |
244 | str r12, [r11] | 258 | str r12, [r11] |
259 | #endif | ||
245 | skip_cs1_prog: | 260 | skip_cs1_prog: |
246 | ldr r12, [r11] @ posted-write barrier for SDRC | 261 | ldr r12, [r11] @ posted-write barrier for SDRC |
247 | bx lr | 262 | bx lr |
diff --git a/arch/arm/mach-omap2/usb-ehci.c b/arch/arm/mach-omap2/usb-ehci.c index e448abd5ec5d..f1df873d59db 100644 --- a/arch/arm/mach-omap2/usb-ehci.c +++ b/arch/arm/mach-omap2/usb-ehci.c | |||
@@ -27,6 +27,8 @@ | |||
27 | #include <mach/irqs.h> | 27 | #include <mach/irqs.h> |
28 | #include <plat/usb.h> | 28 | #include <plat/usb.h> |
29 | 29 | ||
30 | #include "mux.h" | ||
31 | |||
30 | #if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_EHCI_HCD_MODULE) | 32 | #if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_EHCI_HCD_MODULE) |
31 | 33 | ||
32 | static struct resource ehci_resources[] = { | 34 | static struct resource ehci_resources[] = { |
@@ -72,32 +74,44 @@ static void setup_ehci_io_mux(enum ehci_hcd_omap_mode *port_mode) | |||
72 | { | 74 | { |
73 | switch (port_mode[0]) { | 75 | switch (port_mode[0]) { |
74 | case EHCI_HCD_OMAP_MODE_PHY: | 76 | case EHCI_HCD_OMAP_MODE_PHY: |
75 | omap_cfg_reg(Y9_3430_USB1HS_PHY_STP); | 77 | omap_mux_init_signal("hsusb1_stp", OMAP_PIN_OUTPUT); |
76 | omap_cfg_reg(Y8_3430_USB1HS_PHY_CLK); | 78 | omap_mux_init_signal("hsusb1_clk", OMAP_PIN_OUTPUT); |
77 | omap_cfg_reg(AA14_3430_USB1HS_PHY_DIR); | 79 | omap_mux_init_signal("hsusb1_dir", OMAP_PIN_INPUT_PULLDOWN); |
78 | omap_cfg_reg(AA11_3430_USB1HS_PHY_NXT); | 80 | omap_mux_init_signal("hsusb1_nxt", OMAP_PIN_INPUT_PULLDOWN); |
79 | omap_cfg_reg(W13_3430_USB1HS_PHY_DATA0); | 81 | omap_mux_init_signal("hsusb1_data0", OMAP_PIN_INPUT_PULLDOWN); |
80 | omap_cfg_reg(W12_3430_USB1HS_PHY_DATA1); | 82 | omap_mux_init_signal("hsusb1_data1", OMAP_PIN_INPUT_PULLDOWN); |
81 | omap_cfg_reg(W11_3430_USB1HS_PHY_DATA2); | 83 | omap_mux_init_signal("hsusb1_data2", OMAP_PIN_INPUT_PULLDOWN); |
82 | omap_cfg_reg(Y11_3430_USB1HS_PHY_DATA3); | 84 | omap_mux_init_signal("hsusb1_data3", OMAP_PIN_INPUT_PULLDOWN); |
83 | omap_cfg_reg(W9_3430_USB1HS_PHY_DATA4); | 85 | omap_mux_init_signal("hsusb1_data4", OMAP_PIN_INPUT_PULLDOWN); |
84 | omap_cfg_reg(Y12_3430_USB1HS_PHY_DATA5); | 86 | omap_mux_init_signal("hsusb1_data5", OMAP_PIN_INPUT_PULLDOWN); |
85 | omap_cfg_reg(W8_3430_USB1HS_PHY_DATA6); | 87 | omap_mux_init_signal("hsusb1_data6", OMAP_PIN_INPUT_PULLDOWN); |
86 | omap_cfg_reg(Y13_3430_USB1HS_PHY_DATA7); | 88 | omap_mux_init_signal("hsusb1_data7", OMAP_PIN_INPUT_PULLDOWN); |
87 | break; | 89 | break; |
88 | case EHCI_HCD_OMAP_MODE_TLL: | 90 | case EHCI_HCD_OMAP_MODE_TLL: |
89 | omap_cfg_reg(Y9_3430_USB1HS_TLL_STP); | 91 | omap_mux_init_signal("hsusb1_tll_stp", |
90 | omap_cfg_reg(Y8_3430_USB1HS_TLL_CLK); | 92 | OMAP_PIN_INPUT_PULLUP); |
91 | omap_cfg_reg(AA14_3430_USB1HS_TLL_DIR); | 93 | omap_mux_init_signal("hsusb1_tll_clk", |
92 | omap_cfg_reg(AA11_3430_USB1HS_TLL_NXT); | 94 | OMAP_PIN_INPUT_PULLDOWN); |
93 | omap_cfg_reg(W13_3430_USB1HS_TLL_DATA0); | 95 | omap_mux_init_signal("hsusb1_tll_dir", |
94 | omap_cfg_reg(W12_3430_USB1HS_TLL_DATA1); | 96 | OMAP_PIN_INPUT_PULLDOWN); |
95 | omap_cfg_reg(W11_3430_USB1HS_TLL_DATA2); | 97 | omap_mux_init_signal("hsusb1_tll_nxt", |
96 | omap_cfg_reg(Y11_3430_USB1HS_TLL_DATA3); | 98 | OMAP_PIN_INPUT_PULLDOWN); |
97 | omap_cfg_reg(W9_3430_USB1HS_TLL_DATA4); | 99 | omap_mux_init_signal("hsusb1_tll_data0", |
98 | omap_cfg_reg(Y12_3430_USB1HS_TLL_DATA5); | 100 | OMAP_PIN_INPUT_PULLDOWN); |
99 | omap_cfg_reg(W8_3430_USB1HS_TLL_DATA6); | 101 | omap_mux_init_signal("hsusb1_tll_data1", |
100 | omap_cfg_reg(Y13_3430_USB1HS_TLL_DATA7); | 102 | OMAP_PIN_INPUT_PULLDOWN); |
103 | omap_mux_init_signal("hsusb1_tll_data2", | ||
104 | OMAP_PIN_INPUT_PULLDOWN); | ||
105 | omap_mux_init_signal("hsusb1_tll_data3", | ||
106 | OMAP_PIN_INPUT_PULLDOWN); | ||
107 | omap_mux_init_signal("hsusb1_tll_data4", | ||
108 | OMAP_PIN_INPUT_PULLDOWN); | ||
109 | omap_mux_init_signal("hsusb1_tll_data5", | ||
110 | OMAP_PIN_INPUT_PULLDOWN); | ||
111 | omap_mux_init_signal("hsusb1_tll_data6", | ||
112 | OMAP_PIN_INPUT_PULLDOWN); | ||
113 | omap_mux_init_signal("hsusb1_tll_data7", | ||
114 | OMAP_PIN_INPUT_PULLDOWN); | ||
101 | break; | 115 | break; |
102 | case EHCI_HCD_OMAP_MODE_UNKNOWN: | 116 | case EHCI_HCD_OMAP_MODE_UNKNOWN: |
103 | /* FALLTHROUGH */ | 117 | /* FALLTHROUGH */ |
@@ -107,32 +121,52 @@ static void setup_ehci_io_mux(enum ehci_hcd_omap_mode *port_mode) | |||
107 | 121 | ||
108 | switch (port_mode[1]) { | 122 | switch (port_mode[1]) { |
109 | case EHCI_HCD_OMAP_MODE_PHY: | 123 | case EHCI_HCD_OMAP_MODE_PHY: |
110 | omap_cfg_reg(AA10_3430_USB2HS_PHY_STP); | 124 | omap_mux_init_signal("hsusb2_stp", OMAP_PIN_OUTPUT); |
111 | omap_cfg_reg(AA8_3430_USB2HS_PHY_CLK); | 125 | omap_mux_init_signal("hsusb2_clk", OMAP_PIN_OUTPUT); |
112 | omap_cfg_reg(AA9_3430_USB2HS_PHY_DIR); | 126 | omap_mux_init_signal("hsusb2_dir", OMAP_PIN_INPUT_PULLDOWN); |
113 | omap_cfg_reg(AB11_3430_USB2HS_PHY_NXT); | 127 | omap_mux_init_signal("hsusb2_nxt", OMAP_PIN_INPUT_PULLDOWN); |
114 | omap_cfg_reg(AB10_3430_USB2HS_PHY_DATA0); | 128 | omap_mux_init_signal("hsusb2_data0", |
115 | omap_cfg_reg(AB9_3430_USB2HS_PHY_DATA1); | 129 | OMAP_PIN_INPUT_PULLDOWN); |
116 | omap_cfg_reg(W3_3430_USB2HS_PHY_DATA2); | 130 | omap_mux_init_signal("hsusb2_data1", |
117 | omap_cfg_reg(T4_3430_USB2HS_PHY_DATA3); | 131 | OMAP_PIN_INPUT_PULLDOWN); |
118 | omap_cfg_reg(T3_3430_USB2HS_PHY_DATA4); | 132 | omap_mux_init_signal("hsusb2_data2", |
119 | omap_cfg_reg(R3_3430_USB2HS_PHY_DATA5); | 133 | OMAP_PIN_INPUT_PULLDOWN); |
120 | omap_cfg_reg(R4_3430_USB2HS_PHY_DATA6); | 134 | omap_mux_init_signal("hsusb2_data3", |
121 | omap_cfg_reg(T2_3430_USB2HS_PHY_DATA7); | 135 | OMAP_PIN_INPUT_PULLDOWN); |
136 | omap_mux_init_signal("hsusb2_data4", | ||
137 | OMAP_PIN_INPUT_PULLDOWN); | ||
138 | omap_mux_init_signal("hsusb2_data5", | ||
139 | OMAP_PIN_INPUT_PULLDOWN); | ||
140 | omap_mux_init_signal("hsusb2_data6", | ||
141 | OMAP_PIN_INPUT_PULLDOWN); | ||
142 | omap_mux_init_signal("hsusb2_data7", | ||
143 | OMAP_PIN_INPUT_PULLDOWN); | ||
122 | break; | 144 | break; |
123 | case EHCI_HCD_OMAP_MODE_TLL: | 145 | case EHCI_HCD_OMAP_MODE_TLL: |
124 | omap_cfg_reg(AA10_3430_USB2HS_TLL_STP); | 146 | omap_mux_init_signal("hsusb2_tll_stp", |
125 | omap_cfg_reg(AA8_3430_USB2HS_TLL_CLK); | 147 | OMAP_PIN_INPUT_PULLUP); |
126 | omap_cfg_reg(AA9_3430_USB2HS_TLL_DIR); | 148 | omap_mux_init_signal("hsusb2_tll_clk", |
127 | omap_cfg_reg(AB11_3430_USB2HS_TLL_NXT); | 149 | OMAP_PIN_INPUT_PULLDOWN); |
128 | omap_cfg_reg(AB10_3430_USB2HS_TLL_DATA0); | 150 | omap_mux_init_signal("hsusb2_tll_dir", |
129 | omap_cfg_reg(AB9_3430_USB2HS_TLL_DATA1); | 151 | OMAP_PIN_INPUT_PULLDOWN); |
130 | omap_cfg_reg(W3_3430_USB2HS_TLL_DATA2); | 152 | omap_mux_init_signal("hsusb2_tll_nxt", |
131 | omap_cfg_reg(T4_3430_USB2HS_TLL_DATA3); | 153 | OMAP_PIN_INPUT_PULLDOWN); |
132 | omap_cfg_reg(T3_3430_USB2HS_TLL_DATA4); | 154 | omap_mux_init_signal("hsusb2_tll_data0", |
133 | omap_cfg_reg(R3_3430_USB2HS_TLL_DATA5); | 155 | OMAP_PIN_INPUT_PULLDOWN); |
134 | omap_cfg_reg(R4_3430_USB2HS_TLL_DATA6); | 156 | omap_mux_init_signal("hsusb2_tll_data1", |
135 | omap_cfg_reg(T2_3430_USB2HS_TLL_DATA7); | 157 | OMAP_PIN_INPUT_PULLDOWN); |
158 | omap_mux_init_signal("hsusb2_tll_data2", | ||
159 | OMAP_PIN_INPUT_PULLDOWN); | ||
160 | omap_mux_init_signal("hsusb2_tll_data3", | ||
161 | OMAP_PIN_INPUT_PULLDOWN); | ||
162 | omap_mux_init_signal("hsusb2_tll_data4", | ||
163 | OMAP_PIN_INPUT_PULLDOWN); | ||
164 | omap_mux_init_signal("hsusb2_tll_data5", | ||
165 | OMAP_PIN_INPUT_PULLDOWN); | ||
166 | omap_mux_init_signal("hsusb2_tll_data6", | ||
167 | OMAP_PIN_INPUT_PULLDOWN); | ||
168 | omap_mux_init_signal("hsusb2_tll_data7", | ||
169 | OMAP_PIN_INPUT_PULLDOWN); | ||
136 | break; | 170 | break; |
137 | case EHCI_HCD_OMAP_MODE_UNKNOWN: | 171 | case EHCI_HCD_OMAP_MODE_UNKNOWN: |
138 | /* FALLTHROUGH */ | 172 | /* FALLTHROUGH */ |
@@ -145,18 +179,30 @@ static void setup_ehci_io_mux(enum ehci_hcd_omap_mode *port_mode) | |||
145 | printk(KERN_WARNING "Port3 can't be used in PHY mode\n"); | 179 | printk(KERN_WARNING "Port3 can't be used in PHY mode\n"); |
146 | break; | 180 | break; |
147 | case EHCI_HCD_OMAP_MODE_TLL: | 181 | case EHCI_HCD_OMAP_MODE_TLL: |
148 | omap_cfg_reg(AB3_3430_USB3HS_TLL_STP); | 182 | omap_mux_init_signal("hsusb3_tll_stp", |
149 | omap_cfg_reg(AA6_3430_USB3HS_TLL_CLK); | 183 | OMAP_PIN_INPUT_PULLUP); |
150 | omap_cfg_reg(AA3_3430_USB3HS_TLL_DIR); | 184 | omap_mux_init_signal("hsusb3_tll_clk", |
151 | omap_cfg_reg(Y3_3430_USB3HS_TLL_NXT); | 185 | OMAP_PIN_INPUT_PULLDOWN); |
152 | omap_cfg_reg(AA5_3430_USB3HS_TLL_DATA0); | 186 | omap_mux_init_signal("hsusb3_tll_dir", |
153 | omap_cfg_reg(Y4_3430_USB3HS_TLL_DATA1); | 187 | OMAP_PIN_INPUT_PULLDOWN); |
154 | omap_cfg_reg(Y5_3430_USB3HS_TLL_DATA2); | 188 | omap_mux_init_signal("hsusb3_tll_nxt", |
155 | omap_cfg_reg(W5_3430_USB3HS_TLL_DATA3); | 189 | OMAP_PIN_INPUT_PULLDOWN); |
156 | omap_cfg_reg(AB12_3430_USB3HS_TLL_DATA4); | 190 | omap_mux_init_signal("hsusb3_tll_data0", |
157 | omap_cfg_reg(AB13_3430_USB3HS_TLL_DATA5); | 191 | OMAP_PIN_INPUT_PULLDOWN); |
158 | omap_cfg_reg(AA13_3430_USB3HS_TLL_DATA6); | 192 | omap_mux_init_signal("hsusb3_tll_data1", |
159 | omap_cfg_reg(AA12_3430_USB3HS_TLL_DATA7); | 193 | OMAP_PIN_INPUT_PULLDOWN); |
194 | omap_mux_init_signal("hsusb3_tll_data2", | ||
195 | OMAP_PIN_INPUT_PULLDOWN); | ||
196 | omap_mux_init_signal("hsusb3_tll_data3", | ||
197 | OMAP_PIN_INPUT_PULLDOWN); | ||
198 | omap_mux_init_signal("hsusb3_tll_data4", | ||
199 | OMAP_PIN_INPUT_PULLDOWN); | ||
200 | omap_mux_init_signal("hsusb3_tll_data5", | ||
201 | OMAP_PIN_INPUT_PULLDOWN); | ||
202 | omap_mux_init_signal("hsusb3_tll_data6", | ||
203 | OMAP_PIN_INPUT_PULLDOWN); | ||
204 | omap_mux_init_signal("hsusb3_tll_data7", | ||
205 | OMAP_PIN_INPUT_PULLDOWN); | ||
160 | break; | 206 | break; |
161 | case EHCI_HCD_OMAP_MODE_UNKNOWN: | 207 | case EHCI_HCD_OMAP_MODE_UNKNOWN: |
162 | /* FALLTHROUGH */ | 208 | /* FALLTHROUGH */ |
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig index d89c6adbe8bc..e6d8e10ae5d1 100644 --- a/arch/arm/mach-pxa/Kconfig +++ b/arch/arm/mach-pxa/Kconfig | |||
@@ -63,6 +63,15 @@ config ARCH_VIPER | |||
63 | select HAVE_PWM | 63 | select HAVE_PWM |
64 | select PXA_HAVE_BOARD_IRQS | 64 | select PXA_HAVE_BOARD_IRQS |
65 | select PXA_HAVE_ISA_IRQS | 65 | select PXA_HAVE_ISA_IRQS |
66 | select ARCOM_PCMCIA | ||
67 | |||
68 | config MACH_ARCOM_ZEUS | ||
69 | bool "Arcom/Eurotech ZEUS SBC" | ||
70 | select PXA27x | ||
71 | select ISA | ||
72 | select PXA_HAVE_BOARD_IRQS | ||
73 | select PXA_HAVE_ISA_IRQS | ||
74 | select ARCOM_PCMCIA | ||
66 | 75 | ||
67 | config MACH_BALLOON3 | 76 | config MACH_BALLOON3 |
68 | bool "Balloon 3 board" | 77 | bool "Balloon 3 board" |
@@ -179,6 +188,11 @@ config MACH_TRIZEPS_ANY | |||
179 | 188 | ||
180 | endchoice | 189 | endchoice |
181 | 190 | ||
191 | config ARCOM_PCMCIA | ||
192 | bool | ||
193 | help | ||
194 | Generic option for Arcom Viper/Zeus PCMCIA | ||
195 | |||
182 | config TRIZEPS_PCMCIA | 196 | config TRIZEPS_PCMCIA |
183 | bool | 197 | bool |
184 | help | 198 | help |
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile index b5d29e60a341..f64afda7e6f6 100644 --- a/arch/arm/mach-pxa/Makefile +++ b/arch/arm/mach-pxa/Makefile | |||
@@ -38,6 +38,7 @@ obj-$(CONFIG_MACH_SAAR) += saar.o | |||
38 | # 3rd Party Dev Platforms | 38 | # 3rd Party Dev Platforms |
39 | obj-$(CONFIG_ARCH_PXA_IDP) += idp.o | 39 | obj-$(CONFIG_ARCH_PXA_IDP) += idp.o |
40 | obj-$(CONFIG_ARCH_VIPER) += viper.o | 40 | obj-$(CONFIG_ARCH_VIPER) += viper.o |
41 | obj-$(CONFIG_MACH_ARCOM_ZEUS) += zeus.o | ||
41 | obj-$(CONFIG_MACH_BALLOON3) += balloon3.o | 42 | obj-$(CONFIG_MACH_BALLOON3) += balloon3.o |
42 | obj-$(CONFIG_MACH_CSB726) += csb726.o | 43 | obj-$(CONFIG_MACH_CSB726) += csb726.o |
43 | obj-$(CONFIG_CSB726_CSB701) += csb701.o | 44 | obj-$(CONFIG_CSB726_CSB701) += csb701.o |
diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c index 1c0de808b54d..c8a01bc85fde 100644 --- a/arch/arm/mach-pxa/em-x270.c +++ b/arch/arm/mach-pxa/em-x270.c | |||
@@ -497,16 +497,15 @@ static int em_x270_usb_hub_init(void) | |||
497 | goto err_free_vbus_gpio; | 497 | goto err_free_vbus_gpio; |
498 | 498 | ||
499 | /* USB Hub power-on and reset */ | 499 | /* USB Hub power-on and reset */ |
500 | gpio_direction_output(usb_hub_reset, 0); | 500 | gpio_direction_output(usb_hub_reset, 1); |
501 | gpio_direction_output(GPIO9_USB_VBUS_EN, 0); | ||
501 | regulator_enable(em_x270_usb_ldo); | 502 | regulator_enable(em_x270_usb_ldo); |
502 | gpio_set_value(usb_hub_reset, 1); | ||
503 | gpio_set_value(usb_hub_reset, 0); | 503 | gpio_set_value(usb_hub_reset, 0); |
504 | gpio_set_value(usb_hub_reset, 1); | ||
504 | regulator_disable(em_x270_usb_ldo); | 505 | regulator_disable(em_x270_usb_ldo); |
505 | regulator_enable(em_x270_usb_ldo); | 506 | regulator_enable(em_x270_usb_ldo); |
506 | gpio_set_value(usb_hub_reset, 1); | 507 | gpio_set_value(usb_hub_reset, 0); |
507 | 508 | gpio_set_value(GPIO9_USB_VBUS_EN, 1); | |
508 | /* enable VBUS */ | ||
509 | gpio_direction_output(GPIO9_USB_VBUS_EN, 1); | ||
510 | 509 | ||
511 | return 0; | 510 | return 0; |
512 | 511 | ||
diff --git a/arch/arm/mach-pxa/include/mach/arcom-pcmcia.h b/arch/arm/mach-pxa/include/mach/arcom-pcmcia.h new file mode 100644 index 000000000000..d428be4db44c --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/arcom-pcmcia.h | |||
@@ -0,0 +1,11 @@ | |||
1 | #ifndef __ARCOM_PCMCIA_H | ||
2 | #define __ARCOM_PCMCIA_H | ||
3 | |||
4 | struct arcom_pcmcia_pdata { | ||
5 | int cd_gpio; | ||
6 | int rdy_gpio; | ||
7 | int pwr_gpio; | ||
8 | void (*reset)(int state); | ||
9 | }; | ||
10 | |||
11 | #endif | ||
diff --git a/arch/arm/mach-pxa/include/mach/viper.h b/arch/arm/mach-pxa/include/mach/viper.h index 10988c270ca3..5f5fbf1f6489 100644 --- a/arch/arm/mach-pxa/include/mach/viper.h +++ b/arch/arm/mach-pxa/include/mach/viper.h | |||
@@ -85,8 +85,6 @@ | |||
85 | /* Interrupt and Configuration Register (VIPER_ICR) */ | 85 | /* Interrupt and Configuration Register (VIPER_ICR) */ |
86 | /* This is a write only register. Only CF_RST is used under Linux */ | 86 | /* This is a write only register. Only CF_RST is used under Linux */ |
87 | 87 | ||
88 | extern void viper_cf_rst(int state); | ||
89 | |||
90 | #define VIPER_ICR_RETRIG (1 << 0) | 88 | #define VIPER_ICR_RETRIG (1 << 0) |
91 | #define VIPER_ICR_AUTO_CLR (1 << 1) | 89 | #define VIPER_ICR_AUTO_CLR (1 << 1) |
92 | #define VIPER_ICR_R_DIS (1 << 2) | 90 | #define VIPER_ICR_R_DIS (1 << 2) |
diff --git a/arch/arm/mach-pxa/include/mach/zeus.h b/arch/arm/mach-pxa/include/mach/zeus.h new file mode 100644 index 000000000000..c387046d2f28 --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/zeus.h | |||
@@ -0,0 +1,82 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-pxa/include/mach/zeus.h | ||
3 | * | ||
4 | * Author: David Vrabel | ||
5 | * Created: Sept 28, 2005 | ||
6 | * Copyright: Arcom Control Systems Ltd. | ||
7 | * | ||
8 | * Maintained by: Marc Zyngier <maz@misterjones.org> | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #ifndef _MACH_ZEUS_H | ||
16 | #define _MACH_ZEUS_H | ||
17 | |||
18 | /* Physical addresses */ | ||
19 | #define ZEUS_FLASH_PHYS PXA_CS0_PHYS | ||
20 | #define ZEUS_ETH0_PHYS PXA_CS1_PHYS | ||
21 | #define ZEUS_ETH1_PHYS PXA_CS2_PHYS | ||
22 | #define ZEUS_CPLD_PHYS (PXA_CS4_PHYS+0x2000000) | ||
23 | #define ZEUS_SRAM_PHYS PXA_CS5_PHYS | ||
24 | #define ZEUS_PC104IO_PHYS (0x30000000) | ||
25 | |||
26 | #define ZEUS_CPLD_VERSION_PHYS (ZEUS_CPLD_PHYS + 0x00000000) | ||
27 | #define ZEUS_CPLD_ISA_IRQ_PHYS (ZEUS_CPLD_PHYS + 0x00800000) | ||
28 | #define ZEUS_CPLD_CONTROL_PHYS (ZEUS_CPLD_PHYS + 0x01000000) | ||
29 | #define ZEUS_CPLD_EXTWDOG_PHYS (ZEUS_CPLD_PHYS + 0x01800000) | ||
30 | |||
31 | /* GPIOs */ | ||
32 | #define ZEUS_AC97_GPIO 0 | ||
33 | #define ZEUS_WAKEUP_GPIO 1 | ||
34 | #define ZEUS_UARTA_GPIO 9 | ||
35 | #define ZEUS_UARTB_GPIO 10 | ||
36 | #define ZEUS_UARTC_GPIO 12 | ||
37 | #define ZEUS_UARTD_GPIO 11 | ||
38 | #define ZEUS_ETH0_GPIO 14 | ||
39 | #define ZEUS_ISA_GPIO 17 | ||
40 | #define ZEUS_BKLEN_GPIO 19 | ||
41 | #define ZEUS_USB2_PWREN_GPIO 22 | ||
42 | #define ZEUS_PTT_GPIO 27 | ||
43 | #define ZEUS_CF_CD_GPIO 35 | ||
44 | #define ZEUS_MMC_WP_GPIO 52 | ||
45 | #define ZEUS_MMC_CD_GPIO 53 | ||
46 | #define ZEUS_EXTGPIO_GPIO 91 | ||
47 | #define ZEUS_CF_PWEN_GPIO 97 | ||
48 | #define ZEUS_CF_RDY_GPIO 99 | ||
49 | #define ZEUS_LCD_EN_GPIO 101 | ||
50 | #define ZEUS_ETH1_GPIO 113 | ||
51 | #define ZEUS_CAN_GPIO 116 | ||
52 | |||
53 | #define ZEUS_EXT0_GPIO_BASE 128 | ||
54 | #define ZEUS_EXT1_GPIO_BASE 160 | ||
55 | #define ZEUS_USER_GPIO_BASE 192 | ||
56 | |||
57 | #define ZEUS_EXT0_GPIO(x) (ZEUS_EXT0_GPIO_BASE + (x)) | ||
58 | #define ZEUS_EXT1_GPIO(x) (ZEUS_EXT1_GPIO_BASE + (x)) | ||
59 | #define ZEUS_USER_GPIO(x) (ZEUS_USER_GPIO_BASE + (x)) | ||
60 | |||
61 | /* | ||
62 | * CPLD registers: | ||
63 | * Only 4 registers, but spreaded over a 32MB address space. | ||
64 | * Be gentle, and remap that over 32kB... | ||
65 | */ | ||
66 | |||
67 | #define ZEUS_CPLD (0xf0000000) | ||
68 | #define ZEUS_CPLD_VERSION (ZEUS_CPLD + 0x0000) | ||
69 | #define ZEUS_CPLD_ISA_IRQ (ZEUS_CPLD + 0x1000) | ||
70 | #define ZEUS_CPLD_CONTROL (ZEUS_CPLD + 0x2000) | ||
71 | #define ZEUS_CPLD_EXTWDOG (ZEUS_CPLD + 0x3000) | ||
72 | |||
73 | /* CPLD register bits */ | ||
74 | #define ZEUS_CPLD_CONTROL_CF_RST 0x01 | ||
75 | |||
76 | #define ZEUS_PC104IO (0xf1000000) | ||
77 | |||
78 | #define ZEUS_SRAM_SIZE (256 * 1024) | ||
79 | |||
80 | #endif | ||
81 | |||
82 | |||
diff --git a/arch/arm/mach-pxa/viper.c b/arch/arm/mach-pxa/viper.c index cf0d71b7797e..5352b4e5a7dd 100644 --- a/arch/arm/mach-pxa/viper.c +++ b/arch/arm/mach-pxa/viper.c | |||
@@ -47,6 +47,7 @@ | |||
47 | #include <mach/pxafb.h> | 47 | #include <mach/pxafb.h> |
48 | #include <plat/i2c.h> | 48 | #include <plat/i2c.h> |
49 | #include <mach/regs-uart.h> | 49 | #include <mach/regs-uart.h> |
50 | #include <mach/arcom-pcmcia.h> | ||
50 | #include <mach/viper.h> | 51 | #include <mach/viper.h> |
51 | 52 | ||
52 | #include <asm/setup.h> | 53 | #include <asm/setup.h> |
@@ -76,14 +77,28 @@ static void viper_icr_clear_bit(unsigned int bit) | |||
76 | } | 77 | } |
77 | 78 | ||
78 | /* This function is used from the pcmcia module to reset the CF */ | 79 | /* This function is used from the pcmcia module to reset the CF */ |
79 | void viper_cf_rst(int state) | 80 | static void viper_cf_reset(int state) |
80 | { | 81 | { |
81 | if (state) | 82 | if (state) |
82 | viper_icr_set_bit(VIPER_ICR_CF_RST); | 83 | viper_icr_set_bit(VIPER_ICR_CF_RST); |
83 | else | 84 | else |
84 | viper_icr_clear_bit(VIPER_ICR_CF_RST); | 85 | viper_icr_clear_bit(VIPER_ICR_CF_RST); |
85 | } | 86 | } |
86 | EXPORT_SYMBOL(viper_cf_rst); | 87 | |
88 | static struct arcom_pcmcia_pdata viper_pcmcia_info = { | ||
89 | .cd_gpio = VIPER_CF_CD_GPIO, | ||
90 | .rdy_gpio = VIPER_CF_RDY_GPIO, | ||
91 | .pwr_gpio = VIPER_CF_POWER_GPIO, | ||
92 | .reset = viper_cf_reset, | ||
93 | }; | ||
94 | |||
95 | static struct platform_device viper_pcmcia_device = { | ||
96 | .name = "viper-pcmcia", | ||
97 | .id = -1, | ||
98 | .dev = { | ||
99 | .platform_data = &viper_pcmcia_info, | ||
100 | }, | ||
101 | }; | ||
87 | 102 | ||
88 | /* | 103 | /* |
89 | * The CPLD version register was not present on VIPER boards prior to | 104 | * The CPLD version register was not present on VIPER boards prior to |
@@ -685,6 +700,7 @@ static struct platform_device *viper_devs[] __initdata = { | |||
685 | &viper_mtd_devices[0], | 700 | &viper_mtd_devices[0], |
686 | &viper_mtd_devices[1], | 701 | &viper_mtd_devices[1], |
687 | &viper_backlight_device, | 702 | &viper_backlight_device, |
703 | &viper_pcmcia_device, | ||
688 | }; | 704 | }; |
689 | 705 | ||
690 | static mfp_cfg_t viper_pin_config[] __initdata = { | 706 | static mfp_cfg_t viper_pin_config[] __initdata = { |
diff --git a/arch/arm/mach-pxa/zeus.c b/arch/arm/mach-pxa/zeus.c new file mode 100644 index 000000000000..5b986a8bd9e6 --- /dev/null +++ b/arch/arm/mach-pxa/zeus.c | |||
@@ -0,0 +1,820 @@ | |||
1 | /* | ||
2 | * Support for the Arcom ZEUS. | ||
3 | * | ||
4 | * Copyright (C) 2006 Arcom Control Systems Ltd. | ||
5 | * | ||
6 | * Loosely based on Arcom's 2.6.16.28. | ||
7 | * Maintained by Marc Zyngier <maz@misterjones.org> | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License version 2 as | ||
11 | * published by the Free Software Foundation. | ||
12 | */ | ||
13 | |||
14 | #include <linux/cpufreq.h> | ||
15 | #include <linux/interrupt.h> | ||
16 | #include <linux/irq.h> | ||
17 | #include <linux/pm.h> | ||
18 | #include <linux/gpio.h> | ||
19 | #include <linux/serial_8250.h> | ||
20 | #include <linux/dm9000.h> | ||
21 | #include <linux/mmc/host.h> | ||
22 | #include <linux/spi/spi.h> | ||
23 | #include <linux/mtd/mtd.h> | ||
24 | #include <linux/mtd/partitions.h> | ||
25 | #include <linux/mtd/physmap.h> | ||
26 | #include <linux/i2c.h> | ||
27 | #include <linux/i2c/pca953x.h> | ||
28 | |||
29 | #include <asm/mach-types.h> | ||
30 | #include <asm/mach/arch.h> | ||
31 | #include <asm/mach/map.h> | ||
32 | |||
33 | #include <plat/i2c.h> | ||
34 | |||
35 | #include <mach/pxa2xx-regs.h> | ||
36 | #include <mach/regs-uart.h> | ||
37 | #include <mach/ohci.h> | ||
38 | #include <mach/mmc.h> | ||
39 | #include <mach/pxa27x-udc.h> | ||
40 | #include <mach/udc.h> | ||
41 | #include <mach/pxafb.h> | ||
42 | #include <mach/pxa2xx_spi.h> | ||
43 | #include <mach/mfp-pxa27x.h> | ||
44 | #include <mach/pm.h> | ||
45 | #include <mach/audio.h> | ||
46 | #include <mach/arcom-pcmcia.h> | ||
47 | #include <mach/zeus.h> | ||
48 | |||
49 | #include "generic.h" | ||
50 | |||
51 | /* | ||
52 | * Interrupt handling | ||
53 | */ | ||
54 | |||
55 | static unsigned long zeus_irq_enabled_mask; | ||
56 | static const int zeus_isa_irqs[] = { 3, 4, 5, 6, 7, 10, 11, 12, }; | ||
57 | static const int zeus_isa_irq_map[] = { | ||
58 | 0, /* ISA irq #0, invalid */ | ||
59 | 0, /* ISA irq #1, invalid */ | ||
60 | 0, /* ISA irq #2, invalid */ | ||
61 | 1 << 0, /* ISA irq #3 */ | ||
62 | 1 << 1, /* ISA irq #4 */ | ||
63 | 1 << 2, /* ISA irq #5 */ | ||
64 | 1 << 3, /* ISA irq #6 */ | ||
65 | 1 << 4, /* ISA irq #7 */ | ||
66 | 0, /* ISA irq #8, invalid */ | ||
67 | 0, /* ISA irq #9, invalid */ | ||
68 | 1 << 5, /* ISA irq #10 */ | ||
69 | 1 << 6, /* ISA irq #11 */ | ||
70 | 1 << 7, /* ISA irq #12 */ | ||
71 | }; | ||
72 | |||
73 | static inline int zeus_irq_to_bitmask(unsigned int irq) | ||
74 | { | ||
75 | return zeus_isa_irq_map[irq - PXA_ISA_IRQ(0)]; | ||
76 | } | ||
77 | |||
78 | static inline int zeus_bit_to_irq(int bit) | ||
79 | { | ||
80 | return zeus_isa_irqs[bit] + PXA_ISA_IRQ(0); | ||
81 | } | ||
82 | |||
83 | static void zeus_ack_irq(unsigned int irq) | ||
84 | { | ||
85 | __raw_writew(zeus_irq_to_bitmask(irq), ZEUS_CPLD_ISA_IRQ); | ||
86 | } | ||
87 | |||
88 | static void zeus_mask_irq(unsigned int irq) | ||
89 | { | ||
90 | zeus_irq_enabled_mask &= ~(zeus_irq_to_bitmask(irq)); | ||
91 | } | ||
92 | |||
93 | static void zeus_unmask_irq(unsigned int irq) | ||
94 | { | ||
95 | zeus_irq_enabled_mask |= zeus_irq_to_bitmask(irq); | ||
96 | } | ||
97 | |||
98 | static inline unsigned long zeus_irq_pending(void) | ||
99 | { | ||
100 | return __raw_readw(ZEUS_CPLD_ISA_IRQ) & zeus_irq_enabled_mask; | ||
101 | } | ||
102 | |||
103 | static void zeus_irq_handler(unsigned int irq, struct irq_desc *desc) | ||
104 | { | ||
105 | unsigned long pending; | ||
106 | |||
107 | pending = zeus_irq_pending(); | ||
108 | do { | ||
109 | /* we're in a chained irq handler, | ||
110 | * so ack the interrupt by hand */ | ||
111 | desc->chip->ack(gpio_to_irq(ZEUS_ISA_GPIO)); | ||
112 | |||
113 | if (likely(pending)) { | ||
114 | irq = zeus_bit_to_irq(__ffs(pending)); | ||
115 | generic_handle_irq(irq); | ||
116 | } | ||
117 | pending = zeus_irq_pending(); | ||
118 | } while (pending); | ||
119 | } | ||
120 | |||
121 | static struct irq_chip zeus_irq_chip = { | ||
122 | .name = "ISA", | ||
123 | .ack = zeus_ack_irq, | ||
124 | .mask = zeus_mask_irq, | ||
125 | .unmask = zeus_unmask_irq, | ||
126 | }; | ||
127 | |||
128 | static void __init zeus_init_irq(void) | ||
129 | { | ||
130 | int level; | ||
131 | int isa_irq; | ||
132 | |||
133 | pxa27x_init_irq(); | ||
134 | |||
135 | /* Peripheral IRQs. It would be nice to move those inside driver | ||
136 | configuration, but it is not supported at the moment. */ | ||
137 | set_irq_type(gpio_to_irq(ZEUS_AC97_GPIO), IRQ_TYPE_EDGE_RISING); | ||
138 | set_irq_type(gpio_to_irq(ZEUS_WAKEUP_GPIO), IRQ_TYPE_EDGE_RISING); | ||
139 | set_irq_type(gpio_to_irq(ZEUS_PTT_GPIO), IRQ_TYPE_EDGE_RISING); | ||
140 | set_irq_type(gpio_to_irq(ZEUS_EXTGPIO_GPIO), IRQ_TYPE_EDGE_FALLING); | ||
141 | set_irq_type(gpio_to_irq(ZEUS_CAN_GPIO), IRQ_TYPE_EDGE_FALLING); | ||
142 | |||
143 | /* Setup ISA IRQs */ | ||
144 | for (level = 0; level < ARRAY_SIZE(zeus_isa_irqs); level++) { | ||
145 | isa_irq = zeus_bit_to_irq(level); | ||
146 | set_irq_chip(isa_irq, &zeus_irq_chip); | ||
147 | set_irq_handler(isa_irq, handle_edge_irq); | ||
148 | set_irq_flags(isa_irq, IRQF_VALID | IRQF_PROBE); | ||
149 | } | ||
150 | |||
151 | set_irq_type(gpio_to_irq(ZEUS_ISA_GPIO), IRQ_TYPE_EDGE_RISING); | ||
152 | set_irq_chained_handler(gpio_to_irq(ZEUS_ISA_GPIO), zeus_irq_handler); | ||
153 | } | ||
154 | |||
155 | |||
156 | /* | ||
157 | * Platform devices | ||
158 | */ | ||
159 | |||
160 | /* Flash */ | ||
161 | static struct resource zeus_mtd_resources[] = { | ||
162 | [0] = { /* NOR Flash (up to 64MB) */ | ||
163 | .start = ZEUS_FLASH_PHYS, | ||
164 | .end = ZEUS_FLASH_PHYS + SZ_64M - 1, | ||
165 | .flags = IORESOURCE_MEM, | ||
166 | }, | ||
167 | [1] = { /* SRAM */ | ||
168 | .start = ZEUS_SRAM_PHYS, | ||
169 | .end = ZEUS_SRAM_PHYS + SZ_512K - 1, | ||
170 | .flags = IORESOURCE_MEM, | ||
171 | }, | ||
172 | }; | ||
173 | |||
174 | static struct physmap_flash_data zeus_flash_data[] = { | ||
175 | [0] = { | ||
176 | .width = 2, | ||
177 | .parts = NULL, | ||
178 | .nr_parts = 0, | ||
179 | }, | ||
180 | }; | ||
181 | |||
182 | static struct platform_device zeus_mtd_devices[] = { | ||
183 | [0] = { | ||
184 | .name = "physmap-flash", | ||
185 | .id = 0, | ||
186 | .dev = { | ||
187 | .platform_data = &zeus_flash_data[0], | ||
188 | }, | ||
189 | .resource = &zeus_mtd_resources[0], | ||
190 | .num_resources = 1, | ||
191 | }, | ||
192 | }; | ||
193 | |||
194 | /* Serial */ | ||
195 | static struct resource zeus_serial_resources[] = { | ||
196 | { | ||
197 | .start = 0x10000000, | ||
198 | .end = 0x1000000f, | ||
199 | .flags = IORESOURCE_MEM, | ||
200 | }, | ||
201 | { | ||
202 | .start = 0x10800000, | ||
203 | .end = 0x1080000f, | ||
204 | .flags = IORESOURCE_MEM, | ||
205 | }, | ||
206 | { | ||
207 | .start = 0x11000000, | ||
208 | .end = 0x1100000f, | ||
209 | .flags = IORESOURCE_MEM, | ||
210 | }, | ||
211 | { | ||
212 | .start = 0x40100000, | ||
213 | .end = 0x4010001f, | ||
214 | .flags = IORESOURCE_MEM, | ||
215 | }, | ||
216 | { | ||
217 | .start = 0x40200000, | ||
218 | .end = 0x4020001f, | ||
219 | .flags = IORESOURCE_MEM, | ||
220 | }, | ||
221 | { | ||
222 | .start = 0x40700000, | ||
223 | .end = 0x4070001f, | ||
224 | .flags = IORESOURCE_MEM, | ||
225 | }, | ||
226 | }; | ||
227 | |||
228 | static struct plat_serial8250_port serial_platform_data[] = { | ||
229 | /* External UARTs */ | ||
230 | /* FIXME: Shared IRQs on COM1-COM4 will not work properly on v1i1 hardware. */ | ||
231 | { /* COM1 */ | ||
232 | .mapbase = 0x10000000, | ||
233 | .irq = gpio_to_irq(ZEUS_UARTA_GPIO), | ||
234 | .irqflags = IRQF_TRIGGER_RISING, | ||
235 | .uartclk = 14745600, | ||
236 | .regshift = 1, | ||
237 | .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, | ||
238 | .iotype = UPIO_MEM, | ||
239 | }, | ||
240 | { /* COM2 */ | ||
241 | .mapbase = 0x10800000, | ||
242 | .irq = gpio_to_irq(ZEUS_UARTB_GPIO), | ||
243 | .irqflags = IRQF_TRIGGER_RISING, | ||
244 | .uartclk = 14745600, | ||
245 | .regshift = 1, | ||
246 | .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, | ||
247 | .iotype = UPIO_MEM, | ||
248 | }, | ||
249 | { /* COM3 */ | ||
250 | .mapbase = 0x11000000, | ||
251 | .irq = gpio_to_irq(ZEUS_UARTC_GPIO), | ||
252 | .irqflags = IRQF_TRIGGER_RISING, | ||
253 | .uartclk = 14745600, | ||
254 | .regshift = 1, | ||
255 | .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, | ||
256 | .iotype = UPIO_MEM, | ||
257 | }, | ||
258 | { /* COM4 */ | ||
259 | .mapbase = 0x11800000, | ||
260 | .irq = gpio_to_irq(ZEUS_UARTD_GPIO), | ||
261 | .irqflags = IRQF_TRIGGER_RISING, | ||
262 | .uartclk = 14745600, | ||
263 | .regshift = 1, | ||
264 | .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, | ||
265 | .iotype = UPIO_MEM, | ||
266 | }, | ||
267 | /* Internal UARTs */ | ||
268 | { /* FFUART */ | ||
269 | .membase = (void *)&FFUART, | ||
270 | .mapbase = __PREG(FFUART), | ||
271 | .irq = IRQ_FFUART, | ||
272 | .uartclk = 921600 * 16, | ||
273 | .regshift = 2, | ||
274 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, | ||
275 | .iotype = UPIO_MEM, | ||
276 | }, | ||
277 | { /* BTUART */ | ||
278 | .membase = (void *)&BTUART, | ||
279 | .mapbase = __PREG(BTUART), | ||
280 | .irq = IRQ_BTUART, | ||
281 | .uartclk = 921600 * 16, | ||
282 | .regshift = 2, | ||
283 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, | ||
284 | .iotype = UPIO_MEM, | ||
285 | }, | ||
286 | { /* STUART */ | ||
287 | .membase = (void *)&STUART, | ||
288 | .mapbase = __PREG(STUART), | ||
289 | .irq = IRQ_STUART, | ||
290 | .uartclk = 921600 * 16, | ||
291 | .regshift = 2, | ||
292 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, | ||
293 | .iotype = UPIO_MEM, | ||
294 | }, | ||
295 | { }, | ||
296 | }; | ||
297 | |||
298 | static struct platform_device zeus_serial_device = { | ||
299 | .name = "serial8250", | ||
300 | .id = PLAT8250_DEV_PLATFORM, | ||
301 | .dev = { | ||
302 | .platform_data = serial_platform_data, | ||
303 | }, | ||
304 | .num_resources = ARRAY_SIZE(zeus_serial_resources), | ||
305 | .resource = zeus_serial_resources, | ||
306 | }; | ||
307 | |||
308 | /* Ethernet */ | ||
309 | static struct resource zeus_dm9k0_resource[] = { | ||
310 | [0] = { | ||
311 | .start = ZEUS_ETH0_PHYS, | ||
312 | .end = ZEUS_ETH0_PHYS + 1, | ||
313 | .flags = IORESOURCE_MEM | ||
314 | }, | ||
315 | [1] = { | ||
316 | .start = ZEUS_ETH0_PHYS + 2, | ||
317 | .end = ZEUS_ETH0_PHYS + 3, | ||
318 | .flags = IORESOURCE_MEM | ||
319 | }, | ||
320 | [2] = { | ||
321 | .start = gpio_to_irq(ZEUS_ETH0_GPIO), | ||
322 | .end = gpio_to_irq(ZEUS_ETH0_GPIO), | ||
323 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE, | ||
324 | }, | ||
325 | }; | ||
326 | |||
327 | static struct resource zeus_dm9k1_resource[] = { | ||
328 | [0] = { | ||
329 | .start = ZEUS_ETH1_PHYS, | ||
330 | .end = ZEUS_ETH1_PHYS + 1, | ||
331 | .flags = IORESOURCE_MEM | ||
332 | }, | ||
333 | [1] = { | ||
334 | .start = ZEUS_ETH1_PHYS + 2, | ||
335 | .end = ZEUS_ETH1_PHYS + 3, | ||
336 | .flags = IORESOURCE_MEM, | ||
337 | }, | ||
338 | [2] = { | ||
339 | .start = gpio_to_irq(ZEUS_ETH1_GPIO), | ||
340 | .end = gpio_to_irq(ZEUS_ETH1_GPIO), | ||
341 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE, | ||
342 | }, | ||
343 | }; | ||
344 | |||
345 | static struct dm9000_plat_data zeus_dm9k_platdata = { | ||
346 | .flags = DM9000_PLATF_16BITONLY, | ||
347 | }; | ||
348 | |||
349 | static struct platform_device zeus_dm9k0_device = { | ||
350 | .name = "dm9000", | ||
351 | .id = 0, | ||
352 | .num_resources = ARRAY_SIZE(zeus_dm9k0_resource), | ||
353 | .resource = zeus_dm9k0_resource, | ||
354 | .dev = { | ||
355 | .platform_data = &zeus_dm9k_platdata, | ||
356 | } | ||
357 | }; | ||
358 | |||
359 | static struct platform_device zeus_dm9k1_device = { | ||
360 | .name = "dm9000", | ||
361 | .id = 1, | ||
362 | .num_resources = ARRAY_SIZE(zeus_dm9k1_resource), | ||
363 | .resource = zeus_dm9k1_resource, | ||
364 | .dev = { | ||
365 | .platform_data = &zeus_dm9k_platdata, | ||
366 | } | ||
367 | }; | ||
368 | |||
369 | /* External SRAM */ | ||
370 | static struct resource zeus_sram_resource = { | ||
371 | .start = ZEUS_SRAM_PHYS, | ||
372 | .end = ZEUS_SRAM_PHYS + ZEUS_SRAM_SIZE * 2 - 1, | ||
373 | .flags = IORESOURCE_MEM, | ||
374 | }; | ||
375 | |||
376 | static struct platform_device zeus_sram_device = { | ||
377 | .name = "pxa2xx-8bit-sram", | ||
378 | .id = 0, | ||
379 | .num_resources = 1, | ||
380 | .resource = &zeus_sram_resource, | ||
381 | }; | ||
382 | |||
383 | /* SPI interface on SSP3 */ | ||
384 | static struct pxa2xx_spi_master pxa2xx_spi_ssp3_master_info = { | ||
385 | .num_chipselect = 1, | ||
386 | .enable_dma = 1, | ||
387 | }; | ||
388 | |||
389 | static struct platform_device pxa2xx_spi_ssp3_device = { | ||
390 | .name = "pxa2xx-spi", | ||
391 | .id = 3, | ||
392 | .dev = { | ||
393 | .platform_data = &pxa2xx_spi_ssp3_master_info, | ||
394 | }, | ||
395 | }; | ||
396 | |||
397 | /* Leds */ | ||
398 | static struct gpio_led zeus_leds[] = { | ||
399 | [0] = { | ||
400 | .name = "zeus:yellow:1", | ||
401 | .default_trigger = "heartbeat", | ||
402 | .gpio = ZEUS_EXT0_GPIO(3), | ||
403 | .active_low = 1, | ||
404 | }, | ||
405 | [1] = { | ||
406 | .name = "zeus:yellow:2", | ||
407 | .default_trigger = "default-on", | ||
408 | .gpio = ZEUS_EXT0_GPIO(4), | ||
409 | .active_low = 1, | ||
410 | }, | ||
411 | [2] = { | ||
412 | .name = "zeus:yellow:3", | ||
413 | .default_trigger = "default-on", | ||
414 | .gpio = ZEUS_EXT0_GPIO(5), | ||
415 | .active_low = 1, | ||
416 | }, | ||
417 | }; | ||
418 | |||
419 | static struct gpio_led_platform_data zeus_leds_info = { | ||
420 | .leds = zeus_leds, | ||
421 | .num_leds = ARRAY_SIZE(zeus_leds), | ||
422 | }; | ||
423 | |||
424 | static struct platform_device zeus_leds_device = { | ||
425 | .name = "leds-gpio", | ||
426 | .id = -1, | ||
427 | .dev = { | ||
428 | .platform_data = &zeus_leds_info, | ||
429 | }, | ||
430 | }; | ||
431 | |||
432 | static void zeus_cf_reset(int state) | ||
433 | { | ||
434 | u16 cpld_state = __raw_readw(ZEUS_CPLD_CONTROL); | ||
435 | |||
436 | if (state) | ||
437 | cpld_state |= ZEUS_CPLD_CONTROL_CF_RST; | ||
438 | else | ||
439 | cpld_state &= ~ZEUS_CPLD_CONTROL_CF_RST; | ||
440 | |||
441 | __raw_writew(cpld_state, ZEUS_CPLD_CONTROL); | ||
442 | } | ||
443 | |||
444 | static struct arcom_pcmcia_pdata zeus_pcmcia_info = { | ||
445 | .cd_gpio = ZEUS_CF_CD_GPIO, | ||
446 | .rdy_gpio = ZEUS_CF_RDY_GPIO, | ||
447 | .pwr_gpio = ZEUS_CF_PWEN_GPIO, | ||
448 | .reset = zeus_cf_reset, | ||
449 | }; | ||
450 | |||
451 | static struct platform_device zeus_pcmcia_device = { | ||
452 | .name = "zeus-pcmcia", | ||
453 | .id = -1, | ||
454 | .dev = { | ||
455 | .platform_data = &zeus_pcmcia_info, | ||
456 | }, | ||
457 | }; | ||
458 | |||
459 | static struct platform_device *zeus_devices[] __initdata = { | ||
460 | &zeus_serial_device, | ||
461 | &zeus_mtd_devices[0], | ||
462 | &zeus_dm9k0_device, | ||
463 | &zeus_dm9k1_device, | ||
464 | &zeus_sram_device, | ||
465 | &pxa2xx_spi_ssp3_device, | ||
466 | &zeus_leds_device, | ||
467 | &zeus_pcmcia_device, | ||
468 | }; | ||
469 | |||
470 | /* AC'97 */ | ||
471 | static pxa2xx_audio_ops_t zeus_ac97_info = { | ||
472 | .reset_gpio = 95, | ||
473 | }; | ||
474 | |||
475 | |||
476 | /* | ||
477 | * USB host | ||
478 | */ | ||
479 | |||
480 | static int zeus_ohci_init(struct device *dev) | ||
481 | { | ||
482 | int err; | ||
483 | |||
484 | /* Switch on port 2. */ | ||
485 | if ((err = gpio_request(ZEUS_USB2_PWREN_GPIO, "USB2_PWREN"))) { | ||
486 | dev_err(dev, "Can't request USB2_PWREN\n"); | ||
487 | return err; | ||
488 | } | ||
489 | |||
490 | if ((err = gpio_direction_output(ZEUS_USB2_PWREN_GPIO, 1))) { | ||
491 | gpio_free(ZEUS_USB2_PWREN_GPIO); | ||
492 | dev_err(dev, "Can't enable USB2_PWREN\n"); | ||
493 | return err; | ||
494 | } | ||
495 | |||
496 | /* Port 2 is shared between host and client interface. */ | ||
497 | UP2OCR = UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE; | ||
498 | |||
499 | return 0; | ||
500 | } | ||
501 | |||
502 | static void zeus_ohci_exit(struct device *dev) | ||
503 | { | ||
504 | /* Power-off port 2 */ | ||
505 | gpio_direction_output(ZEUS_USB2_PWREN_GPIO, 0); | ||
506 | gpio_free(ZEUS_USB2_PWREN_GPIO); | ||
507 | } | ||
508 | |||
509 | static struct pxaohci_platform_data zeus_ohci_platform_data = { | ||
510 | .port_mode = PMM_NPS_MODE, | ||
511 | .flags = ENABLE_PORT_ALL | POWER_CONTROL_LOW | POWER_SENSE_LOW, | ||
512 | .init = zeus_ohci_init, | ||
513 | .exit = zeus_ohci_exit, | ||
514 | }; | ||
515 | |||
516 | /* | ||
517 | * Flat Panel | ||
518 | */ | ||
519 | |||
520 | static void zeus_lcd_power(int on, struct fb_var_screeninfo *si) | ||
521 | { | ||
522 | gpio_set_value(ZEUS_LCD_EN_GPIO, on); | ||
523 | } | ||
524 | |||
525 | static void zeus_backlight_power(int on) | ||
526 | { | ||
527 | gpio_set_value(ZEUS_BKLEN_GPIO, on); | ||
528 | } | ||
529 | |||
530 | static int zeus_setup_fb_gpios(void) | ||
531 | { | ||
532 | int err; | ||
533 | |||
534 | if ((err = gpio_request(ZEUS_LCD_EN_GPIO, "LCD_EN"))) | ||
535 | goto out_err; | ||
536 | |||
537 | if ((err = gpio_direction_output(ZEUS_LCD_EN_GPIO, 0))) | ||
538 | goto out_err_lcd; | ||
539 | |||
540 | if ((err = gpio_request(ZEUS_BKLEN_GPIO, "BKLEN"))) | ||
541 | goto out_err_lcd; | ||
542 | |||
543 | if ((err = gpio_direction_output(ZEUS_BKLEN_GPIO, 0))) | ||
544 | goto out_err_bkl; | ||
545 | |||
546 | return 0; | ||
547 | |||
548 | out_err_bkl: | ||
549 | gpio_free(ZEUS_BKLEN_GPIO); | ||
550 | out_err_lcd: | ||
551 | gpio_free(ZEUS_LCD_EN_GPIO); | ||
552 | out_err: | ||
553 | return err; | ||
554 | } | ||
555 | |||
556 | static struct pxafb_mode_info zeus_fb_mode_info[] = { | ||
557 | { | ||
558 | .pixclock = 39722, | ||
559 | |||
560 | .xres = 640, | ||
561 | .yres = 480, | ||
562 | |||
563 | .bpp = 16, | ||
564 | |||
565 | .hsync_len = 63, | ||
566 | .left_margin = 16, | ||
567 | .right_margin = 81, | ||
568 | |||
569 | .vsync_len = 2, | ||
570 | .upper_margin = 12, | ||
571 | .lower_margin = 31, | ||
572 | |||
573 | .sync = 0, | ||
574 | }, | ||
575 | }; | ||
576 | |||
577 | static struct pxafb_mach_info zeus_fb_info = { | ||
578 | .modes = zeus_fb_mode_info, | ||
579 | .num_modes = 1, | ||
580 | .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL, | ||
581 | .pxafb_lcd_power = zeus_lcd_power, | ||
582 | .pxafb_backlight_power = zeus_backlight_power, | ||
583 | }; | ||
584 | |||
585 | /* | ||
586 | * MMC/SD Device | ||
587 | * | ||
588 | * The card detect interrupt isn't debounced so we delay it by 250ms | ||
589 | * to give the card a chance to fully insert/eject. | ||
590 | */ | ||
591 | |||
592 | static struct pxamci_platform_data zeus_mci_platform_data = { | ||
593 | .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, | ||
594 | .detect_delay = HZ/4, | ||
595 | .gpio_card_detect = ZEUS_MMC_CD_GPIO, | ||
596 | .gpio_card_ro = ZEUS_MMC_WP_GPIO, | ||
597 | .gpio_card_ro_invert = 1, | ||
598 | .gpio_power = -1 | ||
599 | }; | ||
600 | |||
601 | /* | ||
602 | * USB Device Controller | ||
603 | */ | ||
604 | static void zeus_udc_command(int cmd) | ||
605 | { | ||
606 | switch (cmd) { | ||
607 | case PXA2XX_UDC_CMD_DISCONNECT: | ||
608 | pr_info("zeus: disconnecting USB client\n"); | ||
609 | UP2OCR = UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE; | ||
610 | break; | ||
611 | |||
612 | case PXA2XX_UDC_CMD_CONNECT: | ||
613 | pr_info("zeus: connecting USB client\n"); | ||
614 | UP2OCR = UP2OCR_HXOE | UP2OCR_DPPUE; | ||
615 | break; | ||
616 | } | ||
617 | } | ||
618 | |||
619 | static struct pxa2xx_udc_mach_info zeus_udc_info = { | ||
620 | .udc_command = zeus_udc_command, | ||
621 | }; | ||
622 | |||
623 | static void zeus_power_off(void) | ||
624 | { | ||
625 | local_irq_disable(); | ||
626 | pxa27x_cpu_suspend(PWRMODE_DEEPSLEEP); | ||
627 | } | ||
628 | |||
629 | int zeus_get_pcb_info(struct i2c_client *client, unsigned gpio, | ||
630 | unsigned ngpio, void *context) | ||
631 | { | ||
632 | int i; | ||
633 | u8 pcb_info = 0; | ||
634 | |||
635 | for (i = 0; i < 8; i++) { | ||
636 | int pcb_bit = gpio + i + 8; | ||
637 | |||
638 | if (gpio_request(pcb_bit, "pcb info")) { | ||
639 | dev_err(&client->dev, "Can't request pcb info %d\n", i); | ||
640 | continue; | ||
641 | } | ||
642 | |||
643 | if (gpio_direction_input(pcb_bit)) { | ||
644 | dev_err(&client->dev, "Can't read pcb info %d\n", i); | ||
645 | gpio_free(pcb_bit); | ||
646 | continue; | ||
647 | } | ||
648 | |||
649 | pcb_info |= !!gpio_get_value(pcb_bit) << i; | ||
650 | |||
651 | gpio_free(pcb_bit); | ||
652 | } | ||
653 | |||
654 | dev_info(&client->dev, "Zeus PCB version %d issue %d\n", | ||
655 | pcb_info >> 4, pcb_info & 0xf); | ||
656 | |||
657 | return 0; | ||
658 | } | ||
659 | |||
660 | static struct pca953x_platform_data zeus_pca953x_pdata[] = { | ||
661 | [0] = { .gpio_base = ZEUS_EXT0_GPIO_BASE, }, | ||
662 | [1] = { | ||
663 | .gpio_base = ZEUS_EXT1_GPIO_BASE, | ||
664 | .setup = zeus_get_pcb_info, | ||
665 | }, | ||
666 | [2] = { .gpio_base = ZEUS_USER_GPIO_BASE, }, | ||
667 | }; | ||
668 | |||
669 | static struct i2c_board_info __initdata zeus_i2c_devices[] = { | ||
670 | { | ||
671 | I2C_BOARD_INFO("pca9535", 0x21), | ||
672 | .platform_data = &zeus_pca953x_pdata[0], | ||
673 | }, | ||
674 | { | ||
675 | I2C_BOARD_INFO("pca9535", 0x22), | ||
676 | .platform_data = &zeus_pca953x_pdata[1], | ||
677 | }, | ||
678 | { | ||
679 | I2C_BOARD_INFO("pca9535", 0x20), | ||
680 | .platform_data = &zeus_pca953x_pdata[2], | ||
681 | .irq = gpio_to_irq(ZEUS_EXTGPIO_GPIO), | ||
682 | }, | ||
683 | { I2C_BOARD_INFO("lm75a", 0x48) }, | ||
684 | { I2C_BOARD_INFO("24c01", 0x50) }, | ||
685 | { I2C_BOARD_INFO("isl1208", 0x6f) }, | ||
686 | }; | ||
687 | |||
688 | static mfp_cfg_t zeus_pin_config[] __initdata = { | ||
689 | GPIO15_nCS_1, | ||
690 | GPIO78_nCS_2, | ||
691 | GPIO80_nCS_4, | ||
692 | GPIO33_nCS_5, | ||
693 | |||
694 | GPIO22_GPIO, | ||
695 | GPIO32_MMC_CLK, | ||
696 | GPIO92_MMC_DAT_0, | ||
697 | GPIO109_MMC_DAT_1, | ||
698 | GPIO110_MMC_DAT_2, | ||
699 | GPIO111_MMC_DAT_3, | ||
700 | GPIO112_MMC_CMD, | ||
701 | |||
702 | GPIO88_USBH1_PWR, | ||
703 | GPIO89_USBH1_PEN, | ||
704 | GPIO119_USBH2_PWR, | ||
705 | GPIO120_USBH2_PEN, | ||
706 | |||
707 | GPIO86_LCD_LDD_16, | ||
708 | GPIO87_LCD_LDD_17, | ||
709 | |||
710 | GPIO102_GPIO, | ||
711 | GPIO104_CIF_DD_2, | ||
712 | GPIO105_CIF_DD_1, | ||
713 | |||
714 | GPIO48_nPOE, | ||
715 | GPIO49_nPWE, | ||
716 | GPIO50_nPIOR, | ||
717 | GPIO51_nPIOW, | ||
718 | GPIO85_nPCE_1, | ||
719 | GPIO54_nPCE_2, | ||
720 | GPIO79_PSKTSEL, | ||
721 | GPIO55_nPREG, | ||
722 | GPIO56_nPWAIT, | ||
723 | GPIO57_nIOIS16, | ||
724 | GPIO36_GPIO, /* CF CD */ | ||
725 | GPIO97_GPIO, /* CF PWREN */ | ||
726 | GPIO99_GPIO, /* CF RDY */ | ||
727 | }; | ||
728 | |||
729 | static void __init zeus_init(void) | ||
730 | { | ||
731 | u16 dm9000_msc = 0xe279; | ||
732 | |||
733 | system_rev = __raw_readw(ZEUS_CPLD_VERSION); | ||
734 | pr_info("Zeus CPLD V%dI%d\n", (system_rev & 0xf0) >> 4, (system_rev & 0x0f)); | ||
735 | |||
736 | /* Fix timings for dm9000s (CS1/CS2)*/ | ||
737 | MSC0 = (MSC0 & 0xffff) | (dm9000_msc << 16); | ||
738 | MSC1 = (MSC1 & 0xffff0000) | dm9000_msc; | ||
739 | |||
740 | pm_power_off = zeus_power_off; | ||
741 | |||
742 | pxa2xx_mfp_config(ARRAY_AND_SIZE(zeus_pin_config)); | ||
743 | |||
744 | platform_add_devices(zeus_devices, ARRAY_SIZE(zeus_devices)); | ||
745 | |||
746 | pxa_set_ohci_info(&zeus_ohci_platform_data); | ||
747 | |||
748 | if (zeus_setup_fb_gpios()) | ||
749 | pr_err("Failed to setup fb gpios\n"); | ||
750 | else | ||
751 | set_pxa_fb_info(&zeus_fb_info); | ||
752 | |||
753 | pxa_set_mci_info(&zeus_mci_platform_data); | ||
754 | pxa_set_udc_info(&zeus_udc_info); | ||
755 | pxa_set_ac97_info(&zeus_ac97_info); | ||
756 | pxa_set_i2c_info(NULL); | ||
757 | i2c_register_board_info(0, ARRAY_AND_SIZE(zeus_i2c_devices)); | ||
758 | } | ||
759 | |||
760 | static struct map_desc zeus_io_desc[] __initdata = { | ||
761 | { | ||
762 | .virtual = ZEUS_CPLD_VERSION, | ||
763 | .pfn = __phys_to_pfn(ZEUS_CPLD_VERSION_PHYS), | ||
764 | .length = 0x1000, | ||
765 | .type = MT_DEVICE, | ||
766 | }, | ||
767 | { | ||
768 | .virtual = ZEUS_CPLD_ISA_IRQ, | ||
769 | .pfn = __phys_to_pfn(ZEUS_CPLD_ISA_IRQ_PHYS), | ||
770 | .length = 0x1000, | ||
771 | .type = MT_DEVICE, | ||
772 | }, | ||
773 | { | ||
774 | .virtual = ZEUS_CPLD_CONTROL, | ||
775 | .pfn = __phys_to_pfn(ZEUS_CPLD_CONTROL_PHYS), | ||
776 | .length = 0x1000, | ||
777 | .type = MT_DEVICE, | ||
778 | }, | ||
779 | { | ||
780 | .virtual = ZEUS_CPLD_EXTWDOG, | ||
781 | .pfn = __phys_to_pfn(ZEUS_CPLD_EXTWDOG_PHYS), | ||
782 | .length = 0x1000, | ||
783 | .type = MT_DEVICE, | ||
784 | }, | ||
785 | { | ||
786 | .virtual = ZEUS_PC104IO, | ||
787 | .pfn = __phys_to_pfn(ZEUS_PC104IO_PHYS), | ||
788 | .length = 0x00800000, | ||
789 | .type = MT_DEVICE, | ||
790 | }, | ||
791 | }; | ||
792 | |||
793 | static void __init zeus_map_io(void) | ||
794 | { | ||
795 | pxa_map_io(); | ||
796 | |||
797 | iotable_init(zeus_io_desc, ARRAY_SIZE(zeus_io_desc)); | ||
798 | |||
799 | /* Clear PSPR to ensure a full restart on wake-up. */ | ||
800 | PMCR = PSPR = 0; | ||
801 | |||
802 | /* enable internal 32.768Khz oscillator (ignore OSCC_OOK) */ | ||
803 | OSCC |= OSCC_OON; | ||
804 | |||
805 | /* Some clock cycles later (from OSCC_ON), programme PCFR (OPDE...). | ||
806 | * float chip selects and PCMCIA */ | ||
807 | PCFR = PCFR_OPDE | PCFR_DC_EN | PCFR_FS | PCFR_FP; | ||
808 | } | ||
809 | |||
810 | MACHINE_START(ARCOM_ZEUS, "Arcom ZEUS") | ||
811 | /* Maintainer: Marc Zyngier <maz@misterjones.org> */ | ||
812 | .phys_io = 0x40000000, | ||
813 | .io_pg_offst = ((io_p2v(0x40000000) >> 18) & 0xfffc), | ||
814 | .boot_params = 0xa0000100, | ||
815 | .map_io = zeus_map_io, | ||
816 | .init_irq = zeus_init_irq, | ||
817 | .timer = &pxa_timer, | ||
818 | .init_machine = zeus_init, | ||
819 | MACHINE_END | ||
820 | |||
diff --git a/arch/arm/mach-realview/Kconfig b/arch/arm/mach-realview/Kconfig index c48e1f2c3349..ee5e392430e8 100644 --- a/arch/arm/mach-realview/Kconfig +++ b/arch/arm/mach-realview/Kconfig | |||
@@ -70,7 +70,7 @@ config MACH_REALVIEW_PBX | |||
70 | bool "Support RealView/PBX platform" | 70 | bool "Support RealView/PBX platform" |
71 | select ARM_GIC | 71 | select ARM_GIC |
72 | select HAVE_PATA_PLATFORM | 72 | select HAVE_PATA_PLATFORM |
73 | select ARCH_SPARSEMEM_ENABLE if CPU_V7 && !HIGH_PHYS_OFFSET | 73 | select ARCH_SPARSEMEM_ENABLE if CPU_V7 && !REALVIEW_HIGH_PHYS_OFFSET |
74 | select ZONE_DMA if SPARSEMEM | 74 | select ZONE_DMA if SPARSEMEM |
75 | help | 75 | help |
76 | Include support for the ARM(R) RealView PBX platform. | 76 | Include support for the ARM(R) RealView PBX platform. |
diff --git a/arch/arm/mach-s3c2442/mach-gta02.c b/arch/arm/mach-s3c2442/mach-gta02.c index f76d6ff4aeb9..0b4a3a03071f 100644 --- a/arch/arm/mach-s3c2442/mach-gta02.c +++ b/arch/arm/mach-s3c2442/mach-gta02.c | |||
@@ -268,6 +268,9 @@ struct pcf50633_platform_data gta02_pcf_pdata = { | |||
268 | 268 | ||
269 | .batteries = gta02_batteries, | 269 | .batteries = gta02_batteries, |
270 | .num_batteries = ARRAY_SIZE(gta02_batteries), | 270 | .num_batteries = ARRAY_SIZE(gta02_batteries), |
271 | |||
272 | .charger_reference_current_ma = 1000, | ||
273 | |||
271 | .reg_init_data = { | 274 | .reg_init_data = { |
272 | [PCF50633_REGULATOR_AUTO] = { | 275 | [PCF50633_REGULATOR_AUTO] = { |
273 | .constraints = { | 276 | .constraints = { |
diff --git a/arch/arm/mach-s3c24a0/include/mach/memory.h b/arch/arm/mach-s3c24a0/include/mach/memory.h index 585211ca0187..7d74fd5c8d66 100644 --- a/arch/arm/mach-s3c24a0/include/mach/memory.h +++ b/arch/arm/mach-s3c24a0/include/mach/memory.h | |||
@@ -15,5 +15,7 @@ | |||
15 | 15 | ||
16 | #define __virt_to_bus(x) __virt_to_phys(x) | 16 | #define __virt_to_bus(x) __virt_to_phys(x) |
17 | #define __bus_to_virt(x) __phys_to_virt(x) | 17 | #define __bus_to_virt(x) __phys_to_virt(x) |
18 | #define __pfn_to_bus(x) __pfn_to_phys(x) | ||
19 | #define __bus_to_pfn(x) __phys_to_pfn(x) | ||
18 | 20 | ||
19 | #endif | 21 | #endif |
diff --git a/arch/arm/mach-sa1100/Kconfig b/arch/arm/mach-sa1100/Kconfig index 03a7f3857c5e..b17d52f7cc48 100644 --- a/arch/arm/mach-sa1100/Kconfig +++ b/arch/arm/mach-sa1100/Kconfig | |||
@@ -4,6 +4,7 @@ menu "SA11x0 Implementations" | |||
4 | 4 | ||
5 | config SA1100_ASSABET | 5 | config SA1100_ASSABET |
6 | bool "Assabet" | 6 | bool "Assabet" |
7 | select CPU_FREQ_SA1110 | ||
7 | help | 8 | help |
8 | Say Y here if you are using the Intel(R) StrongARM(R) SA-1110 | 9 | Say Y here if you are using the Intel(R) StrongARM(R) SA-1110 |
9 | Microprocessor Development Board (also known as the Assabet). | 10 | Microprocessor Development Board (also known as the Assabet). |
@@ -19,6 +20,7 @@ config ASSABET_NEPONSET | |||
19 | 20 | ||
20 | config SA1100_CERF | 21 | config SA1100_CERF |
21 | bool "CerfBoard" | 22 | bool "CerfBoard" |
23 | select CPU_FREQ_SA1110 | ||
22 | help | 24 | help |
23 | The Intrinsyc CerfBoard is based on the StrongARM 1110 (Discontinued). | 25 | The Intrinsyc CerfBoard is based on the StrongARM 1110 (Discontinued). |
24 | More information is available at: | 26 | More information is available at: |
@@ -45,6 +47,7 @@ endchoice | |||
45 | 47 | ||
46 | config SA1100_COLLIE | 48 | config SA1100_COLLIE |
47 | bool "Sharp Zaurus SL5500" | 49 | bool "Sharp Zaurus SL5500" |
50 | # FIXME: select CPU_FREQ_SA11x0 | ||
48 | select SHARP_LOCOMO | 51 | select SHARP_LOCOMO |
49 | select SHARP_SCOOP | 52 | select SHARP_SCOOP |
50 | select SHARP_PARAM | 53 | select SHARP_PARAM |
@@ -54,6 +57,7 @@ config SA1100_COLLIE | |||
54 | config SA1100_H3100 | 57 | config SA1100_H3100 |
55 | bool "Compaq iPAQ H3100" | 58 | bool "Compaq iPAQ H3100" |
56 | select HTC_EGPIO | 59 | select HTC_EGPIO |
60 | select CPU_FREQ_SA1100 | ||
57 | help | 61 | help |
58 | Say Y here if you intend to run this kernel on the Compaq iPAQ | 62 | Say Y here if you intend to run this kernel on the Compaq iPAQ |
59 | H3100 handheld computer. Information about this machine and the | 63 | H3100 handheld computer. Information about this machine and the |
@@ -64,6 +68,7 @@ config SA1100_H3100 | |||
64 | config SA1100_H3600 | 68 | config SA1100_H3600 |
65 | bool "Compaq iPAQ H3600/H3700" | 69 | bool "Compaq iPAQ H3600/H3700" |
66 | select HTC_EGPIO | 70 | select HTC_EGPIO |
71 | select CPU_FREQ_SA1100 | ||
67 | help | 72 | help |
68 | Say Y here if you intend to run this kernel on the Compaq iPAQ | 73 | Say Y here if you intend to run this kernel on the Compaq iPAQ |
69 | H3600 handheld computer. Information about this machine and the | 74 | H3600 handheld computer. Information about this machine and the |
@@ -74,6 +79,7 @@ config SA1100_H3600 | |||
74 | config SA1100_BADGE4 | 79 | config SA1100_BADGE4 |
75 | bool "HP Labs BadgePAD 4" | 80 | bool "HP Labs BadgePAD 4" |
76 | select SA1111 | 81 | select SA1111 |
82 | select CPU_FREQ_SA1100 | ||
77 | help | 83 | help |
78 | Say Y here if you want to build a kernel for the HP Laboratories | 84 | Say Y here if you want to build a kernel for the HP Laboratories |
79 | BadgePAD 4. | 85 | BadgePAD 4. |
@@ -81,6 +87,7 @@ config SA1100_BADGE4 | |||
81 | config SA1100_JORNADA720 | 87 | config SA1100_JORNADA720 |
82 | bool "HP Jornada 720" | 88 | bool "HP Jornada 720" |
83 | select SA1111 | 89 | select SA1111 |
90 | # FIXME: select CPU_FREQ_SA11x0 | ||
84 | help | 91 | help |
85 | Say Y here if you want to build a kernel for the HP Jornada 720 | 92 | Say Y here if you want to build a kernel for the HP Jornada 720 |
86 | handheld computer. See <http://www.hp.com/jornada/products/720> | 93 | handheld computer. See <http://www.hp.com/jornada/products/720> |
@@ -98,12 +105,14 @@ config SA1100_JORNADA720_SSP | |||
98 | 105 | ||
99 | config SA1100_HACKKIT | 106 | config SA1100_HACKKIT |
100 | bool "HackKit Core CPU Board" | 107 | bool "HackKit Core CPU Board" |
108 | select CPU_FREQ_SA1100 | ||
101 | help | 109 | help |
102 | Say Y here to support the HackKit Core CPU Board | 110 | Say Y here to support the HackKit Core CPU Board |
103 | <http://hackkit.eletztrick.de>; | 111 | <http://hackkit.eletztrick.de>; |
104 | 112 | ||
105 | config SA1100_LART | 113 | config SA1100_LART |
106 | bool "LART" | 114 | bool "LART" |
115 | select CPU_FREQ_SA1100 | ||
107 | help | 116 | help |
108 | Say Y here if you are using the Linux Advanced Radio Terminal | 117 | Say Y here if you are using the Linux Advanced Radio Terminal |
109 | (also known as the LART). See <http://www.lartmaker.nl/> for | 118 | (also known as the LART). See <http://www.lartmaker.nl/> for |
@@ -111,6 +120,7 @@ config SA1100_LART | |||
111 | 120 | ||
112 | config SA1100_PLEB | 121 | config SA1100_PLEB |
113 | bool "PLEB" | 122 | bool "PLEB" |
123 | select CPU_FREQ_SA1100 | ||
114 | help | 124 | help |
115 | Say Y here if you are using version 1 of the Portable Linux | 125 | Say Y here if you are using version 1 of the Portable Linux |
116 | Embedded Board (also known as PLEB). | 126 | Embedded Board (also known as PLEB). |
@@ -119,6 +129,7 @@ config SA1100_PLEB | |||
119 | 129 | ||
120 | config SA1100_SHANNON | 130 | config SA1100_SHANNON |
121 | bool "Shannon" | 131 | bool "Shannon" |
132 | select CPU_FREQ_SA1100 | ||
122 | help | 133 | help |
123 | The Shannon (also known as a Tuxscreen, and also as a IS2630) was a | 134 | The Shannon (also known as a Tuxscreen, and also as a IS2630) was a |
124 | limited edition webphone produced by Philips. The Shannon is a SA1100 | 135 | limited edition webphone produced by Philips. The Shannon is a SA1100 |
@@ -127,6 +138,7 @@ config SA1100_SHANNON | |||
127 | 138 | ||
128 | config SA1100_SIMPAD | 139 | config SA1100_SIMPAD |
129 | bool "Simpad" | 140 | bool "Simpad" |
141 | select CPU_FREQ_SA1110 | ||
130 | help | 142 | help |
131 | The SIEMENS webpad SIMpad is based on the StrongARM 1110. There | 143 | The SIEMENS webpad SIMpad is based on the StrongARM 1110. There |
132 | are two different versions CL4 and SL4. CL4 has 32MB RAM and 16MB | 144 | are two different versions CL4 and SL4. CL4 has 32MB RAM and 16MB |
@@ -145,3 +157,4 @@ config SA1100_SSP | |||
145 | endmenu | 157 | endmenu |
146 | 158 | ||
147 | endif | 159 | endif |
160 | |||
diff --git a/arch/arm/mach-sa1100/generic.c b/arch/arm/mach-sa1100/generic.c index 9faea1511c1f..3c1fcd696714 100644 --- a/arch/arm/mach-sa1100/generic.c +++ b/arch/arm/mach-sa1100/generic.c | |||
@@ -58,7 +58,6 @@ static const unsigned short cclk_frequency_100khz[NR_FREQS] = { | |||
58 | 2802 /* 280.2 MHz */ | 58 | 2802 /* 280.2 MHz */ |
59 | }; | 59 | }; |
60 | 60 | ||
61 | #if defined(CONFIG_CPU_FREQ_SA1100) || defined(CONFIG_CPU_FREQ_SA1110) | ||
62 | /* rounds up(!) */ | 61 | /* rounds up(!) */ |
63 | unsigned int sa11x0_freq_to_ppcr(unsigned int khz) | 62 | unsigned int sa11x0_freq_to_ppcr(unsigned int khz) |
64 | { | 63 | { |
@@ -110,17 +109,6 @@ unsigned int sa11x0_getspeed(unsigned int cpu) | |||
110 | return cclk_frequency_100khz[PPCR & 0xf] * 100; | 109 | return cclk_frequency_100khz[PPCR & 0xf] * 100; |
111 | } | 110 | } |
112 | 111 | ||
113 | #else | ||
114 | /* | ||
115 | * We still need to provide this so building without cpufreq works. | ||
116 | */ | ||
117 | unsigned int cpufreq_get(unsigned int cpu) | ||
118 | { | ||
119 | return cclk_frequency_100khz[PPCR & 0xf] * 100; | ||
120 | } | ||
121 | EXPORT_SYMBOL(cpufreq_get); | ||
122 | #endif | ||
123 | |||
124 | /* | 112 | /* |
125 | * This is the SA11x0 sched_clock implementation. This has | 113 | * This is the SA11x0 sched_clock implementation. This has |
126 | * a resolution of 271ns, and a maximum value of 32025597s (370 days). | 114 | * a resolution of 271ns, and a maximum value of 32025597s (370 days). |
diff --git a/arch/arm/mach-u300/include/mach/coh901318.h b/arch/arm/mach-u300/include/mach/coh901318.h new file mode 100644 index 000000000000..f4cfee9c7d28 --- /dev/null +++ b/arch/arm/mach-u300/include/mach/coh901318.h | |||
@@ -0,0 +1,281 @@ | |||
1 | /* | ||
2 | * | ||
3 | * include/linux/coh901318.h | ||
4 | * | ||
5 | * | ||
6 | * Copyright (C) 2007-2009 ST-Ericsson | ||
7 | * License terms: GNU General Public License (GPL) version 2 | ||
8 | * DMA driver for COH 901 318 | ||
9 | * Author: Per Friden <per.friden@stericsson.com> | ||
10 | */ | ||
11 | |||
12 | #ifndef COH901318_H | ||
13 | #define COH901318_H | ||
14 | |||
15 | #include <linux/device.h> | ||
16 | #include <linux/dmaengine.h> | ||
17 | |||
18 | #define MAX_DMA_PACKET_SIZE_SHIFT 11 | ||
19 | #define MAX_DMA_PACKET_SIZE (1 << MAX_DMA_PACKET_SIZE_SHIFT) | ||
20 | |||
21 | /** | ||
22 | * struct coh901318_lli - linked list item for DMAC | ||
23 | * @control: control settings for DMAC | ||
24 | * @src_addr: transfer source address | ||
25 | * @dst_addr: transfer destination address | ||
26 | * @link_addr: physical address to next lli | ||
27 | * @virt_link_addr: virtual addres of next lli (only used by pool_free) | ||
28 | * @phy_this: physical address of current lli (only used by pool_free) | ||
29 | */ | ||
30 | struct coh901318_lli { | ||
31 | u32 control; | ||
32 | dma_addr_t src_addr; | ||
33 | dma_addr_t dst_addr; | ||
34 | dma_addr_t link_addr; | ||
35 | |||
36 | void *virt_link_addr; | ||
37 | dma_addr_t phy_this; | ||
38 | }; | ||
39 | /** | ||
40 | * struct coh901318_params - parameters for DMAC configuration | ||
41 | * @config: DMA config register | ||
42 | * @ctrl_lli_last: DMA control register for the last lli in the list | ||
43 | * @ctrl_lli: DMA control register for an lli | ||
44 | * @ctrl_lli_chained: DMA control register for a chained lli | ||
45 | */ | ||
46 | struct coh901318_params { | ||
47 | u32 config; | ||
48 | u32 ctrl_lli_last; | ||
49 | u32 ctrl_lli; | ||
50 | u32 ctrl_lli_chained; | ||
51 | }; | ||
52 | /** | ||
53 | * struct coh_dma_channel - dma channel base | ||
54 | * @name: ascii name of dma channel | ||
55 | * @number: channel id number | ||
56 | * @desc_nbr_max: number of preallocated descriptortors | ||
57 | * @priority_high: prio of channel, 0 low otherwise high. | ||
58 | * @param: configuration parameters | ||
59 | * @dev_addr: physical address of periphal connected to channel | ||
60 | */ | ||
61 | struct coh_dma_channel { | ||
62 | const char name[32]; | ||
63 | const int number; | ||
64 | const int desc_nbr_max; | ||
65 | const int priority_high; | ||
66 | const struct coh901318_params param; | ||
67 | const dma_addr_t dev_addr; | ||
68 | }; | ||
69 | |||
70 | /** | ||
71 | * dma_access_memory_state_t - register dma for memory access | ||
72 | * | ||
73 | * @dev: The dma device | ||
74 | * @active: 1 means dma intends to access memory | ||
75 | * 0 means dma wont access memory | ||
76 | */ | ||
77 | typedef void (*dma_access_memory_state_t)(struct device *dev, | ||
78 | bool active); | ||
79 | |||
80 | /** | ||
81 | * struct powersave - DMA power save structure | ||
82 | * @lock: lock protecting data in this struct | ||
83 | * @started_channels: bit mask indicating active dma channels | ||
84 | */ | ||
85 | struct powersave { | ||
86 | spinlock_t lock; | ||
87 | u64 started_channels; | ||
88 | }; | ||
89 | /** | ||
90 | * struct coh901318_platform - platform arch structure | ||
91 | * @chans_slave: specifying dma slave channels | ||
92 | * @chans_memcpy: specifying dma memcpy channels | ||
93 | * @access_memory_state: requesting DMA memeory access (on / off) | ||
94 | * @chan_conf: dma channel configurations | ||
95 | * @max_channels: max number of dma chanenls | ||
96 | */ | ||
97 | struct coh901318_platform { | ||
98 | const int *chans_slave; | ||
99 | const int *chans_memcpy; | ||
100 | const dma_access_memory_state_t access_memory_state; | ||
101 | const struct coh_dma_channel *chan_conf; | ||
102 | const int max_channels; | ||
103 | }; | ||
104 | |||
105 | /** | ||
106 | * coh901318_get_bytes_left() - Get number of bytes left on a current transfer | ||
107 | * @chan: dma channel handle | ||
108 | * return number of bytes left, or negative on error | ||
109 | */ | ||
110 | u32 coh901318_get_bytes_left(struct dma_chan *chan); | ||
111 | |||
112 | /** | ||
113 | * coh901318_stop() - Stops dma transfer | ||
114 | * @chan: dma channel handle | ||
115 | * return 0 on success otherwise negative value | ||
116 | */ | ||
117 | void coh901318_stop(struct dma_chan *chan); | ||
118 | |||
119 | /** | ||
120 | * coh901318_continue() - Resumes a stopped dma transfer | ||
121 | * @chan: dma channel handle | ||
122 | * return 0 on success otherwise negative value | ||
123 | */ | ||
124 | void coh901318_continue(struct dma_chan *chan); | ||
125 | |||
126 | /** | ||
127 | * coh901318_filter_id() - DMA channel filter function | ||
128 | * @chan: dma channel handle | ||
129 | * @chan_id: id of dma channel to be filter out | ||
130 | * | ||
131 | * In dma_request_channel() it specifies what channel id to be requested | ||
132 | */ | ||
133 | bool coh901318_filter_id(struct dma_chan *chan, void *chan_id); | ||
134 | |||
135 | /* | ||
136 | * DMA Controller - this access the static mappings of the coh901318 dma. | ||
137 | * | ||
138 | */ | ||
139 | |||
140 | #define COH901318_MOD32_MASK (0x1F) | ||
141 | #define COH901318_WORD_MASK (0xFFFFFFFF) | ||
142 | /* INT_STATUS - Interrupt Status Registers 32bit (R/-) */ | ||
143 | #define COH901318_INT_STATUS1 (0x0000) | ||
144 | #define COH901318_INT_STATUS2 (0x0004) | ||
145 | /* TC_INT_STATUS - Terminal Count Interrupt Status Registers 32bit (R/-) */ | ||
146 | #define COH901318_TC_INT_STATUS1 (0x0008) | ||
147 | #define COH901318_TC_INT_STATUS2 (0x000C) | ||
148 | /* TC_INT_CLEAR - Terminal Count Interrupt Clear Registers 32bit (-/W) */ | ||
149 | #define COH901318_TC_INT_CLEAR1 (0x0010) | ||
150 | #define COH901318_TC_INT_CLEAR2 (0x0014) | ||
151 | /* RAW_TC_INT_STATUS - Raw Term Count Interrupt Status Registers 32bit (R/-) */ | ||
152 | #define COH901318_RAW_TC_INT_STATUS1 (0x0018) | ||
153 | #define COH901318_RAW_TC_INT_STATUS2 (0x001C) | ||
154 | /* BE_INT_STATUS - Bus Error Interrupt Status Registers 32bit (R/-) */ | ||
155 | #define COH901318_BE_INT_STATUS1 (0x0020) | ||
156 | #define COH901318_BE_INT_STATUS2 (0x0024) | ||
157 | /* BE_INT_CLEAR - Bus Error Interrupt Clear Registers 32bit (-/W) */ | ||
158 | #define COH901318_BE_INT_CLEAR1 (0x0028) | ||
159 | #define COH901318_BE_INT_CLEAR2 (0x002C) | ||
160 | /* RAW_BE_INT_STATUS - Raw Term Count Interrupt Status Registers 32bit (R/-) */ | ||
161 | #define COH901318_RAW_BE_INT_STATUS1 (0x0030) | ||
162 | #define COH901318_RAW_BE_INT_STATUS2 (0x0034) | ||
163 | |||
164 | /* | ||
165 | * CX_CFG - Channel Configuration Registers 32bit (R/W) | ||
166 | */ | ||
167 | #define COH901318_CX_CFG (0x0100) | ||
168 | #define COH901318_CX_CFG_SPACING (0x04) | ||
169 | /* Channel enable activates tha dma job */ | ||
170 | #define COH901318_CX_CFG_CH_ENABLE (0x00000001) | ||
171 | #define COH901318_CX_CFG_CH_DISABLE (0x00000000) | ||
172 | /* Request Mode */ | ||
173 | #define COH901318_CX_CFG_RM_MASK (0x00000006) | ||
174 | #define COH901318_CX_CFG_RM_MEMORY_TO_MEMORY (0x0 << 1) | ||
175 | #define COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY (0x1 << 1) | ||
176 | #define COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY (0x1 << 1) | ||
177 | #define COH901318_CX_CFG_RM_PRIMARY_TO_SECONDARY (0x3 << 1) | ||
178 | #define COH901318_CX_CFG_RM_SECONDARY_TO_PRIMARY (0x3 << 1) | ||
179 | /* Linked channel request field. RM must == 11 */ | ||
180 | #define COH901318_CX_CFG_LCRF_SHIFT 3 | ||
181 | #define COH901318_CX_CFG_LCRF_MASK (0x000001F8) | ||
182 | #define COH901318_CX_CFG_LCR_DISABLE (0x00000000) | ||
183 | /* Terminal Counter Interrupt Request Mask */ | ||
184 | #define COH901318_CX_CFG_TC_IRQ_ENABLE (0x00000200) | ||
185 | #define COH901318_CX_CFG_TC_IRQ_DISABLE (0x00000000) | ||
186 | /* Bus Error interrupt Mask */ | ||
187 | #define COH901318_CX_CFG_BE_IRQ_ENABLE (0x00000400) | ||
188 | #define COH901318_CX_CFG_BE_IRQ_DISABLE (0x00000000) | ||
189 | |||
190 | /* | ||
191 | * CX_STAT - Channel Status Registers 32bit (R/-) | ||
192 | */ | ||
193 | #define COH901318_CX_STAT (0x0200) | ||
194 | #define COH901318_CX_STAT_SPACING (0x04) | ||
195 | #define COH901318_CX_STAT_RBE_IRQ_IND (0x00000008) | ||
196 | #define COH901318_CX_STAT_RTC_IRQ_IND (0x00000004) | ||
197 | #define COH901318_CX_STAT_ACTIVE (0x00000002) | ||
198 | #define COH901318_CX_STAT_ENABLED (0x00000001) | ||
199 | |||
200 | /* | ||
201 | * CX_CTRL - Channel Control Registers 32bit (R/W) | ||
202 | */ | ||
203 | #define COH901318_CX_CTRL (0x0400) | ||
204 | #define COH901318_CX_CTRL_SPACING (0x10) | ||
205 | /* Transfer Count Enable */ | ||
206 | #define COH901318_CX_CTRL_TC_ENABLE (0x00001000) | ||
207 | #define COH901318_CX_CTRL_TC_DISABLE (0x00000000) | ||
208 | /* Transfer Count Value 0 - 4095 */ | ||
209 | #define COH901318_CX_CTRL_TC_VALUE_MASK (0x00000FFF) | ||
210 | /* Burst count */ | ||
211 | #define COH901318_CX_CTRL_BURST_COUNT_MASK (0x0000E000) | ||
212 | #define COH901318_CX_CTRL_BURST_COUNT_64_BYTES (0x7 << 13) | ||
213 | #define COH901318_CX_CTRL_BURST_COUNT_48_BYTES (0x6 << 13) | ||
214 | #define COH901318_CX_CTRL_BURST_COUNT_32_BYTES (0x5 << 13) | ||
215 | #define COH901318_CX_CTRL_BURST_COUNT_16_BYTES (0x4 << 13) | ||
216 | #define COH901318_CX_CTRL_BURST_COUNT_8_BYTES (0x3 << 13) | ||
217 | #define COH901318_CX_CTRL_BURST_COUNT_4_BYTES (0x2 << 13) | ||
218 | #define COH901318_CX_CTRL_BURST_COUNT_2_BYTES (0x1 << 13) | ||
219 | #define COH901318_CX_CTRL_BURST_COUNT_1_BYTE (0x0 << 13) | ||
220 | /* Source bus size */ | ||
221 | #define COH901318_CX_CTRL_SRC_BUS_SIZE_MASK (0x00030000) | ||
222 | #define COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS (0x2 << 16) | ||
223 | #define COH901318_CX_CTRL_SRC_BUS_SIZE_16_BITS (0x1 << 16) | ||
224 | #define COH901318_CX_CTRL_SRC_BUS_SIZE_8_BITS (0x0 << 16) | ||
225 | /* Source address increment */ | ||
226 | #define COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE (0x00040000) | ||
227 | #define COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE (0x00000000) | ||
228 | /* Destination Bus Size */ | ||
229 | #define COH901318_CX_CTRL_DST_BUS_SIZE_MASK (0x00180000) | ||
230 | #define COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS (0x2 << 19) | ||
231 | #define COH901318_CX_CTRL_DST_BUS_SIZE_16_BITS (0x1 << 19) | ||
232 | #define COH901318_CX_CTRL_DST_BUS_SIZE_8_BITS (0x0 << 19) | ||
233 | /* Destination address increment */ | ||
234 | #define COH901318_CX_CTRL_DST_ADDR_INC_ENABLE (0x00200000) | ||
235 | #define COH901318_CX_CTRL_DST_ADDR_INC_DISABLE (0x00000000) | ||
236 | /* Master Mode (Master2 is only connected to MSL) */ | ||
237 | #define COH901318_CX_CTRL_MASTER_MODE_MASK (0x00C00000) | ||
238 | #define COH901318_CX_CTRL_MASTER_MODE_M2R_M1W (0x3 << 22) | ||
239 | #define COH901318_CX_CTRL_MASTER_MODE_M1R_M2W (0x2 << 22) | ||
240 | #define COH901318_CX_CTRL_MASTER_MODE_M2RW (0x1 << 22) | ||
241 | #define COH901318_CX_CTRL_MASTER_MODE_M1RW (0x0 << 22) | ||
242 | /* Terminal Count flag to PER enable */ | ||
243 | #define COH901318_CX_CTRL_TCP_ENABLE (0x01000000) | ||
244 | #define COH901318_CX_CTRL_TCP_DISABLE (0x00000000) | ||
245 | /* Terminal Count flags to CPU enable */ | ||
246 | #define COH901318_CX_CTRL_TC_IRQ_ENABLE (0x02000000) | ||
247 | #define COH901318_CX_CTRL_TC_IRQ_DISABLE (0x00000000) | ||
248 | /* Hand shake to peripheral */ | ||
249 | #define COH901318_CX_CTRL_HSP_ENABLE (0x04000000) | ||
250 | #define COH901318_CX_CTRL_HSP_DISABLE (0x00000000) | ||
251 | #define COH901318_CX_CTRL_HSS_ENABLE (0x08000000) | ||
252 | #define COH901318_CX_CTRL_HSS_DISABLE (0x00000000) | ||
253 | /* DMA mode */ | ||
254 | #define COH901318_CX_CTRL_DDMA_MASK (0x30000000) | ||
255 | #define COH901318_CX_CTRL_DDMA_LEGACY (0x0 << 28) | ||
256 | #define COH901318_CX_CTRL_DDMA_DEMAND_DMA1 (0x1 << 28) | ||
257 | #define COH901318_CX_CTRL_DDMA_DEMAND_DMA2 (0x2 << 28) | ||
258 | /* Primary Request Data Destination */ | ||
259 | #define COH901318_CX_CTRL_PRDD_MASK (0x40000000) | ||
260 | #define COH901318_CX_CTRL_PRDD_DEST (0x1 << 30) | ||
261 | #define COH901318_CX_CTRL_PRDD_SOURCE (0x0 << 30) | ||
262 | |||
263 | /* | ||
264 | * CX_SRC_ADDR - Channel Source Address Registers 32bit (R/W) | ||
265 | */ | ||
266 | #define COH901318_CX_SRC_ADDR (0x0404) | ||
267 | #define COH901318_CX_SRC_ADDR_SPACING (0x10) | ||
268 | |||
269 | /* | ||
270 | * CX_DST_ADDR - Channel Destination Address Registers 32bit R/W | ||
271 | */ | ||
272 | #define COH901318_CX_DST_ADDR (0x0408) | ||
273 | #define COH901318_CX_DST_ADDR_SPACING (0x10) | ||
274 | |||
275 | /* | ||
276 | * CX_LNK_ADDR - Channel Link Address Registers 32bit (R/W) | ||
277 | */ | ||
278 | #define COH901318_CX_LNK_ADDR (0x040C) | ||
279 | #define COH901318_CX_LNK_ADDR_SPACING (0x10) | ||
280 | #define COH901318_CX_LNK_LINK_IMMEDIATE (0x00000001) | ||
281 | #endif /* COH901318_H */ | ||
diff --git a/arch/arm/mach-w90x900/include/mach/nuc900_spi.h b/arch/arm/mach-w90x900/include/mach/nuc900_spi.h new file mode 100644 index 000000000000..bd94819e314f --- /dev/null +++ b/arch/arm/mach-w90x900/include/mach/nuc900_spi.h | |||
@@ -0,0 +1,35 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-w90x900/include/mach/nuc900_spi.h | ||
3 | * | ||
4 | * Copyright (c) 2009 Nuvoton technology corporation. | ||
5 | * | ||
6 | * Wan ZongShun <mcuos.com@gmail.com> | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License as published by | ||
10 | * the Free Software Foundation;version 2 of the License. | ||
11 | * | ||
12 | */ | ||
13 | |||
14 | #ifndef __ASM_ARCH_SPI_H | ||
15 | #define __ASM_ARCH_SPI_H | ||
16 | |||
17 | extern void mfp_set_groupg(struct device *dev); | ||
18 | |||
19 | struct nuc900_spi_info { | ||
20 | unsigned int num_cs; | ||
21 | unsigned int lsb; | ||
22 | unsigned int txneg; | ||
23 | unsigned int rxneg; | ||
24 | unsigned int divider; | ||
25 | unsigned int sleep; | ||
26 | unsigned int txnum; | ||
27 | unsigned int txbitlen; | ||
28 | int bus_num; | ||
29 | }; | ||
30 | |||
31 | struct nuc900_spi_chip { | ||
32 | unsigned char bits_per_word; | ||
33 | }; | ||
34 | |||
35 | #endif /* __ASM_ARCH_SPI_H */ | ||
diff --git a/arch/arm/plat-mxc/include/mach/mxc_nand.h b/arch/arm/plat-mxc/include/mach/mxc_nand.h index 2b972df22d12..5d2d21d414e0 100644 --- a/arch/arm/plat-mxc/include/mach/mxc_nand.h +++ b/arch/arm/plat-mxc/include/mach/mxc_nand.h | |||
@@ -22,6 +22,7 @@ | |||
22 | 22 | ||
23 | struct mxc_nand_platform_data { | 23 | struct mxc_nand_platform_data { |
24 | int width; /* data bus width in bytes */ | 24 | int width; /* data bus width in bytes */ |
25 | int hw_ecc; /* 0 if supress hardware ECC */ | 25 | int hw_ecc:1; /* 0 if supress hardware ECC */ |
26 | int flash_bbt:1; /* set to 1 to use a flash based bbt */ | ||
26 | }; | 27 | }; |
27 | #endif /* __ASM_ARCH_NAND_H */ | 28 | #endif /* __ASM_ARCH_NAND_H */ |
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig index f348ddfb0492..e2ea04a4c8a1 100644 --- a/arch/arm/plat-omap/Kconfig +++ b/arch/arm/plat-omap/Kconfig | |||
@@ -27,6 +27,7 @@ config ARCH_OMAP4 | |||
27 | bool "TI OMAP4" | 27 | bool "TI OMAP4" |
28 | select CPU_V7 | 28 | select CPU_V7 |
29 | select ARM_GIC | 29 | select ARM_GIC |
30 | select COMMON_CLKDEV | ||
30 | 31 | ||
31 | endchoice | 32 | endchoice |
32 | 33 | ||
@@ -42,28 +43,6 @@ config OMAP_DEBUG_LEDS | |||
42 | depends on OMAP_DEBUG_DEVICES | 43 | depends on OMAP_DEBUG_DEVICES |
43 | default y if LEDS || LEDS_OMAP_DEBUG | 44 | default y if LEDS || LEDS_OMAP_DEBUG |
44 | 45 | ||
45 | config OMAP_DEBUG_POWERDOMAIN | ||
46 | bool "Emit debug messages from powerdomain layer" | ||
47 | depends on ARCH_OMAP2 || ARCH_OMAP3 | ||
48 | help | ||
49 | Say Y here if you want to compile in powerdomain layer | ||
50 | debugging messages for OMAP2/3. These messages can | ||
51 | provide more detail as to why some powerdomain calls | ||
52 | may be failing, and will also emit a descriptive message | ||
53 | for every powerdomain register write. However, the | ||
54 | extra detail costs some memory. | ||
55 | |||
56 | config OMAP_DEBUG_CLOCKDOMAIN | ||
57 | bool "Emit debug messages from clockdomain layer" | ||
58 | depends on ARCH_OMAP2 || ARCH_OMAP3 | ||
59 | help | ||
60 | Say Y here if you want to compile in clockdomain layer | ||
61 | debugging messages for OMAP2/3. These messages can | ||
62 | provide more detail as to why some clockdomain calls | ||
63 | may be failing, and will also emit a descriptive message | ||
64 | for every clockdomain register write. However, the | ||
65 | extra detail costs some memory. | ||
66 | |||
67 | config OMAP_RESET_CLOCKS | 46 | config OMAP_RESET_CLOCKS |
68 | bool "Reset unused clocks during boot" | 47 | bool "Reset unused clocks during boot" |
69 | depends on ARCH_OMAP | 48 | depends on ARCH_OMAP |
@@ -78,28 +57,28 @@ config OMAP_RESET_CLOCKS | |||
78 | 57 | ||
79 | config OMAP_MUX | 58 | config OMAP_MUX |
80 | bool "OMAP multiplexing support" | 59 | bool "OMAP multiplexing support" |
81 | depends on ARCH_OMAP | 60 | depends on ARCH_OMAP |
82 | default y | 61 | default y |
83 | help | 62 | help |
84 | Pin multiplexing support for OMAP boards. If your bootloader | 63 | Pin multiplexing support for OMAP boards. If your bootloader |
85 | sets the multiplexing correctly, say N. Otherwise, or if unsure, | 64 | sets the multiplexing correctly, say N. Otherwise, or if unsure, |
86 | say Y. | 65 | say Y. |
87 | 66 | ||
88 | config OMAP_MUX_DEBUG | 67 | config OMAP_MUX_DEBUG |
89 | bool "Multiplexing debug output" | 68 | bool "Multiplexing debug output" |
90 | depends on OMAP_MUX | 69 | depends on OMAP_MUX |
91 | help | 70 | help |
92 | Makes the multiplexing functions print out a lot of debug info. | 71 | Makes the multiplexing functions print out a lot of debug info. |
93 | This is useful if you want to find out the correct values of the | 72 | This is useful if you want to find out the correct values of the |
94 | multiplexing registers. | 73 | multiplexing registers. |
95 | 74 | ||
96 | config OMAP_MUX_WARNINGS | 75 | config OMAP_MUX_WARNINGS |
97 | bool "Warn about pins the bootloader didn't set up" | 76 | bool "Warn about pins the bootloader didn't set up" |
98 | depends on OMAP_MUX | 77 | depends on OMAP_MUX |
99 | default y | 78 | default y |
100 | help | 79 | help |
101 | Choose Y here to warn whenever driver initialization logic needs | 80 | Choose Y here to warn whenever driver initialization logic needs |
102 | to change the pin multiplexing setup. When there are no warnings | 81 | to change the pin multiplexing setup. When there are no warnings |
103 | printed, it's safe to deselect OMAP_MUX for your product. | 82 | printed, it's safe to deselect OMAP_MUX for your product. |
104 | 83 | ||
105 | config OMAP_MCBSP | 84 | config OMAP_MCBSP |
@@ -125,7 +104,7 @@ config OMAP_IOMMU_DEBUG | |||
125 | tristate | 104 | tristate |
126 | 105 | ||
127 | choice | 106 | choice |
128 | prompt "System timer" | 107 | prompt "System timer" |
129 | default OMAP_MPU_TIMER | 108 | default OMAP_MPU_TIMER |
130 | 109 | ||
131 | config OMAP_MPU_TIMER | 110 | config OMAP_MPU_TIMER |
@@ -148,11 +127,11 @@ config OMAP_32K_TIMER | |||
148 | endchoice | 127 | endchoice |
149 | 128 | ||
150 | config OMAP_32K_TIMER_HZ | 129 | config OMAP_32K_TIMER_HZ |
151 | int "Kernel internal timer frequency for 32KHz timer" | 130 | int "Kernel internal timer frequency for 32KHz timer" |
152 | range 32 1024 | 131 | range 32 1024 |
153 | depends on OMAP_32K_TIMER | 132 | depends on OMAP_32K_TIMER |
154 | default "128" | 133 | default "128" |
155 | help | 134 | help |
156 | Kernel internal timer frequency should be a divisor of 32768, | 135 | Kernel internal timer frequency should be a divisor of 32768, |
157 | such as 64 or 128. | 136 | such as 64 or 128. |
158 | 137 | ||
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c index 681bfc37ebb2..89cafc937249 100644 --- a/arch/arm/plat-omap/clock.c +++ b/arch/arm/plat-omap/clock.c | |||
@@ -40,36 +40,10 @@ static struct clk_functions *arch_clock; | |||
40 | * clock framework is not up , it is defined here to avoid rework in | 40 | * clock framework is not up , it is defined here to avoid rework in |
41 | * every driver. Also dummy prcm reset function is added */ | 41 | * every driver. Also dummy prcm reset function is added */ |
42 | 42 | ||
43 | /* Dummy hooks only for OMAP4.For rest OMAPs, common clkdev is used */ | ||
44 | #if defined(CONFIG_ARCH_OMAP4) | ||
45 | struct clk *clk_get(struct device *dev, const char *id) | ||
46 | { | ||
47 | return NULL; | ||
48 | } | ||
49 | EXPORT_SYMBOL(clk_get); | ||
50 | |||
51 | void clk_put(struct clk *clk) | ||
52 | { | ||
53 | } | ||
54 | EXPORT_SYMBOL(clk_put); | ||
55 | |||
56 | void omap2_clk_prepare_for_reboot(void) | ||
57 | { | ||
58 | } | ||
59 | EXPORT_SYMBOL(omap2_clk_prepare_for_reboot); | ||
60 | |||
61 | void omap_prcm_arch_reset(char mode) | ||
62 | { | ||
63 | } | ||
64 | EXPORT_SYMBOL(omap_prcm_arch_reset); | ||
65 | #endif | ||
66 | int clk_enable(struct clk *clk) | 43 | int clk_enable(struct clk *clk) |
67 | { | 44 | { |
68 | unsigned long flags; | 45 | unsigned long flags; |
69 | int ret = 0; | 46 | int ret = 0; |
70 | if (cpu_is_omap44xx()) | ||
71 | /* OMAP4 clk framework not supported yet */ | ||
72 | return 0; | ||
73 | 47 | ||
74 | if (clk == NULL || IS_ERR(clk)) | 48 | if (clk == NULL || IS_ERR(clk)) |
75 | return -EINVAL; | 49 | return -EINVAL; |
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c index cc050b3313bd..bf1eaf3a27d4 100644 --- a/arch/arm/plat-omap/common.c +++ b/arch/arm/plat-omap/common.c | |||
@@ -280,16 +280,18 @@ void __init omap2_set_globals_343x(void) | |||
280 | #if defined(CONFIG_ARCH_OMAP4) | 280 | #if defined(CONFIG_ARCH_OMAP4) |
281 | static struct omap_globals omap4_globals = { | 281 | static struct omap_globals omap4_globals = { |
282 | .class = OMAP443X_CLASS, | 282 | .class = OMAP443X_CLASS, |
283 | .tap = OMAP2_L4_IO_ADDRESS(0x4830a000), | 283 | .tap = OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE), |
284 | .ctrl = OMAP2_L4_IO_ADDRESS(OMAP443X_CTRL_BASE), | 284 | .ctrl = OMAP2_L4_IO_ADDRESS(OMAP443X_CTRL_BASE), |
285 | .prm = OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE), | 285 | .prm = OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE), |
286 | .cm = OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE), | 286 | .cm = OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE), |
287 | .cm2 = OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE), | ||
287 | }; | 288 | }; |
288 | 289 | ||
289 | void __init omap2_set_globals_443x(void) | 290 | void __init omap2_set_globals_443x(void) |
290 | { | 291 | { |
291 | omap2_set_globals_tap(&omap4_globals); | 292 | omap2_set_globals_tap(&omap4_globals); |
292 | omap2_set_globals_control(&omap4_globals); | 293 | omap2_set_globals_control(&omap4_globals); |
294 | omap2_set_globals_prcm(&omap4_globals); | ||
293 | } | 295 | } |
294 | #endif | 296 | #endif |
295 | 297 | ||
diff --git a/arch/arm/plat-omap/debug-devices.c b/arch/arm/plat-omap/debug-devices.c index 09c1107637f6..923c9621096b 100644 --- a/arch/arm/plat-omap/debug-devices.c +++ b/arch/arm/plat-omap/debug-devices.c | |||
@@ -13,6 +13,7 @@ | |||
13 | #include <linux/init.h> | 13 | #include <linux/init.h> |
14 | #include <linux/platform_device.h> | 14 | #include <linux/platform_device.h> |
15 | #include <linux/io.h> | 15 | #include <linux/io.h> |
16 | #include <linux/smc91x.h> | ||
16 | 17 | ||
17 | #include <mach/hardware.h> | 18 | #include <mach/hardware.h> |
18 | 19 | ||
@@ -24,6 +25,12 @@ | |||
24 | * platforms include H2, H3, H4, and Perseus2. | 25 | * platforms include H2, H3, H4, and Perseus2. |
25 | */ | 26 | */ |
26 | 27 | ||
28 | static struct smc91x_platdata smc91x_info = { | ||
29 | .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, | ||
30 | .leda = RPC_LED_100_10, | ||
31 | .ledb = RPC_LED_TX_RX, | ||
32 | }; | ||
33 | |||
27 | static struct resource smc91x_resources[] = { | 34 | static struct resource smc91x_resources[] = { |
28 | [0] = { | 35 | [0] = { |
29 | .flags = IORESOURCE_MEM, | 36 | .flags = IORESOURCE_MEM, |
@@ -36,6 +43,9 @@ static struct resource smc91x_resources[] = { | |||
36 | static struct platform_device smc91x_device = { | 43 | static struct platform_device smc91x_device = { |
37 | .name = "smc91x", | 44 | .name = "smc91x", |
38 | .id = -1, | 45 | .id = -1, |
46 | .dev = { | ||
47 | .platform_data = &smc91x_info, | ||
48 | }, | ||
39 | .num_resources = ARRAY_SIZE(smc91x_resources), | 49 | .num_resources = ARRAY_SIZE(smc91x_resources), |
40 | .resource = smc91x_resources, | 50 | .resource = smc91x_resources, |
41 | }; | 51 | }; |
diff --git a/arch/arm/plat-omap/debug-leds.c b/arch/arm/plat-omap/debug-leds.c index 6c768b71ad64..53fcef7c5201 100644 --- a/arch/arm/plat-omap/debug-leds.c +++ b/arch/arm/plat-omap/debug-leds.c | |||
@@ -293,7 +293,7 @@ static int fpga_resume_noirq(struct device *dev) | |||
293 | return 0; | 293 | return 0; |
294 | } | 294 | } |
295 | 295 | ||
296 | static struct dev_pm_ops fpga_dev_pm_ops = { | 296 | static const struct dev_pm_ops fpga_dev_pm_ops = { |
297 | .suspend_noirq = fpga_suspend_noirq, | 297 | .suspend_noirq = fpga_suspend_noirq, |
298 | .resume_noirq = fpga_resume_noirq, | 298 | .resume_noirq = fpga_resume_noirq, |
299 | }; | 299 | }; |
diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c index f86617869b38..30b5db73017a 100644 --- a/arch/arm/plat-omap/devices.c +++ b/arch/arm/plat-omap/devices.c | |||
@@ -242,6 +242,39 @@ fail: | |||
242 | 242 | ||
243 | /*-------------------------------------------------------------------------*/ | 243 | /*-------------------------------------------------------------------------*/ |
244 | 244 | ||
245 | #if defined(CONFIG_HW_RANDOM_OMAP) || defined(CONFIG_HW_RANDOM_OMAP_MODULE) | ||
246 | |||
247 | #ifdef CONFIG_ARCH_OMAP24XX | ||
248 | #define OMAP_RNG_BASE 0x480A0000 | ||
249 | #else | ||
250 | #define OMAP_RNG_BASE 0xfffe5000 | ||
251 | #endif | ||
252 | |||
253 | static struct resource rng_resources[] = { | ||
254 | { | ||
255 | .start = OMAP_RNG_BASE, | ||
256 | .end = OMAP_RNG_BASE + 0x4f, | ||
257 | .flags = IORESOURCE_MEM, | ||
258 | }, | ||
259 | }; | ||
260 | |||
261 | static struct platform_device omap_rng_device = { | ||
262 | .name = "omap_rng", | ||
263 | .id = -1, | ||
264 | .num_resources = ARRAY_SIZE(rng_resources), | ||
265 | .resource = rng_resources, | ||
266 | }; | ||
267 | |||
268 | static void omap_init_rng(void) | ||
269 | { | ||
270 | (void) platform_device_register(&omap_rng_device); | ||
271 | } | ||
272 | #else | ||
273 | static inline void omap_init_rng(void) {} | ||
274 | #endif | ||
275 | |||
276 | /*-------------------------------------------------------------------------*/ | ||
277 | |||
245 | /* Numbering for the SPI-capable controllers when used for SPI: | 278 | /* Numbering for the SPI-capable controllers when used for SPI: |
246 | * spi = 1 | 279 | * spi = 1 |
247 | * uwire = 2 | 280 | * uwire = 2 |
@@ -324,39 +357,6 @@ static void omap_init_wdt(void) | |||
324 | static inline void omap_init_wdt(void) {} | 357 | static inline void omap_init_wdt(void) {} |
325 | #endif | 358 | #endif |
326 | 359 | ||
327 | /*-------------------------------------------------------------------------*/ | ||
328 | |||
329 | #if defined(CONFIG_HW_RANDOM_OMAP) || defined(CONFIG_HW_RANDOM_OMAP_MODULE) | ||
330 | |||
331 | #ifdef CONFIG_ARCH_OMAP24XX | ||
332 | #define OMAP_RNG_BASE 0x480A0000 | ||
333 | #else | ||
334 | #define OMAP_RNG_BASE 0xfffe5000 | ||
335 | #endif | ||
336 | |||
337 | static struct resource rng_resources[] = { | ||
338 | { | ||
339 | .start = OMAP_RNG_BASE, | ||
340 | .end = OMAP_RNG_BASE + 0x4f, | ||
341 | .flags = IORESOURCE_MEM, | ||
342 | }, | ||
343 | }; | ||
344 | |||
345 | static struct platform_device omap_rng_device = { | ||
346 | .name = "omap_rng", | ||
347 | .id = -1, | ||
348 | .num_resources = ARRAY_SIZE(rng_resources), | ||
349 | .resource = rng_resources, | ||
350 | }; | ||
351 | |||
352 | static void omap_init_rng(void) | ||
353 | { | ||
354 | (void) platform_device_register(&omap_rng_device); | ||
355 | } | ||
356 | #else | ||
357 | static inline void omap_init_rng(void) {} | ||
358 | #endif | ||
359 | |||
360 | /* | 360 | /* |
361 | * This gets called after board-specific INIT_MACHINE, and initializes most | 361 | * This gets called after board-specific INIT_MACHINE, and initializes most |
362 | * on-chip peripherals accessible on this board (except for few like USB): | 362 | * on-chip peripherals accessible on this board (except for few like USB): |
@@ -384,9 +384,9 @@ static int __init omap_init_devices(void) | |||
384 | */ | 384 | */ |
385 | omap_init_dsp(); | 385 | omap_init_dsp(); |
386 | omap_init_kp(); | 386 | omap_init_kp(); |
387 | omap_init_rng(); | ||
387 | omap_init_uwire(); | 388 | omap_init_uwire(); |
388 | omap_init_wdt(); | 389 | omap_init_wdt(); |
389 | omap_init_rng(); | ||
390 | return 0; | 390 | return 0; |
391 | } | 391 | } |
392 | arch_initcall(omap_init_devices); | 392 | arch_initcall(omap_init_devices); |
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c index d17375e06a1e..09d82b3c66ce 100644 --- a/arch/arm/plat-omap/dma.c +++ b/arch/arm/plat-omap/dma.c | |||
@@ -47,7 +47,6 @@ enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED }; | |||
47 | #endif | 47 | #endif |
48 | 48 | ||
49 | #define OMAP_DMA_ACTIVE 0x01 | 49 | #define OMAP_DMA_ACTIVE 0x01 |
50 | #define OMAP_DMA_CCR_EN (1 << 7) | ||
51 | #define OMAP2_DMA_CSR_CLEAR_MASK 0xffe | 50 | #define OMAP2_DMA_CSR_CLEAR_MASK 0xffe |
52 | 51 | ||
53 | #define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec) | 52 | #define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec) |
@@ -1120,17 +1119,8 @@ int omap_dma_running(void) | |||
1120 | { | 1119 | { |
1121 | int lch; | 1120 | int lch; |
1122 | 1121 | ||
1123 | /* | 1122 | if (cpu_class_is_omap1()) |
1124 | * On OMAP1510, internal LCD controller will start the transfer | 1123 | if (omap_lcd_dma_running()) |
1125 | * when it gets enabled, so assume DMA running if LCD enabled. | ||
1126 | */ | ||
1127 | if (cpu_is_omap1510()) | ||
1128 | if (omap_readw(0xfffec000 + 0x00) & (1 << 0)) | ||
1129 | return 1; | ||
1130 | |||
1131 | /* Check if LCD DMA is running */ | ||
1132 | if (cpu_is_omap16xx()) | ||
1133 | if (omap_readw(OMAP1610_DMA_LCD_CCR) & OMAP_DMA_CCR_EN) | ||
1134 | return 1; | 1124 | return 1; |
1135 | 1125 | ||
1136 | for (lch = 0; lch < dma_chan_count; lch++) | 1126 | for (lch = 0; lch < dma_chan_count; lch++) |
@@ -1990,377 +1980,6 @@ static struct irqaction omap24xx_dma_irq; | |||
1990 | 1980 | ||
1991 | /*----------------------------------------------------------------------------*/ | 1981 | /*----------------------------------------------------------------------------*/ |
1992 | 1982 | ||
1993 | static struct lcd_dma_info { | ||
1994 | spinlock_t lock; | ||
1995 | int reserved; | ||
1996 | void (*callback)(u16 status, void *data); | ||
1997 | void *cb_data; | ||
1998 | |||
1999 | int active; | ||
2000 | unsigned long addr, size; | ||
2001 | int rotate, data_type, xres, yres; | ||
2002 | int vxres; | ||
2003 | int mirror; | ||
2004 | int xscale, yscale; | ||
2005 | int ext_ctrl; | ||
2006 | int src_port; | ||
2007 | int single_transfer; | ||
2008 | } lcd_dma; | ||
2009 | |||
2010 | void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres, | ||
2011 | int data_type) | ||
2012 | { | ||
2013 | lcd_dma.addr = addr; | ||
2014 | lcd_dma.data_type = data_type; | ||
2015 | lcd_dma.xres = fb_xres; | ||
2016 | lcd_dma.yres = fb_yres; | ||
2017 | } | ||
2018 | EXPORT_SYMBOL(omap_set_lcd_dma_b1); | ||
2019 | |||
2020 | void omap_set_lcd_dma_src_port(int port) | ||
2021 | { | ||
2022 | lcd_dma.src_port = port; | ||
2023 | } | ||
2024 | |||
2025 | void omap_set_lcd_dma_ext_controller(int external) | ||
2026 | { | ||
2027 | lcd_dma.ext_ctrl = external; | ||
2028 | } | ||
2029 | EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller); | ||
2030 | |||
2031 | void omap_set_lcd_dma_single_transfer(int single) | ||
2032 | { | ||
2033 | lcd_dma.single_transfer = single; | ||
2034 | } | ||
2035 | EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer); | ||
2036 | |||
2037 | void omap_set_lcd_dma_b1_rotation(int rotate) | ||
2038 | { | ||
2039 | if (omap_dma_in_1510_mode()) { | ||
2040 | printk(KERN_ERR "DMA rotation is not supported in 1510 mode\n"); | ||
2041 | BUG(); | ||
2042 | return; | ||
2043 | } | ||
2044 | lcd_dma.rotate = rotate; | ||
2045 | } | ||
2046 | EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation); | ||
2047 | |||
2048 | void omap_set_lcd_dma_b1_mirror(int mirror) | ||
2049 | { | ||
2050 | if (omap_dma_in_1510_mode()) { | ||
2051 | printk(KERN_ERR "DMA mirror is not supported in 1510 mode\n"); | ||
2052 | BUG(); | ||
2053 | } | ||
2054 | lcd_dma.mirror = mirror; | ||
2055 | } | ||
2056 | EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror); | ||
2057 | |||
2058 | void omap_set_lcd_dma_b1_vxres(unsigned long vxres) | ||
2059 | { | ||
2060 | if (omap_dma_in_1510_mode()) { | ||
2061 | printk(KERN_ERR "DMA virtual resulotion is not supported " | ||
2062 | "in 1510 mode\n"); | ||
2063 | BUG(); | ||
2064 | } | ||
2065 | lcd_dma.vxres = vxres; | ||
2066 | } | ||
2067 | EXPORT_SYMBOL(omap_set_lcd_dma_b1_vxres); | ||
2068 | |||
2069 | void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale) | ||
2070 | { | ||
2071 | if (omap_dma_in_1510_mode()) { | ||
2072 | printk(KERN_ERR "DMA scale is not supported in 1510 mode\n"); | ||
2073 | BUG(); | ||
2074 | } | ||
2075 | lcd_dma.xscale = xscale; | ||
2076 | lcd_dma.yscale = yscale; | ||
2077 | } | ||
2078 | EXPORT_SYMBOL(omap_set_lcd_dma_b1_scale); | ||
2079 | |||
2080 | static void set_b1_regs(void) | ||
2081 | { | ||
2082 | unsigned long top, bottom; | ||
2083 | int es; | ||
2084 | u16 w; | ||
2085 | unsigned long en, fn; | ||
2086 | long ei, fi; | ||
2087 | unsigned long vxres; | ||
2088 | unsigned int xscale, yscale; | ||
2089 | |||
2090 | switch (lcd_dma.data_type) { | ||
2091 | case OMAP_DMA_DATA_TYPE_S8: | ||
2092 | es = 1; | ||
2093 | break; | ||
2094 | case OMAP_DMA_DATA_TYPE_S16: | ||
2095 | es = 2; | ||
2096 | break; | ||
2097 | case OMAP_DMA_DATA_TYPE_S32: | ||
2098 | es = 4; | ||
2099 | break; | ||
2100 | default: | ||
2101 | BUG(); | ||
2102 | return; | ||
2103 | } | ||
2104 | |||
2105 | vxres = lcd_dma.vxres ? lcd_dma.vxres : lcd_dma.xres; | ||
2106 | xscale = lcd_dma.xscale ? lcd_dma.xscale : 1; | ||
2107 | yscale = lcd_dma.yscale ? lcd_dma.yscale : 1; | ||
2108 | BUG_ON(vxres < lcd_dma.xres); | ||
2109 | |||
2110 | #define PIXADDR(x, y) (lcd_dma.addr + \ | ||
2111 | ((y) * vxres * yscale + (x) * xscale) * es) | ||
2112 | #define PIXSTEP(sx, sy, dx, dy) (PIXADDR(dx, dy) - PIXADDR(sx, sy) - es + 1) | ||
2113 | |||
2114 | switch (lcd_dma.rotate) { | ||
2115 | case 0: | ||
2116 | if (!lcd_dma.mirror) { | ||
2117 | top = PIXADDR(0, 0); | ||
2118 | bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1); | ||
2119 | /* 1510 DMA requires the bottom address to be 2 more | ||
2120 | * than the actual last memory access location. */ | ||
2121 | if (omap_dma_in_1510_mode() && | ||
2122 | lcd_dma.data_type == OMAP_DMA_DATA_TYPE_S32) | ||
2123 | bottom += 2; | ||
2124 | ei = PIXSTEP(0, 0, 1, 0); | ||
2125 | fi = PIXSTEP(lcd_dma.xres - 1, 0, 0, 1); | ||
2126 | } else { | ||
2127 | top = PIXADDR(lcd_dma.xres - 1, 0); | ||
2128 | bottom = PIXADDR(0, lcd_dma.yres - 1); | ||
2129 | ei = PIXSTEP(1, 0, 0, 0); | ||
2130 | fi = PIXSTEP(0, 0, lcd_dma.xres - 1, 1); | ||
2131 | } | ||
2132 | en = lcd_dma.xres; | ||
2133 | fn = lcd_dma.yres; | ||
2134 | break; | ||
2135 | case 90: | ||
2136 | if (!lcd_dma.mirror) { | ||
2137 | top = PIXADDR(0, lcd_dma.yres - 1); | ||
2138 | bottom = PIXADDR(lcd_dma.xres - 1, 0); | ||
2139 | ei = PIXSTEP(0, 1, 0, 0); | ||
2140 | fi = PIXSTEP(0, 0, 1, lcd_dma.yres - 1); | ||
2141 | } else { | ||
2142 | top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1); | ||
2143 | bottom = PIXADDR(0, 0); | ||
2144 | ei = PIXSTEP(0, 1, 0, 0); | ||
2145 | fi = PIXSTEP(1, 0, 0, lcd_dma.yres - 1); | ||
2146 | } | ||
2147 | en = lcd_dma.yres; | ||
2148 | fn = lcd_dma.xres; | ||
2149 | break; | ||
2150 | case 180: | ||
2151 | if (!lcd_dma.mirror) { | ||
2152 | top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1); | ||
2153 | bottom = PIXADDR(0, 0); | ||
2154 | ei = PIXSTEP(1, 0, 0, 0); | ||
2155 | fi = PIXSTEP(0, 1, lcd_dma.xres - 1, 0); | ||
2156 | } else { | ||
2157 | top = PIXADDR(0, lcd_dma.yres - 1); | ||
2158 | bottom = PIXADDR(lcd_dma.xres - 1, 0); | ||
2159 | ei = PIXSTEP(0, 0, 1, 0); | ||
2160 | fi = PIXSTEP(lcd_dma.xres - 1, 1, 0, 0); | ||
2161 | } | ||
2162 | en = lcd_dma.xres; | ||
2163 | fn = lcd_dma.yres; | ||
2164 | break; | ||
2165 | case 270: | ||
2166 | if (!lcd_dma.mirror) { | ||
2167 | top = PIXADDR(lcd_dma.xres - 1, 0); | ||
2168 | bottom = PIXADDR(0, lcd_dma.yres - 1); | ||
2169 | ei = PIXSTEP(0, 0, 0, 1); | ||
2170 | fi = PIXSTEP(1, lcd_dma.yres - 1, 0, 0); | ||
2171 | } else { | ||
2172 | top = PIXADDR(0, 0); | ||
2173 | bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1); | ||
2174 | ei = PIXSTEP(0, 0, 0, 1); | ||
2175 | fi = PIXSTEP(0, lcd_dma.yres - 1, 1, 0); | ||
2176 | } | ||
2177 | en = lcd_dma.yres; | ||
2178 | fn = lcd_dma.xres; | ||
2179 | break; | ||
2180 | default: | ||
2181 | BUG(); | ||
2182 | return; /* Suppress warning about uninitialized vars */ | ||
2183 | } | ||
2184 | |||
2185 | if (omap_dma_in_1510_mode()) { | ||
2186 | omap_writew(top >> 16, OMAP1510_DMA_LCD_TOP_F1_U); | ||
2187 | omap_writew(top, OMAP1510_DMA_LCD_TOP_F1_L); | ||
2188 | omap_writew(bottom >> 16, OMAP1510_DMA_LCD_BOT_F1_U); | ||
2189 | omap_writew(bottom, OMAP1510_DMA_LCD_BOT_F1_L); | ||
2190 | |||
2191 | return; | ||
2192 | } | ||
2193 | |||
2194 | /* 1610 regs */ | ||
2195 | omap_writew(top >> 16, OMAP1610_DMA_LCD_TOP_B1_U); | ||
2196 | omap_writew(top, OMAP1610_DMA_LCD_TOP_B1_L); | ||
2197 | omap_writew(bottom >> 16, OMAP1610_DMA_LCD_BOT_B1_U); | ||
2198 | omap_writew(bottom, OMAP1610_DMA_LCD_BOT_B1_L); | ||
2199 | |||
2200 | omap_writew(en, OMAP1610_DMA_LCD_SRC_EN_B1); | ||
2201 | omap_writew(fn, OMAP1610_DMA_LCD_SRC_FN_B1); | ||
2202 | |||
2203 | w = omap_readw(OMAP1610_DMA_LCD_CSDP); | ||
2204 | w &= ~0x03; | ||
2205 | w |= lcd_dma.data_type; | ||
2206 | omap_writew(w, OMAP1610_DMA_LCD_CSDP); | ||
2207 | |||
2208 | w = omap_readw(OMAP1610_DMA_LCD_CTRL); | ||
2209 | /* Always set the source port as SDRAM for now*/ | ||
2210 | w &= ~(0x03 << 6); | ||
2211 | if (lcd_dma.callback != NULL) | ||
2212 | w |= 1 << 1; /* Block interrupt enable */ | ||
2213 | else | ||
2214 | w &= ~(1 << 1); | ||
2215 | omap_writew(w, OMAP1610_DMA_LCD_CTRL); | ||
2216 | |||
2217 | if (!(lcd_dma.rotate || lcd_dma.mirror || | ||
2218 | lcd_dma.vxres || lcd_dma.xscale || lcd_dma.yscale)) | ||
2219 | return; | ||
2220 | |||
2221 | w = omap_readw(OMAP1610_DMA_LCD_CCR); | ||
2222 | /* Set the double-indexed addressing mode */ | ||
2223 | w |= (0x03 << 12); | ||
2224 | omap_writew(w, OMAP1610_DMA_LCD_CCR); | ||
2225 | |||
2226 | omap_writew(ei, OMAP1610_DMA_LCD_SRC_EI_B1); | ||
2227 | omap_writew(fi >> 16, OMAP1610_DMA_LCD_SRC_FI_B1_U); | ||
2228 | omap_writew(fi, OMAP1610_DMA_LCD_SRC_FI_B1_L); | ||
2229 | } | ||
2230 | |||
2231 | static irqreturn_t lcd_dma_irq_handler(int irq, void *dev_id) | ||
2232 | { | ||
2233 | u16 w; | ||
2234 | |||
2235 | w = omap_readw(OMAP1610_DMA_LCD_CTRL); | ||
2236 | if (unlikely(!(w & (1 << 3)))) { | ||
2237 | printk(KERN_WARNING "Spurious LCD DMA IRQ\n"); | ||
2238 | return IRQ_NONE; | ||
2239 | } | ||
2240 | /* Ack the IRQ */ | ||
2241 | w |= (1 << 3); | ||
2242 | omap_writew(w, OMAP1610_DMA_LCD_CTRL); | ||
2243 | lcd_dma.active = 0; | ||
2244 | if (lcd_dma.callback != NULL) | ||
2245 | lcd_dma.callback(w, lcd_dma.cb_data); | ||
2246 | |||
2247 | return IRQ_HANDLED; | ||
2248 | } | ||
2249 | |||
2250 | int omap_request_lcd_dma(void (*callback)(u16 status, void *data), | ||
2251 | void *data) | ||
2252 | { | ||
2253 | spin_lock_irq(&lcd_dma.lock); | ||
2254 | if (lcd_dma.reserved) { | ||
2255 | spin_unlock_irq(&lcd_dma.lock); | ||
2256 | printk(KERN_ERR "LCD DMA channel already reserved\n"); | ||
2257 | BUG(); | ||
2258 | return -EBUSY; | ||
2259 | } | ||
2260 | lcd_dma.reserved = 1; | ||
2261 | spin_unlock_irq(&lcd_dma.lock); | ||
2262 | lcd_dma.callback = callback; | ||
2263 | lcd_dma.cb_data = data; | ||
2264 | lcd_dma.active = 0; | ||
2265 | lcd_dma.single_transfer = 0; | ||
2266 | lcd_dma.rotate = 0; | ||
2267 | lcd_dma.vxres = 0; | ||
2268 | lcd_dma.mirror = 0; | ||
2269 | lcd_dma.xscale = 0; | ||
2270 | lcd_dma.yscale = 0; | ||
2271 | lcd_dma.ext_ctrl = 0; | ||
2272 | lcd_dma.src_port = 0; | ||
2273 | |||
2274 | return 0; | ||
2275 | } | ||
2276 | EXPORT_SYMBOL(omap_request_lcd_dma); | ||
2277 | |||
2278 | void omap_free_lcd_dma(void) | ||
2279 | { | ||
2280 | spin_lock(&lcd_dma.lock); | ||
2281 | if (!lcd_dma.reserved) { | ||
2282 | spin_unlock(&lcd_dma.lock); | ||
2283 | printk(KERN_ERR "LCD DMA is not reserved\n"); | ||
2284 | BUG(); | ||
2285 | return; | ||
2286 | } | ||
2287 | if (!enable_1510_mode) | ||
2288 | omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR) & ~1, | ||
2289 | OMAP1610_DMA_LCD_CCR); | ||
2290 | lcd_dma.reserved = 0; | ||
2291 | spin_unlock(&lcd_dma.lock); | ||
2292 | } | ||
2293 | EXPORT_SYMBOL(omap_free_lcd_dma); | ||
2294 | |||
2295 | void omap_enable_lcd_dma(void) | ||
2296 | { | ||
2297 | u16 w; | ||
2298 | |||
2299 | /* | ||
2300 | * Set the Enable bit only if an external controller is | ||
2301 | * connected. Otherwise the OMAP internal controller will | ||
2302 | * start the transfer when it gets enabled. | ||
2303 | */ | ||
2304 | if (enable_1510_mode || !lcd_dma.ext_ctrl) | ||
2305 | return; | ||
2306 | |||
2307 | w = omap_readw(OMAP1610_DMA_LCD_CTRL); | ||
2308 | w |= 1 << 8; | ||
2309 | omap_writew(w, OMAP1610_DMA_LCD_CTRL); | ||
2310 | |||
2311 | lcd_dma.active = 1; | ||
2312 | |||
2313 | w = omap_readw(OMAP1610_DMA_LCD_CCR); | ||
2314 | w |= 1 << 7; | ||
2315 | omap_writew(w, OMAP1610_DMA_LCD_CCR); | ||
2316 | } | ||
2317 | EXPORT_SYMBOL(omap_enable_lcd_dma); | ||
2318 | |||
2319 | void omap_setup_lcd_dma(void) | ||
2320 | { | ||
2321 | BUG_ON(lcd_dma.active); | ||
2322 | if (!enable_1510_mode) { | ||
2323 | /* Set some reasonable defaults */ | ||
2324 | omap_writew(0x5440, OMAP1610_DMA_LCD_CCR); | ||
2325 | omap_writew(0x9102, OMAP1610_DMA_LCD_CSDP); | ||
2326 | omap_writew(0x0004, OMAP1610_DMA_LCD_LCH_CTRL); | ||
2327 | } | ||
2328 | set_b1_regs(); | ||
2329 | if (!enable_1510_mode) { | ||
2330 | u16 w; | ||
2331 | |||
2332 | w = omap_readw(OMAP1610_DMA_LCD_CCR); | ||
2333 | /* | ||
2334 | * If DMA was already active set the end_prog bit to have | ||
2335 | * the programmed register set loaded into the active | ||
2336 | * register set. | ||
2337 | */ | ||
2338 | w |= 1 << 11; /* End_prog */ | ||
2339 | if (!lcd_dma.single_transfer) | ||
2340 | w |= (3 << 8); /* Auto_init, repeat */ | ||
2341 | omap_writew(w, OMAP1610_DMA_LCD_CCR); | ||
2342 | } | ||
2343 | } | ||
2344 | EXPORT_SYMBOL(omap_setup_lcd_dma); | ||
2345 | |||
2346 | void omap_stop_lcd_dma(void) | ||
2347 | { | ||
2348 | u16 w; | ||
2349 | |||
2350 | lcd_dma.active = 0; | ||
2351 | if (enable_1510_mode || !lcd_dma.ext_ctrl) | ||
2352 | return; | ||
2353 | |||
2354 | w = omap_readw(OMAP1610_DMA_LCD_CCR); | ||
2355 | w &= ~(1 << 7); | ||
2356 | omap_writew(w, OMAP1610_DMA_LCD_CCR); | ||
2357 | |||
2358 | w = omap_readw(OMAP1610_DMA_LCD_CTRL); | ||
2359 | w &= ~(1 << 8); | ||
2360 | omap_writew(w, OMAP1610_DMA_LCD_CTRL); | ||
2361 | } | ||
2362 | EXPORT_SYMBOL(omap_stop_lcd_dma); | ||
2363 | |||
2364 | void omap_dma_global_context_save(void) | 1983 | void omap_dma_global_context_save(void) |
2365 | { | 1984 | { |
2366 | omap_dma_global_context.dma_irqenable_l0 = | 1985 | omap_dma_global_context.dma_irqenable_l0 = |
@@ -2465,14 +2084,6 @@ static int __init omap_init_dma(void) | |||
2465 | dma_chan_count = 16; | 2084 | dma_chan_count = 16; |
2466 | } else | 2085 | } else |
2467 | dma_chan_count = 9; | 2086 | dma_chan_count = 9; |
2468 | if (cpu_is_omap16xx()) { | ||
2469 | u16 w; | ||
2470 | |||
2471 | /* this would prevent OMAP sleep */ | ||
2472 | w = omap_readw(OMAP1610_DMA_LCD_CTRL); | ||
2473 | w &= ~(1 << 8); | ||
2474 | omap_writew(w, OMAP1610_DMA_LCD_CTRL); | ||
2475 | } | ||
2476 | } else if (cpu_class_is_omap2()) { | 2087 | } else if (cpu_class_is_omap2()) { |
2477 | u8 revision = dma_read(REVISION) & 0xff; | 2088 | u8 revision = dma_read(REVISION) & 0xff; |
2478 | printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n", | 2089 | printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n", |
@@ -2483,7 +2094,6 @@ static int __init omap_init_dma(void) | |||
2483 | return 0; | 2094 | return 0; |
2484 | } | 2095 | } |
2485 | 2096 | ||
2486 | spin_lock_init(&lcd_dma.lock); | ||
2487 | spin_lock_init(&dma_chan_lock); | 2097 | spin_lock_init(&dma_chan_lock); |
2488 | 2098 | ||
2489 | for (ch = 0; ch < dma_chan_count; ch++) { | 2099 | for (ch = 0; ch < dma_chan_count; ch++) { |
@@ -2548,22 +2158,6 @@ static int __init omap_init_dma(void) | |||
2548 | } | 2158 | } |
2549 | } | 2159 | } |
2550 | 2160 | ||
2551 | |||
2552 | /* FIXME: Update LCD DMA to work on 24xx */ | ||
2553 | if (cpu_class_is_omap1()) { | ||
2554 | r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0, | ||
2555 | "LCD DMA", NULL); | ||
2556 | if (r != 0) { | ||
2557 | int i; | ||
2558 | |||
2559 | printk(KERN_ERR "unable to request IRQ for LCD DMA " | ||
2560 | "(error %d)\n", r); | ||
2561 | for (i = 0; i < dma_chan_count; i++) | ||
2562 | free_irq(omap1_dma_irq[i], (void *) (i + 1)); | ||
2563 | goto out_free; | ||
2564 | } | ||
2565 | } | ||
2566 | |||
2567 | return 0; | 2161 | return 0; |
2568 | 2162 | ||
2569 | out_free: | 2163 | out_free: |
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c index 055160e0620e..04846811d0aa 100644 --- a/arch/arm/plat-omap/gpio.c +++ b/arch/arm/plat-omap/gpio.c | |||
@@ -1431,7 +1431,7 @@ static int omap_mpuio_resume_noirq(struct device *dev) | |||
1431 | return 0; | 1431 | return 0; |
1432 | } | 1432 | } |
1433 | 1433 | ||
1434 | static struct dev_pm_ops omap_mpuio_dev_pm_ops = { | 1434 | static const struct dev_pm_ops omap_mpuio_dev_pm_ops = { |
1435 | .suspend_noirq = omap_mpuio_suspend_noirq, | 1435 | .suspend_noirq = omap_mpuio_suspend_noirq, |
1436 | .resume_noirq = omap_mpuio_resume_noirq, | 1436 | .resume_noirq = omap_mpuio_resume_noirq, |
1437 | }; | 1437 | }; |
diff --git a/arch/arm/plat-omap/i2c.c b/arch/arm/plat-omap/i2c.c index c08362dbb8ed..33fff4ef382d 100644 --- a/arch/arm/plat-omap/i2c.c +++ b/arch/arm/plat-omap/i2c.c | |||
@@ -80,47 +80,8 @@ static struct platform_device omap_i2c_devices[] = { | |||
80 | #endif | 80 | #endif |
81 | }; | 81 | }; |
82 | 82 | ||
83 | #if defined(CONFIG_ARCH_OMAP24XX) | ||
84 | static const int omap24xx_pins[][2] = { | ||
85 | { M19_24XX_I2C1_SCL, L15_24XX_I2C1_SDA }, | ||
86 | { J15_24XX_I2C2_SCL, H19_24XX_I2C2_SDA }, | ||
87 | }; | ||
88 | #else | ||
89 | static const int omap24xx_pins[][2] = {}; | ||
90 | #endif | ||
91 | #if defined(CONFIG_ARCH_OMAP34XX) | ||
92 | static const int omap34xx_pins[][2] = { | ||
93 | { K21_34XX_I2C1_SCL, J21_34XX_I2C1_SDA}, | ||
94 | { AF15_34XX_I2C2_SCL, AE15_34XX_I2C2_SDA}, | ||
95 | { AF14_34XX_I2C3_SCL, AG14_34XX_I2C3_SDA}, | ||
96 | }; | ||
97 | #else | ||
98 | static const int omap34xx_pins[][2] = {}; | ||
99 | #endif | ||
100 | |||
101 | #define OMAP_I2C_CMDLINE_SETUP (BIT(31)) | 83 | #define OMAP_I2C_CMDLINE_SETUP (BIT(31)) |
102 | 84 | ||
103 | static void __init omap_i2c_mux_pins(int bus) | ||
104 | { | ||
105 | int scl, sda; | ||
106 | |||
107 | if (cpu_class_is_omap1()) { | ||
108 | scl = I2C_SCL; | ||
109 | sda = I2C_SDA; | ||
110 | } else if (cpu_is_omap24xx()) { | ||
111 | scl = omap24xx_pins[bus][0]; | ||
112 | sda = omap24xx_pins[bus][1]; | ||
113 | } else if (cpu_is_omap34xx()) { | ||
114 | scl = omap34xx_pins[bus][0]; | ||
115 | sda = omap34xx_pins[bus][1]; | ||
116 | } else { | ||
117 | return; | ||
118 | } | ||
119 | |||
120 | omap_cfg_reg(sda); | ||
121 | omap_cfg_reg(scl); | ||
122 | } | ||
123 | |||
124 | static int __init omap_i2c_nr_ports(void) | 85 | static int __init omap_i2c_nr_ports(void) |
125 | { | 86 | { |
126 | int ports = 0; | 87 | int ports = 0; |
@@ -156,7 +117,6 @@ static int __init omap_i2c_add_bus(int bus_id) | |||
156 | res[1].start = irq; | 117 | res[1].start = irq; |
157 | } | 118 | } |
158 | 119 | ||
159 | omap_i2c_mux_pins(bus_id - 1); | ||
160 | return platform_device_register(pdev); | 120 | return platform_device_register(pdev); |
161 | } | 121 | } |
162 | 122 | ||
@@ -209,7 +169,7 @@ out: | |||
209 | subsys_initcall(omap_register_i2c_bus_cmdline); | 169 | subsys_initcall(omap_register_i2c_bus_cmdline); |
210 | 170 | ||
211 | /** | 171 | /** |
212 | * omap_register_i2c_bus - register I2C bus with device descriptors | 172 | * omap_plat_register_i2c_bus - register I2C bus with device descriptors |
213 | * @bus_id: bus id counting from number 1 | 173 | * @bus_id: bus id counting from number 1 |
214 | * @clkrate: clock rate of the bus in kHz | 174 | * @clkrate: clock rate of the bus in kHz |
215 | * @info: pointer into I2C device descriptor table or NULL | 175 | * @info: pointer into I2C device descriptor table or NULL |
@@ -217,7 +177,7 @@ subsys_initcall(omap_register_i2c_bus_cmdline); | |||
217 | * | 177 | * |
218 | * Returns 0 on success or an error code. | 178 | * Returns 0 on success or an error code. |
219 | */ | 179 | */ |
220 | int __init omap_register_i2c_bus(int bus_id, u32 clkrate, | 180 | int __init omap_plat_register_i2c_bus(int bus_id, u32 clkrate, |
221 | struct i2c_board_info const *info, | 181 | struct i2c_board_info const *info, |
222 | unsigned len) | 182 | unsigned len) |
223 | { | 183 | { |
diff --git a/arch/arm/plat-omap/include/plat/board.h b/arch/arm/plat-omap/include/plat/board.h index abb17b604f82..376ce18216ff 100644 --- a/arch/arm/plat-omap/include/plat/board.h +++ b/arch/arm/plat-omap/include/plat/board.h | |||
@@ -114,15 +114,6 @@ struct omap_pwm_led_platform_data { | |||
114 | void (*set_power)(struct omap_pwm_led_platform_data *self, int on_off); | 114 | void (*set_power)(struct omap_pwm_led_platform_data *self, int on_off); |
115 | }; | 115 | }; |
116 | 116 | ||
117 | /* See arch/arm/plat-omap/include/mach/gpio-switch.h for definitions */ | ||
118 | struct omap_gpio_switch_config { | ||
119 | char name[12]; | ||
120 | u16 gpio; | ||
121 | int flags:4; | ||
122 | int type:4; | ||
123 | int key_code:24; /* Linux key code */ | ||
124 | }; | ||
125 | |||
126 | struct omap_uart_config { | 117 | struct omap_uart_config { |
127 | /* Bit field of UARTs present; bit 0 --> UART1 */ | 118 | /* Bit field of UARTs present; bit 0 --> UART1 */ |
128 | unsigned int enabled_uarts; | 119 | unsigned int enabled_uarts; |
diff --git a/arch/arm/plat-omap/include/plat/clkdev_omap.h b/arch/arm/plat-omap/include/plat/clkdev_omap.h new file mode 100644 index 000000000000..35b36caf5f91 --- /dev/null +++ b/arch/arm/plat-omap/include/plat/clkdev_omap.h | |||
@@ -0,0 +1,41 @@ | |||
1 | /* | ||
2 | * clkdev <-> OMAP integration | ||
3 | * | ||
4 | * Russell King <linux@arm.linux.org.uk> | ||
5 | * | ||
6 | */ | ||
7 | |||
8 | #ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_CLKDEV_OMAP_H | ||
9 | #define __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_CLKDEV_OMAP_H | ||
10 | |||
11 | #include <asm/clkdev.h> | ||
12 | |||
13 | struct omap_clk { | ||
14 | u16 cpu; | ||
15 | struct clk_lookup lk; | ||
16 | }; | ||
17 | |||
18 | #define CLK(dev, con, ck, cp) \ | ||
19 | { \ | ||
20 | .cpu = cp, \ | ||
21 | .lk = { \ | ||
22 | .dev_id = dev, \ | ||
23 | .con_id = con, \ | ||
24 | .clk = ck, \ | ||
25 | }, \ | ||
26 | } | ||
27 | |||
28 | |||
29 | #define CK_310 (1 << 0) | ||
30 | #define CK_7XX (1 << 1) | ||
31 | #define CK_1510 (1 << 2) | ||
32 | #define CK_16XX (1 << 3) | ||
33 | #define CK_243X (1 << 4) | ||
34 | #define CK_242X (1 << 5) | ||
35 | #define CK_343X (1 << 6) | ||
36 | #define CK_3430ES1 (1 << 7) | ||
37 | #define CK_3430ES2 (1 << 8) | ||
38 | #define CK_443X (1 << 9) | ||
39 | |||
40 | #endif | ||
41 | |||
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h index 4b8b0d65cbf2..309b6d1dccdb 100644 --- a/arch/arm/plat-omap/include/plat/clock.h +++ b/arch/arm/plat-omap/include/plat/clock.h | |||
@@ -13,6 +13,8 @@ | |||
13 | #ifndef __ARCH_ARM_OMAP_CLOCK_H | 13 | #ifndef __ARCH_ARM_OMAP_CLOCK_H |
14 | #define __ARCH_ARM_OMAP_CLOCK_H | 14 | #define __ARCH_ARM_OMAP_CLOCK_H |
15 | 15 | ||
16 | #include <linux/list.h> | ||
17 | |||
16 | struct module; | 18 | struct module; |
17 | struct clk; | 19 | struct clk; |
18 | struct clockdomain; | 20 | struct clockdomain; |
@@ -148,6 +150,8 @@ extern const struct clkops clkops_null; | |||
148 | #define CONFIG_PARTICIPANT (1 << 10) /* Fundamental clock */ | 150 | #define CONFIG_PARTICIPANT (1 << 10) /* Fundamental clock */ |
149 | #define ENABLE_ON_INIT (1 << 11) /* Enable upon framework init */ | 151 | #define ENABLE_ON_INIT (1 << 11) /* Enable upon framework init */ |
150 | #define INVERT_ENABLE (1 << 12) /* 0 enables, 1 disables */ | 152 | #define INVERT_ENABLE (1 << 12) /* 0 enables, 1 disables */ |
153 | #define CLOCK_IN_OMAP4430 (1 << 13) | ||
154 | #define ALWAYS_ENABLED (1 << 14) | ||
151 | /* bits 13-31 are currently free */ | 155 | /* bits 13-31 are currently free */ |
152 | 156 | ||
153 | /* Clksel_rate flags */ | 157 | /* Clksel_rate flags */ |
@@ -156,6 +160,7 @@ extern const struct clkops clkops_null; | |||
156 | #define RATE_IN_243X (1 << 2) | 160 | #define RATE_IN_243X (1 << 2) |
157 | #define RATE_IN_343X (1 << 3) /* rates common to all 343X */ | 161 | #define RATE_IN_343X (1 << 3) /* rates common to all 343X */ |
158 | #define RATE_IN_3430ES2 (1 << 4) /* 3430ES2 rates only */ | 162 | #define RATE_IN_3430ES2 (1 << 4) /* 3430ES2 rates only */ |
163 | #define RATE_IN_4430 (1 << 5) | ||
159 | 164 | ||
160 | #define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X) | 165 | #define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X) |
161 | 166 | ||
diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h index 064f1730f43b..32c22272425d 100644 --- a/arch/arm/plat-omap/include/plat/common.h +++ b/arch/arm/plat-omap/include/plat/common.h | |||
@@ -27,7 +27,7 @@ | |||
27 | #ifndef __ARCH_ARM_MACH_OMAP_COMMON_H | 27 | #ifndef __ARCH_ARM_MACH_OMAP_COMMON_H |
28 | #define __ARCH_ARM_MACH_OMAP_COMMON_H | 28 | #define __ARCH_ARM_MACH_OMAP_COMMON_H |
29 | 29 | ||
30 | #include <linux/i2c.h> | 30 | #include <plat/i2c.h> |
31 | 31 | ||
32 | struct sys_timer; | 32 | struct sys_timer; |
33 | 33 | ||
@@ -36,18 +36,6 @@ extern void __iomem *gic_cpu_base_addr; | |||
36 | 36 | ||
37 | extern void omap_map_common_io(void); | 37 | extern void omap_map_common_io(void); |
38 | extern struct sys_timer omap_timer; | 38 | extern struct sys_timer omap_timer; |
39 | #if defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE) | ||
40 | extern int omap_register_i2c_bus(int bus_id, u32 clkrate, | ||
41 | struct i2c_board_info const *info, | ||
42 | unsigned len); | ||
43 | #else | ||
44 | static inline int omap_register_i2c_bus(int bus_id, u32 clkrate, | ||
45 | struct i2c_board_info const *info, | ||
46 | unsigned len) | ||
47 | { | ||
48 | return 0; | ||
49 | } | ||
50 | #endif | ||
51 | 39 | ||
52 | /* IO bases for various OMAP processors */ | 40 | /* IO bases for various OMAP processors */ |
53 | struct omap_globals { | 41 | struct omap_globals { |
@@ -58,6 +46,7 @@ struct omap_globals { | |||
58 | void __iomem *ctrl; /* System Control Module */ | 46 | void __iomem *ctrl; /* System Control Module */ |
59 | void __iomem *prm; /* Power and Reset Management */ | 47 | void __iomem *prm; /* Power and Reset Management */ |
60 | void __iomem *cm; /* Clock Management */ | 48 | void __iomem *cm; /* Clock Management */ |
49 | void __iomem *cm2; | ||
61 | }; | 50 | }; |
62 | 51 | ||
63 | void omap2_set_globals_242x(void); | 52 | void omap2_set_globals_242x(void); |
@@ -71,4 +60,24 @@ void omap2_set_globals_sdrc(struct omap_globals *); | |||
71 | void omap2_set_globals_control(struct omap_globals *); | 60 | void omap2_set_globals_control(struct omap_globals *); |
72 | void omap2_set_globals_prcm(struct omap_globals *); | 61 | void omap2_set_globals_prcm(struct omap_globals *); |
73 | 62 | ||
63 | /** | ||
64 | * omap_test_timeout - busy-loop, testing a condition | ||
65 | * @cond: condition to test until it evaluates to true | ||
66 | * @timeout: maximum number of microseconds in the timeout | ||
67 | * @index: loop index (integer) | ||
68 | * | ||
69 | * Loop waiting for @cond to become true or until at least @timeout | ||
70 | * microseconds have passed. To use, define some integer @index in the | ||
71 | * calling code. After running, if @index == @timeout, then the loop has | ||
72 | * timed out. | ||
73 | */ | ||
74 | #define omap_test_timeout(cond, timeout, index) \ | ||
75 | ({ \ | ||
76 | for (index = 0; index < timeout; index++) { \ | ||
77 | if (cond) \ | ||
78 | break; \ | ||
79 | udelay(1); \ | ||
80 | } \ | ||
81 | }) | ||
82 | |||
74 | #endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */ | 83 | #endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */ |
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h index 2e1789001dfe..9a028bdebb06 100644 --- a/arch/arm/plat-omap/include/plat/cpu.h +++ b/arch/arm/plat-omap/include/plat/cpu.h | |||
@@ -176,11 +176,13 @@ IS_OMAP_CLASS(15xx, 0x15) | |||
176 | IS_OMAP_CLASS(16xx, 0x16) | 176 | IS_OMAP_CLASS(16xx, 0x16) |
177 | IS_OMAP_CLASS(24xx, 0x24) | 177 | IS_OMAP_CLASS(24xx, 0x24) |
178 | IS_OMAP_CLASS(34xx, 0x34) | 178 | IS_OMAP_CLASS(34xx, 0x34) |
179 | IS_OMAP_CLASS(44xx, 0x44) | ||
179 | 180 | ||
180 | IS_OMAP_SUBCLASS(242x, 0x242) | 181 | IS_OMAP_SUBCLASS(242x, 0x242) |
181 | IS_OMAP_SUBCLASS(243x, 0x243) | 182 | IS_OMAP_SUBCLASS(243x, 0x243) |
182 | IS_OMAP_SUBCLASS(343x, 0x343) | 183 | IS_OMAP_SUBCLASS(343x, 0x343) |
183 | IS_OMAP_SUBCLASS(363x, 0x363) | 184 | IS_OMAP_SUBCLASS(363x, 0x363) |
185 | IS_OMAP_SUBCLASS(443x, 0x443) | ||
184 | 186 | ||
185 | #define cpu_is_omap7xx() 0 | 187 | #define cpu_is_omap7xx() 0 |
186 | #define cpu_is_omap15xx() 0 | 188 | #define cpu_is_omap15xx() 0 |
@@ -393,11 +395,11 @@ IS_OMAP_TYPE(3517, 0x3517) | |||
393 | (!omap3_has_iva()) && \ | 395 | (!omap3_has_iva()) && \ |
394 | (!omap3_has_sgx())) | 396 | (!omap3_has_sgx())) |
395 | # define cpu_is_omap3515() (cpu_is_omap3430() && \ | 397 | # define cpu_is_omap3515() (cpu_is_omap3430() && \ |
396 | (omap3_has_iva()) && \ | 398 | (!omap3_has_iva()) && \ |
397 | (!omap3_has_sgx())) | 399 | (omap3_has_sgx())) |
398 | # define cpu_is_omap3525() (cpu_is_omap3430() && \ | 400 | # define cpu_is_omap3525() (cpu_is_omap3430() && \ |
399 | (omap3_has_sgx()) && \ | 401 | (!omap3_has_sgx()) && \ |
400 | (!omap3_has_iva())) | 402 | (omap3_has_iva())) |
401 | # define cpu_is_omap3530() (cpu_is_omap3430()) | 403 | # define cpu_is_omap3530() (cpu_is_omap3430()) |
402 | # define cpu_is_omap3505() is_omap3505() | 404 | # define cpu_is_omap3505() is_omap3505() |
403 | # define cpu_is_omap3517() is_omap3517() | 405 | # define cpu_is_omap3517() is_omap3517() |
@@ -408,8 +410,8 @@ IS_OMAP_TYPE(3517, 0x3517) | |||
408 | # if defined(CONFIG_ARCH_OMAP4) | 410 | # if defined(CONFIG_ARCH_OMAP4) |
409 | # undef cpu_is_omap44xx | 411 | # undef cpu_is_omap44xx |
410 | # undef cpu_is_omap443x | 412 | # undef cpu_is_omap443x |
411 | # define cpu_is_omap44xx() 1 | 413 | # define cpu_is_omap44xx() is_omap44xx() |
412 | # define cpu_is_omap443x() 1 | 414 | # define cpu_is_omap443x() is_omap443x() |
413 | # endif | 415 | # endif |
414 | 416 | ||
415 | /* Macros to detect if we have OMAP1 or OMAP2 */ | 417 | /* Macros to detect if we have OMAP1 or OMAP2 */ |
@@ -436,14 +438,15 @@ IS_OMAP_TYPE(3517, 0x3517) | |||
436 | #define OMAP3630_REV_ES1_0 0x36300034 | 438 | #define OMAP3630_REV_ES1_0 0x36300034 |
437 | 439 | ||
438 | #define OMAP35XX_CLASS 0x35000034 | 440 | #define OMAP35XX_CLASS 0x35000034 |
439 | #define OMAP3503_REV(v) (OMAP35XX_CLASS | (0x3503 << 16) | (v << 12)) | 441 | #define OMAP3503_REV(v) (OMAP35XX_CLASS | (0x3503 << 16) | (v << 8)) |
440 | #define OMAP3515_REV(v) (OMAP35XX_CLASS | (0x3515 << 16) | (v << 12)) | 442 | #define OMAP3515_REV(v) (OMAP35XX_CLASS | (0x3515 << 16) | (v << 8)) |
441 | #define OMAP3525_REV(v) (OMAP35XX_CLASS | (0x3525 << 16) | (v << 12)) | 443 | #define OMAP3525_REV(v) (OMAP35XX_CLASS | (0x3525 << 16) | (v << 8)) |
442 | #define OMAP3530_REV(v) (OMAP35XX_CLASS | (0x3530 << 16) | (v << 12)) | 444 | #define OMAP3530_REV(v) (OMAP35XX_CLASS | (0x3530 << 16) | (v << 8)) |
443 | #define OMAP3505_REV(v) (OMAP35XX_CLASS | (0x3505 << 16) | (v << 12)) | 445 | #define OMAP3505_REV(v) (OMAP35XX_CLASS | (0x3505 << 16) | (v << 8)) |
444 | #define OMAP3517_REV(v) (OMAP35XX_CLASS | (0x3517 << 16) | (v << 12)) | 446 | #define OMAP3517_REV(v) (OMAP35XX_CLASS | (0x3517 << 16) | (v << 8)) |
445 | 447 | ||
446 | #define OMAP443X_CLASS 0x44300034 | 448 | #define OMAP443X_CLASS 0x44300044 |
449 | #define OMAP4430_REV_ES1_0 0x44300044 | ||
447 | 450 | ||
448 | /* | 451 | /* |
449 | * omap_chip bits | 452 | * omap_chip bits |
diff --git a/arch/arm/plat-omap/include/plat/dma.h b/arch/arm/plat-omap/include/plat/dma.h index 1c017b29b7e9..4ede9e17a0be 100644 --- a/arch/arm/plat-omap/include/plat/dma.h +++ b/arch/arm/plat-omap/include/plat/dma.h | |||
@@ -401,33 +401,6 @@ | |||
401 | 401 | ||
402 | /*----------------------------------------------------------------------------*/ | 402 | /*----------------------------------------------------------------------------*/ |
403 | 403 | ||
404 | /* Hardware registers for LCD DMA */ | ||
405 | #define OMAP1510_DMA_LCD_BASE (0xfffedb00) | ||
406 | #define OMAP1510_DMA_LCD_CTRL (OMAP1510_DMA_LCD_BASE + 0x00) | ||
407 | #define OMAP1510_DMA_LCD_TOP_F1_L (OMAP1510_DMA_LCD_BASE + 0x02) | ||
408 | #define OMAP1510_DMA_LCD_TOP_F1_U (OMAP1510_DMA_LCD_BASE + 0x04) | ||
409 | #define OMAP1510_DMA_LCD_BOT_F1_L (OMAP1510_DMA_LCD_BASE + 0x06) | ||
410 | #define OMAP1510_DMA_LCD_BOT_F1_U (OMAP1510_DMA_LCD_BASE + 0x08) | ||
411 | |||
412 | #define OMAP1610_DMA_LCD_BASE (0xfffee300) | ||
413 | #define OMAP1610_DMA_LCD_CSDP (OMAP1610_DMA_LCD_BASE + 0xc0) | ||
414 | #define OMAP1610_DMA_LCD_CCR (OMAP1610_DMA_LCD_BASE + 0xc2) | ||
415 | #define OMAP1610_DMA_LCD_CTRL (OMAP1610_DMA_LCD_BASE + 0xc4) | ||
416 | #define OMAP1610_DMA_LCD_TOP_B1_L (OMAP1610_DMA_LCD_BASE + 0xc8) | ||
417 | #define OMAP1610_DMA_LCD_TOP_B1_U (OMAP1610_DMA_LCD_BASE + 0xca) | ||
418 | #define OMAP1610_DMA_LCD_BOT_B1_L (OMAP1610_DMA_LCD_BASE + 0xcc) | ||
419 | #define OMAP1610_DMA_LCD_BOT_B1_U (OMAP1610_DMA_LCD_BASE + 0xce) | ||
420 | #define OMAP1610_DMA_LCD_TOP_B2_L (OMAP1610_DMA_LCD_BASE + 0xd0) | ||
421 | #define OMAP1610_DMA_LCD_TOP_B2_U (OMAP1610_DMA_LCD_BASE + 0xd2) | ||
422 | #define OMAP1610_DMA_LCD_BOT_B2_L (OMAP1610_DMA_LCD_BASE + 0xd4) | ||
423 | #define OMAP1610_DMA_LCD_BOT_B2_U (OMAP1610_DMA_LCD_BASE + 0xd6) | ||
424 | #define OMAP1610_DMA_LCD_SRC_EI_B1 (OMAP1610_DMA_LCD_BASE + 0xd8) | ||
425 | #define OMAP1610_DMA_LCD_SRC_FI_B1_L (OMAP1610_DMA_LCD_BASE + 0xda) | ||
426 | #define OMAP1610_DMA_LCD_SRC_EN_B1 (OMAP1610_DMA_LCD_BASE + 0xe0) | ||
427 | #define OMAP1610_DMA_LCD_SRC_FN_B1 (OMAP1610_DMA_LCD_BASE + 0xe4) | ||
428 | #define OMAP1610_DMA_LCD_LCH_CTRL (OMAP1610_DMA_LCD_BASE + 0xea) | ||
429 | #define OMAP1610_DMA_LCD_SRC_FI_B1_U (OMAP1610_DMA_LCD_BASE + 0xf4) | ||
430 | |||
431 | #define OMAP1_DMA_TOUT_IRQ (1 << 0) | 404 | #define OMAP1_DMA_TOUT_IRQ (1 << 0) |
432 | #define OMAP_DMA_DROP_IRQ (1 << 1) | 405 | #define OMAP_DMA_DROP_IRQ (1 << 1) |
433 | #define OMAP_DMA_HALF_IRQ (1 << 2) | 406 | #define OMAP_DMA_HALF_IRQ (1 << 2) |
@@ -441,6 +414,8 @@ | |||
441 | #define OMAP2_DMA_SUPERVISOR_ERR_IRQ (1 << 10) | 414 | #define OMAP2_DMA_SUPERVISOR_ERR_IRQ (1 << 10) |
442 | #define OMAP2_DMA_MISALIGNED_ERR_IRQ (1 << 11) | 415 | #define OMAP2_DMA_MISALIGNED_ERR_IRQ (1 << 11) |
443 | 416 | ||
417 | #define OMAP_DMA_CCR_EN (1 << 7) | ||
418 | |||
444 | #define OMAP_DMA_DATA_TYPE_S8 0x00 | 419 | #define OMAP_DMA_DATA_TYPE_S8 0x00 |
445 | #define OMAP_DMA_DATA_TYPE_S16 0x01 | 420 | #define OMAP_DMA_DATA_TYPE_S16 0x01 |
446 | #define OMAP_DMA_DATA_TYPE_S32 0x02 | 421 | #define OMAP_DMA_DATA_TYPE_S32 0x02 |
@@ -503,14 +478,6 @@ | |||
503 | #define DMA_CH_PRIO_HIGH 0x1 | 478 | #define DMA_CH_PRIO_HIGH 0x1 |
504 | #define DMA_CH_PRIO_LOW 0x0 /* Def */ | 479 | #define DMA_CH_PRIO_LOW 0x0 /* Def */ |
505 | 480 | ||
506 | /* LCD DMA block numbers */ | ||
507 | enum { | ||
508 | OMAP_LCD_DMA_B1_TOP, | ||
509 | OMAP_LCD_DMA_B1_BOTTOM, | ||
510 | OMAP_LCD_DMA_B2_TOP, | ||
511 | OMAP_LCD_DMA_B2_BOTTOM | ||
512 | }; | ||
513 | |||
514 | enum omap_dma_burst_mode { | 481 | enum omap_dma_burst_mode { |
515 | OMAP_DMA_DATA_BURST_DIS = 0, | 482 | OMAP_DMA_DATA_BURST_DIS = 0, |
516 | OMAP_DMA_DATA_BURST_4, | 483 | OMAP_DMA_DATA_BURST_4, |
@@ -661,20 +628,13 @@ extern int omap_modify_dma_chain_params(int chain_id, | |||
661 | extern int omap_dma_chain_status(int chain_id); | 628 | extern int omap_dma_chain_status(int chain_id); |
662 | #endif | 629 | #endif |
663 | 630 | ||
664 | /* LCD DMA functions */ | 631 | #if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_FB_OMAP) |
665 | extern int omap_request_lcd_dma(void (*callback)(u16 status, void *data), | 632 | #include <mach/lcd_dma.h> |
666 | void *data); | 633 | #else |
667 | extern void omap_free_lcd_dma(void); | 634 | static inline int omap_lcd_dma_running(void) |
668 | extern void omap_setup_lcd_dma(void); | 635 | { |
669 | extern void omap_enable_lcd_dma(void); | 636 | return 0; |
670 | extern void omap_stop_lcd_dma(void); | 637 | } |
671 | extern void omap_set_lcd_dma_ext_controller(int external); | 638 | #endif |
672 | extern void omap_set_lcd_dma_single_transfer(int single); | ||
673 | extern void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres, | ||
674 | int data_type); | ||
675 | extern void omap_set_lcd_dma_b1_rotation(int rotate); | ||
676 | extern void omap_set_lcd_dma_b1_vxres(unsigned long vxres); | ||
677 | extern void omap_set_lcd_dma_b1_mirror(int mirror); | ||
678 | extern void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale); | ||
679 | 639 | ||
680 | #endif /* __ASM_ARCH_DMA_H */ | 640 | #endif /* __ASM_ARCH_DMA_H */ |
diff --git a/arch/arm/plat-omap/include/plat/gpmc.h b/arch/arm/plat-omap/include/plat/gpmc.h index 696e0ca051b7..e081338e0b23 100644 --- a/arch/arm/plat-omap/include/plat/gpmc.h +++ b/arch/arm/plat-omap/include/plat/gpmc.h | |||
@@ -45,7 +45,7 @@ | |||
45 | #define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1) | 45 | #define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1) |
46 | #define GPMC_CONFIG1_DEVICETYPE(val) ((val & 3) << 10) | 46 | #define GPMC_CONFIG1_DEVICETYPE(val) ((val & 3) << 10) |
47 | #define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0) | 47 | #define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0) |
48 | #define GPMC_CONFIG1_DEVICETYPE_NAND GPMC_CONFIG1_DEVICETYPE(1) | 48 | #define GPMC_CONFIG1_DEVICETYPE_NAND GPMC_CONFIG1_DEVICETYPE(2) |
49 | #define GPMC_CONFIG1_MUXADDDATA (1 << 9) | 49 | #define GPMC_CONFIG1_MUXADDDATA (1 << 9) |
50 | #define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4) | 50 | #define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4) |
51 | #define GPMC_CONFIG1_FCLK_DIV(val) (val & 3) | 51 | #define GPMC_CONFIG1_FCLK_DIV(val) (val & 3) |
diff --git a/arch/arm/plat-omap/include/plat/i2c.h b/arch/arm/plat-omap/include/plat/i2c.h new file mode 100644 index 000000000000..585d9ca68b97 --- /dev/null +++ b/arch/arm/plat-omap/include/plat/i2c.h | |||
@@ -0,0 +1,39 @@ | |||
1 | /* | ||
2 | * Helper module for board specific I2C bus registration | ||
3 | * | ||
4 | * Copyright (C) 2009 Nokia Corporation. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or | ||
7 | * modify it under the terms of the GNU General Public License | ||
8 | * version 2 as published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope that it will be useful, but | ||
11 | * WITHOUT ANY WARRANTY; without even the implied warranty of | ||
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | ||
13 | * General Public License for more details. | ||
14 | * | ||
15 | * You should have received a copy of the GNU General Public License | ||
16 | * along with this program; if not, write to the Free Software | ||
17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | ||
18 | * 02110-1301 USA | ||
19 | * | ||
20 | */ | ||
21 | |||
22 | #include <linux/i2c.h> | ||
23 | |||
24 | #if defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE) | ||
25 | extern int omap_register_i2c_bus(int bus_id, u32 clkrate, | ||
26 | struct i2c_board_info const *info, | ||
27 | unsigned len); | ||
28 | #else | ||
29 | static inline int omap_register_i2c_bus(int bus_id, u32 clkrate, | ||
30 | struct i2c_board_info const *info, | ||
31 | unsigned len) | ||
32 | { | ||
33 | return 0; | ||
34 | } | ||
35 | #endif | ||
36 | |||
37 | int omap_plat_register_i2c_bus(int bus_id, u32 clkrate, | ||
38 | struct i2c_board_info const *info, | ||
39 | unsigned len); | ||
diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h index ce5dd2d1dc21..97d6c50c3dcb 100644 --- a/arch/arm/plat-omap/include/plat/irqs.h +++ b/arch/arm/plat-omap/include/plat/irqs.h | |||
@@ -472,8 +472,22 @@ | |||
472 | #endif | 472 | #endif |
473 | #define TWL4030_GPIO_IRQ_END (TWL4030_GPIO_IRQ_BASE + TWL4030_GPIO_NR_IRQS) | 473 | #define TWL4030_GPIO_IRQ_END (TWL4030_GPIO_IRQ_BASE + TWL4030_GPIO_NR_IRQS) |
474 | 474 | ||
475 | #define TWL6030_IRQ_BASE (OMAP_FPGA_IRQ_END) | ||
476 | #ifdef CONFIG_TWL4030_CORE | ||
477 | #define TWL6030_BASE_NR_IRQS 20 | ||
478 | #else | ||
479 | #define TWL6030_BASE_NR_IRQS 0 | ||
480 | #endif | ||
481 | #define TWL6030_IRQ_END (TWL6030_IRQ_BASE + TWL6030_BASE_NR_IRQS) | ||
482 | |||
475 | /* Total number of interrupts depends on the enabled blocks above */ | 483 | /* Total number of interrupts depends on the enabled blocks above */ |
476 | #define NR_IRQS TWL4030_GPIO_IRQ_END | 484 | #if (TWL4030_GPIO_IRQ_END > TWL6030_IRQ_END) |
485 | #define TWL_IRQ_END TWL4030_GPIO_IRQ_END | ||
486 | #else | ||
487 | #define TWL_IRQ_END TWL6030_IRQ_END | ||
488 | #endif | ||
489 | |||
490 | #define NR_IRQS TWL_IRQ_END | ||
477 | 491 | ||
478 | #define OMAP_IRQ_BIT(irq) (1 << ((irq) % 32)) | 492 | #define OMAP_IRQ_BIT(irq) (1 << ((irq) % 32)) |
479 | 493 | ||
diff --git a/arch/arm/plat-omap/include/plat/mux.h b/arch/arm/plat-omap/include/plat/mux.h index ba77de601501..8f069cc80350 100644 --- a/arch/arm/plat-omap/include/plat/mux.h +++ b/arch/arm/plat-omap/include/plat/mux.h | |||
@@ -130,58 +130,11 @@ | |||
130 | #define OMAP2_PULL_UP (1 << 4) | 130 | #define OMAP2_PULL_UP (1 << 4) |
131 | #define OMAP2_ALTELECTRICALSEL (1 << 5) | 131 | #define OMAP2_ALTELECTRICALSEL (1 << 5) |
132 | 132 | ||
133 | /* 34xx specific mux bit defines */ | ||
134 | #define OMAP3_INPUT_EN (1 << 8) | ||
135 | #define OMAP3_OFF_EN (1 << 9) | ||
136 | #define OMAP3_OFFOUT_EN (1 << 10) | ||
137 | #define OMAP3_OFFOUT_VAL (1 << 11) | ||
138 | #define OMAP3_OFF_PULL_EN (1 << 12) | ||
139 | #define OMAP3_OFF_PULL_UP (1 << 13) | ||
140 | #define OMAP3_WAKEUP_EN (1 << 14) | ||
141 | |||
142 | /* 34xx mux mode options for each pin. See TRM for options */ | ||
143 | #define OMAP34XX_MUX_MODE0 0 | ||
144 | #define OMAP34XX_MUX_MODE1 1 | ||
145 | #define OMAP34XX_MUX_MODE2 2 | ||
146 | #define OMAP34XX_MUX_MODE3 3 | ||
147 | #define OMAP34XX_MUX_MODE4 4 | ||
148 | #define OMAP34XX_MUX_MODE5 5 | ||
149 | #define OMAP34XX_MUX_MODE6 6 | ||
150 | #define OMAP34XX_MUX_MODE7 7 | ||
151 | |||
152 | /* 34xx active pin states */ | ||
153 | #define OMAP34XX_PIN_OUTPUT 0 | ||
154 | #define OMAP34XX_PIN_INPUT OMAP3_INPUT_EN | ||
155 | #define OMAP34XX_PIN_INPUT_PULLUP (OMAP2_PULL_ENA | OMAP3_INPUT_EN \ | ||
156 | | OMAP2_PULL_UP) | ||
157 | #define OMAP34XX_PIN_INPUT_PULLDOWN (OMAP2_PULL_ENA | OMAP3_INPUT_EN) | ||
158 | |||
159 | /* 34xx off mode states */ | ||
160 | #define OMAP34XX_PIN_OFF_NONE 0 | ||
161 | #define OMAP34XX_PIN_OFF_OUTPUT_HIGH (OMAP3_OFF_EN | OMAP3_OFFOUT_EN \ | ||
162 | | OMAP3_OFFOUT_VAL) | ||
163 | #define OMAP34XX_PIN_OFF_OUTPUT_LOW (OMAP3_OFF_EN | OMAP3_OFFOUT_EN) | ||
164 | #define OMAP34XX_PIN_OFF_INPUT_PULLUP (OMAP3_OFF_EN | OMAP3_OFF_PULL_EN \ | ||
165 | | OMAP3_OFF_PULL_UP) | ||
166 | #define OMAP34XX_PIN_OFF_INPUT_PULLDOWN (OMAP3_OFF_EN | OMAP3_OFF_PULL_EN) | ||
167 | #define OMAP34XX_PIN_OFF_WAKEUPENABLE OMAP3_WAKEUP_EN | ||
168 | |||
169 | #define MUX_CFG_34XX(desc, reg_offset, mux_value) { \ | ||
170 | .name = desc, \ | ||
171 | .debug = 0, \ | ||
172 | .mux_reg = reg_offset, \ | ||
173 | .mux_val = mux_value \ | ||
174 | }, | ||
175 | |||
176 | struct pin_config { | 133 | struct pin_config { |
177 | char *name; | 134 | char *name; |
178 | const unsigned int mux_reg; | 135 | const unsigned int mux_reg; |
179 | unsigned char debug; | 136 | unsigned char debug; |
180 | 137 | ||
181 | #if defined(CONFIG_ARCH_OMAP34XX) | ||
182 | u16 mux_val; /* Wake-up, off mode, pull, mux mode */ | ||
183 | #endif | ||
184 | |||
185 | #if defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP24XX) | 138 | #if defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP24XX) |
186 | const unsigned char mask_offset; | 139 | const unsigned char mask_offset; |
187 | const unsigned char mask; | 140 | const unsigned char mask; |
@@ -219,11 +172,17 @@ enum omap7xx_index { | |||
219 | AA17_7XX_USB_DM, | 172 | AA17_7XX_USB_DM, |
220 | W16_7XX_USB_PU_EN, | 173 | W16_7XX_USB_PU_EN, |
221 | W17_7XX_USB_VBUSI, | 174 | W17_7XX_USB_VBUSI, |
175 | W18_7XX_USB_DMCK_OUT, | ||
176 | W19_7XX_USB_DCRST, | ||
222 | 177 | ||
223 | /* MMC */ | 178 | /* MMC */ |
224 | MMC_7XX_CMD, | 179 | MMC_7XX_CMD, |
225 | MMC_7XX_CLK, | 180 | MMC_7XX_CLK, |
226 | MMC_7XX_DAT0, | 181 | MMC_7XX_DAT0, |
182 | |||
183 | /* I2C */ | ||
184 | I2C_7XX_SCL, | ||
185 | I2C_7XX_SDA, | ||
227 | }; | 186 | }; |
228 | 187 | ||
229 | enum omap1xxx_index { | 188 | enum omap1xxx_index { |
@@ -681,181 +640,6 @@ enum omap24xx_index { | |||
681 | 640 | ||
682 | }; | 641 | }; |
683 | 642 | ||
684 | enum omap34xx_index { | ||
685 | /* 34xx I2C */ | ||
686 | K21_34XX_I2C1_SCL, | ||
687 | J21_34XX_I2C1_SDA, | ||
688 | AF15_34XX_I2C2_SCL, | ||
689 | AE15_34XX_I2C2_SDA, | ||
690 | AF14_34XX_I2C3_SCL, | ||
691 | AG14_34XX_I2C3_SDA, | ||
692 | AD26_34XX_I2C4_SCL, | ||
693 | AE26_34XX_I2C4_SDA, | ||
694 | |||
695 | /* PHY - HSUSB: 12-pin ULPI PHY: Port 1*/ | ||
696 | Y8_3430_USB1HS_PHY_CLK, | ||
697 | Y9_3430_USB1HS_PHY_STP, | ||
698 | AA14_3430_USB1HS_PHY_DIR, | ||
699 | AA11_3430_USB1HS_PHY_NXT, | ||
700 | W13_3430_USB1HS_PHY_DATA0, | ||
701 | W12_3430_USB1HS_PHY_DATA1, | ||
702 | W11_3430_USB1HS_PHY_DATA2, | ||
703 | Y11_3430_USB1HS_PHY_DATA3, | ||
704 | W9_3430_USB1HS_PHY_DATA4, | ||
705 | Y12_3430_USB1HS_PHY_DATA5, | ||
706 | W8_3430_USB1HS_PHY_DATA6, | ||
707 | Y13_3430_USB1HS_PHY_DATA7, | ||
708 | |||
709 | /* PHY - HSUSB: 12-pin ULPI PHY: Port 2*/ | ||
710 | AA8_3430_USB2HS_PHY_CLK, | ||
711 | AA10_3430_USB2HS_PHY_STP, | ||
712 | AA9_3430_USB2HS_PHY_DIR, | ||
713 | AB11_3430_USB2HS_PHY_NXT, | ||
714 | AB10_3430_USB2HS_PHY_DATA0, | ||
715 | AB9_3430_USB2HS_PHY_DATA1, | ||
716 | W3_3430_USB2HS_PHY_DATA2, | ||
717 | T4_3430_USB2HS_PHY_DATA3, | ||
718 | T3_3430_USB2HS_PHY_DATA4, | ||
719 | R3_3430_USB2HS_PHY_DATA5, | ||
720 | R4_3430_USB2HS_PHY_DATA6, | ||
721 | T2_3430_USB2HS_PHY_DATA7, | ||
722 | |||
723 | |||
724 | /* TLL - HSUSB: 12-pin TLL Port 1*/ | ||
725 | Y8_3430_USB1HS_TLL_CLK, | ||
726 | Y9_3430_USB1HS_TLL_STP, | ||
727 | AA14_3430_USB1HS_TLL_DIR, | ||
728 | AA11_3430_USB1HS_TLL_NXT, | ||
729 | W13_3430_USB1HS_TLL_DATA0, | ||
730 | W12_3430_USB1HS_TLL_DATA1, | ||
731 | W11_3430_USB1HS_TLL_DATA2, | ||
732 | Y11_3430_USB1HS_TLL_DATA3, | ||
733 | W9_3430_USB1HS_TLL_DATA4, | ||
734 | Y12_3430_USB1HS_TLL_DATA5, | ||
735 | W8_3430_USB1HS_TLL_DATA6, | ||
736 | Y13_3430_USB1HS_TLL_DATA7, | ||
737 | |||
738 | /* TLL - HSUSB: 12-pin TLL Port 2*/ | ||
739 | AA8_3430_USB2HS_TLL_CLK, | ||
740 | AA10_3430_USB2HS_TLL_STP, | ||
741 | AA9_3430_USB2HS_TLL_DIR, | ||
742 | AB11_3430_USB2HS_TLL_NXT, | ||
743 | AB10_3430_USB2HS_TLL_DATA0, | ||
744 | AB9_3430_USB2HS_TLL_DATA1, | ||
745 | W3_3430_USB2HS_TLL_DATA2, | ||
746 | T4_3430_USB2HS_TLL_DATA3, | ||
747 | T3_3430_USB2HS_TLL_DATA4, | ||
748 | R3_3430_USB2HS_TLL_DATA5, | ||
749 | R4_3430_USB2HS_TLL_DATA6, | ||
750 | T2_3430_USB2HS_TLL_DATA7, | ||
751 | |||
752 | /* TLL - HSUSB: 12-pin TLL Port 3*/ | ||
753 | AA6_3430_USB3HS_TLL_CLK, | ||
754 | AB3_3430_USB3HS_TLL_STP, | ||
755 | AA3_3430_USB3HS_TLL_DIR, | ||
756 | Y3_3430_USB3HS_TLL_NXT, | ||
757 | AA5_3430_USB3HS_TLL_DATA0, | ||
758 | Y4_3430_USB3HS_TLL_DATA1, | ||
759 | Y5_3430_USB3HS_TLL_DATA2, | ||
760 | W5_3430_USB3HS_TLL_DATA3, | ||
761 | AB12_3430_USB3HS_TLL_DATA4, | ||
762 | AB13_3430_USB3HS_TLL_DATA5, | ||
763 | AA13_3430_USB3HS_TLL_DATA6, | ||
764 | AA12_3430_USB3HS_TLL_DATA7, | ||
765 | |||
766 | /* PHY FSUSB: FS Serial for Port 1 (multiple PHY modes supported) */ | ||
767 | AF10_3430_USB1FS_PHY_MM1_RXDP, | ||
768 | AG9_3430_USB1FS_PHY_MM1_RXDM, | ||
769 | W13_3430_USB1FS_PHY_MM1_RXRCV, | ||
770 | W12_3430_USB1FS_PHY_MM1_TXSE0, | ||
771 | W11_3430_USB1FS_PHY_MM1_TXDAT, | ||
772 | Y11_3430_USB1FS_PHY_MM1_TXEN_N, | ||
773 | |||
774 | /* PHY FSUSB: FS Serial for Port 2 (multiple PHY modes supported) */ | ||
775 | AF7_3430_USB2FS_PHY_MM2_RXDP, | ||
776 | AH7_3430_USB2FS_PHY_MM2_RXDM, | ||
777 | AB10_3430_USB2FS_PHY_MM2_RXRCV, | ||
778 | AB9_3430_USB2FS_PHY_MM2_TXSE0, | ||
779 | W3_3430_USB2FS_PHY_MM2_TXDAT, | ||
780 | T4_3430_USB2FS_PHY_MM2_TXEN_N, | ||
781 | |||
782 | /* PHY FSUSB: FS Serial for Port 3 (multiple PHY modes supported) */ | ||
783 | AH3_3430_USB3FS_PHY_MM3_RXDP, | ||
784 | AE3_3430_USB3FS_PHY_MM3_RXDM, | ||
785 | AD1_3430_USB3FS_PHY_MM3_RXRCV, | ||
786 | AE1_3430_USB3FS_PHY_MM3_TXSE0, | ||
787 | AD2_3430_USB3FS_PHY_MM3_TXDAT, | ||
788 | AC1_3430_USB3FS_PHY_MM3_TXEN_N, | ||
789 | |||
790 | /* 34xx GPIO | ||
791 | * - normally these are bidirectional, no internal pullup/pulldown | ||
792 | * - "_UP" suffix (GPIO3_UP) if internal pullup is configured | ||
793 | * - "_DOWN" suffix (GPIO3_DOWN) with internal pulldown | ||
794 | * - "_OUT" suffix (GPIO3_OUT) for output-only pins (unlike 24xx) | ||
795 | */ | ||
796 | AF26_34XX_GPIO0, | ||
797 | AF22_34XX_GPIO9, | ||
798 | AG9_34XX_GPIO23, | ||
799 | AH8_34XX_GPIO29, | ||
800 | U8_34XX_GPIO54_OUT, | ||
801 | U8_34XX_GPIO54_DOWN, | ||
802 | L8_34XX_GPIO63, | ||
803 | G25_34XX_GPIO86_OUT, | ||
804 | AG4_34XX_GPIO134_OUT, | ||
805 | AF4_34XX_GPIO135_OUT, | ||
806 | AE4_34XX_GPIO136_OUT, | ||
807 | AF6_34XX_GPIO140_UP, | ||
808 | AE6_34XX_GPIO141, | ||
809 | AF5_34XX_GPIO142, | ||
810 | AE5_34XX_GPIO143, | ||
811 | H19_34XX_GPIO164_OUT, | ||
812 | J25_34XX_GPIO170, | ||
813 | |||
814 | /* OMAP3 SDRC CKE signals to SDR/DDR ram chips */ | ||
815 | H16_34XX_SDRC_CKE0, | ||
816 | H17_34XX_SDRC_CKE1, | ||
817 | |||
818 | /* MMC1 */ | ||
819 | N28_3430_MMC1_CLK, | ||
820 | M27_3430_MMC1_CMD, | ||
821 | N27_3430_MMC1_DAT0, | ||
822 | N26_3430_MMC1_DAT1, | ||
823 | N25_3430_MMC1_DAT2, | ||
824 | P28_3430_MMC1_DAT3, | ||
825 | P27_3430_MMC1_DAT4, | ||
826 | P26_3430_MMC1_DAT5, | ||
827 | R27_3430_MMC1_DAT6, | ||
828 | R25_3430_MMC1_DAT7, | ||
829 | |||
830 | /* MMC2 */ | ||
831 | AE2_3430_MMC2_CLK, | ||
832 | AG5_3430_MMC2_CMD, | ||
833 | AH5_3430_MMC2_DAT0, | ||
834 | AH4_3430_MMC2_DAT1, | ||
835 | AG4_3430_MMC2_DAT2, | ||
836 | AF4_3430_MMC2_DAT3, | ||
837 | AE4_3430_MMC2_DAT4, | ||
838 | AH3_3430_MMC2_DAT5, | ||
839 | AF3_3430_MMC2_DAT6, | ||
840 | AE3_3430_MMC2_DAT7, | ||
841 | |||
842 | /* MMC3 */ | ||
843 | AF10_3430_MMC3_CLK, | ||
844 | AC3_3430_MMC3_CMD, | ||
845 | AE11_3430_MMC3_DAT0, | ||
846 | AH9_3430_MMC3_DAT1, | ||
847 | AF13_3430_MMC3_DAT2, | ||
848 | AF13_3430_MMC3_DAT3, | ||
849 | |||
850 | /* SYS_NIRQ T2 INT1 */ | ||
851 | AF26_34XX_SYS_NIRQ, | ||
852 | |||
853 | /* EHCI GPIO's for OMAP3EVM (Rev >= E) */ | ||
854 | AH14_34XX_GPIO21, | ||
855 | AF9_34XX_GPIO22, | ||
856 | U3_34XX_GPIO61, | ||
857 | }; | ||
858 | |||
859 | struct omap_mux_cfg { | 643 | struct omap_mux_cfg { |
860 | struct pin_config *pins; | 644 | struct pin_config *pins; |
861 | unsigned long size; | 645 | unsigned long size; |
@@ -865,14 +649,14 @@ struct omap_mux_cfg { | |||
865 | #ifdef CONFIG_OMAP_MUX | 649 | #ifdef CONFIG_OMAP_MUX |
866 | /* setup pin muxing in Linux */ | 650 | /* setup pin muxing in Linux */ |
867 | extern int omap1_mux_init(void); | 651 | extern int omap1_mux_init(void); |
868 | extern int omap2_mux_init(void); | ||
869 | extern int omap_mux_register(struct omap_mux_cfg *); | 652 | extern int omap_mux_register(struct omap_mux_cfg *); |
870 | extern int omap_cfg_reg(unsigned long reg_cfg); | 653 | extern int omap_cfg_reg(unsigned long reg_cfg); |
871 | #else | 654 | #else |
872 | /* boot loader does it all (no warnings from CONFIG_OMAP_MUX_WARNINGS) */ | 655 | /* boot loader does it all (no warnings from CONFIG_OMAP_MUX_WARNINGS) */ |
873 | static inline int omap1_mux_init(void) { return 0; } | 656 | static inline int omap1_mux_init(void) { return 0; } |
874 | static inline int omap2_mux_init(void) { return 0; } | ||
875 | static inline int omap_cfg_reg(unsigned long reg_cfg) { return 0; } | 657 | static inline int omap_cfg_reg(unsigned long reg_cfg) { return 0; } |
876 | #endif | 658 | #endif |
877 | 659 | ||
660 | extern int omap2_mux_init(void); | ||
661 | |||
878 | #endif | 662 | #endif |
diff --git a/arch/arm/plat-omap/include/plat/omap44xx.h b/arch/arm/plat-omap/include/plat/omap44xx.h index e52902a15c1a..ef870de43c29 100644 --- a/arch/arm/plat-omap/include/plat/omap44xx.h +++ b/arch/arm/plat-omap/include/plat/omap44xx.h | |||
@@ -26,8 +26,10 @@ | |||
26 | #define OMAP44XX_EMIF2_BASE 0x4d000000 | 26 | #define OMAP44XX_EMIF2_BASE 0x4d000000 |
27 | #define OMAP44XX_DMM_BASE 0x4e000000 | 27 | #define OMAP44XX_DMM_BASE 0x4e000000 |
28 | #define OMAP4430_32KSYNCT_BASE 0x4a304000 | 28 | #define OMAP4430_32KSYNCT_BASE 0x4a304000 |
29 | #define OMAP4430_CM_BASE 0x4a004000 | 29 | #define OMAP4430_CM1_BASE 0x4a004000 |
30 | #define OMAP4430_PRM_BASE 0x48306000 | 30 | #define OMAP4430_CM_BASE OMAP4430_CM1_BASE |
31 | #define OMAP4430_CM2_BASE 0x4a008000 | ||
32 | #define OMAP4430_PRM_BASE 0x4a306000 | ||
31 | #define OMAP44XX_GPMC_BASE 0x50000000 | 33 | #define OMAP44XX_GPMC_BASE 0x50000000 |
32 | #define OMAP443X_SCM_BASE 0x4a002000 | 34 | #define OMAP443X_SCM_BASE 0x4a002000 |
33 | #define OMAP443X_CTRL_BASE OMAP443X_SCM_BASE | 35 | #define OMAP443X_CTRL_BASE OMAP443X_SCM_BASE |
diff --git a/arch/arm/plat-omap/include/plat/omap_device.h b/arch/arm/plat-omap/include/plat/omap_device.h index 11a9773a4e7f..dc1fac1d805c 100644 --- a/arch/arm/plat-omap/include/plat/omap_device.h +++ b/arch/arm/plat-omap/include/plat/omap_device.h | |||
@@ -50,8 +50,8 @@ | |||
50 | * @pm_lats: ptr to an omap_device_pm_latency table | 50 | * @pm_lats: ptr to an omap_device_pm_latency table |
51 | * @pm_lats_cnt: ARRAY_SIZE() of what is passed to @pm_lats | 51 | * @pm_lats_cnt: ARRAY_SIZE() of what is passed to @pm_lats |
52 | * @pm_lat_level: array index of the last odpl entry executed - -1 if never | 52 | * @pm_lat_level: array index of the last odpl entry executed - -1 if never |
53 | * @dev_wakeup_lat: dev wakeup latency in microseconds | 53 | * @dev_wakeup_lat: dev wakeup latency in nanoseconds |
54 | * @_dev_wakeup_lat_limit: dev wakeup latency limit in usec - set by OMAP PM | 54 | * @_dev_wakeup_lat_limit: dev wakeup latency limit in nsec - set by OMAP PM |
55 | * @_state: one of OMAP_DEVICE_STATE_* (see above) | 55 | * @_state: one of OMAP_DEVICE_STATE_* (see above) |
56 | * @flags: device flags | 56 | * @flags: device flags |
57 | * | 57 | * |
@@ -137,5 +137,7 @@ struct omap_device_pm_latency { | |||
137 | }; | 137 | }; |
138 | 138 | ||
139 | 139 | ||
140 | #endif | 140 | /* Get omap_device pointer from platform_device pointer */ |
141 | #define to_omap_device(x) container_of((x), struct omap_device, pdev) | ||
141 | 142 | ||
143 | #endif | ||
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h index dbdd123eca16..007935a921ea 100644 --- a/arch/arm/plat-omap/include/plat/omap_hwmod.h +++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h | |||
@@ -50,6 +50,8 @@ struct omap_device; | |||
50 | #define SYSC_ENAWAKEUP_MASK (1 << SYSC_ENAWAKEUP_SHIFT) | 50 | #define SYSC_ENAWAKEUP_MASK (1 << SYSC_ENAWAKEUP_SHIFT) |
51 | #define SYSC_SOFTRESET_SHIFT 1 | 51 | #define SYSC_SOFTRESET_SHIFT 1 |
52 | #define SYSC_SOFTRESET_MASK (1 << SYSC_SOFTRESET_SHIFT) | 52 | #define SYSC_SOFTRESET_MASK (1 << SYSC_SOFTRESET_SHIFT) |
53 | #define SYSC_AUTOIDLE_SHIFT 0 | ||
54 | #define SYSC_AUTOIDLE_MASK (1 << SYSC_AUTOIDLE_SHIFT) | ||
53 | 55 | ||
54 | /* OCP SYSSTATUS bit shifts/masks */ | 56 | /* OCP SYSSTATUS bit shifts/masks */ |
55 | #define SYSS_RESETDONE_SHIFT 0 | 57 | #define SYSS_RESETDONE_SHIFT 0 |
@@ -62,7 +64,21 @@ struct omap_device; | |||
62 | 64 | ||
63 | 65 | ||
64 | /** | 66 | /** |
65 | * struct omap_hwmod_dma_info - MPU address space handled by the hwmod | 67 | * struct omap_hwmod_irq_info - MPU IRQs used by the hwmod |
68 | * @name: name of the IRQ channel (module local name) | ||
69 | * @irq_ch: IRQ channel ID | ||
70 | * | ||
71 | * @name should be something short, e.g., "tx" or "rx". It is for use | ||
72 | * by platform_get_resource_byname(). It is defined locally to the | ||
73 | * hwmod. | ||
74 | */ | ||
75 | struct omap_hwmod_irq_info { | ||
76 | const char *name; | ||
77 | u16 irq; | ||
78 | }; | ||
79 | |||
80 | /** | ||
81 | * struct omap_hwmod_dma_info - DMA channels used by the hwmod | ||
66 | * @name: name of the DMA channel (module local name) | 82 | * @name: name of the DMA channel (module local name) |
67 | * @dma_ch: DMA channel ID | 83 | * @dma_ch: DMA channel ID |
68 | * | 84 | * |
@@ -294,13 +310,17 @@ struct omap_hwmod_omap4_prcm { | |||
294 | * SDRAM controller, etc. | 310 | * SDRAM controller, etc. |
295 | * HWMOD_INIT_NO_IDLE: don't idle this module at boot - important for SDRAM | 311 | * HWMOD_INIT_NO_IDLE: don't idle this module at boot - important for SDRAM |
296 | * controller, etc. | 312 | * controller, etc. |
313 | * HWMOD_NO_AUTOIDLE: disable module autoidle (OCP_SYSCONFIG.AUTOIDLE) | ||
314 | * when module is enabled, rather than the default, which is to | ||
315 | * enable autoidle | ||
297 | * HWMOD_SET_DEFAULT_CLOCKACT: program CLOCKACTIVITY bits at startup | 316 | * HWMOD_SET_DEFAULT_CLOCKACT: program CLOCKACTIVITY bits at startup |
298 | */ | 317 | */ |
299 | #define HWMOD_SWSUP_SIDLE (1 << 0) | 318 | #define HWMOD_SWSUP_SIDLE (1 << 0) |
300 | #define HWMOD_SWSUP_MSTANDBY (1 << 1) | 319 | #define HWMOD_SWSUP_MSTANDBY (1 << 1) |
301 | #define HWMOD_INIT_NO_RESET (1 << 2) | 320 | #define HWMOD_INIT_NO_RESET (1 << 2) |
302 | #define HWMOD_INIT_NO_IDLE (1 << 3) | 321 | #define HWMOD_INIT_NO_IDLE (1 << 3) |
303 | #define HWMOD_SET_DEFAULT_CLOCKACT (1 << 4) | 322 | #define HWMOD_NO_OCP_AUTOIDLE (1 << 4) |
323 | #define HWMOD_SET_DEFAULT_CLOCKACT (1 << 5) | ||
304 | 324 | ||
305 | /* | 325 | /* |
306 | * omap_hwmod._int_flags definitions | 326 | * omap_hwmod._int_flags definitions |
@@ -373,7 +393,7 @@ struct omap_hwmod_omap4_prcm { | |||
373 | struct omap_hwmod { | 393 | struct omap_hwmod { |
374 | const char *name; | 394 | const char *name; |
375 | struct omap_device *od; | 395 | struct omap_device *od; |
376 | u8 *mpu_irqs; | 396 | struct omap_hwmod_irq_info *mpu_irqs; |
377 | struct omap_hwmod_dma_info *sdma_chs; | 397 | struct omap_hwmod_dma_info *sdma_chs; |
378 | union { | 398 | union { |
379 | struct omap_hwmod_omap2_prcm omap2; | 399 | struct omap_hwmod_omap2_prcm omap2; |
diff --git a/arch/arm/plat-omap/include/plat/powerdomain.h b/arch/arm/plat-omap/include/plat/powerdomain.h index 3d45ee1d3cf4..0b960051eaed 100644 --- a/arch/arm/plat-omap/include/plat/powerdomain.h +++ b/arch/arm/plat-omap/include/plat/powerdomain.h | |||
@@ -28,6 +28,8 @@ | |||
28 | #define PWRDM_POWER_INACTIVE 0x2 | 28 | #define PWRDM_POWER_INACTIVE 0x2 |
29 | #define PWRDM_POWER_ON 0x3 | 29 | #define PWRDM_POWER_ON 0x3 |
30 | 30 | ||
31 | #define PWRDM_MAX_PWRSTS 4 | ||
32 | |||
31 | /* Powerdomain allowable state bitfields */ | 33 | /* Powerdomain allowable state bitfields */ |
32 | #define PWRSTS_OFF_ON ((1 << PWRDM_POWER_OFF) | \ | 34 | #define PWRSTS_OFF_ON ((1 << PWRDM_POWER_OFF) | \ |
33 | (1 << PWRDM_POWER_ON)) | 35 | (1 << PWRDM_POWER_ON)) |
@@ -40,7 +42,10 @@ | |||
40 | 42 | ||
41 | /* Powerdomain flags */ | 43 | /* Powerdomain flags */ |
42 | #define PWRDM_HAS_HDWR_SAR (1 << 0) /* hardware save-and-restore support */ | 44 | #define PWRDM_HAS_HDWR_SAR (1 << 0) /* hardware save-and-restore support */ |
43 | 45 | #define PWRDM_HAS_MPU_QUIRK (1 << 1) /* MPU pwr domain has MEM bank 0 bits | |
46 | * in MEM bank 1 position. This is | ||
47 | * true for OMAP3430 | ||
48 | */ | ||
44 | 49 | ||
45 | /* | 50 | /* |
46 | * Number of memory banks that are power-controllable. On OMAP3430, the | 51 | * Number of memory banks that are power-controllable. On OMAP3430, the |
@@ -85,15 +90,15 @@ struct powerdomain { | |||
85 | /* Used to represent the OMAP chip types containing this pwrdm */ | 90 | /* Used to represent the OMAP chip types containing this pwrdm */ |
86 | const struct omap_chip_id omap_chip; | 91 | const struct omap_chip_id omap_chip; |
87 | 92 | ||
88 | /* Bit shift of this powerdomain's PM_WKDEP/CM_SLEEPDEP bit */ | ||
89 | const u8 dep_bit; | ||
90 | |||
91 | /* Powerdomains that can be told to wake this powerdomain up */ | 93 | /* Powerdomains that can be told to wake this powerdomain up */ |
92 | struct pwrdm_dep *wkdep_srcs; | 94 | struct pwrdm_dep *wkdep_srcs; |
93 | 95 | ||
94 | /* Powerdomains that can be told to keep this pwrdm from inactivity */ | 96 | /* Powerdomains that can be told to keep this pwrdm from inactivity */ |
95 | struct pwrdm_dep *sleepdep_srcs; | 97 | struct pwrdm_dep *sleepdep_srcs; |
96 | 98 | ||
99 | /* Bit shift of this powerdomain's PM_WKDEP/CM_SLEEPDEP bit */ | ||
100 | const u8 dep_bit; | ||
101 | |||
97 | /* Possible powerdomain power states */ | 102 | /* Possible powerdomain power states */ |
98 | const u8 pwrsts; | 103 | const u8 pwrsts; |
99 | 104 | ||
@@ -118,11 +123,11 @@ struct powerdomain { | |||
118 | struct list_head node; | 123 | struct list_head node; |
119 | 124 | ||
120 | int state; | 125 | int state; |
121 | unsigned state_counter[4]; | 126 | unsigned state_counter[PWRDM_MAX_PWRSTS]; |
122 | 127 | ||
123 | #ifdef CONFIG_PM_DEBUG | 128 | #ifdef CONFIG_PM_DEBUG |
124 | s64 timer; | 129 | s64 timer; |
125 | s64 state_timer[4]; | 130 | s64 state_timer[PWRDM_MAX_PWRSTS]; |
126 | #endif | 131 | #endif |
127 | }; | 132 | }; |
128 | 133 | ||
diff --git a/arch/arm/plat-omap/include/plat/serial.h b/arch/arm/plat-omap/include/plat/serial.h index 9951345a25d6..f5a4a92393ef 100644 --- a/arch/arm/plat-omap/include/plat/serial.h +++ b/arch/arm/plat-omap/include/plat/serial.h | |||
@@ -53,6 +53,7 @@ | |||
53 | #ifndef __ASSEMBLER__ | 53 | #ifndef __ASSEMBLER__ |
54 | extern void __init omap_serial_early_init(void); | 54 | extern void __init omap_serial_early_init(void); |
55 | extern void omap_serial_init(void); | 55 | extern void omap_serial_init(void); |
56 | extern void omap_serial_init_port(int port); | ||
56 | extern int omap_uart_can_sleep(void); | 57 | extern int omap_uart_can_sleep(void); |
57 | extern void omap_uart_check_wakeup(void); | 58 | extern void omap_uart_check_wakeup(void); |
58 | extern void omap_uart_prepare_suspend(void); | 59 | extern void omap_uart_prepare_suspend(void); |
diff --git a/arch/arm/plat-omap/include/plat/smp.h b/arch/arm/plat-omap/include/plat/smp.h index dcaa8fde7063..8983d54c4fd2 100644 --- a/arch/arm/plat-omap/include/plat/smp.h +++ b/arch/arm/plat-omap/include/plat/smp.h | |||
@@ -28,6 +28,8 @@ | |||
28 | 28 | ||
29 | /* Needed for secondary core boot */ | 29 | /* Needed for secondary core boot */ |
30 | extern void omap_secondary_startup(void); | 30 | extern void omap_secondary_startup(void); |
31 | extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask); | ||
32 | extern void omap_auxcoreboot_addr(u32 cpu_addr); | ||
31 | 33 | ||
32 | /* | 34 | /* |
33 | * We use Soft IRQ1 as the IPI | 35 | * We use Soft IRQ1 as the IPI |
diff --git a/arch/arm/plat-omap/mux.c b/arch/arm/plat-omap/mux.c index 05aebcad215b..06703635ace1 100644 --- a/arch/arm/plat-omap/mux.c +++ b/arch/arm/plat-omap/mux.c | |||
@@ -54,8 +54,12 @@ int __init_or_module omap_cfg_reg(const unsigned long index) | |||
54 | { | 54 | { |
55 | struct pin_config *reg; | 55 | struct pin_config *reg; |
56 | 56 | ||
57 | if (cpu_is_omap44xx()) | 57 | if (cpu_is_omap34xx() || cpu_is_omap44xx()) { |
58 | return 0; | 58 | printk(KERN_ERR "mux: Broken omap_cfg_reg(%lu) entry\n", |
59 | index); | ||
60 | WARN_ON(1); | ||
61 | return -EINVAL; | ||
62 | } | ||
59 | 63 | ||
60 | if (mux_cfg == NULL) { | 64 | if (mux_cfg == NULL) { |
61 | printk(KERN_ERR "Pin mux table not initialized\n"); | 65 | printk(KERN_ERR "Pin mux table not initialized\n"); |
diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c index bb16e624a557..1e5648d3e3d8 100644 --- a/arch/arm/plat-omap/omap_device.c +++ b/arch/arm/plat-omap/omap_device.c | |||
@@ -134,18 +134,18 @@ static int _omap_device_activate(struct omap_device *od, u8 ignore_lat) | |||
134 | (od->dev_wakeup_lat <= od->_dev_wakeup_lat_limit)) | 134 | (od->dev_wakeup_lat <= od->_dev_wakeup_lat_limit)) |
135 | break; | 135 | break; |
136 | 136 | ||
137 | getnstimeofday(&a); | 137 | read_persistent_clock(&a); |
138 | 138 | ||
139 | /* XXX check return code */ | 139 | /* XXX check return code */ |
140 | odpl->activate_func(od); | 140 | odpl->activate_func(od); |
141 | 141 | ||
142 | getnstimeofday(&b); | 142 | read_persistent_clock(&b); |
143 | 143 | ||
144 | c = timespec_sub(b, a); | 144 | c = timespec_sub(b, a); |
145 | act_lat = timespec_to_ns(&c) * NSEC_PER_USEC; | 145 | act_lat = timespec_to_ns(&c); |
146 | 146 | ||
147 | pr_debug("omap_device: %s: pm_lat %d: activate: elapsed time " | 147 | pr_debug("omap_device: %s: pm_lat %d: activate: elapsed time " |
148 | "%llu usec\n", od->pdev.name, od->pm_lat_level, | 148 | "%llu nsec\n", od->pdev.name, od->pm_lat_level, |
149 | act_lat); | 149 | act_lat); |
150 | 150 | ||
151 | WARN(act_lat > odpl->activate_lat, "omap_device: %s.%d: " | 151 | WARN(act_lat > odpl->activate_lat, "omap_device: %s.%d: " |
@@ -190,18 +190,18 @@ static int _omap_device_deactivate(struct omap_device *od, u8 ignore_lat) | |||
190 | od->_dev_wakeup_lat_limit)) | 190 | od->_dev_wakeup_lat_limit)) |
191 | break; | 191 | break; |
192 | 192 | ||
193 | getnstimeofday(&a); | 193 | read_persistent_clock(&a); |
194 | 194 | ||
195 | /* XXX check return code */ | 195 | /* XXX check return code */ |
196 | odpl->deactivate_func(od); | 196 | odpl->deactivate_func(od); |
197 | 197 | ||
198 | getnstimeofday(&b); | 198 | read_persistent_clock(&b); |
199 | 199 | ||
200 | c = timespec_sub(b, a); | 200 | c = timespec_sub(b, a); |
201 | deact_lat = timespec_to_ns(&c) * NSEC_PER_USEC; | 201 | deact_lat = timespec_to_ns(&c); |
202 | 202 | ||
203 | pr_debug("omap_device: %s: pm_lat %d: deactivate: elapsed time " | 203 | pr_debug("omap_device: %s: pm_lat %d: deactivate: elapsed time " |
204 | "%llu usec\n", od->pdev.name, od->pm_lat_level, | 204 | "%llu nsec\n", od->pdev.name, od->pm_lat_level, |
205 | deact_lat); | 205 | deact_lat); |
206 | 206 | ||
207 | WARN(deact_lat > odpl->deactivate_lat, "omap_device: %s.%d: " | 207 | WARN(deact_lat > odpl->deactivate_lat, "omap_device: %s.%d: " |
@@ -459,7 +459,7 @@ int omap_device_enable(struct platform_device *pdev) | |||
459 | ret = _omap_device_activate(od, IGNORE_WAKEUP_LAT); | 459 | ret = _omap_device_activate(od, IGNORE_WAKEUP_LAT); |
460 | 460 | ||
461 | od->dev_wakeup_lat = 0; | 461 | od->dev_wakeup_lat = 0; |
462 | od->_dev_wakeup_lat_limit = INT_MAX; | 462 | od->_dev_wakeup_lat_limit = UINT_MAX; |
463 | od->_state = OMAP_DEVICE_STATE_ENABLED; | 463 | od->_state = OMAP_DEVICE_STATE_ENABLED; |
464 | 464 | ||
465 | return ret; | 465 | return ret; |
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c index ad2bf07d30b5..d8d5094b37ed 100644 --- a/arch/arm/plat-omap/sram.c +++ b/arch/arm/plat-omap/sram.c | |||
@@ -48,8 +48,10 @@ | |||
48 | #define OMAP3_SRAM_VA 0xfe400000 | 48 | #define OMAP3_SRAM_VA 0xfe400000 |
49 | #define OMAP3_SRAM_PUB_PA 0x40208000 | 49 | #define OMAP3_SRAM_PUB_PA 0x40208000 |
50 | #define OMAP3_SRAM_PUB_VA (OMAP3_SRAM_VA + 0x8000) | 50 | #define OMAP3_SRAM_PUB_VA (OMAP3_SRAM_VA + 0x8000) |
51 | #define OMAP4_SRAM_PA 0x40200000 /*0x402f0000*/ | 51 | #define OMAP4_SRAM_PA 0x40300000 |
52 | #define OMAP4_SRAM_VA 0xfe400000 /*0xfe4f0000*/ | 52 | #define OMAP4_SRAM_VA 0xfe400000 |
53 | #define OMAP4_SRAM_PUB_PA (OMAP4_SRAM_PA + 0x4000) | ||
54 | #define OMAP4_SRAM_PUB_VA (OMAP4_SRAM_VA + 0x4000) | ||
53 | 55 | ||
54 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) | 56 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
55 | #define SRAM_BOOTLOADER_SZ 0x00 | 57 | #define SRAM_BOOTLOADER_SZ 0x00 |
@@ -140,6 +142,10 @@ void __init omap_detect_sram(void) | |||
140 | } else { | 142 | } else { |
141 | omap_sram_size = 0x8000; /* 32K */ | 143 | omap_sram_size = 0x8000; /* 32K */ |
142 | } | 144 | } |
145 | } else if (cpu_is_omap44xx()) { | ||
146 | omap_sram_base = OMAP4_SRAM_PUB_VA; | ||
147 | omap_sram_start = OMAP4_SRAM_PUB_PA; | ||
148 | omap_sram_size = 0xa000; /* 40K */ | ||
143 | } else { | 149 | } else { |
144 | omap_sram_base = OMAP2_SRAM_PUB_VA; | 150 | omap_sram_base = OMAP2_SRAM_PUB_VA; |
145 | omap_sram_start = OMAP2_SRAM_PUB_PA; | 151 | omap_sram_start = OMAP2_SRAM_PUB_PA; |
@@ -153,7 +159,7 @@ void __init omap_detect_sram(void) | |||
153 | } else if (cpu_is_omap44xx()) { | 159 | } else if (cpu_is_omap44xx()) { |
154 | omap_sram_base = OMAP4_SRAM_VA; | 160 | omap_sram_base = OMAP4_SRAM_VA; |
155 | omap_sram_start = OMAP4_SRAM_PA; | 161 | omap_sram_start = OMAP4_SRAM_PA; |
156 | omap_sram_size = 0x8000; /* 32K */ | 162 | omap_sram_size = 0xe000; /* 56K */ |
157 | } else { | 163 | } else { |
158 | omap_sram_base = OMAP2_SRAM_VA; | 164 | omap_sram_base = OMAP2_SRAM_VA; |
159 | omap_sram_start = OMAP2_SRAM_PA; | 165 | omap_sram_start = OMAP2_SRAM_PA; |
diff --git a/arch/arm/plat-omap/usb.c b/arch/arm/plat-omap/usb.c index 51033a4503c3..d3bf17cd36f3 100644 --- a/arch/arm/plat-omap/usb.c +++ b/arch/arm/plat-omap/usb.c | |||
@@ -137,7 +137,13 @@ static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device) | |||
137 | if (is_device) { | 137 | if (is_device) { |
138 | if (cpu_is_omap24xx()) | 138 | if (cpu_is_omap24xx()) |
139 | omap_cfg_reg(J20_24XX_USB0_PUEN); | 139 | omap_cfg_reg(J20_24XX_USB0_PUEN); |
140 | else | 140 | else if (cpu_is_omap7xx()) { |
141 | omap_cfg_reg(AA17_7XX_USB_DM); | ||
142 | omap_cfg_reg(W16_7XX_USB_PU_EN); | ||
143 | omap_cfg_reg(W17_7XX_USB_VBUSI); | ||
144 | omap_cfg_reg(W18_7XX_USB_DMCK_OUT); | ||
145 | omap_cfg_reg(W19_7XX_USB_DCRST); | ||
146 | } else | ||
141 | omap_cfg_reg(W4_USB_PUEN); | 147 | omap_cfg_reg(W4_USB_PUEN); |
142 | } | 148 | } |
143 | 149 | ||
diff --git a/arch/arm/plat-s3c/include/plat/nand.h b/arch/arm/plat-s3c/include/plat/nand.h index 065985978413..226147b7e026 100644 --- a/arch/arm/plat-s3c/include/plat/nand.h +++ b/arch/arm/plat-s3c/include/plat/nand.h | |||
@@ -17,6 +17,7 @@ | |||
17 | * Setting this flag will allow the kernel to | 17 | * Setting this flag will allow the kernel to |
18 | * look for it at boot time and also skip the NAND | 18 | * look for it at boot time and also skip the NAND |
19 | * scan. | 19 | * scan. |
20 | * @options: Default value to set into 'struct nand_chip' options. | ||
20 | * @nr_chips: Number of chips in this set | 21 | * @nr_chips: Number of chips in this set |
21 | * @nr_partitions: Number of partitions pointed to by @partitions | 22 | * @nr_partitions: Number of partitions pointed to by @partitions |
22 | * @name: Name of set (optional) | 23 | * @name: Name of set (optional) |
@@ -31,6 +32,7 @@ struct s3c2410_nand_set { | |||
31 | unsigned int disable_ecc:1; | 32 | unsigned int disable_ecc:1; |
32 | unsigned int flash_bbt:1; | 33 | unsigned int flash_bbt:1; |
33 | 34 | ||
35 | unsigned int options; | ||
34 | int nr_chips; | 36 | int nr_chips; |
35 | int nr_partitions; | 37 | int nr_partitions; |
36 | char *name; | 38 | char *name; |
diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c index 2d7423af1197..aed05bc3c2ea 100644 --- a/arch/arm/vfp/vfpmodule.c +++ b/arch/arm/vfp/vfpmodule.c | |||
@@ -38,16 +38,72 @@ union vfp_state *last_VFP_context[NR_CPUS]; | |||
38 | */ | 38 | */ |
39 | unsigned int VFP_arch; | 39 | unsigned int VFP_arch; |
40 | 40 | ||
41 | /* | ||
42 | * Per-thread VFP initialization. | ||
43 | */ | ||
44 | static void vfp_thread_flush(struct thread_info *thread) | ||
45 | { | ||
46 | union vfp_state *vfp = &thread->vfpstate; | ||
47 | unsigned int cpu; | ||
48 | |||
49 | memset(vfp, 0, sizeof(union vfp_state)); | ||
50 | |||
51 | vfp->hard.fpexc = FPEXC_EN; | ||
52 | vfp->hard.fpscr = FPSCR_ROUND_NEAREST; | ||
53 | |||
54 | /* | ||
55 | * Disable VFP to ensure we initialize it first. We must ensure | ||
56 | * that the modification of last_VFP_context[] and hardware disable | ||
57 | * are done for the same CPU and without preemption. | ||
58 | */ | ||
59 | cpu = get_cpu(); | ||
60 | if (last_VFP_context[cpu] == vfp) | ||
61 | last_VFP_context[cpu] = NULL; | ||
62 | fmxr(FPEXC, fmrx(FPEXC) & ~FPEXC_EN); | ||
63 | put_cpu(); | ||
64 | } | ||
65 | |||
66 | static void vfp_thread_release(struct thread_info *thread) | ||
67 | { | ||
68 | /* release case: Per-thread VFP cleanup. */ | ||
69 | union vfp_state *vfp = &thread->vfpstate; | ||
70 | unsigned int cpu = thread->cpu; | ||
71 | |||
72 | if (last_VFP_context[cpu] == vfp) | ||
73 | last_VFP_context[cpu] = NULL; | ||
74 | } | ||
75 | |||
76 | /* | ||
77 | * When this function is called with the following 'cmd's, the following | ||
78 | * is true while this function is being run: | ||
79 | * THREAD_NOFTIFY_SWTICH: | ||
80 | * - the previously running thread will not be scheduled onto another CPU. | ||
81 | * - the next thread to be run (v) will not be running on another CPU. | ||
82 | * - thread->cpu is the local CPU number | ||
83 | * - not preemptible as we're called in the middle of a thread switch | ||
84 | * THREAD_NOTIFY_FLUSH: | ||
85 | * - the thread (v) will be running on the local CPU, so | ||
86 | * v === current_thread_info() | ||
87 | * - thread->cpu is the local CPU number at the time it is accessed, | ||
88 | * but may change at any time. | ||
89 | * - we could be preempted if tree preempt rcu is enabled, so | ||
90 | * it is unsafe to use thread->cpu. | ||
91 | * THREAD_NOTIFY_RELEASE: | ||
92 | * - the thread (v) will not be running on any CPU; it is a dead thread. | ||
93 | * - thread->cpu will be the last CPU the thread ran on, which may not | ||
94 | * be the current CPU. | ||
95 | * - we could be preempted if tree preempt rcu is enabled. | ||
96 | */ | ||
41 | static int vfp_notifier(struct notifier_block *self, unsigned long cmd, void *v) | 97 | static int vfp_notifier(struct notifier_block *self, unsigned long cmd, void *v) |
42 | { | 98 | { |
43 | struct thread_info *thread = v; | 99 | struct thread_info *thread = v; |
44 | union vfp_state *vfp; | ||
45 | __u32 cpu = thread->cpu; | ||
46 | 100 | ||
47 | if (likely(cmd == THREAD_NOTIFY_SWITCH)) { | 101 | if (likely(cmd == THREAD_NOTIFY_SWITCH)) { |
48 | u32 fpexc = fmrx(FPEXC); | 102 | u32 fpexc = fmrx(FPEXC); |
49 | 103 | ||
50 | #ifdef CONFIG_SMP | 104 | #ifdef CONFIG_SMP |
105 | unsigned int cpu = thread->cpu; | ||
106 | |||
51 | /* | 107 | /* |
52 | * On SMP, if VFP is enabled, save the old state in | 108 | * On SMP, if VFP is enabled, save the old state in |
53 | * case the thread migrates to a different CPU. The | 109 | * case the thread migrates to a different CPU. The |
@@ -74,25 +130,10 @@ static int vfp_notifier(struct notifier_block *self, unsigned long cmd, void *v) | |||
74 | return NOTIFY_DONE; | 130 | return NOTIFY_DONE; |
75 | } | 131 | } |
76 | 132 | ||
77 | vfp = &thread->vfpstate; | 133 | if (cmd == THREAD_NOTIFY_FLUSH) |
78 | if (cmd == THREAD_NOTIFY_FLUSH) { | 134 | vfp_thread_flush(thread); |
79 | /* | 135 | else |
80 | * Per-thread VFP initialisation. | 136 | vfp_thread_release(thread); |
81 | */ | ||
82 | memset(vfp, 0, sizeof(union vfp_state)); | ||
83 | |||
84 | vfp->hard.fpexc = FPEXC_EN; | ||
85 | vfp->hard.fpscr = FPSCR_ROUND_NEAREST; | ||
86 | |||
87 | /* | ||
88 | * Disable VFP to ensure we initialise it first. | ||
89 | */ | ||
90 | fmxr(FPEXC, fmrx(FPEXC) & ~FPEXC_EN); | ||
91 | } | ||
92 | |||
93 | /* flush and release case: Per-thread VFP cleanup. */ | ||
94 | if (last_VFP_context[cpu] == vfp) | ||
95 | last_VFP_context[cpu] = NULL; | ||
96 | 137 | ||
97 | return NOTIFY_DONE; | 138 | return NOTIFY_DONE; |
98 | } | 139 | } |