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-rw-r--r--arch/arm/Kconfig6
-rw-r--r--arch/arm/boot/.gitignore1
-rw-r--r--arch/arm/boot/dts/exynos4210.dtsi1
-rw-r--r--arch/arm/boot/dts/tegra-paz00.dts6
-rw-r--r--arch/arm/boot/dts/testcases/tests-phandle.dtsi2
-rw-r--r--arch/arm/common/gic.c102
-rw-r--r--arch/arm/common/it8152.c7
-rw-r--r--arch/arm/common/pl330.c3
-rw-r--r--arch/arm/common/vic.c16
-rw-r--r--arch/arm/include/asm/assembler.h9
-rw-r--r--arch/arm/include/asm/domain.h8
-rw-r--r--arch/arm/include/asm/futex.h8
-rw-r--r--arch/arm/include/asm/hardware/gic.h4
-rw-r--r--arch/arm/include/asm/hardware/pl330.h2
-rw-r--r--arch/arm/include/asm/hardware/vic.h2
-rw-r--r--arch/arm/include/asm/highmem.h2
-rw-r--r--arch/arm/include/asm/perf_event.h4
-rw-r--r--arch/arm/include/asm/pmu.h2
-rw-r--r--arch/arm/include/asm/processor.h1
-rw-r--r--arch/arm/include/asm/smp.h6
-rw-r--r--arch/arm/include/asm/smp_plat.h6
-rw-r--r--arch/arm/include/asm/socket.h4
-rw-r--r--arch/arm/include/asm/tlb.h10
-rw-r--r--arch/arm/include/asm/uaccess.h16
-rw-r--r--arch/arm/kernel/ecard.c1
-rw-r--r--arch/arm/kernel/entry-armv.S2
-rw-r--r--arch/arm/kernel/entry-common.S15
-rw-r--r--arch/arm/kernel/perf_event.c49
-rw-r--r--arch/arm/kernel/perf_event_v6.c22
-rw-r--r--arch/arm/kernel/perf_event_v7.c39
-rw-r--r--arch/arm/kernel/perf_event_xscale.c20
-rw-r--r--arch/arm/kernel/process.c4
-rw-r--r--arch/arm/kernel/ptrace.c17
-rw-r--r--arch/arm/kernel/setup.c17
-rw-r--r--arch/arm/kernel/signal.c5
-rw-r--r--arch/arm/kernel/smp.c31
-rw-r--r--arch/arm/kernel/smp_twd.c4
-rw-r--r--arch/arm/kernel/traps.c5
-rw-r--r--arch/arm/kernel/vmlinux.lds.S10
-rw-r--r--arch/arm/lib/getuser.S12
-rw-r--r--arch/arm/lib/putuser.S28
-rw-r--r--arch/arm/lib/uaccess.S82
-rw-r--r--arch/arm/mach-at91/Kconfig14
-rw-r--r--arch/arm/mach-at91/Makefile14
-rw-r--r--arch/arm/mach-at91/at91cap9.c9
-rw-r--r--arch/arm/mach-at91/at91rm9200_devices.c2
-rw-r--r--arch/arm/mach-at91/at91sam9260.c1
-rw-r--r--arch/arm/mach-at91/at91sam9260_devices.c9
-rw-r--r--arch/arm/mach-at91/at91sam9261.c1
-rw-r--r--arch/arm/mach-at91/at91sam9261_devices.c2
-rw-r--r--arch/arm/mach-at91/at91sam9263.c1
-rw-r--r--arch/arm/mach-at91/at91sam9263_devices.c8
-rw-r--r--arch/arm/mach-at91/at91sam9_alt_reset.S7
-rw-r--r--arch/arm/mach-at91/at91sam9g45.c7
-rw-r--r--arch/arm/mach-at91/at91sam9g45_devices.c19
-rw-r--r--arch/arm/mach-at91/at91sam9g45_reset.S40
-rw-r--r--arch/arm/mach-at91/at91sam9rl.c1
-rw-r--r--arch/arm/mach-at91/at91sam9rl_devices.c8
-rw-r--r--arch/arm/mach-at91/generic.h2
-rw-r--r--arch/arm/mach-at91/include/mach/at91_rstc.h18
-rw-r--r--arch/arm/mach-at91/include/mach/at91cap9.h2
-rw-r--r--arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h108
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9260.h2
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9261.h2
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9263.h2
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h30
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9_smc.h29
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9g45.h2
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9rl.h2
-rw-r--r--arch/arm/mach-at91/include/mach/board.h2
-rw-r--r--arch/arm/mach-at91/pm.c9
-rw-r--r--arch/arm/mach-at91/pm.h8
-rw-r--r--arch/arm/mach-at91/pm_slowclock.S5
-rw-r--r--arch/arm/mach-at91/sam9_smc.c76
-rw-r--r--arch/arm/mach-at91/sam9_smc.h23
-rw-r--r--arch/arm/mach-at91/setup.c16
-rw-r--r--arch/arm/mach-bcmring/arch.c2
-rw-r--r--arch/arm/mach-bcmring/dma.c813
-rw-r--r--arch/arm/mach-bcmring/include/mach/dma.h196
-rw-r--r--arch/arm/mach-davinci/board-da850-evm.c2
-rw-r--r--arch/arm/mach-davinci/board-dm365-evm.c2
-rw-r--r--arch/arm/mach-davinci/board-dm644x-evm.c2
-rw-r--r--arch/arm/mach-davinci/board-dm646x-evm.c2
-rw-r--r--arch/arm/mach-davinci/board-neuros-osd2.c2
-rw-r--r--arch/arm/mach-davinci/board-omapl138-hawk.c2
-rw-r--r--arch/arm/mach-davinci/board-sffsdr.c2
-rw-r--r--arch/arm/mach-davinci/da850.c32
-rw-r--r--arch/arm/mach-dove/common.c3
-rw-r--r--arch/arm/mach-ep93xx/core.c19
-rw-r--r--arch/arm/mach-ep93xx/include/mach/platform.h2
-rw-r--r--arch/arm/mach-ep93xx/vision_ep9307.c6
-rw-r--r--arch/arm/mach-exynos/Kconfig10
-rw-r--r--arch/arm/mach-exynos/Makefile2
-rw-r--r--arch/arm/mach-exynos/clock-exynos4210.c2
-rw-r--r--arch/arm/mach-exynos/clock-exynos4212.c2
-rw-r--r--arch/arm/mach-exynos/clock.c2
-rw-r--r--arch/arm/mach-exynos/common.c2
-rw-r--r--arch/arm/mach-exynos/dev-pd.c139
-rw-r--r--arch/arm/mach-exynos/hotplug.c1
-rw-r--r--arch/arm/mach-exynos/mach-exynos4-dt.c8
-rw-r--r--arch/arm/mach-exynos/mach-nuri.c19
-rw-r--r--arch/arm/mach-exynos/mach-origen.c14
-rw-r--r--arch/arm/mach-exynos/mach-smdkv310.c12
-rw-r--r--arch/arm/mach-exynos/mach-universal_c210.c21
-rw-r--r--arch/arm/mach-exynos/platsmp.c1
-rw-r--r--arch/arm/mach-exynos/pm.c4
-rw-r--r--arch/arm/mach-exynos/pm_domains.c195
-rw-r--r--arch/arm/mach-highbank/highbank.c3
-rw-r--r--arch/arm/mach-imx/Kconfig7
-rw-r--r--arch/arm/mach-imx/clock-imx6q.c11
-rw-r--r--arch/arm/mach-imx/eukrea_mbimx27-baseboard.c20
-rw-r--r--arch/arm/mach-imx/eukrea_mbimxsd-baseboard.c1
-rw-r--r--arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c17
-rw-r--r--arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c17
-rw-r--r--arch/arm/mach-imx/imx51-dt.c4
-rw-r--r--arch/arm/mach-imx/imx53-dt.c4
-rw-r--r--arch/arm/mach-imx/mach-imx27_visstrim_m10.c1
-rw-r--r--arch/arm/mach-imx/mach-imx6q.c3
-rw-r--r--arch/arm/mach-imx/mach-mx53_ard.c4
-rw-r--r--arch/arm/mach-imx/mach-pca100.c13
-rw-r--r--arch/arm/mach-imx/mach-pcm037.c9
-rw-r--r--arch/arm/mach-imx/mach-pcm043.c13
-rw-r--r--arch/arm/mach-imx/mm-imx21.c6
-rw-r--r--arch/arm/mach-imx/mm-imx25.c7
-rw-r--r--arch/arm/mach-imx/mm-imx27.c7
-rw-r--r--arch/arm/mach-imx/mm-imx3.c13
-rw-r--r--arch/arm/mach-imx/mm-imx5.c22
-rw-r--r--arch/arm/mach-imx/mx31moboard-devboard.c24
-rw-r--r--arch/arm/mach-imx/mx31moboard-marxbot.c24
-rw-r--r--arch/arm/mach-imx/src.c5
-rw-r--r--arch/arm/mach-kirkwood/common.c3
-rw-r--r--arch/arm/mach-kirkwood/mpp.h320
-rw-r--r--arch/arm/mach-kirkwood/openrd-setup.c6
-rw-r--r--arch/arm/mach-kirkwood/t5325-setup.c6
-rw-r--r--arch/arm/mach-ks8695/leds.c1
-rw-r--r--arch/arm/mach-lpc32xx/include/mach/irqs.h2
-rw-r--r--arch/arm/mach-lpc32xx/irq.c25
-rw-r--r--arch/arm/mach-lpc32xx/serial.c20
-rw-r--r--arch/arm/mach-mmp/aspenite.c1
-rw-r--r--arch/arm/mach-mmp/pxa168.c1
-rw-r--r--arch/arm/mach-mmp/tavorevb.c1
-rw-r--r--arch/arm/mach-msm/board-msm8x60.c8
-rw-r--r--arch/arm/mach-msm/hotplug.c1
-rw-r--r--arch/arm/mach-msm/platsmp.c1
-rw-r--r--arch/arm/mach-mv78xx0/common.c3
-rw-r--r--arch/arm/mach-mv78xx0/mpp.h226
-rw-r--r--arch/arm/mach-omap1/Kconfig3
-rw-r--r--arch/arm/mach-omap1/Makefile4
-rw-r--r--arch/arm/mach-omap1/board-ams-delta.c9
-rw-r--r--arch/arm/mach-omap1/board-fsample.c15
-rw-r--r--arch/arm/mach-omap1/board-h2.c15
-rw-r--r--arch/arm/mach-omap1/board-h3.c9
-rw-r--r--arch/arm/mach-omap1/board-htcherald.c9
-rw-r--r--arch/arm/mach-omap1/board-innovator.c11
-rw-r--r--arch/arm/mach-omap1/board-nokia770.c19
-rw-r--r--arch/arm/mach-omap1/board-osk.c14
-rw-r--r--arch/arm/mach-omap1/board-palmte.c10
-rw-r--r--arch/arm/mach-omap1/board-palmtt.c10
-rw-r--r--arch/arm/mach-omap1/board-palmz71.c10
-rw-r--r--arch/arm/mach-omap1/board-perseus2.c15
-rw-r--r--arch/arm/mach-omap1/board-sx1.c16
-rw-r--r--arch/arm/mach-omap1/devices.c9
-rw-r--r--arch/arm/mach-omap1/lcd_dma.c2
-rw-r--r--arch/arm/mach-omap1/mcbsp.c14
-rw-r--r--arch/arm/mach-omap2/Kconfig16
-rw-r--r--arch/arm/mach-omap2/Makefile8
-rw-r--r--arch/arm/mach-omap2/board-4430sdp.c65
-rw-r--r--arch/arm/mach-omap2/board-cm-t35.c2
-rw-r--r--arch/arm/mach-omap2/board-generic.c6
-rw-r--r--arch/arm/mach-omap2/board-n8x0.c4
-rw-r--r--arch/arm/mach-omap2/board-omap3evm.c25
-rw-r--r--arch/arm/mach-omap2/board-omap4panda.c84
-rw-r--r--arch/arm/mach-omap2/board-zoom-peripherals.c6
-rw-r--r--arch/arm/mach-omap2/common.h1
-rw-r--r--arch/arm/mach-omap2/cpuidle44xx.c5
-rw-r--r--arch/arm/mach-omap2/devices.c24
-rw-r--r--arch/arm/mach-omap2/display.c4
-rw-r--r--arch/arm/mach-omap2/gpmc-smsc911x.c52
-rw-r--r--arch/arm/mach-omap2/gpmc.c6
-rw-r--r--arch/arm/mach-omap2/hsmmc.c30
-rw-r--r--arch/arm/mach-omap2/id.c1
-rw-r--r--arch/arm/mach-omap2/io.c6
-rw-r--r--arch/arm/mach-omap2/mailbox.c10
-rw-r--r--arch/arm/mach-omap2/mcbsp.c54
-rw-r--r--arch/arm/mach-omap2/mux.c24
-rw-r--r--arch/arm/mach-omap2/omap-headsmp.S1
-rw-r--r--arch/arm/mach-omap2/omap-iommu.c3
-rw-r--r--arch/arm/mach-omap2/omap4-common.c27
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.c16
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c21
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c22
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_3xxx_data.c54
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_44xx_data.c2
-rw-r--r--arch/arm/mach-omap2/pm.c3
-rw-r--r--arch/arm/mach-omap2/pm24xx.c8
-rw-r--r--arch/arm/mach-omap2/prm2xxx_3xxx.c1
-rw-r--r--arch/arm/mach-omap2/prm44xx.c1
-rw-r--r--arch/arm/mach-omap2/serial.c8
-rw-r--r--arch/arm/mach-omap2/smartreflex.c2
-rw-r--r--arch/arm/mach-omap2/timer.c2
-rw-r--r--arch/arm/mach-omap2/twl-common.c1
-rw-r--r--arch/arm/mach-omap2/usb-host.c6
-rw-r--r--arch/arm/mach-omap2/vc.c10
-rw-r--r--arch/arm/mach-omap2/voltagedomains3xxx_data.c2
-rw-r--r--arch/arm/mach-omap2/voltagedomains44xx_data.c2
-rw-r--r--arch/arm/mach-omap2/vp.c5
-rw-r--r--arch/arm/mach-orion5x/common.c4
-rw-r--r--arch/arm/mach-orion5x/db88f5281-setup.c4
-rw-r--r--arch/arm/mach-orion5x/rd88f5182-setup.c4
-rw-r--r--arch/arm/mach-prima2/irq.c2
-rw-r--r--arch/arm/mach-pxa/devices.c20
-rw-r--r--arch/arm/mach-pxa/generic.h1
-rw-r--r--arch/arm/mach-pxa/hx4700.c25
-rw-r--r--arch/arm/mach-pxa/mfp-pxa2xx.c7
-rw-r--r--arch/arm/mach-pxa/pxa25x.c3
-rw-r--r--arch/arm/mach-pxa/pxa27x.c3
-rw-r--r--arch/arm/mach-pxa/pxa300.c1
-rw-r--r--arch/arm/mach-pxa/pxa320.c1
-rw-r--r--arch/arm/mach-pxa/pxa3xx-ulpi.c20
-rw-r--r--arch/arm/mach-pxa/pxa3xx.c2
-rw-r--r--arch/arm/mach-pxa/pxa95x.c2
-rw-r--r--arch/arm/mach-pxa/saarb.c1
-rw-r--r--arch/arm/mach-pxa/sharpsl_pm.c3
-rw-r--r--arch/arm/mach-pxa/spitz_pm.c5
-rw-r--r--arch/arm/mach-realview/hotplug.c1
-rw-r--r--arch/arm/mach-realview/include/mach/board-eb.h18
-rw-r--r--arch/arm/mach-realview/include/mach/board-pb11mp.h2
-rw-r--r--arch/arm/mach-realview/realview_eb.c11
-rw-r--r--arch/arm/mach-realview/realview_pb11mp.c13
-rw-r--r--arch/arm/mach-s3c2410/cpu-freq.c8
-rw-r--r--arch/arm/mach-s3c2410/dma.c5
-rw-r--r--arch/arm/mach-s3c2410/pll.c2
-rw-r--r--arch/arm/mach-s3c2410/pm.c2
-rw-r--r--arch/arm/mach-s3c2412/cpu-freq.c3
-rw-r--r--arch/arm/mach-s3c2412/dma.c3
-rw-r--r--arch/arm/mach-s3c2412/irq.c2
-rw-r--r--arch/arm/mach-s3c2412/pm.c2
-rw-r--r--arch/arm/mach-s3c2416/irq.c3
-rw-r--r--arch/arm/mach-s3c2416/pm.c2
-rw-r--r--arch/arm/mach-s3c2440/clock.c2
-rw-r--r--arch/arm/mach-s3c2440/common.h2
-rw-r--r--arch/arm/mach-s3c2440/dma.c3
-rw-r--r--arch/arm/mach-s3c2440/irq.c2
-rw-r--r--arch/arm/mach-s3c2440/mach-anubis.c2
-rw-r--r--arch/arm/mach-s3c2440/mach-at2440evb.c2
-rw-r--r--arch/arm/mach-s3c2440/mach-gta02.c2
-rw-r--r--arch/arm/mach-s3c2440/mach-mini2440.c2
-rw-r--r--arch/arm/mach-s3c2440/mach-nexcoder.c2
-rw-r--r--arch/arm/mach-s3c2440/mach-osiris.c2
-rw-r--r--arch/arm/mach-s3c2440/mach-rx1950.c2
-rw-r--r--arch/arm/mach-s3c2440/mach-rx3715.c2
-rw-r--r--arch/arm/mach-s3c2440/mach-smdk2440.c2
-rw-r--r--arch/arm/mach-s3c2440/s3c2440-cpufreq.c3
-rw-r--r--arch/arm/mach-s3c2440/s3c2440-pll-12000000.c2
-rw-r--r--arch/arm/mach-s3c2440/s3c2440-pll-16934400.c3
-rw-r--r--arch/arm/mach-s3c2440/s3c2440.c13
-rw-r--r--arch/arm/mach-s3c2440/s3c2442.c2
-rw-r--r--arch/arm/mach-s3c2440/s3c244x-clock.c2
-rw-r--r--arch/arm/mach-s3c2440/s3c244x-irq.c2
-rw-r--r--arch/arm/mach-s3c2440/s3c244x.c12
-rw-r--r--arch/arm/mach-s3c2443/dma.c3
-rw-r--r--arch/arm/mach-s3c2443/irq.c3
-rw-r--r--arch/arm/mach-s3c64xx/clock.c5
-rw-r--r--arch/arm/mach-s3c64xx/common.c2
-rw-r--r--arch/arm/mach-s3c64xx/mach-crag6410-module.c1
-rw-r--r--arch/arm/mach-s5p64x0/pm.c2
-rw-r--r--arch/arm/mach-s5pv210/clock.c4
-rw-r--r--arch/arm/mach-s5pv210/pm.c2
-rw-r--r--arch/arm/mach-sa1100/assabet.c12
-rw-r--r--arch/arm/mach-sa1100/cerf.c11
-rw-r--r--arch/arm/mach-sa1100/clock.c91
-rw-r--r--arch/arm/mach-sa1100/collie.c23
-rw-r--r--arch/arm/mach-sa1100/cpu-sa1100.c2
-rw-r--r--arch/arm/mach-sa1100/generic.c27
-rw-r--r--arch/arm/mach-sa1100/include/mach/mcp.h2
-rw-r--r--arch/arm/mach-sa1100/jornada720_ssp.c2
-rw-r--r--arch/arm/mach-sa1100/lart.c10
-rw-r--r--arch/arm/mach-sa1100/shannon.c11
-rw-r--r--arch/arm/mach-sa1100/simpad.c18
-rw-r--r--arch/arm/mach-shmobile/board-ag5evm.c54
-rw-r--r--arch/arm/mach-shmobile/board-ap4evb.c346
-rw-r--r--arch/arm/mach-shmobile/board-bonito.c9
-rw-r--r--arch/arm/mach-shmobile/board-kota2.c3
-rw-r--r--arch/arm/mach-shmobile/board-mackerel.c223
-rw-r--r--arch/arm/mach-shmobile/clock-sh73a0.c113
-rw-r--r--arch/arm/mach-shmobile/include/mach/sh73a0.h6
-rw-r--r--arch/arm/mach-shmobile/intc-sh73a0.c2
-rw-r--r--arch/arm/mach-shmobile/pfc-r8a7779.c2
-rw-r--r--arch/arm/mach-shmobile/pfc-sh7372.c41
-rw-r--r--arch/arm/mach-shmobile/setup-sh7372.c4
-rw-r--r--arch/arm/mach-shmobile/smp-r8a7779.c1
-rw-r--r--arch/arm/mach-shmobile/smp-sh73a0.c3
-rw-r--r--arch/arm/mach-spear3xx/spear300.c2
-rw-r--r--arch/arm/mach-spear3xx/spear310.c2
-rw-r--r--arch/arm/mach-spear3xx/spear320.c2
-rw-r--r--arch/arm/mach-tegra/Kconfig4
-rw-r--r--arch/arm/mach-tegra/board-paz00.c8
-rw-r--r--arch/arm/mach-tegra/board-paz00.h2
-rw-r--r--arch/arm/mach-tegra/fuse.c2
-rw-r--r--arch/arm/mach-tegra/include/mach/dma.h10
-rw-r--r--arch/arm/mach-tegra/include/mach/kbc.h13
-rw-r--r--arch/arm/mach-tegra/include/mach/pinconf-tegra.h63
-rw-r--r--arch/arm/mach-tegra/include/mach/usb_phy.h2
-rw-r--r--arch/arm/mach-tegra/usb_phy.c4
-rw-r--r--arch/arm/mach-u300/core.c80
-rw-r--r--arch/arm/mach-u300/i2c.c2
-rw-r--r--arch/arm/mach-u300/include/mach/gpio-u300.h2
-rw-r--r--arch/arm/mach-ux500/Kconfig3
-rw-r--r--arch/arm/mach-ux500/board-mop500-sdi.c2
-rw-r--r--arch/arm/mach-ux500/cache-l2x0.c48
-rw-r--r--arch/arm/mach-ux500/hotplug.c1
-rw-r--r--arch/arm/mach-ux500/platsmp.c1
-rw-r--r--arch/arm/mach-ux500/usb.c6
-rw-r--r--arch/arm/mach-versatile/core.c7
-rw-r--r--arch/arm/mach-vexpress/Kconfig2
-rw-r--r--arch/arm/mach-vexpress/ct-ca9x4.c4
-rw-r--r--arch/arm/mach-vexpress/hotplug.c1
-rw-r--r--arch/arm/mm/Kconfig4
-rw-r--r--arch/arm/mm/cache-v7.S6
-rw-r--r--arch/arm/mm/copypage-fa.c12
-rw-r--r--arch/arm/mm/copypage-feroceon.c12
-rw-r--r--arch/arm/mm/copypage-v3.c12
-rw-r--r--arch/arm/mm/copypage-v4mc.c8
-rw-r--r--arch/arm/mm/copypage-v4wb.c12
-rw-r--r--arch/arm/mm/copypage-v4wt.c12
-rw-r--r--arch/arm/mm/copypage-v6.c12
-rw-r--r--arch/arm/mm/copypage-xsc3.c12
-rw-r--r--arch/arm/mm/copypage-xscale.c8
-rw-r--r--arch/arm/mm/highmem.c4
-rw-r--r--arch/arm/mm/init.c3
-rw-r--r--arch/arm/mm/proc-v7.S30
-rw-r--r--arch/arm/plat-mxc/3ds_debugboard.c9
-rw-r--r--arch/arm/plat-mxc/Kconfig6
-rw-r--r--arch/arm/plat-mxc/Makefile2
-rw-r--r--arch/arm/plat-mxc/audmux-v1.c64
-rw-r--r--arch/arm/plat-mxc/audmux-v2.c219
-rw-r--r--arch/arm/plat-mxc/include/mach/audmux.h60
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-v1.h2
-rw-r--r--arch/arm/plat-mxc/include/mach/mxc_ehci.h2
-rw-r--r--arch/arm/plat-mxc/include/mach/ulpi.h6
-rw-r--r--arch/arm/plat-mxc/ulpi.c8
-rw-r--r--arch/arm/plat-omap/Kconfig8
-rw-r--r--arch/arm/plat-omap/Makefile2
-rw-r--r--arch/arm/plat-omap/common.c3
-rw-r--r--arch/arm/plat-omap/fb.c334
-rw-r--r--arch/arm/plat-omap/fb.h10
-rw-r--r--arch/arm/plat-omap/include/plat/blizzard.h12
-rw-r--r--arch/arm/plat-omap/include/plat/board.h2
-rw-r--r--arch/arm/plat-omap/include/plat/hwa742.h8
-rw-r--r--arch/arm/plat-omap/include/plat/irqs.h10
-rw-r--r--arch/arm/plat-omap/include/plat/mcbsp.h333
-rw-r--r--arch/arm/plat-omap/include/plat/omap-secure.h8
-rw-r--r--arch/arm/plat-omap/include/plat/omap4-keypad.h9
-rw-r--r--arch/arm/plat-omap/include/plat/vram.h21
-rw-r--r--arch/arm/plat-omap/mcbsp.c1361
-rw-r--r--arch/arm/plat-orion/common.c9
-rw-r--r--arch/arm/plat-orion/include/plat/common.h3
-rw-r--r--arch/arm/plat-orion/mpp.c3
-rw-r--r--arch/arm/plat-s3c24xx/dma.c2
-rw-r--r--arch/arm/plat-s3c24xx/pm-simtec.c2
-rw-r--r--arch/arm/plat-samsung/devs.c6
-rw-r--r--arch/arm/plat-samsung/include/plat/regs-fb.h33
-rw-r--r--arch/arm/plat-spear/include/plat/keyboard.h66
-rw-r--r--arch/arm/plat-spear/time.c6
-rw-r--r--arch/arm/plat-versatile/platsmp.c1
365 files changed, 2772 insertions, 5844 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 24626b0419ee..dfb0312f4e73 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -754,7 +754,7 @@ config ARCH_SA1100
754 select ARCH_HAS_CPUFREQ 754 select ARCH_HAS_CPUFREQ
755 select CPU_FREQ 755 select CPU_FREQ
756 select GENERIC_CLOCKEVENTS 756 select GENERIC_CLOCKEVENTS
757 select CLKDEV_LOOKUP 757 select HAVE_CLK
758 select HAVE_SCHED_CLOCK 758 select HAVE_SCHED_CLOCK
759 select TICK_ONESHOT 759 select TICK_ONESHOT
760 select ARCH_REQUIRE_GPIOLIB 760 select ARCH_REQUIRE_GPIOLIB
@@ -825,7 +825,6 @@ config ARCH_S5PC100
825 select HAVE_CLK 825 select HAVE_CLK
826 select CLKDEV_LOOKUP 826 select CLKDEV_LOOKUP
827 select CPU_V7 827 select CPU_V7
828 select ARM_L1_CACHE_SHIFT_6
829 select ARCH_USES_GETTIMEOFFSET 828 select ARCH_USES_GETTIMEOFFSET
830 select HAVE_S3C2410_I2C if I2C 829 select HAVE_S3C2410_I2C if I2C
831 select HAVE_S3C_RTC if RTC_CLASS 830 select HAVE_S3C_RTC if RTC_CLASS
@@ -842,7 +841,6 @@ config ARCH_S5PV210
842 select HAVE_CLK 841 select HAVE_CLK
843 select CLKDEV_LOOKUP 842 select CLKDEV_LOOKUP
844 select CLKSRC_MMIO 843 select CLKSRC_MMIO
845 select ARM_L1_CACHE_SHIFT_6
846 select ARCH_HAS_CPUFREQ 844 select ARCH_HAS_CPUFREQ
847 select GENERIC_CLOCKEVENTS 845 select GENERIC_CLOCKEVENTS
848 select HAVE_SCHED_CLOCK 846 select HAVE_SCHED_CLOCK
@@ -1282,7 +1280,7 @@ config ARM_ERRATA_743622
1282 depends on CPU_V7 1280 depends on CPU_V7
1283 help 1281 help
1284 This option enables the workaround for the 743622 Cortex-A9 1282 This option enables the workaround for the 743622 Cortex-A9
1285 (r2p0..r2p2) erratum. Under very rare conditions, a faulty 1283 (r2p*) erratum. Under very rare conditions, a faulty
1286 optimisation in the Cortex-A9 Store Buffer may lead to data 1284 optimisation in the Cortex-A9 Store Buffer may lead to data
1287 corruption. This workaround sets a specific bit in the diagnostic 1285 corruption. This workaround sets a specific bit in the diagnostic
1288 register of the Cortex-A9 which disables the Store Buffer 1286 register of the Cortex-A9 which disables the Store Buffer
diff --git a/arch/arm/boot/.gitignore b/arch/arm/boot/.gitignore
index ce1c5ff746e7..3c79f85975aa 100644
--- a/arch/arm/boot/.gitignore
+++ b/arch/arm/boot/.gitignore
@@ -3,3 +3,4 @@ zImage
3xipImage 3xipImage
4bootpImage 4bootpImage
5uImage 5uImage
6*.dtb
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index 63d7578856c1..a1dd2ee83753 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -29,6 +29,7 @@
29 compatible = "arm,cortex-a9-gic"; 29 compatible = "arm,cortex-a9-gic";
30 #interrupt-cells = <3>; 30 #interrupt-cells = <3>;
31 interrupt-controller; 31 interrupt-controller;
32 cpu-offset = <0x8000>;
32 reg = <0x10490000 0x1000>, <0x10480000 0x100>; 33 reg = <0x10490000 0x1000>, <0x10480000 0x100>;
33 }; 34 };
34 35
diff --git a/arch/arm/boot/dts/tegra-paz00.dts b/arch/arm/boot/dts/tegra-paz00.dts
index 1a1d7023b69b..825d2957da0b 100644
--- a/arch/arm/boot/dts/tegra-paz00.dts
+++ b/arch/arm/boot/dts/tegra-paz00.dts
@@ -46,11 +46,11 @@
46 }; 46 };
47 47
48 serial@70006200 { 48 serial@70006200 {
49 status = "disable"; 49 clock-frequency = <216000000>;
50 }; 50 };
51 51
52 serial@70006300 { 52 serial@70006300 {
53 clock-frequency = <216000000>; 53 status = "disable";
54 }; 54 };
55 55
56 serial@70006400 { 56 serial@70006400 {
@@ -60,7 +60,7 @@
60 sdhci@c8000000 { 60 sdhci@c8000000 {
61 cd-gpios = <&gpio 173 0>; /* gpio PV5 */ 61 cd-gpios = <&gpio 173 0>; /* gpio PV5 */
62 wp-gpios = <&gpio 57 0>; /* gpio PH1 */ 62 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
63 power-gpios = <&gpio 155 0>; /* gpio PT3 */ 63 power-gpios = <&gpio 169 0>; /* gpio PV1 */
64 }; 64 };
65 65
66 sdhci@c8000200 { 66 sdhci@c8000200 {
diff --git a/arch/arm/boot/dts/testcases/tests-phandle.dtsi b/arch/arm/boot/dts/testcases/tests-phandle.dtsi
index ec0c4e6212c9..0007d3cd7dc2 100644
--- a/arch/arm/boot/dts/testcases/tests-phandle.dtsi
+++ b/arch/arm/boot/dts/testcases/tests-phandle.dtsi
@@ -31,6 +31,8 @@
31 phandle-list-bad-phandle = <12345678 0 0>; 31 phandle-list-bad-phandle = <12345678 0 0>;
32 phandle-list-bad-args = <&provider2 1 0>, 32 phandle-list-bad-args = <&provider2 1 0>,
33 <&provider3 0>; 33 <&provider3 0>;
34 empty-property;
35 unterminated-string = [40 41 42 43];
34 }; 36 };
35 }; 37 };
36 }; 38 };
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index b2dc2dd7f1df..f0783be17352 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -41,6 +41,7 @@
41 41
42#include <asm/irq.h> 42#include <asm/irq.h>
43#include <asm/exception.h> 43#include <asm/exception.h>
44#include <asm/smp_plat.h>
44#include <asm/mach/irq.h> 45#include <asm/mach/irq.h>
45#include <asm/hardware/gic.h> 46#include <asm/hardware/gic.h>
46 47
@@ -50,7 +51,6 @@ union gic_base {
50}; 51};
51 52
52struct gic_chip_data { 53struct gic_chip_data {
53 unsigned int irq_offset;
54 union gic_base dist_base; 54 union gic_base dist_base;
55 union gic_base cpu_base; 55 union gic_base cpu_base;
56#ifdef CONFIG_CPU_PM 56#ifdef CONFIG_CPU_PM
@@ -60,9 +60,7 @@ struct gic_chip_data {
60 u32 __percpu *saved_ppi_enable; 60 u32 __percpu *saved_ppi_enable;
61 u32 __percpu *saved_ppi_conf; 61 u32 __percpu *saved_ppi_conf;
62#endif 62#endif
63#ifdef CONFIG_IRQ_DOMAIN 63 struct irq_domain *domain;
64 struct irq_domain domain;
65#endif
66 unsigned int gic_irqs; 64 unsigned int gic_irqs;
67#ifdef CONFIG_GIC_NON_BANKED 65#ifdef CONFIG_GIC_NON_BANKED
68 void __iomem *(*get_base)(union gic_base *); 66 void __iomem *(*get_base)(union gic_base *);
@@ -281,7 +279,7 @@ asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
281 irqnr = irqstat & ~0x1c00; 279 irqnr = irqstat & ~0x1c00;
282 280
283 if (likely(irqnr > 15 && irqnr < 1021)) { 281 if (likely(irqnr > 15 && irqnr < 1021)) {
284 irqnr = irq_domain_to_irq(&gic->domain, irqnr); 282 irqnr = irq_find_mapping(gic->domain, irqnr);
285 handle_IRQ(irqnr, regs); 283 handle_IRQ(irqnr, regs);
286 continue; 284 continue;
287 } 285 }
@@ -313,8 +311,8 @@ static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
313 if (gic_irq == 1023) 311 if (gic_irq == 1023)
314 goto out; 312 goto out;
315 313
316 cascade_irq = irq_domain_to_irq(&chip_data->domain, gic_irq); 314 cascade_irq = irq_find_mapping(chip_data->domain, gic_irq);
317 if (unlikely(gic_irq < 32 || gic_irq > 1020 || cascade_irq >= NR_IRQS)) 315 if (unlikely(gic_irq < 32 || gic_irq > 1020))
318 do_bad_IRQ(cascade_irq, desc); 316 do_bad_IRQ(cascade_irq, desc);
319 else 317 else
320 generic_handle_irq(cascade_irq); 318 generic_handle_irq(cascade_irq);
@@ -347,16 +345,11 @@ void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
347 345
348static void __init gic_dist_init(struct gic_chip_data *gic) 346static void __init gic_dist_init(struct gic_chip_data *gic)
349{ 347{
350 unsigned int i, irq; 348 unsigned int i;
351 u32 cpumask; 349 u32 cpumask;
352 unsigned int gic_irqs = gic->gic_irqs; 350 unsigned int gic_irqs = gic->gic_irqs;
353 struct irq_domain *domain = &gic->domain;
354 void __iomem *base = gic_data_dist_base(gic); 351 void __iomem *base = gic_data_dist_base(gic);
355 u32 cpu = 0; 352 u32 cpu = cpu_logical_map(smp_processor_id());
356
357#ifdef CONFIG_SMP
358 cpu = cpu_logical_map(smp_processor_id());
359#endif
360 353
361 cpumask = 1 << cpu; 354 cpumask = 1 << cpu;
362 cpumask |= cpumask << 8; 355 cpumask |= cpumask << 8;
@@ -389,23 +382,6 @@ static void __init gic_dist_init(struct gic_chip_data *gic)
389 for (i = 32; i < gic_irqs; i += 32) 382 for (i = 32; i < gic_irqs; i += 32)
390 writel_relaxed(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32); 383 writel_relaxed(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32);
391 384
392 /*
393 * Setup the Linux IRQ subsystem.
394 */
395 irq_domain_for_each_irq(domain, i, irq) {
396 if (i < 32) {
397 irq_set_percpu_devid(irq);
398 irq_set_chip_and_handler(irq, &gic_chip,
399 handle_percpu_devid_irq);
400 set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN);
401 } else {
402 irq_set_chip_and_handler(irq, &gic_chip,
403 handle_fasteoi_irq);
404 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
405 }
406 irq_set_chip_data(irq, gic);
407 }
408
409 writel_relaxed(1, base + GIC_DIST_CTRL); 385 writel_relaxed(1, base + GIC_DIST_CTRL);
410} 386}
411 387
@@ -621,11 +597,27 @@ static void __init gic_pm_init(struct gic_chip_data *gic)
621} 597}
622#endif 598#endif
623 599
624#ifdef CONFIG_OF 600static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
625static int gic_irq_domain_dt_translate(struct irq_domain *d, 601 irq_hw_number_t hw)
626 struct device_node *controller, 602{
627 const u32 *intspec, unsigned int intsize, 603 if (hw < 32) {
628 unsigned long *out_hwirq, unsigned int *out_type) 604 irq_set_percpu_devid(irq);
605 irq_set_chip_and_handler(irq, &gic_chip,
606 handle_percpu_devid_irq);
607 set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN);
608 } else {
609 irq_set_chip_and_handler(irq, &gic_chip,
610 handle_fasteoi_irq);
611 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
612 }
613 irq_set_chip_data(irq, d->host_data);
614 return 0;
615}
616
617static int gic_irq_domain_xlate(struct irq_domain *d,
618 struct device_node *controller,
619 const u32 *intspec, unsigned int intsize,
620 unsigned long *out_hwirq, unsigned int *out_type)
629{ 621{
630 if (d->of_node != controller) 622 if (d->of_node != controller)
631 return -EINVAL; 623 return -EINVAL;
@@ -642,26 +634,23 @@ static int gic_irq_domain_dt_translate(struct irq_domain *d,
642 *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK; 634 *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
643 return 0; 635 return 0;
644} 636}
645#endif
646 637
647const struct irq_domain_ops gic_irq_domain_ops = { 638const struct irq_domain_ops gic_irq_domain_ops = {
648#ifdef CONFIG_OF 639 .map = gic_irq_domain_map,
649 .dt_translate = gic_irq_domain_dt_translate, 640 .xlate = gic_irq_domain_xlate,
650#endif
651}; 641};
652 642
653void __init gic_init_bases(unsigned int gic_nr, int irq_start, 643void __init gic_init_bases(unsigned int gic_nr, int irq_start,
654 void __iomem *dist_base, void __iomem *cpu_base, 644 void __iomem *dist_base, void __iomem *cpu_base,
655 u32 percpu_offset) 645 u32 percpu_offset, struct device_node *node)
656{ 646{
647 irq_hw_number_t hwirq_base;
657 struct gic_chip_data *gic; 648 struct gic_chip_data *gic;
658 struct irq_domain *domain; 649 int gic_irqs, irq_base;
659 int gic_irqs;
660 650
661 BUG_ON(gic_nr >= MAX_GIC_NR); 651 BUG_ON(gic_nr >= MAX_GIC_NR);
662 652
663 gic = &gic_data[gic_nr]; 653 gic = &gic_data[gic_nr];
664 domain = &gic->domain;
665#ifdef CONFIG_GIC_NON_BANKED 654#ifdef CONFIG_GIC_NON_BANKED
666 if (percpu_offset) { /* Frankein-GIC without banked registers... */ 655 if (percpu_offset) { /* Frankein-GIC without banked registers... */
667 unsigned int cpu; 656 unsigned int cpu;
@@ -697,10 +686,10 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
697 * For primary GICs, skip over SGIs. 686 * For primary GICs, skip over SGIs.
698 * For secondary GICs, skip over PPIs, too. 687 * For secondary GICs, skip over PPIs, too.
699 */ 688 */
700 domain->hwirq_base = 32; 689 hwirq_base = 32;
701 if (gic_nr == 0) { 690 if (gic_nr == 0) {
702 if ((irq_start & 31) > 0) { 691 if ((irq_start & 31) > 0) {
703 domain->hwirq_base = 16; 692 hwirq_base = 16;
704 if (irq_start != -1) 693 if (irq_start != -1)
705 irq_start = (irq_start & ~31) + 16; 694 irq_start = (irq_start & ~31) + 16;
706 } 695 }
@@ -716,17 +705,17 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
716 gic_irqs = 1020; 705 gic_irqs = 1020;
717 gic->gic_irqs = gic_irqs; 706 gic->gic_irqs = gic_irqs;
718 707
719 domain->nr_irq = gic_irqs - domain->hwirq_base; 708 gic_irqs -= hwirq_base; /* calculate # of irqs to allocate */
720 domain->irq_base = irq_alloc_descs(irq_start, 16, domain->nr_irq, 709 irq_base = irq_alloc_descs(irq_start, 16, gic_irqs, numa_node_id());
721 numa_node_id()); 710 if (IS_ERR_VALUE(irq_base)) {
722 if (IS_ERR_VALUE(domain->irq_base)) {
723 WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n", 711 WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n",
724 irq_start); 712 irq_start);
725 domain->irq_base = irq_start; 713 irq_base = irq_start;
726 } 714 }
727 domain->priv = gic; 715 gic->domain = irq_domain_add_legacy(node, gic_irqs, irq_base,
728 domain->ops = &gic_irq_domain_ops; 716 hwirq_base, &gic_irq_domain_ops, gic);
729 irq_domain_add(domain); 717 if (WARN_ON(!gic->domain))
718 return;
730 719
731 gic_chip.flags |= gic_arch_extn.flags; 720 gic_chip.flags |= gic_arch_extn.flags;
732 gic_dist_init(gic); 721 gic_dist_init(gic);
@@ -771,7 +760,6 @@ int __init gic_of_init(struct device_node *node, struct device_node *parent)
771 void __iomem *dist_base; 760 void __iomem *dist_base;
772 u32 percpu_offset; 761 u32 percpu_offset;
773 int irq; 762 int irq;
774 struct irq_domain *domain = &gic_data[gic_cnt].domain;
775 763
776 if (WARN_ON(!node)) 764 if (WARN_ON(!node))
777 return -ENODEV; 765 return -ENODEV;
@@ -785,9 +773,7 @@ int __init gic_of_init(struct device_node *node, struct device_node *parent)
785 if (of_property_read_u32(node, "cpu-offset", &percpu_offset)) 773 if (of_property_read_u32(node, "cpu-offset", &percpu_offset))
786 percpu_offset = 0; 774 percpu_offset = 0;
787 775
788 domain->of_node = of_node_get(node); 776 gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset, node);
789
790 gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset);
791 777
792 if (parent) { 778 if (parent) {
793 irq = irq_of_parse_and_map(node, 0); 779 irq = irq_of_parse_and_map(node, 0);
diff --git a/arch/arm/common/it8152.c b/arch/arm/common/it8152.c
index 9384c2d02baa..dcb13494ca0d 100644
--- a/arch/arm/common/it8152.c
+++ b/arch/arm/common/it8152.c
@@ -320,13 +320,6 @@ err0:
320 return -EBUSY; 320 return -EBUSY;
321} 321}
322 322
323/*
324 * If we set up a device for bus mastering, we need to check the latency
325 * timer as we don't have even crappy BIOSes to set it properly.
326 * The implementation is from arch/i386/pci/i386.c
327 */
328unsigned int pcibios_max_latency = 255;
329
330/* ITE bridge requires setting latency timer to avoid early bus access 323/* ITE bridge requires setting latency timer to avoid early bus access
331 termination by PCI bus master devices 324 termination by PCI bus master devices
332*/ 325*/
diff --git a/arch/arm/common/pl330.c b/arch/arm/common/pl330.c
index d8e44a43047c..ff3ad2244824 100644
--- a/arch/arm/common/pl330.c
+++ b/arch/arm/common/pl330.c
@@ -1502,12 +1502,13 @@ int pl330_chan_ctrl(void *ch_id, enum pl330_chan_op op)
1502 struct pl330_thread *thrd = ch_id; 1502 struct pl330_thread *thrd = ch_id;
1503 struct pl330_dmac *pl330; 1503 struct pl330_dmac *pl330;
1504 unsigned long flags; 1504 unsigned long flags;
1505 int ret = 0, active = thrd->req_running; 1505 int ret = 0, active;
1506 1506
1507 if (!thrd || thrd->free || thrd->dmac->state == DYING) 1507 if (!thrd || thrd->free || thrd->dmac->state == DYING)
1508 return -EINVAL; 1508 return -EINVAL;
1509 1509
1510 pl330 = thrd->dmac; 1510 pl330 = thrd->dmac;
1511 active = thrd->req_running;
1511 1512
1512 spin_lock_irqsave(&pl330->lock, flags); 1513 spin_lock_irqsave(&pl330->lock, flags);
1513 1514
diff --git a/arch/arm/common/vic.c b/arch/arm/common/vic.c
index dcb004a804c7..7a66311f3066 100644
--- a/arch/arm/common/vic.c
+++ b/arch/arm/common/vic.c
@@ -56,7 +56,7 @@ struct vic_device {
56 u32 int_enable; 56 u32 int_enable;
57 u32 soft_int; 57 u32 soft_int;
58 u32 protect; 58 u32 protect;
59 struct irq_domain domain; 59 struct irq_domain *domain;
60}; 60};
61 61
62/* we cannot allocate memory when VICs are initially registered */ 62/* we cannot allocate memory when VICs are initially registered */
@@ -192,14 +192,8 @@ static void __init vic_register(void __iomem *base, unsigned int irq,
192 v->resume_sources = resume_sources; 192 v->resume_sources = resume_sources;
193 v->irq = irq; 193 v->irq = irq;
194 vic_id++; 194 vic_id++;
195 195 v->domain = irq_domain_add_legacy(node, 32, irq, 0,
196 v->domain.irq_base = irq; 196 &irq_domain_simple_ops, v);
197 v->domain.nr_irq = 32;
198#ifdef CONFIG_OF_IRQ
199 v->domain.of_node = of_node_get(node);
200#endif /* CONFIG_OF */
201 v->domain.ops = &irq_domain_simple_ops;
202 irq_domain_add(&v->domain);
203} 197}
204 198
205static void vic_ack_irq(struct irq_data *d) 199static void vic_ack_irq(struct irq_data *d)
@@ -348,7 +342,7 @@ static void __init vic_init_st(void __iomem *base, unsigned int irq_start,
348 vic_register(base, irq_start, 0, node); 342 vic_register(base, irq_start, 0, node);
349} 343}
350 344
351static void __init __vic_init(void __iomem *base, unsigned int irq_start, 345void __init __vic_init(void __iomem *base, unsigned int irq_start,
352 u32 vic_sources, u32 resume_sources, 346 u32 vic_sources, u32 resume_sources,
353 struct device_node *node) 347 struct device_node *node)
354{ 348{
@@ -444,7 +438,7 @@ static int handle_one_vic(struct vic_device *vic, struct pt_regs *regs)
444 stat = readl_relaxed(vic->base + VIC_IRQ_STATUS); 438 stat = readl_relaxed(vic->base + VIC_IRQ_STATUS);
445 while (stat) { 439 while (stat) {
446 irq = ffs(stat) - 1; 440 irq = ffs(stat) - 1;
447 handle_IRQ(irq_domain_to_irq(&vic->domain, irq), regs); 441 handle_IRQ(irq_find_mapping(vic->domain, irq), regs);
448 stat &= ~(1 << irq); 442 stat &= ~(1 << irq);
449 handled = 1; 443 handled = 1;
450 } 444 }
diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
index b6e65dedfd71..23371b17b23e 100644
--- a/arch/arm/include/asm/assembler.h
+++ b/arch/arm/include/asm/assembler.h
@@ -137,6 +137,11 @@
137 disable_irq 137 disable_irq
138 .endm 138 .endm
139 139
140 .macro save_and_disable_irqs_notrace, oldcpsr
141 mrs \oldcpsr, cpsr
142 disable_irq_notrace
143 .endm
144
140/* 145/*
141 * Restore interrupt state previously stored in a register. We don't 146 * Restore interrupt state previously stored in a register. We don't
142 * guarantee that this will preserve the flags. 147 * guarantee that this will preserve the flags.
@@ -237,7 +242,7 @@
237 */ 242 */
238#ifdef CONFIG_THUMB2_KERNEL 243#ifdef CONFIG_THUMB2_KERNEL
239 244
240 .macro usraccoff, instr, reg, ptr, inc, off, cond, abort, t=T() 245 .macro usraccoff, instr, reg, ptr, inc, off, cond, abort, t=TUSER()
2419999: 2469999:
242 .if \inc == 1 247 .if \inc == 1
243 \instr\cond\()b\()\t\().w \reg, [\ptr, #\off] 248 \instr\cond\()b\()\t\().w \reg, [\ptr, #\off]
@@ -277,7 +282,7 @@
277 282
278#else /* !CONFIG_THUMB2_KERNEL */ 283#else /* !CONFIG_THUMB2_KERNEL */
279 284
280 .macro usracc, instr, reg, ptr, inc, cond, rept, abort, t=T() 285 .macro usracc, instr, reg, ptr, inc, cond, rept, abort, t=TUSER()
281 .rept \rept 286 .rept \rept
2829999: 2879999:
283 .if \inc == 1 288 .if \inc == 1
diff --git a/arch/arm/include/asm/domain.h b/arch/arm/include/asm/domain.h
index af18ceaacf5d..b5dc173d336f 100644
--- a/arch/arm/include/asm/domain.h
+++ b/arch/arm/include/asm/domain.h
@@ -83,9 +83,9 @@
83 * instructions (inline assembly) 83 * instructions (inline assembly)
84 */ 84 */
85#ifdef CONFIG_CPU_USE_DOMAINS 85#ifdef CONFIG_CPU_USE_DOMAINS
86#define T(instr) #instr "t" 86#define TUSER(instr) #instr "t"
87#else 87#else
88#define T(instr) #instr 88#define TUSER(instr) #instr
89#endif 89#endif
90 90
91#else /* __ASSEMBLY__ */ 91#else /* __ASSEMBLY__ */
@@ -95,9 +95,9 @@
95 * instructions 95 * instructions
96 */ 96 */
97#ifdef CONFIG_CPU_USE_DOMAINS 97#ifdef CONFIG_CPU_USE_DOMAINS
98#define T(instr) instr ## t 98#define TUSER(instr) instr ## t
99#else 99#else
100#define T(instr) instr 100#define TUSER(instr) instr
101#endif 101#endif
102 102
103#endif /* __ASSEMBLY__ */ 103#endif /* __ASSEMBLY__ */
diff --git a/arch/arm/include/asm/futex.h b/arch/arm/include/asm/futex.h
index 253cc86318bf..7be54690aeec 100644
--- a/arch/arm/include/asm/futex.h
+++ b/arch/arm/include/asm/futex.h
@@ -75,9 +75,9 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
75 75
76#define __futex_atomic_op(insn, ret, oldval, tmp, uaddr, oparg) \ 76#define __futex_atomic_op(insn, ret, oldval, tmp, uaddr, oparg) \
77 __asm__ __volatile__( \ 77 __asm__ __volatile__( \
78 "1: " T(ldr) " %1, [%3]\n" \ 78 "1: " TUSER(ldr) " %1, [%3]\n" \
79 " " insn "\n" \ 79 " " insn "\n" \
80 "2: " T(str) " %0, [%3]\n" \ 80 "2: " TUSER(str) " %0, [%3]\n" \
81 " mov %0, #0\n" \ 81 " mov %0, #0\n" \
82 __futex_atomic_ex_table("%5") \ 82 __futex_atomic_ex_table("%5") \
83 : "=&r" (ret), "=&r" (oldval), "=&r" (tmp) \ 83 : "=&r" (ret), "=&r" (oldval), "=&r" (tmp) \
@@ -95,10 +95,10 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
95 return -EFAULT; 95 return -EFAULT;
96 96
97 __asm__ __volatile__("@futex_atomic_cmpxchg_inatomic\n" 97 __asm__ __volatile__("@futex_atomic_cmpxchg_inatomic\n"
98 "1: " T(ldr) " %1, [%4]\n" 98 "1: " TUSER(ldr) " %1, [%4]\n"
99 " teq %1, %2\n" 99 " teq %1, %2\n"
100 " it eq @ explicit IT needed for the 2b label\n" 100 " it eq @ explicit IT needed for the 2b label\n"
101 "2: " T(streq) " %3, [%4]\n" 101 "2: " TUSER(streq) " %3, [%4]\n"
102 __futex_atomic_ex_table("%5") 102 __futex_atomic_ex_table("%5")
103 : "+r" (ret), "=&r" (val) 103 : "+r" (ret), "=&r" (val)
104 : "r" (oldval), "r" (newval), "r" (uaddr), "Ir" (-EFAULT) 104 : "r" (oldval), "r" (newval), "r" (uaddr), "Ir" (-EFAULT)
diff --git a/arch/arm/include/asm/hardware/gic.h b/arch/arm/include/asm/hardware/gic.h
index 4bdfe0018696..4b1ce6cd477f 100644
--- a/arch/arm/include/asm/hardware/gic.h
+++ b/arch/arm/include/asm/hardware/gic.h
@@ -39,7 +39,7 @@ struct device_node;
39extern struct irq_chip gic_arch_extn; 39extern struct irq_chip gic_arch_extn;
40 40
41void gic_init_bases(unsigned int, int, void __iomem *, void __iomem *, 41void gic_init_bases(unsigned int, int, void __iomem *, void __iomem *,
42 u32 offset); 42 u32 offset, struct device_node *);
43int gic_of_init(struct device_node *node, struct device_node *parent); 43int gic_of_init(struct device_node *node, struct device_node *parent);
44void gic_secondary_init(unsigned int); 44void gic_secondary_init(unsigned int);
45void gic_handle_irq(struct pt_regs *regs); 45void gic_handle_irq(struct pt_regs *regs);
@@ -49,7 +49,7 @@ void gic_raise_softirq(const struct cpumask *mask, unsigned int irq);
49static inline void gic_init(unsigned int nr, int start, 49static inline void gic_init(unsigned int nr, int start,
50 void __iomem *dist , void __iomem *cpu) 50 void __iomem *dist , void __iomem *cpu)
51{ 51{
52 gic_init_bases(nr, start, dist, cpu, 0); 52 gic_init_bases(nr, start, dist, cpu, 0, NULL);
53} 53}
54 54
55#endif 55#endif
diff --git a/arch/arm/include/asm/hardware/pl330.h b/arch/arm/include/asm/hardware/pl330.h
index 575fa8186ca0..c1821385abfa 100644
--- a/arch/arm/include/asm/hardware/pl330.h
+++ b/arch/arm/include/asm/hardware/pl330.h
@@ -41,7 +41,7 @@ enum pl330_dstcachectrl {
41 DCCTRL1, /* Bufferable only */ 41 DCCTRL1, /* Bufferable only */
42 DCCTRL2, /* Cacheable, but do not allocate */ 42 DCCTRL2, /* Cacheable, but do not allocate */
43 DCCTRL3, /* Cacheable and bufferable, but do not allocate */ 43 DCCTRL3, /* Cacheable and bufferable, but do not allocate */
44 DINVALID1 = 8, 44 DINVALID1, /* AWCACHE = 0x1000 */
45 DINVALID2, 45 DINVALID2,
46 DCCTRL6, /* Cacheable write-through, allocate on writes only */ 46 DCCTRL6, /* Cacheable write-through, allocate on writes only */
47 DCCTRL7, /* Cacheable write-back, allocate on writes only */ 47 DCCTRL7, /* Cacheable write-back, allocate on writes only */
diff --git a/arch/arm/include/asm/hardware/vic.h b/arch/arm/include/asm/hardware/vic.h
index f42ebd619590..e14af1a1a320 100644
--- a/arch/arm/include/asm/hardware/vic.h
+++ b/arch/arm/include/asm/hardware/vic.h
@@ -47,6 +47,8 @@
47struct device_node; 47struct device_node;
48struct pt_regs; 48struct pt_regs;
49 49
50void __vic_init(void __iomem *base, unsigned int irq_start, u32 vic_sources,
51 u32 resume_sources, struct device_node *node);
50void vic_init(void __iomem *base, unsigned int irq_start, u32 vic_sources, u32 resume_sources); 52void vic_init(void __iomem *base, unsigned int irq_start, u32 vic_sources, u32 resume_sources);
51int vic_of_init(struct device_node *node, struct device_node *parent); 53int vic_of_init(struct device_node *node, struct device_node *parent);
52void vic_handle_irq(struct pt_regs *regs); 54void vic_handle_irq(struct pt_regs *regs);
diff --git a/arch/arm/include/asm/highmem.h b/arch/arm/include/asm/highmem.h
index a4edd19dd3d6..8c5e828f484d 100644
--- a/arch/arm/include/asm/highmem.h
+++ b/arch/arm/include/asm/highmem.h
@@ -57,7 +57,7 @@ static inline void *kmap_high_get(struct page *page)
57#ifdef CONFIG_HIGHMEM 57#ifdef CONFIG_HIGHMEM
58extern void *kmap(struct page *page); 58extern void *kmap(struct page *page);
59extern void kunmap(struct page *page); 59extern void kunmap(struct page *page);
60extern void *__kmap_atomic(struct page *page); 60extern void *kmap_atomic(struct page *page);
61extern void __kunmap_atomic(void *kvaddr); 61extern void __kunmap_atomic(void *kvaddr);
62extern void *kmap_atomic_pfn(unsigned long pfn); 62extern void *kmap_atomic_pfn(unsigned long pfn);
63extern struct page *kmap_atomic_to_page(const void *ptr); 63extern struct page *kmap_atomic_to_page(const void *ptr);
diff --git a/arch/arm/include/asm/perf_event.h b/arch/arm/include/asm/perf_event.h
index 99cfe3607989..7523340afb8a 100644
--- a/arch/arm/include/asm/perf_event.h
+++ b/arch/arm/include/asm/perf_event.h
@@ -12,10 +12,6 @@
12#ifndef __ARM_PERF_EVENT_H__ 12#ifndef __ARM_PERF_EVENT_H__
13#define __ARM_PERF_EVENT_H__ 13#define __ARM_PERF_EVENT_H__
14 14
15/* ARM performance counters start from 1 (in the cp15 accesses) so use the
16 * same indexes here for consistency. */
17#define PERF_EVENT_INDEX_OFFSET 1
18
19/* ARM perf PMU IDs for use by internal perf clients. */ 15/* ARM perf PMU IDs for use by internal perf clients. */
20enum arm_perf_pmu_ids { 16enum arm_perf_pmu_ids {
21 ARM_PERF_PMU_ID_XSCALE1 = 0, 17 ARM_PERF_PMU_ID_XSCALE1 = 0,
diff --git a/arch/arm/include/asm/pmu.h b/arch/arm/include/asm/pmu.h
index b5a5be2536c1..90114faa9f3c 100644
--- a/arch/arm/include/asm/pmu.h
+++ b/arch/arm/include/asm/pmu.h
@@ -134,7 +134,7 @@ int __init armpmu_register(struct arm_pmu *armpmu, char *name, int type);
134 134
135u64 armpmu_event_update(struct perf_event *event, 135u64 armpmu_event_update(struct perf_event *event,
136 struct hw_perf_event *hwc, 136 struct hw_perf_event *hwc,
137 int idx, int overflow); 137 int idx);
138 138
139int armpmu_event_set_period(struct perf_event *event, 139int armpmu_event_set_period(struct perf_event *event,
140 struct hw_perf_event *hwc, 140 struct hw_perf_event *hwc,
diff --git a/arch/arm/include/asm/processor.h b/arch/arm/include/asm/processor.h
index ce280b8d613c..cb8d638924fd 100644
--- a/arch/arm/include/asm/processor.h
+++ b/arch/arm/include/asm/processor.h
@@ -22,6 +22,7 @@
22#include <asm/hw_breakpoint.h> 22#include <asm/hw_breakpoint.h>
23#include <asm/ptrace.h> 23#include <asm/ptrace.h>
24#include <asm/types.h> 24#include <asm/types.h>
25#include <asm/system.h>
25 26
26#ifdef __KERNEL__ 27#ifdef __KERNEL__
27#define STACK_TOP ((current->personality & ADDR_LIMIT_32BIT) ? \ 28#define STACK_TOP ((current->personality & ADDR_LIMIT_32BIT) ? \
diff --git a/arch/arm/include/asm/smp.h b/arch/arm/include/asm/smp.h
index 1e5717afc4ac..ae29293270a3 100644
--- a/arch/arm/include/asm/smp.h
+++ b/arch/arm/include/asm/smp.h
@@ -71,12 +71,6 @@ extern void platform_secondary_init(unsigned int cpu);
71extern void platform_smp_prepare_cpus(unsigned int); 71extern void platform_smp_prepare_cpus(unsigned int);
72 72
73/* 73/*
74 * Logical CPU mapping.
75 */
76extern int __cpu_logical_map[NR_CPUS];
77#define cpu_logical_map(cpu) __cpu_logical_map[cpu]
78
79/*
80 * Initial data for bringing up a secondary CPU. 74 * Initial data for bringing up a secondary CPU.
81 */ 75 */
82struct secondary_data { 76struct secondary_data {
diff --git a/arch/arm/include/asm/smp_plat.h b/arch/arm/include/asm/smp_plat.h
index f24c1b9e211d..558d6c80aca9 100644
--- a/arch/arm/include/asm/smp_plat.h
+++ b/arch/arm/include/asm/smp_plat.h
@@ -43,4 +43,10 @@ static inline int cache_ops_need_broadcast(void)
43} 43}
44#endif 44#endif
45 45
46/*
47 * Logical CPU mapping.
48 */
49extern int __cpu_logical_map[];
50#define cpu_logical_map(cpu) __cpu_logical_map[cpu]
51
46#endif 52#endif
diff --git a/arch/arm/include/asm/socket.h b/arch/arm/include/asm/socket.h
index dec6f9afb3cf..6433cadb6ed4 100644
--- a/arch/arm/include/asm/socket.h
+++ b/arch/arm/include/asm/socket.h
@@ -64,5 +64,9 @@
64 64
65#define SO_WIFI_STATUS 41 65#define SO_WIFI_STATUS 41
66#define SCM_WIFI_STATUS SO_WIFI_STATUS 66#define SCM_WIFI_STATUS SO_WIFI_STATUS
67#define SO_PEEK_OFF 42
68
69/* Instruct lower device to use last 4-bytes of skb data as FCS */
70#define SO_NOFCS 43
67 71
68#endif /* _ASM_SOCKET_H */ 72#endif /* _ASM_SOCKET_H */
diff --git a/arch/arm/include/asm/tlb.h b/arch/arm/include/asm/tlb.h
index 5d3ed7e38561..314d4664eae7 100644
--- a/arch/arm/include/asm/tlb.h
+++ b/arch/arm/include/asm/tlb.h
@@ -198,7 +198,15 @@ static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte,
198 unsigned long addr) 198 unsigned long addr)
199{ 199{
200 pgtable_page_dtor(pte); 200 pgtable_page_dtor(pte);
201 tlb_add_flush(tlb, addr); 201
202 /*
203 * With the classic ARM MMU, a pte page has two corresponding pmd
204 * entries, each covering 1MB.
205 */
206 addr &= PMD_MASK;
207 tlb_add_flush(tlb, addr + SZ_1M - PAGE_SIZE);
208 tlb_add_flush(tlb, addr + SZ_1M);
209
202 tlb_remove_page(tlb, pte); 210 tlb_remove_page(tlb, pte);
203} 211}
204 212
diff --git a/arch/arm/include/asm/uaccess.h b/arch/arm/include/asm/uaccess.h
index b293616a1a1a..2958976d867b 100644
--- a/arch/arm/include/asm/uaccess.h
+++ b/arch/arm/include/asm/uaccess.h
@@ -227,7 +227,7 @@ do { \
227 227
228#define __get_user_asm_byte(x,addr,err) \ 228#define __get_user_asm_byte(x,addr,err) \
229 __asm__ __volatile__( \ 229 __asm__ __volatile__( \
230 "1: " T(ldrb) " %1,[%2],#0\n" \ 230 "1: " TUSER(ldrb) " %1,[%2],#0\n" \
231 "2:\n" \ 231 "2:\n" \
232 " .pushsection .fixup,\"ax\"\n" \ 232 " .pushsection .fixup,\"ax\"\n" \
233 " .align 2\n" \ 233 " .align 2\n" \
@@ -263,7 +263,7 @@ do { \
263 263
264#define __get_user_asm_word(x,addr,err) \ 264#define __get_user_asm_word(x,addr,err) \
265 __asm__ __volatile__( \ 265 __asm__ __volatile__( \
266 "1: " T(ldr) " %1,[%2],#0\n" \ 266 "1: " TUSER(ldr) " %1,[%2],#0\n" \
267 "2:\n" \ 267 "2:\n" \
268 " .pushsection .fixup,\"ax\"\n" \ 268 " .pushsection .fixup,\"ax\"\n" \
269 " .align 2\n" \ 269 " .align 2\n" \
@@ -308,7 +308,7 @@ do { \
308 308
309#define __put_user_asm_byte(x,__pu_addr,err) \ 309#define __put_user_asm_byte(x,__pu_addr,err) \
310 __asm__ __volatile__( \ 310 __asm__ __volatile__( \
311 "1: " T(strb) " %1,[%2],#0\n" \ 311 "1: " TUSER(strb) " %1,[%2],#0\n" \
312 "2:\n" \ 312 "2:\n" \
313 " .pushsection .fixup,\"ax\"\n" \ 313 " .pushsection .fixup,\"ax\"\n" \
314 " .align 2\n" \ 314 " .align 2\n" \
@@ -341,7 +341,7 @@ do { \
341 341
342#define __put_user_asm_word(x,__pu_addr,err) \ 342#define __put_user_asm_word(x,__pu_addr,err) \
343 __asm__ __volatile__( \ 343 __asm__ __volatile__( \
344 "1: " T(str) " %1,[%2],#0\n" \ 344 "1: " TUSER(str) " %1,[%2],#0\n" \
345 "2:\n" \ 345 "2:\n" \
346 " .pushsection .fixup,\"ax\"\n" \ 346 " .pushsection .fixup,\"ax\"\n" \
347 " .align 2\n" \ 347 " .align 2\n" \
@@ -366,10 +366,10 @@ do { \
366 366
367#define __put_user_asm_dword(x,__pu_addr,err) \ 367#define __put_user_asm_dword(x,__pu_addr,err) \
368 __asm__ __volatile__( \ 368 __asm__ __volatile__( \
369 ARM( "1: " T(str) " " __reg_oper1 ", [%1], #4\n" ) \ 369 ARM( "1: " TUSER(str) " " __reg_oper1 ", [%1], #4\n" ) \
370 ARM( "2: " T(str) " " __reg_oper0 ", [%1]\n" ) \ 370 ARM( "2: " TUSER(str) " " __reg_oper0 ", [%1]\n" ) \
371 THUMB( "1: " T(str) " " __reg_oper1 ", [%1]\n" ) \ 371 THUMB( "1: " TUSER(str) " " __reg_oper1 ", [%1]\n" ) \
372 THUMB( "2: " T(str) " " __reg_oper0 ", [%1, #4]\n" ) \ 372 THUMB( "2: " TUSER(str) " " __reg_oper0 ", [%1, #4]\n" ) \
373 "3:\n" \ 373 "3:\n" \
374 " .pushsection .fixup,\"ax\"\n" \ 374 " .pushsection .fixup,\"ax\"\n" \
375 " .align 2\n" \ 375 " .align 2\n" \
diff --git a/arch/arm/kernel/ecard.c b/arch/arm/kernel/ecard.c
index 4dd0edab6a65..1651d4950744 100644
--- a/arch/arm/kernel/ecard.c
+++ b/arch/arm/kernel/ecard.c
@@ -242,6 +242,7 @@ static void ecard_init_pgtables(struct mm_struct *mm)
242 242
243 memcpy(dst_pgd, src_pgd, sizeof(pgd_t) * (EASI_SIZE / PGDIR_SIZE)); 243 memcpy(dst_pgd, src_pgd, sizeof(pgd_t) * (EASI_SIZE / PGDIR_SIZE));
244 244
245 vma.vm_flags = VM_EXEC;
245 vma.vm_mm = mm; 246 vma.vm_mm = mm;
246 247
247 flush_tlb_range(&vma, IO_START, IO_START + IO_SIZE); 248 flush_tlb_range(&vma, IO_START, IO_START + IO_SIZE);
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index 3a456c6c7005..be16a48007b4 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -790,7 +790,7 @@ __kuser_cmpxchg64: @ 0xffff0f60
790 smp_dmb arm 790 smp_dmb arm
791 rsbs r0, r3, #0 @ set returned val and C flag 791 rsbs r0, r3, #0 @ set returned val and C flag
792 ldmfd sp!, {r4, r5, r6, r7} 792 ldmfd sp!, {r4, r5, r6, r7}
793 bx lr 793 usr_ret lr
794 794
795#elif !defined(CONFIG_SMP) 795#elif !defined(CONFIG_SMP)
796 796
diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
index 520889cf1b5b..9fd0ba90c1d2 100644
--- a/arch/arm/kernel/entry-common.S
+++ b/arch/arm/kernel/entry-common.S
@@ -149,6 +149,11 @@ ENDPROC(ret_from_fork)
149#endif 149#endif
150#endif 150#endif
151 151
152.macro mcount_adjust_addr rd, rn
153 bic \rd, \rn, #1 @ clear the Thumb bit if present
154 sub \rd, \rd, #MCOUNT_INSN_SIZE
155.endm
156
152.macro __mcount suffix 157.macro __mcount suffix
153 mcount_enter 158 mcount_enter
154 ldr r0, =ftrace_trace_function 159 ldr r0, =ftrace_trace_function
@@ -173,8 +178,7 @@ ENDPROC(ret_from_fork)
173 mcount_exit 178 mcount_exit
174 179
1751: mcount_get_lr r1 @ lr of instrumented func 1801: mcount_get_lr r1 @ lr of instrumented func
176 mov r0, lr @ instrumented function 181 mcount_adjust_addr r0, lr @ instrumented function
177 sub r0, r0, #MCOUNT_INSN_SIZE
178 adr lr, BSYM(2f) 182 adr lr, BSYM(2f)
179 mov pc, r2 183 mov pc, r2
1802: mcount_exit 1842: mcount_exit
@@ -184,8 +188,7 @@ ENDPROC(ret_from_fork)
184 mcount_enter 188 mcount_enter
185 189
186 mcount_get_lr r1 @ lr of instrumented func 190 mcount_get_lr r1 @ lr of instrumented func
187 mov r0, lr @ instrumented function 191 mcount_adjust_addr r0, lr @ instrumented function
188 sub r0, r0, #MCOUNT_INSN_SIZE
189 192
190 .globl ftrace_call\suffix 193 .globl ftrace_call\suffix
191ftrace_call\suffix: 194ftrace_call\suffix:
@@ -205,11 +208,11 @@ ftrace_graph_call\suffix:
205#ifdef CONFIG_DYNAMIC_FTRACE 208#ifdef CONFIG_DYNAMIC_FTRACE
206 @ called from __ftrace_caller, saved in mcount_enter 209 @ called from __ftrace_caller, saved in mcount_enter
207 ldr r1, [sp, #16] @ instrumented routine (func) 210 ldr r1, [sp, #16] @ instrumented routine (func)
211 mcount_adjust_addr r1, r1
208#else 212#else
209 @ called from __mcount, untouched in lr 213 @ called from __mcount, untouched in lr
210 mov r1, lr @ instrumented routine (func) 214 mcount_adjust_addr r1, lr @ instrumented routine (func)
211#endif 215#endif
212 sub r1, r1, #MCOUNT_INSN_SIZE
213 mov r2, fp @ frame pointer 216 mov r2, fp @ frame pointer
214 bl prepare_ftrace_return 217 bl prepare_ftrace_return
215 mcount_exit 218 mcount_exit
diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
index 5bb91bf3d47f..8a89d3b7626b 100644
--- a/arch/arm/kernel/perf_event.c
+++ b/arch/arm/kernel/perf_event.c
@@ -180,7 +180,7 @@ armpmu_event_set_period(struct perf_event *event,
180u64 180u64
181armpmu_event_update(struct perf_event *event, 181armpmu_event_update(struct perf_event *event,
182 struct hw_perf_event *hwc, 182 struct hw_perf_event *hwc,
183 int idx, int overflow) 183 int idx)
184{ 184{
185 struct arm_pmu *armpmu = to_arm_pmu(event->pmu); 185 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
186 u64 delta, prev_raw_count, new_raw_count; 186 u64 delta, prev_raw_count, new_raw_count;
@@ -193,13 +193,7 @@ again:
193 new_raw_count) != prev_raw_count) 193 new_raw_count) != prev_raw_count)
194 goto again; 194 goto again;
195 195
196 new_raw_count &= armpmu->max_period; 196 delta = (new_raw_count - prev_raw_count) & armpmu->max_period;
197 prev_raw_count &= armpmu->max_period;
198
199 if (overflow)
200 delta = armpmu->max_period - prev_raw_count + new_raw_count + 1;
201 else
202 delta = new_raw_count - prev_raw_count;
203 197
204 local64_add(delta, &event->count); 198 local64_add(delta, &event->count);
205 local64_sub(delta, &hwc->period_left); 199 local64_sub(delta, &hwc->period_left);
@@ -216,7 +210,7 @@ armpmu_read(struct perf_event *event)
216 if (hwc->idx < 0) 210 if (hwc->idx < 0)
217 return; 211 return;
218 212
219 armpmu_event_update(event, hwc, hwc->idx, 0); 213 armpmu_event_update(event, hwc, hwc->idx);
220} 214}
221 215
222static void 216static void
@@ -232,7 +226,7 @@ armpmu_stop(struct perf_event *event, int flags)
232 if (!(hwc->state & PERF_HES_STOPPED)) { 226 if (!(hwc->state & PERF_HES_STOPPED)) {
233 armpmu->disable(hwc, hwc->idx); 227 armpmu->disable(hwc, hwc->idx);
234 barrier(); /* why? */ 228 barrier(); /* why? */
235 armpmu_event_update(event, hwc, hwc->idx, 0); 229 armpmu_event_update(event, hwc, hwc->idx);
236 hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; 230 hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
237 } 231 }
238} 232}
@@ -518,7 +512,13 @@ __hw_perf_event_init(struct perf_event *event)
518 hwc->config_base |= (unsigned long)mapping; 512 hwc->config_base |= (unsigned long)mapping;
519 513
520 if (!hwc->sample_period) { 514 if (!hwc->sample_period) {
521 hwc->sample_period = armpmu->max_period; 515 /*
516 * For non-sampling runs, limit the sample_period to half
517 * of the counter width. That way, the new counter value
518 * is far less likely to overtake the previous one unless
519 * you have some serious IRQ latency issues.
520 */
521 hwc->sample_period = armpmu->max_period >> 1;
522 hwc->last_period = hwc->sample_period; 522 hwc->last_period = hwc->sample_period;
523 local64_set(&hwc->period_left, hwc->sample_period); 523 local64_set(&hwc->period_left, hwc->sample_period);
524 } 524 }
@@ -539,6 +539,10 @@ static int armpmu_event_init(struct perf_event *event)
539 int err = 0; 539 int err = 0;
540 atomic_t *active_events = &armpmu->active_events; 540 atomic_t *active_events = &armpmu->active_events;
541 541
542 /* does not support taken branch sampling */
543 if (has_branch_stack(event))
544 return -EOPNOTSUPP;
545
542 if (armpmu->map_event(event) == -ENOENT) 546 if (armpmu->map_event(event) == -ENOENT)
543 return -ENOENT; 547 return -ENOENT;
544 548
@@ -680,6 +684,28 @@ static void __init cpu_pmu_init(struct arm_pmu *armpmu)
680} 684}
681 685
682/* 686/*
687 * PMU hardware loses all context when a CPU goes offline.
688 * When a CPU is hotplugged back in, since some hardware registers are
689 * UNKNOWN at reset, the PMU must be explicitly reset to avoid reading
690 * junk values out of them.
691 */
692static int __cpuinit pmu_cpu_notify(struct notifier_block *b,
693 unsigned long action, void *hcpu)
694{
695 if ((action & ~CPU_TASKS_FROZEN) != CPU_STARTING)
696 return NOTIFY_DONE;
697
698 if (cpu_pmu && cpu_pmu->reset)
699 cpu_pmu->reset(NULL);
700
701 return NOTIFY_OK;
702}
703
704static struct notifier_block __cpuinitdata pmu_cpu_notifier = {
705 .notifier_call = pmu_cpu_notify,
706};
707
708/*
683 * CPU PMU identification and registration. 709 * CPU PMU identification and registration.
684 */ 710 */
685static int __init 711static int __init
@@ -730,6 +756,7 @@ init_hw_perf_events(void)
730 pr_info("enabled with %s PMU driver, %d counters available\n", 756 pr_info("enabled with %s PMU driver, %d counters available\n",
731 cpu_pmu->name, cpu_pmu->num_events); 757 cpu_pmu->name, cpu_pmu->num_events);
732 cpu_pmu_init(cpu_pmu); 758 cpu_pmu_init(cpu_pmu);
759 register_cpu_notifier(&pmu_cpu_notifier);
733 armpmu_register(cpu_pmu, "cpu", PERF_TYPE_RAW); 760 armpmu_register(cpu_pmu, "cpu", PERF_TYPE_RAW);
734 } else { 761 } else {
735 pr_info("no hardware support available\n"); 762 pr_info("no hardware support available\n");
diff --git a/arch/arm/kernel/perf_event_v6.c b/arch/arm/kernel/perf_event_v6.c
index 533be9930ec2..b78af0cc6ef3 100644
--- a/arch/arm/kernel/perf_event_v6.c
+++ b/arch/arm/kernel/perf_event_v6.c
@@ -467,23 +467,6 @@ armv6pmu_enable_event(struct hw_perf_event *hwc,
467 raw_spin_unlock_irqrestore(&events->pmu_lock, flags); 467 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
468} 468}
469 469
470static int counter_is_active(unsigned long pmcr, int idx)
471{
472 unsigned long mask = 0;
473 if (idx == ARMV6_CYCLE_COUNTER)
474 mask = ARMV6_PMCR_CCOUNT_IEN;
475 else if (idx == ARMV6_COUNTER0)
476 mask = ARMV6_PMCR_COUNT0_IEN;
477 else if (idx == ARMV6_COUNTER1)
478 mask = ARMV6_PMCR_COUNT1_IEN;
479
480 if (mask)
481 return pmcr & mask;
482
483 WARN_ONCE(1, "invalid counter number (%d)\n", idx);
484 return 0;
485}
486
487static irqreturn_t 470static irqreturn_t
488armv6pmu_handle_irq(int irq_num, 471armv6pmu_handle_irq(int irq_num,
489 void *dev) 472 void *dev)
@@ -513,7 +496,8 @@ armv6pmu_handle_irq(int irq_num,
513 struct perf_event *event = cpuc->events[idx]; 496 struct perf_event *event = cpuc->events[idx];
514 struct hw_perf_event *hwc; 497 struct hw_perf_event *hwc;
515 498
516 if (!counter_is_active(pmcr, idx)) 499 /* Ignore if we don't have an event. */
500 if (!event)
517 continue; 501 continue;
518 502
519 /* 503 /*
@@ -524,7 +508,7 @@ armv6pmu_handle_irq(int irq_num,
524 continue; 508 continue;
525 509
526 hwc = &event->hw; 510 hwc = &event->hw;
527 armpmu_event_update(event, hwc, idx, 1); 511 armpmu_event_update(event, hwc, idx);
528 data.period = event->hw.last_period; 512 data.period = event->hw.last_period;
529 if (!armpmu_event_set_period(event, hwc, idx)) 513 if (!armpmu_event_set_period(event, hwc, idx))
530 continue; 514 continue;
diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c
index 460bbbb6b885..4d7095af2ab3 100644
--- a/arch/arm/kernel/perf_event_v7.c
+++ b/arch/arm/kernel/perf_event_v7.c
@@ -469,6 +469,20 @@ static const unsigned armv7_a5_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
469 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, 469 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
470 }, 470 },
471 }, 471 },
472 [C(NODE)] = {
473 [C(OP_READ)] = {
474 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
475 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
476 },
477 [C(OP_WRITE)] = {
478 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
479 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
480 },
481 [C(OP_PREFETCH)] = {
482 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
483 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
484 },
485 },
472}; 486};
473 487
474/* 488/*
@@ -579,6 +593,20 @@ static const unsigned armv7_a15_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
579 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, 593 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
580 }, 594 },
581 }, 595 },
596 [C(NODE)] = {
597 [C(OP_READ)] = {
598 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
599 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
600 },
601 [C(OP_WRITE)] = {
602 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
603 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
604 },
605 [C(OP_PREFETCH)] = {
606 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
607 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
608 },
609 },
582}; 610};
583 611
584/* 612/*
@@ -781,6 +809,11 @@ static inline int armv7_pmnc_disable_intens(int idx)
781 809
782 counter = ARMV7_IDX_TO_COUNTER(idx); 810 counter = ARMV7_IDX_TO_COUNTER(idx);
783 asm volatile("mcr p15, 0, %0, c9, c14, 2" : : "r" (BIT(counter))); 811 asm volatile("mcr p15, 0, %0, c9, c14, 2" : : "r" (BIT(counter)));
812 isb();
813 /* Clear the overflow flag in case an interrupt is pending. */
814 asm volatile("mcr p15, 0, %0, c9, c12, 3" : : "r" (BIT(counter)));
815 isb();
816
784 return idx; 817 return idx;
785} 818}
786 819
@@ -927,6 +960,10 @@ static irqreturn_t armv7pmu_handle_irq(int irq_num, void *dev)
927 struct perf_event *event = cpuc->events[idx]; 960 struct perf_event *event = cpuc->events[idx];
928 struct hw_perf_event *hwc; 961 struct hw_perf_event *hwc;
929 962
963 /* Ignore if we don't have an event. */
964 if (!event)
965 continue;
966
930 /* 967 /*
931 * We have a single interrupt for all counters. Check that 968 * We have a single interrupt for all counters. Check that
932 * each counter has overflowed before we process it. 969 * each counter has overflowed before we process it.
@@ -935,7 +972,7 @@ static irqreturn_t armv7pmu_handle_irq(int irq_num, void *dev)
935 continue; 972 continue;
936 973
937 hwc = &event->hw; 974 hwc = &event->hw;
938 armpmu_event_update(event, hwc, idx, 1); 975 armpmu_event_update(event, hwc, idx);
939 data.period = event->hw.last_period; 976 data.period = event->hw.last_period;
940 if (!armpmu_event_set_period(event, hwc, idx)) 977 if (!armpmu_event_set_period(event, hwc, idx))
941 continue; 978 continue;
diff --git a/arch/arm/kernel/perf_event_xscale.c b/arch/arm/kernel/perf_event_xscale.c
index 3b99d8269829..71a21e6712f5 100644
--- a/arch/arm/kernel/perf_event_xscale.c
+++ b/arch/arm/kernel/perf_event_xscale.c
@@ -255,11 +255,14 @@ xscale1pmu_handle_irq(int irq_num, void *dev)
255 struct perf_event *event = cpuc->events[idx]; 255 struct perf_event *event = cpuc->events[idx];
256 struct hw_perf_event *hwc; 256 struct hw_perf_event *hwc;
257 257
258 if (!event)
259 continue;
260
258 if (!xscale1_pmnc_counter_has_overflowed(pmnc, idx)) 261 if (!xscale1_pmnc_counter_has_overflowed(pmnc, idx))
259 continue; 262 continue;
260 263
261 hwc = &event->hw; 264 hwc = &event->hw;
262 armpmu_event_update(event, hwc, idx, 1); 265 armpmu_event_update(event, hwc, idx);
263 data.period = event->hw.last_period; 266 data.period = event->hw.last_period;
264 if (!armpmu_event_set_period(event, hwc, idx)) 267 if (!armpmu_event_set_period(event, hwc, idx))
265 continue; 268 continue;
@@ -592,11 +595,14 @@ xscale2pmu_handle_irq(int irq_num, void *dev)
592 struct perf_event *event = cpuc->events[idx]; 595 struct perf_event *event = cpuc->events[idx];
593 struct hw_perf_event *hwc; 596 struct hw_perf_event *hwc;
594 597
595 if (!xscale2_pmnc_counter_has_overflowed(pmnc, idx)) 598 if (!event)
599 continue;
600
601 if (!xscale2_pmnc_counter_has_overflowed(of_flags, idx))
596 continue; 602 continue;
597 603
598 hwc = &event->hw; 604 hwc = &event->hw;
599 armpmu_event_update(event, hwc, idx, 1); 605 armpmu_event_update(event, hwc, idx);
600 data.period = event->hw.last_period; 606 data.period = event->hw.last_period;
601 if (!armpmu_event_set_period(event, hwc, idx)) 607 if (!armpmu_event_set_period(event, hwc, idx))
602 continue; 608 continue;
@@ -663,7 +669,7 @@ xscale2pmu_enable_event(struct hw_perf_event *hwc, int idx)
663static void 669static void
664xscale2pmu_disable_event(struct hw_perf_event *hwc, int idx) 670xscale2pmu_disable_event(struct hw_perf_event *hwc, int idx)
665{ 671{
666 unsigned long flags, ien, evtsel; 672 unsigned long flags, ien, evtsel, of_flags;
667 struct pmu_hw_events *events = cpu_pmu->get_hw_events(); 673 struct pmu_hw_events *events = cpu_pmu->get_hw_events();
668 674
669 ien = xscale2pmu_read_int_enable(); 675 ien = xscale2pmu_read_int_enable();
@@ -672,26 +678,31 @@ xscale2pmu_disable_event(struct hw_perf_event *hwc, int idx)
672 switch (idx) { 678 switch (idx) {
673 case XSCALE_CYCLE_COUNTER: 679 case XSCALE_CYCLE_COUNTER:
674 ien &= ~XSCALE2_CCOUNT_INT_EN; 680 ien &= ~XSCALE2_CCOUNT_INT_EN;
681 of_flags = XSCALE2_CCOUNT_OVERFLOW;
675 break; 682 break;
676 case XSCALE_COUNTER0: 683 case XSCALE_COUNTER0:
677 ien &= ~XSCALE2_COUNT0_INT_EN; 684 ien &= ~XSCALE2_COUNT0_INT_EN;
678 evtsel &= ~XSCALE2_COUNT0_EVT_MASK; 685 evtsel &= ~XSCALE2_COUNT0_EVT_MASK;
679 evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT0_EVT_SHFT; 686 evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT0_EVT_SHFT;
687 of_flags = XSCALE2_COUNT0_OVERFLOW;
680 break; 688 break;
681 case XSCALE_COUNTER1: 689 case XSCALE_COUNTER1:
682 ien &= ~XSCALE2_COUNT1_INT_EN; 690 ien &= ~XSCALE2_COUNT1_INT_EN;
683 evtsel &= ~XSCALE2_COUNT1_EVT_MASK; 691 evtsel &= ~XSCALE2_COUNT1_EVT_MASK;
684 evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT1_EVT_SHFT; 692 evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT1_EVT_SHFT;
693 of_flags = XSCALE2_COUNT1_OVERFLOW;
685 break; 694 break;
686 case XSCALE_COUNTER2: 695 case XSCALE_COUNTER2:
687 ien &= ~XSCALE2_COUNT2_INT_EN; 696 ien &= ~XSCALE2_COUNT2_INT_EN;
688 evtsel &= ~XSCALE2_COUNT2_EVT_MASK; 697 evtsel &= ~XSCALE2_COUNT2_EVT_MASK;
689 evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT2_EVT_SHFT; 698 evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT2_EVT_SHFT;
699 of_flags = XSCALE2_COUNT2_OVERFLOW;
690 break; 700 break;
691 case XSCALE_COUNTER3: 701 case XSCALE_COUNTER3:
692 ien &= ~XSCALE2_COUNT3_INT_EN; 702 ien &= ~XSCALE2_COUNT3_INT_EN;
693 evtsel &= ~XSCALE2_COUNT3_EVT_MASK; 703 evtsel &= ~XSCALE2_COUNT3_EVT_MASK;
694 evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT3_EVT_SHFT; 704 evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT3_EVT_SHFT;
705 of_flags = XSCALE2_COUNT3_OVERFLOW;
695 break; 706 break;
696 default: 707 default:
697 WARN_ONCE(1, "invalid counter number (%d)\n", idx); 708 WARN_ONCE(1, "invalid counter number (%d)\n", idx);
@@ -701,6 +712,7 @@ xscale2pmu_disable_event(struct hw_perf_event *hwc, int idx)
701 raw_spin_lock_irqsave(&events->pmu_lock, flags); 712 raw_spin_lock_irqsave(&events->pmu_lock, flags);
702 xscale2pmu_write_event_select(evtsel); 713 xscale2pmu_write_event_select(evtsel);
703 xscale2pmu_write_int_enable(ien); 714 xscale2pmu_write_int_enable(ien);
715 xscale2pmu_write_overflow_flags(of_flags);
704 raw_spin_unlock_irqrestore(&events->pmu_lock, flags); 716 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
705} 717}
706 718
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index 971d65c253a9..c2ae3cd331fe 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -239,9 +239,7 @@ void cpu_idle(void)
239 leds_event(led_idle_end); 239 leds_event(led_idle_end);
240 rcu_idle_exit(); 240 rcu_idle_exit();
241 tick_nohz_idle_exit(); 241 tick_nohz_idle_exit();
242 preempt_enable_no_resched(); 242 schedule_preempt_disabled();
243 schedule();
244 preempt_disable();
245 } 243 }
246} 244}
247 245
diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
index e1d5e1929fbd..ede6443c34d9 100644
--- a/arch/arm/kernel/ptrace.c
+++ b/arch/arm/kernel/ptrace.c
@@ -23,6 +23,7 @@
23#include <linux/perf_event.h> 23#include <linux/perf_event.h>
24#include <linux/hw_breakpoint.h> 24#include <linux/hw_breakpoint.h>
25#include <linux/regset.h> 25#include <linux/regset.h>
26#include <linux/audit.h>
26 27
27#include <asm/pgtable.h> 28#include <asm/pgtable.h>
28#include <asm/system.h> 29#include <asm/system.h>
@@ -699,10 +700,13 @@ static int vfp_set(struct task_struct *target,
699{ 700{
700 int ret; 701 int ret;
701 struct thread_info *thread = task_thread_info(target); 702 struct thread_info *thread = task_thread_info(target);
702 struct vfp_hard_struct new_vfp = thread->vfpstate.hard; 703 struct vfp_hard_struct new_vfp;
703 const size_t user_fpregs_offset = offsetof(struct user_vfp, fpregs); 704 const size_t user_fpregs_offset = offsetof(struct user_vfp, fpregs);
704 const size_t user_fpscr_offset = offsetof(struct user_vfp, fpscr); 705 const size_t user_fpscr_offset = offsetof(struct user_vfp, fpscr);
705 706
707 vfp_sync_hwstate(thread);
708 new_vfp = thread->vfpstate.hard;
709
706 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, 710 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
707 &new_vfp.fpregs, 711 &new_vfp.fpregs,
708 user_fpregs_offset, 712 user_fpregs_offset,
@@ -723,9 +727,8 @@ static int vfp_set(struct task_struct *target,
723 if (ret) 727 if (ret)
724 return ret; 728 return ret;
725 729
726 vfp_sync_hwstate(thread);
727 thread->vfpstate.hard = new_vfp;
728 vfp_flush_hwstate(thread); 730 vfp_flush_hwstate(thread);
731 thread->vfpstate.hard = new_vfp;
729 732
730 return 0; 733 return 0;
731} 734}
@@ -902,6 +905,12 @@ long arch_ptrace(struct task_struct *child, long request,
902 return ret; 905 return ret;
903} 906}
904 907
908#ifdef __ARMEB__
909#define AUDIT_ARCH_NR AUDIT_ARCH_ARMEB
910#else
911#define AUDIT_ARCH_NR AUDIT_ARCH_ARM
912#endif
913
905asmlinkage int syscall_trace(int why, struct pt_regs *regs, int scno) 914asmlinkage int syscall_trace(int why, struct pt_regs *regs, int scno)
906{ 915{
907 unsigned long ip; 916 unsigned long ip;
@@ -916,7 +925,7 @@ asmlinkage int syscall_trace(int why, struct pt_regs *regs, int scno)
916 if (!ip) 925 if (!ip)
917 audit_syscall_exit(regs); 926 audit_syscall_exit(regs);
918 else 927 else
919 audit_syscall_entry(AUDIT_ARCH_ARMEB, scno, regs->ARM_r0, 928 audit_syscall_entry(AUDIT_ARCH_NR, scno, regs->ARM_r0,
920 regs->ARM_r1, regs->ARM_r2, regs->ARM_r3); 929 regs->ARM_r1, regs->ARM_r2, regs->ARM_r3);
921 930
922 if (!test_thread_flag(TIF_SYSCALL_TRACE)) 931 if (!test_thread_flag(TIF_SYSCALL_TRACE))
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 129fbd55bde8..a255c39612ca 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -21,7 +21,6 @@
21#include <linux/init.h> 21#include <linux/init.h>
22#include <linux/kexec.h> 22#include <linux/kexec.h>
23#include <linux/of_fdt.h> 23#include <linux/of_fdt.h>
24#include <linux/crash_dump.h>
25#include <linux/root_dev.h> 24#include <linux/root_dev.h>
26#include <linux/cpu.h> 25#include <linux/cpu.h>
27#include <linux/interrupt.h> 26#include <linux/interrupt.h>
@@ -160,7 +159,7 @@ static struct resource mem_res[] = {
160 .flags = IORESOURCE_MEM 159 .flags = IORESOURCE_MEM
161 }, 160 },
162 { 161 {
163 .name = "Kernel text", 162 .name = "Kernel code",
164 .start = 0, 163 .start = 0,
165 .end = 0, 164 .end = 0,
166 .flags = IORESOURCE_MEM 165 .flags = IORESOURCE_MEM
@@ -427,6 +426,20 @@ void cpu_init(void)
427 : "r14"); 426 : "r14");
428} 427}
429 428
429int __cpu_logical_map[NR_CPUS];
430
431void __init smp_setup_processor_id(void)
432{
433 int i;
434 u32 cpu = is_smp() ? read_cpuid_mpidr() & 0xff : 0;
435
436 cpu_logical_map(0) = cpu;
437 for (i = 1; i < NR_CPUS; ++i)
438 cpu_logical_map(i) = i == cpu ? 0 : i;
439
440 printk(KERN_INFO "Booting Linux on physical CPU %d\n", cpu);
441}
442
430static void __init setup_processor(void) 443static void __init setup_processor(void)
431{ 444{
432 struct proc_info_list *list; 445 struct proc_info_list *list;
diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c
index 0340224cf73c..9e617bd4a146 100644
--- a/arch/arm/kernel/signal.c
+++ b/arch/arm/kernel/signal.c
@@ -227,6 +227,8 @@ static int restore_vfp_context(struct vfp_sigframe __user *frame)
227 if (magic != VFP_MAGIC || size != VFP_STORAGE_SIZE) 227 if (magic != VFP_MAGIC || size != VFP_STORAGE_SIZE)
228 return -EINVAL; 228 return -EINVAL;
229 229
230 vfp_flush_hwstate(thread);
231
230 /* 232 /*
231 * Copy the floating point registers. There can be unused 233 * Copy the floating point registers. There can be unused
232 * registers see asm/hwcap.h for details. 234 * registers see asm/hwcap.h for details.
@@ -251,9 +253,6 @@ static int restore_vfp_context(struct vfp_sigframe __user *frame)
251 __get_user_error(h->fpinst, &frame->ufp_exc.fpinst, err); 253 __get_user_error(h->fpinst, &frame->ufp_exc.fpinst, err);
252 __get_user_error(h->fpinst2, &frame->ufp_exc.fpinst2, err); 254 __get_user_error(h->fpinst2, &frame->ufp_exc.fpinst2, err);
253 255
254 if (!err)
255 vfp_flush_hwstate(thread);
256
257 return err ? -EFAULT : 0; 256 return err ? -EFAULT : 0;
258} 257}
259 258
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index 57db122a4f62..d616ed51e7a7 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -233,20 +233,6 @@ void __ref cpu_die(void)
233} 233}
234#endif /* CONFIG_HOTPLUG_CPU */ 234#endif /* CONFIG_HOTPLUG_CPU */
235 235
236int __cpu_logical_map[NR_CPUS];
237
238void __init smp_setup_processor_id(void)
239{
240 int i;
241 u32 cpu = is_smp() ? read_cpuid_mpidr() & 0xff : 0;
242
243 cpu_logical_map(0) = cpu;
244 for (i = 1; i < NR_CPUS; ++i)
245 cpu_logical_map(i) = i == cpu ? 0 : i;
246
247 printk(KERN_INFO "Booting Linux on physical CPU %d\n", cpu);
248}
249
250/* 236/*
251 * Called by both boot and secondaries to move global data into 237 * Called by both boot and secondaries to move global data into
252 * per-processor storage. 238 * per-processor storage.
@@ -309,13 +295,6 @@ asmlinkage void __cpuinit secondary_start_kernel(void)
309 */ 295 */
310 percpu_timer_setup(); 296 percpu_timer_setup();
311 297
312 while (!cpu_active(cpu))
313 cpu_relax();
314
315 /*
316 * cpu_active bit is set, so it's safe to enalbe interrupts
317 * now.
318 */
319 local_irq_enable(); 298 local_irq_enable();
320 local_fiq_enable(); 299 local_fiq_enable();
321 300
@@ -443,9 +422,7 @@ static DEFINE_PER_CPU(struct clock_event_device, percpu_clockevent);
443static void ipi_timer(void) 422static void ipi_timer(void)
444{ 423{
445 struct clock_event_device *evt = &__get_cpu_var(percpu_clockevent); 424 struct clock_event_device *evt = &__get_cpu_var(percpu_clockevent);
446 irq_enter();
447 evt->event_handler(evt); 425 evt->event_handler(evt);
448 irq_exit();
449} 426}
450 427
451#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST 428#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
@@ -548,7 +525,9 @@ void handle_IPI(int ipinr, struct pt_regs *regs)
548 525
549 switch (ipinr) { 526 switch (ipinr) {
550 case IPI_TIMER: 527 case IPI_TIMER:
528 irq_enter();
551 ipi_timer(); 529 ipi_timer();
530 irq_exit();
552 break; 531 break;
553 532
554 case IPI_RESCHEDULE: 533 case IPI_RESCHEDULE:
@@ -556,15 +535,21 @@ void handle_IPI(int ipinr, struct pt_regs *regs)
556 break; 535 break;
557 536
558 case IPI_CALL_FUNC: 537 case IPI_CALL_FUNC:
538 irq_enter();
559 generic_smp_call_function_interrupt(); 539 generic_smp_call_function_interrupt();
540 irq_exit();
560 break; 541 break;
561 542
562 case IPI_CALL_FUNC_SINGLE: 543 case IPI_CALL_FUNC_SINGLE:
544 irq_enter();
563 generic_smp_call_function_single_interrupt(); 545 generic_smp_call_function_single_interrupt();
546 irq_exit();
564 break; 547 break;
565 548
566 case IPI_CPU_STOP: 549 case IPI_CPU_STOP:
550 irq_enter();
567 ipi_cpu_stop(cpu); 551 ipi_cpu_stop(cpu);
552 irq_exit();
568 break; 553 break;
569 554
570 default: 555 default:
diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c
index c8e938553d47..7a79b24597b2 100644
--- a/arch/arm/kernel/smp_twd.c
+++ b/arch/arm/kernel/smp_twd.c
@@ -129,7 +129,7 @@ static struct notifier_block twd_cpufreq_nb = {
129 129
130static int twd_cpufreq_init(void) 130static int twd_cpufreq_init(void)
131{ 131{
132 if (!IS_ERR(twd_clk)) 132 if (twd_evt && *__this_cpu_ptr(twd_evt) && !IS_ERR(twd_clk))
133 return cpufreq_register_notifier(&twd_cpufreq_nb, 133 return cpufreq_register_notifier(&twd_cpufreq_nb,
134 CPUFREQ_TRANSITION_NOTIFIER); 134 CPUFREQ_TRANSITION_NOTIFIER);
135 135
@@ -252,6 +252,8 @@ void __cpuinit twd_timer_setup(struct clock_event_device *clk)
252 else 252 else
253 twd_calibrate_rate(); 253 twd_calibrate_rate();
254 254
255 __raw_writel(0, twd_base + TWD_TIMER_CONTROL);
256
255 clk->name = "local_timer"; 257 clk->name = "local_timer";
256 clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | 258 clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT |
257 CLOCK_EVT_FEAT_C3STOP; 259 CLOCK_EVT_FEAT_C3STOP;
diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
index 99a572702509..f84dfe67724f 100644
--- a/arch/arm/kernel/traps.c
+++ b/arch/arm/kernel/traps.c
@@ -266,6 +266,7 @@ void die(const char *str, struct pt_regs *regs, int err)
266{ 266{
267 struct thread_info *thread = current_thread_info(); 267 struct thread_info *thread = current_thread_info();
268 int ret; 268 int ret;
269 enum bug_trap_type bug_type = BUG_TRAP_TYPE_NONE;
269 270
270 oops_enter(); 271 oops_enter();
271 272
@@ -273,7 +274,9 @@ void die(const char *str, struct pt_regs *regs, int err)
273 console_verbose(); 274 console_verbose();
274 bust_spinlocks(1); 275 bust_spinlocks(1);
275 if (!user_mode(regs)) 276 if (!user_mode(regs))
276 report_bug(regs->ARM_pc, regs); 277 bug_type = report_bug(regs->ARM_pc, regs);
278 if (bug_type != BUG_TRAP_TYPE_NONE)
279 str = "Oops - BUG";
277 ret = __die(str, err, thread, regs); 280 ret = __die(str, err, thread, regs);
278 281
279 if (regs && kexec_should_crash(thread->task)) 282 if (regs && kexec_should_crash(thread->task))
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
index f76e75548670..43a31fb06318 100644
--- a/arch/arm/kernel/vmlinux.lds.S
+++ b/arch/arm/kernel/vmlinux.lds.S
@@ -4,11 +4,13 @@
4 */ 4 */
5 5
6#include <asm-generic/vmlinux.lds.h> 6#include <asm-generic/vmlinux.lds.h>
7#include <asm/cache.h>
7#include <asm/thread_info.h> 8#include <asm/thread_info.h>
8#include <asm/memory.h> 9#include <asm/memory.h>
9#include <asm/page.h> 10#include <asm/page.h>
10 11
11#define PROC_INFO \ 12#define PROC_INFO \
13 . = ALIGN(4); \
12 VMLINUX_SYMBOL(__proc_info_begin) = .; \ 14 VMLINUX_SYMBOL(__proc_info_begin) = .; \
13 *(.proc.info.init) \ 15 *(.proc.info.init) \
14 VMLINUX_SYMBOL(__proc_info_end) = .; 16 VMLINUX_SYMBOL(__proc_info_end) = .;
@@ -181,7 +183,7 @@ SECTIONS
181 } 183 }
182#endif 184#endif
183 185
184 PERCPU_SECTION(32) 186 PERCPU_SECTION(L1_CACHE_BYTES)
185 187
186#ifdef CONFIG_XIP_KERNEL 188#ifdef CONFIG_XIP_KERNEL
187 __data_loc = ALIGN(4); /* location in binary */ 189 __data_loc = ALIGN(4); /* location in binary */
@@ -212,13 +214,13 @@ SECTIONS
212#endif 214#endif
213 215
214 NOSAVE_DATA 216 NOSAVE_DATA
215 CACHELINE_ALIGNED_DATA(32) 217 CACHELINE_ALIGNED_DATA(L1_CACHE_BYTES)
216 READ_MOSTLY_DATA(32) 218 READ_MOSTLY_DATA(L1_CACHE_BYTES)
217 219
218 /* 220 /*
219 * The exception fixup table (might need resorting at runtime) 221 * The exception fixup table (might need resorting at runtime)
220 */ 222 */
221 . = ALIGN(32); 223 . = ALIGN(4);
222 __start___ex_table = .; 224 __start___ex_table = .;
223#ifdef CONFIG_MMU 225#ifdef CONFIG_MMU
224 *(__ex_table) 226 *(__ex_table)
diff --git a/arch/arm/lib/getuser.S b/arch/arm/lib/getuser.S
index 1b049cd7a49a..11093a7c3e32 100644
--- a/arch/arm/lib/getuser.S
+++ b/arch/arm/lib/getuser.S
@@ -31,18 +31,18 @@
31#include <asm/domain.h> 31#include <asm/domain.h>
32 32
33ENTRY(__get_user_1) 33ENTRY(__get_user_1)
341: T(ldrb) r2, [r0] 341: TUSER(ldrb) r2, [r0]
35 mov r0, #0 35 mov r0, #0
36 mov pc, lr 36 mov pc, lr
37ENDPROC(__get_user_1) 37ENDPROC(__get_user_1)
38 38
39ENTRY(__get_user_2) 39ENTRY(__get_user_2)
40#ifdef CONFIG_THUMB2_KERNEL 40#ifdef CONFIG_THUMB2_KERNEL
412: T(ldrb) r2, [r0] 412: TUSER(ldrb) r2, [r0]
423: T(ldrb) r3, [r0, #1] 423: TUSER(ldrb) r3, [r0, #1]
43#else 43#else
442: T(ldrb) r2, [r0], #1 442: TUSER(ldrb) r2, [r0], #1
453: T(ldrb) r3, [r0] 453: TUSER(ldrb) r3, [r0]
46#endif 46#endif
47#ifndef __ARMEB__ 47#ifndef __ARMEB__
48 orr r2, r2, r3, lsl #8 48 orr r2, r2, r3, lsl #8
@@ -54,7 +54,7 @@ ENTRY(__get_user_2)
54ENDPROC(__get_user_2) 54ENDPROC(__get_user_2)
55 55
56ENTRY(__get_user_4) 56ENTRY(__get_user_4)
574: T(ldr) r2, [r0] 574: TUSER(ldr) r2, [r0]
58 mov r0, #0 58 mov r0, #0
59 mov pc, lr 59 mov pc, lr
60ENDPROC(__get_user_4) 60ENDPROC(__get_user_4)
diff --git a/arch/arm/lib/putuser.S b/arch/arm/lib/putuser.S
index c023fc11e86c..7db25990c589 100644
--- a/arch/arm/lib/putuser.S
+++ b/arch/arm/lib/putuser.S
@@ -31,7 +31,7 @@
31#include <asm/domain.h> 31#include <asm/domain.h>
32 32
33ENTRY(__put_user_1) 33ENTRY(__put_user_1)
341: T(strb) r2, [r0] 341: TUSER(strb) r2, [r0]
35 mov r0, #0 35 mov r0, #0
36 mov pc, lr 36 mov pc, lr
37ENDPROC(__put_user_1) 37ENDPROC(__put_user_1)
@@ -40,19 +40,19 @@ ENTRY(__put_user_2)
40 mov ip, r2, lsr #8 40 mov ip, r2, lsr #8
41#ifdef CONFIG_THUMB2_KERNEL 41#ifdef CONFIG_THUMB2_KERNEL
42#ifndef __ARMEB__ 42#ifndef __ARMEB__
432: T(strb) r2, [r0] 432: TUSER(strb) r2, [r0]
443: T(strb) ip, [r0, #1] 443: TUSER(strb) ip, [r0, #1]
45#else 45#else
462: T(strb) ip, [r0] 462: TUSER(strb) ip, [r0]
473: T(strb) r2, [r0, #1] 473: TUSER(strb) r2, [r0, #1]
48#endif 48#endif
49#else /* !CONFIG_THUMB2_KERNEL */ 49#else /* !CONFIG_THUMB2_KERNEL */
50#ifndef __ARMEB__ 50#ifndef __ARMEB__
512: T(strb) r2, [r0], #1 512: TUSER(strb) r2, [r0], #1
523: T(strb) ip, [r0] 523: TUSER(strb) ip, [r0]
53#else 53#else
542: T(strb) ip, [r0], #1 542: TUSER(strb) ip, [r0], #1
553: T(strb) r2, [r0] 553: TUSER(strb) r2, [r0]
56#endif 56#endif
57#endif /* CONFIG_THUMB2_KERNEL */ 57#endif /* CONFIG_THUMB2_KERNEL */
58 mov r0, #0 58 mov r0, #0
@@ -60,18 +60,18 @@ ENTRY(__put_user_2)
60ENDPROC(__put_user_2) 60ENDPROC(__put_user_2)
61 61
62ENTRY(__put_user_4) 62ENTRY(__put_user_4)
634: T(str) r2, [r0] 634: TUSER(str) r2, [r0]
64 mov r0, #0 64 mov r0, #0
65 mov pc, lr 65 mov pc, lr
66ENDPROC(__put_user_4) 66ENDPROC(__put_user_4)
67 67
68ENTRY(__put_user_8) 68ENTRY(__put_user_8)
69#ifdef CONFIG_THUMB2_KERNEL 69#ifdef CONFIG_THUMB2_KERNEL
705: T(str) r2, [r0] 705: TUSER(str) r2, [r0]
716: T(str) r3, [r0, #4] 716: TUSER(str) r3, [r0, #4]
72#else 72#else
735: T(str) r2, [r0], #4 735: TUSER(str) r2, [r0], #4
746: T(str) r3, [r0] 746: TUSER(str) r3, [r0]
75#endif 75#endif
76 mov r0, #0 76 mov r0, #0
77 mov pc, lr 77 mov pc, lr
diff --git a/arch/arm/lib/uaccess.S b/arch/arm/lib/uaccess.S
index d0ece2aeb70d..5c908b1cb8ed 100644
--- a/arch/arm/lib/uaccess.S
+++ b/arch/arm/lib/uaccess.S
@@ -32,11 +32,11 @@
32 rsb ip, ip, #4 32 rsb ip, ip, #4
33 cmp ip, #2 33 cmp ip, #2
34 ldrb r3, [r1], #1 34 ldrb r3, [r1], #1
35USER( T(strb) r3, [r0], #1) @ May fault 35USER( TUSER( strb) r3, [r0], #1) @ May fault
36 ldrgeb r3, [r1], #1 36 ldrgeb r3, [r1], #1
37USER( T(strgeb) r3, [r0], #1) @ May fault 37USER( TUSER( strgeb) r3, [r0], #1) @ May fault
38 ldrgtb r3, [r1], #1 38 ldrgtb r3, [r1], #1
39USER( T(strgtb) r3, [r0], #1) @ May fault 39USER( TUSER( strgtb) r3, [r0], #1) @ May fault
40 sub r2, r2, ip 40 sub r2, r2, ip
41 b .Lc2u_dest_aligned 41 b .Lc2u_dest_aligned
42 42
@@ -59,7 +59,7 @@ ENTRY(__copy_to_user)
59 addmi ip, r2, #4 59 addmi ip, r2, #4
60 bmi .Lc2u_0nowords 60 bmi .Lc2u_0nowords
61 ldr r3, [r1], #4 61 ldr r3, [r1], #4
62USER( T(str) r3, [r0], #4) @ May fault 62USER( TUSER( str) r3, [r0], #4) @ May fault
63 mov ip, r0, lsl #32 - PAGE_SHIFT @ On each page, use a ld/st??t instruction 63 mov ip, r0, lsl #32 - PAGE_SHIFT @ On each page, use a ld/st??t instruction
64 rsb ip, ip, #0 64 rsb ip, ip, #0
65 movs ip, ip, lsr #32 - PAGE_SHIFT 65 movs ip, ip, lsr #32 - PAGE_SHIFT
@@ -88,18 +88,18 @@ USER( T(str) r3, [r0], #4) @ May fault
88 stmneia r0!, {r3 - r4} @ Shouldnt fault 88 stmneia r0!, {r3 - r4} @ Shouldnt fault
89 tst ip, #4 89 tst ip, #4
90 ldrne r3, [r1], #4 90 ldrne r3, [r1], #4
91 T(strne) r3, [r0], #4 @ Shouldnt fault 91 TUSER( strne) r3, [r0], #4 @ Shouldnt fault
92 ands ip, ip, #3 92 ands ip, ip, #3
93 beq .Lc2u_0fupi 93 beq .Lc2u_0fupi
94.Lc2u_0nowords: teq ip, #0 94.Lc2u_0nowords: teq ip, #0
95 beq .Lc2u_finished 95 beq .Lc2u_finished
96.Lc2u_nowords: cmp ip, #2 96.Lc2u_nowords: cmp ip, #2
97 ldrb r3, [r1], #1 97 ldrb r3, [r1], #1
98USER( T(strb) r3, [r0], #1) @ May fault 98USER( TUSER( strb) r3, [r0], #1) @ May fault
99 ldrgeb r3, [r1], #1 99 ldrgeb r3, [r1], #1
100USER( T(strgeb) r3, [r0], #1) @ May fault 100USER( TUSER( strgeb) r3, [r0], #1) @ May fault
101 ldrgtb r3, [r1], #1 101 ldrgtb r3, [r1], #1
102USER( T(strgtb) r3, [r0], #1) @ May fault 102USER( TUSER( strgtb) r3, [r0], #1) @ May fault
103 b .Lc2u_finished 103 b .Lc2u_finished
104 104
105.Lc2u_not_enough: 105.Lc2u_not_enough:
@@ -120,7 +120,7 @@ USER( T(strgtb) r3, [r0], #1) @ May fault
120 mov r3, r7, pull #8 120 mov r3, r7, pull #8
121 ldr r7, [r1], #4 121 ldr r7, [r1], #4
122 orr r3, r3, r7, push #24 122 orr r3, r3, r7, push #24
123USER( T(str) r3, [r0], #4) @ May fault 123USER( TUSER( str) r3, [r0], #4) @ May fault
124 mov ip, r0, lsl #32 - PAGE_SHIFT 124 mov ip, r0, lsl #32 - PAGE_SHIFT
125 rsb ip, ip, #0 125 rsb ip, ip, #0
126 movs ip, ip, lsr #32 - PAGE_SHIFT 126 movs ip, ip, lsr #32 - PAGE_SHIFT
@@ -155,18 +155,18 @@ USER( T(str) r3, [r0], #4) @ May fault
155 movne r3, r7, pull #8 155 movne r3, r7, pull #8
156 ldrne r7, [r1], #4 156 ldrne r7, [r1], #4
157 orrne r3, r3, r7, push #24 157 orrne r3, r3, r7, push #24
158 T(strne) r3, [r0], #4 @ Shouldnt fault 158 TUSER( strne) r3, [r0], #4 @ Shouldnt fault
159 ands ip, ip, #3 159 ands ip, ip, #3
160 beq .Lc2u_1fupi 160 beq .Lc2u_1fupi
161.Lc2u_1nowords: mov r3, r7, get_byte_1 161.Lc2u_1nowords: mov r3, r7, get_byte_1
162 teq ip, #0 162 teq ip, #0
163 beq .Lc2u_finished 163 beq .Lc2u_finished
164 cmp ip, #2 164 cmp ip, #2
165USER( T(strb) r3, [r0], #1) @ May fault 165USER( TUSER( strb) r3, [r0], #1) @ May fault
166 movge r3, r7, get_byte_2 166 movge r3, r7, get_byte_2
167USER( T(strgeb) r3, [r0], #1) @ May fault 167USER( TUSER( strgeb) r3, [r0], #1) @ May fault
168 movgt r3, r7, get_byte_3 168 movgt r3, r7, get_byte_3
169USER( T(strgtb) r3, [r0], #1) @ May fault 169USER( TUSER( strgtb) r3, [r0], #1) @ May fault
170 b .Lc2u_finished 170 b .Lc2u_finished
171 171
172.Lc2u_2fupi: subs r2, r2, #4 172.Lc2u_2fupi: subs r2, r2, #4
@@ -175,7 +175,7 @@ USER( T(strgtb) r3, [r0], #1) @ May fault
175 mov r3, r7, pull #16 175 mov r3, r7, pull #16
176 ldr r7, [r1], #4 176 ldr r7, [r1], #4
177 orr r3, r3, r7, push #16 177 orr r3, r3, r7, push #16
178USER( T(str) r3, [r0], #4) @ May fault 178USER( TUSER( str) r3, [r0], #4) @ May fault
179 mov ip, r0, lsl #32 - PAGE_SHIFT 179 mov ip, r0, lsl #32 - PAGE_SHIFT
180 rsb ip, ip, #0 180 rsb ip, ip, #0
181 movs ip, ip, lsr #32 - PAGE_SHIFT 181 movs ip, ip, lsr #32 - PAGE_SHIFT
@@ -210,18 +210,18 @@ USER( T(str) r3, [r0], #4) @ May fault
210 movne r3, r7, pull #16 210 movne r3, r7, pull #16
211 ldrne r7, [r1], #4 211 ldrne r7, [r1], #4
212 orrne r3, r3, r7, push #16 212 orrne r3, r3, r7, push #16
213 T(strne) r3, [r0], #4 @ Shouldnt fault 213 TUSER( strne) r3, [r0], #4 @ Shouldnt fault
214 ands ip, ip, #3 214 ands ip, ip, #3
215 beq .Lc2u_2fupi 215 beq .Lc2u_2fupi
216.Lc2u_2nowords: mov r3, r7, get_byte_2 216.Lc2u_2nowords: mov r3, r7, get_byte_2
217 teq ip, #0 217 teq ip, #0
218 beq .Lc2u_finished 218 beq .Lc2u_finished
219 cmp ip, #2 219 cmp ip, #2
220USER( T(strb) r3, [r0], #1) @ May fault 220USER( TUSER( strb) r3, [r0], #1) @ May fault
221 movge r3, r7, get_byte_3 221 movge r3, r7, get_byte_3
222USER( T(strgeb) r3, [r0], #1) @ May fault 222USER( TUSER( strgeb) r3, [r0], #1) @ May fault
223 ldrgtb r3, [r1], #0 223 ldrgtb r3, [r1], #0
224USER( T(strgtb) r3, [r0], #1) @ May fault 224USER( TUSER( strgtb) r3, [r0], #1) @ May fault
225 b .Lc2u_finished 225 b .Lc2u_finished
226 226
227.Lc2u_3fupi: subs r2, r2, #4 227.Lc2u_3fupi: subs r2, r2, #4
@@ -230,7 +230,7 @@ USER( T(strgtb) r3, [r0], #1) @ May fault
230 mov r3, r7, pull #24 230 mov r3, r7, pull #24
231 ldr r7, [r1], #4 231 ldr r7, [r1], #4
232 orr r3, r3, r7, push #8 232 orr r3, r3, r7, push #8
233USER( T(str) r3, [r0], #4) @ May fault 233USER( TUSER( str) r3, [r0], #4) @ May fault
234 mov ip, r0, lsl #32 - PAGE_SHIFT 234 mov ip, r0, lsl #32 - PAGE_SHIFT
235 rsb ip, ip, #0 235 rsb ip, ip, #0
236 movs ip, ip, lsr #32 - PAGE_SHIFT 236 movs ip, ip, lsr #32 - PAGE_SHIFT
@@ -265,18 +265,18 @@ USER( T(str) r3, [r0], #4) @ May fault
265 movne r3, r7, pull #24 265 movne r3, r7, pull #24
266 ldrne r7, [r1], #4 266 ldrne r7, [r1], #4
267 orrne r3, r3, r7, push #8 267 orrne r3, r3, r7, push #8
268 T(strne) r3, [r0], #4 @ Shouldnt fault 268 TUSER( strne) r3, [r0], #4 @ Shouldnt fault
269 ands ip, ip, #3 269 ands ip, ip, #3
270 beq .Lc2u_3fupi 270 beq .Lc2u_3fupi
271.Lc2u_3nowords: mov r3, r7, get_byte_3 271.Lc2u_3nowords: mov r3, r7, get_byte_3
272 teq ip, #0 272 teq ip, #0
273 beq .Lc2u_finished 273 beq .Lc2u_finished
274 cmp ip, #2 274 cmp ip, #2
275USER( T(strb) r3, [r0], #1) @ May fault 275USER( TUSER( strb) r3, [r0], #1) @ May fault
276 ldrgeb r3, [r1], #1 276 ldrgeb r3, [r1], #1
277USER( T(strgeb) r3, [r0], #1) @ May fault 277USER( TUSER( strgeb) r3, [r0], #1) @ May fault
278 ldrgtb r3, [r1], #0 278 ldrgtb r3, [r1], #0
279USER( T(strgtb) r3, [r0], #1) @ May fault 279USER( TUSER( strgtb) r3, [r0], #1) @ May fault
280 b .Lc2u_finished 280 b .Lc2u_finished
281ENDPROC(__copy_to_user) 281ENDPROC(__copy_to_user)
282 282
@@ -295,11 +295,11 @@ ENDPROC(__copy_to_user)
295.Lcfu_dest_not_aligned: 295.Lcfu_dest_not_aligned:
296 rsb ip, ip, #4 296 rsb ip, ip, #4
297 cmp ip, #2 297 cmp ip, #2
298USER( T(ldrb) r3, [r1], #1) @ May fault 298USER( TUSER( ldrb) r3, [r1], #1) @ May fault
299 strb r3, [r0], #1 299 strb r3, [r0], #1
300USER( T(ldrgeb) r3, [r1], #1) @ May fault 300USER( TUSER( ldrgeb) r3, [r1], #1) @ May fault
301 strgeb r3, [r0], #1 301 strgeb r3, [r0], #1
302USER( T(ldrgtb) r3, [r1], #1) @ May fault 302USER( TUSER( ldrgtb) r3, [r1], #1) @ May fault
303 strgtb r3, [r0], #1 303 strgtb r3, [r0], #1
304 sub r2, r2, ip 304 sub r2, r2, ip
305 b .Lcfu_dest_aligned 305 b .Lcfu_dest_aligned
@@ -322,7 +322,7 @@ ENTRY(__copy_from_user)
322.Lcfu_0fupi: subs r2, r2, #4 322.Lcfu_0fupi: subs r2, r2, #4
323 addmi ip, r2, #4 323 addmi ip, r2, #4
324 bmi .Lcfu_0nowords 324 bmi .Lcfu_0nowords
325USER( T(ldr) r3, [r1], #4) 325USER( TUSER( ldr) r3, [r1], #4)
326 str r3, [r0], #4 326 str r3, [r0], #4
327 mov ip, r1, lsl #32 - PAGE_SHIFT @ On each page, use a ld/st??t instruction 327 mov ip, r1, lsl #32 - PAGE_SHIFT @ On each page, use a ld/st??t instruction
328 rsb ip, ip, #0 328 rsb ip, ip, #0
@@ -351,18 +351,18 @@ USER( T(ldr) r3, [r1], #4)
351 ldmneia r1!, {r3 - r4} @ Shouldnt fault 351 ldmneia r1!, {r3 - r4} @ Shouldnt fault
352 stmneia r0!, {r3 - r4} 352 stmneia r0!, {r3 - r4}
353 tst ip, #4 353 tst ip, #4
354 T(ldrne) r3, [r1], #4 @ Shouldnt fault 354 TUSER( ldrne) r3, [r1], #4 @ Shouldnt fault
355 strne r3, [r0], #4 355 strne r3, [r0], #4
356 ands ip, ip, #3 356 ands ip, ip, #3
357 beq .Lcfu_0fupi 357 beq .Lcfu_0fupi
358.Lcfu_0nowords: teq ip, #0 358.Lcfu_0nowords: teq ip, #0
359 beq .Lcfu_finished 359 beq .Lcfu_finished
360.Lcfu_nowords: cmp ip, #2 360.Lcfu_nowords: cmp ip, #2
361USER( T(ldrb) r3, [r1], #1) @ May fault 361USER( TUSER( ldrb) r3, [r1], #1) @ May fault
362 strb r3, [r0], #1 362 strb r3, [r0], #1
363USER( T(ldrgeb) r3, [r1], #1) @ May fault 363USER( TUSER( ldrgeb) r3, [r1], #1) @ May fault
364 strgeb r3, [r0], #1 364 strgeb r3, [r0], #1
365USER( T(ldrgtb) r3, [r1], #1) @ May fault 365USER( TUSER( ldrgtb) r3, [r1], #1) @ May fault
366 strgtb r3, [r0], #1 366 strgtb r3, [r0], #1
367 b .Lcfu_finished 367 b .Lcfu_finished
368 368
@@ -375,7 +375,7 @@ USER( T(ldrgtb) r3, [r1], #1) @ May fault
375 375
376.Lcfu_src_not_aligned: 376.Lcfu_src_not_aligned:
377 bic r1, r1, #3 377 bic r1, r1, #3
378USER( T(ldr) r7, [r1], #4) @ May fault 378USER( TUSER( ldr) r7, [r1], #4) @ May fault
379 cmp ip, #2 379 cmp ip, #2
380 bgt .Lcfu_3fupi 380 bgt .Lcfu_3fupi
381 beq .Lcfu_2fupi 381 beq .Lcfu_2fupi
@@ -383,7 +383,7 @@ USER( T(ldr) r7, [r1], #4) @ May fault
383 addmi ip, r2, #4 383 addmi ip, r2, #4
384 bmi .Lcfu_1nowords 384 bmi .Lcfu_1nowords
385 mov r3, r7, pull #8 385 mov r3, r7, pull #8
386USER( T(ldr) r7, [r1], #4) @ May fault 386USER( TUSER( ldr) r7, [r1], #4) @ May fault
387 orr r3, r3, r7, push #24 387 orr r3, r3, r7, push #24
388 str r3, [r0], #4 388 str r3, [r0], #4
389 mov ip, r1, lsl #32 - PAGE_SHIFT 389 mov ip, r1, lsl #32 - PAGE_SHIFT
@@ -418,7 +418,7 @@ USER( T(ldr) r7, [r1], #4) @ May fault
418 stmneia r0!, {r3 - r4} 418 stmneia r0!, {r3 - r4}
419 tst ip, #4 419 tst ip, #4
420 movne r3, r7, pull #8 420 movne r3, r7, pull #8
421USER( T(ldrne) r7, [r1], #4) @ May fault 421USER( TUSER( ldrne) r7, [r1], #4) @ May fault
422 orrne r3, r3, r7, push #24 422 orrne r3, r3, r7, push #24
423 strne r3, [r0], #4 423 strne r3, [r0], #4
424 ands ip, ip, #3 424 ands ip, ip, #3
@@ -438,7 +438,7 @@ USER( T(ldrne) r7, [r1], #4) @ May fault
438 addmi ip, r2, #4 438 addmi ip, r2, #4
439 bmi .Lcfu_2nowords 439 bmi .Lcfu_2nowords
440 mov r3, r7, pull #16 440 mov r3, r7, pull #16
441USER( T(ldr) r7, [r1], #4) @ May fault 441USER( TUSER( ldr) r7, [r1], #4) @ May fault
442 orr r3, r3, r7, push #16 442 orr r3, r3, r7, push #16
443 str r3, [r0], #4 443 str r3, [r0], #4
444 mov ip, r1, lsl #32 - PAGE_SHIFT 444 mov ip, r1, lsl #32 - PAGE_SHIFT
@@ -474,7 +474,7 @@ USER( T(ldr) r7, [r1], #4) @ May fault
474 stmneia r0!, {r3 - r4} 474 stmneia r0!, {r3 - r4}
475 tst ip, #4 475 tst ip, #4
476 movne r3, r7, pull #16 476 movne r3, r7, pull #16
477USER( T(ldrne) r7, [r1], #4) @ May fault 477USER( TUSER( ldrne) r7, [r1], #4) @ May fault
478 orrne r3, r3, r7, push #16 478 orrne r3, r3, r7, push #16
479 strne r3, [r0], #4 479 strne r3, [r0], #4
480 ands ip, ip, #3 480 ands ip, ip, #3
@@ -486,7 +486,7 @@ USER( T(ldrne) r7, [r1], #4) @ May fault
486 strb r3, [r0], #1 486 strb r3, [r0], #1
487 movge r3, r7, get_byte_3 487 movge r3, r7, get_byte_3
488 strgeb r3, [r0], #1 488 strgeb r3, [r0], #1
489USER( T(ldrgtb) r3, [r1], #0) @ May fault 489USER( TUSER( ldrgtb) r3, [r1], #0) @ May fault
490 strgtb r3, [r0], #1 490 strgtb r3, [r0], #1
491 b .Lcfu_finished 491 b .Lcfu_finished
492 492
@@ -494,7 +494,7 @@ USER( T(ldrgtb) r3, [r1], #0) @ May fault
494 addmi ip, r2, #4 494 addmi ip, r2, #4
495 bmi .Lcfu_3nowords 495 bmi .Lcfu_3nowords
496 mov r3, r7, pull #24 496 mov r3, r7, pull #24
497USER( T(ldr) r7, [r1], #4) @ May fault 497USER( TUSER( ldr) r7, [r1], #4) @ May fault
498 orr r3, r3, r7, push #8 498 orr r3, r3, r7, push #8
499 str r3, [r0], #4 499 str r3, [r0], #4
500 mov ip, r1, lsl #32 - PAGE_SHIFT 500 mov ip, r1, lsl #32 - PAGE_SHIFT
@@ -529,7 +529,7 @@ USER( T(ldr) r7, [r1], #4) @ May fault
529 stmneia r0!, {r3 - r4} 529 stmneia r0!, {r3 - r4}
530 tst ip, #4 530 tst ip, #4
531 movne r3, r7, pull #24 531 movne r3, r7, pull #24
532USER( T(ldrne) r7, [r1], #4) @ May fault 532USER( TUSER( ldrne) r7, [r1], #4) @ May fault
533 orrne r3, r3, r7, push #8 533 orrne r3, r3, r7, push #8
534 strne r3, [r0], #4 534 strne r3, [r0], #4
535 ands ip, ip, #3 535 ands ip, ip, #3
@@ -539,9 +539,9 @@ USER( T(ldrne) r7, [r1], #4) @ May fault
539 beq .Lcfu_finished 539 beq .Lcfu_finished
540 cmp ip, #2 540 cmp ip, #2
541 strb r3, [r0], #1 541 strb r3, [r0], #1
542USER( T(ldrgeb) r3, [r1], #1) @ May fault 542USER( TUSER( ldrgeb) r3, [r1], #1) @ May fault
543 strgeb r3, [r0], #1 543 strgeb r3, [r0], #1
544USER( T(ldrgtb) r3, [r1], #1) @ May fault 544USER( TUSER( ldrgtb) r3, [r1], #1) @ May fault
545 strgtb r3, [r0], #1 545 strgtb r3, [r0], #1
546 b .Lcfu_finished 546 b .Lcfu_finished
547ENDPROC(__copy_from_user) 547ENDPROC(__copy_from_user)
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 4f991f295284..71feb00a1e99 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -18,6 +18,12 @@ config HAVE_AT91_USART4
18config HAVE_AT91_USART5 18config HAVE_AT91_USART5
19 bool 19 bool
20 20
21config AT91_SAM9_ALT_RESET
22 bool
23
24config AT91_SAM9G45_RESET
25 bool
26
21menu "Atmel AT91 System-on-Chip" 27menu "Atmel AT91 System-on-Chip"
22 28
23choice 29choice
@@ -39,6 +45,7 @@ config ARCH_AT91SAM9260
39 select HAVE_AT91_USART4 45 select HAVE_AT91_USART4
40 select HAVE_AT91_USART5 46 select HAVE_AT91_USART5
41 select HAVE_NET_MACB 47 select HAVE_NET_MACB
48 select AT91_SAM9_ALT_RESET
42 49
43config ARCH_AT91SAM9261 50config ARCH_AT91SAM9261
44 bool "AT91SAM9261" 51 bool "AT91SAM9261"
@@ -46,6 +53,7 @@ config ARCH_AT91SAM9261
46 select GENERIC_CLOCKEVENTS 53 select GENERIC_CLOCKEVENTS
47 select HAVE_FB_ATMEL 54 select HAVE_FB_ATMEL
48 select HAVE_AT91_DBGU0 55 select HAVE_AT91_DBGU0
56 select AT91_SAM9_ALT_RESET
49 57
50config ARCH_AT91SAM9G10 58config ARCH_AT91SAM9G10
51 bool "AT91SAM9G10" 59 bool "AT91SAM9G10"
@@ -53,6 +61,7 @@ config ARCH_AT91SAM9G10
53 select GENERIC_CLOCKEVENTS 61 select GENERIC_CLOCKEVENTS
54 select HAVE_AT91_DBGU0 62 select HAVE_AT91_DBGU0
55 select HAVE_FB_ATMEL 63 select HAVE_FB_ATMEL
64 select AT91_SAM9_ALT_RESET
56 65
57config ARCH_AT91SAM9263 66config ARCH_AT91SAM9263
58 bool "AT91SAM9263" 67 bool "AT91SAM9263"
@@ -61,6 +70,7 @@ config ARCH_AT91SAM9263
61 select HAVE_FB_ATMEL 70 select HAVE_FB_ATMEL
62 select HAVE_NET_MACB 71 select HAVE_NET_MACB
63 select HAVE_AT91_DBGU1 72 select HAVE_AT91_DBGU1
73 select AT91_SAM9_ALT_RESET
64 74
65config ARCH_AT91SAM9RL 75config ARCH_AT91SAM9RL
66 bool "AT91SAM9RL" 76 bool "AT91SAM9RL"
@@ -69,6 +79,7 @@ config ARCH_AT91SAM9RL
69 select HAVE_AT91_USART3 79 select HAVE_AT91_USART3
70 select HAVE_FB_ATMEL 80 select HAVE_FB_ATMEL
71 select HAVE_AT91_DBGU0 81 select HAVE_AT91_DBGU0
82 select AT91_SAM9_ALT_RESET
72 83
73config ARCH_AT91SAM9G20 84config ARCH_AT91SAM9G20
74 bool "AT91SAM9G20" 85 bool "AT91SAM9G20"
@@ -79,6 +90,7 @@ config ARCH_AT91SAM9G20
79 select HAVE_AT91_USART4 90 select HAVE_AT91_USART4
80 select HAVE_AT91_USART5 91 select HAVE_AT91_USART5
81 select HAVE_NET_MACB 92 select HAVE_NET_MACB
93 select AT91_SAM9_ALT_RESET
82 94
83config ARCH_AT91SAM9G45 95config ARCH_AT91SAM9G45
84 bool "AT91SAM9G45" 96 bool "AT91SAM9G45"
@@ -88,6 +100,7 @@ config ARCH_AT91SAM9G45
88 select HAVE_FB_ATMEL 100 select HAVE_FB_ATMEL
89 select HAVE_NET_MACB 101 select HAVE_NET_MACB
90 select HAVE_AT91_DBGU1 102 select HAVE_AT91_DBGU1
103 select AT91_SAM9G45_RESET
91 104
92config ARCH_AT91CAP9 105config ARCH_AT91CAP9
93 bool "AT91CAP9" 106 bool "AT91CAP9"
@@ -96,6 +109,7 @@ config ARCH_AT91CAP9
96 select HAVE_FB_ATMEL 109 select HAVE_FB_ATMEL
97 select HAVE_NET_MACB 110 select HAVE_NET_MACB
98 select HAVE_AT91_DBGU1 111 select HAVE_AT91_DBGU1
112 select AT91_SAM9G45_RESET
99 113
100config ARCH_AT91X40 114config ARCH_AT91X40
101 bool "AT91x40" 115 bool "AT91x40"
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 242174f9f355..705e1fbded39 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -8,15 +8,17 @@ obj-n :=
8obj- := 8obj- :=
9 9
10obj-$(CONFIG_AT91_PMC_UNIT) += clock.o 10obj-$(CONFIG_AT91_PMC_UNIT) += clock.o
11obj-$(CONFIG_AT91_SAM9_ALT_RESET) += at91sam9_alt_reset.o
12obj-$(CONFIG_AT91_SAM9G45_RESET) += at91sam9g45_reset.o
11 13
12# CPU-specific support 14# CPU-specific support
13obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200.o at91rm9200_time.o at91rm9200_devices.o 15obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200.o at91rm9200_time.o at91rm9200_devices.o
14obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o at91sam9_alt_reset.o 16obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o
15obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o at91sam9_alt_reset.o 17obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o
16obj-$(CONFIG_ARCH_AT91SAM9G10) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o at91sam9_alt_reset.o 18obj-$(CONFIG_ARCH_AT91SAM9G10) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o
17obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o sam9_smc.o at91sam9_alt_reset.o 19obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o sam9_smc.o
18obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o sam9_smc.o at91sam9_alt_reset.o 20obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o sam9_smc.o
19obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o at91sam9_alt_reset.o 21obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o
20obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o 22obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o
21obj-$(CONFIG_ARCH_AT91CAP9) += at91cap9.o at91sam926x_time.o at91cap9_devices.o sam9_smc.o 23obj-$(CONFIG_ARCH_AT91CAP9) += at91cap9.o at91sam926x_time.o at91cap9_devices.o sam9_smc.o
22obj-$(CONFIG_ARCH_AT91X40) += at91x40.o at91x40_time.o 24obj-$(CONFIG_ARCH_AT91X40) += at91x40.o at91x40_time.o
diff --git a/arch/arm/mach-at91/at91cap9.c b/arch/arm/mach-at91/at91cap9.c
index edb879ac04c8..a42edc25a87e 100644
--- a/arch/arm/mach-at91/at91cap9.c
+++ b/arch/arm/mach-at91/at91cap9.c
@@ -21,7 +21,6 @@
21#include <mach/cpu.h> 21#include <mach/cpu.h>
22#include <mach/at91cap9.h> 22#include <mach/at91cap9.h>
23#include <mach/at91_pmc.h> 23#include <mach/at91_pmc.h>
24#include <mach/at91_rstc.h>
25 24
26#include "soc.h" 25#include "soc.h"
27#include "generic.h" 26#include "generic.h"
@@ -314,11 +313,6 @@ static struct at91_gpio_bank at91cap9_gpio[] __initdata = {
314 } 313 }
315}; 314};
316 315
317static void at91cap9_restart(char mode, const char *cmd)
318{
319 at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
320}
321
322/* -------------------------------------------------------------------- 316/* --------------------------------------------------------------------
323 * AT91CAP9 processor initialization 317 * AT91CAP9 processor initialization
324 * -------------------------------------------------------------------- */ 318 * -------------------------------------------------------------------- */
@@ -331,13 +325,14 @@ static void __init at91cap9_map_io(void)
331static void __init at91cap9_ioremap_registers(void) 325static void __init at91cap9_ioremap_registers(void)
332{ 326{
333 at91_ioremap_shdwc(AT91CAP9_BASE_SHDWC); 327 at91_ioremap_shdwc(AT91CAP9_BASE_SHDWC);
328 at91_ioremap_rstc(AT91CAP9_BASE_RSTC);
334 at91sam926x_ioremap_pit(AT91CAP9_BASE_PIT); 329 at91sam926x_ioremap_pit(AT91CAP9_BASE_PIT);
335 at91sam9_ioremap_smc(0, AT91CAP9_BASE_SMC); 330 at91sam9_ioremap_smc(0, AT91CAP9_BASE_SMC);
336} 331}
337 332
338static void __init at91cap9_initialize(void) 333static void __init at91cap9_initialize(void)
339{ 334{
340 arm_pm_restart = at91cap9_restart; 335 arm_pm_restart = at91sam9g45_restart;
341 at91_extern_irq = (1 << AT91CAP9_ID_IRQ0) | (1 << AT91CAP9_ID_IRQ1); 336 at91_extern_irq = (1 << AT91CAP9_ID_IRQ0) | (1 << AT91CAP9_ID_IRQ1);
342 337
343 /* Register GPIO subsystem */ 338 /* Register GPIO subsystem */
diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c
index 18bacec2b094..97676bdae998 100644
--- a/arch/arm/mach-at91/at91rm9200_devices.c
+++ b/arch/arm/mach-at91/at91rm9200_devices.c
@@ -83,7 +83,7 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
83 * USB Device (Gadget) 83 * USB Device (Gadget)
84 * -------------------------------------------------------------------- */ 84 * -------------------------------------------------------------------- */
85 85
86#ifdef CONFIG_USB_AT91 86#if defined(CONFIG_USB_AT91) || defined(CONFIG_USB_AT91_MODULE)
87static struct at91_udc_data udc_data; 87static struct at91_udc_data udc_data;
88 88
89static struct resource udc_resources[] = { 89static struct resource udc_resources[] = {
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index 5e46e4a96430..d4036ba43612 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -323,6 +323,7 @@ static void __init at91sam9260_map_io(void)
323static void __init at91sam9260_ioremap_registers(void) 323static void __init at91sam9260_ioremap_registers(void)
324{ 324{
325 at91_ioremap_shdwc(AT91SAM9260_BASE_SHDWC); 325 at91_ioremap_shdwc(AT91SAM9260_BASE_SHDWC);
326 at91_ioremap_rstc(AT91SAM9260_BASE_RSTC);
326 at91sam926x_ioremap_pit(AT91SAM9260_BASE_PIT); 327 at91sam926x_ioremap_pit(AT91SAM9260_BASE_PIT);
327 at91sam9_ioremap_smc(0, AT91SAM9260_BASE_SMC); 328 at91sam9_ioremap_smc(0, AT91SAM9260_BASE_SMC);
328} 329}
diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c
index 642ccb6d26b2..5a24f0b4554d 100644
--- a/arch/arm/mach-at91/at91sam9260_devices.c
+++ b/arch/arm/mach-at91/at91sam9260_devices.c
@@ -84,7 +84,7 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
84 * USB Device (Gadget) 84 * USB Device (Gadget)
85 * -------------------------------------------------------------------- */ 85 * -------------------------------------------------------------------- */
86 86
87#ifdef CONFIG_USB_AT91 87#if defined(CONFIG_USB_AT91) || defined(CONFIG_USB_AT91_MODULE)
88static struct at91_udc_data udc_data; 88static struct at91_udc_data udc_data;
89 89
90static struct resource udc_resources[] = { 90static struct resource udc_resources[] = {
@@ -1215,8 +1215,7 @@ void __init at91_add_device_serial(void) {}
1215 * CF/IDE 1215 * CF/IDE
1216 * -------------------------------------------------------------------- */ 1216 * -------------------------------------------------------------------- */
1217 1217
1218#if defined(CONFIG_BLK_DEV_IDE_AT91) || defined(CONFIG_BLK_DEV_IDE_AT91_MODULE) || \ 1218#if defined(CONFIG_PATA_AT91) || defined(CONFIG_PATA_AT91_MODULE) || \
1219 defined(CONFIG_PATA_AT91) || defined(CONFIG_PATA_AT91_MODULE) || \
1220 defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE) 1219 defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE)
1221 1220
1222static struct at91_cf_data cf0_data; 1221static struct at91_cf_data cf0_data;
@@ -1313,10 +1312,8 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
1313 if (data->flags & AT91_CF_TRUE_IDE) 1312 if (data->flags & AT91_CF_TRUE_IDE)
1314#if defined(CONFIG_PATA_AT91) || defined(CONFIG_PATA_AT91_MODULE) 1313#if defined(CONFIG_PATA_AT91) || defined(CONFIG_PATA_AT91_MODULE)
1315 pdev->name = "pata_at91"; 1314 pdev->name = "pata_at91";
1316#elif defined(CONFIG_BLK_DEV_IDE_AT91) || defined(CONFIG_BLK_DEV_IDE_AT91_MODULE)
1317 pdev->name = "at91_ide";
1318#else 1315#else
1319#warning "board requires AT91_CF_TRUE_IDE: enable either at91_ide or pata_at91" 1316#warning "board requires AT91_CF_TRUE_IDE: enable pata_at91"
1320#endif 1317#endif
1321 else 1318 else
1322 pdev->name = "at91_cf"; 1319 pdev->name = "at91_cf";
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index b85b9ea60170..023c2ff138df 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -281,6 +281,7 @@ static void __init at91sam9261_map_io(void)
281static void __init at91sam9261_ioremap_registers(void) 281static void __init at91sam9261_ioremap_registers(void)
282{ 282{
283 at91_ioremap_shdwc(AT91SAM9261_BASE_SHDWC); 283 at91_ioremap_shdwc(AT91SAM9261_BASE_SHDWC);
284 at91_ioremap_rstc(AT91SAM9261_BASE_RSTC);
284 at91sam926x_ioremap_pit(AT91SAM9261_BASE_PIT); 285 at91sam926x_ioremap_pit(AT91SAM9261_BASE_PIT);
285 at91sam9_ioremap_smc(0, AT91SAM9261_BASE_SMC); 286 at91sam9_ioremap_smc(0, AT91SAM9261_BASE_SMC);
286} 287}
diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c
index fc59cbdb0e3c..1e28bed8f425 100644
--- a/arch/arm/mach-at91/at91sam9261_devices.c
+++ b/arch/arm/mach-at91/at91sam9261_devices.c
@@ -87,7 +87,7 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
87 * USB Device (Gadget) 87 * USB Device (Gadget)
88 * -------------------------------------------------------------------- */ 88 * -------------------------------------------------------------------- */
89 89
90#ifdef CONFIG_USB_AT91 90#if defined(CONFIG_USB_AT91) || defined(CONFIG_USB_AT91_MODULE)
91static struct at91_udc_data udc_data; 91static struct at91_udc_data udc_data;
92 92
93static struct resource udc_resources[] = { 93static struct resource udc_resources[] = {
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index 79e3669b1117..75e876c258af 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -301,6 +301,7 @@ static void __init at91sam9263_map_io(void)
301static void __init at91sam9263_ioremap_registers(void) 301static void __init at91sam9263_ioremap_registers(void)
302{ 302{
303 at91_ioremap_shdwc(AT91SAM9263_BASE_SHDWC); 303 at91_ioremap_shdwc(AT91SAM9263_BASE_SHDWC);
304 at91_ioremap_rstc(AT91SAM9263_BASE_RSTC);
304 at91sam926x_ioremap_pit(AT91SAM9263_BASE_PIT); 305 at91sam926x_ioremap_pit(AT91SAM9263_BASE_PIT);
305 at91sam9_ioremap_smc(0, AT91SAM9263_BASE_SMC0); 306 at91sam9_ioremap_smc(0, AT91SAM9263_BASE_SMC0);
306 at91sam9_ioremap_smc(1, AT91SAM9263_BASE_SMC1); 307 at91sam9_ioremap_smc(1, AT91SAM9263_BASE_SMC1);
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
index 7b46b2787022..366a7765635b 100644
--- a/arch/arm/mach-at91/at91sam9263_devices.c
+++ b/arch/arm/mach-at91/at91sam9263_devices.c
@@ -92,7 +92,7 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
92 * USB Device (Gadget) 92 * USB Device (Gadget)
93 * -------------------------------------------------------------------- */ 93 * -------------------------------------------------------------------- */
94 94
95#ifdef CONFIG_USB_AT91 95#if defined(CONFIG_USB_AT91) || defined(CONFIG_USB_AT91_MODULE)
96static struct at91_udc_data udc_data; 96static struct at91_udc_data udc_data;
97 97
98static struct resource udc_resources[] = { 98static struct resource udc_resources[] = {
@@ -355,8 +355,8 @@ void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
355 * Compact Flash (PCMCIA or IDE) 355 * Compact Flash (PCMCIA or IDE)
356 * -------------------------------------------------------------------- */ 356 * -------------------------------------------------------------------- */
357 357
358#if defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE) || \ 358#if defined(CONFIG_PATA_AT91) || defined(CONFIG_PATA_AT91_MODULE) || \
359 defined(CONFIG_BLK_DEV_IDE_AT91) || defined(CONFIG_BLK_DEV_IDE_AT91_MODULE) 359 defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE)
360 360
361static struct at91_cf_data cf0_data; 361static struct at91_cf_data cf0_data;
362 362
@@ -450,7 +450,7 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
450 at91_set_A_periph(AT91_PIN_PD9, 0); /* CFCE2 */ 450 at91_set_A_periph(AT91_PIN_PD9, 0); /* CFCE2 */
451 at91_set_A_periph(AT91_PIN_PD14, 0); /* CFNRW */ 451 at91_set_A_periph(AT91_PIN_PD14, 0); /* CFNRW */
452 452
453 pdev->name = (data->flags & AT91_CF_TRUE_IDE) ? "at91_ide" : "at91_cf"; 453 pdev->name = (data->flags & AT91_CF_TRUE_IDE) ? "pata_at91" : "at91_cf";
454 platform_device_register(pdev); 454 platform_device_register(pdev);
455} 455}
456#else 456#else
diff --git a/arch/arm/mach-at91/at91sam9_alt_reset.S b/arch/arm/mach-at91/at91sam9_alt_reset.S
index d3f931c5942e..518e42377171 100644
--- a/arch/arm/mach-at91/at91sam9_alt_reset.S
+++ b/arch/arm/mach-at91/at91sam9_alt_reset.S
@@ -23,7 +23,8 @@
23 .globl at91sam9_alt_restart 23 .globl at91sam9_alt_restart
24 24
25at91sam9_alt_restart: ldr r0, .at91_va_base_sdramc @ preload constants 25at91sam9_alt_restart: ldr r0, .at91_va_base_sdramc @ preload constants
26 ldr r1, .at91_va_base_rstc_cr 26 ldr r1, =at91_rstc_base
27 ldr r1, [r1]
27 28
28 mov r2, #1 29 mov r2, #1
29 mov r3, #AT91_SDRAMC_LPCB_POWER_DOWN 30 mov r3, #AT91_SDRAMC_LPCB_POWER_DOWN
@@ -33,11 +34,9 @@ at91sam9_alt_restart: ldr r0, .at91_va_base_sdramc @ preload constants
33 34
34 str r2, [r0, #AT91_SDRAMC_TR] @ disable SDRAM access 35 str r2, [r0, #AT91_SDRAMC_TR] @ disable SDRAM access
35 str r3, [r0, #AT91_SDRAMC_LPR] @ power down SDRAM 36 str r3, [r0, #AT91_SDRAMC_LPR] @ power down SDRAM
36 str r4, [r1] @ reset processor 37 str r4, [r1, #AT91_RSTC_CR] @ reset processor
37 38
38 b . 39 b .
39 40
40.at91_va_base_sdramc: 41.at91_va_base_sdramc:
41 .word AT91_VA_BASE_SYS + AT91_SDRAMC0 42 .word AT91_VA_BASE_SYS + AT91_SDRAMC0
42.at91_va_base_rstc_cr:
43 .word AT91_VA_BASE_SYS + AT91_RSTC_CR
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index 7032dd32cdf0..1cb6a96b1c1e 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -18,7 +18,6 @@
18#include <asm/mach/map.h> 18#include <asm/mach/map.h>
19#include <mach/at91sam9g45.h> 19#include <mach/at91sam9g45.h>
20#include <mach/at91_pmc.h> 20#include <mach/at91_pmc.h>
21#include <mach/at91_rstc.h>
22#include <mach/cpu.h> 21#include <mach/cpu.h>
23 22
24#include "soc.h" 23#include "soc.h"
@@ -318,11 +317,6 @@ static struct at91_gpio_bank at91sam9g45_gpio[] __initdata = {
318 } 317 }
319}; 318};
320 319
321static void at91sam9g45_restart(char mode, const char *cmd)
322{
323 at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
324}
325
326/* -------------------------------------------------------------------- 320/* --------------------------------------------------------------------
327 * AT91SAM9G45 processor initialization 321 * AT91SAM9G45 processor initialization
328 * -------------------------------------------------------------------- */ 322 * -------------------------------------------------------------------- */
@@ -336,6 +330,7 @@ static void __init at91sam9g45_map_io(void)
336static void __init at91sam9g45_ioremap_registers(void) 330static void __init at91sam9g45_ioremap_registers(void)
337{ 331{
338 at91_ioremap_shdwc(AT91SAM9G45_BASE_SHDWC); 332 at91_ioremap_shdwc(AT91SAM9G45_BASE_SHDWC);
333 at91_ioremap_rstc(AT91SAM9G45_BASE_RSTC);
339 at91sam926x_ioremap_pit(AT91SAM9G45_BASE_PIT); 334 at91sam926x_ioremap_pit(AT91SAM9G45_BASE_PIT);
340 at91sam9_ioremap_smc(0, AT91SAM9G45_BASE_SMC); 335 at91sam9_ioremap_smc(0, AT91SAM9G45_BASE_SMC);
341} 336}
diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c
index b7582dd10dc3..96e2adcd5a84 100644
--- a/arch/arm/mach-at91/at91sam9g45_devices.c
+++ b/arch/arm/mach-at91/at91sam9g45_devices.c
@@ -38,10 +38,6 @@
38#if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE) 38#if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
39static u64 hdmac_dmamask = DMA_BIT_MASK(32); 39static u64 hdmac_dmamask = DMA_BIT_MASK(32);
40 40
41static struct at_dma_platform_data atdma_pdata = {
42 .nr_channels = 8,
43};
44
45static struct resource hdmac_resources[] = { 41static struct resource hdmac_resources[] = {
46 [0] = { 42 [0] = {
47 .start = AT91SAM9G45_BASE_DMA, 43 .start = AT91SAM9G45_BASE_DMA,
@@ -56,12 +52,11 @@ static struct resource hdmac_resources[] = {
56}; 52};
57 53
58static struct platform_device at_hdmac_device = { 54static struct platform_device at_hdmac_device = {
59 .name = "at_hdmac", 55 .name = "at91sam9g45_dma",
60 .id = -1, 56 .id = -1,
61 .dev = { 57 .dev = {
62 .dma_mask = &hdmac_dmamask, 58 .dma_mask = &hdmac_dmamask,
63 .coherent_dma_mask = DMA_BIT_MASK(32), 59 .coherent_dma_mask = DMA_BIT_MASK(32),
64 .platform_data = &atdma_pdata,
65 }, 60 },
66 .resource = hdmac_resources, 61 .resource = hdmac_resources,
67 .num_resources = ARRAY_SIZE(hdmac_resources), 62 .num_resources = ARRAY_SIZE(hdmac_resources),
@@ -69,9 +64,15 @@ static struct platform_device at_hdmac_device = {
69 64
70void __init at91_add_device_hdmac(void) 65void __init at91_add_device_hdmac(void)
71{ 66{
72 dma_cap_set(DMA_MEMCPY, atdma_pdata.cap_mask); 67#if defined(CONFIG_OF)
73 dma_cap_set(DMA_SLAVE, atdma_pdata.cap_mask); 68 struct device_node *of_node =
74 platform_device_register(&at_hdmac_device); 69 of_find_node_by_name(NULL, "dma-controller");
70
71 if (of_node)
72 of_node_put(of_node);
73 else
74#endif
75 platform_device_register(&at_hdmac_device);
75} 76}
76#else 77#else
77void __init at91_add_device_hdmac(void) {} 78void __init at91_add_device_hdmac(void) {}
diff --git a/arch/arm/mach-at91/at91sam9g45_reset.S b/arch/arm/mach-at91/at91sam9g45_reset.S
new file mode 100644
index 000000000000..0468be10980b
--- /dev/null
+++ b/arch/arm/mach-at91/at91sam9g45_reset.S
@@ -0,0 +1,40 @@
1/*
2 * reset AT91SAM9G45 as per errata
3 *
4 * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcosoft.com>
5 *
6 * unless the SDRAM is cleanly shutdown before we hit the
7 * reset register it can be left driving the data bus and
8 * killing the chance of a subsequent boot from NAND
9 *
10 * GPLv2 Only
11 */
12
13#include <linux/linkage.h>
14#include <mach/hardware.h>
15#include <mach/at91sam9_ddrsdr.h>
16#include <mach/at91_rstc.h>
17
18 .arm
19
20 .globl at91sam9g45_restart
21
22at91sam9g45_restart:
23 ldr r0, .at91_va_base_sdramc0 @ preload constants
24 ldr r1, =at91_rstc_base
25 ldr r1, [r1]
26
27 mov r2, #1
28 mov r3, #AT91_DDRSDRC_LPCB_POWER_DOWN
29 ldr r4, =AT91_RSTC_KEY | AT91_RSTC_PERRST | AT91_RSTC_PROCRST
30
31 .balign 32 @ align to cache line
32
33 str r2, [r0, #AT91_DDRSDRC_RTR] @ disable DDR0 access
34 str r3, [r0, #AT91_DDRSDRC_LPR] @ power down DDR0
35 str r4, [r1, #AT91_RSTC_CR] @ reset processor
36
37 b .
38
39.at91_va_base_sdramc0:
40 .word AT91_VA_BASE_SYS + AT91_DDRSDRC0
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
index d6bcb1da11df..d2c91a841cb8 100644
--- a/arch/arm/mach-at91/at91sam9rl.c
+++ b/arch/arm/mach-at91/at91sam9rl.c
@@ -286,6 +286,7 @@ static void __init at91sam9rl_map_io(void)
286static void __init at91sam9rl_ioremap_registers(void) 286static void __init at91sam9rl_ioremap_registers(void)
287{ 287{
288 at91_ioremap_shdwc(AT91SAM9RL_BASE_SHDWC); 288 at91_ioremap_shdwc(AT91SAM9RL_BASE_SHDWC);
289 at91_ioremap_rstc(AT91SAM9RL_BASE_RSTC);
289 at91sam926x_ioremap_pit(AT91SAM9RL_BASE_PIT); 290 at91sam926x_ioremap_pit(AT91SAM9RL_BASE_PIT);
290 at91sam9_ioremap_smc(0, AT91SAM9RL_BASE_SMC); 291 at91sam9_ioremap_smc(0, AT91SAM9RL_BASE_SMC);
291} 292}
diff --git a/arch/arm/mach-at91/at91sam9rl_devices.c b/arch/arm/mach-at91/at91sam9rl_devices.c
index 61908dce9784..9be71c11d0f0 100644
--- a/arch/arm/mach-at91/at91sam9rl_devices.c
+++ b/arch/arm/mach-at91/at91sam9rl_devices.c
@@ -33,10 +33,6 @@
33#if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE) 33#if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
34static u64 hdmac_dmamask = DMA_BIT_MASK(32); 34static u64 hdmac_dmamask = DMA_BIT_MASK(32);
35 35
36static struct at_dma_platform_data atdma_pdata = {
37 .nr_channels = 2,
38};
39
40static struct resource hdmac_resources[] = { 36static struct resource hdmac_resources[] = {
41 [0] = { 37 [0] = {
42 .start = AT91SAM9RL_BASE_DMA, 38 .start = AT91SAM9RL_BASE_DMA,
@@ -51,12 +47,11 @@ static struct resource hdmac_resources[] = {
51}; 47};
52 48
53static struct platform_device at_hdmac_device = { 49static struct platform_device at_hdmac_device = {
54 .name = "at_hdmac", 50 .name = "at91sam9rl_dma",
55 .id = -1, 51 .id = -1,
56 .dev = { 52 .dev = {
57 .dma_mask = &hdmac_dmamask, 53 .dma_mask = &hdmac_dmamask,
58 .coherent_dma_mask = DMA_BIT_MASK(32), 54 .coherent_dma_mask = DMA_BIT_MASK(32),
59 .platform_data = &atdma_pdata,
60 }, 55 },
61 .resource = hdmac_resources, 56 .resource = hdmac_resources,
62 .num_resources = ARRAY_SIZE(hdmac_resources), 57 .num_resources = ARRAY_SIZE(hdmac_resources),
@@ -64,7 +59,6 @@ static struct platform_device at_hdmac_device = {
64 59
65void __init at91_add_device_hdmac(void) 60void __init at91_add_device_hdmac(void)
66{ 61{
67 dma_cap_set(DMA_MEMCPY, atdma_pdata.cap_mask);
68 platform_device_register(&at_hdmac_device); 62 platform_device_register(&at_hdmac_device);
69} 63}
70#else 64#else
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index 4866b8180d66..594133451c0c 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -58,7 +58,9 @@ extern void at91_irq_suspend(void);
58extern void at91_irq_resume(void); 58extern void at91_irq_resume(void);
59 59
60/* reset */ 60/* reset */
61extern void at91_ioremap_rstc(u32 base_addr);
61extern void at91sam9_alt_restart(char, const char *); 62extern void at91sam9_alt_restart(char, const char *);
63extern void at91sam9g45_restart(char, const char *);
62 64
63/* shutdown */ 65/* shutdown */
64extern void at91_ioremap_shdwc(u32 base_addr); 66extern void at91_ioremap_shdwc(u32 base_addr);
diff --git a/arch/arm/mach-at91/include/mach/at91_rstc.h b/arch/arm/mach-at91/include/mach/at91_rstc.h
index cbd2bf052c1f..875fa336800b 100644
--- a/arch/arm/mach-at91/include/mach/at91_rstc.h
+++ b/arch/arm/mach-at91/include/mach/at91_rstc.h
@@ -16,13 +16,25 @@
16#ifndef AT91_RSTC_H 16#ifndef AT91_RSTC_H
17#define AT91_RSTC_H 17#define AT91_RSTC_H
18 18
19#define AT91_RSTC_CR (AT91_RSTC + 0x00) /* Reset Controller Control Register */ 19#ifndef __ASSEMBLY__
20extern void __iomem *at91_rstc_base;
21
22#define at91_rstc_read(field) \
23 __raw_readl(at91_rstc_base + field)
24
25#define at91_rstc_write(field, value) \
26 __raw_writel(value, at91_rstc_base + field);
27#else
28.extern at91_rstc_base
29#endif
30
31#define AT91_RSTC_CR 0x00 /* Reset Controller Control Register */
20#define AT91_RSTC_PROCRST (1 << 0) /* Processor Reset */ 32#define AT91_RSTC_PROCRST (1 << 0) /* Processor Reset */
21#define AT91_RSTC_PERRST (1 << 2) /* Peripheral Reset */ 33#define AT91_RSTC_PERRST (1 << 2) /* Peripheral Reset */
22#define AT91_RSTC_EXTRST (1 << 3) /* External Reset */ 34#define AT91_RSTC_EXTRST (1 << 3) /* External Reset */
23#define AT91_RSTC_KEY (0xa5 << 24) /* KEY Password */ 35#define AT91_RSTC_KEY (0xa5 << 24) /* KEY Password */
24 36
25#define AT91_RSTC_SR (AT91_RSTC + 0x04) /* Reset Controller Status Register */ 37#define AT91_RSTC_SR 0x04 /* Reset Controller Status Register */
26#define AT91_RSTC_URSTS (1 << 0) /* User Reset Status */ 38#define AT91_RSTC_URSTS (1 << 0) /* User Reset Status */
27#define AT91_RSTC_RSTTYP (7 << 8) /* Reset Type */ 39#define AT91_RSTC_RSTTYP (7 << 8) /* Reset Type */
28#define AT91_RSTC_RSTTYP_GENERAL (0 << 8) 40#define AT91_RSTC_RSTTYP_GENERAL (0 << 8)
@@ -33,7 +45,7 @@
33#define AT91_RSTC_NRSTL (1 << 16) /* NRST Pin Level */ 45#define AT91_RSTC_NRSTL (1 << 16) /* NRST Pin Level */
34#define AT91_RSTC_SRCMP (1 << 17) /* Software Reset Command in Progress */ 46#define AT91_RSTC_SRCMP (1 << 17) /* Software Reset Command in Progress */
35 47
36#define AT91_RSTC_MR (AT91_RSTC + 0x08) /* Reset Controller Mode Register */ 48#define AT91_RSTC_MR 0x08 /* Reset Controller Mode Register */
37#define AT91_RSTC_URSTEN (1 << 0) /* User Reset Enable */ 49#define AT91_RSTC_URSTEN (1 << 0) /* User Reset Enable */
38#define AT91_RSTC_URSTIEN (1 << 4) /* User Reset Interrupt Enable */ 50#define AT91_RSTC_URSTIEN (1 << 4) /* User Reset Interrupt Enable */
39#define AT91_RSTC_ERSTL (0xf << 8) /* External Reset Length */ 51#define AT91_RSTC_ERSTL (0xf << 8) /* External Reset Length */
diff --git a/arch/arm/mach-at91/include/mach/at91cap9.h b/arch/arm/mach-at91/include/mach/at91cap9.h
index 4c0e2f6011d7..61d952902f2b 100644
--- a/arch/arm/mach-at91/include/mach/at91cap9.h
+++ b/arch/arm/mach-at91/include/mach/at91cap9.h
@@ -83,7 +83,6 @@
83#define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS) 83#define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS)
84#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS) 84#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS)
85#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) 85#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
86#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
87#define AT91_GPBR (cpu_is_at91cap9_revB() ? \ 86#define AT91_GPBR (cpu_is_at91cap9_revB() ? \
88 (0xfffffd50 - AT91_BASE_SYS) : \ 87 (0xfffffd50 - AT91_BASE_SYS) : \
89 (0xfffffd60 - AT91_BASE_SYS)) 88 (0xfffffd60 - AT91_BASE_SYS))
@@ -96,6 +95,7 @@
96#define AT91CAP9_BASE_PIOB 0xfffff400 95#define AT91CAP9_BASE_PIOB 0xfffff400
97#define AT91CAP9_BASE_PIOC 0xfffff600 96#define AT91CAP9_BASE_PIOC 0xfffff600
98#define AT91CAP9_BASE_PIOD 0xfffff800 97#define AT91CAP9_BASE_PIOD 0xfffff800
98#define AT91CAP9_BASE_RSTC 0xfffffd00
99#define AT91CAP9_BASE_SHDWC 0xfffffd10 99#define AT91CAP9_BASE_SHDWC 0xfffffd10
100#define AT91CAP9_BASE_RTT 0xfffffd20 100#define AT91CAP9_BASE_RTT 0xfffffd20
101#define AT91CAP9_BASE_PIT 0xfffffd30 101#define AT91CAP9_BASE_PIT 0xfffffd30
diff --git a/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h b/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h
deleted file mode 100644
index 976f4a6c3353..000000000000
--- a/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h
+++ /dev/null
@@ -1,108 +0,0 @@
1/*
2 * arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h
3 *
4 * (C) 2008 Andrew Victor
5 *
6 * DDR/SDR Controller (DDRSDRC) - System peripherals registers.
7 * Based on AT91CAP9 datasheet revision B.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15#ifndef AT91CAP9_DDRSDR_H
16#define AT91CAP9_DDRSDR_H
17
18#define AT91_DDRSDRC_MR 0x00 /* Mode Register */
19#define AT91_DDRSDRC_MODE (0xf << 0) /* Command Mode */
20#define AT91_DDRSDRC_MODE_NORMAL 0
21#define AT91_DDRSDRC_MODE_NOP 1
22#define AT91_DDRSDRC_MODE_PRECHARGE 2
23#define AT91_DDRSDRC_MODE_LMR 3
24#define AT91_DDRSDRC_MODE_REFRESH 4
25#define AT91_DDRSDRC_MODE_EXT_LMR 5
26#define AT91_DDRSDRC_MODE_DEEP 6
27
28#define AT91_DDRSDRC_RTR 0x04 /* Refresh Timer Register */
29#define AT91_DDRSDRC_COUNT (0xfff << 0) /* Refresh Timer Counter */
30
31#define AT91_DDRSDRC_CR 0x08 /* Configuration Register */
32#define AT91_DDRSDRC_NC (3 << 0) /* Number of Column Bits */
33#define AT91_DDRSDRC_NC_SDR8 (0 << 0)
34#define AT91_DDRSDRC_NC_SDR9 (1 << 0)
35#define AT91_DDRSDRC_NC_SDR10 (2 << 0)
36#define AT91_DDRSDRC_NC_SDR11 (3 << 0)
37#define AT91_DDRSDRC_NC_DDR9 (0 << 0)
38#define AT91_DDRSDRC_NC_DDR10 (1 << 0)
39#define AT91_DDRSDRC_NC_DDR11 (2 << 0)
40#define AT91_DDRSDRC_NC_DDR12 (3 << 0)
41#define AT91_DDRSDRC_NR (3 << 2) /* Number of Row Bits */
42#define AT91_DDRSDRC_NR_11 (0 << 2)
43#define AT91_DDRSDRC_NR_12 (1 << 2)
44#define AT91_DDRSDRC_NR_13 (2 << 2)
45#define AT91_DDRSDRC_CAS (7 << 4) /* CAS Latency */
46#define AT91_DDRSDRC_CAS_2 (2 << 4)
47#define AT91_DDRSDRC_CAS_3 (3 << 4)
48#define AT91_DDRSDRC_CAS_25 (6 << 4)
49#define AT91_DDRSDRC_DLL (1 << 7) /* Reset DLL */
50#define AT91_DDRSDRC_DICDS (1 << 8) /* Output impedance control */
51
52#define AT91_DDRSDRC_T0PR 0x0C /* Timing 0 Register */
53#define AT91_DDRSDRC_TRAS (0xf << 0) /* Active to Precharge delay */
54#define AT91_DDRSDRC_TRCD (0xf << 4) /* Row to Column delay */
55#define AT91_DDRSDRC_TWR (0xf << 8) /* Write recovery delay */
56#define AT91_DDRSDRC_TRC (0xf << 12) /* Row cycle delay */
57#define AT91_DDRSDRC_TRP (0xf << 16) /* Row precharge delay */
58#define AT91_DDRSDRC_TRRD (0xf << 20) /* Active BankA to BankB */
59#define AT91_DDRSDRC_TWTR (1 << 24) /* Internal Write to Read delay */
60#define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */
61
62#define AT91_DDRSDRC_T1PR 0x10 /* Timing 1 Register */
63#define AT91_DDRSDRC_TRFC (0x1f << 0) /* Row Cycle Delay */
64#define AT91_DDRSDRC_TXSNR (0xff << 8) /* Exit self-refresh to non-read */
65#define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */
66#define AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */
67
68#define AT91_DDRSDRC_LPR 0x18 /* Low Power Register */
69#define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */
70#define AT91_DDRSDRC_LPCB_DISABLE 0
71#define AT91_DDRSDRC_LPCB_SELF_REFRESH 1
72#define AT91_DDRSDRC_LPCB_POWER_DOWN 2
73#define AT91_DDRSDRC_LPCB_DEEP_POWER_DOWN 3
74#define AT91_DDRSDRC_CLKFR (1 << 2) /* Clock Frozen */
75#define AT91_DDRSDRC_PASR (7 << 4) /* Partial Array Self Refresh */
76#define AT91_DDRSDRC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */
77#define AT91_DDRSDRC_DS (3 << 10) /* Drive Strength */
78#define AT91_DDRSDRC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */
79#define AT91_DDRSDRC_TIMEOUT_0_CLK_CYCLES (0 << 12)
80#define AT91_DDRSDRC_TIMEOUT_64_CLK_CYCLES (1 << 12)
81#define AT91_DDRSDRC_TIMEOUT_128_CLK_CYCLES (2 << 12)
82
83#define AT91_DDRSDRC_MDR 0x1C /* Memory Device Register */
84#define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */
85#define AT91_DDRSDRC_MD_SDR 0
86#define AT91_DDRSDRC_MD_LOW_POWER_SDR 1
87#define AT91_DDRSDRC_MD_DDR 2
88#define AT91_DDRSDRC_MD_LOW_POWER_DDR 3
89
90#define AT91_DDRSDRC_DLLR 0x20 /* DLL Information Register */
91#define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */
92#define AT91_DDRSDRC_MDDEC (1 << 1) /* Master Delay decrement */
93#define AT91_DDRSDRC_MDOVF (1 << 2) /* Master Delay Overflow */
94#define AT91_DDRSDRC_SDCOVF (1 << 3) /* Slave Delay Correction Overflow */
95#define AT91_DDRSDRC_SDCUDF (1 << 4) /* Slave Delay Correction Underflow */
96#define AT91_DDRSDRC_SDERF (1 << 5) /* Slave Delay Correction error */
97#define AT91_DDRSDRC_MDVAL (0xff << 8) /* Master Delay value */
98#define AT91_DDRSDRC_SDVAL (0xff << 16) /* Slave Delay value */
99#define AT91_DDRSDRC_SDCVAL (0xff << 24) /* Slave Delay Correction value */
100
101/* Register access macros */
102#define at91_ramc_read(num, reg) \
103 at91_sys_read(AT91_DDRSDRC##num + reg)
104#define at91_ramc_write(num, reg, value) \
105 at91_sys_write(AT91_DDRSDRC##num + reg, value)
106
107
108#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9260.h b/arch/arm/mach-at91/include/mach/at91sam9260.h
index f937c476bb67..fa5ca278adeb 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9260.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9260.h
@@ -83,7 +83,6 @@
83#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS) 83#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS)
84#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) 84#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
85#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) 85#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
86#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
87#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) 86#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
88 87
89#define AT91SAM9260_BASE_ECC 0xffffe800 88#define AT91SAM9260_BASE_ECC 0xffffe800
@@ -92,6 +91,7 @@
92#define AT91SAM9260_BASE_PIOA 0xfffff400 91#define AT91SAM9260_BASE_PIOA 0xfffff400
93#define AT91SAM9260_BASE_PIOB 0xfffff600 92#define AT91SAM9260_BASE_PIOB 0xfffff600
94#define AT91SAM9260_BASE_PIOC 0xfffff800 93#define AT91SAM9260_BASE_PIOC 0xfffff800
94#define AT91SAM9260_BASE_RSTC 0xfffffd00
95#define AT91SAM9260_BASE_SHDWC 0xfffffd10 95#define AT91SAM9260_BASE_SHDWC 0xfffffd10
96#define AT91SAM9260_BASE_RTT 0xfffffd20 96#define AT91SAM9260_BASE_RTT 0xfffffd20
97#define AT91SAM9260_BASE_PIT 0xfffffd30 97#define AT91SAM9260_BASE_PIT 0xfffffd30
diff --git a/arch/arm/mach-at91/include/mach/at91sam9261.h b/arch/arm/mach-at91/include/mach/at91sam9261.h
index 175604e261be..7cde2d36570e 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9261.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9261.h
@@ -68,7 +68,6 @@
68#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS) 68#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS)
69#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) 69#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
70#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) 70#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
71#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
72#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) 71#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
73 72
74#define AT91SAM9261_BASE_SMC 0xffffec00 73#define AT91SAM9261_BASE_SMC 0xffffec00
@@ -76,6 +75,7 @@
76#define AT91SAM9261_BASE_PIOA 0xfffff400 75#define AT91SAM9261_BASE_PIOA 0xfffff400
77#define AT91SAM9261_BASE_PIOB 0xfffff600 76#define AT91SAM9261_BASE_PIOB 0xfffff600
78#define AT91SAM9261_BASE_PIOC 0xfffff800 77#define AT91SAM9261_BASE_PIOC 0xfffff800
78#define AT91SAM9261_BASE_RSTC 0xfffffd00
79#define AT91SAM9261_BASE_SHDWC 0xfffffd10 79#define AT91SAM9261_BASE_SHDWC 0xfffffd10
80#define AT91SAM9261_BASE_RTT 0xfffffd20 80#define AT91SAM9261_BASE_RTT 0xfffffd20
81#define AT91SAM9261_BASE_PIT 0xfffffd30 81#define AT91SAM9261_BASE_PIT 0xfffffd30
diff --git a/arch/arm/mach-at91/include/mach/at91sam9263.h b/arch/arm/mach-at91/include/mach/at91sam9263.h
index 80c915002d83..5949abda962b 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9263.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9263.h
@@ -78,7 +78,6 @@
78#define AT91_SDRAMC1 (0xffffe800 - AT91_BASE_SYS) 78#define AT91_SDRAMC1 (0xffffe800 - AT91_BASE_SYS)
79#define AT91_MATRIX (0xffffec00 - AT91_BASE_SYS) 79#define AT91_MATRIX (0xffffec00 - AT91_BASE_SYS)
80#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) 80#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
81#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
82#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) 81#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
83 82
84#define AT91SAM9263_BASE_ECC0 0xffffe000 83#define AT91SAM9263_BASE_ECC0 0xffffe000
@@ -91,6 +90,7 @@
91#define AT91SAM9263_BASE_PIOC 0xfffff600 90#define AT91SAM9263_BASE_PIOC 0xfffff600
92#define AT91SAM9263_BASE_PIOD 0xfffff800 91#define AT91SAM9263_BASE_PIOD 0xfffff800
93#define AT91SAM9263_BASE_PIOE 0xfffffa00 92#define AT91SAM9263_BASE_PIOE 0xfffffa00
93#define AT91SAM9263_BASE_RSTC 0xfffffd00
94#define AT91SAM9263_BASE_SHDWC 0xfffffd10 94#define AT91SAM9263_BASE_SHDWC 0xfffffd10
95#define AT91SAM9263_BASE_RTT0 0xfffffd20 95#define AT91SAM9263_BASE_RTT0 0xfffffd20
96#define AT91SAM9263_BASE_PIT 0xfffffd30 96#define AT91SAM9263_BASE_PIT 0xfffffd30
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
index d27b15ba8ebf..e2f8da8ce5bc 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
@@ -46,10 +46,10 @@
46#define AT91_DDRSDRC_CAS_25 (6 << 4) 46#define AT91_DDRSDRC_CAS_25 (6 << 4)
47#define AT91_DDRSDRC_RST_DLL (1 << 7) /* Reset DLL */ 47#define AT91_DDRSDRC_RST_DLL (1 << 7) /* Reset DLL */
48#define AT91_DDRSDRC_DICDS (1 << 8) /* Output impedance control */ 48#define AT91_DDRSDRC_DICDS (1 << 8) /* Output impedance control */
49#define AT91_DDRSDRC_DIS_DLL (1 << 9) /* Disable DLL */ 49#define AT91_DDRSDRC_DIS_DLL (1 << 9) /* Disable DLL [SAM9 Only] */
50#define AT91_DDRSDRC_OCD (1 << 12) /* Off-Chip Driver */ 50#define AT91_DDRSDRC_OCD (1 << 12) /* Off-Chip Driver [SAM9 Only] */
51#define AT91_DDRSDRC_DQMS (1 << 16) /* Mask Data is Shared */ 51#define AT91_DDRSDRC_DQMS (1 << 16) /* Mask Data is Shared [SAM9 Only] */
52#define AT91_DDRSDRC_ACTBST (1 << 18) /* Active Bank X to Burst Stop Read Access Bank Y */ 52#define AT91_DDRSDRC_ACTBST (1 << 18) /* Active Bank X to Burst Stop Read Access Bank Y [SAM9 Only] */
53 53
54#define AT91_DDRSDRC_T0PR 0x0C /* Timing 0 Register */ 54#define AT91_DDRSDRC_T0PR 0x0C /* Timing 0 Register */
55#define AT91_DDRSDRC_TRAS (0xf << 0) /* Active to Precharge delay */ 55#define AT91_DDRSDRC_TRAS (0xf << 0) /* Active to Precharge delay */
@@ -59,7 +59,8 @@
59#define AT91_DDRSDRC_TRP (0xf << 16) /* Row precharge delay */ 59#define AT91_DDRSDRC_TRP (0xf << 16) /* Row precharge delay */
60#define AT91_DDRSDRC_TRRD (0xf << 20) /* Active BankA to BankB */ 60#define AT91_DDRSDRC_TRRD (0xf << 20) /* Active BankA to BankB */
61#define AT91_DDRSDRC_TWTR (0x7 << 24) /* Internal Write to Read delay */ 61#define AT91_DDRSDRC_TWTR (0x7 << 24) /* Internal Write to Read delay */
62#define AT91_DDRSDRC_RED_WRRD (0x1 << 27) /* Reduce Write to Read Delay */ 62#define AT91CAP9_DDRSDRC_TWTR (1 << 24) /* Internal Write to Read delay */
63#define AT91_DDRSDRC_RED_WRRD (0x1 << 27) /* Reduce Write to Read Delay [SAM9 Only] */
63#define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */ 64#define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */
64 65
65#define AT91_DDRSDRC_T1PR 0x10 /* Timing 1 Register */ 66#define AT91_DDRSDRC_T1PR 0x10 /* Timing 1 Register */
@@ -68,13 +69,14 @@
68#define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */ 69#define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */
69#define AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */ 70#define AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */
70 71
71#define AT91_DDRSDRC_T2PR 0x14 /* Timing 2 Register */ 72#define AT91_DDRSDRC_T2PR 0x14 /* Timing 2 Register [SAM9 Only] */
72#define AT91_DDRSDRC_TXARD (0xf << 0) /* Exit active power down delay to read command in mode "Fast Exit" */ 73#define AT91_DDRSDRC_TXARD (0xf << 0) /* Exit active power down delay to read command in mode "Fast Exit" */
73#define AT91_DDRSDRC_TXARDS (0xf << 4) /* Exit active power down delay to read command in mode "Slow Exit" */ 74#define AT91_DDRSDRC_TXARDS (0xf << 4) /* Exit active power down delay to read command in mode "Slow Exit" */
74#define AT91_DDRSDRC_TRPA (0xf << 8) /* Row Precharge All delay */ 75#define AT91_DDRSDRC_TRPA (0xf << 8) /* Row Precharge All delay */
75#define AT91_DDRSDRC_TRTP (0x7 << 12) /* Read to Precharge delay */ 76#define AT91_DDRSDRC_TRTP (0x7 << 12) /* Read to Precharge delay */
76 77
77#define AT91_DDRSDRC_LPR 0x1C /* Low Power Register */ 78#define AT91_DDRSDRC_LPR 0x1C /* Low Power Register */
79#define AT91CAP9_DDRSDRC_LPR 0x18 /* Low Power Register */
78#define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */ 80#define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */
79#define AT91_DDRSDRC_LPCB_DISABLE 0 81#define AT91_DDRSDRC_LPCB_DISABLE 0
80#define AT91_DDRSDRC_LPCB_SELF_REFRESH 1 82#define AT91_DDRSDRC_LPCB_SELF_REFRESH 1
@@ -92,32 +94,40 @@
92#define AT91_DDRSDRC_UPD_MR (3 << 20) /* Update load mode register and extended mode register */ 94#define AT91_DDRSDRC_UPD_MR (3 << 20) /* Update load mode register and extended mode register */
93 95
94#define AT91_DDRSDRC_MDR 0x20 /* Memory Device Register */ 96#define AT91_DDRSDRC_MDR 0x20 /* Memory Device Register */
97#define AT91CAP9_DDRSDRC_MDR 0x1C /* Memory Device Register */
95#define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */ 98#define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */
96#define AT91_DDRSDRC_MD_SDR 0 99#define AT91_DDRSDRC_MD_SDR 0
97#define AT91_DDRSDRC_MD_LOW_POWER_SDR 1 100#define AT91_DDRSDRC_MD_LOW_POWER_SDR 1
101#define AT91CAP9_DDRSDRC_MD_DDR 2
98#define AT91_DDRSDRC_MD_LOW_POWER_DDR 3 102#define AT91_DDRSDRC_MD_LOW_POWER_DDR 3
99#define AT91_DDRSDRC_MD_DDR2 6 103#define AT91_DDRSDRC_MD_DDR2 6 /* [SAM9 Only] */
100#define AT91_DDRSDRC_DBW (1 << 4) /* Data Bus Width */ 104#define AT91_DDRSDRC_DBW (1 << 4) /* Data Bus Width */
101#define AT91_DDRSDRC_DBW_32BITS (0 << 4) 105#define AT91_DDRSDRC_DBW_32BITS (0 << 4)
102#define AT91_DDRSDRC_DBW_16BITS (1 << 4) 106#define AT91_DDRSDRC_DBW_16BITS (1 << 4)
103 107
104#define AT91_DDRSDRC_DLL 0x24 /* DLL Information Register */ 108#define AT91_DDRSDRC_DLL 0x24 /* DLL Information Register */
109#define AT91CAP9_DDRSDRC_DLL 0x20 /* DLL Information Register */
105#define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */ 110#define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */
106#define AT91_DDRSDRC_MDDEC (1 << 1) /* Master Delay decrement */ 111#define AT91_DDRSDRC_MDDEC (1 << 1) /* Master Delay decrement */
107#define AT91_DDRSDRC_MDOVF (1 << 2) /* Master Delay Overflow */ 112#define AT91_DDRSDRC_MDOVF (1 << 2) /* Master Delay Overflow */
113#define AT91CAP9_DDRSDRC_SDCOVF (1 << 3) /* Slave Delay Correction Overflow */
114#define AT91CAP9_DDRSDRC_SDCUDF (1 << 4) /* Slave Delay Correction Underflow */
115#define AT91CAP9_DDRSDRC_SDERF (1 << 5) /* Slave Delay Correction error */
108#define AT91_DDRSDRC_MDVAL (0xff << 8) /* Master Delay value */ 116#define AT91_DDRSDRC_MDVAL (0xff << 8) /* Master Delay value */
117#define AT91CAP9_DDRSDRC_SDVAL (0xff << 16) /* Slave Delay value */
118#define AT91CAP9_DDRSDRC_SDCVAL (0xff << 24) /* Slave Delay Correction value */
109 119
110#define AT91_DDRSDRC_HS 0x2C /* High Speed Register */ 120#define AT91_DDRSDRC_HS 0x2C /* High Speed Register [SAM9 Only] */
111#define AT91_DDRSDRC_DIS_ATCP_RD (1 << 2) /* Anticip read access is disabled */ 121#define AT91_DDRSDRC_DIS_ATCP_RD (1 << 2) /* Anticip read access is disabled */
112 122
113#define AT91_DDRSDRC_DELAY(n) (0x30 + (0x4 * (n))) /* Delay I/O Register n */ 123#define AT91_DDRSDRC_DELAY(n) (0x30 + (0x4 * (n))) /* Delay I/O Register n */
114 124
115#define AT91_DDRSDRC_WPMR 0xE4 /* Write Protect Mode Register */ 125#define AT91_DDRSDRC_WPMR 0xE4 /* Write Protect Mode Register [SAM9 Only] */
116#define AT91_DDRSDRC_WP (1 << 0) /* Write protect enable */ 126#define AT91_DDRSDRC_WP (1 << 0) /* Write protect enable */
117#define AT91_DDRSDRC_WPKEY (0xffffff << 8) /* Write protect key */ 127#define AT91_DDRSDRC_WPKEY (0xffffff << 8) /* Write protect key */
118#define AT91_DDRSDRC_KEY (0x444452 << 8) /* Write protect key = "DDR" */ 128#define AT91_DDRSDRC_KEY (0x444452 << 8) /* Write protect key = "DDR" */
119 129
120#define AT91_DDRSDRC_WPSR 0xE8 /* Write Protect Status Register */ 130#define AT91_DDRSDRC_WPSR 0xE8 /* Write Protect Status Register [SAM9 Only] */
121#define AT91_DDRSDRC_WPVS (1 << 0) /* Write protect violation status */ 131#define AT91_DDRSDRC_WPVS (1 << 0) /* Write protect violation status */
122#define AT91_DDRSDRC_WPVSRC (0xffff << 8) /* Write protect violation source */ 132#define AT91_DDRSDRC_WPVSRC (0xffff << 8) /* Write protect violation source */
123 133
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_smc.h b/arch/arm/mach-at91/include/mach/at91sam9_smc.h
index eb18a70fa647..175e1fdd9fe8 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9_smc.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9_smc.h
@@ -18,6 +18,35 @@
18 18
19#include <mach/cpu.h> 19#include <mach/cpu.h>
20 20
21#ifndef __ASSEMBLY__
22struct sam9_smc_config {
23 /* Setup register */
24 u8 ncs_read_setup;
25 u8 nrd_setup;
26 u8 ncs_write_setup;
27 u8 nwe_setup;
28
29 /* Pulse register */
30 u8 ncs_read_pulse;
31 u8 nrd_pulse;
32 u8 ncs_write_pulse;
33 u8 nwe_pulse;
34
35 /* Cycle register */
36 u16 read_cycle;
37 u16 write_cycle;
38
39 /* Mode register */
40 u32 mode;
41 u8 tdf_cycles:4;
42};
43
44extern void sam9_smc_configure(int id, int cs, struct sam9_smc_config *config);
45extern void sam9_smc_read(int id, int cs, struct sam9_smc_config *config);
46extern void sam9_smc_read_mode(int id, int cs, struct sam9_smc_config *config);
47extern void sam9_smc_write_mode(int id, int cs, struct sam9_smc_config *config);
48#endif
49
21#define AT91_SMC_SETUP 0x00 /* Setup Register for CS n */ 50#define AT91_SMC_SETUP 0x00 /* Setup Register for CS n */
22#define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */ 51#define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */
23#define AT91_SMC_NWESETUP_(x) ((x) << 0) 52#define AT91_SMC_NWESETUP_(x) ((x) << 0)
diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h
index f0c23c960dec..dd9c95ea0862 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9g45.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9g45.h
@@ -90,7 +90,6 @@
90#define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS) 90#define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS)
91#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS) 91#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS)
92#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) 92#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
93#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
94#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) 93#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
95 94
96#define AT91SAM9G45_BASE_ECC 0xffffe200 95#define AT91SAM9G45_BASE_ECC 0xffffe200
@@ -102,6 +101,7 @@
102#define AT91SAM9G45_BASE_PIOC 0xfffff600 101#define AT91SAM9G45_BASE_PIOC 0xfffff600
103#define AT91SAM9G45_BASE_PIOD 0xfffff800 102#define AT91SAM9G45_BASE_PIOD 0xfffff800
104#define AT91SAM9G45_BASE_PIOE 0xfffffa00 103#define AT91SAM9G45_BASE_PIOE 0xfffffa00
104#define AT91SAM9G45_BASE_RSTC 0xfffffd00
105#define AT91SAM9G45_BASE_SHDWC 0xfffffd10 105#define AT91SAM9G45_BASE_SHDWC 0xfffffd10
106#define AT91SAM9G45_BASE_RTT 0xfffffd20 106#define AT91SAM9G45_BASE_RTT 0xfffffd20
107#define AT91SAM9G45_BASE_PIT 0xfffffd30 107#define AT91SAM9G45_BASE_PIT 0xfffffd30
diff --git a/arch/arm/mach-at91/include/mach/at91sam9rl.h b/arch/arm/mach-at91/include/mach/at91sam9rl.h
index 2bb359e60b97..d7bead7118da 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9rl.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9rl.h
@@ -72,7 +72,6 @@
72#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS) 72#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS)
73#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) 73#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
74#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) 74#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
75#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
76#define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS) 75#define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS)
77#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) 76#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
78 77
@@ -84,6 +83,7 @@
84#define AT91SAM9RL_BASE_PIOB 0xfffff600 83#define AT91SAM9RL_BASE_PIOB 0xfffff600
85#define AT91SAM9RL_BASE_PIOC 0xfffff800 84#define AT91SAM9RL_BASE_PIOC 0xfffff800
86#define AT91SAM9RL_BASE_PIOD 0xfffffa00 85#define AT91SAM9RL_BASE_PIOD 0xfffffa00
86#define AT91SAM9RL_BASE_RSTC 0xfffffd00
87#define AT91SAM9RL_BASE_SHDWC 0xfffffd10 87#define AT91SAM9RL_BASE_SHDWC 0xfffffd10
88#define AT91SAM9RL_BASE_RTT 0xfffffd20 88#define AT91SAM9RL_BASE_RTT 0xfffffd20
89#define AT91SAM9RL_BASE_PIT 0xfffffd30 89#define AT91SAM9RL_BASE_PIT 0xfffffd30
diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h
index d0b377b21bd7..3b33f07b1e11 100644
--- a/arch/arm/mach-at91/include/mach/board.h
+++ b/arch/arm/mach-at91/include/mach/board.h
@@ -88,7 +88,7 @@ extern void __init at91_add_device_eth(struct macb_platform_data *data);
88struct at91_usbh_data { 88struct at91_usbh_data {
89 u8 ports; /* number of ports on root hub */ 89 u8 ports; /* number of ports on root hub */
90 int vbus_pin[2]; /* port power-control pin */ 90 int vbus_pin[2]; /* port power-control pin */
91 u8 vbus_pin_inverted; 91 u8 vbus_pin_active_low[2];
92 u8 overcurrent_supported; 92 u8 overcurrent_supported;
93 int overcurrent_pin[2]; 93 int overcurrent_pin[2];
94 u8 overcurrent_status[2]; 94 u8 overcurrent_status[2];
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index 62ad95556c36..1606379ac284 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -34,7 +34,6 @@
34/* 34/*
35 * Show the reason for the previous system reset. 35 * Show the reason for the previous system reset.
36 */ 36 */
37#if defined(AT91_RSTC)
38 37
39#include <mach/at91_rstc.h> 38#include <mach/at91_rstc.h>
40#include <mach/at91_shdwc.h> 39#include <mach/at91_shdwc.h>
@@ -58,10 +57,10 @@ static void __init show_reset_status(void)
58 char *reason, *r2 = reset; 57 char *reason, *r2 = reset;
59 u32 reset_type, wake_type; 58 u32 reset_type, wake_type;
60 59
61 if (!at91_shdwc_base) 60 if (!at91_shdwc_base || !at91_rstc_base)
62 return; 61 return;
63 62
64 reset_type = at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_RSTTYP; 63 reset_type = at91_rstc_read(AT91_RSTC_SR) & AT91_RSTC_RSTTYP;
65 wake_type = at91_shdwc_read(AT91_SHDW_SR); 64 wake_type = at91_shdwc_read(AT91_SHDW_SR);
66 65
67 switch (reset_type) { 66 switch (reset_type) {
@@ -102,10 +101,6 @@ static void __init show_reset_status(void)
102 } 101 }
103 pr_info("AT91: Starting after %s %s\n", reason, r2); 102 pr_info("AT91: Starting after %s %s\n", reason, r2);
104} 103}
105#else
106static void __init show_reset_status(void) {}
107#endif
108
109 104
110static int at91_pm_valid_state(suspend_state_t state) 105static int at91_pm_valid_state(suspend_state_t state)
111{ 106{
diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h
index ce9a20699111..7eb40d24242f 100644
--- a/arch/arm/mach-at91/pm.h
+++ b/arch/arm/mach-at91/pm.h
@@ -25,21 +25,21 @@ static inline u32 sdram_selfrefresh_enable(void)
25 : : "r" (0)) 25 : : "r" (0))
26 26
27#elif defined(CONFIG_ARCH_AT91CAP9) 27#elif defined(CONFIG_ARCH_AT91CAP9)
28#include <mach/at91cap9_ddrsdr.h> 28#include <mach/at91sam9_ddrsdr.h>
29 29
30 30
31static inline u32 sdram_selfrefresh_enable(void) 31static inline u32 sdram_selfrefresh_enable(void)
32{ 32{
33 u32 saved_lpr, lpr; 33 u32 saved_lpr, lpr;
34 34
35 saved_lpr = at91_ramc_read(0, AT91_DDRSDRC_LPR); 35 saved_lpr = at91_ramc_read(0, AT91CAP9_DDRSDRC_LPR);
36 36
37 lpr = saved_lpr & ~AT91_DDRSDRC_LPCB; 37 lpr = saved_lpr & ~AT91_DDRSDRC_LPCB;
38 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr | AT91_DDRSDRC_LPCB_SELF_REFRESH); 38 at91_ramc_write(0, AT91CAP9_DDRSDRC_LPR, lpr | AT91_DDRSDRC_LPCB_SELF_REFRESH);
39 return saved_lpr; 39 return saved_lpr;
40} 40}
41 41
42#define sdram_selfrefresh_disable(saved_lpr) at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr) 42#define sdram_selfrefresh_disable(saved_lpr) at91_ramc_write(0, AT91CAP9_DDRSDRC_LPR, saved_lpr)
43#define wait_for_interrupt_enable() cpu_do_idle() 43#define wait_for_interrupt_enable() cpu_do_idle()
44 44
45#elif defined(CONFIG_ARCH_AT91SAM9G45) 45#elif defined(CONFIG_ARCH_AT91SAM9G45)
diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S
index f7922a436172..92dfb8461392 100644
--- a/arch/arm/mach-at91/pm_slowclock.S
+++ b/arch/arm/mach-at91/pm_slowclock.S
@@ -18,9 +18,8 @@
18 18
19#if defined(CONFIG_ARCH_AT91RM9200) 19#if defined(CONFIG_ARCH_AT91RM9200)
20#include <mach/at91rm9200_mc.h> 20#include <mach/at91rm9200_mc.h>
21#elif defined(CONFIG_ARCH_AT91CAP9) 21#elif defined(CONFIG_ARCH_AT91CAP9) \
22#include <mach/at91cap9_ddrsdr.h> 22 || defined(CONFIG_ARCH_AT91SAM9G45)
23#elif defined(CONFIG_ARCH_AT91SAM9G45)
24#include <mach/at91sam9_ddrsdr.h> 23#include <mach/at91sam9_ddrsdr.h>
25#else 24#else
26#include <mach/at91sam9_sdramc.h> 25#include <mach/at91sam9_sdramc.h>
diff --git a/arch/arm/mach-at91/sam9_smc.c b/arch/arm/mach-at91/sam9_smc.c
index 8294783b679d..99a0a1d2b7dc 100644
--- a/arch/arm/mach-at91/sam9_smc.c
+++ b/arch/arm/mach-at91/sam9_smc.c
@@ -2,6 +2,7 @@
2 * linux/arch/arm/mach-at91/sam9_smc.c 2 * linux/arch/arm/mach-at91/sam9_smc.c
3 * 3 *
4 * Copyright (C) 2008 Andrew Victor 4 * Copyright (C) 2008 Andrew Victor
5 * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 * 6 *
6 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as 8 * it under the terms of the GNU General Public License version 2 as
@@ -22,7 +23,22 @@
22 23
23static void __iomem *smc_base_addr[2]; 24static void __iomem *smc_base_addr[2];
24 25
25static void __init sam9_smc_cs_configure(void __iomem *base, struct sam9_smc_config* config) 26static void sam9_smc_cs_write_mode(void __iomem *base,
27 struct sam9_smc_config *config)
28{
29 __raw_writel(config->mode
30 | AT91_SMC_TDF_(config->tdf_cycles),
31 base + AT91_SMC_MODE);
32}
33
34void sam9_smc_write_mode(int id, int cs,
35 struct sam9_smc_config *config)
36{
37 sam9_smc_cs_write_mode(AT91_SMC_CS(id, cs), config);
38}
39
40static void sam9_smc_cs_configure(void __iomem *base,
41 struct sam9_smc_config *config)
26{ 42{
27 43
28 /* Setup register */ 44 /* Setup register */
@@ -45,16 +61,66 @@ static void __init sam9_smc_cs_configure(void __iomem *base, struct sam9_smc_con
45 base + AT91_SMC_CYCLE); 61 base + AT91_SMC_CYCLE);
46 62
47 /* Mode register */ 63 /* Mode register */
48 __raw_writel(config->mode 64 sam9_smc_cs_write_mode(base, config);
49 | AT91_SMC_TDF_(config->tdf_cycles),
50 base + AT91_SMC_MODE);
51} 65}
52 66
53void __init sam9_smc_configure(int id, int cs, struct sam9_smc_config* config) 67void sam9_smc_configure(int id, int cs,
68 struct sam9_smc_config *config)
54{ 69{
55 sam9_smc_cs_configure(AT91_SMC_CS(id, cs), config); 70 sam9_smc_cs_configure(AT91_SMC_CS(id, cs), config);
56} 71}
57 72
73static void sam9_smc_cs_read_mode(void __iomem *base,
74 struct sam9_smc_config *config)
75{
76 u32 val = __raw_readl(base + AT91_SMC_MODE);
77
78 config->mode = (val & ~AT91_SMC_NWECYCLE);
79 config->tdf_cycles = (val & AT91_SMC_NWECYCLE) >> 16 ;
80}
81
82void sam9_smc_read_mode(int id, int cs,
83 struct sam9_smc_config *config)
84{
85 sam9_smc_cs_read_mode(AT91_SMC_CS(id, cs), config);
86}
87
88static void sam9_smc_cs_read(void __iomem *base,
89 struct sam9_smc_config *config)
90{
91 u32 val;
92
93 /* Setup register */
94 val = __raw_readl(base + AT91_SMC_SETUP);
95
96 config->nwe_setup = val & AT91_SMC_NWESETUP;
97 config->ncs_write_setup = (val & AT91_SMC_NCS_WRSETUP) >> 8;
98 config->nrd_setup = (val & AT91_SMC_NRDSETUP) >> 16;
99 config->ncs_read_setup = (val & AT91_SMC_NCS_RDSETUP) >> 24;
100
101 /* Pulse register */
102 val = __raw_readl(base + AT91_SMC_PULSE);
103
104 config->nwe_setup = val & AT91_SMC_NWEPULSE;
105 config->ncs_write_pulse = (val & AT91_SMC_NCS_WRPULSE) >> 8;
106 config->nrd_pulse = (val & AT91_SMC_NRDPULSE) >> 16;
107 config->ncs_read_pulse = (val & AT91_SMC_NCS_RDPULSE) >> 24;
108
109 /* Cycle register */
110 val = __raw_readl(base + AT91_SMC_CYCLE);
111
112 config->write_cycle = val & AT91_SMC_NWECYCLE;
113 config->read_cycle = (val & AT91_SMC_NRDCYCLE) >> 16;
114
115 /* Mode register */
116 sam9_smc_cs_read_mode(base, config);
117}
118
119void sam9_smc_read(int id, int cs, struct sam9_smc_config *config)
120{
121 sam9_smc_cs_read(AT91_SMC_CS(id, cs), config);
122}
123
58void __init at91sam9_ioremap_smc(int id, u32 addr) 124void __init at91sam9_ioremap_smc(int id, u32 addr)
59{ 125{
60 if (id > 1) { 126 if (id > 1) {
diff --git a/arch/arm/mach-at91/sam9_smc.h b/arch/arm/mach-at91/sam9_smc.h
index 039c5ce17aec..3e52dcd4a59f 100644
--- a/arch/arm/mach-at91/sam9_smc.h
+++ b/arch/arm/mach-at91/sam9_smc.h
@@ -8,27 +8,4 @@
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 */ 9 */
10 10
11struct sam9_smc_config {
12 /* Setup register */
13 u8 ncs_read_setup;
14 u8 nrd_setup;
15 u8 ncs_write_setup;
16 u8 nwe_setup;
17
18 /* Pulse register */
19 u8 ncs_read_pulse;
20 u8 nrd_pulse;
21 u8 ncs_write_pulse;
22 u8 nwe_pulse;
23
24 /* Cycle register */
25 u16 read_cycle;
26 u16 write_cycle;
27
28 /* Mode register */
29 u32 mode;
30 u8 tdf_cycles:4;
31};
32
33extern void __init sam9_smc_configure(int id, int cs, struct sam9_smc_config* config);
34extern void __init at91sam9_ioremap_smc(int id, u32 addr); 11extern void __init at91sam9_ioremap_smc(int id, u32 addr);
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index 8bdcc3cb6012..69d3fc4c46f3 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -29,9 +29,12 @@ EXPORT_SYMBOL(at91_soc_initdata);
29void __init at91rm9200_set_type(int type) 29void __init at91rm9200_set_type(int type)
30{ 30{
31 if (type == ARCH_REVISON_9200_PQFP) 31 if (type == ARCH_REVISON_9200_PQFP)
32 at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA;
33 else
34 at91_soc_initdata.subtype = AT91_SOC_RM9200_PQFP; 32 at91_soc_initdata.subtype = AT91_SOC_RM9200_PQFP;
33 else
34 at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA;
35
36 pr_info("AT91: filled in soc subtype: %s\n",
37 at91_get_soc_subtype(&at91_soc_initdata));
35} 38}
36 39
37void __init at91_init_irq_default(void) 40void __init at91_init_irq_default(void)
@@ -281,6 +284,15 @@ void __init at91_ioremap_shdwc(u32 base_addr)
281 pm_power_off = at91sam9_poweroff; 284 pm_power_off = at91sam9_poweroff;
282} 285}
283 286
287void __iomem *at91_rstc_base;
288
289void __init at91_ioremap_rstc(u32 base_addr)
290{
291 at91_rstc_base = ioremap(base_addr, 16);
292 if (!at91_rstc_base)
293 panic("Impossible to ioremap at91_rstc_base\n");
294}
295
284void __init at91_initialize(unsigned long main_clock) 296void __init at91_initialize(unsigned long main_clock)
285{ 297{
286 at91_boot_soc.ioremap_registers(); 298 at91_boot_soc.ioremap_registers();
diff --git a/arch/arm/mach-bcmring/arch.c b/arch/arm/mach-bcmring/arch.c
index 9e5e7552498c..45c97b1ee9b1 100644
--- a/arch/arm/mach-bcmring/arch.c
+++ b/arch/arm/mach-bcmring/arch.c
@@ -194,6 +194,6 @@ MACHINE_START(BCMRING, "BCMRING")
194 .init_early = bcmring_init_early, 194 .init_early = bcmring_init_early,
195 .init_irq = bcmring_init_irq, 195 .init_irq = bcmring_init_irq,
196 .timer = &bcmring_timer, 196 .timer = &bcmring_timer,
197 .init_machine = bcmring_init_machine 197 .init_machine = bcmring_init_machine,
198 .restart = bcmring_restart, 198 .restart = bcmring_restart,
199MACHINE_END 199MACHINE_END
diff --git a/arch/arm/mach-bcmring/dma.c b/arch/arm/mach-bcmring/dma.c
index 1a1a27dd5654..e5fd241fccdc 100644
--- a/arch/arm/mach-bcmring/dma.c
+++ b/arch/arm/mach-bcmring/dma.c
@@ -33,17 +33,10 @@
33 33
34#include <mach/timer.h> 34#include <mach/timer.h>
35 35
36#include <linux/mm.h>
37#include <linux/pfn.h> 36#include <linux/pfn.h>
38#include <linux/atomic.h> 37#include <linux/atomic.h>
39#include <linux/sched.h>
40#include <mach/dma.h> 38#include <mach/dma.h>
41 39
42/* I don't quite understand why dc4 fails when this is set to 1 and DMA is enabled */
43/* especially since dc4 doesn't use kmalloc'd memory. */
44
45#define ALLOW_MAP_OF_KMALLOC_MEMORY 0
46
47/* ---- Public Variables ------------------------------------------------- */ 40/* ---- Public Variables ------------------------------------------------- */
48 41
49/* ---- Private Constants and Types -------------------------------------- */ 42/* ---- Private Constants and Types -------------------------------------- */
@@ -53,24 +46,12 @@
53#define CONTROLLER_FROM_HANDLE(handle) (((handle) >> 4) & 0x0f) 46#define CONTROLLER_FROM_HANDLE(handle) (((handle) >> 4) & 0x0f)
54#define CHANNEL_FROM_HANDLE(handle) ((handle) & 0x0f) 47#define CHANNEL_FROM_HANDLE(handle) ((handle) & 0x0f)
55 48
56#define DMA_MAP_DEBUG 0
57
58#if DMA_MAP_DEBUG
59# define DMA_MAP_PRINT(fmt, args...) printk("%s: " fmt, __func__, ## args)
60#else
61# define DMA_MAP_PRINT(fmt, args...)
62#endif
63 49
64/* ---- Private Variables ------------------------------------------------ */ 50/* ---- Private Variables ------------------------------------------------ */
65 51
66static DMA_Global_t gDMA; 52static DMA_Global_t gDMA;
67static struct proc_dir_entry *gDmaDir; 53static struct proc_dir_entry *gDmaDir;
68 54
69static atomic_t gDmaStatMemTypeKmalloc = ATOMIC_INIT(0);
70static atomic_t gDmaStatMemTypeVmalloc = ATOMIC_INIT(0);
71static atomic_t gDmaStatMemTypeUser = ATOMIC_INIT(0);
72static atomic_t gDmaStatMemTypeCoherent = ATOMIC_INIT(0);
73
74#include "dma_device.c" 55#include "dma_device.c"
75 56
76/* ---- Private Function Prototypes -------------------------------------- */ 57/* ---- Private Function Prototypes -------------------------------------- */
@@ -79,34 +60,6 @@ static atomic_t gDmaStatMemTypeCoherent = ATOMIC_INIT(0);
79 60
80/****************************************************************************/ 61/****************************************************************************/
81/** 62/**
82* Displays information for /proc/dma/mem-type
83*/
84/****************************************************************************/
85
86static int dma_proc_read_mem_type(char *buf, char **start, off_t offset,
87 int count, int *eof, void *data)
88{
89 int len = 0;
90
91 len += sprintf(buf + len, "dma_map_mem statistics\n");
92 len +=
93 sprintf(buf + len, "coherent: %d\n",
94 atomic_read(&gDmaStatMemTypeCoherent));
95 len +=
96 sprintf(buf + len, "kmalloc: %d\n",
97 atomic_read(&gDmaStatMemTypeKmalloc));
98 len +=
99 sprintf(buf + len, "vmalloc: %d\n",
100 atomic_read(&gDmaStatMemTypeVmalloc));
101 len +=
102 sprintf(buf + len, "user: %d\n",
103 atomic_read(&gDmaStatMemTypeUser));
104
105 return len;
106}
107
108/****************************************************************************/
109/**
110* Displays information for /proc/dma/channels 63* Displays information for /proc/dma/channels
111*/ 64*/
112/****************************************************************************/ 65/****************************************************************************/
@@ -846,8 +799,6 @@ int dma_init(void)
846 dma_proc_read_channels, NULL); 799 dma_proc_read_channels, NULL);
847 create_proc_read_entry("devices", 0, gDmaDir, 800 create_proc_read_entry("devices", 0, gDmaDir,
848 dma_proc_read_devices, NULL); 801 dma_proc_read_devices, NULL);
849 create_proc_read_entry("mem-type", 0, gDmaDir,
850 dma_proc_read_mem_type, NULL);
851 } 802 }
852 803
853out: 804out:
@@ -1565,767 +1516,3 @@ int dma_set_device_handler(DMA_Device_t dev, /* Device to set the callback for.
1565} 1516}
1566 1517
1567EXPORT_SYMBOL(dma_set_device_handler); 1518EXPORT_SYMBOL(dma_set_device_handler);
1568
1569/****************************************************************************/
1570/**
1571* Initializes a memory mapping structure
1572*/
1573/****************************************************************************/
1574
1575int dma_init_mem_map(DMA_MemMap_t *memMap)
1576{
1577 memset(memMap, 0, sizeof(*memMap));
1578
1579 sema_init(&memMap->lock, 1);
1580
1581 return 0;
1582}
1583
1584EXPORT_SYMBOL(dma_init_mem_map);
1585
1586/****************************************************************************/
1587/**
1588* Releases any memory currently being held by a memory mapping structure.
1589*/
1590/****************************************************************************/
1591
1592int dma_term_mem_map(DMA_MemMap_t *memMap)
1593{
1594 down(&memMap->lock); /* Just being paranoid */
1595
1596 /* Free up any allocated memory */
1597
1598 up(&memMap->lock);
1599 memset(memMap, 0, sizeof(*memMap));
1600
1601 return 0;
1602}
1603
1604EXPORT_SYMBOL(dma_term_mem_map);
1605
1606/****************************************************************************/
1607/**
1608* Looks at a memory address and categorizes it.
1609*
1610* @return One of the values from the DMA_MemType_t enumeration.
1611*/
1612/****************************************************************************/
1613
1614DMA_MemType_t dma_mem_type(void *addr)
1615{
1616 unsigned long addrVal = (unsigned long)addr;
1617
1618 if (addrVal >= CONSISTENT_BASE) {
1619 /* NOTE: DMA virtual memory space starts at 0xFFxxxxxx */
1620
1621 /* dma_alloc_xxx pages are physically and virtually contiguous */
1622
1623 return DMA_MEM_TYPE_DMA;
1624 }
1625
1626 /* Technically, we could add one more classification. Addresses between VMALLOC_END */
1627 /* and the beginning of the DMA virtual address could be considered to be I/O space. */
1628 /* Right now, nobody cares about this particular classification, so we ignore it. */
1629
1630 if (is_vmalloc_addr(addr)) {
1631 /* Address comes from the vmalloc'd region. Pages are virtually */
1632 /* contiguous but NOT physically contiguous */
1633
1634 return DMA_MEM_TYPE_VMALLOC;
1635 }
1636
1637 if (addrVal >= PAGE_OFFSET) {
1638 /* PAGE_OFFSET is typically 0xC0000000 */
1639
1640 /* kmalloc'd pages are physically contiguous */
1641
1642 return DMA_MEM_TYPE_KMALLOC;
1643 }
1644
1645 return DMA_MEM_TYPE_USER;
1646}
1647
1648EXPORT_SYMBOL(dma_mem_type);
1649
1650/****************************************************************************/
1651/**
1652* Looks at a memory address and determines if we support DMA'ing to/from
1653* that type of memory.
1654*
1655* @return boolean -
1656* return value != 0 means dma supported
1657* return value == 0 means dma not supported
1658*/
1659/****************************************************************************/
1660
1661int dma_mem_supports_dma(void *addr)
1662{
1663 DMA_MemType_t memType = dma_mem_type(addr);
1664
1665 return (memType == DMA_MEM_TYPE_DMA)
1666#if ALLOW_MAP_OF_KMALLOC_MEMORY
1667 || (memType == DMA_MEM_TYPE_KMALLOC)
1668#endif
1669 || (memType == DMA_MEM_TYPE_USER);
1670}
1671
1672EXPORT_SYMBOL(dma_mem_supports_dma);
1673
1674/****************************************************************************/
1675/**
1676* Maps in a memory region such that it can be used for performing a DMA.
1677*
1678* @return
1679*/
1680/****************************************************************************/
1681
1682int dma_map_start(DMA_MemMap_t *memMap, /* Stores state information about the map */
1683 enum dma_data_direction dir /* Direction that the mapping will be going */
1684 ) {
1685 int rc;
1686
1687 down(&memMap->lock);
1688
1689 DMA_MAP_PRINT("memMap: %p\n", memMap);
1690
1691 if (memMap->inUse) {
1692 printk(KERN_ERR "%s: memory map %p is already being used\n",
1693 __func__, memMap);
1694 rc = -EBUSY;
1695 goto out;
1696 }
1697
1698 memMap->inUse = 1;
1699 memMap->dir = dir;
1700 memMap->numRegionsUsed = 0;
1701
1702 rc = 0;
1703
1704out:
1705
1706 DMA_MAP_PRINT("returning %d", rc);
1707
1708 up(&memMap->lock);
1709
1710 return rc;
1711}
1712
1713EXPORT_SYMBOL(dma_map_start);
1714
1715/****************************************************************************/
1716/**
1717* Adds a segment of memory to a memory map. Each segment is both
1718* physically and virtually contiguous.
1719*
1720* @return 0 on success, error code otherwise.
1721*/
1722/****************************************************************************/
1723
1724static int dma_map_add_segment(DMA_MemMap_t *memMap, /* Stores state information about the map */
1725 DMA_Region_t *region, /* Region that the segment belongs to */
1726 void *virtAddr, /* Virtual address of the segment being added */
1727 dma_addr_t physAddr, /* Physical address of the segment being added */
1728 size_t numBytes /* Number of bytes of the segment being added */
1729 ) {
1730 DMA_Segment_t *segment;
1731
1732 DMA_MAP_PRINT("memMap:%p va:%p pa:0x%x #:%d\n", memMap, virtAddr,
1733 physAddr, numBytes);
1734
1735 /* Sanity check */
1736
1737 if (((unsigned long)virtAddr < (unsigned long)region->virtAddr)
1738 || (((unsigned long)virtAddr + numBytes)) >
1739 ((unsigned long)region->virtAddr + region->numBytes)) {
1740 printk(KERN_ERR
1741 "%s: virtAddr %p is outside region @ %p len: %d\n",
1742 __func__, virtAddr, region->virtAddr, region->numBytes);
1743 return -EINVAL;
1744 }
1745
1746 if (region->numSegmentsUsed > 0) {
1747 /* Check to see if this segment is physically contiguous with the previous one */
1748
1749 segment = &region->segment[region->numSegmentsUsed - 1];
1750
1751 if ((segment->physAddr + segment->numBytes) == physAddr) {
1752 /* It is - just add on to the end */
1753
1754 DMA_MAP_PRINT("appending %d bytes to last segment\n",
1755 numBytes);
1756
1757 segment->numBytes += numBytes;
1758
1759 return 0;
1760 }
1761 }
1762
1763 /* Reallocate to hold more segments, if required. */
1764
1765 if (region->numSegmentsUsed >= region->numSegmentsAllocated) {
1766 DMA_Segment_t *newSegment;
1767 size_t oldSize =
1768 region->numSegmentsAllocated * sizeof(*newSegment);
1769 int newAlloc = region->numSegmentsAllocated + 4;
1770 size_t newSize = newAlloc * sizeof(*newSegment);
1771
1772 newSegment = kmalloc(newSize, GFP_KERNEL);
1773 if (newSegment == NULL) {
1774 return -ENOMEM;
1775 }
1776 memcpy(newSegment, region->segment, oldSize);
1777 memset(&((uint8_t *) newSegment)[oldSize], 0,
1778 newSize - oldSize);
1779 kfree(region->segment);
1780
1781 region->numSegmentsAllocated = newAlloc;
1782 region->segment = newSegment;
1783 }
1784
1785 segment = &region->segment[region->numSegmentsUsed];
1786 region->numSegmentsUsed++;
1787
1788 segment->virtAddr = virtAddr;
1789 segment->physAddr = physAddr;
1790 segment->numBytes = numBytes;
1791
1792 DMA_MAP_PRINT("returning success\n");
1793
1794 return 0;
1795}
1796
1797/****************************************************************************/
1798/**
1799* Adds a region of memory to a memory map. Each region is virtually
1800* contiguous, but not necessarily physically contiguous.
1801*
1802* @return 0 on success, error code otherwise.
1803*/
1804/****************************************************************************/
1805
1806int dma_map_add_region(DMA_MemMap_t *memMap, /* Stores state information about the map */
1807 void *mem, /* Virtual address that we want to get a map of */
1808 size_t numBytes /* Number of bytes being mapped */
1809 ) {
1810 unsigned long addr = (unsigned long)mem;
1811 unsigned int offset;
1812 int rc = 0;
1813 DMA_Region_t *region;
1814 dma_addr_t physAddr;
1815
1816 down(&memMap->lock);
1817
1818 DMA_MAP_PRINT("memMap:%p va:%p #:%d\n", memMap, mem, numBytes);
1819
1820 if (!memMap->inUse) {
1821 printk(KERN_ERR "%s: Make sure you call dma_map_start first\n",
1822 __func__);
1823 rc = -EINVAL;
1824 goto out;
1825 }
1826
1827 /* Reallocate to hold more regions. */
1828
1829 if (memMap->numRegionsUsed >= memMap->numRegionsAllocated) {
1830 DMA_Region_t *newRegion;
1831 size_t oldSize =
1832 memMap->numRegionsAllocated * sizeof(*newRegion);
1833 int newAlloc = memMap->numRegionsAllocated + 4;
1834 size_t newSize = newAlloc * sizeof(*newRegion);
1835
1836 newRegion = kmalloc(newSize, GFP_KERNEL);
1837 if (newRegion == NULL) {
1838 rc = -ENOMEM;
1839 goto out;
1840 }
1841 memcpy(newRegion, memMap->region, oldSize);
1842 memset(&((uint8_t *) newRegion)[oldSize], 0, newSize - oldSize);
1843
1844 kfree(memMap->region);
1845
1846 memMap->numRegionsAllocated = newAlloc;
1847 memMap->region = newRegion;
1848 }
1849
1850 region = &memMap->region[memMap->numRegionsUsed];
1851 memMap->numRegionsUsed++;
1852
1853 offset = addr & ~PAGE_MASK;
1854
1855 region->memType = dma_mem_type(mem);
1856 region->virtAddr = mem;
1857 region->numBytes = numBytes;
1858 region->numSegmentsUsed = 0;
1859 region->numLockedPages = 0;
1860 region->lockedPages = NULL;
1861
1862 switch (region->memType) {
1863 case DMA_MEM_TYPE_VMALLOC:
1864 {
1865 atomic_inc(&gDmaStatMemTypeVmalloc);
1866
1867 /* printk(KERN_ERR "%s: vmalloc'd pages are not supported\n", __func__); */
1868
1869 /* vmalloc'd pages are not physically contiguous */
1870
1871 rc = -EINVAL;
1872 break;
1873 }
1874
1875 case DMA_MEM_TYPE_KMALLOC:
1876 {
1877 atomic_inc(&gDmaStatMemTypeKmalloc);
1878
1879 /* kmalloc'd pages are physically contiguous, so they'll have exactly */
1880 /* one segment */
1881
1882#if ALLOW_MAP_OF_KMALLOC_MEMORY
1883 physAddr =
1884 dma_map_single(NULL, mem, numBytes, memMap->dir);
1885 rc = dma_map_add_segment(memMap, region, mem, physAddr,
1886 numBytes);
1887#else
1888 rc = -EINVAL;
1889#endif
1890 break;
1891 }
1892
1893 case DMA_MEM_TYPE_DMA:
1894 {
1895 /* dma_alloc_xxx pages are physically contiguous */
1896
1897 atomic_inc(&gDmaStatMemTypeCoherent);
1898
1899 physAddr = (vmalloc_to_pfn(mem) << PAGE_SHIFT) + offset;
1900
1901 dma_sync_single_for_cpu(NULL, physAddr, numBytes,
1902 memMap->dir);
1903 rc = dma_map_add_segment(memMap, region, mem, physAddr,
1904 numBytes);
1905 break;
1906 }
1907
1908 case DMA_MEM_TYPE_USER:
1909 {
1910 size_t firstPageOffset;
1911 size_t firstPageSize;
1912 struct page **pages;
1913 struct task_struct *userTask;
1914
1915 atomic_inc(&gDmaStatMemTypeUser);
1916
1917#if 1
1918 /* If the pages are user pages, then the dma_mem_map_set_user_task function */
1919 /* must have been previously called. */
1920
1921 if (memMap->userTask == NULL) {
1922 printk(KERN_ERR
1923 "%s: must call dma_mem_map_set_user_task when using user-mode memory\n",
1924 __func__);
1925 return -EINVAL;
1926 }
1927
1928 /* User pages need to be locked. */
1929
1930 firstPageOffset =
1931 (unsigned long)region->virtAddr & (PAGE_SIZE - 1);
1932 firstPageSize = PAGE_SIZE - firstPageOffset;
1933
1934 region->numLockedPages = (firstPageOffset
1935 + region->numBytes +
1936 PAGE_SIZE - 1) / PAGE_SIZE;
1937 pages =
1938 kmalloc(region->numLockedPages *
1939 sizeof(struct page *), GFP_KERNEL);
1940
1941 if (pages == NULL) {
1942 region->numLockedPages = 0;
1943 return -ENOMEM;
1944 }
1945
1946 userTask = memMap->userTask;
1947
1948 down_read(&userTask->mm->mmap_sem);
1949 rc = get_user_pages(userTask, /* task */
1950 userTask->mm, /* mm */
1951 (unsigned long)region->virtAddr, /* start */
1952 region->numLockedPages, /* len */
1953 memMap->dir == DMA_FROM_DEVICE, /* write */
1954 0, /* force */
1955 pages, /* pages (array of pointers to page) */
1956 NULL); /* vmas */
1957 up_read(&userTask->mm->mmap_sem);
1958
1959 if (rc != region->numLockedPages) {
1960 kfree(pages);
1961 region->numLockedPages = 0;
1962
1963 if (rc >= 0) {
1964 rc = -EINVAL;
1965 }
1966 } else {
1967 uint8_t *virtAddr = region->virtAddr;
1968 size_t bytesRemaining;
1969 int pageIdx;
1970
1971 rc = 0; /* Since get_user_pages returns +ve number */
1972
1973 region->lockedPages = pages;
1974
1975 /* We've locked the user pages. Now we need to walk them and figure */
1976 /* out the physical addresses. */
1977
1978 /* The first page may be partial */
1979
1980 dma_map_add_segment(memMap,
1981 region,
1982 virtAddr,
1983 PFN_PHYS(page_to_pfn
1984 (pages[0])) +
1985 firstPageOffset,
1986 firstPageSize);
1987
1988 virtAddr += firstPageSize;
1989 bytesRemaining =
1990 region->numBytes - firstPageSize;
1991
1992 for (pageIdx = 1;
1993 pageIdx < region->numLockedPages;
1994 pageIdx++) {
1995 size_t bytesThisPage =
1996 (bytesRemaining >
1997 PAGE_SIZE ? PAGE_SIZE :
1998 bytesRemaining);
1999
2000 DMA_MAP_PRINT
2001 ("pageIdx:%d pages[pageIdx]=%p pfn=%u phys=%u\n",
2002 pageIdx, pages[pageIdx],
2003 page_to_pfn(pages[pageIdx]),
2004 PFN_PHYS(page_to_pfn
2005 (pages[pageIdx])));
2006
2007 dma_map_add_segment(memMap,
2008 region,
2009 virtAddr,
2010 PFN_PHYS(page_to_pfn
2011 (pages
2012 [pageIdx])),
2013 bytesThisPage);
2014
2015 virtAddr += bytesThisPage;
2016 bytesRemaining -= bytesThisPage;
2017 }
2018 }
2019#else
2020 printk(KERN_ERR
2021 "%s: User mode pages are not yet supported\n",
2022 __func__);
2023
2024 /* user pages are not physically contiguous */
2025
2026 rc = -EINVAL;
2027#endif
2028 break;
2029 }
2030
2031 default:
2032 {
2033 printk(KERN_ERR "%s: Unsupported memory type: %d\n",
2034 __func__, region->memType);
2035
2036 rc = -EINVAL;
2037 break;
2038 }
2039 }
2040
2041 if (rc != 0) {
2042 memMap->numRegionsUsed--;
2043 }
2044
2045out:
2046
2047 DMA_MAP_PRINT("returning %d\n", rc);
2048
2049 up(&memMap->lock);
2050
2051 return rc;
2052}
2053
2054EXPORT_SYMBOL(dma_map_add_segment);
2055
2056/****************************************************************************/
2057/**
2058* Maps in a memory region such that it can be used for performing a DMA.
2059*
2060* @return 0 on success, error code otherwise.
2061*/
2062/****************************************************************************/
2063
2064int dma_map_mem(DMA_MemMap_t *memMap, /* Stores state information about the map */
2065 void *mem, /* Virtual address that we want to get a map of */
2066 size_t numBytes, /* Number of bytes being mapped */
2067 enum dma_data_direction dir /* Direction that the mapping will be going */
2068 ) {
2069 int rc;
2070
2071 rc = dma_map_start(memMap, dir);
2072 if (rc == 0) {
2073 rc = dma_map_add_region(memMap, mem, numBytes);
2074 if (rc < 0) {
2075 /* Since the add fails, this function will fail, and the caller won't */
2076 /* call unmap, so we need to do it here. */
2077
2078 dma_unmap(memMap, 0);
2079 }
2080 }
2081
2082 return rc;
2083}
2084
2085EXPORT_SYMBOL(dma_map_mem);
2086
2087/****************************************************************************/
2088/**
2089* Setup a descriptor ring for a given memory map.
2090*
2091* It is assumed that the descriptor ring has already been initialized, and
2092* this routine will only reallocate a new descriptor ring if the existing
2093* one is too small.
2094*
2095* @return 0 on success, error code otherwise.
2096*/
2097/****************************************************************************/
2098
2099int dma_map_create_descriptor_ring(DMA_Device_t dev, /* DMA device (where the ring is stored) */
2100 DMA_MemMap_t *memMap, /* Memory map that will be used */
2101 dma_addr_t devPhysAddr /* Physical address of device */
2102 ) {
2103 int rc;
2104 int numDescriptors;
2105 DMA_DeviceAttribute_t *devAttr;
2106 DMA_Region_t *region;
2107 DMA_Segment_t *segment;
2108 dma_addr_t srcPhysAddr;
2109 dma_addr_t dstPhysAddr;
2110 int regionIdx;
2111 int segmentIdx;
2112
2113 devAttr = &DMA_gDeviceAttribute[dev];
2114
2115 down(&memMap->lock);
2116
2117 /* Figure out how many descriptors we need */
2118
2119 numDescriptors = 0;
2120 for (regionIdx = 0; regionIdx < memMap->numRegionsUsed; regionIdx++) {
2121 region = &memMap->region[regionIdx];
2122
2123 for (segmentIdx = 0; segmentIdx < region->numSegmentsUsed;
2124 segmentIdx++) {
2125 segment = &region->segment[segmentIdx];
2126
2127 if (memMap->dir == DMA_TO_DEVICE) {
2128 srcPhysAddr = segment->physAddr;
2129 dstPhysAddr = devPhysAddr;
2130 } else {
2131 srcPhysAddr = devPhysAddr;
2132 dstPhysAddr = segment->physAddr;
2133 }
2134
2135 rc =
2136 dma_calculate_descriptor_count(dev, srcPhysAddr,
2137 dstPhysAddr,
2138 segment->
2139 numBytes);
2140 if (rc < 0) {
2141 printk(KERN_ERR
2142 "%s: dma_calculate_descriptor_count failed: %d\n",
2143 __func__, rc);
2144 goto out;
2145 }
2146 numDescriptors += rc;
2147 }
2148 }
2149
2150 /* Adjust the size of the ring, if it isn't big enough */
2151
2152 if (numDescriptors > devAttr->ring.descriptorsAllocated) {
2153 dma_free_descriptor_ring(&devAttr->ring);
2154 rc =
2155 dma_alloc_descriptor_ring(&devAttr->ring,
2156 numDescriptors);
2157 if (rc < 0) {
2158 printk(KERN_ERR
2159 "%s: dma_alloc_descriptor_ring failed: %d\n",
2160 __func__, rc);
2161 goto out;
2162 }
2163 } else {
2164 rc =
2165 dma_init_descriptor_ring(&devAttr->ring,
2166 numDescriptors);
2167 if (rc < 0) {
2168 printk(KERN_ERR
2169 "%s: dma_init_descriptor_ring failed: %d\n",
2170 __func__, rc);
2171 goto out;
2172 }
2173 }
2174
2175 /* Populate the descriptors */
2176
2177 for (regionIdx = 0; regionIdx < memMap->numRegionsUsed; regionIdx++) {
2178 region = &memMap->region[regionIdx];
2179
2180 for (segmentIdx = 0; segmentIdx < region->numSegmentsUsed;
2181 segmentIdx++) {
2182 segment = &region->segment[segmentIdx];
2183
2184 if (memMap->dir == DMA_TO_DEVICE) {
2185 srcPhysAddr = segment->physAddr;
2186 dstPhysAddr = devPhysAddr;
2187 } else {
2188 srcPhysAddr = devPhysAddr;
2189 dstPhysAddr = segment->physAddr;
2190 }
2191
2192 rc =
2193 dma_add_descriptors(&devAttr->ring, dev,
2194 srcPhysAddr, dstPhysAddr,
2195 segment->numBytes);
2196 if (rc < 0) {
2197 printk(KERN_ERR
2198 "%s: dma_add_descriptors failed: %d\n",
2199 __func__, rc);
2200 goto out;
2201 }
2202 }
2203 }
2204
2205 rc = 0;
2206
2207out:
2208
2209 up(&memMap->lock);
2210 return rc;
2211}
2212
2213EXPORT_SYMBOL(dma_map_create_descriptor_ring);
2214
2215/****************************************************************************/
2216/**
2217* Maps in a memory region such that it can be used for performing a DMA.
2218*
2219* @return
2220*/
2221/****************************************************************************/
2222
2223int dma_unmap(DMA_MemMap_t *memMap, /* Stores state information about the map */
2224 int dirtied /* non-zero if any of the pages were modified */
2225 ) {
2226
2227 int rc = 0;
2228 int regionIdx;
2229 int segmentIdx;
2230 DMA_Region_t *region;
2231 DMA_Segment_t *segment;
2232
2233 down(&memMap->lock);
2234
2235 for (regionIdx = 0; regionIdx < memMap->numRegionsUsed; regionIdx++) {
2236 region = &memMap->region[regionIdx];
2237
2238 for (segmentIdx = 0; segmentIdx < region->numSegmentsUsed;
2239 segmentIdx++) {
2240 segment = &region->segment[segmentIdx];
2241
2242 switch (region->memType) {
2243 case DMA_MEM_TYPE_VMALLOC:
2244 {
2245 printk(KERN_ERR
2246 "%s: vmalloc'd pages are not yet supported\n",
2247 __func__);
2248 rc = -EINVAL;
2249 goto out;
2250 }
2251
2252 case DMA_MEM_TYPE_KMALLOC:
2253 {
2254#if ALLOW_MAP_OF_KMALLOC_MEMORY
2255 dma_unmap_single(NULL,
2256 segment->physAddr,
2257 segment->numBytes,
2258 memMap->dir);
2259#endif
2260 break;
2261 }
2262
2263 case DMA_MEM_TYPE_DMA:
2264 {
2265 dma_sync_single_for_cpu(NULL,
2266 segment->
2267 physAddr,
2268 segment->
2269 numBytes,
2270 memMap->dir);
2271 break;
2272 }
2273
2274 case DMA_MEM_TYPE_USER:
2275 {
2276 /* Nothing to do here. */
2277
2278 break;
2279 }
2280
2281 default:
2282 {
2283 printk(KERN_ERR
2284 "%s: Unsupported memory type: %d\n",
2285 __func__, region->memType);
2286 rc = -EINVAL;
2287 goto out;
2288 }
2289 }
2290
2291 segment->virtAddr = NULL;
2292 segment->physAddr = 0;
2293 segment->numBytes = 0;
2294 }
2295
2296 if (region->numLockedPages > 0) {
2297 int pageIdx;
2298
2299 /* Some user pages were locked. We need to go and unlock them now. */
2300
2301 for (pageIdx = 0; pageIdx < region->numLockedPages;
2302 pageIdx++) {
2303 struct page *page =
2304 region->lockedPages[pageIdx];
2305
2306 if (memMap->dir == DMA_FROM_DEVICE) {
2307 SetPageDirty(page);
2308 }
2309 page_cache_release(page);
2310 }
2311 kfree(region->lockedPages);
2312 region->numLockedPages = 0;
2313 region->lockedPages = NULL;
2314 }
2315
2316 region->memType = DMA_MEM_TYPE_NONE;
2317 region->virtAddr = NULL;
2318 region->numBytes = 0;
2319 region->numSegmentsUsed = 0;
2320 }
2321 memMap->userTask = NULL;
2322 memMap->numRegionsUsed = 0;
2323 memMap->inUse = 0;
2324
2325out:
2326 up(&memMap->lock);
2327
2328 return rc;
2329}
2330
2331EXPORT_SYMBOL(dma_unmap);
diff --git a/arch/arm/mach-bcmring/include/mach/dma.h b/arch/arm/mach-bcmring/include/mach/dma.h
index 1f2c5319c056..72543781207b 100644
--- a/arch/arm/mach-bcmring/include/mach/dma.h
+++ b/arch/arm/mach-bcmring/include/mach/dma.h
@@ -26,15 +26,9 @@
26/* ---- Include Files ---------------------------------------------------- */ 26/* ---- Include Files ---------------------------------------------------- */
27 27
28#include <linux/kernel.h> 28#include <linux/kernel.h>
29#include <linux/wait.h>
30#include <linux/semaphore.h> 29#include <linux/semaphore.h>
31#include <csp/dmacHw.h> 30#include <csp/dmacHw.h>
32#include <mach/timer.h> 31#include <mach/timer.h>
33#include <linux/scatterlist.h>
34#include <linux/dma-mapping.h>
35#include <linux/mm.h>
36#include <linux/vmalloc.h>
37#include <linux/pagemap.h>
38 32
39/* ---- Constants and Types ---------------------------------------------- */ 33/* ---- Constants and Types ---------------------------------------------- */
40 34
@@ -113,78 +107,6 @@ typedef struct {
113 107
114/**************************************************************************** 108/****************************************************************************
115* 109*
116* The DMA_MemType_t and DMA_MemMap_t are helper structures used to setup
117* DMA chains from a variety of memory sources.
118*
119*****************************************************************************/
120
121#define DMA_MEM_MAP_MIN_SIZE 4096 /* Pages less than this size are better */
122 /* off not being DMA'd. */
123
124typedef enum {
125 DMA_MEM_TYPE_NONE, /* Not a valid setting */
126 DMA_MEM_TYPE_VMALLOC, /* Memory came from vmalloc call */
127 DMA_MEM_TYPE_KMALLOC, /* Memory came from kmalloc call */
128 DMA_MEM_TYPE_DMA, /* Memory came from dma_alloc_xxx call */
129 DMA_MEM_TYPE_USER, /* Memory came from user space. */
130
131} DMA_MemType_t;
132
133/* A segment represents a physically and virtually contiguous chunk of memory. */
134/* i.e. each segment can be DMA'd */
135/* A user of the DMA code will add memory regions. Each region may need to be */
136/* represented by one or more segments. */
137
138typedef struct {
139 void *virtAddr; /* Virtual address used for this segment */
140 dma_addr_t physAddr; /* Physical address this segment maps to */
141 size_t numBytes; /* Size of the segment, in bytes */
142
143} DMA_Segment_t;
144
145/* A region represents a virtually contiguous chunk of memory, which may be */
146/* made up of multiple segments. */
147
148typedef struct {
149 DMA_MemType_t memType;
150 void *virtAddr;
151 size_t numBytes;
152
153 /* Each region (virtually contiguous) consists of one or more segments. Each */
154 /* segment is virtually and physically contiguous. */
155
156 int numSegmentsUsed;
157 int numSegmentsAllocated;
158 DMA_Segment_t *segment;
159
160 /* When a region corresponds to user memory, we need to lock all of the pages */
161 /* down before we can figure out the physical addresses. The lockedPage array contains */
162 /* the pages that were locked, and which subsequently need to be unlocked once the */
163 /* memory is unmapped. */
164
165 unsigned numLockedPages;
166 struct page **lockedPages;
167
168} DMA_Region_t;
169
170typedef struct {
171 int inUse; /* Is this mapping currently being used? */
172 struct semaphore lock; /* Acquired when using this structure */
173 enum dma_data_direction dir; /* Direction this transfer is intended for */
174
175 /* In the event that we're mapping user memory, we need to know which task */
176 /* the memory is for, so that we can obtain the correct mm locks. */
177
178 struct task_struct *userTask;
179
180 int numRegionsUsed;
181 int numRegionsAllocated;
182 DMA_Region_t *region;
183
184} DMA_MemMap_t;
185
186/****************************************************************************
187*
188* The DMA_DeviceAttribute_t contains information which describes a 110* The DMA_DeviceAttribute_t contains information which describes a
189* particular DMA device (or peripheral). 111* particular DMA device (or peripheral).
190* 112*
@@ -570,124 +492,6 @@ int dma_alloc_double_dst_descriptors(DMA_Handle_t handle, /* DMA Handle */
570 492
571/****************************************************************************/ 493/****************************************************************************/
572/** 494/**
573* Initializes a DMA_MemMap_t data structure
574*/
575/****************************************************************************/
576
577int dma_init_mem_map(DMA_MemMap_t *memMap /* Stores state information about the map */
578 );
579
580/****************************************************************************/
581/**
582* Releases any memory currently being held by a memory mapping structure.
583*/
584/****************************************************************************/
585
586int dma_term_mem_map(DMA_MemMap_t *memMap /* Stores state information about the map */
587 );
588
589/****************************************************************************/
590/**
591* Looks at a memory address and categorizes it.
592*
593* @return One of the values from the DMA_MemType_t enumeration.
594*/
595/****************************************************************************/
596
597DMA_MemType_t dma_mem_type(void *addr);
598
599/****************************************************************************/
600/**
601* Sets the process (aka userTask) associated with a mem map. This is
602* required if user-mode segments will be added to the mapping.
603*/
604/****************************************************************************/
605
606static inline void dma_mem_map_set_user_task(DMA_MemMap_t *memMap,
607 struct task_struct *task)
608{
609 memMap->userTask = task;
610}
611
612/****************************************************************************/
613/**
614* Looks at a memory address and determines if we support DMA'ing to/from
615* that type of memory.
616*
617* @return boolean -
618* return value != 0 means dma supported
619* return value == 0 means dma not supported
620*/
621/****************************************************************************/
622
623int dma_mem_supports_dma(void *addr);
624
625/****************************************************************************/
626/**
627* Initializes a memory map for use. Since this function acquires a
628* sempaphore within the memory map, it is VERY important that dma_unmap
629* be called when you're finished using the map.
630*/
631/****************************************************************************/
632
633int dma_map_start(DMA_MemMap_t *memMap, /* Stores state information about the map */
634 enum dma_data_direction dir /* Direction that the mapping will be going */
635 );
636
637/****************************************************************************/
638/**
639* Adds a segment of memory to a memory map.
640*
641* @return 0 on success, error code otherwise.
642*/
643/****************************************************************************/
644
645int dma_map_add_region(DMA_MemMap_t *memMap, /* Stores state information about the map */
646 void *mem, /* Virtual address that we want to get a map of */
647 size_t numBytes /* Number of bytes being mapped */
648 );
649
650/****************************************************************************/
651/**
652* Creates a descriptor ring from a memory mapping.
653*
654* @return 0 on success, error code otherwise.
655*/
656/****************************************************************************/
657
658int dma_map_create_descriptor_ring(DMA_Device_t dev, /* DMA device (where the ring is stored) */
659 DMA_MemMap_t *memMap, /* Memory map that will be used */
660 dma_addr_t devPhysAddr /* Physical address of device */
661 );
662
663/****************************************************************************/
664/**
665* Maps in a memory region such that it can be used for performing a DMA.
666*
667* @return
668*/
669/****************************************************************************/
670
671int dma_map_mem(DMA_MemMap_t *memMap, /* Stores state information about the map */
672 void *addr, /* Virtual address that we want to get a map of */
673 size_t count, /* Number of bytes being mapped */
674 enum dma_data_direction dir /* Direction that the mapping will be going */
675 );
676
677/****************************************************************************/
678/**
679* Maps in a memory region such that it can be used for performing a DMA.
680*
681* @return
682*/
683/****************************************************************************/
684
685int dma_unmap(DMA_MemMap_t *memMap, /* Stores state information about the map */
686 int dirtied /* non-zero if any of the pages were modified */
687 );
688
689/****************************************************************************/
690/**
691* Initiates a transfer when the descriptors have already been setup. 495* Initiates a transfer when the descriptors have already been setup.
692* 496*
693* This is a special case, and normally, the dma_transfer_xxx functions should 497* This is a special case, and normally, the dma_transfer_xxx functions should
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index 6b22b543a83f..d5088900af6c 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -44,7 +44,7 @@
44#include <mach/aemif.h> 44#include <mach/aemif.h>
45#include <mach/spi.h> 45#include <mach/spi.h>
46 46
47#define DA850_EVM_PHY_ID "0:00" 47#define DA850_EVM_PHY_ID "davinci_mdio-0:00"
48#define DA850_LCD_PWR_PIN GPIO_TO_PIN(2, 8) 48#define DA850_LCD_PWR_PIN GPIO_TO_PIN(2, 8)
49#define DA850_LCD_BL_PIN GPIO_TO_PIN(2, 15) 49#define DA850_LCD_BL_PIN GPIO_TO_PIN(2, 15)
50 50
diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c
index 346e1de2f5a8..849311d3cb7c 100644
--- a/arch/arm/mach-davinci/board-dm365-evm.c
+++ b/arch/arm/mach-davinci/board-dm365-evm.c
@@ -54,7 +54,7 @@ static inline int have_tvp7002(void)
54 return 0; 54 return 0;
55} 55}
56 56
57#define DM365_EVM_PHY_ID "0:01" 57#define DM365_EVM_PHY_ID "davinci_mdio-0:01"
58/* 58/*
59 * A MAX-II CPLD is used for various board control functions. 59 * A MAX-II CPLD is used for various board control functions.
60 */ 60 */
diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c
index a64b49cfedca..1247ecdcf752 100644
--- a/arch/arm/mach-davinci/board-dm644x-evm.c
+++ b/arch/arm/mach-davinci/board-dm644x-evm.c
@@ -40,7 +40,7 @@
40#include <mach/usb.h> 40#include <mach/usb.h>
41#include <mach/aemif.h> 41#include <mach/aemif.h>
42 42
43#define DM644X_EVM_PHY_ID "0:01" 43#define DM644X_EVM_PHY_ID "davinci_mdio-0:01"
44#define LXT971_PHY_ID (0x001378e2) 44#define LXT971_PHY_ID (0x001378e2)
45#define LXT971_PHY_MASK (0xfffffff0) 45#define LXT971_PHY_MASK (0xfffffff0)
46 46
diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c
index 64017558860b..872ac69fa049 100644
--- a/arch/arm/mach-davinci/board-dm646x-evm.c
+++ b/arch/arm/mach-davinci/board-dm646x-evm.c
@@ -736,7 +736,7 @@ static struct davinci_uart_config uart_config __initdata = {
736 .enabled_uarts = (1 << 0), 736 .enabled_uarts = (1 << 0),
737}; 737};
738 738
739#define DM646X_EVM_PHY_ID "0:01" 739#define DM646X_EVM_PHY_ID "davinci_mdio-0:01"
740/* 740/*
741 * The following EDMA channels/slots are not being used by drivers (for 741 * The following EDMA channels/slots are not being used by drivers (for
742 * example: Timer, GPIO, UART events etc) on dm646x, hence they are being 742 * example: Timer, GPIO, UART events etc) on dm646x, hence they are being
diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c
index 6c4a16415d47..8d34f513d415 100644
--- a/arch/arm/mach-davinci/board-neuros-osd2.c
+++ b/arch/arm/mach-davinci/board-neuros-osd2.c
@@ -39,7 +39,7 @@
39#include <mach/mmc.h> 39#include <mach/mmc.h>
40#include <mach/usb.h> 40#include <mach/usb.h>
41 41
42#define NEUROS_OSD2_PHY_ID "0:01" 42#define NEUROS_OSD2_PHY_ID "davinci_mdio-0:01"
43#define LXT971_PHY_ID 0x001378e2 43#define LXT971_PHY_ID 0x001378e2
44#define LXT971_PHY_MASK 0xfffffff0 44#define LXT971_PHY_MASK 0xfffffff0
45 45
diff --git a/arch/arm/mach-davinci/board-omapl138-hawk.c b/arch/arm/mach-davinci/board-omapl138-hawk.c
index e7c0c7c53493..45e815760a27 100644
--- a/arch/arm/mach-davinci/board-omapl138-hawk.c
+++ b/arch/arm/mach-davinci/board-omapl138-hawk.c
@@ -21,7 +21,7 @@
21#include <mach/da8xx.h> 21#include <mach/da8xx.h>
22#include <mach/mux.h> 22#include <mach/mux.h>
23 23
24#define HAWKBOARD_PHY_ID "0:07" 24#define HAWKBOARD_PHY_ID "davinci_mdio-0:07"
25#define DA850_HAWK_MMCSD_CD_PIN GPIO_TO_PIN(3, 12) 25#define DA850_HAWK_MMCSD_CD_PIN GPIO_TO_PIN(3, 12)
26#define DA850_HAWK_MMCSD_WP_PIN GPIO_TO_PIN(3, 13) 26#define DA850_HAWK_MMCSD_WP_PIN GPIO_TO_PIN(3, 13)
27 27
diff --git a/arch/arm/mach-davinci/board-sffsdr.c b/arch/arm/mach-davinci/board-sffsdr.c
index 0b136a831c59..31da3c5b2ba3 100644
--- a/arch/arm/mach-davinci/board-sffsdr.c
+++ b/arch/arm/mach-davinci/board-sffsdr.c
@@ -42,7 +42,7 @@
42#include <mach/mux.h> 42#include <mach/mux.h>
43#include <mach/usb.h> 43#include <mach/usb.h>
44 44
45#define SFFSDR_PHY_ID "0:01" 45#define SFFSDR_PHY_ID "davinci_mdio-0:01"
46static struct mtd_partition davinci_sffsdr_nandflash_partition[] = { 46static struct mtd_partition davinci_sffsdr_nandflash_partition[] = {
47 /* U-Boot Environment: Block 0 47 /* U-Boot Environment: Block 0
48 * UBL: Block 1 48 * UBL: Block 1
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index 0ed7fdb64efb..992c4c410185 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -153,34 +153,6 @@ static struct clk pll1_sysclk3 = {
153 .div_reg = PLLDIV3, 153 .div_reg = PLLDIV3,
154}; 154};
155 155
156static struct clk pll1_sysclk4 = {
157 .name = "pll1_sysclk4",
158 .parent = &pll1_clk,
159 .flags = CLK_PLL,
160 .div_reg = PLLDIV4,
161};
162
163static struct clk pll1_sysclk5 = {
164 .name = "pll1_sysclk5",
165 .parent = &pll1_clk,
166 .flags = CLK_PLL,
167 .div_reg = PLLDIV5,
168};
169
170static struct clk pll1_sysclk6 = {
171 .name = "pll0_sysclk6",
172 .parent = &pll0_clk,
173 .flags = CLK_PLL,
174 .div_reg = PLLDIV6,
175};
176
177static struct clk pll1_sysclk7 = {
178 .name = "pll1_sysclk7",
179 .parent = &pll1_clk,
180 .flags = CLK_PLL,
181 .div_reg = PLLDIV7,
182};
183
184static struct clk i2c0_clk = { 156static struct clk i2c0_clk = {
185 .name = "i2c0", 157 .name = "i2c0",
186 .parent = &pll0_aux_clk, 158 .parent = &pll0_aux_clk,
@@ -397,10 +369,6 @@ static struct clk_lookup da850_clks[] = {
397 CLK(NULL, "pll1_aux", &pll1_aux_clk), 369 CLK(NULL, "pll1_aux", &pll1_aux_clk),
398 CLK(NULL, "pll1_sysclk2", &pll1_sysclk2), 370 CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
399 CLK(NULL, "pll1_sysclk3", &pll1_sysclk3), 371 CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
400 CLK(NULL, "pll1_sysclk4", &pll1_sysclk4),
401 CLK(NULL, "pll1_sysclk5", &pll1_sysclk5),
402 CLK(NULL, "pll1_sysclk6", &pll1_sysclk6),
403 CLK(NULL, "pll1_sysclk7", &pll1_sysclk7),
404 CLK("i2c_davinci.1", NULL, &i2c0_clk), 372 CLK("i2c_davinci.1", NULL, &i2c0_clk),
405 CLK(NULL, "timer0", &timerp64_0_clk), 373 CLK(NULL, "timer0", &timerp64_0_clk),
406 CLK("watchdog", NULL, &timerp64_1_clk), 374 CLK("watchdog", NULL, &timerp64_1_clk),
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index dd1429ae6405..bda7aca04ca0 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -28,6 +28,7 @@
28#include <asm/mach/arch.h> 28#include <asm/mach/arch.h>
29#include <linux/irq.h> 29#include <linux/irq.h>
30#include <plat/time.h> 30#include <plat/time.h>
31#include <plat/ehci-orion.h>
31#include <plat/common.h> 32#include <plat/common.h>
32#include <plat/addr-map.h> 33#include <plat/addr-map.h>
33#include "common.h" 34#include "common.h"
@@ -71,7 +72,7 @@ void __init dove_map_io(void)
71 ****************************************************************************/ 72 ****************************************************************************/
72void __init dove_ehci0_init(void) 73void __init dove_ehci0_init(void)
73{ 74{
74 orion_ehci_init(DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0); 75 orion_ehci_init(DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0, EHCI_PHY_NA);
75} 76}
76 77
77/***************************************************************************** 78/*****************************************************************************
diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
index 24203f9a6796..b5c1dae8327f 100644
--- a/arch/arm/mach-ep93xx/core.c
+++ b/arch/arm/mach-ep93xx/core.c
@@ -817,23 +817,12 @@ void __init ep93xx_register_i2s(void)
817#define EP93XX_I2SCLKDIV_MASK (EP93XX_SYSCON_I2SCLKDIV_ORIDE | \ 817#define EP93XX_I2SCLKDIV_MASK (EP93XX_SYSCON_I2SCLKDIV_ORIDE | \
818 EP93XX_SYSCON_I2SCLKDIV_SPOL) 818 EP93XX_SYSCON_I2SCLKDIV_SPOL)
819 819
820int ep93xx_i2s_acquire(unsigned i2s_pins, unsigned i2s_config) 820int ep93xx_i2s_acquire(void)
821{ 821{
822 unsigned val; 822 unsigned val;
823 823
824 /* Sanity check */ 824 ep93xx_devcfg_set_clear(EP93XX_SYSCON_DEVCFG_I2SONAC97,
825 if (i2s_pins & ~EP93XX_SYSCON_DEVCFG_I2S_MASK) 825 EP93XX_SYSCON_DEVCFG_I2S_MASK);
826 return -EINVAL;
827 if (i2s_config & ~EP93XX_I2SCLKDIV_MASK)
828 return -EINVAL;
829
830 /* Must have only one of I2SONSSP/I2SONAC97 set */
831 if ((i2s_pins & EP93XX_SYSCON_DEVCFG_I2SONSSP) ==
832 (i2s_pins & EP93XX_SYSCON_DEVCFG_I2SONAC97))
833 return -EINVAL;
834
835 ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_I2S_MASK);
836 ep93xx_devcfg_set_bits(i2s_pins);
837 826
838 /* 827 /*
839 * This is potentially racy with the clock api for i2s_mclk, sclk and 828 * This is potentially racy with the clock api for i2s_mclk, sclk and
@@ -843,7 +832,7 @@ int ep93xx_i2s_acquire(unsigned i2s_pins, unsigned i2s_config)
843 */ 832 */
844 val = __raw_readl(EP93XX_SYSCON_I2SCLKDIV); 833 val = __raw_readl(EP93XX_SYSCON_I2SCLKDIV);
845 val &= ~EP93XX_I2SCLKDIV_MASK; 834 val &= ~EP93XX_I2SCLKDIV_MASK;
846 val |= i2s_config; 835 val |= EP93XX_SYSCON_I2SCLKDIV_ORIDE | EP93XX_SYSCON_I2SCLKDIV_SPOL;
847 ep93xx_syscon_swlocked_write(val, EP93XX_SYSCON_I2SCLKDIV); 836 ep93xx_syscon_swlocked_write(val, EP93XX_SYSCON_I2SCLKDIV);
848 837
849 return 0; 838 return 0;
diff --git a/arch/arm/mach-ep93xx/include/mach/platform.h b/arch/arm/mach-ep93xx/include/mach/platform.h
index d4c934931f9d..ad63d4be693f 100644
--- a/arch/arm/mach-ep93xx/include/mach/platform.h
+++ b/arch/arm/mach-ep93xx/include/mach/platform.h
@@ -59,7 +59,7 @@ void ep93xx_register_keypad(struct ep93xx_keypad_platform_data *data);
59int ep93xx_keypad_acquire_gpio(struct platform_device *pdev); 59int ep93xx_keypad_acquire_gpio(struct platform_device *pdev);
60void ep93xx_keypad_release_gpio(struct platform_device *pdev); 60void ep93xx_keypad_release_gpio(struct platform_device *pdev);
61void ep93xx_register_i2s(void); 61void ep93xx_register_i2s(void);
62int ep93xx_i2s_acquire(unsigned i2s_pins, unsigned i2s_config); 62int ep93xx_i2s_acquire(void);
63void ep93xx_i2s_release(void); 63void ep93xx_i2s_release(void);
64void ep93xx_register_ac97(void); 64void ep93xx_register_ac97(void);
65 65
diff --git a/arch/arm/mach-ep93xx/vision_ep9307.c b/arch/arm/mach-ep93xx/vision_ep9307.c
index 03dd4012043e..d67d0b4feb6f 100644
--- a/arch/arm/mach-ep93xx/vision_ep9307.c
+++ b/arch/arm/mach-ep93xx/vision_ep9307.c
@@ -32,7 +32,9 @@
32#include <mach/hardware.h> 32#include <mach/hardware.h>
33#include <mach/fb.h> 33#include <mach/fb.h>
34#include <mach/ep93xx_spi.h> 34#include <mach/ep93xx_spi.h>
35#include <mach/gpio-ep93xx.h>
35 36
37#include <asm/hardware/vic.h>
36#include <asm/mach-types.h> 38#include <asm/mach-types.h>
37#include <asm/mach/map.h> 39#include <asm/mach/map.h>
38#include <asm/mach/arch.h> 40#include <asm/mach/arch.h>
@@ -153,7 +155,6 @@ static struct i2c_board_info vision_i2c_info[] __initdata = {
153 }, { 155 }, {
154 I2C_BOARD_INFO("pca9539", 0x74), 156 I2C_BOARD_INFO("pca9539", 0x74),
155 .platform_data = &pca953x_74_gpio_data, 157 .platform_data = &pca953x_74_gpio_data,
156 .irq = gpio_to_irq(EP93XX_GPIO_LINE_F(7)),
157 }, { 158 }, {
158 I2C_BOARD_INFO("pca9539", 0x75), 159 I2C_BOARD_INFO("pca9539", 0x75),
159 .platform_data = &pca953x_75_gpio_data, 160 .platform_data = &pca953x_75_gpio_data,
@@ -348,6 +349,8 @@ static void __init vision_init_machine(void)
348 "pca9539:74")) 349 "pca9539:74"))
349 pr_warn("cannot request interrupt gpio for pca9539:74\n"); 350 pr_warn("cannot request interrupt gpio for pca9539:74\n");
350 351
352 vision_i2c_info[1].irq = gpio_to_irq(EP93XX_GPIO_LINE_F(7));
353
351 ep93xx_register_i2c(&vision_i2c_gpio_data, vision_i2c_info, 354 ep93xx_register_i2c(&vision_i2c_gpio_data, vision_i2c_info,
352 ARRAY_SIZE(vision_i2c_info)); 355 ARRAY_SIZE(vision_i2c_info));
353 ep93xx_register_spi(&vision_spi_master, vision_spi_board_info, 356 ep93xx_register_spi(&vision_spi_master, vision_spi_board_info,
@@ -359,6 +362,7 @@ MACHINE_START(VISION_EP9307, "Vision Engraving Systems EP9307")
359 .atag_offset = 0x100, 362 .atag_offset = 0x100,
360 .map_io = vision_map_io, 363 .map_io = vision_map_io,
361 .init_irq = ep93xx_init_irq, 364 .init_irq = ep93xx_init_irq,
365 .handle_irq = vic_handle_irq,
362 .timer = &ep93xx_timer, 366 .timer = &ep93xx_timer,
363 .init_machine = vision_init_machine, 367 .init_machine = vision_init_machine,
364 .restart = ep93xx_restart, 368 .restart = ep93xx_restart,
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 5d602f68a0e8..dfad6538b273 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -34,6 +34,7 @@ config CPU_EXYNOS4210
34 select ARM_CPU_SUSPEND if PM 34 select ARM_CPU_SUSPEND if PM
35 select S5P_PM if PM 35 select S5P_PM if PM
36 select S5P_SLEEP if PM 36 select S5P_SLEEP if PM
37 select PM_GENERIC_DOMAINS
37 help 38 help
38 Enable EXYNOS4210 CPU support 39 Enable EXYNOS4210 CPU support
39 40
@@ -74,11 +75,6 @@ config EXYNOS4_SETUP_FIMD0
74 help 75 help
75 Common setup code for FIMD0. 76 Common setup code for FIMD0.
76 77
77config EXYNOS4_DEV_PD
78 bool
79 help
80 Compile in platform device definitions for Power Domain
81
82config EXYNOS4_DEV_SYSMMU 78config EXYNOS4_DEV_SYSMMU
83 bool 79 bool
84 help 80 help
@@ -195,7 +191,6 @@ config MACH_SMDKV310
195 select EXYNOS4_DEV_AHCI 191 select EXYNOS4_DEV_AHCI
196 select SAMSUNG_DEV_KEYPAD 192 select SAMSUNG_DEV_KEYPAD
197 select EXYNOS4_DEV_DMA 193 select EXYNOS4_DEV_DMA
198 select EXYNOS4_DEV_PD
199 select SAMSUNG_DEV_PWM 194 select SAMSUNG_DEV_PWM
200 select EXYNOS4_DEV_USB_OHCI 195 select EXYNOS4_DEV_USB_OHCI
201 select EXYNOS4_DEV_SYSMMU 196 select EXYNOS4_DEV_SYSMMU
@@ -243,7 +238,6 @@ config MACH_UNIVERSAL_C210
243 select S5P_DEV_ONENAND 238 select S5P_DEV_ONENAND
244 select S5P_DEV_TV 239 select S5P_DEV_TV
245 select EXYNOS4_DEV_DMA 240 select EXYNOS4_DEV_DMA
246 select EXYNOS4_DEV_PD
247 select EXYNOS4_SETUP_FIMD0 241 select EXYNOS4_SETUP_FIMD0
248 select EXYNOS4_SETUP_I2C1 242 select EXYNOS4_SETUP_I2C1
249 select EXYNOS4_SETUP_I2C3 243 select EXYNOS4_SETUP_I2C3
@@ -277,7 +271,6 @@ config MACH_NURI
277 select S5P_DEV_USB_EHCI 271 select S5P_DEV_USB_EHCI
278 select S5P_SETUP_MIPIPHY 272 select S5P_SETUP_MIPIPHY
279 select EXYNOS4_DEV_DMA 273 select EXYNOS4_DEV_DMA
280 select EXYNOS4_DEV_PD
281 select EXYNOS4_SETUP_FIMC 274 select EXYNOS4_SETUP_FIMC
282 select EXYNOS4_SETUP_FIMD0 275 select EXYNOS4_SETUP_FIMD0
283 select EXYNOS4_SETUP_I2C1 276 select EXYNOS4_SETUP_I2C1
@@ -310,7 +303,6 @@ config MACH_ORIGEN
310 select SAMSUNG_DEV_BACKLIGHT 303 select SAMSUNG_DEV_BACKLIGHT
311 select SAMSUNG_DEV_PWM 304 select SAMSUNG_DEV_PWM
312 select EXYNOS4_DEV_DMA 305 select EXYNOS4_DEV_DMA
313 select EXYNOS4_DEV_PD
314 select EXYNOS4_DEV_USB_OHCI 306 select EXYNOS4_DEV_USB_OHCI
315 select EXYNOS4_SETUP_FIMD0 307 select EXYNOS4_SETUP_FIMD0
316 select EXYNOS4_SETUP_SDHCI 308 select EXYNOS4_SETUP_SDHCI
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 5fc202cdfdb6..d9191f9a7af8 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_CPU_EXYNOS4210) += clock-exynos4210.o
17obj-$(CONFIG_SOC_EXYNOS4212) += clock-exynos4212.o 17obj-$(CONFIG_SOC_EXYNOS4212) += clock-exynos4212.o
18 18
19obj-$(CONFIG_PM) += pm.o 19obj-$(CONFIG_PM) += pm.o
20obj-$(CONFIG_PM_GENERIC_DOMAINS) += pm_domains.o
20obj-$(CONFIG_CPU_IDLE) += cpuidle.o 21obj-$(CONFIG_CPU_IDLE) += cpuidle.o
21 22
22obj-$(CONFIG_ARCH_EXYNOS4) += pmu.o 23obj-$(CONFIG_ARCH_EXYNOS4) += pmu.o
@@ -45,7 +46,6 @@ obj-$(CONFIG_MACH_EXYNOS4_DT) += mach-exynos4-dt.o
45 46
46obj-$(CONFIG_ARCH_EXYNOS4) += dev-audio.o 47obj-$(CONFIG_ARCH_EXYNOS4) += dev-audio.o
47obj-$(CONFIG_EXYNOS4_DEV_AHCI) += dev-ahci.o 48obj-$(CONFIG_EXYNOS4_DEV_AHCI) += dev-ahci.o
48obj-$(CONFIG_EXYNOS4_DEV_PD) += dev-pd.o
49obj-$(CONFIG_EXYNOS4_DEV_SYSMMU) += dev-sysmmu.o 49obj-$(CONFIG_EXYNOS4_DEV_SYSMMU) += dev-sysmmu.o
50obj-$(CONFIG_EXYNOS4_DEV_DWMCI) += dev-dwmci.o 50obj-$(CONFIG_EXYNOS4_DEV_DWMCI) += dev-dwmci.o
51obj-$(CONFIG_EXYNOS4_DEV_DMA) += dma.o 51obj-$(CONFIG_EXYNOS4_DEV_DMA) += dma.o
diff --git a/arch/arm/mach-exynos/clock-exynos4210.c b/arch/arm/mach-exynos/clock-exynos4210.c
index a5823a7f249e..13312ccb2d93 100644
--- a/arch/arm/mach-exynos/clock-exynos4210.c
+++ b/arch/arm/mach-exynos/clock-exynos4210.c
@@ -32,6 +32,7 @@
32 32
33#include "common.h" 33#include "common.h"
34 34
35#ifdef CONFIG_PM_SLEEP
35static struct sleep_save exynos4210_clock_save[] = { 36static struct sleep_save exynos4210_clock_save[] = {
36 SAVE_ITEM(S5P_CLKSRC_IMAGE), 37 SAVE_ITEM(S5P_CLKSRC_IMAGE),
37 SAVE_ITEM(S5P_CLKSRC_LCD1), 38 SAVE_ITEM(S5P_CLKSRC_LCD1),
@@ -42,6 +43,7 @@ static struct sleep_save exynos4210_clock_save[] = {
42 SAVE_ITEM(S5P_CLKGATE_IP_LCD1), 43 SAVE_ITEM(S5P_CLKGATE_IP_LCD1),
43 SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4210), 44 SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4210),
44}; 45};
46#endif
45 47
46static struct clksrc_clk *sysclks[] = { 48static struct clksrc_clk *sysclks[] = {
47 /* nothing here yet */ 49 /* nothing here yet */
diff --git a/arch/arm/mach-exynos/clock-exynos4212.c b/arch/arm/mach-exynos/clock-exynos4212.c
index 26a668b0d101..48af28566fa1 100644
--- a/arch/arm/mach-exynos/clock-exynos4212.c
+++ b/arch/arm/mach-exynos/clock-exynos4212.c
@@ -32,12 +32,14 @@
32 32
33#include "common.h" 33#include "common.h"
34 34
35#ifdef CONFIG_PM_SLEEP
35static struct sleep_save exynos4212_clock_save[] = { 36static struct sleep_save exynos4212_clock_save[] = {
36 SAVE_ITEM(S5P_CLKSRC_IMAGE), 37 SAVE_ITEM(S5P_CLKSRC_IMAGE),
37 SAVE_ITEM(S5P_CLKDIV_IMAGE), 38 SAVE_ITEM(S5P_CLKDIV_IMAGE),
38 SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4212), 39 SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4212),
39 SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4212), 40 SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4212),
40}; 41};
42#endif
41 43
42static struct clk *clk_src_mpll_user_list[] = { 44static struct clk *clk_src_mpll_user_list[] = {
43 [0] = &clk_fin_mpll, 45 [0] = &clk_fin_mpll,
diff --git a/arch/arm/mach-exynos/clock.c b/arch/arm/mach-exynos/clock.c
index 5a8c42e90005..187287aa57ab 100644
--- a/arch/arm/mach-exynos/clock.c
+++ b/arch/arm/mach-exynos/clock.c
@@ -30,6 +30,7 @@
30 30
31#include "common.h" 31#include "common.h"
32 32
33#ifdef CONFIG_PM_SLEEP
33static struct sleep_save exynos4_clock_save[] = { 34static struct sleep_save exynos4_clock_save[] = {
34 SAVE_ITEM(S5P_CLKDIV_LEFTBUS), 35 SAVE_ITEM(S5P_CLKDIV_LEFTBUS),
35 SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS), 36 SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS),
@@ -93,6 +94,7 @@ static struct sleep_save exynos4_clock_save[] = {
93 SAVE_ITEM(S5P_CLKGATE_SCLKCPU), 94 SAVE_ITEM(S5P_CLKGATE_SCLKCPU),
94 SAVE_ITEM(S5P_CLKGATE_IP_CPU), 95 SAVE_ITEM(S5P_CLKGATE_IP_CPU),
95}; 96};
97#endif
96 98
97struct clk clk_sclk_hdmi27m = { 99struct clk clk_sclk_hdmi27m = {
98 .name = "sclk_hdmi27m", 100 .name = "sclk_hdmi27m",
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index c59e18871006..6de298c5d2d3 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -402,7 +402,7 @@ void __init exynos4_init_irq(void)
402 gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000; 402 gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
403 403
404 if (!of_have_populated_dt()) 404 if (!of_have_populated_dt())
405 gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset); 405 gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset, NULL);
406#ifdef CONFIG_OF 406#ifdef CONFIG_OF
407 else 407 else
408 of_irq_init(exynos4_dt_irq_match); 408 of_irq_init(exynos4_dt_irq_match);
diff --git a/arch/arm/mach-exynos/dev-pd.c b/arch/arm/mach-exynos/dev-pd.c
deleted file mode 100644
index 3273f25d6a75..000000000000
--- a/arch/arm/mach-exynos/dev-pd.c
+++ /dev/null
@@ -1,139 +0,0 @@
1/* linux/arch/arm/mach-exynos4/dev-pd.c
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS4 - Power Domain support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/io.h>
14#include <linux/kernel.h>
15#include <linux/platform_device.h>
16#include <linux/delay.h>
17
18#include <mach/regs-pmu.h>
19
20#include <plat/pd.h>
21
22static int exynos4_pd_enable(struct device *dev)
23{
24 struct samsung_pd_info *pdata = dev->platform_data;
25 u32 timeout;
26
27 __raw_writel(S5P_INT_LOCAL_PWR_EN, pdata->base);
28
29 /* Wait max 1ms */
30 timeout = 10;
31 while ((__raw_readl(pdata->base + 0x4) & S5P_INT_LOCAL_PWR_EN)
32 != S5P_INT_LOCAL_PWR_EN) {
33 if (timeout == 0) {
34 printk(KERN_ERR "Power domain %s enable failed.\n",
35 dev_name(dev));
36 return -ETIMEDOUT;
37 }
38 timeout--;
39 udelay(100);
40 }
41
42 return 0;
43}
44
45static int exynos4_pd_disable(struct device *dev)
46{
47 struct samsung_pd_info *pdata = dev->platform_data;
48 u32 timeout;
49
50 __raw_writel(0, pdata->base);
51
52 /* Wait max 1ms */
53 timeout = 10;
54 while (__raw_readl(pdata->base + 0x4) & S5P_INT_LOCAL_PWR_EN) {
55 if (timeout == 0) {
56 printk(KERN_ERR "Power domain %s disable failed.\n",
57 dev_name(dev));
58 return -ETIMEDOUT;
59 }
60 timeout--;
61 udelay(100);
62 }
63
64 return 0;
65}
66
67struct platform_device exynos4_device_pd[] = {
68 {
69 .name = "samsung-pd",
70 .id = 0,
71 .dev = {
72 .platform_data = &(struct samsung_pd_info) {
73 .enable = exynos4_pd_enable,
74 .disable = exynos4_pd_disable,
75 .base = S5P_PMU_MFC_CONF,
76 },
77 },
78 }, {
79 .name = "samsung-pd",
80 .id = 1,
81 .dev = {
82 .platform_data = &(struct samsung_pd_info) {
83 .enable = exynos4_pd_enable,
84 .disable = exynos4_pd_disable,
85 .base = S5P_PMU_G3D_CONF,
86 },
87 },
88 }, {
89 .name = "samsung-pd",
90 .id = 2,
91 .dev = {
92 .platform_data = &(struct samsung_pd_info) {
93 .enable = exynos4_pd_enable,
94 .disable = exynos4_pd_disable,
95 .base = S5P_PMU_LCD0_CONF,
96 },
97 },
98 }, {
99 .name = "samsung-pd",
100 .id = 3,
101 .dev = {
102 .platform_data = &(struct samsung_pd_info) {
103 .enable = exynos4_pd_enable,
104 .disable = exynos4_pd_disable,
105 .base = S5P_PMU_LCD1_CONF,
106 },
107 },
108 }, {
109 .name = "samsung-pd",
110 .id = 4,
111 .dev = {
112 .platform_data = &(struct samsung_pd_info) {
113 .enable = exynos4_pd_enable,
114 .disable = exynos4_pd_disable,
115 .base = S5P_PMU_TV_CONF,
116 },
117 },
118 }, {
119 .name = "samsung-pd",
120 .id = 5,
121 .dev = {
122 .platform_data = &(struct samsung_pd_info) {
123 .enable = exynos4_pd_enable,
124 .disable = exynos4_pd_disable,
125 .base = S5P_PMU_CAM_CONF,
126 },
127 },
128 }, {
129 .name = "samsung-pd",
130 .id = 6,
131 .dev = {
132 .platform_data = &(struct samsung_pd_info) {
133 .enable = exynos4_pd_enable,
134 .disable = exynos4_pd_disable,
135 .base = S5P_PMU_GPS_CONF,
136 },
137 },
138 },
139};
diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c
index da70e7e39937..dd1ad55524c9 100644
--- a/arch/arm/mach-exynos/hotplug.c
+++ b/arch/arm/mach-exynos/hotplug.c
@@ -16,6 +16,7 @@
16#include <linux/io.h> 16#include <linux/io.h>
17 17
18#include <asm/cacheflush.h> 18#include <asm/cacheflush.h>
19#include <asm/smp_plat.h>
19 20
20#include <mach/regs-pmu.h> 21#include <mach/regs-pmu.h>
21 22
diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c b/arch/arm/mach-exynos/mach-exynos4-dt.c
index 85fa02767d67..e6b02fdf1b09 100644
--- a/arch/arm/mach-exynos/mach-exynos4-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos4-dt.c
@@ -15,11 +15,13 @@
15#include <linux/serial_core.h> 15#include <linux/serial_core.h>
16 16
17#include <asm/mach/arch.h> 17#include <asm/mach/arch.h>
18#include <asm/hardware/gic.h>
18#include <mach/map.h> 19#include <mach/map.h>
19 20
20#include <plat/cpu.h> 21#include <plat/cpu.h>
21#include <plat/regs-serial.h> 22#include <plat/regs-serial.h>
22#include <plat/exynos4.h> 23
24#include "common.h"
23 25
24/* 26/*
25 * The following lookup table is used to override device names when devices 27 * The following lookup table is used to override device names when devices
@@ -60,7 +62,7 @@ static const struct of_dev_auxdata exynos4210_auxdata_lookup[] __initconst = {
60 62
61static void __init exynos4210_dt_map_io(void) 63static void __init exynos4210_dt_map_io(void)
62{ 64{
63 s5p_init_io(NULL, 0, S5P_VA_CHIPID); 65 exynos_init_io(NULL, 0);
64 s3c24xx_init_clocks(24000000); 66 s3c24xx_init_clocks(24000000);
65} 67}
66 68
@@ -79,7 +81,9 @@ DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened Device Tree)")
79 /* Maintainer: Thomas Abraham <thomas.abraham@linaro.org> */ 81 /* Maintainer: Thomas Abraham <thomas.abraham@linaro.org> */
80 .init_irq = exynos4_init_irq, 82 .init_irq = exynos4_init_irq,
81 .map_io = exynos4210_dt_map_io, 83 .map_io = exynos4210_dt_map_io,
84 .handle_irq = gic_handle_irq,
82 .init_machine = exynos4210_dt_machine_init, 85 .init_machine = exynos4210_dt_machine_init,
83 .timer = &exynos4_timer, 86 .timer = &exynos4_timer,
84 .dt_compat = exynos4210_dt_compat, 87 .dt_compat = exynos4210_dt_compat,
88 .restart = exynos4_restart,
85MACHINE_END 89MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c
index b895ec031105..aa37179d776c 100644
--- a/arch/arm/mach-exynos/mach-nuri.c
+++ b/arch/arm/mach-exynos/mach-nuri.c
@@ -220,14 +220,14 @@ static struct s3c_fb_pd_win nuri_fb_win0 = {
220 .lower_margin = 1, 220 .lower_margin = 1,
221 .hsync_len = 48, 221 .hsync_len = 48,
222 .vsync_len = 3, 222 .vsync_len = 3,
223 .xres = 1280, 223 .xres = 1024,
224 .yres = 800, 224 .yres = 600,
225 .refresh = 60, 225 .refresh = 60,
226 }, 226 },
227 .max_bpp = 24, 227 .max_bpp = 24,
228 .default_bpp = 16, 228 .default_bpp = 16,
229 .virtual_x = 1280, 229 .virtual_x = 1024,
230 .virtual_y = 800, 230 .virtual_y = 2 * 600,
231}; 231};
232 232
233static struct s3c_fb_platdata nuri_fb_pdata __initdata = { 233static struct s3c_fb_platdata nuri_fb_pdata __initdata = {
@@ -1263,9 +1263,6 @@ static struct platform_device *nuri_devices[] __initdata = {
1263 &s5p_device_mfc, 1263 &s5p_device_mfc,
1264 &s5p_device_mfc_l, 1264 &s5p_device_mfc_l,
1265 &s5p_device_mfc_r, 1265 &s5p_device_mfc_r,
1266 &exynos4_device_pd[PD_MFC],
1267 &exynos4_device_pd[PD_LCD0],
1268 &exynos4_device_pd[PD_CAM],
1269 &s5p_device_fimc_md, 1266 &s5p_device_fimc_md,
1270 1267
1271 /* NURI Devices */ 1268 /* NURI Devices */
@@ -1315,14 +1312,6 @@ static void __init nuri_machine_init(void)
1315 1312
1316 /* Last */ 1313 /* Last */
1317 platform_add_devices(nuri_devices, ARRAY_SIZE(nuri_devices)); 1314 platform_add_devices(nuri_devices, ARRAY_SIZE(nuri_devices));
1318 s5p_device_mfc.dev.parent = &exynos4_device_pd[PD_MFC].dev;
1319 s5p_device_fimd0.dev.parent = &exynos4_device_pd[PD_LCD0].dev;
1320
1321 s5p_device_fimc0.dev.parent = &exynos4_device_pd[PD_CAM].dev;
1322 s5p_device_fimc1.dev.parent = &exynos4_device_pd[PD_CAM].dev;
1323 s5p_device_fimc2.dev.parent = &exynos4_device_pd[PD_CAM].dev;
1324 s5p_device_fimc3.dev.parent = &exynos4_device_pd[PD_CAM].dev;
1325 s5p_device_mipi_csis0.dev.parent = &exynos4_device_pd[PD_CAM].dev;
1326} 1315}
1327 1316
1328MACHINE_START(NURI, "NURI") 1317MACHINE_START(NURI, "NURI")
diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c
index 0679b8ad2d1e..fa5c4a59b0aa 100644
--- a/arch/arm/mach-exynos/mach-origen.c
+++ b/arch/arm/mach-exynos/mach-origen.c
@@ -621,13 +621,6 @@ static struct platform_device *origen_devices[] __initdata = {
621 &s5p_device_mfc_r, 621 &s5p_device_mfc_r,
622 &s5p_device_mixer, 622 &s5p_device_mixer,
623 &exynos4_device_ohci, 623 &exynos4_device_ohci,
624 &exynos4_device_pd[PD_LCD0],
625 &exynos4_device_pd[PD_TV],
626 &exynos4_device_pd[PD_G3D],
627 &exynos4_device_pd[PD_LCD1],
628 &exynos4_device_pd[PD_CAM],
629 &exynos4_device_pd[PD_GPS],
630 &exynos4_device_pd[PD_MFC],
631 &origen_device_gpiokeys, 624 &origen_device_gpiokeys,
632 &origen_lcd_hv070wsa, 625 &origen_lcd_hv070wsa,
633}; 626};
@@ -695,13 +688,6 @@ static void __init origen_machine_init(void)
695 688
696 platform_add_devices(origen_devices, ARRAY_SIZE(origen_devices)); 689 platform_add_devices(origen_devices, ARRAY_SIZE(origen_devices));
697 690
698 s5p_device_fimd0.dev.parent = &exynos4_device_pd[PD_LCD0].dev;
699
700 s5p_device_hdmi.dev.parent = &exynos4_device_pd[PD_TV].dev;
701 s5p_device_mixer.dev.parent = &exynos4_device_pd[PD_TV].dev;
702
703 s5p_device_mfc.dev.parent = &exynos4_device_pd[PD_MFC].dev;
704
705 samsung_bl_set(&origen_bl_gpio_info, &origen_bl_data); 691 samsung_bl_set(&origen_bl_gpio_info, &origen_bl_data);
706} 692}
707 693
diff --git a/arch/arm/mach-exynos/mach-smdkv310.c b/arch/arm/mach-exynos/mach-smdkv310.c
index b2c5557f50e4..5258b8563676 100644
--- a/arch/arm/mach-exynos/mach-smdkv310.c
+++ b/arch/arm/mach-exynos/mach-smdkv310.c
@@ -277,13 +277,6 @@ static struct platform_device *smdkv310_devices[] __initdata = {
277 &s5p_device_mfc, 277 &s5p_device_mfc,
278 &s5p_device_mfc_l, 278 &s5p_device_mfc_l,
279 &s5p_device_mfc_r, 279 &s5p_device_mfc_r,
280 &exynos4_device_pd[PD_MFC],
281 &exynos4_device_pd[PD_G3D],
282 &exynos4_device_pd[PD_LCD0],
283 &exynos4_device_pd[PD_LCD1],
284 &exynos4_device_pd[PD_CAM],
285 &exynos4_device_pd[PD_TV],
286 &exynos4_device_pd[PD_GPS],
287 &exynos4_device_spdif, 280 &exynos4_device_spdif,
288 &exynos4_device_sysmmu, 281 &exynos4_device_sysmmu,
289 &samsung_asoc_dma, 282 &samsung_asoc_dma,
@@ -336,10 +329,6 @@ static void s5p_tv_setup(void)
336 WARN_ON(gpio_request_one(EXYNOS4_GPX3(7), GPIOF_IN, "hpd-plug")); 329 WARN_ON(gpio_request_one(EXYNOS4_GPX3(7), GPIOF_IN, "hpd-plug"));
337 s3c_gpio_cfgpin(EXYNOS4_GPX3(7), S3C_GPIO_SFN(0x3)); 330 s3c_gpio_cfgpin(EXYNOS4_GPX3(7), S3C_GPIO_SFN(0x3));
338 s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE); 331 s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE);
339
340 /* setup dependencies between TV devices */
341 s5p_device_hdmi.dev.parent = &exynos4_device_pd[PD_TV].dev;
342 s5p_device_mixer.dev.parent = &exynos4_device_pd[PD_TV].dev;
343} 332}
344 333
345static void __init smdkv310_map_io(void) 334static void __init smdkv310_map_io(void)
@@ -379,7 +368,6 @@ static void __init smdkv310_machine_init(void)
379 clk_xusbxti.rate = 24000000; 368 clk_xusbxti.rate = 24000000;
380 369
381 platform_add_devices(smdkv310_devices, ARRAY_SIZE(smdkv310_devices)); 370 platform_add_devices(smdkv310_devices, ARRAY_SIZE(smdkv310_devices));
382 s5p_device_mfc.dev.parent = &exynos4_device_pd[PD_MFC].dev;
383} 371}
384 372
385MACHINE_START(SMDKV310, "SMDKV310") 373MACHINE_START(SMDKV310, "SMDKV310")
diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c
index 37ac93e8d6d9..b2d495b31094 100644
--- a/arch/arm/mach-exynos/mach-universal_c210.c
+++ b/arch/arm/mach-exynos/mach-universal_c210.c
@@ -13,6 +13,7 @@
13#include <linux/i2c.h> 13#include <linux/i2c.h>
14#include <linux/gpio_keys.h> 14#include <linux/gpio_keys.h>
15#include <linux/gpio.h> 15#include <linux/gpio.h>
16#include <linux/interrupt.h>
16#include <linux/fb.h> 17#include <linux/fb.h>
17#include <linux/mfd/max8998.h> 18#include <linux/mfd/max8998.h>
18#include <linux/regulator/machine.h> 19#include <linux/regulator/machine.h>
@@ -595,6 +596,7 @@ static struct mxt_platform_data qt602240_platform_data = {
595 .threshold = 0x28, 596 .threshold = 0x28,
596 .voltage = 2800000, /* 2.8V */ 597 .voltage = 2800000, /* 2.8V */
597 .orient = MXT_DIAGONAL, 598 .orient = MXT_DIAGONAL,
599 .irqflags = IRQF_TRIGGER_FALLING,
598}; 600};
599 601
600static struct i2c_board_info i2c3_devs[] __initdata = { 602static struct i2c_board_info i2c3_devs[] __initdata = {
@@ -910,7 +912,7 @@ static struct s5p_fimc_isp_info universal_camera_sensors[] = {
910 .bus_type = FIMC_MIPI_CSI2, 912 .bus_type = FIMC_MIPI_CSI2,
911 .board_info = &m5mols_board_info, 913 .board_info = &m5mols_board_info,
912 .i2c_bus_num = 0, 914 .i2c_bus_num = 0,
913 .clk_frequency = 21600000UL, 915 .clk_frequency = 24000000UL,
914 .csi_data_align = 32, 916 .csi_data_align = 32,
915 }, 917 },
916}; 918};
@@ -969,7 +971,6 @@ static struct platform_device *universal_devices[] __initdata = {
969 &s3c_device_i2c5, 971 &s3c_device_i2c5,
970 &s5p_device_i2c_hdmiphy, 972 &s5p_device_i2c_hdmiphy,
971 &hdmi_fixed_voltage, 973 &hdmi_fixed_voltage,
972 &exynos4_device_pd[PD_TV],
973 &s5p_device_hdmi, 974 &s5p_device_hdmi,
974 &s5p_device_sdo, 975 &s5p_device_sdo,
975 &s5p_device_mixer, 976 &s5p_device_mixer,
@@ -982,9 +983,6 @@ static struct platform_device *universal_devices[] __initdata = {
982 &s5p_device_mfc, 983 &s5p_device_mfc,
983 &s5p_device_mfc_l, 984 &s5p_device_mfc_l,
984 &s5p_device_mfc_r, 985 &s5p_device_mfc_r,
985 &exynos4_device_pd[PD_MFC],
986 &exynos4_device_pd[PD_LCD0],
987 &exynos4_device_pd[PD_CAM],
988 &cam_i_core_fixed_reg_dev, 986 &cam_i_core_fixed_reg_dev,
989 &cam_s_if_fixed_reg_dev, 987 &cam_s_if_fixed_reg_dev,
990 &s5p_device_fimc_md, 988 &s5p_device_fimc_md,
@@ -1003,10 +1001,6 @@ void s5p_tv_setup(void)
1003 gpio_request_one(EXYNOS4_GPX3(7), GPIOF_IN, "hpd-plug"); 1001 gpio_request_one(EXYNOS4_GPX3(7), GPIOF_IN, "hpd-plug");
1004 s3c_gpio_cfgpin(EXYNOS4_GPX3(7), S3C_GPIO_SFN(0x3)); 1002 s3c_gpio_cfgpin(EXYNOS4_GPX3(7), S3C_GPIO_SFN(0x3));
1005 s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE); 1003 s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE);
1006
1007 /* setup dependencies between TV devices */
1008 s5p_device_hdmi.dev.parent = &exynos4_device_pd[PD_TV].dev;
1009 s5p_device_mixer.dev.parent = &exynos4_device_pd[PD_TV].dev;
1010} 1004}
1011 1005
1012static void __init universal_reserve(void) 1006static void __init universal_reserve(void)
@@ -1040,15 +1034,6 @@ static void __init universal_machine_init(void)
1040 1034
1041 /* Last */ 1035 /* Last */
1042 platform_add_devices(universal_devices, ARRAY_SIZE(universal_devices)); 1036 platform_add_devices(universal_devices, ARRAY_SIZE(universal_devices));
1043
1044 s5p_device_mfc.dev.parent = &exynos4_device_pd[PD_MFC].dev;
1045 s5p_device_fimd0.dev.parent = &exynos4_device_pd[PD_LCD0].dev;
1046
1047 s5p_device_fimc0.dev.parent = &exynos4_device_pd[PD_CAM].dev;
1048 s5p_device_fimc1.dev.parent = &exynos4_device_pd[PD_CAM].dev;
1049 s5p_device_fimc2.dev.parent = &exynos4_device_pd[PD_CAM].dev;
1050 s5p_device_fimc3.dev.parent = &exynos4_device_pd[PD_CAM].dev;
1051 s5p_device_mipi_csis0.dev.parent = &exynos4_device_pd[PD_CAM].dev;
1052} 1037}
1053 1038
1054MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210") 1039MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 683aec786b78..0f2035a1eb6e 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -23,6 +23,7 @@
23 23
24#include <asm/cacheflush.h> 24#include <asm/cacheflush.h>
25#include <asm/hardware/gic.h> 25#include <asm/hardware/gic.h>
26#include <asm/smp_plat.h>
26#include <asm/smp_scu.h> 27#include <asm/smp_scu.h>
27 28
28#include <mach/hardware.h> 29#include <mach/hardware.h>
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index a4f61a43c7ba..e19013051772 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -206,7 +206,7 @@ static void exynos4_pm_prepare(void)
206 206
207} 207}
208 208
209static int exynos4_pm_add(struct device *dev) 209static int exynos4_pm_add(struct device *dev, struct subsys_interface *sif)
210{ 210{
211 pm_cpu_prep = exynos4_pm_prepare; 211 pm_cpu_prep = exynos4_pm_prepare;
212 pm_cpu_sleep = exynos4_cpu_suspend; 212 pm_cpu_sleep = exynos4_cpu_suspend;
@@ -384,7 +384,9 @@ static void exynos4_pm_resume(void)
384 384
385 exynos4_restore_pll(); 385 exynos4_restore_pll();
386 386
387#ifdef CONFIG_SMP
387 scu_enable(S5P_VA_SCU); 388 scu_enable(S5P_VA_SCU);
389#endif
388 390
389#ifdef CONFIG_CACHE_L2X0 391#ifdef CONFIG_CACHE_L2X0
390 s3c_pm_do_restore_core(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save)); 392 s3c_pm_do_restore_core(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save));
diff --git a/arch/arm/mach-exynos/pm_domains.c b/arch/arm/mach-exynos/pm_domains.c
new file mode 100644
index 000000000000..0b04af2b13cc
--- /dev/null
+++ b/arch/arm/mach-exynos/pm_domains.c
@@ -0,0 +1,195 @@
1/*
2 * Exynos Generic power domain support.
3 *
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Implementation of Exynos specific power domain control which is used in
8 * conjunction with runtime-pm. Support for both device-tree and non-device-tree
9 * based power domain support is included.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14*/
15
16#include <linux/io.h>
17#include <linux/err.h>
18#include <linux/slab.h>
19#include <linux/pm_domain.h>
20#include <linux/delay.h>
21#include <linux/of_address.h>
22
23#include <mach/regs-pmu.h>
24#include <plat/devs.h>
25
26/*
27 * Exynos specific wrapper around the generic power domain
28 */
29struct exynos_pm_domain {
30 void __iomem *base;
31 char const *name;
32 bool is_off;
33 struct generic_pm_domain pd;
34};
35
36static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on)
37{
38 struct exynos_pm_domain *pd;
39 void __iomem *base;
40 u32 timeout, pwr;
41 char *op;
42
43 pd = container_of(domain, struct exynos_pm_domain, pd);
44 base = pd->base;
45
46 pwr = power_on ? S5P_INT_LOCAL_PWR_EN : 0;
47 __raw_writel(pwr, base);
48
49 /* Wait max 1ms */
50 timeout = 10;
51
52 while ((__raw_readl(base + 0x4) & S5P_INT_LOCAL_PWR_EN) != pwr) {
53 if (!timeout) {
54 op = (power_on) ? "enable" : "disable";
55 pr_err("Power domain %s %s failed\n", domain->name, op);
56 return -ETIMEDOUT;
57 }
58 timeout--;
59 cpu_relax();
60 usleep_range(80, 100);
61 }
62 return 0;
63}
64
65static int exynos_pd_power_on(struct generic_pm_domain *domain)
66{
67 return exynos_pd_power(domain, true);
68}
69
70static int exynos_pd_power_off(struct generic_pm_domain *domain)
71{
72 return exynos_pd_power(domain, false);
73}
74
75#define EXYNOS_GPD(PD, BASE, NAME) \
76static struct exynos_pm_domain PD = { \
77 .base = (void __iomem *)BASE, \
78 .name = NAME, \
79 .pd = { \
80 .power_off = exynos_pd_power_off, \
81 .power_on = exynos_pd_power_on, \
82 }, \
83}
84
85#ifdef CONFIG_OF
86static __init int exynos_pm_dt_parse_domains(void)
87{
88 struct device_node *np;
89
90 for_each_compatible_node(np, NULL, "samsung,exynos4210-pd") {
91 struct exynos_pm_domain *pd;
92
93 pd = kzalloc(sizeof(*pd), GFP_KERNEL);
94 if (!pd) {
95 pr_err("%s: failed to allocate memory for domain\n",
96 __func__);
97 return -ENOMEM;
98 }
99
100 if (of_get_property(np, "samsung,exynos4210-pd-off", NULL))
101 pd->is_off = true;
102 pd->name = np->name;
103 pd->base = of_iomap(np, 0);
104 pd->pd.power_off = exynos_pd_power_off;
105 pd->pd.power_on = exynos_pd_power_on;
106 pd->pd.of_node = np;
107 pm_genpd_init(&pd->pd, NULL, false);
108 }
109 return 0;
110}
111#else
112static __init int exynos_pm_dt_parse_domains(void)
113{
114 return 0;
115}
116#endif /* CONFIG_OF */
117
118static __init void exynos_pm_add_dev_to_genpd(struct platform_device *pdev,
119 struct exynos_pm_domain *pd)
120{
121 if (pdev->dev.bus) {
122 if (pm_genpd_add_device(&pd->pd, &pdev->dev))
123 pr_info("%s: error in adding %s device to %s power"
124 "domain\n", __func__, dev_name(&pdev->dev),
125 pd->name);
126 }
127}
128
129EXYNOS_GPD(exynos4_pd_mfc, S5P_PMU_MFC_CONF, "pd-mfc");
130EXYNOS_GPD(exynos4_pd_g3d, S5P_PMU_G3D_CONF, "pd-g3d");
131EXYNOS_GPD(exynos4_pd_lcd0, S5P_PMU_LCD0_CONF, "pd-lcd0");
132EXYNOS_GPD(exynos4_pd_lcd1, S5P_PMU_LCD1_CONF, "pd-lcd1");
133EXYNOS_GPD(exynos4_pd_tv, S5P_PMU_TV_CONF, "pd-tv");
134EXYNOS_GPD(exynos4_pd_cam, S5P_PMU_CAM_CONF, "pd-cam");
135EXYNOS_GPD(exynos4_pd_gps, S5P_PMU_GPS_CONF, "pd-gps");
136
137static struct exynos_pm_domain *exynos4_pm_domains[] = {
138 &exynos4_pd_mfc,
139 &exynos4_pd_g3d,
140 &exynos4_pd_lcd0,
141 &exynos4_pd_lcd1,
142 &exynos4_pd_tv,
143 &exynos4_pd_cam,
144 &exynos4_pd_gps,
145};
146
147static __init int exynos4_pm_init_power_domain(void)
148{
149 int idx;
150
151 if (of_have_populated_dt())
152 return exynos_pm_dt_parse_domains();
153
154 for (idx = 0; idx < ARRAY_SIZE(exynos4_pm_domains); idx++)
155 pm_genpd_init(&exynos4_pm_domains[idx]->pd, NULL,
156 exynos4_pm_domains[idx]->is_off);
157
158#ifdef CONFIG_S5P_DEV_FIMD0
159 exynos_pm_add_dev_to_genpd(&s5p_device_fimd0, &exynos4_pd_lcd0);
160#endif
161#ifdef CONFIG_S5P_DEV_TV
162 exynos_pm_add_dev_to_genpd(&s5p_device_hdmi, &exynos4_pd_tv);
163 exynos_pm_add_dev_to_genpd(&s5p_device_mixer, &exynos4_pd_tv);
164#endif
165#ifdef CONFIG_S5P_DEV_MFC
166 exynos_pm_add_dev_to_genpd(&s5p_device_mfc, &exynos4_pd_mfc);
167#endif
168#ifdef CONFIG_S5P_DEV_FIMC0
169 exynos_pm_add_dev_to_genpd(&s5p_device_fimc0, &exynos4_pd_cam);
170#endif
171#ifdef CONFIG_S5P_DEV_FIMC1
172 exynos_pm_add_dev_to_genpd(&s5p_device_fimc1, &exynos4_pd_cam);
173#endif
174#ifdef CONFIG_S5P_DEV_FIMC2
175 exynos_pm_add_dev_to_genpd(&s5p_device_fimc2, &exynos4_pd_cam);
176#endif
177#ifdef CONFIG_S5P_DEV_FIMC3
178 exynos_pm_add_dev_to_genpd(&s5p_device_fimc3, &exynos4_pd_cam);
179#endif
180#ifdef CONFIG_S5P_DEV_CSIS0
181 exynos_pm_add_dev_to_genpd(&s5p_device_mipi_csis0, &exynos4_pd_cam);
182#endif
183#ifdef CONFIG_S5P_DEV_CSIS1
184 exynos_pm_add_dev_to_genpd(&s5p_device_mipi_csis1, &exynos4_pd_cam);
185#endif
186 return 0;
187}
188arch_initcall(exynos4_pm_init_power_domain);
189
190static __init int exynos_pm_late_initcall(void)
191{
192 pm_genpd_poweroff_unused();
193 return 0;
194}
195late_initcall(exynos_pm_late_initcall);
diff --git a/arch/arm/mach-highbank/highbank.c b/arch/arm/mach-highbank/highbank.c
index 7afbe1e55beb..8394d512a402 100644
--- a/arch/arm/mach-highbank/highbank.c
+++ b/arch/arm/mach-highbank/highbank.c
@@ -25,6 +25,7 @@
25#include <linux/smp.h> 25#include <linux/smp.h>
26 26
27#include <asm/cacheflush.h> 27#include <asm/cacheflush.h>
28#include <asm/smp_plat.h>
28#include <asm/smp_scu.h> 29#include <asm/smp_scu.h>
29#include <asm/hardware/arm_timer.h> 30#include <asm/hardware/arm_timer.h>
30#include <asm/hardware/timer-sp.h> 31#include <asm/hardware/timer-sp.h>
@@ -72,9 +73,7 @@ static void __init highbank_map_io(void)
72 73
73void highbank_set_cpu_jump(int cpu, void *jump_addr) 74void highbank_set_cpu_jump(int cpu, void *jump_addr)
74{ 75{
75#ifdef CONFIG_SMP
76 cpu = cpu_logical_map(cpu); 76 cpu = cpu_logical_map(cpu);
77#endif
78 writel(virt_to_phys(jump_addr), HB_JUMP_TABLE_VIRT(cpu)); 77 writel(virt_to_phys(jump_addr), HB_JUMP_TABLE_VIRT(cpu));
79 __cpuc_flush_dcache_area(HB_JUMP_TABLE_VIRT(cpu), 16); 78 __cpuc_flush_dcache_area(HB_JUMP_TABLE_VIRT(cpu), 16);
80 outer_clean_range(HB_JUMP_TABLE_PHYS(cpu), 79 outer_clean_range(HB_JUMP_TABLE_PHYS(cpu),
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 09f357bcecde..3919fba52ac8 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -46,7 +46,6 @@ config SOC_IMX21
46 bool 46 bool
47 select MACH_MX21 47 select MACH_MX21
48 select CPU_ARM926T 48 select CPU_ARM926T
49 select ARCH_MXC_AUDMUX_V1
50 select IMX_HAVE_DMA_V1 49 select IMX_HAVE_DMA_V1
51 select IMX_HAVE_IOMUX_V1 50 select IMX_HAVE_IOMUX_V1
52 select MXC_AVIC 51 select MXC_AVIC
@@ -55,7 +54,6 @@ config SOC_IMX25
55 bool 54 bool
56 select ARCH_MX25 55 select ARCH_MX25
57 select CPU_ARM926T 56 select CPU_ARM926T
58 select ARCH_MXC_AUDMUX_V2
59 select ARCH_MXC_IOMUX_V3 57 select ARCH_MXC_IOMUX_V3
60 select MXC_AVIC 58 select MXC_AVIC
61 59
@@ -63,7 +61,6 @@ config SOC_IMX27
63 bool 61 bool
64 select MACH_MX27 62 select MACH_MX27
65 select CPU_ARM926T 63 select CPU_ARM926T
66 select ARCH_MXC_AUDMUX_V1
67 select IMX_HAVE_DMA_V1 64 select IMX_HAVE_DMA_V1
68 select IMX_HAVE_IOMUX_V1 65 select IMX_HAVE_IOMUX_V1
69 select MXC_AVIC 66 select MXC_AVIC
@@ -72,7 +69,6 @@ config SOC_IMX31
72 bool 69 bool
73 select CPU_V6 70 select CPU_V6
74 select IMX_HAVE_PLATFORM_MXC_RNGA 71 select IMX_HAVE_PLATFORM_MXC_RNGA
75 select ARCH_MXC_AUDMUX_V2
76 select MXC_AVIC 72 select MXC_AVIC
77 select SMP_ON_UP if SMP 73 select SMP_ON_UP if SMP
78 74
@@ -80,17 +76,14 @@ config SOC_IMX35
80 bool 76 bool
81 select CPU_V6 77 select CPU_V6
82 select ARCH_MXC_IOMUX_V3 78 select ARCH_MXC_IOMUX_V3
83 select ARCH_MXC_AUDMUX_V2
84 select HAVE_EPIT 79 select HAVE_EPIT
85 select MXC_AVIC 80 select MXC_AVIC
86 select SMP_ON_UP if SMP 81 select SMP_ON_UP if SMP
87 82
88config SOC_IMX5 83config SOC_IMX5
89 select CPU_V7 84 select CPU_V7
90 select ARM_L1_CACHE_SHIFT_6
91 select MXC_TZIC 85 select MXC_TZIC
92 select ARCH_MXC_IOMUX_V3 86 select ARCH_MXC_IOMUX_V3
93 select ARCH_MXC_AUDMUX_V2
94 select ARCH_HAS_CPUFREQ 87 select ARCH_HAS_CPUFREQ
95 select ARCH_MX5 88 select ARCH_MX5
96 bool 89 bool
diff --git a/arch/arm/mach-imx/clock-imx6q.c b/arch/arm/mach-imx/clock-imx6q.c
index 9273c2a24b54..2d88f8b9a454 100644
--- a/arch/arm/mach-imx/clock-imx6q.c
+++ b/arch/arm/mach-imx/clock-imx6q.c
@@ -814,6 +814,16 @@ DEF_PFD(pll3_pfd_540m, PFD_480, PFD1, &pll3_usb_otg);
814DEF_PFD(pll3_pfd_508m, PFD_480, PFD2, &pll3_usb_otg); 814DEF_PFD(pll3_pfd_508m, PFD_480, PFD2, &pll3_usb_otg);
815DEF_PFD(pll3_pfd_454m, PFD_480, PFD3, &pll3_usb_otg); 815DEF_PFD(pll3_pfd_454m, PFD_480, PFD3, &pll3_usb_otg);
816 816
817static unsigned long twd_clk_get_rate(struct clk *clk)
818{
819 return clk_get_rate(clk->parent) / 2;
820}
821
822static struct clk twd_clk = {
823 .parent = &arm_clk,
824 .get_rate = twd_clk_get_rate,
825};
826
817static unsigned long pll2_200m_get_rate(struct clk *clk) 827static unsigned long pll2_200m_get_rate(struct clk *clk)
818{ 828{
819 return clk_get_rate(clk->parent) / 2; 829 return clk_get_rate(clk->parent) / 2;
@@ -1894,6 +1904,7 @@ static struct clk_lookup lookups[] = {
1894 _REGISTER_CLOCK("20ec000.sdma", NULL, sdma_clk), 1904 _REGISTER_CLOCK("20ec000.sdma", NULL, sdma_clk),
1895 _REGISTER_CLOCK("20bc000.wdog", NULL, dummy_clk), 1905 _REGISTER_CLOCK("20bc000.wdog", NULL, dummy_clk),
1896 _REGISTER_CLOCK("20c0000.wdog", NULL, dummy_clk), 1906 _REGISTER_CLOCK("20c0000.wdog", NULL, dummy_clk),
1907 _REGISTER_CLOCK("smp_twd", NULL, twd_clk),
1897 _REGISTER_CLOCK(NULL, "ckih", ckih_clk), 1908 _REGISTER_CLOCK(NULL, "ckih", ckih_clk),
1898 _REGISTER_CLOCK(NULL, "ckil_clk", ckil_clk), 1909 _REGISTER_CLOCK(NULL, "ckil_clk", ckil_clk),
1899 _REGISTER_CLOCK(NULL, "aips_tz1_clk", aips_tz1_clk), 1910 _REGISTER_CLOCK(NULL, "aips_tz1_clk", aips_tz1_clk),
diff --git a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
index 5db3e1463af7..5f2f91d1798b 100644
--- a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
@@ -32,7 +32,6 @@
32#include <mach/common.h> 32#include <mach/common.h>
33#include <mach/iomux-mx27.h> 33#include <mach/iomux-mx27.h>
34#include <mach/hardware.h> 34#include <mach/hardware.h>
35#include <mach/audmux.h>
36 35
37#include "devices-imx27.h" 36#include "devices-imx27.h"
38 37
@@ -306,25 +305,6 @@ void __init eukrea_mbimx27_baseboard_init(void)
306 mxc_gpio_setup_multiple_pins(eukrea_mbimx27_pins, 305 mxc_gpio_setup_multiple_pins(eukrea_mbimx27_pins,
307 ARRAY_SIZE(eukrea_mbimx27_pins), "MBIMX27"); 306 ARRAY_SIZE(eukrea_mbimx27_pins), "MBIMX27");
308 307
309#if defined(CONFIG_SND_SOC_EUKREA_TLV320) \
310 || defined(CONFIG_SND_SOC_EUKREA_TLV320_MODULE)
311 /* SSI unit master I2S codec connected to SSI_PINS_4*/
312 mxc_audmux_v1_configure_port(MX27_AUDMUX_HPCR1_SSI0,
313 MXC_AUDMUX_V1_PCR_SYN |
314 MXC_AUDMUX_V1_PCR_TFSDIR |
315 MXC_AUDMUX_V1_PCR_TCLKDIR |
316 MXC_AUDMUX_V1_PCR_RFSDIR |
317 MXC_AUDMUX_V1_PCR_RCLKDIR |
318 MXC_AUDMUX_V1_PCR_TFCSEL(MX27_AUDMUX_HPCR3_SSI_PINS_4) |
319 MXC_AUDMUX_V1_PCR_RFCSEL(MX27_AUDMUX_HPCR3_SSI_PINS_4) |
320 MXC_AUDMUX_V1_PCR_RXDSEL(MX27_AUDMUX_HPCR3_SSI_PINS_4)
321 );
322 mxc_audmux_v1_configure_port(MX27_AUDMUX_HPCR3_SSI_PINS_4,
323 MXC_AUDMUX_V1_PCR_SYN |
324 MXC_AUDMUX_V1_PCR_RXDSEL(MX27_AUDMUX_HPCR1_SSI0)
325 );
326#endif
327
328 imx27_add_imx_uart1(&uart_pdata); 308 imx27_add_imx_uart1(&uart_pdata);
329 imx27_add_imx_uart2(&uart_pdata); 309 imx27_add_imx_uart2(&uart_pdata);
330#if !defined(MACH_EUKREA_CPUIMX27_USEUART4) 310#if !defined(MACH_EUKREA_CPUIMX27_USEUART4)
diff --git a/arch/arm/mach-imx/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd-baseboard.c
index d817fc80b986..aaa592fdb9ce 100644
--- a/arch/arm/mach-imx/eukrea_mbimxsd-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimxsd-baseboard.c
@@ -37,7 +37,6 @@
37#include <mach/hardware.h> 37#include <mach/hardware.h>
38#include <mach/common.h> 38#include <mach/common.h>
39#include <mach/iomux-mx51.h> 39#include <mach/iomux-mx51.h>
40#include <mach/audmux.h>
41 40
42#include "devices-imx51.h" 41#include "devices-imx51.h"
43 42
diff --git a/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c
index 66e8726253fa..2cf603e11c4f 100644
--- a/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c
@@ -31,7 +31,6 @@
31#include <asm/mach-types.h> 31#include <asm/mach-types.h>
32#include <asm/mach/arch.h> 32#include <asm/mach/arch.h>
33#include <mach/mx25.h> 33#include <mach/mx25.h>
34#include <mach/audmux.h>
35 34
36#include "devices-imx25.h" 35#include "devices-imx25.h"
37 36
@@ -241,22 +240,6 @@ void __init eukrea_mbimxsd25_baseboard_init(void)
241 ARRAY_SIZE(eukrea_mbimxsd_pads))) 240 ARRAY_SIZE(eukrea_mbimxsd_pads)))
242 printk(KERN_ERR "error setting mbimxsd pads !\n"); 241 printk(KERN_ERR "error setting mbimxsd pads !\n");
243 242
244#if defined(CONFIG_SND_SOC_EUKREA_TLV320)
245 /* SSI unit master I2S codec connected to SSI_AUD5*/
246 mxc_audmux_v2_configure_port(0,
247 MXC_AUDMUX_V2_PTCR_SYN |
248 MXC_AUDMUX_V2_PTCR_TFSDIR |
249 MXC_AUDMUX_V2_PTCR_TFSEL(4) |
250 MXC_AUDMUX_V2_PTCR_TCLKDIR |
251 MXC_AUDMUX_V2_PTCR_TCSEL(4),
252 MXC_AUDMUX_V2_PDCR_RXDSEL(4)
253 );
254 mxc_audmux_v2_configure_port(4,
255 MXC_AUDMUX_V2_PTCR_SYN,
256 MXC_AUDMUX_V2_PDCR_RXDSEL(0)
257 );
258#endif
259
260 imx25_add_imx_uart1(&uart_pdata); 243 imx25_add_imx_uart1(&uart_pdata);
261 imx25_add_imx_fb(&eukrea_mximxsd_fb_pdata); 244 imx25_add_imx_fb(&eukrea_mximxsd_fb_pdata);
262 imx25_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata); 245 imx25_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata);
diff --git a/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c
index 0f0af02b3182..fd8bf8a425a7 100644
--- a/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c
@@ -38,7 +38,6 @@
38#include <mach/hardware.h> 38#include <mach/hardware.h>
39#include <mach/common.h> 39#include <mach/common.h>
40#include <mach/iomux-mx35.h> 40#include <mach/iomux-mx35.h>
41#include <mach/audmux.h>
42 41
43#include "devices-imx35.h" 42#include "devices-imx35.h"
44 43
@@ -252,22 +251,6 @@ void __init eukrea_mbimxsd35_baseboard_init(void)
252 ARRAY_SIZE(eukrea_mbimxsd_pads))) 251 ARRAY_SIZE(eukrea_mbimxsd_pads)))
253 printk(KERN_ERR "error setting mbimxsd pads !\n"); 252 printk(KERN_ERR "error setting mbimxsd pads !\n");
254 253
255#if defined(CONFIG_SND_SOC_EUKREA_TLV320)
256 /* SSI unit master I2S codec connected to SSI_AUD4 */
257 mxc_audmux_v2_configure_port(0,
258 MXC_AUDMUX_V2_PTCR_SYN |
259 MXC_AUDMUX_V2_PTCR_TFSDIR |
260 MXC_AUDMUX_V2_PTCR_TFSEL(3) |
261 MXC_AUDMUX_V2_PTCR_TCLKDIR |
262 MXC_AUDMUX_V2_PTCR_TCSEL(3),
263 MXC_AUDMUX_V2_PDCR_RXDSEL(3)
264 );
265 mxc_audmux_v2_configure_port(3,
266 MXC_AUDMUX_V2_PTCR_SYN,
267 MXC_AUDMUX_V2_PDCR_RXDSEL(0)
268 );
269#endif
270
271 imx35_add_imx_uart1(&uart_pdata); 254 imx35_add_imx_uart1(&uart_pdata);
272 imx35_add_ipu_core(&mx3_ipu_data); 255 imx35_add_ipu_core(&mx3_ipu_data);
273 imx35_add_mx3_sdc_fb(&mx3fb_pdata); 256 imx35_add_mx3_sdc_fb(&mx3fb_pdata);
diff --git a/arch/arm/mach-imx/imx51-dt.c b/arch/arm/mach-imx/imx51-dt.c
index e6bad17b908c..1e03ef42faa0 100644
--- a/arch/arm/mach-imx/imx51-dt.c
+++ b/arch/arm/mach-imx/imx51-dt.c
@@ -47,7 +47,7 @@ static const struct of_dev_auxdata imx51_auxdata_lookup[] __initconst = {
47static int __init imx51_tzic_add_irq_domain(struct device_node *np, 47static int __init imx51_tzic_add_irq_domain(struct device_node *np,
48 struct device_node *interrupt_parent) 48 struct device_node *interrupt_parent)
49{ 49{
50 irq_domain_add_simple(np, 0); 50 irq_domain_add_legacy(np, 128, 0, 0, &irq_domain_simple_ops, NULL);
51 return 0; 51 return 0;
52} 52}
53 53
@@ -57,7 +57,7 @@ static int __init imx51_gpio_add_irq_domain(struct device_node *np,
57 static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS; 57 static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS;
58 58
59 gpio_irq_base -= 32; 59 gpio_irq_base -= 32;
60 irq_domain_add_simple(np, gpio_irq_base); 60 irq_domain_add_legacy(np, 32, gpio_irq_base, 0, &irq_domain_simple_ops, NULL);
61 61
62 return 0; 62 return 0;
63} 63}
diff --git a/arch/arm/mach-imx/imx53-dt.c b/arch/arm/mach-imx/imx53-dt.c
index 05ebb3e68679..fd5be0f20fbb 100644
--- a/arch/arm/mach-imx/imx53-dt.c
+++ b/arch/arm/mach-imx/imx53-dt.c
@@ -51,7 +51,7 @@ static const struct of_dev_auxdata imx53_auxdata_lookup[] __initconst = {
51static int __init imx53_tzic_add_irq_domain(struct device_node *np, 51static int __init imx53_tzic_add_irq_domain(struct device_node *np,
52 struct device_node *interrupt_parent) 52 struct device_node *interrupt_parent)
53{ 53{
54 irq_domain_add_simple(np, 0); 54 irq_domain_add_legacy(np, 128, 0, 0, &irq_domain_simple_ops, NULL);
55 return 0; 55 return 0;
56} 56}
57 57
@@ -61,7 +61,7 @@ static int __init imx53_gpio_add_irq_domain(struct device_node *np,
61 static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS; 61 static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS;
62 62
63 gpio_irq_base -= 32; 63 gpio_irq_base -= 32;
64 irq_domain_add_simple(np, gpio_irq_base); 64 irq_domain_add_legacy(np, 32, gpio_irq_base, 0, &irq_domain_simple_ops, NULL);
65 65
66 return 0; 66 return 0;
67} 67}
diff --git a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
index c2766ae02b4f..428459fbca4b 100644
--- a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
+++ b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
@@ -263,6 +263,7 @@ static void __init visstrim_m10_board_init(void)
263 imx27_add_fec(NULL); 263 imx27_add_fec(NULL);
264 imx_add_gpio_keys(&visstrim_gpio_keys_platform_data); 264 imx_add_gpio_keys(&visstrim_gpio_keys_platform_data);
265 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); 265 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
266 imx_add_platform_device("mx27vis", 0, NULL, 0, NULL, 0);
266} 267}
267 268
268static void __init visstrim_m10_timer_init(void) 269static void __init visstrim_m10_timer_init(void)
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index c25728106917..6075d4d62dd6 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -97,7 +97,8 @@ static int __init imx6q_gpio_add_irq_domain(struct device_node *np,
97 static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS; 97 static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS;
98 98
99 gpio_irq_base -= 32; 99 gpio_irq_base -= 32;
100 irq_domain_add_simple(np, gpio_irq_base); 100 irq_domain_add_legacy(np, 32, gpio_irq_base, 0, &irq_domain_simple_ops,
101 NULL);
101 102
102 return 0; 103 return 0;
103} 104}
diff --git a/arch/arm/mach-imx/mach-mx53_ard.c b/arch/arm/mach-imx/mach-mx53_ard.c
index 08dfb7628d2d..753f4fc9ec04 100644
--- a/arch/arm/mach-imx/mach-mx53_ard.c
+++ b/arch/arm/mach-imx/mach-mx53_ard.c
@@ -188,8 +188,10 @@ static int weim_cs_config(void)
188 return -ENOMEM; 188 return -ENOMEM;
189 189
190 iomuxc_base = ioremap(MX53_IOMUXC_BASE_ADDR, SZ_4K); 190 iomuxc_base = ioremap(MX53_IOMUXC_BASE_ADDR, SZ_4K);
191 if (!iomuxc_base) 191 if (!iomuxc_base) {
192 iounmap(weim_base);
192 return -ENOMEM; 193 return -ENOMEM;
194 }
193 195
194 /* CS1 timings for LAN9220 */ 196 /* CS1 timings for LAN9220 */
195 writel(0x20001, (weim_base + 0x18)); 197 writel(0x20001, (weim_base + 0x18));
diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c
index d3b9c6b5edde..541152e450c4 100644
--- a/arch/arm/mach-imx/mach-pca100.c
+++ b/arch/arm/mach-imx/mach-pca100.c
@@ -36,7 +36,6 @@
36#include <mach/hardware.h> 36#include <mach/hardware.h>
37#include <mach/iomux-mx27.h> 37#include <mach/iomux-mx27.h>
38#include <asm/mach/time.h> 38#include <asm/mach/time.h>
39#include <mach/audmux.h>
40#include <mach/irqs.h> 39#include <mach/irqs.h>
41#include <mach/ulpi.h> 40#include <mach/ulpi.h>
42 41
@@ -359,18 +358,6 @@ static void __init pca100_init(void)
359 358
360 imx27_soc_init(); 359 imx27_soc_init();
361 360
362 /* SSI unit */
363 mxc_audmux_v1_configure_port(MX27_AUDMUX_HPCR1_SSI0,
364 MXC_AUDMUX_V1_PCR_SYN | /* 4wire mode */
365 MXC_AUDMUX_V1_PCR_TFCSEL(3) |
366 MXC_AUDMUX_V1_PCR_TCLKDIR | /* clock is output */
367 MXC_AUDMUX_V1_PCR_RXDSEL(3));
368 mxc_audmux_v1_configure_port(3,
369 MXC_AUDMUX_V1_PCR_SYN | /* 4wire mode */
370 MXC_AUDMUX_V1_PCR_TFCSEL(0) |
371 MXC_AUDMUX_V1_PCR_TFSDIR |
372 MXC_AUDMUX_V1_PCR_RXDSEL(0));
373
374 ret = mxc_gpio_setup_multiple_pins(pca100_pins, 361 ret = mxc_gpio_setup_multiple_pins(pca100_pins,
375 ARRAY_SIZE(pca100_pins), "PCA100"); 362 ARRAY_SIZE(pca100_pins), "PCA100");
376 if (ret) 363 if (ret)
diff --git a/arch/arm/mach-imx/mach-pcm037.c b/arch/arm/mach-imx/mach-pcm037.c
index e48854b9d990..5fddf94cc969 100644
--- a/arch/arm/mach-imx/mach-pcm037.c
+++ b/arch/arm/mach-imx/mach-pcm037.c
@@ -32,6 +32,8 @@
32#include <linux/usb/ulpi.h> 32#include <linux/usb/ulpi.h>
33#include <linux/gfp.h> 33#include <linux/gfp.h>
34#include <linux/memblock.h> 34#include <linux/memblock.h>
35#include <linux/regulator/machine.h>
36#include <linux/regulator/fixed.h>
35 37
36#include <media/soc_camera.h> 38#include <media/soc_camera.h>
37 39
@@ -570,6 +572,11 @@ static int __init pcm037_otg_mode(char *options)
570} 572}
571__setup("otg_mode=", pcm037_otg_mode); 573__setup("otg_mode=", pcm037_otg_mode);
572 574
575static struct regulator_consumer_supply dummy_supplies[] = {
576 REGULATOR_SUPPLY("vdd33a", "smsc911x"),
577 REGULATOR_SUPPLY("vddvario", "smsc911x"),
578};
579
573/* 580/*
574 * Board specific initialization. 581 * Board specific initialization.
575 */ 582 */
@@ -579,6 +586,8 @@ static void __init pcm037_init(void)
579 586
580 imx31_soc_init(); 587 imx31_soc_init();
581 588
589 regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
590
582 mxc_iomux_set_gpr(MUX_PGP_UH2, 1); 591 mxc_iomux_set_gpr(MUX_PGP_UH2, 1);
583 592
584 mxc_iomux_setup_multiple_pins(pcm037_pins, ARRAY_SIZE(pcm037_pins), 593 mxc_iomux_setup_multiple_pins(pcm037_pins, ARRAY_SIZE(pcm037_pins),
diff --git a/arch/arm/mach-imx/mach-pcm043.c b/arch/arm/mach-imx/mach-pcm043.c
index 06dc106519ae..237474fcca23 100644
--- a/arch/arm/mach-imx/mach-pcm043.c
+++ b/arch/arm/mach-imx/mach-pcm043.c
@@ -37,7 +37,6 @@
37#include <mach/common.h> 37#include <mach/common.h>
38#include <mach/iomux-mx35.h> 38#include <mach/iomux-mx35.h>
39#include <mach/ulpi.h> 39#include <mach/ulpi.h>
40#include <mach/audmux.h>
41 40
42#include "devices-imx35.h" 41#include "devices-imx35.h"
43 42
@@ -362,18 +361,6 @@ static void __init pcm043_init(void)
362 361
363 mxc_iomux_v3_setup_multiple_pads(pcm043_pads, ARRAY_SIZE(pcm043_pads)); 362 mxc_iomux_v3_setup_multiple_pads(pcm043_pads, ARRAY_SIZE(pcm043_pads));
364 363
365 mxc_audmux_v2_configure_port(3,
366 MXC_AUDMUX_V2_PTCR_SYN | /* 4wire mode */
367 MXC_AUDMUX_V2_PTCR_TFSEL(0) |
368 MXC_AUDMUX_V2_PTCR_TFSDIR,
369 MXC_AUDMUX_V2_PDCR_RXDSEL(0));
370
371 mxc_audmux_v2_configure_port(0,
372 MXC_AUDMUX_V2_PTCR_SYN | /* 4wire mode */
373 MXC_AUDMUX_V2_PTCR_TCSEL(3) |
374 MXC_AUDMUX_V2_PTCR_TCLKDIR, /* clock is output */
375 MXC_AUDMUX_V2_PDCR_RXDSEL(3));
376
377 imx35_add_fec(NULL); 364 imx35_add_fec(NULL);
378 platform_add_devices(devices, ARRAY_SIZE(devices)); 365 platform_add_devices(devices, ARRAY_SIZE(devices));
379 imx35_add_imx2_wdt(NULL); 366 imx35_add_imx2_wdt(NULL);
diff --git a/arch/arm/mach-imx/mm-imx21.c b/arch/arm/mach-imx/mm-imx21.c
index 3f05dfebacc9..14d540edfd1e 100644
--- a/arch/arm/mach-imx/mm-imx21.c
+++ b/arch/arm/mach-imx/mm-imx21.c
@@ -75,6 +75,10 @@ void __init mx21_init_irq(void)
75 mxc_init_irq(MX21_IO_ADDRESS(MX21_AVIC_BASE_ADDR)); 75 mxc_init_irq(MX21_IO_ADDRESS(MX21_AVIC_BASE_ADDR));
76} 76}
77 77
78static const struct resource imx21_audmux_res[] __initconst = {
79 DEFINE_RES_MEM(MX21_AUDMUX_BASE_ADDR, SZ_4K),
80};
81
78void __init imx21_soc_init(void) 82void __init imx21_soc_init(void)
79{ 83{
80 mxc_register_gpio("imx21-gpio", 0, MX21_GPIO1_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0); 84 mxc_register_gpio("imx21-gpio", 0, MX21_GPIO1_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
@@ -85,4 +89,6 @@ void __init imx21_soc_init(void)
85 mxc_register_gpio("imx21-gpio", 5, MX21_GPIO6_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0); 89 mxc_register_gpio("imx21-gpio", 5, MX21_GPIO6_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
86 90
87 imx_add_imx_dma(); 91 imx_add_imx_dma();
92 platform_device_register_simple("imx21-audmux", 0, imx21_audmux_res,
93 ARRAY_SIZE(imx21_audmux_res));
88} 94}
diff --git a/arch/arm/mach-imx/mm-imx25.c b/arch/arm/mach-imx/mm-imx25.c
index cc4d152bd9bd..153b457acdc0 100644
--- a/arch/arm/mach-imx/mm-imx25.c
+++ b/arch/arm/mach-imx/mm-imx25.c
@@ -83,6 +83,10 @@ static struct sdma_platform_data imx25_sdma_pdata __initdata = {
83 .script_addrs = &imx25_sdma_script, 83 .script_addrs = &imx25_sdma_script,
84}; 84};
85 85
86static const struct resource imx25_audmux_res[] __initconst = {
87 DEFINE_RES_MEM(MX25_AUDMUX_BASE_ADDR, SZ_16K),
88};
89
86void __init imx25_soc_init(void) 90void __init imx25_soc_init(void)
87{ 91{
88 /* i.mx25 has the i.mx31 type gpio */ 92 /* i.mx25 has the i.mx31 type gpio */
@@ -93,4 +97,7 @@ void __init imx25_soc_init(void)
93 97
94 /* i.mx25 has the i.mx35 type sdma */ 98 /* i.mx25 has the i.mx35 type sdma */
95 imx_add_imx_sdma("imx35-sdma", MX25_SDMA_BASE_ADDR, MX25_INT_SDMA, &imx25_sdma_pdata); 99 imx_add_imx_sdma("imx35-sdma", MX25_SDMA_BASE_ADDR, MX25_INT_SDMA, &imx25_sdma_pdata);
100 /* i.mx25 has the i.mx31 type audmux */
101 platform_device_register_simple("imx31-audmux", 0, imx25_audmux_res,
102 ARRAY_SIZE(imx25_audmux_res));
96} 103}
diff --git a/arch/arm/mach-imx/mm-imx27.c b/arch/arm/mach-imx/mm-imx27.c
index 96dd1f5ea7bd..8cb3f5e3e569 100644
--- a/arch/arm/mach-imx/mm-imx27.c
+++ b/arch/arm/mach-imx/mm-imx27.c
@@ -75,6 +75,10 @@ void __init mx27_init_irq(void)
75 mxc_init_irq(MX27_IO_ADDRESS(MX27_AVIC_BASE_ADDR)); 75 mxc_init_irq(MX27_IO_ADDRESS(MX27_AVIC_BASE_ADDR));
76} 76}
77 77
78static const struct resource imx27_audmux_res[] __initconst = {
79 DEFINE_RES_MEM(MX27_AUDMUX_BASE_ADDR, SZ_4K),
80};
81
78void __init imx27_soc_init(void) 82void __init imx27_soc_init(void)
79{ 83{
80 /* i.mx27 has the i.mx21 type gpio */ 84 /* i.mx27 has the i.mx21 type gpio */
@@ -86,4 +90,7 @@ void __init imx27_soc_init(void)
86 mxc_register_gpio("imx21-gpio", 5, MX27_GPIO6_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0); 90 mxc_register_gpio("imx21-gpio", 5, MX27_GPIO6_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0);
87 91
88 imx_add_imx_dma(); 92 imx_add_imx_dma();
93 /* imx27 has the imx21 type audmux */
94 platform_device_register_simple("imx21-audmux", 0, imx27_audmux_res,
95 ARRAY_SIZE(imx27_audmux_res));
89} 96}
diff --git a/arch/arm/mach-imx/mm-imx3.c b/arch/arm/mach-imx/mm-imx3.c
index 31807d2a8b7b..2530c151b7b3 100644
--- a/arch/arm/mach-imx/mm-imx3.c
+++ b/arch/arm/mach-imx/mm-imx3.c
@@ -158,6 +158,10 @@ static struct sdma_platform_data imx31_sdma_pdata __initdata = {
158 .script_addrs = &imx31_to2_sdma_script, 158 .script_addrs = &imx31_to2_sdma_script,
159}; 159};
160 160
161static const struct resource imx31_audmux_res[] __initconst = {
162 DEFINE_RES_MEM(MX31_AUDMUX_BASE_ADDR, SZ_16K),
163};
164
161void __init imx31_soc_init(void) 165void __init imx31_soc_init(void)
162{ 166{
163 int to_version = mx31_revision() >> 4; 167 int to_version = mx31_revision() >> 4;
@@ -175,6 +179,8 @@ void __init imx31_soc_init(void)
175 } 179 }
176 180
177 imx_add_imx_sdma("imx31-sdma", MX31_SDMA_BASE_ADDR, MX31_INT_SDMA, &imx31_sdma_pdata); 181 imx_add_imx_sdma("imx31-sdma", MX31_SDMA_BASE_ADDR, MX31_INT_SDMA, &imx31_sdma_pdata);
182 platform_device_register_simple("imx31-audmux", 0, imx31_audmux_res,
183 ARRAY_SIZE(imx31_audmux_res));
178} 184}
179#endif /* ifdef CONFIG_SOC_IMX31 */ 185#endif /* ifdef CONFIG_SOC_IMX31 */
180 186
@@ -241,6 +247,10 @@ static struct sdma_platform_data imx35_sdma_pdata __initdata = {
241 .script_addrs = &imx35_to2_sdma_script, 247 .script_addrs = &imx35_to2_sdma_script,
242}; 248};
243 249
250static const struct resource imx35_audmux_res[] __initconst = {
251 DEFINE_RES_MEM(MX35_AUDMUX_BASE_ADDR, SZ_16K),
252};
253
244void __init imx35_soc_init(void) 254void __init imx35_soc_init(void)
245{ 255{
246 int to_version = mx35_revision() >> 4; 256 int to_version = mx35_revision() >> 4;
@@ -259,5 +269,8 @@ void __init imx35_soc_init(void)
259 } 269 }
260 270
261 imx_add_imx_sdma("imx35-sdma", MX35_SDMA_BASE_ADDR, MX35_INT_SDMA, &imx35_sdma_pdata); 271 imx_add_imx_sdma("imx35-sdma", MX35_SDMA_BASE_ADDR, MX35_INT_SDMA, &imx35_sdma_pdata);
272 /* i.mx35 has the i.mx31 type audmux */
273 platform_device_register_simple("imx31-audmux", 0, imx35_audmux_res,
274 ARRAY_SIZE(imx35_audmux_res));
262} 275}
263#endif /* ifdef CONFIG_SOC_IMX35 */ 276#endif /* ifdef CONFIG_SOC_IMX35 */
diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c
index bc17dfea3817..90d7880bb372 100644
--- a/arch/arm/mach-imx/mm-imx5.c
+++ b/arch/arm/mach-imx/mm-imx5.c
@@ -170,6 +170,18 @@ static struct sdma_platform_data imx53_sdma_pdata __initdata = {
170 .script_addrs = &imx53_sdma_script, 170 .script_addrs = &imx53_sdma_script,
171}; 171};
172 172
173static const struct resource imx50_audmux_res[] __initconst = {
174 DEFINE_RES_MEM(MX50_AUDMUX_BASE_ADDR, SZ_16K),
175};
176
177static const struct resource imx51_audmux_res[] __initconst = {
178 DEFINE_RES_MEM(MX51_AUDMUX_BASE_ADDR, SZ_16K),
179};
180
181static const struct resource imx53_audmux_res[] __initconst = {
182 DEFINE_RES_MEM(MX53_AUDMUX_BASE_ADDR, SZ_16K),
183};
184
173void __init imx50_soc_init(void) 185void __init imx50_soc_init(void)
174{ 186{
175 /* i.mx50 has the i.mx31 type gpio */ 187 /* i.mx50 has the i.mx31 type gpio */
@@ -179,6 +191,10 @@ void __init imx50_soc_init(void)
179 mxc_register_gpio("imx31-gpio", 3, MX50_GPIO4_BASE_ADDR, SZ_16K, MX50_INT_GPIO4_LOW, MX50_INT_GPIO4_HIGH); 191 mxc_register_gpio("imx31-gpio", 3, MX50_GPIO4_BASE_ADDR, SZ_16K, MX50_INT_GPIO4_LOW, MX50_INT_GPIO4_HIGH);
180 mxc_register_gpio("imx31-gpio", 4, MX50_GPIO5_BASE_ADDR, SZ_16K, MX50_INT_GPIO5_LOW, MX50_INT_GPIO5_HIGH); 192 mxc_register_gpio("imx31-gpio", 4, MX50_GPIO5_BASE_ADDR, SZ_16K, MX50_INT_GPIO5_LOW, MX50_INT_GPIO5_HIGH);
181 mxc_register_gpio("imx31-gpio", 5, MX50_GPIO6_BASE_ADDR, SZ_16K, MX50_INT_GPIO6_LOW, MX50_INT_GPIO6_HIGH); 193 mxc_register_gpio("imx31-gpio", 5, MX50_GPIO6_BASE_ADDR, SZ_16K, MX50_INT_GPIO6_LOW, MX50_INT_GPIO6_HIGH);
194
195 /* i.mx50 has the i.mx31 type audmux */
196 platform_device_register_simple("imx31-audmux", 0, imx50_audmux_res,
197 ARRAY_SIZE(imx50_audmux_res));
182} 198}
183 199
184void __init imx51_soc_init(void) 200void __init imx51_soc_init(void)
@@ -191,6 +207,9 @@ void __init imx51_soc_init(void)
191 207
192 /* i.mx51 has the i.mx35 type sdma */ 208 /* i.mx51 has the i.mx35 type sdma */
193 imx_add_imx_sdma("imx35-sdma", MX51_SDMA_BASE_ADDR, MX51_INT_SDMA, &imx51_sdma_pdata); 209 imx_add_imx_sdma("imx35-sdma", MX51_SDMA_BASE_ADDR, MX51_INT_SDMA, &imx51_sdma_pdata);
210 /* i.mx51 has the i.mx31 type audmux */
211 platform_device_register_simple("imx31-audmux", 0, imx51_audmux_res,
212 ARRAY_SIZE(imx51_audmux_res));
194} 213}
195 214
196void __init imx53_soc_init(void) 215void __init imx53_soc_init(void)
@@ -206,4 +225,7 @@ void __init imx53_soc_init(void)
206 225
207 /* i.mx53 has the i.mx35 type sdma */ 226 /* i.mx53 has the i.mx35 type sdma */
208 imx_add_imx_sdma("imx35-sdma", MX53_SDMA_BASE_ADDR, MX53_INT_SDMA, &imx53_sdma_pdata); 227 imx_add_imx_sdma("imx35-sdma", MX53_SDMA_BASE_ADDR, MX53_INT_SDMA, &imx53_sdma_pdata);
228 /* i.mx53 has the i.mx31 type audmux */
229 platform_device_register_simple("imx31-audmux", 0, imx53_audmux_res,
230 ARRAY_SIZE(imx53_audmux_res));
209} 231}
diff --git a/arch/arm/mach-imx/mx31moboard-devboard.c b/arch/arm/mach-imx/mx31moboard-devboard.c
index 0aa25364360d..cc285e507286 100644
--- a/arch/arm/mach-imx/mx31moboard-devboard.c
+++ b/arch/arm/mach-imx/mx31moboard-devboard.c
@@ -158,7 +158,7 @@ static int devboard_usbh1_hw_init(struct platform_device *pdev)
158#define USBH1_VBUSEN_B IOMUX_TO_GPIO(MX31_PIN_NFRE_B) 158#define USBH1_VBUSEN_B IOMUX_TO_GPIO(MX31_PIN_NFRE_B)
159#define USBH1_MODE IOMUX_TO_GPIO(MX31_PIN_NFALE) 159#define USBH1_MODE IOMUX_TO_GPIO(MX31_PIN_NFALE)
160 160
161static int devboard_isp1105_init(struct otg_transceiver *otg) 161static int devboard_isp1105_init(struct usb_phy *otg)
162{ 162{
163 int ret = gpio_request(USBH1_MODE, "usbh1-mode"); 163 int ret = gpio_request(USBH1_MODE, "usbh1-mode");
164 if (ret) 164 if (ret)
@@ -177,7 +177,7 @@ static int devboard_isp1105_init(struct otg_transceiver *otg)
177} 177}
178 178
179 179
180static int devboard_isp1105_set_vbus(struct otg_transceiver *otg, bool on) 180static int devboard_isp1105_set_vbus(struct usb_otg *otg, bool on)
181{ 181{
182 if (on) 182 if (on)
183 gpio_set_value(USBH1_VBUSEN_B, 0); 183 gpio_set_value(USBH1_VBUSEN_B, 0);
@@ -194,18 +194,24 @@ static struct mxc_usbh_platform_data usbh1_pdata __initdata = {
194 194
195static int __init devboard_usbh1_init(void) 195static int __init devboard_usbh1_init(void)
196{ 196{
197 struct otg_transceiver *otg; 197 struct usb_phy *phy;
198 struct platform_device *pdev; 198 struct platform_device *pdev;
199 199
200 otg = kzalloc(sizeof(*otg), GFP_KERNEL); 200 phy = kzalloc(sizeof(*phy), GFP_KERNEL);
201 if (!otg) 201 if (!phy)
202 return -ENOMEM; 202 return -ENOMEM;
203 203
204 otg->label = "ISP1105"; 204 phy->otg = kzalloc(sizeof(struct usb_otg), GFP_KERNEL);
205 otg->init = devboard_isp1105_init; 205 if (!phy->otg) {
206 otg->set_vbus = devboard_isp1105_set_vbus; 206 kfree(phy);
207 return -ENOMEM;
208 }
209
210 phy->label = "ISP1105";
211 phy->init = devboard_isp1105_init;
212 phy->otg->set_vbus = devboard_isp1105_set_vbus;
207 213
208 usbh1_pdata.otg = otg; 214 usbh1_pdata.otg = phy;
209 215
210 pdev = imx31_add_mxc_ehci_hs(1, &usbh1_pdata); 216 pdev = imx31_add_mxc_ehci_hs(1, &usbh1_pdata);
211 if (IS_ERR(pdev)) 217 if (IS_ERR(pdev))
diff --git a/arch/arm/mach-imx/mx31moboard-marxbot.c b/arch/arm/mach-imx/mx31moboard-marxbot.c
index bb639cbda4e5..135c90e3a45f 100644
--- a/arch/arm/mach-imx/mx31moboard-marxbot.c
+++ b/arch/arm/mach-imx/mx31moboard-marxbot.c
@@ -272,7 +272,7 @@ static int marxbot_usbh1_hw_init(struct platform_device *pdev)
272#define USBH1_VBUSEN_B IOMUX_TO_GPIO(MX31_PIN_NFRE_B) 272#define USBH1_VBUSEN_B IOMUX_TO_GPIO(MX31_PIN_NFRE_B)
273#define USBH1_MODE IOMUX_TO_GPIO(MX31_PIN_NFALE) 273#define USBH1_MODE IOMUX_TO_GPIO(MX31_PIN_NFALE)
274 274
275static int marxbot_isp1105_init(struct otg_transceiver *otg) 275static int marxbot_isp1105_init(struct usb_phy *otg)
276{ 276{
277 int ret = gpio_request(USBH1_MODE, "usbh1-mode"); 277 int ret = gpio_request(USBH1_MODE, "usbh1-mode");
278 if (ret) 278 if (ret)
@@ -291,7 +291,7 @@ static int marxbot_isp1105_init(struct otg_transceiver *otg)
291} 291}
292 292
293 293
294static int marxbot_isp1105_set_vbus(struct otg_transceiver *otg, bool on) 294static int marxbot_isp1105_set_vbus(struct usb_otg *otg, bool on)
295{ 295{
296 if (on) 296 if (on)
297 gpio_set_value(USBH1_VBUSEN_B, 0); 297 gpio_set_value(USBH1_VBUSEN_B, 0);
@@ -308,18 +308,24 @@ static struct mxc_usbh_platform_data usbh1_pdata __initdata = {
308 308
309static int __init marxbot_usbh1_init(void) 309static int __init marxbot_usbh1_init(void)
310{ 310{
311 struct otg_transceiver *otg; 311 struct usb_phy *phy;
312 struct platform_device *pdev; 312 struct platform_device *pdev;
313 313
314 otg = kzalloc(sizeof(*otg), GFP_KERNEL); 314 phy = kzalloc(sizeof(*phy), GFP_KERNEL);
315 if (!otg) 315 if (!phy)
316 return -ENOMEM; 316 return -ENOMEM;
317 317
318 otg->label = "ISP1105"; 318 phy->otg = kzalloc(sizeof(struct usb_otg), GFP_KERNEL);
319 otg->init = marxbot_isp1105_init; 319 if (!phy->otg) {
320 otg->set_vbus = marxbot_isp1105_set_vbus; 320 kfree(phy);
321 return -ENOMEM;
322 }
323
324 phy->label = "ISP1105";
325 phy->init = marxbot_isp1105_init;
326 phy->otg->set_vbus = marxbot_isp1105_set_vbus;
321 327
322 usbh1_pdata.otg = otg; 328 usbh1_pdata.otg = phy;
323 329
324 pdev = imx31_add_mxc_ehci_hs(1, &usbh1_pdata); 330 pdev = imx31_add_mxc_ehci_hs(1, &usbh1_pdata);
325 if (IS_ERR(pdev)) 331 if (IS_ERR(pdev))
diff --git a/arch/arm/mach-imx/src.c b/arch/arm/mach-imx/src.c
index 29bd1243781e..e15f1555c59b 100644
--- a/arch/arm/mach-imx/src.c
+++ b/arch/arm/mach-imx/src.c
@@ -15,6 +15,7 @@
15#include <linux/of.h> 15#include <linux/of.h>
16#include <linux/of_address.h> 16#include <linux/of_address.h>
17#include <linux/smp.h> 17#include <linux/smp.h>
18#include <asm/smp_plat.h>
18 19
19#define SRC_SCR 0x000 20#define SRC_SCR 0x000
20#define SRC_GPR1 0x020 21#define SRC_GPR1 0x020
@@ -24,10 +25,6 @@
24 25
25static void __iomem *src_base; 26static void __iomem *src_base;
26 27
27#ifndef CONFIG_SMP
28#define cpu_logical_map(cpu) 0
29#endif
30
31void imx_enable_cpu(int cpu, bool enable) 28void imx_enable_cpu(int cpu, bool enable)
32{ 29{
33 u32 mask, val; 30 u32 mask, val;
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index cc15426787b1..77d4852e19f2 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -27,6 +27,7 @@
27#include <plat/cache-feroceon-l2.h> 27#include <plat/cache-feroceon-l2.h>
28#include <plat/mvsdio.h> 28#include <plat/mvsdio.h>
29#include <plat/orion_nand.h> 29#include <plat/orion_nand.h>
30#include <plat/ehci-orion.h>
30#include <plat/common.h> 31#include <plat/common.h>
31#include <plat/time.h> 32#include <plat/time.h>
32#include <plat/addr-map.h> 33#include <plat/addr-map.h>
@@ -73,7 +74,7 @@ unsigned int kirkwood_clk_ctrl = CGC_DUNIT | CGC_RESERVED;
73void __init kirkwood_ehci_init(void) 74void __init kirkwood_ehci_init(void)
74{ 75{
75 kirkwood_clk_ctrl |= CGC_USB0; 76 kirkwood_clk_ctrl |= CGC_USB0;
76 orion_ehci_init(USB_PHYS_BASE, IRQ_KIRKWOOD_USB); 77 orion_ehci_init(USB_PHYS_BASE, IRQ_KIRKWOOD_USB, EHCI_PHY_NA);
77} 78}
78 79
79 80
diff --git a/arch/arm/mach-kirkwood/mpp.h b/arch/arm/mach-kirkwood/mpp.h
index e8fda45c0736..d5a0d1da2e0e 100644
--- a/arch/arm/mach-kirkwood/mpp.h
+++ b/arch/arm/mach-kirkwood/mpp.h
@@ -31,314 +31,314 @@
31#define MPP_F6282_MASK MPP( 0, 0x0, 0, 0, 0, 0, 0, 0, 1 ) 31#define MPP_F6282_MASK MPP( 0, 0x0, 0, 0, 0, 0, 0, 0, 1 )
32 32
33#define MPP0_GPIO MPP( 0, 0x0, 1, 1, 1, 1, 1, 1, 1 ) 33#define MPP0_GPIO MPP( 0, 0x0, 1, 1, 1, 1, 1, 1, 1 )
34#define MPP0_NF_IO2 MPP( 0, 0x1, 1, 1, 1, 1, 1, 1, 1 ) 34#define MPP0_NF_IO2 MPP( 0, 0x1, 0, 0, 1, 1, 1, 1, 1 )
35#define MPP0_SPI_SCn MPP( 0, 0x2, 0, 1, 1, 1, 1, 1, 1 ) 35#define MPP0_SPI_SCn MPP( 0, 0x2, 0, 0, 1, 1, 1, 1, 1 )
36 36
37#define MPP1_GPO MPP( 1, 0x0, 0, 1, 1, 1, 1, 1, 1 ) 37#define MPP1_GPO MPP( 1, 0x0, 0, 1, 1, 1, 1, 1, 1 )
38#define MPP1_NF_IO3 MPP( 1, 0x1, 1, 1, 1, 1, 1, 1, 1 ) 38#define MPP1_NF_IO3 MPP( 1, 0x1, 0, 0, 1, 1, 1, 1, 1 )
39#define MPP1_SPI_MOSI MPP( 1, 0x2, 0, 1, 1, 1, 1, 1, 1 ) 39#define MPP1_SPI_MOSI MPP( 1, 0x2, 0, 0, 1, 1, 1, 1, 1 )
40 40
41#define MPP2_GPO MPP( 2, 0x0, 0, 1, 1, 1, 1, 1, 1 ) 41#define MPP2_GPO MPP( 2, 0x0, 0, 1, 1, 1, 1, 1, 1 )
42#define MPP2_NF_IO4 MPP( 2, 0x1, 1, 1, 1, 1, 1, 1, 1 ) 42#define MPP2_NF_IO4 MPP( 2, 0x1, 0, 0, 1, 1, 1, 1, 1 )
43#define MPP2_SPI_SCK MPP( 2, 0x2, 0, 1, 1, 1, 1, 1, 1 ) 43#define MPP2_SPI_SCK MPP( 2, 0x2, 0, 0, 1, 1, 1, 1, 1 )
44 44
45#define MPP3_GPO MPP( 3, 0x0, 0, 1, 1, 1, 1, 1, 1 ) 45#define MPP3_GPO MPP( 3, 0x0, 0, 1, 1, 1, 1, 1, 1 )
46#define MPP3_NF_IO5 MPP( 3, 0x1, 1, 1, 1, 1, 1, 1, 1 ) 46#define MPP3_NF_IO5 MPP( 3, 0x1, 0, 0, 1, 1, 1, 1, 1 )
47#define MPP3_SPI_MISO MPP( 3, 0x2, 1, 0, 1, 1, 1, 1, 1 ) 47#define MPP3_SPI_MISO MPP( 3, 0x2, 0, 0, 1, 1, 1, 1, 1 )
48 48
49#define MPP4_GPIO MPP( 4, 0x0, 1, 1, 1, 1, 1, 1, 1 ) 49#define MPP4_GPIO MPP( 4, 0x0, 1, 1, 1, 1, 1, 1, 1 )
50#define MPP4_NF_IO6 MPP( 4, 0x1, 1, 1, 1, 1, 1, 1, 1 ) 50#define MPP4_NF_IO6 MPP( 4, 0x1, 0, 0, 1, 1, 1, 1, 1 )
51#define MPP4_UART0_RXD MPP( 4, 0x2, 1, 0, 1, 1, 1, 1, 1 ) 51#define MPP4_UART0_RXD MPP( 4, 0x2, 0, 0, 1, 1, 1, 1, 1 )
52#define MPP4_SATA1_ACTn MPP( 4, 0x5, 0, 1, 0, 0, 1, 1, 1 ) 52#define MPP4_SATA1_ACTn MPP( 4, 0x5, 0, 0, 0, 0, 1, 1, 1 )
53#define MPP4_LCD_VGA_HSYNC MPP( 4, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 53#define MPP4_LCD_VGA_HSYNC MPP( 4, 0xb, 0, 0, 0, 0, 0, 0, 1 )
54#define MPP4_PTP_CLK MPP( 4, 0xd, 1, 0, 1, 1, 1, 1, 0 ) 54#define MPP4_PTP_CLK MPP( 4, 0xd, 0, 0, 1, 1, 1, 1, 0 )
55 55
56#define MPP5_GPO MPP( 5, 0x0, 0, 1, 1, 1, 1, 1, 1 ) 56#define MPP5_GPO MPP( 5, 0x0, 0, 1, 1, 1, 1, 1, 1 )
57#define MPP5_NF_IO7 MPP( 5, 0x1, 1, 1, 1, 1, 1, 1, 1 ) 57#define MPP5_NF_IO7 MPP( 5, 0x1, 0, 0, 1, 1, 1, 1, 1 )
58#define MPP5_UART0_TXD MPP( 5, 0x2, 0, 1, 1, 1, 1, 1, 1 ) 58#define MPP5_UART0_TXD MPP( 5, 0x2, 0, 0, 1, 1, 1, 1, 1 )
59#define MPP5_PTP_TRIG_GEN MPP( 5, 0x4, 0, 1, 1, 1, 1, 1, 0 ) 59#define MPP5_PTP_TRIG_GEN MPP( 5, 0x4, 0, 0, 1, 1, 1, 1, 0 )
60#define MPP5_SATA0_ACTn MPP( 5, 0x5, 0, 1, 0, 1, 1, 1, 1 ) 60#define MPP5_SATA0_ACTn MPP( 5, 0x5, 0, 0, 0, 1, 1, 1, 1 )
61#define MPP5_LCD_VGA_VSYNC MPP( 5, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 61#define MPP5_LCD_VGA_VSYNC MPP( 5, 0xb, 0, 0, 0, 0, 0, 0, 1 )
62 62
63#define MPP6_SYSRST_OUTn MPP( 6, 0x1, 0, 1, 1, 1, 1, 1, 1 ) 63#define MPP6_SYSRST_OUTn MPP( 6, 0x1, 0, 0, 1, 1, 1, 1, 1 )
64#define MPP6_SPI_MOSI MPP( 6, 0x2, 0, 1, 1, 1, 1, 1, 1 ) 64#define MPP6_SPI_MOSI MPP( 6, 0x2, 0, 0, 1, 1, 1, 1, 1 )
65#define MPP6_PTP_TRIG_GEN MPP( 6, 0x3, 0, 1, 1, 1, 1, 1, 0 ) 65#define MPP6_PTP_TRIG_GEN MPP( 6, 0x3, 0, 0, 1, 1, 1, 1, 0 )
66 66
67#define MPP7_GPO MPP( 7, 0x0, 0, 1, 1, 1, 1, 1, 1 ) 67#define MPP7_GPO MPP( 7, 0x0, 0, 1, 1, 1, 1, 1, 1 )
68#define MPP7_PEX_RST_OUTn MPP( 7, 0x1, 0, 1, 1, 1, 1, 1, 0 ) 68#define MPP7_PEX_RST_OUTn MPP( 7, 0x1, 0, 0, 1, 1, 1, 1, 0 )
69#define MPP7_SPI_SCn MPP( 7, 0x2, 0, 1, 1, 1, 1, 1, 1 ) 69#define MPP7_SPI_SCn MPP( 7, 0x2, 0, 0, 1, 1, 1, 1, 1 )
70#define MPP7_PTP_TRIG_GEN MPP( 7, 0x3, 0, 1, 1, 1, 1, 1, 0 ) 70#define MPP7_PTP_TRIG_GEN MPP( 7, 0x3, 0, 0, 1, 1, 1, 1, 0 )
71#define MPP7_LCD_PWM MPP( 7, 0xb, 0, 1, 0, 0, 0, 0, 1 ) 71#define MPP7_LCD_PWM MPP( 7, 0xb, 0, 0, 0, 0, 0, 0, 1 )
72 72
73#define MPP8_GPIO MPP( 8, 0x0, 1, 1, 1, 1, 1, 1, 1 ) 73#define MPP8_GPIO MPP( 8, 0x0, 1, 1, 1, 1, 1, 1, 1 )
74#define MPP8_TW0_SDA MPP( 8, 0x1, 1, 1, 1, 1, 1, 1, 1 ) 74#define MPP8_TW0_SDA MPP( 8, 0x1, 0, 0, 1, 1, 1, 1, 1 )
75#define MPP8_UART0_RTS MPP( 8, 0x2, 0, 1, 1, 1, 1, 1, 1 ) 75#define MPP8_UART0_RTS MPP( 8, 0x2, 0, 0, 1, 1, 1, 1, 1 )
76#define MPP8_UART1_RTS MPP( 8, 0x3, 0, 1, 1, 1, 1, 1, 1 ) 76#define MPP8_UART1_RTS MPP( 8, 0x3, 0, 0, 1, 1, 1, 1, 1 )
77#define MPP8_MII0_RXERR MPP( 8, 0x4, 1, 0, 0, 1, 1, 1, 1 ) 77#define MPP8_MII0_RXERR MPP( 8, 0x4, 0, 0, 0, 1, 1, 1, 1 )
78#define MPP8_SATA1_PRESENTn MPP( 8, 0x5, 0, 1, 0, 0, 1, 1, 1 ) 78#define MPP8_SATA1_PRESENTn MPP( 8, 0x5, 0, 0, 0, 0, 1, 1, 1 )
79#define MPP8_PTP_CLK MPP( 8, 0xc, 1, 0, 1, 1, 1, 1, 0 ) 79#define MPP8_PTP_CLK MPP( 8, 0xc, 0, 0, 1, 1, 1, 1, 0 )
80#define MPP8_MII0_COL MPP( 8, 0xd, 1, 0, 1, 1, 1, 1, 1 ) 80#define MPP8_MII0_COL MPP( 8, 0xd, 0, 0, 1, 1, 1, 1, 1 )
81 81
82#define MPP9_GPIO MPP( 9, 0x0, 1, 1, 1, 1, 1, 1, 1 ) 82#define MPP9_GPIO MPP( 9, 0x0, 1, 1, 1, 1, 1, 1, 1 )
83#define MPP9_TW0_SCK MPP( 9, 0x1, 1, 1, 1, 1, 1, 1, 1 ) 83#define MPP9_TW0_SCK MPP( 9, 0x1, 0, 0, 1, 1, 1, 1, 1 )
84#define MPP9_UART0_CTS MPP( 9, 0x2, 1, 0, 1, 1, 1, 1, 1 ) 84#define MPP9_UART0_CTS MPP( 9, 0x2, 0, 0, 1, 1, 1, 1, 1 )
85#define MPP9_UART1_CTS MPP( 9, 0x3, 1, 0, 1, 1, 1, 1, 1 ) 85#define MPP9_UART1_CTS MPP( 9, 0x3, 0, 0, 1, 1, 1, 1, 1 )
86#define MPP9_SATA0_PRESENTn MPP( 9, 0x5, 0, 1, 0, 1, 1, 1, 1 ) 86#define MPP9_SATA0_PRESENTn MPP( 9, 0x5, 0, 0, 0, 1, 1, 1, 1 )
87#define MPP9_PTP_EVENT_REQ MPP( 9, 0xc, 1, 0, 1, 1, 1, 1, 0 ) 87#define MPP9_PTP_EVENT_REQ MPP( 9, 0xc, 0, 0, 1, 1, 1, 1, 0 )
88#define MPP9_MII0_CRS MPP( 9, 0xd, 1, 0, 1, 1, 1, 1, 1 ) 88#define MPP9_MII0_CRS MPP( 9, 0xd, 0, 0, 1, 1, 1, 1, 1 )
89 89
90#define MPP10_GPO MPP( 10, 0x0, 0, 1, 1, 1, 1, 1, 1 ) 90#define MPP10_GPO MPP( 10, 0x0, 0, 1, 1, 1, 1, 1, 1 )
91#define MPP10_SPI_SCK MPP( 10, 0x2, 0, 1, 1, 1, 1, 1, 1 ) 91#define MPP10_SPI_SCK MPP( 10, 0x2, 0, 0, 1, 1, 1, 1, 1 )
92#define MPP10_UART0_TXD MPP( 10, 0X3, 0, 1, 1, 1, 1, 1, 1 ) 92#define MPP10_UART0_TXD MPP( 10, 0X3, 0, 0, 1, 1, 1, 1, 1 )
93#define MPP10_SATA1_ACTn MPP( 10, 0x5, 0, 1, 0, 0, 1, 1, 1 ) 93#define MPP10_SATA1_ACTn MPP( 10, 0x5, 0, 0, 0, 0, 1, 1, 1 )
94#define MPP10_PTP_TRIG_GEN MPP( 10, 0xc, 0, 1, 1, 1, 1, 1, 0 ) 94#define MPP10_PTP_TRIG_GEN MPP( 10, 0xc, 0, 0, 1, 1, 1, 1, 0 )
95 95
96#define MPP11_GPIO MPP( 11, 0x0, 1, 1, 1, 1, 1, 1, 1 ) 96#define MPP11_GPIO MPP( 11, 0x0, 1, 1, 1, 1, 1, 1, 1 )
97#define MPP11_SPI_MISO MPP( 11, 0x2, 1, 0, 1, 1, 1, 1, 1 ) 97#define MPP11_SPI_MISO MPP( 11, 0x2, 0, 0, 1, 1, 1, 1, 1 )
98#define MPP11_UART0_RXD MPP( 11, 0x3, 1, 0, 1, 1, 1, 1, 1 ) 98#define MPP11_UART0_RXD MPP( 11, 0x3, 0, 0, 1, 1, 1, 1, 1 )
99#define MPP11_PTP_EVENT_REQ MPP( 11, 0x4, 1, 0, 1, 1, 1, 1, 0 ) 99#define MPP11_PTP_EVENT_REQ MPP( 11, 0x4, 0, 0, 1, 1, 1, 1, 0 )
100#define MPP11_PTP_TRIG_GEN MPP( 11, 0xc, 0, 1, 1, 1, 1, 1, 0 ) 100#define MPP11_PTP_TRIG_GEN MPP( 11, 0xc, 0, 0, 1, 1, 1, 1, 0 )
101#define MPP11_PTP_CLK MPP( 11, 0xd, 1, 0, 1, 1, 1, 1, 0 ) 101#define MPP11_PTP_CLK MPP( 11, 0xd, 0, 0, 1, 1, 1, 1, 0 )
102#define MPP11_SATA0_ACTn MPP( 11, 0x5, 0, 1, 0, 1, 1, 1, 1 ) 102#define MPP11_SATA0_ACTn MPP( 11, 0x5, 0, 0, 0, 1, 1, 1, 1 )
103 103
104#define MPP12_GPO MPP( 12, 0x0, 0, 1, 1, 1, 1, 1, 1 ) 104#define MPP12_GPO MPP( 12, 0x0, 0, 1, 1, 1, 1, 1, 1 )
105#define MPP12_GPIO MPP( 12, 0x0, 1, 1, 0, 0, 0, 1, 0 ) 105#define MPP12_GPIO MPP( 12, 0x0, 1, 1, 0, 0, 0, 1, 0 )
106#define MPP12_SD_CLK MPP( 12, 0x1, 0, 1, 1, 1, 1, 1, 1 ) 106#define MPP12_SD_CLK MPP( 12, 0x1, 0, 0, 1, 1, 1, 1, 1 )
107#define MPP12_AU_SPDIF0 MPP( 12, 0xa, 0, 1, 0, 0, 0, 0, 1 ) 107#define MPP12_AU_SPDIF0 MPP( 12, 0xa, 0, 0, 0, 0, 0, 0, 1 )
108#define MPP12_SPI_MOSI MPP( 12, 0xb, 0, 1, 0, 0, 0, 0, 1 ) 108#define MPP12_SPI_MOSI MPP( 12, 0xb, 0, 0, 0, 0, 0, 0, 1 )
109#define MPP12_TW1_SDA MPP( 12, 0xd, 1, 0, 0, 0, 0, 0, 1 ) 109#define MPP12_TW1_SDA MPP( 12, 0xd, 0, 0, 0, 0, 0, 0, 1 )
110 110
111#define MPP13_GPIO MPP( 13, 0x0, 1, 1, 1, 1, 1, 1, 1 ) 111#define MPP13_GPIO MPP( 13, 0x0, 1, 1, 1, 1, 1, 1, 1 )
112#define MPP13_SD_CMD MPP( 13, 0x1, 1, 1, 1, 1, 1, 1, 1 ) 112#define MPP13_SD_CMD MPP( 13, 0x1, 0, 0, 1, 1, 1, 1, 1 )
113#define MPP13_UART1_TXD MPP( 13, 0x3, 0, 1, 1, 1, 1, 1, 1 ) 113#define MPP13_UART1_TXD MPP( 13, 0x3, 0, 0, 1, 1, 1, 1, 1 )
114#define MPP13_AU_SPDIFRMCLK MPP( 13, 0xa, 0, 1, 0, 0, 0, 0, 1 ) 114#define MPP13_AU_SPDIFRMCLK MPP( 13, 0xa, 0, 0, 0, 0, 0, 0, 1 )
115#define MPP13_LCDPWM MPP( 13, 0xb, 0, 1, 0, 0, 0, 0, 1 ) 115#define MPP13_LCDPWM MPP( 13, 0xb, 0, 0, 0, 0, 0, 0, 1 )
116 116
117#define MPP14_GPIO MPP( 14, 0x0, 1, 1, 1, 1, 1, 1, 1 ) 117#define MPP14_GPIO MPP( 14, 0x0, 1, 1, 1, 1, 1, 1, 1 )
118#define MPP14_SD_D0 MPP( 14, 0x1, 1, 1, 1, 1, 1, 1, 1 ) 118#define MPP14_SD_D0 MPP( 14, 0x1, 0, 0, 1, 1, 1, 1, 1 )
119#define MPP14_UART1_RXD MPP( 14, 0x3, 1, 0, 1, 1, 1, 1, 1 ) 119#define MPP14_UART1_RXD MPP( 14, 0x3, 0, 0, 1, 1, 1, 1, 1 )
120#define MPP14_SATA1_PRESENTn MPP( 14, 0x4, 0, 1, 0, 0, 1, 1, 1 ) 120#define MPP14_SATA1_PRESENTn MPP( 14, 0x4, 0, 0, 0, 0, 1, 1, 1 )
121#define MPP14_AU_SPDIFI MPP( 14, 0xa, 1, 0, 0, 0, 0, 0, 1 ) 121#define MPP14_AU_SPDIFI MPP( 14, 0xa, 0, 0, 0, 0, 0, 0, 1 )
122#define MPP14_AU_I2SDI MPP( 14, 0xb, 1, 0, 0, 0, 0, 0, 1 ) 122#define MPP14_AU_I2SDI MPP( 14, 0xb, 0, 0, 0, 0, 0, 0, 1 )
123#define MPP14_MII0_COL MPP( 14, 0xd, 1, 0, 1, 1, 1, 1, 1 ) 123#define MPP14_MII0_COL MPP( 14, 0xd, 0, 0, 1, 1, 1, 1, 1 )
124 124
125#define MPP15_GPIO MPP( 15, 0x0, 1, 1, 1, 1, 1, 1, 1 ) 125#define MPP15_GPIO MPP( 15, 0x0, 1, 1, 1, 1, 1, 1, 1 )
126#define MPP15_SD_D1 MPP( 15, 0x1, 1, 1, 1, 1, 1, 1, 1 ) 126#define MPP15_SD_D1 MPP( 15, 0x1, 0, 0, 1, 1, 1, 1, 1 )
127#define MPP15_UART0_RTS MPP( 15, 0x2, 0, 1, 1, 1, 1, 1, 1 ) 127#define MPP15_UART0_RTS MPP( 15, 0x2, 0, 0, 1, 1, 1, 1, 1 )
128#define MPP15_UART1_TXD MPP( 15, 0x3, 0, 1, 1, 1, 1, 1, 1 ) 128#define MPP15_UART1_TXD MPP( 15, 0x3, 0, 0, 1, 1, 1, 1, 1 )
129#define MPP15_SATA0_ACTn MPP( 15, 0x4, 0, 1, 0, 1, 1, 1, 1 ) 129#define MPP15_SATA0_ACTn MPP( 15, 0x4, 0, 0, 0, 1, 1, 1, 1 )
130#define MPP15_SPI_CSn MPP( 15, 0xb, 0, 1, 0, 0, 0, 0, 1 ) 130#define MPP15_SPI_CSn MPP( 15, 0xb, 0, 0, 0, 0, 0, 0, 1 )
131 131
132#define MPP16_GPIO MPP( 16, 0x0, 1, 1, 1, 1, 1, 1, 1 ) 132#define MPP16_GPIO MPP( 16, 0x0, 1, 1, 1, 1, 1, 1, 1 )
133#define MPP16_SD_D2 MPP( 16, 0x1, 1, 1, 1, 1, 1, 1, 1 ) 133#define MPP16_SD_D2 MPP( 16, 0x1, 0, 0, 1, 1, 1, 1, 1 )
134#define MPP16_UART0_CTS MPP( 16, 0x2, 1, 0, 1, 1, 1, 1, 1 ) 134#define MPP16_UART0_CTS MPP( 16, 0x2, 0, 0, 1, 1, 1, 1, 1 )
135#define MPP16_UART1_RXD MPP( 16, 0x3, 1, 0, 1, 1, 1, 1, 1 ) 135#define MPP16_UART1_RXD MPP( 16, 0x3, 0, 0, 1, 1, 1, 1, 1 )
136#define MPP16_SATA1_ACTn MPP( 16, 0x4, 0, 1, 0, 0, 1, 1, 1 ) 136#define MPP16_SATA1_ACTn MPP( 16, 0x4, 0, 0, 0, 0, 1, 1, 1 )
137#define MPP16_LCD_EXT_REF_CLK MPP( 16, 0xb, 1, 0, 0, 0, 0, 0, 1 ) 137#define MPP16_LCD_EXT_REF_CLK MPP( 16, 0xb, 0, 0, 0, 0, 0, 0, 1 )
138#define MPP16_MII0_CRS MPP( 16, 0xd, 1, 0, 1, 1, 1, 1, 1 ) 138#define MPP16_MII0_CRS MPP( 16, 0xd, 0, 0, 1, 1, 1, 1, 1 )
139 139
140#define MPP17_GPIO MPP( 17, 0x0, 1, 1, 1, 1, 1, 1, 1 ) 140#define MPP17_GPIO MPP( 17, 0x0, 1, 1, 1, 1, 1, 1, 1 )
141#define MPP17_SD_D3 MPP( 17, 0x1, 1, 1, 1, 1, 1, 1, 1 ) 141#define MPP17_SD_D3 MPP( 17, 0x1, 0, 0, 1, 1, 1, 1, 1 )
142#define MPP17_SATA0_PRESENTn MPP( 17, 0x4, 0, 1, 0, 1, 1, 1, 1 ) 142#define MPP17_SATA0_PRESENTn MPP( 17, 0x4, 0, 0, 0, 1, 1, 1, 1 )
143#define MPP17_SATA1_ACTn MPP( 17, 0xa, 0, 1, 0, 0, 0, 0, 1 ) 143#define MPP17_SATA1_ACTn MPP( 17, 0xa, 0, 0, 0, 0, 0, 0, 1 )
144#define MPP17_TW1_SCK MPP( 17, 0xd, 1, 1, 0, 0, 0, 0, 1 ) 144#define MPP17_TW1_SCK MPP( 17, 0xd, 0, 0, 0, 0, 0, 0, 1 )
145 145
146#define MPP18_GPO MPP( 18, 0x0, 0, 1, 1, 1, 1, 1, 1 ) 146#define MPP18_GPO MPP( 18, 0x0, 0, 1, 1, 1, 1, 1, 1 )
147#define MPP18_NF_IO0 MPP( 18, 0x1, 1, 1, 1, 1, 1, 1, 1 ) 147#define MPP18_NF_IO0 MPP( 18, 0x1, 0, 0, 1, 1, 1, 1, 1 )
148#define MPP18_PEX0_CLKREQ MPP( 18, 0x2, 0, 1, 0, 0, 0, 0, 1 ) 148#define MPP18_PEX0_CLKREQ MPP( 18, 0x2, 0, 0, 0, 0, 0, 0, 1 )
149 149
150#define MPP19_GPO MPP( 19, 0x0, 0, 1, 1, 1, 1, 1, 1 ) 150#define MPP19_GPO MPP( 19, 0x0, 0, 1, 1, 1, 1, 1, 1 )
151#define MPP19_NF_IO1 MPP( 19, 0x1, 1, 1, 1, 1, 1, 1, 1 ) 151#define MPP19_NF_IO1 MPP( 19, 0x1, 0, 0, 1, 1, 1, 1, 1 )
152 152
153#define MPP20_GPIO MPP( 20, 0x0, 1, 1, 0, 1, 1, 1, 1 ) 153#define MPP20_GPIO MPP( 20, 0x0, 1, 1, 0, 1, 1, 1, 1 )
154#define MPP20_TSMP0 MPP( 20, 0x1, 1, 1, 0, 0, 1, 1, 1 ) 154#define MPP20_TSMP0 MPP( 20, 0x1, 0, 0, 0, 0, 1, 1, 1 )
155#define MPP20_TDM_CH0_TX_QL MPP( 20, 0x2, 0, 1, 0, 0, 1, 1, 1 ) 155#define MPP20_TDM_CH0_TX_QL MPP( 20, 0x2, 0, 0, 0, 0, 1, 1, 1 )
156#define MPP20_GE1_TXD0 MPP( 20, 0x3, 0, 0, 0, 1, 1, 1, 1 ) 156#define MPP20_GE1_TXD0 MPP( 20, 0x3, 0, 0, 0, 1, 1, 1, 1 )
157#define MPP20_AU_SPDIFI MPP( 20, 0x4, 1, 0, 0, 0, 1, 1, 1 ) 157#define MPP20_AU_SPDIFI MPP( 20, 0x4, 0, 0, 0, 0, 1, 1, 1 )
158#define MPP20_SATA1_ACTn MPP( 20, 0x5, 0, 1, 0, 0, 1, 1, 1 ) 158#define MPP20_SATA1_ACTn MPP( 20, 0x5, 0, 0, 0, 0, 1, 1, 1 )
159#define MPP20_LCD_D0 MPP( 20, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 159#define MPP20_LCD_D0 MPP( 20, 0xb, 0, 0, 0, 0, 0, 0, 1 )
160 160
161#define MPP21_GPIO MPP( 21, 0x0, 1, 1, 0, 1, 1, 1, 1 ) 161#define MPP21_GPIO MPP( 21, 0x0, 1, 1, 0, 1, 1, 1, 1 )
162#define MPP21_TSMP1 MPP( 21, 0x1, 1, 1, 0, 0, 1, 1, 1 ) 162#define MPP21_TSMP1 MPP( 21, 0x1, 0, 0, 0, 0, 1, 1, 1 )
163#define MPP21_TDM_CH0_RX_QL MPP( 21, 0x2, 0, 1, 0, 0, 1, 1, 1 ) 163#define MPP21_TDM_CH0_RX_QL MPP( 21, 0x2, 0, 0, 0, 0, 1, 1, 1 )
164#define MPP21_GE1_TXD1 MPP( 21, 0x3, 0, 0, 0, 1, 1, 1, 1 ) 164#define MPP21_GE1_TXD1 MPP( 21, 0x3, 0, 0, 0, 1, 1, 1, 1 )
165#define MPP21_AU_SPDIFO MPP( 21, 0x4, 0, 1, 0, 0, 1, 1, 1 ) 165#define MPP21_AU_SPDIFO MPP( 21, 0x4, 0, 0, 0, 0, 1, 1, 1 )
166#define MPP21_SATA0_ACTn MPP( 21, 0x5, 0, 1, 0, 1, 1, 1, 1 ) 166#define MPP21_SATA0_ACTn MPP( 21, 0x5, 0, 0, 0, 1, 1, 1, 1 )
167#define MPP21_LCD_D1 MPP( 21, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 167#define MPP21_LCD_D1 MPP( 21, 0xb, 0, 0, 0, 0, 0, 0, 1 )
168 168
169#define MPP22_GPIO MPP( 22, 0x0, 1, 1, 0, 1, 1, 1, 1 ) 169#define MPP22_GPIO MPP( 22, 0x0, 1, 1, 0, 1, 1, 1, 1 )
170#define MPP22_TSMP2 MPP( 22, 0x1, 1, 1, 0, 0, 1, 1, 1 ) 170#define MPP22_TSMP2 MPP( 22, 0x1, 0, 0, 0, 0, 1, 1, 1 )
171#define MPP22_TDM_CH2_TX_QL MPP( 22, 0x2, 0, 1, 0, 0, 1, 1, 1 ) 171#define MPP22_TDM_CH2_TX_QL MPP( 22, 0x2, 0, 0, 0, 0, 1, 1, 1 )
172#define MPP22_GE1_TXD2 MPP( 22, 0x3, 0, 0, 0, 1, 1, 1, 1 ) 172#define MPP22_GE1_TXD2 MPP( 22, 0x3, 0, 0, 0, 1, 1, 1, 1 )
173#define MPP22_AU_SPDIFRMKCLK MPP( 22, 0x4, 0, 1, 0, 0, 1, 1, 1 ) 173#define MPP22_AU_SPDIFRMKCLK MPP( 22, 0x4, 0, 0, 0, 0, 1, 1, 1 )
174#define MPP22_SATA1_PRESENTn MPP( 22, 0x5, 0, 1, 0, 0, 1, 1, 1 ) 174#define MPP22_SATA1_PRESENTn MPP( 22, 0x5, 0, 0, 0, 0, 1, 1, 1 )
175#define MPP22_LCD_D2 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 175#define MPP22_LCD_D2 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 )
176 176
177#define MPP23_GPIO MPP( 23, 0x0, 1, 1, 0, 1, 1, 1, 1 ) 177#define MPP23_GPIO MPP( 23, 0x0, 1, 1, 0, 1, 1, 1, 1 )
178#define MPP23_TSMP3 MPP( 23, 0x1, 1, 1, 0, 0, 1, 1, 1 ) 178#define MPP23_TSMP3 MPP( 23, 0x1, 0, 0, 0, 0, 1, 1, 1 )
179#define MPP23_TDM_CH2_RX_QL MPP( 23, 0x2, 1, 0, 0, 0, 1, 1, 1 ) 179#define MPP23_TDM_CH2_RX_QL MPP( 23, 0x2, 0, 0, 0, 0, 1, 1, 1 )
180#define MPP23_GE1_TXD3 MPP( 23, 0x3, 0, 0, 0, 1, 1, 1, 1 ) 180#define MPP23_GE1_TXD3 MPP( 23, 0x3, 0, 0, 0, 1, 1, 1, 1 )
181#define MPP23_AU_I2SBCLK MPP( 23, 0x4, 0, 1, 0, 0, 1, 1, 1 ) 181#define MPP23_AU_I2SBCLK MPP( 23, 0x4, 0, 0, 0, 0, 1, 1, 1 )
182#define MPP23_SATA0_PRESENTn MPP( 23, 0x5, 0, 1, 0, 1, 1, 1, 1 ) 182#define MPP23_SATA0_PRESENTn MPP( 23, 0x5, 0, 0, 0, 1, 1, 1, 1 )
183#define MPP23_LCD_D3 MPP( 23, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 183#define MPP23_LCD_D3 MPP( 23, 0xb, 0, 0, 0, 0, 0, 0, 1 )
184 184
185#define MPP24_GPIO MPP( 24, 0x0, 1, 1, 0, 1, 1, 1, 1 ) 185#define MPP24_GPIO MPP( 24, 0x0, 1, 1, 0, 1, 1, 1, 1 )
186#define MPP24_TSMP4 MPP( 24, 0x1, 1, 1, 0, 0, 1, 1, 1 ) 186#define MPP24_TSMP4 MPP( 24, 0x1, 0, 0, 0, 0, 1, 1, 1 )
187#define MPP24_TDM_SPI_CS0 MPP( 24, 0x2, 0, 1, 0, 0, 1, 1, 1 ) 187#define MPP24_TDM_SPI_CS0 MPP( 24, 0x2, 0, 0, 0, 0, 1, 1, 1 )
188#define MPP24_GE1_RXD0 MPP( 24, 0x3, 0, 0, 0, 1, 1, 1, 1 ) 188#define MPP24_GE1_RXD0 MPP( 24, 0x3, 0, 0, 0, 1, 1, 1, 1 )
189#define MPP24_AU_I2SDO MPP( 24, 0x4, 0, 1, 0, 0, 1, 1, 1 ) 189#define MPP24_AU_I2SDO MPP( 24, 0x4, 0, 0, 0, 0, 1, 1, 1 )
190#define MPP24_LCD_D4 MPP( 24, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 190#define MPP24_LCD_D4 MPP( 24, 0xb, 0, 0, 0, 0, 0, 0, 1 )
191 191
192#define MPP25_GPIO MPP( 25, 0x0, 1, 1, 0, 1, 1, 1, 1 ) 192#define MPP25_GPIO MPP( 25, 0x0, 1, 1, 0, 1, 1, 1, 1 )
193#define MPP25_TSMP5 MPP( 25, 0x1, 1, 1, 0, 0, 1, 1, 1 ) 193#define MPP25_TSMP5 MPP( 25, 0x1, 0, 0, 0, 0, 1, 1, 1 )
194#define MPP25_TDM_SPI_SCK MPP( 25, 0x2, 0, 1, 0, 0, 1, 1, 1 ) 194#define MPP25_TDM_SPI_SCK MPP( 25, 0x2, 0, 0, 0, 0, 1, 1, 1 )
195#define MPP25_GE1_RXD1 MPP( 25, 0x3, 0, 0, 0, 1, 1, 1, 1 ) 195#define MPP25_GE1_RXD1 MPP( 25, 0x3, 0, 0, 0, 1, 1, 1, 1 )
196#define MPP25_AU_I2SLRCLK MPP( 25, 0x4, 0, 1, 0, 0, 1, 1, 1 ) 196#define MPP25_AU_I2SLRCLK MPP( 25, 0x4, 0, 0, 0, 0, 1, 1, 1 )
197#define MPP25_LCD_D5 MPP( 25, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 197#define MPP25_LCD_D5 MPP( 25, 0xb, 0, 0, 0, 0, 0, 0, 1 )
198 198
199#define MPP26_GPIO MPP( 26, 0x0, 1, 1, 0, 1, 1, 1, 1 ) 199#define MPP26_GPIO MPP( 26, 0x0, 1, 1, 0, 1, 1, 1, 1 )
200#define MPP26_TSMP6 MPP( 26, 0x1, 1, 1, 0, 0, 1, 1, 1 ) 200#define MPP26_TSMP6 MPP( 26, 0x1, 0, 0, 0, 0, 1, 1, 1 )
201#define MPP26_TDM_SPI_MISO MPP( 26, 0x2, 1, 0, 0, 0, 1, 1, 1 ) 201#define MPP26_TDM_SPI_MISO MPP( 26, 0x2, 0, 0, 0, 0, 1, 1, 1 )
202#define MPP26_GE1_RXD2 MPP( 26, 0x3, 0, 0, 0, 1, 1, 1, 1 ) 202#define MPP26_GE1_RXD2 MPP( 26, 0x3, 0, 0, 0, 1, 1, 1, 1 )
203#define MPP26_AU_I2SMCLK MPP( 26, 0x4, 0, 1, 0, 0, 1, 1, 1 ) 203#define MPP26_AU_I2SMCLK MPP( 26, 0x4, 0, 0, 0, 0, 1, 1, 1 )
204#define MPP26_LCD_D6 MPP( 26, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 204#define MPP26_LCD_D6 MPP( 26, 0xb, 0, 0, 0, 0, 0, 0, 1 )
205 205
206#define MPP27_GPIO MPP( 27, 0x0, 1, 1, 0, 1, 1, 1, 1 ) 206#define MPP27_GPIO MPP( 27, 0x0, 1, 1, 0, 1, 1, 1, 1 )
207#define MPP27_TSMP7 MPP( 27, 0x1, 1, 1, 0, 0, 1, 1, 1 ) 207#define MPP27_TSMP7 MPP( 27, 0x1, 0, 0, 0, 0, 1, 1, 1 )
208#define MPP27_TDM_SPI_MOSI MPP( 27, 0x2, 0, 1, 0, 0, 1, 1, 1 ) 208#define MPP27_TDM_SPI_MOSI MPP( 27, 0x2, 0, 0, 0, 0, 1, 1, 1 )
209#define MPP27_GE1_RXD3 MPP( 27, 0x3, 0, 0, 0, 1, 1, 1, 1 ) 209#define MPP27_GE1_RXD3 MPP( 27, 0x3, 0, 0, 0, 1, 1, 1, 1 )
210#define MPP27_AU_I2SDI MPP( 27, 0x4, 1, 0, 0, 0, 1, 1, 1 ) 210#define MPP27_AU_I2SDI MPP( 27, 0x4, 0, 0, 0, 0, 1, 1, 1 )
211#define MPP27_LCD_D7 MPP( 27, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 211#define MPP27_LCD_D7 MPP( 27, 0xb, 0, 0, 0, 0, 0, 0, 1 )
212 212
213#define MPP28_GPIO MPP( 28, 0x0, 1, 1, 0, 1, 1, 1, 1 ) 213#define MPP28_GPIO MPP( 28, 0x0, 1, 1, 0, 1, 1, 1, 1 )
214#define MPP28_TSMP8 MPP( 28, 0x1, 1, 1, 0, 0, 1, 1, 1 ) 214#define MPP28_TSMP8 MPP( 28, 0x1, 0, 0, 0, 0, 1, 1, 1 )
215#define MPP28_TDM_CODEC_INTn MPP( 28, 0x2, 0, 0, 0, 0, 1, 1, 1 ) 215#define MPP28_TDM_CODEC_INTn MPP( 28, 0x2, 0, 0, 0, 0, 1, 1, 1 )
216#define MPP28_GE1_COL MPP( 28, 0x3, 0, 0, 0, 1, 1, 1, 1 ) 216#define MPP28_GE1_COL MPP( 28, 0x3, 0, 0, 0, 1, 1, 1, 1 )
217#define MPP28_AU_EXTCLK MPP( 28, 0x4, 1, 0, 0, 0, 1, 1, 1 ) 217#define MPP28_AU_EXTCLK MPP( 28, 0x4, 0, 0, 0, 0, 1, 1, 1 )
218#define MPP28_LCD_D8 MPP( 28, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 218#define MPP28_LCD_D8 MPP( 28, 0xb, 0, 0, 0, 0, 0, 0, 1 )
219 219
220#define MPP29_GPIO MPP( 29, 0x0, 1, 1, 0, 1, 1, 1, 1 ) 220#define MPP29_GPIO MPP( 29, 0x0, 1, 1, 0, 1, 1, 1, 1 )
221#define MPP29_TSMP9 MPP( 29, 0x1, 1, 1, 0, 0, 1, 1, 1 ) 221#define MPP29_TSMP9 MPP( 29, 0x1, 0, 0, 0, 0, 1, 1, 1 )
222#define MPP29_TDM_CODEC_RSTn MPP( 29, 0x2, 0, 0, 0, 0, 1, 1, 1 ) 222#define MPP29_TDM_CODEC_RSTn MPP( 29, 0x2, 0, 0, 0, 0, 1, 1, 1 )
223#define MPP29_GE1_TCLK MPP( 29, 0x3, 0, 0, 0, 1, 1, 1, 1 ) 223#define MPP29_GE1_TCLK MPP( 29, 0x3, 0, 0, 0, 1, 1, 1, 1 )
224#define MPP29_LCD_D9 MPP( 29, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 224#define MPP29_LCD_D9 MPP( 29, 0xb, 0, 0, 0, 0, 0, 0, 1 )
225 225
226#define MPP30_GPIO MPP( 30, 0x0, 1, 1, 0, 1, 1, 1, 1 ) 226#define MPP30_GPIO MPP( 30, 0x0, 1, 1, 0, 1, 1, 1, 1 )
227#define MPP30_TSMP10 MPP( 30, 0x1, 1, 1, 0, 0, 1, 1, 1 ) 227#define MPP30_TSMP10 MPP( 30, 0x1, 0, 0, 0, 0, 1, 1, 1 )
228#define MPP30_TDM_PCLK MPP( 30, 0x2, 1, 1, 0, 0, 1, 1, 1 ) 228#define MPP30_TDM_PCLK MPP( 30, 0x2, 0, 0, 0, 0, 1, 1, 1 )
229#define MPP30_GE1_RXCTL MPP( 30, 0x3, 0, 0, 0, 1, 1, 1, 1 ) 229#define MPP30_GE1_RXCTL MPP( 30, 0x3, 0, 0, 0, 1, 1, 1, 1 )
230#define MPP30_LCD_D10 MPP( 30, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 230#define MPP30_LCD_D10 MPP( 30, 0xb, 0, 0, 0, 0, 0, 0, 1 )
231 231
232#define MPP31_GPIO MPP( 31, 0x0, 1, 1, 0, 1, 1, 1, 1 ) 232#define MPP31_GPIO MPP( 31, 0x0, 1, 1, 0, 1, 1, 1, 1 )
233#define MPP31_TSMP11 MPP( 31, 0x1, 1, 1, 0, 0, 1, 1, 1 ) 233#define MPP31_TSMP11 MPP( 31, 0x1, 0, 0, 0, 0, 1, 1, 1 )
234#define MPP31_TDM_FS MPP( 31, 0x2, 1, 1, 0, 0, 1, 1, 1 ) 234#define MPP31_TDM_FS MPP( 31, 0x2, 0, 0, 0, 0, 1, 1, 1 )
235#define MPP31_GE1_RXCLK MPP( 31, 0x3, 0, 0, 0, 1, 1, 1, 1 ) 235#define MPP31_GE1_RXCLK MPP( 31, 0x3, 0, 0, 0, 1, 1, 1, 1 )
236#define MPP31_LCD_D11 MPP( 31, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 236#define MPP31_LCD_D11 MPP( 31, 0xb, 0, 0, 0, 0, 0, 0, 1 )
237 237
238#define MPP32_GPIO MPP( 32, 0x0, 1, 1, 0, 1, 1, 1, 1 ) 238#define MPP32_GPIO MPP( 32, 0x0, 1, 1, 0, 1, 1, 1, 1 )
239#define MPP32_TSMP12 MPP( 32, 0x1, 1, 1, 0, 0, 1, 1, 1 ) 239#define MPP32_TSMP12 MPP( 32, 0x1, 0, 0, 0, 0, 1, 1, 1 )
240#define MPP32_TDM_DRX MPP( 32, 0x2, 1, 0, 0, 0, 1, 1, 1 ) 240#define MPP32_TDM_DRX MPP( 32, 0x2, 0, 0, 0, 0, 1, 1, 1 )
241#define MPP32_GE1_TCLKOUT MPP( 32, 0x3, 0, 0, 0, 1, 1, 1, 1 ) 241#define MPP32_GE1_TCLKOUT MPP( 32, 0x3, 0, 0, 0, 1, 1, 1, 1 )
242#define MPP32_LCD_D12 MPP( 32, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 242#define MPP32_LCD_D12 MPP( 32, 0xb, 0, 0, 0, 0, 0, 0, 1 )
243 243
244#define MPP33_GPO MPP( 33, 0x0, 0, 1, 0, 1, 1, 1, 1 ) 244#define MPP33_GPO MPP( 33, 0x0, 0, 1, 0, 1, 1, 1, 1 )
245#define MPP33_TDM_DTX MPP( 33, 0x2, 0, 1, 0, 0, 1, 1, 1 ) 245#define MPP33_TDM_DTX MPP( 33, 0x2, 0, 0, 0, 0, 1, 1, 1 )
246#define MPP33_GE1_TXCTL MPP( 33, 0x3, 0, 0, 0, 1, 1, 1, 1 ) 246#define MPP33_GE1_TXCTL MPP( 33, 0x3, 0, 0, 0, 1, 1, 1, 1 )
247#define MPP33_LCD_D13 MPP( 33, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 247#define MPP33_LCD_D13 MPP( 33, 0xb, 0, 0, 0, 0, 0, 0, 1 )
248 248
249#define MPP34_GPIO MPP( 34, 0x0, 1, 1, 0, 1, 1, 1, 1 ) 249#define MPP34_GPIO MPP( 34, 0x0, 1, 1, 0, 1, 1, 1, 1 )
250#define MPP34_TDM_SPI_CS1 MPP( 34, 0x2, 0, 1, 0, 0, 1, 1, 1 ) 250#define MPP34_TDM_SPI_CS1 MPP( 34, 0x2, 0, 0, 0, 0, 1, 1, 1 )
251#define MPP34_GE1_TXEN MPP( 34, 0x3, 0, 0, 0, 1, 1, 1, 1 ) 251#define MPP34_GE1_TXEN MPP( 34, 0x3, 0, 0, 0, 1, 1, 1, 1 )
252#define MPP34_SATA1_ACTn MPP( 34, 0x5, 0, 1, 0, 0, 0, 1, 1 ) 252#define MPP34_SATA1_ACTn MPP( 34, 0x5, 0, 0, 0, 0, 0, 1, 1 )
253#define MPP34_LCD_D14 MPP( 34, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 253#define MPP34_LCD_D14 MPP( 34, 0xb, 0, 0, 0, 0, 0, 0, 1 )
254 254
255#define MPP35_GPIO MPP( 35, 0x0, 1, 1, 1, 1, 1, 1, 1 ) 255#define MPP35_GPIO MPP( 35, 0x0, 1, 1, 1, 1, 1, 1, 1 )
256#define MPP35_TDM_CH0_TX_QL MPP( 35, 0x2, 0, 1, 0, 0, 1, 1, 1 ) 256#define MPP35_TDM_CH0_TX_QL MPP( 35, 0x2, 0, 0, 0, 0, 1, 1, 1 )
257#define MPP35_GE1_RXERR MPP( 35, 0x3, 0, 0, 0, 1, 1, 1, 1 ) 257#define MPP35_GE1_RXERR MPP( 35, 0x3, 0, 0, 0, 1, 1, 1, 1 )
258#define MPP35_SATA0_ACTn MPP( 35, 0x5, 0, 1, 0, 1, 1, 1, 1 ) 258#define MPP35_SATA0_ACTn MPP( 35, 0x5, 0, 0, 0, 1, 1, 1, 1 )
259#define MPP35_LCD_D15 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 259#define MPP35_LCD_D15 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 )
260#define MPP35_MII0_RXERR MPP( 35, 0xc, 1, 0, 1, 1, 1, 1, 1 ) 260#define MPP35_MII0_RXERR MPP( 35, 0xc, 0, 0, 1, 1, 1, 1, 1 )
261 261
262#define MPP36_GPIO MPP( 36, 0x0, 1, 1, 1, 0, 0, 1, 1 ) 262#define MPP36_GPIO MPP( 36, 0x0, 1, 1, 1, 0, 0, 1, 1 )
263#define MPP36_TSMP0 MPP( 36, 0x1, 1, 1, 0, 0, 0, 1, 1 ) 263#define MPP36_TSMP0 MPP( 36, 0x1, 0, 0, 0, 0, 0, 1, 1 )
264#define MPP36_TDM_SPI_CS1 MPP( 36, 0x2, 0, 1, 0, 0, 0, 1, 1 ) 264#define MPP36_TDM_SPI_CS1 MPP( 36, 0x2, 0, 0, 0, 0, 0, 1, 1 )
265#define MPP36_AU_SPDIFI MPP( 36, 0x4, 1, 0, 1, 0, 0, 1, 1 ) 265#define MPP36_AU_SPDIFI MPP( 36, 0x4, 0, 0, 1, 0, 0, 1, 1 )
266#define MPP36_TW1_SDA MPP( 36, 0xb, 1, 1, 0, 0, 0, 0, 1 ) 266#define MPP36_TW1_SDA MPP( 36, 0xb, 0, 0, 0, 0, 0, 0, 1 )
267 267
268#define MPP37_GPIO MPP( 37, 0x0, 1, 1, 1, 0, 0, 1, 1 ) 268#define MPP37_GPIO MPP( 37, 0x0, 1, 1, 1, 0, 0, 1, 1 )
269#define MPP37_TSMP1 MPP( 37, 0x1, 1, 1, 0, 0, 0, 1, 1 ) 269#define MPP37_TSMP1 MPP( 37, 0x1, 0, 0, 0, 0, 0, 1, 1 )
270#define MPP37_TDM_CH2_TX_QL MPP( 37, 0x2, 0, 1, 0, 0, 0, 1, 1 ) 270#define MPP37_TDM_CH2_TX_QL MPP( 37, 0x2, 0, 0, 0, 0, 0, 1, 1 )
271#define MPP37_AU_SPDIFO MPP( 37, 0x4, 0, 1, 1, 0, 0, 1, 1 ) 271#define MPP37_AU_SPDIFO MPP( 37, 0x4, 0, 0, 1, 0, 0, 1, 1 )
272#define MPP37_TW1_SCK MPP( 37, 0xb, 1, 1, 0, 0, 0, 0, 1 ) 272#define MPP37_TW1_SCK MPP( 37, 0xb, 0, 0, 0, 0, 0, 0, 1 )
273 273
274#define MPP38_GPIO MPP( 38, 0x0, 1, 1, 1, 0, 0, 1, 1 ) 274#define MPP38_GPIO MPP( 38, 0x0, 1, 1, 1, 0, 0, 1, 1 )
275#define MPP38_TSMP2 MPP( 38, 0x1, 1, 1, 0, 0, 0, 1, 1 ) 275#define MPP38_TSMP2 MPP( 38, 0x1, 0, 0, 0, 0, 0, 1, 1 )
276#define MPP38_TDM_CH2_RX_QL MPP( 38, 0x2, 0, 1, 0, 0, 0, 1, 1 ) 276#define MPP38_TDM_CH2_RX_QL MPP( 38, 0x2, 0, 0, 0, 0, 0, 1, 1 )
277#define MPP38_AU_SPDIFRMLCLK MPP( 38, 0x4, 0, 1, 1, 0, 0, 1, 1 ) 277#define MPP38_AU_SPDIFRMLCLK MPP( 38, 0x4, 0, 0, 1, 0, 0, 1, 1 )
278#define MPP38_LCD_D18 MPP( 38, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 278#define MPP38_LCD_D18 MPP( 38, 0xb, 0, 0, 0, 0, 0, 0, 1 )
279 279
280#define MPP39_GPIO MPP( 39, 0x0, 1, 1, 1, 0, 0, 1, 1 ) 280#define MPP39_GPIO MPP( 39, 0x0, 1, 1, 1, 0, 0, 1, 1 )
281#define MPP39_TSMP3 MPP( 39, 0x1, 1, 1, 0, 0, 0, 1, 1 ) 281#define MPP39_TSMP3 MPP( 39, 0x1, 0, 0, 0, 0, 0, 1, 1 )
282#define MPP39_TDM_SPI_CS0 MPP( 39, 0x2, 0, 1, 0, 0, 0, 1, 1 ) 282#define MPP39_TDM_SPI_CS0 MPP( 39, 0x2, 0, 0, 0, 0, 0, 1, 1 )
283#define MPP39_AU_I2SBCLK MPP( 39, 0x4, 0, 1, 1, 0, 0, 1, 1 ) 283#define MPP39_AU_I2SBCLK MPP( 39, 0x4, 0, 0, 1, 0, 0, 1, 1 )
284#define MPP39_LCD_D19 MPP( 39, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 284#define MPP39_LCD_D19 MPP( 39, 0xb, 0, 0, 0, 0, 0, 0, 1 )
285 285
286#define MPP40_GPIO MPP( 40, 0x0, 1, 1, 1, 0, 0, 1, 1 ) 286#define MPP40_GPIO MPP( 40, 0x0, 1, 1, 1, 0, 0, 1, 1 )
287#define MPP40_TSMP4 MPP( 40, 0x1, 1, 1, 0, 0, 0, 1, 1 ) 287#define MPP40_TSMP4 MPP( 40, 0x1, 0, 0, 0, 0, 0, 1, 1 )
288#define MPP40_TDM_SPI_SCK MPP( 40, 0x2, 0, 1, 0, 0, 0, 1, 1 ) 288#define MPP40_TDM_SPI_SCK MPP( 40, 0x2, 0, 0, 0, 0, 0, 1, 1 )
289#define MPP40_AU_I2SDO MPP( 40, 0x4, 0, 1, 1, 0, 0, 1, 1 ) 289#define MPP40_AU_I2SDO MPP( 40, 0x4, 0, 0, 1, 0, 0, 1, 1 )
290#define MPP40_LCD_D20 MPP( 40, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 290#define MPP40_LCD_D20 MPP( 40, 0xb, 0, 0, 0, 0, 0, 0, 1 )
291 291
292#define MPP41_GPIO MPP( 41, 0x0, 1, 1, 1, 0, 0, 1, 1 ) 292#define MPP41_GPIO MPP( 41, 0x0, 1, 1, 1, 0, 0, 1, 1 )
293#define MPP41_TSMP5 MPP( 41, 0x1, 1, 1, 0, 0, 0, 1, 1 ) 293#define MPP41_TSMP5 MPP( 41, 0x1, 0, 0, 0, 0, 0, 1, 1 )
294#define MPP41_TDM_SPI_MISO MPP( 41, 0x2, 1, 0, 0, 0, 0, 1, 1 ) 294#define MPP41_TDM_SPI_MISO MPP( 41, 0x2, 0, 0, 0, 0, 0, 1, 1 )
295#define MPP41_AU_I2SLRCLK MPP( 41, 0x4, 0, 1, 1, 0, 0, 1, 1 ) 295#define MPP41_AU_I2SLRCLK MPP( 41, 0x4, 0, 0, 1, 0, 0, 1, 1 )
296#define MPP41_LCD_D21 MPP( 41, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 296#define MPP41_LCD_D21 MPP( 41, 0xb, 0, 0, 0, 0, 0, 0, 1 )
297 297
298#define MPP42_GPIO MPP( 42, 0x0, 1, 1, 1, 0, 0, 1, 1 ) 298#define MPP42_GPIO MPP( 42, 0x0, 1, 1, 1, 0, 0, 1, 1 )
299#define MPP42_TSMP6 MPP( 42, 0x1, 1, 1, 0, 0, 0, 1, 1 ) 299#define MPP42_TSMP6 MPP( 42, 0x1, 0, 0, 0, 0, 0, 1, 1 )
300#define MPP42_TDM_SPI_MOSI MPP( 42, 0x2, 0, 1, 0, 0, 0, 1, 1 ) 300#define MPP42_TDM_SPI_MOSI MPP( 42, 0x2, 0, 0, 0, 0, 0, 1, 1 )
301#define MPP42_AU_I2SMCLK MPP( 42, 0x4, 0, 1, 1, 0, 0, 1, 1 ) 301#define MPP42_AU_I2SMCLK MPP( 42, 0x4, 0, 0, 1, 0, 0, 1, 1 )
302#define MPP42_LCD_D22 MPP( 42, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 302#define MPP42_LCD_D22 MPP( 42, 0xb, 0, 0, 0, 0, 0, 0, 1 )
303 303
304#define MPP43_GPIO MPP( 43, 0x0, 1, 1, 1, 0, 0, 1, 1 ) 304#define MPP43_GPIO MPP( 43, 0x0, 1, 1, 1, 0, 0, 1, 1 )
305#define MPP43_TSMP7 MPP( 43, 0x1, 1, 1, 0, 0, 0, 1, 1 ) 305#define MPP43_TSMP7 MPP( 43, 0x1, 0, 0, 0, 0, 0, 1, 1 )
306#define MPP43_TDM_CODEC_INTn MPP( 43, 0x2, 0, 0, 0, 0, 0, 1, 1 ) 306#define MPP43_TDM_CODEC_INTn MPP( 43, 0x2, 0, 0, 0, 0, 0, 1, 1 )
307#define MPP43_AU_I2SDI MPP( 43, 0x4, 1, 0, 1, 0, 0, 1, 1 ) 307#define MPP43_AU_I2SDI MPP( 43, 0x4, 0, 0, 1, 0, 0, 1, 1 )
308#define MPP43_LCD_D23 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 308#define MPP43_LCD_D23 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 )
309 309
310#define MPP44_GPIO MPP( 44, 0x0, 1, 1, 1, 0, 0, 1, 1 ) 310#define MPP44_GPIO MPP( 44, 0x0, 1, 1, 1, 0, 0, 1, 1 )
311#define MPP44_TSMP8 MPP( 44, 0x1, 1, 1, 0, 0, 0, 1, 1 ) 311#define MPP44_TSMP8 MPP( 44, 0x1, 0, 0, 0, 0, 0, 1, 1 )
312#define MPP44_TDM_CODEC_RSTn MPP( 44, 0x2, 0, 0, 0, 0, 0, 1, 1 ) 312#define MPP44_TDM_CODEC_RSTn MPP( 44, 0x2, 0, 0, 0, 0, 0, 1, 1 )
313#define MPP44_AU_EXTCLK MPP( 44, 0x4, 1, 0, 1, 0, 0, 1, 1 ) 313#define MPP44_AU_EXTCLK MPP( 44, 0x4, 0, 0, 1, 0, 0, 1, 1 )
314#define MPP44_LCD_CLK MPP( 44, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 314#define MPP44_LCD_CLK MPP( 44, 0xb, 0, 0, 0, 0, 0, 0, 1 )
315 315
316#define MPP45_GPIO MPP( 45, 0x0, 1, 1, 0, 0, 0, 1, 1 ) 316#define MPP45_GPIO MPP( 45, 0x0, 1, 1, 0, 0, 0, 1, 1 )
317#define MPP45_TSMP9 MPP( 45, 0x1, 1, 1, 0, 0, 0, 1, 1 ) 317#define MPP45_TSMP9 MPP( 45, 0x1, 0, 0, 0, 0, 0, 1, 1 )
318#define MPP45_TDM_PCLK MPP( 45, 0x2, 1, 1, 0, 0, 0, 1, 1 ) 318#define MPP45_TDM_PCLK MPP( 45, 0x2, 0, 0, 0, 0, 0, 1, 1 )
319#define MPP245_LCD_E MPP( 45, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 319#define MPP245_LCD_E MPP( 45, 0xb, 0, 0, 0, 0, 0, 0, 1 )
320 320
321#define MPP46_GPIO MPP( 46, 0x0, 1, 1, 0, 0, 0, 1, 1 ) 321#define MPP46_GPIO MPP( 46, 0x0, 1, 1, 0, 0, 0, 1, 1 )
322#define MPP46_TSMP10 MPP( 46, 0x1, 1, 1, 0, 0, 0, 1, 1 ) 322#define MPP46_TSMP10 MPP( 46, 0x1, 0, 0, 0, 0, 0, 1, 1 )
323#define MPP46_TDM_FS MPP( 46, 0x2, 1, 1, 0, 0, 0, 1, 1 ) 323#define MPP46_TDM_FS MPP( 46, 0x2, 0, 0, 0, 0, 0, 1, 1 )
324#define MPP46_LCD_HSYNC MPP( 46, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 324#define MPP46_LCD_HSYNC MPP( 46, 0xb, 0, 0, 0, 0, 0, 0, 1 )
325 325
326#define MPP47_GPIO MPP( 47, 0x0, 1, 1, 0, 0, 0, 1, 1 ) 326#define MPP47_GPIO MPP( 47, 0x0, 1, 1, 0, 0, 0, 1, 1 )
327#define MPP47_TSMP11 MPP( 47, 0x1, 1, 1, 0, 0, 0, 1, 1 ) 327#define MPP47_TSMP11 MPP( 47, 0x1, 0, 0, 0, 0, 0, 1, 1 )
328#define MPP47_TDM_DRX MPP( 47, 0x2, 1, 0, 0, 0, 0, 1, 1 ) 328#define MPP47_TDM_DRX MPP( 47, 0x2, 0, 0, 0, 0, 0, 1, 1 )
329#define MPP47_LCD_VSYNC MPP( 47, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 329#define MPP47_LCD_VSYNC MPP( 47, 0xb, 0, 0, 0, 0, 0, 0, 1 )
330 330
331#define MPP48_GPIO MPP( 48, 0x0, 1, 1, 0, 0, 0, 1, 1 ) 331#define MPP48_GPIO MPP( 48, 0x0, 1, 1, 0, 0, 0, 1, 1 )
332#define MPP48_TSMP12 MPP( 48, 0x1, 1, 1, 0, 0, 0, 1, 1 ) 332#define MPP48_TSMP12 MPP( 48, 0x1, 0, 0, 0, 0, 0, 1, 1 )
333#define MPP48_TDM_DTX MPP( 48, 0x2, 0, 1, 0, 0, 0, 1, 1 ) 333#define MPP48_TDM_DTX MPP( 48, 0x2, 0, 0, 0, 0, 0, 1, 1 )
334#define MPP48_LCD_D16 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 334#define MPP48_LCD_D16 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 )
335 335
336#define MPP49_GPIO MPP( 49, 0x0, 1, 1, 0, 0, 0, 1, 0 ) 336#define MPP49_GPIO MPP( 49, 0x0, 1, 1, 0, 0, 0, 1, 0 )
337#define MPP49_GPO MPP( 49, 0x0, 0, 1, 0, 0, 0, 0, 1 ) 337#define MPP49_GPO MPP( 49, 0x0, 0, 1, 0, 0, 0, 0, 1 )
338#define MPP49_TSMP9 MPP( 49, 0x1, 1, 1, 0, 0, 0, 1, 0 ) 338#define MPP49_TSMP9 MPP( 49, 0x1, 0, 0, 0, 0, 0, 1, 0 )
339#define MPP49_TDM_CH0_RX_QL MPP( 49, 0x2, 0, 1, 0, 0, 0, 1, 1 ) 339#define MPP49_TDM_CH0_RX_QL MPP( 49, 0x2, 0, 0, 0, 0, 0, 1, 1 )
340#define MPP49_PTP_CLK MPP( 49, 0x5, 1, 0, 0, 0, 0, 1, 0 ) 340#define MPP49_PTP_CLK MPP( 49, 0x5, 0, 0, 0, 0, 0, 1, 0 )
341#define MPP49_PEX0_CLKREQ MPP( 49, 0xa, 0, 1, 0, 0, 0, 0, 1 ) 341#define MPP49_PEX0_CLKREQ MPP( 49, 0xa, 0, 0, 0, 0, 0, 0, 1 )
342#define MPP49_LCD_D17 MPP( 49, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 342#define MPP49_LCD_D17 MPP( 49, 0xb, 0, 0, 0, 0, 0, 0, 1 )
343 343
344#define MPP_MAX 49 344#define MPP_MAX 49
diff --git a/arch/arm/mach-kirkwood/openrd-setup.c b/arch/arm/mach-kirkwood/openrd-setup.c
index 01f8c8992880..7e99c3f340fc 100644
--- a/arch/arm/mach-kirkwood/openrd-setup.c
+++ b/arch/arm/mach-kirkwood/openrd-setup.c
@@ -83,6 +83,11 @@ static struct i2c_board_info i2c_board_info[] __initdata = {
83 }, 83 },
84}; 84};
85 85
86static struct platform_device openrd_client_audio_device = {
87 .name = "openrd-client-audio",
88 .id = -1,
89};
90
86static int __initdata uart1; 91static int __initdata uart1;
87 92
88static int __init sd_uart_selection(char *str) 93static int __init sd_uart_selection(char *str)
@@ -172,6 +177,7 @@ static void __init openrd_init(void)
172 kirkwood_i2c_init(); 177 kirkwood_i2c_init();
173 178
174 if (machine_is_openrd_client() || machine_is_openrd_ultimate()) { 179 if (machine_is_openrd_client() || machine_is_openrd_ultimate()) {
180 platform_device_register(&openrd_client_audio_device);
175 i2c_register_board_info(0, i2c_board_info, 181 i2c_register_board_info(0, i2c_board_info,
176 ARRAY_SIZE(i2c_board_info)); 182 ARRAY_SIZE(i2c_board_info));
177 kirkwood_audio_init(); 183 kirkwood_audio_init();
diff --git a/arch/arm/mach-kirkwood/t5325-setup.c b/arch/arm/mach-kirkwood/t5325-setup.c
index 966b2b3bb813..f9d2a11b7f96 100644
--- a/arch/arm/mach-kirkwood/t5325-setup.c
+++ b/arch/arm/mach-kirkwood/t5325-setup.c
@@ -106,6 +106,11 @@ static struct platform_device hp_t5325_button_device = {
106 } 106 }
107}; 107};
108 108
109static struct platform_device hp_t5325_audio_device = {
110 .name = "t5325-audio",
111 .id = -1,
112};
113
109static unsigned int hp_t5325_mpp_config[] __initdata = { 114static unsigned int hp_t5325_mpp_config[] __initdata = {
110 MPP0_NF_IO2, 115 MPP0_NF_IO2,
111 MPP1_SPI_MOSI, 116 MPP1_SPI_MOSI,
@@ -179,6 +184,7 @@ static void __init hp_t5325_init(void)
179 kirkwood_sata_init(&hp_t5325_sata_data); 184 kirkwood_sata_init(&hp_t5325_sata_data);
180 kirkwood_ehci_init(); 185 kirkwood_ehci_init();
181 platform_device_register(&hp_t5325_button_device); 186 platform_device_register(&hp_t5325_button_device);
187 platform_device_register(&hp_t5325_audio_device);
182 188
183 i2c_register_board_info(0, i2c_board_info, ARRAY_SIZE(i2c_board_info)); 189 i2c_register_board_info(0, i2c_board_info, ARRAY_SIZE(i2c_board_info));
184 kirkwood_audio_init(); 190 kirkwood_audio_init();
diff --git a/arch/arm/mach-ks8695/leds.c b/arch/arm/mach-ks8695/leds.c
index d6f6502ac9b5..4bd707547293 100644
--- a/arch/arm/mach-ks8695/leds.c
+++ b/arch/arm/mach-ks8695/leds.c
@@ -11,7 +11,6 @@
11#include <linux/kernel.h> 11#include <linux/kernel.h>
12#include <linux/module.h> 12#include <linux/module.h>
13#include <linux/init.h> 13#include <linux/init.h>
14#include <linux/gpio.h>
15 14
16#include <asm/leds.h> 15#include <asm/leds.h>
17#include <mach/devices.h> 16#include <mach/devices.h>
diff --git a/arch/arm/mach-lpc32xx/include/mach/irqs.h b/arch/arm/mach-lpc32xx/include/mach/irqs.h
index 2667f52e3b04..9e3b90df32e1 100644
--- a/arch/arm/mach-lpc32xx/include/mach/irqs.h
+++ b/arch/arm/mach-lpc32xx/include/mach/irqs.h
@@ -61,7 +61,7 @@
61 */ 61 */
62#define IRQ_LPC32XX_JTAG_COMM_TX LPC32XX_SIC1_IRQ(1) 62#define IRQ_LPC32XX_JTAG_COMM_TX LPC32XX_SIC1_IRQ(1)
63#define IRQ_LPC32XX_JTAG_COMM_RX LPC32XX_SIC1_IRQ(2) 63#define IRQ_LPC32XX_JTAG_COMM_RX LPC32XX_SIC1_IRQ(2)
64#define IRQ_LPC32XX_GPI_11 LPC32XX_SIC1_IRQ(4) 64#define IRQ_LPC32XX_GPI_28 LPC32XX_SIC1_IRQ(4)
65#define IRQ_LPC32XX_TS_P LPC32XX_SIC1_IRQ(6) 65#define IRQ_LPC32XX_TS_P LPC32XX_SIC1_IRQ(6)
66#define IRQ_LPC32XX_TS_IRQ LPC32XX_SIC1_IRQ(7) 66#define IRQ_LPC32XX_TS_IRQ LPC32XX_SIC1_IRQ(7)
67#define IRQ_LPC32XX_TS_AUX LPC32XX_SIC1_IRQ(8) 67#define IRQ_LPC32XX_TS_AUX LPC32XX_SIC1_IRQ(8)
diff --git a/arch/arm/mach-lpc32xx/irq.c b/arch/arm/mach-lpc32xx/irq.c
index 4eae566dfdc7..c74de01ab5b6 100644
--- a/arch/arm/mach-lpc32xx/irq.c
+++ b/arch/arm/mach-lpc32xx/irq.c
@@ -118,6 +118,10 @@ static const struct lpc32xx_event_info lpc32xx_events[NR_IRQS] = {
118 .event_group = &lpc32xx_event_pin_regs, 118 .event_group = &lpc32xx_event_pin_regs,
119 .mask = LPC32XX_CLKPWR_EXTSRC_GPI_06_BIT, 119 .mask = LPC32XX_CLKPWR_EXTSRC_GPI_06_BIT,
120 }, 120 },
121 [IRQ_LPC32XX_GPI_28] = {
122 .event_group = &lpc32xx_event_pin_regs,
123 .mask = LPC32XX_CLKPWR_EXTSRC_GPI_28_BIT,
124 },
121 [IRQ_LPC32XX_GPIO_00] = { 125 [IRQ_LPC32XX_GPIO_00] = {
122 .event_group = &lpc32xx_event_int_regs, 126 .event_group = &lpc32xx_event_int_regs,
123 .mask = LPC32XX_CLKPWR_INTSRC_GPIO_00_BIT, 127 .mask = LPC32XX_CLKPWR_INTSRC_GPIO_00_BIT,
@@ -305,9 +309,18 @@ static int lpc32xx_irq_wake(struct irq_data *d, unsigned int state)
305 309
306 if (state) 310 if (state)
307 eventreg |= lpc32xx_events[d->irq].mask; 311 eventreg |= lpc32xx_events[d->irq].mask;
308 else 312 else {
309 eventreg &= ~lpc32xx_events[d->irq].mask; 313 eventreg &= ~lpc32xx_events[d->irq].mask;
310 314
315 /*
316 * When disabling the wakeup, clear the latched
317 * event
318 */
319 __raw_writel(lpc32xx_events[d->irq].mask,
320 lpc32xx_events[d->irq].
321 event_group->rawstat_reg);
322 }
323
311 __raw_writel(eventreg, 324 __raw_writel(eventreg,
312 lpc32xx_events[d->irq].event_group->enab_reg); 325 lpc32xx_events[d->irq].event_group->enab_reg);
313 326
@@ -380,13 +393,15 @@ void __init lpc32xx_init_irq(void)
380 393
381 /* Setup SIC1 */ 394 /* Setup SIC1 */
382 __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC1_BASE)); 395 __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC1_BASE));
383 __raw_writel(MIC_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC1_BASE)); 396 __raw_writel(SIC1_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC1_BASE));
384 __raw_writel(MIC_ATR_DEFAULT, LPC32XX_INTC_ACT_TYPE(LPC32XX_SIC1_BASE)); 397 __raw_writel(SIC1_ATR_DEFAULT,
398 LPC32XX_INTC_ACT_TYPE(LPC32XX_SIC1_BASE));
385 399
386 /* Setup SIC2 */ 400 /* Setup SIC2 */
387 __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC2_BASE)); 401 __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC2_BASE));
388 __raw_writel(MIC_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC2_BASE)); 402 __raw_writel(SIC2_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC2_BASE));
389 __raw_writel(MIC_ATR_DEFAULT, LPC32XX_INTC_ACT_TYPE(LPC32XX_SIC2_BASE)); 403 __raw_writel(SIC2_ATR_DEFAULT,
404 LPC32XX_INTC_ACT_TYPE(LPC32XX_SIC2_BASE));
390 405
391 /* Configure supported IRQ's */ 406 /* Configure supported IRQ's */
392 for (i = 0; i < NR_IRQS; i++) { 407 for (i = 0; i < NR_IRQS; i++) {
diff --git a/arch/arm/mach-lpc32xx/serial.c b/arch/arm/mach-lpc32xx/serial.c
index 429cfdbb2b3d..f2735281616a 100644
--- a/arch/arm/mach-lpc32xx/serial.c
+++ b/arch/arm/mach-lpc32xx/serial.c
@@ -88,6 +88,7 @@ struct uartinit {
88 char *uart_ck_name; 88 char *uart_ck_name;
89 u32 ck_mode_mask; 89 u32 ck_mode_mask;
90 void __iomem *pdiv_clk_reg; 90 void __iomem *pdiv_clk_reg;
91 resource_size_t mapbase;
91}; 92};
92 93
93static struct uartinit uartinit_data[] __initdata = { 94static struct uartinit uartinit_data[] __initdata = {
@@ -97,6 +98,7 @@ static struct uartinit uartinit_data[] __initdata = {
97 .ck_mode_mask = 98 .ck_mode_mask =
98 LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 5), 99 LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 5),
99 .pdiv_clk_reg = LPC32XX_CLKPWR_UART5_CLK_CTRL, 100 .pdiv_clk_reg = LPC32XX_CLKPWR_UART5_CLK_CTRL,
101 .mapbase = LPC32XX_UART5_BASE,
100 }, 102 },
101#endif 103#endif
102#ifdef CONFIG_ARCH_LPC32XX_UART3_SELECT 104#ifdef CONFIG_ARCH_LPC32XX_UART3_SELECT
@@ -105,6 +107,7 @@ static struct uartinit uartinit_data[] __initdata = {
105 .ck_mode_mask = 107 .ck_mode_mask =
106 LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 3), 108 LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 3),
107 .pdiv_clk_reg = LPC32XX_CLKPWR_UART3_CLK_CTRL, 109 .pdiv_clk_reg = LPC32XX_CLKPWR_UART3_CLK_CTRL,
110 .mapbase = LPC32XX_UART3_BASE,
108 }, 111 },
109#endif 112#endif
110#ifdef CONFIG_ARCH_LPC32XX_UART4_SELECT 113#ifdef CONFIG_ARCH_LPC32XX_UART4_SELECT
@@ -113,6 +116,7 @@ static struct uartinit uartinit_data[] __initdata = {
113 .ck_mode_mask = 116 .ck_mode_mask =
114 LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 4), 117 LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 4),
115 .pdiv_clk_reg = LPC32XX_CLKPWR_UART4_CLK_CTRL, 118 .pdiv_clk_reg = LPC32XX_CLKPWR_UART4_CLK_CTRL,
119 .mapbase = LPC32XX_UART4_BASE,
116 }, 120 },
117#endif 121#endif
118#ifdef CONFIG_ARCH_LPC32XX_UART6_SELECT 122#ifdef CONFIG_ARCH_LPC32XX_UART6_SELECT
@@ -121,6 +125,7 @@ static struct uartinit uartinit_data[] __initdata = {
121 .ck_mode_mask = 125 .ck_mode_mask =
122 LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 6), 126 LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 6),
123 .pdiv_clk_reg = LPC32XX_CLKPWR_UART6_CLK_CTRL, 127 .pdiv_clk_reg = LPC32XX_CLKPWR_UART6_CLK_CTRL,
128 .mapbase = LPC32XX_UART6_BASE,
124 }, 129 },
125#endif 130#endif
126}; 131};
@@ -165,11 +170,24 @@ void __init lpc32xx_serial_init(void)
165 170
166 /* pre-UART clock divider set to 1 */ 171 /* pre-UART clock divider set to 1 */
167 __raw_writel(0x0101, uartinit_data[i].pdiv_clk_reg); 172 __raw_writel(0x0101, uartinit_data[i].pdiv_clk_reg);
173
174 /*
175 * Force a flush of the RX FIFOs to work around a
176 * HW bug
177 */
178 puart = uartinit_data[i].mapbase;
179 __raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart));
180 __raw_writel(0x00, LPC32XX_UART_DLL_FIFO(puart));
181 j = LPC32XX_SUART_FIFO_SIZE;
182 while (j--)
183 tmp = __raw_readl(
184 LPC32XX_UART_DLL_FIFO(puart));
185 __raw_writel(0, LPC32XX_UART_IIR_FCR(puart));
168 } 186 }
169 187
170 /* This needs to be done after all UART clocks are setup */ 188 /* This needs to be done after all UART clocks are setup */
171 __raw_writel(clkmodes, LPC32XX_UARTCTL_CLKMODE); 189 __raw_writel(clkmodes, LPC32XX_UARTCTL_CLKMODE);
172 for (i = 0; i < ARRAY_SIZE(uartinit_data) - 1; i++) { 190 for (i = 0; i < ARRAY_SIZE(uartinit_data); i++) {
173 /* Force a flush of the RX FIFOs to work around a HW bug */ 191 /* Force a flush of the RX FIFOs to work around a HW bug */
174 puart = serial_std_platform_data[i].mapbase; 192 puart = serial_std_platform_data[i].mapbase;
175 __raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart)); 193 __raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart));
diff --git a/arch/arm/mach-mmp/aspenite.c b/arch/arm/mach-mmp/aspenite.c
index 17cb76060125..3588a5584153 100644
--- a/arch/arm/mach-mmp/aspenite.c
+++ b/arch/arm/mach-mmp/aspenite.c
@@ -17,7 +17,6 @@
17#include <linux/mtd/partitions.h> 17#include <linux/mtd/partitions.h>
18#include <linux/mtd/nand.h> 18#include <linux/mtd/nand.h>
19#include <linux/interrupt.h> 19#include <linux/interrupt.h>
20#include <linux/gpio.h>
21 20
22#include <asm/mach-types.h> 21#include <asm/mach-types.h>
23#include <asm/mach/arch.h> 22#include <asm/mach/arch.h>
diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c
index 7bc17eaa12eb..ada1213982b4 100644
--- a/arch/arm/mach-mmp/pxa168.c
+++ b/arch/arm/mach-mmp/pxa168.c
@@ -24,7 +24,6 @@
24#include <mach/dma.h> 24#include <mach/dma.h>
25#include <mach/devices.h> 25#include <mach/devices.h>
26#include <mach/mfp.h> 26#include <mach/mfp.h>
27#include <linux/platform_device.h>
28#include <linux/dma-mapping.h> 27#include <linux/dma-mapping.h>
29#include <mach/pxa168.h> 28#include <mach/pxa168.h>
30 29
diff --git a/arch/arm/mach-mmp/tavorevb.c b/arch/arm/mach-mmp/tavorevb.c
index 8e3b5af04a57..bc97170125bf 100644
--- a/arch/arm/mach-mmp/tavorevb.c
+++ b/arch/arm/mach-mmp/tavorevb.c
@@ -12,7 +12,6 @@
12#include <linux/kernel.h> 12#include <linux/kernel.h>
13#include <linux/platform_device.h> 13#include <linux/platform_device.h>
14#include <linux/smc91x.h> 14#include <linux/smc91x.h>
15#include <linux/gpio.h>
16 15
17#include <asm/mach-types.h> 16#include <asm/mach-types.h>
18#include <asm/mach/arch.h> 17#include <asm/mach/arch.h>
diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c
index 0a113424632c..962e71169750 100644
--- a/arch/arm/mach-msm/board-msm8x60.c
+++ b/arch/arm/mach-msm/board-msm8x60.c
@@ -80,12 +80,8 @@ static struct of_device_id msm_dt_gic_match[] __initdata = {
80 80
81static void __init msm8x60_dt_init(void) 81static void __init msm8x60_dt_init(void)
82{ 82{
83 struct device_node *node; 83 irq_domain_generate_simple(msm_dt_gic_match, MSM8X60_QGIC_DIST_PHYS,
84 84 GIC_SPI_START);
85 node = of_find_matching_node_by_address(NULL, msm_dt_gic_match,
86 MSM8X60_QGIC_DIST_PHYS);
87 if (node)
88 irq_domain_add_simple(node, GIC_SPI_START);
89 85
90 if (of_machine_is_compatible("qcom,msm8660-surf")) { 86 if (of_machine_is_compatible("qcom,msm8660-surf")) {
91 printk(KERN_INFO "Init surf UART registers\n"); 87 printk(KERN_INFO "Init surf UART registers\n");
diff --git a/arch/arm/mach-msm/hotplug.c b/arch/arm/mach-msm/hotplug.c
index 41c252de0215..a446fc14221f 100644
--- a/arch/arm/mach-msm/hotplug.c
+++ b/arch/arm/mach-msm/hotplug.c
@@ -11,6 +11,7 @@
11#include <linux/smp.h> 11#include <linux/smp.h>
12 12
13#include <asm/cacheflush.h> 13#include <asm/cacheflush.h>
14#include <asm/smp_plat.h>
14 15
15extern volatile int pen_release; 16extern volatile int pen_release;
16 17
diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-msm/platsmp.c
index 0b3e357c4c8c..db0117ec55f4 100644
--- a/arch/arm/mach-msm/platsmp.c
+++ b/arch/arm/mach-msm/platsmp.c
@@ -20,6 +20,7 @@
20#include <asm/cacheflush.h> 20#include <asm/cacheflush.h>
21#include <asm/cputype.h> 21#include <asm/cputype.h>
22#include <asm/mach-types.h> 22#include <asm/mach-types.h>
23#include <asm/smp_plat.h>
23 24
24#include <mach/msm_iomap.h> 25#include <mach/msm_iomap.h>
25 26
diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c
index 0cdd41004ad0..a5dcf766a3f9 100644
--- a/arch/arm/mach-mv78xx0/common.c
+++ b/arch/arm/mach-mv78xx0/common.c
@@ -19,6 +19,7 @@
19#include <mach/mv78xx0.h> 19#include <mach/mv78xx0.h>
20#include <mach/bridge-regs.h> 20#include <mach/bridge-regs.h>
21#include <plat/cache-feroceon-l2.h> 21#include <plat/cache-feroceon-l2.h>
22#include <plat/ehci-orion.h>
22#include <plat/orion_nand.h> 23#include <plat/orion_nand.h>
23#include <plat/time.h> 24#include <plat/time.h>
24#include <plat/common.h> 25#include <plat/common.h>
@@ -169,7 +170,7 @@ void __init mv78xx0_map_io(void)
169 ****************************************************************************/ 170 ****************************************************************************/
170void __init mv78xx0_ehci0_init(void) 171void __init mv78xx0_ehci0_init(void)
171{ 172{
172 orion_ehci_init(USB0_PHYS_BASE, IRQ_MV78XX0_USB_0); 173 orion_ehci_init(USB0_PHYS_BASE, IRQ_MV78XX0_USB_0, EHCI_PHY_NA);
173} 174}
174 175
175 176
diff --git a/arch/arm/mach-mv78xx0/mpp.h b/arch/arm/mach-mv78xx0/mpp.h
index b61b50927123..3752302ae2ee 100644
--- a/arch/arm/mach-mv78xx0/mpp.h
+++ b/arch/arm/mach-mv78xx0/mpp.h
@@ -24,296 +24,296 @@
24#define MPP_78100_A0_MASK MPP(0, 0x0, 0, 0, 1) 24#define MPP_78100_A0_MASK MPP(0, 0x0, 0, 0, 1)
25 25
26#define MPP0_GPIO MPP(0, 0x0, 1, 1, 1) 26#define MPP0_GPIO MPP(0, 0x0, 1, 1, 1)
27#define MPP0_GE0_COL MPP(0, 0x1, 1, 0, 1) 27#define MPP0_GE0_COL MPP(0, 0x1, 0, 0, 1)
28#define MPP0_GE1_TXCLK MPP(0, 0x2, 0, 1, 1) 28#define MPP0_GE1_TXCLK MPP(0, 0x2, 0, 0, 1)
29#define MPP0_UNUSED MPP(0, 0x3, 0, 0, 1) 29#define MPP0_UNUSED MPP(0, 0x3, 0, 0, 1)
30 30
31#define MPP1_GPIO MPP(1, 0x0, 1, 1, 1) 31#define MPP1_GPIO MPP(1, 0x0, 1, 1, 1)
32#define MPP1_GE0_RXERR MPP(1, 0x1, 1, 0, 1) 32#define MPP1_GE0_RXERR MPP(1, 0x1, 0, 0, 1)
33#define MPP1_GE1_TXCTL MPP(1, 0x2, 0, 1, 1) 33#define MPP1_GE1_TXCTL MPP(1, 0x2, 0, 0, 1)
34#define MPP1_UNUSED MPP(1, 0x3, 0, 0, 1) 34#define MPP1_UNUSED MPP(1, 0x3, 0, 0, 1)
35 35
36#define MPP2_GPIO MPP(2, 0x0, 1, 1, 1) 36#define MPP2_GPIO MPP(2, 0x0, 1, 1, 1)
37#define MPP2_GE0_CRS MPP(2, 0x1, 1, 0, 1) 37#define MPP2_GE0_CRS MPP(2, 0x1, 0, 0, 1)
38#define MPP2_GE1_RXCTL MPP(2, 0x2, 1, 0, 1) 38#define MPP2_GE1_RXCTL MPP(2, 0x2, 0, 0, 1)
39#define MPP2_UNUSED MPP(2, 0x3, 0, 0, 1) 39#define MPP2_UNUSED MPP(2, 0x3, 0, 0, 1)
40 40
41#define MPP3_GPIO MPP(3, 0x0, 1, 1, 1) 41#define MPP3_GPIO MPP(3, 0x0, 1, 1, 1)
42#define MPP3_GE0_TXERR MPP(3, 0x1, 0, 1, 1) 42#define MPP3_GE0_TXERR MPP(3, 0x1, 0, 0, 1)
43#define MPP3_GE1_RXCLK MPP(3, 0x2, 1, 0, 1) 43#define MPP3_GE1_RXCLK MPP(3, 0x2, 0, 0, 1)
44#define MPP3_UNUSED MPP(3, 0x3, 0, 0, 1) 44#define MPP3_UNUSED MPP(3, 0x3, 0, 0, 1)
45 45
46#define MPP4_GPIO MPP(4, 0x0, 1, 1, 1) 46#define MPP4_GPIO MPP(4, 0x0, 1, 1, 1)
47#define MPP4_GE0_TXD4 MPP(4, 0x1, 0, 1, 1) 47#define MPP4_GE0_TXD4 MPP(4, 0x1, 0, 0, 1)
48#define MPP4_GE1_TXD0 MPP(4, 0x2, 0, 1, 1) 48#define MPP4_GE1_TXD0 MPP(4, 0x2, 0, 0, 1)
49#define MPP4_UNUSED MPP(4, 0x3, 0, 0, 1) 49#define MPP4_UNUSED MPP(4, 0x3, 0, 0, 1)
50 50
51#define MPP5_GPIO MPP(5, 0x0, 1, 1, 1) 51#define MPP5_GPIO MPP(5, 0x0, 1, 1, 1)
52#define MPP5_GE0_TXD5 MPP(5, 0x1, 0, 1, 1) 52#define MPP5_GE0_TXD5 MPP(5, 0x1, 0, 0, 1)
53#define MPP5_GE1_TXD1 MPP(5, 0x2, 0, 1, 1) 53#define MPP5_GE1_TXD1 MPP(5, 0x2, 0, 0, 1)
54#define MPP5_UNUSED MPP(5, 0x3, 0, 0, 1) 54#define MPP5_UNUSED MPP(5, 0x3, 0, 0, 1)
55 55
56#define MPP6_GPIO MPP(6, 0x0, 1, 1, 1) 56#define MPP6_GPIO MPP(6, 0x0, 1, 1, 1)
57#define MPP6_GE0_TXD6 MPP(6, 0x1, 0, 1, 1) 57#define MPP6_GE0_TXD6 MPP(6, 0x1, 0, 0, 1)
58#define MPP6_GE1_TXD2 MPP(6, 0x2, 0, 1, 1) 58#define MPP6_GE1_TXD2 MPP(6, 0x2, 0, 0, 1)
59#define MPP6_UNUSED MPP(6, 0x3, 0, 0, 1) 59#define MPP6_UNUSED MPP(6, 0x3, 0, 0, 1)
60 60
61#define MPP7_GPIO MPP(7, 0x0, 1, 1, 1) 61#define MPP7_GPIO MPP(7, 0x0, 1, 1, 1)
62#define MPP7_GE0_TXD7 MPP(7, 0x1, 0, 1, 1) 62#define MPP7_GE0_TXD7 MPP(7, 0x1, 0, 0, 1)
63#define MPP7_GE1_TXD3 MPP(7, 0x2, 0, 1, 1) 63#define MPP7_GE1_TXD3 MPP(7, 0x2, 0, 0, 1)
64#define MPP7_UNUSED MPP(7, 0x3, 0, 0, 1) 64#define MPP7_UNUSED MPP(7, 0x3, 0, 0, 1)
65 65
66#define MPP8_GPIO MPP(8, 0x0, 1, 1, 1) 66#define MPP8_GPIO MPP(8, 0x0, 1, 1, 1)
67#define MPP8_GE0_RXD4 MPP(8, 0x1, 1, 0, 1) 67#define MPP8_GE0_RXD4 MPP(8, 0x1, 0, 0, 1)
68#define MPP8_GE1_RXD0 MPP(8, 0x2, 1, 0, 1) 68#define MPP8_GE1_RXD0 MPP(8, 0x2, 0, 0, 1)
69#define MPP8_UNUSED MPP(8, 0x3, 0, 0, 1) 69#define MPP8_UNUSED MPP(8, 0x3, 0, 0, 1)
70 70
71#define MPP9_GPIO MPP(9, 0x0, 1, 1, 1) 71#define MPP9_GPIO MPP(9, 0x0, 1, 1, 1)
72#define MPP9_GE0_RXD5 MPP(9, 0x1, 1, 0, 1) 72#define MPP9_GE0_RXD5 MPP(9, 0x1, 0, 0, 1)
73#define MPP9_GE1_RXD1 MPP(9, 0x2, 1, 0, 1) 73#define MPP9_GE1_RXD1 MPP(9, 0x2, 0, 0, 1)
74#define MPP9_UNUSED MPP(9, 0x3, 0, 0, 1) 74#define MPP9_UNUSED MPP(9, 0x3, 0, 0, 1)
75 75
76#define MPP10_GPIO MPP(10, 0x0, 1, 1, 1) 76#define MPP10_GPIO MPP(10, 0x0, 1, 1, 1)
77#define MPP10_GE0_RXD6 MPP(10, 0x1, 1, 0, 1) 77#define MPP10_GE0_RXD6 MPP(10, 0x1, 0, 0, 1)
78#define MPP10_GE1_RXD2 MPP(10, 0x2, 1, 0, 1) 78#define MPP10_GE1_RXD2 MPP(10, 0x2, 0, 0, 1)
79#define MPP10_UNUSED MPP(10, 0x3, 0, 0, 1) 79#define MPP10_UNUSED MPP(10, 0x3, 0, 0, 1)
80 80
81#define MPP11_GPIO MPP(11, 0x0, 1, 1, 1) 81#define MPP11_GPIO MPP(11, 0x0, 1, 1, 1)
82#define MPP11_GE0_RXD7 MPP(11, 0x1, 1, 0, 1) 82#define MPP11_GE0_RXD7 MPP(11, 0x1, 0, 0, 1)
83#define MPP11_GE1_RXD3 MPP(11, 0x2, 1, 0, 1) 83#define MPP11_GE1_RXD3 MPP(11, 0x2, 0, 0, 1)
84#define MPP11_UNUSED MPP(11, 0x3, 0, 0, 1) 84#define MPP11_UNUSED MPP(11, 0x3, 0, 0, 1)
85 85
86#define MPP12_GPIO MPP(12, 0x0, 1, 1, 1) 86#define MPP12_GPIO MPP(12, 0x0, 1, 1, 1)
87#define MPP12_M_BB MPP(12, 0x3, 1, 0, 1) 87#define MPP12_M_BB MPP(12, 0x3, 0, 0, 1)
88#define MPP12_UA0_CTSn MPP(12, 0x4, 1, 0, 1) 88#define MPP12_UA0_CTSn MPP(12, 0x4, 0, 0, 1)
89#define MPP12_NAND_FLASH_REn0 MPP(12, 0x5, 0, 1, 1) 89#define MPP12_NAND_FLASH_REn0 MPP(12, 0x5, 0, 0, 1)
90#define MPP12_TDM0_SCSn MPP(12, 0X6, 0, 1, 1) 90#define MPP12_TDM0_SCSn MPP(12, 0X6, 0, 0, 1)
91#define MPP12_UNUSED MPP(12, 0x1, 0, 0, 1) 91#define MPP12_UNUSED MPP(12, 0x1, 0, 0, 1)
92 92
93#define MPP13_GPIO MPP(13, 0x0, 1, 1, 1) 93#define MPP13_GPIO MPP(13, 0x0, 1, 1, 1)
94#define MPP13_SYSRST_OUTn MPP(13, 0x3, 0, 1, 1) 94#define MPP13_SYSRST_OUTn MPP(13, 0x3, 0, 0, 1)
95#define MPP13_UA0_RTSn MPP(13, 0x4, 0, 1, 1) 95#define MPP13_UA0_RTSn MPP(13, 0x4, 0, 0, 1)
96#define MPP13_NAN_FLASH_WEn0 MPP(13, 0x5, 0, 1, 1) 96#define MPP13_NAN_FLASH_WEn0 MPP(13, 0x5, 0, 0, 1)
97#define MPP13_TDM_SCLK MPP(13, 0x6, 0, 1, 1) 97#define MPP13_TDM_SCLK MPP(13, 0x6, 0, 0, 1)
98#define MPP13_UNUSED MPP(13, 0x1, 0, 0, 1) 98#define MPP13_UNUSED MPP(13, 0x1, 0, 0, 1)
99 99
100#define MPP14_GPIO MPP(14, 0x0, 1, 1, 1) 100#define MPP14_GPIO MPP(14, 0x0, 1, 1, 1)
101#define MPP14_SATA1_ACTn MPP(14, 0x3, 0, 1, 1) 101#define MPP14_SATA1_ACTn MPP(14, 0x3, 0, 0, 1)
102#define MPP14_UA1_CTSn MPP(14, 0x4, 1, 0, 1) 102#define MPP14_UA1_CTSn MPP(14, 0x4, 0, 0, 1)
103#define MPP14_NAND_FLASH_REn1 MPP(14, 0x5, 0, 1, 1) 103#define MPP14_NAND_FLASH_REn1 MPP(14, 0x5, 0, 0, 1)
104#define MPP14_TDM_SMOSI MPP(14, 0x6, 0, 1, 1) 104#define MPP14_TDM_SMOSI MPP(14, 0x6, 0, 0, 1)
105#define MPP14_UNUSED MPP(14, 0x1, 0, 0, 1) 105#define MPP14_UNUSED MPP(14, 0x1, 0, 0, 1)
106 106
107#define MPP15_GPIO MPP(15, 0x0, 1, 1, 1) 107#define MPP15_GPIO MPP(15, 0x0, 1, 1, 1)
108#define MPP15_SATA0_ACTn MPP(15, 0x3, 0, 1, 1) 108#define MPP15_SATA0_ACTn MPP(15, 0x3, 0, 0, 1)
109#define MPP15_UA1_RTSn MPP(15, 0x4, 0, 1, 1) 109#define MPP15_UA1_RTSn MPP(15, 0x4, 0, 0, 1)
110#define MPP15_NAND_FLASH_WEn1 MPP(15, 0x5, 0, 1, 1) 110#define MPP15_NAND_FLASH_WEn1 MPP(15, 0x5, 0, 0, 1)
111#define MPP15_TDM_SMISO MPP(15, 0x6, 1, 0, 1) 111#define MPP15_TDM_SMISO MPP(15, 0x6, 0, 0, 1)
112#define MPP15_UNUSED MPP(15, 0x1, 0, 0, 1) 112#define MPP15_UNUSED MPP(15, 0x1, 0, 0, 1)
113 113
114#define MPP16_GPIO MPP(16, 0x0, 1, 1, 1) 114#define MPP16_GPIO MPP(16, 0x0, 1, 1, 1)
115#define MPP16_SATA1_PRESENTn MPP(16, 0x3, 0, 1, 1) 115#define MPP16_SATA1_PRESENTn MPP(16, 0x3, 0, 0, 1)
116#define MPP16_UA2_TXD MPP(16, 0x4, 0, 1, 1) 116#define MPP16_UA2_TXD MPP(16, 0x4, 0, 0, 1)
117#define MPP16_NAND_FLASH_REn3 MPP(16, 0x5, 0, 1, 1) 117#define MPP16_NAND_FLASH_REn3 MPP(16, 0x5, 0, 0, 1)
118#define MPP16_TDM_INTn MPP(16, 0x6, 1, 0, 1) 118#define MPP16_TDM_INTn MPP(16, 0x6, 0, 0, 1)
119#define MPP16_UNUSED MPP(16, 0x1, 0, 0, 1) 119#define MPP16_UNUSED MPP(16, 0x1, 0, 0, 1)
120 120
121 121
122#define MPP17_GPIO MPP(17, 0x0, 1, 1, 1) 122#define MPP17_GPIO MPP(17, 0x0, 1, 1, 1)
123#define MPP17_SATA0_PRESENTn MPP(17, 0x3, 0, 1, 1) 123#define MPP17_SATA0_PRESENTn MPP(17, 0x3, 0, 0, 1)
124#define MPP17_UA2_RXD MPP(17, 0x4, 1, 0, 1) 124#define MPP17_UA2_RXD MPP(17, 0x4, 0, 0, 1)
125#define MPP17_NAND_FLASH_WEn3 MPP(17, 0x5, 0, 1, 1) 125#define MPP17_NAND_FLASH_WEn3 MPP(17, 0x5, 0, 0, 1)
126#define MPP17_TDM_RSTn MPP(17, 0x6, 0, 1, 1) 126#define MPP17_TDM_RSTn MPP(17, 0x6, 0, 0, 1)
127#define MPP17_UNUSED MPP(17, 0x1, 0, 0, 1) 127#define MPP17_UNUSED MPP(17, 0x1, 0, 0, 1)
128 128
129 129
130#define MPP18_GPIO MPP(18, 0x0, 1, 1, 1) 130#define MPP18_GPIO MPP(18, 0x0, 1, 1, 1)
131#define MPP18_UA0_CTSn MPP(18, 0x4, 1, 0, 1) 131#define MPP18_UA0_CTSn MPP(18, 0x4, 0, 0, 1)
132#define MPP18_BOOT_FLASH_REn MPP(18, 0x5, 0, 1, 1) 132#define MPP18_BOOT_FLASH_REn MPP(18, 0x5, 0, 0, 1)
133#define MPP18_UNUSED MPP(18, 0x1, 0, 0, 1) 133#define MPP18_UNUSED MPP(18, 0x1, 0, 0, 1)
134 134
135 135
136 136
137#define MPP19_GPIO MPP(19, 0x0, 1, 1, 1) 137#define MPP19_GPIO MPP(19, 0x0, 1, 1, 1)
138#define MPP19_UA0_CTSn MPP(19, 0x4, 0, 1, 1) 138#define MPP19_UA0_CTSn MPP(19, 0x4, 0, 0, 1)
139#define MPP19_BOOT_FLASH_WEn MPP(19, 0x5, 0, 1, 1) 139#define MPP19_BOOT_FLASH_WEn MPP(19, 0x5, 0, 0, 1)
140#define MPP19_UNUSED MPP(19, 0x1, 0, 0, 1) 140#define MPP19_UNUSED MPP(19, 0x1, 0, 0, 1)
141 141
142 142
143#define MPP20_GPIO MPP(20, 0x0, 1, 1, 1) 143#define MPP20_GPIO MPP(20, 0x0, 1, 1, 1)
144#define MPP20_UA1_CTSs MPP(20, 0x4, 1, 0, 1) 144#define MPP20_UA1_CTSs MPP(20, 0x4, 0, 0, 1)
145#define MPP20_TDM_PCLK MPP(20, 0x6, 1, 1, 0) 145#define MPP20_TDM_PCLK MPP(20, 0x6, 0, 0, 0)
146#define MPP20_UNUSED MPP(20, 0x1, 0, 0, 1) 146#define MPP20_UNUSED MPP(20, 0x1, 0, 0, 1)
147 147
148 148
149 149
150#define MPP21_GPIO MPP(21, 0x0, 1, 1, 1) 150#define MPP21_GPIO MPP(21, 0x0, 1, 1, 1)
151#define MPP21_UA1_CTSs MPP(21, 0x4, 0, 1, 1) 151#define MPP21_UA1_CTSs MPP(21, 0x4, 0, 0, 1)
152#define MPP21_TDM_FSYNC MPP(21, 0x6, 1, 1, 0) 152#define MPP21_TDM_FSYNC MPP(21, 0x6, 0, 0, 0)
153#define MPP21_UNUSED MPP(21, 0x1, 0, 0, 1) 153#define MPP21_UNUSED MPP(21, 0x1, 0, 0, 1)
154 154
155 155
156 156
157#define MPP22_GPIO MPP(22, 0x0, 1, 1, 1) 157#define MPP22_GPIO MPP(22, 0x0, 1, 1, 1)
158#define MPP22_UA3_TDX MPP(22, 0x4, 0, 1, 1) 158#define MPP22_UA3_TDX MPP(22, 0x4, 0, 0, 1)
159#define MPP22_NAND_FLASH_REn2 MPP(22, 0x5, 0, 1, 1) 159#define MPP22_NAND_FLASH_REn2 MPP(22, 0x5, 0, 0, 1)
160#define MPP22_TDM_DRX MPP(22, 0x6, 1, 0, 1) 160#define MPP22_TDM_DRX MPP(22, 0x6, 0, 0, 1)
161#define MPP22_UNUSED MPP(22, 0x1, 0, 0, 1) 161#define MPP22_UNUSED MPP(22, 0x1, 0, 0, 1)
162 162
163 163
164 164
165#define MPP23_GPIO MPP(23, 0x0, 1, 1, 1) 165#define MPP23_GPIO MPP(23, 0x0, 1, 1, 1)
166#define MPP23_UA3_RDX MPP(23, 0x4, 1, 0, 1) 166#define MPP23_UA3_RDX MPP(23, 0x4, 0, 0, 1)
167#define MPP23_NAND_FLASH_WEn2 MPP(23, 0x5, 0, 1, 1) 167#define MPP23_NAND_FLASH_WEn2 MPP(23, 0x5, 0, 0, 1)
168#define MPP23_TDM_DTX MPP(23, 0x6, 0, 1, 1) 168#define MPP23_TDM_DTX MPP(23, 0x6, 0, 0, 1)
169#define MPP23_UNUSED MPP(23, 0x1, 0, 0, 1) 169#define MPP23_UNUSED MPP(23, 0x1, 0, 0, 1)
170 170
171 171
172#define MPP24_GPIO MPP(24, 0x0, 1, 1, 1) 172#define MPP24_GPIO MPP(24, 0x0, 1, 1, 1)
173#define MPP24_UA2_TXD MPP(24, 0x4, 0, 1, 1) 173#define MPP24_UA2_TXD MPP(24, 0x4, 0, 0, 1)
174#define MPP24_TDM_INTn MPP(24, 0x6, 1, 0, 1) 174#define MPP24_TDM_INTn MPP(24, 0x6, 0, 0, 1)
175#define MPP24_UNUSED MPP(24, 0x1, 0, 0, 1) 175#define MPP24_UNUSED MPP(24, 0x1, 0, 0, 1)
176 176
177 177
178#define MPP25_GPIO MPP(25, 0x0, 1, 1, 1) 178#define MPP25_GPIO MPP(25, 0x0, 1, 1, 1)
179#define MPP25_UA2_RXD MPP(25, 0x4, 1, 0, 1) 179#define MPP25_UA2_RXD MPP(25, 0x4, 0, 0, 1)
180#define MPP25_TDM_RSTn MPP(25, 0x6, 0, 1, 1) 180#define MPP25_TDM_RSTn MPP(25, 0x6, 0, 0, 1)
181#define MPP25_UNUSED MPP(25, 0x1, 0, 0, 1) 181#define MPP25_UNUSED MPP(25, 0x1, 0, 0, 1)
182 182
183 183
184#define MPP26_GPIO MPP(26, 0x0, 1, 1, 1) 184#define MPP26_GPIO MPP(26, 0x0, 1, 1, 1)
185#define MPP26_UA2_CTSn MPP(26, 0x4, 1, 0, 1) 185#define MPP26_UA2_CTSn MPP(26, 0x4, 0, 0, 1)
186#define MPP26_TDM_PCLK MPP(26, 0x6, 1, 1, 1) 186#define MPP26_TDM_PCLK MPP(26, 0x6, 0, 0, 1)
187#define MPP26_UNUSED MPP(26, 0x1, 0, 0, 1) 187#define MPP26_UNUSED MPP(26, 0x1, 0, 0, 1)
188 188
189 189
190#define MPP27_GPIO MPP(27, 0x0, 1, 1, 1) 190#define MPP27_GPIO MPP(27, 0x0, 1, 1, 1)
191#define MPP27_UA2_RTSn MPP(27, 0x4, 0, 1, 1) 191#define MPP27_UA2_RTSn MPP(27, 0x4, 0, 0, 1)
192#define MPP27_TDM_FSYNC MPP(27, 0x6, 1, 1, 1) 192#define MPP27_TDM_FSYNC MPP(27, 0x6, 0, 0, 1)
193#define MPP27_UNUSED MPP(27, 0x1, 0, 0, 1) 193#define MPP27_UNUSED MPP(27, 0x1, 0, 0, 1)
194 194
195 195
196#define MPP28_GPIO MPP(28, 0x0, 1, 1, 1) 196#define MPP28_GPIO MPP(28, 0x0, 1, 1, 1)
197#define MPP28_UA3_TXD MPP(28, 0x4, 0, 1, 1) 197#define MPP28_UA3_TXD MPP(28, 0x4, 0, 0, 1)
198#define MPP28_TDM_DRX MPP(28, 0x6, 1, 0, 1) 198#define MPP28_TDM_DRX MPP(28, 0x6, 0, 0, 1)
199#define MPP28_UNUSED MPP(28, 0x1, 0, 0, 1) 199#define MPP28_UNUSED MPP(28, 0x1, 0, 0, 1)
200 200
201#define MPP29_GPIO MPP(29, 0x0, 1, 1, 1) 201#define MPP29_GPIO MPP(29, 0x0, 1, 1, 1)
202#define MPP29_UA3_RXD MPP(29, 0x4, 1, 0, 1) 202#define MPP29_UA3_RXD MPP(29, 0x4, 0, 0, 1)
203#define MPP29_SYSRST_OUTn MPP(29, 0x5, 0, 1, 1) 203#define MPP29_SYSRST_OUTn MPP(29, 0x5, 0, 0, 1)
204#define MPP29_TDM_DTX MPP(29, 0x6, 0, 1, 1) 204#define MPP29_TDM_DTX MPP(29, 0x6, 0, 0, 1)
205#define MPP29_UNUSED MPP(29, 0x1, 0, 0, 1) 205#define MPP29_UNUSED MPP(29, 0x1, 0, 0, 1)
206 206
207#define MPP30_GPIO MPP(30, 0x0, 1, 1, 1) 207#define MPP30_GPIO MPP(30, 0x0, 1, 1, 1)
208#define MPP30_UA3_CTSn MPP(30, 0x4, 1, 0, 1) 208#define MPP30_UA3_CTSn MPP(30, 0x4, 0, 0, 1)
209#define MPP30_UNUSED MPP(30, 0x1, 0, 0, 1) 209#define MPP30_UNUSED MPP(30, 0x1, 0, 0, 1)
210 210
211#define MPP31_GPIO MPP(31, 0x0, 1, 1, 1) 211#define MPP31_GPIO MPP(31, 0x0, 1, 1, 1)
212#define MPP31_UA3_RTSn MPP(31, 0x4, 0, 1, 1) 212#define MPP31_UA3_RTSn MPP(31, 0x4, 0, 0, 1)
213#define MPP31_TDM1_SCSn MPP(31, 0x6, 0, 1, 1) 213#define MPP31_TDM1_SCSn MPP(31, 0x6, 0, 0, 1)
214#define MPP31_UNUSED MPP(31, 0x1, 0, 0, 1) 214#define MPP31_UNUSED MPP(31, 0x1, 0, 0, 1)
215 215
216 216
217#define MPP32_GPIO MPP(32, 0x1, 1, 1, 1) 217#define MPP32_GPIO MPP(32, 0x1, 1, 1, 1)
218#define MPP32_UA3_TDX MPP(32, 0x4, 0, 1, 1) 218#define MPP32_UA3_TDX MPP(32, 0x4, 0, 0, 1)
219#define MPP32_SYSRST_OUTn MPP(32, 0x5, 0, 1, 1) 219#define MPP32_SYSRST_OUTn MPP(32, 0x5, 0, 0, 1)
220#define MPP32_TDM0_RXQ MPP(32, 0x6, 0, 1, 1) 220#define MPP32_TDM0_RXQ MPP(32, 0x6, 0, 0, 1)
221#define MPP32_UNUSED MPP(32, 0x3, 0, 0, 1) 221#define MPP32_UNUSED MPP(32, 0x3, 0, 0, 1)
222 222
223 223
224#define MPP33_GPIO MPP(33, 0x1, 1, 1, 1) 224#define MPP33_GPIO MPP(33, 0x1, 1, 1, 1)
225#define MPP33_UA3_RDX MPP(33, 0x4, 1, 0, 1) 225#define MPP33_UA3_RDX MPP(33, 0x4, 0, 0, 1)
226#define MPP33_TDM0_TXQ MPP(33, 0x6, 0, 1, 1) 226#define MPP33_TDM0_TXQ MPP(33, 0x6, 0, 0, 1)
227#define MPP33_UNUSED MPP(33, 0x3, 0, 0, 1) 227#define MPP33_UNUSED MPP(33, 0x3, 0, 0, 1)
228 228
229 229
230 230
231#define MPP34_GPIO MPP(34, 0x1, 1, 1, 1) 231#define MPP34_GPIO MPP(34, 0x1, 1, 1, 1)
232#define MPP34_UA2_TDX MPP(34, 0x4, 0, 1, 1) 232#define MPP34_UA2_TDX MPP(34, 0x4, 0, 0, 1)
233#define MPP34_TDM1_RXQ MPP(34, 0x6, 0, 1, 1) 233#define MPP34_TDM1_RXQ MPP(34, 0x6, 0, 0, 1)
234#define MPP34_UNUSED MPP(34, 0x3, 0, 0, 1) 234#define MPP34_UNUSED MPP(34, 0x3, 0, 0, 1)
235 235
236 236
237 237
238#define MPP35_GPIO MPP(35, 0x1, 1, 1, 1) 238#define MPP35_GPIO MPP(35, 0x1, 1, 1, 1)
239#define MPP35_UA2_RDX MPP(35, 0x4, 1, 0, 1) 239#define MPP35_UA2_RDX MPP(35, 0x4, 0, 0, 1)
240#define MPP35_TDM1_TXQ MPP(35, 0x6, 0, 1, 1) 240#define MPP35_TDM1_TXQ MPP(35, 0x6, 0, 0, 1)
241#define MPP35_UNUSED MPP(35, 0x3, 0, 0, 1) 241#define MPP35_UNUSED MPP(35, 0x3, 0, 0, 1)
242 242
243#define MPP36_GPIO MPP(36, 0x1, 1, 1, 1) 243#define MPP36_GPIO MPP(36, 0x1, 1, 1, 1)
244#define MPP36_UA0_CTSn MPP(36, 0x2, 1, 0, 1) 244#define MPP36_UA0_CTSn MPP(36, 0x2, 0, 0, 1)
245#define MPP36_UA2_TDX MPP(36, 0x4, 0, 1, 1) 245#define MPP36_UA2_TDX MPP(36, 0x4, 0, 0, 1)
246#define MPP36_TDM0_SCSn MPP(36, 0x6, 0, 1, 1) 246#define MPP36_TDM0_SCSn MPP(36, 0x6, 0, 0, 1)
247#define MPP36_UNUSED MPP(36, 0x3, 0, 0, 1) 247#define MPP36_UNUSED MPP(36, 0x3, 0, 0, 1)
248 248
249 249
250#define MPP37_GPIO MPP(37, 0x1, 1, 1, 1) 250#define MPP37_GPIO MPP(37, 0x1, 1, 1, 1)
251#define MPP37_UA0_RTSn MPP(37, 0x2, 0, 1, 1) 251#define MPP37_UA0_RTSn MPP(37, 0x2, 0, 0, 1)
252#define MPP37_UA2_RXD MPP(37, 0x4, 1, 0, 1) 252#define MPP37_UA2_RXD MPP(37, 0x4, 0, 0, 1)
253#define MPP37_SYSRST_OUTn MPP(37, 0x5, 0, 1, 1) 253#define MPP37_SYSRST_OUTn MPP(37, 0x5, 0, 0, 1)
254#define MPP37_TDM_SCLK MPP(37, 0x6, 0, 1, 1) 254#define MPP37_TDM_SCLK MPP(37, 0x6, 0, 0, 1)
255#define MPP37_UNUSED MPP(37, 0x3, 0, 0, 1) 255#define MPP37_UNUSED MPP(37, 0x3, 0, 0, 1)
256 256
257 257
258 258
259 259
260#define MPP38_GPIO MPP(38, 0x1, 1, 1, 1) 260#define MPP38_GPIO MPP(38, 0x1, 1, 1, 1)
261#define MPP38_UA1_CTSn MPP(38, 0x2, 1, 0, 1) 261#define MPP38_UA1_CTSn MPP(38, 0x2, 0, 0, 1)
262#define MPP38_UA3_TXD MPP(38, 0x4, 0, 1, 1) 262#define MPP38_UA3_TXD MPP(38, 0x4, 0, 0, 1)
263#define MPP38_SYSRST_OUTn MPP(38, 0x5, 0, 1, 1) 263#define MPP38_SYSRST_OUTn MPP(38, 0x5, 0, 0, 1)
264#define MPP38_TDM_SMOSI MPP(38, 0x6, 0, 1, 1) 264#define MPP38_TDM_SMOSI MPP(38, 0x6, 0, 0, 1)
265#define MPP38_UNUSED MPP(38, 0x3, 0, 0, 1) 265#define MPP38_UNUSED MPP(38, 0x3, 0, 0, 1)
266 266
267 267
268 268
269 269
270#define MPP39_GPIO MPP(39, 0x1, 1, 1, 1) 270#define MPP39_GPIO MPP(39, 0x1, 1, 1, 1)
271#define MPP39_UA1_RTSn MPP(39, 0x2, 0, 1, 1) 271#define MPP39_UA1_RTSn MPP(39, 0x2, 0, 0, 1)
272#define MPP39_UA3_RXD MPP(39, 0x4, 1, 0, 1) 272#define MPP39_UA3_RXD MPP(39, 0x4, 0, 0, 1)
273#define MPP39_SYSRST_OUTn MPP(39, 0x5, 0, 1, 1) 273#define MPP39_SYSRST_OUTn MPP(39, 0x5, 0, 0, 1)
274#define MPP39_TDM_SMISO MPP(39, 0x6, 1, 0, 1) 274#define MPP39_TDM_SMISO MPP(39, 0x6, 0, 0, 1)
275#define MPP39_UNUSED MPP(39, 0x3, 0, 0, 1) 275#define MPP39_UNUSED MPP(39, 0x3, 0, 0, 1)
276 276
277 277
278 278
279#define MPP40_GPIO MPP(40, 0x1, 1, 1, 1) 279#define MPP40_GPIO MPP(40, 0x1, 1, 1, 1)
280#define MPP40_TDM_INTn MPP(40, 0x6, 1, 0, 1) 280#define MPP40_TDM_INTn MPP(40, 0x6, 0, 0, 1)
281#define MPP40_UNUSED MPP(40, 0x0, 0, 0, 1) 281#define MPP40_UNUSED MPP(40, 0x0, 0, 0, 1)
282 282
283 283
284 284
285#define MPP41_GPIO MPP(41, 0x1, 1, 1, 1) 285#define MPP41_GPIO MPP(41, 0x1, 1, 1, 1)
286#define MPP41_TDM_RSTn MPP(41, 0x6, 0, 1, 1) 286#define MPP41_TDM_RSTn MPP(41, 0x6, 0, 0, 1)
287#define MPP41_UNUSED MPP(41, 0x0, 0, 0, 1) 287#define MPP41_UNUSED MPP(41, 0x0, 0, 0, 1)
288 288
289 289
290 290
291#define MPP42_GPIO MPP(42, 0x1, 1, 1, 1) 291#define MPP42_GPIO MPP(42, 0x1, 1, 1, 1)
292#define MPP42_TDM_PCLK MPP(42, 0x6, 1, 1, 1) 292#define MPP42_TDM_PCLK MPP(42, 0x6, 0, 0, 1)
293#define MPP42_UNUSED MPP(42, 0x0, 0, 0, 1) 293#define MPP42_UNUSED MPP(42, 0x0, 0, 0, 1)
294 294
295 295
296 296
297#define MPP43_GPIO MPP(43, 0x1, 1, 1, 1) 297#define MPP43_GPIO MPP(43, 0x1, 1, 1, 1)
298#define MPP43_TDM_FSYNC MPP(43, 0x6, 1, 1, 1) 298#define MPP43_TDM_FSYNC MPP(43, 0x6, 0, 0, 1)
299#define MPP43_UNUSED MPP(43, 0x0, 0, 0, 1) 299#define MPP43_UNUSED MPP(43, 0x0, 0, 0, 1)
300 300
301 301
302 302
303#define MPP44_GPIO MPP(44, 0x1, 1, 1, 1) 303#define MPP44_GPIO MPP(44, 0x1, 1, 1, 1)
304#define MPP44_TDM_DRX MPP(44, 0x6, 1, 0, 1) 304#define MPP44_TDM_DRX MPP(44, 0x6, 0, 0, 1)
305#define MPP44_UNUSED MPP(44, 0x0, 0, 0, 1) 305#define MPP44_UNUSED MPP(44, 0x0, 0, 0, 1)
306 306
307 307
308 308
309#define MPP45_GPIO MPP(45, 0x1, 1, 1, 1) 309#define MPP45_GPIO MPP(45, 0x1, 1, 1, 1)
310#define MPP45_SATA0_ACTn MPP(45, 0x3, 0, 1, 1) 310#define MPP45_SATA0_ACTn MPP(45, 0x3, 0, 0, 1)
311#define MPP45_TDM_DRX MPP(45, 0x6, 0, 1, 1) 311#define MPP45_TDM_DRX MPP(45, 0x6, 0, 0, 1)
312#define MPP45_UNUSED MPP(45, 0x0, 0, 0, 1) 312#define MPP45_UNUSED MPP(45, 0x0, 0, 0, 1)
313 313
314 314
315#define MPP46_GPIO MPP(46, 0x1, 1, 1, 1) 315#define MPP46_GPIO MPP(46, 0x1, 1, 1, 1)
316#define MPP46_TDM_SCSn MPP(46, 0x6, 0, 1, 1) 316#define MPP46_TDM_SCSn MPP(46, 0x6, 0, 0, 1)
317#define MPP46_UNUSED MPP(46, 0x0, 0, 0, 1) 317#define MPP46_UNUSED MPP(46, 0x0, 0, 0, 1)
318 318
319 319
@@ -323,14 +323,14 @@
323 323
324 324
325#define MPP48_GPIO MPP(48, 0x1, 1, 1, 1) 325#define MPP48_GPIO MPP(48, 0x1, 1, 1, 1)
326#define MPP48_SATA1_ACTn MPP(48, 0x3, 0, 1, 1) 326#define MPP48_SATA1_ACTn MPP(48, 0x3, 0, 0, 1)
327#define MPP48_UNUSED MPP(48, 0x2, 0, 0, 1) 327#define MPP48_UNUSED MPP(48, 0x2, 0, 0, 1)
328 328
329 329
330 330
331#define MPP49_GPIO MPP(49, 0x1, 1, 1, 1) 331#define MPP49_GPIO MPP(49, 0x1, 1, 1, 1)
332#define MPP49_SATA0_ACTn MPP(49, 0x3, 0, 1, 1) 332#define MPP49_SATA0_ACTn MPP(49, 0x3, 0, 0, 1)
333#define MPP49_M_BB MPP(49, 0x4, 1, 0, 1) 333#define MPP49_M_BB MPP(49, 0x4, 0, 0, 1)
334#define MPP49_UNUSED MPP(49, 0x2, 0, 0, 1) 334#define MPP49_UNUSED MPP(49, 0x2, 0, 0, 1)
335 335
336 336
diff --git a/arch/arm/mach-omap1/Kconfig b/arch/arm/mach-omap1/Kconfig
index 4f8d66f044e7..922ab0dc2bcd 100644
--- a/arch/arm/mach-omap1/Kconfig
+++ b/arch/arm/mach-omap1/Kconfig
@@ -37,7 +37,6 @@ comment "OMAP Board Type"
37config MACH_OMAP_INNOVATOR 37config MACH_OMAP_INNOVATOR
38 bool "TI Innovator" 38 bool "TI Innovator"
39 depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX) 39 depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX)
40 select OMAP_MCBSP
41 help 40 help
42 TI OMAP 1510 or 1610 Innovator board support. Say Y here if you 41 TI OMAP 1510 or 1610 Innovator board support. Say Y here if you
43 have such a board. 42 have such a board.
@@ -45,7 +44,6 @@ config MACH_OMAP_INNOVATOR
45config MACH_OMAP_H2 44config MACH_OMAP_H2
46 bool "TI H2 Support" 45 bool "TI H2 Support"
47 depends on ARCH_OMAP1 && ARCH_OMAP16XX 46 depends on ARCH_OMAP1 && ARCH_OMAP16XX
48 select OMAP_MCBSP
49 help 47 help
50 TI OMAP 1610/1611B H2 board support. Say Y here if you have such 48 TI OMAP 1610/1611B H2 board support. Say Y here if you have such
51 a board. 49 a board.
@@ -72,7 +70,6 @@ config MACH_HERALD
72config MACH_OMAP_OSK 70config MACH_OMAP_OSK
73 bool "TI OSK Support" 71 bool "TI OSK Support"
74 depends on ARCH_OMAP1 && ARCH_OMAP16XX 72 depends on ARCH_OMAP1 && ARCH_OMAP16XX
75 select OMAP_MCBSP
76 help 73 help
77 TI OMAP 5912 OSK (OMAP Starter Kit) board support. Say Y here 74 TI OMAP 5912 OSK (OMAP Starter Kit) board support. Say Y here
78 if you have such a board. 75 if you have such a board.
diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile
index 11c85cd2731a..9923f92b5450 100644
--- a/arch/arm/mach-omap1/Makefile
+++ b/arch/arm/mach-omap1/Makefile
@@ -6,7 +6,9 @@
6obj-y := io.o id.o sram.o time.o irq.o mux.o flash.o serial.o devices.o dma.o 6obj-y := io.o id.o sram.o time.o irq.o mux.o flash.o serial.o devices.o dma.o
7obj-y += clock.o clock_data.o opp_data.o reset.o pm_bus.o timer.o 7obj-y += clock.o clock_data.o opp_data.o reset.o pm_bus.o timer.o
8 8
9obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o 9ifneq ($(CONFIG_SND_OMAP_SOC_MCBSP),)
10obj-y += mcbsp.o
11endif
10 12
11obj-$(CONFIG_OMAP_32K_TIMER) += timer32k.o 13obj-$(CONFIG_OMAP_32K_TIMER) += timer32k.o
12 14
diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c
index 88909cc0b254..e0e8245f3c9f 100644
--- a/arch/arm/mach-omap1/board-ams-delta.c
+++ b/arch/arm/mach-omap1/board-ams-delta.c
@@ -20,6 +20,7 @@
20#include <linux/platform_device.h> 20#include <linux/platform_device.h>
21#include <linux/serial_8250.h> 21#include <linux/serial_8250.h>
22#include <linux/export.h> 22#include <linux/export.h>
23#include <linux/omapfb.h>
23 24
24#include <media/soc_camera.h> 25#include <media/soc_camera.h>
25 26
@@ -169,10 +170,6 @@ static struct omap_usb_config ams_delta_usb_config __initdata = {
169 .pins[0] = 2, 170 .pins[0] = 2,
170}; 171};
171 172
172static struct omap_board_config_kernel ams_delta_config[] __initdata = {
173 { OMAP_TAG_LCD, &ams_delta_lcd_config },
174};
175
176static struct resource ams_delta_nand_resources[] = { 173static struct resource ams_delta_nand_resources[] = {
177 [0] = { 174 [0] = {
178 .start = OMAP1_MPUIO_BASE, 175 .start = OMAP1_MPUIO_BASE,
@@ -302,8 +299,6 @@ static void __init ams_delta_init(void)
302 omap_cfg_reg(J19_1610_CAM_D6); 299 omap_cfg_reg(J19_1610_CAM_D6);
303 omap_cfg_reg(J18_1610_CAM_D7); 300 omap_cfg_reg(J18_1610_CAM_D7);
304 301
305 omap_board_config = ams_delta_config;
306 omap_board_config_size = ARRAY_SIZE(ams_delta_config);
307 omap_serial_init(); 302 omap_serial_init();
308 omap_register_i2c_bus(1, 100, NULL, 0); 303 omap_register_i2c_bus(1, 100, NULL, 0);
309 304
@@ -321,6 +316,8 @@ static void __init ams_delta_init(void)
321 ams_delta_init_fiq(); 316 ams_delta_init_fiq();
322 317
323 omap_writew(omap_readw(ARM_RSTCT1) | 0x0004, ARM_RSTCT1); 318 omap_writew(omap_readw(ARM_RSTCT1) | 0x0004, ARM_RSTCT1);
319
320 omapfb_set_lcd_config(&ams_delta_lcd_config);
324} 321}
325 322
326static struct plat_serial8250_port ams_delta_modem_ports[] = { 323static struct plat_serial8250_port ams_delta_modem_ports[] = {
diff --git a/arch/arm/mach-omap1/board-fsample.c b/arch/arm/mach-omap1/board-fsample.c
index 0b9464b41212..7afaf3c5bdc6 100644
--- a/arch/arm/mach-omap1/board-fsample.c
+++ b/arch/arm/mach-omap1/board-fsample.c
@@ -21,6 +21,7 @@
21#include <linux/mtd/physmap.h> 21#include <linux/mtd/physmap.h>
22#include <linux/input.h> 22#include <linux/input.h>
23#include <linux/smc91x.h> 23#include <linux/smc91x.h>
24#include <linux/omapfb.h>
24 25
25#include <mach/hardware.h> 26#include <mach/hardware.h>
26#include <asm/mach-types.h> 27#include <asm/mach-types.h>
@@ -273,27 +274,17 @@ static struct platform_device kp_device = {
273 .resource = kp_resources, 274 .resource = kp_resources,
274}; 275};
275 276
276static struct platform_device lcd_device = {
277 .name = "lcd_p2",
278 .id = -1,
279};
280
281static struct platform_device *devices[] __initdata = { 277static struct platform_device *devices[] __initdata = {
282 &nor_device, 278 &nor_device,
283 &nand_device, 279 &nand_device,
284 &smc91x_device, 280 &smc91x_device,
285 &kp_device, 281 &kp_device,
286 &lcd_device,
287}; 282};
288 283
289static struct omap_lcd_config fsample_lcd_config = { 284static struct omap_lcd_config fsample_lcd_config = {
290 .ctrl_name = "internal", 285 .ctrl_name = "internal",
291}; 286};
292 287
293static struct omap_board_config_kernel fsample_config[] __initdata = {
294 { OMAP_TAG_LCD, &fsample_lcd_config },
295};
296
297static void __init omap_fsample_init(void) 288static void __init omap_fsample_init(void)
298{ 289{
299 /* Early, board-dependent init */ 290 /* Early, board-dependent init */
@@ -352,10 +343,10 @@ static void __init omap_fsample_init(void)
352 343
353 platform_add_devices(devices, ARRAY_SIZE(devices)); 344 platform_add_devices(devices, ARRAY_SIZE(devices));
354 345
355 omap_board_config = fsample_config;
356 omap_board_config_size = ARRAY_SIZE(fsample_config);
357 omap_serial_init(); 346 omap_serial_init();
358 omap_register_i2c_bus(1, 100, NULL, 0); 347 omap_register_i2c_bus(1, 100, NULL, 0);
348
349 omapfb_set_lcd_config(&fsample_lcd_config);
359} 350}
360 351
361/* Only FPGA needs to be mapped here. All others are done with ioremap */ 352/* Only FPGA needs to be mapped here. All others are done with ioremap */
diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c
index 00ad6b22d60a..af2be8c12c07 100644
--- a/arch/arm/mach-omap1/board-h2.c
+++ b/arch/arm/mach-omap1/board-h2.c
@@ -30,6 +30,7 @@
30#include <linux/input.h> 30#include <linux/input.h>
31#include <linux/i2c/tps65010.h> 31#include <linux/i2c/tps65010.h>
32#include <linux/smc91x.h> 32#include <linux/smc91x.h>
33#include <linux/omapfb.h>
33 34
34#include <mach/hardware.h> 35#include <mach/hardware.h>
35 36
@@ -325,18 +326,12 @@ static struct platform_device h2_irda_device = {
325 .resource = h2_irda_resources, 326 .resource = h2_irda_resources,
326}; 327};
327 328
328static struct platform_device h2_lcd_device = {
329 .name = "lcd_h2",
330 .id = -1,
331};
332
333static struct platform_device *h2_devices[] __initdata = { 329static struct platform_device *h2_devices[] __initdata = {
334 &h2_nor_device, 330 &h2_nor_device,
335 &h2_nand_device, 331 &h2_nand_device,
336 &h2_smc91x_device, 332 &h2_smc91x_device,
337 &h2_irda_device, 333 &h2_irda_device,
338 &h2_kp_device, 334 &h2_kp_device,
339 &h2_lcd_device,
340}; 335};
341 336
342static void __init h2_init_smc91x(void) 337static void __init h2_init_smc91x(void)
@@ -391,10 +386,6 @@ static struct omap_lcd_config h2_lcd_config __initdata = {
391 .ctrl_name = "internal", 386 .ctrl_name = "internal",
392}; 387};
393 388
394static struct omap_board_config_kernel h2_config[] __initdata = {
395 { OMAP_TAG_LCD, &h2_lcd_config },
396};
397
398static void __init h2_init(void) 389static void __init h2_init(void)
399{ 390{
400 h2_init_smc91x(); 391 h2_init_smc91x();
@@ -438,13 +429,13 @@ static void __init h2_init(void)
438 omap_cfg_reg(N19_1610_KBR5); 429 omap_cfg_reg(N19_1610_KBR5);
439 430
440 platform_add_devices(h2_devices, ARRAY_SIZE(h2_devices)); 431 platform_add_devices(h2_devices, ARRAY_SIZE(h2_devices));
441 omap_board_config = h2_config;
442 omap_board_config_size = ARRAY_SIZE(h2_config);
443 omap_serial_init(); 432 omap_serial_init();
444 omap_register_i2c_bus(1, 100, h2_i2c_board_info, 433 omap_register_i2c_bus(1, 100, h2_i2c_board_info,
445 ARRAY_SIZE(h2_i2c_board_info)); 434 ARRAY_SIZE(h2_i2c_board_info));
446 omap1_usb_init(&h2_usb_config); 435 omap1_usb_init(&h2_usb_config);
447 h2_mmc_init(); 436 h2_mmc_init();
437
438 omapfb_set_lcd_config(&h2_lcd_config);
448} 439}
449 440
450MACHINE_START(OMAP_H2, "TI-H2") 441MACHINE_START(OMAP_H2, "TI-H2")
diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c
index 4a7f25149703..7cfd25b90735 100644
--- a/arch/arm/mach-omap1/board-h3.c
+++ b/arch/arm/mach-omap1/board-h3.c
@@ -30,6 +30,7 @@
30#include <linux/spi/spi.h> 30#include <linux/spi/spi.h>
31#include <linux/i2c/tps65010.h> 31#include <linux/i2c/tps65010.h>
32#include <linux/smc91x.h> 32#include <linux/smc91x.h>
33#include <linux/omapfb.h>
33 34
34#include <asm/setup.h> 35#include <asm/setup.h>
35#include <asm/page.h> 36#include <asm/page.h>
@@ -370,10 +371,6 @@ static struct omap_lcd_config h3_lcd_config __initdata = {
370 .ctrl_name = "internal", 371 .ctrl_name = "internal",
371}; 372};
372 373
373static struct omap_board_config_kernel h3_config[] __initdata = {
374 { OMAP_TAG_LCD, &h3_lcd_config },
375};
376
377static struct i2c_board_info __initdata h3_i2c_board_info[] = { 374static struct i2c_board_info __initdata h3_i2c_board_info[] = {
378 { 375 {
379 I2C_BOARD_INFO("tps65013", 0x48), 376 I2C_BOARD_INFO("tps65013", 0x48),
@@ -426,13 +423,13 @@ static void __init h3_init(void)
426 platform_add_devices(devices, ARRAY_SIZE(devices)); 423 platform_add_devices(devices, ARRAY_SIZE(devices));
427 spi_register_board_info(h3_spi_board_info, 424 spi_register_board_info(h3_spi_board_info,
428 ARRAY_SIZE(h3_spi_board_info)); 425 ARRAY_SIZE(h3_spi_board_info));
429 omap_board_config = h3_config;
430 omap_board_config_size = ARRAY_SIZE(h3_config);
431 omap_serial_init(); 426 omap_serial_init();
432 omap_register_i2c_bus(1, 100, h3_i2c_board_info, 427 omap_register_i2c_bus(1, 100, h3_i2c_board_info,
433 ARRAY_SIZE(h3_i2c_board_info)); 428 ARRAY_SIZE(h3_i2c_board_info));
434 omap1_usb_init(&h3_usb_config); 429 omap1_usb_init(&h3_usb_config);
435 h3_mmc_init(); 430 h3_mmc_init();
431
432 omapfb_set_lcd_config(&h3_lcd_config);
436} 433}
437 434
438MACHINE_START(OMAP_H3, "TI OMAP1710 H3 board") 435MACHINE_START(OMAP_H3, "TI OMAP1710 H3 board")
diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c
index 731cc3db7ab3..af2afcf24f75 100644
--- a/arch/arm/mach-omap1/board-htcherald.c
+++ b/arch/arm/mach-omap1/board-htcherald.c
@@ -36,6 +36,7 @@
36#include <linux/leds.h> 36#include <linux/leds.h>
37#include <linux/spi/spi.h> 37#include <linux/spi/spi.h>
38#include <linux/spi/ads7846.h> 38#include <linux/spi/ads7846.h>
39#include <linux/omapfb.h>
39 40
40#include <asm/mach-types.h> 41#include <asm/mach-types.h>
41#include <asm/mach/arch.h> 42#include <asm/mach/arch.h>
@@ -398,10 +399,6 @@ static struct omap_lcd_config htcherald_lcd_config __initdata = {
398 .ctrl_name = "internal", 399 .ctrl_name = "internal",
399}; 400};
400 401
401static struct omap_board_config_kernel htcherald_config[] __initdata = {
402 { OMAP_TAG_LCD, &htcherald_lcd_config },
403};
404
405static struct platform_device lcd_device = { 402static struct platform_device lcd_device = {
406 .name = "lcd_htcherald", 403 .name = "lcd_htcherald",
407 .id = -1, 404 .id = -1,
@@ -580,8 +577,6 @@ static void __init htcherald_init(void)
580 printk(KERN_INFO "HTC Herald init.\n"); 577 printk(KERN_INFO "HTC Herald init.\n");
581 578
582 /* Do board initialization before we register all the devices */ 579 /* Do board initialization before we register all the devices */
583 omap_board_config = htcherald_config;
584 omap_board_config_size = ARRAY_SIZE(htcherald_config);
585 platform_add_devices(devices, ARRAY_SIZE(devices)); 580 platform_add_devices(devices, ARRAY_SIZE(devices));
586 581
587 htcherald_disable_watchdog(); 582 htcherald_disable_watchdog();
@@ -598,6 +593,8 @@ static void __init htcherald_init(void)
598 htc_mmc_data[0] = &htc_mmc1_data; 593 htc_mmc_data[0] = &htc_mmc1_data;
599 omap1_init_mmc(htc_mmc_data, 1); 594 omap1_init_mmc(htc_mmc_data, 1);
600#endif 595#endif
596
597 omapfb_set_lcd_config(&htcherald_lcd_config);
601} 598}
602 599
603MACHINE_START(HERALD, "HTC Herald") 600MACHINE_START(HERALD, "HTC Herald")
diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c
index 309369ea6978..1d5ab6606b9f 100644
--- a/arch/arm/mach-omap1/board-innovator.c
+++ b/arch/arm/mach-omap1/board-innovator.c
@@ -25,6 +25,7 @@
25#include <linux/mtd/physmap.h> 25#include <linux/mtd/physmap.h>
26#include <linux/input.h> 26#include <linux/input.h>
27#include <linux/smc91x.h> 27#include <linux/smc91x.h>
28#include <linux/omapfb.h>
28 29
29#include <mach/hardware.h> 30#include <mach/hardware.h>
30#include <asm/mach-types.h> 31#include <asm/mach-types.h>
@@ -370,10 +371,6 @@ static inline void innovator_mmc_init(void)
370} 371}
371#endif 372#endif
372 373
373static struct omap_board_config_kernel innovator_config[] = {
374 { OMAP_TAG_LCD, NULL },
375};
376
377static void __init innovator_init(void) 374static void __init innovator_init(void)
378{ 375{
379 if (cpu_is_omap1510()) 376 if (cpu_is_omap1510())
@@ -416,17 +413,15 @@ static void __init innovator_init(void)
416#ifdef CONFIG_ARCH_OMAP15XX 413#ifdef CONFIG_ARCH_OMAP15XX
417 if (cpu_is_omap1510()) { 414 if (cpu_is_omap1510()) {
418 omap1_usb_init(&innovator1510_usb_config); 415 omap1_usb_init(&innovator1510_usb_config);
419 innovator_config[1].data = &innovator1510_lcd_config; 416 omapfb_set_lcd_config(&innovator1510_lcd_config);
420 } 417 }
421#endif 418#endif
422#ifdef CONFIG_ARCH_OMAP16XX 419#ifdef CONFIG_ARCH_OMAP16XX
423 if (cpu_is_omap1610()) { 420 if (cpu_is_omap1610()) {
424 omap1_usb_init(&h2_usb_config); 421 omap1_usb_init(&h2_usb_config);
425 innovator_config[1].data = &innovator1610_lcd_config; 422 omapfb_set_lcd_config(&innovator1610_lcd_config);
426 } 423 }
427#endif 424#endif
428 omap_board_config = innovator_config;
429 omap_board_config_size = ARRAY_SIZE(innovator_config);
430 omap_serial_init(); 425 omap_serial_init();
431 omap_register_i2c_bus(1, 100, NULL, 0); 426 omap_register_i2c_bus(1, 100, NULL, 0);
432 innovator_mmc_init(); 427 innovator_mmc_init();
diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c
index f9efc036ba96..9b6332a31fb6 100644
--- a/arch/arm/mach-omap1/board-nokia770.c
+++ b/arch/arm/mach-omap1/board-nokia770.c
@@ -31,7 +31,6 @@
31#include <plat/board.h> 31#include <plat/board.h>
32#include <plat/keypad.h> 32#include <plat/keypad.h>
33#include "common.h" 33#include "common.h"
34#include <plat/hwa742.h>
35#include <plat/lcd_mipid.h> 34#include <plat/lcd_mipid.h>
36#include <plat/mmc.h> 35#include <plat/mmc.h>
37#include <plat/clock.h> 36#include <plat/clock.h>
@@ -99,15 +98,16 @@ static struct mipid_platform_data nokia770_mipid_platform_data = {
99 .shutdown = mipid_shutdown, 98 .shutdown = mipid_shutdown,
100}; 99};
101 100
101static struct omap_lcd_config nokia770_lcd_config __initdata = {
102 .ctrl_name = "hwa742",
103};
104
102static void __init mipid_dev_init(void) 105static void __init mipid_dev_init(void)
103{ 106{
104 const struct omap_lcd_config *conf; 107 nokia770_mipid_platform_data.nreset_gpio = 13;
108 nokia770_mipid_platform_data.data_lines = 16;
105 109
106 conf = omap_get_config(OMAP_TAG_LCD, struct omap_lcd_config); 110 omapfb_set_lcd_config(&nokia770_lcd_config);
107 if (conf != NULL) {
108 nokia770_mipid_platform_data.nreset_gpio = conf->nreset_gpio;
109 nokia770_mipid_platform_data.data_lines = conf->data_lines;
110 }
111} 111}
112 112
113static void __init ads7846_dev_init(void) 113static void __init ads7846_dev_init(void)
@@ -150,14 +150,9 @@ static struct spi_board_info nokia770_spi_board_info[] __initdata = {
150 }, 150 },
151}; 151};
152 152
153static struct hwa742_platform_data nokia770_hwa742_platform_data = {
154 .te_connected = 1,
155};
156
157static void __init hwa742_dev_init(void) 153static void __init hwa742_dev_init(void)
158{ 154{
159 clk_add_alias("hwa_sys_ck", NULL, "bclk", NULL); 155 clk_add_alias("hwa_sys_ck", NULL, "bclk", NULL);
160 omapfb_set_ctrl_platform_data(&nokia770_hwa742_platform_data);
161} 156}
162 157
163/* assume no Mini-AB port */ 158/* assume no Mini-AB port */
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c
index 675de06557aa..ef874655fbd3 100644
--- a/arch/arm/mach-omap1/board-osk.c
+++ b/arch/arm/mach-omap1/board-osk.c
@@ -34,6 +34,7 @@
34#include <linux/i2c.h> 34#include <linux/i2c.h>
35#include <linux/leds.h> 35#include <linux/leds.h>
36#include <linux/smc91x.h> 36#include <linux/smc91x.h>
37#include <linux/omapfb.h>
37 38
38#include <linux/mtd/mtd.h> 39#include <linux/mtd/mtd.h>
39#include <linux/mtd/partitions.h> 40#include <linux/mtd/partitions.h>
@@ -300,12 +301,6 @@ static struct omap_lcd_config osk_lcd_config __initdata = {
300}; 301};
301#endif 302#endif
302 303
303static struct omap_board_config_kernel osk_config[] __initdata = {
304#ifdef CONFIG_OMAP_OSK_MISTRAL
305 { OMAP_TAG_LCD, &osk_lcd_config },
306#endif
307};
308
309#ifdef CONFIG_OMAP_OSK_MISTRAL 304#ifdef CONFIG_OMAP_OSK_MISTRAL
310 305
311#include <linux/input.h> 306#include <linux/input.h>
@@ -549,8 +544,6 @@ static void __init osk_init(void)
549 osk_flash_resource.end = osk_flash_resource.start = omap_cs3_phys(); 544 osk_flash_resource.end = osk_flash_resource.start = omap_cs3_phys();
550 osk_flash_resource.end += SZ_32M - 1; 545 osk_flash_resource.end += SZ_32M - 1;
551 platform_add_devices(osk5912_devices, ARRAY_SIZE(osk5912_devices)); 546 platform_add_devices(osk5912_devices, ARRAY_SIZE(osk5912_devices));
552 omap_board_config = osk_config;
553 omap_board_config_size = ARRAY_SIZE(osk_config);
554 547
555 l = omap_readl(USB_TRANSCEIVER_CTRL); 548 l = omap_readl(USB_TRANSCEIVER_CTRL);
556 l |= (3 << 1); 549 l |= (3 << 1);
@@ -567,6 +560,11 @@ static void __init osk_init(void)
567 omap_register_i2c_bus(1, 400, osk_i2c_board_info, 560 omap_register_i2c_bus(1, 400, osk_i2c_board_info,
568 ARRAY_SIZE(osk_i2c_board_info)); 561 ARRAY_SIZE(osk_i2c_board_info));
569 osk_mistral_init(); 562 osk_mistral_init();
563
564#ifdef CONFIG_OMAP_OSK_MISTRAL
565 omapfb_set_lcd_config(&osk_lcd_config);
566#endif
567
570} 568}
571 569
572MACHINE_START(OMAP_OSK, "TI-OSK") 570MACHINE_START(OMAP_OSK, "TI-OSK")
diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c
index 81fa27f88369..612342cb2a2d 100644
--- a/arch/arm/mach-omap1/board-palmte.c
+++ b/arch/arm/mach-omap1/board-palmte.c
@@ -27,6 +27,7 @@
27#include <linux/spi/spi.h> 27#include <linux/spi/spi.h>
28#include <linux/interrupt.h> 28#include <linux/interrupt.h>
29#include <linux/apm-emulation.h> 29#include <linux/apm-emulation.h>
30#include <linux/omapfb.h>
30 31
31#include <mach/hardware.h> 32#include <mach/hardware.h>
32#include <asm/mach-types.h> 33#include <asm/mach-types.h>
@@ -209,10 +210,6 @@ static struct omap_lcd_config palmte_lcd_config __initdata = {
209 .ctrl_name = "internal", 210 .ctrl_name = "internal",
210}; 211};
211 212
212static struct omap_board_config_kernel palmte_config[] __initdata = {
213 { OMAP_TAG_LCD, &palmte_lcd_config },
214};
215
216static struct spi_board_info palmte_spi_info[] __initdata = { 213static struct spi_board_info palmte_spi_info[] __initdata = {
217 { 214 {
218 .modalias = "tsc2102", 215 .modalias = "tsc2102",
@@ -250,9 +247,6 @@ static void __init omap_palmte_init(void)
250 omap_cfg_reg(UART3_TX); 247 omap_cfg_reg(UART3_TX);
251 omap_cfg_reg(UART3_RX); 248 omap_cfg_reg(UART3_RX);
252 249
253 omap_board_config = palmte_config;
254 omap_board_config_size = ARRAY_SIZE(palmte_config);
255
256 platform_add_devices(palmte_devices, ARRAY_SIZE(palmte_devices)); 250 platform_add_devices(palmte_devices, ARRAY_SIZE(palmte_devices));
257 251
258 spi_register_board_info(palmte_spi_info, ARRAY_SIZE(palmte_spi_info)); 252 spi_register_board_info(palmte_spi_info, ARRAY_SIZE(palmte_spi_info));
@@ -260,6 +254,8 @@ static void __init omap_palmte_init(void)
260 omap_serial_init(); 254 omap_serial_init();
261 omap1_usb_init(&palmte_usb_config); 255 omap1_usb_init(&palmte_usb_config);
262 omap_register_i2c_bus(1, 100, NULL, 0); 256 omap_register_i2c_bus(1, 100, NULL, 0);
257
258 omapfb_set_lcd_config(&palmte_lcd_config);
263} 259}
264 260
265MACHINE_START(OMAP_PALMTE, "OMAP310 based Palm Tungsten E") 261MACHINE_START(OMAP_PALMTE, "OMAP310 based Palm Tungsten E")
diff --git a/arch/arm/mach-omap1/board-palmtt.c b/arch/arm/mach-omap1/board-palmtt.c
index 81cb82178388..b63350bc88fd 100644
--- a/arch/arm/mach-omap1/board-palmtt.c
+++ b/arch/arm/mach-omap1/board-palmtt.c
@@ -24,6 +24,7 @@
24#include <linux/mtd/partitions.h> 24#include <linux/mtd/partitions.h>
25#include <linux/mtd/physmap.h> 25#include <linux/mtd/physmap.h>
26#include <linux/leds.h> 26#include <linux/leds.h>
27#include <linux/omapfb.h>
27 28
28#include <mach/hardware.h> 29#include <mach/hardware.h>
29#include <asm/mach-types.h> 30#include <asm/mach-types.h>
@@ -273,10 +274,6 @@ static struct omap_lcd_config palmtt_lcd_config __initdata = {
273 .ctrl_name = "internal", 274 .ctrl_name = "internal",
274}; 275};
275 276
276static struct omap_board_config_kernel palmtt_config[] __initdata = {
277 { OMAP_TAG_LCD, &palmtt_lcd_config },
278};
279
280static void __init omap_mpu_wdt_mode(int mode) { 277static void __init omap_mpu_wdt_mode(int mode) {
281 if (mode) 278 if (mode)
282 omap_writew(0x8000, OMAP_WDT_TIMER_MODE); 279 omap_writew(0x8000, OMAP_WDT_TIMER_MODE);
@@ -298,15 +295,14 @@ static void __init omap_palmtt_init(void)
298 295
299 omap_mpu_wdt_mode(0); 296 omap_mpu_wdt_mode(0);
300 297
301 omap_board_config = palmtt_config;
302 omap_board_config_size = ARRAY_SIZE(palmtt_config);
303
304 platform_add_devices(palmtt_devices, ARRAY_SIZE(palmtt_devices)); 298 platform_add_devices(palmtt_devices, ARRAY_SIZE(palmtt_devices));
305 299
306 spi_register_board_info(palmtt_boardinfo,ARRAY_SIZE(palmtt_boardinfo)); 300 spi_register_board_info(palmtt_boardinfo,ARRAY_SIZE(palmtt_boardinfo));
307 omap_serial_init(); 301 omap_serial_init();
308 omap1_usb_init(&palmtt_usb_config); 302 omap1_usb_init(&palmtt_usb_config);
309 omap_register_i2c_bus(1, 100, NULL, 0); 303 omap_register_i2c_bus(1, 100, NULL, 0);
304
305 omapfb_set_lcd_config(&palmtt_lcd_config);
310} 306}
311 307
312MACHINE_START(OMAP_PALMTT, "OMAP1510 based Palm Tungsten|T") 308MACHINE_START(OMAP_PALMTT, "OMAP1510 based Palm Tungsten|T")
diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c
index e881945ce8ec..9924c70af09f 100644
--- a/arch/arm/mach-omap1/board-palmz71.c
+++ b/arch/arm/mach-omap1/board-palmz71.c
@@ -27,6 +27,7 @@
27#include <linux/mtd/mtd.h> 27#include <linux/mtd/mtd.h>
28#include <linux/mtd/partitions.h> 28#include <linux/mtd/partitions.h>
29#include <linux/mtd/physmap.h> 29#include <linux/mtd/physmap.h>
30#include <linux/omapfb.h>
30 31
31#include <mach/hardware.h> 32#include <mach/hardware.h>
32#include <asm/mach-types.h> 33#include <asm/mach-types.h>
@@ -239,10 +240,6 @@ static struct omap_lcd_config palmz71_lcd_config __initdata = {
239 .ctrl_name = "internal", 240 .ctrl_name = "internal",
240}; 241};
241 242
242static struct omap_board_config_kernel palmz71_config[] __initdata = {
243 {OMAP_TAG_LCD, &palmz71_lcd_config},
244};
245
246static irqreturn_t 243static irqreturn_t
247palmz71_powercable(int irq, void *dev_id) 244palmz71_powercable(int irq, void *dev_id)
248{ 245{
@@ -313,9 +310,6 @@ omap_palmz71_init(void)
313 palmz71_gpio_setup(1); 310 palmz71_gpio_setup(1);
314 omap_mpu_wdt_mode(0); 311 omap_mpu_wdt_mode(0);
315 312
316 omap_board_config = palmz71_config;
317 omap_board_config_size = ARRAY_SIZE(palmz71_config);
318
319 platform_add_devices(devices, ARRAY_SIZE(devices)); 313 platform_add_devices(devices, ARRAY_SIZE(devices));
320 314
321 spi_register_board_info(palmz71_boardinfo, 315 spi_register_board_info(palmz71_boardinfo,
@@ -324,6 +318,8 @@ omap_palmz71_init(void)
324 omap_serial_init(); 318 omap_serial_init();
325 omap_register_i2c_bus(1, 100, NULL, 0); 319 omap_register_i2c_bus(1, 100, NULL, 0);
326 palmz71_gpio_setup(0); 320 palmz71_gpio_setup(0);
321
322 omapfb_set_lcd_config(&palmz71_lcd_config);
327} 323}
328 324
329MACHINE_START(OMAP_PALMZ71, "OMAP310 based Palm Zire71") 325MACHINE_START(OMAP_PALMZ71, "OMAP310 based Palm Zire71")
diff --git a/arch/arm/mach-omap1/board-perseus2.c b/arch/arm/mach-omap1/board-perseus2.c
index c000bed76276..8e0153447c6d 100644
--- a/arch/arm/mach-omap1/board-perseus2.c
+++ b/arch/arm/mach-omap1/board-perseus2.c
@@ -21,6 +21,7 @@
21#include <linux/mtd/physmap.h> 21#include <linux/mtd/physmap.h>
22#include <linux/input.h> 22#include <linux/input.h>
23#include <linux/smc91x.h> 23#include <linux/smc91x.h>
24#include <linux/omapfb.h>
24 25
25#include <mach/hardware.h> 26#include <mach/hardware.h>
26#include <asm/mach-types.h> 27#include <asm/mach-types.h>
@@ -232,27 +233,17 @@ static struct platform_device kp_device = {
232 .resource = kp_resources, 233 .resource = kp_resources,
233}; 234};
234 235
235static struct platform_device lcd_device = {
236 .name = "lcd_p2",
237 .id = -1,
238};
239
240static struct platform_device *devices[] __initdata = { 236static struct platform_device *devices[] __initdata = {
241 &nor_device, 237 &nor_device,
242 &nand_device, 238 &nand_device,
243 &smc91x_device, 239 &smc91x_device,
244 &kp_device, 240 &kp_device,
245 &lcd_device,
246}; 241};
247 242
248static struct omap_lcd_config perseus2_lcd_config __initdata = { 243static struct omap_lcd_config perseus2_lcd_config __initdata = {
249 .ctrl_name = "internal", 244 .ctrl_name = "internal",
250}; 245};
251 246
252static struct omap_board_config_kernel perseus2_config[] __initdata = {
253 { OMAP_TAG_LCD, &perseus2_lcd_config },
254};
255
256static void __init perseus2_init_smc91x(void) 247static void __init perseus2_init_smc91x(void)
257{ 248{
258 fpga_write(1, H2P2_DBG_FPGA_LAN_RESET); 249 fpga_write(1, H2P2_DBG_FPGA_LAN_RESET);
@@ -320,10 +311,10 @@ static void __init omap_perseus2_init(void)
320 311
321 platform_add_devices(devices, ARRAY_SIZE(devices)); 312 platform_add_devices(devices, ARRAY_SIZE(devices));
322 313
323 omap_board_config = perseus2_config;
324 omap_board_config_size = ARRAY_SIZE(perseus2_config);
325 omap_serial_init(); 314 omap_serial_init();
326 omap_register_i2c_bus(1, 100, NULL, 0); 315 omap_register_i2c_bus(1, 100, NULL, 0);
316
317 omapfb_set_lcd_config(&perseus2_lcd_config);
327} 318}
328 319
329/* Only FPGA needs to be mapped here. All others are done with ioremap */ 320/* Only FPGA needs to be mapped here. All others are done with ioremap */
diff --git a/arch/arm/mach-omap1/board-sx1.c b/arch/arm/mach-omap1/board-sx1.c
index 7bcd82ab0fd0..0c76e12337d9 100644
--- a/arch/arm/mach-omap1/board-sx1.c
+++ b/arch/arm/mach-omap1/board-sx1.c
@@ -27,6 +27,7 @@
27#include <linux/i2c.h> 27#include <linux/i2c.h>
28#include <linux/errno.h> 28#include <linux/errno.h>
29#include <linux/export.h> 29#include <linux/export.h>
30#include <linux/omapfb.h>
30 31
31#include <mach/hardware.h> 32#include <mach/hardware.h>
32#include <asm/mach-types.h> 33#include <asm/mach-types.h>
@@ -355,11 +356,6 @@ static struct omap_usb_config sx1_usb_config __initdata = {
355 356
356/*----------- LCD -------------------------*/ 357/*----------- LCD -------------------------*/
357 358
358static struct platform_device sx1_lcd_device = {
359 .name = "lcd_sx1",
360 .id = -1,
361};
362
363static struct omap_lcd_config sx1_lcd_config __initdata = { 359static struct omap_lcd_config sx1_lcd_config __initdata = {
364 .ctrl_name = "internal", 360 .ctrl_name = "internal",
365}; 361};
@@ -368,14 +364,8 @@ static struct omap_lcd_config sx1_lcd_config __initdata = {
368static struct platform_device *sx1_devices[] __initdata = { 364static struct platform_device *sx1_devices[] __initdata = {
369 &sx1_flash_device, 365 &sx1_flash_device,
370 &sx1_kp_device, 366 &sx1_kp_device,
371 &sx1_lcd_device,
372 &sx1_irda_device, 367 &sx1_irda_device,
373}; 368};
374/*-----------------------------------------*/
375
376static struct omap_board_config_kernel sx1_config[] __initdata = {
377 { OMAP_TAG_LCD, &sx1_lcd_config },
378};
379 369
380/*-----------------------------------------*/ 370/*-----------------------------------------*/
381 371
@@ -391,8 +381,6 @@ static void __init omap_sx1_init(void)
391 381
392 platform_add_devices(sx1_devices, ARRAY_SIZE(sx1_devices)); 382 platform_add_devices(sx1_devices, ARRAY_SIZE(sx1_devices));
393 383
394 omap_board_config = sx1_config;
395 omap_board_config_size = ARRAY_SIZE(sx1_config);
396 omap_serial_init(); 384 omap_serial_init();
397 omap_register_i2c_bus(1, 100, NULL, 0); 385 omap_register_i2c_bus(1, 100, NULL, 0);
398 omap1_usb_init(&sx1_usb_config); 386 omap1_usb_init(&sx1_usb_config);
@@ -406,6 +394,8 @@ static void __init omap_sx1_init(void)
406 gpio_direction_output(1, 1); /*A_IRDA_OFF = 1 */ 394 gpio_direction_output(1, 1); /*A_IRDA_OFF = 1 */
407 gpio_direction_output(11, 0); /*A_SWITCH = 0 */ 395 gpio_direction_output(11, 0); /*A_SWITCH = 0 */
408 gpio_direction_output(15, 0); /*A_USB_ON = 0 */ 396 gpio_direction_output(15, 0); /*A_USB_ON = 0 */
397
398 omapfb_set_lcd_config(&sx1_lcd_config);
409} 399}
410 400
411MACHINE_START(SX1, "OMAP310 based Siemens SX1") 401MACHINE_START(SX1, "OMAP310 based Siemens SX1")
diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c
index 1d76a63c0983..187b2fe132e9 100644
--- a/arch/arm/mach-omap1/devices.c
+++ b/arch/arm/mach-omap1/devices.c
@@ -28,7 +28,6 @@
28#include <plat/mux.h> 28#include <plat/mux.h>
29#include <plat/mmc.h> 29#include <plat/mmc.h>
30#include <plat/omap7xx.h> 30#include <plat/omap7xx.h>
31#include <plat/mcbsp.h>
32 31
33#include "clock.h" 32#include "clock.h"
34 33
@@ -250,16 +249,8 @@ static struct platform_device omap_pcm = {
250 .id = -1, 249 .id = -1,
251}; 250};
252 251
253OMAP_MCBSP_PLATFORM_DEVICE(1);
254OMAP_MCBSP_PLATFORM_DEVICE(2);
255OMAP_MCBSP_PLATFORM_DEVICE(3);
256
257static void omap_init_audio(void) 252static void omap_init_audio(void)
258{ 253{
259 platform_device_register(&omap_mcbsp1);
260 platform_device_register(&omap_mcbsp2);
261 if (!cpu_is_omap7xx())
262 platform_device_register(&omap_mcbsp3);
263 platform_device_register(&omap_pcm); 254 platform_device_register(&omap_pcm);
264} 255}
265 256
diff --git a/arch/arm/mach-omap1/lcd_dma.c b/arch/arm/mach-omap1/lcd_dma.c
index 453809359ba6..4c5ce7d829c2 100644
--- a/arch/arm/mach-omap1/lcd_dma.c
+++ b/arch/arm/mach-omap1/lcd_dma.c
@@ -117,7 +117,7 @@ EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror);
117void omap_set_lcd_dma_b1_vxres(unsigned long vxres) 117void omap_set_lcd_dma_b1_vxres(unsigned long vxres)
118{ 118{
119 if (cpu_is_omap15xx()) { 119 if (cpu_is_omap15xx()) {
120 printk(KERN_ERR "DMA virtual resulotion is not supported " 120 printk(KERN_ERR "DMA virtual resolution is not supported "
121 "in 1510 mode\n"); 121 "in 1510 mode\n");
122 BUG(); 122 BUG();
123 } 123 }
diff --git a/arch/arm/mach-omap1/mcbsp.c b/arch/arm/mach-omap1/mcbsp.c
index 91f9abbd3250..3e8410a99990 100644
--- a/arch/arm/mach-omap1/mcbsp.c
+++ b/arch/arm/mach-omap1/mcbsp.c
@@ -420,18 +420,6 @@ static int __init omap1_mcbsp_init(void)
420 return -ENODEV; 420 return -ENODEV;
421 421
422 if (cpu_is_omap7xx()) 422 if (cpu_is_omap7xx())
423 omap_mcbsp_count = OMAP7XX_MCBSP_COUNT;
424 else if (cpu_is_omap15xx())
425 omap_mcbsp_count = OMAP15XX_MCBSP_COUNT;
426 else if (cpu_is_omap16xx())
427 omap_mcbsp_count = OMAP16XX_MCBSP_COUNT;
428
429 mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *),
430 GFP_KERNEL);
431 if (!mcbsp_ptr)
432 return -ENOMEM;
433
434 if (cpu_is_omap7xx())
435 omap_mcbsp_register_board_cfg(omap7xx_mcbsp_res_0, 423 omap_mcbsp_register_board_cfg(omap7xx_mcbsp_res_0,
436 OMAP7XX_MCBSP_RES_SZ, 424 OMAP7XX_MCBSP_RES_SZ,
437 omap7xx_mcbsp_pdata, 425 omap7xx_mcbsp_pdata,
@@ -449,7 +437,7 @@ static int __init omap1_mcbsp_init(void)
449 omap16xx_mcbsp_pdata, 437 omap16xx_mcbsp_pdata,
450 OMAP16XX_MCBSP_COUNT); 438 OMAP16XX_MCBSP_COUNT);
451 439
452 return omap_mcbsp_init(); 440 return 0;
453} 441}
454 442
455arch_initcall(omap1_mcbsp_init); 443arch_initcall(omap1_mcbsp_init);
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index a8ba7b96dcd1..e20c8ab80b0e 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -33,7 +33,6 @@ config ARCH_OMAP3
33 default y 33 default y
34 select CPU_V7 34 select CPU_V7
35 select USB_ARCH_HAS_EHCI 35 select USB_ARCH_HAS_EHCI
36 select ARM_L1_CACHE_SHIFT_6 if !ARCH_OMAP4
37 select ARCH_HAS_OPP 36 select ARCH_HAS_OPP
38 select PM_OPP if PM 37 select PM_OPP if PM
39 select ARM_CPU_SUSPEND if PM 38 select ARM_CPU_SUSPEND if PM
@@ -214,13 +213,12 @@ config MACH_OMAP3_PANDORA
214 depends on ARCH_OMAP3 213 depends on ARCH_OMAP3
215 default y 214 default y
216 select OMAP_PACKAGE_CBB 215 select OMAP_PACKAGE_CBB
217 select REGULATOR_FIXED_VOLTAGE 216 select REGULATOR_FIXED_VOLTAGE if REGULATOR
218 217
219config MACH_OMAP3_TOUCHBOOK 218config MACH_OMAP3_TOUCHBOOK
220 bool "OMAP3 Touch Book" 219 bool "OMAP3 Touch Book"
221 depends on ARCH_OMAP3 220 depends on ARCH_OMAP3
222 default y 221 default y
223 select BACKLIGHT_CLASS_DEVICE
224 222
225config MACH_OMAP_3430SDP 223config MACH_OMAP_3430SDP
226 bool "OMAP 3430 SDP board" 224 bool "OMAP 3430 SDP board"
@@ -266,7 +264,7 @@ config MACH_OMAP_ZOOM2
266 select SERIAL_8250 264 select SERIAL_8250
267 select SERIAL_CORE_CONSOLE 265 select SERIAL_CORE_CONSOLE
268 select SERIAL_8250_CONSOLE 266 select SERIAL_8250_CONSOLE
269 select REGULATOR_FIXED_VOLTAGE 267 select REGULATOR_FIXED_VOLTAGE if REGULATOR
270 268
271config MACH_OMAP_ZOOM3 269config MACH_OMAP_ZOOM3
272 bool "OMAP3630 Zoom3 board" 270 bool "OMAP3630 Zoom3 board"
@@ -276,7 +274,7 @@ config MACH_OMAP_ZOOM3
276 select SERIAL_8250 274 select SERIAL_8250
277 select SERIAL_CORE_CONSOLE 275 select SERIAL_CORE_CONSOLE
278 select SERIAL_8250_CONSOLE 276 select SERIAL_8250_CONSOLE
279 select REGULATOR_FIXED_VOLTAGE 277 select REGULATOR_FIXED_VOLTAGE if REGULATOR
280 278
281config MACH_CM_T35 279config MACH_CM_T35
282 bool "CompuLab CM-T35/CM-T3730 modules" 280 bool "CompuLab CM-T35/CM-T3730 modules"
@@ -335,7 +333,7 @@ config MACH_OMAP_4430SDP
335 depends on ARCH_OMAP4 333 depends on ARCH_OMAP4
336 select OMAP_PACKAGE_CBL 334 select OMAP_PACKAGE_CBL
337 select OMAP_PACKAGE_CBS 335 select OMAP_PACKAGE_CBS
338 select REGULATOR_FIXED_VOLTAGE 336 select REGULATOR_FIXED_VOLTAGE if REGULATOR
339 337
340config MACH_OMAP4_PANDA 338config MACH_OMAP4_PANDA
341 bool "OMAP4 Panda Board" 339 bool "OMAP4 Panda Board"
@@ -343,7 +341,7 @@ config MACH_OMAP4_PANDA
343 depends on ARCH_OMAP4 341 depends on ARCH_OMAP4
344 select OMAP_PACKAGE_CBL 342 select OMAP_PACKAGE_CBL
345 select OMAP_PACKAGE_CBS 343 select OMAP_PACKAGE_CBS
346 select REGULATOR_FIXED_VOLTAGE 344 select REGULATOR_FIXED_VOLTAGE if REGULATOR
347 345
348config OMAP3_EMU 346config OMAP3_EMU
349 bool "OMAP3 debugging peripherals" 347 bool "OMAP3 debugging peripherals"
@@ -366,8 +364,8 @@ config OMAP3_SDRC_AC_TIMING
366 going on could result in system crashes; 364 going on could result in system crashes;
367 365
368config OMAP4_ERRATA_I688 366config OMAP4_ERRATA_I688
369 bool "OMAP4 errata: Async Bridge Corruption (BROKEN)" 367 bool "OMAP4 errata: Async Bridge Corruption"
370 depends on ARCH_OMAP4 && BROKEN 368 depends on ARCH_OMAP4
371 select ARCH_HAS_BARRIERS 369 select ARCH_HAS_BARRIERS
372 help 370 help
373 If a data is stalled inside asynchronous bridge because of back 371 If a data is stalled inside asynchronous bridge because of back
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index fc9b238cbc19..06326a6e460d 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -11,13 +11,15 @@ hwmod-common = omap_hwmod.o \
11 omap_hwmod_common_data.o 11 omap_hwmod_common_data.o
12clock-common = clock.o clock_common_data.o \ 12clock-common = clock.o clock_common_data.o \
13 clkt_dpll.o clkt_clksel.o 13 clkt_dpll.o clkt_clksel.o
14secure-common = omap-smc.o omap-secure.o 14secure-common = omap-smc.o omap-secure.o
15 15
16obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common) $(secure-common) 16obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common)
17obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common) 17obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common)
18obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common) 18obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common)
19 19
20obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o 20ifneq ($(CONFIG_SND_OMAP_SOC_MCBSP),)
21obj-y += mcbsp.o
22endif
21 23
22obj-$(CONFIG_TWL4030_CORE) += omap_twl.o 24obj-$(CONFIG_TWL4030_CORE) += omap_twl.o
23 25
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index 39fba9df17fb..44cf1893829a 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -25,6 +25,7 @@
25#include <linux/regulator/fixed.h> 25#include <linux/regulator/fixed.h>
26#include <linux/leds.h> 26#include <linux/leds.h>
27#include <linux/leds_pwm.h> 27#include <linux/leds_pwm.h>
28#include <linux/platform_data/omap4-keypad.h>
28 29
29#include <mach/hardware.h> 30#include <mach/hardware.h>
30#include <asm/hardware/gic.h> 31#include <asm/hardware/gic.h>
@@ -41,6 +42,7 @@
41#include <video/omap-panel-nokia-dsi.h> 42#include <video/omap-panel-nokia-dsi.h>
42#include <video/omap-panel-picodlp.h> 43#include <video/omap-panel-picodlp.h>
43#include <linux/wl12xx.h> 44#include <linux/wl12xx.h>
45#include <linux/platform_data/omap-abe-twl6040.h>
44 46
45#include "mux.h" 47#include "mux.h"
46#include "hsmmc.h" 48#include "hsmmc.h"
@@ -52,8 +54,9 @@
52#define ETH_KS8851_QUART 138 54#define ETH_KS8851_QUART 138
53#define OMAP4_SFH7741_SENSOR_OUTPUT_GPIO 184 55#define OMAP4_SFH7741_SENSOR_OUTPUT_GPIO 184
54#define OMAP4_SFH7741_ENABLE_GPIO 188 56#define OMAP4_SFH7741_ENABLE_GPIO 188
55#define HDMI_GPIO_HPD 60 /* Hot plug pin for HDMI */ 57#define HDMI_GPIO_CT_CP_HPD 60 /* HPD mode enable/disable */
56#define HDMI_GPIO_LS_OE 41 /* Level shifter for HDMI */ 58#define HDMI_GPIO_LS_OE 41 /* Level shifter for HDMI */
59#define HDMI_GPIO_HPD 63 /* Hotplug detect */
57#define DISPLAY_SEL_GPIO 59 /* LCD2/PicoDLP switch */ 60#define DISPLAY_SEL_GPIO 59 /* LCD2/PicoDLP switch */
58#define DLP_POWER_ON_GPIO 40 61#define DLP_POWER_ON_GPIO 40
59 62
@@ -377,12 +380,40 @@ static struct platform_device sdp4430_dmic_codec = {
377 .id = -1, 380 .id = -1,
378}; 381};
379 382
383static struct omap_abe_twl6040_data sdp4430_abe_audio_data = {
384 .card_name = "SDP4430",
385 .has_hs = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT,
386 .has_hf = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT,
387 .has_ep = 1,
388 .has_aux = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT,
389 .has_vibra = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT,
390
391 .has_dmic = 1,
392 .has_hsmic = 1,
393 .has_mainmic = 1,
394 .has_submic = 1,
395 .has_afm = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT,
396
397 .jack_detection = 1,
398 /* MCLK input is 38.4MHz */
399 .mclk_freq = 38400000,
400};
401
402static struct platform_device sdp4430_abe_audio = {
403 .name = "omap-abe-twl6040",
404 .id = -1,
405 .dev = {
406 .platform_data = &sdp4430_abe_audio_data,
407 },
408};
409
380static struct platform_device *sdp4430_devices[] __initdata = { 410static struct platform_device *sdp4430_devices[] __initdata = {
381 &sdp4430_gpio_keys_device, 411 &sdp4430_gpio_keys_device,
382 &sdp4430_leds_gpio, 412 &sdp4430_leds_gpio,
383 &sdp4430_leds_pwm, 413 &sdp4430_leds_pwm,
384 &sdp4430_vbat, 414 &sdp4430_vbat,
385 &sdp4430_dmic_codec, 415 &sdp4430_dmic_codec,
416 &sdp4430_abe_audio,
386}; 417};
387 418
388static struct omap_musb_board_data musb_board_data = { 419static struct omap_musb_board_data musb_board_data = {
@@ -603,8 +634,9 @@ static void __init omap_sfh7741prox_init(void)
603} 634}
604 635
605static struct gpio sdp4430_hdmi_gpios[] = { 636static struct gpio sdp4430_hdmi_gpios[] = {
606 { HDMI_GPIO_HPD, GPIOF_OUT_INIT_HIGH, "hdmi_gpio_hpd" }, 637 { HDMI_GPIO_CT_CP_HPD, GPIOF_OUT_INIT_HIGH, "hdmi_gpio_ct_cp_hpd" },
607 { HDMI_GPIO_LS_OE, GPIOF_OUT_INIT_HIGH, "hdmi_gpio_ls_oe" }, 638 { HDMI_GPIO_LS_OE, GPIOF_OUT_INIT_HIGH, "hdmi_gpio_ls_oe" },
639 { HDMI_GPIO_HPD, GPIOF_DIR_IN, "hdmi_gpio_hpd" },
608}; 640};
609 641
610static int sdp4430_panel_enable_hdmi(struct omap_dss_device *dssdev) 642static int sdp4430_panel_enable_hdmi(struct omap_dss_device *dssdev)
@@ -621,8 +653,7 @@ static int sdp4430_panel_enable_hdmi(struct omap_dss_device *dssdev)
621 653
622static void sdp4430_panel_disable_hdmi(struct omap_dss_device *dssdev) 654static void sdp4430_panel_disable_hdmi(struct omap_dss_device *dssdev)
623{ 655{
624 gpio_free(HDMI_GPIO_LS_OE); 656 gpio_free_array(sdp4430_hdmi_gpios, ARRAY_SIZE(sdp4430_hdmi_gpios));
625 gpio_free(HDMI_GPIO_HPD);
626} 657}
627 658
628static struct nokia_dsi_panel_data dsi1_panel = { 659static struct nokia_dsi_panel_data dsi1_panel = {
@@ -738,6 +769,10 @@ static void sdp4430_lcd_init(void)
738 pr_err("%s: Could not get lcd2_reset_gpio\n", __func__); 769 pr_err("%s: Could not get lcd2_reset_gpio\n", __func__);
739} 770}
740 771
772static struct omap_dss_hdmi_data sdp4430_hdmi_data = {
773 .hpd_gpio = HDMI_GPIO_HPD,
774};
775
741static struct omap_dss_device sdp4430_hdmi_device = { 776static struct omap_dss_device sdp4430_hdmi_device = {
742 .name = "hdmi", 777 .name = "hdmi",
743 .driver_name = "hdmi_panel", 778 .driver_name = "hdmi_panel",
@@ -745,6 +780,7 @@ static struct omap_dss_device sdp4430_hdmi_device = {
745 .platform_enable = sdp4430_panel_enable_hdmi, 780 .platform_enable = sdp4430_panel_enable_hdmi,
746 .platform_disable = sdp4430_panel_disable_hdmi, 781 .platform_disable = sdp4430_panel_disable_hdmi,
747 .channel = OMAP_DSS_CHANNEL_DIGIT, 782 .channel = OMAP_DSS_CHANNEL_DIGIT,
783 .data = &sdp4430_hdmi_data,
748}; 784};
749 785
750static struct picodlp_panel_data sdp4430_picodlp_pdata = { 786static struct picodlp_panel_data sdp4430_picodlp_pdata = {
@@ -808,7 +844,7 @@ static struct omap_dss_board_info sdp4430_dss_data = {
808 .default_device = &sdp4430_lcd_device, 844 .default_device = &sdp4430_lcd_device,
809}; 845};
810 846
811static void omap_4430sdp_display_init(void) 847static void __init omap_4430sdp_display_init(void)
812{ 848{
813 int r; 849 int r;
814 850
@@ -829,6 +865,10 @@ static void omap_4430sdp_display_init(void)
829 omap_hdmi_init(OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP); 865 omap_hdmi_init(OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP);
830 else 866 else
831 omap_hdmi_init(0); 867 omap_hdmi_init(0);
868
869 omap_mux_init_gpio(HDMI_GPIO_LS_OE, OMAP_PIN_OUTPUT);
870 omap_mux_init_gpio(HDMI_GPIO_CT_CP_HPD, OMAP_PIN_OUTPUT);
871 omap_mux_init_gpio(HDMI_GPIO_HPD, OMAP_PIN_INPUT_PULLDOWN);
832} 872}
833 873
834#ifdef CONFIG_OMAP_MUX 874#ifdef CONFIG_OMAP_MUX
@@ -841,7 +881,7 @@ static struct omap_board_mux board_mux[] __initdata = {
841#define board_mux NULL 881#define board_mux NULL
842 #endif 882 #endif
843 883
844static void omap4_sdp4430_wifi_mux_init(void) 884static void __init omap4_sdp4430_wifi_mux_init(void)
845{ 885{
846 omap_mux_init_gpio(GPIO_WIFI_IRQ, OMAP_PIN_INPUT | 886 omap_mux_init_gpio(GPIO_WIFI_IRQ, OMAP_PIN_INPUT |
847 OMAP_PIN_OFF_WAKEUPENABLE); 887 OMAP_PIN_OFF_WAKEUPENABLE);
@@ -868,12 +908,17 @@ static struct wl12xx_platform_data omap4_sdp4430_wlan_data __initdata = {
868 .board_tcxo_clock = WL12XX_TCXOCLOCK_26, 908 .board_tcxo_clock = WL12XX_TCXOCLOCK_26,
869}; 909};
870 910
871static void omap4_sdp4430_wifi_init(void) 911static void __init omap4_sdp4430_wifi_init(void)
872{ 912{
913 int ret;
914
873 omap4_sdp4430_wifi_mux_init(); 915 omap4_sdp4430_wifi_mux_init();
874 if (wl12xx_set_platform_data(&omap4_sdp4430_wlan_data)) 916 ret = wl12xx_set_platform_data(&omap4_sdp4430_wlan_data);
875 pr_err("Error setting wl12xx data\n"); 917 if (ret)
876 platform_device_register(&omap_vwlan_device); 918 pr_err("Error setting wl12xx data: %d\n", ret);
919 ret = platform_device_register(&omap_vwlan_device);
920 if (ret)
921 pr_err("Error registering wl12xx device: %d\n", ret);
877} 922}
878 923
879static void __init omap_4430sdp_init(void) 924static void __init omap_4430sdp_init(void)
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index e921e3be24a4..d73316ed4207 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -437,7 +437,7 @@ static struct usbhs_omap_board_data usbhs_bdata __initdata = {
437 .reset_gpio_port[2] = -EINVAL 437 .reset_gpio_port[2] = -EINVAL
438}; 438};
439 439
440static void cm_t35_init_usbh(void) 440static void __init cm_t35_init_usbh(void)
441{ 441{
442 int err; 442 int err;
443 443
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index d58756060483..45fdfe2bd9d5 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -17,6 +17,7 @@
17#include <linux/i2c/twl.h> 17#include <linux/i2c/twl.h>
18 18
19#include <mach/hardware.h> 19#include <mach/hardware.h>
20#include <asm/hardware/gic.h>
20#include <asm/mach/arch.h> 21#include <asm/mach/arch.h>
21 22
22#include <plat/board.h> 23#include <plat/board.h>
@@ -67,7 +68,7 @@ static void __init omap_generic_init(void)
67{ 68{
68 struct device_node *node = of_find_matching_node(NULL, intc_match); 69 struct device_node *node = of_find_matching_node(NULL, intc_match);
69 if (node) 70 if (node)
70 irq_domain_add_simple(node, 0); 71 irq_domain_add_legacy(node, 32, 0, 0, &irq_domain_simple_ops, NULL);
71 72
72 omap_sdrc_init(NULL, NULL); 73 omap_sdrc_init(NULL, NULL);
73 74
@@ -102,6 +103,7 @@ DT_MACHINE_START(OMAP242X_DT, "Generic OMAP2420 (Flattened Device Tree)")
102 .map_io = omap242x_map_io, 103 .map_io = omap242x_map_io,
103 .init_early = omap2420_init_early, 104 .init_early = omap2420_init_early,
104 .init_irq = omap2_init_irq, 105 .init_irq = omap2_init_irq,
106 .handle_irq = omap2_intc_handle_irq,
105 .init_machine = omap_generic_init, 107 .init_machine = omap_generic_init,
106 .timer = &omap2_timer, 108 .timer = &omap2_timer,
107 .dt_compat = omap242x_boards_compat, 109 .dt_compat = omap242x_boards_compat,
@@ -141,6 +143,7 @@ DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)")
141 .map_io = omap3_map_io, 143 .map_io = omap3_map_io,
142 .init_early = omap3430_init_early, 144 .init_early = omap3430_init_early,
143 .init_irq = omap3_init_irq, 145 .init_irq = omap3_init_irq,
146 .handle_irq = omap3_intc_handle_irq,
144 .init_machine = omap3_init, 147 .init_machine = omap3_init,
145 .timer = &omap3_timer, 148 .timer = &omap3_timer,
146 .dt_compat = omap3_boards_compat, 149 .dt_compat = omap3_boards_compat,
@@ -160,6 +163,7 @@ DT_MACHINE_START(OMAP4_DT, "Generic OMAP4 (Flattened Device Tree)")
160 .map_io = omap4_map_io, 163 .map_io = omap4_map_io,
161 .init_early = omap4430_init_early, 164 .init_early = omap4430_init_early,
162 .init_irq = gic_init_irq, 165 .init_irq = gic_init_irq,
166 .handle_irq = gic_handle_irq,
163 .init_machine = omap4_init, 167 .init_machine = omap4_init,
164 .timer = &omap4_timer, 168 .timer = &omap4_timer,
165 .dt_compat = omap4_boards_compat, 169 .dt_compat = omap4_boards_compat,
diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
index 42a4d11fad23..672262717601 100644
--- a/arch/arm/mach-omap2/board-n8x0.c
+++ b/arch/arm/mach-omap2/board-n8x0.c
@@ -371,7 +371,11 @@ static void n8x0_mmc_callback(void *data, u8 card_mask)
371 else 371 else
372 *openp = 0; 372 *openp = 0;
373 373
374#ifdef CONFIG_MMC_OMAP
374 omap_mmc_notify_cover_event(mmc_device, index, *openp); 375 omap_mmc_notify_cover_event(mmc_device, index, *openp);
376#else
377 pr_warn("MMC: notify cover event not available\n");
378#endif
375} 379}
376 380
377static int n8x0_mmc_late_init(struct device *dev) 381static int n8x0_mmc_late_init(struct device *dev)
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index 003fe34c9343..c877236a8442 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -381,7 +381,7 @@ static int omap3evm_twl_gpio_setup(struct device *dev,
381 gpio_request_one(gpio + 7, GPIOF_OUT_INIT_LOW, "EN_DVI"); 381 gpio_request_one(gpio + 7, GPIOF_OUT_INIT_LOW, "EN_DVI");
382 382
383 /* TWL4030_GPIO_MAX + 1 == ledB (out, active low LED) */ 383 /* TWL4030_GPIO_MAX + 1 == ledB (out, active low LED) */
384 gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1; 384 gpio_leds[0].gpio = gpio + TWL4030_GPIO_MAX + 1;
385 385
386 platform_device_register(&leds_gpio); 386 platform_device_register(&leds_gpio);
387 387
@@ -617,6 +617,21 @@ static struct gpio omap3_evm_ehci_gpios[] __initdata = {
617 { OMAP3_EVM_EHCI_SELECT, GPIOF_OUT_INIT_LOW, "select EHCI port" }, 617 { OMAP3_EVM_EHCI_SELECT, GPIOF_OUT_INIT_LOW, "select EHCI port" },
618}; 618};
619 619
620static void __init omap3_evm_wl12xx_init(void)
621{
622#ifdef CONFIG_WL12XX_PLATFORM_DATA
623 int ret;
624
625 /* WL12xx WLAN Init */
626 ret = wl12xx_set_platform_data(&omap3evm_wlan_data);
627 if (ret)
628 pr_err("error setting wl12xx data: %d\n", ret);
629 ret = platform_device_register(&omap3evm_wlan_regulator);
630 if (ret)
631 pr_err("error registering wl12xx device: %d\n", ret);
632#endif
633}
634
620static void __init omap3_evm_init(void) 635static void __init omap3_evm_init(void)
621{ 636{
622 omap3_evm_get_revision(); 637 omap3_evm_get_revision();
@@ -665,13 +680,7 @@ static void __init omap3_evm_init(void)
665 omap_ads7846_init(1, OMAP3_EVM_TS_GPIO, 310, NULL); 680 omap_ads7846_init(1, OMAP3_EVM_TS_GPIO, 310, NULL);
666 omap3evm_init_smsc911x(); 681 omap3evm_init_smsc911x();
667 omap3_evm_display_init(); 682 omap3_evm_display_init();
668 683 omap3_evm_wl12xx_init();
669#ifdef CONFIG_WL12XX_PLATFORM_DATA
670 /* WL12xx WLAN Init */
671 if (wl12xx_set_platform_data(&omap3evm_wlan_data))
672 pr_err("error setting wl12xx data\n");
673 platform_device_register(&omap3evm_wlan_regulator);
674#endif
675} 684}
676 685
677MACHINE_START(OMAP3EVM, "OMAP3 EVM") 686MACHINE_START(OMAP3EVM, "OMAP3 EVM")
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index 30ad40db2cf3..e4415917693f 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -28,6 +28,7 @@
28#include <linux/regulator/machine.h> 28#include <linux/regulator/machine.h>
29#include <linux/regulator/fixed.h> 29#include <linux/regulator/fixed.h>
30#include <linux/wl12xx.h> 30#include <linux/wl12xx.h>
31#include <linux/platform_data/omap-abe-twl6040.h>
31 32
32#include <mach/hardware.h> 33#include <mach/hardware.h>
33#include <asm/hardware/gic.h> 34#include <asm/hardware/gic.h>
@@ -51,8 +52,9 @@
51#define GPIO_HUB_NRESET 62 52#define GPIO_HUB_NRESET 62
52#define GPIO_WIFI_PMENA 43 53#define GPIO_WIFI_PMENA 43
53#define GPIO_WIFI_IRQ 53 54#define GPIO_WIFI_IRQ 53
54#define HDMI_GPIO_HPD 60 /* Hot plug pin for HDMI */ 55#define HDMI_GPIO_CT_CP_HPD 60 /* HPD mode enable/disable */
55#define HDMI_GPIO_LS_OE 41 /* Level shifter for HDMI */ 56#define HDMI_GPIO_LS_OE 41 /* Level shifter for HDMI */
57#define HDMI_GPIO_HPD 63 /* Hotplug detect */
56 58
57/* wl127x BT, FM, GPS connectivity chip */ 59/* wl127x BT, FM, GPS connectivity chip */
58static int wl1271_gpios[] = {46, -1, -1}; 60static int wl1271_gpios[] = {46, -1, -1};
@@ -90,9 +92,34 @@ static struct platform_device leds_gpio = {
90 }, 92 },
91}; 93};
92 94
95static struct omap_abe_twl6040_data panda_abe_audio_data = {
96 /* Audio out */
97 .has_hs = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT,
98 /* HandsFree through expasion connector */
99 .has_hf = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT,
100 /* PandaBoard: FM TX, PandaBoardES: can be connected to audio out */
101 .has_aux = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT,
102 /* PandaBoard: FM RX, PandaBoardES: audio in */
103 .has_afm = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT,
104 /* No jack detection. */
105 .jack_detection = 0,
106 /* MCLK input is 38.4MHz */
107 .mclk_freq = 38400000,
108
109};
110
111static struct platform_device panda_abe_audio = {
112 .name = "omap-abe-twl6040",
113 .id = -1,
114 .dev = {
115 .platform_data = &panda_abe_audio_data,
116 },
117};
118
93static struct platform_device *panda_devices[] __initdata = { 119static struct platform_device *panda_devices[] __initdata = {
94 &leds_gpio, 120 &leds_gpio,
95 &wl1271_device, 121 &wl1271_device,
122 &panda_abe_audio,
96}; 123};
97 124
98static const struct usbhs_omap_board_data usbhs_bdata __initconst = { 125static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
@@ -251,8 +278,25 @@ static int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
251 return 0; 278 return 0;
252} 279}
253 280
281static struct twl4030_codec_data twl6040_codec = {
282 /* single-step ramp for headset and handsfree */
283 .hs_left_step = 0x0f,
284 .hs_right_step = 0x0f,
285 .hf_left_step = 0x1d,
286 .hf_right_step = 0x1d,
287};
288
289static struct twl4030_audio_data twl6040_audio = {
290 .codec = &twl6040_codec,
291 .audpwron_gpio = 127,
292 .naudint_irq = OMAP44XX_IRQ_SYS_2N,
293 .irq_base = TWL6040_CODEC_IRQ_BASE,
294};
295
254/* Panda board uses the common PMIC configuration */ 296/* Panda board uses the common PMIC configuration */
255static struct twl4030_platform_data omap4_panda_twldata; 297static struct twl4030_platform_data omap4_panda_twldata = {
298 .audio = &twl6040_audio,
299};
256 300
257/* 301/*
258 * Display monitor features are burnt in their EEPROM as EDID data. The EEPROM 302 * Display monitor features are burnt in their EEPROM as EDID data. The EEPROM
@@ -413,8 +457,9 @@ int __init omap4_panda_dvi_init(void)
413} 457}
414 458
415static struct gpio panda_hdmi_gpios[] = { 459static struct gpio panda_hdmi_gpios[] = {
416 { HDMI_GPIO_HPD, GPIOF_OUT_INIT_HIGH, "hdmi_gpio_hpd" }, 460 { HDMI_GPIO_CT_CP_HPD, GPIOF_OUT_INIT_HIGH, "hdmi_gpio_ct_cp_hpd" },
417 { HDMI_GPIO_LS_OE, GPIOF_OUT_INIT_HIGH, "hdmi_gpio_ls_oe" }, 461 { HDMI_GPIO_LS_OE, GPIOF_OUT_INIT_HIGH, "hdmi_gpio_ls_oe" },
462 { HDMI_GPIO_HPD, GPIOF_DIR_IN, "hdmi_gpio_hpd" },
418}; 463};
419 464
420static int omap4_panda_panel_enable_hdmi(struct omap_dss_device *dssdev) 465static int omap4_panda_panel_enable_hdmi(struct omap_dss_device *dssdev)
@@ -431,10 +476,13 @@ static int omap4_panda_panel_enable_hdmi(struct omap_dss_device *dssdev)
431 476
432static void omap4_panda_panel_disable_hdmi(struct omap_dss_device *dssdev) 477static void omap4_panda_panel_disable_hdmi(struct omap_dss_device *dssdev)
433{ 478{
434 gpio_free(HDMI_GPIO_LS_OE); 479 gpio_free_array(panda_hdmi_gpios, ARRAY_SIZE(panda_hdmi_gpios));
435 gpio_free(HDMI_GPIO_HPD);
436} 480}
437 481
482static struct omap_dss_hdmi_data omap4_panda_hdmi_data = {
483 .hpd_gpio = HDMI_GPIO_HPD,
484};
485
438static struct omap_dss_device omap4_panda_hdmi_device = { 486static struct omap_dss_device omap4_panda_hdmi_device = {
439 .name = "hdmi", 487 .name = "hdmi",
440 .driver_name = "hdmi_panel", 488 .driver_name = "hdmi_panel",
@@ -442,6 +490,7 @@ static struct omap_dss_device omap4_panda_hdmi_device = {
442 .platform_enable = omap4_panda_panel_enable_hdmi, 490 .platform_enable = omap4_panda_panel_enable_hdmi,
443 .platform_disable = omap4_panda_panel_disable_hdmi, 491 .platform_disable = omap4_panda_panel_disable_hdmi,
444 .channel = OMAP_DSS_CHANNEL_DIGIT, 492 .channel = OMAP_DSS_CHANNEL_DIGIT,
493 .data = &omap4_panda_hdmi_data,
445}; 494};
446 495
447static struct omap_dss_device *omap4_panda_dss_devices[] = { 496static struct omap_dss_device *omap4_panda_dss_devices[] = {
@@ -473,19 +522,40 @@ void omap4_panda_display_init(void)
473 omap_hdmi_init(OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP); 522 omap_hdmi_init(OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP);
474 else 523 else
475 omap_hdmi_init(0); 524 omap_hdmi_init(0);
525
526 omap_mux_init_gpio(HDMI_GPIO_LS_OE, OMAP_PIN_OUTPUT);
527 omap_mux_init_gpio(HDMI_GPIO_CT_CP_HPD, OMAP_PIN_OUTPUT);
528 omap_mux_init_gpio(HDMI_GPIO_HPD, OMAP_PIN_INPUT_PULLDOWN);
529}
530
531static void omap4_panda_init_rev(void)
532{
533 if (cpu_is_omap443x()) {
534 /* PandaBoard 4430 */
535 /* ASoC audio configuration */
536 panda_abe_audio_data.card_name = "PandaBoard";
537 panda_abe_audio_data.has_hsmic = 1;
538 } else {
539 /* PandaBoard ES */
540 /* ASoC audio configuration */
541 panda_abe_audio_data.card_name = "PandaBoardES";
542 }
476} 543}
477 544
478static void __init omap4_panda_init(void) 545static void __init omap4_panda_init(void)
479{ 546{
480 int package = OMAP_PACKAGE_CBS; 547 int package = OMAP_PACKAGE_CBS;
548 int ret;
481 549
482 if (omap_rev() == OMAP4430_REV_ES1_0) 550 if (omap_rev() == OMAP4430_REV_ES1_0)
483 package = OMAP_PACKAGE_CBL; 551 package = OMAP_PACKAGE_CBL;
484 omap4_mux_init(board_mux, NULL, package); 552 omap4_mux_init(board_mux, NULL, package);
485 553
486 if (wl12xx_set_platform_data(&omap_panda_wlan_data)) 554 ret = wl12xx_set_platform_data(&omap_panda_wlan_data);
487 pr_err("error setting wl12xx data\n"); 555 if (ret)
556 pr_err("error setting wl12xx data: %d\n", ret);
488 557
558 omap4_panda_init_rev();
489 omap4_panda_i2c_init(); 559 omap4_panda_i2c_init();
490 platform_add_devices(panda_devices, ARRAY_SIZE(panda_devices)); 560 platform_add_devices(panda_devices, ARRAY_SIZE(panda_devices));
491 platform_device_register(&omap_vwlan_device); 561 platform_device_register(&omap_vwlan_device);
diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c
index 8d7ce11cfeaf..c126461836ac 100644
--- a/arch/arm/mach-omap2/board-zoom-peripherals.c
+++ b/arch/arm/mach-omap2/board-zoom-peripherals.c
@@ -296,8 +296,10 @@ static void enable_board_wakeup_source(void)
296 296
297void __init zoom_peripherals_init(void) 297void __init zoom_peripherals_init(void)
298{ 298{
299 if (wl12xx_set_platform_data(&omap_zoom_wlan_data)) 299 int ret = wl12xx_set_platform_data(&omap_zoom_wlan_data);
300 pr_err("error setting wl12xx data\n"); 300
301 if (ret)
302 pr_err("error setting wl12xx data: %d\n", ret);
301 303
302 omap_i2c_init(); 304 omap_i2c_init();
303 platform_device_register(&omap_vwlan_device); 305 platform_device_register(&omap_vwlan_device);
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index febffde2ff10..7e9338e8d684 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -132,6 +132,7 @@ void omap3_map_io(void);
132void am33xx_map_io(void); 132void am33xx_map_io(void);
133void omap4_map_io(void); 133void omap4_map_io(void);
134void ti81xx_map_io(void); 134void ti81xx_map_io(void);
135void omap_barriers_init(void);
135 136
136/** 137/**
137 * omap_test_timeout - busy-loop, testing a condition 138 * omap_test_timeout - busy-loop, testing a condition
diff --git a/arch/arm/mach-omap2/cpuidle44xx.c b/arch/arm/mach-omap2/cpuidle44xx.c
index cfdbb86bc84e..72e018b9b260 100644
--- a/arch/arm/mach-omap2/cpuidle44xx.c
+++ b/arch/arm/mach-omap2/cpuidle44xx.c
@@ -65,7 +65,6 @@ static int omap4_enter_idle(struct cpuidle_device *dev,
65 struct timespec ts_preidle, ts_postidle, ts_idle; 65 struct timespec ts_preidle, ts_postidle, ts_idle;
66 u32 cpu1_state; 66 u32 cpu1_state;
67 int idle_time; 67 int idle_time;
68 int new_state_idx;
69 int cpu_id = smp_processor_id(); 68 int cpu_id = smp_processor_id();
70 69
71 /* Used to keep track of the total time in idle */ 70 /* Used to keep track of the total time in idle */
@@ -84,8 +83,8 @@ static int omap4_enter_idle(struct cpuidle_device *dev,
84 */ 83 */
85 cpu1_state = pwrdm_read_pwrst(cpu1_pd); 84 cpu1_state = pwrdm_read_pwrst(cpu1_pd);
86 if (cpu1_state != PWRDM_POWER_OFF) { 85 if (cpu1_state != PWRDM_POWER_OFF) {
87 new_state_idx = drv->safe_state_index; 86 index = drv->safe_state_index;
88 cx = cpuidle_get_statedata(&dev->states_usage[new_state_idx]); 87 cx = cpuidle_get_statedata(&dev->states_usage[index]);
89 } 88 }
90 89
91 if (index > 0) 90 if (index > 0)
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 0b510ad01a00..f713818be06f 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -17,6 +17,7 @@
17#include <linux/err.h> 17#include <linux/err.h>
18#include <linux/slab.h> 18#include <linux/slab.h>
19#include <linux/of.h> 19#include <linux/of.h>
20#include <linux/platform_data/omap4-keypad.h>
20 21
21#include <mach/hardware.h> 22#include <mach/hardware.h>
22#include <mach/irqs.h> 23#include <mach/irqs.h>
@@ -26,7 +27,6 @@
26 27
27#include <plat/tc.h> 28#include <plat/tc.h>
28#include <plat/board.h> 29#include <plat/board.h>
29#include <plat/mcbsp.h>
30#include <plat/mmc.h> 30#include <plat/mmc.h>
31#include <plat/dma.h> 31#include <plat/dma.h>
32#include <plat/omap_hwmod.h> 32#include <plat/omap_hwmod.h>
@@ -304,29 +304,8 @@ static struct platform_device omap_pcm = {
304 .id = -1, 304 .id = -1,
305}; 305};
306 306
307/*
308 * OMAP2420 has 2 McBSP ports
309 * OMAP2430 has 5 McBSP ports
310 * OMAP3 has 5 McBSP ports
311 * OMAP4 has 4 McBSP ports
312 */
313OMAP_MCBSP_PLATFORM_DEVICE(1);
314OMAP_MCBSP_PLATFORM_DEVICE(2);
315OMAP_MCBSP_PLATFORM_DEVICE(3);
316OMAP_MCBSP_PLATFORM_DEVICE(4);
317OMAP_MCBSP_PLATFORM_DEVICE(5);
318
319static void omap_init_audio(void) 307static void omap_init_audio(void)
320{ 308{
321 platform_device_register(&omap_mcbsp1);
322 platform_device_register(&omap_mcbsp2);
323 if (cpu_is_omap243x() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
324 platform_device_register(&omap_mcbsp3);
325 platform_device_register(&omap_mcbsp4);
326 }
327 if (cpu_is_omap243x() || cpu_is_omap34xx())
328 platform_device_register(&omap_mcbsp5);
329
330 platform_device_register(&omap_pcm); 309 platform_device_register(&omap_pcm);
331} 310}
332 311
@@ -405,6 +384,7 @@ static int omap_mcspi_init(struct omap_hwmod *oh, void *unused)
405 break; 384 break;
406 default: 385 default:
407 pr_err("Invalid McSPI Revision value\n"); 386 pr_err("Invalid McSPI Revision value\n");
387 kfree(pdata);
408 return -EINVAL; 388 return -EINVAL;
409 } 389 }
410 390
diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c
index 3c446d1a1781..3677b1f58b85 100644
--- a/arch/arm/mach-omap2/display.c
+++ b/arch/arm/mach-omap2/display.c
@@ -103,12 +103,8 @@ static void omap4_hdmi_mux_pads(enum omap_hdmi_flags flags)
103 u32 reg; 103 u32 reg;
104 u16 control_i2c_1; 104 u16 control_i2c_1;
105 105
106 /* PAD0_HDMI_HPD_PAD1_HDMI_CEC */
107 omap_mux_init_signal("hdmi_hpd",
108 OMAP_PIN_INPUT_PULLUP);
109 omap_mux_init_signal("hdmi_cec", 106 omap_mux_init_signal("hdmi_cec",
110 OMAP_PIN_INPUT_PULLUP); 107 OMAP_PIN_INPUT_PULLUP);
111 /* PAD0_HDMI_DDC_SCL_PAD1_HDMI_DDC_SDA */
112 omap_mux_init_signal("hdmi_ddc_scl", 108 omap_mux_init_signal("hdmi_ddc_scl",
113 OMAP_PIN_INPUT_PULLUP); 109 OMAP_PIN_INPUT_PULLUP);
114 omap_mux_init_signal("hdmi_ddc_sda", 110 omap_mux_init_signal("hdmi_ddc_sda",
diff --git a/arch/arm/mach-omap2/gpmc-smsc911x.c b/arch/arm/mach-omap2/gpmc-smsc911x.c
index 997033129d26..bbb870c04a5e 100644
--- a/arch/arm/mach-omap2/gpmc-smsc911x.c
+++ b/arch/arm/mach-omap2/gpmc-smsc911x.c
@@ -19,6 +19,8 @@
19#include <linux/interrupt.h> 19#include <linux/interrupt.h>
20#include <linux/io.h> 20#include <linux/io.h>
21#include <linux/smsc911x.h> 21#include <linux/smsc911x.h>
22#include <linux/regulator/fixed.h>
23#include <linux/regulator/machine.h>
22 24
23#include <plat/board.h> 25#include <plat/board.h>
24#include <plat/gpmc.h> 26#include <plat/gpmc.h>
@@ -42,6 +44,50 @@ static struct smsc911x_platform_config gpmc_smsc911x_config = {
42 .flags = SMSC911X_USE_16BIT, 44 .flags = SMSC911X_USE_16BIT,
43}; 45};
44 46
47static struct regulator_consumer_supply gpmc_smsc911x_supply[] = {
48 REGULATOR_SUPPLY("vddvario", "smsc911x.0"),
49 REGULATOR_SUPPLY("vdd33a", "smsc911x.0"),
50};
51
52/* Generic regulator definition to satisfy smsc911x */
53static struct regulator_init_data gpmc_smsc911x_reg_init_data = {
54 .constraints = {
55 .min_uV = 3300000,
56 .max_uV = 3300000,
57 .valid_modes_mask = REGULATOR_MODE_NORMAL
58 | REGULATOR_MODE_STANDBY,
59 .valid_ops_mask = REGULATOR_CHANGE_MODE
60 | REGULATOR_CHANGE_STATUS,
61 },
62 .num_consumer_supplies = ARRAY_SIZE(gpmc_smsc911x_supply),
63 .consumer_supplies = gpmc_smsc911x_supply,
64};
65
66static struct fixed_voltage_config gpmc_smsc911x_fixed_reg_data = {
67 .supply_name = "gpmc_smsc911x",
68 .microvolts = 3300000,
69 .gpio = -EINVAL,
70 .startup_delay = 0,
71 .enable_high = 0,
72 .enabled_at_boot = 1,
73 .init_data = &gpmc_smsc911x_reg_init_data,
74};
75
76/*
77 * Platform device id of 42 is a temporary fix to avoid conflicts
78 * with other reg-fixed-voltage devices. The real fix should
79 * involve the driver core providing a way of dynamically
80 * assigning a unique id on registration for platform devices
81 * in the same name space.
82 */
83static struct platform_device gpmc_smsc911x_regulator = {
84 .name = "reg-fixed-voltage",
85 .id = 42,
86 .dev = {
87 .platform_data = &gpmc_smsc911x_fixed_reg_data,
88 },
89};
90
45/* 91/*
46 * Initialize smsc911x device connected to the GPMC. Note that we 92 * Initialize smsc911x device connected to the GPMC. Note that we
47 * assume that pin multiplexing is done in the board-*.c file, 93 * assume that pin multiplexing is done in the board-*.c file,
@@ -55,6 +101,12 @@ void __init gpmc_smsc911x_init(struct omap_smsc911x_platform_data *board_data)
55 101
56 gpmc_cfg = board_data; 102 gpmc_cfg = board_data;
57 103
104 ret = platform_device_register(&gpmc_smsc911x_regulator);
105 if (ret < 0) {
106 pr_err("Unable to register smsc911x regulators: %d\n", ret);
107 return;
108 }
109
58 if (gpmc_cs_request(gpmc_cfg->cs, SZ_16M, &cs_mem_base) < 0) { 110 if (gpmc_cs_request(gpmc_cfg->cs, SZ_16M, &cs_mem_base) < 0) {
59 pr_err("Failed to request GPMC mem region\n"); 111 pr_err("Failed to request GPMC mem region\n");
60 return; 112 return;
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 130034bf01d5..dfffbbf4c009 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -528,7 +528,13 @@ int gpmc_cs_configure(int cs, int cmd, int wval)
528 528
529 case GPMC_CONFIG_DEV_SIZE: 529 case GPMC_CONFIG_DEV_SIZE:
530 regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); 530 regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
531
532 /* clear 2 target bits */
533 regval &= ~GPMC_CONFIG1_DEVICESIZE(3);
534
535 /* set the proper value */
531 regval |= GPMC_CONFIG1_DEVICESIZE(wval); 536 regval |= GPMC_CONFIG1_DEVICESIZE(wval);
537
532 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval); 538 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
533 break; 539 break;
534 540
diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
index bd844af13af5..19dd1657245c 100644
--- a/arch/arm/mach-omap2/hsmmc.c
+++ b/arch/arm/mach-omap2/hsmmc.c
@@ -175,14 +175,15 @@ static void hsmmc2_select_input_clk_src(struct omap_mmc_platform_data *mmc)
175{ 175{
176 u32 reg; 176 u32 reg;
177 177
178 if (mmc->slots[0].internal_clock) { 178 reg = omap_ctrl_readl(control_devconf1_offset);
179 reg = omap_ctrl_readl(control_devconf1_offset); 179 if (mmc->slots[0].internal_clock)
180 reg |= OMAP2_MMCSDIO2ADPCLKISEL; 180 reg |= OMAP2_MMCSDIO2ADPCLKISEL;
181 omap_ctrl_writel(reg, control_devconf1_offset); 181 else
182 } 182 reg &= ~OMAP2_MMCSDIO2ADPCLKISEL;
183 omap_ctrl_writel(reg, control_devconf1_offset);
183} 184}
184 185
185static void hsmmc23_before_set_reg(struct device *dev, int slot, 186static void hsmmc2_before_set_reg(struct device *dev, int slot,
186 int power_on, int vdd) 187 int power_on, int vdd)
187{ 188{
188 struct omap_mmc_platform_data *mmc = dev->platform_data; 189 struct omap_mmc_platform_data *mmc = dev->platform_data;
@@ -292,8 +293,8 @@ static inline void omap_hsmmc_mux(struct omap_mmc_platform_data *mmc_controller,
292 } 293 }
293} 294}
294 295
295static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c, 296static int omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
296 struct omap_mmc_platform_data *mmc) 297 struct omap_mmc_platform_data *mmc)
297{ 298{
298 char *hc_name; 299 char *hc_name;
299 300
@@ -407,14 +408,13 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
407 c->caps &= ~MMC_CAP_8_BIT_DATA; 408 c->caps &= ~MMC_CAP_8_BIT_DATA;
408 c->caps |= MMC_CAP_4_BIT_DATA; 409 c->caps |= MMC_CAP_4_BIT_DATA;
409 } 410 }
410 /* FALLTHROUGH */
411 case 3:
412 if (mmc->slots[0].features & HSMMC_HAS_PBIAS) { 411 if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
413 /* off-chip level shifting, or none */ 412 /* off-chip level shifting, or none */
414 mmc->slots[0].before_set_reg = hsmmc23_before_set_reg; 413 mmc->slots[0].before_set_reg = hsmmc2_before_set_reg;
415 mmc->slots[0].after_set_reg = NULL; 414 mmc->slots[0].after_set_reg = NULL;
416 } 415 }
417 break; 416 break;
417 case 3:
418 case 4: 418 case 4:
419 case 5: 419 case 5:
420 mmc->slots[0].before_set_reg = NULL; 420 mmc->slots[0].before_set_reg = NULL;
@@ -428,9 +428,10 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
428 return 0; 428 return 0;
429} 429}
430 430
431static int omap_hsmmc_done;
431#define MAX_OMAP_MMC_HWMOD_NAME_LEN 16 432#define MAX_OMAP_MMC_HWMOD_NAME_LEN 16
432 433
433void __init omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo, int ctrl_nr) 434void omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo, int ctrl_nr)
434{ 435{
435 struct omap_hwmod *oh; 436 struct omap_hwmod *oh;
436 struct platform_device *pdev; 437 struct platform_device *pdev;
@@ -487,10 +488,15 @@ done:
487 kfree(mmc_data); 488 kfree(mmc_data);
488} 489}
489 490
490void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers) 491void omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
491{ 492{
492 u32 reg; 493 u32 reg;
493 494
495 if (omap_hsmmc_done)
496 return;
497
498 omap_hsmmc_done = 1;
499
494 if (!cpu_is_omap44xx()) { 500 if (!cpu_is_omap44xx()) {
495 if (cpu_is_omap2430()) { 501 if (cpu_is_omap2430()) {
496 control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE; 502 control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 6c5826605eae..719ee423abe2 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -343,6 +343,7 @@ static void __init omap3_check_revision(const char **cpu_rev)
343 case 0xb944: 343 case 0xb944:
344 omap_revision = AM335X_REV_ES1_0; 344 omap_revision = AM335X_REV_ES1_0;
345 *cpu_rev = "1.0"; 345 *cpu_rev = "1.0";
346 break;
346 case 0xb8f2: 347 case 0xb8f2:
347 switch (rev) { 348 switch (rev) {
348 case 0: 349 case 0:
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 3f174d51f67f..e501b4972a64 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -21,7 +21,6 @@
21#include <linux/init.h> 21#include <linux/init.h>
22#include <linux/io.h> 22#include <linux/io.h>
23#include <linux/clk.h> 23#include <linux/clk.h>
24#include <linux/omapfb.h>
25 24
26#include <asm/tlb.h> 25#include <asm/tlb.h>
27 26
@@ -307,6 +306,7 @@ void __init omapam33xx_map_common_io(void)
307void __init omap44xx_map_common_io(void) 306void __init omap44xx_map_common_io(void)
308{ 307{
309 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc)); 308 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
309 omap_barriers_init();
310} 310}
311#endif 311#endif
312 312
@@ -388,7 +388,7 @@ static void __init omap_hwmod_init_postsetup(void)
388 omap_pm_if_early_init(); 388 omap_pm_if_early_init();
389} 389}
390 390
391#ifdef CONFIG_ARCH_OMAP2 391#ifdef CONFIG_SOC_OMAP2420
392void __init omap2420_init_early(void) 392void __init omap2420_init_early(void)
393{ 393{
394 omap2_set_globals_242x(); 394 omap2_set_globals_242x();
@@ -400,7 +400,9 @@ void __init omap2420_init_early(void)
400 omap_hwmod_init_postsetup(); 400 omap_hwmod_init_postsetup();
401 omap2420_clk_init(); 401 omap2420_clk_init();
402} 402}
403#endif
403 404
405#ifdef CONFIG_SOC_OMAP2430
404void __init omap2430_init_early(void) 406void __init omap2430_init_early(void)
405{ 407{
406 omap2_set_globals_243x(); 408 omap2_set_globals_243x();
diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
index 609ea2ded7e3..415a6f1cf419 100644
--- a/arch/arm/mach-omap2/mailbox.c
+++ b/arch/arm/mach-omap2/mailbox.c
@@ -281,8 +281,16 @@ static struct omap_mbox mbox_iva_info = {
281 .ops = &omap2_mbox_ops, 281 .ops = &omap2_mbox_ops,
282 .priv = &omap2_mbox_iva_priv, 282 .priv = &omap2_mbox_iva_priv,
283}; 283};
284#endif
284 285
285struct omap_mbox *omap2_mboxes[] = { &mbox_dsp_info, &mbox_iva_info, NULL }; 286#ifdef CONFIG_ARCH_OMAP2
287struct omap_mbox *omap2_mboxes[] = {
288 &mbox_dsp_info,
289#ifdef CONFIG_SOC_OMAP2420
290 &mbox_iva_info,
291#endif
292 NULL
293};
286#endif 294#endif
287 295
288#if defined(CONFIG_ARCH_OMAP4) 296#if defined(CONFIG_ARCH_OMAP4)
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index fb4bcf81a183..ecc039e794db 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -34,7 +34,7 @@
34#include "cm2xxx_3xxx.h" 34#include "cm2xxx_3xxx.h"
35#include "cm-regbits-34xx.h" 35#include "cm-regbits-34xx.h"
36 36
37/* McBSP internal signal muxing function */ 37/* McBSP1 internal signal muxing function for OMAP2/3 */
38static int omap2_mcbsp1_mux_rx_clk(struct device *dev, const char *signal, 38static int omap2_mcbsp1_mux_rx_clk(struct device *dev, const char *signal,
39 const char *src) 39 const char *src)
40{ 40{
@@ -65,6 +65,42 @@ static int omap2_mcbsp1_mux_rx_clk(struct device *dev, const char *signal,
65 return 0; 65 return 0;
66} 66}
67 67
68/* McBSP4 internal signal muxing function for OMAP4 */
69#define OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_FSX (1 << 31)
70#define OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_CLKX (1 << 30)
71static int omap4_mcbsp4_mux_rx_clk(struct device *dev, const char *signal,
72 const char *src)
73{
74 u32 v;
75
76 /*
77 * In CONTROL_MCBSPLP register only bit 30 (CLKR mux), and bit 31 (FSR
78 * mux) is used */
79 v = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP);
80
81 if (!strcmp(signal, "clkr")) {
82 if (!strcmp(src, "clkr"))
83 v &= ~OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_CLKX;
84 else if (!strcmp(src, "clkx"))
85 v |= OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_CLKX;
86 else
87 return -EINVAL;
88 } else if (!strcmp(signal, "fsr")) {
89 if (!strcmp(src, "fsr"))
90 v &= ~OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_FSX;
91 else if (!strcmp(src, "fsx"))
92 v |= OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_FSX;
93 else
94 return -EINVAL;
95 } else {
96 return -EINVAL;
97 }
98
99 omap4_ctrl_pad_writel(v, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP);
100
101 return 0;
102}
103
68/* McBSP CLKS source switching function */ 104/* McBSP CLKS source switching function */
69static int omap2_mcbsp_set_clk_src(struct device *dev, struct clk *clk, 105static int omap2_mcbsp_set_clk_src(struct device *dev, struct clk *clk,
70 const char *src) 106 const char *src)
@@ -146,9 +182,15 @@ static int omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
146 pdata->has_ccr = true; 182 pdata->has_ccr = true;
147 } 183 }
148 pdata->set_clk_src = omap2_mcbsp_set_clk_src; 184 pdata->set_clk_src = omap2_mcbsp_set_clk_src;
149 if (id == 1) 185
186 /* On OMAP2/3 the McBSP1 port has 6 pin configuration */
187 if (id == 1 && oh->class->rev < MCBSP_CONFIG_TYPE4)
150 pdata->mux_signal = omap2_mcbsp1_mux_rx_clk; 188 pdata->mux_signal = omap2_mcbsp1_mux_rx_clk;
151 189
190 /* On OMAP4 the McBSP4 port has 6 pin configuration */
191 if (id == 4 && oh->class->rev == MCBSP_CONFIG_TYPE4)
192 pdata->mux_signal = omap4_mcbsp4_mux_rx_clk;
193
152 if (oh->class->rev == MCBSP_CONFIG_TYPE3) { 194 if (oh->class->rev == MCBSP_CONFIG_TYPE3) {
153 if (id == 2) 195 if (id == 2)
154 /* The FIFO has 1024 + 256 locations */ 196 /* The FIFO has 1024 + 256 locations */
@@ -180,7 +222,6 @@ static int omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
180 name, oh->name); 222 name, oh->name);
181 return PTR_ERR(pdev); 223 return PTR_ERR(pdev);
182 } 224 }
183 omap_mcbsp_count++;
184 return 0; 225 return 0;
185} 226}
186 227
@@ -188,11 +229,6 @@ static int __init omap2_mcbsp_init(void)
188{ 229{
189 omap_hwmod_for_each_by_class("mcbsp", omap_init_mcbsp, NULL); 230 omap_hwmod_for_each_by_class("mcbsp", omap_init_mcbsp, NULL);
190 231
191 mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *), 232 return 0;
192 GFP_KERNEL);
193 if (!mcbsp_ptr)
194 return -ENOMEM;
195
196 return omap_mcbsp_init();
197} 233}
198arch_initcall(omap2_mcbsp_init); 234arch_initcall(omap2_mcbsp_init);
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index e1cc75d1a57a..611a0e3d54ca 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -100,8 +100,8 @@ void omap_mux_write_array(struct omap_mux_partition *partition,
100 100
101static char *omap_mux_options; 101static char *omap_mux_options;
102 102
103static int __init _omap_mux_init_gpio(struct omap_mux_partition *partition, 103static int _omap_mux_init_gpio(struct omap_mux_partition *partition,
104 int gpio, int val) 104 int gpio, int val)
105{ 105{
106 struct omap_mux_entry *e; 106 struct omap_mux_entry *e;
107 struct omap_mux *gpio_mux = NULL; 107 struct omap_mux *gpio_mux = NULL;
@@ -145,7 +145,7 @@ static int __init _omap_mux_init_gpio(struct omap_mux_partition *partition,
145 return 0; 145 return 0;
146} 146}
147 147
148int __init omap_mux_init_gpio(int gpio, int val) 148int omap_mux_init_gpio(int gpio, int val)
149{ 149{
150 struct omap_mux_partition *partition; 150 struct omap_mux_partition *partition;
151 int ret; 151 int ret;
@@ -159,9 +159,9 @@ int __init omap_mux_init_gpio(int gpio, int val)
159 return -ENODEV; 159 return -ENODEV;
160} 160}
161 161
162static int __init _omap_mux_get_by_name(struct omap_mux_partition *partition, 162static int _omap_mux_get_by_name(struct omap_mux_partition *partition,
163 const char *muxname, 163 const char *muxname,
164 struct omap_mux **found_mux) 164 struct omap_mux **found_mux)
165{ 165{
166 struct omap_mux *mux = NULL; 166 struct omap_mux *mux = NULL;
167 struct omap_mux_entry *e; 167 struct omap_mux_entry *e;
@@ -218,7 +218,7 @@ static int __init _omap_mux_get_by_name(struct omap_mux_partition *partition,
218 return -ENODEV; 218 return -ENODEV;
219} 219}
220 220
221static int __init 221static int
222omap_mux_get_by_name(const char *muxname, 222omap_mux_get_by_name(const char *muxname,
223 struct omap_mux_partition **found_partition, 223 struct omap_mux_partition **found_partition,
224 struct omap_mux **found_mux) 224 struct omap_mux **found_mux)
@@ -240,7 +240,7 @@ omap_mux_get_by_name(const char *muxname,
240 return -ENODEV; 240 return -ENODEV;
241} 241}
242 242
243int __init omap_mux_init_signal(const char *muxname, int val) 243int omap_mux_init_signal(const char *muxname, int val)
244{ 244{
245 struct omap_mux_partition *partition = NULL; 245 struct omap_mux_partition *partition = NULL;
246 struct omap_mux *mux = NULL; 246 struct omap_mux *mux = NULL;
@@ -1094,8 +1094,8 @@ static void omap_mux_init_package(struct omap_mux *superset,
1094 omap_mux_package_init_balls(package_balls, superset); 1094 omap_mux_package_init_balls(package_balls, superset);
1095} 1095}
1096 1096
1097static void omap_mux_init_signals(struct omap_mux_partition *partition, 1097static void __init omap_mux_init_signals(struct omap_mux_partition *partition,
1098 struct omap_board_mux *board_mux) 1098 struct omap_board_mux *board_mux)
1099{ 1099{
1100 omap_mux_set_cmdline_signals(); 1100 omap_mux_set_cmdline_signals();
1101 omap_mux_write_array(partition, board_mux); 1101 omap_mux_write_array(partition, board_mux);
@@ -1109,8 +1109,8 @@ static void omap_mux_init_package(struct omap_mux *superset,
1109{ 1109{
1110} 1110}
1111 1111
1112static void omap_mux_init_signals(struct omap_mux_partition *partition, 1112static void __init omap_mux_init_signals(struct omap_mux_partition *partition,
1113 struct omap_board_mux *board_mux) 1113 struct omap_board_mux *board_mux)
1114{ 1114{
1115} 1115}
1116 1116
diff --git a/arch/arm/mach-omap2/omap-headsmp.S b/arch/arm/mach-omap2/omap-headsmp.S
index b13ef7ef5ef4..503ac777a2ba 100644
--- a/arch/arm/mach-omap2/omap-headsmp.S
+++ b/arch/arm/mach-omap2/omap-headsmp.S
@@ -18,6 +18,7 @@
18#include <linux/linkage.h> 18#include <linux/linkage.h>
19#include <linux/init.h> 19#include <linux/init.h>
20 20
21 __CPUINIT
21/* 22/*
22 * OMAP4 specific entry point for secondary CPU to jump from ROM 23 * OMAP4 specific entry point for secondary CPU to jump from ROM
23 * code. This routine also provides a holding flag into which 24 * code. This routine also provides a holding flag into which
diff --git a/arch/arm/mach-omap2/omap-iommu.c b/arch/arm/mach-omap2/omap-iommu.c
index b8822048e409..ac49384d0285 100644
--- a/arch/arm/mach-omap2/omap-iommu.c
+++ b/arch/arm/mach-omap2/omap-iommu.c
@@ -150,7 +150,8 @@ err_out:
150 platform_device_put(omap_iommu_pdev[i]); 150 platform_device_put(omap_iommu_pdev[i]);
151 return err; 151 return err;
152} 152}
153module_init(omap_iommu_init); 153/* must be ready before omap3isp is probed */
154subsys_initcall(omap_iommu_init);
154 155
155static void __exit omap_iommu_exit(void) 156static void __exit omap_iommu_exit(void)
156{ 157{
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index 40a8fbc07e4b..70de277f5c15 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -24,12 +24,14 @@
24 24
25#include <plat/irqs.h> 25#include <plat/irqs.h>
26#include <plat/sram.h> 26#include <plat/sram.h>
27#include <plat/omap-secure.h>
27 28
28#include <mach/hardware.h> 29#include <mach/hardware.h>
29#include <mach/omap-wakeupgen.h> 30#include <mach/omap-wakeupgen.h>
30 31
31#include "common.h" 32#include "common.h"
32#include "omap4-sar-layout.h" 33#include "omap4-sar-layout.h"
34#include <linux/export.h>
33 35
34#ifdef CONFIG_CACHE_L2X0 36#ifdef CONFIG_CACHE_L2X0
35static void __iomem *l2cache_base; 37static void __iomem *l2cache_base;
@@ -43,6 +45,9 @@ static void __iomem *sar_ram_base;
43 45
44void __iomem *dram_sync, *sram_sync; 46void __iomem *dram_sync, *sram_sync;
45 47
48static phys_addr_t paddr;
49static u32 size;
50
46void omap_bus_sync(void) 51void omap_bus_sync(void)
47{ 52{
48 if (dram_sync && sram_sync) { 53 if (dram_sync && sram_sync) {
@@ -51,19 +56,22 @@ void omap_bus_sync(void)
51 isb(); 56 isb();
52 } 57 }
53} 58}
59EXPORT_SYMBOL(omap_bus_sync);
54 60
55static int __init omap_barriers_init(void) 61/* Steal one page physical memory for barrier implementation */
62int __init omap_barrier_reserve_memblock(void)
56{ 63{
57 struct map_desc dram_io_desc[1];
58 phys_addr_t paddr;
59 u32 size;
60
61 if (!cpu_is_omap44xx())
62 return -ENODEV;
63 64
64 size = ALIGN(PAGE_SIZE, SZ_1M); 65 size = ALIGN(PAGE_SIZE, SZ_1M);
65 paddr = arm_memblock_steal(size, SZ_1M); 66 paddr = arm_memblock_steal(size, SZ_1M);
66 67
68 return 0;
69}
70
71void __init omap_barriers_init(void)
72{
73 struct map_desc dram_io_desc[1];
74
67 dram_io_desc[0].virtual = OMAP4_DRAM_BARRIER_VA; 75 dram_io_desc[0].virtual = OMAP4_DRAM_BARRIER_VA;
68 dram_io_desc[0].pfn = __phys_to_pfn(paddr); 76 dram_io_desc[0].pfn = __phys_to_pfn(paddr);
69 dram_io_desc[0].length = size; 77 dram_io_desc[0].length = size;
@@ -75,9 +83,10 @@ static int __init omap_barriers_init(void)
75 pr_info("OMAP4: Map 0x%08llx to 0x%08lx for dram barrier\n", 83 pr_info("OMAP4: Map 0x%08llx to 0x%08lx for dram barrier\n",
76 (long long) paddr, dram_io_desc[0].virtual); 84 (long long) paddr, dram_io_desc[0].virtual);
77 85
78 return 0;
79} 86}
80core_initcall(omap_barriers_init); 87#else
88void __init omap_barriers_init(void)
89{}
81#endif 90#endif
82 91
83void __init gic_init_irq(void) 92void __init gic_init_irq(void)
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 5192cabb40ed..eba6cd3816f5 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -1517,8 +1517,8 @@ static int _enable(struct omap_hwmod *oh)
1517 if (oh->_state != _HWMOD_STATE_INITIALIZED && 1517 if (oh->_state != _HWMOD_STATE_INITIALIZED &&
1518 oh->_state != _HWMOD_STATE_IDLE && 1518 oh->_state != _HWMOD_STATE_IDLE &&
1519 oh->_state != _HWMOD_STATE_DISABLED) { 1519 oh->_state != _HWMOD_STATE_DISABLED) {
1520 WARN(1, "omap_hwmod: %s: enabled state can only be entered " 1520 WARN(1, "omap_hwmod: %s: enabled state can only be entered from initialized, idle, or disabled state\n",
1521 "from initialized, idle, or disabled state\n", oh->name); 1521 oh->name);
1522 return -EINVAL; 1522 return -EINVAL;
1523 } 1523 }
1524 1524
@@ -1600,8 +1600,8 @@ static int _idle(struct omap_hwmod *oh)
1600 pr_debug("omap_hwmod: %s: idling\n", oh->name); 1600 pr_debug("omap_hwmod: %s: idling\n", oh->name);
1601 1601
1602 if (oh->_state != _HWMOD_STATE_ENABLED) { 1602 if (oh->_state != _HWMOD_STATE_ENABLED) {
1603 WARN(1, "omap_hwmod: %s: idle state can only be entered from " 1603 WARN(1, "omap_hwmod: %s: idle state can only be entered from enabled state\n",
1604 "enabled state\n", oh->name); 1604 oh->name);
1605 return -EINVAL; 1605 return -EINVAL;
1606 } 1606 }
1607 1607
@@ -1682,8 +1682,8 @@ static int _shutdown(struct omap_hwmod *oh)
1682 1682
1683 if (oh->_state != _HWMOD_STATE_IDLE && 1683 if (oh->_state != _HWMOD_STATE_IDLE &&
1684 oh->_state != _HWMOD_STATE_ENABLED) { 1684 oh->_state != _HWMOD_STATE_ENABLED) {
1685 WARN(1, "omap_hwmod: %s: disabled state can only be entered " 1685 WARN(1, "omap_hwmod: %s: disabled state can only be entered from idle, or enabled state\n",
1686 "from idle, or enabled state\n", oh->name); 1686 oh->name);
1687 return -EINVAL; 1687 return -EINVAL;
1688 } 1688 }
1689 1689
@@ -2240,8 +2240,8 @@ void omap_hwmod_ocp_barrier(struct omap_hwmod *oh)
2240 BUG_ON(!oh); 2240 BUG_ON(!oh);
2241 2241
2242 if (!oh->class->sysc || !oh->class->sysc->sysc_flags) { 2242 if (!oh->class->sysc || !oh->class->sysc->sysc_flags) {
2243 WARN(1, "omap_device: %s: OCP barrier impossible due to " 2243 WARN(1, "omap_device: %s: OCP barrier impossible due to device configuration\n",
2244 "device configuration\n", oh->name); 2244 oh->name);
2245 return; 2245 return;
2246 } 2246 }
2247 2247
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
index c11273da5dcc..f08e442af397 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
@@ -56,27 +56,6 @@ struct omap_hwmod_class omap2_dss_hwmod_class = {
56}; 56};
57 57
58/* 58/*
59 * 'dispc' class
60 * display controller
61 */
62
63static struct omap_hwmod_class_sysconfig omap2_dispc_sysc = {
64 .rev_offs = 0x0000,
65 .sysc_offs = 0x0010,
66 .syss_offs = 0x0014,
67 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
68 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
69 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
70 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
71 .sysc_fields = &omap_hwmod_sysc_type1,
72};
73
74struct omap_hwmod_class omap2_dispc_hwmod_class = {
75 .name = "dispc",
76 .sysc = &omap2_dispc_sysc,
77};
78
79/*
80 * 'rfbi' class 59 * 'rfbi' class
81 * remote frame buffer interface 60 * remote frame buffer interface
82 */ 61 */
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
index 177dee20faef..2a6729741b06 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
@@ -28,6 +28,28 @@ struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[] = {
28 { .name = "dispc", .dma_req = 5 }, 28 { .name = "dispc", .dma_req = 5 },
29 { .dma_req = -1 } 29 { .dma_req = -1 }
30}; 30};
31
32/*
33 * 'dispc' class
34 * display controller
35 */
36
37static struct omap_hwmod_class_sysconfig omap2_dispc_sysc = {
38 .rev_offs = 0x0000,
39 .sysc_offs = 0x0010,
40 .syss_offs = 0x0014,
41 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
42 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
43 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
44 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
45 .sysc_fields = &omap_hwmod_sysc_type1,
46};
47
48struct omap_hwmod_class omap2_dispc_hwmod_class = {
49 .name = "dispc",
50 .sysc = &omap2_dispc_sysc,
51};
52
31/* OMAP2xxx Timer Common */ 53/* OMAP2xxx Timer Common */
32static struct omap_hwmod_class_sysconfig omap2xxx_timer_sysc = { 54static struct omap_hwmod_class_sysconfig omap2xxx_timer_sysc = {
33 .rev_offs = 0x0000, 55 .rev_offs = 0x0000,
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 5324e8d93bc0..3c8dd928628e 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -1480,6 +1480,28 @@ static struct omap_hwmod omap3xxx_dss_core_hwmod = {
1480 .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters), 1480 .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters),
1481}; 1481};
1482 1482
1483/*
1484 * 'dispc' class
1485 * display controller
1486 */
1487
1488static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = {
1489 .rev_offs = 0x0000,
1490 .sysc_offs = 0x0010,
1491 .syss_offs = 0x0014,
1492 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
1493 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1494 SYSC_HAS_ENAWAKEUP),
1495 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1496 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1497 .sysc_fields = &omap_hwmod_sysc_type1,
1498};
1499
1500static struct omap_hwmod_class omap3_dispc_hwmod_class = {
1501 .name = "dispc",
1502 .sysc = &omap3_dispc_sysc,
1503};
1504
1483/* l4_core -> dss_dispc */ 1505/* l4_core -> dss_dispc */
1484static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = { 1506static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
1485 .master = &omap3xxx_l4_core_hwmod, 1507 .master = &omap3xxx_l4_core_hwmod,
@@ -1503,7 +1525,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = {
1503 1525
1504static struct omap_hwmod omap3xxx_dss_dispc_hwmod = { 1526static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
1505 .name = "dss_dispc", 1527 .name = "dss_dispc",
1506 .class = &omap2_dispc_hwmod_class, 1528 .class = &omap3_dispc_hwmod_class,
1507 .mpu_irqs = omap2_dispc_irqs, 1529 .mpu_irqs = omap2_dispc_irqs,
1508 .main_clk = "dss1_alwon_fck", 1530 .main_clk = "dss1_alwon_fck",
1509 .prcm = { 1531 .prcm = {
@@ -3523,12 +3545,6 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
3523 &omap3xxx_uart2_hwmod, 3545 &omap3xxx_uart2_hwmod,
3524 &omap3xxx_uart3_hwmod, 3546 &omap3xxx_uart3_hwmod,
3525 3547
3526 /* dss class */
3527 &omap3xxx_dss_dispc_hwmod,
3528 &omap3xxx_dss_dsi1_hwmod,
3529 &omap3xxx_dss_rfbi_hwmod,
3530 &omap3xxx_dss_venc_hwmod,
3531
3532 /* i2c class */ 3548 /* i2c class */
3533 &omap3xxx_i2c1_hwmod, 3549 &omap3xxx_i2c1_hwmod,
3534 &omap3xxx_i2c2_hwmod, 3550 &omap3xxx_i2c2_hwmod,
@@ -3635,6 +3651,15 @@ static __initdata struct omap_hwmod *am35xx_hwmods[] = {
3635 NULL 3651 NULL
3636}; 3652};
3637 3653
3654static __initdata struct omap_hwmod *omap3xxx_dss_hwmods[] = {
3655 /* dss class */
3656 &omap3xxx_dss_dispc_hwmod,
3657 &omap3xxx_dss_dsi1_hwmod,
3658 &omap3xxx_dss_rfbi_hwmod,
3659 &omap3xxx_dss_venc_hwmod,
3660 NULL
3661};
3662
3638int __init omap3xxx_hwmod_init(void) 3663int __init omap3xxx_hwmod_init(void)
3639{ 3664{
3640 int r; 3665 int r;
@@ -3708,6 +3733,21 @@ int __init omap3xxx_hwmod_init(void)
3708 3733
3709 if (h) 3734 if (h)
3710 r = omap_hwmod_register(h); 3735 r = omap_hwmod_register(h);
3736 if (r < 0)
3737 return r;
3738
3739 /*
3740 * DSS code presumes that dss_core hwmod is handled first,
3741 * _before_ any other DSS related hwmods so register common
3742 * DSS hwmods last to ensure that dss_core is already registered.
3743 * Otherwise some change things may happen, for ex. if dispc
3744 * is handled before dss_core and DSS is enabled in bootloader
3745 * DIPSC will be reset with outputs enabled which sometimes leads
3746 * to unrecoverable L3 error.
3747 * XXX The long-term fix to this is to ensure modules are set up
3748 * in dependency order in the hwmod core code.
3749 */
3750 r = omap_hwmod_register(omap3xxx_dss_hwmods);
3711 3751
3712 return r; 3752 return r;
3713} 3753}
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index f9f151081760..ef0524c10a84 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -1031,6 +1031,7 @@ static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
1031 1031
1032static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = { 1032static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
1033 { 1033 {
1034 .name = "mpu",
1034 .pa_start = 0x4012e000, 1035 .pa_start = 0x4012e000,
1035 .pa_end = 0x4012e07f, 1036 .pa_end = 0x4012e07f,
1036 .flags = ADDR_TYPE_RT 1037 .flags = ADDR_TYPE_RT
@@ -1049,6 +1050,7 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
1049 1050
1050static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = { 1051static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
1051 { 1052 {
1053 .name = "dma",
1052 .pa_start = 0x4902e000, 1054 .pa_start = 0x4902e000,
1053 .pa_end = 0x4902e07f, 1055 .pa_end = 0x4902e07f,
1054 .flags = ADDR_TYPE_RT 1056 .flags = ADDR_TYPE_RT
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 1881fe915149..5a65dd04aa38 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -174,14 +174,17 @@ static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name,
174 freq = clk->rate; 174 freq = clk->rate;
175 clk_put(clk); 175 clk_put(clk);
176 176
177 rcu_read_lock();
177 opp = opp_find_freq_ceil(dev, &freq); 178 opp = opp_find_freq_ceil(dev, &freq);
178 if (IS_ERR(opp)) { 179 if (IS_ERR(opp)) {
180 rcu_read_unlock();
179 pr_err("%s: unable to find boot up OPP for vdd_%s\n", 181 pr_err("%s: unable to find boot up OPP for vdd_%s\n",
180 __func__, vdd_name); 182 __func__, vdd_name);
181 goto exit; 183 goto exit;
182 } 184 }
183 185
184 bootup_volt = opp_get_voltage(opp); 186 bootup_volt = opp_get_voltage(opp);
187 rcu_read_unlock();
185 if (!bootup_volt) { 188 if (!bootup_volt) {
186 pr_err("%s: unable to find voltage corresponding " 189 pr_err("%s: unable to find voltage corresponding "
187 "to the bootup OPP for vdd_%s\n", __func__, vdd_name); 190 "to the bootup OPP for vdd_%s\n", __func__, vdd_name);
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index b8822f8b2891..23de98d03841 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -82,13 +82,7 @@ static int omap2_fclks_active(void)
82 f1 = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); 82 f1 = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
83 f2 = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2); 83 f2 = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
84 84
85 /* Ignore UART clocks. These are handled by UART core (serial.c) */ 85 return (f1 | f2) ? 1 : 0;
86 f1 &= ~(OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_UART2_MASK);
87 f2 &= ~OMAP24XX_EN_UART3_MASK;
88
89 if (f1 | f2)
90 return 1;
91 return 0;
92} 86}
93 87
94static void omap2_enter_full_retention(void) 88static void omap2_enter_full_retention(void)
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c
index c1c4d86a79a8..9ce765407ad5 100644
--- a/arch/arm/mach-omap2/prm2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c
@@ -19,6 +19,7 @@
19#include "common.h" 19#include "common.h"
20#include <plat/cpu.h> 20#include <plat/cpu.h>
21#include <plat/prcm.h> 21#include <plat/prcm.h>
22#include <plat/irqs.h>
22 23
23#include "vp.h" 24#include "vp.h"
24 25
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index 33dd655e6aab..a1d6154dc120 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -19,6 +19,7 @@
19 19
20#include "common.h" 20#include "common.h"
21#include <plat/cpu.h> 21#include <plat/cpu.h>
22#include <plat/irqs.h>
22#include <plat/prcm.h> 23#include <plat/prcm.h>
23 24
24#include "vp.h" 25#include "vp.h"
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index 247d89478f24..f590afc1f673 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -107,18 +107,18 @@ static void omap_uart_set_noidle(struct platform_device *pdev)
107 omap_hwmod_set_slave_idlemode(od->hwmods[0], HWMOD_IDLEMODE_NO); 107 omap_hwmod_set_slave_idlemode(od->hwmods[0], HWMOD_IDLEMODE_NO);
108} 108}
109 109
110static void omap_uart_set_forceidle(struct platform_device *pdev) 110static void omap_uart_set_smartidle(struct platform_device *pdev)
111{ 111{
112 struct omap_device *od = to_omap_device(pdev); 112 struct omap_device *od = to_omap_device(pdev);
113 113
114 omap_hwmod_set_slave_idlemode(od->hwmods[0], HWMOD_IDLEMODE_FORCE); 114 omap_hwmod_set_slave_idlemode(od->hwmods[0], HWMOD_IDLEMODE_SMART);
115} 115}
116 116
117#else 117#else
118static void omap_uart_enable_wakeup(struct platform_device *pdev, bool enable) 118static void omap_uart_enable_wakeup(struct platform_device *pdev, bool enable)
119{} 119{}
120static void omap_uart_set_noidle(struct platform_device *pdev) {} 120static void omap_uart_set_noidle(struct platform_device *pdev) {}
121static void omap_uart_set_forceidle(struct platform_device *pdev) {} 121static void omap_uart_set_smartidle(struct platform_device *pdev) {}
122#endif /* CONFIG_PM */ 122#endif /* CONFIG_PM */
123 123
124#ifdef CONFIG_OMAP_MUX 124#ifdef CONFIG_OMAP_MUX
@@ -349,7 +349,7 @@ void __init omap_serial_init_port(struct omap_board_data *bdata,
349 omap_up.uartclk = OMAP24XX_BASE_BAUD * 16; 349 omap_up.uartclk = OMAP24XX_BASE_BAUD * 16;
350 omap_up.flags = UPF_BOOT_AUTOCONF; 350 omap_up.flags = UPF_BOOT_AUTOCONF;
351 omap_up.get_context_loss_count = omap_pm_get_dev_context_loss_count; 351 omap_up.get_context_loss_count = omap_pm_get_dev_context_loss_count;
352 omap_up.set_forceidle = omap_uart_set_forceidle; 352 omap_up.set_forceidle = omap_uart_set_smartidle;
353 omap_up.set_noidle = omap_uart_set_noidle; 353 omap_up.set_noidle = omap_uart_set_noidle;
354 omap_up.enable_wakeup = omap_uart_enable_wakeup; 354 omap_up.enable_wakeup = omap_uart_enable_wakeup;
355 omap_up.dma_rx_buf_size = info->dma_rx_buf_size; 355 omap_up.dma_rx_buf_size = info->dma_rx_buf_size;
diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
index 9dd93453e563..7e755bb0ffc4 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -897,7 +897,7 @@ static int __init omap_sr_probe(struct platform_device *pdev)
897 ret = sr_late_init(sr_info); 897 ret = sr_late_init(sr_info);
898 if (ret) { 898 if (ret) {
899 pr_warning("%s: Error in SR late init\n", __func__); 899 pr_warning("%s: Error in SR late init\n", __func__);
900 return ret; 900 goto err_iounmap;
901 } 901 }
902 } 902 }
903 903
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 6eeff0e0ae01..5c9acea95761 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -270,7 +270,7 @@ static struct clocksource clocksource_gpt = {
270static u32 notrace dmtimer_read_sched_clock(void) 270static u32 notrace dmtimer_read_sched_clock(void)
271{ 271{
272 if (clksrc.reserved) 272 if (clksrc.reserved)
273 return __omap_dm_timer_read_counter(clksrc.io_base, 1); 273 return __omap_dm_timer_read_counter(&clksrc, 1);
274 274
275 return 0; 275 return 0;
276} 276}
diff --git a/arch/arm/mach-omap2/twl-common.c b/arch/arm/mach-omap2/twl-common.c
index 10b20c652e5d..4b57757bf9d1 100644
--- a/arch/arm/mach-omap2/twl-common.c
+++ b/arch/arm/mach-omap2/twl-common.c
@@ -270,7 +270,6 @@ static struct regulator_init_data omap4_vusb_idata = {
270 .constraints = { 270 .constraints = {
271 .min_uV = 3300000, 271 .min_uV = 3300000,
272 .max_uV = 3300000, 272 .max_uV = 3300000,
273 .apply_uV = true,
274 .valid_modes_mask = REGULATOR_MODE_NORMAL 273 .valid_modes_mask = REGULATOR_MODE_NORMAL
275 | REGULATOR_MODE_STANDBY, 274 | REGULATOR_MODE_STANDBY,
276 .valid_ops_mask = REGULATOR_CHANGE_MODE 275 .valid_ops_mask = REGULATOR_CHANGE_MODE
diff --git a/arch/arm/mach-omap2/usb-host.c b/arch/arm/mach-omap2/usb-host.c
index 771dc781b746..f51348dafafd 100644
--- a/arch/arm/mach-omap2/usb-host.c
+++ b/arch/arm/mach-omap2/usb-host.c
@@ -486,7 +486,7 @@ static void setup_4430ohci_io_mux(const enum usbhs_omap_port_mode *port_mode)
486void __init usbhs_init(const struct usbhs_omap_board_data *pdata) 486void __init usbhs_init(const struct usbhs_omap_board_data *pdata)
487{ 487{
488 struct omap_hwmod *oh[2]; 488 struct omap_hwmod *oh[2];
489 struct omap_device *od; 489 struct platform_device *pdev;
490 int bus_id = -1; 490 int bus_id = -1;
491 int i; 491 int i;
492 492
@@ -522,11 +522,11 @@ void __init usbhs_init(const struct usbhs_omap_board_data *pdata)
522 return; 522 return;
523 } 523 }
524 524
525 od = omap_device_build_ss(OMAP_USBHS_DEVICE, bus_id, oh, 2, 525 pdev = omap_device_build_ss(OMAP_USBHS_DEVICE, bus_id, oh, 2,
526 (void *)&usbhs_data, sizeof(usbhs_data), 526 (void *)&usbhs_data, sizeof(usbhs_data),
527 omap_uhhtll_latency, 527 omap_uhhtll_latency,
528 ARRAY_SIZE(omap_uhhtll_latency), false); 528 ARRAY_SIZE(omap_uhhtll_latency), false);
529 if (IS_ERR(od)) { 529 if (IS_ERR(pdev)) {
530 pr_err("Could not build hwmod devices %s,%s\n", 530 pr_err("Could not build hwmod devices %s,%s\n",
531 USBHS_UHH_HWMODNAME, USBHS_TLL_HWMODNAME); 531 USBHS_UHH_HWMODNAME, USBHS_TLL_HWMODNAME);
532 return; 532 return;
diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c
index 031d116fbf10..175b7d86d86a 100644
--- a/arch/arm/mach-omap2/vc.c
+++ b/arch/arm/mach-omap2/vc.c
@@ -247,7 +247,7 @@ static void __init omap4_vc_init_channel(struct voltagedomain *voltdm)
247 * omap_vc_i2c_init - initialize I2C interface to PMIC 247 * omap_vc_i2c_init - initialize I2C interface to PMIC
248 * @voltdm: voltage domain containing VC data 248 * @voltdm: voltage domain containing VC data
249 * 249 *
250 * Use PMIC supplied seetings for I2C high-speed mode and 250 * Use PMIC supplied settings for I2C high-speed mode and
251 * master code (if set) and program the VC I2C configuration 251 * master code (if set) and program the VC I2C configuration
252 * register. 252 * register.
253 * 253 *
@@ -265,8 +265,8 @@ static void __init omap_vc_i2c_init(struct voltagedomain *voltdm)
265 265
266 if (initialized) { 266 if (initialized) {
267 if (voltdm->pmic->i2c_high_speed != i2c_high_speed) 267 if (voltdm->pmic->i2c_high_speed != i2c_high_speed)
268 pr_warn("%s: I2C config for all channels must match.", 268 pr_warn("%s: I2C config for vdd_%s does not match other channels (%u).",
269 __func__); 269 __func__, voltdm->name, i2c_high_speed);
270 return; 270 return;
271 } 271 }
272 272
@@ -292,9 +292,7 @@ void __init omap_vc_init_channel(struct voltagedomain *voltdm)
292 u32 val; 292 u32 val;
293 293
294 if (!voltdm->pmic || !voltdm->pmic->uv_to_vsel) { 294 if (!voltdm->pmic || !voltdm->pmic->uv_to_vsel) {
295 pr_err("%s: PMIC info requried to configure vc for" 295 pr_err("%s: No PMIC info for vdd_%s\n", __func__, voltdm->name);
296 "vdd_%s not populated.Hence cannot initialize vc\n",
297 __func__, voltdm->name);
298 return; 296 return;
299 } 297 }
300 298
diff --git a/arch/arm/mach-omap2/voltagedomains3xxx_data.c b/arch/arm/mach-omap2/voltagedomains3xxx_data.c
index c005e2f5e383..57db2038b23c 100644
--- a/arch/arm/mach-omap2/voltagedomains3xxx_data.c
+++ b/arch/arm/mach-omap2/voltagedomains3xxx_data.c
@@ -108,6 +108,7 @@ void __init omap3xxx_voltagedomains_init(void)
108 * XXX Will depend on the process, validation, and binning 108 * XXX Will depend on the process, validation, and binning
109 * for the currently-running IC 109 * for the currently-running IC
110 */ 110 */
111#ifdef CONFIG_PM_OPP
111 if (cpu_is_omap3630()) { 112 if (cpu_is_omap3630()) {
112 omap3_voltdm_mpu.volt_data = omap36xx_vddmpu_volt_data; 113 omap3_voltdm_mpu.volt_data = omap36xx_vddmpu_volt_data;
113 omap3_voltdm_core.volt_data = omap36xx_vddcore_volt_data; 114 omap3_voltdm_core.volt_data = omap36xx_vddcore_volt_data;
@@ -115,6 +116,7 @@ void __init omap3xxx_voltagedomains_init(void)
115 omap3_voltdm_mpu.volt_data = omap34xx_vddmpu_volt_data; 116 omap3_voltdm_mpu.volt_data = omap34xx_vddmpu_volt_data;
116 omap3_voltdm_core.volt_data = omap34xx_vddcore_volt_data; 117 omap3_voltdm_core.volt_data = omap34xx_vddcore_volt_data;
117 } 118 }
119#endif
118 120
119 if (cpu_is_omap3517() || cpu_is_omap3505()) 121 if (cpu_is_omap3517() || cpu_is_omap3505())
120 voltdms = voltagedomains_am35xx; 122 voltdms = voltagedomains_am35xx;
diff --git a/arch/arm/mach-omap2/voltagedomains44xx_data.c b/arch/arm/mach-omap2/voltagedomains44xx_data.c
index 4e11d022595d..c3115f6853d4 100644
--- a/arch/arm/mach-omap2/voltagedomains44xx_data.c
+++ b/arch/arm/mach-omap2/voltagedomains44xx_data.c
@@ -100,9 +100,11 @@ void __init omap44xx_voltagedomains_init(void)
100 * XXX Will depend on the process, validation, and binning 100 * XXX Will depend on the process, validation, and binning
101 * for the currently-running IC 101 * for the currently-running IC
102 */ 102 */
103#ifdef CONFIG_PM_OPP
103 omap4_voltdm_mpu.volt_data = omap44xx_vdd_mpu_volt_data; 104 omap4_voltdm_mpu.volt_data = omap44xx_vdd_mpu_volt_data;
104 omap4_voltdm_iva.volt_data = omap44xx_vdd_iva_volt_data; 105 omap4_voltdm_iva.volt_data = omap44xx_vdd_iva_volt_data;
105 omap4_voltdm_core.volt_data = omap44xx_vdd_core_volt_data; 106 omap4_voltdm_core.volt_data = omap44xx_vdd_core_volt_data;
107#endif
106 108
107 for (i = 0; voltdm = voltagedomains_omap4[i], voltdm; i++) 109 for (i = 0; voltdm = voltagedomains_omap4[i], voltdm; i++)
108 voltdm->sys_clk.name = sys_clk_name; 110 voltdm->sys_clk.name = sys_clk_name;
diff --git a/arch/arm/mach-omap2/vp.c b/arch/arm/mach-omap2/vp.c
index 807391d84a9d..0df88820978d 100644
--- a/arch/arm/mach-omap2/vp.c
+++ b/arch/arm/mach-omap2/vp.c
@@ -41,6 +41,11 @@ void __init omap_vp_init(struct voltagedomain *voltdm)
41 u32 val, sys_clk_rate, timeout, waittime; 41 u32 val, sys_clk_rate, timeout, waittime;
42 u32 vddmin, vddmax, vstepmin, vstepmax; 42 u32 vddmin, vddmax, vstepmin, vstepmax;
43 43
44 if (!voltdm->pmic || !voltdm->pmic->uv_to_vsel) {
45 pr_err("%s: No PMIC info for vdd_%s\n", __func__, voltdm->name);
46 return;
47 }
48
44 if (!voltdm->read || !voltdm->write) { 49 if (!voltdm->read || !voltdm->write) {
45 pr_err("%s: No read/write API for accessing vdd_%s regs\n", 50 pr_err("%s: No read/write API for accessing vdd_%s regs\n",
46 __func__, voltdm->name); 51 __func__, voltdm->name);
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index 0e28bae20bd4..5dad38ec00ea 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -29,6 +29,7 @@
29#include <mach/hardware.h> 29#include <mach/hardware.h>
30#include <mach/orion5x.h> 30#include <mach/orion5x.h>
31#include <plat/orion_nand.h> 31#include <plat/orion_nand.h>
32#include <plat/ehci-orion.h>
32#include <plat/time.h> 33#include <plat/time.h>
33#include <plat/common.h> 34#include <plat/common.h>
34#include <plat/addr-map.h> 35#include <plat/addr-map.h>
@@ -72,7 +73,8 @@ void __init orion5x_map_io(void)
72 ****************************************************************************/ 73 ****************************************************************************/
73void __init orion5x_ehci0_init(void) 74void __init orion5x_ehci0_init(void)
74{ 75{
75 orion_ehci_init(ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL); 76 orion_ehci_init(ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL,
77 EHCI_PHY_ORION);
76} 78}
77 79
78 80
diff --git a/arch/arm/mach-orion5x/db88f5281-setup.c b/arch/arm/mach-orion5x/db88f5281-setup.c
index a104d5a80e11..e52108c9aaea 100644
--- a/arch/arm/mach-orion5x/db88f5281-setup.c
+++ b/arch/arm/mach-orion5x/db88f5281-setup.c
@@ -214,7 +214,7 @@ void __init db88f5281_pci_preinit(void)
214 if (gpio_direction_input(pin) == 0) { 214 if (gpio_direction_input(pin) == 0) {
215 irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); 215 irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
216 } else { 216 } else {
217 printk(KERN_ERR "db88f5281_pci_preinit faield to " 217 printk(KERN_ERR "db88f5281_pci_preinit failed to "
218 "set_irq_type pin %d\n", pin); 218 "set_irq_type pin %d\n", pin);
219 gpio_free(pin); 219 gpio_free(pin);
220 } 220 }
@@ -227,7 +227,7 @@ void __init db88f5281_pci_preinit(void)
227 if (gpio_direction_input(pin) == 0) { 227 if (gpio_direction_input(pin) == 0) {
228 irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); 228 irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
229 } else { 229 } else {
230 printk(KERN_ERR "db88f5281_pci_preinit faield " 230 printk(KERN_ERR "db88f5281_pci_preinit failed "
231 "to set_irq_type pin %d\n", pin); 231 "to set_irq_type pin %d\n", pin);
232 gpio_free(pin); 232 gpio_free(pin);
233 } 233 }
diff --git a/arch/arm/mach-orion5x/rd88f5182-setup.c b/arch/arm/mach-orion5x/rd88f5182-setup.c
index 96438b6b2022..e3ce61711478 100644
--- a/arch/arm/mach-orion5x/rd88f5182-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5182-setup.c
@@ -149,7 +149,7 @@ void __init rd88f5182_pci_preinit(void)
149 if (gpio_direction_input(pin) == 0) { 149 if (gpio_direction_input(pin) == 0) {
150 irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); 150 irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
151 } else { 151 } else {
152 printk(KERN_ERR "rd88f5182_pci_preinit faield to " 152 printk(KERN_ERR "rd88f5182_pci_preinit failed to "
153 "set_irq_type pin %d\n", pin); 153 "set_irq_type pin %d\n", pin);
154 gpio_free(pin); 154 gpio_free(pin);
155 } 155 }
@@ -162,7 +162,7 @@ void __init rd88f5182_pci_preinit(void)
162 if (gpio_direction_input(pin) == 0) { 162 if (gpio_direction_input(pin) == 0) {
163 irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); 163 irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
164 } else { 164 } else {
165 printk(KERN_ERR "rd88f5182_pci_preinit faield to " 165 printk(KERN_ERR "rd88f5182_pci_preinit failed to "
166 "set_irq_type pin %d\n", pin); 166 "set_irq_type pin %d\n", pin);
167 gpio_free(pin); 167 gpio_free(pin);
168 } 168 }
diff --git a/arch/arm/mach-prima2/irq.c b/arch/arm/mach-prima2/irq.c
index d93ceef4a50a..37c2de9b6f26 100644
--- a/arch/arm/mach-prima2/irq.c
+++ b/arch/arm/mach-prima2/irq.c
@@ -68,7 +68,7 @@ void __init sirfsoc_of_irq_init(void)
68 if (!sirfsoc_intc_base) 68 if (!sirfsoc_intc_base)
69 panic("unable to map intc cpu registers\n"); 69 panic("unable to map intc cpu registers\n");
70 70
71 irq_domain_add_simple(np, 0); 71 irq_domain_add_legacy(np, 32, 0, 0, &irq_domain_simple_ops, NULL);
72 72
73 of_node_put(np); 73 of_node_put(np);
74 74
diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c
index 18fd177073f4..5bc13121eac5 100644
--- a/arch/arm/mach-pxa/devices.c
+++ b/arch/arm/mach-pxa/devices.c
@@ -415,29 +415,9 @@ static struct resource pxa_rtc_resources[] = {
415 }, 415 },
416}; 416};
417 417
418static struct resource sa1100_rtc_resources[] = {
419 [0] = {
420 .start = 0x40900000,
421 .end = 0x409000ff,
422 .flags = IORESOURCE_MEM,
423 },
424 [1] = {
425 .start = IRQ_RTC1Hz,
426 .end = IRQ_RTC1Hz,
427 .flags = IORESOURCE_IRQ,
428 },
429 [2] = {
430 .start = IRQ_RTCAlrm,
431 .end = IRQ_RTCAlrm,
432 .flags = IORESOURCE_IRQ,
433 },
434};
435
436struct platform_device sa1100_device_rtc = { 418struct platform_device sa1100_device_rtc = {
437 .name = "sa1100-rtc", 419 .name = "sa1100-rtc",
438 .id = -1, 420 .id = -1,
439 .num_resources = ARRAY_SIZE(sa1100_rtc_resources),
440 .resource = sa1100_rtc_resources,
441}; 421};
442 422
443struct platform_device pxa_device_rtc = { 423struct platform_device pxa_device_rtc = {
diff --git a/arch/arm/mach-pxa/generic.h b/arch/arm/mach-pxa/generic.h
index 0d729e6619df..42d5cca66257 100644
--- a/arch/arm/mach-pxa/generic.h
+++ b/arch/arm/mach-pxa/generic.h
@@ -49,7 +49,6 @@ extern unsigned pxa3xx_get_clk_frequency_khz(int);
49#endif 49#endif
50 50
51extern struct syscore_ops pxa_irq_syscore_ops; 51extern struct syscore_ops pxa_irq_syscore_ops;
52extern struct syscore_ops pxa_gpio_syscore_ops;
53extern struct syscore_ops pxa2xx_mfp_syscore_ops; 52extern struct syscore_ops pxa2xx_mfp_syscore_ops;
54extern struct syscore_ops pxa3xx_mfp_syscore_ops; 53extern struct syscore_ops pxa3xx_mfp_syscore_ops;
55 54
diff --git a/arch/arm/mach-pxa/hx4700.c b/arch/arm/mach-pxa/hx4700.c
index fb9b62dcf4ca..208eef1c0485 100644
--- a/arch/arm/mach-pxa/hx4700.c
+++ b/arch/arm/mach-pxa/hx4700.c
@@ -45,6 +45,7 @@
45#include <mach/hx4700.h> 45#include <mach/hx4700.h>
46#include <mach/irda.h> 46#include <mach/irda.h>
47 47
48#include <sound/ak4641.h>
48#include <video/platform_lcd.h> 49#include <video/platform_lcd.h>
49#include <video/w100fb.h> 50#include <video/w100fb.h>
50 51
@@ -765,6 +766,28 @@ static struct i2c_board_info __initdata pi2c_board_info[] = {
765}; 766};
766 767
767/* 768/*
769 * Asahi Kasei AK4641 on I2C
770 */
771
772static struct ak4641_platform_data ak4641_info = {
773 .gpio_power = GPIO27_HX4700_CODEC_ON,
774 .gpio_npdn = GPIO109_HX4700_CODEC_nPDN,
775};
776
777static struct i2c_board_info i2c_board_info[] __initdata = {
778 {
779 I2C_BOARD_INFO("ak4641", 0x12),
780 .platform_data = &ak4641_info,
781 },
782};
783
784static struct platform_device audio = {
785 .name = "hx4700-audio",
786 .id = -1,
787};
788
789
790/*
768 * PCMCIA 791 * PCMCIA
769 */ 792 */
770 793
@@ -790,6 +813,7 @@ static struct platform_device *devices[] __initdata = {
790 &gpio_vbus, 813 &gpio_vbus,
791 &power_supply, 814 &power_supply,
792 &strataflash, 815 &strataflash,
816 &audio,
793 &pcmcia, 817 &pcmcia,
794}; 818};
795 819
@@ -827,6 +851,7 @@ static void __init hx4700_init(void)
827 pxa_set_ficp_info(&ficp_info); 851 pxa_set_ficp_info(&ficp_info);
828 pxa27x_set_i2c_power_info(NULL); 852 pxa27x_set_i2c_power_info(NULL);
829 pxa_set_i2c_info(NULL); 853 pxa_set_i2c_info(NULL);
854 i2c_register_board_info(0, ARRAY_AND_SIZE(i2c_board_info));
830 i2c_register_board_info(1, ARRAY_AND_SIZE(pi2c_board_info)); 855 i2c_register_board_info(1, ARRAY_AND_SIZE(pi2c_board_info));
831 pxa2xx_set_spi_info(2, &pxa_ssp2_master_info); 856 pxa2xx_set_spi_info(2, &pxa_ssp2_master_info);
832 spi_register_board_info(ARRAY_AND_SIZE(tsc2046_board_info)); 857 spi_register_board_info(ARRAY_AND_SIZE(tsc2046_board_info));
diff --git a/arch/arm/mach-pxa/mfp-pxa2xx.c b/arch/arm/mach-pxa/mfp-pxa2xx.c
index f14775536b83..29b62afc6f7c 100644
--- a/arch/arm/mach-pxa/mfp-pxa2xx.c
+++ b/arch/arm/mach-pxa/mfp-pxa2xx.c
@@ -226,6 +226,12 @@ static void __init pxa25x_mfp_init(void)
226{ 226{
227 int i; 227 int i;
228 228
229 /* running before pxa_gpio_probe() */
230#ifdef CONFIG_CPU_PXA26x
231 pxa_last_gpio = 89;
232#else
233 pxa_last_gpio = 84;
234#endif
229 for (i = 0; i <= pxa_last_gpio; i++) 235 for (i = 0; i <= pxa_last_gpio; i++)
230 gpio_desc[i].valid = 1; 236 gpio_desc[i].valid = 1;
231 237
@@ -295,6 +301,7 @@ static void __init pxa27x_mfp_init(void)
295{ 301{
296 int i, gpio; 302 int i, gpio;
297 303
304 pxa_last_gpio = 120; /* running before pxa_gpio_probe() */
298 for (i = 0; i <= pxa_last_gpio; i++) { 305 for (i = 0; i <= pxa_last_gpio; i++) {
299 /* skip GPIO2, 5, 6, 7, 8, they are not 306 /* skip GPIO2, 5, 6, 7, 8, they are not
300 * valid pins allow configuration 307 * valid pins allow configuration
diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c
index adf058fa97ee..3352b37b60cf 100644
--- a/arch/arm/mach-pxa/pxa25x.c
+++ b/arch/arm/mach-pxa/pxa25x.c
@@ -25,7 +25,6 @@
25#include <linux/suspend.h> 25#include <linux/suspend.h>
26#include <linux/syscore_ops.h> 26#include <linux/syscore_ops.h>
27#include <linux/irq.h> 27#include <linux/irq.h>
28#include <linux/gpio.h>
29 28
30#include <asm/mach/map.h> 29#include <asm/mach/map.h>
31#include <asm/suspend.h> 30#include <asm/suspend.h>
@@ -210,7 +209,6 @@ static struct clk_lookup pxa25x_clkregs[] = {
210 INIT_CLKREG(&clk_pxa25x_gpio12, NULL, "GPIO12_CLK"), 209 INIT_CLKREG(&clk_pxa25x_gpio12, NULL, "GPIO12_CLK"),
211 INIT_CLKREG(&clk_pxa25x_mem, "pxa2xx-pcmcia", NULL), 210 INIT_CLKREG(&clk_pxa25x_mem, "pxa2xx-pcmcia", NULL),
212 INIT_CLKREG(&clk_dummy, "pxa-gpio", NULL), 211 INIT_CLKREG(&clk_dummy, "pxa-gpio", NULL),
213 INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
214}; 212};
215 213
216static struct clk_lookup pxa25x_hwuart_clkreg = 214static struct clk_lookup pxa25x_hwuart_clkreg =
@@ -370,7 +368,6 @@ static int __init pxa25x_init(void)
370 368
371 register_syscore_ops(&pxa_irq_syscore_ops); 369 register_syscore_ops(&pxa_irq_syscore_ops);
372 register_syscore_ops(&pxa2xx_mfp_syscore_ops); 370 register_syscore_ops(&pxa2xx_mfp_syscore_ops);
373 register_syscore_ops(&pxa_gpio_syscore_ops);
374 register_syscore_ops(&pxa2xx_clock_syscore_ops); 371 register_syscore_ops(&pxa2xx_clock_syscore_ops);
375 372
376 ret = platform_add_devices(pxa25x_devices, 373 ret = platform_add_devices(pxa25x_devices,
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c
index 180bd8675d4b..6bce78edce7a 100644
--- a/arch/arm/mach-pxa/pxa27x.c
+++ b/arch/arm/mach-pxa/pxa27x.c
@@ -22,7 +22,6 @@
22#include <linux/io.h> 22#include <linux/io.h>
23#include <linux/irq.h> 23#include <linux/irq.h>
24#include <linux/i2c/pxa-i2c.h> 24#include <linux/i2c/pxa-i2c.h>
25#include <linux/gpio.h>
26 25
27#include <asm/mach/map.h> 26#include <asm/mach/map.h>
28#include <mach/hardware.h> 27#include <mach/hardware.h>
@@ -231,7 +230,6 @@ static struct clk_lookup pxa27x_clkregs[] = {
231 INIT_CLKREG(&clk_pxa27x_memc, NULL, "MEMCLK"), 230 INIT_CLKREG(&clk_pxa27x_memc, NULL, "MEMCLK"),
232 INIT_CLKREG(&clk_pxa27x_mem, "pxa2xx-pcmcia", NULL), 231 INIT_CLKREG(&clk_pxa27x_mem, "pxa2xx-pcmcia", NULL),
233 INIT_CLKREG(&clk_dummy, "pxa-gpio", NULL), 232 INIT_CLKREG(&clk_dummy, "pxa-gpio", NULL),
234 INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
235}; 233};
236 234
237#ifdef CONFIG_PM 235#ifdef CONFIG_PM
@@ -458,7 +456,6 @@ static int __init pxa27x_init(void)
458 456
459 register_syscore_ops(&pxa_irq_syscore_ops); 457 register_syscore_ops(&pxa_irq_syscore_ops);
460 register_syscore_ops(&pxa2xx_mfp_syscore_ops); 458 register_syscore_ops(&pxa2xx_mfp_syscore_ops);
461 register_syscore_ops(&pxa_gpio_syscore_ops);
462 register_syscore_ops(&pxa2xx_clock_syscore_ops); 459 register_syscore_ops(&pxa2xx_clock_syscore_ops);
463 460
464 ret = platform_add_devices(devices, ARRAY_SIZE(devices)); 461 ret = platform_add_devices(devices, ARRAY_SIZE(devices));
diff --git a/arch/arm/mach-pxa/pxa300.c b/arch/arm/mach-pxa/pxa300.c
index 0388eda7878a..40bb16501d86 100644
--- a/arch/arm/mach-pxa/pxa300.c
+++ b/arch/arm/mach-pxa/pxa300.c
@@ -89,7 +89,6 @@ static DEFINE_PXA3_CKEN(gcu, PXA300_GCU, 0, 0);
89static struct clk_lookup common_clkregs[] = { 89static struct clk_lookup common_clkregs[] = {
90 INIT_CLKREG(&clk_common_nand, "pxa3xx-nand", NULL), 90 INIT_CLKREG(&clk_common_nand, "pxa3xx-nand", NULL),
91 INIT_CLKREG(&clk_gcu, "pxa3xx-gcu", NULL), 91 INIT_CLKREG(&clk_gcu, "pxa3xx-gcu", NULL),
92 INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
93}; 92};
94 93
95static DEFINE_PXA3_CKEN(pxa310_mmc3, MMC3, 19500000, 0); 94static DEFINE_PXA3_CKEN(pxa310_mmc3, MMC3, 19500000, 0);
diff --git a/arch/arm/mach-pxa/pxa320.c b/arch/arm/mach-pxa/pxa320.c
index d487e1ff4c9a..8d614ecd8e99 100644
--- a/arch/arm/mach-pxa/pxa320.c
+++ b/arch/arm/mach-pxa/pxa320.c
@@ -83,7 +83,6 @@ static DEFINE_PXA3_CKEN(gcu, PXA320_GCU, 0, 0);
83static struct clk_lookup pxa320_clkregs[] = { 83static struct clk_lookup pxa320_clkregs[] = {
84 INIT_CLKREG(&clk_pxa320_nand, "pxa3xx-nand", NULL), 84 INIT_CLKREG(&clk_pxa320_nand, "pxa3xx-nand", NULL),
85 INIT_CLKREG(&clk_gcu, "pxa3xx-gcu", NULL), 85 INIT_CLKREG(&clk_gcu, "pxa3xx-gcu", NULL),
86 INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
87}; 86};
88 87
89static int __init pxa320_init(void) 88static int __init pxa320_init(void)
diff --git a/arch/arm/mach-pxa/pxa3xx-ulpi.c b/arch/arm/mach-pxa/pxa3xx-ulpi.c
index e28dfb88827f..5ead6d480c6d 100644
--- a/arch/arm/mach-pxa/pxa3xx-ulpi.c
+++ b/arch/arm/mach-pxa/pxa3xx-ulpi.c
@@ -33,7 +33,7 @@ struct pxa3xx_u2d_ulpi {
33 struct clk *clk; 33 struct clk *clk;
34 void __iomem *mmio_base; 34 void __iomem *mmio_base;
35 35
36 struct otg_transceiver *otg; 36 struct usb_phy *otg;
37 unsigned int ulpi_mode; 37 unsigned int ulpi_mode;
38}; 38};
39 39
@@ -79,7 +79,7 @@ static int pxa310_ulpi_poll(void)
79 return -ETIMEDOUT; 79 return -ETIMEDOUT;
80} 80}
81 81
82static int pxa310_ulpi_read(struct otg_transceiver *otg, u32 reg) 82static int pxa310_ulpi_read(struct usb_phy *otg, u32 reg)
83{ 83{
84 int err; 84 int err;
85 85
@@ -98,7 +98,7 @@ static int pxa310_ulpi_read(struct otg_transceiver *otg, u32 reg)
98 return u2d_readl(U2DOTGUCR) & U2DOTGUCR_RDATA; 98 return u2d_readl(U2DOTGUCR) & U2DOTGUCR_RDATA;
99} 99}
100 100
101static int pxa310_ulpi_write(struct otg_transceiver *otg, u32 val, u32 reg) 101static int pxa310_ulpi_write(struct usb_phy *otg, u32 val, u32 reg)
102{ 102{
103 if (pxa310_ulpi_get_phymode() != SYNCH) { 103 if (pxa310_ulpi_get_phymode() != SYNCH) {
104 pr_warning("%s: PHY is not in SYNCH mode!\n", __func__); 104 pr_warning("%s: PHY is not in SYNCH mode!\n", __func__);
@@ -111,7 +111,7 @@ static int pxa310_ulpi_write(struct otg_transceiver *otg, u32 val, u32 reg)
111 return pxa310_ulpi_poll(); 111 return pxa310_ulpi_poll();
112} 112}
113 113
114struct otg_io_access_ops pxa310_ulpi_access_ops = { 114struct usb_phy_io_ops pxa310_ulpi_access_ops = {
115 .read = pxa310_ulpi_read, 115 .read = pxa310_ulpi_read,
116 .write = pxa310_ulpi_write, 116 .write = pxa310_ulpi_write,
117}; 117};
@@ -139,19 +139,19 @@ static int pxa310_start_otg_host_transcvr(struct usb_bus *host)
139 139
140 pxa310_otg_transceiver_rtsm(); 140 pxa310_otg_transceiver_rtsm();
141 141
142 err = otg_init(u2d->otg); 142 err = usb_phy_init(u2d->otg);
143 if (err) { 143 if (err) {
144 pr_err("OTG transceiver init failed"); 144 pr_err("OTG transceiver init failed");
145 return err; 145 return err;
146 } 146 }
147 147
148 err = otg_set_vbus(u2d->otg, 1); 148 err = otg_set_vbus(u2d->otg->otg, 1);
149 if (err) { 149 if (err) {
150 pr_err("OTG transceiver VBUS set failed"); 150 pr_err("OTG transceiver VBUS set failed");
151 return err; 151 return err;
152 } 152 }
153 153
154 err = otg_set_host(u2d->otg, host); 154 err = otg_set_host(u2d->otg->otg, host);
155 if (err) 155 if (err)
156 pr_err("OTG transceiver Host mode set failed"); 156 pr_err("OTG transceiver Host mode set failed");
157 157
@@ -189,9 +189,9 @@ static void pxa310_stop_otg_hc(void)
189{ 189{
190 pxa310_otg_transceiver_rtsm(); 190 pxa310_otg_transceiver_rtsm();
191 191
192 otg_set_host(u2d->otg, NULL); 192 otg_set_host(u2d->otg->otg, NULL);
193 otg_set_vbus(u2d->otg, 0); 193 otg_set_vbus(u2d->otg->otg, 0);
194 otg_shutdown(u2d->otg); 194 usb_phy_shutdown(u2d->otg);
195} 195}
196 196
197static void pxa310_u2d_setup_otg_hc(void) 197static void pxa310_u2d_setup_otg_hc(void)
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
index f107c71c7589..3918a672238e 100644
--- a/arch/arm/mach-pxa/pxa3xx.c
+++ b/arch/arm/mach-pxa/pxa3xx.c
@@ -67,7 +67,6 @@ static struct clk_lookup pxa3xx_clkregs[] = {
67 INIT_CLKREG(&clk_pxa3xx_pout, NULL, "CLK_POUT"), 67 INIT_CLKREG(&clk_pxa3xx_pout, NULL, "CLK_POUT"),
68 /* Power I2C clock is always on */ 68 /* Power I2C clock is always on */
69 INIT_CLKREG(&clk_dummy, "pxa3xx-pwri2c.1", NULL), 69 INIT_CLKREG(&clk_dummy, "pxa3xx-pwri2c.1", NULL),
70 INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
71 INIT_CLKREG(&clk_pxa3xx_lcd, "pxa2xx-fb", NULL), 70 INIT_CLKREG(&clk_pxa3xx_lcd, "pxa2xx-fb", NULL),
72 INIT_CLKREG(&clk_pxa3xx_camera, NULL, "CAMCLK"), 71 INIT_CLKREG(&clk_pxa3xx_camera, NULL, "CAMCLK"),
73 INIT_CLKREG(&clk_pxa3xx_ac97, NULL, "AC97CLK"), 72 INIT_CLKREG(&clk_pxa3xx_ac97, NULL, "AC97CLK"),
@@ -463,7 +462,6 @@ static int __init pxa3xx_init(void)
463 462
464 register_syscore_ops(&pxa_irq_syscore_ops); 463 register_syscore_ops(&pxa_irq_syscore_ops);
465 register_syscore_ops(&pxa3xx_mfp_syscore_ops); 464 register_syscore_ops(&pxa3xx_mfp_syscore_ops);
466 register_syscore_ops(&pxa_gpio_syscore_ops);
467 register_syscore_ops(&pxa3xx_clock_syscore_ops); 465 register_syscore_ops(&pxa3xx_clock_syscore_ops);
468 466
469 ret = platform_add_devices(devices, ARRAY_SIZE(devices)); 467 ret = platform_add_devices(devices, ARRAY_SIZE(devices));
diff --git a/arch/arm/mach-pxa/pxa95x.c b/arch/arm/mach-pxa/pxa95x.c
index fccc644702e6..5ce434b95e87 100644
--- a/arch/arm/mach-pxa/pxa95x.c
+++ b/arch/arm/mach-pxa/pxa95x.c
@@ -217,7 +217,6 @@ static struct clk_lookup pxa95x_clkregs[] = {
217 INIT_CLKREG(&clk_pxa95x_pout, NULL, "CLK_POUT"), 217 INIT_CLKREG(&clk_pxa95x_pout, NULL, "CLK_POUT"),
218 /* Power I2C clock is always on */ 218 /* Power I2C clock is always on */
219 INIT_CLKREG(&clk_dummy, "pxa3xx-pwri2c.1", NULL), 219 INIT_CLKREG(&clk_dummy, "pxa3xx-pwri2c.1", NULL),
220 INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
221 INIT_CLKREG(&clk_pxa95x_lcd, "pxa2xx-fb", NULL), 220 INIT_CLKREG(&clk_pxa95x_lcd, "pxa2xx-fb", NULL),
222 INIT_CLKREG(&clk_pxa95x_ffuart, "pxa2xx-uart.0", NULL), 221 INIT_CLKREG(&clk_pxa95x_ffuart, "pxa2xx-uart.0", NULL),
223 INIT_CLKREG(&clk_pxa95x_btuart, "pxa2xx-uart.1", NULL), 222 INIT_CLKREG(&clk_pxa95x_btuart, "pxa2xx-uart.1", NULL),
@@ -284,7 +283,6 @@ static int __init pxa95x_init(void)
284 return ret; 283 return ret;
285 284
286 register_syscore_ops(&pxa_irq_syscore_ops); 285 register_syscore_ops(&pxa_irq_syscore_ops);
287 register_syscore_ops(&pxa_gpio_syscore_ops);
288 register_syscore_ops(&pxa3xx_clock_syscore_ops); 286 register_syscore_ops(&pxa3xx_clock_syscore_ops);
289 287
290 ret = platform_add_devices(devices, ARRAY_SIZE(devices)); 288 ret = platform_add_devices(devices, ARRAY_SIZE(devices));
diff --git a/arch/arm/mach-pxa/saarb.c b/arch/arm/mach-pxa/saarb.c
index febc809ed5a6..5aded5e6148f 100644
--- a/arch/arm/mach-pxa/saarb.c
+++ b/arch/arm/mach-pxa/saarb.c
@@ -15,7 +15,6 @@
15#include <linux/i2c.h> 15#include <linux/i2c.h>
16#include <linux/i2c/pxa-i2c.h> 16#include <linux/i2c/pxa-i2c.h>
17#include <linux/mfd/88pm860x.h> 17#include <linux/mfd/88pm860x.h>
18#include <linux/gpio.h>
19 18
20#include <asm/mach-types.h> 19#include <asm/mach-types.h>
21#include <asm/mach/arch.h> 20#include <asm/mach/arch.h>
diff --git a/arch/arm/mach-pxa/sharpsl_pm.c b/arch/arm/mach-pxa/sharpsl_pm.c
index 8d5168d253a9..30989baf7f2a 100644
--- a/arch/arm/mach-pxa/sharpsl_pm.c
+++ b/arch/arm/mach-pxa/sharpsl_pm.c
@@ -168,6 +168,7 @@ struct battery_thresh sharpsl_battery_levels_noac[] = {
168#define MAXCTRL_SEL_SH 4 168#define MAXCTRL_SEL_SH 4
169#define MAXCTRL_STR (1u << 7) 169#define MAXCTRL_STR (1u << 7)
170 170
171extern int max1111_read_channel(int);
171/* 172/*
172 * Read MAX1111 ADC 173 * Read MAX1111 ADC
173 */ 174 */
@@ -177,8 +178,6 @@ int sharpsl_pm_pxa_read_max1111(int channel)
177 if (machine_is_tosa()) 178 if (machine_is_tosa())
178 return 0; 179 return 0;
179 180
180 extern int max1111_read_channel(int);
181
182 /* max1111 accepts channels from 0-3, however, 181 /* max1111 accepts channels from 0-3, however,
183 * it is encoded from 0-7 here in the code. 182 * it is encoded from 0-7 here in the code.
184 */ 183 */
diff --git a/arch/arm/mach-pxa/spitz_pm.c b/arch/arm/mach-pxa/spitz_pm.c
index 34cbdac51525..438f02fe122a 100644
--- a/arch/arm/mach-pxa/spitz_pm.c
+++ b/arch/arm/mach-pxa/spitz_pm.c
@@ -172,10 +172,9 @@ static int spitz_should_wakeup(unsigned int resume_on_alarm)
172static unsigned long spitz_charger_wakeup(void) 172static unsigned long spitz_charger_wakeup(void)
173{ 173{
174 unsigned long ret; 174 unsigned long ret;
175 ret = (!gpio_get_value(SPITZ_GPIO_KEY_INT) 175 ret = ((!gpio_get_value(SPITZ_GPIO_KEY_INT)
176 << GPIO_bit(SPITZ_GPIO_KEY_INT)) 176 << GPIO_bit(SPITZ_GPIO_KEY_INT))
177 | (!gpio_get_value(SPITZ_GPIO_SYNC) 177 | gpio_get_value(SPITZ_GPIO_SYNC));
178 << GPIO_bit(SPITZ_GPIO_SYNC));
179 return ret; 178 return ret;
180} 179}
181 180
diff --git a/arch/arm/mach-realview/hotplug.c b/arch/arm/mach-realview/hotplug.c
index ac1aed2a8da4..eb55f05bef3a 100644
--- a/arch/arm/mach-realview/hotplug.c
+++ b/arch/arm/mach-realview/hotplug.c
@@ -13,6 +13,7 @@
13#include <linux/smp.h> 13#include <linux/smp.h>
14 14
15#include <asm/cacheflush.h> 15#include <asm/cacheflush.h>
16#include <asm/smp_plat.h>
16 17
17extern volatile int pen_release; 18extern volatile int pen_release;
18 19
diff --git a/arch/arm/mach-realview/include/mach/board-eb.h b/arch/arm/mach-realview/include/mach/board-eb.h
index 794a8d91a6a6..124bce6b4d7b 100644
--- a/arch/arm/mach-realview/include/mach/board-eb.h
+++ b/arch/arm/mach-realview/include/mach/board-eb.h
@@ -47,21 +47,23 @@
47#define REALVIEW_EB_USB_BASE 0x4F000000 /* USB */ 47#define REALVIEW_EB_USB_BASE 0x4F000000 /* USB */
48 48
49#ifdef CONFIG_REALVIEW_EB_ARM11MP_REVB 49#ifdef CONFIG_REALVIEW_EB_ARM11MP_REVB
50#define REALVIEW_EB11MP_SCU_BASE 0x10100000 /* SCU registers */ 50#define REALVIEW_EB11MP_PRIV_MEM_BASE 0x1F000000
51#define REALVIEW_EB11MP_GIC_CPU_BASE 0x10100100 /* Generic interrupt controller CPU interface */
52#define REALVIEW_EB11MP_TWD_BASE 0x10100600
53#define REALVIEW_EB11MP_GIC_DIST_BASE 0x10101000 /* Generic interrupt controller distributor */
54#define REALVIEW_EB11MP_L220_BASE 0x10102000 /* L220 registers */ 51#define REALVIEW_EB11MP_L220_BASE 0x10102000 /* L220 registers */
55#define REALVIEW_EB11MP_SYS_PLD_CTRL1 0xD8 /* Register offset for MPCore sysctl */ 52#define REALVIEW_EB11MP_SYS_PLD_CTRL1 0xD8 /* Register offset for MPCore sysctl */
56#else 53#else
57#define REALVIEW_EB11MP_SCU_BASE 0x1F000000 /* SCU registers */ 54#define REALVIEW_EB11MP_PRIV_MEM_BASE 0x1F000000
58#define REALVIEW_EB11MP_GIC_CPU_BASE 0x1F000100 /* Generic interrupt controller CPU interface */
59#define REALVIEW_EB11MP_TWD_BASE 0x1F000600
60#define REALVIEW_EB11MP_GIC_DIST_BASE 0x1F001000 /* Generic interrupt controller distributor */
61#define REALVIEW_EB11MP_L220_BASE 0x1F002000 /* L220 registers */ 55#define REALVIEW_EB11MP_L220_BASE 0x1F002000 /* L220 registers */
62#define REALVIEW_EB11MP_SYS_PLD_CTRL1 0x74 /* Register offset for MPCore sysctl */ 56#define REALVIEW_EB11MP_SYS_PLD_CTRL1 0x74 /* Register offset for MPCore sysctl */
63#endif 57#endif
64 58
59#define REALVIEW_EB11MP_PRIV_MEM_SIZE SZ_8K
60#define REALVIEW_EB11MP_PRIV_MEM_OFF(x) (REALVIEW_EB11MP_PRIV_MEM_BASE + (x))
61
62#define REALVIEW_EB11MP_SCU_BASE REALVIEW_EB11MP_PRIV_MEM_OFF(0) /* SCU registers */
63#define REALVIEW_EB11MP_GIC_CPU_BASE REALVIEW_EB11MP_PRIV_MEM_OFF(0x0100) /* Generic interrupt controller CPU interface */
64#define REALVIEW_EB11MP_TWD_BASE REALVIEW_EB11MP_PRIV_MEM_OFF(0x0600)
65#define REALVIEW_EB11MP_GIC_DIST_BASE REALVIEW_EB11MP_PRIV_MEM_OFF(0x1000) /* Generic interrupt controller distributor */
66
65/* 67/*
66 * Core tile identification (REALVIEW_SYS_PROCID) 68 * Core tile identification (REALVIEW_SYS_PROCID)
67 */ 69 */
diff --git a/arch/arm/mach-realview/include/mach/board-pb11mp.h b/arch/arm/mach-realview/include/mach/board-pb11mp.h
index 7abf918b77e9..aa2d4e02ea2c 100644
--- a/arch/arm/mach-realview/include/mach/board-pb11mp.h
+++ b/arch/arm/mach-realview/include/mach/board-pb11mp.h
@@ -75,6 +75,8 @@
75/* 75/*
76 * Testchip peripheral and fpga gic regions 76 * Testchip peripheral and fpga gic regions
77 */ 77 */
78#define REALVIEW_TC11MP_PRIV_MEM_BASE 0x1F000000
79#define REALVIEW_TC11MP_PRIV_MEM_SIZE SZ_8K
78#define REALVIEW_TC11MP_SCU_BASE 0x1F000000 /* IRQ, Test chip */ 80#define REALVIEW_TC11MP_SCU_BASE 0x1F000000 /* IRQ, Test chip */
79#define REALVIEW_TC11MP_GIC_CPU_BASE 0x1F000100 /* Test chip interrupt controller CPU interface */ 81#define REALVIEW_TC11MP_GIC_CPU_BASE 0x1F000100 /* Test chip interrupt controller CPU interface */
80#define REALVIEW_TC11MP_TWD_BASE 0x1F000600 82#define REALVIEW_TC11MP_TWD_BASE 0x1F000600
diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c
index e62962117763..9578145f2df0 100644
--- a/arch/arm/mach-realview/realview_eb.c
+++ b/arch/arm/mach-realview/realview_eb.c
@@ -91,14 +91,9 @@ static struct map_desc realview_eb_io_desc[] __initdata = {
91 91
92static struct map_desc realview_eb11mp_io_desc[] __initdata = { 92static struct map_desc realview_eb11mp_io_desc[] __initdata = {
93 { 93 {
94 .virtual = IO_ADDRESS(REALVIEW_EB11MP_SCU_BASE), 94 .virtual = IO_ADDRESS(REALVIEW_EB11MP_PRIV_MEM_BASE),
95 .pfn = __phys_to_pfn(REALVIEW_EB11MP_SCU_BASE), 95 .pfn = __phys_to_pfn(REALVIEW_EB11MP_PRIV_MEM_BASE),
96 .length = SZ_4K, 96 .length = REALVIEW_EB11MP_PRIV_MEM_SIZE,
97 .type = MT_DEVICE,
98 }, {
99 .virtual = IO_ADDRESS(REALVIEW_EB11MP_GIC_DIST_BASE),
100 .pfn = __phys_to_pfn(REALVIEW_EB11MP_GIC_DIST_BASE),
101 .length = SZ_4K,
102 .type = MT_DEVICE, 97 .type = MT_DEVICE,
103 }, { 98 }, {
104 .virtual = IO_ADDRESS(REALVIEW_EB11MP_L220_BASE), 99 .virtual = IO_ADDRESS(REALVIEW_EB11MP_L220_BASE),
diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c
index 127a3fd42ab1..2147335f66f5 100644
--- a/arch/arm/mach-realview/realview_pb11mp.c
+++ b/arch/arm/mach-realview/realview_pb11mp.c
@@ -64,15 +64,10 @@ static struct map_desc realview_pb11mp_io_desc[] __initdata = {
64 .pfn = __phys_to_pfn(REALVIEW_PB11MP_GIC_DIST_BASE), 64 .pfn = __phys_to_pfn(REALVIEW_PB11MP_GIC_DIST_BASE),
65 .length = SZ_4K, 65 .length = SZ_4K,
66 .type = MT_DEVICE, 66 .type = MT_DEVICE,
67 }, { 67 }, { /* Maps the SCU, GIC CPU interface, TWD, GIC DIST */
68 .virtual = IO_ADDRESS(REALVIEW_TC11MP_GIC_CPU_BASE), 68 .virtual = IO_ADDRESS(REALVIEW_TC11MP_PRIV_MEM_BASE),
69 .pfn = __phys_to_pfn(REALVIEW_TC11MP_GIC_CPU_BASE), 69 .pfn = __phys_to_pfn(REALVIEW_TC11MP_PRIV_MEM_BASE),
70 .length = SZ_4K, 70 .length = REALVIEW_TC11MP_PRIV_MEM_SIZE,
71 .type = MT_DEVICE,
72 }, {
73 .virtual = IO_ADDRESS(REALVIEW_TC11MP_GIC_DIST_BASE),
74 .pfn = __phys_to_pfn(REALVIEW_TC11MP_GIC_DIST_BASE),
75 .length = SZ_4K,
76 .type = MT_DEVICE, 71 .type = MT_DEVICE,
77 }, { 72 }, {
78 .virtual = IO_ADDRESS(REALVIEW_SCTL_BASE), 73 .virtual = IO_ADDRESS(REALVIEW_SCTL_BASE),
diff --git a/arch/arm/mach-s3c2410/cpu-freq.c b/arch/arm/mach-s3c2410/cpu-freq.c
index 7dc6c46b5e2b..5404535da1a5 100644
--- a/arch/arm/mach-s3c2410/cpu-freq.c
+++ b/arch/arm/mach-s3c2410/cpu-freq.c
@@ -115,7 +115,8 @@ static struct s3c_cpufreq_info s3c2410_cpufreq_info = {
115 .debug_io_show = s3c_cpufreq_debugfs_call(s3c2410_iotiming_debugfs), 115 .debug_io_show = s3c_cpufreq_debugfs_call(s3c2410_iotiming_debugfs),
116}; 116};
117 117
118static int s3c2410_cpufreq_add(struct device *dev) 118static int s3c2410_cpufreq_add(struct device *dev,
119 struct subsys_interface *sif)
119{ 120{
120 return s3c_cpufreq_register(&s3c2410_cpufreq_info); 121 return s3c_cpufreq_register(&s3c2410_cpufreq_info);
121} 122}
@@ -133,7 +134,8 @@ static int __init s3c2410_cpufreq_init(void)
133 134
134arch_initcall(s3c2410_cpufreq_init); 135arch_initcall(s3c2410_cpufreq_init);
135 136
136static int s3c2410a_cpufreq_add(struct device *dev) 137static int s3c2410a_cpufreq_add(struct device *dev,
138 struct subsys_interface *sif)
137{ 139{
138 /* alter the maximum freq settings for S3C2410A. If a board knows 140 /* alter the maximum freq settings for S3C2410A. If a board knows
139 * it only has a maximum of 200, then it should register its own 141 * it only has a maximum of 200, then it should register its own
@@ -144,7 +146,7 @@ static int s3c2410a_cpufreq_add(struct device *dev)
144 s3c2410_cpufreq_info.max.pclk = 66500000; 146 s3c2410_cpufreq_info.max.pclk = 66500000;
145 s3c2410_cpufreq_info.name = "s3c2410a"; 147 s3c2410_cpufreq_info.name = "s3c2410a";
146 148
147 return s3c2410_cpufreq_add(dev); 149 return s3c2410_cpufreq_add(dev, sif);
148} 150}
149 151
150static struct subsys_interface s3c2410a_cpufreq_interface = { 152static struct subsys_interface s3c2410a_cpufreq_interface = {
diff --git a/arch/arm/mach-s3c2410/dma.c b/arch/arm/mach-s3c2410/dma.c
index 2afd00014a77..4803338cf56e 100644
--- a/arch/arm/mach-s3c2410/dma.c
+++ b/arch/arm/mach-s3c2410/dma.c
@@ -132,7 +132,8 @@ static struct s3c24xx_dma_order __initdata s3c2410_dma_order = {
132 }, 132 },
133}; 133};
134 134
135static int __init s3c2410_dma_add(struct device *dev) 135static int __init s3c2410_dma_add(struct device *dev,
136 struct subsys_interface *sif)
136{ 137{
137 s3c2410_dma_init(); 138 s3c2410_dma_init();
138 s3c24xx_dma_order_set(&s3c2410_dma_order); 139 s3c24xx_dma_order_set(&s3c2410_dma_order);
@@ -148,7 +149,7 @@ static struct subsys_interface s3c2410_dma_interface = {
148 149
149static int __init s3c2410_dma_drvinit(void) 150static int __init s3c2410_dma_drvinit(void)
150{ 151{
151 return subsys_interface_register(&s3c2410_interface); 152 return subsys_interface_register(&s3c2410_dma_interface);
152} 153}
153 154
154arch_initcall(s3c2410_dma_drvinit); 155arch_initcall(s3c2410_dma_drvinit);
diff --git a/arch/arm/mach-s3c2410/pll.c b/arch/arm/mach-s3c2410/pll.c
index c07438bfc99f..e0b3b347da82 100644
--- a/arch/arm/mach-s3c2410/pll.c
+++ b/arch/arm/mach-s3c2410/pll.c
@@ -66,7 +66,7 @@ static struct cpufreq_frequency_table pll_vals_12MHz[] = {
66 { .frequency = 270000000, .index = PLLVAL(127, 1, 1), }, 66 { .frequency = 270000000, .index = PLLVAL(127, 1, 1), },
67}; 67};
68 68
69static int s3c2410_plls_add(struct device *dev) 69static int s3c2410_plls_add(struct device *dev, struct subsys_interface *sif)
70{ 70{
71 return s3c_plltab_register(pll_vals_12MHz, ARRAY_SIZE(pll_vals_12MHz)); 71 return s3c_plltab_register(pll_vals_12MHz, ARRAY_SIZE(pll_vals_12MHz));
72} 72}
diff --git a/arch/arm/mach-s3c2410/pm.c b/arch/arm/mach-s3c2410/pm.c
index fda5385deff6..03f706dd6009 100644
--- a/arch/arm/mach-s3c2410/pm.c
+++ b/arch/arm/mach-s3c2410/pm.c
@@ -111,7 +111,7 @@ struct syscore_ops s3c2410_pm_syscore_ops = {
111 .resume = s3c2410_pm_resume, 111 .resume = s3c2410_pm_resume,
112}; 112};
113 113
114static int s3c2410_pm_add(struct device *dev) 114static int s3c2410_pm_add(struct device *dev, struct subsys_interface *sif)
115{ 115{
116 pm_cpu_prep = s3c2410_pm_prepare; 116 pm_cpu_prep = s3c2410_pm_prepare;
117 pm_cpu_sleep = s3c2410_cpu_suspend; 117 pm_cpu_sleep = s3c2410_cpu_suspend;
diff --git a/arch/arm/mach-s3c2412/cpu-freq.c b/arch/arm/mach-s3c2412/cpu-freq.c
index d8664b7652ce..125be7d5fa60 100644
--- a/arch/arm/mach-s3c2412/cpu-freq.c
+++ b/arch/arm/mach-s3c2412/cpu-freq.c
@@ -194,7 +194,8 @@ static struct s3c_cpufreq_info s3c2412_cpufreq_info = {
194 .debug_io_show = s3c_cpufreq_debugfs_call(s3c2412_iotiming_debugfs), 194 .debug_io_show = s3c_cpufreq_debugfs_call(s3c2412_iotiming_debugfs),
195}; 195};
196 196
197static int s3c2412_cpufreq_add(struct device *dev) 197static int s3c2412_cpufreq_add(struct device *dev,
198 struct subsys_interface *sif)
198{ 199{
199 unsigned long fclk_rate; 200 unsigned long fclk_rate;
200 201
diff --git a/arch/arm/mach-s3c2412/dma.c b/arch/arm/mach-s3c2412/dma.c
index 142acd3b5e15..38472ac920ff 100644
--- a/arch/arm/mach-s3c2412/dma.c
+++ b/arch/arm/mach-s3c2412/dma.c
@@ -159,7 +159,8 @@ static struct s3c24xx_dma_selection __initdata s3c2412_dma_sel = {
159 .map_size = ARRAY_SIZE(s3c2412_dma_mappings), 159 .map_size = ARRAY_SIZE(s3c2412_dma_mappings),
160}; 160};
161 161
162static int __init s3c2412_dma_add(struct device *dev) 162static int __init s3c2412_dma_add(struct device *dev,
163 struct subsys_interface *sif)
163{ 164{
164 s3c2410_dma_init(); 165 s3c2410_dma_init();
165 return s3c24xx_dma_init_map(&s3c2412_dma_sel); 166 return s3c24xx_dma_init_map(&s3c2412_dma_sel);
diff --git a/arch/arm/mach-s3c2412/irq.c b/arch/arm/mach-s3c2412/irq.c
index a8a46c1644f4..e65619ddbccc 100644
--- a/arch/arm/mach-s3c2412/irq.c
+++ b/arch/arm/mach-s3c2412/irq.c
@@ -170,7 +170,7 @@ static int s3c2412_irq_rtc_wake(struct irq_data *data, unsigned int state)
170 170
171static struct irq_chip s3c2412_irq_rtc_chip; 171static struct irq_chip s3c2412_irq_rtc_chip;
172 172
173static int s3c2412_irq_add(struct device *dev) 173static int s3c2412_irq_add(struct device *dev, struct subsys_interface *sif)
174{ 174{
175 unsigned int irqno; 175 unsigned int irqno;
176 176
diff --git a/arch/arm/mach-s3c2412/pm.c b/arch/arm/mach-s3c2412/pm.c
index d1adfa65f66d..d04588506ec4 100644
--- a/arch/arm/mach-s3c2412/pm.c
+++ b/arch/arm/mach-s3c2412/pm.c
@@ -56,7 +56,7 @@ static void s3c2412_pm_prepare(void)
56{ 56{
57} 57}
58 58
59static int s3c2412_pm_add(struct device *dev) 59static int s3c2412_pm_add(struct device *dev, struct subsys_interface *sif)
60{ 60{
61 pm_cpu_prep = s3c2412_pm_prepare; 61 pm_cpu_prep = s3c2412_pm_prepare;
62 pm_cpu_sleep = s3c2412_cpu_suspend; 62 pm_cpu_sleep = s3c2412_cpu_suspend;
diff --git a/arch/arm/mach-s3c2416/irq.c b/arch/arm/mach-s3c2416/irq.c
index 36df761061de..fd49f35e448e 100644
--- a/arch/arm/mach-s3c2416/irq.c
+++ b/arch/arm/mach-s3c2416/irq.c
@@ -213,7 +213,8 @@ static int __init s3c2416_add_sub(unsigned int base,
213 return 0; 213 return 0;
214} 214}
215 215
216static int __init s3c2416_irq_add(struct device *dev) 216static int __init s3c2416_irq_add(struct device *dev,
217 struct subsys_interface *sif)
217{ 218{
218 printk(KERN_INFO "S3C2416: IRQ Support\n"); 219 printk(KERN_INFO "S3C2416: IRQ Support\n");
219 220
diff --git a/arch/arm/mach-s3c2416/pm.c b/arch/arm/mach-s3c2416/pm.c
index 3bdb15a0d419..1bd4817b8eb8 100644
--- a/arch/arm/mach-s3c2416/pm.c
+++ b/arch/arm/mach-s3c2416/pm.c
@@ -48,7 +48,7 @@ static void s3c2416_pm_prepare(void)
48 __raw_writel(virt_to_phys(s3c_cpu_resume), S3C2412_INFORM1); 48 __raw_writel(virt_to_phys(s3c_cpu_resume), S3C2412_INFORM1);
49} 49}
50 50
51static int s3c2416_pm_add(struct device *dev) 51static int s3c2416_pm_add(struct device *dev, struct subsys_interface *sif)
52{ 52{
53 pm_cpu_prep = s3c2416_pm_prepare; 53 pm_cpu_prep = s3c2416_pm_prepare;
54 pm_cpu_sleep = s3c2416_cpu_suspend; 54 pm_cpu_sleep = s3c2416_cpu_suspend;
diff --git a/arch/arm/mach-s3c2440/clock.c b/arch/arm/mach-s3c2440/clock.c
index bedbc87a3426..414364eb426c 100644
--- a/arch/arm/mach-s3c2440/clock.c
+++ b/arch/arm/mach-s3c2440/clock.c
@@ -149,7 +149,7 @@ static struct clk_lookup s3c2440_clk_lookup[] = {
149 CLKDEV_INIT(NULL, "clk_uart_baud3", &s3c2440_clk_fclk_n), 149 CLKDEV_INIT(NULL, "clk_uart_baud3", &s3c2440_clk_fclk_n),
150}; 150};
151 151
152static int s3c2440_clk_add(struct device *dev) 152static int s3c2440_clk_add(struct device *dev, struct subsys_interface *sif)
153{ 153{
154 struct clk *clock_upll; 154 struct clk *clock_upll;
155 struct clk *clock_h; 155 struct clk *clock_h;
diff --git a/arch/arm/mach-s3c2440/common.h b/arch/arm/mach-s3c2440/common.h
index db8a98ac68c5..0c1eb1dfc534 100644
--- a/arch/arm/mach-s3c2440/common.h
+++ b/arch/arm/mach-s3c2440/common.h
@@ -12,6 +12,6 @@
12#ifndef __ARCH_ARM_MACH_S3C2440_COMMON_H 12#ifndef __ARCH_ARM_MACH_S3C2440_COMMON_H
13#define __ARCH_ARM_MACH_S3C2440_COMMON_H 13#define __ARCH_ARM_MACH_S3C2440_COMMON_H
14 14
15void s3c2440_restart(char mode, const char *cmd); 15void s3c244x_restart(char mode, const char *cmd);
16 16
17#endif /* __ARCH_ARM_MACH_S3C2440_COMMON_H */ 17#endif /* __ARCH_ARM_MACH_S3C2440_COMMON_H */
diff --git a/arch/arm/mach-s3c2440/dma.c b/arch/arm/mach-s3c2440/dma.c
index 15b1ddf8f626..5f0a0c8ef84f 100644
--- a/arch/arm/mach-s3c2440/dma.c
+++ b/arch/arm/mach-s3c2440/dma.c
@@ -174,7 +174,8 @@ static struct s3c24xx_dma_order __initdata s3c2440_dma_order = {
174 }, 174 },
175}; 175};
176 176
177static int __init s3c2440_dma_add(struct device *dev) 177static int __init s3c2440_dma_add(struct device *dev,
178 struct subsys_interface *sif)
178{ 179{
179 s3c2410_dma_init(); 180 s3c2410_dma_init();
180 s3c24xx_dma_order_set(&s3c2440_dma_order); 181 s3c24xx_dma_order_set(&s3c2440_dma_order);
diff --git a/arch/arm/mach-s3c2440/irq.c b/arch/arm/mach-s3c2440/irq.c
index 4fee9bc6bcb5..4a18cde439cc 100644
--- a/arch/arm/mach-s3c2440/irq.c
+++ b/arch/arm/mach-s3c2440/irq.c
@@ -92,7 +92,7 @@ static struct irq_chip s3c_irq_wdtac97 = {
92 .irq_ack = s3c_irq_wdtac97_ack, 92 .irq_ack = s3c_irq_wdtac97_ack,
93}; 93};
94 94
95static int s3c2440_irq_add(struct device *dev) 95static int s3c2440_irq_add(struct device *dev, struct subsys_interface *sif)
96{ 96{
97 unsigned int irqno; 97 unsigned int irqno;
98 98
diff --git a/arch/arm/mach-s3c2440/mach-anubis.c b/arch/arm/mach-s3c2440/mach-anubis.c
index 24569550de1a..19b577bc09b8 100644
--- a/arch/arm/mach-s3c2440/mach-anubis.c
+++ b/arch/arm/mach-s3c2440/mach-anubis.c
@@ -487,5 +487,5 @@ MACHINE_START(ANUBIS, "Simtec-Anubis")
487 .init_machine = anubis_init, 487 .init_machine = anubis_init,
488 .init_irq = s3c24xx_init_irq, 488 .init_irq = s3c24xx_init_irq,
489 .timer = &s3c24xx_timer, 489 .timer = &s3c24xx_timer,
490 .restart = s3c2440_restart, 490 .restart = s3c244x_restart,
491MACHINE_END 491MACHINE_END
diff --git a/arch/arm/mach-s3c2440/mach-at2440evb.c b/arch/arm/mach-s3c2440/mach-at2440evb.c
index d6a9763110cd..d7ae49c90118 100644
--- a/arch/arm/mach-s3c2440/mach-at2440evb.c
+++ b/arch/arm/mach-s3c2440/mach-at2440evb.c
@@ -222,5 +222,5 @@ MACHINE_START(AT2440EVB, "AT2440EVB")
222 .init_machine = at2440evb_init, 222 .init_machine = at2440evb_init,
223 .init_irq = s3c24xx_init_irq, 223 .init_irq = s3c24xx_init_irq,
224 .timer = &s3c24xx_timer, 224 .timer = &s3c24xx_timer,
225 .restart = s3c2440_restart, 225 .restart = s3c244x_restart,
226MACHINE_END 226MACHINE_END
diff --git a/arch/arm/mach-s3c2440/mach-gta02.c b/arch/arm/mach-s3c2440/mach-gta02.c
index 5859e609d28c..9a4a5bc008e6 100644
--- a/arch/arm/mach-s3c2440/mach-gta02.c
+++ b/arch/arm/mach-s3c2440/mach-gta02.c
@@ -601,5 +601,5 @@ MACHINE_START(NEO1973_GTA02, "GTA02")
601 .init_irq = s3c24xx_init_irq, 601 .init_irq = s3c24xx_init_irq,
602 .init_machine = gta02_machine_init, 602 .init_machine = gta02_machine_init,
603 .timer = &s3c24xx_timer, 603 .timer = &s3c24xx_timer,
604 .restart = s3c2440_restart, 604 .restart = s3c244x_restart,
605MACHINE_END 605MACHINE_END
diff --git a/arch/arm/mach-s3c2440/mach-mini2440.c b/arch/arm/mach-s3c2440/mach-mini2440.c
index adbbb85bc4cd..5d66fb218a41 100644
--- a/arch/arm/mach-s3c2440/mach-mini2440.c
+++ b/arch/arm/mach-s3c2440/mach-mini2440.c
@@ -701,5 +701,5 @@ MACHINE_START(MINI2440, "MINI2440")
701 .init_machine = mini2440_init, 701 .init_machine = mini2440_init,
702 .init_irq = s3c24xx_init_irq, 702 .init_irq = s3c24xx_init_irq,
703 .timer = &s3c24xx_timer, 703 .timer = &s3c24xx_timer,
704 .restart = s3c2440_restart, 704 .restart = s3c244x_restart,
705MACHINE_END 705MACHINE_END
diff --git a/arch/arm/mach-s3c2440/mach-nexcoder.c b/arch/arm/mach-s3c2440/mach-nexcoder.c
index 40eaf844bc1f..5198e3e1c5be 100644
--- a/arch/arm/mach-s3c2440/mach-nexcoder.c
+++ b/arch/arm/mach-s3c2440/mach-nexcoder.c
@@ -158,5 +158,5 @@ MACHINE_START(NEXCODER_2440, "NexVision - Nexcoder 2440")
158 .init_machine = nexcoder_init, 158 .init_machine = nexcoder_init,
159 .init_irq = s3c24xx_init_irq, 159 .init_irq = s3c24xx_init_irq,
160 .timer = &s3c24xx_timer, 160 .timer = &s3c24xx_timer,
161 .restart = s3c2440_restart, 161 .restart = s3c244x_restart,
162MACHINE_END 162MACHINE_END
diff --git a/arch/arm/mach-s3c2440/mach-osiris.c b/arch/arm/mach-s3c2440/mach-osiris.c
index 4c480ef734f6..c5daeb612a88 100644
--- a/arch/arm/mach-s3c2440/mach-osiris.c
+++ b/arch/arm/mach-s3c2440/mach-osiris.c
@@ -436,5 +436,5 @@ MACHINE_START(OSIRIS, "Simtec-OSIRIS")
436 .init_irq = s3c24xx_init_irq, 436 .init_irq = s3c24xx_init_irq,
437 .init_machine = osiris_init, 437 .init_machine = osiris_init,
438 .timer = &s3c24xx_timer, 438 .timer = &s3c24xx_timer,
439 .restart = s3c2440_restart, 439 .restart = s3c244x_restart,
440MACHINE_END 440MACHINE_END
diff --git a/arch/arm/mach-s3c2440/mach-rx1950.c b/arch/arm/mach-s3c2440/mach-rx1950.c
index 80077f6472ee..6f68abf44fab 100644
--- a/arch/arm/mach-s3c2440/mach-rx1950.c
+++ b/arch/arm/mach-s3c2440/mach-rx1950.c
@@ -822,5 +822,5 @@ MACHINE_START(RX1950, "HP iPAQ RX1950")
822 .init_irq = s3c24xx_init_irq, 822 .init_irq = s3c24xx_init_irq,
823 .init_machine = rx1950_init_machine, 823 .init_machine = rx1950_init_machine,
824 .timer = &s3c24xx_timer, 824 .timer = &s3c24xx_timer,
825 .restart = s3c2440_restart, 825 .restart = s3c244x_restart,
826MACHINE_END 826MACHINE_END
diff --git a/arch/arm/mach-s3c2440/mach-rx3715.c b/arch/arm/mach-s3c2440/mach-rx3715.c
index 20103bafbd4b..56af35447598 100644
--- a/arch/arm/mach-s3c2440/mach-rx3715.c
+++ b/arch/arm/mach-s3c2440/mach-rx3715.c
@@ -213,5 +213,5 @@ MACHINE_START(RX3715, "IPAQ-RX3715")
213 .init_irq = rx3715_init_irq, 213 .init_irq = rx3715_init_irq,
214 .init_machine = rx3715_init_machine, 214 .init_machine = rx3715_init_machine,
215 .timer = &s3c24xx_timer, 215 .timer = &s3c24xx_timer,
216 .restart = s3c2440_restart, 216 .restart = s3c244x_restart,
217MACHINE_END 217MACHINE_END
diff --git a/arch/arm/mach-s3c2440/mach-smdk2440.c b/arch/arm/mach-s3c2440/mach-smdk2440.c
index 1deb60d12a60..83a1036d7dcb 100644
--- a/arch/arm/mach-s3c2440/mach-smdk2440.c
+++ b/arch/arm/mach-s3c2440/mach-smdk2440.c
@@ -183,5 +183,5 @@ MACHINE_START(S3C2440, "SMDK2440")
183 .map_io = smdk2440_map_io, 183 .map_io = smdk2440_map_io,
184 .init_machine = smdk2440_machine_init, 184 .init_machine = smdk2440_machine_init,
185 .timer = &s3c24xx_timer, 185 .timer = &s3c24xx_timer,
186 .restart = s3c2440_restart, 186 .restart = s3c244x_restart,
187MACHINE_END 187MACHINE_END
diff --git a/arch/arm/mach-s3c2440/s3c2440-cpufreq.c b/arch/arm/mach-s3c2440/s3c2440-cpufreq.c
index cf7596694efe..61776764d9f4 100644
--- a/arch/arm/mach-s3c2440/s3c2440-cpufreq.c
+++ b/arch/arm/mach-s3c2440/s3c2440-cpufreq.c
@@ -270,7 +270,8 @@ struct s3c_cpufreq_info s3c2440_cpufreq_info = {
270 .debug_io_show = s3c_cpufreq_debugfs_call(s3c2410_iotiming_debugfs), 270 .debug_io_show = s3c_cpufreq_debugfs_call(s3c2410_iotiming_debugfs),
271}; 271};
272 272
273static int s3c2440_cpufreq_add(struct device *dev) 273static int s3c2440_cpufreq_add(struct device *dev,
274 struct subsys_interface *sif)
274{ 275{
275 xtal = s3c_cpufreq_clk_get(NULL, "xtal"); 276 xtal = s3c_cpufreq_clk_get(NULL, "xtal");
276 hclk = s3c_cpufreq_clk_get(NULL, "hclk"); 277 hclk = s3c_cpufreq_clk_get(NULL, "hclk");
diff --git a/arch/arm/mach-s3c2440/s3c2440-pll-12000000.c b/arch/arm/mach-s3c2440/s3c2440-pll-12000000.c
index b5368ae8d7fe..551fb433be87 100644
--- a/arch/arm/mach-s3c2440/s3c2440-pll-12000000.c
+++ b/arch/arm/mach-s3c2440/s3c2440-pll-12000000.c
@@ -51,7 +51,7 @@ static struct cpufreq_frequency_table s3c2440_plls_12[] __initdata = {
51 { .frequency = 400000000, .index = PLLVAL(0x5c, 1, 1), }, /* FVco 800.000000 */ 51 { .frequency = 400000000, .index = PLLVAL(0x5c, 1, 1), }, /* FVco 800.000000 */
52}; 52};
53 53
54static int s3c2440_plls12_add(struct device *dev) 54static int s3c2440_plls12_add(struct device *dev, struct subsys_interface *sif)
55{ 55{
56 struct clk *xtal_clk; 56 struct clk *xtal_clk;
57 unsigned long xtal; 57 unsigned long xtal;
diff --git a/arch/arm/mach-s3c2440/s3c2440-pll-16934400.c b/arch/arm/mach-s3c2440/s3c2440-pll-16934400.c
index 42f2b5cd2399..3f15bcf64290 100644
--- a/arch/arm/mach-s3c2440/s3c2440-pll-16934400.c
+++ b/arch/arm/mach-s3c2440/s3c2440-pll-16934400.c
@@ -79,7 +79,8 @@ static struct cpufreq_frequency_table s3c2440_plls_169344[] __initdata = {
79 { .frequency = 402192000, .index = PLLVAL(87, 2, 1), }, /* FVco 804.384000 */ 79 { .frequency = 402192000, .index = PLLVAL(87, 2, 1), }, /* FVco 804.384000 */
80}; 80};
81 81
82static int s3c2440_plls169344_add(struct device *dev) 82static int s3c2440_plls169344_add(struct device *dev,
83 struct subsys_interface *sif)
83{ 84{
84 struct clk *xtal_clk; 85 struct clk *xtal_clk;
85 unsigned long xtal; 86 unsigned long xtal;
diff --git a/arch/arm/mach-s3c2440/s3c2440.c b/arch/arm/mach-s3c2440/s3c2440.c
index 517623a09fc5..2b3dddb49af7 100644
--- a/arch/arm/mach-s3c2440/s3c2440.c
+++ b/arch/arm/mach-s3c2440/s3c2440.c
@@ -35,7 +35,6 @@
35#include <plat/cpu.h> 35#include <plat/cpu.h>
36#include <plat/s3c244x.h> 36#include <plat/s3c244x.h>
37#include <plat/pm.h> 37#include <plat/pm.h>
38#include <plat/watchdog-reset.h>
39 38
40#include <plat/gpio-core.h> 39#include <plat/gpio-core.h>
41#include <plat/gpio-cfg.h> 40#include <plat/gpio-cfg.h>
@@ -74,15 +73,3 @@ void __init s3c2440_map_io(void)
74 s3c24xx_gpiocfg_default.set_pull = s3c24xx_gpio_setpull_1up; 73 s3c24xx_gpiocfg_default.set_pull = s3c24xx_gpio_setpull_1up;
75 s3c24xx_gpiocfg_default.get_pull = s3c24xx_gpio_getpull_1up; 74 s3c24xx_gpiocfg_default.get_pull = s3c24xx_gpio_getpull_1up;
76} 75}
77
78void s3c2440_restart(char mode, const char *cmd)
79{
80 if (mode == 's') {
81 soft_restart(0);
82 }
83
84 arch_wdt_reset();
85
86 /* we'll take a jump through zero as a poor second */
87 soft_restart(0);
88}
diff --git a/arch/arm/mach-s3c2440/s3c2442.c b/arch/arm/mach-s3c2440/s3c2442.c
index 8004e0497bf4..22cb7c94a8c8 100644
--- a/arch/arm/mach-s3c2440/s3c2442.c
+++ b/arch/arm/mach-s3c2440/s3c2442.c
@@ -122,7 +122,7 @@ static struct clk s3c2442_clk_cam_upll = {
122 }, 122 },
123}; 123};
124 124
125static int s3c2442_clk_add(struct device *dev) 125static int s3c2442_clk_add(struct device *dev, struct subsys_interface *sif)
126{ 126{
127 struct clk *clock_upll; 127 struct clk *clock_upll;
128 struct clk *clock_h; 128 struct clk *clock_h;
diff --git a/arch/arm/mach-s3c2440/s3c244x-clock.c b/arch/arm/mach-s3c2440/s3c244x-clock.c
index b3fdbdda3d5f..6d9b688c442b 100644
--- a/arch/arm/mach-s3c2440/s3c244x-clock.c
+++ b/arch/arm/mach-s3c2440/s3c244x-clock.c
@@ -72,7 +72,7 @@ static struct clk clk_arm = {
72 }, 72 },
73}; 73};
74 74
75static int s3c244x_clk_add(struct device *dev) 75static int s3c244x_clk_add(struct device *dev, struct subsys_interface *sif)
76{ 76{
77 unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN); 77 unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN);
78 unsigned long clkdivn; 78 unsigned long clkdivn;
diff --git a/arch/arm/mach-s3c2440/s3c244x-irq.c b/arch/arm/mach-s3c2440/s3c244x-irq.c
index 74d3dcf46a48..5fe8e58d3afd 100644
--- a/arch/arm/mach-s3c2440/s3c244x-irq.c
+++ b/arch/arm/mach-s3c2440/s3c244x-irq.c
@@ -91,7 +91,7 @@ static struct irq_chip s3c_irq_cam = {
91 .irq_ack = s3c_irq_cam_ack, 91 .irq_ack = s3c_irq_cam_ack,
92}; 92};
93 93
94static int s3c244x_irq_add(struct device *dev) 94static int s3c244x_irq_add(struct device *dev, struct subsys_interface *sif)
95{ 95{
96 unsigned int irqno; 96 unsigned int irqno;
97 97
diff --git a/arch/arm/mach-s3c2440/s3c244x.c b/arch/arm/mach-s3c2440/s3c244x.c
index 36bc60f61d0a..d15852f642b7 100644
--- a/arch/arm/mach-s3c2440/s3c244x.c
+++ b/arch/arm/mach-s3c2440/s3c244x.c
@@ -46,6 +46,7 @@
46#include <plat/pm.h> 46#include <plat/pm.h>
47#include <plat/pll.h> 47#include <plat/pll.h>
48#include <plat/nand-core.h> 48#include <plat/nand-core.h>
49#include <plat/watchdog-reset.h>
49 50
50static struct map_desc s3c244x_iodesc[] __initdata = { 51static struct map_desc s3c244x_iodesc[] __initdata = {
51 IODESC_ENT(CLKPWR), 52 IODESC_ENT(CLKPWR),
@@ -196,3 +197,14 @@ struct syscore_ops s3c244x_pm_syscore_ops = {
196 .suspend = s3c244x_suspend, 197 .suspend = s3c244x_suspend,
197 .resume = s3c244x_resume, 198 .resume = s3c244x_resume,
198}; 199};
200
201void s3c244x_restart(char mode, const char *cmd)
202{
203 if (mode == 's')
204 soft_restart(0);
205
206 arch_wdt_reset();
207
208 /* we'll take a jump through zero as a poor second */
209 soft_restart(0);
210}
diff --git a/arch/arm/mach-s3c2443/dma.c b/arch/arm/mach-s3c2443/dma.c
index de6b4a23c9ed..14224517e621 100644
--- a/arch/arm/mach-s3c2443/dma.c
+++ b/arch/arm/mach-s3c2443/dma.c
@@ -135,7 +135,8 @@ static struct s3c24xx_dma_selection __initdata s3c2443_dma_sel = {
135 .map_size = ARRAY_SIZE(s3c2443_dma_mappings), 135 .map_size = ARRAY_SIZE(s3c2443_dma_mappings),
136}; 136};
137 137
138static int __init s3c2443_dma_add(struct device *dev) 138static int __init s3c2443_dma_add(struct device *dev,
139 struct subsys_interface *sif)
139{ 140{
140 s3c24xx_dma_init(6, IRQ_S3C2443_DMA0, 0x100); 141 s3c24xx_dma_init(6, IRQ_S3C2443_DMA0, 0x100);
141 return s3c24xx_dma_init_map(&s3c2443_dma_sel); 142 return s3c24xx_dma_init_map(&s3c2443_dma_sel);
diff --git a/arch/arm/mach-s3c2443/irq.c b/arch/arm/mach-s3c2443/irq.c
index 35e4ff24fb43..ac2829f56d12 100644
--- a/arch/arm/mach-s3c2443/irq.c
+++ b/arch/arm/mach-s3c2443/irq.c
@@ -241,7 +241,8 @@ static int __init s3c2443_add_sub(unsigned int base,
241 return 0; 241 return 0;
242} 242}
243 243
244static int __init s3c2443_irq_add(struct device *dev) 244static int __init s3c2443_irq_add(struct device *dev,
245 struct subsys_interface *sif)
245{ 246{
246 printk("S3C2443: IRQ Support\n"); 247 printk("S3C2443: IRQ Support\n");
247 248
diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c
index 31bb27dc4aeb..aebbcc291b4e 100644
--- a/arch/arm/mach-s3c64xx/clock.c
+++ b/arch/arm/mach-s3c64xx/clock.c
@@ -138,6 +138,11 @@ static struct clk init_clocks_off[] = {
138 .ctrlbit = S3C_CLKCON_PCLK_TSADC, 138 .ctrlbit = S3C_CLKCON_PCLK_TSADC,
139 }, { 139 }, {
140 .name = "i2c", 140 .name = "i2c",
141#ifdef CONFIG_S3C_DEV_I2C1
142 .devname = "s3c2440-i2c.0",
143#else
144 .devname = "s3c2440-i2c",
145#endif
141 .parent = &clk_p, 146 .parent = &clk_p,
142 .enable = s3c64xx_pclk_ctrl, 147 .enable = s3c64xx_pclk_ctrl,
143 .ctrlbit = S3C_CLKCON_PCLK_IIC, 148 .ctrlbit = S3C_CLKCON_PCLK_IIC,
diff --git a/arch/arm/mach-s3c64xx/common.c b/arch/arm/mach-s3c64xx/common.c
index 4a7394d4bd9e..bee7dcd4df7c 100644
--- a/arch/arm/mach-s3c64xx/common.c
+++ b/arch/arm/mach-s3c64xx/common.c
@@ -49,7 +49,7 @@
49 49
50/* uart registration process */ 50/* uart registration process */
51 51
52void __init s3c64xx_init_uarts(struct s3c2410_uartcfg *cfg, int no) 52static void __init s3c64xx_init_uarts(struct s3c2410_uartcfg *cfg, int no)
53{ 53{
54 s3c24xx_init_uartdevs("s3c6400-uart", s3c64xx_uart_resources, cfg, no); 54 s3c24xx_init_uartdevs("s3c6400-uart", s3c64xx_uart_resources, cfg, no);
55} 55}
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410-module.c b/arch/arm/mach-s3c64xx/mach-crag6410-module.c
index cd3c97e2ee75..32a30f38ba0c 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410-module.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410-module.c
@@ -102,6 +102,7 @@ static struct wm8962_pdata wm8962_pdata __initdata = {
102 0x8000 | WM8962_GPIO_FN_DMICDAT, 102 0x8000 | WM8962_GPIO_FN_DMICDAT,
103 WM8962_GPIO_FN_IRQ, /* Open drain mode */ 103 WM8962_GPIO_FN_IRQ, /* Open drain mode */
104 }, 104 },
105 .in4_dc_measure = true,
105}; 106};
106 107
107static struct wm9081_pdata wm9081_pdata __initdata = { 108static struct wm9081_pdata wm9081_pdata __initdata = {
diff --git a/arch/arm/mach-s5p64x0/pm.c b/arch/arm/mach-s5p64x0/pm.c
index 23f9b22439c9..9cba18bfe47b 100644
--- a/arch/arm/mach-s5p64x0/pm.c
+++ b/arch/arm/mach-s5p64x0/pm.c
@@ -160,7 +160,7 @@ static void s5p64x0_pm_prepare(void)
160 160
161} 161}
162 162
163static int s5p64x0_pm_add(struct device *dev) 163static int s5p64x0_pm_add(struct device *dev, struct subsys_interface *sif)
164{ 164{
165 pm_cpu_prep = s5p64x0_pm_prepare; 165 pm_cpu_prep = s5p64x0_pm_prepare;
166 pm_cpu_sleep = s5p64x0_cpu_suspend; 166 pm_cpu_sleep = s5p64x0_cpu_suspend;
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
index c78dfddd77fd..b9ec0c35379f 100644
--- a/arch/arm/mach-s5pv210/clock.c
+++ b/arch/arm/mach-s5pv210/clock.c
@@ -175,7 +175,7 @@ static int s5pv210_clk_mask1_ctrl(struct clk *clk, int enable)
175 return s5p_gatectrl(S5P_CLK_SRC_MASK1, clk, enable); 175 return s5p_gatectrl(S5P_CLK_SRC_MASK1, clk, enable);
176} 176}
177 177
178static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable) 178static int s5pv210_clk_hdmiphy_ctrl(struct clk *clk, int enable)
179{ 179{
180 return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable); 180 return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
181} 181}
@@ -372,7 +372,7 @@ static struct clk init_clocks_off[] = {
372 }, { 372 }, {
373 .name = "hdmiphy", 373 .name = "hdmiphy",
374 .devname = "s5pv210-hdmi", 374 .devname = "s5pv210-hdmi",
375 .enable = exynos4_clk_hdmiphy_ctrl, 375 .enable = s5pv210_clk_hdmiphy_ctrl,
376 .ctrlbit = (1 << 0), 376 .ctrlbit = (1 << 0),
377 }, { 377 }, {
378 .name = "dacphy", 378 .name = "dacphy",
diff --git a/arch/arm/mach-s5pv210/pm.c b/arch/arm/mach-s5pv210/pm.c
index 677c71c41e50..736bfb103cbc 100644
--- a/arch/arm/mach-s5pv210/pm.c
+++ b/arch/arm/mach-s5pv210/pm.c
@@ -133,7 +133,7 @@ static void s5pv210_pm_prepare(void)
133 s3c_pm_do_save(s5pv210_core_save, ARRAY_SIZE(s5pv210_core_save)); 133 s3c_pm_do_save(s5pv210_core_save, ARRAY_SIZE(s5pv210_core_save));
134} 134}
135 135
136static int s5pv210_pm_add(struct device *dev) 136static int s5pv210_pm_add(struct device *dev, struct subsys_interface *sif)
137{ 137{
138 pm_cpu_prep = s5pv210_pm_prepare; 138 pm_cpu_prep = s5pv210_pm_prepare;
139 pm_cpu_sleep = s5pv210_cpu_suspend; 139 pm_cpu_sleep = s5pv210_cpu_suspend;
diff --git a/arch/arm/mach-sa1100/assabet.c b/arch/arm/mach-sa1100/assabet.c
index ebafe8aa8956..0c4b76ab4d8e 100644
--- a/arch/arm/mach-sa1100/assabet.c
+++ b/arch/arm/mach-sa1100/assabet.c
@@ -202,7 +202,6 @@ static struct irda_platform_data assabet_irda_data = {
202static struct mcp_plat_data assabet_mcp_data = { 202static struct mcp_plat_data assabet_mcp_data = {
203 .mccr0 = MCCR0_ADM, 203 .mccr0 = MCCR0_ADM,
204 .sclk_rate = 11981000, 204 .sclk_rate = 11981000,
205 .codec = "ucb1x00",
206}; 205};
207 206
208static void __init assabet_init(void) 207static void __init assabet_init(void)
@@ -253,17 +252,6 @@ static void __init assabet_init(void)
253 sa11x0_register_mtd(&assabet_flash_data, assabet_flash_resources, 252 sa11x0_register_mtd(&assabet_flash_data, assabet_flash_resources,
254 ARRAY_SIZE(assabet_flash_resources)); 253 ARRAY_SIZE(assabet_flash_resources));
255 sa11x0_register_irda(&assabet_irda_data); 254 sa11x0_register_irda(&assabet_irda_data);
256
257 /*
258 * Setup the PPC unit correctly.
259 */
260 PPDR &= ~PPC_RXD4;
261 PPDR |= PPC_TXD4 | PPC_SCLK | PPC_SFRM;
262 PSDR |= PPC_RXD4;
263 PSDR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
264 PPSR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
265
266 ASSABET_BCR_set(ASSABET_BCR_CODEC_RST);
267 sa11x0_register_mcp(&assabet_mcp_data); 255 sa11x0_register_mcp(&assabet_mcp_data);
268} 256}
269 257
diff --git a/arch/arm/mach-sa1100/cerf.c b/arch/arm/mach-sa1100/cerf.c
index d12d0f48b1dc..11bb6d0b9be3 100644
--- a/arch/arm/mach-sa1100/cerf.c
+++ b/arch/arm/mach-sa1100/cerf.c
@@ -124,23 +124,12 @@ static void __init cerf_map_io(void)
124static struct mcp_plat_data cerf_mcp_data = { 124static struct mcp_plat_data cerf_mcp_data = {
125 .mccr0 = MCCR0_ADM, 125 .mccr0 = MCCR0_ADM,
126 .sclk_rate = 11981000, 126 .sclk_rate = 11981000,
127 .codec = "ucb1x00",
128}; 127};
129 128
130static void __init cerf_init(void) 129static void __init cerf_init(void)
131{ 130{
132 platform_add_devices(cerf_devices, ARRAY_SIZE(cerf_devices)); 131 platform_add_devices(cerf_devices, ARRAY_SIZE(cerf_devices));
133 sa11x0_register_mtd(&cerf_flash_data, &cerf_flash_resource, 1); 132 sa11x0_register_mtd(&cerf_flash_data, &cerf_flash_resource, 1);
134
135 /*
136 * Setup the PPC unit correctly.
137 */
138 PPDR &= ~PPC_RXD4;
139 PPDR |= PPC_TXD4 | PPC_SCLK | PPC_SFRM;
140 PSDR |= PPC_RXD4;
141 PSDR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
142 PPSR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
143
144 sa11x0_register_mcp(&cerf_mcp_data); 133 sa11x0_register_mcp(&cerf_mcp_data);
145} 134}
146 135
diff --git a/arch/arm/mach-sa1100/clock.c b/arch/arm/mach-sa1100/clock.c
index d6df9f6c9f7e..dab3c6347a8f 100644
--- a/arch/arm/mach-sa1100/clock.c
+++ b/arch/arm/mach-sa1100/clock.c
@@ -11,39 +11,17 @@
11#include <linux/clk.h> 11#include <linux/clk.h>
12#include <linux/spinlock.h> 12#include <linux/spinlock.h>
13#include <linux/mutex.h> 13#include <linux/mutex.h>
14#include <linux/io.h>
15#include <linux/clkdev.h>
16 14
17#include <mach/hardware.h> 15#include <mach/hardware.h>
18 16
19struct clkops { 17/*
20 void (*enable)(struct clk *); 18 * Very simple clock implementation - we only have one clock to deal with.
21 void (*disable)(struct clk *); 19 */
22 unsigned long (*getrate)(struct clk *);
23};
24
25struct clk { 20struct clk {
26 const struct clkops *ops;
27 unsigned long rate;
28 unsigned int enabled; 21 unsigned int enabled;
29}; 22};
30 23
31#define INIT_CLKREG(_clk, _devname, _conname) \ 24static void clk_gpio27_enable(void)
32 { \
33 .clk = _clk, \
34 .dev_id = _devname, \
35 .con_id = _conname, \
36 }
37
38#define DEFINE_CLK(_name, _ops, _rate) \
39struct clk clk_##_name = { \
40 .ops = _ops, \
41 .rate = _rate, \
42 }
43
44static DEFINE_SPINLOCK(clocks_lock);
45
46static void clk_gpio27_enable(struct clk *clk)
47{ 25{
48 /* 26 /*
49 * First, set up the 3.6864MHz clock on GPIO 27 for the SA-1111: 27 * First, set up the 3.6864MHz clock on GPIO 27 for the SA-1111:
@@ -54,22 +32,38 @@ static void clk_gpio27_enable(struct clk *clk)
54 TUCR = TUCR_3_6864MHz; 32 TUCR = TUCR_3_6864MHz;
55} 33}
56 34
57static void clk_gpio27_disable(struct clk *clk) 35static void clk_gpio27_disable(void)
58{ 36{
59 TUCR = 0; 37 TUCR = 0;
60 GPDR &= ~GPIO_32_768kHz; 38 GPDR &= ~GPIO_32_768kHz;
61 GAFR &= ~GPIO_32_768kHz; 39 GAFR &= ~GPIO_32_768kHz;
62} 40}
63 41
42static struct clk clk_gpio27;
43
44static DEFINE_SPINLOCK(clocks_lock);
45
46struct clk *clk_get(struct device *dev, const char *id)
47{
48 const char *devname = dev_name(dev);
49
50 return strcmp(devname, "sa1111.0") ? ERR_PTR(-ENOENT) : &clk_gpio27;
51}
52EXPORT_SYMBOL(clk_get);
53
54void clk_put(struct clk *clk)
55{
56}
57EXPORT_SYMBOL(clk_put);
58
64int clk_enable(struct clk *clk) 59int clk_enable(struct clk *clk)
65{ 60{
66 unsigned long flags; 61 unsigned long flags;
67 62
68 spin_lock_irqsave(&clocks_lock, flags); 63 spin_lock_irqsave(&clocks_lock, flags);
69 if (clk->enabled++ == 0) 64 if (clk->enabled++ == 0)
70 clk->ops->enable(clk); 65 clk_gpio27_enable();
71 spin_unlock_irqrestore(&clocks_lock, flags); 66 spin_unlock_irqrestore(&clocks_lock, flags);
72
73 return 0; 67 return 0;
74} 68}
75EXPORT_SYMBOL(clk_enable); 69EXPORT_SYMBOL(clk_enable);
@@ -82,48 +76,13 @@ void clk_disable(struct clk *clk)
82 76
83 spin_lock_irqsave(&clocks_lock, flags); 77 spin_lock_irqsave(&clocks_lock, flags);
84 if (--clk->enabled == 0) 78 if (--clk->enabled == 0)
85 clk->ops->disable(clk); 79 clk_gpio27_disable();
86 spin_unlock_irqrestore(&clocks_lock, flags); 80 spin_unlock_irqrestore(&clocks_lock, flags);
87} 81}
88EXPORT_SYMBOL(clk_disable); 82EXPORT_SYMBOL(clk_disable);
89 83
90unsigned long clk_get_rate(struct clk *clk) 84unsigned long clk_get_rate(struct clk *clk)
91{ 85{
92 unsigned long rate; 86 return 3686400;
93
94 rate = clk->rate;
95 if (clk->ops->getrate)
96 rate = clk->ops->getrate(clk);
97
98 return rate;
99} 87}
100EXPORT_SYMBOL(clk_get_rate); 88EXPORT_SYMBOL(clk_get_rate);
101
102const struct clkops clk_gpio27_ops = {
103 .enable = clk_gpio27_enable,
104 .disable = clk_gpio27_disable,
105};
106
107static void clk_dummy_enable(struct clk *clk) { }
108static void clk_dummy_disable(struct clk *clk) { }
109
110const struct clkops clk_dummy_ops = {
111 .enable = clk_dummy_enable,
112 .disable = clk_dummy_disable,
113};
114
115static DEFINE_CLK(gpio27, &clk_gpio27_ops, 3686400);
116static DEFINE_CLK(dummy, &clk_dummy_ops, 0);
117
118static struct clk_lookup sa11xx_clkregs[] = {
119 INIT_CLKREG(&clk_gpio27, "sa1111.0", NULL),
120 INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
121};
122
123static int __init sa11xx_clk_init(void)
124{
125 clkdev_add_table(sa11xx_clkregs, ARRAY_SIZE(sa11xx_clkregs));
126 return 0;
127}
128
129postcore_initcall(sa11xx_clk_init);
diff --git a/arch/arm/mach-sa1100/collie.c b/arch/arm/mach-sa1100/collie.c
index c483912d08af..fd5652118ed1 100644
--- a/arch/arm/mach-sa1100/collie.c
+++ b/arch/arm/mach-sa1100/collie.c
@@ -27,7 +27,6 @@
27#include <linux/timer.h> 27#include <linux/timer.h>
28#include <linux/gpio.h> 28#include <linux/gpio.h>
29#include <linux/pda_power.h> 29#include <linux/pda_power.h>
30#include <linux/mfd/ucb1x00.h>
31 30
32#include <mach/hardware.h> 31#include <mach/hardware.h>
33#include <asm/mach-types.h> 32#include <asm/mach-types.h>
@@ -86,15 +85,10 @@ static struct scoop_pcmcia_config collie_pcmcia_config = {
86 .num_devs = 1, 85 .num_devs = 1,
87}; 86};
88 87
89static struct ucb1x00_plat_data collie_ucb1x00_data = {
90 .gpio_base = COLLIE_TC35143_GPIO_BASE,
91};
92
93static struct mcp_plat_data collie_mcp_data = { 88static struct mcp_plat_data collie_mcp_data = {
94 .mccr0 = MCCR0_ADM | MCCR0_ExtClk, 89 .mccr0 = MCCR0_ADM | MCCR0_ExtClk,
95 .sclk_rate = 9216000, 90 .sclk_rate = 9216000,
96 .codec = "ucb1x00", 91 .gpio_base = COLLIE_TC35143_GPIO_BASE,
97 .codec_pdata = &collie_ucb1x00_data,
98}; 92};
99 93
100/* 94/*
@@ -144,8 +138,6 @@ static struct pda_power_pdata collie_power_data = {
144static struct resource collie_power_resource[] = { 138static struct resource collie_power_resource[] = {
145 { 139 {
146 .name = "ac", 140 .name = "ac",
147 .start = gpio_to_irq(COLLIE_GPIO_AC_IN),
148 .end = gpio_to_irq(COLLIE_GPIO_AC_IN),
149 .flags = IORESOURCE_IRQ | 141 .flags = IORESOURCE_IRQ |
150 IORESOURCE_IRQ_HIGHEDGE | 142 IORESOURCE_IRQ_HIGHEDGE |
151 IORESOURCE_IRQ_LOWEDGE, 143 IORESOURCE_IRQ_LOWEDGE,
@@ -347,7 +339,8 @@ static void __init collie_init(void)
347 339
348 GPSR |= _COLLIE_GPIO_UCB1x00_RESET; 340 GPSR |= _COLLIE_GPIO_UCB1x00_RESET;
349 341
350 342 collie_power_resource[0].start = gpio_to_irq(COLLIE_GPIO_AC_IN);
343 collie_power_resource[0].end = gpio_to_irq(COLLIE_GPIO_AC_IN);
351 platform_scoop_config = &collie_pcmcia_config; 344 platform_scoop_config = &collie_pcmcia_config;
352 345
353 ret = platform_add_devices(devices, ARRAY_SIZE(devices)); 346 ret = platform_add_devices(devices, ARRAY_SIZE(devices));
@@ -357,16 +350,6 @@ static void __init collie_init(void)
357 350
358 sa11x0_register_mtd(&collie_flash_data, collie_flash_resources, 351 sa11x0_register_mtd(&collie_flash_data, collie_flash_resources,
359 ARRAY_SIZE(collie_flash_resources)); 352 ARRAY_SIZE(collie_flash_resources));
360
361 /*
362 * Setup the PPC unit correctly.
363 */
364 PPDR &= ~PPC_RXD4;
365 PPDR |= PPC_TXD4 | PPC_SCLK | PPC_SFRM;
366 PSDR |= PPC_RXD4;
367 PSDR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
368 PPSR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
369
370 sa11x0_register_mcp(&collie_mcp_data); 353 sa11x0_register_mcp(&collie_mcp_data);
371 354
372 sharpsl_save_param(); 355 sharpsl_save_param();
diff --git a/arch/arm/mach-sa1100/cpu-sa1100.c b/arch/arm/mach-sa1100/cpu-sa1100.c
index aaa8acf76b7b..19b2053f5af4 100644
--- a/arch/arm/mach-sa1100/cpu-sa1100.c
+++ b/arch/arm/mach-sa1100/cpu-sa1100.c
@@ -228,7 +228,7 @@ static int __init sa1100_cpu_init(struct cpufreq_policy *policy)
228 return 0; 228 return 0;
229} 229}
230 230
231static struct cpufreq_driver sa1100_driver = { 231static struct cpufreq_driver sa1100_driver __refdata = {
232 .flags = CPUFREQ_STICKY, 232 .flags = CPUFREQ_STICKY,
233 .verify = sa11x0_verify_speed, 233 .verify = sa11x0_verify_speed,
234 .target = sa1100_target, 234 .target = sa1100_target,
diff --git a/arch/arm/mach-sa1100/generic.c b/arch/arm/mach-sa1100/generic.c
index e3a28ca2a7b7..bb10ee2cb89f 100644
--- a/arch/arm/mach-sa1100/generic.c
+++ b/arch/arm/mach-sa1100/generic.c
@@ -217,15 +217,10 @@ static struct platform_device sa11x0uart3_device = {
217static struct resource sa11x0mcp_resources[] = { 217static struct resource sa11x0mcp_resources[] = {
218 [0] = { 218 [0] = {
219 .start = __PREG(Ser4MCCR0), 219 .start = __PREG(Ser4MCCR0),
220 .end = __PREG(Ser4MCCR0) + 0x1C - 1, 220 .end = __PREG(Ser4MCCR0) + 0xffff,
221 .flags = IORESOURCE_MEM, 221 .flags = IORESOURCE_MEM,
222 }, 222 },
223 [1] = { 223 [1] = {
224 .start = __PREG(Ser4MCCR1),
225 .end = __PREG(Ser4MCCR1) + 0x4 - 1,
226 .flags = IORESOURCE_MEM,
227 },
228 [2] = {
229 .start = IRQ_Ser4MCP, 224 .start = IRQ_Ser4MCP,
230 .end = IRQ_Ser4MCP, 225 .end = IRQ_Ser4MCP,
231 .flags = IORESOURCE_IRQ, 226 .flags = IORESOURCE_IRQ,
@@ -350,29 +345,9 @@ void sa11x0_register_irda(struct irda_platform_data *irda)
350 sa11x0_register_device(&sa11x0ir_device, irda); 345 sa11x0_register_device(&sa11x0ir_device, irda);
351} 346}
352 347
353static struct resource sa11x0rtc_resources[] = {
354 [0] = {
355 .start = 0x90010000,
356 .end = 0x900100ff,
357 .flags = IORESOURCE_MEM,
358 },
359 [1] = {
360 .start = IRQ_RTC1Hz,
361 .end = IRQ_RTC1Hz,
362 .flags = IORESOURCE_IRQ,
363 },
364 [2] = {
365 .start = IRQ_RTCAlrm,
366 .end = IRQ_RTCAlrm,
367 .flags = IORESOURCE_IRQ,
368 },
369};
370
371static struct platform_device sa11x0rtc_device = { 348static struct platform_device sa11x0rtc_device = {
372 .name = "sa1100-rtc", 349 .name = "sa1100-rtc",
373 .id = -1, 350 .id = -1,
374 .resource = sa11x0rtc_resources,
375 .num_resources = ARRAY_SIZE(sa11x0rtc_resources),
376}; 351};
377 352
378static struct platform_device *sa11x0_devices[] __initdata = { 353static struct platform_device *sa11x0_devices[] __initdata = {
diff --git a/arch/arm/mach-sa1100/include/mach/mcp.h b/arch/arm/mach-sa1100/include/mach/mcp.h
index 586cec898b35..ed1a331508a7 100644
--- a/arch/arm/mach-sa1100/include/mach/mcp.h
+++ b/arch/arm/mach-sa1100/include/mach/mcp.h
@@ -17,8 +17,6 @@ struct mcp_plat_data {
17 u32 mccr1; 17 u32 mccr1;
18 unsigned int sclk_rate; 18 unsigned int sclk_rate;
19 int gpio_base; 19 int gpio_base;
20 const char *codec;
21 void *codec_pdata;
22}; 20};
23 21
24#endif 22#endif
diff --git a/arch/arm/mach-sa1100/jornada720_ssp.c b/arch/arm/mach-sa1100/jornada720_ssp.c
index f50b00bd18a0..b412fc09c80c 100644
--- a/arch/arm/mach-sa1100/jornada720_ssp.c
+++ b/arch/arm/mach-sa1100/jornada720_ssp.c
@@ -198,3 +198,5 @@ static int __init jornada_ssp_init(void)
198{ 198{
199 return platform_driver_register(&jornadassp_driver); 199 return platform_driver_register(&jornadassp_driver);
200} 200}
201
202module_init(jornada_ssp_init);
diff --git a/arch/arm/mach-sa1100/lart.c b/arch/arm/mach-sa1100/lart.c
index d117ceab6215..af4e2761f3db 100644
--- a/arch/arm/mach-sa1100/lart.c
+++ b/arch/arm/mach-sa1100/lart.c
@@ -24,20 +24,10 @@
24static struct mcp_plat_data lart_mcp_data = { 24static struct mcp_plat_data lart_mcp_data = {
25 .mccr0 = MCCR0_ADM, 25 .mccr0 = MCCR0_ADM,
26 .sclk_rate = 11981000, 26 .sclk_rate = 11981000,
27 .codec = "ucb1x00",
28}; 27};
29 28
30static void __init lart_init(void) 29static void __init lart_init(void)
31{ 30{
32 /*
33 * Setup the PPC unit correctly.
34 */
35 PPDR &= ~PPC_RXD4;
36 PPDR |= PPC_TXD4 | PPC_SCLK | PPC_SFRM;
37 PSDR |= PPC_RXD4;
38 PSDR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
39 PPSR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
40
41 sa11x0_register_mcp(&lart_mcp_data); 31 sa11x0_register_mcp(&lart_mcp_data);
42} 32}
43 33
diff --git a/arch/arm/mach-sa1100/shannon.c b/arch/arm/mach-sa1100/shannon.c
index 748d34435b3f..318b2b766a0b 100644
--- a/arch/arm/mach-sa1100/shannon.c
+++ b/arch/arm/mach-sa1100/shannon.c
@@ -55,22 +55,11 @@ static struct resource shannon_flash_resource = {
55static struct mcp_plat_data shannon_mcp_data = { 55static struct mcp_plat_data shannon_mcp_data = {
56 .mccr0 = MCCR0_ADM, 56 .mccr0 = MCCR0_ADM,
57 .sclk_rate = 11981000, 57 .sclk_rate = 11981000,
58 .codec = "ucb1x00",
59}; 58};
60 59
61static void __init shannon_init(void) 60static void __init shannon_init(void)
62{ 61{
63 sa11x0_register_mtd(&shannon_flash_data, &shannon_flash_resource, 1); 62 sa11x0_register_mtd(&shannon_flash_data, &shannon_flash_resource, 1);
64
65 /*
66 * Setup the PPC unit correctly.
67 */
68 PPDR &= ~PPC_RXD4;
69 PPDR |= PPC_TXD4 | PPC_SCLK | PPC_SFRM;
70 PSDR |= PPC_RXD4;
71 PSDR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
72 PPSR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
73
74 sa11x0_register_mcp(&shannon_mcp_data); 63 sa11x0_register_mcp(&shannon_mcp_data);
75} 64}
76 65
diff --git a/arch/arm/mach-sa1100/simpad.c b/arch/arm/mach-sa1100/simpad.c
index 458ececefa58..e17c04d6e324 100644
--- a/arch/arm/mach-sa1100/simpad.c
+++ b/arch/arm/mach-sa1100/simpad.c
@@ -14,7 +14,6 @@
14#include <linux/mtd/partitions.h> 14#include <linux/mtd/partitions.h>
15#include <linux/io.h> 15#include <linux/io.h>
16#include <linux/gpio.h> 16#include <linux/gpio.h>
17#include <linux/mfd/ucb1x00.h>
18 17
19#include <asm/irq.h> 18#include <asm/irq.h>
20#include <mach/hardware.h> 19#include <mach/hardware.h>
@@ -188,15 +187,10 @@ static struct resource simpad_flash_resources [] = {
188 } 187 }
189}; 188};
190 189
191static struct ucb1x00_plat_data simpad_ucb1x00_data = {
192 .gpio_base = SIMPAD_UCB1X00_GPIO_BASE,
193};
194
195static struct mcp_plat_data simpad_mcp_data = { 190static struct mcp_plat_data simpad_mcp_data = {
196 .mccr0 = MCCR0_ADM, 191 .mccr0 = MCCR0_ADM,
197 .sclk_rate = 11981000, 192 .sclk_rate = 11981000,
198 .codec = "ucb1300", 193 .gpio_base = SIMPAD_UCB1X00_GPIO_BASE,
199 .codec_pdata = &simpad_ucb1x00_data,
200}; 194};
201 195
202 196
@@ -384,16 +378,6 @@ static int __init simpad_init(void)
384 378
385 sa11x0_register_mtd(&simpad_flash_data, simpad_flash_resources, 379 sa11x0_register_mtd(&simpad_flash_data, simpad_flash_resources,
386 ARRAY_SIZE(simpad_flash_resources)); 380 ARRAY_SIZE(simpad_flash_resources));
387
388 /*
389 * Setup the PPC unit correctly.
390 */
391 PPDR &= ~PPC_RXD4;
392 PPDR |= PPC_TXD4 | PPC_SCLK | PPC_SFRM;
393 PSDR |= PPC_RXD4;
394 PSDR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
395 PPSR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
396
397 sa11x0_register_mcp(&simpad_mcp_data); 381 sa11x0_register_mcp(&simpad_mcp_data);
398 382
399 ret = platform_add_devices(devices, ARRAY_SIZE(devices)); 383 ret = platform_add_devices(devices, ARRAY_SIZE(devices));
diff --git a/arch/arm/mach-shmobile/board-ag5evm.c b/arch/arm/mach-shmobile/board-ag5evm.c
index eff8a96c75ee..12c431f3443f 100644
--- a/arch/arm/mach-shmobile/board-ag5evm.c
+++ b/arch/arm/mach-shmobile/board-ag5evm.c
@@ -30,6 +30,7 @@
30#include <linux/serial_sci.h> 30#include <linux/serial_sci.h>
31#include <linux/smsc911x.h> 31#include <linux/smsc911x.h>
32#include <linux/gpio.h> 32#include <linux/gpio.h>
33#include <linux/videodev2.h>
33#include <linux/input.h> 34#include <linux/input.h>
34#include <linux/input/sh_keysc.h> 35#include <linux/input/sh_keysc.h>
35#include <linux/mmc/host.h> 36#include <linux/mmc/host.h>
@@ -37,7 +38,7 @@
37#include <linux/mmc/sh_mobile_sdhi.h> 38#include <linux/mmc/sh_mobile_sdhi.h>
38#include <linux/mfd/tmio.h> 39#include <linux/mfd/tmio.h>
39#include <linux/sh_clk.h> 40#include <linux/sh_clk.h>
40#include <linux/dma-mapping.h> 41#include <linux/videodev2.h>
41#include <video/sh_mobile_lcdc.h> 42#include <video/sh_mobile_lcdc.h>
42#include <video/sh_mipi_dsi.h> 43#include <video/sh_mipi_dsi.h>
43#include <sound/sh_fsi.h> 44#include <sound/sh_fsi.h>
@@ -159,19 +160,12 @@ static struct resource sh_mmcif_resources[] = {
159 }, 160 },
160}; 161};
161 162
162static struct sh_mmcif_dma sh_mmcif_dma = {
163 .chan_priv_rx = {
164 .slave_id = SHDMA_SLAVE_MMCIF_RX,
165 },
166 .chan_priv_tx = {
167 .slave_id = SHDMA_SLAVE_MMCIF_TX,
168 },
169};
170static struct sh_mmcif_plat_data sh_mmcif_platdata = { 163static struct sh_mmcif_plat_data sh_mmcif_platdata = {
171 .sup_pclk = 0, 164 .sup_pclk = 0,
172 .ocr = MMC_VDD_165_195, 165 .ocr = MMC_VDD_165_195,
173 .caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE, 166 .caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE,
174 .dma = &sh_mmcif_dma, 167 .slave_id_tx = SHDMA_SLAVE_MMCIF_TX,
168 .slave_id_rx = SHDMA_SLAVE_MMCIF_RX,
175}; 169};
176 170
177static struct platform_device mmc_device = { 171static struct platform_device mmc_device = {
@@ -236,16 +230,6 @@ static void lcd_backlight_reset(void)
236 gpio_set_value(GPIO_PORT235, 1); 230 gpio_set_value(GPIO_PORT235, 1);
237} 231}
238 232
239static void lcd_on(void *board_data, struct fb_info *info)
240{
241 lcd_backlight_on();
242}
243
244static void lcd_off(void *board_data)
245{
246 lcd_backlight_reset();
247}
248
249/* LCDC0 */ 233/* LCDC0 */
250static const struct fb_videomode lcdc0_modes[] = { 234static const struct fb_videomode lcdc0_modes[] = {
251 { 235 {
@@ -269,14 +253,14 @@ static struct sh_mobile_lcdc_info lcdc0_info = {
269 .interface_type = RGB24, 253 .interface_type = RGB24,
270 .clock_divider = 1, 254 .clock_divider = 1,
271 .flags = LCDC_FLAGS_DWPOL, 255 .flags = LCDC_FLAGS_DWPOL,
272 .lcd_size_cfg.width = 44,
273 .lcd_size_cfg.height = 79,
274 .fourcc = V4L2_PIX_FMT_RGB565, 256 .fourcc = V4L2_PIX_FMT_RGB565,
275 .lcd_cfg = lcdc0_modes, 257 .lcd_modes = lcdc0_modes,
276 .num_cfg = ARRAY_SIZE(lcdc0_modes), 258 .num_modes = ARRAY_SIZE(lcdc0_modes),
277 .board_cfg = { 259 .panel_cfg = {
278 .display_on = lcd_on, 260 .width = 44,
279 .display_off = lcd_off, 261 .height = 79,
262 .display_on = lcd_backlight_on,
263 .display_off = lcd_backlight_reset,
280 }, 264 },
281 } 265 }
282}; 266};
@@ -321,12 +305,11 @@ static struct resource mipidsi0_resources[] = {
321 }, 305 },
322}; 306};
323 307
324#define DSI0PHYCR 0xe615006c
325static int sh_mipi_set_dot_clock(struct platform_device *pdev, 308static int sh_mipi_set_dot_clock(struct platform_device *pdev,
326 void __iomem *base, 309 void __iomem *base,
327 int enable) 310 int enable)
328{ 311{
329 struct clk *pck; 312 struct clk *pck, *phy;
330 int ret; 313 int ret;
331 314
332 pck = clk_get(&pdev->dev, "dsip_clk"); 315 pck = clk_get(&pdev->dev, "dsip_clk");
@@ -335,18 +318,27 @@ static int sh_mipi_set_dot_clock(struct platform_device *pdev,
335 goto sh_mipi_set_dot_clock_pck_err; 318 goto sh_mipi_set_dot_clock_pck_err;
336 } 319 }
337 320
321 phy = clk_get(&pdev->dev, "dsiphy_clk");
322 if (IS_ERR(phy)) {
323 ret = PTR_ERR(phy);
324 goto sh_mipi_set_dot_clock_phy_err;
325 }
326
338 if (enable) { 327 if (enable) {
339 clk_set_rate(pck, clk_round_rate(pck, 24000000)); 328 clk_set_rate(pck, clk_round_rate(pck, 24000000));
340 __raw_writel(0x2a809010, DSI0PHYCR); 329 clk_set_rate(phy, clk_round_rate(pck, 510000000));
341 clk_enable(pck); 330 clk_enable(pck);
331 clk_enable(phy);
342 } else { 332 } else {
343 clk_disable(pck); 333 clk_disable(pck);
334 clk_disable(phy);
344 } 335 }
345 336
346 ret = 0; 337 ret = 0;
347 338
339 clk_put(phy);
340sh_mipi_set_dot_clock_phy_err:
348 clk_put(pck); 341 clk_put(pck);
349
350sh_mipi_set_dot_clock_pck_err: 342sh_mipi_set_dot_clock_pck_err:
351 return ret; 343 return ret;
352} 344}
diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index aab0a349f759..f90ba5b850a3 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -258,10 +258,16 @@ static struct sh_mobile_meram_info meram_info = {
258 258
259static struct resource meram_resources[] = { 259static struct resource meram_resources[] = {
260 [0] = { 260 [0] = {
261 .name = "MERAM", 261 .name = "regs",
262 .start = 0xe8000000, 262 .start = 0xe8000000,
263 .end = 0xe81fffff, 263 .end = 0xe807ffff,
264 .flags = IORESOURCE_MEM, 264 .flags = IORESOURCE_MEM,
265 },
266 [1] = {
267 .name = "meram",
268 .start = 0xe8080000,
269 .end = 0xe81fffff,
270 .flags = IORESOURCE_MEM,
265 }, 271 },
266}; 272};
267 273
@@ -295,15 +301,6 @@ static struct resource sh_mmcif_resources[] = {
295 }, 301 },
296}; 302};
297 303
298static struct sh_mmcif_dma sh_mmcif_dma = {
299 .chan_priv_rx = {
300 .slave_id = SHDMA_SLAVE_MMCIF_RX,
301 },
302 .chan_priv_tx = {
303 .slave_id = SHDMA_SLAVE_MMCIF_TX,
304 },
305};
306
307static struct sh_mmcif_plat_data sh_mmcif_plat = { 304static struct sh_mmcif_plat_data sh_mmcif_plat = {
308 .sup_pclk = 0, 305 .sup_pclk = 0,
309 .ocr = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34, 306 .ocr = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
@@ -311,7 +308,8 @@ static struct sh_mmcif_plat_data sh_mmcif_plat = {
311 MMC_CAP_8_BIT_DATA | 308 MMC_CAP_8_BIT_DATA |
312 MMC_CAP_NEEDS_POLL, 309 MMC_CAP_NEEDS_POLL,
313 .get_cd = slot_cn7_get_cd, 310 .get_cd = slot_cn7_get_cd,
314 .dma = &sh_mmcif_dma, 311 .slave_id_tx = SHDMA_SLAVE_MMCIF_TX,
312 .slave_id_rx = SHDMA_SLAVE_MMCIF_RX,
315}; 313};
316 314
317static struct platform_device sh_mmcif_device = { 315static struct platform_device sh_mmcif_device = {
@@ -445,82 +443,6 @@ static struct platform_device usb1_host_device = {
445 .resource = usb1_host_resources, 443 .resource = usb1_host_resources,
446}; 444};
447 445
448static const struct fb_videomode ap4evb_lcdc_modes[] = {
449 {
450#ifdef CONFIG_AP4EVB_QHD
451 .name = "R63302(QHD)",
452 .xres = 544,
453 .yres = 961,
454 .left_margin = 72,
455 .right_margin = 600,
456 .hsync_len = 16,
457 .upper_margin = 8,
458 .lower_margin = 8,
459 .vsync_len = 2,
460 .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT,
461#else
462 .name = "WVGA Panel",
463 .xres = 800,
464 .yres = 480,
465 .left_margin = 220,
466 .right_margin = 110,
467 .hsync_len = 70,
468 .upper_margin = 20,
469 .lower_margin = 5,
470 .vsync_len = 5,
471 .sync = 0,
472#endif
473 },
474};
475static struct sh_mobile_meram_cfg lcd_meram_cfg = {
476 .icb[0] = {
477 .marker_icb = 28,
478 .cache_icb = 24,
479 .meram_offset = 0x0,
480 .meram_size = 0x40,
481 },
482 .icb[1] = {
483 .marker_icb = 29,
484 .cache_icb = 25,
485 .meram_offset = 0x40,
486 .meram_size = 0x40,
487 },
488};
489
490static struct sh_mobile_lcdc_info lcdc_info = {
491 .meram_dev = &meram_info,
492 .ch[0] = {
493 .chan = LCDC_CHAN_MAINLCD,
494 .fourcc = V4L2_PIX_FMT_RGB565,
495 .lcd_cfg = ap4evb_lcdc_modes,
496 .num_cfg = ARRAY_SIZE(ap4evb_lcdc_modes),
497 .meram_cfg = &lcd_meram_cfg,
498 }
499};
500
501static struct resource lcdc_resources[] = {
502 [0] = {
503 .name = "LCDC",
504 .start = 0xfe940000, /* P4-only space */
505 .end = 0xfe943fff,
506 .flags = IORESOURCE_MEM,
507 },
508 [1] = {
509 .start = intcs_evt2irq(0x580),
510 .flags = IORESOURCE_IRQ,
511 },
512};
513
514static struct platform_device lcdc_device = {
515 .name = "sh_mobile_lcdc_fb",
516 .num_resources = ARRAY_SIZE(lcdc_resources),
517 .resource = lcdc_resources,
518 .dev = {
519 .platform_data = &lcdc_info,
520 .coherent_dma_mask = ~0,
521 },
522};
523
524/* 446/*
525 * QHD display 447 * QHD display
526 */ 448 */
@@ -564,20 +486,25 @@ static struct platform_device keysc_device = {
564}; 486};
565 487
566/* MIPI-DSI */ 488/* MIPI-DSI */
567#define PHYCTRL 0x0070
568static int sh_mipi_set_dot_clock(struct platform_device *pdev, 489static int sh_mipi_set_dot_clock(struct platform_device *pdev,
569 void __iomem *base, 490 void __iomem *base,
570 int enable) 491 int enable)
571{ 492{
572 struct clk *pck = clk_get(&pdev->dev, "dsip_clk"); 493 struct clk *pck = clk_get(&pdev->dev, "dsip_clk");
573 void __iomem *phy = base + PHYCTRL;
574 494
575 if (IS_ERR(pck)) 495 if (IS_ERR(pck))
576 return PTR_ERR(pck); 496 return PTR_ERR(pck);
577 497
578 if (enable) { 498 if (enable) {
499 /*
500 * DSIPCLK = 24MHz
501 * D-PHY = DSIPCLK * ((0x6*2)+1) = 312MHz (see .phyctrl)
502 * HsByteCLK = D-PHY/8 = 39MHz
503 *
504 * X * Y * FPS =
505 * (544+72+600+16) * (961+8+8+2) * 30 = 36.1MHz
506 */
579 clk_set_rate(pck, clk_round_rate(pck, 24000000)); 507 clk_set_rate(pck, clk_round_rate(pck, 24000000));
580 iowrite32(ioread32(phy) | (0xb << 8), phy);
581 clk_enable(pck); 508 clk_enable(pck);
582 } else { 509 } else {
583 clk_disable(pck); 510 clk_disable(pck);
@@ -601,11 +528,14 @@ static struct resource mipidsi0_resources[] = {
601 }, 528 },
602}; 529};
603 530
531static struct sh_mobile_lcdc_info lcdc_info;
532
604static struct sh_mipi_dsi_info mipidsi0_info = { 533static struct sh_mipi_dsi_info mipidsi0_info = {
605 .data_format = MIPI_RGB888, 534 .data_format = MIPI_RGB888,
606 .lcd_chan = &lcdc_info.ch[0], 535 .lcd_chan = &lcdc_info.ch[0],
607 .lane = 2, 536 .lane = 2,
608 .vsynw_offset = 17, 537 .vsynw_offset = 17,
538 .phyctrl = 0x6 << 8,
609 .flags = SH_MIPI_DSI_SYNC_PULSES_MODE | 539 .flags = SH_MIPI_DSI_SYNC_PULSES_MODE |
610 SH_MIPI_DSI_HSbyteCLK, 540 SH_MIPI_DSI_HSbyteCLK,
611 .set_dot_clock = sh_mipi_set_dot_clock, 541 .set_dot_clock = sh_mipi_set_dot_clock,
@@ -627,6 +557,81 @@ static struct platform_device *qhd_devices[] __initdata = {
627}; 557};
628#endif /* CONFIG_AP4EVB_QHD */ 558#endif /* CONFIG_AP4EVB_QHD */
629 559
560/* LCDC0 */
561static const struct fb_videomode ap4evb_lcdc_modes[] = {
562 {
563#ifdef CONFIG_AP4EVB_QHD
564 .name = "R63302(QHD)",
565 .xres = 544,
566 .yres = 961,
567 .left_margin = 72,
568 .right_margin = 600,
569 .hsync_len = 16,
570 .upper_margin = 8,
571 .lower_margin = 8,
572 .vsync_len = 2,
573 .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT,
574#else
575 .name = "WVGA Panel",
576 .xres = 800,
577 .yres = 480,
578 .left_margin = 220,
579 .right_margin = 110,
580 .hsync_len = 70,
581 .upper_margin = 20,
582 .lower_margin = 5,
583 .vsync_len = 5,
584 .sync = 0,
585#endif
586 },
587};
588
589static const struct sh_mobile_meram_cfg lcd_meram_cfg = {
590 .icb[0] = {
591 .meram_size = 0x40,
592 },
593 .icb[1] = {
594 .meram_size = 0x40,
595 },
596};
597
598static struct sh_mobile_lcdc_info lcdc_info = {
599 .meram_dev = &meram_info,
600 .ch[0] = {
601 .chan = LCDC_CHAN_MAINLCD,
602 .fourcc = V4L2_PIX_FMT_RGB565,
603 .lcd_modes = ap4evb_lcdc_modes,
604 .num_modes = ARRAY_SIZE(ap4evb_lcdc_modes),
605 .meram_cfg = &lcd_meram_cfg,
606#ifdef CONFIG_AP4EVB_QHD
607 .tx_dev = &mipidsi0_device,
608#endif
609 }
610};
611
612static struct resource lcdc_resources[] = {
613 [0] = {
614 .name = "LCDC",
615 .start = 0xfe940000, /* P4-only space */
616 .end = 0xfe943fff,
617 .flags = IORESOURCE_MEM,
618 },
619 [1] = {
620 .start = intcs_evt2irq(0x580),
621 .flags = IORESOURCE_IRQ,
622 },
623};
624
625static struct platform_device lcdc_device = {
626 .name = "sh_mobile_lcdc_fb",
627 .num_resources = ARRAY_SIZE(lcdc_resources),
628 .resource = lcdc_resources,
629 .dev = {
630 .platform_data = &lcdc_info,
631 .coherent_dma_mask = ~0,
632 },
633};
634
630/* FSI */ 635/* FSI */
631#define IRQ_FSI evt2irq(0x1840) 636#define IRQ_FSI evt2irq(0x1840)
632static int __fsi_set_rate(struct clk *clk, long rate, int enable) 637static int __fsi_set_rate(struct clk *clk, long rate, int enable)
@@ -745,26 +750,18 @@ fsi_set_rate_end:
745 return ret; 750 return ret;
746} 751}
747 752
748static int fsi_set_rate(struct device *dev, int is_porta, int rate, int enable)
749{
750 int ret;
751
752 if (is_porta)
753 ret = fsi_ak4642_set_rate(dev, rate, enable);
754 else
755 ret = fsi_hdmi_set_rate(dev, rate, enable);
756
757 return ret;
758}
759
760static struct sh_fsi_platform_info fsi_info = { 753static struct sh_fsi_platform_info fsi_info = {
761 .porta_flags = SH_FSI_BRS_INV, 754 .port_a = {
762 755 .flags = SH_FSI_BRS_INV,
763 .portb_flags = SH_FSI_BRS_INV | 756 .set_rate = fsi_ak4642_set_rate,
764 SH_FSI_BRM_INV | 757 },
765 SH_FSI_LRS_INV | 758 .port_b = {
766 SH_FSI_FMT_SPDIF, 759 .flags = SH_FSI_BRS_INV |
767 .set_rate = fsi_set_rate, 760 SH_FSI_BRM_INV |
761 SH_FSI_LRS_INV |
762 SH_FSI_FMT_SPDIF,
763 .set_rate = fsi_hdmi_set_rate,
764 },
768}; 765};
769 766
770static struct resource fsi_resources[] = { 767static struct resource fsi_resources[] = {
@@ -802,69 +799,15 @@ static struct fsi_ak4642_info fsi2_ak4643_info = {
802static struct platform_device fsi_ak4643_device = { 799static struct platform_device fsi_ak4643_device = {
803 .name = "fsi-ak4642-audio", 800 .name = "fsi-ak4642-audio",
804 .dev = { 801 .dev = {
805 .platform_data = &fsi_info, 802 .platform_data = &fsi2_ak4643_info,
806 },
807};
808
809static struct sh_mobile_meram_cfg hdmi_meram_cfg = {
810 .icb[0] = {
811 .marker_icb = 30,
812 .cache_icb = 26,
813 .meram_offset = 0x80,
814 .meram_size = 0x100,
815 },
816 .icb[1] = {
817 .marker_icb = 31,
818 .cache_icb = 27,
819 .meram_offset = 0x180,
820 .meram_size = 0x100,
821 },
822};
823
824static struct sh_mobile_lcdc_info sh_mobile_lcdc1_info = {
825 .clock_source = LCDC_CLK_EXTERNAL,
826 .meram_dev = &meram_info,
827 .ch[0] = {
828 .chan = LCDC_CHAN_MAINLCD,
829 .fourcc = V4L2_PIX_FMT_RGB565,
830 .interface_type = RGB24,
831 .clock_divider = 1,
832 .flags = LCDC_FLAGS_DWPOL,
833 .meram_cfg = &hdmi_meram_cfg,
834 }
835};
836
837static struct resource lcdc1_resources[] = {
838 [0] = {
839 .name = "LCDC1",
840 .start = 0xfe944000,
841 .end = 0xfe947fff,
842 .flags = IORESOURCE_MEM,
843 },
844 [1] = {
845 .start = intcs_evt2irq(0x1780),
846 .flags = IORESOURCE_IRQ,
847 },
848};
849
850static struct platform_device lcdc1_device = {
851 .name = "sh_mobile_lcdc_fb",
852 .num_resources = ARRAY_SIZE(lcdc1_resources),
853 .resource = lcdc1_resources,
854 .id = 1,
855 .dev = {
856 .platform_data = &sh_mobile_lcdc1_info,
857 .coherent_dma_mask = ~0,
858 }, 803 },
859}; 804};
860 805
806/* LCDC1 */
861static long ap4evb_clk_optimize(unsigned long target, unsigned long *best_freq, 807static long ap4evb_clk_optimize(unsigned long target, unsigned long *best_freq,
862 unsigned long *parent_freq); 808 unsigned long *parent_freq);
863 809
864
865static struct sh_mobile_hdmi_info hdmi_info = { 810static struct sh_mobile_hdmi_info hdmi_info = {
866 .lcd_chan = &sh_mobile_lcdc1_info.ch[0],
867 .lcd_dev = &lcdc1_device.dev,
868 .flags = HDMI_SND_SRC_SPDIF, 811 .flags = HDMI_SND_SRC_SPDIF,
869 .clk_optimize_parent = ap4evb_clk_optimize, 812 .clk_optimize_parent = ap4evb_clk_optimize,
870}; 813};
@@ -893,10 +836,6 @@ static struct platform_device hdmi_device = {
893 }, 836 },
894}; 837};
895 838
896static struct platform_device fsi_hdmi_device = {
897 .name = "sh_fsi2_b_hdmi",
898};
899
900static long ap4evb_clk_optimize(unsigned long target, unsigned long *best_freq, 839static long ap4evb_clk_optimize(unsigned long target, unsigned long *best_freq,
901 unsigned long *parent_freq) 840 unsigned long *parent_freq)
902{ 841{
@@ -916,6 +855,57 @@ static long ap4evb_clk_optimize(unsigned long target, unsigned long *best_freq,
916 return error; 855 return error;
917} 856}
918 857
858static const struct sh_mobile_meram_cfg hdmi_meram_cfg = {
859 .icb[0] = {
860 .meram_size = 0x100,
861 },
862 .icb[1] = {
863 .meram_size = 0x100,
864 },
865};
866
867static struct sh_mobile_lcdc_info sh_mobile_lcdc1_info = {
868 .clock_source = LCDC_CLK_EXTERNAL,
869 .meram_dev = &meram_info,
870 .ch[0] = {
871 .chan = LCDC_CHAN_MAINLCD,
872 .fourcc = V4L2_PIX_FMT_RGB565,
873 .interface_type = RGB24,
874 .clock_divider = 1,
875 .flags = LCDC_FLAGS_DWPOL,
876 .meram_cfg = &hdmi_meram_cfg,
877 .tx_dev = &hdmi_device,
878 }
879};
880
881static struct resource lcdc1_resources[] = {
882 [0] = {
883 .name = "LCDC1",
884 .start = 0xfe944000,
885 .end = 0xfe947fff,
886 .flags = IORESOURCE_MEM,
887 },
888 [1] = {
889 .start = intcs_evt2irq(0x1780),
890 .flags = IORESOURCE_IRQ,
891 },
892};
893
894static struct platform_device lcdc1_device = {
895 .name = "sh_mobile_lcdc_fb",
896 .num_resources = ARRAY_SIZE(lcdc1_resources),
897 .resource = lcdc1_resources,
898 .id = 1,
899 .dev = {
900 .platform_data = &sh_mobile_lcdc1_info,
901 .coherent_dma_mask = ~0,
902 },
903};
904
905static struct platform_device fsi_hdmi_device = {
906 .name = "sh_fsi2_b_hdmi",
907};
908
919static struct gpio_led ap4evb_leds[] = { 909static struct gpio_led ap4evb_leds[] = {
920 { 910 {
921 .name = "led4", 911 .name = "led4",
@@ -1050,9 +1040,9 @@ static struct platform_device *ap4evb_devices[] __initdata = {
1050 &fsi_ak4643_device, 1040 &fsi_ak4643_device,
1051 &fsi_hdmi_device, 1041 &fsi_hdmi_device,
1052 &sh_mmcif_device, 1042 &sh_mmcif_device,
1053 &lcdc1_device,
1054 &lcdc_device,
1055 &hdmi_device, 1043 &hdmi_device,
1044 &lcdc_device,
1045 &lcdc1_device,
1056 &ceu_device, 1046 &ceu_device,
1057 &ap4evb_camera, 1047 &ap4evb_camera,
1058 &meram_device, 1048 &meram_device,
@@ -1363,8 +1353,8 @@ static void __init ap4evb_init(void)
1363 lcdc_info.ch[0].interface_type = RGB24; 1353 lcdc_info.ch[0].interface_type = RGB24;
1364 lcdc_info.ch[0].clock_divider = 1; 1354 lcdc_info.ch[0].clock_divider = 1;
1365 lcdc_info.ch[0].flags = LCDC_FLAGS_DWPOL; 1355 lcdc_info.ch[0].flags = LCDC_FLAGS_DWPOL;
1366 lcdc_info.ch[0].lcd_size_cfg.width = 44; 1356 lcdc_info.ch[0].panel_cfg.width = 44;
1367 lcdc_info.ch[0].lcd_size_cfg.height = 79; 1357 lcdc_info.ch[0].panel_cfg.height = 79;
1368 1358
1369 platform_add_devices(qhd_devices, ARRAY_SIZE(qhd_devices)); 1359 platform_add_devices(qhd_devices, ARRAY_SIZE(qhd_devices));
1370 1360
@@ -1405,8 +1395,8 @@ static void __init ap4evb_init(void)
1405 lcdc_info.ch[0].interface_type = RGB18; 1395 lcdc_info.ch[0].interface_type = RGB18;
1406 lcdc_info.ch[0].clock_divider = 3; 1396 lcdc_info.ch[0].clock_divider = 3;
1407 lcdc_info.ch[0].flags = 0; 1397 lcdc_info.ch[0].flags = 0;
1408 lcdc_info.ch[0].lcd_size_cfg.width = 152; 1398 lcdc_info.ch[0].panel_cfg.width = 152;
1409 lcdc_info.ch[0].lcd_size_cfg.height = 91; 1399 lcdc_info.ch[0].panel_cfg.height = 91;
1410 1400
1411 /* enable TouchScreen */ 1401 /* enable TouchScreen */
1412 irq_set_irq_type(IRQ7, IRQ_TYPE_LEVEL_LOW); 1402 irq_set_irq_type(IRQ7, IRQ_TYPE_LEVEL_LOW);
diff --git a/arch/arm/mach-shmobile/board-bonito.c b/arch/arm/mach-shmobile/board-bonito.c
index 4d2201622323..c79baa9ef61b 100644
--- a/arch/arm/mach-shmobile/board-bonito.c
+++ b/arch/arm/mach-shmobile/board-bonito.c
@@ -27,6 +27,7 @@
27#include <linux/platform_device.h> 27#include <linux/platform_device.h>
28#include <linux/gpio.h> 28#include <linux/gpio.h>
29#include <linux/smsc911x.h> 29#include <linux/smsc911x.h>
30#include <linux/videodev2.h>
30#include <mach/common.h> 31#include <mach/common.h>
31#include <asm/mach-types.h> 32#include <asm/mach-types.h>
32#include <asm/mach/arch.h> 33#include <asm/mach/arch.h>
@@ -241,13 +242,13 @@ static struct sh_mobile_lcdc_info lcdc0_info = {
241 .clock_source = LCDC_CLK_BUS, 242 .clock_source = LCDC_CLK_BUS,
242 .ch[0] = { 243 .ch[0] = {
243 .chan = LCDC_CHAN_MAINLCD, 244 .chan = LCDC_CHAN_MAINLCD,
244 .bpp = 16, 245 .fourcc = V4L2_PIX_FMT_RGB565,
245 .interface_type = RGB24, 246 .interface_type = RGB24,
246 .clock_divider = 5, 247 .clock_divider = 5,
247 .flags = 0, 248 .flags = 0,
248 .lcd_cfg = &lcdc0_mode, 249 .lcd_modes = &lcdc0_mode,
249 .num_cfg = 1, 250 .num_modes = 1,
250 .lcd_size_cfg = { 251 .panel_cfg = {
251 .width = 152, 252 .width = 152,
252 .height = 91, 253 .height = 91,
253 }, 254 },
diff --git a/arch/arm/mach-shmobile/board-kota2.c b/arch/arm/mach-shmobile/board-kota2.c
index 857ceeec1bb0..c8e7ca23fc06 100644
--- a/arch/arm/mach-shmobile/board-kota2.c
+++ b/arch/arm/mach-shmobile/board-kota2.c
@@ -143,11 +143,10 @@ static struct gpio_keys_button gpio_buttons[] = {
143static struct gpio_keys_platform_data gpio_key_info = { 143static struct gpio_keys_platform_data gpio_key_info = {
144 .buttons = gpio_buttons, 144 .buttons = gpio_buttons,
145 .nbuttons = ARRAY_SIZE(gpio_buttons), 145 .nbuttons = ARRAY_SIZE(gpio_buttons),
146 .poll_interval = 250, /* polled for now */
147}; 146};
148 147
149static struct platform_device gpio_keys_device = { 148static struct platform_device gpio_keys_device = {
150 .name = "gpio-keys-polled", /* polled for now */ 149 .name = "gpio-keys",
151 .id = -1, 150 .id = -1,
152 .dev = { 151 .dev = {
153 .platform_data = &gpio_key_info, 152 .platform_data = &gpio_key_info,
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index 9b42fbd10f8e..865d56d96299 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -43,7 +43,6 @@
43#include <linux/smsc911x.h> 43#include <linux/smsc911x.h>
44#include <linux/sh_intc.h> 44#include <linux/sh_intc.h>
45#include <linux/tca6416_keypad.h> 45#include <linux/tca6416_keypad.h>
46#include <linux/usb/r8a66597.h>
47#include <linux/usb/renesas_usbhs.h> 46#include <linux/usb/renesas_usbhs.h>
48#include <linux/dma-mapping.h> 47#include <linux/dma-mapping.h>
49 48
@@ -145,11 +144,6 @@
145 * 1-2 short | VBUS 5V | Host 144 * 1-2 short | VBUS 5V | Host
146 * open | external VBUS | Function 145 * open | external VBUS | Function
147 * 146 *
148 * *1
149 * CN31 is used as
150 * CONFIG_USB_R8A66597_HCD Host
151 * CONFIG_USB_RENESAS_USBHS Function
152 *
153 * CAUTION 147 * CAUTION
154 * 148 *
155 * renesas_usbhs driver can use external interrupt mode 149 * renesas_usbhs driver can use external interrupt mode
@@ -161,15 +155,6 @@
161 * mackerel can not use external interrupt (IRQ7-PORT167) mode on "USB0", 155 * mackerel can not use external interrupt (IRQ7-PORT167) mode on "USB0",
162 * because Touchscreen is using IRQ7-PORT40. 156 * because Touchscreen is using IRQ7-PORT40.
163 * It is impossible to use IRQ7 demux on this board. 157 * It is impossible to use IRQ7 demux on this board.
164 *
165 * We can use external interrupt mode USB-Function on "USB1".
166 * USB1 can become Host by r8a66597, and become Function by renesas_usbhs.
167 * But don't select both drivers in same time.
168 * These uses same IRQ number for request_irq(), and aren't supporting
169 * IRQF_SHARED / IORESOURCE_IRQ_SHAREABLE.
170 *
171 * Actually these are old/new version of USB driver.
172 * This mean its register will be broken if it supports shared IRQ,
173 */ 158 */
174 159
175/* 160/*
@@ -208,6 +193,16 @@
208 */ 193 */
209 194
210/* 195/*
196 * FSI - AK4642
197 *
198 * it needs amixer settings for playing
199 *
200 * amixer set "Headphone" on
201 * amixer set "HPOUTL Mixer DACH" on
202 * amixer set "HPOUTR Mixer DACH" on
203 */
204
205/*
211 * FIXME !! 206 * FIXME !!
212 * 207 *
213 * gpio_no_direction 208 * gpio_no_direction
@@ -323,8 +318,14 @@ static struct sh_mobile_meram_info mackerel_meram_info = {
323 318
324static struct resource meram_resources[] = { 319static struct resource meram_resources[] = {
325 [0] = { 320 [0] = {
326 .name = "MERAM", 321 .name = "regs",
327 .start = 0xe8000000, 322 .start = 0xe8000000,
323 .end = 0xe807ffff,
324 .flags = IORESOURCE_MEM,
325 },
326 [1] = {
327 .name = "meram",
328 .start = 0xe8080000,
328 .end = 0xe81fffff, 329 .end = 0xe81fffff,
329 .flags = IORESOURCE_MEM, 330 .flags = IORESOURCE_MEM,
330 }, 331 },
@@ -356,29 +357,23 @@ static struct fb_videomode mackerel_lcdc_modes[] = {
356 }, 357 },
357}; 358};
358 359
359static int mackerel_set_brightness(void *board_data, int brightness) 360static int mackerel_set_brightness(int brightness)
360{ 361{
361 gpio_set_value(GPIO_PORT31, brightness); 362 gpio_set_value(GPIO_PORT31, brightness);
362 363
363 return 0; 364 return 0;
364} 365}
365 366
366static int mackerel_get_brightness(void *board_data) 367static int mackerel_get_brightness(void)
367{ 368{
368 return gpio_get_value(GPIO_PORT31); 369 return gpio_get_value(GPIO_PORT31);
369} 370}
370 371
371static struct sh_mobile_meram_cfg lcd_meram_cfg = { 372static const struct sh_mobile_meram_cfg lcd_meram_cfg = {
372 .icb[0] = { 373 .icb[0] = {
373 .marker_icb = 28,
374 .cache_icb = 24,
375 .meram_offset = 0x0,
376 .meram_size = 0x40, 374 .meram_size = 0x40,
377 }, 375 },
378 .icb[1] = { 376 .icb[1] = {
379 .marker_icb = 29,
380 .cache_icb = 25,
381 .meram_offset = 0x40,
382 .meram_size = 0x40, 377 .meram_size = 0x40,
383 }, 378 },
384}; 379};
@@ -389,20 +384,20 @@ static struct sh_mobile_lcdc_info lcdc_info = {
389 .ch[0] = { 384 .ch[0] = {
390 .chan = LCDC_CHAN_MAINLCD, 385 .chan = LCDC_CHAN_MAINLCD,
391 .fourcc = V4L2_PIX_FMT_RGB565, 386 .fourcc = V4L2_PIX_FMT_RGB565,
392 .lcd_cfg = mackerel_lcdc_modes, 387 .lcd_modes = mackerel_lcdc_modes,
393 .num_cfg = ARRAY_SIZE(mackerel_lcdc_modes), 388 .num_modes = ARRAY_SIZE(mackerel_lcdc_modes),
394 .interface_type = RGB24, 389 .interface_type = RGB24,
395 .clock_divider = 3, 390 .clock_divider = 3,
396 .flags = 0, 391 .flags = 0,
397 .lcd_size_cfg.width = 152, 392 .panel_cfg = {
398 .lcd_size_cfg.height = 91, 393 .width = 152,
399 .board_cfg = { 394 .height = 91,
400 .set_brightness = mackerel_set_brightness,
401 .get_brightness = mackerel_get_brightness,
402 }, 395 },
403 .bl_info = { 396 .bl_info = {
404 .name = "sh_mobile_lcdc_bl", 397 .name = "sh_mobile_lcdc_bl",
405 .max_brightness = 1, 398 .max_brightness = 1,
399 .set_brightness = mackerel_set_brightness,
400 .get_brightness = mackerel_get_brightness,
406 }, 401 },
407 .meram_cfg = &lcd_meram_cfg, 402 .meram_cfg = &lcd_meram_cfg,
408 } 403 }
@@ -431,21 +426,44 @@ static struct platform_device lcdc_device = {
431 }, 426 },
432}; 427};
433 428
434static struct sh_mobile_meram_cfg hdmi_meram_cfg = { 429/* HDMI */
430static struct sh_mobile_hdmi_info hdmi_info = {
431 .flags = HDMI_SND_SRC_SPDIF,
432};
433
434static struct resource hdmi_resources[] = {
435 [0] = {
436 .name = "HDMI",
437 .start = 0xe6be0000,
438 .end = 0xe6be00ff,
439 .flags = IORESOURCE_MEM,
440 },
441 [1] = {
442 /* There's also an HDMI interrupt on INTCS @ 0x18e0 */
443 .start = evt2irq(0x17e0),
444 .flags = IORESOURCE_IRQ,
445 },
446};
447
448static struct platform_device hdmi_device = {
449 .name = "sh-mobile-hdmi",
450 .num_resources = ARRAY_SIZE(hdmi_resources),
451 .resource = hdmi_resources,
452 .id = -1,
453 .dev = {
454 .platform_data = &hdmi_info,
455 },
456};
457
458static const struct sh_mobile_meram_cfg hdmi_meram_cfg = {
435 .icb[0] = { 459 .icb[0] = {
436 .marker_icb = 30,
437 .cache_icb = 26,
438 .meram_offset = 0x80,
439 .meram_size = 0x100, 460 .meram_size = 0x100,
440 }, 461 },
441 .icb[1] = { 462 .icb[1] = {
442 .marker_icb = 31,
443 .cache_icb = 27,
444 .meram_offset = 0x180,
445 .meram_size = 0x100, 463 .meram_size = 0x100,
446 }, 464 },
447}; 465};
448/* HDMI */ 466
449static struct sh_mobile_lcdc_info hdmi_lcdc_info = { 467static struct sh_mobile_lcdc_info hdmi_lcdc_info = {
450 .meram_dev = &mackerel_meram_info, 468 .meram_dev = &mackerel_meram_info,
451 .clock_source = LCDC_CLK_EXTERNAL, 469 .clock_source = LCDC_CLK_EXTERNAL,
@@ -456,6 +474,7 @@ static struct sh_mobile_lcdc_info hdmi_lcdc_info = {
456 .clock_divider = 1, 474 .clock_divider = 1,
457 .flags = LCDC_FLAGS_DWPOL, 475 .flags = LCDC_FLAGS_DWPOL,
458 .meram_cfg = &hdmi_meram_cfg, 476 .meram_cfg = &hdmi_meram_cfg,
477 .tx_dev = &hdmi_device,
459 } 478 }
460}; 479};
461 480
@@ -483,36 +502,6 @@ static struct platform_device hdmi_lcdc_device = {
483 }, 502 },
484}; 503};
485 504
486static struct sh_mobile_hdmi_info hdmi_info = {
487 .lcd_chan = &hdmi_lcdc_info.ch[0],
488 .lcd_dev = &hdmi_lcdc_device.dev,
489 .flags = HDMI_SND_SRC_SPDIF,
490};
491
492static struct resource hdmi_resources[] = {
493 [0] = {
494 .name = "HDMI",
495 .start = 0xe6be0000,
496 .end = 0xe6be00ff,
497 .flags = IORESOURCE_MEM,
498 },
499 [1] = {
500 /* There's also an HDMI interrupt on INTCS @ 0x18e0 */
501 .start = evt2irq(0x17e0),
502 .flags = IORESOURCE_IRQ,
503 },
504};
505
506static struct platform_device hdmi_device = {
507 .name = "sh-mobile-hdmi",
508 .num_resources = ARRAY_SIZE(hdmi_resources),
509 .resource = hdmi_resources,
510 .id = -1,
511 .dev = {
512 .platform_data = &hdmi_info,
513 },
514};
515
516static struct platform_device fsi_hdmi_device = { 505static struct platform_device fsi_hdmi_device = {
517 .name = "sh_fsi2_b_hdmi", 506 .name = "sh_fsi2_b_hdmi",
518}; 507};
@@ -676,51 +665,16 @@ static struct platform_device usbhs0_device = {
676 * Use J30 to select between Host and Function. This setting 665 * Use J30 to select between Host and Function. This setting
677 * can however not be detected by software. Hotplug of USBHS1 666 * can however not be detected by software. Hotplug of USBHS1
678 * is provided via IRQ8. 667 * is provided via IRQ8.
668 *
669 * Current USB1 works as "USB Host".
670 * - set J30 "short"
671 *
672 * If you want to use it as "USB gadget",
673 * - J30 "open"
674 * - modify usbhs1_get_id() USBHS_HOST -> USBHS_GADGET
675 * - add .get_vbus = usbhs_get_vbus in usbhs1_private
679 */ 676 */
680#define IRQ8 evt2irq(0x0300) 677#define IRQ8 evt2irq(0x0300)
681
682/* USBHS1 USB Host support via r8a66597_hcd */
683static void usb1_host_port_power(int port, int power)
684{
685 if (!power) /* only power-on is supported for now */
686 return;
687
688 /* set VBOUT/PWEN and EXTLP1 in DVSTCTR */
689 __raw_writew(__raw_readw(0xE68B0008) | 0x600, 0xE68B0008);
690}
691
692static struct r8a66597_platdata usb1_host_data = {
693 .on_chip = 1,
694 .port_power = usb1_host_port_power,
695};
696
697static struct resource usb1_host_resources[] = {
698 [0] = {
699 .name = "USBHS1",
700 .start = 0xe68b0000,
701 .end = 0xe68b00e6 - 1,
702 .flags = IORESOURCE_MEM,
703 },
704 [1] = {
705 .start = evt2irq(0x1ce0) /* USB1_USB1I0 */,
706 .flags = IORESOURCE_IRQ,
707 },
708};
709
710static struct platform_device usb1_host_device = {
711 .name = "r8a66597_hcd",
712 .id = 1,
713 .dev = {
714 .dma_mask = NULL, /* not use dma */
715 .coherent_dma_mask = 0xffffffff,
716 .platform_data = &usb1_host_data,
717 },
718 .num_resources = ARRAY_SIZE(usb1_host_resources),
719 .resource = usb1_host_resources,
720};
721
722/* USBHS1 USB Function support via renesas_usbhs */
723
724#define USB_PHY_MODE (1 << 4) 678#define USB_PHY_MODE (1 << 4)
725#define USB_PHY_INT_EN ((1 << 3) | (1 << 2)) 679#define USB_PHY_INT_EN ((1 << 3) | (1 << 2))
726#define USB_PHY_ON (1 << 1) 680#define USB_PHY_ON (1 << 1)
@@ -776,7 +730,7 @@ static void usbhs1_hardware_exit(struct platform_device *pdev)
776 730
777static int usbhs1_get_id(struct platform_device *pdev) 731static int usbhs1_get_id(struct platform_device *pdev)
778{ 732{
779 return USBHS_GADGET; 733 return USBHS_HOST;
780} 734}
781 735
782static u32 usbhs1_pipe_cfg[] = { 736static u32 usbhs1_pipe_cfg[] = {
@@ -807,7 +761,6 @@ static struct usbhs_private usbhs1_private = {
807 .hardware_exit = usbhs1_hardware_exit, 761 .hardware_exit = usbhs1_hardware_exit,
808 .get_id = usbhs1_get_id, 762 .get_id = usbhs1_get_id,
809 .phy_reset = usbhs_phy_reset, 763 .phy_reset = usbhs_phy_reset,
810 .get_vbus = usbhs_get_vbus,
811 }, 764 },
812 .driver_param = { 765 .driver_param = {
813 .buswait_bwait = 4, 766 .buswait_bwait = 4,
@@ -901,7 +854,7 @@ static int __fsi_set_round_rate(struct clk *clk, long rate, int enable)
901 return clk_enable(clk); 854 return clk_enable(clk);
902} 855}
903 856
904static int fsi_set_rate(struct device *dev, int is_porta, int rate, int enable) 857static int fsi_b_set_rate(struct device *dev, int rate, int enable)
905{ 858{
906 struct clk *fsib_clk; 859 struct clk *fsib_clk;
907 struct clk *fdiv_clk = &sh7372_fsidivb_clk; 860 struct clk *fdiv_clk = &sh7372_fsidivb_clk;
@@ -910,10 +863,6 @@ static int fsi_set_rate(struct device *dev, int is_porta, int rate, int enable)
910 int ackmd_bpfmd; 863 int ackmd_bpfmd;
911 int ret; 864 int ret;
912 865
913 /* FSIA is slave mode. nothing to do here */
914 if (is_porta)
915 return 0;
916
917 /* clock start */ 866 /* clock start */
918 switch (rate) { 867 switch (rate) {
919 case 44100: 868 case 44100:
@@ -957,14 +906,16 @@ fsi_set_rate_end:
957} 906}
958 907
959static struct sh_fsi_platform_info fsi_info = { 908static struct sh_fsi_platform_info fsi_info = {
960 .porta_flags = SH_FSI_BRS_INV, 909 .port_a = {
961 910 .flags = SH_FSI_BRS_INV,
962 .portb_flags = SH_FSI_BRS_INV | 911 },
912 .port_b = {
913 .flags = SH_FSI_BRS_INV |
963 SH_FSI_BRM_INV | 914 SH_FSI_BRM_INV |
964 SH_FSI_LRS_INV | 915 SH_FSI_LRS_INV |
965 SH_FSI_FMT_SPDIF, 916 SH_FSI_FMT_SPDIF,
966 917 .set_rate = fsi_b_set_rate,
967 .set_rate = fsi_set_rate, 918 }
968}; 919};
969 920
970static struct resource fsi_resources[] = { 921static struct resource fsi_resources[] = {
@@ -1184,15 +1135,6 @@ static struct resource sh_mmcif_resources[] = {
1184 }, 1135 },
1185}; 1136};
1186 1137
1187static struct sh_mmcif_dma sh_mmcif_dma = {
1188 .chan_priv_rx = {
1189 .slave_id = SHDMA_SLAVE_MMCIF_RX,
1190 },
1191 .chan_priv_tx = {
1192 .slave_id = SHDMA_SLAVE_MMCIF_TX,
1193 },
1194};
1195
1196static struct sh_mmcif_plat_data sh_mmcif_plat = { 1138static struct sh_mmcif_plat_data sh_mmcif_plat = {
1197 .sup_pclk = 0, 1139 .sup_pclk = 0,
1198 .ocr = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34, 1140 .ocr = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
@@ -1200,7 +1142,8 @@ static struct sh_mmcif_plat_data sh_mmcif_plat = {
1200 MMC_CAP_8_BIT_DATA | 1142 MMC_CAP_8_BIT_DATA |
1201 MMC_CAP_NEEDS_POLL, 1143 MMC_CAP_NEEDS_POLL,
1202 .get_cd = slot_cn7_get_cd, 1144 .get_cd = slot_cn7_get_cd,
1203 .dma = &sh_mmcif_dma, 1145 .slave_id_tx = SHDMA_SLAVE_MMCIF_TX,
1146 .slave_id_rx = SHDMA_SLAVE_MMCIF_RX,
1204}; 1147};
1205 1148
1206static struct platform_device sh_mmcif_device = { 1149static struct platform_device sh_mmcif_device = {
@@ -1311,7 +1254,6 @@ static struct platform_device *mackerel_devices[] __initdata = {
1311 &nor_flash_device, 1254 &nor_flash_device,
1312 &smc911x_device, 1255 &smc911x_device,
1313 &lcdc_device, 1256 &lcdc_device,
1314 &usb1_host_device,
1315 &usbhs1_device, 1257 &usbhs1_device,
1316 &usbhs0_device, 1258 &usbhs0_device,
1317 &leds_device, 1259 &leds_device,
@@ -1326,8 +1268,8 @@ static struct platform_device *mackerel_devices[] __initdata = {
1326 &sh_mmcif_device, 1268 &sh_mmcif_device,
1327 &ceu_device, 1269 &ceu_device,
1328 &mackerel_camera, 1270 &mackerel_camera,
1329 &hdmi_lcdc_device,
1330 &hdmi_device, 1271 &hdmi_device,
1272 &hdmi_lcdc_device,
1331 &meram_device, 1273 &meram_device,
1332}; 1274};
1333 1275
@@ -1402,6 +1344,10 @@ static struct map_desc mackerel_io_desc[] __initdata = {
1402static void __init mackerel_map_io(void) 1344static void __init mackerel_map_io(void)
1403{ 1345{
1404 iotable_init(mackerel_io_desc, ARRAY_SIZE(mackerel_io_desc)); 1346 iotable_init(mackerel_io_desc, ARRAY_SIZE(mackerel_io_desc));
1347 /* DMA memory at 0xff200000 - 0xffdfffff. The default 2MB size isn't
1348 * enough to allocate the frame buffer memory.
1349 */
1350 init_consistent_dma_size(12 << 20);
1405 1351
1406 /* setup early devices and console here as well */ 1352 /* setup early devices and console here as well */
1407 sh7372_add_early_devices(); 1353 sh7372_add_early_devices();
@@ -1473,9 +1419,6 @@ static void __init mackerel_init(void)
1473 gpio_pull_down(GPIO_PORT167CR); /* VBUS0_1 pull down */ 1419 gpio_pull_down(GPIO_PORT167CR); /* VBUS0_1 pull down */
1474 gpio_request(GPIO_FN_IDIN_1_113, NULL); 1420 gpio_request(GPIO_FN_IDIN_1_113, NULL);
1475 1421
1476 /* USB phy tweak to make the r8a66597_hcd host driver work */
1477 __raw_writew(0x8a0a, 0xe6058130); /* USBCR4 */
1478
1479 /* enable FSI2 port A (ak4643) */ 1422 /* enable FSI2 port A (ak4643) */
1480 gpio_request(GPIO_FN_FSIAIBT, NULL); 1423 gpio_request(GPIO_FN_FSIAIBT, NULL);
1481 gpio_request(GPIO_FN_FSIAILR, NULL); 1424 gpio_request(GPIO_FN_FSIAILR, NULL);
diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c
index afbead6a6e17..7727cca6136c 100644
--- a/arch/arm/mach-shmobile/clock-sh73a0.c
+++ b/arch/arm/mach-shmobile/clock-sh73a0.c
@@ -365,6 +365,114 @@ static struct clk div6_clks[DIV6_NR] = {
365 dsi_parent, ARRAY_SIZE(dsi_parent), 12, 3), 365 dsi_parent, ARRAY_SIZE(dsi_parent), 12, 3),
366}; 366};
367 367
368/* DSI DIV */
369static unsigned long dsiphy_recalc(struct clk *clk)
370{
371 u32 value;
372
373 value = __raw_readl(clk->mapping->base);
374
375 /* FIXME */
376 if (!(value & 0x000B8000))
377 return clk->parent->rate;
378
379 value &= 0x3f;
380 value += 1;
381
382 if ((value < 12) ||
383 (value > 33)) {
384 pr_err("DSIPHY has wrong value (%d)", value);
385 return 0;
386 }
387
388 return clk->parent->rate / value;
389}
390
391static long dsiphy_round_rate(struct clk *clk, unsigned long rate)
392{
393 return clk_rate_mult_range_round(clk, 12, 33, rate);
394}
395
396static void dsiphy_disable(struct clk *clk)
397{
398 u32 value;
399
400 value = __raw_readl(clk->mapping->base);
401 value &= ~0x000B8000;
402
403 __raw_writel(value , clk->mapping->base);
404}
405
406static int dsiphy_enable(struct clk *clk)
407{
408 u32 value;
409 int multi;
410
411 value = __raw_readl(clk->mapping->base);
412 multi = (value & 0x3f) + 1;
413
414 if ((multi < 12) || (multi > 33))
415 return -EIO;
416
417 __raw_writel(value | 0x000B8000, clk->mapping->base);
418
419 return 0;
420}
421
422static int dsiphy_set_rate(struct clk *clk, unsigned long rate)
423{
424 u32 value;
425 int idx;
426
427 idx = rate / clk->parent->rate;
428 if ((idx < 12) || (idx > 33))
429 return -EINVAL;
430
431 idx += -1;
432
433 value = __raw_readl(clk->mapping->base);
434 value = (value & ~0x3f) + idx;
435
436 __raw_writel(value, clk->mapping->base);
437
438 return 0;
439}
440
441static struct clk_ops dsiphy_clk_ops = {
442 .recalc = dsiphy_recalc,
443 .round_rate = dsiphy_round_rate,
444 .set_rate = dsiphy_set_rate,
445 .enable = dsiphy_enable,
446 .disable = dsiphy_disable,
447};
448
449static struct clk_mapping dsi0phy_clk_mapping = {
450 .phys = DSI0PHYCR,
451 .len = 4,
452};
453
454static struct clk_mapping dsi1phy_clk_mapping = {
455 .phys = DSI1PHYCR,
456 .len = 4,
457};
458
459static struct clk dsi0phy_clk = {
460 .ops = &dsiphy_clk_ops,
461 .parent = &div6_clks[DIV6_DSI0P], /* late install */
462 .mapping = &dsi0phy_clk_mapping,
463};
464
465static struct clk dsi1phy_clk = {
466 .ops = &dsiphy_clk_ops,
467 .parent = &div6_clks[DIV6_DSI1P], /* late install */
468 .mapping = &dsi1phy_clk_mapping,
469};
470
471static struct clk *late_main_clks[] = {
472 &dsi0phy_clk,
473 &dsi1phy_clk,
474};
475
368enum { MSTP001, 476enum { MSTP001,
369 MSTP129, MSTP128, MSTP127, MSTP126, MSTP125, MSTP118, MSTP116, MSTP100, 477 MSTP129, MSTP128, MSTP127, MSTP126, MSTP125, MSTP118, MSTP116, MSTP100,
370 MSTP219, 478 MSTP219,
@@ -429,6 +537,8 @@ static struct clk_lookup lookups[] = {
429 CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSIT]), 537 CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSIT]),
430 CLKDEV_ICK_ID("dsip_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSI0P]), 538 CLKDEV_ICK_ID("dsip_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSI0P]),
431 CLKDEV_ICK_ID("dsip_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSI1P]), 539 CLKDEV_ICK_ID("dsip_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSI1P]),
540 CLKDEV_ICK_ID("dsiphy_clk", "sh-mipi-dsi.0", &dsi0phy_clk),
541 CLKDEV_ICK_ID("dsiphy_clk", "sh-mipi-dsi.1", &dsi1phy_clk),
432 542
433 /* MSTP32 clocks */ 543 /* MSTP32 clocks */
434 CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* I2C2 */ 544 CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* I2C2 */
@@ -504,6 +614,9 @@ void __init sh73a0_clock_init(void)
504 if (!ret) 614 if (!ret)
505 ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR); 615 ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
506 616
617 for (k = 0; !ret && (k < ARRAY_SIZE(late_main_clks)); k++)
618 ret = clk_register(late_main_clks[k]);
619
507 clkdev_add_table(lookups, ARRAY_SIZE(lookups)); 620 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
508 621
509 if (!ret) 622 if (!ret)
diff --git a/arch/arm/mach-shmobile/include/mach/sh73a0.h b/arch/arm/mach-shmobile/include/mach/sh73a0.h
index 881d515a9686..cad57578ceed 100644
--- a/arch/arm/mach-shmobile/include/mach/sh73a0.h
+++ b/arch/arm/mach-shmobile/include/mach/sh73a0.h
@@ -515,8 +515,8 @@ enum {
515 SHDMA_SLAVE_MMCIF_RX, 515 SHDMA_SLAVE_MMCIF_RX,
516}; 516};
517 517
518/* PINT interrupts are located at Linux IRQ 768 and up */ 518/* PINT interrupts are located at Linux IRQ 800 and up */
519#define SH73A0_PINT0_IRQ(irq) ((irq) + 768) 519#define SH73A0_PINT0_IRQ(irq) ((irq) + 800)
520#define SH73A0_PINT1_IRQ(irq) ((irq) + 800) 520#define SH73A0_PINT1_IRQ(irq) ((irq) + 832)
521 521
522#endif /* __ASM_SH73A0_H__ */ 522#endif /* __ASM_SH73A0_H__ */
diff --git a/arch/arm/mach-shmobile/intc-sh73a0.c b/arch/arm/mach-shmobile/intc-sh73a0.c
index 1eda6b0b69e3..9857595eaa79 100644
--- a/arch/arm/mach-shmobile/intc-sh73a0.c
+++ b/arch/arm/mach-shmobile/intc-sh73a0.c
@@ -19,6 +19,7 @@
19#include <linux/kernel.h> 19#include <linux/kernel.h>
20#include <linux/init.h> 20#include <linux/init.h>
21#include <linux/interrupt.h> 21#include <linux/interrupt.h>
22#include <linux/module.h>
22#include <linux/irq.h> 23#include <linux/irq.h>
23#include <linux/io.h> 24#include <linux/io.h>
24#include <linux/sh_intc.h> 25#include <linux/sh_intc.h>
@@ -445,6 +446,7 @@ void __init sh73a0_init_irq(void)
445 setup_irq(gic_spi(1 + k), &sh73a0_irq_pin_cascade[k]); 446 setup_irq(gic_spi(1 + k), &sh73a0_irq_pin_cascade[k]);
446 447
447 n = intcs_evt2irq(to_intc_vect(gic_spi(1 + k))); 448 n = intcs_evt2irq(to_intc_vect(gic_spi(1 + k)));
449 WARN_ON(irq_alloc_desc_at(n, numa_node_id()) != n);
448 irq_set_chip_and_handler_name(n, &intca_gic_irq_chip, 450 irq_set_chip_and_handler_name(n, &intca_gic_irq_chip,
449 handle_level_irq, "level"); 451 handle_level_irq, "level");
450 set_irq_flags(n, IRQF_VALID); /* yuck */ 452 set_irq_flags(n, IRQF_VALID); /* yuck */
diff --git a/arch/arm/mach-shmobile/pfc-r8a7779.c b/arch/arm/mach-shmobile/pfc-r8a7779.c
index 963532f2b2c4..d14c9b048077 100644
--- a/arch/arm/mach-shmobile/pfc-r8a7779.c
+++ b/arch/arm/mach-shmobile/pfc-r8a7779.c
@@ -2120,7 +2120,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
2120 FN_AUDATA3, 0, 0, 0 } 2120 FN_AUDATA3, 0, 0, 0 }
2121 }, 2121 },
2122 { PINMUX_CFG_REG_VAR("IPSR4", 0xfffc0030, 32, 2122 { PINMUX_CFG_REG_VAR("IPSR4", 0xfffc0030, 32,
2123 3, 1, 1, 1, 1, 1, 1, 3, 3, 1, 2123 3, 1, 1, 1, 1, 1, 1, 3, 3,
2124 1, 1, 1, 1, 1, 1, 3, 3, 3, 2) { 2124 1, 1, 1, 1, 1, 1, 3, 3, 3, 2) {
2125 /* IP4_31_29 [3] */ 2125 /* IP4_31_29 [3] */
2126 FN_DU1_DB0, FN_VI2_DATA4_VI2_B4, FN_SCL2_B, FN_SD3_DAT0, 2126 FN_DU1_DB0, FN_VI2_DATA4_VI2_B4, FN_SCL2_B, FN_SD3_DAT0,
diff --git a/arch/arm/mach-shmobile/pfc-sh7372.c b/arch/arm/mach-shmobile/pfc-sh7372.c
index 1bd6585a6acf..336093f9210a 100644
--- a/arch/arm/mach-shmobile/pfc-sh7372.c
+++ b/arch/arm/mach-shmobile/pfc-sh7372.c
@@ -23,6 +23,7 @@
23#include <linux/init.h> 23#include <linux/init.h>
24#include <linux/kernel.h> 24#include <linux/kernel.h>
25#include <linux/gpio.h> 25#include <linux/gpio.h>
26#include <mach/irqs.h>
26#include <mach/sh7372.h> 27#include <mach/sh7372.h>
27 28
28#define CPU_ALL_PORT(fn, pfx, sfx) \ 29#define CPU_ALL_PORT(fn, pfx, sfx) \
@@ -1594,6 +1595,43 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
1594 { }, 1595 { },
1595}; 1596};
1596 1597
1598#define EXT_IRQ16L(n) evt2irq(0x200 + ((n) << 5))
1599#define EXT_IRQ16H(n) evt2irq(0x3200 + (((n) - 16) << 5))
1600static struct pinmux_irq pinmux_irqs[] = {
1601 PINMUX_IRQ(EXT_IRQ16L(0), PORT6_FN0, PORT162_FN0),
1602 PINMUX_IRQ(EXT_IRQ16L(1), PORT12_FN0),
1603 PINMUX_IRQ(EXT_IRQ16L(2), PORT4_FN0, PORT5_FN0),
1604 PINMUX_IRQ(EXT_IRQ16L(3), PORT8_FN0, PORT16_FN0),
1605 PINMUX_IRQ(EXT_IRQ16L(4), PORT17_FN0, PORT163_FN0),
1606 PINMUX_IRQ(EXT_IRQ16L(5), PORT18_FN0),
1607 PINMUX_IRQ(EXT_IRQ16L(6), PORT39_FN0, PORT164_FN0),
1608 PINMUX_IRQ(EXT_IRQ16L(7), PORT40_FN0, PORT167_FN0),
1609 PINMUX_IRQ(EXT_IRQ16L(8), PORT41_FN0, PORT168_FN0),
1610 PINMUX_IRQ(EXT_IRQ16L(9), PORT42_FN0, PORT169_FN0),
1611 PINMUX_IRQ(EXT_IRQ16L(10), PORT65_FN0),
1612 PINMUX_IRQ(EXT_IRQ16L(11), PORT67_FN0),
1613 PINMUX_IRQ(EXT_IRQ16L(12), PORT80_FN0, PORT137_FN0),
1614 PINMUX_IRQ(EXT_IRQ16L(13), PORT81_FN0, PORT145_FN0),
1615 PINMUX_IRQ(EXT_IRQ16L(14), PORT82_FN0, PORT146_FN0),
1616 PINMUX_IRQ(EXT_IRQ16L(15), PORT83_FN0, PORT147_FN0),
1617 PINMUX_IRQ(EXT_IRQ16H(16), PORT84_FN0, PORT170_FN0),
1618 PINMUX_IRQ(EXT_IRQ16H(17), PORT85_FN0),
1619 PINMUX_IRQ(EXT_IRQ16H(18), PORT86_FN0),
1620 PINMUX_IRQ(EXT_IRQ16H(19), PORT87_FN0),
1621 PINMUX_IRQ(EXT_IRQ16H(20), PORT92_FN0),
1622 PINMUX_IRQ(EXT_IRQ16H(21), PORT93_FN0),
1623 PINMUX_IRQ(EXT_IRQ16H(22), PORT94_FN0),
1624 PINMUX_IRQ(EXT_IRQ16H(23), PORT95_FN0),
1625 PINMUX_IRQ(EXT_IRQ16H(24), PORT112_FN0),
1626 PINMUX_IRQ(EXT_IRQ16H(25), PORT119_FN0),
1627 PINMUX_IRQ(EXT_IRQ16H(26), PORT121_FN0, PORT172_FN0),
1628 PINMUX_IRQ(EXT_IRQ16H(27), PORT122_FN0, PORT180_FN0),
1629 PINMUX_IRQ(EXT_IRQ16H(28), PORT123_FN0, PORT181_FN0),
1630 PINMUX_IRQ(EXT_IRQ16H(29), PORT129_FN0, PORT182_FN0),
1631 PINMUX_IRQ(EXT_IRQ16H(30), PORT130_FN0, PORT183_FN0),
1632 PINMUX_IRQ(EXT_IRQ16H(31), PORT138_FN0, PORT184_FN0),
1633};
1634
1597static struct pinmux_info sh7372_pinmux_info = { 1635static struct pinmux_info sh7372_pinmux_info = {
1598 .name = "sh7372_pfc", 1636 .name = "sh7372_pfc",
1599 .reserved_id = PINMUX_RESERVED, 1637 .reserved_id = PINMUX_RESERVED,
@@ -1614,6 +1652,9 @@ static struct pinmux_info sh7372_pinmux_info = {
1614 1652
1615 .gpio_data = pinmux_data, 1653 .gpio_data = pinmux_data,
1616 .gpio_data_size = ARRAY_SIZE(pinmux_data), 1654 .gpio_data_size = ARRAY_SIZE(pinmux_data),
1655
1656 .gpio_irq = pinmux_irqs,
1657 .gpio_irq_size = ARRAY_SIZE(pinmux_irqs),
1617}; 1658};
1618 1659
1619void sh7372_pinmux_init(void) 1660void sh7372_pinmux_init(void)
diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c
index 6fcf304d3cdf..cccf91b8fae1 100644
--- a/arch/arm/mach-shmobile/setup-sh7372.c
+++ b/arch/arm/mach-shmobile/setup-sh7372.c
@@ -662,6 +662,7 @@ static struct sh_dmae_pdata usb_dma0_platform_data = {
662 .dmaor_is_32bit = 1, 662 .dmaor_is_32bit = 1,
663 .needs_tend_set = 1, 663 .needs_tend_set = 1,
664 .no_dmars = 1, 664 .no_dmars = 1,
665 .slave_only = 1,
665}; 666};
666 667
667static struct resource sh7372_usb_dmae0_resources[] = { 668static struct resource sh7372_usb_dmae0_resources[] = {
@@ -723,6 +724,7 @@ static struct sh_dmae_pdata usb_dma1_platform_data = {
723 .dmaor_is_32bit = 1, 724 .dmaor_is_32bit = 1,
724 .needs_tend_set = 1, 725 .needs_tend_set = 1,
725 .no_dmars = 1, 726 .no_dmars = 1,
727 .slave_only = 1,
726}; 728};
727 729
728static struct resource sh7372_usb_dmae1_resources[] = { 730static struct resource sh7372_usb_dmae1_resources[] = {
@@ -1041,6 +1043,8 @@ void __init sh7372_add_standard_devices(void)
1041 sh7372_add_device_to_domain(&sh7372_a4r, &veu2_device); 1043 sh7372_add_device_to_domain(&sh7372_a4r, &veu2_device);
1042 sh7372_add_device_to_domain(&sh7372_a4r, &veu3_device); 1044 sh7372_add_device_to_domain(&sh7372_a4r, &veu3_device);
1043 sh7372_add_device_to_domain(&sh7372_a4r, &jpu_device); 1045 sh7372_add_device_to_domain(&sh7372_a4r, &jpu_device);
1046 sh7372_add_device_to_domain(&sh7372_a4r, &tmu00_device);
1047 sh7372_add_device_to_domain(&sh7372_a4r, &tmu01_device);
1044} 1048}
1045 1049
1046void __init sh7372_add_early_devices(void) 1050void __init sh7372_add_early_devices(void)
diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c
index cc97ef892d1b..4fe2e9eaf501 100644
--- a/arch/arm/mach-shmobile/smp-r8a7779.c
+++ b/arch/arm/mach-shmobile/smp-r8a7779.c
@@ -25,6 +25,7 @@
25#include <linux/delay.h> 25#include <linux/delay.h>
26#include <mach/common.h> 26#include <mach/common.h>
27#include <mach/r8a7779.h> 27#include <mach/r8a7779.h>
28#include <asm/smp_plat.h>
28#include <asm/smp_scu.h> 29#include <asm/smp_scu.h>
29#include <asm/smp_twd.h> 30#include <asm/smp_twd.h>
30#include <asm/hardware/gic.h> 31#include <asm/hardware/gic.h>
diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c
index be1ade76ccc8..2d0d4212be41 100644
--- a/arch/arm/mach-shmobile/smp-sh73a0.c
+++ b/arch/arm/mach-shmobile/smp-sh73a0.c
@@ -23,6 +23,7 @@
23#include <linux/spinlock.h> 23#include <linux/spinlock.h>
24#include <linux/io.h> 24#include <linux/io.h>
25#include <mach/common.h> 25#include <mach/common.h>
26#include <asm/smp_plat.h>
26#include <asm/smp_scu.h> 27#include <asm/smp_scu.h>
27#include <asm/smp_twd.h> 28#include <asm/smp_twd.h>
28#include <asm/hardware/gic.h> 29#include <asm/hardware/gic.h>
@@ -79,7 +80,7 @@ int __cpuinit sh73a0_boot_secondary(unsigned int cpu)
79 /* enable cache coherency */ 80 /* enable cache coherency */
80 modify_scu_cpu_psr(0, 3 << (cpu * 8)); 81 modify_scu_cpu_psr(0, 3 << (cpu * 8));
81 82
82 if (((__raw_readw(__io(PSTR)) >> (4 * cpu)) & 3) == 3) 83 if (((__raw_readl(__io(PSTR)) >> (4 * cpu)) & 3) == 3)
83 __raw_writel(1 << cpu, __io(WUPCR)); /* wake up */ 84 __raw_writel(1 << cpu, __io(WUPCR)); /* wake up */
84 else 85 else
85 __raw_writel(1 << cpu, __io(SRESCR)); /* reset */ 86 __raw_writel(1 << cpu, __io(SRESCR)); /* reset */
diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c
index a5e46b4ade20..4f7f5182dd4d 100644
--- a/arch/arm/mach-spear3xx/spear300.c
+++ b/arch/arm/mach-spear3xx/spear300.c
@@ -469,7 +469,7 @@ void __init spear300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
469 if (pmx_driver.base) { 469 if (pmx_driver.base) {
470 ret = pmx_register(&pmx_driver); 470 ret = pmx_register(&pmx_driver);
471 if (ret) 471 if (ret)
472 printk(KERN_ERR "padmux: registeration failed. err no" 472 printk(KERN_ERR "padmux: registration failed. err no"
473 ": %d\n", ret); 473 ": %d\n", ret);
474 /* Free Mapping, device selection already done */ 474 /* Free Mapping, device selection already done */
475 iounmap(pmx_driver.base); 475 iounmap(pmx_driver.base);
diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c
index 9004cf9f01bf..febaa6fcfb6a 100644
--- a/arch/arm/mach-spear3xx/spear310.c
+++ b/arch/arm/mach-spear3xx/spear310.c
@@ -303,6 +303,6 @@ void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
303 303
304 ret = pmx_register(&pmx_driver); 304 ret = pmx_register(&pmx_driver);
305 if (ret) 305 if (ret)
306 printk(KERN_ERR "padmux: registeration failed. err no: %d\n", 306 printk(KERN_ERR "padmux: registration failed. err no: %d\n",
307 ret); 307 ret);
308} 308}
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index ee29bef43074..deaaf199612c 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -550,6 +550,6 @@ void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
550 550
551 ret = pmx_register(&pmx_driver); 551 ret = pmx_register(&pmx_driver);
552 if (ret) 552 if (ret)
553 printk(KERN_ERR "padmux: registeration failed. err no: %d\n", 553 printk(KERN_ERR "padmux: registration failed. err no: %d\n",
554 ret); 554 ret);
555} 555}
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 373652d76b90..32b420a90c3d 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -7,6 +7,8 @@ config ARCH_TEGRA_2x_SOC
7 select CPU_V7 7 select CPU_V7
8 select ARM_GIC 8 select ARM_GIC
9 select ARCH_REQUIRE_GPIOLIB 9 select ARCH_REQUIRE_GPIOLIB
10 select PINCTRL
11 select PINCTRL_TEGRA20
10 select USB_ARCH_HAS_EHCI if USB_SUPPORT 12 select USB_ARCH_HAS_EHCI if USB_SUPPORT
11 select USB_ULPI if USB_SUPPORT 13 select USB_ULPI if USB_SUPPORT
12 select USB_ULPI_VIEWPORT if USB_SUPPORT 14 select USB_ULPI_VIEWPORT if USB_SUPPORT
@@ -19,6 +21,8 @@ config ARCH_TEGRA_3x_SOC
19 select CPU_V7 21 select CPU_V7
20 select ARM_GIC 22 select ARM_GIC
21 select ARCH_REQUIRE_GPIOLIB 23 select ARCH_REQUIRE_GPIOLIB
24 select PINCTRL
25 select PINCTRL_TEGRA30
22 select USB_ARCH_HAS_EHCI if USB_SUPPORT 26 select USB_ARCH_HAS_EHCI if USB_SUPPORT
23 select USB_ULPI if USB_SUPPORT 27 select USB_ULPI if USB_SUPPORT
24 select USB_ULPI_VIEWPORT if USB_SUPPORT 28 select USB_ULPI_VIEWPORT if USB_SUPPORT
diff --git a/arch/arm/mach-tegra/board-paz00.c b/arch/arm/mach-tegra/board-paz00.c
index fcf4f377b1dc..330afdfa2475 100644
--- a/arch/arm/mach-tegra/board-paz00.c
+++ b/arch/arm/mach-tegra/board-paz00.c
@@ -60,9 +60,9 @@ static struct plat_serial8250_port debug_uart_platform_data[] = {
60 .uartclk = 216000000, 60 .uartclk = 216000000,
61 }, { 61 }, {
62 /* serial port on mini-pcie */ 62 /* serial port on mini-pcie */
63 .membase = IO_ADDRESS(TEGRA_UARTD_BASE), 63 .membase = IO_ADDRESS(TEGRA_UARTC_BASE),
64 .mapbase = TEGRA_UARTD_BASE, 64 .mapbase = TEGRA_UARTC_BASE,
65 .irq = INT_UARTD, 65 .irq = INT_UARTC,
66 .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE, 66 .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
67 .type = PORT_TEGRA, 67 .type = PORT_TEGRA,
68 .iotype = UPIO_MEM, 68 .iotype = UPIO_MEM,
@@ -174,7 +174,7 @@ static void __init tegra_paz00_fixup(struct tag *tags, char **cmdline,
174static __initdata struct tegra_clk_init_table paz00_clk_init_table[] = { 174static __initdata struct tegra_clk_init_table paz00_clk_init_table[] = {
175 /* name parent rate enabled */ 175 /* name parent rate enabled */
176 { "uarta", "pll_p", 216000000, true }, 176 { "uarta", "pll_p", 216000000, true },
177 { "uartd", "pll_p", 216000000, true }, 177 { "uartc", "pll_p", 216000000, true },
178 178
179 { "pll_p_out4", "pll_p", 24000000, true }, 179 { "pll_p_out4", "pll_p", 24000000, true },
180 { "usbd", "clk_m", 12000000, false }, 180 { "usbd", "clk_m", 12000000, false },
diff --git a/arch/arm/mach-tegra/board-paz00.h b/arch/arm/mach-tegra/board-paz00.h
index ffa83f580db6..3c9f8da37ea3 100644
--- a/arch/arm/mach-tegra/board-paz00.h
+++ b/arch/arm/mach-tegra/board-paz00.h
@@ -22,7 +22,7 @@
22/* SDCARD */ 22/* SDCARD */
23#define TEGRA_GPIO_SD1_CD TEGRA_GPIO_PV5 23#define TEGRA_GPIO_SD1_CD TEGRA_GPIO_PV5
24#define TEGRA_GPIO_SD1_WP TEGRA_GPIO_PH1 24#define TEGRA_GPIO_SD1_WP TEGRA_GPIO_PH1
25#define TEGRA_GPIO_SD1_POWER TEGRA_GPIO_PT3 25#define TEGRA_GPIO_SD1_POWER TEGRA_GPIO_PV1
26 26
27/* ULPI */ 27/* ULPI */
28#define TEGRA_ULPI_RST TEGRA_GPIO_PV0 28#define TEGRA_ULPI_RST TEGRA_GPIO_PV0
diff --git a/arch/arm/mach-tegra/fuse.c b/arch/arm/mach-tegra/fuse.c
index 1fa26d9a1a68..ea49bd93c6b9 100644
--- a/arch/arm/mach-tegra/fuse.c
+++ b/arch/arm/mach-tegra/fuse.c
@@ -19,6 +19,7 @@
19 19
20#include <linux/kernel.h> 20#include <linux/kernel.h>
21#include <linux/io.h> 21#include <linux/io.h>
22#include <linux/module.h>
22 23
23#include <mach/iomap.h> 24#include <mach/iomap.h>
24 25
@@ -58,6 +59,7 @@ unsigned long long tegra_chip_uid(void)
58 hi = fuse_readl(FUSE_UID_HIGH); 59 hi = fuse_readl(FUSE_UID_HIGH);
59 return (hi << 32ull) | lo; 60 return (hi << 32ull) | lo;
60} 61}
62EXPORT_SYMBOL(tegra_chip_uid);
61 63
62int tegra_sku_id(void) 64int tegra_sku_id(void)
63{ 65{
diff --git a/arch/arm/mach-tegra/include/mach/dma.h b/arch/arm/mach-tegra/include/mach/dma.h
index d0132e8031a1..3c9339058bec 100644
--- a/arch/arm/mach-tegra/include/mach/dma.h
+++ b/arch/arm/mach-tegra/include/mach/dma.h
@@ -23,11 +23,6 @@
23 23
24#include <linux/list.h> 24#include <linux/list.h>
25 25
26#if defined(CONFIG_TEGRA_SYSTEM_DMA)
27
28struct tegra_dma_req;
29struct tegra_dma_channel;
30
31#define TEGRA_DMA_REQ_SEL_CNTR 0 26#define TEGRA_DMA_REQ_SEL_CNTR 0
32#define TEGRA_DMA_REQ_SEL_I2S_2 1 27#define TEGRA_DMA_REQ_SEL_I2S_2 1
33#define TEGRA_DMA_REQ_SEL_I2S_1 2 28#define TEGRA_DMA_REQ_SEL_I2S_1 2
@@ -56,6 +51,11 @@ struct tegra_dma_channel;
56#define TEGRA_DMA_REQ_SEL_OWR 25 51#define TEGRA_DMA_REQ_SEL_OWR 25
57#define TEGRA_DMA_REQ_SEL_INVALID 31 52#define TEGRA_DMA_REQ_SEL_INVALID 31
58 53
54#if defined(CONFIG_TEGRA_SYSTEM_DMA)
55
56struct tegra_dma_req;
57struct tegra_dma_channel;
58
59enum tegra_dma_mode { 59enum tegra_dma_mode {
60 TEGRA_DMA_SHARED = 1, 60 TEGRA_DMA_SHARED = 1,
61 TEGRA_DMA_MODE_CONTINOUS = 2, 61 TEGRA_DMA_MODE_CONTINOUS = 2,
diff --git a/arch/arm/mach-tegra/include/mach/kbc.h b/arch/arm/mach-tegra/include/mach/kbc.h
index 20bb0545f992..a13025612939 100644
--- a/arch/arm/mach-tegra/include/mach/kbc.h
+++ b/arch/arm/mach-tegra/include/mach/kbc.h
@@ -24,20 +24,21 @@
24#include <linux/types.h> 24#include <linux/types.h>
25#include <linux/input/matrix_keypad.h> 25#include <linux/input/matrix_keypad.h>
26 26
27#ifdef CONFIG_ARCH_TEGRA_2x_SOC
28#define KBC_MAX_GPIO 24 27#define KBC_MAX_GPIO 24
29#define KBC_MAX_KPENT 8 28#define KBC_MAX_KPENT 8
30#else
31#define KBC_MAX_GPIO 20
32#define KBC_MAX_KPENT 7
33#endif
34 29
35#define KBC_MAX_ROW 16 30#define KBC_MAX_ROW 16
36#define KBC_MAX_COL 8 31#define KBC_MAX_COL 8
37#define KBC_MAX_KEY (KBC_MAX_ROW * KBC_MAX_COL) 32#define KBC_MAX_KEY (KBC_MAX_ROW * KBC_MAX_COL)
38 33
34enum tegra_pin_type {
35 PIN_CFG_IGNORE,
36 PIN_CFG_COL,
37 PIN_CFG_ROW,
38};
39
39struct tegra_kbc_pin_cfg { 40struct tegra_kbc_pin_cfg {
40 bool is_row; 41 enum tegra_pin_type type;
41 unsigned char num; 42 unsigned char num;
42}; 43};
43 44
diff --git a/arch/arm/mach-tegra/include/mach/pinconf-tegra.h b/arch/arm/mach-tegra/include/mach/pinconf-tegra.h
new file mode 100644
index 000000000000..1f24d304921e
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/pinconf-tegra.h
@@ -0,0 +1,63 @@
1/*
2 * pinctrl configuration definitions for the NVIDIA Tegra pinmux
3 *
4 * Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#ifndef __PINCONF_TEGRA_H__
17#define __PINCONF_TEGRA_H__
18
19enum tegra_pinconf_param {
20 /* argument: tegra_pinconf_pull */
21 TEGRA_PINCONF_PARAM_PULL,
22 /* argument: tegra_pinconf_tristate */
23 TEGRA_PINCONF_PARAM_TRISTATE,
24 /* argument: Boolean */
25 TEGRA_PINCONF_PARAM_ENABLE_INPUT,
26 /* argument: Boolean */
27 TEGRA_PINCONF_PARAM_OPEN_DRAIN,
28 /* argument: Boolean */
29 TEGRA_PINCONF_PARAM_LOCK,
30 /* argument: Boolean */
31 TEGRA_PINCONF_PARAM_IORESET,
32 /* argument: Boolean */
33 TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE,
34 /* argument: Boolean */
35 TEGRA_PINCONF_PARAM_SCHMITT,
36 /* argument: Boolean */
37 TEGRA_PINCONF_PARAM_LOW_POWER_MODE,
38 /* argument: Integer, range is HW-dependant */
39 TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH,
40 /* argument: Integer, range is HW-dependant */
41 TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH,
42 /* argument: Integer, range is HW-dependant */
43 TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING,
44 /* argument: Integer, range is HW-dependant */
45 TEGRA_PINCONF_PARAM_SLEW_RATE_RISING,
46};
47
48enum tegra_pinconf_pull {
49 TEGRA_PINCONFIG_PULL_NONE,
50 TEGRA_PINCONFIG_PULL_DOWN,
51 TEGRA_PINCONFIG_PULL_UP,
52};
53
54enum tegra_pinconf_tristate {
55 TEGRA_PINCONFIG_DRIVEN,
56 TEGRA_PINCONFIG_TRISTATE,
57};
58
59#define TEGRA_PINCONF_PACK(_param_, _arg_) ((_param_) << 16 | (_arg_))
60#define TEGRA_PINCONF_UNPACK_PARAM(_conf_) ((_conf_) >> 16)
61#define TEGRA_PINCONF_UNPACK_ARG(_conf_) ((_conf_) & 0xffff)
62
63#endif
diff --git a/arch/arm/mach-tegra/include/mach/usb_phy.h b/arch/arm/mach-tegra/include/mach/usb_phy.h
index d4b8f9e298a8..de1a0f602b28 100644
--- a/arch/arm/mach-tegra/include/mach/usb_phy.h
+++ b/arch/arm/mach-tegra/include/mach/usb_phy.h
@@ -58,7 +58,7 @@ struct tegra_usb_phy {
58 struct clk *pad_clk; 58 struct clk *pad_clk;
59 enum tegra_usb_phy_mode mode; 59 enum tegra_usb_phy_mode mode;
60 void *config; 60 void *config;
61 struct otg_transceiver *ulpi; 61 struct usb_phy *ulpi;
62}; 62};
63 63
64struct tegra_usb_phy *tegra_usb_phy_open(int instance, void __iomem *regs, 64struct tegra_usb_phy *tegra_usb_phy_open(int instance, void __iomem *regs,
diff --git a/arch/arm/mach-tegra/usb_phy.c b/arch/arm/mach-tegra/usb_phy.c
index 37576a721aeb..ad321f9e2bb8 100644
--- a/arch/arm/mach-tegra/usb_phy.c
+++ b/arch/arm/mach-tegra/usb_phy.c
@@ -608,13 +608,13 @@ static int ulpi_phy_power_on(struct tegra_usb_phy *phy)
608 writel(val, base + ULPI_TIMING_CTRL_1); 608 writel(val, base + ULPI_TIMING_CTRL_1);
609 609
610 /* Fix VbusInvalid due to floating VBUS */ 610 /* Fix VbusInvalid due to floating VBUS */
611 ret = otg_io_write(phy->ulpi, 0x40, 0x08); 611 ret = usb_phy_io_write(phy->ulpi, 0x40, 0x08);
612 if (ret) { 612 if (ret) {
613 pr_err("%s: ulpi write failed\n", __func__); 613 pr_err("%s: ulpi write failed\n", __func__);
614 return ret; 614 return ret;
615 } 615 }
616 616
617 ret = otg_io_write(phy->ulpi, 0x80, 0x0B); 617 ret = usb_phy_io_write(phy->ulpi, 0x80, 0x0B);
618 if (ret) { 618 if (ret) {
619 pr_err("%s: ulpi write failed\n", __func__); 619 pr_err("%s: ulpi write failed\n", __func__);
620 return ret; 620 return ret;
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index b4c6926a700c..a7b3f36e2262 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -26,7 +26,8 @@
26#include <linux/mtd/nand.h> 26#include <linux/mtd/nand.h>
27#include <linux/mtd/fsmc.h> 27#include <linux/mtd/fsmc.h>
28#include <linux/pinctrl/machine.h> 28#include <linux/pinctrl/machine.h>
29#include <linux/pinctrl/pinmux.h> 29#include <linux/pinctrl/consumer.h>
30#include <linux/pinctrl/pinconf-generic.h>
30#include <linux/dma-mapping.h> 31#include <linux/dma-mapping.h>
31 32
32#include <asm/types.h> 33#include <asm/types.h>
@@ -1477,7 +1478,7 @@ static struct coh901318_platform coh901318_platform = {
1477 .max_channels = U300_DMA_CHANNELS, 1478 .max_channels = U300_DMA_CHANNELS,
1478}; 1479};
1479 1480
1480static struct resource pinmux_resources[] = { 1481static struct resource pinctrl_resources[] = {
1481 { 1482 {
1482 .start = U300_SYSCON_BASE, 1483 .start = U300_SYSCON_BASE,
1483 .end = U300_SYSCON_BASE + SZ_4K - 1, 1484 .end = U300_SYSCON_BASE + SZ_4K - 1,
@@ -1506,6 +1507,13 @@ static struct platform_device i2c1_device = {
1506 .resource = i2c1_resources, 1507 .resource = i2c1_resources,
1507}; 1508};
1508 1509
1510static struct platform_device pinctrl_device = {
1511 .name = "pinctrl-u300",
1512 .id = -1,
1513 .num_resources = ARRAY_SIZE(pinctrl_resources),
1514 .resource = pinctrl_resources,
1515};
1516
1509/* 1517/*
1510 * The different variants have a few different versions of the 1518 * The different variants have a few different versions of the
1511 * GPIO block, with different number of ports. 1519 * GPIO block, with different number of ports.
@@ -1525,6 +1533,7 @@ static struct u300_gpio_platform u300_gpio_plat = {
1525#endif 1533#endif
1526 .gpio_base = 0, 1534 .gpio_base = 0,
1527 .gpio_irq_base = IRQ_U300_GPIO_BASE, 1535 .gpio_irq_base = IRQ_U300_GPIO_BASE,
1536 .pinctrl_device = &pinctrl_device,
1528}; 1537};
1529 1538
1530static struct platform_device gpio_device = { 1539static struct platform_device gpio_device = {
@@ -1597,71 +1606,67 @@ static struct platform_device dma_device = {
1597 }, 1606 },
1598}; 1607};
1599 1608
1600static struct platform_device pinmux_device = { 1609static unsigned long pin_pullup_conf[] = {
1601 .name = "pinmux-u300", 1610 PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 1),
1602 .id = -1,
1603 .num_resources = ARRAY_SIZE(pinmux_resources),
1604 .resource = pinmux_resources,
1605}; 1611};
1606 1612
1607/* Pinmux settings */ 1613static unsigned long pin_highz_conf[] = {
1608static struct pinmux_map __initdata u300_pinmux_map[] = { 1614 PIN_CONF_PACKED(PIN_CONFIG_BIAS_HIGH_IMPEDANCE, 0),
1615};
1616
1617/* Pin control settings */
1618static struct pinctrl_map __initdata u300_pinmux_map[] = {
1609 /* anonymous maps for chip power and EMIFs */ 1619 /* anonymous maps for chip power and EMIFs */
1610 PINMUX_MAP_SYS_HOG("POWER", "pinmux-u300", "power"), 1620 PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-u300", NULL, "power"),
1611 PINMUX_MAP_SYS_HOG("EMIF0", "pinmux-u300", "emif0"), 1621 PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-u300", NULL, "emif0"),
1612 PINMUX_MAP_SYS_HOG("EMIF1", "pinmux-u300", "emif1"), 1622 PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-u300", NULL, "emif1"),
1613 /* per-device maps for MMC/SD, SPI and UART */ 1623 /* per-device maps for MMC/SD, SPI and UART */
1614 PINMUX_MAP("MMCSD", "pinmux-u300", "mmc0", "mmci"), 1624 PIN_MAP_MUX_GROUP_DEFAULT("mmci", "pinctrl-u300", NULL, "mmc0"),
1615 PINMUX_MAP("SPI", "pinmux-u300", "spi0", "pl022"), 1625 PIN_MAP_MUX_GROUP_DEFAULT("pl022", "pinctrl-u300", NULL, "spi0"),
1616 PINMUX_MAP("UART0", "pinmux-u300", "uart0", "uart0"), 1626 PIN_MAP_MUX_GROUP_DEFAULT("uart0", "pinctrl-u300", NULL, "uart0"),
1627 /* This pin is used for clock return rather than GPIO */
1628 PIN_MAP_CONFIGS_PIN_DEFAULT("mmci", "pinctrl-u300", "PIO APP GPIO 11",
1629 pin_pullup_conf),
1630 /* This pin is used for card detect */
1631 PIN_MAP_CONFIGS_PIN_DEFAULT("mmci", "pinctrl-u300", "PIO MS INS",
1632 pin_highz_conf),
1617}; 1633};
1618 1634
1619struct u300_mux_hog { 1635struct u300_mux_hog {
1620 const char *name;
1621 struct device *dev; 1636 struct device *dev;
1622 struct pinmux *pmx; 1637 struct pinctrl *p;
1623}; 1638};
1624 1639
1625static struct u300_mux_hog u300_mux_hogs[] = { 1640static struct u300_mux_hog u300_mux_hogs[] = {
1626 { 1641 {
1627 .name = "uart0",
1628 .dev = &uart0_device.dev, 1642 .dev = &uart0_device.dev,
1629 }, 1643 },
1630 { 1644 {
1631 .name = "spi0",
1632 .dev = &pl022_device.dev, 1645 .dev = &pl022_device.dev,
1633 }, 1646 },
1634 { 1647 {
1635 .name = "mmc0",
1636 .dev = &mmcsd_device.dev, 1648 .dev = &mmcsd_device.dev,
1637 }, 1649 },
1638}; 1650};
1639 1651
1640static int __init u300_pinmux_fetch(void) 1652static int __init u300_pinctrl_fetch(void)
1641{ 1653{
1642 int i; 1654 int i;
1643 1655
1644 for (i = 0; i < ARRAY_SIZE(u300_mux_hogs); i++) { 1656 for (i = 0; i < ARRAY_SIZE(u300_mux_hogs); i++) {
1645 struct pinmux *pmx; 1657 struct pinctrl *p;
1646 int ret;
1647 1658
1648 pmx = pinmux_get(u300_mux_hogs[i].dev, NULL); 1659 p = pinctrl_get_select_default(u300_mux_hogs[i].dev);
1649 if (IS_ERR(pmx)) { 1660 if (IS_ERR(p)) {
1650 pr_err("u300: could not get pinmux hog %s\n", 1661 pr_err("u300: could not get pinmux hog for dev %s\n",
1651 u300_mux_hogs[i].name); 1662 dev_name(u300_mux_hogs[i].dev));
1652 continue;
1653 }
1654 ret = pinmux_enable(pmx);
1655 if (ret) {
1656 pr_err("u300: could enable pinmux hog %s\n",
1657 u300_mux_hogs[i].name);
1658 continue; 1663 continue;
1659 } 1664 }
1660 u300_mux_hogs[i].pmx = pmx; 1665 u300_mux_hogs[i].p = p;
1661 } 1666 }
1662 return 0; 1667 return 0;
1663} 1668}
1664subsys_initcall(u300_pinmux_fetch); 1669subsys_initcall(u300_pinctrl_fetch);
1665 1670
1666/* 1671/*
1667 * Notice that AMBA devices are initialized before platform devices. 1672 * Notice that AMBA devices are initialized before platform devices.
@@ -1676,7 +1681,6 @@ static struct platform_device *platform_devs[] __initdata = {
1676 &gpio_device, 1681 &gpio_device,
1677 &nand_device, 1682 &nand_device,
1678 &wdog_device, 1683 &wdog_device,
1679 &pinmux_device,
1680}; 1684};
1681 1685
1682/* 1686/*
@@ -1861,8 +1865,8 @@ void __init u300_init_devices(void)
1861 u300_assign_physmem(); 1865 u300_assign_physmem();
1862 1866
1863 /* Initialize pinmuxing */ 1867 /* Initialize pinmuxing */
1864 pinmux_register_mappings(u300_pinmux_map, 1868 pinctrl_register_mappings(u300_pinmux_map,
1865 ARRAY_SIZE(u300_pinmux_map)); 1869 ARRAY_SIZE(u300_pinmux_map));
1866 1870
1867 /* Register subdevices on the I2C buses */ 1871 /* Register subdevices on the I2C buses */
1868 u300_i2c_register_board_devices(); 1872 u300_i2c_register_board_devices();
diff --git a/arch/arm/mach-u300/i2c.c b/arch/arm/mach-u300/i2c.c
index 5140deeddf7b..a38f80238ea9 100644
--- a/arch/arm/mach-u300/i2c.c
+++ b/arch/arm/mach-u300/i2c.c
@@ -60,7 +60,6 @@ static struct regulator_consumer_supply supply_ldo_c[] = {
60 */ 60 */
61static struct regulator_consumer_supply supply_ldo_d[] = { 61static struct regulator_consumer_supply supply_ldo_d[] = {
62 { 62 {
63 .dev = NULL,
64 .supply = "vana15", /* Powers the SoC (CPU etc) */ 63 .supply = "vana15", /* Powers the SoC (CPU etc) */
65 }, 64 },
66}; 65};
@@ -92,7 +91,6 @@ static struct regulator_consumer_supply supply_ldo_k[] = {
92 */ 91 */
93static struct regulator_consumer_supply supply_ldo_ext[] = { 92static struct regulator_consumer_supply supply_ldo_ext[] = {
94 { 93 {
95 .dev = NULL,
96 .supply = "vext", /* External power */ 94 .supply = "vext", /* External power */
97 }, 95 },
98}; 96};
diff --git a/arch/arm/mach-u300/include/mach/gpio-u300.h b/arch/arm/mach-u300/include/mach/gpio-u300.h
index bf4c7935aecd..e81400c1753a 100644
--- a/arch/arm/mach-u300/include/mach/gpio-u300.h
+++ b/arch/arm/mach-u300/include/mach/gpio-u300.h
@@ -24,12 +24,14 @@ enum u300_gpio_variant {
24 * @ports: number of GPIO block ports 24 * @ports: number of GPIO block ports
25 * @gpio_base: first GPIO number for this block (use a free range) 25 * @gpio_base: first GPIO number for this block (use a free range)
26 * @gpio_irq_base: first GPIO IRQ number for this block (use a free range) 26 * @gpio_irq_base: first GPIO IRQ number for this block (use a free range)
27 * @pinctrl_device: pin control device to spawn as child
27 */ 28 */
28struct u300_gpio_platform { 29struct u300_gpio_platform {
29 enum u300_gpio_variant variant; 30 enum u300_gpio_variant variant;
30 u8 ports; 31 u8 ports;
31 int gpio_base; 32 int gpio_base;
32 int gpio_irq_base; 33 int gpio_irq_base;
34 struct platform_device *pinctrl_device;
33}; 35};
34 36
35#endif /* __MACH_U300_GPIO_U300_H */ 37#endif /* __MACH_U300_GPIO_U300_H */
diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
index a3e0c8692f0d..c59e8b892d6b 100644
--- a/arch/arm/mach-ux500/Kconfig
+++ b/arch/arm/mach-ux500/Kconfig
@@ -5,8 +5,9 @@ config UX500_SOC_COMMON
5 default y 5 default y
6 select ARM_GIC 6 select ARM_GIC
7 select HAS_MTU 7 select HAS_MTU
8 select ARM_ERRATA_753970 8 select PL310_ERRATA_753970
9 select ARM_ERRATA_754322 9 select ARM_ERRATA_754322
10 select ARM_ERRATA_764369
10 11
11menu "Ux500 SoC" 12menu "Ux500 SoC"
12 13
diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c
index 23be34b3bb6e..5dde4d4ebe88 100644
--- a/arch/arm/mach-ux500/board-mop500-sdi.c
+++ b/arch/arm/mach-ux500/board-mop500-sdi.c
@@ -261,6 +261,8 @@ void __init mop500_sdi_init(void)
261 261
262void __init snowball_sdi_init(void) 262void __init snowball_sdi_init(void)
263{ 263{
264 /* On Snowball MMC_CAP_SD_HIGHSPEED isn't supported (Hardware issue?) */
265 mop500_sdi0_data.capabilities &= ~MMC_CAP_SD_HIGHSPEED;
264 /* On-board eMMC */ 266 /* On-board eMMC */
265 db8500_add_sdi4(&mop500_sdi4_data, U8500_SDI_V2_PERIPHID); 267 db8500_add_sdi4(&mop500_sdi4_data, U8500_SDI_V2_PERIPHID);
266 /* External Micro SD slot */ 268 /* External Micro SD slot */
diff --git a/arch/arm/mach-ux500/cache-l2x0.c b/arch/arm/mach-ux500/cache-l2x0.c
index 122ddde00ba7..da5569d83d58 100644
--- a/arch/arm/mach-ux500/cache-l2x0.c
+++ b/arch/arm/mach-ux500/cache-l2x0.c
@@ -12,44 +12,6 @@
12 12
13static void __iomem *l2x0_base; 13static void __iomem *l2x0_base;
14 14
15static inline void ux500_cache_wait(void __iomem *reg, unsigned long mask)
16{
17 /* wait for the operation to complete */
18 while (readl_relaxed(reg) & mask)
19 cpu_relax();
20}
21
22static inline void ux500_cache_sync(void)
23{
24 writel_relaxed(0, l2x0_base + L2X0_CACHE_SYNC);
25 ux500_cache_wait(l2x0_base + L2X0_CACHE_SYNC, 1);
26}
27
28/*
29 * The L2 cache cannot be turned off in the non-secure world.
30 * Dummy until a secure service is in place.
31 */
32static void ux500_l2x0_disable(void)
33{
34}
35
36/*
37 * This is only called when doing a kexec, just after turning off the L2
38 * and L1 cache, and it is surrounded by a spinlock in the generic version.
39 * However, we're not really turning off the L2 cache right now and the
40 * PL310 does not support exclusive accesses (used to implement the spinlock).
41 * So, the invalidation needs to be done without the spinlock.
42 */
43static void ux500_l2x0_inv_all(void)
44{
45 uint32_t l2x0_way_mask = (1<<16) - 1; /* Bitmask of active ways */
46
47 /* invalidate all ways */
48 writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_INV_WAY);
49 ux500_cache_wait(l2x0_base + L2X0_INV_WAY, l2x0_way_mask);
50 ux500_cache_sync();
51}
52
53static int __init ux500_l2x0_unlock(void) 15static int __init ux500_l2x0_unlock(void)
54{ 16{
55 int i; 17 int i;
@@ -85,9 +47,13 @@ static int __init ux500_l2x0_init(void)
85 /* 64KB way size, 8 way associativity, force WA */ 47 /* 64KB way size, 8 way associativity, force WA */
86 l2x0_init(l2x0_base, 0x3e060000, 0xc0000fff); 48 l2x0_init(l2x0_base, 0x3e060000, 0xc0000fff);
87 49
88 /* Override invalidate function */ 50 /*
89 outer_cache.disable = ux500_l2x0_disable; 51 * We can't disable l2 as we are in non secure mode, currently
90 outer_cache.inv_all = ux500_l2x0_inv_all; 52 * this seems be called only during kexec path. So let's
53 * override outer.disable with nasty assignment until we have
54 * some SMI service available.
55 */
56 outer_cache.disable = NULL;
91 57
92 return 0; 58 return 0;
93} 59}
diff --git a/arch/arm/mach-ux500/hotplug.c b/arch/arm/mach-ux500/hotplug.c
index 572015e57cd9..c76f0f456f04 100644
--- a/arch/arm/mach-ux500/hotplug.c
+++ b/arch/arm/mach-ux500/hotplug.c
@@ -13,6 +13,7 @@
13#include <linux/smp.h> 13#include <linux/smp.h>
14 14
15#include <asm/cacheflush.h> 15#include <asm/cacheflush.h>
16#include <asm/smp_plat.h>
16 17
17extern volatile int pen_release; 18extern volatile int pen_release;
18 19
diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c
index a19e398dade3..d2058ef8345f 100644
--- a/arch/arm/mach-ux500/platsmp.c
+++ b/arch/arm/mach-ux500/platsmp.c
@@ -19,6 +19,7 @@
19 19
20#include <asm/cacheflush.h> 20#include <asm/cacheflush.h>
21#include <asm/hardware/gic.h> 21#include <asm/hardware/gic.h>
22#include <asm/smp_plat.h>
22#include <asm/smp_scu.h> 23#include <asm/smp_scu.h>
23#include <mach/hardware.h> 24#include <mach/hardware.h>
24#include <mach/setup.h> 25#include <mach/setup.h>
diff --git a/arch/arm/mach-ux500/usb.c b/arch/arm/mach-ux500/usb.c
index 0a01cbdfe063..9f9e1c203061 100644
--- a/arch/arm/mach-ux500/usb.c
+++ b/arch/arm/mach-ux500/usb.c
@@ -95,13 +95,7 @@ static struct musb_hdrc_config musb_hdrc_config = {
95}; 95};
96 96
97static struct musb_hdrc_platform_data musb_platform_data = { 97static struct musb_hdrc_platform_data musb_platform_data = {
98#if defined(CONFIG_USB_MUSB_OTG)
99 .mode = MUSB_OTG, 98 .mode = MUSB_OTG,
100#elif defined(CONFIG_USB_MUSB_PERIPHERAL)
101 .mode = MUSB_PERIPHERAL,
102#else /* defined(CONFIG_USB_MUSB_HOST) */
103 .mode = MUSB_HOST,
104#endif
105 .config = &musb_hdrc_config, 99 .config = &musb_hdrc_config,
106 .board_data = &musb_board_data, 100 .board_data = &musb_board_data,
107}; 101};
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index 02b7b9303f3b..008ce22b9a06 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -98,8 +98,11 @@ static const struct of_device_id sic_of_match[] __initconst = {
98 98
99void __init versatile_init_irq(void) 99void __init versatile_init_irq(void)
100{ 100{
101 vic_init(VA_VIC_BASE, IRQ_VIC_START, ~0, 0); 101 struct device_node *np;
102 irq_domain_generate_simple(vic_of_match, VERSATILE_VIC_BASE, IRQ_VIC_START); 102
103 np = of_find_matching_node_by_address(NULL, vic_of_match,
104 VERSATILE_VIC_BASE);
105 __vic_init(VA_VIC_BASE, IRQ_VIC_START, ~0, 0, np);
103 106
104 writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR); 107 writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
105 108
diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig
index 9b3d0fbaee72..88c3ba151e87 100644
--- a/arch/arm/mach-vexpress/Kconfig
+++ b/arch/arm/mach-vexpress/Kconfig
@@ -7,7 +7,7 @@ config ARCH_VEXPRESS_CA9X4
7 select ARM_GIC 7 select ARM_GIC
8 select ARM_ERRATA_720789 8 select ARM_ERRATA_720789
9 select ARM_ERRATA_751472 9 select ARM_ERRATA_751472
10 select ARM_ERRATA_753970 10 select PL310_ERRATA_753970
11 select HAVE_SMP 11 select HAVE_SMP
12 select MIGHT_HAVE_CACHE_L2X0 12 select MIGHT_HAVE_CACHE_L2X0
13 13
diff --git a/arch/arm/mach-vexpress/ct-ca9x4.c b/arch/arm/mach-vexpress/ct-ca9x4.c
index 2b1e836a76ed..b1e87c184e54 100644
--- a/arch/arm/mach-vexpress/ct-ca9x4.c
+++ b/arch/arm/mach-vexpress/ct-ca9x4.c
@@ -217,7 +217,7 @@ static void __init ct_ca9x4_init(void)
217} 217}
218 218
219#ifdef CONFIG_SMP 219#ifdef CONFIG_SMP
220static void ct_ca9x4_init_cpu_map(void) 220static void __init ct_ca9x4_init_cpu_map(void)
221{ 221{
222 int i, ncores = scu_get_core_count(MMIO_P2V(A9_MPCORE_SCU)); 222 int i, ncores = scu_get_core_count(MMIO_P2V(A9_MPCORE_SCU));
223 223
@@ -233,7 +233,7 @@ static void ct_ca9x4_init_cpu_map(void)
233 set_smp_cross_call(gic_raise_softirq); 233 set_smp_cross_call(gic_raise_softirq);
234} 234}
235 235
236static void ct_ca9x4_smp_enable(unsigned int max_cpus) 236static void __init ct_ca9x4_smp_enable(unsigned int max_cpus)
237{ 237{
238 scu_enable(MMIO_P2V(A9_MPCORE_SCU)); 238 scu_enable(MMIO_P2V(A9_MPCORE_SCU));
239} 239}
diff --git a/arch/arm/mach-vexpress/hotplug.c b/arch/arm/mach-vexpress/hotplug.c
index 813ee08f96e6..3034a4dab4a1 100644
--- a/arch/arm/mach-vexpress/hotplug.c
+++ b/arch/arm/mach-vexpress/hotplug.c
@@ -13,6 +13,7 @@
13#include <linux/smp.h> 13#include <linux/smp.h>
14 14
15#include <asm/cacheflush.h> 15#include <asm/cacheflush.h>
16#include <asm/smp_plat.h>
16#include <asm/system.h> 17#include <asm/system.h>
17 18
18extern volatile int pen_release; 19extern volatile int pen_release;
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 4cefb57d9ed2..7edef9121632 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -631,7 +631,8 @@ comment "Processor Features"
631 631
632config ARM_LPAE 632config ARM_LPAE
633 bool "Support for the Large Physical Address Extension" 633 bool "Support for the Large Physical Address Extension"
634 depends on MMU && CPU_V7 634 depends on MMU && CPU_32v7 && !CPU_32v6 && !CPU_32v5 && \
635 !CPU_32v4 && !CPU_32v3
635 help 636 help
636 Say Y if you have an ARMv7 processor supporting the LPAE page 637 Say Y if you have an ARMv7 processor supporting the LPAE page
637 table format and you would like to access memory beyond the 638 table format and you would like to access memory beyond the
@@ -882,6 +883,7 @@ config CACHE_XSC3L2
882 883
883config ARM_L1_CACHE_SHIFT_6 884config ARM_L1_CACHE_SHIFT_6
884 bool 885 bool
886 default y if CPU_V7
885 help 887 help
886 Setting ARM L1 cache line size to 64 Bytes. 888 Setting ARM L1 cache line size to 64 Bytes.
887 889
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index 07c4bc8ea0a4..a655d3da386d 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -54,9 +54,15 @@ loop1:
54 and r1, r1, #7 @ mask of the bits for current cache only 54 and r1, r1, #7 @ mask of the bits for current cache only
55 cmp r1, #2 @ see what cache we have at this level 55 cmp r1, #2 @ see what cache we have at this level
56 blt skip @ skip if no cache, or just i-cache 56 blt skip @ skip if no cache, or just i-cache
57#ifdef CONFIG_PREEMPT
58 save_and_disable_irqs_notrace r9 @ make cssr&csidr read atomic
59#endif
57 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr 60 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
58 isb @ isb to sych the new cssr&csidr 61 isb @ isb to sych the new cssr&csidr
59 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr 62 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
63#ifdef CONFIG_PREEMPT
64 restore_irqs_notrace r9
65#endif
60 and r2, r1, #7 @ extract the length of the cache lines 66 and r2, r1, #7 @ extract the length of the cache lines
61 add r2, r2, #4 @ add 4 (line length offset) 67 add r2, r2, #4 @ add 4 (line length offset)
62 ldr r4, =0x3ff 68 ldr r4, =0x3ff
diff --git a/arch/arm/mm/copypage-fa.c b/arch/arm/mm/copypage-fa.c
index d2852e1635b1..d130a5ece5d5 100644
--- a/arch/arm/mm/copypage-fa.c
+++ b/arch/arm/mm/copypage-fa.c
@@ -44,11 +44,11 @@ void fa_copy_user_highpage(struct page *to, struct page *from,
44{ 44{
45 void *kto, *kfrom; 45 void *kto, *kfrom;
46 46
47 kto = kmap_atomic(to, KM_USER0); 47 kto = kmap_atomic(to);
48 kfrom = kmap_atomic(from, KM_USER1); 48 kfrom = kmap_atomic(from);
49 fa_copy_user_page(kto, kfrom); 49 fa_copy_user_page(kto, kfrom);
50 kunmap_atomic(kfrom, KM_USER1); 50 kunmap_atomic(kfrom);
51 kunmap_atomic(kto, KM_USER0); 51 kunmap_atomic(kto);
52} 52}
53 53
54/* 54/*
@@ -58,7 +58,7 @@ void fa_copy_user_highpage(struct page *to, struct page *from,
58 */ 58 */
59void fa_clear_user_highpage(struct page *page, unsigned long vaddr) 59void fa_clear_user_highpage(struct page *page, unsigned long vaddr)
60{ 60{
61 void *ptr, *kaddr = kmap_atomic(page, KM_USER0); 61 void *ptr, *kaddr = kmap_atomic(page);
62 asm volatile("\ 62 asm volatile("\
63 mov r1, %2 @ 1\n\ 63 mov r1, %2 @ 1\n\
64 mov r2, #0 @ 1\n\ 64 mov r2, #0 @ 1\n\
@@ -77,7 +77,7 @@ void fa_clear_user_highpage(struct page *page, unsigned long vaddr)
77 : "=r" (ptr) 77 : "=r" (ptr)
78 : "0" (kaddr), "I" (PAGE_SIZE / 32) 78 : "0" (kaddr), "I" (PAGE_SIZE / 32)
79 : "r1", "r2", "r3", "ip", "lr"); 79 : "r1", "r2", "r3", "ip", "lr");
80 kunmap_atomic(kaddr, KM_USER0); 80 kunmap_atomic(kaddr);
81} 81}
82 82
83struct cpu_user_fns fa_user_fns __initdata = { 83struct cpu_user_fns fa_user_fns __initdata = {
diff --git a/arch/arm/mm/copypage-feroceon.c b/arch/arm/mm/copypage-feroceon.c
index ac163de7dc01..49ee0c1a7209 100644
--- a/arch/arm/mm/copypage-feroceon.c
+++ b/arch/arm/mm/copypage-feroceon.c
@@ -72,17 +72,17 @@ void feroceon_copy_user_highpage(struct page *to, struct page *from,
72{ 72{
73 void *kto, *kfrom; 73 void *kto, *kfrom;
74 74
75 kto = kmap_atomic(to, KM_USER0); 75 kto = kmap_atomic(to);
76 kfrom = kmap_atomic(from, KM_USER1); 76 kfrom = kmap_atomic(from);
77 flush_cache_page(vma, vaddr, page_to_pfn(from)); 77 flush_cache_page(vma, vaddr, page_to_pfn(from));
78 feroceon_copy_user_page(kto, kfrom); 78 feroceon_copy_user_page(kto, kfrom);
79 kunmap_atomic(kfrom, KM_USER1); 79 kunmap_atomic(kfrom);
80 kunmap_atomic(kto, KM_USER0); 80 kunmap_atomic(kto);
81} 81}
82 82
83void feroceon_clear_user_highpage(struct page *page, unsigned long vaddr) 83void feroceon_clear_user_highpage(struct page *page, unsigned long vaddr)
84{ 84{
85 void *ptr, *kaddr = kmap_atomic(page, KM_USER0); 85 void *ptr, *kaddr = kmap_atomic(page);
86 asm volatile ("\ 86 asm volatile ("\
87 mov r1, %2 \n\ 87 mov r1, %2 \n\
88 mov r2, #0 \n\ 88 mov r2, #0 \n\
@@ -102,7 +102,7 @@ void feroceon_clear_user_highpage(struct page *page, unsigned long vaddr)
102 : "=r" (ptr) 102 : "=r" (ptr)
103 : "0" (kaddr), "I" (PAGE_SIZE / 32) 103 : "0" (kaddr), "I" (PAGE_SIZE / 32)
104 : "r1", "r2", "r3", "r4", "r5", "r6", "r7", "ip", "lr"); 104 : "r1", "r2", "r3", "r4", "r5", "r6", "r7", "ip", "lr");
105 kunmap_atomic(kaddr, KM_USER0); 105 kunmap_atomic(kaddr);
106} 106}
107 107
108struct cpu_user_fns feroceon_user_fns __initdata = { 108struct cpu_user_fns feroceon_user_fns __initdata = {
diff --git a/arch/arm/mm/copypage-v3.c b/arch/arm/mm/copypage-v3.c
index f72303e1d804..3935bddd4769 100644
--- a/arch/arm/mm/copypage-v3.c
+++ b/arch/arm/mm/copypage-v3.c
@@ -42,11 +42,11 @@ void v3_copy_user_highpage(struct page *to, struct page *from,
42{ 42{
43 void *kto, *kfrom; 43 void *kto, *kfrom;
44 44
45 kto = kmap_atomic(to, KM_USER0); 45 kto = kmap_atomic(to);
46 kfrom = kmap_atomic(from, KM_USER1); 46 kfrom = kmap_atomic(from);
47 v3_copy_user_page(kto, kfrom); 47 v3_copy_user_page(kto, kfrom);
48 kunmap_atomic(kfrom, KM_USER1); 48 kunmap_atomic(kfrom);
49 kunmap_atomic(kto, KM_USER0); 49 kunmap_atomic(kto);
50} 50}
51 51
52/* 52/*
@@ -56,7 +56,7 @@ void v3_copy_user_highpage(struct page *to, struct page *from,
56 */ 56 */
57void v3_clear_user_highpage(struct page *page, unsigned long vaddr) 57void v3_clear_user_highpage(struct page *page, unsigned long vaddr)
58{ 58{
59 void *ptr, *kaddr = kmap_atomic(page, KM_USER0); 59 void *ptr, *kaddr = kmap_atomic(page);
60 asm volatile("\n\ 60 asm volatile("\n\
61 mov r1, %2 @ 1\n\ 61 mov r1, %2 @ 1\n\
62 mov r2, #0 @ 1\n\ 62 mov r2, #0 @ 1\n\
@@ -72,7 +72,7 @@ void v3_clear_user_highpage(struct page *page, unsigned long vaddr)
72 : "=r" (ptr) 72 : "=r" (ptr)
73 : "0" (kaddr), "I" (PAGE_SIZE / 64) 73 : "0" (kaddr), "I" (PAGE_SIZE / 64)
74 : "r1", "r2", "r3", "ip", "lr"); 74 : "r1", "r2", "r3", "ip", "lr");
75 kunmap_atomic(kaddr, KM_USER0); 75 kunmap_atomic(kaddr);
76} 76}
77 77
78struct cpu_user_fns v3_user_fns __initdata = { 78struct cpu_user_fns v3_user_fns __initdata = {
diff --git a/arch/arm/mm/copypage-v4mc.c b/arch/arm/mm/copypage-v4mc.c
index 7d0a8c230342..ec8c3befb9c8 100644
--- a/arch/arm/mm/copypage-v4mc.c
+++ b/arch/arm/mm/copypage-v4mc.c
@@ -71,7 +71,7 @@ mc_copy_user_page(void *from, void *to)
71void v4_mc_copy_user_highpage(struct page *to, struct page *from, 71void v4_mc_copy_user_highpage(struct page *to, struct page *from,
72 unsigned long vaddr, struct vm_area_struct *vma) 72 unsigned long vaddr, struct vm_area_struct *vma)
73{ 73{
74 void *kto = kmap_atomic(to, KM_USER1); 74 void *kto = kmap_atomic(to);
75 75
76 if (!test_and_set_bit(PG_dcache_clean, &from->flags)) 76 if (!test_and_set_bit(PG_dcache_clean, &from->flags))
77 __flush_dcache_page(page_mapping(from), from); 77 __flush_dcache_page(page_mapping(from), from);
@@ -85,7 +85,7 @@ void v4_mc_copy_user_highpage(struct page *to, struct page *from,
85 85
86 raw_spin_unlock(&minicache_lock); 86 raw_spin_unlock(&minicache_lock);
87 87
88 kunmap_atomic(kto, KM_USER1); 88 kunmap_atomic(kto);
89} 89}
90 90
91/* 91/*
@@ -93,7 +93,7 @@ void v4_mc_copy_user_highpage(struct page *to, struct page *from,
93 */ 93 */
94void v4_mc_clear_user_highpage(struct page *page, unsigned long vaddr) 94void v4_mc_clear_user_highpage(struct page *page, unsigned long vaddr)
95{ 95{
96 void *ptr, *kaddr = kmap_atomic(page, KM_USER0); 96 void *ptr, *kaddr = kmap_atomic(page);
97 asm volatile("\ 97 asm volatile("\
98 mov r1, %2 @ 1\n\ 98 mov r1, %2 @ 1\n\
99 mov r2, #0 @ 1\n\ 99 mov r2, #0 @ 1\n\
@@ -111,7 +111,7 @@ void v4_mc_clear_user_highpage(struct page *page, unsigned long vaddr)
111 : "=r" (ptr) 111 : "=r" (ptr)
112 : "0" (kaddr), "I" (PAGE_SIZE / 64) 112 : "0" (kaddr), "I" (PAGE_SIZE / 64)
113 : "r1", "r2", "r3", "ip", "lr"); 113 : "r1", "r2", "r3", "ip", "lr");
114 kunmap_atomic(kaddr, KM_USER0); 114 kunmap_atomic(kaddr);
115} 115}
116 116
117struct cpu_user_fns v4_mc_user_fns __initdata = { 117struct cpu_user_fns v4_mc_user_fns __initdata = {
diff --git a/arch/arm/mm/copypage-v4wb.c b/arch/arm/mm/copypage-v4wb.c
index cb589cbb2b6c..067d0fdd630c 100644
--- a/arch/arm/mm/copypage-v4wb.c
+++ b/arch/arm/mm/copypage-v4wb.c
@@ -52,12 +52,12 @@ void v4wb_copy_user_highpage(struct page *to, struct page *from,
52{ 52{
53 void *kto, *kfrom; 53 void *kto, *kfrom;
54 54
55 kto = kmap_atomic(to, KM_USER0); 55 kto = kmap_atomic(to);
56 kfrom = kmap_atomic(from, KM_USER1); 56 kfrom = kmap_atomic(from);
57 flush_cache_page(vma, vaddr, page_to_pfn(from)); 57 flush_cache_page(vma, vaddr, page_to_pfn(from));
58 v4wb_copy_user_page(kto, kfrom); 58 v4wb_copy_user_page(kto, kfrom);
59 kunmap_atomic(kfrom, KM_USER1); 59 kunmap_atomic(kfrom);
60 kunmap_atomic(kto, KM_USER0); 60 kunmap_atomic(kto);
61} 61}
62 62
63/* 63/*
@@ -67,7 +67,7 @@ void v4wb_copy_user_highpage(struct page *to, struct page *from,
67 */ 67 */
68void v4wb_clear_user_highpage(struct page *page, unsigned long vaddr) 68void v4wb_clear_user_highpage(struct page *page, unsigned long vaddr)
69{ 69{
70 void *ptr, *kaddr = kmap_atomic(page, KM_USER0); 70 void *ptr, *kaddr = kmap_atomic(page);
71 asm volatile("\ 71 asm volatile("\
72 mov r1, %2 @ 1\n\ 72 mov r1, %2 @ 1\n\
73 mov r2, #0 @ 1\n\ 73 mov r2, #0 @ 1\n\
@@ -86,7 +86,7 @@ void v4wb_clear_user_highpage(struct page *page, unsigned long vaddr)
86 : "=r" (ptr) 86 : "=r" (ptr)
87 : "0" (kaddr), "I" (PAGE_SIZE / 64) 87 : "0" (kaddr), "I" (PAGE_SIZE / 64)
88 : "r1", "r2", "r3", "ip", "lr"); 88 : "r1", "r2", "r3", "ip", "lr");
89 kunmap_atomic(kaddr, KM_USER0); 89 kunmap_atomic(kaddr);
90} 90}
91 91
92struct cpu_user_fns v4wb_user_fns __initdata = { 92struct cpu_user_fns v4wb_user_fns __initdata = {
diff --git a/arch/arm/mm/copypage-v4wt.c b/arch/arm/mm/copypage-v4wt.c
index 30c7d048a324..b85c5da2e510 100644
--- a/arch/arm/mm/copypage-v4wt.c
+++ b/arch/arm/mm/copypage-v4wt.c
@@ -48,11 +48,11 @@ void v4wt_copy_user_highpage(struct page *to, struct page *from,
48{ 48{
49 void *kto, *kfrom; 49 void *kto, *kfrom;
50 50
51 kto = kmap_atomic(to, KM_USER0); 51 kto = kmap_atomic(to);
52 kfrom = kmap_atomic(from, KM_USER1); 52 kfrom = kmap_atomic(from);
53 v4wt_copy_user_page(kto, kfrom); 53 v4wt_copy_user_page(kto, kfrom);
54 kunmap_atomic(kfrom, KM_USER1); 54 kunmap_atomic(kfrom);
55 kunmap_atomic(kto, KM_USER0); 55 kunmap_atomic(kto);
56} 56}
57 57
58/* 58/*
@@ -62,7 +62,7 @@ void v4wt_copy_user_highpage(struct page *to, struct page *from,
62 */ 62 */
63void v4wt_clear_user_highpage(struct page *page, unsigned long vaddr) 63void v4wt_clear_user_highpage(struct page *page, unsigned long vaddr)
64{ 64{
65 void *ptr, *kaddr = kmap_atomic(page, KM_USER0); 65 void *ptr, *kaddr = kmap_atomic(page);
66 asm volatile("\ 66 asm volatile("\
67 mov r1, %2 @ 1\n\ 67 mov r1, %2 @ 1\n\
68 mov r2, #0 @ 1\n\ 68 mov r2, #0 @ 1\n\
@@ -79,7 +79,7 @@ void v4wt_clear_user_highpage(struct page *page, unsigned long vaddr)
79 : "=r" (ptr) 79 : "=r" (ptr)
80 : "0" (kaddr), "I" (PAGE_SIZE / 64) 80 : "0" (kaddr), "I" (PAGE_SIZE / 64)
81 : "r1", "r2", "r3", "ip", "lr"); 81 : "r1", "r2", "r3", "ip", "lr");
82 kunmap_atomic(kaddr, KM_USER0); 82 kunmap_atomic(kaddr);
83} 83}
84 84
85struct cpu_user_fns v4wt_user_fns __initdata = { 85struct cpu_user_fns v4wt_user_fns __initdata = {
diff --git a/arch/arm/mm/copypage-v6.c b/arch/arm/mm/copypage-v6.c
index 3d9a1552cef6..8b03a5814d00 100644
--- a/arch/arm/mm/copypage-v6.c
+++ b/arch/arm/mm/copypage-v6.c
@@ -38,11 +38,11 @@ static void v6_copy_user_highpage_nonaliasing(struct page *to,
38{ 38{
39 void *kto, *kfrom; 39 void *kto, *kfrom;
40 40
41 kfrom = kmap_atomic(from, KM_USER0); 41 kfrom = kmap_atomic(from);
42 kto = kmap_atomic(to, KM_USER1); 42 kto = kmap_atomic(to);
43 copy_page(kto, kfrom); 43 copy_page(kto, kfrom);
44 kunmap_atomic(kto, KM_USER1); 44 kunmap_atomic(kto);
45 kunmap_atomic(kfrom, KM_USER0); 45 kunmap_atomic(kfrom);
46} 46}
47 47
48/* 48/*
@@ -51,9 +51,9 @@ static void v6_copy_user_highpage_nonaliasing(struct page *to,
51 */ 51 */
52static void v6_clear_user_highpage_nonaliasing(struct page *page, unsigned long vaddr) 52static void v6_clear_user_highpage_nonaliasing(struct page *page, unsigned long vaddr)
53{ 53{
54 void *kaddr = kmap_atomic(page, KM_USER0); 54 void *kaddr = kmap_atomic(page);
55 clear_page(kaddr); 55 clear_page(kaddr);
56 kunmap_atomic(kaddr, KM_USER0); 56 kunmap_atomic(kaddr);
57} 57}
58 58
59/* 59/*
diff --git a/arch/arm/mm/copypage-xsc3.c b/arch/arm/mm/copypage-xsc3.c
index f9cde0702f1e..03a2042aced5 100644
--- a/arch/arm/mm/copypage-xsc3.c
+++ b/arch/arm/mm/copypage-xsc3.c
@@ -75,12 +75,12 @@ void xsc3_mc_copy_user_highpage(struct page *to, struct page *from,
75{ 75{
76 void *kto, *kfrom; 76 void *kto, *kfrom;
77 77
78 kto = kmap_atomic(to, KM_USER0); 78 kto = kmap_atomic(to);
79 kfrom = kmap_atomic(from, KM_USER1); 79 kfrom = kmap_atomic(from);
80 flush_cache_page(vma, vaddr, page_to_pfn(from)); 80 flush_cache_page(vma, vaddr, page_to_pfn(from));
81 xsc3_mc_copy_user_page(kto, kfrom); 81 xsc3_mc_copy_user_page(kto, kfrom);
82 kunmap_atomic(kfrom, KM_USER1); 82 kunmap_atomic(kfrom);
83 kunmap_atomic(kto, KM_USER0); 83 kunmap_atomic(kto);
84} 84}
85 85
86/* 86/*
@@ -90,7 +90,7 @@ void xsc3_mc_copy_user_highpage(struct page *to, struct page *from,
90 */ 90 */
91void xsc3_mc_clear_user_highpage(struct page *page, unsigned long vaddr) 91void xsc3_mc_clear_user_highpage(struct page *page, unsigned long vaddr)
92{ 92{
93 void *ptr, *kaddr = kmap_atomic(page, KM_USER0); 93 void *ptr, *kaddr = kmap_atomic(page);
94 asm volatile ("\ 94 asm volatile ("\
95 mov r1, %2 \n\ 95 mov r1, %2 \n\
96 mov r2, #0 \n\ 96 mov r2, #0 \n\
@@ -105,7 +105,7 @@ void xsc3_mc_clear_user_highpage(struct page *page, unsigned long vaddr)
105 : "=r" (ptr) 105 : "=r" (ptr)
106 : "0" (kaddr), "I" (PAGE_SIZE / 32) 106 : "0" (kaddr), "I" (PAGE_SIZE / 32)
107 : "r1", "r2", "r3"); 107 : "r1", "r2", "r3");
108 kunmap_atomic(kaddr, KM_USER0); 108 kunmap_atomic(kaddr);
109} 109}
110 110
111struct cpu_user_fns xsc3_mc_user_fns __initdata = { 111struct cpu_user_fns xsc3_mc_user_fns __initdata = {
diff --git a/arch/arm/mm/copypage-xscale.c b/arch/arm/mm/copypage-xscale.c
index 610c24ced310..439d106ae638 100644
--- a/arch/arm/mm/copypage-xscale.c
+++ b/arch/arm/mm/copypage-xscale.c
@@ -93,7 +93,7 @@ mc_copy_user_page(void *from, void *to)
93void xscale_mc_copy_user_highpage(struct page *to, struct page *from, 93void xscale_mc_copy_user_highpage(struct page *to, struct page *from,
94 unsigned long vaddr, struct vm_area_struct *vma) 94 unsigned long vaddr, struct vm_area_struct *vma)
95{ 95{
96 void *kto = kmap_atomic(to, KM_USER1); 96 void *kto = kmap_atomic(to);
97 97
98 if (!test_and_set_bit(PG_dcache_clean, &from->flags)) 98 if (!test_and_set_bit(PG_dcache_clean, &from->flags))
99 __flush_dcache_page(page_mapping(from), from); 99 __flush_dcache_page(page_mapping(from), from);
@@ -107,7 +107,7 @@ void xscale_mc_copy_user_highpage(struct page *to, struct page *from,
107 107
108 raw_spin_unlock(&minicache_lock); 108 raw_spin_unlock(&minicache_lock);
109 109
110 kunmap_atomic(kto, KM_USER1); 110 kunmap_atomic(kto);
111} 111}
112 112
113/* 113/*
@@ -116,7 +116,7 @@ void xscale_mc_copy_user_highpage(struct page *to, struct page *from,
116void 116void
117xscale_mc_clear_user_highpage(struct page *page, unsigned long vaddr) 117xscale_mc_clear_user_highpage(struct page *page, unsigned long vaddr)
118{ 118{
119 void *ptr, *kaddr = kmap_atomic(page, KM_USER0); 119 void *ptr, *kaddr = kmap_atomic(page);
120 asm volatile( 120 asm volatile(
121 "mov r1, %2 \n\ 121 "mov r1, %2 \n\
122 mov r2, #0 \n\ 122 mov r2, #0 \n\
@@ -133,7 +133,7 @@ xscale_mc_clear_user_highpage(struct page *page, unsigned long vaddr)
133 : "=r" (ptr) 133 : "=r" (ptr)
134 : "0" (kaddr), "I" (PAGE_SIZE / 32) 134 : "0" (kaddr), "I" (PAGE_SIZE / 32)
135 : "r1", "r2", "r3", "ip"); 135 : "r1", "r2", "r3", "ip");
136 kunmap_atomic(kaddr, KM_USER0); 136 kunmap_atomic(kaddr);
137} 137}
138 138
139struct cpu_user_fns xscale_mc_user_fns __initdata = { 139struct cpu_user_fns xscale_mc_user_fns __initdata = {
diff --git a/arch/arm/mm/highmem.c b/arch/arm/mm/highmem.c
index 807c0573abbe..5a21505d7550 100644
--- a/arch/arm/mm/highmem.c
+++ b/arch/arm/mm/highmem.c
@@ -36,7 +36,7 @@ void kunmap(struct page *page)
36} 36}
37EXPORT_SYMBOL(kunmap); 37EXPORT_SYMBOL(kunmap);
38 38
39void *__kmap_atomic(struct page *page) 39void *kmap_atomic(struct page *page)
40{ 40{
41 unsigned int idx; 41 unsigned int idx;
42 unsigned long vaddr; 42 unsigned long vaddr;
@@ -81,7 +81,7 @@ void *__kmap_atomic(struct page *page)
81 81
82 return (void *)vaddr; 82 return (void *)vaddr;
83} 83}
84EXPORT_SYMBOL(__kmap_atomic); 84EXPORT_SYMBOL(kmap_atomic);
85 85
86void __kunmap_atomic(void *kvaddr) 86void __kunmap_atomic(void *kvaddr)
87{ 87{
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 6ec1226fc62d..245a55a0a5bb 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -32,7 +32,6 @@
32 32
33#include <asm/mach/arch.h> 33#include <asm/mach/arch.h>
34#include <asm/mach/map.h> 34#include <asm/mach/map.h>
35#include <asm/memblock.h>
36 35
37#include "mm.h" 36#include "mm.h"
38 37
@@ -310,7 +309,7 @@ static void arm_memory_present(void)
310 309
311static bool arm_memblock_steal_permitted = true; 310static bool arm_memblock_steal_permitted = true;
312 311
313phys_addr_t arm_memblock_steal(phys_addr_t size, phys_addr_t align) 312phys_addr_t __init arm_memblock_steal(phys_addr_t size, phys_addr_t align)
314{ 313{
315 phys_addr_t phys; 314 phys_addr_t phys;
316 315
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 7e9b5bf910c1..f1c8486f7501 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -148,10 +148,6 @@ ENDPROC(cpu_v7_do_resume)
148 * Initialise TLB, Caches, and MMU state ready to switch the MMU 148 * Initialise TLB, Caches, and MMU state ready to switch the MMU
149 * on. Return in r0 the new CP15 C1 control register setting. 149 * on. Return in r0 the new CP15 C1 control register setting.
150 * 150 *
151 * We automatically detect if we have a Harvard cache, and use the
152 * Harvard cache control instructions insead of the unified cache
153 * control instructions.
154 *
155 * This should be able to cover all ARMv7 cores. 151 * This should be able to cover all ARMv7 cores.
156 * 152 *
157 * It is assumed that: 153 * It is assumed that:
@@ -234,9 +230,7 @@ __v7_setup:
234 mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register 230 mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
235#endif 231#endif
236#ifdef CONFIG_ARM_ERRATA_743622 232#ifdef CONFIG_ARM_ERRATA_743622
237 teq r6, #0x20 @ present in r2p0 233 teq r5, #0x00200000 @ only present in r2p*
238 teqne r6, #0x21 @ present in r2p1
239 teqne r6, #0x22 @ present in r2p2
240 mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register 234 mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
241 orreq r10, r10, #1 << 6 @ set bit #6 235 orreq r10, r10, #1 << 6 @ set bit #6
242 mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register 236 mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
@@ -251,9 +245,7 @@ __v7_setup:
251#endif 245#endif
252 246
2533: mov r10, #0 2473: mov r10, #0
254#ifdef HARVARD_CACHE
255 mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate 248 mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
256#endif
257 dsb 249 dsb
258#ifdef CONFIG_MMU 250#ifdef CONFIG_MMU
259 mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs 251 mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
@@ -330,16 +322,6 @@ __v7_ca5mp_proc_info:
330 .size __v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info 322 .size __v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info
331 323
332 /* 324 /*
333 * ARM Ltd. Cortex A7 processor.
334 */
335 .type __v7_ca7mp_proc_info, #object
336__v7_ca7mp_proc_info:
337 .long 0x410fc070
338 .long 0xff0ffff0
339 __v7_proc __v7_ca7mp_setup, hwcaps = HWCAP_IDIV
340 .size __v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info
341
342 /*
343 * ARM Ltd. Cortex A9 processor. 325 * ARM Ltd. Cortex A9 processor.
344 */ 326 */
345 .type __v7_ca9mp_proc_info, #object 327 .type __v7_ca9mp_proc_info, #object
@@ -351,6 +333,16 @@ __v7_ca9mp_proc_info:
351#endif /* CONFIG_ARM_LPAE */ 333#endif /* CONFIG_ARM_LPAE */
352 334
353 /* 335 /*
336 * ARM Ltd. Cortex A7 processor.
337 */
338 .type __v7_ca7mp_proc_info, #object
339__v7_ca7mp_proc_info:
340 .long 0x410fc070
341 .long 0xff0ffff0
342 __v7_proc __v7_ca7mp_setup, hwcaps = HWCAP_IDIV
343 .size __v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info
344
345 /*
354 * ARM Ltd. Cortex A15 processor. 346 * ARM Ltd. Cortex A15 processor.
355 */ 347 */
356 .type __v7_ca15mp_proc_info, #object 348 .type __v7_ca15mp_proc_info, #object
diff --git a/arch/arm/plat-mxc/3ds_debugboard.c b/arch/arm/plat-mxc/3ds_debugboard.c
index f0ba0726306c..d1e31fa1b0c3 100644
--- a/arch/arm/plat-mxc/3ds_debugboard.c
+++ b/arch/arm/plat-mxc/3ds_debugboard.c
@@ -16,6 +16,8 @@
16#include <linux/platform_device.h> 16#include <linux/platform_device.h>
17#include <linux/gpio.h> 17#include <linux/gpio.h>
18#include <linux/smsc911x.h> 18#include <linux/smsc911x.h>
19#include <linux/regulator/machine.h>
20#include <linux/regulator/fixed.h>
19 21
20#include <mach/hardware.h> 22#include <mach/hardware.h>
21 23
@@ -148,6 +150,11 @@ static struct irq_chip expio_irq_chip = {
148 .irq_unmask = expio_unmask_irq, 150 .irq_unmask = expio_unmask_irq,
149}; 151};
150 152
153static struct regulator_consumer_supply dummy_supplies[] = {
154 REGULATOR_SUPPLY("vdd33a", "smsc911x"),
155 REGULATOR_SUPPLY("vddvario", "smsc911x"),
156};
157
151int __init mxc_expio_init(u32 base, u32 p_irq) 158int __init mxc_expio_init(u32 base, u32 p_irq)
152{ 159{
153 int i; 160 int i;
@@ -188,6 +195,8 @@ int __init mxc_expio_init(u32 base, u32 p_irq)
188 irq_set_chained_handler(p_irq, mxc_expio_irq_handler); 195 irq_set_chained_handler(p_irq, mxc_expio_irq_handler);
189 196
190 /* Register Lan device on the debugboard */ 197 /* Register Lan device on the debugboard */
198 regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
199
191 smsc911x_resources[0].start = LAN9217_BASE_ADDR(base); 200 smsc911x_resources[0].start = LAN9217_BASE_ADDR(base);
192 smsc911x_resources[0].end = LAN9217_BASE_ADDR(base) + 0x100 - 1; 201 smsc911x_resources[0].end = LAN9217_BASE_ADDR(base) + 0x100 - 1;
193 platform_device_register(&smsc_lan9217_device); 202 platform_device_register(&smsc_lan9217_device);
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index dcebb1230f7f..c722f9ce6918 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -88,12 +88,6 @@ config IMX_HAVE_IOMUX_V1
88config ARCH_MXC_IOMUX_V3 88config ARCH_MXC_IOMUX_V3
89 bool 89 bool
90 90
91config ARCH_MXC_AUDMUX_V1
92 bool
93
94config ARCH_MXC_AUDMUX_V2
95 bool
96
97config IRAM_ALLOC 91config IRAM_ALLOC
98 bool 92 bool
99 select GENERIC_ALLOCATOR 93 select GENERIC_ALLOCATOR
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
index 076db84f3e31..e81290c27c65 100644
--- a/arch/arm/plat-mxc/Makefile
+++ b/arch/arm/plat-mxc/Makefile
@@ -14,8 +14,6 @@ obj-$(CONFIG_IRAM_ALLOC) += iram_alloc.o
14obj-$(CONFIG_MXC_PWM) += pwm.o 14obj-$(CONFIG_MXC_PWM) += pwm.o
15obj-$(CONFIG_MXC_ULPI) += ulpi.o 15obj-$(CONFIG_MXC_ULPI) += ulpi.o
16obj-$(CONFIG_MXC_USE_EPIT) += epit.o 16obj-$(CONFIG_MXC_USE_EPIT) += epit.o
17obj-$(CONFIG_ARCH_MXC_AUDMUX_V1) += audmux-v1.o
18obj-$(CONFIG_ARCH_MXC_AUDMUX_V2) += audmux-v2.o
19obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o 17obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o
20obj-$(CONFIG_CPU_FREQ_IMX) += cpufreq.o 18obj-$(CONFIG_CPU_FREQ_IMX) += cpufreq.o
21ifdef CONFIG_SND_IMX_SOC 19ifdef CONFIG_SND_IMX_SOC
diff --git a/arch/arm/plat-mxc/audmux-v1.c b/arch/arm/plat-mxc/audmux-v1.c
deleted file mode 100644
index 1180bef7664b..000000000000
--- a/arch/arm/plat-mxc/audmux-v1.c
+++ /dev/null
@@ -1,64 +0,0 @@
1/*
2 * Copyright 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
3 *
4 * Initial development of this code was funded by
5 * Phytec Messtechnik GmbH, http://www.phytec.de
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18#include <linux/module.h>
19#include <linux/err.h>
20#include <linux/io.h>
21#include <linux/clk.h>
22#include <mach/audmux.h>
23#include <mach/hardware.h>
24
25static void __iomem *audmux_base;
26
27static unsigned char port_mapping[] = {
28 0x0, 0x4, 0x8, 0x10, 0x14, 0x1c,
29};
30
31int mxc_audmux_v1_configure_port(unsigned int port, unsigned int pcr)
32{
33 if (!audmux_base) {
34 printk("%s: not configured\n", __func__);
35 return -ENOSYS;
36 }
37
38 if (port >= ARRAY_SIZE(port_mapping))
39 return -EINVAL;
40
41 writel(pcr, audmux_base + port_mapping[port]);
42
43 return 0;
44}
45EXPORT_SYMBOL_GPL(mxc_audmux_v1_configure_port);
46
47static int mxc_audmux_v1_init(void)
48{
49#ifdef CONFIG_MACH_MX21
50 if (cpu_is_mx21())
51 audmux_base = MX21_IO_ADDRESS(MX21_AUDMUX_BASE_ADDR);
52 else
53#endif
54#ifdef CONFIG_MACH_MX27
55 if (cpu_is_mx27())
56 audmux_base = MX27_IO_ADDRESS(MX27_AUDMUX_BASE_ADDR);
57 else
58#endif
59 (void)0;
60
61 return 0;
62}
63
64postcore_initcall(mxc_audmux_v1_init);
diff --git a/arch/arm/plat-mxc/audmux-v2.c b/arch/arm/plat-mxc/audmux-v2.c
deleted file mode 100644
index 8cced35009bd..000000000000
--- a/arch/arm/plat-mxc/audmux-v2.c
+++ /dev/null
@@ -1,219 +0,0 @@
1/*
2 * Copyright 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
3 *
4 * Initial development of this code was funded by
5 * Phytec Messtechnik GmbH, http://www.phytec.de
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18#include <linux/module.h>
19#include <linux/err.h>
20#include <linux/io.h>
21#include <linux/clk.h>
22#include <linux/debugfs.h>
23#include <linux/slab.h>
24#include <mach/audmux.h>
25#include <mach/hardware.h>
26
27static struct clk *audmux_clk;
28static void __iomem *audmux_base;
29
30#define MXC_AUDMUX_V2_PTCR(x) ((x) * 8)
31#define MXC_AUDMUX_V2_PDCR(x) ((x) * 8 + 4)
32
33#ifdef CONFIG_DEBUG_FS
34static struct dentry *audmux_debugfs_root;
35
36static int audmux_open_file(struct inode *inode, struct file *file)
37{
38 file->private_data = inode->i_private;
39 return 0;
40}
41
42/* There is an annoying discontinuity in the SSI numbering with regard
43 * to the Linux number of the devices */
44static const char *audmux_port_string(int port)
45{
46 switch (port) {
47 case MX31_AUDMUX_PORT1_SSI0:
48 return "imx-ssi.0";
49 case MX31_AUDMUX_PORT2_SSI1:
50 return "imx-ssi.1";
51 case MX31_AUDMUX_PORT3_SSI_PINS_3:
52 return "SSI3";
53 case MX31_AUDMUX_PORT4_SSI_PINS_4:
54 return "SSI4";
55 case MX31_AUDMUX_PORT5_SSI_PINS_5:
56 return "SSI5";
57 case MX31_AUDMUX_PORT6_SSI_PINS_6:
58 return "SSI6";
59 default:
60 return "UNKNOWN";
61 }
62}
63
64static ssize_t audmux_read_file(struct file *file, char __user *user_buf,
65 size_t count, loff_t *ppos)
66{
67 ssize_t ret;
68 char *buf = kmalloc(PAGE_SIZE, GFP_KERNEL);
69 int port = (int)file->private_data;
70 u32 pdcr, ptcr;
71
72 if (!buf)
73 return -ENOMEM;
74
75 if (audmux_clk)
76 clk_enable(audmux_clk);
77
78 ptcr = readl(audmux_base + MXC_AUDMUX_V2_PTCR(port));
79 pdcr = readl(audmux_base + MXC_AUDMUX_V2_PDCR(port));
80
81 if (audmux_clk)
82 clk_disable(audmux_clk);
83
84 ret = snprintf(buf, PAGE_SIZE, "PDCR: %08x\nPTCR: %08x\n",
85 pdcr, ptcr);
86
87 if (ptcr & MXC_AUDMUX_V2_PTCR_TFSDIR)
88 ret += snprintf(buf + ret, PAGE_SIZE - ret,
89 "TxFS output from %s, ",
90 audmux_port_string((ptcr >> 27) & 0x7));
91 else
92 ret += snprintf(buf + ret, PAGE_SIZE - ret,
93 "TxFS input, ");
94
95 if (ptcr & MXC_AUDMUX_V2_PTCR_TCLKDIR)
96 ret += snprintf(buf + ret, PAGE_SIZE - ret,
97 "TxClk output from %s",
98 audmux_port_string((ptcr >> 22) & 0x7));
99 else
100 ret += snprintf(buf + ret, PAGE_SIZE - ret,
101 "TxClk input");
102
103 ret += snprintf(buf + ret, PAGE_SIZE - ret, "\n");
104
105 if (ptcr & MXC_AUDMUX_V2_PTCR_SYN) {
106 ret += snprintf(buf + ret, PAGE_SIZE - ret,
107 "Port is symmetric");
108 } else {
109 if (ptcr & MXC_AUDMUX_V2_PTCR_RFSDIR)
110 ret += snprintf(buf + ret, PAGE_SIZE - ret,
111 "RxFS output from %s, ",
112 audmux_port_string((ptcr >> 17) & 0x7));
113 else
114 ret += snprintf(buf + ret, PAGE_SIZE - ret,
115 "RxFS input, ");
116
117 if (ptcr & MXC_AUDMUX_V2_PTCR_RCLKDIR)
118 ret += snprintf(buf + ret, PAGE_SIZE - ret,
119 "RxClk output from %s",
120 audmux_port_string((ptcr >> 12) & 0x7));
121 else
122 ret += snprintf(buf + ret, PAGE_SIZE - ret,
123 "RxClk input");
124 }
125
126 ret += snprintf(buf + ret, PAGE_SIZE - ret,
127 "\nData received from %s\n",
128 audmux_port_string((pdcr >> 13) & 0x7));
129
130 ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
131
132 kfree(buf);
133
134 return ret;
135}
136
137static const struct file_operations audmux_debugfs_fops = {
138 .open = audmux_open_file,
139 .read = audmux_read_file,
140 .llseek = default_llseek,
141};
142
143static void audmux_debugfs_init(void)
144{
145 int i;
146 char buf[20];
147
148 audmux_debugfs_root = debugfs_create_dir("audmux", NULL);
149 if (!audmux_debugfs_root) {
150 pr_warning("Failed to create AUDMUX debugfs root\n");
151 return;
152 }
153
154 for (i = 1; i < 8; i++) {
155 snprintf(buf, sizeof(buf), "ssi%d", i);
156 if (!debugfs_create_file(buf, 0444, audmux_debugfs_root,
157 (void *)i, &audmux_debugfs_fops))
158 pr_warning("Failed to create AUDMUX port %d debugfs file\n",
159 i);
160 }
161}
162#else
163static inline void audmux_debugfs_init(void)
164{
165}
166#endif
167
168int mxc_audmux_v2_configure_port(unsigned int port, unsigned int ptcr,
169 unsigned int pdcr)
170{
171 if (!audmux_base)
172 return -ENOSYS;
173
174 if (audmux_clk)
175 clk_enable(audmux_clk);
176
177 writel(ptcr, audmux_base + MXC_AUDMUX_V2_PTCR(port));
178 writel(pdcr, audmux_base + MXC_AUDMUX_V2_PDCR(port));
179
180 if (audmux_clk)
181 clk_disable(audmux_clk);
182
183 return 0;
184}
185EXPORT_SYMBOL_GPL(mxc_audmux_v2_configure_port);
186
187static int mxc_audmux_v2_init(void)
188{
189 int ret;
190 if (cpu_is_mx51()) {
191 audmux_base = MX51_IO_ADDRESS(MX51_AUDMUX_BASE_ADDR);
192 } else if (cpu_is_mx31()) {
193 audmux_base = MX31_IO_ADDRESS(MX31_AUDMUX_BASE_ADDR);
194 } else if (cpu_is_mx35()) {
195 audmux_clk = clk_get(NULL, "audmux");
196 if (IS_ERR(audmux_clk)) {
197 ret = PTR_ERR(audmux_clk);
198 printk(KERN_ERR "%s: cannot get clock: %d\n", __func__,
199 ret);
200 return ret;
201 }
202 audmux_base = MX35_IO_ADDRESS(MX35_AUDMUX_BASE_ADDR);
203 } else if (cpu_is_mx25()) {
204 audmux_clk = clk_get(NULL, "audmux");
205 if (IS_ERR(audmux_clk)) {
206 ret = PTR_ERR(audmux_clk);
207 printk(KERN_ERR "%s: cannot get clock: %d\n", __func__,
208 ret);
209 return ret;
210 }
211 audmux_base = MX25_IO_ADDRESS(MX25_AUDMUX_BASE_ADDR);
212 }
213
214 audmux_debugfs_init();
215
216 return 0;
217}
218
219postcore_initcall(mxc_audmux_v2_init);
diff --git a/arch/arm/plat-mxc/include/mach/audmux.h b/arch/arm/plat-mxc/include/mach/audmux.h
deleted file mode 100644
index 6fda788ed0e9..000000000000
--- a/arch/arm/plat-mxc/include/mach/audmux.h
+++ /dev/null
@@ -1,60 +0,0 @@
1#ifndef __MACH_AUDMUX_H
2#define __MACH_AUDMUX_H
3
4#define MX27_AUDMUX_HPCR1_SSI0 0
5#define MX27_AUDMUX_HPCR2_SSI1 1
6#define MX27_AUDMUX_HPCR3_SSI_PINS_4 2
7#define MX27_AUDMUX_PPCR1_SSI_PINS_1 3
8#define MX27_AUDMUX_PPCR2_SSI_PINS_2 4
9#define MX27_AUDMUX_PPCR3_SSI_PINS_3 5
10
11#define MX31_AUDMUX_PORT1_SSI0 0
12#define MX31_AUDMUX_PORT2_SSI1 1
13#define MX31_AUDMUX_PORT3_SSI_PINS_3 2
14#define MX31_AUDMUX_PORT4_SSI_PINS_4 3
15#define MX31_AUDMUX_PORT5_SSI_PINS_5 4
16#define MX31_AUDMUX_PORT6_SSI_PINS_6 5
17
18#define MX51_AUDMUX_PORT1_SSI0 0
19#define MX51_AUDMUX_PORT2_SSI1 1
20#define MX51_AUDMUX_PORT3 2
21#define MX51_AUDMUX_PORT4 3
22#define MX51_AUDMUX_PORT5 4
23#define MX51_AUDMUX_PORT6 5
24#define MX51_AUDMUX_PORT7 6
25
26/* Register definitions for the i.MX21/27 Digital Audio Multiplexer */
27#define MXC_AUDMUX_V1_PCR_INMMASK(x) ((x) & 0xff)
28#define MXC_AUDMUX_V1_PCR_INMEN (1 << 8)
29#define MXC_AUDMUX_V1_PCR_TXRXEN (1 << 10)
30#define MXC_AUDMUX_V1_PCR_SYN (1 << 12)
31#define MXC_AUDMUX_V1_PCR_RXDSEL(x) (((x) & 0x7) << 13)
32#define MXC_AUDMUX_V1_PCR_RFCSEL(x) (((x) & 0xf) << 20)
33#define MXC_AUDMUX_V1_PCR_RCLKDIR (1 << 24)
34#define MXC_AUDMUX_V1_PCR_RFSDIR (1 << 25)
35#define MXC_AUDMUX_V1_PCR_TFCSEL(x) (((x) & 0xf) << 26)
36#define MXC_AUDMUX_V1_PCR_TCLKDIR (1 << 30)
37#define MXC_AUDMUX_V1_PCR_TFSDIR (1 << 31)
38
39/* Register definitions for the i.MX25/31/35/51 Digital Audio Multiplexer */
40#define MXC_AUDMUX_V2_PTCR_TFSDIR (1 << 31)
41#define MXC_AUDMUX_V2_PTCR_TFSEL(x) (((x) & 0xf) << 27)
42#define MXC_AUDMUX_V2_PTCR_TCLKDIR (1 << 26)
43#define MXC_AUDMUX_V2_PTCR_TCSEL(x) (((x) & 0xf) << 22)
44#define MXC_AUDMUX_V2_PTCR_RFSDIR (1 << 21)
45#define MXC_AUDMUX_V2_PTCR_RFSEL(x) (((x) & 0xf) << 17)
46#define MXC_AUDMUX_V2_PTCR_RCLKDIR (1 << 16)
47#define MXC_AUDMUX_V2_PTCR_RCSEL(x) (((x) & 0xf) << 12)
48#define MXC_AUDMUX_V2_PTCR_SYN (1 << 11)
49
50#define MXC_AUDMUX_V2_PDCR_RXDSEL(x) (((x) & 0x7) << 13)
51#define MXC_AUDMUX_V2_PDCR_TXRXEN (1 << 12)
52#define MXC_AUDMUX_V2_PDCR_MODE(x) (((x) & 0x3) << 8)
53#define MXC_AUDMUX_V2_PDCR_INMMASK(x) ((x) & 0xff)
54
55int mxc_audmux_v1_configure_port(unsigned int port, unsigned int pcr);
56
57int mxc_audmux_v2_configure_port(unsigned int port, unsigned int ptcr,
58 unsigned int pdcr);
59
60#endif /* __MACH_AUDMUX_H */
diff --git a/arch/arm/plat-mxc/include/mach/iomux-v1.h b/arch/arm/plat-mxc/include/mach/iomux-v1.h
index 6fa8a707b9a0..f7d18046c04f 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-v1.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-v1.h
@@ -96,6 +96,6 @@ extern int mxc_gpio_mode(int gpio_mode);
96extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count, 96extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
97 const char *label); 97 const char *label);
98 98
99extern int __init imx_iomuxv1_init(void __iomem *base, int numports); 99extern int imx_iomuxv1_init(void __iomem *base, int numports);
100 100
101#endif /* __MACH_IOMUX_V1_H__ */ 101#endif /* __MACH_IOMUX_V1_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mxc_ehci.h b/arch/arm/plat-mxc/include/mach/mxc_ehci.h
index 2c159dc2398b..9ffd1bbe615f 100644
--- a/arch/arm/plat-mxc/include/mach/mxc_ehci.h
+++ b/arch/arm/plat-mxc/include/mach/mxc_ehci.h
@@ -44,7 +44,7 @@ struct mxc_usbh_platform_data {
44 int (*exit)(struct platform_device *pdev); 44 int (*exit)(struct platform_device *pdev);
45 45
46 unsigned int portsc; 46 unsigned int portsc;
47 struct otg_transceiver *otg; 47 struct usb_phy *otg;
48}; 48};
49 49
50int mx51_initialize_usb_hw(int port, unsigned int flags); 50int mx51_initialize_usb_hw(int port, unsigned int flags);
diff --git a/arch/arm/plat-mxc/include/mach/ulpi.h b/arch/arm/plat-mxc/include/mach/ulpi.h
index f9161c96d7bd..42bdaca6d7d9 100644
--- a/arch/arm/plat-mxc/include/mach/ulpi.h
+++ b/arch/arm/plat-mxc/include/mach/ulpi.h
@@ -2,15 +2,15 @@
2#define __MACH_ULPI_H 2#define __MACH_ULPI_H
3 3
4#ifdef CONFIG_USB_ULPI 4#ifdef CONFIG_USB_ULPI
5struct otg_transceiver *imx_otg_ulpi_create(unsigned int flags); 5struct usb_phy *imx_otg_ulpi_create(unsigned int flags);
6#else 6#else
7static inline struct otg_transceiver *imx_otg_ulpi_create(unsigned int flags) 7static inline struct usb_phy *imx_otg_ulpi_create(unsigned int flags)
8{ 8{
9 return NULL; 9 return NULL;
10} 10}
11#endif 11#endif
12 12
13extern struct otg_io_access_ops mxc_ulpi_access_ops; 13extern struct usb_phy_io_ops mxc_ulpi_access_ops;
14 14
15#endif /* __MACH_ULPI_H */ 15#endif /* __MACH_ULPI_H */
16 16
diff --git a/arch/arm/plat-mxc/ulpi.c b/arch/arm/plat-mxc/ulpi.c
index 477e45bea1be..d2963427184f 100644
--- a/arch/arm/plat-mxc/ulpi.c
+++ b/arch/arm/plat-mxc/ulpi.c
@@ -58,7 +58,7 @@ static int ulpi_poll(void __iomem *view, u32 bit)
58 return -ETIMEDOUT; 58 return -ETIMEDOUT;
59} 59}
60 60
61static int ulpi_read(struct otg_transceiver *otg, u32 reg) 61static int ulpi_read(struct usb_phy *otg, u32 reg)
62{ 62{
63 int ret; 63 int ret;
64 void __iomem *view = otg->io_priv; 64 void __iomem *view = otg->io_priv;
@@ -84,7 +84,7 @@ static int ulpi_read(struct otg_transceiver *otg, u32 reg)
84 return (__raw_readl(view) >> ULPIVW_RDATA_SHIFT) & ULPIVW_RDATA_MASK; 84 return (__raw_readl(view) >> ULPIVW_RDATA_SHIFT) & ULPIVW_RDATA_MASK;
85} 85}
86 86
87static int ulpi_write(struct otg_transceiver *otg, u32 val, u32 reg) 87static int ulpi_write(struct usb_phy *otg, u32 val, u32 reg)
88{ 88{
89 int ret; 89 int ret;
90 void __iomem *view = otg->io_priv; 90 void __iomem *view = otg->io_priv;
@@ -106,13 +106,13 @@ static int ulpi_write(struct otg_transceiver *otg, u32 val, u32 reg)
106 return ulpi_poll(view, ULPIVW_RUN); 106 return ulpi_poll(view, ULPIVW_RUN);
107} 107}
108 108
109struct otg_io_access_ops mxc_ulpi_access_ops = { 109struct usb_phy_io_ops mxc_ulpi_access_ops = {
110 .read = ulpi_read, 110 .read = ulpi_read,
111 .write = ulpi_write, 111 .write = ulpi_write,
112}; 112};
113EXPORT_SYMBOL_GPL(mxc_ulpi_access_ops); 113EXPORT_SYMBOL_GPL(mxc_ulpi_access_ops);
114 114
115struct otg_transceiver *imx_otg_ulpi_create(unsigned int flags) 115struct usb_phy *imx_otg_ulpi_create(unsigned int flags)
116{ 116{
117 return otg_ulpi_create(&mxc_ulpi_access_ops, flags); 117 return otg_ulpi_create(&mxc_ulpi_access_ops, flags);
118} 118}
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index aa59f4247dc5..8f81503a4df7 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -110,14 +110,6 @@ config OMAP_MUX_WARNINGS
110 to change the pin multiplexing setup. When there are no warnings 110 to change the pin multiplexing setup. When there are no warnings
111 printed, it's safe to deselect OMAP_MUX for your product. 111 printed, it's safe to deselect OMAP_MUX for your product.
112 112
113config OMAP_MCBSP
114 bool "McBSP support"
115 depends on ARCH_OMAP
116 default y
117 help
118 Say Y here if you want support for the OMAP Multichannel
119 Buffered Serial Port.
120
121config OMAP_MBOX_FWK 113config OMAP_MBOX_FWK
122 tristate "Mailbox framework support" 114 tristate "Mailbox framework support"
123 depends on ARCH_OMAP 115 depends on ARCH_OMAP
diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
index 9a584614e7e6..c0fe2757b695 100644
--- a/arch/arm/plat-omap/Makefile
+++ b/arch/arm/plat-omap/Makefile
@@ -17,8 +17,6 @@ obj-$(CONFIG_ARCH_OMAP2) += omap_device.o
17obj-$(CONFIG_ARCH_OMAP3) += omap_device.o 17obj-$(CONFIG_ARCH_OMAP3) += omap_device.o
18obj-$(CONFIG_ARCH_OMAP4) += omap_device.o 18obj-$(CONFIG_ARCH_OMAP4) += omap_device.o
19 19
20obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
21
22obj-$(CONFIG_OMAP_DM_TIMER) += dmtimer.o 20obj-$(CONFIG_OMAP_DM_TIMER) += dmtimer.o
23obj-$(CONFIG_OMAP_DEBUG_DEVICES) += debug-devices.o 21obj-$(CONFIG_OMAP_DEBUG_DEVICES) += debug-devices.o
24obj-$(CONFIG_OMAP_DEBUG_LEDS) += debug-leds.o 22obj-$(CONFIG_OMAP_DEBUG_LEDS) += debug-leds.o
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
index 06383b51e655..f1e46ea6b81d 100644
--- a/arch/arm/plat-omap/common.c
+++ b/arch/arm/plat-omap/common.c
@@ -15,7 +15,6 @@
15#include <linux/init.h> 15#include <linux/init.h>
16#include <linux/io.h> 16#include <linux/io.h>
17#include <linux/dma-mapping.h> 17#include <linux/dma-mapping.h>
18#include <linux/omapfb.h>
19 18
20#include <plat/common.h> 19#include <plat/common.h>
21#include <plat/board.h> 20#include <plat/board.h>
@@ -65,10 +64,10 @@ const void *__init omap_get_var_config(u16 tag, size_t *len)
65 64
66void __init omap_reserve(void) 65void __init omap_reserve(void)
67{ 66{
68 omapfb_reserve_sdram_memblock();
69 omap_vram_reserve_sdram_memblock(); 67 omap_vram_reserve_sdram_memblock();
70 omap_dsp_reserve_sdram_memblock(); 68 omap_dsp_reserve_sdram_memblock();
71 omap_secure_ram_reserve_memblock(); 69 omap_secure_ram_reserve_memblock();
70 omap_barrier_reserve_memblock();
72} 71}
73 72
74void __init omap_init_consistent_dma_size(void) 73void __init omap_init_consistent_dma_size(void)
diff --git a/arch/arm/plat-omap/fb.c b/arch/arm/plat-omap/fb.c
index c9e5d7298c40..dd6f92c99e56 100644
--- a/arch/arm/plat-omap/fb.c
+++ b/arch/arm/plat-omap/fb.c
@@ -34,15 +34,11 @@
34#include <asm/mach/map.h> 34#include <asm/mach/map.h>
35 35
36#include <plat/board.h> 36#include <plat/board.h>
37#include <plat/sram.h>
38
39#include "fb.h"
40 37
41#if defined(CONFIG_FB_OMAP) || defined(CONFIG_FB_OMAP_MODULE) 38#if defined(CONFIG_FB_OMAP) || defined(CONFIG_FB_OMAP_MODULE)
42 39
40static bool omapfb_lcd_configured;
43static struct omapfb_platform_data omapfb_config; 41static struct omapfb_platform_data omapfb_config;
44static int config_invalid;
45static int configured_regions;
46 42
47static u64 omap_fb_dma_mask = ~(u32)0; 43static u64 omap_fb_dma_mask = ~(u32)0;
48 44
@@ -57,302 +53,21 @@ static struct platform_device omap_fb_device = {
57 .num_resources = 0, 53 .num_resources = 0,
58}; 54};
59 55
60void omapfb_set_platform_data(struct omapfb_platform_data *data) 56void __init omapfb_set_lcd_config(const struct omap_lcd_config *config)
61{
62}
63
64static inline int ranges_overlap(unsigned long start1, unsigned long size1,
65 unsigned long start2, unsigned long size2)
66{
67 return (start1 >= start2 && start1 < start2 + size2) ||
68 (start2 >= start1 && start2 < start1 + size1);
69}
70
71static inline int range_included(unsigned long start1, unsigned long size1,
72 unsigned long start2, unsigned long size2)
73{
74 return start1 >= start2 && start1 + size1 <= start2 + size2;
75}
76
77
78/* Check if there is an overlapping region. */
79static int fbmem_region_reserved(unsigned long start, size_t size)
80{
81 struct omapfb_mem_region *rg;
82 int i;
83
84 rg = &omapfb_config.mem_desc.region[0];
85 for (i = 0; i < OMAPFB_PLANE_NUM; i++, rg++) {
86 if (!rg->paddr)
87 /* Empty slot. */
88 continue;
89 if (ranges_overlap(start, size, rg->paddr, rg->size))
90 return 1;
91 }
92 return 0;
93}
94
95/*
96 * Get the region_idx`th region from board config/ATAG and convert it to
97 * our internal format.
98 */
99static int __init get_fbmem_region(int region_idx, struct omapfb_mem_region *rg)
100{ 57{
101 const struct omap_fbmem_config *conf; 58 omapfb_config.lcd = *config;
102 u32 paddr; 59 omapfb_lcd_configured = true;
103
104 conf = omap_get_nr_config(OMAP_TAG_FBMEM,
105 struct omap_fbmem_config, region_idx);
106 if (conf == NULL)
107 return -ENOENT;
108
109 paddr = conf->start;
110 /*
111 * Low bits encode the page allocation mode, if high bits
112 * are zero. Otherwise we need a page aligned fixed
113 * address.
114 */
115 memset(rg, 0, sizeof(*rg));
116 rg->type = paddr & ~PAGE_MASK;
117 rg->paddr = paddr & PAGE_MASK;
118 rg->size = PAGE_ALIGN(conf->size);
119 return 0;
120} 60}
121 61
122static int set_fbmem_region_type(struct omapfb_mem_region *rg, int mem_type, 62static int __init omap_init_fb(void)
123 unsigned long mem_start,
124 unsigned long mem_size)
125{
126 /*
127 * Check if the configuration specifies the type explicitly.
128 * type = 0 && paddr = 0, a default don't care case maps to
129 * the SDRAM type.
130 */
131 if (rg->type || !rg->paddr)
132 return 0;
133 if (ranges_overlap(rg->paddr, rg->size, mem_start, mem_size)) {
134 rg->type = mem_type;
135 return 0;
136 }
137 /* Can't determine it. */
138 return -1;
139}
140
141static int check_fbmem_region(int region_idx, struct omapfb_mem_region *rg,
142 unsigned long start_avail, unsigned size_avail)
143{ 63{
144 unsigned long paddr = rg->paddr;
145 size_t size = rg->size;
146
147 if (rg->type > OMAPFB_MEMTYPE_MAX) {
148 printk(KERN_ERR
149 "Invalid start address for FB region %d\n", region_idx);
150 return -EINVAL;
151 }
152
153 if (!rg->size) {
154 printk(KERN_ERR "Zero size for FB region %d\n", region_idx);
155 return -EINVAL;
156 }
157
158 if (!paddr)
159 /* Allocate this dynamically, leave paddr 0 for now. */
160 return 0;
161
162 /* 64 /*
163 * Fixed region for the given RAM range. Check if it's already 65 * If the board file has not set the lcd config with
164 * reserved by the FB code or someone else. 66 * omapfb_set_lcd_config(), don't bother registering the omapfb device
165 */ 67 */
166 if (fbmem_region_reserved(paddr, size) || 68 if (!omapfb_lcd_configured)
167 !range_included(paddr, size, start_avail, size_avail)) {
168 printk(KERN_ERR "Trying to use reserved memory "
169 "for FB region %d\n", region_idx);
170 return -EINVAL;
171 }
172
173 return 0;
174}
175
176static int valid_sdram(unsigned long addr, unsigned long size)
177{
178 return memblock_is_region_memory(addr, size);
179}
180
181static int reserve_sdram(unsigned long addr, unsigned long size)
182{
183 if (memblock_is_region_reserved(addr, size))
184 return -EBUSY;
185 if (memblock_reserve(addr, size))
186 return -ENOMEM;
187 return 0;
188}
189
190/*
191 * Called from map_io. We need to call to this early enough so that we
192 * can reserve the fixed SDRAM regions before VM could get hold of them.
193 */
194void __init omapfb_reserve_sdram_memblock(void)
195{
196 unsigned long reserved = 0;
197 int i;
198
199 if (config_invalid)
200 return;
201
202 for (i = 0; ; i++) {
203 struct omapfb_mem_region rg;
204
205 if (get_fbmem_region(i, &rg) < 0)
206 break;
207
208 if (i == OMAPFB_PLANE_NUM) {
209 pr_err("Extraneous FB mem configuration entries\n");
210 config_invalid = 1;
211 return;
212 }
213
214 /* Check if it's our memory type. */
215 if (rg.type != OMAPFB_MEMTYPE_SDRAM)
216 continue;
217
218 /* Check if the region falls within SDRAM */
219 if (rg.paddr && !valid_sdram(rg.paddr, rg.size))
220 continue;
221
222 if (rg.size == 0) {
223 pr_err("Zero size for FB region %d\n", i);
224 config_invalid = 1;
225 return;
226 }
227
228 if (rg.paddr) {
229 if (reserve_sdram(rg.paddr, rg.size)) {
230 pr_err("Trying to use reserved memory for FB region %d\n",
231 i);
232 config_invalid = 1;
233 return;
234 }
235 reserved += rg.size;
236 }
237
238 if (omapfb_config.mem_desc.region[i].size) {
239 pr_err("FB region %d already set\n", i);
240 config_invalid = 1;
241 return;
242 }
243
244 omapfb_config.mem_desc.region[i] = rg;
245 configured_regions++;
246 }
247 omapfb_config.mem_desc.region_cnt = i;
248 if (reserved)
249 pr_info("Reserving %lu bytes SDRAM for frame buffer\n",
250 reserved);
251}
252
253/*
254 * Called at sram init time, before anything is pushed to the SRAM stack.
255 * Because of the stack scheme, we will allocate everything from the
256 * start of the lowest address region to the end of SRAM. This will also
257 * include padding for page alignment and possible holes between regions.
258 *
259 * As opposed to the SDRAM case, we'll also do any dynamic allocations at
260 * this point, since the driver built as a module would have problem with
261 * freeing / reallocating the regions.
262 */
263unsigned long __init omapfb_reserve_sram(unsigned long sram_pstart,
264 unsigned long sram_vstart,
265 unsigned long sram_size,
266 unsigned long pstart_avail,
267 unsigned long size_avail)
268{
269 struct omapfb_mem_region rg;
270 unsigned long pend_avail;
271 unsigned long reserved;
272 int i;
273
274 if (config_invalid)
275 return 0; 69 return 0;
276 70
277 reserved = 0;
278 pend_avail = pstart_avail + size_avail;
279 for (i = 0; ; i++) {
280 if (get_fbmem_region(i, &rg) < 0)
281 break;
282 if (i == OMAPFB_PLANE_NUM) {
283 printk(KERN_ERR
284 "Extraneous FB mem configuration entries\n");
285 config_invalid = 1;
286 return 0;
287 }
288
289 /* Check if it's our memory type. */
290 if (set_fbmem_region_type(&rg, OMAPFB_MEMTYPE_SRAM,
291 sram_pstart, sram_size) < 0 ||
292 (rg.type != OMAPFB_MEMTYPE_SRAM))
293 continue;
294 BUG_ON(omapfb_config.mem_desc.region[i].size);
295
296 if (check_fbmem_region(i, &rg, pstart_avail, size_avail) < 0) {
297 config_invalid = 1;
298 return 0;
299 }
300
301 if (!rg.paddr) {
302 /* Dynamic allocation */
303 if ((size_avail & PAGE_MASK) < rg.size) {
304 printk("Not enough SRAM for FB region %d\n",
305 i);
306 config_invalid = 1;
307 return 0;
308 }
309 size_avail = (size_avail - rg.size) & PAGE_MASK;
310 rg.paddr = pstart_avail + size_avail;
311 }
312 /* Reserve everything above the start of the region. */
313 if (pend_avail - rg.paddr > reserved)
314 reserved = pend_avail - rg.paddr;
315 size_avail = pend_avail - reserved - pstart_avail;
316
317 /*
318 * We have a kernel mapping for this already, so the
319 * driver won't have to make one.
320 */
321 rg.vaddr = (void *)(sram_vstart + rg.paddr - sram_pstart);
322 omapfb_config.mem_desc.region[i] = rg;
323 configured_regions++;
324 }
325 omapfb_config.mem_desc.region_cnt = i;
326 if (reserved)
327 pr_info("Reserving %lu bytes SRAM for frame buffer\n",
328 reserved);
329 return reserved;
330}
331
332void omapfb_set_ctrl_platform_data(void *data)
333{
334 omapfb_config.ctrl_platform_data = data;
335}
336
337static int __init omap_init_fb(void)
338{
339 const struct omap_lcd_config *conf;
340
341 if (config_invalid)
342 return 0;
343 if (configured_regions != omapfb_config.mem_desc.region_cnt) {
344 printk(KERN_ERR "Invalid FB mem configuration entries\n");
345 return 0;
346 }
347 conf = omap_get_config(OMAP_TAG_LCD, struct omap_lcd_config);
348 if (conf == NULL) {
349 if (configured_regions)
350 /* FB mem config, but no LCD config? */
351 printk(KERN_ERR "Missing LCD configuration\n");
352 return 0;
353 }
354 omapfb_config.lcd = *conf;
355
356 return platform_device_register(&omap_fb_device); 71 return platform_device_register(&omap_fb_device);
357} 72}
358 73
@@ -374,11 +89,6 @@ static struct platform_device omap_fb_device = {
374 .num_resources = 0, 89 .num_resources = 0,
375}; 90};
376 91
377void omapfb_set_platform_data(struct omapfb_platform_data *data)
378{
379 omapfb_config = *data;
380}
381
382static int __init omap_init_fb(void) 92static int __init omap_init_fb(void)
383{ 93{
384 return platform_device_register(&omap_fb_device); 94 return platform_device_register(&omap_fb_device);
@@ -386,36 +96,10 @@ static int __init omap_init_fb(void)
386 96
387arch_initcall(omap_init_fb); 97arch_initcall(omap_init_fb);
388 98
389void omapfb_reserve_sdram_memblock(void)
390{
391}
392
393unsigned long __init omapfb_reserve_sram(unsigned long sram_pstart,
394 unsigned long sram_vstart,
395 unsigned long sram_size,
396 unsigned long start_avail,
397 unsigned long size_avail)
398{
399 return 0;
400}
401
402#else 99#else
403 100
404void omapfb_set_platform_data(struct omapfb_platform_data *data) 101void __init omapfb_set_lcd_config(const struct omap_lcd_config *config)
405{
406}
407
408void omapfb_reserve_sdram_memblock(void)
409{
410}
411
412unsigned long __init omapfb_reserve_sram(unsigned long sram_pstart,
413 unsigned long sram_vstart,
414 unsigned long sram_size,
415 unsigned long start_avail,
416 unsigned long size_avail)
417{ 102{
418 return 0;
419} 103}
420 104
421#endif 105#endif
diff --git a/arch/arm/plat-omap/fb.h b/arch/arm/plat-omap/fb.h
deleted file mode 100644
index d765d0bd8520..000000000000
--- a/arch/arm/plat-omap/fb.h
+++ /dev/null
@@ -1,10 +0,0 @@
1#ifndef __PLAT_OMAP_FB_H__
2#define __PLAT_OMAP_FB_H__
3
4extern unsigned long omapfb_reserve_sram(unsigned long sram_pstart,
5 unsigned long sram_vstart,
6 unsigned long sram_size,
7 unsigned long pstart_avail,
8 unsigned long size_avail);
9
10#endif /* __PLAT_OMAP_FB_H__ */
diff --git a/arch/arm/plat-omap/include/plat/blizzard.h b/arch/arm/plat-omap/include/plat/blizzard.h
deleted file mode 100644
index 56e7f2e7d12f..000000000000
--- a/arch/arm/plat-omap/include/plat/blizzard.h
+++ /dev/null
@@ -1,12 +0,0 @@
1#ifndef _BLIZZARD_H
2#define _BLIZZARD_H
3
4struct blizzard_platform_data {
5 void (*power_up)(struct device *dev);
6 void (*power_down)(struct device *dev);
7 unsigned long (*get_clock_rate)(struct device *dev);
8
9 unsigned te_connected:1;
10};
11
12#endif
diff --git a/arch/arm/plat-omap/include/plat/board.h b/arch/arm/plat-omap/include/plat/board.h
index 97126dfd2888..d5eb4c87db9d 100644
--- a/arch/arm/plat-omap/include/plat/board.h
+++ b/arch/arm/plat-omap/include/plat/board.h
@@ -28,9 +28,7 @@ enum {
28 28
29/* Different peripheral ids */ 29/* Different peripheral ids */
30#define OMAP_TAG_CLOCK 0x4f01 30#define OMAP_TAG_CLOCK 0x4f01
31#define OMAP_TAG_LCD 0x4f05
32#define OMAP_TAG_GPIO_SWITCH 0x4f06 31#define OMAP_TAG_GPIO_SWITCH 0x4f06
33#define OMAP_TAG_FBMEM 0x4f08
34#define OMAP_TAG_STI_CONSOLE 0x4f09 32#define OMAP_TAG_STI_CONSOLE 0x4f09
35#define OMAP_TAG_CAMERA_SENSOR 0x4f0a 33#define OMAP_TAG_CAMERA_SENSOR 0x4f0a
36 34
diff --git a/arch/arm/plat-omap/include/plat/hwa742.h b/arch/arm/plat-omap/include/plat/hwa742.h
deleted file mode 100644
index 886248d32b49..000000000000
--- a/arch/arm/plat-omap/include/plat/hwa742.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef _HWA742_H
2#define _HWA742_H
3
4struct hwa742_platform_data {
5 unsigned te_connected:1;
6};
7
8#endif
diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h
index 2efd6454bce0..37bbbbb981b2 100644
--- a/arch/arm/plat-omap/include/plat/irqs.h
+++ b/arch/arm/plat-omap/include/plat/irqs.h
@@ -428,8 +428,16 @@
428#define OMAP_GPMC_NR_IRQS 8 428#define OMAP_GPMC_NR_IRQS 8
429#define OMAP_GPMC_IRQ_END (OMAP_GPMC_IRQ_BASE + OMAP_GPMC_NR_IRQS) 429#define OMAP_GPMC_IRQ_END (OMAP_GPMC_IRQ_BASE + OMAP_GPMC_NR_IRQS)
430 430
431/* PRCM IRQ handler */
432#ifdef CONFIG_ARCH_OMAP2PLUS
433#define OMAP_PRCM_IRQ_BASE (OMAP_GPMC_IRQ_END)
434#define OMAP_PRCM_NR_IRQS 64
435#define OMAP_PRCM_IRQ_END (OMAP_PRCM_IRQ_BASE + OMAP_PRCM_NR_IRQS)
436#else
437#define OMAP_PRCM_IRQ_END OMAP_GPMC_IRQ_END
438#endif
431 439
432#define NR_IRQS OMAP_GPMC_IRQ_END 440#define NR_IRQS OMAP_PRCM_IRQ_END
433 441
434#define OMAP_IRQ_BIT(irq) (1 << ((irq) % 32)) 442#define OMAP_IRQ_BIT(irq) (1 << ((irq) % 32))
435 443
diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h
index 8fa74e2c9d6e..18814127809a 100644
--- a/arch/arm/plat-omap/include/plat/mcbsp.h
+++ b/arch/arm/plat-omap/include/plat/mcbsp.h
@@ -27,271 +27,10 @@
27#include <linux/spinlock.h> 27#include <linux/spinlock.h>
28#include <linux/clk.h> 28#include <linux/clk.h>
29 29
30/* macro for building platform_device for McBSP ports */
31#define OMAP_MCBSP_PLATFORM_DEVICE(port_nr) \
32static struct platform_device omap_mcbsp##port_nr = { \
33 .name = "omap-mcbsp-dai", \
34 .id = port_nr - 1, \
35}
36
37#define MCBSP_CONFIG_TYPE2 0x2 30#define MCBSP_CONFIG_TYPE2 0x2
38#define MCBSP_CONFIG_TYPE3 0x3 31#define MCBSP_CONFIG_TYPE3 0x3
39#define MCBSP_CONFIG_TYPE4 0x4 32#define MCBSP_CONFIG_TYPE4 0x4
40 33
41/* McBSP register numbers. Register address offset = num * reg_step */
42enum {
43 /* Common registers */
44 OMAP_MCBSP_REG_SPCR2 = 4,
45 OMAP_MCBSP_REG_SPCR1,
46 OMAP_MCBSP_REG_RCR2,
47 OMAP_MCBSP_REG_RCR1,
48 OMAP_MCBSP_REG_XCR2,
49 OMAP_MCBSP_REG_XCR1,
50 OMAP_MCBSP_REG_SRGR2,
51 OMAP_MCBSP_REG_SRGR1,
52 OMAP_MCBSP_REG_MCR2,
53 OMAP_MCBSP_REG_MCR1,
54 OMAP_MCBSP_REG_RCERA,
55 OMAP_MCBSP_REG_RCERB,
56 OMAP_MCBSP_REG_XCERA,
57 OMAP_MCBSP_REG_XCERB,
58 OMAP_MCBSP_REG_PCR0,
59 OMAP_MCBSP_REG_RCERC,
60 OMAP_MCBSP_REG_RCERD,
61 OMAP_MCBSP_REG_XCERC,
62 OMAP_MCBSP_REG_XCERD,
63 OMAP_MCBSP_REG_RCERE,
64 OMAP_MCBSP_REG_RCERF,
65 OMAP_MCBSP_REG_XCERE,
66 OMAP_MCBSP_REG_XCERF,
67 OMAP_MCBSP_REG_RCERG,
68 OMAP_MCBSP_REG_RCERH,
69 OMAP_MCBSP_REG_XCERG,
70 OMAP_MCBSP_REG_XCERH,
71
72 /* OMAP1-OMAP2420 registers */
73 OMAP_MCBSP_REG_DRR2 = 0,
74 OMAP_MCBSP_REG_DRR1,
75 OMAP_MCBSP_REG_DXR2,
76 OMAP_MCBSP_REG_DXR1,
77
78 /* OMAP2430 and onwards */
79 OMAP_MCBSP_REG_DRR = 0,
80 OMAP_MCBSP_REG_DXR = 2,
81 OMAP_MCBSP_REG_SYSCON = 35,
82 OMAP_MCBSP_REG_THRSH2,
83 OMAP_MCBSP_REG_THRSH1,
84 OMAP_MCBSP_REG_IRQST = 40,
85 OMAP_MCBSP_REG_IRQEN,
86 OMAP_MCBSP_REG_WAKEUPEN,
87 OMAP_MCBSP_REG_XCCR,
88 OMAP_MCBSP_REG_RCCR,
89 OMAP_MCBSP_REG_XBUFFSTAT,
90 OMAP_MCBSP_REG_RBUFFSTAT,
91 OMAP_MCBSP_REG_SSELCR,
92};
93
94/* OMAP3 sidetone control registers */
95#define OMAP_ST_REG_REV 0x00
96#define OMAP_ST_REG_SYSCONFIG 0x10
97#define OMAP_ST_REG_IRQSTATUS 0x18
98#define OMAP_ST_REG_IRQENABLE 0x1C
99#define OMAP_ST_REG_SGAINCR 0x24
100#define OMAP_ST_REG_SFIRCR 0x28
101#define OMAP_ST_REG_SSELCR 0x2C
102
103/************************** McBSP SPCR1 bit definitions ***********************/
104#define RRST 0x0001
105#define RRDY 0x0002
106#define RFULL 0x0004
107#define RSYNC_ERR 0x0008
108#define RINTM(value) ((value)<<4) /* bits 4:5 */
109#define ABIS 0x0040
110#define DXENA 0x0080
111#define CLKSTP(value) ((value)<<11) /* bits 11:12 */
112#define RJUST(value) ((value)<<13) /* bits 13:14 */
113#define ALB 0x8000
114#define DLB 0x8000
115
116/************************** McBSP SPCR2 bit definitions ***********************/
117#define XRST 0x0001
118#define XRDY 0x0002
119#define XEMPTY 0x0004
120#define XSYNC_ERR 0x0008
121#define XINTM(value) ((value)<<4) /* bits 4:5 */
122#define GRST 0x0040
123#define FRST 0x0080
124#define SOFT 0x0100
125#define FREE 0x0200
126
127/************************** McBSP PCR bit definitions *************************/
128#define CLKRP 0x0001
129#define CLKXP 0x0002
130#define FSRP 0x0004
131#define FSXP 0x0008
132#define DR_STAT 0x0010
133#define DX_STAT 0x0020
134#define CLKS_STAT 0x0040
135#define SCLKME 0x0080
136#define CLKRM 0x0100
137#define CLKXM 0x0200
138#define FSRM 0x0400
139#define FSXM 0x0800
140#define RIOEN 0x1000
141#define XIOEN 0x2000
142#define IDLE_EN 0x4000
143
144/************************** McBSP RCR1 bit definitions ************************/
145#define RWDLEN1(value) ((value)<<5) /* Bits 5:7 */
146#define RFRLEN1(value) ((value)<<8) /* Bits 8:14 */
147
148/************************** McBSP XCR1 bit definitions ************************/
149#define XWDLEN1(value) ((value)<<5) /* Bits 5:7 */
150#define XFRLEN1(value) ((value)<<8) /* Bits 8:14 */
151
152/*************************** McBSP RCR2 bit definitions ***********************/
153#define RDATDLY(value) (value) /* Bits 0:1 */
154#define RFIG 0x0004
155#define RCOMPAND(value) ((value)<<3) /* Bits 3:4 */
156#define RWDLEN2(value) ((value)<<5) /* Bits 5:7 */
157#define RFRLEN2(value) ((value)<<8) /* Bits 8:14 */
158#define RPHASE 0x8000
159
160/*************************** McBSP XCR2 bit definitions ***********************/
161#define XDATDLY(value) (value) /* Bits 0:1 */
162#define XFIG 0x0004
163#define XCOMPAND(value) ((value)<<3) /* Bits 3:4 */
164#define XWDLEN2(value) ((value)<<5) /* Bits 5:7 */
165#define XFRLEN2(value) ((value)<<8) /* Bits 8:14 */
166#define XPHASE 0x8000
167
168/************************* McBSP SRGR1 bit definitions ************************/
169#define CLKGDV(value) (value) /* Bits 0:7 */
170#define FWID(value) ((value)<<8) /* Bits 8:15 */
171
172/************************* McBSP SRGR2 bit definitions ************************/
173#define FPER(value) (value) /* Bits 0:11 */
174#define FSGM 0x1000
175#define CLKSM 0x2000
176#define CLKSP 0x4000
177#define GSYNC 0x8000
178
179/************************* McBSP MCR1 bit definitions *************************/
180#define RMCM 0x0001
181#define RCBLK(value) ((value)<<2) /* Bits 2:4 */
182#define RPABLK(value) ((value)<<5) /* Bits 5:6 */
183#define RPBBLK(value) ((value)<<7) /* Bits 7:8 */
184
185/************************* McBSP MCR2 bit definitions *************************/
186#define XMCM(value) (value) /* Bits 0:1 */
187#define XCBLK(value) ((value)<<2) /* Bits 2:4 */
188#define XPABLK(value) ((value)<<5) /* Bits 5:6 */
189#define XPBBLK(value) ((value)<<7) /* Bits 7:8 */
190
191/*********************** McBSP XCCR bit definitions *************************/
192#define EXTCLKGATE 0x8000
193#define PPCONNECT 0x4000
194#define DXENDLY(value) ((value)<<12) /* Bits 12:13 */
195#define XFULL_CYCLE 0x0800
196#define DILB 0x0020
197#define XDMAEN 0x0008
198#define XDISABLE 0x0001
199
200/********************** McBSP RCCR bit definitions *************************/
201#define RFULL_CYCLE 0x0800
202#define RDMAEN 0x0008
203#define RDISABLE 0x0001
204
205/********************** McBSP SYSCONFIG bit definitions ********************/
206#define CLOCKACTIVITY(value) ((value)<<8)
207#define SIDLEMODE(value) ((value)<<3)
208#define ENAWAKEUP 0x0004
209#define SOFTRST 0x0002
210
211/********************** McBSP SSELCR bit definitions ***********************/
212#define SIDETONEEN 0x0400
213
214/********************** McBSP Sidetone SYSCONFIG bit definitions ***********/
215#define ST_AUTOIDLE 0x0001
216
217/********************** McBSP Sidetone SGAINCR bit definitions *************/
218#define ST_CH1GAIN(value) ((value<<16)) /* Bits 16:31 */
219#define ST_CH0GAIN(value) (value) /* Bits 0:15 */
220
221/********************** McBSP Sidetone SFIRCR bit definitions **************/
222#define ST_FIRCOEFF(value) (value) /* Bits 0:15 */
223
224/********************** McBSP Sidetone SSELCR bit definitions **************/
225#define ST_COEFFWRDONE 0x0004
226#define ST_COEFFWREN 0x0002
227#define ST_SIDETONEEN 0x0001
228
229/********************** McBSP DMA operating modes **************************/
230#define MCBSP_DMA_MODE_ELEMENT 0
231#define MCBSP_DMA_MODE_THRESHOLD 1
232#define MCBSP_DMA_MODE_FRAME 2
233
234/********************** McBSP WAKEUPEN bit definitions *********************/
235#define XEMPTYEOFEN 0x4000
236#define XRDYEN 0x0400
237#define XEOFEN 0x0200
238#define XFSXEN 0x0100
239#define XSYNCERREN 0x0080
240#define RRDYEN 0x0008
241#define REOFEN 0x0004
242#define RFSREN 0x0002
243#define RSYNCERREN 0x0001
244
245/* CLKR signal muxing options */
246#define CLKR_SRC_CLKR 0
247#define CLKR_SRC_CLKX 1
248
249/* FSR signal muxing options */
250#define FSR_SRC_FSR 0
251#define FSR_SRC_FSX 1
252
253/* McBSP functional clock sources */
254#define MCBSP_CLKS_PRCM_SRC 0
255#define MCBSP_CLKS_PAD_SRC 1
256
257/* we don't do multichannel for now */
258struct omap_mcbsp_reg_cfg {
259 u16 spcr2;
260 u16 spcr1;
261 u16 rcr2;
262 u16 rcr1;
263 u16 xcr2;
264 u16 xcr1;
265 u16 srgr2;
266 u16 srgr1;
267 u16 mcr2;
268 u16 mcr1;
269 u16 pcr0;
270 u16 rcerc;
271 u16 rcerd;
272 u16 xcerc;
273 u16 xcerd;
274 u16 rcere;
275 u16 rcerf;
276 u16 xcere;
277 u16 xcerf;
278 u16 rcerg;
279 u16 rcerh;
280 u16 xcerg;
281 u16 xcerh;
282 u16 xccr;
283 u16 rccr;
284};
285
286typedef enum {
287 OMAP_MCBSP_WORD_8 = 0,
288 OMAP_MCBSP_WORD_12,
289 OMAP_MCBSP_WORD_16,
290 OMAP_MCBSP_WORD_20,
291 OMAP_MCBSP_WORD_24,
292 OMAP_MCBSP_WORD_32,
293} omap_mcbsp_word_length;
294
295/* Platform specific configuration */ 34/* Platform specific configuration */
296struct omap_mcbsp_ops { 35struct omap_mcbsp_ops {
297 void (*request)(unsigned int); 36 void (*request)(unsigned int);
@@ -312,43 +51,6 @@ struct omap_mcbsp_platform_data {
312 int (*mux_signal)(struct device *dev, const char *signal, const char *src); 51 int (*mux_signal)(struct device *dev, const char *signal, const char *src);
313}; 52};
314 53
315struct omap_mcbsp_st_data {
316 void __iomem *io_base_st;
317 bool running;
318 bool enabled;
319 s16 taps[128]; /* Sidetone filter coefficients */
320 int nr_taps; /* Number of filter coefficients in use */
321 s16 ch0gain;
322 s16 ch1gain;
323};
324
325struct omap_mcbsp {
326 struct device *dev;
327 unsigned long phys_base;
328 unsigned long phys_dma_base;
329 void __iomem *io_base;
330 u8 id;
331 u8 free;
332
333 int rx_irq;
334 int tx_irq;
335
336 /* DMA stuff */
337 u8 dma_rx_sync;
338 u8 dma_tx_sync;
339
340 /* Protect the field .free, while checking if the mcbsp is in use */
341 spinlock_t lock;
342 struct omap_mcbsp_platform_data *pdata;
343 struct clk *fclk;
344 struct omap_mcbsp_st_data *st_data;
345 int dma_op_mode;
346 u16 max_tx_thres;
347 u16 max_rx_thres;
348 void *reg_cache;
349 int reg_cache_size;
350};
351
352/** 54/**
353 * omap_mcbsp_dev_attr - OMAP McBSP device attributes for omap_hwmod 55 * omap_mcbsp_dev_attr - OMAP McBSP device attributes for omap_hwmod
354 * @sidetone: name of the sidetone device 56 * @sidetone: name of the sidetone device
@@ -357,39 +59,4 @@ struct omap_mcbsp_dev_attr {
357 const char *sidetone; 59 const char *sidetone;
358}; 60};
359 61
360extern struct omap_mcbsp **mcbsp_ptr;
361extern int omap_mcbsp_count;
362
363int omap_mcbsp_init(void);
364void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config);
365void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold);
366void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold);
367u16 omap_mcbsp_get_max_tx_threshold(unsigned int id);
368u16 omap_mcbsp_get_max_rx_threshold(unsigned int id);
369u16 omap_mcbsp_get_fifo_size(unsigned int id);
370u16 omap_mcbsp_get_tx_delay(unsigned int id);
371u16 omap_mcbsp_get_rx_delay(unsigned int id);
372int omap_mcbsp_get_dma_op_mode(unsigned int id);
373int omap_mcbsp_request(unsigned int id);
374void omap_mcbsp_free(unsigned int id);
375void omap_mcbsp_start(unsigned int id, int tx, int rx);
376void omap_mcbsp_stop(unsigned int id, int tx, int rx);
377
378/* McBSP functional clock source changing function */
379extern int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id);
380
381/* McBSP signal muxing API */
382void omap2_mcbsp1_mux_clkr_src(u8 mux);
383void omap2_mcbsp1_mux_fsr_src(u8 mux);
384
385int omap_mcbsp_dma_ch_params(unsigned int id, unsigned int stream);
386int omap_mcbsp_dma_reg_params(unsigned int id, unsigned int stream);
387
388/* Sidetone specific API */
389int omap_st_set_chgain(unsigned int id, int channel, s16 chgain);
390int omap_st_get_chgain(unsigned int id, int channel, s16 *chgain);
391int omap_st_enable(unsigned int id);
392int omap_st_disable(unsigned int id);
393int omap_st_is_enabled(unsigned int id);
394
395#endif 62#endif
diff --git a/arch/arm/plat-omap/include/plat/omap-secure.h b/arch/arm/plat-omap/include/plat/omap-secure.h
index 64f9d1c7f1bb..8c7994ce9869 100644
--- a/arch/arm/plat-omap/include/plat/omap-secure.h
+++ b/arch/arm/plat-omap/include/plat/omap-secure.h
@@ -3,11 +3,17 @@
3 3
4#include <linux/types.h> 4#include <linux/types.h>
5 5
6#ifdef CONFIG_ARCH_OMAP2PLUS 6#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
7extern int omap_secure_ram_reserve_memblock(void); 7extern int omap_secure_ram_reserve_memblock(void);
8#else 8#else
9static inline void omap_secure_ram_reserve_memblock(void) 9static inline void omap_secure_ram_reserve_memblock(void)
10{ } 10{ }
11#endif 11#endif
12 12
13#ifdef CONFIG_OMAP4_ERRATA_I688
14extern int omap_barrier_reserve_memblock(void);
15#else
16static inline void omap_barrier_reserve_memblock(void)
17{ }
18#endif
13#endif /* __OMAP_SECURE_H__ */ 19#endif /* __OMAP_SECURE_H__ */
diff --git a/arch/arm/plat-omap/include/plat/omap4-keypad.h b/arch/arm/plat-omap/include/plat/omap4-keypad.h
index 9fe6c8783236..8ad0a377a54b 100644
--- a/arch/arm/plat-omap/include/plat/omap4-keypad.h
+++ b/arch/arm/plat-omap/include/plat/omap4-keypad.h
@@ -1,15 +1,6 @@
1#ifndef ARCH_ARM_PLAT_OMAP4_KEYPAD_H 1#ifndef ARCH_ARM_PLAT_OMAP4_KEYPAD_H
2#define ARCH_ARM_PLAT_OMAP4_KEYPAD_H 2#define ARCH_ARM_PLAT_OMAP4_KEYPAD_H
3 3
4#include <linux/input/matrix_keypad.h>
5
6struct omap4_keypad_platform_data {
7 const struct matrix_keymap_data *keymap_data;
8
9 u8 rows;
10 u8 cols;
11};
12
13extern int omap4_keyboard_init(struct omap4_keypad_platform_data *, 4extern int omap4_keyboard_init(struct omap4_keypad_platform_data *,
14 struct omap_board_data *); 5 struct omap_board_data *);
15#endif 6#endif
diff --git a/arch/arm/plat-omap/include/plat/vram.h b/arch/arm/plat-omap/include/plat/vram.h
index 0aa4ecd12c7d..4d65b7d06e6c 100644
--- a/arch/arm/plat-omap/include/plat/vram.h
+++ b/arch/arm/plat-omap/include/plat/vram.h
@@ -23,40 +23,21 @@
23 23
24#include <linux/types.h> 24#include <linux/types.h>
25 25
26#define OMAP_VRAM_MEMTYPE_SDRAM 0
27#define OMAP_VRAM_MEMTYPE_SRAM 1
28#define OMAP_VRAM_MEMTYPE_MAX 1
29
30extern int omap_vram_add_region(unsigned long paddr, size_t size); 26extern int omap_vram_add_region(unsigned long paddr, size_t size);
31extern int omap_vram_free(unsigned long paddr, size_t size); 27extern int omap_vram_free(unsigned long paddr, size_t size);
32extern int omap_vram_alloc(int mtype, size_t size, unsigned long *paddr); 28extern int omap_vram_alloc(size_t size, unsigned long *paddr);
33extern int omap_vram_reserve(unsigned long paddr, size_t size); 29extern int omap_vram_reserve(unsigned long paddr, size_t size);
34extern void omap_vram_get_info(unsigned long *vram, unsigned long *free_vram, 30extern void omap_vram_get_info(unsigned long *vram, unsigned long *free_vram,
35 unsigned long *largest_free_block); 31 unsigned long *largest_free_block);
36 32
37#ifdef CONFIG_OMAP2_VRAM 33#ifdef CONFIG_OMAP2_VRAM
38extern void omap_vram_set_sdram_vram(u32 size, u32 start); 34extern void omap_vram_set_sdram_vram(u32 size, u32 start);
39extern void omap_vram_set_sram_vram(u32 size, u32 start);
40 35
41extern void omap_vram_reserve_sdram_memblock(void); 36extern void omap_vram_reserve_sdram_memblock(void);
42extern unsigned long omap_vram_reserve_sram(unsigned long sram_pstart,
43 unsigned long sram_vstart,
44 unsigned long sram_size,
45 unsigned long pstart_avail,
46 unsigned long size_avail);
47#else 37#else
48static inline void omap_vram_set_sdram_vram(u32 size, u32 start) { } 38static inline void omap_vram_set_sdram_vram(u32 size, u32 start) { }
49static inline void omap_vram_set_sram_vram(u32 size, u32 start) { }
50 39
51static inline void omap_vram_reserve_sdram_memblock(void) { } 40static inline void omap_vram_reserve_sdram_memblock(void) { }
52static inline unsigned long omap_vram_reserve_sram(unsigned long sram_pstart,
53 unsigned long sram_vstart,
54 unsigned long sram_size,
55 unsigned long pstart_avail,
56 unsigned long size_avail)
57{
58 return 0;
59}
60#endif 41#endif
61 42
62#endif 43#endif
diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c
deleted file mode 100644
index 4b15cd7926d7..000000000000
--- a/arch/arm/plat-omap/mcbsp.c
+++ /dev/null
@@ -1,1361 +0,0 @@
1/*
2 * linux/arch/arm/plat-omap/mcbsp.c
3 *
4 * Copyright (C) 2004 Nokia Corporation
5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com>
6 *
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Multichannel mode not supported.
13 */
14
15#include <linux/module.h>
16#include <linux/init.h>
17#include <linux/device.h>
18#include <linux/platform_device.h>
19#include <linux/interrupt.h>
20#include <linux/err.h>
21#include <linux/clk.h>
22#include <linux/delay.h>
23#include <linux/io.h>
24#include <linux/slab.h>
25
26#include <plat/mcbsp.h>
27#include <linux/pm_runtime.h>
28
29struct omap_mcbsp **mcbsp_ptr;
30int omap_mcbsp_count;
31
32#define omap_mcbsp_check_valid_id(id) (id < omap_mcbsp_count)
33#define id_to_mcbsp_ptr(id) mcbsp_ptr[id];
34
35static void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
36{
37 void __iomem *addr = mcbsp->io_base + reg * mcbsp->pdata->reg_step;
38
39 if (mcbsp->pdata->reg_size == 2) {
40 ((u16 *)mcbsp->reg_cache)[reg] = (u16)val;
41 __raw_writew((u16)val, addr);
42 } else {
43 ((u32 *)mcbsp->reg_cache)[reg] = val;
44 __raw_writel(val, addr);
45 }
46}
47
48static int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache)
49{
50 void __iomem *addr = mcbsp->io_base + reg * mcbsp->pdata->reg_step;
51
52 if (mcbsp->pdata->reg_size == 2) {
53 return !from_cache ? __raw_readw(addr) :
54 ((u16 *)mcbsp->reg_cache)[reg];
55 } else {
56 return !from_cache ? __raw_readl(addr) :
57 ((u32 *)mcbsp->reg_cache)[reg];
58 }
59}
60
61static void omap_mcbsp_st_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
62{
63 __raw_writel(val, mcbsp->st_data->io_base_st + reg);
64}
65
66static int omap_mcbsp_st_read(struct omap_mcbsp *mcbsp, u16 reg)
67{
68 return __raw_readl(mcbsp->st_data->io_base_st + reg);
69}
70
71#define MCBSP_READ(mcbsp, reg) \
72 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 0)
73#define MCBSP_WRITE(mcbsp, reg, val) \
74 omap_mcbsp_write(mcbsp, OMAP_MCBSP_REG_##reg, val)
75#define MCBSP_READ_CACHE(mcbsp, reg) \
76 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 1)
77
78#define MCBSP_ST_READ(mcbsp, reg) \
79 omap_mcbsp_st_read(mcbsp, OMAP_ST_REG_##reg)
80#define MCBSP_ST_WRITE(mcbsp, reg, val) \
81 omap_mcbsp_st_write(mcbsp, OMAP_ST_REG_##reg, val)
82
83static void omap_mcbsp_dump_reg(u8 id)
84{
85 struct omap_mcbsp *mcbsp = id_to_mcbsp_ptr(id);
86
87 dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id);
88 dev_dbg(mcbsp->dev, "DRR2: 0x%04x\n",
89 MCBSP_READ(mcbsp, DRR2));
90 dev_dbg(mcbsp->dev, "DRR1: 0x%04x\n",
91 MCBSP_READ(mcbsp, DRR1));
92 dev_dbg(mcbsp->dev, "DXR2: 0x%04x\n",
93 MCBSP_READ(mcbsp, DXR2));
94 dev_dbg(mcbsp->dev, "DXR1: 0x%04x\n",
95 MCBSP_READ(mcbsp, DXR1));
96 dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n",
97 MCBSP_READ(mcbsp, SPCR2));
98 dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n",
99 MCBSP_READ(mcbsp, SPCR1));
100 dev_dbg(mcbsp->dev, "RCR2: 0x%04x\n",
101 MCBSP_READ(mcbsp, RCR2));
102 dev_dbg(mcbsp->dev, "RCR1: 0x%04x\n",
103 MCBSP_READ(mcbsp, RCR1));
104 dev_dbg(mcbsp->dev, "XCR2: 0x%04x\n",
105 MCBSP_READ(mcbsp, XCR2));
106 dev_dbg(mcbsp->dev, "XCR1: 0x%04x\n",
107 MCBSP_READ(mcbsp, XCR1));
108 dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n",
109 MCBSP_READ(mcbsp, SRGR2));
110 dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n",
111 MCBSP_READ(mcbsp, SRGR1));
112 dev_dbg(mcbsp->dev, "PCR0: 0x%04x\n",
113 MCBSP_READ(mcbsp, PCR0));
114 dev_dbg(mcbsp->dev, "***********************\n");
115}
116
117static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
118{
119 struct omap_mcbsp *mcbsp_tx = dev_id;
120 u16 irqst_spcr2;
121
122 irqst_spcr2 = MCBSP_READ(mcbsp_tx, SPCR2);
123 dev_dbg(mcbsp_tx->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2);
124
125 if (irqst_spcr2 & XSYNC_ERR) {
126 dev_err(mcbsp_tx->dev, "TX Frame Sync Error! : 0x%x\n",
127 irqst_spcr2);
128 /* Writing zero to XSYNC_ERR clears the IRQ */
129 MCBSP_WRITE(mcbsp_tx, SPCR2, MCBSP_READ_CACHE(mcbsp_tx, SPCR2));
130 }
131
132 return IRQ_HANDLED;
133}
134
135static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
136{
137 struct omap_mcbsp *mcbsp_rx = dev_id;
138 u16 irqst_spcr1;
139
140 irqst_spcr1 = MCBSP_READ(mcbsp_rx, SPCR1);
141 dev_dbg(mcbsp_rx->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1);
142
143 if (irqst_spcr1 & RSYNC_ERR) {
144 dev_err(mcbsp_rx->dev, "RX Frame Sync Error! : 0x%x\n",
145 irqst_spcr1);
146 /* Writing zero to RSYNC_ERR clears the IRQ */
147 MCBSP_WRITE(mcbsp_rx, SPCR1, MCBSP_READ_CACHE(mcbsp_rx, SPCR1));
148 }
149
150 return IRQ_HANDLED;
151}
152
153/*
154 * omap_mcbsp_config simply write a config to the
155 * appropriate McBSP.
156 * You either call this function or set the McBSP registers
157 * by yourself before calling omap_mcbsp_start().
158 */
159void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
160{
161 struct omap_mcbsp *mcbsp;
162
163 if (!omap_mcbsp_check_valid_id(id)) {
164 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
165 return;
166 }
167 mcbsp = id_to_mcbsp_ptr(id);
168
169 dev_dbg(mcbsp->dev, "Configuring McBSP%d phys_base: 0x%08lx\n",
170 mcbsp->id, mcbsp->phys_base);
171
172 /* We write the given config */
173 MCBSP_WRITE(mcbsp, SPCR2, config->spcr2);
174 MCBSP_WRITE(mcbsp, SPCR1, config->spcr1);
175 MCBSP_WRITE(mcbsp, RCR2, config->rcr2);
176 MCBSP_WRITE(mcbsp, RCR1, config->rcr1);
177 MCBSP_WRITE(mcbsp, XCR2, config->xcr2);
178 MCBSP_WRITE(mcbsp, XCR1, config->xcr1);
179 MCBSP_WRITE(mcbsp, SRGR2, config->srgr2);
180 MCBSP_WRITE(mcbsp, SRGR1, config->srgr1);
181 MCBSP_WRITE(mcbsp, MCR2, config->mcr2);
182 MCBSP_WRITE(mcbsp, MCR1, config->mcr1);
183 MCBSP_WRITE(mcbsp, PCR0, config->pcr0);
184 if (mcbsp->pdata->has_ccr) {
185 MCBSP_WRITE(mcbsp, XCCR, config->xccr);
186 MCBSP_WRITE(mcbsp, RCCR, config->rccr);
187 }
188}
189EXPORT_SYMBOL(omap_mcbsp_config);
190
191/**
192 * omap_mcbsp_dma_params - returns the dma channel number
193 * @id - mcbsp id
194 * @stream - indicates the direction of data flow (rx or tx)
195 *
196 * Returns the dma channel number for the rx channel or tx channel
197 * based on the value of @stream for the requested mcbsp given by @id
198 */
199int omap_mcbsp_dma_ch_params(unsigned int id, unsigned int stream)
200{
201 struct omap_mcbsp *mcbsp;
202
203 if (!omap_mcbsp_check_valid_id(id)) {
204 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
205 return -ENODEV;
206 }
207 mcbsp = id_to_mcbsp_ptr(id);
208
209 if (stream)
210 return mcbsp->dma_rx_sync;
211 else
212 return mcbsp->dma_tx_sync;
213}
214EXPORT_SYMBOL(omap_mcbsp_dma_ch_params);
215
216/**
217 * omap_mcbsp_dma_reg_params - returns the address of mcbsp data register
218 * @id - mcbsp id
219 * @stream - indicates the direction of data flow (rx or tx)
220 *
221 * Returns the address of mcbsp data transmit register or data receive register
222 * to be used by DMA for transferring/receiving data based on the value of
223 * @stream for the requested mcbsp given by @id
224 */
225int omap_mcbsp_dma_reg_params(unsigned int id, unsigned int stream)
226{
227 struct omap_mcbsp *mcbsp;
228 int data_reg;
229
230 if (!omap_mcbsp_check_valid_id(id)) {
231 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
232 return -ENODEV;
233 }
234 mcbsp = id_to_mcbsp_ptr(id);
235
236 if (mcbsp->pdata->reg_size == 2) {
237 if (stream)
238 data_reg = OMAP_MCBSP_REG_DRR1;
239 else
240 data_reg = OMAP_MCBSP_REG_DXR1;
241 } else {
242 if (stream)
243 data_reg = OMAP_MCBSP_REG_DRR;
244 else
245 data_reg = OMAP_MCBSP_REG_DXR;
246 }
247
248 return mcbsp->phys_dma_base + data_reg * mcbsp->pdata->reg_step;
249}
250EXPORT_SYMBOL(omap_mcbsp_dma_reg_params);
251
252static void omap_st_on(struct omap_mcbsp *mcbsp)
253{
254 unsigned int w;
255
256 if (mcbsp->pdata->enable_st_clock)
257 mcbsp->pdata->enable_st_clock(mcbsp->id, 1);
258
259 /* Enable McBSP Sidetone */
260 w = MCBSP_READ(mcbsp, SSELCR);
261 MCBSP_WRITE(mcbsp, SSELCR, w | SIDETONEEN);
262
263 /* Enable Sidetone from Sidetone Core */
264 w = MCBSP_ST_READ(mcbsp, SSELCR);
265 MCBSP_ST_WRITE(mcbsp, SSELCR, w | ST_SIDETONEEN);
266}
267
268static void omap_st_off(struct omap_mcbsp *mcbsp)
269{
270 unsigned int w;
271
272 w = MCBSP_ST_READ(mcbsp, SSELCR);
273 MCBSP_ST_WRITE(mcbsp, SSELCR, w & ~(ST_SIDETONEEN));
274
275 w = MCBSP_READ(mcbsp, SSELCR);
276 MCBSP_WRITE(mcbsp, SSELCR, w & ~(SIDETONEEN));
277
278 if (mcbsp->pdata->enable_st_clock)
279 mcbsp->pdata->enable_st_clock(mcbsp->id, 0);
280}
281
282static void omap_st_fir_write(struct omap_mcbsp *mcbsp, s16 *fir)
283{
284 u16 val, i;
285
286 val = MCBSP_ST_READ(mcbsp, SSELCR);
287
288 if (val & ST_COEFFWREN)
289 MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
290
291 MCBSP_ST_WRITE(mcbsp, SSELCR, val | ST_COEFFWREN);
292
293 for (i = 0; i < 128; i++)
294 MCBSP_ST_WRITE(mcbsp, SFIRCR, fir[i]);
295
296 i = 0;
297
298 val = MCBSP_ST_READ(mcbsp, SSELCR);
299 while (!(val & ST_COEFFWRDONE) && (++i < 1000))
300 val = MCBSP_ST_READ(mcbsp, SSELCR);
301
302 MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
303
304 if (i == 1000)
305 dev_err(mcbsp->dev, "McBSP FIR load error!\n");
306}
307
308static void omap_st_chgain(struct omap_mcbsp *mcbsp)
309{
310 u16 w;
311 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
312
313 w = MCBSP_ST_READ(mcbsp, SSELCR);
314
315 MCBSP_ST_WRITE(mcbsp, SGAINCR, ST_CH0GAIN(st_data->ch0gain) | \
316 ST_CH1GAIN(st_data->ch1gain));
317}
318
319int omap_st_set_chgain(unsigned int id, int channel, s16 chgain)
320{
321 struct omap_mcbsp *mcbsp;
322 struct omap_mcbsp_st_data *st_data;
323 int ret = 0;
324
325 if (!omap_mcbsp_check_valid_id(id)) {
326 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
327 return -ENODEV;
328 }
329
330 mcbsp = id_to_mcbsp_ptr(id);
331 st_data = mcbsp->st_data;
332
333 if (!st_data)
334 return -ENOENT;
335
336 spin_lock_irq(&mcbsp->lock);
337 if (channel == 0)
338 st_data->ch0gain = chgain;
339 else if (channel == 1)
340 st_data->ch1gain = chgain;
341 else
342 ret = -EINVAL;
343
344 if (st_data->enabled)
345 omap_st_chgain(mcbsp);
346 spin_unlock_irq(&mcbsp->lock);
347
348 return ret;
349}
350EXPORT_SYMBOL(omap_st_set_chgain);
351
352int omap_st_get_chgain(unsigned int id, int channel, s16 *chgain)
353{
354 struct omap_mcbsp *mcbsp;
355 struct omap_mcbsp_st_data *st_data;
356 int ret = 0;
357
358 if (!omap_mcbsp_check_valid_id(id)) {
359 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
360 return -ENODEV;
361 }
362
363 mcbsp = id_to_mcbsp_ptr(id);
364 st_data = mcbsp->st_data;
365
366 if (!st_data)
367 return -ENOENT;
368
369 spin_lock_irq(&mcbsp->lock);
370 if (channel == 0)
371 *chgain = st_data->ch0gain;
372 else if (channel == 1)
373 *chgain = st_data->ch1gain;
374 else
375 ret = -EINVAL;
376 spin_unlock_irq(&mcbsp->lock);
377
378 return ret;
379}
380EXPORT_SYMBOL(omap_st_get_chgain);
381
382static int omap_st_start(struct omap_mcbsp *mcbsp)
383{
384 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
385
386 if (st_data && st_data->enabled && !st_data->running) {
387 omap_st_fir_write(mcbsp, st_data->taps);
388 omap_st_chgain(mcbsp);
389
390 if (!mcbsp->free) {
391 omap_st_on(mcbsp);
392 st_data->running = 1;
393 }
394 }
395
396 return 0;
397}
398
399int omap_st_enable(unsigned int id)
400{
401 struct omap_mcbsp *mcbsp;
402 struct omap_mcbsp_st_data *st_data;
403
404 if (!omap_mcbsp_check_valid_id(id)) {
405 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
406 return -ENODEV;
407 }
408
409 mcbsp = id_to_mcbsp_ptr(id);
410 st_data = mcbsp->st_data;
411
412 if (!st_data)
413 return -ENODEV;
414
415 spin_lock_irq(&mcbsp->lock);
416 st_data->enabled = 1;
417 omap_st_start(mcbsp);
418 spin_unlock_irq(&mcbsp->lock);
419
420 return 0;
421}
422EXPORT_SYMBOL(omap_st_enable);
423
424static int omap_st_stop(struct omap_mcbsp *mcbsp)
425{
426 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
427
428 if (st_data && st_data->running) {
429 if (!mcbsp->free) {
430 omap_st_off(mcbsp);
431 st_data->running = 0;
432 }
433 }
434
435 return 0;
436}
437
438int omap_st_disable(unsigned int id)
439{
440 struct omap_mcbsp *mcbsp;
441 struct omap_mcbsp_st_data *st_data;
442 int ret = 0;
443
444 if (!omap_mcbsp_check_valid_id(id)) {
445 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
446 return -ENODEV;
447 }
448
449 mcbsp = id_to_mcbsp_ptr(id);
450 st_data = mcbsp->st_data;
451
452 if (!st_data)
453 return -ENODEV;
454
455 spin_lock_irq(&mcbsp->lock);
456 omap_st_stop(mcbsp);
457 st_data->enabled = 0;
458 spin_unlock_irq(&mcbsp->lock);
459
460 return ret;
461}
462EXPORT_SYMBOL(omap_st_disable);
463
464int omap_st_is_enabled(unsigned int id)
465{
466 struct omap_mcbsp *mcbsp;
467 struct omap_mcbsp_st_data *st_data;
468
469 if (!omap_mcbsp_check_valid_id(id)) {
470 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
471 return -ENODEV;
472 }
473
474 mcbsp = id_to_mcbsp_ptr(id);
475 st_data = mcbsp->st_data;
476
477 if (!st_data)
478 return -ENODEV;
479
480
481 return st_data->enabled;
482}
483EXPORT_SYMBOL(omap_st_is_enabled);
484
485/*
486 * omap_mcbsp_set_rx_threshold configures the transmit threshold in words.
487 * The threshold parameter is 1 based, and it is converted (threshold - 1)
488 * for the THRSH2 register.
489 */
490void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
491{
492 struct omap_mcbsp *mcbsp;
493
494 if (!omap_mcbsp_check_valid_id(id)) {
495 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
496 return;
497 }
498 mcbsp = id_to_mcbsp_ptr(id);
499 if (mcbsp->pdata->buffer_size == 0)
500 return;
501
502 if (threshold && threshold <= mcbsp->max_tx_thres)
503 MCBSP_WRITE(mcbsp, THRSH2, threshold - 1);
504}
505EXPORT_SYMBOL(omap_mcbsp_set_tx_threshold);
506
507/*
508 * omap_mcbsp_set_rx_threshold configures the receive threshold in words.
509 * The threshold parameter is 1 based, and it is converted (threshold - 1)
510 * for the THRSH1 register.
511 */
512void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
513{
514 struct omap_mcbsp *mcbsp;
515
516 if (!omap_mcbsp_check_valid_id(id)) {
517 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
518 return;
519 }
520 mcbsp = id_to_mcbsp_ptr(id);
521 if (mcbsp->pdata->buffer_size == 0)
522 return;
523
524 if (threshold && threshold <= mcbsp->max_rx_thres)
525 MCBSP_WRITE(mcbsp, THRSH1, threshold - 1);
526}
527EXPORT_SYMBOL(omap_mcbsp_set_rx_threshold);
528
529/*
530 * omap_mcbsp_get_max_tx_thres just return the current configured
531 * maximum threshold for transmission
532 */
533u16 omap_mcbsp_get_max_tx_threshold(unsigned int id)
534{
535 struct omap_mcbsp *mcbsp;
536
537 if (!omap_mcbsp_check_valid_id(id)) {
538 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
539 return -ENODEV;
540 }
541 mcbsp = id_to_mcbsp_ptr(id);
542
543 return mcbsp->max_tx_thres;
544}
545EXPORT_SYMBOL(omap_mcbsp_get_max_tx_threshold);
546
547/*
548 * omap_mcbsp_get_max_rx_thres just return the current configured
549 * maximum threshold for reception
550 */
551u16 omap_mcbsp_get_max_rx_threshold(unsigned int id)
552{
553 struct omap_mcbsp *mcbsp;
554
555 if (!omap_mcbsp_check_valid_id(id)) {
556 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
557 return -ENODEV;
558 }
559 mcbsp = id_to_mcbsp_ptr(id);
560
561 return mcbsp->max_rx_thres;
562}
563EXPORT_SYMBOL(omap_mcbsp_get_max_rx_threshold);
564
565u16 omap_mcbsp_get_fifo_size(unsigned int id)
566{
567 struct omap_mcbsp *mcbsp;
568
569 if (!omap_mcbsp_check_valid_id(id)) {
570 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
571 return -ENODEV;
572 }
573 mcbsp = id_to_mcbsp_ptr(id);
574
575 return mcbsp->pdata->buffer_size;
576}
577EXPORT_SYMBOL(omap_mcbsp_get_fifo_size);
578
579/*
580 * omap_mcbsp_get_tx_delay returns the number of used slots in the McBSP FIFO
581 */
582u16 omap_mcbsp_get_tx_delay(unsigned int id)
583{
584 struct omap_mcbsp *mcbsp;
585 u16 buffstat;
586
587 if (!omap_mcbsp_check_valid_id(id)) {
588 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
589 return -ENODEV;
590 }
591 mcbsp = id_to_mcbsp_ptr(id);
592 if (mcbsp->pdata->buffer_size == 0)
593 return 0;
594
595 /* Returns the number of free locations in the buffer */
596 buffstat = MCBSP_READ(mcbsp, XBUFFSTAT);
597
598 /* Number of slots are different in McBSP ports */
599 return mcbsp->pdata->buffer_size - buffstat;
600}
601EXPORT_SYMBOL(omap_mcbsp_get_tx_delay);
602
603/*
604 * omap_mcbsp_get_rx_delay returns the number of free slots in the McBSP FIFO
605 * to reach the threshold value (when the DMA will be triggered to read it)
606 */
607u16 omap_mcbsp_get_rx_delay(unsigned int id)
608{
609 struct omap_mcbsp *mcbsp;
610 u16 buffstat, threshold;
611
612 if (!omap_mcbsp_check_valid_id(id)) {
613 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
614 return -ENODEV;
615 }
616 mcbsp = id_to_mcbsp_ptr(id);
617 if (mcbsp->pdata->buffer_size == 0)
618 return 0;
619
620 /* Returns the number of used locations in the buffer */
621 buffstat = MCBSP_READ(mcbsp, RBUFFSTAT);
622 /* RX threshold */
623 threshold = MCBSP_READ(mcbsp, THRSH1);
624
625 /* Return the number of location till we reach the threshold limit */
626 if (threshold <= buffstat)
627 return 0;
628 else
629 return threshold - buffstat;
630}
631EXPORT_SYMBOL(omap_mcbsp_get_rx_delay);
632
633/*
634 * omap_mcbsp_get_dma_op_mode just return the current configured
635 * operating mode for the mcbsp channel
636 */
637int omap_mcbsp_get_dma_op_mode(unsigned int id)
638{
639 struct omap_mcbsp *mcbsp;
640 int dma_op_mode;
641
642 if (!omap_mcbsp_check_valid_id(id)) {
643 printk(KERN_ERR "%s: Invalid id (%u)\n", __func__, id + 1);
644 return -ENODEV;
645 }
646 mcbsp = id_to_mcbsp_ptr(id);
647
648 dma_op_mode = mcbsp->dma_op_mode;
649
650 return dma_op_mode;
651}
652EXPORT_SYMBOL(omap_mcbsp_get_dma_op_mode);
653
654int omap_mcbsp_request(unsigned int id)
655{
656 struct omap_mcbsp *mcbsp;
657 void *reg_cache;
658 int err;
659
660 if (!omap_mcbsp_check_valid_id(id)) {
661 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
662 return -ENODEV;
663 }
664 mcbsp = id_to_mcbsp_ptr(id);
665
666 reg_cache = kzalloc(mcbsp->reg_cache_size, GFP_KERNEL);
667 if (!reg_cache) {
668 return -ENOMEM;
669 }
670
671 spin_lock(&mcbsp->lock);
672 if (!mcbsp->free) {
673 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
674 mcbsp->id);
675 err = -EBUSY;
676 goto err_kfree;
677 }
678
679 mcbsp->free = false;
680 mcbsp->reg_cache = reg_cache;
681 spin_unlock(&mcbsp->lock);
682
683 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request)
684 mcbsp->pdata->ops->request(id);
685
686 pm_runtime_get_sync(mcbsp->dev);
687
688 /* Enable wakeup behavior */
689 if (mcbsp->pdata->has_wakeup)
690 MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN);
691
692 /*
693 * Make sure that transmitter, receiver and sample-rate generator are
694 * not running before activating IRQs.
695 */
696 MCBSP_WRITE(mcbsp, SPCR1, 0);
697 MCBSP_WRITE(mcbsp, SPCR2, 0);
698
699 err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler,
700 0, "McBSP", (void *)mcbsp);
701 if (err != 0) {
702 dev_err(mcbsp->dev, "Unable to request TX IRQ %d "
703 "for McBSP%d\n", mcbsp->tx_irq,
704 mcbsp->id);
705 goto err_clk_disable;
706 }
707
708 if (mcbsp->rx_irq) {
709 err = request_irq(mcbsp->rx_irq,
710 omap_mcbsp_rx_irq_handler,
711 0, "McBSP", (void *)mcbsp);
712 if (err != 0) {
713 dev_err(mcbsp->dev, "Unable to request RX IRQ %d "
714 "for McBSP%d\n", mcbsp->rx_irq,
715 mcbsp->id);
716 goto err_free_irq;
717 }
718 }
719
720 return 0;
721err_free_irq:
722 free_irq(mcbsp->tx_irq, (void *)mcbsp);
723err_clk_disable:
724 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
725 mcbsp->pdata->ops->free(id);
726
727 /* Disable wakeup behavior */
728 if (mcbsp->pdata->has_wakeup)
729 MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
730
731 pm_runtime_put_sync(mcbsp->dev);
732
733 spin_lock(&mcbsp->lock);
734 mcbsp->free = true;
735 mcbsp->reg_cache = NULL;
736err_kfree:
737 spin_unlock(&mcbsp->lock);
738 kfree(reg_cache);
739
740 return err;
741}
742EXPORT_SYMBOL(omap_mcbsp_request);
743
744void omap_mcbsp_free(unsigned int id)
745{
746 struct omap_mcbsp *mcbsp;
747 void *reg_cache;
748
749 if (!omap_mcbsp_check_valid_id(id)) {
750 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
751 return;
752 }
753 mcbsp = id_to_mcbsp_ptr(id);
754
755 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
756 mcbsp->pdata->ops->free(id);
757
758 /* Disable wakeup behavior */
759 if (mcbsp->pdata->has_wakeup)
760 MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
761
762 pm_runtime_put_sync(mcbsp->dev);
763
764 if (mcbsp->rx_irq)
765 free_irq(mcbsp->rx_irq, (void *)mcbsp);
766 free_irq(mcbsp->tx_irq, (void *)mcbsp);
767
768 reg_cache = mcbsp->reg_cache;
769
770 spin_lock(&mcbsp->lock);
771 if (mcbsp->free)
772 dev_err(mcbsp->dev, "McBSP%d was not reserved\n", mcbsp->id);
773 else
774 mcbsp->free = true;
775 mcbsp->reg_cache = NULL;
776 spin_unlock(&mcbsp->lock);
777
778 if (reg_cache)
779 kfree(reg_cache);
780}
781EXPORT_SYMBOL(omap_mcbsp_free);
782
783/*
784 * Here we start the McBSP, by enabling transmitter, receiver or both.
785 * If no transmitter or receiver is active prior calling, then sample-rate
786 * generator and frame sync are started.
787 */
788void omap_mcbsp_start(unsigned int id, int tx, int rx)
789{
790 struct omap_mcbsp *mcbsp;
791 int enable_srg = 0;
792 u16 w;
793
794 if (!omap_mcbsp_check_valid_id(id)) {
795 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
796 return;
797 }
798 mcbsp = id_to_mcbsp_ptr(id);
799
800 if (mcbsp->st_data)
801 omap_st_start(mcbsp);
802
803 /* Only enable SRG, if McBSP is master */
804 w = MCBSP_READ_CACHE(mcbsp, PCR0);
805 if (w & (FSXM | FSRM | CLKXM | CLKRM))
806 enable_srg = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
807 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
808
809 if (enable_srg) {
810 /* Start the sample generator */
811 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
812 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 6));
813 }
814
815 /* Enable transmitter and receiver */
816 tx &= 1;
817 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
818 MCBSP_WRITE(mcbsp, SPCR2, w | tx);
819
820 rx &= 1;
821 w = MCBSP_READ_CACHE(mcbsp, SPCR1);
822 MCBSP_WRITE(mcbsp, SPCR1, w | rx);
823
824 /*
825 * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec
826 * REVISIT: 100us may give enough time for two CLKSRG, however
827 * due to some unknown PM related, clock gating etc. reason it
828 * is now at 500us.
829 */
830 udelay(500);
831
832 if (enable_srg) {
833 /* Start frame sync */
834 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
835 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7));
836 }
837
838 if (mcbsp->pdata->has_ccr) {
839 /* Release the transmitter and receiver */
840 w = MCBSP_READ_CACHE(mcbsp, XCCR);
841 w &= ~(tx ? XDISABLE : 0);
842 MCBSP_WRITE(mcbsp, XCCR, w);
843 w = MCBSP_READ_CACHE(mcbsp, RCCR);
844 w &= ~(rx ? RDISABLE : 0);
845 MCBSP_WRITE(mcbsp, RCCR, w);
846 }
847
848 /* Dump McBSP Regs */
849 omap_mcbsp_dump_reg(id);
850}
851EXPORT_SYMBOL(omap_mcbsp_start);
852
853void omap_mcbsp_stop(unsigned int id, int tx, int rx)
854{
855 struct omap_mcbsp *mcbsp;
856 int idle;
857 u16 w;
858
859 if (!omap_mcbsp_check_valid_id(id)) {
860 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
861 return;
862 }
863
864 mcbsp = id_to_mcbsp_ptr(id);
865
866 /* Reset transmitter */
867 tx &= 1;
868 if (mcbsp->pdata->has_ccr) {
869 w = MCBSP_READ_CACHE(mcbsp, XCCR);
870 w |= (tx ? XDISABLE : 0);
871 MCBSP_WRITE(mcbsp, XCCR, w);
872 }
873 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
874 MCBSP_WRITE(mcbsp, SPCR2, w & ~tx);
875
876 /* Reset receiver */
877 rx &= 1;
878 if (mcbsp->pdata->has_ccr) {
879 w = MCBSP_READ_CACHE(mcbsp, RCCR);
880 w |= (rx ? RDISABLE : 0);
881 MCBSP_WRITE(mcbsp, RCCR, w);
882 }
883 w = MCBSP_READ_CACHE(mcbsp, SPCR1);
884 MCBSP_WRITE(mcbsp, SPCR1, w & ~rx);
885
886 idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
887 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
888
889 if (idle) {
890 /* Reset the sample rate generator */
891 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
892 MCBSP_WRITE(mcbsp, SPCR2, w & ~(1 << 6));
893 }
894
895 if (mcbsp->st_data)
896 omap_st_stop(mcbsp);
897}
898EXPORT_SYMBOL(omap_mcbsp_stop);
899
900int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id)
901{
902 struct omap_mcbsp *mcbsp;
903 const char *src;
904
905 if (!omap_mcbsp_check_valid_id(id)) {
906 pr_err("%s: Invalid id (%d)\n", __func__, id + 1);
907 return -EINVAL;
908 }
909 mcbsp = id_to_mcbsp_ptr(id);
910
911 if (fck_src_id == MCBSP_CLKS_PAD_SRC)
912 src = "clks_ext";
913 else if (fck_src_id == MCBSP_CLKS_PRCM_SRC)
914 src = "clks_fclk";
915 else
916 return -EINVAL;
917
918 if (mcbsp->pdata->set_clk_src)
919 return mcbsp->pdata->set_clk_src(mcbsp->dev, mcbsp->fclk, src);
920 else
921 return -EINVAL;
922}
923EXPORT_SYMBOL(omap2_mcbsp_set_clks_src);
924
925void omap2_mcbsp1_mux_clkr_src(u8 mux)
926{
927 struct omap_mcbsp *mcbsp;
928 const char *src;
929
930 if (mux == CLKR_SRC_CLKR)
931 src = "clkr";
932 else if (mux == CLKR_SRC_CLKX)
933 src = "clkx";
934 else
935 return;
936
937 mcbsp = id_to_mcbsp_ptr(0);
938 if (mcbsp->pdata->mux_signal)
939 mcbsp->pdata->mux_signal(mcbsp->dev, "clkr", src);
940}
941EXPORT_SYMBOL(omap2_mcbsp1_mux_clkr_src);
942
943void omap2_mcbsp1_mux_fsr_src(u8 mux)
944{
945 struct omap_mcbsp *mcbsp;
946 const char *src;
947
948 if (mux == FSR_SRC_FSR)
949 src = "fsr";
950 else if (mux == FSR_SRC_FSX)
951 src = "fsx";
952 else
953 return;
954
955 mcbsp = id_to_mcbsp_ptr(0);
956 if (mcbsp->pdata->mux_signal)
957 mcbsp->pdata->mux_signal(mcbsp->dev, "fsr", src);
958}
959EXPORT_SYMBOL(omap2_mcbsp1_mux_fsr_src);
960
961#define max_thres(m) (mcbsp->pdata->buffer_size)
962#define valid_threshold(m, val) ((val) <= max_thres(m))
963#define THRESHOLD_PROP_BUILDER(prop) \
964static ssize_t prop##_show(struct device *dev, \
965 struct device_attribute *attr, char *buf) \
966{ \
967 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
968 \
969 return sprintf(buf, "%u\n", mcbsp->prop); \
970} \
971 \
972static ssize_t prop##_store(struct device *dev, \
973 struct device_attribute *attr, \
974 const char *buf, size_t size) \
975{ \
976 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
977 unsigned long val; \
978 int status; \
979 \
980 status = strict_strtoul(buf, 0, &val); \
981 if (status) \
982 return status; \
983 \
984 if (!valid_threshold(mcbsp, val)) \
985 return -EDOM; \
986 \
987 mcbsp->prop = val; \
988 return size; \
989} \
990 \
991static DEVICE_ATTR(prop, 0644, prop##_show, prop##_store);
992
993THRESHOLD_PROP_BUILDER(max_tx_thres);
994THRESHOLD_PROP_BUILDER(max_rx_thres);
995
996static const char *dma_op_modes[] = {
997 "element", "threshold", "frame",
998};
999
1000static ssize_t dma_op_mode_show(struct device *dev,
1001 struct device_attribute *attr, char *buf)
1002{
1003 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1004 int dma_op_mode, i = 0;
1005 ssize_t len = 0;
1006 const char * const *s;
1007
1008 dma_op_mode = mcbsp->dma_op_mode;
1009
1010 for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++) {
1011 if (dma_op_mode == i)
1012 len += sprintf(buf + len, "[%s] ", *s);
1013 else
1014 len += sprintf(buf + len, "%s ", *s);
1015 }
1016 len += sprintf(buf + len, "\n");
1017
1018 return len;
1019}
1020
1021static ssize_t dma_op_mode_store(struct device *dev,
1022 struct device_attribute *attr,
1023 const char *buf, size_t size)
1024{
1025 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1026 const char * const *s;
1027 int i = 0;
1028
1029 for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++)
1030 if (sysfs_streq(buf, *s))
1031 break;
1032
1033 if (i == ARRAY_SIZE(dma_op_modes))
1034 return -EINVAL;
1035
1036 spin_lock_irq(&mcbsp->lock);
1037 if (!mcbsp->free) {
1038 size = -EBUSY;
1039 goto unlock;
1040 }
1041 mcbsp->dma_op_mode = i;
1042
1043unlock:
1044 spin_unlock_irq(&mcbsp->lock);
1045
1046 return size;
1047}
1048
1049static DEVICE_ATTR(dma_op_mode, 0644, dma_op_mode_show, dma_op_mode_store);
1050
1051static const struct attribute *additional_attrs[] = {
1052 &dev_attr_max_tx_thres.attr,
1053 &dev_attr_max_rx_thres.attr,
1054 &dev_attr_dma_op_mode.attr,
1055 NULL,
1056};
1057
1058static const struct attribute_group additional_attr_group = {
1059 .attrs = (struct attribute **)additional_attrs,
1060};
1061
1062static ssize_t st_taps_show(struct device *dev,
1063 struct device_attribute *attr, char *buf)
1064{
1065 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1066 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1067 ssize_t status = 0;
1068 int i;
1069
1070 spin_lock_irq(&mcbsp->lock);
1071 for (i = 0; i < st_data->nr_taps; i++)
1072 status += sprintf(&buf[status], (i ? ", %d" : "%d"),
1073 st_data->taps[i]);
1074 if (i)
1075 status += sprintf(&buf[status], "\n");
1076 spin_unlock_irq(&mcbsp->lock);
1077
1078 return status;
1079}
1080
1081static ssize_t st_taps_store(struct device *dev,
1082 struct device_attribute *attr,
1083 const char *buf, size_t size)
1084{
1085 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1086 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1087 int val, tmp, status, i = 0;
1088
1089 spin_lock_irq(&mcbsp->lock);
1090 memset(st_data->taps, 0, sizeof(st_data->taps));
1091 st_data->nr_taps = 0;
1092
1093 do {
1094 status = sscanf(buf, "%d%n", &val, &tmp);
1095 if (status < 0 || status == 0) {
1096 size = -EINVAL;
1097 goto out;
1098 }
1099 if (val < -32768 || val > 32767) {
1100 size = -EINVAL;
1101 goto out;
1102 }
1103 st_data->taps[i++] = val;
1104 buf += tmp;
1105 if (*buf != ',')
1106 break;
1107 buf++;
1108 } while (1);
1109
1110 st_data->nr_taps = i;
1111
1112out:
1113 spin_unlock_irq(&mcbsp->lock);
1114
1115 return size;
1116}
1117
1118static DEVICE_ATTR(st_taps, 0644, st_taps_show, st_taps_store);
1119
1120static const struct attribute *sidetone_attrs[] = {
1121 &dev_attr_st_taps.attr,
1122 NULL,
1123};
1124
1125static const struct attribute_group sidetone_attr_group = {
1126 .attrs = (struct attribute **)sidetone_attrs,
1127};
1128
1129static int __devinit omap_st_add(struct omap_mcbsp *mcbsp,
1130 struct resource *res)
1131{
1132 struct omap_mcbsp_st_data *st_data;
1133 int err;
1134
1135 st_data = kzalloc(sizeof(*mcbsp->st_data), GFP_KERNEL);
1136 if (!st_data) {
1137 err = -ENOMEM;
1138 goto err1;
1139 }
1140
1141 st_data->io_base_st = ioremap(res->start, resource_size(res));
1142 if (!st_data->io_base_st) {
1143 err = -ENOMEM;
1144 goto err2;
1145 }
1146
1147 err = sysfs_create_group(&mcbsp->dev->kobj, &sidetone_attr_group);
1148 if (err)
1149 goto err3;
1150
1151 mcbsp->st_data = st_data;
1152 return 0;
1153
1154err3:
1155 iounmap(st_data->io_base_st);
1156err2:
1157 kfree(st_data);
1158err1:
1159 return err;
1160
1161}
1162
1163static void __devexit omap_st_remove(struct omap_mcbsp *mcbsp)
1164{
1165 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1166
1167 sysfs_remove_group(&mcbsp->dev->kobj, &sidetone_attr_group);
1168 iounmap(st_data->io_base_st);
1169 kfree(st_data);
1170}
1171
1172/*
1173 * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
1174 * 730 has only 2 McBSP, and both of them are MPU peripherals.
1175 */
1176static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
1177{
1178 struct omap_mcbsp_platform_data *pdata = pdev->dev.platform_data;
1179 struct omap_mcbsp *mcbsp;
1180 int id = pdev->id - 1;
1181 struct resource *res;
1182 int ret = 0;
1183
1184 if (!pdata) {
1185 dev_err(&pdev->dev, "McBSP device initialized without"
1186 "platform data\n");
1187 ret = -EINVAL;
1188 goto exit;
1189 }
1190
1191 dev_dbg(&pdev->dev, "Initializing OMAP McBSP (%d).\n", pdev->id);
1192
1193 if (id >= omap_mcbsp_count) {
1194 dev_err(&pdev->dev, "Invalid McBSP device id (%d)\n", id);
1195 ret = -EINVAL;
1196 goto exit;
1197 }
1198
1199 mcbsp = kzalloc(sizeof(struct omap_mcbsp), GFP_KERNEL);
1200 if (!mcbsp) {
1201 ret = -ENOMEM;
1202 goto exit;
1203 }
1204
1205 spin_lock_init(&mcbsp->lock);
1206 mcbsp->id = id + 1;
1207 mcbsp->free = true;
1208
1209 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
1210 if (!res) {
1211 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1212 if (!res) {
1213 dev_err(&pdev->dev, "%s:mcbsp%d has invalid memory"
1214 "resource\n", __func__, pdev->id);
1215 ret = -ENOMEM;
1216 goto exit;
1217 }
1218 }
1219 mcbsp->phys_base = res->start;
1220 mcbsp->reg_cache_size = resource_size(res);
1221 mcbsp->io_base = ioremap(res->start, resource_size(res));
1222 if (!mcbsp->io_base) {
1223 ret = -ENOMEM;
1224 goto err_ioremap;
1225 }
1226
1227 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
1228 if (!res)
1229 mcbsp->phys_dma_base = mcbsp->phys_base;
1230 else
1231 mcbsp->phys_dma_base = res->start;
1232
1233 mcbsp->tx_irq = platform_get_irq_byname(pdev, "tx");
1234 mcbsp->rx_irq = platform_get_irq_byname(pdev, "rx");
1235
1236 /* From OMAP4 there will be a single irq line */
1237 if (mcbsp->tx_irq == -ENXIO)
1238 mcbsp->tx_irq = platform_get_irq(pdev, 0);
1239
1240 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
1241 if (!res) {
1242 dev_err(&pdev->dev, "%s:mcbsp%d has invalid rx DMA channel\n",
1243 __func__, pdev->id);
1244 ret = -ENODEV;
1245 goto err_res;
1246 }
1247 mcbsp->dma_rx_sync = res->start;
1248
1249 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
1250 if (!res) {
1251 dev_err(&pdev->dev, "%s:mcbsp%d has invalid tx DMA channel\n",
1252 __func__, pdev->id);
1253 ret = -ENODEV;
1254 goto err_res;
1255 }
1256 mcbsp->dma_tx_sync = res->start;
1257
1258 mcbsp->fclk = clk_get(&pdev->dev, "fck");
1259 if (IS_ERR(mcbsp->fclk)) {
1260 ret = PTR_ERR(mcbsp->fclk);
1261 dev_err(&pdev->dev, "unable to get fck: %d\n", ret);
1262 goto err_res;
1263 }
1264
1265 mcbsp->pdata = pdata;
1266 mcbsp->dev = &pdev->dev;
1267 mcbsp_ptr[id] = mcbsp;
1268 platform_set_drvdata(pdev, mcbsp);
1269 pm_runtime_enable(mcbsp->dev);
1270
1271 mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT;
1272 if (mcbsp->pdata->buffer_size) {
1273 /*
1274 * Initially configure the maximum thresholds to a safe value.
1275 * The McBSP FIFO usage with these values should not go under
1276 * 16 locations.
1277 * If the whole FIFO without safety buffer is used, than there
1278 * is a possibility that the DMA will be not able to push the
1279 * new data on time, causing channel shifts in runtime.
1280 */
1281 mcbsp->max_tx_thres = max_thres(mcbsp) - 0x10;
1282 mcbsp->max_rx_thres = max_thres(mcbsp) - 0x10;
1283
1284 ret = sysfs_create_group(&mcbsp->dev->kobj,
1285 &additional_attr_group);
1286 if (ret) {
1287 dev_err(mcbsp->dev,
1288 "Unable to create additional controls\n");
1289 goto err_thres;
1290 }
1291 } else {
1292 mcbsp->max_tx_thres = -EINVAL;
1293 mcbsp->max_rx_thres = -EINVAL;
1294 }
1295
1296 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sidetone");
1297 if (res) {
1298 ret = omap_st_add(mcbsp, res);
1299 if (ret) {
1300 dev_err(mcbsp->dev,
1301 "Unable to create sidetone controls\n");
1302 goto err_st;
1303 }
1304 }
1305
1306 return 0;
1307
1308err_st:
1309 if (mcbsp->pdata->buffer_size)
1310 sysfs_remove_group(&mcbsp->dev->kobj,
1311 &additional_attr_group);
1312err_thres:
1313 clk_put(mcbsp->fclk);
1314err_res:
1315 iounmap(mcbsp->io_base);
1316err_ioremap:
1317 kfree(mcbsp);
1318exit:
1319 return ret;
1320}
1321
1322static int __devexit omap_mcbsp_remove(struct platform_device *pdev)
1323{
1324 struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
1325
1326 platform_set_drvdata(pdev, NULL);
1327 if (mcbsp) {
1328
1329 if (mcbsp->pdata && mcbsp->pdata->ops &&
1330 mcbsp->pdata->ops->free)
1331 mcbsp->pdata->ops->free(mcbsp->id);
1332
1333 if (mcbsp->pdata->buffer_size)
1334 sysfs_remove_group(&mcbsp->dev->kobj,
1335 &additional_attr_group);
1336
1337 if (mcbsp->st_data)
1338 omap_st_remove(mcbsp);
1339
1340 clk_put(mcbsp->fclk);
1341
1342 iounmap(mcbsp->io_base);
1343 kfree(mcbsp);
1344 }
1345
1346 return 0;
1347}
1348
1349static struct platform_driver omap_mcbsp_driver = {
1350 .probe = omap_mcbsp_probe,
1351 .remove = __devexit_p(omap_mcbsp_remove),
1352 .driver = {
1353 .name = "omap-mcbsp",
1354 },
1355};
1356
1357int __init omap_mcbsp_init(void)
1358{
1359 /* Register the McBSP driver */
1360 return platform_driver_register(&omap_mcbsp_driver);
1361}
diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c
index e5a2fde29b19..089899a7db72 100644
--- a/arch/arm/plat-orion/common.c
+++ b/arch/arm/plat-orion/common.c
@@ -789,10 +789,7 @@ void __init orion_xor1_init(unsigned long mapbase_low,
789/***************************************************************************** 789/*****************************************************************************
790 * EHCI 790 * EHCI
791 ****************************************************************************/ 791 ****************************************************************************/
792static struct orion_ehci_data orion_ehci_data = { 792static struct orion_ehci_data orion_ehci_data;
793 .phy_version = EHCI_PHY_NA,
794};
795
796static u64 ehci_dmamask = DMA_BIT_MASK(32); 793static u64 ehci_dmamask = DMA_BIT_MASK(32);
797 794
798 795
@@ -812,8 +809,10 @@ static struct platform_device orion_ehci = {
812}; 809};
813 810
814void __init orion_ehci_init(unsigned long mapbase, 811void __init orion_ehci_init(unsigned long mapbase,
815 unsigned long irq) 812 unsigned long irq,
813 enum orion_ehci_phy_ver phy_version)
816{ 814{
815 orion_ehci_data.phy_version = phy_version;
817 fill_resources(&orion_ehci, orion_ehci_resources, mapbase, SZ_4K - 1, 816 fill_resources(&orion_ehci, orion_ehci_resources, mapbase, SZ_4K - 1,
818 irq); 817 irq);
819 818
diff --git a/arch/arm/plat-orion/include/plat/common.h b/arch/arm/plat-orion/include/plat/common.h
index 0fe08d77e835..a7fa005a5a0e 100644
--- a/arch/arm/plat-orion/include/plat/common.h
+++ b/arch/arm/plat-orion/include/plat/common.h
@@ -89,7 +89,8 @@ void __init orion_xor1_init(unsigned long mapbase_low,
89 unsigned long irq_1); 89 unsigned long irq_1);
90 90
91void __init orion_ehci_init(unsigned long mapbase, 91void __init orion_ehci_init(unsigned long mapbase,
92 unsigned long irq); 92 unsigned long irq,
93 enum orion_ehci_phy_ver phy_version);
93 94
94void __init orion_ehci_1_init(unsigned long mapbase, 95void __init orion_ehci_1_init(unsigned long mapbase,
95 unsigned long irq); 96 unsigned long irq);
diff --git a/arch/arm/plat-orion/mpp.c b/arch/arm/plat-orion/mpp.c
index 91553432711d..3b1e17bd3d17 100644
--- a/arch/arm/plat-orion/mpp.c
+++ b/arch/arm/plat-orion/mpp.c
@@ -64,8 +64,7 @@ void __init orion_mpp_conf(unsigned int *mpp_list, unsigned int variant_mask,
64 gpio_mode |= GPIO_INPUT_OK; 64 gpio_mode |= GPIO_INPUT_OK;
65 if (*mpp_list & MPP_OUTPUT_MASK) 65 if (*mpp_list & MPP_OUTPUT_MASK)
66 gpio_mode |= GPIO_OUTPUT_OK; 66 gpio_mode |= GPIO_OUTPUT_OK;
67 if (sel != 0) 67
68 gpio_mode = 0;
69 orion_gpio_set_valid(num, gpio_mode); 68 orion_gpio_set_valid(num, gpio_mode);
70 } 69 }
71 70
diff --git a/arch/arm/plat-s3c24xx/dma.c b/arch/arm/plat-s3c24xx/dma.c
index 9fe35348e03b..2bab4c99a234 100644
--- a/arch/arm/plat-s3c24xx/dma.c
+++ b/arch/arm/plat-s3c24xx/dma.c
@@ -1249,7 +1249,7 @@ static void s3c2410_dma_resume(void)
1249 struct s3c2410_dma_chan *cp = s3c2410_chans + dma_channels - 1; 1249 struct s3c2410_dma_chan *cp = s3c2410_chans + dma_channels - 1;
1250 int channel; 1250 int channel;
1251 1251
1252 for (channel = dma_channels - 1; channel >= 0; cp++, channel--) 1252 for (channel = dma_channels - 1; channel >= 0; cp--, channel--)
1253 s3c2410_dma_resume_chan(cp); 1253 s3c2410_dma_resume_chan(cp);
1254} 1254}
1255 1255
diff --git a/arch/arm/plat-s3c24xx/pm-simtec.c b/arch/arm/plat-s3c24xx/pm-simtec.c
index 68296b1fe7e5..699f93171297 100644
--- a/arch/arm/plat-s3c24xx/pm-simtec.c
+++ b/arch/arm/plat-s3c24xx/pm-simtec.c
@@ -52,7 +52,7 @@ static __init int pm_simtec_init(void)
52 !machine_is_aml_m5900()) 52 !machine_is_aml_m5900())
53 return 0; 53 return 0;
54 54
55 printk(KERN_INFO "Simtec Board Power Manangement" COPYRIGHT "\n"); 55 printk(KERN_INFO "Simtec Board Power Management" COPYRIGHT "\n");
56 56
57 gstatus4 = (__raw_readl(S3C2410_BANKCON7) & 0x3) << 30; 57 gstatus4 = (__raw_readl(S3C2410_BANKCON7) & 0x3) << 30;
58 gstatus4 |= (__raw_readl(S3C2410_BANKCON6) & 0x3) << 28; 58 gstatus4 |= (__raw_readl(S3C2410_BANKCON6) & 0x3) << 28;
diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
index 32a6e394db24..d21d744e4d99 100644
--- a/arch/arm/plat-samsung/devs.c
+++ b/arch/arm/plat-samsung/devs.c
@@ -468,8 +468,10 @@ void __init s3c_i2c0_set_platdata(struct s3c2410_platform_i2c *pd)
468{ 468{
469 struct s3c2410_platform_i2c *npd; 469 struct s3c2410_platform_i2c *npd;
470 470
471 if (!pd) 471 if (!pd) {
472 pd = &default_i2c_data; 472 pd = &default_i2c_data;
473 pd->bus_num = 0;
474 }
473 475
474 npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c), 476 npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
475 &s3c_device_i2c0); 477 &s3c_device_i2c0);
@@ -1407,7 +1409,7 @@ void __init s5p_ehci_set_platdata(struct s5p_ehci_platdata *pd)
1407 1409
1408#ifdef CONFIG_S3C_DEV_USB_HSOTG 1410#ifdef CONFIG_S3C_DEV_USB_HSOTG
1409static struct resource s3c_usb_hsotg_resources[] = { 1411static struct resource s3c_usb_hsotg_resources[] = {
1410 [0] = DEFINE_RES_MEM(S3C_PA_USB_HSOTG, SZ_16K), 1412 [0] = DEFINE_RES_MEM(S3C_PA_USB_HSOTG, SZ_128K),
1411 [1] = DEFINE_RES_IRQ(IRQ_OTG), 1413 [1] = DEFINE_RES_IRQ(IRQ_OTG),
1412}; 1414};
1413 1415
diff --git a/arch/arm/plat-samsung/include/plat/regs-fb.h b/arch/arm/plat-samsung/include/plat/regs-fb.h
index 8f39aa5b26ea..9a78012d6f43 100644
--- a/arch/arm/plat-samsung/include/plat/regs-fb.h
+++ b/arch/arm/plat-samsung/include/plat/regs-fb.h
@@ -91,6 +91,9 @@
91#define VIDCON1_VSTATUS_BACKPORCH (0x1 << 13) 91#define VIDCON1_VSTATUS_BACKPORCH (0x1 << 13)
92#define VIDCON1_VSTATUS_ACTIVE (0x2 << 13) 92#define VIDCON1_VSTATUS_ACTIVE (0x2 << 13)
93#define VIDCON1_VSTATUS_FRONTPORCH (0x0 << 13) 93#define VIDCON1_VSTATUS_FRONTPORCH (0x0 << 13)
94#define VIDCON1_VCLK_MASK (0x3 << 9)
95#define VIDCON1_VCLK_HOLD (0x0 << 9)
96#define VIDCON1_VCLK_RUN (0x1 << 9)
94 97
95#define VIDCON1_INV_VCLK (1 << 7) 98#define VIDCON1_INV_VCLK (1 << 7)
96#define VIDCON1_INV_HSYNC (1 << 6) 99#define VIDCON1_INV_HSYNC (1 << 6)
@@ -164,15 +167,17 @@
164#define VIDTCON1_HSPW(_x) ((_x) << 0) 167#define VIDTCON1_HSPW(_x) ((_x) << 0)
165 168
166#define VIDTCON2 (0x18) 169#define VIDTCON2 (0x18)
170#define VIDTCON2_LINEVAL_E(_x) ((((_x) & 0x800) >> 11) << 23)
167#define VIDTCON2_LINEVAL_MASK (0x7ff << 11) 171#define VIDTCON2_LINEVAL_MASK (0x7ff << 11)
168#define VIDTCON2_LINEVAL_SHIFT (11) 172#define VIDTCON2_LINEVAL_SHIFT (11)
169#define VIDTCON2_LINEVAL_LIMIT (0x7ff) 173#define VIDTCON2_LINEVAL_LIMIT (0x7ff)
170#define VIDTCON2_LINEVAL(_x) ((_x) << 11) 174#define VIDTCON2_LINEVAL(_x) (((_x) & 0x7ff) << 11)
171 175
176#define VIDTCON2_HOZVAL_E(_x) ((((_x) & 0x800) >> 11) << 22)
172#define VIDTCON2_HOZVAL_MASK (0x7ff << 0) 177#define VIDTCON2_HOZVAL_MASK (0x7ff << 0)
173#define VIDTCON2_HOZVAL_SHIFT (0) 178#define VIDTCON2_HOZVAL_SHIFT (0)
174#define VIDTCON2_HOZVAL_LIMIT (0x7ff) 179#define VIDTCON2_HOZVAL_LIMIT (0x7ff)
175#define VIDTCON2_HOZVAL(_x) ((_x) << 0) 180#define VIDTCON2_HOZVAL(_x) (((_x) & 0x7ff) << 0)
176 181
177/* WINCONx */ 182/* WINCONx */
178 183
@@ -228,25 +233,29 @@
228/* Local input channels (windows 0-2) */ 233/* Local input channels (windows 0-2) */
229#define SHADOWCON_CHx_LOCAL_ENABLE(_win) (1 << (5 + (_win))) 234#define SHADOWCON_CHx_LOCAL_ENABLE(_win) (1 << (5 + (_win)))
230 235
236#define VIDOSDxA_TOPLEFT_X_E(_x) ((((_x) & 0x800) >> 11) << 23)
231#define VIDOSDxA_TOPLEFT_X_MASK (0x7ff << 11) 237#define VIDOSDxA_TOPLEFT_X_MASK (0x7ff << 11)
232#define VIDOSDxA_TOPLEFT_X_SHIFT (11) 238#define VIDOSDxA_TOPLEFT_X_SHIFT (11)
233#define VIDOSDxA_TOPLEFT_X_LIMIT (0x7ff) 239#define VIDOSDxA_TOPLEFT_X_LIMIT (0x7ff)
234#define VIDOSDxA_TOPLEFT_X(_x) ((_x) << 11) 240#define VIDOSDxA_TOPLEFT_X(_x) (((_x) & 0x7ff) << 11)
235 241
242#define VIDOSDxA_TOPLEFT_Y_E(_x) ((((_x) & 0x800) >> 11) << 22)
236#define VIDOSDxA_TOPLEFT_Y_MASK (0x7ff << 0) 243#define VIDOSDxA_TOPLEFT_Y_MASK (0x7ff << 0)
237#define VIDOSDxA_TOPLEFT_Y_SHIFT (0) 244#define VIDOSDxA_TOPLEFT_Y_SHIFT (0)
238#define VIDOSDxA_TOPLEFT_Y_LIMIT (0x7ff) 245#define VIDOSDxA_TOPLEFT_Y_LIMIT (0x7ff)
239#define VIDOSDxA_TOPLEFT_Y(_x) ((_x) << 0) 246#define VIDOSDxA_TOPLEFT_Y(_x) (((_x) & 0x7ff) << 0)
240 247
248#define VIDOSDxB_BOTRIGHT_X_E(_x) ((((_x) & 0x800) >> 11) << 23)
241#define VIDOSDxB_BOTRIGHT_X_MASK (0x7ff << 11) 249#define VIDOSDxB_BOTRIGHT_X_MASK (0x7ff << 11)
242#define VIDOSDxB_BOTRIGHT_X_SHIFT (11) 250#define VIDOSDxB_BOTRIGHT_X_SHIFT (11)
243#define VIDOSDxB_BOTRIGHT_X_LIMIT (0x7ff) 251#define VIDOSDxB_BOTRIGHT_X_LIMIT (0x7ff)
244#define VIDOSDxB_BOTRIGHT_X(_x) ((_x) << 11) 252#define VIDOSDxB_BOTRIGHT_X(_x) (((_x) & 0x7ff) << 11)
245 253
254#define VIDOSDxB_BOTRIGHT_Y_E(_x) ((((_x) & 0x800) >> 11) << 22)
246#define VIDOSDxB_BOTRIGHT_Y_MASK (0x7ff << 0) 255#define VIDOSDxB_BOTRIGHT_Y_MASK (0x7ff << 0)
247#define VIDOSDxB_BOTRIGHT_Y_SHIFT (0) 256#define VIDOSDxB_BOTRIGHT_Y_SHIFT (0)
248#define VIDOSDxB_BOTRIGHT_Y_LIMIT (0x7ff) 257#define VIDOSDxB_BOTRIGHT_Y_LIMIT (0x7ff)
249#define VIDOSDxB_BOTRIGHT_Y(_x) ((_x) << 0) 258#define VIDOSDxB_BOTRIGHT_Y(_x) (((_x) & 0x7ff) << 0)
250 259
251/* For VIDOSD[1..4]C */ 260/* For VIDOSD[1..4]C */
252#define VIDISD14C_ALPHA0_R(_x) ((_x) << 20) 261#define VIDISD14C_ALPHA0_R(_x) ((_x) << 20)
@@ -278,15 +287,17 @@
278#define VIDW_BUF_END1(_buff) (0xD4 + ((_buff) * 8)) 287#define VIDW_BUF_END1(_buff) (0xD4 + ((_buff) * 8))
279#define VIDW_BUF_SIZE(_buff) (0x100 + ((_buff) * 4)) 288#define VIDW_BUF_SIZE(_buff) (0x100 + ((_buff) * 4))
280 289
290#define VIDW_BUF_SIZE_OFFSET_E(_x) ((((_x) & 0x2000) >> 13) << 27)
281#define VIDW_BUF_SIZE_OFFSET_MASK (0x1fff << 13) 291#define VIDW_BUF_SIZE_OFFSET_MASK (0x1fff << 13)
282#define VIDW_BUF_SIZE_OFFSET_SHIFT (13) 292#define VIDW_BUF_SIZE_OFFSET_SHIFT (13)
283#define VIDW_BUF_SIZE_OFFSET_LIMIT (0x1fff) 293#define VIDW_BUF_SIZE_OFFSET_LIMIT (0x1fff)
284#define VIDW_BUF_SIZE_OFFSET(_x) ((_x) << 13) 294#define VIDW_BUF_SIZE_OFFSET(_x) (((_x) & 0x1fff) << 13)
285 295
296#define VIDW_BUF_SIZE_PAGEWIDTH_E(_x) ((((_x) & 0x2000) >> 13) << 26)
286#define VIDW_BUF_SIZE_PAGEWIDTH_MASK (0x1fff << 0) 297#define VIDW_BUF_SIZE_PAGEWIDTH_MASK (0x1fff << 0)
287#define VIDW_BUF_SIZE_PAGEWIDTH_SHIFT (0) 298#define VIDW_BUF_SIZE_PAGEWIDTH_SHIFT (0)
288#define VIDW_BUF_SIZE_PAGEWIDTH_LIMIT (0x1fff) 299#define VIDW_BUF_SIZE_PAGEWIDTH_LIMIT (0x1fff)
289#define VIDW_BUF_SIZE_PAGEWIDTH(_x) ((_x) << 0) 300#define VIDW_BUF_SIZE_PAGEWIDTH(_x) (((_x) & 0x1fff) << 0)
290 301
291/* Interrupt controls and status */ 302/* Interrupt controls and status */
292 303
@@ -384,3 +395,9 @@
384#define WPALCON_W0PAL_16BPP_A555 (0x5 << 0) 395#define WPALCON_W0PAL_16BPP_A555 (0x5 << 0)
385#define WPALCON_W0PAL_16BPP_565 (0x6 << 0) 396#define WPALCON_W0PAL_16BPP_565 (0x6 << 0)
386 397
398/* Blending equation control */
399#define BLENDCON (0x260)
400#define BLENDCON_NEW_MASK (1 << 0)
401#define BLENDCON_NEW_8BIT_ALPHA_VALUE (1 << 0)
402#define BLENDCON_NEW_4BIT_ALPHA_VALUE (0 << 0)
403
diff --git a/arch/arm/plat-spear/include/plat/keyboard.h b/arch/arm/plat-spear/include/plat/keyboard.h
index 68b5394fc583..c16cc31ecbed 100644
--- a/arch/arm/plat-spear/include/plat/keyboard.h
+++ b/arch/arm/plat-spear/include/plat/keyboard.h
@@ -15,7 +15,7 @@
15#include <linux/input/matrix_keypad.h> 15#include <linux/input/matrix_keypad.h>
16#include <linux/types.h> 16#include <linux/types.h>
17 17
18#define DECLARE_KEYMAP(_name) \ 18#define DECLARE_9x9_KEYMAP(_name) \
19int _name[] = { \ 19int _name[] = { \
20 KEY(0, 0, KEY_ESC), \ 20 KEY(0, 0, KEY_ESC), \
21 KEY(0, 1, KEY_1), \ 21 KEY(0, 1, KEY_1), \
@@ -62,24 +62,6 @@ int _name[] = { \
62 KEY(4, 6, KEY_Z), \ 62 KEY(4, 6, KEY_Z), \
63 KEY(4, 7, KEY_X), \ 63 KEY(4, 7, KEY_X), \
64 KEY(4, 8, KEY_C), \ 64 KEY(4, 8, KEY_C), \
65 KEY(4, 0, KEY_L), \
66 KEY(4, 1, KEY_SEMICOLON), \
67 KEY(4, 2, KEY_APOSTROPHE), \
68 KEY(4, 3, KEY_GRAVE), \
69 KEY(4, 4, KEY_LEFTSHIFT), \
70 KEY(4, 5, KEY_BACKSLASH), \
71 KEY(4, 6, KEY_Z), \
72 KEY(4, 7, KEY_X), \
73 KEY(4, 8, KEY_C), \
74 KEY(4, 0, KEY_L), \
75 KEY(4, 1, KEY_SEMICOLON), \
76 KEY(4, 2, KEY_APOSTROPHE), \
77 KEY(4, 3, KEY_GRAVE), \
78 KEY(4, 4, KEY_LEFTSHIFT), \
79 KEY(4, 5, KEY_BACKSLASH), \
80 KEY(4, 6, KEY_Z), \
81 KEY(4, 7, KEY_X), \
82 KEY(4, 8, KEY_C), \
83 KEY(5, 0, KEY_V), \ 65 KEY(5, 0, KEY_V), \
84 KEY(5, 1, KEY_B), \ 66 KEY(5, 1, KEY_B), \
85 KEY(5, 2, KEY_N), \ 67 KEY(5, 2, KEY_N), \
@@ -118,10 +100,55 @@ int _name[] = { \
118 KEY(8, 8, KEY_KP0), \ 100 KEY(8, 8, KEY_KP0), \
119} 101}
120 102
103#define DECLARE_6x6_KEYMAP(_name) \
104int _name[] = { \
105 KEY(0, 0, KEY_RESERVED), \
106 KEY(0, 1, KEY_1), \
107 KEY(0, 2, KEY_2), \
108 KEY(0, 3, KEY_3), \
109 KEY(0, 4, KEY_4), \
110 KEY(0, 5, KEY_5), \
111 KEY(1, 0, KEY_Q), \
112 KEY(1, 1, KEY_W), \
113 KEY(1, 2, KEY_E), \
114 KEY(1, 3, KEY_R), \
115 KEY(1, 4, KEY_T), \
116 KEY(1, 5, KEY_Y), \
117 KEY(2, 0, KEY_D), \
118 KEY(2, 1, KEY_F), \
119 KEY(2, 2, KEY_G), \
120 KEY(2, 3, KEY_H), \
121 KEY(2, 4, KEY_J), \
122 KEY(2, 5, KEY_K), \
123 KEY(3, 0, KEY_B), \
124 KEY(3, 1, KEY_N), \
125 KEY(3, 2, KEY_M), \
126 KEY(3, 3, KEY_COMMA), \
127 KEY(3, 4, KEY_DOT), \
128 KEY(3, 5, KEY_SLASH), \
129 KEY(4, 0, KEY_F6), \
130 KEY(4, 1, KEY_F7), \
131 KEY(4, 2, KEY_F8), \
132 KEY(4, 3, KEY_F9), \
133 KEY(4, 4, KEY_F10), \
134 KEY(4, 5, KEY_NUMLOCK), \
135 KEY(5, 0, KEY_KP2), \
136 KEY(5, 1, KEY_KP3), \
137 KEY(5, 2, KEY_KP0), \
138 KEY(5, 3, KEY_KPDOT), \
139 KEY(5, 4, KEY_RO), \
140 KEY(5, 5, KEY_ZENKAKUHANKAKU), \
141}
142
143#define KEYPAD_9x9 0
144#define KEYPAD_6x6 1
145#define KEYPAD_2x2 2
146
121/** 147/**
122 * struct kbd_platform_data - spear keyboard platform data 148 * struct kbd_platform_data - spear keyboard platform data
123 * keymap: pointer to keymap data (table and size) 149 * keymap: pointer to keymap data (table and size)
124 * rep: enables key autorepeat 150 * rep: enables key autorepeat
151 * mode: choose keyboard support(9x9, 6x6, 2x2)
125 * 152 *
126 * This structure is supposed to be used by platform code to supply 153 * This structure is supposed to be used by platform code to supply
127 * keymaps to drivers that implement keyboards. 154 * keymaps to drivers that implement keyboards.
@@ -129,6 +156,7 @@ int _name[] = { \
129struct kbd_platform_data { 156struct kbd_platform_data {
130 const struct matrix_keymap_data *keymap; 157 const struct matrix_keymap_data *keymap;
131 bool rep; 158 bool rep;
159 unsigned int mode;
132}; 160};
133 161
134/* This function is used to set platform data field of pdev->dev */ 162/* This function is used to set platform data field of pdev->dev */
diff --git a/arch/arm/plat-spear/time.c b/arch/arm/plat-spear/time.c
index 0c77e4298675..abb5bdecd509 100644
--- a/arch/arm/plat-spear/time.c
+++ b/arch/arm/plat-spear/time.c
@@ -145,11 +145,13 @@ static void clockevent_set_mode(enum clock_event_mode mode,
145static int clockevent_next_event(unsigned long cycles, 145static int clockevent_next_event(unsigned long cycles,
146 struct clock_event_device *clk_event_dev) 146 struct clock_event_device *clk_event_dev)
147{ 147{
148 u16 val; 148 u16 val = readw(gpt_base + CR(CLKEVT));
149
150 if (val & CTRL_ENABLE)
151 writew(val & ~CTRL_ENABLE, gpt_base + CR(CLKEVT));
149 152
150 writew(cycles, gpt_base + LOAD(CLKEVT)); 153 writew(cycles, gpt_base + LOAD(CLKEVT));
151 154
152 val = readw(gpt_base + CR(CLKEVT));
153 val |= CTRL_ENABLE | CTRL_INT_ENABLE; 155 val |= CTRL_ENABLE | CTRL_INT_ENABLE;
154 writew(val, gpt_base + CR(CLKEVT)); 156 writew(val, gpt_base + CR(CLKEVT));
155 157
diff --git a/arch/arm/plat-versatile/platsmp.c b/arch/arm/plat-versatile/platsmp.c
index 92f18d372b69..49c7db48c7f1 100644
--- a/arch/arm/plat-versatile/platsmp.c
+++ b/arch/arm/plat-versatile/platsmp.c
@@ -16,6 +16,7 @@
16#include <linux/smp.h> 16#include <linux/smp.h>
17 17
18#include <asm/cacheflush.h> 18#include <asm/cacheflush.h>
19#include <asm/smp_plat.h>
19#include <asm/hardware/gic.h> 20#include <asm/hardware/gic.h>
20 21
21/* 22/*