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-rw-r--r--arch/arm/boot/compressed/head.S9
-rw-r--r--arch/arm/common/gic.c2
-rw-r--r--arch/arm/include/asm/pci.h13
-rw-r--r--arch/arm/include/asm/unistd.h2
-rw-r--r--arch/arm/kernel/calls.S2
-rw-r--r--arch/arm/kernel/init_task.c4
-rw-r--r--arch/arm/kernel/irq.c6
-rw-r--r--arch/arm/kernel/process.c19
-rw-r--r--arch/arm/kernel/unwind.c19
-rw-r--r--arch/arm/kernel/vmlinux.lds.S8
-rw-r--r--arch/arm/mach-omap2/clock.c2
-rw-r--r--arch/arm/mach-omap2/clock34xx.c42
-rw-r--r--arch/arm/mach-omap2/io.c36
-rw-r--r--arch/arm/mach-omap2/powerdomain.c2
-rw-r--r--arch/arm/mach-omap2/sram34xx.S129
-rw-r--r--arch/arm/mach-orion5x/addr-map.c2
-rw-r--r--arch/arm/mach-orion5x/common.c10
-rw-r--r--arch/arm/mach-orion5x/common.h1
-rw-r--r--arch/arm/mach-pxa/Kconfig10
-rw-r--r--arch/arm/mach-pxa/Makefile1
-rw-r--r--arch/arm/mach-pxa/corgi.c6
-rw-r--r--arch/arm/mach-pxa/em-x270.c63
-rw-r--r--arch/arm/mach-pxa/hx4700.c41
-rw-r--r--arch/arm/mach-pxa/include/mach/palmz72.h5
-rw-r--r--arch/arm/mach-pxa/include/mach/treo680.h49
-rw-r--r--arch/arm/mach-pxa/mioa701.c42
-rw-r--r--arch/arm/mach-pxa/palmz72.c65
-rw-r--r--arch/arm/mach-pxa/pcm990-baseboard.c23
-rw-r--r--arch/arm/mach-pxa/poodle.c6
-rw-r--r--arch/arm/mach-pxa/treo680.c612
-rw-r--r--arch/arm/mach-realview/realview_pbx.c1
-rw-r--r--arch/arm/mm/alignment.c139
-rw-r--r--arch/arm/mm/mmu.c7
-rw-r--r--arch/arm/plat-omap/include/mach/sram.h6
-rw-r--r--arch/arm/plat-omap/sram.c8
-rw-r--r--arch/arm/plat-s3c/include/plat/regs-usb-hsotg-phy.h50
-rw-r--r--arch/arm/plat-s3c/include/plat/regs-usb-hsotg.h377
-rw-r--r--arch/arm/tools/mach-types39
38 files changed, 1722 insertions, 136 deletions
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 01d49be3b2ca..4515728c5345 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -674,6 +674,15 @@ proc_types:
674 b __armv4_mmu_cache_off 674 b __armv4_mmu_cache_off
675 b __armv5tej_mmu_cache_flush 675 b __armv5tej_mmu_cache_flush
676 676
677#ifdef CONFIG_CPU_FEROCEON_OLD_ID
678 /* this conflicts with the standard ARMv5TE entry */
679 .long 0x41009260 @ Old Feroceon
680 .long 0xff00fff0
681 b __armv4_mmu_cache_on
682 b __armv4_mmu_cache_off
683 b __armv5tej_mmu_cache_flush
684#endif
685
677 .word 0x66015261 @ FA526 686 .word 0x66015261 @ FA526
678 .word 0xff01fff1 687 .word 0xff01fff1
679 b __fa526_cache_on 688 b __fa526_cache_on
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index 664c7b8b1ba8..337741f734ac 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -117,7 +117,7 @@ static int gic_set_cpu(unsigned int irq, const struct cpumask *mask_val)
117 u32 val; 117 u32 val;
118 118
119 spin_lock(&irq_controller_lock); 119 spin_lock(&irq_controller_lock);
120 irq_desc[irq].cpu = cpu; 120 irq_desc[irq].node = cpu;
121 val = readl(reg) & ~(0xff << shift); 121 val = readl(reg) & ~(0xff << shift);
122 val |= 1 << (cpu + shift); 122 val |= 1 << (cpu + shift);
123 writel(val, reg); 123 writel(val, reg);
diff --git a/arch/arm/include/asm/pci.h b/arch/arm/include/asm/pci.h
index 918d0cbbf064..0abf386ba3d3 100644
--- a/arch/arm/include/asm/pci.h
+++ b/arch/arm/include/asm/pci.h
@@ -65,19 +65,6 @@ extern void
65pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, 65pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
66 struct pci_bus_region *region); 66 struct pci_bus_region *region);
67 67
68static inline struct resource *
69pcibios_select_root(struct pci_dev *pdev, struct resource *res)
70{
71 struct resource *root = NULL;
72
73 if (res->flags & IORESOURCE_IO)
74 root = &ioport_resource;
75 if (res->flags & IORESOURCE_MEM)
76 root = &iomem_resource;
77
78 return root;
79}
80
81/* 68/*
82 * Dummy implementation; always return 0. 69 * Dummy implementation; always return 0.
83 */ 70 */
diff --git a/arch/arm/include/asm/unistd.h b/arch/arm/include/asm/unistd.h
index 94cc58ef61ae..0e97b8cb77d5 100644
--- a/arch/arm/include/asm/unistd.h
+++ b/arch/arm/include/asm/unistd.h
@@ -389,6 +389,8 @@
389#define __NR_inotify_init1 (__NR_SYSCALL_BASE+360) 389#define __NR_inotify_init1 (__NR_SYSCALL_BASE+360)
390#define __NR_preadv (__NR_SYSCALL_BASE+361) 390#define __NR_preadv (__NR_SYSCALL_BASE+361)
391#define __NR_pwritev (__NR_SYSCALL_BASE+362) 391#define __NR_pwritev (__NR_SYSCALL_BASE+362)
392#define __NR_rt_tgsigqueueinfo (__NR_SYSCALL_BASE+363)
393#define __NR_perf_counter_open (__NR_SYSCALL_BASE+364)
392 394
393/* 395/*
394 * The following SWIs are ARM private. 396 * The following SWIs are ARM private.
diff --git a/arch/arm/kernel/calls.S b/arch/arm/kernel/calls.S
index 1680e9e9c831..f776e72a4cb8 100644
--- a/arch/arm/kernel/calls.S
+++ b/arch/arm/kernel/calls.S
@@ -372,6 +372,8 @@
372/* 360 */ CALL(sys_inotify_init1) 372/* 360 */ CALL(sys_inotify_init1)
373 CALL(sys_preadv) 373 CALL(sys_preadv)
374 CALL(sys_pwritev) 374 CALL(sys_pwritev)
375 CALL(sys_rt_tgsigqueueinfo)
376 CALL(sys_perf_counter_open)
375#ifndef syscalls_counted 377#ifndef syscalls_counted
376.equ syscalls_padding, ((NR_syscalls + 3) & ~3) - NR_syscalls 378.equ syscalls_padding, ((NR_syscalls + 3) & ~3) - NR_syscalls
377#define syscalls_counted 379#define syscalls_counted
diff --git a/arch/arm/kernel/init_task.c b/arch/arm/kernel/init_task.c
index e859af349467..3f470866bb89 100644
--- a/arch/arm/kernel/init_task.c
+++ b/arch/arm/kernel/init_task.c
@@ -14,10 +14,6 @@
14 14
15static struct signal_struct init_signals = INIT_SIGNALS(init_signals); 15static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
16static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand); 16static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
17struct mm_struct init_mm = INIT_MM(init_mm);
18
19EXPORT_SYMBOL(init_mm);
20
21/* 17/*
22 * Initial thread structure. 18 * Initial thread structure.
23 * 19 *
diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c
index 6874c7dca75a..096f600dc8d8 100644
--- a/arch/arm/kernel/irq.c
+++ b/arch/arm/kernel/irq.c
@@ -167,7 +167,7 @@ void __init init_IRQ(void)
167 167
168#ifdef CONFIG_SMP 168#ifdef CONFIG_SMP
169 cpumask_setall(bad_irq_desc.affinity); 169 cpumask_setall(bad_irq_desc.affinity);
170 bad_irq_desc.cpu = smp_processor_id(); 170 bad_irq_desc.node = smp_processor_id();
171#endif 171#endif
172 init_arch_irq(); 172 init_arch_irq();
173} 173}
@@ -176,7 +176,7 @@ void __init init_IRQ(void)
176 176
177static void route_irq(struct irq_desc *desc, unsigned int irq, unsigned int cpu) 177static void route_irq(struct irq_desc *desc, unsigned int irq, unsigned int cpu)
178{ 178{
179 pr_debug("IRQ%u: moving from cpu%u to cpu%u\n", irq, desc->cpu, cpu); 179 pr_debug("IRQ%u: moving from cpu%u to cpu%u\n", irq, desc->node, cpu);
180 180
181 spin_lock_irq(&desc->lock); 181 spin_lock_irq(&desc->lock);
182 desc->chip->set_affinity(irq, cpumask_of(cpu)); 182 desc->chip->set_affinity(irq, cpumask_of(cpu));
@@ -195,7 +195,7 @@ void migrate_irqs(void)
195 for (i = 0; i < NR_IRQS; i++) { 195 for (i = 0; i < NR_IRQS; i++) {
196 struct irq_desc *desc = irq_desc + i; 196 struct irq_desc *desc = irq_desc + i;
197 197
198 if (desc->cpu == cpu) { 198 if (desc->node == cpu) {
199 unsigned int newcpu = cpumask_any_and(desc->affinity, 199 unsigned int newcpu = cpumask_any_and(desc->affinity,
200 cpu_online_mask); 200 cpu_online_mask);
201 if (newcpu >= nr_cpu_ids) { 201 if (newcpu >= nr_cpu_ids) {
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index 1585423699ee..56820cce91a4 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -352,6 +352,23 @@ asm( ".section .text\n"
352" .size kernel_thread_helper, . - kernel_thread_helper\n" 352" .size kernel_thread_helper, . - kernel_thread_helper\n"
353" .previous"); 353" .previous");
354 354
355#ifdef CONFIG_ARM_UNWIND
356extern void kernel_thread_exit(long code);
357asm( ".section .text\n"
358" .align\n"
359" .type kernel_thread_exit, #function\n"
360"kernel_thread_exit:\n"
361" .fnstart\n"
362" .cantunwind\n"
363" bl do_exit\n"
364" nop\n"
365" .fnend\n"
366" .size kernel_thread_exit, . - kernel_thread_exit\n"
367" .previous");
368#else
369#define kernel_thread_exit do_exit
370#endif
371
355/* 372/*
356 * Create a kernel thread. 373 * Create a kernel thread.
357 */ 374 */
@@ -363,7 +380,7 @@ pid_t kernel_thread(int (*fn)(void *), void *arg, unsigned long flags)
363 380
364 regs.ARM_r1 = (unsigned long)arg; 381 regs.ARM_r1 = (unsigned long)arg;
365 regs.ARM_r2 = (unsigned long)fn; 382 regs.ARM_r2 = (unsigned long)fn;
366 regs.ARM_r3 = (unsigned long)do_exit; 383 regs.ARM_r3 = (unsigned long)kernel_thread_exit;
367 regs.ARM_pc = (unsigned long)kernel_thread_helper; 384 regs.ARM_pc = (unsigned long)kernel_thread_helper;
368 regs.ARM_cpsr = SVC_MODE | PSR_ENDSTATE; 385 regs.ARM_cpsr = SVC_MODE | PSR_ENDSTATE;
369 386
diff --git a/arch/arm/kernel/unwind.c b/arch/arm/kernel/unwind.c
index 1dedc2c7ff49..dd56e11f339a 100644
--- a/arch/arm/kernel/unwind.c
+++ b/arch/arm/kernel/unwind.c
@@ -212,7 +212,8 @@ static int unwind_exec_insn(struct unwind_ctrl_block *ctrl)
212 ctrl->vrs[14] = *vsp++; 212 ctrl->vrs[14] = *vsp++;
213 ctrl->vrs[SP] = (unsigned long)vsp; 213 ctrl->vrs[SP] = (unsigned long)vsp;
214 } else if (insn == 0xb0) { 214 } else if (insn == 0xb0) {
215 ctrl->vrs[PC] = ctrl->vrs[LR]; 215 if (ctrl->vrs[PC] == 0)
216 ctrl->vrs[PC] = ctrl->vrs[LR];
216 /* no further processing */ 217 /* no further processing */
217 ctrl->entries = 0; 218 ctrl->entries = 0;
218 } else if (insn == 0xb1) { 219 } else if (insn == 0xb1) {
@@ -309,18 +310,20 @@ int unwind_frame(struct stackframe *frame)
309 } 310 }
310 311
311 while (ctrl.entries > 0) { 312 while (ctrl.entries > 0) {
312 int urc; 313 int urc = unwind_exec_insn(&ctrl);
313
314 if (ctrl.vrs[SP] < low || ctrl.vrs[SP] >= high)
315 return -URC_FAILURE;
316 urc = unwind_exec_insn(&ctrl);
317 if (urc < 0) 314 if (urc < 0)
318 return urc; 315 return urc;
316 if (ctrl.vrs[SP] < low || ctrl.vrs[SP] >= high)
317 return -URC_FAILURE;
319 } 318 }
320 319
321 if (ctrl.vrs[PC] == 0) 320 if (ctrl.vrs[PC] == 0)
322 ctrl.vrs[PC] = ctrl.vrs[LR]; 321 ctrl.vrs[PC] = ctrl.vrs[LR];
323 322
323 /* check for infinite loop */
324 if (frame->pc == ctrl.vrs[PC])
325 return -URC_FAILURE;
326
324 frame->fp = ctrl.vrs[FP]; 327 frame->fp = ctrl.vrs[FP];
325 frame->sp = ctrl.vrs[SP]; 328 frame->sp = ctrl.vrs[SP];
326 frame->lr = ctrl.vrs[LR]; 329 frame->lr = ctrl.vrs[LR];
@@ -332,7 +335,6 @@ int unwind_frame(struct stackframe *frame)
332void unwind_backtrace(struct pt_regs *regs, struct task_struct *tsk) 335void unwind_backtrace(struct pt_regs *regs, struct task_struct *tsk)
333{ 336{
334 struct stackframe frame; 337 struct stackframe frame;
335 unsigned long high, low;
336 register unsigned long current_sp asm ("sp"); 338 register unsigned long current_sp asm ("sp");
337 339
338 pr_debug("%s(regs = %p tsk = %p)\n", __func__, regs, tsk); 340 pr_debug("%s(regs = %p tsk = %p)\n", __func__, regs, tsk);
@@ -362,9 +364,6 @@ void unwind_backtrace(struct pt_regs *regs, struct task_struct *tsk)
362 frame.pc = thread_saved_pc(tsk); 364 frame.pc = thread_saved_pc(tsk);
363 } 365 }
364 366
365 low = frame.sp & ~(THREAD_SIZE - 1);
366 high = low + THREAD_SIZE;
367
368 while (1) { 367 while (1) {
369 int urc; 368 int urc;
370 unsigned long where = frame.pc; 369 unsigned long where = frame.pc;
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
index 6c0779792546..4340bf3d2c84 100644
--- a/arch/arm/kernel/vmlinux.lds.S
+++ b/arch/arm/kernel/vmlinux.lds.S
@@ -84,6 +84,14 @@ SECTIONS
84 *(.exitcall.exit) 84 *(.exitcall.exit)
85 *(.ARM.exidx.exit.text) 85 *(.ARM.exidx.exit.text)
86 *(.ARM.extab.exit.text) 86 *(.ARM.extab.exit.text)
87#ifndef CONFIG_HOTPLUG_CPU
88 *(.ARM.exidx.cpuexit.text)
89 *(.ARM.extab.cpuexit.text)
90#endif
91#ifndef CONFIG_HOTPLUG
92 *(.ARM.exidx.devexit.text)
93 *(.ARM.extab.devexit.text)
94#endif
87#ifndef CONFIG_MMU 95#ifndef CONFIG_MMU
88 *(.fixup) 96 *(.fixup)
89 *(__ex_table) 97 *(__ex_table)
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index ba528f85749c..b0665f161c03 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -302,7 +302,7 @@ int omap2_wait_clock_ready(void __iomem *reg, u32 mask, const char *name)
302 udelay(1); 302 udelay(1);
303 } 303 }
304 304
305 if (i < MAX_CLOCK_ENABLE_WAIT) 305 if (i <= MAX_CLOCK_ENABLE_WAIT)
306 pr_debug("Clock %s stable after %d loops\n", name, i); 306 pr_debug("Clock %s stable after %d loops\n", name, i);
307 else 307 else
308 printk(KERN_ERR "Clock %s didn't enable in %d tries\n", 308 printk(KERN_ERR "Clock %s didn't enable in %d tries\n",
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index 9e43fe5209d3..045da923e75b 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -286,6 +286,20 @@ static struct omap_clk omap34xx_clks[] = {
286 286
287#define MIN_SDRC_DLL_LOCK_FREQ 83000000 287#define MIN_SDRC_DLL_LOCK_FREQ 83000000
288 288
289#define CYCLES_PER_MHZ 1000000
290
291/* Scale factor for fixed-point arith in omap3_core_dpll_m2_set_rate() */
292#define SDRC_MPURATE_SCALE 8
293
294/* 2^SDRC_MPURATE_BASE_SHIFT: MPU MHz that SDRC_MPURATE_LOOPS is defined for */
295#define SDRC_MPURATE_BASE_SHIFT 9
296
297/*
298 * SDRC_MPURATE_LOOPS: Number of MPU loops to execute at
299 * 2^MPURATE_BASE_SHIFT MHz for SDRC to stabilize
300 */
301#define SDRC_MPURATE_LOOPS 96
302
289/** 303/**
290 * omap3_dpll_recalc - recalculate DPLL rate 304 * omap3_dpll_recalc - recalculate DPLL rate
291 * @clk: DPLL struct clk 305 * @clk: DPLL struct clk
@@ -709,7 +723,8 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
709{ 723{
710 u32 new_div = 0; 724 u32 new_div = 0;
711 u32 unlock_dll = 0; 725 u32 unlock_dll = 0;
712 unsigned long validrate, sdrcrate; 726 u32 c;
727 unsigned long validrate, sdrcrate, mpurate;
713 struct omap_sdrc_params *sp; 728 struct omap_sdrc_params *sp;
714 729
715 if (!clk || !rate) 730 if (!clk || !rate)
@@ -718,18 +733,15 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
718 if (clk != &dpll3_m2_ck) 733 if (clk != &dpll3_m2_ck)
719 return -EINVAL; 734 return -EINVAL;
720 735
721 if (rate == clk->rate)
722 return 0;
723
724 validrate = omap2_clksel_round_rate_div(clk, rate, &new_div); 736 validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
725 if (validrate != rate) 737 if (validrate != rate)
726 return -EINVAL; 738 return -EINVAL;
727 739
728 sdrcrate = sdrc_ick.rate; 740 sdrcrate = sdrc_ick.rate;
729 if (rate > clk->rate) 741 if (rate > clk->rate)
730 sdrcrate <<= ((rate / clk->rate) - 1); 742 sdrcrate <<= ((rate / clk->rate) >> 1);
731 else 743 else
732 sdrcrate >>= ((clk->rate / rate) - 1); 744 sdrcrate >>= ((clk->rate / rate) >> 1);
733 745
734 sp = omap2_sdrc_get_params(sdrcrate); 746 sp = omap2_sdrc_get_params(sdrcrate);
735 if (!sp) 747 if (!sp)
@@ -740,17 +752,25 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
740 unlock_dll = 1; 752 unlock_dll = 1;
741 } 753 }
742 754
755 /*
756 * XXX This only needs to be done when the CPU frequency changes
757 */
758 mpurate = arm_fck.rate / CYCLES_PER_MHZ;
759 c = (mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT;
760 c += 1; /* for safety */
761 c *= SDRC_MPURATE_LOOPS;
762 c >>= SDRC_MPURATE_SCALE;
763 if (c == 0)
764 c = 1;
765
743 pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate, 766 pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
744 validrate); 767 validrate);
745 pr_debug("clock: SDRC timing params used: %08x %08x %08x\n", 768 pr_debug("clock: SDRC timing params used: %08x %08x %08x\n",
746 sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb); 769 sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb);
747 770
748 /* REVISIT: SRAM code doesn't support other M2 divisors yet */
749 WARN_ON(new_div != 1 && new_div != 2);
750
751 /* REVISIT: Add SDRC_MR changing to this code also */
752 omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla, 771 omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla,
753 sp->actim_ctrlb, new_div, unlock_dll); 772 sp->actim_ctrlb, new_div, unlock_dll, c,
773 sp->mr, rate > clk->rate);
754 774
755 return 0; 775 return 0;
756} 776}
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 32afd9448216..3a86b0f66031 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -21,6 +21,7 @@
21#include <linux/kernel.h> 21#include <linux/kernel.h>
22#include <linux/init.h> 22#include <linux/init.h>
23#include <linux/io.h> 23#include <linux/io.h>
24#include <linux/clk.h>
24 25
25#include <asm/tlb.h> 26#include <asm/tlb.h>
26 27
@@ -241,6 +242,40 @@ void __init omap2_map_common_io(void)
241 omapfb_reserve_sdram(); 242 omapfb_reserve_sdram();
242} 243}
243 244
245/*
246 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
247 *
248 * Sets the CORE DPLL3 M2 divider to the same value that it's at
249 * currently. This has the effect of setting the SDRC SDRAM AC timing
250 * registers to the values currently defined by the kernel. Currently
251 * only defined for OMAP3; will return 0 if called on OMAP2. Returns
252 * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
253 * or passes along the return value of clk_set_rate().
254 */
255static int __init _omap2_init_reprogram_sdrc(void)
256{
257 struct clk *dpll3_m2_ck;
258 int v = -EINVAL;
259 long rate;
260
261 if (!cpu_is_omap34xx())
262 return 0;
263
264 dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
265 if (!dpll3_m2_ck)
266 return -EINVAL;
267
268 rate = clk_get_rate(dpll3_m2_ck);
269 pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
270 v = clk_set_rate(dpll3_m2_ck, rate);
271 if (v)
272 pr_err("dpll3_m2_clk rate change failed: %d\n", v);
273
274 clk_put(dpll3_m2_ck);
275
276 return v;
277}
278
244void __init omap2_init_common_hw(struct omap_sdrc_params *sp) 279void __init omap2_init_common_hw(struct omap_sdrc_params *sp)
245{ 280{
246 omap2_mux_init(); 281 omap2_mux_init();
@@ -249,6 +284,7 @@ void __init omap2_init_common_hw(struct omap_sdrc_params *sp)
249 clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps); 284 clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps);
250 omap2_clk_init(); 285 omap2_clk_init();
251 omap2_sdrc_init(sp); 286 omap2_sdrc_init(sp);
287 _omap2_init_reprogram_sdrc();
252#endif 288#endif
253 gpmc_init(); 289 gpmc_init();
254} 290}
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index 73e2971b1757..983f1cb676be 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -1099,7 +1099,7 @@ int pwrdm_wait_transition(struct powerdomain *pwrdm)
1099 (c++ < PWRDM_TRANSITION_BAILOUT)) 1099 (c++ < PWRDM_TRANSITION_BAILOUT))
1100 udelay(1); 1100 udelay(1);
1101 1101
1102 if (c >= PWRDM_TRANSITION_BAILOUT) { 1102 if (c > PWRDM_TRANSITION_BAILOUT) {
1103 printk(KERN_ERR "powerdomain: waited too long for " 1103 printk(KERN_ERR "powerdomain: waited too long for "
1104 "powerdomain %s to complete transition\n", pwrdm->name); 1104 "powerdomain %s to complete transition\n", pwrdm->name);
1105 return -EAGAIN; 1105 return -EAGAIN;
diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S
index c080c82521e1..f41f8d96ddba 100644
--- a/arch/arm/mach-omap2/sram34xx.S
+++ b/arch/arm/mach-omap2/sram34xx.S
@@ -3,13 +3,12 @@
3 * 3 *
4 * Omap3 specific functions that need to be run in internal SRAM 4 * Omap3 specific functions that need to be run in internal SRAM
5 * 5 *
6 * (C) Copyright 2007 6 * Copyright (C) 2004, 2007, 2008 Texas Instruments, Inc.
7 * Texas Instruments Inc. 7 * Copyright (C) 2008 Nokia Corporation
8 * Rajendra Nayak <rnayak@ti.com>
9 * 8 *
10 * (C) Copyright 2004 9 * Rajendra Nayak <rnayak@ti.com>
11 * Texas Instruments, <www.ti.com>
12 * Richard Woodruff <r-woodruff2@ti.com> 10 * Richard Woodruff <r-woodruff2@ti.com>
11 * Paul Walmsley
13 * 12 *
14 * This program is free software; you can redistribute it and/or 13 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as 14 * modify it under the terms of the GNU General Public License as
@@ -37,61 +36,112 @@
37 36
38 .text 37 .text
39 38
39/* r4 parameters */
40#define SDRC_NO_UNLOCK_DLL 0x0
41#define SDRC_UNLOCK_DLL 0x1
42
43/* SDRC_DLLA_CTRL bit settings */
44#define FIXEDDELAY_SHIFT 24
45#define FIXEDDELAY_MASK (0xff << FIXEDDELAY_SHIFT)
46#define DLLIDLE_MASK 0x4
47
48/*
49 * SDRC_DLLA_CTRL default values: TI hardware team indicates that
50 * FIXEDDELAY should be initialized to 0xf. This apparently was
51 * empirically determined during process testing, so no derivation
52 * was provided.
53 */
54#define FIXEDDELAY_DEFAULT (0x0f << FIXEDDELAY_SHIFT)
55
56/* SDRC_DLLA_STATUS bit settings */
57#define LOCKSTATUS_MASK 0x4
58
59/* SDRC_POWER bit settings */
60#define SRFRONIDLEREQ_MASK 0x40
61#define PWDENA_MASK 0x4
62
63/* CM_IDLEST1_CORE bit settings */
64#define ST_SDRC_MASK 0x2
65
66/* CM_ICLKEN1_CORE bit settings */
67#define EN_SDRC_MASK 0x2
68
69/* CM_CLKSEL1_PLL bit settings */
70#define CORE_DPLL_CLKOUT_DIV_SHIFT 0x1b
71
40/* 72/*
41 * Change frequency of core dpll 73 * omap3_sram_configure_core_dpll - change DPLL3 M2 divider
42 * r0 = sdrc_rfr_ctrl r1 = sdrc_actim_ctrla r2 = sdrc_actim_ctrlb r3 = M2 74 * r0 = new SDRC_RFR_CTRL register contents
43 * r4 = Unlock SDRC DLL? (1 = yes, 0 = no) -- only unlock DLL for 75 * r1 = new SDRC_ACTIM_CTRLA register contents
76 * r2 = new SDRC_ACTIM_CTRLB register contents
77 * r3 = new M2 divider setting (only 1 and 2 supported right now)
78 * r4 = unlock SDRC DLL? (1 = yes, 0 = no). Only unlock DLL for
44 * SDRC rates < 83MHz 79 * SDRC rates < 83MHz
80 * r5 = number of MPU cycles to wait for SDRC to stabilize after
81 * reprogramming the SDRC when switching to a slower MPU speed
82 * r6 = new SDRC_MR_0 register value
83 * r7 = increasing SDRC rate? (1 = yes, 0 = no)
84 *
45 */ 85 */
46ENTRY(omap3_sram_configure_core_dpll) 86ENTRY(omap3_sram_configure_core_dpll)
47 stmfd sp!, {r1-r12, lr} @ store regs to stack 87 stmfd sp!, {r1-r12, lr} @ store regs to stack
48 ldr r4, [sp, #52] @ pull extra args off the stack 88 ldr r4, [sp, #52] @ pull extra args off the stack
89 ldr r5, [sp, #56] @ load extra args from the stack
90 ldr r6, [sp, #60] @ load extra args from the stack
91 ldr r7, [sp, #64] @ load extra args from the stack
49 dsb @ flush buffered writes to interconnect 92 dsb @ flush buffered writes to interconnect
50 cmp r3, #0x2 93 cmp r7, #1 @ if increasing SDRC clk rate,
51 blne configure_sdrc 94 bleq configure_sdrc @ program the SDRC regs early (for RFR)
52 cmp r4, #0x1 95 cmp r4, #SDRC_UNLOCK_DLL @ set the intended DLL state
53 bleq unlock_dll 96 bleq unlock_dll
54 blne lock_dll 97 blne lock_dll
55 bl sdram_in_selfrefresh @ put the SDRAM in self refresh 98 bl sdram_in_selfrefresh @ put SDRAM in self refresh, idle SDRC
56 bl configure_core_dpll 99 bl configure_core_dpll @ change the DPLL3 M2 divider
57 bl enable_sdrc 100 bl enable_sdrc @ take SDRC out of idle
58 cmp r4, #0x1 101 cmp r4, #SDRC_UNLOCK_DLL @ wait for DLL status to change
59 bleq wait_dll_unlock 102 bleq wait_dll_unlock
60 blne wait_dll_lock 103 blne wait_dll_lock
61 cmp r3, #0x1 104 cmp r7, #1 @ if increasing SDRC clk rate,
62 blne configure_sdrc 105 beq return_to_sdram @ return to SDRAM code, otherwise,
106 bl configure_sdrc @ reprogram SDRC regs now
107 mov r12, r5
108 bl wait_clk_stable @ wait for SDRC to stabilize
109return_to_sdram:
63 isb @ prevent speculative exec past here 110 isb @ prevent speculative exec past here
64 mov r0, #0 @ return value 111 mov r0, #0 @ return value
65 ldmfd sp!, {r1-r12, pc} @ restore regs and return 112 ldmfd sp!, {r1-r12, pc} @ restore regs and return
66unlock_dll: 113unlock_dll:
67 ldr r11, omap3_sdrc_dlla_ctrl 114 ldr r11, omap3_sdrc_dlla_ctrl
68 ldr r12, [r11] 115 ldr r12, [r11]
69 orr r12, r12, #0x4 116 and r12, r12, #FIXEDDELAY_MASK
117 orr r12, r12, #FIXEDDELAY_DEFAULT
118 orr r12, r12, #DLLIDLE_MASK
70 str r12, [r11] @ (no OCP barrier needed) 119 str r12, [r11] @ (no OCP barrier needed)
71 bx lr 120 bx lr
72lock_dll: 121lock_dll:
73 ldr r11, omap3_sdrc_dlla_ctrl 122 ldr r11, omap3_sdrc_dlla_ctrl
74 ldr r12, [r11] 123 ldr r12, [r11]
75 bic r12, r12, #0x4 124 bic r12, r12, #DLLIDLE_MASK
76 str r12, [r11] @ (no OCP barrier needed) 125 str r12, [r11] @ (no OCP barrier needed)
77 bx lr 126 bx lr
78sdram_in_selfrefresh: 127sdram_in_selfrefresh:
79 ldr r11, omap3_sdrc_power @ read the SDRC_POWER register 128 ldr r11, omap3_sdrc_power @ read the SDRC_POWER register
80 ldr r12, [r11] @ read the contents of SDRC_POWER 129 ldr r12, [r11] @ read the contents of SDRC_POWER
81 mov r9, r12 @ keep a copy of SDRC_POWER bits 130 mov r9, r12 @ keep a copy of SDRC_POWER bits
82 orr r12, r12, #0x40 @ enable self refresh on idle req 131 orr r12, r12, #SRFRONIDLEREQ_MASK @ enable self refresh on idle
83 bic r12, r12, #0x4 @ clear PWDENA 132 bic r12, r12, #PWDENA_MASK @ clear PWDENA
84 str r12, [r11] @ write back to SDRC_POWER register 133 str r12, [r11] @ write back to SDRC_POWER register
85 ldr r12, [r11] @ posted-write barrier for SDRC 134 ldr r12, [r11] @ posted-write barrier for SDRC
135idle_sdrc:
86 ldr r11, omap3_cm_iclken1_core @ read the CM_ICLKEN1_CORE reg 136 ldr r11, omap3_cm_iclken1_core @ read the CM_ICLKEN1_CORE reg
87 ldr r12, [r11] 137 ldr r12, [r11]
88 bic r12, r12, #0x2 @ disable iclk bit for SDRC 138 bic r12, r12, #EN_SDRC_MASK @ disable iclk bit for SDRC
89 str r12, [r11] 139 str r12, [r11]
90wait_sdrc_idle: 140wait_sdrc_idle:
91 ldr r11, omap3_cm_idlest1_core 141 ldr r11, omap3_cm_idlest1_core
92 ldr r12, [r11] 142 ldr r12, [r11]
93 and r12, r12, #0x2 @ check for SDRC idle 143 and r12, r12, #ST_SDRC_MASK @ check for SDRC idle
94 cmp r12, #2 144 cmp r12, #ST_SDRC_MASK
95 bne wait_sdrc_idle 145 bne wait_sdrc_idle
96 bx lr 146 bx lr
97configure_core_dpll: 147configure_core_dpll:
@@ -99,36 +149,23 @@ configure_core_dpll:
99 ldr r12, [r11] 149 ldr r12, [r11]
100 ldr r10, core_m2_mask_val @ modify m2 for core dpll 150 ldr r10, core_m2_mask_val @ modify m2 for core dpll
101 and r12, r12, r10 151 and r12, r12, r10
102 orr r12, r12, r3, lsl #0x1B @ r3 contains the M2 val 152 orr r12, r12, r3, lsl #CORE_DPLL_CLKOUT_DIV_SHIFT
103 str r12, [r11] 153 str r12, [r11]
104 ldr r12, [r11] @ posted-write barrier for CM 154 ldr r12, [r11] @ posted-write barrier for CM
105 mov r12, #0x800 @ wait for the clock to stabilise
106 cmp r3, #2
107 bne wait_clk_stable
108 bx lr 155 bx lr
109wait_clk_stable: 156wait_clk_stable:
110 subs r12, r12, #1 157 subs r12, r12, #1
111 bne wait_clk_stable 158 bne wait_clk_stable
112 nop
113 nop
114 nop
115 nop
116 nop
117 nop
118 nop
119 nop
120 nop
121 nop
122 bx lr 159 bx lr
123enable_sdrc: 160enable_sdrc:
124 ldr r11, omap3_cm_iclken1_core 161 ldr r11, omap3_cm_iclken1_core
125 ldr r12, [r11] 162 ldr r12, [r11]
126 orr r12, r12, #0x2 @ enable iclk bit for SDRC 163 orr r12, r12, #EN_SDRC_MASK @ enable iclk bit for SDRC
127 str r12, [r11] 164 str r12, [r11]
128wait_sdrc_idle1: 165wait_sdrc_idle1:
129 ldr r11, omap3_cm_idlest1_core 166 ldr r11, omap3_cm_idlest1_core
130 ldr r12, [r11] 167 ldr r12, [r11]
131 and r12, r12, #0x2 168 and r12, r12, #ST_SDRC_MASK
132 cmp r12, #0 169 cmp r12, #0
133 bne wait_sdrc_idle1 170 bne wait_sdrc_idle1
134restore_sdrc_power_val: 171restore_sdrc_power_val:
@@ -138,14 +175,14 @@ restore_sdrc_power_val:
138wait_dll_lock: 175wait_dll_lock:
139 ldr r11, omap3_sdrc_dlla_status 176 ldr r11, omap3_sdrc_dlla_status
140 ldr r12, [r11] 177 ldr r12, [r11]
141 and r12, r12, #0x4 178 and r12, r12, #LOCKSTATUS_MASK
142 cmp r12, #0x4 179 cmp r12, #LOCKSTATUS_MASK
143 bne wait_dll_lock 180 bne wait_dll_lock
144 bx lr 181 bx lr
145wait_dll_unlock: 182wait_dll_unlock:
146 ldr r11, omap3_sdrc_dlla_status 183 ldr r11, omap3_sdrc_dlla_status
147 ldr r12, [r11] 184 ldr r12, [r11]
148 and r12, r12, #0x4 185 and r12, r12, #LOCKSTATUS_MASK
149 cmp r12, #0x0 186 cmp r12, #0x0
150 bne wait_dll_unlock 187 bne wait_dll_unlock
151 bx lr 188 bx lr
@@ -156,7 +193,9 @@ configure_sdrc:
156 str r1, [r11] 193 str r1, [r11]
157 ldr r11, omap3_sdrc_actim_ctrlb 194 ldr r11, omap3_sdrc_actim_ctrlb
158 str r2, [r11] 195 str r2, [r11]
159 ldr r2, [r11] @ posted-write barrier for SDRC 196 ldr r11, omap3_sdrc_mr_0
197 str r6, [r11]
198 ldr r6, [r11] @ posted-write barrier for SDRC
160 bx lr 199 bx lr
161 200
162omap3_sdrc_power: 201omap3_sdrc_power:
@@ -173,6 +212,8 @@ omap3_sdrc_actim_ctrla:
173 .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0) 212 .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0)
174omap3_sdrc_actim_ctrlb: 213omap3_sdrc_actim_ctrlb:
175 .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0) 214 .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0)
215omap3_sdrc_mr_0:
216 .word OMAP34XX_SDRC_REGADDR(SDRC_MR_0)
176omap3_sdrc_dlla_status: 217omap3_sdrc_dlla_status:
177 .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS) 218 .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
178omap3_sdrc_dlla_ctrl: 219omap3_sdrc_dlla_ctrl:
diff --git a/arch/arm/mach-orion5x/addr-map.c b/arch/arm/mach-orion5x/addr-map.c
index 6f3f77d031d0..d78731edebb6 100644
--- a/arch/arm/mach-orion5x/addr-map.c
+++ b/arch/arm/mach-orion5x/addr-map.c
@@ -200,6 +200,6 @@ void __init orion5x_setup_pcie_wa_win(u32 base, u32 size)
200 200
201int __init orion5x_setup_sram_win(void) 201int __init orion5x_setup_sram_win(void)
202{ 202{
203 return setup_cpu_win(win_alloc_count, ORION5X_SRAM_PHYS_BASE, 203 return setup_cpu_win(win_alloc_count++, ORION5X_SRAM_PHYS_BASE,
204 ORION5X_SRAM_SIZE, TARGET_SRAM, ATTR_SRAM, -1); 204 ORION5X_SRAM_SIZE, TARGET_SRAM, ATTR_SRAM, -1);
205} 205}
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index eafcc49009ea..f87fa1253803 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -562,7 +562,7 @@ static struct platform_device orion5x_crypto_device = {
562 .resource = orion5x_crypto_res, 562 .resource = orion5x_crypto_res,
563}; 563};
564 564
565int __init orion5x_crypto_init(void) 565static int __init orion5x_crypto_init(void)
566{ 566{
567 int ret; 567 int ret;
568 568
@@ -697,6 +697,14 @@ void __init orion5x_init(void)
697 } 697 }
698 698
699 /* 699 /*
700 * The 5082/5181l/5182/6082/6082l/6183 have crypto
701 * while 5180n/5181/5281 don't have crypto.
702 */
703 if ((dev == MV88F5181_DEV_ID && rev >= MV88F5181L_REV_A0) ||
704 dev == MV88F5182_DEV_ID || dev == MV88F6183_DEV_ID)
705 orion5x_crypto_init();
706
707 /*
700 * Register watchdog driver 708 * Register watchdog driver
701 */ 709 */
702 orion5x_wdt_init(); 710 orion5x_wdt_init();
diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h
index de483e83edd7..8f004503c96d 100644
--- a/arch/arm/mach-orion5x/common.h
+++ b/arch/arm/mach-orion5x/common.h
@@ -38,7 +38,6 @@ void orion5x_spi_init(void);
38void orion5x_uart0_init(void); 38void orion5x_uart0_init(void);
39void orion5x_uart1_init(void); 39void orion5x_uart1_init(void);
40void orion5x_xor_init(void); 40void orion5x_xor_init(void);
41int orion5x_crypto_init(void);
42 41
43/* 42/*
44 * PCIe/PCI functions. 43 * PCIe/PCI functions.
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index f4533f8ff4e8..89c992b8f75b 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -401,6 +401,16 @@ config MACH_PALMZ72
401 Say Y here if you intend to run this kernel on Palm Zire 72 401 Say Y here if you intend to run this kernel on Palm Zire 72
402 handheld computer. 402 handheld computer.
403 403
404config MACH_TREO680
405 bool "Palm Treo 680"
406 default y
407 depends on ARCH_PXA_PALM
408 select PXA27x
409 select IWMMXT
410 help
411 Say Y here if you intend to run this kernel on Palm Treo 680
412 smartphone.
413
404config MACH_PALMLD 414config MACH_PALMLD
405 bool "Palm LifeDrive" 415 bool "Palm LifeDrive"
406 default y 416 default y
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile
index d18ffef44b8c..d4c6122a342f 100644
--- a/arch/arm/mach-pxa/Makefile
+++ b/arch/arm/mach-pxa/Makefile
@@ -62,6 +62,7 @@ obj-$(CONFIG_MACH_PALMT5) += palmt5.o
62obj-$(CONFIG_MACH_PALMTX) += palmtx.o 62obj-$(CONFIG_MACH_PALMTX) += palmtx.o
63obj-$(CONFIG_MACH_PALMLD) += palmld.o 63obj-$(CONFIG_MACH_PALMLD) += palmld.o
64obj-$(CONFIG_MACH_PALMZ72) += palmz72.o 64obj-$(CONFIG_MACH_PALMZ72) += palmz72.o
65obj-$(CONFIG_MACH_TREO680) += treo680.o
65obj-$(CONFIG_ARCH_VIPER) += viper.o 66obj-$(CONFIG_ARCH_VIPER) += viper.o
66 67
67ifeq ($(CONFIG_MACH_ZYLONITE),y) 68ifeq ($(CONFIG_MACH_ZYLONITE),y)
diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c
index 962dda2e154a..5363e1aea3fb 100644
--- a/arch/arm/mach-pxa/corgi.c
+++ b/arch/arm/mach-pxa/corgi.c
@@ -23,6 +23,7 @@
23#include <linux/pm.h> 23#include <linux/pm.h>
24#include <linux/gpio.h> 24#include <linux/gpio.h>
25#include <linux/backlight.h> 25#include <linux/backlight.h>
26#include <linux/i2c.h>
26#include <linux/io.h> 27#include <linux/io.h>
27#include <linux/spi/spi.h> 28#include <linux/spi/spi.h>
28#include <linux/spi/ads7846.h> 29#include <linux/spi/ads7846.h>
@@ -600,6 +601,10 @@ static struct platform_device *devices[] __initdata = {
600 &sharpsl_rom_device, 601 &sharpsl_rom_device,
601}; 602};
602 603
604static struct i2c_board_info __initdata corgi_i2c_devices[] = {
605 { I2C_BOARD_INFO("wm8731", 0x1b) },
606};
607
603static void corgi_poweroff(void) 608static void corgi_poweroff(void)
604{ 609{
605 if (!machine_is_corgi()) 610 if (!machine_is_corgi())
@@ -634,6 +639,7 @@ static void __init corgi_init(void)
634 pxa_set_mci_info(&corgi_mci_platform_data); 639 pxa_set_mci_info(&corgi_mci_platform_data);
635 pxa_set_ficp_info(&corgi_ficp_platform_data); 640 pxa_set_ficp_info(&corgi_ficp_platform_data);
636 pxa_set_i2c_info(NULL); 641 pxa_set_i2c_info(NULL);
642 i2c_register_board_info(0, ARRAY_AND_SIZE(corgi_i2c_devices));
637 643
638 platform_scoop_config = &corgi_pcmcia_config; 644 platform_scoop_config = &corgi_pcmcia_config;
639 645
diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c
index 243e0802b5f4..63b10d9bb1d3 100644
--- a/arch/arm/mach-pxa/em-x270.c
+++ b/arch/arm/mach-pxa/em-x270.c
@@ -30,6 +30,7 @@
30#include <linux/apm-emulation.h> 30#include <linux/apm-emulation.h>
31#include <linux/i2c.h> 31#include <linux/i2c.h>
32#include <linux/i2c/pca953x.h> 32#include <linux/i2c/pca953x.h>
33#include <linux/regulator/userspace-consumer.h>
33 34
34#include <media/soc_camera.h> 35#include <media/soc_camera.h>
35 36
@@ -735,6 +736,7 @@ static struct pxa2xx_spi_chip em_x270_libertas_chip = {
735 .rx_threshold = 1, 736 .rx_threshold = 1,
736 .tx_threshold = 1, 737 .tx_threshold = 1,
737 .timeout = 1000, 738 .timeout = 1000,
739 .gpio_cs = 14,
738}; 740};
739 741
740static unsigned long em_x270_libertas_pin_config[] = { 742static unsigned long em_x270_libertas_pin_config[] = {
@@ -803,7 +805,6 @@ static int em_x270_libertas_teardown(struct spi_device *spi)
803 805
804struct libertas_spi_platform_data em_x270_libertas_pdata = { 806struct libertas_spi_platform_data em_x270_libertas_pdata = {
805 .use_dummy_writes = 1, 807 .use_dummy_writes = 1,
806 .gpio_cs = 14,
807 .setup = em_x270_libertas_setup, 808 .setup = em_x270_libertas_setup,
808 .teardown = em_x270_libertas_teardown, 809 .teardown = em_x270_libertas_teardown,
809}; 810};
@@ -838,10 +839,14 @@ static void __init em_x270_init_spi(void)
838static inline void em_x270_init_spi(void) {} 839static inline void em_x270_init_spi(void) {}
839#endif 840#endif
840 841
841#if defined(CONFIG_SND_PXA2XX_AC97) || defined(CONFIG_SND_PXA2XX_AC97_MODULE) 842#if defined(CONFIG_SND_PXA2XX_LIB_AC97)
843static pxa2xx_audio_ops_t em_x270_ac97_info = {
844 .reset_gpio = 113,
845};
846
842static void __init em_x270_init_ac97(void) 847static void __init em_x270_init_ac97(void)
843{ 848{
844 pxa_set_ac97_info(NULL); 849 pxa_set_ac97_info(&em_x270_ac97_info);
845} 850}
846#else 851#else
847static inline void em_x270_init_ac97(void) {} 852static inline void em_x270_init_ac97(void) {}
@@ -1038,6 +1043,52 @@ static void __init em_x270_init_camera(void)
1038static inline void em_x270_init_camera(void) {} 1043static inline void em_x270_init_camera(void) {}
1039#endif 1044#endif
1040 1045
1046static struct regulator_bulk_data em_x270_gps_consumer_supply = {
1047 .supply = "vcc gps",
1048};
1049
1050static struct regulator_userspace_consumer_data em_x270_gps_consumer_data = {
1051 .name = "vcc gps",
1052 .num_supplies = 1,
1053 .supplies = &em_x270_gps_consumer_supply,
1054};
1055
1056static struct platform_device em_x270_gps_userspace_consumer = {
1057 .name = "reg-userspace-consumer",
1058 .id = 0,
1059 .dev = {
1060 .platform_data = &em_x270_gps_consumer_data,
1061 },
1062};
1063
1064static struct regulator_bulk_data em_x270_gprs_consumer_supply = {
1065 .supply = "vcc gprs",
1066};
1067
1068static struct regulator_userspace_consumer_data em_x270_gprs_consumer_data = {
1069 .name = "vcc gprs",
1070 .num_supplies = 1,
1071 .supplies = &em_x270_gprs_consumer_supply
1072};
1073
1074static struct platform_device em_x270_gprs_userspace_consumer = {
1075 .name = "reg-userspace-consumer",
1076 .id = 1,
1077 .dev = {
1078 .platform_data = &em_x270_gprs_consumer_data,
1079 }
1080};
1081
1082static struct platform_device *em_x270_userspace_consumers[] = {
1083 &em_x270_gps_userspace_consumer,
1084 &em_x270_gprs_userspace_consumer,
1085};
1086
1087static void __init em_x270_userspace_consumers_init(void)
1088{
1089 platform_add_devices(ARRAY_AND_SIZE(em_x270_userspace_consumers));
1090}
1091
1041/* DA9030 related initializations */ 1092/* DA9030 related initializations */
1042#define REGULATOR_CONSUMER(_name, _dev, _supply) \ 1093#define REGULATOR_CONSUMER(_name, _dev, _supply) \
1043 static struct regulator_consumer_supply _name##_consumers[] = { \ 1094 static struct regulator_consumer_supply _name##_consumers[] = { \
@@ -1047,11 +1098,11 @@ static inline void em_x270_init_camera(void) {}
1047 }, \ 1098 }, \
1048 } 1099 }
1049 1100
1050REGULATOR_CONSUMER(ldo3, NULL, "vcc gps"); 1101REGULATOR_CONSUMER(ldo3, &em_x270_gps_userspace_consumer.dev, "vcc gps");
1051REGULATOR_CONSUMER(ldo5, NULL, "vcc cam"); 1102REGULATOR_CONSUMER(ldo5, NULL, "vcc cam");
1052REGULATOR_CONSUMER(ldo10, &pxa_device_mci.dev, "vcc sdio"); 1103REGULATOR_CONSUMER(ldo10, &pxa_device_mci.dev, "vcc sdio");
1053REGULATOR_CONSUMER(ldo12, NULL, "vcc usb"); 1104REGULATOR_CONSUMER(ldo12, NULL, "vcc usb");
1054REGULATOR_CONSUMER(ldo19, NULL, "vcc gprs"); 1105REGULATOR_CONSUMER(ldo19, &em_x270_gprs_userspace_consumer.dev, "vcc gprs");
1055 1106
1056#define REGULATOR_INIT(_ldo, _min_uV, _max_uV, _ops_mask) \ 1107#define REGULATOR_INIT(_ldo, _min_uV, _max_uV, _ops_mask) \
1057 static struct regulator_init_data _ldo##_data = { \ 1108 static struct regulator_init_data _ldo##_data = { \
@@ -1062,6 +1113,7 @@ REGULATOR_CONSUMER(ldo19, NULL, "vcc gprs");
1062 .enabled = 0, \ 1113 .enabled = 0, \
1063 }, \ 1114 }, \
1064 .valid_ops_mask = _ops_mask, \ 1115 .valid_ops_mask = _ops_mask, \
1116 .apply_uV = 1, \
1065 }, \ 1117 }, \
1066 .num_consumer_supplies = ARRAY_SIZE(_ldo##_consumers), \ 1118 .num_consumer_supplies = ARRAY_SIZE(_ldo##_consumers), \
1067 .consumer_supplies = _ldo##_consumers, \ 1119 .consumer_supplies = _ldo##_consumers, \
@@ -1240,6 +1292,7 @@ static void __init em_x270_init(void)
1240 em_x270_init_spi(); 1292 em_x270_init_spi();
1241 em_x270_init_i2c(); 1293 em_x270_init_i2c();
1242 em_x270_init_camera(); 1294 em_x270_init_camera();
1295 em_x270_userspace_consumers_init();
1243} 1296}
1244 1297
1245MACHINE_START(EM_X270, "Compulab EM-X270") 1298MACHINE_START(EM_X270, "Compulab EM-X270")
diff --git a/arch/arm/mach-pxa/hx4700.c b/arch/arm/mach-pxa/hx4700.c
index 7fff467e84fc..81359d574f88 100644
--- a/arch/arm/mach-pxa/hx4700.c
+++ b/arch/arm/mach-pxa/hx4700.c
@@ -30,6 +30,7 @@
30#include <linux/pwm_backlight.h> 30#include <linux/pwm_backlight.h>
31#include <linux/regulator/bq24022.h> 31#include <linux/regulator/bq24022.h>
32#include <linux/regulator/machine.h> 32#include <linux/regulator/machine.h>
33#include <linux/regulator/max1586.h>
33#include <linux/spi/ads7846.h> 34#include <linux/spi/ads7846.h>
34#include <linux/spi/spi.h> 35#include <linux/spi/spi.h>
35#include <linux/usb/gpio_vbus.h> 36#include <linux/usb/gpio_vbus.h>
@@ -775,6 +776,45 @@ static struct platform_device strataflash = {
775}; 776};
776 777
777/* 778/*
779 * Maxim MAX1587A on PI2C
780 */
781
782static struct regulator_consumer_supply max1587a_consumer = {
783 .supply = "vcc_core",
784};
785
786static struct regulator_init_data max1587a_v3_info = {
787 .constraints = {
788 .name = "vcc_core range",
789 .min_uV = 900000,
790 .max_uV = 1705000,
791 .always_on = 1,
792 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
793 },
794 .num_consumer_supplies = 1,
795 .consumer_supplies = &max1587a_consumer,
796};
797
798static struct max1586_subdev_data max1587a_subdev = {
799 .name = "vcc_core",
800 .id = MAX1586_V3,
801 .platform_data = &max1587a_v3_info,
802};
803
804static struct max1586_platform_data max1587a_info = {
805 .num_subdevs = 1,
806 .subdevs = &max1587a_subdev,
807 .v3_gain = MAX1586_GAIN_R24_3k32, /* 730..1550 mV */
808};
809
810static struct i2c_board_info __initdata pi2c_board_info[] = {
811 {
812 I2C_BOARD_INFO("max1586", 0x14),
813 .platform_data = &max1587a_info,
814 },
815};
816
817/*
778 * PCMCIA 818 * PCMCIA
779 */ 819 */
780 820
@@ -828,6 +868,7 @@ static void __init hx4700_init(void)
828 pxa_set_ficp_info(&ficp_info); 868 pxa_set_ficp_info(&ficp_info);
829 pxa27x_set_i2c_power_info(NULL); 869 pxa27x_set_i2c_power_info(NULL);
830 pxa_set_i2c_info(NULL); 870 pxa_set_i2c_info(NULL);
871 i2c_register_board_info(1, ARRAY_AND_SIZE(pi2c_board_info));
831 pxa2xx_set_spi_info(2, &pxa_ssp2_master_info); 872 pxa2xx_set_spi_info(2, &pxa_ssp2_master_info);
832 spi_register_board_info(ARRAY_AND_SIZE(tsc2046_board_info)); 873 spi_register_board_info(ARRAY_AND_SIZE(tsc2046_board_info));
833 874
diff --git a/arch/arm/mach-pxa/include/mach/palmz72.h b/arch/arm/mach-pxa/include/mach/palmz72.h
index 5032307ebf7d..2806ef69ba5a 100644
--- a/arch/arm/mach-pxa/include/mach/palmz72.h
+++ b/arch/arm/mach-pxa/include/mach/palmz72.h
@@ -21,7 +21,7 @@
21/* SD/MMC */ 21/* SD/MMC */
22#define GPIO_NR_PALMZ72_SD_DETECT_N 14 22#define GPIO_NR_PALMZ72_SD_DETECT_N 14
23#define GPIO_NR_PALMZ72_SD_POWER_N 98 23#define GPIO_NR_PALMZ72_SD_POWER_N 98
24#define GPIO_NR_PALMZ72_SD_RO 115 24#define GPIO_NR_PALMZ72_SD_RO 115
25 25
26/* Touchscreen */ 26/* Touchscreen */
27#define GPIO_NR_PALMZ72_WM9712_IRQ 27 27#define GPIO_NR_PALMZ72_WM9712_IRQ 27
@@ -31,8 +31,7 @@
31 31
32/* USB */ 32/* USB */
33#define GPIO_NR_PALMZ72_USB_DETECT_N 15 33#define GPIO_NR_PALMZ72_USB_DETECT_N 15
34#define GPIO_NR_PALMZ72_USB_POWER 95 34#define GPIO_NR_PALMZ72_USB_PULLUP 95
35#define GPIO_NR_PALMZ72_USB_PULLUP 12
36 35
37/* LCD/Backlight */ 36/* LCD/Backlight */
38#define GPIO_NR_PALMZ72_BL_POWER 20 37#define GPIO_NR_PALMZ72_BL_POWER 20
diff --git a/arch/arm/mach-pxa/include/mach/treo680.h b/arch/arm/mach-pxa/include/mach/treo680.h
new file mode 100644
index 000000000000..af443b24d99a
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/treo680.h
@@ -0,0 +1,49 @@
1/*
2 * GPIOs and interrupts for Palm Treo 680 smartphone
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 */
9
10#ifndef _INCLUDE_TREO680_H_
11#define _INCLUDE_TREO680_H_
12
13/* GPIOs */
14#define GPIO_NR_TREO680_POWER_DETECT 0
15#define GPIO_NR_TREO680_AMP_EN 27
16#define GPIO_NR_TREO680_KEYB_BL 24
17#define GPIO_NR_TREO680_VIBRATE_EN 44
18#define GPIO_NR_TREO680_GREEN_LED 20
19#define GPIO_NR_TREO680_RED_LED 79
20#define GPIO_NR_TREO680_SD_DETECT_N 113
21#define GPIO_NR_TREO680_SD_READONLY 33
22#define GPIO_NR_TREO680_EP_DETECT_N 116
23#define GPIO_NR_TREO680_SD_POWER 42
24#define GPIO_NR_TREO680_USB_DETECT 1
25#define GPIO_NR_TREO680_USB_PULLUP 114
26#define GPIO_NR_TREO680_GSM_POWER 40
27#define GPIO_NR_TREO680_GSM_RESET 87
28#define GPIO_NR_TREO680_GSM_WAKE 57
29#define GPIO_NR_TREO680_GSM_HOST_WAKE 14
30#define GPIO_NR_TREO680_GSM_TRIGGER 10
31#define GPIO_NR_TREO680_BT_EN 43
32#define GPIO_NR_TREO680_IR_EN 115
33#define GPIO_NR_TREO680_IR_TXD 47
34#define GPIO_NR_TREO680_BL_POWER 38
35#define GPIO_NR_TREO680_LCD_POWER 25
36
37/* Various addresses */
38#define TREO680_PHYS_RAM_START 0xa0000000
39#define TREO680_PHYS_IO_START 0x40000000
40#define TREO680_STR_BASE 0xa2000000
41
42/* BACKLIGHT */
43#define TREO680_MAX_INTENSITY 254
44#define TREO680_DEFAULT_INTENSITY 160
45#define TREO680_LIMIT_MASK 0x7F
46#define TREO680_PRESCALER 63
47#define TREO680_PERIOD_NS 3500
48
49#endif
diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c
index 4dc8c2ec40a9..2d28132c725b 100644
--- a/arch/arm/mach-pxa/mioa701.c
+++ b/arch/arm/mach-pxa/mioa701.c
@@ -37,6 +37,7 @@
37#include <linux/wm97xx_batt.h> 37#include <linux/wm97xx_batt.h>
38#include <linux/mtd/physmap.h> 38#include <linux/mtd/physmap.h>
39#include <linux/usb/gpio_vbus.h> 39#include <linux/usb/gpio_vbus.h>
40#include <linux/regulator/max1586.h>
40 41
41#include <asm/mach-types.h> 42#include <asm/mach-types.h>
42#include <asm/mach/arch.h> 43#include <asm/mach/arch.h>
@@ -717,6 +718,38 @@ static struct wm97xx_batt_info mioa701_battery_data = {
717}; 718};
718 719
719/* 720/*
721 * Voltage regulation
722 */
723static struct regulator_consumer_supply max1586_consumers[] = {
724 {
725 .supply = "vcc_core",
726 }
727};
728
729static struct regulator_init_data max1586_v3_info = {
730 .constraints = {
731 .name = "vcc_core range",
732 .min_uV = 1000000,
733 .max_uV = 1705000,
734 .always_on = 1,
735 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
736 },
737 .num_consumer_supplies = ARRAY_SIZE(max1586_consumers),
738 .consumer_supplies = max1586_consumers,
739};
740
741static struct max1586_subdev_data max1586_subdevs[] = {
742 { .name = "vcc_core", .id = MAX1586_V3,
743 .platform_data = &max1586_v3_info },
744};
745
746static struct max1586_platform_data max1586_info = {
747 .subdevs = max1586_subdevs,
748 .num_subdevs = ARRAY_SIZE(max1586_subdevs),
749 .v3_gain = MAX1586_GAIN_NO_R24, /* 700..1475 mV */
750};
751
752/*
720 * Camera interface 753 * Camera interface
721 */ 754 */
722struct pxacamera_platform_data mioa701_pxacamera_platform_data = { 755struct pxacamera_platform_data mioa701_pxacamera_platform_data = {
@@ -725,6 +758,13 @@ struct pxacamera_platform_data mioa701_pxacamera_platform_data = {
725 .mclk_10khz = 5000, 758 .mclk_10khz = 5000,
726}; 759};
727 760
761static struct i2c_board_info __initdata mioa701_pi2c_devices[] = {
762 {
763 I2C_BOARD_INFO("max1586", 0x14),
764 .platform_data = &max1586_info,
765 },
766};
767
728static struct soc_camera_link iclink = { 768static struct soc_camera_link iclink = {
729 .bus_id = 0, /* Must match id in pxa27x_device_camera in device.c */ 769 .bus_id = 0, /* Must match id in pxa27x_device_camera in device.c */
730}; 770};
@@ -825,7 +865,9 @@ static void __init mioa701_machine_init(void)
825 platform_add_devices(devices, ARRAY_SIZE(devices)); 865 platform_add_devices(devices, ARRAY_SIZE(devices));
826 gsm_init(); 866 gsm_init();
827 867
868 i2c_register_board_info(1, ARRAY_AND_SIZE(mioa701_pi2c_devices));
828 pxa_set_i2c_info(&i2c_pdata); 869 pxa_set_i2c_info(&i2c_pdata);
870 pxa27x_set_i2c_power_info(NULL);
829 pxa_set_camera_info(&mioa701_pxacamera_platform_data); 871 pxa_set_camera_info(&mioa701_pxacamera_platform_data);
830 i2c_register_board_info(0, ARRAY_AND_SIZE(mioa701_i2c_devices)); 872 i2c_register_board_info(0, ARRAY_AND_SIZE(mioa701_i2c_devices));
831} 873}
diff --git a/arch/arm/mach-pxa/palmz72.c b/arch/arm/mach-pxa/palmz72.c
index b88eb4dd2c84..c3645aa3fa3d 100644
--- a/arch/arm/mach-pxa/palmz72.c
+++ b/arch/arm/mach-pxa/palmz72.c
@@ -27,7 +27,9 @@
27#include <linux/pda_power.h> 27#include <linux/pda_power.h>
28#include <linux/pwm_backlight.h> 28#include <linux/pwm_backlight.h>
29#include <linux/gpio.h> 29#include <linux/gpio.h>
30#include <linux/wm97xx_batt.h>
30#include <linux/power_supply.h> 31#include <linux/power_supply.h>
32#include <linux/usb/gpio_vbus.h>
31 33
32#include <asm/mach-types.h> 34#include <asm/mach-types.h>
33#include <asm/mach/arch.h> 35#include <asm/mach/arch.h>
@@ -41,6 +43,8 @@
41#include <mach/irda.h> 43#include <mach/irda.h>
42#include <mach/pxa27x_keypad.h> 44#include <mach/pxa27x_keypad.h>
43#include <mach/udc.h> 45#include <mach/udc.h>
46#include <mach/palmasoc.h>
47
44#include <mach/pm.h> 48#include <mach/pm.h>
45 49
46#include "generic.h" 50#include "generic.h"
@@ -66,6 +70,8 @@ static unsigned long palmz72_pin_config[] __initdata = {
66 GPIO29_AC97_SDATA_IN_0, 70 GPIO29_AC97_SDATA_IN_0,
67 GPIO30_AC97_SDATA_OUT, 71 GPIO30_AC97_SDATA_OUT,
68 GPIO31_AC97_SYNC, 72 GPIO31_AC97_SYNC,
73 GPIO89_AC97_SYSCLK,
74 GPIO113_AC97_nRESET,
69 75
70 /* IrDA */ 76 /* IrDA */
71 GPIO49_GPIO, /* ir disable */ 77 GPIO49_GPIO, /* ir disable */
@@ -77,8 +83,7 @@ static unsigned long palmz72_pin_config[] __initdata = {
77 83
78 /* USB */ 84 /* USB */
79 GPIO15_GPIO, /* usb detect */ 85 GPIO15_GPIO, /* usb detect */
80 GPIO12_GPIO, /* usb pullup */ 86 GPIO95_GPIO, /* usb pullup */
81 GPIO95_GPIO, /* usb power */
82 87
83 /* Matrix keypad */ 88 /* Matrix keypad */
84 GPIO100_KP_MKIN_0 | WAKEUP_ON_LEVEL_HIGH, 89 GPIO100_KP_MKIN_0 | WAKEUP_ON_LEVEL_HIGH,
@@ -355,6 +360,22 @@ static struct platform_device palmz72_leds = {
355}; 360};
356 361
357/****************************************************************************** 362/******************************************************************************
363 * UDC
364 ******************************************************************************/
365static struct gpio_vbus_mach_info palmz72_udc_info = {
366 .gpio_vbus = GPIO_NR_PALMZ72_USB_DETECT_N,
367 .gpio_pullup = GPIO_NR_PALMZ72_USB_PULLUP,
368};
369
370static struct platform_device palmz72_gpio_vbus = {
371 .name = "gpio-vbus",
372 .id = -1,
373 .dev = {
374 .platform_data = &palmz72_udc_info,
375 },
376};
377
378/******************************************************************************
358 * Power supply 379 * Power supply
359 ******************************************************************************/ 380 ******************************************************************************/
360static int power_supply_init(struct device *dev) 381static int power_supply_init(struct device *dev)
@@ -422,6 +443,31 @@ static struct platform_device power_supply = {
422}; 443};
423 444
424/****************************************************************************** 445/******************************************************************************
446 * WM97xx battery
447 ******************************************************************************/
448static struct wm97xx_batt_info wm97xx_batt_pdata = {
449 .batt_aux = WM97XX_AUX_ID3,
450 .temp_aux = WM97XX_AUX_ID2,
451 .charge_gpio = -1,
452 .max_voltage = PALMZ72_BAT_MAX_VOLTAGE,
453 .min_voltage = PALMZ72_BAT_MIN_VOLTAGE,
454 .batt_mult = 1000,
455 .batt_div = 414,
456 .temp_mult = 1,
457 .temp_div = 1,
458 .batt_tech = POWER_SUPPLY_TECHNOLOGY_LIPO,
459 .batt_name = "main-batt",
460};
461
462/******************************************************************************
463 * aSoC audio
464 ******************************************************************************/
465static struct platform_device palmz72_asoc = {
466 .name = "palm27x-asoc",
467 .id = -1,
468};
469
470/******************************************************************************
425 * Framebuffer 471 * Framebuffer
426 ******************************************************************************/ 472 ******************************************************************************/
427static struct pxafb_mode_info palmz72_lcd_modes[] = { 473static struct pxafb_mode_info palmz72_lcd_modes[] = {
@@ -527,17 +573,32 @@ device_initcall(palmz72_pm_init);
527static struct platform_device *devices[] __initdata = { 573static struct platform_device *devices[] __initdata = {
528 &palmz72_backlight, 574 &palmz72_backlight,
529 &palmz72_leds, 575 &palmz72_leds,
576 &palmz72_asoc,
530 &power_supply, 577 &power_supply,
578 &palmz72_gpio_vbus,
531}; 579};
532 580
581/* setup udc GPIOs initial state */
582static void __init palmz72_udc_init(void)
583{
584 if (!gpio_request(GPIO_NR_PALMZ72_USB_PULLUP, "USB Pullup")) {
585 gpio_direction_output(GPIO_NR_PALMZ72_USB_PULLUP, 0);
586 gpio_free(GPIO_NR_PALMZ72_USB_PULLUP);
587 }
588}
589
533static void __init palmz72_init(void) 590static void __init palmz72_init(void)
534{ 591{
535 pxa2xx_mfp_config(ARRAY_AND_SIZE(palmz72_pin_config)); 592 pxa2xx_mfp_config(ARRAY_AND_SIZE(palmz72_pin_config));
593
536 set_pxa_fb_info(&palmz72_lcd_screen); 594 set_pxa_fb_info(&palmz72_lcd_screen);
537 pxa_set_mci_info(&palmz72_mci_platform_data); 595 pxa_set_mci_info(&palmz72_mci_platform_data);
596 palmz72_udc_init();
538 pxa_set_ac97_info(NULL); 597 pxa_set_ac97_info(NULL);
539 pxa_set_ficp_info(&palmz72_ficp_platform_data); 598 pxa_set_ficp_info(&palmz72_ficp_platform_data);
540 pxa_set_keypad_info(&palmz72_keypad_platform_data); 599 pxa_set_keypad_info(&palmz72_keypad_platform_data);
600 wm97xx_bat_set_pdata(&wm97xx_batt_pdata);
601
541 platform_add_devices(devices, ARRAY_SIZE(devices)); 602 platform_add_devices(devices, ARRAY_SIZE(devices));
542} 603}
543 604
diff --git a/arch/arm/mach-pxa/pcm990-baseboard.c b/arch/arm/mach-pxa/pcm990-baseboard.c
index 095521e9ee24..01791d74e08e 100644
--- a/arch/arm/mach-pxa/pcm990-baseboard.c
+++ b/arch/arm/mach-pxa/pcm990-baseboard.c
@@ -380,12 +380,12 @@ static struct pca953x_platform_data pca9536_data = {
380 .gpio_base = NR_BUILTIN_GPIO, 380 .gpio_base = NR_BUILTIN_GPIO,
381}; 381};
382 382
383static int gpio_bus_switch; 383static int gpio_bus_switch = -EINVAL;
384 384
385static int pcm990_camera_set_bus_param(struct soc_camera_link *link, 385static int pcm990_camera_set_bus_param(struct soc_camera_link *link,
386 unsigned long flags) 386 unsigned long flags)
387{ 387{
388 if (gpio_bus_switch <= 0) { 388 if (gpio_bus_switch < 0) {
389 if (flags == SOCAM_DATAWIDTH_10) 389 if (flags == SOCAM_DATAWIDTH_10)
390 return 0; 390 return 0;
391 else 391 else
@@ -404,25 +404,34 @@ static unsigned long pcm990_camera_query_bus_param(struct soc_camera_link *link)
404{ 404{
405 int ret; 405 int ret;
406 406
407 if (!gpio_bus_switch) { 407 if (gpio_bus_switch < 0) {
408 ret = gpio_request(NR_BUILTIN_GPIO, "camera"); 408 ret = gpio_request(NR_BUILTIN_GPIO, "camera");
409 if (!ret) { 409 if (!ret) {
410 gpio_bus_switch = NR_BUILTIN_GPIO; 410 gpio_bus_switch = NR_BUILTIN_GPIO;
411 gpio_direction_output(gpio_bus_switch, 0); 411 gpio_direction_output(gpio_bus_switch, 0);
412 } else 412 }
413 gpio_bus_switch = -EINVAL;
414 } 413 }
415 414
416 if (gpio_bus_switch > 0) 415 if (gpio_bus_switch >= 0)
417 return SOCAM_DATAWIDTH_8 | SOCAM_DATAWIDTH_10; 416 return SOCAM_DATAWIDTH_8 | SOCAM_DATAWIDTH_10;
418 else 417 else
419 return SOCAM_DATAWIDTH_10; 418 return SOCAM_DATAWIDTH_10;
420} 419}
421 420
421static void pcm990_camera_free_bus(struct soc_camera_link *link)
422{
423 if (gpio_bus_switch < 0)
424 return;
425
426 gpio_free(gpio_bus_switch);
427 gpio_bus_switch = -EINVAL;
428}
429
422static struct soc_camera_link iclink = { 430static struct soc_camera_link iclink = {
423 .bus_id = 0, /* Must match with the camera ID above */ 431 .bus_id = 0, /* Must match with the camera ID above */
424 .query_bus_param = pcm990_camera_query_bus_param, 432 .query_bus_param = pcm990_camera_query_bus_param,
425 .set_bus_param = pcm990_camera_set_bus_param, 433 .set_bus_param = pcm990_camera_set_bus_param,
434 .free_bus = pcm990_camera_free_bus,
426}; 435};
427 436
428/* Board I2C devices. */ 437/* Board I2C devices. */
diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c
index ac431ed10399..9352d4a34837 100644
--- a/arch/arm/mach-pxa/poodle.c
+++ b/arch/arm/mach-pxa/poodle.c
@@ -22,6 +22,7 @@
22#include <linux/delay.h> 22#include <linux/delay.h>
23#include <linux/mtd/physmap.h> 23#include <linux/mtd/physmap.h>
24#include <linux/gpio.h> 24#include <linux/gpio.h>
25#include <linux/i2c.h>
25#include <linux/spi/spi.h> 26#include <linux/spi/spi.h>
26#include <linux/spi/ads7846.h> 27#include <linux/spi/ads7846.h>
27#include <linux/mtd/sharpsl.h> 28#include <linux/mtd/sharpsl.h>
@@ -486,6 +487,10 @@ static struct platform_device *devices[] __initdata = {
486 &sharpsl_rom_device, 487 &sharpsl_rom_device,
487}; 488};
488 489
490static struct i2c_board_info __initdata poodle_i2c_devices[] = {
491 { I2C_BOARD_INFO("wm8731", 0x1b) },
492};
493
489static void poodle_poweroff(void) 494static void poodle_poweroff(void)
490{ 495{
491 arm_machine_restart('h', NULL); 496 arm_machine_restart('h', NULL);
@@ -519,6 +524,7 @@ static void __init poodle_init(void)
519 pxa_set_mci_info(&poodle_mci_platform_data); 524 pxa_set_mci_info(&poodle_mci_platform_data);
520 pxa_set_ficp_info(&poodle_ficp_platform_data); 525 pxa_set_ficp_info(&poodle_ficp_platform_data);
521 pxa_set_i2c_info(NULL); 526 pxa_set_i2c_info(NULL);
527 i2c_register_board_info(0, ARRAY_AND_SIZE(poodle_i2c_devices));
522 poodle_init_spi(); 528 poodle_init_spi();
523} 529}
524 530
diff --git a/arch/arm/mach-pxa/treo680.c b/arch/arm/mach-pxa/treo680.c
new file mode 100644
index 000000000000..a06f19edebb3
--- /dev/null
+++ b/arch/arm/mach-pxa/treo680.c
@@ -0,0 +1,612 @@
1/*
2 * Hardware definitions for Palm Treo 680
3 *
4 * Author: Tomas Cech <sleep_walker@suse.cz>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * (find more info at www.hackndev.com)
11 *
12 */
13
14#include <linux/platform_device.h>
15#include <linux/delay.h>
16#include <linux/irq.h>
17#include <linux/gpio_keys.h>
18#include <linux/input.h>
19#include <linux/pda_power.h>
20#include <linux/pwm_backlight.h>
21#include <linux/gpio.h>
22#include <linux/wm97xx_batt.h>
23#include <linux/power_supply.h>
24#include <linux/sysdev.h>
25#include <linux/w1-gpio.h>
26
27#include <asm/mach-types.h>
28#include <asm/mach/arch.h>
29#include <asm/mach/map.h>
30
31#include <mach/pxa27x.h>
32#include <mach/pxa27x-udc.h>
33#include <mach/audio.h>
34#include <mach/treo680.h>
35#include <mach/mmc.h>
36#include <mach/pxafb.h>
37#include <mach/irda.h>
38#include <mach/pxa27x_keypad.h>
39#include <mach/udc.h>
40#include <mach/ohci.h>
41#include <mach/pxa2xx-regs.h>
42#include <mach/palmasoc.h>
43#include <mach/camera.h>
44
45#include <sound/pxa2xx-lib.h>
46
47#include "generic.h"
48#include "devices.h"
49
50/******************************************************************************
51 * Pin configuration
52 ******************************************************************************/
53static unsigned long treo680_pin_config[] __initdata = {
54 /* MMC */
55 GPIO32_MMC_CLK,
56 GPIO92_MMC_DAT_0,
57 GPIO109_MMC_DAT_1,
58 GPIO110_MMC_DAT_2,
59 GPIO111_MMC_DAT_3,
60 GPIO112_MMC_CMD,
61 GPIO33_GPIO, /* SD read only */
62 GPIO113_GPIO, /* SD detect */
63
64 /* AC97 */
65 GPIO28_AC97_BITCLK,
66 GPIO29_AC97_SDATA_IN_0,
67 GPIO30_AC97_SDATA_OUT,
68 GPIO31_AC97_SYNC,
69 GPIO89_AC97_SYSCLK,
70 GPIO95_AC97_nRESET,
71
72 /* IrDA */
73 GPIO46_FICP_RXD,
74 GPIO47_FICP_TXD,
75
76 /* PWM */
77 GPIO16_PWM0_OUT,
78
79 /* USB */
80 GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH, /* usb detect */
81
82 /* MATRIX KEYPAD */
83 GPIO100_KP_MKIN_0 | WAKEUP_ON_LEVEL_HIGH,
84 GPIO101_KP_MKIN_1,
85 GPIO102_KP_MKIN_2,
86 GPIO97_KP_MKIN_3,
87 GPIO98_KP_MKIN_4,
88 GPIO99_KP_MKIN_5,
89 GPIO91_KP_MKIN_6,
90 GPIO13_KP_MKIN_7,
91 GPIO103_KP_MKOUT_0 | MFP_LPM_DRIVE_HIGH,
92 GPIO104_KP_MKOUT_1,
93 GPIO105_KP_MKOUT_2,
94 GPIO106_KP_MKOUT_3,
95 GPIO107_KP_MKOUT_4,
96 GPIO108_KP_MKOUT_5,
97 GPIO96_KP_MKOUT_6,
98 GPIO93_KP_DKIN_0 | WAKEUP_ON_LEVEL_HIGH, /* Hotsync button */
99
100 /* LCD */
101 GPIO58_LCD_LDD_0,
102 GPIO59_LCD_LDD_1,
103 GPIO60_LCD_LDD_2,
104 GPIO61_LCD_LDD_3,
105 GPIO62_LCD_LDD_4,
106 GPIO63_LCD_LDD_5,
107 GPIO64_LCD_LDD_6,
108 GPIO65_LCD_LDD_7,
109 GPIO66_LCD_LDD_8,
110 GPIO67_LCD_LDD_9,
111 GPIO68_LCD_LDD_10,
112 GPIO69_LCD_LDD_11,
113 GPIO70_LCD_LDD_12,
114 GPIO71_LCD_LDD_13,
115 GPIO72_LCD_LDD_14,
116 GPIO73_LCD_LDD_15,
117 GPIO74_LCD_FCLK,
118 GPIO75_LCD_LCLK,
119 GPIO76_LCD_PCLK,
120
121 /* Quick Capture Interface */
122 GPIO84_CIF_FV,
123 GPIO85_CIF_LV,
124 GPIO53_CIF_MCLK,
125 GPIO54_CIF_PCLK,
126 GPIO81_CIF_DD_0,
127 GPIO55_CIF_DD_1,
128 GPIO51_CIF_DD_2,
129 GPIO50_CIF_DD_3,
130 GPIO52_CIF_DD_4,
131 GPIO48_CIF_DD_5,
132 GPIO17_CIF_DD_6,
133 GPIO12_CIF_DD_7,
134
135 /* I2C */
136 GPIO117_I2C_SCL,
137 GPIO118_I2C_SDA,
138
139 /* GSM */
140 GPIO14_GPIO | WAKEUP_ON_EDGE_BOTH, /* GSM host wake up */
141 GPIO34_FFUART_RXD,
142 GPIO35_FFUART_CTS,
143 GPIO39_FFUART_TXD,
144 GPIO41_FFUART_RTS,
145
146 /* MISC. */
147 GPIO0_GPIO | WAKEUP_ON_EDGE_BOTH, /* external power detect */
148 GPIO15_GPIO | WAKEUP_ON_EDGE_BOTH, /* silent switch */
149 GPIO116_GPIO, /* headphone detect */
150 GPIO11_GPIO | WAKEUP_ON_EDGE_BOTH, /* bluetooth host wake up */
151};
152
153/******************************************************************************
154 * SD/MMC card controller
155 ******************************************************************************/
156static int treo680_mci_init(struct device *dev,
157 irq_handler_t treo680_detect_int, void *data)
158{
159 int err = 0;
160
161 /* Setup an interrupt for detecting card insert/remove events */
162 err = gpio_request(GPIO_NR_TREO680_SD_DETECT_N, "SD IRQ");
163
164 if (err)
165 goto err;
166
167 err = gpio_direction_input(GPIO_NR_TREO680_SD_DETECT_N);
168 if (err)
169 goto err2;
170
171 err = request_irq(gpio_to_irq(GPIO_NR_TREO680_SD_DETECT_N),
172 treo680_detect_int, IRQF_DISABLED | IRQF_SAMPLE_RANDOM |
173 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
174 "SD/MMC card detect", data);
175
176 if (err) {
177 dev_err(dev, "%s: cannot request SD/MMC card detect IRQ\n",
178 __func__);
179 goto err2;
180 }
181
182 err = gpio_request(GPIO_NR_TREO680_SD_POWER, "SD_POWER");
183 if (err)
184 goto err3;
185
186 err = gpio_direction_output(GPIO_NR_TREO680_SD_POWER, 1);
187 if (err)
188 goto err4;
189
190 err = gpio_request(GPIO_NR_TREO680_SD_READONLY, "SD_READONLY");
191 if (err)
192 goto err4;
193
194 err = gpio_direction_input(GPIO_NR_TREO680_SD_READONLY);
195 if (err)
196 goto err5;
197
198 return 0;
199
200err5:
201 gpio_free(GPIO_NR_TREO680_SD_READONLY);
202err4:
203 gpio_free(GPIO_NR_TREO680_SD_POWER);
204err3:
205 free_irq(gpio_to_irq(GPIO_NR_TREO680_SD_DETECT_N), data);
206err2:
207 gpio_free(GPIO_NR_TREO680_SD_DETECT_N);
208err:
209 return err;
210}
211
212static void treo680_mci_exit(struct device *dev, void *data)
213{
214 gpio_free(GPIO_NR_TREO680_SD_READONLY);
215 gpio_free(GPIO_NR_TREO680_SD_POWER);
216 free_irq(gpio_to_irq(GPIO_NR_TREO680_SD_DETECT_N), data);
217 gpio_free(GPIO_NR_TREO680_SD_DETECT_N);
218}
219
220static void treo680_mci_power(struct device *dev, unsigned int vdd)
221{
222 struct pxamci_platform_data *p_d = dev->platform_data;
223 gpio_set_value(GPIO_NR_TREO680_SD_POWER, p_d->ocr_mask & (1 << vdd));
224}
225
226static int treo680_mci_get_ro(struct device *dev)
227{
228 return gpio_get_value(GPIO_NR_TREO680_SD_READONLY);
229}
230
231static struct pxamci_platform_data treo680_mci_platform_data = {
232 .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34,
233 .setpower = treo680_mci_power,
234 .get_ro = treo680_mci_get_ro,
235 .init = treo680_mci_init,
236 .exit = treo680_mci_exit,
237};
238
239/******************************************************************************
240 * GPIO keyboard
241 ******************************************************************************/
242static unsigned int treo680_matrix_keys[] = {
243 KEY(0, 0, KEY_F8), /* Red/Off/Power */
244 KEY(0, 1, KEY_LEFT),
245 KEY(0, 2, KEY_LEFTCTRL), /* Alternate */
246 KEY(0, 3, KEY_L),
247 KEY(0, 4, KEY_A),
248 KEY(0, 5, KEY_Q),
249 KEY(0, 6, KEY_P),
250
251 KEY(1, 0, KEY_RIGHTCTRL), /* Menu */
252 KEY(1, 1, KEY_RIGHT),
253 KEY(1, 2, KEY_LEFTSHIFT), /* Left shift */
254 KEY(1, 3, KEY_Z),
255 KEY(1, 4, KEY_S),
256 KEY(1, 5, KEY_W),
257
258 KEY(2, 0, KEY_F1), /* Phone */
259 KEY(2, 1, KEY_UP),
260 KEY(2, 2, KEY_0),
261 KEY(2, 3, KEY_X),
262 KEY(2, 4, KEY_D),
263 KEY(2, 5, KEY_E),
264
265 KEY(3, 0, KEY_F10), /* Calendar */
266 KEY(3, 1, KEY_DOWN),
267 KEY(3, 2, KEY_SPACE),
268 KEY(3, 3, KEY_C),
269 KEY(3, 4, KEY_F),
270 KEY(3, 5, KEY_R),
271
272 KEY(4, 0, KEY_F12), /* Mail */
273 KEY(4, 1, KEY_KPENTER),
274 KEY(4, 2, KEY_RIGHTALT), /* Alt */
275 KEY(4, 3, KEY_V),
276 KEY(4, 4, KEY_G),
277 KEY(4, 5, KEY_T),
278
279 KEY(5, 0, KEY_F9), /* Home */
280 KEY(5, 1, KEY_PAGEUP), /* Side up */
281 KEY(5, 2, KEY_DOT),
282 KEY(5, 3, KEY_B),
283 KEY(5, 4, KEY_H),
284 KEY(5, 5, KEY_Y),
285
286 KEY(6, 0, KEY_TAB), /* Side Activate */
287 KEY(6, 1, KEY_PAGEDOWN), /* Side down */
288 KEY(6, 2, KEY_ENTER),
289 KEY(6, 3, KEY_N),
290 KEY(6, 4, KEY_J),
291 KEY(6, 5, KEY_U),
292
293 KEY(7, 0, KEY_F6), /* Green/Call */
294 KEY(7, 1, KEY_O),
295 KEY(7, 2, KEY_BACKSPACE),
296 KEY(7, 3, KEY_M),
297 KEY(7, 4, KEY_K),
298 KEY(7, 5, KEY_I),
299};
300
301static struct pxa27x_keypad_platform_data treo680_keypad_platform_data = {
302 .matrix_key_rows = 8,
303 .matrix_key_cols = 7,
304 .matrix_key_map = treo680_matrix_keys,
305 .matrix_key_map_size = ARRAY_SIZE(treo680_matrix_keys),
306 .direct_key_map = { KEY_CONNECT },
307 .direct_key_num = 1,
308
309 .debounce_interval = 30,
310};
311
312/******************************************************************************
313 * aSoC audio
314 ******************************************************************************/
315
316static pxa2xx_audio_ops_t treo680_ac97_pdata = {
317 .reset_gpio = 95,
318};
319
320/******************************************************************************
321 * Backlight
322 ******************************************************************************/
323static int treo680_backlight_init(struct device *dev)
324{
325 int ret;
326
327 ret = gpio_request(GPIO_NR_TREO680_BL_POWER, "BL POWER");
328 if (ret)
329 goto err;
330 ret = gpio_direction_output(GPIO_NR_TREO680_BL_POWER, 0);
331 if (ret)
332 goto err2;
333 ret = gpio_request(GPIO_NR_TREO680_LCD_POWER, "LCD POWER");
334 if (ret)
335 goto err2;
336 ret = gpio_direction_output(GPIO_NR_TREO680_LCD_POWER, 0);
337 if (ret)
338 goto err3;
339
340 return 0;
341err3:
342 gpio_free(GPIO_NR_TREO680_LCD_POWER);
343err2:
344 gpio_free(GPIO_NR_TREO680_BL_POWER);
345err:
346 return ret;
347}
348
349static int treo680_backlight_notify(int brightness)
350{
351 gpio_set_value(GPIO_NR_TREO680_BL_POWER, brightness);
352 return TREO680_MAX_INTENSITY - brightness;
353};
354
355static void treo680_backlight_exit(struct device *dev)
356{
357 gpio_free(GPIO_NR_TREO680_BL_POWER);
358 gpio_free(GPIO_NR_TREO680_LCD_POWER);
359}
360
361static struct platform_pwm_backlight_data treo680_backlight_data = {
362 .pwm_id = 0,
363 .max_brightness = TREO680_MAX_INTENSITY,
364 .dft_brightness = TREO680_DEFAULT_INTENSITY,
365 .pwm_period_ns = TREO680_PERIOD_NS,
366 .init = treo680_backlight_init,
367 .notify = treo680_backlight_notify,
368 .exit = treo680_backlight_exit,
369};
370
371static struct platform_device treo680_backlight = {
372 .name = "pwm-backlight",
373 .dev = {
374 .parent = &pxa27x_device_pwm0.dev,
375 .platform_data = &treo680_backlight_data,
376 },
377};
378
379/******************************************************************************
380 * IrDA
381 ******************************************************************************/
382static void treo680_transceiver_mode(struct device *dev, int mode)
383{
384 gpio_set_value(GPIO_NR_TREO680_IR_EN, mode & IR_OFF);
385 pxa2xx_transceiver_mode(dev, mode);
386}
387
388static int treo680_irda_startup(struct device *dev)
389{
390 int err;
391
392 err = gpio_request(GPIO_NR_TREO680_IR_EN, "Ir port disable");
393 if (err)
394 goto err1;
395
396 err = gpio_direction_output(GPIO_NR_TREO680_IR_EN, 1);
397 if (err)
398 goto err2;
399
400 return 0;
401
402err2:
403 dev_err(dev, "treo680_irda: cannot change IR gpio direction\n");
404 gpio_free(GPIO_NR_TREO680_IR_EN);
405err1:
406 dev_err(dev, "treo680_irda: cannot allocate IR gpio\n");
407 return err;
408}
409
410static void treo680_irda_shutdown(struct device *dev)
411{
412 gpio_free(GPIO_NR_TREO680_AMP_EN);
413}
414
415static struct pxaficp_platform_data treo680_ficp_info = {
416 .transceiver_cap = IR_FIRMODE | IR_SIRMODE | IR_OFF,
417 .startup = treo680_irda_startup,
418 .shutdown = treo680_irda_shutdown,
419 .transceiver_mode = treo680_transceiver_mode,
420};
421
422/******************************************************************************
423 * UDC
424 ******************************************************************************/
425static struct pxa2xx_udc_mach_info treo680_udc_info __initdata = {
426 .gpio_vbus = GPIO_NR_TREO680_USB_DETECT,
427 .gpio_vbus_inverted = 1,
428 .gpio_pullup = GPIO_NR_TREO680_USB_PULLUP,
429};
430
431
432/******************************************************************************
433 * USB host
434 ******************************************************************************/
435static struct pxaohci_platform_data treo680_ohci_info = {
436 .port_mode = PMM_PERPORT_MODE,
437 .flags = ENABLE_PORT1 | ENABLE_PORT3,
438 .power_budget = 0,
439};
440
441/******************************************************************************
442 * Power supply
443 ******************************************************************************/
444static int power_supply_init(struct device *dev)
445{
446 int ret;
447
448 ret = gpio_request(GPIO_NR_TREO680_POWER_DETECT, "CABLE_STATE_AC");
449 if (ret)
450 goto err1;
451 ret = gpio_direction_input(GPIO_NR_TREO680_POWER_DETECT);
452 if (ret)
453 goto err2;
454
455 return 0;
456
457err2:
458 gpio_free(GPIO_NR_TREO680_POWER_DETECT);
459err1:
460 return ret;
461}
462
463static int treo680_is_ac_online(void)
464{
465 return gpio_get_value(GPIO_NR_TREO680_POWER_DETECT);
466}
467
468static void power_supply_exit(struct device *dev)
469{
470 gpio_free(GPIO_NR_TREO680_POWER_DETECT);
471}
472
473static char *treo680_supplicants[] = {
474 "main-battery",
475};
476
477static struct pda_power_pdata power_supply_info = {
478 .init = power_supply_init,
479 .is_ac_online = treo680_is_ac_online,
480 .exit = power_supply_exit,
481 .supplied_to = treo680_supplicants,
482 .num_supplicants = ARRAY_SIZE(treo680_supplicants),
483};
484
485static struct platform_device power_supply = {
486 .name = "pda-power",
487 .id = -1,
488 .dev = {
489 .platform_data = &power_supply_info,
490 },
491};
492
493/******************************************************************************
494 * Vibra and LEDs
495 ******************************************************************************/
496static struct gpio_led gpio_leds[] = {
497 {
498 .name = "treo680:vibra:vibra",
499 .default_trigger = "none",
500 .gpio = GPIO_NR_TREO680_VIBRATE_EN,
501 },
502 {
503 .name = "treo680:green:led",
504 .default_trigger = "mmc0",
505 .gpio = GPIO_NR_TREO680_GREEN_LED,
506 },
507 {
508 .name = "treo680:keybbl:keybbl",
509 .default_trigger = "none",
510 .gpio = GPIO_NR_TREO680_KEYB_BL,
511 },
512};
513
514static struct gpio_led_platform_data gpio_led_info = {
515 .leds = gpio_leds,
516 .num_leds = ARRAY_SIZE(gpio_leds),
517};
518
519static struct platform_device treo680_leds = {
520 .name = "leds-gpio",
521 .id = -1,
522 .dev = {
523 .platform_data = &gpio_led_info,
524 }
525};
526
527
528/******************************************************************************
529 * Framebuffer
530 ******************************************************************************/
531/* TODO: add support for 324x324 */
532static struct pxafb_mode_info treo680_lcd_modes[] = {
533{
534 .pixclock = 86538,
535 .xres = 320,
536 .yres = 320,
537 .bpp = 16,
538
539 .left_margin = 20,
540 .right_margin = 8,
541 .upper_margin = 8,
542 .lower_margin = 5,
543
544 .hsync_len = 4,
545 .vsync_len = 1,
546},
547};
548
549static struct pxafb_mach_info treo680_lcd_screen = {
550 .modes = treo680_lcd_modes,
551 .num_modes = ARRAY_SIZE(treo680_lcd_modes),
552 .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL,
553};
554
555/******************************************************************************
556 * Power management - standby
557 ******************************************************************************/
558static void __init treo680_pm_init(void)
559{
560 static u32 resume[] = {
561 0xe3a00101, /* mov r0, #0x40000000 */
562 0xe380060f, /* orr r0, r0, #0x00f00000 */
563 0xe590f008, /* ldr pc, [r0, #0x08] */
564 };
565
566 /* this is where the bootloader jumps */
567 memcpy(phys_to_virt(TREO680_STR_BASE), resume, sizeof(resume));
568}
569
570/******************************************************************************
571 * Machine init
572 ******************************************************************************/
573static struct platform_device *devices[] __initdata = {
574 &treo680_backlight,
575 &treo680_leds,
576 &power_supply,
577};
578
579/* setup udc GPIOs initial state */
580static void __init treo680_udc_init(void)
581{
582 if (!gpio_request(GPIO_NR_TREO680_USB_PULLUP, "UDC Vbus")) {
583 gpio_direction_output(GPIO_NR_TREO680_USB_PULLUP, 1);
584 gpio_free(GPIO_NR_TREO680_USB_PULLUP);
585 }
586}
587
588static void __init treo680_init(void)
589{
590 treo680_pm_init();
591 pxa2xx_mfp_config(ARRAY_AND_SIZE(treo680_pin_config));
592 pxa_set_keypad_info(&treo680_keypad_platform_data);
593 set_pxa_fb_info(&treo680_lcd_screen);
594 pxa_set_mci_info(&treo680_mci_platform_data);
595 treo680_udc_init();
596 pxa_set_udc_info(&treo680_udc_info);
597 pxa_set_ac97_info(&treo680_ac97_pdata);
598 pxa_set_ficp_info(&treo680_ficp_info);
599 pxa_set_ohci_info(&treo680_ohci_info);
600
601 platform_add_devices(devices, ARRAY_SIZE(devices));
602}
603
604MACHINE_START(TREO680, "Palm Treo 680")
605 .phys_io = TREO680_PHYS_IO_START,
606 .io_pg_offst = io_p2v(0x40000000),
607 .boot_params = 0xa0000100,
608 .map_io = pxa_map_io,
609 .init_irq = pxa27x_init_irq,
610 .timer = &pxa_timer,
611 .init_machine = treo680_init,
612MACHINE_END
diff --git a/arch/arm/mach-realview/realview_pbx.c b/arch/arm/mach-realview/realview_pbx.c
index 1fe294d0bf9d..ede2a57240a3 100644
--- a/arch/arm/mach-realview/realview_pbx.c
+++ b/arch/arm/mach-realview/realview_pbx.c
@@ -27,6 +27,7 @@
27#include <asm/irq.h> 27#include <asm/irq.h>
28#include <asm/leds.h> 28#include <asm/leds.h>
29#include <asm/mach-types.h> 29#include <asm/mach-types.h>
30#include <asm/smp_twd.h>
30#include <asm/hardware/gic.h> 31#include <asm/hardware/gic.h>
31#include <asm/hardware/cache-l2x0.h> 32#include <asm/hardware/cache-l2x0.h>
32 33
diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c
index 3a398befed41..03cd27d917b9 100644
--- a/arch/arm/mm/alignment.c
+++ b/arch/arm/mm/alignment.c
@@ -62,6 +62,12 @@
62#define SHIFT_ASR 0x40 62#define SHIFT_ASR 0x40
63#define SHIFT_RORRRX 0x60 63#define SHIFT_RORRRX 0x60
64 64
65#define BAD_INSTR 0xdeadc0de
66
67/* Thumb-2 32 bit format per ARMv7 DDI0406A A6.3, either f800h,e800h,f800h */
68#define IS_T32(hi16) \
69 (((hi16) & 0xe000) == 0xe000 && ((hi16) & 0x1800))
70
65static unsigned long ai_user; 71static unsigned long ai_user;
66static unsigned long ai_sys; 72static unsigned long ai_sys;
67static unsigned long ai_skipped; 73static unsigned long ai_skipped;
@@ -332,38 +338,48 @@ do_alignment_ldrdstrd(unsigned long addr, unsigned long instr,
332 struct pt_regs *regs) 338 struct pt_regs *regs)
333{ 339{
334 unsigned int rd = RD_BITS(instr); 340 unsigned int rd = RD_BITS(instr);
335 341 unsigned int rd2;
336 if (((rd & 1) == 1) || (rd == 14)) 342 int load;
343
344 if ((instr & 0xfe000000) == 0xe8000000) {
345 /* ARMv7 Thumb-2 32-bit LDRD/STRD */
346 rd2 = (instr >> 8) & 0xf;
347 load = !!(LDST_L_BIT(instr));
348 } else if (((rd & 1) == 1) || (rd == 14))
337 goto bad; 349 goto bad;
350 else {
351 load = ((instr & 0xf0) == 0xd0);
352 rd2 = rd + 1;
353 }
338 354
339 ai_dword += 1; 355 ai_dword += 1;
340 356
341 if (user_mode(regs)) 357 if (user_mode(regs))
342 goto user; 358 goto user;
343 359
344 if ((instr & 0xf0) == 0xd0) { 360 if (load) {
345 unsigned long val; 361 unsigned long val;
346 get32_unaligned_check(val, addr); 362 get32_unaligned_check(val, addr);
347 regs->uregs[rd] = val; 363 regs->uregs[rd] = val;
348 get32_unaligned_check(val, addr + 4); 364 get32_unaligned_check(val, addr + 4);
349 regs->uregs[rd + 1] = val; 365 regs->uregs[rd2] = val;
350 } else { 366 } else {
351 put32_unaligned_check(regs->uregs[rd], addr); 367 put32_unaligned_check(regs->uregs[rd], addr);
352 put32_unaligned_check(regs->uregs[rd + 1], addr + 4); 368 put32_unaligned_check(regs->uregs[rd2], addr + 4);
353 } 369 }
354 370
355 return TYPE_LDST; 371 return TYPE_LDST;
356 372
357 user: 373 user:
358 if ((instr & 0xf0) == 0xd0) { 374 if (load) {
359 unsigned long val; 375 unsigned long val;
360 get32t_unaligned_check(val, addr); 376 get32t_unaligned_check(val, addr);
361 regs->uregs[rd] = val; 377 regs->uregs[rd] = val;
362 get32t_unaligned_check(val, addr + 4); 378 get32t_unaligned_check(val, addr + 4);
363 regs->uregs[rd + 1] = val; 379 regs->uregs[rd2] = val;
364 } else { 380 } else {
365 put32t_unaligned_check(regs->uregs[rd], addr); 381 put32t_unaligned_check(regs->uregs[rd], addr);
366 put32t_unaligned_check(regs->uregs[rd + 1], addr + 4); 382 put32t_unaligned_check(regs->uregs[rd2], addr + 4);
367 } 383 }
368 384
369 return TYPE_LDST; 385 return TYPE_LDST;
@@ -616,8 +632,72 @@ thumb2arm(u16 tinstr)
616 /* Else fall through for illegal instruction case */ 632 /* Else fall through for illegal instruction case */
617 633
618 default: 634 default:
619 return 0xdeadc0de; 635 return BAD_INSTR;
636 }
637}
638
639/*
640 * Convert Thumb-2 32 bit LDM, STM, LDRD, STRD to equivalent instruction
641 * handlable by ARM alignment handler, also find the corresponding handler,
642 * so that we can reuse ARM userland alignment fault fixups for Thumb.
643 *
644 * @pinstr: original Thumb-2 instruction; returns new handlable instruction
645 * @regs: register context.
646 * @poffset: return offset from faulted addr for later writeback
647 *
648 * NOTES:
649 * 1. Comments below refer to ARMv7 DDI0406A Thumb Instruction sections.
650 * 2. Register name Rt from ARMv7 is same as Rd from ARMv6 (Rd is Rt)
651 */
652static void *
653do_alignment_t32_to_handler(unsigned long *pinstr, struct pt_regs *regs,
654 union offset_union *poffset)
655{
656 unsigned long instr = *pinstr;
657 u16 tinst1 = (instr >> 16) & 0xffff;
658 u16 tinst2 = instr & 0xffff;
659 poffset->un = 0;
660
661 switch (tinst1 & 0xffe0) {
662 /* A6.3.5 Load/Store multiple */
663 case 0xe880: /* STM/STMIA/STMEA,LDM/LDMIA, PUSH/POP T2 */
664 case 0xe8a0: /* ...above writeback version */
665 case 0xe900: /* STMDB/STMFD, LDMDB/LDMEA */
666 case 0xe920: /* ...above writeback version */
667 /* no need offset decision since handler calculates it */
668 return do_alignment_ldmstm;
669
670 case 0xf840: /* POP/PUSH T3 (single register) */
671 if (RN_BITS(instr) == 13 && (tinst2 & 0x09ff) == 0x0904) {
672 u32 L = !!(LDST_L_BIT(instr));
673 const u32 subset[2] = {
674 0xe92d0000, /* STMDB sp!,{registers} */
675 0xe8bd0000, /* LDMIA sp!,{registers} */
676 };
677 *pinstr = subset[L] | (1<<RD_BITS(instr));
678 return do_alignment_ldmstm;
679 }
680 /* Else fall through for illegal instruction case */
681 break;
682
683 /* A6.3.6 Load/store double, STRD/LDRD(immed, lit, reg) */
684 case 0xe860:
685 case 0xe960:
686 case 0xe8e0:
687 case 0xe9e0:
688 poffset->un = (tinst2 & 0xff) << 2;
689 case 0xe940:
690 case 0xe9c0:
691 return do_alignment_ldrdstrd;
692
693 /*
694 * No need to handle load/store instructions up to word size
695 * since ARMv6 and later CPUs can perform unaligned accesses.
696 */
697 default:
698 break;
620 } 699 }
700 return NULL;
621} 701}
622 702
623static int 703static int
@@ -630,6 +710,8 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
630 mm_segment_t fs; 710 mm_segment_t fs;
631 unsigned int fault; 711 unsigned int fault;
632 u16 tinstr = 0; 712 u16 tinstr = 0;
713 int isize = 4;
714 int thumb2_32b = 0;
633 715
634 instrptr = instruction_pointer(regs); 716 instrptr = instruction_pointer(regs);
635 717
@@ -637,8 +719,19 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
637 set_fs(KERNEL_DS); 719 set_fs(KERNEL_DS);
638 if (thumb_mode(regs)) { 720 if (thumb_mode(regs)) {
639 fault = __get_user(tinstr, (u16 *)(instrptr & ~1)); 721 fault = __get_user(tinstr, (u16 *)(instrptr & ~1));
640 if (!(fault)) 722 if (!fault) {
641 instr = thumb2arm(tinstr); 723 if (cpu_architecture() >= CPU_ARCH_ARMv7 &&
724 IS_T32(tinstr)) {
725 /* Thumb-2 32-bit */
726 u16 tinst2 = 0;
727 fault = __get_user(tinst2, (u16 *)(instrptr+2));
728 instr = (tinstr << 16) | tinst2;
729 thumb2_32b = 1;
730 } else {
731 isize = 2;
732 instr = thumb2arm(tinstr);
733 }
734 }
642 } else 735 } else
643 fault = __get_user(instr, (u32 *)instrptr); 736 fault = __get_user(instr, (u32 *)instrptr);
644 set_fs(fs); 737 set_fs(fs);
@@ -655,7 +748,7 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
655 748
656 fixup: 749 fixup:
657 750
658 regs->ARM_pc += thumb_mode(regs) ? 2 : 4; 751 regs->ARM_pc += isize;
659 752
660 switch (CODING_BITS(instr)) { 753 switch (CODING_BITS(instr)) {
661 case 0x00000000: /* 3.13.4 load/store instruction extensions */ 754 case 0x00000000: /* 3.13.4 load/store instruction extensions */
@@ -714,18 +807,25 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
714 handler = do_alignment_ldrstr; 807 handler = do_alignment_ldrstr;
715 break; 808 break;
716 809
717 case 0x08000000: /* ldm or stm */ 810 case 0x08000000: /* ldm or stm, or thumb-2 32bit instruction */
718 handler = do_alignment_ldmstm; 811 if (thumb2_32b)
812 handler = do_alignment_t32_to_handler(&instr, regs, &offset);
813 else
814 handler = do_alignment_ldmstm;
719 break; 815 break;
720 816
721 default: 817 default:
722 goto bad; 818 goto bad;
723 } 819 }
724 820
821 if (!handler)
822 goto bad;
725 type = handler(addr, instr, regs); 823 type = handler(addr, instr, regs);
726 824
727 if (type == TYPE_ERROR || type == TYPE_FAULT) 825 if (type == TYPE_ERROR || type == TYPE_FAULT) {
826 regs->ARM_pc -= isize;
728 goto bad_or_fault; 827 goto bad_or_fault;
828 }
729 829
730 if (type == TYPE_LDST) 830 if (type == TYPE_LDST)
731 do_alignment_finish_ldst(addr, instr, regs, offset); 831 do_alignment_finish_ldst(addr, instr, regs, offset);
@@ -735,7 +835,6 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
735 bad_or_fault: 835 bad_or_fault:
736 if (type == TYPE_ERROR) 836 if (type == TYPE_ERROR)
737 goto bad; 837 goto bad;
738 regs->ARM_pc -= thumb_mode(regs) ? 2 : 4;
739 /* 838 /*
740 * We got a fault - fix it up, or die. 839 * We got a fault - fix it up, or die.
741 */ 840 */
@@ -751,8 +850,8 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
751 */ 850 */
752 printk(KERN_ERR "Alignment trap: not handling instruction " 851 printk(KERN_ERR "Alignment trap: not handling instruction "
753 "%0*lx at [<%08lx>]\n", 852 "%0*lx at [<%08lx>]\n",
754 thumb_mode(regs) ? 4 : 8, 853 isize << 1,
755 thumb_mode(regs) ? tinstr : instr, instrptr); 854 isize == 2 ? tinstr : instr, instrptr);
756 ai_skipped += 1; 855 ai_skipped += 1;
757 return 1; 856 return 1;
758 857
@@ -763,8 +862,8 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
763 printk("Alignment trap: %s (%d) PC=0x%08lx Instr=0x%0*lx " 862 printk("Alignment trap: %s (%d) PC=0x%08lx Instr=0x%0*lx "
764 "Address=0x%08lx FSR 0x%03x\n", current->comm, 863 "Address=0x%08lx FSR 0x%03x\n", current->comm,
765 task_pid_nr(current), instrptr, 864 task_pid_nr(current), instrptr,
766 thumb_mode(regs) ? 4 : 8, 865 isize << 1,
767 thumb_mode(regs) ? tinstr : instr, 866 isize == 2 ? tinstr : instr,
768 addr, fsr); 867 addr, fsr);
769 868
770 if (ai_usermode & UM_FIXUP) 869 if (ai_usermode & UM_FIXUP)
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index fdaa9bb87c16..4722582b17b8 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -836,6 +836,13 @@ void __init reserve_node_zero(pg_data_t *pgdat)
836 BOOTMEM_EXCLUSIVE); 836 BOOTMEM_EXCLUSIVE);
837 } 837 }
838 838
839 if (machine_is_treo680()) {
840 reserve_bootmem_node(pgdat, 0xa0000000, 0x1000,
841 BOOTMEM_EXCLUSIVE);
842 reserve_bootmem_node(pgdat, 0xa2000000, 0x1000,
843 BOOTMEM_EXCLUSIVE);
844 }
845
839 if (machine_is_palmt5()) 846 if (machine_is_palmt5())
840 reserve_bootmem_node(pgdat, 0xa0200000, 0x1000, 847 reserve_bootmem_node(pgdat, 0xa0200000, 0x1000,
841 BOOTMEM_EXCLUSIVE); 848 BOOTMEM_EXCLUSIVE);
diff --git a/arch/arm/plat-omap/include/mach/sram.h b/arch/arm/plat-omap/include/mach/sram.h
index dca7c16ae903..4d53cc59d7a3 100644
--- a/arch/arm/plat-omap/include/mach/sram.h
+++ b/arch/arm/plat-omap/include/mach/sram.h
@@ -24,7 +24,8 @@ extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
24extern u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, 24extern u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl,
25 u32 sdrc_actim_ctrla, 25 u32 sdrc_actim_ctrla,
26 u32 sdrc_actim_ctrlb, u32 m2, 26 u32 sdrc_actim_ctrlb, u32 m2,
27 u32 unlock_dll); 27 u32 unlock_dll, u32 f, u32 sdrc_mr,
28 u32 inc);
28 29
29/* Do not use these */ 30/* Do not use these */
30extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl); 31extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
@@ -62,7 +63,8 @@ extern unsigned long omap243x_sram_reprogram_sdrc_sz;
62extern u32 omap3_sram_configure_core_dpll(u32 sdrc_rfr_ctrl, 63extern u32 omap3_sram_configure_core_dpll(u32 sdrc_rfr_ctrl,
63 u32 sdrc_actim_ctrla, 64 u32 sdrc_actim_ctrla,
64 u32 sdrc_actim_ctrlb, u32 m2, 65 u32 sdrc_actim_ctrlb, u32 m2,
65 u32 unlock_dll); 66 u32 unlock_dll, u32 f, u32 sdrc_mr,
67 u32 inc);
66extern unsigned long omap3_sram_configure_core_dpll_sz; 68extern unsigned long omap3_sram_configure_core_dpll_sz;
67 69
68#endif 70#endif
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index a5b9bcd6b108..65006df3f1b7 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -371,15 +371,17 @@ static inline int omap243x_sram_init(void)
371static u32 (*_omap3_sram_configure_core_dpll)(u32 sdrc_rfr_ctrl, 371static u32 (*_omap3_sram_configure_core_dpll)(u32 sdrc_rfr_ctrl,
372 u32 sdrc_actim_ctrla, 372 u32 sdrc_actim_ctrla,
373 u32 sdrc_actim_ctrlb, 373 u32 sdrc_actim_ctrlb,
374 u32 m2, u32 unlock_dll); 374 u32 m2, u32 unlock_dll,
375 u32 f, u32 sdrc_mr, u32 inc);
375u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla, 376u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla,
376 u32 sdrc_actim_ctrlb, u32 m2, u32 unlock_dll) 377 u32 sdrc_actim_ctrlb, u32 m2, u32 unlock_dll,
378 u32 f, u32 sdrc_mr, u32 inc)
377{ 379{
378 BUG_ON(!_omap3_sram_configure_core_dpll); 380 BUG_ON(!_omap3_sram_configure_core_dpll);
379 return _omap3_sram_configure_core_dpll(sdrc_rfr_ctrl, 381 return _omap3_sram_configure_core_dpll(sdrc_rfr_ctrl,
380 sdrc_actim_ctrla, 382 sdrc_actim_ctrla,
381 sdrc_actim_ctrlb, m2, 383 sdrc_actim_ctrlb, m2,
382 unlock_dll); 384 unlock_dll, f, sdrc_mr, inc);
383} 385}
384 386
385/* REVISIT: Should this be same as omap34xx_sram_init() after off-idle? */ 387/* REVISIT: Should this be same as omap34xx_sram_init() after off-idle? */
diff --git a/arch/arm/plat-s3c/include/plat/regs-usb-hsotg-phy.h b/arch/arm/plat-s3c/include/plat/regs-usb-hsotg-phy.h
new file mode 100644
index 000000000000..36a85f5000c8
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/regs-usb-hsotg-phy.h
@@ -0,0 +1,50 @@
1/* arch/arm/plat-s3c/include/plat/regs-usb-hsotg-phy.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk>
7 *
8 * S3C - USB2.0 Highspeed/OtG device PHY registers
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15/* Note, this is a seperate header file as some of the clock framework
16 * needs to touch this if the clk_48m is used as the USB OHCI or other
17 * peripheral source.
18*/
19
20#ifndef __PLAT_S3C64XX_REGS_USB_HSOTG_PHY_H
21#define __PLAT_S3C64XX_REGS_USB_HSOTG_PHY_H __FILE__
22
23/* S3C64XX_PA_USB_HSPHY */
24
25#define S3C_HSOTG_PHYREG(x) ((x) + S3C_VA_USB_HSPHY)
26
27#define S3C_PHYPWR S3C_HSOTG_PHYREG(0x00)
28#define SRC_PHYPWR_OTG_DISABLE (1 << 4)
29#define SRC_PHYPWR_ANALOG_POWERDOWN (1 << 3)
30#define SRC_PHYPWR_FORCE_SUSPEND (1 << 1)
31
32#define S3C_PHYCLK S3C_HSOTG_PHYREG(0x04)
33#define S3C_PHYCLK_MODE_USB11 (1 << 6)
34#define S3C_PHYCLK_EXT_OSC (1 << 5)
35#define S3C_PHYCLK_CLK_FORCE (1 << 4)
36#define S3C_PHYCLK_ID_PULL (1 << 2)
37#define S3C_PHYCLK_CLKSEL_MASK (0x3 << 0)
38#define S3C_PHYCLK_CLKSEL_SHIFT (0)
39#define S3C_PHYCLK_CLKSEL_48M (0x0 << 0)
40#define S3C_PHYCLK_CLKSEL_12M (0x2 << 0)
41#define S3C_PHYCLK_CLKSEL_24M (0x3 << 0)
42
43#define S3C_RSTCON S3C_HSOTG_PHYREG(0x08)
44#define S3C_RSTCON_PHYCLK (1 << 2)
45#define S3C_RSTCON_HCLK (1 << 2)
46#define S3C_RSTCON_PHY (1 << 0)
47
48#define S3C_PHYTUNE S3C_HSOTG_PHYREG(0x20)
49
50#endif /* __PLAT_S3C64XX_REGS_USB_HSOTG_PHY_H */
diff --git a/arch/arm/plat-s3c/include/plat/regs-usb-hsotg.h b/arch/arm/plat-s3c/include/plat/regs-usb-hsotg.h
new file mode 100644
index 000000000000..8d18d9d4d148
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/regs-usb-hsotg.h
@@ -0,0 +1,377 @@
1/* arch/arm/plat-s3c/include/plat/regs-usb-hsotg.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk>
7 *
8 * S3C - USB2.0 Highspeed/OtG device block registers
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#ifndef __PLAT_S3C64XX_REGS_USB_HSOTG_H
16#define __PLAT_S3C64XX_REGS_USB_HSOTG_H __FILE__
17
18#define S3C_HSOTG_REG(x) (x)
19
20#define S3C_GOTGCTL S3C_HSOTG_REG(0x000)
21#define S3C_GOTGCTL_BSESVLD (1 << 19)
22#define S3C_GOTGCTL_ASESVLD (1 << 18)
23#define S3C_GOTGCTL_DBNC_SHORT (1 << 17)
24#define S3C_GOTGCTL_CONID_B (1 << 16)
25#define S3C_GOTGCTL_DEVHNPEN (1 << 11)
26#define S3C_GOTGCTL_HSSETHNPEN (1 << 10)
27#define S3C_GOTGCTL_HNPREQ (1 << 9)
28#define S3C_GOTGCTL_HSTNEGSCS (1 << 8)
29#define S3C_GOTGCTL_SESREQ (1 << 1)
30#define S3C_GOTGCTL_SESREQSCS (1 << 0)
31
32#define S3C_GOTGINT S3C_HSOTG_REG(0x004)
33#define S3C_GOTGINT_DbnceDone (1 << 19)
34#define S3C_GOTGINT_ADevTOUTChg (1 << 18)
35#define S3C_GOTGINT_HstNegDet (1 << 17)
36#define S3C_GOTGINT_HstnegSucStsChng (1 << 9)
37#define S3C_GOTGINT_SesReqSucStsChng (1 << 8)
38#define S3C_GOTGINT_SesEndDet (1 << 2)
39
40#define S3C_GAHBCFG S3C_HSOTG_REG(0x008)
41#define S3C_GAHBCFG_PTxFEmpLvl (1 << 8)
42#define S3C_GAHBCFG_NPTxFEmpLvl (1 << 7)
43#define S3C_GAHBCFG_DMAEn (1 << 5)
44#define S3C_GAHBCFG_HBstLen_MASK (0xf << 1)
45#define S3C_GAHBCFG_HBstLen_SHIFT (1)
46#define S3C_GAHBCFG_HBstLen_Single (0x0 << 1)
47#define S3C_GAHBCFG_HBstLen_Incr (0x1 << 1)
48#define S3C_GAHBCFG_HBstLen_Incr4 (0x3 << 1)
49#define S3C_GAHBCFG_HBstLen_Incr8 (0x5 << 1)
50#define S3C_GAHBCFG_HBstLen_Incr16 (0x7 << 1)
51#define S3C_GAHBCFG_GlblIntrEn (1 << 0)
52
53#define S3C_GUSBCFG S3C_HSOTG_REG(0x00C)
54#define S3C_GUSBCFG_PHYLPClkSel (1 << 15)
55#define S3C_GUSBCFG_HNPCap (1 << 9)
56#define S3C_GUSBCFG_SRPCap (1 << 8)
57#define S3C_GUSBCFG_PHYIf16 (1 << 3)
58#define S3C_GUSBCFG_TOutCal_MASK (0x7 << 0)
59#define S3C_GUSBCFG_TOutCal_SHIFT (0)
60#define S3C_GUSBCFG_TOutCal_LIMIT (0x7)
61#define S3C_GUSBCFG_TOutCal(_x) ((_x) << 0)
62
63#define S3C_GRSTCTL S3C_HSOTG_REG(0x010)
64
65#define S3C_GRSTCTL_AHBIdle (1 << 31)
66#define S3C_GRSTCTL_DMAReq (1 << 30)
67#define S3C_GRSTCTL_TxFNum_MASK (0x1f << 6)
68#define S3C_GRSTCTL_TxFNum_SHIFT (6)
69#define S3C_GRSTCTL_TxFNum_LIMIT (0x1f)
70#define S3C_GRSTCTL_TxFNum(_x) ((_x) << 6)
71#define S3C_GRSTCTL_TxFFlsh (1 << 5)
72#define S3C_GRSTCTL_RxFFlsh (1 << 4)
73#define S3C_GRSTCTL_INTknQFlsh (1 << 3)
74#define S3C_GRSTCTL_FrmCntrRst (1 << 2)
75#define S3C_GRSTCTL_HSftRst (1 << 1)
76#define S3C_GRSTCTL_CSftRst (1 << 0)
77
78#define S3C_GINTSTS S3C_HSOTG_REG(0x014)
79#define S3C_GINTMSK S3C_HSOTG_REG(0x018)
80
81#define S3C_GINTSTS_WkUpInt (1 << 31)
82#define S3C_GINTSTS_SessReqInt (1 << 30)
83#define S3C_GINTSTS_DisconnInt (1 << 29)
84#define S3C_GINTSTS_ConIDStsChng (1 << 28)
85#define S3C_GINTSTS_PTxFEmp (1 << 26)
86#define S3C_GINTSTS_HChInt (1 << 25)
87#define S3C_GINTSTS_PrtInt (1 << 24)
88#define S3C_GINTSTS_FetSusp (1 << 22)
89#define S3C_GINTSTS_incompIP (1 << 21)
90#define S3C_GINTSTS_IncomplSOIN (1 << 20)
91#define S3C_GINTSTS_OEPInt (1 << 19)
92#define S3C_GINTSTS_IEPInt (1 << 18)
93#define S3C_GINTSTS_EPMis (1 << 17)
94#define S3C_GINTSTS_EOPF (1 << 15)
95#define S3C_GINTSTS_ISOutDrop (1 << 14)
96#define S3C_GINTSTS_EnumDone (1 << 13)
97#define S3C_GINTSTS_USBRst (1 << 12)
98#define S3C_GINTSTS_USBSusp (1 << 11)
99#define S3C_GINTSTS_ErlySusp (1 << 10)
100#define S3C_GINTSTS_GOUTNakEff (1 << 7)
101#define S3C_GINTSTS_GINNakEff (1 << 6)
102#define S3C_GINTSTS_NPTxFEmp (1 << 5)
103#define S3C_GINTSTS_RxFLvl (1 << 4)
104#define S3C_GINTSTS_SOF (1 << 3)
105#define S3C_GINTSTS_OTGInt (1 << 2)
106#define S3C_GINTSTS_ModeMis (1 << 1)
107#define S3C_GINTSTS_CurMod_Host (1 << 0)
108
109#define S3C_GRXSTSR S3C_HSOTG_REG(0x01C)
110#define S3C_GRXSTSP S3C_HSOTG_REG(0x020)
111
112#define S3C_GRXSTS_FN_MASK (0x7f << 25)
113#define S3C_GRXSTS_FN_SHIFT (25)
114
115#define S3C_GRXSTS_PktSts_MASK (0xf << 17)
116#define S3C_GRXSTS_PktSts_SHIFT (17)
117#define S3C_GRXSTS_PktSts_GlobalOutNAK (0x1 << 17)
118#define S3C_GRXSTS_PktSts_OutRX (0x2 << 17)
119#define S3C_GRXSTS_PktSts_OutDone (0x3 << 17)
120#define S3C_GRXSTS_PktSts_SetupDone (0x4 << 17)
121#define S3C_GRXSTS_PktSts_SetupRX (0x6 << 17)
122
123#define S3C_GRXSTS_DPID_MASK (0x3 << 15)
124#define S3C_GRXSTS_DPID_SHIFT (15)
125#define S3C_GRXSTS_ByteCnt_MASK (0x7ff << 4)
126#define S3C_GRXSTS_ByteCnt_SHIFT (4)
127#define S3C_GRXSTS_EPNum_MASK (0xf << 0)
128#define S3C_GRXSTS_EPNum_SHIFT (0)
129
130#define S3C_GRXFSIZ S3C_HSOTG_REG(0x024)
131
132#define S3C_GNPTXFSIZ S3C_HSOTG_REG(0x028)
133
134#define S3C_GNPTXFSIZ_NPTxFDep_MASK (0xffff << 16)
135#define S3C_GNPTXFSIZ_NPTxFDep_SHIFT (16)
136#define S3C_GNPTXFSIZ_NPTxFDep_LIMIT (0xffff)
137#define S3C_GNPTXFSIZ_NPTxFDep(_x) ((_x) << 16)
138#define S3C_GNPTXFSIZ_NPTxFStAddr_MASK (0xffff << 0)
139#define S3C_GNPTXFSIZ_NPTxFStAddr_SHIFT (0)
140#define S3C_GNPTXFSIZ_NPTxFStAddr_LIMIT (0xffff)
141#define S3C_GNPTXFSIZ_NPTxFStAddr(_x) ((_x) << 0)
142
143#define S3C_GNPTXSTS S3C_HSOTG_REG(0x02C)
144
145#define S3C_GNPTXSTS_NPtxQTop_MASK (0x7f << 24)
146#define S3C_GNPTXSTS_NPtxQTop_SHIFT (24)
147
148#define S3C_GNPTXSTS_NPTxQSpcAvail_MASK (0xff << 16)
149#define S3C_GNPTXSTS_NPTxQSpcAvail_SHIFT (16)
150#define S3C_GNPTXSTS_NPTxQSpcAvail_GET(_v) (((_v) >> 16) & 0xff)
151
152#define S3C_GNPTXSTS_NPTxFSpcAvail_MASK (0xffff << 0)
153#define S3C_GNPTXSTS_NPTxFSpcAvail_SHIFT (0)
154#define S3C_GNPTXSTS_NPTxFSpcAvail_GET(_v) (((_v) >> 0) & 0xffff)
155
156
157#define S3C_HPTXFSIZ S3C_HSOTG_REG(0x100)
158
159#define S3C_DPTXFSIZn(_a) S3C_HSOTG_REG(0x104 + (((_a) - 1) * 4))
160
161#define S3C_DPTXFSIZn_DPTxFSize_MASK (0xffff << 16)
162#define S3C_DPTXFSIZn_DPTxFSize_SHIFT (16)
163#define S3C_DPTXFSIZn_DPTxFSize_GET(_v) (((_v) >> 16) & 0xffff)
164#define S3C_DPTXFSIZn_DPTxFSize_LIMIT (0xffff)
165#define S3C_DPTXFSIZn_DPTxFSize(_x) ((_x) << 16)
166
167#define S3C_DPTXFSIZn_DPTxFStAddr_MASK (0xffff << 0)
168#define S3C_DPTXFSIZn_DPTxFStAddr_SHIFT (0)
169
170/* Device mode registers */
171#define S3C_DCFG S3C_HSOTG_REG(0x800)
172
173#define S3C_DCFG_EPMisCnt_MASK (0x1f << 18)
174#define S3C_DCFG_EPMisCnt_SHIFT (18)
175#define S3C_DCFG_EPMisCnt_LIMIT (0x1f)
176#define S3C_DCFG_EPMisCnt(_x) ((_x) << 18)
177
178#define S3C_DCFG_PerFrInt_MASK (0x3 << 11)
179#define S3C_DCFG_PerFrInt_SHIFT (11)
180#define S3C_DCFG_PerFrInt_LIMIT (0x3)
181#define S3C_DCFG_PerFrInt(_x) ((_x) << 11)
182
183#define S3C_DCFG_DevAddr_MASK (0x7f << 4)
184#define S3C_DCFG_DevAddr_SHIFT (4)
185#define S3C_DCFG_DevAddr_LIMIT (0x7f)
186#define S3C_DCFG_DevAddr(_x) ((_x) << 4)
187
188#define S3C_DCFG_NZStsOUTHShk (1 << 2)
189
190#define S3C_DCFG_DevSpd_MASK (0x3 << 0)
191#define S3C_DCFG_DevSpd_SHIFT (0)
192#define S3C_DCFG_DevSpd_HS (0x0 << 0)
193#define S3C_DCFG_DevSpd_FS (0x1 << 0)
194#define S3C_DCFG_DevSpd_LS (0x2 << 0)
195#define S3C_DCFG_DevSpd_FS48 (0x3 << 0)
196
197#define S3C_DCTL S3C_HSOTG_REG(0x804)
198
199#define S3C_DCTL_PWROnPrgDone (1 << 11)
200#define S3C_DCTL_CGOUTNak (1 << 10)
201#define S3C_DCTL_SGOUTNak (1 << 9)
202#define S3C_DCTL_CGNPInNAK (1 << 8)
203#define S3C_DCTL_SGNPInNAK (1 << 7)
204#define S3C_DCTL_TstCtl_MASK (0x7 << 4)
205#define S3C_DCTL_TstCtl_SHIFT (4)
206#define S3C_DCTL_GOUTNakSts (1 << 3)
207#define S3C_DCTL_GNPINNakSts (1 << 2)
208#define S3C_DCTL_SftDiscon (1 << 1)
209#define S3C_DCTL_RmtWkUpSig (1 << 0)
210
211#define S3C_DSTS S3C_HSOTG_REG(0x808)
212
213#define S3C_DSTS_SOFFN_MASK (0x3fff << 8)
214#define S3C_DSTS_SOFFN_SHIFT (8)
215#define S3C_DSTS_SOFFN_LIMIT (0x3fff)
216#define S3C_DSTS_SOFFN(_x) ((_x) << 8)
217#define S3C_DSTS_ErraticErr (1 << 3)
218#define S3C_DSTS_EnumSpd_MASK (0x3 << 1)
219#define S3C_DSTS_EnumSpd_SHIFT (1)
220#define S3C_DSTS_EnumSpd_HS (0x0 << 1)
221#define S3C_DSTS_EnumSpd_FS (0x1 << 1)
222#define S3C_DSTS_EnumSpd_LS (0x2 << 1)
223#define S3C_DSTS_EnumSpd_FS48 (0x3 << 1)
224
225#define S3C_DSTS_SuspSts (1 << 0)
226
227#define S3C_DIEPMSK S3C_HSOTG_REG(0x810)
228
229#define S3C_DIEPMSK_INEPNakEffMsk (1 << 6)
230#define S3C_DIEPMSK_INTknEPMisMsk (1 << 5)
231#define S3C_DIEPMSK_INTknTXFEmpMsk (1 << 4)
232#define S3C_DIEPMSK_TimeOUTMsk (1 << 3)
233#define S3C_DIEPMSK_AHBErrMsk (1 << 2)
234#define S3C_DIEPMSK_EPDisbldMsk (1 << 1)
235#define S3C_DIEPMSK_XferComplMsk (1 << 0)
236
237#define S3C_DOEPMSK S3C_HSOTG_REG(0x814)
238
239#define S3C_DOEPMSK_Back2BackSetup (1 << 6)
240#define S3C_DOEPMSK_OUTTknEPdisMsk (1 << 4)
241#define S3C_DOEPMSK_SetupMsk (1 << 3)
242#define S3C_DOEPMSK_AHBErrMsk (1 << 2)
243#define S3C_DOEPMSK_EPDisbldMsk (1 << 1)
244#define S3C_DOEPMSK_XferComplMsk (1 << 0)
245
246#define S3C_DAINT S3C_HSOTG_REG(0x818)
247#define S3C_DAINTMSK S3C_HSOTG_REG(0x81C)
248
249#define S3C_DAINT_OutEP_SHIFT (16)
250#define S3C_DAINT_OutEP(x) (1 << ((x) + 16))
251#define S3C_DAINT_InEP(x) (1 << (x))
252
253#define S3C_DTKNQR1 S3C_HSOTG_REG(0x820)
254#define S3C_DTKNQR2 S3C_HSOTG_REG(0x824)
255#define S3C_DTKNQR3 S3C_HSOTG_REG(0x830)
256#define S3C_DTKNQR4 S3C_HSOTG_REG(0x834)
257
258#define S3C_DVBUSDIS S3C_HSOTG_REG(0x828)
259#define S3C_DVBUSPULSE S3C_HSOTG_REG(0x82C)
260
261#define S3C_DIEPCTL0 S3C_HSOTG_REG(0x900)
262#define S3C_DOEPCTL0 S3C_HSOTG_REG(0xB00)
263#define S3C_DIEPCTL(_a) S3C_HSOTG_REG(0x900 + ((_a) * 0x20))
264#define S3C_DOEPCTL(_a) S3C_HSOTG_REG(0xB00 + ((_a) * 0x20))
265
266/* EP0 specialness:
267 * bits[29..28] - reserved (no SetD0PID, SetD1PID)
268 * bits[25..22] - should always be zero, this isn't a periodic endpoint
269 * bits[10..0] - MPS setting differenct for EP0
270*/
271#define S3C_D0EPCTL_MPS_MASK (0x3 << 0)
272#define S3C_D0EPCTL_MPS_SHIFT (0)
273#define S3C_D0EPCTL_MPS_64 (0x0 << 0)
274#define S3C_D0EPCTL_MPS_32 (0x1 << 0)
275#define S3C_D0EPCTL_MPS_16 (0x2 << 0)
276#define S3C_D0EPCTL_MPS_8 (0x3 << 0)
277
278#define S3C_DxEPCTL_EPEna (1 << 31)
279#define S3C_DxEPCTL_EPDis (1 << 30)
280#define S3C_DxEPCTL_SetD1PID (1 << 29)
281#define S3C_DxEPCTL_SetOddFr (1 << 29)
282#define S3C_DxEPCTL_SetD0PID (1 << 28)
283#define S3C_DxEPCTL_SetEvenFr (1 << 28)
284#define S3C_DxEPCTL_SNAK (1 << 27)
285#define S3C_DxEPCTL_CNAK (1 << 26)
286#define S3C_DxEPCTL_TxFNum_MASK (0xf << 22)
287#define S3C_DxEPCTL_TxFNum_SHIFT (22)
288#define S3C_DxEPCTL_TxFNum_LIMIT (0xf)
289#define S3C_DxEPCTL_TxFNum(_x) ((_x) << 22)
290
291#define S3C_DxEPCTL_Stall (1 << 21)
292#define S3C_DxEPCTL_Snp (1 << 20)
293#define S3C_DxEPCTL_EPType_MASK (0x3 << 18)
294#define S3C_DxEPCTL_EPType_SHIFT (18)
295#define S3C_DxEPCTL_EPType_Control (0x0 << 18)
296#define S3C_DxEPCTL_EPType_Iso (0x1 << 18)
297#define S3C_DxEPCTL_EPType_Bulk (0x2 << 18)
298#define S3C_DxEPCTL_EPType_Intterupt (0x3 << 18)
299
300#define S3C_DxEPCTL_NAKsts (1 << 17)
301#define S3C_DxEPCTL_DPID (1 << 16)
302#define S3C_DxEPCTL_EOFrNum (1 << 16)
303#define S3C_DxEPCTL_USBActEp (1 << 15)
304#define S3C_DxEPCTL_NextEp_MASK (0xf << 11)
305#define S3C_DxEPCTL_NextEp_SHIFT (11)
306#define S3C_DxEPCTL_NextEp_LIMIT (0xf)
307#define S3C_DxEPCTL_NextEp(_x) ((_x) << 11)
308
309#define S3C_DxEPCTL_MPS_MASK (0x7ff << 0)
310#define S3C_DxEPCTL_MPS_SHIFT (0)
311#define S3C_DxEPCTL_MPS_LIMIT (0x7ff)
312#define S3C_DxEPCTL_MPS(_x) ((_x) << 0)
313
314#define S3C_DIEPINT(_a) S3C_HSOTG_REG(0x908 + ((_a) * 0x20))
315#define S3C_DOEPINT(_a) S3C_HSOTG_REG(0xB08 + ((_a) * 0x20))
316
317#define S3C_DxEPINT_INEPNakEff (1 << 6)
318#define S3C_DxEPINT_Back2BackSetup (1 << 6)
319#define S3C_DxEPINT_INTknEPMis (1 << 5)
320#define S3C_DxEPINT_INTknTXFEmp (1 << 4)
321#define S3C_DxEPINT_OUTTknEPdis (1 << 4)
322#define S3C_DxEPINT_Timeout (1 << 3)
323#define S3C_DxEPINT_Setup (1 << 3)
324#define S3C_DxEPINT_AHBErr (1 << 2)
325#define S3C_DxEPINT_EPDisbld (1 << 1)
326#define S3C_DxEPINT_XferCompl (1 << 0)
327
328#define S3C_DIEPTSIZ0 S3C_HSOTG_REG(0x910)
329
330#define S3C_DIEPTSIZ0_PktCnt_MASK (0x3 << 19)
331#define S3C_DIEPTSIZ0_PktCnt_SHIFT (19)
332#define S3C_DIEPTSIZ0_PktCnt_LIMIT (0x3)
333#define S3C_DIEPTSIZ0_PktCnt(_x) ((_x) << 19)
334
335#define S3C_DIEPTSIZ0_XferSize_MASK (0x7f << 0)
336#define S3C_DIEPTSIZ0_XferSize_SHIFT (0)
337#define S3C_DIEPTSIZ0_XferSize_LIMIT (0x7f)
338#define S3C_DIEPTSIZ0_XferSize(_x) ((_x) << 0)
339
340
341#define DOEPTSIZ0 S3C_HSOTG_REG(0xB10)
342#define S3C_DOEPTSIZ0_SUPCnt_MASK (0x3 << 29)
343#define S3C_DOEPTSIZ0_SUPCnt_SHIFT (29)
344#define S3C_DOEPTSIZ0_SUPCnt_LIMIT (0x3)
345#define S3C_DOEPTSIZ0_SUPCnt(_x) ((_x) << 29)
346
347#define S3C_DOEPTSIZ0_PktCnt (1 << 19)
348#define S3C_DOEPTSIZ0_XferSize_MASK (0x7f << 0)
349#define S3C_DOEPTSIZ0_XferSize_SHIFT (0)
350
351#define S3C_DIEPTSIZ(_a) S3C_HSOTG_REG(0x910 + ((_a) * 0x20))
352#define S3C_DOEPTSIZ(_a) S3C_HSOTG_REG(0xB10 + ((_a) * 0x20))
353
354#define S3C_DxEPTSIZ_MC_MASK (0x3 << 29)
355#define S3C_DxEPTSIZ_MC_SHIFT (29)
356#define S3C_DxEPTSIZ_MC_LIMIT (0x3)
357#define S3C_DxEPTSIZ_MC(_x) ((_x) << 29)
358
359#define S3C_DxEPTSIZ_PktCnt_MASK (0x3ff << 19)
360#define S3C_DxEPTSIZ_PktCnt_SHIFT (19)
361#define S3C_DxEPTSIZ_PktCnt_GET(_v) (((_v) >> 19) & 0x3ff)
362#define S3C_DxEPTSIZ_PktCnt_LIMIT (0x3ff)
363#define S3C_DxEPTSIZ_PktCnt(_x) ((_x) << 19)
364
365#define S3C_DxEPTSIZ_XferSize_MASK (0x7ffff << 0)
366#define S3C_DxEPTSIZ_XferSize_SHIFT (0)
367#define S3C_DxEPTSIZ_XferSize_GET(_v) (((_v) >> 0) & 0x7ffff)
368#define S3C_DxEPTSIZ_XferSize_LIMIT (0x7ffff)
369#define S3C_DxEPTSIZ_XferSize(_x) ((_x) << 0)
370
371
372#define S3C_DIEPDMA(_a) S3C_HSOTG_REG(0x914 + ((_a) * 0x20))
373#define S3C_DOEPDMA(_a) S3C_HSOTG_REG(0xB14 + ((_a) * 0x20))
374
375#define S3C_EPFIFO(_a) S3C_HSOTG_REG(0x1000 + ((_a) * 0x1000))
376
377#endif /* __PLAT_S3C64XX_REGS_USB_HSOTG_H */
diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types
index fec64678a63a..33026eff2aa4 100644
--- a/arch/arm/tools/mach-types
+++ b/arch/arm/tools/mach-types
@@ -12,7 +12,7 @@
12# 12#
13# http://www.arm.linux.org.uk/developer/machines/?action=new 13# http://www.arm.linux.org.uk/developer/machines/?action=new
14# 14#
15# Last update: Fri May 29 10:14:20 2009 15# Last update: Sat Jun 20 22:28:39 2009
16# 16#
17# machine_is_xxx CONFIG_xxxx MACH_TYPE_xxx number 17# machine_is_xxx CONFIG_xxxx MACH_TYPE_xxx number
18# 18#
@@ -1455,7 +1455,7 @@ gba MACH_GBA GBA 1457
1455h6044 MACH_H6044 H6044 1458 1455h6044 MACH_H6044 H6044 1458
1456app MACH_APP APP 1459 1456app MACH_APP APP 1459
1457tct_hammer MACH_TCT_HAMMER TCT_HAMMER 1460 1457tct_hammer MACH_TCT_HAMMER TCT_HAMMER 1460
1458herald MACH_HERMES HERMES 1461 1458herald MACH_HERALD HERALD 1461
1459artemis MACH_ARTEMIS ARTEMIS 1462 1459artemis MACH_ARTEMIS ARTEMIS 1462
1460htctitan MACH_HTCTITAN HTCTITAN 1463 1460htctitan MACH_HTCTITAN HTCTITAN 1463
1461qranium MACH_QRANIUM QRANIUM 1464 1461qranium MACH_QRANIUM QRANIUM 1464
@@ -2245,3 +2245,38 @@ str9 MACH_STR9 STR9 2257
2245omap3_wl_ff MACH_OMAP3_WL_FF OMAP3_WL_FF 2258 2245omap3_wl_ff MACH_OMAP3_WL_FF OMAP3_WL_FF 2258
2246simcom MACH_SIMCOM SIMCOM 2259 2246simcom MACH_SIMCOM SIMCOM 2259
2247mcwebio MACH_MCWEBIO MCWEBIO 2260 2247mcwebio MACH_MCWEBIO MCWEBIO 2260
2248omap3_phrazer MACH_OMAP3_PHRAZER OMAP3_PHRAZER 2261
2249darwin MACH_DARWIN DARWIN 2262
2250oratiscomu MACH_ORATISCOMU ORATISCOMU 2263
2251rtsbc20 MACH_RTSBC20 RTSBC20 2264
2252i780 MACH_I780 I780 2265
2253gemini324 MACH_GEMINI324 GEMINI324 2266
2254oratislan MACH_ORATISLAN ORATISLAN 2267
2255oratisalog MACH_ORATISALOG ORATISALOG 2268
2256oratismadi MACH_ORATISMADI ORATISMADI 2269
2257oratisot16 MACH_ORATISOT16 ORATISOT16 2270
2258oratisdesk MACH_ORATISDESK ORATISDESK 2271
2259v2p_ca9 MACH_V2P_CA9 V2P_CA9 2272
2260sintexo MACH_SINTEXO SINTEXO 2273
2261cm3389 MACH_CM3389 CM3389 2274
2262omap3_cio MACH_OMAP3_CIO OMAP3_CIO 2275
2263sgh_i900 MACH_SGH_I900 SGH_I900 2276
2264bst100 MACH_BST100 BST100 2277
2265passion MACH_PASSION PASSION 2278
2266indesign_at91sam MACH_INDESIGN_AT91SAM INDESIGN_AT91SAM 2279
2267c4_badger MACH_C4_BADGER C4_BADGER 2280
2268c4_viper MACH_C4_VIPER C4_VIPER 2281
2269d2net MACH_D2NET D2NET 2282
2270bigdisk MACH_BIGDISK BIGDISK 2283
2271notalvision MACH_NOTALVISION NOTALVISION 2284
2272omap3_kboc MACH_OMAP3_KBOC OMAP3_KBOC 2285
2273cyclone MACH_CYCLONE CYCLONE 2286
2274ninja MACH_NINJA NINJA 2287
2275at91sam9g20ek_2mmc MACH_AT91SAM9G20EK_2MMC AT91SAM9G20EK_2MMC 2288
2276bcmring MACH_BCMRING BCMRING 2289
2277resol_dl2 MACH_RESOL_DL2 RESOL_DL2 2290
2278ifosw MACH_IFOSW IFOSW 2291
2279htcrhodium MACH_HTCRHODIUM HTCRHODIUM 2292
2280htctopaz MACH_HTCTOPAZ HTCTOPAZ 2293
2281matrix504 MACH_MATRIX504 MATRIX504 2294
2282mrfsa MACH_MRFSA MRFSA 2295
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-09 03:45:21 -0500