diff options
Diffstat (limited to 'arch/arm')
-rw-r--r-- | arch/arm/include/asm/sizes.h | 1 | ||||
-rw-r--r-- | arch/arm/mach-ixp4xx/common-pci.c | 25 | ||||
-rw-r--r-- | arch/arm/mach-ixp4xx/include/mach/cpu.h | 35 | ||||
-rw-r--r-- | arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h | 42 | ||||
-rw-r--r-- | arch/arm/mach-ixp4xx/ixp4xx_npe.c | 6 |
5 files changed, 69 insertions, 40 deletions
diff --git a/arch/arm/include/asm/sizes.h b/arch/arm/include/asm/sizes.h index 503843db1565..c10d1aa4b487 100644 --- a/arch/arm/include/asm/sizes.h +++ b/arch/arm/include/asm/sizes.h | |||
@@ -43,6 +43,7 @@ | |||
43 | #define SZ_8M 0x00800000 | 43 | #define SZ_8M 0x00800000 |
44 | #define SZ_16M 0x01000000 | 44 | #define SZ_16M 0x01000000 |
45 | #define SZ_32M 0x02000000 | 45 | #define SZ_32M 0x02000000 |
46 | #define SZ_48M 0x03000000 | ||
46 | #define SZ_64M 0x04000000 | 47 | #define SZ_64M 0x04000000 |
47 | #define SZ_128M 0x08000000 | 48 | #define SZ_128M 0x08000000 |
48 | #define SZ_256M 0x10000000 | 49 | #define SZ_256M 0x10000000 |
diff --git a/arch/arm/mach-ixp4xx/common-pci.c b/arch/arm/mach-ixp4xx/common-pci.c index d816c51320c7..70afcfe5b881 100644 --- a/arch/arm/mach-ixp4xx/common-pci.c +++ b/arch/arm/mach-ixp4xx/common-pci.c | |||
@@ -366,7 +366,7 @@ void __init ixp4xx_adjust_zones(int node, unsigned long *zone_size, | |||
366 | } | 366 | } |
367 | 367 | ||
368 | void __init ixp4xx_pci_preinit(void) | 368 | void __init ixp4xx_pci_preinit(void) |
369 | { | 369 | { |
370 | unsigned long cpuid = read_cpuid_id(); | 370 | unsigned long cpuid = read_cpuid_id(); |
371 | 371 | ||
372 | /* | 372 | /* |
@@ -386,17 +386,17 @@ void __init ixp4xx_pci_preinit(void) | |||
386 | 386 | ||
387 | pr_debug("setup PCI-AHB(inbound) and AHB-PCI(outbound) address mappings\n"); | 387 | pr_debug("setup PCI-AHB(inbound) and AHB-PCI(outbound) address mappings\n"); |
388 | 388 | ||
389 | /* | 389 | /* |
390 | * We use identity AHB->PCI address translation | 390 | * We use identity AHB->PCI address translation |
391 | * in the 0x48000000 to 0x4bffffff address space | 391 | * in the 0x48000000 to 0x4bffffff address space |
392 | */ | 392 | */ |
393 | *PCI_PCIMEMBASE = 0x48494A4B; | 393 | *PCI_PCIMEMBASE = 0x48494A4B; |
394 | 394 | ||
395 | /* | 395 | /* |
396 | * We also use identity PCI->AHB address translation | 396 | * We also use identity PCI->AHB address translation |
397 | * in 4 16MB BARs that begin at the physical memory start | 397 | * in 4 16MB BARs that begin at the physical memory start |
398 | */ | 398 | */ |
399 | *PCI_AHBMEMBASE = (PHYS_OFFSET & 0xFF000000) + | 399 | *PCI_AHBMEMBASE = (PHYS_OFFSET & 0xFF000000) + |
400 | ((PHYS_OFFSET & 0xFF000000) >> 8) + | 400 | ((PHYS_OFFSET & 0xFF000000) >> 8) + |
401 | ((PHYS_OFFSET & 0xFF000000) >> 16) + | 401 | ((PHYS_OFFSET & 0xFF000000) >> 16) + |
402 | ((PHYS_OFFSET & 0xFF000000) >> 24) + | 402 | ((PHYS_OFFSET & 0xFF000000) >> 24) + |
@@ -408,18 +408,19 @@ void __init ixp4xx_pci_preinit(void) | |||
408 | pr_debug("setup BARs in controller\n"); | 408 | pr_debug("setup BARs in controller\n"); |
409 | 409 | ||
410 | /* | 410 | /* |
411 | * We configure the PCI inbound memory windows to be | 411 | * We configure the PCI inbound memory windows to be |
412 | * 1:1 mapped to SDRAM | 412 | * 1:1 mapped to SDRAM |
413 | */ | 413 | */ |
414 | local_write_config(PCI_BASE_ADDRESS_0, 4, PHYS_OFFSET + 0x00000000); | 414 | local_write_config(PCI_BASE_ADDRESS_0, 4, PHYS_OFFSET); |
415 | local_write_config(PCI_BASE_ADDRESS_1, 4, PHYS_OFFSET + 0x01000000); | 415 | local_write_config(PCI_BASE_ADDRESS_1, 4, PHYS_OFFSET + SZ_16M); |
416 | local_write_config(PCI_BASE_ADDRESS_2, 4, PHYS_OFFSET + 0x02000000); | 416 | local_write_config(PCI_BASE_ADDRESS_2, 4, PHYS_OFFSET + SZ_32M); |
417 | local_write_config(PCI_BASE_ADDRESS_3, 4, PHYS_OFFSET + 0x03000000); | 417 | local_write_config(PCI_BASE_ADDRESS_3, 4, PHYS_OFFSET + SZ_48M); |
418 | 418 | ||
419 | /* | 419 | /* |
420 | * Enable CSR window at 0xff000000. | 420 | * Enable CSR window at 64 MiB to allow PCI masters |
421 | * to continue prefetching past 64 MiB boundary. | ||
421 | */ | 422 | */ |
422 | local_write_config(PCI_BASE_ADDRESS_4, 4, 0xff000008); | 423 | local_write_config(PCI_BASE_ADDRESS_4, 4, PHYS_OFFSET + SZ_64M); |
423 | 424 | ||
424 | /* | 425 | /* |
425 | * Enable the IO window to be way up high, at 0xfffffc00 | 426 | * Enable the IO window to be way up high, at 0xfffffc00 |
@@ -500,7 +501,7 @@ int ixp4xx_setup(int nr, struct pci_sys_data *sys) | |||
500 | return 1; | 501 | return 1; |
501 | } | 502 | } |
502 | 503 | ||
503 | struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys) | 504 | struct pci_bus * __devinit ixp4xx_scan_bus(int nr, struct pci_sys_data *sys) |
504 | { | 505 | { |
505 | return pci_scan_bus(sys->busnr, &ixp4xx_ops, sys); | 506 | return pci_scan_bus(sys->busnr, &ixp4xx_ops, sys); |
506 | } | 507 | } |
diff --git a/arch/arm/mach-ixp4xx/include/mach/cpu.h b/arch/arm/mach-ixp4xx/include/mach/cpu.h index 51bd69c46d94..def7773be67c 100644 --- a/arch/arm/mach-ixp4xx/include/mach/cpu.h +++ b/arch/arm/mach-ixp4xx/include/mach/cpu.h | |||
@@ -17,26 +17,31 @@ | |||
17 | #include <asm/cputype.h> | 17 | #include <asm/cputype.h> |
18 | 18 | ||
19 | /* Processor id value in CP15 Register 0 */ | 19 | /* Processor id value in CP15 Register 0 */ |
20 | #define IXP425_PROCESSOR_ID_VALUE 0x690541c0 | 20 | #define IXP42X_PROCESSOR_ID_VALUE 0x690541c0 /* including unused 0x690541Ex */ |
21 | #define IXP435_PROCESSOR_ID_VALUE 0x69054040 | 21 | #define IXP42X_PROCESSOR_ID_MASK 0xffffffc0 |
22 | #define IXP465_PROCESSOR_ID_VALUE 0x69054200 | 22 | |
23 | #define IXP4XX_PROCESSOR_ID_MASK 0xfffffff0 | 23 | #define IXP43X_PROCESSOR_ID_VALUE 0x69054040 |
24 | 24 | #define IXP43X_PROCESSOR_ID_MASK 0xfffffff0 | |
25 | #define cpu_is_ixp42x() ((read_cpuid_id() & IXP4XX_PROCESSOR_ID_MASK) == \ | 25 | |
26 | IXP425_PROCESSOR_ID_VALUE) | 26 | #define IXP46X_PROCESSOR_ID_VALUE 0x69054200 /* including IXP455 */ |
27 | #define cpu_is_ixp43x() ((read_cpuid_id() & IXP4XX_PROCESSOR_ID_MASK) == \ | 27 | #define IXP46X_PROCESSOR_ID_MASK 0xfffffff0 |
28 | IXP435_PROCESSOR_ID_VALUE) | 28 | |
29 | #define cpu_is_ixp46x() ((read_cpuid_id() & IXP4XX_PROCESSOR_ID_MASK) == \ | 29 | #define cpu_is_ixp42x() ((read_cpuid_id() & IXP42X_PROCESSOR_ID_MASK) == \ |
30 | IXP465_PROCESSOR_ID_VALUE) | 30 | IXP42X_PROCESSOR_ID_VALUE) |
31 | #define cpu_is_ixp43x() ((read_cpuid_id() & IXP43X_PROCESSOR_ID_MASK) == \ | ||
32 | IXP43X_PROCESSOR_ID_VALUE) | ||
33 | #define cpu_is_ixp46x() ((read_cpuid_id() & IXP46X_PROCESSOR_ID_MASK) == \ | ||
34 | IXP46X_PROCESSOR_ID_VALUE) | ||
31 | 35 | ||
32 | static inline u32 ixp4xx_read_feature_bits(void) | 36 | static inline u32 ixp4xx_read_feature_bits(void) |
33 | { | 37 | { |
34 | unsigned int val = ~*IXP4XX_EXP_CFG2; | 38 | unsigned int val = ~*IXP4XX_EXP_CFG2; |
35 | val &= ~IXP4XX_FEATURE_RESERVED; | ||
36 | if (!cpu_is_ixp46x()) | ||
37 | val &= ~IXP4XX_FEATURE_IXP46X_ONLY; | ||
38 | 39 | ||
39 | return val; | 40 | if (cpu_is_ixp42x()) |
41 | return val & IXP42X_FEATURE_MASK; | ||
42 | if (cpu_is_ixp43x()) | ||
43 | return val & IXP43X_FEATURE_MASK; | ||
44 | return val & IXP46X_FEATURE_MASK; | ||
40 | } | 45 | } |
41 | 46 | ||
42 | static inline void ixp4xx_write_feature_bits(u32 value) | 47 | static inline void ixp4xx_write_feature_bits(u32 value) |
diff --git a/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h b/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h index ad9c888dd850..97c530f66e78 100644 --- a/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h +++ b/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h | |||
@@ -604,6 +604,7 @@ | |||
604 | #define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */ | 604 | #define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */ |
605 | 605 | ||
606 | /* "fuse" bits of IXP_EXP_CFG2 */ | 606 | /* "fuse" bits of IXP_EXP_CFG2 */ |
607 | /* All IXP4xx CPUs */ | ||
607 | #define IXP4XX_FEATURE_RCOMP (1 << 0) | 608 | #define IXP4XX_FEATURE_RCOMP (1 << 0) |
608 | #define IXP4XX_FEATURE_USB_DEVICE (1 << 1) | 609 | #define IXP4XX_FEATURE_USB_DEVICE (1 << 1) |
609 | #define IXP4XX_FEATURE_HASH (1 << 2) | 610 | #define IXP4XX_FEATURE_HASH (1 << 2) |
@@ -619,20 +620,41 @@ | |||
619 | #define IXP4XX_FEATURE_RESET_NPEB (1 << 12) | 620 | #define IXP4XX_FEATURE_RESET_NPEB (1 << 12) |
620 | #define IXP4XX_FEATURE_RESET_NPEC (1 << 13) | 621 | #define IXP4XX_FEATURE_RESET_NPEC (1 << 13) |
621 | #define IXP4XX_FEATURE_PCI (1 << 14) | 622 | #define IXP4XX_FEATURE_PCI (1 << 14) |
622 | #define IXP4XX_FEATURE_ECC_TIMESYNC (1 << 15) | ||
623 | #define IXP4XX_FEATURE_UTOPIA_PHY_LIMIT (3 << 16) | 623 | #define IXP4XX_FEATURE_UTOPIA_PHY_LIMIT (3 << 16) |
624 | #define IXP4XX_FEATURE_XSCALE_MAX_FREQ (3 << 22) | ||
625 | #define IXP42X_FEATURE_MASK (IXP4XX_FEATURE_RCOMP | \ | ||
626 | IXP4XX_FEATURE_USB_DEVICE | \ | ||
627 | IXP4XX_FEATURE_HASH | \ | ||
628 | IXP4XX_FEATURE_AES | \ | ||
629 | IXP4XX_FEATURE_DES | \ | ||
630 | IXP4XX_FEATURE_HDLC | \ | ||
631 | IXP4XX_FEATURE_AAL | \ | ||
632 | IXP4XX_FEATURE_HSS | \ | ||
633 | IXP4XX_FEATURE_UTOPIA | \ | ||
634 | IXP4XX_FEATURE_NPEB_ETH0 | \ | ||
635 | IXP4XX_FEATURE_NPEC_ETH | \ | ||
636 | IXP4XX_FEATURE_RESET_NPEA | \ | ||
637 | IXP4XX_FEATURE_RESET_NPEB | \ | ||
638 | IXP4XX_FEATURE_RESET_NPEC | \ | ||
639 | IXP4XX_FEATURE_PCI | \ | ||
640 | IXP4XX_FEATURE_UTOPIA_PHY_LIMIT | \ | ||
641 | IXP4XX_FEATURE_XSCALE_MAX_FREQ) | ||
642 | |||
643 | |||
644 | /* IXP43x/46x CPUs */ | ||
645 | #define IXP4XX_FEATURE_ECC_TIMESYNC (1 << 15) | ||
624 | #define IXP4XX_FEATURE_USB_HOST (1 << 18) | 646 | #define IXP4XX_FEATURE_USB_HOST (1 << 18) |
625 | #define IXP4XX_FEATURE_NPEA_ETH (1 << 19) | 647 | #define IXP4XX_FEATURE_NPEA_ETH (1 << 19) |
648 | #define IXP43X_FEATURE_MASK (IXP42X_FEATURE_MASK | \ | ||
649 | IXP4XX_FEATURE_ECC_TIMESYNC | \ | ||
650 | IXP4XX_FEATURE_USB_HOST | \ | ||
651 | IXP4XX_FEATURE_NPEA_ETH) | ||
652 | |||
653 | /* IXP46x CPU (including IXP455) only */ | ||
626 | #define IXP4XX_FEATURE_NPEB_ETH_1_TO_3 (1 << 20) | 654 | #define IXP4XX_FEATURE_NPEB_ETH_1_TO_3 (1 << 20) |
627 | #define IXP4XX_FEATURE_RSA (1 << 21) | 655 | #define IXP4XX_FEATURE_RSA (1 << 21) |
628 | #define IXP4XX_FEATURE_XSCALE_MAX_FREQ (3 << 22) | 656 | #define IXP46X_FEATURE_MASK (IXP43X_FEATURE_MASK | \ |
629 | #define IXP4XX_FEATURE_RESERVED (0xFF << 24) | 657 | IXP4XX_FEATURE_NPEB_ETH_1_TO_3 | \ |
630 | 658 | IXP4XX_FEATURE_RSA) | |
631 | #define IXP4XX_FEATURE_IXP46X_ONLY (IXP4XX_FEATURE_ECC_TIMESYNC | \ | ||
632 | IXP4XX_FEATURE_USB_HOST | \ | ||
633 | IXP4XX_FEATURE_NPEA_ETH | \ | ||
634 | IXP4XX_FEATURE_NPEB_ETH_1_TO_3 | \ | ||
635 | IXP4XX_FEATURE_RSA | \ | ||
636 | IXP4XX_FEATURE_XSCALE_MAX_FREQ) | ||
637 | 659 | ||
638 | #endif | 660 | #endif |
diff --git a/arch/arm/mach-ixp4xx/ixp4xx_npe.c b/arch/arm/mach-ixp4xx/ixp4xx_npe.c index c73a94d0ca2b..252310234903 100644 --- a/arch/arm/mach-ixp4xx/ixp4xx_npe.c +++ b/arch/arm/mach-ixp4xx/ixp4xx_npe.c | |||
@@ -575,8 +575,8 @@ int npe_load_firmware(struct npe *npe, const char *name, struct device *dev) | |||
575 | for (i = 0; i < image->size; i++) | 575 | for (i = 0; i < image->size; i++) |
576 | image->data[i] = swab32(image->data[i]); | 576 | image->data[i] = swab32(image->data[i]); |
577 | 577 | ||
578 | if (!cpu_is_ixp46x() && ((image->id >> 28) & 0xF /* device ID */)) { | 578 | if (cpu_is_ixp42x() && ((image->id >> 28) & 0xF /* device ID */)) { |
579 | print_npe(KERN_INFO, npe, "IXP46x firmware ignored on " | 579 | print_npe(KERN_INFO, npe, "IXP43x/IXP46x firmware ignored on " |
580 | "IXP42x\n"); | 580 | "IXP42x\n"); |
581 | goto err; | 581 | goto err; |
582 | } | 582 | } |
@@ -596,7 +596,7 @@ int npe_load_firmware(struct npe *npe, const char *name, struct device *dev) | |||
596 | "revision 0x%X:%X\n", (image->id >> 16) & 0xFF, | 596 | "revision 0x%X:%X\n", (image->id >> 16) & 0xFF, |
597 | (image->id >> 8) & 0xFF, image->id & 0xFF); | 597 | (image->id >> 8) & 0xFF, image->id & 0xFF); |
598 | 598 | ||
599 | if (!cpu_is_ixp46x()) { | 599 | if (cpu_is_ixp42x()) { |
600 | if (!npe->id) | 600 | if (!npe->id) |
601 | instr_size = NPE_A_42X_INSTR_SIZE; | 601 | instr_size = NPE_A_42X_INSTR_SIZE; |
602 | else | 602 | else |