14 files changed, 74 insertions, 38 deletions

diff --git a/arch/arm64/crypto/sha2-ce-glue.c b/arch/arm64/crypto/sha2-ce-glue.c
index c294e67d3925..ae67e88c28b9 100644
--- a/arch/arm64/crypto/sha2-ce-glue.c
+++ b/arch/arm64/crypto/sha2-ce-glue.c
@@ -150,7 +150,6 @@ static void sha2_finup(struct shash_desc *desc, const u8 *data,
         kernel_neon_begin_partial(28);
         sha2_ce_transform(blocks, data, sctx->state, NULL, len);
         kernel_neon_end();
-        data += blocks * SHA256_BLOCK_SIZE;
 }
 
 static int sha224_finup(struct shash_desc *desc, const u8 *data,
diff --git a/arch/arm64/include/asm/hw_breakpoint.h b/arch/arm64/include/asm/hw_breakpoint.h
index d064047612b1..52b484b6aa1a 100644
--- a/arch/arm64/include/asm/hw_breakpoint.h
+++ b/arch/arm64/include/asm/hw_breakpoint.h
@@ -79,7 +79,6 @@ static inline void decode_ctrl_reg(u32 reg,
  */
 #define ARM_MAX_BRP             16
 #define ARM_MAX_WRP             16
-#define ARM_MAX_HBP_SLOTS       (ARM_MAX_BRP + ARM_MAX_WRP)
 
 /* Virtual debug register bases. */
 #define AARCH64_DBG_REG_BVR     0
diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h
index 3df21feeabdd..286b1bec547c 100644
--- a/arch/arm64/include/asm/processor.h
+++ b/arch/arm64/include/asm/processor.h
@@ -139,7 +139,7 @@ extern struct task_struct *cpu_switch_to(struct task_struct *prev,
         ((struct pt_regs *)(THREAD_START_SP + task_stack_page(p)) - 1)
 
 #define KSTK_EIP(tsk)   ((unsigned long)task_pt_regs(tsk)->pc)
-#define KSTK_ESP(tsk)   ((unsigned long)task_pt_regs(tsk)->sp)
+#define KSTK_ESP(tsk)   user_stack_pointer(task_pt_regs(tsk))
 
 /*
  * Prefetching support
diff --git a/arch/arm64/include/asm/ptrace.h b/arch/arm64/include/asm/ptrace.h
index 501000fadb6f..41ed9e13795e 100644
--- a/arch/arm64/include/asm/ptrace.h
+++ b/arch/arm64/include/asm/ptrace.h
@@ -137,7 +137,7 @@ struct pt_regs {
         (!((regs)->pstate & PSR_F_BIT))
 
 #define user_stack_pointer(regs) \
-        (!compat_user_mode(regs)) ? ((regs)->sp) : ((regs)->compat_sp)
+        (!compat_user_mode(regs) ? (regs)->sp : (regs)->compat_sp)
 
 static inline unsigned long regs_return_value(struct pt_regs *regs)
 {
diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c
index ad8aebb1cdef..3dca15634e69 100644
--- a/arch/arm64/kernel/fpsimd.c
+++ b/arch/arm64/kernel/fpsimd.c
@@ -270,6 +270,7 @@ static int fpsimd_cpu_pm_notifier(struct notifier_block *self,
         case CPU_PM_ENTER:
                 if (current->mm && !test_thread_flag(TIF_FOREIGN_FPSTATE))
                         fpsimd_save_state(&current->thread.fpsimd_state);
+                this_cpu_write(fpsimd_last_state, NULL);
                 break;
         case CPU_PM_EXIT:
                 if (current->mm)
diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S
index bed028364a93..873069056229 100644
--- a/arch/arm64/kernel/head.S
+++ b/arch/arm64/kernel/head.S
@@ -373,10 +373,6 @@ ENTRY(__boot_cpu_mode)
         .long   0
         .popsection
 
-        .align  3
-2:      .quad   .
-        .quad   PAGE_OFFSET
-
 #ifdef CONFIG_SMP
         .align  3
 1:      .quad   .
diff --git a/arch/arm64/kernel/irq.c b/arch/arm64/kernel/irq.c
index 0f08dfd69ebc..dfa6e3e74fdd 100644
--- a/arch/arm64/kernel/irq.c
+++ b/arch/arm64/kernel/irq.c
@@ -97,19 +97,15 @@ static bool migrate_one_irq(struct irq_desc *desc)
         if (irqd_is_per_cpu(d) || !cpumask_test_cpu(smp_processor_id(), affinity))
                 return false;
 
-        if (cpumask_any_and(affinity, cpu_online_mask) >= nr_cpu_ids)
+        if (cpumask_any_and(affinity, cpu_online_mask) >= nr_cpu_ids) {
+                affinity = cpu_online_mask;
                 ret = true;
+        }
 
-        /*
-         * when using forced irq_set_affinity we must ensure that the cpu
-         * being offlined is not present in the affinity mask, it may be
-         * selected as the target CPU otherwise
-         */
-        affinity = cpu_online_mask;
         c = irq_data_get_irq_chip(d);
         if (!c->irq_set_affinity)
                 pr_debug("IRQ%u: unable to set affinity\n", d->irq);
-        else if (c->irq_set_affinity(d, affinity, true) == IRQ_SET_MASK_OK && ret)
+        else if (c->irq_set_affinity(d, affinity, false) == IRQ_SET_MASK_OK && ret)
                 cpumask_copy(d->affinity, affinity);
 
         return ret;
diff --git a/arch/arm64/kernel/perf_regs.c b/arch/arm64/kernel/perf_regs.c
index 422ebd63b619..6762ad705587 100644
--- a/arch/arm64/kernel/perf_regs.c
+++ b/arch/arm64/kernel/perf_regs.c
@@ -24,6 +24,12 @@ u64 perf_reg_value(struct pt_regs *regs, int idx)
                         return regs->compat_lr;
         }
 
+        if ((u32)idx == PERF_REG_ARM64_SP)
+                return regs->sp;
+
+        if ((u32)idx == PERF_REG_ARM64_PC)
+                return regs->pc;
+
         return regs->regs[idx];
 }
 
diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c
index 1309d64aa926..29d48690f2ac 100644
--- a/arch/arm64/kernel/process.c
+++ b/arch/arm64/kernel/process.c
@@ -230,9 +230,27 @@ void exit_thread(void)
 {
 }
 
+static void tls_thread_flush(void)
+{
+        asm ("msr tpidr_el0, xzr");
+
+        if (is_compat_task()) {
+                current->thread.tp_value = 0;
+
+                /*
+                 * We need to ensure ordering between the shadow state and the
+                 * hardware state, so that we don't corrupt the hardware state
+                 * with a stale shadow state during context switch.
+                 */
+                barrier();
+                asm ("msr tpidrro_el0, xzr");
+        }
+}
+
 void flush_thread(void)
 {
         fpsimd_flush_thread();
+        tls_thread_flush();
         flush_ptrace_hw_breakpoint(current);
 }
 
diff --git a/arch/arm64/kernel/ptrace.c b/arch/arm64/kernel/ptrace.c
index 70526cfda056..fe63ac5e9bf5 100644
--- a/arch/arm64/kernel/ptrace.c
+++ b/arch/arm64/kernel/ptrace.c
@@ -87,7 +87,8 @@ static void ptrace_hbptriggered(struct perf_event *bp,
                         break;
                 }
         }
-        for (i = ARM_MAX_BRP; i < ARM_MAX_HBP_SLOTS && !bp; ++i) {
+
+        for (i = 0; i < ARM_MAX_WRP; ++i) {
                 if (current->thread.debug.hbp_watch[i] == bp) {
                         info.si_errno = -((i << 1) + 1);
                         break;
@@ -662,8 +663,10 @@ static int compat_gpr_get(struct task_struct *target,
                         kbuf += sizeof(reg);
                 } else {
                         ret = copy_to_user(ubuf, &reg, sizeof(reg));
-                        if (ret)
+                        if (ret) {
+                                ret = -EFAULT;
                                 break;
+                        }
 
                         ubuf += sizeof(reg);
                 }
@@ -701,8 +704,10 @@ static int compat_gpr_set(struct task_struct *target,
                         kbuf += sizeof(reg);
                 } else {
                         ret = copy_from_user(&reg, ubuf, sizeof(reg));
-                        if (ret)
-                                return ret;
+                        if (ret) {
+                                ret = -EFAULT;
+                                break;
+                        }
 
                         ubuf += sizeof(reg);
                 }
diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c
index f6f0ccf35ae6..edb146d01857 100644
--- a/arch/arm64/kernel/setup.c
+++ b/arch/arm64/kernel/setup.c
@@ -78,6 +78,7 @@ unsigned int compat_elf_hwcap2 __read_mostly;
 #endif
 
 static const char *cpu_name;
+static const char *machine_name;
 phys_addr_t __fdt_pointer __initdata;
 
 /*
@@ -309,6 +310,8 @@ static void __init setup_machine_fdt(phys_addr_t dt_phys)
                 while (true)
                         cpu_relax();
         }
+
+        machine_name = of_flat_dt_get_machine_name();
 }
 
 /*
@@ -447,21 +450,10 @@ static int c_show(struct seq_file *m, void *v)
 {
         int i;
 
-        /*
-         * Dump out the common processor features in a single line. Userspace
-         * should read the hwcaps with getauxval(AT_HWCAP) rather than
-         * attempting to parse this.
-         */
-        seq_puts(m, "features\t:");
-        for (i = 0; hwcap_str[i]; i++)
-                if (elf_hwcap & (1 << i))
-                        seq_printf(m, " %s", hwcap_str[i]);
-        seq_puts(m, "\n\n");
+        seq_printf(m, "Processor\t: %s rev %d (%s)\n",
+                   cpu_name, read_cpuid_id() & 15, ELF_PLATFORM);
 
         for_each_online_cpu(i) {
-                struct cpuinfo_arm64 *cpuinfo = &per_cpu(cpu_data, i);
-                u32 midr = cpuinfo->reg_midr;
-
                 /*
                  * glibc reads /proc/cpuinfo to determine the number of
                  * online processors, looking for lines beginning with
@@ -470,13 +462,25 @@ static int c_show(struct seq_file *m, void *v)
 #ifdef CONFIG_SMP
                 seq_printf(m, "processor\t: %d\n", i);
 #endif
-                seq_printf(m, "implementer\t: 0x%02x\n",
-                           MIDR_IMPLEMENTOR(midr));
-                seq_printf(m, "variant\t\t: 0x%x\n", MIDR_VARIANT(midr));
-                seq_printf(m, "partnum\t\t: 0x%03x\n", MIDR_PARTNUM(midr));
-                seq_printf(m, "revision\t: 0x%x\n\n", MIDR_REVISION(midr));
         }
 
+        /* dump out the processor features */
+        seq_puts(m, "Features\t: ");
+
+        for (i = 0; hwcap_str[i]; i++)
+                if (elf_hwcap & (1 << i))
+                        seq_printf(m, "%s ", hwcap_str[i]);
+
+        seq_printf(m, "\nCPU implementer\t: 0x%02x\n", read_cpuid_id() >> 24);
+        seq_printf(m, "CPU architecture: AArch64\n");
+        seq_printf(m, "CPU variant\t: 0x%x\n", (read_cpuid_id() >> 20) & 15);
+        seq_printf(m, "CPU part\t: 0x%03x\n", (read_cpuid_id() >> 4) & 0xfff);
+        seq_printf(m, "CPU revision\t: %d\n", read_cpuid_id() & 15);
+
+        seq_puts(m, "\n");
+
+        seq_printf(m, "Hardware\t: %s\n", machine_name);
+
         return 0;
 }
 
diff --git a/arch/arm64/kernel/sys_compat.c b/arch/arm64/kernel/sys_compat.c
index de2b0226e06d..dc47e53e9e28 100644
--- a/arch/arm64/kernel/sys_compat.c
+++ b/arch/arm64/kernel/sys_compat.c
@@ -79,6 +79,12 @@ long compat_arm_syscall(struct pt_regs *regs)
 
         case __ARM_NR_compat_set_tls:
                 current->thread.tp_value = regs->regs[0];
+
+                /*
+                 * Protect against register corruption from context switch.
+                 * See comment in tls_thread_flush.
+                 */
+                barrier();
                 asm ("msr tpidrro_el0, %0" : : "r" (regs->regs[0]));
                 return 0;
 
diff --git a/arch/arm64/kvm/handle_exit.c b/arch/arm64/kvm/handle_exit.c
index e28be510380c..34b8bd0711e9 100644
--- a/arch/arm64/kvm/handle_exit.c
+++ b/arch/arm64/kvm/handle_exit.c
@@ -66,6 +66,8 @@ static int kvm_handle_wfx(struct kvm_vcpu *vcpu, struct kvm_run *run)
         else
                 kvm_vcpu_block(vcpu);
 
+        kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
+
         return 1;
 }
 
diff --git a/arch/arm64/kvm/hyp-init.S b/arch/arm64/kvm/hyp-init.S
index d968796f4b2d..c3191168a994 100644
--- a/arch/arm64/kvm/hyp-init.S
+++ b/arch/arm64/kvm/hyp-init.S
@@ -80,6 +80,10 @@ __do_hyp_init:
         msr     mair_el2, x4
         isb
 
+        /* Invalidate the stale TLBs from Bootloader */
+        tlbi    alle2
+        dsb     sy
+
         mrs     x4, sctlr_el2
         and     x4, x4, #SCTLR_EL2_EE   // preserve endianness of EL2
         ldr     x5, =SCTLR_EL2_FLAGS