1 files changed, 7 insertions, 7 deletions

diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
index 1333e6f9a8e5..e085ee6ef4e2 100644
--- a/arch/arm64/mm/proc.S
+++ b/arch/arm64/mm/proc.S
@@ -173,12 +173,6 @@ ENDPROC(cpu_do_switch_mm)
  *      value of the SCTLR_EL1 register.
  */
 ENTRY(__cpu_setup)
-        /*
-         * Preserve the link register across the function call.
-         */
-        mov     x28, lr
-        bl      __flush_dcache_all
-        mov     lr, x28
         ic      iallu                           // I+BTB cache invalidate
         tlbi    vmalle1is                       // invalidate I + D TLBs
         dsb     sy
@@ -215,8 +209,14 @@ ENTRY(__cpu_setup)
          * Set/prepare TCR and TTBR. We use 512GB (39-bit) address range for
          * both user and kernel.
          */
-        ldr     x10, =TCR_TxSZ(VA_BITS) | TCR_FLAGS | TCR_IPS_40BIT | \
+        ldr     x10, =TCR_TxSZ(VA_BITS) | TCR_FLAGS | \
                       TCR_ASID16 | TCR_TBI0 | (1 << 31)
+        /*
+         * Read the PARange bits from ID_AA64MMFR0_EL1 and set the IPS bits in
+         * TCR_EL1.
+         */
+        mrs     x9, ID_AA64MMFR0_EL1
+        bfi     x10, x9, #32, #3
 #ifdef CONFIG_ARM64_64K_PAGES
         orr     x10, x10, TCR_TG0_64K
         orr     x10, x10, TCR_TG1_64K