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-rw-r--r--arch/arm64/kernel/head.S18
1 files changed, 18 insertions, 0 deletions
diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S
index a96d3a6a63f6..96623502519c 100644
--- a/arch/arm64/kernel/head.S
+++ b/arch/arm64/kernel/head.S
@@ -22,6 +22,7 @@
22 22
23#include <linux/linkage.h> 23#include <linux/linkage.h>
24#include <linux/init.h> 24#include <linux/init.h>
25#include <linux/irqchip/arm-gic-v3.h>
25 26
26#include <asm/assembler.h> 27#include <asm/assembler.h>
27#include <asm/ptrace.h> 28#include <asm/ptrace.h>
@@ -296,6 +297,23 @@ CPU_LE( bic x0, x0, #(3 << 24) ) // Clear the EE and E0E bits for EL1
296 msr cnthctl_el2, x0 297 msr cnthctl_el2, x0
297 msr cntvoff_el2, xzr // Clear virtual offset 298 msr cntvoff_el2, xzr // Clear virtual offset
298 299
300#ifdef CONFIG_ARM_GIC_V3
301 /* GICv3 system register access */
302 mrs x0, id_aa64pfr0_el1
303 ubfx x0, x0, #24, #4
304 cmp x0, #1
305 b.ne 3f
306
307 mrs x0, ICC_SRE_EL2
308 orr x0, x0, #ICC_SRE_EL2_SRE // Set ICC_SRE_EL2.SRE==1
309 orr x0, x0, #ICC_SRE_EL2_ENABLE // Set ICC_SRE_EL2.Enable==1
310 msr ICC_SRE_EL2, x0
311 isb // Make sure SRE is now set
312 msr ICH_HCR_EL2, xzr // Reset ICC_HCR_EL2 to defaults
313
3143:
315#endif
316
299 /* Populate ID registers. */ 317 /* Populate ID registers. */
300 mrs x0, midr_el1 318 mrs x0, midr_el1
301 mrs x1, mpidr_el1 319 mrs x1, mpidr_el1