10 files changed, 67 insertions, 44 deletions

diff --git a/arch/arm64/include/asm/atomic.h b/arch/arm64/include/asm/atomic.h
index 01de5aaa3edc..0237f0867e37 100644
--- a/arch/arm64/include/asm/atomic.h
+++ b/arch/arm64/include/asm/atomic.h
@@ -54,8 +54,7 @@ static inline void atomic_add(int i, atomic_t *v)
 "       stxr    %w1, %w0, %2\n"
 "       cbnz    %w1, 1b"
         : "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
-        : "Ir" (i)
-        : "cc");
+        : "Ir" (i));
 }
 
 static inline int atomic_add_return(int i, atomic_t *v)
@@ -64,14 +63,15 @@ static inline int atomic_add_return(int i, atomic_t *v)
         int result;
 
         asm volatile("// atomic_add_return\n"
-"1:     ldaxr   %w0, %2\n"
+"1:     ldxr    %w0, %2\n"
 "       add     %w0, %w0, %w3\n"
 "       stlxr   %w1, %w0, %2\n"
 "       cbnz    %w1, 1b"
         : "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
         : "Ir" (i)
-        : "cc", "memory");
+        : "memory");
 
+        smp_mb();
         return result;
 }
 
@@ -86,8 +86,7 @@ static inline void atomic_sub(int i, atomic_t *v)
 "       stxr    %w1, %w0, %2\n"
 "       cbnz    %w1, 1b"
         : "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
-        : "Ir" (i)
-        : "cc");
+        : "Ir" (i));
 }
 
 static inline int atomic_sub_return(int i, atomic_t *v)
@@ -96,14 +95,15 @@ static inline int atomic_sub_return(int i, atomic_t *v)
         int result;
 
         asm volatile("// atomic_sub_return\n"
-"1:     ldaxr   %w0, %2\n"
+"1:     ldxr    %w0, %2\n"
 "       sub     %w0, %w0, %w3\n"
 "       stlxr   %w1, %w0, %2\n"
 "       cbnz    %w1, 1b"
         : "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
         : "Ir" (i)
-        : "cc", "memory");
+        : "memory");
 
+        smp_mb();
         return result;
 }
 
@@ -112,17 +112,20 @@ static inline int atomic_cmpxchg(atomic_t *ptr, int old, int new)
         unsigned long tmp;
         int oldval;
 
+        smp_mb();
+
         asm volatile("// atomic_cmpxchg\n"
-"1:     ldaxr   %w1, %2\n"
+"1:     ldxr    %w1, %2\n"
 "       cmp     %w1, %w3\n"
 "       b.ne    2f\n"
-"       stlxr   %w0, %w4, %2\n"
+"       stxr    %w0, %w4, %2\n"
 "       cbnz    %w0, 1b\n"
 "2:"
         : "=&r" (tmp), "=&r" (oldval), "+Q" (ptr->counter)
         : "Ir" (old), "r" (new)
-        : "cc", "memory");
+        : "cc");
 
+        smp_mb();
         return oldval;
 }
 
@@ -173,8 +176,7 @@ static inline void atomic64_add(u64 i, atomic64_t *v)
 "       stxr    %w1, %0, %2\n"
 "       cbnz    %w1, 1b"
         : "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
-        : "Ir" (i)
-        : "cc");
+        : "Ir" (i));
 }
 
 static inline long atomic64_add_return(long i, atomic64_t *v)
@@ -183,14 +185,15 @@ static inline long atomic64_add_return(long i, atomic64_t *v)
         unsigned long tmp;
 
         asm volatile("// atomic64_add_return\n"
-"1:     ldaxr   %0, %2\n"
+"1:     ldxr    %0, %2\n"
 "       add     %0, %0, %3\n"
 "       stlxr   %w1, %0, %2\n"
 "       cbnz    %w1, 1b"
         : "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
         : "Ir" (i)
-        : "cc", "memory");
+        : "memory");
 
+        smp_mb();
         return result;
 }
 
@@ -205,8 +208,7 @@ static inline void atomic64_sub(u64 i, atomic64_t *v)
 "       stxr    %w1, %0, %2\n"
 "       cbnz    %w1, 1b"
         : "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
-        : "Ir" (i)
-        : "cc");
+        : "Ir" (i));
 }
 
 static inline long atomic64_sub_return(long i, atomic64_t *v)
@@ -215,14 +217,15 @@ static inline long atomic64_sub_return(long i, atomic64_t *v)
         unsigned long tmp;
 
         asm volatile("// atomic64_sub_return\n"
-"1:     ldaxr   %0, %2\n"
+"1:     ldxr    %0, %2\n"
 "       sub     %0, %0, %3\n"
 "       stlxr   %w1, %0, %2\n"
 "       cbnz    %w1, 1b"
         : "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
         : "Ir" (i)
-        : "cc", "memory");
+        : "memory");
 
+        smp_mb();
         return result;
 }
 
@@ -231,17 +234,20 @@ static inline long atomic64_cmpxchg(atomic64_t *ptr, long old, long new)
         long oldval;
         unsigned long res;
 
+        smp_mb();
+
         asm volatile("// atomic64_cmpxchg\n"
-"1:     ldaxr   %1, %2\n"
+"1:     ldxr    %1, %2\n"
 "       cmp     %1, %3\n"
 "       b.ne    2f\n"
-"       stlxr   %w0, %4, %2\n"
+"       stxr    %w0, %4, %2\n"
 "       cbnz    %w0, 1b\n"
 "2:"
         : "=&r" (res), "=&r" (oldval), "+Q" (ptr->counter)
         : "Ir" (old), "r" (new)
-        : "cc", "memory");
+        : "cc");
 
+        smp_mb();
         return oldval;
 }
 
@@ -253,11 +259,12 @@ static inline long atomic64_dec_if_positive(atomic64_t *v)
         unsigned long tmp;
 
         asm volatile("// atomic64_dec_if_positive\n"
-"1:     ldaxr   %0, %2\n"
+"1:     ldxr    %0, %2\n"
 "       subs    %0, %0, #1\n"
 "       b.mi    2f\n"
 "       stlxr   %w1, %0, %2\n"
 "       cbnz    %w1, 1b\n"
+"       dmb     ish\n"
 "2:"
         : "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
         :
diff --git a/arch/arm64/include/asm/barrier.h b/arch/arm64/include/asm/barrier.h
index 78e20ba8806b..409ca370cfe2 100644
--- a/arch/arm64/include/asm/barrier.h
+++ b/arch/arm64/include/asm/barrier.h
@@ -25,7 +25,7 @@
 #define wfi()           asm volatile("wfi" : : : "memory")
 
 #define isb()           asm volatile("isb" : : : "memory")
-#define dsb()           asm volatile("dsb sy" : : : "memory")
+#define dsb(opt)        asm volatile("dsb sy" : : : "memory")
 
 #define mb()            dsb()
 #define rmb()           asm volatile("dsb ld" : : : "memory")
diff --git a/arch/arm64/include/asm/cacheflush.h b/arch/arm64/include/asm/cacheflush.h
index fea9ee327206..889324981aa4 100644
--- a/arch/arm64/include/asm/cacheflush.h
+++ b/arch/arm64/include/asm/cacheflush.h
@@ -116,6 +116,7 @@ extern void flush_dcache_page(struct page *);
 static inline void __flush_icache_all(void)
 {
         asm("ic ialluis");
+        dsb();
 }
 
 #define flush_dcache_mmap_lock(mapping) \
diff --git a/arch/arm64/include/asm/cmpxchg.h b/arch/arm64/include/asm/cmpxchg.h
index 56166d7f4a25..57c0fa7bf711 100644
--- a/arch/arm64/include/asm/cmpxchg.h
+++ b/arch/arm64/include/asm/cmpxchg.h
@@ -29,44 +29,45 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size
         switch (size) {
         case 1:
                 asm volatile("//        __xchg1\n"
-                "1:     ldaxrb  %w0, %2\n"
+                "1:     ldxrb   %w0, %2\n"
                 "       stlxrb  %w1, %w3, %2\n"
                 "       cbnz    %w1, 1b\n"
                         : "=&r" (ret), "=&r" (tmp), "+Q" (*(u8 *)ptr)
                         : "r" (x)
-                        : "cc", "memory");
+                        : "memory");
                 break;
         case 2:
                 asm volatile("//        __xchg2\n"
-                "1:     ldaxrh  %w0, %2\n"
+                "1:     ldxrh   %w0, %2\n"
                 "       stlxrh  %w1, %w3, %2\n"
                 "       cbnz    %w1, 1b\n"
                         : "=&r" (ret), "=&r" (tmp), "+Q" (*(u16 *)ptr)
                         : "r" (x)
-                        : "cc", "memory");
+                        : "memory");
                 break;
         case 4:
                 asm volatile("//        __xchg4\n"
-                "1:     ldaxr   %w0, %2\n"
+                "1:     ldxr    %w0, %2\n"
                 "       stlxr   %w1, %w3, %2\n"
                 "       cbnz    %w1, 1b\n"
                         : "=&r" (ret), "=&r" (tmp), "+Q" (*(u32 *)ptr)
                         : "r" (x)
-                        : "cc", "memory");
+                        : "memory");
                 break;
         case 8:
                 asm volatile("//        __xchg8\n"
-                "1:     ldaxr   %0, %2\n"
+                "1:     ldxr    %0, %2\n"
                 "       stlxr   %w1, %3, %2\n"
                 "       cbnz    %w1, 1b\n"
                         : "=&r" (ret), "=&r" (tmp), "+Q" (*(u64 *)ptr)
                         : "r" (x)
-                        : "cc", "memory");
+                        : "memory");
                 break;
         default:
                 BUILD_BUG();
         }
 
+        smp_mb();
         return ret;
 }
 
diff --git a/arch/arm64/include/asm/esr.h b/arch/arm64/include/asm/esr.h
index 78834123a32e..c4a7f940b387 100644
--- a/arch/arm64/include/asm/esr.h
+++ b/arch/arm64/include/asm/esr.h
@@ -42,7 +42,7 @@
 #define ESR_EL1_EC_SP_ALIGN     (0x26)
 #define ESR_EL1_EC_FP_EXC32     (0x28)
 #define ESR_EL1_EC_FP_EXC64     (0x2C)
-#define ESR_EL1_EC_SERRROR      (0x2F)
+#define ESR_EL1_EC_SERROR       (0x2F)
 #define ESR_EL1_EC_BREAKPT_EL0  (0x30)
 #define ESR_EL1_EC_BREAKPT_EL1  (0x31)
 #define ESR_EL1_EC_SOFTSTP_EL0  (0x32)
diff --git a/arch/arm64/include/asm/futex.h b/arch/arm64/include/asm/futex.h
index 78cc3aba5d69..5f750dc96e0f 100644
--- a/arch/arm64/include/asm/futex.h
+++ b/arch/arm64/include/asm/futex.h
@@ -24,10 +24,11 @@
 
 #define __futex_atomic_op(insn, ret, oldval, uaddr, tmp, oparg)         \
         asm volatile(                                                   \
-"1:     ldaxr   %w1, %2\n"                                              \
+"1:     ldxr    %w1, %2\n"                                              \
         insn "\n"                                                       \
 "2:     stlxr   %w3, %w0, %2\n"                                         \
 "       cbnz    %w3, 1b\n"                                              \
+"       dmb     ish\n"                                                  \
 "3:\n"                                                                  \
 "       .pushsection .fixup,\"ax\"\n"                                   \
 "       .align  2\n"                                                    \
@@ -40,7 +41,7 @@
 "       .popsection\n"                                                  \
         : "=&r" (ret), "=&r" (oldval), "+Q" (*uaddr), "=&r" (tmp)       \
         : "r" (oparg), "Ir" (-EFAULT)                                   \
-        : "cc", "memory")
+        : "memory")
 
 static inline int
 futex_atomic_op_inuser (int encoded_op, u32 __user *uaddr)
@@ -111,11 +112,12 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
                 return -EFAULT;
 
         asm volatile("// futex_atomic_cmpxchg_inatomic\n"
-"1:     ldaxr   %w1, %2\n"
+"1:     ldxr    %w1, %2\n"
 "       sub     %w3, %w1, %w4\n"
 "       cbnz    %w3, 3f\n"
 "2:     stlxr   %w3, %w5, %2\n"
 "       cbnz    %w3, 1b\n"
+"       dmb     ish\n"
 "3:\n"
 "       .pushsection .fixup,\"ax\"\n"
 "4:     mov     %w0, %w6\n"
@@ -127,7 +129,7 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
 "       .popsection\n"
         : "+r" (ret), "=&r" (val), "+Q" (*uaddr), "=&r" (tmp)
         : "r" (oldval), "r" (newval), "Ir" (-EFAULT)
-        : "cc", "memory");
+        : "memory");
 
         *uval = val;
         return ret;
diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h
index c98ef4771c73..0eb398655378 100644
--- a/arch/arm64/include/asm/kvm_arm.h
+++ b/arch/arm64/include/asm/kvm_arm.h
@@ -231,7 +231,7 @@
 #define ESR_EL2_EC_SP_ALIGN     (0x26)
 #define ESR_EL2_EC_FP_EXC32     (0x28)
 #define ESR_EL2_EC_FP_EXC64     (0x2C)
-#define ESR_EL2_EC_SERRROR      (0x2F)
+#define ESR_EL2_EC_SERROR       (0x2F)
 #define ESR_EL2_EC_BREAKPT      (0x30)
 #define ESR_EL2_EC_BREAKPT_HYP  (0x31)
 #define ESR_EL2_EC_SOFTSTP      (0x32)
diff --git a/arch/arm64/include/asm/spinlock.h b/arch/arm64/include/asm/spinlock.h
index 3d5cf064d7a1..c45b7b1b7197 100644
--- a/arch/arm64/include/asm/spinlock.h
+++ b/arch/arm64/include/asm/spinlock.h
@@ -132,7 +132,7 @@ static inline void arch_write_lock(arch_rwlock_t *rw)
         "       cbnz    %w0, 2b\n"
         : "=&r" (tmp), "+Q" (rw->lock)
         : "r" (0x80000000)
-        : "cc", "memory");
+        : "memory");
 }
 
 static inline int arch_write_trylock(arch_rwlock_t *rw)
@@ -146,7 +146,7 @@ static inline int arch_write_trylock(arch_rwlock_t *rw)
         "1:\n"
         : "=&r" (tmp), "+Q" (rw->lock)
         : "r" (0x80000000)
-        : "cc", "memory");
+        : "memory");
 
         return !tmp;
 }
@@ -187,7 +187,7 @@ static inline void arch_read_lock(arch_rwlock_t *rw)
         "       cbnz    %w1, 2b\n"
         : "=&r" (tmp), "=&r" (tmp2), "+Q" (rw->lock)
         :
-        : "cc", "memory");
+        : "memory");
 }
 
 static inline void arch_read_unlock(arch_rwlock_t *rw)
@@ -201,7 +201,7 @@ static inline void arch_read_unlock(arch_rwlock_t *rw)
         "       cbnz    %w1, 1b\n"
         : "=&r" (tmp), "=&r" (tmp2), "+Q" (rw->lock)
         :
-        : "cc", "memory");
+        : "memory");
 }
 
 static inline int arch_read_trylock(arch_rwlock_t *rw)
@@ -216,7 +216,7 @@ static inline int arch_read_trylock(arch_rwlock_t *rw)
         "1:\n"
         : "=&r" (tmp), "+r" (tmp2), "+Q" (rw->lock)
         :
-        : "cc", "memory");
+        : "memory");
 
         return !tmp2;
 }
diff --git a/arch/arm64/include/asm/unistd32.h b/arch/arm64/include/asm/unistd32.h
index 58125bf008d3..bb8eb8a78e67 100644
--- a/arch/arm64/include/asm/unistd32.h
+++ b/arch/arm64/include/asm/unistd32.h
@@ -399,7 +399,10 @@ __SYSCALL(374, compat_sys_sendmmsg)
 __SYSCALL(375, sys_setns)
 __SYSCALL(376, compat_sys_process_vm_readv)
 __SYSCALL(377, compat_sys_process_vm_writev)
-__SYSCALL(378, sys_ni_syscall)                  /* 378 for kcmp */
+__SYSCALL(378, sys_kcmp)
+__SYSCALL(379, sys_finit_module)
+__SYSCALL(380, sys_sched_setattr)
+__SYSCALL(381, sys_sched_getattr)
 
 #define __NR_compat_syscalls            379
 
diff --git a/arch/arm64/include/uapi/asm/kvm.h b/arch/arm64/include/uapi/asm/kvm.h
index 495ab6f84a61..eaf54a30bedc 100644
--- a/arch/arm64/include/uapi/asm/kvm.h
+++ b/arch/arm64/include/uapi/asm/kvm.h
@@ -148,6 +148,15 @@ struct kvm_arch_memory_slot {
 #define KVM_REG_ARM_TIMER_CNT           ARM64_SYS_REG(3, 3, 14, 3, 2)
 #define KVM_REG_ARM_TIMER_CVAL          ARM64_SYS_REG(3, 3, 14, 0, 2)
 
+/* Device Control API: ARM VGIC */
+#define KVM_DEV_ARM_VGIC_GRP_ADDR       0
+#define KVM_DEV_ARM_VGIC_GRP_DIST_REGS  1
+#define KVM_DEV_ARM_VGIC_GRP_CPU_REGS   2
+#define   KVM_DEV_ARM_VGIC_CPUID_SHIFT  32
+#define   KVM_DEV_ARM_VGIC_CPUID_MASK   (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT)
+#define   KVM_DEV_ARM_VGIC_OFFSET_SHIFT 0
+#define   KVM_DEV_ARM_VGIC_OFFSET_MASK  (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT)
+
 /* KVM_IRQ_LINE irq field index values */
 #define KVM_ARM_IRQ_TYPE_SHIFT          24
 #define KVM_ARM_IRQ_TYPE_MASK           0xff