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-rw-r--r--arch/arm64/boot/dts/Makefile3
-rw-r--r--arch/arm64/boot/dts/apm/apm-mustang.dts4
-rw-r--r--arch/arm64/boot/dts/apm/apm-storm.dtsi36
-rw-r--r--arch/arm64/boot/dts/arm/foundation-v8.dts8
-rw-r--r--arch/arm64/boot/dts/arm/juno-clocks.dtsi2
-rw-r--r--arch/arm64/boot/dts/arm/juno.dts28
-rw-r--r--arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts8
-rw-r--r--arch/arm64/boot/dts/mediatek/mt8173-pinfunc.h682
-rw-r--r--arch/arm64/boot/dts/mediatek/mt8173.dtsi20
-rw-r--r--arch/arm64/boot/dts/qcom/Makefile5
-rw-r--r--arch/arm64/boot/dts/qcom/apq8016-sbc.dts21
-rw-r--r--arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi33
-rw-r--r--arch/arm64/boot/dts/qcom/msm8916-mtp.dts22
-rw-r--r--arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi33
-rw-r--r--arch/arm64/boot/dts/qcom/msm8916.dtsi196
-rw-r--r--arch/arm64/boot/dts/sprd/Makefile5
-rw-r--r--arch/arm64/boot/dts/sprd/sc9836-openphone.dts49
-rw-r--r--arch/arm64/boot/dts/sprd/sc9836.dtsi129
-rw-r--r--arch/arm64/boot/dts/sprd/sharkl64.dtsi65
-rw-r--r--arch/arm64/boot/dts/xilinx/Makefile5
-rw-r--r--arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts47
-rw-r--r--arch/arm64/boot/dts/xilinx/zynqmp.dtsi305
22 files changed, 1697 insertions, 9 deletions
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index e0350caf049e..ad26a752b976 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -5,5 +5,8 @@ dts-dirs += cavium
5dts-dirs += exynos 5dts-dirs += exynos
6dts-dirs += freescale 6dts-dirs += freescale
7dts-dirs += mediatek 7dts-dirs += mediatek
8dts-dirs += qcom
9dts-dirs += sprd
10dts-dirs += xilinx
8 11
9subdir-y := $(dts-dirs) 12subdir-y := $(dts-dirs)
diff --git a/arch/arm64/boot/dts/apm/apm-mustang.dts b/arch/arm64/boot/dts/apm/apm-mustang.dts
index 2e25de0800b9..83578e766b94 100644
--- a/arch/arm64/boot/dts/apm/apm-mustang.dts
+++ b/arch/arm64/boot/dts/apm/apm-mustang.dts
@@ -45,6 +45,10 @@
45 status = "ok"; 45 status = "ok";
46}; 46};
47 47
48&sgenet1 {
49 status = "ok";
50};
51
48&xgenet { 52&xgenet {
49 status = "ok"; 53 status = "ok";
50}; 54};
diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi
index 947177004039..c8d3e0e86678 100644
--- a/arch/arm64/boot/dts/apm/apm-storm.dtsi
+++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi
@@ -187,6 +187,16 @@
187 clock-output-names = "sge0clk"; 187 clock-output-names = "sge0clk";
188 }; 188 };
189 189
190 sge1clk: sge1clk@1f21c000 {
191 compatible = "apm,xgene-device-clock";
192 #clock-cells = <1>;
193 clocks = <&socplldiv2 0>;
194 reg = <0x0 0x1f21c000 0x0 0x1000>;
195 reg-names = "csr-reg";
196 csr-mask = <0xc>;
197 clock-output-names = "sge1clk";
198 };
199
190 xge0clk: xge0clk@1f61c000 { 200 xge0clk: xge0clk@1f61c000 {
191 compatible = "apm,xgene-device-clock"; 201 compatible = "apm,xgene-device-clock";
192 #clock-cells = <1>; 202 #clock-cells = <1>;
@@ -632,27 +642,45 @@
632 }; 642 };
633 643
634 sgenet0: ethernet@1f210000 { 644 sgenet0: ethernet@1f210000 {
635 compatible = "apm,xgene-enet"; 645 compatible = "apm,xgene1-sgenet";
636 status = "disabled"; 646 status = "disabled";
637 reg = <0x0 0x1f210000 0x0 0xd100>, 647 reg = <0x0 0x1f210000 0x0 0xd100>,
638 <0x0 0x1f200000 0x0 0Xc300>, 648 <0x0 0x1f200000 0x0 0Xc300>,
639 <0x0 0x1B000000 0x0 0X200>; 649 <0x0 0x1B000000 0x0 0X200>;
640 reg-names = "enet_csr", "ring_csr", "ring_cmd"; 650 reg-names = "enet_csr", "ring_csr", "ring_cmd";
641 interrupts = <0x0 0xA0 0x4>; 651 interrupts = <0x0 0xA0 0x4>,
652 <0x0 0xA1 0x4>;
642 dma-coherent; 653 dma-coherent;
643 clocks = <&sge0clk 0>; 654 clocks = <&sge0clk 0>;
644 local-mac-address = [00 00 00 00 00 00]; 655 local-mac-address = [00 00 00 00 00 00];
645 phy-connection-type = "sgmii"; 656 phy-connection-type = "sgmii";
646 }; 657 };
647 658
659 sgenet1: ethernet@1f210030 {
660 compatible = "apm,xgene1-sgenet";
661 status = "disabled";
662 reg = <0x0 0x1f210030 0x0 0xd100>,
663 <0x0 0x1f200000 0x0 0Xc300>,
664 <0x0 0x1B000000 0x0 0X8000>;
665 reg-names = "enet_csr", "ring_csr", "ring_cmd";
666 interrupts = <0x0 0xAC 0x4>,
667 <0x0 0xAD 0x4>;
668 port-id = <1>;
669 dma-coherent;
670 clocks = <&sge1clk 0>;
671 local-mac-address = [00 00 00 00 00 00];
672 phy-connection-type = "sgmii";
673 };
674
648 xgenet: ethernet@1f610000 { 675 xgenet: ethernet@1f610000 {
649 compatible = "apm,xgene-enet"; 676 compatible = "apm,xgene1-xgenet";
650 status = "disabled"; 677 status = "disabled";
651 reg = <0x0 0x1f610000 0x0 0xd100>, 678 reg = <0x0 0x1f610000 0x0 0xd100>,
652 <0x0 0x1f600000 0x0 0Xc300>, 679 <0x0 0x1f600000 0x0 0Xc300>,
653 <0x0 0x18000000 0x0 0X200>; 680 <0x0 0x18000000 0x0 0X200>;
654 reg-names = "enet_csr", "ring_csr", "ring_cmd"; 681 reg-names = "enet_csr", "ring_csr", "ring_cmd";
655 interrupts = <0x0 0x60 0x4>; 682 interrupts = <0x0 0x60 0x4>,
683 <0x0 0x61 0x4>;
656 dma-coherent; 684 dma-coherent;
657 clocks = <&xge0clk 0>; 685 clocks = <&xge0clk 0>;
658 /* mac address will be overwritten by the bootloader */ 686 /* mac address will be overwritten by the bootloader */
diff --git a/arch/arm64/boot/dts/arm/foundation-v8.dts b/arch/arm64/boot/dts/arm/foundation-v8.dts
index 27f32962e55c..4eac8dcea423 100644
--- a/arch/arm64/boot/dts/arm/foundation-v8.dts
+++ b/arch/arm64/boot/dts/arm/foundation-v8.dts
@@ -34,6 +34,7 @@
34 reg = <0x0 0x0>; 34 reg = <0x0 0x0>;
35 enable-method = "spin-table"; 35 enable-method = "spin-table";
36 cpu-release-addr = <0x0 0x8000fff8>; 36 cpu-release-addr = <0x0 0x8000fff8>;
37 next-level-cache = <&L2_0>;
37 }; 38 };
38 cpu@1 { 39 cpu@1 {
39 device_type = "cpu"; 40 device_type = "cpu";
@@ -41,6 +42,7 @@
41 reg = <0x0 0x1>; 42 reg = <0x0 0x1>;
42 enable-method = "spin-table"; 43 enable-method = "spin-table";
43 cpu-release-addr = <0x0 0x8000fff8>; 44 cpu-release-addr = <0x0 0x8000fff8>;
45 next-level-cache = <&L2_0>;
44 }; 46 };
45 cpu@2 { 47 cpu@2 {
46 device_type = "cpu"; 48 device_type = "cpu";
@@ -48,6 +50,7 @@
48 reg = <0x0 0x2>; 50 reg = <0x0 0x2>;
49 enable-method = "spin-table"; 51 enable-method = "spin-table";
50 cpu-release-addr = <0x0 0x8000fff8>; 52 cpu-release-addr = <0x0 0x8000fff8>;
53 next-level-cache = <&L2_0>;
51 }; 54 };
52 cpu@3 { 55 cpu@3 {
53 device_type = "cpu"; 56 device_type = "cpu";
@@ -55,6 +58,11 @@
55 reg = <0x0 0x3>; 58 reg = <0x0 0x3>;
56 enable-method = "spin-table"; 59 enable-method = "spin-table";
57 cpu-release-addr = <0x0 0x8000fff8>; 60 cpu-release-addr = <0x0 0x8000fff8>;
61 next-level-cache = <&L2_0>;
62 };
63
64 L2_0: l2-cache0 {
65 compatible = "cache";
58 }; 66 };
59 }; 67 };
60 68
diff --git a/arch/arm64/boot/dts/arm/juno-clocks.dtsi b/arch/arm64/boot/dts/arm/juno-clocks.dtsi
index ea2b5666a16f..c9b89efe0f56 100644
--- a/arch/arm64/boot/dts/arm/juno-clocks.dtsi
+++ b/arch/arm64/boot/dts/arm/juno-clocks.dtsi
@@ -8,7 +8,7 @@
8 */ 8 */
9 9
10 /* SoC fixed clocks */ 10 /* SoC fixed clocks */
11 soc_uartclk: refclk72738khz { 11 soc_uartclk: refclk7273800hz {
12 compatible = "fixed-clock"; 12 compatible = "fixed-clock";
13 #clock-cells = <0>; 13 #clock-cells = <0>;
14 clock-frequency = <7273800>; 14 clock-frequency = <7273800>;
diff --git a/arch/arm64/boot/dts/arm/juno.dts b/arch/arm64/boot/dts/arm/juno.dts
index d429129ecb3d..5e9110a3353d 100644
--- a/arch/arm64/boot/dts/arm/juno.dts
+++ b/arch/arm64/boot/dts/arm/juno.dts
@@ -39,6 +39,7 @@
39 reg = <0x0 0x0>; 39 reg = <0x0 0x0>;
40 device_type = "cpu"; 40 device_type = "cpu";
41 enable-method = "psci"; 41 enable-method = "psci";
42 next-level-cache = <&A57_L2>;
42 }; 43 };
43 44
44 A57_1: cpu@1 { 45 A57_1: cpu@1 {
@@ -46,6 +47,7 @@
46 reg = <0x0 0x1>; 47 reg = <0x0 0x1>;
47 device_type = "cpu"; 48 device_type = "cpu";
48 enable-method = "psci"; 49 enable-method = "psci";
50 next-level-cache = <&A57_L2>;
49 }; 51 };
50 52
51 A53_0: cpu@100 { 53 A53_0: cpu@100 {
@@ -53,6 +55,7 @@
53 reg = <0x0 0x100>; 55 reg = <0x0 0x100>;
54 device_type = "cpu"; 56 device_type = "cpu";
55 enable-method = "psci"; 57 enable-method = "psci";
58 next-level-cache = <&A53_L2>;
56 }; 59 };
57 60
58 A53_1: cpu@101 { 61 A53_1: cpu@101 {
@@ -60,6 +63,7 @@
60 reg = <0x0 0x101>; 63 reg = <0x0 0x101>;
61 device_type = "cpu"; 64 device_type = "cpu";
62 enable-method = "psci"; 65 enable-method = "psci";
66 next-level-cache = <&A53_L2>;
63 }; 67 };
64 68
65 A53_2: cpu@102 { 69 A53_2: cpu@102 {
@@ -67,6 +71,7 @@
67 reg = <0x0 0x102>; 71 reg = <0x0 0x102>;
68 device_type = "cpu"; 72 device_type = "cpu";
69 enable-method = "psci"; 73 enable-method = "psci";
74 next-level-cache = <&A53_L2>;
70 }; 75 };
71 76
72 A53_3: cpu@103 { 77 A53_3: cpu@103 {
@@ -74,6 +79,15 @@
74 reg = <0x0 0x103>; 79 reg = <0x0 0x103>;
75 device_type = "cpu"; 80 device_type = "cpu";
76 enable-method = "psci"; 81 enable-method = "psci";
82 next-level-cache = <&A53_L2>;
83 };
84
85 A57_L2: l2-cache0 {
86 compatible = "cache";
87 };
88
89 A53_L2: l2-cache1 {
90 compatible = "cache";
77 }; 91 };
78 }; 92 };
79 93
@@ -106,12 +120,18 @@
106 120
107 pmu { 121 pmu {
108 compatible = "arm,armv8-pmuv3"; 122 compatible = "arm,armv8-pmuv3";
109 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 123 interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>,
124 <GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>,
125 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
110 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 126 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
111 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 127 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
112 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 128 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
113 <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>, 129 interrupt-affinity = <&A57_0>,
114 <GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>; 130 <&A57_1>,
131 <&A53_0>,
132 <&A53_1>,
133 <&A53_2>,
134 <&A53_3>;
115 }; 135 };
116 136
117 /include/ "juno-clocks.dtsi" 137 /include/ "juno-clocks.dtsi"
diff --git a/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts b/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts
index efc59b3baf63..20addabbd127 100644
--- a/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts
+++ b/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts
@@ -37,6 +37,7 @@
37 reg = <0x0 0x0>; 37 reg = <0x0 0x0>;
38 enable-method = "spin-table"; 38 enable-method = "spin-table";
39 cpu-release-addr = <0x0 0x8000fff8>; 39 cpu-release-addr = <0x0 0x8000fff8>;
40 next-level-cache = <&L2_0>;
40 }; 41 };
41 cpu@1 { 42 cpu@1 {
42 device_type = "cpu"; 43 device_type = "cpu";
@@ -44,6 +45,7 @@
44 reg = <0x0 0x1>; 45 reg = <0x0 0x1>;
45 enable-method = "spin-table"; 46 enable-method = "spin-table";
46 cpu-release-addr = <0x0 0x8000fff8>; 47 cpu-release-addr = <0x0 0x8000fff8>;
48 next-level-cache = <&L2_0>;
47 }; 49 };
48 cpu@2 { 50 cpu@2 {
49 device_type = "cpu"; 51 device_type = "cpu";
@@ -51,6 +53,7 @@
51 reg = <0x0 0x2>; 53 reg = <0x0 0x2>;
52 enable-method = "spin-table"; 54 enable-method = "spin-table";
53 cpu-release-addr = <0x0 0x8000fff8>; 55 cpu-release-addr = <0x0 0x8000fff8>;
56 next-level-cache = <&L2_0>;
54 }; 57 };
55 cpu@3 { 58 cpu@3 {
56 device_type = "cpu"; 59 device_type = "cpu";
@@ -58,6 +61,11 @@
58 reg = <0x0 0x3>; 61 reg = <0x0 0x3>;
59 enable-method = "spin-table"; 62 enable-method = "spin-table";
60 cpu-release-addr = <0x0 0x8000fff8>; 63 cpu-release-addr = <0x0 0x8000fff8>;
64 next-level-cache = <&L2_0>;
65 };
66
67 L2_0: l2-cache0 {
68 compatible = "cache";
61 }; 69 };
62 }; 70 };
63 71
diff --git a/arch/arm64/boot/dts/mediatek/mt8173-pinfunc.h b/arch/arm64/boot/dts/mediatek/mt8173-pinfunc.h
new file mode 100644
index 000000000000..d2f3809af70e
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8173-pinfunc.h
@@ -0,0 +1,682 @@
1/*
2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#ifndef __DTS_MT8173_PINFUNC_H
16#define __DTS_MT8173_PINFUNC_H
17
18#include <dt-bindings/pinctrl/mt65xx.h>
19
20#define MT8173_PIN_0_EINT0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0)
21#define MT8173_PIN_0_EINT0__FUNC_IRDA_PDN (MTK_PIN_NO(0) | 1)
22#define MT8173_PIN_0_EINT0__FUNC_I2S1_WS (MTK_PIN_NO(0) | 2)
23#define MT8173_PIN_0_EINT0__FUNC_AUD_SPDIF (MTK_PIN_NO(0) | 3)
24#define MT8173_PIN_0_EINT0__FUNC_UTXD0 (MTK_PIN_NO(0) | 4)
25#define MT8173_PIN_0_EINT0__FUNC_DBG_MON_A_20_ (MTK_PIN_NO(0) | 7)
26
27#define MT8173_PIN_1_EINT1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0)
28#define MT8173_PIN_1_EINT1__FUNC_IRDA_RXD (MTK_PIN_NO(1) | 1)
29#define MT8173_PIN_1_EINT1__FUNC_I2S1_BCK (MTK_PIN_NO(1) | 2)
30#define MT8173_PIN_1_EINT1__FUNC_SDA5 (MTK_PIN_NO(1) | 3)
31#define MT8173_PIN_1_EINT1__FUNC_URXD0 (MTK_PIN_NO(1) | 4)
32#define MT8173_PIN_1_EINT1__FUNC_DBG_MON_A_21_ (MTK_PIN_NO(1) | 7)
33
34#define MT8173_PIN_2_EINT2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0)
35#define MT8173_PIN_2_EINT2__FUNC_IRDA_TXD (MTK_PIN_NO(2) | 1)
36#define MT8173_PIN_2_EINT2__FUNC_I2S1_MCK (MTK_PIN_NO(2) | 2)
37#define MT8173_PIN_2_EINT2__FUNC_SCL5 (MTK_PIN_NO(2) | 3)
38#define MT8173_PIN_2_EINT2__FUNC_UTXD3 (MTK_PIN_NO(2) | 4)
39#define MT8173_PIN_2_EINT2__FUNC_DBG_MON_A_22_ (MTK_PIN_NO(2) | 7)
40
41#define MT8173_PIN_3_EINT3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0)
42#define MT8173_PIN_3_EINT3__FUNC_DSI1_TE (MTK_PIN_NO(3) | 1)
43#define MT8173_PIN_3_EINT3__FUNC_I2S1_DO_1 (MTK_PIN_NO(3) | 2)
44#define MT8173_PIN_3_EINT3__FUNC_SDA3 (MTK_PIN_NO(3) | 3)
45#define MT8173_PIN_3_EINT3__FUNC_URXD3 (MTK_PIN_NO(3) | 4)
46#define MT8173_PIN_3_EINT3__FUNC_DBG_MON_A_23_ (MTK_PIN_NO(3) | 7)
47
48#define MT8173_PIN_4_EINT4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0)
49#define MT8173_PIN_4_EINT4__FUNC_DISP_PWM1 (MTK_PIN_NO(4) | 1)
50#define MT8173_PIN_4_EINT4__FUNC_I2S1_DO_2 (MTK_PIN_NO(4) | 2)
51#define MT8173_PIN_4_EINT4__FUNC_SCL3 (MTK_PIN_NO(4) | 3)
52#define MT8173_PIN_4_EINT4__FUNC_UCTS3 (MTK_PIN_NO(4) | 4)
53#define MT8173_PIN_4_EINT4__FUNC_SFWP_B (MTK_PIN_NO(4) | 6)
54
55#define MT8173_PIN_5_EINT5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0)
56#define MT8173_PIN_5_EINT5__FUNC_PCM1_CLK (MTK_PIN_NO(5) | 1)
57#define MT8173_PIN_5_EINT5__FUNC_I2S2_WS (MTK_PIN_NO(5) | 2)
58#define MT8173_PIN_5_EINT5__FUNC_SPI_CK_3_ (MTK_PIN_NO(5) | 3)
59#define MT8173_PIN_5_EINT5__FUNC_URTS3 (MTK_PIN_NO(5) | 4)
60#define MT8173_PIN_5_EINT5__FUNC_AP_MD32_JTAG_TMS (MTK_PIN_NO(5) | 5)
61#define MT8173_PIN_5_EINT5__FUNC_SFOUT (MTK_PIN_NO(5) | 6)
62
63#define MT8173_PIN_6_EINT6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0)
64#define MT8173_PIN_6_EINT6__FUNC_PCM1_SYNC (MTK_PIN_NO(6) | 1)
65#define MT8173_PIN_6_EINT6__FUNC_I2S2_BCK (MTK_PIN_NO(6) | 2)
66#define MT8173_PIN_6_EINT6__FUNC_SPI_MI_3_ (MTK_PIN_NO(6) | 3)
67#define MT8173_PIN_6_EINT6__FUNC_AP_MD32_JTAG_TCK (MTK_PIN_NO(6) | 5)
68#define MT8173_PIN_6_EINT6__FUNC_SFCS0 (MTK_PIN_NO(6) | 6)
69
70#define MT8173_PIN_7_EINT7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0)
71#define MT8173_PIN_7_EINT7__FUNC_PCM1_DI (MTK_PIN_NO(7) | 1)
72#define MT8173_PIN_7_EINT7__FUNC_I2S2_DI_1 (MTK_PIN_NO(7) | 2)
73#define MT8173_PIN_7_EINT7__FUNC_SPI_MO_3_ (MTK_PIN_NO(7) | 3)
74#define MT8173_PIN_7_EINT7__FUNC_AP_MD32_JTAG_TDI (MTK_PIN_NO(7) | 5)
75#define MT8173_PIN_7_EINT7__FUNC_SFHOLD (MTK_PIN_NO(7) | 6)
76
77#define MT8173_PIN_8_EINT8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0)
78#define MT8173_PIN_8_EINT8__FUNC_PCM1_DO (MTK_PIN_NO(8) | 1)
79#define MT8173_PIN_8_EINT8__FUNC_I2S2_DI_2 (MTK_PIN_NO(8) | 2)
80#define MT8173_PIN_8_EINT8__FUNC_SPI_CS_3_ (MTK_PIN_NO(8) | 3)
81#define MT8173_PIN_8_EINT8__FUNC_AUD_SPDIF (MTK_PIN_NO(8) | 4)
82#define MT8173_PIN_8_EINT8__FUNC_AP_MD32_JTAG_TDO (MTK_PIN_NO(8) | 5)
83#define MT8173_PIN_8_EINT8__FUNC_SFIN (MTK_PIN_NO(8) | 6)
84
85#define MT8173_PIN_9_EINT9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0)
86#define MT8173_PIN_9_EINT9__FUNC_USB_DRVVBUS_P0 (MTK_PIN_NO(9) | 1)
87#define MT8173_PIN_9_EINT9__FUNC_I2S2_MCK (MTK_PIN_NO(9) | 2)
88#define MT8173_PIN_9_EINT9__FUNC_USB_DRVVBUS_P1 (MTK_PIN_NO(9) | 4)
89#define MT8173_PIN_9_EINT9__FUNC_AP_MD32_JTAG_TRST (MTK_PIN_NO(9) | 5)
90#define MT8173_PIN_9_EINT9__FUNC_SFCK (MTK_PIN_NO(9) | 6)
91
92#define MT8173_PIN_10_EINT10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0)
93#define MT8173_PIN_10_EINT10__FUNC_CLKM0 (MTK_PIN_NO(10) | 1)
94#define MT8173_PIN_10_EINT10__FUNC_DSI1_TE (MTK_PIN_NO(10) | 2)
95#define MT8173_PIN_10_EINT10__FUNC_DISP_PWM1 (MTK_PIN_NO(10) | 3)
96#define MT8173_PIN_10_EINT10__FUNC_PWM4 (MTK_PIN_NO(10) | 4)
97#define MT8173_PIN_10_EINT10__FUNC_IRDA_RXD (MTK_PIN_NO(10) | 5)
98
99#define MT8173_PIN_11_EINT11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0)
100#define MT8173_PIN_11_EINT11__FUNC_CLKM1 (MTK_PIN_NO(11) | 1)
101#define MT8173_PIN_11_EINT11__FUNC_I2S3_WS (MTK_PIN_NO(11) | 2)
102#define MT8173_PIN_11_EINT11__FUNC_USB_DRVVBUS_P0 (MTK_PIN_NO(11) | 3)
103#define MT8173_PIN_11_EINT11__FUNC_PWM5 (MTK_PIN_NO(11) | 4)
104#define MT8173_PIN_11_EINT11__FUNC_IRDA_TXD (MTK_PIN_NO(11) | 5)
105#define MT8173_PIN_11_EINT11__FUNC_USB_DRVVBUS_P1 (MTK_PIN_NO(11) | 6)
106#define MT8173_PIN_11_EINT11__FUNC_DBG_MON_B_30_ (MTK_PIN_NO(11) | 7)
107
108#define MT8173_PIN_12_EINT12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0)
109#define MT8173_PIN_12_EINT12__FUNC_CLKM2 (MTK_PIN_NO(12) | 1)
110#define MT8173_PIN_12_EINT12__FUNC_I2S3_BCK (MTK_PIN_NO(12) | 2)
111#define MT8173_PIN_12_EINT12__FUNC_SRCLKENA0 (MTK_PIN_NO(12) | 3)
112#define MT8173_PIN_12_EINT12__FUNC_I2S2_WS (MTK_PIN_NO(12) | 5)
113#define MT8173_PIN_12_EINT12__FUNC_DBG_MON_B_32_ (MTK_PIN_NO(12) | 7)
114
115#define MT8173_PIN_13_EINT13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0)
116#define MT8173_PIN_13_EINT13__FUNC_CLKM3 (MTK_PIN_NO(13) | 1)
117#define MT8173_PIN_13_EINT13__FUNC_I2S3_MCK (MTK_PIN_NO(13) | 2)
118#define MT8173_PIN_13_EINT13__FUNC_SRCLKENA0 (MTK_PIN_NO(13) | 3)
119#define MT8173_PIN_13_EINT13__FUNC_I2S2_BCK (MTK_PIN_NO(13) | 5)
120#define MT8173_PIN_13_EINT13__FUNC_DBG_MON_A_32_ (MTK_PIN_NO(13) | 7)
121
122#define MT8173_PIN_14_EINT14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0)
123#define MT8173_PIN_14_EINT14__FUNC_CMDAT0 (MTK_PIN_NO(14) | 1)
124#define MT8173_PIN_14_EINT14__FUNC_CMCSD0 (MTK_PIN_NO(14) | 2)
125#define MT8173_PIN_14_EINT14__FUNC_CLKM2 (MTK_PIN_NO(14) | 4)
126#define MT8173_PIN_14_EINT14__FUNC_DBG_MON_B_6_ (MTK_PIN_NO(14) | 7)
127
128#define MT8173_PIN_15_EINT15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0)
129#define MT8173_PIN_15_EINT15__FUNC_CMDAT1 (MTK_PIN_NO(15) | 1)
130#define MT8173_PIN_15_EINT15__FUNC_CMCSD1 (MTK_PIN_NO(15) | 2)
131#define MT8173_PIN_15_EINT15__FUNC_CMFLASH (MTK_PIN_NO(15) | 3)
132#define MT8173_PIN_15_EINT15__FUNC_CLKM3 (MTK_PIN_NO(15) | 4)
133#define MT8173_PIN_15_EINT15__FUNC_DBG_MON_B_29_ (MTK_PIN_NO(15) | 7)
134
135#define MT8173_PIN_16_IDDIG__FUNC_GPIO16 (MTK_PIN_NO(16) | 0)
136#define MT8173_PIN_16_IDDIG__FUNC_IDDIG (MTK_PIN_NO(16) | 1)
137#define MT8173_PIN_16_IDDIG__FUNC_CMFLASH (MTK_PIN_NO(16) | 2)
138#define MT8173_PIN_16_IDDIG__FUNC_PWM5 (MTK_PIN_NO(16) | 4)
139
140#define MT8173_PIN_17_WATCHDOG__FUNC_GPIO17 (MTK_PIN_NO(17) | 0)
141#define MT8173_PIN_17_WATCHDOG__FUNC_WATCHDOG_AO (MTK_PIN_NO(17) | 1)
142
143#define MT8173_PIN_18_CEC__FUNC_GPIO18 (MTK_PIN_NO(18) | 0)
144#define MT8173_PIN_18_CEC__FUNC_CEC (MTK_PIN_NO(18) | 1)
145
146#define MT8173_PIN_19_HDMISCK__FUNC_GPIO19 (MTK_PIN_NO(19) | 0)
147#define MT8173_PIN_19_HDMISCK__FUNC_HDMISCK (MTK_PIN_NO(19) | 1)
148#define MT8173_PIN_19_HDMISCK__FUNC_HDCP_SCL (MTK_PIN_NO(19) | 2)
149
150#define MT8173_PIN_20_HDMISD__FUNC_GPIO20 (MTK_PIN_NO(20) | 0)
151#define MT8173_PIN_20_HDMISD__FUNC_HDMISD (MTK_PIN_NO(20) | 1)
152#define MT8173_PIN_20_HDMISD__FUNC_HDCP_SDA (MTK_PIN_NO(20) | 2)
153
154#define MT8173_PIN_21_HTPLG__FUNC_GPIO21 (MTK_PIN_NO(21) | 0)
155#define MT8173_PIN_21_HTPLG__FUNC_HTPLG (MTK_PIN_NO(21) | 1)
156
157#define MT8173_PIN_22_MSDC3_DAT0__FUNC_GPIO22 (MTK_PIN_NO(22) | 0)
158#define MT8173_PIN_22_MSDC3_DAT0__FUNC_MSDC3_DAT0 (MTK_PIN_NO(22) | 1)
159
160#define MT8173_PIN_23_MSDC3_DAT1__FUNC_GPIO23 (MTK_PIN_NO(23) | 0)
161#define MT8173_PIN_23_MSDC3_DAT1__FUNC_MSDC3_DAT1 (MTK_PIN_NO(23) | 1)
162
163#define MT8173_PIN_24_MSDC3_DAT2__FUNC_GPIO24 (MTK_PIN_NO(24) | 0)
164#define MT8173_PIN_24_MSDC3_DAT2__FUNC_MSDC3_DAT2 (MTK_PIN_NO(24) | 1)
165
166#define MT8173_PIN_25_MSDC3_DAT3__FUNC_GPIO25 (MTK_PIN_NO(25) | 0)
167#define MT8173_PIN_25_MSDC3_DAT3__FUNC_MSDC3_DAT3 (MTK_PIN_NO(25) | 1)
168
169#define MT8173_PIN_26_MSDC3_CLK__FUNC_GPIO26 (MTK_PIN_NO(26) | 0)
170#define MT8173_PIN_26_MSDC3_CLK__FUNC_MSDC3_CLK (MTK_PIN_NO(26) | 1)
171
172#define MT8173_PIN_27_MSDC3_CMD__FUNC_GPIO27 (MTK_PIN_NO(27) | 0)
173#define MT8173_PIN_27_MSDC3_CMD__FUNC_MSDC3_CMD (MTK_PIN_NO(27) | 1)
174
175#define MT8173_PIN_28_MSDC3_DSL__FUNC_GPIO28 (MTK_PIN_NO(28) | 0)
176#define MT8173_PIN_28_MSDC3_DSL__FUNC_MSDC3_DSL (MTK_PIN_NO(28) | 1)
177
178#define MT8173_PIN_29_UCTS2__FUNC_GPIO29 (MTK_PIN_NO(29) | 0)
179#define MT8173_PIN_29_UCTS2__FUNC_UCTS2 (MTK_PIN_NO(29) | 1)
180
181#define MT8173_PIN_30_URTS2__FUNC_GPIO30 (MTK_PIN_NO(30) | 0)
182#define MT8173_PIN_30_URTS2__FUNC_URTS2 (MTK_PIN_NO(30) | 1)
183
184#define MT8173_PIN_31_URXD2__FUNC_GPIO31 (MTK_PIN_NO(31) | 0)
185#define MT8173_PIN_31_URXD2__FUNC_URXD2 (MTK_PIN_NO(31) | 1)
186#define MT8173_PIN_31_URXD2__FUNC_UTXD2 (MTK_PIN_NO(31) | 2)
187
188#define MT8173_PIN_32_UTXD2__FUNC_GPIO32 (MTK_PIN_NO(32) | 0)
189#define MT8173_PIN_32_UTXD2__FUNC_UTXD2 (MTK_PIN_NO(32) | 1)
190#define MT8173_PIN_32_UTXD2__FUNC_URXD2 (MTK_PIN_NO(32) | 2)
191
192#define MT8173_PIN_33_DAICLK__FUNC_GPIO33 (MTK_PIN_NO(33) | 0)
193#define MT8173_PIN_33_DAICLK__FUNC_MRG_CLK (MTK_PIN_NO(33) | 1)
194#define MT8173_PIN_33_DAICLK__FUNC_PCM0_CLK (MTK_PIN_NO(33) | 2)
195
196#define MT8173_PIN_34_DAIPCMIN__FUNC_GPIO34 (MTK_PIN_NO(34) | 0)
197#define MT8173_PIN_34_DAIPCMIN__FUNC_MRG_DI (MTK_PIN_NO(34) | 1)
198#define MT8173_PIN_34_DAIPCMIN__FUNC_PCM0_DI (MTK_PIN_NO(34) | 2)
199
200#define MT8173_PIN_35_DAIPCMOUT__FUNC_GPIO35 (MTK_PIN_NO(35) | 0)
201#define MT8173_PIN_35_DAIPCMOUT__FUNC_MRG_DO (MTK_PIN_NO(35) | 1)
202#define MT8173_PIN_35_DAIPCMOUT__FUNC_PCM0_DO (MTK_PIN_NO(35) | 2)
203
204#define MT8173_PIN_36_DAISYNC__FUNC_GPIO36 (MTK_PIN_NO(36) | 0)
205#define MT8173_PIN_36_DAISYNC__FUNC_MRG_SYNC (MTK_PIN_NO(36) | 1)
206#define MT8173_PIN_36_DAISYNC__FUNC_PCM0_SYNC (MTK_PIN_NO(36) | 2)
207
208#define MT8173_PIN_37_EINT16__FUNC_GPIO37 (MTK_PIN_NO(37) | 0)
209#define MT8173_PIN_37_EINT16__FUNC_USB_DRVVBUS_P0 (MTK_PIN_NO(37) | 1)
210#define MT8173_PIN_37_EINT16__FUNC_USB_DRVVBUS_P1 (MTK_PIN_NO(37) | 2)
211#define MT8173_PIN_37_EINT16__FUNC_PWM0 (MTK_PIN_NO(37) | 3)
212#define MT8173_PIN_37_EINT16__FUNC_PWM1 (MTK_PIN_NO(37) | 4)
213#define MT8173_PIN_37_EINT16__FUNC_PWM2 (MTK_PIN_NO(37) | 5)
214#define MT8173_PIN_37_EINT16__FUNC_CLKM0 (MTK_PIN_NO(37) | 6)
215
216#define MT8173_PIN_38_CONN_RST__FUNC_GPIO38 (MTK_PIN_NO(38) | 0)
217#define MT8173_PIN_38_CONN_RST__FUNC_USB_DRVVBUS_P0 (MTK_PIN_NO(38) | 1)
218#define MT8173_PIN_38_CONN_RST__FUNC_USB_DRVVBUS_P1 (MTK_PIN_NO(38) | 2)
219#define MT8173_PIN_38_CONN_RST__FUNC_CLKM1 (MTK_PIN_NO(38) | 6)
220
221#define MT8173_PIN_39_CM2MCLK__FUNC_GPIO39 (MTK_PIN_NO(39) | 0)
222#define MT8173_PIN_39_CM2MCLK__FUNC_CM2MCLK (MTK_PIN_NO(39) | 1)
223#define MT8173_PIN_39_CM2MCLK__FUNC_CMCSD0 (MTK_PIN_NO(39) | 2)
224#define MT8173_PIN_39_CM2MCLK__FUNC_DBG_MON_A_17_ (MTK_PIN_NO(39) | 7)
225
226#define MT8173_PIN_40_CMPCLK__FUNC_GPIO40 (MTK_PIN_NO(40) | 0)
227#define MT8173_PIN_40_CMPCLK__FUNC_CMPCLK (MTK_PIN_NO(40) | 1)
228#define MT8173_PIN_40_CMPCLK__FUNC_CMCSK (MTK_PIN_NO(40) | 2)
229#define MT8173_PIN_40_CMPCLK__FUNC_CMCSD2 (MTK_PIN_NO(40) | 3)
230#define MT8173_PIN_40_CMPCLK__FUNC_DBG_MON_A_18_ (MTK_PIN_NO(40) | 7)
231
232#define MT8173_PIN_41_CMMCLK__FUNC_GPIO41 (MTK_PIN_NO(41) | 0)
233#define MT8173_PIN_41_CMMCLK__FUNC_CMMCLK (MTK_PIN_NO(41) | 1)
234#define MT8173_PIN_41_CMMCLK__FUNC_DBG_MON_A_19_ (MTK_PIN_NO(41) | 7)
235
236#define MT8173_PIN_42_DSI_TE__FUNC_GPIO42 (MTK_PIN_NO(42) | 0)
237#define MT8173_PIN_42_DSI_TE__FUNC_DSI_TE (MTK_PIN_NO(42) | 1)
238
239#define MT8173_PIN_43_SDA2__FUNC_GPIO43 (MTK_PIN_NO(43) | 0)
240#define MT8173_PIN_43_SDA2__FUNC_SDA2 (MTK_PIN_NO(43) | 1)
241
242#define MT8173_PIN_44_SCL2__FUNC_GPIO44 (MTK_PIN_NO(44) | 0)
243#define MT8173_PIN_44_SCL2__FUNC_SCL2 (MTK_PIN_NO(44) | 1)
244
245#define MT8173_PIN_45_SDA0__FUNC_GPIO45 (MTK_PIN_NO(45) | 0)
246#define MT8173_PIN_45_SDA0__FUNC_SDA0 (MTK_PIN_NO(45) | 1)
247
248#define MT8173_PIN_46_SCL0__FUNC_GPIO46 (MTK_PIN_NO(46) | 0)
249#define MT8173_PIN_46_SCL0__FUNC_SCL0 (MTK_PIN_NO(46) | 1)
250
251#define MT8173_PIN_47_RDN0_A__FUNC_GPIO47 (MTK_PIN_NO(47) | 0)
252#define MT8173_PIN_47_RDN0_A__FUNC_CMDAT2 (MTK_PIN_NO(47) | 1)
253
254#define MT8173_PIN_48_RDP0_A__FUNC_GPIO48 (MTK_PIN_NO(48) | 0)
255#define MT8173_PIN_48_RDP0_A__FUNC_CMDAT3 (MTK_PIN_NO(48) | 1)
256
257#define MT8173_PIN_49_RDN1_A__FUNC_GPIO49 (MTK_PIN_NO(49) | 0)
258#define MT8173_PIN_49_RDN1_A__FUNC_CMDAT4 (MTK_PIN_NO(49) | 1)
259
260#define MT8173_PIN_50_RDP1_A__FUNC_GPIO50 (MTK_PIN_NO(50) | 0)
261#define MT8173_PIN_50_RDP1_A__FUNC_CMDAT5 (MTK_PIN_NO(50) | 1)
262
263#define MT8173_PIN_51_RCN_A__FUNC_GPIO51 (MTK_PIN_NO(51) | 0)
264#define MT8173_PIN_51_RCN_A__FUNC_CMDAT6 (MTK_PIN_NO(51) | 1)
265
266#define MT8173_PIN_52_RCP_A__FUNC_GPIO52 (MTK_PIN_NO(52) | 0)
267#define MT8173_PIN_52_RCP_A__FUNC_CMDAT7 (MTK_PIN_NO(52) | 1)
268
269#define MT8173_PIN_53_RDN2_A__FUNC_GPIO53 (MTK_PIN_NO(53) | 0)
270#define MT8173_PIN_53_RDN2_A__FUNC_CMDAT8 (MTK_PIN_NO(53) | 1)
271#define MT8173_PIN_53_RDN2_A__FUNC_CMCSD3 (MTK_PIN_NO(53) | 2)
272
273#define MT8173_PIN_54_RDP2_A__FUNC_GPIO54 (MTK_PIN_NO(54) | 0)
274#define MT8173_PIN_54_RDP2_A__FUNC_CMDAT9 (MTK_PIN_NO(54) | 1)
275#define MT8173_PIN_54_RDP2_A__FUNC_CMCSD2 (MTK_PIN_NO(54) | 2)
276
277#define MT8173_PIN_55_RDN3_A__FUNC_GPIO55 (MTK_PIN_NO(55) | 0)
278#define MT8173_PIN_55_RDN3_A__FUNC_CMHSYNC (MTK_PIN_NO(55) | 1)
279#define MT8173_PIN_55_RDN3_A__FUNC_CMCSD1 (MTK_PIN_NO(55) | 2)
280
281#define MT8173_PIN_56_RDP3_A__FUNC_GPIO56 (MTK_PIN_NO(56) | 0)
282#define MT8173_PIN_56_RDP3_A__FUNC_CMVSYNC (MTK_PIN_NO(56) | 1)
283#define MT8173_PIN_56_RDP3_A__FUNC_CMCSD0 (MTK_PIN_NO(56) | 2)
284
285#define MT8173_PIN_57_MSDC0_DAT0__FUNC_GPIO57 (MTK_PIN_NO(57) | 0)
286#define MT8173_PIN_57_MSDC0_DAT0__FUNC_MSDC0_DAT0 (MTK_PIN_NO(57) | 1)
287#define MT8173_PIN_57_MSDC0_DAT0__FUNC_I2S1_WS (MTK_PIN_NO(57) | 2)
288#define MT8173_PIN_57_MSDC0_DAT0__FUNC_DBG_MON_B_7_ (MTK_PIN_NO(57) | 7)
289
290#define MT8173_PIN_58_MSDC0_DAT1__FUNC_GPIO58 (MTK_PIN_NO(58) | 0)
291#define MT8173_PIN_58_MSDC0_DAT1__FUNC_MSDC0_DAT1 (MTK_PIN_NO(58) | 1)
292#define MT8173_PIN_58_MSDC0_DAT1__FUNC_I2S1_BCK (MTK_PIN_NO(58) | 2)
293#define MT8173_PIN_58_MSDC0_DAT1__FUNC_DBG_MON_B_8_ (MTK_PIN_NO(58) | 7)
294
295#define MT8173_PIN_59_MSDC0_DAT2__FUNC_GPIO59 (MTK_PIN_NO(59) | 0)
296#define MT8173_PIN_59_MSDC0_DAT2__FUNC_MSDC0_DAT2 (MTK_PIN_NO(59) | 1)
297#define MT8173_PIN_59_MSDC0_DAT2__FUNC_I2S1_MCK (MTK_PIN_NO(59) | 2)
298#define MT8173_PIN_59_MSDC0_DAT2__FUNC_DBG_MON_B_9_ (MTK_PIN_NO(59) | 7)
299
300#define MT8173_PIN_60_MSDC0_DAT3__FUNC_GPIO60 (MTK_PIN_NO(60) | 0)
301#define MT8173_PIN_60_MSDC0_DAT3__FUNC_MSDC0_DAT3 (MTK_PIN_NO(60) | 1)
302#define MT8173_PIN_60_MSDC0_DAT3__FUNC_I2S1_DO_1 (MTK_PIN_NO(60) | 2)
303#define MT8173_PIN_60_MSDC0_DAT3__FUNC_DBG_MON_B_10_ (MTK_PIN_NO(60) | 7)
304
305#define MT8173_PIN_61_MSDC0_DAT4__FUNC_GPIO61 (MTK_PIN_NO(61) | 0)
306#define MT8173_PIN_61_MSDC0_DAT4__FUNC_MSDC0_DAT4 (MTK_PIN_NO(61) | 1)
307#define MT8173_PIN_61_MSDC0_DAT4__FUNC_I2S1_DO_2 (MTK_PIN_NO(61) | 2)
308#define MT8173_PIN_61_MSDC0_DAT4__FUNC_DBG_MON_B_11_ (MTK_PIN_NO(61) | 7)
309
310#define MT8173_PIN_62_MSDC0_DAT5__FUNC_GPIO62 (MTK_PIN_NO(62) | 0)
311#define MT8173_PIN_62_MSDC0_DAT5__FUNC_MSDC0_DAT5 (MTK_PIN_NO(62) | 1)
312#define MT8173_PIN_62_MSDC0_DAT5__FUNC_I2S2_WS (MTK_PIN_NO(62) | 2)
313#define MT8173_PIN_62_MSDC0_DAT5__FUNC_DBG_MON_B_12_ (MTK_PIN_NO(62) | 7)
314
315#define MT8173_PIN_63_MSDC0_DAT6__FUNC_GPIO63 (MTK_PIN_NO(63) | 0)
316#define MT8173_PIN_63_MSDC0_DAT6__FUNC_MSDC0_DAT6 (MTK_PIN_NO(63) | 1)
317#define MT8173_PIN_63_MSDC0_DAT6__FUNC_I2S2_BCK (MTK_PIN_NO(63) | 2)
318#define MT8173_PIN_63_MSDC0_DAT6__FUNC_DBG_MON_B_13_ (MTK_PIN_NO(63) | 7)
319
320#define MT8173_PIN_64_MSDC0_DAT7__FUNC_GPIO64 (MTK_PIN_NO(64) | 0)
321#define MT8173_PIN_64_MSDC0_DAT7__FUNC_MSDC0_DAT7 (MTK_PIN_NO(64) | 1)
322#define MT8173_PIN_64_MSDC0_DAT7__FUNC_I2S2_DI_1 (MTK_PIN_NO(64) | 2)
323#define MT8173_PIN_64_MSDC0_DAT7__FUNC_DBG_MON_B_14_ (MTK_PIN_NO(64) | 7)
324
325#define MT8173_PIN_65_MSDC0_CLK__FUNC_GPIO65 (MTK_PIN_NO(65) | 0)
326#define MT8173_PIN_65_MSDC0_CLK__FUNC_MSDC0_CLK (MTK_PIN_NO(65) | 1)
327#define MT8173_PIN_65_MSDC0_CLK__FUNC_DBG_MON_B_16_ (MTK_PIN_NO(65) | 7)
328
329#define MT8173_PIN_66_MSDC0_CMD__FUNC_GPIO66 (MTK_PIN_NO(66) | 0)
330#define MT8173_PIN_66_MSDC0_CMD__FUNC_MSDC0_CMD (MTK_PIN_NO(66) | 1)
331#define MT8173_PIN_66_MSDC0_CMD__FUNC_I2S2_DI_2 (MTK_PIN_NO(66) | 2)
332#define MT8173_PIN_66_MSDC0_CMD__FUNC_DBG_MON_B_15_ (MTK_PIN_NO(66) | 7)
333
334#define MT8173_PIN_67_MSDC0_DSL__FUNC_GPIO67 (MTK_PIN_NO(67) | 0)
335#define MT8173_PIN_67_MSDC0_DSL__FUNC_MSDC0_DSL (MTK_PIN_NO(67) | 1)
336#define MT8173_PIN_67_MSDC0_DSL__FUNC_DBG_MON_B_17_ (MTK_PIN_NO(67) | 7)
337
338#define MT8173_PIN_68_MSDC0_RST___FUNC_GPIO68 (MTK_PIN_NO(68) | 0)
339#define MT8173_PIN_68_MSDC0_RST___FUNC_MSDC0_RSTB (MTK_PIN_NO(68) | 1)
340#define MT8173_PIN_68_MSDC0_RST___FUNC_I2S2_MCK (MTK_PIN_NO(68) | 2)
341#define MT8173_PIN_68_MSDC0_RST___FUNC_DBG_MON_B_18_ (MTK_PIN_NO(68) | 7)
342
343#define MT8173_PIN_69_SPI_CK__FUNC_GPIO69 (MTK_PIN_NO(69) | 0)
344#define MT8173_PIN_69_SPI_CK__FUNC_SPI_CK_0_ (MTK_PIN_NO(69) | 1)
345#define MT8173_PIN_69_SPI_CK__FUNC_I2S3_DO_1 (MTK_PIN_NO(69) | 2)
346#define MT8173_PIN_69_SPI_CK__FUNC_PWM0 (MTK_PIN_NO(69) | 3)
347#define MT8173_PIN_69_SPI_CK__FUNC_PWM5 (MTK_PIN_NO(69) | 4)
348#define MT8173_PIN_69_SPI_CK__FUNC_I2S2_MCK (MTK_PIN_NO(69) | 5)
349#define MT8173_PIN_69_SPI_CK__FUNC_DBG_MON_B_19_ (MTK_PIN_NO(69) | 7)
350
351#define MT8173_PIN_70_SPI_MI__FUNC_GPIO70 (MTK_PIN_NO(70) | 0)
352#define MT8173_PIN_70_SPI_MI__FUNC_SPI_MI_0_ (MTK_PIN_NO(70) | 1)
353#define MT8173_PIN_70_SPI_MI__FUNC_I2S3_DO_2 (MTK_PIN_NO(70) | 2)
354#define MT8173_PIN_70_SPI_MI__FUNC_PWM1 (MTK_PIN_NO(70) | 3)
355#define MT8173_PIN_70_SPI_MI__FUNC_SPI_MO_0_ (MTK_PIN_NO(70) | 4)
356#define MT8173_PIN_70_SPI_MI__FUNC_I2S2_DI_1 (MTK_PIN_NO(70) | 5)
357#define MT8173_PIN_70_SPI_MI__FUNC_DSI1_TE (MTK_PIN_NO(70) | 6)
358#define MT8173_PIN_70_SPI_MI__FUNC_DBG_MON_B_20_ (MTK_PIN_NO(70) | 7)
359
360#define MT8173_PIN_71_SPI_MO__FUNC_GPIO71 (MTK_PIN_NO(71) | 0)
361#define MT8173_PIN_71_SPI_MO__FUNC_SPI_MO_0_ (MTK_PIN_NO(71) | 1)
362#define MT8173_PIN_71_SPI_MO__FUNC_I2S3_DO_3 (MTK_PIN_NO(71) | 2)
363#define MT8173_PIN_71_SPI_MO__FUNC_PWM2 (MTK_PIN_NO(71) | 3)
364#define MT8173_PIN_71_SPI_MO__FUNC_SPI_MI_0_ (MTK_PIN_NO(71) | 4)
365#define MT8173_PIN_71_SPI_MO__FUNC_I2S2_DI_2 (MTK_PIN_NO(71) | 5)
366#define MT8173_PIN_71_SPI_MO__FUNC_DBG_MON_B_21_ (MTK_PIN_NO(71) | 7)
367
368#define MT8173_PIN_72_SPI_CS__FUNC_GPIO72 (MTK_PIN_NO(72) | 0)
369#define MT8173_PIN_72_SPI_CS__FUNC_SPI_CS_0_ (MTK_PIN_NO(72) | 1)
370#define MT8173_PIN_72_SPI_CS__FUNC_I2S3_DO_4 (MTK_PIN_NO(72) | 2)
371#define MT8173_PIN_72_SPI_CS__FUNC_PWM3 (MTK_PIN_NO(72) | 3)
372#define MT8173_PIN_72_SPI_CS__FUNC_PWM6 (MTK_PIN_NO(72) | 4)
373#define MT8173_PIN_72_SPI_CS__FUNC_DISP_PWM1 (MTK_PIN_NO(72) | 5)
374#define MT8173_PIN_72_SPI_CS__FUNC_DBG_MON_B_22_ (MTK_PIN_NO(72) | 7)
375
376#define MT8173_PIN_73_MSDC1_DAT0__FUNC_GPIO73 (MTK_PIN_NO(73) | 0)
377#define MT8173_PIN_73_MSDC1_DAT0__FUNC_MSDC1_DAT0 (MTK_PIN_NO(73) | 1)
378#define MT8173_PIN_73_MSDC1_DAT0__FUNC_DBG_MON_B_24_ (MTK_PIN_NO(73) | 7)
379
380#define MT8173_PIN_74_MSDC1_DAT1__FUNC_GPIO74 (MTK_PIN_NO(74) | 0)
381#define MT8173_PIN_74_MSDC1_DAT1__FUNC_MSDC1_DAT1 (MTK_PIN_NO(74) | 1)
382#define MT8173_PIN_74_MSDC1_DAT1__FUNC_DBG_MON_B_25_ (MTK_PIN_NO(74) | 7)
383
384#define MT8173_PIN_75_MSDC1_DAT2__FUNC_GPIO75 (MTK_PIN_NO(75) | 0)
385#define MT8173_PIN_75_MSDC1_DAT2__FUNC_MSDC1_DAT2 (MTK_PIN_NO(75) | 1)
386#define MT8173_PIN_75_MSDC1_DAT2__FUNC_DBG_MON_B_26_ (MTK_PIN_NO(75) | 7)
387
388#define MT8173_PIN_76_MSDC1_DAT3__FUNC_GPIO76 (MTK_PIN_NO(76) | 0)
389#define MT8173_PIN_76_MSDC1_DAT3__FUNC_MSDC1_DAT3 (MTK_PIN_NO(76) | 1)
390#define MT8173_PIN_76_MSDC1_DAT3__FUNC_DBG_MON_B_27_ (MTK_PIN_NO(76) | 7)
391
392#define MT8173_PIN_77_MSDC1_CLK__FUNC_GPIO77 (MTK_PIN_NO(77) | 0)
393#define MT8173_PIN_77_MSDC1_CLK__FUNC_MSDC1_CLK (MTK_PIN_NO(77) | 1)
394#define MT8173_PIN_77_MSDC1_CLK__FUNC_DBG_MON_B_28_ (MTK_PIN_NO(77) | 7)
395
396#define MT8173_PIN_78_MSDC1_CMD__FUNC_GPIO78 (MTK_PIN_NO(78) | 0)
397#define MT8173_PIN_78_MSDC1_CMD__FUNC_MSDC1_CMD (MTK_PIN_NO(78) | 1)
398#define MT8173_PIN_78_MSDC1_CMD__FUNC_DBG_MON_B_23_ (MTK_PIN_NO(78) | 7)
399
400#define MT8173_PIN_79_PWRAP_SPI0_MI__FUNC_GPIO79 (MTK_PIN_NO(79) | 0)
401#define MT8173_PIN_79_PWRAP_SPI0_MI__FUNC_PWRAP_SPIMI (MTK_PIN_NO(79) | 1)
402#define MT8173_PIN_79_PWRAP_SPI0_MI__FUNC_PWRAP_SPIMO (MTK_PIN_NO(79) | 2)
403
404#define MT8173_PIN_80_PWRAP_SPI0_MO__FUNC_GPIO80 (MTK_PIN_NO(80) | 0)
405#define MT8173_PIN_80_PWRAP_SPI0_MO__FUNC_PWRAP_SPIMO (MTK_PIN_NO(80) | 1)
406#define MT8173_PIN_80_PWRAP_SPI0_MO__FUNC_PWRAP_SPIMI (MTK_PIN_NO(80) | 2)
407
408#define MT8173_PIN_81_PWRAP_SPI0_CK__FUNC_GPIO81 (MTK_PIN_NO(81) | 0)
409#define MT8173_PIN_81_PWRAP_SPI0_CK__FUNC_PWRAP_SPICK (MTK_PIN_NO(81) | 1)
410
411#define MT8173_PIN_82_PWRAP_SPI0_CSN__FUNC_GPIO82 (MTK_PIN_NO(82) | 0)
412#define MT8173_PIN_82_PWRAP_SPI0_CSN__FUNC_PWRAP_SPICS (MTK_PIN_NO(82) | 1)
413
414#define MT8173_PIN_83_AUD_CLK_MOSI__FUNC_GPIO83 (MTK_PIN_NO(83) | 0)
415#define MT8173_PIN_83_AUD_CLK_MOSI__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(83) | 1)
416
417#define MT8173_PIN_84_AUD_DAT_MISO__FUNC_GPIO84 (MTK_PIN_NO(84) | 0)
418#define MT8173_PIN_84_AUD_DAT_MISO__FUNC_AUD_DAT_MISO (MTK_PIN_NO(84) | 1)
419#define MT8173_PIN_84_AUD_DAT_MISO__FUNC_AUD_DAT_MOSI (MTK_PIN_NO(84) | 2)
420
421#define MT8173_PIN_85_AUD_DAT_MOSI__FUNC_GPIO85 (MTK_PIN_NO(85) | 0)
422#define MT8173_PIN_85_AUD_DAT_MOSI__FUNC_AUD_DAT_MOSI (MTK_PIN_NO(85) | 1)
423#define MT8173_PIN_85_AUD_DAT_MOSI__FUNC_AUD_DAT_MISO (MTK_PIN_NO(85) | 2)
424
425#define MT8173_PIN_86_RTC32K_CK__FUNC_GPIO86 (MTK_PIN_NO(86) | 0)
426#define MT8173_PIN_86_RTC32K_CK__FUNC_RTC32K_CK (MTK_PIN_NO(86) | 1)
427
428#define MT8173_PIN_87_DISP_PWM0__FUNC_GPIO87 (MTK_PIN_NO(87) | 0)
429#define MT8173_PIN_87_DISP_PWM0__FUNC_DISP_PWM0 (MTK_PIN_NO(87) | 1)
430#define MT8173_PIN_87_DISP_PWM0__FUNC_DISP_PWM1 (MTK_PIN_NO(87) | 2)
431#define MT8173_PIN_87_DISP_PWM0__FUNC_DBG_MON_B_31_ (MTK_PIN_NO(87) | 7)
432
433#define MT8173_PIN_88_SRCLKENAI__FUNC_GPIO88 (MTK_PIN_NO(88) | 0)
434#define MT8173_PIN_88_SRCLKENAI__FUNC_SRCLKENAI (MTK_PIN_NO(88) | 1)
435
436#define MT8173_PIN_89_SRCLKENAI2__FUNC_GPIO89 (MTK_PIN_NO(89) | 0)
437#define MT8173_PIN_89_SRCLKENAI2__FUNC_SRCLKENAI2 (MTK_PIN_NO(89) | 1)
438
439#define MT8173_PIN_90_SRCLKENA0__FUNC_GPIO90 (MTK_PIN_NO(90) | 0)
440#define MT8173_PIN_90_SRCLKENA0__FUNC_SRCLKENA0 (MTK_PIN_NO(90) | 1)
441
442#define MT8173_PIN_91_SRCLKENA1__FUNC_GPIO91 (MTK_PIN_NO(91) | 0)
443#define MT8173_PIN_91_SRCLKENA1__FUNC_SRCLKENA1 (MTK_PIN_NO(91) | 1)
444
445#define MT8173_PIN_92_PCM_CLK__FUNC_GPIO92 (MTK_PIN_NO(92) | 0)
446#define MT8173_PIN_92_PCM_CLK__FUNC_PCM1_CLK (MTK_PIN_NO(92) | 1)
447#define MT8173_PIN_92_PCM_CLK__FUNC_I2S0_BCK (MTK_PIN_NO(92) | 2)
448#define MT8173_PIN_92_PCM_CLK__FUNC_DBG_MON_A_24_ (MTK_PIN_NO(92) | 7)
449
450#define MT8173_PIN_93_PCM_SYNC__FUNC_GPIO93 (MTK_PIN_NO(93) | 0)
451#define MT8173_PIN_93_PCM_SYNC__FUNC_PCM1_SYNC (MTK_PIN_NO(93) | 1)
452#define MT8173_PIN_93_PCM_SYNC__FUNC_I2S0_WS (MTK_PIN_NO(93) | 2)
453#define MT8173_PIN_93_PCM_SYNC__FUNC_DBG_MON_A_25_ (MTK_PIN_NO(93) | 7)
454
455#define MT8173_PIN_94_PCM_RX__FUNC_GPIO94 (MTK_PIN_NO(94) | 0)
456#define MT8173_PIN_94_PCM_RX__FUNC_PCM1_DI (MTK_PIN_NO(94) | 1)
457#define MT8173_PIN_94_PCM_RX__FUNC_I2S0_DI (MTK_PIN_NO(94) | 2)
458#define MT8173_PIN_94_PCM_RX__FUNC_DBG_MON_A_26_ (MTK_PIN_NO(94) | 7)
459
460#define MT8173_PIN_95_PCM_TX__FUNC_GPIO95 (MTK_PIN_NO(95) | 0)
461#define MT8173_PIN_95_PCM_TX__FUNC_PCM1_DO (MTK_PIN_NO(95) | 1)
462#define MT8173_PIN_95_PCM_TX__FUNC_I2S0_DO (MTK_PIN_NO(95) | 2)
463#define MT8173_PIN_95_PCM_TX__FUNC_DBG_MON_A_27_ (MTK_PIN_NO(95) | 7)
464
465#define MT8173_PIN_96_URXD1__FUNC_GPIO96 (MTK_PIN_NO(96) | 0)
466#define MT8173_PIN_96_URXD1__FUNC_URXD1 (MTK_PIN_NO(96) | 1)
467#define MT8173_PIN_96_URXD1__FUNC_UTXD1 (MTK_PIN_NO(96) | 2)
468#define MT8173_PIN_96_URXD1__FUNC_DBG_MON_A_28_ (MTK_PIN_NO(96) | 7)
469
470#define MT8173_PIN_97_UTXD1__FUNC_GPIO97 (MTK_PIN_NO(97) | 0)
471#define MT8173_PIN_97_UTXD1__FUNC_UTXD1 (MTK_PIN_NO(97) | 1)
472#define MT8173_PIN_97_UTXD1__FUNC_URXD1 (MTK_PIN_NO(97) | 2)
473#define MT8173_PIN_97_UTXD1__FUNC_DBG_MON_A_29_ (MTK_PIN_NO(97) | 7)
474
475#define MT8173_PIN_98_URTS1__FUNC_GPIO98 (MTK_PIN_NO(98) | 0)
476#define MT8173_PIN_98_URTS1__FUNC_URTS1 (MTK_PIN_NO(98) | 1)
477#define MT8173_PIN_98_URTS1__FUNC_UCTS1 (MTK_PIN_NO(98) | 2)
478#define MT8173_PIN_98_URTS1__FUNC_DBG_MON_A_30_ (MTK_PIN_NO(98) | 7)
479
480#define MT8173_PIN_99_UCTS1__FUNC_GPIO99 (MTK_PIN_NO(99) | 0)
481#define MT8173_PIN_99_UCTS1__FUNC_UCTS1 (MTK_PIN_NO(99) | 1)
482#define MT8173_PIN_99_UCTS1__FUNC_URTS1 (MTK_PIN_NO(99) | 2)
483#define MT8173_PIN_99_UCTS1__FUNC_DBG_MON_A_31_ (MTK_PIN_NO(99) | 7)
484
485#define MT8173_PIN_100_MSDC2_DAT0__FUNC_GPIO100 (MTK_PIN_NO(100) | 0)
486#define MT8173_PIN_100_MSDC2_DAT0__FUNC_MSDC2_DAT0 (MTK_PIN_NO(100) | 1)
487#define MT8173_PIN_100_MSDC2_DAT0__FUNC_USB_DRVVBUS_P0 (MTK_PIN_NO(100) | 3)
488#define MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5 (MTK_PIN_NO(100) | 4)
489#define MT8173_PIN_100_MSDC2_DAT0__FUNC_USB_DRVVBUS_P1 (MTK_PIN_NO(100) | 5)
490#define MT8173_PIN_100_MSDC2_DAT0__FUNC_DBG_MON_B_0_ (MTK_PIN_NO(100) | 7)
491
492#define MT8173_PIN_101_MSDC2_DAT1__FUNC_GPIO101 (MTK_PIN_NO(101) | 0)
493#define MT8173_PIN_101_MSDC2_DAT1__FUNC_MSDC2_DAT1 (MTK_PIN_NO(101) | 1)
494#define MT8173_PIN_101_MSDC2_DAT1__FUNC_AUD_SPDIF (MTK_PIN_NO(101) | 3)
495#define MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5 (MTK_PIN_NO(101) | 4)
496#define MT8173_PIN_101_MSDC2_DAT1__FUNC_DBG_MON_B_1_ (MTK_PIN_NO(101) | 7)
497
498#define MT8173_PIN_102_MSDC2_DAT2__FUNC_GPIO102 (MTK_PIN_NO(102) | 0)
499#define MT8173_PIN_102_MSDC2_DAT2__FUNC_MSDC2_DAT2 (MTK_PIN_NO(102) | 1)
500#define MT8173_PIN_102_MSDC2_DAT2__FUNC_UTXD0 (MTK_PIN_NO(102) | 3)
501#define MT8173_PIN_102_MSDC2_DAT2__FUNC_PWM0 (MTK_PIN_NO(102) | 5)
502#define MT8173_PIN_102_MSDC2_DAT2__FUNC_SPI_CK_1_ (MTK_PIN_NO(102) | 6)
503#define MT8173_PIN_102_MSDC2_DAT2__FUNC_DBG_MON_B_2_ (MTK_PIN_NO(102) | 7)
504
505#define MT8173_PIN_103_MSDC2_DAT3__FUNC_GPIO103 (MTK_PIN_NO(103) | 0)
506#define MT8173_PIN_103_MSDC2_DAT3__FUNC_MSDC2_DAT3 (MTK_PIN_NO(103) | 1)
507#define MT8173_PIN_103_MSDC2_DAT3__FUNC_URXD0 (MTK_PIN_NO(103) | 3)
508#define MT8173_PIN_103_MSDC2_DAT3__FUNC_PWM1 (MTK_PIN_NO(103) | 5)
509#define MT8173_PIN_103_MSDC2_DAT3__FUNC_SPI_MI_1_ (MTK_PIN_NO(103) | 6)
510#define MT8173_PIN_103_MSDC2_DAT3__FUNC_DBG_MON_B_3_ (MTK_PIN_NO(103) | 7)
511
512#define MT8173_PIN_104_MSDC2_CLK__FUNC_GPIO104 (MTK_PIN_NO(104) | 0)
513#define MT8173_PIN_104_MSDC2_CLK__FUNC_MSDC2_CLK (MTK_PIN_NO(104) | 1)
514#define MT8173_PIN_104_MSDC2_CLK__FUNC_UTXD3 (MTK_PIN_NO(104) | 3)
515#define MT8173_PIN_104_MSDC2_CLK__FUNC_SDA3 (MTK_PIN_NO(104) | 4)
516#define MT8173_PIN_104_MSDC2_CLK__FUNC_PWM2 (MTK_PIN_NO(104) | 5)
517#define MT8173_PIN_104_MSDC2_CLK__FUNC_SPI_MO_1_ (MTK_PIN_NO(104) | 6)
518#define MT8173_PIN_104_MSDC2_CLK__FUNC_DBG_MON_B_4_ (MTK_PIN_NO(104) | 7)
519
520#define MT8173_PIN_105_MSDC2_CMD__FUNC_GPIO105 (MTK_PIN_NO(105) | 0)
521#define MT8173_PIN_105_MSDC2_CMD__FUNC_MSDC2_CMD (MTK_PIN_NO(105) | 1)
522#define MT8173_PIN_105_MSDC2_CMD__FUNC_URXD3 (MTK_PIN_NO(105) | 3)
523#define MT8173_PIN_105_MSDC2_CMD__FUNC_SCL3 (MTK_PIN_NO(105) | 4)
524#define MT8173_PIN_105_MSDC2_CMD__FUNC_PWM3 (MTK_PIN_NO(105) | 5)
525#define MT8173_PIN_105_MSDC2_CMD__FUNC_SPI_CS_1_ (MTK_PIN_NO(105) | 6)
526#define MT8173_PIN_105_MSDC2_CMD__FUNC_DBG_MON_B_5_ (MTK_PIN_NO(105) | 7)
527
528#define MT8173_PIN_106_SDA3__FUNC_GPIO106 (MTK_PIN_NO(106) | 0)
529#define MT8173_PIN_106_SDA3__FUNC_SDA3 (MTK_PIN_NO(106) | 1)
530
531#define MT8173_PIN_107_SCL3__FUNC_GPIO107 (MTK_PIN_NO(107) | 0)
532#define MT8173_PIN_107_SCL3__FUNC_SCL3 (MTK_PIN_NO(107) | 1)
533
534#define MT8173_PIN_108_JTMS__FUNC_GPIO108 (MTK_PIN_NO(108) | 0)
535#define MT8173_PIN_108_JTMS__FUNC_JTMS (MTK_PIN_NO(108) | 1)
536#define MT8173_PIN_108_JTMS__FUNC_MFG_JTAG_TMS (MTK_PIN_NO(108) | 2)
537#define MT8173_PIN_108_JTMS__FUNC_AP_MD32_JTAG_TMS (MTK_PIN_NO(108) | 5)
538#define MT8173_PIN_108_JTMS__FUNC_DFD_TMS (MTK_PIN_NO(108) | 6)
539
540#define MT8173_PIN_109_JTCK__FUNC_GPIO109 (MTK_PIN_NO(109) | 0)
541#define MT8173_PIN_109_JTCK__FUNC_JTCK (MTK_PIN_NO(109) | 1)
542#define MT8173_PIN_109_JTCK__FUNC_MFG_JTAG_TCK (MTK_PIN_NO(109) | 2)
543#define MT8173_PIN_109_JTCK__FUNC_AP_MD32_JTAG_TCK (MTK_PIN_NO(109) | 5)
544#define MT8173_PIN_109_JTCK__FUNC_DFD_TCK (MTK_PIN_NO(109) | 6)
545
546#define MT8173_PIN_110_JTDI__FUNC_GPIO110 (MTK_PIN_NO(110) | 0)
547#define MT8173_PIN_110_JTDI__FUNC_JTDI (MTK_PIN_NO(110) | 1)
548#define MT8173_PIN_110_JTDI__FUNC_MFG_JTAG_TDI (MTK_PIN_NO(110) | 2)
549#define MT8173_PIN_110_JTDI__FUNC_AP_MD32_JTAG_TDI (MTK_PIN_NO(110) | 5)
550#define MT8173_PIN_110_JTDI__FUNC_DFD_TDI (MTK_PIN_NO(110) | 6)
551
552#define MT8173_PIN_111_JTDO__FUNC_GPIO111 (MTK_PIN_NO(111) | 0)
553#define MT8173_PIN_111_JTDO__FUNC_JTDO (MTK_PIN_NO(111) | 1)
554#define MT8173_PIN_111_JTDO__FUNC_MFG_JTAG_TDO (MTK_PIN_NO(111) | 2)
555#define MT8173_PIN_111_JTDO__FUNC_AP_MD32_JTAG_TDO (MTK_PIN_NO(111) | 5)
556#define MT8173_PIN_111_JTDO__FUNC_DFD_TDO (MTK_PIN_NO(111) | 6)
557
558#define MT8173_PIN_112_JTRST_B__FUNC_GPIO112 (MTK_PIN_NO(112) | 0)
559#define MT8173_PIN_112_JTRST_B__FUNC_JTRST_B (MTK_PIN_NO(112) | 1)
560#define MT8173_PIN_112_JTRST_B__FUNC_MFG_JTAG_TRSTN (MTK_PIN_NO(112) | 2)
561#define MT8173_PIN_112_JTRST_B__FUNC_AP_MD32_JTAG_TRST (MTK_PIN_NO(112) | 5)
562#define MT8173_PIN_112_JTRST_B__FUNC_DFD_NTRST (MTK_PIN_NO(112) | 6)
563
564#define MT8173_PIN_113_URXD0__FUNC_GPIO113 (MTK_PIN_NO(113) | 0)
565#define MT8173_PIN_113_URXD0__FUNC_URXD0 (MTK_PIN_NO(113) | 1)
566#define MT8173_PIN_113_URXD0__FUNC_UTXD0 (MTK_PIN_NO(113) | 2)
567#define MT8173_PIN_113_URXD0__FUNC_I2S2_WS (MTK_PIN_NO(113) | 6)
568#define MT8173_PIN_113_URXD0__FUNC_DBG_MON_A_0_ (MTK_PIN_NO(113) | 7)
569
570#define MT8173_PIN_114_UTXD0__FUNC_GPIO114 (MTK_PIN_NO(114) | 0)
571#define MT8173_PIN_114_UTXD0__FUNC_UTXD0 (MTK_PIN_NO(114) | 1)
572#define MT8173_PIN_114_UTXD0__FUNC_URXD0 (MTK_PIN_NO(114) | 2)
573#define MT8173_PIN_114_UTXD0__FUNC_I2S2_BCK (MTK_PIN_NO(114) | 6)
574#define MT8173_PIN_114_UTXD0__FUNC_DBG_MON_A_1_ (MTK_PIN_NO(114) | 7)
575
576#define MT8173_PIN_115_URTS0__FUNC_GPIO115 (MTK_PIN_NO(115) | 0)
577#define MT8173_PIN_115_URTS0__FUNC_URTS0 (MTK_PIN_NO(115) | 1)
578#define MT8173_PIN_115_URTS0__FUNC_UCTS0 (MTK_PIN_NO(115) | 2)
579#define MT8173_PIN_115_URTS0__FUNC_I2S2_MCK (MTK_PIN_NO(115) | 6)
580#define MT8173_PIN_115_URTS0__FUNC_DBG_MON_A_2_ (MTK_PIN_NO(115) | 7)
581
582#define MT8173_PIN_116_UCTS0__FUNC_GPIO116 (MTK_PIN_NO(116) | 0)
583#define MT8173_PIN_116_UCTS0__FUNC_UCTS0 (MTK_PIN_NO(116) | 1)
584#define MT8173_PIN_116_UCTS0__FUNC_URTS0 (MTK_PIN_NO(116) | 2)
585#define MT8173_PIN_116_UCTS0__FUNC_I2S2_DI_1 (MTK_PIN_NO(116) | 6)
586#define MT8173_PIN_116_UCTS0__FUNC_DBG_MON_A_3_ (MTK_PIN_NO(116) | 7)
587
588#define MT8173_PIN_117_URXD3__FUNC_GPIO117 (MTK_PIN_NO(117) | 0)
589#define MT8173_PIN_117_URXD3__FUNC_URXD3 (MTK_PIN_NO(117) | 1)
590#define MT8173_PIN_117_URXD3__FUNC_UTXD3 (MTK_PIN_NO(117) | 2)
591#define MT8173_PIN_117_URXD3__FUNC_DBG_MON_A_9_ (MTK_PIN_NO(117) | 7)
592
593#define MT8173_PIN_118_UTXD3__FUNC_GPIO118 (MTK_PIN_NO(118) | 0)
594#define MT8173_PIN_118_UTXD3__FUNC_UTXD3 (MTK_PIN_NO(118) | 1)
595#define MT8173_PIN_118_UTXD3__FUNC_URXD3 (MTK_PIN_NO(118) | 2)
596#define MT8173_PIN_118_UTXD3__FUNC_DBG_MON_A_10_ (MTK_PIN_NO(118) | 7)
597
598#define MT8173_PIN_119_KPROW0__FUNC_GPIO119 (MTK_PIN_NO(119) | 0)
599#define MT8173_PIN_119_KPROW0__FUNC_KROW0 (MTK_PIN_NO(119) | 1)
600#define MT8173_PIN_119_KPROW0__FUNC_DBG_MON_A_11_ (MTK_PIN_NO(119) | 7)
601
602#define MT8173_PIN_120_KPROW1__FUNC_GPIO120 (MTK_PIN_NO(120) | 0)
603#define MT8173_PIN_120_KPROW1__FUNC_KROW1 (MTK_PIN_NO(120) | 1)
604#define MT8173_PIN_120_KPROW1__FUNC_PWM6 (MTK_PIN_NO(120) | 3)
605#define MT8173_PIN_120_KPROW1__FUNC_DBG_MON_A_12_ (MTK_PIN_NO(120) | 7)
606
607#define MT8173_PIN_121_KPROW2__FUNC_GPIO121 (MTK_PIN_NO(121) | 0)
608#define MT8173_PIN_121_KPROW2__FUNC_KROW2 (MTK_PIN_NO(121) | 1)
609#define MT8173_PIN_121_KPROW2__FUNC_IRDA_PDN (MTK_PIN_NO(121) | 2)
610#define MT8173_PIN_121_KPROW2__FUNC_USB_DRVVBUS_P0 (MTK_PIN_NO(121) | 3)
611#define MT8173_PIN_121_KPROW2__FUNC_PWM4 (MTK_PIN_NO(121) | 4)
612#define MT8173_PIN_121_KPROW2__FUNC_USB_DRVVBUS_P1 (MTK_PIN_NO(121) | 5)
613#define MT8173_PIN_121_KPROW2__FUNC_DBG_MON_A_13_ (MTK_PIN_NO(121) | 7)
614
615#define MT8173_PIN_122_KPCOL0__FUNC_GPIO122 (MTK_PIN_NO(122) | 0)
616#define MT8173_PIN_122_KPCOL0__FUNC_KCOL0 (MTK_PIN_NO(122) | 1)
617#define MT8173_PIN_122_KPCOL0__FUNC_DBG_MON_A_14_ (MTK_PIN_NO(122) | 7)
618
619#define MT8173_PIN_123_KPCOL1__FUNC_GPIO123 (MTK_PIN_NO(123) | 0)
620#define MT8173_PIN_123_KPCOL1__FUNC_KCOL1 (MTK_PIN_NO(123) | 1)
621#define MT8173_PIN_123_KPCOL1__FUNC_IRDA_RXD (MTK_PIN_NO(123) | 2)
622#define MT8173_PIN_123_KPCOL1__FUNC_PWM5 (MTK_PIN_NO(123) | 3)
623#define MT8173_PIN_123_KPCOL1__FUNC_DBG_MON_A_15_ (MTK_PIN_NO(123) | 7)
624
625#define MT8173_PIN_124_KPCOL2__FUNC_GPIO124 (MTK_PIN_NO(124) | 0)
626#define MT8173_PIN_124_KPCOL2__FUNC_KCOL2 (MTK_PIN_NO(124) | 1)
627#define MT8173_PIN_124_KPCOL2__FUNC_IRDA_TXD (MTK_PIN_NO(124) | 2)
628#define MT8173_PIN_124_KPCOL2__FUNC_USB_DRVVBUS_P0 (MTK_PIN_NO(124) | 3)
629#define MT8173_PIN_124_KPCOL2__FUNC_PWM3 (MTK_PIN_NO(124) | 4)
630#define MT8173_PIN_124_KPCOL2__FUNC_USB_DRVVBUS_P1 (MTK_PIN_NO(124) | 5)
631#define MT8173_PIN_124_KPCOL2__FUNC_DBG_MON_A_16_ (MTK_PIN_NO(124) | 7)
632
633#define MT8173_PIN_125_SDA1__FUNC_GPIO125 (MTK_PIN_NO(125) | 0)
634#define MT8173_PIN_125_SDA1__FUNC_SDA1 (MTK_PIN_NO(125) | 1)
635
636#define MT8173_PIN_126_SCL1__FUNC_GPIO126 (MTK_PIN_NO(126) | 0)
637#define MT8173_PIN_126_SCL1__FUNC_SCL1 (MTK_PIN_NO(126) | 1)
638
639#define MT8173_PIN_127_LCM_RST__FUNC_GPIO127 (MTK_PIN_NO(127) | 0)
640#define MT8173_PIN_127_LCM_RST__FUNC_LCM_RST (MTK_PIN_NO(127) | 1)
641
642#define MT8173_PIN_128_I2S0_LRCK__FUNC_GPIO128 (MTK_PIN_NO(128) | 0)
643#define MT8173_PIN_128_I2S0_LRCK__FUNC_I2S0_WS (MTK_PIN_NO(128) | 1)
644#define MT8173_PIN_128_I2S0_LRCK__FUNC_I2S1_WS (MTK_PIN_NO(128) | 2)
645#define MT8173_PIN_128_I2S0_LRCK__FUNC_I2S2_WS (MTK_PIN_NO(128) | 3)
646#define MT8173_PIN_128_I2S0_LRCK__FUNC_SPI_CK_2_ (MTK_PIN_NO(128) | 5)
647#define MT8173_PIN_128_I2S0_LRCK__FUNC_DBG_MON_A_4_ (MTK_PIN_NO(128) | 7)
648
649#define MT8173_PIN_129_I2S0_BCK__FUNC_GPIO129 (MTK_PIN_NO(129) | 0)
650#define MT8173_PIN_129_I2S0_BCK__FUNC_I2S0_BCK (MTK_PIN_NO(129) | 1)
651#define MT8173_PIN_129_I2S0_BCK__FUNC_I2S1_BCK (MTK_PIN_NO(129) | 2)
652#define MT8173_PIN_129_I2S0_BCK__FUNC_I2S2_BCK (MTK_PIN_NO(129) | 3)
653#define MT8173_PIN_129_I2S0_BCK__FUNC_SPI_MI_2_ (MTK_PIN_NO(129) | 5)
654#define MT8173_PIN_129_I2S0_BCK__FUNC_DBG_MON_A_5_ (MTK_PIN_NO(129) | 7)
655
656#define MT8173_PIN_130_I2S0_MCK__FUNC_GPIO130 (MTK_PIN_NO(130) | 0)
657#define MT8173_PIN_130_I2S0_MCK__FUNC_I2S0_MCK (MTK_PIN_NO(130) | 1)
658#define MT8173_PIN_130_I2S0_MCK__FUNC_I2S1_MCK (MTK_PIN_NO(130) | 2)
659#define MT8173_PIN_130_I2S0_MCK__FUNC_I2S2_MCK (MTK_PIN_NO(130) | 3)
660#define MT8173_PIN_130_I2S0_MCK__FUNC_SPI_MO_2_ (MTK_PIN_NO(130) | 5)
661#define MT8173_PIN_130_I2S0_MCK__FUNC_DBG_MON_A_6_ (MTK_PIN_NO(130) | 7)
662
663#define MT8173_PIN_131_I2S0_DATA0__FUNC_GPIO131 (MTK_PIN_NO(131) | 0)
664#define MT8173_PIN_131_I2S0_DATA0__FUNC_I2S0_DO (MTK_PIN_NO(131) | 1)
665#define MT8173_PIN_131_I2S0_DATA0__FUNC_I2S1_DO_1 (MTK_PIN_NO(131) | 2)
666#define MT8173_PIN_131_I2S0_DATA0__FUNC_I2S2_DI_1 (MTK_PIN_NO(131) | 3)
667#define MT8173_PIN_131_I2S0_DATA0__FUNC_SPI_CS_2_ (MTK_PIN_NO(131) | 5)
668#define MT8173_PIN_131_I2S0_DATA0__FUNC_DBG_MON_A_7_ (MTK_PIN_NO(131) | 7)
669
670#define MT8173_PIN_132_I2S0_DATA1__FUNC_GPIO132 (MTK_PIN_NO(132) | 0)
671#define MT8173_PIN_132_I2S0_DATA1__FUNC_I2S0_DI (MTK_PIN_NO(132) | 1)
672#define MT8173_PIN_132_I2S0_DATA1__FUNC_I2S1_DO_2 (MTK_PIN_NO(132) | 2)
673#define MT8173_PIN_132_I2S0_DATA1__FUNC_I2S2_DI_2 (MTK_PIN_NO(132) | 3)
674#define MT8173_PIN_132_I2S0_DATA1__FUNC_DBG_MON_A_8_ (MTK_PIN_NO(132) | 7)
675
676#define MT8173_PIN_133_SDA4__FUNC_GPIO133 (MTK_PIN_NO(133) | 0)
677#define MT8173_PIN_133_SDA4__FUNC_SDA4 (MTK_PIN_NO(133) | 1)
678
679#define MT8173_PIN_134_SCL4__FUNC_GPIO134 (MTK_PIN_NO(134) | 0)
680#define MT8173_PIN_134_SCL4__FUNC_SCL4 (MTK_PIN_NO(134) | 1)
681
682#endif /* __DTS_MT8173_PINFUNC_H */
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 8554ec31dd9e..924fdb6673ff 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -13,6 +13,7 @@
13 13
14#include <dt-bindings/interrupt-controller/irq.h> 14#include <dt-bindings/interrupt-controller/irq.h>
15#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/interrupt-controller/arm-gic.h>
16#include "mt8173-pinfunc.h"
16 17
17/ { 18/ {
18 compatible = "mediatek,mt8173"; 19 compatible = "mediatek,mt8173";
@@ -105,6 +106,25 @@
105 compatible = "simple-bus"; 106 compatible = "simple-bus";
106 ranges; 107 ranges;
107 108
109 syscfg_pctl_a: syscfg_pctl_a@10005000 {
110 compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon";
111 reg = <0 0x10005000 0 0x1000>;
112 };
113
114 pio: pinctrl@0x10005000 {
115 compatible = "mediatek,mt8173-pinctrl";
116 reg = <0 0x1000B000 0 0x1000>;
117 mediatek,pctl-regmap = <&syscfg_pctl_a>;
118 pins-are-numbered;
119 gpio-controller;
120 #gpio-cells = <2>;
121 interrupt-controller;
122 #interrupt-cells = <2>;
123 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
124 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
125 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
126 };
127
108 sysirq: intpol-controller@10200620 { 128 sysirq: intpol-controller@10200620 {
109 compatible = "mediatek,mt8173-sysirq", 129 compatible = "mediatek,mt8173-sysirq",
110 "mediatek,mt6577-sysirq"; 130 "mediatek,mt6577-sysirq";
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
new file mode 100644
index 000000000000..8e94af64ee94
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -0,0 +1,5 @@
1dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb msm8916-mtp.dtb
2
3always := $(dtb-y)
4subdir-y := $(dts-dirs)
5clean-files := *.dtb
diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts
new file mode 100644
index 000000000000..825f489a2af7
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts
@@ -0,0 +1,21 @@
1/*
2 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14/dts-v1/;
15
16#include "apq8016-sbc.dtsi"
17
18/ {
19 model = "Qualcomm Technologies, Inc. APQ 8016 SBC";
20 compatible = "qcom,apq8016-sbc", "qcom,apq8016", "qcom,sbc";
21};
diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
new file mode 100644
index 000000000000..703a4f16e711
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
@@ -0,0 +1,33 @@
1/*
2 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include "msm8916.dtsi"
15
16/ {
17 aliases {
18 serial0 = &blsp1_uart2;
19 };
20
21 chosen {
22 stdout-path = "serial0";
23 };
24
25 soc {
26 serial@78b0000 {
27 status = "okay";
28 pinctrl-names = "default", "sleep";
29 pinctrl-0 = <&blsp1_uart2_default>;
30 pinctrl-1 = <&blsp1_uart2_sleep>;
31 };
32 };
33};
diff --git a/arch/arm64/boot/dts/qcom/msm8916-mtp.dts b/arch/arm64/boot/dts/qcom/msm8916-mtp.dts
new file mode 100644
index 000000000000..fced77f0fd3a
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/msm8916-mtp.dts
@@ -0,0 +1,22 @@
1/*
2 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14/dts-v1/;
15
16#include "msm8916-mtp.dtsi"
17
18/ {
19 model = "Qualcomm Technologies, Inc. MSM 8916 MTP";
20 compatible = "qcom,msm8916-mtp", "qcom,msm8916-mtp-smb1360",
21 "qcom,msm8916", "qcom,mtp";
22};
diff --git a/arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi b/arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi
new file mode 100644
index 000000000000..bea871b0df13
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi
@@ -0,0 +1,33 @@
1/*
2 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include "msm8916.dtsi"
15
16/ {
17 aliases {
18 serial0 = &blsp1_uart2;
19 };
20
21 chosen {
22 stdout-path = "serial0";
23 };
24
25 soc {
26 serial@78b0000 {
27 status = "okay";
28 pinctrl-names = "default", "sleep";
29 pinctrl-0 = <&blsp1_uart2_default>;
30 pinctrl-1 = <&blsp1_uart2_sleep>;
31 };
32 };
33};
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
new file mode 100644
index 000000000000..f212b8303d04
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -0,0 +1,196 @@
1/*
2 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <dt-bindings/interrupt-controller/arm-gic.h>
15#include <dt-bindings/clock/qcom,gcc-msm8916.h>
16#include <dt-bindings/reset/qcom,gcc-msm8916.h>
17
18/ {
19 model = "Qualcomm Technologies, Inc. MSM8916";
20 compatible = "qcom,msm8916";
21
22 interrupt-parent = <&intc>;
23
24 #address-cells = <2>;
25 #size-cells = <2>;
26
27 aliases { };
28
29 chosen { };
30
31 memory {
32 device_type = "memory";
33 /* We expect the bootloader to fill in the reg */
34 reg = <0 0 0 0>;
35 };
36
37 cpus {
38 #address-cells = <1>;
39 #size-cells = <0>;
40
41 CPU0: cpu@0 {
42 device_type = "cpu";
43 compatible = "arm,cortex-a53", "arm,armv8";
44 reg = <0x0>;
45 };
46
47 CPU1: cpu@1 {
48 device_type = "cpu";
49 compatible = "arm,cortex-a53", "arm,armv8";
50 reg = <0x1>;
51 };
52
53 CPU2: cpu@2 {
54 device_type = "cpu";
55 compatible = "arm,cortex-a53", "arm,armv8";
56 reg = <0x2>;
57 };
58
59 CPU3: cpu@3 {
60 device_type = "cpu";
61 compatible = "arm,cortex-a53", "arm,armv8";
62 reg = <0x3>;
63 };
64 };
65
66 timer {
67 compatible = "arm,armv8-timer";
68 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
69 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
70 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
71 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
72 };
73
74 soc: soc {
75 #address-cells = <1>;
76 #size-cells = <1>;
77 ranges = <0 0 0 0xffffffff>;
78 compatible = "simple-bus";
79
80 pinctrl@1000000 {
81 compatible = "qcom,msm8916-pinctrl";
82 reg = <0x1000000 0x300000>;
83 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
84 gpio-controller;
85 #gpio-cells = <2>;
86 interrupt-controller;
87 #interrupt-cells = <2>;
88
89 blsp1_uart2_default: blsp1_uart2_default {
90 pinmux {
91 function = "blsp_uart2";
92 pins = "gpio4", "gpio5";
93 };
94 pinconf {
95 pins = "gpio4", "gpio5";
96 drive-strength = <16>;
97 bias-disable;
98 };
99 };
100
101 blsp1_uart2_sleep: blsp1_uart2_sleep {
102 pinmux {
103 function = "blsp_uart2";
104 pins = "gpio4", "gpio5";
105 };
106 pinconf {
107 pins = "gpio4", "gpio5";
108 drive-strength = <2>;
109 bias-pull-down;
110 };
111 };
112 };
113
114 gcc: qcom,gcc@1800000 {
115 compatible = "qcom,gcc-msm8916";
116 #clock-cells = <1>;
117 #reset-cells = <1>;
118 reg = <0x1800000 0x80000>;
119 };
120
121 blsp1_uart2: serial@78b0000 {
122 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
123 reg = <0x78b0000 0x200>;
124 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
125 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
126 clock-names = "core", "iface";
127 status = "disabled";
128 };
129
130 intc: interrupt-controller@b000000 {
131 compatible = "qcom,msm-qgic2";
132 interrupt-controller;
133 #interrupt-cells = <3>;
134 reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
135 };
136
137 timer@b020000 {
138 #address-cells = <1>;
139 #size-cells = <1>;
140 ranges;
141 compatible = "arm,armv7-timer-mem";
142 reg = <0xb020000 0x1000>;
143 clock-frequency = <19200000>;
144
145 frame@b021000 {
146 frame-number = <0>;
147 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
148 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
149 reg = <0xb021000 0x1000>,
150 <0xb022000 0x1000>;
151 };
152
153 frame@b023000 {
154 frame-number = <1>;
155 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
156 reg = <0xb023000 0x1000>;
157 status = "disabled";
158 };
159
160 frame@b024000 {
161 frame-number = <2>;
162 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
163 reg = <0xb024000 0x1000>;
164 status = "disabled";
165 };
166
167 frame@b025000 {
168 frame-number = <3>;
169 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
170 reg = <0xb025000 0x1000>;
171 status = "disabled";
172 };
173
174 frame@b026000 {
175 frame-number = <4>;
176 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
177 reg = <0xb026000 0x1000>;
178 status = "disabled";
179 };
180
181 frame@b027000 {
182 frame-number = <5>;
183 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
184 reg = <0xb027000 0x1000>;
185 status = "disabled";
186 };
187
188 frame@b028000 {
189 frame-number = <6>;
190 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
191 reg = <0xb028000 0x1000>;
192 status = "disabled";
193 };
194 };
195 };
196};
diff --git a/arch/arm64/boot/dts/sprd/Makefile b/arch/arm64/boot/dts/sprd/Makefile
new file mode 100644
index 000000000000..b658c5e09b15
--- /dev/null
+++ b/arch/arm64/boot/dts/sprd/Makefile
@@ -0,0 +1,5 @@
1dtb-$(CONFIG_ARCH_SPRD) += sc9836-openphone.dtb
2
3always := $(dtb-y)
4subdir-y := $(dts-dirs)
5clean-files := *.dtb
diff --git a/arch/arm64/boot/dts/sprd/sc9836-openphone.dts b/arch/arm64/boot/dts/sprd/sc9836-openphone.dts
new file mode 100644
index 000000000000..e5657c35cd10
--- /dev/null
+++ b/arch/arm64/boot/dts/sprd/sc9836-openphone.dts
@@ -0,0 +1,49 @@
1/*
2 * Spreadtrum SC9836 openphone board DTS file
3 *
4 * Copyright (C) 2014, Spreadtrum Communications Inc.
5 *
6 * This file is licensed under a dual GPLv2 or X11 license.
7 */
8
9/dts-v1/;
10
11#include "sc9836.dtsi"
12
13/ {
14 model = "Spreadtrum SC9836 Openphone Board";
15
16 compatible = "sprd,sc9836-openphone", "sprd,sc9836";
17
18 aliases {
19 serial0 = &uart0;
20 serial1 = &uart1;
21 serial2 = &uart2;
22 serial3 = &uart3;
23 };
24
25 memory@80000000 {
26 device_type = "memory";
27 reg = <0 0x80000000 0 0x20000000>;
28 };
29
30 chosen {
31 stdout-path = "serial1:115200n8";
32 };
33};
34
35&uart0 {
36 status = "okay";
37};
38
39&uart1 {
40 status = "okay";
41};
42
43&uart2 {
44 status = "okay";
45};
46
47&uart3 {
48 status = "okay";
49};
diff --git a/arch/arm64/boot/dts/sprd/sc9836.dtsi b/arch/arm64/boot/dts/sprd/sc9836.dtsi
new file mode 100644
index 000000000000..ee34e1a36e03
--- /dev/null
+++ b/arch/arm64/boot/dts/sprd/sc9836.dtsi
@@ -0,0 +1,129 @@
1/*
2 * Spreadtrum SC9836 SoC DTS file
3 *
4 * Copyright (C) 2014, Spreadtrum Communications Inc.
5 *
6 * This file is licensed under a dual GPLv2 or X11 license.
7 */
8
9#include "sharkl64.dtsi"
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11
12/ {
13 compatible = "sprd,sc9836";
14
15 cpus {
16 #address-cells = <2>;
17 #size-cells = <0>;
18
19 cpu@0 {
20 device_type = "cpu";
21 compatible = "arm,cortex-a53", "arm,armv8";
22 reg = <0x0 0x0>;
23 enable-method = "psci";
24 };
25
26 cpu@1 {
27 device_type = "cpu";
28 compatible = "arm,cortex-a53", "arm,armv8";
29 reg = <0x0 0x1>;
30 enable-method = "psci";
31 };
32
33 cpu@2 {
34 device_type = "cpu";
35 compatible = "arm,cortex-a53", "arm,armv8";
36 reg = <0x0 0x2>;
37 enable-method = "psci";
38 };
39
40 cpu@3 {
41 device_type = "cpu";
42 compatible = "arm,cortex-a53", "arm,armv8";
43 reg = <0x0 0x3>;
44 enable-method = "psci";
45 };
46 };
47
48 etf@10003000 {
49 compatible = "arm,coresight-tmc", "arm,primecell";
50 reg = <0 0x10003000 0 0x1000>;
51 clocks = <&clk26mhz>;
52 clock-names = "apb_pclk";
53 port {
54 etf_in: endpoint {
55 slave-mode;
56 remote-endpoint = <&funnel_out_port0>;
57 };
58 };
59 };
60
61 funnel@10001000 {
62 compatible = "arm,coresight-funnel", "arm,primecell";
63 reg = <0 0x10001000 0 0x1000>;
64 clocks = <&clk26mhz>;
65 clock-names = "apb_pclk";
66 ports {
67 #address-cells = <1>;
68 #size-cells = <0>;
69
70 /* funnel output port */
71 port@0 {
72 reg = <0>;
73 funnel_out_port0: endpoint {
74 remote-endpoint = <&etf_in>;
75 };
76 };
77
78 /* funnel input port 0~3 is reserved for ETMs */
79 port@1 {
80 reg = <4>;
81 funnel_in_port4: endpoint {
82 slave-mode;
83 remote-endpoint = <&stm_out>;
84 };
85 };
86 };
87 };
88
89 stm@10006000 {
90 compatible = "arm,coresight-stm", "arm,primecell";
91 reg = <0 0x10006000 0 0x1000>,
92 <0 0x01000000 0 0x180000>;
93 reg-names = "stm-base", "stm-stimulus-base";
94 clocks = <&clk26mhz>;
95 clock-names = "apb_pclk";
96 port {
97 stm_out: endpoint {
98 remote-endpoint = <&funnel_in_port4>;
99 };
100 };
101 };
102
103 gic: interrupt-controller@12001000 {
104 compatible = "arm,gic-400";
105 reg = <0 0x12001000 0 0x1000>,
106 <0 0x12002000 0 0x2000>,
107 <0 0x12004000 0 0x2000>,
108 <0 0x12006000 0 0x2000>;
109 #interrupt-cells = <3>;
110 interrupt-controller;
111 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
112 };
113
114 psci {
115 compatible = "arm,psci";
116 method = "smc";
117 cpu_on = <0xc4000003>;
118 cpu_off = <0x84000002>;
119 cpu_suspend = <0xc4000001>;
120 };
121
122 timer {
123 compatible = "arm,armv8-timer";
124 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
125 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
126 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
127 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
128 };
129};
diff --git a/arch/arm64/boot/dts/sprd/sharkl64.dtsi b/arch/arm64/boot/dts/sprd/sharkl64.dtsi
new file mode 100644
index 000000000000..69f64e7fce7c
--- /dev/null
+++ b/arch/arm64/boot/dts/sprd/sharkl64.dtsi
@@ -0,0 +1,65 @@
1/*
2 * Spreadtrum Sharkl64 platform DTS file
3 *
4 * Copyright (C) 2014, Spreadtrum Communications Inc.
5 *
6 * This file is licensed under a dual GPLv2 or X11 license.
7 */
8
9/ {
10 interrupt-parent = <&gic>;
11 #address-cells = <2>;
12 #size-cells = <2>;
13
14 soc {
15 compatible = "simple-bus";
16 #address-cells = <2>;
17 #size-cells = <2>;
18 ranges;
19
20 ap-apb {
21 compatible = "simple-bus";
22 #address-cells = <2>;
23 #size-cells = <2>;
24 ranges;
25
26 uart0: serial@70000000 {
27 compatible = "sprd,sc9836-uart";
28 reg = <0 0x70000000 0 0x100>;
29 interrupts = <0 2 0xf04>;
30 clocks = <&clk26mhz>;
31 status = "disabled";
32 };
33
34 uart1: serial@70100000 {
35 compatible = "sprd,sc9836-uart";
36 reg = <0 0x70100000 0 0x100>;
37 interrupts = <0 3 0xf04>;
38 clocks = <&clk26mhz>;
39 status = "disabled";
40 };
41
42 uart2: serial@70200000 {
43 compatible = "sprd,sc9836-uart";
44 reg = <0 0x70200000 0 0x100>;
45 interrupts = <0 4 0xf04>;
46 clocks = <&clk26mhz>;
47 status = "disabled";
48 };
49
50 uart3: serial@70300000 {
51 compatible = "sprd,sc9836-uart";
52 reg = <0 0x70300000 0 0x100>;
53 interrupts = <0 5 0xf04>;
54 clocks = <&clk26mhz>;
55 status = "disabled";
56 };
57 };
58 };
59
60 clk26mhz: clk26mhz {
61 compatible = "fixed-clock";
62 #clock-cells = <0>;
63 clock-frequency = <26000000>;
64 };
65};
diff --git a/arch/arm64/boot/dts/xilinx/Makefile b/arch/arm64/boot/dts/xilinx/Makefile
new file mode 100644
index 000000000000..ae16427f6a4a
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/Makefile
@@ -0,0 +1,5 @@
1dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-ep108.dtb
2
3always := $(dtb-y)
4subdir-y := $(dts-dirs)
5clean-files := *.dtb
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts b/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
new file mode 100644
index 000000000000..0a3f40ecd06d
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
@@ -0,0 +1,47 @@
1/*
2 * dts file for Xilinx ZynqMP ep108 development board
3 *
4 * (C) Copyright 2014 - 2015, Xilinx, Inc.
5 *
6 * Michal Simek <michal.simek@xilinx.com>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 */
13
14/dts-v1/;
15
16/include/ "zynqmp.dtsi"
17
18/ {
19 model = "ZynqMP EP108";
20
21 aliases {
22 serial0 = &uart0;
23 };
24
25 chosen {
26 stdout-path = "serial0:115200n8";
27 };
28
29 memory {
30 device_type = "memory";
31 reg = <0x0 0x0 0x40000000>;
32 };
33};
34
35&gem0 {
36 status = "okay";
37 phy-handle = <&phy0>;
38 phy-mode = "rgmii-id";
39 phy0: phy@0{
40 reg = <0>;
41 max-speed = <100>;
42 };
43};
44
45&uart0 {
46 status = "okay";
47};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
new file mode 100644
index 000000000000..11e0b00045cf
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
@@ -0,0 +1,305 @@
1/*
2 * dts file for Xilinx ZynqMP
3 *
4 * (C) Copyright 2014 - 2015, Xilinx, Inc.
5 *
6 * Michal Simek <michal.simek@xilinx.com>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 */
13
14/ {
15 compatible = "xlnx,zynqmp";
16 #address-cells = <2>;
17 #size-cells = <1>;
18
19 cpus {
20 #address-cells = <1>;
21 #size-cells = <0>;
22
23 cpu@0 {
24 compatible = "arm,cortex-a53", "arm,armv8";
25 device_type = "cpu";
26 enable-method = "psci";
27 reg = <0x0>;
28 };
29
30 cpu@1 {
31 compatible = "arm,cortex-a53", "arm,armv8";
32 device_type = "cpu";
33 enable-method = "psci";
34 reg = <0x1>;
35 };
36
37 cpu@2 {
38 compatible = "arm,cortex-a53", "arm,armv8";
39 device_type = "cpu";
40 enable-method = "psci";
41 reg = <0x2>;
42 };
43
44 cpu@3 {
45 compatible = "arm,cortex-a53", "arm,armv8";
46 device_type = "cpu";
47 enable-method = "psci";
48 reg = <0x3>;
49 };
50 };
51
52 pmu {
53 compatible = "arm,armv8-pmuv3";
54 interrupts = <0 143 4>,
55 <0 144 4>,
56 <0 145 4>,
57 <0 146 4>;
58 };
59
60 psci {
61 compatible = "arm,psci-0.2";
62 method = "smc";
63 };
64
65 timer {
66 compatible = "arm,armv8-timer";
67 interrupt-parent = <&gic>;
68 interrupts = <1 13 0xf01>,
69 <1 14 0xf01>,
70 <1 11 0xf01>,
71 <1 10 0xf01>;
72 };
73
74 amba_apu {
75 compatible = "simple-bus";
76 #address-cells = <2>;
77 #size-cells = <1>;
78 ranges;
79
80 gic: interrupt-controller@f9010000 {
81 compatible = "arm,gic-400", "arm,cortex-a15-gic";
82 #interrupt-cells = <3>;
83 reg = <0x0 0xf9010000 0x10000>,
84 <0x0 0xf902f000 0x2000>,
85 <0x0 0xf9040000 0x20000>,
86 <0x0 0xf906f000 0x2000>;
87 interrupt-controller;
88 interrupt-parent = <&gic>;
89 interrupts = <1 9 0xf04>;
90 };
91 };
92
93 amba {
94 compatible = "simple-bus";
95 #address-cells = <2>;
96 #size-cells = <1>;
97 ranges;
98
99 misc_clk: misc_clk {
100 compatible = "fixed-clock";
101 #clock-cells = <0>;
102 clock-frequency = <25000000>;
103 };
104
105 ttc0: timer@ff110000 {
106 compatible = "cdns,ttc";
107 status = "disabled";
108 interrupt-parent = <&gic>;
109 interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
110 reg = <0x0 0xff110000 0x1000>;
111 clocks = <&misc_clk>;
112 timer-width = <32>;
113 };
114
115 ttc1: timer@ff120000 {
116 compatible = "cdns,ttc";
117 status = "disabled";
118 interrupt-parent = <&gic>;
119 interrupts = <0 39 4>, <0 40 4>, <0 41 4>;
120 reg = <0x0 0xff120000 0x1000>;
121 clocks = <&misc_clk>;
122 timer-width = <32>;
123 };
124
125 ttc2: timer@ff130000 {
126 compatible = "cdns,ttc";
127 status = "disabled";
128 interrupt-parent = <&gic>;
129 interrupts = <0 42 4>, <0 43 4>, <0 44 4>;
130 reg = <0x0 0xff130000 0x1000>;
131 clocks = <&misc_clk>;
132 timer-width = <32>;
133 };
134
135 ttc3: timer@ff140000 {
136 compatible = "cdns,ttc";
137 status = "disabled";
138 interrupt-parent = <&gic>;
139 interrupts = <0 45 4>, <0 46 4>, <0 47 4>;
140 reg = <0x0 0xff140000 0x1000>;
141 clocks = <&misc_clk>;
142 timer-width = <32>;
143 };
144
145 uart0: serial@ff000000 {
146 compatible = "cdns,uart-r1p8";
147 status = "disabled";
148 interrupt-parent = <&gic>;
149 interrupts = <0 21 4>;
150 reg = <0x0 0xff000000 0x1000>;
151 clock-names = "uart_clk", "pclk";
152 clocks = <&misc_clk &misc_clk>;
153 };
154
155 uart1: serial@ff010000 {
156 compatible = "cdns,uart-r1p8";
157 status = "disabled";
158 interrupt-parent = <&gic>;
159 interrupts = <0 22 4>;
160 reg = <0x0 0xff010000 0x1000>;
161 clock-names = "uart_clk", "pclk";
162 clocks = <&misc_clk &misc_clk>;
163 };
164
165 gpio: gpio@ff0a0000 {
166 compatible = "xlnx,zynq-gpio-1.0";
167 status = "disabled";
168 #gpio-cells = <0x2>;
169 clocks = <&misc_clk>;
170 interrupt-parent = <&gic>;
171 interrupts = <0 16 4>;
172 reg = <0x0 0xff0a0000 0x1000>;
173 };
174
175 gem0: ethernet@ff0b0000 {
176 compatible = "cdns,gem";
177 status = "disabled";
178 interrupt-parent = <&gic>;
179 interrupts = <0 57 4>, <0 57 4>;
180 reg = <0x0 0xff0b0000 0x1000>;
181 clock-names = "pclk", "hclk", "tx_clk";
182 clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
183 #address-cells = <1>;
184 #size-cells = <0>;
185 };
186
187 gem1: ethernet@ff0c0000 {
188 compatible = "cdns,gem";
189 status = "disabled";
190 interrupt-parent = <&gic>;
191 interrupts = <0 59 4>, <0 59 4>;
192 reg = <0x0 0xff0c0000 0x1000>;
193 clock-names = "pclk", "hclk", "tx_clk";
194 clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
195 #address-cells = <1>;
196 #size-cells = <0>;
197 };
198
199 gem2: ethernet@ff0d0000 {
200 compatible = "cdns,gem";
201 status = "disabled";
202 interrupt-parent = <&gic>;
203 interrupts = <0 61 4>, <0 61 4>;
204 reg = <0x0 0xff0d0000 0x1000>;
205 clock-names = "pclk", "hclk", "tx_clk";
206 clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
207 #address-cells = <1>;
208 #size-cells = <0>;
209 };
210
211 gem3: ethernet@ff0e0000 {
212 compatible = "cdns,gem";
213 status = "disabled";
214 interrupt-parent = <&gic>;
215 interrupts = <0 63 4>, <0 63 4>;
216 reg = <0x0 0xff0e0000 0x1000>;
217 clock-names = "pclk", "hclk", "tx_clk";
218 clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
219 #address-cells = <1>;
220 #size-cells = <0>;
221 };
222
223 spi0: spi@ff040000 {
224 compatible = "cdns,spi-r1p6";
225 status = "disabled";
226 interrupt-parent = <&gic>;
227 interrupts = <0 19 4>;
228 reg = <0x0 0xff040000 0x1000>;
229 clock-names = "ref_clk", "pclk";
230 clocks = <&misc_clk &misc_clk>;
231 #address-cells = <1>;
232 #size-cells = <0>;
233 };
234
235 spi1: spi@ff050000 {
236 compatible = "cdns,spi-r1p6";
237 status = "disabled";
238 interrupt-parent = <&gic>;
239 interrupts = <0 20 4>;
240 reg = <0x0 0xff050000 0x1000>;
241 clock-names = "ref_clk", "pclk";
242 clocks = <&misc_clk &misc_clk>;
243 #address-cells = <1>;
244 #size-cells = <0>;
245 };
246
247 i2c_clk: i2c_clk {
248 compatible = "fixed-clock";
249 #clock-cells = <0x0>;
250 clock-frequency = <111111111>;
251 };
252
253 i2c0: i2c@ff020000 {
254 compatible = "cdns,i2c-r1p10";
255 status = "disabled";
256 interrupt-parent = <&gic>;
257 interrupts = <0 17 4>;
258 reg = <0x0 0xff020000 0x1000>;
259 clocks = <&i2c_clk>;
260 #address-cells = <1>;
261 #size-cells = <0>;
262 };
263
264 i2c1: i2c@ff030000 {
265 compatible = "cdns,i2c-r1p10";
266 status = "disabled";
267 interrupt-parent = <&gic>;
268 interrupts = <0 18 4>;
269 reg = <0x0 0xff030000 0x1000>;
270 clocks = <&i2c_clk>;
271 #address-cells = <1>;
272 #size-cells = <0>;
273 };
274
275 sdhci0: sdhci@ff160000 {
276 compatible = "arasan,sdhci-8.9a";
277 status = "disabled";
278 interrupt-parent = <&gic>;
279 interrupts = <0 48 4>;
280 reg = <0x0 0xff160000 0x1000>;
281 clock-names = "clk_xin", "clk_ahb";
282 clocks = <&misc_clk>, <&misc_clk>;
283 };
284
285 sdhci1: sdhci@ff170000 {
286 compatible = "arasan,sdhci-8.9a";
287 status = "disabled";
288 interrupt-parent = <&gic>;
289 interrupts = <0 49 4>;
290 reg = <0x0 0xff170000 0x1000>;
291 clock-names = "clk_xin", "clk_ahb";
292 clocks = <&misc_clk>, <&misc_clk>;
293 };
294
295 watchdog0: watchdog@fd4d0000 {
296 compatible = "cdns,wdt-r1p2";
297 status = "disabled";
298 clocks= <&misc_clk>;
299 interrupt-parent = <&gic>;
300 interrupts = <0 52 1>;
301 reg = <0x0 0xfd4d0000 0x1000>;
302 timeout-sec = <10>;
303 };
304 };
305};
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-10 09:33:07 -0400