diff options
Diffstat (limited to 'arch/arm64/boot/dts/foundation-v8.dts')
-rw-r--r-- | arch/arm64/boot/dts/foundation-v8.dts | 230 |
1 files changed, 230 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/foundation-v8.dts b/arch/arm64/boot/dts/foundation-v8.dts new file mode 100644 index 000000000000..198682b6de31 --- /dev/null +++ b/arch/arm64/boot/dts/foundation-v8.dts | |||
@@ -0,0 +1,230 @@ | |||
1 | /* | ||
2 | * ARM Ltd. | ||
3 | * | ||
4 | * ARMv8 Foundation model DTS | ||
5 | */ | ||
6 | |||
7 | /dts-v1/; | ||
8 | |||
9 | / { | ||
10 | model = "Foundation-v8A"; | ||
11 | compatible = "arm,foundation-aarch64", "arm,vexpress"; | ||
12 | interrupt-parent = <&gic>; | ||
13 | #address-cells = <2>; | ||
14 | #size-cells = <2>; | ||
15 | |||
16 | chosen { }; | ||
17 | |||
18 | aliases { | ||
19 | serial0 = &v2m_serial0; | ||
20 | serial1 = &v2m_serial1; | ||
21 | serial2 = &v2m_serial2; | ||
22 | serial3 = &v2m_serial3; | ||
23 | }; | ||
24 | |||
25 | cpus { | ||
26 | #address-cells = <1>; | ||
27 | #size-cells = <0>; | ||
28 | |||
29 | cpu@0 { | ||
30 | device_type = "cpu"; | ||
31 | compatible = "arm,armv8"; | ||
32 | reg = <0x0 0x0>; | ||
33 | enable-method = "spin-table"; | ||
34 | cpu-release-addr = <0x0 0x8000fff8>; | ||
35 | }; | ||
36 | cpu@1 { | ||
37 | device_type = "cpu"; | ||
38 | compatible = "arm,armv8"; | ||
39 | reg = <0x0 0x1>; | ||
40 | enable-method = "spin-table"; | ||
41 | cpu-release-addr = <0x0 0x8000fff8>; | ||
42 | }; | ||
43 | cpu@2 { | ||
44 | device_type = "cpu"; | ||
45 | compatible = "arm,armv8"; | ||
46 | reg = <0x0 0x2>; | ||
47 | enable-method = "spin-table"; | ||
48 | cpu-release-addr = <0x0 0x8000fff8>; | ||
49 | }; | ||
50 | cpu@3 { | ||
51 | device_type = "cpu"; | ||
52 | compatible = "arm,armv8"; | ||
53 | reg = <0x0 0x3>; | ||
54 | enable-method = "spin-table"; | ||
55 | cpu-release-addr = <0x0 0x8000fff8>; | ||
56 | }; | ||
57 | }; | ||
58 | |||
59 | memory@80000000 { | ||
60 | device_type = "memory"; | ||
61 | reg = <0x00000000 0x80000000 0 0x80000000>, | ||
62 | <0x00000008 0x80000000 0 0x80000000>; | ||
63 | }; | ||
64 | |||
65 | gic: interrupt-controller@2c001000 { | ||
66 | compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; | ||
67 | #interrupt-cells = <3>; | ||
68 | #address-cells = <0>; | ||
69 | interrupt-controller; | ||
70 | reg = <0x0 0x2c001000 0 0x1000>, | ||
71 | <0x0 0x2c002000 0 0x1000>, | ||
72 | <0x0 0x2c004000 0 0x2000>, | ||
73 | <0x0 0x2c006000 0 0x2000>; | ||
74 | interrupts = <1 9 0xf04>; | ||
75 | }; | ||
76 | |||
77 | timer { | ||
78 | compatible = "arm,armv8-timer"; | ||
79 | interrupts = <1 13 0xff01>, | ||
80 | <1 14 0xff01>, | ||
81 | <1 11 0xff01>, | ||
82 | <1 10 0xff01>; | ||
83 | clock-frequency = <100000000>; | ||
84 | }; | ||
85 | |||
86 | pmu { | ||
87 | compatible = "arm,armv8-pmuv3"; | ||
88 | interrupts = <0 60 4>, | ||
89 | <0 61 4>, | ||
90 | <0 62 4>, | ||
91 | <0 63 4>; | ||
92 | }; | ||
93 | |||
94 | smb { | ||
95 | compatible = "arm,vexpress,v2m-p1", "simple-bus"; | ||
96 | arm,v2m-memory-map = "rs1"; | ||
97 | #address-cells = <2>; /* SMB chipselect number and offset */ | ||
98 | #size-cells = <1>; | ||
99 | |||
100 | ranges = <0 0 0 0x08000000 0x04000000>, | ||
101 | <1 0 0 0x14000000 0x04000000>, | ||
102 | <2 0 0 0x18000000 0x04000000>, | ||
103 | <3 0 0 0x1c000000 0x04000000>, | ||
104 | <4 0 0 0x0c000000 0x04000000>, | ||
105 | <5 0 0 0x10000000 0x04000000>; | ||
106 | |||
107 | #interrupt-cells = <1>; | ||
108 | interrupt-map-mask = <0 0 63>; | ||
109 | interrupt-map = <0 0 0 &gic 0 0 4>, | ||
110 | <0 0 1 &gic 0 1 4>, | ||
111 | <0 0 2 &gic 0 2 4>, | ||
112 | <0 0 3 &gic 0 3 4>, | ||
113 | <0 0 4 &gic 0 4 4>, | ||
114 | <0 0 5 &gic 0 5 4>, | ||
115 | <0 0 6 &gic 0 6 4>, | ||
116 | <0 0 7 &gic 0 7 4>, | ||
117 | <0 0 8 &gic 0 8 4>, | ||
118 | <0 0 9 &gic 0 9 4>, | ||
119 | <0 0 10 &gic 0 10 4>, | ||
120 | <0 0 11 &gic 0 11 4>, | ||
121 | <0 0 12 &gic 0 12 4>, | ||
122 | <0 0 13 &gic 0 13 4>, | ||
123 | <0 0 14 &gic 0 14 4>, | ||
124 | <0 0 15 &gic 0 15 4>, | ||
125 | <0 0 16 &gic 0 16 4>, | ||
126 | <0 0 17 &gic 0 17 4>, | ||
127 | <0 0 18 &gic 0 18 4>, | ||
128 | <0 0 19 &gic 0 19 4>, | ||
129 | <0 0 20 &gic 0 20 4>, | ||
130 | <0 0 21 &gic 0 21 4>, | ||
131 | <0 0 22 &gic 0 22 4>, | ||
132 | <0 0 23 &gic 0 23 4>, | ||
133 | <0 0 24 &gic 0 24 4>, | ||
134 | <0 0 25 &gic 0 25 4>, | ||
135 | <0 0 26 &gic 0 26 4>, | ||
136 | <0 0 27 &gic 0 27 4>, | ||
137 | <0 0 28 &gic 0 28 4>, | ||
138 | <0 0 29 &gic 0 29 4>, | ||
139 | <0 0 30 &gic 0 30 4>, | ||
140 | <0 0 31 &gic 0 31 4>, | ||
141 | <0 0 32 &gic 0 32 4>, | ||
142 | <0 0 33 &gic 0 33 4>, | ||
143 | <0 0 34 &gic 0 34 4>, | ||
144 | <0 0 35 &gic 0 35 4>, | ||
145 | <0 0 36 &gic 0 36 4>, | ||
146 | <0 0 37 &gic 0 37 4>, | ||
147 | <0 0 38 &gic 0 38 4>, | ||
148 | <0 0 39 &gic 0 39 4>, | ||
149 | <0 0 40 &gic 0 40 4>, | ||
150 | <0 0 41 &gic 0 41 4>, | ||
151 | <0 0 42 &gic 0 42 4>; | ||
152 | |||
153 | ethernet@2,02000000 { | ||
154 | compatible = "smsc,lan91c111"; | ||
155 | reg = <2 0x02000000 0x10000>; | ||
156 | interrupts = <15>; | ||
157 | }; | ||
158 | |||
159 | v2m_clk24mhz: clk24mhz { | ||
160 | compatible = "fixed-clock"; | ||
161 | #clock-cells = <0>; | ||
162 | clock-frequency = <24000000>; | ||
163 | clock-output-names = "v2m:clk24mhz"; | ||
164 | }; | ||
165 | |||
166 | v2m_refclk1mhz: refclk1mhz { | ||
167 | compatible = "fixed-clock"; | ||
168 | #clock-cells = <0>; | ||
169 | clock-frequency = <1000000>; | ||
170 | clock-output-names = "v2m:refclk1mhz"; | ||
171 | }; | ||
172 | |||
173 | v2m_refclk32khz: refclk32khz { | ||
174 | compatible = "fixed-clock"; | ||
175 | #clock-cells = <0>; | ||
176 | clock-frequency = <32768>; | ||
177 | clock-output-names = "v2m:refclk32khz"; | ||
178 | }; | ||
179 | |||
180 | iofpga@3,00000000 { | ||
181 | compatible = "arm,amba-bus", "simple-bus"; | ||
182 | #address-cells = <1>; | ||
183 | #size-cells = <1>; | ||
184 | ranges = <0 3 0 0x200000>; | ||
185 | |||
186 | v2m_sysreg: sysreg@010000 { | ||
187 | compatible = "arm,vexpress-sysreg"; | ||
188 | reg = <0x010000 0x1000>; | ||
189 | }; | ||
190 | |||
191 | v2m_serial0: uart@090000 { | ||
192 | compatible = "arm,pl011", "arm,primecell"; | ||
193 | reg = <0x090000 0x1000>; | ||
194 | interrupts = <5>; | ||
195 | clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; | ||
196 | clock-names = "uartclk", "apb_pclk"; | ||
197 | }; | ||
198 | |||
199 | v2m_serial1: uart@0a0000 { | ||
200 | compatible = "arm,pl011", "arm,primecell"; | ||
201 | reg = <0x0a0000 0x1000>; | ||
202 | interrupts = <6>; | ||
203 | clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; | ||
204 | clock-names = "uartclk", "apb_pclk"; | ||
205 | }; | ||
206 | |||
207 | v2m_serial2: uart@0b0000 { | ||
208 | compatible = "arm,pl011", "arm,primecell"; | ||
209 | reg = <0x0b0000 0x1000>; | ||
210 | interrupts = <7>; | ||
211 | clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; | ||
212 | clock-names = "uartclk", "apb_pclk"; | ||
213 | }; | ||
214 | |||
215 | v2m_serial3: uart@0c0000 { | ||
216 | compatible = "arm,pl011", "arm,primecell"; | ||
217 | reg = <0x0c0000 0x1000>; | ||
218 | interrupts = <8>; | ||
219 | clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; | ||
220 | clock-names = "uartclk", "apb_pclk"; | ||
221 | }; | ||
222 | |||
223 | virtio_block@0130000 { | ||
224 | compatible = "virtio,mmio"; | ||
225 | reg = <0x130000 0x1000>; | ||
226 | interrupts = <42>; | ||
227 | }; | ||
228 | }; | ||
229 | }; | ||
230 | }; | ||