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-rw-r--r--arch/arm26/nwfpe/ARM-gcc.h120
-rw-r--r--arch/arm26/nwfpe/ChangeLog83
-rw-r--r--arch/arm26/nwfpe/Makefile15
-rw-r--r--arch/arm26/nwfpe/double_cpdo.c288
-rw-r--r--arch/arm26/nwfpe/entry.S114
-rw-r--r--arch/arm26/nwfpe/extended_cpdo.c273
-rw-r--r--arch/arm26/nwfpe/fpa11.c221
-rw-r--r--arch/arm26/nwfpe/fpa11.h87
-rw-r--r--arch/arm26/nwfpe/fpa11.inl51
-rw-r--r--arch/arm26/nwfpe/fpa11_cpdo.c117
-rw-r--r--arch/arm26/nwfpe/fpa11_cpdt.c368
-rw-r--r--arch/arm26/nwfpe/fpa11_cprt.c289
-rw-r--r--arch/arm26/nwfpe/fpmodule.c182
-rw-r--r--arch/arm26/nwfpe/fpmodule.h47
-rw-r--r--arch/arm26/nwfpe/fpmodule.inl84
-rw-r--r--arch/arm26/nwfpe/fpopcode.c148
-rw-r--r--arch/arm26/nwfpe/fpopcode.h390
-rw-r--r--arch/arm26/nwfpe/fpsr.h108
-rw-r--r--arch/arm26/nwfpe/milieu.h48
-rw-r--r--arch/arm26/nwfpe/single_cpdo.c255
-rw-r--r--arch/arm26/nwfpe/softfloat-macros740
-rw-r--r--arch/arm26/nwfpe/softfloat-specialize366
-rw-r--r--arch/arm26/nwfpe/softfloat.c3439
-rw-r--r--arch/arm26/nwfpe/softfloat.h232
24 files changed, 8065 insertions, 0 deletions
diff --git a/arch/arm26/nwfpe/ARM-gcc.h b/arch/arm26/nwfpe/ARM-gcc.h
new file mode 100644
index 000000000000..e6598470b076
--- /dev/null
+++ b/arch/arm26/nwfpe/ARM-gcc.h
@@ -0,0 +1,120 @@
1/*
2-------------------------------------------------------------------------------
3The macro `BITS64' can be defined to indicate that 64-bit integer types are
4supported by the compiler.
5-------------------------------------------------------------------------------
6*/
7#define BITS64
8
9/*
10-------------------------------------------------------------------------------
11Each of the following `typedef's defines the most convenient type that holds
12integers of at least as many bits as specified. For example, `uint8' should
13be the most convenient type that can hold unsigned integers of as many as
148 bits. The `flag' type must be able to hold either a 0 or 1. For most
15implementations of C, `flag', `uint8', and `int8' should all be `typedef'ed
16to the same as `int'.
17-------------------------------------------------------------------------------
18*/
19typedef char flag;
20typedef unsigned char uint8;
21typedef signed char int8;
22typedef int uint16;
23typedef int int16;
24typedef unsigned int uint32;
25typedef signed int int32;
26#ifdef BITS64
27typedef unsigned long long int bits64;
28typedef signed long long int sbits64;
29#endif
30
31/*
32-------------------------------------------------------------------------------
33Each of the following `typedef's defines a type that holds integers
34of _exactly_ the number of bits specified. For instance, for most
35implementation of C, `bits16' and `sbits16' should be `typedef'ed to
36`unsigned short int' and `signed short int' (or `short int'), respectively.
37-------------------------------------------------------------------------------
38*/
39typedef unsigned char bits8;
40typedef signed char sbits8;
41typedef unsigned short int bits16;
42typedef signed short int sbits16;
43typedef unsigned int bits32;
44typedef signed int sbits32;
45#ifdef BITS64
46typedef unsigned long long int uint64;
47typedef signed long long int int64;
48#endif
49
50#ifdef BITS64
51/*
52-------------------------------------------------------------------------------
53The `LIT64' macro takes as its argument a textual integer literal and if
54necessary ``marks'' the literal as having a 64-bit integer type. For
55example, the Gnu C Compiler (`gcc') requires that 64-bit literals be
56appended with the letters `LL' standing for `long long', which is `gcc's
57name for the 64-bit integer type. Some compilers may allow `LIT64' to be
58defined as the identity macro: `#define LIT64( a ) a'.
59-------------------------------------------------------------------------------
60*/
61#define LIT64( a ) a##LL
62#endif
63
64/*
65-------------------------------------------------------------------------------
66The macro `INLINE' can be used before functions that should be inlined. If
67a compiler does not support explicit inlining, this macro should be defined
68to be `static'.
69-------------------------------------------------------------------------------
70*/
71#define INLINE extern __inline__
72
73
74/* For use as a GCC soft-float library we need some special function names. */
75
76#ifdef __LIBFLOAT__
77
78/* Some 32-bit ops can be mapped straight across by just changing the name. */
79#define float32_add __addsf3
80#define float32_sub __subsf3
81#define float32_mul __mulsf3
82#define float32_div __divsf3
83#define int32_to_float32 __floatsisf
84#define float32_to_int32_round_to_zero __fixsfsi
85#define float32_to_uint32_round_to_zero __fixunssfsi
86
87/* These ones go through the glue code. To avoid namespace pollution
88 we rename the internal functions too. */
89#define float32_eq ___float32_eq
90#define float32_le ___float32_le
91#define float32_lt ___float32_lt
92
93/* All the 64-bit ops have to go through the glue, so we pull the same
94 trick. */
95#define float64_add ___float64_add
96#define float64_sub ___float64_sub
97#define float64_mul ___float64_mul
98#define float64_div ___float64_div
99#define int32_to_float64 ___int32_to_float64
100#define float64_to_int32_round_to_zero ___float64_to_int32_round_to_zero
101#define float64_to_uint32_round_to_zero ___float64_to_uint32_round_to_zero
102#define float64_to_float32 ___float64_to_float32
103#define float32_to_float64 ___float32_to_float64
104#define float64_eq ___float64_eq
105#define float64_le ___float64_le
106#define float64_lt ___float64_lt
107
108#if 0
109#define float64_add __adddf3
110#define float64_sub __subdf3
111#define float64_mul __muldf3
112#define float64_div __divdf3
113#define int32_to_float64 __floatsidf
114#define float64_to_int32_round_to_zero __fixdfsi
115#define float64_to_uint32_round_to_zero __fixunsdfsi
116#define float64_to_float32 __truncdfsf2
117#define float32_to_float64 __extendsfdf2
118#endif
119
120#endif
diff --git a/arch/arm26/nwfpe/ChangeLog b/arch/arm26/nwfpe/ChangeLog
new file mode 100644
index 000000000000..0c580f764baf
--- /dev/null
+++ b/arch/arm26/nwfpe/ChangeLog
@@ -0,0 +1,83 @@
12002-01-19 Russell King <rmk@arm.linux.org.uk>
2
3 * fpa11.h - Add documentation
4 - remove userRegisters pointer from this structure.
5 - add new method to obtain integer register values.
6 * softfloat.c - Remove float128
7 * softfloat.h - Remove float128
8 * softfloat-specialize - Remove float128
9
10 * The FPA11 structure is not a kernel-specific data structure.
11 It is used by users of ptrace to examine the values of the
12 floating point registers. Therefore, any changes to the
13 FPA11 structure (size or position of elements contained
14 within) have to be well thought out.
15
16 * Since 128-bit float requires the FPA11 structure to change
17 size, it has been removed. 128-bit float is currently unused,
18 and needs various things to be re-worked so that we won't
19 overflow the available space in the task structure.
20
21 * The changes are designed to break any patch that goes on top
22 of this code, so that the authors properly review their changes.
23
241999-08-19 Scott Bambrough <scottb@netwinder.org>
25
26 * fpmodule.c - Changed version number to 0.95
27 * fpa11.h - modified FPA11, FPREG structures
28 * fpa11.c - Changes due to FPA11, FPREG structure alterations.
29 * fpa11_cpdo.c - Changes due to FPA11, FPREG structure alterations.
30 * fpa11_cpdt.c - Changes due to FPA11, FPREG structure alterations.
31 * fpa11_cprt.c - Changes due to FPA11, FPREG structure alterations.
32 * single_cpdo.c - Changes due to FPA11, FPREG structure alterations.
33 * double_cpdo.c - Changes due to FPA11, FPREG structure alterations.
34 * extended_cpdo.c - Changes due to FPA11, FPREG structure alterations.
35
36 * I discovered several bugs. First and worst is that the kernel
37 passes in a pointer to the FPE's state area. This is defined
38 as a struct user_fp (see user.h). This pointer was cast to a
39 FPA11*. Unfortunately FPA11 and user_fp are of different sizes;
40 user_fp is smaller. This meant that the FPE scribbled on things
41 below its area, which is bad, as the area is in the thread_struct
42 embedded in the process task structure. Thus we were scribbling
43 over one of the most important structures in the entire OS.
44
45 * user_fp and FPA11 have now been harmonized. Most of the changes
46 in the above code were dereferencing problems due to moving the
47 register type out of FPREG, and getting rid of the union variable
48 fpvalue.
49
50 * Second I noticed resetFPA11 was not always being called for a
51 task. This should happen on the first floating point exception
52 that occurs. It is controlled by init_flag in FPA11. The
53 comment in the code beside init_flag state the kernel guarantees
54 this to be zero. Not so. I found that the kernel recycles task
55 structures, and that recycled ones may not have init_flag zeroed.
56 I couldn't even find anything that guarantees it is zeroed when
57 when the task structure is initially allocated. In any case
58 I now initialize the entire FPE state in the thread structure to
59 zero when allocated and recycled. See alloc_task_struct() and
60 flush_thread() in arch/arm/process.c. The change to
61 alloc_task_struct() may not be necessary, but I left it in for
62 completeness (better safe than sorry).
63
641998-11-23 Scott Bambrough <scottb@netwinder.org>
65
66 * README.FPE - fix typo in description of lfm/sfm instructions
67 * NOTES - Added file to describe known bugs/problems
68 * fpmodule.c - Changed version number to 0.94
69
701998-11-20 Scott Bambrough <scottb@netwinder.org>
71
72 * README.FPE - fix description of URD, NRM instructions
73 * TODO - remove URD, NRM instructions from TODO list
74 * single_cpdo.c - implement URD, NRM
75 * double_cpdo.c - implement URD, NRM
76 * extended_cpdo.c - implement URD, NRM
77
781998-11-19 Scott Bambrough <scottb@netwinder.org>
79
80 * ChangeLog - Added this file to track changes made.
81 * fpa11.c - added code to initialize register types to typeNone
82 * fpa11_cpdt.c - fixed bug in storeExtended (typeExtended changed to
83 typeDouble in switch statement)
diff --git a/arch/arm26/nwfpe/Makefile b/arch/arm26/nwfpe/Makefile
new file mode 100644
index 000000000000..b39d34dff054
--- /dev/null
+++ b/arch/arm26/nwfpe/Makefile
@@ -0,0 +1,15 @@
1#
2# Copyright (C) 1998, 1999, 2001 Philip Blundell
3#
4
5obj-y :=
6obj-m :=
7obj-n :=
8
9obj-$(CONFIG_FPE_NWFPE) += nwfpe.o
10
11nwfpe-objs := fpa11.o fpa11_cpdo.o fpa11_cpdt.o fpa11_cprt.o \
12 fpmodule.o fpopcode.o softfloat.o \
13 single_cpdo.o double_cpdo.o extended_cpdo.o \
14 entry.o
15
diff --git a/arch/arm26/nwfpe/double_cpdo.c b/arch/arm26/nwfpe/double_cpdo.c
new file mode 100644
index 000000000000..7f4fef0216c7
--- /dev/null
+++ b/arch/arm26/nwfpe/double_cpdo.c
@@ -0,0 +1,288 @@
1/*
2 NetWinder Floating Point Emulator
3 (c) Rebel.COM, 1998,1999
4
5 Direct questions, comments to Scott Bambrough <scottb@netwinder.org>
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20*/
21
22#include "fpa11.h"
23#include "softfloat.h"
24#include "fpopcode.h"
25
26float64 float64_exp(float64 Fm);
27float64 float64_ln(float64 Fm);
28float64 float64_sin(float64 rFm);
29float64 float64_cos(float64 rFm);
30float64 float64_arcsin(float64 rFm);
31float64 float64_arctan(float64 rFm);
32float64 float64_log(float64 rFm);
33float64 float64_tan(float64 rFm);
34float64 float64_arccos(float64 rFm);
35float64 float64_pow(float64 rFn,float64 rFm);
36float64 float64_pol(float64 rFn,float64 rFm);
37
38unsigned int DoubleCPDO(const unsigned int opcode)
39{
40 FPA11 *fpa11 = GET_FPA11();
41 float64 rFm, rFn = 0; //FIXME - should be zero?
42 unsigned int Fd, Fm, Fn, nRc = 1;
43
44 //printk("DoubleCPDO(0x%08x)\n",opcode);
45
46 Fm = getFm(opcode);
47 if (CONSTANT_FM(opcode))
48 {
49 rFm = getDoubleConstant(Fm);
50 }
51 else
52 {
53 switch (fpa11->fType[Fm])
54 {
55 case typeSingle:
56 rFm = float32_to_float64(fpa11->fpreg[Fm].fSingle);
57 break;
58
59 case typeDouble:
60 rFm = fpa11->fpreg[Fm].fDouble;
61 break;
62
63 case typeExtended:
64 // !! patb
65 //printk("not implemented! why not?\n");
66 //!! ScottB
67 // should never get here, if extended involved
68 // then other operand should be promoted then
69 // ExtendedCPDO called.
70 break;
71
72 default: return 0;
73 }
74 }
75
76 if (!MONADIC_INSTRUCTION(opcode))
77 {
78 Fn = getFn(opcode);
79 switch (fpa11->fType[Fn])
80 {
81 case typeSingle:
82 rFn = float32_to_float64(fpa11->fpreg[Fn].fSingle);
83 break;
84
85 case typeDouble:
86 rFn = fpa11->fpreg[Fn].fDouble;
87 break;
88
89 default: return 0;
90 }
91 }
92
93 Fd = getFd(opcode);
94 /* !! this switch isn't optimized; better (opcode & MASK_ARITHMETIC_OPCODE)>>24, sort of */
95 switch (opcode & MASK_ARITHMETIC_OPCODE)
96 {
97 /* dyadic opcodes */
98 case ADF_CODE:
99 fpa11->fpreg[Fd].fDouble = float64_add(rFn,rFm);
100 break;
101
102 case MUF_CODE:
103 case FML_CODE:
104 fpa11->fpreg[Fd].fDouble = float64_mul(rFn,rFm);
105 break;
106
107 case SUF_CODE:
108 fpa11->fpreg[Fd].fDouble = float64_sub(rFn,rFm);
109 break;
110
111 case RSF_CODE:
112 fpa11->fpreg[Fd].fDouble = float64_sub(rFm,rFn);
113 break;
114
115 case DVF_CODE:
116 case FDV_CODE:
117 fpa11->fpreg[Fd].fDouble = float64_div(rFn,rFm);
118 break;
119
120 case RDF_CODE:
121 case FRD_CODE:
122 fpa11->fpreg[Fd].fDouble = float64_div(rFm,rFn);
123 break;
124
125#if 0
126 case POW_CODE:
127 fpa11->fpreg[Fd].fDouble = float64_pow(rFn,rFm);
128 break;
129
130 case RPW_CODE:
131 fpa11->fpreg[Fd].fDouble = float64_pow(rFm,rFn);
132 break;
133#endif
134
135 case RMF_CODE:
136 fpa11->fpreg[Fd].fDouble = float64_rem(rFn,rFm);
137 break;
138
139#if 0
140 case POL_CODE:
141 fpa11->fpreg[Fd].fDouble = float64_pol(rFn,rFm);
142 break;
143#endif
144
145 /* monadic opcodes */
146 case MVF_CODE:
147 fpa11->fpreg[Fd].fDouble = rFm;
148 break;
149
150 case MNF_CODE:
151 {
152 unsigned int *p = (unsigned int*)&rFm;
153 p[1] ^= 0x80000000;
154 fpa11->fpreg[Fd].fDouble = rFm;
155 }
156 break;
157
158 case ABS_CODE:
159 {
160 unsigned int *p = (unsigned int*)&rFm;
161 p[1] &= 0x7fffffff;
162 fpa11->fpreg[Fd].fDouble = rFm;
163 }
164 break;
165
166 case RND_CODE:
167 case URD_CODE:
168 fpa11->fpreg[Fd].fDouble = float64_round_to_int(rFm);
169 break;
170
171 case SQT_CODE:
172 fpa11->fpreg[Fd].fDouble = float64_sqrt(rFm);
173 break;
174
175#if 0
176 case LOG_CODE:
177 fpa11->fpreg[Fd].fDouble = float64_log(rFm);
178 break;
179
180 case LGN_CODE:
181 fpa11->fpreg[Fd].fDouble = float64_ln(rFm);
182 break;
183
184 case EXP_CODE:
185 fpa11->fpreg[Fd].fDouble = float64_exp(rFm);
186 break;
187
188 case SIN_CODE:
189 fpa11->fpreg[Fd].fDouble = float64_sin(rFm);
190 break;
191
192 case COS_CODE:
193 fpa11->fpreg[Fd].fDouble = float64_cos(rFm);
194 break;
195
196 case TAN_CODE:
197 fpa11->fpreg[Fd].fDouble = float64_tan(rFm);
198 break;
199
200 case ASN_CODE:
201 fpa11->fpreg[Fd].fDouble = float64_arcsin(rFm);
202 break;
203
204 case ACS_CODE:
205 fpa11->fpreg[Fd].fDouble = float64_arccos(rFm);
206 break;
207
208 case ATN_CODE:
209 fpa11->fpreg[Fd].fDouble = float64_arctan(rFm);
210 break;
211#endif
212
213 case NRM_CODE:
214 break;
215
216 default:
217 {
218 nRc = 0;
219 }
220 }
221
222 if (0 != nRc) fpa11->fType[Fd] = typeDouble;
223 return nRc;
224}
225
226#if 0
227float64 float64_exp(float64 rFm)
228{
229 return rFm;
230//series
231}
232
233float64 float64_ln(float64 rFm)
234{
235 return rFm;
236//series
237}
238
239float64 float64_sin(float64 rFm)
240{
241 return rFm;
242//series
243}
244
245float64 float64_cos(float64 rFm)
246{
247 return rFm;
248 //series
249}
250
251#if 0
252float64 float64_arcsin(float64 rFm)
253{
254//series
255}
256
257float64 float64_arctan(float64 rFm)
258{
259 //series
260}
261#endif
262
263float64 float64_log(float64 rFm)
264{
265 return float64_div(float64_ln(rFm),getDoubleConstant(7));
266}
267
268float64 float64_tan(float64 rFm)
269{
270 return float64_div(float64_sin(rFm),float64_cos(rFm));
271}
272
273float64 float64_arccos(float64 rFm)
274{
275return rFm;
276 //return float64_sub(halfPi,float64_arcsin(rFm));
277}
278
279float64 float64_pow(float64 rFn,float64 rFm)
280{
281 return float64_exp(float64_mul(rFm,float64_ln(rFn)));
282}
283
284float64 float64_pol(float64 rFn,float64 rFm)
285{
286 return float64_arctan(float64_div(rFn,rFm));
287}
288#endif
diff --git a/arch/arm26/nwfpe/entry.S b/arch/arm26/nwfpe/entry.S
new file mode 100644
index 000000000000..7d6dfaad80c2
--- /dev/null
+++ b/arch/arm26/nwfpe/entry.S
@@ -0,0 +1,114 @@
1/*
2 NetWinder Floating Point Emulator
3 (c) Rebel.COM, 1998
4 (c) Philip Blundell 1998-1999
5
6 Direct questions, comments to Scott Bambrough <scottb@netwinder.org>
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21*/
22
23#include <asm/asm_offsets.h>
24
25/* This is the kernel's entry point into the floating point emulator.
26It is called from the kernel with code similar to this:
27
28 mov fp, #0
29 teqp pc, #PSR_I_BIT | MODE_SVC
30 ldr r4, .LC2
31 ldr pc, [r4] @ Call FP module USR entry point
32
33The kernel expects the emulator to return via one of two possible
34points of return it passes to the emulator. The emulator, if
35successful in its emulation, jumps to ret_from_exception and the
36kernel takes care of returning control from the trap to the user code.
37If the emulator is unable to emulate the instruction, it returns to
38fpundefinstr and the kernel halts the user program with a core dump.
39
40This routine does four things:
41
421) It saves SP into a variable called userRegisters. The kernel has
43created a struct pt_regs on the stack and saved the user registers
44into it. See /usr/include/asm/proc/ptrace.h for details. The
45emulator code uses userRegisters as the base of an array of words from
46which the contents of the registers can be extracted.
47
482) It locates the FP emulator work area within the TSS structure and
49points `fpa11' to it.
50
513) It calls EmulateAll to emulate a floating point instruction.
52EmulateAll returns 1 if the emulation was successful, or 0 if not.
53
544) If an instruction has been emulated successfully, it looks ahead at
55the next instruction. If it is a floating point instruction, it
56executes the instruction, without returning to user space. In this
57way it repeatedly looks ahead and executes floating point instructions
58until it encounters a non floating point instruction, at which time it
59returns via _fpreturn.
60
61This is done to reduce the effect of the trap overhead on each
62floating point instructions. GCC attempts to group floating point
63instructions to allow the emulator to spread the cost of the trap over
64several floating point instructions. */
65
66 .globl nwfpe_enter
67nwfpe_enter:
68 mov sl, sp
69 bl FPA11_CheckInit @ check to see if we are initialised
70
71 ldr r5, [sp, #60] @ get contents of PC
72 bic r5, r5, #0xfc000003
73 ldr r0, [r5, #-4] @ get actual instruction into r0
74 bl EmulateAll @ emulate the instruction
751: cmp r0, #0 @ was emulation successful
76 beq fpundefinstr @ no, return failure
77
78next:
79.Lx1: ldrt r6, [r5], #4 @ get the next instruction and
80 @ increment PC
81
82 and r2, r6, #0x0F000000 @ test for FP insns
83 teq r2, #0x0C000000
84 teqne r2, #0x0D000000
85 teqne r2, #0x0E000000
86 bne ret_from_exception @ return ok if not a fp insn
87
88 ldr r9, [sp, #60] @ get new condition codes
89 and r9, r9, #0xfc000003
90 orr r7, r5, r9
91 str r7, [sp, #60] @ update PC copy in regs
92
93 mov r0, r6 @ save a copy
94 mov r1, r9 @ fetch the condition codes
95 bl checkCondition @ check the condition
96 cmp r0, #0 @ r0 = 0 ==> condition failed
97
98 @ if condition code failed to match, next insn
99 beq next @ get the next instruction;
100
101 mov r0, r6 @ prepare for EmulateAll()
102 adr lr, 1b
103 orr lr, lr, #3
104 b EmulateAll @ if r0 != 0, goto EmulateAll
105
106.Lret: b ret_from_exception @ let the user eat segfaults
107
108 @ We need to be prepared for the instruction at .Lx1 to fault.
109 @ Emit the appropriate exception gunk to fix things up.
110 .section __ex_table,"a"
111 .align 3
112 .long .Lx1
113 ldr lr, [lr, $(.Lret - .Lx1)/4]
114 .previous
diff --git a/arch/arm26/nwfpe/extended_cpdo.c b/arch/arm26/nwfpe/extended_cpdo.c
new file mode 100644
index 000000000000..331407596d91
--- /dev/null
+++ b/arch/arm26/nwfpe/extended_cpdo.c
@@ -0,0 +1,273 @@
1/*
2 NetWinder Floating Point Emulator
3 (c) Rebel.COM, 1998,1999
4
5 Direct questions, comments to Scott Bambrough <scottb@netwinder.org>
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20*/
21
22#include "fpa11.h"
23#include "softfloat.h"
24#include "fpopcode.h"
25
26floatx80 floatx80_exp(floatx80 Fm);
27floatx80 floatx80_ln(floatx80 Fm);
28floatx80 floatx80_sin(floatx80 rFm);
29floatx80 floatx80_cos(floatx80 rFm);
30floatx80 floatx80_arcsin(floatx80 rFm);
31floatx80 floatx80_arctan(floatx80 rFm);
32floatx80 floatx80_log(floatx80 rFm);
33floatx80 floatx80_tan(floatx80 rFm);
34floatx80 floatx80_arccos(floatx80 rFm);
35floatx80 floatx80_pow(floatx80 rFn,floatx80 rFm);
36floatx80 floatx80_pol(floatx80 rFn,floatx80 rFm);
37
38unsigned int ExtendedCPDO(const unsigned int opcode)
39{
40 FPA11 *fpa11 = GET_FPA11();
41 floatx80 rFm, rFn;
42 unsigned int Fd, Fm, Fn, nRc = 1;
43
44 //printk("ExtendedCPDO(0x%08x)\n",opcode);
45
46 Fm = getFm(opcode);
47 if (CONSTANT_FM(opcode))
48 {
49 rFm = getExtendedConstant(Fm);
50 }
51 else
52 {
53 switch (fpa11->fType[Fm])
54 {
55 case typeSingle:
56 rFm = float32_to_floatx80(fpa11->fpreg[Fm].fSingle);
57 break;
58
59 case typeDouble:
60 rFm = float64_to_floatx80(fpa11->fpreg[Fm].fDouble);
61 break;
62
63 case typeExtended:
64 rFm = fpa11->fpreg[Fm].fExtended;
65 break;
66
67 default: return 0;
68 }
69 }
70
71 if (!MONADIC_INSTRUCTION(opcode))
72 {
73 Fn = getFn(opcode);
74 switch (fpa11->fType[Fn])
75 {
76 case typeSingle:
77 rFn = float32_to_floatx80(fpa11->fpreg[Fn].fSingle);
78 break;
79
80 case typeDouble:
81 rFn = float64_to_floatx80(fpa11->fpreg[Fn].fDouble);
82 break;
83
84 case typeExtended:
85 rFn = fpa11->fpreg[Fn].fExtended;
86 break;
87
88 default: return 0;
89 }
90 }
91
92 Fd = getFd(opcode);
93 switch (opcode & MASK_ARITHMETIC_OPCODE)
94 {
95 /* dyadic opcodes */
96 case ADF_CODE:
97 fpa11->fpreg[Fd].fExtended = floatx80_add(rFn,rFm);
98 break;
99
100 case MUF_CODE:
101 case FML_CODE:
102 fpa11->fpreg[Fd].fExtended = floatx80_mul(rFn,rFm);
103 break;
104
105 case SUF_CODE:
106 fpa11->fpreg[Fd].fExtended = floatx80_sub(rFn,rFm);
107 break;
108
109 case RSF_CODE:
110 fpa11->fpreg[Fd].fExtended = floatx80_sub(rFm,rFn);
111 break;
112
113 case DVF_CODE:
114 case FDV_CODE:
115 fpa11->fpreg[Fd].fExtended = floatx80_div(rFn,rFm);
116 break;
117
118 case RDF_CODE:
119 case FRD_CODE:
120 fpa11->fpreg[Fd].fExtended = floatx80_div(rFm,rFn);
121 break;
122
123#if 0
124 case POW_CODE:
125 fpa11->fpreg[Fd].fExtended = floatx80_pow(rFn,rFm);
126 break;
127
128 case RPW_CODE:
129 fpa11->fpreg[Fd].fExtended = floatx80_pow(rFm,rFn);
130 break;
131#endif
132
133 case RMF_CODE:
134 fpa11->fpreg[Fd].fExtended = floatx80_rem(rFn,rFm);
135 break;
136
137#if 0
138 case POL_CODE:
139 fpa11->fpreg[Fd].fExtended = floatx80_pol(rFn,rFm);
140 break;
141#endif
142
143 /* monadic opcodes */
144 case MVF_CODE:
145 fpa11->fpreg[Fd].fExtended = rFm;
146 break;
147
148 case MNF_CODE:
149 rFm.high ^= 0x8000;
150 fpa11->fpreg[Fd].fExtended = rFm;
151 break;
152
153 case ABS_CODE:
154 rFm.high &= 0x7fff;
155 fpa11->fpreg[Fd].fExtended = rFm;
156 break;
157
158 case RND_CODE:
159 case URD_CODE:
160 fpa11->fpreg[Fd].fExtended = floatx80_round_to_int(rFm);
161 break;
162
163 case SQT_CODE:
164 fpa11->fpreg[Fd].fExtended = floatx80_sqrt(rFm);
165 break;
166
167#if 0
168 case LOG_CODE:
169 fpa11->fpreg[Fd].fExtended = floatx80_log(rFm);
170 break;
171
172 case LGN_CODE:
173 fpa11->fpreg[Fd].fExtended = floatx80_ln(rFm);
174 break;
175
176 case EXP_CODE:
177 fpa11->fpreg[Fd].fExtended = floatx80_exp(rFm);
178 break;
179
180 case SIN_CODE:
181 fpa11->fpreg[Fd].fExtended = floatx80_sin(rFm);
182 break;
183
184 case COS_CODE:
185 fpa11->fpreg[Fd].fExtended = floatx80_cos(rFm);
186 break;
187
188 case TAN_CODE:
189 fpa11->fpreg[Fd].fExtended = floatx80_tan(rFm);
190 break;
191
192 case ASN_CODE:
193 fpa11->fpreg[Fd].fExtended = floatx80_arcsin(rFm);
194 break;
195
196 case ACS_CODE:
197 fpa11->fpreg[Fd].fExtended = floatx80_arccos(rFm);
198 break;
199
200 case ATN_CODE:
201 fpa11->fpreg[Fd].fExtended = floatx80_arctan(rFm);
202 break;
203#endif
204
205 case NRM_CODE:
206 break;
207
208 default:
209 {
210 nRc = 0;
211 }
212 }
213
214 if (0 != nRc) fpa11->fType[Fd] = typeExtended;
215 return nRc;
216}
217
218#if 0
219floatx80 floatx80_exp(floatx80 Fm)
220{
221//series
222}
223
224floatx80 floatx80_ln(floatx80 Fm)
225{
226//series
227}
228
229floatx80 floatx80_sin(floatx80 rFm)
230{
231//series
232}
233
234floatx80 floatx80_cos(floatx80 rFm)
235{
236//series
237}
238
239floatx80 floatx80_arcsin(floatx80 rFm)
240{
241//series
242}
243
244floatx80 floatx80_arctan(floatx80 rFm)
245{
246 //series
247}
248
249floatx80 floatx80_log(floatx80 rFm)
250{
251 return floatx80_div(floatx80_ln(rFm),getExtendedConstant(7));
252}
253
254floatx80 floatx80_tan(floatx80 rFm)
255{
256 return floatx80_div(floatx80_sin(rFm),floatx80_cos(rFm));
257}
258
259floatx80 floatx80_arccos(floatx80 rFm)
260{
261 //return floatx80_sub(halfPi,floatx80_arcsin(rFm));
262}
263
264floatx80 floatx80_pow(floatx80 rFn,floatx80 rFm)
265{
266 return floatx80_exp(floatx80_mul(rFm,floatx80_ln(rFn)));
267}
268
269floatx80 floatx80_pol(floatx80 rFn,floatx80 rFm)
270{
271 return floatx80_arctan(floatx80_div(rFn,rFm));
272}
273#endif
diff --git a/arch/arm26/nwfpe/fpa11.c b/arch/arm26/nwfpe/fpa11.c
new file mode 100644
index 000000000000..e954540a9464
--- /dev/null
+++ b/arch/arm26/nwfpe/fpa11.c
@@ -0,0 +1,221 @@
1/*
2 NetWinder Floating Point Emulator
3 (c) Rebel.COM, 1998,1999
4
5 Direct questions, comments to Scott Bambrough <scottb@netwinder.org>
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20*/
21
22#include "fpa11.h"
23#include "fpopcode.h"
24
25#include "fpmodule.h"
26#include "fpmodule.inl"
27
28#include <linux/compiler.h>
29#include <asm/system.h>
30
31/* forward declarations */
32unsigned int EmulateCPDO(const unsigned int);
33unsigned int EmulateCPDT(const unsigned int);
34unsigned int EmulateCPRT(const unsigned int);
35
36/* Reset the FPA11 chip. Called to initialize and reset the emulator. */
37void resetFPA11(void)
38{
39 int i;
40 FPA11 *fpa11 = GET_FPA11();
41
42 /* initialize the register type array */
43 for (i=0;i<=7;i++)
44 {
45 fpa11->fType[i] = typeNone;
46 }
47
48 /* FPSR: set system id to FP_EMULATOR, set AC, clear all other bits */
49 fpa11->fpsr = FP_EMULATOR | BIT_AC;
50
51 /* FPCR: set SB, AB and DA bits, clear all others */
52#if MAINTAIN_FPCR
53 fpa11->fpcr = MASK_RESET;
54#endif
55}
56
57void SetRoundingMode(const unsigned int opcode)
58{
59#if MAINTAIN_FPCR
60 FPA11 *fpa11 = GET_FPA11();
61 fpa11->fpcr &= ~MASK_ROUNDING_MODE;
62#endif
63 switch (opcode & MASK_ROUNDING_MODE)
64 {
65 default:
66 case ROUND_TO_NEAREST:
67 float_rounding_mode = float_round_nearest_even;
68#if MAINTAIN_FPCR
69 fpa11->fpcr |= ROUND_TO_NEAREST;
70#endif
71 break;
72
73 case ROUND_TO_PLUS_INFINITY:
74 float_rounding_mode = float_round_up;
75#if MAINTAIN_FPCR
76 fpa11->fpcr |= ROUND_TO_PLUS_INFINITY;
77#endif
78 break;
79
80 case ROUND_TO_MINUS_INFINITY:
81 float_rounding_mode = float_round_down;
82#if MAINTAIN_FPCR
83 fpa11->fpcr |= ROUND_TO_MINUS_INFINITY;
84#endif
85 break;
86
87 case ROUND_TO_ZERO:
88 float_rounding_mode = float_round_to_zero;
89#if MAINTAIN_FPCR
90 fpa11->fpcr |= ROUND_TO_ZERO;
91#endif
92 break;
93 }
94}
95
96void SetRoundingPrecision(const unsigned int opcode)
97{
98#if MAINTAIN_FPCR
99 FPA11 *fpa11 = GET_FPA11();
100 fpa11->fpcr &= ~MASK_ROUNDING_PRECISION;
101#endif
102 switch (opcode & MASK_ROUNDING_PRECISION)
103 {
104 case ROUND_SINGLE:
105 floatx80_rounding_precision = 32;
106#if MAINTAIN_FPCR
107 fpa11->fpcr |= ROUND_SINGLE;
108#endif
109 break;
110
111 case ROUND_DOUBLE:
112 floatx80_rounding_precision = 64;
113#if MAINTAIN_FPCR
114 fpa11->fpcr |= ROUND_DOUBLE;
115#endif
116 break;
117
118 case ROUND_EXTENDED:
119 floatx80_rounding_precision = 80;
120#if MAINTAIN_FPCR
121 fpa11->fpcr |= ROUND_EXTENDED;
122#endif
123 break;
124
125 default: floatx80_rounding_precision = 80;
126 }
127}
128
129void FPA11_CheckInit(void)
130{
131 FPA11 *fpa11 = GET_FPA11();
132 if (unlikely(fpa11->initflag == 0))
133 {
134 resetFPA11();
135 SetRoundingMode(ROUND_TO_NEAREST);
136 SetRoundingPrecision(ROUND_EXTENDED);
137 fpa11->initflag = 1;
138 }
139}
140
141/* Emulate the instruction in the opcode. */
142unsigned int EmulateAll(unsigned int opcode)
143{
144 unsigned int nRc = 1, code;
145
146 code = opcode & 0x00000f00;
147 if (code == 0x00000100 || code == 0x00000200)
148 {
149 /* For coprocessor 1 or 2 (FPA11) */
150 code = opcode & 0x0e000000;
151 if (code == 0x0e000000)
152 {
153 if (opcode & 0x00000010)
154 {
155 /* Emulate conversion opcodes. */
156 /* Emulate register transfer opcodes. */
157 /* Emulate comparison opcodes. */
158 nRc = EmulateCPRT(opcode);
159 }
160 else
161 {
162 /* Emulate monadic arithmetic opcodes. */
163 /* Emulate dyadic arithmetic opcodes. */
164 nRc = EmulateCPDO(opcode);
165 }
166 }
167 else if (code == 0x0c000000)
168 {
169 /* Emulate load/store opcodes. */
170 /* Emulate load/store multiple opcodes. */
171 nRc = EmulateCPDT(opcode);
172 }
173 else
174 {
175 /* Invalid instruction detected. Return FALSE. */
176 nRc = 0;
177 }
178 }
179
180 return(nRc);
181}
182
183#if 0
184unsigned int EmulateAll1(unsigned int opcode)
185{
186 switch ((opcode >> 24) & 0xf)
187 {
188 case 0xc:
189 case 0xd:
190 if ((opcode >> 20) & 0x1)
191 {
192 switch ((opcode >> 8) & 0xf)
193 {
194 case 0x1: return PerformLDF(opcode); break;
195 case 0x2: return PerformLFM(opcode); break;
196 default: return 0;
197 }
198 }
199 else
200 {
201 switch ((opcode >> 8) & 0xf)
202 {
203 case 0x1: return PerformSTF(opcode); break;
204 case 0x2: return PerformSFM(opcode); break;
205 default: return 0;
206 }
207 }
208 break;
209
210 case 0xe:
211 if (opcode & 0x10)
212 return EmulateCPDO(opcode);
213 else
214 return EmulateCPRT(opcode);
215 break;
216
217 default: return 0;
218 }
219}
220#endif
221
diff --git a/arch/arm26/nwfpe/fpa11.h b/arch/arm26/nwfpe/fpa11.h
new file mode 100644
index 000000000000..be09902a211d
--- /dev/null
+++ b/arch/arm26/nwfpe/fpa11.h
@@ -0,0 +1,87 @@
1/*
2 NetWinder Floating Point Emulator
3 (c) Rebel.com, 1998-1999
4
5 Direct questions, comments to Scott Bambrough <scottb@netwinder.org>
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20*/
21
22#ifndef __FPA11_H__
23#define __FPA11_H__
24
25#define GET_FPA11() ((FPA11 *)(&current_thread_info()->fpstate))
26
27/*
28 * The processes registers are always at the very top of the 8K
29 * stack+task struct. Use the same method as 'current' uses to
30 * reach them.
31 */
32register unsigned int *user_registers asm("sl");
33
34#define GET_USERREG() (user_registers)
35
36#include <linux/thread_info.h>
37
38/* includes */
39#include "fpsr.h" /* FP control and status register definitions */
40#include "softfloat.h"
41
42#define typeNone 0x00
43#define typeSingle 0x01
44#define typeDouble 0x02
45#define typeExtended 0x03
46
47/*
48 * This must be no more and no less than 12 bytes.
49 */
50typedef union tagFPREG {
51 floatx80 fExtended;
52 float64 fDouble;
53 float32 fSingle;
54} FPREG;
55
56/*
57 * FPA11 device model.
58 *
59 * This structure is exported to user space. Do not re-order.
60 * Only add new stuff to the end, and do not change the size of
61 * any element. Elements of this structure are used by user
62 * space, and must match struct user_fp in include/asm-arm/user.h.
63 * We include the byte offsets below for documentation purposes.
64 *
65 * The size of this structure and FPREG are checked by fpmodule.c
66 * on initialisation. If the rules have been broken, NWFPE will
67 * not initialise.
68 */
69typedef struct tagFPA11 {
70/* 0 */ FPREG fpreg[8]; /* 8 floating point registers */
71/* 96 */ FPSR fpsr; /* floating point status register */
72/* 100 */ FPCR fpcr; /* floating point control register */
73/* 104 */ unsigned char fType[8]; /* type of floating point value held in
74 floating point registers. One of none
75 single, double or extended. */
76/* 112 */ int initflag; /* this is special. The kernel guarantees
77 to set it to 0 when a thread is launched,
78 so we can use it to detect whether this
79 instance of the emulator needs to be
80 initialised. */
81} FPA11;
82
83extern void resetFPA11(void);
84extern void SetRoundingMode(const unsigned int);
85extern void SetRoundingPrecision(const unsigned int);
86
87#endif
diff --git a/arch/arm26/nwfpe/fpa11.inl b/arch/arm26/nwfpe/fpa11.inl
new file mode 100644
index 000000000000..1c45cba2de66
--- /dev/null
+++ b/arch/arm26/nwfpe/fpa11.inl
@@ -0,0 +1,51 @@
1/*
2 NetWinder Floating Point Emulator
3 (c) Rebel.COM, 1998,1999
4
5 Direct questions, comments to Scott Bambrough <scottb@netwinder.org>
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20*/
21
22#include "fpa11.h"
23
24/* Read and write floating point status register */
25extern __inline__ unsigned int readFPSR(void)
26{
27 FPA11 *fpa11 = GET_FPA11();
28 return(fpa11->fpsr);
29}
30
31extern __inline__ void writeFPSR(FPSR reg)
32{
33 FPA11 *fpa11 = GET_FPA11();
34 /* the sysid byte in the status register is readonly */
35 fpa11->fpsr = (fpa11->fpsr & MASK_SYSID) | (reg & ~MASK_SYSID);
36}
37
38/* Read and write floating point control register */
39extern __inline__ FPCR readFPCR(void)
40{
41 FPA11 *fpa11 = GET_FPA11();
42 /* clear SB, AB and DA bits before returning FPCR */
43 return(fpa11->fpcr & ~MASK_RFC);
44}
45
46extern __inline__ void writeFPCR(FPCR reg)
47{
48 FPA11 *fpa11 = GET_FPA11();
49 fpa11->fpcr &= ~MASK_WFC; /* clear SB, AB and DA bits */
50 fpa11->fpcr |= (reg & MASK_WFC); /* write SB, AB and DA bits */
51}
diff --git a/arch/arm26/nwfpe/fpa11_cpdo.c b/arch/arm26/nwfpe/fpa11_cpdo.c
new file mode 100644
index 000000000000..343a6b9fd520
--- /dev/null
+++ b/arch/arm26/nwfpe/fpa11_cpdo.c
@@ -0,0 +1,117 @@
1/*
2 NetWinder Floating Point Emulator
3 (c) Rebel.COM, 1998,1999
4
5 Direct questions, comments to Scott Bambrough <scottb@netwinder.org>
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20*/
21
22#include "fpa11.h"
23#include "fpopcode.h"
24
25unsigned int SingleCPDO(const unsigned int opcode);
26unsigned int DoubleCPDO(const unsigned int opcode);
27unsigned int ExtendedCPDO(const unsigned int opcode);
28
29unsigned int EmulateCPDO(const unsigned int opcode)
30{
31 FPA11 *fpa11 = GET_FPA11();
32 unsigned int Fd, nType, nDest, nRc = 1;
33
34 //printk("EmulateCPDO(0x%08x)\n",opcode);
35
36 /* Get the destination size. If not valid let Linux perform
37 an invalid instruction trap. */
38 nDest = getDestinationSize(opcode);
39 if (typeNone == nDest) return 0;
40
41 SetRoundingMode(opcode);
42
43 /* Compare the size of the operands in Fn and Fm.
44 Choose the largest size and perform operations in that size,
45 in order to make use of all the precision of the operands.
46 If Fm is a constant, we just grab a constant of a size
47 matching the size of the operand in Fn. */
48 if (MONADIC_INSTRUCTION(opcode))
49 nType = nDest;
50 else
51 nType = fpa11->fType[getFn(opcode)];
52
53 if (!CONSTANT_FM(opcode))
54 {
55 register unsigned int Fm = getFm(opcode);
56 if (nType < fpa11->fType[Fm])
57 {
58 nType = fpa11->fType[Fm];
59 }
60 }
61
62 switch (nType)
63 {
64 case typeSingle : nRc = SingleCPDO(opcode); break;
65 case typeDouble : nRc = DoubleCPDO(opcode); break;
66 case typeExtended : nRc = ExtendedCPDO(opcode); break;
67 default : nRc = 0;
68 }
69
70 /* If the operation succeeded, check to see if the result in the
71 destination register is the correct size. If not force it
72 to be. */
73 Fd = getFd(opcode);
74 nType = fpa11->fType[Fd];
75 if ((0 != nRc) && (nDest != nType))
76 {
77 switch (nDest)
78 {
79 case typeSingle:
80 {
81 if (typeDouble == nType)
82 fpa11->fpreg[Fd].fSingle =
83 float64_to_float32(fpa11->fpreg[Fd].fDouble);
84 else
85 fpa11->fpreg[Fd].fSingle =
86 floatx80_to_float32(fpa11->fpreg[Fd].fExtended);
87 }
88 break;
89
90 case typeDouble:
91 {
92 if (typeSingle == nType)
93 fpa11->fpreg[Fd].fDouble =
94 float32_to_float64(fpa11->fpreg[Fd].fSingle);
95 else
96 fpa11->fpreg[Fd].fDouble =
97 floatx80_to_float64(fpa11->fpreg[Fd].fExtended);
98 }
99 break;
100
101 case typeExtended:
102 {
103 if (typeSingle == nType)
104 fpa11->fpreg[Fd].fExtended =
105 float32_to_floatx80(fpa11->fpreg[Fd].fSingle);
106 else
107 fpa11->fpreg[Fd].fExtended =
108 float64_to_floatx80(fpa11->fpreg[Fd].fDouble);
109 }
110 break;
111 }
112
113 fpa11->fType[Fd] = nDest;
114 }
115
116 return nRc;
117}
diff --git a/arch/arm26/nwfpe/fpa11_cpdt.c b/arch/arm26/nwfpe/fpa11_cpdt.c
new file mode 100644
index 000000000000..e12db7c51a76
--- /dev/null
+++ b/arch/arm26/nwfpe/fpa11_cpdt.c
@@ -0,0 +1,368 @@
1/*
2 NetWinder Floating Point Emulator
3 (c) Rebel.com, 1998-1999
4 (c) Philip Blundell, 1998
5
6 Direct questions, comments to Scott Bambrough <scottb@netwinder.org>
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21*/
22
23#include "fpa11.h"
24#include "softfloat.h"
25#include "fpopcode.h"
26#include "fpmodule.h"
27#include "fpmodule.inl"
28
29#include <asm/uaccess.h>
30
31static inline
32void loadSingle(const unsigned int Fn,const unsigned int *pMem)
33{
34 FPA11 *fpa11 = GET_FPA11();
35 fpa11->fType[Fn] = typeSingle;
36 get_user(fpa11->fpreg[Fn].fSingle, pMem);
37}
38
39static inline
40void loadDouble(const unsigned int Fn,const unsigned int *pMem)
41{
42 FPA11 *fpa11 = GET_FPA11();
43 unsigned int *p;
44 p = (unsigned int*)&fpa11->fpreg[Fn].fDouble;
45 fpa11->fType[Fn] = typeDouble;
46 get_user(p[0], &pMem[1]);
47 get_user(p[1], &pMem[0]); /* sign & exponent */
48}
49
50static inline
51void loadExtended(const unsigned int Fn,const unsigned int *pMem)
52{
53 FPA11 *fpa11 = GET_FPA11();
54 unsigned int *p;
55 p = (unsigned int*)&fpa11->fpreg[Fn].fExtended;
56 fpa11->fType[Fn] = typeExtended;
57 get_user(p[0], &pMem[0]); /* sign & exponent */
58 get_user(p[1], &pMem[2]); /* ls bits */
59 get_user(p[2], &pMem[1]); /* ms bits */
60}
61
62static inline
63void loadMultiple(const unsigned int Fn,const unsigned int *pMem)
64{
65 FPA11 *fpa11 = GET_FPA11();
66 register unsigned int *p;
67 unsigned long x;
68
69 p = (unsigned int*)&(fpa11->fpreg[Fn]);
70 get_user(x, &pMem[0]);
71 fpa11->fType[Fn] = (x >> 14) & 0x00000003;
72
73 switch (fpa11->fType[Fn])
74 {
75 case typeSingle:
76 case typeDouble:
77 {
78 get_user(p[0], &pMem[2]); /* Single */
79 get_user(p[1], &pMem[1]); /* double msw */
80 p[2] = 0; /* empty */
81 }
82 break;
83
84 case typeExtended:
85 {
86 get_user(p[1], &pMem[2]);
87 get_user(p[2], &pMem[1]); /* msw */
88 p[0] = (x & 0x80003fff);
89 }
90 break;
91 }
92}
93
94static inline
95void storeSingle(const unsigned int Fn,unsigned int *pMem)
96{
97 FPA11 *fpa11 = GET_FPA11();
98 union
99 {
100 float32 f;
101 unsigned int i[1];
102 } val;
103
104 switch (fpa11->fType[Fn])
105 {
106 case typeDouble:
107 val.f = float64_to_float32(fpa11->fpreg[Fn].fDouble);
108 break;
109
110 case typeExtended:
111 val.f = floatx80_to_float32(fpa11->fpreg[Fn].fExtended);
112 break;
113
114 default: val.f = fpa11->fpreg[Fn].fSingle;
115 }
116
117 put_user(val.i[0], pMem);
118}
119
120static inline
121void storeDouble(const unsigned int Fn,unsigned int *pMem)
122{
123 FPA11 *fpa11 = GET_FPA11();
124 union
125 {
126 float64 f;
127 unsigned int i[2];
128 } val;
129
130 switch (fpa11->fType[Fn])
131 {
132 case typeSingle:
133 val.f = float32_to_float64(fpa11->fpreg[Fn].fSingle);
134 break;
135
136 case typeExtended:
137 val.f = floatx80_to_float64(fpa11->fpreg[Fn].fExtended);
138 break;
139
140 default: val.f = fpa11->fpreg[Fn].fDouble;
141 }
142
143 put_user(val.i[1], &pMem[0]); /* msw */
144 put_user(val.i[0], &pMem[1]); /* lsw */
145}
146
147static inline
148void storeExtended(const unsigned int Fn,unsigned int *pMem)
149{
150 FPA11 *fpa11 = GET_FPA11();
151 union
152 {
153 floatx80 f;
154 unsigned int i[3];
155 } val;
156
157 switch (fpa11->fType[Fn])
158 {
159 case typeSingle:
160 val.f = float32_to_floatx80(fpa11->fpreg[Fn].fSingle);
161 break;
162
163 case typeDouble:
164 val.f = float64_to_floatx80(fpa11->fpreg[Fn].fDouble);
165 break;
166
167 default: val.f = fpa11->fpreg[Fn].fExtended;
168 }
169
170 put_user(val.i[0], &pMem[0]); /* sign & exp */
171 put_user(val.i[1], &pMem[2]);
172 put_user(val.i[2], &pMem[1]); /* msw */
173}
174
175static inline
176void storeMultiple(const unsigned int Fn,unsigned int *pMem)
177{
178 FPA11 *fpa11 = GET_FPA11();
179 register unsigned int nType, *p;
180
181 p = (unsigned int*)&(fpa11->fpreg[Fn]);
182 nType = fpa11->fType[Fn];
183
184 switch (nType)
185 {
186 case typeSingle:
187 case typeDouble:
188 {
189 put_user(p[0], &pMem[2]); /* single */
190 put_user(p[1], &pMem[1]); /* double msw */
191 put_user(nType << 14, &pMem[0]);
192 }
193 break;
194
195 case typeExtended:
196 {
197 put_user(p[2], &pMem[1]); /* msw */
198 put_user(p[1], &pMem[2]);
199 put_user((p[0] & 0x80003fff) | (nType << 14), &pMem[0]);
200 }
201 break;
202 }
203}
204
205unsigned int PerformLDF(const unsigned int opcode)
206{
207 unsigned int *pBase, *pAddress, *pFinal, nRc = 1,
208 write_back = WRITE_BACK(opcode);
209
210 //printk("PerformLDF(0x%08x), Fd = 0x%08x\n",opcode,getFd(opcode));
211
212 pBase = (unsigned int*)readRegister(getRn(opcode));
213 if (REG_PC == getRn(opcode))
214 {
215 pBase += 2;
216 write_back = 0;
217 }
218
219 pFinal = pBase;
220 if (BIT_UP_SET(opcode))
221 pFinal += getOffset(opcode);
222 else
223 pFinal -= getOffset(opcode);
224
225 if (PREINDEXED(opcode)) pAddress = pFinal; else pAddress = pBase;
226
227 switch (opcode & MASK_TRANSFER_LENGTH)
228 {
229 case TRANSFER_SINGLE : loadSingle(getFd(opcode),pAddress); break;
230 case TRANSFER_DOUBLE : loadDouble(getFd(opcode),pAddress); break;
231 case TRANSFER_EXTENDED: loadExtended(getFd(opcode),pAddress); break;
232 default: nRc = 0;
233 }
234
235 if (write_back) writeRegister(getRn(opcode),(unsigned int)pFinal);
236 return nRc;
237}
238
239unsigned int PerformSTF(const unsigned int opcode)
240{
241 unsigned int *pBase, *pAddress, *pFinal, nRc = 1,
242 write_back = WRITE_BACK(opcode);
243
244 //printk("PerformSTF(0x%08x), Fd = 0x%08x\n",opcode,getFd(opcode));
245 SetRoundingMode(ROUND_TO_NEAREST);
246
247 pBase = (unsigned int*)readRegister(getRn(opcode));
248 if (REG_PC == getRn(opcode))
249 {
250 pBase += 2;
251 write_back = 0;
252 }
253
254 pFinal = pBase;
255 if (BIT_UP_SET(opcode))
256 pFinal += getOffset(opcode);
257 else
258 pFinal -= getOffset(opcode);
259
260 if (PREINDEXED(opcode)) pAddress = pFinal; else pAddress = pBase;
261
262 switch (opcode & MASK_TRANSFER_LENGTH)
263 {
264 case TRANSFER_SINGLE : storeSingle(getFd(opcode),pAddress); break;
265 case TRANSFER_DOUBLE : storeDouble(getFd(opcode),pAddress); break;
266 case TRANSFER_EXTENDED: storeExtended(getFd(opcode),pAddress); break;
267 default: nRc = 0;
268 }
269
270 if (write_back) writeRegister(getRn(opcode),(unsigned int)pFinal);
271 return nRc;
272}
273
274unsigned int PerformLFM(const unsigned int opcode)
275{
276 unsigned int i, Fd, *pBase, *pAddress, *pFinal,
277 write_back = WRITE_BACK(opcode);
278
279 pBase = (unsigned int*)readRegister(getRn(opcode));
280 if (REG_PC == getRn(opcode))
281 {
282 pBase += 2;
283 write_back = 0;
284 }
285
286 pFinal = pBase;
287 if (BIT_UP_SET(opcode))
288 pFinal += getOffset(opcode);
289 else
290 pFinal -= getOffset(opcode);
291
292 if (PREINDEXED(opcode)) pAddress = pFinal; else pAddress = pBase;
293
294 Fd = getFd(opcode);
295 for (i=getRegisterCount(opcode);i>0;i--)
296 {
297 loadMultiple(Fd,pAddress);
298 pAddress += 3; Fd++;
299 if (Fd == 8) Fd = 0;
300 }
301
302 if (write_back) writeRegister(getRn(opcode),(unsigned int)pFinal);
303 return 1;
304}
305
306unsigned int PerformSFM(const unsigned int opcode)
307{
308 unsigned int i, Fd, *pBase, *pAddress, *pFinal,
309 write_back = WRITE_BACK(opcode);
310
311 pBase = (unsigned int*)readRegister(getRn(opcode));
312 if (REG_PC == getRn(opcode))
313 {
314 pBase += 2;
315 write_back = 0;
316 }
317
318 pFinal = pBase;
319 if (BIT_UP_SET(opcode))
320 pFinal += getOffset(opcode);
321 else
322 pFinal -= getOffset(opcode);
323
324 if (PREINDEXED(opcode)) pAddress = pFinal; else pAddress = pBase;
325
326 Fd = getFd(opcode);
327 for (i=getRegisterCount(opcode);i>0;i--)
328 {
329 storeMultiple(Fd,pAddress);
330 pAddress += 3; Fd++;
331 if (Fd == 8) Fd = 0;
332 }
333
334 if (write_back) writeRegister(getRn(opcode),(unsigned int)pFinal);
335 return 1;
336}
337
338#if 1
339unsigned int EmulateCPDT(const unsigned int opcode)
340{
341 unsigned int nRc = 0;
342
343 //printk("EmulateCPDT(0x%08x)\n",opcode);
344
345 if (LDF_OP(opcode))
346 {
347 nRc = PerformLDF(opcode);
348 }
349 else if (LFM_OP(opcode))
350 {
351 nRc = PerformLFM(opcode);
352 }
353 else if (STF_OP(opcode))
354 {
355 nRc = PerformSTF(opcode);
356 }
357 else if (SFM_OP(opcode))
358 {
359 nRc = PerformSFM(opcode);
360 }
361 else
362 {
363 nRc = 0;
364 }
365
366 return nRc;
367}
368#endif
diff --git a/arch/arm26/nwfpe/fpa11_cprt.c b/arch/arm26/nwfpe/fpa11_cprt.c
new file mode 100644
index 000000000000..a201076c1f14
--- /dev/null
+++ b/arch/arm26/nwfpe/fpa11_cprt.c
@@ -0,0 +1,289 @@
1/*
2 NetWinder Floating Point Emulator
3 (c) Rebel.COM, 1998,1999
4 (c) Philip Blundell, 1999
5
6 Direct questions, comments to Scott Bambrough <scottb@netwinder.org>
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21*/
22
23#include "fpa11.h"
24#include "milieu.h"
25#include "softfloat.h"
26#include "fpopcode.h"
27#include "fpa11.inl"
28#include "fpmodule.h"
29#include "fpmodule.inl"
30
31extern flag floatx80_is_nan(floatx80);
32extern flag float64_is_nan( float64);
33extern flag float32_is_nan( float32);
34
35void SetRoundingMode(const unsigned int opcode);
36
37unsigned int PerformFLT(const unsigned int opcode);
38unsigned int PerformFIX(const unsigned int opcode);
39
40static unsigned int
41PerformComparison(const unsigned int opcode);
42
43unsigned int EmulateCPRT(const unsigned int opcode)
44{
45 unsigned int nRc = 1;
46
47 //printk("EmulateCPRT(0x%08x)\n",opcode);
48
49 if (opcode & 0x800000)
50 {
51 /* This is some variant of a comparison (PerformComparison will
52 sort out which one). Since most of the other CPRT
53 instructions are oddball cases of some sort or other it makes
54 sense to pull this out into a fast path. */
55 return PerformComparison(opcode);
56 }
57
58 /* Hint to GCC that we'd like a jump table rather than a load of CMPs */
59 switch ((opcode & 0x700000) >> 20)
60 {
61 case FLT_CODE >> 20: nRc = PerformFLT(opcode); break;
62 case FIX_CODE >> 20: nRc = PerformFIX(opcode); break;
63
64 case WFS_CODE >> 20: writeFPSR(readRegister(getRd(opcode))); break;
65 case RFS_CODE >> 20: writeRegister(getRd(opcode),readFPSR()); break;
66
67#if 0 /* We currently have no use for the FPCR, so there's no point
68 in emulating it. */
69 case WFC_CODE >> 20: writeFPCR(readRegister(getRd(opcode)));
70 case RFC_CODE >> 20: writeRegister(getRd(opcode),readFPCR()); break;
71#endif
72
73 default: nRc = 0;
74 }
75
76 return nRc;
77}
78
79unsigned int PerformFLT(const unsigned int opcode)
80{
81 FPA11 *fpa11 = GET_FPA11();
82
83 unsigned int nRc = 1;
84 SetRoundingMode(opcode);
85
86 switch (opcode & MASK_ROUNDING_PRECISION)
87 {
88 case ROUND_SINGLE:
89 {
90 fpa11->fType[getFn(opcode)] = typeSingle;
91 fpa11->fpreg[getFn(opcode)].fSingle =
92 int32_to_float32(readRegister(getRd(opcode)));
93 }
94 break;
95
96 case ROUND_DOUBLE:
97 {
98 fpa11->fType[getFn(opcode)] = typeDouble;
99 fpa11->fpreg[getFn(opcode)].fDouble =
100 int32_to_float64(readRegister(getRd(opcode)));
101 }
102 break;
103
104 case ROUND_EXTENDED:
105 {
106 fpa11->fType[getFn(opcode)] = typeExtended;
107 fpa11->fpreg[getFn(opcode)].fExtended =
108 int32_to_floatx80(readRegister(getRd(opcode)));
109 }
110 break;
111
112 default: nRc = 0;
113 }
114
115 return nRc;
116}
117
118unsigned int PerformFIX(const unsigned int opcode)
119{
120 FPA11 *fpa11 = GET_FPA11();
121 unsigned int nRc = 1;
122 unsigned int Fn = getFm(opcode);
123
124 SetRoundingMode(opcode);
125
126 switch (fpa11->fType[Fn])
127 {
128 case typeSingle:
129 {
130 writeRegister(getRd(opcode),
131 float32_to_int32(fpa11->fpreg[Fn].fSingle));
132 }
133 break;
134
135 case typeDouble:
136 {
137 writeRegister(getRd(opcode),
138 float64_to_int32(fpa11->fpreg[Fn].fDouble));
139 }
140 break;
141
142 case typeExtended:
143 {
144 writeRegister(getRd(opcode),
145 floatx80_to_int32(fpa11->fpreg[Fn].fExtended));
146 }
147 break;
148
149 default: nRc = 0;
150 }
151
152 return nRc;
153}
154
155
156static unsigned int __inline__
157PerformComparisonOperation(floatx80 Fn, floatx80 Fm)
158{
159 unsigned int flags = 0;
160
161 /* test for less than condition */
162 if (floatx80_lt(Fn,Fm))
163 {
164 flags |= CC_NEGATIVE;
165 }
166
167 /* test for equal condition */
168 if (floatx80_eq(Fn,Fm))
169 {
170 flags |= CC_ZERO;
171 }
172
173 /* test for greater than or equal condition */
174 if (floatx80_lt(Fm,Fn))
175 {
176 flags |= CC_CARRY;
177 }
178
179 writeConditionCodes(flags);
180 return 1;
181}
182
183/* This instruction sets the flags N, Z, C, V in the FPSR. */
184
185static unsigned int PerformComparison(const unsigned int opcode)
186{
187 FPA11 *fpa11 = GET_FPA11();
188 unsigned int Fn, Fm;
189 floatx80 rFn, rFm;
190 int e_flag = opcode & 0x400000; /* 1 if CxFE */
191 int n_flag = opcode & 0x200000; /* 1 if CNxx */
192 unsigned int flags = 0;
193
194 //printk("PerformComparison(0x%08x)\n",opcode);
195
196 Fn = getFn(opcode);
197 Fm = getFm(opcode);
198
199 /* Check for unordered condition and convert all operands to 80-bit
200 format.
201 ?? Might be some mileage in avoiding this conversion if possible.
202 Eg, if both operands are 32-bit, detect this and do a 32-bit
203 comparison (cheaper than an 80-bit one). */
204 switch (fpa11->fType[Fn])
205 {
206 case typeSingle:
207 //printk("single.\n");
208 if (float32_is_nan(fpa11->fpreg[Fn].fSingle))
209 goto unordered;
210 rFn = float32_to_floatx80(fpa11->fpreg[Fn].fSingle);
211 break;
212
213 case typeDouble:
214 //printk("double.\n");
215 if (float64_is_nan(fpa11->fpreg[Fn].fDouble))
216 goto unordered;
217 rFn = float64_to_floatx80(fpa11->fpreg[Fn].fDouble);
218 break;
219
220 case typeExtended:
221 //printk("extended.\n");
222 if (floatx80_is_nan(fpa11->fpreg[Fn].fExtended))
223 goto unordered;
224 rFn = fpa11->fpreg[Fn].fExtended;
225 break;
226
227 default: return 0;
228 }
229
230 if (CONSTANT_FM(opcode))
231 {
232 //printk("Fm is a constant: #%d.\n",Fm);
233 rFm = getExtendedConstant(Fm);
234 if (floatx80_is_nan(rFm))
235 goto unordered;
236 }
237 else
238 {
239 //printk("Fm = r%d which contains a ",Fm);
240 switch (fpa11->fType[Fm])
241 {
242 case typeSingle:
243 //printk("single.\n");
244 if (float32_is_nan(fpa11->fpreg[Fm].fSingle))
245 goto unordered;
246 rFm = float32_to_floatx80(fpa11->fpreg[Fm].fSingle);
247 break;
248
249 case typeDouble:
250 //printk("double.\n");
251 if (float64_is_nan(fpa11->fpreg[Fm].fDouble))
252 goto unordered;
253 rFm = float64_to_floatx80(fpa11->fpreg[Fm].fDouble);
254 break;
255
256 case typeExtended:
257 //printk("extended.\n");
258 if (floatx80_is_nan(fpa11->fpreg[Fm].fExtended))
259 goto unordered;
260 rFm = fpa11->fpreg[Fm].fExtended;
261 break;
262
263 default: return 0;
264 }
265 }
266
267 if (n_flag)
268 {
269 rFm.high ^= 0x8000;
270 }
271
272 return PerformComparisonOperation(rFn,rFm);
273
274 unordered:
275 /* ?? The FPA data sheet is pretty vague about this, in particular
276 about whether the non-E comparisons can ever raise exceptions.
277 This implementation is based on a combination of what it says in
278 the data sheet, observation of how the Acorn emulator actually
279 behaves (and how programs expect it to) and guesswork. */
280 flags |= CC_OVERFLOW;
281 flags &= ~(CC_ZERO | CC_NEGATIVE);
282
283 if (BIT_AC & readFPSR()) flags |= CC_CARRY;
284
285 if (e_flag) float_raise(float_flag_invalid);
286
287 writeConditionCodes(flags);
288 return 1;
289}
diff --git a/arch/arm26/nwfpe/fpmodule.c b/arch/arm26/nwfpe/fpmodule.c
new file mode 100644
index 000000000000..528fa710aa34
--- /dev/null
+++ b/arch/arm26/nwfpe/fpmodule.c
@@ -0,0 +1,182 @@
1
2/*
3 NetWinder Floating Point Emulator
4 (c) Rebel.com, 1998-1999
5 (c) Philip Blundell, 1998-1999
6
7 Direct questions, comments to Scott Bambrough <scottb@netwinder.org>
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22*/
23
24#include "fpa11.h"
25
26#include <linux/module.h>
27#include <linux/version.h>
28#include <linux/config.h>
29
30/* XXX */
31#include <linux/errno.h>
32#include <linux/types.h>
33#include <linux/kernel.h>
34#include <linux/signal.h>
35#include <linux/sched.h>
36#include <linux/init.h>
37/* XXX */
38
39#include "softfloat.h"
40#include "fpopcode.h"
41#include "fpmodule.h"
42#include "fpa11.inl"
43
44/* kernel symbols required for signal handling */
45typedef struct task_struct* PTASK;
46
47#ifdef MODULE
48void fp_send_sig(unsigned long sig, PTASK p, int priv);
49#if LINUX_VERSION_CODE > 0x20115
50MODULE_AUTHOR("Scott Bambrough <scottb@rebel.com>");
51MODULE_DESCRIPTION("NWFPE floating point emulator");
52#endif
53
54#else
55#define fp_send_sig send_sig
56#define kern_fp_enter fp_enter
57
58extern char fpe_type[];
59#endif
60
61/* kernel function prototypes required */
62void fp_setup(void);
63
64/* external declarations for saved kernel symbols */
65extern void (*kern_fp_enter)(void);
66
67/* Original value of fp_enter from kernel before patched by fpe_init. */
68static void (*orig_fp_enter)(void);
69
70/* forward declarations */
71extern void nwfpe_enter(void);
72
73#ifdef MODULE
74/*
75 * Return 0 if we can be unloaded. This can only happen if
76 * kern_fp_enter is still pointing at nwfpe_enter
77 */
78static int fpe_unload(void)
79{
80 return (kern_fp_enter == nwfpe_enter) ? 0 : 1;
81}
82#endif
83
84static int __init fpe_init(void)
85{
86 if (sizeof(FPA11) > sizeof(union fp_state)) {
87 printk(KERN_ERR "nwfpe: bad structure size\n");
88 return -EINVAL;
89 }
90
91 if (sizeof(FPREG) != 12) {
92 printk(KERN_ERR "nwfpe: bad register size\n");
93 return -EINVAL;
94 }
95
96#ifdef MODULE
97 if (!mod_member_present(&__this_module, can_unload))
98 return -EINVAL;
99 __this_module.can_unload = fpe_unload;
100#else
101 if (fpe_type[0] && strcmp(fpe_type, "nwfpe"))
102 return 0;
103#endif
104
105 /* Display title, version and copyright information. */
106 printk(KERN_WARNING "NetWinder Floating Point Emulator V0.95 "
107 "(c) 1998-1999 Rebel.com\n");
108
109 /* Save pointer to the old FP handler and then patch ourselves in */
110 orig_fp_enter = kern_fp_enter;
111 kern_fp_enter = nwfpe_enter;
112
113 return 0;
114}
115
116static void __exit fpe_exit(void)
117{
118 /* Restore the values we saved earlier. */
119 kern_fp_enter = orig_fp_enter;
120}
121
122/*
123ScottB: November 4, 1998
124
125Moved this function out of softfloat-specialize into fpmodule.c.
126This effectively isolates all the changes required for integrating with the
127Linux kernel into fpmodule.c. Porting to NetBSD should only require modifying
128fpmodule.c to integrate with the NetBSD kernel (I hope!).
129
130[1/1/99: Not quite true any more unfortunately. There is Linux-specific
131code to access data in user space in some other source files at the
132moment (grep for get_user / put_user calls). --philb]
133
134float_exception_flags is a global variable in SoftFloat.
135
136This function is called by the SoftFloat routines to raise a floating
137point exception. We check the trap enable byte in the FPSR, and raise
138a SIGFPE exception if necessary. If not the relevant bits in the
139cumulative exceptions flag byte are set and we return.
140*/
141
142void float_raise(signed char flags)
143{
144 register unsigned int fpsr, cumulativeTraps;
145
146#ifdef CONFIG_DEBUG_USER
147 printk(KERN_DEBUG "NWFPE: %s[%d] takes exception %08x at %p from %08x\n",
148 current->comm, current->pid, flags,
149 __builtin_return_address(0), GET_USERREG()[15]);
150#endif
151
152 /* Keep SoftFloat exception flags up to date. */
153 float_exception_flags |= flags;
154
155 /* Read fpsr and initialize the cumulativeTraps. */
156 fpsr = readFPSR();
157 cumulativeTraps = 0;
158
159 /* For each type of exception, the cumulative trap exception bit is only
160 set if the corresponding trap enable bit is not set. */
161 if ((!(fpsr & BIT_IXE)) && (flags & BIT_IXC))
162 cumulativeTraps |= BIT_IXC;
163 if ((!(fpsr & BIT_UFE)) && (flags & BIT_UFC))
164 cumulativeTraps |= BIT_UFC;
165 if ((!(fpsr & BIT_OFE)) && (flags & BIT_OFC))
166 cumulativeTraps |= BIT_OFC;
167 if ((!(fpsr & BIT_DZE)) && (flags & BIT_DZC))
168 cumulativeTraps |= BIT_DZC;
169 if ((!(fpsr & BIT_IOE)) && (flags & BIT_IOC))
170 cumulativeTraps |= BIT_IOC;
171
172 /* Set the cumulative exceptions flags. */
173 if (cumulativeTraps)
174 writeFPSR(fpsr | cumulativeTraps);
175
176 /* Raise an exception if necessary. */
177 if (fpsr & (flags << 16))
178 fp_send_sig(SIGFPE, current, 1);
179}
180
181module_init(fpe_init);
182module_exit(fpe_exit);
diff --git a/arch/arm26/nwfpe/fpmodule.h b/arch/arm26/nwfpe/fpmodule.h
new file mode 100644
index 000000000000..ef71aab46a32
--- /dev/null
+++ b/arch/arm26/nwfpe/fpmodule.h
@@ -0,0 +1,47 @@
1/*
2 NetWinder Floating Point Emulator
3 (c) Rebel.com, 1998-1999
4
5 Direct questions, comments to Scott Bambrough <scottb@netwinder.org>
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20*/
21
22#ifndef __FPMODULE_H__
23#define __FPMODULE_H__
24
25#include <linux/config.h>
26
27#define REG_ORIG_R0 16
28#define REG_CPSR 15
29#define REG_PC 15
30#define REG_LR 14
31#define REG_SP 13
32#define REG_IP 12
33#define REG_FP 11
34#define REG_R10 10
35#define REG_R9 9
36#define REG_R9 9
37#define REG_R8 8
38#define REG_R7 7
39#define REG_R6 6
40#define REG_R5 5
41#define REG_R4 4
42#define REG_R3 3
43#define REG_R2 2
44#define REG_R1 1
45#define REG_R0 0
46
47#endif
diff --git a/arch/arm26/nwfpe/fpmodule.inl b/arch/arm26/nwfpe/fpmodule.inl
new file mode 100644
index 000000000000..ef228378ffaf
--- /dev/null
+++ b/arch/arm26/nwfpe/fpmodule.inl
@@ -0,0 +1,84 @@
1/*
2 NetWinder Floating Point Emulator
3 (c) Rebel.COM, 1998,1999
4
5 Direct questions, comments to Scott Bambrough <scottb@netwinder.org>
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20*/
21
22extern __inline__
23unsigned int readRegister(const unsigned int nReg)
24{
25 /* Note: The CPU thinks it has dealt with the current instruction. As
26 a result the program counter has been advanced to the next
27 instruction, and points 4 bytes beyond the actual instruction
28 that caused the invalid instruction trap to occur. We adjust
29 for this in this routine. LDF/STF instructions with Rn = PC
30 depend on the PC being correct, as they use PC+8 in their
31 address calculations. */
32 unsigned int *userRegisters = GET_USERREG();
33 unsigned int val = userRegisters[nReg];
34 if (REG_PC == nReg) val -= 4;
35 return val;
36}
37
38extern __inline__
39void writeRegister(const unsigned int nReg, const unsigned int val)
40{
41 unsigned int *userRegisters = GET_USERREG();
42 userRegisters[nReg] = val;
43}
44
45extern __inline__
46unsigned int readCPSR(void)
47{
48 return(readRegister(REG_CPSR));
49}
50
51extern __inline__
52void writeCPSR(const unsigned int val)
53{
54 writeRegister(REG_CPSR,val);
55}
56
57extern __inline__
58unsigned int readConditionCodes(void)
59{
60#ifdef __FPEM_TEST__
61 return(0);
62#else
63 return(readCPSR() & CC_MASK);
64#endif
65}
66
67extern __inline__
68void writeConditionCodes(const unsigned int val)
69{
70 unsigned int *userRegisters = GET_USERREG();
71 unsigned int rval;
72 /*
73 * Operate directly on userRegisters since
74 * the CPSR may be the PC register itself.
75 */
76 rval = userRegisters[REG_CPSR] & ~CC_MASK;
77 userRegisters[REG_CPSR] = rval | (val & CC_MASK);
78}
79
80extern __inline__
81unsigned int readMemoryInt(unsigned int *pMem)
82{
83 return *pMem;
84}
diff --git a/arch/arm26/nwfpe/fpopcode.c b/arch/arm26/nwfpe/fpopcode.c
new file mode 100644
index 000000000000..d81ddd188322
--- /dev/null
+++ b/arch/arm26/nwfpe/fpopcode.c
@@ -0,0 +1,148 @@
1/*
2 NetWinder Floating Point Emulator
3 (c) Rebel.COM, 1998,1999
4
5 Direct questions, comments to Scott Bambrough <scottb@netwinder.org>
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20*/
21
22#include "fpa11.h"
23#include "softfloat.h"
24#include "fpopcode.h"
25#include "fpsr.h"
26#include "fpmodule.h"
27#include "fpmodule.inl"
28
29const floatx80 floatx80Constant[] = {
30 { 0x0000, 0x0000000000000000ULL}, /* extended 0.0 */
31 { 0x3fff, 0x8000000000000000ULL}, /* extended 1.0 */
32 { 0x4000, 0x8000000000000000ULL}, /* extended 2.0 */
33 { 0x4000, 0xc000000000000000ULL}, /* extended 3.0 */
34 { 0x4001, 0x8000000000000000ULL}, /* extended 4.0 */
35 { 0x4001, 0xa000000000000000ULL}, /* extended 5.0 */
36 { 0x3ffe, 0x8000000000000000ULL}, /* extended 0.5 */
37 { 0x4002, 0xa000000000000000ULL} /* extended 10.0 */
38};
39
40const float64 float64Constant[] = {
41 0x0000000000000000ULL, /* double 0.0 */
42 0x3ff0000000000000ULL, /* double 1.0 */
43 0x4000000000000000ULL, /* double 2.0 */
44 0x4008000000000000ULL, /* double 3.0 */
45 0x4010000000000000ULL, /* double 4.0 */
46 0x4014000000000000ULL, /* double 5.0 */
47 0x3fe0000000000000ULL, /* double 0.5 */
48 0x4024000000000000ULL /* double 10.0 */
49};
50
51const float32 float32Constant[] = {
52 0x00000000, /* single 0.0 */
53 0x3f800000, /* single 1.0 */
54 0x40000000, /* single 2.0 */
55 0x40400000, /* single 3.0 */
56 0x40800000, /* single 4.0 */
57 0x40a00000, /* single 5.0 */
58 0x3f000000, /* single 0.5 */
59 0x41200000 /* single 10.0 */
60};
61
62unsigned int getTransferLength(const unsigned int opcode)
63{
64 unsigned int nRc;
65
66 switch (opcode & MASK_TRANSFER_LENGTH)
67 {
68 case 0x00000000: nRc = 1; break; /* single precision */
69 case 0x00008000: nRc = 2; break; /* double precision */
70 case 0x00400000: nRc = 3; break; /* extended precision */
71 default: nRc = 0;
72 }
73
74 return(nRc);
75}
76
77unsigned int getRegisterCount(const unsigned int opcode)
78{
79 unsigned int nRc;
80
81 switch (opcode & MASK_REGISTER_COUNT)
82 {
83 case 0x00000000: nRc = 4; break;
84 case 0x00008000: nRc = 1; break;
85 case 0x00400000: nRc = 2; break;
86 case 0x00408000: nRc = 3; break;
87 default: nRc = 0;
88 }
89
90 return(nRc);
91}
92
93unsigned int getRoundingPrecision(const unsigned int opcode)
94{
95 unsigned int nRc;
96
97 switch (opcode & MASK_ROUNDING_PRECISION)
98 {
99 case 0x00000000: nRc = 1; break;
100 case 0x00000080: nRc = 2; break;
101 case 0x00080000: nRc = 3; break;
102 default: nRc = 0;
103 }
104
105 return(nRc);
106}
107
108unsigned int getDestinationSize(const unsigned int opcode)
109{
110 unsigned int nRc;
111
112 switch (opcode & MASK_DESTINATION_SIZE)
113 {
114 case 0x00000000: nRc = typeSingle; break;
115 case 0x00000080: nRc = typeDouble; break;
116 case 0x00080000: nRc = typeExtended; break;
117 default: nRc = typeNone;
118 }
119
120 return(nRc);
121}
122
123/* condition code lookup table
124 index into the table is test code: EQ, NE, ... LT, GT, AL, NV
125 bit position in short is condition code: NZCV */
126static const unsigned short aCC[16] = {
127 0xF0F0, // EQ == Z set
128 0x0F0F, // NE
129 0xCCCC, // CS == C set
130 0x3333, // CC
131 0xFF00, // MI == N set
132 0x00FF, // PL
133 0xAAAA, // VS == V set
134 0x5555, // VC
135 0x0C0C, // HI == C set && Z clear
136 0xF3F3, // LS == C clear || Z set
137 0xAA55, // GE == (N==V)
138 0x55AA, // LT == (N!=V)
139 0x0A05, // GT == (!Z && (N==V))
140 0xF5FA, // LE == (Z || (N!=V))
141 0xFFFF, // AL always
142 0 // NV
143};
144
145unsigned int checkCondition(const unsigned int opcode, const unsigned int ccodes)
146{
147 return (aCC[opcode>>28] >> (ccodes>>28)) & 1;
148}
diff --git a/arch/arm26/nwfpe/fpopcode.h b/arch/arm26/nwfpe/fpopcode.h
new file mode 100644
index 000000000000..13c7419262ab
--- /dev/null
+++ b/arch/arm26/nwfpe/fpopcode.h
@@ -0,0 +1,390 @@
1/*
2 NetWinder Floating Point Emulator
3 (c) Rebel.COM, 1998,1999
4
5 Direct questions, comments to Scott Bambrough <scottb@netwinder.org>
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20*/
21
22#ifndef __FPOPCODE_H__
23#define __FPOPCODE_H__
24
25/*
26ARM Floating Point Instruction Classes
27| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
28|c o n d|1 1 0 P|U|u|W|L| Rn |v| Fd |0|0|0|1| o f f s e t | CPDT
29|c o n d|1 1 0 P|U|w|W|L| Rn |x| Fd |0|0|0|1| o f f s e t | CPDT
30| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
31|c o n d|1 1 1 0|a|b|c|d|e| Fn |j| Fd |0|0|0|1|f|g|h|0|i| Fm | CPDO
32|c o n d|1 1 1 0|a|b|c|L|e| Fn | Rd |0|0|0|1|f|g|h|1|i| Fm | CPRT
33|c o n d|1 1 1 0|a|b|c|1|e| Fn |1|1|1|1|0|0|0|1|f|g|h|1|i| Fm | comparisons
34| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
35
36CPDT data transfer instructions
37 LDF, STF, LFM, SFM
38
39CPDO dyadic arithmetic instructions
40 ADF, MUF, SUF, RSF, DVF, RDF,
41 POW, RPW, RMF, FML, FDV, FRD, POL
42
43CPDO monadic arithmetic instructions
44 MVF, MNF, ABS, RND, SQT, LOG, LGN, EXP,
45 SIN, COS, TAN, ASN, ACS, ATN, URD, NRM
46
47CPRT joint arithmetic/data transfer instructions
48 FIX (arithmetic followed by load/store)
49 FLT (load/store followed by arithmetic)
50 CMF, CNF CMFE, CNFE (comparisons)
51 WFS, RFS (write/read floating point status register)
52 WFC, RFC (write/read floating point control register)
53
54cond condition codes
55P pre/post index bit: 0 = postindex, 1 = preindex
56U up/down bit: 0 = stack grows down, 1 = stack grows up
57W write back bit: 1 = update base register (Rn)
58L load/store bit: 0 = store, 1 = load
59Rn base register
60Rd destination/source register
61Fd floating point destination register
62Fn floating point source register
63Fm floating point source register or floating point constant
64
65uv transfer length (TABLE 1)
66wx register count (TABLE 2)
67abcd arithmetic opcode (TABLES 3 & 4)
68ef destination size (rounding precision) (TABLE 5)
69gh rounding mode (TABLE 6)
70j dyadic/monadic bit: 0 = dyadic, 1 = monadic
71i constant bit: 1 = constant (TABLE 6)
72*/
73
74/*
75TABLE 1
76+-------------------------+---+---+---------+---------+
77| Precision | u | v | FPSR.EP | length |
78+-------------------------+---+---+---------+---------+
79| Single | 0 ü 0 | x | 1 words |
80| Double | 1 ü 1 | x | 2 words |
81| Extended | 1 ü 1 | x | 3 words |
82| Packed decimal | 1 ü 1 | 0 | 3 words |
83| Expanded packed decimal | 1 ü 1 | 1 | 4 words |
84+-------------------------+---+---+---------+---------+
85Note: x = don't care
86*/
87
88/*
89TABLE 2
90+---+---+---------------------------------+
91| w | x | Number of registers to transfer |
92+---+---+---------------------------------+
93| 0 ü 1 | 1 |
94| 1 ü 0 | 2 |
95| 1 ü 1 | 3 |
96| 0 ü 0 | 4 |
97+---+---+---------------------------------+
98*/
99
100/*
101TABLE 3: Dyadic Floating Point Opcodes
102+---+---+---+---+----------+-----------------------+-----------------------+
103| a | b | c | d | Mnemonic | Description | Operation |
104+---+---+---+---+----------+-----------------------+-----------------------+
105| 0 | 0 | 0 | 0 | ADF | Add | Fd := Fn + Fm |
106| 0 | 0 | 0 | 1 | MUF | Multiply | Fd := Fn * Fm |
107| 0 | 0 | 1 | 0 | SUF | Subtract | Fd := Fn - Fm |
108| 0 | 0 | 1 | 1 | RSF | Reverse subtract | Fd := Fm - Fn |
109| 0 | 1 | 0 | 0 | DVF | Divide | Fd := Fn / Fm |
110| 0 | 1 | 0 | 1 | RDF | Reverse divide | Fd := Fm / Fn |
111| 0 | 1 | 1 | 0 | POW | Power | Fd := Fn ^ Fm |
112| 0 | 1 | 1 | 1 | RPW | Reverse power | Fd := Fm ^ Fn |
113| 1 | 0 | 0 | 0 | RMF | Remainder | Fd := IEEE rem(Fn/Fm) |
114| 1 | 0 | 0 | 1 | FML | Fast Multiply | Fd := Fn * Fm |
115| 1 | 0 | 1 | 0 | FDV | Fast Divide | Fd := Fn / Fm |
116| 1 | 0 | 1 | 1 | FRD | Fast reverse divide | Fd := Fm / Fn |
117| 1 | 1 | 0 | 0 | POL | Polar angle (ArcTan2) | Fd := arctan2(Fn,Fm) |
118| 1 | 1 | 0 | 1 | | undefined instruction | trap |
119| 1 | 1 | 1 | 0 | | undefined instruction | trap |
120| 1 | 1 | 1 | 1 | | undefined instruction | trap |
121+---+---+---+---+----------+-----------------------+-----------------------+
122Note: POW, RPW, POL are deprecated, and are available for backwards
123 compatibility only.
124*/
125
126/*
127TABLE 4: Monadic Floating Point Opcodes
128+---+---+---+---+----------+-----------------------+-----------------------+
129| a | b | c | d | Mnemonic | Description | Operation |
130+---+---+---+---+----------+-----------------------+-----------------------+
131| 0 | 0 | 0 | 0 | MVF | Move | Fd := Fm |
132| 0 | 0 | 0 | 1 | MNF | Move negated | Fd := - Fm |
133| 0 | 0 | 1 | 0 | ABS | Absolute value | Fd := abs(Fm) |
134| 0 | 0 | 1 | 1 | RND | Round to integer | Fd := int(Fm) |
135| 0 | 1 | 0 | 0 | SQT | Square root | Fd := sqrt(Fm) |
136| 0 | 1 | 0 | 1 | LOG | Log base 10 | Fd := log10(Fm) |
137| 0 | 1 | 1 | 0 | LGN | Log base e | Fd := ln(Fm) |
138| 0 | 1 | 1 | 1 | EXP | Exponent | Fd := e ^ Fm |
139| 1 | 0 | 0 | 0 | SIN | Sine | Fd := sin(Fm) |
140| 1 | 0 | 0 | 1 | COS | Cosine | Fd := cos(Fm) |
141| 1 | 0 | 1 | 0 | TAN | Tangent | Fd := tan(Fm) |
142| 1 | 0 | 1 | 1 | ASN | Arc Sine | Fd := arcsin(Fm) |
143| 1 | 1 | 0 | 0 | ACS | Arc Cosine | Fd := arccos(Fm) |
144| 1 | 1 | 0 | 1 | ATN | Arc Tangent | Fd := arctan(Fm) |
145| 1 | 1 | 1 | 0 | URD | Unnormalized round | Fd := int(Fm) |
146| 1 | 1 | 1 | 1 | NRM | Normalize | Fd := norm(Fm) |
147+---+---+---+---+----------+-----------------------+-----------------------+
148Note: LOG, LGN, EXP, SIN, COS, TAN, ASN, ACS, ATN are deprecated, and are
149 available for backwards compatibility only.
150*/
151
152/*
153TABLE 5
154+-------------------------+---+---+
155| Rounding Precision | e | f |
156+-------------------------+---+---+
157| IEEE Single precision | 0 ü 0 |
158| IEEE Double precision | 0 ü 1 |
159| IEEE Extended precision | 1 ü 0 |
160| undefined (trap) | 1 ü 1 |
161+-------------------------+---+---+
162*/
163
164/*
165TABLE 5
166+---------------------------------+---+---+
167| Rounding Mode | g | h |
168+---------------------------------+---+---+
169| Round to nearest (default) | 0 ü 0 |
170| Round toward plus infinity | 0 ü 1 |
171| Round toward negative infinity | 1 ü 0 |
172| Round toward zero | 1 ü 1 |
173+---------------------------------+---+---+
174*/
175
176/*
177===
178=== Definitions for load and store instructions
179===
180*/
181
182/* bit masks */
183#define BIT_PREINDEX 0x01000000
184#define BIT_UP 0x00800000
185#define BIT_WRITE_BACK 0x00200000
186#define BIT_LOAD 0x00100000
187
188/* masks for load/store */
189#define MASK_CPDT 0x0c000000 /* data processing opcode */
190#define MASK_OFFSET 0x000000ff
191#define MASK_TRANSFER_LENGTH 0x00408000
192#define MASK_REGISTER_COUNT MASK_TRANSFER_LENGTH
193#define MASK_COPROCESSOR 0x00000f00
194
195/* Tests for transfer length */
196#define TRANSFER_SINGLE 0x00000000
197#define TRANSFER_DOUBLE 0x00008000
198#define TRANSFER_EXTENDED 0x00400000
199#define TRANSFER_PACKED MASK_TRANSFER_LENGTH
200
201/* Get the coprocessor number from the opcode. */
202#define getCoprocessorNumber(opcode) ((opcode & MASK_COPROCESSOR) >> 8)
203
204/* Get the offset from the opcode. */
205#define getOffset(opcode) (opcode & MASK_OFFSET)
206
207/* Tests for specific data transfer load/store opcodes. */
208#define TEST_OPCODE(opcode,mask) (((opcode) & (mask)) == (mask))
209
210#define LOAD_OP(opcode) TEST_OPCODE((opcode),MASK_CPDT | BIT_LOAD)
211#define STORE_OP(opcode) ((opcode & (MASK_CPDT | BIT_LOAD)) == MASK_CPDT)
212
213#define LDF_OP(opcode) (LOAD_OP(opcode) && (getCoprocessorNumber(opcode) == 1))
214#define LFM_OP(opcode) (LOAD_OP(opcode) && (getCoprocessorNumber(opcode) == 2))
215#define STF_OP(opcode) (STORE_OP(opcode) && (getCoprocessorNumber(opcode) == 1))
216#define SFM_OP(opcode) (STORE_OP(opcode) && (getCoprocessorNumber(opcode) == 2))
217
218#define PREINDEXED(opcode) ((opcode & BIT_PREINDEX) != 0)
219#define POSTINDEXED(opcode) ((opcode & BIT_PREINDEX) == 0)
220#define BIT_UP_SET(opcode) ((opcode & BIT_UP) != 0)
221#define BIT_UP_CLEAR(opcode) ((opcode & BIT_DOWN) == 0)
222#define WRITE_BACK(opcode) ((opcode & BIT_WRITE_BACK) != 0)
223#define LOAD(opcode) ((opcode & BIT_LOAD) != 0)
224#define STORE(opcode) ((opcode & BIT_LOAD) == 0)
225
226/*
227===
228=== Definitions for arithmetic instructions
229===
230*/
231/* bit masks */
232#define BIT_MONADIC 0x00008000
233#define BIT_CONSTANT 0x00000008
234
235#define CONSTANT_FM(opcode) ((opcode & BIT_CONSTANT) != 0)
236#define MONADIC_INSTRUCTION(opcode) ((opcode & BIT_MONADIC) != 0)
237
238/* instruction identification masks */
239#define MASK_CPDO 0x0e000000 /* arithmetic opcode */
240#define MASK_ARITHMETIC_OPCODE 0x00f08000
241#define MASK_DESTINATION_SIZE 0x00080080
242
243/* dyadic arithmetic opcodes. */
244#define ADF_CODE 0x00000000
245#define MUF_CODE 0x00100000
246#define SUF_CODE 0x00200000
247#define RSF_CODE 0x00300000
248#define DVF_CODE 0x00400000
249#define RDF_CODE 0x00500000
250#define POW_CODE 0x00600000
251#define RPW_CODE 0x00700000
252#define RMF_CODE 0x00800000
253#define FML_CODE 0x00900000
254#define FDV_CODE 0x00a00000
255#define FRD_CODE 0x00b00000
256#define POL_CODE 0x00c00000
257/* 0x00d00000 is an invalid dyadic arithmetic opcode */
258/* 0x00e00000 is an invalid dyadic arithmetic opcode */
259/* 0x00f00000 is an invalid dyadic arithmetic opcode */
260
261/* monadic arithmetic opcodes. */
262#define MVF_CODE 0x00008000
263#define MNF_CODE 0x00108000
264#define ABS_CODE 0x00208000
265#define RND_CODE 0x00308000
266#define SQT_CODE 0x00408000
267#define LOG_CODE 0x00508000
268#define LGN_CODE 0x00608000
269#define EXP_CODE 0x00708000
270#define SIN_CODE 0x00808000
271#define COS_CODE 0x00908000
272#define TAN_CODE 0x00a08000
273#define ASN_CODE 0x00b08000
274#define ACS_CODE 0x00c08000
275#define ATN_CODE 0x00d08000
276#define URD_CODE 0x00e08000
277#define NRM_CODE 0x00f08000
278
279/*
280===
281=== Definitions for register transfer and comparison instructions
282===
283*/
284
285#define MASK_CPRT 0x0e000010 /* register transfer opcode */
286#define MASK_CPRT_CODE 0x00f00000
287#define FLT_CODE 0x00000000
288#define FIX_CODE 0x00100000
289#define WFS_CODE 0x00200000
290#define RFS_CODE 0x00300000
291#define WFC_CODE 0x00400000
292#define RFC_CODE 0x00500000
293#define CMF_CODE 0x00900000
294#define CNF_CODE 0x00b00000
295#define CMFE_CODE 0x00d00000
296#define CNFE_CODE 0x00f00000
297
298/*
299===
300=== Common definitions
301===
302*/
303
304/* register masks */
305#define MASK_Rd 0x0000f000
306#define MASK_Rn 0x000f0000
307#define MASK_Fd 0x00007000
308#define MASK_Fm 0x00000007
309#define MASK_Fn 0x00070000
310
311/* condition code masks */
312#define CC_MASK 0xf0000000
313#define CC_NEGATIVE 0x80000000
314#define CC_ZERO 0x40000000
315#define CC_CARRY 0x20000000
316#define CC_OVERFLOW 0x10000000
317#define CC_EQ 0x00000000
318#define CC_NE 0x10000000
319#define CC_CS 0x20000000
320#define CC_HS CC_CS
321#define CC_CC 0x30000000
322#define CC_LO CC_CC
323#define CC_MI 0x40000000
324#define CC_PL 0x50000000
325#define CC_VS 0x60000000
326#define CC_VC 0x70000000
327#define CC_HI 0x80000000
328#define CC_LS 0x90000000
329#define CC_GE 0xa0000000
330#define CC_LT 0xb0000000
331#define CC_GT 0xc0000000
332#define CC_LE 0xd0000000
333#define CC_AL 0xe0000000
334#define CC_NV 0xf0000000
335
336/* rounding masks/values */
337#define MASK_ROUNDING_MODE 0x00000060
338#define ROUND_TO_NEAREST 0x00000000
339#define ROUND_TO_PLUS_INFINITY 0x00000020
340#define ROUND_TO_MINUS_INFINITY 0x00000040
341#define ROUND_TO_ZERO 0x00000060
342
343#define MASK_ROUNDING_PRECISION 0x00080080
344#define ROUND_SINGLE 0x00000000
345#define ROUND_DOUBLE 0x00000080
346#define ROUND_EXTENDED 0x00080000
347
348/* Get the condition code from the opcode. */
349#define getCondition(opcode) (opcode >> 28)
350
351/* Get the source register from the opcode. */
352#define getRn(opcode) ((opcode & MASK_Rn) >> 16)
353
354/* Get the destination floating point register from the opcode. */
355#define getFd(opcode) ((opcode & MASK_Fd) >> 12)
356
357/* Get the first source floating point register from the opcode. */
358#define getFn(opcode) ((opcode & MASK_Fn) >> 16)
359
360/* Get the second source floating point register from the opcode. */
361#define getFm(opcode) (opcode & MASK_Fm)
362
363/* Get the destination register from the opcode. */
364#define getRd(opcode) ((opcode & MASK_Rd) >> 12)
365
366/* Get the rounding mode from the opcode. */
367#define getRoundingMode(opcode) ((opcode & MASK_ROUNDING_MODE) >> 5)
368
369static inline const floatx80 getExtendedConstant(const unsigned int nIndex)
370{
371 extern const floatx80 floatx80Constant[];
372 return floatx80Constant[nIndex];
373}
374
375static inline const float64 getDoubleConstant(const unsigned int nIndex)
376{
377 extern const float64 float64Constant[];
378 return float64Constant[nIndex];
379}
380
381static inline const float32 getSingleConstant(const unsigned int nIndex)
382{
383 extern const float32 float32Constant[];
384 return float32Constant[nIndex];
385}
386
387extern unsigned int getRegisterCount(const unsigned int opcode);
388extern unsigned int getDestinationSize(const unsigned int opcode);
389
390#endif
diff --git a/arch/arm26/nwfpe/fpsr.h b/arch/arm26/nwfpe/fpsr.h
new file mode 100644
index 000000000000..6dafb0f5243c
--- /dev/null
+++ b/arch/arm26/nwfpe/fpsr.h
@@ -0,0 +1,108 @@
1/*
2 NetWinder Floating Point Emulator
3 (c) Rebel.com, 1998-1999
4
5 Direct questions, comments to Scott Bambrough <scottb@netwinder.org>
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20*/
21
22#ifndef __FPSR_H__
23#define __FPSR_H__
24
25/*
26The FPSR is a 32 bit register consisting of 4 parts, each exactly
27one byte.
28
29 SYSTEM ID
30 EXCEPTION TRAP ENABLE BYTE
31 SYSTEM CONTROL BYTE
32 CUMULATIVE EXCEPTION FLAGS BYTE
33
34The FPCR is a 32 bit register consisting of bit flags.
35*/
36
37/* SYSTEM ID
38------------
39Note: the system id byte is read only */
40
41typedef unsigned int FPSR; /* type for floating point status register */
42typedef unsigned int FPCR; /* type for floating point control register */
43
44#define MASK_SYSID 0xff000000
45#define BIT_HARDWARE 0x80000000
46#define FP_EMULATOR 0x01000000 /* System ID for emulator */
47#define FP_ACCELERATOR 0x81000000 /* System ID for FPA11 */
48
49/* EXCEPTION TRAP ENABLE BYTE
50----------------------------- */
51
52#define MASK_TRAP_ENABLE 0x00ff0000
53#define MASK_TRAP_ENABLE_STRICT 0x001f0000
54#define BIT_IXE 0x00100000 /* inexact exception enable */
55#define BIT_UFE 0x00080000 /* underflow exception enable */
56#define BIT_OFE 0x00040000 /* overflow exception enable */
57#define BIT_DZE 0x00020000 /* divide by zero exception enable */
58#define BIT_IOE 0x00010000 /* invalid operation exception enable */
59
60/* SYSTEM CONTROL BYTE
61---------------------- */
62
63#define MASK_SYSTEM_CONTROL 0x0000ff00
64#define MASK_TRAP_STRICT 0x00001f00
65
66#define BIT_AC 0x00001000 /* use alternative C-flag definition
67 for compares */
68#define BIT_EP 0x00000800 /* use expanded packed decimal format */
69#define BIT_SO 0x00000400 /* select synchronous operation of FPA */
70#define BIT_NE 0x00000200 /* NaN exception bit */
71#define BIT_ND 0x00000100 /* no denormalized numbers bit */
72
73/* CUMULATIVE EXCEPTION FLAGS BYTE
74---------------------------------- */
75
76#define MASK_EXCEPTION_FLAGS 0x000000ff
77#define MASK_EXCEPTION_FLAGS_STRICT 0x0000001f
78
79#define BIT_IXC 0x00000010 /* inexact exception flag */
80#define BIT_UFC 0x00000008 /* underflow exception flag */
81#define BIT_OFC 0x00000004 /* overfloat exception flag */
82#define BIT_DZC 0x00000002 /* divide by zero exception flag */
83#define BIT_IOC 0x00000001 /* invalid operation exception flag */
84
85/* Floating Point Control Register
86----------------------------------*/
87
88#define BIT_RU 0x80000000 /* rounded up bit */
89#define BIT_IE 0x10000000 /* inexact bit */
90#define BIT_MO 0x08000000 /* mantissa overflow bit */
91#define BIT_EO 0x04000000 /* exponent overflow bit */
92#define BIT_SB 0x00000800 /* store bounce */
93#define BIT_AB 0x00000400 /* arithmetic bounce */
94#define BIT_RE 0x00000200 /* rounding exception */
95#define BIT_DA 0x00000100 /* disable FPA */
96
97#define MASK_OP 0x00f08010 /* AU operation code */
98#define MASK_PR 0x00080080 /* AU precision */
99#define MASK_S1 0x00070000 /* AU source register 1 */
100#define MASK_S2 0x00000007 /* AU source register 2 */
101#define MASK_DS 0x00007000 /* AU destination register */
102#define MASK_RM 0x00000060 /* AU rounding mode */
103#define MASK_ALU 0x9cfff2ff /* only ALU can write these bits */
104#define MASK_RESET 0x00000d00 /* bits set on reset, all others cleared */
105#define MASK_WFC MASK_RESET
106#define MASK_RFC ~MASK_RESET
107
108#endif
diff --git a/arch/arm26/nwfpe/milieu.h b/arch/arm26/nwfpe/milieu.h
new file mode 100644
index 000000000000..a3892ab2dca4
--- /dev/null
+++ b/arch/arm26/nwfpe/milieu.h
@@ -0,0 +1,48 @@
1
2/*
3===============================================================================
4
5This C header file is part of the SoftFloat IEC/IEEE Floating-point
6Arithmetic Package, Release 2.
7
8Written by John R. Hauser. This work was made possible in part by the
9International Computer Science Institute, located at Suite 600, 1947 Center
10Street, Berkeley, California 94704. Funding was partially provided by the
11National Science Foundation under grant MIP-9311980. The original version
12of this code was written as part of a project to build a fixed-point vector
13processor in collaboration with the University of California at Berkeley,
14overseen by Profs. Nelson Morgan and John Wawrzynek. More information
15is available through the Web page `http://HTTP.CS.Berkeley.EDU/~jhauser/
16arithmetic/softfloat.html'.
17
18THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort
19has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT
20TIMES RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO
21PERSONS AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ANY
22AND ALL LOSSES, COSTS, OR OTHER PROBLEMS ARISING FROM ITS USE.
23
24Derivative works are acceptable, even for commercial purposes, so long as
25(1) they include prominent notice that the work is derivative, and (2) they
26include prominent notice akin to these three paragraphs for those parts of
27this code that are retained.
28
29===============================================================================
30*/
31
32/*
33-------------------------------------------------------------------------------
34Include common integer types and flags.
35-------------------------------------------------------------------------------
36*/
37#include "ARM-gcc.h"
38
39/*
40-------------------------------------------------------------------------------
41Symbolic Boolean literals.
42-------------------------------------------------------------------------------
43*/
44enum {
45 FALSE = 0,
46 TRUE = 1
47};
48
diff --git a/arch/arm26/nwfpe/single_cpdo.c b/arch/arm26/nwfpe/single_cpdo.c
new file mode 100644
index 000000000000..5cdcddbb8999
--- /dev/null
+++ b/arch/arm26/nwfpe/single_cpdo.c
@@ -0,0 +1,255 @@
1/*
2 NetWinder Floating Point Emulator
3 (c) Rebel.COM, 1998,1999
4
5 Direct questions, comments to Scott Bambrough <scottb@netwinder.org>
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20*/
21
22#include "fpa11.h"
23#include "softfloat.h"
24#include "fpopcode.h"
25
26float32 float32_exp(float32 Fm);
27float32 float32_ln(float32 Fm);
28float32 float32_sin(float32 rFm);
29float32 float32_cos(float32 rFm);
30float32 float32_arcsin(float32 rFm);
31float32 float32_arctan(float32 rFm);
32float32 float32_log(float32 rFm);
33float32 float32_tan(float32 rFm);
34float32 float32_arccos(float32 rFm);
35float32 float32_pow(float32 rFn,float32 rFm);
36float32 float32_pol(float32 rFn,float32 rFm);
37
38unsigned int SingleCPDO(const unsigned int opcode)
39{
40 FPA11 *fpa11 = GET_FPA11();
41 float32 rFm, rFn = 0; //FIXME - should be zero?
42 unsigned int Fd, Fm, Fn, nRc = 1;
43
44 Fm = getFm(opcode);
45 if (CONSTANT_FM(opcode))
46 {
47 rFm = getSingleConstant(Fm);
48 }
49 else
50 {
51 switch (fpa11->fType[Fm])
52 {
53 case typeSingle:
54 rFm = fpa11->fpreg[Fm].fSingle;
55 break;
56
57 default: return 0;
58 }
59 }
60
61 if (!MONADIC_INSTRUCTION(opcode))
62 {
63 Fn = getFn(opcode);
64 switch (fpa11->fType[Fn])
65 {
66 case typeSingle:
67 rFn = fpa11->fpreg[Fn].fSingle;
68 break;
69
70 default: return 0;
71 }
72 }
73
74 Fd = getFd(opcode);
75 switch (opcode & MASK_ARITHMETIC_OPCODE)
76 {
77 /* dyadic opcodes */
78 case ADF_CODE:
79 fpa11->fpreg[Fd].fSingle = float32_add(rFn,rFm);
80 break;
81
82 case MUF_CODE:
83 case FML_CODE:
84 fpa11->fpreg[Fd].fSingle = float32_mul(rFn,rFm);
85 break;
86
87 case SUF_CODE:
88 fpa11->fpreg[Fd].fSingle = float32_sub(rFn,rFm);
89 break;
90
91 case RSF_CODE:
92 fpa11->fpreg[Fd].fSingle = float32_sub(rFm,rFn);
93 break;
94
95 case DVF_CODE:
96 case FDV_CODE:
97 fpa11->fpreg[Fd].fSingle = float32_div(rFn,rFm);
98 break;
99
100 case RDF_CODE:
101 case FRD_CODE:
102 fpa11->fpreg[Fd].fSingle = float32_div(rFm,rFn);
103 break;
104
105#if 0
106 case POW_CODE:
107 fpa11->fpreg[Fd].fSingle = float32_pow(rFn,rFm);
108 break;
109
110 case RPW_CODE:
111 fpa11->fpreg[Fd].fSingle = float32_pow(rFm,rFn);
112 break;
113#endif
114
115 case RMF_CODE:
116 fpa11->fpreg[Fd].fSingle = float32_rem(rFn,rFm);
117 break;
118
119#if 0
120 case POL_CODE:
121 fpa11->fpreg[Fd].fSingle = float32_pol(rFn,rFm);
122 break;
123#endif
124
125 /* monadic opcodes */
126 case MVF_CODE:
127 fpa11->fpreg[Fd].fSingle = rFm;
128 break;
129
130 case MNF_CODE:
131 rFm ^= 0x80000000;
132 fpa11->fpreg[Fd].fSingle = rFm;
133 break;
134
135 case ABS_CODE:
136 rFm &= 0x7fffffff;
137 fpa11->fpreg[Fd].fSingle = rFm;
138 break;
139
140 case RND_CODE:
141 case URD_CODE:
142 fpa11->fpreg[Fd].fSingle = float32_round_to_int(rFm);
143 break;
144
145 case SQT_CODE:
146 fpa11->fpreg[Fd].fSingle = float32_sqrt(rFm);
147 break;
148
149#if 0
150 case LOG_CODE:
151 fpa11->fpreg[Fd].fSingle = float32_log(rFm);
152 break;
153
154 case LGN_CODE:
155 fpa11->fpreg[Fd].fSingle = float32_ln(rFm);
156 break;
157
158 case EXP_CODE:
159 fpa11->fpreg[Fd].fSingle = float32_exp(rFm);
160 break;
161
162 case SIN_CODE:
163 fpa11->fpreg[Fd].fSingle = float32_sin(rFm);
164 break;
165
166 case COS_CODE:
167 fpa11->fpreg[Fd].fSingle = float32_cos(rFm);
168 break;
169
170 case TAN_CODE:
171 fpa11->fpreg[Fd].fSingle = float32_tan(rFm);
172 break;
173
174 case ASN_CODE:
175 fpa11->fpreg[Fd].fSingle = float32_arcsin(rFm);
176 break;
177
178 case ACS_CODE:
179 fpa11->fpreg[Fd].fSingle = float32_arccos(rFm);
180 break;
181
182 case ATN_CODE:
183 fpa11->fpreg[Fd].fSingle = float32_arctan(rFm);
184 break;
185#endif
186
187 case NRM_CODE:
188 break;
189
190 default:
191 {
192 nRc = 0;
193 }
194 }
195
196 if (0 != nRc) fpa11->fType[Fd] = typeSingle;
197 return nRc;
198}
199
200#if 0
201float32 float32_exp(float32 Fm)
202{
203//series
204}
205
206float32 float32_ln(float32 Fm)
207{
208//series
209}
210
211float32 float32_sin(float32 rFm)
212{
213//series
214}
215
216float32 float32_cos(float32 rFm)
217{
218//series
219}
220
221float32 float32_arcsin(float32 rFm)
222{
223//series
224}
225
226float32 float32_arctan(float32 rFm)
227{
228 //series
229}
230
231float32 float32_arccos(float32 rFm)
232{
233 //return float32_sub(halfPi,float32_arcsin(rFm));
234}
235
236float32 float32_log(float32 rFm)
237{
238 return float32_div(float32_ln(rFm),getSingleConstant(7));
239}
240
241float32 float32_tan(float32 rFm)
242{
243 return float32_div(float32_sin(rFm),float32_cos(rFm));
244}
245
246float32 float32_pow(float32 rFn,float32 rFm)
247{
248 return float32_exp(float32_mul(rFm,float32_ln(rFn)));
249}
250
251float32 float32_pol(float32 rFn,float32 rFm)
252{
253 return float32_arctan(float32_div(rFn,rFm));
254}
255#endif
diff --git a/arch/arm26/nwfpe/softfloat-macros b/arch/arm26/nwfpe/softfloat-macros
new file mode 100644
index 000000000000..5469989f2c5e
--- /dev/null
+++ b/arch/arm26/nwfpe/softfloat-macros
@@ -0,0 +1,740 @@
1
2/*
3===============================================================================
4
5This C source fragment is part of the SoftFloat IEC/IEEE Floating-point
6Arithmetic Package, Release 2.
7
8Written by John R. Hauser. This work was made possible in part by the
9International Computer Science Institute, located at Suite 600, 1947 Center
10Street, Berkeley, California 94704. Funding was partially provided by the
11National Science Foundation under grant MIP-9311980. The original version
12of this code was written as part of a project to build a fixed-point vector
13processor in collaboration with the University of California at Berkeley,
14overseen by Profs. Nelson Morgan and John Wawrzynek. More information
15is available through the web page `http://HTTP.CS.Berkeley.EDU/~jhauser/
16arithmetic/softfloat.html'.
17
18THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort
19has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT
20TIMES RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO
21PERSONS AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ANY
22AND ALL LOSSES, COSTS, OR OTHER PROBLEMS ARISING FROM ITS USE.
23
24Derivative works are acceptable, even for commercial purposes, so long as
25(1) they include prominent notice that the work is derivative, and (2) they
26include prominent notice akin to these three paragraphs for those parts of
27this code that are retained.
28
29===============================================================================
30*/
31
32/*
33-------------------------------------------------------------------------------
34Shifts `a' right by the number of bits given in `count'. If any nonzero
35bits are shifted off, they are ``jammed'' into the least significant bit of
36the result by setting the least significant bit to 1. The value of `count'
37can be arbitrarily large; in particular, if `count' is greater than 32, the
38result will be either 0 or 1, depending on whether `a' is zero or nonzero.
39The result is stored in the location pointed to by `zPtr'.
40-------------------------------------------------------------------------------
41*/
42INLINE void shift32RightJamming( bits32 a, int16 count, bits32 *zPtr )
43{
44 bits32 z;
45 if ( count == 0 ) {
46 z = a;
47 }
48 else if ( count < 32 ) {
49 z = ( a>>count ) | ( ( a<<( ( - count ) & 31 ) ) != 0 );
50 }
51 else {
52 z = ( a != 0 );
53 }
54 *zPtr = z;
55}
56
57/*
58-------------------------------------------------------------------------------
59Shifts `a' right by the number of bits given in `count'. If any nonzero
60bits are shifted off, they are ``jammed'' into the least significant bit of
61the result by setting the least significant bit to 1. The value of `count'
62can be arbitrarily large; in particular, if `count' is greater than 64, the
63result will be either 0 or 1, depending on whether `a' is zero or nonzero.
64The result is stored in the location pointed to by `zPtr'.
65-------------------------------------------------------------------------------
66*/
67INLINE void shift64RightJamming( bits64 a, int16 count, bits64 *zPtr )
68{
69 bits64 z;
70
71 __asm__("@shift64RightJamming -- start");
72 if ( count == 0 ) {
73 z = a;
74 }
75 else if ( count < 64 ) {
76 z = ( a>>count ) | ( ( a<<( ( - count ) & 63 ) ) != 0 );
77 }
78 else {
79 z = ( a != 0 );
80 }
81 __asm__("@shift64RightJamming -- end");
82 *zPtr = z;
83}
84
85/*
86-------------------------------------------------------------------------------
87Shifts the 128-bit value formed by concatenating `a0' and `a1' right by 64
88_plus_ the number of bits given in `count'. The shifted result is at most
8964 nonzero bits; this is stored at the location pointed to by `z0Ptr'. The
90bits shifted off form a second 64-bit result as follows: The _last_ bit
91shifted off is the most-significant bit of the extra result, and the other
9263 bits of the extra result are all zero if and only if _all_but_the_last_
93bits shifted off were all zero. This extra result is stored in the location
94pointed to by `z1Ptr'. The value of `count' can be arbitrarily large.
95 (This routine makes more sense if `a0' and `a1' are considered to form a
96fixed-point value with binary point between `a0' and `a1'. This fixed-point
97value is shifted right by the number of bits given in `count', and the
98integer part of the result is returned at the location pointed to by
99`z0Ptr'. The fractional part of the result may be slightly corrupted as
100described above, and is returned at the location pointed to by `z1Ptr'.)
101-------------------------------------------------------------------------------
102*/
103INLINE void
104 shift64ExtraRightJamming(
105 bits64 a0, bits64 a1, int16 count, bits64 *z0Ptr, bits64 *z1Ptr )
106{
107 bits64 z0, z1;
108 int8 negCount = ( - count ) & 63;
109
110 if ( count == 0 ) {
111 z1 = a1;
112 z0 = a0;
113 }
114 else if ( count < 64 ) {
115 z1 = ( a0<<negCount ) | ( a1 != 0 );
116 z0 = a0>>count;
117 }
118 else {
119 if ( count == 64 ) {
120 z1 = a0 | ( a1 != 0 );
121 }
122 else {
123 z1 = ( ( a0 | a1 ) != 0 );
124 }
125 z0 = 0;
126 }
127 *z1Ptr = z1;
128 *z0Ptr = z0;
129
130}
131
132/*
133-------------------------------------------------------------------------------
134Shifts the 128-bit value formed by concatenating `a0' and `a1' right by the
135number of bits given in `count'. Any bits shifted off are lost. The value
136of `count' can be arbitrarily large; in particular, if `count' is greater
137than 128, the result will be 0. The result is broken into two 64-bit pieces
138which are stored at the locations pointed to by `z0Ptr' and `z1Ptr'.
139-------------------------------------------------------------------------------
140*/
141INLINE void
142 shift128Right(
143 bits64 a0, bits64 a1, int16 count, bits64 *z0Ptr, bits64 *z1Ptr )
144{
145 bits64 z0, z1;
146 int8 negCount = ( - count ) & 63;
147
148 if ( count == 0 ) {
149 z1 = a1;
150 z0 = a0;
151 }
152 else if ( count < 64 ) {
153 z1 = ( a0<<negCount ) | ( a1>>count );
154 z0 = a0>>count;
155 }
156 else {
157 z1 = ( count < 64 ) ? ( a0>>( count & 63 ) ) : 0;
158 z0 = 0;
159 }
160 *z1Ptr = z1;
161 *z0Ptr = z0;
162
163}
164
165/*
166-------------------------------------------------------------------------------
167Shifts the 128-bit value formed by concatenating `a0' and `a1' right by the
168number of bits given in `count'. If any nonzero bits are shifted off, they
169are ``jammed'' into the least significant bit of the result by setting the
170least significant bit to 1. The value of `count' can be arbitrarily large;
171in particular, if `count' is greater than 128, the result will be either 0
172or 1, depending on whether the concatenation of `a0' and `a1' is zero or
173nonzero. The result is broken into two 64-bit pieces which are stored at
174the locations pointed to by `z0Ptr' and `z1Ptr'.
175-------------------------------------------------------------------------------
176*/
177INLINE void
178 shift128RightJamming(
179 bits64 a0, bits64 a1, int16 count, bits64 *z0Ptr, bits64 *z1Ptr )
180{
181 bits64 z0, z1;
182 int8 negCount = ( - count ) & 63;
183
184 if ( count == 0 ) {
185 z1 = a1;
186 z0 = a0;
187 }
188 else if ( count < 64 ) {
189 z1 = ( a0<<negCount ) | ( a1>>count ) | ( ( a1<<negCount ) != 0 );
190 z0 = a0>>count;
191 }
192 else {
193 if ( count == 64 ) {
194 z1 = a0 | ( a1 != 0 );
195 }
196 else if ( count < 128 ) {
197 z1 = ( a0>>( count & 63 ) ) | ( ( ( a0<<negCount ) | a1 ) != 0 );
198 }
199 else {
200 z1 = ( ( a0 | a1 ) != 0 );
201 }
202 z0 = 0;
203 }
204 *z1Ptr = z1;
205 *z0Ptr = z0;
206
207}
208
209/*
210-------------------------------------------------------------------------------
211Shifts the 192-bit value formed by concatenating `a0', `a1', and `a2' right
212by 64 _plus_ the number of bits given in `count'. The shifted result is
213at most 128 nonzero bits; these are broken into two 64-bit pieces which are
214stored at the locations pointed to by `z0Ptr' and `z1Ptr'. The bits shifted
215off form a third 64-bit result as follows: The _last_ bit shifted off is
216the most-significant bit of the extra result, and the other 63 bits of the
217extra result are all zero if and only if _all_but_the_last_ bits shifted off
218were all zero. This extra result is stored in the location pointed to by
219`z2Ptr'. The value of `count' can be arbitrarily large.
220 (This routine makes more sense if `a0', `a1', and `a2' are considered
221to form a fixed-point value with binary point between `a1' and `a2'. This
222fixed-point value is shifted right by the number of bits given in `count',
223and the integer part of the result is returned at the locations pointed to
224by `z0Ptr' and `z1Ptr'. The fractional part of the result may be slightly
225corrupted as described above, and is returned at the location pointed to by
226`z2Ptr'.)
227-------------------------------------------------------------------------------
228*/
229INLINE void
230 shift128ExtraRightJamming(
231 bits64 a0,
232 bits64 a1,
233 bits64 a2,
234 int16 count,
235 bits64 *z0Ptr,
236 bits64 *z1Ptr,
237 bits64 *z2Ptr
238 )
239{
240 bits64 z0, z1, z2;
241 int8 negCount = ( - count ) & 63;
242
243 if ( count == 0 ) {
244 z2 = a2;
245 z1 = a1;
246 z0 = a0;
247 }
248 else {
249 if ( count < 64 ) {
250 z2 = a1<<negCount;
251 z1 = ( a0<<negCount ) | ( a1>>count );
252 z0 = a0>>count;
253 }
254 else {
255 if ( count == 64 ) {
256 z2 = a1;
257 z1 = a0;
258 }
259 else {
260 a2 |= a1;
261 if ( count < 128 ) {
262 z2 = a0<<negCount;
263 z1 = a0>>( count & 63 );
264 }
265 else {
266 z2 = ( count == 128 ) ? a0 : ( a0 != 0 );
267 z1 = 0;
268 }
269 }
270 z0 = 0;
271 }
272 z2 |= ( a2 != 0 );
273 }
274 *z2Ptr = z2;
275 *z1Ptr = z1;
276 *z0Ptr = z0;
277
278}
279
280/*
281-------------------------------------------------------------------------------
282Shifts the 128-bit value formed by concatenating `a0' and `a1' left by the
283number of bits given in `count'. Any bits shifted off are lost. The value
284of `count' must be less than 64. The result is broken into two 64-bit
285pieces which are stored at the locations pointed to by `z0Ptr' and `z1Ptr'.
286-------------------------------------------------------------------------------
287*/
288INLINE void
289 shortShift128Left(
290 bits64 a0, bits64 a1, int16 count, bits64 *z0Ptr, bits64 *z1Ptr )
291{
292
293 *z1Ptr = a1<<count;
294 *z0Ptr =
295 ( count == 0 ) ? a0 : ( a0<<count ) | ( a1>>( ( - count ) & 63 ) );
296
297}
298
299/*
300-------------------------------------------------------------------------------
301Shifts the 192-bit value formed by concatenating `a0', `a1', and `a2' left
302by the number of bits given in `count'. Any bits shifted off are lost.
303The value of `count' must be less than 64. The result is broken into three
30464-bit pieces which are stored at the locations pointed to by `z0Ptr',
305`z1Ptr', and `z2Ptr'.
306-------------------------------------------------------------------------------
307*/
308INLINE void
309 shortShift192Left(
310 bits64 a0,
311 bits64 a1,
312 bits64 a2,
313 int16 count,
314 bits64 *z0Ptr,
315 bits64 *z1Ptr,
316 bits64 *z2Ptr
317 )
318{
319 bits64 z0, z1, z2;
320 int8 negCount;
321
322 z2 = a2<<count;
323 z1 = a1<<count;
324 z0 = a0<<count;
325 if ( 0 < count ) {
326 negCount = ( ( - count ) & 63 );
327 z1 |= a2>>negCount;
328 z0 |= a1>>negCount;
329 }
330 *z2Ptr = z2;
331 *z1Ptr = z1;
332 *z0Ptr = z0;
333
334}
335
336/*
337-------------------------------------------------------------------------------
338Adds the 128-bit value formed by concatenating `a0' and `a1' to the 128-bit
339value formed by concatenating `b0' and `b1'. Addition is modulo 2^128, so
340any carry out is lost. The result is broken into two 64-bit pieces which
341are stored at the locations pointed to by `z0Ptr' and `z1Ptr'.
342-------------------------------------------------------------------------------
343*/
344INLINE void
345 add128(
346 bits64 a0, bits64 a1, bits64 b0, bits64 b1, bits64 *z0Ptr, bits64 *z1Ptr )
347{
348 bits64 z1;
349
350 z1 = a1 + b1;
351 *z1Ptr = z1;
352 *z0Ptr = a0 + b0 + ( z1 < a1 );
353
354}
355
356/*
357-------------------------------------------------------------------------------
358Adds the 192-bit value formed by concatenating `a0', `a1', and `a2' to the
359192-bit value formed by concatenating `b0', `b1', and `b2'. Addition is
360modulo 2^192, so any carry out is lost. The result is broken into three
36164-bit pieces which are stored at the locations pointed to by `z0Ptr',
362`z1Ptr', and `z2Ptr'.
363-------------------------------------------------------------------------------
364*/
365INLINE void
366 add192(
367 bits64 a0,
368 bits64 a1,
369 bits64 a2,
370 bits64 b0,
371 bits64 b1,
372 bits64 b2,
373 bits64 *z0Ptr,
374 bits64 *z1Ptr,
375 bits64 *z2Ptr
376 )
377{
378 bits64 z0, z1, z2;
379 int8 carry0, carry1;
380
381 z2 = a2 + b2;
382 carry1 = ( z2 < a2 );
383 z1 = a1 + b1;
384 carry0 = ( z1 < a1 );
385 z0 = a0 + b0;
386 z1 += carry1;
387 z0 += ( z1 < carry1 );
388 z0 += carry0;
389 *z2Ptr = z2;
390 *z1Ptr = z1;
391 *z0Ptr = z0;
392
393}
394
395/*
396-------------------------------------------------------------------------------
397Subtracts the 128-bit value formed by concatenating `b0' and `b1' from the
398128-bit value formed by concatenating `a0' and `a1'. Subtraction is modulo
3992^128, so any borrow out (carry out) is lost. The result is broken into two
40064-bit pieces which are stored at the locations pointed to by `z0Ptr' and
401`z1Ptr'.
402-------------------------------------------------------------------------------
403*/
404INLINE void
405 sub128(
406 bits64 a0, bits64 a1, bits64 b0, bits64 b1, bits64 *z0Ptr, bits64 *z1Ptr )
407{
408
409 *z1Ptr = a1 - b1;
410 *z0Ptr = a0 - b0 - ( a1 < b1 );
411
412}
413
414/*
415-------------------------------------------------------------------------------
416Subtracts the 192-bit value formed by concatenating `b0', `b1', and `b2'
417from the 192-bit value formed by concatenating `a0', `a1', and `a2'.
418Subtraction is modulo 2^192, so any borrow out (carry out) is lost. The
419result is broken into three 64-bit pieces which are stored at the locations
420pointed to by `z0Ptr', `z1Ptr', and `z2Ptr'.
421-------------------------------------------------------------------------------
422*/
423INLINE void
424 sub192(
425 bits64 a0,
426 bits64 a1,
427 bits64 a2,
428 bits64 b0,
429 bits64 b1,
430 bits64 b2,
431 bits64 *z0Ptr,
432 bits64 *z1Ptr,
433 bits64 *z2Ptr
434 )
435{
436 bits64 z0, z1, z2;
437 int8 borrow0, borrow1;
438
439 z2 = a2 - b2;
440 borrow1 = ( a2 < b2 );
441 z1 = a1 - b1;
442 borrow0 = ( a1 < b1 );
443 z0 = a0 - b0;
444 z0 -= ( z1 < borrow1 );
445 z1 -= borrow1;
446 z0 -= borrow0;
447 *z2Ptr = z2;
448 *z1Ptr = z1;
449 *z0Ptr = z0;
450
451}
452
453/*
454-------------------------------------------------------------------------------
455Multiplies `a' by `b' to obtain a 128-bit product. The product is broken
456into two 64-bit pieces which are stored at the locations pointed to by
457`z0Ptr' and `z1Ptr'.
458-------------------------------------------------------------------------------
459*/
460INLINE void mul64To128( bits64 a, bits64 b, bits64 *z0Ptr, bits64 *z1Ptr )
461{
462 bits32 aHigh, aLow, bHigh, bLow;
463 bits64 z0, zMiddleA, zMiddleB, z1;
464
465 aLow = a;
466 aHigh = a>>32;
467 bLow = b;
468 bHigh = b>>32;
469 z1 = ( (bits64) aLow ) * bLow;
470 zMiddleA = ( (bits64) aLow ) * bHigh;
471 zMiddleB = ( (bits64) aHigh ) * bLow;
472 z0 = ( (bits64) aHigh ) * bHigh;
473 zMiddleA += zMiddleB;
474 z0 += ( ( (bits64) ( zMiddleA < zMiddleB ) )<<32 ) + ( zMiddleA>>32 );
475 zMiddleA <<= 32;
476 z1 += zMiddleA;
477 z0 += ( z1 < zMiddleA );
478 *z1Ptr = z1;
479 *z0Ptr = z0;
480
481}
482
483/*
484-------------------------------------------------------------------------------
485Multiplies the 128-bit value formed by concatenating `a0' and `a1' by `b' to
486obtain a 192-bit product. The product is broken into three 64-bit pieces
487which are stored at the locations pointed to by `z0Ptr', `z1Ptr', and
488`z2Ptr'.
489-------------------------------------------------------------------------------
490*/
491INLINE void
492 mul128By64To192(
493 bits64 a0,
494 bits64 a1,
495 bits64 b,
496 bits64 *z0Ptr,
497 bits64 *z1Ptr,
498 bits64 *z2Ptr
499 )
500{
501 bits64 z0, z1, z2, more1;
502
503 mul64To128( a1, b, &z1, &z2 );
504 mul64To128( a0, b, &z0, &more1 );
505 add128( z0, more1, 0, z1, &z0, &z1 );
506 *z2Ptr = z2;
507 *z1Ptr = z1;
508 *z0Ptr = z0;
509
510}
511
512/*
513-------------------------------------------------------------------------------
514Multiplies the 128-bit value formed by concatenating `a0' and `a1' to the
515128-bit value formed by concatenating `b0' and `b1' to obtain a 256-bit
516product. The product is broken into four 64-bit pieces which are stored at
517the locations pointed to by `z0Ptr', `z1Ptr', `z2Ptr', and `z3Ptr'.
518-------------------------------------------------------------------------------
519*/
520INLINE void
521 mul128To256(
522 bits64 a0,
523 bits64 a1,
524 bits64 b0,
525 bits64 b1,
526 bits64 *z0Ptr,
527 bits64 *z1Ptr,
528 bits64 *z2Ptr,
529 bits64 *z3Ptr
530 )
531{
532 bits64 z0, z1, z2, z3;
533 bits64 more1, more2;
534
535 mul64To128( a1, b1, &z2, &z3 );
536 mul64To128( a1, b0, &z1, &more2 );
537 add128( z1, more2, 0, z2, &z1, &z2 );
538 mul64To128( a0, b0, &z0, &more1 );
539 add128( z0, more1, 0, z1, &z0, &z1 );
540 mul64To128( a0, b1, &more1, &more2 );
541 add128( more1, more2, 0, z2, &more1, &z2 );
542 add128( z0, z1, 0, more1, &z0, &z1 );
543 *z3Ptr = z3;
544 *z2Ptr = z2;
545 *z1Ptr = z1;
546 *z0Ptr = z0;
547
548}
549
550/*
551-------------------------------------------------------------------------------
552Returns an approximation to the 64-bit integer quotient obtained by dividing
553`b' into the 128-bit value formed by concatenating `a0' and `a1'. The
554divisor `b' must be at least 2^63. If q is the exact quotient truncated
555toward zero, the approximation returned lies between q and q + 2 inclusive.
556If the exact quotient q is larger than 64 bits, the maximum positive 64-bit
557unsigned integer is returned.
558-------------------------------------------------------------------------------
559*/
560static bits64 estimateDiv128To64( bits64 a0, bits64 a1, bits64 b )
561{
562 bits64 b0, b1;
563 bits64 rem0, rem1, term0, term1;
564 bits64 z;
565 if ( b <= a0 ) return LIT64( 0xFFFFFFFFFFFFFFFF );
566 b0 = b>>32;
567 z = ( b0<<32 <= a0 ) ? LIT64( 0xFFFFFFFF00000000 ) : ( a0 / b0 )<<32;
568 mul64To128( b, z, &term0, &term1 );
569 sub128( a0, a1, term0, term1, &rem0, &rem1 );
570 while ( ( (sbits64) rem0 ) < 0 ) {
571 z -= LIT64( 0x100000000 );
572 b1 = b<<32;
573 add128( rem0, rem1, b0, b1, &rem0, &rem1 );
574 }
575 rem0 = ( rem0<<32 ) | ( rem1>>32 );
576 z |= ( b0<<32 <= rem0 ) ? 0xFFFFFFFF : rem0 / b0;
577 return z;
578
579}
580
581/*
582-------------------------------------------------------------------------------
583Returns an approximation to the square root of the 32-bit significand given
584by `a'. Considered as an integer, `a' must be at least 2^31. If bit 0 of
585`aExp' (the least significant bit) is 1, the integer returned approximates
5862^31*sqrt(`a'/2^31), where `a' is considered an integer. If bit 0 of `aExp'
587is 0, the integer returned approximates 2^31*sqrt(`a'/2^30). In either
588case, the approximation returned lies strictly within +/-2 of the exact
589value.
590-------------------------------------------------------------------------------
591*/
592static bits32 estimateSqrt32( int16 aExp, bits32 a )
593{
594 static const bits16 sqrtOddAdjustments[] = {
595 0x0004, 0x0022, 0x005D, 0x00B1, 0x011D, 0x019F, 0x0236, 0x02E0,
596 0x039C, 0x0468, 0x0545, 0x0631, 0x072B, 0x0832, 0x0946, 0x0A67
597 };
598 static const bits16 sqrtEvenAdjustments[] = {
599 0x0A2D, 0x08AF, 0x075A, 0x0629, 0x051A, 0x0429, 0x0356, 0x029E,
600 0x0200, 0x0179, 0x0109, 0x00AF, 0x0068, 0x0034, 0x0012, 0x0002
601 };
602 int8 index;
603 bits32 z;
604
605 index = ( a>>27 ) & 15;
606 if ( aExp & 1 ) {
607 z = 0x4000 + ( a>>17 ) - sqrtOddAdjustments[ index ];
608 z = ( ( a / z )<<14 ) + ( z<<15 );
609 a >>= 1;
610 }
611 else {
612 z = 0x8000 + ( a>>17 ) - sqrtEvenAdjustments[ index ];
613 z = a / z + z;
614 z = ( 0x20000 <= z ) ? 0xFFFF8000 : ( z<<15 );
615 if ( z <= a ) return (bits32) ( ( (sbits32) a )>>1 );
616 }
617 return ( (bits32) ( ( ( (bits64) a )<<31 ) / z ) ) + ( z>>1 );
618
619}
620
621/*
622-------------------------------------------------------------------------------
623Returns the number of leading 0 bits before the most-significant 1 bit
624of `a'. If `a' is zero, 32 is returned.
625-------------------------------------------------------------------------------
626*/
627static int8 countLeadingZeros32( bits32 a )
628{
629 static const int8 countLeadingZerosHigh[] = {
630 8, 7, 6, 6, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4,
631 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
632 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
633 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
634 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
635 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
636 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
637 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
638 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
639 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
640 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
641 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
642 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
643 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
644 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
645 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
646 };
647 int8 shiftCount;
648
649 shiftCount = 0;
650 if ( a < 0x10000 ) {
651 shiftCount += 16;
652 a <<= 16;
653 }
654 if ( a < 0x1000000 ) {
655 shiftCount += 8;
656 a <<= 8;
657 }
658 shiftCount += countLeadingZerosHigh[ a>>24 ];
659 return shiftCount;
660
661}
662
663/*
664-------------------------------------------------------------------------------
665Returns the number of leading 0 bits before the most-significant 1 bit
666of `a'. If `a' is zero, 64 is returned.
667-------------------------------------------------------------------------------
668*/
669static int8 countLeadingZeros64( bits64 a )
670{
671 int8 shiftCount;
672
673 shiftCount = 0;
674 if ( a < ( (bits64) 1 )<<32 ) {
675 shiftCount += 32;
676 }
677 else {
678 a >>= 32;
679 }
680 shiftCount += countLeadingZeros32( a );
681 return shiftCount;
682
683}
684
685/*
686-------------------------------------------------------------------------------
687Returns 1 if the 128-bit value formed by concatenating `a0' and `a1'
688is equal to the 128-bit value formed by concatenating `b0' and `b1'.
689Otherwise, returns 0.
690-------------------------------------------------------------------------------
691*/
692INLINE flag eq128( bits64 a0, bits64 a1, bits64 b0, bits64 b1 )
693{
694
695 return ( a0 == b0 ) && ( a1 == b1 );
696
697}
698
699/*
700-------------------------------------------------------------------------------
701Returns 1 if the 128-bit value formed by concatenating `a0' and `a1' is less
702than or equal to the 128-bit value formed by concatenating `b0' and `b1'.
703Otherwise, returns 0.
704-------------------------------------------------------------------------------
705*/
706INLINE flag le128( bits64 a0, bits64 a1, bits64 b0, bits64 b1 )
707{
708
709 return ( a0 < b0 ) || ( ( a0 == b0 ) && ( a1 <= b1 ) );
710
711}
712
713/*
714-------------------------------------------------------------------------------
715Returns 1 if the 128-bit value formed by concatenating `a0' and `a1' is less
716than the 128-bit value formed by concatenating `b0' and `b1'. Otherwise,
717returns 0.
718-------------------------------------------------------------------------------
719*/
720INLINE flag lt128( bits64 a0, bits64 a1, bits64 b0, bits64 b1 )
721{
722
723 return ( a0 < b0 ) || ( ( a0 == b0 ) && ( a1 < b1 ) );
724
725}
726
727/*
728-------------------------------------------------------------------------------
729Returns 1 if the 128-bit value formed by concatenating `a0' and `a1' is
730not equal to the 128-bit value formed by concatenating `b0' and `b1'.
731Otherwise, returns 0.
732-------------------------------------------------------------------------------
733*/
734INLINE flag ne128( bits64 a0, bits64 a1, bits64 b0, bits64 b1 )
735{
736
737 return ( a0 != b0 ) || ( a1 != b1 );
738
739}
740
diff --git a/arch/arm26/nwfpe/softfloat-specialize b/arch/arm26/nwfpe/softfloat-specialize
new file mode 100644
index 000000000000..acf409144763
--- /dev/null
+++ b/arch/arm26/nwfpe/softfloat-specialize
@@ -0,0 +1,366 @@
1
2/*
3===============================================================================
4
5This C source fragment is part of the SoftFloat IEC/IEEE Floating-point
6Arithmetic Package, Release 2.
7
8Written by John R. Hauser. This work was made possible in part by the
9International Computer Science Institute, located at Suite 600, 1947 Center
10Street, Berkeley, California 94704. Funding was partially provided by the
11National Science Foundation under grant MIP-9311980. The original version
12of this code was written as part of a project to build a fixed-point vector
13processor in collaboration with the University of California at Berkeley,
14overseen by Profs. Nelson Morgan and John Wawrzynek. More information
15is available through the Web page `http://HTTP.CS.Berkeley.EDU/~jhauser/
16arithmetic/softfloat.html'.
17
18THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort
19has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT
20TIMES RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO
21PERSONS AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ANY
22AND ALL LOSSES, COSTS, OR OTHER PROBLEMS ARISING FROM ITS USE.
23
24Derivative works are acceptable, even for commercial purposes, so long as
25(1) they include prominent notice that the work is derivative, and (2) they
26include prominent notice akin to these three paragraphs for those parts of
27this code that are retained.
28
29===============================================================================
30*/
31
32/*
33-------------------------------------------------------------------------------
34Underflow tininess-detection mode, statically initialized to default value.
35(The declaration in `softfloat.h' must match the `int8' type here.)
36-------------------------------------------------------------------------------
37*/
38int8 float_detect_tininess = float_tininess_after_rounding;
39
40/*
41-------------------------------------------------------------------------------
42Raises the exceptions specified by `flags'. Floating-point traps can be
43defined here if desired. It is currently not possible for such a trap to
44substitute a result value. If traps are not implemented, this routine
45should be simply `float_exception_flags |= flags;'.
46
47ScottB: November 4, 1998
48Moved this function out of softfloat-specialize into fpmodule.c.
49This effectively isolates all the changes required for integrating with the
50Linux kernel into fpmodule.c. Porting to NetBSD should only require modifying
51fpmodule.c to integrate with the NetBSD kernel (I hope!).
52-------------------------------------------------------------------------------
53void float_raise( int8 flags )
54{
55 float_exception_flags |= flags;
56}
57*/
58
59/*
60-------------------------------------------------------------------------------
61Internal canonical NaN format.
62-------------------------------------------------------------------------------
63*/
64typedef struct {
65 flag sign;
66 bits64 high, low;
67} commonNaNT;
68
69/*
70-------------------------------------------------------------------------------
71The pattern for a default generated single-precision NaN.
72-------------------------------------------------------------------------------
73*/
74#define float32_default_nan 0xFFFFFFFF
75
76/*
77-------------------------------------------------------------------------------
78Returns 1 if the single-precision floating-point value `a' is a NaN;
79otherwise returns 0.
80-------------------------------------------------------------------------------
81*/
82flag float32_is_nan( float32 a )
83{
84
85 return ( 0xFF000000 < (bits32) ( a<<1 ) );
86
87}
88
89/*
90-------------------------------------------------------------------------------
91Returns 1 if the single-precision floating-point value `a' is a signaling
92NaN; otherwise returns 0.
93-------------------------------------------------------------------------------
94*/
95flag float32_is_signaling_nan( float32 a )
96{
97
98 return ( ( ( a>>22 ) & 0x1FF ) == 0x1FE ) && ( a & 0x003FFFFF );
99
100}
101
102/*
103-------------------------------------------------------------------------------
104Returns the result of converting the single-precision floating-point NaN
105`a' to the canonical NaN format. If `a' is a signaling NaN, the invalid
106exception is raised.
107-------------------------------------------------------------------------------
108*/
109static commonNaNT float32ToCommonNaN( float32 a )
110{
111 commonNaNT z;
112
113 if ( float32_is_signaling_nan( a ) ) float_raise( float_flag_invalid );
114 z.sign = a>>31;
115 z.low = 0;
116 z.high = ( (bits64) a )<<41;
117 return z;
118
119}
120
121/*
122-------------------------------------------------------------------------------
123Returns the result of converting the canonical NaN `a' to the single-
124precision floating-point format.
125-------------------------------------------------------------------------------
126*/
127static float32 commonNaNToFloat32( commonNaNT a )
128{
129
130 return ( ( (bits32) a.sign )<<31 ) | 0x7FC00000 | ( a.high>>41 );
131
132}
133
134/*
135-------------------------------------------------------------------------------
136Takes two single-precision floating-point values `a' and `b', one of which
137is a NaN, and returns the appropriate NaN result. If either `a' or `b' is a
138signaling NaN, the invalid exception is raised.
139-------------------------------------------------------------------------------
140*/
141static float32 propagateFloat32NaN( float32 a, float32 b )
142{
143 flag aIsNaN, aIsSignalingNaN, bIsNaN, bIsSignalingNaN;
144
145 aIsNaN = float32_is_nan( a );
146 aIsSignalingNaN = float32_is_signaling_nan( a );
147 bIsNaN = float32_is_nan( b );
148 bIsSignalingNaN = float32_is_signaling_nan( b );
149 a |= 0x00400000;
150 b |= 0x00400000;
151 if ( aIsSignalingNaN | bIsSignalingNaN ) float_raise( float_flag_invalid );
152 if ( aIsNaN ) {
153 return ( aIsSignalingNaN & bIsNaN ) ? b : a;
154 }
155 else {
156 return b;
157 }
158
159}
160
161/*
162-------------------------------------------------------------------------------
163The pattern for a default generated double-precision NaN.
164-------------------------------------------------------------------------------
165*/
166#define float64_default_nan LIT64( 0xFFFFFFFFFFFFFFFF )
167
168/*
169-------------------------------------------------------------------------------
170Returns 1 if the double-precision floating-point value `a' is a NaN;
171otherwise returns 0.
172-------------------------------------------------------------------------------
173*/
174flag float64_is_nan( float64 a )
175{
176
177 return ( LIT64( 0xFFE0000000000000 ) < (bits64) ( a<<1 ) );
178
179}
180
181/*
182-------------------------------------------------------------------------------
183Returns 1 if the double-precision floating-point value `a' is a signaling
184NaN; otherwise returns 0.
185-------------------------------------------------------------------------------
186*/
187flag float64_is_signaling_nan( float64 a )
188{
189
190 return
191 ( ( ( a>>51 ) & 0xFFF ) == 0xFFE )
192 && ( a & LIT64( 0x0007FFFFFFFFFFFF ) );
193
194}
195
196/*
197-------------------------------------------------------------------------------
198Returns the result of converting the double-precision floating-point NaN
199`a' to the canonical NaN format. If `a' is a signaling NaN, the invalid
200exception is raised.
201-------------------------------------------------------------------------------
202*/
203static commonNaNT float64ToCommonNaN( float64 a )
204{
205 commonNaNT z;
206
207 if ( float64_is_signaling_nan( a ) ) float_raise( float_flag_invalid );
208 z.sign = a>>63;
209 z.low = 0;
210 z.high = a<<12;
211 return z;
212
213}
214
215/*
216-------------------------------------------------------------------------------
217Returns the result of converting the canonical NaN `a' to the double-
218precision floating-point format.
219-------------------------------------------------------------------------------
220*/
221static float64 commonNaNToFloat64( commonNaNT a )
222{
223
224 return
225 ( ( (bits64) a.sign )<<63 )
226 | LIT64( 0x7FF8000000000000 )
227 | ( a.high>>12 );
228
229}
230
231/*
232-------------------------------------------------------------------------------
233Takes two double-precision floating-point values `a' and `b', one of which
234is a NaN, and returns the appropriate NaN result. If either `a' or `b' is a
235signaling NaN, the invalid exception is raised.
236-------------------------------------------------------------------------------
237*/
238static float64 propagateFloat64NaN( float64 a, float64 b )
239{
240 flag aIsNaN, aIsSignalingNaN, bIsNaN, bIsSignalingNaN;
241
242 aIsNaN = float64_is_nan( a );
243 aIsSignalingNaN = float64_is_signaling_nan( a );
244 bIsNaN = float64_is_nan( b );
245 bIsSignalingNaN = float64_is_signaling_nan( b );
246 a |= LIT64( 0x0008000000000000 );
247 b |= LIT64( 0x0008000000000000 );
248 if ( aIsSignalingNaN | bIsSignalingNaN ) float_raise( float_flag_invalid );
249 if ( aIsNaN ) {
250 return ( aIsSignalingNaN & bIsNaN ) ? b : a;
251 }
252 else {
253 return b;
254 }
255
256}
257
258#ifdef FLOATX80
259
260/*
261-------------------------------------------------------------------------------
262The pattern for a default generated extended double-precision NaN. The
263`high' and `low' values hold the most- and least-significant bits,
264respectively.
265-------------------------------------------------------------------------------
266*/
267#define floatx80_default_nan_high 0xFFFF
268#define floatx80_default_nan_low LIT64( 0xFFFFFFFFFFFFFFFF )
269
270/*
271-------------------------------------------------------------------------------
272Returns 1 if the extended double-precision floating-point value `a' is a
273NaN; otherwise returns 0.
274-------------------------------------------------------------------------------
275*/
276flag floatx80_is_nan( floatx80 a )
277{
278
279 return ( ( a.high & 0x7FFF ) == 0x7FFF ) && (bits64) ( a.low<<1 );
280
281}
282
283/*
284-------------------------------------------------------------------------------
285Returns 1 if the extended double-precision floating-point value `a' is a
286signaling NaN; otherwise returns 0.
287-------------------------------------------------------------------------------
288*/
289flag floatx80_is_signaling_nan( floatx80 a )
290{
291 //register int lr;
292 bits64 aLow;
293
294 //__asm__("mov %0, lr" : : "g" (lr));
295 //fp_printk("floatx80_is_signalling_nan() called from 0x%08x\n",lr);
296 aLow = a.low & ~ LIT64( 0x4000000000000000 );
297 return
298 ( ( a.high & 0x7FFF ) == 0x7FFF )
299 && (bits64) ( aLow<<1 )
300 && ( a.low == aLow );
301
302}
303
304/*
305-------------------------------------------------------------------------------
306Returns the result of converting the extended double-precision floating-
307point NaN `a' to the canonical NaN format. If `a' is a signaling NaN, the
308invalid exception is raised.
309-------------------------------------------------------------------------------
310*/
311static commonNaNT floatx80ToCommonNaN( floatx80 a )
312{
313 commonNaNT z;
314
315 if ( floatx80_is_signaling_nan( a ) ) float_raise( float_flag_invalid );
316 z.sign = a.high>>15;
317 z.low = 0;
318 z.high = a.low<<1;
319 return z;
320
321}
322
323/*
324-------------------------------------------------------------------------------
325Returns the result of converting the canonical NaN `a' to the extended
326double-precision floating-point format.
327-------------------------------------------------------------------------------
328*/
329static floatx80 commonNaNToFloatx80( commonNaNT a )
330{
331 floatx80 z;
332
333 z.low = LIT64( 0xC000000000000000 ) | ( a.high>>1 );
334 z.high = ( ( (bits16) a.sign )<<15 ) | 0x7FFF;
335 return z;
336
337}
338
339/*
340-------------------------------------------------------------------------------
341Takes two extended double-precision floating-point values `a' and `b', one
342of which is a NaN, and returns the appropriate NaN result. If either `a' or
343`b' is a signaling NaN, the invalid exception is raised.
344-------------------------------------------------------------------------------
345*/
346static floatx80 propagateFloatx80NaN( floatx80 a, floatx80 b )
347{
348 flag aIsNaN, aIsSignalingNaN, bIsNaN, bIsSignalingNaN;
349
350 aIsNaN = floatx80_is_nan( a );
351 aIsSignalingNaN = floatx80_is_signaling_nan( a );
352 bIsNaN = floatx80_is_nan( b );
353 bIsSignalingNaN = floatx80_is_signaling_nan( b );
354 a.low |= LIT64( 0xC000000000000000 );
355 b.low |= LIT64( 0xC000000000000000 );
356 if ( aIsSignalingNaN | bIsSignalingNaN ) float_raise( float_flag_invalid );
357 if ( aIsNaN ) {
358 return ( aIsSignalingNaN & bIsNaN ) ? b : a;
359 }
360 else {
361 return b;
362 }
363
364}
365
366#endif
diff --git a/arch/arm26/nwfpe/softfloat.c b/arch/arm26/nwfpe/softfloat.c
new file mode 100644
index 000000000000..26c1b916e527
--- /dev/null
+++ b/arch/arm26/nwfpe/softfloat.c
@@ -0,0 +1,3439 @@
1/*
2===============================================================================
3
4This C source file is part of the SoftFloat IEC/IEEE Floating-point
5Arithmetic Package, Release 2.
6
7Written by John R. Hauser. This work was made possible in part by the
8International Computer Science Institute, located at Suite 600, 1947 Center
9Street, Berkeley, California 94704. Funding was partially provided by the
10National Science Foundation under grant MIP-9311980. The original version
11of this code was written as part of a project to build a fixed-point vector
12processor in collaboration with the University of California at Berkeley,
13overseen by Profs. Nelson Morgan and John Wawrzynek. More information
14is available through the web page `http://HTTP.CS.Berkeley.EDU/~jhauser/
15arithmetic/softfloat.html'.
16
17THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort
18has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT
19TIMES RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO
20PERSONS AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ANY
21AND ALL LOSSES, COSTS, OR OTHER PROBLEMS ARISING FROM ITS USE.
22
23Derivative works are acceptable, even for commercial purposes, so long as
24(1) they include prominent notice that the work is derivative, and (2) they
25include prominent notice akin to these three paragraphs for those parts of
26this code that are retained.
27
28===============================================================================
29*/
30
31#include "fpa11.h"
32#include "milieu.h"
33#include "softfloat.h"
34
35/*
36-------------------------------------------------------------------------------
37Floating-point rounding mode, extended double-precision rounding precision,
38and exception flags.
39-------------------------------------------------------------------------------
40*/
41int8 float_rounding_mode = float_round_nearest_even;
42int8 floatx80_rounding_precision = 80;
43int8 float_exception_flags;
44
45/*
46-------------------------------------------------------------------------------
47Primitive arithmetic functions, including multi-word arithmetic, and
48division and square root approximations. (Can be specialized to target if
49desired.)
50-------------------------------------------------------------------------------
51*/
52#include "softfloat-macros"
53
54/*
55-------------------------------------------------------------------------------
56Functions and definitions to determine: (1) whether tininess for underflow
57is detected before or after rounding by default, (2) what (if anything)
58happens when exceptions are raised, (3) how signaling NaNs are distinguished
59from quiet NaNs, (4) the default generated quiet NaNs, and (5) how NaNs
60are propagated from function inputs to output. These details are target-
61specific.
62-------------------------------------------------------------------------------
63*/
64#include "softfloat-specialize"
65
66/*
67-------------------------------------------------------------------------------
68Takes a 64-bit fixed-point value `absZ' with binary point between bits 6
69and 7, and returns the properly rounded 32-bit integer corresponding to the
70input. If `zSign' is nonzero, the input is negated before being converted
71to an integer. Bit 63 of `absZ' must be zero. Ordinarily, the fixed-point
72input is simply rounded to an integer, with the inexact exception raised if
73the input cannot be represented exactly as an integer. If the fixed-point
74input is too large, however, the invalid exception is raised and the largest
75positive or negative integer is returned.
76-------------------------------------------------------------------------------
77*/
78static int32 roundAndPackInt32( flag zSign, bits64 absZ )
79{
80 int8 roundingMode;
81 flag roundNearestEven;
82 int8 roundIncrement, roundBits;
83 int32 z;
84
85 roundingMode = float_rounding_mode;
86 roundNearestEven = ( roundingMode == float_round_nearest_even );
87 roundIncrement = 0x40;
88 if ( ! roundNearestEven ) {
89 if ( roundingMode == float_round_to_zero ) {
90 roundIncrement = 0;
91 }
92 else {
93 roundIncrement = 0x7F;
94 if ( zSign ) {
95 if ( roundingMode == float_round_up ) roundIncrement = 0;
96 }
97 else {
98 if ( roundingMode == float_round_down ) roundIncrement = 0;
99 }
100 }
101 }
102 roundBits = absZ & 0x7F;
103 absZ = ( absZ + roundIncrement )>>7;
104 absZ &= ~ ( ( ( roundBits ^ 0x40 ) == 0 ) & roundNearestEven );
105 z = absZ;
106 if ( zSign ) z = - z;
107 if ( ( absZ>>32 ) || ( z && ( ( z < 0 ) ^ zSign ) ) ) {
108 float_exception_flags |= float_flag_invalid;
109 return zSign ? 0x80000000 : 0x7FFFFFFF;
110 }
111 if ( roundBits ) float_exception_flags |= float_flag_inexact;
112 return z;
113
114}
115
116/*
117-------------------------------------------------------------------------------
118Returns the fraction bits of the single-precision floating-point value `a'.
119-------------------------------------------------------------------------------
120*/
121INLINE bits32 extractFloat32Frac( float32 a )
122{
123
124 return a & 0x007FFFFF;
125
126}
127
128/*
129-------------------------------------------------------------------------------
130Returns the exponent bits of the single-precision floating-point value `a'.
131-------------------------------------------------------------------------------
132*/
133INLINE int16 extractFloat32Exp( float32 a )
134{
135
136 return ( a>>23 ) & 0xFF;
137
138}
139
140/*
141-------------------------------------------------------------------------------
142Returns the sign bit of the single-precision floating-point value `a'.
143-------------------------------------------------------------------------------
144*/
145INLINE flag extractFloat32Sign( float32 a )
146{
147
148 return a>>31;
149
150}
151
152/*
153-------------------------------------------------------------------------------
154Normalizes the subnormal single-precision floating-point value represented
155by the denormalized significand `aSig'. The normalized exponent and
156significand are stored at the locations pointed to by `zExpPtr' and
157`zSigPtr', respectively.
158-------------------------------------------------------------------------------
159*/
160static void
161 normalizeFloat32Subnormal( bits32 aSig, int16 *zExpPtr, bits32 *zSigPtr )
162{
163 int8 shiftCount;
164
165 shiftCount = countLeadingZeros32( aSig ) - 8;
166 *zSigPtr = aSig<<shiftCount;
167 *zExpPtr = 1 - shiftCount;
168
169}
170
171/*
172-------------------------------------------------------------------------------
173Packs the sign `zSign', exponent `zExp', and significand `zSig' into a
174single-precision floating-point value, returning the result. After being
175shifted into the proper positions, the three fields are simply added
176together to form the result. This means that any integer portion of `zSig'
177will be added into the exponent. Since a properly normalized significand
178will have an integer portion equal to 1, the `zExp' input should be 1 less
179than the desired result exponent whenever `zSig' is a complete, normalized
180significand.
181-------------------------------------------------------------------------------
182*/
183INLINE float32 packFloat32( flag zSign, int16 zExp, bits32 zSig )
184{
185#if 0
186 float32 f;
187 __asm__("@ packFloat32; \n\
188 mov %0, %1, asl #31; \n\
189 orr %0, %2, asl #23; \n\
190 orr %0, %3"
191 : /* no outputs */
192 : "g" (f), "g" (zSign), "g" (zExp), "g" (zSig)
193 : "cc");
194 return f;
195#else
196 return ( ( (bits32) zSign )<<31 ) + ( ( (bits32) zExp )<<23 ) + zSig;
197#endif
198}
199
200/*
201-------------------------------------------------------------------------------
202Takes an abstract floating-point value having sign `zSign', exponent `zExp',
203and significand `zSig', and returns the proper single-precision floating-
204point value corresponding to the abstract input. Ordinarily, the abstract
205value is simply rounded and packed into the single-precision format, with
206the inexact exception raised if the abstract input cannot be represented
207exactly. If the abstract value is too large, however, the overflow and
208inexact exceptions are raised and an infinity or maximal finite value is
209returned. If the abstract value is too small, the input value is rounded to
210a subnormal number, and the underflow and inexact exceptions are raised if
211the abstract input cannot be represented exactly as a subnormal single-
212precision floating-point number.
213 The input significand `zSig' has its binary point between bits 30
214and 29, which is 7 bits to the left of the usual location. This shifted
215significand must be normalized or smaller. If `zSig' is not normalized,
216`zExp' must be 0; in that case, the result returned is a subnormal number,
217and it must not require rounding. In the usual case that `zSig' is
218normalized, `zExp' must be 1 less than the ``true'' floating-point exponent.
219The handling of underflow and overflow follows the IEC/IEEE Standard for
220Binary Floating-point Arithmetic.
221-------------------------------------------------------------------------------
222*/
223static float32 roundAndPackFloat32( flag zSign, int16 zExp, bits32 zSig )
224{
225 int8 roundingMode;
226 flag roundNearestEven;
227 int8 roundIncrement, roundBits;
228 flag isTiny;
229
230 roundingMode = float_rounding_mode;
231 roundNearestEven = ( roundingMode == float_round_nearest_even );
232 roundIncrement = 0x40;
233 if ( ! roundNearestEven ) {
234 if ( roundingMode == float_round_to_zero ) {
235 roundIncrement = 0;
236 }
237 else {
238 roundIncrement = 0x7F;
239 if ( zSign ) {
240 if ( roundingMode == float_round_up ) roundIncrement = 0;
241 }
242 else {
243 if ( roundingMode == float_round_down ) roundIncrement = 0;
244 }
245 }
246 }
247 roundBits = zSig & 0x7F;
248 if ( 0xFD <= (bits16) zExp ) {
249 if ( ( 0xFD < zExp )
250 || ( ( zExp == 0xFD )
251 && ( (sbits32) ( zSig + roundIncrement ) < 0 ) )
252 ) {
253 float_raise( float_flag_overflow | float_flag_inexact );
254 return packFloat32( zSign, 0xFF, 0 ) - ( roundIncrement == 0 );
255 }
256 if ( zExp < 0 ) {
257 isTiny =
258 ( float_detect_tininess == float_tininess_before_rounding )
259 || ( zExp < -1 )
260 || ( zSig + roundIncrement < 0x80000000 );
261 shift32RightJamming( zSig, - zExp, &zSig );
262 zExp = 0;
263 roundBits = zSig & 0x7F;
264 if ( isTiny && roundBits ) float_raise( float_flag_underflow );
265 }
266 }
267 if ( roundBits ) float_exception_flags |= float_flag_inexact;
268 zSig = ( zSig + roundIncrement )>>7;
269 zSig &= ~ ( ( ( roundBits ^ 0x40 ) == 0 ) & roundNearestEven );
270 if ( zSig == 0 ) zExp = 0;
271 return packFloat32( zSign, zExp, zSig );
272
273}
274
275/*
276-------------------------------------------------------------------------------
277Takes an abstract floating-point value having sign `zSign', exponent `zExp',
278and significand `zSig', and returns the proper single-precision floating-
279point value corresponding to the abstract input. This routine is just like
280`roundAndPackFloat32' except that `zSig' does not have to be normalized in
281any way. In all cases, `zExp' must be 1 less than the ``true'' floating-
282point exponent.
283-------------------------------------------------------------------------------
284*/
285static float32
286 normalizeRoundAndPackFloat32( flag zSign, int16 zExp, bits32 zSig )
287{
288 int8 shiftCount;
289
290 shiftCount = countLeadingZeros32( zSig ) - 1;
291 return roundAndPackFloat32( zSign, zExp - shiftCount, zSig<<shiftCount );
292
293}
294
295/*
296-------------------------------------------------------------------------------
297Returns the fraction bits of the double-precision floating-point value `a'.
298-------------------------------------------------------------------------------
299*/
300INLINE bits64 extractFloat64Frac( float64 a )
301{
302
303 return a & LIT64( 0x000FFFFFFFFFFFFF );
304
305}
306
307/*
308-------------------------------------------------------------------------------
309Returns the exponent bits of the double-precision floating-point value `a'.
310-------------------------------------------------------------------------------
311*/
312INLINE int16 extractFloat64Exp( float64 a )
313{
314
315 return ( a>>52 ) & 0x7FF;
316
317}
318
319/*
320-------------------------------------------------------------------------------
321Returns the sign bit of the double-precision floating-point value `a'.
322-------------------------------------------------------------------------------
323*/
324INLINE flag extractFloat64Sign( float64 a )
325{
326
327 return a>>63;
328
329}
330
331/*
332-------------------------------------------------------------------------------
333Normalizes the subnormal double-precision floating-point value represented
334by the denormalized significand `aSig'. The normalized exponent and
335significand are stored at the locations pointed to by `zExpPtr' and
336`zSigPtr', respectively.
337-------------------------------------------------------------------------------
338*/
339static void
340 normalizeFloat64Subnormal( bits64 aSig, int16 *zExpPtr, bits64 *zSigPtr )
341{
342 int8 shiftCount;
343
344 shiftCount = countLeadingZeros64( aSig ) - 11;
345 *zSigPtr = aSig<<shiftCount;
346 *zExpPtr = 1 - shiftCount;
347
348}
349
350/*
351-------------------------------------------------------------------------------
352Packs the sign `zSign', exponent `zExp', and significand `zSig' into a
353double-precision floating-point value, returning the result. After being
354shifted into the proper positions, the three fields are simply added
355together to form the result. This means that any integer portion of `zSig'
356will be added into the exponent. Since a properly normalized significand
357will have an integer portion equal to 1, the `zExp' input should be 1 less
358than the desired result exponent whenever `zSig' is a complete, normalized
359significand.
360-------------------------------------------------------------------------------
361*/
362INLINE float64 packFloat64( flag zSign, int16 zExp, bits64 zSig )
363{
364
365 return ( ( (bits64) zSign )<<63 ) + ( ( (bits64) zExp )<<52 ) + zSig;
366
367}
368
369/*
370-------------------------------------------------------------------------------
371Takes an abstract floating-point value having sign `zSign', exponent `zExp',
372and significand `zSig', and returns the proper double-precision floating-
373point value corresponding to the abstract input. Ordinarily, the abstract
374value is simply rounded and packed into the double-precision format, with
375the inexact exception raised if the abstract input cannot be represented
376exactly. If the abstract value is too large, however, the overflow and
377inexact exceptions are raised and an infinity or maximal finite value is
378returned. If the abstract value is too small, the input value is rounded to
379a subnormal number, and the underflow and inexact exceptions are raised if
380the abstract input cannot be represented exactly as a subnormal double-
381precision floating-point number.
382 The input significand `zSig' has its binary point between bits 62
383and 61, which is 10 bits to the left of the usual location. This shifted
384significand must be normalized or smaller. If `zSig' is not normalized,
385`zExp' must be 0; in that case, the result returned is a subnormal number,
386and it must not require rounding. In the usual case that `zSig' is
387normalized, `zExp' must be 1 less than the ``true'' floating-point exponent.
388The handling of underflow and overflow follows the IEC/IEEE Standard for
389Binary Floating-point Arithmetic.
390-------------------------------------------------------------------------------
391*/
392static float64 roundAndPackFloat64( flag zSign, int16 zExp, bits64 zSig )
393{
394 int8 roundingMode;
395 flag roundNearestEven;
396 int16 roundIncrement, roundBits;
397 flag isTiny;
398
399 roundingMode = float_rounding_mode;
400 roundNearestEven = ( roundingMode == float_round_nearest_even );
401 roundIncrement = 0x200;
402 if ( ! roundNearestEven ) {
403 if ( roundingMode == float_round_to_zero ) {
404 roundIncrement = 0;
405 }
406 else {
407 roundIncrement = 0x3FF;
408 if ( zSign ) {
409 if ( roundingMode == float_round_up ) roundIncrement = 0;
410 }
411 else {
412 if ( roundingMode == float_round_down ) roundIncrement = 0;
413 }
414 }
415 }
416 roundBits = zSig & 0x3FF;
417 if ( 0x7FD <= (bits16) zExp ) {
418 if ( ( 0x7FD < zExp )
419 || ( ( zExp == 0x7FD )
420 && ( (sbits64) ( zSig + roundIncrement ) < 0 ) )
421 ) {
422 //register int lr = __builtin_return_address(0);
423 //printk("roundAndPackFloat64 called from 0x%08x\n",lr);
424 float_raise( float_flag_overflow | float_flag_inexact );
425 return packFloat64( zSign, 0x7FF, 0 ) - ( roundIncrement == 0 );
426 }
427 if ( zExp < 0 ) {
428 isTiny =
429 ( float_detect_tininess == float_tininess_before_rounding )
430 || ( zExp < -1 )
431 || ( zSig + roundIncrement < LIT64( 0x8000000000000000 ) );
432 shift64RightJamming( zSig, - zExp, &zSig );
433 zExp = 0;
434 roundBits = zSig & 0x3FF;
435 if ( isTiny && roundBits ) float_raise( float_flag_underflow );
436 }
437 }
438 if ( roundBits ) float_exception_flags |= float_flag_inexact;
439 zSig = ( zSig + roundIncrement )>>10;
440 zSig &= ~ ( ( ( roundBits ^ 0x200 ) == 0 ) & roundNearestEven );
441 if ( zSig == 0 ) zExp = 0;
442 return packFloat64( zSign, zExp, zSig );
443
444}
445
446/*
447-------------------------------------------------------------------------------
448Takes an abstract floating-point value having sign `zSign', exponent `zExp',
449and significand `zSig', and returns the proper double-precision floating-
450point value corresponding to the abstract input. This routine is just like
451`roundAndPackFloat64' except that `zSig' does not have to be normalized in
452any way. In all cases, `zExp' must be 1 less than the ``true'' floating-
453point exponent.
454-------------------------------------------------------------------------------
455*/
456static float64
457 normalizeRoundAndPackFloat64( flag zSign, int16 zExp, bits64 zSig )
458{
459 int8 shiftCount;
460
461 shiftCount = countLeadingZeros64( zSig ) - 1;
462 return roundAndPackFloat64( zSign, zExp - shiftCount, zSig<<shiftCount );
463
464}
465
466#ifdef FLOATX80
467
468/*
469-------------------------------------------------------------------------------
470Returns the fraction bits of the extended double-precision floating-point
471value `a'.
472-------------------------------------------------------------------------------
473*/
474INLINE bits64 extractFloatx80Frac( floatx80 a )
475{
476
477 return a.low;
478
479}
480
481/*
482-------------------------------------------------------------------------------
483Returns the exponent bits of the extended double-precision floating-point
484value `a'.
485-------------------------------------------------------------------------------
486*/
487INLINE int32 extractFloatx80Exp( floatx80 a )
488{
489
490 return a.high & 0x7FFF;
491
492}
493
494/*
495-------------------------------------------------------------------------------
496Returns the sign bit of the extended double-precision floating-point value
497`a'.
498-------------------------------------------------------------------------------
499*/
500INLINE flag extractFloatx80Sign( floatx80 a )
501{
502
503 return a.high>>15;
504
505}
506
507/*
508-------------------------------------------------------------------------------
509Normalizes the subnormal extended double-precision floating-point value
510represented by the denormalized significand `aSig'. The normalized exponent
511and significand are stored at the locations pointed to by `zExpPtr' and
512`zSigPtr', respectively.
513-------------------------------------------------------------------------------
514*/
515static void
516 normalizeFloatx80Subnormal( bits64 aSig, int32 *zExpPtr, bits64 *zSigPtr )
517{
518 int8 shiftCount;
519
520 shiftCount = countLeadingZeros64( aSig );
521 *zSigPtr = aSig<<shiftCount;
522 *zExpPtr = 1 - shiftCount;
523
524}
525
526/*
527-------------------------------------------------------------------------------
528Packs the sign `zSign', exponent `zExp', and significand `zSig' into an
529extended double-precision floating-point value, returning the result.
530-------------------------------------------------------------------------------
531*/
532INLINE floatx80 packFloatx80( flag zSign, int32 zExp, bits64 zSig )
533{
534 floatx80 z;
535
536 z.low = zSig;
537 z.high = ( ( (bits16) zSign )<<15 ) + zExp;
538 return z;
539
540}
541
542/*
543-------------------------------------------------------------------------------
544Takes an abstract floating-point value having sign `zSign', exponent `zExp',
545and extended significand formed by the concatenation of `zSig0' and `zSig1',
546and returns the proper extended double-precision floating-point value
547corresponding to the abstract input. Ordinarily, the abstract value is
548rounded and packed into the extended double-precision format, with the
549inexact exception raised if the abstract input cannot be represented
550exactly. If the abstract value is too large, however, the overflow and
551inexact exceptions are raised and an infinity or maximal finite value is
552returned. If the abstract value is too small, the input value is rounded to
553a subnormal number, and the underflow and inexact exceptions are raised if
554the abstract input cannot be represented exactly as a subnormal extended
555double-precision floating-point number.
556 If `roundingPrecision' is 32 or 64, the result is rounded to the same
557number of bits as single or double precision, respectively. Otherwise, the
558result is rounded to the full precision of the extended double-precision
559format.
560 The input significand must be normalized or smaller. If the input
561significand is not normalized, `zExp' must be 0; in that case, the result
562returned is a subnormal number, and it must not require rounding. The
563handling of underflow and overflow follows the IEC/IEEE Standard for Binary
564Floating-point Arithmetic.
565-------------------------------------------------------------------------------
566*/
567static floatx80
568 roundAndPackFloatx80(
569 int8 roundingPrecision, flag zSign, int32 zExp, bits64 zSig0, bits64 zSig1
570 )
571{
572 int8 roundingMode;
573 flag roundNearestEven, increment, isTiny;
574 int64 roundIncrement, roundMask, roundBits;
575
576 roundingMode = float_rounding_mode;
577 roundNearestEven = ( roundingMode == float_round_nearest_even );
578 if ( roundingPrecision == 80 ) goto precision80;
579 if ( roundingPrecision == 64 ) {
580 roundIncrement = LIT64( 0x0000000000000400 );
581 roundMask = LIT64( 0x00000000000007FF );
582 }
583 else if ( roundingPrecision == 32 ) {
584 roundIncrement = LIT64( 0x0000008000000000 );
585 roundMask = LIT64( 0x000000FFFFFFFFFF );
586 }
587 else {
588 goto precision80;
589 }
590 zSig0 |= ( zSig1 != 0 );
591 if ( ! roundNearestEven ) {
592 if ( roundingMode == float_round_to_zero ) {
593 roundIncrement = 0;
594 }
595 else {
596 roundIncrement = roundMask;
597 if ( zSign ) {
598 if ( roundingMode == float_round_up ) roundIncrement = 0;
599 }
600 else {
601 if ( roundingMode == float_round_down ) roundIncrement = 0;
602 }
603 }
604 }
605 roundBits = zSig0 & roundMask;
606 if ( 0x7FFD <= (bits32) ( zExp - 1 ) ) {
607 if ( ( 0x7FFE < zExp )
608 || ( ( zExp == 0x7FFE ) && ( zSig0 + roundIncrement < zSig0 ) )
609 ) {
610 goto overflow;
611 }
612 if ( zExp <= 0 ) {
613 isTiny =
614 ( float_detect_tininess == float_tininess_before_rounding )
615 || ( zExp < 0 )
616 || ( zSig0 <= zSig0 + roundIncrement );
617 shift64RightJamming( zSig0, 1 - zExp, &zSig0 );
618 zExp = 0;
619 roundBits = zSig0 & roundMask;
620 if ( isTiny && roundBits ) float_raise( float_flag_underflow );
621 if ( roundBits ) float_exception_flags |= float_flag_inexact;
622 zSig0 += roundIncrement;
623 if ( (sbits64) zSig0 < 0 ) zExp = 1;
624 roundIncrement = roundMask + 1;
625 if ( roundNearestEven && ( roundBits<<1 == roundIncrement ) ) {
626 roundMask |= roundIncrement;
627 }
628 zSig0 &= ~ roundMask;
629 return packFloatx80( zSign, zExp, zSig0 );
630 }
631 }
632 if ( roundBits ) float_exception_flags |= float_flag_inexact;
633 zSig0 += roundIncrement;
634 if ( zSig0 < roundIncrement ) {
635 ++zExp;
636 zSig0 = LIT64( 0x8000000000000000 );
637 }
638 roundIncrement = roundMask + 1;
639 if ( roundNearestEven && ( roundBits<<1 == roundIncrement ) ) {
640 roundMask |= roundIncrement;
641 }
642 zSig0 &= ~ roundMask;
643 if ( zSig0 == 0 ) zExp = 0;
644 return packFloatx80( zSign, zExp, zSig0 );
645 precision80:
646 increment = ( (sbits64) zSig1 < 0 );
647 if ( ! roundNearestEven ) {
648 if ( roundingMode == float_round_to_zero ) {
649 increment = 0;
650 }
651 else {
652 if ( zSign ) {
653 increment = ( roundingMode == float_round_down ) && zSig1;
654 }
655 else {
656 increment = ( roundingMode == float_round_up ) && zSig1;
657 }
658 }
659 }
660 if ( 0x7FFD <= (bits32) ( zExp - 1 ) ) {
661 if ( ( 0x7FFE < zExp )
662 || ( ( zExp == 0x7FFE )
663 && ( zSig0 == LIT64( 0xFFFFFFFFFFFFFFFF ) )
664 && increment
665 )
666 ) {
667 roundMask = 0;
668 overflow:
669 float_raise( float_flag_overflow | float_flag_inexact );
670 if ( ( roundingMode == float_round_to_zero )
671 || ( zSign && ( roundingMode == float_round_up ) )
672 || ( ! zSign && ( roundingMode == float_round_down ) )
673 ) {
674 return packFloatx80( zSign, 0x7FFE, ~ roundMask );
675 }
676 return packFloatx80( zSign, 0x7FFF, LIT64( 0x8000000000000000 ) );
677 }
678 if ( zExp <= 0 ) {
679 isTiny =
680 ( float_detect_tininess == float_tininess_before_rounding )
681 || ( zExp < 0 )
682 || ! increment
683 || ( zSig0 < LIT64( 0xFFFFFFFFFFFFFFFF ) );
684 shift64ExtraRightJamming( zSig0, zSig1, 1 - zExp, &zSig0, &zSig1 );
685 zExp = 0;
686 if ( isTiny && zSig1 ) float_raise( float_flag_underflow );
687 if ( zSig1 ) float_exception_flags |= float_flag_inexact;
688 if ( roundNearestEven ) {
689 increment = ( (sbits64) zSig1 < 0 );
690 }
691 else {
692 if ( zSign ) {
693 increment = ( roundingMode == float_round_down ) && zSig1;
694 }
695 else {
696 increment = ( roundingMode == float_round_up ) && zSig1;
697 }
698 }
699 if ( increment ) {
700 ++zSig0;
701 zSig0 &= ~ ( ( zSig1 + zSig1 == 0 ) & roundNearestEven );
702 if ( (sbits64) zSig0 < 0 ) zExp = 1;
703 }
704 return packFloatx80( zSign, zExp, zSig0 );
705 }
706 }
707 if ( zSig1 ) float_exception_flags |= float_flag_inexact;
708 if ( increment ) {
709 ++zSig0;
710 if ( zSig0 == 0 ) {
711 ++zExp;
712 zSig0 = LIT64( 0x8000000000000000 );
713 }
714 else {
715 zSig0 &= ~ ( ( zSig1 + zSig1 == 0 ) & roundNearestEven );
716 }
717 }
718 else {
719 if ( zSig0 == 0 ) zExp = 0;
720 }
721
722 return packFloatx80( zSign, zExp, zSig0 );
723}
724
725/*
726-------------------------------------------------------------------------------
727Takes an abstract floating-point value having sign `zSign', exponent
728`zExp', and significand formed by the concatenation of `zSig0' and `zSig1',
729and returns the proper extended double-precision floating-point value
730corresponding to the abstract input. This routine is just like
731`roundAndPackFloatx80' except that the input significand does not have to be
732normalized.
733-------------------------------------------------------------------------------
734*/
735static floatx80
736 normalizeRoundAndPackFloatx80(
737 int8 roundingPrecision, flag zSign, int32 zExp, bits64 zSig0, bits64 zSig1
738 )
739{
740 int8 shiftCount;
741
742 if ( zSig0 == 0 ) {
743 zSig0 = zSig1;
744 zSig1 = 0;
745 zExp -= 64;
746 }
747 shiftCount = countLeadingZeros64( zSig0 );
748 shortShift128Left( zSig0, zSig1, shiftCount, &zSig0, &zSig1 );
749 zExp -= shiftCount;
750 return
751 roundAndPackFloatx80( roundingPrecision, zSign, zExp, zSig0, zSig1 );
752
753}
754
755#endif
756
757/*
758-------------------------------------------------------------------------------
759Returns the result of converting the 32-bit two's complement integer `a' to
760the single-precision floating-point format. The conversion is performed
761according to the IEC/IEEE Standard for Binary Floating-point Arithmetic.
762-------------------------------------------------------------------------------
763*/
764float32 int32_to_float32( int32 a )
765{
766 flag zSign;
767
768 if ( a == 0 ) return 0;
769 if ( a == 0x80000000 ) return packFloat32( 1, 0x9E, 0 );
770 zSign = ( a < 0 );
771 return normalizeRoundAndPackFloat32( zSign, 0x9C, zSign ? - a : a );
772
773}
774
775/*
776-------------------------------------------------------------------------------
777Returns the result of converting the 32-bit two's complement integer `a' to
778the double-precision floating-point format. The conversion is performed
779according to the IEC/IEEE Standard for Binary Floating-point Arithmetic.
780-------------------------------------------------------------------------------
781*/
782float64 int32_to_float64( int32 a )
783{
784 flag aSign;
785 uint32 absA;
786 int8 shiftCount;
787 bits64 zSig;
788
789 if ( a == 0 ) return 0;
790 aSign = ( a < 0 );
791 absA = aSign ? - a : a;
792 shiftCount = countLeadingZeros32( absA ) + 21;
793 zSig = absA;
794 return packFloat64( aSign, 0x432 - shiftCount, zSig<<shiftCount );
795
796}
797
798#ifdef FLOATX80
799
800/*
801-------------------------------------------------------------------------------
802Returns the result of converting the 32-bit two's complement integer `a'
803to the extended double-precision floating-point format. The conversion
804is performed according to the IEC/IEEE Standard for Binary Floating-point
805Arithmetic.
806-------------------------------------------------------------------------------
807*/
808floatx80 int32_to_floatx80( int32 a )
809{
810 flag zSign;
811 uint32 absA;
812 int8 shiftCount;
813 bits64 zSig;
814
815 if ( a == 0 ) return packFloatx80( 0, 0, 0 );
816 zSign = ( a < 0 );
817 absA = zSign ? - a : a;
818 shiftCount = countLeadingZeros32( absA ) + 32;
819 zSig = absA;
820 return packFloatx80( zSign, 0x403E - shiftCount, zSig<<shiftCount );
821
822}
823
824#endif
825
826/*
827-------------------------------------------------------------------------------
828Returns the result of converting the single-precision floating-point value
829`a' to the 32-bit two's complement integer format. The conversion is
830performed according to the IEC/IEEE Standard for Binary Floating-point
831Arithmetic---which means in particular that the conversion is rounded
832according to the current rounding mode. If `a' is a NaN, the largest
833positive integer is returned. Otherwise, if the conversion overflows, the
834largest integer with the same sign as `a' is returned.
835-------------------------------------------------------------------------------
836*/
837int32 float32_to_int32( float32 a )
838{
839 flag aSign;
840 int16 aExp, shiftCount;
841 bits32 aSig;
842 bits64 zSig;
843
844 aSig = extractFloat32Frac( a );
845 aExp = extractFloat32Exp( a );
846 aSign = extractFloat32Sign( a );
847 if ( ( aExp == 0x7FF ) && aSig ) aSign = 0;
848 if ( aExp ) aSig |= 0x00800000;
849 shiftCount = 0xAF - aExp;
850 zSig = aSig;
851 zSig <<= 32;
852 if ( 0 < shiftCount ) shift64RightJamming( zSig, shiftCount, &zSig );
853 return roundAndPackInt32( aSign, zSig );
854
855}
856
857/*
858-------------------------------------------------------------------------------
859Returns the result of converting the single-precision floating-point value
860`a' to the 32-bit two's complement integer format. The conversion is
861performed according to the IEC/IEEE Standard for Binary Floating-point
862Arithmetic, except that the conversion is always rounded toward zero. If
863`a' is a NaN, the largest positive integer is returned. Otherwise, if the
864conversion overflows, the largest integer with the same sign as `a' is
865returned.
866-------------------------------------------------------------------------------
867*/
868int32 float32_to_int32_round_to_zero( float32 a )
869{
870 flag aSign;
871 int16 aExp, shiftCount;
872 bits32 aSig;
873 int32 z;
874
875 aSig = extractFloat32Frac( a );
876 aExp = extractFloat32Exp( a );
877 aSign = extractFloat32Sign( a );
878 shiftCount = aExp - 0x9E;
879 if ( 0 <= shiftCount ) {
880 if ( a == 0xCF000000 ) return 0x80000000;
881 float_raise( float_flag_invalid );
882 if ( ! aSign || ( ( aExp == 0xFF ) && aSig ) ) return 0x7FFFFFFF;
883 return 0x80000000;
884 }
885 else if ( aExp <= 0x7E ) {
886 if ( aExp | aSig ) float_exception_flags |= float_flag_inexact;
887 return 0;
888 }
889 aSig = ( aSig | 0x00800000 )<<8;
890 z = aSig>>( - shiftCount );
891 if ( (bits32) ( aSig<<( shiftCount & 31 ) ) ) {
892 float_exception_flags |= float_flag_inexact;
893 }
894 return aSign ? - z : z;
895
896}
897
898/*
899-------------------------------------------------------------------------------
900Returns the result of converting the single-precision floating-point value
901`a' to the double-precision floating-point format. The conversion is
902performed according to the IEC/IEEE Standard for Binary Floating-point
903Arithmetic.
904-------------------------------------------------------------------------------
905*/
906float64 float32_to_float64( float32 a )
907{
908 flag aSign;
909 int16 aExp;
910 bits32 aSig;
911
912 aSig = extractFloat32Frac( a );
913 aExp = extractFloat32Exp( a );
914 aSign = extractFloat32Sign( a );
915 if ( aExp == 0xFF ) {
916 if ( aSig ) return commonNaNToFloat64( float32ToCommonNaN( a ) );
917 return packFloat64( aSign, 0x7FF, 0 );
918 }
919 if ( aExp == 0 ) {
920 if ( aSig == 0 ) return packFloat64( aSign, 0, 0 );
921 normalizeFloat32Subnormal( aSig, &aExp, &aSig );
922 --aExp;
923 }
924 return packFloat64( aSign, aExp + 0x380, ( (bits64) aSig )<<29 );
925
926}
927
928#ifdef FLOATX80
929
930/*
931-------------------------------------------------------------------------------
932Returns the result of converting the single-precision floating-point value
933`a' to the extended double-precision floating-point format. The conversion
934is performed according to the IEC/IEEE Standard for Binary Floating-point
935Arithmetic.
936-------------------------------------------------------------------------------
937*/
938floatx80 float32_to_floatx80( float32 a )
939{
940 flag aSign;
941 int16 aExp;
942 bits32 aSig;
943
944 aSig = extractFloat32Frac( a );
945 aExp = extractFloat32Exp( a );
946 aSign = extractFloat32Sign( a );
947 if ( aExp == 0xFF ) {
948 if ( aSig ) return commonNaNToFloatx80( float32ToCommonNaN( a ) );
949 return packFloatx80( aSign, 0x7FFF, LIT64( 0x8000000000000000 ) );
950 }
951 if ( aExp == 0 ) {
952 if ( aSig == 0 ) return packFloatx80( aSign, 0, 0 );
953 normalizeFloat32Subnormal( aSig, &aExp, &aSig );
954 }
955 aSig |= 0x00800000;
956 return packFloatx80( aSign, aExp + 0x3F80, ( (bits64) aSig )<<40 );
957
958}
959
960#endif
961
962/*
963-------------------------------------------------------------------------------
964Rounds the single-precision floating-point value `a' to an integer, and
965returns the result as a single-precision floating-point value. The
966operation is performed according to the IEC/IEEE Standard for Binary
967Floating-point Arithmetic.
968-------------------------------------------------------------------------------
969*/
970float32 float32_round_to_int( float32 a )
971{
972 flag aSign;
973 int16 aExp;
974 bits32 lastBitMask, roundBitsMask;
975 int8 roundingMode;
976 float32 z;
977
978 aExp = extractFloat32Exp( a );
979 if ( 0x96 <= aExp ) {
980 if ( ( aExp == 0xFF ) && extractFloat32Frac( a ) ) {
981 return propagateFloat32NaN( a, a );
982 }
983 return a;
984 }
985 if ( aExp <= 0x7E ) {
986 if ( (bits32) ( a<<1 ) == 0 ) return a;
987 float_exception_flags |= float_flag_inexact;
988 aSign = extractFloat32Sign( a );
989 switch ( float_rounding_mode ) {
990 case float_round_nearest_even:
991 if ( ( aExp == 0x7E ) && extractFloat32Frac( a ) ) {
992 return packFloat32( aSign, 0x7F, 0 );
993 }
994 break;
995 case float_round_down:
996 return aSign ? 0xBF800000 : 0;
997 case float_round_up:
998 return aSign ? 0x80000000 : 0x3F800000;
999 }
1000 return packFloat32( aSign, 0, 0 );
1001 }
1002 lastBitMask = 1;
1003 lastBitMask <<= 0x96 - aExp;
1004 roundBitsMask = lastBitMask - 1;
1005 z = a;
1006 roundingMode = float_rounding_mode;
1007 if ( roundingMode == float_round_nearest_even ) {
1008 z += lastBitMask>>1;
1009 if ( ( z & roundBitsMask ) == 0 ) z &= ~ lastBitMask;
1010 }
1011 else if ( roundingMode != float_round_to_zero ) {
1012 if ( extractFloat32Sign( z ) ^ ( roundingMode == float_round_up ) ) {
1013 z += roundBitsMask;
1014 }
1015 }
1016 z &= ~ roundBitsMask;
1017 if ( z != a ) float_exception_flags |= float_flag_inexact;
1018 return z;
1019
1020}
1021
1022/*
1023-------------------------------------------------------------------------------
1024Returns the result of adding the absolute values of the single-precision
1025floating-point values `a' and `b'. If `zSign' is true, the sum is negated
1026before being returned. `zSign' is ignored if the result is a NaN. The
1027addition is performed according to the IEC/IEEE Standard for Binary
1028Floating-point Arithmetic.
1029-------------------------------------------------------------------------------
1030*/
1031static float32 addFloat32Sigs( float32 a, float32 b, flag zSign )
1032{
1033 int16 aExp, bExp, zExp;
1034 bits32 aSig, bSig, zSig;
1035 int16 expDiff;
1036
1037 aSig = extractFloat32Frac( a );
1038 aExp = extractFloat32Exp( a );
1039 bSig = extractFloat32Frac( b );
1040 bExp = extractFloat32Exp( b );
1041 expDiff = aExp - bExp;
1042 aSig <<= 6;
1043 bSig <<= 6;
1044 if ( 0 < expDiff ) {
1045 if ( aExp == 0xFF ) {
1046 if ( aSig ) return propagateFloat32NaN( a, b );
1047 return a;
1048 }
1049 if ( bExp == 0 ) {
1050 --expDiff;
1051 }
1052 else {
1053 bSig |= 0x20000000;
1054 }
1055 shift32RightJamming( bSig, expDiff, &bSig );
1056 zExp = aExp;
1057 }
1058 else if ( expDiff < 0 ) {
1059 if ( bExp == 0xFF ) {
1060 if ( bSig ) return propagateFloat32NaN( a, b );
1061 return packFloat32( zSign, 0xFF, 0 );
1062 }
1063 if ( aExp == 0 ) {
1064 ++expDiff;
1065 }
1066 else {
1067 aSig |= 0x20000000;
1068 }
1069 shift32RightJamming( aSig, - expDiff, &aSig );
1070 zExp = bExp;
1071 }
1072 else {
1073 if ( aExp == 0xFF ) {
1074 if ( aSig | bSig ) return propagateFloat32NaN( a, b );
1075 return a;
1076 }
1077 if ( aExp == 0 ) return packFloat32( zSign, 0, ( aSig + bSig )>>6 );
1078 zSig = 0x40000000 + aSig + bSig;
1079 zExp = aExp;
1080 goto roundAndPack;
1081 }
1082 aSig |= 0x20000000;
1083 zSig = ( aSig + bSig )<<1;
1084 --zExp;
1085 if ( (sbits32) zSig < 0 ) {
1086 zSig = aSig + bSig;
1087 ++zExp;
1088 }
1089 roundAndPack:
1090 return roundAndPackFloat32( zSign, zExp, zSig );
1091
1092}
1093
1094/*
1095-------------------------------------------------------------------------------
1096Returns the result of subtracting the absolute values of the single-
1097precision floating-point values `a' and `b'. If `zSign' is true, the
1098difference is negated before being returned. `zSign' is ignored if the
1099result is a NaN. The subtraction is performed according to the IEC/IEEE
1100Standard for Binary Floating-point Arithmetic.
1101-------------------------------------------------------------------------------
1102*/
1103static float32 subFloat32Sigs( float32 a, float32 b, flag zSign )
1104{
1105 int16 aExp, bExp, zExp;
1106 bits32 aSig, bSig, zSig;
1107 int16 expDiff;
1108
1109 aSig = extractFloat32Frac( a );
1110 aExp = extractFloat32Exp( a );
1111 bSig = extractFloat32Frac( b );
1112 bExp = extractFloat32Exp( b );
1113 expDiff = aExp - bExp;
1114 aSig <<= 7;
1115 bSig <<= 7;
1116 if ( 0 < expDiff ) goto aExpBigger;
1117 if ( expDiff < 0 ) goto bExpBigger;
1118 if ( aExp == 0xFF ) {
1119 if ( aSig | bSig ) return propagateFloat32NaN( a, b );
1120 float_raise( float_flag_invalid );
1121 return float32_default_nan;
1122 }
1123 if ( aExp == 0 ) {
1124 aExp = 1;
1125 bExp = 1;
1126 }
1127 if ( bSig < aSig ) goto aBigger;
1128 if ( aSig < bSig ) goto bBigger;
1129 return packFloat32( float_rounding_mode == float_round_down, 0, 0 );
1130 bExpBigger:
1131 if ( bExp == 0xFF ) {
1132 if ( bSig ) return propagateFloat32NaN( a, b );
1133 return packFloat32( zSign ^ 1, 0xFF, 0 );
1134 }
1135 if ( aExp == 0 ) {
1136 ++expDiff;
1137 }
1138 else {
1139 aSig |= 0x40000000;
1140 }
1141 shift32RightJamming( aSig, - expDiff, &aSig );
1142 bSig |= 0x40000000;
1143 bBigger:
1144 zSig = bSig - aSig;
1145 zExp = bExp;
1146 zSign ^= 1;
1147 goto normalizeRoundAndPack;
1148 aExpBigger:
1149 if ( aExp == 0xFF ) {
1150 if ( aSig ) return propagateFloat32NaN( a, b );
1151 return a;
1152 }
1153 if ( bExp == 0 ) {
1154 --expDiff;
1155 }
1156 else {
1157 bSig |= 0x40000000;
1158 }
1159 shift32RightJamming( bSig, expDiff, &bSig );
1160 aSig |= 0x40000000;
1161 aBigger:
1162 zSig = aSig - bSig;
1163 zExp = aExp;
1164 normalizeRoundAndPack:
1165 --zExp;
1166 return normalizeRoundAndPackFloat32( zSign, zExp, zSig );
1167
1168}
1169
1170/*
1171-------------------------------------------------------------------------------
1172Returns the result of adding the single-precision floating-point values `a'
1173and `b'. The operation is performed according to the IEC/IEEE Standard for
1174Binary Floating-point Arithmetic.
1175-------------------------------------------------------------------------------
1176*/
1177float32 float32_add( float32 a, float32 b )
1178{
1179 flag aSign, bSign;
1180
1181 aSign = extractFloat32Sign( a );
1182 bSign = extractFloat32Sign( b );
1183 if ( aSign == bSign ) {
1184 return addFloat32Sigs( a, b, aSign );
1185 }
1186 else {
1187 return subFloat32Sigs( a, b, aSign );
1188 }
1189
1190}
1191
1192/*
1193-------------------------------------------------------------------------------
1194Returns the result of subtracting the single-precision floating-point values
1195`a' and `b'. The operation is performed according to the IEC/IEEE Standard
1196for Binary Floating-point Arithmetic.
1197-------------------------------------------------------------------------------
1198*/
1199float32 float32_sub( float32 a, float32 b )
1200{
1201 flag aSign, bSign;
1202
1203 aSign = extractFloat32Sign( a );
1204 bSign = extractFloat32Sign( b );
1205 if ( aSign == bSign ) {
1206 return subFloat32Sigs( a, b, aSign );
1207 }
1208 else {
1209 return addFloat32Sigs( a, b, aSign );
1210 }
1211
1212}
1213
1214/*
1215-------------------------------------------------------------------------------
1216Returns the result of multiplying the single-precision floating-point values
1217`a' and `b'. The operation is performed according to the IEC/IEEE Standard
1218for Binary Floating-point Arithmetic.
1219-------------------------------------------------------------------------------
1220*/
1221float32 float32_mul( float32 a, float32 b )
1222{
1223 flag aSign, bSign, zSign;
1224 int16 aExp, bExp, zExp;
1225 bits32 aSig, bSig;
1226 bits64 zSig64;
1227 bits32 zSig;
1228
1229 aSig = extractFloat32Frac( a );
1230 aExp = extractFloat32Exp( a );
1231 aSign = extractFloat32Sign( a );
1232 bSig = extractFloat32Frac( b );
1233 bExp = extractFloat32Exp( b );
1234 bSign = extractFloat32Sign( b );
1235 zSign = aSign ^ bSign;
1236 if ( aExp == 0xFF ) {
1237 if ( aSig || ( ( bExp == 0xFF ) && bSig ) ) {
1238 return propagateFloat32NaN( a, b );
1239 }
1240 if ( ( bExp | bSig ) == 0 ) {
1241 float_raise( float_flag_invalid );
1242 return float32_default_nan;
1243 }
1244 return packFloat32( zSign, 0xFF, 0 );
1245 }
1246 if ( bExp == 0xFF ) {
1247 if ( bSig ) return propagateFloat32NaN( a, b );
1248 if ( ( aExp | aSig ) == 0 ) {
1249 float_raise( float_flag_invalid );
1250 return float32_default_nan;
1251 }
1252 return packFloat32( zSign, 0xFF, 0 );
1253 }
1254 if ( aExp == 0 ) {
1255 if ( aSig == 0 ) return packFloat32( zSign, 0, 0 );
1256 normalizeFloat32Subnormal( aSig, &aExp, &aSig );
1257 }
1258 if ( bExp == 0 ) {
1259 if ( bSig == 0 ) return packFloat32( zSign, 0, 0 );
1260 normalizeFloat32Subnormal( bSig, &bExp, &bSig );
1261 }
1262 zExp = aExp + bExp - 0x7F;
1263 aSig = ( aSig | 0x00800000 )<<7;
1264 bSig = ( bSig | 0x00800000 )<<8;
1265 shift64RightJamming( ( (bits64) aSig ) * bSig, 32, &zSig64 );
1266 zSig = zSig64;
1267 if ( 0 <= (sbits32) ( zSig<<1 ) ) {
1268 zSig <<= 1;
1269 --zExp;
1270 }
1271 return roundAndPackFloat32( zSign, zExp, zSig );
1272
1273}
1274
1275/*
1276-------------------------------------------------------------------------------
1277Returns the result of dividing the single-precision floating-point value `a'
1278by the corresponding value `b'. The operation is performed according to the
1279IEC/IEEE Standard for Binary Floating-point Arithmetic.
1280-------------------------------------------------------------------------------
1281*/
1282float32 float32_div( float32 a, float32 b )
1283{
1284 flag aSign, bSign, zSign;
1285 int16 aExp, bExp, zExp;
1286 bits32 aSig, bSig, zSig;
1287
1288 aSig = extractFloat32Frac( a );
1289 aExp = extractFloat32Exp( a );
1290 aSign = extractFloat32Sign( a );
1291 bSig = extractFloat32Frac( b );
1292 bExp = extractFloat32Exp( b );
1293 bSign = extractFloat32Sign( b );
1294 zSign = aSign ^ bSign;
1295 if ( aExp == 0xFF ) {
1296 if ( aSig ) return propagateFloat32NaN( a, b );
1297 if ( bExp == 0xFF ) {
1298 if ( bSig ) return propagateFloat32NaN( a, b );
1299 float_raise( float_flag_invalid );
1300 return float32_default_nan;
1301 }
1302 return packFloat32( zSign, 0xFF, 0 );
1303 }
1304 if ( bExp == 0xFF ) {
1305 if ( bSig ) return propagateFloat32NaN( a, b );
1306 return packFloat32( zSign, 0, 0 );
1307 }
1308 if ( bExp == 0 ) {
1309 if ( bSig == 0 ) {
1310 if ( ( aExp | aSig ) == 0 ) {
1311 float_raise( float_flag_invalid );
1312 return float32_default_nan;
1313 }
1314 float_raise( float_flag_divbyzero );
1315 return packFloat32( zSign, 0xFF, 0 );
1316 }
1317 normalizeFloat32Subnormal( bSig, &bExp, &bSig );
1318 }
1319 if ( aExp == 0 ) {
1320 if ( aSig == 0 ) return packFloat32( zSign, 0, 0 );
1321 normalizeFloat32Subnormal( aSig, &aExp, &aSig );
1322 }
1323 zExp = aExp - bExp + 0x7D;
1324 aSig = ( aSig | 0x00800000 )<<7;
1325 bSig = ( bSig | 0x00800000 )<<8;
1326 if ( bSig <= ( aSig + aSig ) ) {
1327 aSig >>= 1;
1328 ++zExp;
1329 }
1330 zSig = ( ( (bits64) aSig )<<32 ) / bSig;
1331 if ( ( zSig & 0x3F ) == 0 ) {
1332 zSig |= ( ( (bits64) bSig ) * zSig != ( (bits64) aSig )<<32 );
1333 }
1334 return roundAndPackFloat32( zSign, zExp, zSig );
1335
1336}
1337
1338/*
1339-------------------------------------------------------------------------------
1340Returns the remainder of the single-precision floating-point value `a'
1341with respect to the corresponding value `b'. The operation is performed
1342according to the IEC/IEEE Standard for Binary Floating-point Arithmetic.
1343-------------------------------------------------------------------------------
1344*/
1345float32 float32_rem( float32 a, float32 b )
1346{
1347 flag aSign, bSign, zSign;
1348 int16 aExp, bExp, expDiff;
1349 bits32 aSig, bSig;
1350 bits32 q;
1351 bits64 aSig64, bSig64, q64;
1352 bits32 alternateASig;
1353 sbits32 sigMean;
1354
1355 aSig = extractFloat32Frac( a );
1356 aExp = extractFloat32Exp( a );
1357 aSign = extractFloat32Sign( a );
1358 bSig = extractFloat32Frac( b );
1359 bExp = extractFloat32Exp( b );
1360 bSign = extractFloat32Sign( b );
1361 if ( aExp == 0xFF ) {
1362 if ( aSig || ( ( bExp == 0xFF ) && bSig ) ) {
1363 return propagateFloat32NaN( a, b );
1364 }
1365 float_raise( float_flag_invalid );
1366 return float32_default_nan;
1367 }
1368 if ( bExp == 0xFF ) {
1369 if ( bSig ) return propagateFloat32NaN( a, b );
1370 return a;
1371 }
1372 if ( bExp == 0 ) {
1373 if ( bSig == 0 ) {
1374 float_raise( float_flag_invalid );
1375 return float32_default_nan;
1376 }
1377 normalizeFloat32Subnormal( bSig, &bExp, &bSig );
1378 }
1379 if ( aExp == 0 ) {
1380 if ( aSig == 0 ) return a;
1381 normalizeFloat32Subnormal( aSig, &aExp, &aSig );
1382 }
1383 expDiff = aExp - bExp;
1384 aSig |= 0x00800000;
1385 bSig |= 0x00800000;
1386 if ( expDiff < 32 ) {
1387 aSig <<= 8;
1388 bSig <<= 8;
1389 if ( expDiff < 0 ) {
1390 if ( expDiff < -1 ) return a;
1391 aSig >>= 1;
1392 }
1393 q = ( bSig <= aSig );
1394 if ( q ) aSig -= bSig;
1395 if ( 0 < expDiff ) {
1396 q = ( ( (bits64) aSig )<<32 ) / bSig;
1397 q >>= 32 - expDiff;
1398 bSig >>= 2;
1399 aSig = ( ( aSig>>1 )<<( expDiff - 1 ) ) - bSig * q;
1400 }
1401 else {
1402 aSig >>= 2;
1403 bSig >>= 2;
1404 }
1405 }
1406 else {
1407 if ( bSig <= aSig ) aSig -= bSig;
1408 aSig64 = ( (bits64) aSig )<<40;
1409 bSig64 = ( (bits64) bSig )<<40;
1410 expDiff -= 64;
1411 while ( 0 < expDiff ) {
1412 q64 = estimateDiv128To64( aSig64, 0, bSig64 );
1413 q64 = ( 2 < q64 ) ? q64 - 2 : 0;
1414 aSig64 = - ( ( bSig * q64 )<<38 );
1415 expDiff -= 62;
1416 }
1417 expDiff += 64;
1418 q64 = estimateDiv128To64( aSig64, 0, bSig64 );
1419 q64 = ( 2 < q64 ) ? q64 - 2 : 0;
1420 q = q64>>( 64 - expDiff );
1421 bSig <<= 6;
1422 aSig = ( ( aSig64>>33 )<<( expDiff - 1 ) ) - bSig * q;
1423 }
1424 do {
1425 alternateASig = aSig;
1426 ++q;
1427 aSig -= bSig;
1428 } while ( 0 <= (sbits32) aSig );
1429 sigMean = aSig + alternateASig;
1430 if ( ( sigMean < 0 ) || ( ( sigMean == 0 ) && ( q & 1 ) ) ) {
1431 aSig = alternateASig;
1432 }
1433 zSign = ( (sbits32) aSig < 0 );
1434 if ( zSign ) aSig = - aSig;
1435 return normalizeRoundAndPackFloat32( aSign ^ zSign, bExp, aSig );
1436
1437}
1438
1439/*
1440-------------------------------------------------------------------------------
1441Returns the square root of the single-precision floating-point value `a'.
1442The operation is performed according to the IEC/IEEE Standard for Binary
1443Floating-point Arithmetic.
1444-------------------------------------------------------------------------------
1445*/
1446float32 float32_sqrt( float32 a )
1447{
1448 flag aSign;
1449 int16 aExp, zExp;
1450 bits32 aSig, zSig;
1451 bits64 rem, term;
1452
1453 aSig = extractFloat32Frac( a );
1454 aExp = extractFloat32Exp( a );
1455 aSign = extractFloat32Sign( a );
1456 if ( aExp == 0xFF ) {
1457 if ( aSig ) return propagateFloat32NaN( a, 0 );
1458 if ( ! aSign ) return a;
1459 float_raise( float_flag_invalid );
1460 return float32_default_nan;
1461 }
1462 if ( aSign ) {
1463 if ( ( aExp | aSig ) == 0 ) return a;
1464 float_raise( float_flag_invalid );
1465 return float32_default_nan;
1466 }
1467 if ( aExp == 0 ) {
1468 if ( aSig == 0 ) return 0;
1469 normalizeFloat32Subnormal( aSig, &aExp, &aSig );
1470 }
1471 zExp = ( ( aExp - 0x7F )>>1 ) + 0x7E;
1472 aSig = ( aSig | 0x00800000 )<<8;
1473 zSig = estimateSqrt32( aExp, aSig ) + 2;
1474 if ( ( zSig & 0x7F ) <= 5 ) {
1475 if ( zSig < 2 ) {
1476 zSig = 0xFFFFFFFF;
1477 }
1478 else {
1479 aSig >>= aExp & 1;
1480 term = ( (bits64) zSig ) * zSig;
1481 rem = ( ( (bits64) aSig )<<32 ) - term;
1482 while ( (sbits64) rem < 0 ) {
1483 --zSig;
1484 rem += ( ( (bits64) zSig )<<1 ) | 1;
1485 }
1486 zSig |= ( rem != 0 );
1487 }
1488 }
1489 shift32RightJamming( zSig, 1, &zSig );
1490 return roundAndPackFloat32( 0, zExp, zSig );
1491
1492}
1493
1494/*
1495-------------------------------------------------------------------------------
1496Returns 1 if the single-precision floating-point value `a' is equal to the
1497corresponding value `b', and 0 otherwise. The comparison is performed
1498according to the IEC/IEEE Standard for Binary Floating-point Arithmetic.
1499-------------------------------------------------------------------------------
1500*/
1501flag float32_eq( float32 a, float32 b )
1502{
1503
1504 if ( ( ( extractFloat32Exp( a ) == 0xFF ) && extractFloat32Frac( a ) )
1505 || ( ( extractFloat32Exp( b ) == 0xFF ) && extractFloat32Frac( b ) )
1506 ) {
1507 if ( float32_is_signaling_nan( a ) || float32_is_signaling_nan( b ) ) {
1508 float_raise( float_flag_invalid );
1509 }
1510 return 0;
1511 }
1512 return ( a == b ) || ( (bits32) ( ( a | b )<<1 ) == 0 );
1513
1514}
1515
1516/*
1517-------------------------------------------------------------------------------
1518Returns 1 if the single-precision floating-point value `a' is less than or
1519equal to the corresponding value `b', and 0 otherwise. The comparison is
1520performed according to the IEC/IEEE Standard for Binary Floating-point
1521Arithmetic.
1522-------------------------------------------------------------------------------
1523*/
1524flag float32_le( float32 a, float32 b )
1525{
1526 flag aSign, bSign;
1527
1528 if ( ( ( extractFloat32Exp( a ) == 0xFF ) && extractFloat32Frac( a ) )
1529 || ( ( extractFloat32Exp( b ) == 0xFF ) && extractFloat32Frac( b ) )
1530 ) {
1531 float_raise( float_flag_invalid );
1532 return 0;
1533 }
1534 aSign = extractFloat32Sign( a );
1535 bSign = extractFloat32Sign( b );
1536 if ( aSign != bSign ) return aSign || ( (bits32) ( ( a | b )<<1 ) == 0 );
1537 return ( a == b ) || ( aSign ^ ( a < b ) );
1538
1539}
1540
1541/*
1542-------------------------------------------------------------------------------
1543Returns 1 if the single-precision floating-point value `a' is less than
1544the corresponding value `b', and 0 otherwise. The comparison is performed
1545according to the IEC/IEEE Standard for Binary Floating-point Arithmetic.
1546-------------------------------------------------------------------------------
1547*/
1548flag float32_lt( float32 a, float32 b )
1549{
1550 flag aSign, bSign;
1551
1552 if ( ( ( extractFloat32Exp( a ) == 0xFF ) && extractFloat32Frac( a ) )
1553 || ( ( extractFloat32Exp( b ) == 0xFF ) && extractFloat32Frac( b ) )
1554 ) {
1555 float_raise( float_flag_invalid );
1556 return 0;
1557 }
1558 aSign = extractFloat32Sign( a );
1559 bSign = extractFloat32Sign( b );
1560 if ( aSign != bSign ) return aSign && ( (bits32) ( ( a | b )<<1 ) != 0 );
1561 return ( a != b ) && ( aSign ^ ( a < b ) );
1562
1563}
1564
1565/*
1566-------------------------------------------------------------------------------
1567Returns 1 if the single-precision floating-point value `a' is equal to the
1568corresponding value `b', and 0 otherwise. The invalid exception is raised
1569if either operand is a NaN. Otherwise, the comparison is performed
1570according to the IEC/IEEE Standard for Binary Floating-point Arithmetic.
1571-------------------------------------------------------------------------------
1572*/
1573flag float32_eq_signaling( float32 a, float32 b )
1574{
1575
1576 if ( ( ( extractFloat32Exp( a ) == 0xFF ) && extractFloat32Frac( a ) )
1577 || ( ( extractFloat32Exp( b ) == 0xFF ) && extractFloat32Frac( b ) )
1578 ) {
1579 float_raise( float_flag_invalid );
1580 return 0;
1581 }
1582 return ( a == b ) || ( (bits32) ( ( a | b )<<1 ) == 0 );
1583
1584}
1585
1586/*
1587-------------------------------------------------------------------------------
1588Returns 1 if the single-precision floating-point value `a' is less than or
1589equal to the corresponding value `b', and 0 otherwise. Quiet NaNs do not
1590cause an exception. Otherwise, the comparison is performed according to the
1591IEC/IEEE Standard for Binary Floating-point Arithmetic.
1592-------------------------------------------------------------------------------
1593*/
1594flag float32_le_quiet( float32 a, float32 b )
1595{
1596 flag aSign, bSign;
1597 //int16 aExp, bExp;
1598
1599 if ( ( ( extractFloat32Exp( a ) == 0xFF ) && extractFloat32Frac( a ) )
1600 || ( ( extractFloat32Exp( b ) == 0xFF ) && extractFloat32Frac( b ) )
1601 ) {
1602 if ( float32_is_signaling_nan( a ) || float32_is_signaling_nan( b ) ) {
1603 float_raise( float_flag_invalid );
1604 }
1605 return 0;
1606 }
1607 aSign = extractFloat32Sign( a );
1608 bSign = extractFloat32Sign( b );
1609 if ( aSign != bSign ) return aSign || ( (bits32) ( ( a | b )<<1 ) == 0 );
1610 return ( a == b ) || ( aSign ^ ( a < b ) );
1611
1612}
1613
1614/*
1615-------------------------------------------------------------------------------
1616Returns 1 if the single-precision floating-point value `a' is less than
1617the corresponding value `b', and 0 otherwise. Quiet NaNs do not cause an
1618exception. Otherwise, the comparison is performed according to the IEC/IEEE
1619Standard for Binary Floating-point Arithmetic.
1620-------------------------------------------------------------------------------
1621*/
1622flag float32_lt_quiet( float32 a, float32 b )
1623{
1624 flag aSign, bSign;
1625
1626 if ( ( ( extractFloat32Exp( a ) == 0xFF ) && extractFloat32Frac( a ) )
1627 || ( ( extractFloat32Exp( b ) == 0xFF ) && extractFloat32Frac( b ) )
1628 ) {
1629 if ( float32_is_signaling_nan( a ) || float32_is_signaling_nan( b ) ) {
1630 float_raise( float_flag_invalid );
1631 }
1632 return 0;
1633 }
1634 aSign = extractFloat32Sign( a );
1635 bSign = extractFloat32Sign( b );
1636 if ( aSign != bSign ) return aSign && ( (bits32) ( ( a | b )<<1 ) != 0 );
1637 return ( a != b ) && ( aSign ^ ( a < b ) );
1638
1639}
1640
1641/*
1642-------------------------------------------------------------------------------
1643Returns the result of converting the double-precision floating-point value
1644`a' to the 32-bit two's complement integer format. The conversion is
1645performed according to the IEC/IEEE Standard for Binary Floating-point
1646Arithmetic---which means in particular that the conversion is rounded
1647according to the current rounding mode. If `a' is a NaN, the largest
1648positive integer is returned. Otherwise, if the conversion overflows, the
1649largest integer with the same sign as `a' is returned.
1650-------------------------------------------------------------------------------
1651*/
1652int32 float64_to_int32( float64 a )
1653{
1654 flag aSign;
1655 int16 aExp, shiftCount;
1656 bits64 aSig;
1657
1658 aSig = extractFloat64Frac( a );
1659 aExp = extractFloat64Exp( a );
1660 aSign = extractFloat64Sign( a );
1661 if ( ( aExp == 0x7FF ) && aSig ) aSign = 0;
1662 if ( aExp ) aSig |= LIT64( 0x0010000000000000 );
1663 shiftCount = 0x42C - aExp;
1664 if ( 0 < shiftCount ) shift64RightJamming( aSig, shiftCount, &aSig );
1665 return roundAndPackInt32( aSign, aSig );
1666
1667}
1668
1669/*
1670-------------------------------------------------------------------------------
1671Returns the result of converting the double-precision floating-point value
1672`a' to the 32-bit two's complement integer format. The conversion is
1673performed according to the IEC/IEEE Standard for Binary Floating-point
1674Arithmetic, except that the conversion is always rounded toward zero. If
1675`a' is a NaN, the largest positive integer is returned. Otherwise, if the
1676conversion overflows, the largest integer with the same sign as `a' is
1677returned.
1678-------------------------------------------------------------------------------
1679*/
1680int32 float64_to_int32_round_to_zero( float64 a )
1681{
1682 flag aSign;
1683 int16 aExp, shiftCount;
1684 bits64 aSig, savedASig;
1685 int32 z;
1686
1687 aSig = extractFloat64Frac( a );
1688 aExp = extractFloat64Exp( a );
1689 aSign = extractFloat64Sign( a );
1690 shiftCount = 0x433 - aExp;
1691 if ( shiftCount < 21 ) {
1692 if ( ( aExp == 0x7FF ) && aSig ) aSign = 0;
1693 goto invalid;
1694 }
1695 else if ( 52 < shiftCount ) {
1696 if ( aExp || aSig ) float_exception_flags |= float_flag_inexact;
1697 return 0;
1698 }
1699 aSig |= LIT64( 0x0010000000000000 );
1700 savedASig = aSig;
1701 aSig >>= shiftCount;
1702 z = aSig;
1703 if ( aSign ) z = - z;
1704 if ( ( z < 0 ) ^ aSign ) {
1705 invalid:
1706 float_exception_flags |= float_flag_invalid;
1707 return aSign ? 0x80000000 : 0x7FFFFFFF;
1708 }
1709 if ( ( aSig<<shiftCount ) != savedASig ) {
1710 float_exception_flags |= float_flag_inexact;
1711 }
1712 return z;
1713
1714}
1715
1716/*
1717-------------------------------------------------------------------------------
1718Returns the result of converting the double-precision floating-point value
1719`a' to the 32-bit two's complement unsigned integer format. The conversion
1720is performed according to the IEC/IEEE Standard for Binary Floating-point
1721Arithmetic---which means in particular that the conversion is rounded
1722according to the current rounding mode. If `a' is a NaN, the largest
1723positive integer is returned. Otherwise, if the conversion overflows, the
1724largest positive integer is returned.
1725-------------------------------------------------------------------------------
1726*/
1727int32 float64_to_uint32( float64 a )
1728{
1729 flag aSign;
1730 int16 aExp, shiftCount;
1731 bits64 aSig;
1732
1733 aSig = extractFloat64Frac( a );
1734 aExp = extractFloat64Exp( a );
1735 aSign = 0; //extractFloat64Sign( a );
1736 //if ( ( aExp == 0x7FF ) && aSig ) aSign = 0;
1737 if ( aExp ) aSig |= LIT64( 0x0010000000000000 );
1738 shiftCount = 0x42C - aExp;
1739 if ( 0 < shiftCount ) shift64RightJamming( aSig, shiftCount, &aSig );
1740 return roundAndPackInt32( aSign, aSig );
1741}
1742
1743/*
1744-------------------------------------------------------------------------------
1745Returns the result of converting the double-precision floating-point value
1746`a' to the 32-bit two's complement integer format. The conversion is
1747performed according to the IEC/IEEE Standard for Binary Floating-point
1748Arithmetic, except that the conversion is always rounded toward zero. If
1749`a' is a NaN, the largest positive integer is returned. Otherwise, if the
1750conversion overflows, the largest positive integer is returned.
1751-------------------------------------------------------------------------------
1752*/
1753int32 float64_to_uint32_round_to_zero( float64 a )
1754{
1755 flag aSign;
1756 int16 aExp, shiftCount;
1757 bits64 aSig, savedASig;
1758 int32 z;
1759
1760 aSig = extractFloat64Frac( a );
1761 aExp = extractFloat64Exp( a );
1762 aSign = extractFloat64Sign( a );
1763 shiftCount = 0x433 - aExp;
1764 if ( shiftCount < 21 ) {
1765 if ( ( aExp == 0x7FF ) && aSig ) aSign = 0;
1766 goto invalid;
1767 }
1768 else if ( 52 < shiftCount ) {
1769 if ( aExp || aSig ) float_exception_flags |= float_flag_inexact;
1770 return 0;
1771 }
1772 aSig |= LIT64( 0x0010000000000000 );
1773 savedASig = aSig;
1774 aSig >>= shiftCount;
1775 z = aSig;
1776 if ( aSign ) z = - z;
1777 if ( ( z < 0 ) ^ aSign ) {
1778 invalid:
1779 float_exception_flags |= float_flag_invalid;
1780 return aSign ? 0x80000000 : 0x7FFFFFFF;
1781 }
1782 if ( ( aSig<<shiftCount ) != savedASig ) {
1783 float_exception_flags |= float_flag_inexact;
1784 }
1785 return z;
1786}
1787
1788/*
1789-------------------------------------------------------------------------------
1790Returns the result of converting the double-precision floating-point value
1791`a' to the single-precision floating-point format. The conversion is
1792performed according to the IEC/IEEE Standard for Binary Floating-point
1793Arithmetic.
1794-------------------------------------------------------------------------------
1795*/
1796float32 float64_to_float32( float64 a )
1797{
1798 flag aSign;
1799 int16 aExp;
1800 bits64 aSig;
1801 bits32 zSig;
1802
1803 aSig = extractFloat64Frac( a );
1804 aExp = extractFloat64Exp( a );
1805 aSign = extractFloat64Sign( a );
1806 if ( aExp == 0x7FF ) {
1807 if ( aSig ) return commonNaNToFloat32( float64ToCommonNaN( a ) );
1808 return packFloat32( aSign, 0xFF, 0 );
1809 }
1810 shift64RightJamming( aSig, 22, &aSig );
1811 zSig = aSig;
1812 if ( aExp || zSig ) {
1813 zSig |= 0x40000000;
1814 aExp -= 0x381;
1815 }
1816 return roundAndPackFloat32( aSign, aExp, zSig );
1817
1818}
1819
1820#ifdef FLOATX80
1821
1822/*
1823-------------------------------------------------------------------------------
1824Returns the result of converting the double-precision floating-point value
1825`a' to the extended double-precision floating-point format. The conversion
1826is performed according to the IEC/IEEE Standard for Binary Floating-point
1827Arithmetic.
1828-------------------------------------------------------------------------------
1829*/
1830floatx80 float64_to_floatx80( float64 a )
1831{
1832 flag aSign;
1833 int16 aExp;
1834 bits64 aSig;
1835
1836 aSig = extractFloat64Frac( a );
1837 aExp = extractFloat64Exp( a );
1838 aSign = extractFloat64Sign( a );
1839 if ( aExp == 0x7FF ) {
1840 if ( aSig ) return commonNaNToFloatx80( float64ToCommonNaN( a ) );
1841 return packFloatx80( aSign, 0x7FFF, LIT64( 0x8000000000000000 ) );
1842 }
1843 if ( aExp == 0 ) {
1844 if ( aSig == 0 ) return packFloatx80( aSign, 0, 0 );
1845 normalizeFloat64Subnormal( aSig, &aExp, &aSig );
1846 }
1847 return
1848 packFloatx80(
1849 aSign, aExp + 0x3C00, ( aSig | LIT64( 0x0010000000000000 ) )<<11 );
1850
1851}
1852
1853#endif
1854
1855/*
1856-------------------------------------------------------------------------------
1857Rounds the double-precision floating-point value `a' to an integer, and
1858returns the result as a double-precision floating-point value. The
1859operation is performed according to the IEC/IEEE Standard for Binary
1860Floating-point Arithmetic.
1861-------------------------------------------------------------------------------
1862*/
1863float64 float64_round_to_int( float64 a )
1864{
1865 flag aSign;
1866 int16 aExp;
1867 bits64 lastBitMask, roundBitsMask;
1868 int8 roundingMode;
1869 float64 z;
1870
1871 aExp = extractFloat64Exp( a );
1872 if ( 0x433 <= aExp ) {
1873 if ( ( aExp == 0x7FF ) && extractFloat64Frac( a ) ) {
1874 return propagateFloat64NaN( a, a );
1875 }
1876 return a;
1877 }
1878 if ( aExp <= 0x3FE ) {
1879 if ( (bits64) ( a<<1 ) == 0 ) return a;
1880 float_exception_flags |= float_flag_inexact;
1881 aSign = extractFloat64Sign( a );
1882 switch ( float_rounding_mode ) {
1883 case float_round_nearest_even:
1884 if ( ( aExp == 0x3FE ) && extractFloat64Frac( a ) ) {
1885 return packFloat64( aSign, 0x3FF, 0 );
1886 }
1887 break;
1888 case float_round_down:
1889 return aSign ? LIT64( 0xBFF0000000000000 ) : 0;
1890 case float_round_up:
1891 return
1892 aSign ? LIT64( 0x8000000000000000 ) : LIT64( 0x3FF0000000000000 );
1893 }
1894 return packFloat64( aSign, 0, 0 );
1895 }
1896 lastBitMask = 1;
1897 lastBitMask <<= 0x433 - aExp;
1898 roundBitsMask = lastBitMask - 1;
1899 z = a;
1900 roundingMode = float_rounding_mode;
1901 if ( roundingMode == float_round_nearest_even ) {
1902 z += lastBitMask>>1;
1903 if ( ( z & roundBitsMask ) == 0 ) z &= ~ lastBitMask;
1904 }
1905 else if ( roundingMode != float_round_to_zero ) {
1906 if ( extractFloat64Sign( z ) ^ ( roundingMode == float_round_up ) ) {
1907 z += roundBitsMask;
1908 }
1909 }
1910 z &= ~ roundBitsMask;
1911 if ( z != a ) float_exception_flags |= float_flag_inexact;
1912 return z;
1913
1914}
1915
1916/*
1917-------------------------------------------------------------------------------
1918Returns the result of adding the absolute values of the double-precision
1919floating-point values `a' and `b'. If `zSign' is true, the sum is negated
1920before being returned. `zSign' is ignored if the result is a NaN. The
1921addition is performed according to the IEC/IEEE Standard for Binary
1922Floating-point Arithmetic.
1923-------------------------------------------------------------------------------
1924*/
1925static float64 addFloat64Sigs( float64 a, float64 b, flag zSign )
1926{
1927 int16 aExp, bExp, zExp;
1928 bits64 aSig, bSig, zSig;
1929 int16 expDiff;
1930
1931 aSig = extractFloat64Frac( a );
1932 aExp = extractFloat64Exp( a );
1933 bSig = extractFloat64Frac( b );
1934 bExp = extractFloat64Exp( b );
1935 expDiff = aExp - bExp;
1936 aSig <<= 9;
1937 bSig <<= 9;
1938 if ( 0 < expDiff ) {
1939 if ( aExp == 0x7FF ) {
1940 if ( aSig ) return propagateFloat64NaN( a, b );
1941 return a;
1942 }
1943 if ( bExp == 0 ) {
1944 --expDiff;
1945 }
1946 else {
1947 bSig |= LIT64( 0x2000000000000000 );
1948 }
1949 shift64RightJamming( bSig, expDiff, &bSig );
1950 zExp = aExp;
1951 }
1952 else if ( expDiff < 0 ) {
1953 if ( bExp == 0x7FF ) {
1954 if ( bSig ) return propagateFloat64NaN( a, b );
1955 return packFloat64( zSign, 0x7FF, 0 );
1956 }
1957 if ( aExp == 0 ) {
1958 ++expDiff;
1959 }
1960 else {
1961 aSig |= LIT64( 0x2000000000000000 );
1962 }
1963 shift64RightJamming( aSig, - expDiff, &aSig );
1964 zExp = bExp;
1965 }
1966 else {
1967 if ( aExp == 0x7FF ) {
1968 if ( aSig | bSig ) return propagateFloat64NaN( a, b );
1969 return a;
1970 }
1971 if ( aExp == 0 ) return packFloat64( zSign, 0, ( aSig + bSig )>>9 );
1972 zSig = LIT64( 0x4000000000000000 ) + aSig + bSig;
1973 zExp = aExp;
1974 goto roundAndPack;
1975 }
1976 aSig |= LIT64( 0x2000000000000000 );
1977 zSig = ( aSig + bSig )<<1;
1978 --zExp;
1979 if ( (sbits64) zSig < 0 ) {
1980 zSig = aSig + bSig;
1981 ++zExp;
1982 }
1983 roundAndPack:
1984 return roundAndPackFloat64( zSign, zExp, zSig );
1985
1986}
1987
1988/*
1989-------------------------------------------------------------------------------
1990Returns the result of subtracting the absolute values of the double-
1991precision floating-point values `a' and `b'. If `zSign' is true, the
1992difference is negated before being returned. `zSign' is ignored if the
1993result is a NaN. The subtraction is performed according to the IEC/IEEE
1994Standard for Binary Floating-point Arithmetic.
1995-------------------------------------------------------------------------------
1996*/
1997static float64 subFloat64Sigs( float64 a, float64 b, flag zSign )
1998{
1999 int16 aExp, bExp, zExp;
2000 bits64 aSig, bSig, zSig;
2001 int16 expDiff;
2002
2003 aSig = extractFloat64Frac( a );
2004 aExp = extractFloat64Exp( a );
2005 bSig = extractFloat64Frac( b );
2006 bExp = extractFloat64Exp( b );
2007 expDiff = aExp - bExp;
2008 aSig <<= 10;
2009 bSig <<= 10;
2010 if ( 0 < expDiff ) goto aExpBigger;
2011 if ( expDiff < 0 ) goto bExpBigger;
2012 if ( aExp == 0x7FF ) {
2013 if ( aSig | bSig ) return propagateFloat64NaN( a, b );
2014 float_raise( float_flag_invalid );
2015 return float64_default_nan;
2016 }
2017 if ( aExp == 0 ) {
2018 aExp = 1;
2019 bExp = 1;
2020 }
2021 if ( bSig < aSig ) goto aBigger;
2022 if ( aSig < bSig ) goto bBigger;
2023 return packFloat64( float_rounding_mode == float_round_down, 0, 0 );
2024 bExpBigger:
2025 if ( bExp == 0x7FF ) {
2026 if ( bSig ) return propagateFloat64NaN( a, b );
2027 return packFloat64( zSign ^ 1, 0x7FF, 0 );
2028 }
2029 if ( aExp == 0 ) {
2030 ++expDiff;
2031 }
2032 else {
2033 aSig |= LIT64( 0x4000000000000000 );
2034 }
2035 shift64RightJamming( aSig, - expDiff, &aSig );
2036 bSig |= LIT64( 0x4000000000000000 );
2037 bBigger:
2038 zSig = bSig - aSig;
2039 zExp = bExp;
2040 zSign ^= 1;
2041 goto normalizeRoundAndPack;
2042 aExpBigger:
2043 if ( aExp == 0x7FF ) {
2044 if ( aSig ) return propagateFloat64NaN( a, b );
2045 return a;
2046 }
2047 if ( bExp == 0 ) {
2048 --expDiff;
2049 }
2050 else {
2051 bSig |= LIT64( 0x4000000000000000 );
2052 }
2053 shift64RightJamming( bSig, expDiff, &bSig );
2054 aSig |= LIT64( 0x4000000000000000 );
2055 aBigger:
2056 zSig = aSig - bSig;
2057 zExp = aExp;
2058 normalizeRoundAndPack:
2059 --zExp;
2060 return normalizeRoundAndPackFloat64( zSign, zExp, zSig );
2061
2062}
2063
2064/*
2065-------------------------------------------------------------------------------
2066Returns the result of adding the double-precision floating-point values `a'
2067and `b'. The operation is performed according to the IEC/IEEE Standard for
2068Binary Floating-point Arithmetic.
2069-------------------------------------------------------------------------------
2070*/
2071float64 float64_add( float64 a, float64 b )
2072{
2073 flag aSign, bSign;
2074
2075 aSign = extractFloat64Sign( a );
2076 bSign = extractFloat64Sign( b );
2077 if ( aSign == bSign ) {
2078 return addFloat64Sigs( a, b, aSign );
2079 }
2080 else {
2081 return subFloat64Sigs( a, b, aSign );
2082 }
2083
2084}
2085
2086/*
2087-------------------------------------------------------------------------------
2088Returns the result of subtracting the double-precision floating-point values
2089`a' and `b'. The operation is performed according to the IEC/IEEE Standard
2090for Binary Floating-point Arithmetic.
2091-------------------------------------------------------------------------------
2092*/
2093float64 float64_sub( float64 a, float64 b )
2094{
2095 flag aSign, bSign;
2096
2097 aSign = extractFloat64Sign( a );
2098 bSign = extractFloat64Sign( b );
2099 if ( aSign == bSign ) {
2100 return subFloat64Sigs( a, b, aSign );
2101 }
2102 else {
2103 return addFloat64Sigs( a, b, aSign );
2104 }
2105
2106}
2107
2108/*
2109-------------------------------------------------------------------------------
2110Returns the result of multiplying the double-precision floating-point values
2111`a' and `b'. The operation is performed according to the IEC/IEEE Standard
2112for Binary Floating-point Arithmetic.
2113-------------------------------------------------------------------------------
2114*/
2115float64 float64_mul( float64 a, float64 b )
2116{
2117 flag aSign, bSign, zSign;
2118 int16 aExp, bExp, zExp;
2119 bits64 aSig, bSig, zSig0, zSig1;
2120
2121 aSig = extractFloat64Frac( a );
2122 aExp = extractFloat64Exp( a );
2123 aSign = extractFloat64Sign( a );
2124 bSig = extractFloat64Frac( b );
2125 bExp = extractFloat64Exp( b );
2126 bSign = extractFloat64Sign( b );
2127 zSign = aSign ^ bSign;
2128 if ( aExp == 0x7FF ) {
2129 if ( aSig || ( ( bExp == 0x7FF ) && bSig ) ) {
2130 return propagateFloat64NaN( a, b );
2131 }
2132 if ( ( bExp | bSig ) == 0 ) {
2133 float_raise( float_flag_invalid );
2134 return float64_default_nan;
2135 }
2136 return packFloat64( zSign, 0x7FF, 0 );
2137 }
2138 if ( bExp == 0x7FF ) {
2139 if ( bSig ) return propagateFloat64NaN( a, b );
2140 if ( ( aExp | aSig ) == 0 ) {
2141 float_raise( float_flag_invalid );
2142 return float64_default_nan;
2143 }
2144 return packFloat64( zSign, 0x7FF, 0 );
2145 }
2146 if ( aExp == 0 ) {
2147 if ( aSig == 0 ) return packFloat64( zSign, 0, 0 );
2148 normalizeFloat64Subnormal( aSig, &aExp, &aSig );
2149 }
2150 if ( bExp == 0 ) {
2151 if ( bSig == 0 ) return packFloat64( zSign, 0, 0 );
2152 normalizeFloat64Subnormal( bSig, &bExp, &bSig );
2153 }
2154 zExp = aExp + bExp - 0x3FF;
2155 aSig = ( aSig | LIT64( 0x0010000000000000 ) )<<10;
2156 bSig = ( bSig | LIT64( 0x0010000000000000 ) )<<11;
2157 mul64To128( aSig, bSig, &zSig0, &zSig1 );
2158 zSig0 |= ( zSig1 != 0 );
2159 if ( 0 <= (sbits64) ( zSig0<<1 ) ) {
2160 zSig0 <<= 1;
2161 --zExp;
2162 }
2163 return roundAndPackFloat64( zSign, zExp, zSig0 );
2164
2165}
2166
2167/*
2168-------------------------------------------------------------------------------
2169Returns the result of dividing the double-precision floating-point value `a'
2170by the corresponding value `b'. The operation is performed according to
2171the IEC/IEEE Standard for Binary Floating-point Arithmetic.
2172-------------------------------------------------------------------------------
2173*/
2174float64 float64_div( float64 a, float64 b )
2175{
2176 flag aSign, bSign, zSign;
2177 int16 aExp, bExp, zExp;
2178 bits64 aSig, bSig, zSig;
2179 bits64 rem0, rem1;
2180 bits64 term0, term1;
2181
2182 aSig = extractFloat64Frac( a );
2183 aExp = extractFloat64Exp( a );
2184 aSign = extractFloat64Sign( a );
2185 bSig = extractFloat64Frac( b );
2186 bExp = extractFloat64Exp( b );
2187 bSign = extractFloat64Sign( b );
2188 zSign = aSign ^ bSign;
2189 if ( aExp == 0x7FF ) {
2190 if ( aSig ) return propagateFloat64NaN( a, b );
2191 if ( bExp == 0x7FF ) {
2192 if ( bSig ) return propagateFloat64NaN( a, b );
2193 float_raise( float_flag_invalid );
2194 return float64_default_nan;
2195 }
2196 return packFloat64( zSign, 0x7FF, 0 );
2197 }
2198 if ( bExp == 0x7FF ) {
2199 if ( bSig ) return propagateFloat64NaN( a, b );
2200 return packFloat64( zSign, 0, 0 );
2201 }
2202 if ( bExp == 0 ) {
2203 if ( bSig == 0 ) {
2204 if ( ( aExp | aSig ) == 0 ) {
2205 float_raise( float_flag_invalid );
2206 return float64_default_nan;
2207 }
2208 float_raise( float_flag_divbyzero );
2209 return packFloat64( zSign, 0x7FF, 0 );
2210 }
2211 normalizeFloat64Subnormal( bSig, &bExp, &bSig );
2212 }
2213 if ( aExp == 0 ) {
2214 if ( aSig == 0 ) return packFloat64( zSign, 0, 0 );
2215 normalizeFloat64Subnormal( aSig, &aExp, &aSig );
2216 }
2217 zExp = aExp - bExp + 0x3FD;
2218 aSig = ( aSig | LIT64( 0x0010000000000000 ) )<<10;
2219 bSig = ( bSig | LIT64( 0x0010000000000000 ) )<<11;
2220 if ( bSig <= ( aSig + aSig ) ) {
2221 aSig >>= 1;
2222 ++zExp;
2223 }
2224 zSig = estimateDiv128To64( aSig, 0, bSig );
2225 if ( ( zSig & 0x1FF ) <= 2 ) {
2226 mul64To128( bSig, zSig, &term0, &term1 );
2227 sub128( aSig, 0, term0, term1, &rem0, &rem1 );
2228 while ( (sbits64) rem0 < 0 ) {
2229 --zSig;
2230 add128( rem0, rem1, 0, bSig, &rem0, &rem1 );
2231 }
2232 zSig |= ( rem1 != 0 );
2233 }
2234 return roundAndPackFloat64( zSign, zExp, zSig );
2235
2236}
2237
2238/*
2239-------------------------------------------------------------------------------
2240Returns the remainder of the double-precision floating-point value `a'
2241with respect to the corresponding value `b'. The operation is performed
2242according to the IEC/IEEE Standard for Binary Floating-point Arithmetic.
2243-------------------------------------------------------------------------------
2244*/
2245float64 float64_rem( float64 a, float64 b )
2246{
2247 flag aSign, bSign, zSign;
2248 int16 aExp, bExp, expDiff;
2249 bits64 aSig, bSig;
2250 bits64 q, alternateASig;
2251 sbits64 sigMean;
2252
2253 aSig = extractFloat64Frac( a );
2254 aExp = extractFloat64Exp( a );
2255 aSign = extractFloat64Sign( a );
2256 bSig = extractFloat64Frac( b );
2257 bExp = extractFloat64Exp( b );
2258 bSign = extractFloat64Sign( b );
2259 if ( aExp == 0x7FF ) {
2260 if ( aSig || ( ( bExp == 0x7FF ) && bSig ) ) {
2261 return propagateFloat64NaN( a, b );
2262 }
2263 float_raise( float_flag_invalid );
2264 return float64_default_nan;
2265 }
2266 if ( bExp == 0x7FF ) {
2267 if ( bSig ) return propagateFloat64NaN( a, b );
2268 return a;
2269 }
2270 if ( bExp == 0 ) {
2271 if ( bSig == 0 ) {
2272 float_raise( float_flag_invalid );
2273 return float64_default_nan;
2274 }
2275 normalizeFloat64Subnormal( bSig, &bExp, &bSig );
2276 }
2277 if ( aExp == 0 ) {
2278 if ( aSig == 0 ) return a;
2279 normalizeFloat64Subnormal( aSig, &aExp, &aSig );
2280 }
2281 expDiff = aExp - bExp;
2282 aSig = ( aSig | LIT64( 0x0010000000000000 ) )<<11;
2283 bSig = ( bSig | LIT64( 0x0010000000000000 ) )<<11;
2284 if ( expDiff < 0 ) {
2285 if ( expDiff < -1 ) return a;
2286 aSig >>= 1;
2287 }
2288 q = ( bSig <= aSig );
2289 if ( q ) aSig -= bSig;
2290 expDiff -= 64;
2291 while ( 0 < expDiff ) {
2292 q = estimateDiv128To64( aSig, 0, bSig );
2293 q = ( 2 < q ) ? q - 2 : 0;
2294 aSig = - ( ( bSig>>2 ) * q );
2295 expDiff -= 62;
2296 }
2297 expDiff += 64;
2298 if ( 0 < expDiff ) {
2299 q = estimateDiv128To64( aSig, 0, bSig );
2300 q = ( 2 < q ) ? q - 2 : 0;
2301 q >>= 64 - expDiff;
2302 bSig >>= 2;
2303 aSig = ( ( aSig>>1 )<<( expDiff - 1 ) ) - bSig * q;
2304 }
2305 else {
2306 aSig >>= 2;
2307 bSig >>= 2;
2308 }
2309 do {
2310 alternateASig = aSig;
2311 ++q;
2312 aSig -= bSig;
2313 } while ( 0 <= (sbits64) aSig );
2314 sigMean = aSig + alternateASig;
2315 if ( ( sigMean < 0 ) || ( ( sigMean == 0 ) && ( q & 1 ) ) ) {
2316 aSig = alternateASig;
2317 }
2318 zSign = ( (sbits64) aSig < 0 );
2319 if ( zSign ) aSig = - aSig;
2320 return normalizeRoundAndPackFloat64( aSign ^ zSign, bExp, aSig );
2321
2322}
2323
2324/*
2325-------------------------------------------------------------------------------
2326Returns the square root of the double-precision floating-point value `a'.
2327The operation is performed according to the IEC/IEEE Standard for Binary
2328Floating-point Arithmetic.
2329-------------------------------------------------------------------------------
2330*/
2331float64 float64_sqrt( float64 a )
2332{
2333 flag aSign;
2334 int16 aExp, zExp;
2335 bits64 aSig, zSig;
2336 bits64 rem0, rem1, term0, term1; //, shiftedRem;
2337 //float64 z;
2338
2339 aSig = extractFloat64Frac( a );
2340 aExp = extractFloat64Exp( a );
2341 aSign = extractFloat64Sign( a );
2342 if ( aExp == 0x7FF ) {
2343 if ( aSig ) return propagateFloat64NaN( a, a );
2344 if ( ! aSign ) return a;
2345 float_raise( float_flag_invalid );
2346 return float64_default_nan;
2347 }
2348 if ( aSign ) {
2349 if ( ( aExp | aSig ) == 0 ) return a;
2350 float_raise( float_flag_invalid );
2351 return float64_default_nan;
2352 }
2353 if ( aExp == 0 ) {
2354 if ( aSig == 0 ) return 0;
2355 normalizeFloat64Subnormal( aSig, &aExp, &aSig );
2356 }
2357 zExp = ( ( aExp - 0x3FF )>>1 ) + 0x3FE;
2358 aSig |= LIT64( 0x0010000000000000 );
2359 zSig = estimateSqrt32( aExp, aSig>>21 );
2360 zSig <<= 31;
2361 aSig <<= 9 - ( aExp & 1 );
2362 zSig = estimateDiv128To64( aSig, 0, zSig ) + zSig + 2;
2363 if ( ( zSig & 0x3FF ) <= 5 ) {
2364 if ( zSig < 2 ) {
2365 zSig = LIT64( 0xFFFFFFFFFFFFFFFF );
2366 }
2367 else {
2368 aSig <<= 2;
2369 mul64To128( zSig, zSig, &term0, &term1 );
2370 sub128( aSig, 0, term0, term1, &rem0, &rem1 );
2371 while ( (sbits64) rem0 < 0 ) {
2372 --zSig;
2373 shortShift128Left( 0, zSig, 1, &term0, &term1 );
2374 term1 |= 1;
2375 add128( rem0, rem1, term0, term1, &rem0, &rem1 );
2376 }
2377 zSig |= ( ( rem0 | rem1 ) != 0 );
2378 }
2379 }
2380 shift64RightJamming( zSig, 1, &zSig );
2381 return roundAndPackFloat64( 0, zExp, zSig );
2382
2383}
2384
2385/*
2386-------------------------------------------------------------------------------
2387Returns 1 if the double-precision floating-point value `a' is equal to the
2388corresponding value `b', and 0 otherwise. The comparison is performed
2389according to the IEC/IEEE Standard for Binary Floating-point Arithmetic.
2390-------------------------------------------------------------------------------
2391*/
2392flag float64_eq( float64 a, float64 b )
2393{
2394
2395 if ( ( ( extractFloat64Exp( a ) == 0x7FF ) && extractFloat64Frac( a ) )
2396 || ( ( extractFloat64Exp( b ) == 0x7FF ) && extractFloat64Frac( b ) )
2397 ) {
2398 if ( float64_is_signaling_nan( a ) || float64_is_signaling_nan( b ) ) {
2399 float_raise( float_flag_invalid );
2400 }
2401 return 0;
2402 }
2403 return ( a == b ) || ( (bits64) ( ( a | b )<<1 ) == 0 );
2404
2405}
2406
2407/*
2408-------------------------------------------------------------------------------
2409Returns 1 if the double-precision floating-point value `a' is less than or
2410equal to the corresponding value `b', and 0 otherwise. The comparison is
2411performed according to the IEC/IEEE Standard for Binary Floating-point
2412Arithmetic.
2413-------------------------------------------------------------------------------
2414*/
2415flag float64_le( float64 a, float64 b )
2416{
2417 flag aSign, bSign;
2418
2419 if ( ( ( extractFloat64Exp( a ) == 0x7FF ) && extractFloat64Frac( a ) )
2420 || ( ( extractFloat64Exp( b ) == 0x7FF ) && extractFloat64Frac( b ) )
2421 ) {
2422 float_raise( float_flag_invalid );
2423 return 0;
2424 }
2425 aSign = extractFloat64Sign( a );
2426 bSign = extractFloat64Sign( b );
2427 if ( aSign != bSign ) return aSign || ( (bits64) ( ( a | b )<<1 ) == 0 );
2428 return ( a == b ) || ( aSign ^ ( a < b ) );
2429
2430}
2431
2432/*
2433-------------------------------------------------------------------------------
2434Returns 1 if the double-precision floating-point value `a' is less than
2435the corresponding value `b', and 0 otherwise. The comparison is performed
2436according to the IEC/IEEE Standard for Binary Floating-point Arithmetic.
2437-------------------------------------------------------------------------------
2438*/
2439flag float64_lt( float64 a, float64 b )
2440{
2441 flag aSign, bSign;
2442
2443 if ( ( ( extractFloat64Exp( a ) == 0x7FF ) && extractFloat64Frac( a ) )
2444 || ( ( extractFloat64Exp( b ) == 0x7FF ) && extractFloat64Frac( b ) )
2445 ) {
2446 float_raise( float_flag_invalid );
2447 return 0;
2448 }
2449 aSign = extractFloat64Sign( a );
2450 bSign = extractFloat64Sign( b );
2451 if ( aSign != bSign ) return aSign && ( (bits64) ( ( a | b )<<1 ) != 0 );
2452 return ( a != b ) && ( aSign ^ ( a < b ) );
2453
2454}
2455
2456/*
2457-------------------------------------------------------------------------------
2458Returns 1 if the double-precision floating-point value `a' is equal to the
2459corresponding value `b', and 0 otherwise. The invalid exception is raised
2460if either operand is a NaN. Otherwise, the comparison is performed
2461according to the IEC/IEEE Standard for Binary Floating-point Arithmetic.
2462-------------------------------------------------------------------------------
2463*/
2464flag float64_eq_signaling( float64 a, float64 b )
2465{
2466
2467 if ( ( ( extractFloat64Exp( a ) == 0x7FF ) && extractFloat64Frac( a ) )
2468 || ( ( extractFloat64Exp( b ) == 0x7FF ) && extractFloat64Frac( b ) )
2469 ) {
2470 float_raise( float_flag_invalid );
2471 return 0;
2472 }
2473 return ( a == b ) || ( (bits64) ( ( a | b )<<1 ) == 0 );
2474
2475}
2476
2477/*
2478-------------------------------------------------------------------------------
2479Returns 1 if the double-precision floating-point value `a' is less than or
2480equal to the corresponding value `b', and 0 otherwise. Quiet NaNs do not
2481cause an exception. Otherwise, the comparison is performed according to the
2482IEC/IEEE Standard for Binary Floating-point Arithmetic.
2483-------------------------------------------------------------------------------
2484*/
2485flag float64_le_quiet( float64 a, float64 b )
2486{
2487 flag aSign, bSign;
2488 //int16 aExp, bExp;
2489
2490 if ( ( ( extractFloat64Exp( a ) == 0x7FF ) && extractFloat64Frac( a ) )
2491 || ( ( extractFloat64Exp( b ) == 0x7FF ) && extractFloat64Frac( b ) )
2492 ) {
2493 if ( float64_is_signaling_nan( a ) || float64_is_signaling_nan( b ) ) {
2494 float_raise( float_flag_invalid );
2495 }
2496 return 0;
2497 }
2498 aSign = extractFloat64Sign( a );
2499 bSign = extractFloat64Sign( b );
2500 if ( aSign != bSign ) return aSign || ( (bits64) ( ( a | b )<<1 ) == 0 );
2501 return ( a == b ) || ( aSign ^ ( a < b ) );
2502
2503}
2504
2505/*
2506-------------------------------------------------------------------------------
2507Returns 1 if the double-precision floating-point value `a' is less than
2508the corresponding value `b', and 0 otherwise. Quiet NaNs do not cause an
2509exception. Otherwise, the comparison is performed according to the IEC/IEEE
2510Standard for Binary Floating-point Arithmetic.
2511-------------------------------------------------------------------------------
2512*/
2513flag float64_lt_quiet( float64 a, float64 b )
2514{
2515 flag aSign, bSign;
2516
2517 if ( ( ( extractFloat64Exp( a ) == 0x7FF ) && extractFloat64Frac( a ) )
2518 || ( ( extractFloat64Exp( b ) == 0x7FF ) && extractFloat64Frac( b ) )
2519 ) {
2520 if ( float64_is_signaling_nan( a ) || float64_is_signaling_nan( b ) ) {
2521 float_raise( float_flag_invalid );
2522 }
2523 return 0;
2524 }
2525 aSign = extractFloat64Sign( a );
2526 bSign = extractFloat64Sign( b );
2527 if ( aSign != bSign ) return aSign && ( (bits64) ( ( a | b )<<1 ) != 0 );
2528 return ( a != b ) && ( aSign ^ ( a < b ) );
2529
2530}
2531
2532#ifdef FLOATX80
2533
2534/*
2535-------------------------------------------------------------------------------
2536Returns the result of converting the extended double-precision floating-
2537point value `a' to the 32-bit two's complement integer format. The
2538conversion is performed according to the IEC/IEEE Standard for Binary
2539Floating-point Arithmetic---which means in particular that the conversion
2540is rounded according to the current rounding mode. If `a' is a NaN, the
2541largest positive integer is returned. Otherwise, if the conversion
2542overflows, the largest integer with the same sign as `a' is returned.
2543-------------------------------------------------------------------------------
2544*/
2545int32 floatx80_to_int32( floatx80 a )
2546{
2547 flag aSign;
2548 int32 aExp, shiftCount;
2549 bits64 aSig;
2550
2551 aSig = extractFloatx80Frac( a );
2552 aExp = extractFloatx80Exp( a );
2553 aSign = extractFloatx80Sign( a );
2554 if ( ( aExp == 0x7FFF ) && (bits64) ( aSig<<1 ) ) aSign = 0;
2555 shiftCount = 0x4037 - aExp;
2556 if ( shiftCount <= 0 ) shiftCount = 1;
2557 shift64RightJamming( aSig, shiftCount, &aSig );
2558 return roundAndPackInt32( aSign, aSig );
2559
2560}
2561
2562/*
2563-------------------------------------------------------------------------------
2564Returns the result of converting the extended double-precision floating-
2565point value `a' to the 32-bit two's complement integer format. The
2566conversion is performed according to the IEC/IEEE Standard for Binary
2567Floating-point Arithmetic, except that the conversion is always rounded
2568toward zero. If `a' is a NaN, the largest positive integer is returned.
2569Otherwise, if the conversion overflows, the largest integer with the same
2570sign as `a' is returned.
2571-------------------------------------------------------------------------------
2572*/
2573int32 floatx80_to_int32_round_to_zero( floatx80 a )
2574{
2575 flag aSign;
2576 int32 aExp, shiftCount;
2577 bits64 aSig, savedASig;
2578 int32 z;
2579
2580 aSig = extractFloatx80Frac( a );
2581 aExp = extractFloatx80Exp( a );
2582 aSign = extractFloatx80Sign( a );
2583 shiftCount = 0x403E - aExp;
2584 if ( shiftCount < 32 ) {
2585 if ( ( aExp == 0x7FFF ) && (bits64) ( aSig<<1 ) ) aSign = 0;
2586 goto invalid;
2587 }
2588 else if ( 63 < shiftCount ) {
2589 if ( aExp || aSig ) float_exception_flags |= float_flag_inexact;
2590 return 0;
2591 }
2592 savedASig = aSig;
2593 aSig >>= shiftCount;
2594 z = aSig;
2595 if ( aSign ) z = - z;
2596 if ( ( z < 0 ) ^ aSign ) {
2597 invalid:
2598 float_exception_flags |= float_flag_invalid;
2599 return aSign ? 0x80000000 : 0x7FFFFFFF;
2600 }
2601 if ( ( aSig<<shiftCount ) != savedASig ) {
2602 float_exception_flags |= float_flag_inexact;
2603 }
2604 return z;
2605
2606}
2607
2608/*
2609-------------------------------------------------------------------------------
2610Returns the result of converting the extended double-precision floating-
2611point value `a' to the single-precision floating-point format. The
2612conversion is performed according to the IEC/IEEE Standard for Binary
2613Floating-point Arithmetic.
2614-------------------------------------------------------------------------------
2615*/
2616float32 floatx80_to_float32( floatx80 a )
2617{
2618 flag aSign;
2619 int32 aExp;
2620 bits64 aSig;
2621
2622 aSig = extractFloatx80Frac( a );
2623 aExp = extractFloatx80Exp( a );
2624 aSign = extractFloatx80Sign( a );
2625 if ( aExp == 0x7FFF ) {
2626 if ( (bits64) ( aSig<<1 ) ) {
2627 return commonNaNToFloat32( floatx80ToCommonNaN( a ) );
2628 }
2629 return packFloat32( aSign, 0xFF, 0 );
2630 }
2631 shift64RightJamming( aSig, 33, &aSig );
2632 if ( aExp || aSig ) aExp -= 0x3F81;
2633 return roundAndPackFloat32( aSign, aExp, aSig );
2634
2635}
2636
2637/*
2638-------------------------------------------------------------------------------
2639Returns the result of converting the extended double-precision floating-
2640point value `a' to the double-precision floating-point format. The
2641conversion is performed according to the IEC/IEEE Standard for Binary
2642Floating-point Arithmetic.
2643-------------------------------------------------------------------------------
2644*/
2645float64 floatx80_to_float64( floatx80 a )
2646{
2647 flag aSign;
2648 int32 aExp;
2649 bits64 aSig, zSig;
2650
2651 aSig = extractFloatx80Frac( a );
2652 aExp = extractFloatx80Exp( a );
2653 aSign = extractFloatx80Sign( a );
2654 if ( aExp == 0x7FFF ) {
2655 if ( (bits64) ( aSig<<1 ) ) {
2656 return commonNaNToFloat64( floatx80ToCommonNaN( a ) );
2657 }
2658 return packFloat64( aSign, 0x7FF, 0 );
2659 }
2660 shift64RightJamming( aSig, 1, &zSig );
2661 if ( aExp || aSig ) aExp -= 0x3C01;
2662 return roundAndPackFloat64( aSign, aExp, zSig );
2663
2664}
2665
2666/*
2667-------------------------------------------------------------------------------
2668Rounds the extended double-precision floating-point value `a' to an integer,
2669and returns the result as an extended quadruple-precision floating-point
2670value. The operation is performed according to the IEC/IEEE Standard for
2671Binary Floating-point Arithmetic.
2672-------------------------------------------------------------------------------
2673*/
2674floatx80 floatx80_round_to_int( floatx80 a )
2675{
2676 flag aSign;
2677 int32 aExp;
2678 bits64 lastBitMask, roundBitsMask;
2679 int8 roundingMode;
2680 floatx80 z;
2681
2682 aExp = extractFloatx80Exp( a );
2683 if ( 0x403E <= aExp ) {
2684 if ( ( aExp == 0x7FFF ) && (bits64) ( extractFloatx80Frac( a )<<1 ) ) {
2685 return propagateFloatx80NaN( a, a );
2686 }
2687 return a;
2688 }
2689 if ( aExp <= 0x3FFE ) {
2690 if ( ( aExp == 0 )
2691 && ( (bits64) ( extractFloatx80Frac( a )<<1 ) == 0 ) ) {
2692 return a;
2693 }
2694 float_exception_flags |= float_flag_inexact;
2695 aSign = extractFloatx80Sign( a );
2696 switch ( float_rounding_mode ) {
2697 case float_round_nearest_even:
2698 if ( ( aExp == 0x3FFE ) && (bits64) ( extractFloatx80Frac( a )<<1 )
2699 ) {
2700 return
2701 packFloatx80( aSign, 0x3FFF, LIT64( 0x8000000000000000 ) );
2702 }
2703 break;
2704 case float_round_down:
2705 return
2706 aSign ?
2707 packFloatx80( 1, 0x3FFF, LIT64( 0x8000000000000000 ) )
2708 : packFloatx80( 0, 0, 0 );
2709 case float_round_up:
2710 return
2711 aSign ? packFloatx80( 1, 0, 0 )
2712 : packFloatx80( 0, 0x3FFF, LIT64( 0x8000000000000000 ) );
2713 }
2714 return packFloatx80( aSign, 0, 0 );
2715 }
2716 lastBitMask = 1;
2717 lastBitMask <<= 0x403E - aExp;
2718 roundBitsMask = lastBitMask - 1;
2719 z = a;
2720 roundingMode = float_rounding_mode;
2721 if ( roundingMode == float_round_nearest_even ) {
2722 z.low += lastBitMask>>1;
2723 if ( ( z.low & roundBitsMask ) == 0 ) z.low &= ~ lastBitMask;
2724 }
2725 else if ( roundingMode != float_round_to_zero ) {
2726 if ( extractFloatx80Sign( z ) ^ ( roundingMode == float_round_up ) ) {
2727 z.low += roundBitsMask;
2728 }
2729 }
2730 z.low &= ~ roundBitsMask;
2731 if ( z.low == 0 ) {
2732 ++z.high;
2733 z.low = LIT64( 0x8000000000000000 );
2734 }
2735 if ( z.low != a.low ) float_exception_flags |= float_flag_inexact;
2736 return z;
2737
2738}
2739
2740/*
2741-------------------------------------------------------------------------------
2742Returns the result of adding the absolute values of the extended double-
2743precision floating-point values `a' and `b'. If `zSign' is true, the sum is
2744negated before being returned. `zSign' is ignored if the result is a NaN.
2745The addition is performed according to the IEC/IEEE Standard for Binary
2746Floating-point Arithmetic.
2747-------------------------------------------------------------------------------
2748*/
2749static floatx80 addFloatx80Sigs( floatx80 a, floatx80 b, flag zSign )
2750{
2751 int32 aExp, bExp, zExp;
2752 bits64 aSig, bSig, zSig0, zSig1;
2753 int32 expDiff;
2754
2755 aSig = extractFloatx80Frac( a );
2756 aExp = extractFloatx80Exp( a );
2757 bSig = extractFloatx80Frac( b );
2758 bExp = extractFloatx80Exp( b );
2759 expDiff = aExp - bExp;
2760 if ( 0 < expDiff ) {
2761 if ( aExp == 0x7FFF ) {
2762 if ( (bits64) ( aSig<<1 ) ) return propagateFloatx80NaN( a, b );
2763 return a;
2764 }
2765 if ( bExp == 0 ) --expDiff;
2766 shift64ExtraRightJamming( bSig, 0, expDiff, &bSig, &zSig1 );
2767 zExp = aExp;
2768 }
2769 else if ( expDiff < 0 ) {
2770 if ( bExp == 0x7FFF ) {
2771 if ( (bits64) ( bSig<<1 ) ) return propagateFloatx80NaN( a, b );
2772 return packFloatx80( zSign, 0x7FFF, LIT64( 0x8000000000000000 ) );
2773 }
2774 if ( aExp == 0 ) ++expDiff;
2775 shift64ExtraRightJamming( aSig, 0, - expDiff, &aSig, &zSig1 );
2776 zExp = bExp;
2777 }
2778 else {
2779 if ( aExp == 0x7FFF ) {
2780 if ( (bits64) ( ( aSig | bSig )<<1 ) ) {
2781 return propagateFloatx80NaN( a, b );
2782 }
2783 return a;
2784 }
2785 zSig1 = 0;
2786 zSig0 = aSig + bSig;
2787 if ( aExp == 0 ) {
2788 normalizeFloatx80Subnormal( zSig0, &zExp, &zSig0 );
2789 goto roundAndPack;
2790 }
2791 zExp = aExp;
2792 goto shiftRight1;
2793 }
2794
2795 zSig0 = aSig + bSig;
2796
2797 if ( (sbits64) zSig0 < 0 ) goto roundAndPack;
2798 shiftRight1:
2799 shift64ExtraRightJamming( zSig0, zSig1, 1, &zSig0, &zSig1 );
2800 zSig0 |= LIT64( 0x8000000000000000 );
2801 ++zExp;
2802 roundAndPack:
2803 return
2804 roundAndPackFloatx80(
2805 floatx80_rounding_precision, zSign, zExp, zSig0, zSig1 );
2806
2807}
2808
2809/*
2810-------------------------------------------------------------------------------
2811Returns the result of subtracting the absolute values of the extended
2812double-precision floating-point values `a' and `b'. If `zSign' is true,
2813the difference is negated before being returned. `zSign' is ignored if the
2814result is a NaN. The subtraction is performed according to the IEC/IEEE
2815Standard for Binary Floating-point Arithmetic.
2816-------------------------------------------------------------------------------
2817*/
2818static floatx80 subFloatx80Sigs( floatx80 a, floatx80 b, flag zSign )
2819{
2820 int32 aExp, bExp, zExp;
2821 bits64 aSig, bSig, zSig0, zSig1;
2822 int32 expDiff;
2823 floatx80 z;
2824
2825 aSig = extractFloatx80Frac( a );
2826 aExp = extractFloatx80Exp( a );
2827 bSig = extractFloatx80Frac( b );
2828 bExp = extractFloatx80Exp( b );
2829 expDiff = aExp - bExp;
2830 if ( 0 < expDiff ) goto aExpBigger;
2831 if ( expDiff < 0 ) goto bExpBigger;
2832 if ( aExp == 0x7FFF ) {
2833 if ( (bits64) ( ( aSig | bSig )<<1 ) ) {
2834 return propagateFloatx80NaN( a, b );
2835 }
2836 float_raise( float_flag_invalid );
2837 z.low = floatx80_default_nan_low;
2838 z.high = floatx80_default_nan_high;
2839 return z;
2840 }
2841 if ( aExp == 0 ) {
2842 aExp = 1;
2843 bExp = 1;
2844 }
2845 zSig1 = 0;
2846 if ( bSig < aSig ) goto aBigger;
2847 if ( aSig < bSig ) goto bBigger;
2848 return packFloatx80( float_rounding_mode == float_round_down, 0, 0 );
2849 bExpBigger:
2850 if ( bExp == 0x7FFF ) {
2851 if ( (bits64) ( bSig<<1 ) ) return propagateFloatx80NaN( a, b );
2852 return packFloatx80( zSign ^ 1, 0x7FFF, LIT64( 0x8000000000000000 ) );
2853 }
2854 if ( aExp == 0 ) ++expDiff;
2855 shift128RightJamming( aSig, 0, - expDiff, &aSig, &zSig1 );
2856 bBigger:
2857 sub128( bSig, 0, aSig, zSig1, &zSig0, &zSig1 );
2858 zExp = bExp;
2859 zSign ^= 1;
2860 goto normalizeRoundAndPack;
2861 aExpBigger:
2862 if ( aExp == 0x7FFF ) {
2863 if ( (bits64) ( aSig<<1 ) ) return propagateFloatx80NaN( a, b );
2864 return a;
2865 }
2866 if ( bExp == 0 ) --expDiff;
2867 shift128RightJamming( bSig, 0, expDiff, &bSig, &zSig1 );
2868 aBigger:
2869 sub128( aSig, 0, bSig, zSig1, &zSig0, &zSig1 );
2870 zExp = aExp;
2871 normalizeRoundAndPack:
2872 return
2873 normalizeRoundAndPackFloatx80(
2874 floatx80_rounding_precision, zSign, zExp, zSig0, zSig1 );
2875
2876}
2877
2878/*
2879-------------------------------------------------------------------------------
2880Returns the result of adding the extended double-precision floating-point
2881values `a' and `b'. The operation is performed according to the IEC/IEEE
2882Standard for Binary Floating-point Arithmetic.
2883-------------------------------------------------------------------------------
2884*/
2885floatx80 floatx80_add( floatx80 a, floatx80 b )
2886{
2887 flag aSign, bSign;
2888
2889 aSign = extractFloatx80Sign( a );
2890 bSign = extractFloatx80Sign( b );
2891 if ( aSign == bSign ) {
2892 return addFloatx80Sigs( a, b, aSign );
2893 }
2894 else {
2895 return subFloatx80Sigs( a, b, aSign );
2896 }
2897
2898}
2899
2900/*
2901-------------------------------------------------------------------------------
2902Returns the result of subtracting the extended double-precision floating-
2903point values `a' and `b'. The operation is performed according to the
2904IEC/IEEE Standard for Binary Floating-point Arithmetic.
2905-------------------------------------------------------------------------------
2906*/
2907floatx80 floatx80_sub( floatx80 a, floatx80 b )
2908{
2909 flag aSign, bSign;
2910
2911 aSign = extractFloatx80Sign( a );
2912 bSign = extractFloatx80Sign( b );
2913 if ( aSign == bSign ) {
2914 return subFloatx80Sigs( a, b, aSign );
2915 }
2916 else {
2917 return addFloatx80Sigs( a, b, aSign );
2918 }
2919
2920}
2921
2922/*
2923-------------------------------------------------------------------------------
2924Returns the result of multiplying the extended double-precision floating-
2925point values `a' and `b'. The operation is performed according to the
2926IEC/IEEE Standard for Binary Floating-point Arithmetic.
2927-------------------------------------------------------------------------------
2928*/
2929floatx80 floatx80_mul( floatx80 a, floatx80 b )
2930{
2931 flag aSign, bSign, zSign;
2932 int32 aExp, bExp, zExp;
2933 bits64 aSig, bSig, zSig0, zSig1;
2934 floatx80 z;
2935
2936 aSig = extractFloatx80Frac( a );
2937 aExp = extractFloatx80Exp( a );
2938 aSign = extractFloatx80Sign( a );
2939 bSig = extractFloatx80Frac( b );
2940 bExp = extractFloatx80Exp( b );
2941 bSign = extractFloatx80Sign( b );
2942 zSign = aSign ^ bSign;
2943 if ( aExp == 0x7FFF ) {
2944 if ( (bits64) ( aSig<<1 )
2945 || ( ( bExp == 0x7FFF ) && (bits64) ( bSig<<1 ) ) ) {
2946 return propagateFloatx80NaN( a, b );
2947 }
2948 if ( ( bExp | bSig ) == 0 ) goto invalid;
2949 return packFloatx80( zSign, 0x7FFF, LIT64( 0x8000000000000000 ) );
2950 }
2951 if ( bExp == 0x7FFF ) {
2952 if ( (bits64) ( bSig<<1 ) ) return propagateFloatx80NaN( a, b );
2953 if ( ( aExp | aSig ) == 0 ) {
2954 invalid:
2955 float_raise( float_flag_invalid );
2956 z.low = floatx80_default_nan_low;
2957 z.high = floatx80_default_nan_high;
2958 return z;
2959 }
2960 return packFloatx80( zSign, 0x7FFF, LIT64( 0x8000000000000000 ) );
2961 }
2962 if ( aExp == 0 ) {
2963 if ( aSig == 0 ) return packFloatx80( zSign, 0, 0 );
2964 normalizeFloatx80Subnormal( aSig, &aExp, &aSig );
2965 }
2966 if ( bExp == 0 ) {
2967 if ( bSig == 0 ) return packFloatx80( zSign, 0, 0 );
2968 normalizeFloatx80Subnormal( bSig, &bExp, &bSig );
2969 }
2970 zExp = aExp + bExp - 0x3FFE;
2971 mul64To128( aSig, bSig, &zSig0, &zSig1 );
2972 if ( 0 < (sbits64) zSig0 ) {
2973 shortShift128Left( zSig0, zSig1, 1, &zSig0, &zSig1 );
2974 --zExp;
2975 }
2976 return
2977 roundAndPackFloatx80(
2978 floatx80_rounding_precision, zSign, zExp, zSig0, zSig1 );
2979
2980}
2981
2982/*
2983-------------------------------------------------------------------------------
2984Returns the result of dividing the extended double-precision floating-point
2985value `a' by the corresponding value `b'. The operation is performed
2986according to the IEC/IEEE Standard for Binary Floating-point Arithmetic.
2987-------------------------------------------------------------------------------
2988*/
2989floatx80 floatx80_div( floatx80 a, floatx80 b )
2990{
2991 flag aSign, bSign, zSign;
2992 int32 aExp, bExp, zExp;
2993 bits64 aSig, bSig, zSig0, zSig1;
2994 bits64 rem0, rem1, rem2, term0, term1, term2;
2995 floatx80 z;
2996
2997 aSig = extractFloatx80Frac( a );
2998 aExp = extractFloatx80Exp( a );
2999 aSign = extractFloatx80Sign( a );
3000 bSig = extractFloatx80Frac( b );
3001 bExp = extractFloatx80Exp( b );
3002 bSign = extractFloatx80Sign( b );
3003 zSign = aSign ^ bSign;
3004 if ( aExp == 0x7FFF ) {
3005 if ( (bits64) ( aSig<<1 ) ) return propagateFloatx80NaN( a, b );
3006 if ( bExp == 0x7FFF ) {
3007 if ( (bits64) ( bSig<<1 ) ) return propagateFloatx80NaN( a, b );
3008 goto invalid;
3009 }
3010 return packFloatx80( zSign, 0x7FFF, LIT64( 0x8000000000000000 ) );
3011 }
3012 if ( bExp == 0x7FFF ) {
3013 if ( (bits64) ( bSig<<1 ) ) return propagateFloatx80NaN( a, b );
3014 return packFloatx80( zSign, 0, 0 );
3015 }
3016 if ( bExp == 0 ) {
3017 if ( bSig == 0 ) {
3018 if ( ( aExp | aSig ) == 0 ) {
3019 invalid:
3020 float_raise( float_flag_invalid );
3021 z.low = floatx80_default_nan_low;
3022 z.high = floatx80_default_nan_high;
3023 return z;
3024 }
3025 float_raise( float_flag_divbyzero );
3026 return packFloatx80( zSign, 0x7FFF, LIT64( 0x8000000000000000 ) );
3027 }
3028 normalizeFloatx80Subnormal( bSig, &bExp, &bSig );
3029 }
3030 if ( aExp == 0 ) {
3031 if ( aSig == 0 ) return packFloatx80( zSign, 0, 0 );
3032 normalizeFloatx80Subnormal( aSig, &aExp, &aSig );
3033 }
3034 zExp = aExp - bExp + 0x3FFE;
3035 rem1 = 0;
3036 if ( bSig <= aSig ) {
3037 shift128Right( aSig, 0, 1, &aSig, &rem1 );
3038 ++zExp;
3039 }
3040 zSig0 = estimateDiv128To64( aSig, rem1, bSig );
3041 mul64To128( bSig, zSig0, &term0, &term1 );
3042 sub128( aSig, rem1, term0, term1, &rem0, &rem1 );
3043 while ( (sbits64) rem0 < 0 ) {
3044 --zSig0;
3045 add128( rem0, rem1, 0, bSig, &rem0, &rem1 );
3046 }
3047 zSig1 = estimateDiv128To64( rem1, 0, bSig );
3048 if ( (bits64) ( zSig1<<1 ) <= 8 ) {
3049 mul64To128( bSig, zSig1, &term1, &term2 );
3050 sub128( rem1, 0, term1, term2, &rem1, &rem2 );
3051 while ( (sbits64) rem1 < 0 ) {
3052 --zSig1;
3053 add128( rem1, rem2, 0, bSig, &rem1, &rem2 );
3054 }
3055 zSig1 |= ( ( rem1 | rem2 ) != 0 );
3056 }
3057 return
3058 roundAndPackFloatx80(
3059 floatx80_rounding_precision, zSign, zExp, zSig0, zSig1 );
3060
3061}
3062
3063/*
3064-------------------------------------------------------------------------------
3065Returns the remainder of the extended double-precision floating-point value
3066`a' with respect to the corresponding value `b'. The operation is performed
3067according to the IEC/IEEE Standard for Binary Floating-point Arithmetic.
3068-------------------------------------------------------------------------------
3069*/
3070floatx80 floatx80_rem( floatx80 a, floatx80 b )
3071{
3072 flag aSign, bSign, zSign;
3073 int32 aExp, bExp, expDiff;
3074 bits64 aSig0, aSig1, bSig;
3075 bits64 q, term0, term1, alternateASig0, alternateASig1;
3076 floatx80 z;
3077
3078 aSig0 = extractFloatx80Frac( a );
3079 aExp = extractFloatx80Exp( a );
3080 aSign = extractFloatx80Sign( a );
3081 bSig = extractFloatx80Frac( b );
3082 bExp = extractFloatx80Exp( b );
3083 bSign = extractFloatx80Sign( b );
3084 if ( aExp == 0x7FFF ) {
3085 if ( (bits64) ( aSig0<<1 )
3086 || ( ( bExp == 0x7FFF ) && (bits64) ( bSig<<1 ) ) ) {
3087 return propagateFloatx80NaN( a, b );
3088 }
3089 goto invalid;
3090 }
3091 if ( bExp == 0x7FFF ) {
3092 if ( (bits64) ( bSig<<1 ) ) return propagateFloatx80NaN( a, b );
3093 return a;
3094 }
3095 if ( bExp == 0 ) {
3096 if ( bSig == 0 ) {
3097 invalid:
3098 float_raise( float_flag_invalid );
3099 z.low = floatx80_default_nan_low;
3100 z.high = floatx80_default_nan_high;
3101 return z;
3102 }
3103 normalizeFloatx80Subnormal( bSig, &bExp, &bSig );
3104 }
3105 if ( aExp == 0 ) {
3106 if ( (bits64) ( aSig0<<1 ) == 0 ) return a;
3107 normalizeFloatx80Subnormal( aSig0, &aExp, &aSig0 );
3108 }
3109 bSig |= LIT64( 0x8000000000000000 );
3110 zSign = aSign;
3111 expDiff = aExp - bExp;
3112 aSig1 = 0;
3113 if ( expDiff < 0 ) {
3114 if ( expDiff < -1 ) return a;
3115 shift128Right( aSig0, 0, 1, &aSig0, &aSig1 );
3116 expDiff = 0;
3117 }
3118 q = ( bSig <= aSig0 );
3119 if ( q ) aSig0 -= bSig;
3120 expDiff -= 64;
3121 while ( 0 < expDiff ) {
3122 q = estimateDiv128To64( aSig0, aSig1, bSig );
3123 q = ( 2 < q ) ? q - 2 : 0;
3124 mul64To128( bSig, q, &term0, &term1 );
3125 sub128( aSig0, aSig1, term0, term1, &aSig0, &aSig1 );
3126 shortShift128Left( aSig0, aSig1, 62, &aSig0, &aSig1 );
3127 expDiff -= 62;
3128 }
3129 expDiff += 64;
3130 if ( 0 < expDiff ) {
3131 q = estimateDiv128To64( aSig0, aSig1, bSig );
3132 q = ( 2 < q ) ? q - 2 : 0;
3133 q >>= 64 - expDiff;
3134 mul64To128( bSig, q<<( 64 - expDiff ), &term0, &term1 );
3135 sub128( aSig0, aSig1, term0, term1, &aSig0, &aSig1 );
3136 shortShift128Left( 0, bSig, 64 - expDiff, &term0, &term1 );
3137 while ( le128( term0, term1, aSig0, aSig1 ) ) {
3138 ++q;
3139 sub128( aSig0, aSig1, term0, term1, &aSig0, &aSig1 );
3140 }
3141 }
3142 else {
3143 term1 = 0;
3144 term0 = bSig;
3145 }
3146 sub128( term0, term1, aSig0, aSig1, &alternateASig0, &alternateASig1 );
3147 if ( lt128( alternateASig0, alternateASig1, aSig0, aSig1 )
3148 || ( eq128( alternateASig0, alternateASig1, aSig0, aSig1 )
3149 && ( q & 1 ) )
3150 ) {
3151 aSig0 = alternateASig0;
3152 aSig1 = alternateASig1;
3153 zSign = ! zSign;
3154 }
3155 return
3156 normalizeRoundAndPackFloatx80(
3157 80, zSign, bExp + expDiff, aSig0, aSig1 );
3158
3159}
3160
3161/*
3162-------------------------------------------------------------------------------
3163Returns the square root of the extended double-precision floating-point
3164value `a'. The operation is performed according to the IEC/IEEE Standard
3165for Binary Floating-point Arithmetic.
3166-------------------------------------------------------------------------------
3167*/
3168floatx80 floatx80_sqrt( floatx80 a )
3169{
3170 flag aSign;
3171 int32 aExp, zExp;
3172 bits64 aSig0, aSig1, zSig0, zSig1;
3173 bits64 rem0, rem1, rem2, rem3, term0, term1, term2, term3;
3174 bits64 shiftedRem0, shiftedRem1;
3175 floatx80 z;
3176
3177 aSig0 = extractFloatx80Frac( a );
3178 aExp = extractFloatx80Exp( a );
3179 aSign = extractFloatx80Sign( a );
3180 if ( aExp == 0x7FFF ) {
3181 if ( (bits64) ( aSig0<<1 ) ) return propagateFloatx80NaN( a, a );
3182 if ( ! aSign ) return a;
3183 goto invalid;
3184 }
3185 if ( aSign ) {
3186 if ( ( aExp | aSig0 ) == 0 ) return a;
3187 invalid:
3188 float_raise( float_flag_invalid );
3189 z.low = floatx80_default_nan_low;
3190 z.high = floatx80_default_nan_high;
3191 return z;
3192 }
3193 if ( aExp == 0 ) {
3194 if ( aSig0 == 0 ) return packFloatx80( 0, 0, 0 );
3195 normalizeFloatx80Subnormal( aSig0, &aExp, &aSig0 );
3196 }
3197 zExp = ( ( aExp - 0x3FFF )>>1 ) + 0x3FFF;
3198 zSig0 = estimateSqrt32( aExp, aSig0>>32 );
3199 zSig0 <<= 31;
3200 aSig1 = 0;
3201 shift128Right( aSig0, 0, ( aExp & 1 ) + 2, &aSig0, &aSig1 );
3202 zSig0 = estimateDiv128To64( aSig0, aSig1, zSig0 ) + zSig0 + 4;
3203 if ( 0 <= (sbits64) zSig0 ) zSig0 = LIT64( 0xFFFFFFFFFFFFFFFF );
3204 shortShift128Left( aSig0, aSig1, 2, &aSig0, &aSig1 );
3205 mul64To128( zSig0, zSig0, &term0, &term1 );
3206 sub128( aSig0, aSig1, term0, term1, &rem0, &rem1 );
3207 while ( (sbits64) rem0 < 0 ) {
3208 --zSig0;
3209 shortShift128Left( 0, zSig0, 1, &term0, &term1 );
3210 term1 |= 1;
3211 add128( rem0, rem1, term0, term1, &rem0, &rem1 );
3212 }
3213 shortShift128Left( rem0, rem1, 63, &shiftedRem0, &shiftedRem1 );
3214 zSig1 = estimateDiv128To64( shiftedRem0, shiftedRem1, zSig0 );
3215 if ( (bits64) ( zSig1<<1 ) <= 10 ) {
3216 if ( zSig1 == 0 ) zSig1 = 1;
3217 mul64To128( zSig0, zSig1, &term1, &term2 );
3218 shortShift128Left( term1, term2, 1, &term1, &term2 );
3219 sub128( rem1, 0, term1, term2, &rem1, &rem2 );
3220 mul64To128( zSig1, zSig1, &term2, &term3 );
3221 sub192( rem1, rem2, 0, 0, term2, term3, &rem1, &rem2, &rem3 );
3222 while ( (sbits64) rem1 < 0 ) {
3223 --zSig1;
3224 shortShift192Left( 0, zSig0, zSig1, 1, &term1, &term2, &term3 );
3225 term3 |= 1;
3226 add192(
3227 rem1, rem2, rem3, term1, term2, term3, &rem1, &rem2, &rem3 );
3228 }
3229 zSig1 |= ( ( rem1 | rem2 | rem3 ) != 0 );
3230 }
3231 return
3232 roundAndPackFloatx80(
3233 floatx80_rounding_precision, 0, zExp, zSig0, zSig1 );
3234
3235}
3236
3237/*
3238-------------------------------------------------------------------------------
3239Returns 1 if the extended double-precision floating-point value `a' is
3240equal to the corresponding value `b', and 0 otherwise. The comparison is
3241performed according to the IEC/IEEE Standard for Binary Floating-point
3242Arithmetic.
3243-------------------------------------------------------------------------------
3244*/
3245flag floatx80_eq( floatx80 a, floatx80 b )
3246{
3247
3248 if ( ( ( extractFloatx80Exp( a ) == 0x7FFF )
3249 && (bits64) ( extractFloatx80Frac( a )<<1 ) )
3250 || ( ( extractFloatx80Exp( b ) == 0x7FFF )
3251 && (bits64) ( extractFloatx80Frac( b )<<1 ) )
3252 ) {
3253 if ( floatx80_is_signaling_nan( a )
3254 || floatx80_is_signaling_nan( b ) ) {
3255 float_raise( float_flag_invalid );
3256 }
3257 return 0;
3258 }
3259 return
3260 ( a.low == b.low )
3261 && ( ( a.high == b.high )
3262 || ( ( a.low == 0 )
3263 && ( (bits16) ( ( a.high | b.high )<<1 ) == 0 ) )
3264 );
3265
3266}
3267
3268/*
3269-------------------------------------------------------------------------------
3270Returns 1 if the extended double-precision floating-point value `a' is
3271less than or equal to the corresponding value `b', and 0 otherwise. The
3272comparison is performed according to the IEC/IEEE Standard for Binary
3273Floating-point Arithmetic.
3274-------------------------------------------------------------------------------
3275*/
3276flag floatx80_le( floatx80 a, floatx80 b )
3277{
3278 flag aSign, bSign;
3279
3280 if ( ( ( extractFloatx80Exp( a ) == 0x7FFF )
3281 && (bits64) ( extractFloatx80Frac( a )<<1 ) )
3282 || ( ( extractFloatx80Exp( b ) == 0x7FFF )
3283 && (bits64) ( extractFloatx80Frac( b )<<1 ) )
3284 ) {
3285 float_raise( float_flag_invalid );
3286 return 0;
3287 }
3288 aSign = extractFloatx80Sign( a );
3289 bSign = extractFloatx80Sign( b );
3290 if ( aSign != bSign ) {
3291 return
3292 aSign
3293 || ( ( ( (bits16) ( ( a.high | b.high )<<1 ) ) | a.low | b.low )
3294 == 0 );
3295 }
3296 return
3297 aSign ? le128( b.high, b.low, a.high, a.low )
3298 : le128( a.high, a.low, b.high, b.low );
3299
3300}
3301
3302/*
3303-------------------------------------------------------------------------------
3304Returns 1 if the extended double-precision floating-point value `a' is
3305less than the corresponding value `b', and 0 otherwise. The comparison
3306is performed according to the IEC/IEEE Standard for Binary Floating-point
3307Arithmetic.
3308-------------------------------------------------------------------------------
3309*/
3310flag floatx80_lt( floatx80 a, floatx80 b )
3311{
3312 flag aSign, bSign;
3313
3314 if ( ( ( extractFloatx80Exp( a ) == 0x7FFF )
3315 && (bits64) ( extractFloatx80Frac( a )<<1 ) )
3316 || ( ( extractFloatx80Exp( b ) == 0x7FFF )
3317 && (bits64) ( extractFloatx80Frac( b )<<1 ) )
3318 ) {
3319 float_raise( float_flag_invalid );
3320 return 0;
3321 }
3322 aSign = extractFloatx80Sign( a );
3323 bSign = extractFloatx80Sign( b );
3324 if ( aSign != bSign ) {
3325 return
3326 aSign
3327 && ( ( ( (bits16) ( ( a.high | b.high )<<1 ) ) | a.low | b.low )
3328 != 0 );
3329 }
3330 return
3331 aSign ? lt128( b.high, b.low, a.high, a.low )
3332 : lt128( a.high, a.low, b.high, b.low );
3333
3334}
3335
3336/*
3337-------------------------------------------------------------------------------
3338Returns 1 if the extended double-precision floating-point value `a' is equal
3339to the corresponding value `b', and 0 otherwise. The invalid exception is
3340raised if either operand is a NaN. Otherwise, the comparison is performed
3341according to the IEC/IEEE Standard for Binary Floating-point Arithmetic.
3342-------------------------------------------------------------------------------
3343*/
3344flag floatx80_eq_signaling( floatx80 a, floatx80 b )
3345{
3346
3347 if ( ( ( extractFloatx80Exp( a ) == 0x7FFF )
3348 && (bits64) ( extractFloatx80Frac( a )<<1 ) )
3349 || ( ( extractFloatx80Exp( b ) == 0x7FFF )
3350 && (bits64) ( extractFloatx80Frac( b )<<1 ) )
3351 ) {
3352 float_raise( float_flag_invalid );
3353 return 0;
3354 }
3355 return
3356 ( a.low == b.low )
3357 && ( ( a.high == b.high )
3358 || ( ( a.low == 0 )
3359 && ( (bits16) ( ( a.high | b.high )<<1 ) == 0 ) )
3360 );
3361
3362}
3363
3364/*
3365-------------------------------------------------------------------------------
3366Returns 1 if the extended double-precision floating-point value `a' is less
3367than or equal to the corresponding value `b', and 0 otherwise. Quiet NaNs
3368do not cause an exception. Otherwise, the comparison is performed according
3369to the IEC/IEEE Standard for Binary Floating-point Arithmetic.
3370-------------------------------------------------------------------------------
3371*/
3372flag floatx80_le_quiet( floatx80 a, floatx80 b )
3373{
3374 flag aSign, bSign;
3375
3376 if ( ( ( extractFloatx80Exp( a ) == 0x7FFF )
3377 && (bits64) ( extractFloatx80Frac( a )<<1 ) )
3378 || ( ( extractFloatx80Exp( b ) == 0x7FFF )
3379 && (bits64) ( extractFloatx80Frac( b )<<1 ) )
3380 ) {
3381 if ( floatx80_is_signaling_nan( a )
3382 || floatx80_is_signaling_nan( b ) ) {
3383 float_raise( float_flag_invalid );
3384 }
3385 return 0;
3386 }
3387 aSign = extractFloatx80Sign( a );
3388 bSign = extractFloatx80Sign( b );
3389 if ( aSign != bSign ) {
3390 return
3391 aSign
3392 || ( ( ( (bits16) ( ( a.high | b.high )<<1 ) ) | a.low | b.low )
3393 == 0 );
3394 }
3395 return
3396 aSign ? le128( b.high, b.low, a.high, a.low )
3397 : le128( a.high, a.low, b.high, b.low );
3398
3399}
3400
3401/*
3402-------------------------------------------------------------------------------
3403Returns 1 if the extended double-precision floating-point value `a' is less
3404than the corresponding value `b', and 0 otherwise. Quiet NaNs do not cause
3405an exception. Otherwise, the comparison is performed according to the
3406IEC/IEEE Standard for Binary Floating-point Arithmetic.
3407-------------------------------------------------------------------------------
3408*/
3409flag floatx80_lt_quiet( floatx80 a, floatx80 b )
3410{
3411 flag aSign, bSign;
3412
3413 if ( ( ( extractFloatx80Exp( a ) == 0x7FFF )
3414 && (bits64) ( extractFloatx80Frac( a )<<1 ) )
3415 || ( ( extractFloatx80Exp( b ) == 0x7FFF )
3416 && (bits64) ( extractFloatx80Frac( b )<<1 ) )
3417 ) {
3418 if ( floatx80_is_signaling_nan( a )
3419 || floatx80_is_signaling_nan( b ) ) {
3420 float_raise( float_flag_invalid );
3421 }
3422 return 0;
3423 }
3424 aSign = extractFloatx80Sign( a );
3425 bSign = extractFloatx80Sign( b );
3426 if ( aSign != bSign ) {
3427 return
3428 aSign
3429 && ( ( ( (bits16) ( ( a.high | b.high )<<1 ) ) | a.low | b.low )
3430 != 0 );
3431 }
3432 return
3433 aSign ? lt128( b.high, b.low, a.high, a.low )
3434 : lt128( a.high, a.low, b.high, b.low );
3435
3436}
3437
3438#endif
3439
diff --git a/arch/arm26/nwfpe/softfloat.h b/arch/arm26/nwfpe/softfloat.h
new file mode 100644
index 000000000000..22c2193a4997
--- /dev/null
+++ b/arch/arm26/nwfpe/softfloat.h
@@ -0,0 +1,232 @@
1
2/*
3===============================================================================
4
5This C header file is part of the SoftFloat IEC/IEEE Floating-point
6Arithmetic Package, Release 2.
7
8Written by John R. Hauser. This work was made possible in part by the
9International Computer Science Institute, located at Suite 600, 1947 Center
10Street, Berkeley, California 94704. Funding was partially provided by the
11National Science Foundation under grant MIP-9311980. The original version
12of this code was written as part of a project to build a fixed-point vector
13processor in collaboration with the University of California at Berkeley,
14overseen by Profs. Nelson Morgan and John Wawrzynek. More information
15is available through the Web page `http://HTTP.CS.Berkeley.EDU/~jhauser/
16arithmetic/softfloat.html'.
17
18THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort
19has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT
20TIMES RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO
21PERSONS AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ANY
22AND ALL LOSSES, COSTS, OR OTHER PROBLEMS ARISING FROM ITS USE.
23
24Derivative works are acceptable, even for commercial purposes, so long as
25(1) they include prominent notice that the work is derivative, and (2) they
26include prominent notice akin to these three paragraphs for those parts of
27this code that are retained.
28
29===============================================================================
30*/
31
32#ifndef __SOFTFLOAT_H__
33#define __SOFTFLOAT_H__
34
35/*
36-------------------------------------------------------------------------------
37The macro `FLOATX80' must be defined to enable the extended double-precision
38floating-point format `floatx80'. If this macro is not defined, the
39`floatx80' type will not be defined, and none of the functions that either
40input or output the `floatx80' type will be defined.
41-------------------------------------------------------------------------------
42*/
43#define FLOATX80
44
45/*
46-------------------------------------------------------------------------------
47Software IEC/IEEE floating-point types.
48-------------------------------------------------------------------------------
49*/
50typedef unsigned long int float32;
51typedef unsigned long long float64;
52typedef struct {
53 unsigned short high;
54 unsigned long long low;
55} floatx80;
56
57/*
58-------------------------------------------------------------------------------
59Software IEC/IEEE floating-point underflow tininess-detection mode.
60-------------------------------------------------------------------------------
61*/
62extern signed char float_detect_tininess;
63enum {
64 float_tininess_after_rounding = 0,
65 float_tininess_before_rounding = 1
66};
67
68/*
69-------------------------------------------------------------------------------
70Software IEC/IEEE floating-point rounding mode.
71-------------------------------------------------------------------------------
72*/
73extern signed char float_rounding_mode;
74enum {
75 float_round_nearest_even = 0,
76 float_round_to_zero = 1,
77 float_round_down = 2,
78 float_round_up = 3
79};
80
81/*
82-------------------------------------------------------------------------------
83Software IEC/IEEE floating-point exception flags.
84-------------------------------------------------------------------------------
85extern signed char float_exception_flags;
86enum {
87 float_flag_inexact = 1,
88 float_flag_underflow = 2,
89 float_flag_overflow = 4,
90 float_flag_divbyzero = 8,
91 float_flag_invalid = 16
92};
93
94ScottB: November 4, 1998
95Changed the enumeration to match the bit order in the FPA11.
96*/
97
98extern signed char float_exception_flags;
99enum {
100 float_flag_invalid = 1,
101 float_flag_divbyzero = 2,
102 float_flag_overflow = 4,
103 float_flag_underflow = 8,
104 float_flag_inexact = 16
105};
106
107/*
108-------------------------------------------------------------------------------
109Routine to raise any or all of the software IEC/IEEE floating-point
110exception flags.
111-------------------------------------------------------------------------------
112*/
113void float_raise( signed char );
114
115/*
116-------------------------------------------------------------------------------
117Software IEC/IEEE integer-to-floating-point conversion routines.
118-------------------------------------------------------------------------------
119*/
120float32 int32_to_float32( signed int );
121float64 int32_to_float64( signed int );
122#ifdef FLOATX80
123floatx80 int32_to_floatx80( signed int );
124#endif
125
126/*
127-------------------------------------------------------------------------------
128Software IEC/IEEE single-precision conversion routines.
129-------------------------------------------------------------------------------
130*/
131signed int float32_to_int32( float32 );
132signed int float32_to_int32_round_to_zero( float32 );
133float64 float32_to_float64( float32 );
134#ifdef FLOATX80
135floatx80 float32_to_floatx80( float32 );
136#endif
137
138/*
139-------------------------------------------------------------------------------
140Software IEC/IEEE single-precision operations.
141-------------------------------------------------------------------------------
142*/
143float32 float32_round_to_int( float32 );
144float32 float32_add( float32, float32 );
145float32 float32_sub( float32, float32 );
146float32 float32_mul( float32, float32 );
147float32 float32_div( float32, float32 );
148float32 float32_rem( float32, float32 );
149float32 float32_sqrt( float32 );
150char float32_eq( float32, float32 );
151char float32_le( float32, float32 );
152char float32_lt( float32, float32 );
153char float32_eq_signaling( float32, float32 );
154char float32_le_quiet( float32, float32 );
155char float32_lt_quiet( float32, float32 );
156char float32_is_signaling_nan( float32 );
157
158/*
159-------------------------------------------------------------------------------
160Software IEC/IEEE double-precision conversion routines.
161-------------------------------------------------------------------------------
162*/
163signed int float64_to_int32( float64 );
164signed int float64_to_int32_round_to_zero( float64 );
165float32 float64_to_float32( float64 );
166#ifdef FLOATX80
167floatx80 float64_to_floatx80( float64 );
168#endif
169
170/*
171-------------------------------------------------------------------------------
172Software IEC/IEEE double-precision operations.
173-------------------------------------------------------------------------------
174*/
175float64 float64_round_to_int( float64 );
176float64 float64_add( float64, float64 );
177float64 float64_sub( float64, float64 );
178float64 float64_mul( float64, float64 );
179float64 float64_div( float64, float64 );
180float64 float64_rem( float64, float64 );
181float64 float64_sqrt( float64 );
182char float64_eq( float64, float64 );
183char float64_le( float64, float64 );
184char float64_lt( float64, float64 );
185char float64_eq_signaling( float64, float64 );
186char float64_le_quiet( float64, float64 );
187char float64_lt_quiet( float64, float64 );
188char float64_is_signaling_nan( float64 );
189
190#ifdef FLOATX80
191
192/*
193-------------------------------------------------------------------------------
194Software IEC/IEEE extended double-precision conversion routines.
195-------------------------------------------------------------------------------
196*/
197signed int floatx80_to_int32( floatx80 );
198signed int floatx80_to_int32_round_to_zero( floatx80 );
199float32 floatx80_to_float32( floatx80 );
200float64 floatx80_to_float64( floatx80 );
201
202/*
203-------------------------------------------------------------------------------
204Software IEC/IEEE extended double-precision rounding precision. Valid
205values are 32, 64, and 80.
206-------------------------------------------------------------------------------
207*/
208extern signed char floatx80_rounding_precision;
209
210/*
211-------------------------------------------------------------------------------
212Software IEC/IEEE extended double-precision operations.
213-------------------------------------------------------------------------------
214*/
215floatx80 floatx80_round_to_int( floatx80 );
216floatx80 floatx80_add( floatx80, floatx80 );
217floatx80 floatx80_sub( floatx80, floatx80 );
218floatx80 floatx80_mul( floatx80, floatx80 );
219floatx80 floatx80_div( floatx80, floatx80 );
220floatx80 floatx80_rem( floatx80, floatx80 );
221floatx80 floatx80_sqrt( floatx80 );
222char floatx80_eq( floatx80, floatx80 );
223char floatx80_le( floatx80, floatx80 );
224char floatx80_lt( floatx80, floatx80 );
225char floatx80_eq_signaling( floatx80, floatx80 );
226char floatx80_le_quiet( floatx80, floatx80 );
227char floatx80_lt_quiet( floatx80, floatx80 );
228char floatx80_is_signaling_nan( floatx80 );
229
230#endif
231
232#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-21 21:19:36 -0500