diff options
Diffstat (limited to 'arch/arm26/lib/io-writesw.S')
-rw-r--r-- | arch/arm26/lib/io-writesw.S | 127 |
1 files changed, 127 insertions, 0 deletions
diff --git a/arch/arm26/lib/io-writesw.S b/arch/arm26/lib/io-writesw.S new file mode 100644 index 000000000000..a24f891f6b1c --- /dev/null +++ b/arch/arm26/lib/io-writesw.S | |||
@@ -0,0 +1,127 @@ | |||
1 | /* | ||
2 | * linux/arch/arm26/lib/io-writesw.S | ||
3 | * | ||
4 | * Copyright (C) 1995-2000 Russell King | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | #include <linux/linkage.h> | ||
11 | #include <asm/assembler.h> | ||
12 | #include <asm/hardware.h> | ||
13 | |||
14 | .outsw_bad_alignment: | ||
15 | adr r0, .outsw_bad_align_msg | ||
16 | mov r2, lr | ||
17 | b panic | ||
18 | .outsw_bad_align_msg: | ||
19 | .asciz "outsw: bad buffer alignment (0x%p, lr=0x%08lX)\n" | ||
20 | .align | ||
21 | |||
22 | .outsw_align: tst r1, #1 | ||
23 | bne .outsw_bad_alignment | ||
24 | |||
25 | add r1, r1, #2 | ||
26 | |||
27 | ldr r3, [r1, #-4] | ||
28 | mov r3, r3, lsr #16 | ||
29 | orr r3, r3, r3, lsl #16 | ||
30 | str r3, [r0] | ||
31 | subs r2, r2, #1 | ||
32 | RETINSTR(moveq, pc, lr) | ||
33 | |||
34 | ENTRY(__raw_writesw) | ||
35 | teq r2, #0 @ do we have to check for the zero len? | ||
36 | moveq pc, lr | ||
37 | tst r1, #3 | ||
38 | bne .outsw_align | ||
39 | |||
40 | .outsw_aligned: stmfd sp!, {r4, r5, r6, lr} | ||
41 | |||
42 | subs r2, r2, #8 | ||
43 | bmi .no_outsw_8 | ||
44 | |||
45 | .outsw_8_lp: ldmia r1!, {r3, r4, r5, r6} | ||
46 | |||
47 | mov ip, r3, lsl #16 | ||
48 | orr ip, ip, ip, lsr #16 | ||
49 | str ip, [r0] | ||
50 | |||
51 | mov ip, r3, lsr #16 | ||
52 | orr ip, ip, ip, lsl #16 | ||
53 | str ip, [r0] | ||
54 | |||
55 | mov ip, r4, lsl #16 | ||
56 | orr ip, ip, ip, lsr #16 | ||
57 | str ip, [r0] | ||
58 | |||
59 | mov ip, r4, lsr #16 | ||
60 | orr ip, ip, ip, lsl #16 | ||
61 | str ip, [r0] | ||
62 | |||
63 | mov ip, r5, lsl #16 | ||
64 | orr ip, ip, ip, lsr #16 | ||
65 | str ip, [r0] | ||
66 | |||
67 | mov ip, r5, lsr #16 | ||
68 | orr ip, ip, ip, lsl #16 | ||
69 | str ip, [r0] | ||
70 | |||
71 | mov ip, r6, lsl #16 | ||
72 | orr ip, ip, ip, lsr #16 | ||
73 | str ip, [r0] | ||
74 | |||
75 | mov ip, r6, lsr #16 | ||
76 | orr ip, ip, ip, lsl #16 | ||
77 | str ip, [r0] | ||
78 | |||
79 | subs r2, r2, #8 | ||
80 | bpl .outsw_8_lp | ||
81 | |||
82 | tst r2, #7 | ||
83 | LOADREGS(eqfd, sp!, {r4, r5, r6, pc}) | ||
84 | |||
85 | .no_outsw_8: tst r2, #4 | ||
86 | beq .no_outsw_4 | ||
87 | |||
88 | ldmia r1!, {r3, r4} | ||
89 | |||
90 | mov ip, r3, lsl #16 | ||
91 | orr ip, ip, ip, lsr #16 | ||
92 | str ip, [r0] | ||
93 | |||
94 | mov ip, r3, lsr #16 | ||
95 | orr ip, ip, ip, lsl #16 | ||
96 | str ip, [r0] | ||
97 | |||
98 | mov ip, r4, lsl #16 | ||
99 | orr ip, ip, ip, lsr #16 | ||
100 | str ip, [r0] | ||
101 | |||
102 | mov ip, r4, lsr #16 | ||
103 | orr ip, ip, ip, lsl #16 | ||
104 | str ip, [r0] | ||
105 | |||
106 | .no_outsw_4: tst r2, #2 | ||
107 | beq .no_outsw_2 | ||
108 | |||
109 | ldr r3, [r1], #4 | ||
110 | |||
111 | mov ip, r3, lsl #16 | ||
112 | orr ip, ip, ip, lsr #16 | ||
113 | str ip, [r0] | ||
114 | |||
115 | mov ip, r3, lsr #16 | ||
116 | orr ip, ip, ip, lsl #16 | ||
117 | str ip, [r0] | ||
118 | |||
119 | .no_outsw_2: tst r2, #1 | ||
120 | |||
121 | ldrne r3, [r1] | ||
122 | |||
123 | movne ip, r3, lsl #16 | ||
124 | orrne ip, ip, ip, lsr #16 | ||
125 | strne ip, [r0] | ||
126 | |||
127 | LOADREGS(fd, sp!, {r4, r5, r6, pc}) | ||