diff options
Diffstat (limited to 'arch/arm26/kernel/fiq.c')
| -rw-r--r-- | arch/arm26/kernel/fiq.c | 32 |
1 files changed, 16 insertions, 16 deletions
diff --git a/arch/arm26/kernel/fiq.c b/arch/arm26/kernel/fiq.c index 08a97c9498ff..a24272b61f30 100644 --- a/arch/arm26/kernel/fiq.c +++ b/arch/arm26/kernel/fiq.c | |||
| @@ -104,14 +104,14 @@ void set_fiq_regs(struct pt_regs *regs) | |||
| 104 | { | 104 | { |
| 105 | register unsigned long tmp, tmp2; | 105 | register unsigned long tmp, tmp2; |
| 106 | __asm__ volatile ( | 106 | __asm__ volatile ( |
| 107 | "mov %0, pc | 107 | "mov %0, pc \n" |
| 108 | bic %1, %0, #0x3 | 108 | "bic %1, %0, #0x3 \n" |
| 109 | orr %1, %1, %3 | 109 | "orr %1, %1, %3 \n" |
| 110 | teqp %1, #0 @ select FIQ mode | 110 | "teqp %1, #0 @ select FIQ mode \n" |
| 111 | mov r0, r0 | 111 | "mov r0, r0 \n" |
| 112 | ldmia %2, {r8 - r14} | 112 | "ldmia %2, {r8 - r14} \n" |
| 113 | teqp %0, #0 @ return to SVC mode | 113 | "teqp %0, #0 @ return to SVC mode \n" |
| 114 | mov r0, r0" | 114 | "mov r0, r0 " |
| 115 | : "=&r" (tmp), "=&r" (tmp2) | 115 | : "=&r" (tmp), "=&r" (tmp2) |
| 116 | : "r" (®s->ARM_r8), "I" (PSR_I_BIT | PSR_F_BIT | MODE_FIQ26) | 116 | : "r" (®s->ARM_r8), "I" (PSR_I_BIT | PSR_F_BIT | MODE_FIQ26) |
| 117 | /* These registers aren't modified by the above code in a way | 117 | /* These registers aren't modified by the above code in a way |
| @@ -125,14 +125,14 @@ void get_fiq_regs(struct pt_regs *regs) | |||
| 125 | { | 125 | { |
| 126 | register unsigned long tmp, tmp2; | 126 | register unsigned long tmp, tmp2; |
| 127 | __asm__ volatile ( | 127 | __asm__ volatile ( |
| 128 | "mov %0, pc | 128 | "mov %0, pc \n" |
| 129 | bic %1, %0, #0x3 | 129 | "bic %1, %0, #0x3 \n" |
| 130 | orr %1, %1, %3 | 130 | "orr %1, %1, %3 \n" |
| 131 | teqp %1, #0 @ select FIQ mode | 131 | "teqp %1, #0 @ select FIQ mode \n" |
| 132 | mov r0, r0 | 132 | "mov r0, r0 \n" |
| 133 | stmia %2, {r8 - r14} | 133 | "stmia %2, {r8 - r14} \n" |
| 134 | teqp %0, #0 @ return to SVC mode | 134 | "teqp %0, #0 @ return to SVC mode \n" |
| 135 | mov r0, r0" | 135 | "mov r0, r0 " |
| 136 | : "=&r" (tmp), "=&r" (tmp2) | 136 | : "=&r" (tmp), "=&r" (tmp2) |
| 137 | : "r" (®s->ARM_r8), "I" (PSR_I_BIT | PSR_F_BIT | MODE_FIQ26) | 137 | : "r" (®s->ARM_r8), "I" (PSR_I_BIT | PSR_F_BIT | MODE_FIQ26) |
| 138 | /* These registers aren't modified by the above code in a way | 138 | /* These registers aren't modified by the above code in a way |