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-rw-r--r--arch/arm/vfp/vfp.h6
-rw-r--r--arch/arm/vfp/vfpdouble.c73
-rw-r--r--arch/arm/vfp/vfpsingle.c79
3 files changed, 73 insertions, 85 deletions
diff --git a/arch/arm/vfp/vfp.h b/arch/arm/vfp/vfp.h
index 19ace2e37789..f2797896e6d5 100644
--- a/arch/arm/vfp/vfp.h
+++ b/arch/arm/vfp/vfp.h
@@ -357,10 +357,14 @@ u32 vfp_estimate_sqrt_significand(u32 exponent, u32 significand);
357#define VFP_EXCEPTION_ERROR ((u32)-1 & ~VFP_NAN_FLAG) 357#define VFP_EXCEPTION_ERROR ((u32)-1 & ~VFP_NAN_FLAG)
358 358
359/* 359/*
360 * A flag to tell vfp instruction type 360 * A flag to tell vfp instruction type.
361 * OP_SCALAR - this operation always operates in scalar mode
362 * OP_SD - the instruction exceptionally writes to a single precision result.
363 * OP_DD - the instruction exceptionally writes to a double precision result.
361 */ 364 */
362#define OP_SCALAR (1 << 0) 365#define OP_SCALAR (1 << 0)
363#define OP_SD (1 << 1) 366#define OP_SD (1 << 1)
367#define OP_DD (1 << 1)
364 368
365struct op { 369struct op {
366 u32 (* const fn)(int dd, int dn, int dm, u32 fpscr); 370 u32 (* const fn)(int dd, int dn, int dm, u32 fpscr);
diff --git a/arch/arm/vfp/vfpdouble.c b/arch/arm/vfp/vfpdouble.c
index e19a4f7620de..4fc05ee0a2ef 100644
--- a/arch/arm/vfp/vfpdouble.c
+++ b/arch/arm/vfp/vfpdouble.c
@@ -660,21 +660,21 @@ static u32 vfp_double_ftosiz(int dd, int unused, int dm, u32 fpscr)
660 660
661 661
662static struct op fops_ext[32] = { 662static struct op fops_ext[32] = {
663 [FEXT_TO_IDX(FEXT_FCPY)] = {vfp_double_fcpy, 0}, 663 [FEXT_TO_IDX(FEXT_FCPY)] = { vfp_double_fcpy, 0 },
664 [FEXT_TO_IDX(FEXT_FABS)] = {vfp_double_fabs, 0}, 664 [FEXT_TO_IDX(FEXT_FABS)] = { vfp_double_fabs, 0 },
665 [FEXT_TO_IDX(FEXT_FNEG)] = {vfp_double_fneg, 0}, 665 [FEXT_TO_IDX(FEXT_FNEG)] = { vfp_double_fneg, 0 },
666 [FEXT_TO_IDX(FEXT_FSQRT)] = {vfp_double_fsqrt, 0}, 666 [FEXT_TO_IDX(FEXT_FSQRT)] = { vfp_double_fsqrt, 0 },
667 [FEXT_TO_IDX(FEXT_FCMP)] = {vfp_double_fcmp, OP_SCALAR}, 667 [FEXT_TO_IDX(FEXT_FCMP)] = { vfp_double_fcmp, OP_SCALAR },
668 [FEXT_TO_IDX(FEXT_FCMPE)] = {vfp_double_fcmpe, OP_SCALAR}, 668 [FEXT_TO_IDX(FEXT_FCMPE)] = { vfp_double_fcmpe, OP_SCALAR },
669 [FEXT_TO_IDX(FEXT_FCMPZ)] = {vfp_double_fcmpz, OP_SCALAR}, 669 [FEXT_TO_IDX(FEXT_FCMPZ)] = { vfp_double_fcmpz, OP_SCALAR },
670 [FEXT_TO_IDX(FEXT_FCMPEZ)] = {vfp_double_fcmpez, OP_SCALAR}, 670 [FEXT_TO_IDX(FEXT_FCMPEZ)] = { vfp_double_fcmpez, OP_SCALAR },
671 [FEXT_TO_IDX(FEXT_FCVT)] = {vfp_double_fcvts, (OP_SD|OP_SCALAR)}, 671 [FEXT_TO_IDX(FEXT_FCVT)] = { vfp_double_fcvts, OP_SCALAR|OP_SD },
672 [FEXT_TO_IDX(FEXT_FUITO)] = {vfp_double_fuito, OP_SCALAR}, 672 [FEXT_TO_IDX(FEXT_FUITO)] = { vfp_double_fuito, OP_SCALAR },
673 [FEXT_TO_IDX(FEXT_FSITO)] = {vfp_double_fsito, OP_SCALAR}, 673 [FEXT_TO_IDX(FEXT_FSITO)] = { vfp_double_fsito, OP_SCALAR },
674 [FEXT_TO_IDX(FEXT_FTOUI)] = {vfp_double_ftoui, (OP_SD|OP_SCALAR)}, 674 [FEXT_TO_IDX(FEXT_FTOUI)] = { vfp_double_ftoui, OP_SCALAR|OP_SD },
675 [FEXT_TO_IDX(FEXT_FTOUIZ)] = {vfp_double_ftouiz, (OP_SD|OP_SCALAR)}, 675 [FEXT_TO_IDX(FEXT_FTOUIZ)] = { vfp_double_ftouiz, OP_SCALAR|OP_SD },
676 [FEXT_TO_IDX(FEXT_FTOSI)] = {vfp_double_ftosi, (OP_SD|OP_SCALAR)}, 676 [FEXT_TO_IDX(FEXT_FTOSI)] = { vfp_double_ftosi, OP_SCALAR|OP_SD },
677 [FEXT_TO_IDX(FEXT_FTOSIZ)] = {vfp_double_ftosiz, (OP_SD|OP_SCALAR)}, 677 [FEXT_TO_IDX(FEXT_FTOSIZ)] = { vfp_double_ftosiz, OP_SCALAR|OP_SD },
678}; 678};
679 679
680 680
@@ -1109,15 +1109,15 @@ static u32 vfp_double_fdiv(int dd, int dn, int dm, u32 fpscr)
1109} 1109}
1110 1110
1111static struct op fops[16] = { 1111static struct op fops[16] = {
1112 [FOP_TO_IDX(FOP_FMAC)] = {vfp_double_fmac, 0}, 1112 [FOP_TO_IDX(FOP_FMAC)] = { vfp_double_fmac, 0 },
1113 [FOP_TO_IDX(FOP_FNMAC)] = {vfp_double_fnmac, 0}, 1113 [FOP_TO_IDX(FOP_FNMAC)] = { vfp_double_fnmac, 0 },
1114 [FOP_TO_IDX(FOP_FMSC)] = {vfp_double_fmsc, 0}, 1114 [FOP_TO_IDX(FOP_FMSC)] = { vfp_double_fmsc, 0 },
1115 [FOP_TO_IDX(FOP_FNMSC)] = {vfp_double_fnmsc, 0}, 1115 [FOP_TO_IDX(FOP_FNMSC)] = { vfp_double_fnmsc, 0 },
1116 [FOP_TO_IDX(FOP_FMUL)] = {vfp_double_fmul, 0}, 1116 [FOP_TO_IDX(FOP_FMUL)] = { vfp_double_fmul, 0 },
1117 [FOP_TO_IDX(FOP_FNMUL)] = {vfp_double_fnmul, 0}, 1117 [FOP_TO_IDX(FOP_FNMUL)] = { vfp_double_fnmul, 0 },
1118 [FOP_TO_IDX(FOP_FADD)] = {vfp_double_fadd, 0}, 1118 [FOP_TO_IDX(FOP_FADD)] = { vfp_double_fadd, 0 },
1119 [FOP_TO_IDX(FOP_FSUB)] = {vfp_double_fsub, 0}, 1119 [FOP_TO_IDX(FOP_FSUB)] = { vfp_double_fsub, 0 },
1120 [FOP_TO_IDX(FOP_FDIV)] = {vfp_double_fdiv, 0}, 1120 [FOP_TO_IDX(FOP_FDIV)] = { vfp_double_fdiv, 0 },
1121}; 1121};
1122 1122
1123#define FREG_BANK(x) ((x) & 0x0c) 1123#define FREG_BANK(x) ((x) & 0x0c)
@@ -1136,6 +1136,7 @@ u32 vfp_double_cpdo(u32 inst, u32 fpscr)
1136 vecstride = (1 + ((fpscr & FPSCR_STRIDE_MASK) == FPSCR_STRIDE_MASK)) * 2; 1136 vecstride = (1 + ((fpscr & FPSCR_STRIDE_MASK) == FPSCR_STRIDE_MASK)) * 2;
1137 1137
1138 fop = (op == FOP_EXT) ? &fops_ext[FEXT_TO_IDX(inst)] : &fops[FOP_TO_IDX(op)]; 1138 fop = (op == FOP_EXT) ? &fops_ext[FEXT_TO_IDX(inst)] : &fops[FOP_TO_IDX(op)];
1139
1139 /* 1140 /*
1140 * fcvtds takes an sN register number as destination, not dN. 1141 * fcvtds takes an sN register number as destination, not dN.
1141 * It also always operates on scalars. 1142 * It also always operates on scalars.
@@ -1162,19 +1163,17 @@ u32 vfp_double_cpdo(u32 inst, u32 fpscr)
1162 1163
1163 for (vecitr = 0; vecitr <= veclen; vecitr += 1 << FPSCR_LENGTH_BIT) { 1164 for (vecitr = 0; vecitr <= veclen; vecitr += 1 << FPSCR_LENGTH_BIT) {
1164 u32 except; 1165 u32 except;
1166 char type;
1165 1167
1166 if (op == FOP_EXT && (fop->flags & OP_SD)) 1168 type = fop->flags & OP_SD ? 's' : 'd';
1167 pr_debug("VFP: itr%d (s%u) = op[%u] (d%u)\n", 1169 if (op == FOP_EXT)
1168 vecitr >> FPSCR_LENGTH_BIT, 1170 pr_debug("VFP: itr%d (%c%u) = op[%u] (d%u)\n",
1169 dest, dn, dm);
1170 else if (op == FOP_EXT)
1171 pr_debug("VFP: itr%d (d%u) = op[%u] (d%u)\n",
1172 vecitr >> FPSCR_LENGTH_BIT, 1171 vecitr >> FPSCR_LENGTH_BIT,
1173 dest, dn, dm); 1172 type, dest, dn, dm);
1174 else 1173 else
1175 pr_debug("VFP: itr%d (d%u) = (d%u) op[%u] (d%u)\n", 1174 pr_debug("VFP: itr%d (%c%u) = (d%u) op[%u] (d%u)\n",
1176 vecitr >> FPSCR_LENGTH_BIT, 1175 vecitr >> FPSCR_LENGTH_BIT,
1177 dest, dn, FOP_TO_IDX(op), dm); 1176 type, dest, dn, FOP_TO_IDX(op), dm);
1178 1177
1179 except = fop->fn(dest, dn, dm, fpscr); 1178 except = fop->fn(dest, dn, dm, fpscr);
1180 pr_debug("VFP: itr%d: exceptions=%08x\n", 1179 pr_debug("VFP: itr%d: exceptions=%08x\n",
@@ -1183,17 +1182,9 @@ u32 vfp_double_cpdo(u32 inst, u32 fpscr)
1183 exceptions |= except; 1182 exceptions |= except;
1184 1183
1185 /* 1184 /*
1186 * This ensures that comparisons only operate on scalars;
1187 * comparisons always return with one FPSCR status bit set.
1188 */
1189 if (except & (FPSCR_N|FPSCR_Z|FPSCR_C|FPSCR_V))
1190 break;
1191
1192 /*
1193 * CHECK: It appears to be undefined whether we stop when 1185 * CHECK: It appears to be undefined whether we stop when
1194 * we encounter an exception. We continue. 1186 * we encounter an exception. We continue.
1195 */ 1187 */
1196
1197 dest = FREG_BANK(dest) + ((FREG_IDX(dest) + vecstride) & 6); 1188 dest = FREG_BANK(dest) + ((FREG_IDX(dest) + vecstride) & 6);
1198 dn = FREG_BANK(dn) + ((FREG_IDX(dn) + vecstride) & 6); 1189 dn = FREG_BANK(dn) + ((FREG_IDX(dn) + vecstride) & 6);
1199 if (FREG_BANK(dm) != 0) 1190 if (FREG_BANK(dm) != 0)
diff --git a/arch/arm/vfp/vfpsingle.c b/arch/arm/vfp/vfpsingle.c
index 4f717d72eb6b..ab5e9503bae5 100644
--- a/arch/arm/vfp/vfpsingle.c
+++ b/arch/arm/vfp/vfpsingle.c
@@ -703,21 +703,21 @@ static u32 vfp_single_ftosiz(int sd, int unused, s32 m, u32 fpscr)
703} 703}
704 704
705static struct op fops_ext[32] = { 705static struct op fops_ext[32] = {
706 [FEXT_TO_IDX(FEXT_FCPY)] = {vfp_single_fcpy, 0}, 706 [FEXT_TO_IDX(FEXT_FCPY)] = { vfp_single_fcpy, 0 },
707 [FEXT_TO_IDX(FEXT_FABS)] = {vfp_single_fabs, 0}, 707 [FEXT_TO_IDX(FEXT_FABS)] = { vfp_single_fabs, 0 },
708 [FEXT_TO_IDX(FEXT_FNEG)] = {vfp_single_fneg, 0}, 708 [FEXT_TO_IDX(FEXT_FNEG)] = { vfp_single_fneg, 0 },
709 [FEXT_TO_IDX(FEXT_FSQRT)] = {vfp_single_fsqrt, 0}, 709 [FEXT_TO_IDX(FEXT_FSQRT)] = { vfp_single_fsqrt, 0 },
710 [FEXT_TO_IDX(FEXT_FCMP)] = {vfp_single_fcmp, OP_SCALAR}, 710 [FEXT_TO_IDX(FEXT_FCMP)] = { vfp_single_fcmp, OP_SCALAR },
711 [FEXT_TO_IDX(FEXT_FCMPE)] = {vfp_single_fcmpe, OP_SCALAR}, 711 [FEXT_TO_IDX(FEXT_FCMPE)] = { vfp_single_fcmpe, OP_SCALAR },
712 [FEXT_TO_IDX(FEXT_FCMPZ)] = {vfp_single_fcmpz, OP_SCALAR}, 712 [FEXT_TO_IDX(FEXT_FCMPZ)] = { vfp_single_fcmpz, OP_SCALAR },
713 [FEXT_TO_IDX(FEXT_FCMPEZ)] = {vfp_single_fcmpez, OP_SCALAR}, 713 [FEXT_TO_IDX(FEXT_FCMPEZ)] = { vfp_single_fcmpez, OP_SCALAR },
714 [FEXT_TO_IDX(FEXT_FCVT)] = {vfp_single_fcvtd, (OP_SD|OP_SCALAR)}, 714 [FEXT_TO_IDX(FEXT_FCVT)] = { vfp_single_fcvtd, OP_SCALAR|OP_DD },
715 [FEXT_TO_IDX(FEXT_FUITO)] = {vfp_single_fuito, OP_SCALAR}, 715 [FEXT_TO_IDX(FEXT_FUITO)] = { vfp_single_fuito, OP_SCALAR },
716 [FEXT_TO_IDX(FEXT_FSITO)] = {vfp_single_fsito, OP_SCALAR}, 716 [FEXT_TO_IDX(FEXT_FSITO)] = { vfp_single_fsito, OP_SCALAR },
717 [FEXT_TO_IDX(FEXT_FTOUI)] = {vfp_single_ftoui, OP_SCALAR}, 717 [FEXT_TO_IDX(FEXT_FTOUI)] = { vfp_single_ftoui, OP_SCALAR },
718 [FEXT_TO_IDX(FEXT_FTOUIZ)] = {vfp_single_ftouiz, OP_SCALAR}, 718 [FEXT_TO_IDX(FEXT_FTOUIZ)] = { vfp_single_ftouiz, OP_SCALAR },
719 [FEXT_TO_IDX(FEXT_FTOSI)] = {vfp_single_ftosi, OP_SCALAR}, 719 [FEXT_TO_IDX(FEXT_FTOSI)] = { vfp_single_ftosi, OP_SCALAR },
720 [FEXT_TO_IDX(FEXT_FTOSIZ)] = {vfp_single_ftosiz, OP_SCALAR}, 720 [FEXT_TO_IDX(FEXT_FTOSIZ)] = { vfp_single_ftosiz, OP_SCALAR },
721}; 721};
722 722
723 723
@@ -1152,15 +1152,15 @@ static u32 vfp_single_fdiv(int sd, int sn, s32 m, u32 fpscr)
1152} 1152}
1153 1153
1154static struct op fops[16] = { 1154static struct op fops[16] = {
1155 [FOP_TO_IDX(FOP_FMAC)] = {vfp_single_fmac, 0}, 1155 [FOP_TO_IDX(FOP_FMAC)] = { vfp_single_fmac, 0 },
1156 [FOP_TO_IDX(FOP_FNMAC)] = {vfp_single_fnmac, 0}, 1156 [FOP_TO_IDX(FOP_FNMAC)] = { vfp_single_fnmac, 0 },
1157 [FOP_TO_IDX(FOP_FMSC)] = {vfp_single_fmsc, 0}, 1157 [FOP_TO_IDX(FOP_FMSC)] = { vfp_single_fmsc, 0 },
1158 [FOP_TO_IDX(FOP_FNMSC)] = {vfp_single_fnmsc, 0}, 1158 [FOP_TO_IDX(FOP_FNMSC)] = { vfp_single_fnmsc, 0 },
1159 [FOP_TO_IDX(FOP_FMUL)] = {vfp_single_fmul, 0}, 1159 [FOP_TO_IDX(FOP_FMUL)] = { vfp_single_fmul, 0 },
1160 [FOP_TO_IDX(FOP_FNMUL)] = {vfp_single_fnmul, 0}, 1160 [FOP_TO_IDX(FOP_FNMUL)] = { vfp_single_fnmul, 0 },
1161 [FOP_TO_IDX(FOP_FADD)] = {vfp_single_fadd, 0}, 1161 [FOP_TO_IDX(FOP_FADD)] = { vfp_single_fadd, 0 },
1162 [FOP_TO_IDX(FOP_FSUB)] = {vfp_single_fsub, 0}, 1162 [FOP_TO_IDX(FOP_FSUB)] = { vfp_single_fsub, 0 },
1163 [FOP_TO_IDX(FOP_FDIV)] = {vfp_single_fdiv, 0}, 1163 [FOP_TO_IDX(FOP_FDIV)] = { vfp_single_fdiv, 0 },
1164}; 1164};
1165 1165
1166#define FREG_BANK(x) ((x) & 0x18) 1166#define FREG_BANK(x) ((x) & 0x18)
@@ -1179,22 +1179,23 @@ u32 vfp_single_cpdo(u32 inst, u32 fpscr)
1179 vecstride = 1 + ((fpscr & FPSCR_STRIDE_MASK) == FPSCR_STRIDE_MASK); 1179 vecstride = 1 + ((fpscr & FPSCR_STRIDE_MASK) == FPSCR_STRIDE_MASK);
1180 1180
1181 fop = (op == FOP_EXT) ? &fops_ext[FEXT_TO_IDX(inst)] : &fops[FOP_TO_IDX(op)]; 1181 fop = (op == FOP_EXT) ? &fops_ext[FEXT_TO_IDX(inst)] : &fops[FOP_TO_IDX(op)];
1182
1182 /* 1183 /*
1183 * fcvtsd takes a dN register number as destination, not sN. 1184 * fcvtsd takes a dN register number as destination, not sN.
1184 * Technically, if bit 0 of dd is set, this is an invalid 1185 * Technically, if bit 0 of dd is set, this is an invalid
1185 * instruction. However, we ignore this for efficiency. 1186 * instruction. However, we ignore this for efficiency.
1186 * It also only operates on scalars. 1187 * It also only operates on scalars.
1187 */ 1188 */
1188 if (fop->flags & OP_SD) { 1189 if (fop->flags & OP_DD)
1189 dest = vfp_get_dd(inst); 1190 dest = vfp_get_dd(inst);
1190 } else 1191 else
1191 dest = vfp_get_sd(inst); 1192 dest = vfp_get_sd(inst);
1192 1193
1193 /* 1194 /*
1194 * If destination bank is zero, vector length is always '1'. 1195 * If destination bank is zero, vector length is always '1'.
1195 * ARM DDI0100F C5.1.3, C5.3.2. 1196 * ARM DDI0100F C5.1.3, C5.3.2.
1196 */ 1197 */
1197 if ((fop->flags & OP_SCALAR) || (FREG_BANK(dest) == 0)) 1198 if ((fop->flags & OP_SCALAR) || FREG_BANK(dest) == 0)
1198 veclen = 0; 1199 veclen = 0;
1199 else 1200 else
1200 veclen = fpscr & FPSCR_LENGTH_MASK; 1201 veclen = fpscr & FPSCR_LENGTH_MASK;
@@ -1208,16 +1209,16 @@ u32 vfp_single_cpdo(u32 inst, u32 fpscr)
1208 for (vecitr = 0; vecitr <= veclen; vecitr += 1 << FPSCR_LENGTH_BIT) { 1209 for (vecitr = 0; vecitr <= veclen; vecitr += 1 << FPSCR_LENGTH_BIT) {
1209 s32 m = vfp_get_float(sm); 1210 s32 m = vfp_get_float(sm);
1210 u32 except; 1211 u32 except;
1212 char type;
1211 1213
1212 if (op == FOP_EXT && (fop->flags & OP_SD)) 1214 type = fop->flags & OP_DD ? 'd' : 's';
1213 pr_debug("VFP: itr%d (d%u) = op[%u] (s%u=%08x)\n", 1215 if (op == FOP_EXT)
1214 vecitr >> FPSCR_LENGTH_BIT, dest, sn, sm, m); 1216 pr_debug("VFP: itr%d (%c%u) = op[%u] (s%u=%08x)\n",
1215 else if (op == FOP_EXT) 1217 vecitr >> FPSCR_LENGTH_BIT, type, dest, sn,
1216 pr_debug("VFP: itr%d (s%u) = op[%u] (s%u=%08x)\n", 1218 sm, m);
1217 vecitr >> FPSCR_LENGTH_BIT, dest, sn, sm, m);
1218 else 1219 else
1219 pr_debug("VFP: itr%d (s%u) = (s%u) op[%u] (s%u=%08x)\n", 1220 pr_debug("VFP: itr%d (%c%u) = (s%u) op[%u] (s%u=%08x)\n",
1220 vecitr >> FPSCR_LENGTH_BIT, dest, sn, 1221 vecitr >> FPSCR_LENGTH_BIT, type, dest, sn,
1221 FOP_TO_IDX(op), sm, m); 1222 FOP_TO_IDX(op), sm, m);
1222 1223
1223 except = fop->fn(dest, sn, m, fpscr); 1224 except = fop->fn(dest, sn, m, fpscr);
@@ -1227,17 +1228,9 @@ u32 vfp_single_cpdo(u32 inst, u32 fpscr)
1227 exceptions |= except; 1228 exceptions |= except;
1228 1229
1229 /* 1230 /*
1230 * This ensures that comparisons only operate on scalars;
1231 * comparisons always return with one FPSCR status bit set.
1232 */
1233 if (except & (FPSCR_N|FPSCR_Z|FPSCR_C|FPSCR_V))
1234 break;
1235
1236 /*
1237 * CHECK: It appears to be undefined whether we stop when 1231 * CHECK: It appears to be undefined whether we stop when
1238 * we encounter an exception. We continue. 1232 * we encounter an exception. We continue.
1239 */ 1233 */
1240
1241 dest = FREG_BANK(dest) + ((FREG_IDX(dest) + vecstride) & 7); 1234 dest = FREG_BANK(dest) + ((FREG_IDX(dest) + vecstride) & 7);
1242 sn = FREG_BANK(sn) + ((FREG_IDX(sn) + vecstride) & 7); 1235 sn = FREG_BANK(sn) + ((FREG_IDX(sn) + vecstride) & 7);
1243 if (FREG_BANK(sm) != 0) 1236 if (FREG_BANK(sm) != 0)