diff options
Diffstat (limited to 'arch/arm/vfp/vfpdouble.c')
-rw-r--r-- | arch/arm/vfp/vfpdouble.c | 30 |
1 files changed, 22 insertions, 8 deletions
diff --git a/arch/arm/vfp/vfpdouble.c b/arch/arm/vfp/vfpdouble.c index 009038c8113e..04bd3425b29b 100644 --- a/arch/arm/vfp/vfpdouble.c +++ b/arch/arm/vfp/vfpdouble.c | |||
@@ -465,7 +465,7 @@ static u32 vfp_double_fcvts(int sd, int unused, int dm, u32 fpscr) | |||
465 | */ | 465 | */ |
466 | if (tm & (VFP_INFINITY|VFP_NAN)) { | 466 | if (tm & (VFP_INFINITY|VFP_NAN)) { |
467 | vsd.exponent = 255; | 467 | vsd.exponent = 255; |
468 | if (tm & VFP_NAN) | 468 | if (tm == VFP_QNAN) |
469 | vsd.significand |= VFP_SINGLE_SIGNIFICAND_QNAN; | 469 | vsd.significand |= VFP_SINGLE_SIGNIFICAND_QNAN; |
470 | goto pack_nan; | 470 | goto pack_nan; |
471 | } else if (tm & VFP_ZERO) | 471 | } else if (tm & VFP_ZERO) |
@@ -1127,7 +1127,7 @@ u32 vfp_double_cpdo(u32 inst, u32 fpscr) | |||
1127 | { | 1127 | { |
1128 | u32 op = inst & FOP_MASK; | 1128 | u32 op = inst & FOP_MASK; |
1129 | u32 exceptions = 0; | 1129 | u32 exceptions = 0; |
1130 | unsigned int dd = vfp_get_dd(inst); | 1130 | unsigned int dest; |
1131 | unsigned int dn = vfp_get_dn(inst); | 1131 | unsigned int dn = vfp_get_dn(inst); |
1132 | unsigned int dm = vfp_get_dm(inst); | 1132 | unsigned int dm = vfp_get_dm(inst); |
1133 | unsigned int vecitr, veclen, vecstride; | 1133 | unsigned int vecitr, veclen, vecstride; |
@@ -1137,10 +1137,20 @@ u32 vfp_double_cpdo(u32 inst, u32 fpscr) | |||
1137 | vecstride = (1 + ((fpscr & FPSCR_STRIDE_MASK) == FPSCR_STRIDE_MASK)) * 2; | 1137 | vecstride = (1 + ((fpscr & FPSCR_STRIDE_MASK) == FPSCR_STRIDE_MASK)) * 2; |
1138 | 1138 | ||
1139 | /* | 1139 | /* |
1140 | * fcvtds takes an sN register number as destination, not dN. | ||
1141 | * It also always operates on scalars. | ||
1142 | */ | ||
1143 | if ((inst & FEXT_MASK) == FEXT_FCVT) { | ||
1144 | veclen = 0; | ||
1145 | dest = vfp_get_sd(inst); | ||
1146 | } else | ||
1147 | dest = vfp_get_dd(inst); | ||
1148 | |||
1149 | /* | ||
1140 | * If destination bank is zero, vector length is always '1'. | 1150 | * If destination bank is zero, vector length is always '1'. |
1141 | * ARM DDI0100F C5.1.3, C5.3.2. | 1151 | * ARM DDI0100F C5.1.3, C5.3.2. |
1142 | */ | 1152 | */ |
1143 | if (FREG_BANK(dd) == 0) | 1153 | if (FREG_BANK(dest) == 0) |
1144 | veclen = 0; | 1154 | veclen = 0; |
1145 | 1155 | ||
1146 | pr_debug("VFP: vecstride=%u veclen=%u\n", vecstride, | 1156 | pr_debug("VFP: vecstride=%u veclen=%u\n", vecstride, |
@@ -1153,16 +1163,20 @@ u32 vfp_double_cpdo(u32 inst, u32 fpscr) | |||
1153 | for (vecitr = 0; vecitr <= veclen; vecitr += 1 << FPSCR_LENGTH_BIT) { | 1163 | for (vecitr = 0; vecitr <= veclen; vecitr += 1 << FPSCR_LENGTH_BIT) { |
1154 | u32 except; | 1164 | u32 except; |
1155 | 1165 | ||
1156 | if (op == FOP_EXT) | 1166 | if (op == FOP_EXT && (inst & FEXT_MASK) == FEXT_FCVT) |
1167 | pr_debug("VFP: itr%d (s%u) = op[%u] (d%u)\n", | ||
1168 | vecitr >> FPSCR_LENGTH_BIT, | ||
1169 | dest, dn, dm); | ||
1170 | else if (op == FOP_EXT) | ||
1157 | pr_debug("VFP: itr%d (d%u) = op[%u] (d%u)\n", | 1171 | pr_debug("VFP: itr%d (d%u) = op[%u] (d%u)\n", |
1158 | vecitr >> FPSCR_LENGTH_BIT, | 1172 | vecitr >> FPSCR_LENGTH_BIT, |
1159 | dd, dn, dm); | 1173 | dest, dn, dm); |
1160 | else | 1174 | else |
1161 | pr_debug("VFP: itr%d (d%u) = (d%u) op[%u] (d%u)\n", | 1175 | pr_debug("VFP: itr%d (d%u) = (d%u) op[%u] (d%u)\n", |
1162 | vecitr >> FPSCR_LENGTH_BIT, | 1176 | vecitr >> FPSCR_LENGTH_BIT, |
1163 | dd, dn, FOP_TO_IDX(op), dm); | 1177 | dest, dn, FOP_TO_IDX(op), dm); |
1164 | 1178 | ||
1165 | except = fop(dd, dn, dm, fpscr); | 1179 | except = fop(dest, dn, dm, fpscr); |
1166 | pr_debug("VFP: itr%d: exceptions=%08x\n", | 1180 | pr_debug("VFP: itr%d: exceptions=%08x\n", |
1167 | vecitr >> FPSCR_LENGTH_BIT, except); | 1181 | vecitr >> FPSCR_LENGTH_BIT, except); |
1168 | 1182 | ||
@@ -1180,7 +1194,7 @@ u32 vfp_double_cpdo(u32 inst, u32 fpscr) | |||
1180 | * we encounter an exception. We continue. | 1194 | * we encounter an exception. We continue. |
1181 | */ | 1195 | */ |
1182 | 1196 | ||
1183 | dd = FREG_BANK(dd) + ((FREG_IDX(dd) + vecstride) & 6); | 1197 | dest = FREG_BANK(dest) + ((FREG_IDX(dest) + vecstride) & 6); |
1184 | dn = FREG_BANK(dn) + ((FREG_IDX(dn) + vecstride) & 6); | 1198 | dn = FREG_BANK(dn) + ((FREG_IDX(dn) + vecstride) & 6); |
1185 | if (FREG_BANK(dm) != 0) | 1199 | if (FREG_BANK(dm) != 0) |
1186 | dm = FREG_BANK(dm) + ((FREG_IDX(dm) + vecstride) & 6); | 1200 | dm = FREG_BANK(dm) + ((FREG_IDX(dm) + vecstride) & 6); |