18 files changed, 1585 insertions, 0 deletions

diff --git a/arch/arm/plat-spear/Kconfig b/arch/arm/plat-spear/Kconfig
new file mode 100644
index 000000000000..1bb3dbce8810
--- /dev/null
+++ b/arch/arm/plat-spear/Kconfig
@@ -0,0 +1,31 @@
+#
+# SPEAr Platform configuration file
+#
+
+if PLAT_SPEAR
+
+choice
+        prompt "ST SPEAr Family"
+        default ARCH_SPEAR3XX
+
+config ARCH_SPEAR3XX
+        bool "SPEAr3XX"
+        select ARM_VIC
+        select CPU_ARM926T
+        help
+          Supports for ARM's SPEAR3XX family
+
+config ARCH_SPEAR6XX
+        bool "SPEAr6XX"
+        select ARM_VIC
+        select CPU_ARM926T
+        help
+          Supports for ARM's SPEAR6XX family
+
+endchoice
+
+# Adding SPEAr machine specific configuration files
+source "arch/arm/mach-spear3xx/Kconfig"
+source "arch/arm/mach-spear6xx/Kconfig"
+
+endif
diff --git a/arch/arm/plat-spear/Makefile b/arch/arm/plat-spear/Makefile
new file mode 100644
index 000000000000..eb89540aeda9
--- /dev/null
+++ b/arch/arm/plat-spear/Makefile
@@ -0,0 +1,8 @@
+#
+# SPEAr Platform specific Makefile
+#
+
+# Common support
+obj-y   := clock.o padmux.o time.o
+
+obj-$(CONFIG_ARCH_SPEAR3XX)     += shirq.o
diff --git a/arch/arm/plat-spear/clock.c b/arch/arm/plat-spear/clock.c
new file mode 100644
index 000000000000..ee4f90e534d8
--- /dev/null
+++ b/arch/arm/plat-spear/clock.c
@@ -0,0 +1,435 @@
+/*
+ * arch/arm/plat-spear/clock.c
+ *
+ * Clock framework for SPEAr platform
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/bug.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/list.h>
+#include <linux/module.h>
+#include <linux/spinlock.h>
+#include <mach/misc_regs.h>
+#include <plat/clock.h>
+
+static DEFINE_SPINLOCK(clocks_lock);
+static LIST_HEAD(root_clks);
+
+static void propagate_rate(struct list_head *);
+
+static int generic_clk_enable(struct clk *clk)
+{
+        unsigned int val;
+
+        if (!clk->en_reg)
+                return -EFAULT;
+
+        val = readl(clk->en_reg);
+        if (unlikely(clk->flags & RESET_TO_ENABLE))
+                val &= ~(1 << clk->en_reg_bit);
+        else
+                val |= 1 << clk->en_reg_bit;
+
+        writel(val, clk->en_reg);
+
+        return 0;
+}
+
+static void generic_clk_disable(struct clk *clk)
+{
+        unsigned int val;
+
+        if (!clk->en_reg)
+                return;
+
+        val = readl(clk->en_reg);
+        if (unlikely(clk->flags & RESET_TO_ENABLE))
+                val |= 1 << clk->en_reg_bit;
+        else
+                val &= ~(1 << clk->en_reg_bit);
+
+        writel(val, clk->en_reg);
+}
+
+/* generic clk ops */
+static struct clkops generic_clkops = {
+        .enable = generic_clk_enable,
+        .disable = generic_clk_disable,
+};
+
+/*
+ * clk_enable - inform the system when the clock source should be running.
+ * @clk: clock source
+ *
+ * If the clock can not be enabled/disabled, this should return success.
+ *
+ * Returns success (0) or negative errno.
+ */
+int clk_enable(struct clk *clk)
+{
+        unsigned long flags;
+        int ret = 0;
+
+        if (!clk || IS_ERR(clk))
+                return -EFAULT;
+
+        spin_lock_irqsave(&clocks_lock, flags);
+        if (clk->usage_count == 0) {
+                if (clk->ops && clk->ops->enable)
+                        ret = clk->ops->enable(clk);
+        }
+        clk->usage_count++;
+        spin_unlock_irqrestore(&clocks_lock, flags);
+
+        return ret;
+}
+EXPORT_SYMBOL(clk_enable);
+
+/*
+ * clk_disable - inform the system when the clock source is no longer required.
+ * @clk: clock source
+ *
+ * Inform the system that a clock source is no longer required by
+ * a driver and may be shut down.
+ *
+ * Implementation detail: if the clock source is shared between
+ * multiple drivers, clk_enable() calls must be balanced by the
+ * same number of clk_disable() calls for the clock source to be
+ * disabled.
+ */
+void clk_disable(struct clk *clk)
+{
+        unsigned long flags;
+
+        if (!clk || IS_ERR(clk))
+                return;
+
+        WARN_ON(clk->usage_count == 0);
+
+        spin_lock_irqsave(&clocks_lock, flags);
+        clk->usage_count--;
+        if (clk->usage_count == 0) {
+                if (clk->ops && clk->ops->disable)
+                        clk->ops->disable(clk);
+        }
+        spin_unlock_irqrestore(&clocks_lock, flags);
+}
+EXPORT_SYMBOL(clk_disable);
+
+/**
+ * clk_get_rate - obtain the current clock rate (in Hz) for a clock source.
+ *               This is only valid once the clock source has been enabled.
+ * @clk: clock source
+ */
+unsigned long clk_get_rate(struct clk *clk)
+{
+        unsigned long flags, rate;
+
+        spin_lock_irqsave(&clocks_lock, flags);
+        rate = clk->rate;
+        spin_unlock_irqrestore(&clocks_lock, flags);
+
+        return rate;
+}
+EXPORT_SYMBOL(clk_get_rate);
+
+/**
+ * clk_set_parent - set the parent clock source for this clock
+ * @clk: clock source
+ * @parent: parent clock source
+ *
+ * Returns success (0) or negative errno.
+ */
+int clk_set_parent(struct clk *clk, struct clk *parent)
+{
+        int i, found = 0, val = 0;
+        unsigned long flags;
+
+        if (!clk || IS_ERR(clk) || !parent || IS_ERR(parent))
+                return -EFAULT;
+        if (clk->usage_count)
+                return -EBUSY;
+        if (!clk->pclk_sel)
+                return -EPERM;
+        if (clk->pclk == parent)
+                return 0;
+
+        for (i = 0; i < clk->pclk_sel->pclk_count; i++) {
+                if (clk->pclk_sel->pclk_info[i].pclk == parent) {
+                        found = 1;
+                        break;
+                }
+        }
+
+        if (!found)
+                return -EINVAL;
+
+        spin_lock_irqsave(&clocks_lock, flags);
+        /* reflect parent change in hardware */
+        val = readl(clk->pclk_sel->pclk_sel_reg);
+        val &= ~(clk->pclk_sel->pclk_sel_mask << clk->pclk_sel_shift);
+        val |= clk->pclk_sel->pclk_info[i].pclk_mask << clk->pclk_sel_shift;
+        writel(val, clk->pclk_sel->pclk_sel_reg);
+        spin_unlock_irqrestore(&clocks_lock, flags);
+
+        /* reflect parent change in software */
+        clk->recalc(clk);
+        propagate_rate(&clk->children);
+        return 0;
+}
+EXPORT_SYMBOL(clk_set_parent);
+
+/* registers clock in platform clock framework */
+void clk_register(struct clk_lookup *cl)
+{
+        struct clk *clk = cl->clk;
+        unsigned long flags;
+
+        if (!clk || IS_ERR(clk))
+                return;
+
+        spin_lock_irqsave(&clocks_lock, flags);
+
+        INIT_LIST_HEAD(&clk->children);
+        if (clk->flags & ALWAYS_ENABLED)
+                clk->ops = NULL;
+        else if (!clk->ops)
+                clk->ops = &generic_clkops;
+
+        /* root clock don't have any parents */
+        if (!clk->pclk && !clk->pclk_sel) {
+                list_add(&clk->sibling, &root_clks);
+                /* add clocks with only one parent to parent's children list */
+        } else if (clk->pclk && !clk->pclk_sel) {
+                list_add(&clk->sibling, &clk->pclk->children);
+        } else {
+                /* add clocks with > 1 parent to 1st parent's children list */
+                list_add(&clk->sibling,
+                         &clk->pclk_sel->pclk_info[0].pclk->children);
+        }
+        spin_unlock_irqrestore(&clocks_lock, flags);
+
+        /* add clock to arm clockdev framework */
+        clkdev_add(cl);
+}
+
+/**
+ * propagate_rate - recalculate and propagate all clocks in list head
+ *
+ * Recalculates all root clocks in list head, which if the clock's .recalc is
+ * set correctly, should also propagate their rates.
+ */
+static void propagate_rate(struct list_head *lhead)
+{
+        struct clk *clkp, *_temp;
+
+        list_for_each_entry_safe(clkp, _temp, lhead, sibling) {
+                if (clkp->recalc)
+                        clkp->recalc(clkp);
+                propagate_rate(&clkp->children);
+        }
+}
+
+/* returns current programmed clocks clock info structure */
+static struct pclk_info *pclk_info_get(struct clk *clk)
+{
+        unsigned int mask, i;
+        unsigned long flags;
+        struct pclk_info *info = NULL;
+
+        spin_lock_irqsave(&clocks_lock, flags);
+        mask = (readl(clk->pclk_sel->pclk_sel_reg) >> clk->pclk_sel_shift)
+                        & clk->pclk_sel->pclk_sel_mask;
+
+        for (i = 0; i < clk->pclk_sel->pclk_count; i++) {
+                if (clk->pclk_sel->pclk_info[i].pclk_mask == mask)
+                        info = &clk->pclk_sel->pclk_info[i];
+        }
+        spin_unlock_irqrestore(&clocks_lock, flags);
+
+        return info;
+}
+
+/*
+ * Set pclk as cclk's parent and add clock sibling node to current parents
+ * children list
+ */
+static void change_parent(struct clk *cclk, struct clk *pclk)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&clocks_lock, flags);
+        list_del(&cclk->sibling);
+        list_add(&cclk->sibling, &pclk->children);
+
+        cclk->pclk = pclk;
+        spin_unlock_irqrestore(&clocks_lock, flags);
+}
+
+/*
+ * calculates current programmed rate of pll1
+ *
+ * In normal mode
+ * rate = (2 * M[15:8] * Fin)/(N * 2^P)
+ *
+ * In Dithered mode
+ * rate = (2 * M[15:0] * Fin)/(256 * N * 2^P)
+ */
+void pll1_clk_recalc(struct clk *clk)
+{
+        struct pll_clk_config *config = clk->private_data;
+        unsigned int num = 2, den = 0, val, mode = 0;
+        unsigned long flags;
+
+        spin_lock_irqsave(&clocks_lock, flags);
+        mode = (readl(config->mode_reg) >> PLL_MODE_SHIFT) &
+                PLL_MODE_MASK;
+
+        val = readl(config->cfg_reg);
+        /* calculate denominator */
+        den = (val >> PLL_DIV_P_SHIFT) & PLL_DIV_P_MASK;
+        den = 1 << den;
+        den *= (val >> PLL_DIV_N_SHIFT) & PLL_DIV_N_MASK;
+
+        /* calculate numerator & denominator */
+        if (!mode) {
+                /* Normal mode */
+                num *= (val >> PLL_NORM_FDBK_M_SHIFT) & PLL_NORM_FDBK_M_MASK;
+        } else {
+                /* Dithered mode */
+                num *= (val >> PLL_DITH_FDBK_M_SHIFT) & PLL_DITH_FDBK_M_MASK;
+                den *= 256;
+        }
+
+        clk->rate = (((clk->pclk->rate/10000) * num) / den) * 10000;
+        spin_unlock_irqrestore(&clocks_lock, flags);
+}
+
+/* calculates current programmed rate of ahb or apb bus */
+void bus_clk_recalc(struct clk *clk)
+{
+        struct bus_clk_config *config = clk->private_data;
+        unsigned int div;
+        unsigned long flags;
+
+        spin_lock_irqsave(&clocks_lock, flags);
+        div = ((readl(config->reg) >> config->shift) & config->mask) + 1;
+        clk->rate = (unsigned long)clk->pclk->rate / div;
+        spin_unlock_irqrestore(&clocks_lock, flags);
+}
+
+/*
+ * calculates current programmed rate of auxiliary synthesizers
+ * used by: UART, FIRDA
+ *
+ * Fout from synthesizer can be given from two equations:
+ * Fout1 = (Fin * X/Y)/2
+ * Fout2 = Fin * X/Y
+ *
+ * Selection of eqn 1 or 2 is programmed in register
+ */
+void aux_clk_recalc(struct clk *clk)
+{
+        struct aux_clk_config *config = clk->private_data;
+        struct pclk_info *pclk_info = NULL;
+        unsigned int num = 1, den = 1, val, eqn;
+        unsigned long flags;
+
+        /* get current programmed parent */
+        pclk_info = pclk_info_get(clk);
+        if (!pclk_info) {
+                spin_lock_irqsave(&clocks_lock, flags);
+                clk->pclk = NULL;
+                clk->rate = 0;
+                spin_unlock_irqrestore(&clocks_lock, flags);
+                return;
+        }
+
+        change_parent(clk, pclk_info->pclk);
+
+        spin_lock_irqsave(&clocks_lock, flags);
+        if (pclk_info->scalable) {
+                val = readl(config->synth_reg);
+
+                eqn = (val >> AUX_EQ_SEL_SHIFT) & AUX_EQ_SEL_MASK;
+                if (eqn == AUX_EQ1_SEL)
+                        den *= 2;
+
+                /* calculate numerator */
+                num = (val >> AUX_XSCALE_SHIFT) & AUX_XSCALE_MASK;
+
+                /* calculate denominator */
+                den *= (val >> AUX_YSCALE_SHIFT) & AUX_YSCALE_MASK;
+                val = (((clk->pclk->rate/10000) * num) / den) * 10000;
+        } else
+                val = clk->pclk->rate;
+
+        clk->rate = val;
+        spin_unlock_irqrestore(&clocks_lock, flags);
+}
+
+/*
+ * calculates current programmed rate of gpt synthesizers
+ * Fout from synthesizer can be given from below equations:
+ * Fout= Fin/((2 ^ (N+1)) * (M+1))
+ */
+void gpt_clk_recalc(struct clk *clk)
+{
+        struct aux_clk_config *config = clk->private_data;
+        struct pclk_info *pclk_info = NULL;
+        unsigned int div = 1, val;
+        unsigned long flags;
+
+        pclk_info = pclk_info_get(clk);
+        if (!pclk_info) {
+                spin_lock_irqsave(&clocks_lock, flags);
+                clk->pclk = NULL;
+                clk->rate = 0;
+                spin_unlock_irqrestore(&clocks_lock, flags);
+                return;
+        }
+
+        change_parent(clk, pclk_info->pclk);
+
+        spin_lock_irqsave(&clocks_lock, flags);
+        if (pclk_info->scalable) {
+                val = readl(config->synth_reg);
+                div += (val >> GPT_MSCALE_SHIFT) & GPT_MSCALE_MASK;
+                div *= 1 << (((val >> GPT_NSCALE_SHIFT) & GPT_NSCALE_MASK) + 1);
+        }
+
+        clk->rate = (unsigned long)clk->pclk->rate / div;
+        spin_unlock_irqrestore(&clocks_lock, flags);
+}
+
+/*
+ * Used for clocks that always have same value as the parent clock divided by a
+ * fixed divisor
+ */
+void follow_parent(struct clk *clk)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&clocks_lock, flags);
+        clk->rate = clk->pclk->rate;
+        spin_unlock_irqrestore(&clocks_lock, flags);
+}
+
+/**
+ * recalc_root_clocks - recalculate and propagate all root clocks
+ *
+ * Recalculates all root clocks (clocks with no parent), which if the
+ * clock's .recalc is set correctly, should also propagate their rates.
+ */
+void recalc_root_clocks(void)
+{
+        propagate_rate(&root_clks);
+}
diff --git a/arch/arm/plat-spear/include/plat/clkdev.h b/arch/arm/plat-spear/include/plat/clkdev.h
new file mode 100644
index 000000000000..a2d0112fcaf7
--- /dev/null
+++ b/arch/arm/plat-spear/include/plat/clkdev.h
@@ -0,0 +1,20 @@
+/*
+ * arch/arm/plat-spear/include/plat/clkdev.h
+ *
+ * Clock Dev framework definitions for SPEAr platform
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __PLAT_CLKDEV_H
+#define __PLAT_CLKDEV_H
+
+#define __clk_get(clk) ({ 1; })
+#define __clk_put(clk) do { } while (0)
+
+#endif /* __PLAT_CLKDEV_H */
diff --git a/arch/arm/plat-spear/include/plat/clock.h b/arch/arm/plat-spear/include/plat/clock.h
new file mode 100644
index 000000000000..298bafc0a52f
--- /dev/null
+++ b/arch/arm/plat-spear/include/plat/clock.h
@@ -0,0 +1,126 @@
+/*
+ * arch/arm/plat-spear/include/plat/clock.h
+ *
+ * Clock framework definitions for SPEAr platform
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __PLAT_CLOCK_H
+#define __PLAT_CLOCK_H
+
+#include <linux/list.h>
+#include <asm/clkdev.h>
+#include <linux/types.h>
+
+/* clk structure flags */
+#define ALWAYS_ENABLED          (1 << 0) /* clock always enabled */
+#define RESET_TO_ENABLE         (1 << 1) /* reset register bit to enable clk */
+
+/**
+ * struct clkops - clock operations
+ * @enable: pointer to clock enable function
+ * @disable: pointer to clock disable function
+ */
+struct clkops {
+        int (*enable) (struct clk *);
+        void (*disable) (struct clk *);
+};
+
+/**
+ * struct pclk_info - parents info
+ * @pclk: pointer to parent clk
+ * @pclk_mask: value to be written for selecting this parent
+ * @scalable: Is parent scalable (1 - YES, 0 - NO)
+ */
+struct pclk_info {
+        struct clk *pclk;
+        u8 pclk_mask;
+        u8 scalable;
+};
+
+/**
+ * struct pclk_sel - parents selection configuration
+ * @pclk_info: pointer to array of parent clock info
+ * @pclk_count: number of parents
+ * @pclk_sel_reg: register for selecting a parent
+ * @pclk_sel_mask: mask for selecting parent (can be used to clear bits also)
+ */
+struct pclk_sel {
+        struct pclk_info *pclk_info;
+        u8 pclk_count;
+        unsigned int *pclk_sel_reg;
+        unsigned int pclk_sel_mask;
+};
+
+/**
+ * struct clk - clock structure
+ * @usage_count: num of users who enabled this clock
+ * @flags: flags for clock properties
+ * @rate: programmed clock rate in Hz
+ * @en_reg: clk enable/disable reg
+ * @en_reg_bit: clk enable/disable bit
+ * @ops: clk enable/disable ops - generic_clkops selected if NULL
+ * @recalc: pointer to clock rate recalculate function
+ * @pclk: current parent clk
+ * @pclk_sel: pointer to parent selection structure
+ * @pclk_sel_shift: register shift for selecting parent of this clock
+ * @children: list for childrens or this clock
+ * @sibling: node for list of clocks having same parents
+ * @private_data: clock specific private data
+ */
+struct clk {
+        unsigned int usage_count;
+        unsigned int flags;
+        unsigned long rate;
+        unsigned int *en_reg;
+        u8 en_reg_bit;
+        const struct clkops *ops;
+        void (*recalc) (struct clk *);
+
+        struct clk *pclk;
+        struct pclk_sel *pclk_sel;
+        unsigned int pclk_sel_shift;
+
+        struct list_head children;
+        struct list_head sibling;
+        void *private_data;
+};
+
+/* pll configuration structure */
+struct pll_clk_config {
+        unsigned int *mode_reg;
+        unsigned int *cfg_reg;
+};
+
+/* ahb and apb bus configuration structure */
+struct bus_clk_config {
+        unsigned int *reg;
+        unsigned int mask;
+        unsigned int shift;
+};
+
+/*
+ * Aux clk configuration structure: applicable to GPT, UART and FIRDA
+ */
+struct aux_clk_config {
+        unsigned int *synth_reg;
+};
+
+/* platform specific clock functions */
+void clk_register(struct clk_lookup *cl);
+void recalc_root_clocks(void);
+
+/* clock recalc functions */
+void follow_parent(struct clk *clk);
+void pll1_clk_recalc(struct clk *clk);
+void bus_clk_recalc(struct clk *clk);
+void gpt_clk_recalc(struct clk *clk);
+void aux_clk_recalc(struct clk *clk);
+
+#endif /* __PLAT_CLOCK_H */
diff --git a/arch/arm/plat-spear/include/plat/debug-macro.S b/arch/arm/plat-spear/include/plat/debug-macro.S
new file mode 100644
index 000000000000..1670734b7e51
--- /dev/null
+++ b/arch/arm/plat-spear/include/plat/debug-macro.S
@@ -0,0 +1,38 @@
+/*
+ * arch/arm/plat-spear/include/plat/debug-macro.S
+ *
+ * Debugging macro include header for spear platform
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/amba/serial.h>
+#include <mach/spear.h>
+
+                .macro  addruart, rx
+                mrc     p15, 0, \rx, c1, c0
+                tst     \rx, #1                                 @ MMU enabled?
+                moveq   \rx, =SPEAR_DBG_UART_BASE               @ Physical base
+                movne   \rx, =VA_SPEAR_DBG_UART_BASE            @ Virtual base
+                .endm
+
+                .macro  senduart, rd, rx
+                strb    \rd, [\rx, #UART01x_DR]                 @ ASC_TX_BUFFER
+                .endm
+
+                .macro  waituart, rd, rx
+1001:           ldr     \rd, [\rx, #UART01x_FR]                 @ FLAG REGISTER
+                tst     \rd, #UART01x_FR_TXFF                   @ TX_FULL
+                bne     1001b
+                .endm
+
+                .macro  busyuart, rd, rx
+1002:           ldr     \rd, [\rx, #UART01x_FR]                 @ FLAG REGISTER
+                tst     \rd, #UART011_FR_TXFE                   @ TX_EMPTY
+                beq     1002b
+                .endm
diff --git a/arch/arm/plat-spear/include/plat/gpio.h b/arch/arm/plat-spear/include/plat/gpio.h
new file mode 100644
index 000000000000..b857c91257dd
--- /dev/null
+++ b/arch/arm/plat-spear/include/plat/gpio.h
@@ -0,0 +1,24 @@
+/*
+ * arch/arm/plat-spear/include/plat/gpio.h
+ *
+ * GPIO macros for SPEAr platform
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __PLAT_GPIO_H
+#define __PLAT_GPIO_H
+
+#include <asm-generic/gpio.h>
+
+#define gpio_get_value  __gpio_get_value
+#define gpio_set_value  __gpio_set_value
+#define gpio_cansleep   __gpio_cansleep
+#define gpio_to_irq     __gpio_to_irq
+
+#endif /* __PLAT_GPIO_H */
diff --git a/arch/arm/plat-spear/include/plat/io.h b/arch/arm/plat-spear/include/plat/io.h
new file mode 100644
index 000000000000..4d4ba822b3eb
--- /dev/null
+++ b/arch/arm/plat-spear/include/plat/io.h
@@ -0,0 +1,22 @@
+/*
+ * arch/arm/plat-spear/include/plat/io.h
+ *
+ * IO definitions for SPEAr platform
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __PLAT_IO_H
+#define __PLAT_IO_H
+
+#define IO_SPACE_LIMIT          0xFFFFFFFF
+
+#define __io(a)                 __typesafe_io(a)
+#define __mem_pci(a)            (a)
+
+#endif /* __PLAT_IO_H */
diff --git a/arch/arm/plat-spear/include/plat/memory.h b/arch/arm/plat-spear/include/plat/memory.h
new file mode 100644
index 000000000000..27a4aba77343
--- /dev/null
+++ b/arch/arm/plat-spear/include/plat/memory.h
@@ -0,0 +1,20 @@
+/*
+ * arch/arm/plat-spear/include/plat/memory.h
+ *
+ * Memory map for SPEAr platform
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __PLAT_MEMORY_H
+#define __PLAT_MEMORY_H
+
+/* Physical DRAM offset */
+#define PHYS_OFFSET             UL(0x00000000)
+
+#endif /* __PLAT_MEMORY_H */
diff --git a/arch/arm/plat-spear/include/plat/padmux.h b/arch/arm/plat-spear/include/plat/padmux.h
new file mode 100644
index 000000000000..877f3adcf610
--- /dev/null
+++ b/arch/arm/plat-spear/include/plat/padmux.h
@@ -0,0 +1,92 @@
+/*
+ * arch/arm/plat-spear/include/plat/padmux.h
+ *
+ * SPEAr platform specific gpio pads muxing file
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __PLAT_PADMUX_H
+#define __PLAT_PADMUX_H
+
+#include <linux/types.h>
+
+/*
+ * struct pmx_reg: configuration structure for mode reg and mux reg
+ *
+ * offset: offset of mode reg
+ * mask: mask of mode reg
+ */
+struct pmx_reg {
+        u32 offset;
+        u32 mask;
+};
+
+/*
+ * struct pmx_dev_mode: configuration structure every group of modes of a device
+ *
+ * ids: all modes for this configuration
+ * mask: mask for supported mode
+ */
+struct pmx_dev_mode {
+        u32 ids;
+        u32 mask;
+};
+
+/*
+ * struct pmx_mode: mode definition structure
+ *
+ * name: mode name
+ * mask: mode mask
+ */
+struct pmx_mode {
+        char *name;
+        u32 id;
+        u32 mask;
+};
+
+/*
+ * struct pmx_dev: device definition structure
+ *
+ * name: device name
+ * modes: device configuration array for different modes supported
+ * mode_count: size of modes array
+ * is_active: is peripheral active/enabled
+ * enb_on_reset: if 1, mask bits to be cleared in reg otherwise to be set in reg
+ */
+struct pmx_dev {
+        char *name;
+        struct pmx_dev_mode *modes;
+        u8 mode_count;
+        bool is_active;
+        bool enb_on_reset;
+};
+
+/*
+ * struct pmx_driver: driver definition structure
+ *
+ * mode: mode to be set
+ * devs: array of pointer to pmx devices
+ * devs_count: ARRAY_SIZE of devs
+ * base: base address of soc config registers
+ * mode_reg: structure of mode config register
+ * mux_reg: structure of device mux config register
+ */
+struct pmx_driver {
+        struct pmx_mode *mode;
+        struct pmx_dev **devs;
+        u8 devs_count;
+        u32 *base;
+        struct pmx_reg mode_reg;
+        struct pmx_reg mux_reg;
+};
+
+/* pmx functions */
+int pmx_register(struct pmx_driver *driver);
+
+#endif /* __PLAT_PADMUX_H */
diff --git a/arch/arm/plat-spear/include/plat/shirq.h b/arch/arm/plat-spear/include/plat/shirq.h
new file mode 100644
index 000000000000..03ed8b585dcf
--- /dev/null
+++ b/arch/arm/plat-spear/include/plat/shirq.h
@@ -0,0 +1,73 @@
+/*
+ * arch/arm/plat-spear/include/plat/shirq.h
+ *
+ * SPEAr platform shared irq layer header file
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __PLAT_SHIRQ_H
+#define __PLAT_SHIRQ_H
+
+#include <linux/irq.h>
+#include <linux/types.h>
+
+/*
+ * struct shirq_dev_config: shared irq device configuration
+ *
+ * virq: virtual irq number of device
+ * enb_mask: enable mask of device
+ * status_mask: status mask of device
+ * clear_mask: clear mask of device
+ */
+struct shirq_dev_config {
+        u32 virq;
+        u32 enb_mask;
+        u32 status_mask;
+        u32 clear_mask;
+};
+
+/*
+ * struct shirq_regs: shared irq register configuration
+ *
+ * base: base address of shared irq register
+ * enb_reg: enable register offset
+ * reset_to_enb: val 1 indicates, we need to clear bit for enabling interrupt
+ * status_reg: status register offset
+ * status_reg_mask: status register valid mask
+ * clear_reg: clear register offset
+ * reset_to_clear: val 1 indicates, we need to clear bit for clearing interrupt
+ */
+struct shirq_regs {
+        void __iomem *base;
+        u32 enb_reg;
+        u32 reset_to_enb;
+        u32 status_reg;
+        u32 status_reg_mask;
+        u32 clear_reg;
+        u32 reset_to_clear;
+};
+
+/*
+ * struct spear_shirq: shared irq structure
+ *
+ * irq: hardware irq number
+ * dev_config: array of device config structures which are using "irq" line
+ * dev_count: size of dev_config array
+ * regs: register configuration for shared irq block
+ */
+struct spear_shirq {
+        u32 irq;
+        struct shirq_dev_config *dev_config;
+        u32 dev_count;
+        struct shirq_regs regs;
+};
+
+int spear_shirq_register(struct spear_shirq *shirq);
+
+#endif /* __PLAT_SHIRQ_H */
diff --git a/arch/arm/plat-spear/include/plat/system.h b/arch/arm/plat-spear/include/plat/system.h
new file mode 100644
index 000000000000..55a4e405d578
--- /dev/null
+++ b/arch/arm/plat-spear/include/plat/system.h
@@ -0,0 +1,41 @@
+/*
+ * arch/arm/plat-spear/include/plat/system.h
+ *
+ * SPEAr platform specific architecture functions
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __PLAT_SYSTEM_H
+#define __PLAT_SYSTEM_H
+
+#include <asm/hardware/sp810.h>
+#include <linux/io.h>
+#include <mach/spear.h>
+
+static inline void arch_idle(void)
+{
+        /*
+         * This should do all the clock switching
+         * and wait for interrupt tricks
+         */
+        cpu_do_idle();
+}
+
+static inline void arch_reset(char mode, const char *cmd)
+{
+        if (mode == 's') {
+                /* software reset, Jump into ROM at address 0 */
+                cpu_reset(0);
+        } else {
+                /* hardware reset, Use on-chip reset capability */
+                sysctl_soft_reset((void __iomem *)VA_SPEAR_SYS_CTRL_BASE);
+        }
+}
+
+#endif /* __PLAT_SYSTEM_H */
diff --git a/arch/arm/plat-spear/include/plat/timex.h b/arch/arm/plat-spear/include/plat/timex.h
new file mode 100644
index 000000000000..914d09dd50fd
--- /dev/null
+++ b/arch/arm/plat-spear/include/plat/timex.h
@@ -0,0 +1,19 @@
+/*
+ * arch/arm/plat-spear/include/plat/timex.h
+ *
+ * SPEAr platform specific timex definitions
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __PLAT_TIMEX_H
+#define __PLAT_TIMEX_H
+
+#define CLOCK_TICK_RATE                 48000000
+
+#endif /* __PLAT_TIMEX_H */
diff --git a/arch/arm/plat-spear/include/plat/uncompress.h b/arch/arm/plat-spear/include/plat/uncompress.h
new file mode 100644
index 000000000000..99ba6789cc97
--- /dev/null
+++ b/arch/arm/plat-spear/include/plat/uncompress.h
@@ -0,0 +1,43 @@
+/*
+ * arch/arm/plat-spear/include/plat/uncompress.h
+ *
+ * Serial port stubs for kernel decompress status messages
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/io.h>
+#include <linux/amba/serial.h>
+#include <mach/spear.h>
+
+#ifndef __PLAT_UNCOMPRESS_H
+#define __PLAT_UNCOMPRESS_H
+/*
+ * This does not append a newline
+ */
+static inline void putc(int c)
+{
+        void __iomem *base = (void __iomem *)SPEAR_DBG_UART_BASE;
+
+        while (readl(base + UART01x_FR) & UART01x_FR_TXFF)
+                barrier();
+
+        writel(c, base + UART01x_DR);
+}
+
+static inline void flush(void)
+{
+}
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
+
+#endif /* __PLAT_UNCOMPRESS_H */
diff --git a/arch/arm/plat-spear/include/plat/vmalloc.h b/arch/arm/plat-spear/include/plat/vmalloc.h
new file mode 100644
index 000000000000..09e9372aea21
--- /dev/null
+++ b/arch/arm/plat-spear/include/plat/vmalloc.h
@@ -0,0 +1,19 @@
+/*
+ * arch/arm/plat-spear/include/plat/vmalloc.h
+ *
+ * Defining Vmalloc area for SPEAr platform
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __PLAT_VMALLOC_H
+#define __PLAT_VMALLOC_H
+
+#define VMALLOC_END             0xF0000000
+
+#endif /* __PLAT_VMALLOC_H */
diff --git a/arch/arm/plat-spear/padmux.c b/arch/arm/plat-spear/padmux.c
new file mode 100644
index 000000000000..d2aab3adcdeb
--- /dev/null
+++ b/arch/arm/plat-spear/padmux.c
@@ -0,0 +1,164 @@
+/*
+ * arch/arm/plat-spear/include/plat/padmux.c
+ *
+ * SPEAr platform specific gpio pads muxing source file
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <plat/padmux.h>
+
+/*
+ * struct pmx: pmx definition structure
+ *
+ * base: base address of configuration registers
+ * mode_reg: mode configurations
+ * mux_reg: muxing configurations
+ * active_mode: pointer to current active mode
+ */
+struct pmx {
+        u32 base;
+        struct pmx_reg mode_reg;
+        struct pmx_reg mux_reg;
+        struct pmx_mode *active_mode;
+};
+
+static struct pmx *pmx;
+
+/**
+ * pmx_mode_set - Enables an multiplexing mode
+ * @mode - pointer to pmx mode
+ *
+ * It will set mode of operation in hardware.
+ * Returns -ve on Err otherwise 0
+ */
+static int pmx_mode_set(struct pmx_mode *mode)
+{
+        u32 val;
+
+        if (!mode->name)
+                return -EFAULT;
+
+        pmx->active_mode = mode;
+
+        val = readl(pmx->base + pmx->mode_reg.offset);
+        val &= ~pmx->mode_reg.mask;
+        val |= mode->mask & pmx->mode_reg.mask;
+        writel(val, pmx->base + pmx->mode_reg.offset);
+
+        return 0;
+}
+
+/**
+ * pmx_devs_enable - Enables list of devices
+ * @devs - pointer to pmx device array
+ * @count - number of devices to enable
+ *
+ * It will enable pads for all required peripherals once and only once.
+ * If peripheral is not supported by current mode then request is rejected.
+ * Conflicts between peripherals are not handled and peripherals will be
+ * enabled in the order they are present in pmx_dev array.
+ * In case of conflicts last peripheral enalbed will be present.
+ * Returns -ve on Err otherwise 0
+ */
+static int pmx_devs_enable(struct pmx_dev **devs, u8 count)
+{
+        u32 val, i, mask;
+
+        if (!count)
+                return -EINVAL;
+
+        val = readl(pmx->base + pmx->mux_reg.offset);
+        for (i = 0; i < count; i++) {
+                u8 j = 0;
+
+                if (!devs[i]->name || !devs[i]->modes) {
+                        printk(KERN_ERR "padmux: dev name or modes is null\n");
+                        continue;
+                }
+                /* check if peripheral exists in active mode */
+                if (pmx->active_mode) {
+                        bool found = false;
+                        for (j = 0; j < devs[i]->mode_count; j++) {
+                                if (devs[i]->modes[j].ids &
+                                                pmx->active_mode->id) {
+                                        found = true;
+                                        break;
+                                }
+                        }
+                        if (found == false) {
+                                printk(KERN_ERR "%s device not available in %s"\
+                                                "mode\n", devs[i]->name,
+                                                pmx->active_mode->name);
+                                continue;
+                        }
+                }
+
+                /* enable peripheral */
+                mask = devs[i]->modes[j].mask & pmx->mux_reg.mask;
+                if (devs[i]->enb_on_reset)
+                        val &= ~mask;
+                else
+                        val |= mask;
+
+                devs[i]->is_active = true;
+        }
+        writel(val, pmx->base + pmx->mux_reg.offset);
+        kfree(pmx);
+
+        /* this will ensure that multiplexing can't be changed now */
+        pmx = (struct pmx *)-1;
+
+        return 0;
+}
+
+/**
+ * pmx_register - registers a platform requesting pad mux feature
+ * @driver - pointer to driver structure containing driver specific parameters
+ *
+ * Also this must be called only once. This will allocate memory for pmx
+ * structure, will call pmx_mode_set, will call pmx_devs_enable.
+ * Returns -ve on Err otherwise 0
+ */
+int pmx_register(struct pmx_driver *driver)
+{
+        int ret = 0;
+
+        if (pmx)
+                return -EPERM;
+        if (!driver->base || !driver->devs)
+                return -EFAULT;
+
+        pmx = kzalloc(sizeof(*pmx), GFP_KERNEL);
+        if (!pmx)
+                return -ENOMEM;
+
+        pmx->base = (u32)driver->base;
+        pmx->mode_reg.offset = driver->mode_reg.offset;
+        pmx->mode_reg.mask = driver->mode_reg.mask;
+        pmx->mux_reg.offset = driver->mux_reg.offset;
+        pmx->mux_reg.mask = driver->mux_reg.mask;
+
+        /* choose mode to enable */
+        if (driver->mode) {
+                ret = pmx_mode_set(driver->mode);
+                if (ret)
+                        goto pmx_fail;
+        }
+        ret = pmx_devs_enable(driver->devs, driver->devs_count);
+        if (ret)
+                goto pmx_fail;
+
+        return 0;
+
+pmx_fail:
+        return ret;
+}
diff --git a/arch/arm/plat-spear/shirq.c b/arch/arm/plat-spear/shirq.c
new file mode 100644
index 000000000000..2172d6946aea
--- /dev/null
+++ b/arch/arm/plat-spear/shirq.c
@@ -0,0 +1,118 @@
+/*
+ * arch/arm/plat-spear/shirq.c
+ *
+ * SPEAr platform shared irq layer source file
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/spinlock.h>
+#include <plat/shirq.h>
+
+struct spear_shirq *shirq;
+static DEFINE_SPINLOCK(lock);
+
+static void shirq_irq_mask(unsigned irq)
+{
+        struct spear_shirq *shirq = get_irq_chip_data(irq);
+        u32 val, id = irq - shirq->dev_config[0].virq;
+        unsigned long flags;
+
+        if ((shirq->regs.enb_reg == -1) || shirq->dev_config[id].enb_mask == -1)
+                return;
+
+        spin_lock_irqsave(&lock, flags);
+        val = readl(shirq->regs.base + shirq->regs.enb_reg);
+        if (shirq->regs.reset_to_enb)
+                val |= shirq->dev_config[id].enb_mask;
+        else
+                val &= ~(shirq->dev_config[id].enb_mask);
+        writel(val, shirq->regs.base + shirq->regs.enb_reg);
+        spin_unlock_irqrestore(&lock, flags);
+}
+
+static void shirq_irq_unmask(unsigned irq)
+{
+        struct spear_shirq *shirq = get_irq_chip_data(irq);
+        u32 val, id = irq - shirq->dev_config[0].virq;
+        unsigned long flags;
+
+        if ((shirq->regs.enb_reg == -1) || shirq->dev_config[id].enb_mask == -1)
+                return;
+
+        spin_lock_irqsave(&lock, flags);
+        val = readl(shirq->regs.base + shirq->regs.enb_reg);
+        if (shirq->regs.reset_to_enb)
+                val &= ~(shirq->dev_config[id].enb_mask);
+        else
+                val |= shirq->dev_config[id].enb_mask;
+        writel(val, shirq->regs.base + shirq->regs.enb_reg);
+        spin_unlock_irqrestore(&lock, flags);
+}
+
+static struct irq_chip shirq_chip = {
+        .name           = "spear_shirq",
+        .ack            = shirq_irq_mask,
+        .mask           = shirq_irq_mask,
+        .unmask         = shirq_irq_unmask,
+};
+
+static void shirq_handler(unsigned irq, struct irq_desc *desc)
+{
+        u32 i, val, mask;
+        struct spear_shirq *shirq = get_irq_data(irq);
+
+        desc->chip->ack(irq);
+        while ((val = readl(shirq->regs.base + shirq->regs.status_reg) &
+                                shirq->regs.status_reg_mask)) {
+                for (i = 0; (i < shirq->dev_count) && val; i++) {
+                        if (!(shirq->dev_config[i].status_mask & val))
+                                continue;
+
+                        generic_handle_irq(shirq->dev_config[i].virq);
+
+                        /* clear interrupt */
+                        val &= ~shirq->dev_config[i].status_mask;
+                        if ((shirq->regs.clear_reg == -1) ||
+                                        shirq->dev_config[i].clear_mask == -1)
+                                continue;
+                        mask = readl(shirq->regs.base + shirq->regs.clear_reg);
+                        if (shirq->regs.reset_to_clear)
+                                mask &= ~shirq->dev_config[i].clear_mask;
+                        else
+                                mask |= shirq->dev_config[i].clear_mask;
+                        writel(mask, shirq->regs.base + shirq->regs.clear_reg);
+                }
+        }
+        desc->chip->unmask(irq);
+}
+
+int spear_shirq_register(struct spear_shirq *shirq)
+{
+        int i;
+
+        if (!shirq || !shirq->dev_config || !shirq->regs.base)
+                return -EFAULT;
+
+        if (!shirq->dev_count)
+                return -EINVAL;
+
+        set_irq_chained_handler(shirq->irq, shirq_handler);
+        for (i = 0; i < shirq->dev_count; i++) {
+                set_irq_chip(shirq->dev_config[i].virq, &shirq_chip);
+                set_irq_handler(shirq->dev_config[i].virq, handle_simple_irq);
+                set_irq_flags(shirq->dev_config[i].virq, IRQF_VALID);
+                set_irq_chip_data(shirq->dev_config[i].virq, shirq);
+        }
+
+        set_irq_data(shirq->irq, shirq);
+        return 0;
+}
diff --git a/arch/arm/plat-spear/time.c b/arch/arm/plat-spear/time.c
new file mode 100644
index 000000000000..a1025d38f383
--- /dev/null
+++ b/arch/arm/plat-spear/time.c
@@ -0,0 +1,292 @@
+/*
+ * arch/arm/plat-spear/time.c
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Shiraz Hashim<shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/clk.h>
+#include <linux/clockchips.h>
+#include <linux/clocksource.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/time.h>
+#include <linux/irq.h>
+#include <asm/mach/time.h>
+#include <mach/irqs.h>
+#include <mach/hardware.h>
+#include <mach/spear.h>
+#include <mach/generic.h>
+
+/*
+ * We would use TIMER0 and TIMER1 as clockevent and clocksource.
+ * Timer0 and Timer1 both belong to same gpt block in cpu subbsystem. Further
+ * they share same functional clock. Any change in one's functional clock will
+ * also affect other timer.
+ */
+
+#define CLKEVT  0       /* gpt0, channel0 as clockevent */
+#define CLKSRC  1       /* gpt0, channel1 as clocksource */
+
+/* Register offsets, x is channel number */
+#define CR(x)           ((x) * 0x80 + 0x80)
+#define IR(x)           ((x) * 0x80 + 0x84)
+#define LOAD(x)         ((x) * 0x80 + 0x88)
+#define COUNT(x)        ((x) * 0x80 + 0x8C)
+
+/* Reg bit definitions */
+#define CTRL_INT_ENABLE         0x0100
+#define CTRL_ENABLE             0x0020
+#define CTRL_ONE_SHOT           0x0010
+
+#define CTRL_PRESCALER1         0x0
+#define CTRL_PRESCALER2         0x1
+#define CTRL_PRESCALER4         0x2
+#define CTRL_PRESCALER8         0x3
+#define CTRL_PRESCALER16        0x4
+#define CTRL_PRESCALER32        0x5
+#define CTRL_PRESCALER64        0x6
+#define CTRL_PRESCALER128       0x7
+#define CTRL_PRESCALER256       0x8
+
+#define INT_STATUS              0x1
+
+static __iomem void *gpt_base;
+static struct clk *gpt_clk;
+
+static void clockevent_set_mode(enum clock_event_mode mode,
+                                struct clock_event_device *clk_event_dev);
+static int clockevent_next_event(unsigned long evt,
+                                 struct clock_event_device *clk_event_dev);
+
+/*
+ * Following clocksource_set_clock and clockevent_set_clock picked
+ * from arch/mips/kernel/time.c
+ */
+
+void __init clocksource_set_clock(struct clocksource *cs, unsigned int clock)
+{
+        u64 temp;
+        u32 shift;
+
+        /* Find a shift value */
+        for (shift = 32; shift > 0; shift--) {
+                temp = (u64) NSEC_PER_SEC << shift;
+                do_div(temp, clock);
+                if ((temp >> 32) == 0)
+                        break;
+        }
+        cs->shift = shift;
+        cs->mult = (u32) temp;
+}
+
+void __init clockevent_set_clock(struct clock_event_device *cd,
+        unsigned int clock)
+{
+        u64 temp;
+        u32 shift;
+
+        /* Find a shift value */
+        for (shift = 32; shift > 0; shift--) {
+                temp = (u64) clock << shift;
+                do_div(temp, NSEC_PER_SEC);
+                if ((temp >> 32) == 0)
+                        break;
+        }
+        cd->shift = shift;
+        cd->mult = (u32) temp;
+}
+
+static cycle_t clocksource_read_cycles(struct clocksource *cs)
+{
+        return (cycle_t) readw(gpt_base + COUNT(CLKSRC));
+}
+
+static struct clocksource clksrc = {
+        .name = "tmr1",
+        .rating = 200,          /* its a pretty decent clock */
+        .read = clocksource_read_cycles,
+        .mask = 0xFFFF,         /* 16 bits */
+        .mult = 0,              /* to be computed */
+        .shift = 0,             /* to be computed */
+        .flags = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+static void spear_clocksource_init(void)
+{
+        u32 tick_rate;
+        u16 val;
+
+        /* program the prescaler (/256)*/
+        writew(CTRL_PRESCALER256, gpt_base + CR(CLKSRC));
+
+        /* find out actual clock driving Timer */
+        tick_rate = clk_get_rate(gpt_clk);
+        tick_rate >>= CTRL_PRESCALER256;
+
+        writew(0xFFFF, gpt_base + LOAD(CLKSRC));
+
+        val = readw(gpt_base + CR(CLKSRC));
+        val &= ~CTRL_ONE_SHOT;  /* autoreload mode */
+        val |= CTRL_ENABLE ;
+        writew(val, gpt_base + CR(CLKSRC));
+
+        clocksource_set_clock(&clksrc, tick_rate);
+
+        /* register the clocksource */
+        clocksource_register(&clksrc);
+}
+
+static struct clock_event_device clkevt = {
+        .name = "tmr0",
+        .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
+        .set_mode = clockevent_set_mode,
+        .set_next_event = clockevent_next_event,
+        .shift = 0,     /* to be computed */
+};
+
+static void clockevent_set_mode(enum clock_event_mode mode,
+                                struct clock_event_device *clk_event_dev)
+{
+        u32 period;
+        u16 val;
+
+        /* stop the timer */
+        val = readw(gpt_base + CR(CLKEVT));
+        val &= ~CTRL_ENABLE;
+        writew(val, gpt_base + CR(CLKEVT));
+
+        switch (mode) {
+        case CLOCK_EVT_MODE_PERIODIC:
+                period = clk_get_rate(gpt_clk) / HZ;
+                period >>= CTRL_PRESCALER16;
+                writew(period, gpt_base + LOAD(CLKEVT));
+
+                val = readw(gpt_base + CR(CLKEVT));
+                val &= ~CTRL_ONE_SHOT;
+                val |= CTRL_ENABLE | CTRL_INT_ENABLE;
+                writew(val, gpt_base + CR(CLKEVT));
+
+                break;
+        case CLOCK_EVT_MODE_ONESHOT:
+                val = readw(gpt_base + CR(CLKEVT));
+                val |= CTRL_ONE_SHOT;
+                writew(val, gpt_base + CR(CLKEVT));
+
+                break;
+        case CLOCK_EVT_MODE_UNUSED:
+        case CLOCK_EVT_MODE_SHUTDOWN:
+        case CLOCK_EVT_MODE_RESUME:
+
+                break;
+        default:
+                pr_err("Invalid mode requested\n");
+                break;
+        }
+}
+
+static int clockevent_next_event(unsigned long cycles,
+                                 struct clock_event_device *clk_event_dev)
+{
+        u16 val;
+
+        writew(cycles, gpt_base + LOAD(CLKEVT));
+
+        val = readw(gpt_base + CR(CLKEVT));
+        val |= CTRL_ENABLE | CTRL_INT_ENABLE;
+        writew(val, gpt_base + CR(CLKEVT));
+
+        return 0;
+}
+
+static irqreturn_t spear_timer_interrupt(int irq, void *dev_id)
+{
+        struct clock_event_device *evt = &clkevt;
+
+        writew(INT_STATUS, gpt_base + IR(CLKEVT));
+
+        evt->event_handler(evt);
+
+        return IRQ_HANDLED;
+}
+
+static struct irqaction spear_timer_irq = {
+        .name = "timer",
+        .flags = IRQF_DISABLED | IRQF_TIMER,
+        .handler = spear_timer_interrupt
+};
+
+static void __init spear_clockevent_init(void)
+{
+        u32 tick_rate;
+
+        /* program the prescaler */
+        writew(CTRL_PRESCALER16, gpt_base + CR(CLKEVT));
+
+        tick_rate = clk_get_rate(gpt_clk);
+        tick_rate >>= CTRL_PRESCALER16;
+
+        clockevent_set_clock(&clkevt, tick_rate);
+
+        clkevt.max_delta_ns = clockevent_delta2ns(0xfff0,
+                        &clkevt);
+        clkevt.min_delta_ns = clockevent_delta2ns(3, &clkevt);
+
+        clkevt.cpumask = cpumask_of(0);
+
+        clockevents_register_device(&clkevt);
+
+        setup_irq(SPEAR_GPT0_CHAN0_IRQ, &spear_timer_irq);
+}
+
+void __init spear_setup_timer(void)
+{
+        struct clk *pll3_clk;
+
+        if (!request_mem_region(SPEAR_GPT0_BASE, SZ_1K, "gpt0")) {
+                pr_err("%s:cannot get IO addr\n", __func__);
+                return;
+        }
+
+        gpt_base = (void __iomem *)ioremap(SPEAR_GPT0_BASE, SZ_1K);
+        if (!gpt_base) {
+                pr_err("%s:ioremap failed for gpt\n", __func__);
+                goto err_mem;
+        }
+
+        gpt_clk = clk_get_sys("gpt0", NULL);
+        if (!gpt_clk) {
+                pr_err("%s:couldn't get clk for gpt\n", __func__);
+                goto err_iomap;
+        }
+
+        pll3_clk = clk_get(NULL, "pll3_48m_clk");
+        if (!pll3_clk) {
+                pr_err("%s:couldn't get PLL3 as parent for gpt\n", __func__);
+                goto err_iomap;
+        }
+
+        clk_set_parent(gpt_clk, pll3_clk);
+
+        spear_clockevent_init();
+        spear_clocksource_init();
+
+        return;
+
+err_iomap:
+        iounmap(gpt_base);
+
+err_mem:
+        release_mem_region(SPEAR_GPT0_BASE, SZ_1K);
+}
+
+struct sys_timer spear_sys_timer = {
+        .init = spear_setup_timer,
+};