3 files changed, 84 insertions, 6 deletions

diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index c91c21ac5fcb..711d5a4cce58 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -90,12 +90,6 @@ config S3C_GPIO_CFG_S3C64XX
           Internal configuration to enable S3C64XX style GPIO configuration
           functions.
 
-config S5P_GPIO_CFG_S5PC1XX
-        bool
-        help
-          Internal configuration to enable S5PC1XX style GPIO configuration
-          functions.
-
 config S3C_GPIO_PULL_UPDOWN
         bool
         help
@@ -111,6 +105,12 @@ config S3C_GPIO_PULL_UP
         help
           Internal configuration to enable the correct GPIO pull helper
 
+config S5P_GPIO_DRVSTR
+        bool
+        help
+          Internal configuration to get and set correct GPIO driver strength
+          helper
+
 config SAMSUNG_GPIO_EXTRA
         int "Number of additional GPIO pins"
         default 0
diff --git a/arch/arm/plat-samsung/gpio-config.c b/arch/arm/plat-samsung/gpio-config.c
index a76eef533392..57b68a50f45e 100644
--- a/arch/arm/plat-samsung/gpio-config.c
+++ b/arch/arm/plat-samsung/gpio-config.c
@@ -261,3 +261,51 @@ s3c_gpio_pull_t s3c_gpio_getpull_1up(struct s3c_gpio_chip *chip,
 }
 #endif /* CONFIG_S3C_GPIO_PULL_UP */
 
+#ifdef CONFIG_S5P_GPIO_DRVSTR
+s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin)
+{
+        struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
+        unsigned int off;
+        void __iomem *reg;
+        int shift;
+        u32 drvstr;
+
+        if (!chip)
+                return -EINVAL;
+
+        off = chip->chip.base - pin;
+        shift = off * 2;
+        reg = chip->base + 0x0C;
+
+        drvstr = __raw_readl(reg);
+        drvstr = 0xffff & (0x3 << shift);
+        drvstr = drvstr >> shift;
+
+        return (__force s5p_gpio_drvstr_t)drvstr;
+}
+EXPORT_SYMBOL(s5p_gpio_get_drvstr);
+
+int s5p_gpio_set_drvstr(unsigned int pin, s5p_gpio_drvstr_t drvstr)
+{
+        struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
+        unsigned int off;
+        void __iomem *reg;
+        int shift;
+        u32 tmp;
+
+        if (!chip)
+                return -EINVAL;
+
+        off = chip->chip.base - pin;
+        shift = off * 2;
+        reg = chip->base + 0x0C;
+
+        tmp = __raw_readl(reg);
+        tmp |= drvstr << shift;
+
+        __raw_writel(tmp, reg);
+
+        return 0;
+}
+EXPORT_SYMBOL(s5p_gpio_set_drvstr);
+#endif  /* CONFIG_S5P_GPIO_DRVSTR */
diff --git a/arch/arm/plat-samsung/include/plat/gpio-cfg.h b/arch/arm/plat-samsung/include/plat/gpio-cfg.h
index 8d01e853df39..34efdd2b032c 100644
--- a/arch/arm/plat-samsung/include/plat/gpio-cfg.h
+++ b/arch/arm/plat-samsung/include/plat/gpio-cfg.h
@@ -25,6 +25,7 @@
 #define __PLAT_GPIO_CFG_H __FILE__
 
 typedef unsigned int __bitwise__ s3c_gpio_pull_t;
+typedef unsigned int __bitwise__ s5p_gpio_drvstr_t;
 
 /* forward declaration if gpio-core.h hasn't been included */
 struct s3c_gpio_chip;
@@ -118,4 +119,33 @@ extern int s3c_gpio_setpull(unsigned int pin, s3c_gpio_pull_t pull);
 */
 extern s3c_gpio_pull_t s3c_gpio_getpull(unsigned int pin);
 
+/* Define values for the drvstr available for each gpio pin.
+ *
+ * These values control the value of the output signal driver strength,
+ * configurable on most pins on the S5C series.
+ */
+#define S5P_GPIO_DRVSTR_LV1     ((__force s5p_gpio_drvstr_t)0x00)
+#define S5P_GPIO_DRVSTR_LV2     ((__force s5p_gpio_drvstr_t)0x01)
+#define S5P_GPIO_DRVSTR_LV3     ((__force s5p_gpio_drvstr_t)0x10)
+#define S5P_GPIO_DRVSTR_LV4     ((__force s5p_gpio_drvstr_t)0x11)
+
+/**
+ * s5c_gpio_get_drvstr() - get the driver streght value of a gpio pin
+ * @pin: The pin number to get the settings for
+ *
+ * Read the driver streght value for the specified pin.
+*/
+extern s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin);
+
+/**
+ * s3c_gpio_set_drvstr() - set the driver streght value of a gpio pin
+ * @pin: The pin number to configure the driver streght value
+ * @drvstr: The new value of the driver strength
+ *
+ * This function sets the driver strength value for the specified pin.
+ * It will return 0 if successfull, or a negative error code if the pin
+ * cannot support the requested setting.
+*/
+extern int s5p_gpio_set_drvstr(unsigned int pin, s5p_gpio_drvstr_t drvstr);
+
 #endif /* __PLAT_GPIO_CFG_H */